diff --git a/axi4_to_ahb.fir b/axi4_to_ahb.fir index 65ef74e4..03f62457 100644 --- a/axi4_to_ahb.fir +++ b/axi4_to_ahb.fir @@ -545,14 +545,14 @@ circuit axi4_to_ahb : node _T_83 = bits(_T_58, 7, 7) @[axi4_to_ahb.scala 175:44] node _T_84 = geq(UInt<3>("h07"), _T_61) @[axi4_to_ahb.scala 175:62] node _T_85 = and(_T_83, _T_84) @[axi4_to_ahb.scala 175:48] - node _T_86 = mux(_T_85, UInt<3>("h07"), UInt<4>("h08")) @[Mux.scala 98:16] - node _T_87 = mux(_T_82, UInt<3>("h06"), _T_86) @[Mux.scala 98:16] - node _T_88 = mux(_T_79, UInt<3>("h05"), _T_87) @[Mux.scala 98:16] - node _T_89 = mux(_T_76, UInt<3>("h04"), _T_88) @[Mux.scala 98:16] - node _T_90 = mux(_T_73, UInt<2>("h03"), _T_89) @[Mux.scala 98:16] - node _T_91 = mux(_T_70, UInt<2>("h02"), _T_90) @[Mux.scala 98:16] - node _T_92 = mux(_T_67, UInt<1>("h01"), _T_91) @[Mux.scala 98:16] - node _T_93 = mux(_T_64, UInt<1>("h00"), _T_92) @[Mux.scala 98:16] + node _T_86 = mux(_T_64, UInt<1>("h00"), UInt<4>("h08")) @[Mux.scala 98:16] + node _T_87 = mux(_T_67, UInt<1>("h01"), _T_86) @[Mux.scala 98:16] + node _T_88 = mux(_T_70, UInt<2>("h02"), _T_87) @[Mux.scala 98:16] + node _T_89 = mux(_T_73, UInt<2>("h03"), _T_88) @[Mux.scala 98:16] + node _T_90 = mux(_T_76, UInt<3>("h04"), _T_89) @[Mux.scala 98:16] + node _T_91 = mux(_T_79, UInt<3>("h05"), _T_90) @[Mux.scala 98:16] + node _T_92 = mux(_T_82, UInt<3>("h06"), _T_91) @[Mux.scala 98:16] + node _T_93 = mux(_T_85, UInt<3>("h07"), _T_92) @[Mux.scala 98:16] node _T_94 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 233:124] node _T_95 = mux(_T_57, _T_93, _T_94) @[axi4_to_ahb.scala 233:30] buf_cmd_byte_ptr <= _T_95 @[axi4_to_ahb.scala 233:24] @@ -620,7 +620,7 @@ circuit axi4_to_ahb : node _T_139 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 252:82] node _T_140 = eq(_T_139, UInt<1>("h01")) @[axi4_to_ahb.scala 252:89] node _T_141 = and(master_valid, _T_140) @[axi4_to_ahb.scala 252:70] - node _T_142 = eq(_T_141, UInt<1>("h00")) @[axi4_to_ahb.scala 252:55] + node _T_142 = not(_T_141) @[axi4_to_ahb.scala 252:55] node _T_143 = and(_T_138, _T_142) @[axi4_to_ahb.scala 252:53] master_ready <= _T_143 @[axi4_to_ahb.scala 252:20] node _T_144 = and(master_valid, master_ready) @[axi4_to_ahb.scala 253:34] @@ -740,14 +740,14 @@ circuit axi4_to_ahb : node _T_220 = bits(_T_195, 7, 7) @[axi4_to_ahb.scala 175:44] node _T_221 = geq(UInt<3>("h07"), _T_198) @[axi4_to_ahb.scala 175:62] node _T_222 = and(_T_220, _T_221) @[axi4_to_ahb.scala 175:48] - node _T_223 = mux(_T_222, UInt<3>("h07"), UInt<4>("h08")) @[Mux.scala 98:16] - node _T_224 = mux(_T_219, UInt<3>("h06"), _T_223) @[Mux.scala 98:16] - node _T_225 = mux(_T_216, UInt<3>("h05"), _T_224) @[Mux.scala 98:16] - node _T_226 = mux(_T_213, UInt<3>("h04"), _T_225) @[Mux.scala 98:16] - node _T_227 = mux(_T_210, UInt<2>("h03"), _T_226) @[Mux.scala 98:16] - node _T_228 = mux(_T_207, UInt<2>("h02"), _T_227) @[Mux.scala 98:16] - node _T_229 = mux(_T_204, UInt<1>("h01"), _T_228) @[Mux.scala 98:16] - node _T_230 = mux(_T_201, UInt<1>("h00"), _T_229) @[Mux.scala 98:16] + node _T_223 = mux(_T_201, UInt<1>("h00"), UInt<4>("h08")) @[Mux.scala 98:16] + node _T_224 = mux(_T_204, UInt<1>("h01"), _T_223) @[Mux.scala 98:16] + node _T_225 = mux(_T_207, UInt<2>("h02"), _T_224) @[Mux.scala 98:16] + node _T_226 = mux(_T_210, UInt<2>("h03"), _T_225) @[Mux.scala 98:16] + node _T_227 = mux(_T_213, UInt<3>("h04"), _T_226) @[Mux.scala 98:16] + node _T_228 = mux(_T_216, UInt<3>("h05"), _T_227) @[Mux.scala 98:16] + node _T_229 = mux(_T_219, UInt<3>("h06"), _T_228) @[Mux.scala 98:16] + node _T_230 = mux(_T_222, UInt<3>("h07"), _T_229) @[Mux.scala 98:16] node _T_231 = mux(_T_193, _T_230, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 291:30] buf_cmd_byte_ptr <= _T_231 @[axi4_to_ahb.scala 291:24] node _T_232 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 292:65] @@ -781,14 +781,14 @@ circuit axi4_to_ahb : node _T_260 = bits(_T_235, 7, 7) @[axi4_to_ahb.scala 175:44] node _T_261 = geq(UInt<3>("h07"), _T_238) @[axi4_to_ahb.scala 175:62] node _T_262 = and(_T_260, _T_261) @[axi4_to_ahb.scala 175:48] - node _T_263 = mux(_T_262, UInt<3>("h07"), UInt<4>("h08")) @[Mux.scala 98:16] - node _T_264 = mux(_T_259, UInt<3>("h06"), _T_263) @[Mux.scala 98:16] - node _T_265 = mux(_T_256, UInt<3>("h05"), _T_264) @[Mux.scala 98:16] - node _T_266 = mux(_T_253, UInt<3>("h04"), _T_265) @[Mux.scala 98:16] - node _T_267 = mux(_T_250, UInt<2>("h03"), _T_266) @[Mux.scala 98:16] - node _T_268 = mux(_T_247, UInt<2>("h02"), _T_267) @[Mux.scala 98:16] - node _T_269 = mux(_T_244, UInt<1>("h01"), _T_268) @[Mux.scala 98:16] - node _T_270 = mux(_T_241, UInt<1>("h00"), _T_269) @[Mux.scala 98:16] + node _T_263 = mux(_T_241, UInt<1>("h00"), UInt<4>("h08")) @[Mux.scala 98:16] + node _T_264 = mux(_T_244, UInt<1>("h01"), _T_263) @[Mux.scala 98:16] + node _T_265 = mux(_T_247, UInt<2>("h02"), _T_264) @[Mux.scala 98:16] + node _T_266 = mux(_T_250, UInt<2>("h03"), _T_265) @[Mux.scala 98:16] + node _T_267 = mux(_T_253, UInt<3>("h04"), _T_266) @[Mux.scala 98:16] + node _T_268 = mux(_T_256, UInt<3>("h05"), _T_267) @[Mux.scala 98:16] + node _T_269 = mux(_T_259, UInt<3>("h06"), _T_268) @[Mux.scala 98:16] + node _T_270 = mux(_T_262, UInt<3>("h07"), _T_269) @[Mux.scala 98:16] node _T_271 = dshr(buf_byteen, _T_270) @[axi4_to_ahb.scala 292:92] node _T_272 = bits(_T_271, 0, 0) @[axi4_to_ahb.scala 292:92] node _T_273 = eq(_T_272, UInt<1>("h00")) @[axi4_to_ahb.scala 292:163] @@ -808,617 +808,614 @@ circuit axi4_to_ahb : node _T_282 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 297:34] node _T_283 = or(_T_282, ahb_hresp_q) @[axi4_to_ahb.scala 297:50] buf_state_en <= _T_283 @[axi4_to_ahb.scala 297:20] - node _T_284 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 298:35] - node _T_285 = or(_T_284, ahb_hresp_q) @[axi4_to_ahb.scala 298:51] - node _T_286 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 298:68] - node _T_287 = and(_T_285, _T_286) @[axi4_to_ahb.scala 298:66] - node _T_288 = and(_T_287, slave_ready) @[axi4_to_ahb.scala 298:81] - master_ready <= _T_288 @[axi4_to_ahb.scala 298:20] - node _T_289 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 299:42] - node _T_290 = or(ahb_hresp_q, _T_289) @[axi4_to_ahb.scala 299:40] - node _T_291 = bits(_T_290, 0, 0) @[axi4_to_ahb.scala 299:62] - node _T_292 = and(master_valid, master_ready) @[axi4_to_ahb.scala 299:90] - node _T_293 = bits(_T_292, 0, 0) @[axi4_to_ahb.scala 299:112] - node _T_294 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 299:131] - node _T_295 = eq(_T_294, UInt<2>("h01")) @[axi4_to_ahb.scala 299:138] - node _T_296 = mux(_T_295, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 299:119] - node _T_297 = mux(_T_293, _T_296, UInt<3>("h00")) @[axi4_to_ahb.scala 299:75] - node _T_298 = mux(_T_291, UInt<3>("h05"), _T_297) @[axi4_to_ahb.scala 299:26] - buf_nxtstate <= _T_298 @[axi4_to_ahb.scala 299:20] + node _T_284 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 298:38] + node _T_285 = and(buf_state_en, _T_284) @[axi4_to_ahb.scala 298:36] + node _T_286 = and(_T_285, slave_ready) @[axi4_to_ahb.scala 298:51] + master_ready <= _T_286 @[axi4_to_ahb.scala 298:20] + node _T_287 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 299:42] + node _T_288 = or(ahb_hresp_q, _T_287) @[axi4_to_ahb.scala 299:40] + node _T_289 = and(master_valid, master_valid) @[axi4_to_ahb.scala 299:80] + node _T_290 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 299:111] + node _T_291 = eq(_T_290, UInt<1>("h01")) @[axi4_to_ahb.scala 299:117] + node _T_292 = bits(_T_291, 0, 0) @[axi4_to_ahb.scala 299:132] + node _T_293 = mux(_T_292, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 299:99] + node _T_294 = mux(_T_289, _T_293, UInt<3>("h00")) @[axi4_to_ahb.scala 299:65] + node _T_295 = mux(_T_288, UInt<3>("h05"), _T_294) @[axi4_to_ahb.scala 299:26] + buf_nxtstate <= _T_295 @[axi4_to_ahb.scala 299:20] slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 300:23] slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 301:23] - node _T_299 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 302:34] - node _T_300 = eq(_T_299, UInt<1>("h01")) @[axi4_to_ahb.scala 302:41] - buf_write_in <= _T_300 @[axi4_to_ahb.scala 302:20] - node _T_301 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 303:50] - node _T_302 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 303:78] - node _T_303 = or(_T_301, _T_302) @[axi4_to_ahb.scala 303:62] - node _T_304 = and(buf_state_en, _T_303) @[axi4_to_ahb.scala 303:33] - buf_wr_en <= _T_304 @[axi4_to_ahb.scala 303:17] + node _T_296 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 302:33] + node _T_297 = eq(_T_296, UInt<1>("h01")) @[axi4_to_ahb.scala 302:39] + buf_write_in <= _T_297 @[axi4_to_ahb.scala 302:20] + node _T_298 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 303:50] + node _T_299 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 303:78] + node _T_300 = or(_T_298, _T_299) @[axi4_to_ahb.scala 303:62] + node _T_301 = and(buf_state_en, _T_300) @[axi4_to_ahb.scala 303:33] + buf_wr_en <= _T_301 @[axi4_to_ahb.scala 303:17] buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 304:22] - node _T_305 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 305:63] - node _T_306 = neq(_T_305, UInt<2>("h00")) @[axi4_to_ahb.scala 305:70] - node _T_307 = and(ahb_hready_q, _T_306) @[axi4_to_ahb.scala 305:48] - node _T_308 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 305:109] - node _T_309 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 305:170] - node _T_310 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 305:188] - node _T_311 = add(_T_309, UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] - node _T_312 = tail(_T_311, 1) @[axi4_to_ahb.scala 174:52] - node _T_313 = mux(UInt<1>("h01"), _T_312, _T_309) @[axi4_to_ahb.scala 174:24] - node _T_314 = bits(_T_310, 0, 0) @[axi4_to_ahb.scala 175:44] - node _T_315 = geq(UInt<1>("h00"), _T_313) @[axi4_to_ahb.scala 175:62] + node _T_302 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 305:65] + node _T_303 = neq(_T_302, UInt<1>("h00")) @[axi4_to_ahb.scala 305:71] + node _T_304 = and(ahb_hready_q, _T_303) @[axi4_to_ahb.scala 305:50] + node _T_305 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 306:29] + node _T_306 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 306:85] + node _T_307 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 306:101] + node _T_308 = add(_T_306, UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] + node _T_309 = tail(_T_308, 1) @[axi4_to_ahb.scala 174:52] + node _T_310 = mux(UInt<1>("h01"), _T_309, _T_306) @[axi4_to_ahb.scala 174:24] + node _T_311 = bits(_T_307, 0, 0) @[axi4_to_ahb.scala 175:44] + node _T_312 = geq(UInt<1>("h00"), _T_310) @[axi4_to_ahb.scala 175:62] + node _T_313 = and(_T_311, _T_312) @[axi4_to_ahb.scala 175:48] + node _T_314 = bits(_T_307, 1, 1) @[axi4_to_ahb.scala 175:44] + node _T_315 = geq(UInt<1>("h01"), _T_310) @[axi4_to_ahb.scala 175:62] node _T_316 = and(_T_314, _T_315) @[axi4_to_ahb.scala 175:48] - node _T_317 = bits(_T_310, 1, 1) @[axi4_to_ahb.scala 175:44] - node _T_318 = geq(UInt<1>("h01"), _T_313) @[axi4_to_ahb.scala 175:62] + node _T_317 = bits(_T_307, 2, 2) @[axi4_to_ahb.scala 175:44] + node _T_318 = geq(UInt<2>("h02"), _T_310) @[axi4_to_ahb.scala 175:62] node _T_319 = and(_T_317, _T_318) @[axi4_to_ahb.scala 175:48] - node _T_320 = bits(_T_310, 2, 2) @[axi4_to_ahb.scala 175:44] - node _T_321 = geq(UInt<2>("h02"), _T_313) @[axi4_to_ahb.scala 175:62] + node _T_320 = bits(_T_307, 3, 3) @[axi4_to_ahb.scala 175:44] + node _T_321 = geq(UInt<2>("h03"), _T_310) @[axi4_to_ahb.scala 175:62] node _T_322 = and(_T_320, _T_321) @[axi4_to_ahb.scala 175:48] - node _T_323 = bits(_T_310, 3, 3) @[axi4_to_ahb.scala 175:44] - node _T_324 = geq(UInt<2>("h03"), _T_313) @[axi4_to_ahb.scala 175:62] + node _T_323 = bits(_T_307, 4, 4) @[axi4_to_ahb.scala 175:44] + node _T_324 = geq(UInt<3>("h04"), _T_310) @[axi4_to_ahb.scala 175:62] node _T_325 = and(_T_323, _T_324) @[axi4_to_ahb.scala 175:48] - node _T_326 = bits(_T_310, 4, 4) @[axi4_to_ahb.scala 175:44] - node _T_327 = geq(UInt<3>("h04"), _T_313) @[axi4_to_ahb.scala 175:62] + node _T_326 = bits(_T_307, 5, 5) @[axi4_to_ahb.scala 175:44] + node _T_327 = geq(UInt<3>("h05"), _T_310) @[axi4_to_ahb.scala 175:62] node _T_328 = and(_T_326, _T_327) @[axi4_to_ahb.scala 175:48] - node _T_329 = bits(_T_310, 5, 5) @[axi4_to_ahb.scala 175:44] - node _T_330 = geq(UInt<3>("h05"), _T_313) @[axi4_to_ahb.scala 175:62] + node _T_329 = bits(_T_307, 6, 6) @[axi4_to_ahb.scala 175:44] + node _T_330 = geq(UInt<3>("h06"), _T_310) @[axi4_to_ahb.scala 175:62] node _T_331 = and(_T_329, _T_330) @[axi4_to_ahb.scala 175:48] - node _T_332 = bits(_T_310, 6, 6) @[axi4_to_ahb.scala 175:44] - node _T_333 = geq(UInt<3>("h06"), _T_313) @[axi4_to_ahb.scala 175:62] + node _T_332 = bits(_T_307, 7, 7) @[axi4_to_ahb.scala 175:44] + node _T_333 = geq(UInt<3>("h07"), _T_310) @[axi4_to_ahb.scala 175:62] node _T_334 = and(_T_332, _T_333) @[axi4_to_ahb.scala 175:48] - node _T_335 = bits(_T_310, 7, 7) @[axi4_to_ahb.scala 175:44] - node _T_336 = geq(UInt<3>("h07"), _T_313) @[axi4_to_ahb.scala 175:62] - node _T_337 = and(_T_335, _T_336) @[axi4_to_ahb.scala 175:48] - node _T_338 = mux(_T_337, UInt<3>("h07"), UInt<4>("h08")) @[Mux.scala 98:16] - node _T_339 = mux(_T_334, UInt<3>("h06"), _T_338) @[Mux.scala 98:16] - node _T_340 = mux(_T_331, UInt<3>("h05"), _T_339) @[Mux.scala 98:16] - node _T_341 = mux(_T_328, UInt<3>("h04"), _T_340) @[Mux.scala 98:16] - node _T_342 = mux(_T_325, UInt<2>("h03"), _T_341) @[Mux.scala 98:16] - node _T_343 = mux(_T_322, UInt<2>("h02"), _T_342) @[Mux.scala 98:16] - node _T_344 = mux(_T_319, UInt<1>("h01"), _T_343) @[Mux.scala 98:16] - node _T_345 = mux(_T_316, UInt<1>("h00"), _T_344) @[Mux.scala 98:16] - node _T_346 = dshr(buf_byteen, _T_345) @[axi4_to_ahb.scala 305:136] - node _T_347 = bits(_T_346, 0, 0) @[axi4_to_ahb.scala 305:136] - node _T_348 = eq(_T_347, UInt<1>("h00")) @[axi4_to_ahb.scala 305:205] - node _T_349 = or(_T_308, _T_348) @[axi4_to_ahb.scala 305:123] - node _T_350 = and(_T_307, _T_349) @[axi4_to_ahb.scala 305:87] - node _T_351 = or(ahb_hresp_q, _T_350) @[axi4_to_ahb.scala 305:32] - cmd_done <= _T_351 @[axi4_to_ahb.scala 305:16] - node _T_352 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 306:33] - node _T_353 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 306:64] - node _T_354 = and(_T_352, _T_353) @[axi4_to_ahb.scala 306:48] - bypass_en <= _T_354 @[axi4_to_ahb.scala 306:17] - node _T_355 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 307:44] - node _T_356 = eq(_T_355, UInt<1>("h00")) @[axi4_to_ahb.scala 307:33] - node _T_357 = or(_T_356, bypass_en) @[axi4_to_ahb.scala 307:57] - node _T_358 = bits(_T_357, 0, 0) @[Bitwise.scala 72:15] - node _T_359 = mux(_T_358, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_360 = and(_T_359, UInt<2>("h02")) @[axi4_to_ahb.scala 307:71] - io.ahb_htrans <= _T_360 @[axi4_to_ahb.scala 307:21] - node _T_361 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 308:55] - node _T_362 = and(buf_state_en, _T_361) @[axi4_to_ahb.scala 308:39] - slave_valid_pre <= _T_362 @[axi4_to_ahb.scala 308:23] - node _T_363 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 309:33] - node _T_364 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 309:63] - node _T_365 = neq(_T_364, UInt<2>("h00")) @[axi4_to_ahb.scala 309:70] - node _T_366 = and(_T_363, _T_365) @[axi4_to_ahb.scala 309:48] - trxn_done <= _T_366 @[axi4_to_ahb.scala 309:17] - node _T_367 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 310:40] - buf_cmd_byte_ptr_en <= _T_367 @[axi4_to_ahb.scala 310:27] - node _T_368 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 311:81] - node _T_369 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] - node _T_370 = tail(_T_369, 1) @[axi4_to_ahb.scala 174:52] - node _T_371 = mux(UInt<1>("h00"), _T_370, UInt<3>("h00")) @[axi4_to_ahb.scala 174:24] - node _T_372 = bits(_T_368, 0, 0) @[axi4_to_ahb.scala 175:44] - node _T_373 = geq(UInt<1>("h00"), _T_371) @[axi4_to_ahb.scala 175:62] + node _T_335 = mux(_T_313, UInt<1>("h00"), UInt<4>("h08")) @[Mux.scala 98:16] + node _T_336 = mux(_T_316, UInt<1>("h01"), _T_335) @[Mux.scala 98:16] + node _T_337 = mux(_T_319, UInt<2>("h02"), _T_336) @[Mux.scala 98:16] + node _T_338 = mux(_T_322, UInt<2>("h03"), _T_337) @[Mux.scala 98:16] + node _T_339 = mux(_T_325, UInt<3>("h04"), _T_338) @[Mux.scala 98:16] + node _T_340 = mux(_T_328, UInt<3>("h05"), _T_339) @[Mux.scala 98:16] + node _T_341 = mux(_T_331, UInt<3>("h06"), _T_340) @[Mux.scala 98:16] + node _T_342 = mux(_T_334, UInt<3>("h07"), _T_341) @[Mux.scala 98:16] + node _T_343 = dshr(buf_byteen, _T_342) @[axi4_to_ahb.scala 306:51] + node _T_344 = bits(_T_343, 0, 0) @[axi4_to_ahb.scala 306:51] + node _T_345 = eq(_T_344, UInt<1>("h00")) @[axi4_to_ahb.scala 306:116] + node _T_346 = or(_T_305, _T_345) @[axi4_to_ahb.scala 306:38] + node _T_347 = and(_T_304, _T_346) @[axi4_to_ahb.scala 305:80] + node _T_348 = or(ahb_hresp_q, _T_347) @[axi4_to_ahb.scala 305:34] + cmd_done <= _T_348 @[axi4_to_ahb.scala 305:16] + node _T_349 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 307:33] + node _T_350 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 307:64] + node _T_351 = and(_T_349, _T_350) @[axi4_to_ahb.scala 307:48] + bypass_en <= _T_351 @[axi4_to_ahb.scala 307:17] + node _T_352 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 308:44] + node _T_353 = eq(_T_352, UInt<1>("h00")) @[axi4_to_ahb.scala 308:33] + node _T_354 = or(_T_353, bypass_en) @[axi4_to_ahb.scala 308:57] + node _T_355 = bits(_T_354, 0, 0) @[Bitwise.scala 72:15] + node _T_356 = mux(_T_355, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_357 = and(_T_356, UInt<2>("h02")) @[axi4_to_ahb.scala 308:71] + io.ahb_htrans <= _T_357 @[axi4_to_ahb.scala 308:21] + node _T_358 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 309:55] + node _T_359 = and(buf_state_en, _T_358) @[axi4_to_ahb.scala 309:39] + slave_valid_pre <= _T_359 @[axi4_to_ahb.scala 309:23] + node _T_360 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 310:33] + node _T_361 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 310:63] + node _T_362 = neq(_T_361, UInt<1>("h00")) @[axi4_to_ahb.scala 310:69] + node _T_363 = and(_T_360, _T_362) @[axi4_to_ahb.scala 310:48] + trxn_done <= _T_363 @[axi4_to_ahb.scala 310:17] + node _T_364 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 311:40] + buf_cmd_byte_ptr_en <= _T_364 @[axi4_to_ahb.scala 311:27] + node _T_365 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 312:79] + node _T_366 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] + node _T_367 = tail(_T_366, 1) @[axi4_to_ahb.scala 174:52] + node _T_368 = mux(UInt<1>("h00"), _T_367, UInt<3>("h00")) @[axi4_to_ahb.scala 174:24] + node _T_369 = bits(_T_365, 0, 0) @[axi4_to_ahb.scala 175:44] + node _T_370 = geq(UInt<1>("h00"), _T_368) @[axi4_to_ahb.scala 175:62] + node _T_371 = and(_T_369, _T_370) @[axi4_to_ahb.scala 175:48] + node _T_372 = bits(_T_365, 1, 1) @[axi4_to_ahb.scala 175:44] + node _T_373 = geq(UInt<1>("h01"), _T_368) @[axi4_to_ahb.scala 175:62] node _T_374 = and(_T_372, _T_373) @[axi4_to_ahb.scala 175:48] - node _T_375 = bits(_T_368, 1, 1) @[axi4_to_ahb.scala 175:44] - node _T_376 = geq(UInt<1>("h01"), _T_371) @[axi4_to_ahb.scala 175:62] + node _T_375 = bits(_T_365, 2, 2) @[axi4_to_ahb.scala 175:44] + node _T_376 = geq(UInt<2>("h02"), _T_368) @[axi4_to_ahb.scala 175:62] node _T_377 = and(_T_375, _T_376) @[axi4_to_ahb.scala 175:48] - node _T_378 = bits(_T_368, 2, 2) @[axi4_to_ahb.scala 175:44] - node _T_379 = geq(UInt<2>("h02"), _T_371) @[axi4_to_ahb.scala 175:62] + node _T_378 = bits(_T_365, 3, 3) @[axi4_to_ahb.scala 175:44] + node _T_379 = geq(UInt<2>("h03"), _T_368) @[axi4_to_ahb.scala 175:62] node _T_380 = and(_T_378, _T_379) @[axi4_to_ahb.scala 175:48] - node _T_381 = bits(_T_368, 3, 3) @[axi4_to_ahb.scala 175:44] - node _T_382 = geq(UInt<2>("h03"), _T_371) @[axi4_to_ahb.scala 175:62] + node _T_381 = bits(_T_365, 4, 4) @[axi4_to_ahb.scala 175:44] + node _T_382 = geq(UInt<3>("h04"), _T_368) @[axi4_to_ahb.scala 175:62] node _T_383 = and(_T_381, _T_382) @[axi4_to_ahb.scala 175:48] - node _T_384 = bits(_T_368, 4, 4) @[axi4_to_ahb.scala 175:44] - node _T_385 = geq(UInt<3>("h04"), _T_371) @[axi4_to_ahb.scala 175:62] + node _T_384 = bits(_T_365, 5, 5) @[axi4_to_ahb.scala 175:44] + node _T_385 = geq(UInt<3>("h05"), _T_368) @[axi4_to_ahb.scala 175:62] node _T_386 = and(_T_384, _T_385) @[axi4_to_ahb.scala 175:48] - node _T_387 = bits(_T_368, 5, 5) @[axi4_to_ahb.scala 175:44] - node _T_388 = geq(UInt<3>("h05"), _T_371) @[axi4_to_ahb.scala 175:62] + node _T_387 = bits(_T_365, 6, 6) @[axi4_to_ahb.scala 175:44] + node _T_388 = geq(UInt<3>("h06"), _T_368) @[axi4_to_ahb.scala 175:62] node _T_389 = and(_T_387, _T_388) @[axi4_to_ahb.scala 175:48] - node _T_390 = bits(_T_368, 6, 6) @[axi4_to_ahb.scala 175:44] - node _T_391 = geq(UInt<3>("h06"), _T_371) @[axi4_to_ahb.scala 175:62] + node _T_390 = bits(_T_365, 7, 7) @[axi4_to_ahb.scala 175:44] + node _T_391 = geq(UInt<3>("h07"), _T_368) @[axi4_to_ahb.scala 175:62] node _T_392 = and(_T_390, _T_391) @[axi4_to_ahb.scala 175:48] - node _T_393 = bits(_T_368, 7, 7) @[axi4_to_ahb.scala 175:44] - node _T_394 = geq(UInt<3>("h07"), _T_371) @[axi4_to_ahb.scala 175:62] - node _T_395 = and(_T_393, _T_394) @[axi4_to_ahb.scala 175:48] - node _T_396 = mux(_T_395, UInt<3>("h07"), UInt<4>("h08")) @[Mux.scala 98:16] - node _T_397 = mux(_T_392, UInt<3>("h06"), _T_396) @[Mux.scala 98:16] - node _T_398 = mux(_T_389, UInt<3>("h05"), _T_397) @[Mux.scala 98:16] - node _T_399 = mux(_T_386, UInt<3>("h04"), _T_398) @[Mux.scala 98:16] - node _T_400 = mux(_T_383, UInt<2>("h03"), _T_399) @[Mux.scala 98:16] - node _T_401 = mux(_T_380, UInt<2>("h02"), _T_400) @[Mux.scala 98:16] - node _T_402 = mux(_T_377, UInt<1>("h01"), _T_401) @[Mux.scala 98:16] - node _T_403 = mux(_T_374, UInt<1>("h00"), _T_402) @[Mux.scala 98:16] - node _T_404 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 311:147] - node _T_405 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 311:165] - node _T_406 = add(_T_404, UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] - node _T_407 = tail(_T_406, 1) @[axi4_to_ahb.scala 174:52] - node _T_408 = mux(UInt<1>("h01"), _T_407, _T_404) @[axi4_to_ahb.scala 174:24] - node _T_409 = bits(_T_405, 0, 0) @[axi4_to_ahb.scala 175:44] - node _T_410 = geq(UInt<1>("h00"), _T_408) @[axi4_to_ahb.scala 175:62] + node _T_393 = mux(_T_371, UInt<1>("h00"), UInt<4>("h08")) @[Mux.scala 98:16] + node _T_394 = mux(_T_374, UInt<1>("h01"), _T_393) @[Mux.scala 98:16] + node _T_395 = mux(_T_377, UInt<2>("h02"), _T_394) @[Mux.scala 98:16] + node _T_396 = mux(_T_380, UInt<2>("h03"), _T_395) @[Mux.scala 98:16] + node _T_397 = mux(_T_383, UInt<3>("h04"), _T_396) @[Mux.scala 98:16] + node _T_398 = mux(_T_386, UInt<3>("h05"), _T_397) @[Mux.scala 98:16] + node _T_399 = mux(_T_389, UInt<3>("h06"), _T_398) @[Mux.scala 98:16] + node _T_400 = mux(_T_392, UInt<3>("h07"), _T_399) @[Mux.scala 98:16] + node _T_401 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 312:141] + node _T_402 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 312:157] + node _T_403 = add(_T_401, UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] + node _T_404 = tail(_T_403, 1) @[axi4_to_ahb.scala 174:52] + node _T_405 = mux(UInt<1>("h01"), _T_404, _T_401) @[axi4_to_ahb.scala 174:24] + node _T_406 = bits(_T_402, 0, 0) @[axi4_to_ahb.scala 175:44] + node _T_407 = geq(UInt<1>("h00"), _T_405) @[axi4_to_ahb.scala 175:62] + node _T_408 = and(_T_406, _T_407) @[axi4_to_ahb.scala 175:48] + node _T_409 = bits(_T_402, 1, 1) @[axi4_to_ahb.scala 175:44] + node _T_410 = geq(UInt<1>("h01"), _T_405) @[axi4_to_ahb.scala 175:62] node _T_411 = and(_T_409, _T_410) @[axi4_to_ahb.scala 175:48] - node _T_412 = bits(_T_405, 1, 1) @[axi4_to_ahb.scala 175:44] - node _T_413 = geq(UInt<1>("h01"), _T_408) @[axi4_to_ahb.scala 175:62] + node _T_412 = bits(_T_402, 2, 2) @[axi4_to_ahb.scala 175:44] + node _T_413 = geq(UInt<2>("h02"), _T_405) @[axi4_to_ahb.scala 175:62] node _T_414 = and(_T_412, _T_413) @[axi4_to_ahb.scala 175:48] - node _T_415 = bits(_T_405, 2, 2) @[axi4_to_ahb.scala 175:44] - node _T_416 = geq(UInt<2>("h02"), _T_408) @[axi4_to_ahb.scala 175:62] + node _T_415 = bits(_T_402, 3, 3) @[axi4_to_ahb.scala 175:44] + node _T_416 = geq(UInt<2>("h03"), _T_405) @[axi4_to_ahb.scala 175:62] node _T_417 = and(_T_415, _T_416) @[axi4_to_ahb.scala 175:48] - node _T_418 = bits(_T_405, 3, 3) @[axi4_to_ahb.scala 175:44] - node _T_419 = geq(UInt<2>("h03"), _T_408) @[axi4_to_ahb.scala 175:62] + node _T_418 = bits(_T_402, 4, 4) @[axi4_to_ahb.scala 175:44] + node _T_419 = geq(UInt<3>("h04"), _T_405) @[axi4_to_ahb.scala 175:62] node _T_420 = and(_T_418, _T_419) @[axi4_to_ahb.scala 175:48] - node _T_421 = bits(_T_405, 4, 4) @[axi4_to_ahb.scala 175:44] - node _T_422 = geq(UInt<3>("h04"), _T_408) @[axi4_to_ahb.scala 175:62] + node _T_421 = bits(_T_402, 5, 5) @[axi4_to_ahb.scala 175:44] + node _T_422 = geq(UInt<3>("h05"), _T_405) @[axi4_to_ahb.scala 175:62] node _T_423 = and(_T_421, _T_422) @[axi4_to_ahb.scala 175:48] - node _T_424 = bits(_T_405, 5, 5) @[axi4_to_ahb.scala 175:44] - node _T_425 = geq(UInt<3>("h05"), _T_408) @[axi4_to_ahb.scala 175:62] + node _T_424 = bits(_T_402, 6, 6) @[axi4_to_ahb.scala 175:44] + node _T_425 = geq(UInt<3>("h06"), _T_405) @[axi4_to_ahb.scala 175:62] node _T_426 = and(_T_424, _T_425) @[axi4_to_ahb.scala 175:48] - node _T_427 = bits(_T_405, 6, 6) @[axi4_to_ahb.scala 175:44] - node _T_428 = geq(UInt<3>("h06"), _T_408) @[axi4_to_ahb.scala 175:62] + node _T_427 = bits(_T_402, 7, 7) @[axi4_to_ahb.scala 175:44] + node _T_428 = geq(UInt<3>("h07"), _T_405) @[axi4_to_ahb.scala 175:62] node _T_429 = and(_T_427, _T_428) @[axi4_to_ahb.scala 175:48] - node _T_430 = bits(_T_405, 7, 7) @[axi4_to_ahb.scala 175:44] - node _T_431 = geq(UInt<3>("h07"), _T_408) @[axi4_to_ahb.scala 175:62] - node _T_432 = and(_T_430, _T_431) @[axi4_to_ahb.scala 175:48] - node _T_433 = mux(_T_432, UInt<3>("h07"), UInt<4>("h08")) @[Mux.scala 98:16] - node _T_434 = mux(_T_429, UInt<3>("h06"), _T_433) @[Mux.scala 98:16] - node _T_435 = mux(_T_426, UInt<3>("h05"), _T_434) @[Mux.scala 98:16] - node _T_436 = mux(_T_423, UInt<3>("h04"), _T_435) @[Mux.scala 98:16] - node _T_437 = mux(_T_420, UInt<2>("h03"), _T_436) @[Mux.scala 98:16] - node _T_438 = mux(_T_417, UInt<2>("h02"), _T_437) @[Mux.scala 98:16] - node _T_439 = mux(_T_414, UInt<1>("h01"), _T_438) @[Mux.scala 98:16] - node _T_440 = mux(_T_411, UInt<1>("h00"), _T_439) @[Mux.scala 98:16] - node _T_441 = mux(trxn_done, _T_440, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 311:102] - node _T_442 = mux(bypass_en, _T_403, _T_441) @[axi4_to_ahb.scala 311:30] - buf_cmd_byte_ptr <= _T_442 @[axi4_to_ahb.scala 311:24] + node _T_430 = mux(_T_408, UInt<1>("h00"), UInt<4>("h08")) @[Mux.scala 98:16] + node _T_431 = mux(_T_411, UInt<1>("h01"), _T_430) @[Mux.scala 98:16] + node _T_432 = mux(_T_414, UInt<2>("h02"), _T_431) @[Mux.scala 98:16] + node _T_433 = mux(_T_417, UInt<2>("h03"), _T_432) @[Mux.scala 98:16] + node _T_434 = mux(_T_420, UInt<3>("h04"), _T_433) @[Mux.scala 98:16] + node _T_435 = mux(_T_423, UInt<3>("h05"), _T_434) @[Mux.scala 98:16] + node _T_436 = mux(_T_426, UInt<3>("h06"), _T_435) @[Mux.scala 98:16] + node _T_437 = mux(_T_429, UInt<3>("h07"), _T_436) @[Mux.scala 98:16] + node _T_438 = mux(trxn_done, _T_437, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 312:97] + node _T_439 = mux(bypass_en, _T_400, _T_438) @[axi4_to_ahb.scala 312:30] + buf_cmd_byte_ptr <= _T_439 @[axi4_to_ahb.scala 312:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_443 = eq(UInt<3>("h05"), buf_state) @[Conditional.scala 37:30] - when _T_443 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 315:20] - buf_state_en <= slave_ready @[axi4_to_ahb.scala 316:20] - slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 317:23] - slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 318:23] + node _T_440 = eq(UInt<3>("h05"), buf_state) @[Conditional.scala 37:30] + when _T_440 : @[Conditional.scala 39:67] + buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 334:20] + buf_state_en <= slave_ready @[axi4_to_ahb.scala 335:20] + slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 336:23] + slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 337:23] skip @[Conditional.scala 39:67] - cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 322:16] - node _T_444 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 323:33] - node _T_445 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 323:73] - node _T_446 = eq(_T_445, UInt<1>("h01")) @[axi4_to_ahb.scala 323:80] - node _T_447 = and(buf_aligned_in, _T_446) @[axi4_to_ahb.scala 323:60] - node _T_448 = bits(_T_447, 0, 0) @[axi4_to_ahb.scala 323:100] - node _T_449 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 323:132] - node _T_450 = bits(_T_449, 7, 0) @[axi4_to_ahb.scala 166:50] - node _T_451 = eq(_T_450, UInt<8>("h0ff")) @[axi4_to_ahb.scala 166:57] - node _T_452 = bits(_T_449, 7, 0) @[axi4_to_ahb.scala 166:81] - node _T_453 = eq(_T_452, UInt<8>("h0f")) @[axi4_to_ahb.scala 166:88] - node _T_454 = or(_T_451, _T_453) @[axi4_to_ahb.scala 166:70] - node _T_455 = bits(_T_449, 7, 0) @[axi4_to_ahb.scala 166:117] - node _T_456 = eq(_T_455, UInt<8>("h03")) @[axi4_to_ahb.scala 166:124] - node _T_457 = or(_T_454, _T_456) @[axi4_to_ahb.scala 166:106] - node _T_458 = bits(_T_457, 0, 0) @[Bitwise.scala 72:15] - node _T_459 = mux(_T_458, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_460 = and(UInt<3>("h00"), _T_459) @[axi4_to_ahb.scala 166:29] - node _T_461 = bits(_T_449, 7, 0) @[axi4_to_ahb.scala 167:35] - node _T_462 = eq(_T_461, UInt<8>("h0c")) @[axi4_to_ahb.scala 167:42] - node _T_463 = bits(_T_462, 0, 0) @[Bitwise.scala 72:15] - node _T_464 = mux(_T_463, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_465 = and(UInt<2>("h02"), _T_464) @[axi4_to_ahb.scala 167:15] - node _T_466 = or(_T_460, _T_465) @[axi4_to_ahb.scala 166:146] - node _T_467 = bits(_T_449, 7, 0) @[axi4_to_ahb.scala 168:36] - node _T_468 = eq(_T_467, UInt<8>("h0f0")) @[axi4_to_ahb.scala 168:43] - node _T_469 = bits(_T_449, 7, 0) @[axi4_to_ahb.scala 168:67] - node _T_470 = eq(_T_469, UInt<8>("h03")) @[axi4_to_ahb.scala 168:74] - node _T_471 = or(_T_468, _T_470) @[axi4_to_ahb.scala 168:56] - node _T_472 = bits(_T_471, 0, 0) @[Bitwise.scala 72:15] - node _T_473 = mux(_T_472, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_474 = and(UInt<3>("h04"), _T_473) @[axi4_to_ahb.scala 168:15] - node _T_475 = or(_T_466, _T_474) @[axi4_to_ahb.scala 167:63] - node _T_476 = bits(_T_449, 7, 0) @[axi4_to_ahb.scala 169:37] - node _T_477 = eq(_T_476, UInt<8>("h0c0")) @[axi4_to_ahb.scala 169:44] - node _T_478 = bits(_T_477, 0, 0) @[Bitwise.scala 72:15] - node _T_479 = mux(_T_478, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_480 = and(UInt<3>("h06"), _T_479) @[axi4_to_ahb.scala 169:17] - node _T_481 = or(_T_475, _T_480) @[axi4_to_ahb.scala 168:96] - node _T_482 = bits(_T_449, 7, 0) @[axi4_to_ahb.scala 170:37] - node _T_483 = eq(_T_482, UInt<8>("h0c0")) @[axi4_to_ahb.scala 170:44] - node _T_484 = bits(_T_483, 0, 0) @[Bitwise.scala 72:15] - node _T_485 = mux(_T_484, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_486 = and(UInt<3>("h06"), _T_485) @[axi4_to_ahb.scala 170:17] - node _T_487 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 323:152] - node _T_488 = mux(_T_448, _T_481, _T_487) @[axi4_to_ahb.scala 323:43] - node _T_489 = cat(_T_444, _T_488) @[Cat.scala 29:58] - buf_addr_in <= _T_489 @[axi4_to_ahb.scala 323:15] - node _T_490 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 324:27] - buf_tag_in <= _T_490 @[axi4_to_ahb.scala 324:14] - node _T_491 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 325:32] - buf_byteen_in <= _T_491 @[axi4_to_ahb.scala 325:17] - node _T_492 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 326:33] - node _T_493 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 326:59] - node _T_494 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 326:80] - node _T_495 = mux(_T_492, _T_493, _T_494) @[axi4_to_ahb.scala 326:21] - buf_data_in <= _T_495 @[axi4_to_ahb.scala 326:15] - node _T_496 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 327:52] - node _T_497 = eq(_T_496, UInt<2>("h03")) @[axi4_to_ahb.scala 327:58] - node _T_498 = and(buf_aligned_in, _T_497) @[axi4_to_ahb.scala 327:38] - node _T_499 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 327:84] - node _T_500 = eq(_T_499, UInt<1>("h01")) @[axi4_to_ahb.scala 327:91] - node _T_501 = and(_T_498, _T_500) @[axi4_to_ahb.scala 327:71] - node _T_502 = bits(_T_501, 0, 0) @[axi4_to_ahb.scala 327:111] - node _T_503 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 327:142] - node _T_504 = bits(_T_503, 7, 0) @[axi4_to_ahb.scala 160:40] - node _T_505 = eq(_T_504, UInt<8>("h0ff")) @[axi4_to_ahb.scala 160:47] - node _T_506 = bits(_T_505, 0, 0) @[Bitwise.scala 72:15] - node _T_507 = mux(_T_506, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_508 = and(UInt<2>("h03"), _T_507) @[axi4_to_ahb.scala 160:23] - node _T_509 = bits(_T_503, 7, 0) @[axi4_to_ahb.scala 161:35] - node _T_510 = eq(_T_509, UInt<8>("h0f0")) @[axi4_to_ahb.scala 161:42] - node _T_511 = bits(_T_503, 7, 0) @[axi4_to_ahb.scala 161:64] - node _T_512 = eq(_T_511, UInt<8>("h0f")) @[axi4_to_ahb.scala 161:71] - node _T_513 = or(_T_510, _T_512) @[axi4_to_ahb.scala 161:55] - node _T_514 = bits(_T_513, 0, 0) @[Bitwise.scala 72:15] - node _T_515 = mux(_T_514, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_516 = and(UInt<2>("h02"), _T_515) @[axi4_to_ahb.scala 161:16] - node _T_517 = or(_T_508, _T_516) @[axi4_to_ahb.scala 160:62] - node _T_518 = bits(_T_503, 7, 0) @[axi4_to_ahb.scala 162:40] - node _T_519 = eq(_T_518, UInt<8>("h0c0")) @[axi4_to_ahb.scala 162:47] - node _T_520 = bits(_T_503, 7, 0) @[axi4_to_ahb.scala 162:69] - node _T_521 = eq(_T_520, UInt<6>("h030")) @[axi4_to_ahb.scala 162:76] - node _T_522 = or(_T_519, _T_521) @[axi4_to_ahb.scala 162:60] - node _T_523 = bits(_T_503, 7, 0) @[axi4_to_ahb.scala 162:98] - node _T_524 = eq(_T_523, UInt<8>("h0c")) @[axi4_to_ahb.scala 162:105] - node _T_525 = or(_T_522, _T_524) @[axi4_to_ahb.scala 162:89] - node _T_526 = bits(_T_503, 7, 0) @[axi4_to_ahb.scala 162:132] - node _T_527 = eq(_T_526, UInt<8>("h03")) @[axi4_to_ahb.scala 162:139] - node _T_528 = or(_T_525, _T_527) @[axi4_to_ahb.scala 162:123] - node _T_529 = bits(_T_528, 0, 0) @[Bitwise.scala 72:15] - node _T_530 = mux(_T_529, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_531 = and(UInt<2>("h01"), _T_530) @[axi4_to_ahb.scala 162:21] - node _T_532 = or(_T_517, _T_531) @[axi4_to_ahb.scala 161:93] - node _T_533 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 327:161] - node _T_534 = mux(_T_502, _T_532, _T_533) @[axi4_to_ahb.scala 327:21] - buf_size_in <= _T_534 @[axi4_to_ahb.scala 327:15] - node _T_535 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 328:32] - node _T_536 = eq(_T_535, UInt<1>("h00")) @[axi4_to_ahb.scala 328:39] - node _T_537 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 329:17] - node _T_538 = eq(_T_537, UInt<1>("h00")) @[axi4_to_ahb.scala 329:24] - node _T_539 = or(_T_536, _T_538) @[axi4_to_ahb.scala 328:48] - node _T_540 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 329:47] - node _T_541 = eq(_T_540, UInt<2>("h01")) @[axi4_to_ahb.scala 329:54] - node _T_542 = or(_T_539, _T_541) @[axi4_to_ahb.scala 329:33] - node _T_543 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 329:86] - node _T_544 = eq(_T_543, UInt<2>("h02")) @[axi4_to_ahb.scala 329:93] - node _T_545 = or(_T_542, _T_544) @[axi4_to_ahb.scala 329:72] - node _T_546 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 330:18] - node _T_547 = eq(_T_546, UInt<2>("h03")) @[axi4_to_ahb.scala 330:25] - node _T_548 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 330:55] - node _T_549 = eq(_T_548, UInt<2>("h03")) @[axi4_to_ahb.scala 330:62] - node _T_550 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 330:90] - node _T_551 = eq(_T_550, UInt<4>("h0c")) @[axi4_to_ahb.scala 330:97] - node _T_552 = or(_T_549, _T_551) @[axi4_to_ahb.scala 330:74] - node _T_553 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 330:125] - node _T_554 = eq(_T_553, UInt<6>("h030")) @[axi4_to_ahb.scala 330:132] - node _T_555 = or(_T_552, _T_554) @[axi4_to_ahb.scala 330:109] - node _T_556 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 330:161] - node _T_557 = eq(_T_556, UInt<8>("h0c0")) @[axi4_to_ahb.scala 330:168] - node _T_558 = or(_T_555, _T_557) @[axi4_to_ahb.scala 330:145] - node _T_559 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 331:21] - node _T_560 = eq(_T_559, UInt<4>("h0f")) @[axi4_to_ahb.scala 331:28] - node _T_561 = or(_T_558, _T_560) @[axi4_to_ahb.scala 330:181] - node _T_562 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 331:56] - node _T_563 = eq(_T_562, UInt<8>("h0f0")) @[axi4_to_ahb.scala 331:63] - node _T_564 = or(_T_561, _T_563) @[axi4_to_ahb.scala 331:40] - node _T_565 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 331:92] - node _T_566 = eq(_T_565, UInt<8>("h0ff")) @[axi4_to_ahb.scala 331:99] - node _T_567 = or(_T_564, _T_566) @[axi4_to_ahb.scala 331:76] - node _T_568 = and(_T_547, _T_567) @[axi4_to_ahb.scala 330:38] - node _T_569 = or(_T_545, _T_568) @[axi4_to_ahb.scala 329:106] - buf_aligned_in <= _T_569 @[axi4_to_ahb.scala 328:18] - node _T_570 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 333:39] - node _T_571 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 333:58] - node _T_572 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 333:83] + cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 341:16] + node _T_441 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 342:33] + node _T_442 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 342:73] + node _T_443 = eq(_T_442, UInt<1>("h01")) @[axi4_to_ahb.scala 342:80] + node _T_444 = and(buf_aligned_in, _T_443) @[axi4_to_ahb.scala 342:60] + node _T_445 = bits(_T_444, 0, 0) @[axi4_to_ahb.scala 342:100] + node _T_446 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 342:132] + node _T_447 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 166:50] + node _T_448 = eq(_T_447, UInt<8>("h0ff")) @[axi4_to_ahb.scala 166:57] + node _T_449 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 166:81] + node _T_450 = eq(_T_449, UInt<8>("h0f")) @[axi4_to_ahb.scala 166:88] + node _T_451 = or(_T_448, _T_450) @[axi4_to_ahb.scala 166:70] + node _T_452 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 166:117] + node _T_453 = eq(_T_452, UInt<8>("h03")) @[axi4_to_ahb.scala 166:124] + node _T_454 = or(_T_451, _T_453) @[axi4_to_ahb.scala 166:106] + node _T_455 = bits(_T_454, 0, 0) @[Bitwise.scala 72:15] + node _T_456 = mux(_T_455, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_457 = and(UInt<3>("h00"), _T_456) @[axi4_to_ahb.scala 166:29] + node _T_458 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 167:35] + node _T_459 = eq(_T_458, UInt<8>("h0c")) @[axi4_to_ahb.scala 167:42] + node _T_460 = bits(_T_459, 0, 0) @[Bitwise.scala 72:15] + node _T_461 = mux(_T_460, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_462 = and(UInt<2>("h02"), _T_461) @[axi4_to_ahb.scala 167:15] + node _T_463 = or(_T_457, _T_462) @[axi4_to_ahb.scala 166:146] + node _T_464 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 168:36] + node _T_465 = eq(_T_464, UInt<8>("h0f0")) @[axi4_to_ahb.scala 168:43] + node _T_466 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 168:67] + node _T_467 = eq(_T_466, UInt<8>("h03")) @[axi4_to_ahb.scala 168:74] + node _T_468 = or(_T_465, _T_467) @[axi4_to_ahb.scala 168:56] + node _T_469 = bits(_T_468, 0, 0) @[Bitwise.scala 72:15] + node _T_470 = mux(_T_469, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_471 = and(UInt<3>("h04"), _T_470) @[axi4_to_ahb.scala 168:15] + node _T_472 = or(_T_463, _T_471) @[axi4_to_ahb.scala 167:63] + node _T_473 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 169:37] + node _T_474 = eq(_T_473, UInt<8>("h0c0")) @[axi4_to_ahb.scala 169:44] + node _T_475 = bits(_T_474, 0, 0) @[Bitwise.scala 72:15] + node _T_476 = mux(_T_475, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_477 = and(UInt<3>("h06"), _T_476) @[axi4_to_ahb.scala 169:17] + node _T_478 = or(_T_472, _T_477) @[axi4_to_ahb.scala 168:96] + node _T_479 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 170:37] + node _T_480 = eq(_T_479, UInt<8>("h0c0")) @[axi4_to_ahb.scala 170:44] + node _T_481 = bits(_T_480, 0, 0) @[Bitwise.scala 72:15] + node _T_482 = mux(_T_481, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_483 = and(UInt<3>("h06"), _T_482) @[axi4_to_ahb.scala 170:17] + node _T_484 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 342:152] + node _T_485 = mux(_T_445, _T_478, _T_484) @[axi4_to_ahb.scala 342:43] + node _T_486 = cat(_T_441, _T_485) @[Cat.scala 29:58] + buf_addr_in <= _T_486 @[axi4_to_ahb.scala 342:15] + node _T_487 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 343:27] + buf_tag_in <= _T_487 @[axi4_to_ahb.scala 343:14] + node _T_488 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 344:32] + buf_byteen_in <= _T_488 @[axi4_to_ahb.scala 344:17] + node _T_489 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 345:33] + node _T_490 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 345:59] + node _T_491 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 345:80] + node _T_492 = mux(_T_489, _T_490, _T_491) @[axi4_to_ahb.scala 345:21] + buf_data_in <= _T_492 @[axi4_to_ahb.scala 345:15] + node _T_493 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 346:52] + node _T_494 = eq(_T_493, UInt<2>("h03")) @[axi4_to_ahb.scala 346:58] + node _T_495 = and(buf_aligned_in, _T_494) @[axi4_to_ahb.scala 346:38] + node _T_496 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 346:84] + node _T_497 = eq(_T_496, UInt<1>("h01")) @[axi4_to_ahb.scala 346:91] + node _T_498 = and(_T_495, _T_497) @[axi4_to_ahb.scala 346:71] + node _T_499 = bits(_T_498, 0, 0) @[axi4_to_ahb.scala 346:111] + node _T_500 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 346:142] + node _T_501 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 160:40] + node _T_502 = eq(_T_501, UInt<8>("h0ff")) @[axi4_to_ahb.scala 160:47] + node _T_503 = bits(_T_502, 0, 0) @[Bitwise.scala 72:15] + node _T_504 = mux(_T_503, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_505 = and(UInt<2>("h03"), _T_504) @[axi4_to_ahb.scala 160:23] + node _T_506 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 161:35] + node _T_507 = eq(_T_506, UInt<8>("h0f0")) @[axi4_to_ahb.scala 161:42] + node _T_508 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 161:64] + node _T_509 = eq(_T_508, UInt<8>("h0f")) @[axi4_to_ahb.scala 161:71] + node _T_510 = or(_T_507, _T_509) @[axi4_to_ahb.scala 161:55] + node _T_511 = bits(_T_510, 0, 0) @[Bitwise.scala 72:15] + node _T_512 = mux(_T_511, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_513 = and(UInt<2>("h02"), _T_512) @[axi4_to_ahb.scala 161:16] + node _T_514 = or(_T_505, _T_513) @[axi4_to_ahb.scala 160:62] + node _T_515 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 162:40] + node _T_516 = eq(_T_515, UInt<8>("h0c0")) @[axi4_to_ahb.scala 162:47] + node _T_517 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 162:69] + node _T_518 = eq(_T_517, UInt<6>("h030")) @[axi4_to_ahb.scala 162:76] + node _T_519 = or(_T_516, _T_518) @[axi4_to_ahb.scala 162:60] + node _T_520 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 162:98] + node _T_521 = eq(_T_520, UInt<8>("h0c")) @[axi4_to_ahb.scala 162:105] + node _T_522 = or(_T_519, _T_521) @[axi4_to_ahb.scala 162:89] + node _T_523 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 162:132] + node _T_524 = eq(_T_523, UInt<8>("h03")) @[axi4_to_ahb.scala 162:139] + node _T_525 = or(_T_522, _T_524) @[axi4_to_ahb.scala 162:123] + node _T_526 = bits(_T_525, 0, 0) @[Bitwise.scala 72:15] + node _T_527 = mux(_T_526, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_528 = and(UInt<2>("h01"), _T_527) @[axi4_to_ahb.scala 162:21] + node _T_529 = or(_T_514, _T_528) @[axi4_to_ahb.scala 161:93] + node _T_530 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 346:161] + node _T_531 = mux(_T_499, _T_529, _T_530) @[axi4_to_ahb.scala 346:21] + buf_size_in <= _T_531 @[axi4_to_ahb.scala 346:15] + node _T_532 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 347:32] + node _T_533 = eq(_T_532, UInt<1>("h00")) @[axi4_to_ahb.scala 347:39] + node _T_534 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 348:17] + node _T_535 = eq(_T_534, UInt<1>("h00")) @[axi4_to_ahb.scala 348:24] + node _T_536 = or(_T_533, _T_535) @[axi4_to_ahb.scala 347:48] + node _T_537 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 348:47] + node _T_538 = eq(_T_537, UInt<2>("h01")) @[axi4_to_ahb.scala 348:54] + node _T_539 = or(_T_536, _T_538) @[axi4_to_ahb.scala 348:33] + node _T_540 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 348:86] + node _T_541 = eq(_T_540, UInt<2>("h02")) @[axi4_to_ahb.scala 348:93] + node _T_542 = or(_T_539, _T_541) @[axi4_to_ahb.scala 348:72] + node _T_543 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 349:18] + node _T_544 = eq(_T_543, UInt<2>("h03")) @[axi4_to_ahb.scala 349:25] + node _T_545 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 349:55] + node _T_546 = eq(_T_545, UInt<2>("h03")) @[axi4_to_ahb.scala 349:62] + node _T_547 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 349:90] + node _T_548 = eq(_T_547, UInt<4>("h0c")) @[axi4_to_ahb.scala 349:97] + node _T_549 = or(_T_546, _T_548) @[axi4_to_ahb.scala 349:74] + node _T_550 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 349:125] + node _T_551 = eq(_T_550, UInt<6>("h030")) @[axi4_to_ahb.scala 349:132] + node _T_552 = or(_T_549, _T_551) @[axi4_to_ahb.scala 349:109] + node _T_553 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 349:161] + node _T_554 = eq(_T_553, UInt<8>("h0c0")) @[axi4_to_ahb.scala 349:168] + node _T_555 = or(_T_552, _T_554) @[axi4_to_ahb.scala 349:145] + node _T_556 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 350:21] + node _T_557 = eq(_T_556, UInt<4>("h0f")) @[axi4_to_ahb.scala 350:28] + node _T_558 = or(_T_555, _T_557) @[axi4_to_ahb.scala 349:181] + node _T_559 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 350:56] + node _T_560 = eq(_T_559, UInt<8>("h0f0")) @[axi4_to_ahb.scala 350:63] + node _T_561 = or(_T_558, _T_560) @[axi4_to_ahb.scala 350:40] + node _T_562 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 350:92] + node _T_563 = eq(_T_562, UInt<8>("h0ff")) @[axi4_to_ahb.scala 350:99] + node _T_564 = or(_T_561, _T_563) @[axi4_to_ahb.scala 350:76] + node _T_565 = and(_T_544, _T_564) @[axi4_to_ahb.scala 349:38] + node _T_566 = or(_T_542, _T_565) @[axi4_to_ahb.scala 348:106] + buf_aligned_in <= _T_566 @[axi4_to_ahb.scala 347:18] + node _T_567 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 352:39] + node _T_568 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 352:58] + node _T_569 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 352:83] + node _T_570 = cat(_T_568, _T_569) @[Cat.scala 29:58] + node _T_571 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 352:104] + node _T_572 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 352:129] node _T_573 = cat(_T_571, _T_572) @[Cat.scala 29:58] - node _T_574 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 333:104] - node _T_575 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 333:129] - node _T_576 = cat(_T_574, _T_575) @[Cat.scala 29:58] - node _T_577 = mux(_T_570, _T_573, _T_576) @[axi4_to_ahb.scala 333:22] - io.ahb_haddr <= _T_577 @[axi4_to_ahb.scala 333:16] - node _T_578 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 334:39] - node _T_579 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15] - node _T_580 = mux(_T_579, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_581 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 334:90] - node _T_582 = and(_T_580, _T_581) @[axi4_to_ahb.scala 334:77] - node _T_583 = cat(UInt<1>("h00"), _T_582) @[Cat.scala 29:58] - node _T_584 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15] - node _T_585 = mux(_T_584, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_586 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 334:144] - node _T_587 = and(_T_585, _T_586) @[axi4_to_ahb.scala 334:134] - node _T_588 = cat(UInt<1>("h00"), _T_587) @[Cat.scala 29:58] - node _T_589 = mux(_T_578, _T_583, _T_588) @[axi4_to_ahb.scala 334:22] - io.ahb_hsize <= _T_589 @[axi4_to_ahb.scala 334:16] - io.ahb_hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 336:17] - io.ahb_hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 337:20] - node _T_590 = bits(io.axi_arprot, 2, 2) @[axi4_to_ahb.scala 338:47] - node _T_591 = not(_T_590) @[axi4_to_ahb.scala 338:33] - node _T_592 = cat(UInt<1>("h01"), _T_591) @[Cat.scala 29:58] - io.ahb_hprot <= _T_592 @[axi4_to_ahb.scala 338:16] - node _T_593 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 339:40] - node _T_594 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 339:55] - node _T_595 = eq(_T_594, UInt<1>("h01")) @[axi4_to_ahb.scala 339:62] - node _T_596 = mux(_T_593, _T_595, buf_write) @[axi4_to_ahb.scala 339:23] - io.ahb_hwrite <= _T_596 @[axi4_to_ahb.scala 339:17] - node _T_597 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 340:28] - io.ahb_hwdata <= _T_597 @[axi4_to_ahb.scala 340:17] - slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 342:15] - node _T_598 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 343:43] - node _T_599 = mux(_T_598, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 343:23] - node _T_600 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15] - node _T_601 = mux(_T_600, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_602 = and(_T_601, UInt<2>("h02")) @[axi4_to_ahb.scala 343:88] - node _T_603 = cat(_T_599, _T_602) @[Cat.scala 29:58] - slave_opc <= _T_603 @[axi4_to_ahb.scala 343:13] - node _T_604 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 344:41] - node _T_605 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 344:66] - node _T_606 = cat(_T_605, _T_605) @[Cat.scala 29:58] - node _T_607 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 344:91] - node _T_608 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 344:110] - node _T_609 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 344:131] - node _T_610 = mux(_T_607, _T_608, _T_609) @[axi4_to_ahb.scala 344:79] - node _T_611 = mux(_T_604, _T_606, _T_610) @[axi4_to_ahb.scala 344:21] - slave_rdata <= _T_611 @[axi4_to_ahb.scala 344:15] - node _T_612 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 345:26] - slave_tag <= _T_612 @[axi4_to_ahb.scala 345:13] - node _T_613 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 347:33] - node _T_614 = neq(_T_613, UInt<1>("h00")) @[axi4_to_ahb.scala 347:40] - node _T_615 = and(_T_614, io.ahb_hready) @[axi4_to_ahb.scala 347:52] - node _T_616 = and(_T_615, io.ahb_hwrite) @[axi4_to_ahb.scala 347:68] - last_addr_en <= _T_616 @[axi4_to_ahb.scala 347:16] - node _T_617 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 349:30] - node _T_618 = and(_T_617, master_ready) @[axi4_to_ahb.scala 349:47] - wrbuf_en <= _T_618 @[axi4_to_ahb.scala 349:12] - node _T_619 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 350:34] - node _T_620 = and(_T_619, master_ready) @[axi4_to_ahb.scala 350:50] - wrbuf_data_en <= _T_620 @[axi4_to_ahb.scala 350:17] - node _T_621 = and(master_valid, master_ready) @[axi4_to_ahb.scala 351:34] - node _T_622 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 351:62] - node _T_623 = eq(_T_622, UInt<1>("h01")) @[axi4_to_ahb.scala 351:69] - node _T_624 = and(_T_621, _T_623) @[axi4_to_ahb.scala 351:49] - wrbuf_cmd_sent <= _T_624 @[axi4_to_ahb.scala 351:18] - node _T_625 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 352:33] - node _T_626 = and(wrbuf_cmd_sent, _T_625) @[axi4_to_ahb.scala 352:31] - wrbuf_rst <= _T_626 @[axi4_to_ahb.scala 352:13] - node _T_627 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 354:35] - node _T_628 = and(wrbuf_vld, _T_627) @[axi4_to_ahb.scala 354:33] - node _T_629 = eq(_T_628, UInt<1>("h00")) @[axi4_to_ahb.scala 354:21] - node _T_630 = and(_T_629, master_ready) @[axi4_to_ahb.scala 354:52] - io.axi_awready <= _T_630 @[axi4_to_ahb.scala 354:18] - node _T_631 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 355:39] - node _T_632 = and(wrbuf_data_vld, _T_631) @[axi4_to_ahb.scala 355:37] - node _T_633 = eq(_T_632, UInt<1>("h00")) @[axi4_to_ahb.scala 355:20] - node _T_634 = and(_T_633, master_ready) @[axi4_to_ahb.scala 355:56] - io.axi_wready <= _T_634 @[axi4_to_ahb.scala 355:17] - node _T_635 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 356:33] - node _T_636 = eq(_T_635, UInt<1>("h00")) @[axi4_to_ahb.scala 356:21] - node _T_637 = and(_T_636, master_ready) @[axi4_to_ahb.scala 356:51] - io.axi_arready <= _T_637 @[axi4_to_ahb.scala 356:18] - io.axi_rlast <= UInt<1>("h01") @[axi4_to_ahb.scala 357:16] - node _T_638 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 359:71] - node _T_639 = mux(_T_638, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 359:55] - node _T_640 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 359:91] - node _T_641 = and(_T_639, _T_640) @[axi4_to_ahb.scala 359:89] - reg _T_642 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 359:51] - _T_642 <= _T_641 @[axi4_to_ahb.scala 359:51] - wrbuf_vld <= _T_642 @[axi4_to_ahb.scala 359:21] - node _T_643 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 360:76] - node _T_644 = mux(_T_643, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 360:55] - node _T_645 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 360:102] - node _T_646 = and(_T_644, _T_645) @[axi4_to_ahb.scala 360:100] - reg _T_647 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 360:51] - _T_647 <= _T_646 @[axi4_to_ahb.scala 360:51] - wrbuf_data_vld <= _T_647 @[axi4_to_ahb.scala 360:21] - node _T_648 = bits(io.axi_awid, 0, 0) @[axi4_to_ahb.scala 361:65] - node _T_649 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 361:99] + node _T_574 = mux(_T_567, _T_570, _T_573) @[axi4_to_ahb.scala 352:22] + io.ahb_haddr <= _T_574 @[axi4_to_ahb.scala 352:16] + node _T_575 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 353:39] + node _T_576 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15] + node _T_577 = mux(_T_576, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_578 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 353:90] + node _T_579 = and(_T_577, _T_578) @[axi4_to_ahb.scala 353:77] + node _T_580 = cat(UInt<1>("h00"), _T_579) @[Cat.scala 29:58] + node _T_581 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15] + node _T_582 = mux(_T_581, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_583 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 353:144] + node _T_584 = and(_T_582, _T_583) @[axi4_to_ahb.scala 353:134] + node _T_585 = cat(UInt<1>("h00"), _T_584) @[Cat.scala 29:58] + node _T_586 = mux(_T_575, _T_580, _T_585) @[axi4_to_ahb.scala 353:22] + io.ahb_hsize <= _T_586 @[axi4_to_ahb.scala 353:16] + io.ahb_hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 355:17] + io.ahb_hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 356:20] + node _T_587 = bits(io.axi_arprot, 2, 2) @[axi4_to_ahb.scala 357:47] + node _T_588 = not(_T_587) @[axi4_to_ahb.scala 357:33] + node _T_589 = cat(UInt<1>("h01"), _T_588) @[Cat.scala 29:58] + io.ahb_hprot <= _T_589 @[axi4_to_ahb.scala 357:16] + node _T_590 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 358:40] + node _T_591 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 358:55] + node _T_592 = eq(_T_591, UInt<1>("h01")) @[axi4_to_ahb.scala 358:62] + node _T_593 = mux(_T_590, _T_592, buf_write) @[axi4_to_ahb.scala 358:23] + io.ahb_hwrite <= _T_593 @[axi4_to_ahb.scala 358:17] + node _T_594 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 359:28] + io.ahb_hwdata <= _T_594 @[axi4_to_ahb.scala 359:17] + slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 361:15] + node _T_595 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 362:43] + node _T_596 = mux(_T_595, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 362:23] + node _T_597 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15] + node _T_598 = mux(_T_597, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_599 = and(_T_598, UInt<2>("h02")) @[axi4_to_ahb.scala 362:88] + node _T_600 = cat(_T_596, _T_599) @[Cat.scala 29:58] + slave_opc <= _T_600 @[axi4_to_ahb.scala 362:13] + node _T_601 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 363:41] + node _T_602 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 363:66] + node _T_603 = cat(_T_602, _T_602) @[Cat.scala 29:58] + node _T_604 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 363:91] + node _T_605 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 363:110] + node _T_606 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 363:131] + node _T_607 = mux(_T_604, _T_605, _T_606) @[axi4_to_ahb.scala 363:79] + node _T_608 = mux(_T_601, _T_603, _T_607) @[axi4_to_ahb.scala 363:21] + slave_rdata <= _T_608 @[axi4_to_ahb.scala 363:15] + node _T_609 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 364:26] + slave_tag <= _T_609 @[axi4_to_ahb.scala 364:13] + node _T_610 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 366:33] + node _T_611 = neq(_T_610, UInt<1>("h00")) @[axi4_to_ahb.scala 366:40] + node _T_612 = and(_T_611, io.ahb_hready) @[axi4_to_ahb.scala 366:52] + node _T_613 = and(_T_612, io.ahb_hwrite) @[axi4_to_ahb.scala 366:68] + last_addr_en <= _T_613 @[axi4_to_ahb.scala 366:16] + node _T_614 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 368:30] + node _T_615 = and(_T_614, master_ready) @[axi4_to_ahb.scala 368:47] + wrbuf_en <= _T_615 @[axi4_to_ahb.scala 368:12] + node _T_616 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 369:34] + node _T_617 = and(_T_616, master_ready) @[axi4_to_ahb.scala 369:50] + wrbuf_data_en <= _T_617 @[axi4_to_ahb.scala 369:17] + node _T_618 = and(master_valid, master_ready) @[axi4_to_ahb.scala 370:34] + node _T_619 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 370:62] + node _T_620 = eq(_T_619, UInt<1>("h01")) @[axi4_to_ahb.scala 370:69] + node _T_621 = and(_T_618, _T_620) @[axi4_to_ahb.scala 370:49] + wrbuf_cmd_sent <= _T_621 @[axi4_to_ahb.scala 370:18] + node _T_622 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 371:33] + node _T_623 = and(wrbuf_cmd_sent, _T_622) @[axi4_to_ahb.scala 371:31] + wrbuf_rst <= _T_623 @[axi4_to_ahb.scala 371:13] + node _T_624 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 373:35] + node _T_625 = and(wrbuf_vld, _T_624) @[axi4_to_ahb.scala 373:33] + node _T_626 = eq(_T_625, UInt<1>("h00")) @[axi4_to_ahb.scala 373:21] + node _T_627 = and(_T_626, master_ready) @[axi4_to_ahb.scala 373:52] + io.axi_awready <= _T_627 @[axi4_to_ahb.scala 373:18] + node _T_628 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 374:39] + node _T_629 = and(wrbuf_data_vld, _T_628) @[axi4_to_ahb.scala 374:37] + node _T_630 = eq(_T_629, UInt<1>("h00")) @[axi4_to_ahb.scala 374:20] + node _T_631 = and(_T_630, master_ready) @[axi4_to_ahb.scala 374:56] + io.axi_wready <= _T_631 @[axi4_to_ahb.scala 374:17] + node _T_632 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 375:33] + node _T_633 = eq(_T_632, UInt<1>("h00")) @[axi4_to_ahb.scala 375:21] + node _T_634 = and(_T_633, master_ready) @[axi4_to_ahb.scala 375:51] + io.axi_arready <= _T_634 @[axi4_to_ahb.scala 375:18] + io.axi_rlast <= UInt<1>("h01") @[axi4_to_ahb.scala 376:16] + node _T_635 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 378:71] + node _T_636 = mux(_T_635, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 378:55] + node _T_637 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 378:91] + node _T_638 = and(_T_636, _T_637) @[axi4_to_ahb.scala 378:89] + reg _T_639 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 378:51] + _T_639 <= _T_638 @[axi4_to_ahb.scala 378:51] + wrbuf_vld <= _T_639 @[axi4_to_ahb.scala 378:21] + node _T_640 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 379:76] + node _T_641 = mux(_T_640, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 379:55] + node _T_642 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 379:102] + node _T_643 = and(_T_641, _T_642) @[axi4_to_ahb.scala 379:100] + reg _T_644 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 379:51] + _T_644 <= _T_643 @[axi4_to_ahb.scala 379:51] + wrbuf_data_vld <= _T_644 @[axi4_to_ahb.scala 379:21] + node _T_645 = bits(io.axi_awid, 0, 0) @[axi4_to_ahb.scala 380:65] + node _T_646 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 380:99] + reg _T_647 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_646 : @[Reg.scala 28:19] + _T_647 <= _T_645 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + wrbuf_tag <= _T_647 @[axi4_to_ahb.scala 380:21] + node _T_648 = bits(io.axi_awsize, 2, 0) @[axi4_to_ahb.scala 381:67] + node _T_649 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 381:95] reg _T_650 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_649 : @[Reg.scala 28:19] _T_650 <= _T_648 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_tag <= _T_650 @[axi4_to_ahb.scala 361:21] - node _T_651 = bits(io.axi_awsize, 2, 0) @[axi4_to_ahb.scala 362:67] - node _T_652 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 362:95] - reg _T_653 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_652 : @[Reg.scala 28:19] - _T_653 <= _T_651 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - wrbuf_size <= _T_653 @[axi4_to_ahb.scala 362:21] - node _T_654 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 363:55] + wrbuf_size <= _T_650 @[axi4_to_ahb.scala 381:21] + node _T_651 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 382:55] inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 508:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset rvclkhdr_2.io.clk <= bus_clk @[el2_lib.scala 510:18] - rvclkhdr_2.io.en <= _T_654 @[el2_lib.scala 511:17] + rvclkhdr_2.io.en <= _T_651 @[el2_lib.scala 511:17] rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_655 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_655 <= io.axi_awaddr @[el2_lib.scala 514:16] - wrbuf_addr <= _T_655 @[axi4_to_ahb.scala 363:21] - node _T_656 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 364:59] + reg _T_652 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_652 <= io.axi_awaddr @[el2_lib.scala 514:16] + wrbuf_addr <= _T_652 @[axi4_to_ahb.scala 382:21] + node _T_653 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 383:59] inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 508:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset rvclkhdr_3.io.clk <= bus_clk @[el2_lib.scala 510:18] - rvclkhdr_3.io.en <= _T_656 @[el2_lib.scala 511:17] + rvclkhdr_3.io.en <= _T_653 @[el2_lib.scala 511:17] rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_657 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_657 <= io.axi_wdata @[el2_lib.scala 514:16] - wrbuf_data <= _T_657 @[axi4_to_ahb.scala 364:21] - node _T_658 = bits(io.axi_wstrb, 7, 0) @[axi4_to_ahb.scala 365:66] - node _T_659 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 365:99] - reg _T_660 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + reg _T_654 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_654 <= io.axi_wdata @[el2_lib.scala 514:16] + wrbuf_data <= _T_654 @[axi4_to_ahb.scala 383:21] + node _T_655 = bits(io.axi_wstrb, 7, 0) @[axi4_to_ahb.scala 384:66] + node _T_656 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 384:99] + reg _T_657 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_656 : @[Reg.scala 28:19] + _T_657 <= _T_655 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + wrbuf_byteen <= _T_657 @[axi4_to_ahb.scala 384:21] + node _T_658 = bits(io.ahb_haddr, 31, 0) @[axi4_to_ahb.scala 385:67] + node _T_659 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 385:100] + reg _T_660 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_659 : @[Reg.scala 28:19] _T_660 <= _T_658 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_byteen <= _T_660 @[axi4_to_ahb.scala 365:21] - node _T_661 = bits(io.ahb_haddr, 31, 0) @[axi4_to_ahb.scala 366:67] - node _T_662 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 366:100] - reg _T_663 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_662 : @[Reg.scala 28:19] - _T_663 <= _T_661 @[Reg.scala 28:23] + last_bus_addr <= _T_660 @[axi4_to_ahb.scala 385:21] + node _T_661 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 386:89] + reg _T_662 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_661 : @[Reg.scala 28:19] + _T_662 <= buf_write_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - last_bus_addr <= _T_663 @[axi4_to_ahb.scala 366:21] - node _T_664 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 367:89] + buf_write <= _T_662 @[axi4_to_ahb.scala 386:21] + node _T_663 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 387:64] + node _T_664 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 387:99] reg _T_665 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_664 : @[Reg.scala 28:19] - _T_665 <= buf_write_in @[Reg.scala 28:23] + _T_665 <= _T_663 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_write <= _T_665 @[axi4_to_ahb.scala 367:21] - node _T_666 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 368:64] - node _T_667 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 368:99] - reg _T_668 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_667 : @[Reg.scala 28:19] - _T_668 <= _T_666 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_tag <= _T_668 @[axi4_to_ahb.scala 368:21] - node _T_669 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 369:42] - node _T_670 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 369:61] - node _T_671 = bits(_T_670, 0, 0) @[axi4_to_ahb.scala 369:78] + buf_tag <= _T_665 @[axi4_to_ahb.scala 387:21] + node _T_666 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 388:42] + node _T_667 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 388:61] + node _T_668 = bits(_T_667, 0, 0) @[axi4_to_ahb.scala 388:78] inst rvclkhdr_4 of rvclkhdr_4 @[el2_lib.scala 508:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset rvclkhdr_4.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_4.io.en <= _T_671 @[el2_lib.scala 511:17] + rvclkhdr_4.io.en <= _T_668 @[el2_lib.scala 511:17] rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_672 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_672 <= _T_669 @[el2_lib.scala 514:16] - buf_addr <= _T_672 @[axi4_to_ahb.scala 369:21] - node _T_673 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 370:65] - node _T_674 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 370:94] - reg _T_675 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_674 : @[Reg.scala 28:19] - _T_675 <= _T_673 @[Reg.scala 28:23] + reg _T_669 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_669 <= _T_666 @[el2_lib.scala 514:16] + buf_addr <= _T_669 @[axi4_to_ahb.scala 388:21] + node _T_670 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 389:65] + node _T_671 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 389:94] + reg _T_672 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_671 : @[Reg.scala 28:19] + _T_672 <= _T_670 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_size <= _T_675 @[axi4_to_ahb.scala 370:21] - node _T_676 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 371:91] + buf_size <= _T_672 @[axi4_to_ahb.scala 389:21] + node _T_673 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 390:91] + reg _T_674 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_673 : @[Reg.scala 28:19] + _T_674 <= buf_aligned_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_aligned <= _T_674 @[axi4_to_ahb.scala 390:21] + node _T_675 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 391:67] + node _T_676 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 391:96] reg _T_677 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_676 : @[Reg.scala 28:19] - _T_677 <= buf_aligned_in @[Reg.scala 28:23] + _T_677 <= _T_675 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_aligned <= _T_677 @[axi4_to_ahb.scala 371:21] - node _T_678 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 372:67] - node _T_679 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 372:96] - reg _T_680 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_679 : @[Reg.scala 28:19] - _T_680 <= _T_678 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_byteen <= _T_680 @[axi4_to_ahb.scala 372:21] - node _T_681 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 373:42] - node _T_682 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 373:66] - node _T_683 = bits(_T_682, 0, 0) @[axi4_to_ahb.scala 373:89] + buf_byteen <= _T_677 @[axi4_to_ahb.scala 391:21] + node _T_678 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 392:42] + node _T_679 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 392:66] + node _T_680 = bits(_T_679, 0, 0) @[axi4_to_ahb.scala 392:89] inst rvclkhdr_5 of rvclkhdr_5 @[el2_lib.scala 508:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset rvclkhdr_5.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_5.io.en <= _T_683 @[el2_lib.scala 511:17] + rvclkhdr_5.io.en <= _T_680 @[el2_lib.scala 511:17] rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_684 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_684 <= _T_681 @[el2_lib.scala 514:16] - buf_data <= _T_684 @[axi4_to_ahb.scala 373:21] - node _T_685 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 374:89] + reg _T_681 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_681 <= _T_678 @[el2_lib.scala 514:16] + buf_data <= _T_681 @[axi4_to_ahb.scala 392:21] + node _T_682 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 393:89] + reg _T_683 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_682 : @[Reg.scala 28:19] + _T_683 <= buf_write @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + slvbuf_write <= _T_683 @[axi4_to_ahb.scala 393:21] + node _T_684 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 394:61] + node _T_685 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 394:99] reg _T_686 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_685 : @[Reg.scala 28:19] - _T_686 <= buf_write @[Reg.scala 28:23] + _T_686 <= _T_684 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_write <= _T_686 @[axi4_to_ahb.scala 374:21] - node _T_687 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 375:61] - node _T_688 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 375:99] - reg _T_689 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_688 : @[Reg.scala 28:19] - _T_689 <= _T_687 @[Reg.scala 28:23] + slvbuf_tag <= _T_686 @[axi4_to_ahb.scala 394:21] + node _T_687 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 395:99] + reg _T_688 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_687 : @[Reg.scala 28:19] + _T_688 <= slvbuf_error_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_tag <= _T_689 @[axi4_to_ahb.scala 375:21] - node _T_690 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 376:99] - reg _T_691 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_690 : @[Reg.scala 28:19] - _T_691 <= slvbuf_error_in @[Reg.scala 28:23] + slvbuf_error <= _T_688 @[axi4_to_ahb.scala 395:21] + node _T_689 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 396:72] + node _T_690 = mux(_T_689, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 396:56] + node _T_691 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 396:92] + node _T_692 = and(_T_690, _T_691) @[axi4_to_ahb.scala 396:90] + reg _T_693 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 396:52] + _T_693 <= _T_692 @[axi4_to_ahb.scala 396:52] + cmd_doneQ <= _T_693 @[axi4_to_ahb.scala 396:21] + node _T_694 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 397:71] + node _T_695 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 397:110] + reg _T_696 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_695 : @[Reg.scala 28:19] + _T_696 <= _T_694 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_error <= _T_691 @[axi4_to_ahb.scala 376:21] - node _T_692 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 377:72] - node _T_693 = mux(_T_692, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 377:56] - node _T_694 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 377:92] - node _T_695 = and(_T_693, _T_694) @[axi4_to_ahb.scala 377:90] - reg _T_696 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 377:52] - _T_696 <= _T_695 @[axi4_to_ahb.scala 377:52] - cmd_doneQ <= _T_696 @[axi4_to_ahb.scala 377:21] - node _T_697 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 378:71] - node _T_698 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 378:110] - reg _T_699 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_698 : @[Reg.scala 28:19] - _T_699 <= _T_697 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_cmd_byte_ptrQ <= _T_699 @[axi4_to_ahb.scala 378:21] - reg _T_700 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 379:52] - _T_700 <= io.ahb_hready @[axi4_to_ahb.scala 379:52] - ahb_hready_q <= _T_700 @[axi4_to_ahb.scala 379:21] - node _T_701 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 380:66] - reg _T_702 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 380:52] - _T_702 <= _T_701 @[axi4_to_ahb.scala 380:52] - ahb_htrans_q <= _T_702 @[axi4_to_ahb.scala 380:21] - reg _T_703 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 381:57] - _T_703 <= io.ahb_hwrite @[axi4_to_ahb.scala 381:57] - ahb_hwrite_q <= _T_703 @[axi4_to_ahb.scala 381:21] - reg _T_704 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 382:52] - _T_704 <= io.ahb_hresp @[axi4_to_ahb.scala 382:52] - ahb_hresp_q <= _T_704 @[axi4_to_ahb.scala 382:21] - node _T_705 = bits(io.ahb_hrdata, 63, 0) @[axi4_to_ahb.scala 383:71] - reg _T_706 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 383:57] - _T_706 <= _T_705 @[axi4_to_ahb.scala 383:57] - ahb_hrdata_q <= _T_706 @[axi4_to_ahb.scala 383:21] - node _T_707 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 385:43] - node _T_708 = or(_T_707, io.clk_override) @[axi4_to_ahb.scala 385:58] - node _T_709 = and(io.bus_clk_en, _T_708) @[axi4_to_ahb.scala 385:30] - buf_clken <= _T_709 @[axi4_to_ahb.scala 385:13] - node _T_710 = bits(io.ahb_htrans, 1, 1) @[axi4_to_ahb.scala 386:69] - node _T_711 = and(io.ahb_hready, _T_710) @[axi4_to_ahb.scala 386:54] - node _T_712 = or(_T_711, io.clk_override) @[axi4_to_ahb.scala 386:74] - node _T_713 = and(io.bus_clk_en, _T_712) @[axi4_to_ahb.scala 386:36] - ahbm_addr_clken <= _T_713 @[axi4_to_ahb.scala 386:19] - node _T_714 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 387:50] - node _T_715 = or(_T_714, io.clk_override) @[axi4_to_ahb.scala 387:60] - node _T_716 = and(io.bus_clk_en, _T_715) @[axi4_to_ahb.scala 387:36] - ahbm_data_clken <= _T_716 @[axi4_to_ahb.scala 387:19] + buf_cmd_byte_ptrQ <= _T_696 @[axi4_to_ahb.scala 397:21] + reg _T_697 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 398:52] + _T_697 <= io.ahb_hready @[axi4_to_ahb.scala 398:52] + ahb_hready_q <= _T_697 @[axi4_to_ahb.scala 398:21] + node _T_698 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 399:66] + reg _T_699 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 399:52] + _T_699 <= _T_698 @[axi4_to_ahb.scala 399:52] + ahb_htrans_q <= _T_699 @[axi4_to_ahb.scala 399:21] + reg _T_700 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 400:57] + _T_700 <= io.ahb_hwrite @[axi4_to_ahb.scala 400:57] + ahb_hwrite_q <= _T_700 @[axi4_to_ahb.scala 400:21] + reg _T_701 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 401:52] + _T_701 <= io.ahb_hresp @[axi4_to_ahb.scala 401:52] + ahb_hresp_q <= _T_701 @[axi4_to_ahb.scala 401:21] + node _T_702 = bits(io.ahb_hrdata, 63, 0) @[axi4_to_ahb.scala 402:71] + reg _T_703 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 402:57] + _T_703 <= _T_702 @[axi4_to_ahb.scala 402:57] + ahb_hrdata_q <= _T_703 @[axi4_to_ahb.scala 402:21] + node _T_704 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 404:43] + node _T_705 = or(_T_704, io.clk_override) @[axi4_to_ahb.scala 404:58] + node _T_706 = and(io.bus_clk_en, _T_705) @[axi4_to_ahb.scala 404:30] + buf_clken <= _T_706 @[axi4_to_ahb.scala 404:13] + node _T_707 = bits(io.ahb_htrans, 1, 1) @[axi4_to_ahb.scala 405:69] + node _T_708 = and(io.ahb_hready, _T_707) @[axi4_to_ahb.scala 405:54] + node _T_709 = or(_T_708, io.clk_override) @[axi4_to_ahb.scala 405:74] + node _T_710 = and(io.bus_clk_en, _T_709) @[axi4_to_ahb.scala 405:36] + ahbm_addr_clken <= _T_710 @[axi4_to_ahb.scala 405:19] + node _T_711 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 406:50] + node _T_712 = or(_T_711, io.clk_override) @[axi4_to_ahb.scala 406:60] + node _T_713 = and(io.bus_clk_en, _T_712) @[axi4_to_ahb.scala 406:36] + ahbm_data_clken <= _T_713 @[axi4_to_ahb.scala 406:19] inst rvclkhdr_6 of rvclkhdr_6 @[el2_lib.scala 483:22] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset rvclkhdr_6.io.clk <= clock @[el2_lib.scala 484:17] rvclkhdr_6.io.en <= buf_clken @[el2_lib.scala 485:16] rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 390:12] + buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 409:12] inst rvclkhdr_7 of rvclkhdr_7 @[el2_lib.scala 483:22] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= reset rvclkhdr_7.io.clk <= clock @[el2_lib.scala 484:17] rvclkhdr_7.io.en <= io.bus_clk_en @[el2_lib.scala 485:16] rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 391:12] + ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 410:12] inst rvclkhdr_8 of rvclkhdr_8 @[el2_lib.scala 483:22] rvclkhdr_8.clock <= clock rvclkhdr_8.reset <= reset rvclkhdr_8.io.clk <= clock @[el2_lib.scala 484:17] rvclkhdr_8.io.en <= ahbm_addr_clken @[el2_lib.scala 485:16] rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 392:17] + ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 411:17] inst rvclkhdr_9 of rvclkhdr_9 @[el2_lib.scala 483:22] rvclkhdr_9.clock <= clock rvclkhdr_9.reset <= reset rvclkhdr_9.io.clk <= clock @[el2_lib.scala 484:17] rvclkhdr_9.io.en <= ahbm_data_clken @[el2_lib.scala 485:16] rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 393:17] + ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 412:17] diff --git a/axi4_to_ahb.v b/axi4_to_ahb.v index fb5d18b2..f2a982d1 100644 --- a/axi4_to_ahb.v +++ b/axi4_to_ahb.v @@ -132,25 +132,25 @@ module axi4_to_ahb( wire rvclkhdr_9_io_clk; // @[el2_lib.scala 483:22] wire rvclkhdr_9_io_en; // @[el2_lib.scala 483:22] wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 483:22] - wire ahbm_clk = rvclkhdr_7_io_l1clk; // @[axi4_to_ahb.scala 63:22 axi4_to_ahb.scala 391:12] + wire ahbm_clk = rvclkhdr_7_io_l1clk; // @[axi4_to_ahb.scala 63:22 axi4_to_ahb.scala 410:12] reg [2:0] buf_state; // @[axi4_to_ahb.scala 69:45] wire _T_49 = 3'h0 == buf_state; // @[Conditional.scala 37:30] wire bus_clk = rvclkhdr_io_l1clk; // @[axi4_to_ahb.scala 89:21 axi4_to_ahb.scala 201:11] - reg wrbuf_vld; // @[axi4_to_ahb.scala 359:51] - reg wrbuf_data_vld; // @[axi4_to_ahb.scala 360:51] + reg wrbuf_vld; // @[axi4_to_ahb.scala 378:51] + reg wrbuf_data_vld; // @[axi4_to_ahb.scala 379:51] wire wr_cmd_vld = wrbuf_vld & wrbuf_data_vld; // @[axi4_to_ahb.scala 178:27] wire master_valid = wr_cmd_vld | io_axi_arvalid; // @[axi4_to_ahb.scala 179:30] wire _T_101 = 3'h1 == buf_state; // @[Conditional.scala 37:30] - reg ahb_hready_q; // @[axi4_to_ahb.scala 379:52] - reg [1:0] ahb_htrans_q; // @[axi4_to_ahb.scala 380:52] + reg ahb_hready_q; // @[axi4_to_ahb.scala 398:52] + reg [1:0] ahb_htrans_q; // @[axi4_to_ahb.scala 399:52] wire _T_108 = ahb_htrans_q != 2'h0; // @[axi4_to_ahb.scala 241:58] wire _T_109 = ahb_hready_q & _T_108; // @[axi4_to_ahb.scala 241:36] - wire ahbm_addr_clk = rvclkhdr_8_io_l1clk; // @[axi4_to_ahb.scala 64:27 axi4_to_ahb.scala 392:17] - reg ahb_hwrite_q; // @[axi4_to_ahb.scala 381:57] + wire ahbm_addr_clk = rvclkhdr_8_io_l1clk; // @[axi4_to_ahb.scala 64:27 axi4_to_ahb.scala 411:17] + reg ahb_hwrite_q; // @[axi4_to_ahb.scala 400:57] wire _T_110 = ~ahb_hwrite_q; // @[axi4_to_ahb.scala 241:72] wire _T_111 = _T_109 & _T_110; // @[axi4_to_ahb.scala 241:70] wire _T_136 = 3'h6 == buf_state; // @[Conditional.scala 37:30] - reg ahb_hresp_q; // @[axi4_to_ahb.scala 382:52] + reg ahb_hresp_q; // @[axi4_to_ahb.scala 401:52] wire _T_156 = ahb_hready_q | ahb_hresp_q; // @[axi4_to_ahb.scala 255:37] wire _T_175 = 3'h7 == buf_state; // @[Conditional.scala 37:30] wire _T_186 = 3'h3 == buf_state; // @[Conditional.scala 37:30] @@ -165,12 +165,12 @@ module axi4_to_ahb( wire _GEN_79 = _T_136 ? 1'h0 : _GEN_59; // @[Conditional.scala 39:67] wire _GEN_95 = _T_101 ? 1'h0 : _GEN_79; // @[Conditional.scala 39:67] wire trxn_done = _T_49 ? 1'h0 : _GEN_95; // @[Conditional.scala 40:58] - reg cmd_doneQ; // @[axi4_to_ahb.scala 377:52] + reg cmd_doneQ; // @[axi4_to_ahb.scala 396:52] wire _T_282 = cmd_doneQ & ahb_hready_q; // @[axi4_to_ahb.scala 297:34] wire _T_283 = _T_282 | ahb_hresp_q; // @[axi4_to_ahb.scala 297:50] - wire _T_443 = 3'h5 == buf_state; // @[Conditional.scala 37:30] + wire _T_440 = 3'h5 == buf_state; // @[Conditional.scala 37:30] wire slave_ready = io_axi_bready & io_axi_rready; // @[axi4_to_ahb.scala 196:32] - wire _GEN_1 = _T_443 & slave_ready; // @[Conditional.scala 39:67] + wire _GEN_1 = _T_440 & slave_ready; // @[Conditional.scala 39:67] wire _GEN_3 = _T_281 ? _T_283 : _GEN_1; // @[Conditional.scala 39:67] wire _GEN_20 = _T_188 ? trxn_done : _GEN_3; // @[Conditional.scala 39:67] wire _GEN_35 = _T_186 ? _T_156 : _GEN_20; // @[Conditional.scala 39:67] @@ -199,9 +199,9 @@ module axi4_to_ahb( wire _T_141 = master_valid & _T_51; // @[axi4_to_ahb.scala 252:70] wire _T_142 = ~_T_141; // @[axi4_to_ahb.scala 252:55] wire _T_143 = _T_138 & _T_142; // @[axi4_to_ahb.scala 252:53] - wire _T_287 = _T_283 & _T_137; // @[axi4_to_ahb.scala 298:66] - wire _T_288 = _T_287 & slave_ready; // @[axi4_to_ahb.scala 298:81] - wire _GEN_4 = _T_281 & _T_288; // @[Conditional.scala 39:67] + wire _T_285 = buf_state_en & _T_137; // @[axi4_to_ahb.scala 298:36] + wire _T_286 = _T_285 & slave_ready; // @[axi4_to_ahb.scala 298:51] + wire _GEN_4 = _T_281 & _T_286; // @[Conditional.scala 39:67] wire _GEN_26 = _T_188 ? 1'h0 : _GEN_4; // @[Conditional.scala 39:67] wire _GEN_45 = _T_186 ? 1'h0 : _GEN_26; // @[Conditional.scala 39:67] wire _GEN_62 = _T_175 ? 1'h0 : _GEN_45; // @[Conditional.scala 39:67] @@ -212,12 +212,12 @@ module axi4_to_ahb( wire _T_152 = _T_149 & _T_103; // @[axi4_to_ahb.scala 254:97] wire [2:0] _T_154 = _T_152 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 254:67] wire [2:0] _T_155 = ahb_hresp_q ? 3'h7 : _T_154; // @[axi4_to_ahb.scala 254:26] - wire _T_289 = ~slave_ready; // @[axi4_to_ahb.scala 299:42] - wire _T_290 = ahb_hresp_q | _T_289; // @[axi4_to_ahb.scala 299:40] - wire [2:0] _T_296 = _T_51 ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 299:119] - wire [2:0] _T_297 = _T_149 ? _T_296 : 3'h0; // @[axi4_to_ahb.scala 299:75] - wire [2:0] _T_298 = _T_290 ? 3'h5 : _T_297; // @[axi4_to_ahb.scala 299:26] - wire [2:0] _GEN_5 = _T_281 ? _T_298 : 3'h0; // @[Conditional.scala 39:67] + wire _T_287 = ~slave_ready; // @[axi4_to_ahb.scala 299:42] + wire _T_288 = ahb_hresp_q | _T_287; // @[axi4_to_ahb.scala 299:40] + wire [2:0] _T_293 = _T_51 ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 299:99] + wire [2:0] _T_294 = master_valid ? _T_293 : 3'h0; // @[axi4_to_ahb.scala 299:65] + wire [2:0] _T_295 = _T_288 ? 3'h5 : _T_294; // @[axi4_to_ahb.scala 299:26] + wire [2:0] _GEN_5 = _T_281 ? _T_295 : 3'h0; // @[Conditional.scala 39:67] wire [2:0] _GEN_18 = _T_188 ? 3'h4 : _GEN_5; // @[Conditional.scala 39:67] wire [2:0] _GEN_34 = _T_186 ? 3'h5 : _GEN_18; // @[Conditional.scala 39:67] wire [2:0] _GEN_50 = _T_175 ? 3'h3 : _GEN_34; // @[Conditional.scala 39:67] @@ -231,56 +231,55 @@ module axi4_to_ahb( wire [2:0] master_size = wr_cmd_vld ? wrbuf_size : io_axi_arsize; // @[axi4_to_ahb.scala 183:21] reg [7:0] wrbuf_byteen; // @[Reg.scala 27:20] reg [63:0] wrbuf_data; // @[el2_lib.scala 514:16] - wire _T_158 = buf_state_en & _T_137; // @[axi4_to_ahb.scala 259:39] - wire _T_361 = buf_nxtstate != 3'h5; // @[axi4_to_ahb.scala 308:55] - wire _T_362 = buf_state_en & _T_361; // @[axi4_to_ahb.scala 308:39] - wire _GEN_14 = _T_281 ? _T_362 : _T_443; // @[Conditional.scala 39:67] + wire _T_358 = buf_nxtstate != 3'h5; // @[axi4_to_ahb.scala 309:55] + wire _T_359 = buf_state_en & _T_358; // @[axi4_to_ahb.scala 309:39] + wire _GEN_14 = _T_281 ? _T_359 : _T_440; // @[Conditional.scala 39:67] wire _GEN_33 = _T_188 ? 1'h0 : _GEN_14; // @[Conditional.scala 39:67] wire _GEN_49 = _T_186 ? 1'h0 : _GEN_33; // @[Conditional.scala 39:67] wire _GEN_52 = _T_175 ? buf_state_en : _GEN_49; // @[Conditional.scala 39:67] - wire _GEN_73 = _T_136 ? _T_158 : _GEN_52; // @[Conditional.scala 39:67] + wire _GEN_73 = _T_136 ? _T_285 : _GEN_52; // @[Conditional.scala 39:67] wire _GEN_94 = _T_101 ? 1'h0 : _GEN_73; // @[Conditional.scala 39:67] wire slave_valid_pre = _T_49 ? 1'h0 : _GEN_94; // @[Conditional.scala 40:58] wire _T_25 = slave_valid_pre & slave_ready; // @[axi4_to_ahb.scala 188:32] - wire buf_clk = rvclkhdr_6_io_l1clk; // @[axi4_to_ahb.scala 157:21 axi4_to_ahb.scala 390:12] + wire buf_clk = rvclkhdr_6_io_l1clk; // @[axi4_to_ahb.scala 157:21 axi4_to_ahb.scala 409:12] reg slvbuf_write; // @[Reg.scala 27:20] - wire [1:0] _T_599 = slvbuf_write ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 343:23] + wire [1:0] _T_596 = slvbuf_write ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 362:23] reg slvbuf_error; // @[Reg.scala 27:20] - wire [1:0] _T_601 = slvbuf_error ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_602 = _T_601 & 2'h2; // @[axi4_to_ahb.scala 343:88] - wire [3:0] slave_opc = {_T_599,_T_602}; // @[Cat.scala 29:58] + wire [1:0] _T_598 = slvbuf_error ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_599 = _T_598 & 2'h2; // @[axi4_to_ahb.scala 362:88] + wire [3:0] slave_opc = {_T_596,_T_599}; // @[Cat.scala 29:58] wire [1:0] _T_30 = slave_opc[1] ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 189:49] reg slvbuf_tag; // @[Reg.scala 27:20] wire _T_35 = slave_opc[3:2] == 2'h0; // @[axi4_to_ahb.scala 192:65] reg [31:0] last_bus_addr; // @[Reg.scala 27:20] - wire [63:0] _T_606 = {last_bus_addr,last_bus_addr}; // @[Cat.scala 29:58] - wire _T_607 = buf_state == 3'h5; // @[axi4_to_ahb.scala 344:91] + wire [63:0] _T_603 = {last_bus_addr,last_bus_addr}; // @[Cat.scala 29:58] + wire _T_604 = buf_state == 3'h5; // @[axi4_to_ahb.scala 363:91] reg [63:0] buf_data; // @[el2_lib.scala 514:16] - wire ahbm_data_clk = rvclkhdr_9_io_l1clk; // @[axi4_to_ahb.scala 65:27 axi4_to_ahb.scala 393:17] - reg [63:0] ahb_hrdata_q; // @[axi4_to_ahb.scala 383:57] - wire [63:0] _T_610 = _T_607 ? buf_data : ahb_hrdata_q; // @[axi4_to_ahb.scala 344:79] + wire ahbm_data_clk = rvclkhdr_9_io_l1clk; // @[axi4_to_ahb.scala 65:27 axi4_to_ahb.scala 412:17] + reg [63:0] ahb_hrdata_q; // @[axi4_to_ahb.scala 402:57] + wire [63:0] _T_607 = _T_604 ? buf_data : ahb_hrdata_q; // @[axi4_to_ahb.scala 363:79] wire _T_44 = io_axi_awvalid & io_axi_awready; // @[axi4_to_ahb.scala 199:56] wire _T_45 = io_axi_wvalid & io_axi_wready; // @[axi4_to_ahb.scala 199:91] wire _T_46 = _T_44 | _T_45; // @[axi4_to_ahb.scala 199:74] wire _T_55 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 230:54] wire _T_56 = buf_state_en & _T_55; // @[axi4_to_ahb.scala 230:38] - wire [3:0] _T_86 = wrbuf_byteen[7] ? 4'h7 : 4'h8; // @[Mux.scala 98:16] - wire [3:0] _T_87 = wrbuf_byteen[6] ? 4'h6 : _T_86; // @[Mux.scala 98:16] - wire [3:0] _T_88 = wrbuf_byteen[5] ? 4'h5 : _T_87; // @[Mux.scala 98:16] - wire [3:0] _T_89 = wrbuf_byteen[4] ? 4'h4 : _T_88; // @[Mux.scala 98:16] - wire [3:0] _T_90 = wrbuf_byteen[3] ? 4'h3 : _T_89; // @[Mux.scala 98:16] - wire [3:0] _T_91 = wrbuf_byteen[2] ? 4'h2 : _T_90; // @[Mux.scala 98:16] - wire [3:0] _T_92 = wrbuf_byteen[1] ? 4'h1 : _T_91; // @[Mux.scala 98:16] - wire [3:0] _T_93 = wrbuf_byteen[0] ? 4'h0 : _T_92; // @[Mux.scala 98:16] + wire [3:0] _T_86 = wrbuf_byteen[0] ? 4'h0 : 4'h8; // @[Mux.scala 98:16] + wire [3:0] _T_87 = wrbuf_byteen[1] ? 4'h1 : _T_86; // @[Mux.scala 98:16] + wire [3:0] _T_88 = wrbuf_byteen[2] ? 4'h2 : _T_87; // @[Mux.scala 98:16] + wire [3:0] _T_89 = wrbuf_byteen[3] ? 4'h3 : _T_88; // @[Mux.scala 98:16] + wire [3:0] _T_90 = wrbuf_byteen[4] ? 4'h4 : _T_89; // @[Mux.scala 98:16] + wire [3:0] _T_91 = wrbuf_byteen[5] ? 4'h5 : _T_90; // @[Mux.scala 98:16] + wire [3:0] _T_92 = wrbuf_byteen[6] ? 4'h6 : _T_91; // @[Mux.scala 98:16] + wire [3:0] _T_93 = wrbuf_byteen[7] ? 4'h7 : _T_92; // @[Mux.scala 98:16] wire [3:0] _T_95 = buf_write_in ? _T_93 : {{1'd0}, master_addr[2:0]}; // @[axi4_to_ahb.scala 233:30] wire _T_96 = buf_nxtstate == 3'h1; // @[axi4_to_ahb.scala 235:51] wire _T_126 = master_ready & master_valid; // @[axi4_to_ahb.scala 246:33] wire _T_162 = buf_nxtstate == 3'h6; // @[axi4_to_ahb.scala 261:64] wire _T_163 = _T_126 & _T_162; // @[axi4_to_ahb.scala 261:48] wire _T_164 = _T_163 & buf_state_en; // @[axi4_to_ahb.scala 261:79] - wire _T_352 = buf_state_en & buf_write_in; // @[axi4_to_ahb.scala 306:33] - wire _T_354 = _T_352 & _T_55; // @[axi4_to_ahb.scala 306:48] - wire _GEN_12 = _T_281 & _T_354; // @[Conditional.scala 39:67] + wire _T_349 = buf_state_en & buf_write_in; // @[axi4_to_ahb.scala 307:33] + wire _T_351 = _T_349 & _T_55; // @[axi4_to_ahb.scala 307:48] + wire _GEN_12 = _T_281 & _T_351; // @[Conditional.scala 39:67] wire _GEN_32 = _T_188 ? 1'h0 : _GEN_12; // @[Conditional.scala 39:67] wire _GEN_48 = _T_186 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67] wire _GEN_65 = _T_175 ? 1'h0 : _GEN_48; // @[Conditional.scala 39:67] @@ -321,14 +320,14 @@ module axi4_to_ahb( wire _T_216 = buf_byteen[5] & _T_215; // @[axi4_to_ahb.scala 175:48] wire _T_218 = 3'h6 >= _T_197; // @[axi4_to_ahb.scala 175:62] wire _T_219 = buf_byteen[6] & _T_218; // @[axi4_to_ahb.scala 175:48] - wire [3:0] _T_223 = buf_byteen[7] ? 4'h7 : 4'h8; // @[Mux.scala 98:16] - wire [3:0] _T_224 = _T_219 ? 4'h6 : _T_223; // @[Mux.scala 98:16] - wire [3:0] _T_225 = _T_216 ? 4'h5 : _T_224; // @[Mux.scala 98:16] - wire [3:0] _T_226 = _T_213 ? 4'h4 : _T_225; // @[Mux.scala 98:16] - wire [3:0] _T_227 = _T_210 ? 4'h3 : _T_226; // @[Mux.scala 98:16] - wire [3:0] _T_228 = _T_207 ? 4'h2 : _T_227; // @[Mux.scala 98:16] - wire [3:0] _T_229 = _T_204 ? 4'h1 : _T_228; // @[Mux.scala 98:16] - wire [3:0] _T_230 = _T_201 ? 4'h0 : _T_229; // @[Mux.scala 98:16] + wire [3:0] _T_223 = _T_201 ? 4'h0 : 4'h8; // @[Mux.scala 98:16] + wire [3:0] _T_224 = _T_204 ? 4'h1 : _T_223; // @[Mux.scala 98:16] + wire [3:0] _T_225 = _T_207 ? 4'h2 : _T_224; // @[Mux.scala 98:16] + wire [3:0] _T_226 = _T_210 ? 4'h3 : _T_225; // @[Mux.scala 98:16] + wire [3:0] _T_227 = _T_213 ? 4'h4 : _T_226; // @[Mux.scala 98:16] + wire [3:0] _T_228 = _T_216 ? 4'h5 : _T_227; // @[Mux.scala 98:16] + wire [3:0] _T_229 = _T_219 ? 4'h6 : _T_228; // @[Mux.scala 98:16] + wire [3:0] _T_230 = buf_byteen[7] ? 4'h7 : _T_229; // @[Mux.scala 98:16] wire [3:0] _T_231 = trxn_done ? _T_230 : {{1'd0}, buf_cmd_byte_ptrQ}; // @[axi4_to_ahb.scala 291:30] wire _T_232 = buf_cmd_byte_ptrQ == 3'h7; // @[axi4_to_ahb.scala 292:65] reg buf_aligned; // @[Reg.scala 27:20] @@ -337,10 +336,10 @@ module axi4_to_ahb( wire _T_273 = ~_T_271[0]; // @[axi4_to_ahb.scala 292:163] wire _T_274 = _T_233 | _T_273; // @[axi4_to_ahb.scala 292:79] wire _T_275 = trxn_done & _T_274; // @[axi4_to_ahb.scala 292:29] - wire _T_349 = _T_232 | _T_273; // @[axi4_to_ahb.scala 305:123] - wire _T_350 = _T_109 & _T_349; // @[axi4_to_ahb.scala 305:87] - wire _T_351 = ahb_hresp_q | _T_350; // @[axi4_to_ahb.scala 305:32] - wire _GEN_11 = _T_281 & _T_351; // @[Conditional.scala 39:67] + wire _T_346 = _T_232 | _T_273; // @[axi4_to_ahb.scala 306:38] + wire _T_347 = _T_109 & _T_346; // @[axi4_to_ahb.scala 305:80] + wire _T_348 = ahb_hresp_q | _T_347; // @[axi4_to_ahb.scala 305:34] + wire _GEN_11 = _T_281 & _T_348; // @[Conditional.scala 39:67] wire _GEN_24 = _T_188 ? _T_275 : _GEN_11; // @[Conditional.scala 39:67] wire _GEN_43 = _T_186 ? 1'h0 : _GEN_24; // @[Conditional.scala 39:67] wire _GEN_61 = _T_175 ? 1'h0 : _GEN_43; // @[Conditional.scala 39:67] @@ -351,16 +350,16 @@ module axi4_to_ahb( wire _T_277 = ~_T_276; // @[axi4_to_ahb.scala 293:32] wire [1:0] _T_279 = _T_277 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] wire [1:0] _T_280 = _T_279 & 2'h2; // @[axi4_to_ahb.scala 293:57] - wire _T_303 = _T_55 | _T_96; // @[axi4_to_ahb.scala 303:62] - wire _T_304 = buf_state_en & _T_303; // @[axi4_to_ahb.scala 303:33] - wire _T_357 = _T_277 | bypass_en; // @[axi4_to_ahb.scala 307:57] - wire [1:0] _T_359 = _T_357 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_360 = _T_359 & 2'h2; // @[axi4_to_ahb.scala 307:71] - wire _T_367 = trxn_done | bypass_en; // @[axi4_to_ahb.scala 310:40] - wire [3:0] _T_442 = bypass_en ? _T_93 : _T_231; // @[axi4_to_ahb.scala 311:30] + wire _T_300 = _T_55 | _T_96; // @[axi4_to_ahb.scala 303:62] + wire _T_301 = buf_state_en & _T_300; // @[axi4_to_ahb.scala 303:33] + wire _T_354 = _T_277 | bypass_en; // @[axi4_to_ahb.scala 308:57] + wire [1:0] _T_356 = _T_354 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_357 = _T_356 & 2'h2; // @[axi4_to_ahb.scala 308:71] + wire _T_364 = trxn_done | bypass_en; // @[axi4_to_ahb.scala 311:40] + wire [3:0] _T_439 = bypass_en ? _T_93 : _T_231; // @[axi4_to_ahb.scala 312:30] wire _GEN_6 = _T_281 & ahb_hresp_q; // @[Conditional.scala 39:67] - wire _GEN_7 = _T_281 ? buf_state_en : _T_443; // @[Conditional.scala 39:67] - wire _GEN_9 = _T_281 & _T_304; // @[Conditional.scala 39:67] + wire _GEN_7 = _T_281 ? buf_state_en : _T_440; // @[Conditional.scala 39:67] + wire _GEN_9 = _T_281 & _T_301; // @[Conditional.scala 39:67] wire _GEN_30 = _T_188 ? 1'h0 : _GEN_9; // @[Conditional.scala 39:67] wire _GEN_47 = _T_186 ? 1'h0 : _GEN_30; // @[Conditional.scala 39:67] wire _GEN_64 = _T_175 ? 1'h0 : _GEN_47; // @[Conditional.scala 39:67] @@ -368,9 +367,9 @@ module axi4_to_ahb( wire _GEN_87 = _T_101 ? master_ready : _GEN_67; // @[Conditional.scala 39:67] wire buf_wr_en = _T_49 ? buf_state_en : _GEN_87; // @[Conditional.scala 40:58] wire _GEN_10 = _T_281 & buf_wr_en; // @[Conditional.scala 39:67] - wire [1:0] _GEN_13 = _T_281 ? _T_360 : 2'h0; // @[Conditional.scala 39:67] - wire _GEN_16 = _T_281 & _T_367; // @[Conditional.scala 39:67] - wire [3:0] _GEN_17 = _T_281 ? _T_442 : 4'h0; // @[Conditional.scala 39:67] + wire [1:0] _GEN_13 = _T_281 ? _T_357 : 2'h0; // @[Conditional.scala 39:67] + wire _GEN_16 = _T_281 & _T_364; // @[Conditional.scala 39:67] + wire [3:0] _GEN_17 = _T_281 ? _T_439 : 4'h0; // @[Conditional.scala 39:67] wire _GEN_21 = _T_188 ? buf_state_en : _GEN_16; // @[Conditional.scala 39:67] wire _GEN_22 = _T_188 & buf_state_en; // @[Conditional.scala 39:67] wire [3:0] _GEN_23 = _T_188 ? _T_231 : _GEN_17; // @[Conditional.scala 39:67] @@ -406,93 +405,93 @@ module axi4_to_ahb( wire [3:0] _GEN_105 = _T_49 ? _T_95 : _GEN_89; // @[Conditional.scala 40:58] wire slvbuf_wr_en = _T_49 ? 1'h0 : _GEN_85; // @[Conditional.scala 40:58] wire slvbuf_error_en = _T_49 ? 1'h0 : _GEN_93; // @[Conditional.scala 40:58] - wire _T_538 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 329:24] - wire _T_539 = _T_103 | _T_538; // @[axi4_to_ahb.scala 328:48] - wire _T_541 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 329:54] - wire _T_542 = _T_539 | _T_541; // @[axi4_to_ahb.scala 329:33] - wire _T_544 = master_size[1:0] == 2'h2; // @[axi4_to_ahb.scala 329:93] - wire _T_545 = _T_542 | _T_544; // @[axi4_to_ahb.scala 329:72] - wire _T_547 = master_size[1:0] == 2'h3; // @[axi4_to_ahb.scala 330:25] - wire _T_549 = wrbuf_byteen == 8'h3; // @[axi4_to_ahb.scala 330:62] - wire _T_551 = wrbuf_byteen == 8'hc; // @[axi4_to_ahb.scala 330:97] - wire _T_552 = _T_549 | _T_551; // @[axi4_to_ahb.scala 330:74] - wire _T_554 = wrbuf_byteen == 8'h30; // @[axi4_to_ahb.scala 330:132] - wire _T_555 = _T_552 | _T_554; // @[axi4_to_ahb.scala 330:109] - wire _T_557 = wrbuf_byteen == 8'hc0; // @[axi4_to_ahb.scala 330:168] - wire _T_558 = _T_555 | _T_557; // @[axi4_to_ahb.scala 330:145] - wire _T_560 = wrbuf_byteen == 8'hf; // @[axi4_to_ahb.scala 331:28] - wire _T_561 = _T_558 | _T_560; // @[axi4_to_ahb.scala 330:181] - wire _T_563 = wrbuf_byteen == 8'hf0; // @[axi4_to_ahb.scala 331:63] - wire _T_564 = _T_561 | _T_563; // @[axi4_to_ahb.scala 331:40] - wire _T_566 = wrbuf_byteen == 8'hff; // @[axi4_to_ahb.scala 331:99] - wire _T_567 = _T_564 | _T_566; // @[axi4_to_ahb.scala 331:76] - wire _T_568 = _T_547 & _T_567; // @[axi4_to_ahb.scala 330:38] - wire buf_aligned_in = _T_545 | _T_568; // @[axi4_to_ahb.scala 329:106] - wire _T_447 = buf_aligned_in & _T_51; // @[axi4_to_ahb.scala 323:60] - wire [2:0] _T_464 = _T_551 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_465 = 3'h2 & _T_464; // @[axi4_to_ahb.scala 167:15] - wire _T_471 = _T_563 | _T_549; // @[axi4_to_ahb.scala 168:56] - wire [2:0] _T_473 = _T_471 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_474 = 3'h4 & _T_473; // @[axi4_to_ahb.scala 168:15] - wire [2:0] _T_475 = _T_465 | _T_474; // @[axi4_to_ahb.scala 167:63] - wire [2:0] _T_479 = _T_557 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_480 = 3'h6 & _T_479; // @[axi4_to_ahb.scala 169:17] - wire [2:0] _T_481 = _T_475 | _T_480; // @[axi4_to_ahb.scala 168:96] - wire [2:0] _T_488 = _T_447 ? _T_481 : master_addr[2:0]; // @[axi4_to_ahb.scala 323:43] - wire _T_492 = buf_state == 3'h3; // @[axi4_to_ahb.scala 326:33] - wire _T_498 = buf_aligned_in & _T_547; // @[axi4_to_ahb.scala 327:38] - wire _T_501 = _T_498 & _T_51; // @[axi4_to_ahb.scala 327:71] - wire [1:0] _T_507 = _T_566 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire _T_513 = _T_563 | _T_560; // @[axi4_to_ahb.scala 161:55] - wire [1:0] _T_515 = _T_513 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_516 = 2'h2 & _T_515; // @[axi4_to_ahb.scala 161:16] - wire [1:0] _T_517 = _T_507 | _T_516; // @[axi4_to_ahb.scala 160:62] - wire _T_522 = _T_557 | _T_554; // @[axi4_to_ahb.scala 162:60] - wire _T_525 = _T_522 | _T_551; // @[axi4_to_ahb.scala 162:89] - wire _T_528 = _T_525 | _T_549; // @[axi4_to_ahb.scala 162:123] - wire [1:0] _T_530 = _T_528 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_531 = 2'h1 & _T_530; // @[axi4_to_ahb.scala 162:21] - wire [1:0] _T_532 = _T_517 | _T_531; // @[axi4_to_ahb.scala 161:93] - wire [1:0] _T_534 = _T_501 ? _T_532 : master_size[1:0]; // @[axi4_to_ahb.scala 327:21] - wire [2:0] buf_cmd_byte_ptr = _GEN_105[2:0]; // @[axi4_to_ahb.scala 217:20 axi4_to_ahb.scala 233:24 axi4_to_ahb.scala 247:24 axi4_to_ahb.scala 262:24 axi4_to_ahb.scala 272:24 axi4_to_ahb.scala 291:24 axi4_to_ahb.scala 311:24] - wire [31:0] _T_573 = {master_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] - wire [31:0] _T_576 = {buf_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] - wire [1:0] _T_580 = buf_aligned_in ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [2:0] buf_size_in = {{1'd0}, _T_534}; // @[axi4_to_ahb.scala 327:15] - wire [1:0] _T_582 = _T_580 & buf_size_in[1:0]; // @[axi4_to_ahb.scala 334:77] - wire [2:0] _T_583 = {1'h0,_T_582}; // @[Cat.scala 29:58] - wire [1:0] _T_585 = buf_aligned ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire _T_535 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 348:24] + wire _T_536 = _T_103 | _T_535; // @[axi4_to_ahb.scala 347:48] + wire _T_538 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 348:54] + wire _T_539 = _T_536 | _T_538; // @[axi4_to_ahb.scala 348:33] + wire _T_541 = master_size[1:0] == 2'h2; // @[axi4_to_ahb.scala 348:93] + wire _T_542 = _T_539 | _T_541; // @[axi4_to_ahb.scala 348:72] + wire _T_544 = master_size[1:0] == 2'h3; // @[axi4_to_ahb.scala 349:25] + wire _T_546 = wrbuf_byteen == 8'h3; // @[axi4_to_ahb.scala 349:62] + wire _T_548 = wrbuf_byteen == 8'hc; // @[axi4_to_ahb.scala 349:97] + wire _T_549 = _T_546 | _T_548; // @[axi4_to_ahb.scala 349:74] + wire _T_551 = wrbuf_byteen == 8'h30; // @[axi4_to_ahb.scala 349:132] + wire _T_552 = _T_549 | _T_551; // @[axi4_to_ahb.scala 349:109] + wire _T_554 = wrbuf_byteen == 8'hc0; // @[axi4_to_ahb.scala 349:168] + wire _T_555 = _T_552 | _T_554; // @[axi4_to_ahb.scala 349:145] + wire _T_557 = wrbuf_byteen == 8'hf; // @[axi4_to_ahb.scala 350:28] + wire _T_558 = _T_555 | _T_557; // @[axi4_to_ahb.scala 349:181] + wire _T_560 = wrbuf_byteen == 8'hf0; // @[axi4_to_ahb.scala 350:63] + wire _T_561 = _T_558 | _T_560; // @[axi4_to_ahb.scala 350:40] + wire _T_563 = wrbuf_byteen == 8'hff; // @[axi4_to_ahb.scala 350:99] + wire _T_564 = _T_561 | _T_563; // @[axi4_to_ahb.scala 350:76] + wire _T_565 = _T_544 & _T_564; // @[axi4_to_ahb.scala 349:38] + wire buf_aligned_in = _T_542 | _T_565; // @[axi4_to_ahb.scala 348:106] + wire _T_444 = buf_aligned_in & _T_51; // @[axi4_to_ahb.scala 342:60] + wire [2:0] _T_461 = _T_548 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_462 = 3'h2 & _T_461; // @[axi4_to_ahb.scala 167:15] + wire _T_468 = _T_560 | _T_546; // @[axi4_to_ahb.scala 168:56] + wire [2:0] _T_470 = _T_468 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_471 = 3'h4 & _T_470; // @[axi4_to_ahb.scala 168:15] + wire [2:0] _T_472 = _T_462 | _T_471; // @[axi4_to_ahb.scala 167:63] + wire [2:0] _T_476 = _T_554 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_477 = 3'h6 & _T_476; // @[axi4_to_ahb.scala 169:17] + wire [2:0] _T_478 = _T_472 | _T_477; // @[axi4_to_ahb.scala 168:96] + wire [2:0] _T_485 = _T_444 ? _T_478 : master_addr[2:0]; // @[axi4_to_ahb.scala 342:43] + wire _T_489 = buf_state == 3'h3; // @[axi4_to_ahb.scala 345:33] + wire _T_495 = buf_aligned_in & _T_544; // @[axi4_to_ahb.scala 346:38] + wire _T_498 = _T_495 & _T_51; // @[axi4_to_ahb.scala 346:71] + wire [1:0] _T_504 = _T_563 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire _T_510 = _T_560 | _T_557; // @[axi4_to_ahb.scala 161:55] + wire [1:0] _T_512 = _T_510 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_513 = 2'h2 & _T_512; // @[axi4_to_ahb.scala 161:16] + wire [1:0] _T_514 = _T_504 | _T_513; // @[axi4_to_ahb.scala 160:62] + wire _T_519 = _T_554 | _T_551; // @[axi4_to_ahb.scala 162:60] + wire _T_522 = _T_519 | _T_548; // @[axi4_to_ahb.scala 162:89] + wire _T_525 = _T_522 | _T_546; // @[axi4_to_ahb.scala 162:123] + wire [1:0] _T_527 = _T_525 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_528 = 2'h1 & _T_527; // @[axi4_to_ahb.scala 162:21] + wire [1:0] _T_529 = _T_514 | _T_528; // @[axi4_to_ahb.scala 161:93] + wire [1:0] _T_531 = _T_498 ? _T_529 : master_size[1:0]; // @[axi4_to_ahb.scala 346:21] + wire [2:0] buf_cmd_byte_ptr = _GEN_105[2:0]; // @[axi4_to_ahb.scala 217:20 axi4_to_ahb.scala 233:24 axi4_to_ahb.scala 247:24 axi4_to_ahb.scala 262:24 axi4_to_ahb.scala 272:24 axi4_to_ahb.scala 291:24 axi4_to_ahb.scala 312:24] + wire [31:0] _T_570 = {master_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] + wire [31:0] _T_573 = {buf_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] + wire [1:0] _T_577 = buf_aligned_in ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [2:0] buf_size_in = {{1'd0}, _T_531}; // @[axi4_to_ahb.scala 346:15] + wire [1:0] _T_579 = _T_577 & buf_size_in[1:0]; // @[axi4_to_ahb.scala 353:77] + wire [2:0] _T_580 = {1'h0,_T_579}; // @[Cat.scala 29:58] + wire [1:0] _T_582 = buf_aligned ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] reg [1:0] buf_size; // @[Reg.scala 27:20] - wire [1:0] _T_587 = _T_585 & buf_size; // @[axi4_to_ahb.scala 334:134] - wire [2:0] _T_588 = {1'h0,_T_587}; // @[Cat.scala 29:58] - wire _T_591 = ~io_axi_arprot[2]; // @[axi4_to_ahb.scala 338:33] - wire [1:0] _T_592 = {1'h1,_T_591}; // @[Cat.scala 29:58] + wire [1:0] _T_584 = _T_582 & buf_size; // @[axi4_to_ahb.scala 353:134] + wire [2:0] _T_585 = {1'h0,_T_584}; // @[Cat.scala 29:58] + wire _T_588 = ~io_axi_arprot[2]; // @[axi4_to_ahb.scala 357:33] + wire [1:0] _T_589 = {1'h1,_T_588}; // @[Cat.scala 29:58] reg buf_write; // @[Reg.scala 27:20] - wire _T_614 = io_ahb_htrans != 2'h0; // @[axi4_to_ahb.scala 347:40] - wire _T_615 = _T_614 & io_ahb_hready; // @[axi4_to_ahb.scala 347:52] - wire last_addr_en = _T_615 & io_ahb_hwrite; // @[axi4_to_ahb.scala 347:68] - wire wrbuf_en = _T_44 & master_ready; // @[axi4_to_ahb.scala 349:47] - wire wrbuf_data_en = _T_45 & master_ready; // @[axi4_to_ahb.scala 350:50] - wire wrbuf_cmd_sent = _T_149 & _T_51; // @[axi4_to_ahb.scala 351:49] - wire _T_625 = ~wrbuf_en; // @[axi4_to_ahb.scala 352:33] - wire wrbuf_rst = wrbuf_cmd_sent & _T_625; // @[axi4_to_ahb.scala 352:31] - wire _T_627 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 354:35] - wire _T_628 = wrbuf_vld & _T_627; // @[axi4_to_ahb.scala 354:33] - wire _T_629 = ~_T_628; // @[axi4_to_ahb.scala 354:21] - wire _T_632 = wrbuf_data_vld & _T_627; // @[axi4_to_ahb.scala 355:37] - wire _T_633 = ~_T_632; // @[axi4_to_ahb.scala 355:20] - wire _T_636 = ~wr_cmd_vld; // @[axi4_to_ahb.scala 356:21] - wire _T_639 = wrbuf_en | wrbuf_vld; // @[axi4_to_ahb.scala 359:55] - wire _T_640 = ~wrbuf_rst; // @[axi4_to_ahb.scala 359:91] - wire _T_644 = wrbuf_data_en | wrbuf_data_vld; // @[axi4_to_ahb.scala 360:55] + wire _T_611 = io_ahb_htrans != 2'h0; // @[axi4_to_ahb.scala 366:40] + wire _T_612 = _T_611 & io_ahb_hready; // @[axi4_to_ahb.scala 366:52] + wire last_addr_en = _T_612 & io_ahb_hwrite; // @[axi4_to_ahb.scala 366:68] + wire wrbuf_en = _T_44 & master_ready; // @[axi4_to_ahb.scala 368:47] + wire wrbuf_data_en = _T_45 & master_ready; // @[axi4_to_ahb.scala 369:50] + wire wrbuf_cmd_sent = _T_149 & _T_51; // @[axi4_to_ahb.scala 370:49] + wire _T_622 = ~wrbuf_en; // @[axi4_to_ahb.scala 371:33] + wire wrbuf_rst = wrbuf_cmd_sent & _T_622; // @[axi4_to_ahb.scala 371:31] + wire _T_624 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 373:35] + wire _T_625 = wrbuf_vld & _T_624; // @[axi4_to_ahb.scala 373:33] + wire _T_626 = ~_T_625; // @[axi4_to_ahb.scala 373:21] + wire _T_629 = wrbuf_data_vld & _T_624; // @[axi4_to_ahb.scala 374:37] + wire _T_630 = ~_T_629; // @[axi4_to_ahb.scala 374:20] + wire _T_633 = ~wr_cmd_vld; // @[axi4_to_ahb.scala 375:21] + wire _T_636 = wrbuf_en | wrbuf_vld; // @[axi4_to_ahb.scala 378:55] + wire _T_637 = ~wrbuf_rst; // @[axi4_to_ahb.scala 378:91] + wire _T_641 = wrbuf_data_en | wrbuf_data_vld; // @[axi4_to_ahb.scala 379:55] reg buf_tag; // @[Reg.scala 27:20] - wire _T_694 = ~slave_valid_pre; // @[axi4_to_ahb.scala 377:92] - wire _T_707 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 385:43] - wire _T_708 = _T_707 | io_clk_override; // @[axi4_to_ahb.scala 385:58] - wire _T_711 = io_ahb_hready & io_ahb_htrans[1]; // @[axi4_to_ahb.scala 386:54] - wire _T_712 = _T_711 | io_clk_override; // @[axi4_to_ahb.scala 386:74] - wire _T_714 = buf_state != 3'h0; // @[axi4_to_ahb.scala 387:50] - wire _T_715 = _T_714 | io_clk_override; // @[axi4_to_ahb.scala 387:60] + wire _T_691 = ~slave_valid_pre; // @[axi4_to_ahb.scala 396:92] + wire _T_704 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 404:43] + wire _T_705 = _T_704 | io_clk_override; // @[axi4_to_ahb.scala 404:58] + wire _T_708 = io_ahb_hready & io_ahb_htrans[1]; // @[axi4_to_ahb.scala 405:54] + wire _T_709 = _T_708 | io_clk_override; // @[axi4_to_ahb.scala 405:74] + wire _T_711 = buf_state != 3'h0; // @[axi4_to_ahb.scala 406:50] + wire _T_712 = _T_711 | io_clk_override; // @[axi4_to_ahb.scala 406:60] rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), @@ -553,25 +552,25 @@ module axi4_to_ahb( .io_en(rvclkhdr_9_io_en), .io_scan_mode(rvclkhdr_9_io_scan_mode) ); - assign io_axi_awready = _T_629 & master_ready; // @[axi4_to_ahb.scala 354:18] - assign io_axi_wready = _T_633 & master_ready; // @[axi4_to_ahb.scala 355:17] + assign io_axi_awready = _T_626 & master_ready; // @[axi4_to_ahb.scala 373:18] + assign io_axi_wready = _T_630 & master_ready; // @[axi4_to_ahb.scala 374:17] assign io_axi_bvalid = _T_25 & slave_opc[3]; // @[axi4_to_ahb.scala 188:17] assign io_axi_bresp = slave_opc[0] ? 2'h2 : _T_30; // @[axi4_to_ahb.scala 189:16] assign io_axi_bid = slvbuf_tag; // @[axi4_to_ahb.scala 190:14] - assign io_axi_arready = _T_636 & master_ready; // @[axi4_to_ahb.scala 356:18] + assign io_axi_arready = _T_633 & master_ready; // @[axi4_to_ahb.scala 375:18] assign io_axi_rvalid = _T_25 & _T_35; // @[axi4_to_ahb.scala 192:17] assign io_axi_rid = slvbuf_tag; // @[axi4_to_ahb.scala 194:14] - assign io_axi_rdata = slvbuf_error ? _T_606 : _T_610; // @[axi4_to_ahb.scala 195:16] + assign io_axi_rdata = slvbuf_error ? _T_603 : _T_607; // @[axi4_to_ahb.scala 195:16] assign io_axi_rresp = slave_opc[0] ? 2'h2 : _T_30; // @[axi4_to_ahb.scala 193:16] - assign io_axi_rlast = 1'h1; // @[axi4_to_ahb.scala 357:16] - assign io_ahb_haddr = bypass_en ? _T_573 : _T_576; // @[axi4_to_ahb.scala 333:16] - assign io_ahb_hburst = 3'h0; // @[axi4_to_ahb.scala 336:17] - assign io_ahb_hmastlock = 1'h0; // @[axi4_to_ahb.scala 337:20] - assign io_ahb_hprot = {{2'd0}, _T_592}; // @[axi4_to_ahb.scala 338:16] - assign io_ahb_hsize = bypass_en ? _T_583 : _T_588; // @[axi4_to_ahb.scala 334:16] - assign io_ahb_htrans = _T_49 ? _T_100 : _GEN_90; // @[axi4_to_ahb.scala 205:17 axi4_to_ahb.scala 236:21 axi4_to_ahb.scala 248:21 axi4_to_ahb.scala 263:21 axi4_to_ahb.scala 273:21 axi4_to_ahb.scala 293:21 axi4_to_ahb.scala 307:21] - assign io_ahb_hwrite = bypass_en ? _T_51 : buf_write; // @[axi4_to_ahb.scala 339:17] - assign io_ahb_hwdata = buf_data; // @[axi4_to_ahb.scala 340:17] + assign io_axi_rlast = 1'h1; // @[axi4_to_ahb.scala 376:16] + assign io_ahb_haddr = bypass_en ? _T_570 : _T_573; // @[axi4_to_ahb.scala 352:16] + assign io_ahb_hburst = 3'h0; // @[axi4_to_ahb.scala 355:17] + assign io_ahb_hmastlock = 1'h0; // @[axi4_to_ahb.scala 356:20] + assign io_ahb_hprot = {{2'd0}, _T_589}; // @[axi4_to_ahb.scala 357:16] + assign io_ahb_hsize = bypass_en ? _T_580 : _T_585; // @[axi4_to_ahb.scala 353:16] + assign io_ahb_htrans = _T_49 ? _T_100 : _GEN_90; // @[axi4_to_ahb.scala 205:17 axi4_to_ahb.scala 236:21 axi4_to_ahb.scala 248:21 axi4_to_ahb.scala 263:21 axi4_to_ahb.scala 273:21 axi4_to_ahb.scala 293:21 axi4_to_ahb.scala 308:21] + assign io_ahb_hwrite = bypass_en ? _T_51 : buf_write; // @[axi4_to_ahb.scala 358:17] + assign io_ahb_hwdata = buf_data; // @[axi4_to_ahb.scala 359:17] assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 484:17] assign rvclkhdr_io_en = io_bus_clk_en; // @[el2_lib.scala 485:16] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] @@ -591,16 +590,16 @@ module axi4_to_ahb( assign rvclkhdr_5_io_en = buf_data_wr_en & io_bus_clk_en; // @[el2_lib.scala 511:17] assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_6_io_en = io_bus_clk_en & _T_708; // @[el2_lib.scala 485:16] + assign rvclkhdr_6_io_en = io_bus_clk_en & _T_705; // @[el2_lib.scala 485:16] assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 484:17] assign rvclkhdr_7_io_en = io_bus_clk_en; // @[el2_lib.scala 485:16] assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_8_io_en = io_bus_clk_en & _T_712; // @[el2_lib.scala 485:16] + assign rvclkhdr_8_io_en = io_bus_clk_en & _T_709; // @[el2_lib.scala 485:16] assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_9_io_en = io_bus_clk_en & _T_715; // @[el2_lib.scala 485:16] + assign rvclkhdr_9_io_en = io_bus_clk_en & _T_712; // @[el2_lib.scala 485:16] assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE @@ -805,9 +804,9 @@ end // initial end else if (_T_188) begin buf_state <= 3'h4; end else if (_T_281) begin - if (_T_290) begin + if (_T_288) begin buf_state <= 3'h5; - end else if (_T_149) begin + end else if (master_valid) begin if (_T_51) begin buf_state <= 3'h2; end else begin @@ -825,14 +824,14 @@ end // initial if (reset) begin wrbuf_vld <= 1'h0; end else begin - wrbuf_vld <= _T_639 & _T_640; + wrbuf_vld <= _T_636 & _T_637; end end always @(posedge bus_clk or posedge reset) begin if (reset) begin wrbuf_data_vld <= 1'h0; end else begin - wrbuf_data_vld <= _T_644 & _T_640; + wrbuf_data_vld <= _T_641 & _T_637; end end always @(posedge ahbm_clk or posedge reset) begin @@ -867,7 +866,7 @@ end // initial if (reset) begin cmd_doneQ <= 1'h0; end else begin - cmd_doneQ <= _T_276 & _T_694; + cmd_doneQ <= _T_276 & _T_691; end end always @(posedge bus_clk or posedge reset) begin @@ -950,7 +949,7 @@ end // initial always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin if (reset) begin buf_data <= 64'h0; - end else if (_T_492) begin + end else if (_T_489) begin buf_data <= ahb_hrdata_q; end else begin buf_data <= wrbuf_data; @@ -967,7 +966,7 @@ end // initial if (reset) begin buf_addr <= 32'h0; end else begin - buf_addr <= {master_addr[31:3],_T_488}; + buf_addr <= {master_addr[31:3],_T_485}; end end always @(posedge ahbm_clk or posedge reset) begin diff --git a/src/main/scala/lib/axi4_to_ahb.scala b/src/main/scala/lib/axi4_to_ahb.scala index 8e6f7466..80734301 100644 --- a/src/main/scala/lib/axi4_to_ahb.scala +++ b/src/main/scala/lib/axi4_to_ahb.scala @@ -172,7 +172,7 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config } def get_nxtbyte_ptr(current_byte_ptr: UInt, byteen: UInt, get_next: Bool): UInt = { val start_ptr = Mux(get_next, current_byte_ptr + 1.U, current_byte_ptr) - val temp = (0 until 8).map(j => (byteen(j) & (j.asUInt() >= start_ptr)) -> j.U) + val temp = (0 until 8).map(j => (byteen(j) & (j.asUInt() >= start_ptr)) -> j.U).reverse MuxCase(8.U, temp) } wr_cmd_vld := wrbuf_vld & wrbuf_data_vld @@ -249,7 +249,7 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config } is(stream_rd) { - master_ready := (ahb_hready_q & !ahb_hresp_q) & !(master_valid & master_opc(2, 1) === "b01".U) + master_ready := (ahb_hready_q & !ahb_hresp_q) & ~(master_valid & master_opc(2, 1) === "b01".U) buf_wr_en := (master_valid & master_ready & (master_opc(2, 0) === "b000".U)) // update the fifo if we are streaming the read commands buf_nxtstate := Mux(ahb_hresp_q.asBool(), stream_err_rd, Mux((master_valid & master_ready & (master_opc(2, 0) === "b000".U)).asBool(), stream_rd, data_rd)) // assuming that the master accpets the slave response right away. buf_state_en := (ahb_hready_q | ahb_hresp_q) @@ -295,20 +295,39 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config is(data_wr) { buf_state_en := (cmd_doneQ & ahb_hready_q) | ahb_hresp_q - master_ready := ((cmd_doneQ & ahb_hready_q) | ahb_hresp_q) & !ahb_hresp_q & slave_ready - buf_nxtstate := Mux((ahb_hresp_q | !slave_ready).asBool(), done, Mux((master_valid & master_ready).asBool(), Mux((master_opc(2, 1) === "b01".U(2.W)), cmd_wr, cmd_rd), idle)) + master_ready := buf_state_en & !ahb_hresp_q & slave_ready + buf_nxtstate := Mux((ahb_hresp_q | !slave_ready),done ,Mux((master_valid & master_valid),Mux((master_opc(2,1) === 1.U).asBool(),cmd_wr,cmd_rd),idle)) slvbuf_error_in := ahb_hresp_q slvbuf_error_en := buf_state_en - buf_write_in := (master_opc(2, 1) === "b01".U) + buf_write_in := master_opc(2,1) === 1.U buf_wr_en := buf_state_en & ((buf_nxtstate === cmd_wr) | (buf_nxtstate === cmd_rd)) buf_data_wr_en := buf_wr_en - cmd_done := (ahb_hresp_q | (ahb_hready_q & (ahb_htrans_q(1, 0) =/= "b0".U(2.W)) & ((buf_cmd_byte_ptrQ === "b111".U) | (buf_byteen(get_nxtbyte_ptr(buf_cmd_byte_ptrQ(2, 0), buf_byteen(7, 0), true.B)) === "b0".U)))) - bypass_en := buf_state_en & buf_write_in & (buf_nxtstate === cmd_wr) // Only bypass for writes for the time being - io.ahb_htrans := Fill(2, (!(cmd_done | cmd_doneQ) | bypass_en)) & "b10".U + cmd_done := (ahb_hresp_q | (ahb_hready_q & (ahb_htrans_q(1,0) =/= 0.U) & + ((buf_cmd_byte_ptrQ === 7.U) | (buf_byteen(get_nxtbyte_ptr(buf_cmd_byte_ptrQ(2,0),buf_byteen(7,0),true.B)) === 0.U)))) + bypass_en := buf_state_en & buf_write_in & (buf_nxtstate === cmd_wr) + io.ahb_htrans := Fill(2, (!(cmd_done | cmd_doneQ) | bypass_en)) & 2.U slave_valid_pre := buf_state_en & (buf_nxtstate =/= done) - trxn_done := ahb_hready_q & ahb_hwrite_q & (ahb_htrans_q(1, 0) =/= "b0".U(2.W)) + trxn_done := ahb_hready_q & ahb_hwrite_q & (ahb_htrans_q(1,0) =/= 0.U) buf_cmd_byte_ptr_en := trxn_done | bypass_en - buf_cmd_byte_ptr := Mux(bypass_en, get_nxtbyte_ptr(0.U(3.W), buf_byteen_in(7, 0), false.B), Mux(trxn_done, get_nxtbyte_ptr(buf_cmd_byte_ptrQ(2, 0), buf_byteen(7, 0), true.B), buf_cmd_byte_ptrQ)) + buf_cmd_byte_ptr := Mux(bypass_en,get_nxtbyte_ptr(0.U(3.W),buf_byteen_in(7,0),false.B),Mux(trxn_done,get_nxtbyte_ptr(buf_cmd_byte_ptrQ(2,0),buf_byteen(7,0),true.B),buf_cmd_byte_ptrQ)) + + +// +// buf_state_en := (cmd_doneQ & ahb_hready_q) | ahb_hresp_q +// master_ready := ((cmd_doneQ & ahb_hready_q) | ahb_hresp_q) & !ahb_hresp_q & slave_ready +// buf_nxtstate := Mux((ahb_hresp_q | !slave_ready).asBool(), done, Mux((master_valid & master_ready).asBool(), Mux((master_opc(2, 1) === "b01".U(2.W)), cmd_wr, cmd_rd), idle)) +// slvbuf_error_in := ahb_hresp_q +// slvbuf_error_en := buf_state_en +// buf_write_in := (master_opc(2, 1) === "b01".U) +// buf_wr_en := buf_state_en & ((buf_nxtstate === cmd_wr) | (buf_nxtstate === cmd_rd)) +// buf_data_wr_en := buf_wr_en +// cmd_done := (ahb_hresp_q | (ahb_hready_q & (ahb_htrans_q(1, 0) =/= "b0".U(2.W)) & ((buf_cmd_byte_ptrQ === "b111".U) | (buf_byteen(get_nxtbyte_ptr(buf_cmd_byte_ptrQ(2, 0), buf_byteen(7, 0), true.B)) === "b0".U)))) +// bypass_en := buf_state_en & buf_write_in & (buf_nxtstate === cmd_wr) // Only bypass for writes for the time being +// io.ahb_htrans := Fill(2, (!(cmd_done | cmd_doneQ) | bypass_en)) & "b10".U +// slave_valid_pre := buf_state_en & (buf_nxtstate =/= done) +// trxn_done := ahb_hready_q & ahb_hwrite_q & (ahb_htrans_q(1, 0) =/= "b0".U(2.W)) +// buf_cmd_byte_ptr_en := trxn_done | bypass_en +// buf_cmd_byte_ptr := Mux(bypass_en, get_nxtbyte_ptr(0.U(3.W), buf_byteen_in(7, 0), false.B), Mux(trxn_done, get_nxtbyte_ptr(buf_cmd_byte_ptrQ(2, 0), buf_byteen(7, 0), true.B), buf_cmd_byte_ptrQ)) } is(done) { diff --git a/target/scala-2.12/classes/lib/AXImain$.class b/target/scala-2.12/classes/lib/AXImain$.class index eec2c3cc..35922595 100644 Binary files a/target/scala-2.12/classes/lib/AXImain$.class and b/target/scala-2.12/classes/lib/AXImain$.class differ diff --git a/target/scala-2.12/classes/lib/AXImain$delayedInit$body.class b/target/scala-2.12/classes/lib/AXImain$delayedInit$body.class index 20bd63d0..606682c9 100644 Binary files a/target/scala-2.12/classes/lib/AXImain$delayedInit$body.class and b/target/scala-2.12/classes/lib/AXImain$delayedInit$body.class differ diff --git a/target/scala-2.12/classes/lib/axi4_to_ahb.class b/target/scala-2.12/classes/lib/axi4_to_ahb.class index 7c04d3b8..12b1239c 100644 Binary files a/target/scala-2.12/classes/lib/axi4_to_ahb.class and b/target/scala-2.12/classes/lib/axi4_to_ahb.class differ