IFC
This commit is contained in:
waleed-lm
parent
cba130c0f6
commit
7b86559b2c
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@ -1,35 +1,52 @@
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[
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[
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{
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{
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"class":"firrtl.transforms.CombinationalPath",
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_dout_rs1",
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"sink":"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_l2",
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"sources":[
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"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_l2_31",
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"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_din"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_dout",
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"sources":[
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"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_l2_31",
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"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_din"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_l1",
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"sources":[
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"sources":[
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"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_din"
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"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_din"
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]
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]
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},
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},
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{
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{
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"class":"firrtl.transforms.CombinationalPath",
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_dout_rs3",
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"sink":"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_l2_31",
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"sources":[
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"sources":[
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"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_din"
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"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_din"
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]
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]
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},
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},
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{
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{
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"class":"firrtl.transforms.CombinationalPath",
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_dout_rs2",
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"sink":"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_l3",
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"sources":[
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"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_l2_31",
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"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_din"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_o",
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"sources":[
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"sources":[
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"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_din"
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"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_din"
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]
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]
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},
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},
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{
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{
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"class":"firrtl.transforms.CombinationalPath",
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_dout_bits",
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"sink":"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_legal",
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"sources":[
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"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_din"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_dout_rd",
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"sources":[
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"sources":[
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"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_din"
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"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_din"
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]
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]
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File diff suppressed because it is too large
Load Diff
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@ -1,278 +1,531 @@
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module el2_ifu_compress_ctl(
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module el2_ifu_compress_ctl(
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input clock,
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input clock,
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input reset,
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input reset,
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input [31:0] io_din,
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input [15:0] io_din,
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output [31:0] io_dout_bits,
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output [31:0] io_dout,
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output [4:0] io_dout_rd,
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output [31:0] io_l1,
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output [4:0] io_dout_rs1,
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output [31:0] io_l2,
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output [4:0] io_dout_rs2,
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output [31:0] io_l3,
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output [4:0] io_dout_rs3
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output io_legal,
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output [31:0] io_o,
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output [11:0] io_l2_31
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);
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);
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wire _T_3 = |io_din[12:5]; // @[el2_ifu_compress_ctl.scala 257:29]
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wire _T_2 = ~io_din[14]; // @[el2_ifu_compress_ctl.scala 20:83]
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wire [6:0] _T_4 = _T_3 ? 7'h13 : 7'h1f; // @[el2_ifu_compress_ctl.scala 257:20]
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wire _T_4 = ~io_din[13]; // @[el2_ifu_compress_ctl.scala 20:83]
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wire [4:0] _T_14 = {2'h1,io_din[4:2]}; // @[Cat.scala 29:58]
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wire _T_7 = ~io_din[6]; // @[el2_ifu_compress_ctl.scala 20:83]
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wire [29:0] _T_18 = {io_din[10:7],io_din[12:11],io_din[5],io_din[6],2'h0,5'h2,3'h0,2'h1,io_din[4:2],_T_4}; // @[Cat.scala 29:58]
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wire _T_9 = ~io_din[5]; // @[el2_ifu_compress_ctl.scala 20:83]
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wire [7:0] _T_28 = {io_din[6:5],io_din[12:10],3'h0}; // @[Cat.scala 29:58]
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wire _T_11 = io_din[15] & _T_2; // @[el2_ifu_compress_ctl.scala 20:110]
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wire [4:0] _T_30 = {2'h1,io_din[9:7]}; // @[Cat.scala 29:58]
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wire _T_12 = _T_11 & _T_4; // @[el2_ifu_compress_ctl.scala 20:110]
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wire [27:0] _T_36 = {io_din[6:5],io_din[12:10],3'h0,2'h1,io_din[9:7],3'h3,2'h1,io_din[4:2],7'h7}; // @[Cat.scala 29:58]
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wire _T_13 = _T_12 & io_din[10]; // @[el2_ifu_compress_ctl.scala 20:110]
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wire [6:0] _T_50 = {io_din[5],io_din[12:10],io_din[6],2'h0}; // @[Cat.scala 29:58]
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wire _T_14 = _T_13 & _T_7; // @[el2_ifu_compress_ctl.scala 20:110]
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wire [26:0] _T_58 = {io_din[5],io_din[12:10],io_din[6],2'h0,2'h1,io_din[9:7],3'h2,2'h1,io_din[4:2],7'h3}; // @[Cat.scala 29:58]
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wire _T_15 = _T_14 & _T_9; // @[el2_ifu_compress_ctl.scala 20:110]
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wire [26:0] _T_80 = {io_din[5],io_din[12:10],io_din[6],2'h0,2'h1,io_din[9:7],3'h2,2'h1,io_din[4:2],7'h7}; // @[Cat.scala 29:58]
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wire _T_16 = _T_15 & io_din[0]; // @[el2_ifu_compress_ctl.scala 20:110]
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wire [26:0] _T_111 = {_T_50[6:5],2'h1,io_din[4:2],2'h1,io_din[9:7],3'h2,_T_50[4:0],7'h3f}; // @[Cat.scala 29:58]
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wire _T_23 = ~io_din[11]; // @[el2_ifu_compress_ctl.scala 20:83]
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wire [27:0] _T_138 = {_T_28[7:5],2'h1,io_din[4:2],2'h1,io_din[9:7],3'h3,_T_28[4:0],7'h27}; // @[Cat.scala 29:58]
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wire _T_28 = _T_12 & _T_23; // @[el2_ifu_compress_ctl.scala 20:110]
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wire [26:0] _T_169 = {_T_50[6:5],2'h1,io_din[4:2],2'h1,io_din[9:7],3'h2,_T_50[4:0],7'h23}; // @[Cat.scala 29:58]
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wire _T_29 = _T_28 & io_din[10]; // @[el2_ifu_compress_ctl.scala 20:110]
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wire [26:0] _T_200 = {_T_50[6:5],2'h1,io_din[4:2],2'h1,io_din[9:7],3'h2,_T_50[4:0],7'h27}; // @[Cat.scala 29:58]
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wire _T_30 = _T_29 & io_din[0]; // @[el2_ifu_compress_ctl.scala 20:110]
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wire [6:0] _T_211 = io_din[12] ? 7'h7f : 7'h0; // @[Bitwise.scala 72:12]
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wire out_30 = _T_16 | _T_30; // @[el2_ifu_compress_ctl.scala 23:53]
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wire [11:0] _T_213 = {_T_211,io_din[6:2]}; // @[Cat.scala 29:58]
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wire _T_38 = ~io_din[10]; // @[el2_ifu_compress_ctl.scala 20:83]
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wire [31:0] _T_219 = {_T_211,io_din[6:2],io_din[11:7],3'h0,io_din[11:7],7'h13}; // @[Cat.scala 29:58]
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wire _T_40 = ~io_din[9]; // @[el2_ifu_compress_ctl.scala 20:83]
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wire [9:0] _T_228 = io_din[12] ? 10'h3ff : 10'h0; // @[Bitwise.scala 72:12]
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wire _T_42 = ~io_din[8]; // @[el2_ifu_compress_ctl.scala 20:83]
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wire [20:0] _T_243 = {_T_228,io_din[8],io_din[10:9],io_din[6],io_din[7],io_din[2],io_din[11],io_din[5:3],1'h0}; // @[Cat.scala 29:58]
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wire _T_44 = ~io_din[7]; // @[el2_ifu_compress_ctl.scala 20:83]
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wire [31:0] _T_306 = {_T_243[20],_T_243[10:1],_T_243[11],_T_243[19:12],5'h1,7'h6f}; // @[Cat.scala 29:58]
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wire _T_50 = ~io_din[4]; // @[el2_ifu_compress_ctl.scala 20:83]
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wire [31:0] _T_321 = {_T_211,io_din[6:2],5'h0,3'h0,io_din[11:7],7'h13}; // @[Cat.scala 29:58]
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wire _T_52 = ~io_din[3]; // @[el2_ifu_compress_ctl.scala 20:83]
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wire _T_332 = |_T_213; // @[el2_ifu_compress_ctl.scala 294:29]
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wire _T_54 = ~io_din[2]; // @[el2_ifu_compress_ctl.scala 20:83]
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wire [6:0] _T_333 = _T_332 ? 7'h37 : 7'h3f; // @[el2_ifu_compress_ctl.scala 294:20]
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wire _T_56 = _T_2 & io_din[12]; // @[el2_ifu_compress_ctl.scala 20:110]
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wire [14:0] _T_336 = io_din[12] ? 15'h7fff : 15'h0; // @[Bitwise.scala 72:12]
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wire _T_57 = _T_56 & _T_23; // @[el2_ifu_compress_ctl.scala 20:110]
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wire [31:0] _T_339 = {_T_336,io_din[6:2],12'h0}; // @[Cat.scala 29:58]
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wire _T_58 = _T_57 & _T_38; // @[el2_ifu_compress_ctl.scala 20:110]
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wire [31:0] _T_343 = {_T_339[31:12],io_din[11:7],_T_333}; // @[Cat.scala 29:58]
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wire _T_59 = _T_58 & _T_40; // @[el2_ifu_compress_ctl.scala 20:110]
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wire _T_351 = io_din[11:7] == 5'h0; // @[el2_ifu_compress_ctl.scala 296:14]
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wire _T_60 = _T_59 & _T_42; // @[el2_ifu_compress_ctl.scala 20:110]
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wire _T_353 = io_din[11:7] == 5'h2; // @[el2_ifu_compress_ctl.scala 296:27]
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wire _T_61 = _T_60 & _T_44; // @[el2_ifu_compress_ctl.scala 20:110]
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wire _T_354 = _T_351 | _T_353; // @[el2_ifu_compress_ctl.scala 296:21]
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wire _T_62 = _T_61 & _T_7; // @[el2_ifu_compress_ctl.scala 20:110]
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wire [6:0] _T_361 = _T_332 ? 7'h13 : 7'h1f; // @[el2_ifu_compress_ctl.scala 290:20]
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wire _T_63 = _T_62 & _T_9; // @[el2_ifu_compress_ctl.scala 20:110]
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wire [2:0] _T_364 = io_din[12] ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
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wire _T_64 = _T_63 & _T_50; // @[el2_ifu_compress_ctl.scala 20:110]
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wire [31:0] _T_379 = {_T_364,io_din[4:3],io_din[5],io_din[2],io_din[6],4'h0,io_din[11:7],3'h0,io_din[11:7],_T_361}; // @[Cat.scala 29:58]
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wire _T_65 = _T_64 & _T_52; // @[el2_ifu_compress_ctl.scala 20:110]
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wire [31:0] _T_386_bits = _T_354 ? _T_379 : _T_343; // @[el2_ifu_compress_ctl.scala 296:10]
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wire _T_66 = _T_65 & _T_54; // @[el2_ifu_compress_ctl.scala 20:110]
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wire [4:0] _T_386_rd = _T_354 ? io_din[11:7] : io_din[11:7]; // @[el2_ifu_compress_ctl.scala 296:10]
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wire out_20 = _T_66 & io_din[1]; // @[el2_ifu_compress_ctl.scala 20:110]
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wire [4:0] _T_386_rs2 = _T_354 ? _T_14 : _T_14; // @[el2_ifu_compress_ctl.scala 296:10]
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wire _T_79 = _T_28 & io_din[0]; // @[el2_ifu_compress_ctl.scala 20:110]
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wire [4:0] _T_386_rs3 = _T_354 ? io_din[31:27] : io_din[31:27]; // @[el2_ifu_compress_ctl.scala 296:10]
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wire _T_90 = _T_12 & _T_38; // @[el2_ifu_compress_ctl.scala 20:110]
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wire [25:0] _T_397 = {io_din[12],io_din[6:2],2'h1,io_din[9:7],3'h5,2'h1,io_din[9:7],7'h13}; // @[Cat.scala 29:58]
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wire _T_91 = _T_90 & io_din[0]; // @[el2_ifu_compress_ctl.scala 20:110]
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wire [30:0] _GEN_184 = {{5'd0}, _T_397}; // @[el2_ifu_compress_ctl.scala 303:23]
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wire _T_92 = _T_79 | _T_91; // @[el2_ifu_compress_ctl.scala 25:46]
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wire [30:0] _T_409 = _GEN_184 | 31'h40000000; // @[el2_ifu_compress_ctl.scala 303:23]
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wire _T_102 = _T_12 & io_din[6]; // @[el2_ifu_compress_ctl.scala 20:110]
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wire [31:0] _T_422 = {_T_211,io_din[6:2],2'h1,io_din[9:7],3'h7,2'h1,io_din[9:7],7'h13}; // @[Cat.scala 29:58]
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wire _T_103 = _T_102 & io_din[0]; // @[el2_ifu_compress_ctl.scala 20:110]
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wire [2:0] _T_426 = {io_din[12],io_din[6:5]}; // @[Cat.scala 29:58]
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wire _T_104 = _T_92 | _T_103; // @[el2_ifu_compress_ctl.scala 25:80]
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wire _T_428 = io_din[6:5] == 2'h0; // @[el2_ifu_compress_ctl.scala 307:30]
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wire _T_114 = _T_12 & io_din[5]; // @[el2_ifu_compress_ctl.scala 20:110]
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wire [30:0] _T_429 = _T_428 ? 31'h40000000 : 31'h0; // @[el2_ifu_compress_ctl.scala 307:22]
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wire _T_115 = _T_114 & io_din[0]; // @[el2_ifu_compress_ctl.scala 20:110]
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wire [6:0] _T_431 = io_din[12] ? 7'h3b : 7'h33; // @[el2_ifu_compress_ctl.scala 308:22]
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wire out_14 = _T_104 | _T_115; // @[el2_ifu_compress_ctl.scala 25:113]
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wire [2:0] _GEN_1 = 3'h1 == _T_426 ? 3'h4 : 3'h0; // @[Cat.scala 29:58]
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wire _T_128 = _T_12 & io_din[11]; // @[el2_ifu_compress_ctl.scala 20:110]
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wire [2:0] _GEN_2 = 3'h2 == _T_426 ? 3'h6 : _GEN_1; // @[Cat.scala 29:58]
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wire _T_129 = _T_128 & _T_38; // @[el2_ifu_compress_ctl.scala 20:110]
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wire [2:0] _GEN_3 = 3'h3 == _T_426 ? 3'h7 : _GEN_2; // @[Cat.scala 29:58]
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wire _T_130 = _T_129 & io_din[0]; // @[el2_ifu_compress_ctl.scala 20:110]
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wire [2:0] _GEN_4 = 3'h4 == _T_426 ? 3'h0 : _GEN_3; // @[Cat.scala 29:58]
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wire _T_142 = _T_128 & io_din[6]; // @[el2_ifu_compress_ctl.scala 20:110]
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wire [2:0] _GEN_5 = 3'h5 == _T_426 ? 3'h0 : _GEN_4; // @[Cat.scala 29:58]
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wire _T_143 = _T_142 & io_din[0]; // @[el2_ifu_compress_ctl.scala 20:110]
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wire [2:0] _GEN_6 = 3'h6 == _T_426 ? 3'h2 : _GEN_5; // @[Cat.scala 29:58]
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wire _T_144 = _T_130 | _T_143; // @[el2_ifu_compress_ctl.scala 27:50]
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wire [2:0] _GEN_7 = 3'h7 == _T_426 ? 3'h3 : _GEN_6; // @[Cat.scala 29:58]
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wire _T_147 = ~io_din[0]; // @[el2_ifu_compress_ctl.scala 27:101]
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wire [24:0] _T_441 = {2'h1,io_din[4:2],2'h1,io_din[9:7],_GEN_7,2'h1,io_din[9:7],_T_431}; // @[Cat.scala 29:58]
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wire _T_148 = io_din[14] & _T_147; // @[el2_ifu_compress_ctl.scala 27:99]
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wire [30:0] _GEN_185 = {{6'd0}, _T_441}; // @[el2_ifu_compress_ctl.scala 309:43]
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wire out_13 = _T_144 | _T_148; // @[el2_ifu_compress_ctl.scala 27:86]
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wire [30:0] _T_442 = _GEN_185 | _T_429; // @[el2_ifu_compress_ctl.scala 309:43]
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wire _T_161 = _T_102 & io_din[5]; // @[el2_ifu_compress_ctl.scala 20:110]
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wire [31:0] _T_443_0 = {{6'd0}, _T_397}; // @[el2_ifu_compress_ctl.scala 311:19 el2_ifu_compress_ctl.scala 311:19]
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wire _T_162 = _T_161 & io_din[0]; // @[el2_ifu_compress_ctl.scala 20:110]
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wire [31:0] _T_443_1 = {{1'd0}, _T_409}; // @[el2_ifu_compress_ctl.scala 311:19 el2_ifu_compress_ctl.scala 311:19]
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wire _T_175 = _T_162 | _T_79; // @[el2_ifu_compress_ctl.scala 28:47]
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wire [31:0] _GEN_9 = 2'h1 == io_din[11:10] ? _T_443_1 : _T_443_0; // @[el2_ifu_compress_ctl.scala 226:14]
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wire _T_188 = _T_175 | _T_91; // @[el2_ifu_compress_ctl.scala 28:81]
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wire [31:0] _GEN_10 = 2'h2 == io_din[11:10] ? _T_422 : _GEN_9; // @[el2_ifu_compress_ctl.scala 226:14]
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wire _T_190 = ~io_din[15]; // @[el2_ifu_compress_ctl.scala 20:83]
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wire [31:0] _T_443_3 = {{1'd0}, _T_442}; // @[el2_ifu_compress_ctl.scala 311:19 el2_ifu_compress_ctl.scala 311:19]
|
wire _T_194 = _T_190 & _T_2; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [31:0] _GEN_11 = 2'h3 == io_din[11:10] ? _T_443_3 : _GEN_10; // @[el2_ifu_compress_ctl.scala 226:14]
|
wire _T_195 = _T_194 & io_din[1]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [31:0] _T_533 = {_T_243[20],_T_243[10:1],_T_243[11],_T_243[19:12],5'h0,7'h6f}; // @[Cat.scala 29:58]
|
wire _T_196 = _T_188 | _T_195; // @[el2_ifu_compress_ctl.scala 28:115]
|
||||||
wire [4:0] _T_542 = io_din[12] ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12]
|
wire _T_200 = io_din[15] & io_din[14]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [12:0] _T_551 = {_T_542,io_din[6:5],io_din[2],io_din[11:10],io_din[4:3],1'h0}; // @[Cat.scala 29:58]
|
wire _T_201 = _T_200 & io_din[13]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [31:0] _T_600 = {_T_551[12],_T_551[10:5],5'h0,2'h1,io_din[9:7],3'h0,_T_551[4:1],_T_551[11],7'h63}; // @[Cat.scala 29:58]
|
wire out_12 = _T_196 | _T_201; // @[el2_ifu_compress_ctl.scala 29:26]
|
||||||
wire [31:0] _T_667 = {_T_551[12],_T_551[10:5],5'h0,2'h1,io_din[9:7],3'h1,_T_551[4:1],_T_551[11],7'h63}; // @[Cat.scala 29:58]
|
wire _T_217 = _T_11 & _T_7; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire _T_673 = |io_din[11:7]; // @[el2_ifu_compress_ctl.scala 317:27]
|
wire _T_218 = _T_217 & _T_9; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [6:0] _T_674 = _T_673 ? 7'h3 : 7'h1f; // @[el2_ifu_compress_ctl.scala 317:23]
|
wire _T_219 = _T_218 & _T_50; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [25:0] _T_683 = {io_din[12],io_din[6:2],io_din[11:7],3'h1,io_din[11:7],7'h13}; // @[Cat.scala 29:58]
|
wire _T_220 = _T_219 & _T_52; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [28:0] _T_699 = {io_din[4:2],io_din[12],io_din[6:5],3'h0,5'h2,3'h3,io_din[11:7],7'h7}; // @[Cat.scala 29:58]
|
wire _T_221 = _T_220 & _T_54; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [27:0] _T_714 = {io_din[3:2],io_din[12],io_din[6:4],2'h0,5'h2,3'h2,io_din[11:7],_T_674}; // @[Cat.scala 29:58]
|
wire _T_224 = _T_221 & _T_147; // @[el2_ifu_compress_ctl.scala 30:53]
|
||||||
wire [27:0] _T_729 = {io_din[3:2],io_din[12],io_din[6:4],2'h0,5'h2,3'h2,io_din[11:7],7'h7}; // @[Cat.scala 29:58]
|
wire _T_228 = _T_2 & io_din[13]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [24:0] _T_739 = {io_din[6:2],5'h0,3'h0,io_din[11:7],7'h33}; // @[Cat.scala 29:58]
|
wire _T_229 = _T_224 | _T_228; // @[el2_ifu_compress_ctl.scala 30:67]
|
||||||
wire [24:0] _T_750 = {io_din[6:2],io_din[11:7],3'h0,io_din[11:7],7'h33}; // @[Cat.scala 29:58]
|
wire _T_234 = _T_200 & io_din[0]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [24:0] _T_761 = {io_din[6:2],io_din[11:7],3'h0,12'h67}; // @[Cat.scala 29:58]
|
wire out_6 = _T_229 | _T_234; // @[el2_ifu_compress_ctl.scala 30:88]
|
||||||
wire [24:0] _T_763 = {_T_761[24:7],7'h1f}; // @[Cat.scala 29:58]
|
wire _T_239 = io_din[15] & _T_147; // @[el2_ifu_compress_ctl.scala 32:24]
|
||||||
wire [24:0] _T_766 = _T_673 ? _T_761 : _T_763; // @[el2_ifu_compress_ctl.scala 338:33]
|
wire _T_243 = io_din[15] & io_din[11]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire _T_772 = |io_din[6:2]; // @[el2_ifu_compress_ctl.scala 339:27]
|
wire _T_244 = _T_243 & io_din[10]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [31:0] _T_743_bits = {{7'd0}, _T_739}; // @[el2_ifu_compress_ctl.scala 225:19 el2_ifu_compress_ctl.scala 226:14]
|
wire _T_245 = _T_239 | _T_244; // @[el2_ifu_compress_ctl.scala 32:39]
|
||||||
wire [31:0] _T_770_bits = {{7'd0}, _T_766}; // @[el2_ifu_compress_ctl.scala 225:19 el2_ifu_compress_ctl.scala 226:14]
|
wire _T_249 = io_din[13] & _T_42; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [31:0] _T_773_bits = _T_772 ? _T_743_bits : _T_770_bits; // @[el2_ifu_compress_ctl.scala 339:22]
|
wire _T_250 = _T_245 | _T_249; // @[el2_ifu_compress_ctl.scala 32:63]
|
||||||
wire [4:0] _T_773_rd = _T_772 ? io_din[11:7] : 5'h0; // @[el2_ifu_compress_ctl.scala 339:22]
|
wire _T_253 = io_din[13] & io_din[7]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _T_773_rs1 = _T_772 ? 5'h0 : io_din[11:7]; // @[el2_ifu_compress_ctl.scala 339:22]
|
wire _T_254 = _T_250 | _T_253; // @[el2_ifu_compress_ctl.scala 32:83]
|
||||||
wire [4:0] _T_773_rs2 = _T_772 ? io_din[6:2] : io_din[6:2]; // @[el2_ifu_compress_ctl.scala 339:22]
|
wire _T_257 = io_din[13] & io_din[9]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _T_773_rs3 = _T_772 ? io_din[31:27] : io_din[31:27]; // @[el2_ifu_compress_ctl.scala 339:22]
|
wire _T_258 = _T_254 | _T_257; // @[el2_ifu_compress_ctl.scala 32:102]
|
||||||
wire [24:0] _T_779 = {io_din[6:2],io_din[11:7],3'h0,12'he7}; // @[Cat.scala 29:58]
|
wire _T_261 = io_din[13] & io_din[10]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [24:0] _T_781 = {_T_761[24:7],7'h73}; // @[Cat.scala 29:58]
|
wire _T_262 = _T_258 | _T_261; // @[el2_ifu_compress_ctl.scala 33:22]
|
||||||
wire [24:0] _T_782 = _T_781 | 25'h100000; // @[el2_ifu_compress_ctl.scala 341:46]
|
wire _T_265 = io_din[13] & io_din[11]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [24:0] _T_785 = _T_673 ? _T_779 : _T_782; // @[el2_ifu_compress_ctl.scala 342:33]
|
wire _T_266 = _T_262 | _T_265; // @[el2_ifu_compress_ctl.scala 33:42]
|
||||||
wire [31:0] _T_755_bits = {{7'd0}, _T_750}; // @[el2_ifu_compress_ctl.scala 225:19 el2_ifu_compress_ctl.scala 226:14]
|
wire _T_271 = _T_266 | _T_228; // @[el2_ifu_compress_ctl.scala 33:62]
|
||||||
wire [31:0] _T_789_bits = {{7'd0}, _T_785}; // @[el2_ifu_compress_ctl.scala 225:19 el2_ifu_compress_ctl.scala 226:14]
|
wire out_5 = _T_271 | _T_200; // @[el2_ifu_compress_ctl.scala 33:83]
|
||||||
wire [31:0] _T_792_bits = _T_772 ? _T_755_bits : _T_789_bits; // @[el2_ifu_compress_ctl.scala 343:25]
|
wire _T_288 = _T_2 & _T_23; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _T_792_rd = _T_772 ? io_din[11:7] : 5'h1; // @[el2_ifu_compress_ctl.scala 343:25]
|
wire _T_289 = _T_288 & _T_38; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _T_792_rs1 = _T_772 ? io_din[11:7] : io_din[11:7]; // @[el2_ifu_compress_ctl.scala 343:25]
|
wire _T_290 = _T_289 & _T_40; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [31:0] _T_794_bits = io_din[12] ? _T_792_bits : _T_773_bits; // @[el2_ifu_compress_ctl.scala 344:10]
|
wire _T_291 = _T_290 & _T_42; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _T_794_rd = io_din[12] ? _T_792_rd : _T_773_rd; // @[el2_ifu_compress_ctl.scala 344:10]
|
wire _T_292 = _T_291 & _T_44; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _T_794_rs1 = io_din[12] ? _T_792_rs1 : _T_773_rs1; // @[el2_ifu_compress_ctl.scala 344:10]
|
wire _T_295 = _T_292 & _T_147; // @[el2_ifu_compress_ctl.scala 36:50]
|
||||||
wire [4:0] _T_794_rs2 = io_din[12] ? _T_773_rs2 : _T_773_rs2; // @[el2_ifu_compress_ctl.scala 344:10]
|
wire _T_303 = _T_194 & _T_147; // @[el2_ifu_compress_ctl.scala 36:87]
|
||||||
wire [4:0] _T_794_rs3 = io_din[12] ? _T_773_rs3 : _T_773_rs3; // @[el2_ifu_compress_ctl.scala 344:10]
|
wire _T_304 = _T_295 | _T_303; // @[el2_ifu_compress_ctl.scala 36:65]
|
||||||
wire [8:0] _T_798 = {io_din[9:7],io_din[12:10],3'h0}; // @[Cat.scala 29:58]
|
wire _T_308 = _T_2 & io_din[6]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [28:0] _T_810 = {_T_798[8:5],io_din[6:2],5'h2,3'h3,_T_798[4:0],7'h27}; // @[Cat.scala 29:58]
|
wire _T_311 = _T_308 & _T_147; // @[el2_ifu_compress_ctl.scala 37:23]
|
||||||
wire [7:0] _T_818 = {io_din[8:7],io_din[12:9],2'h0}; // @[Cat.scala 29:58]
|
wire _T_312 = _T_304 | _T_311; // @[el2_ifu_compress_ctl.scala 36:102]
|
||||||
wire [27:0] _T_830 = {_T_818[7:5],io_din[6:2],5'h2,3'h2,_T_818[4:0],7'h23}; // @[Cat.scala 29:58]
|
wire _T_317 = _T_190 & io_din[14]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [27:0] _T_850 = {_T_818[7:5],io_din[6:2],5'h2,3'h2,_T_818[4:0],7'h27}; // @[Cat.scala 29:58]
|
wire _T_318 = _T_317 & io_din[0]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _T_898 = {io_din[1:0],io_din[15:13]}; // @[Cat.scala 29:58]
|
wire _T_319 = _T_312 | _T_318; // @[el2_ifu_compress_ctl.scala 37:38]
|
||||||
wire [31:0] _T_921_bits = {{2'd0}, _T_18}; // @[el2_ifu_compress_ctl.scala 225:19 el2_ifu_compress_ctl.scala 226:14]
|
wire _T_323 = _T_2 & io_din[5]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [31:0] _T_941_bits = {{4'd0}, _T_36}; // @[el2_ifu_compress_ctl.scala 225:19 el2_ifu_compress_ctl.scala 226:14]
|
wire _T_326 = _T_323 & _T_147; // @[el2_ifu_compress_ctl.scala 37:82]
|
||||||
wire [31:0] _GEN_29 = 5'h1 == _T_898 ? _T_941_bits : _T_921_bits; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_327 = _T_319 | _T_326; // @[el2_ifu_compress_ctl.scala 37:62]
|
||||||
wire [4:0] _GEN_30 = 5'h1 == _T_898 ? _T_14 : _T_14; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_331 = _T_2 & io_din[4]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_31 = 5'h1 == _T_898 ? _T_30 : 5'h2; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_334 = _T_331 & _T_147; // @[el2_ifu_compress_ctl.scala 38:23]
|
||||||
wire [4:0] _GEN_33 = 5'h1 == _T_898 ? io_din[31:27] : io_din[31:27]; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_335 = _T_327 | _T_334; // @[el2_ifu_compress_ctl.scala 37:97]
|
||||||
wire [31:0] _T_963_bits = {{5'd0}, _T_58}; // @[el2_ifu_compress_ctl.scala 225:19 el2_ifu_compress_ctl.scala 226:14]
|
wire _T_339 = _T_2 & io_din[3]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [31:0] _GEN_34 = 5'h2 == _T_898 ? _T_963_bits : _GEN_29; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_342 = _T_339 & _T_147; // @[el2_ifu_compress_ctl.scala 38:58]
|
||||||
wire [4:0] _GEN_35 = 5'h2 == _T_898 ? _T_14 : _GEN_30; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_343 = _T_335 | _T_342; // @[el2_ifu_compress_ctl.scala 38:38]
|
||||||
wire [4:0] _GEN_36 = 5'h2 == _T_898 ? _T_30 : _GEN_31; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_347 = _T_2 & io_din[2]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_38 = 5'h2 == _T_898 ? io_din[31:27] : _GEN_33; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_350 = _T_347 & _T_147; // @[el2_ifu_compress_ctl.scala 38:93]
|
||||||
wire [31:0] _T_985_bits = {{5'd0}, _T_80}; // @[el2_ifu_compress_ctl.scala 225:19 el2_ifu_compress_ctl.scala 226:14]
|
wire _T_351 = _T_343 | _T_350; // @[el2_ifu_compress_ctl.scala 38:73]
|
||||||
wire [31:0] _GEN_39 = 5'h3 == _T_898 ? _T_985_bits : _GEN_34; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_357 = _T_2 & _T_4; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_40 = 5'h3 == _T_898 ? _T_14 : _GEN_35; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_358 = _T_357 & io_din[0]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_41 = 5'h3 == _T_898 ? _T_30 : _GEN_36; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire out_4 = _T_351 | _T_358; // @[el2_ifu_compress_ctl.scala 38:108]
|
||||||
wire [4:0] _GEN_43 = 5'h3 == _T_898 ? io_din[31:27] : _GEN_38; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_380 = _T_56 & io_din[11]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [31:0] _T_1016_bits = {{5'd0}, _T_111}; // @[el2_ifu_compress_ctl.scala 225:19 el2_ifu_compress_ctl.scala 226:14]
|
wire _T_381 = _T_380 & _T_7; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [31:0] _GEN_44 = 5'h4 == _T_898 ? _T_1016_bits : _GEN_39; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_382 = _T_381 & _T_9; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_45 = 5'h4 == _T_898 ? _T_14 : _GEN_40; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_383 = _T_382 & _T_50; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_46 = 5'h4 == _T_898 ? _T_30 : _GEN_41; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_384 = _T_383 & _T_52; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_48 = 5'h4 == _T_898 ? io_din[31:27] : _GEN_43; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_385 = _T_384 & _T_54; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [31:0] _T_1043_bits = {{4'd0}, _T_138}; // @[el2_ifu_compress_ctl.scala 225:19 el2_ifu_compress_ctl.scala 226:14]
|
wire _T_386 = _T_385 & io_din[1]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [31:0] _GEN_49 = 5'h5 == _T_898 ? _T_1043_bits : _GEN_44; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_403 = _T_56 & io_din[10]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_50 = 5'h5 == _T_898 ? _T_14 : _GEN_45; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_404 = _T_403 & _T_7; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_51 = 5'h5 == _T_898 ? _T_30 : _GEN_46; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_405 = _T_404 & _T_9; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_53 = 5'h5 == _T_898 ? io_din[31:27] : _GEN_48; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_406 = _T_405 & _T_50; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [31:0] _T_1074_bits = {{5'd0}, _T_169}; // @[el2_ifu_compress_ctl.scala 225:19 el2_ifu_compress_ctl.scala 226:14]
|
wire _T_407 = _T_406 & _T_52; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [31:0] _GEN_54 = 5'h6 == _T_898 ? _T_1074_bits : _GEN_49; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_408 = _T_407 & _T_54; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_55 = 5'h6 == _T_898 ? _T_14 : _GEN_50; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_409 = _T_408 & io_din[1]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_56 = 5'h6 == _T_898 ? _T_30 : _GEN_51; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_410 = _T_386 | _T_409; // @[el2_ifu_compress_ctl.scala 45:59]
|
||||||
wire [4:0] _GEN_58 = 5'h6 == _T_898 ? io_din[31:27] : _GEN_53; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_427 = _T_56 & io_din[9]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [31:0] _T_1105_bits = {{5'd0}, _T_200}; // @[el2_ifu_compress_ctl.scala 225:19 el2_ifu_compress_ctl.scala 226:14]
|
wire _T_428 = _T_427 & _T_7; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [31:0] _GEN_59 = 5'h7 == _T_898 ? _T_1105_bits : _GEN_54; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_429 = _T_428 & _T_9; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_60 = 5'h7 == _T_898 ? _T_14 : _GEN_55; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_430 = _T_429 & _T_50; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_61 = 5'h7 == _T_898 ? _T_30 : _GEN_56; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_431 = _T_430 & _T_52; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_63 = 5'h7 == _T_898 ? io_din[31:27] : _GEN_58; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_432 = _T_431 & _T_54; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [31:0] _GEN_64 = 5'h8 == _T_898 ? _T_219 : _GEN_59; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_433 = _T_432 & io_din[1]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_65 = 5'h8 == _T_898 ? io_din[11:7] : _GEN_60; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_434 = _T_410 | _T_433; // @[el2_ifu_compress_ctl.scala 46:59]
|
||||||
wire [4:0] _GEN_66 = 5'h8 == _T_898 ? io_din[11:7] : _GEN_61; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_451 = _T_56 & io_din[8]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_67 = 5'h8 == _T_898 ? _T_14 : _GEN_60; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_452 = _T_451 & _T_7; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_68 = 5'h8 == _T_898 ? io_din[31:27] : _GEN_63; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_453 = _T_452 & _T_9; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [31:0] _GEN_69 = 5'h9 == _T_898 ? _T_306 : _GEN_64; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_454 = _T_453 & _T_50; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_70 = 5'h9 == _T_898 ? 5'h1 : _GEN_65; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_455 = _T_454 & _T_52; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_71 = 5'h9 == _T_898 ? io_din[11:7] : _GEN_66; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_456 = _T_455 & _T_54; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_72 = 5'h9 == _T_898 ? _T_14 : _GEN_67; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_457 = _T_456 & io_din[1]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_73 = 5'h9 == _T_898 ? io_din[31:27] : _GEN_68; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_458 = _T_434 | _T_457; // @[el2_ifu_compress_ctl.scala 47:58]
|
||||||
wire [31:0] _GEN_74 = 5'ha == _T_898 ? _T_321 : _GEN_69; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_475 = _T_56 & io_din[7]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_75 = 5'ha == _T_898 ? io_din[11:7] : _GEN_70; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_476 = _T_475 & _T_7; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_76 = 5'ha == _T_898 ? 5'h0 : _GEN_71; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_477 = _T_476 & _T_9; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_77 = 5'ha == _T_898 ? _T_14 : _GEN_72; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_478 = _T_477 & _T_50; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_78 = 5'ha == _T_898 ? io_din[31:27] : _GEN_73; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_479 = _T_478 & _T_52; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [31:0] _GEN_79 = 5'hb == _T_898 ? _T_386_bits : _GEN_74; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_480 = _T_479 & _T_54; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_80 = 5'hb == _T_898 ? _T_386_rd : _GEN_75; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_481 = _T_480 & io_din[1]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_81 = 5'hb == _T_898 ? _T_386_rd : _GEN_76; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_482 = _T_458 | _T_481; // @[el2_ifu_compress_ctl.scala 48:55]
|
||||||
wire [4:0] _GEN_82 = 5'hb == _T_898 ? _T_386_rs2 : _GEN_77; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_487 = ~io_din[12]; // @[el2_ifu_compress_ctl.scala 20:83]
|
||||||
wire [4:0] _GEN_83 = 5'hb == _T_898 ? _T_386_rs3 : _GEN_78; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_499 = _T_11 & _T_487; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [31:0] _GEN_84 = 5'hc == _T_898 ? _GEN_11 : _GEN_79; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_500 = _T_499 & _T_7; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_85 = 5'hc == _T_898 ? _T_30 : _GEN_80; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_501 = _T_500 & _T_9; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_86 = 5'hc == _T_898 ? _T_30 : _GEN_81; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_502 = _T_501 & _T_50; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_87 = 5'hc == _T_898 ? _T_14 : _GEN_82; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_503 = _T_502 & _T_52; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_88 = 5'hc == _T_898 ? io_din[31:27] : _GEN_83; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_504 = _T_503 & _T_54; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [31:0] _GEN_89 = 5'hd == _T_898 ? _T_533 : _GEN_84; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_507 = _T_504 & _T_147; // @[el2_ifu_compress_ctl.scala 50:56]
|
||||||
wire [4:0] _GEN_90 = 5'hd == _T_898 ? 5'h0 : _GEN_85; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_508 = _T_482 | _T_507; // @[el2_ifu_compress_ctl.scala 49:57]
|
||||||
wire [4:0] _GEN_91 = 5'hd == _T_898 ? _T_30 : _GEN_86; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_514 = _T_190 & io_din[13]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_92 = 5'hd == _T_898 ? _T_14 : _GEN_87; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_515 = _T_514 & _T_42; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_93 = 5'hd == _T_898 ? io_din[31:27] : _GEN_88; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_516 = _T_508 | _T_515; // @[el2_ifu_compress_ctl.scala 50:71]
|
||||||
wire [31:0] _GEN_94 = 5'he == _T_898 ? _T_600 : _GEN_89; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_522 = _T_514 & io_din[7]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_95 = 5'he == _T_898 ? _T_30 : _GEN_90; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_523 = _T_516 | _T_522; // @[el2_ifu_compress_ctl.scala 51:34]
|
||||||
wire [4:0] _GEN_96 = 5'he == _T_898 ? _T_30 : _GEN_91; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_529 = _T_514 & io_din[9]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_97 = 5'he == _T_898 ? 5'h0 : _GEN_92; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_530 = _T_523 | _T_529; // @[el2_ifu_compress_ctl.scala 52:33]
|
||||||
wire [4:0] _GEN_98 = 5'he == _T_898 ? io_din[31:27] : _GEN_93; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_536 = _T_514 & io_din[10]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [31:0] _GEN_99 = 5'hf == _T_898 ? _T_667 : _GEN_94; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_537 = _T_530 | _T_536; // @[el2_ifu_compress_ctl.scala 53:33]
|
||||||
wire [4:0] _GEN_100 = 5'hf == _T_898 ? 5'h0 : _GEN_95; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_543 = _T_514 & io_din[11]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_101 = 5'hf == _T_898 ? _T_30 : _GEN_96; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_544 = _T_537 | _T_543; // @[el2_ifu_compress_ctl.scala 54:34]
|
||||||
wire [4:0] _GEN_102 = 5'hf == _T_898 ? 5'h0 : _GEN_97; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire out_2 = _T_544 | _T_228; // @[el2_ifu_compress_ctl.scala 55:34]
|
||||||
wire [4:0] _GEN_103 = 5'hf == _T_898 ? io_din[31:27] : _GEN_98; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire [4:0] rs2d = io_din[6:2]; // @[el2_ifu_compress_ctl.scala 64:20]
|
||||||
wire [31:0] _T_1585_bits = {{6'd0}, _T_683}; // @[el2_ifu_compress_ctl.scala 225:19 el2_ifu_compress_ctl.scala 226:14]
|
wire [4:0] rdd = io_din[11:7]; // @[el2_ifu_compress_ctl.scala 65:19]
|
||||||
wire [31:0] _GEN_104 = 5'h10 == _T_898 ? _T_1585_bits : _GEN_99; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire [4:0] rdpd = {2'h1,io_din[9:7]}; // @[Cat.scala 29:58]
|
||||||
wire [4:0] _GEN_105 = 5'h10 == _T_898 ? io_din[11:7] : _GEN_100; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire [4:0] rs2pd = {2'h1,io_din[4:2]}; // @[Cat.scala 29:58]
|
||||||
wire [4:0] _GEN_106 = 5'h10 == _T_898 ? io_din[11:7] : _GEN_101; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_557 = _T_308 & io_din[1]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_107 = 5'h10 == _T_898 ? io_din[6:2] : _GEN_102; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_564 = _T_317 & io_din[11]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_108 = 5'h10 == _T_898 ? io_din[31:27] : _GEN_103; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_565 = _T_564 & io_din[0]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [31:0] _T_1600_bits = {{3'd0}, _T_699}; // @[el2_ifu_compress_ctl.scala 225:19 el2_ifu_compress_ctl.scala 226:14]
|
wire _T_566 = _T_557 | _T_565; // @[el2_ifu_compress_ctl.scala 69:33]
|
||||||
wire [31:0] _GEN_109 = 5'h11 == _T_898 ? _T_1600_bits : _GEN_104; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_572 = _T_323 & io_din[1]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_110 = 5'h11 == _T_898 ? io_din[11:7] : _GEN_105; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_573 = _T_566 | _T_572; // @[el2_ifu_compress_ctl.scala 69:58]
|
||||||
wire [4:0] _GEN_111 = 5'h11 == _T_898 ? 5'h2 : _GEN_106; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_580 = _T_317 & io_din[10]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_112 = 5'h11 == _T_898 ? io_din[6:2] : _GEN_107; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_581 = _T_580 & io_din[0]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_113 = 5'h11 == _T_898 ? io_din[31:27] : _GEN_108; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_582 = _T_573 | _T_581; // @[el2_ifu_compress_ctl.scala 69:79]
|
||||||
wire [31:0] _T_1615_bits = {{4'd0}, _T_714}; // @[el2_ifu_compress_ctl.scala 225:19 el2_ifu_compress_ctl.scala 226:14]
|
wire _T_588 = _T_331 & io_din[1]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [31:0] _GEN_114 = 5'h12 == _T_898 ? _T_1615_bits : _GEN_109; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_589 = _T_582 | _T_588; // @[el2_ifu_compress_ctl.scala 69:104]
|
||||||
wire [4:0] _GEN_115 = 5'h12 == _T_898 ? io_din[11:7] : _GEN_110; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_596 = _T_317 & io_din[9]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_116 = 5'h12 == _T_898 ? 5'h2 : _GEN_111; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_597 = _T_596 & io_din[0]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_117 = 5'h12 == _T_898 ? io_din[6:2] : _GEN_112; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_598 = _T_589 | _T_597; // @[el2_ifu_compress_ctl.scala 70:24]
|
||||||
wire [4:0] _GEN_118 = 5'h12 == _T_898 ? io_din[31:27] : _GEN_113; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_604 = _T_339 & io_din[1]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [31:0] _T_1630_bits = {{4'd0}, _T_729}; // @[el2_ifu_compress_ctl.scala 225:19 el2_ifu_compress_ctl.scala 226:14]
|
wire _T_605 = _T_598 | _T_604; // @[el2_ifu_compress_ctl.scala 70:48]
|
||||||
wire [31:0] _GEN_119 = 5'h13 == _T_898 ? _T_1630_bits : _GEN_114; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_613 = _T_317 & _T_42; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_120 = 5'h13 == _T_898 ? io_din[11:7] : _GEN_115; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_614 = _T_613 & io_din[0]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_121 = 5'h13 == _T_898 ? 5'h2 : _GEN_116; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_615 = _T_605 | _T_614; // @[el2_ifu_compress_ctl.scala 70:69]
|
||||||
wire [4:0] _GEN_122 = 5'h13 == _T_898 ? io_din[6:2] : _GEN_117; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_621 = _T_347 & io_din[1]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_123 = 5'h13 == _T_898 ? io_din[31:27] : _GEN_118; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_622 = _T_615 | _T_621; // @[el2_ifu_compress_ctl.scala 70:94]
|
||||||
wire [31:0] _GEN_124 = 5'h14 == _T_898 ? _T_794_bits : _GEN_119; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_629 = _T_317 & io_din[7]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_125 = 5'h14 == _T_898 ? _T_794_rd : _GEN_120; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_630 = _T_629 & io_din[0]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_126 = 5'h14 == _T_898 ? _T_794_rs1 : _GEN_121; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_631 = _T_622 | _T_630; // @[el2_ifu_compress_ctl.scala 71:22]
|
||||||
wire [4:0] _GEN_127 = 5'h14 == _T_898 ? _T_794_rs2 : _GEN_122; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_635 = _T_190 & io_din[1]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_128 = 5'h14 == _T_898 ? _T_794_rs3 : _GEN_123; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_636 = _T_631 | _T_635; // @[el2_ifu_compress_ctl.scala 71:46]
|
||||||
wire [31:0] _T_1711_bits = {{3'd0}, _T_810}; // @[el2_ifu_compress_ctl.scala 225:19 el2_ifu_compress_ctl.scala 226:14]
|
wire _T_642 = _T_190 & _T_4; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [31:0] _GEN_129 = 5'h15 == _T_898 ? _T_1711_bits : _GEN_124; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_643 = _T_642 & io_din[0]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_130 = 5'h15 == _T_898 ? io_din[11:7] : _GEN_125; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire rdrd = _T_636 | _T_643; // @[el2_ifu_compress_ctl.scala 71:65]
|
||||||
wire [4:0] _GEN_131 = 5'h15 == _T_898 ? 5'h2 : _GEN_126; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_651 = _T_380 & io_din[1]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_132 = 5'h15 == _T_898 ? io_din[6:2] : _GEN_127; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_659 = _T_403 & io_din[1]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_133 = 5'h15 == _T_898 ? io_din[31:27] : _GEN_128; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_660 = _T_651 | _T_659; // @[el2_ifu_compress_ctl.scala 73:38]
|
||||||
wire [31:0] _T_1731_bits = {{4'd0}, _T_830}; // @[el2_ifu_compress_ctl.scala 225:19 el2_ifu_compress_ctl.scala 226:14]
|
wire _T_668 = _T_427 & io_din[1]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [31:0] _GEN_134 = 5'h16 == _T_898 ? _T_1731_bits : _GEN_129; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_669 = _T_660 | _T_668; // @[el2_ifu_compress_ctl.scala 74:28]
|
||||||
wire [4:0] _GEN_135 = 5'h16 == _T_898 ? io_din[11:7] : _GEN_130; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_677 = _T_451 & io_din[1]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_136 = 5'h16 == _T_898 ? 5'h2 : _GEN_131; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_678 = _T_669 | _T_677; // @[el2_ifu_compress_ctl.scala 75:27]
|
||||||
wire [4:0] _GEN_137 = 5'h16 == _T_898 ? io_din[6:2] : _GEN_132; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_686 = _T_475 & io_din[1]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_138 = 5'h16 == _T_898 ? io_din[31:27] : _GEN_133; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_687 = _T_678 | _T_686; // @[el2_ifu_compress_ctl.scala 76:27]
|
||||||
wire [31:0] _T_1751_bits = {{4'd0}, _T_850}; // @[el2_ifu_compress_ctl.scala 225:19 el2_ifu_compress_ctl.scala 226:14]
|
wire _T_703 = _T_2 & _T_487; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [31:0] _GEN_139 = 5'h17 == _T_898 ? _T_1751_bits : _GEN_134; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_704 = _T_703 & _T_7; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_140 = 5'h17 == _T_898 ? io_din[11:7] : _GEN_135; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_705 = _T_704 & _T_9; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_141 = 5'h17 == _T_898 ? 5'h2 : _GEN_136; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_706 = _T_705 & _T_50; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_142 = 5'h17 == _T_898 ? io_din[6:2] : _GEN_137; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_707 = _T_706 & _T_52; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_143 = 5'h17 == _T_898 ? io_din[31:27] : _GEN_138; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_708 = _T_707 & _T_54; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [31:0] _GEN_144 = 5'h18 == _T_898 ? io_din : _GEN_139; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_709 = _T_708 & io_din[1]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_145 = 5'h18 == _T_898 ? io_din[11:7] : _GEN_140; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_710 = _T_687 | _T_709; // @[el2_ifu_compress_ctl.scala 77:27]
|
||||||
wire [4:0] _GEN_146 = 5'h18 == _T_898 ? io_din[19:15] : _GEN_141; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_717 = _T_56 & io_din[6]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_147 = 5'h18 == _T_898 ? io_din[24:20] : _GEN_142; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_718 = _T_717 & io_din[1]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_148 = 5'h18 == _T_898 ? io_din[31:27] : _GEN_143; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_719 = _T_710 | _T_718; // @[el2_ifu_compress_ctl.scala 78:41]
|
||||||
wire [31:0] _GEN_149 = 5'h19 == _T_898 ? io_din : _GEN_144; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_726 = _T_56 & io_din[5]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_150 = 5'h19 == _T_898 ? io_din[11:7] : _GEN_145; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_727 = _T_726 & io_din[1]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_151 = 5'h19 == _T_898 ? io_din[19:15] : _GEN_146; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_728 = _T_719 | _T_727; // @[el2_ifu_compress_ctl.scala 79:27]
|
||||||
wire [4:0] _GEN_152 = 5'h19 == _T_898 ? io_din[24:20] : _GEN_147; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_735 = _T_56 & io_din[4]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_153 = 5'h19 == _T_898 ? io_din[31:27] : _GEN_148; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_736 = _T_735 & io_din[1]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [31:0] _GEN_154 = 5'h1a == _T_898 ? io_din : _GEN_149; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_737 = _T_728 | _T_736; // @[el2_ifu_compress_ctl.scala 80:27]
|
||||||
wire [4:0] _GEN_155 = 5'h1a == _T_898 ? io_din[11:7] : _GEN_150; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_744 = _T_56 & io_din[3]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_156 = 5'h1a == _T_898 ? io_din[19:15] : _GEN_151; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_745 = _T_744 & io_din[1]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_157 = 5'h1a == _T_898 ? io_din[24:20] : _GEN_152; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_746 = _T_737 | _T_745; // @[el2_ifu_compress_ctl.scala 81:27]
|
||||||
wire [4:0] _GEN_158 = 5'h1a == _T_898 ? io_din[31:27] : _GEN_153; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_753 = _T_56 & io_din[2]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [31:0] _GEN_159 = 5'h1b == _T_898 ? io_din : _GEN_154; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_754 = _T_753 & io_din[1]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_160 = 5'h1b == _T_898 ? io_din[11:7] : _GEN_155; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_755 = _T_746 | _T_754; // @[el2_ifu_compress_ctl.scala 82:27]
|
||||||
wire [4:0] _GEN_161 = 5'h1b == _T_898 ? io_din[19:15] : _GEN_156; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_764 = _T_194 & _T_4; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_162 = 5'h1b == _T_898 ? io_din[24:20] : _GEN_157; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_765 = _T_764 & io_din[0]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_163 = 5'h1b == _T_898 ? io_din[31:27] : _GEN_158; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_766 = _T_755 | _T_765; // @[el2_ifu_compress_ctl.scala 83:27]
|
||||||
wire [31:0] _GEN_164 = 5'h1c == _T_898 ? io_din : _GEN_159; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire rdrs1 = _T_766 | _T_195; // @[el2_ifu_compress_ctl.scala 84:30]
|
||||||
wire [4:0] _GEN_165 = 5'h1c == _T_898 ? io_din[11:7] : _GEN_160; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_777 = io_din[15] & io_din[6]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_166 = 5'h1c == _T_898 ? io_din[19:15] : _GEN_161; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_778 = _T_777 & io_din[1]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_167 = 5'h1c == _T_898 ? io_din[24:20] : _GEN_162; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_782 = io_din[15] & io_din[5]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_168 = 5'h1c == _T_898 ? io_din[31:27] : _GEN_163; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_783 = _T_782 & io_din[1]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [31:0] _GEN_169 = 5'h1d == _T_898 ? io_din : _GEN_164; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_784 = _T_778 | _T_783; // @[el2_ifu_compress_ctl.scala 87:34]
|
||||||
wire [4:0] _GEN_170 = 5'h1d == _T_898 ? io_din[11:7] : _GEN_165; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_788 = io_din[15] & io_din[4]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_171 = 5'h1d == _T_898 ? io_din[19:15] : _GEN_166; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_789 = _T_788 & io_din[1]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_172 = 5'h1d == _T_898 ? io_din[24:20] : _GEN_167; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_790 = _T_784 | _T_789; // @[el2_ifu_compress_ctl.scala 87:54]
|
||||||
wire [4:0] _GEN_173 = 5'h1d == _T_898 ? io_din[31:27] : _GEN_168; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_794 = io_din[15] & io_din[3]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [31:0] _GEN_174 = 5'h1e == _T_898 ? io_din : _GEN_169; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_795 = _T_794 & io_din[1]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_175 = 5'h1e == _T_898 ? io_din[11:7] : _GEN_170; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_796 = _T_790 | _T_795; // @[el2_ifu_compress_ctl.scala 87:74]
|
||||||
wire [4:0] _GEN_176 = 5'h1e == _T_898 ? io_din[19:15] : _GEN_171; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_800 = io_din[15] & io_din[2]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_177 = 5'h1e == _T_898 ? io_din[24:20] : _GEN_172; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_801 = _T_800 & io_din[1]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
wire [4:0] _GEN_178 = 5'h1e == _T_898 ? io_din[31:27] : _GEN_173; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_802 = _T_796 | _T_801; // @[el2_ifu_compress_ctl.scala 87:94]
|
||||||
assign io_dout_bits = 5'h1f == _T_898 ? io_din : _GEN_174; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_807 = _T_200 & io_din[1]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
assign io_dout_rd = 5'h1f == _T_898 ? io_din[11:7] : _GEN_175; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire rs2rs2 = _T_802 | _T_807; // @[el2_ifu_compress_ctl.scala 87:114]
|
||||||
assign io_dout_rs1 = 5'h1f == _T_898 ? io_din[19:15] : _GEN_176; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire rdprd = _T_12 & io_din[0]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
assign io_dout_rs2 = 5'h1f == _T_898 ? io_din[24:20] : _GEN_177; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_820 = io_din[15] & _T_4; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
assign io_dout_rs3 = 5'h1f == _T_898 ? io_din[31:27] : _GEN_178; // @[el2_ifu_compress_ctl.scala 404:13]
|
wire _T_821 = _T_820 & io_din[0]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_827 = _T_821 | _T_234; // @[el2_ifu_compress_ctl.scala 91:36]
|
||||||
|
wire _T_830 = ~io_din[1]; // @[el2_ifu_compress_ctl.scala 20:83]
|
||||||
|
wire _T_831 = io_din[14] & _T_830; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_834 = _T_831 & _T_147; // @[el2_ifu_compress_ctl.scala 91:76]
|
||||||
|
wire rdprs1 = _T_827 | _T_834; // @[el2_ifu_compress_ctl.scala 91:57]
|
||||||
|
wire _T_846 = _T_128 & io_din[10]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_847 = _T_846 & io_din[0]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_851 = io_din[15] & _T_830; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_854 = _T_851 & _T_147; // @[el2_ifu_compress_ctl.scala 93:66]
|
||||||
|
wire rs2prs2 = _T_847 | _T_854; // @[el2_ifu_compress_ctl.scala 93:47]
|
||||||
|
wire _T_859 = _T_190 & _T_830; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire rs2prd = _T_859 & _T_147; // @[el2_ifu_compress_ctl.scala 94:33]
|
||||||
|
wire _T_866 = _T_2 & _T_830; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire uimm9_2 = _T_866 & _T_147; // @[el2_ifu_compress_ctl.scala 95:34]
|
||||||
|
wire _T_875 = _T_317 & _T_830; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire ulwimm6_2 = _T_875 & _T_147; // @[el2_ifu_compress_ctl.scala 96:39]
|
||||||
|
wire ulwspimm7_2 = _T_317 & io_din[1]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_897 = _T_317 & io_din[13]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_898 = _T_897 & _T_23; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_899 = _T_898 & _T_38; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_900 = _T_899 & _T_40; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_901 = _T_900 & io_din[8]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire rdeq2 = _T_901 & _T_44; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1027 = _T_194 & io_din[13]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire rdeq1 = _T_482 | _T_1027; // @[el2_ifu_compress_ctl.scala 101:42]
|
||||||
|
wire _T_1050 = io_din[14] & io_din[1]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1051 = rdeq2 | _T_1050; // @[el2_ifu_compress_ctl.scala 102:53]
|
||||||
|
wire rs1eq2 = _T_1051 | uimm9_2; // @[el2_ifu_compress_ctl.scala 102:71]
|
||||||
|
wire _T_1092 = _T_357 & io_din[11]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1093 = _T_1092 & _T_38; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1094 = _T_1093 & io_din[0]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire simm5_0 = _T_1094 | _T_643; // @[el2_ifu_compress_ctl.scala 105:45]
|
||||||
|
wire _T_1112 = _T_897 & io_din[7]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1121 = _T_897 & _T_42; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1122 = _T_1112 | _T_1121; // @[el2_ifu_compress_ctl.scala 107:44]
|
||||||
|
wire _T_1130 = _T_897 & io_din[9]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1131 = _T_1122 | _T_1130; // @[el2_ifu_compress_ctl.scala 108:29]
|
||||||
|
wire _T_1139 = _T_897 & io_din[10]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1140 = _T_1131 | _T_1139; // @[el2_ifu_compress_ctl.scala 109:28]
|
||||||
|
wire _T_1148 = _T_897 & io_din[11]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire sluimm17_12 = _T_1140 | _T_1148; // @[el2_ifu_compress_ctl.scala 110:29]
|
||||||
|
wire uimm5_0 = _T_79 | _T_195; // @[el2_ifu_compress_ctl.scala 112:45]
|
||||||
|
wire [6:0] l1_6 = {out_6,out_5,out_4,_T_228,out_2,1'h1,1'h1}; // @[Cat.scala 29:58]
|
||||||
|
wire [4:0] _T_1192 = rdrd ? rdd : 5'h0; // @[Mux.scala 27:72]
|
||||||
|
wire [4:0] _T_1193 = rdprd ? rdpd : 5'h0; // @[Mux.scala 27:72]
|
||||||
|
wire [4:0] _T_1194 = rs2prd ? rs2pd : 5'h0; // @[Mux.scala 27:72]
|
||||||
|
wire [4:0] _T_1195 = rdeq1 ? 5'h1 : 5'h0; // @[Mux.scala 27:72]
|
||||||
|
wire [4:0] _T_1196 = rdeq2 ? 5'h2 : 5'h0; // @[Mux.scala 27:72]
|
||||||
|
wire [4:0] _T_1197 = _T_1192 | _T_1193; // @[Mux.scala 27:72]
|
||||||
|
wire [4:0] _T_1198 = _T_1197 | _T_1194; // @[Mux.scala 27:72]
|
||||||
|
wire [4:0] _T_1199 = _T_1198 | _T_1195; // @[Mux.scala 27:72]
|
||||||
|
wire [4:0] l1_11 = _T_1199 | _T_1196; // @[Mux.scala 27:72]
|
||||||
|
wire [4:0] _T_1210 = rdrs1 ? rdd : 5'h0; // @[Mux.scala 27:72]
|
||||||
|
wire [4:0] _T_1211 = rdprs1 ? rdpd : 5'h0; // @[Mux.scala 27:72]
|
||||||
|
wire [4:0] _T_1212 = rs1eq2 ? 5'h2 : 5'h0; // @[Mux.scala 27:72]
|
||||||
|
wire [4:0] _T_1213 = _T_1210 | _T_1211; // @[Mux.scala 27:72]
|
||||||
|
wire [4:0] l1_19 = _T_1213 | _T_1212; // @[Mux.scala 27:72]
|
||||||
|
wire [4:0] _T_1219 = {3'h0,1'h0,out_20}; // @[Cat.scala 29:58]
|
||||||
|
wire [4:0] _T_1222 = rs2rs2 ? rs2d : 5'h0; // @[Mux.scala 27:72]
|
||||||
|
wire [4:0] _T_1223 = rs2prs2 ? rs2pd : 5'h0; // @[Mux.scala 27:72]
|
||||||
|
wire [4:0] _T_1224 = _T_1222 | _T_1223; // @[Mux.scala 27:72]
|
||||||
|
wire [4:0] l1_24 = _T_1219 | _T_1224; // @[el2_ifu_compress_ctl.scala 125:67]
|
||||||
|
wire [14:0] _T_1232 = {out_14,out_13,out_12,l1_11,l1_6}; // @[Cat.scala 29:58]
|
||||||
|
wire [16:0] _T_1234 = {1'h0,out_30,2'h0,3'h0,l1_24,l1_19}; // @[Cat.scala 29:58]
|
||||||
|
wire [31:0] l1 = {1'h0,out_30,2'h0,3'h0,l1_24,l1_19,_T_1232}; // @[Cat.scala 29:58]
|
||||||
|
wire [5:0] simm5d = {io_din[12],rs2d}; // @[Cat.scala 29:58]
|
||||||
|
wire [5:0] simm9d = {io_din[12],io_din[4:3],io_din[5],io_din[2],io_din[6]}; // @[Cat.scala 29:58]
|
||||||
|
wire [8:0] sjald_12 = io_din[12] ? 9'h1ff : 9'h0; // @[Bitwise.scala 72:12]
|
||||||
|
wire [19:0] sjald = {sjald_12,io_din[12],io_din[8],io_din[10:9],io_din[6],io_din[7],io_din[2],io_din[11],io_din[5:4],io_din[3]}; // @[Cat.scala 29:58]
|
||||||
|
wire [14:0] _T_1281 = io_din[12] ? 15'h7fff : 15'h0; // @[Bitwise.scala 72:12]
|
||||||
|
wire [19:0] sluimmd = {_T_1281,rs2d}; // @[Cat.scala 29:58]
|
||||||
|
wire [6:0] _T_1287 = simm5d[5] ? 7'h7f : 7'h0; // @[Bitwise.scala 72:12]
|
||||||
|
wire [11:0] _T_1289 = {_T_1287,simm5d[4:0]}; // @[Cat.scala 29:58]
|
||||||
|
wire [11:0] _T_1292 = {2'h0,io_din[10:7],io_din[12:11],io_din[5],io_din[6],2'h0}; // @[Cat.scala 29:58]
|
||||||
|
wire [2:0] _T_1296 = simm9d[5] ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
|
||||||
|
wire [11:0] _T_1299 = {_T_1296,simm9d[4:0],4'h0}; // @[Cat.scala 29:58]
|
||||||
|
wire [11:0] _T_1302 = {5'h0,io_din[5],io_din[12:10],io_din[6],2'h0}; // @[Cat.scala 29:58]
|
||||||
|
wire [11:0] _T_1305 = {4'h0,io_din[3:2],io_din[12],io_din[6:4],2'h0}; // @[Cat.scala 29:58]
|
||||||
|
wire [11:0] _T_1307 = {6'h0,io_din[12],rs2d}; // @[Cat.scala 29:58]
|
||||||
|
wire [11:0] _T_1313 = {sjald[19],sjald[9:0],sjald[10]}; // @[Cat.scala 29:58]
|
||||||
|
wire [11:0] _T_1316 = simm5_0 ? _T_1289 : 12'h0; // @[Mux.scala 27:72]
|
||||||
|
wire [11:0] _T_1317 = uimm9_2 ? _T_1292 : 12'h0; // @[Mux.scala 27:72]
|
||||||
|
wire [11:0] _T_1318 = rdeq2 ? _T_1299 : 12'h0; // @[Mux.scala 27:72]
|
||||||
|
wire [11:0] _T_1319 = ulwimm6_2 ? _T_1302 : 12'h0; // @[Mux.scala 27:72]
|
||||||
|
wire [11:0] _T_1320 = ulwspimm7_2 ? _T_1305 : 12'h0; // @[Mux.scala 27:72]
|
||||||
|
wire [11:0] _T_1321 = uimm5_0 ? _T_1307 : 12'h0; // @[Mux.scala 27:72]
|
||||||
|
wire [11:0] _T_1322 = _T_228 ? _T_1313 : 12'h0; // @[Mux.scala 27:72]
|
||||||
|
wire [11:0] _T_1323 = sluimm17_12 ? sluimmd[19:8] : 12'h0; // @[Mux.scala 27:72]
|
||||||
|
wire [11:0] _T_1324 = _T_1316 | _T_1317; // @[Mux.scala 27:72]
|
||||||
|
wire [11:0] _T_1325 = _T_1324 | _T_1318; // @[Mux.scala 27:72]
|
||||||
|
wire [11:0] _T_1326 = _T_1325 | _T_1319; // @[Mux.scala 27:72]
|
||||||
|
wire [11:0] _T_1327 = _T_1326 | _T_1320; // @[Mux.scala 27:72]
|
||||||
|
wire [11:0] _T_1328 = _T_1327 | _T_1321; // @[Mux.scala 27:72]
|
||||||
|
wire [11:0] _T_1329 = _T_1328 | _T_1322; // @[Mux.scala 27:72]
|
||||||
|
wire [11:0] _T_1330 = _T_1329 | _T_1323; // @[Mux.scala 27:72]
|
||||||
|
wire [8:0] _T_1338 = _T_228 ? sjald[19:11] : 9'h0; // @[Mux.scala 27:72]
|
||||||
|
wire [7:0] _T_1339 = sluimm17_12 ? sluimmd[7:0] : 8'h0; // @[Mux.scala 27:72]
|
||||||
|
wire [8:0] _GEN_0 = {{1'd0}, _T_1339}; // @[Mux.scala 27:72]
|
||||||
|
wire [8:0] _T_1340 = _T_1338 | _GEN_0; // @[Mux.scala 27:72]
|
||||||
|
wire [8:0] _GEN_1 = {{1'd0}, l1[19:12]}; // @[el2_ifu_compress_ctl.scala 153:25]
|
||||||
|
wire [8:0] l2_19 = _GEN_1 | _T_1340; // @[el2_ifu_compress_ctl.scala 153:25]
|
||||||
|
wire [32:0] l2 = {io_l2_31,l2_19,l1[11:0]}; // @[Cat.scala 29:58]
|
||||||
|
wire [8:0] sbr8d = {io_din[12],io_din[6],io_din[5],io_din[2],io_din[11],io_din[10],io_din[4],io_din[3],1'h0}; // @[Cat.scala 29:58]
|
||||||
|
wire [6:0] uswimm6d = {io_din[5],io_din[12:10],io_din[6],2'h0}; // @[Cat.scala 29:58]
|
||||||
|
wire [7:0] uswspimm7d = {io_din[8:7],io_din[12:9],2'h0}; // @[Cat.scala 29:58]
|
||||||
|
wire [3:0] _T_1371 = sbr8d[8] ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
||||||
|
wire [6:0] _T_1373 = {_T_1371,sbr8d[7:5]}; // @[Cat.scala 29:58]
|
||||||
|
wire [6:0] _T_1376 = {5'h0,uswimm6d[6:5]}; // @[Cat.scala 29:58]
|
||||||
|
wire [6:0] _T_1379 = {4'h0,uswspimm7d[7:5]}; // @[Cat.scala 29:58]
|
||||||
|
wire [6:0] _T_1380 = _T_234 ? _T_1373 : 7'h0; // @[Mux.scala 27:72]
|
||||||
|
wire [6:0] _T_1381 = _T_854 ? _T_1376 : 7'h0; // @[Mux.scala 27:72]
|
||||||
|
wire [6:0] _T_1382 = _T_807 ? _T_1379 : 7'h0; // @[Mux.scala 27:72]
|
||||||
|
wire [6:0] _T_1383 = _T_1380 | _T_1381; // @[Mux.scala 27:72]
|
||||||
|
wire [6:0] _T_1384 = _T_1383 | _T_1382; // @[Mux.scala 27:72]
|
||||||
|
wire [6:0] l3_31 = l2[31:25] | _T_1384; // @[el2_ifu_compress_ctl.scala 161:25]
|
||||||
|
wire [12:0] l3_24 = l2[24:12]; // @[el2_ifu_compress_ctl.scala 164:17]
|
||||||
|
wire [4:0] _T_1390 = {sbr8d[4:1],sbr8d[8]}; // @[Cat.scala 29:58]
|
||||||
|
wire [4:0] _T_1395 = _T_234 ? _T_1390 : 5'h0; // @[Mux.scala 27:72]
|
||||||
|
wire [4:0] _T_1396 = _T_854 ? uswimm6d[4:0] : 5'h0; // @[Mux.scala 27:72]
|
||||||
|
wire [4:0] _T_1397 = _T_807 ? uswspimm7d[4:0] : 5'h0; // @[Mux.scala 27:72]
|
||||||
|
wire [4:0] _T_1398 = _T_1395 | _T_1396; // @[Mux.scala 27:72]
|
||||||
|
wire [4:0] _T_1399 = _T_1398 | _T_1397; // @[Mux.scala 27:72]
|
||||||
|
wire [4:0] l3_11 = l2[11:7] | _T_1399; // @[el2_ifu_compress_ctl.scala 165:24]
|
||||||
|
wire [11:0] _T_1402 = {l3_11,l2[6:0]}; // @[Cat.scala 29:58]
|
||||||
|
wire [19:0] _T_1403 = {l3_31,l3_24}; // @[Cat.scala 29:58]
|
||||||
|
wire [31:0] l3 = {l3_31,l3_24,l3_11,l2[6:0]}; // @[Cat.scala 29:58]
|
||||||
|
wire _T_1410 = _T_4 & _T_487; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1411 = _T_1410 & io_din[11]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1412 = _T_1411 & io_din[1]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1415 = _T_1412 & _T_147; // @[el2_ifu_compress_ctl.scala 170:39]
|
||||||
|
wire _T_1423 = _T_1410 & io_din[6]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1424 = _T_1423 & io_din[1]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1427 = _T_1424 & _T_147; // @[el2_ifu_compress_ctl.scala 170:79]
|
||||||
|
wire _T_1428 = _T_1415 | _T_1427; // @[el2_ifu_compress_ctl.scala 170:54]
|
||||||
|
wire _T_1437 = _T_642 & io_din[11]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1438 = _T_1437 & _T_830; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1439 = _T_1428 | _T_1438; // @[el2_ifu_compress_ctl.scala 170:94]
|
||||||
|
wire _T_1447 = _T_1410 & io_din[5]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1448 = _T_1447 & io_din[1]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1451 = _T_1448 & _T_147; // @[el2_ifu_compress_ctl.scala 171:55]
|
||||||
|
wire _T_1452 = _T_1439 | _T_1451; // @[el2_ifu_compress_ctl.scala 171:30]
|
||||||
|
wire _T_1460 = _T_1410 & io_din[10]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1461 = _T_1460 & io_din[1]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1464 = _T_1461 & _T_147; // @[el2_ifu_compress_ctl.scala 171:96]
|
||||||
|
wire _T_1465 = _T_1452 | _T_1464; // @[el2_ifu_compress_ctl.scala 171:70]
|
||||||
|
wire _T_1474 = _T_642 & io_din[6]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1475 = _T_1474 & _T_830; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1476 = _T_1465 | _T_1475; // @[el2_ifu_compress_ctl.scala 171:111]
|
||||||
|
wire _T_1483 = io_din[15] & _T_487; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1484 = _T_1483 & _T_830; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1485 = _T_1484 & io_din[0]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1486 = _T_1476 | _T_1485; // @[el2_ifu_compress_ctl.scala 172:29]
|
||||||
|
wire _T_1494 = _T_1410 & io_din[9]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1495 = _T_1494 & io_din[1]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1498 = _T_1495 & _T_147; // @[el2_ifu_compress_ctl.scala 172:79]
|
||||||
|
wire _T_1499 = _T_1486 | _T_1498; // @[el2_ifu_compress_ctl.scala 172:54]
|
||||||
|
wire _T_1506 = _T_487 & io_din[6]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1507 = _T_1506 & _T_830; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1508 = _T_1507 & io_din[0]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1509 = _T_1499 | _T_1508; // @[el2_ifu_compress_ctl.scala 172:94]
|
||||||
|
wire _T_1518 = _T_642 & io_din[5]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1519 = _T_1518 & _T_830; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1520 = _T_1509 | _T_1519; // @[el2_ifu_compress_ctl.scala 172:118]
|
||||||
|
wire _T_1528 = _T_1410 & io_din[8]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1529 = _T_1528 & io_din[1]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1532 = _T_1529 & _T_147; // @[el2_ifu_compress_ctl.scala 173:28]
|
||||||
|
wire _T_1533 = _T_1520 | _T_1532; // @[el2_ifu_compress_ctl.scala 172:144]
|
||||||
|
wire _T_1540 = _T_487 & io_din[5]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1541 = _T_1540 & _T_830; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1542 = _T_1541 & io_din[0]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1543 = _T_1533 | _T_1542; // @[el2_ifu_compress_ctl.scala 173:43]
|
||||||
|
wire _T_1552 = _T_642 & io_din[10]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1553 = _T_1552 & _T_830; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1554 = _T_1543 | _T_1553; // @[el2_ifu_compress_ctl.scala 173:67]
|
||||||
|
wire _T_1562 = _T_1410 & io_din[7]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1563 = _T_1562 & io_din[1]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1566 = _T_1563 & _T_147; // @[el2_ifu_compress_ctl.scala 174:28]
|
||||||
|
wire _T_1567 = _T_1554 | _T_1566; // @[el2_ifu_compress_ctl.scala 173:94]
|
||||||
|
wire _T_1575 = io_din[12] & io_din[11]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1576 = _T_1575 & _T_38; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1577 = _T_1576 & _T_830; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1578 = _T_1577 & io_din[0]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1579 = _T_1567 | _T_1578; // @[el2_ifu_compress_ctl.scala 174:43]
|
||||||
|
wire _T_1588 = _T_642 & io_din[9]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1589 = _T_1588 & _T_830; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1590 = _T_1579 | _T_1589; // @[el2_ifu_compress_ctl.scala 174:71]
|
||||||
|
wire _T_1598 = _T_1410 & io_din[4]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1599 = _T_1598 & io_din[1]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1602 = _T_1599 & _T_147; // @[el2_ifu_compress_ctl.scala 175:28]
|
||||||
|
wire _T_1603 = _T_1590 | _T_1602; // @[el2_ifu_compress_ctl.scala 174:97]
|
||||||
|
wire _T_1609 = io_din[13] & io_din[12]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1610 = _T_1609 & _T_830; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1611 = _T_1610 & io_din[0]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1612 = _T_1603 | _T_1611; // @[el2_ifu_compress_ctl.scala 175:43]
|
||||||
|
wire _T_1621 = _T_642 & io_din[8]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1622 = _T_1621 & _T_830; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1623 = _T_1612 | _T_1622; // @[el2_ifu_compress_ctl.scala 175:67]
|
||||||
|
wire _T_1631 = _T_1410 & io_din[3]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1632 = _T_1631 & io_din[1]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1635 = _T_1632 & _T_147; // @[el2_ifu_compress_ctl.scala 176:28]
|
||||||
|
wire _T_1636 = _T_1623 | _T_1635; // @[el2_ifu_compress_ctl.scala 175:93]
|
||||||
|
wire _T_1642 = io_din[13] & io_din[4]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1643 = _T_1642 & _T_830; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1644 = _T_1643 & io_din[0]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1645 = _T_1636 | _T_1644; // @[el2_ifu_compress_ctl.scala 176:43]
|
||||||
|
wire _T_1653 = _T_1410 & io_din[2]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1654 = _T_1653 & io_din[1]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1657 = _T_1654 & _T_147; // @[el2_ifu_compress_ctl.scala 176:91]
|
||||||
|
wire _T_1658 = _T_1645 | _T_1657; // @[el2_ifu_compress_ctl.scala 176:66]
|
||||||
|
wire _T_1667 = _T_642 & io_din[7]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1668 = _T_1667 & _T_830; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1669 = _T_1658 | _T_1668; // @[el2_ifu_compress_ctl.scala 176:106]
|
||||||
|
wire _T_1675 = io_din[13] & io_din[3]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1676 = _T_1675 & _T_830; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1677 = _T_1676 & io_din[0]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1678 = _T_1669 | _T_1677; // @[el2_ifu_compress_ctl.scala 177:29]
|
||||||
|
wire _T_1684 = io_din[13] & io_din[2]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1685 = _T_1684 & _T_830; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1686 = _T_1685 & io_din[0]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1687 = _T_1678 | _T_1686; // @[el2_ifu_compress_ctl.scala 177:52]
|
||||||
|
wire _T_1693 = io_din[14] & _T_4; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1694 = _T_1693 & _T_830; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1695 = _T_1687 | _T_1694; // @[el2_ifu_compress_ctl.scala 177:75]
|
||||||
|
wire _T_1704 = _T_703 & _T_830; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1705 = _T_1704 & io_din[0]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1706 = _T_1695 | _T_1705; // @[el2_ifu_compress_ctl.scala 177:98]
|
||||||
|
wire _T_1713 = _T_820 & io_din[12]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1714 = _T_1713 & io_din[1]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1717 = _T_1714 & _T_147; // @[el2_ifu_compress_ctl.scala 178:54]
|
||||||
|
wire _T_1718 = _T_1706 | _T_1717; // @[el2_ifu_compress_ctl.scala 178:29]
|
||||||
|
wire _T_1727 = _T_642 & _T_487; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1728 = _T_1727 & io_din[1]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1731 = _T_1728 & _T_147; // @[el2_ifu_compress_ctl.scala 178:96]
|
||||||
|
wire _T_1732 = _T_1718 | _T_1731; // @[el2_ifu_compress_ctl.scala 178:69]
|
||||||
|
wire _T_1741 = _T_642 & io_din[12]; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1742 = _T_1741 & _T_830; // @[el2_ifu_compress_ctl.scala 20:110]
|
||||||
|
wire _T_1743 = _T_1732 | _T_1742; // @[el2_ifu_compress_ctl.scala 178:111]
|
||||||
|
wire _T_1750 = _T_1693 & _T_147; // @[el2_ifu_compress_ctl.scala 179:50]
|
||||||
|
wire legal = _T_1743 | _T_1750; // @[el2_ifu_compress_ctl.scala 179:30]
|
||||||
|
wire [31:0] _T_1752 = legal ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||||
|
wire [9:0] _T_1762 = {1'h0,out_30,1'h0,1'h0,1'h0,1'h0,1'h0,1'h0,1'h0,1'h0}; // @[Cat.scala 29:58]
|
||||||
|
wire [18:0] _T_1771 = {_T_1762,1'h0,out_20,1'h0,1'h0,1'h0,1'h0,1'h0,out_14,out_13}; // @[Cat.scala 29:58]
|
||||||
|
wire [27:0] _T_1780 = {_T_1771,out_12,1'h0,1'h0,1'h0,1'h0,1'h0,out_6,out_5,out_4}; // @[Cat.scala 29:58]
|
||||||
|
wire [30:0] _T_1783 = {_T_1780,_T_228,out_2,1'h1}; // @[Cat.scala 29:58]
|
||||||
|
assign io_dout = l3 & _T_1752; // @[el2_ifu_compress_ctl.scala 181:10]
|
||||||
|
assign io_l1 = {_T_1234,_T_1232}; // @[el2_ifu_compress_ctl.scala 182:9]
|
||||||
|
assign io_l2 = l2[31:0]; // @[el2_ifu_compress_ctl.scala 183:9]
|
||||||
|
assign io_l3 = {_T_1403,_T_1402}; // @[el2_ifu_compress_ctl.scala 184:9]
|
||||||
|
assign io_legal = _T_1743 | _T_1750; // @[el2_ifu_compress_ctl.scala 185:12]
|
||||||
|
assign io_o = {_T_1783,1'h1}; // @[el2_ifu_compress_ctl.scala 186:8]
|
||||||
|
assign io_l2_31 = l1[31:20] | _T_1330; // @[el2_ifu_compress_ctl.scala 143:12]
|
||||||
endmodule
|
endmodule
|
||||||
|
|
|
||||||
|
|
@ -3,204 +3,195 @@ package ifu
|
||||||
import chisel3._
|
import chisel3._
|
||||||
import chisel3.util._
|
import chisel3.util._
|
||||||
|
|
||||||
//class el2_ifu_compress_ctl extends Module {
|
class el2_ifu_compress_ctl extends Module {
|
||||||
// val io = IO(new Bundle{
|
val io = IO(new Bundle{
|
||||||
// val din = Input(UInt(16.W))
|
val din = Input(UInt(16.W))
|
||||||
// val dout = Output(UInt(32.W))
|
val dout = Output(UInt(32.W))
|
||||||
// val l1 = Output(UInt(32.W))
|
val l1 = Output(UInt(32.W))
|
||||||
// val l2 = Output(UInt(32.W))
|
val l2 = Output(UInt(32.W))
|
||||||
// val l3 = Output(UInt(32.W))
|
val l3 = Output(UInt(32.W))
|
||||||
// val legal = Output(Bool())
|
val legal = Output(Bool())
|
||||||
// val o = Output(UInt(32.W))
|
val o = Output(UInt(32.W))
|
||||||
// val sluimmd = Output(UInt())
|
val l2_31 = Output(UInt())
|
||||||
//
|
})
|
||||||
// val uimm5d = Output(UInt())
|
|
||||||
// val ulwspimm7d = Output(UInt())
|
//io.dout := (0 until 32).map(i=> 0.U.asBool)
|
||||||
// val ulwimm6d = Output(UInt())
|
|
||||||
// val simm9d = Output(UInt())
|
def pat(y : List[Int]) = (0 until y.size).map(i=> if(y(i)>=0) io.din(y(i)) else !io.din(y(i).abs)).reduce(_&_)
|
||||||
// val uimm9d = Output(UInt())
|
val out = Wire(Vec(32, UInt(1.W)))
|
||||||
// val simm5d = Output(UInt())
|
out := (0 until 32).map(i=> 0.U.asBool)
|
||||||
// val sjald = Output(UInt())
|
out(30) := pat(List(15, -14, -13, 10, -6, -5, 0)) | pat(List(15, -14, -13, -11, 10, 0))
|
||||||
// val l2_31 = Output(UInt())
|
out(20) := pat(List(-14, 12, -11, -10, -9, -8, -7, -6, -5, -4, -3, -2, 1))
|
||||||
// })
|
out(14) := pat(List(15, -14, -13, -11, 0)) | pat(List(15, -14, -13, -10, 0)) | pat(List(15, -14, -13, 6, 0)) |
|
||||||
//
|
pat(List(15, -14, -13, 5, 0))
|
||||||
// //io.dout := (0 until 32).map(i=> 0.U.asBool)
|
out(13) := pat(List(15, -14, -13, 11, -10, 0)) | pat(List(15, -14, -13, 11, 6, 0)) | (io.din(14)&(!io.din(0)))
|
||||||
//
|
out(12) := pat(List(15, -14, -13, 6, 5, 0)) | pat(List(15, -14, -13, -11, 0)) | pat(List(15, -14, -13, -10, 0)) |
|
||||||
// def pat(y : List[Int]) = (0 until y.size).map(i=> if(y(i)>=0) io.din(y(i)) else !io.din(y(i).abs)).reduce(_&_)
|
pat(List(-15, -14, 1)) | pat(List(15, 14, 13))
|
||||||
// val out = Wire(Vec(32, UInt(1.W)))
|
out(6) := (pat(List(15, -14, -6, -5, -4, -3, -2)) & !io.din(0)) | pat(List(-14, 13)) | pat(List(15, 14, 0))
|
||||||
// out := (0 until 32).map(i=> 0.U.asBool)
|
|
||||||
// out(30) := pat(List(15, -14, -13, 10, -6, -5, 0)) | pat(List(15, -14, -13, -11, 10, 0))
|
out(5) := (io.din(15)&(!io.din(0))) | pat(List(15, 11, 10)) | pat(List(13, -8)) | pat(List(13, 7)) |
|
||||||
// out(20) := pat(List(-14, 12, -11, -10, -9, -8, -7, -6, -5, -4, -3, -2, 1))
|
pat(List(13, 9)) | pat(List(13, 10)) | pat(List(13, 11)) | pat(List(-14, 13)) | pat(List(15, 14))
|
||||||
// out(14) := pat(List(15, -14, -13, -11, 0)) | pat(List(15, -14, -13, -10, 0)) | pat(List(15, -14, -13, 6, 0)) |
|
|
||||||
// pat(List(15, -14, -13, 5, 0))
|
|
||||||
// out(13) := pat(List(15, -14, -13, 11, -10, 0)) | pat(List(15, -14, -13, 11, 6, 0)) | (io.din(14)&(!io.din(0)))
|
out(4) := (pat(List(-14, -11, -10, -9, -8, -7))&(!io.din(0))) | (pat(List(-15, -14))&(!io.din(0))) |
|
||||||
// out(12) := pat(List(15, -14, -13, 6, 5, 0)) | pat(List(15, -14, -13, -11, 0)) | pat(List(15, -14, -13, -10, 0)) |
|
(pat(List(-14, 6))&(!io.din(0))) | pat(List(-15, 14, 0)) | (pat(List(-14, 5))&(!io.din(0))) |
|
||||||
// pat(List(-15, -14, 1)) | pat(List(15, 14, 13))
|
(pat(List(-14, 4))&(!io.din(0))) | (pat(List(-14, 3))&(!io.din(0))) | (pat(List(-14, 2))&(!io.din(0))) |
|
||||||
// out(6) := (pat(List(15, -14, -6, -5, -4, -3, -2)) & !io.din(0)) | pat(List(-14, 13)) | pat(List(15, 14, 0))
|
pat(List(-14, -13, 0))
|
||||||
//
|
|
||||||
// out(5) := (io.din(15)&(!io.din(0))) | pat(List(15, 11, 10)) | pat(List(13, -8)) | pat(List(13, 7)) |
|
|
||||||
// pat(List(13, 9)) | pat(List(13, 10)) | pat(List(13, 11)) | pat(List(-14, 13)) | pat(List(15, 14))
|
|
||||||
//
|
|
||||||
//
|
out(3) := pat(List(-14, 13))
|
||||||
// out(4) := (pat(List(-14, -11, -10, -9, -8, -7))&(!io.din(0))) | (pat(List(-15, -14))&(!io.din(0))) |
|
out(2) := pat(List(-14, 12, 11, -6, -5, -4, -3, -2, 1)) |
|
||||||
// (pat(List(-14, 6))&(!io.din(0))) | pat(List(-15, 14, 0)) | (pat(List(-14, 5))&(!io.din(0))) |
|
pat(List(-14, 12, 10, -6, -5, -4, -3, -2, 1)) |
|
||||||
// (pat(List(-14, 4))&(!io.din(0))) | (pat(List(-14, 3))&(!io.din(0))) | (pat(List(-14, 2))&(!io.din(0))) |
|
pat(List(-14, 12, 9, -6, -5, -4, -3, -2, 1)) |
|
||||||
// pat(List(-14, -13, 0))
|
pat(List(-14, 12, 8, -6,-5,-4, -3, -2,1)) |
|
||||||
//
|
pat(List(-14, 12, 7, -6, -5, -4, -3, -2,1)) |
|
||||||
//
|
(pat(List(15, -14,-12, -6, -5, -4, -3, -2))&(!io.din(0))) |
|
||||||
//
|
pat(List(-15,13,-8)) |
|
||||||
//
|
pat(List(-15,13,7)) |
|
||||||
// out(3) := pat(List(-14, 13))
|
pat(List(-15,13,9)) |
|
||||||
// out(2) := pat(List(-14, 12, 11, -6, -5, -4, -3, -2, 1)) |
|
pat(List(-15,13,10)) |
|
||||||
// pat(List(-14, 12, 10, -6, -5, -4, -3, -2, 1)) |
|
pat(List(-15,13,11)) |
|
||||||
// pat(List(-14, 12, 9, -6, -5, -4, -3, -2, 1)) |
|
pat(List(-14,13))
|
||||||
// pat(List(-14, 12, 8, -6,-5,-4, -3, -2,1)) |
|
out(1) := 1.U.asBool
|
||||||
// pat(List(-14, 12, 7, -6, -5, -4, -3, -2,1)) |
|
out(0) := 1.U.asBool
|
||||||
// (pat(List(15, -14,-12, -6, -5, -4, -3, -2))&(!io.din(0))) |
|
|
||||||
// pat(List(-15,13,-8)) |
|
|
||||||
// pat(List(-15,13,7)) |
|
|
||||||
// pat(List(-15,13,9)) |
|
|
||||||
// pat(List(-15,13,10)) |
|
|
||||||
// pat(List(-15,13,11)) |
|
val rs2d = io.din(6,2)
|
||||||
// pat(List(-14,13))
|
val rdd = io.din(11,7)
|
||||||
// out(1) := 1.U.asBool
|
val rdpd = Cat(1.U(2.W), io.din(9,7))
|
||||||
// out(0) := 1.U.asBool
|
val rs2pd = Cat(1.U(2.W), io.din(4,2))
|
||||||
//
|
|
||||||
//
|
val rdrd = pat(List(-14,6,1)) | pat(List(-15,14,11,0)) | pat(List(-14,5,1)) | pat(List(-15,14,10,0)) |
|
||||||
//
|
pat(List(-14,4,1)) | pat(List(-15,14,9,0)) | pat(List(-14,3,1)) | pat(List(-15,14,-8,0)) |
|
||||||
//
|
pat(List(-14,2,1)) | pat(List(-15,14,7,0)) | pat(List(-15,1)) | pat(List(-15,-13,0))
|
||||||
//
|
|
||||||
// val rs2d = io.din(6,2)
|
val rdrs1 = pat(List(-14,12,11,1)) |
|
||||||
// val rdd = io.din(11,7)
|
pat(List(-14,12,10,1)) |
|
||||||
// val rdpd = Cat(1.U(2.W), io.din(9,7))
|
pat(List(-14,12,9,1)) |
|
||||||
// val rs2pd = Cat(1.U(2.W), io.din(4,2))
|
pat(List(-14,12,8,1)) |
|
||||||
//
|
pat(List(-14,12,7,1)) |
|
||||||
// val rdrd = pat(List(-14,6,1)) | pat(List(-15,14,11,0)) | pat(List(-14,5,1)) | pat(List(-15,14,10,0)) |
|
pat(List(-14,-12,-6,-5,-4,-3,-2,1)) |
|
||||||
// pat(List(-14,4,1)) | pat(List(-15,14,9,0)) | pat(List(-14,3,1)) | pat(List(-15,14,-8,0)) |
|
pat(List(-14,12,6,1)) |
|
||||||
// pat(List(-14,2,1)) | pat(List(-15,14,7,0)) | pat(List(-15,1)) | pat(List(-15,-13,0))
|
pat(List(-14,12,5,1)) |
|
||||||
//
|
pat(List(-14,12,4,1)) |
|
||||||
// val rdrs1 = pat(List(-14,12,11,1)) |
|
pat(List(-14,12,3,1)) |
|
||||||
// pat(List(-14,12,10,1)) |
|
pat(List(-14,12,2,1)) |
|
||||||
// pat(List(-14,12,9,1)) |
|
pat(List(-15,-14,-13,0)) |
|
||||||
// pat(List(-14,12,8,1)) |
|
pat(List(-15,-14,1))
|
||||||
// pat(List(-14,12,7,1)) |
|
|
||||||
// pat(List(-14,-12,-6,-5,-4,-3,-2,1)) |
|
val rs2rs2 = pat(List(15,6,1)) | pat(List(15,5,1)) | pat(List(15,4,1)) | pat(List(15,3,1)) | pat(List(15,2,1)) | pat(List(15,14,1))
|
||||||
// pat(List(-14,12,6,1)) |
|
|
||||||
// pat(List(-14,12,5,1)) |
|
val rdprd = pat(List(15,-14,-13,0))
|
||||||
// pat(List(-14,12,4,1)) |
|
|
||||||
// pat(List(-14,12,3,1)) |
|
val rdprs1 = pat(List(15,-13,0)) | pat(List(15,14,0)) | (pat(List(14,-1))&(!io.din(0)))
|
||||||
// pat(List(-14,12,2,1)) |
|
|
||||||
// pat(List(-15,-14,-13,0)) |
|
val rs2prs2 = pat(List(15,-14,-13,11,10,0)) | (pat(List(15,-1))&(!io.din(0)))
|
||||||
// pat(List(-15,-14,1))
|
val rs2prd = pat(List(-15,-1))&(!io.din(0))
|
||||||
//
|
val uimm9_2 = pat(List(-14,-1))&(!io.din(0))
|
||||||
// val rs2rs2 = pat(List(15,6,1)) | pat(List(15,5,1)) | pat(List(15,4,1)) | pat(List(15,3,1)) | pat(List(15,2,1)) | pat(List(15,14,1))
|
val ulwimm6_2 = pat(List(-15,14,-1))&(!io.din(0))
|
||||||
//
|
val ulwspimm7_2 = pat(List(-15,14,1))
|
||||||
// val rdprd = pat(List(15,-14,-13,0))
|
val rdeq2 = pat(List(-15,14,13,-11,-10,-9,8,-7))
|
||||||
//
|
val rdeq1 = pat(List(-14,12,11,-6,-5,-4,-3,-2,1)) | pat(List(-14,12,10,-6,-5,-4,-3,-2,1)) |
|
||||||
// val rdprs1 = pat(List(15,-13,0)) | pat(List(15,14,0)) | (pat(List(14,-1))&(!io.din(0)))
|
pat(List(-14,12,9,-6,-5,-4,-3,-2,1)) | pat(List(-14,12,8,-6,-5,-4,-3,-2,1)) |
|
||||||
//
|
pat(List(-14,12,7,-6,-5,-4,-3,-2,1)) | pat(List(-15,-14,13))
|
||||||
// val rs2prs2 = pat(List(15,-14,-13,11,10,0)) | (pat(List(15,-1))&(!io.din(0)))
|
val rs1eq2 = pat(List(-15,14,13,-11,-10,-9,8,-7)) | pat(List(14,1)) | (pat(List(-14,-1))&(!io.din(0)))
|
||||||
// val rs2prd = pat(List(-15,-1))&(!io.din(0))
|
val sbroffset8_1 = pat(List(15,14,0))
|
||||||
// val uimm9_2 = pat(List(-14,-1))&(!io.din(0))
|
val simm9_4 = pat(List(-15,14,13,-11,-10,-9,8,-7))
|
||||||
// val ulwimm6_2 = pat(List(-15,14,-1))&(!io.din(0))
|
val simm5_0 = pat(List(-14,-13,11,-10,0)) | pat(List(-15,-13,0))
|
||||||
// val ulwspimm7_2 = pat(List(-15,14,1))
|
val sjaloffset11_1 = pat(List(-14,13))
|
||||||
// val rdeq2 = pat(List(-15,14,13,-11,-10,-9,8,-7))
|
val sluimm17_12 = pat(List(-15,14,13,7)) |
|
||||||
// val rdeq1 = pat(List(-14,12,11,-6,-5,-4,-3,-2,1)) | pat(List(-14,12,10,-6,-5,-4,-3,-2,1)) |
|
pat(List(-15,14,13,-8)) |
|
||||||
// pat(List(-14,12,9,-6,-5,-4,-3,-2,1)) | pat(List(-14,12,8,-6,-5,-4,-3,-2,1)) |
|
pat(List(-15,14,13,9)) |
|
||||||
// pat(List(-14,12,7,-6,-5,-4,-3,-2,1)) | pat(List(-15,-14,13))
|
pat(List(-15,14,13,10)) |
|
||||||
// val rs1eq2 = pat(List(-15,14,13,-11,-10,-9,8,-7)) | pat(List(14,1)) | (pat(List(-14,-1))&(!io.din(0)))
|
pat(List(-15,14,13,11))
|
||||||
// val sbroffset8_1 = pat(List(15,14,0))
|
val uimm5_0 = pat(List(15,-14,-13,-11,0)) | pat(List(-15,-14,1))
|
||||||
// val simm9_4 = pat(List(-15,14,13,-11,-10,-9,8,-7))
|
val uswimm6_2 = pat(List(15,-1))&(!io.din(0))
|
||||||
// val simm5_0 = pat(List(-14,-13,11,-10,0)) | pat(List(-15,-13,0))
|
val uswspimm7_2 = pat(List(15,14,1))
|
||||||
// val sjaloffset11_1 = pat(List(-14,13))
|
|
||||||
// val sluimm17_12 = pat(List(-15,14,13,7)) |
|
val l1_6 = Cat(out(6),out(5),out(4),out(3),out(2),out(1),out(0)).asUInt()
|
||||||
// pat(List(-15,14,13,-8)) |
|
val l1_11 = Cat(out(11),out(10),out(9),out(8),out(7)).asUInt | Mux1H(Seq(rdrd.asBool->rdd,
|
||||||
// pat(List(-15,14,13,9)) |
|
rdprd.asBool->rdpd, rs2prd.asBool->rs2pd, rdeq1.asBool->1.U(5.W), rdeq2.asBool->2.U(5.W)))
|
||||||
// pat(List(-15,14,13,10)) |
|
|
||||||
// pat(List(-15,14,13,11))
|
val l1_14 = Cat(out(14),out(13),out(12))
|
||||||
// val uimm5_0 = pat(List(15,-14,-13,-11,0)) | pat(List(-15,-14,1))
|
|
||||||
// val uswimm6_2 = pat(List(15,-1))&(!io.din(0))
|
val l1_19 = Cat(out(19),out(18),out(17),out(16),out(15)).asUInt | Mux1H(Seq(rdrs1.asBool->rdd,
|
||||||
// val uswspimm7_2 = pat(List(15,14,1))
|
rdprs1.asBool->rdpd, rs1eq2.asBool->2.U(5.W)))
|
||||||
//
|
|
||||||
// val l1_6 = Cat(out(6),out(5),out(4),out(3),out(2),out(1),out(0)).asUInt()
|
val l1_24 = Cat(out(24),out(23),out(22),out(21),out(20)).asUInt | Mux1H(Seq(rs2rs2.asBool->rs2d,
|
||||||
// val l1_11 = Cat(out(11),out(10),out(9),out(8),out(7)).asUInt | Mux1H(Seq(rdrd.asBool->rdd,
|
rs2prs2.asBool->rs2pd))
|
||||||
// rdprd.asBool->rdpd, rs2prd.asBool->rs2pd, rdeq1.asBool->1.U(5.W), rdeq2.asBool->2.U(5.W)))
|
val l1_31 = Cat(out(31),out(30),out(29),out(28),out(27),out(26),out(25)).asUInt
|
||||||
//
|
val l1 = Cat(l1_31,l1_24,l1_19,l1_14,l1_11,l1_6)
|
||||||
// val l1_14 = Cat(out(14),out(13),out(12))
|
|
||||||
//
|
val simm5d = Cat(io.din(12), io.din(6,2))
|
||||||
// val l1_19 = Cat(out(19),out(18),out(17),out(16),out(15)).asUInt | Mux1H(Seq(rdrs1.asBool->rdd,
|
val uimm9d = Cat(io.din(10,7), io.din(12,11), io.din(5), io.din(6))
|
||||||
// rdprs1.asBool->rdpd, rs1eq2.asBool->2.U(5.W)))
|
val simm9d = Cat(io.din(12), io.din(4,3), io.din(5), io.din(2), io.din(6))
|
||||||
//
|
val ulwimm6d = Cat(io.din(5), io.din(12,10), io.din(6))
|
||||||
// val l1_24 = Cat(out(24),out(23),out(22),out(21),out(20)).asUInt | Mux1H(Seq(rs2rs2.asBool->rs2d,
|
val ulwspimm7d = Cat(io.din(3,2), io.din(12), io.din(6,4))
|
||||||
// rs2prs2.asBool->rs2pd))
|
val uimm5d = Cat(io.din(12), io.din(6,2))
|
||||||
// val l1_31 = Cat(out(31),out(30),out(29),out(28),out(27),out(26),out(25)).asUInt
|
val sjald_1 = Cat(io.din(12), io.din(8), io.din(10,9), io.din(6), io.din(7), io.din(2), io.din(11),
|
||||||
// val l1 = Cat(l1_31,l1_24,l1_19,l1_14,l1_11,l1_6)
|
io.din(5,4), io.din(3))
|
||||||
//
|
val sjald_12 = Fill(9, io.din(12))
|
||||||
// val simm5d = Cat(io.din(12), io.din(6,2))
|
val sjald = Cat(sjald_12,sjald_1)
|
||||||
// val uimm9d = Cat(io.din(10,7), io.din(12,11), io.din(5), io.din(6))
|
val sluimmd = Cat(Fill(15, io.din(12)), io.din(6,2))
|
||||||
// val simm9d = Cat(io.din(12), io.din(4,3), io.din(5), io.din(2), io.din(6))
|
//io.sluimmd := sluimmd
|
||||||
// val ulwimm6d = Cat(io.din(5), io.din(12,10), io.din(6))
|
|
||||||
// val ulwspimm7d = Cat(io.din(3,2), io.din(12), io.din(6,4))
|
io.l2_31 := l1(31,20) |
|
||||||
// val uimm5d = Cat(io.din(12), io.din(6,2))
|
Mux1H(Seq(simm5_0.asBool->Cat(Fill(7, simm5d(5)), simm5d(4,0)),
|
||||||
// val sjald_1 = Cat(io.din(12), io.din(8), io.din(10,9), io.din(6), io.din(7), io.din(2), io.din(11),
|
uimm9_2.asBool->Cat(0.U(2.W), uimm9d, 0.U(2.W)),
|
||||||
// io.din(5,4), io.din(3))
|
simm9_4.asBool->Cat(Fill(3, simm9d(5)), simm9d(4,0), 0.U(4.W)),
|
||||||
// val sjald_12 = Fill(9, io.din(12))
|
ulwimm6_2.asBool->Cat(0.U(5.W), ulwimm6d, 0.U(2.W)),
|
||||||
// val sjald = Cat(sjald_12,sjald_1)
|
ulwspimm7_2.asBool->Cat(0.U(4.W), ulwspimm7d, 0.U(2.W)),
|
||||||
// val sluimmd = Cat(Fill(15, io.din(12)), io.din(6,2))
|
uimm5_0.asBool->Cat(0.U(6.W), uimm5d),
|
||||||
|
sjaloffset11_1.asBool->Cat(sjald(19), sjald(9,0), sjald(10)),
|
||||||
|
sluimm17_12.asBool->sluimmd(19,8)))
|
||||||
|
|
||||||
|
val l2_19 = l1(19,12) | Mux1H(Seq(sjaloffset11_1.asBool->sjald(19,11),
|
||||||
|
sluimm17_12.asBool->sluimmd(7,0)))
|
||||||
|
val l2 = Cat(io.l2_31, l2_19, l1(11,0))
|
||||||
|
|
||||||
|
|
||||||
|
val sbr8d = Cat(io.din(12),io.din(6),io.din(5),io.din(2),io.din(11),io.din(10),io.din(4),io.din(3),0.U)
|
||||||
|
val uswimm6d = Cat(io.din(5), io.din(12,10), io.din(6), 0.U(2.W))
|
||||||
|
val uswspimm7d = Cat(io.din(8,7),io.din(12,9), 0.U(2.W))
|
||||||
|
val l3_31 = l2(31,25) | Mux1H(Seq(sbroffset8_1.asBool->Cat(Fill(4,sbr8d(8)),sbr8d(7,5)),
|
||||||
|
uswimm6_2.asBool->Cat(0.U(5.W),uswimm6d(6,5)),
|
||||||
|
uswspimm7_2.asBool->Cat(0.U(4.W),uswspimm7d(7,5))))
|
||||||
|
val l3_24 = l2(24,12)
|
||||||
|
val l3_11 = l2(11,7) | Mux1H(Seq(sbroffset8_1.asBool->Cat(sbr8d(4,1), sbr8d(8)),
|
||||||
|
uswimm6_2.asBool->uswimm6d(4,0),
|
||||||
|
uswspimm7_2.asBool->uswspimm7d(4,0)))
|
||||||
|
val l3 = Cat(l3_31, l3_24, l3_11, l2(6,0))
|
||||||
|
|
||||||
|
val legal = (pat(List(-13,-12,11,1))&(!io.din(0))) | (pat(List(-13,-12,6,1))&(!io.din(0))) |
|
||||||
|
pat(List(-15,-13,11,-1)) | (pat(List(-13,-12,5,1))&(!io.din(0))) | (pat(List(-13,-12,10,1))&(!io.din(0))) |
|
||||||
|
pat(List(-15,-13,6,-1)) | pat(List(15,-12,-1,0)) | (pat(List(-13,-12,9,1))&(!io.din(0))) | pat(List(-12,6,-1,0)) | pat(List(-15,-13,5,-1)) |
|
||||||
|
(pat(List(-13,-12,8,1))&(!io.din(0))) | pat(List(-12,5,-1,0)) | pat(List(-15,-13,10,-1)) |
|
||||||
|
(pat(List(-13,-12,7,1))&(!io.din(0))) | pat(List(12,11,-10,-1,0)) | pat(List(-15,-13,9,-1)) |
|
||||||
|
(pat(List(-13,-12,4,1))&(!io.din(0))) | pat(List(13,12,-1,0)) | pat(List(-15,-13,8,-1)) |
|
||||||
|
(pat(List(-13,-12,3,1))&(!io.din(0))) | pat(List(13,4,-1,0)) | (pat(List(-13,-12,2,1))&(!io.din(0))) |
|
||||||
|
pat(List(-15,-13,7,-1)) | pat(List(13,3,-1,0)) | pat(List(13,2,-1,0)) | pat(List(14,-13,-1)) |
|
||||||
|
pat(List(-14,-12,-1,0)) | (pat(List(15,-13,12,1))&(!io.din(0))) | (pat(List(-15,-13,-12,1))&(!io.din(0))) |
|
||||||
|
pat(List(-15,-13,12,-1)) | (pat(List(14,-13))&(!io.din(0)))
|
||||||
|
|
||||||
|
io.dout:= l3 & Fill(32, legal)
|
||||||
|
io.l1 := l1
|
||||||
|
io.l2 := l2
|
||||||
|
io.l3 := l3
|
||||||
|
io.legal := legal
|
||||||
|
io.o := out.reverse.reduce(Cat(_,_))
|
||||||
// io.sluimmd := sluimmd
|
// io.sluimmd := sluimmd
|
||||||
|
// io.simm5_0 := simm5_0
|
||||||
|
// io.uimm9_2 := uimm9_2
|
||||||
|
// io.simm9_4 := simm9_4
|
||||||
|
// io.ulwimm6_2 := ulwimm6_2
|
||||||
|
// io.ulwspimm7_2 := ulwspimm7_2
|
||||||
|
// io.uimm5_0 := uimm5_0
|
||||||
//
|
//
|
||||||
// io.l2_31 := l1(31,20) |
|
|
||||||
// Mux1H(Seq(simm5_0.asBool->Cat(Fill(7, simm5d(5)), simm5d(4,0)),
|
|
||||||
// uimm9_2.asBool->Cat(0.U(2.W), uimm9d, 0.U(2.W)),
|
|
||||||
// simm9_4.asBool->Cat(Fill(3, simm9d(5)), simm9d(4,0), 0.U(4.W)),
|
|
||||||
// ulwimm6_2.asBool->Cat(0.U(5.W), ulwimm6d, 0.U(2.W)),
|
|
||||||
// ulwspimm7_2.asBool->Cat(0.U(4.W), ulwspimm7d, 0.U(2.W)),
|
|
||||||
// uimm5_0.asBool->Cat(0.U(6.W), uimm5d),
|
|
||||||
// sjaloffset11_1.asBool->Cat(sjald(19), sjald(9,0), sjald(10)),
|
|
||||||
// sluimm17_12.asBool->sluimmd(19,8)))
|
|
||||||
//
|
|
||||||
// val l2_19 = l1(19,12) | Mux1H(Seq(sjaloffset11_1.asBool->sjald(19,11),
|
|
||||||
// sluimm17_12.asBool->sluimmd(7,0)))
|
|
||||||
// val l2 = Cat(io.l2_31, l2_19, l1(11,0))
|
|
||||||
//
|
|
||||||
//
|
|
||||||
// val sbr8d = Cat(io.din(12),io.din(6),io.din(5),io.din(2),io.din(11),io.din(10),io.din(4),io.din(3),0.U)
|
|
||||||
// val uswimm6d = Cat(io.din(5), io.din(12,10), io.din(6), 0.U(2.W))
|
|
||||||
// val uswspimm7d = Cat(io.din(8,7),io.din(12,9), 0.U(2.W))
|
|
||||||
// val l3_31 = l2(31,25) | Mux1H(Seq(sbroffset8_1.asBool->Cat(Fill(4,sbr8d(8)),sbr8d(7,5)),
|
|
||||||
// uswimm6_2.asBool->Cat(0.U(5.W),uswimm6d(6,5)),
|
|
||||||
// uswspimm7_2.asBool->Cat(0.U(4.W),uswspimm7d(7,5))))
|
|
||||||
// val l3_24 = l2(24,12)
|
|
||||||
// val l3_11 = l2(11,7) | Mux1H(Seq(sbroffset8_1.asBool->Cat(sbr8d(4,1), sbr8d(8)),
|
|
||||||
// uswimm6_2.asBool->uswimm6d(4,0),
|
|
||||||
// uswspimm7_2.asBool->uswspimm7d(4,0)))
|
|
||||||
// val l3 = Cat(l3_31, l3_24, l3_11, l2(6,0))
|
|
||||||
//
|
|
||||||
// val legal = (pat(List(-13,-12,11,1))&(!io.din(0))) | (pat(List(-13,-12,6,1))&(!io.din(0))) |
|
|
||||||
// pat(List(-15,-13,11,-1)) | (pat(List(-13,-12,5,1))&(!io.din(0))) | (pat(List(-13,-12,10,1))&(!io.din(0))) |
|
|
||||||
// pat(List(-15,-13,6,-1)) | pat(List(15,-12,-1,0)) | (pat(List(-13,-12,9,1))&(!io.din(0))) | pat(List(-12,6,-1,0)) | pat(List(-15,-13,5,-1)) |
|
|
||||||
// (pat(List(-13,-12,8,1))&(!io.din(0))) | pat(List(-12,5,-1,0)) | pat(List(-15,-13,10,-1)) |
|
|
||||||
// (pat(List(-13,-12,7,1))&(!io.din(0))) | pat(List(12,11,-10,-1,0)) | pat(List(-15,-13,9,-1)) |
|
|
||||||
// (pat(List(-13,-12,4,1))&(!io.din(0))) | pat(List(13,12,-1,0)) | pat(List(-15,-13,8,-1)) |
|
|
||||||
// (pat(List(-13,-12,3,1))&(!io.din(0))) | pat(List(13,4,-1,0)) | (pat(List(-13,-12,2,1))&(!io.din(0))) |
|
|
||||||
// pat(List(-15,-13,7,-1)) | pat(List(13,3,-1,0)) | pat(List(13,2,-1,0)) | pat(List(14,-13,-1)) |
|
|
||||||
// pat(List(-14,-12,-1,0)) | (pat(List(15,-13,12,1))&(!io.din(0))) | (pat(List(-15,-13,-12,1))&(!io.din(0))) |
|
|
||||||
// pat(List(-15,-13,12,-1)) | (pat(List(14,-13))&(!io.din(0)))
|
|
||||||
//
|
|
||||||
// io.dout:= l3 & Fill(32, legal)
|
|
||||||
// io.l1 := l1
|
|
||||||
// io.l2 := l2
|
|
||||||
// io.l3 := l3
|
|
||||||
// io.legal := legal
|
|
||||||
// io.o := out.reverse.reduce(Cat(_,_))
|
|
||||||
//// io.sluimmd := sluimmd
|
|
||||||
//// io.simm5_0 := simm5_0
|
|
||||||
//// io.uimm9_2 := uimm9_2
|
|
||||||
//// io.simm9_4 := simm9_4
|
|
||||||
//// io.ulwimm6_2 := ulwimm6_2
|
|
||||||
//// io.ulwspimm7_2 := ulwspimm7_2
|
|
||||||
//// io.uimm5_0 := uimm5_0
|
|
||||||
////
|
|
||||||
// io.sjald := sjald
|
// io.sjald := sjald
|
||||||
// io.uimm5d := uimm5d
|
// io.uimm5d := uimm5d
|
||||||
// io.ulwspimm7d := ulwspimm7d
|
// io.ulwspimm7d := ulwspimm7d
|
||||||
|
|
@ -208,232 +199,232 @@ import chisel3.util._
|
||||||
// io.simm9d := simm9d//Output(UInt())
|
// io.simm9d := simm9d//Output(UInt())
|
||||||
// io.uimm9d := uimm9d//Output(UInt())
|
// io.uimm9d := uimm9d//Output(UInt())
|
||||||
// io.simm5d := simm5d//Output(UInt())
|
// io.simm5d := simm5d//Output(UInt())
|
||||||
|
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
//class ExpandedInstruction extends Bundle {
|
||||||
|
// val bits = UInt(32.W)
|
||||||
|
// val rd = UInt(5.W)
|
||||||
|
// val rs1 = UInt(5.W)
|
||||||
|
// val rs2 = UInt(5.W)
|
||||||
|
// val rs3 = UInt(5.W)
|
||||||
|
//}
|
||||||
|
//
|
||||||
|
//class RVCDecoder(x: UInt, xLen: Int) {
|
||||||
|
// def inst(bits: UInt, rd: UInt = x(11,7), rs1: UInt = x(19,15), rs2: UInt = x(24,20), rs3: UInt = x(31,27)) = {
|
||||||
|
// val res = Wire(new ExpandedInstruction)
|
||||||
|
// res.bits := bits
|
||||||
|
// res.rd := rd
|
||||||
|
// res.rs1 := rs1
|
||||||
|
// res.rs2 := rs2
|
||||||
|
// res.rs3 := rs3
|
||||||
|
// res
|
||||||
|
// }
|
||||||
|
//
|
||||||
|
// def rs1p = Cat(1.U(2.W), x(9,7))
|
||||||
|
// def rs2p = Cat(1.U(2.W), x(4,2))
|
||||||
|
// def rs2 = x(6,2)
|
||||||
|
// def rd = x(11,7)
|
||||||
|
// def addi4spnImm = Cat(x(10,7), x(12,11), x(5), x(6), 0.U(2.W))
|
||||||
|
// def lwImm = Cat(x(5), x(12,10), x(6), 0.U(2.W))
|
||||||
|
// def ldImm = Cat(x(6,5), x(12,10), 0.U(3.W))
|
||||||
|
// def lwspImm = Cat(x(3,2), x(12), x(6,4), 0.U(2.W))
|
||||||
|
// def ldspImm = Cat(x(4,2), x(12), x(6,5), 0.U(3.W))
|
||||||
|
// def swspImm = Cat(x(8,7), x(12,9), 0.U(2.W))
|
||||||
|
// def sdspImm = Cat(x(9,7), x(12,10), 0.U(3.W))
|
||||||
|
// def luiImm = Cat(Fill(15, x(12)), x(6,2), 0.U(12.W))
|
||||||
|
// def addi16spImm = Cat(Fill(3, x(12)), x(4,3), x(5), x(2), x(6), 0.U(4.W))
|
||||||
|
// def addiImm = Cat(Fill(7, x(12)), x(6,2))
|
||||||
|
// def jImm = Cat(Fill(10, x(12)), x(8), x(10,9), x(6), x(7), x(2), x(11), x(5,3), 0.U(1.W))
|
||||||
|
// def bImm = Cat(Fill(5, x(12)), x(6,5), x(2), x(11,10), x(4,3), 0.U(1.W))
|
||||||
|
// def shamt = Cat(x(12), x(6,2))
|
||||||
|
// def x0 = 0.U(5.W)
|
||||||
|
// def ra = 1.U(5.W)
|
||||||
|
// def sp = 2.U(5.W)
|
||||||
|
//
|
||||||
|
// def q0 = {
|
||||||
|
// def addi4spn = {
|
||||||
|
// val opc = Mux(x(12,5).orR, 0x13.U(7.W), 0x1F.U(7.W))
|
||||||
|
// inst(Cat(addi4spnImm, sp, 0.U(3.W), rs2p, opc), rs2p, sp, rs2p)
|
||||||
|
// }
|
||||||
|
// def ld = inst(Cat(ldImm, rs1p, 3.U(3.W), rs2p, 0x03.U(7.W)), rs2p, rs1p, rs2p)
|
||||||
|
// def lw = inst(Cat(lwImm, rs1p, 2.U(3.W), rs2p, 0x03.U(7.W)), rs2p, rs1p, rs2p)
|
||||||
|
// def fld = inst(Cat(ldImm, rs1p, 3.U(3.W), rs2p, 0x07.U(7.W)), rs2p, rs1p, rs2p)
|
||||||
|
// def flw = {
|
||||||
|
// if (xLen == 32) inst(Cat(lwImm, rs1p, 2.U(3.W), rs2p, 0x07.U(7.W)), rs2p, rs1p, rs2p)
|
||||||
|
// else ld
|
||||||
|
// }
|
||||||
|
// def unimp = inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x3F.U(7.W)), rs2p, rs1p, rs2p)
|
||||||
|
// def sd = inst(Cat(ldImm >> 5, rs2p, rs1p, 3.U(3.W), ldImm(4,0), 0x23.U(7.W)), rs2p, rs1p, rs2p)
|
||||||
|
// def sw = inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x23.U(7.W)), rs2p, rs1p, rs2p)
|
||||||
|
// def fsd = inst(Cat(ldImm >> 5, rs2p, rs1p, 3.U(3.W), ldImm(4,0), 0x27.U(7.W)), rs2p, rs1p, rs2p)
|
||||||
|
// def fsw = {
|
||||||
|
// if (xLen == 32) inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x27.U(7.W)), rs2p, rs1p, rs2p)
|
||||||
|
// else sd
|
||||||
|
// }
|
||||||
|
// Seq(addi4spn, fld, lw, flw, unimp, fsd, sw, fsw)
|
||||||
|
// }
|
||||||
|
//
|
||||||
|
// def q1 = {
|
||||||
|
// def addi = inst(Cat(addiImm, rd, 0.U(3.W), rd, 0x13.U(7.W)), rd, rd, rs2p)
|
||||||
|
// def addiw = {
|
||||||
|
// val opc = Mux(rd.orR, 0x1B.U(7.W), 0x1F.U(7.W))
|
||||||
|
// inst(Cat(addiImm, rd, 0.U(3.W), rd, opc), rd, rd, rs2p)
|
||||||
|
// }
|
||||||
|
// def jal = {
|
||||||
|
// if (xLen == 32) inst(Cat(jImm(20), jImm(10,1), jImm(11), jImm(19,12), ra, 0x6F.U(7.W)), ra, rd, rs2p)
|
||||||
|
// else addiw
|
||||||
|
// }
|
||||||
|
// def li = inst(Cat(addiImm, x0, 0.U(3.W), rd, 0x13.U(7.W)), rd, x0, rs2p)
|
||||||
|
// def addi16sp = {
|
||||||
|
// val opc = Mux(addiImm.orR, 0x13.U(7.W), 0x1F.U(7.W))
|
||||||
|
// inst(Cat(addi16spImm, rd, 0.U(3.W), rd, opc), rd, rd, rs2p)
|
||||||
|
// }
|
||||||
|
// def lui = {
|
||||||
|
// val opc = Mux(addiImm.orR, 0x37.U(7.W), 0x3F.U(7.W))
|
||||||
|
// val me = inst(Cat(luiImm(31,12), rd, opc), rd, rd, rs2p)
|
||||||
|
// Mux(rd === x0 || rd === sp, addi16sp, me)
|
||||||
|
// }
|
||||||
|
// def j = inst(Cat(jImm(20), jImm(10,1), jImm(11), jImm(19,12), x0, 0x6F.U(7.W)), x0, rs1p, rs2p)
|
||||||
|
// def beqz = inst(Cat(bImm(12), bImm(10,5), x0, rs1p, 0.U(3.W), bImm(4,1), bImm(11), 0x63.U(7.W)), rs1p, rs1p, x0)
|
||||||
|
// def bnez = inst(Cat(bImm(12), bImm(10,5), x0, rs1p, 1.U(3.W), bImm(4,1), bImm(11), 0x63.U(7.W)), x0, rs1p, x0)
|
||||||
|
// def arith = {
|
||||||
|
// def srli = Cat(shamt, rs1p, 5.U(3.W), rs1p, 0x13.U(7.W))
|
||||||
|
// def srai = srli | (1 << 30).U
|
||||||
|
// def andi = Cat(addiImm, rs1p, 7.U(3.W), rs1p, 0x13.U(7.W))
|
||||||
|
// def rtype = {
|
||||||
|
// val funct = VecInit(0.U, 4.U, 6.U, 7.U, 0.U, 0.U, 2.U, 3.U)(Cat(x(12), x(6,5)))
|
||||||
|
// val sub = Mux(x(6,5) === 0.U, (1 << 30).U, 0.U)
|
||||||
|
// val opc = Mux(x(12), 0x3B.U(7.W), 0x33.U(7.W))
|
||||||
|
// Cat(rs2p, rs1p, funct, rs1p, opc) | sub
|
||||||
|
// }
|
||||||
|
// inst(VecInit(srli, srai, andi, rtype)(x(11,10)), rs1p, rs1p, rs2p)
|
||||||
|
// }
|
||||||
|
// Seq(addi, jal, li, lui, arith, j, beqz, bnez)
|
||||||
|
// }
|
||||||
|
//
|
||||||
|
// def q2 = {
|
||||||
|
// val load_opc = Mux(rd.orR, 0x03.U(7.W), 0x1F.U(7.W))
|
||||||
|
// def slli = inst(Cat(shamt, rd, 1.U(3.W), rd, 0x13.U(7.W)), rd, rd, rs2)
|
||||||
|
// def ldsp = inst(Cat(ldspImm, sp, 3.U(3.W), rd, load_opc), rd, sp, rs2)
|
||||||
|
// def lwsp = inst(Cat(lwspImm, sp, 2.U(3.W), rd, load_opc), rd, sp, rs2)
|
||||||
|
// def fldsp = inst(Cat(ldspImm, sp, 3.U(3.W), rd, 0x07.U(7.W)), rd, sp, rs2)
|
||||||
|
// def flwsp = {
|
||||||
|
// if (xLen == 32) inst(Cat(lwspImm, sp, 2.U(3.W), rd, 0x07.U(7.W)), rd, sp, rs2)
|
||||||
|
// else ldsp
|
||||||
|
// }
|
||||||
|
// def sdsp = inst(Cat(sdspImm >> 5, rs2, sp, 3.U(3.W), sdspImm(4,0), 0x23.U(7.W)), rd, sp, rs2)
|
||||||
|
// def swsp = inst(Cat(swspImm >> 5, rs2, sp, 2.U(3.W), swspImm(4,0), 0x23.U(7.W)), rd, sp, rs2)
|
||||||
|
// def fsdsp = inst(Cat(sdspImm >> 5, rs2, sp, 3.U(3.W), sdspImm(4,0), 0x27.U(7.W)), rd, sp, rs2)
|
||||||
|
// def fswsp = {
|
||||||
|
// if (xLen == 32) inst(Cat(swspImm >> 5, rs2, sp, 2.U(3.W), swspImm(4,0), 0x27.U(7.W)), rd, sp, rs2)
|
||||||
|
// else sdsp
|
||||||
|
// }
|
||||||
|
// def jalr = {
|
||||||
|
// val mv = inst(Cat(rs2, x0, 0.U(3.W), rd, 0x33.U(7.W)), rd, x0, rs2)
|
||||||
|
// val add = inst(Cat(rs2, rd, 0.U(3.W), rd, 0x33.U(7.W)), rd, rd, rs2)
|
||||||
|
// val jr = Cat(rs2, rd, 0.U(3.W), x0, 0x67.U(7.W))
|
||||||
|
// val reserved = Cat(jr >> 7, 0x1F.U(7.W))
|
||||||
|
// val jr_reserved = inst(Mux(rd.orR, jr, reserved), x0, rd, rs2)
|
||||||
|
// val jr_mv = Mux(rs2.orR, mv, jr_reserved)
|
||||||
|
// val jalr = Cat(rs2, rd, 0.U(3.W), ra, 0x67.U(7.W))
|
||||||
|
// val ebreak = Cat(jr >> 7, 0x73.U(7.W)) | (1 << 20).U
|
||||||
|
// val jalr_ebreak = inst(Mux(rd.orR, jalr, ebreak), ra, rd, rs2)
|
||||||
|
// val jalr_add = Mux(rs2.orR, add, jalr_ebreak)
|
||||||
|
// Mux(x(12), jalr_add, jr_mv)
|
||||||
|
// }
|
||||||
|
// Seq(slli, fldsp, lwsp, flwsp, jalr, fsdsp, swsp, fswsp)
|
||||||
|
// }
|
||||||
|
//
|
||||||
|
// def q3 = Seq.fill(8)(passthrough)
|
||||||
|
//
|
||||||
|
// def passthrough = inst(x)
|
||||||
|
//
|
||||||
|
// def decode = {
|
||||||
|
// val s = VecInit(q0 ++ q1 ++ q2 ++ q3)
|
||||||
|
// s(Cat(x(1,0), x(15,13)))
|
||||||
|
// }
|
||||||
//
|
//
|
||||||
//
|
//
|
||||||
|
//
|
||||||
|
// def changed_q0 = {
|
||||||
|
// def addi4spn = {
|
||||||
|
// val opc = Mux(x(12,5).orR, 0x13.U(7.W), 0x1F.U(7.W))
|
||||||
|
// inst(Cat(addi4spnImm, sp, 0.U(3.W), rs2p, opc), rs2p, sp, rs2p)
|
||||||
|
// }
|
||||||
|
// def ld = inst(Cat(ldImm, rs1p, 3.U(3.W), rs2p, 0x03.U(7.W)), rs2p, rs1p, rs2p)
|
||||||
|
// def lw = inst(Cat(lwImm, rs1p, 2.U(3.W), rs2p, 0x03.U(7.W)), rs2p, rs1p, rs2p)
|
||||||
|
// def fld = inst(Cat(ldImm, rs1p, 3.U(3.W), rs2p, 0x07.U(7.W)), rs2p, rs1p, rs2p)
|
||||||
|
// def flw = {
|
||||||
|
// if (xLen == 32) inst(Cat(lwImm, rs1p, 2.U(3.W), rs2p, 0x07.U(7.W)), rs2p, rs1p, rs2p)
|
||||||
|
// else ld
|
||||||
|
// }
|
||||||
|
// def unimp = inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x3F.U(7.W)), rs2p, rs1p, rs2p)
|
||||||
|
// def sd = inst(Cat(ldImm >> 5, rs2p, rs1p, 3.U(3.W), ldImm(4,0), 0x23.U(7.W)), rs2p, rs1p, rs2p)
|
||||||
|
// def sw = inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x23.U(7.W)), rs2p, rs1p, rs2p)
|
||||||
|
// def fsd = inst(Cat(ldImm >> 5, rs2p, rs1p, 3.U(3.W), ldImm(4,0), 0x27.U(7.W)), rs2p, rs1p, rs2p)
|
||||||
|
// def fsw = {
|
||||||
|
// if (xLen == 32) inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x27.U(7.W)), rs2p, rs1p, rs2p)
|
||||||
|
// else sd
|
||||||
|
// }
|
||||||
|
// addi4spn
|
||||||
|
// }
|
||||||
|
//
|
||||||
|
// def ret_q0 = VecInit(q0)
|
||||||
|
// def ret_q1 = q1
|
||||||
|
// def ret_q2 = q2
|
||||||
|
// def ret_q3 = q3
|
||||||
|
//}
|
||||||
|
//
|
||||||
|
//class el2_ifu_compress_ctl( val XLen: Int, val usingCompressed: Boolean) extends Module {
|
||||||
|
// val io = IO(new Bundle {
|
||||||
|
// val din = Input(UInt(32.W))
|
||||||
|
// val dout = Output(new ExpandedInstruction)
|
||||||
|
// //val rvc = Output(Bool())
|
||||||
|
// //val legal = Output(Bool())
|
||||||
|
// //val waleed_out = Output(UInt(32.W))
|
||||||
|
// //val q1_Out = Output(new ExpandedInstruction)
|
||||||
|
// //val q2_Out = Output(new ExpandedInstruction)
|
||||||
|
// //val q3_Out = Output(new ExpandedInstruction)
|
||||||
|
// })
|
||||||
|
// if (usingCompressed) {
|
||||||
|
// val rvc = io.din(1,0) =/= 3.U
|
||||||
|
// val inst = new RVCDecoder(io.din, XLen)
|
||||||
|
// val decoded = inst.decode
|
||||||
|
// io.dout := inst.decode
|
||||||
|
// //io.out.rd := 0.U
|
||||||
|
// //io.out.rs1 := 0.U
|
||||||
|
// //io.out.rs2 := 0.U
|
||||||
|
// //io.out.rs3 := 0.U
|
||||||
|
// /*io.legal := (!io.in(13))&(!io.in(12))&(io.in(11))&io.in(1)&(!io.in(0)) |
|
||||||
|
// (!io.in(13))&(!io.in(12))&(io.in(6))&io.in(1)&(!io.in(0)) |
|
||||||
|
// (!io.in(15))&(!io.in(13))&io.in(11)(!io.in(1)) |
|
||||||
|
// (!io.in(13))&(!io.in(12))&io.in(5)&io.in(1)&(!io.in(0)) |
|
||||||
|
// (!io.in(13))&(!io.in(12))&io.in(10)&(!io.in(1))&io.in(0) |
|
||||||
|
// (!io.in(15))&(!io.in(13))&io.in(6)&(!io.in(1)) | io.in(15)&(!io.in(12))&(!io.in(1))&io.in(0) |
|
||||||
|
// (!io.in(13))&(!io.in(12))&io.in(9)&io.in(1)&(!io.in(0)) |
|
||||||
|
// (!io.in(12))&io.in(6)&(!io.in(1))&io.in(0) |
|
||||||
|
// (!io.in(15))&(!io.in(13))&io.in(5)&(!io.in(1)) |
|
||||||
|
// (!io.in(13))&(!io.in(12))&io.in(8)&io.in(1)&(!io.in(0)) |
|
||||||
|
// (!io.in(12))&io.in(5)&(!io.in(1))&io.in(0) |
|
||||||
|
// (!io.in(15))&(!io.in(13))&io.in(10)&(!io.in(1)) | (!io.in(13))&(!io.in(12))&io.in(7)&io.in(1)&(!io.in(0)) |
|
||||||
|
// io.in(12)&io.in(11)&(!io.in(10))&(!io.in(1))&io.in(0) | (!io.in(15))&(!io.in(13))&io.in(9)&(!io.in(1)) |
|
||||||
|
// (!io.in(13))&(!io.in(12))&io.in(4)&io.in(1)&(!io.in(0)) | io.in(13)&io.in(12)&(!io.in(1))&io.in(0) |
|
||||||
|
// (!io.in(15))&(!io.in(13))&io.in(8)&(!io.in(1)) | (!io.in(13))&(!io.in(12))&io.in(3)&io.in(1)&(!io.in(0)) |
|
||||||
|
// io.in(13)&io.in(4)&(!io.in(1))&io.in(0) | (!io.in(13))&(!io.in(12))&io.in(2)&io.in(1)&(!io.in(0)) |
|
||||||
|
// (!io.in(15))&(!io.in(13))&io.in(7)&(!io.in(1)) | io.in(13)&io.in(3)&(!io.in(1))&io.in(0) |
|
||||||
|
// io.in(13)&io.in(2)&(!io.in(1))&io.in(0) | io.in(14)&(!io.in(13))&(!io.in(1)) |
|
||||||
|
// (!io.in(14))&(!io.in(12))&(!io.in(1))&io.in(0) | io.in(15)&(!io.in(13))&io.in(12)&io.in(1)&(!io.in(0)) |
|
||||||
|
// (!io.in(15))&(!io.in(13))&(!io.in(12))&io.in(1)&(!io.in(0)) | (!io.in(15))&(!io.in(13))&io.in(12)&(!io.in(1)) |
|
||||||
|
// io.in(14)&(!io.in(13))&(!io.in(0))
|
||||||
|
// io.waleed_out := Mux(io.legal,io.out.bits,0.U)*/
|
||||||
|
// } else {
|
||||||
|
// //io.rvc := false.B
|
||||||
|
// io.dout := new RVCDecoder(io.din, XLen).passthrough
|
||||||
|
// }
|
||||||
//}
|
//}
|
||||||
|
|
||||||
class ExpandedInstruction extends Bundle {
|
|
||||||
val bits = UInt(32.W)
|
|
||||||
val rd = UInt(5.W)
|
|
||||||
val rs1 = UInt(5.W)
|
|
||||||
val rs2 = UInt(5.W)
|
|
||||||
val rs3 = UInt(5.W)
|
|
||||||
}
|
|
||||||
|
|
||||||
class RVCDecoder(x: UInt, xLen: Int) {
|
|
||||||
def inst(bits: UInt, rd: UInt = x(11,7), rs1: UInt = x(19,15), rs2: UInt = x(24,20), rs3: UInt = x(31,27)) = {
|
|
||||||
val res = Wire(new ExpandedInstruction)
|
|
||||||
res.bits := bits
|
|
||||||
res.rd := rd
|
|
||||||
res.rs1 := rs1
|
|
||||||
res.rs2 := rs2
|
|
||||||
res.rs3 := rs3
|
|
||||||
res
|
|
||||||
}
|
|
||||||
|
|
||||||
def rs1p = Cat(1.U(2.W), x(9,7))
|
|
||||||
def rs2p = Cat(1.U(2.W), x(4,2))
|
|
||||||
def rs2 = x(6,2)
|
|
||||||
def rd = x(11,7)
|
|
||||||
def addi4spnImm = Cat(x(10,7), x(12,11), x(5), x(6), 0.U(2.W))
|
|
||||||
def lwImm = Cat(x(5), x(12,10), x(6), 0.U(2.W))
|
|
||||||
def ldImm = Cat(x(6,5), x(12,10), 0.U(3.W))
|
|
||||||
def lwspImm = Cat(x(3,2), x(12), x(6,4), 0.U(2.W))
|
|
||||||
def ldspImm = Cat(x(4,2), x(12), x(6,5), 0.U(3.W))
|
|
||||||
def swspImm = Cat(x(8,7), x(12,9), 0.U(2.W))
|
|
||||||
def sdspImm = Cat(x(9,7), x(12,10), 0.U(3.W))
|
|
||||||
def luiImm = Cat(Fill(15, x(12)), x(6,2), 0.U(12.W))
|
|
||||||
def addi16spImm = Cat(Fill(3, x(12)), x(4,3), x(5), x(2), x(6), 0.U(4.W))
|
|
||||||
def addiImm = Cat(Fill(7, x(12)), x(6,2))
|
|
||||||
def jImm = Cat(Fill(10, x(12)), x(8), x(10,9), x(6), x(7), x(2), x(11), x(5,3), 0.U(1.W))
|
|
||||||
def bImm = Cat(Fill(5, x(12)), x(6,5), x(2), x(11,10), x(4,3), 0.U(1.W))
|
|
||||||
def shamt = Cat(x(12), x(6,2))
|
|
||||||
def x0 = 0.U(5.W)
|
|
||||||
def ra = 1.U(5.W)
|
|
||||||
def sp = 2.U(5.W)
|
|
||||||
|
|
||||||
def q0 = {
|
|
||||||
def addi4spn = {
|
|
||||||
val opc = Mux(x(12,5).orR, 0x13.U(7.W), 0x1F.U(7.W))
|
|
||||||
inst(Cat(addi4spnImm, sp, 0.U(3.W), rs2p, opc), rs2p, sp, rs2p)
|
|
||||||
}
|
|
||||||
def ld = inst(Cat(ldImm, rs1p, 3.U(3.W), rs2p, 0x03.U(7.W)), rs2p, rs1p, rs2p)
|
|
||||||
def lw = inst(Cat(lwImm, rs1p, 2.U(3.W), rs2p, 0x03.U(7.W)), rs2p, rs1p, rs2p)
|
|
||||||
def fld = inst(Cat(ldImm, rs1p, 3.U(3.W), rs2p, 0x07.U(7.W)), rs2p, rs1p, rs2p)
|
|
||||||
def flw = {
|
|
||||||
if (xLen == 32) inst(Cat(lwImm, rs1p, 2.U(3.W), rs2p, 0x07.U(7.W)), rs2p, rs1p, rs2p)
|
|
||||||
else ld
|
|
||||||
}
|
|
||||||
def unimp = inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x3F.U(7.W)), rs2p, rs1p, rs2p)
|
|
||||||
def sd = inst(Cat(ldImm >> 5, rs2p, rs1p, 3.U(3.W), ldImm(4,0), 0x23.U(7.W)), rs2p, rs1p, rs2p)
|
|
||||||
def sw = inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x23.U(7.W)), rs2p, rs1p, rs2p)
|
|
||||||
def fsd = inst(Cat(ldImm >> 5, rs2p, rs1p, 3.U(3.W), ldImm(4,0), 0x27.U(7.W)), rs2p, rs1p, rs2p)
|
|
||||||
def fsw = {
|
|
||||||
if (xLen == 32) inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x27.U(7.W)), rs2p, rs1p, rs2p)
|
|
||||||
else sd
|
|
||||||
}
|
|
||||||
Seq(addi4spn, fld, lw, flw, unimp, fsd, sw, fsw)
|
|
||||||
}
|
|
||||||
|
|
||||||
def q1 = {
|
|
||||||
def addi = inst(Cat(addiImm, rd, 0.U(3.W), rd, 0x13.U(7.W)), rd, rd, rs2p)
|
|
||||||
def addiw = {
|
|
||||||
val opc = Mux(rd.orR, 0x1B.U(7.W), 0x1F.U(7.W))
|
|
||||||
inst(Cat(addiImm, rd, 0.U(3.W), rd, opc), rd, rd, rs2p)
|
|
||||||
}
|
|
||||||
def jal = {
|
|
||||||
if (xLen == 32) inst(Cat(jImm(20), jImm(10,1), jImm(11), jImm(19,12), ra, 0x6F.U(7.W)), ra, rd, rs2p)
|
|
||||||
else addiw
|
|
||||||
}
|
|
||||||
def li = inst(Cat(addiImm, x0, 0.U(3.W), rd, 0x13.U(7.W)), rd, x0, rs2p)
|
|
||||||
def addi16sp = {
|
|
||||||
val opc = Mux(addiImm.orR, 0x13.U(7.W), 0x1F.U(7.W))
|
|
||||||
inst(Cat(addi16spImm, rd, 0.U(3.W), rd, opc), rd, rd, rs2p)
|
|
||||||
}
|
|
||||||
def lui = {
|
|
||||||
val opc = Mux(addiImm.orR, 0x37.U(7.W), 0x3F.U(7.W))
|
|
||||||
val me = inst(Cat(luiImm(31,12), rd, opc), rd, rd, rs2p)
|
|
||||||
Mux(rd === x0 || rd === sp, addi16sp, me)
|
|
||||||
}
|
|
||||||
def j = inst(Cat(jImm(20), jImm(10,1), jImm(11), jImm(19,12), x0, 0x6F.U(7.W)), x0, rs1p, rs2p)
|
|
||||||
def beqz = inst(Cat(bImm(12), bImm(10,5), x0, rs1p, 0.U(3.W), bImm(4,1), bImm(11), 0x63.U(7.W)), rs1p, rs1p, x0)
|
|
||||||
def bnez = inst(Cat(bImm(12), bImm(10,5), x0, rs1p, 1.U(3.W), bImm(4,1), bImm(11), 0x63.U(7.W)), x0, rs1p, x0)
|
|
||||||
def arith = {
|
|
||||||
def srli = Cat(shamt, rs1p, 5.U(3.W), rs1p, 0x13.U(7.W))
|
|
||||||
def srai = srli | (1 << 30).U
|
|
||||||
def andi = Cat(addiImm, rs1p, 7.U(3.W), rs1p, 0x13.U(7.W))
|
|
||||||
def rtype = {
|
|
||||||
val funct = VecInit(0.U, 4.U, 6.U, 7.U, 0.U, 0.U, 2.U, 3.U)(Cat(x(12), x(6,5)))
|
|
||||||
val sub = Mux(x(6,5) === 0.U, (1 << 30).U, 0.U)
|
|
||||||
val opc = Mux(x(12), 0x3B.U(7.W), 0x33.U(7.W))
|
|
||||||
Cat(rs2p, rs1p, funct, rs1p, opc) | sub
|
|
||||||
}
|
|
||||||
inst(VecInit(srli, srai, andi, rtype)(x(11,10)), rs1p, rs1p, rs2p)
|
|
||||||
}
|
|
||||||
Seq(addi, jal, li, lui, arith, j, beqz, bnez)
|
|
||||||
}
|
|
||||||
|
|
||||||
def q2 = {
|
|
||||||
val load_opc = Mux(rd.orR, 0x03.U(7.W), 0x1F.U(7.W))
|
|
||||||
def slli = inst(Cat(shamt, rd, 1.U(3.W), rd, 0x13.U(7.W)), rd, rd, rs2)
|
|
||||||
def ldsp = inst(Cat(ldspImm, sp, 3.U(3.W), rd, load_opc), rd, sp, rs2)
|
|
||||||
def lwsp = inst(Cat(lwspImm, sp, 2.U(3.W), rd, load_opc), rd, sp, rs2)
|
|
||||||
def fldsp = inst(Cat(ldspImm, sp, 3.U(3.W), rd, 0x07.U(7.W)), rd, sp, rs2)
|
|
||||||
def flwsp = {
|
|
||||||
if (xLen == 32) inst(Cat(lwspImm, sp, 2.U(3.W), rd, 0x07.U(7.W)), rd, sp, rs2)
|
|
||||||
else ldsp
|
|
||||||
}
|
|
||||||
def sdsp = inst(Cat(sdspImm >> 5, rs2, sp, 3.U(3.W), sdspImm(4,0), 0x23.U(7.W)), rd, sp, rs2)
|
|
||||||
def swsp = inst(Cat(swspImm >> 5, rs2, sp, 2.U(3.W), swspImm(4,0), 0x23.U(7.W)), rd, sp, rs2)
|
|
||||||
def fsdsp = inst(Cat(sdspImm >> 5, rs2, sp, 3.U(3.W), sdspImm(4,0), 0x27.U(7.W)), rd, sp, rs2)
|
|
||||||
def fswsp = {
|
|
||||||
if (xLen == 32) inst(Cat(swspImm >> 5, rs2, sp, 2.U(3.W), swspImm(4,0), 0x27.U(7.W)), rd, sp, rs2)
|
|
||||||
else sdsp
|
|
||||||
}
|
|
||||||
def jalr = {
|
|
||||||
val mv = inst(Cat(rs2, x0, 0.U(3.W), rd, 0x33.U(7.W)), rd, x0, rs2)
|
|
||||||
val add = inst(Cat(rs2, rd, 0.U(3.W), rd, 0x33.U(7.W)), rd, rd, rs2)
|
|
||||||
val jr = Cat(rs2, rd, 0.U(3.W), x0, 0x67.U(7.W))
|
|
||||||
val reserved = Cat(jr >> 7, 0x1F.U(7.W))
|
|
||||||
val jr_reserved = inst(Mux(rd.orR, jr, reserved), x0, rd, rs2)
|
|
||||||
val jr_mv = Mux(rs2.orR, mv, jr_reserved)
|
|
||||||
val jalr = Cat(rs2, rd, 0.U(3.W), ra, 0x67.U(7.W))
|
|
||||||
val ebreak = Cat(jr >> 7, 0x73.U(7.W)) | (1 << 20).U
|
|
||||||
val jalr_ebreak = inst(Mux(rd.orR, jalr, ebreak), ra, rd, rs2)
|
|
||||||
val jalr_add = Mux(rs2.orR, add, jalr_ebreak)
|
|
||||||
Mux(x(12), jalr_add, jr_mv)
|
|
||||||
}
|
|
||||||
Seq(slli, fldsp, lwsp, flwsp, jalr, fsdsp, swsp, fswsp)
|
|
||||||
}
|
|
||||||
|
|
||||||
def q3 = Seq.fill(8)(passthrough)
|
|
||||||
|
|
||||||
def passthrough = inst(x)
|
|
||||||
|
|
||||||
def decode = {
|
|
||||||
val s = VecInit(q0 ++ q1 ++ q2 ++ q3)
|
|
||||||
s(Cat(x(1,0), x(15,13)))
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
def changed_q0 = {
|
|
||||||
def addi4spn = {
|
|
||||||
val opc = Mux(x(12,5).orR, 0x13.U(7.W), 0x1F.U(7.W))
|
|
||||||
inst(Cat(addi4spnImm, sp, 0.U(3.W), rs2p, opc), rs2p, sp, rs2p)
|
|
||||||
}
|
|
||||||
def ld = inst(Cat(ldImm, rs1p, 3.U(3.W), rs2p, 0x03.U(7.W)), rs2p, rs1p, rs2p)
|
|
||||||
def lw = inst(Cat(lwImm, rs1p, 2.U(3.W), rs2p, 0x03.U(7.W)), rs2p, rs1p, rs2p)
|
|
||||||
def fld = inst(Cat(ldImm, rs1p, 3.U(3.W), rs2p, 0x07.U(7.W)), rs2p, rs1p, rs2p)
|
|
||||||
def flw = {
|
|
||||||
if (xLen == 32) inst(Cat(lwImm, rs1p, 2.U(3.W), rs2p, 0x07.U(7.W)), rs2p, rs1p, rs2p)
|
|
||||||
else ld
|
|
||||||
}
|
|
||||||
def unimp = inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x3F.U(7.W)), rs2p, rs1p, rs2p)
|
|
||||||
def sd = inst(Cat(ldImm >> 5, rs2p, rs1p, 3.U(3.W), ldImm(4,0), 0x23.U(7.W)), rs2p, rs1p, rs2p)
|
|
||||||
def sw = inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x23.U(7.W)), rs2p, rs1p, rs2p)
|
|
||||||
def fsd = inst(Cat(ldImm >> 5, rs2p, rs1p, 3.U(3.W), ldImm(4,0), 0x27.U(7.W)), rs2p, rs1p, rs2p)
|
|
||||||
def fsw = {
|
|
||||||
if (xLen == 32) inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x27.U(7.W)), rs2p, rs1p, rs2p)
|
|
||||||
else sd
|
|
||||||
}
|
|
||||||
addi4spn
|
|
||||||
}
|
|
||||||
|
|
||||||
def ret_q0 = VecInit(q0)
|
|
||||||
def ret_q1 = q1
|
|
||||||
def ret_q2 = q2
|
|
||||||
def ret_q3 = q3
|
|
||||||
}
|
|
||||||
|
|
||||||
class el2_ifu_compress_ctl( val XLen: Int, val usingCompressed: Boolean) extends Module {
|
|
||||||
val io = IO(new Bundle {
|
|
||||||
val din = Input(UInt(32.W))
|
|
||||||
val dout = Output(new ExpandedInstruction)
|
|
||||||
//val rvc = Output(Bool())
|
|
||||||
//val legal = Output(Bool())
|
|
||||||
//val waleed_out = Output(UInt(32.W))
|
|
||||||
//val q1_Out = Output(new ExpandedInstruction)
|
|
||||||
//val q2_Out = Output(new ExpandedInstruction)
|
|
||||||
//val q3_Out = Output(new ExpandedInstruction)
|
|
||||||
})
|
|
||||||
if (usingCompressed) {
|
|
||||||
val rvc = io.din(1,0) =/= 3.U
|
|
||||||
val inst = new RVCDecoder(io.din, XLen)
|
|
||||||
val decoded = inst.decode
|
|
||||||
io.dout := inst.decode
|
|
||||||
//io.out.rd := 0.U
|
|
||||||
//io.out.rs1 := 0.U
|
|
||||||
//io.out.rs2 := 0.U
|
|
||||||
//io.out.rs3 := 0.U
|
|
||||||
/*io.legal := (!io.in(13))&(!io.in(12))&(io.in(11))&io.in(1)&(!io.in(0)) |
|
|
||||||
(!io.in(13))&(!io.in(12))&(io.in(6))&io.in(1)&(!io.in(0)) |
|
|
||||||
(!io.in(15))&(!io.in(13))&io.in(11)(!io.in(1)) |
|
|
||||||
(!io.in(13))&(!io.in(12))&io.in(5)&io.in(1)&(!io.in(0)) |
|
|
||||||
(!io.in(13))&(!io.in(12))&io.in(10)&(!io.in(1))&io.in(0) |
|
|
||||||
(!io.in(15))&(!io.in(13))&io.in(6)&(!io.in(1)) | io.in(15)&(!io.in(12))&(!io.in(1))&io.in(0) |
|
|
||||||
(!io.in(13))&(!io.in(12))&io.in(9)&io.in(1)&(!io.in(0)) |
|
|
||||||
(!io.in(12))&io.in(6)&(!io.in(1))&io.in(0) |
|
|
||||||
(!io.in(15))&(!io.in(13))&io.in(5)&(!io.in(1)) |
|
|
||||||
(!io.in(13))&(!io.in(12))&io.in(8)&io.in(1)&(!io.in(0)) |
|
|
||||||
(!io.in(12))&io.in(5)&(!io.in(1))&io.in(0) |
|
|
||||||
(!io.in(15))&(!io.in(13))&io.in(10)&(!io.in(1)) | (!io.in(13))&(!io.in(12))&io.in(7)&io.in(1)&(!io.in(0)) |
|
|
||||||
io.in(12)&io.in(11)&(!io.in(10))&(!io.in(1))&io.in(0) | (!io.in(15))&(!io.in(13))&io.in(9)&(!io.in(1)) |
|
|
||||||
(!io.in(13))&(!io.in(12))&io.in(4)&io.in(1)&(!io.in(0)) | io.in(13)&io.in(12)&(!io.in(1))&io.in(0) |
|
|
||||||
(!io.in(15))&(!io.in(13))&io.in(8)&(!io.in(1)) | (!io.in(13))&(!io.in(12))&io.in(3)&io.in(1)&(!io.in(0)) |
|
|
||||||
io.in(13)&io.in(4)&(!io.in(1))&io.in(0) | (!io.in(13))&(!io.in(12))&io.in(2)&io.in(1)&(!io.in(0)) |
|
|
||||||
(!io.in(15))&(!io.in(13))&io.in(7)&(!io.in(1)) | io.in(13)&io.in(3)&(!io.in(1))&io.in(0) |
|
|
||||||
io.in(13)&io.in(2)&(!io.in(1))&io.in(0) | io.in(14)&(!io.in(13))&(!io.in(1)) |
|
|
||||||
(!io.in(14))&(!io.in(12))&(!io.in(1))&io.in(0) | io.in(15)&(!io.in(13))&io.in(12)&io.in(1)&(!io.in(0)) |
|
|
||||||
(!io.in(15))&(!io.in(13))&(!io.in(12))&io.in(1)&(!io.in(0)) | (!io.in(15))&(!io.in(13))&io.in(12)&(!io.in(1)) |
|
|
||||||
io.in(14)&(!io.in(13))&(!io.in(0))
|
|
||||||
io.waleed_out := Mux(io.legal,io.out.bits,0.U)*/
|
|
||||||
} else {
|
|
||||||
//io.rvc := false.B
|
|
||||||
io.dout := new RVCDecoder(io.din, XLen).passthrough
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
object ifu_compress extends App {
|
object ifu_compress extends App {
|
||||||
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_compress_ctl(32, true)))
|
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_compress_ctl()))
|
||||||
}
|
}
|
||||||
|
|
|
||||||
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Reference in New Issue