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ICCM Flop done

This commit is contained in:
waleed-lm 2020-10-08 11:27:32 +05:00
parent a885b0e1a7
commit 7ba865dcba
4 changed files with 57 additions and 57 deletions
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48
el2_ifu_iccm_mem.fir
View File

@ -23,30 +23,30 @@ circuit el2_ifu_iccm_mem :
iccm_bank_wr_data[2] <= _T_7 @[el2_ifu_iccm_mem.scala 29:32] iccm_bank_wr_data[2] <= _T_7 @[el2_ifu_iccm_mem.scala 29:32]
node _T_8 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 30:54] node _T_8 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 30:54]
iccm_bank_wr_data[3] <= _T_8 @[el2_ifu_iccm_mem.scala 30:36] iccm_bank_wr_data[3] <= _T_8 @[el2_ifu_iccm_mem.scala 30:36]
node _T_9 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 33:81] node _T_9 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 33:82]
node _T_10 = eq(_T_9, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 33:99] node _T_10 = eq(_T_9, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 33:100]
node _T_11 = and(io.iccm_wren, _T_10) @[el2_ifu_iccm_mem.scala 33:64] node _T_11 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 33:122]
node _T_12 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 33:121] node _T_12 = eq(_T_11, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 33:140]
node _T_13 = eq(_T_12, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 33:139] node _T_13 = or(_T_10, _T_12) @[el2_ifu_iccm_mem.scala 33:107]
node wren_bank_0 = or(_T_11, _T_13) @[el2_ifu_iccm_mem.scala 33:106] node wren_bank_0 = and(io.iccm_wren, _T_13) @[el2_ifu_iccm_mem.scala 33:64]
node _T_14 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 33:81] node _T_14 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 33:82]
node _T_15 = eq(_T_14, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 33:99] node _T_15 = eq(_T_14, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 33:100]
node _T_16 = and(io.iccm_wren, _T_15) @[el2_ifu_iccm_mem.scala 33:64] node _T_16 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 33:122]
node _T_17 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 33:121] node _T_17 = eq(_T_16, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 33:140]
node _T_18 = eq(_T_17, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 33:139] node _T_18 = or(_T_15, _T_17) @[el2_ifu_iccm_mem.scala 33:107]
node wren_bank_1 = or(_T_16, _T_18) @[el2_ifu_iccm_mem.scala 33:106] node wren_bank_1 = and(io.iccm_wren, _T_18) @[el2_ifu_iccm_mem.scala 33:64]
node _T_19 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 33:81] node _T_19 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 33:82]
node _T_20 = eq(_T_19, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 33:99] node _T_20 = eq(_T_19, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 33:100]
node _T_21 = and(io.iccm_wren, _T_20) @[el2_ifu_iccm_mem.scala 33:64] node _T_21 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 33:122]
node _T_22 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 33:121] node _T_22 = eq(_T_21, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 33:140]
node _T_23 = eq(_T_22, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 33:139] node _T_23 = or(_T_20, _T_22) @[el2_ifu_iccm_mem.scala 33:107]
node wren_bank_2 = or(_T_21, _T_23) @[el2_ifu_iccm_mem.scala 33:106] node wren_bank_2 = and(io.iccm_wren, _T_23) @[el2_ifu_iccm_mem.scala 33:64]
node _T_24 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 33:81] node _T_24 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 33:82]
node _T_25 = eq(_T_24, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 33:99] node _T_25 = eq(_T_24, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 33:100]
node _T_26 = and(io.iccm_wren, _T_25) @[el2_ifu_iccm_mem.scala 33:64] node _T_26 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 33:122]
node _T_27 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 33:121] node _T_27 = eq(_T_26, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 33:140]
node _T_28 = eq(_T_27, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 33:139] node _T_28 = or(_T_25, _T_27) @[el2_ifu_iccm_mem.scala 33:107]
node wren_bank_3 = or(_T_26, _T_28) @[el2_ifu_iccm_mem.scala 33:106] node wren_bank_3 = and(io.iccm_wren, _T_28) @[el2_ifu_iccm_mem.scala 33:64]
io.iccm_bank_wr_data[0] <= iccm_bank_wr_data[0] @[el2_ifu_iccm_mem.scala 35:24] io.iccm_bank_wr_data[0] <= iccm_bank_wr_data[0] @[el2_ifu_iccm_mem.scala 35:24]
io.iccm_bank_wr_data[1] <= iccm_bank_wr_data[1] @[el2_ifu_iccm_mem.scala 35:24] io.iccm_bank_wr_data[1] <= iccm_bank_wr_data[1] @[el2_ifu_iccm_mem.scala 35:24]
io.iccm_bank_wr_data[2] <= iccm_bank_wr_data[2] @[el2_ifu_iccm_mem.scala 35:24] io.iccm_bank_wr_data[2] <= iccm_bank_wr_data[2] @[el2_ifu_iccm_mem.scala 35:24]

64
el2_ifu_iccm_mem.v
View File

@ -122,30 +122,30 @@ module el2_ifu_iccm_mem(
wire [14:0] addr_bank_inc = io_iccm_rw_addr + _GEN_15; // @[el2_ifu_iccm_mem.scala 25:54] wire [14:0] addr_bank_inc = io_iccm_rw_addr + _GEN_15; // @[el2_ifu_iccm_mem.scala 25:54]
wire [38:0] iccm_bank_wr_data_0 = io_iccm_wr_data[38:0]; // @[el2_ifu_iccm_mem.scala 29:50] wire [38:0] iccm_bank_wr_data_0 = io_iccm_wr_data[38:0]; // @[el2_ifu_iccm_mem.scala 29:50]
wire [38:0] iccm_bank_wr_data_1 = io_iccm_wr_data[77:39]; // @[el2_ifu_iccm_mem.scala 30:54] wire [38:0] iccm_bank_wr_data_1 = io_iccm_wr_data[77:39]; // @[el2_ifu_iccm_mem.scala 30:54]
wire _T_10 = io_iccm_rw_addr[2:1] == 2'h0; // @[el2_ifu_iccm_mem.scala 33:99] wire _T_10 = io_iccm_rw_addr[2:1] == 2'h0; // @[el2_ifu_iccm_mem.scala 33:100]
wire _T_11 = io_iccm_wren & _T_10; // @[el2_ifu_iccm_mem.scala 33:64] wire _T_12 = addr_bank_inc[2:1] == 2'h0; // @[el2_ifu_iccm_mem.scala 33:140]
wire _T_13 = addr_bank_inc[2:1] == 2'h0; // @[el2_ifu_iccm_mem.scala 33:139] wire _T_13 = _T_10 | _T_12; // @[el2_ifu_iccm_mem.scala 33:107]
wire wren_bank_0 = _T_11 | _T_13; // @[el2_ifu_iccm_mem.scala 33:106] wire wren_bank_0 = io_iccm_wren & _T_13; // @[el2_ifu_iccm_mem.scala 33:64]
wire _T_15 = io_iccm_rw_addr[2:1] == 2'h1; // @[el2_ifu_iccm_mem.scala 33:99] wire _T_15 = io_iccm_rw_addr[2:1] == 2'h1; // @[el2_ifu_iccm_mem.scala 33:100]
wire _T_16 = io_iccm_wren & _T_15; // @[el2_ifu_iccm_mem.scala 33:64] wire _T_17 = addr_bank_inc[2:1] == 2'h1; // @[el2_ifu_iccm_mem.scala 33:140]
wire _T_18 = addr_bank_inc[2:1] == 2'h1; // @[el2_ifu_iccm_mem.scala 33:139] wire _T_18 = _T_15 | _T_17; // @[el2_ifu_iccm_mem.scala 33:107]
wire wren_bank_1 = _T_16 | _T_18; // @[el2_ifu_iccm_mem.scala 33:106] wire wren_bank_1 = io_iccm_wren & _T_18; // @[el2_ifu_iccm_mem.scala 33:64]
wire _T_20 = io_iccm_rw_addr[2:1] == 2'h2; // @[el2_ifu_iccm_mem.scala 33:99] wire _T_20 = io_iccm_rw_addr[2:1] == 2'h2; // @[el2_ifu_iccm_mem.scala 33:100]
wire _T_21 = io_iccm_wren & _T_20; // @[el2_ifu_iccm_mem.scala 33:64] wire _T_22 = addr_bank_inc[2:1] == 2'h2; // @[el2_ifu_iccm_mem.scala 33:140]
wire _T_23 = addr_bank_inc[2:1] == 2'h2; // @[el2_ifu_iccm_mem.scala 33:139] wire _T_23 = _T_20 | _T_22; // @[el2_ifu_iccm_mem.scala 33:107]
wire wren_bank_2 = _T_21 | _T_23; // @[el2_ifu_iccm_mem.scala 33:106] wire wren_bank_2 = io_iccm_wren & _T_23; // @[el2_ifu_iccm_mem.scala 33:64]
wire _T_25 = io_iccm_rw_addr[2:1] == 2'h3; // @[el2_ifu_iccm_mem.scala 33:99] wire _T_25 = io_iccm_rw_addr[2:1] == 2'h3; // @[el2_ifu_iccm_mem.scala 33:100]
wire _T_26 = io_iccm_wren & _T_25; // @[el2_ifu_iccm_mem.scala 33:64] wire _T_27 = addr_bank_inc[2:1] == 2'h3; // @[el2_ifu_iccm_mem.scala 33:140]
wire _T_28 = addr_bank_inc[2:1] == 2'h3; // @[el2_ifu_iccm_mem.scala 33:139] wire _T_28 = _T_25 | _T_27; // @[el2_ifu_iccm_mem.scala 33:107]
wire wren_bank_3 = _T_26 | _T_28; // @[el2_ifu_iccm_mem.scala 33:106] wire wren_bank_3 = io_iccm_wren & _T_28; // @[el2_ifu_iccm_mem.scala 33:64]
wire _T_31 = io_iccm_rden & _T_10; // @[el2_ifu_iccm_mem.scala 36:64] wire _T_31 = io_iccm_rden & _T_10; // @[el2_ifu_iccm_mem.scala 36:64]
wire rden_bank_0 = _T_31 | _T_13; // @[el2_ifu_iccm_mem.scala 36:106] wire rden_bank_0 = _T_31 | _T_12; // @[el2_ifu_iccm_mem.scala 36:106]
wire _T_36 = io_iccm_rden & _T_15; // @[el2_ifu_iccm_mem.scala 36:64] wire _T_36 = io_iccm_rden & _T_15; // @[el2_ifu_iccm_mem.scala 36:64]
wire rden_bank_1 = _T_36 | _T_18; // @[el2_ifu_iccm_mem.scala 36:106] wire rden_bank_1 = _T_36 | _T_17; // @[el2_ifu_iccm_mem.scala 36:106]
wire _T_41 = io_iccm_rden & _T_20; // @[el2_ifu_iccm_mem.scala 36:64] wire _T_41 = io_iccm_rden & _T_20; // @[el2_ifu_iccm_mem.scala 36:64]
wire rden_bank_2 = _T_41 | _T_23; // @[el2_ifu_iccm_mem.scala 36:106] wire rden_bank_2 = _T_41 | _T_22; // @[el2_ifu_iccm_mem.scala 36:106]
wire _T_46 = io_iccm_rden & _T_25; // @[el2_ifu_iccm_mem.scala 36:64] wire _T_46 = io_iccm_rden & _T_25; // @[el2_ifu_iccm_mem.scala 36:64]
wire rden_bank_3 = _T_46 | _T_28; // @[el2_ifu_iccm_mem.scala 36:106] wire rden_bank_3 = _T_46 | _T_27; // @[el2_ifu_iccm_mem.scala 36:106]
wire _T_49 = wren_bank_0 | rden_bank_0; // @[el2_ifu_iccm_mem.scala 37:72] wire _T_49 = wren_bank_0 | rden_bank_0; // @[el2_ifu_iccm_mem.scala 37:72]
wire iccm_clken_0 = _T_49 | io_clk_override; // @[el2_ifu_iccm_mem.scala 37:87] wire iccm_clken_0 = _T_49 | io_clk_override; // @[el2_ifu_iccm_mem.scala 37:87]
wire _T_50 = wren_bank_1 | rden_bank_1; // @[el2_ifu_iccm_mem.scala 37:72] wire _T_50 = wren_bank_1 | rden_bank_1; // @[el2_ifu_iccm_mem.scala 37:72]
@ -154,10 +154,10 @@ module el2_ifu_iccm_mem(
wire iccm_clken_2 = _T_51 | io_clk_override; // @[el2_ifu_iccm_mem.scala 37:87] wire iccm_clken_2 = _T_51 | io_clk_override; // @[el2_ifu_iccm_mem.scala 37:87]
wire _T_52 = wren_bank_3 | rden_bank_3; // @[el2_ifu_iccm_mem.scala 37:72] wire _T_52 = wren_bank_3 | rden_bank_3; // @[el2_ifu_iccm_mem.scala 37:72]
wire iccm_clken_3 = _T_52 | io_clk_override; // @[el2_ifu_iccm_mem.scala 37:87] wire iccm_clken_3 = _T_52 | io_clk_override; // @[el2_ifu_iccm_mem.scala 37:87]
wire [11:0] _T_59 = _T_13 ? addr_bank_inc[14:3] : io_iccm_rw_addr[14:3]; // @[el2_ifu_iccm_mem.scala 39:8] wire [11:0] _T_59 = _T_12 ? addr_bank_inc[14:3] : io_iccm_rw_addr[14:3]; // @[el2_ifu_iccm_mem.scala 39:8]
wire [11:0] _T_66 = _T_18 ? addr_bank_inc[14:3] : io_iccm_rw_addr[14:3]; // @[el2_ifu_iccm_mem.scala 39:8] wire [11:0] _T_66 = _T_17 ? addr_bank_inc[14:3] : io_iccm_rw_addr[14:3]; // @[el2_ifu_iccm_mem.scala 39:8]
wire [11:0] _T_73 = _T_23 ? addr_bank_inc[14:3] : io_iccm_rw_addr[14:3]; // @[el2_ifu_iccm_mem.scala 39:8] wire [11:0] _T_73 = _T_22 ? addr_bank_inc[14:3] : io_iccm_rw_addr[14:3]; // @[el2_ifu_iccm_mem.scala 39:8]
wire [11:0] _T_80 = _T_28 ? addr_bank_inc[14:3] : io_iccm_rw_addr[14:3]; // @[el2_ifu_iccm_mem.scala 39:8] wire [11:0] _T_80 = _T_27 ? addr_bank_inc[14:3] : io_iccm_rw_addr[14:3]; // @[el2_ifu_iccm_mem.scala 39:8]
reg [38:0] iccm_bank_dout_0; // @[el2_ifu_iccm_mem.scala 50:62] reg [38:0] iccm_bank_dout_0; // @[el2_ifu_iccm_mem.scala 50:62]
reg [38:0] iccm_bank_dout_1; // @[el2_ifu_iccm_mem.scala 50:62] reg [38:0] iccm_bank_dout_1; // @[el2_ifu_iccm_mem.scala 50:62]
reg [38:0] iccm_bank_dout_2; // @[el2_ifu_iccm_mem.scala 50:62] reg [38:0] iccm_bank_dout_2; // @[el2_ifu_iccm_mem.scala 50:62]
@ -170,19 +170,19 @@ module el2_ifu_iccm_mem(
wire _T_108 = _T_105 & _T_10; // @[el2_ifu_iccm_mem.scala 56:145] wire _T_108 = _T_105 & _T_10; // @[el2_ifu_iccm_mem.scala 56:145]
wire _T_109 = redundant_valid[1] & _T_108; // @[el2_ifu_iccm_mem.scala 56:71] wire _T_109 = redundant_valid[1] & _T_108; // @[el2_ifu_iccm_mem.scala 56:71]
wire _T_112 = addr_bank_inc[14:1] == redundant_address_1; // @[el2_ifu_iccm_mem.scala 57:37] wire _T_112 = addr_bank_inc[14:1] == redundant_address_1; // @[el2_ifu_iccm_mem.scala 57:37]
wire _T_115 = _T_112 & _T_13; // @[el2_ifu_iccm_mem.scala 57:77] wire _T_115 = _T_112 & _T_12; // @[el2_ifu_iccm_mem.scala 57:77]
wire _T_116 = _T_109 | _T_115; // @[el2_ifu_iccm_mem.scala 56:179] wire _T_116 = _T_109 | _T_115; // @[el2_ifu_iccm_mem.scala 56:179]
wire _T_123 = _T_105 & _T_15; // @[el2_ifu_iccm_mem.scala 56:145] wire _T_123 = _T_105 & _T_15; // @[el2_ifu_iccm_mem.scala 56:145]
wire _T_124 = redundant_valid[1] & _T_123; // @[el2_ifu_iccm_mem.scala 56:71] wire _T_124 = redundant_valid[1] & _T_123; // @[el2_ifu_iccm_mem.scala 56:71]
wire _T_130 = _T_112 & _T_18; // @[el2_ifu_iccm_mem.scala 57:77] wire _T_130 = _T_112 & _T_17; // @[el2_ifu_iccm_mem.scala 57:77]
wire _T_131 = _T_124 | _T_130; // @[el2_ifu_iccm_mem.scala 56:179] wire _T_131 = _T_124 | _T_130; // @[el2_ifu_iccm_mem.scala 56:179]
wire _T_138 = _T_105 & _T_20; // @[el2_ifu_iccm_mem.scala 56:145] wire _T_138 = _T_105 & _T_20; // @[el2_ifu_iccm_mem.scala 56:145]
wire _T_139 = redundant_valid[1] & _T_138; // @[el2_ifu_iccm_mem.scala 56:71] wire _T_139 = redundant_valid[1] & _T_138; // @[el2_ifu_iccm_mem.scala 56:71]
wire _T_145 = _T_112 & _T_23; // @[el2_ifu_iccm_mem.scala 57:77] wire _T_145 = _T_112 & _T_22; // @[el2_ifu_iccm_mem.scala 57:77]
wire _T_146 = _T_139 | _T_145; // @[el2_ifu_iccm_mem.scala 56:179] wire _T_146 = _T_139 | _T_145; // @[el2_ifu_iccm_mem.scala 56:179]
wire _T_153 = _T_105 & _T_25; // @[el2_ifu_iccm_mem.scala 56:145] wire _T_153 = _T_105 & _T_25; // @[el2_ifu_iccm_mem.scala 56:145]
wire _T_154 = redundant_valid[1] & _T_153; // @[el2_ifu_iccm_mem.scala 56:71] wire _T_154 = redundant_valid[1] & _T_153; // @[el2_ifu_iccm_mem.scala 56:71]
wire _T_160 = _T_112 & _T_28; // @[el2_ifu_iccm_mem.scala 57:77] wire _T_160 = _T_112 & _T_27; // @[el2_ifu_iccm_mem.scala 57:77]
wire _T_161 = _T_154 | _T_160; // @[el2_ifu_iccm_mem.scala 56:179] wire _T_161 = _T_154 | _T_160; // @[el2_ifu_iccm_mem.scala 56:179]
wire [3:0] sel_red1 = {_T_161,_T_146,_T_131,_T_116}; // @[Cat.scala 29:58] wire [3:0] sel_red1 = {_T_161,_T_146,_T_131,_T_116}; // @[Cat.scala 29:58]
reg [13:0] redundant_address_0; // @[Reg.scala 27:20] reg [13:0] redundant_address_0; // @[Reg.scala 27:20]
@ -190,19 +190,19 @@ module el2_ifu_iccm_mem(
wire _T_170 = _T_167 & _T_10; // @[el2_ifu_iccm_mem.scala 58:145] wire _T_170 = _T_167 & _T_10; // @[el2_ifu_iccm_mem.scala 58:145]
wire _T_171 = redundant_valid[0] & _T_170; // @[el2_ifu_iccm_mem.scala 58:71] wire _T_171 = redundant_valid[0] & _T_170; // @[el2_ifu_iccm_mem.scala 58:71]
wire _T_174 = addr_bank_inc[14:1] == redundant_address_0; // @[el2_ifu_iccm_mem.scala 59:37] wire _T_174 = addr_bank_inc[14:1] == redundant_address_0; // @[el2_ifu_iccm_mem.scala 59:37]
wire _T_177 = _T_174 & _T_13; // @[el2_ifu_iccm_mem.scala 59:77] wire _T_177 = _T_174 & _T_12; // @[el2_ifu_iccm_mem.scala 59:77]
wire _T_178 = _T_171 | _T_177; // @[el2_ifu_iccm_mem.scala 58:179] wire _T_178 = _T_171 | _T_177; // @[el2_ifu_iccm_mem.scala 58:179]
wire _T_185 = _T_167 & _T_15; // @[el2_ifu_iccm_mem.scala 58:145] wire _T_185 = _T_167 & _T_15; // @[el2_ifu_iccm_mem.scala 58:145]
wire _T_186 = redundant_valid[0] & _T_185; // @[el2_ifu_iccm_mem.scala 58:71] wire _T_186 = redundant_valid[0] & _T_185; // @[el2_ifu_iccm_mem.scala 58:71]
wire _T_192 = _T_174 & _T_18; // @[el2_ifu_iccm_mem.scala 59:77] wire _T_192 = _T_174 & _T_17; // @[el2_ifu_iccm_mem.scala 59:77]
wire _T_193 = _T_186 | _T_192; // @[el2_ifu_iccm_mem.scala 58:179] wire _T_193 = _T_186 | _T_192; // @[el2_ifu_iccm_mem.scala 58:179]
wire _T_200 = _T_167 & _T_20; // @[el2_ifu_iccm_mem.scala 58:145] wire _T_200 = _T_167 & _T_20; // @[el2_ifu_iccm_mem.scala 58:145]
wire _T_201 = redundant_valid[0] & _T_200; // @[el2_ifu_iccm_mem.scala 58:71] wire _T_201 = redundant_valid[0] & _T_200; // @[el2_ifu_iccm_mem.scala 58:71]
wire _T_207 = _T_174 & _T_23; // @[el2_ifu_iccm_mem.scala 59:77] wire _T_207 = _T_174 & _T_22; // @[el2_ifu_iccm_mem.scala 59:77]
wire _T_208 = _T_201 | _T_207; // @[el2_ifu_iccm_mem.scala 58:179] wire _T_208 = _T_201 | _T_207; // @[el2_ifu_iccm_mem.scala 58:179]
wire _T_215 = _T_167 & _T_25; // @[el2_ifu_iccm_mem.scala 58:145] wire _T_215 = _T_167 & _T_25; // @[el2_ifu_iccm_mem.scala 58:145]
wire _T_216 = redundant_valid[0] & _T_215; // @[el2_ifu_iccm_mem.scala 58:71] wire _T_216 = redundant_valid[0] & _T_215; // @[el2_ifu_iccm_mem.scala 58:71]
wire _T_222 = _T_174 & _T_28; // @[el2_ifu_iccm_mem.scala 59:77] wire _T_222 = _T_174 & _T_27; // @[el2_ifu_iccm_mem.scala 59:77]
wire _T_223 = _T_216 | _T_222; // @[el2_ifu_iccm_mem.scala 58:179] wire _T_223 = _T_216 | _T_222; // @[el2_ifu_iccm_mem.scala 58:179]
wire [3:0] sel_red0 = {_T_223,_T_208,_T_193,_T_178}; // @[Cat.scala 29:58] wire [3:0] sel_red0 = {_T_223,_T_208,_T_193,_T_178}; // @[Cat.scala 29:58]
reg [3:0] sel_red0_q; // @[el2_ifu_iccm_mem.scala 61:27] reg [3:0] sel_red0_q; // @[el2_ifu_iccm_mem.scala 61:27]

2
src/main/scala/ifu/el2_ifu_iccm_mem.scala
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@ -30,7 +30,7 @@ class el2_ifu_iccm_mem extends Module with el2_lib {
iccm_bank_wr_data_vec((2*i)+1) := io.iccm_wr_data(77,39) iccm_bank_wr_data_vec((2*i)+1) := io.iccm_wr_data(77,39)
} }
val wren_bank = (0 until ICCM_NUM_BANKS).map(i=> io.iccm_wren&(io.iccm_rw_addr(ICCM_BANK_HI-1,1)===i.U)|(addr_bank_inc(ICCM_BANK_HI-1,1)===i.U)) val wren_bank = (0 until ICCM_NUM_BANKS).map(i=> io.iccm_wren&((io.iccm_rw_addr(ICCM_BANK_HI-1,1)===i.U)|(addr_bank_inc(ICCM_BANK_HI-1,1)===i.U)))
val iccm_bank_wr_data = iccm_bank_wr_data_vec val iccm_bank_wr_data = iccm_bank_wr_data_vec
io.iccm_bank_wr_data := iccm_bank_wr_data io.iccm_bank_wr_data := iccm_bank_wr_data
val rden_bank = (0 until ICCM_NUM_BANKS).map(i=> io.iccm_rden&(io.iccm_rw_addr(ICCM_BANK_HI-1,1)===i.U)|(addr_bank_inc(ICCM_BANK_HI-1,1)===i.U)) val rden_bank = (0 until ICCM_NUM_BANKS).map(i=> io.iccm_rden&(io.iccm_rw_addr(ICCM_BANK_HI-1,1)===i.U)|(addr_bank_inc(ICCM_BANK_HI-1,1)===i.U))

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target/scala-2.12/classes/ifu/el2_ifu_iccm_mem.class
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