From 7cd988ef678e7c5c0f611703ff2155724b9401e1 Mon Sep 17 00:00:00 2001
From: waleed-lm <waleed.ehsan@lampromellon.com>
Date: Tue, 13 Oct 2020 15:36:42 +0500
Subject: [PATCH] Aligner Updated

---
 el2_ifu_aln_ctl.fir                           |   6 +++---
 el2_ifu_aln_ctl.v                             |  14 ++++++++------
 src/main/scala/ifu/el2_ifu_aln_ctl.scala      |  12 ++++++------
 .../classes/ifu/el2_ifu_aln_ctl.class         | Bin 192183 -> 192167 bytes
 4 files changed, 17 insertions(+), 15 deletions(-)

diff --git a/el2_ifu_aln_ctl.fir b/el2_ifu_aln_ctl.fir
index 890f1113..569ad067 100644
--- a/el2_ifu_aln_ctl.fir
+++ b/el2_ifu_aln_ctl.fir
@@ -2439,9 +2439,9 @@ circuit el2_ifu_aln_ctl :
     node _T_225 = bits(misc0eff, 53, 53) @[el2_ifu_aln_ctl.scala 217:21]
     f0icaf <= _T_225 @[el2_ifu_aln_ctl.scala 217:10]
     node f0ictype = bits(misc0eff, 52, 51) @[el2_ifu_aln_ctl.scala 218:26]
-    node f0prett = bits(misc0eff, 50, 20) @[el2_ifu_aln_ctl.scala 219:25]
-    node f0poffset = bits(misc0eff, 19, 8) @[el2_ifu_aln_ctl.scala 220:27]
-    node f0fghr = bits(misc0eff, 7, 0) @[el2_ifu_aln_ctl.scala 221:24]
+    node f0prett = bits(misc0eff, 50, 18) @[el2_ifu_aln_ctl.scala 219:25]
+    node f0poffset = bits(misc0eff, 17, 5) @[el2_ifu_aln_ctl.scala 220:27]
+    node f0fghr = bits(misc0eff, 4, 0) @[el2_ifu_aln_ctl.scala 221:24]
     node _T_226 = bits(io.ifu_bp_hist1_f, 1, 1) @[el2_ifu_aln_ctl.scala 223:37]
     node _T_227 = bits(io.ifu_bp_hist0_f, 1, 1) @[el2_ifu_aln_ctl.scala 223:58]
     node _T_228 = bits(io.ifu_bp_pc4_f, 1, 1) @[el2_ifu_aln_ctl.scala 223:77]
diff --git a/el2_ifu_aln_ctl.v b/el2_ifu_aln_ctl.v
index 092e3c94..e9d736b3 100644
--- a/el2_ifu_aln_ctl.v
+++ b/el2_ifu_aln_ctl.v
@@ -824,9 +824,9 @@ module el2_ifu_aln_ctl(
   wire  f0dbecc = misc0eff[54]; // @[el2_ifu_aln_ctl.scala 216:25]
   wire  f0icaf = misc0eff[53]; // @[el2_ifu_aln_ctl.scala 217:21]
   wire [1:0] f0ictype = misc0eff[52:51]; // @[el2_ifu_aln_ctl.scala 218:26]
-  wire [30:0] f0prett = misc0eff[50:20]; // @[el2_ifu_aln_ctl.scala 219:25]
-  wire [11:0] f0poffset = misc0eff[19:8]; // @[el2_ifu_aln_ctl.scala 220:27]
-  wire [7:0] f0fghr = misc0eff[7:0]; // @[el2_ifu_aln_ctl.scala 221:24]
+  wire [32:0] f0prett = misc0eff[50:18]; // @[el2_ifu_aln_ctl.scala 219:25]
+  wire [12:0] f0poffset = misc0eff[17:5]; // @[el2_ifu_aln_ctl.scala 220:27]
+  wire [4:0] f0fghr = misc0eff[4:0]; // @[el2_ifu_aln_ctl.scala 221:24]
   wire [23:0] _T_251 = {brdata1,brdata0}; // @[Cat.scala 29:58]
   wire [23:0] _T_254 = {brdata2,brdata1}; // @[Cat.scala 29:58]
   wire [23:0] _T_257 = {brdata0,brdata2}; // @[Cat.scala 29:58]
@@ -974,6 +974,8 @@ module el2_ifu_aln_ctl(
   wire  _T_752 = first4B & alignhist0[1]; // @[el2_ifu_aln_ctl.scala 387:42]
   wire  _T_753 = _T_750 | _T_752; // @[el2_ifu_aln_ctl.scala 387:31]
   wire  i0_ends_f1 = first4B & _T_516; // @[el2_ifu_aln_ctl.scala 389:28]
+  wire [12:0] _T_756 = i0_ends_f1 ? {{1'd0}, f1poffset} : f0poffset; // @[el2_ifu_aln_ctl.scala 390:27]
+  wire [32:0] _T_758 = i0_ends_f1 ? {{2'd0}, f1prett} : f0prett; // @[el2_ifu_aln_ctl.scala 392:25]
   wire  _T_769 = io_i0_brp_valid & i0_brp_pc4; // @[el2_ifu_aln_ctl.scala 398:42]
   wire  _T_770 = _T_769 & first2B; // @[el2_ifu_aln_ctl.scala 398:56]
   wire  _T_771 = ~i0_brp_pc4; // @[el2_ifu_aln_ctl.scala 398:89]
@@ -994,17 +996,17 @@ module el2_ifu_aln_ctl(
   assign io_ifu_fb_consume1 = _T_313 & _T_1; // @[el2_ifu_aln_ctl.scala 55:22 el2_ifu_aln_ctl.scala 258:22]
   assign io_ifu_fb_consume2 = _T_316 & _T_1; // @[el2_ifu_aln_ctl.scala 56:22 el2_ifu_aln_ctl.scala 259:22]
   assign io_ifu_i0_bp_index = _T_739 ? firstpc_hash : secondpc_hash; // @[el2_ifu_aln_ctl.scala 57:22 el2_ifu_aln_ctl.scala 400:22]
-  assign io_ifu_i0_bp_fghr = i0_ends_f1 ? f1fghr : f0fghr; // @[el2_ifu_aln_ctl.scala 58:21 el2_ifu_aln_ctl.scala 402:21]
+  assign io_ifu_i0_bp_fghr = i0_ends_f1 ? f1fghr : {{3'd0}, f0fghr}; // @[el2_ifu_aln_ctl.scala 58:21 el2_ifu_aln_ctl.scala 402:21]
   assign io_ifu_i0_bp_btag = _T_739 ? firstbrtag_hash : secondbrtag_hash; // @[el2_ifu_aln_ctl.scala 59:21 el2_ifu_aln_ctl.scala 404:21]
   assign io_ifu_pmu_instr_aligned = io_dec_i0_decode_d & _T_786; // @[el2_ifu_aln_ctl.scala 60:28 el2_ifu_aln_ctl.scala 410:28]
   assign io_ifu_i0_cinst = aligndata[15:0]; // @[el2_ifu_aln_ctl.scala 61:19 el2_ifu_aln_ctl.scala 346:19]
   assign io_i0_brp_valid = _T_723 | _T_727; // @[el2_ifu_aln_ctl.scala 378:19]
-  assign io_i0_brp_toffset = i0_ends_f1 ? f1poffset : f0poffset; // @[el2_ifu_aln_ctl.scala 390:21]
+  assign io_i0_brp_toffset = _T_756[11:0]; // @[el2_ifu_aln_ctl.scala 390:21]
   assign io_i0_brp_hist = {_T_748,_T_753}; // @[el2_ifu_aln_ctl.scala 386:18]
   assign io_i0_brp_br_error = _T_770 | _T_773; // @[el2_ifu_aln_ctl.scala 398:22]
   assign io_i0_brp_br_start_error = _T_658 & alignbrend[0]; // @[el2_ifu_aln_ctl.scala 394:29]
   assign io_i0_brp_bank = _T_739 ? f0pc[1] : secondpc[1]; // @[el2_ifu_aln_ctl.scala 396:29]
-  assign io_i0_brp_prett = i0_ends_f1 ? f1prett : f0prett; // @[el2_ifu_aln_ctl.scala 392:19]
+  assign io_i0_brp_prett = _T_758[30:0]; // @[el2_ifu_aln_ctl.scala 392:19]
   assign io_i0_brp_way = _T_739 ? alignway[0] : alignway[1]; // @[el2_ifu_aln_ctl.scala 384:17]
   assign io_i0_brp_ret = _T_730 | _T_732; // @[el2_ifu_aln_ctl.scala 380:17]
   assign decompressed_io_din = aligndata[15:0]; // @[el2_ifu_aln_ctl.scala 406:23]
diff --git a/src/main/scala/ifu/el2_ifu_aln_ctl.scala b/src/main/scala/ifu/el2_ifu_aln_ctl.scala
index 131b5bb0..cedf5903 100644
--- a/src/main/scala/ifu/el2_ifu_aln_ctl.scala
+++ b/src/main/scala/ifu/el2_ifu_aln_ctl.scala
@@ -213,12 +213,12 @@ class el2_ifu_aln_ctl extends Module with el2_lib {
   val f1poffset = misc1eff(BHT_GHR_SIZE+11, BHT_GHR_SIZE)
   val f1fghr = misc1eff(BHT_GHR_SIZE-1, 0)
 
-  val f0dbecc = misc0eff(misc0eff.getWidth-1)
-  f0icaf := misc0eff(misc0eff.getWidth-2)
-  val f0ictype = misc0eff(misc0eff.getWidth-3,misc0eff.getWidth-4)
-  val f0prett = misc0eff(misc0eff.getWidth-5,misc0eff.getWidth-35)
-  val f0poffset = misc0eff(BHT_GHR_SIZE+11, BHT_GHR_SIZE)
-  val f0fghr = misc0eff(BHT_GHR_SIZE-1, 0)
+  val f0dbecc = misc0eff(MHI)
+  f0icaf := misc0eff(MHI-1)
+  val f0ictype = misc0eff(MHI-2, MHI-3)
+  val f0prett = misc0eff(MHI-4,MHI-36)
+  val f0poffset = misc0eff(MHI-37, MHI-49)
+  val f0fghr = misc0eff(MHI-50, 0)
 
   brdata_in := Cat(io.ifu_bp_hist1_f(1),io.ifu_bp_hist0_f(1),io.ifu_bp_pc4_f(1),io.ifu_bp_way_f(1),io.ifu_bp_valid_f(1),
     io.ifu_bp_ret_f(1), io.ifu_bp_hist1_f(0),io.ifu_bp_hist0_f(0),io.ifu_bp_pc4_f(0),io.ifu_bp_way_f(0),
diff --git a/target/scala-2.12/classes/ifu/el2_ifu_aln_ctl.class b/target/scala-2.12/classes/ifu/el2_ifu_aln_ctl.class
index eb86f9fa390edd1e614ce96938b398c2b06ecbba..85ee99879d17620445e8a40561060a1cb01c0d5d 100644
GIT binary patch
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