From 7d4de00f76aa617768ec61afb77355ee22c1ef11 Mon Sep 17 00:00:00 2001 From: waleed-lm Date: Wed, 16 Dec 2020 12:40:41 +0500 Subject: [PATCH] LSU Paramtere problem --- .idea/modules/chisel-module-template.iml | 2 +- ahb_to_axi4.anno.json | 34 - ahb_to_axi4.fir | 615 - ahb_to_axi4.v | 584 - axi4_to_ahb.anno.json | 113 - axi4_to_ahb.fir | 1406 - axi4_to_ahb.v | 1139 - dbg.anno.json | 89 + dbg.fir | 1280 + dbg.v | 1180 + firrtl_black_box_resource_files.f | 4 +- lsu.anno.json | 506 + lsu.fir | 15817 ++++++++++ lsu.v | 11868 ++++++++ lsu_bus_buffer.anno.json | 179 + lsu_bus_buffer.fir | 6508 +++++ lsu_bus_buffer.v | 4586 +++ .../$8f8b1ccfdfa3315fc811.class | Bin 650 -> 0 bytes ...11$.class => $c0f8b8257add6b2061c5$.class} | Bin 2559 -> 2566 bytes ...c811.cache => $c0f8b8257add6b2061c5.cache} | 0 .../$c0f8b8257add6b2061c5.class | Bin 0 -> 657 bytes .../$056ceca0fd98dd2e0179$.class | Bin 0 -> 4518 bytes ...5c2a.cache => $056ceca0fd98dd2e0179.cache} | 0 .../$056ceca0fd98dd2e0179.class | Bin 0 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+- src/main/scala/ifu/ifu.scala | 4 + src/main/scala/include/bundle.scala | 8 +- src/main/scala/lib/param.scala | 6 +- src/main/scala/lsu/lsu.scala | 3 + src/main/scala/lsu/lsu_bus_buffer.scala | 7 +- src/main/scala/lsu/lsu_bus_intf.scala | 1 - src/main/scala/pic_ctrl.scala | 4 + src/main/scala/quasar.scala | 13 +- .../chisel-module-template_2.12-3.3.0.jar | Bin 1738509 -> 1765467 bytes target/scala-2.12/classes/QUASAR$.class | Bin 3815 -> 3815 bytes .../classes/QUASAR$delayedInit$body.class | Bin 697 -> 697 bytes target/scala-2.12/classes/dbg/dbg.class | Bin 275716 -> 275410 bytes target/scala-2.12/classes/dbg/dbg_main$.class | Bin 0 -> 3845 bytes .../dbg/dbg_main$delayedInit$body.class | Bin 0 -> 730 bytes target/scala-2.12/classes/dbg/dbg_main.class | Bin 0 -> 773 bytes target/scala-2.12/classes/dec/CSR_IO.class | Bin 84352 -> 84352 bytes target/scala-2.12/classes/dec/CSRs.class | Bin 23325 -> 23325 bytes target/scala-2.12/classes/dec/csr_tlu.class | Bin 216564 -> 216564 bytes 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target/scala-2.12/classes/lsu/bus_buffer.class create mode 100644 target/scala-2.12/classes/lsu/lsu_top$.class create mode 100644 target/scala-2.12/classes/lsu/lsu_top$delayedInit$body.class create mode 100644 target/scala-2.12/classes/lsu/lsu_top.class create mode 100644 target/scala-2.12/classes/pic_gen$.class create mode 100644 target/scala-2.12/classes/pic_gen$delayedInit$body.class create mode 100644 target/scala-2.12/classes/pic_gen.class diff --git a/.idea/modules/chisel-module-template.iml b/.idea/modules/chisel-module-template.iml index 2a9bea34..2bbc0953 100644 --- a/.idea/modules/chisel-module-template.iml +++ b/.idea/modules/chisel-module-template.iml @@ -1,5 +1,5 @@ - + diff --git a/ahb_to_axi4.anno.json b/ahb_to_axi4.anno.json deleted file mode 100644 index e256d28b..00000000 --- a/ahb_to_axi4.anno.json +++ /dev/null @@ -1,34 +0,0 @@ -[ - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~ahb_to_axi4|ahb_to_axi4>io_ahb_sig_in_hready", - "sources":[ - "~ahb_to_axi4|ahb_to_axi4>io_ahb_sig_in_hresp", - "~ahb_to_axi4|ahb_to_axi4>io_axi_aw_valid", - "~ahb_to_axi4|ahb_to_axi4>io_axi_aw_ready", - "~ahb_to_axi4|ahb_to_axi4>io_axi_ar_valid", - "~ahb_to_axi4|ahb_to_axi4>io_axi_ar_ready" - ] - }, - { - "class":"firrtl.EmitCircuitAnnotation", - "emitter":"firrtl.VerilogEmitter" - }, - { - "class":"firrtl.transforms.BlackBoxResourceAnno", - "target":"ahb_to_axi4.gated_latch", - "resourceId":"/vsrc/gated_latch.v" - }, - { - "class":"firrtl.options.TargetDirAnnotation", - "directory":"." - }, - { - "class":"firrtl.options.OutputAnnotationFileAnnotation", - "file":"ahb_to_axi4" - }, - { - "class":"firrtl.transforms.BlackBoxTargetDirAnno", - "targetDir":"." - } -] \ No newline at end of file diff --git a/ahb_to_axi4.fir b/ahb_to_axi4.fir deleted file mode 100644 index 1ae07a04..00000000 --- a/ahb_to_axi4.fir +++ /dev/null @@ -1,615 +0,0 @@ -;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 -circuit ahb_to_axi4 : - extmodule gated_latch : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_1 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_1 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_1 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_2 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_2 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_2 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_3 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_3 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_3 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_4 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_4 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_4 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_5 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_5 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_5 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - module ahb_to_axi4 : - input clock : Clock - input reset : AsyncReset - output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ahb : {flip sig : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, flip hsel : UInt<1>, flip hreadyin : UInt<1>}} - - wire _T : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[ahb_to_axi4.scala 20:25] - _T.r.bits.last <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.r.bits.resp <= UInt<2>("h00") @[ahb_to_axi4.scala 20:25] - _T.r.bits.data <= UInt<64>("h00") @[ahb_to_axi4.scala 20:25] - _T.r.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.r.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.r.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.ar.bits.qos <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25] - _T.ar.bits.prot <= UInt<3>("h00") @[ahb_to_axi4.scala 20:25] - _T.ar.bits.cache <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25] - _T.ar.bits.lock <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.ar.bits.burst <= UInt<2>("h00") @[ahb_to_axi4.scala 20:25] - _T.ar.bits.size <= UInt<3>("h00") @[ahb_to_axi4.scala 20:25] - _T.ar.bits.len <= UInt<8>("h00") @[ahb_to_axi4.scala 20:25] - _T.ar.bits.region <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25] - _T.ar.bits.addr <= UInt<32>("h00") @[ahb_to_axi4.scala 20:25] - _T.ar.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.ar.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.ar.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.b.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.b.bits.resp <= UInt<2>("h00") @[ahb_to_axi4.scala 20:25] - _T.b.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.b.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.w.bits.last <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.w.bits.strb <= UInt<8>("h00") @[ahb_to_axi4.scala 20:25] - _T.w.bits.data <= UInt<64>("h00") @[ahb_to_axi4.scala 20:25] - _T.w.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.w.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.aw.bits.qos <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25] - _T.aw.bits.prot <= UInt<3>("h00") @[ahb_to_axi4.scala 20:25] - _T.aw.bits.cache <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25] - _T.aw.bits.lock <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.aw.bits.burst <= UInt<2>("h00") @[ahb_to_axi4.scala 20:25] - _T.aw.bits.size <= UInt<3>("h00") @[ahb_to_axi4.scala 20:25] - _T.aw.bits.len <= UInt<8>("h00") @[ahb_to_axi4.scala 20:25] - _T.aw.bits.region <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25] - _T.aw.bits.addr <= UInt<32>("h00") @[ahb_to_axi4.scala 20:25] - _T.aw.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.aw.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.aw.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.r.bits.last <= io.axi.r.bits.last @[ahb_to_axi4.scala 20:10] - _T.r.bits.resp <= io.axi.r.bits.resp @[ahb_to_axi4.scala 20:10] - _T.r.bits.data <= io.axi.r.bits.data @[ahb_to_axi4.scala 20:10] - _T.r.bits.id <= io.axi.r.bits.id @[ahb_to_axi4.scala 20:10] - _T.r.valid <= io.axi.r.valid @[ahb_to_axi4.scala 20:10] - io.axi.r.ready <= _T.r.ready @[ahb_to_axi4.scala 20:10] - io.axi.ar.bits.qos <= _T.ar.bits.qos @[ahb_to_axi4.scala 20:10] - io.axi.ar.bits.prot <= _T.ar.bits.prot @[ahb_to_axi4.scala 20:10] - io.axi.ar.bits.cache <= _T.ar.bits.cache @[ahb_to_axi4.scala 20:10] - io.axi.ar.bits.lock <= _T.ar.bits.lock @[ahb_to_axi4.scala 20:10] - io.axi.ar.bits.burst <= _T.ar.bits.burst @[ahb_to_axi4.scala 20:10] - io.axi.ar.bits.size <= _T.ar.bits.size @[ahb_to_axi4.scala 20:10] - io.axi.ar.bits.len <= _T.ar.bits.len @[ahb_to_axi4.scala 20:10] - io.axi.ar.bits.region <= _T.ar.bits.region @[ahb_to_axi4.scala 20:10] - io.axi.ar.bits.addr <= _T.ar.bits.addr @[ahb_to_axi4.scala 20:10] - io.axi.ar.bits.id <= _T.ar.bits.id @[ahb_to_axi4.scala 20:10] - io.axi.ar.valid <= _T.ar.valid @[ahb_to_axi4.scala 20:10] - _T.ar.ready <= io.axi.ar.ready @[ahb_to_axi4.scala 20:10] - _T.b.bits.id <= io.axi.b.bits.id @[ahb_to_axi4.scala 20:10] - _T.b.bits.resp <= io.axi.b.bits.resp @[ahb_to_axi4.scala 20:10] - _T.b.valid <= io.axi.b.valid @[ahb_to_axi4.scala 20:10] - io.axi.b.ready <= _T.b.ready @[ahb_to_axi4.scala 20:10] - io.axi.w.bits.last <= _T.w.bits.last @[ahb_to_axi4.scala 20:10] - io.axi.w.bits.strb <= _T.w.bits.strb @[ahb_to_axi4.scala 20:10] - io.axi.w.bits.data <= _T.w.bits.data @[ahb_to_axi4.scala 20:10] - io.axi.w.valid <= _T.w.valid @[ahb_to_axi4.scala 20:10] - _T.w.ready <= io.axi.w.ready @[ahb_to_axi4.scala 20:10] - io.axi.aw.bits.qos <= _T.aw.bits.qos @[ahb_to_axi4.scala 20:10] - io.axi.aw.bits.prot <= _T.aw.bits.prot @[ahb_to_axi4.scala 20:10] - io.axi.aw.bits.cache <= _T.aw.bits.cache @[ahb_to_axi4.scala 20:10] - io.axi.aw.bits.lock <= _T.aw.bits.lock @[ahb_to_axi4.scala 20:10] - io.axi.aw.bits.burst <= _T.aw.bits.burst @[ahb_to_axi4.scala 20:10] - io.axi.aw.bits.size <= _T.aw.bits.size @[ahb_to_axi4.scala 20:10] - io.axi.aw.bits.len <= _T.aw.bits.len @[ahb_to_axi4.scala 20:10] - io.axi.aw.bits.region <= _T.aw.bits.region @[ahb_to_axi4.scala 20:10] - io.axi.aw.bits.addr <= _T.aw.bits.addr @[ahb_to_axi4.scala 20:10] - io.axi.aw.bits.id <= _T.aw.bits.id @[ahb_to_axi4.scala 20:10] - io.axi.aw.valid <= _T.aw.valid @[ahb_to_axi4.scala 20:10] - _T.aw.ready <= io.axi.aw.ready @[ahb_to_axi4.scala 20:10] - wire master_wstrb : UInt<8> - master_wstrb <= UInt<8>("h00") - wire buf_state_en : UInt<1> - buf_state_en <= UInt<1>("h00") - wire buf_read_error_in : UInt<1> - buf_read_error_in <= UInt<1>("h00") - wire buf_read_error : UInt<1> - buf_read_error <= UInt<1>("h00") - wire buf_rdata : UInt<64> - buf_rdata <= UInt<64>("h00") - wire ahb_hready : UInt<1> - ahb_hready <= UInt<1>("h00") - wire ahb_hready_q : UInt<1> - ahb_hready_q <= UInt<1>("h00") - wire ahb_htrans_in : UInt<2> - ahb_htrans_in <= UInt<2>("h00") - wire ahb_htrans_q : UInt<2> - ahb_htrans_q <= UInt<2>("h00") - wire ahb_hsize_q : UInt<3> - ahb_hsize_q <= UInt<3>("h00") - wire ahb_hwrite_q : UInt<1> - ahb_hwrite_q <= UInt<1>("h00") - wire ahb_haddr_q : UInt<32> - ahb_haddr_q <= UInt<32>("h00") - wire ahb_hwdata_q : UInt<64> - ahb_hwdata_q <= UInt<64>("h00") - wire ahb_hresp_q : UInt<1> - ahb_hresp_q <= UInt<1>("h00") - wire buf_rdata_en : UInt<1> - buf_rdata_en <= UInt<1>("h00") - wire ahb_bus_addr_clk_en : UInt<1> - ahb_bus_addr_clk_en <= UInt<1>("h00") - wire buf_rdata_clk_en : UInt<1> - buf_rdata_clk_en <= UInt<1>("h00") - wire ahb_clk : Clock @[ahb_to_axi4.scala 44:33] - wire ahb_addr_clk : Clock @[ahb_to_axi4.scala 45:33] - wire buf_rdata_clk : Clock @[ahb_to_axi4.scala 46:33] - wire cmdbuf_wr_en : UInt<1> - cmdbuf_wr_en <= UInt<1>("h00") - wire cmdbuf_rst : UInt<1> - cmdbuf_rst <= UInt<1>("h00") - wire cmdbuf_full : UInt<1> - cmdbuf_full <= UInt<1>("h00") - wire cmdbuf_vld : UInt<1> - cmdbuf_vld <= UInt<1>("h00") - wire cmdbuf_write : UInt<1> - cmdbuf_write <= UInt<1>("h00") - wire cmdbuf_size : UInt<2> - cmdbuf_size <= UInt<2>("h00") - wire cmdbuf_wstrb : UInt<8> - cmdbuf_wstrb <= UInt<8>("h00") - wire cmdbuf_addr : UInt<32> - cmdbuf_addr <= UInt<32>("h00") - wire cmdbuf_wdata : UInt<64> - cmdbuf_wdata <= UInt<64>("h00") - wire bus_clk : Clock @[ahb_to_axi4.scala 58:33] - node _T_1 = bits(ahb_haddr_q, 31, 28) @[lib.scala 84:25] - node ahb_addr_in_dccm_region_nc = eq(_T_1, UInt<4>("h0f")) @[lib.scala 84:47] - node _T_2 = bits(ahb_haddr_q, 31, 16) @[lib.scala 87:14] - node ahb_addr_in_dccm = eq(_T_2, UInt<16>("h0f004")) @[lib.scala 87:29] - node _T_3 = bits(ahb_haddr_q, 31, 28) @[lib.scala 84:25] - node ahb_addr_in_iccm_region_nc = eq(_T_3, UInt<4>("h0e")) @[lib.scala 84:47] - node _T_4 = bits(ahb_haddr_q, 31, 16) @[lib.scala 87:14] - node ahb_addr_in_iccm = eq(_T_4, UInt<16>("h0ee00")) @[lib.scala 87:29] - node _T_5 = bits(ahb_haddr_q, 31, 28) @[lib.scala 84:25] - node ahb_addr_in_pic_region_nc = eq(_T_5, UInt<4>("h0f")) @[lib.scala 84:47] - node _T_6 = bits(ahb_haddr_q, 31, 15) @[lib.scala 87:14] - node ahb_addr_in_pic = eq(_T_6, UInt<17>("h01e018")) @[lib.scala 87:29] - wire buf_state : UInt<2> - buf_state <= UInt<2>("h00") - wire buf_nxtstate : UInt<2> - buf_nxtstate <= UInt<2>("h00") - buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 68:31] - buf_state_en <= UInt<1>("h00") @[ahb_to_axi4.scala 69:31] - buf_rdata_en <= UInt<1>("h00") @[ahb_to_axi4.scala 70:31] - buf_read_error_in <= UInt<1>("h00") @[ahb_to_axi4.scala 71:31] - cmdbuf_wr_en <= UInt<1>("h00") @[ahb_to_axi4.scala 72:31] - node _T_7 = eq(UInt<2>("h00"), buf_state) @[Conditional.scala 37:30] - when _T_7 : @[Conditional.scala 40:58] - node _T_8 = mux(io.ahb.sig.out.hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 76:26] - buf_nxtstate <= _T_8 @[ahb_to_axi4.scala 76:20] - node _T_9 = bits(io.ahb.sig.out.htrans, 1, 1) @[ahb_to_axi4.scala 77:57] - node _T_10 = and(ahb_hready, _T_9) @[ahb_to_axi4.scala 77:34] - node _T_11 = and(_T_10, io.ahb.hsel) @[ahb_to_axi4.scala 77:61] - buf_state_en <= _T_11 @[ahb_to_axi4.scala 77:20] - skip @[Conditional.scala 40:58] - else : @[Conditional.scala 39:67] - node _T_12 = eq(UInt<2>("h01"), buf_state) @[Conditional.scala 37:30] - when _T_12 : @[Conditional.scala 39:67] - node _T_13 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 80:72] - node _T_14 = eq(_T_13, UInt<1>("h00")) @[ahb_to_axi4.scala 80:79] - node _T_15 = or(io.ahb.sig.in.hresp, _T_14) @[ahb_to_axi4.scala 80:48] - node _T_16 = eq(io.ahb.hsel, UInt<1>("h00")) @[ahb_to_axi4.scala 80:93] - node _T_17 = or(_T_15, _T_16) @[ahb_to_axi4.scala 80:91] - node _T_18 = bits(_T_17, 0, 0) @[ahb_to_axi4.scala 80:107] - node _T_19 = mux(io.ahb.sig.out.hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 80:124] - node _T_20 = mux(_T_18, UInt<2>("h00"), _T_19) @[ahb_to_axi4.scala 80:26] - buf_nxtstate <= _T_20 @[ahb_to_axi4.scala 80:20] - node _T_21 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 81:24] - node _T_22 = or(_T_21, io.ahb.sig.in.hresp) @[ahb_to_axi4.scala 81:37] - buf_state_en <= _T_22 @[ahb_to_axi4.scala 81:20] - node _T_23 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 82:23] - node _T_24 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 82:85] - node _T_25 = eq(_T_24, UInt<2>("h01")) @[ahb_to_axi4.scala 82:92] - node _T_26 = and(_T_25, io.ahb.hsel) @[ahb_to_axi4.scala 82:110] - node _T_27 = or(io.ahb.sig.in.hresp, _T_26) @[ahb_to_axi4.scala 82:60] - node _T_28 = eq(_T_27, UInt<1>("h00")) @[ahb_to_axi4.scala 82:38] - node _T_29 = and(_T_23, _T_28) @[ahb_to_axi4.scala 82:36] - cmdbuf_wr_en <= _T_29 @[ahb_to_axi4.scala 82:20] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_30 = eq(UInt<2>("h02"), buf_state) @[Conditional.scala 37:30] - when _T_30 : @[Conditional.scala 39:67] - node _T_31 = mux(io.ahb.sig.in.hresp, UInt<2>("h00"), UInt<2>("h03")) @[ahb_to_axi4.scala 85:26] - buf_nxtstate <= _T_31 @[ahb_to_axi4.scala 85:20] - node _T_32 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 86:24] - node _T_33 = or(_T_32, io.ahb.sig.in.hresp) @[ahb_to_axi4.scala 86:37] - buf_state_en <= _T_33 @[ahb_to_axi4.scala 86:20] - node _T_34 = eq(io.ahb.sig.in.hresp, UInt<1>("h00")) @[ahb_to_axi4.scala 87:23] - node _T_35 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 87:46] - node _T_36 = and(_T_34, _T_35) @[ahb_to_axi4.scala 87:44] - cmdbuf_wr_en <= _T_36 @[ahb_to_axi4.scala 87:20] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_37 = eq(UInt<2>("h03"), buf_state) @[Conditional.scala 37:30] - when _T_37 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 90:20] - node _T_38 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 91:40] - node _T_39 = and(io.axi.r.valid, _T_38) @[ahb_to_axi4.scala 91:38] - buf_state_en <= _T_39 @[ahb_to_axi4.scala 91:20] - buf_rdata_en <= buf_state_en @[ahb_to_axi4.scala 92:20] - node _T_40 = bits(io.axi.r.bits.resp, 1, 0) @[ahb_to_axi4.scala 93:61] - node _T_41 = orr(_T_40) @[ahb_to_axi4.scala 93:68] - node _T_42 = and(buf_state_en, _T_41) @[ahb_to_axi4.scala 93:41] - buf_read_error_in <= _T_42 @[ahb_to_axi4.scala 93:25] - skip @[Conditional.scala 39:67] - node _T_43 = bits(buf_state_en, 0, 0) @[ahb_to_axi4.scala 96:99] - reg _T_44 : UInt, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_43 : @[Reg.scala 28:19] - _T_44 <= buf_nxtstate @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_state <= _T_44 @[ahb_to_axi4.scala 96:31] - node _T_45 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 98:54] - node _T_46 = eq(_T_45, UInt<1>("h00")) @[ahb_to_axi4.scala 98:60] - node _T_47 = bits(_T_46, 0, 0) @[Bitwise.scala 72:15] - node _T_48 = mux(_T_47, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_49 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 98:92] - node _T_50 = dshl(UInt<1>("h01"), _T_49) @[ahb_to_axi4.scala 98:78] - node _T_51 = and(_T_48, _T_50) @[ahb_to_axi4.scala 98:70] - node _T_52 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 99:24] - node _T_53 = eq(_T_52, UInt<1>("h01")) @[ahb_to_axi4.scala 99:30] - node _T_54 = bits(_T_53, 0, 0) @[Bitwise.scala 72:15] - node _T_55 = mux(_T_54, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_56 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 99:62] - node _T_57 = dshl(UInt<2>("h03"), _T_56) @[ahb_to_axi4.scala 99:48] - node _T_58 = and(_T_55, _T_57) @[ahb_to_axi4.scala 99:40] - node _T_59 = or(_T_51, _T_58) @[ahb_to_axi4.scala 98:109] - node _T_60 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 100:24] - node _T_61 = eq(_T_60, UInt<2>("h02")) @[ahb_to_axi4.scala 100:30] - node _T_62 = bits(_T_61, 0, 0) @[Bitwise.scala 72:15] - node _T_63 = mux(_T_62, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_64 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 100:62] - node _T_65 = dshl(UInt<4>("h0f"), _T_64) @[ahb_to_axi4.scala 100:48] - node _T_66 = and(_T_63, _T_65) @[ahb_to_axi4.scala 100:40] - node _T_67 = or(_T_59, _T_66) @[ahb_to_axi4.scala 99:79] - node _T_68 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 101:24] - node _T_69 = eq(_T_68, UInt<2>("h03")) @[ahb_to_axi4.scala 101:30] - node _T_70 = bits(_T_69, 0, 0) @[Bitwise.scala 72:15] - node _T_71 = mux(_T_70, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_72 = and(_T_71, UInt<8>("h0ff")) @[ahb_to_axi4.scala 101:40] - node _T_73 = or(_T_67, _T_72) @[ahb_to_axi4.scala 100:79] - master_wstrb <= _T_73 @[ahb_to_axi4.scala 98:31] - node _T_74 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 104:80] - node _T_75 = and(ahb_hresp_q, _T_74) @[ahb_to_axi4.scala 104:78] - node _T_76 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 104:98] - node _T_77 = eq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 104:124] - node _T_78 = or(_T_76, _T_77) @[ahb_to_axi4.scala 104:111] - node _T_79 = eq(buf_state, UInt<2>("h02")) @[ahb_to_axi4.scala 104:149] - node _T_80 = eq(buf_state, UInt<2>("h03")) @[ahb_to_axi4.scala 104:168] - node _T_81 = or(_T_79, _T_80) @[ahb_to_axi4.scala 104:156] - node _T_82 = eq(_T_81, UInt<1>("h00")) @[ahb_to_axi4.scala 104:137] - node _T_83 = and(_T_78, _T_82) @[ahb_to_axi4.scala 104:135] - node _T_84 = eq(buf_read_error, UInt<1>("h00")) @[ahb_to_axi4.scala 104:181] - node _T_85 = and(_T_83, _T_84) @[ahb_to_axi4.scala 104:179] - node _T_86 = mux(io.ahb.sig.in.hresp, _T_75, _T_85) @[ahb_to_axi4.scala 104:44] - io.ahb.sig.in.hready <= _T_86 @[ahb_to_axi4.scala 104:38] - node _T_87 = and(io.ahb.sig.in.hready, io.ahb.hreadyin) @[ahb_to_axi4.scala 105:55] - ahb_hready <= _T_87 @[ahb_to_axi4.scala 105:31] - node _T_88 = bits(io.ahb.hsel, 0, 0) @[Bitwise.scala 72:15] - node _T_89 = mux(_T_88, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_90 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 106:77] - node _T_91 = and(_T_89, _T_90) @[ahb_to_axi4.scala 106:54] - ahb_htrans_in <= _T_91 @[ahb_to_axi4.scala 106:31] - node _T_92 = bits(buf_rdata, 63, 0) @[ahb_to_axi4.scala 107:50] - io.ahb.sig.in.hrdata <= _T_92 @[ahb_to_axi4.scala 107:38] - node _T_93 = bits(ahb_htrans_q, 1, 0) @[ahb_to_axi4.scala 108:55] - node _T_94 = neq(_T_93, UInt<1>("h00")) @[ahb_to_axi4.scala 108:61] - node _T_95 = neq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 108:83] - node _T_96 = and(_T_94, _T_95) @[ahb_to_axi4.scala 108:70] - node _T_97 = or(ahb_addr_in_dccm, ahb_addr_in_iccm) @[ahb_to_axi4.scala 109:26] - node _T_98 = eq(_T_97, UInt<1>("h00")) @[ahb_to_axi4.scala 109:7] - node _T_99 = and(ahb_addr_in_dccm, ahb_hwrite_q) @[ahb_to_axi4.scala 110:46] - node _T_100 = or(ahb_addr_in_iccm, _T_99) @[ahb_to_axi4.scala 110:26] - node _T_101 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 110:80] - node _T_102 = eq(_T_101, UInt<2>("h02")) @[ahb_to_axi4.scala 110:86] - node _T_103 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 110:109] - node _T_104 = eq(_T_103, UInt<2>("h03")) @[ahb_to_axi4.scala 110:115] - node _T_105 = or(_T_102, _T_104) @[ahb_to_axi4.scala 110:95] - node _T_106 = eq(_T_105, UInt<1>("h00")) @[ahb_to_axi4.scala 110:66] - node _T_107 = and(_T_100, _T_106) @[ahb_to_axi4.scala 110:64] - node _T_108 = or(_T_98, _T_107) @[ahb_to_axi4.scala 109:47] - node _T_109 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 111:20] - node _T_110 = eq(_T_109, UInt<1>("h01")) @[ahb_to_axi4.scala 111:26] - node _T_111 = bits(ahb_haddr_q, 0, 0) @[ahb_to_axi4.scala 111:48] - node _T_112 = and(_T_110, _T_111) @[ahb_to_axi4.scala 111:35] - node _T_113 = or(_T_108, _T_112) @[ahb_to_axi4.scala 110:126] - node _T_114 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 112:20] - node _T_115 = eq(_T_114, UInt<2>("h02")) @[ahb_to_axi4.scala 112:26] - node _T_116 = bits(ahb_haddr_q, 1, 0) @[ahb_to_axi4.scala 112:49] - node _T_117 = orr(_T_116) @[ahb_to_axi4.scala 112:56] - node _T_118 = and(_T_115, _T_117) @[ahb_to_axi4.scala 112:35] - node _T_119 = or(_T_113, _T_118) @[ahb_to_axi4.scala 111:55] - node _T_120 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 113:20] - node _T_121 = eq(_T_120, UInt<2>("h03")) @[ahb_to_axi4.scala 113:26] - node _T_122 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 113:49] - node _T_123 = orr(_T_122) @[ahb_to_axi4.scala 113:56] - node _T_124 = and(_T_121, _T_123) @[ahb_to_axi4.scala 113:35] - node _T_125 = or(_T_119, _T_124) @[ahb_to_axi4.scala 112:61] - node _T_126 = and(_T_96, _T_125) @[ahb_to_axi4.scala 108:94] - node _T_127 = or(_T_126, buf_read_error) @[ahb_to_axi4.scala 113:63] - node _T_128 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 115:20] - node _T_129 = and(ahb_hresp_q, _T_128) @[ahb_to_axi4.scala 115:18] - node _T_130 = or(_T_127, _T_129) @[ahb_to_axi4.scala 114:20] - io.ahb.sig.in.hresp <= _T_130 @[ahb_to_axi4.scala 108:38] - reg _T_131 : UInt, buf_rdata_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 118:66] - _T_131 <= io.axi.r.bits.data @[ahb_to_axi4.scala 118:66] - buf_rdata <= _T_131 @[ahb_to_axi4.scala 118:31] - reg _T_132 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 119:60] - _T_132 <= buf_read_error_in @[ahb_to_axi4.scala 119:60] - buf_read_error <= _T_132 @[ahb_to_axi4.scala 119:31] - reg _T_133 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 122:60] - _T_133 <= io.ahb.sig.in.hresp @[ahb_to_axi4.scala 122:60] - ahb_hresp_q <= _T_133 @[ahb_to_axi4.scala 122:31] - reg _T_134 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 123:60] - _T_134 <= ahb_hready @[ahb_to_axi4.scala 123:60] - ahb_hready_q <= _T_134 @[ahb_to_axi4.scala 123:31] - reg _T_135 : UInt, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 124:60] - _T_135 <= ahb_htrans_in @[ahb_to_axi4.scala 124:60] - ahb_htrans_q <= _T_135 @[ahb_to_axi4.scala 124:31] - reg _T_136 : UInt, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 125:65] - _T_136 <= io.ahb.sig.out.hsize @[ahb_to_axi4.scala 125:65] - ahb_hsize_q <= _T_136 @[ahb_to_axi4.scala 125:31] - reg _T_137 : UInt<1>, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 126:65] - _T_137 <= io.ahb.sig.out.hwrite @[ahb_to_axi4.scala 126:65] - ahb_hwrite_q <= _T_137 @[ahb_to_axi4.scala 126:31] - reg _T_138 : UInt, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 127:65] - _T_138 <= io.ahb.sig.out.haddr @[ahb_to_axi4.scala 127:65] - ahb_haddr_q <= _T_138 @[ahb_to_axi4.scala 127:31] - node _T_139 = bits(io.ahb.sig.out.htrans, 1, 1) @[ahb_to_axi4.scala 130:85] - node _T_140 = and(ahb_hready, _T_139) @[ahb_to_axi4.scala 130:62] - node _T_141 = and(io.bus_clk_en, _T_140) @[ahb_to_axi4.scala 130:48] - ahb_bus_addr_clk_en <= _T_141 @[ahb_to_axi4.scala 130:31] - node _T_142 = and(io.bus_clk_en, buf_rdata_en) @[ahb_to_axi4.scala 131:48] - buf_rdata_clk_en <= _T_142 @[ahb_to_axi4.scala 131:31] - inst rvclkhdr of rvclkhdr @[lib.scala 343:22] - rvclkhdr.clock <= clock - rvclkhdr.reset <= reset - rvclkhdr.io.clk <= clock @[lib.scala 344:17] - rvclkhdr.io.en <= io.bus_clk_en @[lib.scala 345:16] - rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahb_clk <= rvclkhdr.io.l1clk @[ahb_to_axi4.scala 133:31] - inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 343:22] - rvclkhdr_1.clock <= clock - rvclkhdr_1.reset <= reset - rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_1.io.en <= ahb_bus_addr_clk_en @[lib.scala 345:16] - rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahb_addr_clk <= rvclkhdr_1.io.l1clk @[ahb_to_axi4.scala 134:31] - inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 343:22] - rvclkhdr_2.clock <= clock - rvclkhdr_2.reset <= reset - rvclkhdr_2.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_2.io.en <= buf_rdata_clk_en @[lib.scala 345:16] - rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - buf_rdata_clk <= rvclkhdr_2.io.l1clk @[ahb_to_axi4.scala 135:31] - node _T_143 = and(io.axi.aw.valid, io.axi.aw.ready) @[ahb_to_axi4.scala 137:53] - node _T_144 = and(io.axi.ar.valid, io.axi.ar.ready) @[ahb_to_axi4.scala 137:91] - node _T_145 = or(_T_143, _T_144) @[ahb_to_axi4.scala 137:72] - node _T_146 = eq(cmdbuf_wr_en, UInt<1>("h00")) @[ahb_to_axi4.scala 137:113] - node _T_147 = and(_T_145, _T_146) @[ahb_to_axi4.scala 137:111] - node _T_148 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 137:153] - node _T_149 = and(io.ahb.sig.in.hresp, _T_148) @[ahb_to_axi4.scala 137:151] - node _T_150 = or(_T_147, _T_149) @[ahb_to_axi4.scala 137:128] - cmdbuf_rst <= _T_150 @[ahb_to_axi4.scala 137:31] - node _T_151 = and(io.axi.aw.valid, io.axi.aw.ready) @[ahb_to_axi4.scala 138:67] - node _T_152 = and(io.axi.ar.valid, io.axi.ar.ready) @[ahb_to_axi4.scala 138:105] - node _T_153 = or(_T_151, _T_152) @[ahb_to_axi4.scala 138:86] - node _T_154 = eq(_T_153, UInt<1>("h00")) @[ahb_to_axi4.scala 138:48] - node _T_155 = and(cmdbuf_vld, _T_154) @[ahb_to_axi4.scala 138:46] - cmdbuf_full <= _T_155 @[ahb_to_axi4.scala 138:31] - node _T_156 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 140:86] - node _T_157 = mux(_T_156, UInt<1>("h01"), cmdbuf_vld) @[ahb_to_axi4.scala 140:66] - node _T_158 = eq(cmdbuf_rst, UInt<1>("h00")) @[ahb_to_axi4.scala 140:110] - node _T_159 = and(_T_157, _T_158) @[ahb_to_axi4.scala 140:108] - reg _T_160 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 140:61] - _T_160 <= _T_159 @[ahb_to_axi4.scala 140:61] - cmdbuf_vld <= _T_160 @[ahb_to_axi4.scala 140:31] - node _T_161 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 144:53] - reg _T_162 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_161 : @[Reg.scala 28:19] - _T_162 <= ahb_hwrite_q @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - cmdbuf_write <= _T_162 @[ahb_to_axi4.scala 143:31] - node _T_163 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 147:52] - reg _T_164 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_163 : @[Reg.scala 28:19] - _T_164 <= ahb_hsize_q @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - cmdbuf_size <= _T_164 @[ahb_to_axi4.scala 146:31] - node _T_165 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 150:53] - reg _T_166 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_165 : @[Reg.scala 28:19] - _T_166 <= master_wstrb @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - cmdbuf_wstrb <= _T_166 @[ahb_to_axi4.scala 149:31] - node _T_167 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 153:57] - inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 368:23] - rvclkhdr_3.clock <= clock - rvclkhdr_3.reset <= reset - rvclkhdr_3.io.clk <= bus_clk @[lib.scala 370:18] - rvclkhdr_3.io.en <= _T_167 @[lib.scala 371:17] - rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_168 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_168 <= ahb_haddr_q @[lib.scala 374:16] - cmdbuf_addr <= _T_168 @[ahb_to_axi4.scala 153:15] - node _T_169 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 154:68] - inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 368:23] - rvclkhdr_4.clock <= clock - rvclkhdr_4.reset <= reset - rvclkhdr_4.io.clk <= bus_clk @[lib.scala 370:18] - rvclkhdr_4.io.en <= _T_169 @[lib.scala 371:17] - rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_170 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_170 <= io.ahb.sig.out.hwdata @[lib.scala 374:16] - cmdbuf_wdata <= _T_170 @[ahb_to_axi4.scala 154:16] - node _T_171 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 157:42] - io.axi.aw.valid <= _T_171 @[ahb_to_axi4.scala 157:28] - io.axi.aw.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 158:33] - io.axi.aw.bits.addr <= cmdbuf_addr @[ahb_to_axi4.scala 159:33] - node _T_172 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 160:59] - node _T_173 = cat(UInt<1>("h00"), _T_172) @[Cat.scala 29:58] - io.axi.aw.bits.size <= _T_173 @[ahb_to_axi4.scala 160:33] - node _T_174 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - io.axi.aw.bits.prot <= _T_174 @[ahb_to_axi4.scala 161:33] - node _T_175 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - io.axi.aw.bits.len <= _T_175 @[ahb_to_axi4.scala 162:33] - io.axi.aw.bits.burst <= UInt<1>("h01") @[ahb_to_axi4.scala 163:33] - node _T_176 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 165:42] - io.axi.w.valid <= _T_176 @[ahb_to_axi4.scala 165:28] - io.axi.w.bits.data <= cmdbuf_wdata @[ahb_to_axi4.scala 166:33] - io.axi.w.bits.strb <= cmdbuf_wstrb @[ahb_to_axi4.scala 167:33] - io.axi.w.bits.last <= UInt<1>("h01") @[ahb_to_axi4.scala 168:33] - io.axi.b.ready <= UInt<1>("h01") @[ahb_to_axi4.scala 170:28] - node _T_177 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 172:44] - node _T_178 = and(cmdbuf_vld, _T_177) @[ahb_to_axi4.scala 172:42] - io.axi.ar.valid <= _T_178 @[ahb_to_axi4.scala 172:28] - io.axi.ar.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 173:33] - io.axi.ar.bits.addr <= cmdbuf_addr @[ahb_to_axi4.scala 174:33] - node _T_179 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 175:59] - node _T_180 = cat(UInt<1>("h00"), _T_179) @[Cat.scala 29:58] - io.axi.ar.bits.size <= _T_180 @[ahb_to_axi4.scala 175:33] - node _T_181 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - io.axi.ar.bits.prot <= _T_181 @[ahb_to_axi4.scala 176:33] - node _T_182 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - io.axi.ar.bits.len <= _T_182 @[ahb_to_axi4.scala 177:33] - io.axi.ar.bits.burst <= UInt<1>("h01") @[ahb_to_axi4.scala 178:33] - io.axi.r.ready <= UInt<1>("h01") @[ahb_to_axi4.scala 180:28] - inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 343:22] - rvclkhdr_5.clock <= clock - rvclkhdr_5.reset <= reset - rvclkhdr_5.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_5.io.en <= io.bus_clk_en @[lib.scala 345:16] - rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - bus_clk <= rvclkhdr_5.io.l1clk @[ahb_to_axi4.scala 181:27] - diff --git a/ahb_to_axi4.v b/ahb_to_axi4.v deleted file mode 100644 index b65746cd..00000000 --- a/ahb_to_axi4.v +++ /dev/null @@ -1,584 +0,0 @@ -module rvclkhdr( - output io_l1clk, - input io_clk, - input io_en, - input io_scan_mode -); - wire clkhdr_Q; // @[lib.scala 334:26] - wire clkhdr_CK; // @[lib.scala 334:26] - wire clkhdr_EN; // @[lib.scala 334:26] - wire clkhdr_SE; // @[lib.scala 334:26] - gated_latch clkhdr ( // @[lib.scala 334:26] - .Q(clkhdr_Q), - .CK(clkhdr_CK), - .EN(clkhdr_EN), - .SE(clkhdr_SE) - ); - assign io_l1clk = clkhdr_Q; // @[lib.scala 335:14] - assign clkhdr_CK = io_clk; // @[lib.scala 336:18] - assign clkhdr_EN = io_en; // @[lib.scala 337:18] - assign clkhdr_SE = io_scan_mode; // @[lib.scala 338:18] -endmodule -module ahb_to_axi4( - input clock, - input reset, - input io_scan_mode, - input io_bus_clk_en, - input io_clk_override, - input io_axi_aw_ready, - output io_axi_aw_valid, - output io_axi_aw_bits_id, - output [31:0] io_axi_aw_bits_addr, - output [3:0] io_axi_aw_bits_region, - output [7:0] io_axi_aw_bits_len, - output [2:0] io_axi_aw_bits_size, - output [1:0] io_axi_aw_bits_burst, - output io_axi_aw_bits_lock, - output [3:0] io_axi_aw_bits_cache, - output [2:0] io_axi_aw_bits_prot, - output [3:0] io_axi_aw_bits_qos, - input io_axi_w_ready, - output io_axi_w_valid, - output [63:0] io_axi_w_bits_data, - output [7:0] io_axi_w_bits_strb, - output io_axi_w_bits_last, - output io_axi_b_ready, - input io_axi_b_valid, - input [1:0] io_axi_b_bits_resp, - input io_axi_b_bits_id, - input io_axi_ar_ready, - output io_axi_ar_valid, - output io_axi_ar_bits_id, - output [31:0] io_axi_ar_bits_addr, - output [3:0] io_axi_ar_bits_region, - output [7:0] io_axi_ar_bits_len, - output [2:0] io_axi_ar_bits_size, - output [1:0] io_axi_ar_bits_burst, - output io_axi_ar_bits_lock, - output [3:0] io_axi_ar_bits_cache, - output [2:0] io_axi_ar_bits_prot, - output [3:0] io_axi_ar_bits_qos, - output io_axi_r_ready, - input io_axi_r_valid, - input io_axi_r_bits_id, - input [63:0] io_axi_r_bits_data, - input [1:0] io_axi_r_bits_resp, - input io_axi_r_bits_last, - output [63:0] io_ahb_sig_in_hrdata, - output io_ahb_sig_in_hready, - output io_ahb_sig_in_hresp, - input [31:0] io_ahb_sig_out_haddr, - input [2:0] io_ahb_sig_out_hburst, - input io_ahb_sig_out_hmastlock, - input [3:0] io_ahb_sig_out_hprot, - input [2:0] io_ahb_sig_out_hsize, - input [1:0] io_ahb_sig_out_htrans, - input io_ahb_sig_out_hwrite, - input [63:0] io_ahb_sig_out_hwdata, - input io_ahb_hsel, - input io_ahb_hreadyin -); -`ifdef RANDOMIZE_REG_INIT - reg [31:0] _RAND_0; - reg [31:0] _RAND_1; - reg [31:0] _RAND_2; - reg [31:0] _RAND_3; - reg [31:0] _RAND_4; - reg [31:0] _RAND_5; - reg [31:0] _RAND_6; - reg [31:0] _RAND_7; - reg [63:0] _RAND_8; - reg [31:0] _RAND_9; - reg [31:0] _RAND_10; - reg [31:0] _RAND_11; - reg [31:0] _RAND_12; - reg [31:0] _RAND_13; - reg [63:0] _RAND_14; -`endif // RANDOMIZE_REG_INIT - wire rvclkhdr_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_io_en; // @[lib.scala 343:22] - wire rvclkhdr_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_1_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_1_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_1_io_en; // @[lib.scala 343:22] - wire rvclkhdr_1_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_2_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_2_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_2_io_en; // @[lib.scala 343:22] - wire rvclkhdr_2_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_3_io_l1clk; // @[lib.scala 368:23] - wire rvclkhdr_3_io_clk; // @[lib.scala 368:23] - wire rvclkhdr_3_io_en; // @[lib.scala 368:23] - wire rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23] - wire rvclkhdr_4_io_l1clk; // @[lib.scala 368:23] - wire rvclkhdr_4_io_clk; // @[lib.scala 368:23] - wire rvclkhdr_4_io_en; // @[lib.scala 368:23] - wire rvclkhdr_4_io_scan_mode; // @[lib.scala 368:23] - wire rvclkhdr_5_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_5_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_5_io_en; // @[lib.scala 343:22] - wire rvclkhdr_5_io_scan_mode; // @[lib.scala 343:22] - wire ahb_addr_clk = rvclkhdr_1_io_l1clk; // @[ahb_to_axi4.scala 45:33 ahb_to_axi4.scala 134:31] - reg [31:0] ahb_haddr_q; // @[ahb_to_axi4.scala 127:65] - wire ahb_addr_in_dccm = ahb_haddr_q[31:16] == 16'hf004; // @[lib.scala 87:29] - wire ahb_addr_in_iccm = ahb_haddr_q[31:16] == 16'hee00; // @[lib.scala 87:29] - wire ahb_clk = rvclkhdr_io_l1clk; // @[ahb_to_axi4.scala 44:33 ahb_to_axi4.scala 133:31] - reg [1:0] buf_state; // @[Reg.scala 27:20] - wire _T_7 = 2'h0 == buf_state; // @[Conditional.scala 37:30] - wire ahb_hready = io_ahb_sig_in_hready & io_ahb_hreadyin; // @[ahb_to_axi4.scala 105:55] - wire _T_10 = ahb_hready & io_ahb_sig_out_htrans[1]; // @[ahb_to_axi4.scala 77:34] - wire _T_11 = _T_10 & io_ahb_hsel; // @[ahb_to_axi4.scala 77:61] - wire _T_12 = 2'h1 == buf_state; // @[Conditional.scala 37:30] - wire _T_14 = io_ahb_sig_out_htrans == 2'h0; // @[ahb_to_axi4.scala 80:79] - wire _T_15 = io_ahb_sig_in_hresp | _T_14; // @[ahb_to_axi4.scala 80:48] - wire _T_16 = ~io_ahb_hsel; // @[ahb_to_axi4.scala 80:93] - wire _T_17 = _T_15 | _T_16; // @[ahb_to_axi4.scala 80:91] - wire bus_clk = rvclkhdr_5_io_l1clk; // @[ahb_to_axi4.scala 58:33 ahb_to_axi4.scala 181:27] - reg cmdbuf_vld; // @[ahb_to_axi4.scala 140:61] - wire _T_151 = io_axi_aw_valid & io_axi_aw_ready; // @[ahb_to_axi4.scala 138:67] - wire _T_152 = io_axi_ar_valid & io_axi_ar_ready; // @[ahb_to_axi4.scala 138:105] - wire _T_153 = _T_151 | _T_152; // @[ahb_to_axi4.scala 138:86] - wire _T_154 = ~_T_153; // @[ahb_to_axi4.scala 138:48] - wire cmdbuf_full = cmdbuf_vld & _T_154; // @[ahb_to_axi4.scala 138:46] - wire _T_21 = ~cmdbuf_full; // @[ahb_to_axi4.scala 81:24] - wire _T_22 = _T_21 | io_ahb_sig_in_hresp; // @[ahb_to_axi4.scala 81:37] - wire _T_25 = io_ahb_sig_out_htrans == 2'h1; // @[ahb_to_axi4.scala 82:92] - wire _T_26 = _T_25 & io_ahb_hsel; // @[ahb_to_axi4.scala 82:110] - wire _T_27 = io_ahb_sig_in_hresp | _T_26; // @[ahb_to_axi4.scala 82:60] - wire _T_28 = ~_T_27; // @[ahb_to_axi4.scala 82:38] - wire _T_29 = _T_21 & _T_28; // @[ahb_to_axi4.scala 82:36] - wire _T_30 = 2'h2 == buf_state; // @[Conditional.scala 37:30] - wire _T_34 = ~io_ahb_sig_in_hresp; // @[ahb_to_axi4.scala 87:23] - wire _T_36 = _T_34 & _T_21; // @[ahb_to_axi4.scala 87:44] - wire _T_37 = 2'h3 == buf_state; // @[Conditional.scala 37:30] - reg cmdbuf_write; // @[Reg.scala 27:20] - wire _T_38 = ~cmdbuf_write; // @[ahb_to_axi4.scala 91:40] - wire _T_39 = io_axi_r_valid & _T_38; // @[ahb_to_axi4.scala 91:38] - wire _T_41 = |io_axi_r_bits_resp; // @[ahb_to_axi4.scala 93:68] - wire _GEN_1 = _T_37 & _T_39; // @[Conditional.scala 39:67] - wire _GEN_5 = _T_30 ? _T_22 : _GEN_1; // @[Conditional.scala 39:67] - wire _GEN_10 = _T_12 ? _T_22 : _GEN_5; // @[Conditional.scala 39:67] - wire buf_state_en = _T_7 ? _T_11 : _GEN_10; // @[Conditional.scala 40:58] - wire _T_42 = buf_state_en & _T_41; // @[ahb_to_axi4.scala 93:41] - wire _GEN_2 = _T_37 & buf_state_en; // @[Conditional.scala 39:67] - wire _GEN_3 = _T_37 & _T_42; // @[Conditional.scala 39:67] - wire _GEN_6 = _T_30 & _T_36; // @[Conditional.scala 39:67] - wire _GEN_7 = _T_30 ? 1'h0 : _GEN_2; // @[Conditional.scala 39:67] - wire _GEN_11 = _T_12 ? _T_29 : _GEN_6; // @[Conditional.scala 39:67] - wire _GEN_12 = _T_12 ? 1'h0 : _GEN_7; // @[Conditional.scala 39:67] - wire cmdbuf_wr_en = _T_7 ? 1'h0 : _GEN_11; // @[Conditional.scala 40:58] - wire buf_rdata_en = _T_7 ? 1'h0 : _GEN_12; // @[Conditional.scala 40:58] - reg [2:0] ahb_hsize_q; // @[ahb_to_axi4.scala 125:65] - wire _T_46 = ahb_hsize_q == 3'h0; // @[ahb_to_axi4.scala 98:60] - wire [7:0] _T_48 = _T_46 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_50 = 8'h1 << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 98:78] - wire [7:0] _T_51 = _T_48 & _T_50; // @[ahb_to_axi4.scala 98:70] - wire _T_53 = ahb_hsize_q == 3'h1; // @[ahb_to_axi4.scala 99:30] - wire [7:0] _T_55 = _T_53 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [8:0] _T_57 = 9'h3 << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 99:48] - wire [8:0] _GEN_23 = {{1'd0}, _T_55}; // @[ahb_to_axi4.scala 99:40] - wire [8:0] _T_58 = _GEN_23 & _T_57; // @[ahb_to_axi4.scala 99:40] - wire [8:0] _GEN_24 = {{1'd0}, _T_51}; // @[ahb_to_axi4.scala 98:109] - wire [8:0] _T_59 = _GEN_24 | _T_58; // @[ahb_to_axi4.scala 98:109] - wire _T_61 = ahb_hsize_q == 3'h2; // @[ahb_to_axi4.scala 100:30] - wire [7:0] _T_63 = _T_61 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [10:0] _T_65 = 11'hf << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 100:48] - wire [10:0] _GEN_25 = {{3'd0}, _T_63}; // @[ahb_to_axi4.scala 100:40] - wire [10:0] _T_66 = _GEN_25 & _T_65; // @[ahb_to_axi4.scala 100:40] - wire [10:0] _GEN_26 = {{2'd0}, _T_59}; // @[ahb_to_axi4.scala 99:79] - wire [10:0] _T_67 = _GEN_26 | _T_66; // @[ahb_to_axi4.scala 99:79] - wire _T_69 = ahb_hsize_q == 3'h3; // @[ahb_to_axi4.scala 101:30] - wire [7:0] _T_71 = _T_69 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [10:0] _GEN_27 = {{3'd0}, _T_71}; // @[ahb_to_axi4.scala 100:79] - wire [10:0] _T_73 = _T_67 | _GEN_27; // @[ahb_to_axi4.scala 100:79] - reg ahb_hready_q; // @[ahb_to_axi4.scala 123:60] - wire _T_74 = ~ahb_hready_q; // @[ahb_to_axi4.scala 104:80] - reg ahb_hresp_q; // @[ahb_to_axi4.scala 122:60] - wire _T_75 = ahb_hresp_q & _T_74; // @[ahb_to_axi4.scala 104:78] - wire _T_77 = buf_state == 2'h0; // @[ahb_to_axi4.scala 104:124] - wire _T_78 = _T_21 | _T_77; // @[ahb_to_axi4.scala 104:111] - wire _T_79 = buf_state == 2'h2; // @[ahb_to_axi4.scala 104:149] - wire _T_80 = buf_state == 2'h3; // @[ahb_to_axi4.scala 104:168] - wire _T_81 = _T_79 | _T_80; // @[ahb_to_axi4.scala 104:156] - wire _T_82 = ~_T_81; // @[ahb_to_axi4.scala 104:137] - wire _T_83 = _T_78 & _T_82; // @[ahb_to_axi4.scala 104:135] - reg buf_read_error; // @[ahb_to_axi4.scala 119:60] - wire _T_84 = ~buf_read_error; // @[ahb_to_axi4.scala 104:181] - wire _T_85 = _T_83 & _T_84; // @[ahb_to_axi4.scala 104:179] - wire [1:0] _T_89 = io_ahb_hsel ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire buf_rdata_clk = rvclkhdr_2_io_l1clk; // @[ahb_to_axi4.scala 46:33 ahb_to_axi4.scala 135:31] - reg [63:0] buf_rdata; // @[ahb_to_axi4.scala 118:66] - reg [1:0] ahb_htrans_q; // @[ahb_to_axi4.scala 124:60] - wire _T_94 = ahb_htrans_q != 2'h0; // @[ahb_to_axi4.scala 108:61] - wire _T_95 = buf_state != 2'h0; // @[ahb_to_axi4.scala 108:83] - wire _T_96 = _T_94 & _T_95; // @[ahb_to_axi4.scala 108:70] - wire _T_97 = ahb_addr_in_dccm | ahb_addr_in_iccm; // @[ahb_to_axi4.scala 109:26] - wire _T_98 = ~_T_97; // @[ahb_to_axi4.scala 109:7] - reg ahb_hwrite_q; // @[ahb_to_axi4.scala 126:65] - wire _T_99 = ahb_addr_in_dccm & ahb_hwrite_q; // @[ahb_to_axi4.scala 110:46] - wire _T_100 = ahb_addr_in_iccm | _T_99; // @[ahb_to_axi4.scala 110:26] - wire _T_102 = ahb_hsize_q[1:0] == 2'h2; // @[ahb_to_axi4.scala 110:86] - wire _T_104 = ahb_hsize_q[1:0] == 2'h3; // @[ahb_to_axi4.scala 110:115] - wire _T_105 = _T_102 | _T_104; // @[ahb_to_axi4.scala 110:95] - wire _T_106 = ~_T_105; // @[ahb_to_axi4.scala 110:66] - wire _T_107 = _T_100 & _T_106; // @[ahb_to_axi4.scala 110:64] - wire _T_108 = _T_98 | _T_107; // @[ahb_to_axi4.scala 109:47] - wire _T_112 = _T_53 & ahb_haddr_q[0]; // @[ahb_to_axi4.scala 111:35] - wire _T_113 = _T_108 | _T_112; // @[ahb_to_axi4.scala 110:126] - wire _T_117 = |ahb_haddr_q[1:0]; // @[ahb_to_axi4.scala 112:56] - wire _T_118 = _T_61 & _T_117; // @[ahb_to_axi4.scala 112:35] - wire _T_119 = _T_113 | _T_118; // @[ahb_to_axi4.scala 111:55] - wire _T_123 = |ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 113:56] - wire _T_124 = _T_69 & _T_123; // @[ahb_to_axi4.scala 113:35] - wire _T_125 = _T_119 | _T_124; // @[ahb_to_axi4.scala 112:61] - wire _T_126 = _T_96 & _T_125; // @[ahb_to_axi4.scala 108:94] - wire _T_127 = _T_126 | buf_read_error; // @[ahb_to_axi4.scala 113:63] - wire _T_146 = ~cmdbuf_wr_en; // @[ahb_to_axi4.scala 137:113] - wire _T_147 = _T_153 & _T_146; // @[ahb_to_axi4.scala 137:111] - wire _T_149 = io_ahb_sig_in_hresp & _T_38; // @[ahb_to_axi4.scala 137:151] - wire cmdbuf_rst = _T_147 | _T_149; // @[ahb_to_axi4.scala 137:128] - wire _T_157 = cmdbuf_wr_en | cmdbuf_vld; // @[ahb_to_axi4.scala 140:66] - wire _T_158 = ~cmdbuf_rst; // @[ahb_to_axi4.scala 140:110] - reg [2:0] _T_164; // @[Reg.scala 27:20] - reg [7:0] cmdbuf_wstrb; // @[Reg.scala 27:20] - wire [7:0] master_wstrb = _T_73[7:0]; // @[ahb_to_axi4.scala 98:31] - reg [31:0] cmdbuf_addr; // @[lib.scala 374:16] - reg [63:0] cmdbuf_wdata; // @[lib.scala 374:16] - wire [1:0] cmdbuf_size = _T_164[1:0]; // @[ahb_to_axi4.scala 146:31] - rvclkhdr rvclkhdr ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_io_l1clk), - .io_clk(rvclkhdr_io_clk), - .io_en(rvclkhdr_io_en), - .io_scan_mode(rvclkhdr_io_scan_mode) - ); - rvclkhdr rvclkhdr_1 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_1_io_l1clk), - .io_clk(rvclkhdr_1_io_clk), - .io_en(rvclkhdr_1_io_en), - .io_scan_mode(rvclkhdr_1_io_scan_mode) - ); - rvclkhdr rvclkhdr_2 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_2_io_l1clk), - .io_clk(rvclkhdr_2_io_clk), - .io_en(rvclkhdr_2_io_en), - .io_scan_mode(rvclkhdr_2_io_scan_mode) - ); - rvclkhdr rvclkhdr_3 ( // @[lib.scala 368:23] - .io_l1clk(rvclkhdr_3_io_l1clk), - .io_clk(rvclkhdr_3_io_clk), - .io_en(rvclkhdr_3_io_en), - .io_scan_mode(rvclkhdr_3_io_scan_mode) - ); - rvclkhdr rvclkhdr_4 ( // @[lib.scala 368:23] - .io_l1clk(rvclkhdr_4_io_l1clk), - .io_clk(rvclkhdr_4_io_clk), - .io_en(rvclkhdr_4_io_en), - .io_scan_mode(rvclkhdr_4_io_scan_mode) - ); - rvclkhdr rvclkhdr_5 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_5_io_l1clk), - .io_clk(rvclkhdr_5_io_clk), - .io_en(rvclkhdr_5_io_en), - .io_scan_mode(rvclkhdr_5_io_scan_mode) - ); - assign io_axi_aw_valid = cmdbuf_vld & cmdbuf_write; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 157:28] - assign io_axi_aw_bits_id = 1'h0; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 158:33] - assign io_axi_aw_bits_addr = cmdbuf_addr; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 159:33] - assign io_axi_aw_bits_region = 4'h0; // @[ahb_to_axi4.scala 20:10] - assign io_axi_aw_bits_len = 8'h0; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 162:33] - assign io_axi_aw_bits_size = {1'h0,cmdbuf_size}; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 160:33] - assign io_axi_aw_bits_burst = 2'h1; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 163:33] - assign io_axi_aw_bits_lock = 1'h0; // @[ahb_to_axi4.scala 20:10] - assign io_axi_aw_bits_cache = 4'h0; // @[ahb_to_axi4.scala 20:10] - assign io_axi_aw_bits_prot = 3'h0; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 161:33] - assign io_axi_aw_bits_qos = 4'h0; // @[ahb_to_axi4.scala 20:10] - assign io_axi_w_valid = cmdbuf_vld & cmdbuf_write; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 165:28] - assign io_axi_w_bits_data = cmdbuf_wdata; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 166:33] - assign io_axi_w_bits_strb = cmdbuf_wstrb; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 167:33] - assign io_axi_w_bits_last = 1'h1; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 168:33] - assign io_axi_b_ready = 1'h1; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 170:28] - assign io_axi_ar_valid = cmdbuf_vld & _T_38; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 172:28] - assign io_axi_ar_bits_id = 1'h0; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 173:33] - assign io_axi_ar_bits_addr = cmdbuf_addr; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 174:33] - assign io_axi_ar_bits_region = 4'h0; // @[ahb_to_axi4.scala 20:10] - assign io_axi_ar_bits_len = 8'h0; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 177:33] - assign io_axi_ar_bits_size = {1'h0,cmdbuf_size}; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 175:33] - assign io_axi_ar_bits_burst = 2'h1; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 178:33] - assign io_axi_ar_bits_lock = 1'h0; // @[ahb_to_axi4.scala 20:10] - assign io_axi_ar_bits_cache = 4'h0; // @[ahb_to_axi4.scala 20:10] - assign io_axi_ar_bits_prot = 3'h0; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 176:33] - assign io_axi_ar_bits_qos = 4'h0; // @[ahb_to_axi4.scala 20:10] - assign io_axi_r_ready = 1'h1; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 180:28] - assign io_ahb_sig_in_hrdata = buf_rdata; // @[ahb_to_axi4.scala 107:38] - assign io_ahb_sig_in_hready = io_ahb_sig_in_hresp ? _T_75 : _T_85; // @[ahb_to_axi4.scala 104:38] - assign io_ahb_sig_in_hresp = _T_127 | _T_75; // @[ahb_to_axi4.scala 108:38] - assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_io_en = io_bus_clk_en; // @[lib.scala 345:16] - assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_1_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_1_io_en = io_bus_clk_en & _T_10; // @[lib.scala 345:16] - assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_2_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_2_io_en = io_bus_clk_en & buf_rdata_en; // @[lib.scala 345:16] - assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_3_io_clk = rvclkhdr_5_io_l1clk; // @[lib.scala 370:18] - assign rvclkhdr_3_io_en = _T_7 ? 1'h0 : _GEN_11; // @[lib.scala 371:17] - assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] - assign rvclkhdr_4_io_clk = rvclkhdr_5_io_l1clk; // @[lib.scala 370:18] - assign rvclkhdr_4_io_en = _T_7 ? 1'h0 : _GEN_11; // @[lib.scala 371:17] - assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] - assign rvclkhdr_5_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_5_io_en = io_bus_clk_en; // @[lib.scala 345:16] - assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] -`ifdef RANDOMIZE_GARBAGE_ASSIGN -`define RANDOMIZE -`endif -`ifdef RANDOMIZE_INVALID_ASSIGN -`define RANDOMIZE -`endif -`ifdef RANDOMIZE_REG_INIT -`define RANDOMIZE -`endif -`ifdef RANDOMIZE_MEM_INIT -`define RANDOMIZE -`endif -`ifndef RANDOM -`define RANDOM $random -`endif -`ifdef RANDOMIZE_MEM_INIT - integer initvar; -`endif -`ifndef SYNTHESIS -`ifdef FIRRTL_BEFORE_INITIAL -`FIRRTL_BEFORE_INITIAL -`endif -initial begin - `ifdef RANDOMIZE - `ifdef INIT_RANDOM - `INIT_RANDOM - `endif - `ifndef VERILATOR - `ifdef RANDOMIZE_DELAY - #`RANDOMIZE_DELAY begin end - `else - #0.002 begin end - `endif - `endif -`ifdef RANDOMIZE_REG_INIT - _RAND_0 = {1{`RANDOM}}; - ahb_haddr_q = _RAND_0[31:0]; - _RAND_1 = {1{`RANDOM}}; - buf_state = _RAND_1[1:0]; - _RAND_2 = {1{`RANDOM}}; - cmdbuf_vld = _RAND_2[0:0]; - _RAND_3 = {1{`RANDOM}}; - cmdbuf_write = _RAND_3[0:0]; - _RAND_4 = {1{`RANDOM}}; - ahb_hsize_q = _RAND_4[2:0]; - _RAND_5 = {1{`RANDOM}}; - ahb_hready_q = _RAND_5[0:0]; - _RAND_6 = {1{`RANDOM}}; - ahb_hresp_q = _RAND_6[0:0]; - _RAND_7 = {1{`RANDOM}}; - buf_read_error = _RAND_7[0:0]; - _RAND_8 = {2{`RANDOM}}; - buf_rdata = _RAND_8[63:0]; - _RAND_9 = {1{`RANDOM}}; - ahb_htrans_q = _RAND_9[1:0]; - _RAND_10 = {1{`RANDOM}}; - ahb_hwrite_q = _RAND_10[0:0]; - _RAND_11 = {1{`RANDOM}}; - _T_164 = _RAND_11[2:0]; - _RAND_12 = {1{`RANDOM}}; - cmdbuf_wstrb = _RAND_12[7:0]; - _RAND_13 = {1{`RANDOM}}; - cmdbuf_addr = _RAND_13[31:0]; - _RAND_14 = {2{`RANDOM}}; - cmdbuf_wdata = _RAND_14[63:0]; -`endif // RANDOMIZE_REG_INIT - if (reset) begin - ahb_haddr_q = 32'h0; - end - if (reset) begin - buf_state = 2'h0; - end - if (reset) begin - cmdbuf_vld = 1'h0; - end - if (reset) begin - cmdbuf_write = 1'h0; - end - if (reset) begin - ahb_hsize_q = 3'h0; - end - if (reset) begin - ahb_hready_q = 1'h0; - end - if (reset) begin - ahb_hresp_q = 1'h0; - end - if (reset) begin - buf_read_error = 1'h0; - end - if (reset) begin - buf_rdata = 64'h0; - end - if (reset) begin - ahb_htrans_q = 2'h0; - end - if (reset) begin - ahb_hwrite_q = 1'h0; - end - if (reset) begin - _T_164 = 3'h0; - end - if (reset) begin - cmdbuf_wstrb = 8'h0; - end - if (reset) begin - cmdbuf_addr = 32'h0; - end - if (reset) begin - cmdbuf_wdata = 64'h0; - end - `endif // RANDOMIZE -end // initial -`ifdef FIRRTL_AFTER_INITIAL -`FIRRTL_AFTER_INITIAL -`endif -`endif // SYNTHESIS - always @(posedge ahb_addr_clk or posedge reset) begin - if (reset) begin - ahb_haddr_q <= 32'h0; - end else begin - ahb_haddr_q <= io_ahb_sig_out_haddr; - end - end - always @(posedge ahb_clk or posedge reset) begin - if (reset) begin - buf_state <= 2'h0; - end else if (buf_state_en) begin - if (_T_7) begin - if (io_ahb_sig_out_hwrite) begin - buf_state <= 2'h1; - end else begin - buf_state <= 2'h2; - end - end else if (_T_12) begin - if (_T_17) begin - buf_state <= 2'h0; - end else if (io_ahb_sig_out_hwrite) begin - buf_state <= 2'h1; - end else begin - buf_state <= 2'h2; - end - end else if (_T_30) begin - if (io_ahb_sig_in_hresp) begin - buf_state <= 2'h0; - end else begin - buf_state <= 2'h3; - end - end else begin - buf_state <= 2'h0; - end - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - cmdbuf_vld <= 1'h0; - end else begin - cmdbuf_vld <= _T_157 & _T_158; - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - cmdbuf_write <= 1'h0; - end else if (cmdbuf_wr_en) begin - cmdbuf_write <= ahb_hwrite_q; - end - end - always @(posedge ahb_addr_clk or posedge reset) begin - if (reset) begin - ahb_hsize_q <= 3'h0; - end else begin - ahb_hsize_q <= io_ahb_sig_out_hsize; - end - end - always @(posedge ahb_clk or posedge reset) begin - if (reset) begin - ahb_hready_q <= 1'h0; - end else begin - ahb_hready_q <= io_ahb_sig_in_hready & io_ahb_hreadyin; - end - end - always @(posedge ahb_clk or posedge reset) begin - if (reset) begin - ahb_hresp_q <= 1'h0; - end else begin - ahb_hresp_q <= io_ahb_sig_in_hresp; - end - end - always @(posedge ahb_clk or posedge reset) begin - if (reset) begin - buf_read_error <= 1'h0; - end else if (_T_7) begin - buf_read_error <= 1'h0; - end else if (_T_12) begin - buf_read_error <= 1'h0; - end else if (_T_30) begin - buf_read_error <= 1'h0; - end else begin - buf_read_error <= _GEN_3; - end - end - always @(posedge buf_rdata_clk or posedge reset) begin - if (reset) begin - buf_rdata <= 64'h0; - end else begin - buf_rdata <= io_axi_r_bits_data; - end - end - always @(posedge ahb_clk or posedge reset) begin - if (reset) begin - ahb_htrans_q <= 2'h0; - end else begin - ahb_htrans_q <= _T_89 & io_ahb_sig_out_htrans; - end - end - always @(posedge ahb_addr_clk or posedge reset) begin - if (reset) begin - ahb_hwrite_q <= 1'h0; - end else begin - ahb_hwrite_q <= io_ahb_sig_out_hwrite; - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - _T_164 <= 3'h0; - end else if (cmdbuf_wr_en) begin - _T_164 <= ahb_hsize_q; - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - cmdbuf_wstrb <= 8'h0; - end else if (cmdbuf_wr_en) begin - cmdbuf_wstrb <= master_wstrb; - end - end - always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin - if (reset) begin - cmdbuf_addr <= 32'h0; - end else begin - cmdbuf_addr <= ahb_haddr_q; - end - end - always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin - if (reset) begin - cmdbuf_wdata <= 64'h0; - end else begin - cmdbuf_wdata <= io_ahb_sig_out_hwdata; - end - end -endmodule diff --git a/axi4_to_ahb.anno.json b/axi4_to_ahb.anno.json deleted file mode 100644 index d41890d1..00000000 --- a/axi4_to_ahb.anno.json +++ /dev/null @@ -1,113 +0,0 @@ -[ - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_w_ready", - "sources":[ - "~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid", - "~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready", - "~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_out_hprot", - "sources":[ - "~axi4_to_ahb|axi4_to_ahb>io_axi_ar_bits_prot" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_aw_ready", - "sources":[ - "~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid", - "~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready", - "~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_out_haddr", - "sources":[ - "~axi4_to_ahb|axi4_to_ahb>io_axi_ar_bits_addr", - "~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid", - "~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready", - "~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_b_valid", - "sources":[ - "~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready", - "~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready", - "~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_out_hsize", - "sources":[ - "~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid", - "~axi4_to_ahb|axi4_to_ahb>io_axi_ar_bits_size", - "~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready", - "~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_out_hwrite", - "sources":[ - "~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid", - "~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready", - "~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_out_htrans", - "sources":[ - "~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid", - "~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready", - "~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_r_valid", - "sources":[ - "~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready", - "~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready", - "~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_ready", - "sources":[ - "~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid", - "~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready", - "~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready" - ] - }, - { - "class":"firrtl.EmitCircuitAnnotation", - "emitter":"firrtl.VerilogEmitter" - }, - { - "class":"firrtl.transforms.BlackBoxResourceAnno", - "target":"axi4_to_ahb.gated_latch", - "resourceId":"/vsrc/gated_latch.v" - }, - { - "class":"firrtl.options.TargetDirAnnotation", - "directory":"." - }, - { - "class":"firrtl.options.OutputAnnotationFileAnnotation", - "file":"axi4_to_ahb" - }, - { - "class":"firrtl.transforms.BlackBoxTargetDirAnno", - "targetDir":"." - } -] \ No newline at end of file diff --git a/axi4_to_ahb.fir b/axi4_to_ahb.fir deleted file mode 100644 index 0ecf6351..00000000 --- a/axi4_to_ahb.fir +++ /dev/null @@ -1,1406 +0,0 @@ -;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 -circuit axi4_to_ahb : - extmodule gated_latch : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_1 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_1 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_1 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_2 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_2 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_2 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_3 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_3 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_3 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_4 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_4 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_4 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_5 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_5 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_5 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_6 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_6 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_6 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_7 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_7 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_7 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_8 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_8 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_8 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_9 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_9 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_9 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - module axi4_to_ahb : - input clock : Clock - input reset : AsyncReset - output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ahb : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}} - - wire buf_rst : UInt<1> - buf_rst <= UInt<1>("h00") - buf_rst <= UInt<1>("h00") @[axi4_to_ahb.scala 21:11] - io.ahb.out.htrans <= UInt<1>("h00") @[axi4_to_ahb.scala 22:21] - wire buf_state_en : UInt<1> - buf_state_en <= UInt<1>("h00") - wire ahbm_clk : Clock @[axi4_to_ahb.scala 24:22] - wire ahbm_addr_clk : Clock @[axi4_to_ahb.scala 25:27] - wire ahbm_data_clk : Clock @[axi4_to_ahb.scala 26:27] - wire buf_state : UInt<3> - buf_state <= UInt<3>("h00") - wire buf_nxtstate : UInt<3> - buf_nxtstate <= UInt<3>("h00") - node _T = bits(buf_state_en, 0, 0) @[axi4_to_ahb.scala 30:70] - node _T_1 = mux(_T, buf_nxtstate, buf_state) @[axi4_to_ahb.scala 30:50] - node _T_2 = eq(buf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 30:108] - node _T_3 = bits(_T_2, 0, 0) @[Bitwise.scala 72:15] - node _T_4 = mux(_T_3, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_5 = and(_T_1, _T_4) @[axi4_to_ahb.scala 30:98] - reg _T_6 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 30:45] - _T_6 <= _T_5 @[axi4_to_ahb.scala 30:45] - buf_state <= _T_6 @[axi4_to_ahb.scala 30:13] - wire slave_valid : UInt<1> - slave_valid <= UInt<1>("h00") - wire slave_ready : UInt<1> - slave_ready <= UInt<1>("h00") - wire slave_tag : UInt<3> - slave_tag <= UInt<3>("h00") - wire slave_rdata : UInt<64> - slave_rdata <= UInt<64>("h00") - wire slave_opc : UInt<4> - slave_opc <= UInt<4>("h00") - wire wrbuf_en : UInt<1> - wrbuf_en <= UInt<1>("h00") - wire wrbuf_data_en : UInt<1> - wrbuf_data_en <= UInt<1>("h00") - wire wrbuf_cmd_sent : UInt<1> - wrbuf_cmd_sent <= UInt<1>("h00") - wire wrbuf_rst : UInt<1> - wrbuf_rst <= UInt<1>("h00") - wire wrbuf_vld : UInt<1> - wrbuf_vld <= UInt<1>("h00") - wire wrbuf_data_vld : UInt<1> - wrbuf_data_vld <= UInt<1>("h00") - wire wrbuf_tag : UInt<3> - wrbuf_tag <= UInt<3>("h00") - wire wrbuf_size : UInt<3> - wrbuf_size <= UInt<3>("h00") - wire wrbuf_addr : UInt<32> - wrbuf_addr <= UInt<32>("h00") - wire wrbuf_data : UInt<64> - wrbuf_data <= UInt<64>("h00") - wire wrbuf_byteen : UInt<8> - wrbuf_byteen <= UInt<8>("h00") - wire bus_write_clk_en : UInt<1> - bus_write_clk_en <= UInt<1>("h00") - wire bus_clk : Clock @[axi4_to_ahb.scala 50:21] - wire bus_write_clk : Clock @[axi4_to_ahb.scala 51:27] - wire master_valid : UInt<1> - master_valid <= UInt<1>("h00") - wire master_ready : UInt<1> - master_ready <= UInt<1>("h00") - wire master_tag : UInt<3> - master_tag <= UInt<3>("h00") - wire master_addr : UInt<32> - master_addr <= UInt<32>("h00") - wire master_wdata : UInt<64> - master_wdata <= UInt<64>("h00") - wire master_size : UInt<3> - master_size <= UInt<3>("h00") - wire master_opc : UInt<3> - master_opc <= UInt<3>("h00") - wire master_byteen : UInt<8> - master_byteen <= UInt<8>("h00") - wire buf_addr : UInt<32> - buf_addr <= UInt<32>("h00") - wire buf_size : UInt<2> - buf_size <= UInt<2>("h00") - wire buf_write : UInt<1> - buf_write <= UInt<1>("h00") - wire buf_byteen : UInt<8> - buf_byteen <= UInt<8>("h00") - wire buf_aligned : UInt<1> - buf_aligned <= UInt<1>("h00") - wire buf_data : UInt<64> - buf_data <= UInt<64>("h00") - wire buf_tag : UInt<3> - buf_tag <= UInt<3>("h00") - wire buf_tag_in : UInt<3> - buf_tag_in <= UInt<3>("h00") - wire buf_addr_in : UInt<32> - buf_addr_in <= UInt<32>("h00") - wire buf_byteen_in : UInt<8> - buf_byteen_in <= UInt<8>("h00") - wire buf_data_in : UInt<64> - buf_data_in <= UInt<64>("h00") - wire buf_write_in : UInt<1> - buf_write_in <= UInt<1>("h00") - wire buf_aligned_in : UInt<1> - buf_aligned_in <= UInt<1>("h00") - wire buf_size_in : UInt<3> - buf_size_in <= UInt<3>("h00") - wire buf_wr_en : UInt<1> - buf_wr_en <= UInt<1>("h00") - wire buf_data_wr_en : UInt<1> - buf_data_wr_en <= UInt<1>("h00") - wire slvbuf_error_en : UInt<1> - slvbuf_error_en <= UInt<1>("h00") - wire wr_cmd_vld : UInt<1> - wr_cmd_vld <= UInt<1>("h00") - wire cmd_done_rst : UInt<1> - cmd_done_rst <= UInt<1>("h00") - wire cmd_done : UInt<1> - cmd_done <= UInt<1>("h00") - wire cmd_doneQ : UInt<1> - cmd_doneQ <= UInt<1>("h00") - wire trxn_done : UInt<1> - trxn_done <= UInt<1>("h00") - wire buf_cmd_byte_ptr : UInt<3> - buf_cmd_byte_ptr <= UInt<3>("h00") - wire buf_cmd_byte_ptrQ : UInt<3> - buf_cmd_byte_ptrQ <= UInt<3>("h00") - wire buf_cmd_nxtbyte_ptr : UInt<3> - buf_cmd_nxtbyte_ptr <= UInt<3>("h00") - wire buf_cmd_byte_ptr_en : UInt<1> - buf_cmd_byte_ptr_en <= UInt<1>("h00") - wire found : UInt<1> - found <= UInt<1>("h00") - wire slave_valid_pre : UInt<1> - slave_valid_pre <= UInt<1>("h00") - wire ahb_hready_q : UInt<1> - ahb_hready_q <= UInt<1>("h00") - wire ahb_hresp_q : UInt<1> - ahb_hresp_q <= UInt<1>("h00") - wire ahb_htrans_q : UInt<2> - ahb_htrans_q <= UInt<2>("h00") - wire ahb_hwrite_q : UInt<1> - ahb_hwrite_q <= UInt<1>("h00") - wire ahb_hrdata_q : UInt<64> - ahb_hrdata_q <= UInt<64>("h00") - wire slvbuf_write : UInt<1> - slvbuf_write <= UInt<1>("h00") - wire slvbuf_error : UInt<1> - slvbuf_error <= UInt<1>("h00") - wire slvbuf_tag : UInt<3> - slvbuf_tag <= UInt<3>("h00") - wire slvbuf_error_in : UInt<1> - slvbuf_error_in <= UInt<1>("h00") - wire slvbuf_wr_en : UInt<1> - slvbuf_wr_en <= UInt<1>("h00") - wire bypass_en : UInt<1> - bypass_en <= UInt<1>("h00") - wire rd_bypass_idle : UInt<1> - rd_bypass_idle <= UInt<1>("h00") - wire last_addr_en : UInt<1> - last_addr_en <= UInt<1>("h00") - wire last_bus_addr : UInt<32> - last_bus_addr <= UInt<32>("h00") - wire buf_clken : UInt<1> - buf_clken <= UInt<1>("h00") - wire slvbuf_clken : UInt<1> - slvbuf_clken <= UInt<1>("h00") - wire ahbm_addr_clken : UInt<1> - ahbm_addr_clken <= UInt<1>("h00") - wire ahbm_data_clken : UInt<1> - ahbm_data_clken <= UInt<1>("h00") - wire buf_clk : Clock @[axi4_to_ahb.scala 118:21] - node _T_7 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 139:27] - wr_cmd_vld <= _T_7 @[axi4_to_ahb.scala 139:14] - node _T_8 = or(wr_cmd_vld, io.axi.ar.valid) @[axi4_to_ahb.scala 140:30] - master_valid <= _T_8 @[axi4_to_ahb.scala 140:16] - node _T_9 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 141:38] - node _T_10 = bits(wrbuf_tag, 2, 0) @[axi4_to_ahb.scala 141:51] - node _T_11 = bits(io.axi.ar.bits.id, 2, 0) @[axi4_to_ahb.scala 141:82] - node _T_12 = mux(_T_9, _T_10, _T_11) @[axi4_to_ahb.scala 141:20] - master_tag <= _T_12 @[axi4_to_ahb.scala 141:14] - node _T_13 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 142:38] - node _T_14 = mux(_T_13, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 142:20] - master_opc <= _T_14 @[axi4_to_ahb.scala 142:14] - node _T_15 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 143:39] - node _T_16 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 143:53] - node _T_17 = bits(io.axi.ar.bits.addr, 31, 0) @[axi4_to_ahb.scala 143:81] - node _T_18 = mux(_T_15, _T_16, _T_17) @[axi4_to_ahb.scala 143:21] - master_addr <= _T_18 @[axi4_to_ahb.scala 143:15] - node _T_19 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 144:39] - node _T_20 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 144:53] - node _T_21 = bits(io.axi.ar.bits.size, 2, 0) @[axi4_to_ahb.scala 144:80] - node _T_22 = mux(_T_19, _T_20, _T_21) @[axi4_to_ahb.scala 144:21] - master_size <= _T_22 @[axi4_to_ahb.scala 144:15] - node _T_23 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 145:32] - master_byteen <= _T_23 @[axi4_to_ahb.scala 145:17] - node _T_24 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 146:29] - master_wdata <= _T_24 @[axi4_to_ahb.scala 146:16] - node _T_25 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 149:33] - node _T_26 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 149:58] - node _T_27 = and(_T_25, _T_26) @[axi4_to_ahb.scala 149:47] - io.axi.b.valid <= _T_27 @[axi4_to_ahb.scala 149:18] - node _T_28 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 150:38] - node _T_29 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 150:65] - node _T_30 = mux(_T_29, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 150:55] - node _T_31 = mux(_T_28, UInt<2>("h02"), _T_30) @[axi4_to_ahb.scala 150:28] - io.axi.b.bits.resp <= _T_31 @[axi4_to_ahb.scala 150:22] - node _T_32 = bits(slave_tag, 2, 0) @[axi4_to_ahb.scala 151:32] - io.axi.b.bits.id <= _T_32 @[axi4_to_ahb.scala 151:20] - node _T_33 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 153:33] - node _T_34 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 153:59] - node _T_35 = eq(_T_34, UInt<1>("h00")) @[axi4_to_ahb.scala 153:66] - node _T_36 = and(_T_33, _T_35) @[axi4_to_ahb.scala 153:47] - io.axi.r.valid <= _T_36 @[axi4_to_ahb.scala 153:18] - node _T_37 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 154:38] - node _T_38 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 154:65] - node _T_39 = mux(_T_38, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 154:55] - node _T_40 = mux(_T_37, UInt<2>("h02"), _T_39) @[axi4_to_ahb.scala 154:28] - io.axi.r.bits.resp <= _T_40 @[axi4_to_ahb.scala 154:22] - node _T_41 = bits(slave_tag, 2, 0) @[axi4_to_ahb.scala 155:32] - io.axi.r.bits.id <= _T_41 @[axi4_to_ahb.scala 155:20] - node _T_42 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 156:36] - io.axi.r.bits.data <= _T_42 @[axi4_to_ahb.scala 156:22] - node _T_43 = and(io.axi.b.ready, io.axi.r.ready) @[axi4_to_ahb.scala 157:33] - slave_ready <= _T_43 @[axi4_to_ahb.scala 157:15] - node _T_44 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 160:57] - node _T_45 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 160:94] - node _T_46 = or(_T_44, _T_45) @[axi4_to_ahb.scala 160:76] - node _T_47 = and(io.bus_clk_en, _T_46) @[axi4_to_ahb.scala 160:37] - bus_write_clk_en <= _T_47 @[axi4_to_ahb.scala 160:20] - inst rvclkhdr of rvclkhdr @[lib.scala 343:22] - rvclkhdr.clock <= clock - rvclkhdr.reset <= reset - rvclkhdr.io.clk <= clock @[lib.scala 344:17] - rvclkhdr.io.en <= io.bus_clk_en @[lib.scala 345:16] - rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - bus_clk <= rvclkhdr.io.l1clk @[axi4_to_ahb.scala 162:11] - node _T_48 = bits(bus_write_clk_en, 0, 0) @[axi4_to_ahb.scala 163:59] - inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 343:22] - rvclkhdr_1.clock <= clock - rvclkhdr_1.reset <= reset - rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_1.io.en <= _T_48 @[lib.scala 345:16] - rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - bus_write_clk <= rvclkhdr_1.io.l1clk @[axi4_to_ahb.scala 163:17] - node _T_49 = eq(UInt<3>("h00"), buf_state) @[Conditional.scala 37:30] - when _T_49 : @[Conditional.scala 40:58] - master_ready <= UInt<1>("h01") @[axi4_to_ahb.scala 167:20] - node _T_50 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 168:34] - node _T_51 = eq(_T_50, UInt<1>("h01")) @[axi4_to_ahb.scala 168:41] - buf_write_in <= _T_51 @[axi4_to_ahb.scala 168:20] - node _T_52 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 169:46] - node _T_53 = mux(_T_52, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 169:26] - buf_nxtstate <= _T_53 @[axi4_to_ahb.scala 169:20] - node _T_54 = and(master_valid, UInt<1>("h01")) @[axi4_to_ahb.scala 170:36] - buf_state_en <= _T_54 @[axi4_to_ahb.scala 170:20] - buf_wr_en <= buf_state_en @[axi4_to_ahb.scala 171:17] - node _T_55 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 172:54] - node _T_56 = and(buf_state_en, _T_55) @[axi4_to_ahb.scala 172:38] - buf_data_wr_en <= _T_56 @[axi4_to_ahb.scala 172:22] - buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 173:27] - node _T_57 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 175:50] - node _T_58 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 175:94] - node _T_59 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_60 = tail(_T_59, 1) @[axi4_to_ahb.scala 135:52] - node _T_61 = mux(UInt<1>("h00"), _T_60, UInt<3>("h00")) @[axi4_to_ahb.scala 135:24] - node _T_62 = bits(_T_58, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_63 = geq(UInt<1>("h00"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_64 = and(_T_62, _T_63) @[axi4_to_ahb.scala 136:48] - node _T_65 = bits(_T_58, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_66 = geq(UInt<1>("h01"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_67 = and(_T_65, _T_66) @[axi4_to_ahb.scala 136:48] - node _T_68 = bits(_T_58, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_69 = geq(UInt<2>("h02"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_70 = and(_T_68, _T_69) @[axi4_to_ahb.scala 136:48] - node _T_71 = bits(_T_58, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_72 = geq(UInt<2>("h03"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_73 = and(_T_71, _T_72) @[axi4_to_ahb.scala 136:48] - node _T_74 = bits(_T_58, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_75 = geq(UInt<3>("h04"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_76 = and(_T_74, _T_75) @[axi4_to_ahb.scala 136:48] - node _T_77 = bits(_T_58, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_78 = geq(UInt<3>("h05"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_79 = and(_T_77, _T_78) @[axi4_to_ahb.scala 136:48] - node _T_80 = bits(_T_58, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_81 = geq(UInt<3>("h06"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_82 = and(_T_80, _T_81) @[axi4_to_ahb.scala 136:48] - node _T_83 = bits(_T_58, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_84 = geq(UInt<3>("h07"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_85 = and(_T_83, _T_84) @[axi4_to_ahb.scala 136:48] - node _T_86 = mux(_T_85, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_87 = mux(_T_82, UInt<3>("h06"), _T_86) @[Mux.scala 98:16] - node _T_88 = mux(_T_79, UInt<3>("h05"), _T_87) @[Mux.scala 98:16] - node _T_89 = mux(_T_76, UInt<3>("h04"), _T_88) @[Mux.scala 98:16] - node _T_90 = mux(_T_73, UInt<2>("h03"), _T_89) @[Mux.scala 98:16] - node _T_91 = mux(_T_70, UInt<2>("h02"), _T_90) @[Mux.scala 98:16] - node _T_92 = mux(_T_67, UInt<1>("h01"), _T_91) @[Mux.scala 98:16] - node _T_93 = mux(_T_64, UInt<1>("h00"), _T_92) @[Mux.scala 98:16] - node _T_94 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 175:124] - node _T_95 = mux(_T_57, _T_93, _T_94) @[axi4_to_ahb.scala 175:30] - buf_cmd_byte_ptr <= _T_95 @[axi4_to_ahb.scala 175:24] - bypass_en <= buf_state_en @[axi4_to_ahb.scala 176:17] - node _T_96 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 177:51] - node _T_97 = and(bypass_en, _T_96) @[axi4_to_ahb.scala 177:35] - rd_bypass_idle <= _T_97 @[axi4_to_ahb.scala 177:22] - node _T_98 = bits(bypass_en, 0, 0) @[Bitwise.scala 72:15] - node _T_99 = mux(_T_98, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_100 = and(_T_99, UInt<2>("h02")) @[axi4_to_ahb.scala 178:49] - io.ahb.out.htrans <= _T_100 @[axi4_to_ahb.scala 178:25] - skip @[Conditional.scala 40:58] - else : @[Conditional.scala 39:67] - node _T_101 = eq(UInt<3>("h01"), buf_state) @[Conditional.scala 37:30] - when _T_101 : @[Conditional.scala 39:67] - node _T_102 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 182:54] - node _T_103 = eq(_T_102, UInt<1>("h00")) @[axi4_to_ahb.scala 182:61] - node _T_104 = and(master_valid, _T_103) @[axi4_to_ahb.scala 182:41] - node _T_105 = bits(_T_104, 0, 0) @[axi4_to_ahb.scala 182:82] - node _T_106 = mux(_T_105, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 182:26] - buf_nxtstate <= _T_106 @[axi4_to_ahb.scala 182:20] - node _T_107 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 183:51] - node _T_108 = neq(_T_107, UInt<1>("h00")) @[axi4_to_ahb.scala 183:58] - node _T_109 = and(ahb_hready_q, _T_108) @[axi4_to_ahb.scala 183:36] - node _T_110 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 183:72] - node _T_111 = and(_T_109, _T_110) @[axi4_to_ahb.scala 183:70] - buf_state_en <= _T_111 @[axi4_to_ahb.scala 183:20] - node _T_112 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 184:34] - node _T_113 = and(buf_state_en, _T_112) @[axi4_to_ahb.scala 184:32] - cmd_done <= _T_113 @[axi4_to_ahb.scala 184:16] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 185:20] - node _T_114 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 186:52] - node _T_115 = neq(_T_114, UInt<1>("h00")) @[axi4_to_ahb.scala 186:59] - node _T_116 = and(ahb_hready_q, _T_115) @[axi4_to_ahb.scala 186:37] - node _T_117 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 186:73] - node _T_118 = and(_T_116, _T_117) @[axi4_to_ahb.scala 186:71] - node _T_119 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 186:122] - node _T_120 = eq(_T_119, UInt<1>("h00")) @[axi4_to_ahb.scala 186:129] - node _T_121 = and(master_valid, _T_120) @[axi4_to_ahb.scala 186:109] - node _T_122 = bits(_T_121, 0, 0) @[axi4_to_ahb.scala 186:150] - node _T_123 = mux(_T_122, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 186:94] - node _T_124 = eq(_T_123, UInt<3>("h06")) @[axi4_to_ahb.scala 186:174] - node _T_125 = and(_T_118, _T_124) @[axi4_to_ahb.scala 186:88] - master_ready <= _T_125 @[axi4_to_ahb.scala 186:20] - buf_wr_en <= master_ready @[axi4_to_ahb.scala 187:17] - node _T_126 = and(master_ready, master_valid) @[axi4_to_ahb.scala 188:33] - bypass_en <= _T_126 @[axi4_to_ahb.scala 188:17] - node _T_127 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 189:47] - node _T_128 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 189:62] - node _T_129 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 189:78] - node _T_130 = mux(_T_127, _T_128, _T_129) @[axi4_to_ahb.scala 189:30] - buf_cmd_byte_ptr <= _T_130 @[axi4_to_ahb.scala 189:24] - node _T_131 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 190:48] - node _T_132 = or(_T_131, bypass_en) @[axi4_to_ahb.scala 190:62] - node _T_133 = bits(_T_132, 0, 0) @[Bitwise.scala 72:15] - node _T_134 = mux(_T_133, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_135 = and(UInt<2>("h02"), _T_134) @[axi4_to_ahb.scala 190:36] - io.ahb.out.htrans <= _T_135 @[axi4_to_ahb.scala 190:25] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_136 = eq(UInt<3>("h06"), buf_state) @[Conditional.scala 37:30] - when _T_136 : @[Conditional.scala 39:67] - node _T_137 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 194:39] - node _T_138 = and(ahb_hready_q, _T_137) @[axi4_to_ahb.scala 194:37] - node _T_139 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 194:82] - node _T_140 = eq(_T_139, UInt<1>("h01")) @[axi4_to_ahb.scala 194:89] - node _T_141 = and(master_valid, _T_140) @[axi4_to_ahb.scala 194:70] - node _T_142 = not(_T_141) @[axi4_to_ahb.scala 194:55] - node _T_143 = and(_T_138, _T_142) @[axi4_to_ahb.scala 194:53] - master_ready <= _T_143 @[axi4_to_ahb.scala 194:20] - node _T_144 = and(master_valid, master_ready) @[axi4_to_ahb.scala 195:34] - node _T_145 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 195:62] - node _T_146 = eq(_T_145, UInt<1>("h00")) @[axi4_to_ahb.scala 195:69] - node _T_147 = and(_T_144, _T_146) @[axi4_to_ahb.scala 195:49] - buf_wr_en <= _T_147 @[axi4_to_ahb.scala 195:17] - node _T_148 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 196:45] - node _T_149 = and(master_valid, master_ready) @[axi4_to_ahb.scala 196:82] - node _T_150 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 196:110] - node _T_151 = eq(_T_150, UInt<1>("h00")) @[axi4_to_ahb.scala 196:117] - node _T_152 = and(_T_149, _T_151) @[axi4_to_ahb.scala 196:97] - node _T_153 = bits(_T_152, 0, 0) @[axi4_to_ahb.scala 196:138] - node _T_154 = mux(_T_153, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 196:67] - node _T_155 = mux(_T_148, UInt<3>("h07"), _T_154) @[axi4_to_ahb.scala 196:26] - buf_nxtstate <= _T_155 @[axi4_to_ahb.scala 196:20] - node _T_156 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 197:37] - buf_state_en <= _T_156 @[axi4_to_ahb.scala 197:20] - buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 198:22] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 199:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 200:23] - node _T_157 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 201:41] - node _T_158 = and(buf_state_en, _T_157) @[axi4_to_ahb.scala 201:39] - slave_valid_pre <= _T_158 @[axi4_to_ahb.scala 201:23] - node _T_159 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 202:34] - node _T_160 = and(buf_state_en, _T_159) @[axi4_to_ahb.scala 202:32] - cmd_done <= _T_160 @[axi4_to_ahb.scala 202:16] - node _T_161 = and(master_ready, master_valid) @[axi4_to_ahb.scala 203:33] - node _T_162 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 203:64] - node _T_163 = and(_T_161, _T_162) @[axi4_to_ahb.scala 203:48] - node _T_164 = and(_T_163, buf_state_en) @[axi4_to_ahb.scala 203:79] - bypass_en <= _T_164 @[axi4_to_ahb.scala 203:17] - node _T_165 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 204:47] - node _T_166 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 204:62] - node _T_167 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 204:78] - node _T_168 = mux(_T_165, _T_166, _T_167) @[axi4_to_ahb.scala 204:30] - buf_cmd_byte_ptr <= _T_168 @[axi4_to_ahb.scala 204:24] - node _T_169 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 205:63] - node _T_170 = and(_T_169, buf_state_en) @[axi4_to_ahb.scala 205:78] - node _T_171 = eq(_T_170, UInt<1>("h00")) @[axi4_to_ahb.scala 205:47] - node _T_172 = bits(_T_171, 0, 0) @[Bitwise.scala 72:15] - node _T_173 = mux(_T_172, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_174 = and(UInt<2>("h02"), _T_173) @[axi4_to_ahb.scala 205:36] - io.ahb.out.htrans <= _T_174 @[axi4_to_ahb.scala 205:25] - slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 206:20] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_175 = eq(UInt<3>("h07"), buf_state) @[Conditional.scala 37:30] - when _T_175 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 210:20] - node _T_176 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 211:51] - node _T_177 = neq(_T_176, UInt<1>("h00")) @[axi4_to_ahb.scala 211:58] - node _T_178 = and(ahb_hready_q, _T_177) @[axi4_to_ahb.scala 211:36] - node _T_179 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 211:72] - node _T_180 = and(_T_178, _T_179) @[axi4_to_ahb.scala 211:70] - buf_state_en <= _T_180 @[axi4_to_ahb.scala 211:20] - slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 212:23] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 213:20] - node _T_181 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 214:35] - buf_cmd_byte_ptr <= _T_181 @[axi4_to_ahb.scala 214:24] - node _T_182 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 215:51] - node _T_183 = bits(_T_182, 0, 0) @[Bitwise.scala 72:15] - node _T_184 = mux(_T_183, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_185 = and(UInt<2>("h02"), _T_184) @[axi4_to_ahb.scala 215:41] - io.ahb.out.htrans <= _T_185 @[axi4_to_ahb.scala 215:25] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_186 = eq(UInt<3>("h03"), buf_state) @[Conditional.scala 37:30] - when _T_186 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 219:20] - node _T_187 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 220:37] - buf_state_en <= _T_187 @[axi4_to_ahb.scala 220:20] - buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 221:22] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 222:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 223:23] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 224:20] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_188 = eq(UInt<3>("h02"), buf_state) @[Conditional.scala 37:30] - when _T_188 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 228:20] - node _T_189 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 229:33] - node _T_190 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 229:63] - node _T_191 = neq(_T_190, UInt<1>("h00")) @[axi4_to_ahb.scala 229:70] - node _T_192 = and(_T_189, _T_191) @[axi4_to_ahb.scala 229:48] - trxn_done <= _T_192 @[axi4_to_ahb.scala 229:17] - buf_state_en <= trxn_done @[axi4_to_ahb.scala 230:20] - buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 231:27] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 232:20] - node _T_193 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 233:47] - node _T_194 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 233:85] - node _T_195 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 233:103] - node _T_196 = add(_T_194, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_197 = tail(_T_196, 1) @[axi4_to_ahb.scala 135:52] - node _T_198 = mux(UInt<1>("h01"), _T_197, _T_194) @[axi4_to_ahb.scala 135:24] - node _T_199 = bits(_T_195, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_200 = geq(UInt<1>("h00"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_201 = and(_T_199, _T_200) @[axi4_to_ahb.scala 136:48] - node _T_202 = bits(_T_195, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_203 = geq(UInt<1>("h01"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_204 = and(_T_202, _T_203) @[axi4_to_ahb.scala 136:48] - node _T_205 = bits(_T_195, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_206 = geq(UInt<2>("h02"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_207 = and(_T_205, _T_206) @[axi4_to_ahb.scala 136:48] - node _T_208 = bits(_T_195, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_209 = geq(UInt<2>("h03"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_210 = and(_T_208, _T_209) @[axi4_to_ahb.scala 136:48] - node _T_211 = bits(_T_195, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_212 = geq(UInt<3>("h04"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_213 = and(_T_211, _T_212) @[axi4_to_ahb.scala 136:48] - node _T_214 = bits(_T_195, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_215 = geq(UInt<3>("h05"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_216 = and(_T_214, _T_215) @[axi4_to_ahb.scala 136:48] - node _T_217 = bits(_T_195, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_218 = geq(UInt<3>("h06"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_219 = and(_T_217, _T_218) @[axi4_to_ahb.scala 136:48] - node _T_220 = bits(_T_195, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_221 = geq(UInt<3>("h07"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_222 = and(_T_220, _T_221) @[axi4_to_ahb.scala 136:48] - node _T_223 = mux(_T_222, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_224 = mux(_T_219, UInt<3>("h06"), _T_223) @[Mux.scala 98:16] - node _T_225 = mux(_T_216, UInt<3>("h05"), _T_224) @[Mux.scala 98:16] - node _T_226 = mux(_T_213, UInt<3>("h04"), _T_225) @[Mux.scala 98:16] - node _T_227 = mux(_T_210, UInt<2>("h03"), _T_226) @[Mux.scala 98:16] - node _T_228 = mux(_T_207, UInt<2>("h02"), _T_227) @[Mux.scala 98:16] - node _T_229 = mux(_T_204, UInt<1>("h01"), _T_228) @[Mux.scala 98:16] - node _T_230 = mux(_T_201, UInt<1>("h00"), _T_229) @[Mux.scala 98:16] - node _T_231 = mux(_T_193, _T_230, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 233:30] - buf_cmd_byte_ptr <= _T_231 @[axi4_to_ahb.scala 233:24] - node _T_232 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 234:65] - node _T_233 = or(buf_aligned, _T_232) @[axi4_to_ahb.scala 234:44] - node _T_234 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 234:127] - node _T_235 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 234:145] - node _T_236 = add(_T_234, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_237 = tail(_T_236, 1) @[axi4_to_ahb.scala 135:52] - node _T_238 = mux(UInt<1>("h01"), _T_237, _T_234) @[axi4_to_ahb.scala 135:24] - node _T_239 = bits(_T_235, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_240 = geq(UInt<1>("h00"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_241 = and(_T_239, _T_240) @[axi4_to_ahb.scala 136:48] - node _T_242 = bits(_T_235, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_243 = geq(UInt<1>("h01"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_244 = and(_T_242, _T_243) @[axi4_to_ahb.scala 136:48] - node _T_245 = bits(_T_235, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_246 = geq(UInt<2>("h02"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_247 = and(_T_245, _T_246) @[axi4_to_ahb.scala 136:48] - node _T_248 = bits(_T_235, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_249 = geq(UInt<2>("h03"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_250 = and(_T_248, _T_249) @[axi4_to_ahb.scala 136:48] - node _T_251 = bits(_T_235, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_252 = geq(UInt<3>("h04"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_253 = and(_T_251, _T_252) @[axi4_to_ahb.scala 136:48] - node _T_254 = bits(_T_235, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_255 = geq(UInt<3>("h05"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_256 = and(_T_254, _T_255) @[axi4_to_ahb.scala 136:48] - node _T_257 = bits(_T_235, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_258 = geq(UInt<3>("h06"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_259 = and(_T_257, _T_258) @[axi4_to_ahb.scala 136:48] - node _T_260 = bits(_T_235, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_261 = geq(UInt<3>("h07"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_262 = and(_T_260, _T_261) @[axi4_to_ahb.scala 136:48] - node _T_263 = mux(_T_262, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_264 = mux(_T_259, UInt<3>("h06"), _T_263) @[Mux.scala 98:16] - node _T_265 = mux(_T_256, UInt<3>("h05"), _T_264) @[Mux.scala 98:16] - node _T_266 = mux(_T_253, UInt<3>("h04"), _T_265) @[Mux.scala 98:16] - node _T_267 = mux(_T_250, UInt<2>("h03"), _T_266) @[Mux.scala 98:16] - node _T_268 = mux(_T_247, UInt<2>("h02"), _T_267) @[Mux.scala 98:16] - node _T_269 = mux(_T_244, UInt<1>("h01"), _T_268) @[Mux.scala 98:16] - node _T_270 = mux(_T_241, UInt<1>("h00"), _T_269) @[Mux.scala 98:16] - node _T_271 = dshr(buf_byteen, _T_270) @[axi4_to_ahb.scala 234:92] - node _T_272 = bits(_T_271, 0, 0) @[axi4_to_ahb.scala 234:92] - node _T_273 = eq(_T_272, UInt<1>("h00")) @[axi4_to_ahb.scala 234:163] - node _T_274 = or(_T_233, _T_273) @[axi4_to_ahb.scala 234:79] - node _T_275 = and(trxn_done, _T_274) @[axi4_to_ahb.scala 234:29] - cmd_done <= _T_275 @[axi4_to_ahb.scala 234:16] - node _T_276 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 235:47] - node _T_277 = eq(_T_276, UInt<1>("h00")) @[axi4_to_ahb.scala 235:36] - node _T_278 = bits(_T_277, 0, 0) @[Bitwise.scala 72:15] - node _T_279 = mux(_T_278, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_280 = and(_T_279, UInt<2>("h02")) @[axi4_to_ahb.scala 235:61] - io.ahb.out.htrans <= _T_280 @[axi4_to_ahb.scala 235:25] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_281 = eq(UInt<3>("h04"), buf_state) @[Conditional.scala 37:30] - when _T_281 : @[Conditional.scala 39:67] - node _T_282 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 239:34] - node _T_283 = or(_T_282, ahb_hresp_q) @[axi4_to_ahb.scala 239:50] - buf_state_en <= _T_283 @[axi4_to_ahb.scala 239:20] - node _T_284 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 240:38] - node _T_285 = and(buf_state_en, _T_284) @[axi4_to_ahb.scala 240:36] - node _T_286 = and(_T_285, slave_ready) @[axi4_to_ahb.scala 240:51] - master_ready <= _T_286 @[axi4_to_ahb.scala 240:20] - node _T_287 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 241:42] - node _T_288 = or(ahb_hresp_q, _T_287) @[axi4_to_ahb.scala 241:40] - node _T_289 = and(master_valid, master_valid) @[axi4_to_ahb.scala 241:80] - node _T_290 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 241:111] - node _T_291 = eq(_T_290, UInt<1>("h01")) @[axi4_to_ahb.scala 241:117] - node _T_292 = bits(_T_291, 0, 0) @[axi4_to_ahb.scala 241:132] - node _T_293 = mux(_T_292, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 241:99] - node _T_294 = mux(_T_289, _T_293, UInt<3>("h00")) @[axi4_to_ahb.scala 241:65] - node _T_295 = mux(_T_288, UInt<3>("h05"), _T_294) @[axi4_to_ahb.scala 241:26] - buf_nxtstate <= _T_295 @[axi4_to_ahb.scala 241:20] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 242:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 243:23] - node _T_296 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 244:33] - node _T_297 = eq(_T_296, UInt<1>("h01")) @[axi4_to_ahb.scala 244:39] - buf_write_in <= _T_297 @[axi4_to_ahb.scala 244:20] - node _T_298 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 245:50] - node _T_299 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 245:78] - node _T_300 = or(_T_298, _T_299) @[axi4_to_ahb.scala 245:62] - node _T_301 = and(buf_state_en, _T_300) @[axi4_to_ahb.scala 245:33] - buf_wr_en <= _T_301 @[axi4_to_ahb.scala 245:17] - buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 246:22] - node _T_302 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 247:65] - node _T_303 = neq(_T_302, UInt<1>("h00")) @[axi4_to_ahb.scala 247:71] - node _T_304 = and(ahb_hready_q, _T_303) @[axi4_to_ahb.scala 247:50] - node _T_305 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 248:29] - node _T_306 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 248:85] - node _T_307 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 248:101] - node _T_308 = add(_T_306, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_309 = tail(_T_308, 1) @[axi4_to_ahb.scala 135:52] - node _T_310 = mux(UInt<1>("h01"), _T_309, _T_306) @[axi4_to_ahb.scala 135:24] - node _T_311 = bits(_T_307, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_312 = geq(UInt<1>("h00"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_313 = and(_T_311, _T_312) @[axi4_to_ahb.scala 136:48] - node _T_314 = bits(_T_307, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_315 = geq(UInt<1>("h01"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_316 = and(_T_314, _T_315) @[axi4_to_ahb.scala 136:48] - node _T_317 = bits(_T_307, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_318 = geq(UInt<2>("h02"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_319 = and(_T_317, _T_318) @[axi4_to_ahb.scala 136:48] - node _T_320 = bits(_T_307, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_321 = geq(UInt<2>("h03"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_322 = and(_T_320, _T_321) @[axi4_to_ahb.scala 136:48] - node _T_323 = bits(_T_307, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_324 = geq(UInt<3>("h04"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_325 = and(_T_323, _T_324) @[axi4_to_ahb.scala 136:48] - node _T_326 = bits(_T_307, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_327 = geq(UInt<3>("h05"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_328 = and(_T_326, _T_327) @[axi4_to_ahb.scala 136:48] - node _T_329 = bits(_T_307, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_330 = geq(UInt<3>("h06"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_331 = and(_T_329, _T_330) @[axi4_to_ahb.scala 136:48] - node _T_332 = bits(_T_307, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_333 = geq(UInt<3>("h07"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_334 = and(_T_332, _T_333) @[axi4_to_ahb.scala 136:48] - node _T_335 = mux(_T_334, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_336 = mux(_T_331, UInt<3>("h06"), _T_335) @[Mux.scala 98:16] - node _T_337 = mux(_T_328, UInt<3>("h05"), _T_336) @[Mux.scala 98:16] - node _T_338 = mux(_T_325, UInt<3>("h04"), _T_337) @[Mux.scala 98:16] - node _T_339 = mux(_T_322, UInt<2>("h03"), _T_338) @[Mux.scala 98:16] - node _T_340 = mux(_T_319, UInt<2>("h02"), _T_339) @[Mux.scala 98:16] - node _T_341 = mux(_T_316, UInt<1>("h01"), _T_340) @[Mux.scala 98:16] - node _T_342 = mux(_T_313, UInt<1>("h00"), _T_341) @[Mux.scala 98:16] - node _T_343 = dshr(buf_byteen, _T_342) @[axi4_to_ahb.scala 248:51] - node _T_344 = bits(_T_343, 0, 0) @[axi4_to_ahb.scala 248:51] - node _T_345 = eq(_T_344, UInt<1>("h00")) @[axi4_to_ahb.scala 248:116] - node _T_346 = or(_T_305, _T_345) @[axi4_to_ahb.scala 248:38] - node _T_347 = and(_T_304, _T_346) @[axi4_to_ahb.scala 247:80] - node _T_348 = or(ahb_hresp_q, _T_347) @[axi4_to_ahb.scala 247:34] - cmd_done <= _T_348 @[axi4_to_ahb.scala 247:16] - node _T_349 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 249:33] - node _T_350 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 249:64] - node _T_351 = and(_T_349, _T_350) @[axi4_to_ahb.scala 249:48] - bypass_en <= _T_351 @[axi4_to_ahb.scala 249:17] - node _T_352 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 250:48] - node _T_353 = eq(_T_352, UInt<1>("h00")) @[axi4_to_ahb.scala 250:37] - node _T_354 = or(_T_353, bypass_en) @[axi4_to_ahb.scala 250:61] - node _T_355 = bits(_T_354, 0, 0) @[Bitwise.scala 72:15] - node _T_356 = mux(_T_355, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_357 = and(_T_356, UInt<2>("h02")) @[axi4_to_ahb.scala 250:75] - io.ahb.out.htrans <= _T_357 @[axi4_to_ahb.scala 250:25] - node _T_358 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 251:55] - node _T_359 = and(buf_state_en, _T_358) @[axi4_to_ahb.scala 251:39] - slave_valid_pre <= _T_359 @[axi4_to_ahb.scala 251:23] - node _T_360 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 252:33] - node _T_361 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 252:63] - node _T_362 = neq(_T_361, UInt<1>("h00")) @[axi4_to_ahb.scala 252:69] - node _T_363 = and(_T_360, _T_362) @[axi4_to_ahb.scala 252:48] - trxn_done <= _T_363 @[axi4_to_ahb.scala 252:17] - node _T_364 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 253:40] - buf_cmd_byte_ptr_en <= _T_364 @[axi4_to_ahb.scala 253:27] - node _T_365 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 254:79] - node _T_366 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_367 = tail(_T_366, 1) @[axi4_to_ahb.scala 135:52] - node _T_368 = mux(UInt<1>("h00"), _T_367, UInt<3>("h00")) @[axi4_to_ahb.scala 135:24] - node _T_369 = bits(_T_365, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_370 = geq(UInt<1>("h00"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_371 = and(_T_369, _T_370) @[axi4_to_ahb.scala 136:48] - node _T_372 = bits(_T_365, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_373 = geq(UInt<1>("h01"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_374 = and(_T_372, _T_373) @[axi4_to_ahb.scala 136:48] - node _T_375 = bits(_T_365, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_376 = geq(UInt<2>("h02"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_377 = and(_T_375, _T_376) @[axi4_to_ahb.scala 136:48] - node _T_378 = bits(_T_365, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_379 = geq(UInt<2>("h03"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_380 = and(_T_378, _T_379) @[axi4_to_ahb.scala 136:48] - node _T_381 = bits(_T_365, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_382 = geq(UInt<3>("h04"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_383 = and(_T_381, _T_382) @[axi4_to_ahb.scala 136:48] - node _T_384 = bits(_T_365, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_385 = geq(UInt<3>("h05"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_386 = and(_T_384, _T_385) @[axi4_to_ahb.scala 136:48] - node _T_387 = bits(_T_365, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_388 = geq(UInt<3>("h06"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_389 = and(_T_387, _T_388) @[axi4_to_ahb.scala 136:48] - node _T_390 = bits(_T_365, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_391 = geq(UInt<3>("h07"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_392 = and(_T_390, _T_391) @[axi4_to_ahb.scala 136:48] - node _T_393 = mux(_T_392, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_394 = mux(_T_389, UInt<3>("h06"), _T_393) @[Mux.scala 98:16] - node _T_395 = mux(_T_386, UInt<3>("h05"), _T_394) @[Mux.scala 98:16] - node _T_396 = mux(_T_383, UInt<3>("h04"), _T_395) @[Mux.scala 98:16] - node _T_397 = mux(_T_380, UInt<2>("h03"), _T_396) @[Mux.scala 98:16] - node _T_398 = mux(_T_377, UInt<2>("h02"), _T_397) @[Mux.scala 98:16] - node _T_399 = mux(_T_374, UInt<1>("h01"), _T_398) @[Mux.scala 98:16] - node _T_400 = mux(_T_371, UInt<1>("h00"), _T_399) @[Mux.scala 98:16] - node _T_401 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 254:141] - node _T_402 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 254:157] - node _T_403 = add(_T_401, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_404 = tail(_T_403, 1) @[axi4_to_ahb.scala 135:52] - node _T_405 = mux(UInt<1>("h01"), _T_404, _T_401) @[axi4_to_ahb.scala 135:24] - node _T_406 = bits(_T_402, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_407 = geq(UInt<1>("h00"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_408 = and(_T_406, _T_407) @[axi4_to_ahb.scala 136:48] - node _T_409 = bits(_T_402, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_410 = geq(UInt<1>("h01"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_411 = and(_T_409, _T_410) @[axi4_to_ahb.scala 136:48] - node _T_412 = bits(_T_402, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_413 = geq(UInt<2>("h02"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_414 = and(_T_412, _T_413) @[axi4_to_ahb.scala 136:48] - node _T_415 = bits(_T_402, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_416 = geq(UInt<2>("h03"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_417 = and(_T_415, _T_416) @[axi4_to_ahb.scala 136:48] - node _T_418 = bits(_T_402, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_419 = geq(UInt<3>("h04"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_420 = and(_T_418, _T_419) @[axi4_to_ahb.scala 136:48] - node _T_421 = bits(_T_402, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_422 = geq(UInt<3>("h05"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_423 = and(_T_421, _T_422) @[axi4_to_ahb.scala 136:48] - node _T_424 = bits(_T_402, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_425 = geq(UInt<3>("h06"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_426 = and(_T_424, _T_425) @[axi4_to_ahb.scala 136:48] - node _T_427 = bits(_T_402, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_428 = geq(UInt<3>("h07"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_429 = and(_T_427, _T_428) @[axi4_to_ahb.scala 136:48] - node _T_430 = mux(_T_429, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_431 = mux(_T_426, UInt<3>("h06"), _T_430) @[Mux.scala 98:16] - node _T_432 = mux(_T_423, UInt<3>("h05"), _T_431) @[Mux.scala 98:16] - node _T_433 = mux(_T_420, UInt<3>("h04"), _T_432) @[Mux.scala 98:16] - node _T_434 = mux(_T_417, UInt<2>("h03"), _T_433) @[Mux.scala 98:16] - node _T_435 = mux(_T_414, UInt<2>("h02"), _T_434) @[Mux.scala 98:16] - node _T_436 = mux(_T_411, UInt<1>("h01"), _T_435) @[Mux.scala 98:16] - node _T_437 = mux(_T_408, UInt<1>("h00"), _T_436) @[Mux.scala 98:16] - node _T_438 = mux(trxn_done, _T_437, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 254:97] - node _T_439 = mux(bypass_en, _T_400, _T_438) @[axi4_to_ahb.scala 254:30] - buf_cmd_byte_ptr <= _T_439 @[axi4_to_ahb.scala 254:24] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_440 = eq(UInt<3>("h05"), buf_state) @[Conditional.scala 37:30] - when _T_440 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 257:20] - buf_state_en <= slave_ready @[axi4_to_ahb.scala 258:20] - slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 259:23] - slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 260:23] - skip @[Conditional.scala 39:67] - cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 264:16] - node _T_441 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 265:33] - node _T_442 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 265:73] - node _T_443 = eq(_T_442, UInt<1>("h01")) @[axi4_to_ahb.scala 265:80] - node _T_444 = and(buf_aligned_in, _T_443) @[axi4_to_ahb.scala 265:60] - node _T_445 = bits(_T_444, 0, 0) @[axi4_to_ahb.scala 265:100] - node _T_446 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 265:132] - node _T_447 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:50] - node _T_448 = eq(_T_447, UInt<8>("h0ff")) @[axi4_to_ahb.scala 127:57] - node _T_449 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:81] - node _T_450 = eq(_T_449, UInt<8>("h0f")) @[axi4_to_ahb.scala 127:88] - node _T_451 = or(_T_448, _T_450) @[axi4_to_ahb.scala 127:70] - node _T_452 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:117] - node _T_453 = eq(_T_452, UInt<8>("h03")) @[axi4_to_ahb.scala 127:124] - node _T_454 = or(_T_451, _T_453) @[axi4_to_ahb.scala 127:106] - node _T_455 = bits(_T_454, 0, 0) @[Bitwise.scala 72:15] - node _T_456 = mux(_T_455, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_457 = and(UInt<3>("h00"), _T_456) @[axi4_to_ahb.scala 127:29] - node _T_458 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 128:35] - node _T_459 = eq(_T_458, UInt<8>("h0c")) @[axi4_to_ahb.scala 128:42] - node _T_460 = bits(_T_459, 0, 0) @[Bitwise.scala 72:15] - node _T_461 = mux(_T_460, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_462 = and(UInt<2>("h02"), _T_461) @[axi4_to_ahb.scala 128:15] - node _T_463 = or(_T_457, _T_462) @[axi4_to_ahb.scala 127:146] - node _T_464 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 129:36] - node _T_465 = eq(_T_464, UInt<8>("h0f0")) @[axi4_to_ahb.scala 129:43] - node _T_466 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 129:67] - node _T_467 = eq(_T_466, UInt<8>("h03")) @[axi4_to_ahb.scala 129:74] - node _T_468 = or(_T_465, _T_467) @[axi4_to_ahb.scala 129:56] - node _T_469 = bits(_T_468, 0, 0) @[Bitwise.scala 72:15] - node _T_470 = mux(_T_469, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_471 = and(UInt<3>("h04"), _T_470) @[axi4_to_ahb.scala 129:15] - node _T_472 = or(_T_463, _T_471) @[axi4_to_ahb.scala 128:63] - node _T_473 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 130:35] - node _T_474 = eq(_T_473, UInt<8>("h0c0")) @[axi4_to_ahb.scala 130:42] - node _T_475 = bits(_T_474, 0, 0) @[Bitwise.scala 72:15] - node _T_476 = mux(_T_475, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_477 = and(UInt<3>("h06"), _T_476) @[axi4_to_ahb.scala 130:15] - node _T_478 = or(_T_472, _T_477) @[axi4_to_ahb.scala 129:96] - node _T_479 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 131:33] - node _T_480 = eq(_T_479, UInt<8>("h0c0")) @[axi4_to_ahb.scala 131:40] - node _T_481 = bits(_T_480, 0, 0) @[Bitwise.scala 72:15] - node _T_482 = mux(_T_481, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_483 = and(UInt<3>("h06"), _T_482) @[axi4_to_ahb.scala 131:13] - node _T_484 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 265:152] - node _T_485 = mux(_T_445, _T_478, _T_484) @[axi4_to_ahb.scala 265:43] - node _T_486 = cat(_T_441, _T_485) @[Cat.scala 29:58] - buf_addr_in <= _T_486 @[axi4_to_ahb.scala 265:15] - node _T_487 = bits(master_tag, 2, 0) @[axi4_to_ahb.scala 266:27] - buf_tag_in <= _T_487 @[axi4_to_ahb.scala 266:14] - node _T_488 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 267:32] - buf_byteen_in <= _T_488 @[axi4_to_ahb.scala 267:17] - node _T_489 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 268:33] - node _T_490 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 268:59] - node _T_491 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 268:80] - node _T_492 = mux(_T_489, _T_490, _T_491) @[axi4_to_ahb.scala 268:21] - buf_data_in <= _T_492 @[axi4_to_ahb.scala 268:15] - node _T_493 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 269:52] - node _T_494 = eq(_T_493, UInt<2>("h03")) @[axi4_to_ahb.scala 269:58] - node _T_495 = and(buf_aligned_in, _T_494) @[axi4_to_ahb.scala 269:38] - node _T_496 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 269:84] - node _T_497 = eq(_T_496, UInt<1>("h01")) @[axi4_to_ahb.scala 269:91] - node _T_498 = and(_T_495, _T_497) @[axi4_to_ahb.scala 269:71] - node _T_499 = bits(_T_498, 0, 0) @[axi4_to_ahb.scala 269:111] - node _T_500 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 269:142] - node _T_501 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 121:42] - node _T_502 = eq(_T_501, UInt<8>("h0ff")) @[axi4_to_ahb.scala 121:49] - node _T_503 = bits(_T_502, 0, 0) @[Bitwise.scala 72:15] - node _T_504 = mux(_T_503, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_505 = and(UInt<2>("h03"), _T_504) @[axi4_to_ahb.scala 121:25] - node _T_506 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 122:35] - node _T_507 = eq(_T_506, UInt<8>("h0f0")) @[axi4_to_ahb.scala 122:42] - node _T_508 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 122:64] - node _T_509 = eq(_T_508, UInt<8>("h0f")) @[axi4_to_ahb.scala 122:71] - node _T_510 = or(_T_507, _T_509) @[axi4_to_ahb.scala 122:55] - node _T_511 = bits(_T_510, 0, 0) @[Bitwise.scala 72:15] - node _T_512 = mux(_T_511, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_513 = and(UInt<2>("h02"), _T_512) @[axi4_to_ahb.scala 122:16] - node _T_514 = or(_T_505, _T_513) @[axi4_to_ahb.scala 121:64] - node _T_515 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:40] - node _T_516 = eq(_T_515, UInt<8>("h0c0")) @[axi4_to_ahb.scala 123:47] - node _T_517 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:69] - node _T_518 = eq(_T_517, UInt<6>("h030")) @[axi4_to_ahb.scala 123:76] - node _T_519 = or(_T_516, _T_518) @[axi4_to_ahb.scala 123:60] - node _T_520 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:98] - node _T_521 = eq(_T_520, UInt<8>("h0c")) @[axi4_to_ahb.scala 123:105] - node _T_522 = or(_T_519, _T_521) @[axi4_to_ahb.scala 123:89] - node _T_523 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:132] - node _T_524 = eq(_T_523, UInt<8>("h03")) @[axi4_to_ahb.scala 123:139] - node _T_525 = or(_T_522, _T_524) @[axi4_to_ahb.scala 123:123] - node _T_526 = bits(_T_525, 0, 0) @[Bitwise.scala 72:15] - node _T_527 = mux(_T_526, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_528 = and(UInt<2>("h01"), _T_527) @[axi4_to_ahb.scala 123:21] - node _T_529 = or(_T_514, _T_528) @[axi4_to_ahb.scala 122:93] - node _T_530 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 269:161] - node _T_531 = mux(_T_499, _T_529, _T_530) @[axi4_to_ahb.scala 269:21] - buf_size_in <= _T_531 @[axi4_to_ahb.scala 269:15] - node _T_532 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 270:32] - node _T_533 = eq(_T_532, UInt<1>("h00")) @[axi4_to_ahb.scala 270:39] - node _T_534 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 271:17] - node _T_535 = eq(_T_534, UInt<1>("h00")) @[axi4_to_ahb.scala 271:24] - node _T_536 = or(_T_533, _T_535) @[axi4_to_ahb.scala 270:48] - node _T_537 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 271:47] - node _T_538 = eq(_T_537, UInt<2>("h01")) @[axi4_to_ahb.scala 271:54] - node _T_539 = or(_T_536, _T_538) @[axi4_to_ahb.scala 271:33] - node _T_540 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 271:86] - node _T_541 = eq(_T_540, UInt<2>("h02")) @[axi4_to_ahb.scala 271:93] - node _T_542 = or(_T_539, _T_541) @[axi4_to_ahb.scala 271:72] - node _T_543 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 272:18] - node _T_544 = eq(_T_543, UInt<2>("h03")) @[axi4_to_ahb.scala 272:25] - node _T_545 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:55] - node _T_546 = eq(_T_545, UInt<2>("h03")) @[axi4_to_ahb.scala 272:62] - node _T_547 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:90] - node _T_548 = eq(_T_547, UInt<4>("h0c")) @[axi4_to_ahb.scala 272:97] - node _T_549 = or(_T_546, _T_548) @[axi4_to_ahb.scala 272:74] - node _T_550 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:125] - node _T_551 = eq(_T_550, UInt<6>("h030")) @[axi4_to_ahb.scala 272:132] - node _T_552 = or(_T_549, _T_551) @[axi4_to_ahb.scala 272:109] - node _T_553 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:161] - node _T_554 = eq(_T_553, UInt<8>("h0c0")) @[axi4_to_ahb.scala 272:168] - node _T_555 = or(_T_552, _T_554) @[axi4_to_ahb.scala 272:145] - node _T_556 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 273:21] - node _T_557 = eq(_T_556, UInt<4>("h0f")) @[axi4_to_ahb.scala 273:28] - node _T_558 = or(_T_555, _T_557) @[axi4_to_ahb.scala 272:181] - node _T_559 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 273:56] - node _T_560 = eq(_T_559, UInt<8>("h0f0")) @[axi4_to_ahb.scala 273:63] - node _T_561 = or(_T_558, _T_560) @[axi4_to_ahb.scala 273:40] - node _T_562 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 273:92] - node _T_563 = eq(_T_562, UInt<8>("h0ff")) @[axi4_to_ahb.scala 273:99] - node _T_564 = or(_T_561, _T_563) @[axi4_to_ahb.scala 273:76] - node _T_565 = and(_T_544, _T_564) @[axi4_to_ahb.scala 272:38] - node _T_566 = or(_T_542, _T_565) @[axi4_to_ahb.scala 271:106] - buf_aligned_in <= _T_566 @[axi4_to_ahb.scala 270:18] - node _T_567 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 275:43] - node _T_568 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 275:62] - node _T_569 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 275:87] - node _T_570 = cat(_T_568, _T_569) @[Cat.scala 29:58] - node _T_571 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 275:108] - node _T_572 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 275:133] - node _T_573 = cat(_T_571, _T_572) @[Cat.scala 29:58] - node _T_574 = mux(_T_567, _T_570, _T_573) @[axi4_to_ahb.scala 275:26] - io.ahb.out.haddr <= _T_574 @[axi4_to_ahb.scala 275:20] - node _T_575 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 276:43] - node _T_576 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15] - node _T_577 = mux(_T_576, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_578 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 276:94] - node _T_579 = and(_T_577, _T_578) @[axi4_to_ahb.scala 276:81] - node _T_580 = cat(UInt<1>("h00"), _T_579) @[Cat.scala 29:58] - node _T_581 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15] - node _T_582 = mux(_T_581, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_583 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 276:148] - node _T_584 = and(_T_582, _T_583) @[axi4_to_ahb.scala 276:138] - node _T_585 = cat(UInt<1>("h00"), _T_584) @[Cat.scala 29:58] - node _T_586 = mux(_T_575, _T_580, _T_585) @[axi4_to_ahb.scala 276:26] - io.ahb.out.hsize <= _T_586 @[axi4_to_ahb.scala 276:20] - io.ahb.out.hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 278:21] - io.ahb.out.hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 279:24] - node _T_587 = bits(io.axi.ar.bits.prot, 2, 2) @[axi4_to_ahb.scala 280:57] - node _T_588 = eq(_T_587, UInt<1>("h00")) @[axi4_to_ahb.scala 280:37] - node _T_589 = cat(UInt<1>("h01"), _T_588) @[Cat.scala 29:58] - io.ahb.out.hprot <= _T_589 @[axi4_to_ahb.scala 280:20] - node _T_590 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 281:44] - node _T_591 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 281:59] - node _T_592 = eq(_T_591, UInt<1>("h01")) @[axi4_to_ahb.scala 281:66] - node _T_593 = mux(_T_590, _T_592, buf_write) @[axi4_to_ahb.scala 281:27] - io.ahb.out.hwrite <= _T_593 @[axi4_to_ahb.scala 281:21] - node _T_594 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 282:32] - io.ahb.out.hwdata <= _T_594 @[axi4_to_ahb.scala 282:21] - slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 284:15] - node _T_595 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 285:43] - node _T_596 = mux(_T_595, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 285:23] - node _T_597 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15] - node _T_598 = mux(_T_597, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_599 = and(_T_598, UInt<2>("h02")) @[axi4_to_ahb.scala 285:88] - node _T_600 = cat(_T_596, _T_599) @[Cat.scala 29:58] - slave_opc <= _T_600 @[axi4_to_ahb.scala 285:13] - node _T_601 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 286:41] - node _T_602 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 286:66] - node _T_603 = cat(_T_602, _T_602) @[Cat.scala 29:58] - node _T_604 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 286:91] - node _T_605 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 286:110] - node _T_606 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 286:131] - node _T_607 = mux(_T_604, _T_605, _T_606) @[axi4_to_ahb.scala 286:79] - node _T_608 = mux(_T_601, _T_603, _T_607) @[axi4_to_ahb.scala 286:21] - slave_rdata <= _T_608 @[axi4_to_ahb.scala 286:15] - node _T_609 = bits(slvbuf_tag, 2, 0) @[axi4_to_ahb.scala 287:26] - slave_tag <= _T_609 @[axi4_to_ahb.scala 287:13] - node _T_610 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 289:37] - node _T_611 = neq(_T_610, UInt<1>("h00")) @[axi4_to_ahb.scala 289:44] - node _T_612 = and(_T_611, io.ahb.in.hready) @[axi4_to_ahb.scala 289:56] - node _T_613 = and(_T_612, io.ahb.out.hwrite) @[axi4_to_ahb.scala 289:75] - last_addr_en <= _T_613 @[axi4_to_ahb.scala 289:16] - node _T_614 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 291:31] - node _T_615 = and(_T_614, master_ready) @[axi4_to_ahb.scala 291:49] - wrbuf_en <= _T_615 @[axi4_to_ahb.scala 291:12] - node _T_616 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 292:35] - node _T_617 = and(_T_616, master_ready) @[axi4_to_ahb.scala 292:52] - wrbuf_data_en <= _T_617 @[axi4_to_ahb.scala 292:17] - node _T_618 = and(master_valid, master_ready) @[axi4_to_ahb.scala 293:34] - node _T_619 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 293:62] - node _T_620 = eq(_T_619, UInt<1>("h01")) @[axi4_to_ahb.scala 293:69] - node _T_621 = and(_T_618, _T_620) @[axi4_to_ahb.scala 293:49] - wrbuf_cmd_sent <= _T_621 @[axi4_to_ahb.scala 293:18] - node _T_622 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 294:33] - node _T_623 = and(wrbuf_cmd_sent, _T_622) @[axi4_to_ahb.scala 294:31] - wrbuf_rst <= _T_623 @[axi4_to_ahb.scala 294:13] - node _T_624 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 296:36] - node _T_625 = and(wrbuf_vld, _T_624) @[axi4_to_ahb.scala 296:34] - node _T_626 = eq(_T_625, UInt<1>("h00")) @[axi4_to_ahb.scala 296:22] - node _T_627 = and(_T_626, master_ready) @[axi4_to_ahb.scala 296:53] - io.axi.aw.ready <= _T_627 @[axi4_to_ahb.scala 296:19] - node _T_628 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 297:40] - node _T_629 = and(wrbuf_data_vld, _T_628) @[axi4_to_ahb.scala 297:38] - node _T_630 = eq(_T_629, UInt<1>("h00")) @[axi4_to_ahb.scala 297:21] - node _T_631 = and(_T_630, master_ready) @[axi4_to_ahb.scala 297:57] - io.axi.w.ready <= _T_631 @[axi4_to_ahb.scala 297:18] - node _T_632 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 298:34] - node _T_633 = eq(_T_632, UInt<1>("h00")) @[axi4_to_ahb.scala 298:22] - node _T_634 = and(_T_633, master_ready) @[axi4_to_ahb.scala 298:52] - io.axi.ar.ready <= _T_634 @[axi4_to_ahb.scala 298:19] - io.axi.r.bits.last <= UInt<1>("h01") @[axi4_to_ahb.scala 299:22] - node _T_635 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 301:71] - node _T_636 = mux(_T_635, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 301:55] - node _T_637 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 301:91] - node _T_638 = and(_T_636, _T_637) @[axi4_to_ahb.scala 301:89] - reg _T_639 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 301:51] - _T_639 <= _T_638 @[axi4_to_ahb.scala 301:51] - wrbuf_vld <= _T_639 @[axi4_to_ahb.scala 301:21] - node _T_640 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 302:76] - node _T_641 = mux(_T_640, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 302:55] - node _T_642 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 302:102] - node _T_643 = and(_T_641, _T_642) @[axi4_to_ahb.scala 302:100] - reg _T_644 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 302:51] - _T_644 <= _T_643 @[axi4_to_ahb.scala 302:51] - wrbuf_data_vld <= _T_644 @[axi4_to_ahb.scala 302:21] - node _T_645 = bits(io.axi.aw.bits.id, 2, 0) @[axi4_to_ahb.scala 303:71] - node _T_646 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 303:105] - reg _T_647 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_646 : @[Reg.scala 28:19] - _T_647 <= _T_645 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - wrbuf_tag <= _T_647 @[axi4_to_ahb.scala 303:21] - node _T_648 = bits(io.axi.aw.bits.size, 2, 0) @[axi4_to_ahb.scala 304:73] - node _T_649 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 304:101] - reg _T_650 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_649 : @[Reg.scala 28:19] - _T_650 <= _T_648 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - wrbuf_size <= _T_650 @[axi4_to_ahb.scala 304:21] - node _T_651 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 305:61] - inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 368:23] - rvclkhdr_2.clock <= clock - rvclkhdr_2.reset <= reset - rvclkhdr_2.io.clk <= bus_clk @[lib.scala 370:18] - rvclkhdr_2.io.en <= _T_651 @[lib.scala 371:17] - rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_652 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_652 <= io.axi.aw.bits.addr @[lib.scala 374:16] - wrbuf_addr <= _T_652 @[axi4_to_ahb.scala 305:21] - node _T_653 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 306:65] - inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 368:23] - rvclkhdr_3.clock <= clock - rvclkhdr_3.reset <= reset - rvclkhdr_3.io.clk <= bus_clk @[lib.scala 370:18] - rvclkhdr_3.io.en <= _T_653 @[lib.scala 371:17] - rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_654 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_654 <= io.axi.w.bits.data @[lib.scala 374:16] - wrbuf_data <= _T_654 @[axi4_to_ahb.scala 306:21] - node _T_655 = bits(io.axi.w.bits.strb, 7, 0) @[axi4_to_ahb.scala 307:72] - node _T_656 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 307:105] - reg _T_657 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_656 : @[Reg.scala 28:19] - _T_657 <= _T_655 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - wrbuf_byteen <= _T_657 @[axi4_to_ahb.scala 307:21] - node _T_658 = bits(io.ahb.out.haddr, 31, 0) @[axi4_to_ahb.scala 308:71] - node _T_659 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 308:104] - reg _T_660 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_659 : @[Reg.scala 28:19] - _T_660 <= _T_658 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - last_bus_addr <= _T_660 @[axi4_to_ahb.scala 308:21] - node _T_661 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 309:89] - reg _T_662 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_661 : @[Reg.scala 28:19] - _T_662 <= buf_write_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_write <= _T_662 @[axi4_to_ahb.scala 309:21] - node _T_663 = bits(buf_tag_in, 2, 0) @[axi4_to_ahb.scala 310:64] - node _T_664 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 310:99] - reg _T_665 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_664 : @[Reg.scala 28:19] - _T_665 <= _T_663 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_tag <= _T_665 @[axi4_to_ahb.scala 310:21] - node _T_666 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 311:42] - node _T_667 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 311:61] - node _T_668 = bits(_T_667, 0, 0) @[axi4_to_ahb.scala 311:78] - inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 368:23] - rvclkhdr_4.clock <= clock - rvclkhdr_4.reset <= reset - rvclkhdr_4.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_4.io.en <= _T_668 @[lib.scala 371:17] - rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_669 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_669 <= _T_666 @[lib.scala 374:16] - buf_addr <= _T_669 @[axi4_to_ahb.scala 311:21] - node _T_670 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 312:65] - node _T_671 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 312:94] - reg _T_672 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_671 : @[Reg.scala 28:19] - _T_672 <= _T_670 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_size <= _T_672 @[axi4_to_ahb.scala 312:21] - node _T_673 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 313:91] - reg _T_674 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_673 : @[Reg.scala 28:19] - _T_674 <= buf_aligned_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_aligned <= _T_674 @[axi4_to_ahb.scala 313:21] - node _T_675 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 314:67] - node _T_676 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 314:96] - reg _T_677 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_676 : @[Reg.scala 28:19] - _T_677 <= _T_675 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_byteen <= _T_677 @[axi4_to_ahb.scala 314:21] - node _T_678 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 315:42] - node _T_679 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 315:66] - node _T_680 = bits(_T_679, 0, 0) @[axi4_to_ahb.scala 315:89] - inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 368:23] - rvclkhdr_5.clock <= clock - rvclkhdr_5.reset <= reset - rvclkhdr_5.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_5.io.en <= _T_680 @[lib.scala 371:17] - rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_681 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_681 <= _T_678 @[lib.scala 374:16] - buf_data <= _T_681 @[axi4_to_ahb.scala 315:21] - node _T_682 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 316:89] - reg _T_683 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_682 : @[Reg.scala 28:19] - _T_683 <= buf_write @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - slvbuf_write <= _T_683 @[axi4_to_ahb.scala 316:21] - node _T_684 = bits(buf_tag, 2, 0) @[axi4_to_ahb.scala 317:61] - node _T_685 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 317:99] - reg _T_686 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_685 : @[Reg.scala 28:19] - _T_686 <= _T_684 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - slvbuf_tag <= _T_686 @[axi4_to_ahb.scala 317:21] - node _T_687 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 318:99] - reg _T_688 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_687 : @[Reg.scala 28:19] - _T_688 <= slvbuf_error_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - slvbuf_error <= _T_688 @[axi4_to_ahb.scala 318:21] - node _T_689 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 319:72] - node _T_690 = mux(_T_689, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 319:56] - node _T_691 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 319:92] - node _T_692 = and(_T_690, _T_691) @[axi4_to_ahb.scala 319:90] - reg _T_693 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 319:52] - _T_693 <= _T_692 @[axi4_to_ahb.scala 319:52] - cmd_doneQ <= _T_693 @[axi4_to_ahb.scala 319:21] - node _T_694 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 320:71] - node _T_695 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 320:110] - reg _T_696 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_695 : @[Reg.scala 28:19] - _T_696 <= _T_694 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_cmd_byte_ptrQ <= _T_696 @[axi4_to_ahb.scala 320:21] - reg _T_697 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 321:52] - _T_697 <= io.ahb.in.hready @[axi4_to_ahb.scala 321:52] - ahb_hready_q <= _T_697 @[axi4_to_ahb.scala 321:21] - node _T_698 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 322:70] - reg _T_699 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 322:52] - _T_699 <= _T_698 @[axi4_to_ahb.scala 322:52] - ahb_htrans_q <= _T_699 @[axi4_to_ahb.scala 322:21] - reg _T_700 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 323:57] - _T_700 <= io.ahb.out.hwrite @[axi4_to_ahb.scala 323:57] - ahb_hwrite_q <= _T_700 @[axi4_to_ahb.scala 323:21] - reg _T_701 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 324:52] - _T_701 <= io.ahb.in.hresp @[axi4_to_ahb.scala 324:52] - ahb_hresp_q <= _T_701 @[axi4_to_ahb.scala 324:21] - node _T_702 = bits(io.ahb.in.hrdata, 63, 0) @[axi4_to_ahb.scala 325:74] - reg _T_703 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 325:57] - _T_703 <= _T_702 @[axi4_to_ahb.scala 325:57] - ahb_hrdata_q <= _T_703 @[axi4_to_ahb.scala 325:21] - node _T_704 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 327:43] - node _T_705 = or(_T_704, io.clk_override) @[axi4_to_ahb.scala 327:58] - node _T_706 = and(io.bus_clk_en, _T_705) @[axi4_to_ahb.scala 327:30] - buf_clken <= _T_706 @[axi4_to_ahb.scala 327:13] - node _T_707 = bits(io.ahb.out.htrans, 1, 1) @[axi4_to_ahb.scala 328:76] - node _T_708 = and(io.ahb.in.hready, _T_707) @[axi4_to_ahb.scala 328:57] - node _T_709 = or(_T_708, io.clk_override) @[axi4_to_ahb.scala 328:81] - node _T_710 = and(io.bus_clk_en, _T_709) @[axi4_to_ahb.scala 328:36] - ahbm_addr_clken <= _T_710 @[axi4_to_ahb.scala 328:19] - node _T_711 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 329:50] - node _T_712 = or(_T_711, io.clk_override) @[axi4_to_ahb.scala 329:60] - node _T_713 = and(io.bus_clk_en, _T_712) @[axi4_to_ahb.scala 329:36] - ahbm_data_clken <= _T_713 @[axi4_to_ahb.scala 329:19] - inst rvclkhdr_6 of rvclkhdr_6 @[lib.scala 343:22] - rvclkhdr_6.clock <= clock - rvclkhdr_6.reset <= reset - rvclkhdr_6.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_6.io.en <= buf_clken @[lib.scala 345:16] - rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 332:12] - inst rvclkhdr_7 of rvclkhdr_7 @[lib.scala 343:22] - rvclkhdr_7.clock <= clock - rvclkhdr_7.reset <= reset - rvclkhdr_7.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_7.io.en <= io.bus_clk_en @[lib.scala 345:16] - rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 333:12] - inst rvclkhdr_8 of rvclkhdr_8 @[lib.scala 343:22] - rvclkhdr_8.clock <= clock - rvclkhdr_8.reset <= reset - rvclkhdr_8.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_8.io.en <= ahbm_addr_clken @[lib.scala 345:16] - rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 334:17] - inst rvclkhdr_9 of rvclkhdr_9 @[lib.scala 343:22] - rvclkhdr_9.clock <= clock - rvclkhdr_9.reset <= reset - rvclkhdr_9.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_9.io.en <= ahbm_data_clken @[lib.scala 345:16] - rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 335:17] - diff --git a/axi4_to_ahb.v b/axi4_to_ahb.v deleted file mode 100644 index 5659c6fa..00000000 --- a/axi4_to_ahb.v +++ /dev/null @@ -1,1139 +0,0 @@ -module rvclkhdr( - output io_l1clk, - input io_clk, - input io_en, - input io_scan_mode -); - wire clkhdr_Q; // @[lib.scala 334:26] - wire clkhdr_CK; // @[lib.scala 334:26] - wire clkhdr_EN; // @[lib.scala 334:26] - wire clkhdr_SE; // @[lib.scala 334:26] - gated_latch clkhdr ( // @[lib.scala 334:26] - .Q(clkhdr_Q), - .CK(clkhdr_CK), - .EN(clkhdr_EN), - .SE(clkhdr_SE) - ); - assign io_l1clk = clkhdr_Q; // @[lib.scala 335:14] - assign clkhdr_CK = io_clk; // @[lib.scala 336:18] - assign clkhdr_EN = io_en; // @[lib.scala 337:18] - assign clkhdr_SE = io_scan_mode; // @[lib.scala 338:18] -endmodule -module axi4_to_ahb( - input clock, - input reset, - input io_scan_mode, - input io_bus_clk_en, - input io_clk_override, - output io_axi_aw_ready, - input io_axi_aw_valid, - input [2:0] io_axi_aw_bits_id, - input [31:0] io_axi_aw_bits_addr, - input [3:0] io_axi_aw_bits_region, - input [7:0] io_axi_aw_bits_len, - input [2:0] io_axi_aw_bits_size, - input [1:0] io_axi_aw_bits_burst, - input io_axi_aw_bits_lock, - input [3:0] io_axi_aw_bits_cache, - input [2:0] io_axi_aw_bits_prot, - input [3:0] io_axi_aw_bits_qos, - output io_axi_w_ready, - input io_axi_w_valid, - input [63:0] io_axi_w_bits_data, - input [7:0] io_axi_w_bits_strb, - input io_axi_w_bits_last, - input io_axi_b_ready, - output io_axi_b_valid, - output [1:0] io_axi_b_bits_resp, - output [2:0] io_axi_b_bits_id, - output io_axi_ar_ready, - input io_axi_ar_valid, - input [2:0] io_axi_ar_bits_id, - input [31:0] io_axi_ar_bits_addr, - input [3:0] io_axi_ar_bits_region, - input [7:0] io_axi_ar_bits_len, - input [2:0] io_axi_ar_bits_size, - input [1:0] io_axi_ar_bits_burst, - input io_axi_ar_bits_lock, - input [3:0] io_axi_ar_bits_cache, - input [2:0] io_axi_ar_bits_prot, - input [3:0] io_axi_ar_bits_qos, - input io_axi_r_ready, - output io_axi_r_valid, - output [2:0] io_axi_r_bits_id, - output [63:0] io_axi_r_bits_data, - output [1:0] io_axi_r_bits_resp, - output io_axi_r_bits_last, - input [63:0] io_ahb_in_hrdata, - input io_ahb_in_hready, - input io_ahb_in_hresp, - output [31:0] io_ahb_out_haddr, - output [2:0] io_ahb_out_hburst, - output io_ahb_out_hmastlock, - output [3:0] io_ahb_out_hprot, - output [2:0] io_ahb_out_hsize, - output [1:0] io_ahb_out_htrans, - output io_ahb_out_hwrite, - output [63:0] io_ahb_out_hwdata -); -`ifdef RANDOMIZE_REG_INIT - reg [31:0] _RAND_0; - reg [31:0] _RAND_1; - reg [31:0] _RAND_2; - reg [31:0] _RAND_3; - reg [31:0] _RAND_4; - reg [31:0] _RAND_5; - reg [31:0] _RAND_6; - reg [31:0] _RAND_7; - reg [31:0] _RAND_8; - reg [31:0] _RAND_9; - reg [31:0] _RAND_10; - reg [31:0] _RAND_11; - reg [63:0] _RAND_12; - reg [31:0] _RAND_13; - reg [31:0] _RAND_14; - reg [31:0] _RAND_15; - reg [31:0] _RAND_16; - reg [63:0] _RAND_17; - reg [63:0] _RAND_18; - reg [31:0] _RAND_19; - reg [31:0] _RAND_20; - reg [31:0] _RAND_21; - reg [31:0] _RAND_22; - reg [31:0] _RAND_23; - reg [31:0] _RAND_24; - reg [31:0] _RAND_25; -`endif // RANDOMIZE_REG_INIT - wire rvclkhdr_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_io_en; // @[lib.scala 343:22] - wire rvclkhdr_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_1_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_1_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_1_io_en; // @[lib.scala 343:22] - wire rvclkhdr_1_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_2_io_l1clk; // @[lib.scala 368:23] - wire rvclkhdr_2_io_clk; // @[lib.scala 368:23] - wire rvclkhdr_2_io_en; // @[lib.scala 368:23] - wire rvclkhdr_2_io_scan_mode; // @[lib.scala 368:23] - wire rvclkhdr_3_io_l1clk; // @[lib.scala 368:23] - wire rvclkhdr_3_io_clk; // @[lib.scala 368:23] - wire rvclkhdr_3_io_en; // @[lib.scala 368:23] - wire rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23] - wire rvclkhdr_4_io_l1clk; // @[lib.scala 368:23] - wire rvclkhdr_4_io_clk; // @[lib.scala 368:23] - wire rvclkhdr_4_io_en; // @[lib.scala 368:23] - wire rvclkhdr_4_io_scan_mode; // @[lib.scala 368:23] - wire rvclkhdr_5_io_l1clk; // @[lib.scala 368:23] - wire rvclkhdr_5_io_clk; // @[lib.scala 368:23] - wire rvclkhdr_5_io_en; // @[lib.scala 368:23] - wire rvclkhdr_5_io_scan_mode; // @[lib.scala 368:23] - wire rvclkhdr_6_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_6_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_6_io_en; // @[lib.scala 343:22] - wire rvclkhdr_6_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_7_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_7_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_7_io_en; // @[lib.scala 343:22] - wire rvclkhdr_7_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_8_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_8_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_8_io_en; // @[lib.scala 343:22] - wire rvclkhdr_8_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_9_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_9_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_9_io_en; // @[lib.scala 343:22] - wire rvclkhdr_9_io_scan_mode; // @[lib.scala 343:22] - wire ahbm_clk = rvclkhdr_7_io_l1clk; // @[axi4_to_ahb.scala 24:22 axi4_to_ahb.scala 333:12] - reg [2:0] buf_state; // @[axi4_to_ahb.scala 30:45] - wire _T_49 = 3'h0 == buf_state; // @[Conditional.scala 37:30] - wire bus_clk = rvclkhdr_io_l1clk; // @[axi4_to_ahb.scala 50:21 axi4_to_ahb.scala 162:11] - reg wrbuf_vld; // @[axi4_to_ahb.scala 301:51] - reg wrbuf_data_vld; // @[axi4_to_ahb.scala 302:51] - wire wr_cmd_vld = wrbuf_vld & wrbuf_data_vld; // @[axi4_to_ahb.scala 139:27] - wire master_valid = wr_cmd_vld | io_axi_ar_valid; // @[axi4_to_ahb.scala 140:30] - wire _T_101 = 3'h1 == buf_state; // @[Conditional.scala 37:30] - reg ahb_hready_q; // @[axi4_to_ahb.scala 321:52] - reg [1:0] ahb_htrans_q; // @[axi4_to_ahb.scala 322:52] - wire _T_108 = ahb_htrans_q != 2'h0; // @[axi4_to_ahb.scala 183:58] - wire _T_109 = ahb_hready_q & _T_108; // @[axi4_to_ahb.scala 183:36] - wire ahbm_addr_clk = rvclkhdr_8_io_l1clk; // @[axi4_to_ahb.scala 25:27 axi4_to_ahb.scala 334:17] - reg ahb_hwrite_q; // @[axi4_to_ahb.scala 323:57] - wire _T_110 = ~ahb_hwrite_q; // @[axi4_to_ahb.scala 183:72] - wire _T_111 = _T_109 & _T_110; // @[axi4_to_ahb.scala 183:70] - wire _T_136 = 3'h6 == buf_state; // @[Conditional.scala 37:30] - reg ahb_hresp_q; // @[axi4_to_ahb.scala 324:52] - wire _T_156 = ahb_hready_q | ahb_hresp_q; // @[axi4_to_ahb.scala 197:37] - wire _T_175 = 3'h7 == buf_state; // @[Conditional.scala 37:30] - wire _T_186 = 3'h3 == buf_state; // @[Conditional.scala 37:30] - wire _T_188 = 3'h2 == buf_state; // @[Conditional.scala 37:30] - wire _T_189 = ahb_hready_q & ahb_hwrite_q; // @[axi4_to_ahb.scala 229:33] - wire _T_192 = _T_189 & _T_108; // @[axi4_to_ahb.scala 229:48] - wire _T_281 = 3'h4 == buf_state; // @[Conditional.scala 37:30] - wire _GEN_15 = _T_281 & _T_192; // @[Conditional.scala 39:67] - wire _GEN_19 = _T_188 ? _T_192 : _GEN_15; // @[Conditional.scala 39:67] - wire _GEN_40 = _T_186 ? 1'h0 : _GEN_19; // @[Conditional.scala 39:67] - wire _GEN_59 = _T_175 ? 1'h0 : _GEN_40; // @[Conditional.scala 39:67] - wire _GEN_79 = _T_136 ? 1'h0 : _GEN_59; // @[Conditional.scala 39:67] - wire _GEN_95 = _T_101 ? 1'h0 : _GEN_79; // @[Conditional.scala 39:67] - wire trxn_done = _T_49 ? 1'h0 : _GEN_95; // @[Conditional.scala 40:58] - reg cmd_doneQ; // @[axi4_to_ahb.scala 319:52] - wire _T_282 = cmd_doneQ & ahb_hready_q; // @[axi4_to_ahb.scala 239:34] - wire _T_283 = _T_282 | ahb_hresp_q; // @[axi4_to_ahb.scala 239:50] - wire _T_440 = 3'h5 == buf_state; // @[Conditional.scala 37:30] - wire slave_ready = io_axi_b_ready & io_axi_r_ready; // @[axi4_to_ahb.scala 157:33] - wire _GEN_1 = _T_440 & slave_ready; // @[Conditional.scala 39:67] - wire _GEN_3 = _T_281 ? _T_283 : _GEN_1; // @[Conditional.scala 39:67] - wire _GEN_20 = _T_188 ? trxn_done : _GEN_3; // @[Conditional.scala 39:67] - wire _GEN_35 = _T_186 ? _T_156 : _GEN_20; // @[Conditional.scala 39:67] - wire _GEN_51 = _T_175 ? _T_111 : _GEN_35; // @[Conditional.scala 39:67] - wire _GEN_69 = _T_136 ? _T_156 : _GEN_51; // @[Conditional.scala 39:67] - wire _GEN_83 = _T_101 ? _T_111 : _GEN_69; // @[Conditional.scala 39:67] - wire buf_state_en = _T_49 ? master_valid : _GEN_83; // @[Conditional.scala 40:58] - wire [1:0] _T_14 = wr_cmd_vld ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 142:20] - wire [2:0] master_opc = {{1'd0}, _T_14}; // @[axi4_to_ahb.scala 142:14] - wire _T_51 = master_opc[2:1] == 2'h1; // @[axi4_to_ahb.scala 168:41] - wire _GEN_8 = _T_281 & _T_51; // @[Conditional.scala 39:67] - wire _GEN_29 = _T_188 ? 1'h0 : _GEN_8; // @[Conditional.scala 39:67] - wire _GEN_46 = _T_186 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67] - wire _GEN_63 = _T_175 ? 1'h0 : _GEN_46; // @[Conditional.scala 39:67] - wire _GEN_81 = _T_136 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67] - wire _GEN_97 = _T_101 ? 1'h0 : _GEN_81; // @[Conditional.scala 39:67] - wire buf_write_in = _T_49 ? _T_51 : _GEN_97; // @[Conditional.scala 40:58] - wire [2:0] _T_53 = buf_write_in ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 169:26] - wire _T_103 = master_opc == 3'h0; // @[axi4_to_ahb.scala 182:61] - wire _T_104 = master_valid & _T_103; // @[axi4_to_ahb.scala 182:41] - wire [2:0] _T_106 = _T_104 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 182:26] - wire _T_124 = _T_106 == 3'h6; // @[axi4_to_ahb.scala 186:174] - wire _T_125 = _T_111 & _T_124; // @[axi4_to_ahb.scala 186:88] - wire _T_137 = ~ahb_hresp_q; // @[axi4_to_ahb.scala 194:39] - wire _T_138 = ahb_hready_q & _T_137; // @[axi4_to_ahb.scala 194:37] - wire _T_141 = master_valid & _T_51; // @[axi4_to_ahb.scala 194:70] - wire _T_142 = ~_T_141; // @[axi4_to_ahb.scala 194:55] - wire _T_143 = _T_138 & _T_142; // @[axi4_to_ahb.scala 194:53] - wire _T_285 = buf_state_en & _T_137; // @[axi4_to_ahb.scala 240:36] - wire _T_286 = _T_285 & slave_ready; // @[axi4_to_ahb.scala 240:51] - wire _GEN_4 = _T_281 & _T_286; // @[Conditional.scala 39:67] - wire _GEN_26 = _T_188 ? 1'h0 : _GEN_4; // @[Conditional.scala 39:67] - wire _GEN_45 = _T_186 ? 1'h0 : _GEN_26; // @[Conditional.scala 39:67] - wire _GEN_62 = _T_175 ? 1'h0 : _GEN_45; // @[Conditional.scala 39:67] - wire _GEN_66 = _T_136 ? _T_143 : _GEN_62; // @[Conditional.scala 39:67] - wire _GEN_86 = _T_101 ? _T_125 : _GEN_66; // @[Conditional.scala 39:67] - wire master_ready = _T_49 | _GEN_86; // @[Conditional.scala 40:58] - wire _T_149 = master_valid & master_ready; // @[axi4_to_ahb.scala 196:82] - wire _T_152 = _T_149 & _T_103; // @[axi4_to_ahb.scala 196:97] - wire [2:0] _T_154 = _T_152 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 196:67] - wire [2:0] _T_155 = ahb_hresp_q ? 3'h7 : _T_154; // @[axi4_to_ahb.scala 196:26] - wire _T_287 = ~slave_ready; // @[axi4_to_ahb.scala 241:42] - wire _T_288 = ahb_hresp_q | _T_287; // @[axi4_to_ahb.scala 241:40] - wire [2:0] _T_293 = _T_51 ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 241:99] - wire [2:0] _T_294 = master_valid ? _T_293 : 3'h0; // @[axi4_to_ahb.scala 241:65] - wire [2:0] _T_295 = _T_288 ? 3'h5 : _T_294; // @[axi4_to_ahb.scala 241:26] - wire [2:0] _GEN_5 = _T_281 ? _T_295 : 3'h0; // @[Conditional.scala 39:67] - wire [2:0] _GEN_18 = _T_188 ? 3'h4 : _GEN_5; // @[Conditional.scala 39:67] - wire [2:0] _GEN_34 = _T_186 ? 3'h5 : _GEN_18; // @[Conditional.scala 39:67] - wire [2:0] _GEN_50 = _T_175 ? 3'h3 : _GEN_34; // @[Conditional.scala 39:67] - wire [2:0] _GEN_68 = _T_136 ? _T_155 : _GEN_50; // @[Conditional.scala 39:67] - wire [2:0] _GEN_82 = _T_101 ? _T_106 : _GEN_68; // @[Conditional.scala 39:67] - wire [2:0] buf_nxtstate = _T_49 ? _T_53 : _GEN_82; // @[Conditional.scala 40:58] - reg [2:0] wrbuf_tag; // @[Reg.scala 27:20] - reg [31:0] wrbuf_addr; // @[lib.scala 374:16] - wire [31:0] master_addr = wr_cmd_vld ? wrbuf_addr : io_axi_ar_bits_addr; // @[axi4_to_ahb.scala 143:21] - reg [2:0] wrbuf_size; // @[Reg.scala 27:20] - wire [2:0] master_size = wr_cmd_vld ? wrbuf_size : io_axi_ar_bits_size; // @[axi4_to_ahb.scala 144:21] - reg [7:0] wrbuf_byteen; // @[Reg.scala 27:20] - reg [63:0] wrbuf_data; // @[lib.scala 374:16] - wire _T_358 = buf_nxtstate != 3'h5; // @[axi4_to_ahb.scala 251:55] - wire _T_359 = buf_state_en & _T_358; // @[axi4_to_ahb.scala 251:39] - wire _GEN_14 = _T_281 ? _T_359 : _T_440; // @[Conditional.scala 39:67] - wire _GEN_33 = _T_188 ? 1'h0 : _GEN_14; // @[Conditional.scala 39:67] - wire _GEN_49 = _T_186 ? 1'h0 : _GEN_33; // @[Conditional.scala 39:67] - wire _GEN_52 = _T_175 ? buf_state_en : _GEN_49; // @[Conditional.scala 39:67] - wire _GEN_73 = _T_136 ? _T_285 : _GEN_52; // @[Conditional.scala 39:67] - wire _GEN_94 = _T_101 ? 1'h0 : _GEN_73; // @[Conditional.scala 39:67] - wire slave_valid_pre = _T_49 ? 1'h0 : _GEN_94; // @[Conditional.scala 40:58] - wire _T_25 = slave_valid_pre & slave_ready; // @[axi4_to_ahb.scala 149:33] - wire buf_clk = rvclkhdr_6_io_l1clk; // @[axi4_to_ahb.scala 118:21 axi4_to_ahb.scala 332:12] - reg slvbuf_write; // @[Reg.scala 27:20] - wire [1:0] _T_596 = slvbuf_write ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 285:23] - reg slvbuf_error; // @[Reg.scala 27:20] - wire [1:0] _T_598 = slvbuf_error ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_599 = _T_598 & 2'h2; // @[axi4_to_ahb.scala 285:88] - wire [3:0] slave_opc = {_T_596,_T_599}; // @[Cat.scala 29:58] - wire [1:0] _T_30 = slave_opc[1] ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 150:55] - reg [2:0] slvbuf_tag; // @[Reg.scala 27:20] - wire _T_35 = slave_opc[3:2] == 2'h0; // @[axi4_to_ahb.scala 153:66] - reg [31:0] last_bus_addr; // @[Reg.scala 27:20] - wire [63:0] _T_603 = {last_bus_addr,last_bus_addr}; // @[Cat.scala 29:58] - wire _T_604 = buf_state == 3'h5; // @[axi4_to_ahb.scala 286:91] - reg [63:0] buf_data; // @[lib.scala 374:16] - wire ahbm_data_clk = rvclkhdr_9_io_l1clk; // @[axi4_to_ahb.scala 26:27 axi4_to_ahb.scala 335:17] - reg [63:0] ahb_hrdata_q; // @[axi4_to_ahb.scala 325:57] - wire [63:0] _T_607 = _T_604 ? buf_data : ahb_hrdata_q; // @[axi4_to_ahb.scala 286:79] - wire _T_44 = io_axi_aw_valid & io_axi_aw_ready; // @[axi4_to_ahb.scala 160:57] - wire _T_45 = io_axi_w_valid & io_axi_w_ready; // @[axi4_to_ahb.scala 160:94] - wire _T_46 = _T_44 | _T_45; // @[axi4_to_ahb.scala 160:76] - wire _T_55 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 172:54] - wire _T_56 = buf_state_en & _T_55; // @[axi4_to_ahb.scala 172:38] - wire [2:0] _T_87 = wrbuf_byteen[6] ? 3'h6 : 3'h7; // @[Mux.scala 98:16] - wire [2:0] _T_88 = wrbuf_byteen[5] ? 3'h5 : _T_87; // @[Mux.scala 98:16] - wire [2:0] _T_89 = wrbuf_byteen[4] ? 3'h4 : _T_88; // @[Mux.scala 98:16] - wire [2:0] _T_90 = wrbuf_byteen[3] ? 3'h3 : _T_89; // @[Mux.scala 98:16] - wire [2:0] _T_91 = wrbuf_byteen[2] ? 3'h2 : _T_90; // @[Mux.scala 98:16] - wire [2:0] _T_92 = wrbuf_byteen[1] ? 3'h1 : _T_91; // @[Mux.scala 98:16] - wire [2:0] _T_93 = wrbuf_byteen[0] ? 3'h0 : _T_92; // @[Mux.scala 98:16] - wire [2:0] _T_95 = buf_write_in ? _T_93 : master_addr[2:0]; // @[axi4_to_ahb.scala 175:30] - wire _T_96 = buf_nxtstate == 3'h1; // @[axi4_to_ahb.scala 177:51] - wire _T_126 = master_ready & master_valid; // @[axi4_to_ahb.scala 188:33] - wire _T_162 = buf_nxtstate == 3'h6; // @[axi4_to_ahb.scala 203:64] - wire _T_163 = _T_126 & _T_162; // @[axi4_to_ahb.scala 203:48] - wire _T_164 = _T_163 & buf_state_en; // @[axi4_to_ahb.scala 203:79] - wire _T_349 = buf_state_en & buf_write_in; // @[axi4_to_ahb.scala 249:33] - wire _T_351 = _T_349 & _T_55; // @[axi4_to_ahb.scala 249:48] - wire _GEN_12 = _T_281 & _T_351; // @[Conditional.scala 39:67] - wire _GEN_32 = _T_188 ? 1'h0 : _GEN_12; // @[Conditional.scala 39:67] - wire _GEN_48 = _T_186 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67] - wire _GEN_65 = _T_175 ? 1'h0 : _GEN_48; // @[Conditional.scala 39:67] - wire _GEN_75 = _T_136 ? _T_164 : _GEN_65; // @[Conditional.scala 39:67] - wire _GEN_88 = _T_101 ? _T_126 : _GEN_75; // @[Conditional.scala 39:67] - wire bypass_en = _T_49 ? buf_state_en : _GEN_88; // @[Conditional.scala 40:58] - wire [1:0] _T_99 = bypass_en ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_100 = _T_99 & 2'h2; // @[axi4_to_ahb.scala 178:49] - wire _T_112 = ~master_valid; // @[axi4_to_ahb.scala 184:34] - wire _T_113 = buf_state_en & _T_112; // @[axi4_to_ahb.scala 184:32] - reg [31:0] buf_addr; // @[lib.scala 374:16] - wire [2:0] _T_130 = bypass_en ? master_addr[2:0] : buf_addr[2:0]; // @[axi4_to_ahb.scala 189:30] - wire _T_131 = ~buf_state_en; // @[axi4_to_ahb.scala 190:48] - wire _T_132 = _T_131 | bypass_en; // @[axi4_to_ahb.scala 190:62] - wire [1:0] _T_134 = _T_132 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_135 = 2'h2 & _T_134; // @[axi4_to_ahb.scala 190:36] - wire _T_169 = buf_nxtstate != 3'h6; // @[axi4_to_ahb.scala 205:63] - wire _T_170 = _T_169 & buf_state_en; // @[axi4_to_ahb.scala 205:78] - wire _T_171 = ~_T_170; // @[axi4_to_ahb.scala 205:47] - wire [1:0] _T_173 = _T_171 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_174 = 2'h2 & _T_173; // @[axi4_to_ahb.scala 205:36] - wire [1:0] _T_184 = _T_131 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_185 = 2'h2 & _T_184; // @[axi4_to_ahb.scala 215:41] - reg [2:0] buf_cmd_byte_ptrQ; // @[Reg.scala 27:20] - reg [7:0] buf_byteen; // @[Reg.scala 27:20] - wire [2:0] _T_197 = buf_cmd_byte_ptrQ + 3'h1; // @[axi4_to_ahb.scala 135:52] - wire _T_200 = 3'h0 >= _T_197; // @[axi4_to_ahb.scala 136:62] - wire _T_201 = buf_byteen[0] & _T_200; // @[axi4_to_ahb.scala 136:48] - wire _T_203 = 3'h1 >= _T_197; // @[axi4_to_ahb.scala 136:62] - wire _T_204 = buf_byteen[1] & _T_203; // @[axi4_to_ahb.scala 136:48] - wire _T_206 = 3'h2 >= _T_197; // @[axi4_to_ahb.scala 136:62] - wire _T_207 = buf_byteen[2] & _T_206; // @[axi4_to_ahb.scala 136:48] - wire _T_209 = 3'h3 >= _T_197; // @[axi4_to_ahb.scala 136:62] - wire _T_210 = buf_byteen[3] & _T_209; // @[axi4_to_ahb.scala 136:48] - wire _T_212 = 3'h4 >= _T_197; // @[axi4_to_ahb.scala 136:62] - wire _T_213 = buf_byteen[4] & _T_212; // @[axi4_to_ahb.scala 136:48] - wire _T_215 = 3'h5 >= _T_197; // @[axi4_to_ahb.scala 136:62] - wire _T_216 = buf_byteen[5] & _T_215; // @[axi4_to_ahb.scala 136:48] - wire _T_218 = 3'h6 >= _T_197; // @[axi4_to_ahb.scala 136:62] - wire _T_219 = buf_byteen[6] & _T_218; // @[axi4_to_ahb.scala 136:48] - wire [2:0] _T_224 = _T_219 ? 3'h6 : 3'h7; // @[Mux.scala 98:16] - wire [2:0] _T_225 = _T_216 ? 3'h5 : _T_224; // @[Mux.scala 98:16] - wire [2:0] _T_226 = _T_213 ? 3'h4 : _T_225; // @[Mux.scala 98:16] - wire [2:0] _T_227 = _T_210 ? 3'h3 : _T_226; // @[Mux.scala 98:16] - wire [2:0] _T_228 = _T_207 ? 3'h2 : _T_227; // @[Mux.scala 98:16] - wire [2:0] _T_229 = _T_204 ? 3'h1 : _T_228; // @[Mux.scala 98:16] - wire [2:0] _T_230 = _T_201 ? 3'h0 : _T_229; // @[Mux.scala 98:16] - wire [2:0] _T_231 = trxn_done ? _T_230 : buf_cmd_byte_ptrQ; // @[axi4_to_ahb.scala 233:30] - wire _T_232 = buf_cmd_byte_ptrQ == 3'h7; // @[axi4_to_ahb.scala 234:65] - reg buf_aligned; // @[Reg.scala 27:20] - wire _T_233 = buf_aligned | _T_232; // @[axi4_to_ahb.scala 234:44] - wire [7:0] _T_271 = buf_byteen >> _T_230; // @[axi4_to_ahb.scala 234:92] - wire _T_273 = ~_T_271[0]; // @[axi4_to_ahb.scala 234:163] - wire _T_274 = _T_233 | _T_273; // @[axi4_to_ahb.scala 234:79] - wire _T_275 = trxn_done & _T_274; // @[axi4_to_ahb.scala 234:29] - wire _T_346 = _T_232 | _T_273; // @[axi4_to_ahb.scala 248:38] - wire _T_347 = _T_109 & _T_346; // @[axi4_to_ahb.scala 247:80] - wire _T_348 = ahb_hresp_q | _T_347; // @[axi4_to_ahb.scala 247:34] - wire _GEN_11 = _T_281 & _T_348; // @[Conditional.scala 39:67] - wire _GEN_24 = _T_188 ? _T_275 : _GEN_11; // @[Conditional.scala 39:67] - wire _GEN_43 = _T_186 ? 1'h0 : _GEN_24; // @[Conditional.scala 39:67] - wire _GEN_61 = _T_175 ? 1'h0 : _GEN_43; // @[Conditional.scala 39:67] - wire _GEN_74 = _T_136 ? _T_113 : _GEN_61; // @[Conditional.scala 39:67] - wire _GEN_84 = _T_101 ? _T_113 : _GEN_74; // @[Conditional.scala 39:67] - wire cmd_done = _T_49 ? 1'h0 : _GEN_84; // @[Conditional.scala 40:58] - wire _T_276 = cmd_done | cmd_doneQ; // @[axi4_to_ahb.scala 235:47] - wire _T_277 = ~_T_276; // @[axi4_to_ahb.scala 235:36] - wire [1:0] _T_279 = _T_277 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_280 = _T_279 & 2'h2; // @[axi4_to_ahb.scala 235:61] - wire _T_300 = _T_55 | _T_96; // @[axi4_to_ahb.scala 245:62] - wire _T_301 = buf_state_en & _T_300; // @[axi4_to_ahb.scala 245:33] - wire _T_354 = _T_277 | bypass_en; // @[axi4_to_ahb.scala 250:61] - wire [1:0] _T_356 = _T_354 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_357 = _T_356 & 2'h2; // @[axi4_to_ahb.scala 250:75] - wire _T_364 = trxn_done | bypass_en; // @[axi4_to_ahb.scala 253:40] - wire [2:0] _T_439 = bypass_en ? _T_93 : _T_231; // @[axi4_to_ahb.scala 254:30] - wire _GEN_6 = _T_281 & ahb_hresp_q; // @[Conditional.scala 39:67] - wire _GEN_7 = _T_281 ? buf_state_en : _T_440; // @[Conditional.scala 39:67] - wire _GEN_9 = _T_281 & _T_301; // @[Conditional.scala 39:67] - wire _GEN_30 = _T_188 ? 1'h0 : _GEN_9; // @[Conditional.scala 39:67] - wire _GEN_47 = _T_186 ? 1'h0 : _GEN_30; // @[Conditional.scala 39:67] - wire _GEN_64 = _T_175 ? 1'h0 : _GEN_47; // @[Conditional.scala 39:67] - wire _GEN_67 = _T_136 ? _T_152 : _GEN_64; // @[Conditional.scala 39:67] - wire _GEN_87 = _T_101 ? master_ready : _GEN_67; // @[Conditional.scala 39:67] - wire buf_wr_en = _T_49 ? buf_state_en : _GEN_87; // @[Conditional.scala 40:58] - wire _GEN_10 = _T_281 & buf_wr_en; // @[Conditional.scala 39:67] - wire [1:0] _GEN_13 = _T_281 ? _T_357 : 2'h0; // @[Conditional.scala 39:67] - wire _GEN_16 = _T_281 & _T_364; // @[Conditional.scala 39:67] - wire [2:0] _GEN_17 = _T_281 ? _T_439 : 3'h0; // @[Conditional.scala 39:67] - wire _GEN_21 = _T_188 ? buf_state_en : _GEN_16; // @[Conditional.scala 39:67] - wire _GEN_22 = _T_188 & buf_state_en; // @[Conditional.scala 39:67] - wire [2:0] _GEN_23 = _T_188 ? _T_231 : _GEN_17; // @[Conditional.scala 39:67] - wire [1:0] _GEN_25 = _T_188 ? _T_280 : _GEN_13; // @[Conditional.scala 39:67] - wire _GEN_28 = _T_188 ? 1'h0 : _GEN_7; // @[Conditional.scala 39:67] - wire _GEN_31 = _T_188 ? 1'h0 : _GEN_10; // @[Conditional.scala 39:67] - wire _GEN_36 = _T_186 ? buf_state_en : _GEN_31; // @[Conditional.scala 39:67] - wire _GEN_38 = _T_186 ? buf_state_en : _GEN_28; // @[Conditional.scala 39:67] - wire _GEN_39 = _T_186 ? buf_state_en : _GEN_22; // @[Conditional.scala 39:67] - wire _GEN_41 = _T_186 ? 1'h0 : _GEN_21; // @[Conditional.scala 39:67] - wire [2:0] _GEN_42 = _T_186 ? 3'h0 : _GEN_23; // @[Conditional.scala 39:67] - wire [1:0] _GEN_44 = _T_186 ? 2'h0 : _GEN_25; // @[Conditional.scala 39:67] - wire _GEN_53 = _T_175 ? buf_state_en : _GEN_39; // @[Conditional.scala 39:67] - wire [2:0] _GEN_54 = _T_175 ? buf_addr[2:0] : _GEN_42; // @[Conditional.scala 39:67] - wire [1:0] _GEN_55 = _T_175 ? _T_185 : _GEN_44; // @[Conditional.scala 39:67] - wire _GEN_56 = _T_175 ? 1'h0 : _GEN_36; // @[Conditional.scala 39:67] - wire _GEN_58 = _T_175 ? 1'h0 : _GEN_38; // @[Conditional.scala 39:67] - wire _GEN_60 = _T_175 ? 1'h0 : _GEN_41; // @[Conditional.scala 39:67] - wire _GEN_70 = _T_136 ? buf_state_en : _GEN_56; // @[Conditional.scala 39:67] - wire _GEN_72 = _T_136 ? buf_state_en : _GEN_58; // @[Conditional.scala 39:67] - wire [2:0] _GEN_76 = _T_136 ? _T_130 : _GEN_54; // @[Conditional.scala 39:67] - wire [1:0] _GEN_77 = _T_136 ? _T_174 : _GEN_55; // @[Conditional.scala 39:67] - wire _GEN_78 = _T_136 ? buf_wr_en : _GEN_53; // @[Conditional.scala 39:67] - wire _GEN_80 = _T_136 ? 1'h0 : _GEN_60; // @[Conditional.scala 39:67] - wire _GEN_85 = _T_101 ? buf_state_en : _GEN_78; // @[Conditional.scala 39:67] - wire [2:0] _GEN_89 = _T_101 ? _T_130 : _GEN_76; // @[Conditional.scala 39:67] - wire [1:0] _GEN_90 = _T_101 ? _T_135 : _GEN_77; // @[Conditional.scala 39:67] - wire _GEN_91 = _T_101 ? 1'h0 : _GEN_70; // @[Conditional.scala 39:67] - wire _GEN_93 = _T_101 ? 1'h0 : _GEN_72; // @[Conditional.scala 39:67] - wire _GEN_96 = _T_101 ? 1'h0 : _GEN_80; // @[Conditional.scala 39:67] - wire buf_data_wr_en = _T_49 ? _T_56 : _GEN_91; // @[Conditional.scala 40:58] - wire buf_cmd_byte_ptr_en = _T_49 ? buf_state_en : _GEN_96; // @[Conditional.scala 40:58] - wire [2:0] buf_cmd_byte_ptr = _T_49 ? _T_95 : _GEN_89; // @[Conditional.scala 40:58] - wire slvbuf_wr_en = _T_49 ? 1'h0 : _GEN_85; // @[Conditional.scala 40:58] - wire slvbuf_error_en = _T_49 ? 1'h0 : _GEN_93; // @[Conditional.scala 40:58] - wire _T_535 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 271:24] - wire _T_536 = _T_103 | _T_535; // @[axi4_to_ahb.scala 270:48] - wire _T_538 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 271:54] - wire _T_539 = _T_536 | _T_538; // @[axi4_to_ahb.scala 271:33] - wire _T_541 = master_size[1:0] == 2'h2; // @[axi4_to_ahb.scala 271:93] - wire _T_542 = _T_539 | _T_541; // @[axi4_to_ahb.scala 271:72] - wire _T_544 = master_size[1:0] == 2'h3; // @[axi4_to_ahb.scala 272:25] - wire _T_546 = wrbuf_byteen == 8'h3; // @[axi4_to_ahb.scala 272:62] - wire _T_548 = wrbuf_byteen == 8'hc; // @[axi4_to_ahb.scala 272:97] - wire _T_549 = _T_546 | _T_548; // @[axi4_to_ahb.scala 272:74] - wire _T_551 = wrbuf_byteen == 8'h30; // @[axi4_to_ahb.scala 272:132] - wire _T_552 = _T_549 | _T_551; // @[axi4_to_ahb.scala 272:109] - wire _T_554 = wrbuf_byteen == 8'hc0; // @[axi4_to_ahb.scala 272:168] - wire _T_555 = _T_552 | _T_554; // @[axi4_to_ahb.scala 272:145] - wire _T_557 = wrbuf_byteen == 8'hf; // @[axi4_to_ahb.scala 273:28] - wire _T_558 = _T_555 | _T_557; // @[axi4_to_ahb.scala 272:181] - wire _T_560 = wrbuf_byteen == 8'hf0; // @[axi4_to_ahb.scala 273:63] - wire _T_561 = _T_558 | _T_560; // @[axi4_to_ahb.scala 273:40] - wire _T_563 = wrbuf_byteen == 8'hff; // @[axi4_to_ahb.scala 273:99] - wire _T_564 = _T_561 | _T_563; // @[axi4_to_ahb.scala 273:76] - wire _T_565 = _T_544 & _T_564; // @[axi4_to_ahb.scala 272:38] - wire buf_aligned_in = _T_542 | _T_565; // @[axi4_to_ahb.scala 271:106] - wire _T_444 = buf_aligned_in & _T_51; // @[axi4_to_ahb.scala 265:60] - wire [2:0] _T_461 = _T_548 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_462 = 3'h2 & _T_461; // @[axi4_to_ahb.scala 128:15] - wire _T_468 = _T_560 | _T_546; // @[axi4_to_ahb.scala 129:56] - wire [2:0] _T_470 = _T_468 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_471 = 3'h4 & _T_470; // @[axi4_to_ahb.scala 129:15] - wire [2:0] _T_472 = _T_462 | _T_471; // @[axi4_to_ahb.scala 128:63] - wire [2:0] _T_476 = _T_554 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_477 = 3'h6 & _T_476; // @[axi4_to_ahb.scala 130:15] - wire [2:0] _T_478 = _T_472 | _T_477; // @[axi4_to_ahb.scala 129:96] - wire [2:0] _T_485 = _T_444 ? _T_478 : master_addr[2:0]; // @[axi4_to_ahb.scala 265:43] - wire _T_489 = buf_state == 3'h3; // @[axi4_to_ahb.scala 268:33] - wire _T_495 = buf_aligned_in & _T_544; // @[axi4_to_ahb.scala 269:38] - wire _T_498 = _T_495 & _T_51; // @[axi4_to_ahb.scala 269:71] - wire [1:0] _T_504 = _T_563 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire _T_510 = _T_560 | _T_557; // @[axi4_to_ahb.scala 122:55] - wire [1:0] _T_512 = _T_510 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_513 = 2'h2 & _T_512; // @[axi4_to_ahb.scala 122:16] - wire [1:0] _T_514 = _T_504 | _T_513; // @[axi4_to_ahb.scala 121:64] - wire _T_519 = _T_554 | _T_551; // @[axi4_to_ahb.scala 123:60] - wire _T_522 = _T_519 | _T_548; // @[axi4_to_ahb.scala 123:89] - wire _T_525 = _T_522 | _T_546; // @[axi4_to_ahb.scala 123:123] - wire [1:0] _T_527 = _T_525 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_528 = 2'h1 & _T_527; // @[axi4_to_ahb.scala 123:21] - wire [1:0] _T_529 = _T_514 | _T_528; // @[axi4_to_ahb.scala 122:93] - wire [1:0] _T_531 = _T_498 ? _T_529 : master_size[1:0]; // @[axi4_to_ahb.scala 269:21] - wire [31:0] _T_570 = {master_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] - wire [31:0] _T_573 = {buf_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] - wire [1:0] _T_577 = buf_aligned_in ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [2:0] buf_size_in = {{1'd0}, _T_531}; // @[axi4_to_ahb.scala 269:15] - wire [1:0] _T_579 = _T_577 & buf_size_in[1:0]; // @[axi4_to_ahb.scala 276:81] - wire [2:0] _T_580 = {1'h0,_T_579}; // @[Cat.scala 29:58] - wire [1:0] _T_582 = buf_aligned ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - reg [1:0] buf_size; // @[Reg.scala 27:20] - wire [1:0] _T_584 = _T_582 & buf_size; // @[axi4_to_ahb.scala 276:138] - wire [2:0] _T_585 = {1'h0,_T_584}; // @[Cat.scala 29:58] - wire _T_588 = ~io_axi_ar_bits_prot[2]; // @[axi4_to_ahb.scala 280:37] - wire [1:0] _T_589 = {1'h1,_T_588}; // @[Cat.scala 29:58] - reg buf_write; // @[Reg.scala 27:20] - wire _T_611 = io_ahb_out_htrans != 2'h0; // @[axi4_to_ahb.scala 289:44] - wire _T_612 = _T_611 & io_ahb_in_hready; // @[axi4_to_ahb.scala 289:56] - wire last_addr_en = _T_612 & io_ahb_out_hwrite; // @[axi4_to_ahb.scala 289:75] - wire wrbuf_en = _T_44 & master_ready; // @[axi4_to_ahb.scala 291:49] - wire wrbuf_data_en = _T_45 & master_ready; // @[axi4_to_ahb.scala 292:52] - wire wrbuf_cmd_sent = _T_149 & _T_51; // @[axi4_to_ahb.scala 293:49] - wire _T_622 = ~wrbuf_en; // @[axi4_to_ahb.scala 294:33] - wire wrbuf_rst = wrbuf_cmd_sent & _T_622; // @[axi4_to_ahb.scala 294:31] - wire _T_624 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 296:36] - wire _T_625 = wrbuf_vld & _T_624; // @[axi4_to_ahb.scala 296:34] - wire _T_626 = ~_T_625; // @[axi4_to_ahb.scala 296:22] - wire _T_629 = wrbuf_data_vld & _T_624; // @[axi4_to_ahb.scala 297:38] - wire _T_630 = ~_T_629; // @[axi4_to_ahb.scala 297:21] - wire _T_633 = ~wr_cmd_vld; // @[axi4_to_ahb.scala 298:22] - wire _T_636 = wrbuf_en | wrbuf_vld; // @[axi4_to_ahb.scala 301:55] - wire _T_637 = ~wrbuf_rst; // @[axi4_to_ahb.scala 301:91] - wire _T_641 = wrbuf_data_en | wrbuf_data_vld; // @[axi4_to_ahb.scala 302:55] - reg [2:0] buf_tag; // @[Reg.scala 27:20] - wire _T_691 = ~slave_valid_pre; // @[axi4_to_ahb.scala 319:92] - wire _T_704 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 327:43] - wire _T_705 = _T_704 | io_clk_override; // @[axi4_to_ahb.scala 327:58] - wire _T_708 = io_ahb_in_hready & io_ahb_out_htrans[1]; // @[axi4_to_ahb.scala 328:57] - wire _T_709 = _T_708 | io_clk_override; // @[axi4_to_ahb.scala 328:81] - wire _T_711 = buf_state != 3'h0; // @[axi4_to_ahb.scala 329:50] - wire _T_712 = _T_711 | io_clk_override; // @[axi4_to_ahb.scala 329:60] - rvclkhdr rvclkhdr ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_io_l1clk), - .io_clk(rvclkhdr_io_clk), - .io_en(rvclkhdr_io_en), - .io_scan_mode(rvclkhdr_io_scan_mode) - ); - rvclkhdr rvclkhdr_1 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_1_io_l1clk), - .io_clk(rvclkhdr_1_io_clk), - .io_en(rvclkhdr_1_io_en), - .io_scan_mode(rvclkhdr_1_io_scan_mode) - ); - rvclkhdr rvclkhdr_2 ( // @[lib.scala 368:23] - .io_l1clk(rvclkhdr_2_io_l1clk), - .io_clk(rvclkhdr_2_io_clk), - .io_en(rvclkhdr_2_io_en), - .io_scan_mode(rvclkhdr_2_io_scan_mode) - ); - rvclkhdr rvclkhdr_3 ( // @[lib.scala 368:23] - .io_l1clk(rvclkhdr_3_io_l1clk), - .io_clk(rvclkhdr_3_io_clk), - .io_en(rvclkhdr_3_io_en), - .io_scan_mode(rvclkhdr_3_io_scan_mode) - ); - rvclkhdr rvclkhdr_4 ( // @[lib.scala 368:23] - .io_l1clk(rvclkhdr_4_io_l1clk), - .io_clk(rvclkhdr_4_io_clk), - .io_en(rvclkhdr_4_io_en), - .io_scan_mode(rvclkhdr_4_io_scan_mode) - ); - rvclkhdr rvclkhdr_5 ( // @[lib.scala 368:23] - .io_l1clk(rvclkhdr_5_io_l1clk), - .io_clk(rvclkhdr_5_io_clk), - .io_en(rvclkhdr_5_io_en), - .io_scan_mode(rvclkhdr_5_io_scan_mode) - ); - rvclkhdr rvclkhdr_6 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_6_io_l1clk), - .io_clk(rvclkhdr_6_io_clk), - .io_en(rvclkhdr_6_io_en), - .io_scan_mode(rvclkhdr_6_io_scan_mode) - ); - rvclkhdr rvclkhdr_7 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_7_io_l1clk), - .io_clk(rvclkhdr_7_io_clk), - .io_en(rvclkhdr_7_io_en), - .io_scan_mode(rvclkhdr_7_io_scan_mode) - ); - rvclkhdr rvclkhdr_8 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_8_io_l1clk), - .io_clk(rvclkhdr_8_io_clk), - .io_en(rvclkhdr_8_io_en), - .io_scan_mode(rvclkhdr_8_io_scan_mode) - ); - rvclkhdr rvclkhdr_9 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_9_io_l1clk), - .io_clk(rvclkhdr_9_io_clk), - .io_en(rvclkhdr_9_io_en), - .io_scan_mode(rvclkhdr_9_io_scan_mode) - ); - assign io_axi_aw_ready = _T_626 & master_ready; // @[axi4_to_ahb.scala 296:19] - assign io_axi_w_ready = _T_630 & master_ready; // @[axi4_to_ahb.scala 297:18] - assign io_axi_b_valid = _T_25 & slave_opc[3]; // @[axi4_to_ahb.scala 149:18] - assign io_axi_b_bits_resp = slave_opc[0] ? 2'h2 : _T_30; // @[axi4_to_ahb.scala 150:22] - assign io_axi_b_bits_id = slvbuf_tag; // @[axi4_to_ahb.scala 151:20] - assign io_axi_ar_ready = _T_633 & master_ready; // @[axi4_to_ahb.scala 298:19] - assign io_axi_r_valid = _T_25 & _T_35; // @[axi4_to_ahb.scala 153:18] - assign io_axi_r_bits_id = slvbuf_tag; // @[axi4_to_ahb.scala 155:20] - assign io_axi_r_bits_data = slvbuf_error ? _T_603 : _T_607; // @[axi4_to_ahb.scala 156:22] - assign io_axi_r_bits_resp = slave_opc[0] ? 2'h2 : _T_30; // @[axi4_to_ahb.scala 154:22] - assign io_axi_r_bits_last = 1'h1; // @[axi4_to_ahb.scala 299:22] - assign io_ahb_out_haddr = bypass_en ? _T_570 : _T_573; // @[axi4_to_ahb.scala 275:20] - assign io_ahb_out_hburst = 3'h0; // @[axi4_to_ahb.scala 278:21] - assign io_ahb_out_hmastlock = 1'h0; // @[axi4_to_ahb.scala 279:24] - assign io_ahb_out_hprot = {{2'd0}, _T_589}; // @[axi4_to_ahb.scala 280:20] - assign io_ahb_out_hsize = bypass_en ? _T_580 : _T_585; // @[axi4_to_ahb.scala 276:20] - assign io_ahb_out_htrans = _T_49 ? _T_100 : _GEN_90; // @[axi4_to_ahb.scala 22:21 axi4_to_ahb.scala 178:25 axi4_to_ahb.scala 190:25 axi4_to_ahb.scala 205:25 axi4_to_ahb.scala 215:25 axi4_to_ahb.scala 235:25 axi4_to_ahb.scala 250:25] - assign io_ahb_out_hwrite = bypass_en ? _T_51 : buf_write; // @[axi4_to_ahb.scala 281:21] - assign io_ahb_out_hwdata = buf_data; // @[axi4_to_ahb.scala 282:21] - assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_io_en = io_bus_clk_en; // @[lib.scala 345:16] - assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_1_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_1_io_en = io_bus_clk_en & _T_46; // @[lib.scala 345:16] - assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_2_io_clk = rvclkhdr_io_l1clk; // @[lib.scala 370:18] - assign rvclkhdr_2_io_en = _T_44 & master_ready; // @[lib.scala 371:17] - assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] - assign rvclkhdr_3_io_clk = rvclkhdr_io_l1clk; // @[lib.scala 370:18] - assign rvclkhdr_3_io_en = _T_45 & master_ready; // @[lib.scala 371:17] - assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] - assign rvclkhdr_4_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_4_io_en = buf_wr_en & io_bus_clk_en; // @[lib.scala 371:17] - assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] - assign rvclkhdr_5_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_5_io_en = buf_data_wr_en & io_bus_clk_en; // @[lib.scala 371:17] - assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] - assign rvclkhdr_6_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_6_io_en = io_bus_clk_en & _T_705; // @[lib.scala 345:16] - assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_7_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_7_io_en = io_bus_clk_en; // @[lib.scala 345:16] - assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_8_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_8_io_en = io_bus_clk_en & _T_709; // @[lib.scala 345:16] - assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_9_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_9_io_en = io_bus_clk_en & _T_712; // @[lib.scala 345:16] - assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] -`ifdef RANDOMIZE_GARBAGE_ASSIGN -`define RANDOMIZE -`endif -`ifdef RANDOMIZE_INVALID_ASSIGN -`define RANDOMIZE -`endif -`ifdef RANDOMIZE_REG_INIT -`define RANDOMIZE -`endif -`ifdef RANDOMIZE_MEM_INIT -`define RANDOMIZE -`endif -`ifndef RANDOM -`define RANDOM $random -`endif -`ifdef RANDOMIZE_MEM_INIT - integer initvar; -`endif -`ifndef SYNTHESIS -`ifdef FIRRTL_BEFORE_INITIAL -`FIRRTL_BEFORE_INITIAL -`endif -initial begin - `ifdef RANDOMIZE - `ifdef INIT_RANDOM - `INIT_RANDOM - `endif - `ifndef VERILATOR - `ifdef RANDOMIZE_DELAY - #`RANDOMIZE_DELAY begin end - `else - #0.002 begin end - `endif - `endif -`ifdef RANDOMIZE_REG_INIT - _RAND_0 = {1{`RANDOM}}; - buf_state = _RAND_0[2:0]; - _RAND_1 = {1{`RANDOM}}; - wrbuf_vld = _RAND_1[0:0]; - _RAND_2 = {1{`RANDOM}}; - wrbuf_data_vld = _RAND_2[0:0]; - _RAND_3 = {1{`RANDOM}}; - ahb_hready_q = _RAND_3[0:0]; - _RAND_4 = {1{`RANDOM}}; - ahb_htrans_q = _RAND_4[1:0]; - _RAND_5 = {1{`RANDOM}}; - ahb_hwrite_q = _RAND_5[0:0]; - _RAND_6 = {1{`RANDOM}}; - ahb_hresp_q = _RAND_6[0:0]; - _RAND_7 = {1{`RANDOM}}; - cmd_doneQ = _RAND_7[0:0]; - _RAND_8 = {1{`RANDOM}}; - wrbuf_tag = _RAND_8[2:0]; - _RAND_9 = {1{`RANDOM}}; - wrbuf_addr = _RAND_9[31:0]; - _RAND_10 = {1{`RANDOM}}; - wrbuf_size = _RAND_10[2:0]; - _RAND_11 = {1{`RANDOM}}; - wrbuf_byteen = _RAND_11[7:0]; - _RAND_12 = {2{`RANDOM}}; - wrbuf_data = _RAND_12[63:0]; - _RAND_13 = {1{`RANDOM}}; - slvbuf_write = _RAND_13[0:0]; - _RAND_14 = {1{`RANDOM}}; - slvbuf_error = _RAND_14[0:0]; - _RAND_15 = {1{`RANDOM}}; - slvbuf_tag = _RAND_15[2:0]; - _RAND_16 = {1{`RANDOM}}; - last_bus_addr = _RAND_16[31:0]; - _RAND_17 = {2{`RANDOM}}; - buf_data = _RAND_17[63:0]; - _RAND_18 = {2{`RANDOM}}; - ahb_hrdata_q = _RAND_18[63:0]; - _RAND_19 = {1{`RANDOM}}; - buf_addr = _RAND_19[31:0]; - _RAND_20 = {1{`RANDOM}}; - buf_cmd_byte_ptrQ = _RAND_20[2:0]; - _RAND_21 = {1{`RANDOM}}; - buf_byteen = _RAND_21[7:0]; - _RAND_22 = {1{`RANDOM}}; - buf_aligned = _RAND_22[0:0]; - _RAND_23 = {1{`RANDOM}}; - buf_size = _RAND_23[1:0]; - _RAND_24 = {1{`RANDOM}}; - buf_write = _RAND_24[0:0]; - _RAND_25 = {1{`RANDOM}}; - buf_tag = _RAND_25[2:0]; -`endif // RANDOMIZE_REG_INIT - if (reset) begin - buf_state = 3'h0; - end - if (reset) begin - wrbuf_vld = 1'h0; - end - if (reset) begin - wrbuf_data_vld = 1'h0; - end - if (reset) begin - ahb_hready_q = 1'h0; - end - if (reset) begin - ahb_htrans_q = 2'h0; - end - if (reset) begin - ahb_hwrite_q = 1'h0; - end - if (reset) begin - ahb_hresp_q = 1'h0; - end - if (reset) begin - cmd_doneQ = 1'h0; - end - if (reset) begin - wrbuf_tag = 3'h0; - end - if (reset) begin - wrbuf_addr = 32'h0; - end - if (reset) begin - wrbuf_size = 3'h0; - end - if (reset) begin - wrbuf_byteen = 8'h0; - end - if (reset) begin - wrbuf_data = 64'h0; - end - if (reset) begin - slvbuf_write = 1'h0; - end - if (reset) begin - slvbuf_error = 1'h0; - end - if (reset) begin - slvbuf_tag = 3'h0; - end - if (reset) begin - last_bus_addr = 32'h0; - end - if (reset) begin - buf_data = 64'h0; - end - if (reset) begin - ahb_hrdata_q = 64'h0; - end - if (reset) begin - buf_addr = 32'h0; - end - if (reset) begin - buf_cmd_byte_ptrQ = 3'h0; - end - if (reset) begin - buf_byteen = 8'h0; - end - if (reset) begin - buf_aligned = 1'h0; - end - if (reset) begin - buf_size = 2'h0; - end - if (reset) begin - buf_write = 1'h0; - end - if (reset) begin - buf_tag = 3'h0; - end - `endif // RANDOMIZE -end // initial -`ifdef FIRRTL_AFTER_INITIAL -`FIRRTL_AFTER_INITIAL -`endif -`endif // SYNTHESIS - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - buf_state <= 3'h0; - end else if (buf_state_en) begin - if (_T_49) begin - if (buf_write_in) begin - buf_state <= 3'h2; - end else begin - buf_state <= 3'h1; - end - end else if (_T_101) begin - if (_T_104) begin - buf_state <= 3'h6; - end else begin - buf_state <= 3'h3; - end - end else if (_T_136) begin - if (ahb_hresp_q) begin - buf_state <= 3'h7; - end else if (_T_152) begin - buf_state <= 3'h6; - end else begin - buf_state <= 3'h3; - end - end else if (_T_175) begin - buf_state <= 3'h3; - end else if (_T_186) begin - buf_state <= 3'h5; - end else if (_T_188) begin - buf_state <= 3'h4; - end else if (_T_281) begin - if (_T_288) begin - buf_state <= 3'h5; - end else if (master_valid) begin - if (_T_51) begin - buf_state <= 3'h2; - end else begin - buf_state <= 3'h1; - end - end else begin - buf_state <= 3'h0; - end - end else begin - buf_state <= 3'h0; - end - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - wrbuf_vld <= 1'h0; - end else begin - wrbuf_vld <= _T_636 & _T_637; - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - wrbuf_data_vld <= 1'h0; - end else begin - wrbuf_data_vld <= _T_641 & _T_637; - end - end - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - ahb_hready_q <= 1'h0; - end else begin - ahb_hready_q <= io_ahb_in_hready; - end - end - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - ahb_htrans_q <= 2'h0; - end else begin - ahb_htrans_q <= io_ahb_out_htrans; - end - end - always @(posedge ahbm_addr_clk or posedge reset) begin - if (reset) begin - ahb_hwrite_q <= 1'h0; - end else begin - ahb_hwrite_q <= io_ahb_out_hwrite; - end - end - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - ahb_hresp_q <= 1'h0; - end else begin - ahb_hresp_q <= io_ahb_in_hresp; - end - end - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - cmd_doneQ <= 1'h0; - end else begin - cmd_doneQ <= _T_276 & _T_691; - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - wrbuf_tag <= 3'h0; - end else if (wrbuf_en) begin - wrbuf_tag <= io_axi_aw_bits_id; - end - end - always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin - if (reset) begin - wrbuf_addr <= 32'h0; - end else begin - wrbuf_addr <= io_axi_aw_bits_addr; - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - wrbuf_size <= 3'h0; - end else if (wrbuf_en) begin - wrbuf_size <= io_axi_aw_bits_size; - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - wrbuf_byteen <= 8'h0; - end else if (wrbuf_data_en) begin - wrbuf_byteen <= io_axi_w_bits_strb; - end - end - always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin - if (reset) begin - wrbuf_data <= 64'h0; - end else begin - wrbuf_data <= io_axi_w_bits_data; - end - end - always @(posedge buf_clk or posedge reset) begin - if (reset) begin - slvbuf_write <= 1'h0; - end else if (slvbuf_wr_en) begin - slvbuf_write <= buf_write; - end - end - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - slvbuf_error <= 1'h0; - end else if (slvbuf_error_en) begin - if (_T_49) begin - slvbuf_error <= 1'h0; - end else if (_T_101) begin - slvbuf_error <= 1'h0; - end else if (_T_136) begin - slvbuf_error <= ahb_hresp_q; - end else if (_T_175) begin - slvbuf_error <= 1'h0; - end else if (_T_186) begin - slvbuf_error <= ahb_hresp_q; - end else if (_T_188) begin - slvbuf_error <= 1'h0; - end else begin - slvbuf_error <= _GEN_6; - end - end - end - always @(posedge buf_clk or posedge reset) begin - if (reset) begin - slvbuf_tag <= 3'h0; - end else if (slvbuf_wr_en) begin - slvbuf_tag <= buf_tag; - end - end - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - last_bus_addr <= 32'h0; - end else if (last_addr_en) begin - last_bus_addr <= io_ahb_out_haddr; - end - end - always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin - if (reset) begin - buf_data <= 64'h0; - end else if (_T_489) begin - buf_data <= ahb_hrdata_q; - end else begin - buf_data <= wrbuf_data; - end - end - always @(posedge ahbm_data_clk or posedge reset) begin - if (reset) begin - ahb_hrdata_q <= 64'h0; - end else begin - ahb_hrdata_q <= io_ahb_in_hrdata; - end - end - always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin - if (reset) begin - buf_addr <= 32'h0; - end else begin - buf_addr <= {master_addr[31:3],_T_485}; - end - end - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - buf_cmd_byte_ptrQ <= 3'h0; - end else if (buf_cmd_byte_ptr_en) begin - if (_T_49) begin - if (buf_write_in) begin - if (wrbuf_byteen[0]) begin - buf_cmd_byte_ptrQ <= 3'h0; - end else if (wrbuf_byteen[1]) begin - buf_cmd_byte_ptrQ <= 3'h1; - end else if (wrbuf_byteen[2]) begin - buf_cmd_byte_ptrQ <= 3'h2; - end else if (wrbuf_byteen[3]) begin - buf_cmd_byte_ptrQ <= 3'h3; - end else if (wrbuf_byteen[4]) begin - buf_cmd_byte_ptrQ <= 3'h4; - end else if (wrbuf_byteen[5]) begin - buf_cmd_byte_ptrQ <= 3'h5; - end else if (wrbuf_byteen[6]) begin - buf_cmd_byte_ptrQ <= 3'h6; - end else begin - buf_cmd_byte_ptrQ <= 3'h7; - end - end else begin - buf_cmd_byte_ptrQ <= master_addr[2:0]; - end - end else if (_T_101) begin - if (bypass_en) begin - buf_cmd_byte_ptrQ <= master_addr[2:0]; - end else begin - buf_cmd_byte_ptrQ <= buf_addr[2:0]; - end - end else if (_T_136) begin - if (bypass_en) begin - buf_cmd_byte_ptrQ <= master_addr[2:0]; - end else begin - buf_cmd_byte_ptrQ <= buf_addr[2:0]; - end - end else if (_T_175) begin - buf_cmd_byte_ptrQ <= buf_addr[2:0]; - end else if (_T_186) begin - buf_cmd_byte_ptrQ <= 3'h0; - end else if (_T_188) begin - if (trxn_done) begin - if (_T_201) begin - buf_cmd_byte_ptrQ <= 3'h0; - end else if (_T_204) begin - buf_cmd_byte_ptrQ <= 3'h1; - end else if (_T_207) begin - buf_cmd_byte_ptrQ <= 3'h2; - end else if (_T_210) begin - buf_cmd_byte_ptrQ <= 3'h3; - end else if (_T_213) begin - buf_cmd_byte_ptrQ <= 3'h4; - end else if (_T_216) begin - buf_cmd_byte_ptrQ <= 3'h5; - end else if (_T_219) begin - buf_cmd_byte_ptrQ <= 3'h6; - end else begin - buf_cmd_byte_ptrQ <= 3'h7; - end - end - end else if (_T_281) begin - if (bypass_en) begin - if (wrbuf_byteen[0]) begin - buf_cmd_byte_ptrQ <= 3'h0; - end else if (wrbuf_byteen[1]) begin - buf_cmd_byte_ptrQ <= 3'h1; - end else if (wrbuf_byteen[2]) begin - buf_cmd_byte_ptrQ <= 3'h2; - end else if (wrbuf_byteen[3]) begin - buf_cmd_byte_ptrQ <= 3'h3; - end else if (wrbuf_byteen[4]) begin - buf_cmd_byte_ptrQ <= 3'h4; - end else if (wrbuf_byteen[5]) begin - buf_cmd_byte_ptrQ <= 3'h5; - end else if (wrbuf_byteen[6]) begin - buf_cmd_byte_ptrQ <= 3'h6; - end else begin - buf_cmd_byte_ptrQ <= 3'h7; - end - end else if (trxn_done) begin - if (_T_201) begin - buf_cmd_byte_ptrQ <= 3'h0; - end else if (_T_204) begin - buf_cmd_byte_ptrQ <= 3'h1; - end else if (_T_207) begin - buf_cmd_byte_ptrQ <= 3'h2; - end else if (_T_210) begin - buf_cmd_byte_ptrQ <= 3'h3; - end else if (_T_213) begin - buf_cmd_byte_ptrQ <= 3'h4; - end else if (_T_216) begin - buf_cmd_byte_ptrQ <= 3'h5; - end else if (_T_219) begin - buf_cmd_byte_ptrQ <= 3'h6; - end else begin - buf_cmd_byte_ptrQ <= 3'h7; - end - end - end else begin - buf_cmd_byte_ptrQ <= 3'h0; - end - end - end - always @(posedge buf_clk or posedge reset) begin - if (reset) begin - buf_byteen <= 8'h0; - end else if (buf_wr_en) begin - buf_byteen <= wrbuf_byteen; - end - end - always @(posedge buf_clk or posedge reset) begin - if (reset) begin - buf_aligned <= 1'h0; - end else if (buf_wr_en) begin - buf_aligned <= buf_aligned_in; - end - end - always @(posedge buf_clk or posedge reset) begin - if (reset) begin - buf_size <= 2'h0; - end else if (buf_wr_en) begin - buf_size <= buf_size_in[1:0]; - end - end - always @(posedge buf_clk or posedge reset) begin - if (reset) begin - buf_write <= 1'h0; - end else if (buf_wr_en) begin - if (_T_49) begin - buf_write <= _T_51; - end else if (_T_101) begin - buf_write <= 1'h0; - end else if (_T_136) begin - buf_write <= 1'h0; - end else if (_T_175) begin - buf_write <= 1'h0; - end else if (_T_186) begin - buf_write <= 1'h0; - end else if (_T_188) begin - buf_write <= 1'h0; - end else begin - buf_write <= _GEN_8; - end - end - end - always @(posedge buf_clk or posedge reset) begin - if (reset) begin - buf_tag <= 3'h0; - end else if (buf_wr_en) begin - if (wr_cmd_vld) begin - buf_tag <= wrbuf_tag; - end else begin - buf_tag <= io_axi_ar_bits_id; - end - end - end -endmodule diff --git a/dbg.anno.json b/dbg.anno.json new file mode 100644 index 00000000..25f4fa23 --- /dev/null +++ b/dbg.anno.json @@ -0,0 +1,89 @@ +[ + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dbg|dbg>io_dbg_dma_dbg_ib_dbg_cmd_valid", + "sources":[ + "~dbg|dbg>io_dbg_dec_dbg_ib_dbg_cmd_valid", + "~dbg|dbg>io_dbg_dma_io_dma_dbg_ready" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dbg|dbg>io_dbg_dec_dbg_ib_dbg_cmd_valid", + "sources":[ + "~dbg|dbg>io_dbg_dma_io_dma_dbg_ready" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dbg|dbg>io_dbg_dma_dbg_ib_dbg_cmd_addr", + "sources":[ + "~dbg|dbg>io_dbg_dec_dbg_ib_dbg_cmd_addr" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dbg|dbg>io_dbg_dma_dbg_dctl_dbg_cmd_wrdata", + "sources":[ + "~dbg|dbg>io_dbg_dec_dbg_dctl_dbg_cmd_wrdata" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dbg|dbg>io_dbg_dma_dbg_ib_dbg_cmd_type", + "sources":[ + "~dbg|dbg>io_dbg_dec_dbg_ib_dbg_cmd_type" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dbg|dbg>io_dbg_dma_dbg_ib_dbg_cmd_write", + "sources":[ + "~dbg|dbg>io_dbg_dec_dbg_ib_dbg_cmd_write" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dbg|dbg>io_dbg_resume_req", + "sources":[ + "~dbg|dbg>io_dec_tlu_mpc_halted_only", + "~dbg|dbg>io_dec_tlu_debug_mode", + "~dbg|dbg>io_dbg_dec_dbg_ib_dbg_cmd_valid", + "~dbg|dbg>io_core_dbg_cmd_done", + "~dbg|dbg>io_dmi_reg_wr_en", + "~dbg|dbg>io_dmi_reg_en", + "~dbg|dbg>io_dbg_dma_io_dma_dbg_ready", + "~dbg|dbg>io_dmi_reg_addr", + "~dbg|dbg>reset" + ] + }, + { + "class":"firrtl.EmitCircuitAnnotation", + "emitter":"firrtl.VerilogEmitter" + }, + { + "class":"firrtl.transforms.BlackBoxResourceAnno", + "target":"dbg.gated_latch", + "resourceId":"/vsrc/gated_latch.v" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~dbg|dbg>rst_temp" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~dbg|dbg>dbg_dm_rst_l" + }, + { + "class":"firrtl.options.TargetDirAnnotation", + "directory":"." + }, + { + "class":"firrtl.options.OutputAnnotationFileAnnotation", + "file":"dbg" + }, + { + "class":"firrtl.transforms.BlackBoxTargetDirAnno", + "targetDir":"." + } +] \ No newline at end of file diff --git a/dbg.fir b/dbg.fir new file mode 100644 index 00000000..12311978 --- /dev/null +++ b/dbg.fir @@ -0,0 +1,1280 @@ +;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 +circuit dbg : + extmodule gated_latch : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_1 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_1 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_1 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_2 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_2 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_2 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_3 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_3 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_3 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_4 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_4 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_4 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_5 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_5 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_5 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_6 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_6 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_6 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_7 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_7 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_7 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + module dbg : + input clock : Clock + input reset : AsyncReset + output io : {dbg_cmd_size : UInt<2>, dbg_core_rst_l : UInt<1>, flip core_dbg_rddata : UInt<32>, flip core_dbg_cmd_done : UInt<1>, flip core_dbg_cmd_fail : UInt<1>, dbg_halt_req : UInt<1>, dbg_resume_req : UInt<1>, flip dec_tlu_debug_mode : UInt<1>, flip dec_tlu_dbg_halted : UInt<1>, flip dec_tlu_mpc_halted_only : UInt<1>, flip dec_tlu_resume_ack : UInt<1>, flip dmi_reg_en : UInt<1>, flip dmi_reg_addr : UInt<7>, flip dmi_reg_wr_en : UInt<1>, flip dmi_reg_wdata : UInt<32>, dmi_reg_rdata : UInt<32>, sb_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dbg_dec : {dbg_ib : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<32>}}, flip dbg_dma : {dbg_ib : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<32>}}, flip dbg_dma_io : {flip dbg_dma_bubble : UInt<1>, dma_dbg_ready : UInt<1>}, flip dbg_bus_clk_en : UInt<1>, flip dbg_rst_l : UInt<1>, flip clk_override : UInt<1>, flip scan_mode : UInt<1>} + + wire dbg_state : UInt<3> + dbg_state <= UInt<3>("h00") + wire dbg_state_en : UInt<1> + dbg_state_en <= UInt<1>("h00") + wire sb_state : UInt<4> + sb_state <= UInt<4>("h00") + wire sb_state_en : UInt<1> + sb_state_en <= UInt<1>("h00") + wire dmcontrol_reg : UInt<32> + dmcontrol_reg <= UInt<32>("h00") + wire sbaddress0_reg : UInt<32> + sbaddress0_reg <= UInt<32>("h00") + wire sbcs_sbbusy_wren : UInt<1> + sbcs_sbbusy_wren <= UInt<1>("h00") + wire sbcs_sberror_wren : UInt<1> + sbcs_sberror_wren <= UInt<1>("h00") + wire sb_bus_rdata : UInt<64> + sb_bus_rdata <= UInt<64>("h00") + wire sbaddress0_reg_wren1 : UInt<1> + sbaddress0_reg_wren1 <= UInt<1>("h00") + wire dmstatus_reg : UInt<32> + dmstatus_reg <= UInt<32>("h00") + wire dmstatus_havereset : UInt<1> + dmstatus_havereset <= UInt<1>("h00") + wire dmstatus_resumeack : UInt<1> + dmstatus_resumeack <= UInt<1>("h00") + wire dmstatus_unavail : UInt<1> + dmstatus_unavail <= UInt<1>("h00") + wire dmstatus_running : UInt<1> + dmstatus_running <= UInt<1>("h00") + wire dmstatus_halted : UInt<1> + dmstatus_halted <= UInt<1>("h00") + wire abstractcs_busy_wren : UInt<1> + abstractcs_busy_wren <= UInt<1>("h00") + wire abstractcs_busy_din : UInt<1> + abstractcs_busy_din <= UInt<1>("h00") + wire sb_bus_cmd_read : UInt<1> + sb_bus_cmd_read <= UInt<1>("h00") + wire sb_bus_cmd_write_addr : UInt<1> + sb_bus_cmd_write_addr <= UInt<1>("h00") + wire sb_bus_cmd_write_data : UInt<1> + sb_bus_cmd_write_data <= UInt<1>("h00") + wire sb_bus_rsp_read : UInt<1> + sb_bus_rsp_read <= UInt<1>("h00") + wire sb_bus_rsp_error : UInt<1> + sb_bus_rsp_error <= UInt<1>("h00") + wire sb_bus_rsp_write : UInt<1> + sb_bus_rsp_write <= UInt<1>("h00") + wire sbcs_sbbusy_din : UInt<1> + sbcs_sbbusy_din <= UInt<1>("h00") + wire sbcs_sberror_din : UInt<3> + sbcs_sberror_din <= UInt<3>("h00") + wire data1_reg : UInt<32> + data1_reg <= UInt<32>("h00") + wire sbcs_reg : UInt<32> + sbcs_reg <= UInt<32>("h00") + node _T = neq(dbg_state, UInt<3>("h00")) @[dbg.scala 95:51] + node _T_1 = or(io.dmi_reg_en, _T) @[dbg.scala 95:38] + node _T_2 = or(_T_1, dbg_state_en) @[dbg.scala 95:69] + node _T_3 = or(_T_2, io.dec_tlu_dbg_halted) @[dbg.scala 95:84] + node dbg_free_clken = or(_T_3, io.clk_override) @[dbg.scala 95:108] + node _T_4 = or(io.dmi_reg_en, sb_state_en) @[dbg.scala 96:37] + node _T_5 = neq(sb_state, UInt<4>("h00")) @[dbg.scala 96:63] + node _T_6 = or(_T_4, _T_5) @[dbg.scala 96:51] + node sb_free_clken = or(_T_6, io.clk_override) @[dbg.scala 96:86] + inst rvclkhdr of rvclkhdr @[lib.scala 343:22] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[lib.scala 344:17] + rvclkhdr.io.en <= dbg_free_clken @[lib.scala 345:16] + rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 343:22] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_1.io.en <= sb_free_clken @[lib.scala 345:16] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + node _T_7 = bits(io.dbg_rst_l, 0, 0) @[dbg.scala 100:42] + node _T_8 = bits(dmcontrol_reg, 0, 0) @[dbg.scala 100:61] + node _T_9 = or(_T_8, io.scan_mode) @[dbg.scala 100:65] + node _T_10 = and(_T_7, _T_9) @[dbg.scala 100:45] + node dbg_dm_rst_l = asAsyncReset(_T_10) @[dbg.scala 100:94] + node _T_11 = asUInt(dbg_dm_rst_l) @[dbg.scala 102:38] + node _T_12 = asUInt(reset) @[dbg.scala 102:55] + node _T_13 = and(_T_11, _T_12) @[dbg.scala 102:41] + node rst_temp = asAsyncReset(_T_13) @[dbg.scala 102:71] + node _T_14 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 105:39] + node _T_15 = eq(_T_14, UInt<1>("h00")) @[dbg.scala 105:25] + node _T_16 = bits(_T_15, 0, 0) @[dbg.scala 105:50] + io.dbg_core_rst_l <= _T_16 @[dbg.scala 105:21] + node _T_17 = eq(io.dmi_reg_addr, UInt<6>("h038")) @[dbg.scala 106:36] + node _T_18 = and(_T_17, io.dmi_reg_en) @[dbg.scala 106:49] + node _T_19 = and(_T_18, io.dmi_reg_wr_en) @[dbg.scala 106:65] + node _T_20 = eq(sb_state, UInt<4>("h00")) @[dbg.scala 106:96] + node sbcs_wren = and(_T_19, _T_20) @[dbg.scala 106:84] + node _T_21 = bits(io.dmi_reg_wdata, 22, 22) @[dbg.scala 107:60] + node _T_22 = and(sbcs_wren, _T_21) @[dbg.scala 107:42] + node _T_23 = neq(sb_state, UInt<4>("h00")) @[dbg.scala 107:79] + node _T_24 = and(_T_23, io.dmi_reg_en) @[dbg.scala 107:102] + node _T_25 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[dbg.scala 108:23] + node _T_26 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 108:55] + node _T_27 = or(_T_25, _T_26) @[dbg.scala 108:36] + node _T_28 = eq(io.dmi_reg_addr, UInt<6>("h03d")) @[dbg.scala 108:87] + node _T_29 = or(_T_27, _T_28) @[dbg.scala 108:68] + node _T_30 = and(_T_24, _T_29) @[dbg.scala 107:118] + node sbcs_sbbusyerror_wren = or(_T_22, _T_30) @[dbg.scala 107:66] + node _T_31 = bits(io.dmi_reg_wdata, 22, 22) @[dbg.scala 110:61] + node _T_32 = and(sbcs_wren, _T_31) @[dbg.scala 110:43] + node sbcs_sbbusyerror_din = not(_T_32) @[dbg.scala 110:31] + reg temp_sbcs_22 : UInt, rvclkhdr_1.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] + when sbcs_sbbusyerror_wren : @[Reg.scala 28:19] + temp_sbcs_22 <= sbcs_sbbusyerror_din @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg temp_sbcs_21 : UInt, rvclkhdr_1.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] + when sbcs_sbbusy_wren : @[Reg.scala 28:19] + temp_sbcs_21 <= sbcs_sbbusy_din @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_33 = bits(io.dmi_reg_wdata, 20, 20) @[dbg.scala 120:31] + reg temp_sbcs_20 : UInt, rvclkhdr_1.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] + when sbcs_wren : @[Reg.scala 28:19] + temp_sbcs_20 <= _T_33 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_34 = bits(io.dmi_reg_wdata, 19, 15) @[dbg.scala 124:31] + reg temp_sbcs_19_15 : UInt, rvclkhdr_1.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] + when sbcs_wren : @[Reg.scala 28:19] + temp_sbcs_19_15 <= _T_34 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_35 = bits(sbcs_sberror_din, 2, 0) @[dbg.scala 128:31] + reg temp_sbcs_14_12 : UInt, rvclkhdr_1.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] + when sbcs_sberror_wren : @[Reg.scala 28:19] + temp_sbcs_14_12 <= _T_35 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_36 = cat(UInt<7>("h020"), UInt<5>("h0f")) @[Cat.scala 29:58] + node _T_37 = cat(temp_sbcs_19_15, temp_sbcs_14_12) @[Cat.scala 29:58] + node _T_38 = cat(_T_37, _T_36) @[Cat.scala 29:58] + node _T_39 = cat(temp_sbcs_21, temp_sbcs_20) @[Cat.scala 29:58] + node _T_40 = cat(UInt<3>("h01"), UInt<6>("h00")) @[Cat.scala 29:58] + node _T_41 = cat(_T_40, temp_sbcs_22) @[Cat.scala 29:58] + node _T_42 = cat(_T_41, _T_39) @[Cat.scala 29:58] + node _T_43 = cat(_T_42, _T_38) @[Cat.scala 29:58] + sbcs_reg <= _T_43 @[dbg.scala 130:12] + node _T_44 = bits(sbcs_reg, 19, 17) @[dbg.scala 132:33] + node _T_45 = eq(_T_44, UInt<3>("h01")) @[dbg.scala 132:42] + node _T_46 = bits(sbaddress0_reg, 0, 0) @[dbg.scala 132:77] + node _T_47 = and(_T_45, _T_46) @[dbg.scala 132:61] + node _T_48 = bits(sbcs_reg, 19, 17) @[dbg.scala 133:14] + node _T_49 = eq(_T_48, UInt<3>("h02")) @[dbg.scala 133:23] + node _T_50 = bits(sbaddress0_reg, 1, 0) @[dbg.scala 133:58] + node _T_51 = orr(_T_50) @[dbg.scala 133:65] + node _T_52 = and(_T_49, _T_51) @[dbg.scala 133:42] + node _T_53 = or(_T_47, _T_52) @[dbg.scala 132:81] + node _T_54 = bits(sbcs_reg, 19, 17) @[dbg.scala 134:14] + node _T_55 = eq(_T_54, UInt<3>("h03")) @[dbg.scala 134:23] + node _T_56 = bits(sbaddress0_reg, 2, 0) @[dbg.scala 134:58] + node _T_57 = orr(_T_56) @[dbg.scala 134:65] + node _T_58 = and(_T_55, _T_57) @[dbg.scala 134:42] + node sbcs_unaligned = or(_T_53, _T_58) @[dbg.scala 133:69] + node sbcs_illegal_size = bits(sbcs_reg, 19, 19) @[dbg.scala 136:35] + node _T_59 = bits(sbcs_reg, 19, 17) @[dbg.scala 137:42] + node _T_60 = eq(_T_59, UInt<1>("h00")) @[dbg.scala 137:51] + node _T_61 = bits(_T_60, 0, 0) @[Bitwise.scala 72:15] + node _T_62 = mux(_T_61, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_63 = and(_T_62, UInt<4>("h01")) @[dbg.scala 137:64] + node _T_64 = bits(sbcs_reg, 19, 17) @[dbg.scala 137:100] + node _T_65 = eq(_T_64, UInt<1>("h01")) @[dbg.scala 137:109] + node _T_66 = bits(_T_65, 0, 0) @[Bitwise.scala 72:15] + node _T_67 = mux(_T_66, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_68 = and(_T_67, UInt<4>("h02")) @[dbg.scala 137:122] + node _T_69 = or(_T_63, _T_68) @[dbg.scala 137:81] + node _T_70 = bits(sbcs_reg, 19, 17) @[dbg.scala 138:22] + node _T_71 = eq(_T_70, UInt<2>("h02")) @[dbg.scala 138:31] + node _T_72 = bits(_T_71, 0, 0) @[Bitwise.scala 72:15] + node _T_73 = mux(_T_72, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_74 = and(_T_73, UInt<4>("h04")) @[dbg.scala 138:44] + node _T_75 = or(_T_69, _T_74) @[dbg.scala 137:139] + node _T_76 = bits(sbcs_reg, 19, 17) @[dbg.scala 138:80] + node _T_77 = eq(_T_76, UInt<2>("h03")) @[dbg.scala 138:89] + node _T_78 = bits(_T_77, 0, 0) @[Bitwise.scala 72:15] + node _T_79 = mux(_T_78, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_80 = and(_T_79, UInt<4>("h08")) @[dbg.scala 138:102] + node sbaddress0_incr = or(_T_75, _T_80) @[dbg.scala 138:61] + node _T_81 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 140:41] + node _T_82 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 140:79] + node sbdata0_reg_wren0 = and(_T_81, _T_82) @[dbg.scala 140:60] + node _T_83 = eq(sb_state, UInt<4>("h07")) @[dbg.scala 141:37] + node _T_84 = and(_T_83, sb_state_en) @[dbg.scala 141:60] + node _T_85 = eq(sbcs_sberror_wren, UInt<1>("h00")) @[dbg.scala 141:76] + node sbdata0_reg_wren1 = and(_T_84, _T_85) @[dbg.scala 141:74] + node sbdata0_reg_wren = or(sbdata0_reg_wren0, sbdata0_reg_wren1) @[dbg.scala 142:44] + node _T_86 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 143:41] + node _T_87 = eq(io.dmi_reg_addr, UInt<6>("h03d")) @[dbg.scala 143:79] + node sbdata1_reg_wren0 = and(_T_86, _T_87) @[dbg.scala 143:60] + node _T_88 = eq(sb_state, UInt<4>("h07")) @[dbg.scala 144:37] + node _T_89 = and(_T_88, sb_state_en) @[dbg.scala 144:60] + node _T_90 = eq(sbcs_sberror_wren, UInt<1>("h00")) @[dbg.scala 144:76] + node sbdata1_reg_wren1 = and(_T_89, _T_90) @[dbg.scala 144:74] + node sbdata1_reg_wren = or(sbdata1_reg_wren0, sbdata1_reg_wren1) @[dbg.scala 145:44] + node _T_91 = bits(sbdata0_reg_wren0, 0, 0) @[Bitwise.scala 72:15] + node _T_92 = mux(_T_91, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_93 = and(_T_92, io.dmi_reg_wdata) @[dbg.scala 146:49] + node _T_94 = bits(sbdata0_reg_wren1, 0, 0) @[Bitwise.scala 72:15] + node _T_95 = mux(_T_94, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_96 = bits(sb_bus_rdata, 31, 0) @[dbg.scala 147:47] + node _T_97 = and(_T_95, _T_96) @[dbg.scala 147:33] + node sbdata0_din = or(_T_93, _T_97) @[dbg.scala 146:68] + node _T_98 = bits(sbdata1_reg_wren0, 0, 0) @[Bitwise.scala 72:15] + node _T_99 = mux(_T_98, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_100 = and(_T_99, io.dmi_reg_wdata) @[dbg.scala 149:49] + node _T_101 = bits(sbdata1_reg_wren1, 0, 0) @[Bitwise.scala 72:15] + node _T_102 = mux(_T_101, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_103 = bits(sb_bus_rdata, 63, 32) @[dbg.scala 150:47] + node _T_104 = and(_T_102, _T_103) @[dbg.scala 150:33] + node sbdata1_din = or(_T_100, _T_104) @[dbg.scala 149:68] + inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 368:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= dbg_dm_rst_l + rvclkhdr_2.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_2.io.en <= sbdata0_reg_wren @[lib.scala 371:17] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg sbdata0_reg : UInt, rvclkhdr_2.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[lib.scala 374:16] + sbdata0_reg <= sbdata0_din @[lib.scala 374:16] + inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 368:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= dbg_dm_rst_l + rvclkhdr_3.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_3.io.en <= sbdata1_reg_wren @[lib.scala 371:17] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg sbdata1_reg : UInt, rvclkhdr_3.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[lib.scala 374:16] + sbdata1_reg <= sbdata1_din @[lib.scala 374:16] + node _T_105 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 160:44] + node _T_106 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[dbg.scala 160:82] + node sbaddress0_reg_wren0 = and(_T_105, _T_106) @[dbg.scala 160:63] + node sbaddress0_reg_wren = or(sbaddress0_reg_wren0, sbaddress0_reg_wren1) @[dbg.scala 161:50] + node _T_107 = bits(sbaddress0_reg_wren0, 0, 0) @[Bitwise.scala 72:15] + node _T_108 = mux(_T_107, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_109 = and(_T_108, io.dmi_reg_wdata) @[dbg.scala 162:59] + node _T_110 = bits(sbaddress0_reg_wren1, 0, 0) @[Bitwise.scala 72:15] + node _T_111 = mux(_T_110, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_112 = cat(UInt<28>("h00"), sbaddress0_incr) @[Cat.scala 29:58] + node _T_113 = add(sbaddress0_reg, _T_112) @[dbg.scala 163:54] + node _T_114 = tail(_T_113, 1) @[dbg.scala 163:54] + node _T_115 = and(_T_111, _T_114) @[dbg.scala 163:36] + node sbaddress0_reg_din = or(_T_109, _T_115) @[dbg.scala 162:78] + inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 368:23] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= dbg_dm_rst_l + rvclkhdr_4.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_4.io.en <= sbaddress0_reg_wren @[lib.scala 371:17] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_116 : UInt, rvclkhdr_4.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[lib.scala 374:16] + _T_116 <= sbaddress0_reg_din @[lib.scala 374:16] + sbaddress0_reg <= _T_116 @[dbg.scala 164:18] + node _T_117 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 168:43] + node _T_118 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[dbg.scala 168:81] + node _T_119 = and(_T_117, _T_118) @[dbg.scala 168:62] + node _T_120 = bits(sbcs_reg, 20, 20) @[dbg.scala 168:104] + node sbreadonaddr_access = and(_T_119, _T_120) @[dbg.scala 168:94] + node _T_121 = eq(io.dmi_reg_wr_en, UInt<1>("h00")) @[dbg.scala 169:45] + node _T_122 = and(io.dmi_reg_en, _T_121) @[dbg.scala 169:43] + node _T_123 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 169:82] + node _T_124 = and(_T_122, _T_123) @[dbg.scala 169:63] + node _T_125 = bits(sbcs_reg, 15, 15) @[dbg.scala 169:105] + node sbreadondata_access = and(_T_124, _T_125) @[dbg.scala 169:95] + node _T_126 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 170:40] + node _T_127 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 170:78] + node sbdata0wr_access = and(_T_126, _T_127) @[dbg.scala 170:59] + node _T_128 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[dbg.scala 171:41] + node _T_129 = and(_T_128, io.dmi_reg_en) @[dbg.scala 171:54] + node dmcontrol_wren = and(_T_129, io.dmi_reg_wr_en) @[dbg.scala 171:70] + node _T_130 = bits(io.dmi_reg_wdata, 31, 30) @[dbg.scala 174:27] + node _T_131 = bits(io.dmi_reg_wdata, 28, 28) @[dbg.scala 174:53] + node _T_132 = bits(io.dmi_reg_wdata, 1, 1) @[dbg.scala 174:75] + node _T_133 = cat(_T_130, _T_131) @[Cat.scala 29:58] + node _T_134 = cat(_T_133, _T_132) @[Cat.scala 29:58] + reg dm_temp : UInt, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] + when dmcontrol_wren : @[Reg.scala 28:19] + dm_temp <= _T_134 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_135 = asAsyncReset(io.dbg_rst_l) @[dbg.scala 178:76] + node _T_136 = bits(io.dmi_reg_wdata, 0, 0) @[dbg.scala 179:31] + reg dm_temp_0 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_135, UInt<1>("h00"))) @[Reg.scala 27:20] + when dmcontrol_wren : @[Reg.scala 28:19] + dm_temp_0 <= _T_136 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_137 = bits(dm_temp, 3, 2) @[dbg.scala 182:25] + node _T_138 = bits(dm_temp, 1, 1) @[dbg.scala 182:45] + node _T_139 = bits(dm_temp, 0, 0) @[dbg.scala 182:68] + node _T_140 = cat(UInt<26>("h00"), _T_139) @[Cat.scala 29:58] + node _T_141 = cat(_T_140, dm_temp_0) @[Cat.scala 29:58] + node _T_142 = cat(_T_137, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_143 = cat(_T_142, _T_138) @[Cat.scala 29:58] + node temp = cat(_T_143, _T_141) @[Cat.scala 29:58] + dmcontrol_reg <= temp @[dbg.scala 183:17] + reg dmcontrol_wren_Q : UInt<1>, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[dbg.scala 186:12] + dmcontrol_wren_Q <= dmcontrol_wren @[dbg.scala 186:12] + node _T_144 = bits(dmstatus_havereset, 0, 0) @[Bitwise.scala 72:15] + node _T_145 = mux(_T_144, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_146 = bits(dmstatus_resumeack, 0, 0) @[Bitwise.scala 72:15] + node _T_147 = mux(_T_146, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_148 = bits(dmstatus_unavail, 0, 0) @[Bitwise.scala 72:15] + node _T_149 = mux(_T_148, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_150 = bits(dmstatus_running, 0, 0) @[Bitwise.scala 72:15] + node _T_151 = mux(_T_150, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_152 = bits(dmstatus_halted, 0, 0) @[Bitwise.scala 72:15] + node _T_153 = mux(_T_152, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_154 = cat(UInt<3>("h00"), UInt<4>("h02")) @[Cat.scala 29:58] + node _T_155 = cat(_T_151, _T_153) @[Cat.scala 29:58] + node _T_156 = cat(_T_155, UInt<1>("h01")) @[Cat.scala 29:58] + node _T_157 = cat(_T_156, _T_154) @[Cat.scala 29:58] + node _T_158 = cat(UInt<2>("h00"), _T_149) @[Cat.scala 29:58] + node _T_159 = cat(UInt<12>("h00"), _T_145) @[Cat.scala 29:58] + node _T_160 = cat(_T_159, _T_147) @[Cat.scala 29:58] + node _T_161 = cat(_T_160, _T_158) @[Cat.scala 29:58] + node _T_162 = cat(_T_161, _T_157) @[Cat.scala 29:58] + dmstatus_reg <= _T_162 @[dbg.scala 189:16] + node _T_163 = eq(dbg_state, UInt<3>("h06")) @[dbg.scala 191:44] + node _T_164 = and(_T_163, io.dec_tlu_resume_ack) @[dbg.scala 191:66] + node _T_165 = bits(dmcontrol_reg, 30, 30) @[dbg.scala 191:127] + node _T_166 = eq(_T_165, UInt<1>("h00")) @[dbg.scala 191:113] + node _T_167 = and(dmstatus_resumeack, _T_166) @[dbg.scala 191:111] + node dmstatus_resumeack_wren = or(_T_164, _T_167) @[dbg.scala 191:90] + node _T_168 = eq(dbg_state, UInt<3>("h06")) @[dbg.scala 192:43] + node dmstatus_resumeack_din = and(_T_168, io.dec_tlu_resume_ack) @[dbg.scala 192:65] + node _T_169 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[dbg.scala 193:50] + node _T_170 = bits(io.dmi_reg_wdata, 1, 1) @[dbg.scala 193:81] + node _T_171 = and(_T_169, _T_170) @[dbg.scala 193:63] + node _T_172 = and(_T_171, io.dmi_reg_en) @[dbg.scala 193:85] + node dmstatus_havereset_wren = and(_T_172, io.dmi_reg_wr_en) @[dbg.scala 193:101] + node _T_173 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[dbg.scala 194:49] + node _T_174 = bits(io.dmi_reg_wdata, 28, 28) @[dbg.scala 194:80] + node _T_175 = and(_T_173, _T_174) @[dbg.scala 194:62] + node _T_176 = and(_T_175, io.dmi_reg_en) @[dbg.scala 194:85] + node dmstatus_havereset_rst = and(_T_176, io.dmi_reg_wr_en) @[dbg.scala 194:101] + node temp_rst = asUInt(reset) @[dbg.scala 195:30] + node _T_177 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 196:37] + node _T_178 = eq(temp_rst, UInt<1>("h00")) @[dbg.scala 196:43] + node _T_179 = or(_T_177, _T_178) @[dbg.scala 196:41] + node _T_180 = bits(_T_179, 0, 0) @[dbg.scala 196:62] + dmstatus_unavail <= _T_180 @[dbg.scala 196:20] + node _T_181 = or(dmstatus_unavail, dmstatus_halted) @[dbg.scala 197:42] + node _T_182 = not(_T_181) @[dbg.scala 197:23] + dmstatus_running <= _T_182 @[dbg.scala 197:20] + reg _T_183 : UInt, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] + when dmstatus_resumeack_wren : @[Reg.scala 28:19] + _T_183 <= dmstatus_resumeack_din @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + dmstatus_resumeack <= _T_183 @[dbg.scala 198:22] + node _T_184 = eq(io.dec_tlu_mpc_halted_only, UInt<1>("h00")) @[dbg.scala 203:37] + node _T_185 = and(io.dec_tlu_dbg_halted, _T_184) @[dbg.scala 203:35] + reg _T_186 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[dbg.scala 203:12] + _T_186 <= _T_185 @[dbg.scala 203:12] + dmstatus_halted <= _T_186 @[dbg.scala 202:19] + node _T_187 = mux(dmstatus_havereset_wren, UInt<1>("h01"), dmstatus_havereset) @[dbg.scala 207:16] + node _T_188 = eq(dmstatus_havereset_rst, UInt<1>("h00")) @[dbg.scala 207:72] + node _T_189 = and(_T_187, _T_188) @[dbg.scala 207:70] + reg _T_190 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[dbg.scala 207:12] + _T_190 <= _T_189 @[dbg.scala 207:12] + dmstatus_havereset <= _T_190 @[dbg.scala 206:22] + node haltsum0_reg = cat(UInt<31>("h00"), dmstatus_halted) @[Cat.scala 29:58] + wire abstractcs_reg : UInt<32> + abstractcs_reg <= UInt<32>("h02") + node _T_191 = bits(abstractcs_reg, 12, 12) @[dbg.scala 213:45] + node _T_192 = and(_T_191, io.dmi_reg_en) @[dbg.scala 213:50] + node _T_193 = eq(io.dmi_reg_addr, UInt<5>("h016")) @[dbg.scala 213:106] + node _T_194 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 213:138] + node _T_195 = or(_T_193, _T_194) @[dbg.scala 213:119] + node _T_196 = and(io.dmi_reg_wr_en, _T_195) @[dbg.scala 213:86] + node _T_197 = eq(io.dmi_reg_addr, UInt<3>("h04")) @[dbg.scala 213:171] + node _T_198 = or(_T_196, _T_197) @[dbg.scala 213:152] + node abstractcs_error_sel0 = and(_T_192, _T_198) @[dbg.scala 213:66] + node _T_199 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 214:45] + node _T_200 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 214:83] + node _T_201 = and(_T_199, _T_200) @[dbg.scala 214:64] + node _T_202 = bits(io.dmi_reg_wdata, 31, 24) @[dbg.scala 214:117] + node _T_203 = eq(_T_202, UInt<1>("h00")) @[dbg.scala 214:126] + node _T_204 = bits(io.dmi_reg_wdata, 31, 24) @[dbg.scala 214:154] + node _T_205 = eq(_T_204, UInt<2>("h02")) @[dbg.scala 214:163] + node _T_206 = or(_T_203, _T_205) @[dbg.scala 214:135] + node _T_207 = eq(_T_206, UInt<1>("h00")) @[dbg.scala 214:98] + node abstractcs_error_sel1 = and(_T_201, _T_207) @[dbg.scala 214:96] + node abstractcs_error_sel2 = and(io.core_dbg_cmd_done, io.core_dbg_cmd_fail) @[dbg.scala 215:52] + node _T_208 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 216:45] + node _T_209 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 216:83] + node _T_210 = and(_T_208, _T_209) @[dbg.scala 216:64] + node _T_211 = bits(dmstatus_reg, 9, 9) @[dbg.scala 216:111] + node _T_212 = eq(_T_211, UInt<1>("h00")) @[dbg.scala 216:98] + node abstractcs_error_sel3 = and(_T_210, _T_212) @[dbg.scala 216:96] + node _T_213 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 217:48] + node _T_214 = and(_T_213, io.dmi_reg_en) @[dbg.scala 217:61] + node _T_215 = and(_T_214, io.dmi_reg_wr_en) @[dbg.scala 217:77] + node _T_216 = bits(io.dmi_reg_wdata, 22, 20) @[dbg.scala 218:23] + node _T_217 = neq(_T_216, UInt<3>("h02")) @[dbg.scala 218:32] + node _T_218 = bits(io.dmi_reg_wdata, 31, 24) @[dbg.scala 218:71] + node _T_219 = eq(_T_218, UInt<2>("h02")) @[dbg.scala 218:80] + node _T_220 = bits(data1_reg, 1, 0) @[dbg.scala 218:104] + node _T_221 = orr(_T_220) @[dbg.scala 218:111] + node _T_222 = and(_T_219, _T_221) @[dbg.scala 218:92] + node _T_223 = or(_T_217, _T_222) @[dbg.scala 218:51] + node abstractcs_error_sel4 = and(_T_215, _T_223) @[dbg.scala 217:96] + node _T_224 = eq(io.dmi_reg_addr, UInt<5>("h016")) @[dbg.scala 220:48] + node _T_225 = and(_T_224, io.dmi_reg_en) @[dbg.scala 220:61] + node abstractcs_error_sel5 = and(_T_225, io.dmi_reg_wr_en) @[dbg.scala 220:77] + node _T_226 = or(abstractcs_error_sel0, abstractcs_error_sel1) @[dbg.scala 221:54] + node _T_227 = or(_T_226, abstractcs_error_sel2) @[dbg.scala 221:78] + node _T_228 = or(_T_227, abstractcs_error_sel3) @[dbg.scala 221:102] + node _T_229 = or(_T_228, abstractcs_error_sel4) @[dbg.scala 221:126] + node abstractcs_error_selor = or(_T_229, abstractcs_error_sel5) @[dbg.scala 221:150] + node _T_230 = bits(abstractcs_error_sel0, 0, 0) @[Bitwise.scala 72:15] + node _T_231 = mux(_T_230, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_232 = and(_T_231, UInt<3>("h01")) @[dbg.scala 222:62] + node _T_233 = bits(abstractcs_error_sel1, 0, 0) @[Bitwise.scala 72:15] + node _T_234 = mux(_T_233, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_235 = and(_T_234, UInt<3>("h02")) @[dbg.scala 223:37] + node _T_236 = or(_T_232, _T_235) @[dbg.scala 222:79] + node _T_237 = bits(abstractcs_error_sel2, 0, 0) @[Bitwise.scala 72:15] + node _T_238 = mux(_T_237, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_239 = and(_T_238, UInt<3>("h03")) @[dbg.scala 224:37] + node _T_240 = or(_T_236, _T_239) @[dbg.scala 223:54] + node _T_241 = bits(abstractcs_error_sel3, 0, 0) @[Bitwise.scala 72:15] + node _T_242 = mux(_T_241, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_243 = and(_T_242, UInt<3>("h04")) @[dbg.scala 225:37] + node _T_244 = or(_T_240, _T_243) @[dbg.scala 224:54] + node _T_245 = bits(abstractcs_error_sel4, 0, 0) @[Bitwise.scala 72:15] + node _T_246 = mux(_T_245, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_247 = and(_T_246, UInt<3>("h07")) @[dbg.scala 226:37] + node _T_248 = or(_T_244, _T_247) @[dbg.scala 225:54] + node _T_249 = bits(abstractcs_error_sel5, 0, 0) @[Bitwise.scala 72:15] + node _T_250 = mux(_T_249, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_251 = bits(io.dmi_reg_wdata, 10, 8) @[dbg.scala 227:57] + node _T_252 = not(_T_251) @[dbg.scala 227:40] + node _T_253 = and(_T_250, _T_252) @[dbg.scala 227:37] + node _T_254 = bits(abstractcs_reg, 10, 8) @[dbg.scala 227:91] + node _T_255 = and(_T_253, _T_254) @[dbg.scala 227:75] + node _T_256 = or(_T_248, _T_255) @[dbg.scala 226:54] + node _T_257 = not(abstractcs_error_selor) @[dbg.scala 228:15] + node _T_258 = bits(_T_257, 0, 0) @[Bitwise.scala 72:15] + node _T_259 = mux(_T_258, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_260 = bits(abstractcs_reg, 10, 8) @[dbg.scala 228:66] + node _T_261 = and(_T_259, _T_260) @[dbg.scala 228:50] + node abstractcs_error_din = or(_T_256, _T_261) @[dbg.scala 227:100] + reg abs_temp_12 : UInt, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] + when abstractcs_busy_wren : @[Reg.scala 28:19] + abs_temp_12 <= abstractcs_busy_din @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_262 = bits(abstractcs_error_din, 2, 0) @[dbg.scala 235:33] + reg abs_temp_10_8 : UInt, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[dbg.scala 235:12] + abs_temp_10_8 <= _T_262 @[dbg.scala 235:12] + node _T_263 = cat(abs_temp_10_8, UInt<8>("h02")) @[Cat.scala 29:58] + node _T_264 = cat(UInt<19>("h00"), abs_temp_12) @[Cat.scala 29:58] + node _T_265 = cat(_T_264, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_266 = cat(_T_265, _T_263) @[Cat.scala 29:58] + abstractcs_reg <= _T_266 @[dbg.scala 238:18] + node _T_267 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 240:39] + node _T_268 = and(_T_267, io.dmi_reg_en) @[dbg.scala 240:52] + node _T_269 = and(_T_268, io.dmi_reg_wr_en) @[dbg.scala 240:68] + node _T_270 = eq(dbg_state, UInt<3>("h02")) @[dbg.scala 240:100] + node command_wren = and(_T_269, _T_270) @[dbg.scala 240:87] + node _T_271 = bits(io.dmi_reg_wdata, 31, 24) @[dbg.scala 241:41] + node _T_272 = bits(io.dmi_reg_wdata, 22, 20) @[dbg.scala 241:77] + node _T_273 = bits(io.dmi_reg_wdata, 16, 0) @[dbg.scala 241:113] + node _T_274 = cat(UInt<3>("h00"), _T_273) @[Cat.scala 29:58] + node _T_275 = cat(_T_271, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_276 = cat(_T_275, _T_272) @[Cat.scala 29:58] + node command_din = cat(_T_276, _T_274) @[Cat.scala 29:58] + inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 368:23] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= dbg_dm_rst_l + rvclkhdr_5.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_5.io.en <= command_wren @[lib.scala 371:17] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg command_reg : UInt, rvclkhdr_5.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[lib.scala 374:16] + command_reg <= command_din @[lib.scala 374:16] + node _T_277 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 246:39] + node _T_278 = eq(io.dmi_reg_addr, UInt<3>("h04")) @[dbg.scala 246:77] + node _T_279 = and(_T_277, _T_278) @[dbg.scala 246:58] + node _T_280 = eq(dbg_state, UInt<3>("h02")) @[dbg.scala 246:102] + node data0_reg_wren0 = and(_T_279, _T_280) @[dbg.scala 246:89] + node _T_281 = eq(dbg_state, UInt<3>("h04")) @[dbg.scala 247:59] + node _T_282 = and(io.core_dbg_cmd_done, _T_281) @[dbg.scala 247:46] + node _T_283 = bits(command_reg, 16, 16) @[dbg.scala 247:95] + node _T_284 = eq(_T_283, UInt<1>("h00")) @[dbg.scala 247:83] + node data0_reg_wren1 = and(_T_282, _T_284) @[dbg.scala 247:81] + node data0_reg_wren = or(data0_reg_wren0, data0_reg_wren1) @[dbg.scala 249:40] + node _T_285 = bits(data0_reg_wren0, 0, 0) @[Bitwise.scala 72:15] + node _T_286 = mux(_T_285, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_287 = and(_T_286, io.dmi_reg_wdata) @[dbg.scala 250:45] + node _T_288 = bits(data0_reg_wren1, 0, 0) @[Bitwise.scala 72:15] + node _T_289 = mux(_T_288, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_290 = and(_T_289, io.core_dbg_rddata) @[dbg.scala 250:92] + node data0_din = or(_T_287, _T_290) @[dbg.scala 250:64] + inst rvclkhdr_6 of rvclkhdr_6 @[lib.scala 368:23] + rvclkhdr_6.clock <= clock + rvclkhdr_6.reset <= dbg_dm_rst_l + rvclkhdr_6.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_6.io.en <= data0_reg_wren @[lib.scala 371:17] + rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg data0_reg : UInt, rvclkhdr_6.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[lib.scala 374:16] + data0_reg <= data0_din @[lib.scala 374:16] + node _T_291 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 255:39] + node _T_292 = eq(io.dmi_reg_addr, UInt<3>("h05")) @[dbg.scala 255:77] + node _T_293 = and(_T_291, _T_292) @[dbg.scala 255:58] + node _T_294 = eq(dbg_state, UInt<3>("h02")) @[dbg.scala 255:102] + node data1_reg_wren = and(_T_293, _T_294) @[dbg.scala 255:89] + node _T_295 = bits(data1_reg_wren, 0, 0) @[Bitwise.scala 72:15] + node _T_296 = mux(_T_295, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node data1_din = and(_T_296, io.dmi_reg_wdata) @[dbg.scala 256:44] + inst rvclkhdr_7 of rvclkhdr_7 @[lib.scala 368:23] + rvclkhdr_7.clock <= clock + rvclkhdr_7.reset <= dbg_dm_rst_l + rvclkhdr_7.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_7.io.en <= data1_reg_wren @[lib.scala 371:17] + rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_297 : UInt, rvclkhdr_7.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[lib.scala 374:16] + _T_297 <= data1_din @[lib.scala 374:16] + data1_reg <= _T_297 @[dbg.scala 257:13] + wire dbg_nxtstate : UInt<3> + dbg_nxtstate <= UInt<3>("h00") + dbg_nxtstate <= UInt<3>("h00") @[dbg.scala 262:16] + dbg_state_en <= UInt<1>("h00") @[dbg.scala 263:16] + abstractcs_busy_wren <= UInt<1>("h00") @[dbg.scala 264:24] + abstractcs_busy_din <= UInt<1>("h00") @[dbg.scala 265:23] + io.dbg_halt_req <= UInt<1>("h00") @[dbg.scala 266:19] + io.dbg_resume_req <= UInt<1>("h00") @[dbg.scala 267:21] + node _T_298 = eq(UInt<3>("h00"), dbg_state) @[Conditional.scala 37:30] + when _T_298 : @[Conditional.scala 40:58] + node _T_299 = bits(dmstatus_reg, 9, 9) @[dbg.scala 270:39] + node _T_300 = or(_T_299, io.dec_tlu_mpc_halted_only) @[dbg.scala 270:43] + node _T_301 = mux(_T_300, UInt<3>("h02"), UInt<3>("h01")) @[dbg.scala 270:26] + dbg_nxtstate <= _T_301 @[dbg.scala 270:20] + node _T_302 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 271:38] + node _T_303 = eq(io.dec_tlu_debug_mode, UInt<1>("h00")) @[dbg.scala 271:45] + node _T_304 = and(_T_302, _T_303) @[dbg.scala 271:43] + node _T_305 = bits(dmstatus_reg, 9, 9) @[dbg.scala 271:83] + node _T_306 = or(_T_304, _T_305) @[dbg.scala 271:69] + node _T_307 = or(_T_306, io.dec_tlu_mpc_halted_only) @[dbg.scala 271:87] + node _T_308 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 271:133] + node _T_309 = eq(_T_308, UInt<1>("h00")) @[dbg.scala 271:119] + node _T_310 = and(_T_307, _T_309) @[dbg.scala 271:117] + dbg_state_en <= _T_310 @[dbg.scala 271:20] + node _T_311 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 272:40] + node _T_312 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 272:61] + node _T_313 = eq(_T_312, UInt<1>("h00")) @[dbg.scala 272:47] + node _T_314 = and(_T_311, _T_313) @[dbg.scala 272:45] + node _T_315 = bits(_T_314, 0, 0) @[dbg.scala 272:72] + io.dbg_halt_req <= _T_315 @[dbg.scala 272:23] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_316 = eq(UInt<3>("h01"), dbg_state) @[Conditional.scala 37:30] + when _T_316 : @[Conditional.scala 39:67] + node _T_317 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 275:40] + node _T_318 = mux(_T_317, UInt<3>("h00"), UInt<3>("h02")) @[dbg.scala 275:26] + dbg_nxtstate <= _T_318 @[dbg.scala 275:20] + node _T_319 = bits(dmstatus_reg, 9, 9) @[dbg.scala 276:35] + node _T_320 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 276:54] + node _T_321 = or(_T_319, _T_320) @[dbg.scala 276:39] + dbg_state_en <= _T_321 @[dbg.scala 276:20] + node _T_322 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 277:59] + node _T_323 = and(dmcontrol_wren_Q, _T_322) @[dbg.scala 277:44] + node _T_324 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 277:81] + node _T_325 = not(_T_324) @[dbg.scala 277:67] + node _T_326 = and(_T_323, _T_325) @[dbg.scala 277:64] + node _T_327 = bits(_T_326, 0, 0) @[dbg.scala 277:102] + io.dbg_halt_req <= _T_327 @[dbg.scala 277:23] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_328 = eq(UInt<3>("h02"), dbg_state) @[Conditional.scala 37:30] + when _T_328 : @[Conditional.scala 39:67] + node _T_329 = bits(dmstatus_reg, 9, 9) @[dbg.scala 280:39] + node _T_330 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 280:59] + node _T_331 = eq(_T_330, UInt<1>("h00")) @[dbg.scala 280:45] + node _T_332 = and(_T_329, _T_331) @[dbg.scala 280:43] + node _T_333 = bits(dmcontrol_reg, 30, 30) @[dbg.scala 281:26] + node _T_334 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 281:47] + node _T_335 = eq(_T_334, UInt<1>("h00")) @[dbg.scala 281:33] + node _T_336 = and(_T_333, _T_335) @[dbg.scala 281:31] + node _T_337 = mux(_T_336, UInt<3>("h06"), UInt<3>("h03")) @[dbg.scala 281:12] + node _T_338 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 282:26] + node _T_339 = mux(_T_338, UInt<3>("h01"), UInt<3>("h00")) @[dbg.scala 282:12] + node _T_340 = mux(_T_332, _T_337, _T_339) @[dbg.scala 280:26] + dbg_nxtstate <= _T_340 @[dbg.scala 280:20] + node _T_341 = bits(dmstatus_reg, 9, 9) @[dbg.scala 283:35] + node _T_342 = bits(dmcontrol_reg, 30, 30) @[dbg.scala 283:54] + node _T_343 = and(_T_341, _T_342) @[dbg.scala 283:39] + node _T_344 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 283:75] + node _T_345 = eq(_T_344, UInt<1>("h00")) @[dbg.scala 283:61] + node _T_346 = and(_T_343, _T_345) @[dbg.scala 283:59] + node _T_347 = and(_T_346, dmcontrol_wren_Q) @[dbg.scala 283:80] + node _T_348 = or(_T_347, command_wren) @[dbg.scala 283:99] + node _T_349 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 284:22] + node _T_350 = or(_T_348, _T_349) @[dbg.scala 283:114] + node _T_351 = bits(dmstatus_reg, 9, 9) @[dbg.scala 284:42] + node _T_352 = or(_T_351, io.dec_tlu_mpc_halted_only) @[dbg.scala 284:46] + node _T_353 = eq(_T_352, UInt<1>("h00")) @[dbg.scala 284:28] + node _T_354 = or(_T_350, _T_353) @[dbg.scala 284:26] + dbg_state_en <= _T_354 @[dbg.scala 283:20] + node _T_355 = eq(dbg_nxtstate, UInt<3>("h03")) @[dbg.scala 285:60] + node _T_356 = and(dbg_state_en, _T_355) @[dbg.scala 285:44] + abstractcs_busy_wren <= _T_356 @[dbg.scala 285:28] + abstractcs_busy_din <= UInt<1>("h01") @[dbg.scala 286:27] + node _T_357 = eq(dbg_nxtstate, UInt<3>("h06")) @[dbg.scala 287:58] + node _T_358 = and(dbg_state_en, _T_357) @[dbg.scala 287:42] + node _T_359 = bits(_T_358, 0, 0) @[dbg.scala 287:87] + io.dbg_resume_req <= _T_359 @[dbg.scala 287:25] + node _T_360 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 288:59] + node _T_361 = and(dmcontrol_wren_Q, _T_360) @[dbg.scala 288:44] + node _T_362 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 288:81] + node _T_363 = not(_T_362) @[dbg.scala 288:67] + node _T_364 = and(_T_361, _T_363) @[dbg.scala 288:64] + node _T_365 = bits(_T_364, 0, 0) @[dbg.scala 288:102] + io.dbg_halt_req <= _T_365 @[dbg.scala 288:23] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_366 = eq(UInt<3>("h03"), dbg_state) @[Conditional.scala 37:30] + when _T_366 : @[Conditional.scala 39:67] + node _T_367 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 291:40] + node _T_368 = bits(abstractcs_reg, 10, 8) @[dbg.scala 291:77] + node _T_369 = orr(_T_368) @[dbg.scala 291:85] + node _T_370 = mux(_T_369, UInt<3>("h05"), UInt<3>("h04")) @[dbg.scala 291:62] + node _T_371 = mux(_T_367, UInt<3>("h00"), _T_370) @[dbg.scala 291:26] + dbg_nxtstate <= _T_371 @[dbg.scala 291:20] + node _T_372 = bits(abstractcs_reg, 10, 8) @[dbg.scala 292:71] + node _T_373 = orr(_T_372) @[dbg.scala 292:79] + node _T_374 = or(io.dbg_dec.dbg_ib.dbg_cmd_valid, _T_373) @[dbg.scala 292:55] + node _T_375 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 292:98] + node _T_376 = or(_T_374, _T_375) @[dbg.scala 292:83] + dbg_state_en <= _T_376 @[dbg.scala 292:20] + node _T_377 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 293:59] + node _T_378 = and(dmcontrol_wren_Q, _T_377) @[dbg.scala 293:44] + node _T_379 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 293:81] + node _T_380 = not(_T_379) @[dbg.scala 293:67] + node _T_381 = and(_T_378, _T_380) @[dbg.scala 293:64] + node _T_382 = bits(_T_381, 0, 0) @[dbg.scala 293:102] + io.dbg_halt_req <= _T_382 @[dbg.scala 293:23] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_383 = eq(UInt<3>("h04"), dbg_state) @[Conditional.scala 37:30] + when _T_383 : @[Conditional.scala 39:67] + node _T_384 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 296:40] + node _T_385 = mux(_T_384, UInt<3>("h00"), UInt<3>("h05")) @[dbg.scala 296:26] + dbg_nxtstate <= _T_385 @[dbg.scala 296:20] + node _T_386 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 297:59] + node _T_387 = or(io.core_dbg_cmd_done, _T_386) @[dbg.scala 297:44] + dbg_state_en <= _T_387 @[dbg.scala 297:20] + node _T_388 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 298:59] + node _T_389 = and(dmcontrol_wren_Q, _T_388) @[dbg.scala 298:44] + node _T_390 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 298:81] + node _T_391 = not(_T_390) @[dbg.scala 298:67] + node _T_392 = and(_T_389, _T_391) @[dbg.scala 298:64] + node _T_393 = bits(_T_392, 0, 0) @[dbg.scala 298:102] + io.dbg_halt_req <= _T_393 @[dbg.scala 298:23] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_394 = eq(UInt<3>("h05"), dbg_state) @[Conditional.scala 37:30] + when _T_394 : @[Conditional.scala 39:67] + node _T_395 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 301:40] + node _T_396 = mux(_T_395, UInt<3>("h00"), UInt<3>("h02")) @[dbg.scala 301:26] + dbg_nxtstate <= _T_396 @[dbg.scala 301:20] + dbg_state_en <= UInt<1>("h01") @[dbg.scala 302:20] + abstractcs_busy_wren <= dbg_state_en @[dbg.scala 303:28] + abstractcs_busy_din <= UInt<1>("h00") @[dbg.scala 304:27] + node _T_397 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 305:59] + node _T_398 = and(dmcontrol_wren_Q, _T_397) @[dbg.scala 305:44] + node _T_399 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 305:81] + node _T_400 = not(_T_399) @[dbg.scala 305:67] + node _T_401 = and(_T_398, _T_400) @[dbg.scala 305:64] + node _T_402 = bits(_T_401, 0, 0) @[dbg.scala 305:102] + io.dbg_halt_req <= _T_402 @[dbg.scala 305:23] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_403 = eq(UInt<3>("h06"), dbg_state) @[Conditional.scala 37:30] + when _T_403 : @[Conditional.scala 39:67] + dbg_nxtstate <= UInt<3>("h00") @[dbg.scala 308:20] + node _T_404 = bits(dmstatus_reg, 17, 17) @[dbg.scala 309:35] + node _T_405 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 309:55] + node _T_406 = or(_T_404, _T_405) @[dbg.scala 309:40] + dbg_state_en <= _T_406 @[dbg.scala 309:20] + node _T_407 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 310:59] + node _T_408 = and(dmcontrol_wren_Q, _T_407) @[dbg.scala 310:44] + node _T_409 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 310:81] + node _T_410 = not(_T_409) @[dbg.scala 310:67] + node _T_411 = and(_T_408, _T_410) @[dbg.scala 310:64] + node _T_412 = bits(_T_411, 0, 0) @[dbg.scala 310:102] + io.dbg_halt_req <= _T_412 @[dbg.scala 310:23] + skip @[Conditional.scala 39:67] + node _T_413 = eq(io.dmi_reg_addr, UInt<3>("h04")) @[dbg.scala 313:52] + node _T_414 = bits(_T_413, 0, 0) @[Bitwise.scala 72:15] + node _T_415 = mux(_T_414, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_416 = and(_T_415, data0_reg) @[dbg.scala 313:71] + node _T_417 = eq(io.dmi_reg_addr, UInt<3>("h05")) @[dbg.scala 313:110] + node _T_418 = bits(_T_417, 0, 0) @[Bitwise.scala 72:15] + node _T_419 = mux(_T_418, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_420 = and(_T_419, data1_reg) @[dbg.scala 313:122] + node _T_421 = or(_T_416, _T_420) @[dbg.scala 313:83] + node _T_422 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[dbg.scala 314:30] + node _T_423 = bits(_T_422, 0, 0) @[Bitwise.scala 72:15] + node _T_424 = mux(_T_423, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_425 = and(_T_424, dmcontrol_reg) @[dbg.scala 314:43] + node _T_426 = or(_T_421, _T_425) @[dbg.scala 313:134] + node _T_427 = eq(io.dmi_reg_addr, UInt<5>("h011")) @[dbg.scala 314:86] + node _T_428 = bits(_T_427, 0, 0) @[Bitwise.scala 72:15] + node _T_429 = mux(_T_428, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_430 = and(_T_429, dmstatus_reg) @[dbg.scala 314:99] + node _T_431 = or(_T_426, _T_430) @[dbg.scala 314:59] + node _T_432 = eq(io.dmi_reg_addr, UInt<5>("h016")) @[dbg.scala 315:30] + node _T_433 = bits(_T_432, 0, 0) @[Bitwise.scala 72:15] + node _T_434 = mux(_T_433, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_435 = and(_T_434, abstractcs_reg) @[dbg.scala 315:43] + node _T_436 = or(_T_431, _T_435) @[dbg.scala 314:114] + node _T_437 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 315:87] + node _T_438 = bits(_T_437, 0, 0) @[Bitwise.scala 72:15] + node _T_439 = mux(_T_438, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_440 = and(_T_439, command_reg) @[dbg.scala 315:100] + node _T_441 = or(_T_436, _T_440) @[dbg.scala 315:60] + node _T_442 = eq(io.dmi_reg_addr, UInt<7>("h040")) @[dbg.scala 316:30] + node _T_443 = bits(_T_442, 0, 0) @[Bitwise.scala 72:15] + node _T_444 = mux(_T_443, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_445 = and(_T_444, haltsum0_reg) @[dbg.scala 316:43] + node _T_446 = or(_T_441, _T_445) @[dbg.scala 315:114] + node _T_447 = eq(io.dmi_reg_addr, UInt<6>("h038")) @[dbg.scala 316:85] + node _T_448 = bits(_T_447, 0, 0) @[Bitwise.scala 72:15] + node _T_449 = mux(_T_448, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_450 = and(_T_449, sbcs_reg) @[dbg.scala 316:98] + node _T_451 = or(_T_446, _T_450) @[dbg.scala 316:58] + node _T_452 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[dbg.scala 317:30] + node _T_453 = bits(_T_452, 0, 0) @[Bitwise.scala 72:15] + node _T_454 = mux(_T_453, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_455 = and(_T_454, sbaddress0_reg) @[dbg.scala 317:43] + node _T_456 = or(_T_451, _T_455) @[dbg.scala 316:109] + node _T_457 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 317:87] + node _T_458 = bits(_T_457, 0, 0) @[Bitwise.scala 72:15] + node _T_459 = mux(_T_458, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_460 = and(_T_459, sbdata0_reg) @[dbg.scala 317:100] + node _T_461 = or(_T_456, _T_460) @[dbg.scala 317:60] + node _T_462 = eq(io.dmi_reg_addr, UInt<6>("h03d")) @[dbg.scala 318:30] + node _T_463 = bits(_T_462, 0, 0) @[Bitwise.scala 72:15] + node _T_464 = mux(_T_463, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_465 = and(_T_464, sbdata1_reg) @[dbg.scala 318:43] + node dmi_reg_rdata_din = or(_T_461, _T_465) @[dbg.scala 317:114] + reg _T_466 : UInt, rvclkhdr.io.l1clk with : (reset => (rst_temp, UInt<1>("h00"))) @[Reg.scala 27:20] + when dbg_state_en : @[Reg.scala 28:19] + _T_466 <= dbg_nxtstate @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + dbg_state <= _T_466 @[dbg.scala 320:13] + reg _T_467 : UInt, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] + when io.dmi_reg_en : @[Reg.scala 28:19] + _T_467 <= dmi_reg_rdata_din @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.dmi_reg_rdata <= _T_467 @[dbg.scala 325:20] + node _T_468 = bits(command_reg, 31, 24) @[dbg.scala 329:53] + node _T_469 = eq(_T_468, UInt<2>("h02")) @[dbg.scala 329:62] + node _T_470 = bits(data1_reg, 31, 2) @[dbg.scala 329:88] + node _T_471 = cat(_T_470, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_472 = bits(command_reg, 11, 0) @[dbg.scala 329:138] + node _T_473 = cat(UInt<20>("h00"), _T_472) @[Cat.scala 29:58] + node _T_474 = mux(_T_469, _T_471, _T_473) @[dbg.scala 329:40] + io.dbg_dec.dbg_ib.dbg_cmd_addr <= _T_474 @[dbg.scala 329:34] + node _T_475 = bits(data0_reg, 31, 0) @[dbg.scala 330:50] + io.dbg_dec.dbg_dctl.dbg_cmd_wrdata <= _T_475 @[dbg.scala 330:38] + node _T_476 = eq(dbg_state, UInt<3>("h03")) @[dbg.scala 331:50] + node _T_477 = bits(abstractcs_reg, 10, 8) @[dbg.scala 331:91] + node _T_478 = orr(_T_477) @[dbg.scala 331:99] + node _T_479 = eq(_T_478, UInt<1>("h00")) @[dbg.scala 331:75] + node _T_480 = and(_T_476, _T_479) @[dbg.scala 331:73] + node _T_481 = and(_T_480, io.dbg_dma_io.dma_dbg_ready) @[dbg.scala 331:104] + node _T_482 = bits(_T_481, 0, 0) @[dbg.scala 331:141] + io.dbg_dec.dbg_ib.dbg_cmd_valid <= _T_482 @[dbg.scala 331:35] + node _T_483 = bits(command_reg, 16, 16) @[dbg.scala 332:49] + node _T_484 = bits(_T_483, 0, 0) @[dbg.scala 332:60] + io.dbg_dec.dbg_ib.dbg_cmd_write <= _T_484 @[dbg.scala 332:35] + node _T_485 = bits(command_reg, 31, 24) @[dbg.scala 333:53] + node _T_486 = eq(_T_485, UInt<2>("h02")) @[dbg.scala 333:62] + node _T_487 = bits(command_reg, 15, 12) @[dbg.scala 333:113] + node _T_488 = eq(_T_487, UInt<1>("h00")) @[dbg.scala 333:122] + node _T_489 = cat(UInt<1>("h00"), _T_488) @[Cat.scala 29:58] + node _T_490 = mux(_T_486, UInt<2>("h02"), _T_489) @[dbg.scala 333:40] + io.dbg_dec.dbg_ib.dbg_cmd_type <= _T_490 @[dbg.scala 333:34] + node _T_491 = bits(command_reg, 21, 20) @[dbg.scala 334:33] + io.dbg_cmd_size <= _T_491 @[dbg.scala 334:19] + node _T_492 = eq(dbg_state, UInt<3>("h03")) @[dbg.scala 335:47] + node _T_493 = bits(abstractcs_reg, 10, 8) @[dbg.scala 335:88] + node _T_494 = orr(_T_493) @[dbg.scala 335:96] + node _T_495 = eq(_T_494, UInt<1>("h00")) @[dbg.scala 335:72] + node _T_496 = and(_T_492, _T_495) @[dbg.scala 335:70] + node _T_497 = eq(dbg_state, UInt<3>("h04")) @[dbg.scala 335:114] + node _T_498 = or(_T_496, _T_497) @[dbg.scala 335:101] + node _T_499 = bits(_T_498, 0, 0) @[dbg.scala 335:143] + io.dbg_dma_io.dbg_dma_bubble <= _T_499 @[dbg.scala 335:32] + wire sb_nxtstate : UInt<4> + sb_nxtstate <= UInt<4>("h00") + sb_nxtstate <= UInt<4>("h00") @[dbg.scala 338:15] + sbcs_sbbusy_wren <= UInt<1>("h00") @[dbg.scala 340:20] + sbcs_sbbusy_din <= UInt<1>("h00") @[dbg.scala 341:19] + sbcs_sberror_wren <= UInt<1>("h00") @[dbg.scala 342:21] + sbcs_sberror_din <= UInt<3>("h00") @[dbg.scala 343:20] + sbaddress0_reg_wren1 <= UInt<1>("h00") @[dbg.scala 344:24] + node _T_500 = eq(UInt<4>("h00"), sb_state) @[Conditional.scala 37:30] + when _T_500 : @[Conditional.scala 40:58] + node _T_501 = mux(sbdata0wr_access, UInt<4>("h02"), UInt<4>("h01")) @[dbg.scala 347:25] + sb_nxtstate <= _T_501 @[dbg.scala 347:19] + node _T_502 = or(sbdata0wr_access, sbreadondata_access) @[dbg.scala 348:39] + node _T_503 = or(_T_502, sbreadonaddr_access) @[dbg.scala 348:61] + sb_state_en <= _T_503 @[dbg.scala 348:19] + sbcs_sbbusy_wren <= sb_state_en @[dbg.scala 349:24] + sbcs_sbbusy_din <= UInt<1>("h01") @[dbg.scala 350:23] + node _T_504 = bits(io.dmi_reg_wdata, 14, 12) @[dbg.scala 351:56] + node _T_505 = orr(_T_504) @[dbg.scala 351:65] + node _T_506 = and(sbcs_wren, _T_505) @[dbg.scala 351:38] + sbcs_sberror_wren <= _T_506 @[dbg.scala 351:25] + node _T_507 = bits(io.dmi_reg_wdata, 14, 12) @[dbg.scala 352:44] + node _T_508 = not(_T_507) @[dbg.scala 352:27] + node _T_509 = bits(sbcs_reg, 14, 12) @[dbg.scala 352:63] + node _T_510 = and(_T_508, _T_509) @[dbg.scala 352:53] + sbcs_sberror_din <= _T_510 @[dbg.scala 352:24] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_511 = eq(UInt<4>("h01"), sb_state) @[Conditional.scala 37:30] + when _T_511 : @[Conditional.scala 39:67] + node _T_512 = or(sbcs_unaligned, sbcs_illegal_size) @[dbg.scala 355:41] + node _T_513 = mux(_T_512, UInt<4>("h09"), UInt<4>("h03")) @[dbg.scala 355:25] + sb_nxtstate <= _T_513 @[dbg.scala 355:19] + node _T_514 = or(io.dbg_bus_clk_en, sbcs_unaligned) @[dbg.scala 356:40] + node _T_515 = or(_T_514, sbcs_illegal_size) @[dbg.scala 356:57] + sb_state_en <= _T_515 @[dbg.scala 356:19] + node _T_516 = or(sbcs_unaligned, sbcs_illegal_size) @[dbg.scala 357:43] + sbcs_sberror_wren <= _T_516 @[dbg.scala 357:25] + node _T_517 = mux(sbcs_unaligned, UInt<3>("h03"), UInt<3>("h04")) @[dbg.scala 358:30] + sbcs_sberror_din <= _T_517 @[dbg.scala 358:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_518 = eq(UInt<4>("h02"), sb_state) @[Conditional.scala 37:30] + when _T_518 : @[Conditional.scala 39:67] + node _T_519 = or(sbcs_unaligned, sbcs_illegal_size) @[dbg.scala 361:41] + node _T_520 = mux(_T_519, UInt<4>("h09"), UInt<4>("h04")) @[dbg.scala 361:25] + sb_nxtstate <= _T_520 @[dbg.scala 361:19] + node _T_521 = or(io.dbg_bus_clk_en, sbcs_unaligned) @[dbg.scala 362:40] + node _T_522 = or(_T_521, sbcs_illegal_size) @[dbg.scala 362:57] + sb_state_en <= _T_522 @[dbg.scala 362:19] + node _T_523 = or(sbcs_unaligned, sbcs_illegal_size) @[dbg.scala 363:43] + sbcs_sberror_wren <= _T_523 @[dbg.scala 363:25] + node _T_524 = mux(sbcs_unaligned, UInt<3>("h03"), UInt<3>("h04")) @[dbg.scala 364:30] + sbcs_sberror_din <= _T_524 @[dbg.scala 364:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_525 = eq(UInt<4>("h03"), sb_state) @[Conditional.scala 37:30] + when _T_525 : @[Conditional.scala 39:67] + sb_nxtstate <= UInt<4>("h07") @[dbg.scala 367:19] + node _T_526 = and(sb_bus_cmd_read, io.dbg_bus_clk_en) @[dbg.scala 368:38] + sb_state_en <= _T_526 @[dbg.scala 368:19] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_527 = eq(UInt<4>("h04"), sb_state) @[Conditional.scala 37:30] + when _T_527 : @[Conditional.scala 39:67] + node _T_528 = and(sb_bus_cmd_write_addr, sb_bus_cmd_write_data) @[dbg.scala 371:48] + node _T_529 = mux(sb_bus_cmd_write_data, UInt<4>("h05"), UInt<4>("h06")) @[dbg.scala 371:95] + node _T_530 = mux(_T_528, UInt<4>("h08"), _T_529) @[dbg.scala 371:25] + sb_nxtstate <= _T_530 @[dbg.scala 371:19] + node _T_531 = or(sb_bus_cmd_write_addr, sb_bus_cmd_write_data) @[dbg.scala 372:45] + node _T_532 = and(_T_531, io.dbg_bus_clk_en) @[dbg.scala 372:70] + sb_state_en <= _T_532 @[dbg.scala 372:19] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_533 = eq(UInt<4>("h05"), sb_state) @[Conditional.scala 37:30] + when _T_533 : @[Conditional.scala 39:67] + sb_nxtstate <= UInt<4>("h08") @[dbg.scala 375:19] + node _T_534 = and(sb_bus_cmd_write_addr, io.dbg_bus_clk_en) @[dbg.scala 376:44] + sb_state_en <= _T_534 @[dbg.scala 376:19] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_535 = eq(UInt<4>("h06"), sb_state) @[Conditional.scala 37:30] + when _T_535 : @[Conditional.scala 39:67] + sb_nxtstate <= UInt<4>("h08") @[dbg.scala 379:19] + node _T_536 = and(sb_bus_cmd_write_data, io.dbg_bus_clk_en) @[dbg.scala 380:44] + sb_state_en <= _T_536 @[dbg.scala 380:19] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_537 = eq(UInt<4>("h07"), sb_state) @[Conditional.scala 37:30] + when _T_537 : @[Conditional.scala 39:67] + sb_nxtstate <= UInt<4>("h09") @[dbg.scala 383:19] + node _T_538 = and(sb_bus_rsp_read, io.dbg_bus_clk_en) @[dbg.scala 384:38] + sb_state_en <= _T_538 @[dbg.scala 384:19] + node _T_539 = and(sb_state_en, sb_bus_rsp_error) @[dbg.scala 385:40] + sbcs_sberror_wren <= _T_539 @[dbg.scala 385:25] + sbcs_sberror_din <= UInt<3>("h02") @[dbg.scala 386:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_540 = eq(UInt<4>("h08"), sb_state) @[Conditional.scala 37:30] + when _T_540 : @[Conditional.scala 39:67] + sb_nxtstate <= UInt<4>("h09") @[dbg.scala 389:19] + node _T_541 = and(sb_bus_rsp_write, io.dbg_bus_clk_en) @[dbg.scala 390:39] + sb_state_en <= _T_541 @[dbg.scala 390:19] + node _T_542 = and(sb_state_en, sb_bus_rsp_error) @[dbg.scala 391:40] + sbcs_sberror_wren <= _T_542 @[dbg.scala 391:25] + sbcs_sberror_din <= UInt<3>("h02") @[dbg.scala 392:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_543 = eq(UInt<4>("h09"), sb_state) @[Conditional.scala 37:30] + when _T_543 : @[Conditional.scala 39:67] + sb_nxtstate <= UInt<4>("h00") @[dbg.scala 395:19] + sb_state_en <= UInt<1>("h01") @[dbg.scala 396:19] + sbcs_sbbusy_wren <= UInt<1>("h01") @[dbg.scala 397:24] + sbcs_sbbusy_din <= UInt<1>("h00") @[dbg.scala 398:23] + node _T_544 = bits(sbcs_reg, 16, 16) @[dbg.scala 399:39] + sbaddress0_reg_wren1 <= _T_544 @[dbg.scala 399:28] + skip @[Conditional.scala 39:67] + reg _T_545 : UInt, rvclkhdr_1.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] + when sb_state_en : @[Reg.scala 28:19] + _T_545 <= sb_nxtstate @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + sb_state <= _T_545 @[dbg.scala 402:12] + node _T_546 = and(io.sb_axi.ar.valid, io.sb_axi.ar.ready) @[dbg.scala 406:41] + sb_bus_cmd_read <= _T_546 @[dbg.scala 406:19] + node _T_547 = and(io.sb_axi.aw.valid, io.sb_axi.aw.ready) @[dbg.scala 407:47] + sb_bus_cmd_write_addr <= _T_547 @[dbg.scala 407:25] + node _T_548 = and(io.sb_axi.w.valid, io.sb_axi.w.ready) @[dbg.scala 408:46] + sb_bus_cmd_write_data <= _T_548 @[dbg.scala 408:25] + node _T_549 = and(io.sb_axi.r.valid, io.sb_axi.r.ready) @[dbg.scala 409:40] + sb_bus_rsp_read <= _T_549 @[dbg.scala 409:19] + node _T_550 = and(io.sb_axi.b.valid, io.sb_axi.b.ready) @[dbg.scala 410:41] + sb_bus_rsp_write <= _T_550 @[dbg.scala 410:20] + node _T_551 = bits(io.sb_axi.r.bits.resp, 1, 0) @[dbg.scala 411:62] + node _T_552 = orr(_T_551) @[dbg.scala 411:69] + node _T_553 = and(sb_bus_rsp_read, _T_552) @[dbg.scala 411:39] + node _T_554 = bits(io.sb_axi.b.bits.resp, 1, 0) @[dbg.scala 411:115] + node _T_555 = orr(_T_554) @[dbg.scala 411:122] + node _T_556 = and(sb_bus_rsp_write, _T_555) @[dbg.scala 411:92] + node _T_557 = or(_T_553, _T_556) @[dbg.scala 411:73] + sb_bus_rsp_error <= _T_557 @[dbg.scala 411:20] + node _T_558 = eq(sb_state, UInt<4>("h04")) @[dbg.scala 412:36] + node _T_559 = eq(sb_state, UInt<4>("h05")) @[dbg.scala 412:71] + node _T_560 = or(_T_558, _T_559) @[dbg.scala 412:59] + node _T_561 = bits(_T_560, 0, 0) @[dbg.scala 412:106] + io.sb_axi.aw.valid <= _T_561 @[dbg.scala 412:22] + io.sb_axi.aw.bits.addr <= sbaddress0_reg @[dbg.scala 413:26] + io.sb_axi.aw.bits.id <= UInt<1>("h00") @[dbg.scala 414:24] + node _T_562 = bits(sbcs_reg, 19, 17) @[dbg.scala 415:37] + io.sb_axi.aw.bits.size <= _T_562 @[dbg.scala 415:26] + io.sb_axi.aw.bits.prot <= UInt<1>("h00") @[dbg.scala 416:26] + io.sb_axi.aw.bits.cache <= UInt<4>("h0f") @[dbg.scala 417:27] + node _T_563 = bits(sbaddress0_reg, 31, 28) @[dbg.scala 418:45] + io.sb_axi.aw.bits.region <= _T_563 @[dbg.scala 418:28] + io.sb_axi.aw.bits.len <= UInt<1>("h00") @[dbg.scala 419:25] + io.sb_axi.aw.bits.burst <= UInt<2>("h01") @[dbg.scala 420:27] + io.sb_axi.aw.bits.qos <= UInt<1>("h00") @[dbg.scala 421:25] + io.sb_axi.aw.bits.lock <= UInt<1>("h00") @[dbg.scala 422:26] + node _T_564 = eq(sb_state, UInt<4>("h04")) @[dbg.scala 423:35] + node _T_565 = eq(sb_state, UInt<4>("h06")) @[dbg.scala 423:70] + node _T_566 = or(_T_564, _T_565) @[dbg.scala 423:58] + node _T_567 = bits(_T_566, 0, 0) @[dbg.scala 423:105] + io.sb_axi.w.valid <= _T_567 @[dbg.scala 423:21] + node _T_568 = bits(sbcs_reg, 19, 17) @[dbg.scala 424:46] + node _T_569 = eq(_T_568, UInt<1>("h00")) @[dbg.scala 424:55] + node _T_570 = bits(_T_569, 0, 0) @[Bitwise.scala 72:15] + node _T_571 = mux(_T_570, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] + node _T_572 = bits(sbdata0_reg, 7, 0) @[dbg.scala 424:87] + node _T_573 = cat(_T_572, _T_572) @[Cat.scala 29:58] + node _T_574 = cat(_T_573, _T_573) @[Cat.scala 29:58] + node _T_575 = cat(_T_574, _T_574) @[Cat.scala 29:58] + node _T_576 = and(_T_571, _T_575) @[dbg.scala 424:65] + node _T_577 = bits(sbcs_reg, 19, 17) @[dbg.scala 424:116] + node _T_578 = eq(_T_577, UInt<1>("h01")) @[dbg.scala 424:125] + node _T_579 = bits(_T_578, 0, 0) @[Bitwise.scala 72:15] + node _T_580 = mux(_T_579, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] + node _T_581 = bits(sbdata0_reg, 15, 0) @[dbg.scala 424:159] + node _T_582 = cat(_T_581, _T_581) @[Cat.scala 29:58] + node _T_583 = cat(_T_582, _T_582) @[Cat.scala 29:58] + node _T_584 = and(_T_580, _T_583) @[dbg.scala 424:138] + node _T_585 = or(_T_576, _T_584) @[dbg.scala 424:96] + node _T_586 = bits(sbcs_reg, 19, 17) @[dbg.scala 425:23] + node _T_587 = eq(_T_586, UInt<2>("h02")) @[dbg.scala 425:32] + node _T_588 = bits(_T_587, 0, 0) @[Bitwise.scala 72:15] + node _T_589 = mux(_T_588, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] + node _T_590 = bits(sbdata0_reg, 31, 0) @[dbg.scala 425:67] + node _T_591 = cat(_T_590, _T_590) @[Cat.scala 29:58] + node _T_592 = and(_T_589, _T_591) @[dbg.scala 425:45] + node _T_593 = or(_T_585, _T_592) @[dbg.scala 424:168] + node _T_594 = bits(sbcs_reg, 19, 17) @[dbg.scala 425:97] + node _T_595 = eq(_T_594, UInt<2>("h03")) @[dbg.scala 425:106] + node _T_596 = bits(_T_595, 0, 0) @[Bitwise.scala 72:15] + node _T_597 = mux(_T_596, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] + node _T_598 = bits(sbdata1_reg, 31, 0) @[dbg.scala 425:136] + node _T_599 = bits(sbdata0_reg, 31, 0) @[dbg.scala 425:156] + node _T_600 = cat(_T_598, _T_599) @[Cat.scala 29:58] + node _T_601 = and(_T_597, _T_600) @[dbg.scala 425:119] + node _T_602 = or(_T_593, _T_601) @[dbg.scala 425:77] + io.sb_axi.w.bits.data <= _T_602 @[dbg.scala 424:25] + node _T_603 = bits(sbcs_reg, 19, 17) @[dbg.scala 427:45] + node _T_604 = eq(_T_603, UInt<1>("h00")) @[dbg.scala 427:54] + node _T_605 = bits(_T_604, 0, 0) @[Bitwise.scala 72:15] + node _T_606 = mux(_T_605, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_607 = bits(sbaddress0_reg, 2, 0) @[dbg.scala 427:99] + node _T_608 = dshl(UInt<8>("h01"), _T_607) @[dbg.scala 427:82] + node _T_609 = and(_T_606, _T_608) @[dbg.scala 427:67] + node _T_610 = bits(sbcs_reg, 19, 17) @[dbg.scala 428:22] + node _T_611 = eq(_T_610, UInt<1>("h01")) @[dbg.scala 428:31] + node _T_612 = bits(_T_611, 0, 0) @[Bitwise.scala 72:15] + node _T_613 = mux(_T_612, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_614 = bits(sbaddress0_reg, 2, 1) @[dbg.scala 428:80] + node _T_615 = cat(_T_614, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_616 = dshl(UInt<8>("h03"), _T_615) @[dbg.scala 428:59] + node _T_617 = and(_T_613, _T_616) @[dbg.scala 428:44] + node _T_618 = or(_T_609, _T_617) @[dbg.scala 427:107] + node _T_619 = bits(sbcs_reg, 19, 17) @[dbg.scala 429:22] + node _T_620 = eq(_T_619, UInt<2>("h02")) @[dbg.scala 429:31] + node _T_621 = bits(_T_620, 0, 0) @[Bitwise.scala 72:15] + node _T_622 = mux(_T_621, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_623 = bits(sbaddress0_reg, 2, 2) @[dbg.scala 429:80] + node _T_624 = cat(_T_623, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_625 = dshl(UInt<8>("h0f"), _T_624) @[dbg.scala 429:59] + node _T_626 = and(_T_622, _T_625) @[dbg.scala 429:44] + node _T_627 = or(_T_618, _T_626) @[dbg.scala 428:97] + node _T_628 = bits(sbcs_reg, 19, 17) @[dbg.scala 430:22] + node _T_629 = eq(_T_628, UInt<2>("h03")) @[dbg.scala 430:31] + node _T_630 = bits(_T_629, 0, 0) @[Bitwise.scala 72:15] + node _T_631 = mux(_T_630, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_632 = and(_T_631, UInt<8>("h0ff")) @[dbg.scala 430:44] + node _T_633 = or(_T_627, _T_632) @[dbg.scala 429:100] + io.sb_axi.w.bits.strb <= _T_633 @[dbg.scala 427:25] + io.sb_axi.w.bits.last <= UInt<1>("h01") @[dbg.scala 432:25] + node _T_634 = eq(sb_state, UInt<4>("h03")) @[dbg.scala 433:35] + node _T_635 = bits(_T_634, 0, 0) @[dbg.scala 433:64] + io.sb_axi.ar.valid <= _T_635 @[dbg.scala 433:22] + io.sb_axi.ar.bits.addr <= sbaddress0_reg @[dbg.scala 434:26] + io.sb_axi.ar.bits.id <= UInt<1>("h00") @[dbg.scala 435:24] + node _T_636 = bits(sbcs_reg, 19, 17) @[dbg.scala 436:37] + io.sb_axi.ar.bits.size <= _T_636 @[dbg.scala 436:26] + io.sb_axi.ar.bits.prot <= UInt<1>("h00") @[dbg.scala 437:26] + io.sb_axi.ar.bits.cache <= UInt<1>("h00") @[dbg.scala 438:27] + node _T_637 = bits(sbaddress0_reg, 31, 28) @[dbg.scala 439:45] + io.sb_axi.ar.bits.region <= _T_637 @[dbg.scala 439:28] + io.sb_axi.ar.bits.len <= UInt<1>("h00") @[dbg.scala 440:25] + io.sb_axi.ar.bits.burst <= UInt<2>("h01") @[dbg.scala 441:27] + io.sb_axi.ar.bits.qos <= UInt<1>("h00") @[dbg.scala 442:25] + io.sb_axi.ar.bits.lock <= UInt<1>("h00") @[dbg.scala 443:26] + io.sb_axi.b.ready <= UInt<1>("h01") @[dbg.scala 444:21] + io.sb_axi.r.ready <= UInt<1>("h01") @[dbg.scala 445:21] + node _T_638 = bits(sbcs_reg, 19, 17) @[dbg.scala 446:37] + node _T_639 = eq(_T_638, UInt<1>("h00")) @[dbg.scala 446:46] + node _T_640 = bits(_T_639, 0, 0) @[Bitwise.scala 72:15] + node _T_641 = mux(_T_640, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] + node _T_642 = bits(io.sb_axi.r.bits.data, 63, 0) @[dbg.scala 446:84] + node _T_643 = bits(sbaddress0_reg, 2, 0) @[dbg.scala 446:115] + node _T_644 = mul(UInt<4>("h08"), _T_643) @[dbg.scala 446:99] + node _T_645 = dshr(_T_642, _T_644) @[dbg.scala 446:92] + node _T_646 = and(_T_645, UInt<64>("h0ff")) @[dbg.scala 446:123] + node _T_647 = and(_T_641, _T_646) @[dbg.scala 446:59] + node _T_648 = bits(sbcs_reg, 19, 17) @[dbg.scala 447:23] + node _T_649 = eq(_T_648, UInt<1>("h01")) @[dbg.scala 447:32] + node _T_650 = bits(_T_649, 0, 0) @[Bitwise.scala 72:15] + node _T_651 = mux(_T_650, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] + node _T_652 = bits(io.sb_axi.r.bits.data, 63, 0) @[dbg.scala 447:70] + node _T_653 = bits(sbaddress0_reg, 2, 1) @[dbg.scala 447:102] + node _T_654 = mul(UInt<5>("h010"), _T_653) @[dbg.scala 447:86] + node _T_655 = dshr(_T_652, _T_654) @[dbg.scala 447:78] + node _T_656 = and(_T_655, UInt<64>("h0ffff")) @[dbg.scala 447:110] + node _T_657 = and(_T_651, _T_656) @[dbg.scala 447:45] + node _T_658 = or(_T_647, _T_657) @[dbg.scala 446:140] + node _T_659 = bits(sbcs_reg, 19, 17) @[dbg.scala 448:23] + node _T_660 = eq(_T_659, UInt<2>("h02")) @[dbg.scala 448:32] + node _T_661 = bits(_T_660, 0, 0) @[Bitwise.scala 72:15] + node _T_662 = mux(_T_661, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] + node _T_663 = bits(io.sb_axi.r.bits.data, 63, 0) @[dbg.scala 448:70] + node _T_664 = bits(sbaddress0_reg, 2, 2) @[dbg.scala 448:102] + node _T_665 = mul(UInt<6>("h020"), _T_664) @[dbg.scala 448:86] + node _T_666 = dshr(_T_663, _T_665) @[dbg.scala 448:78] + node _T_667 = and(_T_666, UInt<64>("h0ffffffff")) @[dbg.scala 448:107] + node _T_668 = and(_T_662, _T_667) @[dbg.scala 448:45] + node _T_669 = or(_T_658, _T_668) @[dbg.scala 447:129] + node _T_670 = bits(sbcs_reg, 19, 17) @[dbg.scala 449:23] + node _T_671 = eq(_T_670, UInt<2>("h03")) @[dbg.scala 449:32] + node _T_672 = bits(_T_671, 0, 0) @[Bitwise.scala 72:15] + node _T_673 = mux(_T_672, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] + node _T_674 = bits(io.sb_axi.r.bits.data, 63, 0) @[dbg.scala 449:68] + node _T_675 = and(_T_673, _T_674) @[dbg.scala 449:45] + node _T_676 = or(_T_669, _T_675) @[dbg.scala 448:131] + sb_bus_rdata <= _T_676 @[dbg.scala 446:16] + io.dbg_dma.dbg_ib.dbg_cmd_addr <= io.dbg_dec.dbg_ib.dbg_cmd_addr @[dbg.scala 452:39] + io.dbg_dma.dbg_dctl.dbg_cmd_wrdata <= io.dbg_dec.dbg_dctl.dbg_cmd_wrdata @[dbg.scala 453:39] + io.dbg_dma.dbg_ib.dbg_cmd_valid <= io.dbg_dec.dbg_ib.dbg_cmd_valid @[dbg.scala 454:39] + io.dbg_dma.dbg_ib.dbg_cmd_write <= io.dbg_dec.dbg_ib.dbg_cmd_write @[dbg.scala 455:39] + io.dbg_dma.dbg_ib.dbg_cmd_type <= io.dbg_dec.dbg_ib.dbg_cmd_type @[dbg.scala 456:39] + diff --git a/dbg.v b/dbg.v new file mode 100644 index 00000000..2afb7fd4 --- /dev/null +++ b/dbg.v @@ -0,0 +1,1180 @@ +module rvclkhdr( + output io_l1clk, + input io_clk, + input io_en, + input io_scan_mode +); + wire clkhdr_Q; // @[lib.scala 334:26] + wire clkhdr_CK; // @[lib.scala 334:26] + wire clkhdr_EN; // @[lib.scala 334:26] + wire clkhdr_SE; // @[lib.scala 334:26] + gated_latch clkhdr ( // @[lib.scala 334:26] + .Q(clkhdr_Q), + .CK(clkhdr_CK), + .EN(clkhdr_EN), + .SE(clkhdr_SE) + ); + assign io_l1clk = clkhdr_Q; // @[lib.scala 335:14] + assign clkhdr_CK = io_clk; // @[lib.scala 336:18] + assign clkhdr_EN = io_en; // @[lib.scala 337:18] + assign clkhdr_SE = io_scan_mode; // @[lib.scala 338:18] +endmodule +module dbg( + input clock, + input reset, + output [1:0] io_dbg_cmd_size, + output io_dbg_core_rst_l, + input [31:0] io_core_dbg_rddata, + input io_core_dbg_cmd_done, + input io_core_dbg_cmd_fail, + output io_dbg_halt_req, + output io_dbg_resume_req, + input io_dec_tlu_debug_mode, + input io_dec_tlu_dbg_halted, + input io_dec_tlu_mpc_halted_only, + input io_dec_tlu_resume_ack, + input io_dmi_reg_en, + input [6:0] io_dmi_reg_addr, + input io_dmi_reg_wr_en, + input [31:0] io_dmi_reg_wdata, + output [31:0] io_dmi_reg_rdata, + input io_sb_axi_aw_ready, + output io_sb_axi_aw_valid, + output io_sb_axi_aw_bits_id, + output [31:0] io_sb_axi_aw_bits_addr, + output [3:0] io_sb_axi_aw_bits_region, + output [7:0] io_sb_axi_aw_bits_len, + output [2:0] io_sb_axi_aw_bits_size, + output [1:0] io_sb_axi_aw_bits_burst, + output io_sb_axi_aw_bits_lock, + output [3:0] io_sb_axi_aw_bits_cache, + output [2:0] io_sb_axi_aw_bits_prot, + output [3:0] io_sb_axi_aw_bits_qos, + input io_sb_axi_w_ready, + output io_sb_axi_w_valid, + output [63:0] io_sb_axi_w_bits_data, + output [7:0] io_sb_axi_w_bits_strb, + output io_sb_axi_w_bits_last, + output io_sb_axi_b_ready, + input io_sb_axi_b_valid, + input [1:0] io_sb_axi_b_bits_resp, + input io_sb_axi_b_bits_id, + input io_sb_axi_ar_ready, + output io_sb_axi_ar_valid, + output io_sb_axi_ar_bits_id, + output [31:0] io_sb_axi_ar_bits_addr, + output [3:0] io_sb_axi_ar_bits_region, + output [7:0] io_sb_axi_ar_bits_len, + output [2:0] io_sb_axi_ar_bits_size, + output [1:0] io_sb_axi_ar_bits_burst, + output io_sb_axi_ar_bits_lock, + output [3:0] io_sb_axi_ar_bits_cache, + output [2:0] io_sb_axi_ar_bits_prot, + output [3:0] io_sb_axi_ar_bits_qos, + output io_sb_axi_r_ready, + input io_sb_axi_r_valid, + input io_sb_axi_r_bits_id, + input [63:0] io_sb_axi_r_bits_data, + input [1:0] io_sb_axi_r_bits_resp, + input io_sb_axi_r_bits_last, + output io_dbg_dec_dbg_ib_dbg_cmd_valid, + output io_dbg_dec_dbg_ib_dbg_cmd_write, + output [1:0] io_dbg_dec_dbg_ib_dbg_cmd_type, + output [31:0] io_dbg_dec_dbg_ib_dbg_cmd_addr, + output [31:0] io_dbg_dec_dbg_dctl_dbg_cmd_wrdata, + output io_dbg_dma_dbg_ib_dbg_cmd_valid, + output io_dbg_dma_dbg_ib_dbg_cmd_write, + output [1:0] io_dbg_dma_dbg_ib_dbg_cmd_type, + output [31:0] io_dbg_dma_dbg_ib_dbg_cmd_addr, + output [31:0] io_dbg_dma_dbg_dctl_dbg_cmd_wrdata, + output io_dbg_dma_io_dbg_dma_bubble, + input io_dbg_dma_io_dma_dbg_ready, + input io_dbg_bus_clk_en, + input io_dbg_rst_l, + input io_clk_override, + input io_scan_mode +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; + reg [31:0] _RAND_15; + reg [31:0] _RAND_16; + reg [31:0] _RAND_17; + reg [31:0] _RAND_18; + reg [31:0] _RAND_19; + reg [31:0] _RAND_20; + reg [31:0] _RAND_21; +`endif // RANDOMIZE_REG_INIT + wire [2:0] dbg_state; + wire dbg_state_en; + wire [3:0] sb_state; + wire sb_state_en; + wire [31:0] dmcontrol_reg; + wire [31:0] sbaddress0_reg; + wire sbcs_sbbusy_wren; + wire sbcs_sberror_wren; + wire [63:0] sb_bus_rdata; + wire sbaddress0_reg_wren1; + wire [31:0] dmstatus_reg; + wire dmstatus_havereset; + wire dmstatus_resumeack; + wire dmstatus_unavail; + wire dmstatus_running; + wire dmstatus_halted; + wire abstractcs_busy_wren; + wire sb_bus_cmd_read; + wire sb_bus_cmd_write_addr; + wire sb_bus_cmd_write_data; + wire sb_bus_rsp_read; + wire sb_bus_rsp_error; + wire sb_bus_rsp_write; + wire sbcs_sbbusy_din; + wire [31:0] data1_reg; + wire [31:0] sbcs_reg; + wire _T = dbg_state != 3'h0; // @[dbg.scala 95:51] + wire _T_1 = io_dmi_reg_en | _T; // @[dbg.scala 95:38] + wire _T_2 = _T_1 | dbg_state_en; // @[dbg.scala 95:69] + wire _T_3 = _T_2 | io_dec_tlu_dbg_halted; // @[dbg.scala 95:84] + wire _T_4 = io_dmi_reg_en | sb_state_en; // @[dbg.scala 96:37] + wire _T_5 = sb_state != 4'h0; // @[dbg.scala 96:63] + wire _T_6 = _T_4 | _T_5; // @[dbg.scala 96:51] + wire rvclkhdr_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_io_en; // @[lib.scala 343:22] + wire rvclkhdr_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_1_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_1_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_1_io_en; // @[lib.scala 343:22] + wire rvclkhdr_1_io_scan_mode; // @[lib.scala 343:22] + wire _T_9 = dmcontrol_reg[0] | io_scan_mode; // @[dbg.scala 100:65] + wire dbg_dm_rst_l = io_dbg_rst_l & _T_9; // @[dbg.scala 100:94] + wire _T_11 = io_dbg_rst_l & _T_9; // @[dbg.scala 102:38] + wire rst_temp = _T_11 & reset; // @[dbg.scala 102:71] + wire _T_15 = ~dmcontrol_reg[1]; // @[dbg.scala 105:25] + wire _T_17 = io_dmi_reg_addr == 7'h38; // @[dbg.scala 106:36] + wire _T_18 = _T_17 & io_dmi_reg_en; // @[dbg.scala 106:49] + wire _T_19 = _T_18 & io_dmi_reg_wr_en; // @[dbg.scala 106:65] + wire _T_20 = sb_state == 4'h0; // @[dbg.scala 106:96] + wire sbcs_wren = _T_19 & _T_20; // @[dbg.scala 106:84] + wire _T_22 = sbcs_wren & io_dmi_reg_wdata[22]; // @[dbg.scala 107:42] + wire _T_24 = _T_5 & io_dmi_reg_en; // @[dbg.scala 107:102] + wire _T_25 = io_dmi_reg_addr == 7'h39; // @[dbg.scala 108:23] + wire _T_26 = io_dmi_reg_addr == 7'h3c; // @[dbg.scala 108:55] + wire _T_27 = _T_25 | _T_26; // @[dbg.scala 108:36] + wire _T_28 = io_dmi_reg_addr == 7'h3d; // @[dbg.scala 108:87] + wire _T_29 = _T_27 | _T_28; // @[dbg.scala 108:68] + wire _T_30 = _T_24 & _T_29; // @[dbg.scala 107:118] + wire sbcs_sbbusyerror_wren = _T_22 | _T_30; // @[dbg.scala 107:66] + wire sbcs_sbbusyerror_din = ~_T_22; // @[dbg.scala 110:31] + reg temp_sbcs_22; // @[Reg.scala 27:20] + reg temp_sbcs_21; // @[Reg.scala 27:20] + reg temp_sbcs_20; // @[Reg.scala 27:20] + reg [4:0] temp_sbcs_19_15; // @[Reg.scala 27:20] + reg [2:0] temp_sbcs_14_12; // @[Reg.scala 27:20] + wire [19:0] _T_38 = {temp_sbcs_19_15,temp_sbcs_14_12,12'h40f}; // @[Cat.scala 29:58] + wire [11:0] _T_42 = {9'h40,temp_sbcs_22,temp_sbcs_21,temp_sbcs_20}; // @[Cat.scala 29:58] + wire _T_45 = sbcs_reg[19:17] == 3'h1; // @[dbg.scala 132:42] + wire _T_47 = _T_45 & sbaddress0_reg[0]; // @[dbg.scala 132:61] + wire _T_49 = sbcs_reg[19:17] == 3'h2; // @[dbg.scala 133:23] + wire _T_51 = |sbaddress0_reg[1:0]; // @[dbg.scala 133:65] + wire _T_52 = _T_49 & _T_51; // @[dbg.scala 133:42] + wire _T_53 = _T_47 | _T_52; // @[dbg.scala 132:81] + wire _T_55 = sbcs_reg[19:17] == 3'h3; // @[dbg.scala 134:23] + wire _T_57 = |sbaddress0_reg[2:0]; // @[dbg.scala 134:65] + wire _T_58 = _T_55 & _T_57; // @[dbg.scala 134:42] + wire sbcs_unaligned = _T_53 | _T_58; // @[dbg.scala 133:69] + wire sbcs_illegal_size = sbcs_reg[19]; // @[dbg.scala 136:35] + wire _T_60 = sbcs_reg[19:17] == 3'h0; // @[dbg.scala 137:51] + wire [3:0] _T_62 = _T_60 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_63 = _T_62 & 4'h1; // @[dbg.scala 137:64] + wire [3:0] _T_67 = _T_45 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_68 = _T_67 & 4'h2; // @[dbg.scala 137:122] + wire [3:0] _T_69 = _T_63 | _T_68; // @[dbg.scala 137:81] + wire [3:0] _T_73 = _T_49 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_74 = _T_73 & 4'h4; // @[dbg.scala 138:44] + wire [3:0] _T_75 = _T_69 | _T_74; // @[dbg.scala 137:139] + wire [3:0] _T_79 = _T_55 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_80 = _T_79 & 4'h8; // @[dbg.scala 138:102] + wire [3:0] sbaddress0_incr = _T_75 | _T_80; // @[dbg.scala 138:61] + wire _T_81 = io_dmi_reg_en & io_dmi_reg_wr_en; // @[dbg.scala 140:41] + wire sbdata0_reg_wren0 = _T_81 & _T_26; // @[dbg.scala 140:60] + wire _T_83 = sb_state == 4'h7; // @[dbg.scala 141:37] + wire _T_84 = _T_83 & sb_state_en; // @[dbg.scala 141:60] + wire _T_85 = ~sbcs_sberror_wren; // @[dbg.scala 141:76] + wire sbdata0_reg_wren1 = _T_84 & _T_85; // @[dbg.scala 141:74] + wire sbdata1_reg_wren0 = _T_81 & _T_28; // @[dbg.scala 143:60] + wire [31:0] _T_92 = sbdata0_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_93 = _T_92 & io_dmi_reg_wdata; // @[dbg.scala 146:49] + wire [31:0] _T_95 = sbdata0_reg_wren1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_97 = _T_95 & sb_bus_rdata[31:0]; // @[dbg.scala 147:33] + wire [31:0] _T_99 = sbdata1_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_100 = _T_99 & io_dmi_reg_wdata; // @[dbg.scala 149:49] + wire [31:0] _T_104 = _T_95 & sb_bus_rdata[63:32]; // @[dbg.scala 150:33] + wire rvclkhdr_2_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_2_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_2_io_en; // @[lib.scala 368:23] + wire rvclkhdr_2_io_scan_mode; // @[lib.scala 368:23] + reg [31:0] sbdata0_reg; // @[lib.scala 374:16] + wire rvclkhdr_3_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_3_io_en; // @[lib.scala 368:23] + wire rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23] + reg [31:0] sbdata1_reg; // @[lib.scala 374:16] + wire sbaddress0_reg_wren0 = _T_81 & _T_25; // @[dbg.scala 160:63] + wire [31:0] _T_108 = sbaddress0_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_109 = _T_108 & io_dmi_reg_wdata; // @[dbg.scala 162:59] + wire [31:0] _T_111 = sbaddress0_reg_wren1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_112 = {28'h0,sbaddress0_incr}; // @[Cat.scala 29:58] + wire [31:0] _T_114 = sbaddress0_reg + _T_112; // @[dbg.scala 163:54] + wire [31:0] _T_115 = _T_111 & _T_114; // @[dbg.scala 163:36] + wire rvclkhdr_4_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_4_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_4_io_en; // @[lib.scala 368:23] + wire rvclkhdr_4_io_scan_mode; // @[lib.scala 368:23] + reg [31:0] _T_116; // @[lib.scala 374:16] + wire sbreadonaddr_access = sbaddress0_reg_wren0 & sbcs_reg[20]; // @[dbg.scala 168:94] + wire _T_121 = ~io_dmi_reg_wr_en; // @[dbg.scala 169:45] + wire _T_122 = io_dmi_reg_en & _T_121; // @[dbg.scala 169:43] + wire _T_124 = _T_122 & _T_26; // @[dbg.scala 169:63] + wire sbreadondata_access = _T_124 & sbcs_reg[15]; // @[dbg.scala 169:95] + wire _T_128 = io_dmi_reg_addr == 7'h10; // @[dbg.scala 171:41] + wire _T_129 = _T_128 & io_dmi_reg_en; // @[dbg.scala 171:54] + wire dmcontrol_wren = _T_129 & io_dmi_reg_wr_en; // @[dbg.scala 171:70] + wire [3:0] _T_134 = {io_dmi_reg_wdata[31:30],io_dmi_reg_wdata[28],io_dmi_reg_wdata[1]}; // @[Cat.scala 29:58] + reg [3:0] dm_temp; // @[Reg.scala 27:20] + reg dm_temp_0; // @[Reg.scala 27:20] + wire [27:0] _T_141 = {26'h0,dm_temp[0],dm_temp_0}; // @[Cat.scala 29:58] + wire [3:0] _T_143 = {dm_temp[3:2],1'h0,dm_temp[1]}; // @[Cat.scala 29:58] + reg dmcontrol_wren_Q; // @[dbg.scala 186:12] + wire [1:0] _T_145 = dmstatus_havereset ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_147 = dmstatus_resumeack ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_149 = dmstatus_unavail ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_151 = dmstatus_running ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_153 = dmstatus_halted ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [11:0] _T_157 = {_T_151,_T_153,1'h1,7'h2}; // @[Cat.scala 29:58] + wire [19:0] _T_161 = {12'h0,_T_145,_T_147,2'h0,_T_149}; // @[Cat.scala 29:58] + wire _T_163 = dbg_state == 3'h6; // @[dbg.scala 191:44] + wire _T_164 = _T_163 & io_dec_tlu_resume_ack; // @[dbg.scala 191:66] + wire _T_166 = ~dmcontrol_reg[30]; // @[dbg.scala 191:113] + wire _T_167 = dmstatus_resumeack & _T_166; // @[dbg.scala 191:111] + wire dmstatus_resumeack_wren = _T_164 | _T_167; // @[dbg.scala 191:90] + wire _T_171 = _T_128 & io_dmi_reg_wdata[1]; // @[dbg.scala 193:63] + wire _T_172 = _T_171 & io_dmi_reg_en; // @[dbg.scala 193:85] + wire dmstatus_havereset_wren = _T_172 & io_dmi_reg_wr_en; // @[dbg.scala 193:101] + wire _T_175 = _T_128 & io_dmi_reg_wdata[28]; // @[dbg.scala 194:62] + wire _T_176 = _T_175 & io_dmi_reg_en; // @[dbg.scala 194:85] + wire dmstatus_havereset_rst = _T_176 & io_dmi_reg_wr_en; // @[dbg.scala 194:101] + wire _T_178 = ~reset; // @[dbg.scala 196:43] + wire _T_181 = dmstatus_unavail | dmstatus_halted; // @[dbg.scala 197:42] + reg _T_183; // @[Reg.scala 27:20] + wire _T_184 = ~io_dec_tlu_mpc_halted_only; // @[dbg.scala 203:37] + reg _T_186; // @[dbg.scala 203:12] + wire _T_187 = dmstatus_havereset_wren | dmstatus_havereset; // @[dbg.scala 207:16] + wire _T_188 = ~dmstatus_havereset_rst; // @[dbg.scala 207:72] + reg _T_190; // @[dbg.scala 207:12] + wire [31:0] haltsum0_reg = {31'h0,dmstatus_halted}; // @[Cat.scala 29:58] + wire [31:0] abstractcs_reg; + wire _T_192 = abstractcs_reg[12] & io_dmi_reg_en; // @[dbg.scala 213:50] + wire _T_193 = io_dmi_reg_addr == 7'h16; // @[dbg.scala 213:106] + wire _T_194 = io_dmi_reg_addr == 7'h17; // @[dbg.scala 213:138] + wire _T_195 = _T_193 | _T_194; // @[dbg.scala 213:119] + wire _T_196 = io_dmi_reg_wr_en & _T_195; // @[dbg.scala 213:86] + wire _T_197 = io_dmi_reg_addr == 7'h4; // @[dbg.scala 213:171] + wire _T_198 = _T_196 | _T_197; // @[dbg.scala 213:152] + wire abstractcs_error_sel0 = _T_192 & _T_198; // @[dbg.scala 213:66] + wire _T_201 = _T_81 & _T_194; // @[dbg.scala 214:64] + wire _T_203 = io_dmi_reg_wdata[31:24] == 8'h0; // @[dbg.scala 214:126] + wire _T_205 = io_dmi_reg_wdata[31:24] == 8'h2; // @[dbg.scala 214:163] + wire _T_206 = _T_203 | _T_205; // @[dbg.scala 214:135] + wire _T_207 = ~_T_206; // @[dbg.scala 214:98] + wire abstractcs_error_sel1 = _T_201 & _T_207; // @[dbg.scala 214:96] + wire abstractcs_error_sel2 = io_core_dbg_cmd_done & io_core_dbg_cmd_fail; // @[dbg.scala 215:52] + wire _T_212 = ~dmstatus_reg[9]; // @[dbg.scala 216:98] + wire abstractcs_error_sel3 = _T_201 & _T_212; // @[dbg.scala 216:96] + wire _T_214 = _T_194 & io_dmi_reg_en; // @[dbg.scala 217:61] + wire _T_215 = _T_214 & io_dmi_reg_wr_en; // @[dbg.scala 217:77] + wire _T_217 = io_dmi_reg_wdata[22:20] != 3'h2; // @[dbg.scala 218:32] + wire _T_221 = |data1_reg[1:0]; // @[dbg.scala 218:111] + wire _T_222 = _T_205 & _T_221; // @[dbg.scala 218:92] + wire _T_223 = _T_217 | _T_222; // @[dbg.scala 218:51] + wire abstractcs_error_sel4 = _T_215 & _T_223; // @[dbg.scala 217:96] + wire _T_225 = _T_193 & io_dmi_reg_en; // @[dbg.scala 220:61] + wire abstractcs_error_sel5 = _T_225 & io_dmi_reg_wr_en; // @[dbg.scala 220:77] + wire _T_226 = abstractcs_error_sel0 | abstractcs_error_sel1; // @[dbg.scala 221:54] + wire _T_227 = _T_226 | abstractcs_error_sel2; // @[dbg.scala 221:78] + wire _T_228 = _T_227 | abstractcs_error_sel3; // @[dbg.scala 221:102] + wire _T_229 = _T_228 | abstractcs_error_sel4; // @[dbg.scala 221:126] + wire abstractcs_error_selor = _T_229 | abstractcs_error_sel5; // @[dbg.scala 221:150] + wire [2:0] _T_231 = abstractcs_error_sel0 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_232 = _T_231 & 3'h1; // @[dbg.scala 222:62] + wire [2:0] _T_234 = abstractcs_error_sel1 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_235 = _T_234 & 3'h2; // @[dbg.scala 223:37] + wire [2:0] _T_236 = _T_232 | _T_235; // @[dbg.scala 222:79] + wire [2:0] _T_238 = abstractcs_error_sel2 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_239 = _T_238 & 3'h3; // @[dbg.scala 224:37] + wire [2:0] _T_240 = _T_236 | _T_239; // @[dbg.scala 223:54] + wire [2:0] _T_242 = abstractcs_error_sel3 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_243 = _T_242 & 3'h4; // @[dbg.scala 225:37] + wire [2:0] _T_244 = _T_240 | _T_243; // @[dbg.scala 224:54] + wire [2:0] _T_246 = abstractcs_error_sel4 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_248 = _T_244 | _T_246; // @[dbg.scala 225:54] + wire [2:0] _T_250 = abstractcs_error_sel5 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_252 = ~io_dmi_reg_wdata[10:8]; // @[dbg.scala 227:40] + wire [2:0] _T_253 = _T_250 & _T_252; // @[dbg.scala 227:37] + wire [2:0] _T_255 = _T_253 & abstractcs_reg[10:8]; // @[dbg.scala 227:75] + wire [2:0] _T_256 = _T_248 | _T_255; // @[dbg.scala 226:54] + wire _T_257 = ~abstractcs_error_selor; // @[dbg.scala 228:15] + wire [2:0] _T_259 = _T_257 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_261 = _T_259 & abstractcs_reg[10:8]; // @[dbg.scala 228:50] + reg abs_temp_12; // @[Reg.scala 27:20] + reg [2:0] abs_temp_10_8; // @[dbg.scala 235:12] + wire [10:0] _T_263 = {abs_temp_10_8,8'h2}; // @[Cat.scala 29:58] + wire [20:0] _T_265 = {19'h0,abs_temp_12,1'h0}; // @[Cat.scala 29:58] + wire _T_270 = dbg_state == 3'h2; // @[dbg.scala 240:100] + wire command_wren = _T_215 & _T_270; // @[dbg.scala 240:87] + wire [19:0] _T_274 = {3'h0,io_dmi_reg_wdata[16:0]}; // @[Cat.scala 29:58] + wire [11:0] _T_276 = {io_dmi_reg_wdata[31:24],1'h0,io_dmi_reg_wdata[22:20]}; // @[Cat.scala 29:58] + wire rvclkhdr_5_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_5_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_5_io_en; // @[lib.scala 368:23] + wire rvclkhdr_5_io_scan_mode; // @[lib.scala 368:23] + reg [31:0] command_reg; // @[lib.scala 374:16] + wire _T_279 = _T_81 & _T_197; // @[dbg.scala 246:58] + wire data0_reg_wren0 = _T_279 & _T_270; // @[dbg.scala 246:89] + wire _T_281 = dbg_state == 3'h4; // @[dbg.scala 247:59] + wire _T_282 = io_core_dbg_cmd_done & _T_281; // @[dbg.scala 247:46] + wire _T_284 = ~command_reg[16]; // @[dbg.scala 247:83] + wire data0_reg_wren1 = _T_282 & _T_284; // @[dbg.scala 247:81] + wire [31:0] _T_286 = data0_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_287 = _T_286 & io_dmi_reg_wdata; // @[dbg.scala 250:45] + wire [31:0] _T_289 = data0_reg_wren1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_290 = _T_289 & io_core_dbg_rddata; // @[dbg.scala 250:92] + wire rvclkhdr_6_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_6_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_6_io_en; // @[lib.scala 368:23] + wire rvclkhdr_6_io_scan_mode; // @[lib.scala 368:23] + reg [31:0] data0_reg; // @[lib.scala 374:16] + wire _T_292 = io_dmi_reg_addr == 7'h5; // @[dbg.scala 255:77] + wire _T_293 = _T_81 & _T_292; // @[dbg.scala 255:58] + wire data1_reg_wren = _T_293 & _T_270; // @[dbg.scala 255:89] + wire [31:0] _T_296 = data1_reg_wren ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire rvclkhdr_7_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_7_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_7_io_en; // @[lib.scala 368:23] + wire rvclkhdr_7_io_scan_mode; // @[lib.scala 368:23] + reg [31:0] _T_297; // @[lib.scala 374:16] + wire [2:0] dbg_nxtstate; + wire _T_298 = 3'h0 == dbg_state; // @[Conditional.scala 37:30] + wire _T_300 = dmstatus_reg[9] | io_dec_tlu_mpc_halted_only; // @[dbg.scala 270:43] + wire [2:0] _T_301 = _T_300 ? 3'h2 : 3'h1; // @[dbg.scala 270:26] + wire _T_303 = ~io_dec_tlu_debug_mode; // @[dbg.scala 271:45] + wire _T_304 = dmcontrol_reg[31] & _T_303; // @[dbg.scala 271:43] + wire _T_306 = _T_304 | dmstatus_reg[9]; // @[dbg.scala 271:69] + wire _T_307 = _T_306 | io_dec_tlu_mpc_halted_only; // @[dbg.scala 271:87] + wire _T_310 = _T_307 & _T_15; // @[dbg.scala 271:117] + wire _T_314 = dmcontrol_reg[31] & _T_15; // @[dbg.scala 272:45] + wire _T_316 = 3'h1 == dbg_state; // @[Conditional.scala 37:30] + wire [2:0] _T_318 = dmcontrol_reg[1] ? 3'h0 : 3'h2; // @[dbg.scala 275:26] + wire _T_321 = dmstatus_reg[9] | dmcontrol_reg[1]; // @[dbg.scala 276:39] + wire _T_323 = dmcontrol_wren_Q & dmcontrol_reg[31]; // @[dbg.scala 277:44] + wire _T_326 = _T_323 & _T_15; // @[dbg.scala 277:64] + wire _T_328 = 3'h2 == dbg_state; // @[Conditional.scala 37:30] + wire _T_332 = dmstatus_reg[9] & _T_15; // @[dbg.scala 280:43] + wire _T_335 = ~dmcontrol_reg[31]; // @[dbg.scala 281:33] + wire _T_336 = dmcontrol_reg[30] & _T_335; // @[dbg.scala 281:31] + wire [2:0] _T_337 = _T_336 ? 3'h6 : 3'h3; // @[dbg.scala 281:12] + wire [2:0] _T_339 = dmcontrol_reg[31] ? 3'h1 : 3'h0; // @[dbg.scala 282:12] + wire [2:0] _T_340 = _T_332 ? _T_337 : _T_339; // @[dbg.scala 280:26] + wire _T_343 = dmstatus_reg[9] & dmcontrol_reg[30]; // @[dbg.scala 283:39] + wire _T_346 = _T_343 & _T_335; // @[dbg.scala 283:59] + wire _T_347 = _T_346 & dmcontrol_wren_Q; // @[dbg.scala 283:80] + wire _T_348 = _T_347 | command_wren; // @[dbg.scala 283:99] + wire _T_350 = _T_348 | dmcontrol_reg[1]; // @[dbg.scala 283:114] + wire _T_353 = ~_T_300; // @[dbg.scala 284:28] + wire _T_354 = _T_350 | _T_353; // @[dbg.scala 284:26] + wire _T_355 = dbg_nxtstate == 3'h3; // @[dbg.scala 285:60] + wire _T_356 = dbg_state_en & _T_355; // @[dbg.scala 285:44] + wire _T_357 = dbg_nxtstate == 3'h6; // @[dbg.scala 287:58] + wire _T_358 = dbg_state_en & _T_357; // @[dbg.scala 287:42] + wire _T_366 = 3'h3 == dbg_state; // @[Conditional.scala 37:30] + wire _T_369 = |abstractcs_reg[10:8]; // @[dbg.scala 291:85] + wire [2:0] _T_370 = _T_369 ? 3'h5 : 3'h4; // @[dbg.scala 291:62] + wire [2:0] _T_371 = dmcontrol_reg[1] ? 3'h0 : _T_370; // @[dbg.scala 291:26] + wire _T_374 = io_dbg_dec_dbg_ib_dbg_cmd_valid | _T_369; // @[dbg.scala 292:55] + wire _T_376 = _T_374 | dmcontrol_reg[1]; // @[dbg.scala 292:83] + wire _T_383 = 3'h4 == dbg_state; // @[Conditional.scala 37:30] + wire [2:0] _T_385 = dmcontrol_reg[1] ? 3'h0 : 3'h5; // @[dbg.scala 296:26] + wire _T_387 = io_core_dbg_cmd_done | dmcontrol_reg[1]; // @[dbg.scala 297:44] + wire _T_394 = 3'h5 == dbg_state; // @[Conditional.scala 37:30] + wire _T_403 = 3'h6 == dbg_state; // @[Conditional.scala 37:30] + wire _T_406 = dmstatus_reg[17] | dmcontrol_reg[1]; // @[dbg.scala 309:40] + wire _GEN_10 = _T_403 & _T_406; // @[Conditional.scala 39:67] + wire _GEN_11 = _T_403 & _T_326; // @[Conditional.scala 39:67] + wire [2:0] _GEN_12 = _T_394 ? _T_318 : 3'h0; // @[Conditional.scala 39:67] + wire _GEN_13 = _T_394 | _GEN_10; // @[Conditional.scala 39:67] + wire _GEN_14 = _T_394 & dbg_state_en; // @[Conditional.scala 39:67] + wire _GEN_16 = _T_394 ? _T_326 : _GEN_11; // @[Conditional.scala 39:67] + wire [2:0] _GEN_17 = _T_383 ? _T_385 : _GEN_12; // @[Conditional.scala 39:67] + wire _GEN_18 = _T_383 ? _T_387 : _GEN_13; // @[Conditional.scala 39:67] + wire _GEN_19 = _T_383 ? _T_326 : _GEN_16; // @[Conditional.scala 39:67] + wire _GEN_20 = _T_383 ? 1'h0 : _GEN_14; // @[Conditional.scala 39:67] + wire [2:0] _GEN_22 = _T_366 ? _T_371 : _GEN_17; // @[Conditional.scala 39:67] + wire _GEN_23 = _T_366 ? _T_376 : _GEN_18; // @[Conditional.scala 39:67] + wire _GEN_24 = _T_366 ? _T_326 : _GEN_19; // @[Conditional.scala 39:67] + wire _GEN_25 = _T_366 ? 1'h0 : _GEN_20; // @[Conditional.scala 39:67] + wire [2:0] _GEN_27 = _T_328 ? _T_340 : _GEN_22; // @[Conditional.scala 39:67] + wire _GEN_28 = _T_328 ? _T_354 : _GEN_23; // @[Conditional.scala 39:67] + wire _GEN_29 = _T_328 ? _T_356 : _GEN_25; // @[Conditional.scala 39:67] + wire _GEN_31 = _T_328 & _T_358; // @[Conditional.scala 39:67] + wire _GEN_32 = _T_328 ? _T_326 : _GEN_24; // @[Conditional.scala 39:67] + wire [2:0] _GEN_33 = _T_316 ? _T_318 : _GEN_27; // @[Conditional.scala 39:67] + wire _GEN_34 = _T_316 ? _T_321 : _GEN_28; // @[Conditional.scala 39:67] + wire _GEN_35 = _T_316 ? _T_326 : _GEN_32; // @[Conditional.scala 39:67] + wire _GEN_36 = _T_316 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67] + wire _GEN_38 = _T_316 ? 1'h0 : _GEN_31; // @[Conditional.scala 39:67] + wire [31:0] _T_415 = _T_197 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_416 = _T_415 & data0_reg; // @[dbg.scala 313:71] + wire [31:0] _T_419 = _T_292 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_420 = _T_419 & data1_reg; // @[dbg.scala 313:122] + wire [31:0] _T_421 = _T_416 | _T_420; // @[dbg.scala 313:83] + wire [31:0] _T_424 = _T_128 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_425 = _T_424 & dmcontrol_reg; // @[dbg.scala 314:43] + wire [31:0] _T_426 = _T_421 | _T_425; // @[dbg.scala 313:134] + wire _T_427 = io_dmi_reg_addr == 7'h11; // @[dbg.scala 314:86] + wire [31:0] _T_429 = _T_427 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_430 = _T_429 & dmstatus_reg; // @[dbg.scala 314:99] + wire [31:0] _T_431 = _T_426 | _T_430; // @[dbg.scala 314:59] + wire [31:0] _T_434 = _T_193 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_435 = _T_434 & abstractcs_reg; // @[dbg.scala 315:43] + wire [31:0] _T_436 = _T_431 | _T_435; // @[dbg.scala 314:114] + wire [31:0] _T_439 = _T_194 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_440 = _T_439 & command_reg; // @[dbg.scala 315:100] + wire [31:0] _T_441 = _T_436 | _T_440; // @[dbg.scala 315:60] + wire _T_442 = io_dmi_reg_addr == 7'h40; // @[dbg.scala 316:30] + wire [31:0] _T_444 = _T_442 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_445 = _T_444 & haltsum0_reg; // @[dbg.scala 316:43] + wire [31:0] _T_446 = _T_441 | _T_445; // @[dbg.scala 315:114] + wire [31:0] _T_449 = _T_17 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_450 = _T_449 & sbcs_reg; // @[dbg.scala 316:98] + wire [31:0] _T_451 = _T_446 | _T_450; // @[dbg.scala 316:58] + wire [31:0] _T_454 = _T_25 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_455 = _T_454 & sbaddress0_reg; // @[dbg.scala 317:43] + wire [31:0] _T_456 = _T_451 | _T_455; // @[dbg.scala 316:109] + wire [31:0] _T_459 = _T_26 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_460 = _T_459 & sbdata0_reg; // @[dbg.scala 317:100] + wire [31:0] _T_461 = _T_456 | _T_460; // @[dbg.scala 317:60] + wire [31:0] _T_464 = _T_28 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_465 = _T_464 & sbdata1_reg; // @[dbg.scala 318:43] + wire [31:0] dmi_reg_rdata_din = _T_461 | _T_465; // @[dbg.scala 317:114] + reg [2:0] _T_466; // @[Reg.scala 27:20] + reg [31:0] _T_467; // @[Reg.scala 27:20] + wire _T_469 = command_reg[31:24] == 8'h2; // @[dbg.scala 329:62] + wire [31:0] _T_471 = {data1_reg[31:2],2'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_473 = {20'h0,command_reg[11:0]}; // @[Cat.scala 29:58] + wire _T_476 = dbg_state == 3'h3; // @[dbg.scala 331:50] + wire _T_479 = ~_T_369; // @[dbg.scala 331:75] + wire _T_480 = _T_476 & _T_479; // @[dbg.scala 331:73] + wire _T_488 = command_reg[15:12] == 4'h0; // @[dbg.scala 333:122] + wire [1:0] _T_489 = {1'h0,_T_488}; // @[Cat.scala 29:58] + wire _T_500 = 4'h0 == sb_state; // @[Conditional.scala 37:30] + wire _T_502 = sbdata0_reg_wren0 | sbreadondata_access; // @[dbg.scala 348:39] + wire _T_503 = _T_502 | sbreadonaddr_access; // @[dbg.scala 348:61] + wire _T_505 = |io_dmi_reg_wdata[14:12]; // @[dbg.scala 351:65] + wire _T_506 = sbcs_wren & _T_505; // @[dbg.scala 351:38] + wire [2:0] _T_508 = ~io_dmi_reg_wdata[14:12]; // @[dbg.scala 352:27] + wire [2:0] _T_510 = _T_508 & sbcs_reg[14:12]; // @[dbg.scala 352:53] + wire _T_511 = 4'h1 == sb_state; // @[Conditional.scala 37:30] + wire _T_512 = sbcs_unaligned | sbcs_illegal_size; // @[dbg.scala 355:41] + wire _T_514 = io_dbg_bus_clk_en | sbcs_unaligned; // @[dbg.scala 356:40] + wire _T_515 = _T_514 | sbcs_illegal_size; // @[dbg.scala 356:57] + wire _T_518 = 4'h2 == sb_state; // @[Conditional.scala 37:30] + wire _T_525 = 4'h3 == sb_state; // @[Conditional.scala 37:30] + wire _T_526 = sb_bus_cmd_read & io_dbg_bus_clk_en; // @[dbg.scala 368:38] + wire _T_527 = 4'h4 == sb_state; // @[Conditional.scala 37:30] + wire _T_528 = sb_bus_cmd_write_addr & sb_bus_cmd_write_data; // @[dbg.scala 371:48] + wire _T_531 = sb_bus_cmd_write_addr | sb_bus_cmd_write_data; // @[dbg.scala 372:45] + wire _T_532 = _T_531 & io_dbg_bus_clk_en; // @[dbg.scala 372:70] + wire _T_533 = 4'h5 == sb_state; // @[Conditional.scala 37:30] + wire _T_534 = sb_bus_cmd_write_addr & io_dbg_bus_clk_en; // @[dbg.scala 376:44] + wire _T_535 = 4'h6 == sb_state; // @[Conditional.scala 37:30] + wire _T_536 = sb_bus_cmd_write_data & io_dbg_bus_clk_en; // @[dbg.scala 380:44] + wire _T_537 = 4'h7 == sb_state; // @[Conditional.scala 37:30] + wire _T_538 = sb_bus_rsp_read & io_dbg_bus_clk_en; // @[dbg.scala 384:38] + wire _T_539 = sb_state_en & sb_bus_rsp_error; // @[dbg.scala 385:40] + wire _T_540 = 4'h8 == sb_state; // @[Conditional.scala 37:30] + wire _T_541 = sb_bus_rsp_write & io_dbg_bus_clk_en; // @[dbg.scala 390:39] + wire _T_543 = 4'h9 == sb_state; // @[Conditional.scala 37:30] + wire _GEN_50 = _T_543 & sbcs_reg[16]; // @[Conditional.scala 39:67] + wire _GEN_52 = _T_540 ? _T_541 : _T_543; // @[Conditional.scala 39:67] + wire _GEN_53 = _T_540 & _T_539; // @[Conditional.scala 39:67] + wire _GEN_55 = _T_540 ? 1'h0 : _T_543; // @[Conditional.scala 39:67] + wire _GEN_57 = _T_540 ? 1'h0 : _GEN_50; // @[Conditional.scala 39:67] + wire _GEN_59 = _T_537 ? _T_538 : _GEN_52; // @[Conditional.scala 39:67] + wire _GEN_60 = _T_537 ? _T_539 : _GEN_53; // @[Conditional.scala 39:67] + wire _GEN_62 = _T_537 ? 1'h0 : _GEN_55; // @[Conditional.scala 39:67] + wire _GEN_64 = _T_537 ? 1'h0 : _GEN_57; // @[Conditional.scala 39:67] + wire _GEN_66 = _T_535 ? _T_536 : _GEN_59; // @[Conditional.scala 39:67] + wire _GEN_67 = _T_535 ? 1'h0 : _GEN_60; // @[Conditional.scala 39:67] + wire _GEN_69 = _T_535 ? 1'h0 : _GEN_62; // @[Conditional.scala 39:67] + wire _GEN_71 = _T_535 ? 1'h0 : _GEN_64; // @[Conditional.scala 39:67] + wire _GEN_73 = _T_533 ? _T_534 : _GEN_66; // @[Conditional.scala 39:67] + wire _GEN_74 = _T_533 ? 1'h0 : _GEN_67; // @[Conditional.scala 39:67] + wire _GEN_76 = _T_533 ? 1'h0 : _GEN_69; // @[Conditional.scala 39:67] + wire _GEN_78 = _T_533 ? 1'h0 : _GEN_71; // @[Conditional.scala 39:67] + wire _GEN_80 = _T_527 ? _T_532 : _GEN_73; // @[Conditional.scala 39:67] + wire _GEN_81 = _T_527 ? 1'h0 : _GEN_74; // @[Conditional.scala 39:67] + wire _GEN_83 = _T_527 ? 1'h0 : _GEN_76; // @[Conditional.scala 39:67] + wire _GEN_85 = _T_527 ? 1'h0 : _GEN_78; // @[Conditional.scala 39:67] + wire _GEN_87 = _T_525 ? _T_526 : _GEN_80; // @[Conditional.scala 39:67] + wire _GEN_88 = _T_525 ? 1'h0 : _GEN_81; // @[Conditional.scala 39:67] + wire _GEN_90 = _T_525 ? 1'h0 : _GEN_83; // @[Conditional.scala 39:67] + wire _GEN_92 = _T_525 ? 1'h0 : _GEN_85; // @[Conditional.scala 39:67] + wire _GEN_94 = _T_518 ? _T_515 : _GEN_87; // @[Conditional.scala 39:67] + wire _GEN_95 = _T_518 ? _T_512 : _GEN_88; // @[Conditional.scala 39:67] + wire _GEN_97 = _T_518 ? 1'h0 : _GEN_90; // @[Conditional.scala 39:67] + wire _GEN_99 = _T_518 ? 1'h0 : _GEN_92; // @[Conditional.scala 39:67] + wire _GEN_101 = _T_511 ? _T_515 : _GEN_94; // @[Conditional.scala 39:67] + wire _GEN_102 = _T_511 ? _T_512 : _GEN_95; // @[Conditional.scala 39:67] + wire _GEN_104 = _T_511 ? 1'h0 : _GEN_97; // @[Conditional.scala 39:67] + wire _GEN_106 = _T_511 ? 1'h0 : _GEN_99; // @[Conditional.scala 39:67] + reg [3:0] _T_545; // @[Reg.scala 27:20] + wire _T_552 = |io_sb_axi_r_bits_resp; // @[dbg.scala 411:69] + wire _T_553 = sb_bus_rsp_read & _T_552; // @[dbg.scala 411:39] + wire _T_555 = |io_sb_axi_b_bits_resp; // @[dbg.scala 411:122] + wire _T_556 = sb_bus_rsp_write & _T_555; // @[dbg.scala 411:92] + wire _T_558 = sb_state == 4'h4; // @[dbg.scala 412:36] + wire _T_559 = sb_state == 4'h5; // @[dbg.scala 412:71] + wire _T_565 = sb_state == 4'h6; // @[dbg.scala 423:70] + wire [63:0] _T_571 = _T_60 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12] + wire [63:0] _T_575 = {sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0]}; // @[Cat.scala 29:58] + wire [63:0] _T_576 = _T_571 & _T_575; // @[dbg.scala 424:65] + wire [63:0] _T_580 = _T_45 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12] + wire [63:0] _T_583 = {sbdata0_reg[15:0],sbdata0_reg[15:0],sbdata0_reg[15:0],sbdata0_reg[15:0]}; // @[Cat.scala 29:58] + wire [63:0] _T_584 = _T_580 & _T_583; // @[dbg.scala 424:138] + wire [63:0] _T_585 = _T_576 | _T_584; // @[dbg.scala 424:96] + wire [63:0] _T_589 = _T_49 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12] + wire [63:0] _T_591 = {sbdata0_reg,sbdata0_reg}; // @[Cat.scala 29:58] + wire [63:0] _T_592 = _T_589 & _T_591; // @[dbg.scala 425:45] + wire [63:0] _T_593 = _T_585 | _T_592; // @[dbg.scala 424:168] + wire [63:0] _T_597 = _T_55 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12] + wire [63:0] _T_600 = {sbdata1_reg,sbdata0_reg}; // @[Cat.scala 29:58] + wire [63:0] _T_601 = _T_597 & _T_600; // @[dbg.scala 425:119] + wire [7:0] _T_606 = _T_60 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [14:0] _T_608 = 15'h1 << sbaddress0_reg[2:0]; // @[dbg.scala 427:82] + wire [14:0] _GEN_115 = {{7'd0}, _T_606}; // @[dbg.scala 427:67] + wire [14:0] _T_609 = _GEN_115 & _T_608; // @[dbg.scala 427:67] + wire [7:0] _T_613 = _T_45 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_615 = {sbaddress0_reg[2:1],1'h0}; // @[Cat.scala 29:58] + wire [14:0] _T_616 = 15'h3 << _T_615; // @[dbg.scala 428:59] + wire [14:0] _GEN_116 = {{7'd0}, _T_613}; // @[dbg.scala 428:44] + wire [14:0] _T_617 = _GEN_116 & _T_616; // @[dbg.scala 428:44] + wire [14:0] _T_618 = _T_609 | _T_617; // @[dbg.scala 427:107] + wire [7:0] _T_622 = _T_49 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_624 = {sbaddress0_reg[2],2'h0}; // @[Cat.scala 29:58] + wire [14:0] _T_625 = 15'hf << _T_624; // @[dbg.scala 429:59] + wire [14:0] _GEN_117 = {{7'd0}, _T_622}; // @[dbg.scala 429:44] + wire [14:0] _T_626 = _GEN_117 & _T_625; // @[dbg.scala 429:44] + wire [14:0] _T_627 = _T_618 | _T_626; // @[dbg.scala 428:97] + wire [7:0] _T_631 = _T_55 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [14:0] _GEN_118 = {{7'd0}, _T_631}; // @[dbg.scala 429:100] + wire [14:0] _T_633 = _T_627 | _GEN_118; // @[dbg.scala 429:100] + wire [3:0] _GEN_119 = {{1'd0}, sbaddress0_reg[2:0]}; // @[dbg.scala 446:99] + wire [6:0] _T_644 = 4'h8 * _GEN_119; // @[dbg.scala 446:99] + wire [63:0] _T_645 = io_sb_axi_r_bits_data >> _T_644; // @[dbg.scala 446:92] + wire [63:0] _T_646 = _T_645 & 64'hff; // @[dbg.scala 446:123] + wire [63:0] _T_647 = _T_571 & _T_646; // @[dbg.scala 446:59] + wire [4:0] _GEN_120 = {{3'd0}, sbaddress0_reg[2:1]}; // @[dbg.scala 447:86] + wire [6:0] _T_654 = 5'h10 * _GEN_120; // @[dbg.scala 447:86] + wire [63:0] _T_655 = io_sb_axi_r_bits_data >> _T_654; // @[dbg.scala 447:78] + wire [63:0] _T_656 = _T_655 & 64'hffff; // @[dbg.scala 447:110] + wire [63:0] _T_657 = _T_580 & _T_656; // @[dbg.scala 447:45] + wire [63:0] _T_658 = _T_647 | _T_657; // @[dbg.scala 446:140] + wire [5:0] _GEN_121 = {{5'd0}, sbaddress0_reg[2]}; // @[dbg.scala 448:86] + wire [6:0] _T_665 = 6'h20 * _GEN_121; // @[dbg.scala 448:86] + wire [63:0] _T_666 = io_sb_axi_r_bits_data >> _T_665; // @[dbg.scala 448:78] + wire [63:0] _T_667 = _T_666 & 64'hffffffff; // @[dbg.scala 448:107] + wire [63:0] _T_668 = _T_589 & _T_667; // @[dbg.scala 448:45] + wire [63:0] _T_669 = _T_658 | _T_668; // @[dbg.scala 447:129] + wire [63:0] _T_675 = _T_597 & io_sb_axi_r_bits_data; // @[dbg.scala 449:45] + rvclkhdr rvclkhdr ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) + ); + rvclkhdr rvclkhdr_1 ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_1_io_l1clk), + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en), + .io_scan_mode(rvclkhdr_1_io_scan_mode) + ); + rvclkhdr rvclkhdr_2 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_2_io_l1clk), + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en), + .io_scan_mode(rvclkhdr_2_io_scan_mode) + ); + rvclkhdr rvclkhdr_3 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_3_io_l1clk), + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en), + .io_scan_mode(rvclkhdr_3_io_scan_mode) + ); + rvclkhdr rvclkhdr_4 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_4_io_l1clk), + .io_clk(rvclkhdr_4_io_clk), + .io_en(rvclkhdr_4_io_en), + .io_scan_mode(rvclkhdr_4_io_scan_mode) + ); + rvclkhdr rvclkhdr_5 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_5_io_l1clk), + .io_clk(rvclkhdr_5_io_clk), + .io_en(rvclkhdr_5_io_en), + .io_scan_mode(rvclkhdr_5_io_scan_mode) + ); + rvclkhdr rvclkhdr_6 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_6_io_l1clk), + .io_clk(rvclkhdr_6_io_clk), + .io_en(rvclkhdr_6_io_en), + .io_scan_mode(rvclkhdr_6_io_scan_mode) + ); + rvclkhdr rvclkhdr_7 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_7_io_l1clk), + .io_clk(rvclkhdr_7_io_clk), + .io_en(rvclkhdr_7_io_en), + .io_scan_mode(rvclkhdr_7_io_scan_mode) + ); + assign io_dbg_cmd_size = command_reg[21:20]; // @[dbg.scala 334:19] + assign io_dbg_core_rst_l = ~dmcontrol_reg[1]; // @[dbg.scala 105:21] + assign io_dbg_halt_req = _T_298 ? _T_314 : _GEN_35; // @[dbg.scala 266:19 dbg.scala 272:23 dbg.scala 277:23 dbg.scala 288:23 dbg.scala 293:23 dbg.scala 298:23 dbg.scala 305:23 dbg.scala 310:23] + assign io_dbg_resume_req = _T_298 ? 1'h0 : _GEN_38; // @[dbg.scala 267:21 dbg.scala 287:25] + assign io_dmi_reg_rdata = _T_467; // @[dbg.scala 325:20] + assign io_sb_axi_aw_valid = _T_558 | _T_559; // @[dbg.scala 412:22] + assign io_sb_axi_aw_bits_id = 1'h0; // @[dbg.scala 414:24] + assign io_sb_axi_aw_bits_addr = sbaddress0_reg; // @[dbg.scala 413:26] + assign io_sb_axi_aw_bits_region = sbaddress0_reg[31:28]; // @[dbg.scala 418:28] + assign io_sb_axi_aw_bits_len = 8'h0; // @[dbg.scala 419:25] + assign io_sb_axi_aw_bits_size = sbcs_reg[19:17]; // @[dbg.scala 415:26] + assign io_sb_axi_aw_bits_burst = 2'h1; // @[dbg.scala 420:27] + assign io_sb_axi_aw_bits_lock = 1'h0; // @[dbg.scala 422:26] + assign io_sb_axi_aw_bits_cache = 4'hf; // @[dbg.scala 417:27] + assign io_sb_axi_aw_bits_prot = 3'h0; // @[dbg.scala 416:26] + assign io_sb_axi_aw_bits_qos = 4'h0; // @[dbg.scala 421:25] + assign io_sb_axi_w_valid = _T_558 | _T_565; // @[dbg.scala 423:21] + assign io_sb_axi_w_bits_data = _T_593 | _T_601; // @[dbg.scala 424:25] + assign io_sb_axi_w_bits_strb = _T_633[7:0]; // @[dbg.scala 427:25] + assign io_sb_axi_w_bits_last = 1'h1; // @[dbg.scala 432:25] + assign io_sb_axi_b_ready = 1'h1; // @[dbg.scala 444:21] + assign io_sb_axi_ar_valid = sb_state == 4'h3; // @[dbg.scala 433:22] + assign io_sb_axi_ar_bits_id = 1'h0; // @[dbg.scala 435:24] + assign io_sb_axi_ar_bits_addr = sbaddress0_reg; // @[dbg.scala 434:26] + assign io_sb_axi_ar_bits_region = sbaddress0_reg[31:28]; // @[dbg.scala 439:28] + assign io_sb_axi_ar_bits_len = 8'h0; // @[dbg.scala 440:25] + assign io_sb_axi_ar_bits_size = sbcs_reg[19:17]; // @[dbg.scala 436:26] + assign io_sb_axi_ar_bits_burst = 2'h1; // @[dbg.scala 441:27] + assign io_sb_axi_ar_bits_lock = 1'h0; // @[dbg.scala 443:26] + assign io_sb_axi_ar_bits_cache = 4'h0; // @[dbg.scala 438:27] + assign io_sb_axi_ar_bits_prot = 3'h0; // @[dbg.scala 437:26] + assign io_sb_axi_ar_bits_qos = 4'h0; // @[dbg.scala 442:25] + assign io_sb_axi_r_ready = 1'h1; // @[dbg.scala 445:21] + assign io_dbg_dec_dbg_ib_dbg_cmd_valid = _T_480 & io_dbg_dma_io_dma_dbg_ready; // @[dbg.scala 331:35] + assign io_dbg_dec_dbg_ib_dbg_cmd_write = command_reg[16]; // @[dbg.scala 332:35] + assign io_dbg_dec_dbg_ib_dbg_cmd_type = _T_469 ? 2'h2 : _T_489; // @[dbg.scala 333:34] + assign io_dbg_dec_dbg_ib_dbg_cmd_addr = _T_469 ? _T_471 : _T_473; // @[dbg.scala 329:34] + assign io_dbg_dec_dbg_dctl_dbg_cmd_wrdata = data0_reg; // @[dbg.scala 330:38] + assign io_dbg_dma_dbg_ib_dbg_cmd_valid = io_dbg_dec_dbg_ib_dbg_cmd_valid; // @[dbg.scala 454:39] + assign io_dbg_dma_dbg_ib_dbg_cmd_write = io_dbg_dec_dbg_ib_dbg_cmd_write; // @[dbg.scala 455:39] + assign io_dbg_dma_dbg_ib_dbg_cmd_type = io_dbg_dec_dbg_ib_dbg_cmd_type; // @[dbg.scala 456:39] + assign io_dbg_dma_dbg_ib_dbg_cmd_addr = io_dbg_dec_dbg_ib_dbg_cmd_addr; // @[dbg.scala 452:39] + assign io_dbg_dma_dbg_dctl_dbg_cmd_wrdata = io_dbg_dec_dbg_dctl_dbg_cmd_wrdata; // @[dbg.scala 453:39] + assign io_dbg_dma_io_dbg_dma_bubble = _T_480 | _T_281; // @[dbg.scala 335:32] + assign dbg_state = _T_466; // @[dbg.scala 320:13] + assign dbg_state_en = _T_298 ? _T_310 : _GEN_34; // @[dbg.scala 263:16 dbg.scala 271:20 dbg.scala 276:20 dbg.scala 283:20 dbg.scala 292:20 dbg.scala 297:20 dbg.scala 302:20 dbg.scala 309:20] + assign sb_state = _T_545; // @[dbg.scala 402:12] + assign sb_state_en = _T_500 ? _T_503 : _GEN_101; // @[dbg.scala 348:19 dbg.scala 356:19 dbg.scala 362:19 dbg.scala 368:19 dbg.scala 372:19 dbg.scala 376:19 dbg.scala 380:19 dbg.scala 384:19 dbg.scala 390:19 dbg.scala 396:19] + assign dmcontrol_reg = {_T_143,_T_141}; // @[dbg.scala 183:17] + assign sbaddress0_reg = _T_116; // @[dbg.scala 164:18] + assign sbcs_sbbusy_wren = _T_500 ? sb_state_en : _GEN_104; // @[dbg.scala 340:20 dbg.scala 349:24 dbg.scala 397:24] + assign sbcs_sberror_wren = _T_500 ? _T_506 : _GEN_102; // @[dbg.scala 342:21 dbg.scala 351:25 dbg.scala 357:25 dbg.scala 363:25 dbg.scala 385:25 dbg.scala 391:25] + assign sb_bus_rdata = _T_669 | _T_675; // @[dbg.scala 446:16] + assign sbaddress0_reg_wren1 = _T_500 ? 1'h0 : _GEN_106; // @[dbg.scala 344:24 dbg.scala 399:28] + assign dmstatus_reg = {_T_161,_T_157}; // @[dbg.scala 189:16] + assign dmstatus_havereset = _T_190; // @[dbg.scala 206:22] + assign dmstatus_resumeack = _T_183; // @[dbg.scala 198:22] + assign dmstatus_unavail = dmcontrol_reg[1] | _T_178; // @[dbg.scala 196:20] + assign dmstatus_running = ~_T_181; // @[dbg.scala 197:20] + assign dmstatus_halted = _T_186; // @[dbg.scala 202:19] + assign abstractcs_busy_wren = _T_298 ? 1'h0 : _GEN_36; // @[dbg.scala 264:24 dbg.scala 285:28 dbg.scala 303:28] + assign sb_bus_cmd_read = io_sb_axi_ar_valid & io_sb_axi_ar_ready; // @[dbg.scala 406:19] + assign sb_bus_cmd_write_addr = io_sb_axi_aw_valid & io_sb_axi_aw_ready; // @[dbg.scala 407:25] + assign sb_bus_cmd_write_data = io_sb_axi_w_valid & io_sb_axi_w_ready; // @[dbg.scala 408:25] + assign sb_bus_rsp_read = io_sb_axi_r_valid & io_sb_axi_r_ready; // @[dbg.scala 409:19] + assign sb_bus_rsp_error = _T_553 | _T_556; // @[dbg.scala 411:20] + assign sb_bus_rsp_write = io_sb_axi_b_valid & io_sb_axi_b_ready; // @[dbg.scala 410:20] + assign sbcs_sbbusy_din = 4'h0 == sb_state; // @[dbg.scala 341:19 dbg.scala 350:23 dbg.scala 398:23] + assign data1_reg = _T_297; // @[dbg.scala 257:13] + assign sbcs_reg = {_T_42,_T_38}; // @[dbg.scala 130:12] + assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_io_en = _T_3 | io_clk_override; // @[lib.scala 345:16] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_1_io_en = _T_6 | io_clk_override; // @[lib.scala 345:16] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_2_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_2_io_en = sbdata0_reg_wren0 | sbdata0_reg_wren1; // @[lib.scala 371:17] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_3_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_3_io_en = sbdata1_reg_wren0 | sbdata0_reg_wren1; // @[lib.scala 371:17] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_4_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_4_io_en = sbaddress0_reg_wren0 | sbaddress0_reg_wren1; // @[lib.scala 371:17] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign abstractcs_reg = {_T_265,_T_263}; // @[dbg.scala 238:18] + assign rvclkhdr_5_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_5_io_en = _T_215 & _T_270; // @[lib.scala 371:17] + assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_6_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_6_io_en = data0_reg_wren0 | data0_reg_wren1; // @[lib.scala 371:17] + assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_7_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_7_io_en = _T_293 & _T_270; // @[lib.scala 371:17] + assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign dbg_nxtstate = _T_298 ? _T_301 : _GEN_33; // @[dbg.scala 262:16 dbg.scala 270:20 dbg.scala 275:20 dbg.scala 280:20 dbg.scala 291:20 dbg.scala 296:20 dbg.scala 301:20 dbg.scala 308:20] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + temp_sbcs_22 = _RAND_0[0:0]; + _RAND_1 = {1{`RANDOM}}; + temp_sbcs_21 = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + temp_sbcs_20 = _RAND_2[0:0]; + _RAND_3 = {1{`RANDOM}}; + temp_sbcs_19_15 = _RAND_3[4:0]; + _RAND_4 = {1{`RANDOM}}; + temp_sbcs_14_12 = _RAND_4[2:0]; + _RAND_5 = {1{`RANDOM}}; + sbdata0_reg = _RAND_5[31:0]; + _RAND_6 = {1{`RANDOM}}; + sbdata1_reg = _RAND_6[31:0]; + _RAND_7 = {1{`RANDOM}}; + _T_116 = _RAND_7[31:0]; + _RAND_8 = {1{`RANDOM}}; + dm_temp = _RAND_8[3:0]; + _RAND_9 = {1{`RANDOM}}; + dm_temp_0 = _RAND_9[0:0]; + _RAND_10 = {1{`RANDOM}}; + dmcontrol_wren_Q = _RAND_10[0:0]; + _RAND_11 = {1{`RANDOM}}; + _T_183 = _RAND_11[0:0]; + _RAND_12 = {1{`RANDOM}}; + _T_186 = _RAND_12[0:0]; + _RAND_13 = {1{`RANDOM}}; + _T_190 = _RAND_13[0:0]; + _RAND_14 = {1{`RANDOM}}; + abs_temp_12 = _RAND_14[0:0]; + _RAND_15 = {1{`RANDOM}}; + abs_temp_10_8 = _RAND_15[2:0]; + _RAND_16 = {1{`RANDOM}}; + command_reg = _RAND_16[31:0]; + _RAND_17 = {1{`RANDOM}}; + data0_reg = _RAND_17[31:0]; + _RAND_18 = {1{`RANDOM}}; + _T_297 = _RAND_18[31:0]; + _RAND_19 = {1{`RANDOM}}; + _T_466 = _RAND_19[2:0]; + _RAND_20 = {1{`RANDOM}}; + _T_467 = _RAND_20[31:0]; + _RAND_21 = {1{`RANDOM}}; + _T_545 = _RAND_21[3:0]; +`endif // RANDOMIZE_REG_INIT + if (dbg_dm_rst_l) begin + temp_sbcs_22 = 1'h0; + end + if (dbg_dm_rst_l) begin + temp_sbcs_21 = 1'h0; + end + if (dbg_dm_rst_l) begin + temp_sbcs_20 = 1'h0; + end + if (dbg_dm_rst_l) begin + temp_sbcs_19_15 = 5'h0; + end + if (dbg_dm_rst_l) begin + temp_sbcs_14_12 = 3'h0; + end + if (dbg_dm_rst_l) begin + sbdata0_reg = 32'h0; + end + if (dbg_dm_rst_l) begin + sbdata1_reg = 32'h0; + end + if (dbg_dm_rst_l) begin + _T_116 = 32'h0; + end + if (dbg_dm_rst_l) begin + dm_temp = 4'h0; + end + if (io_dbg_rst_l) begin + dm_temp_0 = 1'h0; + end + if (dbg_dm_rst_l) begin + dmcontrol_wren_Q = 1'h0; + end + if (dbg_dm_rst_l) begin + _T_183 = 1'h0; + end + if (dbg_dm_rst_l) begin + _T_186 = 1'h0; + end + if (dbg_dm_rst_l) begin + _T_190 = 1'h0; + end + if (dbg_dm_rst_l) begin + abs_temp_12 = 1'h0; + end + if (dbg_dm_rst_l) begin + abs_temp_10_8 = 3'h0; + end + if (dbg_dm_rst_l) begin + command_reg = 32'h0; + end + if (dbg_dm_rst_l) begin + data0_reg = 32'h0; + end + if (dbg_dm_rst_l) begin + _T_297 = 32'h0; + end + if (rst_temp) begin + _T_466 = 3'h0; + end + if (dbg_dm_rst_l) begin + _T_467 = 32'h0; + end + if (dbg_dm_rst_l) begin + _T_545 = 4'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge rvclkhdr_1_io_l1clk or posedge dbg_dm_rst_l) begin + if (dbg_dm_rst_l) begin + temp_sbcs_22 <= 1'h0; + end else if (sbcs_sbbusyerror_wren) begin + temp_sbcs_22 <= sbcs_sbbusyerror_din; + end + end + always @(posedge rvclkhdr_1_io_l1clk or posedge dbg_dm_rst_l) begin + if (dbg_dm_rst_l) begin + temp_sbcs_21 <= 1'h0; + end else if (sbcs_sbbusy_wren) begin + temp_sbcs_21 <= sbcs_sbbusy_din; + end + end + always @(posedge rvclkhdr_1_io_l1clk or posedge dbg_dm_rst_l) begin + if (dbg_dm_rst_l) begin + temp_sbcs_20 <= 1'h0; + end else if (sbcs_wren) begin + temp_sbcs_20 <= io_dmi_reg_wdata[20]; + end + end + always @(posedge rvclkhdr_1_io_l1clk or posedge dbg_dm_rst_l) begin + if (dbg_dm_rst_l) begin + temp_sbcs_19_15 <= 5'h0; + end else if (sbcs_wren) begin + temp_sbcs_19_15 <= io_dmi_reg_wdata[19:15]; + end + end + always @(posedge rvclkhdr_1_io_l1clk or posedge dbg_dm_rst_l) begin + if (dbg_dm_rst_l) begin + temp_sbcs_14_12 <= 3'h0; + end else if (sbcs_sberror_wren) begin + if (_T_500) begin + temp_sbcs_14_12 <= _T_510; + end else if (_T_511) begin + if (sbcs_unaligned) begin + temp_sbcs_14_12 <= 3'h3; + end else begin + temp_sbcs_14_12 <= 3'h4; + end + end else if (_T_518) begin + if (sbcs_unaligned) begin + temp_sbcs_14_12 <= 3'h3; + end else begin + temp_sbcs_14_12 <= 3'h4; + end + end else if (_T_525) begin + temp_sbcs_14_12 <= 3'h0; + end else if (_T_527) begin + temp_sbcs_14_12 <= 3'h0; + end else if (_T_533) begin + temp_sbcs_14_12 <= 3'h0; + end else if (_T_535) begin + temp_sbcs_14_12 <= 3'h0; + end else if (_T_537) begin + temp_sbcs_14_12 <= 3'h2; + end else if (_T_540) begin + temp_sbcs_14_12 <= 3'h2; + end else begin + temp_sbcs_14_12 <= 3'h0; + end + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge dbg_dm_rst_l) begin + if (dbg_dm_rst_l) begin + sbdata0_reg <= 32'h0; + end else begin + sbdata0_reg <= _T_93 | _T_97; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge dbg_dm_rst_l) begin + if (dbg_dm_rst_l) begin + sbdata1_reg <= 32'h0; + end else begin + sbdata1_reg <= _T_100 | _T_104; + end + end + always @(posedge rvclkhdr_4_io_l1clk or posedge dbg_dm_rst_l) begin + if (dbg_dm_rst_l) begin + _T_116 <= 32'h0; + end else begin + _T_116 <= _T_109 | _T_115; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge dbg_dm_rst_l) begin + if (dbg_dm_rst_l) begin + dm_temp <= 4'h0; + end else if (dmcontrol_wren) begin + dm_temp <= _T_134; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge io_dbg_rst_l) begin + if (io_dbg_rst_l) begin + dm_temp_0 <= 1'h0; + end else if (dmcontrol_wren) begin + dm_temp_0 <= io_dmi_reg_wdata[0]; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge dbg_dm_rst_l) begin + if (dbg_dm_rst_l) begin + dmcontrol_wren_Q <= 1'h0; + end else begin + dmcontrol_wren_Q <= _T_129 & io_dmi_reg_wr_en; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge dbg_dm_rst_l) begin + if (dbg_dm_rst_l) begin + _T_183 <= 1'h0; + end else if (dmstatus_resumeack_wren) begin + _T_183 <= _T_164; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge dbg_dm_rst_l) begin + if (dbg_dm_rst_l) begin + _T_186 <= 1'h0; + end else begin + _T_186 <= io_dec_tlu_dbg_halted & _T_184; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge dbg_dm_rst_l) begin + if (dbg_dm_rst_l) begin + _T_190 <= 1'h0; + end else begin + _T_190 <= _T_187 & _T_188; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge dbg_dm_rst_l) begin + if (dbg_dm_rst_l) begin + abs_temp_12 <= 1'h0; + end else if (abstractcs_busy_wren) begin + if (_T_298) begin + abs_temp_12 <= 1'h0; + end else if (_T_316) begin + abs_temp_12 <= 1'h0; + end else begin + abs_temp_12 <= _T_328; + end + end + end + always @(posedge rvclkhdr_io_l1clk or posedge dbg_dm_rst_l) begin + if (dbg_dm_rst_l) begin + abs_temp_10_8 <= 3'h0; + end else begin + abs_temp_10_8 <= _T_256 | _T_261; + end + end + always @(posedge rvclkhdr_5_io_l1clk or posedge dbg_dm_rst_l) begin + if (dbg_dm_rst_l) begin + command_reg <= 32'h0; + end else begin + command_reg <= {_T_276,_T_274}; + end + end + always @(posedge rvclkhdr_6_io_l1clk or posedge dbg_dm_rst_l) begin + if (dbg_dm_rst_l) begin + data0_reg <= 32'h0; + end else begin + data0_reg <= _T_287 | _T_290; + end + end + always @(posedge rvclkhdr_7_io_l1clk or posedge dbg_dm_rst_l) begin + if (dbg_dm_rst_l) begin + _T_297 <= 32'h0; + end else begin + _T_297 <= _T_296 & io_dmi_reg_wdata; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge rst_temp) begin + if (rst_temp) begin + _T_466 <= 3'h0; + end else if (dbg_state_en) begin + if (_T_298) begin + if (_T_300) begin + _T_466 <= 3'h2; + end else begin + _T_466 <= 3'h1; + end + end else if (_T_316) begin + if (dmcontrol_reg[1]) begin + _T_466 <= 3'h0; + end else begin + _T_466 <= 3'h2; + end + end else if (_T_328) begin + if (_T_332) begin + if (_T_336) begin + _T_466 <= 3'h6; + end else begin + _T_466 <= 3'h3; + end + end else if (dmcontrol_reg[31]) begin + _T_466 <= 3'h1; + end else begin + _T_466 <= 3'h0; + end + end else if (_T_366) begin + if (dmcontrol_reg[1]) begin + _T_466 <= 3'h0; + end else if (_T_369) begin + _T_466 <= 3'h5; + end else begin + _T_466 <= 3'h4; + end + end else if (_T_383) begin + if (dmcontrol_reg[1]) begin + _T_466 <= 3'h0; + end else begin + _T_466 <= 3'h5; + end + end else if (_T_394) begin + if (dmcontrol_reg[1]) begin + _T_466 <= 3'h0; + end else begin + _T_466 <= 3'h2; + end + end else begin + _T_466 <= 3'h0; + end + end + end + always @(posedge rvclkhdr_io_l1clk or posedge dbg_dm_rst_l) begin + if (dbg_dm_rst_l) begin + _T_467 <= 32'h0; + end else if (io_dmi_reg_en) begin + _T_467 <= dmi_reg_rdata_din; + end + end + always @(posedge rvclkhdr_1_io_l1clk or posedge dbg_dm_rst_l) begin + if (dbg_dm_rst_l) begin + _T_545 <= 4'h0; + end else if (sb_state_en) begin + if (_T_500) begin + if (sbdata0_reg_wren0) begin + _T_545 <= 4'h2; + end else begin + _T_545 <= 4'h1; + end + end else if (_T_511) begin + if (_T_512) begin + _T_545 <= 4'h9; + end else begin + _T_545 <= 4'h3; + end + end else if (_T_518) begin + if (_T_512) begin + _T_545 <= 4'h9; + end else begin + _T_545 <= 4'h4; + end + end else if (_T_525) begin + _T_545 <= 4'h7; + end else if (_T_527) begin + if (_T_528) begin + _T_545 <= 4'h8; + end else if (sb_bus_cmd_write_data) begin + _T_545 <= 4'h5; + end else begin + _T_545 <= 4'h6; + end + end else if (_T_533) begin + _T_545 <= 4'h8; + end else if (_T_535) begin + _T_545 <= 4'h8; + end else if (_T_537) begin + _T_545 <= 4'h9; + end else if (_T_540) begin + _T_545 <= 4'h9; + end else begin + _T_545 <= 4'h0; + end + end + end +endmodule diff --git a/firrtl_black_box_resource_files.f b/firrtl_black_box_resource_files.f index 40eae7ce..3a437a28 100644 --- a/firrtl_black_box_resource_files.f +++ b/firrtl_black_box_resource_files.f @@ -1,3 +1 @@ -/home/waleedbinehsan/Desktop/Quasar/gated_latch.v -/home/waleedbinehsan/Desktop/Quasar/dmi_wrapper.sv -/home/waleedbinehsan/Desktop/Quasar/mem.sv \ No newline at end of file +/home/waleedbinehsan/Desktop/Quasar-master/gated_latch.v \ No newline at end of file diff --git a/lsu.anno.json b/lsu.anno.json new file mode 100644 index 00000000..3a56a59b --- /dev/null +++ b/lsu.anno.json @@ -0,0 +1,506 @@ +[ + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn", + "sources":[ + "~lsu|lsu>io_axi_ar_ready", + "~lsu|lsu>io_axi_aw_ready", + "~lsu|lsu>io_axi_w_ready" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_single_ecc_error_incr", + "sources":[ + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r", + "~lsu|lsu>io_dec_tlu_core_ecc_disable", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_dma_dccm_ready", + "sources":[ + "~lsu|lsu>io_dec_lsu_valid_raw_d" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_dccm_wr_addr_lo", + "sources":[ + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write", + "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr", + "~lsu|lsu>io_dec_lsu_valid_raw_d", + "~lsu|lsu>io_dec_lsu_offset_d", + "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu|lsu>io_lsu_p_bits_dword", + "~lsu|lsu>io_lsu_p_bits_half", + "~lsu|lsu>io_lsu_p_bits_word", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz", + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_trigger_match_m", + "sources":[ + "~lsu|lsu>io_trigger_pkt_any_0_store", + "~lsu|lsu>io_trigger_pkt_any_1_store", + "~lsu|lsu>io_trigger_pkt_any_0_load", + "~lsu|lsu>io_trigger_pkt_any_0_select", + "~lsu|lsu>io_trigger_pkt_any_3_store", + "~lsu|lsu>io_trigger_pkt_any_2_store", + "~lsu|lsu>io_trigger_pkt_any_1_load", + "~lsu|lsu>io_trigger_pkt_any_1_select", + "~lsu|lsu>io_trigger_pkt_any_3_load", + "~lsu|lsu>io_trigger_pkt_any_3_select", + "~lsu|lsu>io_trigger_pkt_any_2_load", + "~lsu|lsu>io_trigger_pkt_any_2_select", + "~lsu|lsu>io_trigger_pkt_any_0_tdata2", + "~lsu|lsu>io_trigger_pkt_any_0_match_pkt", + "~lsu|lsu>io_trigger_pkt_any_1_tdata2", + "~lsu|lsu>io_trigger_pkt_any_1_match_pkt", + "~lsu|lsu>io_trigger_pkt_any_3_tdata2", + "~lsu|lsu>io_trigger_pkt_any_3_match_pkt", + "~lsu|lsu>io_trigger_pkt_any_2_tdata2", + "~lsu|lsu>io_trigger_pkt_any_2_match_pkt", + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_dccm_rd_addr_hi", + "sources":[ + "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr", + "~lsu|lsu>io_dec_lsu_valid_raw_d", + "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu|lsu>io_dec_lsu_offset_d", + "~lsu|lsu>io_lsu_p_bits_dword", + "~lsu|lsu>io_lsu_p_bits_half", + "~lsu|lsu>io_lsu_p_bits_word", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz", + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_dccm_rd_addr_lo", + "sources":[ + "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr", + "~lsu|lsu>io_dec_lsu_valid_raw_d", + "~lsu|lsu>io_dec_lsu_offset_d", + "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_dccm_rden", + "sources":[ + "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr", + "~lsu|lsu>io_dec_lsu_valid_raw_d", + "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu|lsu>io_dec_lsu_offset_d", + "~lsu|lsu>io_lsu_p_bits_dword", + "~lsu|lsu>io_lsu_p_bits_half", + "~lsu|lsu>io_lsu_p_bits_word", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req", + "~lsu|lsu>io_lsu_p_valid", + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_lsu_p_bits_fast_int", + "~lsu|lsu>io_lsu_p_bits_load", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write", + "~lsu|lsu>io_lsu_p_bits_store", + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy", + "sources":[ + "~lsu|lsu>io_axi_ar_ready", + "~lsu|lsu>io_axi_aw_ready", + "~lsu|lsu>io_axi_w_ready" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata", + "sources":[ + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dec_tlu_core_ecc_disable", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_dccm_wr_data_lo", + "sources":[ + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write", + "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr", + "~lsu|lsu>io_dec_lsu_valid_raw_d", + "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu|lsu>io_dec_lsu_offset_d", + "~lsu|lsu>io_lsu_p_bits_dword", + "~lsu|lsu>io_lsu_p_bits_half", + "~lsu|lsu>io_lsu_p_bits_word", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_wdata", + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_dccm_wren", + "sources":[ + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write", + "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr", + "~lsu|lsu>io_dec_lsu_valid_raw_d", + "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu|lsu>io_dec_lsu_offset_d", + "~lsu|lsu>io_lsu_p_bits_dword", + "~lsu|lsu>io_lsu_p_bits_half", + "~lsu|lsu>io_lsu_p_bits_word", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz", + "~lsu|lsu>io_lsu_p_valid", + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_lsu_p_bits_fast_int", + "~lsu|lsu>io_lsu_p_bits_load", + "~lsu|lsu>io_lsu_p_bits_store", + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_load_stall_any", + "sources":[ + "~lsu|lsu>io_dec_lsu_valid_raw_d", + "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr", + "~lsu|lsu>io_dec_lsu_offset_d", + "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu|lsu>io_lsu_p_bits_dword", + "~lsu|lsu>io_lsu_p_bits_half", + "~lsu|lsu>io_lsu_p_bits_word", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz", + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_pic_picm_wren", + "sources":[ + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r", + "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr", + "~lsu|lsu>io_dec_lsu_valid_raw_d", + "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu|lsu>io_dec_lsu_offset_d", + "~lsu|lsu>io_lsu_p_bits_dword", + "~lsu|lsu>io_lsu_p_bits_half", + "~lsu|lsu>io_lsu_p_bits_word", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz", + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_flush_lower_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_fastint_stall_any", + "sources":[ + "~lsu|lsu>io_dec_tlu_core_ecc_disable", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_pic_picm_rdaddr", + "sources":[ + "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr", + "~lsu|lsu>io_dec_lsu_valid_raw_d", + "~lsu|lsu>io_dec_lsu_offset_d", + "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_dccm_wr_data_hi", + "sources":[ + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write", + "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr", + "~lsu|lsu>io_dec_lsu_valid_raw_d", + "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu|lsu>io_dec_lsu_offset_d", + "~lsu|lsu>io_lsu_p_bits_dword", + "~lsu|lsu>io_lsu_p_bits_half", + "~lsu|lsu>io_lsu_p_bits_word", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_wdata", + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_pic_picm_wraddr", + "sources":[ + "~lsu|lsu>io_lsu_dma_dma_dccm_ctl_dma_mem_addr", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write", + "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr", + "~lsu|lsu>io_dec_lsu_valid_raw_d", + "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu|lsu>io_dec_lsu_offset_d", + "~lsu|lsu>io_lsu_p_bits_dword", + "~lsu|lsu>io_lsu_p_bits_half", + "~lsu|lsu>io_lsu_p_bits_word", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz", + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned", + "sources":[ + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_pic_picm_mken", + "sources":[ + "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr", + "~lsu|lsu>io_dec_lsu_valid_raw_d", + "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu|lsu>io_dec_lsu_offset_d", + "~lsu|lsu>io_lsu_p_bits_dword", + "~lsu|lsu>io_lsu_p_bits_half", + "~lsu|lsu>io_lsu_p_bits_word", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req", + "~lsu|lsu>io_lsu_p_valid", + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_lsu_p_bits_fast_int", + "~lsu|lsu>io_lsu_p_bits_store", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write", + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error", + "sources":[ + "~lsu|lsu>io_dec_tlu_core_ecc_disable", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_pic_picm_rden", + "sources":[ + "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr", + "~lsu|lsu>io_dec_lsu_valid_raw_d", + "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu|lsu>io_dec_lsu_offset_d", + "~lsu|lsu>io_lsu_p_bits_dword", + "~lsu|lsu>io_lsu_p_bits_half", + "~lsu|lsu>io_lsu_p_bits_word", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req", + "~lsu|lsu>io_lsu_p_valid", + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_lsu_p_bits_fast_int", + "~lsu|lsu>io_lsu_p_bits_load", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write", + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r", + "sources":[ + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m", + "sources":[ + "~lsu|lsu>io_dec_tlu_flush_lower_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_pic_picm_wr_data", + "sources":[ + "~lsu|lsu>io_lsu_dma_dma_dccm_ctl_dma_mem_wdata", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write", + "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr", + "~lsu|lsu>io_dec_lsu_valid_raw_d", + "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu|lsu>io_dec_lsu_offset_d", + "~lsu|lsu>io_lsu_p_bits_dword", + "~lsu|lsu>io_lsu_p_bits_half", + "~lsu|lsu>io_lsu_p_bits_word", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz", + "~lsu|lsu>io_lsu_p_valid", + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_lsu_p_bits_fast_int", + "~lsu|lsu>io_lsu_p_bits_load", + "~lsu|lsu>io_lsu_p_bits_store", + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_result_m", + "sources":[ + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_lsu_store_stall_any", + "sources":[ + "~lsu|lsu>io_dec_lsu_valid_raw_d", + "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr", + "~lsu|lsu>io_dec_lsu_offset_d", + "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu|lsu>io_lsu_p_bits_dword", + "~lsu|lsu>io_lsu_p_bits_half", + "~lsu|lsu>io_lsu_p_bits_word", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz", + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu|lsu>io_dccm_wr_addr_hi", + "sources":[ + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write", + "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr", + "~lsu|lsu>io_dec_lsu_valid_raw_d", + "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d", + "~lsu|lsu>io_dec_lsu_offset_d", + "~lsu|lsu>io_lsu_p_bits_dword", + "~lsu|lsu>io_lsu_p_bits_half", + "~lsu|lsu>io_lsu_p_bits_word", + "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz", + "~lsu|lsu>io_lsu_pic_picm_rd_data", + "~lsu|lsu>io_dccm_rd_data_hi", + "~lsu|lsu>io_dccm_rd_data_lo", + "~lsu|lsu>io_dec_tlu_flush_lower_r", + "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r" + ] + }, + { + "class":"firrtl.EmitCircuitAnnotation", + "emitter":"firrtl.VerilogEmitter" + }, + { + "class":"firrtl.transforms.BlackBoxResourceAnno", + "target":"lsu.gated_latch", + "resourceId":"/vsrc/gated_latch.v" + }, + { + "class":"firrtl.options.TargetDirAnnotation", + "directory":"." + }, + { + "class":"firrtl.options.OutputAnnotationFileAnnotation", + "file":"lsu" + }, + { + "class":"firrtl.transforms.BlackBoxTargetDirAnno", + "targetDir":"." + } +] \ No newline at end of file diff --git a/lsu.fir b/lsu.fir new file mode 100644 index 00000000..0bf43dd2 --- /dev/null +++ b/lsu.fir @@ -0,0 +1,15817 @@ +;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 +circuit lsu : + module lsu_addrcheck : + input clock : Clock + input reset : AsyncReset + output io : {flip lsu_c2_m_clk : Clock, flip start_addr_d : UInt<32>, flip end_addr_d : UInt<32>, flip lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip dec_tlu_mrac_ff : UInt<32>, flip rs1_region_d : UInt<4>, flip rs1_d : UInt<32>, is_sideeffects_m : UInt<1>, addr_in_dccm_d : UInt<1>, addr_in_pic_d : UInt<1>, addr_external_d : UInt<1>, access_fault_d : UInt<1>, misaligned_fault_d : UInt<1>, exc_mscause_d : UInt<4>, fir_dccm_access_error_d : UInt<1>, fir_nondccm_access_error_d : UInt<1>, flip scan_mode : UInt<1>} + + node _T = bits(io.start_addr_d, 31, 28) @[lib.scala 356:27] + node start_addr_in_dccm_region_d = eq(_T, UInt<4>("h0f")) @[lib.scala 356:49] + wire start_addr_in_dccm_d : UInt<1> @[lib.scala 357:26] + node _T_1 = bits(io.start_addr_d, 31, 16) @[lib.scala 361:24] + node _T_2 = eq(_T_1, UInt<16>("h0f004")) @[lib.scala 361:39] + start_addr_in_dccm_d <= _T_2 @[lib.scala 361:16] + node _T_3 = bits(io.end_addr_d, 31, 28) @[lib.scala 356:27] + node end_addr_in_dccm_region_d = eq(_T_3, UInt<4>("h0f")) @[lib.scala 356:49] + wire end_addr_in_dccm_d : UInt<1> @[lib.scala 357:26] + node _T_4 = bits(io.end_addr_d, 31, 16) @[lib.scala 361:24] + node _T_5 = eq(_T_4, UInt<16>("h0f004")) @[lib.scala 361:39] + end_addr_in_dccm_d <= _T_5 @[lib.scala 361:16] + wire addr_in_iccm : UInt<1> + addr_in_iccm <= UInt<1>("h00") + node _T_6 = bits(io.start_addr_d, 31, 28) @[lsu_addrcheck.scala 42:37] + node _T_7 = eq(_T_6, UInt<4>("h0e")) @[lsu_addrcheck.scala 42:45] + addr_in_iccm <= _T_7 @[lsu_addrcheck.scala 42:18] + node _T_8 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 50:89] + node _T_9 = bits(_T_8, 31, 28) @[lib.scala 356:27] + node start_addr_in_pic_region_d = eq(_T_9, UInt<4>("h0f")) @[lib.scala 356:49] + wire start_addr_in_pic_d : UInt<1> @[lib.scala 357:26] + node _T_10 = bits(_T_8, 31, 15) @[lib.scala 361:24] + node _T_11 = eq(_T_10, UInt<17>("h01e018")) @[lib.scala 361:39] + start_addr_in_pic_d <= _T_11 @[lib.scala 361:16] + node _T_12 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 52:83] + node _T_13 = bits(_T_12, 31, 28) @[lib.scala 356:27] + node end_addr_in_pic_region_d = eq(_T_13, UInt<4>("h0f")) @[lib.scala 356:49] + wire end_addr_in_pic_d : UInt<1> @[lib.scala 357:26] + node _T_14 = bits(_T_12, 31, 15) @[lib.scala 361:24] + node _T_15 = eq(_T_14, UInt<17>("h01e018")) @[lib.scala 361:39] + end_addr_in_pic_d <= _T_15 @[lib.scala 361:16] + node start_addr_dccm_or_pic = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[lsu_addrcheck.scala 54:60] + node _T_16 = bits(io.rs1_region_d, 3, 0) @[lsu_addrcheck.scala 55:48] + node _T_17 = eq(_T_16, UInt<4>("h0f")) @[lsu_addrcheck.scala 55:54] + node _T_18 = bits(io.rs1_region_d, 3, 0) @[lsu_addrcheck.scala 55:91] + node _T_19 = eq(_T_18, UInt<4>("h0f")) @[lsu_addrcheck.scala 55:97] + node base_reg_dccm_or_pic = or(_T_17, _T_19) @[lsu_addrcheck.scala 55:73] + node _T_20 = and(start_addr_in_dccm_d, end_addr_in_dccm_d) @[lsu_addrcheck.scala 56:57] + io.addr_in_dccm_d <= _T_20 @[lsu_addrcheck.scala 56:32] + node _T_21 = and(start_addr_in_pic_d, end_addr_in_pic_d) @[lsu_addrcheck.scala 57:56] + io.addr_in_pic_d <= _T_21 @[lsu_addrcheck.scala 57:32] + node _T_22 = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[lsu_addrcheck.scala 59:63] + node _T_23 = not(_T_22) @[lsu_addrcheck.scala 59:33] + io.addr_external_d <= _T_23 @[lsu_addrcheck.scala 59:30] + node _T_24 = bits(io.start_addr_d, 31, 28) @[lsu_addrcheck.scala 60:51] + node csr_idx = cat(_T_24, UInt<1>("h01")) @[Cat.scala 29:58] + node _T_25 = dshr(io.dec_tlu_mrac_ff, csr_idx) @[lsu_addrcheck.scala 61:50] + node _T_26 = bits(_T_25, 0, 0) @[lsu_addrcheck.scala 61:50] + node _T_27 = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[lsu_addrcheck.scala 61:92] + node _T_28 = or(_T_27, addr_in_iccm) @[lsu_addrcheck.scala 61:121] + node _T_29 = eq(_T_28, UInt<1>("h00")) @[lsu_addrcheck.scala 61:62] + node _T_30 = and(_T_26, _T_29) @[lsu_addrcheck.scala 61:60] + node _T_31 = and(_T_30, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 61:137] + node _T_32 = or(io.lsu_pkt_d.bits.store, io.lsu_pkt_d.bits.load) @[lsu_addrcheck.scala 61:185] + node is_sideeffects_d = and(_T_31, _T_32) @[lsu_addrcheck.scala 61:158] + node _T_33 = bits(io.start_addr_d, 1, 0) @[lsu_addrcheck.scala 62:74] + node _T_34 = eq(_T_33, UInt<1>("h00")) @[lsu_addrcheck.scala 62:80] + node _T_35 = and(io.lsu_pkt_d.bits.word, _T_34) @[lsu_addrcheck.scala 62:56] + node _T_36 = bits(io.start_addr_d, 0, 0) @[lsu_addrcheck.scala 62:134] + node _T_37 = eq(_T_36, UInt<1>("h00")) @[lsu_addrcheck.scala 62:138] + node _T_38 = and(io.lsu_pkt_d.bits.half, _T_37) @[lsu_addrcheck.scala 62:116] + node _T_39 = or(_T_35, _T_38) @[lsu_addrcheck.scala 62:90] + node is_aligned_d = or(_T_39, io.lsu_pkt_d.bits.by) @[lsu_addrcheck.scala 62:148] + node _T_40 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58] + node _T_41 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58] + node _T_42 = cat(_T_41, _T_40) @[Cat.scala 29:58] + node _T_43 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58] + node _T_44 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58] + node _T_45 = cat(_T_44, _T_43) @[Cat.scala 29:58] + node _T_46 = cat(_T_45, _T_42) @[Cat.scala 29:58] + node _T_47 = orr(_T_46) @[lsu_addrcheck.scala 66:99] + node _T_48 = eq(_T_47, UInt<1>("h00")) @[lsu_addrcheck.scala 65:33] + node _T_49 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 67:49] + node _T_50 = or(_T_49, UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 67:56] + node _T_51 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 67:121] + node _T_52 = eq(_T_50, _T_51) @[lsu_addrcheck.scala 67:88] + node _T_53 = and(UInt<1>("h01"), _T_52) @[lsu_addrcheck.scala 67:30] + node _T_54 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 68:49] + node _T_55 = or(_T_54, UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 68:56] + node _T_56 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 68:121] + node _T_57 = eq(_T_55, _T_56) @[lsu_addrcheck.scala 68:88] + node _T_58 = and(UInt<1>("h01"), _T_57) @[lsu_addrcheck.scala 68:30] + node _T_59 = or(_T_53, _T_58) @[lsu_addrcheck.scala 67:153] + node _T_60 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 69:49] + node _T_61 = or(_T_60, UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 69:56] + node _T_62 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 69:121] + node _T_63 = eq(_T_61, _T_62) @[lsu_addrcheck.scala 69:88] + node _T_64 = and(UInt<1>("h01"), _T_63) @[lsu_addrcheck.scala 69:30] + node _T_65 = or(_T_59, _T_64) @[lsu_addrcheck.scala 68:153] + node _T_66 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 70:49] + node _T_67 = or(_T_66, UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 70:56] + node _T_68 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 70:121] + node _T_69 = eq(_T_67, _T_68) @[lsu_addrcheck.scala 70:88] + node _T_70 = and(UInt<1>("h01"), _T_69) @[lsu_addrcheck.scala 70:30] + node _T_71 = or(_T_65, _T_70) @[lsu_addrcheck.scala 69:153] + node _T_72 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 71:49] + node _T_73 = or(_T_72, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 71:56] + node _T_74 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 71:121] + node _T_75 = eq(_T_73, _T_74) @[lsu_addrcheck.scala 71:88] + node _T_76 = and(UInt<1>("h00"), _T_75) @[lsu_addrcheck.scala 71:30] + node _T_77 = or(_T_71, _T_76) @[lsu_addrcheck.scala 70:153] + node _T_78 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 72:49] + node _T_79 = or(_T_78, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 72:56] + node _T_80 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 72:121] + node _T_81 = eq(_T_79, _T_80) @[lsu_addrcheck.scala 72:88] + node _T_82 = and(UInt<1>("h00"), _T_81) @[lsu_addrcheck.scala 72:30] + node _T_83 = or(_T_77, _T_82) @[lsu_addrcheck.scala 71:153] + node _T_84 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 73:49] + node _T_85 = or(_T_84, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 73:56] + node _T_86 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 73:121] + node _T_87 = eq(_T_85, _T_86) @[lsu_addrcheck.scala 73:88] + node _T_88 = and(UInt<1>("h00"), _T_87) @[lsu_addrcheck.scala 73:30] + node _T_89 = or(_T_83, _T_88) @[lsu_addrcheck.scala 72:153] + node _T_90 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 74:49] + node _T_91 = or(_T_90, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 74:56] + node _T_92 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 74:121] + node _T_93 = eq(_T_91, _T_92) @[lsu_addrcheck.scala 74:88] + node _T_94 = and(UInt<1>("h00"), _T_93) @[lsu_addrcheck.scala 74:30] + node _T_95 = or(_T_89, _T_94) @[lsu_addrcheck.scala 73:153] + node _T_96 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 76:48] + node _T_97 = or(_T_96, UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 76:57] + node _T_98 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 76:122] + node _T_99 = eq(_T_97, _T_98) @[lsu_addrcheck.scala 76:89] + node _T_100 = and(UInt<1>("h01"), _T_99) @[lsu_addrcheck.scala 76:31] + node _T_101 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 77:49] + node _T_102 = or(_T_101, UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 77:58] + node _T_103 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 77:123] + node _T_104 = eq(_T_102, _T_103) @[lsu_addrcheck.scala 77:90] + node _T_105 = and(UInt<1>("h01"), _T_104) @[lsu_addrcheck.scala 77:32] + node _T_106 = or(_T_100, _T_105) @[lsu_addrcheck.scala 76:154] + node _T_107 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 78:49] + node _T_108 = or(_T_107, UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 78:58] + node _T_109 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 78:123] + node _T_110 = eq(_T_108, _T_109) @[lsu_addrcheck.scala 78:90] + node _T_111 = and(UInt<1>("h01"), _T_110) @[lsu_addrcheck.scala 78:32] + node _T_112 = or(_T_106, _T_111) @[lsu_addrcheck.scala 77:155] + node _T_113 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 79:49] + node _T_114 = or(_T_113, UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 79:58] + node _T_115 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 79:123] + node _T_116 = eq(_T_114, _T_115) @[lsu_addrcheck.scala 79:90] + node _T_117 = and(UInt<1>("h01"), _T_116) @[lsu_addrcheck.scala 79:32] + node _T_118 = or(_T_112, _T_117) @[lsu_addrcheck.scala 78:155] + node _T_119 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 80:49] + node _T_120 = or(_T_119, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 80:58] + node _T_121 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 80:123] + node _T_122 = eq(_T_120, _T_121) @[lsu_addrcheck.scala 80:90] + node _T_123 = and(UInt<1>("h00"), _T_122) @[lsu_addrcheck.scala 80:32] + node _T_124 = or(_T_118, _T_123) @[lsu_addrcheck.scala 79:155] + node _T_125 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 81:49] + node _T_126 = or(_T_125, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 81:58] + node _T_127 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 81:123] + node _T_128 = eq(_T_126, _T_127) @[lsu_addrcheck.scala 81:90] + node _T_129 = and(UInt<1>("h00"), _T_128) @[lsu_addrcheck.scala 81:32] + node _T_130 = or(_T_124, _T_129) @[lsu_addrcheck.scala 80:155] + node _T_131 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 82:49] + node _T_132 = or(_T_131, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 82:58] + node _T_133 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 82:123] + node _T_134 = eq(_T_132, _T_133) @[lsu_addrcheck.scala 82:90] + node _T_135 = and(UInt<1>("h00"), _T_134) @[lsu_addrcheck.scala 82:32] + node _T_136 = or(_T_130, _T_135) @[lsu_addrcheck.scala 81:155] + node _T_137 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 83:49] + node _T_138 = or(_T_137, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 83:58] + node _T_139 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 83:123] + node _T_140 = eq(_T_138, _T_139) @[lsu_addrcheck.scala 83:90] + node _T_141 = and(UInt<1>("h00"), _T_140) @[lsu_addrcheck.scala 83:32] + node _T_142 = or(_T_136, _T_141) @[lsu_addrcheck.scala 82:155] + node _T_143 = and(_T_95, _T_142) @[lsu_addrcheck.scala 75:7] + node non_dccm_access_ok = or(_T_48, _T_143) @[lsu_addrcheck.scala 66:104] + node regpred_access_fault_d = xor(start_addr_dccm_or_pic, base_reg_dccm_or_pic) @[lsu_addrcheck.scala 85:57] + node _T_144 = bits(io.start_addr_d, 1, 0) @[lsu_addrcheck.scala 86:70] + node _T_145 = neq(_T_144, UInt<2>("h00")) @[lsu_addrcheck.scala 86:76] + node _T_146 = eq(io.lsu_pkt_d.bits.word, UInt<1>("h00")) @[lsu_addrcheck.scala 86:92] + node _T_147 = or(_T_145, _T_146) @[lsu_addrcheck.scala 86:90] + node picm_access_fault_d = and(io.addr_in_pic_d, _T_147) @[lsu_addrcheck.scala 86:51] + wire unmapped_access_fault_d : UInt<1> + unmapped_access_fault_d <= UInt<1>("h01") + wire mpu_access_fault_d : UInt<1> + mpu_access_fault_d <= UInt<1>("h01") + node _T_148 = or(start_addr_in_dccm_d, start_addr_in_pic_d) @[lsu_addrcheck.scala 91:87] + node _T_149 = eq(_T_148, UInt<1>("h00")) @[lsu_addrcheck.scala 91:64] + node _T_150 = and(start_addr_in_dccm_region_d, _T_149) @[lsu_addrcheck.scala 91:62] + node _T_151 = or(end_addr_in_dccm_d, end_addr_in_pic_d) @[lsu_addrcheck.scala 93:57] + node _T_152 = eq(_T_151, UInt<1>("h00")) @[lsu_addrcheck.scala 93:36] + node _T_153 = and(end_addr_in_dccm_region_d, _T_152) @[lsu_addrcheck.scala 93:34] + node _T_154 = or(_T_150, _T_153) @[lsu_addrcheck.scala 91:112] + node _T_155 = and(start_addr_in_dccm_d, end_addr_in_pic_d) @[lsu_addrcheck.scala 95:29] + node _T_156 = or(_T_154, _T_155) @[lsu_addrcheck.scala 93:85] + node _T_157 = and(start_addr_in_pic_d, end_addr_in_dccm_d) @[lsu_addrcheck.scala 97:29] + node _T_158 = or(_T_156, _T_157) @[lsu_addrcheck.scala 95:85] + unmapped_access_fault_d <= _T_158 @[lsu_addrcheck.scala 91:29] + node _T_159 = eq(start_addr_in_dccm_region_d, UInt<1>("h00")) @[lsu_addrcheck.scala 99:33] + node _T_160 = eq(non_dccm_access_ok, UInt<1>("h00")) @[lsu_addrcheck.scala 99:64] + node _T_161 = and(_T_159, _T_160) @[lsu_addrcheck.scala 99:62] + mpu_access_fault_d <= _T_161 @[lsu_addrcheck.scala 99:29] + node _T_162 = or(unmapped_access_fault_d, mpu_access_fault_d) @[lsu_addrcheck.scala 111:49] + node _T_163 = or(_T_162, picm_access_fault_d) @[lsu_addrcheck.scala 111:70] + node _T_164 = or(_T_163, regpred_access_fault_d) @[lsu_addrcheck.scala 111:92] + node _T_165 = and(_T_164, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 111:118] + node _T_166 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[lsu_addrcheck.scala 111:141] + node _T_167 = and(_T_165, _T_166) @[lsu_addrcheck.scala 111:139] + io.access_fault_d <= _T_167 @[lsu_addrcheck.scala 111:21] + node _T_168 = bits(unmapped_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:60] + node _T_169 = bits(mpu_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:100] + node _T_170 = bits(regpred_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:144] + node _T_171 = bits(picm_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:185] + node _T_172 = mux(_T_171, UInt<4>("h06"), UInt<4>("h00")) @[lsu_addrcheck.scala 112:164] + node _T_173 = mux(_T_170, UInt<4>("h05"), _T_172) @[lsu_addrcheck.scala 112:120] + node _T_174 = mux(_T_169, UInt<4>("h03"), _T_173) @[lsu_addrcheck.scala 112:80] + node access_fault_mscause_d = mux(_T_168, UInt<4>("h02"), _T_174) @[lsu_addrcheck.scala 112:35] + node _T_175 = bits(io.start_addr_d, 31, 28) @[lsu_addrcheck.scala 113:53] + node _T_176 = bits(io.end_addr_d, 31, 28) @[lsu_addrcheck.scala 113:78] + node regcross_misaligned_fault_d = neq(_T_175, _T_176) @[lsu_addrcheck.scala 113:61] + node _T_177 = eq(is_aligned_d, UInt<1>("h00")) @[lsu_addrcheck.scala 114:59] + node sideeffect_misaligned_fault_d = and(is_sideeffects_d, _T_177) @[lsu_addrcheck.scala 114:57] + node _T_178 = and(sideeffect_misaligned_fault_d, io.addr_external_d) @[lsu_addrcheck.scala 115:90] + node _T_179 = or(regcross_misaligned_fault_d, _T_178) @[lsu_addrcheck.scala 115:57] + node _T_180 = and(_T_179, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 115:113] + node _T_181 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[lsu_addrcheck.scala 115:136] + node _T_182 = and(_T_180, _T_181) @[lsu_addrcheck.scala 115:134] + io.misaligned_fault_d <= _T_182 @[lsu_addrcheck.scala 115:25] + node _T_183 = bits(sideeffect_misaligned_fault_d, 0, 0) @[lsu_addrcheck.scala 116:111] + node _T_184 = mux(_T_183, UInt<4>("h01"), UInt<4>("h00")) @[lsu_addrcheck.scala 116:80] + node misaligned_fault_mscause_d = mux(regcross_misaligned_fault_d, UInt<4>("h02"), _T_184) @[lsu_addrcheck.scala 116:39] + node _T_185 = bits(io.misaligned_fault_d, 0, 0) @[lsu_addrcheck.scala 117:50] + node _T_186 = bits(misaligned_fault_mscause_d, 3, 0) @[lsu_addrcheck.scala 117:84] + node _T_187 = bits(access_fault_mscause_d, 3, 0) @[lsu_addrcheck.scala 117:113] + node _T_188 = mux(_T_185, _T_186, _T_187) @[lsu_addrcheck.scala 117:27] + io.exc_mscause_d <= _T_188 @[lsu_addrcheck.scala 117:21] + node _T_189 = eq(start_addr_in_dccm_d, UInt<1>("h00")) @[lsu_addrcheck.scala 118:66] + node _T_190 = and(start_addr_in_dccm_region_d, _T_189) @[lsu_addrcheck.scala 118:64] + node _T_191 = eq(end_addr_in_dccm_d, UInt<1>("h00")) @[lsu_addrcheck.scala 118:120] + node _T_192 = and(end_addr_in_dccm_region_d, _T_191) @[lsu_addrcheck.scala 118:118] + node _T_193 = or(_T_190, _T_192) @[lsu_addrcheck.scala 118:88] + node _T_194 = and(_T_193, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 118:142] + node _T_195 = and(_T_194, io.lsu_pkt_d.bits.fast_int) @[lsu_addrcheck.scala 118:163] + io.fir_dccm_access_error_d <= _T_195 @[lsu_addrcheck.scala 118:31] + node _T_196 = and(start_addr_in_dccm_region_d, end_addr_in_dccm_region_d) @[lsu_addrcheck.scala 119:66] + node _T_197 = eq(_T_196, UInt<1>("h00")) @[lsu_addrcheck.scala 119:36] + node _T_198 = and(_T_197, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 119:95] + node _T_199 = and(_T_198, io.lsu_pkt_d.bits.fast_int) @[lsu_addrcheck.scala 119:116] + io.fir_nondccm_access_error_d <= _T_199 @[lsu_addrcheck.scala 119:33] + reg _T_200 : UInt<1>, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_addrcheck.scala 121:60] + _T_200 <= is_sideeffects_d @[lsu_addrcheck.scala 121:60] + io.is_sideeffects_m <= _T_200 @[lsu_addrcheck.scala 121:50] + + module lsu_lsc_ctl : + input clock : Clock + input reset : AsyncReset + output io : {flip lsu_c1_m_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_c2_m_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_store_c1_m_clk : Clock, flip lsu_ld_data_r : UInt<32>, flip lsu_ld_data_corr_r : UInt<32>, flip lsu_single_ecc_error_r : UInt<1>, flip lsu_double_ecc_error_r : UInt<1>, flip lsu_ld_data_m : UInt<32>, flip lsu_single_ecc_error_m : UInt<1>, flip lsu_double_ecc_error_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, lsu_exu : {flip exu_lsu_rs1_d : UInt<32>, flip exu_lsu_rs2_d : UInt<32>}, flip lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip dec_lsu_valid_raw_d : UInt<1>, flip dec_lsu_offset_d : UInt<12>, flip picm_mask_data_m : UInt<32>, flip bus_read_data_m : UInt<32>, lsu_result_m : UInt<32>, lsu_result_corr_r : UInt<32>, lsu_addr_d : UInt<32>, lsu_addr_m : UInt<32>, lsu_addr_r : UInt<32>, end_addr_d : UInt<32>, end_addr_m : UInt<32>, end_addr_r : UInt<32>, store_data_m : UInt<32>, flip dec_tlu_mrac_ff : UInt<32>, lsu_exc_m : UInt<1>, is_sideeffects_m : UInt<1>, lsu_commit_r : UInt<1>, lsu_single_ecc_error_incr : UInt<1>, lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, lsu_fir_addr : UInt<31>, lsu_fir_error : UInt<2>, addr_in_dccm_d : UInt<1>, addr_in_dccm_m : UInt<1>, addr_in_dccm_r : UInt<1>, addr_in_pic_d : UInt<1>, addr_in_pic_m : UInt<1>, addr_in_pic_r : UInt<1>, addr_external_m : UInt<1>, dma_lsc_ctl : {flip dma_dccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>}, lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip scan_mode : UInt<1>} + + wire dma_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 90:29] + wire lsu_pkt_m_in : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 91:29] + wire lsu_pkt_r_in : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 92:29] + wire lsu_error_pkt_m : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}} @[lsu_lsc_ctl.scala 93:29] + node _T = bits(io.dec_lsu_valid_raw_d, 0, 0) @[lsu_lsc_ctl.scala 95:52] + node lsu_rs1_d = mux(_T, io.lsu_exu.exu_lsu_rs1_d, io.dma_lsc_ctl.dma_mem_addr) @[lsu_lsc_ctl.scala 95:28] + node _T_1 = bits(io.dec_lsu_offset_d, 11, 0) @[lsu_lsc_ctl.scala 96:44] + node _T_2 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[Bitwise.scala 72:15] + node _T_3 = mux(_T_2, UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12] + node lsu_offset_d = and(_T_1, _T_3) @[lsu_lsc_ctl.scala 96:51] + node _T_4 = bits(io.lsu_pkt_d.bits.load_ldst_bypass_d, 0, 0) @[lsu_lsc_ctl.scala 99:66] + node rs1_d = mux(_T_4, io.lsu_result_m, lsu_rs1_d) @[lsu_lsc_ctl.scala 99:28] + node _T_5 = bits(rs1_d, 11, 0) @[lib.scala 92:31] + node _T_6 = cat(UInt<1>("h00"), _T_5) @[Cat.scala 29:58] + node _T_7 = bits(lsu_offset_d, 11, 0) @[lib.scala 92:60] + node _T_8 = cat(UInt<1>("h00"), _T_7) @[Cat.scala 29:58] + node _T_9 = add(_T_6, _T_8) @[lib.scala 92:39] + node _T_10 = tail(_T_9, 1) @[lib.scala 92:39] + node _T_11 = bits(lsu_offset_d, 11, 11) @[lib.scala 93:41] + node _T_12 = bits(_T_10, 12, 12) @[lib.scala 93:50] + node _T_13 = xor(_T_11, _T_12) @[lib.scala 93:46] + node _T_14 = not(_T_13) @[lib.scala 93:33] + node _T_15 = bits(_T_14, 0, 0) @[Bitwise.scala 72:15] + node _T_16 = mux(_T_15, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12] + node _T_17 = bits(rs1_d, 31, 12) @[lib.scala 93:63] + node _T_18 = and(_T_16, _T_17) @[lib.scala 93:58] + node _T_19 = bits(lsu_offset_d, 11, 11) @[lib.scala 94:25] + node _T_20 = not(_T_19) @[lib.scala 94:18] + node _T_21 = bits(_T_10, 12, 12) @[lib.scala 94:34] + node _T_22 = and(_T_20, _T_21) @[lib.scala 94:30] + node _T_23 = bits(_T_22, 0, 0) @[Bitwise.scala 72:15] + node _T_24 = mux(_T_23, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12] + node _T_25 = bits(rs1_d, 31, 12) @[lib.scala 94:47] + node _T_26 = add(_T_25, UInt<1>("h01")) @[lib.scala 94:54] + node _T_27 = tail(_T_26, 1) @[lib.scala 94:54] + node _T_28 = and(_T_24, _T_27) @[lib.scala 94:41] + node _T_29 = or(_T_18, _T_28) @[lib.scala 93:72] + node _T_30 = bits(lsu_offset_d, 11, 11) @[lib.scala 95:24] + node _T_31 = bits(_T_10, 12, 12) @[lib.scala 95:34] + node _T_32 = not(_T_31) @[lib.scala 95:31] + node _T_33 = and(_T_30, _T_32) @[lib.scala 95:29] + node _T_34 = bits(_T_33, 0, 0) @[Bitwise.scala 72:15] + node _T_35 = mux(_T_34, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12] + node _T_36 = bits(rs1_d, 31, 12) @[lib.scala 95:47] + node _T_37 = sub(_T_36, UInt<1>("h01")) @[lib.scala 95:54] + node _T_38 = tail(_T_37, 1) @[lib.scala 95:54] + node _T_39 = and(_T_35, _T_38) @[lib.scala 95:41] + node _T_40 = or(_T_29, _T_39) @[lib.scala 94:61] + node _T_41 = bits(_T_10, 11, 0) @[lib.scala 96:22] + node full_addr_d = cat(_T_40, _T_41) @[Cat.scala 29:58] + node _T_42 = bits(io.lsu_pkt_d.bits.half, 0, 0) @[Bitwise.scala 72:15] + node _T_43 = mux(_T_42, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_44 = and(_T_43, UInt<3>("h01")) @[lsu_lsc_ctl.scala 104:58] + node _T_45 = bits(io.lsu_pkt_d.bits.word, 0, 0) @[Bitwise.scala 72:15] + node _T_46 = mux(_T_45, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_47 = and(_T_46, UInt<3>("h03")) @[lsu_lsc_ctl.scala 105:40] + node _T_48 = or(_T_44, _T_47) @[lsu_lsc_ctl.scala 104:70] + node _T_49 = bits(io.lsu_pkt_d.bits.dword, 0, 0) @[Bitwise.scala 72:15] + node _T_50 = mux(_T_49, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_51 = and(_T_50, UInt<3>("h07")) @[lsu_lsc_ctl.scala 106:40] + node addr_offset_d = or(_T_48, _T_51) @[lsu_lsc_ctl.scala 105:52] + node _T_52 = bits(lsu_offset_d, 11, 11) @[lsu_lsc_ctl.scala 108:39] + node _T_53 = bits(lsu_offset_d, 11, 0) @[lsu_lsc_ctl.scala 108:52] + node _T_54 = cat(_T_52, _T_53) @[Cat.scala 29:58] + node _T_55 = mux(UInt<1>("h00"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 72:12] + node _T_56 = bits(addr_offset_d, 2, 0) @[lsu_lsc_ctl.scala 108:91] + node _T_57 = cat(_T_55, _T_56) @[Cat.scala 29:58] + node _T_58 = add(_T_54, _T_57) @[lsu_lsc_ctl.scala 108:60] + node end_addr_offset_d = tail(_T_58, 1) @[lsu_lsc_ctl.scala 108:60] + node _T_59 = bits(rs1_d, 31, 0) @[lsu_lsc_ctl.scala 109:32] + node _T_60 = bits(end_addr_offset_d, 12, 12) @[lsu_lsc_ctl.scala 109:70] + node _T_61 = bits(_T_60, 0, 0) @[Bitwise.scala 72:15] + node _T_62 = mux(_T_61, UInt<19>("h07ffff"), UInt<19>("h00")) @[Bitwise.scala 72:12] + node _T_63 = bits(end_addr_offset_d, 12, 0) @[lsu_lsc_ctl.scala 109:93] + node _T_64 = cat(_T_62, _T_63) @[Cat.scala 29:58] + node _T_65 = add(_T_59, _T_64) @[lsu_lsc_ctl.scala 109:39] + node full_end_addr_d = tail(_T_65, 1) @[lsu_lsc_ctl.scala 109:39] + io.end_addr_d <= full_end_addr_d @[lsu_lsc_ctl.scala 110:24] + inst addrcheck of lsu_addrcheck @[lsu_lsc_ctl.scala 113:25] + addrcheck.clock <= clock + addrcheck.reset <= reset + addrcheck.io.lsu_c2_m_clk <= io.lsu_c2_m_clk @[lsu_lsc_ctl.scala 115:42] + addrcheck.io.start_addr_d <= full_addr_d @[lsu_lsc_ctl.scala 117:42] + addrcheck.io.end_addr_d <= full_end_addr_d @[lsu_lsc_ctl.scala 118:42] + addrcheck.io.lsu_pkt_d.bits.store_data_bypass_m <= io.lsu_pkt_d.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 119:42] + addrcheck.io.lsu_pkt_d.bits.load_ldst_bypass_d <= io.lsu_pkt_d.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 119:42] + addrcheck.io.lsu_pkt_d.bits.store_data_bypass_d <= io.lsu_pkt_d.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 119:42] + addrcheck.io.lsu_pkt_d.bits.dma <= io.lsu_pkt_d.bits.dma @[lsu_lsc_ctl.scala 119:42] + addrcheck.io.lsu_pkt_d.bits.unsign <= io.lsu_pkt_d.bits.unsign @[lsu_lsc_ctl.scala 119:42] + addrcheck.io.lsu_pkt_d.bits.store <= io.lsu_pkt_d.bits.store @[lsu_lsc_ctl.scala 119:42] + addrcheck.io.lsu_pkt_d.bits.load <= io.lsu_pkt_d.bits.load @[lsu_lsc_ctl.scala 119:42] + addrcheck.io.lsu_pkt_d.bits.dword <= io.lsu_pkt_d.bits.dword @[lsu_lsc_ctl.scala 119:42] + addrcheck.io.lsu_pkt_d.bits.word <= io.lsu_pkt_d.bits.word @[lsu_lsc_ctl.scala 119:42] + addrcheck.io.lsu_pkt_d.bits.half <= io.lsu_pkt_d.bits.half @[lsu_lsc_ctl.scala 119:42] + addrcheck.io.lsu_pkt_d.bits.by <= io.lsu_pkt_d.bits.by @[lsu_lsc_ctl.scala 119:42] + addrcheck.io.lsu_pkt_d.bits.fast_int <= io.lsu_pkt_d.bits.fast_int @[lsu_lsc_ctl.scala 119:42] + addrcheck.io.lsu_pkt_d.valid <= io.lsu_pkt_d.valid @[lsu_lsc_ctl.scala 119:42] + addrcheck.io.dec_tlu_mrac_ff <= io.dec_tlu_mrac_ff @[lsu_lsc_ctl.scala 120:42] + node _T_66 = bits(rs1_d, 31, 28) @[lsu_lsc_ctl.scala 121:50] + addrcheck.io.rs1_region_d <= _T_66 @[lsu_lsc_ctl.scala 121:42] + addrcheck.io.rs1_d <= rs1_d @[lsu_lsc_ctl.scala 122:42] + io.is_sideeffects_m <= addrcheck.io.is_sideeffects_m @[lsu_lsc_ctl.scala 123:42] + io.addr_in_dccm_d <= addrcheck.io.addr_in_dccm_d @[lsu_lsc_ctl.scala 124:42] + io.addr_in_pic_d <= addrcheck.io.addr_in_pic_d @[lsu_lsc_ctl.scala 125:42] + addrcheck.io.scan_mode <= io.scan_mode @[lsu_lsc_ctl.scala 132:42] + wire exc_mscause_r : UInt<4> + exc_mscause_r <= UInt<4>("h00") + wire fir_dccm_access_error_r : UInt<1> + fir_dccm_access_error_r <= UInt<1>("h00") + wire fir_nondccm_access_error_r : UInt<1> + fir_nondccm_access_error_r <= UInt<1>("h00") + wire access_fault_r : UInt<1> + access_fault_r <= UInt<1>("h00") + wire misaligned_fault_r : UInt<1> + misaligned_fault_r <= UInt<1>("h00") + wire lsu_fir_error_m : UInt<2> + lsu_fir_error_m <= UInt<2>("h00") + wire fir_dccm_access_error_m : UInt<1> + fir_dccm_access_error_m <= UInt<1>("h00") + wire fir_nondccm_access_error_m : UInt<1> + fir_nondccm_access_error_m <= UInt<1>("h00") + reg access_fault_m : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 144:75] + access_fault_m <= addrcheck.io.access_fault_d @[lsu_lsc_ctl.scala 144:75] + reg misaligned_fault_m : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 145:75] + misaligned_fault_m <= addrcheck.io.misaligned_fault_d @[lsu_lsc_ctl.scala 145:75] + reg exc_mscause_m : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 146:75] + exc_mscause_m <= addrcheck.io.exc_mscause_d @[lsu_lsc_ctl.scala 146:75] + reg _T_67 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 147:75] + _T_67 <= addrcheck.io.fir_dccm_access_error_d @[lsu_lsc_ctl.scala 147:75] + fir_dccm_access_error_m <= _T_67 @[lsu_lsc_ctl.scala 147:38] + reg _T_68 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 148:75] + _T_68 <= addrcheck.io.fir_nondccm_access_error_d @[lsu_lsc_ctl.scala 148:75] + fir_nondccm_access_error_m <= _T_68 @[lsu_lsc_ctl.scala 148:38] + node _T_69 = or(access_fault_m, misaligned_fault_m) @[lsu_lsc_ctl.scala 150:34] + io.lsu_exc_m <= _T_69 @[lsu_lsc_ctl.scala 150:16] + node _T_70 = eq(io.lsu_double_ecc_error_r, UInt<1>("h00")) @[lsu_lsc_ctl.scala 151:64] + node _T_71 = and(io.lsu_single_ecc_error_r, _T_70) @[lsu_lsc_ctl.scala 151:62] + node _T_72 = or(io.lsu_commit_r, io.lsu_pkt_r.bits.dma) @[lsu_lsc_ctl.scala 151:111] + node _T_73 = and(_T_71, _T_72) @[lsu_lsc_ctl.scala 151:92] + node _T_74 = and(_T_73, io.lsu_pkt_r.valid) @[lsu_lsc_ctl.scala 151:136] + io.lsu_single_ecc_error_incr <= _T_74 @[lsu_lsc_ctl.scala 151:32] + node _T_75 = or(access_fault_m, misaligned_fault_m) @[lsu_lsc_ctl.scala 173:46] + node _T_76 = or(_T_75, io.lsu_double_ecc_error_m) @[lsu_lsc_ctl.scala 173:67] + node _T_77 = and(_T_76, io.lsu_pkt_m.valid) @[lsu_lsc_ctl.scala 173:96] + node _T_78 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 173:119] + node _T_79 = and(_T_77, _T_78) @[lsu_lsc_ctl.scala 173:117] + node _T_80 = eq(io.lsu_pkt_m.bits.fast_int, UInt<1>("h00")) @[lsu_lsc_ctl.scala 173:144] + node _T_81 = and(_T_79, _T_80) @[lsu_lsc_ctl.scala 173:142] + node _T_82 = eq(io.flush_m_up, UInt<1>("h00")) @[lsu_lsc_ctl.scala 173:174] + node _T_83 = and(_T_81, _T_82) @[lsu_lsc_ctl.scala 173:172] + lsu_error_pkt_m.valid <= _T_83 @[lsu_lsc_ctl.scala 173:27] + node _T_84 = eq(lsu_error_pkt_m.valid, UInt<1>("h00")) @[lsu_lsc_ctl.scala 174:75] + node _T_85 = and(io.lsu_single_ecc_error_m, _T_84) @[lsu_lsc_ctl.scala 174:73] + node _T_86 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 174:101] + node _T_87 = and(_T_85, _T_86) @[lsu_lsc_ctl.scala 174:99] + lsu_error_pkt_m.bits.single_ecc_error <= _T_87 @[lsu_lsc_ctl.scala 174:43] + lsu_error_pkt_m.bits.inst_type <= io.lsu_pkt_m.bits.store @[lsu_lsc_ctl.scala 175:43] + node _T_88 = not(misaligned_fault_m) @[lsu_lsc_ctl.scala 176:46] + lsu_error_pkt_m.bits.exc_type <= _T_88 @[lsu_lsc_ctl.scala 176:43] + node _T_89 = eq(misaligned_fault_m, UInt<1>("h00")) @[lsu_lsc_ctl.scala 177:80] + node _T_90 = and(io.lsu_double_ecc_error_m, _T_89) @[lsu_lsc_ctl.scala 177:78] + node _T_91 = eq(access_fault_m, UInt<1>("h00")) @[lsu_lsc_ctl.scala 177:102] + node _T_92 = and(_T_90, _T_91) @[lsu_lsc_ctl.scala 177:100] + node _T_93 = eq(_T_92, UInt<1>("h01")) @[lsu_lsc_ctl.scala 177:118] + node _T_94 = bits(exc_mscause_m, 3, 0) @[lsu_lsc_ctl.scala 177:149] + node _T_95 = mux(_T_93, UInt<4>("h01"), _T_94) @[lsu_lsc_ctl.scala 177:49] + lsu_error_pkt_m.bits.mscause <= _T_95 @[lsu_lsc_ctl.scala 177:43] + node _T_96 = bits(io.lsu_addr_m, 31, 0) @[lsu_lsc_ctl.scala 178:59] + lsu_error_pkt_m.bits.addr <= _T_96 @[lsu_lsc_ctl.scala 178:43] + node _T_97 = bits(fir_nondccm_access_error_m, 0, 0) @[lsu_lsc_ctl.scala 179:72] + node _T_98 = bits(fir_dccm_access_error_m, 0, 0) @[lsu_lsc_ctl.scala 179:117] + node _T_99 = and(io.lsu_pkt_m.bits.fast_int, io.lsu_double_ecc_error_m) @[lsu_lsc_ctl.scala 179:166] + node _T_100 = bits(_T_99, 0, 0) @[lsu_lsc_ctl.scala 179:195] + node _T_101 = mux(_T_100, UInt<2>("h01"), UInt<2>("h00")) @[lsu_lsc_ctl.scala 179:137] + node _T_102 = mux(_T_98, UInt<2>("h02"), _T_101) @[lsu_lsc_ctl.scala 179:92] + node _T_103 = mux(_T_97, UInt<2>("h03"), _T_102) @[lsu_lsc_ctl.scala 179:44] + lsu_fir_error_m <= _T_103 @[lsu_lsc_ctl.scala 179:38] + wire _T_104 : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}} @[lsu_lsc_ctl.scala 180:104] + _T_104.bits.addr <= UInt<32>("h00") @[lsu_lsc_ctl.scala 180:104] + _T_104.bits.mscause <= UInt<4>("h00") @[lsu_lsc_ctl.scala 180:104] + _T_104.bits.exc_type <= UInt<1>("h00") @[lsu_lsc_ctl.scala 180:104] + _T_104.bits.inst_type <= UInt<1>("h00") @[lsu_lsc_ctl.scala 180:104] + _T_104.bits.single_ecc_error <= UInt<1>("h00") @[lsu_lsc_ctl.scala 180:104] + _T_104.valid <= UInt<1>("h00") @[lsu_lsc_ctl.scala 180:104] + reg _T_105 : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, io.lsu_c2_r_clk with : (reset => (reset, _T_104)) @[lsu_lsc_ctl.scala 180:75] + _T_105.bits.addr <= lsu_error_pkt_m.bits.addr @[lsu_lsc_ctl.scala 180:75] + _T_105.bits.mscause <= lsu_error_pkt_m.bits.mscause @[lsu_lsc_ctl.scala 180:75] + _T_105.bits.exc_type <= lsu_error_pkt_m.bits.exc_type @[lsu_lsc_ctl.scala 180:75] + _T_105.bits.inst_type <= lsu_error_pkt_m.bits.inst_type @[lsu_lsc_ctl.scala 180:75] + _T_105.bits.single_ecc_error <= lsu_error_pkt_m.bits.single_ecc_error @[lsu_lsc_ctl.scala 180:75] + _T_105.valid <= lsu_error_pkt_m.valid @[lsu_lsc_ctl.scala 180:75] + io.lsu_error_pkt_r.bits.addr <= _T_105.bits.addr @[lsu_lsc_ctl.scala 180:38] + io.lsu_error_pkt_r.bits.mscause <= _T_105.bits.mscause @[lsu_lsc_ctl.scala 180:38] + io.lsu_error_pkt_r.bits.exc_type <= _T_105.bits.exc_type @[lsu_lsc_ctl.scala 180:38] + io.lsu_error_pkt_r.bits.inst_type <= _T_105.bits.inst_type @[lsu_lsc_ctl.scala 180:38] + io.lsu_error_pkt_r.bits.single_ecc_error <= _T_105.bits.single_ecc_error @[lsu_lsc_ctl.scala 180:38] + io.lsu_error_pkt_r.valid <= _T_105.valid @[lsu_lsc_ctl.scala 180:38] + reg _T_106 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 181:75] + _T_106 <= lsu_fir_error_m @[lsu_lsc_ctl.scala 181:75] + io.lsu_fir_error <= _T_106 @[lsu_lsc_ctl.scala 181:38] + dma_pkt_d.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 183:27] + dma_pkt_d.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 184:27] + dma_pkt_d.valid <= io.dma_lsc_ctl.dma_dccm_req @[lsu_lsc_ctl.scala 185:22] + dma_pkt_d.bits.dma <= UInt<1>("h01") @[lsu_lsc_ctl.scala 186:27] + dma_pkt_d.bits.store <= io.dma_lsc_ctl.dma_mem_write @[lsu_lsc_ctl.scala 187:27] + node _T_107 = not(io.dma_lsc_ctl.dma_mem_write) @[lsu_lsc_ctl.scala 188:30] + dma_pkt_d.bits.load <= _T_107 @[lsu_lsc_ctl.scala 188:27] + node _T_108 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 189:56] + node _T_109 = eq(_T_108, UInt<3>("h00")) @[lsu_lsc_ctl.scala 189:62] + dma_pkt_d.bits.by <= _T_109 @[lsu_lsc_ctl.scala 189:27] + node _T_110 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 190:56] + node _T_111 = eq(_T_110, UInt<3>("h01")) @[lsu_lsc_ctl.scala 190:62] + dma_pkt_d.bits.half <= _T_111 @[lsu_lsc_ctl.scala 190:27] + node _T_112 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 191:56] + node _T_113 = eq(_T_112, UInt<3>("h02")) @[lsu_lsc_ctl.scala 191:62] + dma_pkt_d.bits.word <= _T_113 @[lsu_lsc_ctl.scala 191:27] + node _T_114 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 192:56] + node _T_115 = eq(_T_114, UInt<3>("h03")) @[lsu_lsc_ctl.scala 192:62] + dma_pkt_d.bits.dword <= _T_115 @[lsu_lsc_ctl.scala 192:27] + dma_pkt_d.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 193:39] + dma_pkt_d.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 194:39] + dma_pkt_d.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 195:39] + wire lsu_ld_datafn_r : UInt<32> + lsu_ld_datafn_r <= UInt<32>("h00") + wire lsu_ld_datafn_corr_r : UInt<32> + lsu_ld_datafn_corr_r <= UInt<32>("h00") + wire lsu_ld_datafn_m : UInt<32> + lsu_ld_datafn_m <= UInt<32>("h00") + node _T_116 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[lsu_lsc_ctl.scala 201:50] + node _T_117 = mux(_T_116, io.lsu_p, dma_pkt_d) @[lsu_lsc_ctl.scala 201:26] + io.lsu_pkt_d.bits.store_data_bypass_m <= _T_117.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 201:20] + io.lsu_pkt_d.bits.load_ldst_bypass_d <= _T_117.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 201:20] + io.lsu_pkt_d.bits.store_data_bypass_d <= _T_117.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 201:20] + io.lsu_pkt_d.bits.dma <= _T_117.bits.dma @[lsu_lsc_ctl.scala 201:20] + io.lsu_pkt_d.bits.unsign <= _T_117.bits.unsign @[lsu_lsc_ctl.scala 201:20] + io.lsu_pkt_d.bits.store <= _T_117.bits.store @[lsu_lsc_ctl.scala 201:20] + io.lsu_pkt_d.bits.load <= _T_117.bits.load @[lsu_lsc_ctl.scala 201:20] + io.lsu_pkt_d.bits.dword <= _T_117.bits.dword @[lsu_lsc_ctl.scala 201:20] + io.lsu_pkt_d.bits.word <= _T_117.bits.word @[lsu_lsc_ctl.scala 201:20] + io.lsu_pkt_d.bits.half <= _T_117.bits.half @[lsu_lsc_ctl.scala 201:20] + io.lsu_pkt_d.bits.by <= _T_117.bits.by @[lsu_lsc_ctl.scala 201:20] + io.lsu_pkt_d.bits.fast_int <= _T_117.bits.fast_int @[lsu_lsc_ctl.scala 201:20] + io.lsu_pkt_d.valid <= _T_117.valid @[lsu_lsc_ctl.scala 201:20] + lsu_pkt_m_in.bits.store_data_bypass_m <= io.lsu_pkt_d.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 202:20] + lsu_pkt_m_in.bits.load_ldst_bypass_d <= io.lsu_pkt_d.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 202:20] + lsu_pkt_m_in.bits.store_data_bypass_d <= io.lsu_pkt_d.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 202:20] + lsu_pkt_m_in.bits.dma <= io.lsu_pkt_d.bits.dma @[lsu_lsc_ctl.scala 202:20] + lsu_pkt_m_in.bits.unsign <= io.lsu_pkt_d.bits.unsign @[lsu_lsc_ctl.scala 202:20] + lsu_pkt_m_in.bits.store <= io.lsu_pkt_d.bits.store @[lsu_lsc_ctl.scala 202:20] + lsu_pkt_m_in.bits.load <= io.lsu_pkt_d.bits.load @[lsu_lsc_ctl.scala 202:20] + lsu_pkt_m_in.bits.dword <= io.lsu_pkt_d.bits.dword @[lsu_lsc_ctl.scala 202:20] + lsu_pkt_m_in.bits.word <= io.lsu_pkt_d.bits.word @[lsu_lsc_ctl.scala 202:20] + lsu_pkt_m_in.bits.half <= io.lsu_pkt_d.bits.half @[lsu_lsc_ctl.scala 202:20] + lsu_pkt_m_in.bits.by <= io.lsu_pkt_d.bits.by @[lsu_lsc_ctl.scala 202:20] + lsu_pkt_m_in.bits.fast_int <= io.lsu_pkt_d.bits.fast_int @[lsu_lsc_ctl.scala 202:20] + lsu_pkt_m_in.valid <= io.lsu_pkt_d.valid @[lsu_lsc_ctl.scala 202:20] + lsu_pkt_r_in.bits.store_data_bypass_m <= io.lsu_pkt_m.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 203:20] + lsu_pkt_r_in.bits.load_ldst_bypass_d <= io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 203:20] + lsu_pkt_r_in.bits.store_data_bypass_d <= io.lsu_pkt_m.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 203:20] + lsu_pkt_r_in.bits.dma <= io.lsu_pkt_m.bits.dma @[lsu_lsc_ctl.scala 203:20] + lsu_pkt_r_in.bits.unsign <= io.lsu_pkt_m.bits.unsign @[lsu_lsc_ctl.scala 203:20] + lsu_pkt_r_in.bits.store <= io.lsu_pkt_m.bits.store @[lsu_lsc_ctl.scala 203:20] + lsu_pkt_r_in.bits.load <= io.lsu_pkt_m.bits.load @[lsu_lsc_ctl.scala 203:20] + lsu_pkt_r_in.bits.dword <= io.lsu_pkt_m.bits.dword @[lsu_lsc_ctl.scala 203:20] + lsu_pkt_r_in.bits.word <= io.lsu_pkt_m.bits.word @[lsu_lsc_ctl.scala 203:20] + lsu_pkt_r_in.bits.half <= io.lsu_pkt_m.bits.half @[lsu_lsc_ctl.scala 203:20] + lsu_pkt_r_in.bits.by <= io.lsu_pkt_m.bits.by @[lsu_lsc_ctl.scala 203:20] + lsu_pkt_r_in.bits.fast_int <= io.lsu_pkt_m.bits.fast_int @[lsu_lsc_ctl.scala 203:20] + lsu_pkt_r_in.valid <= io.lsu_pkt_m.valid @[lsu_lsc_ctl.scala 203:20] + node _T_118 = eq(io.lsu_p.bits.fast_int, UInt<1>("h00")) @[lsu_lsc_ctl.scala 205:64] + node _T_119 = and(io.flush_m_up, _T_118) @[lsu_lsc_ctl.scala 205:61] + node _T_120 = eq(_T_119, UInt<1>("h00")) @[lsu_lsc_ctl.scala 205:45] + node _T_121 = and(io.lsu_p.valid, _T_120) @[lsu_lsc_ctl.scala 205:43] + node _T_122 = or(_T_121, io.dma_lsc_ctl.dma_dccm_req) @[lsu_lsc_ctl.scala 205:90] + io.lsu_pkt_d.valid <= _T_122 @[lsu_lsc_ctl.scala 205:24] + node _T_123 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 206:68] + node _T_124 = and(io.flush_m_up, _T_123) @[lsu_lsc_ctl.scala 206:65] + node _T_125 = eq(_T_124, UInt<1>("h00")) @[lsu_lsc_ctl.scala 206:49] + node _T_126 = and(io.lsu_pkt_d.valid, _T_125) @[lsu_lsc_ctl.scala 206:47] + lsu_pkt_m_in.valid <= _T_126 @[lsu_lsc_ctl.scala 206:24] + node _T_127 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 207:68] + node _T_128 = and(io.flush_m_up, _T_127) @[lsu_lsc_ctl.scala 207:65] + node _T_129 = eq(_T_128, UInt<1>("h00")) @[lsu_lsc_ctl.scala 207:49] + node _T_130 = and(io.lsu_pkt_m.valid, _T_129) @[lsu_lsc_ctl.scala 207:47] + lsu_pkt_r_in.valid <= _T_130 @[lsu_lsc_ctl.scala 207:24] + wire _T_131 : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 209:91] + _T_131.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 209:91] + _T_131.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 209:91] + _T_131.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 209:91] + _T_131.bits.dma <= UInt<1>("h00") @[lsu_lsc_ctl.scala 209:91] + _T_131.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 209:91] + _T_131.bits.store <= UInt<1>("h00") @[lsu_lsc_ctl.scala 209:91] + _T_131.bits.load <= UInt<1>("h00") @[lsu_lsc_ctl.scala 209:91] + _T_131.bits.dword <= UInt<1>("h00") @[lsu_lsc_ctl.scala 209:91] + _T_131.bits.word <= UInt<1>("h00") @[lsu_lsc_ctl.scala 209:91] + _T_131.bits.half <= UInt<1>("h00") @[lsu_lsc_ctl.scala 209:91] + _T_131.bits.by <= UInt<1>("h00") @[lsu_lsc_ctl.scala 209:91] + _T_131.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 209:91] + _T_131.valid <= UInt<1>("h00") @[lsu_lsc_ctl.scala 209:91] + reg _T_132 : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, io.lsu_c1_m_clk with : (reset => (reset, _T_131)) @[lsu_lsc_ctl.scala 209:65] + _T_132.bits.store_data_bypass_m <= lsu_pkt_m_in.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 209:65] + _T_132.bits.load_ldst_bypass_d <= lsu_pkt_m_in.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 209:65] + _T_132.bits.store_data_bypass_d <= lsu_pkt_m_in.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 209:65] + _T_132.bits.dma <= lsu_pkt_m_in.bits.dma @[lsu_lsc_ctl.scala 209:65] + _T_132.bits.unsign <= lsu_pkt_m_in.bits.unsign @[lsu_lsc_ctl.scala 209:65] + _T_132.bits.store <= lsu_pkt_m_in.bits.store @[lsu_lsc_ctl.scala 209:65] + _T_132.bits.load <= lsu_pkt_m_in.bits.load @[lsu_lsc_ctl.scala 209:65] + _T_132.bits.dword <= lsu_pkt_m_in.bits.dword @[lsu_lsc_ctl.scala 209:65] + _T_132.bits.word <= lsu_pkt_m_in.bits.word @[lsu_lsc_ctl.scala 209:65] + _T_132.bits.half <= lsu_pkt_m_in.bits.half @[lsu_lsc_ctl.scala 209:65] + _T_132.bits.by <= lsu_pkt_m_in.bits.by @[lsu_lsc_ctl.scala 209:65] + _T_132.bits.fast_int <= lsu_pkt_m_in.bits.fast_int @[lsu_lsc_ctl.scala 209:65] + _T_132.valid <= lsu_pkt_m_in.valid @[lsu_lsc_ctl.scala 209:65] + io.lsu_pkt_m.bits.store_data_bypass_m <= _T_132.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 209:28] + io.lsu_pkt_m.bits.load_ldst_bypass_d <= _T_132.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 209:28] + io.lsu_pkt_m.bits.store_data_bypass_d <= _T_132.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 209:28] + io.lsu_pkt_m.bits.dma <= _T_132.bits.dma @[lsu_lsc_ctl.scala 209:28] + io.lsu_pkt_m.bits.unsign <= _T_132.bits.unsign @[lsu_lsc_ctl.scala 209:28] + io.lsu_pkt_m.bits.store <= _T_132.bits.store @[lsu_lsc_ctl.scala 209:28] + io.lsu_pkt_m.bits.load <= _T_132.bits.load @[lsu_lsc_ctl.scala 209:28] + io.lsu_pkt_m.bits.dword <= _T_132.bits.dword @[lsu_lsc_ctl.scala 209:28] + io.lsu_pkt_m.bits.word <= _T_132.bits.word @[lsu_lsc_ctl.scala 209:28] + io.lsu_pkt_m.bits.half <= _T_132.bits.half @[lsu_lsc_ctl.scala 209:28] + io.lsu_pkt_m.bits.by <= _T_132.bits.by @[lsu_lsc_ctl.scala 209:28] + io.lsu_pkt_m.bits.fast_int <= _T_132.bits.fast_int @[lsu_lsc_ctl.scala 209:28] + io.lsu_pkt_m.valid <= _T_132.valid @[lsu_lsc_ctl.scala 209:28] + wire _T_133 : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 210:91] + _T_133.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 210:91] + _T_133.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 210:91] + _T_133.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 210:91] + _T_133.bits.dma <= UInt<1>("h00") @[lsu_lsc_ctl.scala 210:91] + _T_133.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 210:91] + _T_133.bits.store <= UInt<1>("h00") @[lsu_lsc_ctl.scala 210:91] + _T_133.bits.load <= UInt<1>("h00") @[lsu_lsc_ctl.scala 210:91] + _T_133.bits.dword <= UInt<1>("h00") @[lsu_lsc_ctl.scala 210:91] + _T_133.bits.word <= UInt<1>("h00") @[lsu_lsc_ctl.scala 210:91] + _T_133.bits.half <= UInt<1>("h00") @[lsu_lsc_ctl.scala 210:91] + _T_133.bits.by <= UInt<1>("h00") @[lsu_lsc_ctl.scala 210:91] + _T_133.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 210:91] + _T_133.valid <= UInt<1>("h00") @[lsu_lsc_ctl.scala 210:91] + reg _T_134 : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, io.lsu_c1_r_clk with : (reset => (reset, _T_133)) @[lsu_lsc_ctl.scala 210:65] + _T_134.bits.store_data_bypass_m <= lsu_pkt_r_in.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 210:65] + _T_134.bits.load_ldst_bypass_d <= lsu_pkt_r_in.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 210:65] + _T_134.bits.store_data_bypass_d <= lsu_pkt_r_in.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 210:65] + _T_134.bits.dma <= lsu_pkt_r_in.bits.dma @[lsu_lsc_ctl.scala 210:65] + _T_134.bits.unsign <= lsu_pkt_r_in.bits.unsign @[lsu_lsc_ctl.scala 210:65] + _T_134.bits.store <= lsu_pkt_r_in.bits.store @[lsu_lsc_ctl.scala 210:65] + _T_134.bits.load <= lsu_pkt_r_in.bits.load @[lsu_lsc_ctl.scala 210:65] + _T_134.bits.dword <= lsu_pkt_r_in.bits.dword @[lsu_lsc_ctl.scala 210:65] + _T_134.bits.word <= lsu_pkt_r_in.bits.word @[lsu_lsc_ctl.scala 210:65] + _T_134.bits.half <= lsu_pkt_r_in.bits.half @[lsu_lsc_ctl.scala 210:65] + _T_134.bits.by <= lsu_pkt_r_in.bits.by @[lsu_lsc_ctl.scala 210:65] + _T_134.bits.fast_int <= lsu_pkt_r_in.bits.fast_int @[lsu_lsc_ctl.scala 210:65] + _T_134.valid <= lsu_pkt_r_in.valid @[lsu_lsc_ctl.scala 210:65] + io.lsu_pkt_r.bits.store_data_bypass_m <= _T_134.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 210:28] + io.lsu_pkt_r.bits.load_ldst_bypass_d <= _T_134.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 210:28] + io.lsu_pkt_r.bits.store_data_bypass_d <= _T_134.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 210:28] + io.lsu_pkt_r.bits.dma <= _T_134.bits.dma @[lsu_lsc_ctl.scala 210:28] + io.lsu_pkt_r.bits.unsign <= _T_134.bits.unsign @[lsu_lsc_ctl.scala 210:28] + io.lsu_pkt_r.bits.store <= _T_134.bits.store @[lsu_lsc_ctl.scala 210:28] + io.lsu_pkt_r.bits.load <= _T_134.bits.load @[lsu_lsc_ctl.scala 210:28] + io.lsu_pkt_r.bits.dword <= _T_134.bits.dword @[lsu_lsc_ctl.scala 210:28] + io.lsu_pkt_r.bits.word <= _T_134.bits.word @[lsu_lsc_ctl.scala 210:28] + io.lsu_pkt_r.bits.half <= _T_134.bits.half @[lsu_lsc_ctl.scala 210:28] + io.lsu_pkt_r.bits.by <= _T_134.bits.by @[lsu_lsc_ctl.scala 210:28] + io.lsu_pkt_r.bits.fast_int <= _T_134.bits.fast_int @[lsu_lsc_ctl.scala 210:28] + io.lsu_pkt_r.valid <= _T_134.valid @[lsu_lsc_ctl.scala 210:28] + reg _T_135 : UInt<1>, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 211:65] + _T_135 <= lsu_pkt_m_in.valid @[lsu_lsc_ctl.scala 211:65] + io.lsu_pkt_m.valid <= _T_135 @[lsu_lsc_ctl.scala 211:28] + reg _T_136 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 212:65] + _T_136 <= lsu_pkt_r_in.valid @[lsu_lsc_ctl.scala 212:65] + io.lsu_pkt_r.valid <= _T_136 @[lsu_lsc_ctl.scala 212:28] + node _T_137 = bits(io.dma_lsc_ctl.dma_mem_wdata, 63, 0) @[lsu_lsc_ctl.scala 214:59] + node _T_138 = bits(io.dma_lsc_ctl.dma_mem_addr, 2, 0) @[lsu_lsc_ctl.scala 214:100] + node _T_139 = cat(_T_138, UInt<3>("h00")) @[Cat.scala 29:58] + node dma_mem_wdata_shifted = dshr(_T_137, _T_139) @[lsu_lsc_ctl.scala 214:66] + node _T_140 = bits(io.dma_lsc_ctl.dma_dccm_req, 0, 0) @[lsu_lsc_ctl.scala 215:63] + node _T_141 = bits(dma_mem_wdata_shifted, 31, 0) @[lsu_lsc_ctl.scala 215:91] + node _T_142 = bits(io.lsu_exu.exu_lsu_rs2_d, 31, 0) @[lsu_lsc_ctl.scala 215:122] + node store_data_d = mux(_T_140, _T_141, _T_142) @[lsu_lsc_ctl.scala 215:34] + node _T_143 = bits(io.lsu_pkt_d.bits.store_data_bypass_d, 0, 0) @[lsu_lsc_ctl.scala 216:73] + node _T_144 = bits(io.lsu_result_m, 31, 0) @[lsu_lsc_ctl.scala 216:95] + node _T_145 = bits(store_data_d, 31, 0) @[lsu_lsc_ctl.scala 216:114] + node store_data_m_in = mux(_T_143, _T_144, _T_145) @[lsu_lsc_ctl.scala 216:34] + reg store_data_pre_m : UInt, io.lsu_store_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 218:72] + store_data_pre_m <= store_data_m_in @[lsu_lsc_ctl.scala 218:72] + reg _T_146 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 219:62] + _T_146 <= io.lsu_addr_d @[lsu_lsc_ctl.scala 219:62] + io.lsu_addr_m <= _T_146 @[lsu_lsc_ctl.scala 219:24] + reg _T_147 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 220:62] + _T_147 <= io.lsu_addr_m @[lsu_lsc_ctl.scala 220:62] + io.lsu_addr_r <= _T_147 @[lsu_lsc_ctl.scala 220:24] + reg _T_148 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 221:62] + _T_148 <= io.end_addr_d @[lsu_lsc_ctl.scala 221:62] + io.end_addr_m <= _T_148 @[lsu_lsc_ctl.scala 221:24] + reg _T_149 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 222:62] + _T_149 <= io.end_addr_m @[lsu_lsc_ctl.scala 222:62] + io.end_addr_r <= _T_149 @[lsu_lsc_ctl.scala 222:24] + reg _T_150 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 223:62] + _T_150 <= io.addr_in_dccm_d @[lsu_lsc_ctl.scala 223:62] + io.addr_in_dccm_m <= _T_150 @[lsu_lsc_ctl.scala 223:24] + reg _T_151 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 224:62] + _T_151 <= io.addr_in_dccm_m @[lsu_lsc_ctl.scala 224:62] + io.addr_in_dccm_r <= _T_151 @[lsu_lsc_ctl.scala 224:24] + reg _T_152 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 225:62] + _T_152 <= io.addr_in_pic_d @[lsu_lsc_ctl.scala 225:62] + io.addr_in_pic_m <= _T_152 @[lsu_lsc_ctl.scala 225:24] + reg _T_153 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 226:62] + _T_153 <= io.addr_in_pic_m @[lsu_lsc_ctl.scala 226:62] + io.addr_in_pic_r <= _T_153 @[lsu_lsc_ctl.scala 226:24] + reg _T_154 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 227:62] + _T_154 <= addrcheck.io.addr_external_d @[lsu_lsc_ctl.scala 227:62] + io.addr_external_m <= _T_154 @[lsu_lsc_ctl.scala 227:24] + reg addr_external_r : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 228:66] + addr_external_r <= io.addr_external_m @[lsu_lsc_ctl.scala 228:66] + reg bus_read_data_r : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 229:66] + bus_read_data_r <= io.bus_read_data_m @[lsu_lsc_ctl.scala 229:66] + node _T_155 = bits(io.lsu_ld_data_corr_r, 31, 1) @[lsu_lsc_ctl.scala 231:52] + io.lsu_fir_addr <= _T_155 @[lsu_lsc_ctl.scala 231:28] + io.lsu_addr_d <= full_addr_d @[lsu_lsc_ctl.scala 233:28] + node _T_156 = or(io.lsu_pkt_r.bits.store, io.lsu_pkt_r.bits.load) @[lsu_lsc_ctl.scala 235:68] + node _T_157 = and(io.lsu_pkt_r.valid, _T_156) @[lsu_lsc_ctl.scala 235:41] + node _T_158 = eq(io.flush_r, UInt<1>("h00")) @[lsu_lsc_ctl.scala 235:96] + node _T_159 = and(_T_157, _T_158) @[lsu_lsc_ctl.scala 235:94] + node _T_160 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 235:110] + node _T_161 = and(_T_159, _T_160) @[lsu_lsc_ctl.scala 235:108] + io.lsu_commit_r <= _T_161 @[lsu_lsc_ctl.scala 235:19] + node _T_162 = bits(io.picm_mask_data_m, 31, 0) @[lsu_lsc_ctl.scala 236:52] + node _T_163 = eq(io.addr_in_pic_m, UInt<1>("h00")) @[lsu_lsc_ctl.scala 236:69] + node _T_164 = bits(_T_163, 0, 0) @[Bitwise.scala 72:15] + node _T_165 = mux(_T_164, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_166 = or(_T_162, _T_165) @[lsu_lsc_ctl.scala 236:59] + node _T_167 = bits(io.lsu_pkt_m.bits.store_data_bypass_m, 0, 0) @[lsu_lsc_ctl.scala 236:133] + node _T_168 = mux(_T_167, io.lsu_result_m, store_data_pre_m) @[lsu_lsc_ctl.scala 236:94] + node _T_169 = and(_T_166, _T_168) @[lsu_lsc_ctl.scala 236:89] + io.store_data_m <= _T_169 @[lsu_lsc_ctl.scala 236:29] + node _T_170 = bits(io.addr_external_m, 0, 0) @[lsu_lsc_ctl.scala 257:53] + node _T_171 = mux(_T_170, io.bus_read_data_m, io.lsu_ld_data_m) @[lsu_lsc_ctl.scala 257:33] + lsu_ld_datafn_m <= _T_171 @[lsu_lsc_ctl.scala 257:27] + node _T_172 = eq(addr_external_r, UInt<1>("h01")) @[lsu_lsc_ctl.scala 258:49] + node _T_173 = mux(_T_172, bus_read_data_r, io.lsu_ld_data_corr_r) @[lsu_lsc_ctl.scala 258:33] + lsu_ld_datafn_corr_r <= _T_173 @[lsu_lsc_ctl.scala 258:27] + node _T_174 = and(io.lsu_pkt_m.bits.unsign, io.lsu_pkt_m.bits.by) @[lsu_lsc_ctl.scala 259:66] + node _T_175 = bits(_T_174, 0, 0) @[Bitwise.scala 72:15] + node _T_176 = mux(_T_175, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_177 = bits(lsu_ld_datafn_m, 7, 0) @[lsu_lsc_ctl.scala 259:125] + node _T_178 = cat(UInt<24>("h00"), _T_177) @[Cat.scala 29:58] + node _T_179 = and(_T_176, _T_178) @[lsu_lsc_ctl.scala 259:94] + node _T_180 = and(io.lsu_pkt_m.bits.unsign, io.lsu_pkt_m.bits.half) @[lsu_lsc_ctl.scala 260:43] + node _T_181 = bits(_T_180, 0, 0) @[Bitwise.scala 72:15] + node _T_182 = mux(_T_181, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_183 = bits(lsu_ld_datafn_m, 15, 0) @[lsu_lsc_ctl.scala 260:102] + node _T_184 = cat(UInt<16>("h00"), _T_183) @[Cat.scala 29:58] + node _T_185 = and(_T_182, _T_184) @[lsu_lsc_ctl.scala 260:71] + node _T_186 = or(_T_179, _T_185) @[lsu_lsc_ctl.scala 259:133] + node _T_187 = eq(io.lsu_pkt_m.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 261:17] + node _T_188 = and(_T_187, io.lsu_pkt_m.bits.by) @[lsu_lsc_ctl.scala 261:43] + node _T_189 = bits(_T_188, 0, 0) @[Bitwise.scala 72:15] + node _T_190 = mux(_T_189, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_191 = bits(lsu_ld_datafn_m, 7, 7) @[lsu_lsc_ctl.scala 261:102] + node _T_192 = bits(_T_191, 0, 0) @[Bitwise.scala 72:15] + node _T_193 = mux(_T_192, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12] + node _T_194 = bits(lsu_ld_datafn_m, 7, 0) @[lsu_lsc_ctl.scala 261:125] + node _T_195 = cat(_T_193, _T_194) @[Cat.scala 29:58] + node _T_196 = and(_T_190, _T_195) @[lsu_lsc_ctl.scala 261:71] + node _T_197 = or(_T_186, _T_196) @[lsu_lsc_ctl.scala 260:114] + node _T_198 = eq(io.lsu_pkt_m.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 262:17] + node _T_199 = and(_T_198, io.lsu_pkt_m.bits.half) @[lsu_lsc_ctl.scala 262:43] + node _T_200 = bits(_T_199, 0, 0) @[Bitwise.scala 72:15] + node _T_201 = mux(_T_200, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_202 = bits(lsu_ld_datafn_m, 15, 15) @[lsu_lsc_ctl.scala 262:101] + node _T_203 = bits(_T_202, 0, 0) @[Bitwise.scala 72:15] + node _T_204 = mux(_T_203, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] + node _T_205 = bits(lsu_ld_datafn_m, 15, 0) @[lsu_lsc_ctl.scala 262:125] + node _T_206 = cat(_T_204, _T_205) @[Cat.scala 29:58] + node _T_207 = and(_T_201, _T_206) @[lsu_lsc_ctl.scala 262:71] + node _T_208 = or(_T_197, _T_207) @[lsu_lsc_ctl.scala 261:134] + node _T_209 = bits(io.lsu_pkt_m.bits.word, 0, 0) @[Bitwise.scala 72:15] + node _T_210 = mux(_T_209, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_211 = bits(lsu_ld_datafn_m, 31, 0) @[lsu_lsc_ctl.scala 263:60] + node _T_212 = and(_T_210, _T_211) @[lsu_lsc_ctl.scala 263:43] + node _T_213 = or(_T_208, _T_212) @[lsu_lsc_ctl.scala 262:134] + io.lsu_result_m <= _T_213 @[lsu_lsc_ctl.scala 259:27] + node _T_214 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 264:66] + node _T_215 = bits(_T_214, 0, 0) @[Bitwise.scala 72:15] + node _T_216 = mux(_T_215, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_217 = bits(lsu_ld_datafn_corr_r, 7, 0) @[lsu_lsc_ctl.scala 264:130] + node _T_218 = cat(UInt<24>("h00"), _T_217) @[Cat.scala 29:58] + node _T_219 = and(_T_216, _T_218) @[lsu_lsc_ctl.scala 264:94] + node _T_220 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 265:43] + node _T_221 = bits(_T_220, 0, 0) @[Bitwise.scala 72:15] + node _T_222 = mux(_T_221, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_223 = bits(lsu_ld_datafn_corr_r, 15, 0) @[lsu_lsc_ctl.scala 265:107] + node _T_224 = cat(UInt<16>("h00"), _T_223) @[Cat.scala 29:58] + node _T_225 = and(_T_222, _T_224) @[lsu_lsc_ctl.scala 265:71] + node _T_226 = or(_T_219, _T_225) @[lsu_lsc_ctl.scala 264:138] + node _T_227 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 266:17] + node _T_228 = and(_T_227, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 266:43] + node _T_229 = bits(_T_228, 0, 0) @[Bitwise.scala 72:15] + node _T_230 = mux(_T_229, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_231 = bits(lsu_ld_datafn_corr_r, 7, 7) @[lsu_lsc_ctl.scala 266:107] + node _T_232 = bits(_T_231, 0, 0) @[Bitwise.scala 72:15] + node _T_233 = mux(_T_232, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12] + node _T_234 = bits(lsu_ld_datafn_corr_r, 7, 0) @[lsu_lsc_ctl.scala 266:135] + node _T_235 = cat(_T_233, _T_234) @[Cat.scala 29:58] + node _T_236 = and(_T_230, _T_235) @[lsu_lsc_ctl.scala 266:71] + node _T_237 = or(_T_226, _T_236) @[lsu_lsc_ctl.scala 265:119] + node _T_238 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 267:17] + node _T_239 = and(_T_238, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 267:43] + node _T_240 = bits(_T_239, 0, 0) @[Bitwise.scala 72:15] + node _T_241 = mux(_T_240, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_242 = bits(lsu_ld_datafn_corr_r, 15, 15) @[lsu_lsc_ctl.scala 267:106] + node _T_243 = bits(_T_242, 0, 0) @[Bitwise.scala 72:15] + node _T_244 = mux(_T_243, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] + node _T_245 = bits(lsu_ld_datafn_corr_r, 15, 0) @[lsu_lsc_ctl.scala 267:135] + node _T_246 = cat(_T_244, _T_245) @[Cat.scala 29:58] + node _T_247 = and(_T_241, _T_246) @[lsu_lsc_ctl.scala 267:71] + node _T_248 = or(_T_237, _T_247) @[lsu_lsc_ctl.scala 266:144] + node _T_249 = bits(io.lsu_pkt_r.bits.word, 0, 0) @[Bitwise.scala 72:15] + node _T_250 = mux(_T_249, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_251 = bits(lsu_ld_datafn_corr_r, 31, 0) @[lsu_lsc_ctl.scala 268:65] + node _T_252 = and(_T_250, _T_251) @[lsu_lsc_ctl.scala 268:43] + node _T_253 = or(_T_248, _T_252) @[lsu_lsc_ctl.scala 267:144] + io.lsu_result_corr_r <= _T_253 @[lsu_lsc_ctl.scala 264:27] + + extmodule gated_latch : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_1 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_1 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_1 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + module lsu_dccm_ctl : + input clock : Clock + input reset : AsyncReset + output io : {flip lsu_c2_m_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_free_c2_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_store_c1_r_clk : Clock, flip lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip addr_in_dccm_d : UInt<1>, flip addr_in_dccm_m : UInt<1>, flip addr_in_dccm_r : UInt<1>, flip addr_in_pic_d : UInt<1>, flip addr_in_pic_m : UInt<1>, flip addr_in_pic_r : UInt<1>, flip lsu_raw_fwd_lo_r : UInt<1>, flip lsu_raw_fwd_hi_r : UInt<1>, flip lsu_commit_r : UInt<1>, flip lsu_addr_d : UInt<32>, flip lsu_addr_m : UInt<16>, flip lsu_addr_r : UInt<32>, flip end_addr_d : UInt<16>, flip end_addr_m : UInt<16>, flip end_addr_r : UInt<16>, flip stbuf_reqvld_any : UInt<1>, flip stbuf_addr_any : UInt<16>, flip stbuf_data_any : UInt<32>, flip stbuf_ecc_any : UInt<7>, flip stbuf_fwddata_hi_m : UInt<32>, flip stbuf_fwddata_lo_m : UInt<32>, flip stbuf_fwdbyteen_lo_m : UInt<4>, flip stbuf_fwdbyteen_hi_m : UInt<4>, dccm_rdata_hi_r : UInt<32>, dccm_rdata_lo_r : UInt<32>, dccm_data_ecc_hi_r : UInt<7>, dccm_data_ecc_lo_r : UInt<7>, lsu_ld_data_r : UInt<32>, lsu_ld_data_corr_r : UInt<32>, flip lsu_double_ecc_error_r : UInt<1>, flip single_ecc_error_hi_r : UInt<1>, flip single_ecc_error_lo_r : UInt<1>, flip sec_data_hi_r : UInt<32>, flip sec_data_lo_r : UInt<32>, flip sec_data_hi_r_ff : UInt<32>, flip sec_data_lo_r_ff : UInt<32>, flip sec_data_ecc_hi_r_ff : UInt<7>, flip sec_data_ecc_lo_r_ff : UInt<7>, dccm_rdata_hi_m : UInt<32>, dccm_rdata_lo_m : UInt<32>, dccm_data_ecc_hi_m : UInt<7>, dccm_data_ecc_lo_m : UInt<7>, lsu_ld_data_m : UInt<32>, flip lsu_double_ecc_error_m : UInt<1>, flip sec_data_hi_m : UInt<32>, flip sec_data_lo_m : UInt<32>, flip store_data_m : UInt<32>, flip dma_dccm_wen : UInt<1>, flip dma_pic_wen : UInt<1>, flip dma_mem_tag_m : UInt<3>, flip dma_dccm_wdata_lo : UInt<32>, flip dma_dccm_wdata_hi : UInt<32>, flip dma_dccm_wdata_ecc_hi : UInt<7>, flip dma_dccm_wdata_ecc_lo : UInt<7>, store_data_hi_r : UInt<32>, store_data_lo_r : UInt<32>, store_datafn_hi_r : UInt<32>, store_datafn_lo_r : UInt<32>, store_data_r : UInt<32>, ld_single_ecc_error_r : UInt<1>, ld_single_ecc_error_r_ff : UInt<1>, picm_mask_data_m : UInt<32>, lsu_stbuf_commit_any : UInt<1>, lsu_dccm_rden_m : UInt<1>, lsu_dccm_rden_r : UInt<1>, dma_dccm_ctl : {flip dma_mem_addr : UInt<32>, flip dma_mem_wdata : UInt<64>, dccm_dma_rvalid : UInt<1>, dccm_dma_ecc_error : UInt<1>, dccm_dma_rtag : UInt<3>, dccm_dma_rdata : UInt<64>}, flip dccm : {flip wren : UInt<1>, flip rden : UInt<1>, flip wr_addr_lo : UInt<16>, flip wr_addr_hi : UInt<16>, flip rd_addr_lo : UInt<16>, flip rd_addr_hi : UInt<16>, flip wr_data_lo : UInt<39>, flip wr_data_hi : UInt<39>, rd_data_lo : UInt<39>, rd_data_hi : UInt<39>}, lsu_pic : {picm_wren : UInt<1>, picm_rden : UInt<1>, picm_mken : UInt<1>, picm_rdaddr : UInt<32>, picm_wraddr : UInt<32>, picm_wr_data : UInt<32>, flip picm_rd_data : UInt<32>}, flip scan_mode : UInt<1>} + + node picm_rd_data_m = cat(io.lsu_pic.picm_rd_data, io.lsu_pic.picm_rd_data) @[Cat.scala 29:58] + node dccm_rdata_corr_r = cat(io.sec_data_hi_r, io.sec_data_lo_r) @[Cat.scala 29:58] + node dccm_rdata_corr_m = cat(io.sec_data_hi_m, io.sec_data_lo_m) @[Cat.scala 29:58] + node dccm_rdata_r = cat(io.dccm_rdata_hi_r, io.dccm_rdata_lo_r) @[Cat.scala 29:58] + node dccm_rdata_m = cat(io.dccm_rdata_hi_m, io.dccm_rdata_lo_m) @[Cat.scala 29:58] + wire lsu_rdata_r : UInt<64> + lsu_rdata_r <= UInt<1>("h00") + wire lsu_rdata_m : UInt<64> + lsu_rdata_m <= UInt<1>("h00") + wire lsu_rdata_corr_r : UInt<64> + lsu_rdata_corr_r <= UInt<1>("h00") + wire lsu_rdata_corr_m : UInt<64> + lsu_rdata_corr_m <= UInt<1>("h00") + wire stbuf_fwddata_r : UInt<64> + stbuf_fwddata_r <= UInt<1>("h00") + wire stbuf_fwdbyteen_r : UInt<64> + stbuf_fwdbyteen_r <= UInt<1>("h00") + wire picm_rd_data_r_32 : UInt<32> + picm_rd_data_r_32 <= UInt<1>("h00") + wire picm_rd_data_r : UInt<64> + picm_rd_data_r <= UInt<1>("h00") + wire lsu_ld_data_corr_m : UInt<64> + lsu_ld_data_corr_m <= UInt<1>("h00") + node _T = and(io.lsu_pkt_m.valid, io.lsu_pkt_m.bits.load) @[lsu_dccm_ctl.scala 137:63] + node _T_1 = and(_T, io.lsu_pkt_m.bits.dma) @[lsu_dccm_ctl.scala 137:88] + io.dma_dccm_ctl.dccm_dma_rvalid <= _T_1 @[lsu_dccm_ctl.scala 137:41] + io.dma_dccm_ctl.dccm_dma_ecc_error <= io.lsu_double_ecc_error_m @[lsu_dccm_ctl.scala 138:41] + io.dma_dccm_ctl.dccm_dma_rdata <= lsu_rdata_corr_m @[lsu_dccm_ctl.scala 139:41] + io.dma_dccm_ctl.dccm_dma_rtag <= io.dma_mem_tag_m @[lsu_dccm_ctl.scala 140:41] + io.dccm_rdata_lo_r <= UInt<1>("h00") @[lsu_dccm_ctl.scala 141:28] + io.dccm_rdata_hi_r <= UInt<1>("h00") @[lsu_dccm_ctl.scala 142:28] + io.dccm_data_ecc_hi_r <= UInt<1>("h00") @[lsu_dccm_ctl.scala 143:28] + io.dccm_data_ecc_lo_r <= UInt<1>("h00") @[lsu_dccm_ctl.scala 144:28] + io.lsu_ld_data_r <= UInt<1>("h00") @[lsu_dccm_ctl.scala 145:28] + reg _T_2 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_dccm_ctl.scala 147:65] + _T_2 <= lsu_ld_data_corr_m @[lsu_dccm_ctl.scala 147:65] + io.lsu_ld_data_corr_r <= _T_2 @[lsu_dccm_ctl.scala 147:28] + node _T_3 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_4 = bits(_T_3, 0, 0) @[lsu_dccm_ctl.scala 148:134] + node _T_5 = bits(_T_4, 0, 0) @[lsu_dccm_ctl.scala 148:139] + node _T_6 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_7 = bits(_T_6, 7, 0) @[lsu_dccm_ctl.scala 148:196] + node _T_8 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 148:231] + node _T_9 = bits(picm_rd_data_m, 7, 0) @[lsu_dccm_ctl.scala 148:252] + node _T_10 = bits(dccm_rdata_corr_m, 7, 0) @[lsu_dccm_ctl.scala 148:283] + node _T_11 = mux(_T_8, _T_9, _T_10) @[lsu_dccm_ctl.scala 148:213] + node _T_12 = mux(_T_5, _T_7, _T_11) @[lsu_dccm_ctl.scala 148:78] + node _T_13 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_14 = xor(UInt<8>("h0ff"), _T_13) @[Bitwise.scala 102:21] + node _T_15 = shr(_T_12, 4) @[Bitwise.scala 103:21] + node _T_16 = and(_T_15, _T_14) @[Bitwise.scala 103:31] + node _T_17 = bits(_T_12, 3, 0) @[Bitwise.scala 103:46] + node _T_18 = shl(_T_17, 4) @[Bitwise.scala 103:65] + node _T_19 = not(_T_14) @[Bitwise.scala 103:77] + node _T_20 = and(_T_18, _T_19) @[Bitwise.scala 103:75] + node _T_21 = or(_T_16, _T_20) @[Bitwise.scala 103:39] + node _T_22 = bits(_T_14, 5, 0) @[Bitwise.scala 102:28] + node _T_23 = shl(_T_22, 2) @[Bitwise.scala 102:47] + node _T_24 = xor(_T_14, _T_23) @[Bitwise.scala 102:21] + node _T_25 = shr(_T_21, 2) @[Bitwise.scala 103:21] + node _T_26 = and(_T_25, _T_24) @[Bitwise.scala 103:31] + node _T_27 = bits(_T_21, 5, 0) @[Bitwise.scala 103:46] + node _T_28 = shl(_T_27, 2) @[Bitwise.scala 103:65] + node _T_29 = not(_T_24) @[Bitwise.scala 103:77] + node _T_30 = and(_T_28, _T_29) @[Bitwise.scala 103:75] + node _T_31 = or(_T_26, _T_30) @[Bitwise.scala 103:39] + node _T_32 = bits(_T_24, 6, 0) @[Bitwise.scala 102:28] + node _T_33 = shl(_T_32, 1) @[Bitwise.scala 102:47] + node _T_34 = xor(_T_24, _T_33) @[Bitwise.scala 102:21] + node _T_35 = shr(_T_31, 1) @[Bitwise.scala 103:21] + node _T_36 = and(_T_35, _T_34) @[Bitwise.scala 103:31] + node _T_37 = bits(_T_31, 6, 0) @[Bitwise.scala 103:46] + node _T_38 = shl(_T_37, 1) @[Bitwise.scala 103:65] + node _T_39 = not(_T_34) @[Bitwise.scala 103:77] + node _T_40 = and(_T_38, _T_39) @[Bitwise.scala 103:75] + node _T_41 = or(_T_36, _T_40) @[Bitwise.scala 103:39] + node _T_42 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_43 = bits(_T_42, 1, 1) @[lsu_dccm_ctl.scala 148:134] + node _T_44 = bits(_T_43, 0, 0) @[lsu_dccm_ctl.scala 148:139] + node _T_45 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_46 = bits(_T_45, 15, 8) @[lsu_dccm_ctl.scala 148:196] + node _T_47 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 148:231] + node _T_48 = bits(picm_rd_data_m, 15, 8) @[lsu_dccm_ctl.scala 148:252] + node _T_49 = bits(dccm_rdata_corr_m, 15, 8) @[lsu_dccm_ctl.scala 148:283] + node _T_50 = mux(_T_47, _T_48, _T_49) @[lsu_dccm_ctl.scala 148:213] + node _T_51 = mux(_T_44, _T_46, _T_50) @[lsu_dccm_ctl.scala 148:78] + node _T_52 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_53 = xor(UInt<8>("h0ff"), _T_52) @[Bitwise.scala 102:21] + node _T_54 = shr(_T_51, 4) @[Bitwise.scala 103:21] + node _T_55 = and(_T_54, _T_53) @[Bitwise.scala 103:31] + node _T_56 = bits(_T_51, 3, 0) @[Bitwise.scala 103:46] + node _T_57 = shl(_T_56, 4) @[Bitwise.scala 103:65] + node _T_58 = not(_T_53) @[Bitwise.scala 103:77] + node _T_59 = and(_T_57, _T_58) @[Bitwise.scala 103:75] + node _T_60 = or(_T_55, _T_59) @[Bitwise.scala 103:39] + node _T_61 = bits(_T_53, 5, 0) @[Bitwise.scala 102:28] + node _T_62 = shl(_T_61, 2) @[Bitwise.scala 102:47] + node _T_63 = xor(_T_53, _T_62) @[Bitwise.scala 102:21] + node _T_64 = shr(_T_60, 2) @[Bitwise.scala 103:21] + node _T_65 = and(_T_64, _T_63) @[Bitwise.scala 103:31] + node _T_66 = bits(_T_60, 5, 0) @[Bitwise.scala 103:46] + node _T_67 = shl(_T_66, 2) @[Bitwise.scala 103:65] + node _T_68 = not(_T_63) @[Bitwise.scala 103:77] + node _T_69 = and(_T_67, _T_68) @[Bitwise.scala 103:75] + node _T_70 = or(_T_65, _T_69) @[Bitwise.scala 103:39] + node _T_71 = bits(_T_63, 6, 0) @[Bitwise.scala 102:28] + node _T_72 = shl(_T_71, 1) @[Bitwise.scala 102:47] + node _T_73 = xor(_T_63, _T_72) @[Bitwise.scala 102:21] + node _T_74 = shr(_T_70, 1) @[Bitwise.scala 103:21] + node _T_75 = and(_T_74, _T_73) @[Bitwise.scala 103:31] + node _T_76 = bits(_T_70, 6, 0) @[Bitwise.scala 103:46] + node _T_77 = shl(_T_76, 1) @[Bitwise.scala 103:65] + node _T_78 = not(_T_73) @[Bitwise.scala 103:77] + node _T_79 = and(_T_77, _T_78) @[Bitwise.scala 103:75] + node _T_80 = or(_T_75, _T_79) @[Bitwise.scala 103:39] + node _T_81 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_82 = bits(_T_81, 2, 2) @[lsu_dccm_ctl.scala 148:134] + node _T_83 = bits(_T_82, 0, 0) @[lsu_dccm_ctl.scala 148:139] + node _T_84 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_85 = bits(_T_84, 23, 16) @[lsu_dccm_ctl.scala 148:196] + node _T_86 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 148:231] + node _T_87 = bits(picm_rd_data_m, 23, 16) @[lsu_dccm_ctl.scala 148:252] + node _T_88 = bits(dccm_rdata_corr_m, 23, 16) @[lsu_dccm_ctl.scala 148:283] + node _T_89 = mux(_T_86, _T_87, _T_88) @[lsu_dccm_ctl.scala 148:213] + node _T_90 = mux(_T_83, _T_85, _T_89) @[lsu_dccm_ctl.scala 148:78] + node _T_91 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_92 = xor(UInt<8>("h0ff"), _T_91) @[Bitwise.scala 102:21] + node _T_93 = shr(_T_90, 4) @[Bitwise.scala 103:21] + node _T_94 = and(_T_93, _T_92) @[Bitwise.scala 103:31] + node _T_95 = bits(_T_90, 3, 0) @[Bitwise.scala 103:46] + node _T_96 = shl(_T_95, 4) @[Bitwise.scala 103:65] + node _T_97 = not(_T_92) @[Bitwise.scala 103:77] + node _T_98 = and(_T_96, _T_97) @[Bitwise.scala 103:75] + node _T_99 = or(_T_94, _T_98) @[Bitwise.scala 103:39] + node _T_100 = bits(_T_92, 5, 0) @[Bitwise.scala 102:28] + node _T_101 = shl(_T_100, 2) @[Bitwise.scala 102:47] + node _T_102 = xor(_T_92, _T_101) @[Bitwise.scala 102:21] + node _T_103 = shr(_T_99, 2) @[Bitwise.scala 103:21] + node _T_104 = and(_T_103, _T_102) @[Bitwise.scala 103:31] + node _T_105 = bits(_T_99, 5, 0) @[Bitwise.scala 103:46] + node _T_106 = shl(_T_105, 2) @[Bitwise.scala 103:65] + node _T_107 = not(_T_102) @[Bitwise.scala 103:77] + node _T_108 = and(_T_106, _T_107) @[Bitwise.scala 103:75] + node _T_109 = or(_T_104, _T_108) @[Bitwise.scala 103:39] + node _T_110 = bits(_T_102, 6, 0) @[Bitwise.scala 102:28] + node _T_111 = shl(_T_110, 1) @[Bitwise.scala 102:47] + node _T_112 = xor(_T_102, _T_111) @[Bitwise.scala 102:21] + node _T_113 = shr(_T_109, 1) @[Bitwise.scala 103:21] + node _T_114 = and(_T_113, _T_112) @[Bitwise.scala 103:31] + node _T_115 = bits(_T_109, 6, 0) @[Bitwise.scala 103:46] + node _T_116 = shl(_T_115, 1) @[Bitwise.scala 103:65] + node _T_117 = not(_T_112) @[Bitwise.scala 103:77] + node _T_118 = and(_T_116, _T_117) @[Bitwise.scala 103:75] + node _T_119 = or(_T_114, _T_118) @[Bitwise.scala 103:39] + node _T_120 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_121 = bits(_T_120, 3, 3) @[lsu_dccm_ctl.scala 148:134] + node _T_122 = bits(_T_121, 0, 0) @[lsu_dccm_ctl.scala 148:139] + node _T_123 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_124 = bits(_T_123, 31, 24) @[lsu_dccm_ctl.scala 148:196] + node _T_125 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 148:231] + node _T_126 = bits(picm_rd_data_m, 31, 24) @[lsu_dccm_ctl.scala 148:252] + node _T_127 = bits(dccm_rdata_corr_m, 31, 24) @[lsu_dccm_ctl.scala 148:283] + node _T_128 = mux(_T_125, _T_126, _T_127) @[lsu_dccm_ctl.scala 148:213] + node _T_129 = mux(_T_122, _T_124, _T_128) @[lsu_dccm_ctl.scala 148:78] + node _T_130 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_131 = xor(UInt<8>("h0ff"), _T_130) @[Bitwise.scala 102:21] + node _T_132 = shr(_T_129, 4) @[Bitwise.scala 103:21] + node _T_133 = and(_T_132, _T_131) @[Bitwise.scala 103:31] + node _T_134 = bits(_T_129, 3, 0) @[Bitwise.scala 103:46] + node _T_135 = shl(_T_134, 4) @[Bitwise.scala 103:65] + node _T_136 = not(_T_131) @[Bitwise.scala 103:77] + node _T_137 = and(_T_135, _T_136) @[Bitwise.scala 103:75] + node _T_138 = or(_T_133, _T_137) @[Bitwise.scala 103:39] + node _T_139 = bits(_T_131, 5, 0) @[Bitwise.scala 102:28] + node _T_140 = shl(_T_139, 2) @[Bitwise.scala 102:47] + node _T_141 = xor(_T_131, _T_140) @[Bitwise.scala 102:21] + node _T_142 = shr(_T_138, 2) @[Bitwise.scala 103:21] + node _T_143 = and(_T_142, _T_141) @[Bitwise.scala 103:31] + node _T_144 = bits(_T_138, 5, 0) @[Bitwise.scala 103:46] + node _T_145 = shl(_T_144, 2) @[Bitwise.scala 103:65] + node _T_146 = not(_T_141) @[Bitwise.scala 103:77] + node _T_147 = and(_T_145, _T_146) @[Bitwise.scala 103:75] + node _T_148 = or(_T_143, _T_147) @[Bitwise.scala 103:39] + node _T_149 = bits(_T_141, 6, 0) @[Bitwise.scala 102:28] + node _T_150 = shl(_T_149, 1) @[Bitwise.scala 102:47] + node _T_151 = xor(_T_141, _T_150) @[Bitwise.scala 102:21] + node _T_152 = shr(_T_148, 1) @[Bitwise.scala 103:21] + node _T_153 = and(_T_152, _T_151) @[Bitwise.scala 103:31] + node _T_154 = bits(_T_148, 6, 0) @[Bitwise.scala 103:46] + node _T_155 = shl(_T_154, 1) @[Bitwise.scala 103:65] + node _T_156 = not(_T_151) @[Bitwise.scala 103:77] + node _T_157 = and(_T_155, _T_156) @[Bitwise.scala 103:75] + node _T_158 = or(_T_153, _T_157) @[Bitwise.scala 103:39] + node _T_159 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_160 = bits(_T_159, 4, 4) @[lsu_dccm_ctl.scala 148:134] + node _T_161 = bits(_T_160, 0, 0) @[lsu_dccm_ctl.scala 148:139] + node _T_162 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_163 = bits(_T_162, 39, 32) @[lsu_dccm_ctl.scala 148:196] + node _T_164 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 148:231] + node _T_165 = bits(picm_rd_data_m, 39, 32) @[lsu_dccm_ctl.scala 148:252] + node _T_166 = bits(dccm_rdata_corr_m, 39, 32) @[lsu_dccm_ctl.scala 148:283] + node _T_167 = mux(_T_164, _T_165, _T_166) @[lsu_dccm_ctl.scala 148:213] + node _T_168 = mux(_T_161, _T_163, _T_167) @[lsu_dccm_ctl.scala 148:78] + node _T_169 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_170 = xor(UInt<8>("h0ff"), _T_169) @[Bitwise.scala 102:21] + node _T_171 = shr(_T_168, 4) @[Bitwise.scala 103:21] + node _T_172 = and(_T_171, _T_170) @[Bitwise.scala 103:31] + node _T_173 = bits(_T_168, 3, 0) @[Bitwise.scala 103:46] + node _T_174 = shl(_T_173, 4) @[Bitwise.scala 103:65] + node _T_175 = not(_T_170) @[Bitwise.scala 103:77] + node _T_176 = and(_T_174, _T_175) @[Bitwise.scala 103:75] + node _T_177 = or(_T_172, _T_176) @[Bitwise.scala 103:39] + node _T_178 = bits(_T_170, 5, 0) @[Bitwise.scala 102:28] + node _T_179 = shl(_T_178, 2) @[Bitwise.scala 102:47] + node _T_180 = xor(_T_170, _T_179) @[Bitwise.scala 102:21] + node _T_181 = shr(_T_177, 2) @[Bitwise.scala 103:21] + node _T_182 = and(_T_181, _T_180) @[Bitwise.scala 103:31] + node _T_183 = bits(_T_177, 5, 0) @[Bitwise.scala 103:46] + node _T_184 = shl(_T_183, 2) @[Bitwise.scala 103:65] + node _T_185 = not(_T_180) @[Bitwise.scala 103:77] + node _T_186 = and(_T_184, _T_185) @[Bitwise.scala 103:75] + node _T_187 = or(_T_182, _T_186) @[Bitwise.scala 103:39] + node _T_188 = bits(_T_180, 6, 0) @[Bitwise.scala 102:28] + node _T_189 = shl(_T_188, 1) @[Bitwise.scala 102:47] + node _T_190 = xor(_T_180, _T_189) @[Bitwise.scala 102:21] + node _T_191 = shr(_T_187, 1) @[Bitwise.scala 103:21] + node _T_192 = and(_T_191, _T_190) @[Bitwise.scala 103:31] + node _T_193 = bits(_T_187, 6, 0) @[Bitwise.scala 103:46] + node _T_194 = shl(_T_193, 1) @[Bitwise.scala 103:65] + node _T_195 = not(_T_190) @[Bitwise.scala 103:77] + node _T_196 = and(_T_194, _T_195) @[Bitwise.scala 103:75] + node _T_197 = or(_T_192, _T_196) @[Bitwise.scala 103:39] + node _T_198 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_199 = bits(_T_198, 5, 5) @[lsu_dccm_ctl.scala 148:134] + node _T_200 = bits(_T_199, 0, 0) @[lsu_dccm_ctl.scala 148:139] + node _T_201 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_202 = bits(_T_201, 47, 40) @[lsu_dccm_ctl.scala 148:196] + node _T_203 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 148:231] + node _T_204 = bits(picm_rd_data_m, 47, 40) @[lsu_dccm_ctl.scala 148:252] + node _T_205 = bits(dccm_rdata_corr_m, 47, 40) @[lsu_dccm_ctl.scala 148:283] + node _T_206 = mux(_T_203, _T_204, _T_205) @[lsu_dccm_ctl.scala 148:213] + node _T_207 = mux(_T_200, _T_202, _T_206) @[lsu_dccm_ctl.scala 148:78] + node _T_208 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_209 = xor(UInt<8>("h0ff"), _T_208) @[Bitwise.scala 102:21] + node _T_210 = shr(_T_207, 4) @[Bitwise.scala 103:21] + node _T_211 = and(_T_210, _T_209) @[Bitwise.scala 103:31] + node _T_212 = bits(_T_207, 3, 0) @[Bitwise.scala 103:46] + node _T_213 = shl(_T_212, 4) @[Bitwise.scala 103:65] + node _T_214 = not(_T_209) @[Bitwise.scala 103:77] + node _T_215 = and(_T_213, _T_214) @[Bitwise.scala 103:75] + node _T_216 = or(_T_211, _T_215) @[Bitwise.scala 103:39] + node _T_217 = bits(_T_209, 5, 0) @[Bitwise.scala 102:28] + node _T_218 = shl(_T_217, 2) @[Bitwise.scala 102:47] + node _T_219 = xor(_T_209, _T_218) @[Bitwise.scala 102:21] + node _T_220 = shr(_T_216, 2) @[Bitwise.scala 103:21] + node _T_221 = and(_T_220, _T_219) @[Bitwise.scala 103:31] + node _T_222 = bits(_T_216, 5, 0) @[Bitwise.scala 103:46] + node _T_223 = shl(_T_222, 2) @[Bitwise.scala 103:65] + node _T_224 = not(_T_219) @[Bitwise.scala 103:77] + node _T_225 = and(_T_223, _T_224) @[Bitwise.scala 103:75] + node _T_226 = or(_T_221, _T_225) @[Bitwise.scala 103:39] + node _T_227 = bits(_T_219, 6, 0) @[Bitwise.scala 102:28] + node _T_228 = shl(_T_227, 1) @[Bitwise.scala 102:47] + node _T_229 = xor(_T_219, _T_228) @[Bitwise.scala 102:21] + node _T_230 = shr(_T_226, 1) @[Bitwise.scala 103:21] + node _T_231 = and(_T_230, _T_229) @[Bitwise.scala 103:31] + node _T_232 = bits(_T_226, 6, 0) @[Bitwise.scala 103:46] + node _T_233 = shl(_T_232, 1) @[Bitwise.scala 103:65] + node _T_234 = not(_T_229) @[Bitwise.scala 103:77] + node _T_235 = and(_T_233, _T_234) @[Bitwise.scala 103:75] + node _T_236 = or(_T_231, _T_235) @[Bitwise.scala 103:39] + node _T_237 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_238 = bits(_T_237, 6, 6) @[lsu_dccm_ctl.scala 148:134] + node _T_239 = bits(_T_238, 0, 0) @[lsu_dccm_ctl.scala 148:139] + node _T_240 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_241 = bits(_T_240, 55, 48) @[lsu_dccm_ctl.scala 148:196] + node _T_242 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 148:231] + node _T_243 = bits(picm_rd_data_m, 55, 48) @[lsu_dccm_ctl.scala 148:252] + node _T_244 = bits(dccm_rdata_corr_m, 55, 48) @[lsu_dccm_ctl.scala 148:283] + node _T_245 = mux(_T_242, _T_243, _T_244) @[lsu_dccm_ctl.scala 148:213] + node _T_246 = mux(_T_239, _T_241, _T_245) @[lsu_dccm_ctl.scala 148:78] + node _T_247 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_248 = xor(UInt<8>("h0ff"), _T_247) @[Bitwise.scala 102:21] + node _T_249 = shr(_T_246, 4) @[Bitwise.scala 103:21] + node _T_250 = and(_T_249, _T_248) @[Bitwise.scala 103:31] + node _T_251 = bits(_T_246, 3, 0) @[Bitwise.scala 103:46] + node _T_252 = shl(_T_251, 4) @[Bitwise.scala 103:65] + node _T_253 = not(_T_248) @[Bitwise.scala 103:77] + node _T_254 = and(_T_252, _T_253) @[Bitwise.scala 103:75] + node _T_255 = or(_T_250, _T_254) @[Bitwise.scala 103:39] + node _T_256 = bits(_T_248, 5, 0) @[Bitwise.scala 102:28] + node _T_257 = shl(_T_256, 2) @[Bitwise.scala 102:47] + node _T_258 = xor(_T_248, _T_257) @[Bitwise.scala 102:21] + node _T_259 = shr(_T_255, 2) @[Bitwise.scala 103:21] + node _T_260 = and(_T_259, _T_258) @[Bitwise.scala 103:31] + node _T_261 = bits(_T_255, 5, 0) @[Bitwise.scala 103:46] + node _T_262 = shl(_T_261, 2) @[Bitwise.scala 103:65] + node _T_263 = not(_T_258) @[Bitwise.scala 103:77] + node _T_264 = and(_T_262, _T_263) @[Bitwise.scala 103:75] + node _T_265 = or(_T_260, _T_264) @[Bitwise.scala 103:39] + node _T_266 = bits(_T_258, 6, 0) @[Bitwise.scala 102:28] + node _T_267 = shl(_T_266, 1) @[Bitwise.scala 102:47] + node _T_268 = xor(_T_258, _T_267) @[Bitwise.scala 102:21] + node _T_269 = shr(_T_265, 1) @[Bitwise.scala 103:21] + node _T_270 = and(_T_269, _T_268) @[Bitwise.scala 103:31] + node _T_271 = bits(_T_265, 6, 0) @[Bitwise.scala 103:46] + node _T_272 = shl(_T_271, 1) @[Bitwise.scala 103:65] + node _T_273 = not(_T_268) @[Bitwise.scala 103:77] + node _T_274 = and(_T_272, _T_273) @[Bitwise.scala 103:75] + node _T_275 = or(_T_270, _T_274) @[Bitwise.scala 103:39] + node _T_276 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_277 = bits(_T_276, 7, 7) @[lsu_dccm_ctl.scala 148:134] + node _T_278 = bits(_T_277, 0, 0) @[lsu_dccm_ctl.scala 148:139] + node _T_279 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_280 = bits(_T_279, 63, 56) @[lsu_dccm_ctl.scala 148:196] + node _T_281 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 148:231] + node _T_282 = bits(picm_rd_data_m, 63, 56) @[lsu_dccm_ctl.scala 148:252] + node _T_283 = bits(dccm_rdata_corr_m, 63, 56) @[lsu_dccm_ctl.scala 148:283] + node _T_284 = mux(_T_281, _T_282, _T_283) @[lsu_dccm_ctl.scala 148:213] + node _T_285 = mux(_T_278, _T_280, _T_284) @[lsu_dccm_ctl.scala 148:78] + node _T_286 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_287 = xor(UInt<8>("h0ff"), _T_286) @[Bitwise.scala 102:21] + node _T_288 = shr(_T_285, 4) @[Bitwise.scala 103:21] + node _T_289 = and(_T_288, _T_287) @[Bitwise.scala 103:31] + node _T_290 = bits(_T_285, 3, 0) @[Bitwise.scala 103:46] + node _T_291 = shl(_T_290, 4) @[Bitwise.scala 103:65] + node _T_292 = not(_T_287) @[Bitwise.scala 103:77] + node _T_293 = and(_T_291, _T_292) @[Bitwise.scala 103:75] + node _T_294 = or(_T_289, _T_293) @[Bitwise.scala 103:39] + node _T_295 = bits(_T_287, 5, 0) @[Bitwise.scala 102:28] + node _T_296 = shl(_T_295, 2) @[Bitwise.scala 102:47] + node _T_297 = xor(_T_287, _T_296) @[Bitwise.scala 102:21] + node _T_298 = shr(_T_294, 2) @[Bitwise.scala 103:21] + node _T_299 = and(_T_298, _T_297) @[Bitwise.scala 103:31] + node _T_300 = bits(_T_294, 5, 0) @[Bitwise.scala 103:46] + node _T_301 = shl(_T_300, 2) @[Bitwise.scala 103:65] + node _T_302 = not(_T_297) @[Bitwise.scala 103:77] + node _T_303 = and(_T_301, _T_302) @[Bitwise.scala 103:75] + node _T_304 = or(_T_299, _T_303) @[Bitwise.scala 103:39] + node _T_305 = bits(_T_297, 6, 0) @[Bitwise.scala 102:28] + node _T_306 = shl(_T_305, 1) @[Bitwise.scala 102:47] + node _T_307 = xor(_T_297, _T_306) @[Bitwise.scala 102:21] + node _T_308 = shr(_T_304, 1) @[Bitwise.scala 103:21] + node _T_309 = and(_T_308, _T_307) @[Bitwise.scala 103:31] + node _T_310 = bits(_T_304, 6, 0) @[Bitwise.scala 103:46] + node _T_311 = shl(_T_310, 1) @[Bitwise.scala 103:65] + node _T_312 = not(_T_307) @[Bitwise.scala 103:77] + node _T_313 = and(_T_311, _T_312) @[Bitwise.scala 103:75] + node _T_314 = or(_T_309, _T_313) @[Bitwise.scala 103:39] + wire _T_315 : UInt<8>[8] @[lsu_dccm_ctl.scala 148:62] + _T_315[0] <= _T_41 @[lsu_dccm_ctl.scala 148:62] + _T_315[1] <= _T_80 @[lsu_dccm_ctl.scala 148:62] + _T_315[2] <= _T_119 @[lsu_dccm_ctl.scala 148:62] + _T_315[3] <= _T_158 @[lsu_dccm_ctl.scala 148:62] + _T_315[4] <= _T_197 @[lsu_dccm_ctl.scala 148:62] + _T_315[5] <= _T_236 @[lsu_dccm_ctl.scala 148:62] + _T_315[6] <= _T_275 @[lsu_dccm_ctl.scala 148:62] + _T_315[7] <= _T_314 @[lsu_dccm_ctl.scala 148:62] + node _T_316 = cat(_T_315[6], _T_315[7]) @[Cat.scala 29:58] + node _T_317 = cat(_T_315[4], _T_315[5]) @[Cat.scala 29:58] + node _T_318 = cat(_T_317, _T_316) @[Cat.scala 29:58] + node _T_319 = cat(_T_315[2], _T_315[3]) @[Cat.scala 29:58] + node _T_320 = cat(_T_315[0], _T_315[1]) @[Cat.scala 29:58] + node _T_321 = cat(_T_320, _T_319) @[Cat.scala 29:58] + node _T_322 = cat(_T_321, _T_318) @[Cat.scala 29:58] + node _T_323 = shl(UInt<32>("h0ffffffff"), 32) @[Bitwise.scala 102:47] + node _T_324 = xor(UInt<64>("h0ffffffffffffffff"), _T_323) @[Bitwise.scala 102:21] + node _T_325 = shr(_T_322, 32) @[Bitwise.scala 103:21] + node _T_326 = and(_T_325, _T_324) @[Bitwise.scala 103:31] + node _T_327 = bits(_T_322, 31, 0) @[Bitwise.scala 103:46] + node _T_328 = shl(_T_327, 32) @[Bitwise.scala 103:65] + node _T_329 = not(_T_324) @[Bitwise.scala 103:77] + node _T_330 = and(_T_328, _T_329) @[Bitwise.scala 103:75] + node _T_331 = or(_T_326, _T_330) @[Bitwise.scala 103:39] + node _T_332 = bits(_T_324, 47, 0) @[Bitwise.scala 102:28] + node _T_333 = shl(_T_332, 16) @[Bitwise.scala 102:47] + node _T_334 = xor(_T_324, _T_333) @[Bitwise.scala 102:21] + node _T_335 = shr(_T_331, 16) @[Bitwise.scala 103:21] + node _T_336 = and(_T_335, _T_334) @[Bitwise.scala 103:31] + node _T_337 = bits(_T_331, 47, 0) @[Bitwise.scala 103:46] + node _T_338 = shl(_T_337, 16) @[Bitwise.scala 103:65] + node _T_339 = not(_T_334) @[Bitwise.scala 103:77] + node _T_340 = and(_T_338, _T_339) @[Bitwise.scala 103:75] + node _T_341 = or(_T_336, _T_340) @[Bitwise.scala 103:39] + node _T_342 = bits(_T_334, 55, 0) @[Bitwise.scala 102:28] + node _T_343 = shl(_T_342, 8) @[Bitwise.scala 102:47] + node _T_344 = xor(_T_334, _T_343) @[Bitwise.scala 102:21] + node _T_345 = shr(_T_341, 8) @[Bitwise.scala 103:21] + node _T_346 = and(_T_345, _T_344) @[Bitwise.scala 103:31] + node _T_347 = bits(_T_341, 55, 0) @[Bitwise.scala 103:46] + node _T_348 = shl(_T_347, 8) @[Bitwise.scala 103:65] + node _T_349 = not(_T_344) @[Bitwise.scala 103:77] + node _T_350 = and(_T_348, _T_349) @[Bitwise.scala 103:75] + node _T_351 = or(_T_346, _T_350) @[Bitwise.scala 103:39] + node _T_352 = bits(_T_344, 59, 0) @[Bitwise.scala 102:28] + node _T_353 = shl(_T_352, 4) @[Bitwise.scala 102:47] + node _T_354 = xor(_T_344, _T_353) @[Bitwise.scala 102:21] + node _T_355 = shr(_T_351, 4) @[Bitwise.scala 103:21] + node _T_356 = and(_T_355, _T_354) @[Bitwise.scala 103:31] + node _T_357 = bits(_T_351, 59, 0) @[Bitwise.scala 103:46] + node _T_358 = shl(_T_357, 4) @[Bitwise.scala 103:65] + node _T_359 = not(_T_354) @[Bitwise.scala 103:77] + node _T_360 = and(_T_358, _T_359) @[Bitwise.scala 103:75] + node _T_361 = or(_T_356, _T_360) @[Bitwise.scala 103:39] + node _T_362 = bits(_T_354, 61, 0) @[Bitwise.scala 102:28] + node _T_363 = shl(_T_362, 2) @[Bitwise.scala 102:47] + node _T_364 = xor(_T_354, _T_363) @[Bitwise.scala 102:21] + node _T_365 = shr(_T_361, 2) @[Bitwise.scala 103:21] + node _T_366 = and(_T_365, _T_364) @[Bitwise.scala 103:31] + node _T_367 = bits(_T_361, 61, 0) @[Bitwise.scala 103:46] + node _T_368 = shl(_T_367, 2) @[Bitwise.scala 103:65] + node _T_369 = not(_T_364) @[Bitwise.scala 103:77] + node _T_370 = and(_T_368, _T_369) @[Bitwise.scala 103:75] + node _T_371 = or(_T_366, _T_370) @[Bitwise.scala 103:39] + node _T_372 = bits(_T_364, 62, 0) @[Bitwise.scala 102:28] + node _T_373 = shl(_T_372, 1) @[Bitwise.scala 102:47] + node _T_374 = xor(_T_364, _T_373) @[Bitwise.scala 102:21] + node _T_375 = shr(_T_371, 1) @[Bitwise.scala 103:21] + node _T_376 = and(_T_375, _T_374) @[Bitwise.scala 103:31] + node _T_377 = bits(_T_371, 62, 0) @[Bitwise.scala 103:46] + node _T_378 = shl(_T_377, 1) @[Bitwise.scala 103:65] + node _T_379 = not(_T_374) @[Bitwise.scala 103:77] + node _T_380 = and(_T_378, _T_379) @[Bitwise.scala 103:75] + node _T_381 = or(_T_376, _T_380) @[Bitwise.scala 103:39] + lsu_rdata_corr_m <= _T_381 @[lsu_dccm_ctl.scala 148:28] + node _T_382 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_383 = bits(_T_382, 0, 0) @[lsu_dccm_ctl.scala 149:134] + node _T_384 = bits(_T_383, 0, 0) @[lsu_dccm_ctl.scala 149:139] + node _T_385 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_386 = bits(_T_385, 7, 0) @[lsu_dccm_ctl.scala 149:196] + node _T_387 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 149:231] + node _T_388 = bits(picm_rd_data_m, 7, 0) @[lsu_dccm_ctl.scala 149:252] + node _T_389 = bits(dccm_rdata_m, 7, 0) @[lsu_dccm_ctl.scala 149:278] + node _T_390 = mux(_T_387, _T_388, _T_389) @[lsu_dccm_ctl.scala 149:213] + node _T_391 = mux(_T_384, _T_386, _T_390) @[lsu_dccm_ctl.scala 149:78] + node _T_392 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_393 = xor(UInt<8>("h0ff"), _T_392) @[Bitwise.scala 102:21] + node _T_394 = shr(_T_391, 4) @[Bitwise.scala 103:21] + node _T_395 = and(_T_394, _T_393) @[Bitwise.scala 103:31] + node _T_396 = bits(_T_391, 3, 0) @[Bitwise.scala 103:46] + node _T_397 = shl(_T_396, 4) @[Bitwise.scala 103:65] + node _T_398 = not(_T_393) @[Bitwise.scala 103:77] + node _T_399 = and(_T_397, _T_398) @[Bitwise.scala 103:75] + node _T_400 = or(_T_395, _T_399) @[Bitwise.scala 103:39] + node _T_401 = bits(_T_393, 5, 0) @[Bitwise.scala 102:28] + node _T_402 = shl(_T_401, 2) @[Bitwise.scala 102:47] + node _T_403 = xor(_T_393, _T_402) @[Bitwise.scala 102:21] + node _T_404 = shr(_T_400, 2) @[Bitwise.scala 103:21] + node _T_405 = and(_T_404, _T_403) @[Bitwise.scala 103:31] + node _T_406 = bits(_T_400, 5, 0) @[Bitwise.scala 103:46] + node _T_407 = shl(_T_406, 2) @[Bitwise.scala 103:65] + node _T_408 = not(_T_403) @[Bitwise.scala 103:77] + node _T_409 = and(_T_407, _T_408) @[Bitwise.scala 103:75] + node _T_410 = or(_T_405, _T_409) @[Bitwise.scala 103:39] + node _T_411 = bits(_T_403, 6, 0) @[Bitwise.scala 102:28] + node _T_412 = shl(_T_411, 1) @[Bitwise.scala 102:47] + node _T_413 = xor(_T_403, _T_412) @[Bitwise.scala 102:21] + node _T_414 = shr(_T_410, 1) @[Bitwise.scala 103:21] + node _T_415 = and(_T_414, _T_413) @[Bitwise.scala 103:31] + node _T_416 = bits(_T_410, 6, 0) @[Bitwise.scala 103:46] + node _T_417 = shl(_T_416, 1) @[Bitwise.scala 103:65] + node _T_418 = not(_T_413) @[Bitwise.scala 103:77] + node _T_419 = and(_T_417, _T_418) @[Bitwise.scala 103:75] + node _T_420 = or(_T_415, _T_419) @[Bitwise.scala 103:39] + node _T_421 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_422 = bits(_T_421, 1, 1) @[lsu_dccm_ctl.scala 149:134] + node _T_423 = bits(_T_422, 0, 0) @[lsu_dccm_ctl.scala 149:139] + node _T_424 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_425 = bits(_T_424, 15, 8) @[lsu_dccm_ctl.scala 149:196] + node _T_426 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 149:231] + node _T_427 = bits(picm_rd_data_m, 15, 8) @[lsu_dccm_ctl.scala 149:252] + node _T_428 = bits(dccm_rdata_m, 15, 8) @[lsu_dccm_ctl.scala 149:278] + node _T_429 = mux(_T_426, _T_427, _T_428) @[lsu_dccm_ctl.scala 149:213] + node _T_430 = mux(_T_423, _T_425, _T_429) @[lsu_dccm_ctl.scala 149:78] + node _T_431 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_432 = xor(UInt<8>("h0ff"), _T_431) @[Bitwise.scala 102:21] + node _T_433 = shr(_T_430, 4) @[Bitwise.scala 103:21] + node _T_434 = and(_T_433, _T_432) @[Bitwise.scala 103:31] + node _T_435 = bits(_T_430, 3, 0) @[Bitwise.scala 103:46] + node _T_436 = shl(_T_435, 4) @[Bitwise.scala 103:65] + node _T_437 = not(_T_432) @[Bitwise.scala 103:77] + node _T_438 = and(_T_436, _T_437) @[Bitwise.scala 103:75] + node _T_439 = or(_T_434, _T_438) @[Bitwise.scala 103:39] + node _T_440 = bits(_T_432, 5, 0) @[Bitwise.scala 102:28] + node _T_441 = shl(_T_440, 2) @[Bitwise.scala 102:47] + node _T_442 = xor(_T_432, _T_441) @[Bitwise.scala 102:21] + node _T_443 = shr(_T_439, 2) @[Bitwise.scala 103:21] + node _T_444 = and(_T_443, _T_442) @[Bitwise.scala 103:31] + node _T_445 = bits(_T_439, 5, 0) @[Bitwise.scala 103:46] + node _T_446 = shl(_T_445, 2) @[Bitwise.scala 103:65] + node _T_447 = not(_T_442) @[Bitwise.scala 103:77] + node _T_448 = and(_T_446, _T_447) @[Bitwise.scala 103:75] + node _T_449 = or(_T_444, _T_448) @[Bitwise.scala 103:39] + node _T_450 = bits(_T_442, 6, 0) @[Bitwise.scala 102:28] + node _T_451 = shl(_T_450, 1) @[Bitwise.scala 102:47] + node _T_452 = xor(_T_442, _T_451) @[Bitwise.scala 102:21] + node _T_453 = shr(_T_449, 1) @[Bitwise.scala 103:21] + node _T_454 = and(_T_453, _T_452) @[Bitwise.scala 103:31] + node _T_455 = bits(_T_449, 6, 0) @[Bitwise.scala 103:46] + node _T_456 = shl(_T_455, 1) @[Bitwise.scala 103:65] + node _T_457 = not(_T_452) @[Bitwise.scala 103:77] + node _T_458 = and(_T_456, _T_457) @[Bitwise.scala 103:75] + node _T_459 = or(_T_454, _T_458) @[Bitwise.scala 103:39] + node _T_460 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_461 = bits(_T_460, 2, 2) @[lsu_dccm_ctl.scala 149:134] + node _T_462 = bits(_T_461, 0, 0) @[lsu_dccm_ctl.scala 149:139] + node _T_463 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_464 = bits(_T_463, 23, 16) @[lsu_dccm_ctl.scala 149:196] + node _T_465 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 149:231] + node _T_466 = bits(picm_rd_data_m, 23, 16) @[lsu_dccm_ctl.scala 149:252] + node _T_467 = bits(dccm_rdata_m, 23, 16) @[lsu_dccm_ctl.scala 149:278] + node _T_468 = mux(_T_465, _T_466, _T_467) @[lsu_dccm_ctl.scala 149:213] + node _T_469 = mux(_T_462, _T_464, _T_468) @[lsu_dccm_ctl.scala 149:78] + node _T_470 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_471 = xor(UInt<8>("h0ff"), _T_470) @[Bitwise.scala 102:21] + node _T_472 = shr(_T_469, 4) @[Bitwise.scala 103:21] + node _T_473 = and(_T_472, _T_471) @[Bitwise.scala 103:31] + node _T_474 = bits(_T_469, 3, 0) @[Bitwise.scala 103:46] + node _T_475 = shl(_T_474, 4) @[Bitwise.scala 103:65] + node _T_476 = not(_T_471) @[Bitwise.scala 103:77] + node _T_477 = and(_T_475, _T_476) @[Bitwise.scala 103:75] + node _T_478 = or(_T_473, _T_477) @[Bitwise.scala 103:39] + node _T_479 = bits(_T_471, 5, 0) @[Bitwise.scala 102:28] + node _T_480 = shl(_T_479, 2) @[Bitwise.scala 102:47] + node _T_481 = xor(_T_471, _T_480) @[Bitwise.scala 102:21] + node _T_482 = shr(_T_478, 2) @[Bitwise.scala 103:21] + node _T_483 = and(_T_482, _T_481) @[Bitwise.scala 103:31] + node _T_484 = bits(_T_478, 5, 0) @[Bitwise.scala 103:46] + node _T_485 = shl(_T_484, 2) @[Bitwise.scala 103:65] + node _T_486 = not(_T_481) @[Bitwise.scala 103:77] + node _T_487 = and(_T_485, _T_486) @[Bitwise.scala 103:75] + node _T_488 = or(_T_483, _T_487) @[Bitwise.scala 103:39] + node _T_489 = bits(_T_481, 6, 0) @[Bitwise.scala 102:28] + node _T_490 = shl(_T_489, 1) @[Bitwise.scala 102:47] + node _T_491 = xor(_T_481, _T_490) @[Bitwise.scala 102:21] + node _T_492 = shr(_T_488, 1) @[Bitwise.scala 103:21] + node _T_493 = and(_T_492, _T_491) @[Bitwise.scala 103:31] + node _T_494 = bits(_T_488, 6, 0) @[Bitwise.scala 103:46] + node _T_495 = shl(_T_494, 1) @[Bitwise.scala 103:65] + node _T_496 = not(_T_491) @[Bitwise.scala 103:77] + node _T_497 = and(_T_495, _T_496) @[Bitwise.scala 103:75] + node _T_498 = or(_T_493, _T_497) @[Bitwise.scala 103:39] + node _T_499 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_500 = bits(_T_499, 3, 3) @[lsu_dccm_ctl.scala 149:134] + node _T_501 = bits(_T_500, 0, 0) @[lsu_dccm_ctl.scala 149:139] + node _T_502 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_503 = bits(_T_502, 31, 24) @[lsu_dccm_ctl.scala 149:196] + node _T_504 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 149:231] + node _T_505 = bits(picm_rd_data_m, 31, 24) @[lsu_dccm_ctl.scala 149:252] + node _T_506 = bits(dccm_rdata_m, 31, 24) @[lsu_dccm_ctl.scala 149:278] + node _T_507 = mux(_T_504, _T_505, _T_506) @[lsu_dccm_ctl.scala 149:213] + node _T_508 = mux(_T_501, _T_503, _T_507) @[lsu_dccm_ctl.scala 149:78] + node _T_509 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_510 = xor(UInt<8>("h0ff"), _T_509) @[Bitwise.scala 102:21] + node _T_511 = shr(_T_508, 4) @[Bitwise.scala 103:21] + node _T_512 = and(_T_511, _T_510) @[Bitwise.scala 103:31] + node _T_513 = bits(_T_508, 3, 0) @[Bitwise.scala 103:46] + node _T_514 = shl(_T_513, 4) @[Bitwise.scala 103:65] + node _T_515 = not(_T_510) @[Bitwise.scala 103:77] + node _T_516 = and(_T_514, _T_515) @[Bitwise.scala 103:75] + node _T_517 = or(_T_512, _T_516) @[Bitwise.scala 103:39] + node _T_518 = bits(_T_510, 5, 0) @[Bitwise.scala 102:28] + node _T_519 = shl(_T_518, 2) @[Bitwise.scala 102:47] + node _T_520 = xor(_T_510, _T_519) @[Bitwise.scala 102:21] + node _T_521 = shr(_T_517, 2) @[Bitwise.scala 103:21] + node _T_522 = and(_T_521, _T_520) @[Bitwise.scala 103:31] + node _T_523 = bits(_T_517, 5, 0) @[Bitwise.scala 103:46] + node _T_524 = shl(_T_523, 2) @[Bitwise.scala 103:65] + node _T_525 = not(_T_520) @[Bitwise.scala 103:77] + node _T_526 = and(_T_524, _T_525) @[Bitwise.scala 103:75] + node _T_527 = or(_T_522, _T_526) @[Bitwise.scala 103:39] + node _T_528 = bits(_T_520, 6, 0) @[Bitwise.scala 102:28] + node _T_529 = shl(_T_528, 1) @[Bitwise.scala 102:47] + node _T_530 = xor(_T_520, _T_529) @[Bitwise.scala 102:21] + node _T_531 = shr(_T_527, 1) @[Bitwise.scala 103:21] + node _T_532 = and(_T_531, _T_530) @[Bitwise.scala 103:31] + node _T_533 = bits(_T_527, 6, 0) @[Bitwise.scala 103:46] + node _T_534 = shl(_T_533, 1) @[Bitwise.scala 103:65] + node _T_535 = not(_T_530) @[Bitwise.scala 103:77] + node _T_536 = and(_T_534, _T_535) @[Bitwise.scala 103:75] + node _T_537 = or(_T_532, _T_536) @[Bitwise.scala 103:39] + node _T_538 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_539 = bits(_T_538, 4, 4) @[lsu_dccm_ctl.scala 149:134] + node _T_540 = bits(_T_539, 0, 0) @[lsu_dccm_ctl.scala 149:139] + node _T_541 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_542 = bits(_T_541, 39, 32) @[lsu_dccm_ctl.scala 149:196] + node _T_543 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 149:231] + node _T_544 = bits(picm_rd_data_m, 39, 32) @[lsu_dccm_ctl.scala 149:252] + node _T_545 = bits(dccm_rdata_m, 39, 32) @[lsu_dccm_ctl.scala 149:278] + node _T_546 = mux(_T_543, _T_544, _T_545) @[lsu_dccm_ctl.scala 149:213] + node _T_547 = mux(_T_540, _T_542, _T_546) @[lsu_dccm_ctl.scala 149:78] + node _T_548 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_549 = xor(UInt<8>("h0ff"), _T_548) @[Bitwise.scala 102:21] + node _T_550 = shr(_T_547, 4) @[Bitwise.scala 103:21] + node _T_551 = and(_T_550, _T_549) @[Bitwise.scala 103:31] + node _T_552 = bits(_T_547, 3, 0) @[Bitwise.scala 103:46] + node _T_553 = shl(_T_552, 4) @[Bitwise.scala 103:65] + node _T_554 = not(_T_549) @[Bitwise.scala 103:77] + node _T_555 = and(_T_553, _T_554) @[Bitwise.scala 103:75] + node _T_556 = or(_T_551, _T_555) @[Bitwise.scala 103:39] + node _T_557 = bits(_T_549, 5, 0) @[Bitwise.scala 102:28] + node _T_558 = shl(_T_557, 2) @[Bitwise.scala 102:47] + node _T_559 = xor(_T_549, _T_558) @[Bitwise.scala 102:21] + node _T_560 = shr(_T_556, 2) @[Bitwise.scala 103:21] + node _T_561 = and(_T_560, _T_559) @[Bitwise.scala 103:31] + node _T_562 = bits(_T_556, 5, 0) @[Bitwise.scala 103:46] + node _T_563 = shl(_T_562, 2) @[Bitwise.scala 103:65] + node _T_564 = not(_T_559) @[Bitwise.scala 103:77] + node _T_565 = and(_T_563, _T_564) @[Bitwise.scala 103:75] + node _T_566 = or(_T_561, _T_565) @[Bitwise.scala 103:39] + node _T_567 = bits(_T_559, 6, 0) @[Bitwise.scala 102:28] + node _T_568 = shl(_T_567, 1) @[Bitwise.scala 102:47] + node _T_569 = xor(_T_559, _T_568) @[Bitwise.scala 102:21] + node _T_570 = shr(_T_566, 1) @[Bitwise.scala 103:21] + node _T_571 = and(_T_570, _T_569) @[Bitwise.scala 103:31] + node _T_572 = bits(_T_566, 6, 0) @[Bitwise.scala 103:46] + node _T_573 = shl(_T_572, 1) @[Bitwise.scala 103:65] + node _T_574 = not(_T_569) @[Bitwise.scala 103:77] + node _T_575 = and(_T_573, _T_574) @[Bitwise.scala 103:75] + node _T_576 = or(_T_571, _T_575) @[Bitwise.scala 103:39] + node _T_577 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_578 = bits(_T_577, 5, 5) @[lsu_dccm_ctl.scala 149:134] + node _T_579 = bits(_T_578, 0, 0) @[lsu_dccm_ctl.scala 149:139] + node _T_580 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_581 = bits(_T_580, 47, 40) @[lsu_dccm_ctl.scala 149:196] + node _T_582 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 149:231] + node _T_583 = bits(picm_rd_data_m, 47, 40) @[lsu_dccm_ctl.scala 149:252] + node _T_584 = bits(dccm_rdata_m, 47, 40) @[lsu_dccm_ctl.scala 149:278] + node _T_585 = mux(_T_582, _T_583, _T_584) @[lsu_dccm_ctl.scala 149:213] + node _T_586 = mux(_T_579, _T_581, _T_585) @[lsu_dccm_ctl.scala 149:78] + node _T_587 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_588 = xor(UInt<8>("h0ff"), _T_587) @[Bitwise.scala 102:21] + node _T_589 = shr(_T_586, 4) @[Bitwise.scala 103:21] + node _T_590 = and(_T_589, _T_588) @[Bitwise.scala 103:31] + node _T_591 = bits(_T_586, 3, 0) @[Bitwise.scala 103:46] + node _T_592 = shl(_T_591, 4) @[Bitwise.scala 103:65] + node _T_593 = not(_T_588) @[Bitwise.scala 103:77] + node _T_594 = and(_T_592, _T_593) @[Bitwise.scala 103:75] + node _T_595 = or(_T_590, _T_594) @[Bitwise.scala 103:39] + node _T_596 = bits(_T_588, 5, 0) @[Bitwise.scala 102:28] + node _T_597 = shl(_T_596, 2) @[Bitwise.scala 102:47] + node _T_598 = xor(_T_588, _T_597) @[Bitwise.scala 102:21] + node _T_599 = shr(_T_595, 2) @[Bitwise.scala 103:21] + node _T_600 = and(_T_599, _T_598) @[Bitwise.scala 103:31] + node _T_601 = bits(_T_595, 5, 0) @[Bitwise.scala 103:46] + node _T_602 = shl(_T_601, 2) @[Bitwise.scala 103:65] + node _T_603 = not(_T_598) @[Bitwise.scala 103:77] + node _T_604 = and(_T_602, _T_603) @[Bitwise.scala 103:75] + node _T_605 = or(_T_600, _T_604) @[Bitwise.scala 103:39] + node _T_606 = bits(_T_598, 6, 0) @[Bitwise.scala 102:28] + node _T_607 = shl(_T_606, 1) @[Bitwise.scala 102:47] + node _T_608 = xor(_T_598, _T_607) @[Bitwise.scala 102:21] + node _T_609 = shr(_T_605, 1) @[Bitwise.scala 103:21] + node _T_610 = and(_T_609, _T_608) @[Bitwise.scala 103:31] + node _T_611 = bits(_T_605, 6, 0) @[Bitwise.scala 103:46] + node _T_612 = shl(_T_611, 1) @[Bitwise.scala 103:65] + node _T_613 = not(_T_608) @[Bitwise.scala 103:77] + node _T_614 = and(_T_612, _T_613) @[Bitwise.scala 103:75] + node _T_615 = or(_T_610, _T_614) @[Bitwise.scala 103:39] + node _T_616 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_617 = bits(_T_616, 6, 6) @[lsu_dccm_ctl.scala 149:134] + node _T_618 = bits(_T_617, 0, 0) @[lsu_dccm_ctl.scala 149:139] + node _T_619 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_620 = bits(_T_619, 55, 48) @[lsu_dccm_ctl.scala 149:196] + node _T_621 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 149:231] + node _T_622 = bits(picm_rd_data_m, 55, 48) @[lsu_dccm_ctl.scala 149:252] + node _T_623 = bits(dccm_rdata_m, 55, 48) @[lsu_dccm_ctl.scala 149:278] + node _T_624 = mux(_T_621, _T_622, _T_623) @[lsu_dccm_ctl.scala 149:213] + node _T_625 = mux(_T_618, _T_620, _T_624) @[lsu_dccm_ctl.scala 149:78] + node _T_626 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_627 = xor(UInt<8>("h0ff"), _T_626) @[Bitwise.scala 102:21] + node _T_628 = shr(_T_625, 4) @[Bitwise.scala 103:21] + node _T_629 = and(_T_628, _T_627) @[Bitwise.scala 103:31] + node _T_630 = bits(_T_625, 3, 0) @[Bitwise.scala 103:46] + node _T_631 = shl(_T_630, 4) @[Bitwise.scala 103:65] + node _T_632 = not(_T_627) @[Bitwise.scala 103:77] + node _T_633 = and(_T_631, _T_632) @[Bitwise.scala 103:75] + node _T_634 = or(_T_629, _T_633) @[Bitwise.scala 103:39] + node _T_635 = bits(_T_627, 5, 0) @[Bitwise.scala 102:28] + node _T_636 = shl(_T_635, 2) @[Bitwise.scala 102:47] + node _T_637 = xor(_T_627, _T_636) @[Bitwise.scala 102:21] + node _T_638 = shr(_T_634, 2) @[Bitwise.scala 103:21] + node _T_639 = and(_T_638, _T_637) @[Bitwise.scala 103:31] + node _T_640 = bits(_T_634, 5, 0) @[Bitwise.scala 103:46] + node _T_641 = shl(_T_640, 2) @[Bitwise.scala 103:65] + node _T_642 = not(_T_637) @[Bitwise.scala 103:77] + node _T_643 = and(_T_641, _T_642) @[Bitwise.scala 103:75] + node _T_644 = or(_T_639, _T_643) @[Bitwise.scala 103:39] + node _T_645 = bits(_T_637, 6, 0) @[Bitwise.scala 102:28] + node _T_646 = shl(_T_645, 1) @[Bitwise.scala 102:47] + node _T_647 = xor(_T_637, _T_646) @[Bitwise.scala 102:21] + node _T_648 = shr(_T_644, 1) @[Bitwise.scala 103:21] + node _T_649 = and(_T_648, _T_647) @[Bitwise.scala 103:31] + node _T_650 = bits(_T_644, 6, 0) @[Bitwise.scala 103:46] + node _T_651 = shl(_T_650, 1) @[Bitwise.scala 103:65] + node _T_652 = not(_T_647) @[Bitwise.scala 103:77] + node _T_653 = and(_T_651, _T_652) @[Bitwise.scala 103:75] + node _T_654 = or(_T_649, _T_653) @[Bitwise.scala 103:39] + node _T_655 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_656 = bits(_T_655, 7, 7) @[lsu_dccm_ctl.scala 149:134] + node _T_657 = bits(_T_656, 0, 0) @[lsu_dccm_ctl.scala 149:139] + node _T_658 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_659 = bits(_T_658, 63, 56) @[lsu_dccm_ctl.scala 149:196] + node _T_660 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 149:231] + node _T_661 = bits(picm_rd_data_m, 63, 56) @[lsu_dccm_ctl.scala 149:252] + node _T_662 = bits(dccm_rdata_m, 63, 56) @[lsu_dccm_ctl.scala 149:278] + node _T_663 = mux(_T_660, _T_661, _T_662) @[lsu_dccm_ctl.scala 149:213] + node _T_664 = mux(_T_657, _T_659, _T_663) @[lsu_dccm_ctl.scala 149:78] + node _T_665 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_666 = xor(UInt<8>("h0ff"), _T_665) @[Bitwise.scala 102:21] + node _T_667 = shr(_T_664, 4) @[Bitwise.scala 103:21] + node _T_668 = and(_T_667, _T_666) @[Bitwise.scala 103:31] + node _T_669 = bits(_T_664, 3, 0) @[Bitwise.scala 103:46] + node _T_670 = shl(_T_669, 4) @[Bitwise.scala 103:65] + node _T_671 = not(_T_666) @[Bitwise.scala 103:77] + node _T_672 = and(_T_670, _T_671) @[Bitwise.scala 103:75] + node _T_673 = or(_T_668, _T_672) @[Bitwise.scala 103:39] + node _T_674 = bits(_T_666, 5, 0) @[Bitwise.scala 102:28] + node _T_675 = shl(_T_674, 2) @[Bitwise.scala 102:47] + node _T_676 = xor(_T_666, _T_675) @[Bitwise.scala 102:21] + node _T_677 = shr(_T_673, 2) @[Bitwise.scala 103:21] + node _T_678 = and(_T_677, _T_676) @[Bitwise.scala 103:31] + node _T_679 = bits(_T_673, 5, 0) @[Bitwise.scala 103:46] + node _T_680 = shl(_T_679, 2) @[Bitwise.scala 103:65] + node _T_681 = not(_T_676) @[Bitwise.scala 103:77] + node _T_682 = and(_T_680, _T_681) @[Bitwise.scala 103:75] + node _T_683 = or(_T_678, _T_682) @[Bitwise.scala 103:39] + node _T_684 = bits(_T_676, 6, 0) @[Bitwise.scala 102:28] + node _T_685 = shl(_T_684, 1) @[Bitwise.scala 102:47] + node _T_686 = xor(_T_676, _T_685) @[Bitwise.scala 102:21] + node _T_687 = shr(_T_683, 1) @[Bitwise.scala 103:21] + node _T_688 = and(_T_687, _T_686) @[Bitwise.scala 103:31] + node _T_689 = bits(_T_683, 6, 0) @[Bitwise.scala 103:46] + node _T_690 = shl(_T_689, 1) @[Bitwise.scala 103:65] + node _T_691 = not(_T_686) @[Bitwise.scala 103:77] + node _T_692 = and(_T_690, _T_691) @[Bitwise.scala 103:75] + node _T_693 = or(_T_688, _T_692) @[Bitwise.scala 103:39] + wire _T_694 : UInt<8>[8] @[lsu_dccm_ctl.scala 149:62] + _T_694[0] <= _T_420 @[lsu_dccm_ctl.scala 149:62] + _T_694[1] <= _T_459 @[lsu_dccm_ctl.scala 149:62] + _T_694[2] <= _T_498 @[lsu_dccm_ctl.scala 149:62] + _T_694[3] <= _T_537 @[lsu_dccm_ctl.scala 149:62] + _T_694[4] <= _T_576 @[lsu_dccm_ctl.scala 149:62] + _T_694[5] <= _T_615 @[lsu_dccm_ctl.scala 149:62] + _T_694[6] <= _T_654 @[lsu_dccm_ctl.scala 149:62] + _T_694[7] <= _T_693 @[lsu_dccm_ctl.scala 149:62] + node _T_695 = cat(_T_694[6], _T_694[7]) @[Cat.scala 29:58] + node _T_696 = cat(_T_694[4], _T_694[5]) @[Cat.scala 29:58] + node _T_697 = cat(_T_696, _T_695) @[Cat.scala 29:58] + node _T_698 = cat(_T_694[2], _T_694[3]) @[Cat.scala 29:58] + node _T_699 = cat(_T_694[0], _T_694[1]) @[Cat.scala 29:58] + node _T_700 = cat(_T_699, _T_698) @[Cat.scala 29:58] + node _T_701 = cat(_T_700, _T_697) @[Cat.scala 29:58] + node _T_702 = shl(UInt<32>("h0ffffffff"), 32) @[Bitwise.scala 102:47] + node _T_703 = xor(UInt<64>("h0ffffffffffffffff"), _T_702) @[Bitwise.scala 102:21] + node _T_704 = shr(_T_701, 32) @[Bitwise.scala 103:21] + node _T_705 = and(_T_704, _T_703) @[Bitwise.scala 103:31] + node _T_706 = bits(_T_701, 31, 0) @[Bitwise.scala 103:46] + node _T_707 = shl(_T_706, 32) @[Bitwise.scala 103:65] + node _T_708 = not(_T_703) @[Bitwise.scala 103:77] + node _T_709 = and(_T_707, _T_708) @[Bitwise.scala 103:75] + node _T_710 = or(_T_705, _T_709) @[Bitwise.scala 103:39] + node _T_711 = bits(_T_703, 47, 0) @[Bitwise.scala 102:28] + node _T_712 = shl(_T_711, 16) @[Bitwise.scala 102:47] + node _T_713 = xor(_T_703, _T_712) @[Bitwise.scala 102:21] + node _T_714 = shr(_T_710, 16) @[Bitwise.scala 103:21] + node _T_715 = and(_T_714, _T_713) @[Bitwise.scala 103:31] + node _T_716 = bits(_T_710, 47, 0) @[Bitwise.scala 103:46] + node _T_717 = shl(_T_716, 16) @[Bitwise.scala 103:65] + node _T_718 = not(_T_713) @[Bitwise.scala 103:77] + node _T_719 = and(_T_717, _T_718) @[Bitwise.scala 103:75] + node _T_720 = or(_T_715, _T_719) @[Bitwise.scala 103:39] + node _T_721 = bits(_T_713, 55, 0) @[Bitwise.scala 102:28] + node _T_722 = shl(_T_721, 8) @[Bitwise.scala 102:47] + node _T_723 = xor(_T_713, _T_722) @[Bitwise.scala 102:21] + node _T_724 = shr(_T_720, 8) @[Bitwise.scala 103:21] + node _T_725 = and(_T_724, _T_723) @[Bitwise.scala 103:31] + node _T_726 = bits(_T_720, 55, 0) @[Bitwise.scala 103:46] + node _T_727 = shl(_T_726, 8) @[Bitwise.scala 103:65] + node _T_728 = not(_T_723) @[Bitwise.scala 103:77] + node _T_729 = and(_T_727, _T_728) @[Bitwise.scala 103:75] + node _T_730 = or(_T_725, _T_729) @[Bitwise.scala 103:39] + node _T_731 = bits(_T_723, 59, 0) @[Bitwise.scala 102:28] + node _T_732 = shl(_T_731, 4) @[Bitwise.scala 102:47] + node _T_733 = xor(_T_723, _T_732) @[Bitwise.scala 102:21] + node _T_734 = shr(_T_730, 4) @[Bitwise.scala 103:21] + node _T_735 = and(_T_734, _T_733) @[Bitwise.scala 103:31] + node _T_736 = bits(_T_730, 59, 0) @[Bitwise.scala 103:46] + node _T_737 = shl(_T_736, 4) @[Bitwise.scala 103:65] + node _T_738 = not(_T_733) @[Bitwise.scala 103:77] + node _T_739 = and(_T_737, _T_738) @[Bitwise.scala 103:75] + node _T_740 = or(_T_735, _T_739) @[Bitwise.scala 103:39] + node _T_741 = bits(_T_733, 61, 0) @[Bitwise.scala 102:28] + node _T_742 = shl(_T_741, 2) @[Bitwise.scala 102:47] + node _T_743 = xor(_T_733, _T_742) @[Bitwise.scala 102:21] + node _T_744 = shr(_T_740, 2) @[Bitwise.scala 103:21] + node _T_745 = and(_T_744, _T_743) @[Bitwise.scala 103:31] + node _T_746 = bits(_T_740, 61, 0) @[Bitwise.scala 103:46] + node _T_747 = shl(_T_746, 2) @[Bitwise.scala 103:65] + node _T_748 = not(_T_743) @[Bitwise.scala 103:77] + node _T_749 = and(_T_747, _T_748) @[Bitwise.scala 103:75] + node _T_750 = or(_T_745, _T_749) @[Bitwise.scala 103:39] + node _T_751 = bits(_T_743, 62, 0) @[Bitwise.scala 102:28] + node _T_752 = shl(_T_751, 1) @[Bitwise.scala 102:47] + node _T_753 = xor(_T_743, _T_752) @[Bitwise.scala 102:21] + node _T_754 = shr(_T_750, 1) @[Bitwise.scala 103:21] + node _T_755 = and(_T_754, _T_753) @[Bitwise.scala 103:31] + node _T_756 = bits(_T_750, 62, 0) @[Bitwise.scala 103:46] + node _T_757 = shl(_T_756, 1) @[Bitwise.scala 103:65] + node _T_758 = not(_T_753) @[Bitwise.scala 103:77] + node _T_759 = and(_T_757, _T_758) @[Bitwise.scala 103:75] + node _T_760 = or(_T_755, _T_759) @[Bitwise.scala 103:39] + lsu_rdata_m <= _T_760 @[lsu_dccm_ctl.scala 149:28] + node _T_761 = bits(io.lsu_addr_m, 1, 0) @[lsu_dccm_ctl.scala 150:63] + node _T_762 = mul(UInt<4>("h08"), _T_761) @[lsu_dccm_ctl.scala 150:49] + node _T_763 = dshr(lsu_rdata_m, _T_762) @[lsu_dccm_ctl.scala 150:43] + io.lsu_ld_data_m <= _T_763 @[lsu_dccm_ctl.scala 150:28] + node _T_764 = bits(io.lsu_addr_m, 1, 0) @[lsu_dccm_ctl.scala 151:68] + node _T_765 = mul(UInt<4>("h08"), _T_764) @[lsu_dccm_ctl.scala 151:54] + node _T_766 = dshr(lsu_rdata_corr_m, _T_765) @[lsu_dccm_ctl.scala 151:48] + lsu_ld_data_corr_m <= _T_766 @[lsu_dccm_ctl.scala 151:28] + node _T_767 = bits(io.lsu_addr_d, 15, 2) @[lsu_dccm_ctl.scala 155:44] + node _T_768 = bits(io.lsu_addr_r, 15, 2) @[lsu_dccm_ctl.scala 155:77] + node _T_769 = eq(_T_767, _T_768) @[lsu_dccm_ctl.scala 155:60] + node _T_770 = bits(io.end_addr_d, 15, 2) @[lsu_dccm_ctl.scala 155:117] + node _T_771 = bits(io.lsu_addr_r, 15, 2) @[lsu_dccm_ctl.scala 155:150] + node _T_772 = eq(_T_770, _T_771) @[lsu_dccm_ctl.scala 155:133] + node _T_773 = or(_T_769, _T_772) @[lsu_dccm_ctl.scala 155:101] + node _T_774 = and(_T_773, io.lsu_pkt_d.valid) @[lsu_dccm_ctl.scala 155:175] + node _T_775 = and(_T_774, io.lsu_pkt_d.bits.store) @[lsu_dccm_ctl.scala 155:196] + node _T_776 = and(_T_775, io.lsu_pkt_d.bits.dma) @[lsu_dccm_ctl.scala 155:222] + node _T_777 = and(_T_776, io.addr_in_dccm_d) @[lsu_dccm_ctl.scala 155:246] + node _T_778 = bits(io.lsu_addr_m, 15, 2) @[lsu_dccm_ctl.scala 156:21] + node _T_779 = bits(io.lsu_addr_r, 15, 2) @[lsu_dccm_ctl.scala 156:54] + node _T_780 = eq(_T_778, _T_779) @[lsu_dccm_ctl.scala 156:37] + node _T_781 = bits(io.end_addr_m, 15, 2) @[lsu_dccm_ctl.scala 156:94] + node _T_782 = bits(io.lsu_addr_r, 15, 2) @[lsu_dccm_ctl.scala 156:127] + node _T_783 = eq(_T_781, _T_782) @[lsu_dccm_ctl.scala 156:110] + node _T_784 = or(_T_780, _T_783) @[lsu_dccm_ctl.scala 156:78] + node _T_785 = and(_T_784, io.lsu_pkt_m.valid) @[lsu_dccm_ctl.scala 156:152] + node _T_786 = and(_T_785, io.lsu_pkt_m.bits.store) @[lsu_dccm_ctl.scala 156:173] + node _T_787 = and(_T_786, io.lsu_pkt_m.bits.dma) @[lsu_dccm_ctl.scala 156:199] + node _T_788 = and(_T_787, io.addr_in_dccm_m) @[lsu_dccm_ctl.scala 156:223] + node kill_ecc_corr_lo_r = or(_T_777, _T_788) @[lsu_dccm_ctl.scala 155:267] + node _T_789 = bits(io.lsu_addr_d, 15, 2) @[lsu_dccm_ctl.scala 158:44] + node _T_790 = bits(io.end_addr_r, 15, 2) @[lsu_dccm_ctl.scala 158:77] + node _T_791 = eq(_T_789, _T_790) @[lsu_dccm_ctl.scala 158:60] + node _T_792 = bits(io.end_addr_d, 15, 2) @[lsu_dccm_ctl.scala 158:117] + node _T_793 = bits(io.end_addr_r, 15, 2) @[lsu_dccm_ctl.scala 158:150] + node _T_794 = eq(_T_792, _T_793) @[lsu_dccm_ctl.scala 158:133] + node _T_795 = or(_T_791, _T_794) @[lsu_dccm_ctl.scala 158:101] + node _T_796 = and(_T_795, io.lsu_pkt_d.valid) @[lsu_dccm_ctl.scala 158:175] + node _T_797 = and(_T_796, io.lsu_pkt_d.bits.store) @[lsu_dccm_ctl.scala 158:196] + node _T_798 = and(_T_797, io.lsu_pkt_d.bits.dma) @[lsu_dccm_ctl.scala 158:222] + node _T_799 = and(_T_798, io.addr_in_dccm_d) @[lsu_dccm_ctl.scala 158:246] + node _T_800 = bits(io.lsu_addr_m, 15, 2) @[lsu_dccm_ctl.scala 159:21] + node _T_801 = bits(io.end_addr_r, 15, 2) @[lsu_dccm_ctl.scala 159:54] + node _T_802 = eq(_T_800, _T_801) @[lsu_dccm_ctl.scala 159:37] + node _T_803 = bits(io.end_addr_m, 15, 2) @[lsu_dccm_ctl.scala 159:94] + node _T_804 = bits(io.end_addr_r, 15, 2) @[lsu_dccm_ctl.scala 159:127] + node _T_805 = eq(_T_803, _T_804) @[lsu_dccm_ctl.scala 159:110] + node _T_806 = or(_T_802, _T_805) @[lsu_dccm_ctl.scala 159:78] + node _T_807 = and(_T_806, io.lsu_pkt_m.valid) @[lsu_dccm_ctl.scala 159:152] + node _T_808 = and(_T_807, io.lsu_pkt_m.bits.store) @[lsu_dccm_ctl.scala 159:173] + node _T_809 = and(_T_808, io.lsu_pkt_m.bits.dma) @[lsu_dccm_ctl.scala 159:199] + node _T_810 = and(_T_809, io.addr_in_dccm_m) @[lsu_dccm_ctl.scala 159:223] + node kill_ecc_corr_hi_r = or(_T_799, _T_810) @[lsu_dccm_ctl.scala 158:267] + node _T_811 = and(io.lsu_pkt_r.bits.load, io.single_ecc_error_lo_r) @[lsu_dccm_ctl.scala 161:60] + node _T_812 = eq(io.lsu_raw_fwd_lo_r, UInt<1>("h00")) @[lsu_dccm_ctl.scala 161:89] + node ld_single_ecc_error_lo_r = and(_T_811, _T_812) @[lsu_dccm_ctl.scala 161:87] + node _T_813 = and(io.lsu_pkt_r.bits.load, io.single_ecc_error_hi_r) @[lsu_dccm_ctl.scala 162:60] + node _T_814 = eq(io.lsu_raw_fwd_hi_r, UInt<1>("h00")) @[lsu_dccm_ctl.scala 162:89] + node ld_single_ecc_error_hi_r = and(_T_813, _T_814) @[lsu_dccm_ctl.scala 162:87] + node _T_815 = or(ld_single_ecc_error_lo_r, ld_single_ecc_error_hi_r) @[lsu_dccm_ctl.scala 163:63] + node _T_816 = eq(io.lsu_double_ecc_error_r, UInt<1>("h00")) @[lsu_dccm_ctl.scala 163:93] + node _T_817 = and(_T_815, _T_816) @[lsu_dccm_ctl.scala 163:91] + io.ld_single_ecc_error_r <= _T_817 @[lsu_dccm_ctl.scala 163:34] + node _T_818 = or(io.lsu_commit_r, io.lsu_pkt_r.bits.dma) @[lsu_dccm_ctl.scala 164:81] + node _T_819 = and(ld_single_ecc_error_lo_r, _T_818) @[lsu_dccm_ctl.scala 164:62] + node _T_820 = eq(kill_ecc_corr_lo_r, UInt<1>("h00")) @[lsu_dccm_ctl.scala 164:108] + node ld_single_ecc_error_lo_r_ns = and(_T_819, _T_820) @[lsu_dccm_ctl.scala 164:106] + node _T_821 = or(io.lsu_commit_r, io.lsu_pkt_r.bits.dma) @[lsu_dccm_ctl.scala 165:81] + node _T_822 = and(ld_single_ecc_error_hi_r, _T_821) @[lsu_dccm_ctl.scala 165:62] + node _T_823 = eq(kill_ecc_corr_hi_r, UInt<1>("h00")) @[lsu_dccm_ctl.scala 165:108] + node ld_single_ecc_error_hi_r_ns = and(_T_822, _T_823) @[lsu_dccm_ctl.scala 165:106] + reg lsu_double_ecc_error_r_ff : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_dccm_ctl.scala 167:74] + lsu_double_ecc_error_r_ff <= io.lsu_double_ecc_error_r @[lsu_dccm_ctl.scala 167:74] + reg ld_single_ecc_error_hi_r_ff : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_dccm_ctl.scala 168:74] + ld_single_ecc_error_hi_r_ff <= ld_single_ecc_error_hi_r_ns @[lsu_dccm_ctl.scala 168:74] + reg ld_single_ecc_error_lo_r_ff : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_dccm_ctl.scala 169:74] + ld_single_ecc_error_lo_r_ff <= ld_single_ecc_error_lo_r_ns @[lsu_dccm_ctl.scala 169:74] + node _T_824 = bits(io.end_addr_r, 15, 0) @[lsu_dccm_ctl.scala 171:49] + node _T_825 = bits(io.ld_single_ecc_error_r, 0, 0) @[lsu_dccm_ctl.scala 171:90] + node _T_826 = bits(io.scan_mode, 0, 0) @[lsu_dccm_ctl.scala 171:116] + inst rvclkhdr of rvclkhdr @[lib.scala 368:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[lib.scala 370:18] + rvclkhdr.io.en <= _T_825 @[lib.scala 371:17] + rvclkhdr.io.scan_mode <= _T_826 @[lib.scala 372:24] + reg ld_sec_addr_hi_r_ff : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + ld_sec_addr_hi_r_ff <= _T_824 @[lib.scala 374:16] + node _T_827 = bits(io.lsu_addr_r, 15, 0) @[lsu_dccm_ctl.scala 172:49] + node _T_828 = bits(io.ld_single_ecc_error_r, 0, 0) @[lsu_dccm_ctl.scala 172:90] + node _T_829 = bits(io.scan_mode, 0, 0) @[lsu_dccm_ctl.scala 172:116] + inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 368:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_1.io.en <= _T_828 @[lib.scala 371:17] + rvclkhdr_1.io.scan_mode <= _T_829 @[lib.scala 372:24] + reg ld_sec_addr_lo_r_ff : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + ld_sec_addr_lo_r_ff <= _T_827 @[lib.scala 374:16] + node _T_830 = or(io.lsu_pkt_d.bits.word, io.lsu_pkt_d.bits.dword) @[lsu_dccm_ctl.scala 173:125] + node _T_831 = eq(_T_830, UInt<1>("h00")) @[lsu_dccm_ctl.scala 173:100] + node _T_832 = bits(io.lsu_addr_d, 1, 0) @[lsu_dccm_ctl.scala 173:168] + node _T_833 = neq(_T_832, UInt<2>("h00")) @[lsu_dccm_ctl.scala 173:174] + node _T_834 = or(_T_831, _T_833) @[lsu_dccm_ctl.scala 173:152] + node _T_835 = and(io.lsu_pkt_d.bits.store, _T_834) @[lsu_dccm_ctl.scala 173:97] + node _T_836 = or(io.lsu_pkt_d.bits.load, _T_835) @[lsu_dccm_ctl.scala 173:70] + node _T_837 = and(io.lsu_pkt_d.valid, _T_836) @[lsu_dccm_ctl.scala 173:44] + node lsu_dccm_rden_d = and(_T_837, io.addr_in_dccm_d) @[lsu_dccm_ctl.scala 173:191] + node _T_838 = or(ld_single_ecc_error_lo_r_ff, ld_single_ecc_error_hi_r_ff) @[lsu_dccm_ctl.scala 176:63] + node _T_839 = eq(lsu_double_ecc_error_r_ff, UInt<1>("h00")) @[lsu_dccm_ctl.scala 176:96] + node _T_840 = and(_T_838, _T_839) @[lsu_dccm_ctl.scala 176:94] + io.ld_single_ecc_error_r_ff <= _T_840 @[lsu_dccm_ctl.scala 176:31] + node _T_841 = or(lsu_dccm_rden_d, io.dma_dccm_wen) @[lsu_dccm_ctl.scala 177:75] + node _T_842 = or(_T_841, io.ld_single_ecc_error_r_ff) @[lsu_dccm_ctl.scala 177:93] + node _T_843 = eq(_T_842, UInt<1>("h00")) @[lsu_dccm_ctl.scala 177:57] + node _T_844 = bits(io.stbuf_addr_any, 3, 2) @[lsu_dccm_ctl.scala 178:44] + node _T_845 = bits(io.lsu_addr_d, 3, 2) @[lsu_dccm_ctl.scala 178:112] + node _T_846 = eq(_T_844, _T_845) @[lsu_dccm_ctl.scala 178:95] + node _T_847 = bits(io.stbuf_addr_any, 3, 2) @[lsu_dccm_ctl.scala 179:25] + node _T_848 = bits(io.end_addr_d, 3, 2) @[lsu_dccm_ctl.scala 179:93] + node _T_849 = eq(_T_847, _T_848) @[lsu_dccm_ctl.scala 179:76] + node _T_850 = or(_T_846, _T_849) @[lsu_dccm_ctl.scala 178:171] + node _T_851 = eq(_T_850, UInt<1>("h00")) @[lsu_dccm_ctl.scala 178:24] + node _T_852 = and(lsu_dccm_rden_d, _T_851) @[lsu_dccm_ctl.scala 178:22] + node _T_853 = or(_T_843, _T_852) @[lsu_dccm_ctl.scala 177:124] + node _T_854 = and(io.stbuf_reqvld_any, _T_853) @[lsu_dccm_ctl.scala 177:54] + io.lsu_stbuf_commit_any <= _T_854 @[lsu_dccm_ctl.scala 177:31] + node _T_855 = or(io.dma_dccm_wen, io.lsu_stbuf_commit_any) @[lsu_dccm_ctl.scala 183:41] + node _T_856 = or(_T_855, io.ld_single_ecc_error_r_ff) @[lsu_dccm_ctl.scala 183:67] + io.dccm.wren <= _T_856 @[lsu_dccm_ctl.scala 183:22] + node _T_857 = and(lsu_dccm_rden_d, io.addr_in_dccm_d) @[lsu_dccm_ctl.scala 184:41] + io.dccm.rden <= _T_857 @[lsu_dccm_ctl.scala 184:22] + node _T_858 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[lsu_dccm_ctl.scala 186:57] + node _T_859 = eq(ld_single_ecc_error_lo_r_ff, UInt<1>("h01")) @[lsu_dccm_ctl.scala 187:36] + node _T_860 = bits(ld_sec_addr_lo_r_ff, 15, 0) @[lsu_dccm_ctl.scala 187:62] + node _T_861 = bits(ld_sec_addr_hi_r_ff, 15, 0) @[lsu_dccm_ctl.scala 187:97] + node _T_862 = mux(_T_859, _T_860, _T_861) @[lsu_dccm_ctl.scala 187:8] + node _T_863 = bits(io.dma_dccm_wen, 0, 0) @[lsu_dccm_ctl.scala 188:25] + node _T_864 = bits(io.lsu_addr_d, 15, 0) @[lsu_dccm_ctl.scala 188:45] + node _T_865 = bits(io.stbuf_addr_any, 15, 0) @[lsu_dccm_ctl.scala 188:78] + node _T_866 = mux(_T_863, _T_864, _T_865) @[lsu_dccm_ctl.scala 188:8] + node _T_867 = mux(_T_858, _T_862, _T_866) @[lsu_dccm_ctl.scala 186:28] + io.dccm.wr_addr_lo <= _T_867 @[lsu_dccm_ctl.scala 186:22] + node _T_868 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[lsu_dccm_ctl.scala 190:57] + node _T_869 = eq(ld_single_ecc_error_hi_r_ff, UInt<1>("h01")) @[lsu_dccm_ctl.scala 191:36] + node _T_870 = bits(ld_sec_addr_hi_r_ff, 15, 0) @[lsu_dccm_ctl.scala 191:63] + node _T_871 = bits(ld_sec_addr_lo_r_ff, 15, 0) @[lsu_dccm_ctl.scala 191:99] + node _T_872 = mux(_T_869, _T_870, _T_871) @[lsu_dccm_ctl.scala 191:8] + node _T_873 = bits(io.dma_dccm_wen, 0, 0) @[lsu_dccm_ctl.scala 192:25] + node _T_874 = bits(io.end_addr_d, 15, 0) @[lsu_dccm_ctl.scala 192:46] + node _T_875 = bits(io.stbuf_addr_any, 15, 0) @[lsu_dccm_ctl.scala 192:79] + node _T_876 = mux(_T_873, _T_874, _T_875) @[lsu_dccm_ctl.scala 192:8] + node _T_877 = mux(_T_868, _T_872, _T_876) @[lsu_dccm_ctl.scala 190:28] + io.dccm.wr_addr_hi <= _T_877 @[lsu_dccm_ctl.scala 190:22] + node _T_878 = bits(io.lsu_addr_d, 15, 0) @[lsu_dccm_ctl.scala 194:38] + io.dccm.rd_addr_lo <= _T_878 @[lsu_dccm_ctl.scala 194:22] + node _T_879 = bits(io.end_addr_d, 15, 0) @[lsu_dccm_ctl.scala 195:38] + io.dccm.rd_addr_hi <= _T_879 @[lsu_dccm_ctl.scala 195:22] + node _T_880 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[lsu_dccm_ctl.scala 197:57] + node _T_881 = eq(ld_single_ecc_error_lo_r_ff, UInt<1>("h01")) @[lsu_dccm_ctl.scala 198:36] + node _T_882 = bits(io.sec_data_ecc_lo_r_ff, 6, 0) @[lsu_dccm_ctl.scala 198:70] + node _T_883 = bits(io.sec_data_lo_r_ff, 31, 0) @[lsu_dccm_ctl.scala 198:110] + node _T_884 = cat(_T_882, _T_883) @[Cat.scala 29:58] + node _T_885 = bits(io.sec_data_ecc_hi_r_ff, 6, 0) @[lsu_dccm_ctl.scala 199:34] + node _T_886 = bits(io.sec_data_hi_r_ff, 31, 0) @[lsu_dccm_ctl.scala 199:74] + node _T_887 = cat(_T_885, _T_886) @[Cat.scala 29:58] + node _T_888 = mux(_T_881, _T_884, _T_887) @[lsu_dccm_ctl.scala 198:8] + node _T_889 = bits(io.dma_dccm_wen, 0, 0) @[lsu_dccm_ctl.scala 200:25] + node _T_890 = bits(io.dma_dccm_wdata_ecc_lo, 6, 0) @[lsu_dccm_ctl.scala 200:60] + node _T_891 = bits(io.dma_dccm_wdata_lo, 31, 0) @[lsu_dccm_ctl.scala 200:101] + node _T_892 = cat(_T_890, _T_891) @[Cat.scala 29:58] + node _T_893 = bits(io.stbuf_ecc_any, 6, 0) @[lsu_dccm_ctl.scala 201:27] + node _T_894 = bits(io.stbuf_data_any, 31, 0) @[lsu_dccm_ctl.scala 201:65] + node _T_895 = cat(_T_893, _T_894) @[Cat.scala 29:58] + node _T_896 = mux(_T_889, _T_892, _T_895) @[lsu_dccm_ctl.scala 200:8] + node _T_897 = mux(_T_880, _T_888, _T_896) @[lsu_dccm_ctl.scala 197:28] + io.dccm.wr_data_lo <= _T_897 @[lsu_dccm_ctl.scala 197:22] + node _T_898 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[lsu_dccm_ctl.scala 203:57] + node _T_899 = eq(ld_single_ecc_error_hi_r_ff, UInt<1>("h01")) @[lsu_dccm_ctl.scala 204:36] + node _T_900 = bits(io.sec_data_ecc_hi_r_ff, 6, 0) @[lsu_dccm_ctl.scala 204:71] + node _T_901 = bits(io.sec_data_hi_r_ff, 31, 0) @[lsu_dccm_ctl.scala 204:111] + node _T_902 = cat(_T_900, _T_901) @[Cat.scala 29:58] + node _T_903 = bits(io.sec_data_ecc_lo_r_ff, 6, 0) @[lsu_dccm_ctl.scala 205:34] + node _T_904 = bits(io.sec_data_lo_r_ff, 31, 0) @[lsu_dccm_ctl.scala 205:74] + node _T_905 = cat(_T_903, _T_904) @[Cat.scala 29:58] + node _T_906 = mux(_T_899, _T_902, _T_905) @[lsu_dccm_ctl.scala 204:8] + node _T_907 = bits(io.dma_dccm_wen, 0, 0) @[lsu_dccm_ctl.scala 206:25] + node _T_908 = bits(io.dma_dccm_wdata_ecc_hi, 6, 0) @[lsu_dccm_ctl.scala 206:61] + node _T_909 = bits(io.dma_dccm_wdata_hi, 31, 0) @[lsu_dccm_ctl.scala 206:102] + node _T_910 = cat(_T_908, _T_909) @[Cat.scala 29:58] + node _T_911 = bits(io.stbuf_ecc_any, 6, 0) @[lsu_dccm_ctl.scala 207:27] + node _T_912 = bits(io.stbuf_data_any, 31, 0) @[lsu_dccm_ctl.scala 207:65] + node _T_913 = cat(_T_911, _T_912) @[Cat.scala 29:58] + node _T_914 = mux(_T_907, _T_910, _T_913) @[lsu_dccm_ctl.scala 206:8] + node _T_915 = mux(_T_898, _T_906, _T_914) @[lsu_dccm_ctl.scala 203:28] + io.dccm.wr_data_hi <= _T_915 @[lsu_dccm_ctl.scala 203:22] + node _T_916 = bits(io.lsu_pkt_m.bits.store, 0, 0) @[Bitwise.scala 72:15] + node _T_917 = mux(_T_916, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_918 = bits(io.lsu_pkt_m.bits.by, 0, 0) @[Bitwise.scala 72:15] + node _T_919 = mux(_T_918, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_920 = and(_T_919, UInt<4>("h01")) @[lsu_dccm_ctl.scala 210:94] + node _T_921 = bits(io.lsu_pkt_m.bits.half, 0, 0) @[Bitwise.scala 72:15] + node _T_922 = mux(_T_921, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_923 = and(_T_922, UInt<4>("h03")) @[lsu_dccm_ctl.scala 211:38] + node _T_924 = or(_T_920, _T_923) @[lsu_dccm_ctl.scala 210:107] + node _T_925 = bits(io.lsu_pkt_m.bits.word, 0, 0) @[Bitwise.scala 72:15] + node _T_926 = mux(_T_925, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_927 = and(_T_926, UInt<4>("h0f")) @[lsu_dccm_ctl.scala 212:38] + node _T_928 = or(_T_924, _T_927) @[lsu_dccm_ctl.scala 211:51] + node store_byteen_m = and(_T_917, _T_928) @[lsu_dccm_ctl.scala 210:58] + node _T_929 = bits(io.lsu_pkt_r.bits.store, 0, 0) @[Bitwise.scala 72:15] + node _T_930 = mux(_T_929, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_931 = bits(io.lsu_pkt_r.bits.by, 0, 0) @[Bitwise.scala 72:15] + node _T_932 = mux(_T_931, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_933 = and(_T_932, UInt<4>("h01")) @[lsu_dccm_ctl.scala 214:94] + node _T_934 = bits(io.lsu_pkt_r.bits.half, 0, 0) @[Bitwise.scala 72:15] + node _T_935 = mux(_T_934, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_936 = and(_T_935, UInt<4>("h03")) @[lsu_dccm_ctl.scala 215:38] + node _T_937 = or(_T_933, _T_936) @[lsu_dccm_ctl.scala 214:107] + node _T_938 = bits(io.lsu_pkt_r.bits.word, 0, 0) @[Bitwise.scala 72:15] + node _T_939 = mux(_T_938, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_940 = and(_T_939, UInt<4>("h0f")) @[lsu_dccm_ctl.scala 216:38] + node _T_941 = or(_T_937, _T_940) @[lsu_dccm_ctl.scala 215:51] + node store_byteen_r = and(_T_930, _T_941) @[lsu_dccm_ctl.scala 214:58] + wire store_byteen_ext_m : UInt<8> + store_byteen_ext_m <= UInt<1>("h00") + node _T_942 = bits(store_byteen_m, 3, 0) @[lsu_dccm_ctl.scala 218:39] + node _T_943 = bits(io.lsu_addr_m, 1, 0) @[lsu_dccm_ctl.scala 218:61] + node _T_944 = dshl(_T_942, _T_943) @[lsu_dccm_ctl.scala 218:45] + store_byteen_ext_m <= _T_944 @[lsu_dccm_ctl.scala 218:22] + wire store_byteen_ext_r : UInt<8> + store_byteen_ext_r <= UInt<1>("h00") + node _T_945 = bits(store_byteen_r, 3, 0) @[lsu_dccm_ctl.scala 220:39] + node _T_946 = bits(io.lsu_addr_r, 1, 0) @[lsu_dccm_ctl.scala 220:61] + node _T_947 = dshl(_T_945, _T_946) @[lsu_dccm_ctl.scala 220:45] + store_byteen_ext_r <= _T_947 @[lsu_dccm_ctl.scala 220:22] + node _T_948 = bits(io.stbuf_addr_any, 15, 2) @[lsu_dccm_ctl.scala 223:51] + node _T_949 = bits(io.lsu_addr_m, 15, 2) @[lsu_dccm_ctl.scala 223:84] + node _T_950 = eq(_T_948, _T_949) @[lsu_dccm_ctl.scala 223:67] + node dccm_wr_bypass_d_m_lo = and(_T_950, io.addr_in_dccm_m) @[lsu_dccm_ctl.scala 223:101] + node _T_951 = bits(io.stbuf_addr_any, 15, 2) @[lsu_dccm_ctl.scala 224:51] + node _T_952 = bits(io.end_addr_m, 15, 2) @[lsu_dccm_ctl.scala 224:84] + node _T_953 = eq(_T_951, _T_952) @[lsu_dccm_ctl.scala 224:67] + node dccm_wr_bypass_d_m_hi = and(_T_953, io.addr_in_dccm_m) @[lsu_dccm_ctl.scala 224:101] + node _T_954 = bits(io.stbuf_addr_any, 15, 2) @[lsu_dccm_ctl.scala 226:51] + node _T_955 = bits(io.lsu_addr_r, 15, 2) @[lsu_dccm_ctl.scala 226:84] + node _T_956 = eq(_T_954, _T_955) @[lsu_dccm_ctl.scala 226:67] + node dccm_wr_bypass_d_r_lo = and(_T_956, io.addr_in_dccm_r) @[lsu_dccm_ctl.scala 226:101] + node _T_957 = bits(io.stbuf_addr_any, 15, 2) @[lsu_dccm_ctl.scala 227:51] + node _T_958 = bits(io.end_addr_r, 15, 2) @[lsu_dccm_ctl.scala 227:84] + node _T_959 = eq(_T_957, _T_958) @[lsu_dccm_ctl.scala 227:67] + node dccm_wr_bypass_d_r_hi = and(_T_959, io.addr_in_dccm_r) @[lsu_dccm_ctl.scala 227:101] + wire dccm_wr_bypass_d_m_hi_Q : UInt<1> + dccm_wr_bypass_d_m_hi_Q <= UInt<1>("h00") + wire dccm_wr_bypass_d_m_lo_Q : UInt<1> + dccm_wr_bypass_d_m_lo_Q <= UInt<1>("h00") + wire dccm_wren_Q : UInt<1> + dccm_wren_Q <= UInt<1>("h00") + wire dccm_wr_data_Q : UInt<32> + dccm_wr_data_Q <= UInt<32>("h00") + wire store_data_pre_r : UInt<64> + store_data_pre_r <= UInt<64>("h00") + wire store_data_pre_hi_r : UInt<32> + store_data_pre_hi_r <= UInt<32>("h00") + wire store_data_pre_lo_r : UInt<32> + store_data_pre_lo_r <= UInt<32>("h00") + wire store_data_pre_m : UInt<64> + store_data_pre_m <= UInt<64>("h00") + wire store_data_hi_m : UInt<32> + store_data_hi_m <= UInt<32>("h00") + wire store_data_lo_m : UInt<32> + store_data_lo_m <= UInt<32>("h00") + node _T_960 = mux(UInt<1>("h00"), UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_961 = bits(io.store_data_m, 31, 0) @[lsu_dccm_ctl.scala 256:64] + node _T_962 = cat(_T_960, _T_961) @[Cat.scala 29:58] + node _T_963 = bits(io.lsu_addr_m, 1, 0) @[lsu_dccm_ctl.scala 256:92] + node _T_964 = mul(UInt<4>("h08"), _T_963) @[lsu_dccm_ctl.scala 256:78] + node _T_965 = dshl(_T_962, _T_964) @[lsu_dccm_ctl.scala 256:72] + store_data_pre_m <= _T_965 @[lsu_dccm_ctl.scala 256:29] + node _T_966 = bits(store_data_pre_m, 63, 32) @[lsu_dccm_ctl.scala 257:48] + store_data_hi_m <= _T_966 @[lsu_dccm_ctl.scala 257:29] + node _T_967 = bits(store_data_pre_m, 31, 0) @[lsu_dccm_ctl.scala 258:48] + store_data_lo_m <= _T_967 @[lsu_dccm_ctl.scala 258:29] + node _T_968 = bits(store_byteen_ext_m, 0, 0) @[lsu_dccm_ctl.scala 259:139] + node _T_969 = bits(_T_968, 0, 0) @[lsu_dccm_ctl.scala 259:143] + node _T_970 = bits(store_data_lo_m, 7, 0) @[lsu_dccm_ctl.scala 259:167] + node _T_971 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_lo) @[lsu_dccm_ctl.scala 259:211] + node _T_972 = bits(_T_971, 0, 0) @[lsu_dccm_ctl.scala 259:237] + node _T_973 = bits(io.stbuf_data_any, 7, 0) @[lsu_dccm_ctl.scala 259:262] + node _T_974 = bits(io.sec_data_lo_m, 7, 0) @[lsu_dccm_ctl.scala 259:292] + node _T_975 = mux(_T_972, _T_973, _T_974) @[lsu_dccm_ctl.scala 259:185] + node _T_976 = mux(_T_969, _T_970, _T_975) @[lsu_dccm_ctl.scala 259:120] + node _T_977 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_978 = xor(UInt<8>("h0ff"), _T_977) @[Bitwise.scala 102:21] + node _T_979 = shr(_T_976, 4) @[Bitwise.scala 103:21] + node _T_980 = and(_T_979, _T_978) @[Bitwise.scala 103:31] + node _T_981 = bits(_T_976, 3, 0) @[Bitwise.scala 103:46] + node _T_982 = shl(_T_981, 4) @[Bitwise.scala 103:65] + node _T_983 = not(_T_978) @[Bitwise.scala 103:77] + node _T_984 = and(_T_982, _T_983) @[Bitwise.scala 103:75] + node _T_985 = or(_T_980, _T_984) @[Bitwise.scala 103:39] + node _T_986 = bits(_T_978, 5, 0) @[Bitwise.scala 102:28] + node _T_987 = shl(_T_986, 2) @[Bitwise.scala 102:47] + node _T_988 = xor(_T_978, _T_987) @[Bitwise.scala 102:21] + node _T_989 = shr(_T_985, 2) @[Bitwise.scala 103:21] + node _T_990 = and(_T_989, _T_988) @[Bitwise.scala 103:31] + node _T_991 = bits(_T_985, 5, 0) @[Bitwise.scala 103:46] + node _T_992 = shl(_T_991, 2) @[Bitwise.scala 103:65] + node _T_993 = not(_T_988) @[Bitwise.scala 103:77] + node _T_994 = and(_T_992, _T_993) @[Bitwise.scala 103:75] + node _T_995 = or(_T_990, _T_994) @[Bitwise.scala 103:39] + node _T_996 = bits(_T_988, 6, 0) @[Bitwise.scala 102:28] + node _T_997 = shl(_T_996, 1) @[Bitwise.scala 102:47] + node _T_998 = xor(_T_988, _T_997) @[Bitwise.scala 102:21] + node _T_999 = shr(_T_995, 1) @[Bitwise.scala 103:21] + node _T_1000 = and(_T_999, _T_998) @[Bitwise.scala 103:31] + node _T_1001 = bits(_T_995, 6, 0) @[Bitwise.scala 103:46] + node _T_1002 = shl(_T_1001, 1) @[Bitwise.scala 103:65] + node _T_1003 = not(_T_998) @[Bitwise.scala 103:77] + node _T_1004 = and(_T_1002, _T_1003) @[Bitwise.scala 103:75] + node _T_1005 = or(_T_1000, _T_1004) @[Bitwise.scala 103:39] + node _T_1006 = bits(store_byteen_ext_m, 1, 1) @[lsu_dccm_ctl.scala 259:139] + node _T_1007 = bits(_T_1006, 0, 0) @[lsu_dccm_ctl.scala 259:143] + node _T_1008 = bits(store_data_lo_m, 15, 8) @[lsu_dccm_ctl.scala 259:167] + node _T_1009 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_lo) @[lsu_dccm_ctl.scala 259:211] + node _T_1010 = bits(_T_1009, 0, 0) @[lsu_dccm_ctl.scala 259:237] + node _T_1011 = bits(io.stbuf_data_any, 15, 8) @[lsu_dccm_ctl.scala 259:262] + node _T_1012 = bits(io.sec_data_lo_m, 15, 8) @[lsu_dccm_ctl.scala 259:292] + node _T_1013 = mux(_T_1010, _T_1011, _T_1012) @[lsu_dccm_ctl.scala 259:185] + node _T_1014 = mux(_T_1007, _T_1008, _T_1013) @[lsu_dccm_ctl.scala 259:120] + node _T_1015 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1016 = xor(UInt<8>("h0ff"), _T_1015) @[Bitwise.scala 102:21] + node _T_1017 = shr(_T_1014, 4) @[Bitwise.scala 103:21] + node _T_1018 = and(_T_1017, _T_1016) @[Bitwise.scala 103:31] + node _T_1019 = bits(_T_1014, 3, 0) @[Bitwise.scala 103:46] + node _T_1020 = shl(_T_1019, 4) @[Bitwise.scala 103:65] + node _T_1021 = not(_T_1016) @[Bitwise.scala 103:77] + node _T_1022 = and(_T_1020, _T_1021) @[Bitwise.scala 103:75] + node _T_1023 = or(_T_1018, _T_1022) @[Bitwise.scala 103:39] + node _T_1024 = bits(_T_1016, 5, 0) @[Bitwise.scala 102:28] + node _T_1025 = shl(_T_1024, 2) @[Bitwise.scala 102:47] + node _T_1026 = xor(_T_1016, _T_1025) @[Bitwise.scala 102:21] + node _T_1027 = shr(_T_1023, 2) @[Bitwise.scala 103:21] + node _T_1028 = and(_T_1027, _T_1026) @[Bitwise.scala 103:31] + node _T_1029 = bits(_T_1023, 5, 0) @[Bitwise.scala 103:46] + node _T_1030 = shl(_T_1029, 2) @[Bitwise.scala 103:65] + node _T_1031 = not(_T_1026) @[Bitwise.scala 103:77] + node _T_1032 = and(_T_1030, _T_1031) @[Bitwise.scala 103:75] + node _T_1033 = or(_T_1028, _T_1032) @[Bitwise.scala 103:39] + node _T_1034 = bits(_T_1026, 6, 0) @[Bitwise.scala 102:28] + node _T_1035 = shl(_T_1034, 1) @[Bitwise.scala 102:47] + node _T_1036 = xor(_T_1026, _T_1035) @[Bitwise.scala 102:21] + node _T_1037 = shr(_T_1033, 1) @[Bitwise.scala 103:21] + node _T_1038 = and(_T_1037, _T_1036) @[Bitwise.scala 103:31] + node _T_1039 = bits(_T_1033, 6, 0) @[Bitwise.scala 103:46] + node _T_1040 = shl(_T_1039, 1) @[Bitwise.scala 103:65] + node _T_1041 = not(_T_1036) @[Bitwise.scala 103:77] + node _T_1042 = and(_T_1040, _T_1041) @[Bitwise.scala 103:75] + node _T_1043 = or(_T_1038, _T_1042) @[Bitwise.scala 103:39] + node _T_1044 = bits(store_byteen_ext_m, 2, 2) @[lsu_dccm_ctl.scala 259:139] + node _T_1045 = bits(_T_1044, 0, 0) @[lsu_dccm_ctl.scala 259:143] + node _T_1046 = bits(store_data_lo_m, 23, 16) @[lsu_dccm_ctl.scala 259:167] + node _T_1047 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_lo) @[lsu_dccm_ctl.scala 259:211] + node _T_1048 = bits(_T_1047, 0, 0) @[lsu_dccm_ctl.scala 259:237] + node _T_1049 = bits(io.stbuf_data_any, 23, 16) @[lsu_dccm_ctl.scala 259:262] + node _T_1050 = bits(io.sec_data_lo_m, 23, 16) @[lsu_dccm_ctl.scala 259:292] + node _T_1051 = mux(_T_1048, _T_1049, _T_1050) @[lsu_dccm_ctl.scala 259:185] + node _T_1052 = mux(_T_1045, _T_1046, _T_1051) @[lsu_dccm_ctl.scala 259:120] + node _T_1053 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1054 = xor(UInt<8>("h0ff"), _T_1053) @[Bitwise.scala 102:21] + node _T_1055 = shr(_T_1052, 4) @[Bitwise.scala 103:21] + node _T_1056 = and(_T_1055, _T_1054) @[Bitwise.scala 103:31] + node _T_1057 = bits(_T_1052, 3, 0) @[Bitwise.scala 103:46] + node _T_1058 = shl(_T_1057, 4) @[Bitwise.scala 103:65] + node _T_1059 = not(_T_1054) @[Bitwise.scala 103:77] + node _T_1060 = and(_T_1058, _T_1059) @[Bitwise.scala 103:75] + node _T_1061 = or(_T_1056, _T_1060) @[Bitwise.scala 103:39] + node _T_1062 = bits(_T_1054, 5, 0) @[Bitwise.scala 102:28] + node _T_1063 = shl(_T_1062, 2) @[Bitwise.scala 102:47] + node _T_1064 = xor(_T_1054, _T_1063) @[Bitwise.scala 102:21] + node _T_1065 = shr(_T_1061, 2) @[Bitwise.scala 103:21] + node _T_1066 = and(_T_1065, _T_1064) @[Bitwise.scala 103:31] + node _T_1067 = bits(_T_1061, 5, 0) @[Bitwise.scala 103:46] + node _T_1068 = shl(_T_1067, 2) @[Bitwise.scala 103:65] + node _T_1069 = not(_T_1064) @[Bitwise.scala 103:77] + node _T_1070 = and(_T_1068, _T_1069) @[Bitwise.scala 103:75] + node _T_1071 = or(_T_1066, _T_1070) @[Bitwise.scala 103:39] + node _T_1072 = bits(_T_1064, 6, 0) @[Bitwise.scala 102:28] + node _T_1073 = shl(_T_1072, 1) @[Bitwise.scala 102:47] + node _T_1074 = xor(_T_1064, _T_1073) @[Bitwise.scala 102:21] + node _T_1075 = shr(_T_1071, 1) @[Bitwise.scala 103:21] + node _T_1076 = and(_T_1075, _T_1074) @[Bitwise.scala 103:31] + node _T_1077 = bits(_T_1071, 6, 0) @[Bitwise.scala 103:46] + node _T_1078 = shl(_T_1077, 1) @[Bitwise.scala 103:65] + node _T_1079 = not(_T_1074) @[Bitwise.scala 103:77] + node _T_1080 = and(_T_1078, _T_1079) @[Bitwise.scala 103:75] + node _T_1081 = or(_T_1076, _T_1080) @[Bitwise.scala 103:39] + node _T_1082 = bits(store_byteen_ext_m, 3, 3) @[lsu_dccm_ctl.scala 259:139] + node _T_1083 = bits(_T_1082, 0, 0) @[lsu_dccm_ctl.scala 259:143] + node _T_1084 = bits(store_data_lo_m, 31, 24) @[lsu_dccm_ctl.scala 259:167] + node _T_1085 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_lo) @[lsu_dccm_ctl.scala 259:211] + node _T_1086 = bits(_T_1085, 0, 0) @[lsu_dccm_ctl.scala 259:237] + node _T_1087 = bits(io.stbuf_data_any, 31, 24) @[lsu_dccm_ctl.scala 259:262] + node _T_1088 = bits(io.sec_data_lo_m, 31, 24) @[lsu_dccm_ctl.scala 259:292] + node _T_1089 = mux(_T_1086, _T_1087, _T_1088) @[lsu_dccm_ctl.scala 259:185] + node _T_1090 = mux(_T_1083, _T_1084, _T_1089) @[lsu_dccm_ctl.scala 259:120] + node _T_1091 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1092 = xor(UInt<8>("h0ff"), _T_1091) @[Bitwise.scala 102:21] + node _T_1093 = shr(_T_1090, 4) @[Bitwise.scala 103:21] + node _T_1094 = and(_T_1093, _T_1092) @[Bitwise.scala 103:31] + node _T_1095 = bits(_T_1090, 3, 0) @[Bitwise.scala 103:46] + node _T_1096 = shl(_T_1095, 4) @[Bitwise.scala 103:65] + node _T_1097 = not(_T_1092) @[Bitwise.scala 103:77] + node _T_1098 = and(_T_1096, _T_1097) @[Bitwise.scala 103:75] + node _T_1099 = or(_T_1094, _T_1098) @[Bitwise.scala 103:39] + node _T_1100 = bits(_T_1092, 5, 0) @[Bitwise.scala 102:28] + node _T_1101 = shl(_T_1100, 2) @[Bitwise.scala 102:47] + node _T_1102 = xor(_T_1092, _T_1101) @[Bitwise.scala 102:21] + node _T_1103 = shr(_T_1099, 2) @[Bitwise.scala 103:21] + node _T_1104 = and(_T_1103, _T_1102) @[Bitwise.scala 103:31] + node _T_1105 = bits(_T_1099, 5, 0) @[Bitwise.scala 103:46] + node _T_1106 = shl(_T_1105, 2) @[Bitwise.scala 103:65] + node _T_1107 = not(_T_1102) @[Bitwise.scala 103:77] + node _T_1108 = and(_T_1106, _T_1107) @[Bitwise.scala 103:75] + node _T_1109 = or(_T_1104, _T_1108) @[Bitwise.scala 103:39] + node _T_1110 = bits(_T_1102, 6, 0) @[Bitwise.scala 102:28] + node _T_1111 = shl(_T_1110, 1) @[Bitwise.scala 102:47] + node _T_1112 = xor(_T_1102, _T_1111) @[Bitwise.scala 102:21] + node _T_1113 = shr(_T_1109, 1) @[Bitwise.scala 103:21] + node _T_1114 = and(_T_1113, _T_1112) @[Bitwise.scala 103:31] + node _T_1115 = bits(_T_1109, 6, 0) @[Bitwise.scala 103:46] + node _T_1116 = shl(_T_1115, 1) @[Bitwise.scala 103:65] + node _T_1117 = not(_T_1112) @[Bitwise.scala 103:77] + node _T_1118 = and(_T_1116, _T_1117) @[Bitwise.scala 103:75] + node _T_1119 = or(_T_1114, _T_1118) @[Bitwise.scala 103:39] + wire _T_1120 : UInt<8>[4] @[lsu_dccm_ctl.scala 259:104] + _T_1120[0] <= _T_1005 @[lsu_dccm_ctl.scala 259:104] + _T_1120[1] <= _T_1043 @[lsu_dccm_ctl.scala 259:104] + _T_1120[2] <= _T_1081 @[lsu_dccm_ctl.scala 259:104] + _T_1120[3] <= _T_1119 @[lsu_dccm_ctl.scala 259:104] + node _T_1121 = cat(_T_1120[2], _T_1120[3]) @[Cat.scala 29:58] + node _T_1122 = cat(_T_1120[0], _T_1120[1]) @[Cat.scala 29:58] + node _T_1123 = cat(_T_1122, _T_1121) @[Cat.scala 29:58] + node _T_1124 = shl(UInt<16>("h0ffff"), 16) @[Bitwise.scala 102:47] + node _T_1125 = xor(UInt<32>("h0ffffffff"), _T_1124) @[Bitwise.scala 102:21] + node _T_1126 = shr(_T_1123, 16) @[Bitwise.scala 103:21] + node _T_1127 = and(_T_1126, _T_1125) @[Bitwise.scala 103:31] + node _T_1128 = bits(_T_1123, 15, 0) @[Bitwise.scala 103:46] + node _T_1129 = shl(_T_1128, 16) @[Bitwise.scala 103:65] + node _T_1130 = not(_T_1125) @[Bitwise.scala 103:77] + node _T_1131 = and(_T_1129, _T_1130) @[Bitwise.scala 103:75] + node _T_1132 = or(_T_1127, _T_1131) @[Bitwise.scala 103:39] + node _T_1133 = bits(_T_1125, 23, 0) @[Bitwise.scala 102:28] + node _T_1134 = shl(_T_1133, 8) @[Bitwise.scala 102:47] + node _T_1135 = xor(_T_1125, _T_1134) @[Bitwise.scala 102:21] + node _T_1136 = shr(_T_1132, 8) @[Bitwise.scala 103:21] + node _T_1137 = and(_T_1136, _T_1135) @[Bitwise.scala 103:31] + node _T_1138 = bits(_T_1132, 23, 0) @[Bitwise.scala 103:46] + node _T_1139 = shl(_T_1138, 8) @[Bitwise.scala 103:65] + node _T_1140 = not(_T_1135) @[Bitwise.scala 103:77] + node _T_1141 = and(_T_1139, _T_1140) @[Bitwise.scala 103:75] + node _T_1142 = or(_T_1137, _T_1141) @[Bitwise.scala 103:39] + node _T_1143 = bits(_T_1135, 27, 0) @[Bitwise.scala 102:28] + node _T_1144 = shl(_T_1143, 4) @[Bitwise.scala 102:47] + node _T_1145 = xor(_T_1135, _T_1144) @[Bitwise.scala 102:21] + node _T_1146 = shr(_T_1142, 4) @[Bitwise.scala 103:21] + node _T_1147 = and(_T_1146, _T_1145) @[Bitwise.scala 103:31] + node _T_1148 = bits(_T_1142, 27, 0) @[Bitwise.scala 103:46] + node _T_1149 = shl(_T_1148, 4) @[Bitwise.scala 103:65] + node _T_1150 = not(_T_1145) @[Bitwise.scala 103:77] + node _T_1151 = and(_T_1149, _T_1150) @[Bitwise.scala 103:75] + node _T_1152 = or(_T_1147, _T_1151) @[Bitwise.scala 103:39] + node _T_1153 = bits(_T_1145, 29, 0) @[Bitwise.scala 102:28] + node _T_1154 = shl(_T_1153, 2) @[Bitwise.scala 102:47] + node _T_1155 = xor(_T_1145, _T_1154) @[Bitwise.scala 102:21] + node _T_1156 = shr(_T_1152, 2) @[Bitwise.scala 103:21] + node _T_1157 = and(_T_1156, _T_1155) @[Bitwise.scala 103:31] + node _T_1158 = bits(_T_1152, 29, 0) @[Bitwise.scala 103:46] + node _T_1159 = shl(_T_1158, 2) @[Bitwise.scala 103:65] + node _T_1160 = not(_T_1155) @[Bitwise.scala 103:77] + node _T_1161 = and(_T_1159, _T_1160) @[Bitwise.scala 103:75] + node _T_1162 = or(_T_1157, _T_1161) @[Bitwise.scala 103:39] + node _T_1163 = bits(_T_1155, 30, 0) @[Bitwise.scala 102:28] + node _T_1164 = shl(_T_1163, 1) @[Bitwise.scala 102:47] + node _T_1165 = xor(_T_1155, _T_1164) @[Bitwise.scala 102:21] + node _T_1166 = shr(_T_1162, 1) @[Bitwise.scala 103:21] + node _T_1167 = and(_T_1166, _T_1165) @[Bitwise.scala 103:31] + node _T_1168 = bits(_T_1162, 30, 0) @[Bitwise.scala 103:46] + node _T_1169 = shl(_T_1168, 1) @[Bitwise.scala 103:65] + node _T_1170 = not(_T_1165) @[Bitwise.scala 103:77] + node _T_1171 = and(_T_1169, _T_1170) @[Bitwise.scala 103:75] + node _T_1172 = or(_T_1167, _T_1171) @[Bitwise.scala 103:39] + reg _T_1173 : UInt, io.lsu_store_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_dccm_ctl.scala 259:72] + _T_1173 <= _T_1172 @[lsu_dccm_ctl.scala 259:72] + io.store_data_lo_r <= _T_1173 @[lsu_dccm_ctl.scala 259:29] + node _T_1174 = bits(store_byteen_ext_m, 4, 4) @[lsu_dccm_ctl.scala 260:139] + node _T_1175 = bits(_T_1174, 0, 0) @[lsu_dccm_ctl.scala 260:145] + node _T_1176 = bits(store_data_hi_m, 7, 0) @[lsu_dccm_ctl.scala 260:167] + node _T_1177 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_hi) @[lsu_dccm_ctl.scala 260:211] + node _T_1178 = bits(_T_1177, 0, 0) @[lsu_dccm_ctl.scala 260:237] + node _T_1179 = bits(io.stbuf_data_any, 7, 0) @[lsu_dccm_ctl.scala 260:262] + node _T_1180 = bits(io.sec_data_hi_m, 7, 0) @[lsu_dccm_ctl.scala 260:292] + node _T_1181 = mux(_T_1178, _T_1179, _T_1180) @[lsu_dccm_ctl.scala 260:185] + node _T_1182 = mux(_T_1175, _T_1176, _T_1181) @[lsu_dccm_ctl.scala 260:120] + node _T_1183 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1184 = xor(UInt<8>("h0ff"), _T_1183) @[Bitwise.scala 102:21] + node _T_1185 = shr(_T_1182, 4) @[Bitwise.scala 103:21] + node _T_1186 = and(_T_1185, _T_1184) @[Bitwise.scala 103:31] + node _T_1187 = bits(_T_1182, 3, 0) @[Bitwise.scala 103:46] + node _T_1188 = shl(_T_1187, 4) @[Bitwise.scala 103:65] + node _T_1189 = not(_T_1184) @[Bitwise.scala 103:77] + node _T_1190 = and(_T_1188, _T_1189) @[Bitwise.scala 103:75] + node _T_1191 = or(_T_1186, _T_1190) @[Bitwise.scala 103:39] + node _T_1192 = bits(_T_1184, 5, 0) @[Bitwise.scala 102:28] + node _T_1193 = shl(_T_1192, 2) @[Bitwise.scala 102:47] + node _T_1194 = xor(_T_1184, _T_1193) @[Bitwise.scala 102:21] + node _T_1195 = shr(_T_1191, 2) @[Bitwise.scala 103:21] + node _T_1196 = and(_T_1195, _T_1194) @[Bitwise.scala 103:31] + node _T_1197 = bits(_T_1191, 5, 0) @[Bitwise.scala 103:46] + node _T_1198 = shl(_T_1197, 2) @[Bitwise.scala 103:65] + node _T_1199 = not(_T_1194) @[Bitwise.scala 103:77] + node _T_1200 = and(_T_1198, _T_1199) @[Bitwise.scala 103:75] + node _T_1201 = or(_T_1196, _T_1200) @[Bitwise.scala 103:39] + node _T_1202 = bits(_T_1194, 6, 0) @[Bitwise.scala 102:28] + node _T_1203 = shl(_T_1202, 1) @[Bitwise.scala 102:47] + node _T_1204 = xor(_T_1194, _T_1203) @[Bitwise.scala 102:21] + node _T_1205 = shr(_T_1201, 1) @[Bitwise.scala 103:21] + node _T_1206 = and(_T_1205, _T_1204) @[Bitwise.scala 103:31] + node _T_1207 = bits(_T_1201, 6, 0) @[Bitwise.scala 103:46] + node _T_1208 = shl(_T_1207, 1) @[Bitwise.scala 103:65] + node _T_1209 = not(_T_1204) @[Bitwise.scala 103:77] + node _T_1210 = and(_T_1208, _T_1209) @[Bitwise.scala 103:75] + node _T_1211 = or(_T_1206, _T_1210) @[Bitwise.scala 103:39] + node _T_1212 = bits(store_byteen_ext_m, 5, 5) @[lsu_dccm_ctl.scala 260:139] + node _T_1213 = bits(_T_1212, 0, 0) @[lsu_dccm_ctl.scala 260:145] + node _T_1214 = bits(store_data_hi_m, 15, 8) @[lsu_dccm_ctl.scala 260:167] + node _T_1215 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_hi) @[lsu_dccm_ctl.scala 260:211] + node _T_1216 = bits(_T_1215, 0, 0) @[lsu_dccm_ctl.scala 260:237] + node _T_1217 = bits(io.stbuf_data_any, 15, 8) @[lsu_dccm_ctl.scala 260:262] + node _T_1218 = bits(io.sec_data_hi_m, 15, 8) @[lsu_dccm_ctl.scala 260:292] + node _T_1219 = mux(_T_1216, _T_1217, _T_1218) @[lsu_dccm_ctl.scala 260:185] + node _T_1220 = mux(_T_1213, _T_1214, _T_1219) @[lsu_dccm_ctl.scala 260:120] + node _T_1221 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1222 = xor(UInt<8>("h0ff"), _T_1221) @[Bitwise.scala 102:21] + node _T_1223 = shr(_T_1220, 4) @[Bitwise.scala 103:21] + node _T_1224 = and(_T_1223, _T_1222) @[Bitwise.scala 103:31] + node _T_1225 = bits(_T_1220, 3, 0) @[Bitwise.scala 103:46] + node _T_1226 = shl(_T_1225, 4) @[Bitwise.scala 103:65] + node _T_1227 = not(_T_1222) @[Bitwise.scala 103:77] + node _T_1228 = and(_T_1226, _T_1227) @[Bitwise.scala 103:75] + node _T_1229 = or(_T_1224, _T_1228) @[Bitwise.scala 103:39] + node _T_1230 = bits(_T_1222, 5, 0) @[Bitwise.scala 102:28] + node _T_1231 = shl(_T_1230, 2) @[Bitwise.scala 102:47] + node _T_1232 = xor(_T_1222, _T_1231) @[Bitwise.scala 102:21] + node _T_1233 = shr(_T_1229, 2) @[Bitwise.scala 103:21] + node _T_1234 = and(_T_1233, _T_1232) @[Bitwise.scala 103:31] + node _T_1235 = bits(_T_1229, 5, 0) @[Bitwise.scala 103:46] + node _T_1236 = shl(_T_1235, 2) @[Bitwise.scala 103:65] + node _T_1237 = not(_T_1232) @[Bitwise.scala 103:77] + node _T_1238 = and(_T_1236, _T_1237) @[Bitwise.scala 103:75] + node _T_1239 = or(_T_1234, _T_1238) @[Bitwise.scala 103:39] + node _T_1240 = bits(_T_1232, 6, 0) @[Bitwise.scala 102:28] + node _T_1241 = shl(_T_1240, 1) @[Bitwise.scala 102:47] + node _T_1242 = xor(_T_1232, _T_1241) @[Bitwise.scala 102:21] + node _T_1243 = shr(_T_1239, 1) @[Bitwise.scala 103:21] + node _T_1244 = and(_T_1243, _T_1242) @[Bitwise.scala 103:31] + node _T_1245 = bits(_T_1239, 6, 0) @[Bitwise.scala 103:46] + node _T_1246 = shl(_T_1245, 1) @[Bitwise.scala 103:65] + node _T_1247 = not(_T_1242) @[Bitwise.scala 103:77] + node _T_1248 = and(_T_1246, _T_1247) @[Bitwise.scala 103:75] + node _T_1249 = or(_T_1244, _T_1248) @[Bitwise.scala 103:39] + node _T_1250 = bits(store_byteen_ext_m, 6, 6) @[lsu_dccm_ctl.scala 260:139] + node _T_1251 = bits(_T_1250, 0, 0) @[lsu_dccm_ctl.scala 260:145] + node _T_1252 = bits(store_data_hi_m, 23, 16) @[lsu_dccm_ctl.scala 260:167] + node _T_1253 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_hi) @[lsu_dccm_ctl.scala 260:211] + node _T_1254 = bits(_T_1253, 0, 0) @[lsu_dccm_ctl.scala 260:237] + node _T_1255 = bits(io.stbuf_data_any, 23, 16) @[lsu_dccm_ctl.scala 260:262] + node _T_1256 = bits(io.sec_data_hi_m, 23, 16) @[lsu_dccm_ctl.scala 260:292] + node _T_1257 = mux(_T_1254, _T_1255, _T_1256) @[lsu_dccm_ctl.scala 260:185] + node _T_1258 = mux(_T_1251, _T_1252, _T_1257) @[lsu_dccm_ctl.scala 260:120] + node _T_1259 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1260 = xor(UInt<8>("h0ff"), _T_1259) @[Bitwise.scala 102:21] + node _T_1261 = shr(_T_1258, 4) @[Bitwise.scala 103:21] + node _T_1262 = and(_T_1261, _T_1260) @[Bitwise.scala 103:31] + node _T_1263 = bits(_T_1258, 3, 0) @[Bitwise.scala 103:46] + node _T_1264 = shl(_T_1263, 4) @[Bitwise.scala 103:65] + node _T_1265 = not(_T_1260) @[Bitwise.scala 103:77] + node _T_1266 = and(_T_1264, _T_1265) @[Bitwise.scala 103:75] + node _T_1267 = or(_T_1262, _T_1266) @[Bitwise.scala 103:39] + node _T_1268 = bits(_T_1260, 5, 0) @[Bitwise.scala 102:28] + node _T_1269 = shl(_T_1268, 2) @[Bitwise.scala 102:47] + node _T_1270 = xor(_T_1260, _T_1269) @[Bitwise.scala 102:21] + node _T_1271 = shr(_T_1267, 2) @[Bitwise.scala 103:21] + node _T_1272 = and(_T_1271, _T_1270) @[Bitwise.scala 103:31] + node _T_1273 = bits(_T_1267, 5, 0) @[Bitwise.scala 103:46] + node _T_1274 = shl(_T_1273, 2) @[Bitwise.scala 103:65] + node _T_1275 = not(_T_1270) @[Bitwise.scala 103:77] + node _T_1276 = and(_T_1274, _T_1275) @[Bitwise.scala 103:75] + node _T_1277 = or(_T_1272, _T_1276) @[Bitwise.scala 103:39] + node _T_1278 = bits(_T_1270, 6, 0) @[Bitwise.scala 102:28] + node _T_1279 = shl(_T_1278, 1) @[Bitwise.scala 102:47] + node _T_1280 = xor(_T_1270, _T_1279) @[Bitwise.scala 102:21] + node _T_1281 = shr(_T_1277, 1) @[Bitwise.scala 103:21] + node _T_1282 = and(_T_1281, _T_1280) @[Bitwise.scala 103:31] + node _T_1283 = bits(_T_1277, 6, 0) @[Bitwise.scala 103:46] + node _T_1284 = shl(_T_1283, 1) @[Bitwise.scala 103:65] + node _T_1285 = not(_T_1280) @[Bitwise.scala 103:77] + node _T_1286 = and(_T_1284, _T_1285) @[Bitwise.scala 103:75] + node _T_1287 = or(_T_1282, _T_1286) @[Bitwise.scala 103:39] + node _T_1288 = bits(store_byteen_ext_m, 7, 7) @[lsu_dccm_ctl.scala 260:139] + node _T_1289 = bits(_T_1288, 0, 0) @[lsu_dccm_ctl.scala 260:145] + node _T_1290 = bits(store_data_hi_m, 31, 24) @[lsu_dccm_ctl.scala 260:167] + node _T_1291 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_hi) @[lsu_dccm_ctl.scala 260:211] + node _T_1292 = bits(_T_1291, 0, 0) @[lsu_dccm_ctl.scala 260:237] + node _T_1293 = bits(io.stbuf_data_any, 31, 24) @[lsu_dccm_ctl.scala 260:262] + node _T_1294 = bits(io.sec_data_hi_m, 31, 24) @[lsu_dccm_ctl.scala 260:292] + node _T_1295 = mux(_T_1292, _T_1293, _T_1294) @[lsu_dccm_ctl.scala 260:185] + node _T_1296 = mux(_T_1289, _T_1290, _T_1295) @[lsu_dccm_ctl.scala 260:120] + node _T_1297 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1298 = xor(UInt<8>("h0ff"), _T_1297) @[Bitwise.scala 102:21] + node _T_1299 = shr(_T_1296, 4) @[Bitwise.scala 103:21] + node _T_1300 = and(_T_1299, _T_1298) @[Bitwise.scala 103:31] + node _T_1301 = bits(_T_1296, 3, 0) @[Bitwise.scala 103:46] + node _T_1302 = shl(_T_1301, 4) @[Bitwise.scala 103:65] + node _T_1303 = not(_T_1298) @[Bitwise.scala 103:77] + node _T_1304 = and(_T_1302, _T_1303) @[Bitwise.scala 103:75] + node _T_1305 = or(_T_1300, _T_1304) @[Bitwise.scala 103:39] + node _T_1306 = bits(_T_1298, 5, 0) @[Bitwise.scala 102:28] + node _T_1307 = shl(_T_1306, 2) @[Bitwise.scala 102:47] + node _T_1308 = xor(_T_1298, _T_1307) @[Bitwise.scala 102:21] + node _T_1309 = shr(_T_1305, 2) @[Bitwise.scala 103:21] + node _T_1310 = and(_T_1309, _T_1308) @[Bitwise.scala 103:31] + node _T_1311 = bits(_T_1305, 5, 0) @[Bitwise.scala 103:46] + node _T_1312 = shl(_T_1311, 2) @[Bitwise.scala 103:65] + node _T_1313 = not(_T_1308) @[Bitwise.scala 103:77] + node _T_1314 = and(_T_1312, _T_1313) @[Bitwise.scala 103:75] + node _T_1315 = or(_T_1310, _T_1314) @[Bitwise.scala 103:39] + node _T_1316 = bits(_T_1308, 6, 0) @[Bitwise.scala 102:28] + node _T_1317 = shl(_T_1316, 1) @[Bitwise.scala 102:47] + node _T_1318 = xor(_T_1308, _T_1317) @[Bitwise.scala 102:21] + node _T_1319 = shr(_T_1315, 1) @[Bitwise.scala 103:21] + node _T_1320 = and(_T_1319, _T_1318) @[Bitwise.scala 103:31] + node _T_1321 = bits(_T_1315, 6, 0) @[Bitwise.scala 103:46] + node _T_1322 = shl(_T_1321, 1) @[Bitwise.scala 103:65] + node _T_1323 = not(_T_1318) @[Bitwise.scala 103:77] + node _T_1324 = and(_T_1322, _T_1323) @[Bitwise.scala 103:75] + node _T_1325 = or(_T_1320, _T_1324) @[Bitwise.scala 103:39] + wire _T_1326 : UInt<8>[4] @[lsu_dccm_ctl.scala 260:104] + _T_1326[0] <= _T_1211 @[lsu_dccm_ctl.scala 260:104] + _T_1326[1] <= _T_1249 @[lsu_dccm_ctl.scala 260:104] + _T_1326[2] <= _T_1287 @[lsu_dccm_ctl.scala 260:104] + _T_1326[3] <= _T_1325 @[lsu_dccm_ctl.scala 260:104] + node _T_1327 = cat(_T_1326[2], _T_1326[3]) @[Cat.scala 29:58] + node _T_1328 = cat(_T_1326[0], _T_1326[1]) @[Cat.scala 29:58] + node _T_1329 = cat(_T_1328, _T_1327) @[Cat.scala 29:58] + node _T_1330 = shl(UInt<16>("h0ffff"), 16) @[Bitwise.scala 102:47] + node _T_1331 = xor(UInt<32>("h0ffffffff"), _T_1330) @[Bitwise.scala 102:21] + node _T_1332 = shr(_T_1329, 16) @[Bitwise.scala 103:21] + node _T_1333 = and(_T_1332, _T_1331) @[Bitwise.scala 103:31] + node _T_1334 = bits(_T_1329, 15, 0) @[Bitwise.scala 103:46] + node _T_1335 = shl(_T_1334, 16) @[Bitwise.scala 103:65] + node _T_1336 = not(_T_1331) @[Bitwise.scala 103:77] + node _T_1337 = and(_T_1335, _T_1336) @[Bitwise.scala 103:75] + node _T_1338 = or(_T_1333, _T_1337) @[Bitwise.scala 103:39] + node _T_1339 = bits(_T_1331, 23, 0) @[Bitwise.scala 102:28] + node _T_1340 = shl(_T_1339, 8) @[Bitwise.scala 102:47] + node _T_1341 = xor(_T_1331, _T_1340) @[Bitwise.scala 102:21] + node _T_1342 = shr(_T_1338, 8) @[Bitwise.scala 103:21] + node _T_1343 = and(_T_1342, _T_1341) @[Bitwise.scala 103:31] + node _T_1344 = bits(_T_1338, 23, 0) @[Bitwise.scala 103:46] + node _T_1345 = shl(_T_1344, 8) @[Bitwise.scala 103:65] + node _T_1346 = not(_T_1341) @[Bitwise.scala 103:77] + node _T_1347 = and(_T_1345, _T_1346) @[Bitwise.scala 103:75] + node _T_1348 = or(_T_1343, _T_1347) @[Bitwise.scala 103:39] + node _T_1349 = bits(_T_1341, 27, 0) @[Bitwise.scala 102:28] + node _T_1350 = shl(_T_1349, 4) @[Bitwise.scala 102:47] + node _T_1351 = xor(_T_1341, _T_1350) @[Bitwise.scala 102:21] + node _T_1352 = shr(_T_1348, 4) @[Bitwise.scala 103:21] + node _T_1353 = and(_T_1352, _T_1351) @[Bitwise.scala 103:31] + node _T_1354 = bits(_T_1348, 27, 0) @[Bitwise.scala 103:46] + node _T_1355 = shl(_T_1354, 4) @[Bitwise.scala 103:65] + node _T_1356 = not(_T_1351) @[Bitwise.scala 103:77] + node _T_1357 = and(_T_1355, _T_1356) @[Bitwise.scala 103:75] + node _T_1358 = or(_T_1353, _T_1357) @[Bitwise.scala 103:39] + node _T_1359 = bits(_T_1351, 29, 0) @[Bitwise.scala 102:28] + node _T_1360 = shl(_T_1359, 2) @[Bitwise.scala 102:47] + node _T_1361 = xor(_T_1351, _T_1360) @[Bitwise.scala 102:21] + node _T_1362 = shr(_T_1358, 2) @[Bitwise.scala 103:21] + node _T_1363 = and(_T_1362, _T_1361) @[Bitwise.scala 103:31] + node _T_1364 = bits(_T_1358, 29, 0) @[Bitwise.scala 103:46] + node _T_1365 = shl(_T_1364, 2) @[Bitwise.scala 103:65] + node _T_1366 = not(_T_1361) @[Bitwise.scala 103:77] + node _T_1367 = and(_T_1365, _T_1366) @[Bitwise.scala 103:75] + node _T_1368 = or(_T_1363, _T_1367) @[Bitwise.scala 103:39] + node _T_1369 = bits(_T_1361, 30, 0) @[Bitwise.scala 102:28] + node _T_1370 = shl(_T_1369, 1) @[Bitwise.scala 102:47] + node _T_1371 = xor(_T_1361, _T_1370) @[Bitwise.scala 102:21] + node _T_1372 = shr(_T_1368, 1) @[Bitwise.scala 103:21] + node _T_1373 = and(_T_1372, _T_1371) @[Bitwise.scala 103:31] + node _T_1374 = bits(_T_1368, 30, 0) @[Bitwise.scala 103:46] + node _T_1375 = shl(_T_1374, 1) @[Bitwise.scala 103:65] + node _T_1376 = not(_T_1371) @[Bitwise.scala 103:77] + node _T_1377 = and(_T_1375, _T_1376) @[Bitwise.scala 103:75] + node _T_1378 = or(_T_1373, _T_1377) @[Bitwise.scala 103:39] + reg _T_1379 : UInt, io.lsu_store_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_dccm_ctl.scala 260:72] + _T_1379 <= _T_1378 @[lsu_dccm_ctl.scala 260:72] + io.store_data_hi_r <= _T_1379 @[lsu_dccm_ctl.scala 260:29] + node _T_1380 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[lsu_dccm_ctl.scala 261:105] + node _T_1381 = bits(store_byteen_ext_r, 0, 0) @[lsu_dccm_ctl.scala 261:150] + node _T_1382 = eq(_T_1381, UInt<1>("h00")) @[lsu_dccm_ctl.scala 261:131] + node _T_1383 = and(_T_1380, _T_1382) @[lsu_dccm_ctl.scala 261:129] + node _T_1384 = bits(_T_1383, 0, 0) @[lsu_dccm_ctl.scala 261:155] + node _T_1385 = bits(io.stbuf_data_any, 7, 0) @[lsu_dccm_ctl.scala 261:179] + node _T_1386 = bits(io.store_data_lo_r, 7, 0) @[lsu_dccm_ctl.scala 261:211] + node _T_1387 = mux(_T_1384, _T_1385, _T_1386) @[lsu_dccm_ctl.scala 261:79] + node _T_1388 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1389 = xor(UInt<8>("h0ff"), _T_1388) @[Bitwise.scala 102:21] + node _T_1390 = shr(_T_1387, 4) @[Bitwise.scala 103:21] + node _T_1391 = and(_T_1390, _T_1389) @[Bitwise.scala 103:31] + node _T_1392 = bits(_T_1387, 3, 0) @[Bitwise.scala 103:46] + node _T_1393 = shl(_T_1392, 4) @[Bitwise.scala 103:65] + node _T_1394 = not(_T_1389) @[Bitwise.scala 103:77] + node _T_1395 = and(_T_1393, _T_1394) @[Bitwise.scala 103:75] + node _T_1396 = or(_T_1391, _T_1395) @[Bitwise.scala 103:39] + node _T_1397 = bits(_T_1389, 5, 0) @[Bitwise.scala 102:28] + node _T_1398 = shl(_T_1397, 2) @[Bitwise.scala 102:47] + node _T_1399 = xor(_T_1389, _T_1398) @[Bitwise.scala 102:21] + node _T_1400 = shr(_T_1396, 2) @[Bitwise.scala 103:21] + node _T_1401 = and(_T_1400, _T_1399) @[Bitwise.scala 103:31] + node _T_1402 = bits(_T_1396, 5, 0) @[Bitwise.scala 103:46] + node _T_1403 = shl(_T_1402, 2) @[Bitwise.scala 103:65] + node _T_1404 = not(_T_1399) @[Bitwise.scala 103:77] + node _T_1405 = and(_T_1403, _T_1404) @[Bitwise.scala 103:75] + node _T_1406 = or(_T_1401, _T_1405) @[Bitwise.scala 103:39] + node _T_1407 = bits(_T_1399, 6, 0) @[Bitwise.scala 102:28] + node _T_1408 = shl(_T_1407, 1) @[Bitwise.scala 102:47] + node _T_1409 = xor(_T_1399, _T_1408) @[Bitwise.scala 102:21] + node _T_1410 = shr(_T_1406, 1) @[Bitwise.scala 103:21] + node _T_1411 = and(_T_1410, _T_1409) @[Bitwise.scala 103:31] + node _T_1412 = bits(_T_1406, 6, 0) @[Bitwise.scala 103:46] + node _T_1413 = shl(_T_1412, 1) @[Bitwise.scala 103:65] + node _T_1414 = not(_T_1409) @[Bitwise.scala 103:77] + node _T_1415 = and(_T_1413, _T_1414) @[Bitwise.scala 103:75] + node _T_1416 = or(_T_1411, _T_1415) @[Bitwise.scala 103:39] + node _T_1417 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[lsu_dccm_ctl.scala 261:105] + node _T_1418 = bits(store_byteen_ext_r, 1, 1) @[lsu_dccm_ctl.scala 261:150] + node _T_1419 = eq(_T_1418, UInt<1>("h00")) @[lsu_dccm_ctl.scala 261:131] + node _T_1420 = and(_T_1417, _T_1419) @[lsu_dccm_ctl.scala 261:129] + node _T_1421 = bits(_T_1420, 0, 0) @[lsu_dccm_ctl.scala 261:155] + node _T_1422 = bits(io.stbuf_data_any, 15, 8) @[lsu_dccm_ctl.scala 261:179] + node _T_1423 = bits(io.store_data_lo_r, 15, 8) @[lsu_dccm_ctl.scala 261:211] + node _T_1424 = mux(_T_1421, _T_1422, _T_1423) @[lsu_dccm_ctl.scala 261:79] + node _T_1425 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1426 = xor(UInt<8>("h0ff"), _T_1425) @[Bitwise.scala 102:21] + node _T_1427 = shr(_T_1424, 4) @[Bitwise.scala 103:21] + node _T_1428 = and(_T_1427, _T_1426) @[Bitwise.scala 103:31] + node _T_1429 = bits(_T_1424, 3, 0) @[Bitwise.scala 103:46] + node _T_1430 = shl(_T_1429, 4) @[Bitwise.scala 103:65] + node _T_1431 = not(_T_1426) @[Bitwise.scala 103:77] + node _T_1432 = and(_T_1430, _T_1431) @[Bitwise.scala 103:75] + node _T_1433 = or(_T_1428, _T_1432) @[Bitwise.scala 103:39] + node _T_1434 = bits(_T_1426, 5, 0) @[Bitwise.scala 102:28] + node _T_1435 = shl(_T_1434, 2) @[Bitwise.scala 102:47] + node _T_1436 = xor(_T_1426, _T_1435) @[Bitwise.scala 102:21] + node _T_1437 = shr(_T_1433, 2) @[Bitwise.scala 103:21] + node _T_1438 = and(_T_1437, _T_1436) @[Bitwise.scala 103:31] + node _T_1439 = bits(_T_1433, 5, 0) @[Bitwise.scala 103:46] + node _T_1440 = shl(_T_1439, 2) @[Bitwise.scala 103:65] + node _T_1441 = not(_T_1436) @[Bitwise.scala 103:77] + node _T_1442 = and(_T_1440, _T_1441) @[Bitwise.scala 103:75] + node _T_1443 = or(_T_1438, _T_1442) @[Bitwise.scala 103:39] + node _T_1444 = bits(_T_1436, 6, 0) @[Bitwise.scala 102:28] + node _T_1445 = shl(_T_1444, 1) @[Bitwise.scala 102:47] + node _T_1446 = xor(_T_1436, _T_1445) @[Bitwise.scala 102:21] + node _T_1447 = shr(_T_1443, 1) @[Bitwise.scala 103:21] + node _T_1448 = and(_T_1447, _T_1446) @[Bitwise.scala 103:31] + node _T_1449 = bits(_T_1443, 6, 0) @[Bitwise.scala 103:46] + node _T_1450 = shl(_T_1449, 1) @[Bitwise.scala 103:65] + node _T_1451 = not(_T_1446) @[Bitwise.scala 103:77] + node _T_1452 = and(_T_1450, _T_1451) @[Bitwise.scala 103:75] + node _T_1453 = or(_T_1448, _T_1452) @[Bitwise.scala 103:39] + node _T_1454 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[lsu_dccm_ctl.scala 261:105] + node _T_1455 = bits(store_byteen_ext_r, 2, 2) @[lsu_dccm_ctl.scala 261:150] + node _T_1456 = eq(_T_1455, UInt<1>("h00")) @[lsu_dccm_ctl.scala 261:131] + node _T_1457 = and(_T_1454, _T_1456) @[lsu_dccm_ctl.scala 261:129] + node _T_1458 = bits(_T_1457, 0, 0) @[lsu_dccm_ctl.scala 261:155] + node _T_1459 = bits(io.stbuf_data_any, 23, 16) @[lsu_dccm_ctl.scala 261:179] + node _T_1460 = bits(io.store_data_lo_r, 23, 16) @[lsu_dccm_ctl.scala 261:211] + node _T_1461 = mux(_T_1458, _T_1459, _T_1460) @[lsu_dccm_ctl.scala 261:79] + node _T_1462 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1463 = xor(UInt<8>("h0ff"), _T_1462) @[Bitwise.scala 102:21] + node _T_1464 = shr(_T_1461, 4) @[Bitwise.scala 103:21] + node _T_1465 = and(_T_1464, _T_1463) @[Bitwise.scala 103:31] + node _T_1466 = bits(_T_1461, 3, 0) @[Bitwise.scala 103:46] + node _T_1467 = shl(_T_1466, 4) @[Bitwise.scala 103:65] + node _T_1468 = not(_T_1463) @[Bitwise.scala 103:77] + node _T_1469 = and(_T_1467, _T_1468) @[Bitwise.scala 103:75] + node _T_1470 = or(_T_1465, _T_1469) @[Bitwise.scala 103:39] + node _T_1471 = bits(_T_1463, 5, 0) @[Bitwise.scala 102:28] + node _T_1472 = shl(_T_1471, 2) @[Bitwise.scala 102:47] + node _T_1473 = xor(_T_1463, _T_1472) @[Bitwise.scala 102:21] + node _T_1474 = shr(_T_1470, 2) @[Bitwise.scala 103:21] + node _T_1475 = and(_T_1474, _T_1473) @[Bitwise.scala 103:31] + node _T_1476 = bits(_T_1470, 5, 0) @[Bitwise.scala 103:46] + node _T_1477 = shl(_T_1476, 2) @[Bitwise.scala 103:65] + node _T_1478 = not(_T_1473) @[Bitwise.scala 103:77] + node _T_1479 = and(_T_1477, _T_1478) @[Bitwise.scala 103:75] + node _T_1480 = or(_T_1475, _T_1479) @[Bitwise.scala 103:39] + node _T_1481 = bits(_T_1473, 6, 0) @[Bitwise.scala 102:28] + node _T_1482 = shl(_T_1481, 1) @[Bitwise.scala 102:47] + node _T_1483 = xor(_T_1473, _T_1482) @[Bitwise.scala 102:21] + node _T_1484 = shr(_T_1480, 1) @[Bitwise.scala 103:21] + node _T_1485 = and(_T_1484, _T_1483) @[Bitwise.scala 103:31] + node _T_1486 = bits(_T_1480, 6, 0) @[Bitwise.scala 103:46] + node _T_1487 = shl(_T_1486, 1) @[Bitwise.scala 103:65] + node _T_1488 = not(_T_1483) @[Bitwise.scala 103:77] + node _T_1489 = and(_T_1487, _T_1488) @[Bitwise.scala 103:75] + node _T_1490 = or(_T_1485, _T_1489) @[Bitwise.scala 103:39] + node _T_1491 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[lsu_dccm_ctl.scala 261:105] + node _T_1492 = bits(store_byteen_ext_r, 3, 3) @[lsu_dccm_ctl.scala 261:150] + node _T_1493 = eq(_T_1492, UInt<1>("h00")) @[lsu_dccm_ctl.scala 261:131] + node _T_1494 = and(_T_1491, _T_1493) @[lsu_dccm_ctl.scala 261:129] + node _T_1495 = bits(_T_1494, 0, 0) @[lsu_dccm_ctl.scala 261:155] + node _T_1496 = bits(io.stbuf_data_any, 31, 24) @[lsu_dccm_ctl.scala 261:179] + node _T_1497 = bits(io.store_data_lo_r, 31, 24) @[lsu_dccm_ctl.scala 261:211] + node _T_1498 = mux(_T_1495, _T_1496, _T_1497) @[lsu_dccm_ctl.scala 261:79] + node _T_1499 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1500 = xor(UInt<8>("h0ff"), _T_1499) @[Bitwise.scala 102:21] + node _T_1501 = shr(_T_1498, 4) @[Bitwise.scala 103:21] + node _T_1502 = and(_T_1501, _T_1500) @[Bitwise.scala 103:31] + node _T_1503 = bits(_T_1498, 3, 0) @[Bitwise.scala 103:46] + node _T_1504 = shl(_T_1503, 4) @[Bitwise.scala 103:65] + node _T_1505 = not(_T_1500) @[Bitwise.scala 103:77] + node _T_1506 = and(_T_1504, _T_1505) @[Bitwise.scala 103:75] + node _T_1507 = or(_T_1502, _T_1506) @[Bitwise.scala 103:39] + node _T_1508 = bits(_T_1500, 5, 0) @[Bitwise.scala 102:28] + node _T_1509 = shl(_T_1508, 2) @[Bitwise.scala 102:47] + node _T_1510 = xor(_T_1500, _T_1509) @[Bitwise.scala 102:21] + node _T_1511 = shr(_T_1507, 2) @[Bitwise.scala 103:21] + node _T_1512 = and(_T_1511, _T_1510) @[Bitwise.scala 103:31] + node _T_1513 = bits(_T_1507, 5, 0) @[Bitwise.scala 103:46] + node _T_1514 = shl(_T_1513, 2) @[Bitwise.scala 103:65] + node _T_1515 = not(_T_1510) @[Bitwise.scala 103:77] + node _T_1516 = and(_T_1514, _T_1515) @[Bitwise.scala 103:75] + node _T_1517 = or(_T_1512, _T_1516) @[Bitwise.scala 103:39] + node _T_1518 = bits(_T_1510, 6, 0) @[Bitwise.scala 102:28] + node _T_1519 = shl(_T_1518, 1) @[Bitwise.scala 102:47] + node _T_1520 = xor(_T_1510, _T_1519) @[Bitwise.scala 102:21] + node _T_1521 = shr(_T_1517, 1) @[Bitwise.scala 103:21] + node _T_1522 = and(_T_1521, _T_1520) @[Bitwise.scala 103:31] + node _T_1523 = bits(_T_1517, 6, 0) @[Bitwise.scala 103:46] + node _T_1524 = shl(_T_1523, 1) @[Bitwise.scala 103:65] + node _T_1525 = not(_T_1520) @[Bitwise.scala 103:77] + node _T_1526 = and(_T_1524, _T_1525) @[Bitwise.scala 103:75] + node _T_1527 = or(_T_1522, _T_1526) @[Bitwise.scala 103:39] + wire _T_1528 : UInt<8>[4] @[lsu_dccm_ctl.scala 261:63] + _T_1528[0] <= _T_1416 @[lsu_dccm_ctl.scala 261:63] + _T_1528[1] <= _T_1453 @[lsu_dccm_ctl.scala 261:63] + _T_1528[2] <= _T_1490 @[lsu_dccm_ctl.scala 261:63] + _T_1528[3] <= _T_1527 @[lsu_dccm_ctl.scala 261:63] + node _T_1529 = cat(_T_1528[2], _T_1528[3]) @[Cat.scala 29:58] + node _T_1530 = cat(_T_1528[0], _T_1528[1]) @[Cat.scala 29:58] + node _T_1531 = cat(_T_1530, _T_1529) @[Cat.scala 29:58] + node _T_1532 = shl(UInt<16>("h0ffff"), 16) @[Bitwise.scala 102:47] + node _T_1533 = xor(UInt<32>("h0ffffffff"), _T_1532) @[Bitwise.scala 102:21] + node _T_1534 = shr(_T_1531, 16) @[Bitwise.scala 103:21] + node _T_1535 = and(_T_1534, _T_1533) @[Bitwise.scala 103:31] + node _T_1536 = bits(_T_1531, 15, 0) @[Bitwise.scala 103:46] + node _T_1537 = shl(_T_1536, 16) @[Bitwise.scala 103:65] + node _T_1538 = not(_T_1533) @[Bitwise.scala 103:77] + node _T_1539 = and(_T_1537, _T_1538) @[Bitwise.scala 103:75] + node _T_1540 = or(_T_1535, _T_1539) @[Bitwise.scala 103:39] + node _T_1541 = bits(_T_1533, 23, 0) @[Bitwise.scala 102:28] + node _T_1542 = shl(_T_1541, 8) @[Bitwise.scala 102:47] + node _T_1543 = xor(_T_1533, _T_1542) @[Bitwise.scala 102:21] + node _T_1544 = shr(_T_1540, 8) @[Bitwise.scala 103:21] + node _T_1545 = and(_T_1544, _T_1543) @[Bitwise.scala 103:31] + node _T_1546 = bits(_T_1540, 23, 0) @[Bitwise.scala 103:46] + node _T_1547 = shl(_T_1546, 8) @[Bitwise.scala 103:65] + node _T_1548 = not(_T_1543) @[Bitwise.scala 103:77] + node _T_1549 = and(_T_1547, _T_1548) @[Bitwise.scala 103:75] + node _T_1550 = or(_T_1545, _T_1549) @[Bitwise.scala 103:39] + node _T_1551 = bits(_T_1543, 27, 0) @[Bitwise.scala 102:28] + node _T_1552 = shl(_T_1551, 4) @[Bitwise.scala 102:47] + node _T_1553 = xor(_T_1543, _T_1552) @[Bitwise.scala 102:21] + node _T_1554 = shr(_T_1550, 4) @[Bitwise.scala 103:21] + node _T_1555 = and(_T_1554, _T_1553) @[Bitwise.scala 103:31] + node _T_1556 = bits(_T_1550, 27, 0) @[Bitwise.scala 103:46] + node _T_1557 = shl(_T_1556, 4) @[Bitwise.scala 103:65] + node _T_1558 = not(_T_1553) @[Bitwise.scala 103:77] + node _T_1559 = and(_T_1557, _T_1558) @[Bitwise.scala 103:75] + node _T_1560 = or(_T_1555, _T_1559) @[Bitwise.scala 103:39] + node _T_1561 = bits(_T_1553, 29, 0) @[Bitwise.scala 102:28] + node _T_1562 = shl(_T_1561, 2) @[Bitwise.scala 102:47] + node _T_1563 = xor(_T_1553, _T_1562) @[Bitwise.scala 102:21] + node _T_1564 = shr(_T_1560, 2) @[Bitwise.scala 103:21] + node _T_1565 = and(_T_1564, _T_1563) @[Bitwise.scala 103:31] + node _T_1566 = bits(_T_1560, 29, 0) @[Bitwise.scala 103:46] + node _T_1567 = shl(_T_1566, 2) @[Bitwise.scala 103:65] + node _T_1568 = not(_T_1563) @[Bitwise.scala 103:77] + node _T_1569 = and(_T_1567, _T_1568) @[Bitwise.scala 103:75] + node _T_1570 = or(_T_1565, _T_1569) @[Bitwise.scala 103:39] + node _T_1571 = bits(_T_1563, 30, 0) @[Bitwise.scala 102:28] + node _T_1572 = shl(_T_1571, 1) @[Bitwise.scala 102:47] + node _T_1573 = xor(_T_1563, _T_1572) @[Bitwise.scala 102:21] + node _T_1574 = shr(_T_1570, 1) @[Bitwise.scala 103:21] + node _T_1575 = and(_T_1574, _T_1573) @[Bitwise.scala 103:31] + node _T_1576 = bits(_T_1570, 30, 0) @[Bitwise.scala 103:46] + node _T_1577 = shl(_T_1576, 1) @[Bitwise.scala 103:65] + node _T_1578 = not(_T_1573) @[Bitwise.scala 103:77] + node _T_1579 = and(_T_1577, _T_1578) @[Bitwise.scala 103:75] + node _T_1580 = or(_T_1575, _T_1579) @[Bitwise.scala 103:39] + io.store_datafn_lo_r <= _T_1580 @[lsu_dccm_ctl.scala 261:29] + node _T_1581 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_hi) @[lsu_dccm_ctl.scala 262:105] + node _T_1582 = bits(store_byteen_ext_r, 4, 4) @[lsu_dccm_ctl.scala 262:150] + node _T_1583 = eq(_T_1582, UInt<1>("h00")) @[lsu_dccm_ctl.scala 262:131] + node _T_1584 = and(_T_1581, _T_1583) @[lsu_dccm_ctl.scala 262:129] + node _T_1585 = bits(_T_1584, 0, 0) @[lsu_dccm_ctl.scala 262:157] + node _T_1586 = bits(io.stbuf_data_any, 7, 0) @[lsu_dccm_ctl.scala 262:181] + node _T_1587 = bits(io.store_data_hi_r, 7, 0) @[lsu_dccm_ctl.scala 262:213] + node _T_1588 = mux(_T_1585, _T_1586, _T_1587) @[lsu_dccm_ctl.scala 262:79] + node _T_1589 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1590 = xor(UInt<8>("h0ff"), _T_1589) @[Bitwise.scala 102:21] + node _T_1591 = shr(_T_1588, 4) @[Bitwise.scala 103:21] + node _T_1592 = and(_T_1591, _T_1590) @[Bitwise.scala 103:31] + node _T_1593 = bits(_T_1588, 3, 0) @[Bitwise.scala 103:46] + node _T_1594 = shl(_T_1593, 4) @[Bitwise.scala 103:65] + node _T_1595 = not(_T_1590) @[Bitwise.scala 103:77] + node _T_1596 = and(_T_1594, _T_1595) @[Bitwise.scala 103:75] + node _T_1597 = or(_T_1592, _T_1596) @[Bitwise.scala 103:39] + node _T_1598 = bits(_T_1590, 5, 0) @[Bitwise.scala 102:28] + node _T_1599 = shl(_T_1598, 2) @[Bitwise.scala 102:47] + node _T_1600 = xor(_T_1590, _T_1599) @[Bitwise.scala 102:21] + node _T_1601 = shr(_T_1597, 2) @[Bitwise.scala 103:21] + node _T_1602 = and(_T_1601, _T_1600) @[Bitwise.scala 103:31] + node _T_1603 = bits(_T_1597, 5, 0) @[Bitwise.scala 103:46] + node _T_1604 = shl(_T_1603, 2) @[Bitwise.scala 103:65] + node _T_1605 = not(_T_1600) @[Bitwise.scala 103:77] + node _T_1606 = and(_T_1604, _T_1605) @[Bitwise.scala 103:75] + node _T_1607 = or(_T_1602, _T_1606) @[Bitwise.scala 103:39] + node _T_1608 = bits(_T_1600, 6, 0) @[Bitwise.scala 102:28] + node _T_1609 = shl(_T_1608, 1) @[Bitwise.scala 102:47] + node _T_1610 = xor(_T_1600, _T_1609) @[Bitwise.scala 102:21] + node _T_1611 = shr(_T_1607, 1) @[Bitwise.scala 103:21] + node _T_1612 = and(_T_1611, _T_1610) @[Bitwise.scala 103:31] + node _T_1613 = bits(_T_1607, 6, 0) @[Bitwise.scala 103:46] + node _T_1614 = shl(_T_1613, 1) @[Bitwise.scala 103:65] + node _T_1615 = not(_T_1610) @[Bitwise.scala 103:77] + node _T_1616 = and(_T_1614, _T_1615) @[Bitwise.scala 103:75] + node _T_1617 = or(_T_1612, _T_1616) @[Bitwise.scala 103:39] + node _T_1618 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_hi) @[lsu_dccm_ctl.scala 262:105] + node _T_1619 = bits(store_byteen_ext_r, 5, 5) @[lsu_dccm_ctl.scala 262:150] + node _T_1620 = eq(_T_1619, UInt<1>("h00")) @[lsu_dccm_ctl.scala 262:131] + node _T_1621 = and(_T_1618, _T_1620) @[lsu_dccm_ctl.scala 262:129] + node _T_1622 = bits(_T_1621, 0, 0) @[lsu_dccm_ctl.scala 262:157] + node _T_1623 = bits(io.stbuf_data_any, 15, 8) @[lsu_dccm_ctl.scala 262:181] + node _T_1624 = bits(io.store_data_hi_r, 15, 8) @[lsu_dccm_ctl.scala 262:213] + node _T_1625 = mux(_T_1622, _T_1623, _T_1624) @[lsu_dccm_ctl.scala 262:79] + node _T_1626 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1627 = xor(UInt<8>("h0ff"), _T_1626) @[Bitwise.scala 102:21] + node _T_1628 = shr(_T_1625, 4) @[Bitwise.scala 103:21] + node _T_1629 = and(_T_1628, _T_1627) @[Bitwise.scala 103:31] + node _T_1630 = bits(_T_1625, 3, 0) @[Bitwise.scala 103:46] + node _T_1631 = shl(_T_1630, 4) @[Bitwise.scala 103:65] + node _T_1632 = not(_T_1627) @[Bitwise.scala 103:77] + node _T_1633 = and(_T_1631, _T_1632) @[Bitwise.scala 103:75] + node _T_1634 = or(_T_1629, _T_1633) @[Bitwise.scala 103:39] + node _T_1635 = bits(_T_1627, 5, 0) @[Bitwise.scala 102:28] + node _T_1636 = shl(_T_1635, 2) @[Bitwise.scala 102:47] + node _T_1637 = xor(_T_1627, _T_1636) @[Bitwise.scala 102:21] + node _T_1638 = shr(_T_1634, 2) @[Bitwise.scala 103:21] + node _T_1639 = and(_T_1638, _T_1637) @[Bitwise.scala 103:31] + node _T_1640 = bits(_T_1634, 5, 0) @[Bitwise.scala 103:46] + node _T_1641 = shl(_T_1640, 2) @[Bitwise.scala 103:65] + node _T_1642 = not(_T_1637) @[Bitwise.scala 103:77] + node _T_1643 = and(_T_1641, _T_1642) @[Bitwise.scala 103:75] + node _T_1644 = or(_T_1639, _T_1643) @[Bitwise.scala 103:39] + node _T_1645 = bits(_T_1637, 6, 0) @[Bitwise.scala 102:28] + node _T_1646 = shl(_T_1645, 1) @[Bitwise.scala 102:47] + node _T_1647 = xor(_T_1637, _T_1646) @[Bitwise.scala 102:21] + node _T_1648 = shr(_T_1644, 1) @[Bitwise.scala 103:21] + node _T_1649 = and(_T_1648, _T_1647) @[Bitwise.scala 103:31] + node _T_1650 = bits(_T_1644, 6, 0) @[Bitwise.scala 103:46] + node _T_1651 = shl(_T_1650, 1) @[Bitwise.scala 103:65] + node _T_1652 = not(_T_1647) @[Bitwise.scala 103:77] + node _T_1653 = and(_T_1651, _T_1652) @[Bitwise.scala 103:75] + node _T_1654 = or(_T_1649, _T_1653) @[Bitwise.scala 103:39] + node _T_1655 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_hi) @[lsu_dccm_ctl.scala 262:105] + node _T_1656 = bits(store_byteen_ext_r, 6, 6) @[lsu_dccm_ctl.scala 262:150] + node _T_1657 = eq(_T_1656, UInt<1>("h00")) @[lsu_dccm_ctl.scala 262:131] + node _T_1658 = and(_T_1655, _T_1657) @[lsu_dccm_ctl.scala 262:129] + node _T_1659 = bits(_T_1658, 0, 0) @[lsu_dccm_ctl.scala 262:157] + node _T_1660 = bits(io.stbuf_data_any, 23, 16) @[lsu_dccm_ctl.scala 262:181] + node _T_1661 = bits(io.store_data_hi_r, 23, 16) @[lsu_dccm_ctl.scala 262:213] + node _T_1662 = mux(_T_1659, _T_1660, _T_1661) @[lsu_dccm_ctl.scala 262:79] + node _T_1663 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1664 = xor(UInt<8>("h0ff"), _T_1663) @[Bitwise.scala 102:21] + node _T_1665 = shr(_T_1662, 4) @[Bitwise.scala 103:21] + node _T_1666 = and(_T_1665, _T_1664) @[Bitwise.scala 103:31] + node _T_1667 = bits(_T_1662, 3, 0) @[Bitwise.scala 103:46] + node _T_1668 = shl(_T_1667, 4) @[Bitwise.scala 103:65] + node _T_1669 = not(_T_1664) @[Bitwise.scala 103:77] + node _T_1670 = and(_T_1668, _T_1669) @[Bitwise.scala 103:75] + node _T_1671 = or(_T_1666, _T_1670) @[Bitwise.scala 103:39] + node _T_1672 = bits(_T_1664, 5, 0) @[Bitwise.scala 102:28] + node _T_1673 = shl(_T_1672, 2) @[Bitwise.scala 102:47] + node _T_1674 = xor(_T_1664, _T_1673) @[Bitwise.scala 102:21] + node _T_1675 = shr(_T_1671, 2) @[Bitwise.scala 103:21] + node _T_1676 = and(_T_1675, _T_1674) @[Bitwise.scala 103:31] + node _T_1677 = bits(_T_1671, 5, 0) @[Bitwise.scala 103:46] + node _T_1678 = shl(_T_1677, 2) @[Bitwise.scala 103:65] + node _T_1679 = not(_T_1674) @[Bitwise.scala 103:77] + node _T_1680 = and(_T_1678, _T_1679) @[Bitwise.scala 103:75] + node _T_1681 = or(_T_1676, _T_1680) @[Bitwise.scala 103:39] + node _T_1682 = bits(_T_1674, 6, 0) @[Bitwise.scala 102:28] + node _T_1683 = shl(_T_1682, 1) @[Bitwise.scala 102:47] + node _T_1684 = xor(_T_1674, _T_1683) @[Bitwise.scala 102:21] + node _T_1685 = shr(_T_1681, 1) @[Bitwise.scala 103:21] + node _T_1686 = and(_T_1685, _T_1684) @[Bitwise.scala 103:31] + node _T_1687 = bits(_T_1681, 6, 0) @[Bitwise.scala 103:46] + node _T_1688 = shl(_T_1687, 1) @[Bitwise.scala 103:65] + node _T_1689 = not(_T_1684) @[Bitwise.scala 103:77] + node _T_1690 = and(_T_1688, _T_1689) @[Bitwise.scala 103:75] + node _T_1691 = or(_T_1686, _T_1690) @[Bitwise.scala 103:39] + node _T_1692 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_hi) @[lsu_dccm_ctl.scala 262:105] + node _T_1693 = bits(store_byteen_ext_r, 7, 7) @[lsu_dccm_ctl.scala 262:150] + node _T_1694 = eq(_T_1693, UInt<1>("h00")) @[lsu_dccm_ctl.scala 262:131] + node _T_1695 = and(_T_1692, _T_1694) @[lsu_dccm_ctl.scala 262:129] + node _T_1696 = bits(_T_1695, 0, 0) @[lsu_dccm_ctl.scala 262:157] + node _T_1697 = bits(io.stbuf_data_any, 31, 24) @[lsu_dccm_ctl.scala 262:181] + node _T_1698 = bits(io.store_data_hi_r, 31, 24) @[lsu_dccm_ctl.scala 262:213] + node _T_1699 = mux(_T_1696, _T_1697, _T_1698) @[lsu_dccm_ctl.scala 262:79] + node _T_1700 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1701 = xor(UInt<8>("h0ff"), _T_1700) @[Bitwise.scala 102:21] + node _T_1702 = shr(_T_1699, 4) @[Bitwise.scala 103:21] + node _T_1703 = and(_T_1702, _T_1701) @[Bitwise.scala 103:31] + node _T_1704 = bits(_T_1699, 3, 0) @[Bitwise.scala 103:46] + node _T_1705 = shl(_T_1704, 4) @[Bitwise.scala 103:65] + node _T_1706 = not(_T_1701) @[Bitwise.scala 103:77] + node _T_1707 = and(_T_1705, _T_1706) @[Bitwise.scala 103:75] + node _T_1708 = or(_T_1703, _T_1707) @[Bitwise.scala 103:39] + node _T_1709 = bits(_T_1701, 5, 0) @[Bitwise.scala 102:28] + node _T_1710 = shl(_T_1709, 2) @[Bitwise.scala 102:47] + node _T_1711 = xor(_T_1701, _T_1710) @[Bitwise.scala 102:21] + node _T_1712 = shr(_T_1708, 2) @[Bitwise.scala 103:21] + node _T_1713 = and(_T_1712, _T_1711) @[Bitwise.scala 103:31] + node _T_1714 = bits(_T_1708, 5, 0) @[Bitwise.scala 103:46] + node _T_1715 = shl(_T_1714, 2) @[Bitwise.scala 103:65] + node _T_1716 = not(_T_1711) @[Bitwise.scala 103:77] + node _T_1717 = and(_T_1715, _T_1716) @[Bitwise.scala 103:75] + node _T_1718 = or(_T_1713, _T_1717) @[Bitwise.scala 103:39] + node _T_1719 = bits(_T_1711, 6, 0) @[Bitwise.scala 102:28] + node _T_1720 = shl(_T_1719, 1) @[Bitwise.scala 102:47] + node _T_1721 = xor(_T_1711, _T_1720) @[Bitwise.scala 102:21] + node _T_1722 = shr(_T_1718, 1) @[Bitwise.scala 103:21] + node _T_1723 = and(_T_1722, _T_1721) @[Bitwise.scala 103:31] + node _T_1724 = bits(_T_1718, 6, 0) @[Bitwise.scala 103:46] + node _T_1725 = shl(_T_1724, 1) @[Bitwise.scala 103:65] + node _T_1726 = not(_T_1721) @[Bitwise.scala 103:77] + node _T_1727 = and(_T_1725, _T_1726) @[Bitwise.scala 103:75] + node _T_1728 = or(_T_1723, _T_1727) @[Bitwise.scala 103:39] + wire _T_1729 : UInt<8>[4] @[lsu_dccm_ctl.scala 262:63] + _T_1729[0] <= _T_1617 @[lsu_dccm_ctl.scala 262:63] + _T_1729[1] <= _T_1654 @[lsu_dccm_ctl.scala 262:63] + _T_1729[2] <= _T_1691 @[lsu_dccm_ctl.scala 262:63] + _T_1729[3] <= _T_1728 @[lsu_dccm_ctl.scala 262:63] + node _T_1730 = cat(_T_1729[2], _T_1729[3]) @[Cat.scala 29:58] + node _T_1731 = cat(_T_1729[0], _T_1729[1]) @[Cat.scala 29:58] + node _T_1732 = cat(_T_1731, _T_1730) @[Cat.scala 29:58] + node _T_1733 = shl(UInt<16>("h0ffff"), 16) @[Bitwise.scala 102:47] + node _T_1734 = xor(UInt<32>("h0ffffffff"), _T_1733) @[Bitwise.scala 102:21] + node _T_1735 = shr(_T_1732, 16) @[Bitwise.scala 103:21] + node _T_1736 = and(_T_1735, _T_1734) @[Bitwise.scala 103:31] + node _T_1737 = bits(_T_1732, 15, 0) @[Bitwise.scala 103:46] + node _T_1738 = shl(_T_1737, 16) @[Bitwise.scala 103:65] + node _T_1739 = not(_T_1734) @[Bitwise.scala 103:77] + node _T_1740 = and(_T_1738, _T_1739) @[Bitwise.scala 103:75] + node _T_1741 = or(_T_1736, _T_1740) @[Bitwise.scala 103:39] + node _T_1742 = bits(_T_1734, 23, 0) @[Bitwise.scala 102:28] + node _T_1743 = shl(_T_1742, 8) @[Bitwise.scala 102:47] + node _T_1744 = xor(_T_1734, _T_1743) @[Bitwise.scala 102:21] + node _T_1745 = shr(_T_1741, 8) @[Bitwise.scala 103:21] + node _T_1746 = and(_T_1745, _T_1744) @[Bitwise.scala 103:31] + node _T_1747 = bits(_T_1741, 23, 0) @[Bitwise.scala 103:46] + node _T_1748 = shl(_T_1747, 8) @[Bitwise.scala 103:65] + node _T_1749 = not(_T_1744) @[Bitwise.scala 103:77] + node _T_1750 = and(_T_1748, _T_1749) @[Bitwise.scala 103:75] + node _T_1751 = or(_T_1746, _T_1750) @[Bitwise.scala 103:39] + node _T_1752 = bits(_T_1744, 27, 0) @[Bitwise.scala 102:28] + node _T_1753 = shl(_T_1752, 4) @[Bitwise.scala 102:47] + node _T_1754 = xor(_T_1744, _T_1753) @[Bitwise.scala 102:21] + node _T_1755 = shr(_T_1751, 4) @[Bitwise.scala 103:21] + node _T_1756 = and(_T_1755, _T_1754) @[Bitwise.scala 103:31] + node _T_1757 = bits(_T_1751, 27, 0) @[Bitwise.scala 103:46] + node _T_1758 = shl(_T_1757, 4) @[Bitwise.scala 103:65] + node _T_1759 = not(_T_1754) @[Bitwise.scala 103:77] + node _T_1760 = and(_T_1758, _T_1759) @[Bitwise.scala 103:75] + node _T_1761 = or(_T_1756, _T_1760) @[Bitwise.scala 103:39] + node _T_1762 = bits(_T_1754, 29, 0) @[Bitwise.scala 102:28] + node _T_1763 = shl(_T_1762, 2) @[Bitwise.scala 102:47] + node _T_1764 = xor(_T_1754, _T_1763) @[Bitwise.scala 102:21] + node _T_1765 = shr(_T_1761, 2) @[Bitwise.scala 103:21] + node _T_1766 = and(_T_1765, _T_1764) @[Bitwise.scala 103:31] + node _T_1767 = bits(_T_1761, 29, 0) @[Bitwise.scala 103:46] + node _T_1768 = shl(_T_1767, 2) @[Bitwise.scala 103:65] + node _T_1769 = not(_T_1764) @[Bitwise.scala 103:77] + node _T_1770 = and(_T_1768, _T_1769) @[Bitwise.scala 103:75] + node _T_1771 = or(_T_1766, _T_1770) @[Bitwise.scala 103:39] + node _T_1772 = bits(_T_1764, 30, 0) @[Bitwise.scala 102:28] + node _T_1773 = shl(_T_1772, 1) @[Bitwise.scala 102:47] + node _T_1774 = xor(_T_1764, _T_1773) @[Bitwise.scala 102:21] + node _T_1775 = shr(_T_1771, 1) @[Bitwise.scala 103:21] + node _T_1776 = and(_T_1775, _T_1774) @[Bitwise.scala 103:31] + node _T_1777 = bits(_T_1771, 30, 0) @[Bitwise.scala 103:46] + node _T_1778 = shl(_T_1777, 1) @[Bitwise.scala 103:65] + node _T_1779 = not(_T_1774) @[Bitwise.scala 103:77] + node _T_1780 = and(_T_1778, _T_1779) @[Bitwise.scala 103:75] + node _T_1781 = or(_T_1776, _T_1780) @[Bitwise.scala 103:39] + io.store_datafn_hi_r <= _T_1781 @[lsu_dccm_ctl.scala 262:29] + node _T_1782 = bits(io.store_data_hi_r, 31, 0) @[lsu_dccm_ctl.scala 263:55] + node _T_1783 = bits(io.store_data_lo_r, 31, 0) @[lsu_dccm_ctl.scala 263:80] + node _T_1784 = cat(_T_1782, _T_1783) @[Cat.scala 29:58] + node _T_1785 = bits(io.lsu_addr_r, 1, 0) @[lsu_dccm_ctl.scala 263:108] + node _T_1786 = mul(UInt<4>("h08"), _T_1785) @[lsu_dccm_ctl.scala 263:94] + node _T_1787 = dshr(_T_1784, _T_1786) @[lsu_dccm_ctl.scala 263:88] + node _T_1788 = bits(store_byteen_r, 0, 0) @[lsu_dccm_ctl.scala 263:174] + node _T_1789 = bits(_T_1788, 0, 0) @[Bitwise.scala 72:15] + node _T_1790 = mux(_T_1789, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1791 = bits(store_byteen_r, 1, 1) @[lsu_dccm_ctl.scala 263:174] + node _T_1792 = bits(_T_1791, 0, 0) @[Bitwise.scala 72:15] + node _T_1793 = mux(_T_1792, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1794 = bits(store_byteen_r, 2, 2) @[lsu_dccm_ctl.scala 263:174] + node _T_1795 = bits(_T_1794, 0, 0) @[Bitwise.scala 72:15] + node _T_1796 = mux(_T_1795, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1797 = bits(store_byteen_r, 3, 3) @[lsu_dccm_ctl.scala 263:174] + node _T_1798 = bits(_T_1797, 0, 0) @[Bitwise.scala 72:15] + node _T_1799 = mux(_T_1798, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + wire _T_1800 : UInt<8>[4] @[lsu_dccm_ctl.scala 263:148] + _T_1800[0] <= _T_1790 @[lsu_dccm_ctl.scala 263:148] + _T_1800[1] <= _T_1793 @[lsu_dccm_ctl.scala 263:148] + _T_1800[2] <= _T_1796 @[lsu_dccm_ctl.scala 263:148] + _T_1800[3] <= _T_1799 @[lsu_dccm_ctl.scala 263:148] + node _T_1801 = cat(_T_1800[2], _T_1800[3]) @[Cat.scala 29:58] + node _T_1802 = cat(_T_1800[0], _T_1800[1]) @[Cat.scala 29:58] + node _T_1803 = cat(_T_1802, _T_1801) @[Cat.scala 29:58] + node _T_1804 = shl(UInt<16>("h0ffff"), 16) @[Bitwise.scala 102:47] + node _T_1805 = xor(UInt<32>("h0ffffffff"), _T_1804) @[Bitwise.scala 102:21] + node _T_1806 = shr(_T_1803, 16) @[Bitwise.scala 103:21] + node _T_1807 = and(_T_1806, _T_1805) @[Bitwise.scala 103:31] + node _T_1808 = bits(_T_1803, 15, 0) @[Bitwise.scala 103:46] + node _T_1809 = shl(_T_1808, 16) @[Bitwise.scala 103:65] + node _T_1810 = not(_T_1805) @[Bitwise.scala 103:77] + node _T_1811 = and(_T_1809, _T_1810) @[Bitwise.scala 103:75] + node _T_1812 = or(_T_1807, _T_1811) @[Bitwise.scala 103:39] + node _T_1813 = bits(_T_1805, 23, 0) @[Bitwise.scala 102:28] + node _T_1814 = shl(_T_1813, 8) @[Bitwise.scala 102:47] + node _T_1815 = xor(_T_1805, _T_1814) @[Bitwise.scala 102:21] + node _T_1816 = shr(_T_1812, 8) @[Bitwise.scala 103:21] + node _T_1817 = and(_T_1816, _T_1815) @[Bitwise.scala 103:31] + node _T_1818 = bits(_T_1812, 23, 0) @[Bitwise.scala 103:46] + node _T_1819 = shl(_T_1818, 8) @[Bitwise.scala 103:65] + node _T_1820 = not(_T_1815) @[Bitwise.scala 103:77] + node _T_1821 = and(_T_1819, _T_1820) @[Bitwise.scala 103:75] + node _T_1822 = or(_T_1817, _T_1821) @[Bitwise.scala 103:39] + node _T_1823 = bits(_T_1815, 27, 0) @[Bitwise.scala 102:28] + node _T_1824 = shl(_T_1823, 4) @[Bitwise.scala 102:47] + node _T_1825 = xor(_T_1815, _T_1824) @[Bitwise.scala 102:21] + node _T_1826 = shr(_T_1822, 4) @[Bitwise.scala 103:21] + node _T_1827 = and(_T_1826, _T_1825) @[Bitwise.scala 103:31] + node _T_1828 = bits(_T_1822, 27, 0) @[Bitwise.scala 103:46] + node _T_1829 = shl(_T_1828, 4) @[Bitwise.scala 103:65] + node _T_1830 = not(_T_1825) @[Bitwise.scala 103:77] + node _T_1831 = and(_T_1829, _T_1830) @[Bitwise.scala 103:75] + node _T_1832 = or(_T_1827, _T_1831) @[Bitwise.scala 103:39] + node _T_1833 = bits(_T_1825, 29, 0) @[Bitwise.scala 102:28] + node _T_1834 = shl(_T_1833, 2) @[Bitwise.scala 102:47] + node _T_1835 = xor(_T_1825, _T_1834) @[Bitwise.scala 102:21] + node _T_1836 = shr(_T_1832, 2) @[Bitwise.scala 103:21] + node _T_1837 = and(_T_1836, _T_1835) @[Bitwise.scala 103:31] + node _T_1838 = bits(_T_1832, 29, 0) @[Bitwise.scala 103:46] + node _T_1839 = shl(_T_1838, 2) @[Bitwise.scala 103:65] + node _T_1840 = not(_T_1835) @[Bitwise.scala 103:77] + node _T_1841 = and(_T_1839, _T_1840) @[Bitwise.scala 103:75] + node _T_1842 = or(_T_1837, _T_1841) @[Bitwise.scala 103:39] + node _T_1843 = bits(_T_1835, 30, 0) @[Bitwise.scala 102:28] + node _T_1844 = shl(_T_1843, 1) @[Bitwise.scala 102:47] + node _T_1845 = xor(_T_1835, _T_1844) @[Bitwise.scala 102:21] + node _T_1846 = shr(_T_1842, 1) @[Bitwise.scala 103:21] + node _T_1847 = and(_T_1846, _T_1845) @[Bitwise.scala 103:31] + node _T_1848 = bits(_T_1842, 30, 0) @[Bitwise.scala 103:46] + node _T_1849 = shl(_T_1848, 1) @[Bitwise.scala 103:65] + node _T_1850 = not(_T_1845) @[Bitwise.scala 103:77] + node _T_1851 = and(_T_1849, _T_1850) @[Bitwise.scala 103:75] + node _T_1852 = or(_T_1847, _T_1851) @[Bitwise.scala 103:39] + node _T_1853 = and(_T_1787, _T_1852) @[lsu_dccm_ctl.scala 263:115] + io.store_data_r <= _T_1853 @[lsu_dccm_ctl.scala 263:29] + node _T_1854 = bits(io.dccm.rd_data_lo, 31, 0) @[lsu_dccm_ctl.scala 265:48] + io.dccm_rdata_lo_m <= _T_1854 @[lsu_dccm_ctl.scala 265:27] + node _T_1855 = bits(io.dccm.rd_data_hi, 31, 0) @[lsu_dccm_ctl.scala 266:48] + io.dccm_rdata_hi_m <= _T_1855 @[lsu_dccm_ctl.scala 266:27] + node _T_1856 = bits(io.dccm.rd_data_lo, 38, 32) @[lsu_dccm_ctl.scala 267:48] + io.dccm_data_ecc_lo_m <= _T_1856 @[lsu_dccm_ctl.scala 267:27] + node _T_1857 = bits(io.dccm.rd_data_hi, 38, 32) @[lsu_dccm_ctl.scala 268:48] + io.dccm_data_ecc_hi_m <= _T_1857 @[lsu_dccm_ctl.scala 268:27] + node _T_1858 = and(io.lsu_pkt_r.valid, io.lsu_pkt_r.bits.store) @[lsu_dccm_ctl.scala 270:58] + node _T_1859 = and(_T_1858, io.addr_in_pic_r) @[lsu_dccm_ctl.scala 270:84] + node _T_1860 = and(_T_1859, io.lsu_commit_r) @[lsu_dccm_ctl.scala 270:103] + node _T_1861 = or(_T_1860, io.dma_pic_wen) @[lsu_dccm_ctl.scala 270:122] + io.lsu_pic.picm_wren <= _T_1861 @[lsu_dccm_ctl.scala 270:35] + node _T_1862 = and(io.lsu_pkt_d.valid, io.lsu_pkt_d.bits.load) @[lsu_dccm_ctl.scala 271:58] + node _T_1863 = and(_T_1862, io.addr_in_pic_d) @[lsu_dccm_ctl.scala 271:84] + io.lsu_pic.picm_rden <= _T_1863 @[lsu_dccm_ctl.scala 271:35] + node _T_1864 = and(io.lsu_pkt_d.valid, io.lsu_pkt_d.bits.store) @[lsu_dccm_ctl.scala 272:58] + node _T_1865 = and(_T_1864, io.addr_in_pic_d) @[lsu_dccm_ctl.scala 272:84] + io.lsu_pic.picm_mken <= _T_1865 @[lsu_dccm_ctl.scala 272:35] + node _T_1866 = mux(UInt<1>("h00"), UInt<17>("h01ffff"), UInt<17>("h00")) @[Bitwise.scala 72:12] + node _T_1867 = bits(io.lsu_addr_d, 14, 0) @[lsu_dccm_ctl.scala 273:103] + node _T_1868 = cat(_T_1866, _T_1867) @[Cat.scala 29:58] + node _T_1869 = or(UInt<32>("h0f00c0000"), _T_1868) @[lsu_dccm_ctl.scala 273:62] + io.lsu_pic.picm_rdaddr <= _T_1869 @[lsu_dccm_ctl.scala 273:35] + node _T_1870 = mux(UInt<1>("h00"), UInt<17>("h01ffff"), UInt<17>("h00")) @[Bitwise.scala 72:12] + node _T_1871 = bits(io.dma_pic_wen, 0, 0) @[lsu_dccm_ctl.scala 274:109] + node _T_1872 = bits(io.dma_dccm_ctl.dma_mem_addr, 14, 0) @[lsu_dccm_ctl.scala 274:144] + node _T_1873 = bits(io.lsu_addr_r, 14, 0) @[lsu_dccm_ctl.scala 274:172] + node _T_1874 = mux(_T_1871, _T_1872, _T_1873) @[lsu_dccm_ctl.scala 274:93] + node _T_1875 = cat(_T_1870, _T_1874) @[Cat.scala 29:58] + node _T_1876 = or(UInt<32>("h0f00c0000"), _T_1875) @[lsu_dccm_ctl.scala 274:62] + io.lsu_pic.picm_wraddr <= _T_1876 @[lsu_dccm_ctl.scala 274:35] + node _T_1877 = bits(picm_rd_data_m, 31, 0) @[lsu_dccm_ctl.scala 275:44] + io.picm_mask_data_m <= _T_1877 @[lsu_dccm_ctl.scala 275:27] + node _T_1878 = bits(io.dma_pic_wen, 0, 0) @[lsu_dccm_ctl.scala 276:57] + node _T_1879 = bits(io.dma_dccm_ctl.dma_mem_wdata, 31, 0) @[lsu_dccm_ctl.scala 276:93] + node _T_1880 = bits(io.store_datafn_lo_r, 31, 0) @[lsu_dccm_ctl.scala 276:120] + node _T_1881 = mux(_T_1878, _T_1879, _T_1880) @[lsu_dccm_ctl.scala 276:41] + io.lsu_pic.picm_wr_data <= _T_1881 @[lsu_dccm_ctl.scala 276:35] + reg _T_1882 : UInt, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_dccm_ctl.scala 279:61] + _T_1882 <= lsu_dccm_rden_d @[lsu_dccm_ctl.scala 279:61] + io.lsu_dccm_rden_m <= _T_1882 @[lsu_dccm_ctl.scala 279:24] + reg _T_1883 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_dccm_ctl.scala 280:61] + _T_1883 <= io.lsu_dccm_rden_m @[lsu_dccm_ctl.scala 280:61] + io.lsu_dccm_rden_r <= _T_1883 @[lsu_dccm_ctl.scala 280:24] + + extmodule gated_latch_2 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_2 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_2 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_3 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_3 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_3 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_4 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_4 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_4 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_5 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_5 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_5 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_6 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_6 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_6 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_7 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_7 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_7 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_8 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_8 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_8 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_9 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_9 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_9 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + module lsu_stbuf : + input clock : Clock + input reset : AsyncReset + output io : {flip lsu_c1_m_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_stbuf_c1_clk : Clock, flip lsu_free_c2_clk : Clock, flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip store_stbuf_reqvld_r : UInt<1>, flip lsu_commit_r : UInt<1>, flip dec_lsu_valid_raw_d : UInt<1>, flip store_data_hi_r : UInt<32>, flip store_data_lo_r : UInt<32>, flip store_datafn_hi_r : UInt<32>, flip store_datafn_lo_r : UInt<32>, flip lsu_stbuf_commit_any : UInt<1>, flip lsu_addr_d : UInt<16>, flip lsu_addr_m : UInt<32>, flip lsu_addr_r : UInt<32>, flip end_addr_d : UInt<16>, flip end_addr_m : UInt<32>, flip end_addr_r : UInt<32>, flip addr_in_dccm_m : UInt<1>, flip addr_in_dccm_r : UInt<1>, flip lsu_cmpen_m : UInt<1>, flip scan_mode : UInt<1>, stbuf_reqvld_any : UInt<1>, stbuf_reqvld_flushed_any : UInt<1>, stbuf_addr_any : UInt<16>, stbuf_data_any : UInt<32>, lsu_stbuf_full_any : UInt<1>, lsu_stbuf_empty_any : UInt<1>, ldst_stbuf_reqvld_r : UInt<1>, stbuf_fwddata_hi_m : UInt<32>, stbuf_fwddata_lo_m : UInt<32>, stbuf_fwdbyteen_hi_m : UInt<4>, stbuf_fwdbyteen_lo_m : UInt<4>} + + io.stbuf_reqvld_any <= UInt<1>("h00") @[lsu_stbuf.scala 51:47] + io.stbuf_reqvld_flushed_any <= UInt<1>("h00") @[lsu_stbuf.scala 52:35] + io.stbuf_addr_any <= UInt<1>("h00") @[lsu_stbuf.scala 53:35] + io.stbuf_data_any <= UInt<1>("h00") @[lsu_stbuf.scala 54:35] + io.lsu_stbuf_full_any <= UInt<1>("h00") @[lsu_stbuf.scala 55:43] + io.lsu_stbuf_empty_any <= UInt<1>("h00") @[lsu_stbuf.scala 56:43] + io.ldst_stbuf_reqvld_r <= UInt<1>("h00") @[lsu_stbuf.scala 57:43] + io.stbuf_fwddata_hi_m <= UInt<1>("h00") @[lsu_stbuf.scala 58:43] + io.stbuf_fwddata_lo_m <= UInt<1>("h00") @[lsu_stbuf.scala 59:43] + io.stbuf_fwdbyteen_hi_m <= UInt<1>("h00") @[lsu_stbuf.scala 60:37] + io.stbuf_fwdbyteen_lo_m <= UInt<1>("h00") @[lsu_stbuf.scala 61:37] + wire stbuf_vld : UInt<4> + stbuf_vld <= UInt<1>("h00") + wire stbuf_wr_en : UInt<4> + stbuf_wr_en <= UInt<1>("h00") + wire stbuf_dma_kill_en : UInt<4> + stbuf_dma_kill_en <= UInt<1>("h00") + wire stbuf_dma_kill : UInt<4> + stbuf_dma_kill <= UInt<1>("h00") + wire stbuf_reset : UInt<4> + stbuf_reset <= UInt<1>("h00") + wire store_byteen_ext_r : UInt<8> + store_byteen_ext_r <= UInt<1>("h00") + wire stbuf_addr : UInt<16>[4] @[lsu_stbuf.scala 70:38] + stbuf_addr[0] <= UInt<1>("h00") @[lsu_stbuf.scala 71:14] + stbuf_addr[1] <= UInt<1>("h00") @[lsu_stbuf.scala 71:14] + stbuf_addr[2] <= UInt<1>("h00") @[lsu_stbuf.scala 71:14] + stbuf_addr[3] <= UInt<1>("h00") @[lsu_stbuf.scala 71:14] + wire stbuf_byteen : UInt<4>[4] @[lsu_stbuf.scala 72:38] + stbuf_byteen[0] <= UInt<1>("h00") @[lsu_stbuf.scala 73:16] + stbuf_byteen[1] <= UInt<1>("h00") @[lsu_stbuf.scala 73:16] + stbuf_byteen[2] <= UInt<1>("h00") @[lsu_stbuf.scala 73:16] + stbuf_byteen[3] <= UInt<1>("h00") @[lsu_stbuf.scala 73:16] + wire stbuf_data : UInt<32>[4] @[lsu_stbuf.scala 74:38] + stbuf_data[0] <= UInt<1>("h00") @[lsu_stbuf.scala 75:14] + stbuf_data[1] <= UInt<1>("h00") @[lsu_stbuf.scala 75:14] + stbuf_data[2] <= UInt<1>("h00") @[lsu_stbuf.scala 75:14] + stbuf_data[3] <= UInt<1>("h00") @[lsu_stbuf.scala 75:14] + wire stbuf_addrin : UInt<16>[4] @[lsu_stbuf.scala 76:38] + stbuf_addrin[0] <= UInt<1>("h00") @[lsu_stbuf.scala 77:16] + stbuf_addrin[1] <= UInt<1>("h00") @[lsu_stbuf.scala 77:16] + stbuf_addrin[2] <= UInt<1>("h00") @[lsu_stbuf.scala 77:16] + stbuf_addrin[3] <= UInt<1>("h00") @[lsu_stbuf.scala 77:16] + wire stbuf_datain : UInt<32>[4] @[lsu_stbuf.scala 78:38] + stbuf_datain[0] <= UInt<1>("h00") @[lsu_stbuf.scala 79:16] + stbuf_datain[1] <= UInt<1>("h00") @[lsu_stbuf.scala 79:16] + stbuf_datain[2] <= UInt<1>("h00") @[lsu_stbuf.scala 79:16] + stbuf_datain[3] <= UInt<1>("h00") @[lsu_stbuf.scala 79:16] + wire stbuf_byteenin : UInt<4>[4] @[lsu_stbuf.scala 80:38] + stbuf_byteenin[0] <= UInt<1>("h00") @[lsu_stbuf.scala 81:18] + stbuf_byteenin[1] <= UInt<1>("h00") @[lsu_stbuf.scala 81:18] + stbuf_byteenin[2] <= UInt<1>("h00") @[lsu_stbuf.scala 81:18] + stbuf_byteenin[3] <= UInt<1>("h00") @[lsu_stbuf.scala 81:18] + wire WrPtr : UInt<2> + WrPtr <= UInt<1>("h00") + wire RdPtr : UInt<2> + RdPtr <= UInt<1>("h00") + wire ldst_dual_m : UInt<1> + ldst_dual_m <= UInt<1>("h00") + wire ldst_dual_r : UInt<1> + ldst_dual_r <= UInt<1>("h00") + wire cmpaddr_hi_m : UInt<16> + cmpaddr_hi_m <= UInt<16>("h00") + wire stbuf_specvld_m : UInt<2> + stbuf_specvld_m <= UInt<2>("h00") + wire stbuf_specvld_r : UInt<2> + stbuf_specvld_r <= UInt<2>("h00") + wire cmpaddr_lo_m : UInt<16> + cmpaddr_lo_m <= UInt<16>("h00") + wire stbuf_fwdata_hi_pre_m : UInt<32> + stbuf_fwdata_hi_pre_m <= UInt<1>("h00") + wire stbuf_fwdata_lo_pre_m : UInt<32> + stbuf_fwdata_lo_pre_m <= UInt<1>("h00") + wire ld_byte_rhit_lo_lo : UInt<4> + ld_byte_rhit_lo_lo <= UInt<1>("h00") + wire ld_byte_rhit_hi_lo : UInt<4> + ld_byte_rhit_hi_lo <= UInt<1>("h00") + wire ld_byte_rhit_lo_hi : UInt<4> + ld_byte_rhit_lo_hi <= UInt<1>("h00") + wire ld_byte_rhit_hi_hi : UInt<4> + ld_byte_rhit_hi_hi <= UInt<1>("h00") + wire ld_byte_hit_lo : UInt<4> + ld_byte_hit_lo <= UInt<1>("h00") + wire ld_byte_rhit_lo : UInt<4> + ld_byte_rhit_lo <= UInt<1>("h00") + wire ld_byte_hit_hi : UInt<4> + ld_byte_hit_hi <= UInt<1>("h00") + wire ld_byte_rhit_hi : UInt<4> + ld_byte_rhit_hi <= UInt<1>("h00") + wire ldst_byteen_ext_r : UInt<8> + ldst_byteen_ext_r <= UInt<1>("h00") + wire ld_fwddata_rpipe_lo : UInt<32> + ld_fwddata_rpipe_lo <= UInt<1>("h00") + wire ld_fwddata_rpipe_hi : UInt<32> + ld_fwddata_rpipe_hi <= UInt<1>("h00") + wire datain1 : UInt<8>[4] @[lsu_stbuf.scala 105:33] + wire datain2 : UInt<8>[4] @[lsu_stbuf.scala 106:33] + wire datain3 : UInt<8>[4] @[lsu_stbuf.scala 107:33] + wire datain4 : UInt<8>[4] @[lsu_stbuf.scala 108:33] + node _T = bits(io.lsu_pkt_r.bits.by, 0, 0) @[lsu_stbuf.scala 112:26] + node _T_1 = bits(io.lsu_pkt_r.bits.half, 0, 0) @[lsu_stbuf.scala 113:28] + node _T_2 = bits(io.lsu_pkt_r.bits.word, 0, 0) @[lsu_stbuf.scala 114:28] + node _T_3 = bits(io.lsu_pkt_r.bits.dword, 0, 0) @[lsu_stbuf.scala 115:29] + node _T_4 = mux(_T, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_5 = mux(_T_1, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_6 = mux(_T_2, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_7 = mux(_T_3, UInt<8>("h0ff"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_8 = or(_T_4, _T_5) @[Mux.scala 27:72] + node _T_9 = or(_T_8, _T_6) @[Mux.scala 27:72] + node _T_10 = or(_T_9, _T_7) @[Mux.scala 27:72] + wire ldst_byteen_r : UInt<8> @[Mux.scala 27:72] + ldst_byteen_r <= _T_10 @[Mux.scala 27:72] + node _T_11 = bits(io.lsu_addr_d, 2, 2) @[lsu_stbuf.scala 117:35] + node _T_12 = bits(io.end_addr_d, 2, 2) @[lsu_stbuf.scala 117:56] + node ldst_dual_d = neq(_T_11, _T_12) @[lsu_stbuf.scala 117:39] + node dual_stbuf_write_r = and(ldst_dual_r, io.store_stbuf_reqvld_r) @[lsu_stbuf.scala 118:40] + node _T_13 = bits(io.lsu_addr_r, 1, 0) @[lsu_stbuf.scala 120:55] + node _T_14 = dshl(ldst_byteen_r, _T_13) @[lsu_stbuf.scala 120:39] + store_byteen_ext_r <= _T_14 @[lsu_stbuf.scala 120:22] + node _T_15 = bits(store_byteen_ext_r, 7, 4) @[lsu_stbuf.scala 121:46] + node _T_16 = bits(io.lsu_pkt_r.bits.store, 0, 0) @[Bitwise.scala 72:15] + node _T_17 = mux(_T_16, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node store_byteen_hi_r = and(_T_15, _T_17) @[lsu_stbuf.scala 121:52] + node _T_18 = bits(store_byteen_ext_r, 3, 0) @[lsu_stbuf.scala 122:46] + node _T_19 = bits(io.lsu_pkt_r.bits.store, 0, 0) @[Bitwise.scala 72:15] + node _T_20 = mux(_T_19, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node store_byteen_lo_r = and(_T_18, _T_20) @[lsu_stbuf.scala 122:52] + node _T_21 = add(RdPtr, UInt<1>("h01")) @[lsu_stbuf.scala 124:26] + node RdPtrPlus1 = tail(_T_21, 1) @[lsu_stbuf.scala 124:26] + node _T_22 = add(WrPtr, UInt<1>("h01")) @[lsu_stbuf.scala 125:26] + node WrPtrPlus1 = tail(_T_22, 1) @[lsu_stbuf.scala 125:26] + node _T_23 = add(WrPtr, UInt<2>("h02")) @[lsu_stbuf.scala 126:26] + node WrPtrPlus2 = tail(_T_23, 1) @[lsu_stbuf.scala 126:26] + node _T_24 = and(io.lsu_commit_r, io.store_stbuf_reqvld_r) @[lsu_stbuf.scala 128:45] + io.ldst_stbuf_reqvld_r <= _T_24 @[lsu_stbuf.scala 128:26] + node _T_25 = bits(stbuf_addr[0], 15, 2) @[lsu_stbuf.scala 130:78] + node _T_26 = bits(io.lsu_addr_r, 15, 2) @[lsu_stbuf.scala 130:137] + node _T_27 = eq(_T_25, _T_26) @[lsu_stbuf.scala 130:120] + node _T_28 = bits(stbuf_vld, 0, 0) @[lsu_stbuf.scala 130:191] + node _T_29 = and(_T_27, _T_28) @[lsu_stbuf.scala 130:179] + node _T_30 = bits(stbuf_dma_kill, 0, 0) @[lsu_stbuf.scala 130:212] + node _T_31 = eq(_T_30, UInt<1>("h00")) @[lsu_stbuf.scala 130:197] + node _T_32 = and(_T_29, _T_31) @[lsu_stbuf.scala 130:195] + node _T_33 = bits(stbuf_reset, 0, 0) @[lsu_stbuf.scala 130:230] + node _T_34 = eq(_T_33, UInt<1>("h00")) @[lsu_stbuf.scala 130:218] + node _T_35 = and(_T_32, _T_34) @[lsu_stbuf.scala 130:216] + node _T_36 = bits(stbuf_addr[1], 15, 2) @[lsu_stbuf.scala 130:78] + node _T_37 = bits(io.lsu_addr_r, 15, 2) @[lsu_stbuf.scala 130:137] + node _T_38 = eq(_T_36, _T_37) @[lsu_stbuf.scala 130:120] + node _T_39 = bits(stbuf_vld, 1, 1) @[lsu_stbuf.scala 130:191] + node _T_40 = and(_T_38, _T_39) @[lsu_stbuf.scala 130:179] + node _T_41 = bits(stbuf_dma_kill, 1, 1) @[lsu_stbuf.scala 130:212] + node _T_42 = eq(_T_41, UInt<1>("h00")) @[lsu_stbuf.scala 130:197] + node _T_43 = and(_T_40, _T_42) @[lsu_stbuf.scala 130:195] + node _T_44 = bits(stbuf_reset, 1, 1) @[lsu_stbuf.scala 130:230] + node _T_45 = eq(_T_44, UInt<1>("h00")) @[lsu_stbuf.scala 130:218] + node _T_46 = and(_T_43, _T_45) @[lsu_stbuf.scala 130:216] + node _T_47 = bits(stbuf_addr[2], 15, 2) @[lsu_stbuf.scala 130:78] + node _T_48 = bits(io.lsu_addr_r, 15, 2) @[lsu_stbuf.scala 130:137] + node _T_49 = eq(_T_47, _T_48) @[lsu_stbuf.scala 130:120] + node _T_50 = bits(stbuf_vld, 2, 2) @[lsu_stbuf.scala 130:191] + node _T_51 = and(_T_49, _T_50) @[lsu_stbuf.scala 130:179] + node _T_52 = bits(stbuf_dma_kill, 2, 2) @[lsu_stbuf.scala 130:212] + node _T_53 = eq(_T_52, UInt<1>("h00")) @[lsu_stbuf.scala 130:197] + node _T_54 = and(_T_51, _T_53) @[lsu_stbuf.scala 130:195] + node _T_55 = bits(stbuf_reset, 2, 2) @[lsu_stbuf.scala 130:230] + node _T_56 = eq(_T_55, UInt<1>("h00")) @[lsu_stbuf.scala 130:218] + node _T_57 = and(_T_54, _T_56) @[lsu_stbuf.scala 130:216] + node _T_58 = bits(stbuf_addr[3], 15, 2) @[lsu_stbuf.scala 130:78] + node _T_59 = bits(io.lsu_addr_r, 15, 2) @[lsu_stbuf.scala 130:137] + node _T_60 = eq(_T_58, _T_59) @[lsu_stbuf.scala 130:120] + node _T_61 = bits(stbuf_vld, 3, 3) @[lsu_stbuf.scala 130:191] + node _T_62 = and(_T_60, _T_61) @[lsu_stbuf.scala 130:179] + node _T_63 = bits(stbuf_dma_kill, 3, 3) @[lsu_stbuf.scala 130:212] + node _T_64 = eq(_T_63, UInt<1>("h00")) @[lsu_stbuf.scala 130:197] + node _T_65 = and(_T_62, _T_64) @[lsu_stbuf.scala 130:195] + node _T_66 = bits(stbuf_reset, 3, 3) @[lsu_stbuf.scala 130:230] + node _T_67 = eq(_T_66, UInt<1>("h00")) @[lsu_stbuf.scala 130:218] + node _T_68 = and(_T_65, _T_67) @[lsu_stbuf.scala 130:216] + node _T_69 = cat(_T_68, _T_57) @[Cat.scala 29:58] + node _T_70 = cat(_T_69, _T_46) @[Cat.scala 29:58] + node store_matchvec_lo_r = cat(_T_70, _T_35) @[Cat.scala 29:58] + node _T_71 = bits(stbuf_addr[0], 15, 2) @[lsu_stbuf.scala 131:78] + node _T_72 = bits(io.end_addr_r, 15, 2) @[lsu_stbuf.scala 131:137] + node _T_73 = eq(_T_71, _T_72) @[lsu_stbuf.scala 131:120] + node _T_74 = bits(stbuf_vld, 0, 0) @[lsu_stbuf.scala 131:190] + node _T_75 = and(_T_73, _T_74) @[lsu_stbuf.scala 131:179] + node _T_76 = bits(stbuf_dma_kill, 0, 0) @[lsu_stbuf.scala 131:211] + node _T_77 = eq(_T_76, UInt<1>("h00")) @[lsu_stbuf.scala 131:196] + node _T_78 = and(_T_75, _T_77) @[lsu_stbuf.scala 131:194] + node _T_79 = and(_T_78, dual_stbuf_write_r) @[lsu_stbuf.scala 131:215] + node _T_80 = bits(stbuf_reset, 0, 0) @[lsu_stbuf.scala 131:250] + node _T_81 = eq(_T_80, UInt<1>("h00")) @[lsu_stbuf.scala 131:238] + node _T_82 = and(_T_79, _T_81) @[lsu_stbuf.scala 131:236] + node _T_83 = bits(stbuf_addr[1], 15, 2) @[lsu_stbuf.scala 131:78] + node _T_84 = bits(io.end_addr_r, 15, 2) @[lsu_stbuf.scala 131:137] + node _T_85 = eq(_T_83, _T_84) @[lsu_stbuf.scala 131:120] + node _T_86 = bits(stbuf_vld, 1, 1) @[lsu_stbuf.scala 131:190] + node _T_87 = and(_T_85, _T_86) @[lsu_stbuf.scala 131:179] + node _T_88 = bits(stbuf_dma_kill, 1, 1) @[lsu_stbuf.scala 131:211] + node _T_89 = eq(_T_88, UInt<1>("h00")) @[lsu_stbuf.scala 131:196] + node _T_90 = and(_T_87, _T_89) @[lsu_stbuf.scala 131:194] + node _T_91 = and(_T_90, dual_stbuf_write_r) @[lsu_stbuf.scala 131:215] + node _T_92 = bits(stbuf_reset, 1, 1) @[lsu_stbuf.scala 131:250] + node _T_93 = eq(_T_92, UInt<1>("h00")) @[lsu_stbuf.scala 131:238] + node _T_94 = and(_T_91, _T_93) @[lsu_stbuf.scala 131:236] + node _T_95 = bits(stbuf_addr[2], 15, 2) @[lsu_stbuf.scala 131:78] + node _T_96 = bits(io.end_addr_r, 15, 2) @[lsu_stbuf.scala 131:137] + node _T_97 = eq(_T_95, _T_96) @[lsu_stbuf.scala 131:120] + node _T_98 = bits(stbuf_vld, 2, 2) @[lsu_stbuf.scala 131:190] + node _T_99 = and(_T_97, _T_98) @[lsu_stbuf.scala 131:179] + node _T_100 = bits(stbuf_dma_kill, 2, 2) @[lsu_stbuf.scala 131:211] + node _T_101 = eq(_T_100, UInt<1>("h00")) @[lsu_stbuf.scala 131:196] + node _T_102 = and(_T_99, _T_101) @[lsu_stbuf.scala 131:194] + node _T_103 = and(_T_102, dual_stbuf_write_r) @[lsu_stbuf.scala 131:215] + node _T_104 = bits(stbuf_reset, 2, 2) @[lsu_stbuf.scala 131:250] + node _T_105 = eq(_T_104, UInt<1>("h00")) @[lsu_stbuf.scala 131:238] + node _T_106 = and(_T_103, _T_105) @[lsu_stbuf.scala 131:236] + node _T_107 = bits(stbuf_addr[3], 15, 2) @[lsu_stbuf.scala 131:78] + node _T_108 = bits(io.end_addr_r, 15, 2) @[lsu_stbuf.scala 131:137] + node _T_109 = eq(_T_107, _T_108) @[lsu_stbuf.scala 131:120] + node _T_110 = bits(stbuf_vld, 3, 3) @[lsu_stbuf.scala 131:190] + node _T_111 = and(_T_109, _T_110) @[lsu_stbuf.scala 131:179] + node _T_112 = bits(stbuf_dma_kill, 3, 3) @[lsu_stbuf.scala 131:211] + node _T_113 = eq(_T_112, UInt<1>("h00")) @[lsu_stbuf.scala 131:196] + node _T_114 = and(_T_111, _T_113) @[lsu_stbuf.scala 131:194] + node _T_115 = and(_T_114, dual_stbuf_write_r) @[lsu_stbuf.scala 131:215] + node _T_116 = bits(stbuf_reset, 3, 3) @[lsu_stbuf.scala 131:250] + node _T_117 = eq(_T_116, UInt<1>("h00")) @[lsu_stbuf.scala 131:238] + node _T_118 = and(_T_115, _T_117) @[lsu_stbuf.scala 131:236] + node _T_119 = cat(_T_118, _T_106) @[Cat.scala 29:58] + node _T_120 = cat(_T_119, _T_94) @[Cat.scala 29:58] + node store_matchvec_hi_r = cat(_T_120, _T_82) @[Cat.scala 29:58] + node store_coalesce_lo_r = orr(store_matchvec_lo_r) @[lsu_stbuf.scala 133:49] + node store_coalesce_hi_r = orr(store_matchvec_hi_r) @[lsu_stbuf.scala 134:49] + node _T_121 = eq(UInt<1>("h00"), WrPtr) @[lsu_stbuf.scala 137:16] + node _T_122 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[lsu_stbuf.scala 137:29] + node _T_123 = and(_T_121, _T_122) @[lsu_stbuf.scala 137:27] + node _T_124 = eq(UInt<1>("h00"), WrPtr) @[lsu_stbuf.scala 138:18] + node _T_125 = and(_T_124, dual_stbuf_write_r) @[lsu_stbuf.scala 138:29] + node _T_126 = eq(store_coalesce_hi_r, UInt<1>("h00")) @[lsu_stbuf.scala 138:52] + node _T_127 = and(_T_125, _T_126) @[lsu_stbuf.scala 138:50] + node _T_128 = or(_T_123, _T_127) @[lsu_stbuf.scala 137:51] + node _T_129 = eq(UInt<1>("h00"), WrPtrPlus1) @[lsu_stbuf.scala 139:18] + node _T_130 = and(_T_129, dual_stbuf_write_r) @[lsu_stbuf.scala 139:34] + node _T_131 = or(store_coalesce_lo_r, store_coalesce_hi_r) @[lsu_stbuf.scala 139:79] + node _T_132 = eq(_T_131, UInt<1>("h00")) @[lsu_stbuf.scala 139:57] + node _T_133 = and(_T_130, _T_132) @[lsu_stbuf.scala 139:55] + node _T_134 = or(_T_128, _T_133) @[lsu_stbuf.scala 138:74] + node _T_135 = bits(store_matchvec_lo_r, 0, 0) @[lsu_stbuf.scala 140:26] + node _T_136 = or(_T_134, _T_135) @[lsu_stbuf.scala 139:103] + node _T_137 = bits(store_matchvec_hi_r, 0, 0) @[lsu_stbuf.scala 140:51] + node _T_138 = or(_T_136, _T_137) @[lsu_stbuf.scala 140:30] + node _T_139 = and(io.ldst_stbuf_reqvld_r, _T_138) @[lsu_stbuf.scala 136:76] + node _T_140 = eq(UInt<1>("h01"), WrPtr) @[lsu_stbuf.scala 137:16] + node _T_141 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[lsu_stbuf.scala 137:29] + node _T_142 = and(_T_140, _T_141) @[lsu_stbuf.scala 137:27] + node _T_143 = eq(UInt<1>("h01"), WrPtr) @[lsu_stbuf.scala 138:18] + node _T_144 = and(_T_143, dual_stbuf_write_r) @[lsu_stbuf.scala 138:29] + node _T_145 = eq(store_coalesce_hi_r, UInt<1>("h00")) @[lsu_stbuf.scala 138:52] + node _T_146 = and(_T_144, _T_145) @[lsu_stbuf.scala 138:50] + node _T_147 = or(_T_142, _T_146) @[lsu_stbuf.scala 137:51] + node _T_148 = eq(UInt<1>("h01"), WrPtrPlus1) @[lsu_stbuf.scala 139:18] + node _T_149 = and(_T_148, dual_stbuf_write_r) @[lsu_stbuf.scala 139:34] + node _T_150 = or(store_coalesce_lo_r, store_coalesce_hi_r) @[lsu_stbuf.scala 139:79] + node _T_151 = eq(_T_150, UInt<1>("h00")) @[lsu_stbuf.scala 139:57] + node _T_152 = and(_T_149, _T_151) @[lsu_stbuf.scala 139:55] + node _T_153 = or(_T_147, _T_152) @[lsu_stbuf.scala 138:74] + node _T_154 = bits(store_matchvec_lo_r, 1, 1) @[lsu_stbuf.scala 140:26] + node _T_155 = or(_T_153, _T_154) @[lsu_stbuf.scala 139:103] + node _T_156 = bits(store_matchvec_hi_r, 1, 1) @[lsu_stbuf.scala 140:51] + node _T_157 = or(_T_155, _T_156) @[lsu_stbuf.scala 140:30] + node _T_158 = and(io.ldst_stbuf_reqvld_r, _T_157) @[lsu_stbuf.scala 136:76] + node _T_159 = eq(UInt<2>("h02"), WrPtr) @[lsu_stbuf.scala 137:16] + node _T_160 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[lsu_stbuf.scala 137:29] + node _T_161 = and(_T_159, _T_160) @[lsu_stbuf.scala 137:27] + node _T_162 = eq(UInt<2>("h02"), WrPtr) @[lsu_stbuf.scala 138:18] + node _T_163 = and(_T_162, dual_stbuf_write_r) @[lsu_stbuf.scala 138:29] + node _T_164 = eq(store_coalesce_hi_r, UInt<1>("h00")) @[lsu_stbuf.scala 138:52] + node _T_165 = and(_T_163, _T_164) @[lsu_stbuf.scala 138:50] + node _T_166 = or(_T_161, _T_165) @[lsu_stbuf.scala 137:51] + node _T_167 = eq(UInt<2>("h02"), WrPtrPlus1) @[lsu_stbuf.scala 139:18] + node _T_168 = and(_T_167, dual_stbuf_write_r) @[lsu_stbuf.scala 139:34] + node _T_169 = or(store_coalesce_lo_r, store_coalesce_hi_r) @[lsu_stbuf.scala 139:79] + node _T_170 = eq(_T_169, UInt<1>("h00")) @[lsu_stbuf.scala 139:57] + node _T_171 = and(_T_168, _T_170) @[lsu_stbuf.scala 139:55] + node _T_172 = or(_T_166, _T_171) @[lsu_stbuf.scala 138:74] + node _T_173 = bits(store_matchvec_lo_r, 2, 2) @[lsu_stbuf.scala 140:26] + node _T_174 = or(_T_172, _T_173) @[lsu_stbuf.scala 139:103] + node _T_175 = bits(store_matchvec_hi_r, 2, 2) @[lsu_stbuf.scala 140:51] + node _T_176 = or(_T_174, _T_175) @[lsu_stbuf.scala 140:30] + node _T_177 = and(io.ldst_stbuf_reqvld_r, _T_176) @[lsu_stbuf.scala 136:76] + node _T_178 = eq(UInt<2>("h03"), WrPtr) @[lsu_stbuf.scala 137:16] + node _T_179 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[lsu_stbuf.scala 137:29] + node _T_180 = and(_T_178, _T_179) @[lsu_stbuf.scala 137:27] + node _T_181 = eq(UInt<2>("h03"), WrPtr) @[lsu_stbuf.scala 138:18] + node _T_182 = and(_T_181, dual_stbuf_write_r) @[lsu_stbuf.scala 138:29] + node _T_183 = eq(store_coalesce_hi_r, UInt<1>("h00")) @[lsu_stbuf.scala 138:52] + node _T_184 = and(_T_182, _T_183) @[lsu_stbuf.scala 138:50] + node _T_185 = or(_T_180, _T_184) @[lsu_stbuf.scala 137:51] + node _T_186 = eq(UInt<2>("h03"), WrPtrPlus1) @[lsu_stbuf.scala 139:18] + node _T_187 = and(_T_186, dual_stbuf_write_r) @[lsu_stbuf.scala 139:34] + node _T_188 = or(store_coalesce_lo_r, store_coalesce_hi_r) @[lsu_stbuf.scala 139:79] + node _T_189 = eq(_T_188, UInt<1>("h00")) @[lsu_stbuf.scala 139:57] + node _T_190 = and(_T_187, _T_189) @[lsu_stbuf.scala 139:55] + node _T_191 = or(_T_185, _T_190) @[lsu_stbuf.scala 138:74] + node _T_192 = bits(store_matchvec_lo_r, 3, 3) @[lsu_stbuf.scala 140:26] + node _T_193 = or(_T_191, _T_192) @[lsu_stbuf.scala 139:103] + node _T_194 = bits(store_matchvec_hi_r, 3, 3) @[lsu_stbuf.scala 140:51] + node _T_195 = or(_T_193, _T_194) @[lsu_stbuf.scala 140:30] + node _T_196 = and(io.ldst_stbuf_reqvld_r, _T_195) @[lsu_stbuf.scala 136:76] + node _T_197 = cat(_T_196, _T_177) @[Cat.scala 29:58] + node _T_198 = cat(_T_197, _T_158) @[Cat.scala 29:58] + node _T_199 = cat(_T_198, _T_139) @[Cat.scala 29:58] + stbuf_wr_en <= _T_199 @[lsu_stbuf.scala 136:15] + node _T_200 = or(io.lsu_stbuf_commit_any, io.stbuf_reqvld_flushed_any) @[lsu_stbuf.scala 141:78] + node _T_201 = eq(UInt<1>("h00"), RdPtr) @[lsu_stbuf.scala 141:121] + node _T_202 = bits(_T_201, 0, 0) @[lsu_stbuf.scala 141:132] + node _T_203 = and(_T_200, _T_202) @[lsu_stbuf.scala 141:109] + node _T_204 = or(io.lsu_stbuf_commit_any, io.stbuf_reqvld_flushed_any) @[lsu_stbuf.scala 141:78] + node _T_205 = eq(UInt<1>("h01"), RdPtr) @[lsu_stbuf.scala 141:121] + node _T_206 = bits(_T_205, 0, 0) @[lsu_stbuf.scala 141:132] + node _T_207 = and(_T_204, _T_206) @[lsu_stbuf.scala 141:109] + node _T_208 = or(io.lsu_stbuf_commit_any, io.stbuf_reqvld_flushed_any) @[lsu_stbuf.scala 141:78] + node _T_209 = eq(UInt<2>("h02"), RdPtr) @[lsu_stbuf.scala 141:121] + node _T_210 = bits(_T_209, 0, 0) @[lsu_stbuf.scala 141:132] + node _T_211 = and(_T_208, _T_210) @[lsu_stbuf.scala 141:109] + node _T_212 = or(io.lsu_stbuf_commit_any, io.stbuf_reqvld_flushed_any) @[lsu_stbuf.scala 141:78] + node _T_213 = eq(UInt<2>("h03"), RdPtr) @[lsu_stbuf.scala 141:121] + node _T_214 = bits(_T_213, 0, 0) @[lsu_stbuf.scala 141:132] + node _T_215 = and(_T_212, _T_214) @[lsu_stbuf.scala 141:109] + node _T_216 = cat(_T_215, _T_211) @[Cat.scala 29:58] + node _T_217 = cat(_T_216, _T_207) @[Cat.scala 29:58] + node _T_218 = cat(_T_217, _T_203) @[Cat.scala 29:58] + stbuf_reset <= _T_218 @[lsu_stbuf.scala 141:15] + node _T_219 = eq(ldst_dual_r, UInt<1>("h00")) @[lsu_stbuf.scala 142:53] + node _T_220 = or(_T_219, io.store_stbuf_reqvld_r) @[lsu_stbuf.scala 142:66] + node _T_221 = eq(UInt<1>("h00"), WrPtr) @[lsu_stbuf.scala 142:105] + node _T_222 = bits(_T_221, 0, 0) @[lsu_stbuf.scala 142:116] + node _T_223 = and(_T_220, _T_222) @[lsu_stbuf.scala 142:93] + node _T_224 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[lsu_stbuf.scala 142:125] + node _T_225 = and(_T_223, _T_224) @[lsu_stbuf.scala 142:123] + node _T_226 = bits(store_matchvec_lo_r, 0, 0) @[lsu_stbuf.scala 142:168] + node _T_227 = or(_T_225, _T_226) @[lsu_stbuf.scala 142:147] + node _T_228 = eq(ldst_dual_r, UInt<1>("h00")) @[lsu_stbuf.scala 142:53] + node _T_229 = or(_T_228, io.store_stbuf_reqvld_r) @[lsu_stbuf.scala 142:66] + node _T_230 = eq(UInt<1>("h01"), WrPtr) @[lsu_stbuf.scala 142:105] + node _T_231 = bits(_T_230, 0, 0) @[lsu_stbuf.scala 142:116] + node _T_232 = and(_T_229, _T_231) @[lsu_stbuf.scala 142:93] + node _T_233 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[lsu_stbuf.scala 142:125] + node _T_234 = and(_T_232, _T_233) @[lsu_stbuf.scala 142:123] + node _T_235 = bits(store_matchvec_lo_r, 1, 1) @[lsu_stbuf.scala 142:168] + node _T_236 = or(_T_234, _T_235) @[lsu_stbuf.scala 142:147] + node _T_237 = eq(ldst_dual_r, UInt<1>("h00")) @[lsu_stbuf.scala 142:53] + node _T_238 = or(_T_237, io.store_stbuf_reqvld_r) @[lsu_stbuf.scala 142:66] + node _T_239 = eq(UInt<2>("h02"), WrPtr) @[lsu_stbuf.scala 142:105] + node _T_240 = bits(_T_239, 0, 0) @[lsu_stbuf.scala 142:116] + node _T_241 = and(_T_238, _T_240) @[lsu_stbuf.scala 142:93] + node _T_242 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[lsu_stbuf.scala 142:125] + node _T_243 = and(_T_241, _T_242) @[lsu_stbuf.scala 142:123] + node _T_244 = bits(store_matchvec_lo_r, 2, 2) @[lsu_stbuf.scala 142:168] + node _T_245 = or(_T_243, _T_244) @[lsu_stbuf.scala 142:147] + node _T_246 = eq(ldst_dual_r, UInt<1>("h00")) @[lsu_stbuf.scala 142:53] + node _T_247 = or(_T_246, io.store_stbuf_reqvld_r) @[lsu_stbuf.scala 142:66] + node _T_248 = eq(UInt<2>("h03"), WrPtr) @[lsu_stbuf.scala 142:105] + node _T_249 = bits(_T_248, 0, 0) @[lsu_stbuf.scala 142:116] + node _T_250 = and(_T_247, _T_249) @[lsu_stbuf.scala 142:93] + node _T_251 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[lsu_stbuf.scala 142:125] + node _T_252 = and(_T_250, _T_251) @[lsu_stbuf.scala 142:123] + node _T_253 = bits(store_matchvec_lo_r, 3, 3) @[lsu_stbuf.scala 142:168] + node _T_254 = or(_T_252, _T_253) @[lsu_stbuf.scala 142:147] + node _T_255 = cat(_T_254, _T_245) @[Cat.scala 29:58] + node _T_256 = cat(_T_255, _T_236) @[Cat.scala 29:58] + node sel_lo = cat(_T_256, _T_227) @[Cat.scala 29:58] + node _T_257 = bits(sel_lo, 0, 0) @[lsu_stbuf.scala 144:63] + node _T_258 = bits(io.lsu_addr_r, 15, 0) @[lsu_stbuf.scala 144:81] + node _T_259 = bits(io.end_addr_r, 15, 0) @[lsu_stbuf.scala 144:113] + node _T_260 = mux(_T_257, _T_258, _T_259) @[lsu_stbuf.scala 144:56] + node _T_261 = bits(sel_lo, 1, 1) @[lsu_stbuf.scala 144:63] + node _T_262 = bits(io.lsu_addr_r, 15, 0) @[lsu_stbuf.scala 144:81] + node _T_263 = bits(io.end_addr_r, 15, 0) @[lsu_stbuf.scala 144:113] + node _T_264 = mux(_T_261, _T_262, _T_263) @[lsu_stbuf.scala 144:56] + node _T_265 = bits(sel_lo, 2, 2) @[lsu_stbuf.scala 144:63] + node _T_266 = bits(io.lsu_addr_r, 15, 0) @[lsu_stbuf.scala 144:81] + node _T_267 = bits(io.end_addr_r, 15, 0) @[lsu_stbuf.scala 144:113] + node _T_268 = mux(_T_265, _T_266, _T_267) @[lsu_stbuf.scala 144:56] + node _T_269 = bits(sel_lo, 3, 3) @[lsu_stbuf.scala 144:63] + node _T_270 = bits(io.lsu_addr_r, 15, 0) @[lsu_stbuf.scala 144:81] + node _T_271 = bits(io.end_addr_r, 15, 0) @[lsu_stbuf.scala 144:113] + node _T_272 = mux(_T_269, _T_270, _T_271) @[lsu_stbuf.scala 144:56] + stbuf_addrin[0] <= _T_260 @[lsu_stbuf.scala 144:16] + stbuf_addrin[1] <= _T_264 @[lsu_stbuf.scala 144:16] + stbuf_addrin[2] <= _T_268 @[lsu_stbuf.scala 144:16] + stbuf_addrin[3] <= _T_272 @[lsu_stbuf.scala 144:16] + node _T_273 = bits(sel_lo, 0, 0) @[lsu_stbuf.scala 145:65] + node _T_274 = or(stbuf_byteen[0], store_byteen_lo_r) @[lsu_stbuf.scala 145:86] + node _T_275 = or(stbuf_byteen[0], store_byteen_hi_r) @[lsu_stbuf.scala 145:123] + node _T_276 = mux(_T_273, _T_274, _T_275) @[lsu_stbuf.scala 145:58] + node _T_277 = bits(sel_lo, 1, 1) @[lsu_stbuf.scala 145:65] + node _T_278 = or(stbuf_byteen[1], store_byteen_lo_r) @[lsu_stbuf.scala 145:86] + node _T_279 = or(stbuf_byteen[1], store_byteen_hi_r) @[lsu_stbuf.scala 145:123] + node _T_280 = mux(_T_277, _T_278, _T_279) @[lsu_stbuf.scala 145:58] + node _T_281 = bits(sel_lo, 2, 2) @[lsu_stbuf.scala 145:65] + node _T_282 = or(stbuf_byteen[2], store_byteen_lo_r) @[lsu_stbuf.scala 145:86] + node _T_283 = or(stbuf_byteen[2], store_byteen_hi_r) @[lsu_stbuf.scala 145:123] + node _T_284 = mux(_T_281, _T_282, _T_283) @[lsu_stbuf.scala 145:58] + node _T_285 = bits(sel_lo, 3, 3) @[lsu_stbuf.scala 145:65] + node _T_286 = or(stbuf_byteen[3], store_byteen_lo_r) @[lsu_stbuf.scala 145:86] + node _T_287 = or(stbuf_byteen[3], store_byteen_hi_r) @[lsu_stbuf.scala 145:123] + node _T_288 = mux(_T_285, _T_286, _T_287) @[lsu_stbuf.scala 145:58] + stbuf_byteenin[0] <= _T_276 @[lsu_stbuf.scala 145:18] + stbuf_byteenin[1] <= _T_280 @[lsu_stbuf.scala 145:18] + stbuf_byteenin[2] <= _T_284 @[lsu_stbuf.scala 145:18] + stbuf_byteenin[3] <= _T_288 @[lsu_stbuf.scala 145:18] + node _T_289 = bits(sel_lo, 0, 0) @[lsu_stbuf.scala 147:58] + node _T_290 = bits(stbuf_byteen[0], 0, 0) @[lsu_stbuf.scala 147:83] + node _T_291 = eq(_T_290, UInt<1>("h00")) @[lsu_stbuf.scala 147:67] + node _T_292 = bits(store_byteen_lo_r, 0, 0) @[lsu_stbuf.scala 147:106] + node _T_293 = or(_T_291, _T_292) @[lsu_stbuf.scala 147:87] + node _T_294 = bits(io.store_datafn_lo_r, 7, 0) @[lsu_stbuf.scala 147:131] + node _T_295 = bits(stbuf_data[0], 7, 0) @[lsu_stbuf.scala 147:152] + node _T_296 = mux(_T_293, _T_294, _T_295) @[lsu_stbuf.scala 147:66] + node _T_297 = bits(stbuf_byteen[0], 0, 0) @[lsu_stbuf.scala 148:25] + node _T_298 = eq(_T_297, UInt<1>("h00")) @[lsu_stbuf.scala 148:9] + node _T_299 = bits(store_byteen_hi_r, 0, 0) @[lsu_stbuf.scala 148:48] + node _T_300 = or(_T_298, _T_299) @[lsu_stbuf.scala 148:29] + node _T_301 = bits(io.store_datafn_hi_r, 7, 0) @[lsu_stbuf.scala 148:73] + node _T_302 = bits(stbuf_data[0], 7, 0) @[lsu_stbuf.scala 148:94] + node _T_303 = mux(_T_300, _T_301, _T_302) @[lsu_stbuf.scala 148:8] + node _T_304 = mux(_T_289, _T_296, _T_303) @[lsu_stbuf.scala 147:51] + node _T_305 = bits(sel_lo, 1, 1) @[lsu_stbuf.scala 147:58] + node _T_306 = bits(stbuf_byteen[1], 0, 0) @[lsu_stbuf.scala 147:83] + node _T_307 = eq(_T_306, UInt<1>("h00")) @[lsu_stbuf.scala 147:67] + node _T_308 = bits(store_byteen_lo_r, 0, 0) @[lsu_stbuf.scala 147:106] + node _T_309 = or(_T_307, _T_308) @[lsu_stbuf.scala 147:87] + node _T_310 = bits(io.store_datafn_lo_r, 7, 0) @[lsu_stbuf.scala 147:131] + node _T_311 = bits(stbuf_data[1], 7, 0) @[lsu_stbuf.scala 147:152] + node _T_312 = mux(_T_309, _T_310, _T_311) @[lsu_stbuf.scala 147:66] + node _T_313 = bits(stbuf_byteen[1], 0, 0) @[lsu_stbuf.scala 148:25] + node _T_314 = eq(_T_313, UInt<1>("h00")) @[lsu_stbuf.scala 148:9] + node _T_315 = bits(store_byteen_hi_r, 0, 0) @[lsu_stbuf.scala 148:48] + node _T_316 = or(_T_314, _T_315) @[lsu_stbuf.scala 148:29] + node _T_317 = bits(io.store_datafn_hi_r, 7, 0) @[lsu_stbuf.scala 148:73] + node _T_318 = bits(stbuf_data[1], 7, 0) @[lsu_stbuf.scala 148:94] + node _T_319 = mux(_T_316, _T_317, _T_318) @[lsu_stbuf.scala 148:8] + node _T_320 = mux(_T_305, _T_312, _T_319) @[lsu_stbuf.scala 147:51] + node _T_321 = bits(sel_lo, 2, 2) @[lsu_stbuf.scala 147:58] + node _T_322 = bits(stbuf_byteen[2], 0, 0) @[lsu_stbuf.scala 147:83] + node _T_323 = eq(_T_322, UInt<1>("h00")) @[lsu_stbuf.scala 147:67] + node _T_324 = bits(store_byteen_lo_r, 0, 0) @[lsu_stbuf.scala 147:106] + node _T_325 = or(_T_323, _T_324) @[lsu_stbuf.scala 147:87] + node _T_326 = bits(io.store_datafn_lo_r, 7, 0) @[lsu_stbuf.scala 147:131] + node _T_327 = bits(stbuf_data[2], 7, 0) @[lsu_stbuf.scala 147:152] + node _T_328 = mux(_T_325, _T_326, _T_327) @[lsu_stbuf.scala 147:66] + node _T_329 = bits(stbuf_byteen[2], 0, 0) @[lsu_stbuf.scala 148:25] + node _T_330 = eq(_T_329, UInt<1>("h00")) @[lsu_stbuf.scala 148:9] + node _T_331 = bits(store_byteen_hi_r, 0, 0) @[lsu_stbuf.scala 148:48] + node _T_332 = or(_T_330, _T_331) @[lsu_stbuf.scala 148:29] + node _T_333 = bits(io.store_datafn_hi_r, 7, 0) @[lsu_stbuf.scala 148:73] + node _T_334 = bits(stbuf_data[2], 7, 0) @[lsu_stbuf.scala 148:94] + node _T_335 = mux(_T_332, _T_333, _T_334) @[lsu_stbuf.scala 148:8] + node _T_336 = mux(_T_321, _T_328, _T_335) @[lsu_stbuf.scala 147:51] + node _T_337 = bits(sel_lo, 3, 3) @[lsu_stbuf.scala 147:58] + node _T_338 = bits(stbuf_byteen[3], 0, 0) @[lsu_stbuf.scala 147:83] + node _T_339 = eq(_T_338, UInt<1>("h00")) @[lsu_stbuf.scala 147:67] + node _T_340 = bits(store_byteen_lo_r, 0, 0) @[lsu_stbuf.scala 147:106] + node _T_341 = or(_T_339, _T_340) @[lsu_stbuf.scala 147:87] + node _T_342 = bits(io.store_datafn_lo_r, 7, 0) @[lsu_stbuf.scala 147:131] + node _T_343 = bits(stbuf_data[3], 7, 0) @[lsu_stbuf.scala 147:152] + node _T_344 = mux(_T_341, _T_342, _T_343) @[lsu_stbuf.scala 147:66] + node _T_345 = bits(stbuf_byteen[3], 0, 0) @[lsu_stbuf.scala 148:25] + node _T_346 = eq(_T_345, UInt<1>("h00")) @[lsu_stbuf.scala 148:9] + node _T_347 = bits(store_byteen_hi_r, 0, 0) @[lsu_stbuf.scala 148:48] + node _T_348 = or(_T_346, _T_347) @[lsu_stbuf.scala 148:29] + node _T_349 = bits(io.store_datafn_hi_r, 7, 0) @[lsu_stbuf.scala 148:73] + node _T_350 = bits(stbuf_data[3], 7, 0) @[lsu_stbuf.scala 148:94] + node _T_351 = mux(_T_348, _T_349, _T_350) @[lsu_stbuf.scala 148:8] + node _T_352 = mux(_T_337, _T_344, _T_351) @[lsu_stbuf.scala 147:51] + datain1[0] <= _T_304 @[lsu_stbuf.scala 147:11] + datain1[1] <= _T_320 @[lsu_stbuf.scala 147:11] + datain1[2] <= _T_336 @[lsu_stbuf.scala 147:11] + datain1[3] <= _T_352 @[lsu_stbuf.scala 147:11] + node _T_353 = bits(sel_lo, 0, 0) @[lsu_stbuf.scala 150:59] + node _T_354 = bits(stbuf_byteen[0], 1, 1) @[lsu_stbuf.scala 150:84] + node _T_355 = eq(_T_354, UInt<1>("h00")) @[lsu_stbuf.scala 150:68] + node _T_356 = bits(store_byteen_lo_r, 1, 1) @[lsu_stbuf.scala 150:107] + node _T_357 = or(_T_355, _T_356) @[lsu_stbuf.scala 150:88] + node _T_358 = bits(io.store_datafn_lo_r, 15, 8) @[lsu_stbuf.scala 150:132] + node _T_359 = bits(stbuf_data[0], 15, 8) @[lsu_stbuf.scala 150:154] + node _T_360 = mux(_T_357, _T_358, _T_359) @[lsu_stbuf.scala 150:67] + node _T_361 = bits(stbuf_byteen[0], 1, 1) @[lsu_stbuf.scala 151:25] + node _T_362 = eq(_T_361, UInt<1>("h00")) @[lsu_stbuf.scala 151:9] + node _T_363 = bits(store_byteen_hi_r, 1, 1) @[lsu_stbuf.scala 151:48] + node _T_364 = or(_T_362, _T_363) @[lsu_stbuf.scala 151:29] + node _T_365 = bits(io.store_datafn_hi_r, 15, 8) @[lsu_stbuf.scala 151:73] + node _T_366 = bits(stbuf_data[0], 15, 8) @[lsu_stbuf.scala 151:95] + node _T_367 = mux(_T_364, _T_365, _T_366) @[lsu_stbuf.scala 151:8] + node _T_368 = mux(_T_353, _T_360, _T_367) @[lsu_stbuf.scala 150:52] + node _T_369 = bits(sel_lo, 1, 1) @[lsu_stbuf.scala 150:59] + node _T_370 = bits(stbuf_byteen[1], 1, 1) @[lsu_stbuf.scala 150:84] + node _T_371 = eq(_T_370, UInt<1>("h00")) @[lsu_stbuf.scala 150:68] + node _T_372 = bits(store_byteen_lo_r, 1, 1) @[lsu_stbuf.scala 150:107] + node _T_373 = or(_T_371, _T_372) @[lsu_stbuf.scala 150:88] + node _T_374 = bits(io.store_datafn_lo_r, 15, 8) @[lsu_stbuf.scala 150:132] + node _T_375 = bits(stbuf_data[1], 15, 8) @[lsu_stbuf.scala 150:154] + node _T_376 = mux(_T_373, _T_374, _T_375) @[lsu_stbuf.scala 150:67] + node _T_377 = bits(stbuf_byteen[1], 1, 1) @[lsu_stbuf.scala 151:25] + node _T_378 = eq(_T_377, UInt<1>("h00")) @[lsu_stbuf.scala 151:9] + node _T_379 = bits(store_byteen_hi_r, 1, 1) @[lsu_stbuf.scala 151:48] + node _T_380 = or(_T_378, _T_379) @[lsu_stbuf.scala 151:29] + node _T_381 = bits(io.store_datafn_hi_r, 15, 8) @[lsu_stbuf.scala 151:73] + node _T_382 = bits(stbuf_data[1], 15, 8) @[lsu_stbuf.scala 151:95] + node _T_383 = mux(_T_380, _T_381, _T_382) @[lsu_stbuf.scala 151:8] + node _T_384 = mux(_T_369, _T_376, _T_383) @[lsu_stbuf.scala 150:52] + node _T_385 = bits(sel_lo, 2, 2) @[lsu_stbuf.scala 150:59] + node _T_386 = bits(stbuf_byteen[2], 1, 1) @[lsu_stbuf.scala 150:84] + node _T_387 = eq(_T_386, UInt<1>("h00")) @[lsu_stbuf.scala 150:68] + node _T_388 = bits(store_byteen_lo_r, 1, 1) @[lsu_stbuf.scala 150:107] + node _T_389 = or(_T_387, _T_388) @[lsu_stbuf.scala 150:88] + node _T_390 = bits(io.store_datafn_lo_r, 15, 8) @[lsu_stbuf.scala 150:132] + node _T_391 = bits(stbuf_data[2], 15, 8) @[lsu_stbuf.scala 150:154] + node _T_392 = mux(_T_389, _T_390, _T_391) @[lsu_stbuf.scala 150:67] + node _T_393 = bits(stbuf_byteen[2], 1, 1) @[lsu_stbuf.scala 151:25] + node _T_394 = eq(_T_393, UInt<1>("h00")) @[lsu_stbuf.scala 151:9] + node _T_395 = bits(store_byteen_hi_r, 1, 1) @[lsu_stbuf.scala 151:48] + node _T_396 = or(_T_394, _T_395) @[lsu_stbuf.scala 151:29] + node _T_397 = bits(io.store_datafn_hi_r, 15, 8) @[lsu_stbuf.scala 151:73] + node _T_398 = bits(stbuf_data[2], 15, 8) @[lsu_stbuf.scala 151:95] + node _T_399 = mux(_T_396, _T_397, _T_398) @[lsu_stbuf.scala 151:8] + node _T_400 = mux(_T_385, _T_392, _T_399) @[lsu_stbuf.scala 150:52] + node _T_401 = bits(sel_lo, 3, 3) @[lsu_stbuf.scala 150:59] + node _T_402 = bits(stbuf_byteen[3], 1, 1) @[lsu_stbuf.scala 150:84] + node _T_403 = eq(_T_402, UInt<1>("h00")) @[lsu_stbuf.scala 150:68] + node _T_404 = bits(store_byteen_lo_r, 1, 1) @[lsu_stbuf.scala 150:107] + node _T_405 = or(_T_403, _T_404) @[lsu_stbuf.scala 150:88] + node _T_406 = bits(io.store_datafn_lo_r, 15, 8) @[lsu_stbuf.scala 150:132] + node _T_407 = bits(stbuf_data[3], 15, 8) @[lsu_stbuf.scala 150:154] + node _T_408 = mux(_T_405, _T_406, _T_407) @[lsu_stbuf.scala 150:67] + node _T_409 = bits(stbuf_byteen[3], 1, 1) @[lsu_stbuf.scala 151:25] + node _T_410 = eq(_T_409, UInt<1>("h00")) @[lsu_stbuf.scala 151:9] + node _T_411 = bits(store_byteen_hi_r, 1, 1) @[lsu_stbuf.scala 151:48] + node _T_412 = or(_T_410, _T_411) @[lsu_stbuf.scala 151:29] + node _T_413 = bits(io.store_datafn_hi_r, 15, 8) @[lsu_stbuf.scala 151:73] + node _T_414 = bits(stbuf_data[3], 15, 8) @[lsu_stbuf.scala 151:95] + node _T_415 = mux(_T_412, _T_413, _T_414) @[lsu_stbuf.scala 151:8] + node _T_416 = mux(_T_401, _T_408, _T_415) @[lsu_stbuf.scala 150:52] + datain2[0] <= _T_368 @[lsu_stbuf.scala 150:12] + datain2[1] <= _T_384 @[lsu_stbuf.scala 150:12] + datain2[2] <= _T_400 @[lsu_stbuf.scala 150:12] + datain2[3] <= _T_416 @[lsu_stbuf.scala 150:12] + node _T_417 = bits(sel_lo, 0, 0) @[lsu_stbuf.scala 153:59] + node _T_418 = bits(stbuf_byteen[0], 2, 2) @[lsu_stbuf.scala 153:84] + node _T_419 = eq(_T_418, UInt<1>("h00")) @[lsu_stbuf.scala 153:68] + node _T_420 = bits(store_byteen_lo_r, 2, 2) @[lsu_stbuf.scala 153:107] + node _T_421 = or(_T_419, _T_420) @[lsu_stbuf.scala 153:88] + node _T_422 = bits(io.store_datafn_lo_r, 23, 16) @[lsu_stbuf.scala 153:132] + node _T_423 = bits(stbuf_data[0], 23, 16) @[lsu_stbuf.scala 153:155] + node _T_424 = mux(_T_421, _T_422, _T_423) @[lsu_stbuf.scala 153:67] + node _T_425 = bits(stbuf_byteen[0], 2, 2) @[lsu_stbuf.scala 154:25] + node _T_426 = eq(_T_425, UInt<1>("h00")) @[lsu_stbuf.scala 154:9] + node _T_427 = bits(store_byteen_hi_r, 2, 2) @[lsu_stbuf.scala 154:48] + node _T_428 = or(_T_426, _T_427) @[lsu_stbuf.scala 154:29] + node _T_429 = bits(io.store_datafn_hi_r, 23, 16) @[lsu_stbuf.scala 154:73] + node _T_430 = bits(stbuf_data[0], 23, 16) @[lsu_stbuf.scala 154:96] + node _T_431 = mux(_T_428, _T_429, _T_430) @[lsu_stbuf.scala 154:8] + node _T_432 = mux(_T_417, _T_424, _T_431) @[lsu_stbuf.scala 153:52] + node _T_433 = bits(sel_lo, 1, 1) @[lsu_stbuf.scala 153:59] + node _T_434 = bits(stbuf_byteen[1], 2, 2) @[lsu_stbuf.scala 153:84] + node _T_435 = eq(_T_434, UInt<1>("h00")) @[lsu_stbuf.scala 153:68] + node _T_436 = bits(store_byteen_lo_r, 2, 2) @[lsu_stbuf.scala 153:107] + node _T_437 = or(_T_435, _T_436) @[lsu_stbuf.scala 153:88] + node _T_438 = bits(io.store_datafn_lo_r, 23, 16) @[lsu_stbuf.scala 153:132] + node _T_439 = bits(stbuf_data[1], 23, 16) @[lsu_stbuf.scala 153:155] + node _T_440 = mux(_T_437, _T_438, _T_439) @[lsu_stbuf.scala 153:67] + node _T_441 = bits(stbuf_byteen[1], 2, 2) @[lsu_stbuf.scala 154:25] + node _T_442 = eq(_T_441, UInt<1>("h00")) @[lsu_stbuf.scala 154:9] + node _T_443 = bits(store_byteen_hi_r, 2, 2) @[lsu_stbuf.scala 154:48] + node _T_444 = or(_T_442, _T_443) @[lsu_stbuf.scala 154:29] + node _T_445 = bits(io.store_datafn_hi_r, 23, 16) @[lsu_stbuf.scala 154:73] + node _T_446 = bits(stbuf_data[1], 23, 16) @[lsu_stbuf.scala 154:96] + node _T_447 = mux(_T_444, _T_445, _T_446) @[lsu_stbuf.scala 154:8] + node _T_448 = mux(_T_433, _T_440, _T_447) @[lsu_stbuf.scala 153:52] + node _T_449 = bits(sel_lo, 2, 2) @[lsu_stbuf.scala 153:59] + node _T_450 = bits(stbuf_byteen[2], 2, 2) @[lsu_stbuf.scala 153:84] + node _T_451 = eq(_T_450, UInt<1>("h00")) @[lsu_stbuf.scala 153:68] + node _T_452 = bits(store_byteen_lo_r, 2, 2) @[lsu_stbuf.scala 153:107] + node _T_453 = or(_T_451, _T_452) @[lsu_stbuf.scala 153:88] + node _T_454 = bits(io.store_datafn_lo_r, 23, 16) @[lsu_stbuf.scala 153:132] + node _T_455 = bits(stbuf_data[2], 23, 16) @[lsu_stbuf.scala 153:155] + node _T_456 = mux(_T_453, _T_454, _T_455) @[lsu_stbuf.scala 153:67] + node _T_457 = bits(stbuf_byteen[2], 2, 2) @[lsu_stbuf.scala 154:25] + node _T_458 = eq(_T_457, UInt<1>("h00")) @[lsu_stbuf.scala 154:9] + node _T_459 = bits(store_byteen_hi_r, 2, 2) @[lsu_stbuf.scala 154:48] + node _T_460 = or(_T_458, _T_459) @[lsu_stbuf.scala 154:29] + node _T_461 = bits(io.store_datafn_hi_r, 23, 16) @[lsu_stbuf.scala 154:73] + node _T_462 = bits(stbuf_data[2], 23, 16) @[lsu_stbuf.scala 154:96] + node _T_463 = mux(_T_460, _T_461, _T_462) @[lsu_stbuf.scala 154:8] + node _T_464 = mux(_T_449, _T_456, _T_463) @[lsu_stbuf.scala 153:52] + node _T_465 = bits(sel_lo, 3, 3) @[lsu_stbuf.scala 153:59] + node _T_466 = bits(stbuf_byteen[3], 2, 2) @[lsu_stbuf.scala 153:84] + node _T_467 = eq(_T_466, UInt<1>("h00")) @[lsu_stbuf.scala 153:68] + node _T_468 = bits(store_byteen_lo_r, 2, 2) @[lsu_stbuf.scala 153:107] + node _T_469 = or(_T_467, _T_468) @[lsu_stbuf.scala 153:88] + node _T_470 = bits(io.store_datafn_lo_r, 23, 16) @[lsu_stbuf.scala 153:132] + node _T_471 = bits(stbuf_data[3], 23, 16) @[lsu_stbuf.scala 153:155] + node _T_472 = mux(_T_469, _T_470, _T_471) @[lsu_stbuf.scala 153:67] + node _T_473 = bits(stbuf_byteen[3], 2, 2) @[lsu_stbuf.scala 154:25] + node _T_474 = eq(_T_473, UInt<1>("h00")) @[lsu_stbuf.scala 154:9] + node _T_475 = bits(store_byteen_hi_r, 2, 2) @[lsu_stbuf.scala 154:48] + node _T_476 = or(_T_474, _T_475) @[lsu_stbuf.scala 154:29] + node _T_477 = bits(io.store_datafn_hi_r, 23, 16) @[lsu_stbuf.scala 154:73] + node _T_478 = bits(stbuf_data[3], 23, 16) @[lsu_stbuf.scala 154:96] + node _T_479 = mux(_T_476, _T_477, _T_478) @[lsu_stbuf.scala 154:8] + node _T_480 = mux(_T_465, _T_472, _T_479) @[lsu_stbuf.scala 153:52] + datain3[0] <= _T_432 @[lsu_stbuf.scala 153:12] + datain3[1] <= _T_448 @[lsu_stbuf.scala 153:12] + datain3[2] <= _T_464 @[lsu_stbuf.scala 153:12] + datain3[3] <= _T_480 @[lsu_stbuf.scala 153:12] + node _T_481 = bits(sel_lo, 0, 0) @[lsu_stbuf.scala 156:59] + node _T_482 = bits(stbuf_byteen[0], 3, 3) @[lsu_stbuf.scala 156:84] + node _T_483 = eq(_T_482, UInt<1>("h00")) @[lsu_stbuf.scala 156:68] + node _T_484 = bits(store_byteen_lo_r, 3, 3) @[lsu_stbuf.scala 156:107] + node _T_485 = or(_T_483, _T_484) @[lsu_stbuf.scala 156:88] + node _T_486 = bits(io.store_datafn_lo_r, 31, 24) @[lsu_stbuf.scala 156:132] + node _T_487 = bits(stbuf_data[0], 31, 24) @[lsu_stbuf.scala 156:155] + node _T_488 = mux(_T_485, _T_486, _T_487) @[lsu_stbuf.scala 156:67] + node _T_489 = bits(stbuf_byteen[0], 3, 3) @[lsu_stbuf.scala 157:25] + node _T_490 = eq(_T_489, UInt<1>("h00")) @[lsu_stbuf.scala 157:9] + node _T_491 = bits(store_byteen_hi_r, 3, 3) @[lsu_stbuf.scala 157:48] + node _T_492 = or(_T_490, _T_491) @[lsu_stbuf.scala 157:29] + node _T_493 = bits(io.store_datafn_hi_r, 31, 24) @[lsu_stbuf.scala 157:73] + node _T_494 = bits(stbuf_data[0], 31, 24) @[lsu_stbuf.scala 157:96] + node _T_495 = mux(_T_492, _T_493, _T_494) @[lsu_stbuf.scala 157:8] + node _T_496 = mux(_T_481, _T_488, _T_495) @[lsu_stbuf.scala 156:52] + node _T_497 = bits(sel_lo, 1, 1) @[lsu_stbuf.scala 156:59] + node _T_498 = bits(stbuf_byteen[1], 3, 3) @[lsu_stbuf.scala 156:84] + node _T_499 = eq(_T_498, UInt<1>("h00")) @[lsu_stbuf.scala 156:68] + node _T_500 = bits(store_byteen_lo_r, 3, 3) @[lsu_stbuf.scala 156:107] + node _T_501 = or(_T_499, _T_500) @[lsu_stbuf.scala 156:88] + node _T_502 = bits(io.store_datafn_lo_r, 31, 24) @[lsu_stbuf.scala 156:132] + node _T_503 = bits(stbuf_data[1], 31, 24) @[lsu_stbuf.scala 156:155] + node _T_504 = mux(_T_501, _T_502, _T_503) @[lsu_stbuf.scala 156:67] + node _T_505 = bits(stbuf_byteen[1], 3, 3) @[lsu_stbuf.scala 157:25] + node _T_506 = eq(_T_505, UInt<1>("h00")) @[lsu_stbuf.scala 157:9] + node _T_507 = bits(store_byteen_hi_r, 3, 3) @[lsu_stbuf.scala 157:48] + node _T_508 = or(_T_506, _T_507) @[lsu_stbuf.scala 157:29] + node _T_509 = bits(io.store_datafn_hi_r, 31, 24) @[lsu_stbuf.scala 157:73] + node _T_510 = bits(stbuf_data[1], 31, 24) @[lsu_stbuf.scala 157:96] + node _T_511 = mux(_T_508, _T_509, _T_510) @[lsu_stbuf.scala 157:8] + node _T_512 = mux(_T_497, _T_504, _T_511) @[lsu_stbuf.scala 156:52] + node _T_513 = bits(sel_lo, 2, 2) @[lsu_stbuf.scala 156:59] + node _T_514 = bits(stbuf_byteen[2], 3, 3) @[lsu_stbuf.scala 156:84] + node _T_515 = eq(_T_514, UInt<1>("h00")) @[lsu_stbuf.scala 156:68] + node _T_516 = bits(store_byteen_lo_r, 3, 3) @[lsu_stbuf.scala 156:107] + node _T_517 = or(_T_515, _T_516) @[lsu_stbuf.scala 156:88] + node _T_518 = bits(io.store_datafn_lo_r, 31, 24) @[lsu_stbuf.scala 156:132] + node _T_519 = bits(stbuf_data[2], 31, 24) @[lsu_stbuf.scala 156:155] + node _T_520 = mux(_T_517, _T_518, _T_519) @[lsu_stbuf.scala 156:67] + node _T_521 = bits(stbuf_byteen[2], 3, 3) @[lsu_stbuf.scala 157:25] + node _T_522 = eq(_T_521, UInt<1>("h00")) @[lsu_stbuf.scala 157:9] + node _T_523 = bits(store_byteen_hi_r, 3, 3) @[lsu_stbuf.scala 157:48] + node _T_524 = or(_T_522, _T_523) @[lsu_stbuf.scala 157:29] + node _T_525 = bits(io.store_datafn_hi_r, 31, 24) @[lsu_stbuf.scala 157:73] + node _T_526 = bits(stbuf_data[2], 31, 24) @[lsu_stbuf.scala 157:96] + node _T_527 = mux(_T_524, _T_525, _T_526) @[lsu_stbuf.scala 157:8] + node _T_528 = mux(_T_513, _T_520, _T_527) @[lsu_stbuf.scala 156:52] + node _T_529 = bits(sel_lo, 3, 3) @[lsu_stbuf.scala 156:59] + node _T_530 = bits(stbuf_byteen[3], 3, 3) @[lsu_stbuf.scala 156:84] + node _T_531 = eq(_T_530, UInt<1>("h00")) @[lsu_stbuf.scala 156:68] + node _T_532 = bits(store_byteen_lo_r, 3, 3) @[lsu_stbuf.scala 156:107] + node _T_533 = or(_T_531, _T_532) @[lsu_stbuf.scala 156:88] + node _T_534 = bits(io.store_datafn_lo_r, 31, 24) @[lsu_stbuf.scala 156:132] + node _T_535 = bits(stbuf_data[3], 31, 24) @[lsu_stbuf.scala 156:155] + node _T_536 = mux(_T_533, _T_534, _T_535) @[lsu_stbuf.scala 156:67] + node _T_537 = bits(stbuf_byteen[3], 3, 3) @[lsu_stbuf.scala 157:25] + node _T_538 = eq(_T_537, UInt<1>("h00")) @[lsu_stbuf.scala 157:9] + node _T_539 = bits(store_byteen_hi_r, 3, 3) @[lsu_stbuf.scala 157:48] + node _T_540 = or(_T_538, _T_539) @[lsu_stbuf.scala 157:29] + node _T_541 = bits(io.store_datafn_hi_r, 31, 24) @[lsu_stbuf.scala 157:73] + node _T_542 = bits(stbuf_data[3], 31, 24) @[lsu_stbuf.scala 157:96] + node _T_543 = mux(_T_540, _T_541, _T_542) @[lsu_stbuf.scala 157:8] + node _T_544 = mux(_T_529, _T_536, _T_543) @[lsu_stbuf.scala 156:52] + datain4[0] <= _T_496 @[lsu_stbuf.scala 156:12] + datain4[1] <= _T_512 @[lsu_stbuf.scala 156:12] + datain4[2] <= _T_528 @[lsu_stbuf.scala 156:12] + datain4[3] <= _T_544 @[lsu_stbuf.scala 156:12] + node _T_545 = cat(datain2[0], datain1[0]) @[Cat.scala 29:58] + node _T_546 = cat(datain4[0], datain3[0]) @[Cat.scala 29:58] + node _T_547 = cat(_T_546, _T_545) @[Cat.scala 29:58] + node _T_548 = cat(datain2[1], datain1[1]) @[Cat.scala 29:58] + node _T_549 = cat(datain4[1], datain3[1]) @[Cat.scala 29:58] + node _T_550 = cat(_T_549, _T_548) @[Cat.scala 29:58] + node _T_551 = cat(datain2[2], datain1[2]) @[Cat.scala 29:58] + node _T_552 = cat(datain4[2], datain3[2]) @[Cat.scala 29:58] + node _T_553 = cat(_T_552, _T_551) @[Cat.scala 29:58] + node _T_554 = cat(datain2[3], datain1[3]) @[Cat.scala 29:58] + node _T_555 = cat(datain4[3], datain3[3]) @[Cat.scala 29:58] + node _T_556 = cat(_T_555, _T_554) @[Cat.scala 29:58] + stbuf_datain[0] <= _T_547 @[lsu_stbuf.scala 159:16] + stbuf_datain[1] <= _T_550 @[lsu_stbuf.scala 159:16] + stbuf_datain[2] <= _T_553 @[lsu_stbuf.scala 159:16] + stbuf_datain[3] <= _T_556 @[lsu_stbuf.scala 159:16] + node _T_557 = bits(stbuf_wr_en, 0, 0) @[lsu_stbuf.scala 163:104] + node _T_558 = bits(_T_557, 0, 0) @[lsu_stbuf.scala 163:114] + node _T_559 = bits(stbuf_vld, 0, 0) @[lsu_stbuf.scala 163:131] + node _T_560 = mux(_T_558, UInt<1>("h01"), _T_559) @[lsu_stbuf.scala 163:92] + node _T_561 = bits(stbuf_reset, 0, 0) @[lsu_stbuf.scala 163:150] + node _T_562 = eq(_T_561, UInt<1>("h00")) @[lsu_stbuf.scala 163:138] + node _T_563 = and(_T_560, _T_562) @[lsu_stbuf.scala 163:136] + reg _T_564 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_stbuf.scala 163:88] + _T_564 <= _T_563 @[lsu_stbuf.scala 163:88] + node _T_565 = bits(stbuf_wr_en, 1, 1) @[lsu_stbuf.scala 163:104] + node _T_566 = bits(_T_565, 0, 0) @[lsu_stbuf.scala 163:114] + node _T_567 = bits(stbuf_vld, 1, 1) @[lsu_stbuf.scala 163:131] + node _T_568 = mux(_T_566, UInt<1>("h01"), _T_567) @[lsu_stbuf.scala 163:92] + node _T_569 = bits(stbuf_reset, 1, 1) @[lsu_stbuf.scala 163:150] + node _T_570 = eq(_T_569, UInt<1>("h00")) @[lsu_stbuf.scala 163:138] + node _T_571 = and(_T_568, _T_570) @[lsu_stbuf.scala 163:136] + reg _T_572 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_stbuf.scala 163:88] + _T_572 <= _T_571 @[lsu_stbuf.scala 163:88] + node _T_573 = bits(stbuf_wr_en, 2, 2) @[lsu_stbuf.scala 163:104] + node _T_574 = bits(_T_573, 0, 0) @[lsu_stbuf.scala 163:114] + node _T_575 = bits(stbuf_vld, 2, 2) @[lsu_stbuf.scala 163:131] + node _T_576 = mux(_T_574, UInt<1>("h01"), _T_575) @[lsu_stbuf.scala 163:92] + node _T_577 = bits(stbuf_reset, 2, 2) @[lsu_stbuf.scala 163:150] + node _T_578 = eq(_T_577, UInt<1>("h00")) @[lsu_stbuf.scala 163:138] + node _T_579 = and(_T_576, _T_578) @[lsu_stbuf.scala 163:136] + reg _T_580 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_stbuf.scala 163:88] + _T_580 <= _T_579 @[lsu_stbuf.scala 163:88] + node _T_581 = bits(stbuf_wr_en, 3, 3) @[lsu_stbuf.scala 163:104] + node _T_582 = bits(_T_581, 0, 0) @[lsu_stbuf.scala 163:114] + node _T_583 = bits(stbuf_vld, 3, 3) @[lsu_stbuf.scala 163:131] + node _T_584 = mux(_T_582, UInt<1>("h01"), _T_583) @[lsu_stbuf.scala 163:92] + node _T_585 = bits(stbuf_reset, 3, 3) @[lsu_stbuf.scala 163:150] + node _T_586 = eq(_T_585, UInt<1>("h00")) @[lsu_stbuf.scala 163:138] + node _T_587 = and(_T_584, _T_586) @[lsu_stbuf.scala 163:136] + reg _T_588 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_stbuf.scala 163:88] + _T_588 <= _T_587 @[lsu_stbuf.scala 163:88] + node _T_589 = cat(_T_588, _T_580) @[Cat.scala 29:58] + node _T_590 = cat(_T_589, _T_572) @[Cat.scala 29:58] + node _T_591 = cat(_T_590, _T_564) @[Cat.scala 29:58] + stbuf_vld <= _T_591 @[lsu_stbuf.scala 163:13] + node _T_592 = bits(stbuf_dma_kill_en, 0, 0) @[lsu_stbuf.scala 164:114] + node _T_593 = bits(_T_592, 0, 0) @[lsu_stbuf.scala 164:118] + node _T_594 = bits(stbuf_dma_kill, 0, 0) @[lsu_stbuf.scala 164:144] + node _T_595 = mux(_T_593, UInt<1>("h01"), _T_594) @[lsu_stbuf.scala 164:96] + node _T_596 = bits(stbuf_reset, 0, 0) @[lsu_stbuf.scala 164:163] + node _T_597 = eq(_T_596, UInt<1>("h00")) @[lsu_stbuf.scala 164:151] + node _T_598 = and(_T_595, _T_597) @[lsu_stbuf.scala 164:149] + reg _T_599 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_stbuf.scala 164:92] + _T_599 <= _T_598 @[lsu_stbuf.scala 164:92] + node _T_600 = bits(stbuf_dma_kill_en, 1, 1) @[lsu_stbuf.scala 164:114] + node _T_601 = bits(_T_600, 0, 0) @[lsu_stbuf.scala 164:118] + node _T_602 = bits(stbuf_dma_kill, 1, 1) @[lsu_stbuf.scala 164:144] + node _T_603 = mux(_T_601, UInt<1>("h01"), _T_602) @[lsu_stbuf.scala 164:96] + node _T_604 = bits(stbuf_reset, 1, 1) @[lsu_stbuf.scala 164:163] + node _T_605 = eq(_T_604, UInt<1>("h00")) @[lsu_stbuf.scala 164:151] + node _T_606 = and(_T_603, _T_605) @[lsu_stbuf.scala 164:149] + reg _T_607 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_stbuf.scala 164:92] + _T_607 <= _T_606 @[lsu_stbuf.scala 164:92] + node _T_608 = bits(stbuf_dma_kill_en, 2, 2) @[lsu_stbuf.scala 164:114] + node _T_609 = bits(_T_608, 0, 0) @[lsu_stbuf.scala 164:118] + node _T_610 = bits(stbuf_dma_kill, 2, 2) @[lsu_stbuf.scala 164:144] + node _T_611 = mux(_T_609, UInt<1>("h01"), _T_610) @[lsu_stbuf.scala 164:96] + node _T_612 = bits(stbuf_reset, 2, 2) @[lsu_stbuf.scala 164:163] + node _T_613 = eq(_T_612, UInt<1>("h00")) @[lsu_stbuf.scala 164:151] + node _T_614 = and(_T_611, _T_613) @[lsu_stbuf.scala 164:149] + reg _T_615 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_stbuf.scala 164:92] + _T_615 <= _T_614 @[lsu_stbuf.scala 164:92] + node _T_616 = bits(stbuf_dma_kill_en, 3, 3) @[lsu_stbuf.scala 164:114] + node _T_617 = bits(_T_616, 0, 0) @[lsu_stbuf.scala 164:118] + node _T_618 = bits(stbuf_dma_kill, 3, 3) @[lsu_stbuf.scala 164:144] + node _T_619 = mux(_T_617, UInt<1>("h01"), _T_618) @[lsu_stbuf.scala 164:96] + node _T_620 = bits(stbuf_reset, 3, 3) @[lsu_stbuf.scala 164:163] + node _T_621 = eq(_T_620, UInt<1>("h00")) @[lsu_stbuf.scala 164:151] + node _T_622 = and(_T_619, _T_621) @[lsu_stbuf.scala 164:149] + reg _T_623 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_stbuf.scala 164:92] + _T_623 <= _T_622 @[lsu_stbuf.scala 164:92] + node _T_624 = cat(_T_623, _T_615) @[Cat.scala 29:58] + node _T_625 = cat(_T_624, _T_607) @[Cat.scala 29:58] + node _T_626 = cat(_T_625, _T_599) @[Cat.scala 29:58] + stbuf_dma_kill <= _T_626 @[lsu_stbuf.scala 164:18] + node _T_627 = bits(stbuf_wr_en, 0, 0) @[lsu_stbuf.scala 165:108] + node _T_628 = bits(_T_627, 0, 0) @[lsu_stbuf.scala 165:118] + node _T_629 = mux(_T_628, stbuf_byteenin[0], stbuf_byteen[0]) @[lsu_stbuf.scala 165:96] + node _T_630 = bits(stbuf_reset, 0, 0) @[lsu_stbuf.scala 165:206] + node _T_631 = eq(_T_630, UInt<1>("h00")) @[lsu_stbuf.scala 165:194] + node _T_632 = bits(_T_631, 0, 0) @[Bitwise.scala 72:15] + node _T_633 = mux(_T_632, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_634 = and(_T_629, _T_633) @[lsu_stbuf.scala 165:158] + reg _T_635 : UInt, io.lsu_stbuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_stbuf.scala 165:92] + _T_635 <= _T_634 @[lsu_stbuf.scala 165:92] + node _T_636 = bits(stbuf_wr_en, 1, 1) @[lsu_stbuf.scala 165:108] + node _T_637 = bits(_T_636, 0, 0) @[lsu_stbuf.scala 165:118] + node _T_638 = mux(_T_637, stbuf_byteenin[1], stbuf_byteen[1]) @[lsu_stbuf.scala 165:96] + node _T_639 = bits(stbuf_reset, 1, 1) @[lsu_stbuf.scala 165:206] + node _T_640 = eq(_T_639, UInt<1>("h00")) @[lsu_stbuf.scala 165:194] + node _T_641 = bits(_T_640, 0, 0) @[Bitwise.scala 72:15] + node _T_642 = mux(_T_641, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_643 = and(_T_638, _T_642) @[lsu_stbuf.scala 165:158] + reg _T_644 : UInt, io.lsu_stbuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_stbuf.scala 165:92] + _T_644 <= _T_643 @[lsu_stbuf.scala 165:92] + node _T_645 = bits(stbuf_wr_en, 2, 2) @[lsu_stbuf.scala 165:108] + node _T_646 = bits(_T_645, 0, 0) @[lsu_stbuf.scala 165:118] + node _T_647 = mux(_T_646, stbuf_byteenin[2], stbuf_byteen[2]) @[lsu_stbuf.scala 165:96] + node _T_648 = bits(stbuf_reset, 2, 2) @[lsu_stbuf.scala 165:206] + node _T_649 = eq(_T_648, UInt<1>("h00")) @[lsu_stbuf.scala 165:194] + node _T_650 = bits(_T_649, 0, 0) @[Bitwise.scala 72:15] + node _T_651 = mux(_T_650, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_652 = and(_T_647, _T_651) @[lsu_stbuf.scala 165:158] + reg _T_653 : UInt, io.lsu_stbuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_stbuf.scala 165:92] + _T_653 <= _T_652 @[lsu_stbuf.scala 165:92] + node _T_654 = bits(stbuf_wr_en, 3, 3) @[lsu_stbuf.scala 165:108] + node _T_655 = bits(_T_654, 0, 0) @[lsu_stbuf.scala 165:118] + node _T_656 = mux(_T_655, stbuf_byteenin[3], stbuf_byteen[3]) @[lsu_stbuf.scala 165:96] + node _T_657 = bits(stbuf_reset, 3, 3) @[lsu_stbuf.scala 165:206] + node _T_658 = eq(_T_657, UInt<1>("h00")) @[lsu_stbuf.scala 165:194] + node _T_659 = bits(_T_658, 0, 0) @[Bitwise.scala 72:15] + node _T_660 = mux(_T_659, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_661 = and(_T_656, _T_660) @[lsu_stbuf.scala 165:158] + reg _T_662 : UInt, io.lsu_stbuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_stbuf.scala 165:92] + _T_662 <= _T_661 @[lsu_stbuf.scala 165:92] + stbuf_byteen[0] <= _T_635 @[lsu_stbuf.scala 165:16] + stbuf_byteen[1] <= _T_644 @[lsu_stbuf.scala 165:16] + stbuf_byteen[2] <= _T_653 @[lsu_stbuf.scala 165:16] + stbuf_byteen[3] <= _T_662 @[lsu_stbuf.scala 165:16] + node _T_663 = bits(stbuf_wr_en, 0, 0) @[lsu_stbuf.scala 167:56] + node _T_664 = bits(_T_663, 0, 0) @[lsu_stbuf.scala 167:66] + inst rvclkhdr of rvclkhdr_2 @[lib.scala 368:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[lib.scala 370:18] + rvclkhdr.io.en <= _T_664 @[lib.scala 371:17] + rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_665 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_665 <= stbuf_addrin[0] @[lib.scala 374:16] + stbuf_addr[0] <= _T_665 @[lsu_stbuf.scala 167:19] + node _T_666 = bits(stbuf_wr_en, 0, 0) @[lsu_stbuf.scala 168:56] + node _T_667 = bits(_T_666, 0, 0) @[lsu_stbuf.scala 168:66] + inst rvclkhdr_1 of rvclkhdr_3 @[lib.scala 368:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_1.io.en <= _T_667 @[lib.scala 371:17] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_668 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_668 <= stbuf_datain[0] @[lib.scala 374:16] + stbuf_data[0] <= _T_668 @[lsu_stbuf.scala 168:19] + node _T_669 = bits(stbuf_wr_en, 1, 1) @[lsu_stbuf.scala 167:56] + node _T_670 = bits(_T_669, 0, 0) @[lsu_stbuf.scala 167:66] + inst rvclkhdr_2 of rvclkhdr_4 @[lib.scala 368:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_2.io.en <= _T_670 @[lib.scala 371:17] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_671 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_671 <= stbuf_addrin[1] @[lib.scala 374:16] + stbuf_addr[1] <= _T_671 @[lsu_stbuf.scala 167:19] + node _T_672 = bits(stbuf_wr_en, 1, 1) @[lsu_stbuf.scala 168:56] + node _T_673 = bits(_T_672, 0, 0) @[lsu_stbuf.scala 168:66] + inst rvclkhdr_3 of rvclkhdr_5 @[lib.scala 368:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_3.io.en <= _T_673 @[lib.scala 371:17] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_674 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_674 <= stbuf_datain[1] @[lib.scala 374:16] + stbuf_data[1] <= _T_674 @[lsu_stbuf.scala 168:19] + node _T_675 = bits(stbuf_wr_en, 2, 2) @[lsu_stbuf.scala 167:56] + node _T_676 = bits(_T_675, 0, 0) @[lsu_stbuf.scala 167:66] + inst rvclkhdr_4 of rvclkhdr_6 @[lib.scala 368:23] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= reset + rvclkhdr_4.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_4.io.en <= _T_676 @[lib.scala 371:17] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_677 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_677 <= stbuf_addrin[2] @[lib.scala 374:16] + stbuf_addr[2] <= _T_677 @[lsu_stbuf.scala 167:19] + node _T_678 = bits(stbuf_wr_en, 2, 2) @[lsu_stbuf.scala 168:56] + node _T_679 = bits(_T_678, 0, 0) @[lsu_stbuf.scala 168:66] + inst rvclkhdr_5 of rvclkhdr_7 @[lib.scala 368:23] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= reset + rvclkhdr_5.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_5.io.en <= _T_679 @[lib.scala 371:17] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_680 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_680 <= stbuf_datain[2] @[lib.scala 374:16] + stbuf_data[2] <= _T_680 @[lsu_stbuf.scala 168:19] + node _T_681 = bits(stbuf_wr_en, 3, 3) @[lsu_stbuf.scala 167:56] + node _T_682 = bits(_T_681, 0, 0) @[lsu_stbuf.scala 167:66] + inst rvclkhdr_6 of rvclkhdr_8 @[lib.scala 368:23] + rvclkhdr_6.clock <= clock + rvclkhdr_6.reset <= reset + rvclkhdr_6.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_6.io.en <= _T_682 @[lib.scala 371:17] + rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_683 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_683 <= stbuf_addrin[3] @[lib.scala 374:16] + stbuf_addr[3] <= _T_683 @[lsu_stbuf.scala 167:19] + node _T_684 = bits(stbuf_wr_en, 3, 3) @[lsu_stbuf.scala 168:56] + node _T_685 = bits(_T_684, 0, 0) @[lsu_stbuf.scala 168:66] + inst rvclkhdr_7 of rvclkhdr_9 @[lib.scala 368:23] + rvclkhdr_7.clock <= clock + rvclkhdr_7.reset <= reset + rvclkhdr_7.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_7.io.en <= _T_685 @[lib.scala 371:17] + rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_686 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_686 <= stbuf_datain[3] @[lib.scala 374:16] + stbuf_data[3] <= _T_686 @[lsu_stbuf.scala 168:19] + reg _T_687 : UInt<1>, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_stbuf.scala 170:52] + _T_687 <= ldst_dual_d @[lsu_stbuf.scala 170:52] + ldst_dual_m <= _T_687 @[lsu_stbuf.scala 170:42] + reg _T_688 : UInt<1>, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_stbuf.scala 171:52] + _T_688 <= ldst_dual_m @[lsu_stbuf.scala 171:52] + ldst_dual_r <= _T_688 @[lsu_stbuf.scala 171:42] + node _T_689 = dshr(stbuf_vld, RdPtr) @[lsu_stbuf.scala 174:43] + node _T_690 = bits(_T_689, 0, 0) @[lsu_stbuf.scala 174:43] + node _T_691 = dshr(stbuf_dma_kill, RdPtr) @[lsu_stbuf.scala 174:67] + node _T_692 = bits(_T_691, 0, 0) @[lsu_stbuf.scala 174:67] + node _T_693 = and(_T_690, _T_692) @[lsu_stbuf.scala 174:51] + io.stbuf_reqvld_flushed_any <= _T_693 @[lsu_stbuf.scala 174:31] + node _T_694 = dshr(stbuf_vld, RdPtr) @[lsu_stbuf.scala 175:36] + node _T_695 = bits(_T_694, 0, 0) @[lsu_stbuf.scala 175:36] + node _T_696 = dshr(stbuf_dma_kill, RdPtr) @[lsu_stbuf.scala 175:61] + node _T_697 = bits(_T_696, 0, 0) @[lsu_stbuf.scala 175:61] + node _T_698 = eq(_T_697, UInt<1>("h00")) @[lsu_stbuf.scala 175:46] + node _T_699 = and(_T_695, _T_698) @[lsu_stbuf.scala 175:44] + node _T_700 = orr(stbuf_dma_kill_en) @[lsu_stbuf.scala 175:91] + node _T_701 = eq(_T_700, UInt<1>("h00")) @[lsu_stbuf.scala 175:71] + node _T_702 = and(_T_699, _T_701) @[lsu_stbuf.scala 175:69] + io.stbuf_reqvld_any <= _T_702 @[lsu_stbuf.scala 175:24] + io.stbuf_addr_any <= stbuf_addr[RdPtr] @[lsu_stbuf.scala 176:22] + io.stbuf_data_any <= stbuf_data[RdPtr] @[lsu_stbuf.scala 177:22] + node _T_703 = eq(dual_stbuf_write_r, UInt<1>("h00")) @[lsu_stbuf.scala 179:44] + node _T_704 = and(io.ldst_stbuf_reqvld_r, _T_703) @[lsu_stbuf.scala 179:42] + node _T_705 = or(store_coalesce_hi_r, store_coalesce_lo_r) @[lsu_stbuf.scala 179:88] + node _T_706 = eq(_T_705, UInt<1>("h00")) @[lsu_stbuf.scala 179:66] + node _T_707 = and(_T_704, _T_706) @[lsu_stbuf.scala 179:64] + node _T_708 = and(io.ldst_stbuf_reqvld_r, dual_stbuf_write_r) @[lsu_stbuf.scala 180:30] + node _T_709 = and(store_coalesce_hi_r, store_coalesce_lo_r) @[lsu_stbuf.scala 180:76] + node _T_710 = eq(_T_709, UInt<1>("h00")) @[lsu_stbuf.scala 180:54] + node _T_711 = and(_T_708, _T_710) @[lsu_stbuf.scala 180:52] + node _T_712 = or(_T_707, _T_711) @[lsu_stbuf.scala 179:113] + node WrPtrEn = bits(_T_712, 0, 0) @[lsu_stbuf.scala 180:101] + node _T_713 = and(io.ldst_stbuf_reqvld_r, dual_stbuf_write_r) @[lsu_stbuf.scala 181:46] + node _T_714 = or(store_coalesce_hi_r, store_coalesce_lo_r) @[lsu_stbuf.scala 181:91] + node _T_715 = eq(_T_714, UInt<1>("h00")) @[lsu_stbuf.scala 181:69] + node _T_716 = and(_T_713, _T_715) @[lsu_stbuf.scala 181:67] + node _T_717 = bits(_T_716, 0, 0) @[lsu_stbuf.scala 181:115] + node NxtWrPtr = mux(_T_717, WrPtrPlus2, WrPtrPlus1) @[lsu_stbuf.scala 181:21] + node RdPtrEn = or(io.lsu_stbuf_commit_any, io.stbuf_reqvld_flushed_any) @[lsu_stbuf.scala 182:42] + reg _T_718 : UInt, io.lsu_stbuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when WrPtrEn : @[Reg.scala 28:19] + _T_718 <= NxtWrPtr @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + WrPtr <= _T_718 @[lsu_stbuf.scala 185:41] + reg _T_719 : UInt, io.lsu_stbuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when RdPtrEn : @[Reg.scala 28:19] + _T_719 <= RdPtrPlus1 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + RdPtr <= _T_719 @[lsu_stbuf.scala 186:41] + node _T_720 = bits(stbuf_vld, 0, 0) @[lsu_stbuf.scala 188:86] + node _T_721 = cat(UInt<3>("h00"), _T_720) @[Cat.scala 29:58] + node _T_722 = bits(stbuf_vld, 1, 1) @[lsu_stbuf.scala 188:86] + node _T_723 = cat(UInt<3>("h00"), _T_722) @[Cat.scala 29:58] + node _T_724 = bits(stbuf_vld, 2, 2) @[lsu_stbuf.scala 188:86] + node _T_725 = cat(UInt<3>("h00"), _T_724) @[Cat.scala 29:58] + node _T_726 = bits(stbuf_vld, 3, 3) @[lsu_stbuf.scala 188:86] + node _T_727 = cat(UInt<3>("h00"), _T_726) @[Cat.scala 29:58] + wire _T_728 : UInt<4>[4] @[lsu_stbuf.scala 188:59] + _T_728[0] <= _T_721 @[lsu_stbuf.scala 188:59] + _T_728[1] <= _T_723 @[lsu_stbuf.scala 188:59] + _T_728[2] <= _T_725 @[lsu_stbuf.scala 188:59] + _T_728[3] <= _T_727 @[lsu_stbuf.scala 188:59] + node _T_729 = add(_T_728[0], _T_728[1]) @[lsu_stbuf.scala 188:101] + node _T_730 = tail(_T_729, 1) @[lsu_stbuf.scala 188:101] + node _T_731 = add(_T_730, _T_728[2]) @[lsu_stbuf.scala 188:101] + node _T_732 = tail(_T_731, 1) @[lsu_stbuf.scala 188:101] + node _T_733 = add(_T_732, _T_728[3]) @[lsu_stbuf.scala 188:101] + node stbuf_numvld_any = tail(_T_733, 1) @[lsu_stbuf.scala 188:101] + node _T_734 = and(io.lsu_pkt_m.valid, io.lsu_pkt_m.bits.store) @[lsu_stbuf.scala 189:39] + node _T_735 = and(_T_734, io.addr_in_dccm_m) @[lsu_stbuf.scala 189:65] + node _T_736 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_stbuf.scala 189:87] + node isdccmst_m = and(_T_735, _T_736) @[lsu_stbuf.scala 189:85] + node _T_737 = and(io.lsu_pkt_r.valid, io.lsu_pkt_r.bits.store) @[lsu_stbuf.scala 190:39] + node _T_738 = and(_T_737, io.addr_in_dccm_r) @[lsu_stbuf.scala 190:65] + node _T_739 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu_stbuf.scala 190:87] + node isdccmst_r = and(_T_738, _T_739) @[lsu_stbuf.scala 190:85] + node _T_740 = cat(UInt<1>("h00"), isdccmst_m) @[Cat.scala 29:58] + node _T_741 = and(isdccmst_m, ldst_dual_m) @[lsu_stbuf.scala 192:62] + node _T_742 = dshl(_T_740, _T_741) @[lsu_stbuf.scala 192:47] + stbuf_specvld_m <= _T_742 @[lsu_stbuf.scala 192:19] + node _T_743 = cat(UInt<1>("h00"), isdccmst_r) @[Cat.scala 29:58] + node _T_744 = and(isdccmst_r, ldst_dual_r) @[lsu_stbuf.scala 193:62] + node _T_745 = dshl(_T_743, _T_744) @[lsu_stbuf.scala 193:47] + stbuf_specvld_r <= _T_745 @[lsu_stbuf.scala 193:19] + node _T_746 = cat(UInt<2>("h00"), stbuf_specvld_m) @[Cat.scala 29:58] + node _T_747 = add(stbuf_numvld_any, _T_746) @[lsu_stbuf.scala 194:44] + node _T_748 = tail(_T_747, 1) @[lsu_stbuf.scala 194:44] + node _T_749 = cat(UInt<2>("h00"), stbuf_specvld_r) @[Cat.scala 29:58] + node _T_750 = add(_T_748, _T_749) @[lsu_stbuf.scala 194:78] + node stbuf_specvld_any = tail(_T_750, 1) @[lsu_stbuf.scala 194:78] + node _T_751 = eq(ldst_dual_d, UInt<1>("h00")) @[lsu_stbuf.scala 196:34] + node _T_752 = and(_T_751, io.dec_lsu_valid_raw_d) @[lsu_stbuf.scala 196:47] + node _T_753 = bits(_T_752, 0, 0) @[lsu_stbuf.scala 196:73] + node _T_754 = geq(stbuf_specvld_any, UInt<3>("h04")) @[lsu_stbuf.scala 196:99] + node _T_755 = geq(stbuf_specvld_any, UInt<2>("h03")) @[lsu_stbuf.scala 196:140] + node _T_756 = mux(_T_753, _T_754, _T_755) @[lsu_stbuf.scala 196:32] + io.lsu_stbuf_full_any <= _T_756 @[lsu_stbuf.scala 196:26] + node _T_757 = eq(stbuf_numvld_any, UInt<1>("h00")) @[lsu_stbuf.scala 197:46] + io.lsu_stbuf_empty_any <= _T_757 @[lsu_stbuf.scala 197:26] + node cmpen_hi_m = and(io.lsu_cmpen_m, ldst_dual_m) @[lsu_stbuf.scala 199:36] + node _T_758 = bits(io.end_addr_m, 15, 2) @[lsu_stbuf.scala 200:32] + cmpaddr_hi_m <= _T_758 @[lsu_stbuf.scala 200:16] + node _T_759 = bits(io.lsu_addr_m, 15, 2) @[lsu_stbuf.scala 203:33] + cmpaddr_lo_m <= _T_759 @[lsu_stbuf.scala 203:17] + node _T_760 = bits(stbuf_addr[0], 15, 2) @[lsu_stbuf.scala 206:73] + node _T_761 = bits(cmpaddr_hi_m, 13, 0) @[lsu_stbuf.scala 206:131] + node _T_762 = eq(_T_760, _T_761) @[lsu_stbuf.scala 206:115] + node _T_763 = bits(stbuf_vld, 0, 0) @[lsu_stbuf.scala 206:150] + node _T_764 = and(_T_762, _T_763) @[lsu_stbuf.scala 206:139] + node _T_765 = bits(stbuf_dma_kill, 0, 0) @[lsu_stbuf.scala 206:171] + node _T_766 = eq(_T_765, UInt<1>("h00")) @[lsu_stbuf.scala 206:156] + node _T_767 = and(_T_764, _T_766) @[lsu_stbuf.scala 206:154] + node _T_768 = and(_T_767, io.addr_in_dccm_m) @[lsu_stbuf.scala 206:175] + node _T_769 = bits(stbuf_addr[1], 15, 2) @[lsu_stbuf.scala 206:73] + node _T_770 = bits(cmpaddr_hi_m, 13, 0) @[lsu_stbuf.scala 206:131] + node _T_771 = eq(_T_769, _T_770) @[lsu_stbuf.scala 206:115] + node _T_772 = bits(stbuf_vld, 1, 1) @[lsu_stbuf.scala 206:150] + node _T_773 = and(_T_771, _T_772) @[lsu_stbuf.scala 206:139] + node _T_774 = bits(stbuf_dma_kill, 1, 1) @[lsu_stbuf.scala 206:171] + node _T_775 = eq(_T_774, UInt<1>("h00")) @[lsu_stbuf.scala 206:156] + node _T_776 = and(_T_773, _T_775) @[lsu_stbuf.scala 206:154] + node _T_777 = and(_T_776, io.addr_in_dccm_m) @[lsu_stbuf.scala 206:175] + node _T_778 = bits(stbuf_addr[2], 15, 2) @[lsu_stbuf.scala 206:73] + node _T_779 = bits(cmpaddr_hi_m, 13, 0) @[lsu_stbuf.scala 206:131] + node _T_780 = eq(_T_778, _T_779) @[lsu_stbuf.scala 206:115] + node _T_781 = bits(stbuf_vld, 2, 2) @[lsu_stbuf.scala 206:150] + node _T_782 = and(_T_780, _T_781) @[lsu_stbuf.scala 206:139] + node _T_783 = bits(stbuf_dma_kill, 2, 2) @[lsu_stbuf.scala 206:171] + node _T_784 = eq(_T_783, UInt<1>("h00")) @[lsu_stbuf.scala 206:156] + node _T_785 = and(_T_782, _T_784) @[lsu_stbuf.scala 206:154] + node _T_786 = and(_T_785, io.addr_in_dccm_m) @[lsu_stbuf.scala 206:175] + node _T_787 = bits(stbuf_addr[3], 15, 2) @[lsu_stbuf.scala 206:73] + node _T_788 = bits(cmpaddr_hi_m, 13, 0) @[lsu_stbuf.scala 206:131] + node _T_789 = eq(_T_787, _T_788) @[lsu_stbuf.scala 206:115] + node _T_790 = bits(stbuf_vld, 3, 3) @[lsu_stbuf.scala 206:150] + node _T_791 = and(_T_789, _T_790) @[lsu_stbuf.scala 206:139] + node _T_792 = bits(stbuf_dma_kill, 3, 3) @[lsu_stbuf.scala 206:171] + node _T_793 = eq(_T_792, UInt<1>("h00")) @[lsu_stbuf.scala 206:156] + node _T_794 = and(_T_791, _T_793) @[lsu_stbuf.scala 206:154] + node _T_795 = and(_T_794, io.addr_in_dccm_m) @[lsu_stbuf.scala 206:175] + node _T_796 = cat(_T_795, _T_786) @[Cat.scala 29:58] + node _T_797 = cat(_T_796, _T_777) @[Cat.scala 29:58] + node stbuf_match_hi = cat(_T_797, _T_768) @[Cat.scala 29:58] + node _T_798 = bits(stbuf_addr[0], 15, 2) @[lsu_stbuf.scala 207:73] + node _T_799 = bits(cmpaddr_lo_m, 13, 0) @[lsu_stbuf.scala 207:131] + node _T_800 = eq(_T_798, _T_799) @[lsu_stbuf.scala 207:115] + node _T_801 = bits(stbuf_vld, 0, 0) @[lsu_stbuf.scala 207:150] + node _T_802 = and(_T_800, _T_801) @[lsu_stbuf.scala 207:139] + node _T_803 = bits(stbuf_dma_kill, 0, 0) @[lsu_stbuf.scala 207:171] + node _T_804 = eq(_T_803, UInt<1>("h00")) @[lsu_stbuf.scala 207:156] + node _T_805 = and(_T_802, _T_804) @[lsu_stbuf.scala 207:154] + node _T_806 = and(_T_805, io.addr_in_dccm_m) @[lsu_stbuf.scala 207:175] + node _T_807 = bits(stbuf_addr[1], 15, 2) @[lsu_stbuf.scala 207:73] + node _T_808 = bits(cmpaddr_lo_m, 13, 0) @[lsu_stbuf.scala 207:131] + node _T_809 = eq(_T_807, _T_808) @[lsu_stbuf.scala 207:115] + node _T_810 = bits(stbuf_vld, 1, 1) @[lsu_stbuf.scala 207:150] + node _T_811 = and(_T_809, _T_810) @[lsu_stbuf.scala 207:139] + node _T_812 = bits(stbuf_dma_kill, 1, 1) @[lsu_stbuf.scala 207:171] + node _T_813 = eq(_T_812, UInt<1>("h00")) @[lsu_stbuf.scala 207:156] + node _T_814 = and(_T_811, _T_813) @[lsu_stbuf.scala 207:154] + node _T_815 = and(_T_814, io.addr_in_dccm_m) @[lsu_stbuf.scala 207:175] + node _T_816 = bits(stbuf_addr[2], 15, 2) @[lsu_stbuf.scala 207:73] + node _T_817 = bits(cmpaddr_lo_m, 13, 0) @[lsu_stbuf.scala 207:131] + node _T_818 = eq(_T_816, _T_817) @[lsu_stbuf.scala 207:115] + node _T_819 = bits(stbuf_vld, 2, 2) @[lsu_stbuf.scala 207:150] + node _T_820 = and(_T_818, _T_819) @[lsu_stbuf.scala 207:139] + node _T_821 = bits(stbuf_dma_kill, 2, 2) @[lsu_stbuf.scala 207:171] + node _T_822 = eq(_T_821, UInt<1>("h00")) @[lsu_stbuf.scala 207:156] + node _T_823 = and(_T_820, _T_822) @[lsu_stbuf.scala 207:154] + node _T_824 = and(_T_823, io.addr_in_dccm_m) @[lsu_stbuf.scala 207:175] + node _T_825 = bits(stbuf_addr[3], 15, 2) @[lsu_stbuf.scala 207:73] + node _T_826 = bits(cmpaddr_lo_m, 13, 0) @[lsu_stbuf.scala 207:131] + node _T_827 = eq(_T_825, _T_826) @[lsu_stbuf.scala 207:115] + node _T_828 = bits(stbuf_vld, 3, 3) @[lsu_stbuf.scala 207:150] + node _T_829 = and(_T_827, _T_828) @[lsu_stbuf.scala 207:139] + node _T_830 = bits(stbuf_dma_kill, 3, 3) @[lsu_stbuf.scala 207:171] + node _T_831 = eq(_T_830, UInt<1>("h00")) @[lsu_stbuf.scala 207:156] + node _T_832 = and(_T_829, _T_831) @[lsu_stbuf.scala 207:154] + node _T_833 = and(_T_832, io.addr_in_dccm_m) @[lsu_stbuf.scala 207:175] + node _T_834 = cat(_T_833, _T_824) @[Cat.scala 29:58] + node _T_835 = cat(_T_834, _T_815) @[Cat.scala 29:58] + node stbuf_match_lo = cat(_T_835, _T_806) @[Cat.scala 29:58] + node _T_836 = bits(stbuf_match_hi, 0, 0) @[lsu_stbuf.scala 208:74] + node _T_837 = bits(stbuf_match_lo, 0, 0) @[lsu_stbuf.scala 208:94] + node _T_838 = or(_T_836, _T_837) @[lsu_stbuf.scala 208:78] + node _T_839 = and(_T_838, io.lsu_pkt_m.valid) @[lsu_stbuf.scala 208:99] + node _T_840 = and(_T_839, io.lsu_pkt_m.bits.dma) @[lsu_stbuf.scala 208:120] + node _T_841 = and(_T_840, io.lsu_pkt_m.bits.store) @[lsu_stbuf.scala 208:144] + node _T_842 = bits(stbuf_match_hi, 1, 1) @[lsu_stbuf.scala 208:74] + node _T_843 = bits(stbuf_match_lo, 1, 1) @[lsu_stbuf.scala 208:94] + node _T_844 = or(_T_842, _T_843) @[lsu_stbuf.scala 208:78] + node _T_845 = and(_T_844, io.lsu_pkt_m.valid) @[lsu_stbuf.scala 208:99] + node _T_846 = and(_T_845, io.lsu_pkt_m.bits.dma) @[lsu_stbuf.scala 208:120] + node _T_847 = and(_T_846, io.lsu_pkt_m.bits.store) @[lsu_stbuf.scala 208:144] + node _T_848 = bits(stbuf_match_hi, 2, 2) @[lsu_stbuf.scala 208:74] + node _T_849 = bits(stbuf_match_lo, 2, 2) @[lsu_stbuf.scala 208:94] + node _T_850 = or(_T_848, _T_849) @[lsu_stbuf.scala 208:78] + node _T_851 = and(_T_850, io.lsu_pkt_m.valid) @[lsu_stbuf.scala 208:99] + node _T_852 = and(_T_851, io.lsu_pkt_m.bits.dma) @[lsu_stbuf.scala 208:120] + node _T_853 = and(_T_852, io.lsu_pkt_m.bits.store) @[lsu_stbuf.scala 208:144] + node _T_854 = bits(stbuf_match_hi, 3, 3) @[lsu_stbuf.scala 208:74] + node _T_855 = bits(stbuf_match_lo, 3, 3) @[lsu_stbuf.scala 208:94] + node _T_856 = or(_T_854, _T_855) @[lsu_stbuf.scala 208:78] + node _T_857 = and(_T_856, io.lsu_pkt_m.valid) @[lsu_stbuf.scala 208:99] + node _T_858 = and(_T_857, io.lsu_pkt_m.bits.dma) @[lsu_stbuf.scala 208:120] + node _T_859 = and(_T_858, io.lsu_pkt_m.bits.store) @[lsu_stbuf.scala 208:144] + node _T_860 = cat(_T_859, _T_853) @[Cat.scala 29:58] + node _T_861 = cat(_T_860, _T_847) @[Cat.scala 29:58] + node _T_862 = cat(_T_861, _T_841) @[Cat.scala 29:58] + stbuf_dma_kill_en <= _T_862 @[lsu_stbuf.scala 208:21] + node _T_863 = bits(stbuf_match_hi, 0, 0) @[lsu_stbuf.scala 211:112] + node _T_864 = bits(stbuf_byteen[0], 0, 0) @[lsu_stbuf.scala 211:133] + node _T_865 = and(_T_863, _T_864) @[lsu_stbuf.scala 211:116] + node _T_866 = bits(stbuf_vld, 0, 0) @[lsu_stbuf.scala 211:148] + node stbuf_fwdbyteenvec_hi_0_0 = and(_T_865, _T_866) @[lsu_stbuf.scala 211:137] + node _T_867 = bits(stbuf_match_hi, 0, 0) @[lsu_stbuf.scala 211:112] + node _T_868 = bits(stbuf_byteen[0], 1, 1) @[lsu_stbuf.scala 211:133] + node _T_869 = and(_T_867, _T_868) @[lsu_stbuf.scala 211:116] + node _T_870 = bits(stbuf_vld, 0, 0) @[lsu_stbuf.scala 211:148] + node stbuf_fwdbyteenvec_hi_0_1 = and(_T_869, _T_870) @[lsu_stbuf.scala 211:137] + node _T_871 = bits(stbuf_match_hi, 0, 0) @[lsu_stbuf.scala 211:112] + node _T_872 = bits(stbuf_byteen[0], 2, 2) @[lsu_stbuf.scala 211:133] + node _T_873 = and(_T_871, _T_872) @[lsu_stbuf.scala 211:116] + node _T_874 = bits(stbuf_vld, 0, 0) @[lsu_stbuf.scala 211:148] + node stbuf_fwdbyteenvec_hi_0_2 = and(_T_873, _T_874) @[lsu_stbuf.scala 211:137] + node _T_875 = bits(stbuf_match_hi, 0, 0) @[lsu_stbuf.scala 211:112] + node _T_876 = bits(stbuf_byteen[0], 3, 3) @[lsu_stbuf.scala 211:133] + node _T_877 = and(_T_875, _T_876) @[lsu_stbuf.scala 211:116] + node _T_878 = bits(stbuf_vld, 0, 0) @[lsu_stbuf.scala 211:148] + node stbuf_fwdbyteenvec_hi_0_3 = and(_T_877, _T_878) @[lsu_stbuf.scala 211:137] + node _T_879 = bits(stbuf_match_hi, 1, 1) @[lsu_stbuf.scala 211:112] + node _T_880 = bits(stbuf_byteen[1], 0, 0) @[lsu_stbuf.scala 211:133] + node _T_881 = and(_T_879, _T_880) @[lsu_stbuf.scala 211:116] + node _T_882 = bits(stbuf_vld, 1, 1) @[lsu_stbuf.scala 211:148] + node stbuf_fwdbyteenvec_hi_1_0 = and(_T_881, _T_882) @[lsu_stbuf.scala 211:137] + node _T_883 = bits(stbuf_match_hi, 1, 1) @[lsu_stbuf.scala 211:112] + node _T_884 = bits(stbuf_byteen[1], 1, 1) @[lsu_stbuf.scala 211:133] + node _T_885 = and(_T_883, _T_884) @[lsu_stbuf.scala 211:116] + node _T_886 = bits(stbuf_vld, 1, 1) @[lsu_stbuf.scala 211:148] + node stbuf_fwdbyteenvec_hi_1_1 = and(_T_885, _T_886) @[lsu_stbuf.scala 211:137] + node _T_887 = bits(stbuf_match_hi, 1, 1) @[lsu_stbuf.scala 211:112] + node _T_888 = bits(stbuf_byteen[1], 2, 2) @[lsu_stbuf.scala 211:133] + node _T_889 = and(_T_887, _T_888) @[lsu_stbuf.scala 211:116] + node _T_890 = bits(stbuf_vld, 1, 1) @[lsu_stbuf.scala 211:148] + node stbuf_fwdbyteenvec_hi_1_2 = and(_T_889, _T_890) @[lsu_stbuf.scala 211:137] + node _T_891 = bits(stbuf_match_hi, 1, 1) @[lsu_stbuf.scala 211:112] + node _T_892 = bits(stbuf_byteen[1], 3, 3) @[lsu_stbuf.scala 211:133] + node _T_893 = and(_T_891, _T_892) @[lsu_stbuf.scala 211:116] + node _T_894 = bits(stbuf_vld, 1, 1) @[lsu_stbuf.scala 211:148] + node stbuf_fwdbyteenvec_hi_1_3 = and(_T_893, _T_894) @[lsu_stbuf.scala 211:137] + node _T_895 = bits(stbuf_match_hi, 2, 2) @[lsu_stbuf.scala 211:112] + node _T_896 = bits(stbuf_byteen[2], 0, 0) @[lsu_stbuf.scala 211:133] + node _T_897 = and(_T_895, _T_896) @[lsu_stbuf.scala 211:116] + node _T_898 = bits(stbuf_vld, 2, 2) @[lsu_stbuf.scala 211:148] + node stbuf_fwdbyteenvec_hi_2_0 = and(_T_897, _T_898) @[lsu_stbuf.scala 211:137] + node _T_899 = bits(stbuf_match_hi, 2, 2) @[lsu_stbuf.scala 211:112] + node _T_900 = bits(stbuf_byteen[2], 1, 1) @[lsu_stbuf.scala 211:133] + node _T_901 = and(_T_899, _T_900) @[lsu_stbuf.scala 211:116] + node _T_902 = bits(stbuf_vld, 2, 2) @[lsu_stbuf.scala 211:148] + node stbuf_fwdbyteenvec_hi_2_1 = and(_T_901, _T_902) @[lsu_stbuf.scala 211:137] + node _T_903 = bits(stbuf_match_hi, 2, 2) @[lsu_stbuf.scala 211:112] + node _T_904 = bits(stbuf_byteen[2], 2, 2) @[lsu_stbuf.scala 211:133] + node _T_905 = and(_T_903, _T_904) @[lsu_stbuf.scala 211:116] + node _T_906 = bits(stbuf_vld, 2, 2) @[lsu_stbuf.scala 211:148] + node stbuf_fwdbyteenvec_hi_2_2 = and(_T_905, _T_906) @[lsu_stbuf.scala 211:137] + node _T_907 = bits(stbuf_match_hi, 2, 2) @[lsu_stbuf.scala 211:112] + node _T_908 = bits(stbuf_byteen[2], 3, 3) @[lsu_stbuf.scala 211:133] + node _T_909 = and(_T_907, _T_908) @[lsu_stbuf.scala 211:116] + node _T_910 = bits(stbuf_vld, 2, 2) @[lsu_stbuf.scala 211:148] + node stbuf_fwdbyteenvec_hi_2_3 = and(_T_909, _T_910) @[lsu_stbuf.scala 211:137] + node _T_911 = bits(stbuf_match_hi, 3, 3) @[lsu_stbuf.scala 211:112] + node _T_912 = bits(stbuf_byteen[3], 0, 0) @[lsu_stbuf.scala 211:133] + node _T_913 = and(_T_911, _T_912) @[lsu_stbuf.scala 211:116] + node _T_914 = bits(stbuf_vld, 3, 3) @[lsu_stbuf.scala 211:148] + node stbuf_fwdbyteenvec_hi_3_0 = and(_T_913, _T_914) @[lsu_stbuf.scala 211:137] + node _T_915 = bits(stbuf_match_hi, 3, 3) @[lsu_stbuf.scala 211:112] + node _T_916 = bits(stbuf_byteen[3], 1, 1) @[lsu_stbuf.scala 211:133] + node _T_917 = and(_T_915, _T_916) @[lsu_stbuf.scala 211:116] + node _T_918 = bits(stbuf_vld, 3, 3) @[lsu_stbuf.scala 211:148] + node stbuf_fwdbyteenvec_hi_3_1 = and(_T_917, _T_918) @[lsu_stbuf.scala 211:137] + node _T_919 = bits(stbuf_match_hi, 3, 3) @[lsu_stbuf.scala 211:112] + node _T_920 = bits(stbuf_byteen[3], 2, 2) @[lsu_stbuf.scala 211:133] + node _T_921 = and(_T_919, _T_920) @[lsu_stbuf.scala 211:116] + node _T_922 = bits(stbuf_vld, 3, 3) @[lsu_stbuf.scala 211:148] + node stbuf_fwdbyteenvec_hi_3_2 = and(_T_921, _T_922) @[lsu_stbuf.scala 211:137] + node _T_923 = bits(stbuf_match_hi, 3, 3) @[lsu_stbuf.scala 211:112] + node _T_924 = bits(stbuf_byteen[3], 3, 3) @[lsu_stbuf.scala 211:133] + node _T_925 = and(_T_923, _T_924) @[lsu_stbuf.scala 211:116] + node _T_926 = bits(stbuf_vld, 3, 3) @[lsu_stbuf.scala 211:148] + node stbuf_fwdbyteenvec_hi_3_3 = and(_T_925, _T_926) @[lsu_stbuf.scala 211:137] + node _T_927 = bits(stbuf_match_lo, 0, 0) @[lsu_stbuf.scala 212:112] + node _T_928 = bits(stbuf_byteen[0], 0, 0) @[lsu_stbuf.scala 212:133] + node _T_929 = and(_T_927, _T_928) @[lsu_stbuf.scala 212:116] + node _T_930 = bits(stbuf_vld, 0, 0) @[lsu_stbuf.scala 212:148] + node stbuf_fwdbyteenvec_lo_0_0 = and(_T_929, _T_930) @[lsu_stbuf.scala 212:137] + node _T_931 = bits(stbuf_match_lo, 0, 0) @[lsu_stbuf.scala 212:112] + node _T_932 = bits(stbuf_byteen[0], 1, 1) @[lsu_stbuf.scala 212:133] + node _T_933 = and(_T_931, _T_932) @[lsu_stbuf.scala 212:116] + node _T_934 = bits(stbuf_vld, 0, 0) @[lsu_stbuf.scala 212:148] + node stbuf_fwdbyteenvec_lo_0_1 = and(_T_933, _T_934) @[lsu_stbuf.scala 212:137] + node _T_935 = bits(stbuf_match_lo, 0, 0) @[lsu_stbuf.scala 212:112] + node _T_936 = bits(stbuf_byteen[0], 2, 2) @[lsu_stbuf.scala 212:133] + node _T_937 = and(_T_935, _T_936) @[lsu_stbuf.scala 212:116] + node _T_938 = bits(stbuf_vld, 0, 0) @[lsu_stbuf.scala 212:148] + node stbuf_fwdbyteenvec_lo_0_2 = and(_T_937, _T_938) @[lsu_stbuf.scala 212:137] + node _T_939 = bits(stbuf_match_lo, 0, 0) @[lsu_stbuf.scala 212:112] + node _T_940 = bits(stbuf_byteen[0], 3, 3) @[lsu_stbuf.scala 212:133] + node _T_941 = and(_T_939, _T_940) @[lsu_stbuf.scala 212:116] + node _T_942 = bits(stbuf_vld, 0, 0) @[lsu_stbuf.scala 212:148] + node stbuf_fwdbyteenvec_lo_0_3 = and(_T_941, _T_942) @[lsu_stbuf.scala 212:137] + node _T_943 = bits(stbuf_match_lo, 1, 1) @[lsu_stbuf.scala 212:112] + node _T_944 = bits(stbuf_byteen[1], 0, 0) @[lsu_stbuf.scala 212:133] + node _T_945 = and(_T_943, _T_944) @[lsu_stbuf.scala 212:116] + node _T_946 = bits(stbuf_vld, 1, 1) @[lsu_stbuf.scala 212:148] + node stbuf_fwdbyteenvec_lo_1_0 = and(_T_945, _T_946) @[lsu_stbuf.scala 212:137] + node _T_947 = bits(stbuf_match_lo, 1, 1) @[lsu_stbuf.scala 212:112] + node _T_948 = bits(stbuf_byteen[1], 1, 1) @[lsu_stbuf.scala 212:133] + node _T_949 = and(_T_947, _T_948) @[lsu_stbuf.scala 212:116] + node _T_950 = bits(stbuf_vld, 1, 1) @[lsu_stbuf.scala 212:148] + node stbuf_fwdbyteenvec_lo_1_1 = and(_T_949, _T_950) @[lsu_stbuf.scala 212:137] + node _T_951 = bits(stbuf_match_lo, 1, 1) @[lsu_stbuf.scala 212:112] + node _T_952 = bits(stbuf_byteen[1], 2, 2) @[lsu_stbuf.scala 212:133] + node _T_953 = and(_T_951, _T_952) @[lsu_stbuf.scala 212:116] + node _T_954 = bits(stbuf_vld, 1, 1) @[lsu_stbuf.scala 212:148] + node stbuf_fwdbyteenvec_lo_1_2 = and(_T_953, _T_954) @[lsu_stbuf.scala 212:137] + node _T_955 = bits(stbuf_match_lo, 1, 1) @[lsu_stbuf.scala 212:112] + node _T_956 = bits(stbuf_byteen[1], 3, 3) @[lsu_stbuf.scala 212:133] + node _T_957 = and(_T_955, _T_956) @[lsu_stbuf.scala 212:116] + node _T_958 = bits(stbuf_vld, 1, 1) @[lsu_stbuf.scala 212:148] + node stbuf_fwdbyteenvec_lo_1_3 = and(_T_957, _T_958) @[lsu_stbuf.scala 212:137] + node _T_959 = bits(stbuf_match_lo, 2, 2) @[lsu_stbuf.scala 212:112] + node _T_960 = bits(stbuf_byteen[2], 0, 0) @[lsu_stbuf.scala 212:133] + node _T_961 = and(_T_959, _T_960) @[lsu_stbuf.scala 212:116] + node _T_962 = bits(stbuf_vld, 2, 2) @[lsu_stbuf.scala 212:148] + node stbuf_fwdbyteenvec_lo_2_0 = and(_T_961, _T_962) @[lsu_stbuf.scala 212:137] + node _T_963 = bits(stbuf_match_lo, 2, 2) @[lsu_stbuf.scala 212:112] + node _T_964 = bits(stbuf_byteen[2], 1, 1) @[lsu_stbuf.scala 212:133] + node _T_965 = and(_T_963, _T_964) @[lsu_stbuf.scala 212:116] + node _T_966 = bits(stbuf_vld, 2, 2) @[lsu_stbuf.scala 212:148] + node stbuf_fwdbyteenvec_lo_2_1 = and(_T_965, _T_966) @[lsu_stbuf.scala 212:137] + node _T_967 = bits(stbuf_match_lo, 2, 2) @[lsu_stbuf.scala 212:112] + node _T_968 = bits(stbuf_byteen[2], 2, 2) @[lsu_stbuf.scala 212:133] + node _T_969 = and(_T_967, _T_968) @[lsu_stbuf.scala 212:116] + node _T_970 = bits(stbuf_vld, 2, 2) @[lsu_stbuf.scala 212:148] + node stbuf_fwdbyteenvec_lo_2_2 = and(_T_969, _T_970) @[lsu_stbuf.scala 212:137] + node _T_971 = bits(stbuf_match_lo, 2, 2) @[lsu_stbuf.scala 212:112] + node _T_972 = bits(stbuf_byteen[2], 3, 3) @[lsu_stbuf.scala 212:133] + node _T_973 = and(_T_971, _T_972) @[lsu_stbuf.scala 212:116] + node _T_974 = bits(stbuf_vld, 2, 2) @[lsu_stbuf.scala 212:148] + node stbuf_fwdbyteenvec_lo_2_3 = and(_T_973, _T_974) @[lsu_stbuf.scala 212:137] + node _T_975 = bits(stbuf_match_lo, 3, 3) @[lsu_stbuf.scala 212:112] + node _T_976 = bits(stbuf_byteen[3], 0, 0) @[lsu_stbuf.scala 212:133] + node _T_977 = and(_T_975, _T_976) @[lsu_stbuf.scala 212:116] + node _T_978 = bits(stbuf_vld, 3, 3) @[lsu_stbuf.scala 212:148] + node stbuf_fwdbyteenvec_lo_3_0 = and(_T_977, _T_978) @[lsu_stbuf.scala 212:137] + node _T_979 = bits(stbuf_match_lo, 3, 3) @[lsu_stbuf.scala 212:112] + node _T_980 = bits(stbuf_byteen[3], 1, 1) @[lsu_stbuf.scala 212:133] + node _T_981 = and(_T_979, _T_980) @[lsu_stbuf.scala 212:116] + node _T_982 = bits(stbuf_vld, 3, 3) @[lsu_stbuf.scala 212:148] + node stbuf_fwdbyteenvec_lo_3_1 = and(_T_981, _T_982) @[lsu_stbuf.scala 212:137] + node _T_983 = bits(stbuf_match_lo, 3, 3) @[lsu_stbuf.scala 212:112] + node _T_984 = bits(stbuf_byteen[3], 2, 2) @[lsu_stbuf.scala 212:133] + node _T_985 = and(_T_983, _T_984) @[lsu_stbuf.scala 212:116] + node _T_986 = bits(stbuf_vld, 3, 3) @[lsu_stbuf.scala 212:148] + node stbuf_fwdbyteenvec_lo_3_2 = and(_T_985, _T_986) @[lsu_stbuf.scala 212:137] + node _T_987 = bits(stbuf_match_lo, 3, 3) @[lsu_stbuf.scala 212:112] + node _T_988 = bits(stbuf_byteen[3], 3, 3) @[lsu_stbuf.scala 212:133] + node _T_989 = and(_T_987, _T_988) @[lsu_stbuf.scala 212:116] + node _T_990 = bits(stbuf_vld, 3, 3) @[lsu_stbuf.scala 212:148] + node stbuf_fwdbyteenvec_lo_3_3 = and(_T_989, _T_990) @[lsu_stbuf.scala 212:137] + node _T_991 = or(stbuf_fwdbyteenvec_hi_0_0, stbuf_fwdbyteenvec_hi_1_0) @[lsu_stbuf.scala 213:147] + node _T_992 = or(_T_991, stbuf_fwdbyteenvec_hi_2_0) @[lsu_stbuf.scala 213:147] + node stbuf_fwdbyteen_hi_pre_m_0 = or(_T_992, stbuf_fwdbyteenvec_hi_3_0) @[lsu_stbuf.scala 213:147] + node _T_993 = or(stbuf_fwdbyteenvec_hi_0_1, stbuf_fwdbyteenvec_hi_1_1) @[lsu_stbuf.scala 213:147] + node _T_994 = or(_T_993, stbuf_fwdbyteenvec_hi_2_1) @[lsu_stbuf.scala 213:147] + node stbuf_fwdbyteen_hi_pre_m_1 = or(_T_994, stbuf_fwdbyteenvec_hi_3_1) @[lsu_stbuf.scala 213:147] + node _T_995 = or(stbuf_fwdbyteenvec_hi_0_2, stbuf_fwdbyteenvec_hi_1_2) @[lsu_stbuf.scala 213:147] + node _T_996 = or(_T_995, stbuf_fwdbyteenvec_hi_2_2) @[lsu_stbuf.scala 213:147] + node stbuf_fwdbyteen_hi_pre_m_2 = or(_T_996, stbuf_fwdbyteenvec_hi_3_2) @[lsu_stbuf.scala 213:147] + node _T_997 = or(stbuf_fwdbyteenvec_hi_0_3, stbuf_fwdbyteenvec_hi_1_3) @[lsu_stbuf.scala 213:147] + node _T_998 = or(_T_997, stbuf_fwdbyteenvec_hi_2_3) @[lsu_stbuf.scala 213:147] + node stbuf_fwdbyteen_hi_pre_m_3 = or(_T_998, stbuf_fwdbyteenvec_hi_3_3) @[lsu_stbuf.scala 213:147] + node _T_999 = or(stbuf_fwdbyteenvec_lo_0_0, stbuf_fwdbyteenvec_lo_1_0) @[lsu_stbuf.scala 214:147] + node _T_1000 = or(_T_999, stbuf_fwdbyteenvec_lo_2_0) @[lsu_stbuf.scala 214:147] + node stbuf_fwdbyteen_lo_pre_m_0 = or(_T_1000, stbuf_fwdbyteenvec_lo_3_0) @[lsu_stbuf.scala 214:147] + node _T_1001 = or(stbuf_fwdbyteenvec_lo_0_1, stbuf_fwdbyteenvec_lo_1_1) @[lsu_stbuf.scala 214:147] + node _T_1002 = or(_T_1001, stbuf_fwdbyteenvec_lo_2_1) @[lsu_stbuf.scala 214:147] + node stbuf_fwdbyteen_lo_pre_m_1 = or(_T_1002, stbuf_fwdbyteenvec_lo_3_1) @[lsu_stbuf.scala 214:147] + node _T_1003 = or(stbuf_fwdbyteenvec_lo_0_2, stbuf_fwdbyteenvec_lo_1_2) @[lsu_stbuf.scala 214:147] + node _T_1004 = or(_T_1003, stbuf_fwdbyteenvec_lo_2_2) @[lsu_stbuf.scala 214:147] + node stbuf_fwdbyteen_lo_pre_m_2 = or(_T_1004, stbuf_fwdbyteenvec_lo_3_2) @[lsu_stbuf.scala 214:147] + node _T_1005 = or(stbuf_fwdbyteenvec_lo_0_3, stbuf_fwdbyteenvec_lo_1_3) @[lsu_stbuf.scala 214:147] + node _T_1006 = or(_T_1005, stbuf_fwdbyteenvec_lo_2_3) @[lsu_stbuf.scala 214:147] + node stbuf_fwdbyteen_lo_pre_m_3 = or(_T_1006, stbuf_fwdbyteenvec_lo_3_3) @[lsu_stbuf.scala 214:147] + node _T_1007 = bits(stbuf_match_hi, 0, 0) @[lsu_stbuf.scala 216:92] + node _T_1008 = bits(_T_1007, 0, 0) @[Bitwise.scala 72:15] + node _T_1009 = mux(_T_1008, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_1010 = and(_T_1009, stbuf_data[0]) @[lsu_stbuf.scala 216:97] + node _T_1011 = bits(stbuf_match_hi, 1, 1) @[lsu_stbuf.scala 216:92] + node _T_1012 = bits(_T_1011, 0, 0) @[Bitwise.scala 72:15] + node _T_1013 = mux(_T_1012, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_1014 = and(_T_1013, stbuf_data[1]) @[lsu_stbuf.scala 216:97] + node _T_1015 = bits(stbuf_match_hi, 2, 2) @[lsu_stbuf.scala 216:92] + node _T_1016 = bits(_T_1015, 0, 0) @[Bitwise.scala 72:15] + node _T_1017 = mux(_T_1016, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_1018 = and(_T_1017, stbuf_data[2]) @[lsu_stbuf.scala 216:97] + node _T_1019 = bits(stbuf_match_hi, 3, 3) @[lsu_stbuf.scala 216:92] + node _T_1020 = bits(_T_1019, 0, 0) @[Bitwise.scala 72:15] + node _T_1021 = mux(_T_1020, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_1022 = and(_T_1021, stbuf_data[3]) @[lsu_stbuf.scala 216:97] + wire _T_1023 : UInt<32>[4] @[lsu_stbuf.scala 216:65] + _T_1023[0] <= _T_1010 @[lsu_stbuf.scala 216:65] + _T_1023[1] <= _T_1014 @[lsu_stbuf.scala 216:65] + _T_1023[2] <= _T_1018 @[lsu_stbuf.scala 216:65] + _T_1023[3] <= _T_1022 @[lsu_stbuf.scala 216:65] + node _T_1024 = or(_T_1023[3], _T_1023[2]) @[lsu_stbuf.scala 216:130] + node _T_1025 = or(_T_1024, _T_1023[1]) @[lsu_stbuf.scala 216:130] + node stbuf_fwddata_hi_pre_m = or(_T_1025, _T_1023[0]) @[lsu_stbuf.scala 216:130] + node _T_1026 = bits(stbuf_match_lo, 0, 0) @[lsu_stbuf.scala 217:92] + node _T_1027 = bits(_T_1026, 0, 0) @[Bitwise.scala 72:15] + node _T_1028 = mux(_T_1027, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_1029 = and(_T_1028, stbuf_data[0]) @[lsu_stbuf.scala 217:97] + node _T_1030 = bits(stbuf_match_lo, 1, 1) @[lsu_stbuf.scala 217:92] + node _T_1031 = bits(_T_1030, 0, 0) @[Bitwise.scala 72:15] + node _T_1032 = mux(_T_1031, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_1033 = and(_T_1032, stbuf_data[1]) @[lsu_stbuf.scala 217:97] + node _T_1034 = bits(stbuf_match_lo, 2, 2) @[lsu_stbuf.scala 217:92] + node _T_1035 = bits(_T_1034, 0, 0) @[Bitwise.scala 72:15] + node _T_1036 = mux(_T_1035, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_1037 = and(_T_1036, stbuf_data[2]) @[lsu_stbuf.scala 217:97] + node _T_1038 = bits(stbuf_match_lo, 3, 3) @[lsu_stbuf.scala 217:92] + node _T_1039 = bits(_T_1038, 0, 0) @[Bitwise.scala 72:15] + node _T_1040 = mux(_T_1039, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_1041 = and(_T_1040, stbuf_data[3]) @[lsu_stbuf.scala 217:97] + wire _T_1042 : UInt<32>[4] @[lsu_stbuf.scala 217:65] + _T_1042[0] <= _T_1029 @[lsu_stbuf.scala 217:65] + _T_1042[1] <= _T_1033 @[lsu_stbuf.scala 217:65] + _T_1042[2] <= _T_1037 @[lsu_stbuf.scala 217:65] + _T_1042[3] <= _T_1041 @[lsu_stbuf.scala 217:65] + node _T_1043 = or(_T_1042[3], _T_1042[2]) @[lsu_stbuf.scala 217:130] + node _T_1044 = or(_T_1043, _T_1042[1]) @[lsu_stbuf.scala 217:130] + node stbuf_fwddata_lo_pre_m = or(_T_1044, _T_1042[0]) @[lsu_stbuf.scala 217:130] + node _T_1045 = bits(io.lsu_addr_r, 1, 0) @[lsu_stbuf.scala 220:54] + node _T_1046 = dshl(ldst_byteen_r, _T_1045) @[lsu_stbuf.scala 220:38] + ldst_byteen_ext_r <= _T_1046 @[lsu_stbuf.scala 220:21] + node ldst_byteen_hi_r = bits(ldst_byteen_ext_r, 7, 4) @[lsu_stbuf.scala 221:43] + node ldst_byteen_lo_r = bits(ldst_byteen_ext_r, 3, 0) @[lsu_stbuf.scala 222:43] + node _T_1047 = bits(io.lsu_addr_m, 31, 2) @[lsu_stbuf.scala 224:42] + node _T_1048 = bits(io.lsu_addr_r, 31, 2) @[lsu_stbuf.scala 224:66] + node _T_1049 = eq(_T_1047, _T_1048) @[lsu_stbuf.scala 224:49] + node _T_1050 = and(_T_1049, io.lsu_pkt_r.valid) @[lsu_stbuf.scala 224:74] + node _T_1051 = and(_T_1050, io.lsu_pkt_r.bits.store) @[lsu_stbuf.scala 224:95] + node _T_1052 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu_stbuf.scala 224:123] + node ld_addr_rhit_lo_lo = and(_T_1051, _T_1052) @[lsu_stbuf.scala 224:121] + node _T_1053 = bits(io.end_addr_m, 31, 2) @[lsu_stbuf.scala 225:42] + node _T_1054 = bits(io.lsu_addr_r, 31, 2) @[lsu_stbuf.scala 225:66] + node _T_1055 = eq(_T_1053, _T_1054) @[lsu_stbuf.scala 225:49] + node _T_1056 = and(_T_1055, io.lsu_pkt_r.valid) @[lsu_stbuf.scala 225:74] + node _T_1057 = and(_T_1056, io.lsu_pkt_r.bits.store) @[lsu_stbuf.scala 225:95] + node _T_1058 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu_stbuf.scala 225:123] + node ld_addr_rhit_lo_hi = and(_T_1057, _T_1058) @[lsu_stbuf.scala 225:121] + node _T_1059 = bits(io.lsu_addr_m, 31, 2) @[lsu_stbuf.scala 226:42] + node _T_1060 = bits(io.end_addr_r, 31, 2) @[lsu_stbuf.scala 226:66] + node _T_1061 = eq(_T_1059, _T_1060) @[lsu_stbuf.scala 226:49] + node _T_1062 = and(_T_1061, io.lsu_pkt_r.valid) @[lsu_stbuf.scala 226:74] + node _T_1063 = and(_T_1062, io.lsu_pkt_r.bits.store) @[lsu_stbuf.scala 226:95] + node _T_1064 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu_stbuf.scala 226:123] + node _T_1065 = and(_T_1063, _T_1064) @[lsu_stbuf.scala 226:121] + node ld_addr_rhit_hi_lo = and(_T_1065, dual_stbuf_write_r) @[lsu_stbuf.scala 226:146] + node _T_1066 = bits(io.end_addr_m, 31, 2) @[lsu_stbuf.scala 227:42] + node _T_1067 = bits(io.end_addr_r, 31, 2) @[lsu_stbuf.scala 227:66] + node _T_1068 = eq(_T_1066, _T_1067) @[lsu_stbuf.scala 227:49] + node _T_1069 = and(_T_1068, io.lsu_pkt_r.valid) @[lsu_stbuf.scala 227:74] + node _T_1070 = and(_T_1069, io.lsu_pkt_r.bits.store) @[lsu_stbuf.scala 227:95] + node _T_1071 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu_stbuf.scala 227:123] + node _T_1072 = and(_T_1070, _T_1071) @[lsu_stbuf.scala 227:121] + node ld_addr_rhit_hi_hi = and(_T_1072, dual_stbuf_write_r) @[lsu_stbuf.scala 227:146] + node _T_1073 = bits(ldst_byteen_lo_r, 0, 0) @[lsu_stbuf.scala 229:97] + node _T_1074 = and(ld_addr_rhit_lo_lo, _T_1073) @[lsu_stbuf.scala 229:79] + node _T_1075 = bits(ldst_byteen_lo_r, 1, 1) @[lsu_stbuf.scala 229:97] + node _T_1076 = and(ld_addr_rhit_lo_lo, _T_1075) @[lsu_stbuf.scala 229:79] + node _T_1077 = bits(ldst_byteen_lo_r, 2, 2) @[lsu_stbuf.scala 229:97] + node _T_1078 = and(ld_addr_rhit_lo_lo, _T_1077) @[lsu_stbuf.scala 229:79] + node _T_1079 = bits(ldst_byteen_lo_r, 3, 3) @[lsu_stbuf.scala 229:97] + node _T_1080 = and(ld_addr_rhit_lo_lo, _T_1079) @[lsu_stbuf.scala 229:79] + node _T_1081 = cat(_T_1080, _T_1078) @[Cat.scala 29:58] + node _T_1082 = cat(_T_1081, _T_1076) @[Cat.scala 29:58] + node _T_1083 = cat(_T_1082, _T_1074) @[Cat.scala 29:58] + ld_byte_rhit_lo_lo <= _T_1083 @[lsu_stbuf.scala 229:22] + node _T_1084 = bits(ldst_byteen_lo_r, 0, 0) @[lsu_stbuf.scala 230:97] + node _T_1085 = and(ld_addr_rhit_lo_hi, _T_1084) @[lsu_stbuf.scala 230:79] + node _T_1086 = bits(ldst_byteen_lo_r, 1, 1) @[lsu_stbuf.scala 230:97] + node _T_1087 = and(ld_addr_rhit_lo_hi, _T_1086) @[lsu_stbuf.scala 230:79] + node _T_1088 = bits(ldst_byteen_lo_r, 2, 2) @[lsu_stbuf.scala 230:97] + node _T_1089 = and(ld_addr_rhit_lo_hi, _T_1088) @[lsu_stbuf.scala 230:79] + node _T_1090 = bits(ldst_byteen_lo_r, 3, 3) @[lsu_stbuf.scala 230:97] + node _T_1091 = and(ld_addr_rhit_lo_hi, _T_1090) @[lsu_stbuf.scala 230:79] + node _T_1092 = cat(_T_1091, _T_1089) @[Cat.scala 29:58] + node _T_1093 = cat(_T_1092, _T_1087) @[Cat.scala 29:58] + node _T_1094 = cat(_T_1093, _T_1085) @[Cat.scala 29:58] + ld_byte_rhit_lo_hi <= _T_1094 @[lsu_stbuf.scala 230:22] + node _T_1095 = bits(ldst_byteen_hi_r, 0, 0) @[lsu_stbuf.scala 231:97] + node _T_1096 = and(ld_addr_rhit_hi_lo, _T_1095) @[lsu_stbuf.scala 231:79] + node _T_1097 = bits(ldst_byteen_hi_r, 1, 1) @[lsu_stbuf.scala 231:97] + node _T_1098 = and(ld_addr_rhit_hi_lo, _T_1097) @[lsu_stbuf.scala 231:79] + node _T_1099 = bits(ldst_byteen_hi_r, 2, 2) @[lsu_stbuf.scala 231:97] + node _T_1100 = and(ld_addr_rhit_hi_lo, _T_1099) @[lsu_stbuf.scala 231:79] + node _T_1101 = bits(ldst_byteen_hi_r, 3, 3) @[lsu_stbuf.scala 231:97] + node _T_1102 = and(ld_addr_rhit_hi_lo, _T_1101) @[lsu_stbuf.scala 231:79] + node _T_1103 = cat(_T_1102, _T_1100) @[Cat.scala 29:58] + node _T_1104 = cat(_T_1103, _T_1098) @[Cat.scala 29:58] + node _T_1105 = cat(_T_1104, _T_1096) @[Cat.scala 29:58] + ld_byte_rhit_hi_lo <= _T_1105 @[lsu_stbuf.scala 231:22] + node _T_1106 = bits(ldst_byteen_hi_r, 0, 0) @[lsu_stbuf.scala 232:97] + node _T_1107 = and(ld_addr_rhit_hi_hi, _T_1106) @[lsu_stbuf.scala 232:79] + node _T_1108 = bits(ldst_byteen_hi_r, 1, 1) @[lsu_stbuf.scala 232:97] + node _T_1109 = and(ld_addr_rhit_hi_hi, _T_1108) @[lsu_stbuf.scala 232:79] + node _T_1110 = bits(ldst_byteen_hi_r, 2, 2) @[lsu_stbuf.scala 232:97] + node _T_1111 = and(ld_addr_rhit_hi_hi, _T_1110) @[lsu_stbuf.scala 232:79] + node _T_1112 = bits(ldst_byteen_hi_r, 3, 3) @[lsu_stbuf.scala 232:97] + node _T_1113 = and(ld_addr_rhit_hi_hi, _T_1112) @[lsu_stbuf.scala 232:79] + node _T_1114 = cat(_T_1113, _T_1111) @[Cat.scala 29:58] + node _T_1115 = cat(_T_1114, _T_1109) @[Cat.scala 29:58] + node _T_1116 = cat(_T_1115, _T_1107) @[Cat.scala 29:58] + ld_byte_rhit_hi_hi <= _T_1116 @[lsu_stbuf.scala 232:22] + node _T_1117 = bits(ld_byte_rhit_lo_lo, 0, 0) @[lsu_stbuf.scala 234:75] + node _T_1118 = bits(ld_byte_rhit_hi_lo, 0, 0) @[lsu_stbuf.scala 234:99] + node _T_1119 = or(_T_1117, _T_1118) @[lsu_stbuf.scala 234:79] + node _T_1120 = bits(ld_byte_rhit_lo_lo, 1, 1) @[lsu_stbuf.scala 234:75] + node _T_1121 = bits(ld_byte_rhit_hi_lo, 1, 1) @[lsu_stbuf.scala 234:99] + node _T_1122 = or(_T_1120, _T_1121) @[lsu_stbuf.scala 234:79] + node _T_1123 = bits(ld_byte_rhit_lo_lo, 2, 2) @[lsu_stbuf.scala 234:75] + node _T_1124 = bits(ld_byte_rhit_hi_lo, 2, 2) @[lsu_stbuf.scala 234:99] + node _T_1125 = or(_T_1123, _T_1124) @[lsu_stbuf.scala 234:79] + node _T_1126 = bits(ld_byte_rhit_lo_lo, 3, 3) @[lsu_stbuf.scala 234:75] + node _T_1127 = bits(ld_byte_rhit_hi_lo, 3, 3) @[lsu_stbuf.scala 234:99] + node _T_1128 = or(_T_1126, _T_1127) @[lsu_stbuf.scala 234:79] + node _T_1129 = cat(_T_1128, _T_1125) @[Cat.scala 29:58] + node _T_1130 = cat(_T_1129, _T_1122) @[Cat.scala 29:58] + node _T_1131 = cat(_T_1130, _T_1119) @[Cat.scala 29:58] + ld_byte_rhit_lo <= _T_1131 @[lsu_stbuf.scala 234:19] + node _T_1132 = bits(ld_byte_rhit_lo_hi, 0, 0) @[lsu_stbuf.scala 235:75] + node _T_1133 = bits(ld_byte_rhit_hi_hi, 0, 0) @[lsu_stbuf.scala 235:99] + node _T_1134 = or(_T_1132, _T_1133) @[lsu_stbuf.scala 235:79] + node _T_1135 = bits(ld_byte_rhit_lo_hi, 1, 1) @[lsu_stbuf.scala 235:75] + node _T_1136 = bits(ld_byte_rhit_hi_hi, 1, 1) @[lsu_stbuf.scala 235:99] + node _T_1137 = or(_T_1135, _T_1136) @[lsu_stbuf.scala 235:79] + node _T_1138 = bits(ld_byte_rhit_lo_hi, 2, 2) @[lsu_stbuf.scala 235:75] + node _T_1139 = bits(ld_byte_rhit_hi_hi, 2, 2) @[lsu_stbuf.scala 235:99] + node _T_1140 = or(_T_1138, _T_1139) @[lsu_stbuf.scala 235:79] + node _T_1141 = bits(ld_byte_rhit_lo_hi, 3, 3) @[lsu_stbuf.scala 235:75] + node _T_1142 = bits(ld_byte_rhit_hi_hi, 3, 3) @[lsu_stbuf.scala 235:99] + node _T_1143 = or(_T_1141, _T_1142) @[lsu_stbuf.scala 235:79] + node _T_1144 = cat(_T_1143, _T_1140) @[Cat.scala 29:58] + node _T_1145 = cat(_T_1144, _T_1137) @[Cat.scala 29:58] + node _T_1146 = cat(_T_1145, _T_1134) @[Cat.scala 29:58] + ld_byte_rhit_hi <= _T_1146 @[lsu_stbuf.scala 235:19] + node _T_1147 = bits(ld_byte_rhit_lo_lo, 0, 0) @[lsu_stbuf.scala 237:48] + node _T_1148 = bits(_T_1147, 0, 0) @[Bitwise.scala 72:15] + node _T_1149 = mux(_T_1148, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1150 = bits(io.store_data_lo_r, 7, 0) @[lsu_stbuf.scala 237:73] + node _T_1151 = and(_T_1149, _T_1150) @[lsu_stbuf.scala 237:53] + node _T_1152 = bits(ld_byte_rhit_hi_lo, 0, 0) @[lsu_stbuf.scala 237:109] + node _T_1153 = bits(_T_1152, 0, 0) @[Bitwise.scala 72:15] + node _T_1154 = mux(_T_1153, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1155 = bits(io.store_data_hi_r, 7, 0) @[lsu_stbuf.scala 237:134] + node _T_1156 = and(_T_1154, _T_1155) @[lsu_stbuf.scala 237:114] + node fwdpipe1_lo = or(_T_1151, _T_1156) @[lsu_stbuf.scala 237:80] + node _T_1157 = bits(ld_byte_rhit_lo_lo, 1, 1) @[lsu_stbuf.scala 238:48] + node _T_1158 = bits(_T_1157, 0, 0) @[Bitwise.scala 72:15] + node _T_1159 = mux(_T_1158, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1160 = bits(io.store_data_lo_r, 15, 8) @[lsu_stbuf.scala 238:73] + node _T_1161 = and(_T_1159, _T_1160) @[lsu_stbuf.scala 238:53] + node _T_1162 = bits(ld_byte_rhit_hi_lo, 1, 1) @[lsu_stbuf.scala 238:110] + node _T_1163 = bits(_T_1162, 0, 0) @[Bitwise.scala 72:15] + node _T_1164 = mux(_T_1163, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1165 = bits(io.store_data_hi_r, 15, 8) @[lsu_stbuf.scala 238:135] + node _T_1166 = and(_T_1164, _T_1165) @[lsu_stbuf.scala 238:115] + node fwdpipe2_lo = or(_T_1161, _T_1166) @[lsu_stbuf.scala 238:81] + node _T_1167 = bits(ld_byte_rhit_lo_lo, 2, 2) @[lsu_stbuf.scala 239:48] + node _T_1168 = bits(_T_1167, 0, 0) @[Bitwise.scala 72:15] + node _T_1169 = mux(_T_1168, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1170 = bits(io.store_data_lo_r, 23, 16) @[lsu_stbuf.scala 239:73] + node _T_1171 = and(_T_1169, _T_1170) @[lsu_stbuf.scala 239:53] + node _T_1172 = bits(ld_byte_rhit_hi_lo, 2, 2) @[lsu_stbuf.scala 239:111] + node _T_1173 = bits(_T_1172, 0, 0) @[Bitwise.scala 72:15] + node _T_1174 = mux(_T_1173, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1175 = bits(io.store_data_hi_r, 23, 16) @[lsu_stbuf.scala 239:136] + node _T_1176 = and(_T_1174, _T_1175) @[lsu_stbuf.scala 239:116] + node fwdpipe3_lo = or(_T_1171, _T_1176) @[lsu_stbuf.scala 239:82] + node _T_1177 = bits(ld_byte_rhit_lo_lo, 3, 3) @[lsu_stbuf.scala 240:48] + node _T_1178 = bits(_T_1177, 0, 0) @[Bitwise.scala 72:15] + node _T_1179 = mux(_T_1178, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1180 = bits(io.store_data_lo_r, 31, 24) @[lsu_stbuf.scala 240:73] + node _T_1181 = and(_T_1179, _T_1180) @[lsu_stbuf.scala 240:53] + node _T_1182 = bits(ld_byte_rhit_hi_lo, 3, 3) @[lsu_stbuf.scala 240:111] + node _T_1183 = bits(_T_1182, 0, 0) @[Bitwise.scala 72:15] + node _T_1184 = mux(_T_1183, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1185 = bits(io.store_data_hi_r, 31, 24) @[lsu_stbuf.scala 240:136] + node _T_1186 = and(_T_1184, _T_1185) @[lsu_stbuf.scala 240:116] + node fwdpipe4_lo = or(_T_1181, _T_1186) @[lsu_stbuf.scala 240:82] + node _T_1187 = cat(fwdpipe2_lo, fwdpipe1_lo) @[Cat.scala 29:58] + node _T_1188 = cat(fwdpipe4_lo, fwdpipe3_lo) @[Cat.scala 29:58] + node _T_1189 = cat(_T_1188, _T_1187) @[Cat.scala 29:58] + ld_fwddata_rpipe_lo <= _T_1189 @[lsu_stbuf.scala 241:23] + node _T_1190 = bits(ld_byte_rhit_lo_hi, 0, 0) @[lsu_stbuf.scala 243:48] + node _T_1191 = bits(_T_1190, 0, 0) @[Bitwise.scala 72:15] + node _T_1192 = mux(_T_1191, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1193 = bits(io.store_data_lo_r, 7, 0) @[lsu_stbuf.scala 243:73] + node _T_1194 = and(_T_1192, _T_1193) @[lsu_stbuf.scala 243:53] + node _T_1195 = bits(ld_byte_rhit_hi_hi, 0, 0) @[lsu_stbuf.scala 243:109] + node _T_1196 = bits(_T_1195, 0, 0) @[Bitwise.scala 72:15] + node _T_1197 = mux(_T_1196, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1198 = bits(io.store_data_hi_r, 7, 0) @[lsu_stbuf.scala 243:134] + node _T_1199 = and(_T_1197, _T_1198) @[lsu_stbuf.scala 243:114] + node fwdpipe1_hi = or(_T_1194, _T_1199) @[lsu_stbuf.scala 243:80] + node _T_1200 = bits(ld_byte_rhit_lo_hi, 1, 1) @[lsu_stbuf.scala 244:48] + node _T_1201 = bits(_T_1200, 0, 0) @[Bitwise.scala 72:15] + node _T_1202 = mux(_T_1201, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1203 = bits(io.store_data_lo_r, 15, 8) @[lsu_stbuf.scala 244:73] + node _T_1204 = and(_T_1202, _T_1203) @[lsu_stbuf.scala 244:53] + node _T_1205 = bits(ld_byte_rhit_hi_hi, 1, 1) @[lsu_stbuf.scala 244:110] + node _T_1206 = bits(_T_1205, 0, 0) @[Bitwise.scala 72:15] + node _T_1207 = mux(_T_1206, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1208 = bits(io.store_data_hi_r, 15, 8) @[lsu_stbuf.scala 244:135] + node _T_1209 = and(_T_1207, _T_1208) @[lsu_stbuf.scala 244:115] + node fwdpipe2_hi = or(_T_1204, _T_1209) @[lsu_stbuf.scala 244:81] + node _T_1210 = bits(ld_byte_rhit_lo_hi, 2, 2) @[lsu_stbuf.scala 245:48] + node _T_1211 = bits(_T_1210, 0, 0) @[Bitwise.scala 72:15] + node _T_1212 = mux(_T_1211, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1213 = bits(io.store_data_lo_r, 23, 16) @[lsu_stbuf.scala 245:73] + node _T_1214 = and(_T_1212, _T_1213) @[lsu_stbuf.scala 245:53] + node _T_1215 = bits(ld_byte_rhit_hi_hi, 2, 2) @[lsu_stbuf.scala 245:111] + node _T_1216 = bits(_T_1215, 0, 0) @[Bitwise.scala 72:15] + node _T_1217 = mux(_T_1216, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1218 = bits(io.store_data_hi_r, 23, 16) @[lsu_stbuf.scala 245:136] + node _T_1219 = and(_T_1217, _T_1218) @[lsu_stbuf.scala 245:116] + node fwdpipe3_hi = or(_T_1214, _T_1219) @[lsu_stbuf.scala 245:82] + node _T_1220 = bits(ld_byte_rhit_lo_hi, 3, 3) @[lsu_stbuf.scala 246:48] + node _T_1221 = bits(_T_1220, 0, 0) @[Bitwise.scala 72:15] + node _T_1222 = mux(_T_1221, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1223 = bits(io.store_data_lo_r, 31, 24) @[lsu_stbuf.scala 246:73] + node _T_1224 = and(_T_1222, _T_1223) @[lsu_stbuf.scala 246:53] + node _T_1225 = bits(ld_byte_rhit_hi_hi, 3, 3) @[lsu_stbuf.scala 246:111] + node _T_1226 = bits(_T_1225, 0, 0) @[Bitwise.scala 72:15] + node _T_1227 = mux(_T_1226, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1228 = bits(io.store_data_hi_r, 31, 24) @[lsu_stbuf.scala 246:136] + node _T_1229 = and(_T_1227, _T_1228) @[lsu_stbuf.scala 246:116] + node fwdpipe4_hi = or(_T_1224, _T_1229) @[lsu_stbuf.scala 246:82] + node _T_1230 = cat(fwdpipe2_hi, fwdpipe1_hi) @[Cat.scala 29:58] + node _T_1231 = cat(fwdpipe4_hi, fwdpipe3_hi) @[Cat.scala 29:58] + node _T_1232 = cat(_T_1231, _T_1230) @[Cat.scala 29:58] + ld_fwddata_rpipe_hi <= _T_1232 @[lsu_stbuf.scala 247:23] + node _T_1233 = bits(ld_byte_rhit_lo_lo, 0, 0) @[lsu_stbuf.scala 249:74] + node _T_1234 = bits(ld_byte_rhit_hi_lo, 0, 0) @[lsu_stbuf.scala 249:98] + node _T_1235 = or(_T_1233, _T_1234) @[lsu_stbuf.scala 249:78] + node _T_1236 = bits(ld_byte_rhit_lo_lo, 1, 1) @[lsu_stbuf.scala 249:74] + node _T_1237 = bits(ld_byte_rhit_hi_lo, 1, 1) @[lsu_stbuf.scala 249:98] + node _T_1238 = or(_T_1236, _T_1237) @[lsu_stbuf.scala 249:78] + node _T_1239 = bits(ld_byte_rhit_lo_lo, 2, 2) @[lsu_stbuf.scala 249:74] + node _T_1240 = bits(ld_byte_rhit_hi_lo, 2, 2) @[lsu_stbuf.scala 249:98] + node _T_1241 = or(_T_1239, _T_1240) @[lsu_stbuf.scala 249:78] + node _T_1242 = bits(ld_byte_rhit_lo_lo, 3, 3) @[lsu_stbuf.scala 249:74] + node _T_1243 = bits(ld_byte_rhit_hi_lo, 3, 3) @[lsu_stbuf.scala 249:98] + node _T_1244 = or(_T_1242, _T_1243) @[lsu_stbuf.scala 249:78] + node _T_1245 = cat(_T_1244, _T_1241) @[Cat.scala 29:58] + node _T_1246 = cat(_T_1245, _T_1238) @[Cat.scala 29:58] + node _T_1247 = cat(_T_1246, _T_1235) @[Cat.scala 29:58] + ld_byte_hit_lo <= _T_1247 @[lsu_stbuf.scala 249:18] + node _T_1248 = bits(ld_byte_rhit_lo_hi, 0, 0) @[lsu_stbuf.scala 250:74] + node _T_1249 = bits(ld_byte_rhit_hi_hi, 0, 0) @[lsu_stbuf.scala 250:98] + node _T_1250 = or(_T_1248, _T_1249) @[lsu_stbuf.scala 250:78] + node _T_1251 = bits(ld_byte_rhit_lo_hi, 1, 1) @[lsu_stbuf.scala 250:74] + node _T_1252 = bits(ld_byte_rhit_hi_hi, 1, 1) @[lsu_stbuf.scala 250:98] + node _T_1253 = or(_T_1251, _T_1252) @[lsu_stbuf.scala 250:78] + node _T_1254 = bits(ld_byte_rhit_lo_hi, 2, 2) @[lsu_stbuf.scala 250:74] + node _T_1255 = bits(ld_byte_rhit_hi_hi, 2, 2) @[lsu_stbuf.scala 250:98] + node _T_1256 = or(_T_1254, _T_1255) @[lsu_stbuf.scala 250:78] + node _T_1257 = bits(ld_byte_rhit_lo_hi, 3, 3) @[lsu_stbuf.scala 250:74] + node _T_1258 = bits(ld_byte_rhit_hi_hi, 3, 3) @[lsu_stbuf.scala 250:98] + node _T_1259 = or(_T_1257, _T_1258) @[lsu_stbuf.scala 250:78] + node _T_1260 = cat(_T_1259, _T_1256) @[Cat.scala 29:58] + node _T_1261 = cat(_T_1260, _T_1253) @[Cat.scala 29:58] + node _T_1262 = cat(_T_1261, _T_1250) @[Cat.scala 29:58] + ld_byte_hit_hi <= _T_1262 @[lsu_stbuf.scala 250:18] + node _T_1263 = bits(ld_byte_hit_hi, 0, 0) @[lsu_stbuf.scala 252:79] + node _T_1264 = or(_T_1263, stbuf_fwdbyteen_hi_pre_m_0) @[lsu_stbuf.scala 252:83] + node _T_1265 = bits(ld_byte_hit_hi, 1, 1) @[lsu_stbuf.scala 252:79] + node _T_1266 = or(_T_1265, stbuf_fwdbyteen_hi_pre_m_1) @[lsu_stbuf.scala 252:83] + node _T_1267 = bits(ld_byte_hit_hi, 2, 2) @[lsu_stbuf.scala 252:79] + node _T_1268 = or(_T_1267, stbuf_fwdbyteen_hi_pre_m_2) @[lsu_stbuf.scala 252:83] + node _T_1269 = bits(ld_byte_hit_hi, 3, 3) @[lsu_stbuf.scala 252:79] + node _T_1270 = or(_T_1269, stbuf_fwdbyteen_hi_pre_m_3) @[lsu_stbuf.scala 252:83] + node _T_1271 = cat(_T_1270, _T_1268) @[Cat.scala 29:58] + node _T_1272 = cat(_T_1271, _T_1266) @[Cat.scala 29:58] + node _T_1273 = cat(_T_1272, _T_1264) @[Cat.scala 29:58] + io.stbuf_fwdbyteen_hi_m <= _T_1273 @[lsu_stbuf.scala 252:27] + node _T_1274 = bits(ld_byte_hit_lo, 0, 0) @[lsu_stbuf.scala 253:79] + node _T_1275 = or(_T_1274, stbuf_fwdbyteen_lo_pre_m_0) @[lsu_stbuf.scala 253:83] + node _T_1276 = bits(ld_byte_hit_lo, 1, 1) @[lsu_stbuf.scala 253:79] + node _T_1277 = or(_T_1276, stbuf_fwdbyteen_lo_pre_m_1) @[lsu_stbuf.scala 253:83] + node _T_1278 = bits(ld_byte_hit_lo, 2, 2) @[lsu_stbuf.scala 253:79] + node _T_1279 = or(_T_1278, stbuf_fwdbyteen_lo_pre_m_2) @[lsu_stbuf.scala 253:83] + node _T_1280 = bits(ld_byte_hit_lo, 3, 3) @[lsu_stbuf.scala 253:79] + node _T_1281 = or(_T_1280, stbuf_fwdbyteen_lo_pre_m_3) @[lsu_stbuf.scala 253:83] + node _T_1282 = cat(_T_1281, _T_1279) @[Cat.scala 29:58] + node _T_1283 = cat(_T_1282, _T_1277) @[Cat.scala 29:58] + node _T_1284 = cat(_T_1283, _T_1275) @[Cat.scala 29:58] + io.stbuf_fwdbyteen_lo_m <= _T_1284 @[lsu_stbuf.scala 253:27] + node _T_1285 = bits(ld_byte_rhit_lo, 0, 0) @[lsu_stbuf.scala 256:46] + node _T_1286 = bits(ld_fwddata_rpipe_lo, 7, 0) @[lsu_stbuf.scala 256:69] + node _T_1287 = bits(stbuf_fwddata_lo_pre_m, 7, 0) @[lsu_stbuf.scala 256:97] + node stbuf_fwdpipe1_lo = mux(_T_1285, _T_1286, _T_1287) @[lsu_stbuf.scala 256:30] + node _T_1288 = bits(ld_byte_rhit_lo, 1, 1) @[lsu_stbuf.scala 257:46] + node _T_1289 = bits(ld_fwddata_rpipe_lo, 15, 8) @[lsu_stbuf.scala 257:69] + node _T_1290 = bits(stbuf_fwddata_lo_pre_m, 15, 8) @[lsu_stbuf.scala 257:98] + node stbuf_fwdpipe2_lo = mux(_T_1288, _T_1289, _T_1290) @[lsu_stbuf.scala 257:30] + node _T_1291 = bits(ld_byte_rhit_lo, 2, 2) @[lsu_stbuf.scala 258:46] + node _T_1292 = bits(ld_fwddata_rpipe_lo, 23, 16) @[lsu_stbuf.scala 258:69] + node _T_1293 = bits(stbuf_fwddata_lo_pre_m, 23, 16) @[lsu_stbuf.scala 258:99] + node stbuf_fwdpipe3_lo = mux(_T_1291, _T_1292, _T_1293) @[lsu_stbuf.scala 258:30] + node _T_1294 = bits(ld_byte_rhit_lo, 3, 3) @[lsu_stbuf.scala 259:46] + node _T_1295 = bits(ld_fwddata_rpipe_lo, 31, 24) @[lsu_stbuf.scala 259:69] + node _T_1296 = bits(stbuf_fwddata_lo_pre_m, 31, 24) @[lsu_stbuf.scala 259:99] + node stbuf_fwdpipe4_lo = mux(_T_1294, _T_1295, _T_1296) @[lsu_stbuf.scala 259:30] + node _T_1297 = cat(stbuf_fwdpipe2_lo, stbuf_fwdpipe1_lo) @[Cat.scala 29:58] + node _T_1298 = cat(stbuf_fwdpipe4_lo, stbuf_fwdpipe3_lo) @[Cat.scala 29:58] + node _T_1299 = cat(_T_1298, _T_1297) @[Cat.scala 29:58] + io.stbuf_fwddata_lo_m <= _T_1299 @[lsu_stbuf.scala 260:25] + node _T_1300 = bits(ld_byte_rhit_hi, 0, 0) @[lsu_stbuf.scala 262:46] + node _T_1301 = bits(ld_fwddata_rpipe_hi, 7, 0) @[lsu_stbuf.scala 262:69] + node _T_1302 = bits(stbuf_fwddata_hi_pre_m, 7, 0) @[lsu_stbuf.scala 262:97] + node stbuf_fwdpipe1_hi = mux(_T_1300, _T_1301, _T_1302) @[lsu_stbuf.scala 262:30] + node _T_1303 = bits(ld_byte_rhit_hi, 1, 1) @[lsu_stbuf.scala 263:46] + node _T_1304 = bits(ld_fwddata_rpipe_hi, 15, 8) @[lsu_stbuf.scala 263:69] + node _T_1305 = bits(stbuf_fwddata_hi_pre_m, 15, 8) @[lsu_stbuf.scala 263:98] + node stbuf_fwdpipe2_hi = mux(_T_1303, _T_1304, _T_1305) @[lsu_stbuf.scala 263:30] + node _T_1306 = bits(ld_byte_rhit_hi, 2, 2) @[lsu_stbuf.scala 264:46] + node _T_1307 = bits(ld_fwddata_rpipe_hi, 23, 16) @[lsu_stbuf.scala 264:69] + node _T_1308 = bits(stbuf_fwddata_hi_pre_m, 23, 16) @[lsu_stbuf.scala 264:99] + node stbuf_fwdpipe3_hi = mux(_T_1306, _T_1307, _T_1308) @[lsu_stbuf.scala 264:30] + node _T_1309 = bits(ld_byte_rhit_hi, 3, 3) @[lsu_stbuf.scala 265:46] + node _T_1310 = bits(ld_fwddata_rpipe_hi, 31, 24) @[lsu_stbuf.scala 265:69] + node _T_1311 = bits(stbuf_fwddata_hi_pre_m, 31, 24) @[lsu_stbuf.scala 265:99] + node stbuf_fwdpipe4_hi = mux(_T_1309, _T_1310, _T_1311) @[lsu_stbuf.scala 265:30] + node _T_1312 = cat(stbuf_fwdpipe2_hi, stbuf_fwdpipe1_hi) @[Cat.scala 29:58] + node _T_1313 = cat(stbuf_fwdpipe4_hi, stbuf_fwdpipe3_hi) @[Cat.scala 29:58] + node _T_1314 = cat(_T_1313, _T_1312) @[Cat.scala 29:58] + io.stbuf_fwddata_hi_m <= _T_1314 @[lsu_stbuf.scala 266:25] + + extmodule gated_latch_10 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_10 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_10 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_11 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_11 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_11 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + module lsu_ecc : + input clock : Clock + input reset : AsyncReset + output io : {flip lsu_c2_r_clk : Clock, flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip stbuf_data_any : UInt<32>, flip dec_tlu_core_ecc_disable : UInt<1>, flip lsu_dccm_rden_r : UInt<1>, flip addr_in_dccm_r : UInt<1>, flip lsu_addr_r : UInt<16>, flip end_addr_r : UInt<16>, flip lsu_addr_m : UInt<16>, flip end_addr_m : UInt<16>, flip dccm_rdata_hi_r : UInt<32>, flip dccm_rdata_lo_r : UInt<32>, flip dccm_rdata_hi_m : UInt<32>, flip dccm_rdata_lo_m : UInt<32>, flip dccm_data_ecc_hi_r : UInt<7>, flip dccm_data_ecc_lo_r : UInt<7>, flip dccm_data_ecc_hi_m : UInt<7>, flip dccm_data_ecc_lo_m : UInt<7>, flip ld_single_ecc_error_r : UInt<1>, flip ld_single_ecc_error_r_ff : UInt<1>, flip lsu_dccm_rden_m : UInt<1>, flip addr_in_dccm_m : UInt<1>, flip dma_dccm_wen : UInt<1>, flip dma_dccm_wdata_lo : UInt<32>, flip dma_dccm_wdata_hi : UInt<32>, flip scan_mode : UInt<1>, sec_data_hi_r : UInt<32>, sec_data_lo_r : UInt<32>, sec_data_hi_m : UInt<32>, sec_data_lo_m : UInt<32>, sec_data_hi_r_ff : UInt<32>, sec_data_lo_r_ff : UInt<32>, dma_dccm_wdata_ecc_hi : UInt<7>, dma_dccm_wdata_ecc_lo : UInt<7>, stbuf_ecc_any : UInt<7>, sec_data_ecc_hi_r_ff : UInt<7>, sec_data_ecc_lo_r_ff : UInt<7>, single_ecc_error_hi_r : UInt<1>, single_ecc_error_lo_r : UInt<1>, lsu_single_ecc_error_r : UInt<1>, lsu_double_ecc_error_r : UInt<1>, lsu_single_ecc_error_m : UInt<1>, lsu_double_ecc_error_m : UInt<1>} + + wire is_ldst_r : UInt<1> + is_ldst_r <= UInt<1>("h00") + wire is_ldst_hi_any : UInt<1> + is_ldst_hi_any <= UInt<1>("h00") + wire is_ldst_lo_any : UInt<1> + is_ldst_lo_any <= UInt<1>("h00") + wire dccm_wdata_hi_any : UInt<32> + dccm_wdata_hi_any <= UInt<32>("h00") + wire dccm_wdata_lo_any : UInt<32> + dccm_wdata_lo_any <= UInt<32>("h00") + wire dccm_rdata_hi_any : UInt<32> + dccm_rdata_hi_any <= UInt<32>("h00") + wire dccm_rdata_lo_any : UInt<32> + dccm_rdata_lo_any <= UInt<32>("h00") + wire dccm_data_ecc_hi_any : UInt<7> + dccm_data_ecc_hi_any <= UInt<7>("h00") + wire dccm_data_ecc_lo_any : UInt<7> + dccm_data_ecc_lo_any <= UInt<7>("h00") + wire double_ecc_error_hi_m : UInt<1> + double_ecc_error_hi_m <= UInt<1>("h00") + wire double_ecc_error_lo_m : UInt<1> + double_ecc_error_lo_m <= UInt<1>("h00") + wire double_ecc_error_hi_r : UInt<1> + double_ecc_error_hi_r <= UInt<1>("h00") + wire double_ecc_error_lo_r : UInt<1> + double_ecc_error_lo_r <= UInt<1>("h00") + wire ldst_dual_m : UInt<1> + ldst_dual_m <= UInt<1>("h00") + wire ldst_dual_r : UInt<1> + ldst_dual_r <= UInt<1>("h00") + wire is_ldst_m : UInt<1> + is_ldst_m <= UInt<1>("h00") + wire is_ldst_hi_m : UInt<1> + is_ldst_hi_m <= UInt<1>("h00") + wire is_ldst_lo_m : UInt<1> + is_ldst_lo_m <= UInt<1>("h00") + wire is_ldst_hi_r : UInt<1> + is_ldst_hi_r <= UInt<1>("h00") + wire is_ldst_lo_r : UInt<1> + is_ldst_lo_r <= UInt<1>("h00") + io.sec_data_hi_m <= UInt<1>("h00") @[lsu_ecc.scala 90:32] + io.sec_data_lo_m <= UInt<1>("h00") @[lsu_ecc.scala 91:32] + io.lsu_single_ecc_error_m <= UInt<1>("h00") @[lsu_ecc.scala 92:30] + io.lsu_double_ecc_error_m <= UInt<1>("h00") @[lsu_ecc.scala 93:30] + wire _T : UInt<1>[18] @[lib.scala 173:18] + wire _T_1 : UInt<1>[18] @[lib.scala 174:18] + wire _T_2 : UInt<1>[18] @[lib.scala 175:18] + wire _T_3 : UInt<1>[15] @[lib.scala 176:18] + wire _T_4 : UInt<1>[15] @[lib.scala 177:18] + wire _T_5 : UInt<1>[6] @[lib.scala 178:18] + node _T_6 = bits(dccm_rdata_hi_any, 0, 0) @[lib.scala 185:36] + _T[0] <= _T_6 @[lib.scala 185:30] + node _T_7 = bits(dccm_rdata_hi_any, 0, 0) @[lib.scala 186:36] + _T_1[0] <= _T_7 @[lib.scala 186:30] + node _T_8 = bits(dccm_rdata_hi_any, 1, 1) @[lib.scala 185:36] + _T[1] <= _T_8 @[lib.scala 185:30] + node _T_9 = bits(dccm_rdata_hi_any, 1, 1) @[lib.scala 187:36] + _T_2[0] <= _T_9 @[lib.scala 187:30] + node _T_10 = bits(dccm_rdata_hi_any, 2, 2) @[lib.scala 186:36] + _T_1[1] <= _T_10 @[lib.scala 186:30] + node _T_11 = bits(dccm_rdata_hi_any, 2, 2) @[lib.scala 187:36] + _T_2[1] <= _T_11 @[lib.scala 187:30] + node _T_12 = bits(dccm_rdata_hi_any, 3, 3) @[lib.scala 185:36] + _T[2] <= _T_12 @[lib.scala 185:30] + node _T_13 = bits(dccm_rdata_hi_any, 3, 3) @[lib.scala 186:36] + _T_1[2] <= _T_13 @[lib.scala 186:30] + node _T_14 = bits(dccm_rdata_hi_any, 3, 3) @[lib.scala 187:36] + _T_2[2] <= _T_14 @[lib.scala 187:30] + node _T_15 = bits(dccm_rdata_hi_any, 4, 4) @[lib.scala 185:36] + _T[3] <= _T_15 @[lib.scala 185:30] + node _T_16 = bits(dccm_rdata_hi_any, 4, 4) @[lib.scala 188:36] + _T_3[0] <= _T_16 @[lib.scala 188:30] + node _T_17 = bits(dccm_rdata_hi_any, 5, 5) @[lib.scala 186:36] + _T_1[3] <= _T_17 @[lib.scala 186:30] + node _T_18 = bits(dccm_rdata_hi_any, 5, 5) @[lib.scala 188:36] + _T_3[1] <= _T_18 @[lib.scala 188:30] + node _T_19 = bits(dccm_rdata_hi_any, 6, 6) @[lib.scala 185:36] + _T[4] <= _T_19 @[lib.scala 185:30] + node _T_20 = bits(dccm_rdata_hi_any, 6, 6) @[lib.scala 186:36] + _T_1[4] <= _T_20 @[lib.scala 186:30] + node _T_21 = bits(dccm_rdata_hi_any, 6, 6) @[lib.scala 188:36] + _T_3[2] <= _T_21 @[lib.scala 188:30] + node _T_22 = bits(dccm_rdata_hi_any, 7, 7) @[lib.scala 187:36] + _T_2[3] <= _T_22 @[lib.scala 187:30] + node _T_23 = bits(dccm_rdata_hi_any, 7, 7) @[lib.scala 188:36] + _T_3[3] <= _T_23 @[lib.scala 188:30] + node _T_24 = bits(dccm_rdata_hi_any, 8, 8) @[lib.scala 185:36] + _T[5] <= _T_24 @[lib.scala 185:30] + node _T_25 = bits(dccm_rdata_hi_any, 8, 8) @[lib.scala 187:36] + _T_2[4] <= _T_25 @[lib.scala 187:30] + node _T_26 = bits(dccm_rdata_hi_any, 8, 8) @[lib.scala 188:36] + _T_3[4] <= _T_26 @[lib.scala 188:30] + node _T_27 = bits(dccm_rdata_hi_any, 9, 9) @[lib.scala 186:36] + _T_1[5] <= _T_27 @[lib.scala 186:30] + node _T_28 = bits(dccm_rdata_hi_any, 9, 9) @[lib.scala 187:36] + _T_2[5] <= _T_28 @[lib.scala 187:30] + node _T_29 = bits(dccm_rdata_hi_any, 9, 9) @[lib.scala 188:36] + _T_3[5] <= _T_29 @[lib.scala 188:30] + node _T_30 = bits(dccm_rdata_hi_any, 10, 10) @[lib.scala 185:36] + _T[6] <= _T_30 @[lib.scala 185:30] + node _T_31 = bits(dccm_rdata_hi_any, 10, 10) @[lib.scala 186:36] + _T_1[6] <= _T_31 @[lib.scala 186:30] + node _T_32 = bits(dccm_rdata_hi_any, 10, 10) @[lib.scala 187:36] + _T_2[6] <= _T_32 @[lib.scala 187:30] + node _T_33 = bits(dccm_rdata_hi_any, 10, 10) @[lib.scala 188:36] + _T_3[6] <= _T_33 @[lib.scala 188:30] + node _T_34 = bits(dccm_rdata_hi_any, 11, 11) @[lib.scala 185:36] + _T[7] <= _T_34 @[lib.scala 185:30] + node _T_35 = bits(dccm_rdata_hi_any, 11, 11) @[lib.scala 189:36] + _T_4[0] <= _T_35 @[lib.scala 189:30] + node _T_36 = bits(dccm_rdata_hi_any, 12, 12) @[lib.scala 186:36] + _T_1[7] <= _T_36 @[lib.scala 186:30] + node _T_37 = bits(dccm_rdata_hi_any, 12, 12) @[lib.scala 189:36] + _T_4[1] <= _T_37 @[lib.scala 189:30] + node _T_38 = bits(dccm_rdata_hi_any, 13, 13) @[lib.scala 185:36] + _T[8] <= _T_38 @[lib.scala 185:30] + node _T_39 = bits(dccm_rdata_hi_any, 13, 13) @[lib.scala 186:36] + _T_1[8] <= _T_39 @[lib.scala 186:30] + node _T_40 = bits(dccm_rdata_hi_any, 13, 13) @[lib.scala 189:36] + _T_4[2] <= _T_40 @[lib.scala 189:30] + node _T_41 = bits(dccm_rdata_hi_any, 14, 14) @[lib.scala 187:36] + _T_2[7] <= _T_41 @[lib.scala 187:30] + node _T_42 = bits(dccm_rdata_hi_any, 14, 14) @[lib.scala 189:36] + _T_4[3] <= _T_42 @[lib.scala 189:30] + node _T_43 = bits(dccm_rdata_hi_any, 15, 15) @[lib.scala 185:36] + _T[9] <= _T_43 @[lib.scala 185:30] + node _T_44 = bits(dccm_rdata_hi_any, 15, 15) @[lib.scala 187:36] + _T_2[8] <= _T_44 @[lib.scala 187:30] + node _T_45 = bits(dccm_rdata_hi_any, 15, 15) @[lib.scala 189:36] + _T_4[4] <= _T_45 @[lib.scala 189:30] + node _T_46 = bits(dccm_rdata_hi_any, 16, 16) @[lib.scala 186:36] + _T_1[9] <= _T_46 @[lib.scala 186:30] + node _T_47 = bits(dccm_rdata_hi_any, 16, 16) @[lib.scala 187:36] + _T_2[9] <= _T_47 @[lib.scala 187:30] + node _T_48 = bits(dccm_rdata_hi_any, 16, 16) @[lib.scala 189:36] + _T_4[5] <= _T_48 @[lib.scala 189:30] + node _T_49 = bits(dccm_rdata_hi_any, 17, 17) @[lib.scala 185:36] + _T[10] <= _T_49 @[lib.scala 185:30] + node _T_50 = bits(dccm_rdata_hi_any, 17, 17) @[lib.scala 186:36] + _T_1[10] <= _T_50 @[lib.scala 186:30] + node _T_51 = bits(dccm_rdata_hi_any, 17, 17) @[lib.scala 187:36] + _T_2[10] <= _T_51 @[lib.scala 187:30] + node _T_52 = bits(dccm_rdata_hi_any, 17, 17) @[lib.scala 189:36] + _T_4[6] <= _T_52 @[lib.scala 189:30] + node _T_53 = bits(dccm_rdata_hi_any, 18, 18) @[lib.scala 188:36] + _T_3[7] <= _T_53 @[lib.scala 188:30] + node _T_54 = bits(dccm_rdata_hi_any, 18, 18) @[lib.scala 189:36] + _T_4[7] <= _T_54 @[lib.scala 189:30] + node _T_55 = bits(dccm_rdata_hi_any, 19, 19) @[lib.scala 185:36] + _T[11] <= _T_55 @[lib.scala 185:30] + node _T_56 = bits(dccm_rdata_hi_any, 19, 19) @[lib.scala 188:36] + _T_3[8] <= _T_56 @[lib.scala 188:30] + node _T_57 = bits(dccm_rdata_hi_any, 19, 19) @[lib.scala 189:36] + _T_4[8] <= _T_57 @[lib.scala 189:30] + node _T_58 = bits(dccm_rdata_hi_any, 20, 20) @[lib.scala 186:36] + _T_1[11] <= _T_58 @[lib.scala 186:30] + node _T_59 = bits(dccm_rdata_hi_any, 20, 20) @[lib.scala 188:36] + _T_3[9] <= _T_59 @[lib.scala 188:30] + node _T_60 = bits(dccm_rdata_hi_any, 20, 20) @[lib.scala 189:36] + _T_4[9] <= _T_60 @[lib.scala 189:30] + node _T_61 = bits(dccm_rdata_hi_any, 21, 21) @[lib.scala 185:36] + _T[12] <= _T_61 @[lib.scala 185:30] + node _T_62 = bits(dccm_rdata_hi_any, 21, 21) @[lib.scala 186:36] + _T_1[12] <= _T_62 @[lib.scala 186:30] + node _T_63 = bits(dccm_rdata_hi_any, 21, 21) @[lib.scala 188:36] + _T_3[10] <= _T_63 @[lib.scala 188:30] + node _T_64 = bits(dccm_rdata_hi_any, 21, 21) @[lib.scala 189:36] + _T_4[10] <= _T_64 @[lib.scala 189:30] + node _T_65 = bits(dccm_rdata_hi_any, 22, 22) @[lib.scala 187:36] + _T_2[11] <= _T_65 @[lib.scala 187:30] + node _T_66 = bits(dccm_rdata_hi_any, 22, 22) @[lib.scala 188:36] + _T_3[11] <= _T_66 @[lib.scala 188:30] + node _T_67 = bits(dccm_rdata_hi_any, 22, 22) @[lib.scala 189:36] + _T_4[11] <= _T_67 @[lib.scala 189:30] + node _T_68 = bits(dccm_rdata_hi_any, 23, 23) @[lib.scala 185:36] + _T[13] <= _T_68 @[lib.scala 185:30] + node _T_69 = bits(dccm_rdata_hi_any, 23, 23) @[lib.scala 187:36] + _T_2[12] <= _T_69 @[lib.scala 187:30] + node _T_70 = bits(dccm_rdata_hi_any, 23, 23) @[lib.scala 188:36] + _T_3[12] <= _T_70 @[lib.scala 188:30] + node _T_71 = bits(dccm_rdata_hi_any, 23, 23) @[lib.scala 189:36] + _T_4[12] <= _T_71 @[lib.scala 189:30] + node _T_72 = bits(dccm_rdata_hi_any, 24, 24) @[lib.scala 186:36] + _T_1[13] <= _T_72 @[lib.scala 186:30] + node _T_73 = bits(dccm_rdata_hi_any, 24, 24) @[lib.scala 187:36] + _T_2[13] <= _T_73 @[lib.scala 187:30] + node _T_74 = bits(dccm_rdata_hi_any, 24, 24) @[lib.scala 188:36] + _T_3[13] <= _T_74 @[lib.scala 188:30] + node _T_75 = bits(dccm_rdata_hi_any, 24, 24) @[lib.scala 189:36] + _T_4[13] <= _T_75 @[lib.scala 189:30] + node _T_76 = bits(dccm_rdata_hi_any, 25, 25) @[lib.scala 185:36] + _T[14] <= _T_76 @[lib.scala 185:30] + node _T_77 = bits(dccm_rdata_hi_any, 25, 25) @[lib.scala 186:36] + _T_1[14] <= _T_77 @[lib.scala 186:30] + node _T_78 = bits(dccm_rdata_hi_any, 25, 25) @[lib.scala 187:36] + _T_2[14] <= _T_78 @[lib.scala 187:30] + node _T_79 = bits(dccm_rdata_hi_any, 25, 25) @[lib.scala 188:36] + _T_3[14] <= _T_79 @[lib.scala 188:30] + node _T_80 = bits(dccm_rdata_hi_any, 25, 25) @[lib.scala 189:36] + _T_4[14] <= _T_80 @[lib.scala 189:30] + node _T_81 = bits(dccm_rdata_hi_any, 26, 26) @[lib.scala 185:36] + _T[15] <= _T_81 @[lib.scala 185:30] + node _T_82 = bits(dccm_rdata_hi_any, 26, 26) @[lib.scala 190:36] + _T_5[0] <= _T_82 @[lib.scala 190:30] + node _T_83 = bits(dccm_rdata_hi_any, 27, 27) @[lib.scala 186:36] + _T_1[15] <= _T_83 @[lib.scala 186:30] + node _T_84 = bits(dccm_rdata_hi_any, 27, 27) @[lib.scala 190:36] + _T_5[1] <= _T_84 @[lib.scala 190:30] + node _T_85 = bits(dccm_rdata_hi_any, 28, 28) @[lib.scala 185:36] + _T[16] <= _T_85 @[lib.scala 185:30] + node _T_86 = bits(dccm_rdata_hi_any, 28, 28) @[lib.scala 186:36] + _T_1[16] <= _T_86 @[lib.scala 186:30] + node _T_87 = bits(dccm_rdata_hi_any, 28, 28) @[lib.scala 190:36] + _T_5[2] <= _T_87 @[lib.scala 190:30] + node _T_88 = bits(dccm_rdata_hi_any, 29, 29) @[lib.scala 187:36] + _T_2[15] <= _T_88 @[lib.scala 187:30] + node _T_89 = bits(dccm_rdata_hi_any, 29, 29) @[lib.scala 190:36] + _T_5[3] <= _T_89 @[lib.scala 190:30] + node _T_90 = bits(dccm_rdata_hi_any, 30, 30) @[lib.scala 185:36] + _T[17] <= _T_90 @[lib.scala 185:30] + node _T_91 = bits(dccm_rdata_hi_any, 30, 30) @[lib.scala 187:36] + _T_2[16] <= _T_91 @[lib.scala 187:30] + node _T_92 = bits(dccm_rdata_hi_any, 30, 30) @[lib.scala 190:36] + _T_5[4] <= _T_92 @[lib.scala 190:30] + node _T_93 = bits(dccm_rdata_hi_any, 31, 31) @[lib.scala 186:36] + _T_1[17] <= _T_93 @[lib.scala 186:30] + node _T_94 = bits(dccm_rdata_hi_any, 31, 31) @[lib.scala 187:36] + _T_2[17] <= _T_94 @[lib.scala 187:30] + node _T_95 = bits(dccm_rdata_hi_any, 31, 31) @[lib.scala 190:36] + _T_5[5] <= _T_95 @[lib.scala 190:30] + node _T_96 = xorr(dccm_rdata_hi_any) @[lib.scala 193:30] + node _T_97 = xorr(dccm_data_ecc_hi_any) @[lib.scala 193:44] + node _T_98 = xor(_T_96, _T_97) @[lib.scala 193:35] + node _T_99 = not(UInt<1>("h00")) @[lib.scala 193:52] + node _T_100 = and(_T_98, _T_99) @[lib.scala 193:50] + node _T_101 = bits(dccm_data_ecc_hi_any, 5, 5) @[lib.scala 193:68] + node _T_102 = cat(_T_5[2], _T_5[1]) @[lib.scala 193:76] + node _T_103 = cat(_T_102, _T_5[0]) @[lib.scala 193:76] + node _T_104 = cat(_T_5[5], _T_5[4]) @[lib.scala 193:76] + node _T_105 = cat(_T_104, _T_5[3]) @[lib.scala 193:76] + node _T_106 = cat(_T_105, _T_103) @[lib.scala 193:76] + node _T_107 = xorr(_T_106) @[lib.scala 193:83] + node _T_108 = xor(_T_101, _T_107) @[lib.scala 193:71] + node _T_109 = bits(dccm_data_ecc_hi_any, 4, 4) @[lib.scala 193:95] + node _T_110 = cat(_T_4[2], _T_4[1]) @[lib.scala 193:103] + node _T_111 = cat(_T_110, _T_4[0]) @[lib.scala 193:103] + node _T_112 = cat(_T_4[4], _T_4[3]) @[lib.scala 193:103] + node _T_113 = cat(_T_4[6], _T_4[5]) @[lib.scala 193:103] + node _T_114 = cat(_T_113, _T_112) @[lib.scala 193:103] + node _T_115 = cat(_T_114, _T_111) @[lib.scala 193:103] + node _T_116 = cat(_T_4[8], _T_4[7]) @[lib.scala 193:103] + node _T_117 = cat(_T_4[10], _T_4[9]) @[lib.scala 193:103] + node _T_118 = cat(_T_117, _T_116) @[lib.scala 193:103] + node _T_119 = cat(_T_4[12], _T_4[11]) @[lib.scala 193:103] + node _T_120 = cat(_T_4[14], _T_4[13]) @[lib.scala 193:103] + node _T_121 = cat(_T_120, _T_119) @[lib.scala 193:103] + node _T_122 = cat(_T_121, _T_118) @[lib.scala 193:103] + node _T_123 = cat(_T_122, _T_115) @[lib.scala 193:103] + node _T_124 = xorr(_T_123) @[lib.scala 193:110] + node _T_125 = xor(_T_109, _T_124) @[lib.scala 193:98] + node _T_126 = bits(dccm_data_ecc_hi_any, 3, 3) @[lib.scala 193:122] + node _T_127 = cat(_T_3[2], _T_3[1]) @[lib.scala 193:130] + node _T_128 = cat(_T_127, _T_3[0]) @[lib.scala 193:130] + node _T_129 = cat(_T_3[4], _T_3[3]) @[lib.scala 193:130] + node _T_130 = cat(_T_3[6], _T_3[5]) @[lib.scala 193:130] + node _T_131 = cat(_T_130, _T_129) @[lib.scala 193:130] + node _T_132 = cat(_T_131, _T_128) @[lib.scala 193:130] + node _T_133 = cat(_T_3[8], _T_3[7]) @[lib.scala 193:130] + node _T_134 = cat(_T_3[10], _T_3[9]) @[lib.scala 193:130] + node _T_135 = cat(_T_134, _T_133) @[lib.scala 193:130] + node _T_136 = cat(_T_3[12], _T_3[11]) @[lib.scala 193:130] + node _T_137 = cat(_T_3[14], _T_3[13]) @[lib.scala 193:130] + node _T_138 = cat(_T_137, _T_136) @[lib.scala 193:130] + node _T_139 = cat(_T_138, _T_135) @[lib.scala 193:130] + node _T_140 = cat(_T_139, _T_132) @[lib.scala 193:130] + node _T_141 = xorr(_T_140) @[lib.scala 193:137] + node _T_142 = xor(_T_126, _T_141) @[lib.scala 193:125] + node _T_143 = bits(dccm_data_ecc_hi_any, 2, 2) @[lib.scala 193:149] + node _T_144 = cat(_T_2[1], _T_2[0]) @[lib.scala 193:157] + node _T_145 = cat(_T_2[3], _T_2[2]) @[lib.scala 193:157] + node _T_146 = cat(_T_145, _T_144) @[lib.scala 193:157] + node _T_147 = cat(_T_2[5], _T_2[4]) @[lib.scala 193:157] + node _T_148 = cat(_T_2[8], _T_2[7]) @[lib.scala 193:157] + node _T_149 = cat(_T_148, _T_2[6]) @[lib.scala 193:157] + node _T_150 = cat(_T_149, _T_147) @[lib.scala 193:157] + node _T_151 = cat(_T_150, _T_146) @[lib.scala 193:157] + node _T_152 = cat(_T_2[10], _T_2[9]) @[lib.scala 193:157] + node _T_153 = cat(_T_2[12], _T_2[11]) @[lib.scala 193:157] + node _T_154 = cat(_T_153, _T_152) @[lib.scala 193:157] + node _T_155 = cat(_T_2[14], _T_2[13]) @[lib.scala 193:157] + node _T_156 = cat(_T_2[17], _T_2[16]) @[lib.scala 193:157] + node _T_157 = cat(_T_156, _T_2[15]) @[lib.scala 193:157] + node _T_158 = cat(_T_157, _T_155) @[lib.scala 193:157] + node _T_159 = cat(_T_158, _T_154) @[lib.scala 193:157] + node _T_160 = cat(_T_159, _T_151) @[lib.scala 193:157] + node _T_161 = xorr(_T_160) @[lib.scala 193:164] + node _T_162 = xor(_T_143, _T_161) @[lib.scala 193:152] + node _T_163 = bits(dccm_data_ecc_hi_any, 1, 1) @[lib.scala 193:176] + node _T_164 = cat(_T_1[1], _T_1[0]) @[lib.scala 193:184] + node _T_165 = cat(_T_1[3], _T_1[2]) @[lib.scala 193:184] + node _T_166 = cat(_T_165, _T_164) @[lib.scala 193:184] + node _T_167 = cat(_T_1[5], _T_1[4]) @[lib.scala 193:184] + node _T_168 = cat(_T_1[8], _T_1[7]) @[lib.scala 193:184] + node _T_169 = cat(_T_168, _T_1[6]) @[lib.scala 193:184] + node _T_170 = cat(_T_169, _T_167) @[lib.scala 193:184] + node _T_171 = cat(_T_170, _T_166) @[lib.scala 193:184] + node _T_172 = cat(_T_1[10], _T_1[9]) @[lib.scala 193:184] + node _T_173 = cat(_T_1[12], _T_1[11]) @[lib.scala 193:184] + node _T_174 = cat(_T_173, _T_172) @[lib.scala 193:184] + node _T_175 = cat(_T_1[14], _T_1[13]) @[lib.scala 193:184] + node _T_176 = cat(_T_1[17], _T_1[16]) @[lib.scala 193:184] + node _T_177 = cat(_T_176, _T_1[15]) @[lib.scala 193:184] + node _T_178 = cat(_T_177, _T_175) @[lib.scala 193:184] + node _T_179 = cat(_T_178, _T_174) @[lib.scala 193:184] + node _T_180 = cat(_T_179, _T_171) @[lib.scala 193:184] + node _T_181 = xorr(_T_180) @[lib.scala 193:191] + node _T_182 = xor(_T_163, _T_181) @[lib.scala 193:179] + node _T_183 = bits(dccm_data_ecc_hi_any, 0, 0) @[lib.scala 193:203] + node _T_184 = cat(_T[1], _T[0]) @[lib.scala 193:211] + node _T_185 = cat(_T[3], _T[2]) @[lib.scala 193:211] + node _T_186 = cat(_T_185, _T_184) @[lib.scala 193:211] + node _T_187 = cat(_T[5], _T[4]) @[lib.scala 193:211] + node _T_188 = cat(_T[8], _T[7]) @[lib.scala 193:211] + node _T_189 = cat(_T_188, _T[6]) @[lib.scala 193:211] + node _T_190 = cat(_T_189, _T_187) @[lib.scala 193:211] + node _T_191 = cat(_T_190, _T_186) @[lib.scala 193:211] + node _T_192 = cat(_T[10], _T[9]) @[lib.scala 193:211] + node _T_193 = cat(_T[12], _T[11]) @[lib.scala 193:211] + node _T_194 = cat(_T_193, _T_192) @[lib.scala 193:211] + node _T_195 = cat(_T[14], _T[13]) @[lib.scala 193:211] + node _T_196 = cat(_T[17], _T[16]) @[lib.scala 193:211] + node _T_197 = cat(_T_196, _T[15]) @[lib.scala 193:211] + node _T_198 = cat(_T_197, _T_195) @[lib.scala 193:211] + node _T_199 = cat(_T_198, _T_194) @[lib.scala 193:211] + node _T_200 = cat(_T_199, _T_191) @[lib.scala 193:211] + node _T_201 = xorr(_T_200) @[lib.scala 193:218] + node _T_202 = xor(_T_183, _T_201) @[lib.scala 193:206] + node _T_203 = cat(_T_162, _T_182) @[Cat.scala 29:58] + node _T_204 = cat(_T_203, _T_202) @[Cat.scala 29:58] + node _T_205 = cat(_T_125, _T_142) @[Cat.scala 29:58] + node _T_206 = cat(_T_100, _T_108) @[Cat.scala 29:58] + node _T_207 = cat(_T_206, _T_205) @[Cat.scala 29:58] + node _T_208 = cat(_T_207, _T_204) @[Cat.scala 29:58] + node _T_209 = neq(_T_208, UInt<1>("h00")) @[lib.scala 194:44] + node _T_210 = and(is_ldst_hi_any, _T_209) @[lib.scala 194:32] + node _T_211 = bits(_T_208, 6, 6) @[lib.scala 194:64] + node single_ecc_error_hi_any = and(_T_210, _T_211) @[lib.scala 194:53] + node _T_212 = neq(_T_208, UInt<1>("h00")) @[lib.scala 195:44] + node _T_213 = and(is_ldst_hi_any, _T_212) @[lib.scala 195:32] + node _T_214 = bits(_T_208, 6, 6) @[lib.scala 195:65] + node _T_215 = not(_T_214) @[lib.scala 195:55] + node double_ecc_error_hi_any = and(_T_213, _T_215) @[lib.scala 195:53] + wire _T_216 : UInt<1>[39] @[lib.scala 196:26] + node _T_217 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_218 = eq(_T_217, UInt<1>("h01")) @[lib.scala 199:41] + _T_216[0] <= _T_218 @[lib.scala 199:23] + node _T_219 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_220 = eq(_T_219, UInt<2>("h02")) @[lib.scala 199:41] + _T_216[1] <= _T_220 @[lib.scala 199:23] + node _T_221 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_222 = eq(_T_221, UInt<2>("h03")) @[lib.scala 199:41] + _T_216[2] <= _T_222 @[lib.scala 199:23] + node _T_223 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_224 = eq(_T_223, UInt<3>("h04")) @[lib.scala 199:41] + _T_216[3] <= _T_224 @[lib.scala 199:23] + node _T_225 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_226 = eq(_T_225, UInt<3>("h05")) @[lib.scala 199:41] + _T_216[4] <= _T_226 @[lib.scala 199:23] + node _T_227 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_228 = eq(_T_227, UInt<3>("h06")) @[lib.scala 199:41] + _T_216[5] <= _T_228 @[lib.scala 199:23] + node _T_229 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_230 = eq(_T_229, UInt<3>("h07")) @[lib.scala 199:41] + _T_216[6] <= _T_230 @[lib.scala 199:23] + node _T_231 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_232 = eq(_T_231, UInt<4>("h08")) @[lib.scala 199:41] + _T_216[7] <= _T_232 @[lib.scala 199:23] + node _T_233 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_234 = eq(_T_233, UInt<4>("h09")) @[lib.scala 199:41] + _T_216[8] <= _T_234 @[lib.scala 199:23] + node _T_235 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_236 = eq(_T_235, UInt<4>("h0a")) @[lib.scala 199:41] + _T_216[9] <= _T_236 @[lib.scala 199:23] + node _T_237 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_238 = eq(_T_237, UInt<4>("h0b")) @[lib.scala 199:41] + _T_216[10] <= _T_238 @[lib.scala 199:23] + node _T_239 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_240 = eq(_T_239, UInt<4>("h0c")) @[lib.scala 199:41] + _T_216[11] <= _T_240 @[lib.scala 199:23] + node _T_241 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_242 = eq(_T_241, UInt<4>("h0d")) @[lib.scala 199:41] + _T_216[12] <= _T_242 @[lib.scala 199:23] + node _T_243 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_244 = eq(_T_243, UInt<4>("h0e")) @[lib.scala 199:41] + _T_216[13] <= _T_244 @[lib.scala 199:23] + node _T_245 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_246 = eq(_T_245, UInt<4>("h0f")) @[lib.scala 199:41] + _T_216[14] <= _T_246 @[lib.scala 199:23] + node _T_247 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_248 = eq(_T_247, UInt<5>("h010")) @[lib.scala 199:41] + _T_216[15] <= _T_248 @[lib.scala 199:23] + node _T_249 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_250 = eq(_T_249, UInt<5>("h011")) @[lib.scala 199:41] + _T_216[16] <= _T_250 @[lib.scala 199:23] + node _T_251 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_252 = eq(_T_251, UInt<5>("h012")) @[lib.scala 199:41] + _T_216[17] <= _T_252 @[lib.scala 199:23] + node _T_253 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_254 = eq(_T_253, UInt<5>("h013")) @[lib.scala 199:41] + _T_216[18] <= _T_254 @[lib.scala 199:23] + node _T_255 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_256 = eq(_T_255, UInt<5>("h014")) @[lib.scala 199:41] + _T_216[19] <= _T_256 @[lib.scala 199:23] + node _T_257 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_258 = eq(_T_257, UInt<5>("h015")) @[lib.scala 199:41] + _T_216[20] <= _T_258 @[lib.scala 199:23] + node _T_259 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_260 = eq(_T_259, UInt<5>("h016")) @[lib.scala 199:41] + _T_216[21] <= _T_260 @[lib.scala 199:23] + node _T_261 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_262 = eq(_T_261, UInt<5>("h017")) @[lib.scala 199:41] + _T_216[22] <= _T_262 @[lib.scala 199:23] + node _T_263 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_264 = eq(_T_263, UInt<5>("h018")) @[lib.scala 199:41] + _T_216[23] <= _T_264 @[lib.scala 199:23] + node _T_265 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_266 = eq(_T_265, UInt<5>("h019")) @[lib.scala 199:41] + _T_216[24] <= _T_266 @[lib.scala 199:23] + node _T_267 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_268 = eq(_T_267, UInt<5>("h01a")) @[lib.scala 199:41] + _T_216[25] <= _T_268 @[lib.scala 199:23] + node _T_269 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_270 = eq(_T_269, UInt<5>("h01b")) @[lib.scala 199:41] + _T_216[26] <= _T_270 @[lib.scala 199:23] + node _T_271 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_272 = eq(_T_271, UInt<5>("h01c")) @[lib.scala 199:41] + _T_216[27] <= _T_272 @[lib.scala 199:23] + node _T_273 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_274 = eq(_T_273, UInt<5>("h01d")) @[lib.scala 199:41] + _T_216[28] <= _T_274 @[lib.scala 199:23] + node _T_275 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_276 = eq(_T_275, UInt<5>("h01e")) @[lib.scala 199:41] + _T_216[29] <= _T_276 @[lib.scala 199:23] + node _T_277 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_278 = eq(_T_277, UInt<5>("h01f")) @[lib.scala 199:41] + _T_216[30] <= _T_278 @[lib.scala 199:23] + node _T_279 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_280 = eq(_T_279, UInt<6>("h020")) @[lib.scala 199:41] + _T_216[31] <= _T_280 @[lib.scala 199:23] + node _T_281 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_282 = eq(_T_281, UInt<6>("h021")) @[lib.scala 199:41] + _T_216[32] <= _T_282 @[lib.scala 199:23] + node _T_283 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_284 = eq(_T_283, UInt<6>("h022")) @[lib.scala 199:41] + _T_216[33] <= _T_284 @[lib.scala 199:23] + node _T_285 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_286 = eq(_T_285, UInt<6>("h023")) @[lib.scala 199:41] + _T_216[34] <= _T_286 @[lib.scala 199:23] + node _T_287 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_288 = eq(_T_287, UInt<6>("h024")) @[lib.scala 199:41] + _T_216[35] <= _T_288 @[lib.scala 199:23] + node _T_289 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_290 = eq(_T_289, UInt<6>("h025")) @[lib.scala 199:41] + _T_216[36] <= _T_290 @[lib.scala 199:23] + node _T_291 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_292 = eq(_T_291, UInt<6>("h026")) @[lib.scala 199:41] + _T_216[37] <= _T_292 @[lib.scala 199:23] + node _T_293 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_294 = eq(_T_293, UInt<6>("h027")) @[lib.scala 199:41] + _T_216[38] <= _T_294 @[lib.scala 199:23] + node _T_295 = bits(dccm_data_ecc_hi_any, 6, 6) @[lib.scala 201:37] + node _T_296 = bits(dccm_rdata_hi_any, 31, 26) @[lib.scala 201:45] + node _T_297 = bits(dccm_data_ecc_hi_any, 5, 5) @[lib.scala 201:60] + node _T_298 = bits(dccm_rdata_hi_any, 25, 11) @[lib.scala 201:68] + node _T_299 = bits(dccm_data_ecc_hi_any, 4, 4) @[lib.scala 201:83] + node _T_300 = bits(dccm_rdata_hi_any, 10, 4) @[lib.scala 201:91] + node _T_301 = bits(dccm_data_ecc_hi_any, 3, 3) @[lib.scala 201:105] + node _T_302 = bits(dccm_rdata_hi_any, 3, 1) @[lib.scala 201:113] + node _T_303 = bits(dccm_data_ecc_hi_any, 2, 2) @[lib.scala 201:126] + node _T_304 = bits(dccm_rdata_hi_any, 0, 0) @[lib.scala 201:134] + node _T_305 = bits(dccm_data_ecc_hi_any, 1, 0) @[lib.scala 201:145] + node _T_306 = cat(_T_304, _T_305) @[Cat.scala 29:58] + node _T_307 = cat(_T_301, _T_302) @[Cat.scala 29:58] + node _T_308 = cat(_T_307, _T_303) @[Cat.scala 29:58] + node _T_309 = cat(_T_308, _T_306) @[Cat.scala 29:58] + node _T_310 = cat(_T_298, _T_299) @[Cat.scala 29:58] + node _T_311 = cat(_T_310, _T_300) @[Cat.scala 29:58] + node _T_312 = cat(_T_295, _T_296) @[Cat.scala 29:58] + node _T_313 = cat(_T_312, _T_297) @[Cat.scala 29:58] + node _T_314 = cat(_T_313, _T_311) @[Cat.scala 29:58] + node _T_315 = cat(_T_314, _T_309) @[Cat.scala 29:58] + node _T_316 = bits(single_ecc_error_hi_any, 0, 0) @[lib.scala 202:49] + node _T_317 = cat(_T_216[1], _T_216[0]) @[lib.scala 202:69] + node _T_318 = cat(_T_216[3], _T_216[2]) @[lib.scala 202:69] + node _T_319 = cat(_T_318, _T_317) @[lib.scala 202:69] + node _T_320 = cat(_T_216[5], _T_216[4]) @[lib.scala 202:69] + node _T_321 = cat(_T_216[8], _T_216[7]) @[lib.scala 202:69] + node _T_322 = cat(_T_321, _T_216[6]) @[lib.scala 202:69] + node _T_323 = cat(_T_322, _T_320) @[lib.scala 202:69] + node _T_324 = cat(_T_323, _T_319) @[lib.scala 202:69] + node _T_325 = cat(_T_216[10], _T_216[9]) @[lib.scala 202:69] + node _T_326 = cat(_T_216[13], _T_216[12]) @[lib.scala 202:69] + node _T_327 = cat(_T_326, _T_216[11]) @[lib.scala 202:69] + node _T_328 = cat(_T_327, _T_325) @[lib.scala 202:69] + node _T_329 = cat(_T_216[15], _T_216[14]) @[lib.scala 202:69] + node _T_330 = cat(_T_216[18], _T_216[17]) @[lib.scala 202:69] + node _T_331 = cat(_T_330, _T_216[16]) @[lib.scala 202:69] + node _T_332 = cat(_T_331, _T_329) @[lib.scala 202:69] + node _T_333 = cat(_T_332, _T_328) @[lib.scala 202:69] + node _T_334 = cat(_T_333, _T_324) @[lib.scala 202:69] + node _T_335 = cat(_T_216[20], _T_216[19]) @[lib.scala 202:69] + node _T_336 = cat(_T_216[23], _T_216[22]) @[lib.scala 202:69] + node _T_337 = cat(_T_336, _T_216[21]) @[lib.scala 202:69] + node _T_338 = cat(_T_337, _T_335) @[lib.scala 202:69] + node _T_339 = cat(_T_216[25], _T_216[24]) @[lib.scala 202:69] + node _T_340 = cat(_T_216[28], _T_216[27]) @[lib.scala 202:69] + node _T_341 = cat(_T_340, _T_216[26]) @[lib.scala 202:69] + node _T_342 = cat(_T_341, _T_339) @[lib.scala 202:69] + node _T_343 = cat(_T_342, _T_338) @[lib.scala 202:69] + node _T_344 = cat(_T_216[30], _T_216[29]) @[lib.scala 202:69] + node _T_345 = cat(_T_216[33], _T_216[32]) @[lib.scala 202:69] + node _T_346 = cat(_T_345, _T_216[31]) @[lib.scala 202:69] + node _T_347 = cat(_T_346, _T_344) @[lib.scala 202:69] + node _T_348 = cat(_T_216[35], _T_216[34]) @[lib.scala 202:69] + node _T_349 = cat(_T_216[38], _T_216[37]) @[lib.scala 202:69] + node _T_350 = cat(_T_349, _T_216[36]) @[lib.scala 202:69] + node _T_351 = cat(_T_350, _T_348) @[lib.scala 202:69] + node _T_352 = cat(_T_351, _T_347) @[lib.scala 202:69] + node _T_353 = cat(_T_352, _T_343) @[lib.scala 202:69] + node _T_354 = cat(_T_353, _T_334) @[lib.scala 202:69] + node _T_355 = xor(_T_354, _T_315) @[lib.scala 202:76] + node _T_356 = mux(_T_316, _T_355, _T_315) @[lib.scala 202:31] + node _T_357 = bits(_T_356, 37, 32) @[lib.scala 204:37] + node _T_358 = bits(_T_356, 30, 16) @[lib.scala 204:61] + node _T_359 = bits(_T_356, 14, 8) @[lib.scala 204:86] + node _T_360 = bits(_T_356, 6, 4) @[lib.scala 204:110] + node _T_361 = bits(_T_356, 2, 2) @[lib.scala 204:133] + node _T_362 = cat(_T_360, _T_361) @[Cat.scala 29:58] + node _T_363 = cat(_T_357, _T_358) @[Cat.scala 29:58] + node _T_364 = cat(_T_363, _T_359) @[Cat.scala 29:58] + node sec_data_hi_any = cat(_T_364, _T_362) @[Cat.scala 29:58] + node _T_365 = bits(_T_356, 38, 38) @[lib.scala 205:39] + node _T_366 = bits(_T_208, 6, 0) @[lib.scala 205:56] + node _T_367 = eq(_T_366, UInt<7>("h040")) @[lib.scala 205:62] + node _T_368 = xor(_T_365, _T_367) @[lib.scala 205:44] + node _T_369 = bits(_T_356, 31, 31) @[lib.scala 205:102] + node _T_370 = bits(_T_356, 15, 15) @[lib.scala 205:124] + node _T_371 = bits(_T_356, 7, 7) @[lib.scala 205:146] + node _T_372 = bits(_T_356, 3, 3) @[lib.scala 205:167] + node _T_373 = bits(_T_356, 1, 0) @[lib.scala 205:188] + node _T_374 = cat(_T_371, _T_372) @[Cat.scala 29:58] + node _T_375 = cat(_T_374, _T_373) @[Cat.scala 29:58] + node _T_376 = cat(_T_368, _T_369) @[Cat.scala 29:58] + node _T_377 = cat(_T_376, _T_370) @[Cat.scala 29:58] + node ecc_out_hi_nc = cat(_T_377, _T_375) @[Cat.scala 29:58] + wire _T_378 : UInt<1>[18] @[lib.scala 173:18] + wire _T_379 : UInt<1>[18] @[lib.scala 174:18] + wire _T_380 : UInt<1>[18] @[lib.scala 175:18] + wire _T_381 : UInt<1>[15] @[lib.scala 176:18] + wire _T_382 : UInt<1>[15] @[lib.scala 177:18] + wire _T_383 : UInt<1>[6] @[lib.scala 178:18] + node _T_384 = bits(dccm_rdata_lo_any, 0, 0) @[lib.scala 185:36] + _T_378[0] <= _T_384 @[lib.scala 185:30] + node _T_385 = bits(dccm_rdata_lo_any, 0, 0) @[lib.scala 186:36] + _T_379[0] <= _T_385 @[lib.scala 186:30] + node _T_386 = bits(dccm_rdata_lo_any, 1, 1) @[lib.scala 185:36] + _T_378[1] <= _T_386 @[lib.scala 185:30] + node _T_387 = bits(dccm_rdata_lo_any, 1, 1) @[lib.scala 187:36] + _T_380[0] <= _T_387 @[lib.scala 187:30] + node _T_388 = bits(dccm_rdata_lo_any, 2, 2) @[lib.scala 186:36] + _T_379[1] <= _T_388 @[lib.scala 186:30] + node _T_389 = bits(dccm_rdata_lo_any, 2, 2) @[lib.scala 187:36] + _T_380[1] <= _T_389 @[lib.scala 187:30] + node _T_390 = bits(dccm_rdata_lo_any, 3, 3) @[lib.scala 185:36] + _T_378[2] <= _T_390 @[lib.scala 185:30] + node _T_391 = bits(dccm_rdata_lo_any, 3, 3) @[lib.scala 186:36] + _T_379[2] <= _T_391 @[lib.scala 186:30] + node _T_392 = bits(dccm_rdata_lo_any, 3, 3) @[lib.scala 187:36] + _T_380[2] <= _T_392 @[lib.scala 187:30] + node _T_393 = bits(dccm_rdata_lo_any, 4, 4) @[lib.scala 185:36] + _T_378[3] <= _T_393 @[lib.scala 185:30] + node _T_394 = bits(dccm_rdata_lo_any, 4, 4) @[lib.scala 188:36] + _T_381[0] <= _T_394 @[lib.scala 188:30] + node _T_395 = bits(dccm_rdata_lo_any, 5, 5) @[lib.scala 186:36] + _T_379[3] <= _T_395 @[lib.scala 186:30] + node _T_396 = bits(dccm_rdata_lo_any, 5, 5) @[lib.scala 188:36] + _T_381[1] <= _T_396 @[lib.scala 188:30] + node _T_397 = bits(dccm_rdata_lo_any, 6, 6) @[lib.scala 185:36] + _T_378[4] <= _T_397 @[lib.scala 185:30] + node _T_398 = bits(dccm_rdata_lo_any, 6, 6) @[lib.scala 186:36] + _T_379[4] <= _T_398 @[lib.scala 186:30] + node _T_399 = bits(dccm_rdata_lo_any, 6, 6) @[lib.scala 188:36] + _T_381[2] <= _T_399 @[lib.scala 188:30] + node _T_400 = bits(dccm_rdata_lo_any, 7, 7) @[lib.scala 187:36] + _T_380[3] <= _T_400 @[lib.scala 187:30] + node _T_401 = bits(dccm_rdata_lo_any, 7, 7) @[lib.scala 188:36] + _T_381[3] <= _T_401 @[lib.scala 188:30] + node _T_402 = bits(dccm_rdata_lo_any, 8, 8) @[lib.scala 185:36] + _T_378[5] <= _T_402 @[lib.scala 185:30] + node _T_403 = bits(dccm_rdata_lo_any, 8, 8) @[lib.scala 187:36] + _T_380[4] <= _T_403 @[lib.scala 187:30] + node _T_404 = bits(dccm_rdata_lo_any, 8, 8) @[lib.scala 188:36] + _T_381[4] <= _T_404 @[lib.scala 188:30] + node _T_405 = bits(dccm_rdata_lo_any, 9, 9) @[lib.scala 186:36] + _T_379[5] <= _T_405 @[lib.scala 186:30] + node _T_406 = bits(dccm_rdata_lo_any, 9, 9) @[lib.scala 187:36] + _T_380[5] <= _T_406 @[lib.scala 187:30] + node _T_407 = bits(dccm_rdata_lo_any, 9, 9) @[lib.scala 188:36] + _T_381[5] <= _T_407 @[lib.scala 188:30] + node _T_408 = bits(dccm_rdata_lo_any, 10, 10) @[lib.scala 185:36] + _T_378[6] <= _T_408 @[lib.scala 185:30] + node _T_409 = bits(dccm_rdata_lo_any, 10, 10) @[lib.scala 186:36] + _T_379[6] <= _T_409 @[lib.scala 186:30] + node _T_410 = bits(dccm_rdata_lo_any, 10, 10) @[lib.scala 187:36] + _T_380[6] <= _T_410 @[lib.scala 187:30] + node _T_411 = bits(dccm_rdata_lo_any, 10, 10) @[lib.scala 188:36] + _T_381[6] <= _T_411 @[lib.scala 188:30] + node _T_412 = bits(dccm_rdata_lo_any, 11, 11) @[lib.scala 185:36] + _T_378[7] <= _T_412 @[lib.scala 185:30] + node _T_413 = bits(dccm_rdata_lo_any, 11, 11) @[lib.scala 189:36] + _T_382[0] <= _T_413 @[lib.scala 189:30] + node _T_414 = bits(dccm_rdata_lo_any, 12, 12) @[lib.scala 186:36] + _T_379[7] <= _T_414 @[lib.scala 186:30] + node _T_415 = bits(dccm_rdata_lo_any, 12, 12) @[lib.scala 189:36] + _T_382[1] <= _T_415 @[lib.scala 189:30] + node _T_416 = bits(dccm_rdata_lo_any, 13, 13) @[lib.scala 185:36] + _T_378[8] <= _T_416 @[lib.scala 185:30] + node _T_417 = bits(dccm_rdata_lo_any, 13, 13) @[lib.scala 186:36] + _T_379[8] <= _T_417 @[lib.scala 186:30] + node _T_418 = bits(dccm_rdata_lo_any, 13, 13) @[lib.scala 189:36] + _T_382[2] <= _T_418 @[lib.scala 189:30] + node _T_419 = bits(dccm_rdata_lo_any, 14, 14) @[lib.scala 187:36] + _T_380[7] <= _T_419 @[lib.scala 187:30] + node _T_420 = bits(dccm_rdata_lo_any, 14, 14) @[lib.scala 189:36] + _T_382[3] <= _T_420 @[lib.scala 189:30] + node _T_421 = bits(dccm_rdata_lo_any, 15, 15) @[lib.scala 185:36] + _T_378[9] <= _T_421 @[lib.scala 185:30] + node _T_422 = bits(dccm_rdata_lo_any, 15, 15) @[lib.scala 187:36] + _T_380[8] <= _T_422 @[lib.scala 187:30] + node _T_423 = bits(dccm_rdata_lo_any, 15, 15) @[lib.scala 189:36] + _T_382[4] <= _T_423 @[lib.scala 189:30] + node _T_424 = bits(dccm_rdata_lo_any, 16, 16) @[lib.scala 186:36] + _T_379[9] <= _T_424 @[lib.scala 186:30] + node _T_425 = bits(dccm_rdata_lo_any, 16, 16) @[lib.scala 187:36] + _T_380[9] <= _T_425 @[lib.scala 187:30] + node _T_426 = bits(dccm_rdata_lo_any, 16, 16) @[lib.scala 189:36] + _T_382[5] <= _T_426 @[lib.scala 189:30] + node _T_427 = bits(dccm_rdata_lo_any, 17, 17) @[lib.scala 185:36] + _T_378[10] <= _T_427 @[lib.scala 185:30] + node _T_428 = bits(dccm_rdata_lo_any, 17, 17) @[lib.scala 186:36] + _T_379[10] <= _T_428 @[lib.scala 186:30] + node _T_429 = bits(dccm_rdata_lo_any, 17, 17) @[lib.scala 187:36] + _T_380[10] <= _T_429 @[lib.scala 187:30] + node _T_430 = bits(dccm_rdata_lo_any, 17, 17) @[lib.scala 189:36] + _T_382[6] <= _T_430 @[lib.scala 189:30] + node _T_431 = bits(dccm_rdata_lo_any, 18, 18) @[lib.scala 188:36] + _T_381[7] <= _T_431 @[lib.scala 188:30] + node _T_432 = bits(dccm_rdata_lo_any, 18, 18) @[lib.scala 189:36] + _T_382[7] <= _T_432 @[lib.scala 189:30] + node _T_433 = bits(dccm_rdata_lo_any, 19, 19) @[lib.scala 185:36] + _T_378[11] <= _T_433 @[lib.scala 185:30] + node _T_434 = bits(dccm_rdata_lo_any, 19, 19) @[lib.scala 188:36] + _T_381[8] <= _T_434 @[lib.scala 188:30] + node _T_435 = bits(dccm_rdata_lo_any, 19, 19) @[lib.scala 189:36] + _T_382[8] <= _T_435 @[lib.scala 189:30] + node _T_436 = bits(dccm_rdata_lo_any, 20, 20) @[lib.scala 186:36] + _T_379[11] <= _T_436 @[lib.scala 186:30] + node _T_437 = bits(dccm_rdata_lo_any, 20, 20) @[lib.scala 188:36] + _T_381[9] <= _T_437 @[lib.scala 188:30] + node _T_438 = bits(dccm_rdata_lo_any, 20, 20) @[lib.scala 189:36] + _T_382[9] <= _T_438 @[lib.scala 189:30] + node _T_439 = bits(dccm_rdata_lo_any, 21, 21) @[lib.scala 185:36] + _T_378[12] <= _T_439 @[lib.scala 185:30] + node _T_440 = bits(dccm_rdata_lo_any, 21, 21) @[lib.scala 186:36] + _T_379[12] <= _T_440 @[lib.scala 186:30] + node _T_441 = bits(dccm_rdata_lo_any, 21, 21) @[lib.scala 188:36] + _T_381[10] <= _T_441 @[lib.scala 188:30] + node _T_442 = bits(dccm_rdata_lo_any, 21, 21) @[lib.scala 189:36] + _T_382[10] <= _T_442 @[lib.scala 189:30] + node _T_443 = bits(dccm_rdata_lo_any, 22, 22) @[lib.scala 187:36] + _T_380[11] <= _T_443 @[lib.scala 187:30] + node _T_444 = bits(dccm_rdata_lo_any, 22, 22) @[lib.scala 188:36] + _T_381[11] <= _T_444 @[lib.scala 188:30] + node _T_445 = bits(dccm_rdata_lo_any, 22, 22) @[lib.scala 189:36] + _T_382[11] <= _T_445 @[lib.scala 189:30] + node _T_446 = bits(dccm_rdata_lo_any, 23, 23) @[lib.scala 185:36] + _T_378[13] <= _T_446 @[lib.scala 185:30] + node _T_447 = bits(dccm_rdata_lo_any, 23, 23) @[lib.scala 187:36] + _T_380[12] <= _T_447 @[lib.scala 187:30] + node _T_448 = bits(dccm_rdata_lo_any, 23, 23) @[lib.scala 188:36] + _T_381[12] <= _T_448 @[lib.scala 188:30] + node _T_449 = bits(dccm_rdata_lo_any, 23, 23) @[lib.scala 189:36] + _T_382[12] <= _T_449 @[lib.scala 189:30] + node _T_450 = bits(dccm_rdata_lo_any, 24, 24) @[lib.scala 186:36] + _T_379[13] <= _T_450 @[lib.scala 186:30] + node _T_451 = bits(dccm_rdata_lo_any, 24, 24) @[lib.scala 187:36] + _T_380[13] <= _T_451 @[lib.scala 187:30] + node _T_452 = bits(dccm_rdata_lo_any, 24, 24) @[lib.scala 188:36] + _T_381[13] <= _T_452 @[lib.scala 188:30] + node _T_453 = bits(dccm_rdata_lo_any, 24, 24) @[lib.scala 189:36] + _T_382[13] <= _T_453 @[lib.scala 189:30] + node _T_454 = bits(dccm_rdata_lo_any, 25, 25) @[lib.scala 185:36] + _T_378[14] <= _T_454 @[lib.scala 185:30] + node _T_455 = bits(dccm_rdata_lo_any, 25, 25) @[lib.scala 186:36] + _T_379[14] <= _T_455 @[lib.scala 186:30] + node _T_456 = bits(dccm_rdata_lo_any, 25, 25) @[lib.scala 187:36] + _T_380[14] <= _T_456 @[lib.scala 187:30] + node _T_457 = bits(dccm_rdata_lo_any, 25, 25) @[lib.scala 188:36] + _T_381[14] <= _T_457 @[lib.scala 188:30] + node _T_458 = bits(dccm_rdata_lo_any, 25, 25) @[lib.scala 189:36] + _T_382[14] <= _T_458 @[lib.scala 189:30] + node _T_459 = bits(dccm_rdata_lo_any, 26, 26) @[lib.scala 185:36] + _T_378[15] <= _T_459 @[lib.scala 185:30] + node _T_460 = bits(dccm_rdata_lo_any, 26, 26) @[lib.scala 190:36] + _T_383[0] <= _T_460 @[lib.scala 190:30] + node _T_461 = bits(dccm_rdata_lo_any, 27, 27) @[lib.scala 186:36] + _T_379[15] <= _T_461 @[lib.scala 186:30] + node _T_462 = bits(dccm_rdata_lo_any, 27, 27) @[lib.scala 190:36] + _T_383[1] <= _T_462 @[lib.scala 190:30] + node _T_463 = bits(dccm_rdata_lo_any, 28, 28) @[lib.scala 185:36] + _T_378[16] <= _T_463 @[lib.scala 185:30] + node _T_464 = bits(dccm_rdata_lo_any, 28, 28) @[lib.scala 186:36] + _T_379[16] <= _T_464 @[lib.scala 186:30] + node _T_465 = bits(dccm_rdata_lo_any, 28, 28) @[lib.scala 190:36] + _T_383[2] <= _T_465 @[lib.scala 190:30] + node _T_466 = bits(dccm_rdata_lo_any, 29, 29) @[lib.scala 187:36] + _T_380[15] <= _T_466 @[lib.scala 187:30] + node _T_467 = bits(dccm_rdata_lo_any, 29, 29) @[lib.scala 190:36] + _T_383[3] <= _T_467 @[lib.scala 190:30] + node _T_468 = bits(dccm_rdata_lo_any, 30, 30) @[lib.scala 185:36] + _T_378[17] <= _T_468 @[lib.scala 185:30] + node _T_469 = bits(dccm_rdata_lo_any, 30, 30) @[lib.scala 187:36] + _T_380[16] <= _T_469 @[lib.scala 187:30] + node _T_470 = bits(dccm_rdata_lo_any, 30, 30) @[lib.scala 190:36] + _T_383[4] <= _T_470 @[lib.scala 190:30] + node _T_471 = bits(dccm_rdata_lo_any, 31, 31) @[lib.scala 186:36] + _T_379[17] <= _T_471 @[lib.scala 186:30] + node _T_472 = bits(dccm_rdata_lo_any, 31, 31) @[lib.scala 187:36] + _T_380[17] <= _T_472 @[lib.scala 187:30] + node _T_473 = bits(dccm_rdata_lo_any, 31, 31) @[lib.scala 190:36] + _T_383[5] <= _T_473 @[lib.scala 190:30] + node _T_474 = xorr(dccm_rdata_lo_any) @[lib.scala 193:30] + node _T_475 = xorr(dccm_data_ecc_lo_any) @[lib.scala 193:44] + node _T_476 = xor(_T_474, _T_475) @[lib.scala 193:35] + node _T_477 = not(UInt<1>("h00")) @[lib.scala 193:52] + node _T_478 = and(_T_476, _T_477) @[lib.scala 193:50] + node _T_479 = bits(dccm_data_ecc_lo_any, 5, 5) @[lib.scala 193:68] + node _T_480 = cat(_T_383[2], _T_383[1]) @[lib.scala 193:76] + node _T_481 = cat(_T_480, _T_383[0]) @[lib.scala 193:76] + node _T_482 = cat(_T_383[5], _T_383[4]) @[lib.scala 193:76] + node _T_483 = cat(_T_482, _T_383[3]) @[lib.scala 193:76] + node _T_484 = cat(_T_483, _T_481) @[lib.scala 193:76] + node _T_485 = xorr(_T_484) @[lib.scala 193:83] + node _T_486 = xor(_T_479, _T_485) @[lib.scala 193:71] + node _T_487 = bits(dccm_data_ecc_lo_any, 4, 4) @[lib.scala 193:95] + node _T_488 = cat(_T_382[2], _T_382[1]) @[lib.scala 193:103] + node _T_489 = cat(_T_488, _T_382[0]) @[lib.scala 193:103] + node _T_490 = cat(_T_382[4], _T_382[3]) @[lib.scala 193:103] + node _T_491 = cat(_T_382[6], _T_382[5]) @[lib.scala 193:103] + node _T_492 = cat(_T_491, _T_490) @[lib.scala 193:103] + node _T_493 = cat(_T_492, _T_489) @[lib.scala 193:103] + node _T_494 = cat(_T_382[8], _T_382[7]) @[lib.scala 193:103] + node _T_495 = cat(_T_382[10], _T_382[9]) @[lib.scala 193:103] + node _T_496 = cat(_T_495, _T_494) @[lib.scala 193:103] + node _T_497 = cat(_T_382[12], _T_382[11]) @[lib.scala 193:103] + node _T_498 = cat(_T_382[14], _T_382[13]) @[lib.scala 193:103] + node _T_499 = cat(_T_498, _T_497) @[lib.scala 193:103] + node _T_500 = cat(_T_499, _T_496) @[lib.scala 193:103] + node _T_501 = cat(_T_500, _T_493) @[lib.scala 193:103] + node _T_502 = xorr(_T_501) @[lib.scala 193:110] + node _T_503 = xor(_T_487, _T_502) @[lib.scala 193:98] + node _T_504 = bits(dccm_data_ecc_lo_any, 3, 3) @[lib.scala 193:122] + node _T_505 = cat(_T_381[2], _T_381[1]) @[lib.scala 193:130] + node _T_506 = cat(_T_505, _T_381[0]) @[lib.scala 193:130] + node _T_507 = cat(_T_381[4], _T_381[3]) @[lib.scala 193:130] + node _T_508 = cat(_T_381[6], _T_381[5]) @[lib.scala 193:130] + node _T_509 = cat(_T_508, _T_507) @[lib.scala 193:130] + node _T_510 = cat(_T_509, _T_506) @[lib.scala 193:130] + node _T_511 = cat(_T_381[8], _T_381[7]) @[lib.scala 193:130] + node _T_512 = cat(_T_381[10], _T_381[9]) @[lib.scala 193:130] + node _T_513 = cat(_T_512, _T_511) @[lib.scala 193:130] + node _T_514 = cat(_T_381[12], _T_381[11]) @[lib.scala 193:130] + node _T_515 = cat(_T_381[14], _T_381[13]) @[lib.scala 193:130] + node _T_516 = cat(_T_515, _T_514) @[lib.scala 193:130] + node _T_517 = cat(_T_516, _T_513) @[lib.scala 193:130] + node _T_518 = cat(_T_517, _T_510) @[lib.scala 193:130] + node _T_519 = xorr(_T_518) @[lib.scala 193:137] + node _T_520 = xor(_T_504, _T_519) @[lib.scala 193:125] + node _T_521 = bits(dccm_data_ecc_lo_any, 2, 2) @[lib.scala 193:149] + node _T_522 = cat(_T_380[1], _T_380[0]) @[lib.scala 193:157] + node _T_523 = cat(_T_380[3], _T_380[2]) @[lib.scala 193:157] + node _T_524 = cat(_T_523, _T_522) @[lib.scala 193:157] + node _T_525 = cat(_T_380[5], _T_380[4]) @[lib.scala 193:157] + node _T_526 = cat(_T_380[8], _T_380[7]) @[lib.scala 193:157] + node _T_527 = cat(_T_526, _T_380[6]) @[lib.scala 193:157] + node _T_528 = cat(_T_527, _T_525) @[lib.scala 193:157] + node _T_529 = cat(_T_528, _T_524) @[lib.scala 193:157] + node _T_530 = cat(_T_380[10], _T_380[9]) @[lib.scala 193:157] + node _T_531 = cat(_T_380[12], _T_380[11]) @[lib.scala 193:157] + node _T_532 = cat(_T_531, _T_530) @[lib.scala 193:157] + node _T_533 = cat(_T_380[14], _T_380[13]) @[lib.scala 193:157] + node _T_534 = cat(_T_380[17], _T_380[16]) @[lib.scala 193:157] + node _T_535 = cat(_T_534, _T_380[15]) @[lib.scala 193:157] + node _T_536 = cat(_T_535, _T_533) @[lib.scala 193:157] + node _T_537 = cat(_T_536, _T_532) @[lib.scala 193:157] + node _T_538 = cat(_T_537, _T_529) @[lib.scala 193:157] + node _T_539 = xorr(_T_538) @[lib.scala 193:164] + node _T_540 = xor(_T_521, _T_539) @[lib.scala 193:152] + node _T_541 = bits(dccm_data_ecc_lo_any, 1, 1) @[lib.scala 193:176] + node _T_542 = cat(_T_379[1], _T_379[0]) @[lib.scala 193:184] + node _T_543 = cat(_T_379[3], _T_379[2]) @[lib.scala 193:184] + node _T_544 = cat(_T_543, _T_542) @[lib.scala 193:184] + node _T_545 = cat(_T_379[5], _T_379[4]) @[lib.scala 193:184] + node _T_546 = cat(_T_379[8], _T_379[7]) @[lib.scala 193:184] + node _T_547 = cat(_T_546, _T_379[6]) @[lib.scala 193:184] + node _T_548 = cat(_T_547, _T_545) @[lib.scala 193:184] + node _T_549 = cat(_T_548, _T_544) @[lib.scala 193:184] + node _T_550 = cat(_T_379[10], _T_379[9]) @[lib.scala 193:184] + node _T_551 = cat(_T_379[12], _T_379[11]) @[lib.scala 193:184] + node _T_552 = cat(_T_551, _T_550) @[lib.scala 193:184] + node _T_553 = cat(_T_379[14], _T_379[13]) @[lib.scala 193:184] + node _T_554 = cat(_T_379[17], _T_379[16]) @[lib.scala 193:184] + node _T_555 = cat(_T_554, _T_379[15]) @[lib.scala 193:184] + node _T_556 = cat(_T_555, _T_553) @[lib.scala 193:184] + node _T_557 = cat(_T_556, _T_552) @[lib.scala 193:184] + node _T_558 = cat(_T_557, _T_549) @[lib.scala 193:184] + node _T_559 = xorr(_T_558) @[lib.scala 193:191] + node _T_560 = xor(_T_541, _T_559) @[lib.scala 193:179] + node _T_561 = bits(dccm_data_ecc_lo_any, 0, 0) @[lib.scala 193:203] + node _T_562 = cat(_T_378[1], _T_378[0]) @[lib.scala 193:211] + node _T_563 = cat(_T_378[3], _T_378[2]) @[lib.scala 193:211] + node _T_564 = cat(_T_563, _T_562) @[lib.scala 193:211] + node _T_565 = cat(_T_378[5], _T_378[4]) @[lib.scala 193:211] + node _T_566 = cat(_T_378[8], _T_378[7]) @[lib.scala 193:211] + node _T_567 = cat(_T_566, _T_378[6]) @[lib.scala 193:211] + node _T_568 = cat(_T_567, _T_565) @[lib.scala 193:211] + node _T_569 = cat(_T_568, _T_564) @[lib.scala 193:211] + node _T_570 = cat(_T_378[10], _T_378[9]) @[lib.scala 193:211] + node _T_571 = cat(_T_378[12], _T_378[11]) @[lib.scala 193:211] + node _T_572 = cat(_T_571, _T_570) @[lib.scala 193:211] + node _T_573 = cat(_T_378[14], _T_378[13]) @[lib.scala 193:211] + node _T_574 = cat(_T_378[17], _T_378[16]) @[lib.scala 193:211] + node _T_575 = cat(_T_574, _T_378[15]) @[lib.scala 193:211] + node _T_576 = cat(_T_575, _T_573) @[lib.scala 193:211] + node _T_577 = cat(_T_576, _T_572) @[lib.scala 193:211] + node _T_578 = cat(_T_577, _T_569) @[lib.scala 193:211] + node _T_579 = xorr(_T_578) @[lib.scala 193:218] + node _T_580 = xor(_T_561, _T_579) @[lib.scala 193:206] + node _T_581 = cat(_T_540, _T_560) @[Cat.scala 29:58] + node _T_582 = cat(_T_581, _T_580) @[Cat.scala 29:58] + node _T_583 = cat(_T_503, _T_520) @[Cat.scala 29:58] + node _T_584 = cat(_T_478, _T_486) @[Cat.scala 29:58] + node _T_585 = cat(_T_584, _T_583) @[Cat.scala 29:58] + node _T_586 = cat(_T_585, _T_582) @[Cat.scala 29:58] + node _T_587 = neq(_T_586, UInt<1>("h00")) @[lib.scala 194:44] + node _T_588 = and(is_ldst_lo_any, _T_587) @[lib.scala 194:32] + node _T_589 = bits(_T_586, 6, 6) @[lib.scala 194:64] + node single_ecc_error_lo_any = and(_T_588, _T_589) @[lib.scala 194:53] + node _T_590 = neq(_T_586, UInt<1>("h00")) @[lib.scala 195:44] + node _T_591 = and(is_ldst_lo_any, _T_590) @[lib.scala 195:32] + node _T_592 = bits(_T_586, 6, 6) @[lib.scala 195:65] + node _T_593 = not(_T_592) @[lib.scala 195:55] + node double_ecc_error_lo_any = and(_T_591, _T_593) @[lib.scala 195:53] + wire _T_594 : UInt<1>[39] @[lib.scala 196:26] + node _T_595 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_596 = eq(_T_595, UInt<1>("h01")) @[lib.scala 199:41] + _T_594[0] <= _T_596 @[lib.scala 199:23] + node _T_597 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_598 = eq(_T_597, UInt<2>("h02")) @[lib.scala 199:41] + _T_594[1] <= _T_598 @[lib.scala 199:23] + node _T_599 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_600 = eq(_T_599, UInt<2>("h03")) @[lib.scala 199:41] + _T_594[2] <= _T_600 @[lib.scala 199:23] + node _T_601 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_602 = eq(_T_601, UInt<3>("h04")) @[lib.scala 199:41] + _T_594[3] <= _T_602 @[lib.scala 199:23] + node _T_603 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_604 = eq(_T_603, UInt<3>("h05")) @[lib.scala 199:41] + _T_594[4] <= _T_604 @[lib.scala 199:23] + node _T_605 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_606 = eq(_T_605, UInt<3>("h06")) @[lib.scala 199:41] + _T_594[5] <= _T_606 @[lib.scala 199:23] + node _T_607 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_608 = eq(_T_607, UInt<3>("h07")) @[lib.scala 199:41] + _T_594[6] <= _T_608 @[lib.scala 199:23] + node _T_609 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_610 = eq(_T_609, UInt<4>("h08")) @[lib.scala 199:41] + _T_594[7] <= _T_610 @[lib.scala 199:23] + node _T_611 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_612 = eq(_T_611, UInt<4>("h09")) @[lib.scala 199:41] + _T_594[8] <= _T_612 @[lib.scala 199:23] + node _T_613 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_614 = eq(_T_613, UInt<4>("h0a")) @[lib.scala 199:41] + _T_594[9] <= _T_614 @[lib.scala 199:23] + node _T_615 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_616 = eq(_T_615, UInt<4>("h0b")) @[lib.scala 199:41] + _T_594[10] <= _T_616 @[lib.scala 199:23] + node _T_617 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_618 = eq(_T_617, UInt<4>("h0c")) @[lib.scala 199:41] + _T_594[11] <= _T_618 @[lib.scala 199:23] + node _T_619 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_620 = eq(_T_619, UInt<4>("h0d")) @[lib.scala 199:41] + _T_594[12] <= _T_620 @[lib.scala 199:23] + node _T_621 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_622 = eq(_T_621, UInt<4>("h0e")) @[lib.scala 199:41] + _T_594[13] <= _T_622 @[lib.scala 199:23] + node _T_623 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_624 = eq(_T_623, UInt<4>("h0f")) @[lib.scala 199:41] + _T_594[14] <= _T_624 @[lib.scala 199:23] + node _T_625 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_626 = eq(_T_625, UInt<5>("h010")) @[lib.scala 199:41] + _T_594[15] <= _T_626 @[lib.scala 199:23] + node _T_627 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_628 = eq(_T_627, UInt<5>("h011")) @[lib.scala 199:41] + _T_594[16] <= _T_628 @[lib.scala 199:23] + node _T_629 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_630 = eq(_T_629, UInt<5>("h012")) @[lib.scala 199:41] + _T_594[17] <= _T_630 @[lib.scala 199:23] + node _T_631 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_632 = eq(_T_631, UInt<5>("h013")) @[lib.scala 199:41] + _T_594[18] <= _T_632 @[lib.scala 199:23] + node _T_633 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_634 = eq(_T_633, UInt<5>("h014")) @[lib.scala 199:41] + _T_594[19] <= _T_634 @[lib.scala 199:23] + node _T_635 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_636 = eq(_T_635, UInt<5>("h015")) @[lib.scala 199:41] + _T_594[20] <= _T_636 @[lib.scala 199:23] + node _T_637 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_638 = eq(_T_637, UInt<5>("h016")) @[lib.scala 199:41] + _T_594[21] <= _T_638 @[lib.scala 199:23] + node _T_639 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_640 = eq(_T_639, UInt<5>("h017")) @[lib.scala 199:41] + _T_594[22] <= _T_640 @[lib.scala 199:23] + node _T_641 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_642 = eq(_T_641, UInt<5>("h018")) @[lib.scala 199:41] + _T_594[23] <= _T_642 @[lib.scala 199:23] + node _T_643 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_644 = eq(_T_643, UInt<5>("h019")) @[lib.scala 199:41] + _T_594[24] <= _T_644 @[lib.scala 199:23] + node _T_645 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_646 = eq(_T_645, UInt<5>("h01a")) @[lib.scala 199:41] + _T_594[25] <= _T_646 @[lib.scala 199:23] + node _T_647 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_648 = eq(_T_647, UInt<5>("h01b")) @[lib.scala 199:41] + _T_594[26] <= _T_648 @[lib.scala 199:23] + node _T_649 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_650 = eq(_T_649, UInt<5>("h01c")) @[lib.scala 199:41] + _T_594[27] <= _T_650 @[lib.scala 199:23] + node _T_651 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_652 = eq(_T_651, UInt<5>("h01d")) @[lib.scala 199:41] + _T_594[28] <= _T_652 @[lib.scala 199:23] + node _T_653 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_654 = eq(_T_653, UInt<5>("h01e")) @[lib.scala 199:41] + _T_594[29] <= _T_654 @[lib.scala 199:23] + node _T_655 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_656 = eq(_T_655, UInt<5>("h01f")) @[lib.scala 199:41] + _T_594[30] <= _T_656 @[lib.scala 199:23] + node _T_657 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_658 = eq(_T_657, UInt<6>("h020")) @[lib.scala 199:41] + _T_594[31] <= _T_658 @[lib.scala 199:23] + node _T_659 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_660 = eq(_T_659, UInt<6>("h021")) @[lib.scala 199:41] + _T_594[32] <= _T_660 @[lib.scala 199:23] + node _T_661 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_662 = eq(_T_661, UInt<6>("h022")) @[lib.scala 199:41] + _T_594[33] <= _T_662 @[lib.scala 199:23] + node _T_663 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_664 = eq(_T_663, UInt<6>("h023")) @[lib.scala 199:41] + _T_594[34] <= _T_664 @[lib.scala 199:23] + node _T_665 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_666 = eq(_T_665, UInt<6>("h024")) @[lib.scala 199:41] + _T_594[35] <= _T_666 @[lib.scala 199:23] + node _T_667 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_668 = eq(_T_667, UInt<6>("h025")) @[lib.scala 199:41] + _T_594[36] <= _T_668 @[lib.scala 199:23] + node _T_669 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_670 = eq(_T_669, UInt<6>("h026")) @[lib.scala 199:41] + _T_594[37] <= _T_670 @[lib.scala 199:23] + node _T_671 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_672 = eq(_T_671, UInt<6>("h027")) @[lib.scala 199:41] + _T_594[38] <= _T_672 @[lib.scala 199:23] + node _T_673 = bits(dccm_data_ecc_lo_any, 6, 6) @[lib.scala 201:37] + node _T_674 = bits(dccm_rdata_lo_any, 31, 26) @[lib.scala 201:45] + node _T_675 = bits(dccm_data_ecc_lo_any, 5, 5) @[lib.scala 201:60] + node _T_676 = bits(dccm_rdata_lo_any, 25, 11) @[lib.scala 201:68] + node _T_677 = bits(dccm_data_ecc_lo_any, 4, 4) @[lib.scala 201:83] + node _T_678 = bits(dccm_rdata_lo_any, 10, 4) @[lib.scala 201:91] + node _T_679 = bits(dccm_data_ecc_lo_any, 3, 3) @[lib.scala 201:105] + node _T_680 = bits(dccm_rdata_lo_any, 3, 1) @[lib.scala 201:113] + node _T_681 = bits(dccm_data_ecc_lo_any, 2, 2) @[lib.scala 201:126] + node _T_682 = bits(dccm_rdata_lo_any, 0, 0) @[lib.scala 201:134] + node _T_683 = bits(dccm_data_ecc_lo_any, 1, 0) @[lib.scala 201:145] + node _T_684 = cat(_T_682, _T_683) @[Cat.scala 29:58] + node _T_685 = cat(_T_679, _T_680) @[Cat.scala 29:58] + node _T_686 = cat(_T_685, _T_681) @[Cat.scala 29:58] + node _T_687 = cat(_T_686, _T_684) @[Cat.scala 29:58] + node _T_688 = cat(_T_676, _T_677) @[Cat.scala 29:58] + node _T_689 = cat(_T_688, _T_678) @[Cat.scala 29:58] + node _T_690 = cat(_T_673, _T_674) @[Cat.scala 29:58] + node _T_691 = cat(_T_690, _T_675) @[Cat.scala 29:58] + node _T_692 = cat(_T_691, _T_689) @[Cat.scala 29:58] + node _T_693 = cat(_T_692, _T_687) @[Cat.scala 29:58] + node _T_694 = bits(single_ecc_error_lo_any, 0, 0) @[lib.scala 202:49] + node _T_695 = cat(_T_594[1], _T_594[0]) @[lib.scala 202:69] + node _T_696 = cat(_T_594[3], _T_594[2]) @[lib.scala 202:69] + node _T_697 = cat(_T_696, _T_695) @[lib.scala 202:69] + node _T_698 = cat(_T_594[5], _T_594[4]) @[lib.scala 202:69] + node _T_699 = cat(_T_594[8], _T_594[7]) @[lib.scala 202:69] + node _T_700 = cat(_T_699, _T_594[6]) @[lib.scala 202:69] + node _T_701 = cat(_T_700, _T_698) @[lib.scala 202:69] + node _T_702 = cat(_T_701, _T_697) @[lib.scala 202:69] + node _T_703 = cat(_T_594[10], _T_594[9]) @[lib.scala 202:69] + node _T_704 = cat(_T_594[13], _T_594[12]) @[lib.scala 202:69] + node _T_705 = cat(_T_704, _T_594[11]) @[lib.scala 202:69] + node _T_706 = cat(_T_705, _T_703) @[lib.scala 202:69] + node _T_707 = cat(_T_594[15], _T_594[14]) @[lib.scala 202:69] + node _T_708 = cat(_T_594[18], _T_594[17]) @[lib.scala 202:69] + node _T_709 = cat(_T_708, _T_594[16]) @[lib.scala 202:69] + node _T_710 = cat(_T_709, _T_707) @[lib.scala 202:69] + node _T_711 = cat(_T_710, _T_706) @[lib.scala 202:69] + node _T_712 = cat(_T_711, _T_702) @[lib.scala 202:69] + node _T_713 = cat(_T_594[20], _T_594[19]) @[lib.scala 202:69] + node _T_714 = cat(_T_594[23], _T_594[22]) @[lib.scala 202:69] + node _T_715 = cat(_T_714, _T_594[21]) @[lib.scala 202:69] + node _T_716 = cat(_T_715, _T_713) @[lib.scala 202:69] + node _T_717 = cat(_T_594[25], _T_594[24]) @[lib.scala 202:69] + node _T_718 = cat(_T_594[28], _T_594[27]) @[lib.scala 202:69] + node _T_719 = cat(_T_718, _T_594[26]) @[lib.scala 202:69] + node _T_720 = cat(_T_719, _T_717) @[lib.scala 202:69] + node _T_721 = cat(_T_720, _T_716) @[lib.scala 202:69] + node _T_722 = cat(_T_594[30], _T_594[29]) @[lib.scala 202:69] + node _T_723 = cat(_T_594[33], _T_594[32]) @[lib.scala 202:69] + node _T_724 = cat(_T_723, _T_594[31]) @[lib.scala 202:69] + node _T_725 = cat(_T_724, _T_722) @[lib.scala 202:69] + node _T_726 = cat(_T_594[35], _T_594[34]) @[lib.scala 202:69] + node _T_727 = cat(_T_594[38], _T_594[37]) @[lib.scala 202:69] + node _T_728 = cat(_T_727, _T_594[36]) @[lib.scala 202:69] + node _T_729 = cat(_T_728, _T_726) @[lib.scala 202:69] + node _T_730 = cat(_T_729, _T_725) @[lib.scala 202:69] + node _T_731 = cat(_T_730, _T_721) @[lib.scala 202:69] + node _T_732 = cat(_T_731, _T_712) @[lib.scala 202:69] + node _T_733 = xor(_T_732, _T_693) @[lib.scala 202:76] + node _T_734 = mux(_T_694, _T_733, _T_693) @[lib.scala 202:31] + node _T_735 = bits(_T_734, 37, 32) @[lib.scala 204:37] + node _T_736 = bits(_T_734, 30, 16) @[lib.scala 204:61] + node _T_737 = bits(_T_734, 14, 8) @[lib.scala 204:86] + node _T_738 = bits(_T_734, 6, 4) @[lib.scala 204:110] + node _T_739 = bits(_T_734, 2, 2) @[lib.scala 204:133] + node _T_740 = cat(_T_738, _T_739) @[Cat.scala 29:58] + node _T_741 = cat(_T_735, _T_736) @[Cat.scala 29:58] + node _T_742 = cat(_T_741, _T_737) @[Cat.scala 29:58] + node sec_data_lo_any = cat(_T_742, _T_740) @[Cat.scala 29:58] + node _T_743 = bits(_T_734, 38, 38) @[lib.scala 205:39] + node _T_744 = bits(_T_586, 6, 0) @[lib.scala 205:56] + node _T_745 = eq(_T_744, UInt<7>("h040")) @[lib.scala 205:62] + node _T_746 = xor(_T_743, _T_745) @[lib.scala 205:44] + node _T_747 = bits(_T_734, 31, 31) @[lib.scala 205:102] + node _T_748 = bits(_T_734, 15, 15) @[lib.scala 205:124] + node _T_749 = bits(_T_734, 7, 7) @[lib.scala 205:146] + node _T_750 = bits(_T_734, 3, 3) @[lib.scala 205:167] + node _T_751 = bits(_T_734, 1, 0) @[lib.scala 205:188] + node _T_752 = cat(_T_749, _T_750) @[Cat.scala 29:58] + node _T_753 = cat(_T_752, _T_751) @[Cat.scala 29:58] + node _T_754 = cat(_T_746, _T_747) @[Cat.scala 29:58] + node _T_755 = cat(_T_754, _T_748) @[Cat.scala 29:58] + node ecc_out_lo_nc = cat(_T_755, _T_753) @[Cat.scala 29:58] + node _T_756 = bits(dccm_wdata_lo_any, 0, 0) @[lib.scala 119:58] + node _T_757 = bits(dccm_wdata_lo_any, 1, 1) @[lib.scala 119:58] + node _T_758 = bits(dccm_wdata_lo_any, 3, 3) @[lib.scala 119:58] + node _T_759 = bits(dccm_wdata_lo_any, 4, 4) @[lib.scala 119:58] + node _T_760 = bits(dccm_wdata_lo_any, 6, 6) @[lib.scala 119:58] + node _T_761 = bits(dccm_wdata_lo_any, 8, 8) @[lib.scala 119:58] + node _T_762 = bits(dccm_wdata_lo_any, 10, 10) @[lib.scala 119:58] + node _T_763 = bits(dccm_wdata_lo_any, 11, 11) @[lib.scala 119:58] + node _T_764 = bits(dccm_wdata_lo_any, 13, 13) @[lib.scala 119:58] + node _T_765 = bits(dccm_wdata_lo_any, 15, 15) @[lib.scala 119:58] + node _T_766 = bits(dccm_wdata_lo_any, 17, 17) @[lib.scala 119:58] + node _T_767 = bits(dccm_wdata_lo_any, 19, 19) @[lib.scala 119:58] + node _T_768 = bits(dccm_wdata_lo_any, 21, 21) @[lib.scala 119:58] + node _T_769 = bits(dccm_wdata_lo_any, 23, 23) @[lib.scala 119:58] + node _T_770 = bits(dccm_wdata_lo_any, 25, 25) @[lib.scala 119:58] + node _T_771 = bits(dccm_wdata_lo_any, 26, 26) @[lib.scala 119:58] + node _T_772 = bits(dccm_wdata_lo_any, 28, 28) @[lib.scala 119:58] + node _T_773 = bits(dccm_wdata_lo_any, 30, 30) @[lib.scala 119:58] + node _T_774 = xor(_T_756, _T_757) @[lib.scala 119:74] + node _T_775 = xor(_T_774, _T_758) @[lib.scala 119:74] + node _T_776 = xor(_T_775, _T_759) @[lib.scala 119:74] + node _T_777 = xor(_T_776, _T_760) @[lib.scala 119:74] + node _T_778 = xor(_T_777, _T_761) @[lib.scala 119:74] + node _T_779 = xor(_T_778, _T_762) @[lib.scala 119:74] + node _T_780 = xor(_T_779, _T_763) @[lib.scala 119:74] + node _T_781 = xor(_T_780, _T_764) @[lib.scala 119:74] + node _T_782 = xor(_T_781, _T_765) @[lib.scala 119:74] + node _T_783 = xor(_T_782, _T_766) @[lib.scala 119:74] + node _T_784 = xor(_T_783, _T_767) @[lib.scala 119:74] + node _T_785 = xor(_T_784, _T_768) @[lib.scala 119:74] + node _T_786 = xor(_T_785, _T_769) @[lib.scala 119:74] + node _T_787 = xor(_T_786, _T_770) @[lib.scala 119:74] + node _T_788 = xor(_T_787, _T_771) @[lib.scala 119:74] + node _T_789 = xor(_T_788, _T_772) @[lib.scala 119:74] + node _T_790 = xor(_T_789, _T_773) @[lib.scala 119:74] + node _T_791 = bits(dccm_wdata_lo_any, 0, 0) @[lib.scala 119:58] + node _T_792 = bits(dccm_wdata_lo_any, 2, 2) @[lib.scala 119:58] + node _T_793 = bits(dccm_wdata_lo_any, 3, 3) @[lib.scala 119:58] + node _T_794 = bits(dccm_wdata_lo_any, 5, 5) @[lib.scala 119:58] + node _T_795 = bits(dccm_wdata_lo_any, 6, 6) @[lib.scala 119:58] + node _T_796 = bits(dccm_wdata_lo_any, 9, 9) @[lib.scala 119:58] + node _T_797 = bits(dccm_wdata_lo_any, 10, 10) @[lib.scala 119:58] + node _T_798 = bits(dccm_wdata_lo_any, 12, 12) @[lib.scala 119:58] + node _T_799 = bits(dccm_wdata_lo_any, 13, 13) @[lib.scala 119:58] + node _T_800 = bits(dccm_wdata_lo_any, 16, 16) @[lib.scala 119:58] + node _T_801 = bits(dccm_wdata_lo_any, 17, 17) @[lib.scala 119:58] + node _T_802 = bits(dccm_wdata_lo_any, 20, 20) @[lib.scala 119:58] + node _T_803 = bits(dccm_wdata_lo_any, 21, 21) @[lib.scala 119:58] + node _T_804 = bits(dccm_wdata_lo_any, 24, 24) @[lib.scala 119:58] + node _T_805 = bits(dccm_wdata_lo_any, 25, 25) @[lib.scala 119:58] + node _T_806 = bits(dccm_wdata_lo_any, 27, 27) @[lib.scala 119:58] + node _T_807 = bits(dccm_wdata_lo_any, 28, 28) @[lib.scala 119:58] + node _T_808 = bits(dccm_wdata_lo_any, 31, 31) @[lib.scala 119:58] + node _T_809 = xor(_T_791, _T_792) @[lib.scala 119:74] + node _T_810 = xor(_T_809, _T_793) @[lib.scala 119:74] + node _T_811 = xor(_T_810, _T_794) @[lib.scala 119:74] + node _T_812 = xor(_T_811, _T_795) @[lib.scala 119:74] + node _T_813 = xor(_T_812, _T_796) @[lib.scala 119:74] + node _T_814 = xor(_T_813, _T_797) @[lib.scala 119:74] + node _T_815 = xor(_T_814, _T_798) @[lib.scala 119:74] + node _T_816 = xor(_T_815, _T_799) @[lib.scala 119:74] + node _T_817 = xor(_T_816, _T_800) @[lib.scala 119:74] + node _T_818 = xor(_T_817, _T_801) @[lib.scala 119:74] + node _T_819 = xor(_T_818, _T_802) @[lib.scala 119:74] + node _T_820 = xor(_T_819, _T_803) @[lib.scala 119:74] + node _T_821 = xor(_T_820, _T_804) @[lib.scala 119:74] + node _T_822 = xor(_T_821, _T_805) @[lib.scala 119:74] + node _T_823 = xor(_T_822, _T_806) @[lib.scala 119:74] + node _T_824 = xor(_T_823, _T_807) @[lib.scala 119:74] + node _T_825 = xor(_T_824, _T_808) @[lib.scala 119:74] + node _T_826 = bits(dccm_wdata_lo_any, 1, 1) @[lib.scala 119:58] + node _T_827 = bits(dccm_wdata_lo_any, 2, 2) @[lib.scala 119:58] + node _T_828 = bits(dccm_wdata_lo_any, 3, 3) @[lib.scala 119:58] + node _T_829 = bits(dccm_wdata_lo_any, 7, 7) @[lib.scala 119:58] + node _T_830 = bits(dccm_wdata_lo_any, 8, 8) @[lib.scala 119:58] + node _T_831 = bits(dccm_wdata_lo_any, 9, 9) @[lib.scala 119:58] + node _T_832 = bits(dccm_wdata_lo_any, 10, 10) @[lib.scala 119:58] + node _T_833 = bits(dccm_wdata_lo_any, 14, 14) @[lib.scala 119:58] + node _T_834 = bits(dccm_wdata_lo_any, 15, 15) @[lib.scala 119:58] + node _T_835 = bits(dccm_wdata_lo_any, 16, 16) @[lib.scala 119:58] + node _T_836 = bits(dccm_wdata_lo_any, 17, 17) @[lib.scala 119:58] + node _T_837 = bits(dccm_wdata_lo_any, 22, 22) @[lib.scala 119:58] + node _T_838 = bits(dccm_wdata_lo_any, 23, 23) @[lib.scala 119:58] + node _T_839 = bits(dccm_wdata_lo_any, 24, 24) @[lib.scala 119:58] + node _T_840 = bits(dccm_wdata_lo_any, 25, 25) @[lib.scala 119:58] + node _T_841 = bits(dccm_wdata_lo_any, 29, 29) @[lib.scala 119:58] + node _T_842 = bits(dccm_wdata_lo_any, 30, 30) @[lib.scala 119:58] + node _T_843 = bits(dccm_wdata_lo_any, 31, 31) @[lib.scala 119:58] + node _T_844 = xor(_T_826, _T_827) @[lib.scala 119:74] + node _T_845 = xor(_T_844, _T_828) @[lib.scala 119:74] + node _T_846 = xor(_T_845, _T_829) @[lib.scala 119:74] + node _T_847 = xor(_T_846, _T_830) @[lib.scala 119:74] + node _T_848 = xor(_T_847, _T_831) @[lib.scala 119:74] + node _T_849 = xor(_T_848, _T_832) @[lib.scala 119:74] + node _T_850 = xor(_T_849, _T_833) @[lib.scala 119:74] + node _T_851 = xor(_T_850, _T_834) @[lib.scala 119:74] + node _T_852 = xor(_T_851, _T_835) @[lib.scala 119:74] + node _T_853 = xor(_T_852, _T_836) @[lib.scala 119:74] + node _T_854 = xor(_T_853, _T_837) @[lib.scala 119:74] + node _T_855 = xor(_T_854, _T_838) @[lib.scala 119:74] + node _T_856 = xor(_T_855, _T_839) @[lib.scala 119:74] + node _T_857 = xor(_T_856, _T_840) @[lib.scala 119:74] + node _T_858 = xor(_T_857, _T_841) @[lib.scala 119:74] + node _T_859 = xor(_T_858, _T_842) @[lib.scala 119:74] + node _T_860 = xor(_T_859, _T_843) @[lib.scala 119:74] + node _T_861 = bits(dccm_wdata_lo_any, 4, 4) @[lib.scala 119:58] + node _T_862 = bits(dccm_wdata_lo_any, 5, 5) @[lib.scala 119:58] + node _T_863 = bits(dccm_wdata_lo_any, 6, 6) @[lib.scala 119:58] + node _T_864 = bits(dccm_wdata_lo_any, 7, 7) @[lib.scala 119:58] + node _T_865 = bits(dccm_wdata_lo_any, 8, 8) @[lib.scala 119:58] + node _T_866 = bits(dccm_wdata_lo_any, 9, 9) @[lib.scala 119:58] + node _T_867 = bits(dccm_wdata_lo_any, 10, 10) @[lib.scala 119:58] + node _T_868 = bits(dccm_wdata_lo_any, 18, 18) @[lib.scala 119:58] + node _T_869 = bits(dccm_wdata_lo_any, 19, 19) @[lib.scala 119:58] + node _T_870 = bits(dccm_wdata_lo_any, 20, 20) @[lib.scala 119:58] + node _T_871 = bits(dccm_wdata_lo_any, 21, 21) @[lib.scala 119:58] + node _T_872 = bits(dccm_wdata_lo_any, 22, 22) @[lib.scala 119:58] + node _T_873 = bits(dccm_wdata_lo_any, 23, 23) @[lib.scala 119:58] + node _T_874 = bits(dccm_wdata_lo_any, 24, 24) @[lib.scala 119:58] + node _T_875 = bits(dccm_wdata_lo_any, 25, 25) @[lib.scala 119:58] + node _T_876 = xor(_T_861, _T_862) @[lib.scala 119:74] + node _T_877 = xor(_T_876, _T_863) @[lib.scala 119:74] + node _T_878 = xor(_T_877, _T_864) @[lib.scala 119:74] + node _T_879 = xor(_T_878, _T_865) @[lib.scala 119:74] + node _T_880 = xor(_T_879, _T_866) @[lib.scala 119:74] + node _T_881 = xor(_T_880, _T_867) @[lib.scala 119:74] + node _T_882 = xor(_T_881, _T_868) @[lib.scala 119:74] + node _T_883 = xor(_T_882, _T_869) @[lib.scala 119:74] + node _T_884 = xor(_T_883, _T_870) @[lib.scala 119:74] + node _T_885 = xor(_T_884, _T_871) @[lib.scala 119:74] + node _T_886 = xor(_T_885, _T_872) @[lib.scala 119:74] + node _T_887 = xor(_T_886, _T_873) @[lib.scala 119:74] + node _T_888 = xor(_T_887, _T_874) @[lib.scala 119:74] + node _T_889 = xor(_T_888, _T_875) @[lib.scala 119:74] + node _T_890 = bits(dccm_wdata_lo_any, 11, 11) @[lib.scala 119:58] + node _T_891 = bits(dccm_wdata_lo_any, 12, 12) @[lib.scala 119:58] + node _T_892 = bits(dccm_wdata_lo_any, 13, 13) @[lib.scala 119:58] + node _T_893 = bits(dccm_wdata_lo_any, 14, 14) @[lib.scala 119:58] + node _T_894 = bits(dccm_wdata_lo_any, 15, 15) @[lib.scala 119:58] + node _T_895 = bits(dccm_wdata_lo_any, 16, 16) @[lib.scala 119:58] + node _T_896 = bits(dccm_wdata_lo_any, 17, 17) @[lib.scala 119:58] + node _T_897 = bits(dccm_wdata_lo_any, 18, 18) @[lib.scala 119:58] + node _T_898 = bits(dccm_wdata_lo_any, 19, 19) @[lib.scala 119:58] + node _T_899 = bits(dccm_wdata_lo_any, 20, 20) @[lib.scala 119:58] + node _T_900 = bits(dccm_wdata_lo_any, 21, 21) @[lib.scala 119:58] + node _T_901 = bits(dccm_wdata_lo_any, 22, 22) @[lib.scala 119:58] + node _T_902 = bits(dccm_wdata_lo_any, 23, 23) @[lib.scala 119:58] + node _T_903 = bits(dccm_wdata_lo_any, 24, 24) @[lib.scala 119:58] + node _T_904 = bits(dccm_wdata_lo_any, 25, 25) @[lib.scala 119:58] + node _T_905 = xor(_T_890, _T_891) @[lib.scala 119:74] + node _T_906 = xor(_T_905, _T_892) @[lib.scala 119:74] + node _T_907 = xor(_T_906, _T_893) @[lib.scala 119:74] + node _T_908 = xor(_T_907, _T_894) @[lib.scala 119:74] + node _T_909 = xor(_T_908, _T_895) @[lib.scala 119:74] + node _T_910 = xor(_T_909, _T_896) @[lib.scala 119:74] + node _T_911 = xor(_T_910, _T_897) @[lib.scala 119:74] + node _T_912 = xor(_T_911, _T_898) @[lib.scala 119:74] + node _T_913 = xor(_T_912, _T_899) @[lib.scala 119:74] + node _T_914 = xor(_T_913, _T_900) @[lib.scala 119:74] + node _T_915 = xor(_T_914, _T_901) @[lib.scala 119:74] + node _T_916 = xor(_T_915, _T_902) @[lib.scala 119:74] + node _T_917 = xor(_T_916, _T_903) @[lib.scala 119:74] + node _T_918 = xor(_T_917, _T_904) @[lib.scala 119:74] + node _T_919 = bits(dccm_wdata_lo_any, 26, 26) @[lib.scala 119:58] + node _T_920 = bits(dccm_wdata_lo_any, 27, 27) @[lib.scala 119:58] + node _T_921 = bits(dccm_wdata_lo_any, 28, 28) @[lib.scala 119:58] + node _T_922 = bits(dccm_wdata_lo_any, 29, 29) @[lib.scala 119:58] + node _T_923 = bits(dccm_wdata_lo_any, 30, 30) @[lib.scala 119:58] + node _T_924 = bits(dccm_wdata_lo_any, 31, 31) @[lib.scala 119:58] + node _T_925 = xor(_T_919, _T_920) @[lib.scala 119:74] + node _T_926 = xor(_T_925, _T_921) @[lib.scala 119:74] + node _T_927 = xor(_T_926, _T_922) @[lib.scala 119:74] + node _T_928 = xor(_T_927, _T_923) @[lib.scala 119:74] + node _T_929 = xor(_T_928, _T_924) @[lib.scala 119:74] + node _T_930 = cat(_T_860, _T_825) @[Cat.scala 29:58] + node _T_931 = cat(_T_930, _T_790) @[Cat.scala 29:58] + node _T_932 = cat(_T_929, _T_918) @[Cat.scala 29:58] + node _T_933 = cat(_T_932, _T_889) @[Cat.scala 29:58] + node _T_934 = cat(_T_933, _T_931) @[Cat.scala 29:58] + node _T_935 = xorr(dccm_wdata_lo_any) @[lib.scala 127:13] + node _T_936 = xorr(_T_934) @[lib.scala 127:23] + node _T_937 = xor(_T_935, _T_936) @[lib.scala 127:18] + node dccm_wdata_ecc_lo_any = cat(_T_937, _T_934) @[Cat.scala 29:58] + node _T_938 = bits(dccm_wdata_hi_any, 0, 0) @[lib.scala 119:58] + node _T_939 = bits(dccm_wdata_hi_any, 1, 1) @[lib.scala 119:58] + node _T_940 = bits(dccm_wdata_hi_any, 3, 3) @[lib.scala 119:58] + node _T_941 = bits(dccm_wdata_hi_any, 4, 4) @[lib.scala 119:58] + node _T_942 = bits(dccm_wdata_hi_any, 6, 6) @[lib.scala 119:58] + node _T_943 = bits(dccm_wdata_hi_any, 8, 8) @[lib.scala 119:58] + node _T_944 = bits(dccm_wdata_hi_any, 10, 10) @[lib.scala 119:58] + node _T_945 = bits(dccm_wdata_hi_any, 11, 11) @[lib.scala 119:58] + node _T_946 = bits(dccm_wdata_hi_any, 13, 13) @[lib.scala 119:58] + node _T_947 = bits(dccm_wdata_hi_any, 15, 15) @[lib.scala 119:58] + node _T_948 = bits(dccm_wdata_hi_any, 17, 17) @[lib.scala 119:58] + node _T_949 = bits(dccm_wdata_hi_any, 19, 19) @[lib.scala 119:58] + node _T_950 = bits(dccm_wdata_hi_any, 21, 21) @[lib.scala 119:58] + node _T_951 = bits(dccm_wdata_hi_any, 23, 23) @[lib.scala 119:58] + node _T_952 = bits(dccm_wdata_hi_any, 25, 25) @[lib.scala 119:58] + node _T_953 = bits(dccm_wdata_hi_any, 26, 26) @[lib.scala 119:58] + node _T_954 = bits(dccm_wdata_hi_any, 28, 28) @[lib.scala 119:58] + node _T_955 = bits(dccm_wdata_hi_any, 30, 30) @[lib.scala 119:58] + node _T_956 = xor(_T_938, _T_939) @[lib.scala 119:74] + node _T_957 = xor(_T_956, _T_940) @[lib.scala 119:74] + node _T_958 = xor(_T_957, _T_941) @[lib.scala 119:74] + node _T_959 = xor(_T_958, _T_942) @[lib.scala 119:74] + node _T_960 = xor(_T_959, _T_943) @[lib.scala 119:74] + node _T_961 = xor(_T_960, _T_944) @[lib.scala 119:74] + node _T_962 = xor(_T_961, _T_945) @[lib.scala 119:74] + node _T_963 = xor(_T_962, _T_946) @[lib.scala 119:74] + node _T_964 = xor(_T_963, _T_947) @[lib.scala 119:74] + node _T_965 = xor(_T_964, _T_948) @[lib.scala 119:74] + node _T_966 = xor(_T_965, _T_949) @[lib.scala 119:74] + node _T_967 = xor(_T_966, _T_950) @[lib.scala 119:74] + node _T_968 = xor(_T_967, _T_951) @[lib.scala 119:74] + node _T_969 = xor(_T_968, _T_952) @[lib.scala 119:74] + node _T_970 = xor(_T_969, _T_953) @[lib.scala 119:74] + node _T_971 = xor(_T_970, _T_954) @[lib.scala 119:74] + node _T_972 = xor(_T_971, _T_955) @[lib.scala 119:74] + node _T_973 = bits(dccm_wdata_hi_any, 0, 0) @[lib.scala 119:58] + node _T_974 = bits(dccm_wdata_hi_any, 2, 2) @[lib.scala 119:58] + node _T_975 = bits(dccm_wdata_hi_any, 3, 3) @[lib.scala 119:58] + node _T_976 = bits(dccm_wdata_hi_any, 5, 5) @[lib.scala 119:58] + node _T_977 = bits(dccm_wdata_hi_any, 6, 6) @[lib.scala 119:58] + node _T_978 = bits(dccm_wdata_hi_any, 9, 9) @[lib.scala 119:58] + node _T_979 = bits(dccm_wdata_hi_any, 10, 10) @[lib.scala 119:58] + node _T_980 = bits(dccm_wdata_hi_any, 12, 12) @[lib.scala 119:58] + node _T_981 = bits(dccm_wdata_hi_any, 13, 13) @[lib.scala 119:58] + node _T_982 = bits(dccm_wdata_hi_any, 16, 16) @[lib.scala 119:58] + node _T_983 = bits(dccm_wdata_hi_any, 17, 17) @[lib.scala 119:58] + node _T_984 = bits(dccm_wdata_hi_any, 20, 20) @[lib.scala 119:58] + node _T_985 = bits(dccm_wdata_hi_any, 21, 21) @[lib.scala 119:58] + node _T_986 = bits(dccm_wdata_hi_any, 24, 24) @[lib.scala 119:58] + node _T_987 = bits(dccm_wdata_hi_any, 25, 25) @[lib.scala 119:58] + node _T_988 = bits(dccm_wdata_hi_any, 27, 27) @[lib.scala 119:58] + node _T_989 = bits(dccm_wdata_hi_any, 28, 28) @[lib.scala 119:58] + node _T_990 = bits(dccm_wdata_hi_any, 31, 31) @[lib.scala 119:58] + node _T_991 = xor(_T_973, _T_974) @[lib.scala 119:74] + node _T_992 = xor(_T_991, _T_975) @[lib.scala 119:74] + node _T_993 = xor(_T_992, _T_976) @[lib.scala 119:74] + node _T_994 = xor(_T_993, _T_977) @[lib.scala 119:74] + node _T_995 = xor(_T_994, _T_978) @[lib.scala 119:74] + node _T_996 = xor(_T_995, _T_979) @[lib.scala 119:74] + node _T_997 = xor(_T_996, _T_980) @[lib.scala 119:74] + node _T_998 = xor(_T_997, _T_981) @[lib.scala 119:74] + node _T_999 = xor(_T_998, _T_982) @[lib.scala 119:74] + node _T_1000 = xor(_T_999, _T_983) @[lib.scala 119:74] + node _T_1001 = xor(_T_1000, _T_984) @[lib.scala 119:74] + node _T_1002 = xor(_T_1001, _T_985) @[lib.scala 119:74] + node _T_1003 = xor(_T_1002, _T_986) @[lib.scala 119:74] + node _T_1004 = xor(_T_1003, _T_987) @[lib.scala 119:74] + node _T_1005 = xor(_T_1004, _T_988) @[lib.scala 119:74] + node _T_1006 = xor(_T_1005, _T_989) @[lib.scala 119:74] + node _T_1007 = xor(_T_1006, _T_990) @[lib.scala 119:74] + node _T_1008 = bits(dccm_wdata_hi_any, 1, 1) @[lib.scala 119:58] + node _T_1009 = bits(dccm_wdata_hi_any, 2, 2) @[lib.scala 119:58] + node _T_1010 = bits(dccm_wdata_hi_any, 3, 3) @[lib.scala 119:58] + node _T_1011 = bits(dccm_wdata_hi_any, 7, 7) @[lib.scala 119:58] + node _T_1012 = bits(dccm_wdata_hi_any, 8, 8) @[lib.scala 119:58] + node _T_1013 = bits(dccm_wdata_hi_any, 9, 9) @[lib.scala 119:58] + node _T_1014 = bits(dccm_wdata_hi_any, 10, 10) @[lib.scala 119:58] + node _T_1015 = bits(dccm_wdata_hi_any, 14, 14) @[lib.scala 119:58] + node _T_1016 = bits(dccm_wdata_hi_any, 15, 15) @[lib.scala 119:58] + node _T_1017 = bits(dccm_wdata_hi_any, 16, 16) @[lib.scala 119:58] + node _T_1018 = bits(dccm_wdata_hi_any, 17, 17) @[lib.scala 119:58] + node _T_1019 = bits(dccm_wdata_hi_any, 22, 22) @[lib.scala 119:58] + node _T_1020 = bits(dccm_wdata_hi_any, 23, 23) @[lib.scala 119:58] + node _T_1021 = bits(dccm_wdata_hi_any, 24, 24) @[lib.scala 119:58] + node _T_1022 = bits(dccm_wdata_hi_any, 25, 25) @[lib.scala 119:58] + node _T_1023 = bits(dccm_wdata_hi_any, 29, 29) @[lib.scala 119:58] + node _T_1024 = bits(dccm_wdata_hi_any, 30, 30) @[lib.scala 119:58] + node _T_1025 = bits(dccm_wdata_hi_any, 31, 31) @[lib.scala 119:58] + node _T_1026 = xor(_T_1008, _T_1009) @[lib.scala 119:74] + node _T_1027 = xor(_T_1026, _T_1010) @[lib.scala 119:74] + node _T_1028 = xor(_T_1027, _T_1011) @[lib.scala 119:74] + node _T_1029 = xor(_T_1028, _T_1012) @[lib.scala 119:74] + node _T_1030 = xor(_T_1029, _T_1013) @[lib.scala 119:74] + node _T_1031 = xor(_T_1030, _T_1014) @[lib.scala 119:74] + node _T_1032 = xor(_T_1031, _T_1015) @[lib.scala 119:74] + node _T_1033 = xor(_T_1032, _T_1016) @[lib.scala 119:74] + node _T_1034 = xor(_T_1033, _T_1017) @[lib.scala 119:74] + node _T_1035 = xor(_T_1034, _T_1018) @[lib.scala 119:74] + node _T_1036 = xor(_T_1035, _T_1019) @[lib.scala 119:74] + node _T_1037 = xor(_T_1036, _T_1020) @[lib.scala 119:74] + node _T_1038 = xor(_T_1037, _T_1021) @[lib.scala 119:74] + node _T_1039 = xor(_T_1038, _T_1022) @[lib.scala 119:74] + node _T_1040 = xor(_T_1039, _T_1023) @[lib.scala 119:74] + node _T_1041 = xor(_T_1040, _T_1024) @[lib.scala 119:74] + node _T_1042 = xor(_T_1041, _T_1025) @[lib.scala 119:74] + node _T_1043 = bits(dccm_wdata_hi_any, 4, 4) @[lib.scala 119:58] + node _T_1044 = bits(dccm_wdata_hi_any, 5, 5) @[lib.scala 119:58] + node _T_1045 = bits(dccm_wdata_hi_any, 6, 6) @[lib.scala 119:58] + node _T_1046 = bits(dccm_wdata_hi_any, 7, 7) @[lib.scala 119:58] + node _T_1047 = bits(dccm_wdata_hi_any, 8, 8) @[lib.scala 119:58] + node _T_1048 = bits(dccm_wdata_hi_any, 9, 9) @[lib.scala 119:58] + node _T_1049 = bits(dccm_wdata_hi_any, 10, 10) @[lib.scala 119:58] + node _T_1050 = bits(dccm_wdata_hi_any, 18, 18) @[lib.scala 119:58] + node _T_1051 = bits(dccm_wdata_hi_any, 19, 19) @[lib.scala 119:58] + node _T_1052 = bits(dccm_wdata_hi_any, 20, 20) @[lib.scala 119:58] + node _T_1053 = bits(dccm_wdata_hi_any, 21, 21) @[lib.scala 119:58] + node _T_1054 = bits(dccm_wdata_hi_any, 22, 22) @[lib.scala 119:58] + node _T_1055 = bits(dccm_wdata_hi_any, 23, 23) @[lib.scala 119:58] + node _T_1056 = bits(dccm_wdata_hi_any, 24, 24) @[lib.scala 119:58] + node _T_1057 = bits(dccm_wdata_hi_any, 25, 25) @[lib.scala 119:58] + node _T_1058 = xor(_T_1043, _T_1044) @[lib.scala 119:74] + node _T_1059 = xor(_T_1058, _T_1045) @[lib.scala 119:74] + node _T_1060 = xor(_T_1059, _T_1046) @[lib.scala 119:74] + node _T_1061 = xor(_T_1060, _T_1047) @[lib.scala 119:74] + node _T_1062 = xor(_T_1061, _T_1048) @[lib.scala 119:74] + node _T_1063 = xor(_T_1062, _T_1049) @[lib.scala 119:74] + node _T_1064 = xor(_T_1063, _T_1050) @[lib.scala 119:74] + node _T_1065 = xor(_T_1064, _T_1051) @[lib.scala 119:74] + node _T_1066 = xor(_T_1065, _T_1052) @[lib.scala 119:74] + node _T_1067 = xor(_T_1066, _T_1053) @[lib.scala 119:74] + node _T_1068 = xor(_T_1067, _T_1054) @[lib.scala 119:74] + node _T_1069 = xor(_T_1068, _T_1055) @[lib.scala 119:74] + node _T_1070 = xor(_T_1069, _T_1056) @[lib.scala 119:74] + node _T_1071 = xor(_T_1070, _T_1057) @[lib.scala 119:74] + node _T_1072 = bits(dccm_wdata_hi_any, 11, 11) @[lib.scala 119:58] + node _T_1073 = bits(dccm_wdata_hi_any, 12, 12) @[lib.scala 119:58] + node _T_1074 = bits(dccm_wdata_hi_any, 13, 13) @[lib.scala 119:58] + node _T_1075 = bits(dccm_wdata_hi_any, 14, 14) @[lib.scala 119:58] + node _T_1076 = bits(dccm_wdata_hi_any, 15, 15) @[lib.scala 119:58] + node _T_1077 = bits(dccm_wdata_hi_any, 16, 16) @[lib.scala 119:58] + node _T_1078 = bits(dccm_wdata_hi_any, 17, 17) @[lib.scala 119:58] + node _T_1079 = bits(dccm_wdata_hi_any, 18, 18) @[lib.scala 119:58] + node _T_1080 = bits(dccm_wdata_hi_any, 19, 19) @[lib.scala 119:58] + node _T_1081 = bits(dccm_wdata_hi_any, 20, 20) @[lib.scala 119:58] + node _T_1082 = bits(dccm_wdata_hi_any, 21, 21) @[lib.scala 119:58] + node _T_1083 = bits(dccm_wdata_hi_any, 22, 22) @[lib.scala 119:58] + node _T_1084 = bits(dccm_wdata_hi_any, 23, 23) @[lib.scala 119:58] + node _T_1085 = bits(dccm_wdata_hi_any, 24, 24) @[lib.scala 119:58] + node _T_1086 = bits(dccm_wdata_hi_any, 25, 25) @[lib.scala 119:58] + node _T_1087 = xor(_T_1072, _T_1073) @[lib.scala 119:74] + node _T_1088 = xor(_T_1087, _T_1074) @[lib.scala 119:74] + node _T_1089 = xor(_T_1088, _T_1075) @[lib.scala 119:74] + node _T_1090 = xor(_T_1089, _T_1076) @[lib.scala 119:74] + node _T_1091 = xor(_T_1090, _T_1077) @[lib.scala 119:74] + node _T_1092 = xor(_T_1091, _T_1078) @[lib.scala 119:74] + node _T_1093 = xor(_T_1092, _T_1079) @[lib.scala 119:74] + node _T_1094 = xor(_T_1093, _T_1080) @[lib.scala 119:74] + node _T_1095 = xor(_T_1094, _T_1081) @[lib.scala 119:74] + node _T_1096 = xor(_T_1095, _T_1082) @[lib.scala 119:74] + node _T_1097 = xor(_T_1096, _T_1083) @[lib.scala 119:74] + node _T_1098 = xor(_T_1097, _T_1084) @[lib.scala 119:74] + node _T_1099 = xor(_T_1098, _T_1085) @[lib.scala 119:74] + node _T_1100 = xor(_T_1099, _T_1086) @[lib.scala 119:74] + node _T_1101 = bits(dccm_wdata_hi_any, 26, 26) @[lib.scala 119:58] + node _T_1102 = bits(dccm_wdata_hi_any, 27, 27) @[lib.scala 119:58] + node _T_1103 = bits(dccm_wdata_hi_any, 28, 28) @[lib.scala 119:58] + node _T_1104 = bits(dccm_wdata_hi_any, 29, 29) @[lib.scala 119:58] + node _T_1105 = bits(dccm_wdata_hi_any, 30, 30) @[lib.scala 119:58] + node _T_1106 = bits(dccm_wdata_hi_any, 31, 31) @[lib.scala 119:58] + node _T_1107 = xor(_T_1101, _T_1102) @[lib.scala 119:74] + node _T_1108 = xor(_T_1107, _T_1103) @[lib.scala 119:74] + node _T_1109 = xor(_T_1108, _T_1104) @[lib.scala 119:74] + node _T_1110 = xor(_T_1109, _T_1105) @[lib.scala 119:74] + node _T_1111 = xor(_T_1110, _T_1106) @[lib.scala 119:74] + node _T_1112 = cat(_T_1042, _T_1007) @[Cat.scala 29:58] + node _T_1113 = cat(_T_1112, _T_972) @[Cat.scala 29:58] + node _T_1114 = cat(_T_1111, _T_1100) @[Cat.scala 29:58] + node _T_1115 = cat(_T_1114, _T_1071) @[Cat.scala 29:58] + node _T_1116 = cat(_T_1115, _T_1113) @[Cat.scala 29:58] + node _T_1117 = xorr(dccm_wdata_hi_any) @[lib.scala 127:13] + node _T_1118 = xorr(_T_1116) @[lib.scala 127:23] + node _T_1119 = xor(_T_1117, _T_1118) @[lib.scala 127:18] + node dccm_wdata_ecc_hi_any = cat(_T_1119, _T_1116) @[Cat.scala 29:58] + when UInt<1>("h00") : @[lsu_ecc.scala 103:30] + node _T_1120 = bits(io.lsu_addr_r, 2, 2) @[lsu_ecc.scala 104:33] + node _T_1121 = bits(io.end_addr_r, 2, 2) @[lsu_ecc.scala 104:54] + node _T_1122 = neq(_T_1120, _T_1121) @[lsu_ecc.scala 104:37] + ldst_dual_r <= _T_1122 @[lsu_ecc.scala 104:17] + node _T_1123 = or(io.lsu_pkt_r.bits.load, io.lsu_pkt_r.bits.store) @[lsu_ecc.scala 105:63] + node _T_1124 = and(io.lsu_pkt_r.valid, _T_1123) @[lsu_ecc.scala 105:37] + node _T_1125 = and(_T_1124, io.addr_in_dccm_r) @[lsu_ecc.scala 105:90] + node _T_1126 = and(_T_1125, io.lsu_dccm_rden_r) @[lsu_ecc.scala 105:110] + is_ldst_r <= _T_1126 @[lsu_ecc.scala 105:15] + node _T_1127 = eq(io.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[lsu_ecc.scala 106:33] + node _T_1128 = and(is_ldst_r, _T_1127) @[lsu_ecc.scala 106:31] + is_ldst_lo_r <= _T_1128 @[lsu_ecc.scala 106:18] + node _T_1129 = or(ldst_dual_r, io.lsu_pkt_r.bits.dma) @[lsu_ecc.scala 107:46] + node _T_1130 = and(is_ldst_r, _T_1129) @[lsu_ecc.scala 107:31] + node _T_1131 = eq(io.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[lsu_ecc.scala 107:73] + node _T_1132 = and(_T_1130, _T_1131) @[lsu_ecc.scala 107:71] + is_ldst_hi_r <= _T_1132 @[lsu_ecc.scala 107:18] + is_ldst_hi_any <= is_ldst_hi_r @[lsu_ecc.scala 108:21] + dccm_rdata_hi_any <= io.dccm_rdata_hi_r @[lsu_ecc.scala 109:24] + dccm_data_ecc_hi_any <= io.dccm_data_ecc_hi_r @[lsu_ecc.scala 110:26] + is_ldst_lo_any <= is_ldst_lo_r @[lsu_ecc.scala 111:20] + dccm_rdata_lo_any <= io.dccm_rdata_lo_r @[lsu_ecc.scala 112:25] + dccm_data_ecc_lo_any <= io.dccm_data_ecc_lo_r @[lsu_ecc.scala 113:26] + io.sec_data_hi_r <= sec_data_hi_any @[lsu_ecc.scala 114:22] + io.single_ecc_error_hi_r <= single_ecc_error_hi_any @[lsu_ecc.scala 115:31] + double_ecc_error_hi_r <= double_ecc_error_hi_any @[lsu_ecc.scala 116:28] + io.sec_data_lo_r <= sec_data_lo_any @[lsu_ecc.scala 117:25] + io.single_ecc_error_lo_r <= single_ecc_error_lo_any @[lsu_ecc.scala 118:31] + double_ecc_error_lo_r <= double_ecc_error_lo_any @[lsu_ecc.scala 119:28] + node _T_1133 = or(io.single_ecc_error_hi_r, io.single_ecc_error_lo_r) @[lsu_ecc.scala 120:59] + io.lsu_single_ecc_error_r <= _T_1133 @[lsu_ecc.scala 120:31] + node _T_1134 = or(double_ecc_error_hi_r, double_ecc_error_lo_r) @[lsu_ecc.scala 121:56] + io.lsu_double_ecc_error_r <= _T_1134 @[lsu_ecc.scala 121:31] + skip @[lsu_ecc.scala 103:30] + else : @[lsu_ecc.scala 123:16] + node _T_1135 = bits(io.lsu_addr_m, 2, 2) @[lsu_ecc.scala 124:35] + node _T_1136 = bits(io.end_addr_m, 2, 2) @[lsu_ecc.scala 124:56] + node _T_1137 = neq(_T_1135, _T_1136) @[lsu_ecc.scala 124:39] + ldst_dual_m <= _T_1137 @[lsu_ecc.scala 124:19] + node _T_1138 = or(io.lsu_pkt_m.bits.load, io.lsu_pkt_m.bits.store) @[lsu_ecc.scala 125:65] + node _T_1139 = and(io.lsu_pkt_m.valid, _T_1138) @[lsu_ecc.scala 125:39] + node _T_1140 = and(_T_1139, io.addr_in_dccm_m) @[lsu_ecc.scala 125:92] + node _T_1141 = and(_T_1140, io.lsu_dccm_rden_m) @[lsu_ecc.scala 125:112] + is_ldst_m <= _T_1141 @[lsu_ecc.scala 125:17] + node _T_1142 = eq(io.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[lsu_ecc.scala 126:35] + node _T_1143 = and(is_ldst_m, _T_1142) @[lsu_ecc.scala 126:33] + is_ldst_lo_m <= _T_1143 @[lsu_ecc.scala 126:20] + node _T_1144 = or(ldst_dual_m, io.lsu_pkt_m.bits.dma) @[lsu_ecc.scala 127:48] + node _T_1145 = and(is_ldst_m, _T_1144) @[lsu_ecc.scala 127:33] + node _T_1146 = eq(io.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[lsu_ecc.scala 127:75] + node _T_1147 = and(_T_1145, _T_1146) @[lsu_ecc.scala 127:73] + is_ldst_hi_m <= _T_1147 @[lsu_ecc.scala 127:20] + is_ldst_hi_any <= is_ldst_hi_m @[lsu_ecc.scala 128:23] + dccm_rdata_hi_any <= io.dccm_rdata_hi_m @[lsu_ecc.scala 129:26] + dccm_data_ecc_hi_any <= io.dccm_data_ecc_hi_m @[lsu_ecc.scala 130:28] + is_ldst_lo_any <= is_ldst_lo_m @[lsu_ecc.scala 131:22] + dccm_rdata_lo_any <= io.dccm_rdata_lo_m @[lsu_ecc.scala 132:27] + dccm_data_ecc_lo_any <= io.dccm_data_ecc_lo_m @[lsu_ecc.scala 133:28] + io.sec_data_hi_m <= sec_data_hi_any @[lsu_ecc.scala 134:27] + double_ecc_error_hi_m <= double_ecc_error_hi_any @[lsu_ecc.scala 135:30] + io.sec_data_lo_m <= sec_data_lo_any @[lsu_ecc.scala 136:27] + double_ecc_error_lo_m <= double_ecc_error_lo_any @[lsu_ecc.scala 137:30] + node _T_1148 = or(single_ecc_error_hi_any, single_ecc_error_lo_any) @[lsu_ecc.scala 138:60] + io.lsu_single_ecc_error_m <= _T_1148 @[lsu_ecc.scala 138:33] + node _T_1149 = or(double_ecc_error_hi_m, double_ecc_error_lo_m) @[lsu_ecc.scala 139:58] + io.lsu_double_ecc_error_m <= _T_1149 @[lsu_ecc.scala 139:33] + reg _T_1150 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_ecc.scala 141:72] + _T_1150 <= io.lsu_single_ecc_error_m @[lsu_ecc.scala 141:72] + io.lsu_single_ecc_error_r <= _T_1150 @[lsu_ecc.scala 141:62] + reg _T_1151 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_ecc.scala 142:72] + _T_1151 <= io.lsu_double_ecc_error_m @[lsu_ecc.scala 142:72] + io.lsu_double_ecc_error_r <= _T_1151 @[lsu_ecc.scala 142:62] + reg _T_1152 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_ecc.scala 143:72] + _T_1152 <= single_ecc_error_lo_any @[lsu_ecc.scala 143:72] + io.single_ecc_error_lo_r <= _T_1152 @[lsu_ecc.scala 143:62] + reg _T_1153 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_ecc.scala 144:72] + _T_1153 <= single_ecc_error_hi_any @[lsu_ecc.scala 144:72] + io.single_ecc_error_hi_r <= _T_1153 @[lsu_ecc.scala 144:62] + reg _T_1154 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_ecc.scala 145:72] + _T_1154 <= io.sec_data_hi_m @[lsu_ecc.scala 145:72] + io.sec_data_hi_r <= _T_1154 @[lsu_ecc.scala 145:62] + reg _T_1155 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_ecc.scala 146:72] + _T_1155 <= io.sec_data_lo_m @[lsu_ecc.scala 146:72] + io.sec_data_lo_r <= _T_1155 @[lsu_ecc.scala 146:62] + skip @[lsu_ecc.scala 123:16] + node _T_1156 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[lsu_ecc.scala 149:56] + node _T_1157 = bits(io.dma_dccm_wen, 0, 0) @[lsu_ecc.scala 149:104] + node _T_1158 = mux(_T_1157, io.dma_dccm_wdata_lo, io.stbuf_data_any) @[lsu_ecc.scala 149:87] + node _T_1159 = mux(_T_1156, io.sec_data_lo_r_ff, _T_1158) @[lsu_ecc.scala 149:27] + dccm_wdata_lo_any <= _T_1159 @[lsu_ecc.scala 149:21] + node _T_1160 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[lsu_ecc.scala 150:56] + node _T_1161 = bits(io.dma_dccm_wen, 0, 0) @[lsu_ecc.scala 150:104] + node _T_1162 = mux(_T_1161, io.dma_dccm_wdata_hi, io.stbuf_data_any) @[lsu_ecc.scala 150:87] + node _T_1163 = mux(_T_1160, io.sec_data_hi_r_ff, _T_1162) @[lsu_ecc.scala 150:27] + dccm_wdata_hi_any <= _T_1163 @[lsu_ecc.scala 150:21] + io.sec_data_ecc_hi_r_ff <= dccm_wdata_ecc_hi_any @[lsu_ecc.scala 151:28] + io.sec_data_ecc_lo_r_ff <= dccm_wdata_ecc_lo_any @[lsu_ecc.scala 152:28] + io.stbuf_ecc_any <= dccm_wdata_ecc_lo_any @[lsu_ecc.scala 153:28] + io.dma_dccm_wdata_ecc_hi <= dccm_wdata_ecc_hi_any @[lsu_ecc.scala 154:28] + io.dma_dccm_wdata_ecc_lo <= dccm_wdata_ecc_lo_any @[lsu_ecc.scala 155:28] + inst rvclkhdr of rvclkhdr_10 @[lib.scala 368:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[lib.scala 370:18] + rvclkhdr.io.en <= io.ld_single_ecc_error_r @[lib.scala 371:17] + rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_1164 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_1164 <= io.sec_data_hi_r @[lib.scala 374:16] + io.sec_data_hi_r_ff <= _T_1164 @[lsu_ecc.scala 157:23] + inst rvclkhdr_1 of rvclkhdr_11 @[lib.scala 368:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_1.io.en <= io.ld_single_ecc_error_r @[lib.scala 371:17] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_1165 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_1165 <= io.sec_data_lo_r @[lib.scala 374:16] + io.sec_data_lo_r_ff <= _T_1165 @[lsu_ecc.scala 158:23] + + module lsu_trigger : + input clock : Clock + input reset : AsyncReset + output io : {flip trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_addr_m : UInt<32>, flip store_data_m : UInt<32>, lsu_trigger_match_m : UInt<4>} + + node _T = bits(io.lsu_pkt_m.bits.word, 0, 0) @[Bitwise.scala 72:15] + node _T_1 = mux(_T, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] + node _T_2 = bits(io.store_data_m, 31, 16) @[lsu_trigger.scala 16:83] + node _T_3 = and(_T_1, _T_2) @[lsu_trigger.scala 16:66] + node _T_4 = or(io.lsu_pkt_m.bits.half, io.lsu_pkt_m.bits.word) @[lsu_trigger.scala 16:124] + node _T_5 = bits(_T_4, 0, 0) @[Bitwise.scala 72:15] + node _T_6 = mux(_T_5, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_7 = bits(io.store_data_m, 15, 8) @[lsu_trigger.scala 16:168] + node _T_8 = and(_T_6, _T_7) @[lsu_trigger.scala 16:151] + node _T_9 = bits(io.store_data_m, 7, 0) @[lsu_trigger.scala 16:192] + node _T_10 = cat(_T_3, _T_8) @[Cat.scala 29:58] + node store_data_trigger_m = cat(_T_10, _T_9) @[Cat.scala 29:58] + node _T_11 = bits(io.trigger_pkt_any[0].select, 0, 0) @[lsu_trigger.scala 17:83] + node _T_12 = eq(_T_11, UInt<1>("h00")) @[lsu_trigger.scala 17:53] + node _T_13 = and(io.trigger_pkt_any[0].select, io.trigger_pkt_any[0].store) @[lsu_trigger.scala 17:136] + node _T_14 = bits(_T_13, 0, 0) @[lsu_trigger.scala 17:167] + node _T_15 = mux(_T_12, io.lsu_addr_m, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_16 = mux(_T_14, store_data_trigger_m, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_17 = or(_T_15, _T_16) @[Mux.scala 27:72] + wire lsu_match_data_0 : UInt<32> @[Mux.scala 27:72] + lsu_match_data_0 <= _T_17 @[Mux.scala 27:72] + node _T_18 = bits(io.trigger_pkt_any[1].select, 0, 0) @[lsu_trigger.scala 17:83] + node _T_19 = eq(_T_18, UInt<1>("h00")) @[lsu_trigger.scala 17:53] + node _T_20 = and(io.trigger_pkt_any[1].select, io.trigger_pkt_any[1].store) @[lsu_trigger.scala 17:136] + node _T_21 = bits(_T_20, 0, 0) @[lsu_trigger.scala 17:167] + node _T_22 = mux(_T_19, io.lsu_addr_m, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_23 = mux(_T_21, store_data_trigger_m, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_24 = or(_T_22, _T_23) @[Mux.scala 27:72] + wire lsu_match_data_1 : UInt<32> @[Mux.scala 27:72] + lsu_match_data_1 <= _T_24 @[Mux.scala 27:72] + node _T_25 = bits(io.trigger_pkt_any[2].select, 0, 0) @[lsu_trigger.scala 17:83] + node _T_26 = eq(_T_25, UInt<1>("h00")) @[lsu_trigger.scala 17:53] + node _T_27 = and(io.trigger_pkt_any[2].select, io.trigger_pkt_any[2].store) @[lsu_trigger.scala 17:136] + node _T_28 = bits(_T_27, 0, 0) @[lsu_trigger.scala 17:167] + node _T_29 = mux(_T_26, io.lsu_addr_m, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_30 = mux(_T_28, store_data_trigger_m, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_31 = or(_T_29, _T_30) @[Mux.scala 27:72] + wire lsu_match_data_2 : UInt<32> @[Mux.scala 27:72] + lsu_match_data_2 <= _T_31 @[Mux.scala 27:72] + node _T_32 = bits(io.trigger_pkt_any[3].select, 0, 0) @[lsu_trigger.scala 17:83] + node _T_33 = eq(_T_32, UInt<1>("h00")) @[lsu_trigger.scala 17:53] + node _T_34 = and(io.trigger_pkt_any[3].select, io.trigger_pkt_any[3].store) @[lsu_trigger.scala 17:136] + node _T_35 = bits(_T_34, 0, 0) @[lsu_trigger.scala 17:167] + node _T_36 = mux(_T_33, io.lsu_addr_m, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_37 = mux(_T_35, store_data_trigger_m, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_38 = or(_T_36, _T_37) @[Mux.scala 27:72] + wire lsu_match_data_3 : UInt<32> @[Mux.scala 27:72] + lsu_match_data_3 <= _T_38 @[Mux.scala 27:72] + node _T_39 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_trigger.scala 18:71] + node _T_40 = and(io.lsu_pkt_m.valid, _T_39) @[lsu_trigger.scala 18:69] + node _T_41 = and(io.trigger_pkt_any[0].store, io.lsu_pkt_m.bits.store) @[lsu_trigger.scala 18:126] + node _T_42 = and(io.trigger_pkt_any[0].load, io.lsu_pkt_m.bits.load) @[lsu_trigger.scala 19:33] + node _T_43 = eq(io.trigger_pkt_any[0].select, UInt<1>("h00")) @[lsu_trigger.scala 19:60] + node _T_44 = and(_T_42, _T_43) @[lsu_trigger.scala 19:58] + node _T_45 = or(_T_41, _T_44) @[lsu_trigger.scala 18:152] + node _T_46 = and(_T_40, _T_45) @[lsu_trigger.scala 18:94] + node _T_47 = bits(io.trigger_pkt_any[0].match_pkt, 0, 0) @[lsu_trigger.scala 20:107] + wire _T_48 : UInt<1>[32] @[lib.scala 100:24] + node _T_49 = andr(io.trigger_pkt_any[0].tdata2) @[lib.scala 101:45] + node _T_50 = not(_T_49) @[lib.scala 101:39] + node _T_51 = and(_T_47, _T_50) @[lib.scala 101:37] + node _T_52 = bits(io.trigger_pkt_any[0].tdata2, 0, 0) @[lib.scala 102:48] + node _T_53 = bits(lsu_match_data_0, 0, 0) @[lib.scala 102:60] + node _T_54 = eq(_T_52, _T_53) @[lib.scala 102:52] + node _T_55 = or(_T_51, _T_54) @[lib.scala 102:41] + _T_48[0] <= _T_55 @[lib.scala 102:18] + node _T_56 = bits(io.trigger_pkt_any[0].tdata2, 0, 0) @[lib.scala 104:28] + node _T_57 = andr(_T_56) @[lib.scala 104:36] + node _T_58 = and(_T_57, _T_51) @[lib.scala 104:41] + node _T_59 = bits(io.trigger_pkt_any[0].tdata2, 1, 1) @[lib.scala 104:74] + node _T_60 = bits(lsu_match_data_0, 1, 1) @[lib.scala 104:86] + node _T_61 = eq(_T_59, _T_60) @[lib.scala 104:78] + node _T_62 = mux(_T_58, UInt<1>("h01"), _T_61) @[lib.scala 104:23] + _T_48[1] <= _T_62 @[lib.scala 104:17] + node _T_63 = bits(io.trigger_pkt_any[0].tdata2, 1, 0) @[lib.scala 104:28] + node _T_64 = andr(_T_63) @[lib.scala 104:36] + node _T_65 = and(_T_64, _T_51) @[lib.scala 104:41] + node _T_66 = bits(io.trigger_pkt_any[0].tdata2, 2, 2) @[lib.scala 104:74] + node _T_67 = bits(lsu_match_data_0, 2, 2) @[lib.scala 104:86] + node _T_68 = eq(_T_66, _T_67) @[lib.scala 104:78] + node _T_69 = mux(_T_65, UInt<1>("h01"), _T_68) @[lib.scala 104:23] + _T_48[2] <= _T_69 @[lib.scala 104:17] + node _T_70 = bits(io.trigger_pkt_any[0].tdata2, 2, 0) @[lib.scala 104:28] + node _T_71 = andr(_T_70) @[lib.scala 104:36] + node _T_72 = and(_T_71, _T_51) @[lib.scala 104:41] + node _T_73 = bits(io.trigger_pkt_any[0].tdata2, 3, 3) @[lib.scala 104:74] + node _T_74 = bits(lsu_match_data_0, 3, 3) @[lib.scala 104:86] + node _T_75 = eq(_T_73, _T_74) @[lib.scala 104:78] + node _T_76 = mux(_T_72, UInt<1>("h01"), _T_75) @[lib.scala 104:23] + _T_48[3] <= _T_76 @[lib.scala 104:17] + node _T_77 = bits(io.trigger_pkt_any[0].tdata2, 3, 0) @[lib.scala 104:28] + node _T_78 = andr(_T_77) @[lib.scala 104:36] + node _T_79 = and(_T_78, _T_51) @[lib.scala 104:41] + node _T_80 = bits(io.trigger_pkt_any[0].tdata2, 4, 4) @[lib.scala 104:74] + node _T_81 = bits(lsu_match_data_0, 4, 4) @[lib.scala 104:86] + node _T_82 = eq(_T_80, _T_81) @[lib.scala 104:78] + node _T_83 = mux(_T_79, UInt<1>("h01"), _T_82) @[lib.scala 104:23] + _T_48[4] <= _T_83 @[lib.scala 104:17] + node _T_84 = bits(io.trigger_pkt_any[0].tdata2, 4, 0) @[lib.scala 104:28] + node _T_85 = andr(_T_84) @[lib.scala 104:36] + node _T_86 = and(_T_85, _T_51) @[lib.scala 104:41] + node _T_87 = bits(io.trigger_pkt_any[0].tdata2, 5, 5) @[lib.scala 104:74] + node _T_88 = bits(lsu_match_data_0, 5, 5) @[lib.scala 104:86] + node _T_89 = eq(_T_87, _T_88) @[lib.scala 104:78] + node _T_90 = mux(_T_86, UInt<1>("h01"), _T_89) @[lib.scala 104:23] + _T_48[5] <= _T_90 @[lib.scala 104:17] + node _T_91 = bits(io.trigger_pkt_any[0].tdata2, 5, 0) @[lib.scala 104:28] + node _T_92 = andr(_T_91) @[lib.scala 104:36] + node _T_93 = and(_T_92, _T_51) @[lib.scala 104:41] + node _T_94 = bits(io.trigger_pkt_any[0].tdata2, 6, 6) @[lib.scala 104:74] + node _T_95 = bits(lsu_match_data_0, 6, 6) @[lib.scala 104:86] + node _T_96 = eq(_T_94, _T_95) @[lib.scala 104:78] + node _T_97 = mux(_T_93, UInt<1>("h01"), _T_96) @[lib.scala 104:23] + _T_48[6] <= _T_97 @[lib.scala 104:17] + node _T_98 = bits(io.trigger_pkt_any[0].tdata2, 6, 0) @[lib.scala 104:28] + node _T_99 = andr(_T_98) @[lib.scala 104:36] + node _T_100 = and(_T_99, _T_51) @[lib.scala 104:41] + node _T_101 = bits(io.trigger_pkt_any[0].tdata2, 7, 7) @[lib.scala 104:74] + node _T_102 = bits(lsu_match_data_0, 7, 7) @[lib.scala 104:86] + node _T_103 = eq(_T_101, _T_102) @[lib.scala 104:78] + node _T_104 = mux(_T_100, UInt<1>("h01"), _T_103) @[lib.scala 104:23] + _T_48[7] <= _T_104 @[lib.scala 104:17] + node _T_105 = bits(io.trigger_pkt_any[0].tdata2, 7, 0) @[lib.scala 104:28] + node _T_106 = andr(_T_105) @[lib.scala 104:36] + node _T_107 = and(_T_106, _T_51) @[lib.scala 104:41] + node _T_108 = bits(io.trigger_pkt_any[0].tdata2, 8, 8) @[lib.scala 104:74] + node _T_109 = bits(lsu_match_data_0, 8, 8) @[lib.scala 104:86] + node _T_110 = eq(_T_108, _T_109) @[lib.scala 104:78] + node _T_111 = mux(_T_107, UInt<1>("h01"), _T_110) @[lib.scala 104:23] + _T_48[8] <= _T_111 @[lib.scala 104:17] + node _T_112 = bits(io.trigger_pkt_any[0].tdata2, 8, 0) @[lib.scala 104:28] + node _T_113 = andr(_T_112) @[lib.scala 104:36] + node _T_114 = and(_T_113, _T_51) @[lib.scala 104:41] + node _T_115 = bits(io.trigger_pkt_any[0].tdata2, 9, 9) @[lib.scala 104:74] + node _T_116 = bits(lsu_match_data_0, 9, 9) @[lib.scala 104:86] + node _T_117 = eq(_T_115, _T_116) @[lib.scala 104:78] + node _T_118 = mux(_T_114, UInt<1>("h01"), _T_117) @[lib.scala 104:23] + _T_48[9] <= _T_118 @[lib.scala 104:17] + node _T_119 = bits(io.trigger_pkt_any[0].tdata2, 9, 0) @[lib.scala 104:28] + node _T_120 = andr(_T_119) @[lib.scala 104:36] + node _T_121 = and(_T_120, _T_51) @[lib.scala 104:41] + node _T_122 = bits(io.trigger_pkt_any[0].tdata2, 10, 10) @[lib.scala 104:74] + node _T_123 = bits(lsu_match_data_0, 10, 10) @[lib.scala 104:86] + node _T_124 = eq(_T_122, _T_123) @[lib.scala 104:78] + node _T_125 = mux(_T_121, UInt<1>("h01"), _T_124) @[lib.scala 104:23] + _T_48[10] <= _T_125 @[lib.scala 104:17] + node _T_126 = bits(io.trigger_pkt_any[0].tdata2, 10, 0) @[lib.scala 104:28] + node _T_127 = andr(_T_126) @[lib.scala 104:36] + node _T_128 = and(_T_127, _T_51) @[lib.scala 104:41] + node _T_129 = bits(io.trigger_pkt_any[0].tdata2, 11, 11) @[lib.scala 104:74] + node _T_130 = bits(lsu_match_data_0, 11, 11) @[lib.scala 104:86] + node _T_131 = eq(_T_129, _T_130) @[lib.scala 104:78] + node _T_132 = mux(_T_128, UInt<1>("h01"), _T_131) @[lib.scala 104:23] + _T_48[11] <= _T_132 @[lib.scala 104:17] + node _T_133 = bits(io.trigger_pkt_any[0].tdata2, 11, 0) @[lib.scala 104:28] + node _T_134 = andr(_T_133) @[lib.scala 104:36] + node _T_135 = and(_T_134, _T_51) @[lib.scala 104:41] + node _T_136 = bits(io.trigger_pkt_any[0].tdata2, 12, 12) @[lib.scala 104:74] + node _T_137 = bits(lsu_match_data_0, 12, 12) @[lib.scala 104:86] + node _T_138 = eq(_T_136, _T_137) @[lib.scala 104:78] + node _T_139 = mux(_T_135, UInt<1>("h01"), _T_138) @[lib.scala 104:23] + _T_48[12] <= _T_139 @[lib.scala 104:17] + node _T_140 = bits(io.trigger_pkt_any[0].tdata2, 12, 0) @[lib.scala 104:28] + node _T_141 = andr(_T_140) @[lib.scala 104:36] + node _T_142 = and(_T_141, _T_51) @[lib.scala 104:41] + node _T_143 = bits(io.trigger_pkt_any[0].tdata2, 13, 13) @[lib.scala 104:74] + node _T_144 = bits(lsu_match_data_0, 13, 13) @[lib.scala 104:86] + node _T_145 = eq(_T_143, _T_144) @[lib.scala 104:78] + node _T_146 = mux(_T_142, UInt<1>("h01"), _T_145) @[lib.scala 104:23] + _T_48[13] <= _T_146 @[lib.scala 104:17] + node _T_147 = bits(io.trigger_pkt_any[0].tdata2, 13, 0) @[lib.scala 104:28] + node _T_148 = andr(_T_147) @[lib.scala 104:36] + node _T_149 = and(_T_148, _T_51) @[lib.scala 104:41] + node _T_150 = bits(io.trigger_pkt_any[0].tdata2, 14, 14) @[lib.scala 104:74] + node _T_151 = bits(lsu_match_data_0, 14, 14) @[lib.scala 104:86] + node _T_152 = eq(_T_150, _T_151) @[lib.scala 104:78] + node _T_153 = mux(_T_149, UInt<1>("h01"), _T_152) @[lib.scala 104:23] + _T_48[14] <= _T_153 @[lib.scala 104:17] + node _T_154 = bits(io.trigger_pkt_any[0].tdata2, 14, 0) @[lib.scala 104:28] + node _T_155 = andr(_T_154) @[lib.scala 104:36] + node _T_156 = and(_T_155, _T_51) @[lib.scala 104:41] + node _T_157 = bits(io.trigger_pkt_any[0].tdata2, 15, 15) @[lib.scala 104:74] + node _T_158 = bits(lsu_match_data_0, 15, 15) @[lib.scala 104:86] + node _T_159 = eq(_T_157, _T_158) @[lib.scala 104:78] + node _T_160 = mux(_T_156, UInt<1>("h01"), _T_159) @[lib.scala 104:23] + _T_48[15] <= _T_160 @[lib.scala 104:17] + node _T_161 = bits(io.trigger_pkt_any[0].tdata2, 15, 0) @[lib.scala 104:28] + node _T_162 = andr(_T_161) @[lib.scala 104:36] + node _T_163 = and(_T_162, _T_51) @[lib.scala 104:41] + node _T_164 = bits(io.trigger_pkt_any[0].tdata2, 16, 16) @[lib.scala 104:74] + node _T_165 = bits(lsu_match_data_0, 16, 16) @[lib.scala 104:86] + node _T_166 = eq(_T_164, _T_165) @[lib.scala 104:78] + node _T_167 = mux(_T_163, UInt<1>("h01"), _T_166) @[lib.scala 104:23] + _T_48[16] <= _T_167 @[lib.scala 104:17] + node _T_168 = bits(io.trigger_pkt_any[0].tdata2, 16, 0) @[lib.scala 104:28] + node _T_169 = andr(_T_168) @[lib.scala 104:36] + node _T_170 = and(_T_169, _T_51) @[lib.scala 104:41] + node _T_171 = bits(io.trigger_pkt_any[0].tdata2, 17, 17) @[lib.scala 104:74] + node _T_172 = bits(lsu_match_data_0, 17, 17) @[lib.scala 104:86] + node _T_173 = eq(_T_171, _T_172) @[lib.scala 104:78] + node _T_174 = mux(_T_170, UInt<1>("h01"), _T_173) @[lib.scala 104:23] + _T_48[17] <= _T_174 @[lib.scala 104:17] + node _T_175 = bits(io.trigger_pkt_any[0].tdata2, 17, 0) @[lib.scala 104:28] + node _T_176 = andr(_T_175) @[lib.scala 104:36] + node _T_177 = and(_T_176, _T_51) @[lib.scala 104:41] + node _T_178 = bits(io.trigger_pkt_any[0].tdata2, 18, 18) @[lib.scala 104:74] + node _T_179 = bits(lsu_match_data_0, 18, 18) @[lib.scala 104:86] + node _T_180 = eq(_T_178, _T_179) @[lib.scala 104:78] + node _T_181 = mux(_T_177, UInt<1>("h01"), _T_180) @[lib.scala 104:23] + _T_48[18] <= _T_181 @[lib.scala 104:17] + node _T_182 = bits(io.trigger_pkt_any[0].tdata2, 18, 0) @[lib.scala 104:28] + node _T_183 = andr(_T_182) @[lib.scala 104:36] + node _T_184 = and(_T_183, _T_51) @[lib.scala 104:41] + node _T_185 = bits(io.trigger_pkt_any[0].tdata2, 19, 19) @[lib.scala 104:74] + node _T_186 = bits(lsu_match_data_0, 19, 19) @[lib.scala 104:86] + node _T_187 = eq(_T_185, _T_186) @[lib.scala 104:78] + node _T_188 = mux(_T_184, UInt<1>("h01"), _T_187) @[lib.scala 104:23] + _T_48[19] <= _T_188 @[lib.scala 104:17] + node _T_189 = bits(io.trigger_pkt_any[0].tdata2, 19, 0) @[lib.scala 104:28] + node _T_190 = andr(_T_189) @[lib.scala 104:36] + node _T_191 = and(_T_190, _T_51) @[lib.scala 104:41] + node _T_192 = bits(io.trigger_pkt_any[0].tdata2, 20, 20) @[lib.scala 104:74] + node _T_193 = bits(lsu_match_data_0, 20, 20) @[lib.scala 104:86] + node _T_194 = eq(_T_192, _T_193) @[lib.scala 104:78] + node _T_195 = mux(_T_191, UInt<1>("h01"), _T_194) @[lib.scala 104:23] + _T_48[20] <= _T_195 @[lib.scala 104:17] + node _T_196 = bits(io.trigger_pkt_any[0].tdata2, 20, 0) @[lib.scala 104:28] + node _T_197 = andr(_T_196) @[lib.scala 104:36] + node _T_198 = and(_T_197, _T_51) @[lib.scala 104:41] + node _T_199 = bits(io.trigger_pkt_any[0].tdata2, 21, 21) @[lib.scala 104:74] + node _T_200 = bits(lsu_match_data_0, 21, 21) @[lib.scala 104:86] + node _T_201 = eq(_T_199, _T_200) @[lib.scala 104:78] + node _T_202 = mux(_T_198, UInt<1>("h01"), _T_201) @[lib.scala 104:23] + _T_48[21] <= _T_202 @[lib.scala 104:17] + node _T_203 = bits(io.trigger_pkt_any[0].tdata2, 21, 0) @[lib.scala 104:28] + node _T_204 = andr(_T_203) @[lib.scala 104:36] + node _T_205 = and(_T_204, _T_51) @[lib.scala 104:41] + node _T_206 = bits(io.trigger_pkt_any[0].tdata2, 22, 22) @[lib.scala 104:74] + node _T_207 = bits(lsu_match_data_0, 22, 22) @[lib.scala 104:86] + node _T_208 = eq(_T_206, _T_207) @[lib.scala 104:78] + node _T_209 = mux(_T_205, UInt<1>("h01"), _T_208) @[lib.scala 104:23] + _T_48[22] <= _T_209 @[lib.scala 104:17] + node _T_210 = bits(io.trigger_pkt_any[0].tdata2, 22, 0) @[lib.scala 104:28] + node _T_211 = andr(_T_210) @[lib.scala 104:36] + node _T_212 = and(_T_211, _T_51) @[lib.scala 104:41] + node _T_213 = bits(io.trigger_pkt_any[0].tdata2, 23, 23) @[lib.scala 104:74] + node _T_214 = bits(lsu_match_data_0, 23, 23) @[lib.scala 104:86] + node _T_215 = eq(_T_213, _T_214) @[lib.scala 104:78] + node _T_216 = mux(_T_212, UInt<1>("h01"), _T_215) @[lib.scala 104:23] + _T_48[23] <= _T_216 @[lib.scala 104:17] + node _T_217 = bits(io.trigger_pkt_any[0].tdata2, 23, 0) @[lib.scala 104:28] + node _T_218 = andr(_T_217) @[lib.scala 104:36] + node _T_219 = and(_T_218, _T_51) @[lib.scala 104:41] + node _T_220 = bits(io.trigger_pkt_any[0].tdata2, 24, 24) @[lib.scala 104:74] + node _T_221 = bits(lsu_match_data_0, 24, 24) @[lib.scala 104:86] + node _T_222 = eq(_T_220, _T_221) @[lib.scala 104:78] + node _T_223 = mux(_T_219, UInt<1>("h01"), _T_222) @[lib.scala 104:23] + _T_48[24] <= _T_223 @[lib.scala 104:17] + node _T_224 = bits(io.trigger_pkt_any[0].tdata2, 24, 0) @[lib.scala 104:28] + node _T_225 = andr(_T_224) @[lib.scala 104:36] + node _T_226 = and(_T_225, _T_51) @[lib.scala 104:41] + node _T_227 = bits(io.trigger_pkt_any[0].tdata2, 25, 25) @[lib.scala 104:74] + node _T_228 = bits(lsu_match_data_0, 25, 25) @[lib.scala 104:86] + node _T_229 = eq(_T_227, _T_228) @[lib.scala 104:78] + node _T_230 = mux(_T_226, UInt<1>("h01"), _T_229) @[lib.scala 104:23] + _T_48[25] <= _T_230 @[lib.scala 104:17] + node _T_231 = bits(io.trigger_pkt_any[0].tdata2, 25, 0) @[lib.scala 104:28] + node _T_232 = andr(_T_231) @[lib.scala 104:36] + node _T_233 = and(_T_232, _T_51) @[lib.scala 104:41] + node _T_234 = bits(io.trigger_pkt_any[0].tdata2, 26, 26) @[lib.scala 104:74] + node _T_235 = bits(lsu_match_data_0, 26, 26) @[lib.scala 104:86] + node _T_236 = eq(_T_234, _T_235) @[lib.scala 104:78] + node _T_237 = mux(_T_233, UInt<1>("h01"), _T_236) @[lib.scala 104:23] + _T_48[26] <= _T_237 @[lib.scala 104:17] + node _T_238 = bits(io.trigger_pkt_any[0].tdata2, 26, 0) @[lib.scala 104:28] + node _T_239 = andr(_T_238) @[lib.scala 104:36] + node _T_240 = and(_T_239, _T_51) @[lib.scala 104:41] + node _T_241 = bits(io.trigger_pkt_any[0].tdata2, 27, 27) @[lib.scala 104:74] + node _T_242 = bits(lsu_match_data_0, 27, 27) @[lib.scala 104:86] + node _T_243 = eq(_T_241, _T_242) @[lib.scala 104:78] + node _T_244 = mux(_T_240, UInt<1>("h01"), _T_243) @[lib.scala 104:23] + _T_48[27] <= _T_244 @[lib.scala 104:17] + node _T_245 = bits(io.trigger_pkt_any[0].tdata2, 27, 0) @[lib.scala 104:28] + node _T_246 = andr(_T_245) @[lib.scala 104:36] + node _T_247 = and(_T_246, _T_51) @[lib.scala 104:41] + node _T_248 = bits(io.trigger_pkt_any[0].tdata2, 28, 28) @[lib.scala 104:74] + node _T_249 = bits(lsu_match_data_0, 28, 28) @[lib.scala 104:86] + node _T_250 = eq(_T_248, _T_249) @[lib.scala 104:78] + node _T_251 = mux(_T_247, UInt<1>("h01"), _T_250) @[lib.scala 104:23] + _T_48[28] <= _T_251 @[lib.scala 104:17] + node _T_252 = bits(io.trigger_pkt_any[0].tdata2, 28, 0) @[lib.scala 104:28] + node _T_253 = andr(_T_252) @[lib.scala 104:36] + node _T_254 = and(_T_253, _T_51) @[lib.scala 104:41] + node _T_255 = bits(io.trigger_pkt_any[0].tdata2, 29, 29) @[lib.scala 104:74] + node _T_256 = bits(lsu_match_data_0, 29, 29) @[lib.scala 104:86] + node _T_257 = eq(_T_255, _T_256) @[lib.scala 104:78] + node _T_258 = mux(_T_254, UInt<1>("h01"), _T_257) @[lib.scala 104:23] + _T_48[29] <= _T_258 @[lib.scala 104:17] + node _T_259 = bits(io.trigger_pkt_any[0].tdata2, 29, 0) @[lib.scala 104:28] + node _T_260 = andr(_T_259) @[lib.scala 104:36] + node _T_261 = and(_T_260, _T_51) @[lib.scala 104:41] + node _T_262 = bits(io.trigger_pkt_any[0].tdata2, 30, 30) @[lib.scala 104:74] + node _T_263 = bits(lsu_match_data_0, 30, 30) @[lib.scala 104:86] + node _T_264 = eq(_T_262, _T_263) @[lib.scala 104:78] + node _T_265 = mux(_T_261, UInt<1>("h01"), _T_264) @[lib.scala 104:23] + _T_48[30] <= _T_265 @[lib.scala 104:17] + node _T_266 = bits(io.trigger_pkt_any[0].tdata2, 30, 0) @[lib.scala 104:28] + node _T_267 = andr(_T_266) @[lib.scala 104:36] + node _T_268 = and(_T_267, _T_51) @[lib.scala 104:41] + node _T_269 = bits(io.trigger_pkt_any[0].tdata2, 31, 31) @[lib.scala 104:74] + node _T_270 = bits(lsu_match_data_0, 31, 31) @[lib.scala 104:86] + node _T_271 = eq(_T_269, _T_270) @[lib.scala 104:78] + node _T_272 = mux(_T_268, UInt<1>("h01"), _T_271) @[lib.scala 104:23] + _T_48[31] <= _T_272 @[lib.scala 104:17] + node _T_273 = cat(_T_48[1], _T_48[0]) @[lib.scala 105:14] + node _T_274 = cat(_T_48[3], _T_48[2]) @[lib.scala 105:14] + node _T_275 = cat(_T_274, _T_273) @[lib.scala 105:14] + node _T_276 = cat(_T_48[5], _T_48[4]) @[lib.scala 105:14] + node _T_277 = cat(_T_48[7], _T_48[6]) @[lib.scala 105:14] + node _T_278 = cat(_T_277, _T_276) @[lib.scala 105:14] + node _T_279 = cat(_T_278, _T_275) @[lib.scala 105:14] + node _T_280 = cat(_T_48[9], _T_48[8]) @[lib.scala 105:14] + node _T_281 = cat(_T_48[11], _T_48[10]) @[lib.scala 105:14] + node _T_282 = cat(_T_281, _T_280) @[lib.scala 105:14] + node _T_283 = cat(_T_48[13], _T_48[12]) @[lib.scala 105:14] + node _T_284 = cat(_T_48[15], _T_48[14]) @[lib.scala 105:14] + node _T_285 = cat(_T_284, _T_283) @[lib.scala 105:14] + node _T_286 = cat(_T_285, _T_282) @[lib.scala 105:14] + node _T_287 = cat(_T_286, _T_279) @[lib.scala 105:14] + node _T_288 = cat(_T_48[17], _T_48[16]) @[lib.scala 105:14] + node _T_289 = cat(_T_48[19], _T_48[18]) @[lib.scala 105:14] + node _T_290 = cat(_T_289, _T_288) @[lib.scala 105:14] + node _T_291 = cat(_T_48[21], _T_48[20]) @[lib.scala 105:14] + node _T_292 = cat(_T_48[23], _T_48[22]) @[lib.scala 105:14] + node _T_293 = cat(_T_292, _T_291) @[lib.scala 105:14] + node _T_294 = cat(_T_293, _T_290) @[lib.scala 105:14] + node _T_295 = cat(_T_48[25], _T_48[24]) @[lib.scala 105:14] + node _T_296 = cat(_T_48[27], _T_48[26]) @[lib.scala 105:14] + node _T_297 = cat(_T_296, _T_295) @[lib.scala 105:14] + node _T_298 = cat(_T_48[29], _T_48[28]) @[lib.scala 105:14] + node _T_299 = cat(_T_48[31], _T_48[30]) @[lib.scala 105:14] + node _T_300 = cat(_T_299, _T_298) @[lib.scala 105:14] + node _T_301 = cat(_T_300, _T_297) @[lib.scala 105:14] + node _T_302 = cat(_T_301, _T_294) @[lib.scala 105:14] + node _T_303 = cat(_T_302, _T_287) @[lib.scala 105:14] + node _T_304 = andr(_T_303) @[lib.scala 105:25] + node _T_305 = and(_T_46, _T_304) @[lsu_trigger.scala 19:92] + node _T_306 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_trigger.scala 18:71] + node _T_307 = and(io.lsu_pkt_m.valid, _T_306) @[lsu_trigger.scala 18:69] + node _T_308 = and(io.trigger_pkt_any[1].store, io.lsu_pkt_m.bits.store) @[lsu_trigger.scala 18:126] + node _T_309 = and(io.trigger_pkt_any[1].load, io.lsu_pkt_m.bits.load) @[lsu_trigger.scala 19:33] + node _T_310 = eq(io.trigger_pkt_any[1].select, UInt<1>("h00")) @[lsu_trigger.scala 19:60] + node _T_311 = and(_T_309, _T_310) @[lsu_trigger.scala 19:58] + node _T_312 = or(_T_308, _T_311) @[lsu_trigger.scala 18:152] + node _T_313 = and(_T_307, _T_312) @[lsu_trigger.scala 18:94] + node _T_314 = bits(io.trigger_pkt_any[1].match_pkt, 0, 0) @[lsu_trigger.scala 20:107] + wire _T_315 : UInt<1>[32] @[lib.scala 100:24] + node _T_316 = andr(io.trigger_pkt_any[1].tdata2) @[lib.scala 101:45] + node _T_317 = not(_T_316) @[lib.scala 101:39] + node _T_318 = and(_T_314, _T_317) @[lib.scala 101:37] + node _T_319 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[lib.scala 102:48] + node _T_320 = bits(lsu_match_data_1, 0, 0) @[lib.scala 102:60] + node _T_321 = eq(_T_319, _T_320) @[lib.scala 102:52] + node _T_322 = or(_T_318, _T_321) @[lib.scala 102:41] + _T_315[0] <= _T_322 @[lib.scala 102:18] + node _T_323 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[lib.scala 104:28] + node _T_324 = andr(_T_323) @[lib.scala 104:36] + node _T_325 = and(_T_324, _T_318) @[lib.scala 104:41] + node _T_326 = bits(io.trigger_pkt_any[1].tdata2, 1, 1) @[lib.scala 104:74] + node _T_327 = bits(lsu_match_data_1, 1, 1) @[lib.scala 104:86] + node _T_328 = eq(_T_326, _T_327) @[lib.scala 104:78] + node _T_329 = mux(_T_325, UInt<1>("h01"), _T_328) @[lib.scala 104:23] + _T_315[1] <= _T_329 @[lib.scala 104:17] + node _T_330 = bits(io.trigger_pkt_any[1].tdata2, 1, 0) @[lib.scala 104:28] + node _T_331 = andr(_T_330) @[lib.scala 104:36] + node _T_332 = and(_T_331, _T_318) @[lib.scala 104:41] + node _T_333 = bits(io.trigger_pkt_any[1].tdata2, 2, 2) @[lib.scala 104:74] + node _T_334 = bits(lsu_match_data_1, 2, 2) @[lib.scala 104:86] + node _T_335 = eq(_T_333, _T_334) @[lib.scala 104:78] + node _T_336 = mux(_T_332, UInt<1>("h01"), _T_335) @[lib.scala 104:23] + _T_315[2] <= _T_336 @[lib.scala 104:17] + node _T_337 = bits(io.trigger_pkt_any[1].tdata2, 2, 0) @[lib.scala 104:28] + node _T_338 = andr(_T_337) @[lib.scala 104:36] + node _T_339 = and(_T_338, _T_318) @[lib.scala 104:41] + node _T_340 = bits(io.trigger_pkt_any[1].tdata2, 3, 3) @[lib.scala 104:74] + node _T_341 = bits(lsu_match_data_1, 3, 3) @[lib.scala 104:86] + node _T_342 = eq(_T_340, _T_341) @[lib.scala 104:78] + node _T_343 = mux(_T_339, UInt<1>("h01"), _T_342) @[lib.scala 104:23] + _T_315[3] <= _T_343 @[lib.scala 104:17] + node _T_344 = bits(io.trigger_pkt_any[1].tdata2, 3, 0) @[lib.scala 104:28] + node _T_345 = andr(_T_344) @[lib.scala 104:36] + node _T_346 = and(_T_345, _T_318) @[lib.scala 104:41] + node _T_347 = bits(io.trigger_pkt_any[1].tdata2, 4, 4) @[lib.scala 104:74] + node _T_348 = bits(lsu_match_data_1, 4, 4) @[lib.scala 104:86] + node _T_349 = eq(_T_347, _T_348) @[lib.scala 104:78] + node _T_350 = mux(_T_346, UInt<1>("h01"), _T_349) @[lib.scala 104:23] + _T_315[4] <= _T_350 @[lib.scala 104:17] + node _T_351 = bits(io.trigger_pkt_any[1].tdata2, 4, 0) @[lib.scala 104:28] + node _T_352 = andr(_T_351) @[lib.scala 104:36] + node _T_353 = and(_T_352, _T_318) @[lib.scala 104:41] + node _T_354 = bits(io.trigger_pkt_any[1].tdata2, 5, 5) @[lib.scala 104:74] + node _T_355 = bits(lsu_match_data_1, 5, 5) @[lib.scala 104:86] + node _T_356 = eq(_T_354, _T_355) @[lib.scala 104:78] + node _T_357 = mux(_T_353, UInt<1>("h01"), _T_356) @[lib.scala 104:23] + _T_315[5] <= _T_357 @[lib.scala 104:17] + node _T_358 = bits(io.trigger_pkt_any[1].tdata2, 5, 0) @[lib.scala 104:28] + node _T_359 = andr(_T_358) @[lib.scala 104:36] + node _T_360 = and(_T_359, _T_318) @[lib.scala 104:41] + node _T_361 = bits(io.trigger_pkt_any[1].tdata2, 6, 6) @[lib.scala 104:74] + node _T_362 = bits(lsu_match_data_1, 6, 6) @[lib.scala 104:86] + node _T_363 = eq(_T_361, _T_362) @[lib.scala 104:78] + node _T_364 = mux(_T_360, UInt<1>("h01"), _T_363) @[lib.scala 104:23] + _T_315[6] <= _T_364 @[lib.scala 104:17] + node _T_365 = bits(io.trigger_pkt_any[1].tdata2, 6, 0) @[lib.scala 104:28] + node _T_366 = andr(_T_365) @[lib.scala 104:36] + node _T_367 = and(_T_366, _T_318) @[lib.scala 104:41] + node _T_368 = bits(io.trigger_pkt_any[1].tdata2, 7, 7) @[lib.scala 104:74] + node _T_369 = bits(lsu_match_data_1, 7, 7) @[lib.scala 104:86] + node _T_370 = eq(_T_368, _T_369) @[lib.scala 104:78] + node _T_371 = mux(_T_367, UInt<1>("h01"), _T_370) @[lib.scala 104:23] + _T_315[7] <= _T_371 @[lib.scala 104:17] + node _T_372 = bits(io.trigger_pkt_any[1].tdata2, 7, 0) @[lib.scala 104:28] + node _T_373 = andr(_T_372) @[lib.scala 104:36] + node _T_374 = and(_T_373, _T_318) @[lib.scala 104:41] + node _T_375 = bits(io.trigger_pkt_any[1].tdata2, 8, 8) @[lib.scala 104:74] + node _T_376 = bits(lsu_match_data_1, 8, 8) @[lib.scala 104:86] + node _T_377 = eq(_T_375, _T_376) @[lib.scala 104:78] + node _T_378 = mux(_T_374, UInt<1>("h01"), _T_377) @[lib.scala 104:23] + _T_315[8] <= _T_378 @[lib.scala 104:17] + node _T_379 = bits(io.trigger_pkt_any[1].tdata2, 8, 0) @[lib.scala 104:28] + node _T_380 = andr(_T_379) @[lib.scala 104:36] + node _T_381 = and(_T_380, _T_318) @[lib.scala 104:41] + node _T_382 = bits(io.trigger_pkt_any[1].tdata2, 9, 9) @[lib.scala 104:74] + node _T_383 = bits(lsu_match_data_1, 9, 9) @[lib.scala 104:86] + node _T_384 = eq(_T_382, _T_383) @[lib.scala 104:78] + node _T_385 = mux(_T_381, UInt<1>("h01"), _T_384) @[lib.scala 104:23] + _T_315[9] <= _T_385 @[lib.scala 104:17] + node _T_386 = bits(io.trigger_pkt_any[1].tdata2, 9, 0) @[lib.scala 104:28] + node _T_387 = andr(_T_386) @[lib.scala 104:36] + node _T_388 = and(_T_387, _T_318) @[lib.scala 104:41] + node _T_389 = bits(io.trigger_pkt_any[1].tdata2, 10, 10) @[lib.scala 104:74] + node _T_390 = bits(lsu_match_data_1, 10, 10) @[lib.scala 104:86] + node _T_391 = eq(_T_389, _T_390) @[lib.scala 104:78] + node _T_392 = mux(_T_388, UInt<1>("h01"), _T_391) @[lib.scala 104:23] + _T_315[10] <= _T_392 @[lib.scala 104:17] + node _T_393 = bits(io.trigger_pkt_any[1].tdata2, 10, 0) @[lib.scala 104:28] + node _T_394 = andr(_T_393) @[lib.scala 104:36] + node _T_395 = and(_T_394, _T_318) @[lib.scala 104:41] + node _T_396 = bits(io.trigger_pkt_any[1].tdata2, 11, 11) @[lib.scala 104:74] + node _T_397 = bits(lsu_match_data_1, 11, 11) @[lib.scala 104:86] + node _T_398 = eq(_T_396, _T_397) @[lib.scala 104:78] + node _T_399 = mux(_T_395, UInt<1>("h01"), _T_398) @[lib.scala 104:23] + _T_315[11] <= _T_399 @[lib.scala 104:17] + node _T_400 = bits(io.trigger_pkt_any[1].tdata2, 11, 0) @[lib.scala 104:28] + node _T_401 = andr(_T_400) @[lib.scala 104:36] + node _T_402 = and(_T_401, _T_318) @[lib.scala 104:41] + node _T_403 = bits(io.trigger_pkt_any[1].tdata2, 12, 12) @[lib.scala 104:74] + node _T_404 = bits(lsu_match_data_1, 12, 12) @[lib.scala 104:86] + node _T_405 = eq(_T_403, _T_404) @[lib.scala 104:78] + node _T_406 = mux(_T_402, UInt<1>("h01"), _T_405) @[lib.scala 104:23] + _T_315[12] <= _T_406 @[lib.scala 104:17] + node _T_407 = bits(io.trigger_pkt_any[1].tdata2, 12, 0) @[lib.scala 104:28] + node _T_408 = andr(_T_407) @[lib.scala 104:36] + node _T_409 = and(_T_408, _T_318) @[lib.scala 104:41] + node _T_410 = bits(io.trigger_pkt_any[1].tdata2, 13, 13) @[lib.scala 104:74] + node _T_411 = bits(lsu_match_data_1, 13, 13) @[lib.scala 104:86] + node _T_412 = eq(_T_410, _T_411) @[lib.scala 104:78] + node _T_413 = mux(_T_409, UInt<1>("h01"), _T_412) @[lib.scala 104:23] + _T_315[13] <= _T_413 @[lib.scala 104:17] + node _T_414 = bits(io.trigger_pkt_any[1].tdata2, 13, 0) @[lib.scala 104:28] + node _T_415 = andr(_T_414) @[lib.scala 104:36] + node _T_416 = and(_T_415, _T_318) @[lib.scala 104:41] + node _T_417 = bits(io.trigger_pkt_any[1].tdata2, 14, 14) @[lib.scala 104:74] + node _T_418 = bits(lsu_match_data_1, 14, 14) @[lib.scala 104:86] + node _T_419 = eq(_T_417, _T_418) @[lib.scala 104:78] + node _T_420 = mux(_T_416, UInt<1>("h01"), _T_419) @[lib.scala 104:23] + _T_315[14] <= _T_420 @[lib.scala 104:17] + node _T_421 = bits(io.trigger_pkt_any[1].tdata2, 14, 0) @[lib.scala 104:28] + node _T_422 = andr(_T_421) @[lib.scala 104:36] + node _T_423 = and(_T_422, _T_318) @[lib.scala 104:41] + node _T_424 = bits(io.trigger_pkt_any[1].tdata2, 15, 15) @[lib.scala 104:74] + node _T_425 = bits(lsu_match_data_1, 15, 15) @[lib.scala 104:86] + node _T_426 = eq(_T_424, _T_425) @[lib.scala 104:78] + node _T_427 = mux(_T_423, UInt<1>("h01"), _T_426) @[lib.scala 104:23] + _T_315[15] <= _T_427 @[lib.scala 104:17] + node _T_428 = bits(io.trigger_pkt_any[1].tdata2, 15, 0) @[lib.scala 104:28] + node _T_429 = andr(_T_428) @[lib.scala 104:36] + node _T_430 = and(_T_429, _T_318) @[lib.scala 104:41] + node _T_431 = bits(io.trigger_pkt_any[1].tdata2, 16, 16) @[lib.scala 104:74] + node _T_432 = bits(lsu_match_data_1, 16, 16) @[lib.scala 104:86] + node _T_433 = eq(_T_431, _T_432) @[lib.scala 104:78] + node _T_434 = mux(_T_430, UInt<1>("h01"), _T_433) @[lib.scala 104:23] + _T_315[16] <= _T_434 @[lib.scala 104:17] + node _T_435 = bits(io.trigger_pkt_any[1].tdata2, 16, 0) @[lib.scala 104:28] + node _T_436 = andr(_T_435) @[lib.scala 104:36] + node _T_437 = and(_T_436, _T_318) @[lib.scala 104:41] + node _T_438 = bits(io.trigger_pkt_any[1].tdata2, 17, 17) @[lib.scala 104:74] + node _T_439 = bits(lsu_match_data_1, 17, 17) @[lib.scala 104:86] + node _T_440 = eq(_T_438, _T_439) @[lib.scala 104:78] + node _T_441 = mux(_T_437, UInt<1>("h01"), _T_440) @[lib.scala 104:23] + _T_315[17] <= _T_441 @[lib.scala 104:17] + node _T_442 = bits(io.trigger_pkt_any[1].tdata2, 17, 0) @[lib.scala 104:28] + node _T_443 = andr(_T_442) @[lib.scala 104:36] + node _T_444 = and(_T_443, _T_318) @[lib.scala 104:41] + node _T_445 = bits(io.trigger_pkt_any[1].tdata2, 18, 18) @[lib.scala 104:74] + node _T_446 = bits(lsu_match_data_1, 18, 18) @[lib.scala 104:86] + node _T_447 = eq(_T_445, _T_446) @[lib.scala 104:78] + node _T_448 = mux(_T_444, UInt<1>("h01"), _T_447) @[lib.scala 104:23] + _T_315[18] <= _T_448 @[lib.scala 104:17] + node _T_449 = bits(io.trigger_pkt_any[1].tdata2, 18, 0) @[lib.scala 104:28] + node _T_450 = andr(_T_449) @[lib.scala 104:36] + node _T_451 = and(_T_450, _T_318) @[lib.scala 104:41] + node _T_452 = bits(io.trigger_pkt_any[1].tdata2, 19, 19) @[lib.scala 104:74] + node _T_453 = bits(lsu_match_data_1, 19, 19) @[lib.scala 104:86] + node _T_454 = eq(_T_452, _T_453) @[lib.scala 104:78] + node _T_455 = mux(_T_451, UInt<1>("h01"), _T_454) @[lib.scala 104:23] + _T_315[19] <= _T_455 @[lib.scala 104:17] + node _T_456 = bits(io.trigger_pkt_any[1].tdata2, 19, 0) @[lib.scala 104:28] + node _T_457 = andr(_T_456) @[lib.scala 104:36] + node _T_458 = and(_T_457, _T_318) @[lib.scala 104:41] + node _T_459 = bits(io.trigger_pkt_any[1].tdata2, 20, 20) @[lib.scala 104:74] + node _T_460 = bits(lsu_match_data_1, 20, 20) @[lib.scala 104:86] + node _T_461 = eq(_T_459, _T_460) @[lib.scala 104:78] + node _T_462 = mux(_T_458, UInt<1>("h01"), _T_461) @[lib.scala 104:23] + _T_315[20] <= _T_462 @[lib.scala 104:17] + node _T_463 = bits(io.trigger_pkt_any[1].tdata2, 20, 0) @[lib.scala 104:28] + node _T_464 = andr(_T_463) @[lib.scala 104:36] + node _T_465 = and(_T_464, _T_318) @[lib.scala 104:41] + node _T_466 = bits(io.trigger_pkt_any[1].tdata2, 21, 21) @[lib.scala 104:74] + node _T_467 = bits(lsu_match_data_1, 21, 21) @[lib.scala 104:86] + node _T_468 = eq(_T_466, _T_467) @[lib.scala 104:78] + node _T_469 = mux(_T_465, UInt<1>("h01"), _T_468) @[lib.scala 104:23] + _T_315[21] <= _T_469 @[lib.scala 104:17] + node _T_470 = bits(io.trigger_pkt_any[1].tdata2, 21, 0) @[lib.scala 104:28] + node _T_471 = andr(_T_470) @[lib.scala 104:36] + node _T_472 = and(_T_471, _T_318) @[lib.scala 104:41] + node _T_473 = bits(io.trigger_pkt_any[1].tdata2, 22, 22) @[lib.scala 104:74] + node _T_474 = bits(lsu_match_data_1, 22, 22) @[lib.scala 104:86] + node _T_475 = eq(_T_473, _T_474) @[lib.scala 104:78] + node _T_476 = mux(_T_472, UInt<1>("h01"), _T_475) @[lib.scala 104:23] + _T_315[22] <= _T_476 @[lib.scala 104:17] + node _T_477 = bits(io.trigger_pkt_any[1].tdata2, 22, 0) @[lib.scala 104:28] + node _T_478 = andr(_T_477) @[lib.scala 104:36] + node _T_479 = and(_T_478, _T_318) @[lib.scala 104:41] + node _T_480 = bits(io.trigger_pkt_any[1].tdata2, 23, 23) @[lib.scala 104:74] + node _T_481 = bits(lsu_match_data_1, 23, 23) @[lib.scala 104:86] + node _T_482 = eq(_T_480, _T_481) @[lib.scala 104:78] + node _T_483 = mux(_T_479, UInt<1>("h01"), _T_482) @[lib.scala 104:23] + _T_315[23] <= _T_483 @[lib.scala 104:17] + node _T_484 = bits(io.trigger_pkt_any[1].tdata2, 23, 0) @[lib.scala 104:28] + node _T_485 = andr(_T_484) @[lib.scala 104:36] + node _T_486 = and(_T_485, _T_318) @[lib.scala 104:41] + node _T_487 = bits(io.trigger_pkt_any[1].tdata2, 24, 24) @[lib.scala 104:74] + node _T_488 = bits(lsu_match_data_1, 24, 24) @[lib.scala 104:86] + node _T_489 = eq(_T_487, _T_488) @[lib.scala 104:78] + node _T_490 = mux(_T_486, UInt<1>("h01"), _T_489) @[lib.scala 104:23] + _T_315[24] <= _T_490 @[lib.scala 104:17] + node _T_491 = bits(io.trigger_pkt_any[1].tdata2, 24, 0) @[lib.scala 104:28] + node _T_492 = andr(_T_491) @[lib.scala 104:36] + node _T_493 = and(_T_492, _T_318) @[lib.scala 104:41] + node _T_494 = bits(io.trigger_pkt_any[1].tdata2, 25, 25) @[lib.scala 104:74] + node _T_495 = bits(lsu_match_data_1, 25, 25) @[lib.scala 104:86] + node _T_496 = eq(_T_494, _T_495) @[lib.scala 104:78] + node _T_497 = mux(_T_493, UInt<1>("h01"), _T_496) @[lib.scala 104:23] + _T_315[25] <= _T_497 @[lib.scala 104:17] + node _T_498 = bits(io.trigger_pkt_any[1].tdata2, 25, 0) @[lib.scala 104:28] + node _T_499 = andr(_T_498) @[lib.scala 104:36] + node _T_500 = and(_T_499, _T_318) @[lib.scala 104:41] + node _T_501 = bits(io.trigger_pkt_any[1].tdata2, 26, 26) @[lib.scala 104:74] + node _T_502 = bits(lsu_match_data_1, 26, 26) @[lib.scala 104:86] + node _T_503 = eq(_T_501, _T_502) @[lib.scala 104:78] + node _T_504 = mux(_T_500, UInt<1>("h01"), _T_503) @[lib.scala 104:23] + _T_315[26] <= _T_504 @[lib.scala 104:17] + node _T_505 = bits(io.trigger_pkt_any[1].tdata2, 26, 0) @[lib.scala 104:28] + node _T_506 = andr(_T_505) @[lib.scala 104:36] + node _T_507 = and(_T_506, _T_318) @[lib.scala 104:41] + node _T_508 = bits(io.trigger_pkt_any[1].tdata2, 27, 27) @[lib.scala 104:74] + node _T_509 = bits(lsu_match_data_1, 27, 27) @[lib.scala 104:86] + node _T_510 = eq(_T_508, _T_509) @[lib.scala 104:78] + node _T_511 = mux(_T_507, UInt<1>("h01"), _T_510) @[lib.scala 104:23] + _T_315[27] <= _T_511 @[lib.scala 104:17] + node _T_512 = bits(io.trigger_pkt_any[1].tdata2, 27, 0) @[lib.scala 104:28] + node _T_513 = andr(_T_512) @[lib.scala 104:36] + node _T_514 = and(_T_513, _T_318) @[lib.scala 104:41] + node _T_515 = bits(io.trigger_pkt_any[1].tdata2, 28, 28) @[lib.scala 104:74] + node _T_516 = bits(lsu_match_data_1, 28, 28) @[lib.scala 104:86] + node _T_517 = eq(_T_515, _T_516) @[lib.scala 104:78] + node _T_518 = mux(_T_514, UInt<1>("h01"), _T_517) @[lib.scala 104:23] + _T_315[28] <= _T_518 @[lib.scala 104:17] + node _T_519 = bits(io.trigger_pkt_any[1].tdata2, 28, 0) @[lib.scala 104:28] + node _T_520 = andr(_T_519) @[lib.scala 104:36] + node _T_521 = and(_T_520, _T_318) @[lib.scala 104:41] + node _T_522 = bits(io.trigger_pkt_any[1].tdata2, 29, 29) @[lib.scala 104:74] + node _T_523 = bits(lsu_match_data_1, 29, 29) @[lib.scala 104:86] + node _T_524 = eq(_T_522, _T_523) @[lib.scala 104:78] + node _T_525 = mux(_T_521, UInt<1>("h01"), _T_524) @[lib.scala 104:23] + _T_315[29] <= _T_525 @[lib.scala 104:17] + node _T_526 = bits(io.trigger_pkt_any[1].tdata2, 29, 0) @[lib.scala 104:28] + node _T_527 = andr(_T_526) @[lib.scala 104:36] + node _T_528 = and(_T_527, _T_318) @[lib.scala 104:41] + node _T_529 = bits(io.trigger_pkt_any[1].tdata2, 30, 30) @[lib.scala 104:74] + node _T_530 = bits(lsu_match_data_1, 30, 30) @[lib.scala 104:86] + node _T_531 = eq(_T_529, _T_530) @[lib.scala 104:78] + node _T_532 = mux(_T_528, UInt<1>("h01"), _T_531) @[lib.scala 104:23] + _T_315[30] <= _T_532 @[lib.scala 104:17] + node _T_533 = bits(io.trigger_pkt_any[1].tdata2, 30, 0) @[lib.scala 104:28] + node _T_534 = andr(_T_533) @[lib.scala 104:36] + node _T_535 = and(_T_534, _T_318) @[lib.scala 104:41] + node _T_536 = bits(io.trigger_pkt_any[1].tdata2, 31, 31) @[lib.scala 104:74] + node _T_537 = bits(lsu_match_data_1, 31, 31) @[lib.scala 104:86] + node _T_538 = eq(_T_536, _T_537) @[lib.scala 104:78] + node _T_539 = mux(_T_535, UInt<1>("h01"), _T_538) @[lib.scala 104:23] + _T_315[31] <= _T_539 @[lib.scala 104:17] + node _T_540 = cat(_T_315[1], _T_315[0]) @[lib.scala 105:14] + node _T_541 = cat(_T_315[3], _T_315[2]) @[lib.scala 105:14] + node _T_542 = cat(_T_541, _T_540) @[lib.scala 105:14] + node _T_543 = cat(_T_315[5], _T_315[4]) @[lib.scala 105:14] + node _T_544 = cat(_T_315[7], _T_315[6]) @[lib.scala 105:14] + node _T_545 = cat(_T_544, _T_543) @[lib.scala 105:14] + node _T_546 = cat(_T_545, _T_542) @[lib.scala 105:14] + node _T_547 = cat(_T_315[9], _T_315[8]) @[lib.scala 105:14] + node _T_548 = cat(_T_315[11], _T_315[10]) @[lib.scala 105:14] + node _T_549 = cat(_T_548, _T_547) @[lib.scala 105:14] + node _T_550 = cat(_T_315[13], _T_315[12]) @[lib.scala 105:14] + node _T_551 = cat(_T_315[15], _T_315[14]) @[lib.scala 105:14] + node _T_552 = cat(_T_551, _T_550) @[lib.scala 105:14] + node _T_553 = cat(_T_552, _T_549) @[lib.scala 105:14] + node _T_554 = cat(_T_553, _T_546) @[lib.scala 105:14] + node _T_555 = cat(_T_315[17], _T_315[16]) @[lib.scala 105:14] + node _T_556 = cat(_T_315[19], _T_315[18]) @[lib.scala 105:14] + node _T_557 = cat(_T_556, _T_555) @[lib.scala 105:14] + node _T_558 = cat(_T_315[21], _T_315[20]) @[lib.scala 105:14] + node _T_559 = cat(_T_315[23], _T_315[22]) @[lib.scala 105:14] + node _T_560 = cat(_T_559, _T_558) @[lib.scala 105:14] + node _T_561 = cat(_T_560, _T_557) @[lib.scala 105:14] + node _T_562 = cat(_T_315[25], _T_315[24]) @[lib.scala 105:14] + node _T_563 = cat(_T_315[27], _T_315[26]) @[lib.scala 105:14] + node _T_564 = cat(_T_563, _T_562) @[lib.scala 105:14] + node _T_565 = cat(_T_315[29], _T_315[28]) @[lib.scala 105:14] + node _T_566 = cat(_T_315[31], _T_315[30]) @[lib.scala 105:14] + node _T_567 = cat(_T_566, _T_565) @[lib.scala 105:14] + node _T_568 = cat(_T_567, _T_564) @[lib.scala 105:14] + node _T_569 = cat(_T_568, _T_561) @[lib.scala 105:14] + node _T_570 = cat(_T_569, _T_554) @[lib.scala 105:14] + node _T_571 = andr(_T_570) @[lib.scala 105:25] + node _T_572 = and(_T_313, _T_571) @[lsu_trigger.scala 19:92] + node _T_573 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_trigger.scala 18:71] + node _T_574 = and(io.lsu_pkt_m.valid, _T_573) @[lsu_trigger.scala 18:69] + node _T_575 = and(io.trigger_pkt_any[2].store, io.lsu_pkt_m.bits.store) @[lsu_trigger.scala 18:126] + node _T_576 = and(io.trigger_pkt_any[2].load, io.lsu_pkt_m.bits.load) @[lsu_trigger.scala 19:33] + node _T_577 = eq(io.trigger_pkt_any[2].select, UInt<1>("h00")) @[lsu_trigger.scala 19:60] + node _T_578 = and(_T_576, _T_577) @[lsu_trigger.scala 19:58] + node _T_579 = or(_T_575, _T_578) @[lsu_trigger.scala 18:152] + node _T_580 = and(_T_574, _T_579) @[lsu_trigger.scala 18:94] + node _T_581 = bits(io.trigger_pkt_any[2].match_pkt, 0, 0) @[lsu_trigger.scala 20:107] + wire _T_582 : UInt<1>[32] @[lib.scala 100:24] + node _T_583 = andr(io.trigger_pkt_any[2].tdata2) @[lib.scala 101:45] + node _T_584 = not(_T_583) @[lib.scala 101:39] + node _T_585 = and(_T_581, _T_584) @[lib.scala 101:37] + node _T_586 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[lib.scala 102:48] + node _T_587 = bits(lsu_match_data_2, 0, 0) @[lib.scala 102:60] + node _T_588 = eq(_T_586, _T_587) @[lib.scala 102:52] + node _T_589 = or(_T_585, _T_588) @[lib.scala 102:41] + _T_582[0] <= _T_589 @[lib.scala 102:18] + node _T_590 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[lib.scala 104:28] + node _T_591 = andr(_T_590) @[lib.scala 104:36] + node _T_592 = and(_T_591, _T_585) @[lib.scala 104:41] + node _T_593 = bits(io.trigger_pkt_any[2].tdata2, 1, 1) @[lib.scala 104:74] + node _T_594 = bits(lsu_match_data_2, 1, 1) @[lib.scala 104:86] + node _T_595 = eq(_T_593, _T_594) @[lib.scala 104:78] + node _T_596 = mux(_T_592, UInt<1>("h01"), _T_595) @[lib.scala 104:23] + _T_582[1] <= _T_596 @[lib.scala 104:17] + node _T_597 = bits(io.trigger_pkt_any[2].tdata2, 1, 0) @[lib.scala 104:28] + node _T_598 = andr(_T_597) @[lib.scala 104:36] + node _T_599 = and(_T_598, _T_585) @[lib.scala 104:41] + node _T_600 = bits(io.trigger_pkt_any[2].tdata2, 2, 2) @[lib.scala 104:74] + node _T_601 = bits(lsu_match_data_2, 2, 2) @[lib.scala 104:86] + node _T_602 = eq(_T_600, _T_601) @[lib.scala 104:78] + node _T_603 = mux(_T_599, UInt<1>("h01"), _T_602) @[lib.scala 104:23] + _T_582[2] <= _T_603 @[lib.scala 104:17] + node _T_604 = bits(io.trigger_pkt_any[2].tdata2, 2, 0) @[lib.scala 104:28] + node _T_605 = andr(_T_604) @[lib.scala 104:36] + node _T_606 = and(_T_605, _T_585) @[lib.scala 104:41] + node _T_607 = bits(io.trigger_pkt_any[2].tdata2, 3, 3) @[lib.scala 104:74] + node _T_608 = bits(lsu_match_data_2, 3, 3) @[lib.scala 104:86] + node _T_609 = eq(_T_607, _T_608) @[lib.scala 104:78] + node _T_610 = mux(_T_606, UInt<1>("h01"), _T_609) @[lib.scala 104:23] + _T_582[3] <= _T_610 @[lib.scala 104:17] + node _T_611 = bits(io.trigger_pkt_any[2].tdata2, 3, 0) @[lib.scala 104:28] + node _T_612 = andr(_T_611) @[lib.scala 104:36] + node _T_613 = and(_T_612, _T_585) @[lib.scala 104:41] + node _T_614 = bits(io.trigger_pkt_any[2].tdata2, 4, 4) @[lib.scala 104:74] + node _T_615 = bits(lsu_match_data_2, 4, 4) @[lib.scala 104:86] + node _T_616 = eq(_T_614, _T_615) @[lib.scala 104:78] + node _T_617 = mux(_T_613, UInt<1>("h01"), _T_616) @[lib.scala 104:23] + _T_582[4] <= _T_617 @[lib.scala 104:17] + node _T_618 = bits(io.trigger_pkt_any[2].tdata2, 4, 0) @[lib.scala 104:28] + node _T_619 = andr(_T_618) @[lib.scala 104:36] + node _T_620 = and(_T_619, _T_585) @[lib.scala 104:41] + node _T_621 = bits(io.trigger_pkt_any[2].tdata2, 5, 5) @[lib.scala 104:74] + node _T_622 = bits(lsu_match_data_2, 5, 5) @[lib.scala 104:86] + node _T_623 = eq(_T_621, _T_622) @[lib.scala 104:78] + node _T_624 = mux(_T_620, UInt<1>("h01"), _T_623) @[lib.scala 104:23] + _T_582[5] <= _T_624 @[lib.scala 104:17] + node _T_625 = bits(io.trigger_pkt_any[2].tdata2, 5, 0) @[lib.scala 104:28] + node _T_626 = andr(_T_625) @[lib.scala 104:36] + node _T_627 = and(_T_626, _T_585) @[lib.scala 104:41] + node _T_628 = bits(io.trigger_pkt_any[2].tdata2, 6, 6) @[lib.scala 104:74] + node _T_629 = bits(lsu_match_data_2, 6, 6) @[lib.scala 104:86] + node _T_630 = eq(_T_628, _T_629) @[lib.scala 104:78] + node _T_631 = mux(_T_627, UInt<1>("h01"), _T_630) @[lib.scala 104:23] + _T_582[6] <= _T_631 @[lib.scala 104:17] + node _T_632 = bits(io.trigger_pkt_any[2].tdata2, 6, 0) @[lib.scala 104:28] + node _T_633 = andr(_T_632) @[lib.scala 104:36] + node _T_634 = and(_T_633, _T_585) @[lib.scala 104:41] + node _T_635 = bits(io.trigger_pkt_any[2].tdata2, 7, 7) @[lib.scala 104:74] + node _T_636 = bits(lsu_match_data_2, 7, 7) @[lib.scala 104:86] + node _T_637 = eq(_T_635, _T_636) @[lib.scala 104:78] + node _T_638 = mux(_T_634, UInt<1>("h01"), _T_637) @[lib.scala 104:23] + _T_582[7] <= _T_638 @[lib.scala 104:17] + node _T_639 = bits(io.trigger_pkt_any[2].tdata2, 7, 0) @[lib.scala 104:28] + node _T_640 = andr(_T_639) @[lib.scala 104:36] + node _T_641 = and(_T_640, _T_585) @[lib.scala 104:41] + node _T_642 = bits(io.trigger_pkt_any[2].tdata2, 8, 8) @[lib.scala 104:74] + node _T_643 = bits(lsu_match_data_2, 8, 8) @[lib.scala 104:86] + node _T_644 = eq(_T_642, _T_643) @[lib.scala 104:78] + node _T_645 = mux(_T_641, UInt<1>("h01"), _T_644) @[lib.scala 104:23] + _T_582[8] <= _T_645 @[lib.scala 104:17] + node _T_646 = bits(io.trigger_pkt_any[2].tdata2, 8, 0) @[lib.scala 104:28] + node _T_647 = andr(_T_646) @[lib.scala 104:36] + node _T_648 = and(_T_647, _T_585) @[lib.scala 104:41] + node _T_649 = bits(io.trigger_pkt_any[2].tdata2, 9, 9) @[lib.scala 104:74] + node _T_650 = bits(lsu_match_data_2, 9, 9) @[lib.scala 104:86] + node _T_651 = eq(_T_649, _T_650) @[lib.scala 104:78] + node _T_652 = mux(_T_648, UInt<1>("h01"), _T_651) @[lib.scala 104:23] + _T_582[9] <= _T_652 @[lib.scala 104:17] + node _T_653 = bits(io.trigger_pkt_any[2].tdata2, 9, 0) @[lib.scala 104:28] + node _T_654 = andr(_T_653) @[lib.scala 104:36] + node _T_655 = and(_T_654, _T_585) @[lib.scala 104:41] + node _T_656 = bits(io.trigger_pkt_any[2].tdata2, 10, 10) @[lib.scala 104:74] + node _T_657 = bits(lsu_match_data_2, 10, 10) @[lib.scala 104:86] + node _T_658 = eq(_T_656, _T_657) @[lib.scala 104:78] + node _T_659 = mux(_T_655, UInt<1>("h01"), _T_658) @[lib.scala 104:23] + _T_582[10] <= _T_659 @[lib.scala 104:17] + node _T_660 = bits(io.trigger_pkt_any[2].tdata2, 10, 0) @[lib.scala 104:28] + node _T_661 = andr(_T_660) @[lib.scala 104:36] + node _T_662 = and(_T_661, _T_585) @[lib.scala 104:41] + node _T_663 = bits(io.trigger_pkt_any[2].tdata2, 11, 11) @[lib.scala 104:74] + node _T_664 = bits(lsu_match_data_2, 11, 11) @[lib.scala 104:86] + node _T_665 = eq(_T_663, _T_664) @[lib.scala 104:78] + node _T_666 = mux(_T_662, UInt<1>("h01"), _T_665) @[lib.scala 104:23] + _T_582[11] <= _T_666 @[lib.scala 104:17] + node _T_667 = bits(io.trigger_pkt_any[2].tdata2, 11, 0) @[lib.scala 104:28] + node _T_668 = andr(_T_667) @[lib.scala 104:36] + node _T_669 = and(_T_668, _T_585) @[lib.scala 104:41] + node _T_670 = bits(io.trigger_pkt_any[2].tdata2, 12, 12) @[lib.scala 104:74] + node _T_671 = bits(lsu_match_data_2, 12, 12) @[lib.scala 104:86] + node _T_672 = eq(_T_670, _T_671) @[lib.scala 104:78] + node _T_673 = mux(_T_669, UInt<1>("h01"), _T_672) @[lib.scala 104:23] + _T_582[12] <= _T_673 @[lib.scala 104:17] + node _T_674 = bits(io.trigger_pkt_any[2].tdata2, 12, 0) @[lib.scala 104:28] + node _T_675 = andr(_T_674) @[lib.scala 104:36] + node _T_676 = and(_T_675, _T_585) @[lib.scala 104:41] + node _T_677 = bits(io.trigger_pkt_any[2].tdata2, 13, 13) @[lib.scala 104:74] + node _T_678 = bits(lsu_match_data_2, 13, 13) @[lib.scala 104:86] + node _T_679 = eq(_T_677, _T_678) @[lib.scala 104:78] + node _T_680 = mux(_T_676, UInt<1>("h01"), _T_679) @[lib.scala 104:23] + _T_582[13] <= _T_680 @[lib.scala 104:17] + node _T_681 = bits(io.trigger_pkt_any[2].tdata2, 13, 0) @[lib.scala 104:28] + node _T_682 = andr(_T_681) @[lib.scala 104:36] + node _T_683 = and(_T_682, _T_585) @[lib.scala 104:41] + node _T_684 = bits(io.trigger_pkt_any[2].tdata2, 14, 14) @[lib.scala 104:74] + node _T_685 = bits(lsu_match_data_2, 14, 14) @[lib.scala 104:86] + node _T_686 = eq(_T_684, _T_685) @[lib.scala 104:78] + node _T_687 = mux(_T_683, UInt<1>("h01"), _T_686) @[lib.scala 104:23] + _T_582[14] <= _T_687 @[lib.scala 104:17] + node _T_688 = bits(io.trigger_pkt_any[2].tdata2, 14, 0) @[lib.scala 104:28] + node _T_689 = andr(_T_688) @[lib.scala 104:36] + node _T_690 = and(_T_689, _T_585) @[lib.scala 104:41] + node _T_691 = bits(io.trigger_pkt_any[2].tdata2, 15, 15) @[lib.scala 104:74] + node _T_692 = bits(lsu_match_data_2, 15, 15) @[lib.scala 104:86] + node _T_693 = eq(_T_691, _T_692) @[lib.scala 104:78] + node _T_694 = mux(_T_690, UInt<1>("h01"), _T_693) @[lib.scala 104:23] + _T_582[15] <= _T_694 @[lib.scala 104:17] + node _T_695 = bits(io.trigger_pkt_any[2].tdata2, 15, 0) @[lib.scala 104:28] + node _T_696 = andr(_T_695) @[lib.scala 104:36] + node _T_697 = and(_T_696, _T_585) @[lib.scala 104:41] + node _T_698 = bits(io.trigger_pkt_any[2].tdata2, 16, 16) @[lib.scala 104:74] + node _T_699 = bits(lsu_match_data_2, 16, 16) @[lib.scala 104:86] + node _T_700 = eq(_T_698, _T_699) @[lib.scala 104:78] + node _T_701 = mux(_T_697, UInt<1>("h01"), _T_700) @[lib.scala 104:23] + _T_582[16] <= _T_701 @[lib.scala 104:17] + node _T_702 = bits(io.trigger_pkt_any[2].tdata2, 16, 0) @[lib.scala 104:28] + node _T_703 = andr(_T_702) @[lib.scala 104:36] + node _T_704 = and(_T_703, _T_585) @[lib.scala 104:41] + node _T_705 = bits(io.trigger_pkt_any[2].tdata2, 17, 17) @[lib.scala 104:74] + node _T_706 = bits(lsu_match_data_2, 17, 17) @[lib.scala 104:86] + node _T_707 = eq(_T_705, _T_706) @[lib.scala 104:78] + node _T_708 = mux(_T_704, UInt<1>("h01"), _T_707) @[lib.scala 104:23] + _T_582[17] <= _T_708 @[lib.scala 104:17] + node _T_709 = bits(io.trigger_pkt_any[2].tdata2, 17, 0) @[lib.scala 104:28] + node _T_710 = andr(_T_709) @[lib.scala 104:36] + node _T_711 = and(_T_710, _T_585) @[lib.scala 104:41] + node _T_712 = bits(io.trigger_pkt_any[2].tdata2, 18, 18) @[lib.scala 104:74] + node _T_713 = bits(lsu_match_data_2, 18, 18) @[lib.scala 104:86] + node _T_714 = eq(_T_712, _T_713) @[lib.scala 104:78] + node _T_715 = mux(_T_711, UInt<1>("h01"), _T_714) @[lib.scala 104:23] + _T_582[18] <= _T_715 @[lib.scala 104:17] + node _T_716 = bits(io.trigger_pkt_any[2].tdata2, 18, 0) @[lib.scala 104:28] + node _T_717 = andr(_T_716) @[lib.scala 104:36] + node _T_718 = and(_T_717, _T_585) @[lib.scala 104:41] + node _T_719 = bits(io.trigger_pkt_any[2].tdata2, 19, 19) @[lib.scala 104:74] + node _T_720 = bits(lsu_match_data_2, 19, 19) @[lib.scala 104:86] + node _T_721 = eq(_T_719, _T_720) @[lib.scala 104:78] + node _T_722 = mux(_T_718, UInt<1>("h01"), _T_721) @[lib.scala 104:23] + _T_582[19] <= _T_722 @[lib.scala 104:17] + node _T_723 = bits(io.trigger_pkt_any[2].tdata2, 19, 0) @[lib.scala 104:28] + node _T_724 = andr(_T_723) @[lib.scala 104:36] + node _T_725 = and(_T_724, _T_585) @[lib.scala 104:41] + node _T_726 = bits(io.trigger_pkt_any[2].tdata2, 20, 20) @[lib.scala 104:74] + node _T_727 = bits(lsu_match_data_2, 20, 20) @[lib.scala 104:86] + node _T_728 = eq(_T_726, _T_727) @[lib.scala 104:78] + node _T_729 = mux(_T_725, UInt<1>("h01"), _T_728) @[lib.scala 104:23] + _T_582[20] <= _T_729 @[lib.scala 104:17] + node _T_730 = bits(io.trigger_pkt_any[2].tdata2, 20, 0) @[lib.scala 104:28] + node _T_731 = andr(_T_730) @[lib.scala 104:36] + node _T_732 = and(_T_731, _T_585) @[lib.scala 104:41] + node _T_733 = bits(io.trigger_pkt_any[2].tdata2, 21, 21) @[lib.scala 104:74] + node _T_734 = bits(lsu_match_data_2, 21, 21) @[lib.scala 104:86] + node _T_735 = eq(_T_733, _T_734) @[lib.scala 104:78] + node _T_736 = mux(_T_732, UInt<1>("h01"), _T_735) @[lib.scala 104:23] + _T_582[21] <= _T_736 @[lib.scala 104:17] + node _T_737 = bits(io.trigger_pkt_any[2].tdata2, 21, 0) @[lib.scala 104:28] + node _T_738 = andr(_T_737) @[lib.scala 104:36] + node _T_739 = and(_T_738, _T_585) @[lib.scala 104:41] + node _T_740 = bits(io.trigger_pkt_any[2].tdata2, 22, 22) @[lib.scala 104:74] + node _T_741 = bits(lsu_match_data_2, 22, 22) @[lib.scala 104:86] + node _T_742 = eq(_T_740, _T_741) @[lib.scala 104:78] + node _T_743 = mux(_T_739, UInt<1>("h01"), _T_742) @[lib.scala 104:23] + _T_582[22] <= _T_743 @[lib.scala 104:17] + node _T_744 = bits(io.trigger_pkt_any[2].tdata2, 22, 0) @[lib.scala 104:28] + node _T_745 = andr(_T_744) @[lib.scala 104:36] + node _T_746 = and(_T_745, _T_585) @[lib.scala 104:41] + node _T_747 = bits(io.trigger_pkt_any[2].tdata2, 23, 23) @[lib.scala 104:74] + node _T_748 = bits(lsu_match_data_2, 23, 23) @[lib.scala 104:86] + node _T_749 = eq(_T_747, _T_748) @[lib.scala 104:78] + node _T_750 = mux(_T_746, UInt<1>("h01"), _T_749) @[lib.scala 104:23] + _T_582[23] <= _T_750 @[lib.scala 104:17] + node _T_751 = bits(io.trigger_pkt_any[2].tdata2, 23, 0) @[lib.scala 104:28] + node _T_752 = andr(_T_751) @[lib.scala 104:36] + node _T_753 = and(_T_752, _T_585) @[lib.scala 104:41] + node _T_754 = bits(io.trigger_pkt_any[2].tdata2, 24, 24) @[lib.scala 104:74] + node _T_755 = bits(lsu_match_data_2, 24, 24) @[lib.scala 104:86] + node _T_756 = eq(_T_754, _T_755) @[lib.scala 104:78] + node _T_757 = mux(_T_753, UInt<1>("h01"), _T_756) @[lib.scala 104:23] + _T_582[24] <= _T_757 @[lib.scala 104:17] + node _T_758 = bits(io.trigger_pkt_any[2].tdata2, 24, 0) @[lib.scala 104:28] + node _T_759 = andr(_T_758) @[lib.scala 104:36] + node _T_760 = and(_T_759, _T_585) @[lib.scala 104:41] + node _T_761 = bits(io.trigger_pkt_any[2].tdata2, 25, 25) @[lib.scala 104:74] + node _T_762 = bits(lsu_match_data_2, 25, 25) @[lib.scala 104:86] + node _T_763 = eq(_T_761, _T_762) @[lib.scala 104:78] + node _T_764 = mux(_T_760, UInt<1>("h01"), _T_763) @[lib.scala 104:23] + _T_582[25] <= _T_764 @[lib.scala 104:17] + node _T_765 = bits(io.trigger_pkt_any[2].tdata2, 25, 0) @[lib.scala 104:28] + node _T_766 = andr(_T_765) @[lib.scala 104:36] + node _T_767 = and(_T_766, _T_585) @[lib.scala 104:41] + node _T_768 = bits(io.trigger_pkt_any[2].tdata2, 26, 26) @[lib.scala 104:74] + node _T_769 = bits(lsu_match_data_2, 26, 26) @[lib.scala 104:86] + node _T_770 = eq(_T_768, _T_769) @[lib.scala 104:78] + node _T_771 = mux(_T_767, UInt<1>("h01"), _T_770) @[lib.scala 104:23] + _T_582[26] <= _T_771 @[lib.scala 104:17] + node _T_772 = bits(io.trigger_pkt_any[2].tdata2, 26, 0) @[lib.scala 104:28] + node _T_773 = andr(_T_772) @[lib.scala 104:36] + node _T_774 = and(_T_773, _T_585) @[lib.scala 104:41] + node _T_775 = bits(io.trigger_pkt_any[2].tdata2, 27, 27) @[lib.scala 104:74] + node _T_776 = bits(lsu_match_data_2, 27, 27) @[lib.scala 104:86] + node _T_777 = eq(_T_775, _T_776) @[lib.scala 104:78] + node _T_778 = mux(_T_774, UInt<1>("h01"), _T_777) @[lib.scala 104:23] + _T_582[27] <= _T_778 @[lib.scala 104:17] + node _T_779 = bits(io.trigger_pkt_any[2].tdata2, 27, 0) @[lib.scala 104:28] + node _T_780 = andr(_T_779) @[lib.scala 104:36] + node _T_781 = and(_T_780, _T_585) @[lib.scala 104:41] + node _T_782 = bits(io.trigger_pkt_any[2].tdata2, 28, 28) @[lib.scala 104:74] + node _T_783 = bits(lsu_match_data_2, 28, 28) @[lib.scala 104:86] + node _T_784 = eq(_T_782, _T_783) @[lib.scala 104:78] + node _T_785 = mux(_T_781, UInt<1>("h01"), _T_784) @[lib.scala 104:23] + _T_582[28] <= _T_785 @[lib.scala 104:17] + node _T_786 = bits(io.trigger_pkt_any[2].tdata2, 28, 0) @[lib.scala 104:28] + node _T_787 = andr(_T_786) @[lib.scala 104:36] + node _T_788 = and(_T_787, _T_585) @[lib.scala 104:41] + node _T_789 = bits(io.trigger_pkt_any[2].tdata2, 29, 29) @[lib.scala 104:74] + node _T_790 = bits(lsu_match_data_2, 29, 29) @[lib.scala 104:86] + node _T_791 = eq(_T_789, _T_790) @[lib.scala 104:78] + node _T_792 = mux(_T_788, UInt<1>("h01"), _T_791) @[lib.scala 104:23] + _T_582[29] <= _T_792 @[lib.scala 104:17] + node _T_793 = bits(io.trigger_pkt_any[2].tdata2, 29, 0) @[lib.scala 104:28] + node _T_794 = andr(_T_793) @[lib.scala 104:36] + node _T_795 = and(_T_794, _T_585) @[lib.scala 104:41] + node _T_796 = bits(io.trigger_pkt_any[2].tdata2, 30, 30) @[lib.scala 104:74] + node _T_797 = bits(lsu_match_data_2, 30, 30) @[lib.scala 104:86] + node _T_798 = eq(_T_796, _T_797) @[lib.scala 104:78] + node _T_799 = mux(_T_795, UInt<1>("h01"), _T_798) @[lib.scala 104:23] + _T_582[30] <= _T_799 @[lib.scala 104:17] + node _T_800 = bits(io.trigger_pkt_any[2].tdata2, 30, 0) @[lib.scala 104:28] + node _T_801 = andr(_T_800) @[lib.scala 104:36] + node _T_802 = and(_T_801, _T_585) @[lib.scala 104:41] + node _T_803 = bits(io.trigger_pkt_any[2].tdata2, 31, 31) @[lib.scala 104:74] + node _T_804 = bits(lsu_match_data_2, 31, 31) @[lib.scala 104:86] + node _T_805 = eq(_T_803, _T_804) @[lib.scala 104:78] + node _T_806 = mux(_T_802, UInt<1>("h01"), _T_805) @[lib.scala 104:23] + _T_582[31] <= _T_806 @[lib.scala 104:17] + node _T_807 = cat(_T_582[1], _T_582[0]) @[lib.scala 105:14] + node _T_808 = cat(_T_582[3], _T_582[2]) @[lib.scala 105:14] + node _T_809 = cat(_T_808, _T_807) @[lib.scala 105:14] + node _T_810 = cat(_T_582[5], _T_582[4]) @[lib.scala 105:14] + node _T_811 = cat(_T_582[7], _T_582[6]) @[lib.scala 105:14] + node _T_812 = cat(_T_811, _T_810) @[lib.scala 105:14] + node _T_813 = cat(_T_812, _T_809) @[lib.scala 105:14] + node _T_814 = cat(_T_582[9], _T_582[8]) @[lib.scala 105:14] + node _T_815 = cat(_T_582[11], _T_582[10]) @[lib.scala 105:14] + node _T_816 = cat(_T_815, _T_814) @[lib.scala 105:14] + node _T_817 = cat(_T_582[13], _T_582[12]) @[lib.scala 105:14] + node _T_818 = cat(_T_582[15], _T_582[14]) @[lib.scala 105:14] + node _T_819 = cat(_T_818, _T_817) @[lib.scala 105:14] + node _T_820 = cat(_T_819, _T_816) @[lib.scala 105:14] + node _T_821 = cat(_T_820, _T_813) @[lib.scala 105:14] + node _T_822 = cat(_T_582[17], _T_582[16]) @[lib.scala 105:14] + node _T_823 = cat(_T_582[19], _T_582[18]) @[lib.scala 105:14] + node _T_824 = cat(_T_823, _T_822) @[lib.scala 105:14] + node _T_825 = cat(_T_582[21], _T_582[20]) @[lib.scala 105:14] + node _T_826 = cat(_T_582[23], _T_582[22]) @[lib.scala 105:14] + node _T_827 = cat(_T_826, _T_825) @[lib.scala 105:14] + node _T_828 = cat(_T_827, _T_824) @[lib.scala 105:14] + node _T_829 = cat(_T_582[25], _T_582[24]) @[lib.scala 105:14] + node _T_830 = cat(_T_582[27], _T_582[26]) @[lib.scala 105:14] + node _T_831 = cat(_T_830, _T_829) @[lib.scala 105:14] + node _T_832 = cat(_T_582[29], _T_582[28]) @[lib.scala 105:14] + node _T_833 = cat(_T_582[31], _T_582[30]) @[lib.scala 105:14] + node _T_834 = cat(_T_833, _T_832) @[lib.scala 105:14] + node _T_835 = cat(_T_834, _T_831) @[lib.scala 105:14] + node _T_836 = cat(_T_835, _T_828) @[lib.scala 105:14] + node _T_837 = cat(_T_836, _T_821) @[lib.scala 105:14] + node _T_838 = andr(_T_837) @[lib.scala 105:25] + node _T_839 = and(_T_580, _T_838) @[lsu_trigger.scala 19:92] + node _T_840 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_trigger.scala 18:71] + node _T_841 = and(io.lsu_pkt_m.valid, _T_840) @[lsu_trigger.scala 18:69] + node _T_842 = and(io.trigger_pkt_any[3].store, io.lsu_pkt_m.bits.store) @[lsu_trigger.scala 18:126] + node _T_843 = and(io.trigger_pkt_any[3].load, io.lsu_pkt_m.bits.load) @[lsu_trigger.scala 19:33] + node _T_844 = eq(io.trigger_pkt_any[3].select, UInt<1>("h00")) @[lsu_trigger.scala 19:60] + node _T_845 = and(_T_843, _T_844) @[lsu_trigger.scala 19:58] + node _T_846 = or(_T_842, _T_845) @[lsu_trigger.scala 18:152] + node _T_847 = and(_T_841, _T_846) @[lsu_trigger.scala 18:94] + node _T_848 = bits(io.trigger_pkt_any[3].match_pkt, 0, 0) @[lsu_trigger.scala 20:107] + wire _T_849 : UInt<1>[32] @[lib.scala 100:24] + node _T_850 = andr(io.trigger_pkt_any[3].tdata2) @[lib.scala 101:45] + node _T_851 = not(_T_850) @[lib.scala 101:39] + node _T_852 = and(_T_848, _T_851) @[lib.scala 101:37] + node _T_853 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[lib.scala 102:48] + node _T_854 = bits(lsu_match_data_3, 0, 0) @[lib.scala 102:60] + node _T_855 = eq(_T_853, _T_854) @[lib.scala 102:52] + node _T_856 = or(_T_852, _T_855) @[lib.scala 102:41] + _T_849[0] <= _T_856 @[lib.scala 102:18] + node _T_857 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[lib.scala 104:28] + node _T_858 = andr(_T_857) @[lib.scala 104:36] + node _T_859 = and(_T_858, _T_852) @[lib.scala 104:41] + node _T_860 = bits(io.trigger_pkt_any[3].tdata2, 1, 1) @[lib.scala 104:74] + node _T_861 = bits(lsu_match_data_3, 1, 1) @[lib.scala 104:86] + node _T_862 = eq(_T_860, _T_861) @[lib.scala 104:78] + node _T_863 = mux(_T_859, UInt<1>("h01"), _T_862) @[lib.scala 104:23] + _T_849[1] <= _T_863 @[lib.scala 104:17] + node _T_864 = bits(io.trigger_pkt_any[3].tdata2, 1, 0) @[lib.scala 104:28] + node _T_865 = andr(_T_864) @[lib.scala 104:36] + node _T_866 = and(_T_865, _T_852) @[lib.scala 104:41] + node _T_867 = bits(io.trigger_pkt_any[3].tdata2, 2, 2) @[lib.scala 104:74] + node _T_868 = bits(lsu_match_data_3, 2, 2) @[lib.scala 104:86] + node _T_869 = eq(_T_867, _T_868) @[lib.scala 104:78] + node _T_870 = mux(_T_866, UInt<1>("h01"), _T_869) @[lib.scala 104:23] + _T_849[2] <= _T_870 @[lib.scala 104:17] + node _T_871 = bits(io.trigger_pkt_any[3].tdata2, 2, 0) @[lib.scala 104:28] + node _T_872 = andr(_T_871) @[lib.scala 104:36] + node _T_873 = and(_T_872, _T_852) @[lib.scala 104:41] + node _T_874 = bits(io.trigger_pkt_any[3].tdata2, 3, 3) @[lib.scala 104:74] + node _T_875 = bits(lsu_match_data_3, 3, 3) @[lib.scala 104:86] + node _T_876 = eq(_T_874, _T_875) @[lib.scala 104:78] + node _T_877 = mux(_T_873, UInt<1>("h01"), _T_876) @[lib.scala 104:23] + _T_849[3] <= _T_877 @[lib.scala 104:17] + node _T_878 = bits(io.trigger_pkt_any[3].tdata2, 3, 0) @[lib.scala 104:28] + node _T_879 = andr(_T_878) @[lib.scala 104:36] + node _T_880 = and(_T_879, _T_852) @[lib.scala 104:41] + node _T_881 = bits(io.trigger_pkt_any[3].tdata2, 4, 4) @[lib.scala 104:74] + node _T_882 = bits(lsu_match_data_3, 4, 4) @[lib.scala 104:86] + node _T_883 = eq(_T_881, _T_882) @[lib.scala 104:78] + node _T_884 = mux(_T_880, UInt<1>("h01"), _T_883) @[lib.scala 104:23] + _T_849[4] <= _T_884 @[lib.scala 104:17] + node _T_885 = bits(io.trigger_pkt_any[3].tdata2, 4, 0) @[lib.scala 104:28] + node _T_886 = andr(_T_885) @[lib.scala 104:36] + node _T_887 = and(_T_886, _T_852) @[lib.scala 104:41] + node _T_888 = bits(io.trigger_pkt_any[3].tdata2, 5, 5) @[lib.scala 104:74] + node _T_889 = bits(lsu_match_data_3, 5, 5) @[lib.scala 104:86] + node _T_890 = eq(_T_888, _T_889) @[lib.scala 104:78] + node _T_891 = mux(_T_887, UInt<1>("h01"), _T_890) @[lib.scala 104:23] + _T_849[5] <= _T_891 @[lib.scala 104:17] + node _T_892 = bits(io.trigger_pkt_any[3].tdata2, 5, 0) @[lib.scala 104:28] + node _T_893 = andr(_T_892) @[lib.scala 104:36] + node _T_894 = and(_T_893, _T_852) @[lib.scala 104:41] + node _T_895 = bits(io.trigger_pkt_any[3].tdata2, 6, 6) @[lib.scala 104:74] + node _T_896 = bits(lsu_match_data_3, 6, 6) @[lib.scala 104:86] + node _T_897 = eq(_T_895, _T_896) @[lib.scala 104:78] + node _T_898 = mux(_T_894, UInt<1>("h01"), _T_897) @[lib.scala 104:23] + _T_849[6] <= _T_898 @[lib.scala 104:17] + node _T_899 = bits(io.trigger_pkt_any[3].tdata2, 6, 0) @[lib.scala 104:28] + node _T_900 = andr(_T_899) @[lib.scala 104:36] + node _T_901 = and(_T_900, _T_852) @[lib.scala 104:41] + node _T_902 = bits(io.trigger_pkt_any[3].tdata2, 7, 7) @[lib.scala 104:74] + node _T_903 = bits(lsu_match_data_3, 7, 7) @[lib.scala 104:86] + node _T_904 = eq(_T_902, _T_903) @[lib.scala 104:78] + node _T_905 = mux(_T_901, UInt<1>("h01"), _T_904) @[lib.scala 104:23] + _T_849[7] <= _T_905 @[lib.scala 104:17] + node _T_906 = bits(io.trigger_pkt_any[3].tdata2, 7, 0) @[lib.scala 104:28] + node _T_907 = andr(_T_906) @[lib.scala 104:36] + node _T_908 = and(_T_907, _T_852) @[lib.scala 104:41] + node _T_909 = bits(io.trigger_pkt_any[3].tdata2, 8, 8) @[lib.scala 104:74] + node _T_910 = bits(lsu_match_data_3, 8, 8) @[lib.scala 104:86] + node _T_911 = eq(_T_909, _T_910) @[lib.scala 104:78] + node _T_912 = mux(_T_908, UInt<1>("h01"), _T_911) @[lib.scala 104:23] + _T_849[8] <= _T_912 @[lib.scala 104:17] + node _T_913 = bits(io.trigger_pkt_any[3].tdata2, 8, 0) @[lib.scala 104:28] + node _T_914 = andr(_T_913) @[lib.scala 104:36] + node _T_915 = and(_T_914, _T_852) @[lib.scala 104:41] + node _T_916 = bits(io.trigger_pkt_any[3].tdata2, 9, 9) @[lib.scala 104:74] + node _T_917 = bits(lsu_match_data_3, 9, 9) @[lib.scala 104:86] + node _T_918 = eq(_T_916, _T_917) @[lib.scala 104:78] + node _T_919 = mux(_T_915, UInt<1>("h01"), _T_918) @[lib.scala 104:23] + _T_849[9] <= _T_919 @[lib.scala 104:17] + node _T_920 = bits(io.trigger_pkt_any[3].tdata2, 9, 0) @[lib.scala 104:28] + node _T_921 = andr(_T_920) @[lib.scala 104:36] + node _T_922 = and(_T_921, _T_852) @[lib.scala 104:41] + node _T_923 = bits(io.trigger_pkt_any[3].tdata2, 10, 10) @[lib.scala 104:74] + node _T_924 = bits(lsu_match_data_3, 10, 10) @[lib.scala 104:86] + node _T_925 = eq(_T_923, _T_924) @[lib.scala 104:78] + node _T_926 = mux(_T_922, UInt<1>("h01"), _T_925) @[lib.scala 104:23] + _T_849[10] <= _T_926 @[lib.scala 104:17] + node _T_927 = bits(io.trigger_pkt_any[3].tdata2, 10, 0) @[lib.scala 104:28] + node _T_928 = andr(_T_927) @[lib.scala 104:36] + node _T_929 = and(_T_928, _T_852) @[lib.scala 104:41] + node _T_930 = bits(io.trigger_pkt_any[3].tdata2, 11, 11) @[lib.scala 104:74] + node _T_931 = bits(lsu_match_data_3, 11, 11) @[lib.scala 104:86] + node _T_932 = eq(_T_930, _T_931) @[lib.scala 104:78] + node _T_933 = mux(_T_929, UInt<1>("h01"), _T_932) @[lib.scala 104:23] + _T_849[11] <= _T_933 @[lib.scala 104:17] + node _T_934 = bits(io.trigger_pkt_any[3].tdata2, 11, 0) @[lib.scala 104:28] + node _T_935 = andr(_T_934) @[lib.scala 104:36] + node _T_936 = and(_T_935, _T_852) @[lib.scala 104:41] + node _T_937 = bits(io.trigger_pkt_any[3].tdata2, 12, 12) @[lib.scala 104:74] + node _T_938 = bits(lsu_match_data_3, 12, 12) @[lib.scala 104:86] + node _T_939 = eq(_T_937, _T_938) @[lib.scala 104:78] + node _T_940 = mux(_T_936, UInt<1>("h01"), _T_939) @[lib.scala 104:23] + _T_849[12] <= _T_940 @[lib.scala 104:17] + node _T_941 = bits(io.trigger_pkt_any[3].tdata2, 12, 0) @[lib.scala 104:28] + node _T_942 = andr(_T_941) @[lib.scala 104:36] + node _T_943 = and(_T_942, _T_852) @[lib.scala 104:41] + node _T_944 = bits(io.trigger_pkt_any[3].tdata2, 13, 13) @[lib.scala 104:74] + node _T_945 = bits(lsu_match_data_3, 13, 13) @[lib.scala 104:86] + node _T_946 = eq(_T_944, _T_945) @[lib.scala 104:78] + node _T_947 = mux(_T_943, UInt<1>("h01"), _T_946) @[lib.scala 104:23] + _T_849[13] <= _T_947 @[lib.scala 104:17] + node _T_948 = bits(io.trigger_pkt_any[3].tdata2, 13, 0) @[lib.scala 104:28] + node _T_949 = andr(_T_948) @[lib.scala 104:36] + node _T_950 = and(_T_949, _T_852) @[lib.scala 104:41] + node _T_951 = bits(io.trigger_pkt_any[3].tdata2, 14, 14) @[lib.scala 104:74] + node _T_952 = bits(lsu_match_data_3, 14, 14) @[lib.scala 104:86] + node _T_953 = eq(_T_951, _T_952) @[lib.scala 104:78] + node _T_954 = mux(_T_950, UInt<1>("h01"), _T_953) @[lib.scala 104:23] + _T_849[14] <= _T_954 @[lib.scala 104:17] + node _T_955 = bits(io.trigger_pkt_any[3].tdata2, 14, 0) @[lib.scala 104:28] + node _T_956 = andr(_T_955) @[lib.scala 104:36] + node _T_957 = and(_T_956, _T_852) @[lib.scala 104:41] + node _T_958 = bits(io.trigger_pkt_any[3].tdata2, 15, 15) @[lib.scala 104:74] + node _T_959 = bits(lsu_match_data_3, 15, 15) @[lib.scala 104:86] + node _T_960 = eq(_T_958, _T_959) @[lib.scala 104:78] + node _T_961 = mux(_T_957, UInt<1>("h01"), _T_960) @[lib.scala 104:23] + _T_849[15] <= _T_961 @[lib.scala 104:17] + node _T_962 = bits(io.trigger_pkt_any[3].tdata2, 15, 0) @[lib.scala 104:28] + node _T_963 = andr(_T_962) @[lib.scala 104:36] + node _T_964 = and(_T_963, _T_852) @[lib.scala 104:41] + node _T_965 = bits(io.trigger_pkt_any[3].tdata2, 16, 16) @[lib.scala 104:74] + node _T_966 = bits(lsu_match_data_3, 16, 16) @[lib.scala 104:86] + node _T_967 = eq(_T_965, _T_966) @[lib.scala 104:78] + node _T_968 = mux(_T_964, UInt<1>("h01"), _T_967) @[lib.scala 104:23] + _T_849[16] <= _T_968 @[lib.scala 104:17] + node _T_969 = bits(io.trigger_pkt_any[3].tdata2, 16, 0) @[lib.scala 104:28] + node _T_970 = andr(_T_969) @[lib.scala 104:36] + node _T_971 = and(_T_970, _T_852) @[lib.scala 104:41] + node _T_972 = bits(io.trigger_pkt_any[3].tdata2, 17, 17) @[lib.scala 104:74] + node _T_973 = bits(lsu_match_data_3, 17, 17) @[lib.scala 104:86] + node _T_974 = eq(_T_972, _T_973) @[lib.scala 104:78] + node _T_975 = mux(_T_971, UInt<1>("h01"), _T_974) @[lib.scala 104:23] + _T_849[17] <= _T_975 @[lib.scala 104:17] + node _T_976 = bits(io.trigger_pkt_any[3].tdata2, 17, 0) @[lib.scala 104:28] + node _T_977 = andr(_T_976) @[lib.scala 104:36] + node _T_978 = and(_T_977, _T_852) @[lib.scala 104:41] + node _T_979 = bits(io.trigger_pkt_any[3].tdata2, 18, 18) @[lib.scala 104:74] + node _T_980 = bits(lsu_match_data_3, 18, 18) @[lib.scala 104:86] + node _T_981 = eq(_T_979, _T_980) @[lib.scala 104:78] + node _T_982 = mux(_T_978, UInt<1>("h01"), _T_981) @[lib.scala 104:23] + _T_849[18] <= _T_982 @[lib.scala 104:17] + node _T_983 = bits(io.trigger_pkt_any[3].tdata2, 18, 0) @[lib.scala 104:28] + node _T_984 = andr(_T_983) @[lib.scala 104:36] + node _T_985 = and(_T_984, _T_852) @[lib.scala 104:41] + node _T_986 = bits(io.trigger_pkt_any[3].tdata2, 19, 19) @[lib.scala 104:74] + node _T_987 = bits(lsu_match_data_3, 19, 19) @[lib.scala 104:86] + node _T_988 = eq(_T_986, _T_987) @[lib.scala 104:78] + node _T_989 = mux(_T_985, UInt<1>("h01"), _T_988) @[lib.scala 104:23] + _T_849[19] <= _T_989 @[lib.scala 104:17] + node _T_990 = bits(io.trigger_pkt_any[3].tdata2, 19, 0) @[lib.scala 104:28] + node _T_991 = andr(_T_990) @[lib.scala 104:36] + node _T_992 = and(_T_991, _T_852) @[lib.scala 104:41] + node _T_993 = bits(io.trigger_pkt_any[3].tdata2, 20, 20) @[lib.scala 104:74] + node _T_994 = bits(lsu_match_data_3, 20, 20) @[lib.scala 104:86] + node _T_995 = eq(_T_993, _T_994) @[lib.scala 104:78] + node _T_996 = mux(_T_992, UInt<1>("h01"), _T_995) @[lib.scala 104:23] + _T_849[20] <= _T_996 @[lib.scala 104:17] + node _T_997 = bits(io.trigger_pkt_any[3].tdata2, 20, 0) @[lib.scala 104:28] + node _T_998 = andr(_T_997) @[lib.scala 104:36] + node _T_999 = and(_T_998, _T_852) @[lib.scala 104:41] + node _T_1000 = bits(io.trigger_pkt_any[3].tdata2, 21, 21) @[lib.scala 104:74] + node _T_1001 = bits(lsu_match_data_3, 21, 21) @[lib.scala 104:86] + node _T_1002 = eq(_T_1000, _T_1001) @[lib.scala 104:78] + node _T_1003 = mux(_T_999, UInt<1>("h01"), _T_1002) @[lib.scala 104:23] + _T_849[21] <= _T_1003 @[lib.scala 104:17] + node _T_1004 = bits(io.trigger_pkt_any[3].tdata2, 21, 0) @[lib.scala 104:28] + node _T_1005 = andr(_T_1004) @[lib.scala 104:36] + node _T_1006 = and(_T_1005, _T_852) @[lib.scala 104:41] + node _T_1007 = bits(io.trigger_pkt_any[3].tdata2, 22, 22) @[lib.scala 104:74] + node _T_1008 = bits(lsu_match_data_3, 22, 22) @[lib.scala 104:86] + node _T_1009 = eq(_T_1007, _T_1008) @[lib.scala 104:78] + node _T_1010 = mux(_T_1006, UInt<1>("h01"), _T_1009) @[lib.scala 104:23] + _T_849[22] <= _T_1010 @[lib.scala 104:17] + node _T_1011 = bits(io.trigger_pkt_any[3].tdata2, 22, 0) @[lib.scala 104:28] + node _T_1012 = andr(_T_1011) @[lib.scala 104:36] + node _T_1013 = and(_T_1012, _T_852) @[lib.scala 104:41] + node _T_1014 = bits(io.trigger_pkt_any[3].tdata2, 23, 23) @[lib.scala 104:74] + node _T_1015 = bits(lsu_match_data_3, 23, 23) @[lib.scala 104:86] + node _T_1016 = eq(_T_1014, _T_1015) @[lib.scala 104:78] + node _T_1017 = mux(_T_1013, UInt<1>("h01"), _T_1016) @[lib.scala 104:23] + _T_849[23] <= _T_1017 @[lib.scala 104:17] + node _T_1018 = bits(io.trigger_pkt_any[3].tdata2, 23, 0) @[lib.scala 104:28] + node _T_1019 = andr(_T_1018) @[lib.scala 104:36] + node _T_1020 = and(_T_1019, _T_852) @[lib.scala 104:41] + node _T_1021 = bits(io.trigger_pkt_any[3].tdata2, 24, 24) @[lib.scala 104:74] + node _T_1022 = bits(lsu_match_data_3, 24, 24) @[lib.scala 104:86] + node _T_1023 = eq(_T_1021, _T_1022) @[lib.scala 104:78] + node _T_1024 = mux(_T_1020, UInt<1>("h01"), _T_1023) @[lib.scala 104:23] + _T_849[24] <= _T_1024 @[lib.scala 104:17] + node _T_1025 = bits(io.trigger_pkt_any[3].tdata2, 24, 0) @[lib.scala 104:28] + node _T_1026 = andr(_T_1025) @[lib.scala 104:36] + node _T_1027 = and(_T_1026, _T_852) @[lib.scala 104:41] + node _T_1028 = bits(io.trigger_pkt_any[3].tdata2, 25, 25) @[lib.scala 104:74] + node _T_1029 = bits(lsu_match_data_3, 25, 25) @[lib.scala 104:86] + node _T_1030 = eq(_T_1028, _T_1029) @[lib.scala 104:78] + node _T_1031 = mux(_T_1027, UInt<1>("h01"), _T_1030) @[lib.scala 104:23] + _T_849[25] <= _T_1031 @[lib.scala 104:17] + node _T_1032 = bits(io.trigger_pkt_any[3].tdata2, 25, 0) @[lib.scala 104:28] + node _T_1033 = andr(_T_1032) @[lib.scala 104:36] + node _T_1034 = and(_T_1033, _T_852) @[lib.scala 104:41] + node _T_1035 = bits(io.trigger_pkt_any[3].tdata2, 26, 26) @[lib.scala 104:74] + node _T_1036 = bits(lsu_match_data_3, 26, 26) @[lib.scala 104:86] + node _T_1037 = eq(_T_1035, _T_1036) @[lib.scala 104:78] + node _T_1038 = mux(_T_1034, UInt<1>("h01"), _T_1037) @[lib.scala 104:23] + _T_849[26] <= _T_1038 @[lib.scala 104:17] + node _T_1039 = bits(io.trigger_pkt_any[3].tdata2, 26, 0) @[lib.scala 104:28] + node _T_1040 = andr(_T_1039) @[lib.scala 104:36] + node _T_1041 = and(_T_1040, _T_852) @[lib.scala 104:41] + node _T_1042 = bits(io.trigger_pkt_any[3].tdata2, 27, 27) @[lib.scala 104:74] + node _T_1043 = bits(lsu_match_data_3, 27, 27) @[lib.scala 104:86] + node _T_1044 = eq(_T_1042, _T_1043) @[lib.scala 104:78] + node _T_1045 = mux(_T_1041, UInt<1>("h01"), _T_1044) @[lib.scala 104:23] + _T_849[27] <= _T_1045 @[lib.scala 104:17] + node _T_1046 = bits(io.trigger_pkt_any[3].tdata2, 27, 0) @[lib.scala 104:28] + node _T_1047 = andr(_T_1046) @[lib.scala 104:36] + node _T_1048 = and(_T_1047, _T_852) @[lib.scala 104:41] + node _T_1049 = bits(io.trigger_pkt_any[3].tdata2, 28, 28) @[lib.scala 104:74] + node _T_1050 = bits(lsu_match_data_3, 28, 28) @[lib.scala 104:86] + node _T_1051 = eq(_T_1049, _T_1050) @[lib.scala 104:78] + node _T_1052 = mux(_T_1048, UInt<1>("h01"), _T_1051) @[lib.scala 104:23] + _T_849[28] <= _T_1052 @[lib.scala 104:17] + node _T_1053 = bits(io.trigger_pkt_any[3].tdata2, 28, 0) @[lib.scala 104:28] + node _T_1054 = andr(_T_1053) @[lib.scala 104:36] + node _T_1055 = and(_T_1054, _T_852) @[lib.scala 104:41] + node _T_1056 = bits(io.trigger_pkt_any[3].tdata2, 29, 29) @[lib.scala 104:74] + node _T_1057 = bits(lsu_match_data_3, 29, 29) @[lib.scala 104:86] + node _T_1058 = eq(_T_1056, _T_1057) @[lib.scala 104:78] + node _T_1059 = mux(_T_1055, UInt<1>("h01"), _T_1058) @[lib.scala 104:23] + _T_849[29] <= _T_1059 @[lib.scala 104:17] + node _T_1060 = bits(io.trigger_pkt_any[3].tdata2, 29, 0) @[lib.scala 104:28] + node _T_1061 = andr(_T_1060) @[lib.scala 104:36] + node _T_1062 = and(_T_1061, _T_852) @[lib.scala 104:41] + node _T_1063 = bits(io.trigger_pkt_any[3].tdata2, 30, 30) @[lib.scala 104:74] + node _T_1064 = bits(lsu_match_data_3, 30, 30) @[lib.scala 104:86] + node _T_1065 = eq(_T_1063, _T_1064) @[lib.scala 104:78] + node _T_1066 = mux(_T_1062, UInt<1>("h01"), _T_1065) @[lib.scala 104:23] + _T_849[30] <= _T_1066 @[lib.scala 104:17] + node _T_1067 = bits(io.trigger_pkt_any[3].tdata2, 30, 0) @[lib.scala 104:28] + node _T_1068 = andr(_T_1067) @[lib.scala 104:36] + node _T_1069 = and(_T_1068, _T_852) @[lib.scala 104:41] + node _T_1070 = bits(io.trigger_pkt_any[3].tdata2, 31, 31) @[lib.scala 104:74] + node _T_1071 = bits(lsu_match_data_3, 31, 31) @[lib.scala 104:86] + node _T_1072 = eq(_T_1070, _T_1071) @[lib.scala 104:78] + node _T_1073 = mux(_T_1069, UInt<1>("h01"), _T_1072) @[lib.scala 104:23] + _T_849[31] <= _T_1073 @[lib.scala 104:17] + node _T_1074 = cat(_T_849[1], _T_849[0]) @[lib.scala 105:14] + node _T_1075 = cat(_T_849[3], _T_849[2]) @[lib.scala 105:14] + node _T_1076 = cat(_T_1075, _T_1074) @[lib.scala 105:14] + node _T_1077 = cat(_T_849[5], _T_849[4]) @[lib.scala 105:14] + node _T_1078 = cat(_T_849[7], _T_849[6]) @[lib.scala 105:14] + node _T_1079 = cat(_T_1078, _T_1077) @[lib.scala 105:14] + node _T_1080 = cat(_T_1079, _T_1076) @[lib.scala 105:14] + node _T_1081 = cat(_T_849[9], _T_849[8]) @[lib.scala 105:14] + node _T_1082 = cat(_T_849[11], _T_849[10]) @[lib.scala 105:14] + node _T_1083 = cat(_T_1082, _T_1081) @[lib.scala 105:14] + node _T_1084 = cat(_T_849[13], _T_849[12]) @[lib.scala 105:14] + node _T_1085 = cat(_T_849[15], _T_849[14]) @[lib.scala 105:14] + node _T_1086 = cat(_T_1085, _T_1084) @[lib.scala 105:14] + node _T_1087 = cat(_T_1086, _T_1083) @[lib.scala 105:14] + node _T_1088 = cat(_T_1087, _T_1080) @[lib.scala 105:14] + node _T_1089 = cat(_T_849[17], _T_849[16]) @[lib.scala 105:14] + node _T_1090 = cat(_T_849[19], _T_849[18]) @[lib.scala 105:14] + node _T_1091 = cat(_T_1090, _T_1089) @[lib.scala 105:14] + node _T_1092 = cat(_T_849[21], _T_849[20]) @[lib.scala 105:14] + node _T_1093 = cat(_T_849[23], _T_849[22]) @[lib.scala 105:14] + node _T_1094 = cat(_T_1093, _T_1092) @[lib.scala 105:14] + node _T_1095 = cat(_T_1094, _T_1091) @[lib.scala 105:14] + node _T_1096 = cat(_T_849[25], _T_849[24]) @[lib.scala 105:14] + node _T_1097 = cat(_T_849[27], _T_849[26]) @[lib.scala 105:14] + node _T_1098 = cat(_T_1097, _T_1096) @[lib.scala 105:14] + node _T_1099 = cat(_T_849[29], _T_849[28]) @[lib.scala 105:14] + node _T_1100 = cat(_T_849[31], _T_849[30]) @[lib.scala 105:14] + node _T_1101 = cat(_T_1100, _T_1099) @[lib.scala 105:14] + node _T_1102 = cat(_T_1101, _T_1098) @[lib.scala 105:14] + node _T_1103 = cat(_T_1102, _T_1095) @[lib.scala 105:14] + node _T_1104 = cat(_T_1103, _T_1088) @[lib.scala 105:14] + node _T_1105 = andr(_T_1104) @[lib.scala 105:25] + node _T_1106 = and(_T_847, _T_1105) @[lsu_trigger.scala 19:92] + node _T_1107 = cat(_T_1106, _T_839) @[Cat.scala 29:58] + node _T_1108 = cat(_T_1107, _T_572) @[Cat.scala 29:58] + node _T_1109 = cat(_T_1108, _T_305) @[Cat.scala 29:58] + io.lsu_trigger_match_m <= _T_1109 @[lsu_trigger.scala 18:26] + + extmodule gated_latch_12 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_12 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_12 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_13 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_13 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_13 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_14 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_14 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_14 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_15 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_15 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_15 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_16 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_16 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_16 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_17 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_17 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_17 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_18 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_18 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_18 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_19 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_19 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_19 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_20 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_20 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_20 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_21 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_21 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_21 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_22 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_22 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_22 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_23 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_23 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_23 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + module lsu_clkdomain : + input clock : Clock + input reset : AsyncReset + output io : {flip free_clk : Clock, flip clk_override : UInt<1>, flip addr_in_dccm_m : UInt<1>, flip dma_dccm_req : UInt<1>, flip ldst_stbuf_reqvld_r : UInt<1>, flip stbuf_reqvld_any : UInt<1>, flip stbuf_reqvld_flushed_any : UInt<1>, flip lsu_busreq_r : UInt<1>, flip lsu_bus_buffer_pend_any : UInt<1>, flip lsu_bus_buffer_empty_any : UInt<1>, flip lsu_stbuf_empty_any : UInt<1>, flip lsu_bus_clk_en : UInt<1>, flip lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_c1_m_clk : Clock, lsu_c1_r_clk : Clock, lsu_c2_m_clk : Clock, lsu_c2_r_clk : Clock, lsu_store_c1_m_clk : Clock, lsu_store_c1_r_clk : Clock, lsu_stbuf_c1_clk : Clock, lsu_bus_obuf_c1_clk : Clock, lsu_bus_ibuf_c1_clk : Clock, lsu_bus_buf_c1_clk : Clock, lsu_busm_clk : Clock, lsu_free_c2_clk : Clock, flip scan_mode : UInt<1>} + + wire lsu_c1_d_clken_q : UInt<1> @[lsu_clkdomain.scala 57:36] + wire lsu_c1_m_clken_q : UInt<1> @[lsu_clkdomain.scala 58:36] + wire lsu_c1_r_clken_q : UInt<1> @[lsu_clkdomain.scala 59:36] + wire lsu_free_c1_clken_q : UInt<1> @[lsu_clkdomain.scala 60:36] + node _T = or(io.lsu_p.valid, io.dma_dccm_req) @[lsu_clkdomain.scala 62:51] + node lsu_c1_d_clken = or(_T, io.clk_override) @[lsu_clkdomain.scala 62:70] + node _T_1 = or(io.lsu_pkt_d.valid, lsu_c1_d_clken_q) @[lsu_clkdomain.scala 63:51] + node lsu_c1_m_clken = or(_T_1, io.clk_override) @[lsu_clkdomain.scala 63:70] + node _T_2 = or(io.lsu_pkt_m.valid, lsu_c1_m_clken_q) @[lsu_clkdomain.scala 64:51] + node lsu_c1_r_clken = or(_T_2, io.clk_override) @[lsu_clkdomain.scala 64:70] + node _T_3 = or(lsu_c1_m_clken, lsu_c1_m_clken_q) @[lsu_clkdomain.scala 66:47] + node lsu_c2_m_clken = or(_T_3, io.clk_override) @[lsu_clkdomain.scala 66:66] + node _T_4 = or(lsu_c1_r_clken, lsu_c1_r_clken_q) @[lsu_clkdomain.scala 67:47] + node lsu_c2_r_clken = or(_T_4, io.clk_override) @[lsu_clkdomain.scala 67:66] + node _T_5 = and(lsu_c1_m_clken, io.lsu_pkt_d.bits.store) @[lsu_clkdomain.scala 69:49] + node lsu_store_c1_m_clken = or(_T_5, io.clk_override) @[lsu_clkdomain.scala 69:76] + node _T_6 = and(lsu_c1_r_clken, io.lsu_pkt_m.bits.store) @[lsu_clkdomain.scala 70:49] + node lsu_store_c1_r_clken = or(_T_6, io.clk_override) @[lsu_clkdomain.scala 70:76] + node _T_7 = or(io.ldst_stbuf_reqvld_r, io.stbuf_reqvld_any) @[lsu_clkdomain.scala 71:55] + node _T_8 = or(_T_7, io.stbuf_reqvld_flushed_any) @[lsu_clkdomain.scala 71:77] + node lsu_stbuf_c1_clken = or(_T_8, io.clk_override) @[lsu_clkdomain.scala 71:107] + node lsu_bus_ibuf_c1_clken = or(io.lsu_busreq_r, io.clk_override) @[lsu_clkdomain.scala 72:49] + node _T_9 = or(io.lsu_bus_buffer_pend_any, io.lsu_busreq_r) @[lsu_clkdomain.scala 73:61] + node _T_10 = or(_T_9, io.clk_override) @[lsu_clkdomain.scala 73:79] + node lsu_bus_obuf_c1_clken = and(_T_10, io.lsu_bus_clk_en) @[lsu_clkdomain.scala 73:98] + node _T_11 = eq(io.lsu_bus_buffer_empty_any, UInt<1>("h00")) @[lsu_clkdomain.scala 74:32] + node _T_12 = or(_T_11, io.lsu_busreq_r) @[lsu_clkdomain.scala 74:61] + node lsu_bus_buf_c1_clken = or(_T_12, io.clk_override) @[lsu_clkdomain.scala 74:79] + node _T_13 = or(io.lsu_p.valid, io.lsu_pkt_d.valid) @[lsu_clkdomain.scala 76:48] + node _T_14 = or(_T_13, io.lsu_pkt_m.valid) @[lsu_clkdomain.scala 76:69] + node _T_15 = or(_T_14, io.lsu_pkt_r.valid) @[lsu_clkdomain.scala 76:90] + node _T_16 = eq(io.lsu_bus_buffer_empty_any, UInt<1>("h00")) @[lsu_clkdomain.scala 76:114] + node _T_17 = or(_T_15, _T_16) @[lsu_clkdomain.scala 76:112] + node _T_18 = eq(io.lsu_stbuf_empty_any, UInt<1>("h00")) @[lsu_clkdomain.scala 76:145] + node _T_19 = or(_T_17, _T_18) @[lsu_clkdomain.scala 76:143] + node lsu_free_c1_clken = or(_T_19, io.clk_override) @[lsu_clkdomain.scala 76:169] + node _T_20 = or(lsu_free_c1_clken, lsu_free_c1_clken_q) @[lsu_clkdomain.scala 77:50] + node lsu_free_c2_clken = or(_T_20, io.clk_override) @[lsu_clkdomain.scala 77:72] + reg _T_21 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_clkdomain.scala 80:60] + _T_21 <= lsu_free_c1_clken @[lsu_clkdomain.scala 80:60] + lsu_free_c1_clken_q <= _T_21 @[lsu_clkdomain.scala 80:26] + reg _T_22 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_clkdomain.scala 81:67] + _T_22 <= lsu_c1_d_clken @[lsu_clkdomain.scala 81:67] + lsu_c1_d_clken_q <= _T_22 @[lsu_clkdomain.scala 81:26] + reg _T_23 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_clkdomain.scala 82:67] + _T_23 <= lsu_c1_m_clken @[lsu_clkdomain.scala 82:67] + lsu_c1_m_clken_q <= _T_23 @[lsu_clkdomain.scala 82:26] + reg _T_24 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_clkdomain.scala 83:67] + _T_24 <= lsu_c1_r_clken @[lsu_clkdomain.scala 83:67] + lsu_c1_r_clken_q <= _T_24 @[lsu_clkdomain.scala 83:26] + node _T_25 = bits(lsu_c1_m_clken, 0, 0) @[lsu_clkdomain.scala 85:59] + inst rvclkhdr of rvclkhdr_12 @[lib.scala 343:22] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[lib.scala 344:17] + rvclkhdr.io.en <= _T_25 @[lib.scala 345:16] + rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + io.lsu_c1_m_clk <= rvclkhdr.io.l1clk @[lsu_clkdomain.scala 85:26] + node _T_26 = bits(lsu_c1_r_clken, 0, 0) @[lsu_clkdomain.scala 86:59] + inst rvclkhdr_1 of rvclkhdr_13 @[lib.scala 343:22] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_1.io.en <= _T_26 @[lib.scala 345:16] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + io.lsu_c1_r_clk <= rvclkhdr_1.io.l1clk @[lsu_clkdomain.scala 86:26] + node _T_27 = bits(lsu_c2_m_clken, 0, 0) @[lsu_clkdomain.scala 87:59] + inst rvclkhdr_2 of rvclkhdr_14 @[lib.scala 343:22] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_2.io.en <= _T_27 @[lib.scala 345:16] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + io.lsu_c2_m_clk <= rvclkhdr_2.io.l1clk @[lsu_clkdomain.scala 87:26] + node _T_28 = bits(lsu_c2_r_clken, 0, 0) @[lsu_clkdomain.scala 88:59] + inst rvclkhdr_3 of rvclkhdr_15 @[lib.scala 343:22] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_3.io.en <= _T_28 @[lib.scala 345:16] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + io.lsu_c2_r_clk <= rvclkhdr_3.io.l1clk @[lsu_clkdomain.scala 88:26] + node _T_29 = bits(lsu_store_c1_m_clken, 0, 0) @[lsu_clkdomain.scala 89:65] + inst rvclkhdr_4 of rvclkhdr_16 @[lib.scala 343:22] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= reset + rvclkhdr_4.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_4.io.en <= _T_29 @[lib.scala 345:16] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + io.lsu_store_c1_m_clk <= rvclkhdr_4.io.l1clk @[lsu_clkdomain.scala 89:26] + node _T_30 = bits(lsu_store_c1_r_clken, 0, 0) @[lsu_clkdomain.scala 90:65] + inst rvclkhdr_5 of rvclkhdr_17 @[lib.scala 343:22] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= reset + rvclkhdr_5.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_5.io.en <= _T_30 @[lib.scala 345:16] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + io.lsu_store_c1_r_clk <= rvclkhdr_5.io.l1clk @[lsu_clkdomain.scala 90:26] + node _T_31 = bits(lsu_stbuf_c1_clken, 0, 0) @[lsu_clkdomain.scala 91:63] + inst rvclkhdr_6 of rvclkhdr_18 @[lib.scala 343:22] + rvclkhdr_6.clock <= clock + rvclkhdr_6.reset <= reset + rvclkhdr_6.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_6.io.en <= _T_31 @[lib.scala 345:16] + rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + io.lsu_stbuf_c1_clk <= rvclkhdr_6.io.l1clk @[lsu_clkdomain.scala 91:26] + node _T_32 = bits(lsu_bus_ibuf_c1_clken, 0, 0) @[lsu_clkdomain.scala 92:66] + inst rvclkhdr_7 of rvclkhdr_19 @[lib.scala 343:22] + rvclkhdr_7.clock <= clock + rvclkhdr_7.reset <= reset + rvclkhdr_7.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_7.io.en <= _T_32 @[lib.scala 345:16] + rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + io.lsu_bus_ibuf_c1_clk <= rvclkhdr_7.io.l1clk @[lsu_clkdomain.scala 92:26] + node _T_33 = bits(lsu_bus_obuf_c1_clken, 0, 0) @[lsu_clkdomain.scala 93:66] + inst rvclkhdr_8 of rvclkhdr_20 @[lib.scala 343:22] + rvclkhdr_8.clock <= clock + rvclkhdr_8.reset <= reset + rvclkhdr_8.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_8.io.en <= _T_33 @[lib.scala 345:16] + rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + io.lsu_bus_obuf_c1_clk <= rvclkhdr_8.io.l1clk @[lsu_clkdomain.scala 93:26] + node _T_34 = bits(lsu_bus_buf_c1_clken, 0, 0) @[lsu_clkdomain.scala 94:65] + inst rvclkhdr_9 of rvclkhdr_21 @[lib.scala 343:22] + rvclkhdr_9.clock <= clock + rvclkhdr_9.reset <= reset + rvclkhdr_9.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_9.io.en <= _T_34 @[lib.scala 345:16] + rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + io.lsu_bus_buf_c1_clk <= rvclkhdr_9.io.l1clk @[lsu_clkdomain.scala 94:26] + node _T_35 = bits(io.lsu_bus_clk_en, 0, 0) @[lsu_clkdomain.scala 95:62] + inst rvclkhdr_10 of rvclkhdr_22 @[lib.scala 343:22] + rvclkhdr_10.clock <= clock + rvclkhdr_10.reset <= reset + rvclkhdr_10.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_10.io.en <= _T_35 @[lib.scala 345:16] + rvclkhdr_10.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + io.lsu_busm_clk <= rvclkhdr_10.io.l1clk @[lsu_clkdomain.scala 95:26] + node _T_36 = bits(lsu_free_c2_clken, 0, 0) @[lsu_clkdomain.scala 96:62] + inst rvclkhdr_11 of rvclkhdr_23 @[lib.scala 343:22] + rvclkhdr_11.clock <= clock + rvclkhdr_11.reset <= reset + rvclkhdr_11.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_11.io.en <= _T_36 @[lib.scala 345:16] + rvclkhdr_11.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + io.lsu_free_c2_clk <= rvclkhdr_11.io.l1clk @[lsu_clkdomain.scala 96:26] + + extmodule gated_latch_24 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_24 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_24 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_25 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_25 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_25 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_26 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_26 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_26 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_27 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_27 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_27 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_28 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_28 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_28 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_29 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_29 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_29 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_30 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_30 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_30 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_31 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_31 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_31 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_32 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_32 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_32 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_33 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_33 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_33 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_34 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_34 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_34 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_35 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_35 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_35 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + module lsu_bus_buffer : + input clock : Clock + input reset : AsyncReset + output io : {flip scan_mode : UInt<1>, tlu_busbuff : {lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>}, dctl_busbuff : {lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>}, flip dec_tlu_force_halt : UInt<1>, flip lsu_c2_r_clk : Clock, flip lsu_bus_ibuf_c1_clk : Clock, flip lsu_bus_obuf_c1_clk : Clock, flip lsu_bus_buf_c1_clk : Clock, flip lsu_free_c2_clk : Clock, flip lsu_busm_clk : Clock, flip dec_lsu_valid_raw_d : UInt<1>, flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_addr_m : UInt<32>, flip end_addr_m : UInt<32>, flip lsu_addr_r : UInt<32>, flip end_addr_r : UInt<32>, flip store_data_r : UInt<32>, flip no_word_merge_r : UInt<1>, flip no_dword_merge_r : UInt<1>, flip lsu_busreq_m : UInt<1>, flip ld_full_hit_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, flip lsu_commit_r : UInt<1>, flip is_sideeffects_r : UInt<1>, flip ldst_dual_d : UInt<1>, flip ldst_dual_m : UInt<1>, flip ldst_dual_r : UInt<1>, flip ldst_byteen_ext_m : UInt<8>, lsu_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip lsu_bus_clk_en : UInt<1>, flip lsu_bus_clk_en_q : UInt<1>, lsu_busreq_r : UInt<1>, lsu_bus_buffer_pend_any : UInt<1>, lsu_bus_buffer_full_any : UInt<1>, lsu_bus_buffer_empty_any : UInt<1>, lsu_bus_idle_any : UInt<1>, ld_byte_hit_buf_lo : UInt<4>, ld_byte_hit_buf_hi : UInt<4>, ld_fwddata_buf_lo : UInt<32>, ld_fwddata_buf_hi : UInt<32>} + + wire buf_addr : UInt<32>[4] @[lsu_bus_buffer.scala 67:22] + wire buf_state : UInt<3>[4] @[lsu_bus_buffer.scala 68:23] + wire buf_write : UInt<4> + buf_write <= UInt<1>("h00") + wire CmdPtr0 : UInt<2> + CmdPtr0 <= UInt<1>("h00") + node ldst_byteen_hi_m = bits(io.ldst_byteen_ext_m, 7, 4) @[lsu_bus_buffer.scala 73:46] + node ldst_byteen_lo_m = bits(io.ldst_byteen_ext_m, 3, 0) @[lsu_bus_buffer.scala 74:46] + node _T = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 76:66] + node _T_1 = bits(buf_addr[0], 31, 2) @[lsu_bus_buffer.scala 76:89] + node _T_2 = eq(_T, _T_1) @[lsu_bus_buffer.scala 76:74] + node _T_3 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 76:109] + node _T_4 = and(_T_2, _T_3) @[lsu_bus_buffer.scala 76:98] + node _T_5 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 76:129] + node _T_6 = and(_T_4, _T_5) @[lsu_bus_buffer.scala 76:113] + node ld_addr_hitvec_lo_0 = and(_T_6, io.lsu_busreq_m) @[lsu_bus_buffer.scala 76:141] + node _T_7 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 76:66] + node _T_8 = bits(buf_addr[1], 31, 2) @[lsu_bus_buffer.scala 76:89] + node _T_9 = eq(_T_7, _T_8) @[lsu_bus_buffer.scala 76:74] + node _T_10 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 76:109] + node _T_11 = and(_T_9, _T_10) @[lsu_bus_buffer.scala 76:98] + node _T_12 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 76:129] + node _T_13 = and(_T_11, _T_12) @[lsu_bus_buffer.scala 76:113] + node ld_addr_hitvec_lo_1 = and(_T_13, io.lsu_busreq_m) @[lsu_bus_buffer.scala 76:141] + node _T_14 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 76:66] + node _T_15 = bits(buf_addr[2], 31, 2) @[lsu_bus_buffer.scala 76:89] + node _T_16 = eq(_T_14, _T_15) @[lsu_bus_buffer.scala 76:74] + node _T_17 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 76:109] + node _T_18 = and(_T_16, _T_17) @[lsu_bus_buffer.scala 76:98] + node _T_19 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 76:129] + node _T_20 = and(_T_18, _T_19) @[lsu_bus_buffer.scala 76:113] + node ld_addr_hitvec_lo_2 = and(_T_20, io.lsu_busreq_m) @[lsu_bus_buffer.scala 76:141] + node _T_21 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 76:66] + node _T_22 = bits(buf_addr[3], 31, 2) @[lsu_bus_buffer.scala 76:89] + node _T_23 = eq(_T_21, _T_22) @[lsu_bus_buffer.scala 76:74] + node _T_24 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 76:109] + node _T_25 = and(_T_23, _T_24) @[lsu_bus_buffer.scala 76:98] + node _T_26 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 76:129] + node _T_27 = and(_T_25, _T_26) @[lsu_bus_buffer.scala 76:113] + node ld_addr_hitvec_lo_3 = and(_T_27, io.lsu_busreq_m) @[lsu_bus_buffer.scala 76:141] + node _T_28 = bits(io.end_addr_m, 31, 2) @[lsu_bus_buffer.scala 77:66] + node _T_29 = bits(buf_addr[0], 31, 2) @[lsu_bus_buffer.scala 77:89] + node _T_30 = eq(_T_28, _T_29) @[lsu_bus_buffer.scala 77:74] + node _T_31 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 77:109] + node _T_32 = and(_T_30, _T_31) @[lsu_bus_buffer.scala 77:98] + node _T_33 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 77:129] + node _T_34 = and(_T_32, _T_33) @[lsu_bus_buffer.scala 77:113] + node ld_addr_hitvec_hi_0 = and(_T_34, io.lsu_busreq_m) @[lsu_bus_buffer.scala 77:141] + node _T_35 = bits(io.end_addr_m, 31, 2) @[lsu_bus_buffer.scala 77:66] + node _T_36 = bits(buf_addr[1], 31, 2) @[lsu_bus_buffer.scala 77:89] + node _T_37 = eq(_T_35, _T_36) @[lsu_bus_buffer.scala 77:74] + node _T_38 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 77:109] + node _T_39 = and(_T_37, _T_38) @[lsu_bus_buffer.scala 77:98] + node _T_40 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 77:129] + node _T_41 = and(_T_39, _T_40) @[lsu_bus_buffer.scala 77:113] + node ld_addr_hitvec_hi_1 = and(_T_41, io.lsu_busreq_m) @[lsu_bus_buffer.scala 77:141] + node _T_42 = bits(io.end_addr_m, 31, 2) @[lsu_bus_buffer.scala 77:66] + node _T_43 = bits(buf_addr[2], 31, 2) @[lsu_bus_buffer.scala 77:89] + node _T_44 = eq(_T_42, _T_43) @[lsu_bus_buffer.scala 77:74] + node _T_45 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 77:109] + node _T_46 = and(_T_44, _T_45) @[lsu_bus_buffer.scala 77:98] + node _T_47 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 77:129] + node _T_48 = and(_T_46, _T_47) @[lsu_bus_buffer.scala 77:113] + node ld_addr_hitvec_hi_2 = and(_T_48, io.lsu_busreq_m) @[lsu_bus_buffer.scala 77:141] + node _T_49 = bits(io.end_addr_m, 31, 2) @[lsu_bus_buffer.scala 77:66] + node _T_50 = bits(buf_addr[3], 31, 2) @[lsu_bus_buffer.scala 77:89] + node _T_51 = eq(_T_49, _T_50) @[lsu_bus_buffer.scala 77:74] + node _T_52 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 77:109] + node _T_53 = and(_T_51, _T_52) @[lsu_bus_buffer.scala 77:98] + node _T_54 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 77:129] + node _T_55 = and(_T_53, _T_54) @[lsu_bus_buffer.scala 77:113] + node ld_addr_hitvec_hi_3 = and(_T_55, io.lsu_busreq_m) @[lsu_bus_buffer.scala 77:141] + wire ld_byte_hitvecfn_lo : UInt<4>[4] @[lsu_bus_buffer.scala 78:33] + wire ld_byte_ibuf_hit_lo : UInt<4> + ld_byte_ibuf_hit_lo <= UInt<1>("h00") + wire ld_byte_hitvecfn_hi : UInt<4>[4] @[lsu_bus_buffer.scala 80:33] + wire ld_byte_ibuf_hit_hi : UInt<4> + ld_byte_ibuf_hit_hi <= UInt<1>("h00") + wire buf_byteen : UInt<4>[4] @[lsu_bus_buffer.scala 82:24] + buf_byteen[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 83:14] + buf_byteen[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 83:14] + buf_byteen[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 83:14] + buf_byteen[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 83:14] + wire buf_nxtstate : UInt<3>[4] @[lsu_bus_buffer.scala 84:26] + buf_nxtstate[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 85:16] + buf_nxtstate[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 85:16] + buf_nxtstate[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 85:16] + buf_nxtstate[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 85:16] + wire buf_wr_en : UInt<1>[4] @[lsu_bus_buffer.scala 86:23] + buf_wr_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 87:13] + buf_wr_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 87:13] + buf_wr_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 87:13] + buf_wr_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 87:13] + wire buf_data_en : UInt<1>[4] @[lsu_bus_buffer.scala 88:25] + buf_data_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 89:15] + buf_data_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 89:15] + buf_data_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 89:15] + buf_data_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 89:15] + wire buf_state_bus_en : UInt<1>[4] @[lsu_bus_buffer.scala 90:30] + buf_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 91:20] + buf_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 91:20] + buf_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 91:20] + buf_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 91:20] + wire buf_ldfwd_in : UInt<1>[4] @[lsu_bus_buffer.scala 92:26] + buf_ldfwd_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 93:16] + buf_ldfwd_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 93:16] + buf_ldfwd_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 93:16] + buf_ldfwd_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 93:16] + wire buf_ldfwd_en : UInt<1>[4] @[lsu_bus_buffer.scala 94:26] + buf_ldfwd_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 95:16] + buf_ldfwd_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 95:16] + buf_ldfwd_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 95:16] + buf_ldfwd_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 95:16] + wire buf_data_in : UInt<32>[4] @[lsu_bus_buffer.scala 96:25] + buf_data_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 97:15] + buf_data_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 97:15] + buf_data_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 97:15] + buf_data_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 97:15] + wire buf_ldfwdtag_in : UInt<2>[4] @[lsu_bus_buffer.scala 98:29] + buf_ldfwdtag_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 99:19] + buf_ldfwdtag_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 99:19] + buf_ldfwdtag_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 99:19] + buf_ldfwdtag_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 99:19] + wire buf_error_en : UInt<1>[4] @[lsu_bus_buffer.scala 100:26] + buf_error_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 101:16] + buf_error_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 101:16] + buf_error_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 101:16] + buf_error_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 101:16] + wire bus_rsp_read_error : UInt<1> + bus_rsp_read_error <= UInt<1>("h00") + wire bus_rsp_rdata : UInt<64> + bus_rsp_rdata <= UInt<1>("h00") + wire bus_rsp_write_error : UInt<1> + bus_rsp_write_error <= UInt<1>("h00") + wire buf_dualtag : UInt<2>[4] @[lsu_bus_buffer.scala 105:25] + buf_dualtag[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 106:15] + buf_dualtag[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 106:15] + buf_dualtag[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 106:15] + buf_dualtag[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 106:15] + wire buf_ldfwd : UInt<4> + buf_ldfwd <= UInt<1>("h00") + wire buf_resp_state_bus_en : UInt<1>[4] @[lsu_bus_buffer.scala 108:35] + buf_resp_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 109:25] + buf_resp_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 109:25] + buf_resp_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 109:25] + buf_resp_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 109:25] + wire any_done_wait_state : UInt<1> + any_done_wait_state <= UInt<1>("h00") + wire bus_rsp_write : UInt<1> + bus_rsp_write <= UInt<1>("h00") + wire bus_rsp_write_tag : UInt<3> + bus_rsp_write_tag <= UInt<1>("h00") + wire buf_ldfwdtag : UInt<2>[4] @[lsu_bus_buffer.scala 113:26] + buf_ldfwdtag[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 114:16] + buf_ldfwdtag[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 114:16] + buf_ldfwdtag[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 114:16] + buf_ldfwdtag[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 114:16] + wire buf_rst : UInt<1>[4] @[lsu_bus_buffer.scala 115:21] + buf_rst[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 116:11] + buf_rst[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 116:11] + buf_rst[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 116:11] + buf_rst[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 116:11] + wire ibuf_drainvec_vld : UInt<4> + ibuf_drainvec_vld <= UInt<1>("h00") + wire buf_byteen_in : UInt<4>[4] @[lsu_bus_buffer.scala 118:27] + buf_byteen_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 119:17] + buf_byteen_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 119:17] + buf_byteen_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 119:17] + buf_byteen_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 119:17] + wire buf_addr_in : UInt<32>[4] @[lsu_bus_buffer.scala 120:25] + buf_addr_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 121:15] + buf_addr_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 121:15] + buf_addr_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 121:15] + buf_addr_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 121:15] + wire buf_dual_in : UInt<4> + buf_dual_in <= UInt<1>("h00") + wire buf_samedw_in : UInt<4> + buf_samedw_in <= UInt<1>("h00") + wire buf_nomerge_in : UInt<4> + buf_nomerge_in <= UInt<1>("h00") + wire buf_dualhi_in : UInt<4> + buf_dualhi_in <= UInt<1>("h00") + wire buf_dualtag_in : UInt<2>[4] @[lsu_bus_buffer.scala 126:28] + buf_dualtag_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 127:18] + buf_dualtag_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 127:18] + buf_dualtag_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 127:18] + buf_dualtag_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 127:18] + wire buf_sideeffect_in : UInt<4> + buf_sideeffect_in <= UInt<1>("h00") + wire buf_unsign_in : UInt<4> + buf_unsign_in <= UInt<1>("h00") + wire buf_sz_in : UInt<2>[4] @[lsu_bus_buffer.scala 130:23] + buf_sz_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 131:13] + buf_sz_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 131:13] + buf_sz_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 131:13] + buf_sz_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 131:13] + wire buf_write_in : UInt<4> + buf_write_in <= UInt<1>("h00") + wire buf_unsign : UInt<4> + buf_unsign <= UInt<1>("h00") + wire buf_error : UInt<4> + buf_error <= UInt<1>("h00") + wire CmdPtr1 : UInt<2> + CmdPtr1 <= UInt<1>("h00") + wire ibuf_data : UInt<32> + ibuf_data <= UInt<1>("h00") + node _T_56 = orr(ld_byte_hitvecfn_lo[0]) @[lsu_bus_buffer.scala 138:73] + node _T_57 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[lsu_bus_buffer.scala 138:98] + node _T_58 = or(_T_56, _T_57) @[lsu_bus_buffer.scala 138:77] + node _T_59 = orr(ld_byte_hitvecfn_lo[1]) @[lsu_bus_buffer.scala 138:73] + node _T_60 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[lsu_bus_buffer.scala 138:98] + node _T_61 = or(_T_59, _T_60) @[lsu_bus_buffer.scala 138:77] + node _T_62 = orr(ld_byte_hitvecfn_lo[2]) @[lsu_bus_buffer.scala 138:73] + node _T_63 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[lsu_bus_buffer.scala 138:98] + node _T_64 = or(_T_62, _T_63) @[lsu_bus_buffer.scala 138:77] + node _T_65 = orr(ld_byte_hitvecfn_lo[3]) @[lsu_bus_buffer.scala 138:73] + node _T_66 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[lsu_bus_buffer.scala 138:98] + node _T_67 = or(_T_65, _T_66) @[lsu_bus_buffer.scala 138:77] + node _T_68 = cat(_T_67, _T_64) @[Cat.scala 29:58] + node _T_69 = cat(_T_68, _T_61) @[Cat.scala 29:58] + node _T_70 = cat(_T_69, _T_58) @[Cat.scala 29:58] + io.ld_byte_hit_buf_lo <= _T_70 @[lsu_bus_buffer.scala 138:25] + node _T_71 = orr(ld_byte_hitvecfn_hi[0]) @[lsu_bus_buffer.scala 139:73] + node _T_72 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[lsu_bus_buffer.scala 139:98] + node _T_73 = or(_T_71, _T_72) @[lsu_bus_buffer.scala 139:77] + node _T_74 = orr(ld_byte_hitvecfn_hi[1]) @[lsu_bus_buffer.scala 139:73] + node _T_75 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[lsu_bus_buffer.scala 139:98] + node _T_76 = or(_T_74, _T_75) @[lsu_bus_buffer.scala 139:77] + node _T_77 = orr(ld_byte_hitvecfn_hi[2]) @[lsu_bus_buffer.scala 139:73] + node _T_78 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[lsu_bus_buffer.scala 139:98] + node _T_79 = or(_T_77, _T_78) @[lsu_bus_buffer.scala 139:77] + node _T_80 = orr(ld_byte_hitvecfn_hi[3]) @[lsu_bus_buffer.scala 139:73] + node _T_81 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[lsu_bus_buffer.scala 139:98] + node _T_82 = or(_T_80, _T_81) @[lsu_bus_buffer.scala 139:77] + node _T_83 = cat(_T_82, _T_79) @[Cat.scala 29:58] + node _T_84 = cat(_T_83, _T_76) @[Cat.scala 29:58] + node _T_85 = cat(_T_84, _T_73) @[Cat.scala 29:58] + io.ld_byte_hit_buf_hi <= _T_85 @[lsu_bus_buffer.scala 139:25] + node _T_86 = bits(buf_byteen[0], 0, 0) @[lsu_bus_buffer.scala 141:110] + node _T_87 = and(ld_addr_hitvec_lo_0, _T_86) @[lsu_bus_buffer.scala 141:95] + node _T_88 = bits(ldst_byteen_lo_m, 0, 0) @[lsu_bus_buffer.scala 141:132] + node _T_89 = and(_T_87, _T_88) @[lsu_bus_buffer.scala 141:114] + node _T_90 = bits(buf_byteen[1], 0, 0) @[lsu_bus_buffer.scala 141:110] + node _T_91 = and(ld_addr_hitvec_lo_1, _T_90) @[lsu_bus_buffer.scala 141:95] + node _T_92 = bits(ldst_byteen_lo_m, 0, 0) @[lsu_bus_buffer.scala 141:132] + node _T_93 = and(_T_91, _T_92) @[lsu_bus_buffer.scala 141:114] + node _T_94 = bits(buf_byteen[2], 0, 0) @[lsu_bus_buffer.scala 141:110] + node _T_95 = and(ld_addr_hitvec_lo_2, _T_94) @[lsu_bus_buffer.scala 141:95] + node _T_96 = bits(ldst_byteen_lo_m, 0, 0) @[lsu_bus_buffer.scala 141:132] + node _T_97 = and(_T_95, _T_96) @[lsu_bus_buffer.scala 141:114] + node _T_98 = bits(buf_byteen[3], 0, 0) @[lsu_bus_buffer.scala 141:110] + node _T_99 = and(ld_addr_hitvec_lo_3, _T_98) @[lsu_bus_buffer.scala 141:95] + node _T_100 = bits(ldst_byteen_lo_m, 0, 0) @[lsu_bus_buffer.scala 141:132] + node _T_101 = and(_T_99, _T_100) @[lsu_bus_buffer.scala 141:114] + node _T_102 = cat(_T_101, _T_97) @[Cat.scala 29:58] + node _T_103 = cat(_T_102, _T_93) @[Cat.scala 29:58] + node ld_byte_hitvec_lo_0 = cat(_T_103, _T_89) @[Cat.scala 29:58] + node _T_104 = bits(buf_byteen[0], 1, 1) @[lsu_bus_buffer.scala 141:110] + node _T_105 = and(ld_addr_hitvec_lo_0, _T_104) @[lsu_bus_buffer.scala 141:95] + node _T_106 = bits(ldst_byteen_lo_m, 1, 1) @[lsu_bus_buffer.scala 141:132] + node _T_107 = and(_T_105, _T_106) @[lsu_bus_buffer.scala 141:114] + node _T_108 = bits(buf_byteen[1], 1, 1) @[lsu_bus_buffer.scala 141:110] + node _T_109 = and(ld_addr_hitvec_lo_1, _T_108) @[lsu_bus_buffer.scala 141:95] + node _T_110 = bits(ldst_byteen_lo_m, 1, 1) @[lsu_bus_buffer.scala 141:132] + node _T_111 = and(_T_109, _T_110) @[lsu_bus_buffer.scala 141:114] + node _T_112 = bits(buf_byteen[2], 1, 1) @[lsu_bus_buffer.scala 141:110] + node _T_113 = and(ld_addr_hitvec_lo_2, _T_112) @[lsu_bus_buffer.scala 141:95] + node _T_114 = bits(ldst_byteen_lo_m, 1, 1) @[lsu_bus_buffer.scala 141:132] + node _T_115 = and(_T_113, _T_114) @[lsu_bus_buffer.scala 141:114] + node _T_116 = bits(buf_byteen[3], 1, 1) @[lsu_bus_buffer.scala 141:110] + node _T_117 = and(ld_addr_hitvec_lo_3, _T_116) @[lsu_bus_buffer.scala 141:95] + node _T_118 = bits(ldst_byteen_lo_m, 1, 1) @[lsu_bus_buffer.scala 141:132] + node _T_119 = and(_T_117, _T_118) @[lsu_bus_buffer.scala 141:114] + node _T_120 = cat(_T_119, _T_115) @[Cat.scala 29:58] + node _T_121 = cat(_T_120, _T_111) @[Cat.scala 29:58] + node ld_byte_hitvec_lo_1 = cat(_T_121, _T_107) @[Cat.scala 29:58] + node _T_122 = bits(buf_byteen[0], 2, 2) @[lsu_bus_buffer.scala 141:110] + node _T_123 = and(ld_addr_hitvec_lo_0, _T_122) @[lsu_bus_buffer.scala 141:95] + node _T_124 = bits(ldst_byteen_lo_m, 2, 2) @[lsu_bus_buffer.scala 141:132] + node _T_125 = and(_T_123, _T_124) @[lsu_bus_buffer.scala 141:114] + node _T_126 = bits(buf_byteen[1], 2, 2) @[lsu_bus_buffer.scala 141:110] + node _T_127 = and(ld_addr_hitvec_lo_1, _T_126) @[lsu_bus_buffer.scala 141:95] + node _T_128 = bits(ldst_byteen_lo_m, 2, 2) @[lsu_bus_buffer.scala 141:132] + node _T_129 = and(_T_127, _T_128) @[lsu_bus_buffer.scala 141:114] + node _T_130 = bits(buf_byteen[2], 2, 2) @[lsu_bus_buffer.scala 141:110] + node _T_131 = and(ld_addr_hitvec_lo_2, _T_130) @[lsu_bus_buffer.scala 141:95] + node _T_132 = bits(ldst_byteen_lo_m, 2, 2) @[lsu_bus_buffer.scala 141:132] + node _T_133 = and(_T_131, _T_132) @[lsu_bus_buffer.scala 141:114] + node _T_134 = bits(buf_byteen[3], 2, 2) @[lsu_bus_buffer.scala 141:110] + node _T_135 = and(ld_addr_hitvec_lo_3, _T_134) @[lsu_bus_buffer.scala 141:95] + node _T_136 = bits(ldst_byteen_lo_m, 2, 2) @[lsu_bus_buffer.scala 141:132] + node _T_137 = and(_T_135, _T_136) @[lsu_bus_buffer.scala 141:114] + node _T_138 = cat(_T_137, _T_133) @[Cat.scala 29:58] + node _T_139 = cat(_T_138, _T_129) @[Cat.scala 29:58] + node ld_byte_hitvec_lo_2 = cat(_T_139, _T_125) @[Cat.scala 29:58] + node _T_140 = bits(buf_byteen[0], 3, 3) @[lsu_bus_buffer.scala 141:110] + node _T_141 = and(ld_addr_hitvec_lo_0, _T_140) @[lsu_bus_buffer.scala 141:95] + node _T_142 = bits(ldst_byteen_lo_m, 3, 3) @[lsu_bus_buffer.scala 141:132] + node _T_143 = and(_T_141, _T_142) @[lsu_bus_buffer.scala 141:114] + node _T_144 = bits(buf_byteen[1], 3, 3) @[lsu_bus_buffer.scala 141:110] + node _T_145 = and(ld_addr_hitvec_lo_1, _T_144) @[lsu_bus_buffer.scala 141:95] + node _T_146 = bits(ldst_byteen_lo_m, 3, 3) @[lsu_bus_buffer.scala 141:132] + node _T_147 = and(_T_145, _T_146) @[lsu_bus_buffer.scala 141:114] + node _T_148 = bits(buf_byteen[2], 3, 3) @[lsu_bus_buffer.scala 141:110] + node _T_149 = and(ld_addr_hitvec_lo_2, _T_148) @[lsu_bus_buffer.scala 141:95] + node _T_150 = bits(ldst_byteen_lo_m, 3, 3) @[lsu_bus_buffer.scala 141:132] + node _T_151 = and(_T_149, _T_150) @[lsu_bus_buffer.scala 141:114] + node _T_152 = bits(buf_byteen[3], 3, 3) @[lsu_bus_buffer.scala 141:110] + node _T_153 = and(ld_addr_hitvec_lo_3, _T_152) @[lsu_bus_buffer.scala 141:95] + node _T_154 = bits(ldst_byteen_lo_m, 3, 3) @[lsu_bus_buffer.scala 141:132] + node _T_155 = and(_T_153, _T_154) @[lsu_bus_buffer.scala 141:114] + node _T_156 = cat(_T_155, _T_151) @[Cat.scala 29:58] + node _T_157 = cat(_T_156, _T_147) @[Cat.scala 29:58] + node ld_byte_hitvec_lo_3 = cat(_T_157, _T_143) @[Cat.scala 29:58] + node _T_158 = bits(buf_byteen[0], 0, 0) @[lsu_bus_buffer.scala 142:110] + node _T_159 = and(ld_addr_hitvec_hi_0, _T_158) @[lsu_bus_buffer.scala 142:95] + node _T_160 = bits(ldst_byteen_hi_m, 0, 0) @[lsu_bus_buffer.scala 142:132] + node _T_161 = and(_T_159, _T_160) @[lsu_bus_buffer.scala 142:114] + node _T_162 = bits(buf_byteen[1], 0, 0) @[lsu_bus_buffer.scala 142:110] + node _T_163 = and(ld_addr_hitvec_hi_1, _T_162) @[lsu_bus_buffer.scala 142:95] + node _T_164 = bits(ldst_byteen_hi_m, 0, 0) @[lsu_bus_buffer.scala 142:132] + node _T_165 = and(_T_163, _T_164) @[lsu_bus_buffer.scala 142:114] + node _T_166 = bits(buf_byteen[2], 0, 0) @[lsu_bus_buffer.scala 142:110] + node _T_167 = and(ld_addr_hitvec_hi_2, _T_166) @[lsu_bus_buffer.scala 142:95] + node _T_168 = bits(ldst_byteen_hi_m, 0, 0) @[lsu_bus_buffer.scala 142:132] + node _T_169 = and(_T_167, _T_168) @[lsu_bus_buffer.scala 142:114] + node _T_170 = bits(buf_byteen[3], 0, 0) @[lsu_bus_buffer.scala 142:110] + node _T_171 = and(ld_addr_hitvec_hi_3, _T_170) @[lsu_bus_buffer.scala 142:95] + node _T_172 = bits(ldst_byteen_hi_m, 0, 0) @[lsu_bus_buffer.scala 142:132] + node _T_173 = and(_T_171, _T_172) @[lsu_bus_buffer.scala 142:114] + node _T_174 = cat(_T_173, _T_169) @[Cat.scala 29:58] + node _T_175 = cat(_T_174, _T_165) @[Cat.scala 29:58] + node ld_byte_hitvec_hi_0 = cat(_T_175, _T_161) @[Cat.scala 29:58] + node _T_176 = bits(buf_byteen[0], 1, 1) @[lsu_bus_buffer.scala 142:110] + node _T_177 = and(ld_addr_hitvec_hi_0, _T_176) @[lsu_bus_buffer.scala 142:95] + node _T_178 = bits(ldst_byteen_hi_m, 1, 1) @[lsu_bus_buffer.scala 142:132] + node _T_179 = and(_T_177, _T_178) @[lsu_bus_buffer.scala 142:114] + node _T_180 = bits(buf_byteen[1], 1, 1) @[lsu_bus_buffer.scala 142:110] + node _T_181 = and(ld_addr_hitvec_hi_1, _T_180) @[lsu_bus_buffer.scala 142:95] + node _T_182 = bits(ldst_byteen_hi_m, 1, 1) @[lsu_bus_buffer.scala 142:132] + node _T_183 = and(_T_181, _T_182) @[lsu_bus_buffer.scala 142:114] + node _T_184 = bits(buf_byteen[2], 1, 1) @[lsu_bus_buffer.scala 142:110] + node _T_185 = and(ld_addr_hitvec_hi_2, _T_184) @[lsu_bus_buffer.scala 142:95] + node _T_186 = bits(ldst_byteen_hi_m, 1, 1) @[lsu_bus_buffer.scala 142:132] + node _T_187 = and(_T_185, _T_186) @[lsu_bus_buffer.scala 142:114] + node _T_188 = bits(buf_byteen[3], 1, 1) @[lsu_bus_buffer.scala 142:110] + node _T_189 = and(ld_addr_hitvec_hi_3, _T_188) @[lsu_bus_buffer.scala 142:95] + node _T_190 = bits(ldst_byteen_hi_m, 1, 1) @[lsu_bus_buffer.scala 142:132] + node _T_191 = and(_T_189, _T_190) @[lsu_bus_buffer.scala 142:114] + node _T_192 = cat(_T_191, _T_187) @[Cat.scala 29:58] + node _T_193 = cat(_T_192, _T_183) @[Cat.scala 29:58] + node ld_byte_hitvec_hi_1 = cat(_T_193, _T_179) @[Cat.scala 29:58] + node _T_194 = bits(buf_byteen[0], 2, 2) @[lsu_bus_buffer.scala 142:110] + node _T_195 = and(ld_addr_hitvec_hi_0, _T_194) @[lsu_bus_buffer.scala 142:95] + node _T_196 = bits(ldst_byteen_hi_m, 2, 2) @[lsu_bus_buffer.scala 142:132] + node _T_197 = and(_T_195, _T_196) @[lsu_bus_buffer.scala 142:114] + node _T_198 = bits(buf_byteen[1], 2, 2) @[lsu_bus_buffer.scala 142:110] + node _T_199 = and(ld_addr_hitvec_hi_1, _T_198) @[lsu_bus_buffer.scala 142:95] + node _T_200 = bits(ldst_byteen_hi_m, 2, 2) @[lsu_bus_buffer.scala 142:132] + node _T_201 = and(_T_199, _T_200) @[lsu_bus_buffer.scala 142:114] + node _T_202 = bits(buf_byteen[2], 2, 2) @[lsu_bus_buffer.scala 142:110] + node _T_203 = and(ld_addr_hitvec_hi_2, _T_202) @[lsu_bus_buffer.scala 142:95] + node _T_204 = bits(ldst_byteen_hi_m, 2, 2) @[lsu_bus_buffer.scala 142:132] + node _T_205 = and(_T_203, _T_204) @[lsu_bus_buffer.scala 142:114] + node _T_206 = bits(buf_byteen[3], 2, 2) @[lsu_bus_buffer.scala 142:110] + node _T_207 = and(ld_addr_hitvec_hi_3, _T_206) @[lsu_bus_buffer.scala 142:95] + node _T_208 = bits(ldst_byteen_hi_m, 2, 2) @[lsu_bus_buffer.scala 142:132] + node _T_209 = and(_T_207, _T_208) @[lsu_bus_buffer.scala 142:114] + node _T_210 = cat(_T_209, _T_205) @[Cat.scala 29:58] + node _T_211 = cat(_T_210, _T_201) @[Cat.scala 29:58] + node ld_byte_hitvec_hi_2 = cat(_T_211, _T_197) @[Cat.scala 29:58] + node _T_212 = bits(buf_byteen[0], 3, 3) @[lsu_bus_buffer.scala 142:110] + node _T_213 = and(ld_addr_hitvec_hi_0, _T_212) @[lsu_bus_buffer.scala 142:95] + node _T_214 = bits(ldst_byteen_hi_m, 3, 3) @[lsu_bus_buffer.scala 142:132] + node _T_215 = and(_T_213, _T_214) @[lsu_bus_buffer.scala 142:114] + node _T_216 = bits(buf_byteen[1], 3, 3) @[lsu_bus_buffer.scala 142:110] + node _T_217 = and(ld_addr_hitvec_hi_1, _T_216) @[lsu_bus_buffer.scala 142:95] + node _T_218 = bits(ldst_byteen_hi_m, 3, 3) @[lsu_bus_buffer.scala 142:132] + node _T_219 = and(_T_217, _T_218) @[lsu_bus_buffer.scala 142:114] + node _T_220 = bits(buf_byteen[2], 3, 3) @[lsu_bus_buffer.scala 142:110] + node _T_221 = and(ld_addr_hitvec_hi_2, _T_220) @[lsu_bus_buffer.scala 142:95] + node _T_222 = bits(ldst_byteen_hi_m, 3, 3) @[lsu_bus_buffer.scala 142:132] + node _T_223 = and(_T_221, _T_222) @[lsu_bus_buffer.scala 142:114] + node _T_224 = bits(buf_byteen[3], 3, 3) @[lsu_bus_buffer.scala 142:110] + node _T_225 = and(ld_addr_hitvec_hi_3, _T_224) @[lsu_bus_buffer.scala 142:95] + node _T_226 = bits(ldst_byteen_hi_m, 3, 3) @[lsu_bus_buffer.scala 142:132] + node _T_227 = and(_T_225, _T_226) @[lsu_bus_buffer.scala 142:114] + node _T_228 = cat(_T_227, _T_223) @[Cat.scala 29:58] + node _T_229 = cat(_T_228, _T_219) @[Cat.scala 29:58] + node ld_byte_hitvec_hi_3 = cat(_T_229, _T_215) @[Cat.scala 29:58] + wire buf_age_younger : UInt<4>[4] @[lsu_bus_buffer.scala 144:29] + buf_age_younger[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 145:19] + buf_age_younger[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 145:19] + buf_age_younger[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 145:19] + buf_age_younger[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 145:19] + node _T_230 = bits(ld_byte_hitvec_lo_0, 0, 0) @[lsu_bus_buffer.scala 146:93] + node _T_231 = and(ld_byte_hitvec_lo_0, buf_age_younger[0]) @[lsu_bus_buffer.scala 146:122] + node _T_232 = orr(_T_231) @[lsu_bus_buffer.scala 146:144] + node _T_233 = eq(_T_232, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] + node _T_234 = and(_T_230, _T_233) @[lsu_bus_buffer.scala 146:97] + node _T_235 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[lsu_bus_buffer.scala 146:170] + node _T_236 = eq(_T_235, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] + node _T_237 = and(_T_234, _T_236) @[lsu_bus_buffer.scala 146:148] + node _T_238 = bits(ld_byte_hitvec_lo_0, 1, 1) @[lsu_bus_buffer.scala 146:93] + node _T_239 = and(ld_byte_hitvec_lo_0, buf_age_younger[1]) @[lsu_bus_buffer.scala 146:122] + node _T_240 = orr(_T_239) @[lsu_bus_buffer.scala 146:144] + node _T_241 = eq(_T_240, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] + node _T_242 = and(_T_238, _T_241) @[lsu_bus_buffer.scala 146:97] + node _T_243 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[lsu_bus_buffer.scala 146:170] + node _T_244 = eq(_T_243, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] + node _T_245 = and(_T_242, _T_244) @[lsu_bus_buffer.scala 146:148] + node _T_246 = bits(ld_byte_hitvec_lo_0, 2, 2) @[lsu_bus_buffer.scala 146:93] + node _T_247 = and(ld_byte_hitvec_lo_0, buf_age_younger[2]) @[lsu_bus_buffer.scala 146:122] + node _T_248 = orr(_T_247) @[lsu_bus_buffer.scala 146:144] + node _T_249 = eq(_T_248, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] + node _T_250 = and(_T_246, _T_249) @[lsu_bus_buffer.scala 146:97] + node _T_251 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[lsu_bus_buffer.scala 146:170] + node _T_252 = eq(_T_251, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] + node _T_253 = and(_T_250, _T_252) @[lsu_bus_buffer.scala 146:148] + node _T_254 = bits(ld_byte_hitvec_lo_0, 3, 3) @[lsu_bus_buffer.scala 146:93] + node _T_255 = and(ld_byte_hitvec_lo_0, buf_age_younger[3]) @[lsu_bus_buffer.scala 146:122] + node _T_256 = orr(_T_255) @[lsu_bus_buffer.scala 146:144] + node _T_257 = eq(_T_256, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] + node _T_258 = and(_T_254, _T_257) @[lsu_bus_buffer.scala 146:97] + node _T_259 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[lsu_bus_buffer.scala 146:170] + node _T_260 = eq(_T_259, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] + node _T_261 = and(_T_258, _T_260) @[lsu_bus_buffer.scala 146:148] + node _T_262 = cat(_T_261, _T_253) @[Cat.scala 29:58] + node _T_263 = cat(_T_262, _T_245) @[Cat.scala 29:58] + node _T_264 = cat(_T_263, _T_237) @[Cat.scala 29:58] + node _T_265 = bits(ld_byte_hitvec_lo_1, 0, 0) @[lsu_bus_buffer.scala 146:93] + node _T_266 = and(ld_byte_hitvec_lo_1, buf_age_younger[0]) @[lsu_bus_buffer.scala 146:122] + node _T_267 = orr(_T_266) @[lsu_bus_buffer.scala 146:144] + node _T_268 = eq(_T_267, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] + node _T_269 = and(_T_265, _T_268) @[lsu_bus_buffer.scala 146:97] + node _T_270 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[lsu_bus_buffer.scala 146:170] + node _T_271 = eq(_T_270, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] + node _T_272 = and(_T_269, _T_271) @[lsu_bus_buffer.scala 146:148] + node _T_273 = bits(ld_byte_hitvec_lo_1, 1, 1) @[lsu_bus_buffer.scala 146:93] + node _T_274 = and(ld_byte_hitvec_lo_1, buf_age_younger[1]) @[lsu_bus_buffer.scala 146:122] + node _T_275 = orr(_T_274) @[lsu_bus_buffer.scala 146:144] + node _T_276 = eq(_T_275, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] + node _T_277 = and(_T_273, _T_276) @[lsu_bus_buffer.scala 146:97] + node _T_278 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[lsu_bus_buffer.scala 146:170] + node _T_279 = eq(_T_278, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] + node _T_280 = and(_T_277, _T_279) @[lsu_bus_buffer.scala 146:148] + node _T_281 = bits(ld_byte_hitvec_lo_1, 2, 2) @[lsu_bus_buffer.scala 146:93] + node _T_282 = and(ld_byte_hitvec_lo_1, buf_age_younger[2]) @[lsu_bus_buffer.scala 146:122] + node _T_283 = orr(_T_282) @[lsu_bus_buffer.scala 146:144] + node _T_284 = eq(_T_283, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] + node _T_285 = and(_T_281, _T_284) @[lsu_bus_buffer.scala 146:97] + node _T_286 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[lsu_bus_buffer.scala 146:170] + node _T_287 = eq(_T_286, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] + node _T_288 = and(_T_285, _T_287) @[lsu_bus_buffer.scala 146:148] + node _T_289 = bits(ld_byte_hitvec_lo_1, 3, 3) @[lsu_bus_buffer.scala 146:93] + node _T_290 = and(ld_byte_hitvec_lo_1, buf_age_younger[3]) @[lsu_bus_buffer.scala 146:122] + node _T_291 = orr(_T_290) @[lsu_bus_buffer.scala 146:144] + node _T_292 = eq(_T_291, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] + node _T_293 = and(_T_289, _T_292) @[lsu_bus_buffer.scala 146:97] + node _T_294 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[lsu_bus_buffer.scala 146:170] + node _T_295 = eq(_T_294, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] + node _T_296 = and(_T_293, _T_295) @[lsu_bus_buffer.scala 146:148] + node _T_297 = cat(_T_296, _T_288) @[Cat.scala 29:58] + node _T_298 = cat(_T_297, _T_280) @[Cat.scala 29:58] + node _T_299 = cat(_T_298, _T_272) @[Cat.scala 29:58] + node _T_300 = bits(ld_byte_hitvec_lo_2, 0, 0) @[lsu_bus_buffer.scala 146:93] + node _T_301 = and(ld_byte_hitvec_lo_2, buf_age_younger[0]) @[lsu_bus_buffer.scala 146:122] + node _T_302 = orr(_T_301) @[lsu_bus_buffer.scala 146:144] + node _T_303 = eq(_T_302, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] + node _T_304 = and(_T_300, _T_303) @[lsu_bus_buffer.scala 146:97] + node _T_305 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[lsu_bus_buffer.scala 146:170] + node _T_306 = eq(_T_305, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] + node _T_307 = and(_T_304, _T_306) @[lsu_bus_buffer.scala 146:148] + node _T_308 = bits(ld_byte_hitvec_lo_2, 1, 1) @[lsu_bus_buffer.scala 146:93] + node _T_309 = and(ld_byte_hitvec_lo_2, buf_age_younger[1]) @[lsu_bus_buffer.scala 146:122] + node _T_310 = orr(_T_309) @[lsu_bus_buffer.scala 146:144] + node _T_311 = eq(_T_310, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] + node _T_312 = and(_T_308, _T_311) @[lsu_bus_buffer.scala 146:97] + node _T_313 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[lsu_bus_buffer.scala 146:170] + node _T_314 = eq(_T_313, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] + node _T_315 = and(_T_312, _T_314) @[lsu_bus_buffer.scala 146:148] + node _T_316 = bits(ld_byte_hitvec_lo_2, 2, 2) @[lsu_bus_buffer.scala 146:93] + node _T_317 = and(ld_byte_hitvec_lo_2, buf_age_younger[2]) @[lsu_bus_buffer.scala 146:122] + node _T_318 = orr(_T_317) @[lsu_bus_buffer.scala 146:144] + node _T_319 = eq(_T_318, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] + node _T_320 = and(_T_316, _T_319) @[lsu_bus_buffer.scala 146:97] + node _T_321 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[lsu_bus_buffer.scala 146:170] + node _T_322 = eq(_T_321, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] + node _T_323 = and(_T_320, _T_322) @[lsu_bus_buffer.scala 146:148] + node _T_324 = bits(ld_byte_hitvec_lo_2, 3, 3) @[lsu_bus_buffer.scala 146:93] + node _T_325 = and(ld_byte_hitvec_lo_2, buf_age_younger[3]) @[lsu_bus_buffer.scala 146:122] + node _T_326 = orr(_T_325) @[lsu_bus_buffer.scala 146:144] + node _T_327 = eq(_T_326, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] + node _T_328 = and(_T_324, _T_327) @[lsu_bus_buffer.scala 146:97] + node _T_329 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[lsu_bus_buffer.scala 146:170] + node _T_330 = eq(_T_329, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] + node _T_331 = and(_T_328, _T_330) @[lsu_bus_buffer.scala 146:148] + node _T_332 = cat(_T_331, _T_323) @[Cat.scala 29:58] + node _T_333 = cat(_T_332, _T_315) @[Cat.scala 29:58] + node _T_334 = cat(_T_333, _T_307) @[Cat.scala 29:58] + node _T_335 = bits(ld_byte_hitvec_lo_3, 0, 0) @[lsu_bus_buffer.scala 146:93] + node _T_336 = and(ld_byte_hitvec_lo_3, buf_age_younger[0]) @[lsu_bus_buffer.scala 146:122] + node _T_337 = orr(_T_336) @[lsu_bus_buffer.scala 146:144] + node _T_338 = eq(_T_337, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] + node _T_339 = and(_T_335, _T_338) @[lsu_bus_buffer.scala 146:97] + node _T_340 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[lsu_bus_buffer.scala 146:170] + node _T_341 = eq(_T_340, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] + node _T_342 = and(_T_339, _T_341) @[lsu_bus_buffer.scala 146:148] + node _T_343 = bits(ld_byte_hitvec_lo_3, 1, 1) @[lsu_bus_buffer.scala 146:93] + node _T_344 = and(ld_byte_hitvec_lo_3, buf_age_younger[1]) @[lsu_bus_buffer.scala 146:122] + node _T_345 = orr(_T_344) @[lsu_bus_buffer.scala 146:144] + node _T_346 = eq(_T_345, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] + node _T_347 = and(_T_343, _T_346) @[lsu_bus_buffer.scala 146:97] + node _T_348 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[lsu_bus_buffer.scala 146:170] + node _T_349 = eq(_T_348, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] + node _T_350 = and(_T_347, _T_349) @[lsu_bus_buffer.scala 146:148] + node _T_351 = bits(ld_byte_hitvec_lo_3, 2, 2) @[lsu_bus_buffer.scala 146:93] + node _T_352 = and(ld_byte_hitvec_lo_3, buf_age_younger[2]) @[lsu_bus_buffer.scala 146:122] + node _T_353 = orr(_T_352) @[lsu_bus_buffer.scala 146:144] + node _T_354 = eq(_T_353, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] + node _T_355 = and(_T_351, _T_354) @[lsu_bus_buffer.scala 146:97] + node _T_356 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[lsu_bus_buffer.scala 146:170] + node _T_357 = eq(_T_356, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] + node _T_358 = and(_T_355, _T_357) @[lsu_bus_buffer.scala 146:148] + node _T_359 = bits(ld_byte_hitvec_lo_3, 3, 3) @[lsu_bus_buffer.scala 146:93] + node _T_360 = and(ld_byte_hitvec_lo_3, buf_age_younger[3]) @[lsu_bus_buffer.scala 146:122] + node _T_361 = orr(_T_360) @[lsu_bus_buffer.scala 146:144] + node _T_362 = eq(_T_361, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] + node _T_363 = and(_T_359, _T_362) @[lsu_bus_buffer.scala 146:97] + node _T_364 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[lsu_bus_buffer.scala 146:170] + node _T_365 = eq(_T_364, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] + node _T_366 = and(_T_363, _T_365) @[lsu_bus_buffer.scala 146:148] + node _T_367 = cat(_T_366, _T_358) @[Cat.scala 29:58] + node _T_368 = cat(_T_367, _T_350) @[Cat.scala 29:58] + node _T_369 = cat(_T_368, _T_342) @[Cat.scala 29:58] + ld_byte_hitvecfn_lo[0] <= _T_264 @[lsu_bus_buffer.scala 146:23] + ld_byte_hitvecfn_lo[1] <= _T_299 @[lsu_bus_buffer.scala 146:23] + ld_byte_hitvecfn_lo[2] <= _T_334 @[lsu_bus_buffer.scala 146:23] + ld_byte_hitvecfn_lo[3] <= _T_369 @[lsu_bus_buffer.scala 146:23] + node _T_370 = bits(ld_byte_hitvec_hi_0, 0, 0) @[lsu_bus_buffer.scala 147:93] + node _T_371 = and(ld_byte_hitvec_hi_0, buf_age_younger[0]) @[lsu_bus_buffer.scala 147:122] + node _T_372 = orr(_T_371) @[lsu_bus_buffer.scala 147:144] + node _T_373 = eq(_T_372, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:99] + node _T_374 = and(_T_370, _T_373) @[lsu_bus_buffer.scala 147:97] + node _T_375 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[lsu_bus_buffer.scala 147:170] + node _T_376 = eq(_T_375, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:150] + node _T_377 = and(_T_374, _T_376) @[lsu_bus_buffer.scala 147:148] + node _T_378 = bits(ld_byte_hitvec_hi_0, 1, 1) @[lsu_bus_buffer.scala 147:93] + node _T_379 = and(ld_byte_hitvec_hi_0, buf_age_younger[1]) @[lsu_bus_buffer.scala 147:122] + node _T_380 = orr(_T_379) @[lsu_bus_buffer.scala 147:144] + node _T_381 = eq(_T_380, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:99] + node _T_382 = and(_T_378, _T_381) @[lsu_bus_buffer.scala 147:97] + node _T_383 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[lsu_bus_buffer.scala 147:170] + node _T_384 = eq(_T_383, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:150] + node _T_385 = and(_T_382, _T_384) @[lsu_bus_buffer.scala 147:148] + node _T_386 = bits(ld_byte_hitvec_hi_0, 2, 2) @[lsu_bus_buffer.scala 147:93] + node _T_387 = and(ld_byte_hitvec_hi_0, buf_age_younger[2]) @[lsu_bus_buffer.scala 147:122] + node _T_388 = orr(_T_387) @[lsu_bus_buffer.scala 147:144] + node _T_389 = eq(_T_388, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:99] + node _T_390 = and(_T_386, _T_389) @[lsu_bus_buffer.scala 147:97] + node _T_391 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[lsu_bus_buffer.scala 147:170] + node _T_392 = eq(_T_391, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:150] + node _T_393 = and(_T_390, _T_392) @[lsu_bus_buffer.scala 147:148] + node _T_394 = bits(ld_byte_hitvec_hi_0, 3, 3) @[lsu_bus_buffer.scala 147:93] + node _T_395 = and(ld_byte_hitvec_hi_0, buf_age_younger[3]) @[lsu_bus_buffer.scala 147:122] + node _T_396 = orr(_T_395) @[lsu_bus_buffer.scala 147:144] + node _T_397 = eq(_T_396, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:99] + node _T_398 = and(_T_394, _T_397) @[lsu_bus_buffer.scala 147:97] + node _T_399 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[lsu_bus_buffer.scala 147:170] + node _T_400 = eq(_T_399, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:150] + node _T_401 = and(_T_398, _T_400) @[lsu_bus_buffer.scala 147:148] + node _T_402 = cat(_T_401, _T_393) @[Cat.scala 29:58] + node _T_403 = cat(_T_402, _T_385) @[Cat.scala 29:58] + node _T_404 = cat(_T_403, _T_377) @[Cat.scala 29:58] + node _T_405 = bits(ld_byte_hitvec_hi_1, 0, 0) @[lsu_bus_buffer.scala 147:93] + node _T_406 = and(ld_byte_hitvec_hi_1, buf_age_younger[0]) @[lsu_bus_buffer.scala 147:122] + node _T_407 = orr(_T_406) @[lsu_bus_buffer.scala 147:144] + node _T_408 = eq(_T_407, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:99] + node _T_409 = and(_T_405, _T_408) @[lsu_bus_buffer.scala 147:97] + node _T_410 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[lsu_bus_buffer.scala 147:170] + node _T_411 = eq(_T_410, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:150] + node _T_412 = and(_T_409, _T_411) @[lsu_bus_buffer.scala 147:148] + node _T_413 = bits(ld_byte_hitvec_hi_1, 1, 1) @[lsu_bus_buffer.scala 147:93] + node _T_414 = and(ld_byte_hitvec_hi_1, buf_age_younger[1]) @[lsu_bus_buffer.scala 147:122] + node _T_415 = orr(_T_414) @[lsu_bus_buffer.scala 147:144] + node _T_416 = eq(_T_415, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:99] + node _T_417 = and(_T_413, _T_416) @[lsu_bus_buffer.scala 147:97] + node _T_418 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[lsu_bus_buffer.scala 147:170] + node _T_419 = eq(_T_418, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:150] + node _T_420 = and(_T_417, _T_419) @[lsu_bus_buffer.scala 147:148] + node _T_421 = bits(ld_byte_hitvec_hi_1, 2, 2) @[lsu_bus_buffer.scala 147:93] + node _T_422 = and(ld_byte_hitvec_hi_1, buf_age_younger[2]) @[lsu_bus_buffer.scala 147:122] + node _T_423 = orr(_T_422) @[lsu_bus_buffer.scala 147:144] + node _T_424 = eq(_T_423, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:99] + node _T_425 = and(_T_421, _T_424) @[lsu_bus_buffer.scala 147:97] + node _T_426 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[lsu_bus_buffer.scala 147:170] + node _T_427 = eq(_T_426, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:150] + node _T_428 = and(_T_425, _T_427) @[lsu_bus_buffer.scala 147:148] + node _T_429 = bits(ld_byte_hitvec_hi_1, 3, 3) @[lsu_bus_buffer.scala 147:93] + node _T_430 = and(ld_byte_hitvec_hi_1, buf_age_younger[3]) @[lsu_bus_buffer.scala 147:122] + node _T_431 = orr(_T_430) @[lsu_bus_buffer.scala 147:144] + node _T_432 = eq(_T_431, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:99] + node _T_433 = and(_T_429, _T_432) @[lsu_bus_buffer.scala 147:97] + node _T_434 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[lsu_bus_buffer.scala 147:170] + node _T_435 = eq(_T_434, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:150] + node _T_436 = and(_T_433, _T_435) @[lsu_bus_buffer.scala 147:148] + node _T_437 = cat(_T_436, _T_428) @[Cat.scala 29:58] + node _T_438 = cat(_T_437, _T_420) @[Cat.scala 29:58] + node _T_439 = cat(_T_438, _T_412) @[Cat.scala 29:58] + node _T_440 = bits(ld_byte_hitvec_hi_2, 0, 0) @[lsu_bus_buffer.scala 147:93] + node _T_441 = and(ld_byte_hitvec_hi_2, buf_age_younger[0]) @[lsu_bus_buffer.scala 147:122] + node _T_442 = orr(_T_441) @[lsu_bus_buffer.scala 147:144] + node _T_443 = eq(_T_442, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:99] + node _T_444 = and(_T_440, _T_443) @[lsu_bus_buffer.scala 147:97] + node _T_445 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[lsu_bus_buffer.scala 147:170] + node _T_446 = eq(_T_445, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:150] + node _T_447 = and(_T_444, _T_446) @[lsu_bus_buffer.scala 147:148] + node _T_448 = bits(ld_byte_hitvec_hi_2, 1, 1) @[lsu_bus_buffer.scala 147:93] + node _T_449 = and(ld_byte_hitvec_hi_2, buf_age_younger[1]) @[lsu_bus_buffer.scala 147:122] + node _T_450 = orr(_T_449) @[lsu_bus_buffer.scala 147:144] + node _T_451 = eq(_T_450, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:99] + node _T_452 = and(_T_448, _T_451) @[lsu_bus_buffer.scala 147:97] + node _T_453 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[lsu_bus_buffer.scala 147:170] + node _T_454 = eq(_T_453, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:150] + node _T_455 = and(_T_452, _T_454) @[lsu_bus_buffer.scala 147:148] + node _T_456 = bits(ld_byte_hitvec_hi_2, 2, 2) @[lsu_bus_buffer.scala 147:93] + node _T_457 = and(ld_byte_hitvec_hi_2, buf_age_younger[2]) @[lsu_bus_buffer.scala 147:122] + node _T_458 = orr(_T_457) @[lsu_bus_buffer.scala 147:144] + node _T_459 = eq(_T_458, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:99] + node _T_460 = and(_T_456, _T_459) @[lsu_bus_buffer.scala 147:97] + node _T_461 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[lsu_bus_buffer.scala 147:170] + node _T_462 = eq(_T_461, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:150] + node _T_463 = and(_T_460, _T_462) @[lsu_bus_buffer.scala 147:148] + node _T_464 = bits(ld_byte_hitvec_hi_2, 3, 3) @[lsu_bus_buffer.scala 147:93] + node _T_465 = and(ld_byte_hitvec_hi_2, buf_age_younger[3]) @[lsu_bus_buffer.scala 147:122] + node _T_466 = orr(_T_465) @[lsu_bus_buffer.scala 147:144] + node _T_467 = eq(_T_466, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:99] + node _T_468 = and(_T_464, _T_467) @[lsu_bus_buffer.scala 147:97] + node _T_469 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[lsu_bus_buffer.scala 147:170] + node _T_470 = eq(_T_469, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:150] + node _T_471 = and(_T_468, _T_470) @[lsu_bus_buffer.scala 147:148] + node _T_472 = cat(_T_471, _T_463) @[Cat.scala 29:58] + node _T_473 = cat(_T_472, _T_455) @[Cat.scala 29:58] + node _T_474 = cat(_T_473, _T_447) @[Cat.scala 29:58] + node _T_475 = bits(ld_byte_hitvec_hi_3, 0, 0) @[lsu_bus_buffer.scala 147:93] + node _T_476 = and(ld_byte_hitvec_hi_3, buf_age_younger[0]) @[lsu_bus_buffer.scala 147:122] + node _T_477 = orr(_T_476) @[lsu_bus_buffer.scala 147:144] + node _T_478 = eq(_T_477, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:99] + node _T_479 = and(_T_475, _T_478) @[lsu_bus_buffer.scala 147:97] + node _T_480 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[lsu_bus_buffer.scala 147:170] + node _T_481 = eq(_T_480, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:150] + node _T_482 = and(_T_479, _T_481) @[lsu_bus_buffer.scala 147:148] + node _T_483 = bits(ld_byte_hitvec_hi_3, 1, 1) @[lsu_bus_buffer.scala 147:93] + node _T_484 = and(ld_byte_hitvec_hi_3, buf_age_younger[1]) @[lsu_bus_buffer.scala 147:122] + node _T_485 = orr(_T_484) @[lsu_bus_buffer.scala 147:144] + node _T_486 = eq(_T_485, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:99] + node _T_487 = and(_T_483, _T_486) @[lsu_bus_buffer.scala 147:97] + node _T_488 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[lsu_bus_buffer.scala 147:170] + node _T_489 = eq(_T_488, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:150] + node _T_490 = and(_T_487, _T_489) @[lsu_bus_buffer.scala 147:148] + node _T_491 = bits(ld_byte_hitvec_hi_3, 2, 2) @[lsu_bus_buffer.scala 147:93] + node _T_492 = and(ld_byte_hitvec_hi_3, buf_age_younger[2]) @[lsu_bus_buffer.scala 147:122] + node _T_493 = orr(_T_492) @[lsu_bus_buffer.scala 147:144] + node _T_494 = eq(_T_493, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:99] + node _T_495 = and(_T_491, _T_494) @[lsu_bus_buffer.scala 147:97] + node _T_496 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[lsu_bus_buffer.scala 147:170] + node _T_497 = eq(_T_496, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:150] + node _T_498 = and(_T_495, _T_497) @[lsu_bus_buffer.scala 147:148] + node _T_499 = bits(ld_byte_hitvec_hi_3, 3, 3) @[lsu_bus_buffer.scala 147:93] + node _T_500 = and(ld_byte_hitvec_hi_3, buf_age_younger[3]) @[lsu_bus_buffer.scala 147:122] + node _T_501 = orr(_T_500) @[lsu_bus_buffer.scala 147:144] + node _T_502 = eq(_T_501, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:99] + node _T_503 = and(_T_499, _T_502) @[lsu_bus_buffer.scala 147:97] + node _T_504 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[lsu_bus_buffer.scala 147:170] + node _T_505 = eq(_T_504, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:150] + node _T_506 = and(_T_503, _T_505) @[lsu_bus_buffer.scala 147:148] + node _T_507 = cat(_T_506, _T_498) @[Cat.scala 29:58] + node _T_508 = cat(_T_507, _T_490) @[Cat.scala 29:58] + node _T_509 = cat(_T_508, _T_482) @[Cat.scala 29:58] + ld_byte_hitvecfn_hi[0] <= _T_404 @[lsu_bus_buffer.scala 147:23] + ld_byte_hitvecfn_hi[1] <= _T_439 @[lsu_bus_buffer.scala 147:23] + ld_byte_hitvecfn_hi[2] <= _T_474 @[lsu_bus_buffer.scala 147:23] + ld_byte_hitvecfn_hi[3] <= _T_509 @[lsu_bus_buffer.scala 147:23] + wire ibuf_addr : UInt<32> + ibuf_addr <= UInt<1>("h00") + wire ibuf_write : UInt<1> + ibuf_write <= UInt<1>("h00") + wire ibuf_valid : UInt<1> + ibuf_valid <= UInt<1>("h00") + node _T_510 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 152:43] + node _T_511 = bits(ibuf_addr, 31, 2) @[lsu_bus_buffer.scala 152:64] + node _T_512 = eq(_T_510, _T_511) @[lsu_bus_buffer.scala 152:51] + node _T_513 = and(_T_512, ibuf_write) @[lsu_bus_buffer.scala 152:73] + node _T_514 = and(_T_513, ibuf_valid) @[lsu_bus_buffer.scala 152:86] + node ld_addr_ibuf_hit_lo = and(_T_514, io.lsu_busreq_m) @[lsu_bus_buffer.scala 152:99] + node _T_515 = bits(io.end_addr_m, 31, 2) @[lsu_bus_buffer.scala 153:43] + node _T_516 = bits(ibuf_addr, 31, 2) @[lsu_bus_buffer.scala 153:64] + node _T_517 = eq(_T_515, _T_516) @[lsu_bus_buffer.scala 153:51] + node _T_518 = and(_T_517, ibuf_write) @[lsu_bus_buffer.scala 153:73] + node _T_519 = and(_T_518, ibuf_valid) @[lsu_bus_buffer.scala 153:86] + node ld_addr_ibuf_hit_hi = and(_T_519, io.lsu_busreq_m) @[lsu_bus_buffer.scala 153:99] + wire ibuf_byteen : UInt<4> + ibuf_byteen <= UInt<1>("h00") + node _T_520 = bits(ld_addr_ibuf_hit_lo, 0, 0) @[Bitwise.scala 72:15] + node _T_521 = mux(_T_520, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_522 = and(_T_521, ibuf_byteen) @[lsu_bus_buffer.scala 157:55] + node _T_523 = and(_T_522, ldst_byteen_lo_m) @[lsu_bus_buffer.scala 157:69] + ld_byte_ibuf_hit_lo <= _T_523 @[lsu_bus_buffer.scala 157:23] + node _T_524 = bits(ld_addr_ibuf_hit_hi, 0, 0) @[Bitwise.scala 72:15] + node _T_525 = mux(_T_524, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_526 = and(_T_525, ibuf_byteen) @[lsu_bus_buffer.scala 158:55] + node _T_527 = and(_T_526, ldst_byteen_hi_m) @[lsu_bus_buffer.scala 158:69] + ld_byte_ibuf_hit_hi <= _T_527 @[lsu_bus_buffer.scala 158:23] + wire buf_data : UInt<32>[4] @[lsu_bus_buffer.scala 160:22] + buf_data[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 161:12] + buf_data[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 161:12] + buf_data[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 161:12] + buf_data[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 161:12] + wire fwd_data : UInt<32> + fwd_data <= UInt<1>("h00") + node _T_528 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[lsu_bus_buffer.scala 163:81] + node _T_529 = bits(_T_528, 0, 0) @[Bitwise.scala 72:15] + node _T_530 = mux(_T_529, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_531 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[lsu_bus_buffer.scala 163:81] + node _T_532 = bits(_T_531, 0, 0) @[Bitwise.scala 72:15] + node _T_533 = mux(_T_532, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_534 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[lsu_bus_buffer.scala 163:81] + node _T_535 = bits(_T_534, 0, 0) @[Bitwise.scala 72:15] + node _T_536 = mux(_T_535, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_537 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[lsu_bus_buffer.scala 163:81] + node _T_538 = bits(_T_537, 0, 0) @[Bitwise.scala 72:15] + node _T_539 = mux(_T_538, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_540 = cat(_T_539, _T_536) @[Cat.scala 29:58] + node _T_541 = cat(_T_540, _T_533) @[Cat.scala 29:58] + node ld_fwddata_buf_lo_initial = cat(_T_541, _T_530) @[Cat.scala 29:58] + node _T_542 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[lsu_bus_buffer.scala 164:81] + node _T_543 = bits(_T_542, 0, 0) @[Bitwise.scala 72:15] + node _T_544 = mux(_T_543, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_545 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[lsu_bus_buffer.scala 164:81] + node _T_546 = bits(_T_545, 0, 0) @[Bitwise.scala 72:15] + node _T_547 = mux(_T_546, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_548 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[lsu_bus_buffer.scala 164:81] + node _T_549 = bits(_T_548, 0, 0) @[Bitwise.scala 72:15] + node _T_550 = mux(_T_549, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_551 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[lsu_bus_buffer.scala 164:81] + node _T_552 = bits(_T_551, 0, 0) @[Bitwise.scala 72:15] + node _T_553 = mux(_T_552, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_554 = cat(_T_553, _T_550) @[Cat.scala 29:58] + node _T_555 = cat(_T_554, _T_547) @[Cat.scala 29:58] + node ld_fwddata_buf_hi_initial = cat(_T_555, _T_544) @[Cat.scala 29:58] + node _T_556 = bits(ld_byte_hitvecfn_lo[3], 0, 0) @[lsu_bus_buffer.scala 165:86] + node _T_557 = bits(_T_556, 0, 0) @[Bitwise.scala 72:15] + node _T_558 = mux(_T_557, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_559 = bits(buf_data[0], 31, 24) @[lsu_bus_buffer.scala 165:104] + node _T_560 = and(_T_558, _T_559) @[lsu_bus_buffer.scala 165:91] + node _T_561 = bits(ld_byte_hitvecfn_lo[3], 1, 1) @[lsu_bus_buffer.scala 165:86] + node _T_562 = bits(_T_561, 0, 0) @[Bitwise.scala 72:15] + node _T_563 = mux(_T_562, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_564 = bits(buf_data[1], 31, 24) @[lsu_bus_buffer.scala 165:104] + node _T_565 = and(_T_563, _T_564) @[lsu_bus_buffer.scala 165:91] + node _T_566 = bits(ld_byte_hitvecfn_lo[3], 2, 2) @[lsu_bus_buffer.scala 165:86] + node _T_567 = bits(_T_566, 0, 0) @[Bitwise.scala 72:15] + node _T_568 = mux(_T_567, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_569 = bits(buf_data[2], 31, 24) @[lsu_bus_buffer.scala 165:104] + node _T_570 = and(_T_568, _T_569) @[lsu_bus_buffer.scala 165:91] + node _T_571 = bits(ld_byte_hitvecfn_lo[3], 3, 3) @[lsu_bus_buffer.scala 165:86] + node _T_572 = bits(_T_571, 0, 0) @[Bitwise.scala 72:15] + node _T_573 = mux(_T_572, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_574 = bits(buf_data[3], 31, 24) @[lsu_bus_buffer.scala 165:104] + node _T_575 = and(_T_573, _T_574) @[lsu_bus_buffer.scala 165:91] + node _T_576 = or(_T_560, _T_565) @[lsu_bus_buffer.scala 165:123] + node _T_577 = or(_T_576, _T_570) @[lsu_bus_buffer.scala 165:123] + node _T_578 = or(_T_577, _T_575) @[lsu_bus_buffer.scala 165:123] + node _T_579 = bits(ld_byte_hitvecfn_lo[2], 0, 0) @[lsu_bus_buffer.scala 166:60] + node _T_580 = bits(_T_579, 0, 0) @[Bitwise.scala 72:15] + node _T_581 = mux(_T_580, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_582 = bits(buf_data[0], 23, 16) @[lsu_bus_buffer.scala 166:78] + node _T_583 = and(_T_581, _T_582) @[lsu_bus_buffer.scala 166:65] + node _T_584 = bits(ld_byte_hitvecfn_lo[2], 1, 1) @[lsu_bus_buffer.scala 166:60] + node _T_585 = bits(_T_584, 0, 0) @[Bitwise.scala 72:15] + node _T_586 = mux(_T_585, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_587 = bits(buf_data[1], 23, 16) @[lsu_bus_buffer.scala 166:78] + node _T_588 = and(_T_586, _T_587) @[lsu_bus_buffer.scala 166:65] + node _T_589 = bits(ld_byte_hitvecfn_lo[2], 2, 2) @[lsu_bus_buffer.scala 166:60] + node _T_590 = bits(_T_589, 0, 0) @[Bitwise.scala 72:15] + node _T_591 = mux(_T_590, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_592 = bits(buf_data[2], 23, 16) @[lsu_bus_buffer.scala 166:78] + node _T_593 = and(_T_591, _T_592) @[lsu_bus_buffer.scala 166:65] + node _T_594 = bits(ld_byte_hitvecfn_lo[2], 3, 3) @[lsu_bus_buffer.scala 166:60] + node _T_595 = bits(_T_594, 0, 0) @[Bitwise.scala 72:15] + node _T_596 = mux(_T_595, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_597 = bits(buf_data[3], 23, 16) @[lsu_bus_buffer.scala 166:78] + node _T_598 = and(_T_596, _T_597) @[lsu_bus_buffer.scala 166:65] + node _T_599 = or(_T_583, _T_588) @[lsu_bus_buffer.scala 166:97] + node _T_600 = or(_T_599, _T_593) @[lsu_bus_buffer.scala 166:97] + node _T_601 = or(_T_600, _T_598) @[lsu_bus_buffer.scala 166:97] + node _T_602 = bits(ld_byte_hitvecfn_lo[1], 0, 0) @[lsu_bus_buffer.scala 167:60] + node _T_603 = bits(_T_602, 0, 0) @[Bitwise.scala 72:15] + node _T_604 = mux(_T_603, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_605 = bits(buf_data[0], 15, 8) @[lsu_bus_buffer.scala 167:78] + node _T_606 = and(_T_604, _T_605) @[lsu_bus_buffer.scala 167:65] + node _T_607 = bits(ld_byte_hitvecfn_lo[1], 1, 1) @[lsu_bus_buffer.scala 167:60] + node _T_608 = bits(_T_607, 0, 0) @[Bitwise.scala 72:15] + node _T_609 = mux(_T_608, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_610 = bits(buf_data[1], 15, 8) @[lsu_bus_buffer.scala 167:78] + node _T_611 = and(_T_609, _T_610) @[lsu_bus_buffer.scala 167:65] + node _T_612 = bits(ld_byte_hitvecfn_lo[1], 2, 2) @[lsu_bus_buffer.scala 167:60] + node _T_613 = bits(_T_612, 0, 0) @[Bitwise.scala 72:15] + node _T_614 = mux(_T_613, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_615 = bits(buf_data[2], 15, 8) @[lsu_bus_buffer.scala 167:78] + node _T_616 = and(_T_614, _T_615) @[lsu_bus_buffer.scala 167:65] + node _T_617 = bits(ld_byte_hitvecfn_lo[1], 3, 3) @[lsu_bus_buffer.scala 167:60] + node _T_618 = bits(_T_617, 0, 0) @[Bitwise.scala 72:15] + node _T_619 = mux(_T_618, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_620 = bits(buf_data[3], 15, 8) @[lsu_bus_buffer.scala 167:78] + node _T_621 = and(_T_619, _T_620) @[lsu_bus_buffer.scala 167:65] + node _T_622 = or(_T_606, _T_611) @[lsu_bus_buffer.scala 167:97] + node _T_623 = or(_T_622, _T_616) @[lsu_bus_buffer.scala 167:97] + node _T_624 = or(_T_623, _T_621) @[lsu_bus_buffer.scala 167:97] + node _T_625 = bits(ld_byte_hitvecfn_lo[0], 0, 0) @[lsu_bus_buffer.scala 168:60] + node _T_626 = bits(_T_625, 0, 0) @[Bitwise.scala 72:15] + node _T_627 = mux(_T_626, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_628 = bits(buf_data[0], 7, 0) @[lsu_bus_buffer.scala 168:78] + node _T_629 = and(_T_627, _T_628) @[lsu_bus_buffer.scala 168:65] + node _T_630 = bits(ld_byte_hitvecfn_lo[0], 1, 1) @[lsu_bus_buffer.scala 168:60] + node _T_631 = bits(_T_630, 0, 0) @[Bitwise.scala 72:15] + node _T_632 = mux(_T_631, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_633 = bits(buf_data[1], 7, 0) @[lsu_bus_buffer.scala 168:78] + node _T_634 = and(_T_632, _T_633) @[lsu_bus_buffer.scala 168:65] + node _T_635 = bits(ld_byte_hitvecfn_lo[0], 2, 2) @[lsu_bus_buffer.scala 168:60] + node _T_636 = bits(_T_635, 0, 0) @[Bitwise.scala 72:15] + node _T_637 = mux(_T_636, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_638 = bits(buf_data[2], 7, 0) @[lsu_bus_buffer.scala 168:78] + node _T_639 = and(_T_637, _T_638) @[lsu_bus_buffer.scala 168:65] + node _T_640 = bits(ld_byte_hitvecfn_lo[0], 3, 3) @[lsu_bus_buffer.scala 168:60] + node _T_641 = bits(_T_640, 0, 0) @[Bitwise.scala 72:15] + node _T_642 = mux(_T_641, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_643 = bits(buf_data[3], 7, 0) @[lsu_bus_buffer.scala 168:78] + node _T_644 = and(_T_642, _T_643) @[lsu_bus_buffer.scala 168:65] + node _T_645 = or(_T_629, _T_634) @[lsu_bus_buffer.scala 168:97] + node _T_646 = or(_T_645, _T_639) @[lsu_bus_buffer.scala 168:97] + node _T_647 = or(_T_646, _T_644) @[lsu_bus_buffer.scala 168:97] + node _T_648 = cat(_T_624, _T_647) @[Cat.scala 29:58] + node _T_649 = cat(_T_578, _T_601) @[Cat.scala 29:58] + node _T_650 = cat(_T_649, _T_648) @[Cat.scala 29:58] + node _T_651 = and(ld_fwddata_buf_lo_initial, ibuf_data) @[lsu_bus_buffer.scala 169:32] + node _T_652 = or(_T_650, _T_651) @[lsu_bus_buffer.scala 168:103] + io.ld_fwddata_buf_lo <= _T_652 @[lsu_bus_buffer.scala 165:24] + node _T_653 = bits(ld_byte_hitvecfn_hi[3], 0, 0) @[lsu_bus_buffer.scala 171:86] + node _T_654 = bits(_T_653, 0, 0) @[Bitwise.scala 72:15] + node _T_655 = mux(_T_654, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_656 = bits(buf_data[0], 31, 24) @[lsu_bus_buffer.scala 171:104] + node _T_657 = and(_T_655, _T_656) @[lsu_bus_buffer.scala 171:91] + node _T_658 = bits(ld_byte_hitvecfn_hi[3], 1, 1) @[lsu_bus_buffer.scala 171:86] + node _T_659 = bits(_T_658, 0, 0) @[Bitwise.scala 72:15] + node _T_660 = mux(_T_659, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_661 = bits(buf_data[1], 31, 24) @[lsu_bus_buffer.scala 171:104] + node _T_662 = and(_T_660, _T_661) @[lsu_bus_buffer.scala 171:91] + node _T_663 = bits(ld_byte_hitvecfn_hi[3], 2, 2) @[lsu_bus_buffer.scala 171:86] + node _T_664 = bits(_T_663, 0, 0) @[Bitwise.scala 72:15] + node _T_665 = mux(_T_664, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_666 = bits(buf_data[2], 31, 24) @[lsu_bus_buffer.scala 171:104] + node _T_667 = and(_T_665, _T_666) @[lsu_bus_buffer.scala 171:91] + node _T_668 = bits(ld_byte_hitvecfn_hi[3], 3, 3) @[lsu_bus_buffer.scala 171:86] + node _T_669 = bits(_T_668, 0, 0) @[Bitwise.scala 72:15] + node _T_670 = mux(_T_669, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_671 = bits(buf_data[3], 31, 24) @[lsu_bus_buffer.scala 171:104] + node _T_672 = and(_T_670, _T_671) @[lsu_bus_buffer.scala 171:91] + node _T_673 = or(_T_657, _T_662) @[lsu_bus_buffer.scala 171:123] + node _T_674 = or(_T_673, _T_667) @[lsu_bus_buffer.scala 171:123] + node _T_675 = or(_T_674, _T_672) @[lsu_bus_buffer.scala 171:123] + node _T_676 = bits(ld_byte_hitvecfn_hi[2], 0, 0) @[lsu_bus_buffer.scala 172:60] + node _T_677 = bits(_T_676, 0, 0) @[Bitwise.scala 72:15] + node _T_678 = mux(_T_677, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_679 = bits(buf_data[0], 23, 16) @[lsu_bus_buffer.scala 172:78] + node _T_680 = and(_T_678, _T_679) @[lsu_bus_buffer.scala 172:65] + node _T_681 = bits(ld_byte_hitvecfn_hi[2], 1, 1) @[lsu_bus_buffer.scala 172:60] + node _T_682 = bits(_T_681, 0, 0) @[Bitwise.scala 72:15] + node _T_683 = mux(_T_682, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_684 = bits(buf_data[1], 23, 16) @[lsu_bus_buffer.scala 172:78] + node _T_685 = and(_T_683, _T_684) @[lsu_bus_buffer.scala 172:65] + node _T_686 = bits(ld_byte_hitvecfn_hi[2], 2, 2) @[lsu_bus_buffer.scala 172:60] + node _T_687 = bits(_T_686, 0, 0) @[Bitwise.scala 72:15] + node _T_688 = mux(_T_687, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_689 = bits(buf_data[2], 23, 16) @[lsu_bus_buffer.scala 172:78] + node _T_690 = and(_T_688, _T_689) @[lsu_bus_buffer.scala 172:65] + node _T_691 = bits(ld_byte_hitvecfn_hi[2], 3, 3) @[lsu_bus_buffer.scala 172:60] + node _T_692 = bits(_T_691, 0, 0) @[Bitwise.scala 72:15] + node _T_693 = mux(_T_692, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_694 = bits(buf_data[3], 23, 16) @[lsu_bus_buffer.scala 172:78] + node _T_695 = and(_T_693, _T_694) @[lsu_bus_buffer.scala 172:65] + node _T_696 = or(_T_680, _T_685) @[lsu_bus_buffer.scala 172:97] + node _T_697 = or(_T_696, _T_690) @[lsu_bus_buffer.scala 172:97] + node _T_698 = or(_T_697, _T_695) @[lsu_bus_buffer.scala 172:97] + node _T_699 = bits(ld_byte_hitvecfn_hi[1], 0, 0) @[lsu_bus_buffer.scala 173:60] + node _T_700 = bits(_T_699, 0, 0) @[Bitwise.scala 72:15] + node _T_701 = mux(_T_700, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_702 = bits(buf_data[0], 15, 8) @[lsu_bus_buffer.scala 173:78] + node _T_703 = and(_T_701, _T_702) @[lsu_bus_buffer.scala 173:65] + node _T_704 = bits(ld_byte_hitvecfn_hi[1], 1, 1) @[lsu_bus_buffer.scala 173:60] + node _T_705 = bits(_T_704, 0, 0) @[Bitwise.scala 72:15] + node _T_706 = mux(_T_705, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_707 = bits(buf_data[1], 15, 8) @[lsu_bus_buffer.scala 173:78] + node _T_708 = and(_T_706, _T_707) @[lsu_bus_buffer.scala 173:65] + node _T_709 = bits(ld_byte_hitvecfn_hi[1], 2, 2) @[lsu_bus_buffer.scala 173:60] + node _T_710 = bits(_T_709, 0, 0) @[Bitwise.scala 72:15] + node _T_711 = mux(_T_710, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_712 = bits(buf_data[2], 15, 8) @[lsu_bus_buffer.scala 173:78] + node _T_713 = and(_T_711, _T_712) @[lsu_bus_buffer.scala 173:65] + node _T_714 = bits(ld_byte_hitvecfn_hi[1], 3, 3) @[lsu_bus_buffer.scala 173:60] + node _T_715 = bits(_T_714, 0, 0) @[Bitwise.scala 72:15] + node _T_716 = mux(_T_715, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_717 = bits(buf_data[3], 15, 8) @[lsu_bus_buffer.scala 173:78] + node _T_718 = and(_T_716, _T_717) @[lsu_bus_buffer.scala 173:65] + node _T_719 = or(_T_703, _T_708) @[lsu_bus_buffer.scala 173:97] + node _T_720 = or(_T_719, _T_713) @[lsu_bus_buffer.scala 173:97] + node _T_721 = or(_T_720, _T_718) @[lsu_bus_buffer.scala 173:97] + node _T_722 = bits(ld_byte_hitvecfn_hi[0], 0, 0) @[lsu_bus_buffer.scala 174:60] + node _T_723 = bits(_T_722, 0, 0) @[Bitwise.scala 72:15] + node _T_724 = mux(_T_723, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_725 = bits(buf_data[0], 7, 0) @[lsu_bus_buffer.scala 174:78] + node _T_726 = and(_T_724, _T_725) @[lsu_bus_buffer.scala 174:65] + node _T_727 = bits(ld_byte_hitvecfn_hi[0], 1, 1) @[lsu_bus_buffer.scala 174:60] + node _T_728 = bits(_T_727, 0, 0) @[Bitwise.scala 72:15] + node _T_729 = mux(_T_728, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_730 = bits(buf_data[1], 7, 0) @[lsu_bus_buffer.scala 174:78] + node _T_731 = and(_T_729, _T_730) @[lsu_bus_buffer.scala 174:65] + node _T_732 = bits(ld_byte_hitvecfn_hi[0], 2, 2) @[lsu_bus_buffer.scala 174:60] + node _T_733 = bits(_T_732, 0, 0) @[Bitwise.scala 72:15] + node _T_734 = mux(_T_733, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_735 = bits(buf_data[2], 7, 0) @[lsu_bus_buffer.scala 174:78] + node _T_736 = and(_T_734, _T_735) @[lsu_bus_buffer.scala 174:65] + node _T_737 = bits(ld_byte_hitvecfn_hi[0], 3, 3) @[lsu_bus_buffer.scala 174:60] + node _T_738 = bits(_T_737, 0, 0) @[Bitwise.scala 72:15] + node _T_739 = mux(_T_738, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_740 = bits(buf_data[3], 7, 0) @[lsu_bus_buffer.scala 174:78] + node _T_741 = and(_T_739, _T_740) @[lsu_bus_buffer.scala 174:65] + node _T_742 = or(_T_726, _T_731) @[lsu_bus_buffer.scala 174:97] + node _T_743 = or(_T_742, _T_736) @[lsu_bus_buffer.scala 174:97] + node _T_744 = or(_T_743, _T_741) @[lsu_bus_buffer.scala 174:97] + node _T_745 = cat(_T_721, _T_744) @[Cat.scala 29:58] + node _T_746 = cat(_T_675, _T_698) @[Cat.scala 29:58] + node _T_747 = cat(_T_746, _T_745) @[Cat.scala 29:58] + node _T_748 = and(ld_fwddata_buf_hi_initial, ibuf_data) @[lsu_bus_buffer.scala 175:32] + node _T_749 = or(_T_747, _T_748) @[lsu_bus_buffer.scala 174:103] + io.ld_fwddata_buf_hi <= _T_749 @[lsu_bus_buffer.scala 171:24] + node bus_coalescing_disable = or(io.tlu_busbuff.dec_tlu_wb_coalescing_disable, UInt<1>("h00")) @[lsu_bus_buffer.scala 177:77] + node _T_750 = mux(io.lsu_pkt_r.bits.by, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_751 = mux(io.lsu_pkt_r.bits.half, UInt<4>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_752 = mux(io.lsu_pkt_r.bits.word, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_753 = or(_T_750, _T_751) @[Mux.scala 27:72] + node _T_754 = or(_T_753, _T_752) @[Mux.scala 27:72] + wire ldst_byteen_r : UInt<4> @[Mux.scala 27:72] + ldst_byteen_r <= _T_754 @[Mux.scala 27:72] + node _T_755 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 182:50] + node _T_756 = eq(_T_755, UInt<1>("h00")) @[lsu_bus_buffer.scala 182:55] + node _T_757 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 183:19] + node _T_758 = eq(_T_757, UInt<1>("h01")) @[lsu_bus_buffer.scala 183:24] + node _T_759 = bits(ldst_byteen_r, 3, 3) @[lsu_bus_buffer.scala 183:60] + node _T_760 = cat(UInt<3>("h00"), _T_759) @[Cat.scala 29:58] + node _T_761 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 184:19] + node _T_762 = eq(_T_761, UInt<2>("h02")) @[lsu_bus_buffer.scala 184:24] + node _T_763 = bits(ldst_byteen_r, 3, 2) @[lsu_bus_buffer.scala 184:60] + node _T_764 = cat(UInt<2>("h00"), _T_763) @[Cat.scala 29:58] + node _T_765 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 185:19] + node _T_766 = eq(_T_765, UInt<2>("h03")) @[lsu_bus_buffer.scala 185:24] + node _T_767 = bits(ldst_byteen_r, 3, 1) @[lsu_bus_buffer.scala 185:60] + node _T_768 = cat(UInt<1>("h00"), _T_767) @[Cat.scala 29:58] + node _T_769 = mux(_T_756, UInt<4>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_770 = mux(_T_758, _T_760, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_771 = mux(_T_762, _T_764, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_772 = mux(_T_766, _T_768, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_773 = or(_T_769, _T_770) @[Mux.scala 27:72] + node _T_774 = or(_T_773, _T_771) @[Mux.scala 27:72] + node _T_775 = or(_T_774, _T_772) @[Mux.scala 27:72] + wire ldst_byteen_hi_r : UInt<4> @[Mux.scala 27:72] + ldst_byteen_hi_r <= _T_775 @[Mux.scala 27:72] + node _T_776 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 187:50] + node _T_777 = eq(_T_776, UInt<1>("h00")) @[lsu_bus_buffer.scala 187:55] + node _T_778 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 188:19] + node _T_779 = eq(_T_778, UInt<1>("h01")) @[lsu_bus_buffer.scala 188:24] + node _T_780 = bits(ldst_byteen_r, 2, 0) @[lsu_bus_buffer.scala 188:50] + node _T_781 = cat(_T_780, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_782 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 189:19] + node _T_783 = eq(_T_782, UInt<2>("h02")) @[lsu_bus_buffer.scala 189:24] + node _T_784 = bits(ldst_byteen_r, 1, 0) @[lsu_bus_buffer.scala 189:50] + node _T_785 = cat(_T_784, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_786 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 190:19] + node _T_787 = eq(_T_786, UInt<2>("h03")) @[lsu_bus_buffer.scala 190:24] + node _T_788 = bits(ldst_byteen_r, 0, 0) @[lsu_bus_buffer.scala 190:50] + node _T_789 = cat(_T_788, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_790 = mux(_T_777, ldst_byteen_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_791 = mux(_T_779, _T_781, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_792 = mux(_T_783, _T_785, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_793 = mux(_T_787, _T_789, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_794 = or(_T_790, _T_791) @[Mux.scala 27:72] + node _T_795 = or(_T_794, _T_792) @[Mux.scala 27:72] + node _T_796 = or(_T_795, _T_793) @[Mux.scala 27:72] + wire ldst_byteen_lo_r : UInt<4> @[Mux.scala 27:72] + ldst_byteen_lo_r <= _T_796 @[Mux.scala 27:72] + node _T_797 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 192:49] + node _T_798 = eq(_T_797, UInt<1>("h00")) @[lsu_bus_buffer.scala 192:54] + node _T_799 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 193:19] + node _T_800 = eq(_T_799, UInt<1>("h01")) @[lsu_bus_buffer.scala 193:24] + node _T_801 = bits(io.store_data_r, 31, 24) @[lsu_bus_buffer.scala 193:64] + node _T_802 = cat(UInt<24>("h00"), _T_801) @[Cat.scala 29:58] + node _T_803 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 194:19] + node _T_804 = eq(_T_803, UInt<2>("h02")) @[lsu_bus_buffer.scala 194:24] + node _T_805 = bits(io.store_data_r, 31, 16) @[lsu_bus_buffer.scala 194:63] + node _T_806 = cat(UInt<16>("h00"), _T_805) @[Cat.scala 29:58] + node _T_807 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 195:19] + node _T_808 = eq(_T_807, UInt<2>("h03")) @[lsu_bus_buffer.scala 195:24] + node _T_809 = bits(io.store_data_r, 31, 8) @[lsu_bus_buffer.scala 195:62] + node _T_810 = cat(UInt<8>("h00"), _T_809) @[Cat.scala 29:58] + node _T_811 = mux(_T_798, UInt<32>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_812 = mux(_T_800, _T_802, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_813 = mux(_T_804, _T_806, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_814 = mux(_T_808, _T_810, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_815 = or(_T_811, _T_812) @[Mux.scala 27:72] + node _T_816 = or(_T_815, _T_813) @[Mux.scala 27:72] + node _T_817 = or(_T_816, _T_814) @[Mux.scala 27:72] + wire store_data_hi_r : UInt<32> @[Mux.scala 27:72] + store_data_hi_r <= _T_817 @[Mux.scala 27:72] + node _T_818 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 197:49] + node _T_819 = eq(_T_818, UInt<1>("h00")) @[lsu_bus_buffer.scala 197:54] + node _T_820 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 198:19] + node _T_821 = eq(_T_820, UInt<1>("h01")) @[lsu_bus_buffer.scala 198:24] + node _T_822 = bits(io.store_data_r, 23, 0) @[lsu_bus_buffer.scala 198:52] + node _T_823 = cat(_T_822, UInt<8>("h00")) @[Cat.scala 29:58] + node _T_824 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 199:19] + node _T_825 = eq(_T_824, UInt<2>("h02")) @[lsu_bus_buffer.scala 199:24] + node _T_826 = bits(io.store_data_r, 15, 0) @[lsu_bus_buffer.scala 199:52] + node _T_827 = cat(_T_826, UInt<16>("h00")) @[Cat.scala 29:58] + node _T_828 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 200:19] + node _T_829 = eq(_T_828, UInt<2>("h03")) @[lsu_bus_buffer.scala 200:24] + node _T_830 = bits(io.store_data_r, 7, 0) @[lsu_bus_buffer.scala 200:52] + node _T_831 = cat(_T_830, UInt<24>("h00")) @[Cat.scala 29:58] + node _T_832 = mux(_T_819, io.store_data_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_833 = mux(_T_821, _T_823, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_834 = mux(_T_825, _T_827, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_835 = mux(_T_829, _T_831, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_836 = or(_T_832, _T_833) @[Mux.scala 27:72] + node _T_837 = or(_T_836, _T_834) @[Mux.scala 27:72] + node _T_838 = or(_T_837, _T_835) @[Mux.scala 27:72] + wire store_data_lo_r : UInt<32> @[Mux.scala 27:72] + store_data_lo_r <= _T_838 @[Mux.scala 27:72] + node _T_839 = bits(io.lsu_addr_r, 3, 3) @[lsu_bus_buffer.scala 203:36] + node _T_840 = bits(io.end_addr_r, 3, 3) @[lsu_bus_buffer.scala 203:57] + node ldst_samedw_r = eq(_T_839, _T_840) @[lsu_bus_buffer.scala 203:40] + node _T_841 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 204:72] + node _T_842 = eq(_T_841, UInt<1>("h00")) @[lsu_bus_buffer.scala 204:79] + node _T_843 = bits(io.lsu_addr_r, 0, 0) @[lsu_bus_buffer.scala 205:45] + node _T_844 = eq(_T_843, UInt<1>("h00")) @[lsu_bus_buffer.scala 205:31] + node _T_845 = mux(io.lsu_pkt_r.bits.word, _T_842, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_846 = mux(io.lsu_pkt_r.bits.half, _T_844, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_847 = mux(io.lsu_pkt_r.bits.by, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_848 = or(_T_845, _T_846) @[Mux.scala 27:72] + node _T_849 = or(_T_848, _T_847) @[Mux.scala 27:72] + wire is_aligned_r : UInt<1> @[Mux.scala 27:72] + is_aligned_r <= _T_849 @[Mux.scala 27:72] + node _T_850 = or(io.lsu_pkt_r.bits.load, io.no_word_merge_r) @[lsu_bus_buffer.scala 207:60] + node _T_851 = and(io.lsu_busreq_r, _T_850) @[lsu_bus_buffer.scala 207:34] + node _T_852 = eq(ibuf_valid, UInt<1>("h00")) @[lsu_bus_buffer.scala 207:84] + node ibuf_byp = and(_T_851, _T_852) @[lsu_bus_buffer.scala 207:82] + node _T_853 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 208:36] + node _T_854 = eq(ibuf_byp, UInt<1>("h00")) @[lsu_bus_buffer.scala 208:56] + node ibuf_wr_en = and(_T_853, _T_854) @[lsu_bus_buffer.scala 208:54] + wire ibuf_drain_vld : UInt<1> + ibuf_drain_vld <= UInt<1>("h00") + node _T_855 = eq(ibuf_wr_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 210:36] + node _T_856 = and(ibuf_drain_vld, _T_855) @[lsu_bus_buffer.scala 210:34] + node ibuf_rst = or(_T_856, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 210:49] + node _T_857 = eq(io.lsu_busreq_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 211:44] + node _T_858 = and(io.lsu_busreq_m, _T_857) @[lsu_bus_buffer.scala 211:42] + node _T_859 = and(_T_858, ibuf_valid) @[lsu_bus_buffer.scala 211:61] + node _T_860 = bits(ibuf_addr, 31, 2) @[lsu_bus_buffer.scala 211:112] + node _T_861 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 211:137] + node _T_862 = neq(_T_860, _T_861) @[lsu_bus_buffer.scala 211:120] + node _T_863 = or(io.lsu_pkt_m.bits.load, _T_862) @[lsu_bus_buffer.scala 211:100] + node ibuf_force_drain = and(_T_859, _T_863) @[lsu_bus_buffer.scala 211:74] + wire ibuf_sideeffect : UInt<1> + ibuf_sideeffect <= UInt<1>("h00") + wire ibuf_timer : UInt<3> + ibuf_timer <= UInt<1>("h00") + wire ibuf_merge_en : UInt<1> + ibuf_merge_en <= UInt<1>("h00") + wire ibuf_merge_in : UInt<1> + ibuf_merge_in <= UInt<1>("h00") + node _T_864 = eq(ibuf_timer, UInt<3>("h07")) @[lsu_bus_buffer.scala 216:62] + node _T_865 = or(ibuf_wr_en, _T_864) @[lsu_bus_buffer.scala 216:48] + node _T_866 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 216:98] + node _T_867 = eq(_T_866, UInt<1>("h00")) @[lsu_bus_buffer.scala 216:82] + node _T_868 = and(_T_865, _T_867) @[lsu_bus_buffer.scala 216:80] + node _T_869 = or(_T_868, ibuf_byp) @[lsu_bus_buffer.scala 217:5] + node _T_870 = or(_T_869, ibuf_force_drain) @[lsu_bus_buffer.scala 217:16] + node _T_871 = or(_T_870, ibuf_sideeffect) @[lsu_bus_buffer.scala 217:35] + node _T_872 = eq(ibuf_write, UInt<1>("h00")) @[lsu_bus_buffer.scala 217:55] + node _T_873 = or(_T_871, _T_872) @[lsu_bus_buffer.scala 217:53] + node _T_874 = or(_T_873, bus_coalescing_disable) @[lsu_bus_buffer.scala 217:67] + node _T_875 = and(ibuf_valid, _T_874) @[lsu_bus_buffer.scala 216:32] + ibuf_drain_vld <= _T_875 @[lsu_bus_buffer.scala 216:18] + wire ibuf_tag : UInt<2> + ibuf_tag <= UInt<1>("h00") + wire WrPtr1_r : UInt<2> + WrPtr1_r <= UInt<1>("h00") + wire WrPtr0_r : UInt<2> + WrPtr0_r <= UInt<1>("h00") + node _T_876 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 222:39] + node _T_877 = mux(io.ldst_dual_r, WrPtr1_r, WrPtr0_r) @[lsu_bus_buffer.scala 222:69] + node ibuf_tag_in = mux(_T_876, ibuf_tag, _T_877) @[lsu_bus_buffer.scala 222:24] + node ibuf_sz_in = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58] + node ibuf_addr_in = mux(io.ldst_dual_r, io.end_addr_r, io.lsu_addr_r) @[lsu_bus_buffer.scala 225:25] + node _T_878 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 226:42] + node _T_879 = bits(ibuf_byteen, 3, 0) @[lsu_bus_buffer.scala 226:70] + node _T_880 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 226:95] + node _T_881 = or(_T_879, _T_880) @[lsu_bus_buffer.scala 226:77] + node _T_882 = bits(ldst_byteen_hi_r, 3, 0) @[lsu_bus_buffer.scala 227:41] + node _T_883 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 227:65] + node _T_884 = mux(io.ldst_dual_r, _T_882, _T_883) @[lsu_bus_buffer.scala 227:8] + node ibuf_byteen_in = mux(_T_878, _T_881, _T_884) @[lsu_bus_buffer.scala 226:27] + node _T_885 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 230:61] + node _T_886 = bits(ldst_byteen_lo_r, 0, 0) @[lsu_bus_buffer.scala 231:25] + node _T_887 = bits(store_data_lo_r, 7, 0) @[lsu_bus_buffer.scala 231:45] + node _T_888 = bits(ibuf_data, 7, 0) @[lsu_bus_buffer.scala 231:76] + node _T_889 = mux(_T_886, _T_887, _T_888) @[lsu_bus_buffer.scala 231:8] + node _T_890 = bits(store_data_hi_r, 7, 0) @[lsu_bus_buffer.scala 232:40] + node _T_891 = bits(store_data_lo_r, 7, 0) @[lsu_bus_buffer.scala 232:77] + node _T_892 = mux(io.ldst_dual_r, _T_890, _T_891) @[lsu_bus_buffer.scala 232:8] + node _T_893 = mux(_T_885, _T_889, _T_892) @[lsu_bus_buffer.scala 230:46] + node _T_894 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 230:61] + node _T_895 = bits(ldst_byteen_lo_r, 1, 1) @[lsu_bus_buffer.scala 231:25] + node _T_896 = bits(store_data_lo_r, 15, 8) @[lsu_bus_buffer.scala 231:45] + node _T_897 = bits(ibuf_data, 15, 8) @[lsu_bus_buffer.scala 231:76] + node _T_898 = mux(_T_895, _T_896, _T_897) @[lsu_bus_buffer.scala 231:8] + node _T_899 = bits(store_data_hi_r, 15, 8) @[lsu_bus_buffer.scala 232:40] + node _T_900 = bits(store_data_lo_r, 15, 8) @[lsu_bus_buffer.scala 232:77] + node _T_901 = mux(io.ldst_dual_r, _T_899, _T_900) @[lsu_bus_buffer.scala 232:8] + node _T_902 = mux(_T_894, _T_898, _T_901) @[lsu_bus_buffer.scala 230:46] + node _T_903 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 230:61] + node _T_904 = bits(ldst_byteen_lo_r, 2, 2) @[lsu_bus_buffer.scala 231:25] + node _T_905 = bits(store_data_lo_r, 23, 16) @[lsu_bus_buffer.scala 231:45] + node _T_906 = bits(ibuf_data, 23, 16) @[lsu_bus_buffer.scala 231:76] + node _T_907 = mux(_T_904, _T_905, _T_906) @[lsu_bus_buffer.scala 231:8] + node _T_908 = bits(store_data_hi_r, 23, 16) @[lsu_bus_buffer.scala 232:40] + node _T_909 = bits(store_data_lo_r, 23, 16) @[lsu_bus_buffer.scala 232:77] + node _T_910 = mux(io.ldst_dual_r, _T_908, _T_909) @[lsu_bus_buffer.scala 232:8] + node _T_911 = mux(_T_903, _T_907, _T_910) @[lsu_bus_buffer.scala 230:46] + node _T_912 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 230:61] + node _T_913 = bits(ldst_byteen_lo_r, 3, 3) @[lsu_bus_buffer.scala 231:25] + node _T_914 = bits(store_data_lo_r, 31, 24) @[lsu_bus_buffer.scala 231:45] + node _T_915 = bits(ibuf_data, 31, 24) @[lsu_bus_buffer.scala 231:76] + node _T_916 = mux(_T_913, _T_914, _T_915) @[lsu_bus_buffer.scala 231:8] + node _T_917 = bits(store_data_hi_r, 31, 24) @[lsu_bus_buffer.scala 232:40] + node _T_918 = bits(store_data_lo_r, 31, 24) @[lsu_bus_buffer.scala 232:77] + node _T_919 = mux(io.ldst_dual_r, _T_917, _T_918) @[lsu_bus_buffer.scala 232:8] + node _T_920 = mux(_T_912, _T_916, _T_919) @[lsu_bus_buffer.scala 230:46] + node _T_921 = cat(_T_920, _T_911) @[Cat.scala 29:58] + node _T_922 = cat(_T_921, _T_902) @[Cat.scala 29:58] + node ibuf_data_in = cat(_T_922, _T_893) @[Cat.scala 29:58] + node _T_923 = lt(ibuf_timer, UInt<3>("h07")) @[lsu_bus_buffer.scala 233:59] + node _T_924 = bits(_T_923, 0, 0) @[lsu_bus_buffer.scala 233:79] + node _T_925 = add(ibuf_timer, UInt<1>("h01")) @[lsu_bus_buffer.scala 233:93] + node _T_926 = tail(_T_925, 1) @[lsu_bus_buffer.scala 233:93] + node _T_927 = mux(_T_924, _T_926, ibuf_timer) @[lsu_bus_buffer.scala 233:47] + node ibuf_timer_in = mux(ibuf_wr_en, UInt<1>("h00"), _T_927) @[lsu_bus_buffer.scala 233:26] + node _T_928 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 235:36] + node _T_929 = and(_T_928, io.lsu_pkt_r.bits.store) @[lsu_bus_buffer.scala 235:54] + node _T_930 = and(_T_929, ibuf_valid) @[lsu_bus_buffer.scala 235:80] + node _T_931 = and(_T_930, ibuf_write) @[lsu_bus_buffer.scala 235:93] + node _T_932 = bits(io.lsu_addr_r, 31, 2) @[lsu_bus_buffer.scala 235:122] + node _T_933 = bits(ibuf_addr, 31, 2) @[lsu_bus_buffer.scala 235:142] + node _T_934 = eq(_T_932, _T_933) @[lsu_bus_buffer.scala 235:129] + node _T_935 = and(_T_931, _T_934) @[lsu_bus_buffer.scala 235:106] + node _T_936 = eq(io.is_sideeffects_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 235:152] + node _T_937 = and(_T_935, _T_936) @[lsu_bus_buffer.scala 235:150] + node _T_938 = eq(bus_coalescing_disable, UInt<1>("h00")) @[lsu_bus_buffer.scala 235:175] + node _T_939 = and(_T_937, _T_938) @[lsu_bus_buffer.scala 235:173] + ibuf_merge_en <= _T_939 @[lsu_bus_buffer.scala 235:17] + node _T_940 = eq(io.ldst_dual_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 236:20] + ibuf_merge_in <= _T_940 @[lsu_bus_buffer.scala 236:17] + node _T_941 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 237:65] + node _T_942 = and(ibuf_merge_en, _T_941) @[lsu_bus_buffer.scala 237:63] + node _T_943 = bits(ibuf_byteen, 0, 0) @[lsu_bus_buffer.scala 237:92] + node _T_944 = bits(ldst_byteen_lo_r, 0, 0) @[lsu_bus_buffer.scala 237:114] + node _T_945 = or(_T_943, _T_944) @[lsu_bus_buffer.scala 237:96] + node _T_946 = bits(ibuf_byteen, 0, 0) @[lsu_bus_buffer.scala 237:130] + node _T_947 = mux(_T_942, _T_945, _T_946) @[lsu_bus_buffer.scala 237:48] + node _T_948 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 237:65] + node _T_949 = and(ibuf_merge_en, _T_948) @[lsu_bus_buffer.scala 237:63] + node _T_950 = bits(ibuf_byteen, 1, 1) @[lsu_bus_buffer.scala 237:92] + node _T_951 = bits(ldst_byteen_lo_r, 1, 1) @[lsu_bus_buffer.scala 237:114] + node _T_952 = or(_T_950, _T_951) @[lsu_bus_buffer.scala 237:96] + node _T_953 = bits(ibuf_byteen, 1, 1) @[lsu_bus_buffer.scala 237:130] + node _T_954 = mux(_T_949, _T_952, _T_953) @[lsu_bus_buffer.scala 237:48] + node _T_955 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 237:65] + node _T_956 = and(ibuf_merge_en, _T_955) @[lsu_bus_buffer.scala 237:63] + node _T_957 = bits(ibuf_byteen, 2, 2) @[lsu_bus_buffer.scala 237:92] + node _T_958 = bits(ldst_byteen_lo_r, 2, 2) @[lsu_bus_buffer.scala 237:114] + node _T_959 = or(_T_957, _T_958) @[lsu_bus_buffer.scala 237:96] + node _T_960 = bits(ibuf_byteen, 2, 2) @[lsu_bus_buffer.scala 237:130] + node _T_961 = mux(_T_956, _T_959, _T_960) @[lsu_bus_buffer.scala 237:48] + node _T_962 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 237:65] + node _T_963 = and(ibuf_merge_en, _T_962) @[lsu_bus_buffer.scala 237:63] + node _T_964 = bits(ibuf_byteen, 3, 3) @[lsu_bus_buffer.scala 237:92] + node _T_965 = bits(ldst_byteen_lo_r, 3, 3) @[lsu_bus_buffer.scala 237:114] + node _T_966 = or(_T_964, _T_965) @[lsu_bus_buffer.scala 237:96] + node _T_967 = bits(ibuf_byteen, 3, 3) @[lsu_bus_buffer.scala 237:130] + node _T_968 = mux(_T_963, _T_966, _T_967) @[lsu_bus_buffer.scala 237:48] + node _T_969 = cat(_T_968, _T_961) @[Cat.scala 29:58] + node _T_970 = cat(_T_969, _T_954) @[Cat.scala 29:58] + node ibuf_byteen_out = cat(_T_970, _T_947) @[Cat.scala 29:58] + node _T_971 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 238:62] + node _T_972 = and(ibuf_merge_en, _T_971) @[lsu_bus_buffer.scala 238:60] + node _T_973 = bits(ldst_byteen_lo_r, 0, 0) @[lsu_bus_buffer.scala 238:98] + node _T_974 = bits(store_data_lo_r, 7, 0) @[lsu_bus_buffer.scala 238:118] + node _T_975 = bits(ibuf_data, 7, 0) @[lsu_bus_buffer.scala 238:143] + node _T_976 = mux(_T_973, _T_974, _T_975) @[lsu_bus_buffer.scala 238:81] + node _T_977 = bits(ibuf_data, 7, 0) @[lsu_bus_buffer.scala 238:169] + node _T_978 = mux(_T_972, _T_976, _T_977) @[lsu_bus_buffer.scala 238:45] + node _T_979 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 238:62] + node _T_980 = and(ibuf_merge_en, _T_979) @[lsu_bus_buffer.scala 238:60] + node _T_981 = bits(ldst_byteen_lo_r, 1, 1) @[lsu_bus_buffer.scala 238:98] + node _T_982 = bits(store_data_lo_r, 15, 8) @[lsu_bus_buffer.scala 238:118] + node _T_983 = bits(ibuf_data, 15, 8) @[lsu_bus_buffer.scala 238:143] + node _T_984 = mux(_T_981, _T_982, _T_983) @[lsu_bus_buffer.scala 238:81] + node _T_985 = bits(ibuf_data, 15, 8) @[lsu_bus_buffer.scala 238:169] + node _T_986 = mux(_T_980, _T_984, _T_985) @[lsu_bus_buffer.scala 238:45] + node _T_987 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 238:62] + node _T_988 = and(ibuf_merge_en, _T_987) @[lsu_bus_buffer.scala 238:60] + node _T_989 = bits(ldst_byteen_lo_r, 2, 2) @[lsu_bus_buffer.scala 238:98] + node _T_990 = bits(store_data_lo_r, 23, 16) @[lsu_bus_buffer.scala 238:118] + node _T_991 = bits(ibuf_data, 23, 16) @[lsu_bus_buffer.scala 238:143] + node _T_992 = mux(_T_989, _T_990, _T_991) @[lsu_bus_buffer.scala 238:81] + node _T_993 = bits(ibuf_data, 23, 16) @[lsu_bus_buffer.scala 238:169] + node _T_994 = mux(_T_988, _T_992, _T_993) @[lsu_bus_buffer.scala 238:45] + node _T_995 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 238:62] + node _T_996 = and(ibuf_merge_en, _T_995) @[lsu_bus_buffer.scala 238:60] + node _T_997 = bits(ldst_byteen_lo_r, 3, 3) @[lsu_bus_buffer.scala 238:98] + node _T_998 = bits(store_data_lo_r, 31, 24) @[lsu_bus_buffer.scala 238:118] + node _T_999 = bits(ibuf_data, 31, 24) @[lsu_bus_buffer.scala 238:143] + node _T_1000 = mux(_T_997, _T_998, _T_999) @[lsu_bus_buffer.scala 238:81] + node _T_1001 = bits(ibuf_data, 31, 24) @[lsu_bus_buffer.scala 238:169] + node _T_1002 = mux(_T_996, _T_1000, _T_1001) @[lsu_bus_buffer.scala 238:45] + node _T_1003 = cat(_T_1002, _T_994) @[Cat.scala 29:58] + node _T_1004 = cat(_T_1003, _T_986) @[Cat.scala 29:58] + node ibuf_data_out = cat(_T_1004, _T_978) @[Cat.scala 29:58] + node _T_1005 = mux(ibuf_wr_en, UInt<1>("h01"), ibuf_valid) @[lsu_bus_buffer.scala 240:58] + node _T_1006 = eq(ibuf_rst, UInt<1>("h00")) @[lsu_bus_buffer.scala 240:93] + node _T_1007 = and(_T_1005, _T_1006) @[lsu_bus_buffer.scala 240:91] + reg _T_1008 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 240:54] + _T_1008 <= _T_1007 @[lsu_bus_buffer.scala 240:54] + ibuf_valid <= _T_1008 @[lsu_bus_buffer.scala 240:14] + reg _T_1009 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + _T_1009 <= ibuf_tag_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ibuf_tag <= _T_1009 @[lsu_bus_buffer.scala 241:12] + reg ibuf_dualtag : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_dualtag <= WrPtr0_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg ibuf_dual : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_dual <= io.ldst_dual_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg ibuf_samedw : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_samedw <= ldst_samedw_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg ibuf_nomerge : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_nomerge <= io.no_dword_merge_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg _T_1010 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + _T_1010 <= io.is_sideeffects_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ibuf_sideeffect <= _T_1010 @[lsu_bus_buffer.scala 246:19] + reg ibuf_unsign : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_unsign <= io.lsu_pkt_r.bits.unsign @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg _T_1011 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + _T_1011 <= io.lsu_pkt_r.bits.store @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ibuf_write <= _T_1011 @[lsu_bus_buffer.scala 248:14] + reg ibuf_sz : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_sz <= ibuf_sz_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + inst rvclkhdr of rvclkhdr_24 @[lib.scala 368:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[lib.scala 370:18] + rvclkhdr.io.en <= ibuf_wr_en @[lib.scala 371:17] + rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_1012 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_1012 <= ibuf_addr_in @[lib.scala 374:16] + ibuf_addr <= _T_1012 @[lsu_bus_buffer.scala 250:13] + reg _T_1013 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + _T_1013 <= ibuf_byteen_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ibuf_byteen <= _T_1013 @[lsu_bus_buffer.scala 251:15] + inst rvclkhdr_1 of rvclkhdr_25 @[lib.scala 368:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_1.io.en <= ibuf_wr_en @[lib.scala 371:17] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_1014 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_1014 <= ibuf_data_in @[lib.scala 374:16] + ibuf_data <= _T_1014 @[lsu_bus_buffer.scala 252:13] + reg _T_1015 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 253:55] + _T_1015 <= ibuf_timer_in @[lsu_bus_buffer.scala 253:55] + ibuf_timer <= _T_1015 @[lsu_bus_buffer.scala 253:14] + wire buf_numvld_wrcmd_any : UInt<4> + buf_numvld_wrcmd_any <= UInt<1>("h00") + wire buf_numvld_cmd_any : UInt<4> + buf_numvld_cmd_any <= UInt<1>("h00") + wire obuf_wr_timer : UInt<3> + obuf_wr_timer <= UInt<1>("h00") + wire buf_nomerge : UInt<1>[4] @[lsu_bus_buffer.scala 257:25] + buf_nomerge[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 258:15] + buf_nomerge[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 258:15] + buf_nomerge[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 258:15] + buf_nomerge[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 258:15] + wire buf_sideeffect : UInt<4> + buf_sideeffect <= UInt<1>("h00") + wire obuf_force_wr_en : UInt<1> + obuf_force_wr_en <= UInt<1>("h00") + wire obuf_wr_en : UInt<1> + obuf_wr_en <= UInt<1>("h00") + node _T_1016 = eq(buf_numvld_wrcmd_any, UInt<1>("h01")) @[lsu_bus_buffer.scala 263:43] + node _T_1017 = eq(buf_numvld_cmd_any, UInt<1>("h01")) @[lsu_bus_buffer.scala 263:72] + node _T_1018 = and(_T_1016, _T_1017) @[lsu_bus_buffer.scala 263:51] + node _T_1019 = neq(obuf_wr_timer, UInt<3>("h07")) @[lsu_bus_buffer.scala 263:97] + node _T_1020 = and(_T_1018, _T_1019) @[lsu_bus_buffer.scala 263:80] + node _T_1021 = eq(bus_coalescing_disable, UInt<1>("h00")) @[lsu_bus_buffer.scala 264:5] + node _T_1022 = and(_T_1020, _T_1021) @[lsu_bus_buffer.scala 263:114] + node _T_1023 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 264:114] + node _T_1024 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 264:114] + node _T_1025 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 264:114] + node _T_1026 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 264:114] + node _T_1027 = mux(_T_1023, buf_nomerge[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1028 = mux(_T_1024, buf_nomerge[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1029 = mux(_T_1025, buf_nomerge[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1030 = mux(_T_1026, buf_nomerge[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1031 = or(_T_1027, _T_1028) @[Mux.scala 27:72] + node _T_1032 = or(_T_1031, _T_1029) @[Mux.scala 27:72] + node _T_1033 = or(_T_1032, _T_1030) @[Mux.scala 27:72] + wire _T_1034 : UInt<1> @[Mux.scala 27:72] + _T_1034 <= _T_1033 @[Mux.scala 27:72] + node _T_1035 = eq(_T_1034, UInt<1>("h00")) @[lsu_bus_buffer.scala 264:31] + node _T_1036 = and(_T_1022, _T_1035) @[lsu_bus_buffer.scala 264:29] + node _T_1037 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 265:88] + node _T_1038 = bits(buf_sideeffect, 0, 0) @[lsu_bus_buffer.scala 265:111] + node _T_1039 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 265:88] + node _T_1040 = bits(buf_sideeffect, 1, 1) @[lsu_bus_buffer.scala 265:111] + node _T_1041 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 265:88] + node _T_1042 = bits(buf_sideeffect, 2, 2) @[lsu_bus_buffer.scala 265:111] + node _T_1043 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 265:88] + node _T_1044 = bits(buf_sideeffect, 3, 3) @[lsu_bus_buffer.scala 265:111] + node _T_1045 = mux(_T_1037, _T_1038, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1046 = mux(_T_1039, _T_1040, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1047 = mux(_T_1041, _T_1042, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1048 = mux(_T_1043, _T_1044, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1049 = or(_T_1045, _T_1046) @[Mux.scala 27:72] + node _T_1050 = or(_T_1049, _T_1047) @[Mux.scala 27:72] + node _T_1051 = or(_T_1050, _T_1048) @[Mux.scala 27:72] + wire _T_1052 : UInt<1> @[Mux.scala 27:72] + _T_1052 <= _T_1051 @[Mux.scala 27:72] + node _T_1053 = eq(_T_1052, UInt<1>("h00")) @[lsu_bus_buffer.scala 265:5] + node _T_1054 = and(_T_1036, _T_1053) @[lsu_bus_buffer.scala 264:140] + node _T_1055 = eq(obuf_force_wr_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 265:119] + node obuf_wr_wait = and(_T_1054, _T_1055) @[lsu_bus_buffer.scala 265:117] + node _T_1056 = orr(buf_numvld_cmd_any) @[lsu_bus_buffer.scala 266:75] + node _T_1057 = lt(obuf_wr_timer, UInt<3>("h07")) @[lsu_bus_buffer.scala 266:95] + node _T_1058 = and(_T_1056, _T_1057) @[lsu_bus_buffer.scala 266:79] + node _T_1059 = add(obuf_wr_timer, UInt<1>("h01")) @[lsu_bus_buffer.scala 266:123] + node _T_1060 = tail(_T_1059, 1) @[lsu_bus_buffer.scala 266:123] + node _T_1061 = mux(_T_1058, _T_1060, obuf_wr_timer) @[lsu_bus_buffer.scala 266:55] + node obuf_wr_timer_in = mux(obuf_wr_en, UInt<3>("h00"), _T_1061) @[lsu_bus_buffer.scala 266:29] + node _T_1062 = eq(io.lsu_busreq_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 267:41] + node _T_1063 = and(io.lsu_busreq_m, _T_1062) @[lsu_bus_buffer.scala 267:39] + node _T_1064 = eq(ibuf_valid, UInt<1>("h00")) @[lsu_bus_buffer.scala 267:60] + node _T_1065 = and(_T_1063, _T_1064) @[lsu_bus_buffer.scala 267:58] + node _T_1066 = eq(buf_numvld_cmd_any, UInt<1>("h01")) @[lsu_bus_buffer.scala 267:93] + node _T_1067 = and(_T_1065, _T_1066) @[lsu_bus_buffer.scala 267:72] + node _T_1068 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 267:117] + node _T_1069 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 267:208] + node _T_1070 = bits(buf_addr[0], 31, 2) @[lsu_bus_buffer.scala 267:228] + node _T_1071 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 267:208] + node _T_1072 = bits(buf_addr[1], 31, 2) @[lsu_bus_buffer.scala 267:228] + node _T_1073 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 267:208] + node _T_1074 = bits(buf_addr[2], 31, 2) @[lsu_bus_buffer.scala 267:228] + node _T_1075 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 267:208] + node _T_1076 = bits(buf_addr[3], 31, 2) @[lsu_bus_buffer.scala 267:228] + node _T_1077 = mux(_T_1069, _T_1070, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1078 = mux(_T_1071, _T_1072, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1079 = mux(_T_1073, _T_1074, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1080 = mux(_T_1075, _T_1076, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1081 = or(_T_1077, _T_1078) @[Mux.scala 27:72] + node _T_1082 = or(_T_1081, _T_1079) @[Mux.scala 27:72] + node _T_1083 = or(_T_1082, _T_1080) @[Mux.scala 27:72] + wire _T_1084 : UInt<30> @[Mux.scala 27:72] + _T_1084 <= _T_1083 @[Mux.scala 27:72] + node _T_1085 = neq(_T_1068, _T_1084) @[lsu_bus_buffer.scala 267:123] + node _T_1086 = and(_T_1067, _T_1085) @[lsu_bus_buffer.scala 267:101] + obuf_force_wr_en <= _T_1086 @[lsu_bus_buffer.scala 267:20] + wire buf_numvld_pend_any : UInt<4> + buf_numvld_pend_any <= UInt<1>("h00") + node _T_1087 = eq(buf_numvld_pend_any, UInt<1>("h00")) @[lsu_bus_buffer.scala 269:53] + node _T_1088 = and(ibuf_byp, _T_1087) @[lsu_bus_buffer.scala 269:31] + node _T_1089 = eq(io.lsu_pkt_r.bits.store, UInt<1>("h00")) @[lsu_bus_buffer.scala 269:64] + node _T_1090 = or(_T_1089, io.no_dword_merge_r) @[lsu_bus_buffer.scala 269:89] + node ibuf_buf_byp = and(_T_1088, _T_1090) @[lsu_bus_buffer.scala 269:61] + wire bus_sideeffect_pend : UInt<1> + bus_sideeffect_pend <= UInt<1>("h00") + wire found_cmdptr0 : UInt<1> + found_cmdptr0 <= UInt<1>("h00") + wire buf_cmd_state_bus_en : UInt<1>[4] @[lsu_bus_buffer.scala 272:34] + buf_cmd_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 273:24] + buf_cmd_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 273:24] + buf_cmd_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 273:24] + buf_cmd_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 273:24] + wire buf_dual : UInt<1>[4] @[lsu_bus_buffer.scala 274:22] + buf_dual[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 275:12] + buf_dual[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 275:12] + buf_dual[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 275:12] + buf_dual[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 275:12] + wire buf_samedw : UInt<1>[4] @[lsu_bus_buffer.scala 276:24] + buf_samedw[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 277:14] + buf_samedw[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 277:14] + buf_samedw[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 277:14] + buf_samedw[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 277:14] + wire found_cmdptr1 : UInt<1> + found_cmdptr1 <= UInt<1>("h00") + wire bus_cmd_ready : UInt<1> + bus_cmd_ready <= UInt<1>("h00") + wire obuf_valid : UInt<1> + obuf_valid <= UInt<1>("h00") + wire obuf_nosend : UInt<1> + obuf_nosend <= UInt<1>("h00") + wire lsu_bus_cntr_overflow : UInt<1> + lsu_bus_cntr_overflow <= UInt<1>("h00") + wire bus_addr_match_pending : UInt<1> + bus_addr_match_pending <= UInt<1>("h00") + node _T_1091 = and(ibuf_buf_byp, io.lsu_commit_r) @[lsu_bus_buffer.scala 284:32] + node _T_1092 = and(io.is_sideeffects_r, bus_sideeffect_pend) @[lsu_bus_buffer.scala 284:74] + node _T_1093 = eq(_T_1092, UInt<1>("h00")) @[lsu_bus_buffer.scala 284:52] + node _T_1094 = and(_T_1091, _T_1093) @[lsu_bus_buffer.scala 284:50] + node _T_1095 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1096 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1097 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1098 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] + node _T_1099 = mux(_T_1095, buf_state[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1100 = mux(_T_1096, buf_state[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1101 = mux(_T_1097, buf_state[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1102 = mux(_T_1098, buf_state[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1103 = or(_T_1099, _T_1100) @[Mux.scala 27:72] + node _T_1104 = or(_T_1103, _T_1101) @[Mux.scala 27:72] + node _T_1105 = or(_T_1104, _T_1102) @[Mux.scala 27:72] + wire _T_1106 : UInt<3> @[Mux.scala 27:72] + _T_1106 <= _T_1105 @[Mux.scala 27:72] + node _T_1107 = eq(_T_1106, UInt<3>("h02")) @[lsu_bus_buffer.scala 285:36] + node _T_1108 = and(_T_1107, found_cmdptr0) @[lsu_bus_buffer.scala 285:47] + node _T_1109 = cat(buf_cmd_state_bus_en[3], buf_cmd_state_bus_en[2]) @[Cat.scala 29:58] + node _T_1110 = cat(_T_1109, buf_cmd_state_bus_en[1]) @[Cat.scala 29:58] + node _T_1111 = cat(_T_1110, buf_cmd_state_bus_en[0]) @[Cat.scala 29:58] + node _T_1112 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_1113 = bits(_T_1111, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_1114 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_1115 = bits(_T_1111, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_1116 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_1117 = bits(_T_1111, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_1118 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_1119 = bits(_T_1111, 3, 3) @[lsu_bus_buffer.scala 57:129] + node _T_1120 = mux(_T_1112, _T_1113, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1121 = mux(_T_1114, _T_1115, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1122 = mux(_T_1116, _T_1117, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1123 = mux(_T_1118, _T_1119, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1124 = or(_T_1120, _T_1121) @[Mux.scala 27:72] + node _T_1125 = or(_T_1124, _T_1122) @[Mux.scala 27:72] + node _T_1126 = or(_T_1125, _T_1123) @[Mux.scala 27:72] + wire _T_1127 : UInt<1> @[Mux.scala 27:72] + _T_1127 <= _T_1126 @[Mux.scala 27:72] + node _T_1128 = eq(_T_1127, UInt<1>("h00")) @[lsu_bus_buffer.scala 286:23] + node _T_1129 = and(_T_1108, _T_1128) @[lsu_bus_buffer.scala 286:21] + node _T_1130 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_1131 = bits(buf_sideeffect, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_1132 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_1133 = bits(buf_sideeffect, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_1134 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_1135 = bits(buf_sideeffect, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_1136 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_1137 = bits(buf_sideeffect, 3, 3) @[lsu_bus_buffer.scala 57:129] + node _T_1138 = mux(_T_1130, _T_1131, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1139 = mux(_T_1132, _T_1133, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1140 = mux(_T_1134, _T_1135, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1141 = mux(_T_1136, _T_1137, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1142 = or(_T_1138, _T_1139) @[Mux.scala 27:72] + node _T_1143 = or(_T_1142, _T_1140) @[Mux.scala 27:72] + node _T_1144 = or(_T_1143, _T_1141) @[Mux.scala 27:72] + wire _T_1145 : UInt<1> @[Mux.scala 27:72] + _T_1145 <= _T_1144 @[Mux.scala 27:72] + node _T_1146 = and(_T_1145, bus_sideeffect_pend) @[lsu_bus_buffer.scala 286:141] + node _T_1147 = eq(_T_1146, UInt<1>("h00")) @[lsu_bus_buffer.scala 286:105] + node _T_1148 = and(_T_1129, _T_1147) @[lsu_bus_buffer.scala 286:103] + node _T_1149 = cat(buf_dual[3], buf_dual[2]) @[Cat.scala 29:58] + node _T_1150 = cat(_T_1149, buf_dual[1]) @[Cat.scala 29:58] + node _T_1151 = cat(_T_1150, buf_dual[0]) @[Cat.scala 29:58] + node _T_1152 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_1153 = bits(_T_1151, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_1154 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_1155 = bits(_T_1151, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_1156 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_1157 = bits(_T_1151, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_1158 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_1159 = bits(_T_1151, 3, 3) @[lsu_bus_buffer.scala 57:129] + node _T_1160 = mux(_T_1152, _T_1153, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1161 = mux(_T_1154, _T_1155, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1162 = mux(_T_1156, _T_1157, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1163 = mux(_T_1158, _T_1159, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1164 = or(_T_1160, _T_1161) @[Mux.scala 27:72] + node _T_1165 = or(_T_1164, _T_1162) @[Mux.scala 27:72] + node _T_1166 = or(_T_1165, _T_1163) @[Mux.scala 27:72] + wire _T_1167 : UInt<1> @[Mux.scala 27:72] + _T_1167 <= _T_1166 @[Mux.scala 27:72] + node _T_1168 = cat(buf_samedw[3], buf_samedw[2]) @[Cat.scala 29:58] + node _T_1169 = cat(_T_1168, buf_samedw[1]) @[Cat.scala 29:58] + node _T_1170 = cat(_T_1169, buf_samedw[0]) @[Cat.scala 29:58] + node _T_1171 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_1172 = bits(_T_1170, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_1173 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_1174 = bits(_T_1170, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_1175 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_1176 = bits(_T_1170, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_1177 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_1178 = bits(_T_1170, 3, 3) @[lsu_bus_buffer.scala 57:129] + node _T_1179 = mux(_T_1171, _T_1172, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1180 = mux(_T_1173, _T_1174, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1181 = mux(_T_1175, _T_1176, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1182 = mux(_T_1177, _T_1178, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1183 = or(_T_1179, _T_1180) @[Mux.scala 27:72] + node _T_1184 = or(_T_1183, _T_1181) @[Mux.scala 27:72] + node _T_1185 = or(_T_1184, _T_1182) @[Mux.scala 27:72] + wire _T_1186 : UInt<1> @[Mux.scala 27:72] + _T_1186 <= _T_1185 @[Mux.scala 27:72] + node _T_1187 = and(_T_1167, _T_1186) @[lsu_bus_buffer.scala 287:77] + node _T_1188 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_1189 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_1190 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_1191 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_1192 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_1193 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_1194 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_1195 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 57:129] + node _T_1196 = mux(_T_1188, _T_1189, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1197 = mux(_T_1190, _T_1191, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1198 = mux(_T_1192, _T_1193, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1199 = mux(_T_1194, _T_1195, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1200 = or(_T_1196, _T_1197) @[Mux.scala 27:72] + node _T_1201 = or(_T_1200, _T_1198) @[Mux.scala 27:72] + node _T_1202 = or(_T_1201, _T_1199) @[Mux.scala 27:72] + wire _T_1203 : UInt<1> @[Mux.scala 27:72] + _T_1203 <= _T_1202 @[Mux.scala 27:72] + node _T_1204 = eq(_T_1203, UInt<1>("h00")) @[lsu_bus_buffer.scala 287:150] + node _T_1205 = and(_T_1187, _T_1204) @[lsu_bus_buffer.scala 287:148] + node _T_1206 = eq(_T_1205, UInt<1>("h00")) @[lsu_bus_buffer.scala 287:8] + node _T_1207 = or(_T_1206, found_cmdptr1) @[lsu_bus_buffer.scala 287:181] + node _T_1208 = cat(buf_nomerge[3], buf_nomerge[2]) @[Cat.scala 29:58] + node _T_1209 = cat(_T_1208, buf_nomerge[1]) @[Cat.scala 29:58] + node _T_1210 = cat(_T_1209, buf_nomerge[0]) @[Cat.scala 29:58] + node _T_1211 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_1212 = bits(_T_1210, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_1213 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_1214 = bits(_T_1210, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_1215 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_1216 = bits(_T_1210, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_1217 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_1218 = bits(_T_1210, 3, 3) @[lsu_bus_buffer.scala 57:129] + node _T_1219 = mux(_T_1211, _T_1212, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1220 = mux(_T_1213, _T_1214, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1221 = mux(_T_1215, _T_1216, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1222 = mux(_T_1217, _T_1218, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1223 = or(_T_1219, _T_1220) @[Mux.scala 27:72] + node _T_1224 = or(_T_1223, _T_1221) @[Mux.scala 27:72] + node _T_1225 = or(_T_1224, _T_1222) @[Mux.scala 27:72] + wire _T_1226 : UInt<1> @[Mux.scala 27:72] + _T_1226 <= _T_1225 @[Mux.scala 27:72] + node _T_1227 = or(_T_1207, _T_1226) @[lsu_bus_buffer.scala 287:197] + node _T_1228 = or(_T_1227, obuf_force_wr_en) @[lsu_bus_buffer.scala 287:269] + node _T_1229 = and(_T_1148, _T_1228) @[lsu_bus_buffer.scala 286:164] + node _T_1230 = or(_T_1094, _T_1229) @[lsu_bus_buffer.scala 284:98] + node _T_1231 = eq(obuf_valid, UInt<1>("h00")) @[lsu_bus_buffer.scala 288:48] + node _T_1232 = or(bus_cmd_ready, _T_1231) @[lsu_bus_buffer.scala 288:46] + node _T_1233 = or(_T_1232, obuf_nosend) @[lsu_bus_buffer.scala 288:60] + node _T_1234 = and(_T_1230, _T_1233) @[lsu_bus_buffer.scala 288:29] + node _T_1235 = eq(obuf_wr_wait, UInt<1>("h00")) @[lsu_bus_buffer.scala 288:77] + node _T_1236 = and(_T_1234, _T_1235) @[lsu_bus_buffer.scala 288:75] + node _T_1237 = eq(lsu_bus_cntr_overflow, UInt<1>("h00")) @[lsu_bus_buffer.scala 288:93] + node _T_1238 = and(_T_1236, _T_1237) @[lsu_bus_buffer.scala 288:91] + node _T_1239 = eq(bus_addr_match_pending, UInt<1>("h00")) @[lsu_bus_buffer.scala 288:118] + node _T_1240 = and(_T_1238, _T_1239) @[lsu_bus_buffer.scala 288:116] + node _T_1241 = and(_T_1240, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 288:142] + obuf_wr_en <= _T_1241 @[lsu_bus_buffer.scala 284:14] + wire bus_cmd_sent : UInt<1> + bus_cmd_sent <= UInt<1>("h00") + node _T_1242 = and(obuf_valid, obuf_nosend) @[lsu_bus_buffer.scala 290:47] + node _T_1243 = or(bus_cmd_sent, _T_1242) @[lsu_bus_buffer.scala 290:33] + node _T_1244 = eq(obuf_wr_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 290:65] + node _T_1245 = and(_T_1243, _T_1244) @[lsu_bus_buffer.scala 290:63] + node _T_1246 = and(_T_1245, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 290:77] + node obuf_rst = or(_T_1246, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 290:98] + node _T_1247 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_1248 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_1249 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_1250 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_1251 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_1252 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_1253 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_1254 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 57:129] + node _T_1255 = mux(_T_1247, _T_1248, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1256 = mux(_T_1249, _T_1250, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1257 = mux(_T_1251, _T_1252, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1258 = mux(_T_1253, _T_1254, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1259 = or(_T_1255, _T_1256) @[Mux.scala 27:72] + node _T_1260 = or(_T_1259, _T_1257) @[Mux.scala 27:72] + node _T_1261 = or(_T_1260, _T_1258) @[Mux.scala 27:72] + wire _T_1262 : UInt<1> @[Mux.scala 27:72] + _T_1262 <= _T_1261 @[Mux.scala 27:72] + node obuf_write_in = mux(ibuf_buf_byp, io.lsu_pkt_r.bits.store, _T_1262) @[lsu_bus_buffer.scala 291:26] + node _T_1263 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_1264 = bits(buf_sideeffect, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_1265 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_1266 = bits(buf_sideeffect, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_1267 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_1268 = bits(buf_sideeffect, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_1269 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_1270 = bits(buf_sideeffect, 3, 3) @[lsu_bus_buffer.scala 57:129] + node _T_1271 = mux(_T_1263, _T_1264, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1272 = mux(_T_1265, _T_1266, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1273 = mux(_T_1267, _T_1268, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1274 = mux(_T_1269, _T_1270, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1275 = or(_T_1271, _T_1272) @[Mux.scala 27:72] + node _T_1276 = or(_T_1275, _T_1273) @[Mux.scala 27:72] + node _T_1277 = or(_T_1276, _T_1274) @[Mux.scala 27:72] + wire _T_1278 : UInt<1> @[Mux.scala 27:72] + _T_1278 <= _T_1277 @[Mux.scala 27:72] + node obuf_sideeffect_in = mux(ibuf_buf_byp, io.is_sideeffects_r, _T_1278) @[lsu_bus_buffer.scala 292:31] + node _T_1279 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1280 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1281 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1282 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] + node _T_1283 = mux(_T_1279, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1284 = mux(_T_1280, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1285 = mux(_T_1281, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1286 = mux(_T_1282, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1287 = or(_T_1283, _T_1284) @[Mux.scala 27:72] + node _T_1288 = or(_T_1287, _T_1285) @[Mux.scala 27:72] + node _T_1289 = or(_T_1288, _T_1286) @[Mux.scala 27:72] + wire _T_1290 : UInt<32> @[Mux.scala 27:72] + _T_1290 <= _T_1289 @[Mux.scala 27:72] + node obuf_addr_in = mux(ibuf_buf_byp, io.lsu_addr_r, _T_1290) @[lsu_bus_buffer.scala 293:25] + wire buf_sz : UInt<2>[4] @[lsu_bus_buffer.scala 294:20] + buf_sz[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 295:10] + buf_sz[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 295:10] + buf_sz[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 295:10] + buf_sz[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 295:10] + node _T_1291 = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58] + node _T_1292 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1293 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1294 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1295 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] + node _T_1296 = mux(_T_1292, buf_sz[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1297 = mux(_T_1293, buf_sz[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1298 = mux(_T_1294, buf_sz[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1299 = mux(_T_1295, buf_sz[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1300 = or(_T_1296, _T_1297) @[Mux.scala 27:72] + node _T_1301 = or(_T_1300, _T_1298) @[Mux.scala 27:72] + node _T_1302 = or(_T_1301, _T_1299) @[Mux.scala 27:72] + wire _T_1303 : UInt<2> @[Mux.scala 27:72] + _T_1303 <= _T_1302 @[Mux.scala 27:72] + node obuf_sz_in = mux(ibuf_buf_byp, _T_1291, _T_1303) @[lsu_bus_buffer.scala 296:23] + wire obuf_merge_en : UInt<1> + obuf_merge_en <= UInt<1>("h00") + node obuf_tag0_in = mux(ibuf_buf_byp, WrPtr0_r, CmdPtr0) @[lsu_bus_buffer.scala 299:25] + node obuf_tag1_in = mux(ibuf_buf_byp, WrPtr1_r, CmdPtr1) @[lsu_bus_buffer.scala 301:25] + wire obuf_cmd_done : UInt<1> + obuf_cmd_done <= UInt<1>("h00") + wire bus_wcmd_sent : UInt<1> + bus_wcmd_sent <= UInt<1>("h00") + node _T_1304 = or(obuf_wr_en, obuf_rst) @[lsu_bus_buffer.scala 304:39] + node _T_1305 = eq(_T_1304, UInt<1>("h00")) @[lsu_bus_buffer.scala 304:26] + node _T_1306 = or(obuf_cmd_done, bus_wcmd_sent) @[lsu_bus_buffer.scala 304:68] + node obuf_cmd_done_in = and(_T_1305, _T_1306) @[lsu_bus_buffer.scala 304:51] + wire obuf_data_done : UInt<1> + obuf_data_done <= UInt<1>("h00") + wire bus_wdata_sent : UInt<1> + bus_wdata_sent <= UInt<1>("h00") + node _T_1307 = or(obuf_wr_en, obuf_rst) @[lsu_bus_buffer.scala 307:40] + node _T_1308 = eq(_T_1307, UInt<1>("h00")) @[lsu_bus_buffer.scala 307:27] + node _T_1309 = or(obuf_data_done, bus_wdata_sent) @[lsu_bus_buffer.scala 307:70] + node obuf_data_done_in = and(_T_1308, _T_1309) @[lsu_bus_buffer.scala 307:52] + node _T_1310 = bits(obuf_sz_in, 1, 0) @[lsu_bus_buffer.scala 308:67] + node _T_1311 = eq(_T_1310, UInt<1>("h00")) @[lsu_bus_buffer.scala 308:72] + node _T_1312 = bits(obuf_sz_in, 0, 0) @[lsu_bus_buffer.scala 308:92] + node _T_1313 = bits(obuf_addr_in, 0, 0) @[lsu_bus_buffer.scala 308:111] + node _T_1314 = eq(_T_1313, UInt<1>("h00")) @[lsu_bus_buffer.scala 308:98] + node _T_1315 = and(_T_1312, _T_1314) @[lsu_bus_buffer.scala 308:96] + node _T_1316 = or(_T_1311, _T_1315) @[lsu_bus_buffer.scala 308:79] + node _T_1317 = bits(obuf_sz_in, 1, 1) @[lsu_bus_buffer.scala 308:129] + node _T_1318 = bits(obuf_addr_in, 1, 0) @[lsu_bus_buffer.scala 308:147] + node _T_1319 = orr(_T_1318) @[lsu_bus_buffer.scala 308:153] + node _T_1320 = eq(_T_1319, UInt<1>("h00")) @[lsu_bus_buffer.scala 308:134] + node _T_1321 = and(_T_1317, _T_1320) @[lsu_bus_buffer.scala 308:132] + node _T_1322 = or(_T_1316, _T_1321) @[lsu_bus_buffer.scala 308:116] + node obuf_aligned_in = mux(ibuf_buf_byp, is_aligned_r, _T_1322) @[lsu_bus_buffer.scala 308:28] + wire obuf_nosend_in : UInt<1> + obuf_nosend_in <= UInt<1>("h00") + wire obuf_rdrsp_pend : UInt<1> + obuf_rdrsp_pend <= UInt<1>("h00") + wire bus_rsp_read : UInt<1> + bus_rsp_read <= UInt<1>("h00") + wire bus_rsp_read_tag : UInt<3> + bus_rsp_read_tag <= UInt<1>("h00") + wire obuf_rdrsp_tag : UInt<3> + obuf_rdrsp_tag <= UInt<1>("h00") + wire obuf_write : UInt<1> + obuf_write <= UInt<1>("h00") + node _T_1323 = eq(obuf_nosend_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 316:44] + node _T_1324 = and(obuf_wr_en, _T_1323) @[lsu_bus_buffer.scala 316:42] + node _T_1325 = eq(_T_1324, UInt<1>("h00")) @[lsu_bus_buffer.scala 316:29] + node _T_1326 = and(_T_1325, obuf_rdrsp_pend) @[lsu_bus_buffer.scala 316:61] + node _T_1327 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 316:116] + node _T_1328 = and(bus_rsp_read, _T_1327) @[lsu_bus_buffer.scala 316:96] + node _T_1329 = eq(_T_1328, UInt<1>("h00")) @[lsu_bus_buffer.scala 316:81] + node _T_1330 = and(_T_1326, _T_1329) @[lsu_bus_buffer.scala 316:79] + node _T_1331 = eq(obuf_write, UInt<1>("h00")) @[lsu_bus_buffer.scala 317:22] + node _T_1332 = and(bus_cmd_sent, _T_1331) @[lsu_bus_buffer.scala 317:20] + node _T_1333 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 317:37] + node _T_1334 = and(_T_1332, _T_1333) @[lsu_bus_buffer.scala 317:35] + node obuf_rdrsp_pend_in = or(_T_1330, _T_1334) @[lsu_bus_buffer.scala 316:138] + wire obuf_tag0 : UInt<3> + obuf_tag0 <= UInt<1>("h00") + node _T_1335 = eq(obuf_write, UInt<1>("h00")) @[lsu_bus_buffer.scala 319:46] + node _T_1336 = and(bus_cmd_sent, _T_1335) @[lsu_bus_buffer.scala 319:44] + node obuf_rdrsp_tag_in = mux(_T_1336, obuf_tag0, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 319:30] + wire obuf_addr : UInt<32> + obuf_addr <= UInt<1>("h00") + wire obuf_sideeffect : UInt<1> + obuf_sideeffect <= UInt<1>("h00") + node _T_1337 = bits(obuf_addr_in, 31, 3) @[lsu_bus_buffer.scala 322:34] + node _T_1338 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 322:52] + node _T_1339 = eq(_T_1337, _T_1338) @[lsu_bus_buffer.scala 322:40] + node _T_1340 = and(_T_1339, obuf_aligned_in) @[lsu_bus_buffer.scala 322:60] + node _T_1341 = eq(obuf_sideeffect, UInt<1>("h00")) @[lsu_bus_buffer.scala 322:80] + node _T_1342 = and(_T_1340, _T_1341) @[lsu_bus_buffer.scala 322:78] + node _T_1343 = eq(obuf_write, UInt<1>("h00")) @[lsu_bus_buffer.scala 322:99] + node _T_1344 = and(_T_1342, _T_1343) @[lsu_bus_buffer.scala 322:97] + node _T_1345 = eq(obuf_write_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 322:113] + node _T_1346 = and(_T_1344, _T_1345) @[lsu_bus_buffer.scala 322:111] + node _T_1347 = eq(io.tlu_busbuff.dec_tlu_external_ldfwd_disable, UInt<1>("h00")) @[lsu_bus_buffer.scala 322:130] + node _T_1348 = and(_T_1346, _T_1347) @[lsu_bus_buffer.scala 322:128] + node _T_1349 = eq(obuf_nosend, UInt<1>("h00")) @[lsu_bus_buffer.scala 323:20] + node _T_1350 = and(obuf_valid, _T_1349) @[lsu_bus_buffer.scala 323:18] + node _T_1351 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 323:90] + node _T_1352 = and(bus_rsp_read, _T_1351) @[lsu_bus_buffer.scala 323:70] + node _T_1353 = eq(_T_1352, UInt<1>("h00")) @[lsu_bus_buffer.scala 323:55] + node _T_1354 = and(obuf_rdrsp_pend, _T_1353) @[lsu_bus_buffer.scala 323:53] + node _T_1355 = or(_T_1350, _T_1354) @[lsu_bus_buffer.scala 323:34] + node _T_1356 = and(_T_1348, _T_1355) @[lsu_bus_buffer.scala 322:177] + obuf_nosend_in <= _T_1356 @[lsu_bus_buffer.scala 322:18] + node _T_1357 = bits(io.lsu_addr_r, 2, 2) @[lsu_bus_buffer.scala 324:60] + node _T_1358 = cat(ldst_byteen_lo_r, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_1359 = cat(UInt<4>("h00"), ldst_byteen_lo_r) @[Cat.scala 29:58] + node _T_1360 = mux(_T_1357, _T_1358, _T_1359) @[lsu_bus_buffer.scala 324:46] + node _T_1361 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1362 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1363 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1364 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] + node _T_1365 = mux(_T_1361, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1366 = mux(_T_1362, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1367 = mux(_T_1363, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1368 = mux(_T_1364, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1369 = or(_T_1365, _T_1366) @[Mux.scala 27:72] + node _T_1370 = or(_T_1369, _T_1367) @[Mux.scala 27:72] + node _T_1371 = or(_T_1370, _T_1368) @[Mux.scala 27:72] + wire _T_1372 : UInt<32> @[Mux.scala 27:72] + _T_1372 <= _T_1371 @[Mux.scala 27:72] + node _T_1373 = bits(_T_1372, 2, 2) @[lsu_bus_buffer.scala 325:36] + node _T_1374 = bits(_T_1373, 0, 0) @[lsu_bus_buffer.scala 325:46] + node _T_1375 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1376 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1377 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1378 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] + node _T_1379 = mux(_T_1375, buf_byteen[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1380 = mux(_T_1376, buf_byteen[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1381 = mux(_T_1377, buf_byteen[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1382 = mux(_T_1378, buf_byteen[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1383 = or(_T_1379, _T_1380) @[Mux.scala 27:72] + node _T_1384 = or(_T_1383, _T_1381) @[Mux.scala 27:72] + node _T_1385 = or(_T_1384, _T_1382) @[Mux.scala 27:72] + wire _T_1386 : UInt<4> @[Mux.scala 27:72] + _T_1386 <= _T_1385 @[Mux.scala 27:72] + node _T_1387 = cat(_T_1386, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_1388 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1389 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1390 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1391 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] + node _T_1392 = mux(_T_1388, buf_byteen[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1393 = mux(_T_1389, buf_byteen[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1394 = mux(_T_1390, buf_byteen[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1395 = mux(_T_1391, buf_byteen[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1396 = or(_T_1392, _T_1393) @[Mux.scala 27:72] + node _T_1397 = or(_T_1396, _T_1394) @[Mux.scala 27:72] + node _T_1398 = or(_T_1397, _T_1395) @[Mux.scala 27:72] + wire _T_1399 : UInt<4> @[Mux.scala 27:72] + _T_1399 <= _T_1398 @[Mux.scala 27:72] + node _T_1400 = cat(UInt<4>("h00"), _T_1399) @[Cat.scala 29:58] + node _T_1401 = mux(_T_1374, _T_1387, _T_1400) @[lsu_bus_buffer.scala 325:8] + node obuf_byteen0_in = mux(ibuf_buf_byp, _T_1360, _T_1401) @[lsu_bus_buffer.scala 324:28] + node _T_1402 = bits(io.end_addr_r, 2, 2) @[lsu_bus_buffer.scala 326:60] + node _T_1403 = cat(ldst_byteen_hi_r, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_1404 = cat(UInt<4>("h00"), ldst_byteen_hi_r) @[Cat.scala 29:58] + node _T_1405 = mux(_T_1402, _T_1403, _T_1404) @[lsu_bus_buffer.scala 326:46] + node _T_1406 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1407 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1408 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1409 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] + node _T_1410 = mux(_T_1406, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1411 = mux(_T_1407, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1412 = mux(_T_1408, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1413 = mux(_T_1409, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1414 = or(_T_1410, _T_1411) @[Mux.scala 27:72] + node _T_1415 = or(_T_1414, _T_1412) @[Mux.scala 27:72] + node _T_1416 = or(_T_1415, _T_1413) @[Mux.scala 27:72] + wire _T_1417 : UInt<32> @[Mux.scala 27:72] + _T_1417 <= _T_1416 @[Mux.scala 27:72] + node _T_1418 = bits(_T_1417, 2, 2) @[lsu_bus_buffer.scala 327:36] + node _T_1419 = bits(_T_1418, 0, 0) @[lsu_bus_buffer.scala 327:46] + node _T_1420 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1421 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1422 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1423 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] + node _T_1424 = mux(_T_1420, buf_byteen[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1425 = mux(_T_1421, buf_byteen[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1426 = mux(_T_1422, buf_byteen[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1427 = mux(_T_1423, buf_byteen[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1428 = or(_T_1424, _T_1425) @[Mux.scala 27:72] + node _T_1429 = or(_T_1428, _T_1426) @[Mux.scala 27:72] + node _T_1430 = or(_T_1429, _T_1427) @[Mux.scala 27:72] + wire _T_1431 : UInt<4> @[Mux.scala 27:72] + _T_1431 <= _T_1430 @[Mux.scala 27:72] + node _T_1432 = cat(_T_1431, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_1433 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1434 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1435 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1436 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] + node _T_1437 = mux(_T_1433, buf_byteen[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1438 = mux(_T_1434, buf_byteen[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1439 = mux(_T_1435, buf_byteen[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1440 = mux(_T_1436, buf_byteen[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1441 = or(_T_1437, _T_1438) @[Mux.scala 27:72] + node _T_1442 = or(_T_1441, _T_1439) @[Mux.scala 27:72] + node _T_1443 = or(_T_1442, _T_1440) @[Mux.scala 27:72] + wire _T_1444 : UInt<4> @[Mux.scala 27:72] + _T_1444 <= _T_1443 @[Mux.scala 27:72] + node _T_1445 = cat(UInt<4>("h00"), _T_1444) @[Cat.scala 29:58] + node _T_1446 = mux(_T_1419, _T_1432, _T_1445) @[lsu_bus_buffer.scala 327:8] + node obuf_byteen1_in = mux(ibuf_buf_byp, _T_1405, _T_1446) @[lsu_bus_buffer.scala 326:28] + node _T_1447 = bits(io.lsu_addr_r, 2, 2) @[lsu_bus_buffer.scala 329:58] + node _T_1448 = cat(store_data_lo_r, UInt<32>("h00")) @[Cat.scala 29:58] + node _T_1449 = cat(UInt<32>("h00"), store_data_lo_r) @[Cat.scala 29:58] + node _T_1450 = mux(_T_1447, _T_1448, _T_1449) @[lsu_bus_buffer.scala 329:44] + node _T_1451 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1452 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1453 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1454 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] + node _T_1455 = mux(_T_1451, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1456 = mux(_T_1452, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1457 = mux(_T_1453, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1458 = mux(_T_1454, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1459 = or(_T_1455, _T_1456) @[Mux.scala 27:72] + node _T_1460 = or(_T_1459, _T_1457) @[Mux.scala 27:72] + node _T_1461 = or(_T_1460, _T_1458) @[Mux.scala 27:72] + wire _T_1462 : UInt<32> @[Mux.scala 27:72] + _T_1462 <= _T_1461 @[Mux.scala 27:72] + node _T_1463 = bits(_T_1462, 2, 2) @[lsu_bus_buffer.scala 330:36] + node _T_1464 = bits(_T_1463, 0, 0) @[lsu_bus_buffer.scala 330:46] + node _T_1465 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1466 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1467 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1468 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] + node _T_1469 = mux(_T_1465, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1470 = mux(_T_1466, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1471 = mux(_T_1467, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1472 = mux(_T_1468, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1473 = or(_T_1469, _T_1470) @[Mux.scala 27:72] + node _T_1474 = or(_T_1473, _T_1471) @[Mux.scala 27:72] + node _T_1475 = or(_T_1474, _T_1472) @[Mux.scala 27:72] + wire _T_1476 : UInt<32> @[Mux.scala 27:72] + _T_1476 <= _T_1475 @[Mux.scala 27:72] + node _T_1477 = cat(_T_1476, UInt<32>("h00")) @[Cat.scala 29:58] + node _T_1478 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1479 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1480 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1481 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] + node _T_1482 = mux(_T_1478, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1483 = mux(_T_1479, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1484 = mux(_T_1480, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1485 = mux(_T_1481, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1486 = or(_T_1482, _T_1483) @[Mux.scala 27:72] + node _T_1487 = or(_T_1486, _T_1484) @[Mux.scala 27:72] + node _T_1488 = or(_T_1487, _T_1485) @[Mux.scala 27:72] + wire _T_1489 : UInt<32> @[Mux.scala 27:72] + _T_1489 <= _T_1488 @[Mux.scala 27:72] + node _T_1490 = cat(UInt<32>("h00"), _T_1489) @[Cat.scala 29:58] + node _T_1491 = mux(_T_1464, _T_1477, _T_1490) @[lsu_bus_buffer.scala 330:8] + node obuf_data0_in = mux(ibuf_buf_byp, _T_1450, _T_1491) @[lsu_bus_buffer.scala 329:26] + node _T_1492 = bits(io.lsu_addr_r, 2, 2) @[lsu_bus_buffer.scala 331:58] + node _T_1493 = cat(store_data_hi_r, UInt<32>("h00")) @[Cat.scala 29:58] + node _T_1494 = cat(UInt<32>("h00"), store_data_hi_r) @[Cat.scala 29:58] + node _T_1495 = mux(_T_1492, _T_1493, _T_1494) @[lsu_bus_buffer.scala 331:44] + node _T_1496 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1497 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1498 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1499 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] + node _T_1500 = mux(_T_1496, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1501 = mux(_T_1497, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1502 = mux(_T_1498, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1503 = mux(_T_1499, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1504 = or(_T_1500, _T_1501) @[Mux.scala 27:72] + node _T_1505 = or(_T_1504, _T_1502) @[Mux.scala 27:72] + node _T_1506 = or(_T_1505, _T_1503) @[Mux.scala 27:72] + wire _T_1507 : UInt<32> @[Mux.scala 27:72] + _T_1507 <= _T_1506 @[Mux.scala 27:72] + node _T_1508 = bits(_T_1507, 2, 2) @[lsu_bus_buffer.scala 332:36] + node _T_1509 = bits(_T_1508, 0, 0) @[lsu_bus_buffer.scala 332:46] + node _T_1510 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1511 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1512 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1513 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] + node _T_1514 = mux(_T_1510, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1515 = mux(_T_1511, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1516 = mux(_T_1512, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1517 = mux(_T_1513, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1518 = or(_T_1514, _T_1515) @[Mux.scala 27:72] + node _T_1519 = or(_T_1518, _T_1516) @[Mux.scala 27:72] + node _T_1520 = or(_T_1519, _T_1517) @[Mux.scala 27:72] + wire _T_1521 : UInt<32> @[Mux.scala 27:72] + _T_1521 <= _T_1520 @[Mux.scala 27:72] + node _T_1522 = cat(_T_1521, UInt<32>("h00")) @[Cat.scala 29:58] + node _T_1523 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1524 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1525 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1526 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] + node _T_1527 = mux(_T_1523, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1528 = mux(_T_1524, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1529 = mux(_T_1525, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1530 = mux(_T_1526, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1531 = or(_T_1527, _T_1528) @[Mux.scala 27:72] + node _T_1532 = or(_T_1531, _T_1529) @[Mux.scala 27:72] + node _T_1533 = or(_T_1532, _T_1530) @[Mux.scala 27:72] + wire _T_1534 : UInt<32> @[Mux.scala 27:72] + _T_1534 <= _T_1533 @[Mux.scala 27:72] + node _T_1535 = cat(UInt<32>("h00"), _T_1534) @[Cat.scala 29:58] + node _T_1536 = mux(_T_1509, _T_1522, _T_1535) @[lsu_bus_buffer.scala 332:8] + node obuf_data1_in = mux(ibuf_buf_byp, _T_1495, _T_1536) @[lsu_bus_buffer.scala 331:26] + node _T_1537 = bits(obuf_byteen0_in, 0, 0) @[lsu_bus_buffer.scala 333:59] + node _T_1538 = bits(obuf_byteen1_in, 0, 0) @[lsu_bus_buffer.scala 333:97] + node _T_1539 = and(obuf_merge_en, _T_1538) @[lsu_bus_buffer.scala 333:80] + node _T_1540 = or(_T_1537, _T_1539) @[lsu_bus_buffer.scala 333:63] + node _T_1541 = bits(obuf_byteen0_in, 1, 1) @[lsu_bus_buffer.scala 333:59] + node _T_1542 = bits(obuf_byteen1_in, 1, 1) @[lsu_bus_buffer.scala 333:97] + node _T_1543 = and(obuf_merge_en, _T_1542) @[lsu_bus_buffer.scala 333:80] + node _T_1544 = or(_T_1541, _T_1543) @[lsu_bus_buffer.scala 333:63] + node _T_1545 = bits(obuf_byteen0_in, 2, 2) @[lsu_bus_buffer.scala 333:59] + node _T_1546 = bits(obuf_byteen1_in, 2, 2) @[lsu_bus_buffer.scala 333:97] + node _T_1547 = and(obuf_merge_en, _T_1546) @[lsu_bus_buffer.scala 333:80] + node _T_1548 = or(_T_1545, _T_1547) @[lsu_bus_buffer.scala 333:63] + node _T_1549 = bits(obuf_byteen0_in, 3, 3) @[lsu_bus_buffer.scala 333:59] + node _T_1550 = bits(obuf_byteen1_in, 3, 3) @[lsu_bus_buffer.scala 333:97] + node _T_1551 = and(obuf_merge_en, _T_1550) @[lsu_bus_buffer.scala 333:80] + node _T_1552 = or(_T_1549, _T_1551) @[lsu_bus_buffer.scala 333:63] + node _T_1553 = bits(obuf_byteen0_in, 4, 4) @[lsu_bus_buffer.scala 333:59] + node _T_1554 = bits(obuf_byteen1_in, 4, 4) @[lsu_bus_buffer.scala 333:97] + node _T_1555 = and(obuf_merge_en, _T_1554) @[lsu_bus_buffer.scala 333:80] + node _T_1556 = or(_T_1553, _T_1555) @[lsu_bus_buffer.scala 333:63] + node _T_1557 = bits(obuf_byteen0_in, 5, 5) @[lsu_bus_buffer.scala 333:59] + node _T_1558 = bits(obuf_byteen1_in, 5, 5) @[lsu_bus_buffer.scala 333:97] + node _T_1559 = and(obuf_merge_en, _T_1558) @[lsu_bus_buffer.scala 333:80] + node _T_1560 = or(_T_1557, _T_1559) @[lsu_bus_buffer.scala 333:63] + node _T_1561 = bits(obuf_byteen0_in, 6, 6) @[lsu_bus_buffer.scala 333:59] + node _T_1562 = bits(obuf_byteen1_in, 6, 6) @[lsu_bus_buffer.scala 333:97] + node _T_1563 = and(obuf_merge_en, _T_1562) @[lsu_bus_buffer.scala 333:80] + node _T_1564 = or(_T_1561, _T_1563) @[lsu_bus_buffer.scala 333:63] + node _T_1565 = bits(obuf_byteen0_in, 7, 7) @[lsu_bus_buffer.scala 333:59] + node _T_1566 = bits(obuf_byteen1_in, 7, 7) @[lsu_bus_buffer.scala 333:97] + node _T_1567 = and(obuf_merge_en, _T_1566) @[lsu_bus_buffer.scala 333:80] + node _T_1568 = or(_T_1565, _T_1567) @[lsu_bus_buffer.scala 333:63] + node _T_1569 = cat(_T_1568, _T_1564) @[Cat.scala 29:58] + node _T_1570 = cat(_T_1569, _T_1560) @[Cat.scala 29:58] + node _T_1571 = cat(_T_1570, _T_1556) @[Cat.scala 29:58] + node _T_1572 = cat(_T_1571, _T_1552) @[Cat.scala 29:58] + node _T_1573 = cat(_T_1572, _T_1548) @[Cat.scala 29:58] + node _T_1574 = cat(_T_1573, _T_1544) @[Cat.scala 29:58] + node obuf_byteen_in = cat(_T_1574, _T_1540) @[Cat.scala 29:58] + node _T_1575 = bits(obuf_byteen1_in, 0, 0) @[lsu_bus_buffer.scala 334:76] + node _T_1576 = and(obuf_merge_en, _T_1575) @[lsu_bus_buffer.scala 334:59] + node _T_1577 = bits(obuf_data1_in, 7, 0) @[lsu_bus_buffer.scala 334:94] + node _T_1578 = bits(obuf_data0_in, 7, 0) @[lsu_bus_buffer.scala 334:123] + node _T_1579 = mux(_T_1576, _T_1577, _T_1578) @[lsu_bus_buffer.scala 334:44] + node _T_1580 = bits(obuf_byteen1_in, 1, 1) @[lsu_bus_buffer.scala 334:76] + node _T_1581 = and(obuf_merge_en, _T_1580) @[lsu_bus_buffer.scala 334:59] + node _T_1582 = bits(obuf_data1_in, 15, 8) @[lsu_bus_buffer.scala 334:94] + node _T_1583 = bits(obuf_data0_in, 15, 8) @[lsu_bus_buffer.scala 334:123] + node _T_1584 = mux(_T_1581, _T_1582, _T_1583) @[lsu_bus_buffer.scala 334:44] + node _T_1585 = bits(obuf_byteen1_in, 2, 2) @[lsu_bus_buffer.scala 334:76] + node _T_1586 = and(obuf_merge_en, _T_1585) @[lsu_bus_buffer.scala 334:59] + node _T_1587 = bits(obuf_data1_in, 23, 16) @[lsu_bus_buffer.scala 334:94] + node _T_1588 = bits(obuf_data0_in, 23, 16) @[lsu_bus_buffer.scala 334:123] + node _T_1589 = mux(_T_1586, _T_1587, _T_1588) @[lsu_bus_buffer.scala 334:44] + node _T_1590 = bits(obuf_byteen1_in, 3, 3) @[lsu_bus_buffer.scala 334:76] + node _T_1591 = and(obuf_merge_en, _T_1590) @[lsu_bus_buffer.scala 334:59] + node _T_1592 = bits(obuf_data1_in, 31, 24) @[lsu_bus_buffer.scala 334:94] + node _T_1593 = bits(obuf_data0_in, 31, 24) @[lsu_bus_buffer.scala 334:123] + node _T_1594 = mux(_T_1591, _T_1592, _T_1593) @[lsu_bus_buffer.scala 334:44] + node _T_1595 = bits(obuf_byteen1_in, 4, 4) @[lsu_bus_buffer.scala 334:76] + node _T_1596 = and(obuf_merge_en, _T_1595) @[lsu_bus_buffer.scala 334:59] + node _T_1597 = bits(obuf_data1_in, 39, 32) @[lsu_bus_buffer.scala 334:94] + node _T_1598 = bits(obuf_data0_in, 39, 32) @[lsu_bus_buffer.scala 334:123] + node _T_1599 = mux(_T_1596, _T_1597, _T_1598) @[lsu_bus_buffer.scala 334:44] + node _T_1600 = bits(obuf_byteen1_in, 5, 5) @[lsu_bus_buffer.scala 334:76] + node _T_1601 = and(obuf_merge_en, _T_1600) @[lsu_bus_buffer.scala 334:59] + node _T_1602 = bits(obuf_data1_in, 47, 40) @[lsu_bus_buffer.scala 334:94] + node _T_1603 = bits(obuf_data0_in, 47, 40) @[lsu_bus_buffer.scala 334:123] + node _T_1604 = mux(_T_1601, _T_1602, _T_1603) @[lsu_bus_buffer.scala 334:44] + node _T_1605 = bits(obuf_byteen1_in, 6, 6) @[lsu_bus_buffer.scala 334:76] + node _T_1606 = and(obuf_merge_en, _T_1605) @[lsu_bus_buffer.scala 334:59] + node _T_1607 = bits(obuf_data1_in, 55, 48) @[lsu_bus_buffer.scala 334:94] + node _T_1608 = bits(obuf_data0_in, 55, 48) @[lsu_bus_buffer.scala 334:123] + node _T_1609 = mux(_T_1606, _T_1607, _T_1608) @[lsu_bus_buffer.scala 334:44] + node _T_1610 = bits(obuf_byteen1_in, 7, 7) @[lsu_bus_buffer.scala 334:76] + node _T_1611 = and(obuf_merge_en, _T_1610) @[lsu_bus_buffer.scala 334:59] + node _T_1612 = bits(obuf_data1_in, 63, 56) @[lsu_bus_buffer.scala 334:94] + node _T_1613 = bits(obuf_data0_in, 63, 56) @[lsu_bus_buffer.scala 334:123] + node _T_1614 = mux(_T_1611, _T_1612, _T_1613) @[lsu_bus_buffer.scala 334:44] + node _T_1615 = cat(_T_1614, _T_1609) @[Cat.scala 29:58] + node _T_1616 = cat(_T_1615, _T_1604) @[Cat.scala 29:58] + node _T_1617 = cat(_T_1616, _T_1599) @[Cat.scala 29:58] + node _T_1618 = cat(_T_1617, _T_1594) @[Cat.scala 29:58] + node _T_1619 = cat(_T_1618, _T_1589) @[Cat.scala 29:58] + node _T_1620 = cat(_T_1619, _T_1584) @[Cat.scala 29:58] + node obuf_data_in = cat(_T_1620, _T_1579) @[Cat.scala 29:58] + wire buf_dualhi : UInt<1>[4] @[lsu_bus_buffer.scala 336:24] + buf_dualhi[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 337:14] + buf_dualhi[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 337:14] + buf_dualhi[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 337:14] + buf_dualhi[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 337:14] + node _T_1621 = neq(CmdPtr0, CmdPtr1) @[lsu_bus_buffer.scala 338:30] + node _T_1622 = and(_T_1621, found_cmdptr0) @[lsu_bus_buffer.scala 338:43] + node _T_1623 = and(_T_1622, found_cmdptr1) @[lsu_bus_buffer.scala 338:59] + node _T_1624 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1625 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1626 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1627 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] + node _T_1628 = mux(_T_1624, buf_state[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1629 = mux(_T_1625, buf_state[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1630 = mux(_T_1626, buf_state[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1631 = mux(_T_1627, buf_state[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1632 = or(_T_1628, _T_1629) @[Mux.scala 27:72] + node _T_1633 = or(_T_1632, _T_1630) @[Mux.scala 27:72] + node _T_1634 = or(_T_1633, _T_1631) @[Mux.scala 27:72] + wire _T_1635 : UInt<3> @[Mux.scala 27:72] + _T_1635 <= _T_1634 @[Mux.scala 27:72] + node _T_1636 = eq(_T_1635, UInt<3>("h02")) @[lsu_bus_buffer.scala 338:107] + node _T_1637 = and(_T_1623, _T_1636) @[lsu_bus_buffer.scala 338:75] + node _T_1638 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1639 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1640 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1641 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] + node _T_1642 = mux(_T_1638, buf_state[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1643 = mux(_T_1639, buf_state[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1644 = mux(_T_1640, buf_state[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1645 = mux(_T_1641, buf_state[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1646 = or(_T_1642, _T_1643) @[Mux.scala 27:72] + node _T_1647 = or(_T_1646, _T_1644) @[Mux.scala 27:72] + node _T_1648 = or(_T_1647, _T_1645) @[Mux.scala 27:72] + wire _T_1649 : UInt<3> @[Mux.scala 27:72] + _T_1649 <= _T_1648 @[Mux.scala 27:72] + node _T_1650 = eq(_T_1649, UInt<3>("h02")) @[lsu_bus_buffer.scala 338:150] + node _T_1651 = and(_T_1637, _T_1650) @[lsu_bus_buffer.scala 338:118] + node _T_1652 = cat(buf_cmd_state_bus_en[3], buf_cmd_state_bus_en[2]) @[Cat.scala 29:58] + node _T_1653 = cat(_T_1652, buf_cmd_state_bus_en[1]) @[Cat.scala 29:58] + node _T_1654 = cat(_T_1653, buf_cmd_state_bus_en[0]) @[Cat.scala 29:58] + node _T_1655 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_1656 = bits(_T_1654, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_1657 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_1658 = bits(_T_1654, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_1659 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_1660 = bits(_T_1654, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_1661 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_1662 = bits(_T_1654, 3, 3) @[lsu_bus_buffer.scala 57:129] + node _T_1663 = mux(_T_1655, _T_1656, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1664 = mux(_T_1657, _T_1658, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1665 = mux(_T_1659, _T_1660, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1666 = mux(_T_1661, _T_1662, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1667 = or(_T_1663, _T_1664) @[Mux.scala 27:72] + node _T_1668 = or(_T_1667, _T_1665) @[Mux.scala 27:72] + node _T_1669 = or(_T_1668, _T_1666) @[Mux.scala 27:72] + wire _T_1670 : UInt<1> @[Mux.scala 27:72] + _T_1670 <= _T_1669 @[Mux.scala 27:72] + node _T_1671 = eq(_T_1670, UInt<1>("h00")) @[lsu_bus_buffer.scala 339:5] + node _T_1672 = and(_T_1651, _T_1671) @[lsu_bus_buffer.scala 338:161] + node _T_1673 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_1674 = bits(buf_sideeffect, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_1675 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_1676 = bits(buf_sideeffect, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_1677 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_1678 = bits(buf_sideeffect, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_1679 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_1680 = bits(buf_sideeffect, 3, 3) @[lsu_bus_buffer.scala 57:129] + node _T_1681 = mux(_T_1673, _T_1674, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1682 = mux(_T_1675, _T_1676, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1683 = mux(_T_1677, _T_1678, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1684 = mux(_T_1679, _T_1680, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1685 = or(_T_1681, _T_1682) @[Mux.scala 27:72] + node _T_1686 = or(_T_1685, _T_1683) @[Mux.scala 27:72] + node _T_1687 = or(_T_1686, _T_1684) @[Mux.scala 27:72] + wire _T_1688 : UInt<1> @[Mux.scala 27:72] + _T_1688 <= _T_1687 @[Mux.scala 27:72] + node _T_1689 = eq(_T_1688, UInt<1>("h00")) @[lsu_bus_buffer.scala 339:87] + node _T_1690 = and(_T_1672, _T_1689) @[lsu_bus_buffer.scala 339:85] + node _T_1691 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_1692 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_1693 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_1694 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_1695 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_1696 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_1697 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_1698 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 57:129] + node _T_1699 = mux(_T_1691, _T_1692, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1700 = mux(_T_1693, _T_1694, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1701 = mux(_T_1695, _T_1696, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1702 = mux(_T_1697, _T_1698, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1703 = or(_T_1699, _T_1700) @[Mux.scala 27:72] + node _T_1704 = or(_T_1703, _T_1701) @[Mux.scala 27:72] + node _T_1705 = or(_T_1704, _T_1702) @[Mux.scala 27:72] + wire _T_1706 : UInt<1> @[Mux.scala 27:72] + _T_1706 <= _T_1705 @[Mux.scala 27:72] + node _T_1707 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_1708 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_1709 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_1710 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_1711 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_1712 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_1713 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_1714 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 57:129] + node _T_1715 = mux(_T_1707, _T_1708, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1716 = mux(_T_1709, _T_1710, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1717 = mux(_T_1711, _T_1712, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1718 = mux(_T_1713, _T_1714, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1719 = or(_T_1715, _T_1716) @[Mux.scala 27:72] + node _T_1720 = or(_T_1719, _T_1717) @[Mux.scala 27:72] + node _T_1721 = or(_T_1720, _T_1718) @[Mux.scala 27:72] + wire _T_1722 : UInt<1> @[Mux.scala 27:72] + _T_1722 <= _T_1721 @[Mux.scala 27:72] + node _T_1723 = and(_T_1706, _T_1722) @[lsu_bus_buffer.scala 340:36] + node _T_1724 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1725 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1726 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1727 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] + node _T_1728 = mux(_T_1724, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1729 = mux(_T_1725, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1730 = mux(_T_1726, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1731 = mux(_T_1727, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1732 = or(_T_1728, _T_1729) @[Mux.scala 27:72] + node _T_1733 = or(_T_1732, _T_1730) @[Mux.scala 27:72] + node _T_1734 = or(_T_1733, _T_1731) @[Mux.scala 27:72] + wire _T_1735 : UInt<32> @[Mux.scala 27:72] + _T_1735 <= _T_1734 @[Mux.scala 27:72] + node _T_1736 = bits(_T_1735, 31, 3) @[lsu_bus_buffer.scala 341:35] + node _T_1737 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1738 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1739 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1740 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] + node _T_1741 = mux(_T_1737, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1742 = mux(_T_1738, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1743 = mux(_T_1739, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1744 = mux(_T_1740, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1745 = or(_T_1741, _T_1742) @[Mux.scala 27:72] + node _T_1746 = or(_T_1745, _T_1743) @[Mux.scala 27:72] + node _T_1747 = or(_T_1746, _T_1744) @[Mux.scala 27:72] + wire _T_1748 : UInt<32> @[Mux.scala 27:72] + _T_1748 <= _T_1747 @[Mux.scala 27:72] + node _T_1749 = bits(_T_1748, 31, 3) @[lsu_bus_buffer.scala 341:71] + node _T_1750 = eq(_T_1736, _T_1749) @[lsu_bus_buffer.scala 341:41] + node _T_1751 = and(_T_1723, _T_1750) @[lsu_bus_buffer.scala 340:67] + node _T_1752 = eq(bus_coalescing_disable, UInt<1>("h00")) @[lsu_bus_buffer.scala 341:81] + node _T_1753 = and(_T_1751, _T_1752) @[lsu_bus_buffer.scala 341:79] + node _T_1754 = eq(UInt<1>("h01"), UInt<1>("h00")) @[lsu_bus_buffer.scala 341:107] + node _T_1755 = and(_T_1753, _T_1754) @[lsu_bus_buffer.scala 341:105] + node _T_1756 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_1757 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_1758 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_1759 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_1760 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_1761 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_1762 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_1763 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 57:129] + node _T_1764 = mux(_T_1756, _T_1757, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1765 = mux(_T_1758, _T_1759, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1766 = mux(_T_1760, _T_1761, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1767 = mux(_T_1762, _T_1763, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1768 = or(_T_1764, _T_1765) @[Mux.scala 27:72] + node _T_1769 = or(_T_1768, _T_1766) @[Mux.scala 27:72] + node _T_1770 = or(_T_1769, _T_1767) @[Mux.scala 27:72] + wire _T_1771 : UInt<1> @[Mux.scala 27:72] + _T_1771 <= _T_1770 @[Mux.scala 27:72] + node _T_1772 = eq(_T_1771, UInt<1>("h00")) @[lsu_bus_buffer.scala 342:8] + node _T_1773 = cat(buf_dual[3], buf_dual[2]) @[Cat.scala 29:58] + node _T_1774 = cat(_T_1773, buf_dual[1]) @[Cat.scala 29:58] + node _T_1775 = cat(_T_1774, buf_dual[0]) @[Cat.scala 29:58] + node _T_1776 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_1777 = bits(_T_1775, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_1778 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_1779 = bits(_T_1775, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_1780 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_1781 = bits(_T_1775, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_1782 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_1783 = bits(_T_1775, 3, 3) @[lsu_bus_buffer.scala 57:129] + node _T_1784 = mux(_T_1776, _T_1777, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1785 = mux(_T_1778, _T_1779, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1786 = mux(_T_1780, _T_1781, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1787 = mux(_T_1782, _T_1783, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1788 = or(_T_1784, _T_1785) @[Mux.scala 27:72] + node _T_1789 = or(_T_1788, _T_1786) @[Mux.scala 27:72] + node _T_1790 = or(_T_1789, _T_1787) @[Mux.scala 27:72] + wire _T_1791 : UInt<1> @[Mux.scala 27:72] + _T_1791 <= _T_1790 @[Mux.scala 27:72] + node _T_1792 = and(_T_1772, _T_1791) @[lsu_bus_buffer.scala 342:38] + node _T_1793 = cat(buf_dualhi[3], buf_dualhi[2]) @[Cat.scala 29:58] + node _T_1794 = cat(_T_1793, buf_dualhi[1]) @[Cat.scala 29:58] + node _T_1795 = cat(_T_1794, buf_dualhi[0]) @[Cat.scala 29:58] + node _T_1796 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_1797 = bits(_T_1795, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_1798 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_1799 = bits(_T_1795, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_1800 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_1801 = bits(_T_1795, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_1802 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_1803 = bits(_T_1795, 3, 3) @[lsu_bus_buffer.scala 57:129] + node _T_1804 = mux(_T_1796, _T_1797, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1805 = mux(_T_1798, _T_1799, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1806 = mux(_T_1800, _T_1801, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1807 = mux(_T_1802, _T_1803, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1808 = or(_T_1804, _T_1805) @[Mux.scala 27:72] + node _T_1809 = or(_T_1808, _T_1806) @[Mux.scala 27:72] + node _T_1810 = or(_T_1809, _T_1807) @[Mux.scala 27:72] + wire _T_1811 : UInt<1> @[Mux.scala 27:72] + _T_1811 <= _T_1810 @[Mux.scala 27:72] + node _T_1812 = eq(_T_1811, UInt<1>("h00")) @[lsu_bus_buffer.scala 342:109] + node _T_1813 = and(_T_1792, _T_1812) @[lsu_bus_buffer.scala 342:107] + node _T_1814 = cat(buf_samedw[3], buf_samedw[2]) @[Cat.scala 29:58] + node _T_1815 = cat(_T_1814, buf_samedw[1]) @[Cat.scala 29:58] + node _T_1816 = cat(_T_1815, buf_samedw[0]) @[Cat.scala 29:58] + node _T_1817 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_1818 = bits(_T_1816, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_1819 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_1820 = bits(_T_1816, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_1821 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_1822 = bits(_T_1816, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_1823 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_1824 = bits(_T_1816, 3, 3) @[lsu_bus_buffer.scala 57:129] + node _T_1825 = mux(_T_1817, _T_1818, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1826 = mux(_T_1819, _T_1820, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1827 = mux(_T_1821, _T_1822, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1828 = mux(_T_1823, _T_1824, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1829 = or(_T_1825, _T_1826) @[Mux.scala 27:72] + node _T_1830 = or(_T_1829, _T_1827) @[Mux.scala 27:72] + node _T_1831 = or(_T_1830, _T_1828) @[Mux.scala 27:72] + wire _T_1832 : UInt<1> @[Mux.scala 27:72] + _T_1832 <= _T_1831 @[Mux.scala 27:72] + node _T_1833 = and(_T_1813, _T_1832) @[lsu_bus_buffer.scala 342:179] + node _T_1834 = or(_T_1755, _T_1833) @[lsu_bus_buffer.scala 341:128] + node _T_1835 = and(_T_1690, _T_1834) @[lsu_bus_buffer.scala 339:122] + node _T_1836 = and(ibuf_buf_byp, ldst_samedw_r) @[lsu_bus_buffer.scala 343:19] + node _T_1837 = and(_T_1836, io.ldst_dual_r) @[lsu_bus_buffer.scala 343:35] + node _T_1838 = or(_T_1835, _T_1837) @[lsu_bus_buffer.scala 342:253] + obuf_merge_en <= _T_1838 @[lsu_bus_buffer.scala 338:17] + reg obuf_wr_enQ : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 345:55] + obuf_wr_enQ <= obuf_wr_en @[lsu_bus_buffer.scala 345:55] + node _T_1839 = mux(obuf_wr_en, UInt<1>("h01"), obuf_valid) @[lsu_bus_buffer.scala 346:58] + node _T_1840 = eq(obuf_rst, UInt<1>("h00")) @[lsu_bus_buffer.scala 346:93] + node _T_1841 = and(_T_1839, _T_1840) @[lsu_bus_buffer.scala 346:91] + reg _T_1842 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 346:54] + _T_1842 <= _T_1841 @[lsu_bus_buffer.scala 346:54] + obuf_valid <= _T_1842 @[lsu_bus_buffer.scala 346:14] + reg _T_1843 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when obuf_wr_en : @[Reg.scala 28:19] + _T_1843 <= obuf_nosend_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_nosend <= _T_1843 @[lsu_bus_buffer.scala 347:15] + reg _T_1844 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 348:54] + _T_1844 <= obuf_cmd_done_in @[lsu_bus_buffer.scala 348:54] + obuf_cmd_done <= _T_1844 @[lsu_bus_buffer.scala 348:17] + reg _T_1845 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 349:55] + _T_1845 <= obuf_data_done_in @[lsu_bus_buffer.scala 349:55] + obuf_data_done <= _T_1845 @[lsu_bus_buffer.scala 349:18] + reg _T_1846 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 350:56] + _T_1846 <= obuf_rdrsp_pend_in @[lsu_bus_buffer.scala 350:56] + obuf_rdrsp_pend <= _T_1846 @[lsu_bus_buffer.scala 350:19] + reg _T_1847 : UInt, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 351:55] + _T_1847 <= obuf_rdrsp_tag_in @[lsu_bus_buffer.scala 351:55] + obuf_rdrsp_tag <= _T_1847 @[lsu_bus_buffer.scala 351:18] + reg _T_1848 : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when obuf_wr_en : @[Reg.scala 28:19] + _T_1848 <= obuf_tag0_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_tag0 <= _T_1848 @[lsu_bus_buffer.scala 352:13] + reg obuf_tag1 : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when obuf_wr_en : @[Reg.scala 28:19] + obuf_tag1 <= obuf_tag1_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg obuf_merge : UInt<1>, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when obuf_wr_en : @[Reg.scala 28:19] + obuf_merge <= obuf_merge_en @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg _T_1849 : UInt<1>, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when obuf_wr_en : @[Reg.scala 28:19] + _T_1849 <= obuf_write_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_write <= _T_1849 @[lsu_bus_buffer.scala 355:14] + reg _T_1850 : UInt<1>, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when obuf_wr_en : @[Reg.scala 28:19] + _T_1850 <= obuf_sideeffect_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_sideeffect <= _T_1850 @[lsu_bus_buffer.scala 356:19] + reg obuf_sz : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when obuf_wr_en : @[Reg.scala 28:19] + obuf_sz <= obuf_sz_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + inst rvclkhdr_2 of rvclkhdr_26 @[lib.scala 368:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_2.io.en <= obuf_wr_en @[lib.scala 371:17] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_1851 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_1851 <= obuf_addr_in @[lib.scala 374:16] + obuf_addr <= _T_1851 @[lsu_bus_buffer.scala 358:13] + reg obuf_byteen : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when obuf_wr_en : @[Reg.scala 28:19] + obuf_byteen <= obuf_byteen_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + inst rvclkhdr_3 of rvclkhdr_27 @[lib.scala 368:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_3.io.en <= obuf_wr_en @[lib.scala 371:17] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg obuf_data : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + obuf_data <= obuf_data_in @[lib.scala 374:16] + reg _T_1852 : UInt, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 361:54] + _T_1852 <= obuf_wr_timer_in @[lsu_bus_buffer.scala 361:54] + obuf_wr_timer <= _T_1852 @[lsu_bus_buffer.scala 361:17] + wire WrPtr0_m : UInt<2> + WrPtr0_m <= UInt<1>("h00") + node _T_1853 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 364:65] + node _T_1854 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 365:30] + node _T_1855 = and(ibuf_valid, _T_1854) @[lsu_bus_buffer.scala 365:19] + node _T_1856 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 366:18] + node _T_1857 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 366:57] + node _T_1858 = and(io.ldst_dual_r, _T_1857) @[lsu_bus_buffer.scala 366:45] + node _T_1859 = or(_T_1856, _T_1858) @[lsu_bus_buffer.scala 366:27] + node _T_1860 = and(io.lsu_busreq_r, _T_1859) @[lsu_bus_buffer.scala 365:58] + node _T_1861 = or(_T_1855, _T_1860) @[lsu_bus_buffer.scala 365:39] + node _T_1862 = eq(_T_1861, UInt<1>("h00")) @[lsu_bus_buffer.scala 365:5] + node _T_1863 = and(_T_1853, _T_1862) @[lsu_bus_buffer.scala 364:76] + node _T_1864 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 364:65] + node _T_1865 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 365:30] + node _T_1866 = and(ibuf_valid, _T_1865) @[lsu_bus_buffer.scala 365:19] + node _T_1867 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 366:18] + node _T_1868 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 366:57] + node _T_1869 = and(io.ldst_dual_r, _T_1868) @[lsu_bus_buffer.scala 366:45] + node _T_1870 = or(_T_1867, _T_1869) @[lsu_bus_buffer.scala 366:27] + node _T_1871 = and(io.lsu_busreq_r, _T_1870) @[lsu_bus_buffer.scala 365:58] + node _T_1872 = or(_T_1866, _T_1871) @[lsu_bus_buffer.scala 365:39] + node _T_1873 = eq(_T_1872, UInt<1>("h00")) @[lsu_bus_buffer.scala 365:5] + node _T_1874 = and(_T_1864, _T_1873) @[lsu_bus_buffer.scala 364:76] + node _T_1875 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 364:65] + node _T_1876 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 365:30] + node _T_1877 = and(ibuf_valid, _T_1876) @[lsu_bus_buffer.scala 365:19] + node _T_1878 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 366:18] + node _T_1879 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 366:57] + node _T_1880 = and(io.ldst_dual_r, _T_1879) @[lsu_bus_buffer.scala 366:45] + node _T_1881 = or(_T_1878, _T_1880) @[lsu_bus_buffer.scala 366:27] + node _T_1882 = and(io.lsu_busreq_r, _T_1881) @[lsu_bus_buffer.scala 365:58] + node _T_1883 = or(_T_1877, _T_1882) @[lsu_bus_buffer.scala 365:39] + node _T_1884 = eq(_T_1883, UInt<1>("h00")) @[lsu_bus_buffer.scala 365:5] + node _T_1885 = and(_T_1875, _T_1884) @[lsu_bus_buffer.scala 364:76] + node _T_1886 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 364:65] + node _T_1887 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 365:30] + node _T_1888 = and(ibuf_valid, _T_1887) @[lsu_bus_buffer.scala 365:19] + node _T_1889 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 366:18] + node _T_1890 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 366:57] + node _T_1891 = and(io.ldst_dual_r, _T_1890) @[lsu_bus_buffer.scala 366:45] + node _T_1892 = or(_T_1889, _T_1891) @[lsu_bus_buffer.scala 366:27] + node _T_1893 = and(io.lsu_busreq_r, _T_1892) @[lsu_bus_buffer.scala 365:58] + node _T_1894 = or(_T_1888, _T_1893) @[lsu_bus_buffer.scala 365:39] + node _T_1895 = eq(_T_1894, UInt<1>("h00")) @[lsu_bus_buffer.scala 365:5] + node _T_1896 = and(_T_1886, _T_1895) @[lsu_bus_buffer.scala 364:76] + node _T_1897 = mux(_T_1896, UInt<2>("h03"), UInt<2>("h03")) @[Mux.scala 98:16] + node _T_1898 = mux(_T_1885, UInt<2>("h02"), _T_1897) @[Mux.scala 98:16] + node _T_1899 = mux(_T_1874, UInt<1>("h01"), _T_1898) @[Mux.scala 98:16] + node _T_1900 = mux(_T_1863, UInt<1>("h00"), _T_1899) @[Mux.scala 98:16] + WrPtr0_m <= _T_1900 @[lsu_bus_buffer.scala 364:12] + wire WrPtr1_m : UInt<2> + WrPtr1_m <= UInt<1>("h00") + node _T_1901 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 370:65] + node _T_1902 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 370:103] + node _T_1903 = and(ibuf_valid, _T_1902) @[lsu_bus_buffer.scala 370:92] + node _T_1904 = eq(WrPtr0_m, UInt<1>("h00")) @[lsu_bus_buffer.scala 371:33] + node _T_1905 = and(io.lsu_busreq_m, _T_1904) @[lsu_bus_buffer.scala 371:22] + node _T_1906 = or(_T_1903, _T_1905) @[lsu_bus_buffer.scala 370:112] + node _T_1907 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 372:36] + node _T_1908 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 373:34] + node _T_1909 = and(io.ldst_dual_r, _T_1908) @[lsu_bus_buffer.scala 373:23] + node _T_1910 = or(_T_1907, _T_1909) @[lsu_bus_buffer.scala 372:46] + node _T_1911 = and(io.lsu_busreq_r, _T_1910) @[lsu_bus_buffer.scala 372:22] + node _T_1912 = or(_T_1906, _T_1911) @[lsu_bus_buffer.scala 371:42] + node _T_1913 = eq(_T_1912, UInt<1>("h00")) @[lsu_bus_buffer.scala 370:78] + node _T_1914 = and(_T_1901, _T_1913) @[lsu_bus_buffer.scala 370:76] + node _T_1915 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 370:65] + node _T_1916 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 370:103] + node _T_1917 = and(ibuf_valid, _T_1916) @[lsu_bus_buffer.scala 370:92] + node _T_1918 = eq(WrPtr0_m, UInt<1>("h01")) @[lsu_bus_buffer.scala 371:33] + node _T_1919 = and(io.lsu_busreq_m, _T_1918) @[lsu_bus_buffer.scala 371:22] + node _T_1920 = or(_T_1917, _T_1919) @[lsu_bus_buffer.scala 370:112] + node _T_1921 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 372:36] + node _T_1922 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 373:34] + node _T_1923 = and(io.ldst_dual_r, _T_1922) @[lsu_bus_buffer.scala 373:23] + node _T_1924 = or(_T_1921, _T_1923) @[lsu_bus_buffer.scala 372:46] + node _T_1925 = and(io.lsu_busreq_r, _T_1924) @[lsu_bus_buffer.scala 372:22] + node _T_1926 = or(_T_1920, _T_1925) @[lsu_bus_buffer.scala 371:42] + node _T_1927 = eq(_T_1926, UInt<1>("h00")) @[lsu_bus_buffer.scala 370:78] + node _T_1928 = and(_T_1915, _T_1927) @[lsu_bus_buffer.scala 370:76] + node _T_1929 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 370:65] + node _T_1930 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 370:103] + node _T_1931 = and(ibuf_valid, _T_1930) @[lsu_bus_buffer.scala 370:92] + node _T_1932 = eq(WrPtr0_m, UInt<2>("h02")) @[lsu_bus_buffer.scala 371:33] + node _T_1933 = and(io.lsu_busreq_m, _T_1932) @[lsu_bus_buffer.scala 371:22] + node _T_1934 = or(_T_1931, _T_1933) @[lsu_bus_buffer.scala 370:112] + node _T_1935 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 372:36] + node _T_1936 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 373:34] + node _T_1937 = and(io.ldst_dual_r, _T_1936) @[lsu_bus_buffer.scala 373:23] + node _T_1938 = or(_T_1935, _T_1937) @[lsu_bus_buffer.scala 372:46] + node _T_1939 = and(io.lsu_busreq_r, _T_1938) @[lsu_bus_buffer.scala 372:22] + node _T_1940 = or(_T_1934, _T_1939) @[lsu_bus_buffer.scala 371:42] + node _T_1941 = eq(_T_1940, UInt<1>("h00")) @[lsu_bus_buffer.scala 370:78] + node _T_1942 = and(_T_1929, _T_1941) @[lsu_bus_buffer.scala 370:76] + node _T_1943 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 370:65] + node _T_1944 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 370:103] + node _T_1945 = and(ibuf_valid, _T_1944) @[lsu_bus_buffer.scala 370:92] + node _T_1946 = eq(WrPtr0_m, UInt<2>("h03")) @[lsu_bus_buffer.scala 371:33] + node _T_1947 = and(io.lsu_busreq_m, _T_1946) @[lsu_bus_buffer.scala 371:22] + node _T_1948 = or(_T_1945, _T_1947) @[lsu_bus_buffer.scala 370:112] + node _T_1949 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 372:36] + node _T_1950 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 373:34] + node _T_1951 = and(io.ldst_dual_r, _T_1950) @[lsu_bus_buffer.scala 373:23] + node _T_1952 = or(_T_1949, _T_1951) @[lsu_bus_buffer.scala 372:46] + node _T_1953 = and(io.lsu_busreq_r, _T_1952) @[lsu_bus_buffer.scala 372:22] + node _T_1954 = or(_T_1948, _T_1953) @[lsu_bus_buffer.scala 371:42] + node _T_1955 = eq(_T_1954, UInt<1>("h00")) @[lsu_bus_buffer.scala 370:78] + node _T_1956 = and(_T_1943, _T_1955) @[lsu_bus_buffer.scala 370:76] + node _T_1957 = mux(_T_1956, UInt<2>("h03"), UInt<2>("h03")) @[Mux.scala 98:16] + node _T_1958 = mux(_T_1942, UInt<2>("h02"), _T_1957) @[Mux.scala 98:16] + node _T_1959 = mux(_T_1928, UInt<1>("h01"), _T_1958) @[Mux.scala 98:16] + node _T_1960 = mux(_T_1914, UInt<1>("h00"), _T_1959) @[Mux.scala 98:16] + WrPtr1_m <= _T_1960 @[lsu_bus_buffer.scala 370:12] + wire buf_age : UInt<4>[4] @[lsu_bus_buffer.scala 375:21] + buf_age[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 376:11] + buf_age[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 376:11] + buf_age[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 376:11] + buf_age[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 376:11] + node _T_1961 = orr(buf_age[0]) @[lsu_bus_buffer.scala 378:58] + node _T_1962 = eq(_T_1961, UInt<1>("h00")) @[lsu_bus_buffer.scala 378:45] + node _T_1963 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 378:78] + node _T_1964 = and(_T_1962, _T_1963) @[lsu_bus_buffer.scala 378:63] + node _T_1965 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 378:90] + node _T_1966 = and(_T_1964, _T_1965) @[lsu_bus_buffer.scala 378:88] + node _T_1967 = orr(buf_age[1]) @[lsu_bus_buffer.scala 378:58] + node _T_1968 = eq(_T_1967, UInt<1>("h00")) @[lsu_bus_buffer.scala 378:45] + node _T_1969 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 378:78] + node _T_1970 = and(_T_1968, _T_1969) @[lsu_bus_buffer.scala 378:63] + node _T_1971 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 378:90] + node _T_1972 = and(_T_1970, _T_1971) @[lsu_bus_buffer.scala 378:88] + node _T_1973 = orr(buf_age[2]) @[lsu_bus_buffer.scala 378:58] + node _T_1974 = eq(_T_1973, UInt<1>("h00")) @[lsu_bus_buffer.scala 378:45] + node _T_1975 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 378:78] + node _T_1976 = and(_T_1974, _T_1975) @[lsu_bus_buffer.scala 378:63] + node _T_1977 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 378:90] + node _T_1978 = and(_T_1976, _T_1977) @[lsu_bus_buffer.scala 378:88] + node _T_1979 = orr(buf_age[3]) @[lsu_bus_buffer.scala 378:58] + node _T_1980 = eq(_T_1979, UInt<1>("h00")) @[lsu_bus_buffer.scala 378:45] + node _T_1981 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 378:78] + node _T_1982 = and(_T_1980, _T_1981) @[lsu_bus_buffer.scala 378:63] + node _T_1983 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 378:90] + node _T_1984 = and(_T_1982, _T_1983) @[lsu_bus_buffer.scala 378:88] + node _T_1985 = cat(_T_1984, _T_1978) @[Cat.scala 29:58] + node _T_1986 = cat(_T_1985, _T_1972) @[Cat.scala 29:58] + node CmdPtr0Dec = cat(_T_1986, _T_1966) @[Cat.scala 29:58] + node _T_1987 = not(CmdPtr0Dec) @[lsu_bus_buffer.scala 379:62] + node _T_1988 = and(buf_age[0], _T_1987) @[lsu_bus_buffer.scala 379:59] + node _T_1989 = orr(_T_1988) @[lsu_bus_buffer.scala 379:76] + node _T_1990 = eq(_T_1989, UInt<1>("h00")) @[lsu_bus_buffer.scala 379:45] + node _T_1991 = bits(CmdPtr0Dec, 0, 0) @[lsu_bus_buffer.scala 379:94] + node _T_1992 = eq(_T_1991, UInt<1>("h00")) @[lsu_bus_buffer.scala 379:83] + node _T_1993 = and(_T_1990, _T_1992) @[lsu_bus_buffer.scala 379:81] + node _T_1994 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 379:113] + node _T_1995 = and(_T_1993, _T_1994) @[lsu_bus_buffer.scala 379:98] + node _T_1996 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 379:125] + node _T_1997 = and(_T_1995, _T_1996) @[lsu_bus_buffer.scala 379:123] + node _T_1998 = not(CmdPtr0Dec) @[lsu_bus_buffer.scala 379:62] + node _T_1999 = and(buf_age[1], _T_1998) @[lsu_bus_buffer.scala 379:59] + node _T_2000 = orr(_T_1999) @[lsu_bus_buffer.scala 379:76] + node _T_2001 = eq(_T_2000, UInt<1>("h00")) @[lsu_bus_buffer.scala 379:45] + node _T_2002 = bits(CmdPtr0Dec, 1, 1) @[lsu_bus_buffer.scala 379:94] + node _T_2003 = eq(_T_2002, UInt<1>("h00")) @[lsu_bus_buffer.scala 379:83] + node _T_2004 = and(_T_2001, _T_2003) @[lsu_bus_buffer.scala 379:81] + node _T_2005 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 379:113] + node _T_2006 = and(_T_2004, _T_2005) @[lsu_bus_buffer.scala 379:98] + node _T_2007 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 379:125] + node _T_2008 = and(_T_2006, _T_2007) @[lsu_bus_buffer.scala 379:123] + node _T_2009 = not(CmdPtr0Dec) @[lsu_bus_buffer.scala 379:62] + node _T_2010 = and(buf_age[2], _T_2009) @[lsu_bus_buffer.scala 379:59] + node _T_2011 = orr(_T_2010) @[lsu_bus_buffer.scala 379:76] + node _T_2012 = eq(_T_2011, UInt<1>("h00")) @[lsu_bus_buffer.scala 379:45] + node _T_2013 = bits(CmdPtr0Dec, 2, 2) @[lsu_bus_buffer.scala 379:94] + node _T_2014 = eq(_T_2013, UInt<1>("h00")) @[lsu_bus_buffer.scala 379:83] + node _T_2015 = and(_T_2012, _T_2014) @[lsu_bus_buffer.scala 379:81] + node _T_2016 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 379:113] + node _T_2017 = and(_T_2015, _T_2016) @[lsu_bus_buffer.scala 379:98] + node _T_2018 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 379:125] + node _T_2019 = and(_T_2017, _T_2018) @[lsu_bus_buffer.scala 379:123] + node _T_2020 = not(CmdPtr0Dec) @[lsu_bus_buffer.scala 379:62] + node _T_2021 = and(buf_age[3], _T_2020) @[lsu_bus_buffer.scala 379:59] + node _T_2022 = orr(_T_2021) @[lsu_bus_buffer.scala 379:76] + node _T_2023 = eq(_T_2022, UInt<1>("h00")) @[lsu_bus_buffer.scala 379:45] + node _T_2024 = bits(CmdPtr0Dec, 3, 3) @[lsu_bus_buffer.scala 379:94] + node _T_2025 = eq(_T_2024, UInt<1>("h00")) @[lsu_bus_buffer.scala 379:83] + node _T_2026 = and(_T_2023, _T_2025) @[lsu_bus_buffer.scala 379:81] + node _T_2027 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 379:113] + node _T_2028 = and(_T_2026, _T_2027) @[lsu_bus_buffer.scala 379:98] + node _T_2029 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 379:125] + node _T_2030 = and(_T_2028, _T_2029) @[lsu_bus_buffer.scala 379:123] + node _T_2031 = cat(_T_2030, _T_2019) @[Cat.scala 29:58] + node _T_2032 = cat(_T_2031, _T_2008) @[Cat.scala 29:58] + node CmdPtr1Dec = cat(_T_2032, _T_1997) @[Cat.scala 29:58] + wire buf_rsp_pickage : UInt<4>[4] @[lsu_bus_buffer.scala 380:29] + buf_rsp_pickage[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 381:19] + buf_rsp_pickage[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 381:19] + buf_rsp_pickage[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 381:19] + buf_rsp_pickage[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 381:19] + node _T_2033 = orr(buf_rsp_pickage[0]) @[lsu_bus_buffer.scala 382:65] + node _T_2034 = eq(_T_2033, UInt<1>("h00")) @[lsu_bus_buffer.scala 382:44] + node _T_2035 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 382:85] + node _T_2036 = and(_T_2034, _T_2035) @[lsu_bus_buffer.scala 382:70] + node _T_2037 = orr(buf_rsp_pickage[1]) @[lsu_bus_buffer.scala 382:65] + node _T_2038 = eq(_T_2037, UInt<1>("h00")) @[lsu_bus_buffer.scala 382:44] + node _T_2039 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 382:85] + node _T_2040 = and(_T_2038, _T_2039) @[lsu_bus_buffer.scala 382:70] + node _T_2041 = orr(buf_rsp_pickage[2]) @[lsu_bus_buffer.scala 382:65] + node _T_2042 = eq(_T_2041, UInt<1>("h00")) @[lsu_bus_buffer.scala 382:44] + node _T_2043 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 382:85] + node _T_2044 = and(_T_2042, _T_2043) @[lsu_bus_buffer.scala 382:70] + node _T_2045 = orr(buf_rsp_pickage[3]) @[lsu_bus_buffer.scala 382:65] + node _T_2046 = eq(_T_2045, UInt<1>("h00")) @[lsu_bus_buffer.scala 382:44] + node _T_2047 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 382:85] + node _T_2048 = and(_T_2046, _T_2047) @[lsu_bus_buffer.scala 382:70] + node _T_2049 = cat(_T_2048, _T_2044) @[Cat.scala 29:58] + node _T_2050 = cat(_T_2049, _T_2040) @[Cat.scala 29:58] + node RspPtrDec = cat(_T_2050, _T_2036) @[Cat.scala 29:58] + node _T_2051 = orr(CmdPtr0Dec) @[lsu_bus_buffer.scala 383:31] + found_cmdptr0 <= _T_2051 @[lsu_bus_buffer.scala 383:17] + node _T_2052 = orr(CmdPtr1Dec) @[lsu_bus_buffer.scala 384:31] + found_cmdptr1 <= _T_2052 @[lsu_bus_buffer.scala 384:17] + wire RspPtr : UInt<2> + RspPtr <= UInt<1>("h00") + node _T_2053 = mux(UInt<1>("h00"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_2054 = cat(_T_2053, CmdPtr0Dec) @[Cat.scala 29:58] + node _T_2055 = bits(_T_2054, 4, 4) @[lsu_bus_buffer.scala 386:39] + node _T_2056 = bits(_T_2054, 5, 5) @[lsu_bus_buffer.scala 386:45] + node _T_2057 = or(_T_2055, _T_2056) @[lsu_bus_buffer.scala 386:42] + node _T_2058 = bits(_T_2054, 6, 6) @[lsu_bus_buffer.scala 386:51] + node _T_2059 = or(_T_2057, _T_2058) @[lsu_bus_buffer.scala 386:48] + node _T_2060 = bits(_T_2054, 7, 7) @[lsu_bus_buffer.scala 386:57] + node _T_2061 = or(_T_2059, _T_2060) @[lsu_bus_buffer.scala 386:54] + node _T_2062 = bits(_T_2054, 2, 2) @[lsu_bus_buffer.scala 386:64] + node _T_2063 = bits(_T_2054, 3, 3) @[lsu_bus_buffer.scala 386:70] + node _T_2064 = or(_T_2062, _T_2063) @[lsu_bus_buffer.scala 386:67] + node _T_2065 = bits(_T_2054, 6, 6) @[lsu_bus_buffer.scala 386:76] + node _T_2066 = or(_T_2064, _T_2065) @[lsu_bus_buffer.scala 386:73] + node _T_2067 = bits(_T_2054, 7, 7) @[lsu_bus_buffer.scala 386:82] + node _T_2068 = or(_T_2066, _T_2067) @[lsu_bus_buffer.scala 386:79] + node _T_2069 = bits(_T_2054, 1, 1) @[lsu_bus_buffer.scala 386:89] + node _T_2070 = bits(_T_2054, 3, 3) @[lsu_bus_buffer.scala 386:95] + node _T_2071 = or(_T_2069, _T_2070) @[lsu_bus_buffer.scala 386:92] + node _T_2072 = bits(_T_2054, 5, 5) @[lsu_bus_buffer.scala 386:101] + node _T_2073 = or(_T_2071, _T_2072) @[lsu_bus_buffer.scala 386:98] + node _T_2074 = bits(_T_2054, 7, 7) @[lsu_bus_buffer.scala 386:107] + node _T_2075 = or(_T_2073, _T_2074) @[lsu_bus_buffer.scala 386:104] + node _T_2076 = cat(_T_2061, _T_2068) @[Cat.scala 29:58] + node _T_2077 = cat(_T_2076, _T_2075) @[Cat.scala 29:58] + CmdPtr0 <= _T_2077 @[lsu_bus_buffer.scala 391:11] + node _T_2078 = mux(UInt<1>("h00"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_2079 = cat(_T_2078, CmdPtr1Dec) @[Cat.scala 29:58] + node _T_2080 = bits(_T_2079, 4, 4) @[lsu_bus_buffer.scala 386:39] + node _T_2081 = bits(_T_2079, 5, 5) @[lsu_bus_buffer.scala 386:45] + node _T_2082 = or(_T_2080, _T_2081) @[lsu_bus_buffer.scala 386:42] + node _T_2083 = bits(_T_2079, 6, 6) @[lsu_bus_buffer.scala 386:51] + node _T_2084 = or(_T_2082, _T_2083) @[lsu_bus_buffer.scala 386:48] + node _T_2085 = bits(_T_2079, 7, 7) @[lsu_bus_buffer.scala 386:57] + node _T_2086 = or(_T_2084, _T_2085) @[lsu_bus_buffer.scala 386:54] + node _T_2087 = bits(_T_2079, 2, 2) @[lsu_bus_buffer.scala 386:64] + node _T_2088 = bits(_T_2079, 3, 3) @[lsu_bus_buffer.scala 386:70] + node _T_2089 = or(_T_2087, _T_2088) @[lsu_bus_buffer.scala 386:67] + node _T_2090 = bits(_T_2079, 6, 6) @[lsu_bus_buffer.scala 386:76] + node _T_2091 = or(_T_2089, _T_2090) @[lsu_bus_buffer.scala 386:73] + node _T_2092 = bits(_T_2079, 7, 7) @[lsu_bus_buffer.scala 386:82] + node _T_2093 = or(_T_2091, _T_2092) @[lsu_bus_buffer.scala 386:79] + node _T_2094 = bits(_T_2079, 1, 1) @[lsu_bus_buffer.scala 386:89] + node _T_2095 = bits(_T_2079, 3, 3) @[lsu_bus_buffer.scala 386:95] + node _T_2096 = or(_T_2094, _T_2095) @[lsu_bus_buffer.scala 386:92] + node _T_2097 = bits(_T_2079, 5, 5) @[lsu_bus_buffer.scala 386:101] + node _T_2098 = or(_T_2096, _T_2097) @[lsu_bus_buffer.scala 386:98] + node _T_2099 = bits(_T_2079, 7, 7) @[lsu_bus_buffer.scala 386:107] + node _T_2100 = or(_T_2098, _T_2099) @[lsu_bus_buffer.scala 386:104] + node _T_2101 = cat(_T_2086, _T_2093) @[Cat.scala 29:58] + node _T_2102 = cat(_T_2101, _T_2100) @[Cat.scala 29:58] + CmdPtr1 <= _T_2102 @[lsu_bus_buffer.scala 393:11] + node _T_2103 = mux(UInt<1>("h00"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_2104 = cat(_T_2103, RspPtrDec) @[Cat.scala 29:58] + node _T_2105 = bits(_T_2104, 4, 4) @[lsu_bus_buffer.scala 386:39] + node _T_2106 = bits(_T_2104, 5, 5) @[lsu_bus_buffer.scala 386:45] + node _T_2107 = or(_T_2105, _T_2106) @[lsu_bus_buffer.scala 386:42] + node _T_2108 = bits(_T_2104, 6, 6) @[lsu_bus_buffer.scala 386:51] + node _T_2109 = or(_T_2107, _T_2108) @[lsu_bus_buffer.scala 386:48] + node _T_2110 = bits(_T_2104, 7, 7) @[lsu_bus_buffer.scala 386:57] + node _T_2111 = or(_T_2109, _T_2110) @[lsu_bus_buffer.scala 386:54] + node _T_2112 = bits(_T_2104, 2, 2) @[lsu_bus_buffer.scala 386:64] + node _T_2113 = bits(_T_2104, 3, 3) @[lsu_bus_buffer.scala 386:70] + node _T_2114 = or(_T_2112, _T_2113) @[lsu_bus_buffer.scala 386:67] + node _T_2115 = bits(_T_2104, 6, 6) @[lsu_bus_buffer.scala 386:76] + node _T_2116 = or(_T_2114, _T_2115) @[lsu_bus_buffer.scala 386:73] + node _T_2117 = bits(_T_2104, 7, 7) @[lsu_bus_buffer.scala 386:82] + node _T_2118 = or(_T_2116, _T_2117) @[lsu_bus_buffer.scala 386:79] + node _T_2119 = bits(_T_2104, 1, 1) @[lsu_bus_buffer.scala 386:89] + node _T_2120 = bits(_T_2104, 3, 3) @[lsu_bus_buffer.scala 386:95] + node _T_2121 = or(_T_2119, _T_2120) @[lsu_bus_buffer.scala 386:92] + node _T_2122 = bits(_T_2104, 5, 5) @[lsu_bus_buffer.scala 386:101] + node _T_2123 = or(_T_2121, _T_2122) @[lsu_bus_buffer.scala 386:98] + node _T_2124 = bits(_T_2104, 7, 7) @[lsu_bus_buffer.scala 386:107] + node _T_2125 = or(_T_2123, _T_2124) @[lsu_bus_buffer.scala 386:104] + node _T_2126 = cat(_T_2111, _T_2118) @[Cat.scala 29:58] + node _T_2127 = cat(_T_2126, _T_2125) @[Cat.scala 29:58] + RspPtr <= _T_2127 @[lsu_bus_buffer.scala 394:10] + wire buf_state_en : UInt<1>[4] @[lsu_bus_buffer.scala 395:26] + buf_state_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 396:16] + buf_state_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 396:16] + buf_state_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 396:16] + buf_state_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 396:16] + wire buf_rspageQ : UInt<4>[4] @[lsu_bus_buffer.scala 397:25] + buf_rspageQ[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 398:15] + buf_rspageQ[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 398:15] + buf_rspageQ[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 398:15] + buf_rspageQ[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 398:15] + wire buf_rspage_set : UInt<4>[4] @[lsu_bus_buffer.scala 399:28] + buf_rspage_set[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 400:18] + buf_rspage_set[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 400:18] + buf_rspage_set[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 400:18] + buf_rspage_set[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 400:18] + wire buf_rspage_in : UInt<4>[4] @[lsu_bus_buffer.scala 401:27] + buf_rspage_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 402:17] + buf_rspage_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 402:17] + buf_rspage_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 402:17] + buf_rspage_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 402:17] + wire buf_rspage : UInt<4>[4] @[lsu_bus_buffer.scala 403:24] + buf_rspage[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 404:14] + buf_rspage[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 404:14] + buf_rspage[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 404:14] + buf_rspage[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 404:14] + node _T_2128 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 406:83] + node _T_2129 = and(_T_2128, buf_state_en[0]) @[lsu_bus_buffer.scala 406:94] + node _T_2130 = eq(buf_state[0], UInt<3>("h01")) @[lsu_bus_buffer.scala 407:20] + node _T_2131 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 407:47] + node _T_2132 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 407:59] + node _T_2133 = and(_T_2131, _T_2132) @[lsu_bus_buffer.scala 407:57] + node _T_2134 = or(_T_2130, _T_2133) @[lsu_bus_buffer.scala 407:31] + node _T_2135 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:23] + node _T_2136 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:53] + node _T_2137 = and(_T_2135, _T_2136) @[lsu_bus_buffer.scala 408:41] + node _T_2138 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 408:83] + node _T_2139 = and(_T_2137, _T_2138) @[lsu_bus_buffer.scala 408:71] + node _T_2140 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 408:104] + node _T_2141 = and(_T_2139, _T_2140) @[lsu_bus_buffer.scala 408:92] + node _T_2142 = or(_T_2134, _T_2141) @[lsu_bus_buffer.scala 407:86] + node _T_2143 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 409:17] + node _T_2144 = and(_T_2143, io.ldst_dual_r) @[lsu_bus_buffer.scala 409:35] + node _T_2145 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 409:64] + node _T_2146 = and(_T_2144, _T_2145) @[lsu_bus_buffer.scala 409:52] + node _T_2147 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 409:85] + node _T_2148 = and(_T_2146, _T_2147) @[lsu_bus_buffer.scala 409:73] + node _T_2149 = or(_T_2142, _T_2148) @[lsu_bus_buffer.scala 408:114] + node _T_2150 = and(_T_2129, _T_2149) @[lsu_bus_buffer.scala 406:113] + node _T_2151 = bits(buf_age[0], 0, 0) @[lsu_bus_buffer.scala 409:109] + node _T_2152 = or(_T_2150, _T_2151) @[lsu_bus_buffer.scala 409:97] + node _T_2153 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 406:83] + node _T_2154 = and(_T_2153, buf_state_en[0]) @[lsu_bus_buffer.scala 406:94] + node _T_2155 = eq(buf_state[1], UInt<3>("h01")) @[lsu_bus_buffer.scala 407:20] + node _T_2156 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 407:47] + node _T_2157 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 407:59] + node _T_2158 = and(_T_2156, _T_2157) @[lsu_bus_buffer.scala 407:57] + node _T_2159 = or(_T_2155, _T_2158) @[lsu_bus_buffer.scala 407:31] + node _T_2160 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:23] + node _T_2161 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:53] + node _T_2162 = and(_T_2160, _T_2161) @[lsu_bus_buffer.scala 408:41] + node _T_2163 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 408:83] + node _T_2164 = and(_T_2162, _T_2163) @[lsu_bus_buffer.scala 408:71] + node _T_2165 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 408:104] + node _T_2166 = and(_T_2164, _T_2165) @[lsu_bus_buffer.scala 408:92] + node _T_2167 = or(_T_2159, _T_2166) @[lsu_bus_buffer.scala 407:86] + node _T_2168 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 409:17] + node _T_2169 = and(_T_2168, io.ldst_dual_r) @[lsu_bus_buffer.scala 409:35] + node _T_2170 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 409:64] + node _T_2171 = and(_T_2169, _T_2170) @[lsu_bus_buffer.scala 409:52] + node _T_2172 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 409:85] + node _T_2173 = and(_T_2171, _T_2172) @[lsu_bus_buffer.scala 409:73] + node _T_2174 = or(_T_2167, _T_2173) @[lsu_bus_buffer.scala 408:114] + node _T_2175 = and(_T_2154, _T_2174) @[lsu_bus_buffer.scala 406:113] + node _T_2176 = bits(buf_age[0], 1, 1) @[lsu_bus_buffer.scala 409:109] + node _T_2177 = or(_T_2175, _T_2176) @[lsu_bus_buffer.scala 409:97] + node _T_2178 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 406:83] + node _T_2179 = and(_T_2178, buf_state_en[0]) @[lsu_bus_buffer.scala 406:94] + node _T_2180 = eq(buf_state[2], UInt<3>("h01")) @[lsu_bus_buffer.scala 407:20] + node _T_2181 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 407:47] + node _T_2182 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 407:59] + node _T_2183 = and(_T_2181, _T_2182) @[lsu_bus_buffer.scala 407:57] + node _T_2184 = or(_T_2180, _T_2183) @[lsu_bus_buffer.scala 407:31] + node _T_2185 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:23] + node _T_2186 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:53] + node _T_2187 = and(_T_2185, _T_2186) @[lsu_bus_buffer.scala 408:41] + node _T_2188 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 408:83] + node _T_2189 = and(_T_2187, _T_2188) @[lsu_bus_buffer.scala 408:71] + node _T_2190 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 408:104] + node _T_2191 = and(_T_2189, _T_2190) @[lsu_bus_buffer.scala 408:92] + node _T_2192 = or(_T_2184, _T_2191) @[lsu_bus_buffer.scala 407:86] + node _T_2193 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 409:17] + node _T_2194 = and(_T_2193, io.ldst_dual_r) @[lsu_bus_buffer.scala 409:35] + node _T_2195 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 409:64] + node _T_2196 = and(_T_2194, _T_2195) @[lsu_bus_buffer.scala 409:52] + node _T_2197 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 409:85] + node _T_2198 = and(_T_2196, _T_2197) @[lsu_bus_buffer.scala 409:73] + node _T_2199 = or(_T_2192, _T_2198) @[lsu_bus_buffer.scala 408:114] + node _T_2200 = and(_T_2179, _T_2199) @[lsu_bus_buffer.scala 406:113] + node _T_2201 = bits(buf_age[0], 2, 2) @[lsu_bus_buffer.scala 409:109] + node _T_2202 = or(_T_2200, _T_2201) @[lsu_bus_buffer.scala 409:97] + node _T_2203 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 406:83] + node _T_2204 = and(_T_2203, buf_state_en[0]) @[lsu_bus_buffer.scala 406:94] + node _T_2205 = eq(buf_state[3], UInt<3>("h01")) @[lsu_bus_buffer.scala 407:20] + node _T_2206 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 407:47] + node _T_2207 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 407:59] + node _T_2208 = and(_T_2206, _T_2207) @[lsu_bus_buffer.scala 407:57] + node _T_2209 = or(_T_2205, _T_2208) @[lsu_bus_buffer.scala 407:31] + node _T_2210 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:23] + node _T_2211 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:53] + node _T_2212 = and(_T_2210, _T_2211) @[lsu_bus_buffer.scala 408:41] + node _T_2213 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 408:83] + node _T_2214 = and(_T_2212, _T_2213) @[lsu_bus_buffer.scala 408:71] + node _T_2215 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 408:104] + node _T_2216 = and(_T_2214, _T_2215) @[lsu_bus_buffer.scala 408:92] + node _T_2217 = or(_T_2209, _T_2216) @[lsu_bus_buffer.scala 407:86] + node _T_2218 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 409:17] + node _T_2219 = and(_T_2218, io.ldst_dual_r) @[lsu_bus_buffer.scala 409:35] + node _T_2220 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 409:64] + node _T_2221 = and(_T_2219, _T_2220) @[lsu_bus_buffer.scala 409:52] + node _T_2222 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 409:85] + node _T_2223 = and(_T_2221, _T_2222) @[lsu_bus_buffer.scala 409:73] + node _T_2224 = or(_T_2217, _T_2223) @[lsu_bus_buffer.scala 408:114] + node _T_2225 = and(_T_2204, _T_2224) @[lsu_bus_buffer.scala 406:113] + node _T_2226 = bits(buf_age[0], 3, 3) @[lsu_bus_buffer.scala 409:109] + node _T_2227 = or(_T_2225, _T_2226) @[lsu_bus_buffer.scala 409:97] + node _T_2228 = cat(_T_2227, _T_2202) @[Cat.scala 29:58] + node _T_2229 = cat(_T_2228, _T_2177) @[Cat.scala 29:58] + node buf_age_in_0 = cat(_T_2229, _T_2152) @[Cat.scala 29:58] + node _T_2230 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 406:83] + node _T_2231 = and(_T_2230, buf_state_en[1]) @[lsu_bus_buffer.scala 406:94] + node _T_2232 = eq(buf_state[0], UInt<3>("h01")) @[lsu_bus_buffer.scala 407:20] + node _T_2233 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 407:47] + node _T_2234 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 407:59] + node _T_2235 = and(_T_2233, _T_2234) @[lsu_bus_buffer.scala 407:57] + node _T_2236 = or(_T_2232, _T_2235) @[lsu_bus_buffer.scala 407:31] + node _T_2237 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:23] + node _T_2238 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:53] + node _T_2239 = and(_T_2237, _T_2238) @[lsu_bus_buffer.scala 408:41] + node _T_2240 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 408:83] + node _T_2241 = and(_T_2239, _T_2240) @[lsu_bus_buffer.scala 408:71] + node _T_2242 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 408:104] + node _T_2243 = and(_T_2241, _T_2242) @[lsu_bus_buffer.scala 408:92] + node _T_2244 = or(_T_2236, _T_2243) @[lsu_bus_buffer.scala 407:86] + node _T_2245 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 409:17] + node _T_2246 = and(_T_2245, io.ldst_dual_r) @[lsu_bus_buffer.scala 409:35] + node _T_2247 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 409:64] + node _T_2248 = and(_T_2246, _T_2247) @[lsu_bus_buffer.scala 409:52] + node _T_2249 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 409:85] + node _T_2250 = and(_T_2248, _T_2249) @[lsu_bus_buffer.scala 409:73] + node _T_2251 = or(_T_2244, _T_2250) @[lsu_bus_buffer.scala 408:114] + node _T_2252 = and(_T_2231, _T_2251) @[lsu_bus_buffer.scala 406:113] + node _T_2253 = bits(buf_age[1], 0, 0) @[lsu_bus_buffer.scala 409:109] + node _T_2254 = or(_T_2252, _T_2253) @[lsu_bus_buffer.scala 409:97] + node _T_2255 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 406:83] + node _T_2256 = and(_T_2255, buf_state_en[1]) @[lsu_bus_buffer.scala 406:94] + node _T_2257 = eq(buf_state[1], UInt<3>("h01")) @[lsu_bus_buffer.scala 407:20] + node _T_2258 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 407:47] + node _T_2259 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 407:59] + node _T_2260 = and(_T_2258, _T_2259) @[lsu_bus_buffer.scala 407:57] + node _T_2261 = or(_T_2257, _T_2260) @[lsu_bus_buffer.scala 407:31] + node _T_2262 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:23] + node _T_2263 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:53] + node _T_2264 = and(_T_2262, _T_2263) @[lsu_bus_buffer.scala 408:41] + node _T_2265 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 408:83] + node _T_2266 = and(_T_2264, _T_2265) @[lsu_bus_buffer.scala 408:71] + node _T_2267 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 408:104] + node _T_2268 = and(_T_2266, _T_2267) @[lsu_bus_buffer.scala 408:92] + node _T_2269 = or(_T_2261, _T_2268) @[lsu_bus_buffer.scala 407:86] + node _T_2270 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 409:17] + node _T_2271 = and(_T_2270, io.ldst_dual_r) @[lsu_bus_buffer.scala 409:35] + node _T_2272 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 409:64] + node _T_2273 = and(_T_2271, _T_2272) @[lsu_bus_buffer.scala 409:52] + node _T_2274 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 409:85] + node _T_2275 = and(_T_2273, _T_2274) @[lsu_bus_buffer.scala 409:73] + node _T_2276 = or(_T_2269, _T_2275) @[lsu_bus_buffer.scala 408:114] + node _T_2277 = and(_T_2256, _T_2276) @[lsu_bus_buffer.scala 406:113] + node _T_2278 = bits(buf_age[1], 1, 1) @[lsu_bus_buffer.scala 409:109] + node _T_2279 = or(_T_2277, _T_2278) @[lsu_bus_buffer.scala 409:97] + node _T_2280 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 406:83] + node _T_2281 = and(_T_2280, buf_state_en[1]) @[lsu_bus_buffer.scala 406:94] + node _T_2282 = eq(buf_state[2], UInt<3>("h01")) @[lsu_bus_buffer.scala 407:20] + node _T_2283 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 407:47] + node _T_2284 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 407:59] + node _T_2285 = and(_T_2283, _T_2284) @[lsu_bus_buffer.scala 407:57] + node _T_2286 = or(_T_2282, _T_2285) @[lsu_bus_buffer.scala 407:31] + node _T_2287 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:23] + node _T_2288 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:53] + node _T_2289 = and(_T_2287, _T_2288) @[lsu_bus_buffer.scala 408:41] + node _T_2290 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 408:83] + node _T_2291 = and(_T_2289, _T_2290) @[lsu_bus_buffer.scala 408:71] + node _T_2292 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 408:104] + node _T_2293 = and(_T_2291, _T_2292) @[lsu_bus_buffer.scala 408:92] + node _T_2294 = or(_T_2286, _T_2293) @[lsu_bus_buffer.scala 407:86] + node _T_2295 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 409:17] + node _T_2296 = and(_T_2295, io.ldst_dual_r) @[lsu_bus_buffer.scala 409:35] + node _T_2297 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 409:64] + node _T_2298 = and(_T_2296, _T_2297) @[lsu_bus_buffer.scala 409:52] + node _T_2299 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 409:85] + node _T_2300 = and(_T_2298, _T_2299) @[lsu_bus_buffer.scala 409:73] + node _T_2301 = or(_T_2294, _T_2300) @[lsu_bus_buffer.scala 408:114] + node _T_2302 = and(_T_2281, _T_2301) @[lsu_bus_buffer.scala 406:113] + node _T_2303 = bits(buf_age[1], 2, 2) @[lsu_bus_buffer.scala 409:109] + node _T_2304 = or(_T_2302, _T_2303) @[lsu_bus_buffer.scala 409:97] + node _T_2305 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 406:83] + node _T_2306 = and(_T_2305, buf_state_en[1]) @[lsu_bus_buffer.scala 406:94] + node _T_2307 = eq(buf_state[3], UInt<3>("h01")) @[lsu_bus_buffer.scala 407:20] + node _T_2308 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 407:47] + node _T_2309 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 407:59] + node _T_2310 = and(_T_2308, _T_2309) @[lsu_bus_buffer.scala 407:57] + node _T_2311 = or(_T_2307, _T_2310) @[lsu_bus_buffer.scala 407:31] + node _T_2312 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:23] + node _T_2313 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:53] + node _T_2314 = and(_T_2312, _T_2313) @[lsu_bus_buffer.scala 408:41] + node _T_2315 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 408:83] + node _T_2316 = and(_T_2314, _T_2315) @[lsu_bus_buffer.scala 408:71] + node _T_2317 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 408:104] + node _T_2318 = and(_T_2316, _T_2317) @[lsu_bus_buffer.scala 408:92] + node _T_2319 = or(_T_2311, _T_2318) @[lsu_bus_buffer.scala 407:86] + node _T_2320 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 409:17] + node _T_2321 = and(_T_2320, io.ldst_dual_r) @[lsu_bus_buffer.scala 409:35] + node _T_2322 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 409:64] + node _T_2323 = and(_T_2321, _T_2322) @[lsu_bus_buffer.scala 409:52] + node _T_2324 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 409:85] + node _T_2325 = and(_T_2323, _T_2324) @[lsu_bus_buffer.scala 409:73] + node _T_2326 = or(_T_2319, _T_2325) @[lsu_bus_buffer.scala 408:114] + node _T_2327 = and(_T_2306, _T_2326) @[lsu_bus_buffer.scala 406:113] + node _T_2328 = bits(buf_age[1], 3, 3) @[lsu_bus_buffer.scala 409:109] + node _T_2329 = or(_T_2327, _T_2328) @[lsu_bus_buffer.scala 409:97] + node _T_2330 = cat(_T_2329, _T_2304) @[Cat.scala 29:58] + node _T_2331 = cat(_T_2330, _T_2279) @[Cat.scala 29:58] + node buf_age_in_1 = cat(_T_2331, _T_2254) @[Cat.scala 29:58] + node _T_2332 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 406:83] + node _T_2333 = and(_T_2332, buf_state_en[2]) @[lsu_bus_buffer.scala 406:94] + node _T_2334 = eq(buf_state[0], UInt<3>("h01")) @[lsu_bus_buffer.scala 407:20] + node _T_2335 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 407:47] + node _T_2336 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 407:59] + node _T_2337 = and(_T_2335, _T_2336) @[lsu_bus_buffer.scala 407:57] + node _T_2338 = or(_T_2334, _T_2337) @[lsu_bus_buffer.scala 407:31] + node _T_2339 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:23] + node _T_2340 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:53] + node _T_2341 = and(_T_2339, _T_2340) @[lsu_bus_buffer.scala 408:41] + node _T_2342 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 408:83] + node _T_2343 = and(_T_2341, _T_2342) @[lsu_bus_buffer.scala 408:71] + node _T_2344 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 408:104] + node _T_2345 = and(_T_2343, _T_2344) @[lsu_bus_buffer.scala 408:92] + node _T_2346 = or(_T_2338, _T_2345) @[lsu_bus_buffer.scala 407:86] + node _T_2347 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 409:17] + node _T_2348 = and(_T_2347, io.ldst_dual_r) @[lsu_bus_buffer.scala 409:35] + node _T_2349 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 409:64] + node _T_2350 = and(_T_2348, _T_2349) @[lsu_bus_buffer.scala 409:52] + node _T_2351 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 409:85] + node _T_2352 = and(_T_2350, _T_2351) @[lsu_bus_buffer.scala 409:73] + node _T_2353 = or(_T_2346, _T_2352) @[lsu_bus_buffer.scala 408:114] + node _T_2354 = and(_T_2333, _T_2353) @[lsu_bus_buffer.scala 406:113] + node _T_2355 = bits(buf_age[2], 0, 0) @[lsu_bus_buffer.scala 409:109] + node _T_2356 = or(_T_2354, _T_2355) @[lsu_bus_buffer.scala 409:97] + node _T_2357 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 406:83] + node _T_2358 = and(_T_2357, buf_state_en[2]) @[lsu_bus_buffer.scala 406:94] + node _T_2359 = eq(buf_state[1], UInt<3>("h01")) @[lsu_bus_buffer.scala 407:20] + node _T_2360 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 407:47] + node _T_2361 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 407:59] + node _T_2362 = and(_T_2360, _T_2361) @[lsu_bus_buffer.scala 407:57] + node _T_2363 = or(_T_2359, _T_2362) @[lsu_bus_buffer.scala 407:31] + node _T_2364 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:23] + node _T_2365 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:53] + node _T_2366 = and(_T_2364, _T_2365) @[lsu_bus_buffer.scala 408:41] + node _T_2367 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 408:83] + node _T_2368 = and(_T_2366, _T_2367) @[lsu_bus_buffer.scala 408:71] + node _T_2369 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 408:104] + node _T_2370 = and(_T_2368, _T_2369) @[lsu_bus_buffer.scala 408:92] + node _T_2371 = or(_T_2363, _T_2370) @[lsu_bus_buffer.scala 407:86] + node _T_2372 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 409:17] + node _T_2373 = and(_T_2372, io.ldst_dual_r) @[lsu_bus_buffer.scala 409:35] + node _T_2374 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 409:64] + node _T_2375 = and(_T_2373, _T_2374) @[lsu_bus_buffer.scala 409:52] + node _T_2376 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 409:85] + node _T_2377 = and(_T_2375, _T_2376) @[lsu_bus_buffer.scala 409:73] + node _T_2378 = or(_T_2371, _T_2377) @[lsu_bus_buffer.scala 408:114] + node _T_2379 = and(_T_2358, _T_2378) @[lsu_bus_buffer.scala 406:113] + node _T_2380 = bits(buf_age[2], 1, 1) @[lsu_bus_buffer.scala 409:109] + node _T_2381 = or(_T_2379, _T_2380) @[lsu_bus_buffer.scala 409:97] + node _T_2382 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 406:83] + node _T_2383 = and(_T_2382, buf_state_en[2]) @[lsu_bus_buffer.scala 406:94] + node _T_2384 = eq(buf_state[2], UInt<3>("h01")) @[lsu_bus_buffer.scala 407:20] + node _T_2385 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 407:47] + node _T_2386 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 407:59] + node _T_2387 = and(_T_2385, _T_2386) @[lsu_bus_buffer.scala 407:57] + node _T_2388 = or(_T_2384, _T_2387) @[lsu_bus_buffer.scala 407:31] + node _T_2389 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:23] + node _T_2390 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:53] + node _T_2391 = and(_T_2389, _T_2390) @[lsu_bus_buffer.scala 408:41] + node _T_2392 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 408:83] + node _T_2393 = and(_T_2391, _T_2392) @[lsu_bus_buffer.scala 408:71] + node _T_2394 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 408:104] + node _T_2395 = and(_T_2393, _T_2394) @[lsu_bus_buffer.scala 408:92] + node _T_2396 = or(_T_2388, _T_2395) @[lsu_bus_buffer.scala 407:86] + node _T_2397 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 409:17] + node _T_2398 = and(_T_2397, io.ldst_dual_r) @[lsu_bus_buffer.scala 409:35] + node _T_2399 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 409:64] + node _T_2400 = and(_T_2398, _T_2399) @[lsu_bus_buffer.scala 409:52] + node _T_2401 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 409:85] + node _T_2402 = and(_T_2400, _T_2401) @[lsu_bus_buffer.scala 409:73] + node _T_2403 = or(_T_2396, _T_2402) @[lsu_bus_buffer.scala 408:114] + node _T_2404 = and(_T_2383, _T_2403) @[lsu_bus_buffer.scala 406:113] + node _T_2405 = bits(buf_age[2], 2, 2) @[lsu_bus_buffer.scala 409:109] + node _T_2406 = or(_T_2404, _T_2405) @[lsu_bus_buffer.scala 409:97] + node _T_2407 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 406:83] + node _T_2408 = and(_T_2407, buf_state_en[2]) @[lsu_bus_buffer.scala 406:94] + node _T_2409 = eq(buf_state[3], UInt<3>("h01")) @[lsu_bus_buffer.scala 407:20] + node _T_2410 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 407:47] + node _T_2411 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 407:59] + node _T_2412 = and(_T_2410, _T_2411) @[lsu_bus_buffer.scala 407:57] + node _T_2413 = or(_T_2409, _T_2412) @[lsu_bus_buffer.scala 407:31] + node _T_2414 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:23] + node _T_2415 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:53] + node _T_2416 = and(_T_2414, _T_2415) @[lsu_bus_buffer.scala 408:41] + node _T_2417 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 408:83] + node _T_2418 = and(_T_2416, _T_2417) @[lsu_bus_buffer.scala 408:71] + node _T_2419 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 408:104] + node _T_2420 = and(_T_2418, _T_2419) @[lsu_bus_buffer.scala 408:92] + node _T_2421 = or(_T_2413, _T_2420) @[lsu_bus_buffer.scala 407:86] + node _T_2422 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 409:17] + node _T_2423 = and(_T_2422, io.ldst_dual_r) @[lsu_bus_buffer.scala 409:35] + node _T_2424 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 409:64] + node _T_2425 = and(_T_2423, _T_2424) @[lsu_bus_buffer.scala 409:52] + node _T_2426 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 409:85] + node _T_2427 = and(_T_2425, _T_2426) @[lsu_bus_buffer.scala 409:73] + node _T_2428 = or(_T_2421, _T_2427) @[lsu_bus_buffer.scala 408:114] + node _T_2429 = and(_T_2408, _T_2428) @[lsu_bus_buffer.scala 406:113] + node _T_2430 = bits(buf_age[2], 3, 3) @[lsu_bus_buffer.scala 409:109] + node _T_2431 = or(_T_2429, _T_2430) @[lsu_bus_buffer.scala 409:97] + node _T_2432 = cat(_T_2431, _T_2406) @[Cat.scala 29:58] + node _T_2433 = cat(_T_2432, _T_2381) @[Cat.scala 29:58] + node buf_age_in_2 = cat(_T_2433, _T_2356) @[Cat.scala 29:58] + node _T_2434 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 406:83] + node _T_2435 = and(_T_2434, buf_state_en[3]) @[lsu_bus_buffer.scala 406:94] + node _T_2436 = eq(buf_state[0], UInt<3>("h01")) @[lsu_bus_buffer.scala 407:20] + node _T_2437 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 407:47] + node _T_2438 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 407:59] + node _T_2439 = and(_T_2437, _T_2438) @[lsu_bus_buffer.scala 407:57] + node _T_2440 = or(_T_2436, _T_2439) @[lsu_bus_buffer.scala 407:31] + node _T_2441 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:23] + node _T_2442 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:53] + node _T_2443 = and(_T_2441, _T_2442) @[lsu_bus_buffer.scala 408:41] + node _T_2444 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 408:83] + node _T_2445 = and(_T_2443, _T_2444) @[lsu_bus_buffer.scala 408:71] + node _T_2446 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 408:104] + node _T_2447 = and(_T_2445, _T_2446) @[lsu_bus_buffer.scala 408:92] + node _T_2448 = or(_T_2440, _T_2447) @[lsu_bus_buffer.scala 407:86] + node _T_2449 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 409:17] + node _T_2450 = and(_T_2449, io.ldst_dual_r) @[lsu_bus_buffer.scala 409:35] + node _T_2451 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 409:64] + node _T_2452 = and(_T_2450, _T_2451) @[lsu_bus_buffer.scala 409:52] + node _T_2453 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 409:85] + node _T_2454 = and(_T_2452, _T_2453) @[lsu_bus_buffer.scala 409:73] + node _T_2455 = or(_T_2448, _T_2454) @[lsu_bus_buffer.scala 408:114] + node _T_2456 = and(_T_2435, _T_2455) @[lsu_bus_buffer.scala 406:113] + node _T_2457 = bits(buf_age[3], 0, 0) @[lsu_bus_buffer.scala 409:109] + node _T_2458 = or(_T_2456, _T_2457) @[lsu_bus_buffer.scala 409:97] + node _T_2459 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 406:83] + node _T_2460 = and(_T_2459, buf_state_en[3]) @[lsu_bus_buffer.scala 406:94] + node _T_2461 = eq(buf_state[1], UInt<3>("h01")) @[lsu_bus_buffer.scala 407:20] + node _T_2462 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 407:47] + node _T_2463 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 407:59] + node _T_2464 = and(_T_2462, _T_2463) @[lsu_bus_buffer.scala 407:57] + node _T_2465 = or(_T_2461, _T_2464) @[lsu_bus_buffer.scala 407:31] + node _T_2466 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:23] + node _T_2467 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:53] + node _T_2468 = and(_T_2466, _T_2467) @[lsu_bus_buffer.scala 408:41] + node _T_2469 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 408:83] + node _T_2470 = and(_T_2468, _T_2469) @[lsu_bus_buffer.scala 408:71] + node _T_2471 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 408:104] + node _T_2472 = and(_T_2470, _T_2471) @[lsu_bus_buffer.scala 408:92] + node _T_2473 = or(_T_2465, _T_2472) @[lsu_bus_buffer.scala 407:86] + node _T_2474 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 409:17] + node _T_2475 = and(_T_2474, io.ldst_dual_r) @[lsu_bus_buffer.scala 409:35] + node _T_2476 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 409:64] + node _T_2477 = and(_T_2475, _T_2476) @[lsu_bus_buffer.scala 409:52] + node _T_2478 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 409:85] + node _T_2479 = and(_T_2477, _T_2478) @[lsu_bus_buffer.scala 409:73] + node _T_2480 = or(_T_2473, _T_2479) @[lsu_bus_buffer.scala 408:114] + node _T_2481 = and(_T_2460, _T_2480) @[lsu_bus_buffer.scala 406:113] + node _T_2482 = bits(buf_age[3], 1, 1) @[lsu_bus_buffer.scala 409:109] + node _T_2483 = or(_T_2481, _T_2482) @[lsu_bus_buffer.scala 409:97] + node _T_2484 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 406:83] + node _T_2485 = and(_T_2484, buf_state_en[3]) @[lsu_bus_buffer.scala 406:94] + node _T_2486 = eq(buf_state[2], UInt<3>("h01")) @[lsu_bus_buffer.scala 407:20] + node _T_2487 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 407:47] + node _T_2488 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 407:59] + node _T_2489 = and(_T_2487, _T_2488) @[lsu_bus_buffer.scala 407:57] + node _T_2490 = or(_T_2486, _T_2489) @[lsu_bus_buffer.scala 407:31] + node _T_2491 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:23] + node _T_2492 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:53] + node _T_2493 = and(_T_2491, _T_2492) @[lsu_bus_buffer.scala 408:41] + node _T_2494 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 408:83] + node _T_2495 = and(_T_2493, _T_2494) @[lsu_bus_buffer.scala 408:71] + node _T_2496 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 408:104] + node _T_2497 = and(_T_2495, _T_2496) @[lsu_bus_buffer.scala 408:92] + node _T_2498 = or(_T_2490, _T_2497) @[lsu_bus_buffer.scala 407:86] + node _T_2499 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 409:17] + node _T_2500 = and(_T_2499, io.ldst_dual_r) @[lsu_bus_buffer.scala 409:35] + node _T_2501 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 409:64] + node _T_2502 = and(_T_2500, _T_2501) @[lsu_bus_buffer.scala 409:52] + node _T_2503 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 409:85] + node _T_2504 = and(_T_2502, _T_2503) @[lsu_bus_buffer.scala 409:73] + node _T_2505 = or(_T_2498, _T_2504) @[lsu_bus_buffer.scala 408:114] + node _T_2506 = and(_T_2485, _T_2505) @[lsu_bus_buffer.scala 406:113] + node _T_2507 = bits(buf_age[3], 2, 2) @[lsu_bus_buffer.scala 409:109] + node _T_2508 = or(_T_2506, _T_2507) @[lsu_bus_buffer.scala 409:97] + node _T_2509 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 406:83] + node _T_2510 = and(_T_2509, buf_state_en[3]) @[lsu_bus_buffer.scala 406:94] + node _T_2511 = eq(buf_state[3], UInt<3>("h01")) @[lsu_bus_buffer.scala 407:20] + node _T_2512 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 407:47] + node _T_2513 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 407:59] + node _T_2514 = and(_T_2512, _T_2513) @[lsu_bus_buffer.scala 407:57] + node _T_2515 = or(_T_2511, _T_2514) @[lsu_bus_buffer.scala 407:31] + node _T_2516 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:23] + node _T_2517 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:53] + node _T_2518 = and(_T_2516, _T_2517) @[lsu_bus_buffer.scala 408:41] + node _T_2519 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 408:83] + node _T_2520 = and(_T_2518, _T_2519) @[lsu_bus_buffer.scala 408:71] + node _T_2521 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 408:104] + node _T_2522 = and(_T_2520, _T_2521) @[lsu_bus_buffer.scala 408:92] + node _T_2523 = or(_T_2515, _T_2522) @[lsu_bus_buffer.scala 407:86] + node _T_2524 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 409:17] + node _T_2525 = and(_T_2524, io.ldst_dual_r) @[lsu_bus_buffer.scala 409:35] + node _T_2526 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 409:64] + node _T_2527 = and(_T_2525, _T_2526) @[lsu_bus_buffer.scala 409:52] + node _T_2528 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 409:85] + node _T_2529 = and(_T_2527, _T_2528) @[lsu_bus_buffer.scala 409:73] + node _T_2530 = or(_T_2523, _T_2529) @[lsu_bus_buffer.scala 408:114] + node _T_2531 = and(_T_2510, _T_2530) @[lsu_bus_buffer.scala 406:113] + node _T_2532 = bits(buf_age[3], 3, 3) @[lsu_bus_buffer.scala 409:109] + node _T_2533 = or(_T_2531, _T_2532) @[lsu_bus_buffer.scala 409:97] + node _T_2534 = cat(_T_2533, _T_2508) @[Cat.scala 29:58] + node _T_2535 = cat(_T_2534, _T_2483) @[Cat.scala 29:58] + node buf_age_in_3 = cat(_T_2535, _T_2458) @[Cat.scala 29:58] + wire buf_ageQ : UInt<4>[4] @[lsu_bus_buffer.scala 410:22] + buf_ageQ[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 411:12] + buf_ageQ[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 411:12] + buf_ageQ[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 411:12] + buf_ageQ[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 411:12] + node _T_2536 = bits(buf_ageQ[0], 0, 0) @[lsu_bus_buffer.scala 412:72] + node _T_2537 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:93] + node _T_2538 = and(_T_2537, buf_cmd_state_bus_en[0]) @[lsu_bus_buffer.scala 412:103] + node _T_2539 = eq(_T_2538, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:78] + node _T_2540 = and(_T_2536, _T_2539) @[lsu_bus_buffer.scala 412:76] + node _T_2541 = bits(buf_ageQ[0], 1, 1) @[lsu_bus_buffer.scala 412:72] + node _T_2542 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:93] + node _T_2543 = and(_T_2542, buf_cmd_state_bus_en[1]) @[lsu_bus_buffer.scala 412:103] + node _T_2544 = eq(_T_2543, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:78] + node _T_2545 = and(_T_2541, _T_2544) @[lsu_bus_buffer.scala 412:76] + node _T_2546 = bits(buf_ageQ[0], 2, 2) @[lsu_bus_buffer.scala 412:72] + node _T_2547 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:93] + node _T_2548 = and(_T_2547, buf_cmd_state_bus_en[2]) @[lsu_bus_buffer.scala 412:103] + node _T_2549 = eq(_T_2548, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:78] + node _T_2550 = and(_T_2546, _T_2549) @[lsu_bus_buffer.scala 412:76] + node _T_2551 = bits(buf_ageQ[0], 3, 3) @[lsu_bus_buffer.scala 412:72] + node _T_2552 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:93] + node _T_2553 = and(_T_2552, buf_cmd_state_bus_en[3]) @[lsu_bus_buffer.scala 412:103] + node _T_2554 = eq(_T_2553, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:78] + node _T_2555 = and(_T_2551, _T_2554) @[lsu_bus_buffer.scala 412:76] + node _T_2556 = cat(_T_2555, _T_2550) @[Cat.scala 29:58] + node _T_2557 = cat(_T_2556, _T_2545) @[Cat.scala 29:58] + node _T_2558 = cat(_T_2557, _T_2540) @[Cat.scala 29:58] + node _T_2559 = bits(buf_ageQ[1], 0, 0) @[lsu_bus_buffer.scala 412:72] + node _T_2560 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:93] + node _T_2561 = and(_T_2560, buf_cmd_state_bus_en[0]) @[lsu_bus_buffer.scala 412:103] + node _T_2562 = eq(_T_2561, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:78] + node _T_2563 = and(_T_2559, _T_2562) @[lsu_bus_buffer.scala 412:76] + node _T_2564 = bits(buf_ageQ[1], 1, 1) @[lsu_bus_buffer.scala 412:72] + node _T_2565 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:93] + node _T_2566 = and(_T_2565, buf_cmd_state_bus_en[1]) @[lsu_bus_buffer.scala 412:103] + node _T_2567 = eq(_T_2566, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:78] + node _T_2568 = and(_T_2564, _T_2567) @[lsu_bus_buffer.scala 412:76] + node _T_2569 = bits(buf_ageQ[1], 2, 2) @[lsu_bus_buffer.scala 412:72] + node _T_2570 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:93] + node _T_2571 = and(_T_2570, buf_cmd_state_bus_en[2]) @[lsu_bus_buffer.scala 412:103] + node _T_2572 = eq(_T_2571, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:78] + node _T_2573 = and(_T_2569, _T_2572) @[lsu_bus_buffer.scala 412:76] + node _T_2574 = bits(buf_ageQ[1], 3, 3) @[lsu_bus_buffer.scala 412:72] + node _T_2575 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:93] + node _T_2576 = and(_T_2575, buf_cmd_state_bus_en[3]) @[lsu_bus_buffer.scala 412:103] + node _T_2577 = eq(_T_2576, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:78] + node _T_2578 = and(_T_2574, _T_2577) @[lsu_bus_buffer.scala 412:76] + node _T_2579 = cat(_T_2578, _T_2573) @[Cat.scala 29:58] + node _T_2580 = cat(_T_2579, _T_2568) @[Cat.scala 29:58] + node _T_2581 = cat(_T_2580, _T_2563) @[Cat.scala 29:58] + node _T_2582 = bits(buf_ageQ[2], 0, 0) @[lsu_bus_buffer.scala 412:72] + node _T_2583 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:93] + node _T_2584 = and(_T_2583, buf_cmd_state_bus_en[0]) @[lsu_bus_buffer.scala 412:103] + node _T_2585 = eq(_T_2584, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:78] + node _T_2586 = and(_T_2582, _T_2585) @[lsu_bus_buffer.scala 412:76] + node _T_2587 = bits(buf_ageQ[2], 1, 1) @[lsu_bus_buffer.scala 412:72] + node _T_2588 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:93] + node _T_2589 = and(_T_2588, buf_cmd_state_bus_en[1]) @[lsu_bus_buffer.scala 412:103] + node _T_2590 = eq(_T_2589, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:78] + node _T_2591 = and(_T_2587, _T_2590) @[lsu_bus_buffer.scala 412:76] + node _T_2592 = bits(buf_ageQ[2], 2, 2) @[lsu_bus_buffer.scala 412:72] + node _T_2593 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:93] + node _T_2594 = and(_T_2593, buf_cmd_state_bus_en[2]) @[lsu_bus_buffer.scala 412:103] + node _T_2595 = eq(_T_2594, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:78] + node _T_2596 = and(_T_2592, _T_2595) @[lsu_bus_buffer.scala 412:76] + node _T_2597 = bits(buf_ageQ[2], 3, 3) @[lsu_bus_buffer.scala 412:72] + node _T_2598 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:93] + node _T_2599 = and(_T_2598, buf_cmd_state_bus_en[3]) @[lsu_bus_buffer.scala 412:103] + node _T_2600 = eq(_T_2599, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:78] + node _T_2601 = and(_T_2597, _T_2600) @[lsu_bus_buffer.scala 412:76] + node _T_2602 = cat(_T_2601, _T_2596) @[Cat.scala 29:58] + node _T_2603 = cat(_T_2602, _T_2591) @[Cat.scala 29:58] + node _T_2604 = cat(_T_2603, _T_2586) @[Cat.scala 29:58] + node _T_2605 = bits(buf_ageQ[3], 0, 0) @[lsu_bus_buffer.scala 412:72] + node _T_2606 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:93] + node _T_2607 = and(_T_2606, buf_cmd_state_bus_en[0]) @[lsu_bus_buffer.scala 412:103] + node _T_2608 = eq(_T_2607, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:78] + node _T_2609 = and(_T_2605, _T_2608) @[lsu_bus_buffer.scala 412:76] + node _T_2610 = bits(buf_ageQ[3], 1, 1) @[lsu_bus_buffer.scala 412:72] + node _T_2611 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:93] + node _T_2612 = and(_T_2611, buf_cmd_state_bus_en[1]) @[lsu_bus_buffer.scala 412:103] + node _T_2613 = eq(_T_2612, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:78] + node _T_2614 = and(_T_2610, _T_2613) @[lsu_bus_buffer.scala 412:76] + node _T_2615 = bits(buf_ageQ[3], 2, 2) @[lsu_bus_buffer.scala 412:72] + node _T_2616 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:93] + node _T_2617 = and(_T_2616, buf_cmd_state_bus_en[2]) @[lsu_bus_buffer.scala 412:103] + node _T_2618 = eq(_T_2617, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:78] + node _T_2619 = and(_T_2615, _T_2618) @[lsu_bus_buffer.scala 412:76] + node _T_2620 = bits(buf_ageQ[3], 3, 3) @[lsu_bus_buffer.scala 412:72] + node _T_2621 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:93] + node _T_2622 = and(_T_2621, buf_cmd_state_bus_en[3]) @[lsu_bus_buffer.scala 412:103] + node _T_2623 = eq(_T_2622, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:78] + node _T_2624 = and(_T_2620, _T_2623) @[lsu_bus_buffer.scala 412:76] + node _T_2625 = cat(_T_2624, _T_2619) @[Cat.scala 29:58] + node _T_2626 = cat(_T_2625, _T_2614) @[Cat.scala 29:58] + node _T_2627 = cat(_T_2626, _T_2609) @[Cat.scala 29:58] + buf_age[0] <= _T_2558 @[lsu_bus_buffer.scala 412:11] + buf_age[1] <= _T_2581 @[lsu_bus_buffer.scala 412:11] + buf_age[2] <= _T_2604 @[lsu_bus_buffer.scala 412:11] + buf_age[3] <= _T_2627 @[lsu_bus_buffer.scala 412:11] + node _T_2628 = eq(UInt<1>("h00"), UInt<1>("h00")) @[lsu_bus_buffer.scala 413:76] + node _T_2629 = bits(buf_age[0], 0, 0) @[lsu_bus_buffer.scala 413:100] + node _T_2630 = eq(_T_2629, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:89] + node _T_2631 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 413:119] + node _T_2632 = and(_T_2630, _T_2631) @[lsu_bus_buffer.scala 413:104] + node _T_2633 = mux(_T_2628, UInt<1>("h00"), _T_2632) @[lsu_bus_buffer.scala 413:72] + node _T_2634 = eq(UInt<1>("h00"), UInt<1>("h01")) @[lsu_bus_buffer.scala 413:76] + node _T_2635 = bits(buf_age[0], 1, 1) @[lsu_bus_buffer.scala 413:100] + node _T_2636 = eq(_T_2635, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:89] + node _T_2637 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 413:119] + node _T_2638 = and(_T_2636, _T_2637) @[lsu_bus_buffer.scala 413:104] + node _T_2639 = mux(_T_2634, UInt<1>("h00"), _T_2638) @[lsu_bus_buffer.scala 413:72] + node _T_2640 = eq(UInt<1>("h00"), UInt<2>("h02")) @[lsu_bus_buffer.scala 413:76] + node _T_2641 = bits(buf_age[0], 2, 2) @[lsu_bus_buffer.scala 413:100] + node _T_2642 = eq(_T_2641, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:89] + node _T_2643 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 413:119] + node _T_2644 = and(_T_2642, _T_2643) @[lsu_bus_buffer.scala 413:104] + node _T_2645 = mux(_T_2640, UInt<1>("h00"), _T_2644) @[lsu_bus_buffer.scala 413:72] + node _T_2646 = eq(UInt<1>("h00"), UInt<2>("h03")) @[lsu_bus_buffer.scala 413:76] + node _T_2647 = bits(buf_age[0], 3, 3) @[lsu_bus_buffer.scala 413:100] + node _T_2648 = eq(_T_2647, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:89] + node _T_2649 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 413:119] + node _T_2650 = and(_T_2648, _T_2649) @[lsu_bus_buffer.scala 413:104] + node _T_2651 = mux(_T_2646, UInt<1>("h00"), _T_2650) @[lsu_bus_buffer.scala 413:72] + node _T_2652 = cat(_T_2651, _T_2645) @[Cat.scala 29:58] + node _T_2653 = cat(_T_2652, _T_2639) @[Cat.scala 29:58] + node _T_2654 = cat(_T_2653, _T_2633) @[Cat.scala 29:58] + node _T_2655 = eq(UInt<1>("h01"), UInt<1>("h00")) @[lsu_bus_buffer.scala 413:76] + node _T_2656 = bits(buf_age[1], 0, 0) @[lsu_bus_buffer.scala 413:100] + node _T_2657 = eq(_T_2656, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:89] + node _T_2658 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 413:119] + node _T_2659 = and(_T_2657, _T_2658) @[lsu_bus_buffer.scala 413:104] + node _T_2660 = mux(_T_2655, UInt<1>("h00"), _T_2659) @[lsu_bus_buffer.scala 413:72] + node _T_2661 = eq(UInt<1>("h01"), UInt<1>("h01")) @[lsu_bus_buffer.scala 413:76] + node _T_2662 = bits(buf_age[1], 1, 1) @[lsu_bus_buffer.scala 413:100] + node _T_2663 = eq(_T_2662, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:89] + node _T_2664 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 413:119] + node _T_2665 = and(_T_2663, _T_2664) @[lsu_bus_buffer.scala 413:104] + node _T_2666 = mux(_T_2661, UInt<1>("h00"), _T_2665) @[lsu_bus_buffer.scala 413:72] + node _T_2667 = eq(UInt<1>("h01"), UInt<2>("h02")) @[lsu_bus_buffer.scala 413:76] + node _T_2668 = bits(buf_age[1], 2, 2) @[lsu_bus_buffer.scala 413:100] + node _T_2669 = eq(_T_2668, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:89] + node _T_2670 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 413:119] + node _T_2671 = and(_T_2669, _T_2670) @[lsu_bus_buffer.scala 413:104] + node _T_2672 = mux(_T_2667, UInt<1>("h00"), _T_2671) @[lsu_bus_buffer.scala 413:72] + node _T_2673 = eq(UInt<1>("h01"), UInt<2>("h03")) @[lsu_bus_buffer.scala 413:76] + node _T_2674 = bits(buf_age[1], 3, 3) @[lsu_bus_buffer.scala 413:100] + node _T_2675 = eq(_T_2674, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:89] + node _T_2676 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 413:119] + node _T_2677 = and(_T_2675, _T_2676) @[lsu_bus_buffer.scala 413:104] + node _T_2678 = mux(_T_2673, UInt<1>("h00"), _T_2677) @[lsu_bus_buffer.scala 413:72] + node _T_2679 = cat(_T_2678, _T_2672) @[Cat.scala 29:58] + node _T_2680 = cat(_T_2679, _T_2666) @[Cat.scala 29:58] + node _T_2681 = cat(_T_2680, _T_2660) @[Cat.scala 29:58] + node _T_2682 = eq(UInt<2>("h02"), UInt<1>("h00")) @[lsu_bus_buffer.scala 413:76] + node _T_2683 = bits(buf_age[2], 0, 0) @[lsu_bus_buffer.scala 413:100] + node _T_2684 = eq(_T_2683, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:89] + node _T_2685 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 413:119] + node _T_2686 = and(_T_2684, _T_2685) @[lsu_bus_buffer.scala 413:104] + node _T_2687 = mux(_T_2682, UInt<1>("h00"), _T_2686) @[lsu_bus_buffer.scala 413:72] + node _T_2688 = eq(UInt<2>("h02"), UInt<1>("h01")) @[lsu_bus_buffer.scala 413:76] + node _T_2689 = bits(buf_age[2], 1, 1) @[lsu_bus_buffer.scala 413:100] + node _T_2690 = eq(_T_2689, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:89] + node _T_2691 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 413:119] + node _T_2692 = and(_T_2690, _T_2691) @[lsu_bus_buffer.scala 413:104] + node _T_2693 = mux(_T_2688, UInt<1>("h00"), _T_2692) @[lsu_bus_buffer.scala 413:72] + node _T_2694 = eq(UInt<2>("h02"), UInt<2>("h02")) @[lsu_bus_buffer.scala 413:76] + node _T_2695 = bits(buf_age[2], 2, 2) @[lsu_bus_buffer.scala 413:100] + node _T_2696 = eq(_T_2695, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:89] + node _T_2697 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 413:119] + node _T_2698 = and(_T_2696, _T_2697) @[lsu_bus_buffer.scala 413:104] + node _T_2699 = mux(_T_2694, UInt<1>("h00"), _T_2698) @[lsu_bus_buffer.scala 413:72] + node _T_2700 = eq(UInt<2>("h02"), UInt<2>("h03")) @[lsu_bus_buffer.scala 413:76] + node _T_2701 = bits(buf_age[2], 3, 3) @[lsu_bus_buffer.scala 413:100] + node _T_2702 = eq(_T_2701, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:89] + node _T_2703 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 413:119] + node _T_2704 = and(_T_2702, _T_2703) @[lsu_bus_buffer.scala 413:104] + node _T_2705 = mux(_T_2700, UInt<1>("h00"), _T_2704) @[lsu_bus_buffer.scala 413:72] + node _T_2706 = cat(_T_2705, _T_2699) @[Cat.scala 29:58] + node _T_2707 = cat(_T_2706, _T_2693) @[Cat.scala 29:58] + node _T_2708 = cat(_T_2707, _T_2687) @[Cat.scala 29:58] + node _T_2709 = eq(UInt<2>("h03"), UInt<1>("h00")) @[lsu_bus_buffer.scala 413:76] + node _T_2710 = bits(buf_age[3], 0, 0) @[lsu_bus_buffer.scala 413:100] + node _T_2711 = eq(_T_2710, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:89] + node _T_2712 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 413:119] + node _T_2713 = and(_T_2711, _T_2712) @[lsu_bus_buffer.scala 413:104] + node _T_2714 = mux(_T_2709, UInt<1>("h00"), _T_2713) @[lsu_bus_buffer.scala 413:72] + node _T_2715 = eq(UInt<2>("h03"), UInt<1>("h01")) @[lsu_bus_buffer.scala 413:76] + node _T_2716 = bits(buf_age[3], 1, 1) @[lsu_bus_buffer.scala 413:100] + node _T_2717 = eq(_T_2716, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:89] + node _T_2718 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 413:119] + node _T_2719 = and(_T_2717, _T_2718) @[lsu_bus_buffer.scala 413:104] + node _T_2720 = mux(_T_2715, UInt<1>("h00"), _T_2719) @[lsu_bus_buffer.scala 413:72] + node _T_2721 = eq(UInt<2>("h03"), UInt<2>("h02")) @[lsu_bus_buffer.scala 413:76] + node _T_2722 = bits(buf_age[3], 2, 2) @[lsu_bus_buffer.scala 413:100] + node _T_2723 = eq(_T_2722, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:89] + node _T_2724 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 413:119] + node _T_2725 = and(_T_2723, _T_2724) @[lsu_bus_buffer.scala 413:104] + node _T_2726 = mux(_T_2721, UInt<1>("h00"), _T_2725) @[lsu_bus_buffer.scala 413:72] + node _T_2727 = eq(UInt<2>("h03"), UInt<2>("h03")) @[lsu_bus_buffer.scala 413:76] + node _T_2728 = bits(buf_age[3], 3, 3) @[lsu_bus_buffer.scala 413:100] + node _T_2729 = eq(_T_2728, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:89] + node _T_2730 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 413:119] + node _T_2731 = and(_T_2729, _T_2730) @[lsu_bus_buffer.scala 413:104] + node _T_2732 = mux(_T_2727, UInt<1>("h00"), _T_2731) @[lsu_bus_buffer.scala 413:72] + node _T_2733 = cat(_T_2732, _T_2726) @[Cat.scala 29:58] + node _T_2734 = cat(_T_2733, _T_2720) @[Cat.scala 29:58] + node _T_2735 = cat(_T_2734, _T_2714) @[Cat.scala 29:58] + buf_age_younger[0] <= _T_2654 @[lsu_bus_buffer.scala 413:19] + buf_age_younger[1] <= _T_2681 @[lsu_bus_buffer.scala 413:19] + buf_age_younger[2] <= _T_2708 @[lsu_bus_buffer.scala 413:19] + buf_age_younger[3] <= _T_2735 @[lsu_bus_buffer.scala 413:19] + node _T_2736 = bits(buf_rspageQ[0], 0, 0) @[lsu_bus_buffer.scala 414:83] + node _T_2737 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 414:102] + node _T_2738 = and(_T_2736, _T_2737) @[lsu_bus_buffer.scala 414:87] + node _T_2739 = bits(buf_rspageQ[0], 1, 1) @[lsu_bus_buffer.scala 414:83] + node _T_2740 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 414:102] + node _T_2741 = and(_T_2739, _T_2740) @[lsu_bus_buffer.scala 414:87] + node _T_2742 = bits(buf_rspageQ[0], 2, 2) @[lsu_bus_buffer.scala 414:83] + node _T_2743 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 414:102] + node _T_2744 = and(_T_2742, _T_2743) @[lsu_bus_buffer.scala 414:87] + node _T_2745 = bits(buf_rspageQ[0], 3, 3) @[lsu_bus_buffer.scala 414:83] + node _T_2746 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 414:102] + node _T_2747 = and(_T_2745, _T_2746) @[lsu_bus_buffer.scala 414:87] + node _T_2748 = cat(_T_2747, _T_2744) @[Cat.scala 29:58] + node _T_2749 = cat(_T_2748, _T_2741) @[Cat.scala 29:58] + node _T_2750 = cat(_T_2749, _T_2738) @[Cat.scala 29:58] + node _T_2751 = bits(buf_rspageQ[1], 0, 0) @[lsu_bus_buffer.scala 414:83] + node _T_2752 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 414:102] + node _T_2753 = and(_T_2751, _T_2752) @[lsu_bus_buffer.scala 414:87] + node _T_2754 = bits(buf_rspageQ[1], 1, 1) @[lsu_bus_buffer.scala 414:83] + node _T_2755 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 414:102] + node _T_2756 = and(_T_2754, _T_2755) @[lsu_bus_buffer.scala 414:87] + node _T_2757 = bits(buf_rspageQ[1], 2, 2) @[lsu_bus_buffer.scala 414:83] + node _T_2758 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 414:102] + node _T_2759 = and(_T_2757, _T_2758) @[lsu_bus_buffer.scala 414:87] + node _T_2760 = bits(buf_rspageQ[1], 3, 3) @[lsu_bus_buffer.scala 414:83] + node _T_2761 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 414:102] + node _T_2762 = and(_T_2760, _T_2761) @[lsu_bus_buffer.scala 414:87] + node _T_2763 = cat(_T_2762, _T_2759) @[Cat.scala 29:58] + node _T_2764 = cat(_T_2763, _T_2756) @[Cat.scala 29:58] + node _T_2765 = cat(_T_2764, _T_2753) @[Cat.scala 29:58] + node _T_2766 = bits(buf_rspageQ[2], 0, 0) @[lsu_bus_buffer.scala 414:83] + node _T_2767 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 414:102] + node _T_2768 = and(_T_2766, _T_2767) @[lsu_bus_buffer.scala 414:87] + node _T_2769 = bits(buf_rspageQ[2], 1, 1) @[lsu_bus_buffer.scala 414:83] + node _T_2770 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 414:102] + node _T_2771 = and(_T_2769, _T_2770) @[lsu_bus_buffer.scala 414:87] + node _T_2772 = bits(buf_rspageQ[2], 2, 2) @[lsu_bus_buffer.scala 414:83] + node _T_2773 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 414:102] + node _T_2774 = and(_T_2772, _T_2773) @[lsu_bus_buffer.scala 414:87] + node _T_2775 = bits(buf_rspageQ[2], 3, 3) @[lsu_bus_buffer.scala 414:83] + node _T_2776 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 414:102] + node _T_2777 = and(_T_2775, _T_2776) @[lsu_bus_buffer.scala 414:87] + node _T_2778 = cat(_T_2777, _T_2774) @[Cat.scala 29:58] + node _T_2779 = cat(_T_2778, _T_2771) @[Cat.scala 29:58] + node _T_2780 = cat(_T_2779, _T_2768) @[Cat.scala 29:58] + node _T_2781 = bits(buf_rspageQ[3], 0, 0) @[lsu_bus_buffer.scala 414:83] + node _T_2782 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 414:102] + node _T_2783 = and(_T_2781, _T_2782) @[lsu_bus_buffer.scala 414:87] + node _T_2784 = bits(buf_rspageQ[3], 1, 1) @[lsu_bus_buffer.scala 414:83] + node _T_2785 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 414:102] + node _T_2786 = and(_T_2784, _T_2785) @[lsu_bus_buffer.scala 414:87] + node _T_2787 = bits(buf_rspageQ[3], 2, 2) @[lsu_bus_buffer.scala 414:83] + node _T_2788 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 414:102] + node _T_2789 = and(_T_2787, _T_2788) @[lsu_bus_buffer.scala 414:87] + node _T_2790 = bits(buf_rspageQ[3], 3, 3) @[lsu_bus_buffer.scala 414:83] + node _T_2791 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 414:102] + node _T_2792 = and(_T_2790, _T_2791) @[lsu_bus_buffer.scala 414:87] + node _T_2793 = cat(_T_2792, _T_2789) @[Cat.scala 29:58] + node _T_2794 = cat(_T_2793, _T_2786) @[Cat.scala 29:58] + node _T_2795 = cat(_T_2794, _T_2783) @[Cat.scala 29:58] + buf_rsp_pickage[0] <= _T_2750 @[lsu_bus_buffer.scala 414:19] + buf_rsp_pickage[1] <= _T_2765 @[lsu_bus_buffer.scala 414:19] + buf_rsp_pickage[2] <= _T_2780 @[lsu_bus_buffer.scala 414:19] + buf_rsp_pickage[3] <= _T_2795 @[lsu_bus_buffer.scala 414:19] + node _T_2796 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:82] + node _T_2797 = and(_T_2796, buf_state_en[0]) @[lsu_bus_buffer.scala 416:93] + node _T_2798 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 417:21] + node _T_2799 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 417:47] + node _T_2800 = or(_T_2798, _T_2799) @[lsu_bus_buffer.scala 417:32] + node _T_2801 = eq(_T_2800, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:6] + node _T_2802 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:23] + node _T_2803 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:53] + node _T_2804 = and(_T_2802, _T_2803) @[lsu_bus_buffer.scala 418:41] + node _T_2805 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:82] + node _T_2806 = and(_T_2804, _T_2805) @[lsu_bus_buffer.scala 418:71] + node _T_2807 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:101] + node _T_2808 = and(_T_2806, _T_2807) @[lsu_bus_buffer.scala 418:90] + node _T_2809 = or(_T_2801, _T_2808) @[lsu_bus_buffer.scala 417:59] + node _T_2810 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 419:17] + node _T_2811 = and(_T_2810, io.ldst_dual_r) @[lsu_bus_buffer.scala 419:35] + node _T_2812 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 419:63] + node _T_2813 = and(_T_2811, _T_2812) @[lsu_bus_buffer.scala 419:52] + node _T_2814 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 419:82] + node _T_2815 = and(_T_2813, _T_2814) @[lsu_bus_buffer.scala 419:71] + node _T_2816 = or(_T_2809, _T_2815) @[lsu_bus_buffer.scala 418:110] + node _T_2817 = and(_T_2797, _T_2816) @[lsu_bus_buffer.scala 416:112] + node _T_2818 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:82] + node _T_2819 = and(_T_2818, buf_state_en[0]) @[lsu_bus_buffer.scala 416:93] + node _T_2820 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 417:21] + node _T_2821 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 417:47] + node _T_2822 = or(_T_2820, _T_2821) @[lsu_bus_buffer.scala 417:32] + node _T_2823 = eq(_T_2822, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:6] + node _T_2824 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:23] + node _T_2825 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:53] + node _T_2826 = and(_T_2824, _T_2825) @[lsu_bus_buffer.scala 418:41] + node _T_2827 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:82] + node _T_2828 = and(_T_2826, _T_2827) @[lsu_bus_buffer.scala 418:71] + node _T_2829 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 418:101] + node _T_2830 = and(_T_2828, _T_2829) @[lsu_bus_buffer.scala 418:90] + node _T_2831 = or(_T_2823, _T_2830) @[lsu_bus_buffer.scala 417:59] + node _T_2832 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 419:17] + node _T_2833 = and(_T_2832, io.ldst_dual_r) @[lsu_bus_buffer.scala 419:35] + node _T_2834 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 419:63] + node _T_2835 = and(_T_2833, _T_2834) @[lsu_bus_buffer.scala 419:52] + node _T_2836 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 419:82] + node _T_2837 = and(_T_2835, _T_2836) @[lsu_bus_buffer.scala 419:71] + node _T_2838 = or(_T_2831, _T_2837) @[lsu_bus_buffer.scala 418:110] + node _T_2839 = and(_T_2819, _T_2838) @[lsu_bus_buffer.scala 416:112] + node _T_2840 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:82] + node _T_2841 = and(_T_2840, buf_state_en[0]) @[lsu_bus_buffer.scala 416:93] + node _T_2842 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 417:21] + node _T_2843 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 417:47] + node _T_2844 = or(_T_2842, _T_2843) @[lsu_bus_buffer.scala 417:32] + node _T_2845 = eq(_T_2844, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:6] + node _T_2846 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:23] + node _T_2847 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:53] + node _T_2848 = and(_T_2846, _T_2847) @[lsu_bus_buffer.scala 418:41] + node _T_2849 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:82] + node _T_2850 = and(_T_2848, _T_2849) @[lsu_bus_buffer.scala 418:71] + node _T_2851 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 418:101] + node _T_2852 = and(_T_2850, _T_2851) @[lsu_bus_buffer.scala 418:90] + node _T_2853 = or(_T_2845, _T_2852) @[lsu_bus_buffer.scala 417:59] + node _T_2854 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 419:17] + node _T_2855 = and(_T_2854, io.ldst_dual_r) @[lsu_bus_buffer.scala 419:35] + node _T_2856 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 419:63] + node _T_2857 = and(_T_2855, _T_2856) @[lsu_bus_buffer.scala 419:52] + node _T_2858 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 419:82] + node _T_2859 = and(_T_2857, _T_2858) @[lsu_bus_buffer.scala 419:71] + node _T_2860 = or(_T_2853, _T_2859) @[lsu_bus_buffer.scala 418:110] + node _T_2861 = and(_T_2841, _T_2860) @[lsu_bus_buffer.scala 416:112] + node _T_2862 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:82] + node _T_2863 = and(_T_2862, buf_state_en[0]) @[lsu_bus_buffer.scala 416:93] + node _T_2864 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 417:21] + node _T_2865 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 417:47] + node _T_2866 = or(_T_2864, _T_2865) @[lsu_bus_buffer.scala 417:32] + node _T_2867 = eq(_T_2866, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:6] + node _T_2868 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:23] + node _T_2869 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:53] + node _T_2870 = and(_T_2868, _T_2869) @[lsu_bus_buffer.scala 418:41] + node _T_2871 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:82] + node _T_2872 = and(_T_2870, _T_2871) @[lsu_bus_buffer.scala 418:71] + node _T_2873 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 418:101] + node _T_2874 = and(_T_2872, _T_2873) @[lsu_bus_buffer.scala 418:90] + node _T_2875 = or(_T_2867, _T_2874) @[lsu_bus_buffer.scala 417:59] + node _T_2876 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 419:17] + node _T_2877 = and(_T_2876, io.ldst_dual_r) @[lsu_bus_buffer.scala 419:35] + node _T_2878 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 419:63] + node _T_2879 = and(_T_2877, _T_2878) @[lsu_bus_buffer.scala 419:52] + node _T_2880 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 419:82] + node _T_2881 = and(_T_2879, _T_2880) @[lsu_bus_buffer.scala 419:71] + node _T_2882 = or(_T_2875, _T_2881) @[lsu_bus_buffer.scala 418:110] + node _T_2883 = and(_T_2863, _T_2882) @[lsu_bus_buffer.scala 416:112] + node _T_2884 = cat(_T_2883, _T_2861) @[Cat.scala 29:58] + node _T_2885 = cat(_T_2884, _T_2839) @[Cat.scala 29:58] + node _T_2886 = cat(_T_2885, _T_2817) @[Cat.scala 29:58] + node _T_2887 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:82] + node _T_2888 = and(_T_2887, buf_state_en[1]) @[lsu_bus_buffer.scala 416:93] + node _T_2889 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 417:21] + node _T_2890 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 417:47] + node _T_2891 = or(_T_2889, _T_2890) @[lsu_bus_buffer.scala 417:32] + node _T_2892 = eq(_T_2891, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:6] + node _T_2893 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:23] + node _T_2894 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:53] + node _T_2895 = and(_T_2893, _T_2894) @[lsu_bus_buffer.scala 418:41] + node _T_2896 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 418:82] + node _T_2897 = and(_T_2895, _T_2896) @[lsu_bus_buffer.scala 418:71] + node _T_2898 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:101] + node _T_2899 = and(_T_2897, _T_2898) @[lsu_bus_buffer.scala 418:90] + node _T_2900 = or(_T_2892, _T_2899) @[lsu_bus_buffer.scala 417:59] + node _T_2901 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 419:17] + node _T_2902 = and(_T_2901, io.ldst_dual_r) @[lsu_bus_buffer.scala 419:35] + node _T_2903 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 419:63] + node _T_2904 = and(_T_2902, _T_2903) @[lsu_bus_buffer.scala 419:52] + node _T_2905 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 419:82] + node _T_2906 = and(_T_2904, _T_2905) @[lsu_bus_buffer.scala 419:71] + node _T_2907 = or(_T_2900, _T_2906) @[lsu_bus_buffer.scala 418:110] + node _T_2908 = and(_T_2888, _T_2907) @[lsu_bus_buffer.scala 416:112] + node _T_2909 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:82] + node _T_2910 = and(_T_2909, buf_state_en[1]) @[lsu_bus_buffer.scala 416:93] + node _T_2911 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 417:21] + node _T_2912 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 417:47] + node _T_2913 = or(_T_2911, _T_2912) @[lsu_bus_buffer.scala 417:32] + node _T_2914 = eq(_T_2913, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:6] + node _T_2915 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:23] + node _T_2916 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:53] + node _T_2917 = and(_T_2915, _T_2916) @[lsu_bus_buffer.scala 418:41] + node _T_2918 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 418:82] + node _T_2919 = and(_T_2917, _T_2918) @[lsu_bus_buffer.scala 418:71] + node _T_2920 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 418:101] + node _T_2921 = and(_T_2919, _T_2920) @[lsu_bus_buffer.scala 418:90] + node _T_2922 = or(_T_2914, _T_2921) @[lsu_bus_buffer.scala 417:59] + node _T_2923 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 419:17] + node _T_2924 = and(_T_2923, io.ldst_dual_r) @[lsu_bus_buffer.scala 419:35] + node _T_2925 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 419:63] + node _T_2926 = and(_T_2924, _T_2925) @[lsu_bus_buffer.scala 419:52] + node _T_2927 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 419:82] + node _T_2928 = and(_T_2926, _T_2927) @[lsu_bus_buffer.scala 419:71] + node _T_2929 = or(_T_2922, _T_2928) @[lsu_bus_buffer.scala 418:110] + node _T_2930 = and(_T_2910, _T_2929) @[lsu_bus_buffer.scala 416:112] + node _T_2931 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:82] + node _T_2932 = and(_T_2931, buf_state_en[1]) @[lsu_bus_buffer.scala 416:93] + node _T_2933 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 417:21] + node _T_2934 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 417:47] + node _T_2935 = or(_T_2933, _T_2934) @[lsu_bus_buffer.scala 417:32] + node _T_2936 = eq(_T_2935, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:6] + node _T_2937 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:23] + node _T_2938 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:53] + node _T_2939 = and(_T_2937, _T_2938) @[lsu_bus_buffer.scala 418:41] + node _T_2940 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 418:82] + node _T_2941 = and(_T_2939, _T_2940) @[lsu_bus_buffer.scala 418:71] + node _T_2942 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 418:101] + node _T_2943 = and(_T_2941, _T_2942) @[lsu_bus_buffer.scala 418:90] + node _T_2944 = or(_T_2936, _T_2943) @[lsu_bus_buffer.scala 417:59] + node _T_2945 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 419:17] + node _T_2946 = and(_T_2945, io.ldst_dual_r) @[lsu_bus_buffer.scala 419:35] + node _T_2947 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 419:63] + node _T_2948 = and(_T_2946, _T_2947) @[lsu_bus_buffer.scala 419:52] + node _T_2949 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 419:82] + node _T_2950 = and(_T_2948, _T_2949) @[lsu_bus_buffer.scala 419:71] + node _T_2951 = or(_T_2944, _T_2950) @[lsu_bus_buffer.scala 418:110] + node _T_2952 = and(_T_2932, _T_2951) @[lsu_bus_buffer.scala 416:112] + node _T_2953 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:82] + node _T_2954 = and(_T_2953, buf_state_en[1]) @[lsu_bus_buffer.scala 416:93] + node _T_2955 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 417:21] + node _T_2956 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 417:47] + node _T_2957 = or(_T_2955, _T_2956) @[lsu_bus_buffer.scala 417:32] + node _T_2958 = eq(_T_2957, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:6] + node _T_2959 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:23] + node _T_2960 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:53] + node _T_2961 = and(_T_2959, _T_2960) @[lsu_bus_buffer.scala 418:41] + node _T_2962 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 418:82] + node _T_2963 = and(_T_2961, _T_2962) @[lsu_bus_buffer.scala 418:71] + node _T_2964 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 418:101] + node _T_2965 = and(_T_2963, _T_2964) @[lsu_bus_buffer.scala 418:90] + node _T_2966 = or(_T_2958, _T_2965) @[lsu_bus_buffer.scala 417:59] + node _T_2967 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 419:17] + node _T_2968 = and(_T_2967, io.ldst_dual_r) @[lsu_bus_buffer.scala 419:35] + node _T_2969 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 419:63] + node _T_2970 = and(_T_2968, _T_2969) @[lsu_bus_buffer.scala 419:52] + node _T_2971 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 419:82] + node _T_2972 = and(_T_2970, _T_2971) @[lsu_bus_buffer.scala 419:71] + node _T_2973 = or(_T_2966, _T_2972) @[lsu_bus_buffer.scala 418:110] + node _T_2974 = and(_T_2954, _T_2973) @[lsu_bus_buffer.scala 416:112] + node _T_2975 = cat(_T_2974, _T_2952) @[Cat.scala 29:58] + node _T_2976 = cat(_T_2975, _T_2930) @[Cat.scala 29:58] + node _T_2977 = cat(_T_2976, _T_2908) @[Cat.scala 29:58] + node _T_2978 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:82] + node _T_2979 = and(_T_2978, buf_state_en[2]) @[lsu_bus_buffer.scala 416:93] + node _T_2980 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 417:21] + node _T_2981 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 417:47] + node _T_2982 = or(_T_2980, _T_2981) @[lsu_bus_buffer.scala 417:32] + node _T_2983 = eq(_T_2982, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:6] + node _T_2984 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:23] + node _T_2985 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:53] + node _T_2986 = and(_T_2984, _T_2985) @[lsu_bus_buffer.scala 418:41] + node _T_2987 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 418:82] + node _T_2988 = and(_T_2986, _T_2987) @[lsu_bus_buffer.scala 418:71] + node _T_2989 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:101] + node _T_2990 = and(_T_2988, _T_2989) @[lsu_bus_buffer.scala 418:90] + node _T_2991 = or(_T_2983, _T_2990) @[lsu_bus_buffer.scala 417:59] + node _T_2992 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 419:17] + node _T_2993 = and(_T_2992, io.ldst_dual_r) @[lsu_bus_buffer.scala 419:35] + node _T_2994 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 419:63] + node _T_2995 = and(_T_2993, _T_2994) @[lsu_bus_buffer.scala 419:52] + node _T_2996 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 419:82] + node _T_2997 = and(_T_2995, _T_2996) @[lsu_bus_buffer.scala 419:71] + node _T_2998 = or(_T_2991, _T_2997) @[lsu_bus_buffer.scala 418:110] + node _T_2999 = and(_T_2979, _T_2998) @[lsu_bus_buffer.scala 416:112] + node _T_3000 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:82] + node _T_3001 = and(_T_3000, buf_state_en[2]) @[lsu_bus_buffer.scala 416:93] + node _T_3002 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 417:21] + node _T_3003 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 417:47] + node _T_3004 = or(_T_3002, _T_3003) @[lsu_bus_buffer.scala 417:32] + node _T_3005 = eq(_T_3004, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:6] + node _T_3006 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:23] + node _T_3007 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:53] + node _T_3008 = and(_T_3006, _T_3007) @[lsu_bus_buffer.scala 418:41] + node _T_3009 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 418:82] + node _T_3010 = and(_T_3008, _T_3009) @[lsu_bus_buffer.scala 418:71] + node _T_3011 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 418:101] + node _T_3012 = and(_T_3010, _T_3011) @[lsu_bus_buffer.scala 418:90] + node _T_3013 = or(_T_3005, _T_3012) @[lsu_bus_buffer.scala 417:59] + node _T_3014 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 419:17] + node _T_3015 = and(_T_3014, io.ldst_dual_r) @[lsu_bus_buffer.scala 419:35] + node _T_3016 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 419:63] + node _T_3017 = and(_T_3015, _T_3016) @[lsu_bus_buffer.scala 419:52] + node _T_3018 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 419:82] + node _T_3019 = and(_T_3017, _T_3018) @[lsu_bus_buffer.scala 419:71] + node _T_3020 = or(_T_3013, _T_3019) @[lsu_bus_buffer.scala 418:110] + node _T_3021 = and(_T_3001, _T_3020) @[lsu_bus_buffer.scala 416:112] + node _T_3022 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:82] + node _T_3023 = and(_T_3022, buf_state_en[2]) @[lsu_bus_buffer.scala 416:93] + node _T_3024 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 417:21] + node _T_3025 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 417:47] + node _T_3026 = or(_T_3024, _T_3025) @[lsu_bus_buffer.scala 417:32] + node _T_3027 = eq(_T_3026, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:6] + node _T_3028 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:23] + node _T_3029 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:53] + node _T_3030 = and(_T_3028, _T_3029) @[lsu_bus_buffer.scala 418:41] + node _T_3031 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 418:82] + node _T_3032 = and(_T_3030, _T_3031) @[lsu_bus_buffer.scala 418:71] + node _T_3033 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 418:101] + node _T_3034 = and(_T_3032, _T_3033) @[lsu_bus_buffer.scala 418:90] + node _T_3035 = or(_T_3027, _T_3034) @[lsu_bus_buffer.scala 417:59] + node _T_3036 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 419:17] + node _T_3037 = and(_T_3036, io.ldst_dual_r) @[lsu_bus_buffer.scala 419:35] + node _T_3038 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 419:63] + node _T_3039 = and(_T_3037, _T_3038) @[lsu_bus_buffer.scala 419:52] + node _T_3040 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 419:82] + node _T_3041 = and(_T_3039, _T_3040) @[lsu_bus_buffer.scala 419:71] + node _T_3042 = or(_T_3035, _T_3041) @[lsu_bus_buffer.scala 418:110] + node _T_3043 = and(_T_3023, _T_3042) @[lsu_bus_buffer.scala 416:112] + node _T_3044 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:82] + node _T_3045 = and(_T_3044, buf_state_en[2]) @[lsu_bus_buffer.scala 416:93] + node _T_3046 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 417:21] + node _T_3047 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 417:47] + node _T_3048 = or(_T_3046, _T_3047) @[lsu_bus_buffer.scala 417:32] + node _T_3049 = eq(_T_3048, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:6] + node _T_3050 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:23] + node _T_3051 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:53] + node _T_3052 = and(_T_3050, _T_3051) @[lsu_bus_buffer.scala 418:41] + node _T_3053 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 418:82] + node _T_3054 = and(_T_3052, _T_3053) @[lsu_bus_buffer.scala 418:71] + node _T_3055 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 418:101] + node _T_3056 = and(_T_3054, _T_3055) @[lsu_bus_buffer.scala 418:90] + node _T_3057 = or(_T_3049, _T_3056) @[lsu_bus_buffer.scala 417:59] + node _T_3058 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 419:17] + node _T_3059 = and(_T_3058, io.ldst_dual_r) @[lsu_bus_buffer.scala 419:35] + node _T_3060 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 419:63] + node _T_3061 = and(_T_3059, _T_3060) @[lsu_bus_buffer.scala 419:52] + node _T_3062 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 419:82] + node _T_3063 = and(_T_3061, _T_3062) @[lsu_bus_buffer.scala 419:71] + node _T_3064 = or(_T_3057, _T_3063) @[lsu_bus_buffer.scala 418:110] + node _T_3065 = and(_T_3045, _T_3064) @[lsu_bus_buffer.scala 416:112] + node _T_3066 = cat(_T_3065, _T_3043) @[Cat.scala 29:58] + node _T_3067 = cat(_T_3066, _T_3021) @[Cat.scala 29:58] + node _T_3068 = cat(_T_3067, _T_2999) @[Cat.scala 29:58] + node _T_3069 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:82] + node _T_3070 = and(_T_3069, buf_state_en[3]) @[lsu_bus_buffer.scala 416:93] + node _T_3071 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 417:21] + node _T_3072 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 417:47] + node _T_3073 = or(_T_3071, _T_3072) @[lsu_bus_buffer.scala 417:32] + node _T_3074 = eq(_T_3073, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:6] + node _T_3075 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:23] + node _T_3076 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:53] + node _T_3077 = and(_T_3075, _T_3076) @[lsu_bus_buffer.scala 418:41] + node _T_3078 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 418:82] + node _T_3079 = and(_T_3077, _T_3078) @[lsu_bus_buffer.scala 418:71] + node _T_3080 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:101] + node _T_3081 = and(_T_3079, _T_3080) @[lsu_bus_buffer.scala 418:90] + node _T_3082 = or(_T_3074, _T_3081) @[lsu_bus_buffer.scala 417:59] + node _T_3083 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 419:17] + node _T_3084 = and(_T_3083, io.ldst_dual_r) @[lsu_bus_buffer.scala 419:35] + node _T_3085 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 419:63] + node _T_3086 = and(_T_3084, _T_3085) @[lsu_bus_buffer.scala 419:52] + node _T_3087 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 419:82] + node _T_3088 = and(_T_3086, _T_3087) @[lsu_bus_buffer.scala 419:71] + node _T_3089 = or(_T_3082, _T_3088) @[lsu_bus_buffer.scala 418:110] + node _T_3090 = and(_T_3070, _T_3089) @[lsu_bus_buffer.scala 416:112] + node _T_3091 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:82] + node _T_3092 = and(_T_3091, buf_state_en[3]) @[lsu_bus_buffer.scala 416:93] + node _T_3093 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 417:21] + node _T_3094 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 417:47] + node _T_3095 = or(_T_3093, _T_3094) @[lsu_bus_buffer.scala 417:32] + node _T_3096 = eq(_T_3095, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:6] + node _T_3097 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:23] + node _T_3098 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:53] + node _T_3099 = and(_T_3097, _T_3098) @[lsu_bus_buffer.scala 418:41] + node _T_3100 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 418:82] + node _T_3101 = and(_T_3099, _T_3100) @[lsu_bus_buffer.scala 418:71] + node _T_3102 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 418:101] + node _T_3103 = and(_T_3101, _T_3102) @[lsu_bus_buffer.scala 418:90] + node _T_3104 = or(_T_3096, _T_3103) @[lsu_bus_buffer.scala 417:59] + node _T_3105 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 419:17] + node _T_3106 = and(_T_3105, io.ldst_dual_r) @[lsu_bus_buffer.scala 419:35] + node _T_3107 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 419:63] + node _T_3108 = and(_T_3106, _T_3107) @[lsu_bus_buffer.scala 419:52] + node _T_3109 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 419:82] + node _T_3110 = and(_T_3108, _T_3109) @[lsu_bus_buffer.scala 419:71] + node _T_3111 = or(_T_3104, _T_3110) @[lsu_bus_buffer.scala 418:110] + node _T_3112 = and(_T_3092, _T_3111) @[lsu_bus_buffer.scala 416:112] + node _T_3113 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:82] + node _T_3114 = and(_T_3113, buf_state_en[3]) @[lsu_bus_buffer.scala 416:93] + node _T_3115 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 417:21] + node _T_3116 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 417:47] + node _T_3117 = or(_T_3115, _T_3116) @[lsu_bus_buffer.scala 417:32] + node _T_3118 = eq(_T_3117, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:6] + node _T_3119 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:23] + node _T_3120 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:53] + node _T_3121 = and(_T_3119, _T_3120) @[lsu_bus_buffer.scala 418:41] + node _T_3122 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 418:82] + node _T_3123 = and(_T_3121, _T_3122) @[lsu_bus_buffer.scala 418:71] + node _T_3124 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 418:101] + node _T_3125 = and(_T_3123, _T_3124) @[lsu_bus_buffer.scala 418:90] + node _T_3126 = or(_T_3118, _T_3125) @[lsu_bus_buffer.scala 417:59] + node _T_3127 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 419:17] + node _T_3128 = and(_T_3127, io.ldst_dual_r) @[lsu_bus_buffer.scala 419:35] + node _T_3129 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 419:63] + node _T_3130 = and(_T_3128, _T_3129) @[lsu_bus_buffer.scala 419:52] + node _T_3131 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 419:82] + node _T_3132 = and(_T_3130, _T_3131) @[lsu_bus_buffer.scala 419:71] + node _T_3133 = or(_T_3126, _T_3132) @[lsu_bus_buffer.scala 418:110] + node _T_3134 = and(_T_3114, _T_3133) @[lsu_bus_buffer.scala 416:112] + node _T_3135 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:82] + node _T_3136 = and(_T_3135, buf_state_en[3]) @[lsu_bus_buffer.scala 416:93] + node _T_3137 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 417:21] + node _T_3138 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 417:47] + node _T_3139 = or(_T_3137, _T_3138) @[lsu_bus_buffer.scala 417:32] + node _T_3140 = eq(_T_3139, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:6] + node _T_3141 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:23] + node _T_3142 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:53] + node _T_3143 = and(_T_3141, _T_3142) @[lsu_bus_buffer.scala 418:41] + node _T_3144 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 418:82] + node _T_3145 = and(_T_3143, _T_3144) @[lsu_bus_buffer.scala 418:71] + node _T_3146 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 418:101] + node _T_3147 = and(_T_3145, _T_3146) @[lsu_bus_buffer.scala 418:90] + node _T_3148 = or(_T_3140, _T_3147) @[lsu_bus_buffer.scala 417:59] + node _T_3149 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 419:17] + node _T_3150 = and(_T_3149, io.ldst_dual_r) @[lsu_bus_buffer.scala 419:35] + node _T_3151 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 419:63] + node _T_3152 = and(_T_3150, _T_3151) @[lsu_bus_buffer.scala 419:52] + node _T_3153 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 419:82] + node _T_3154 = and(_T_3152, _T_3153) @[lsu_bus_buffer.scala 419:71] + node _T_3155 = or(_T_3148, _T_3154) @[lsu_bus_buffer.scala 418:110] + node _T_3156 = and(_T_3136, _T_3155) @[lsu_bus_buffer.scala 416:112] + node _T_3157 = cat(_T_3156, _T_3134) @[Cat.scala 29:58] + node _T_3158 = cat(_T_3157, _T_3112) @[Cat.scala 29:58] + node _T_3159 = cat(_T_3158, _T_3090) @[Cat.scala 29:58] + buf_rspage_set[0] <= _T_2886 @[lsu_bus_buffer.scala 416:18] + buf_rspage_set[1] <= _T_2977 @[lsu_bus_buffer.scala 416:18] + buf_rspage_set[2] <= _T_3068 @[lsu_bus_buffer.scala 416:18] + buf_rspage_set[3] <= _T_3159 @[lsu_bus_buffer.scala 416:18] + node _T_3160 = bits(buf_rspage_set[0], 0, 0) @[lsu_bus_buffer.scala 420:84] + node _T_3161 = bits(buf_rspage[0], 0, 0) @[lsu_bus_buffer.scala 420:103] + node _T_3162 = or(_T_3160, _T_3161) @[lsu_bus_buffer.scala 420:88] + node _T_3163 = bits(buf_rspage_set[0], 1, 1) @[lsu_bus_buffer.scala 420:84] + node _T_3164 = bits(buf_rspage[0], 1, 1) @[lsu_bus_buffer.scala 420:103] + node _T_3165 = or(_T_3163, _T_3164) @[lsu_bus_buffer.scala 420:88] + node _T_3166 = bits(buf_rspage_set[0], 2, 2) @[lsu_bus_buffer.scala 420:84] + node _T_3167 = bits(buf_rspage[0], 2, 2) @[lsu_bus_buffer.scala 420:103] + node _T_3168 = or(_T_3166, _T_3167) @[lsu_bus_buffer.scala 420:88] + node _T_3169 = bits(buf_rspage_set[0], 3, 3) @[lsu_bus_buffer.scala 420:84] + node _T_3170 = bits(buf_rspage[0], 3, 3) @[lsu_bus_buffer.scala 420:103] + node _T_3171 = or(_T_3169, _T_3170) @[lsu_bus_buffer.scala 420:88] + node _T_3172 = cat(_T_3171, _T_3168) @[Cat.scala 29:58] + node _T_3173 = cat(_T_3172, _T_3165) @[Cat.scala 29:58] + node _T_3174 = cat(_T_3173, _T_3162) @[Cat.scala 29:58] + node _T_3175 = bits(buf_rspage_set[1], 0, 0) @[lsu_bus_buffer.scala 420:84] + node _T_3176 = bits(buf_rspage[1], 0, 0) @[lsu_bus_buffer.scala 420:103] + node _T_3177 = or(_T_3175, _T_3176) @[lsu_bus_buffer.scala 420:88] + node _T_3178 = bits(buf_rspage_set[1], 1, 1) @[lsu_bus_buffer.scala 420:84] + node _T_3179 = bits(buf_rspage[1], 1, 1) @[lsu_bus_buffer.scala 420:103] + node _T_3180 = or(_T_3178, _T_3179) @[lsu_bus_buffer.scala 420:88] + node _T_3181 = bits(buf_rspage_set[1], 2, 2) @[lsu_bus_buffer.scala 420:84] + node _T_3182 = bits(buf_rspage[1], 2, 2) @[lsu_bus_buffer.scala 420:103] + node _T_3183 = or(_T_3181, _T_3182) @[lsu_bus_buffer.scala 420:88] + node _T_3184 = bits(buf_rspage_set[1], 3, 3) @[lsu_bus_buffer.scala 420:84] + node _T_3185 = bits(buf_rspage[1], 3, 3) @[lsu_bus_buffer.scala 420:103] + node _T_3186 = or(_T_3184, _T_3185) @[lsu_bus_buffer.scala 420:88] + node _T_3187 = cat(_T_3186, _T_3183) @[Cat.scala 29:58] + node _T_3188 = cat(_T_3187, _T_3180) @[Cat.scala 29:58] + node _T_3189 = cat(_T_3188, _T_3177) @[Cat.scala 29:58] + node _T_3190 = bits(buf_rspage_set[2], 0, 0) @[lsu_bus_buffer.scala 420:84] + node _T_3191 = bits(buf_rspage[2], 0, 0) @[lsu_bus_buffer.scala 420:103] + node _T_3192 = or(_T_3190, _T_3191) @[lsu_bus_buffer.scala 420:88] + node _T_3193 = bits(buf_rspage_set[2], 1, 1) @[lsu_bus_buffer.scala 420:84] + node _T_3194 = bits(buf_rspage[2], 1, 1) @[lsu_bus_buffer.scala 420:103] + node _T_3195 = or(_T_3193, _T_3194) @[lsu_bus_buffer.scala 420:88] + node _T_3196 = bits(buf_rspage_set[2], 2, 2) @[lsu_bus_buffer.scala 420:84] + node _T_3197 = bits(buf_rspage[2], 2, 2) @[lsu_bus_buffer.scala 420:103] + node _T_3198 = or(_T_3196, _T_3197) @[lsu_bus_buffer.scala 420:88] + node _T_3199 = bits(buf_rspage_set[2], 3, 3) @[lsu_bus_buffer.scala 420:84] + node _T_3200 = bits(buf_rspage[2], 3, 3) @[lsu_bus_buffer.scala 420:103] + node _T_3201 = or(_T_3199, _T_3200) @[lsu_bus_buffer.scala 420:88] + node _T_3202 = cat(_T_3201, _T_3198) @[Cat.scala 29:58] + node _T_3203 = cat(_T_3202, _T_3195) @[Cat.scala 29:58] + node _T_3204 = cat(_T_3203, _T_3192) @[Cat.scala 29:58] + node _T_3205 = bits(buf_rspage_set[3], 0, 0) @[lsu_bus_buffer.scala 420:84] + node _T_3206 = bits(buf_rspage[3], 0, 0) @[lsu_bus_buffer.scala 420:103] + node _T_3207 = or(_T_3205, _T_3206) @[lsu_bus_buffer.scala 420:88] + node _T_3208 = bits(buf_rspage_set[3], 1, 1) @[lsu_bus_buffer.scala 420:84] + node _T_3209 = bits(buf_rspage[3], 1, 1) @[lsu_bus_buffer.scala 420:103] + node _T_3210 = or(_T_3208, _T_3209) @[lsu_bus_buffer.scala 420:88] + node _T_3211 = bits(buf_rspage_set[3], 2, 2) @[lsu_bus_buffer.scala 420:84] + node _T_3212 = bits(buf_rspage[3], 2, 2) @[lsu_bus_buffer.scala 420:103] + node _T_3213 = or(_T_3211, _T_3212) @[lsu_bus_buffer.scala 420:88] + node _T_3214 = bits(buf_rspage_set[3], 3, 3) @[lsu_bus_buffer.scala 420:84] + node _T_3215 = bits(buf_rspage[3], 3, 3) @[lsu_bus_buffer.scala 420:103] + node _T_3216 = or(_T_3214, _T_3215) @[lsu_bus_buffer.scala 420:88] + node _T_3217 = cat(_T_3216, _T_3213) @[Cat.scala 29:58] + node _T_3218 = cat(_T_3217, _T_3210) @[Cat.scala 29:58] + node _T_3219 = cat(_T_3218, _T_3207) @[Cat.scala 29:58] + buf_rspage_in[0] <= _T_3174 @[lsu_bus_buffer.scala 420:17] + buf_rspage_in[1] <= _T_3189 @[lsu_bus_buffer.scala 420:17] + buf_rspage_in[2] <= _T_3204 @[lsu_bus_buffer.scala 420:17] + buf_rspage_in[3] <= _T_3219 @[lsu_bus_buffer.scala 420:17] + node _T_3220 = bits(buf_rspageQ[0], 0, 0) @[lsu_bus_buffer.scala 421:78] + node _T_3221 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 421:99] + node _T_3222 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:125] + node _T_3223 = or(_T_3221, _T_3222) @[lsu_bus_buffer.scala 421:110] + node _T_3224 = eq(_T_3223, UInt<1>("h00")) @[lsu_bus_buffer.scala 421:84] + node _T_3225 = and(_T_3220, _T_3224) @[lsu_bus_buffer.scala 421:82] + node _T_3226 = bits(buf_rspageQ[0], 1, 1) @[lsu_bus_buffer.scala 421:78] + node _T_3227 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 421:99] + node _T_3228 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:125] + node _T_3229 = or(_T_3227, _T_3228) @[lsu_bus_buffer.scala 421:110] + node _T_3230 = eq(_T_3229, UInt<1>("h00")) @[lsu_bus_buffer.scala 421:84] + node _T_3231 = and(_T_3226, _T_3230) @[lsu_bus_buffer.scala 421:82] + node _T_3232 = bits(buf_rspageQ[0], 2, 2) @[lsu_bus_buffer.scala 421:78] + node _T_3233 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 421:99] + node _T_3234 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:125] + node _T_3235 = or(_T_3233, _T_3234) @[lsu_bus_buffer.scala 421:110] + node _T_3236 = eq(_T_3235, UInt<1>("h00")) @[lsu_bus_buffer.scala 421:84] + node _T_3237 = and(_T_3232, _T_3236) @[lsu_bus_buffer.scala 421:82] + node _T_3238 = bits(buf_rspageQ[0], 3, 3) @[lsu_bus_buffer.scala 421:78] + node _T_3239 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 421:99] + node _T_3240 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:125] + node _T_3241 = or(_T_3239, _T_3240) @[lsu_bus_buffer.scala 421:110] + node _T_3242 = eq(_T_3241, UInt<1>("h00")) @[lsu_bus_buffer.scala 421:84] + node _T_3243 = and(_T_3238, _T_3242) @[lsu_bus_buffer.scala 421:82] + node _T_3244 = cat(_T_3243, _T_3237) @[Cat.scala 29:58] + node _T_3245 = cat(_T_3244, _T_3231) @[Cat.scala 29:58] + node _T_3246 = cat(_T_3245, _T_3225) @[Cat.scala 29:58] + node _T_3247 = bits(buf_rspageQ[1], 0, 0) @[lsu_bus_buffer.scala 421:78] + node _T_3248 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 421:99] + node _T_3249 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:125] + node _T_3250 = or(_T_3248, _T_3249) @[lsu_bus_buffer.scala 421:110] + node _T_3251 = eq(_T_3250, UInt<1>("h00")) @[lsu_bus_buffer.scala 421:84] + node _T_3252 = and(_T_3247, _T_3251) @[lsu_bus_buffer.scala 421:82] + node _T_3253 = bits(buf_rspageQ[1], 1, 1) @[lsu_bus_buffer.scala 421:78] + node _T_3254 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 421:99] + node _T_3255 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:125] + node _T_3256 = or(_T_3254, _T_3255) @[lsu_bus_buffer.scala 421:110] + node _T_3257 = eq(_T_3256, UInt<1>("h00")) @[lsu_bus_buffer.scala 421:84] + node _T_3258 = and(_T_3253, _T_3257) @[lsu_bus_buffer.scala 421:82] + node _T_3259 = bits(buf_rspageQ[1], 2, 2) @[lsu_bus_buffer.scala 421:78] + node _T_3260 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 421:99] + node _T_3261 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:125] + node _T_3262 = or(_T_3260, _T_3261) @[lsu_bus_buffer.scala 421:110] + node _T_3263 = eq(_T_3262, UInt<1>("h00")) @[lsu_bus_buffer.scala 421:84] + node _T_3264 = and(_T_3259, _T_3263) @[lsu_bus_buffer.scala 421:82] + node _T_3265 = bits(buf_rspageQ[1], 3, 3) @[lsu_bus_buffer.scala 421:78] + node _T_3266 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 421:99] + node _T_3267 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:125] + node _T_3268 = or(_T_3266, _T_3267) @[lsu_bus_buffer.scala 421:110] + node _T_3269 = eq(_T_3268, UInt<1>("h00")) @[lsu_bus_buffer.scala 421:84] + node _T_3270 = and(_T_3265, _T_3269) @[lsu_bus_buffer.scala 421:82] + node _T_3271 = cat(_T_3270, _T_3264) @[Cat.scala 29:58] + node _T_3272 = cat(_T_3271, _T_3258) @[Cat.scala 29:58] + node _T_3273 = cat(_T_3272, _T_3252) @[Cat.scala 29:58] + node _T_3274 = bits(buf_rspageQ[2], 0, 0) @[lsu_bus_buffer.scala 421:78] + node _T_3275 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 421:99] + node _T_3276 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:125] + node _T_3277 = or(_T_3275, _T_3276) @[lsu_bus_buffer.scala 421:110] + node _T_3278 = eq(_T_3277, UInt<1>("h00")) @[lsu_bus_buffer.scala 421:84] + node _T_3279 = and(_T_3274, _T_3278) @[lsu_bus_buffer.scala 421:82] + node _T_3280 = bits(buf_rspageQ[2], 1, 1) @[lsu_bus_buffer.scala 421:78] + node _T_3281 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 421:99] + node _T_3282 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:125] + node _T_3283 = or(_T_3281, _T_3282) @[lsu_bus_buffer.scala 421:110] + node _T_3284 = eq(_T_3283, UInt<1>("h00")) @[lsu_bus_buffer.scala 421:84] + node _T_3285 = and(_T_3280, _T_3284) @[lsu_bus_buffer.scala 421:82] + node _T_3286 = bits(buf_rspageQ[2], 2, 2) @[lsu_bus_buffer.scala 421:78] + node _T_3287 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 421:99] + node _T_3288 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:125] + node _T_3289 = or(_T_3287, _T_3288) @[lsu_bus_buffer.scala 421:110] + node _T_3290 = eq(_T_3289, UInt<1>("h00")) @[lsu_bus_buffer.scala 421:84] + node _T_3291 = and(_T_3286, _T_3290) @[lsu_bus_buffer.scala 421:82] + node _T_3292 = bits(buf_rspageQ[2], 3, 3) @[lsu_bus_buffer.scala 421:78] + node _T_3293 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 421:99] + node _T_3294 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:125] + node _T_3295 = or(_T_3293, _T_3294) @[lsu_bus_buffer.scala 421:110] + node _T_3296 = eq(_T_3295, UInt<1>("h00")) @[lsu_bus_buffer.scala 421:84] + node _T_3297 = and(_T_3292, _T_3296) @[lsu_bus_buffer.scala 421:82] + node _T_3298 = cat(_T_3297, _T_3291) @[Cat.scala 29:58] + node _T_3299 = cat(_T_3298, _T_3285) @[Cat.scala 29:58] + node _T_3300 = cat(_T_3299, _T_3279) @[Cat.scala 29:58] + node _T_3301 = bits(buf_rspageQ[3], 0, 0) @[lsu_bus_buffer.scala 421:78] + node _T_3302 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 421:99] + node _T_3303 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:125] + node _T_3304 = or(_T_3302, _T_3303) @[lsu_bus_buffer.scala 421:110] + node _T_3305 = eq(_T_3304, UInt<1>("h00")) @[lsu_bus_buffer.scala 421:84] + node _T_3306 = and(_T_3301, _T_3305) @[lsu_bus_buffer.scala 421:82] + node _T_3307 = bits(buf_rspageQ[3], 1, 1) @[lsu_bus_buffer.scala 421:78] + node _T_3308 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 421:99] + node _T_3309 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:125] + node _T_3310 = or(_T_3308, _T_3309) @[lsu_bus_buffer.scala 421:110] + node _T_3311 = eq(_T_3310, UInt<1>("h00")) @[lsu_bus_buffer.scala 421:84] + node _T_3312 = and(_T_3307, _T_3311) @[lsu_bus_buffer.scala 421:82] + node _T_3313 = bits(buf_rspageQ[3], 2, 2) @[lsu_bus_buffer.scala 421:78] + node _T_3314 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 421:99] + node _T_3315 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:125] + node _T_3316 = or(_T_3314, _T_3315) @[lsu_bus_buffer.scala 421:110] + node _T_3317 = eq(_T_3316, UInt<1>("h00")) @[lsu_bus_buffer.scala 421:84] + node _T_3318 = and(_T_3313, _T_3317) @[lsu_bus_buffer.scala 421:82] + node _T_3319 = bits(buf_rspageQ[3], 3, 3) @[lsu_bus_buffer.scala 421:78] + node _T_3320 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 421:99] + node _T_3321 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:125] + node _T_3322 = or(_T_3320, _T_3321) @[lsu_bus_buffer.scala 421:110] + node _T_3323 = eq(_T_3322, UInt<1>("h00")) @[lsu_bus_buffer.scala 421:84] + node _T_3324 = and(_T_3319, _T_3323) @[lsu_bus_buffer.scala 421:82] + node _T_3325 = cat(_T_3324, _T_3318) @[Cat.scala 29:58] + node _T_3326 = cat(_T_3325, _T_3312) @[Cat.scala 29:58] + node _T_3327 = cat(_T_3326, _T_3306) @[Cat.scala 29:58] + buf_rspage[0] <= _T_3246 @[lsu_bus_buffer.scala 421:14] + buf_rspage[1] <= _T_3273 @[lsu_bus_buffer.scala 421:14] + buf_rspage[2] <= _T_3300 @[lsu_bus_buffer.scala 421:14] + buf_rspage[3] <= _T_3327 @[lsu_bus_buffer.scala 421:14] + node _T_3328 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:75] + node _T_3329 = and(ibuf_drain_vld, _T_3328) @[lsu_bus_buffer.scala 426:63] + node _T_3330 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 426:75] + node _T_3331 = and(ibuf_drain_vld, _T_3330) @[lsu_bus_buffer.scala 426:63] + node _T_3332 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 426:75] + node _T_3333 = and(ibuf_drain_vld, _T_3332) @[lsu_bus_buffer.scala 426:63] + node _T_3334 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 426:75] + node _T_3335 = and(ibuf_drain_vld, _T_3334) @[lsu_bus_buffer.scala 426:63] + node _T_3336 = cat(_T_3335, _T_3333) @[Cat.scala 29:58] + node _T_3337 = cat(_T_3336, _T_3331) @[Cat.scala 29:58] + node _T_3338 = cat(_T_3337, _T_3329) @[Cat.scala 29:58] + ibuf_drainvec_vld <= _T_3338 @[lsu_bus_buffer.scala 426:21] + node _T_3339 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 427:64] + node _T_3340 = bits(ibuf_byteen_out, 3, 0) @[lsu_bus_buffer.scala 427:84] + node _T_3341 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 428:18] + node _T_3342 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 428:46] + node _T_3343 = and(_T_3341, _T_3342) @[lsu_bus_buffer.scala 428:35] + node _T_3344 = bits(ldst_byteen_hi_r, 3, 0) @[lsu_bus_buffer.scala 428:71] + node _T_3345 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 428:94] + node _T_3346 = mux(_T_3343, _T_3344, _T_3345) @[lsu_bus_buffer.scala 428:8] + node _T_3347 = mux(_T_3339, _T_3340, _T_3346) @[lsu_bus_buffer.scala 427:46] + node _T_3348 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 427:64] + node _T_3349 = bits(ibuf_byteen_out, 3, 0) @[lsu_bus_buffer.scala 427:84] + node _T_3350 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 428:18] + node _T_3351 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 428:46] + node _T_3352 = and(_T_3350, _T_3351) @[lsu_bus_buffer.scala 428:35] + node _T_3353 = bits(ldst_byteen_hi_r, 3, 0) @[lsu_bus_buffer.scala 428:71] + node _T_3354 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 428:94] + node _T_3355 = mux(_T_3352, _T_3353, _T_3354) @[lsu_bus_buffer.scala 428:8] + node _T_3356 = mux(_T_3348, _T_3349, _T_3355) @[lsu_bus_buffer.scala 427:46] + node _T_3357 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 427:64] + node _T_3358 = bits(ibuf_byteen_out, 3, 0) @[lsu_bus_buffer.scala 427:84] + node _T_3359 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 428:18] + node _T_3360 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 428:46] + node _T_3361 = and(_T_3359, _T_3360) @[lsu_bus_buffer.scala 428:35] + node _T_3362 = bits(ldst_byteen_hi_r, 3, 0) @[lsu_bus_buffer.scala 428:71] + node _T_3363 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 428:94] + node _T_3364 = mux(_T_3361, _T_3362, _T_3363) @[lsu_bus_buffer.scala 428:8] + node _T_3365 = mux(_T_3357, _T_3358, _T_3364) @[lsu_bus_buffer.scala 427:46] + node _T_3366 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 427:64] + node _T_3367 = bits(ibuf_byteen_out, 3, 0) @[lsu_bus_buffer.scala 427:84] + node _T_3368 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 428:18] + node _T_3369 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 428:46] + node _T_3370 = and(_T_3368, _T_3369) @[lsu_bus_buffer.scala 428:35] + node _T_3371 = bits(ldst_byteen_hi_r, 3, 0) @[lsu_bus_buffer.scala 428:71] + node _T_3372 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 428:94] + node _T_3373 = mux(_T_3370, _T_3371, _T_3372) @[lsu_bus_buffer.scala 428:8] + node _T_3374 = mux(_T_3366, _T_3367, _T_3373) @[lsu_bus_buffer.scala 427:46] + buf_byteen_in[0] <= _T_3347 @[lsu_bus_buffer.scala 427:17] + buf_byteen_in[1] <= _T_3356 @[lsu_bus_buffer.scala 427:17] + buf_byteen_in[2] <= _T_3365 @[lsu_bus_buffer.scala 427:17] + buf_byteen_in[3] <= _T_3374 @[lsu_bus_buffer.scala 427:17] + node _T_3375 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 429:62] + node _T_3376 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 429:91] + node _T_3377 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 429:119] + node _T_3378 = and(_T_3376, _T_3377) @[lsu_bus_buffer.scala 429:108] + node _T_3379 = mux(_T_3378, io.end_addr_r, io.lsu_addr_r) @[lsu_bus_buffer.scala 429:81] + node _T_3380 = mux(_T_3375, ibuf_addr, _T_3379) @[lsu_bus_buffer.scala 429:44] + node _T_3381 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 429:62] + node _T_3382 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 429:91] + node _T_3383 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 429:119] + node _T_3384 = and(_T_3382, _T_3383) @[lsu_bus_buffer.scala 429:108] + node _T_3385 = mux(_T_3384, io.end_addr_r, io.lsu_addr_r) @[lsu_bus_buffer.scala 429:81] + node _T_3386 = mux(_T_3381, ibuf_addr, _T_3385) @[lsu_bus_buffer.scala 429:44] + node _T_3387 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 429:62] + node _T_3388 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 429:91] + node _T_3389 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 429:119] + node _T_3390 = and(_T_3388, _T_3389) @[lsu_bus_buffer.scala 429:108] + node _T_3391 = mux(_T_3390, io.end_addr_r, io.lsu_addr_r) @[lsu_bus_buffer.scala 429:81] + node _T_3392 = mux(_T_3387, ibuf_addr, _T_3391) @[lsu_bus_buffer.scala 429:44] + node _T_3393 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 429:62] + node _T_3394 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 429:91] + node _T_3395 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 429:119] + node _T_3396 = and(_T_3394, _T_3395) @[lsu_bus_buffer.scala 429:108] + node _T_3397 = mux(_T_3396, io.end_addr_r, io.lsu_addr_r) @[lsu_bus_buffer.scala 429:81] + node _T_3398 = mux(_T_3393, ibuf_addr, _T_3397) @[lsu_bus_buffer.scala 429:44] + buf_addr_in[0] <= _T_3380 @[lsu_bus_buffer.scala 429:15] + buf_addr_in[1] <= _T_3386 @[lsu_bus_buffer.scala 429:15] + buf_addr_in[2] <= _T_3392 @[lsu_bus_buffer.scala 429:15] + buf_addr_in[3] <= _T_3398 @[lsu_bus_buffer.scala 429:15] + node _T_3399 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 430:63] + node _T_3400 = mux(_T_3399, ibuf_dual, io.ldst_dual_r) @[lsu_bus_buffer.scala 430:45] + node _T_3401 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 430:63] + node _T_3402 = mux(_T_3401, ibuf_dual, io.ldst_dual_r) @[lsu_bus_buffer.scala 430:45] + node _T_3403 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 430:63] + node _T_3404 = mux(_T_3403, ibuf_dual, io.ldst_dual_r) @[lsu_bus_buffer.scala 430:45] + node _T_3405 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 430:63] + node _T_3406 = mux(_T_3405, ibuf_dual, io.ldst_dual_r) @[lsu_bus_buffer.scala 430:45] + node _T_3407 = cat(_T_3406, _T_3404) @[Cat.scala 29:58] + node _T_3408 = cat(_T_3407, _T_3402) @[Cat.scala 29:58] + node _T_3409 = cat(_T_3408, _T_3400) @[Cat.scala 29:58] + buf_dual_in <= _T_3409 @[lsu_bus_buffer.scala 430:15] + node _T_3410 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 431:65] + node _T_3411 = mux(_T_3410, ibuf_samedw, ldst_samedw_r) @[lsu_bus_buffer.scala 431:47] + node _T_3412 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 431:65] + node _T_3413 = mux(_T_3412, ibuf_samedw, ldst_samedw_r) @[lsu_bus_buffer.scala 431:47] + node _T_3414 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 431:65] + node _T_3415 = mux(_T_3414, ibuf_samedw, ldst_samedw_r) @[lsu_bus_buffer.scala 431:47] + node _T_3416 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 431:65] + node _T_3417 = mux(_T_3416, ibuf_samedw, ldst_samedw_r) @[lsu_bus_buffer.scala 431:47] + node _T_3418 = cat(_T_3417, _T_3415) @[Cat.scala 29:58] + node _T_3419 = cat(_T_3418, _T_3413) @[Cat.scala 29:58] + node _T_3420 = cat(_T_3419, _T_3411) @[Cat.scala 29:58] + buf_samedw_in <= _T_3420 @[lsu_bus_buffer.scala 431:17] + node _T_3421 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 432:66] + node _T_3422 = or(ibuf_nomerge, ibuf_force_drain) @[lsu_bus_buffer.scala 432:84] + node _T_3423 = mux(_T_3421, _T_3422, io.no_dword_merge_r) @[lsu_bus_buffer.scala 432:48] + node _T_3424 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 432:66] + node _T_3425 = or(ibuf_nomerge, ibuf_force_drain) @[lsu_bus_buffer.scala 432:84] + node _T_3426 = mux(_T_3424, _T_3425, io.no_dword_merge_r) @[lsu_bus_buffer.scala 432:48] + node _T_3427 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 432:66] + node _T_3428 = or(ibuf_nomerge, ibuf_force_drain) @[lsu_bus_buffer.scala 432:84] + node _T_3429 = mux(_T_3427, _T_3428, io.no_dword_merge_r) @[lsu_bus_buffer.scala 432:48] + node _T_3430 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 432:66] + node _T_3431 = or(ibuf_nomerge, ibuf_force_drain) @[lsu_bus_buffer.scala 432:84] + node _T_3432 = mux(_T_3430, _T_3431, io.no_dword_merge_r) @[lsu_bus_buffer.scala 432:48] + node _T_3433 = cat(_T_3432, _T_3429) @[Cat.scala 29:58] + node _T_3434 = cat(_T_3433, _T_3426) @[Cat.scala 29:58] + node _T_3435 = cat(_T_3434, _T_3423) @[Cat.scala 29:58] + buf_nomerge_in <= _T_3435 @[lsu_bus_buffer.scala 432:18] + node _T_3436 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 433:65] + node _T_3437 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 433:90] + node _T_3438 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 433:118] + node _T_3439 = and(_T_3437, _T_3438) @[lsu_bus_buffer.scala 433:107] + node _T_3440 = mux(_T_3436, ibuf_dual, _T_3439) @[lsu_bus_buffer.scala 433:47] + node _T_3441 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 433:65] + node _T_3442 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 433:90] + node _T_3443 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 433:118] + node _T_3444 = and(_T_3442, _T_3443) @[lsu_bus_buffer.scala 433:107] + node _T_3445 = mux(_T_3441, ibuf_dual, _T_3444) @[lsu_bus_buffer.scala 433:47] + node _T_3446 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 433:65] + node _T_3447 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 433:90] + node _T_3448 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 433:118] + node _T_3449 = and(_T_3447, _T_3448) @[lsu_bus_buffer.scala 433:107] + node _T_3450 = mux(_T_3446, ibuf_dual, _T_3449) @[lsu_bus_buffer.scala 433:47] + node _T_3451 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 433:65] + node _T_3452 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 433:90] + node _T_3453 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 433:118] + node _T_3454 = and(_T_3452, _T_3453) @[lsu_bus_buffer.scala 433:107] + node _T_3455 = mux(_T_3451, ibuf_dual, _T_3454) @[lsu_bus_buffer.scala 433:47] + node _T_3456 = cat(_T_3455, _T_3450) @[Cat.scala 29:58] + node _T_3457 = cat(_T_3456, _T_3445) @[Cat.scala 29:58] + node _T_3458 = cat(_T_3457, _T_3440) @[Cat.scala 29:58] + buf_dualhi_in <= _T_3458 @[lsu_bus_buffer.scala 433:17] + node _T_3459 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 434:65] + node _T_3460 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 434:97] + node _T_3461 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 434:125] + node _T_3462 = and(_T_3460, _T_3461) @[lsu_bus_buffer.scala 434:114] + node _T_3463 = mux(_T_3462, WrPtr0_r, WrPtr1_r) @[lsu_bus_buffer.scala 434:87] + node _T_3464 = mux(_T_3459, ibuf_dualtag, _T_3463) @[lsu_bus_buffer.scala 434:47] + node _T_3465 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 434:65] + node _T_3466 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 434:97] + node _T_3467 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 434:125] + node _T_3468 = and(_T_3466, _T_3467) @[lsu_bus_buffer.scala 434:114] + node _T_3469 = mux(_T_3468, WrPtr0_r, WrPtr1_r) @[lsu_bus_buffer.scala 434:87] + node _T_3470 = mux(_T_3465, ibuf_dualtag, _T_3469) @[lsu_bus_buffer.scala 434:47] + node _T_3471 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 434:65] + node _T_3472 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 434:97] + node _T_3473 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 434:125] + node _T_3474 = and(_T_3472, _T_3473) @[lsu_bus_buffer.scala 434:114] + node _T_3475 = mux(_T_3474, WrPtr0_r, WrPtr1_r) @[lsu_bus_buffer.scala 434:87] + node _T_3476 = mux(_T_3471, ibuf_dualtag, _T_3475) @[lsu_bus_buffer.scala 434:47] + node _T_3477 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 434:65] + node _T_3478 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 434:97] + node _T_3479 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 434:125] + node _T_3480 = and(_T_3478, _T_3479) @[lsu_bus_buffer.scala 434:114] + node _T_3481 = mux(_T_3480, WrPtr0_r, WrPtr1_r) @[lsu_bus_buffer.scala 434:87] + node _T_3482 = mux(_T_3477, ibuf_dualtag, _T_3481) @[lsu_bus_buffer.scala 434:47] + buf_dualtag_in[0] <= _T_3464 @[lsu_bus_buffer.scala 434:18] + buf_dualtag_in[1] <= _T_3470 @[lsu_bus_buffer.scala 434:18] + buf_dualtag_in[2] <= _T_3476 @[lsu_bus_buffer.scala 434:18] + buf_dualtag_in[3] <= _T_3482 @[lsu_bus_buffer.scala 434:18] + node _T_3483 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 435:69] + node _T_3484 = mux(_T_3483, ibuf_sideeffect, io.is_sideeffects_r) @[lsu_bus_buffer.scala 435:51] + node _T_3485 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 435:69] + node _T_3486 = mux(_T_3485, ibuf_sideeffect, io.is_sideeffects_r) @[lsu_bus_buffer.scala 435:51] + node _T_3487 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 435:69] + node _T_3488 = mux(_T_3487, ibuf_sideeffect, io.is_sideeffects_r) @[lsu_bus_buffer.scala 435:51] + node _T_3489 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 435:69] + node _T_3490 = mux(_T_3489, ibuf_sideeffect, io.is_sideeffects_r) @[lsu_bus_buffer.scala 435:51] + node _T_3491 = cat(_T_3490, _T_3488) @[Cat.scala 29:58] + node _T_3492 = cat(_T_3491, _T_3486) @[Cat.scala 29:58] + node _T_3493 = cat(_T_3492, _T_3484) @[Cat.scala 29:58] + buf_sideeffect_in <= _T_3493 @[lsu_bus_buffer.scala 435:21] + node _T_3494 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 436:65] + node _T_3495 = mux(_T_3494, ibuf_unsign, io.lsu_pkt_r.bits.unsign) @[lsu_bus_buffer.scala 436:47] + node _T_3496 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 436:65] + node _T_3497 = mux(_T_3496, ibuf_unsign, io.lsu_pkt_r.bits.unsign) @[lsu_bus_buffer.scala 436:47] + node _T_3498 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 436:65] + node _T_3499 = mux(_T_3498, ibuf_unsign, io.lsu_pkt_r.bits.unsign) @[lsu_bus_buffer.scala 436:47] + node _T_3500 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 436:65] + node _T_3501 = mux(_T_3500, ibuf_unsign, io.lsu_pkt_r.bits.unsign) @[lsu_bus_buffer.scala 436:47] + node _T_3502 = cat(_T_3501, _T_3499) @[Cat.scala 29:58] + node _T_3503 = cat(_T_3502, _T_3497) @[Cat.scala 29:58] + node _T_3504 = cat(_T_3503, _T_3495) @[Cat.scala 29:58] + buf_unsign_in <= _T_3504 @[lsu_bus_buffer.scala 436:17] + node _T_3505 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 437:60] + node _T_3506 = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58] + node _T_3507 = mux(_T_3505, ibuf_sz, _T_3506) @[lsu_bus_buffer.scala 437:42] + node _T_3508 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 437:60] + node _T_3509 = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58] + node _T_3510 = mux(_T_3508, ibuf_sz, _T_3509) @[lsu_bus_buffer.scala 437:42] + node _T_3511 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 437:60] + node _T_3512 = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58] + node _T_3513 = mux(_T_3511, ibuf_sz, _T_3512) @[lsu_bus_buffer.scala 437:42] + node _T_3514 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 437:60] + node _T_3515 = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58] + node _T_3516 = mux(_T_3514, ibuf_sz, _T_3515) @[lsu_bus_buffer.scala 437:42] + buf_sz_in[0] <= _T_3507 @[lsu_bus_buffer.scala 437:13] + buf_sz_in[1] <= _T_3510 @[lsu_bus_buffer.scala 437:13] + buf_sz_in[2] <= _T_3513 @[lsu_bus_buffer.scala 437:13] + buf_sz_in[3] <= _T_3516 @[lsu_bus_buffer.scala 437:13] + node _T_3517 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 438:64] + node _T_3518 = mux(_T_3517, ibuf_write, io.lsu_pkt_r.bits.store) @[lsu_bus_buffer.scala 438:46] + node _T_3519 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 438:64] + node _T_3520 = mux(_T_3519, ibuf_write, io.lsu_pkt_r.bits.store) @[lsu_bus_buffer.scala 438:46] + node _T_3521 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 438:64] + node _T_3522 = mux(_T_3521, ibuf_write, io.lsu_pkt_r.bits.store) @[lsu_bus_buffer.scala 438:46] + node _T_3523 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 438:64] + node _T_3524 = mux(_T_3523, ibuf_write, io.lsu_pkt_r.bits.store) @[lsu_bus_buffer.scala 438:46] + node _T_3525 = cat(_T_3524, _T_3522) @[Cat.scala 29:58] + node _T_3526 = cat(_T_3525, _T_3520) @[Cat.scala 29:58] + node _T_3527 = cat(_T_3526, _T_3518) @[Cat.scala 29:58] + buf_write_in <= _T_3527 @[lsu_bus_buffer.scala 438:16] + node _T_3528 = eq(UInt<3>("h00"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3528 : @[Conditional.scala 40:58] + node _T_3529 = bits(io.lsu_bus_clk_en, 0, 0) @[lsu_bus_buffer.scala 443:56] + node _T_3530 = mux(_T_3529, UInt<3>("h02"), UInt<3>("h01")) @[lsu_bus_buffer.scala 443:31] + buf_nxtstate[0] <= _T_3530 @[lsu_bus_buffer.scala 443:25] + node _T_3531 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 444:45] + node _T_3532 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 444:77] + node _T_3533 = eq(ibuf_merge_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 444:97] + node _T_3534 = and(_T_3532, _T_3533) @[lsu_bus_buffer.scala 444:95] + node _T_3535 = eq(UInt<1>("h00"), WrPtr0_r) @[lsu_bus_buffer.scala 444:117] + node _T_3536 = and(_T_3534, _T_3535) @[lsu_bus_buffer.scala 444:112] + node _T_3537 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 444:144] + node _T_3538 = eq(UInt<1>("h00"), WrPtr1_r) @[lsu_bus_buffer.scala 444:166] + node _T_3539 = and(_T_3537, _T_3538) @[lsu_bus_buffer.scala 444:161] + node _T_3540 = or(_T_3536, _T_3539) @[lsu_bus_buffer.scala 444:132] + node _T_3541 = and(_T_3531, _T_3540) @[lsu_bus_buffer.scala 444:63] + node _T_3542 = eq(UInt<1>("h00"), ibuf_tag) @[lsu_bus_buffer.scala 444:206] + node _T_3543 = and(ibuf_drain_vld, _T_3542) @[lsu_bus_buffer.scala 444:201] + node _T_3544 = or(_T_3541, _T_3543) @[lsu_bus_buffer.scala 444:183] + buf_state_en[0] <= _T_3544 @[lsu_bus_buffer.scala 444:25] + buf_wr_en[0] <= buf_state_en[0] @[lsu_bus_buffer.scala 445:22] + buf_data_en[0] <= buf_state_en[0] @[lsu_bus_buffer.scala 446:24] + node _T_3545 = eq(UInt<1>("h00"), ibuf_tag) @[lsu_bus_buffer.scala 447:52] + node _T_3546 = and(ibuf_drain_vld, _T_3545) @[lsu_bus_buffer.scala 447:47] + node _T_3547 = bits(_T_3546, 0, 0) @[lsu_bus_buffer.scala 447:73] + node _T_3548 = bits(ibuf_data_out, 31, 0) @[lsu_bus_buffer.scala 447:90] + node _T_3549 = bits(store_data_lo_r, 31, 0) @[lsu_bus_buffer.scala 447:114] + node _T_3550 = mux(_T_3547, _T_3548, _T_3549) @[lsu_bus_buffer.scala 447:30] + buf_data_in[0] <= _T_3550 @[lsu_bus_buffer.scala 447:24] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_3551 = eq(UInt<3>("h01"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3551 : @[Conditional.scala 39:67] + node _T_3552 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 450:60] + node _T_3553 = mux(_T_3552, UInt<3>("h00"), UInt<3>("h02")) @[lsu_bus_buffer.scala 450:31] + buf_nxtstate[0] <= _T_3553 @[lsu_bus_buffer.scala 450:25] + node _T_3554 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 451:46] + buf_state_en[0] <= _T_3554 @[lsu_bus_buffer.scala 451:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3555 = eq(UInt<3>("h02"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3555 : @[Conditional.scala 39:67] + node _T_3556 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 454:60] + node _T_3557 = and(obuf_nosend, bus_rsp_read) @[lsu_bus_buffer.scala 454:89] + node _T_3558 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 454:124] + node _T_3559 = and(_T_3557, _T_3558) @[lsu_bus_buffer.scala 454:104] + node _T_3560 = mux(_T_3559, UInt<3>("h05"), UInt<3>("h03")) @[lsu_bus_buffer.scala 454:75] + node _T_3561 = mux(_T_3556, UInt<3>("h00"), _T_3560) @[lsu_bus_buffer.scala 454:31] + buf_nxtstate[0] <= _T_3561 @[lsu_bus_buffer.scala 454:25] + node _T_3562 = eq(obuf_tag0, UInt<3>("h00")) @[lsu_bus_buffer.scala 455:48] + node _T_3563 = eq(obuf_tag1, UInt<3>("h00")) @[lsu_bus_buffer.scala 455:104] + node _T_3564 = and(obuf_merge, _T_3563) @[lsu_bus_buffer.scala 455:91] + node _T_3565 = or(_T_3562, _T_3564) @[lsu_bus_buffer.scala 455:77] + node _T_3566 = and(_T_3565, obuf_valid) @[lsu_bus_buffer.scala 455:135] + node _T_3567 = and(_T_3566, obuf_wr_enQ) @[lsu_bus_buffer.scala 455:148] + buf_cmd_state_bus_en[0] <= _T_3567 @[lsu_bus_buffer.scala 455:33] + buf_state_bus_en[0] <= buf_cmd_state_bus_en[0] @[lsu_bus_buffer.scala 456:29] + node _T_3568 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 457:49] + node _T_3569 = or(_T_3568, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 457:70] + buf_state_en[0] <= _T_3569 @[lsu_bus_buffer.scala 457:25] + buf_ldfwd_in[0] <= UInt<1>("h01") @[lsu_bus_buffer.scala 458:25] + node _T_3570 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 459:56] + node _T_3571 = eq(_T_3570, UInt<1>("h00")) @[lsu_bus_buffer.scala 459:46] + node _T_3572 = and(buf_state_en[0], _T_3571) @[lsu_bus_buffer.scala 459:44] + node _T_3573 = and(_T_3572, obuf_nosend) @[lsu_bus_buffer.scala 459:60] + node _T_3574 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 459:76] + node _T_3575 = and(_T_3573, _T_3574) @[lsu_bus_buffer.scala 459:74] + buf_ldfwd_en[0] <= _T_3575 @[lsu_bus_buffer.scala 459:25] + node _T_3576 = bits(obuf_rdrsp_tag, 1, 0) @[lsu_bus_buffer.scala 460:46] + buf_ldfwdtag_in[0] <= _T_3576 @[lsu_bus_buffer.scala 460:28] + node _T_3577 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 461:47] + node _T_3578 = and(_T_3577, obuf_nosend) @[lsu_bus_buffer.scala 461:67] + node _T_3579 = and(_T_3578, bus_rsp_read) @[lsu_bus_buffer.scala 461:81] + buf_data_en[0] <= _T_3579 @[lsu_bus_buffer.scala 461:24] + node _T_3580 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 462:48] + node _T_3581 = and(_T_3580, obuf_nosend) @[lsu_bus_buffer.scala 462:68] + node _T_3582 = and(_T_3581, bus_rsp_read_error) @[lsu_bus_buffer.scala 462:82] + buf_error_en[0] <= _T_3582 @[lsu_bus_buffer.scala 462:25] + node _T_3583 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 463:61] + node _T_3584 = bits(buf_addr[0], 2, 2) @[lsu_bus_buffer.scala 463:85] + node _T_3585 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 463:103] + node _T_3586 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 463:126] + node _T_3587 = mux(_T_3584, _T_3585, _T_3586) @[lsu_bus_buffer.scala 463:73] + node _T_3588 = mux(buf_error_en[0], _T_3583, _T_3587) @[lsu_bus_buffer.scala 463:30] + buf_data_in[0] <= _T_3588 @[lsu_bus_buffer.scala 463:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3589 = eq(UInt<3>("h03"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3589 : @[Conditional.scala 39:67] + node _T_3590 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 466:67] + node _T_3591 = and(UInt<1>("h01"), bus_rsp_write_error) @[lsu_bus_buffer.scala 466:94] + node _T_3592 = eq(_T_3591, UInt<1>("h00")) @[lsu_bus_buffer.scala 466:73] + node _T_3593 = and(_T_3590, _T_3592) @[lsu_bus_buffer.scala 466:71] + node _T_3594 = or(io.dec_tlu_force_halt, _T_3593) @[lsu_bus_buffer.scala 466:55] + node _T_3595 = bits(_T_3594, 0, 0) @[lsu_bus_buffer.scala 466:125] + node _T_3596 = eq(buf_samedw[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 467:30] + node _T_3597 = and(buf_dual[0], _T_3596) @[lsu_bus_buffer.scala 467:28] + node _T_3598 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 467:57] + node _T_3599 = eq(_T_3598, UInt<1>("h00")) @[lsu_bus_buffer.scala 467:47] + node _T_3600 = and(_T_3597, _T_3599) @[lsu_bus_buffer.scala 467:45] + node _T_3601 = neq(buf_state[buf_dualtag[0]], UInt<3>("h04")) @[lsu_bus_buffer.scala 467:90] + node _T_3602 = and(_T_3600, _T_3601) @[lsu_bus_buffer.scala 467:61] + node _T_3603 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 468:27] + node _T_3604 = or(_T_3603, any_done_wait_state) @[lsu_bus_buffer.scala 468:31] + node _T_3605 = eq(buf_samedw[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 468:70] + node _T_3606 = and(buf_dual[0], _T_3605) @[lsu_bus_buffer.scala 468:68] + node _T_3607 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 468:97] + node _T_3608 = eq(_T_3607, UInt<1>("h00")) @[lsu_bus_buffer.scala 468:87] + node _T_3609 = and(_T_3606, _T_3608) @[lsu_bus_buffer.scala 468:85] + node _T_3610 = eq(buf_dualtag[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_3611 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_3612 = eq(buf_dualtag[0], UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_3613 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_3614 = eq(buf_dualtag[0], UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_3615 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_3616 = eq(buf_dualtag[0], UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_3617 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 57:129] + node _T_3618 = mux(_T_3610, _T_3611, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3619 = mux(_T_3612, _T_3613, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3620 = mux(_T_3614, _T_3615, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3621 = mux(_T_3616, _T_3617, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3622 = or(_T_3618, _T_3619) @[Mux.scala 27:72] + node _T_3623 = or(_T_3622, _T_3620) @[Mux.scala 27:72] + node _T_3624 = or(_T_3623, _T_3621) @[Mux.scala 27:72] + wire _T_3625 : UInt<1> @[Mux.scala 27:72] + _T_3625 <= _T_3624 @[Mux.scala 27:72] + node _T_3626 = and(_T_3609, _T_3625) @[lsu_bus_buffer.scala 468:101] + node _T_3627 = eq(buf_state[buf_dualtag[0]], UInt<3>("h04")) @[lsu_bus_buffer.scala 468:167] + node _T_3628 = and(_T_3626, _T_3627) @[lsu_bus_buffer.scala 468:138] + node _T_3629 = and(_T_3628, any_done_wait_state) @[lsu_bus_buffer.scala 468:187] + node _T_3630 = or(_T_3604, _T_3629) @[lsu_bus_buffer.scala 468:53] + node _T_3631 = mux(_T_3630, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 468:16] + node _T_3632 = mux(_T_3602, UInt<3>("h04"), _T_3631) @[lsu_bus_buffer.scala 467:14] + node _T_3633 = mux(_T_3595, UInt<3>("h00"), _T_3632) @[lsu_bus_buffer.scala 466:31] + buf_nxtstate[0] <= _T_3633 @[lsu_bus_buffer.scala 466:25] + node _T_3634 = eq(bus_rsp_write_tag, UInt<3>("h00")) @[lsu_bus_buffer.scala 469:73] + node _T_3635 = and(bus_rsp_write, _T_3634) @[lsu_bus_buffer.scala 469:52] + node _T_3636 = eq(bus_rsp_read_tag, UInt<3>("h00")) @[lsu_bus_buffer.scala 470:46] + node _T_3637 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 471:23] + node _T_3638 = eq(bus_rsp_read_tag, buf_ldfwdtag[0]) @[lsu_bus_buffer.scala 471:47] + node _T_3639 = and(_T_3637, _T_3638) @[lsu_bus_buffer.scala 471:27] + node _T_3640 = or(_T_3636, _T_3639) @[lsu_bus_buffer.scala 470:77] + node _T_3641 = and(buf_dual[0], buf_dualhi[0]) @[lsu_bus_buffer.scala 472:26] + node _T_3642 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 472:54] + node _T_3643 = not(_T_3642) @[lsu_bus_buffer.scala 472:44] + node _T_3644 = and(_T_3641, _T_3643) @[lsu_bus_buffer.scala 472:42] + node _T_3645 = and(_T_3644, buf_samedw[0]) @[lsu_bus_buffer.scala 472:58] + node _T_3646 = eq(bus_rsp_read_tag, buf_dualtag[0]) @[lsu_bus_buffer.scala 472:94] + node _T_3647 = and(_T_3645, _T_3646) @[lsu_bus_buffer.scala 472:74] + node _T_3648 = or(_T_3640, _T_3647) @[lsu_bus_buffer.scala 471:71] + node _T_3649 = and(bus_rsp_read, _T_3648) @[lsu_bus_buffer.scala 470:25] + node _T_3650 = or(_T_3635, _T_3649) @[lsu_bus_buffer.scala 469:105] + buf_resp_state_bus_en[0] <= _T_3650 @[lsu_bus_buffer.scala 469:34] + buf_state_bus_en[0] <= buf_resp_state_bus_en[0] @[lsu_bus_buffer.scala 473:29] + node _T_3651 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 474:49] + node _T_3652 = or(_T_3651, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 474:70] + buf_state_en[0] <= _T_3652 @[lsu_bus_buffer.scala 474:25] + node _T_3653 = and(buf_state_bus_en[0], bus_rsp_read) @[lsu_bus_buffer.scala 475:47] + node _T_3654 = and(_T_3653, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 475:62] + buf_data_en[0] <= _T_3654 @[lsu_bus_buffer.scala 475:24] + node _T_3655 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 476:48] + node _T_3656 = eq(bus_rsp_read_tag, UInt<3>("h00")) @[lsu_bus_buffer.scala 476:111] + node _T_3657 = and(bus_rsp_read_error, _T_3656) @[lsu_bus_buffer.scala 476:91] + node _T_3658 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 477:42] + node _T_3659 = and(bus_rsp_read_error, _T_3658) @[lsu_bus_buffer.scala 477:31] + node _T_3660 = eq(bus_rsp_read_tag, buf_ldfwdtag[0]) @[lsu_bus_buffer.scala 477:66] + node _T_3661 = and(_T_3659, _T_3660) @[lsu_bus_buffer.scala 477:46] + node _T_3662 = or(_T_3657, _T_3661) @[lsu_bus_buffer.scala 476:143] + node _T_3663 = and(bus_rsp_write_error, UInt<1>("h01")) @[lsu_bus_buffer.scala 478:32] + node _T_3664 = eq(bus_rsp_write_tag, UInt<3>("h00")) @[lsu_bus_buffer.scala 478:74] + node _T_3665 = and(_T_3663, _T_3664) @[lsu_bus_buffer.scala 478:53] + node _T_3666 = or(_T_3662, _T_3665) @[lsu_bus_buffer.scala 477:88] + node _T_3667 = and(_T_3655, _T_3666) @[lsu_bus_buffer.scala 476:68] + buf_error_en[0] <= _T_3667 @[lsu_bus_buffer.scala 476:25] + node _T_3668 = eq(buf_error_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 479:50] + node _T_3669 = and(buf_state_en[0], _T_3668) @[lsu_bus_buffer.scala 479:48] + node _T_3670 = bits(buf_addr[0], 2, 2) @[lsu_bus_buffer.scala 479:84] + node _T_3671 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 479:102] + node _T_3672 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 479:125] + node _T_3673 = mux(_T_3670, _T_3671, _T_3672) @[lsu_bus_buffer.scala 479:72] + node _T_3674 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 479:148] + node _T_3675 = mux(_T_3669, _T_3673, _T_3674) @[lsu_bus_buffer.scala 479:30] + buf_data_in[0] <= _T_3675 @[lsu_bus_buffer.scala 479:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3676 = eq(UInt<3>("h04"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3676 : @[Conditional.scala 39:67] + node _T_3677 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 482:60] + node _T_3678 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 482:86] + node _T_3679 = dshr(buf_ldfwd, buf_dualtag[0]) @[lsu_bus_buffer.scala 482:101] + node _T_3680 = bits(_T_3679, 0, 0) @[lsu_bus_buffer.scala 482:101] + node _T_3681 = or(_T_3678, _T_3680) @[lsu_bus_buffer.scala 482:90] + node _T_3682 = or(_T_3681, any_done_wait_state) @[lsu_bus_buffer.scala 482:118] + node _T_3683 = mux(_T_3682, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 482:75] + node _T_3684 = mux(_T_3677, UInt<3>("h00"), _T_3683) @[lsu_bus_buffer.scala 482:31] + buf_nxtstate[0] <= _T_3684 @[lsu_bus_buffer.scala 482:25] + node _T_3685 = eq(bus_rsp_read_tag, buf_dualtag[0]) @[lsu_bus_buffer.scala 483:66] + node _T_3686 = dshr(buf_ldfwd, buf_dualtag[0]) @[lsu_bus_buffer.scala 484:21] + node _T_3687 = bits(_T_3686, 0, 0) @[lsu_bus_buffer.scala 484:21] + node _T_3688 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[0]]) @[lsu_bus_buffer.scala 484:58] + node _T_3689 = and(_T_3687, _T_3688) @[lsu_bus_buffer.scala 484:38] + node _T_3690 = or(_T_3685, _T_3689) @[lsu_bus_buffer.scala 483:95] + node _T_3691 = and(bus_rsp_read, _T_3690) @[lsu_bus_buffer.scala 483:45] + buf_state_bus_en[0] <= _T_3691 @[lsu_bus_buffer.scala 483:29] + node _T_3692 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 485:49] + node _T_3693 = or(_T_3692, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 485:70] + buf_state_en[0] <= _T_3693 @[lsu_bus_buffer.scala 485:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3694 = eq(UInt<3>("h05"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3694 : @[Conditional.scala 39:67] + node _T_3695 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 488:60] + node _T_3696 = mux(_T_3695, UInt<3>("h00"), UInt<3>("h06")) @[lsu_bus_buffer.scala 488:31] + buf_nxtstate[0] <= _T_3696 @[lsu_bus_buffer.scala 488:25] + node _T_3697 = eq(RspPtr, UInt<2>("h00")) @[lsu_bus_buffer.scala 489:37] + node _T_3698 = eq(buf_dualtag[0], RspPtr) @[lsu_bus_buffer.scala 489:98] + node _T_3699 = and(buf_dual[0], _T_3698) @[lsu_bus_buffer.scala 489:80] + node _T_3700 = or(_T_3697, _T_3699) @[lsu_bus_buffer.scala 489:65] + node _T_3701 = or(_T_3700, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 489:112] + buf_state_en[0] <= _T_3701 @[lsu_bus_buffer.scala 489:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3702 = eq(UInt<3>("h06"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3702 : @[Conditional.scala 39:67] + buf_nxtstate[0] <= UInt<3>("h00") @[lsu_bus_buffer.scala 492:25] + buf_rst[0] <= UInt<1>("h01") @[lsu_bus_buffer.scala 493:20] + buf_state_en[0] <= UInt<1>("h01") @[lsu_bus_buffer.scala 494:25] + buf_ldfwd_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 495:25] + buf_ldfwd_en[0] <= buf_state_en[0] @[lsu_bus_buffer.scala 496:25] + skip @[Conditional.scala 39:67] + node _T_3703 = bits(buf_state_en[0], 0, 0) @[lsu_bus_buffer.scala 499:108] + reg _T_3704 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3703 : @[Reg.scala 28:19] + _T_3704 <= buf_nxtstate[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_state[0] <= _T_3704 @[lsu_bus_buffer.scala 499:18] + reg _T_3705 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 500:60] + _T_3705 <= buf_age_in_0 @[lsu_bus_buffer.scala 500:60] + buf_ageQ[0] <= _T_3705 @[lsu_bus_buffer.scala 500:17] + reg _T_3706 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 501:63] + _T_3706 <= buf_rspage_in[0] @[lsu_bus_buffer.scala 501:63] + buf_rspageQ[0] <= _T_3706 @[lsu_bus_buffer.scala 501:20] + node _T_3707 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 502:109] + reg _T_3708 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3707 : @[Reg.scala 28:19] + _T_3708 <= buf_dualtag_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualtag[0] <= _T_3708 @[lsu_bus_buffer.scala 502:20] + node _T_3709 = bits(buf_dual_in, 0, 0) @[lsu_bus_buffer.scala 503:74] + node _T_3710 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 503:107] + reg _T_3711 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3710 : @[Reg.scala 28:19] + _T_3711 <= _T_3709 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dual[0] <= _T_3711 @[lsu_bus_buffer.scala 503:17] + node _T_3712 = bits(buf_samedw_in, 0, 0) @[lsu_bus_buffer.scala 504:78] + node _T_3713 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 504:111] + reg _T_3714 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3713 : @[Reg.scala 28:19] + _T_3714 <= _T_3712 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_samedw[0] <= _T_3714 @[lsu_bus_buffer.scala 504:19] + node _T_3715 = bits(buf_nomerge_in, 0, 0) @[lsu_bus_buffer.scala 505:80] + node _T_3716 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 505:113] + reg _T_3717 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3716 : @[Reg.scala 28:19] + _T_3717 <= _T_3715 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_nomerge[0] <= _T_3717 @[lsu_bus_buffer.scala 505:20] + node _T_3718 = bits(buf_dualhi_in, 0, 0) @[lsu_bus_buffer.scala 506:78] + node _T_3719 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 506:111] + reg _T_3720 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3719 : @[Reg.scala 28:19] + _T_3720 <= _T_3718 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualhi[0] <= _T_3720 @[lsu_bus_buffer.scala 506:19] + node _T_3721 = eq(UInt<3>("h00"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3721 : @[Conditional.scala 40:58] + node _T_3722 = bits(io.lsu_bus_clk_en, 0, 0) @[lsu_bus_buffer.scala 443:56] + node _T_3723 = mux(_T_3722, UInt<3>("h02"), UInt<3>("h01")) @[lsu_bus_buffer.scala 443:31] + buf_nxtstate[1] <= _T_3723 @[lsu_bus_buffer.scala 443:25] + node _T_3724 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 444:45] + node _T_3725 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 444:77] + node _T_3726 = eq(ibuf_merge_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 444:97] + node _T_3727 = and(_T_3725, _T_3726) @[lsu_bus_buffer.scala 444:95] + node _T_3728 = eq(UInt<1>("h01"), WrPtr0_r) @[lsu_bus_buffer.scala 444:117] + node _T_3729 = and(_T_3727, _T_3728) @[lsu_bus_buffer.scala 444:112] + node _T_3730 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 444:144] + node _T_3731 = eq(UInt<1>("h01"), WrPtr1_r) @[lsu_bus_buffer.scala 444:166] + node _T_3732 = and(_T_3730, _T_3731) @[lsu_bus_buffer.scala 444:161] + node _T_3733 = or(_T_3729, _T_3732) @[lsu_bus_buffer.scala 444:132] + node _T_3734 = and(_T_3724, _T_3733) @[lsu_bus_buffer.scala 444:63] + node _T_3735 = eq(UInt<1>("h01"), ibuf_tag) @[lsu_bus_buffer.scala 444:206] + node _T_3736 = and(ibuf_drain_vld, _T_3735) @[lsu_bus_buffer.scala 444:201] + node _T_3737 = or(_T_3734, _T_3736) @[lsu_bus_buffer.scala 444:183] + buf_state_en[1] <= _T_3737 @[lsu_bus_buffer.scala 444:25] + buf_wr_en[1] <= buf_state_en[1] @[lsu_bus_buffer.scala 445:22] + buf_data_en[1] <= buf_state_en[1] @[lsu_bus_buffer.scala 446:24] + node _T_3738 = eq(UInt<1>("h01"), ibuf_tag) @[lsu_bus_buffer.scala 447:52] + node _T_3739 = and(ibuf_drain_vld, _T_3738) @[lsu_bus_buffer.scala 447:47] + node _T_3740 = bits(_T_3739, 0, 0) @[lsu_bus_buffer.scala 447:73] + node _T_3741 = bits(ibuf_data_out, 31, 0) @[lsu_bus_buffer.scala 447:90] + node _T_3742 = bits(store_data_lo_r, 31, 0) @[lsu_bus_buffer.scala 447:114] + node _T_3743 = mux(_T_3740, _T_3741, _T_3742) @[lsu_bus_buffer.scala 447:30] + buf_data_in[1] <= _T_3743 @[lsu_bus_buffer.scala 447:24] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_3744 = eq(UInt<3>("h01"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3744 : @[Conditional.scala 39:67] + node _T_3745 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 450:60] + node _T_3746 = mux(_T_3745, UInt<3>("h00"), UInt<3>("h02")) @[lsu_bus_buffer.scala 450:31] + buf_nxtstate[1] <= _T_3746 @[lsu_bus_buffer.scala 450:25] + node _T_3747 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 451:46] + buf_state_en[1] <= _T_3747 @[lsu_bus_buffer.scala 451:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3748 = eq(UInt<3>("h02"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3748 : @[Conditional.scala 39:67] + node _T_3749 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 454:60] + node _T_3750 = and(obuf_nosend, bus_rsp_read) @[lsu_bus_buffer.scala 454:89] + node _T_3751 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 454:124] + node _T_3752 = and(_T_3750, _T_3751) @[lsu_bus_buffer.scala 454:104] + node _T_3753 = mux(_T_3752, UInt<3>("h05"), UInt<3>("h03")) @[lsu_bus_buffer.scala 454:75] + node _T_3754 = mux(_T_3749, UInt<3>("h00"), _T_3753) @[lsu_bus_buffer.scala 454:31] + buf_nxtstate[1] <= _T_3754 @[lsu_bus_buffer.scala 454:25] + node _T_3755 = eq(obuf_tag0, UInt<3>("h01")) @[lsu_bus_buffer.scala 455:48] + node _T_3756 = eq(obuf_tag1, UInt<3>("h01")) @[lsu_bus_buffer.scala 455:104] + node _T_3757 = and(obuf_merge, _T_3756) @[lsu_bus_buffer.scala 455:91] + node _T_3758 = or(_T_3755, _T_3757) @[lsu_bus_buffer.scala 455:77] + node _T_3759 = and(_T_3758, obuf_valid) @[lsu_bus_buffer.scala 455:135] + node _T_3760 = and(_T_3759, obuf_wr_enQ) @[lsu_bus_buffer.scala 455:148] + buf_cmd_state_bus_en[1] <= _T_3760 @[lsu_bus_buffer.scala 455:33] + buf_state_bus_en[1] <= buf_cmd_state_bus_en[1] @[lsu_bus_buffer.scala 456:29] + node _T_3761 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 457:49] + node _T_3762 = or(_T_3761, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 457:70] + buf_state_en[1] <= _T_3762 @[lsu_bus_buffer.scala 457:25] + buf_ldfwd_in[1] <= UInt<1>("h01") @[lsu_bus_buffer.scala 458:25] + node _T_3763 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 459:56] + node _T_3764 = eq(_T_3763, UInt<1>("h00")) @[lsu_bus_buffer.scala 459:46] + node _T_3765 = and(buf_state_en[1], _T_3764) @[lsu_bus_buffer.scala 459:44] + node _T_3766 = and(_T_3765, obuf_nosend) @[lsu_bus_buffer.scala 459:60] + node _T_3767 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 459:76] + node _T_3768 = and(_T_3766, _T_3767) @[lsu_bus_buffer.scala 459:74] + buf_ldfwd_en[1] <= _T_3768 @[lsu_bus_buffer.scala 459:25] + node _T_3769 = bits(obuf_rdrsp_tag, 1, 0) @[lsu_bus_buffer.scala 460:46] + buf_ldfwdtag_in[1] <= _T_3769 @[lsu_bus_buffer.scala 460:28] + node _T_3770 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 461:47] + node _T_3771 = and(_T_3770, obuf_nosend) @[lsu_bus_buffer.scala 461:67] + node _T_3772 = and(_T_3771, bus_rsp_read) @[lsu_bus_buffer.scala 461:81] + buf_data_en[1] <= _T_3772 @[lsu_bus_buffer.scala 461:24] + node _T_3773 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 462:48] + node _T_3774 = and(_T_3773, obuf_nosend) @[lsu_bus_buffer.scala 462:68] + node _T_3775 = and(_T_3774, bus_rsp_read_error) @[lsu_bus_buffer.scala 462:82] + buf_error_en[1] <= _T_3775 @[lsu_bus_buffer.scala 462:25] + node _T_3776 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 463:61] + node _T_3777 = bits(buf_addr[1], 2, 2) @[lsu_bus_buffer.scala 463:85] + node _T_3778 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 463:103] + node _T_3779 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 463:126] + node _T_3780 = mux(_T_3777, _T_3778, _T_3779) @[lsu_bus_buffer.scala 463:73] + node _T_3781 = mux(buf_error_en[1], _T_3776, _T_3780) @[lsu_bus_buffer.scala 463:30] + buf_data_in[1] <= _T_3781 @[lsu_bus_buffer.scala 463:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3782 = eq(UInt<3>("h03"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3782 : @[Conditional.scala 39:67] + node _T_3783 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 466:67] + node _T_3784 = and(UInt<1>("h01"), bus_rsp_write_error) @[lsu_bus_buffer.scala 466:94] + node _T_3785 = eq(_T_3784, UInt<1>("h00")) @[lsu_bus_buffer.scala 466:73] + node _T_3786 = and(_T_3783, _T_3785) @[lsu_bus_buffer.scala 466:71] + node _T_3787 = or(io.dec_tlu_force_halt, _T_3786) @[lsu_bus_buffer.scala 466:55] + node _T_3788 = bits(_T_3787, 0, 0) @[lsu_bus_buffer.scala 466:125] + node _T_3789 = eq(buf_samedw[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 467:30] + node _T_3790 = and(buf_dual[1], _T_3789) @[lsu_bus_buffer.scala 467:28] + node _T_3791 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 467:57] + node _T_3792 = eq(_T_3791, UInt<1>("h00")) @[lsu_bus_buffer.scala 467:47] + node _T_3793 = and(_T_3790, _T_3792) @[lsu_bus_buffer.scala 467:45] + node _T_3794 = neq(buf_state[buf_dualtag[1]], UInt<3>("h04")) @[lsu_bus_buffer.scala 467:90] + node _T_3795 = and(_T_3793, _T_3794) @[lsu_bus_buffer.scala 467:61] + node _T_3796 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 468:27] + node _T_3797 = or(_T_3796, any_done_wait_state) @[lsu_bus_buffer.scala 468:31] + node _T_3798 = eq(buf_samedw[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 468:70] + node _T_3799 = and(buf_dual[1], _T_3798) @[lsu_bus_buffer.scala 468:68] + node _T_3800 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 468:97] + node _T_3801 = eq(_T_3800, UInt<1>("h00")) @[lsu_bus_buffer.scala 468:87] + node _T_3802 = and(_T_3799, _T_3801) @[lsu_bus_buffer.scala 468:85] + node _T_3803 = eq(buf_dualtag[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_3804 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_3805 = eq(buf_dualtag[1], UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_3806 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_3807 = eq(buf_dualtag[1], UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_3808 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_3809 = eq(buf_dualtag[1], UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_3810 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 57:129] + node _T_3811 = mux(_T_3803, _T_3804, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3812 = mux(_T_3805, _T_3806, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3813 = mux(_T_3807, _T_3808, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3814 = mux(_T_3809, _T_3810, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3815 = or(_T_3811, _T_3812) @[Mux.scala 27:72] + node _T_3816 = or(_T_3815, _T_3813) @[Mux.scala 27:72] + node _T_3817 = or(_T_3816, _T_3814) @[Mux.scala 27:72] + wire _T_3818 : UInt<1> @[Mux.scala 27:72] + _T_3818 <= _T_3817 @[Mux.scala 27:72] + node _T_3819 = and(_T_3802, _T_3818) @[lsu_bus_buffer.scala 468:101] + node _T_3820 = eq(buf_state[buf_dualtag[1]], UInt<3>("h04")) @[lsu_bus_buffer.scala 468:167] + node _T_3821 = and(_T_3819, _T_3820) @[lsu_bus_buffer.scala 468:138] + node _T_3822 = and(_T_3821, any_done_wait_state) @[lsu_bus_buffer.scala 468:187] + node _T_3823 = or(_T_3797, _T_3822) @[lsu_bus_buffer.scala 468:53] + node _T_3824 = mux(_T_3823, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 468:16] + node _T_3825 = mux(_T_3795, UInt<3>("h04"), _T_3824) @[lsu_bus_buffer.scala 467:14] + node _T_3826 = mux(_T_3788, UInt<3>("h00"), _T_3825) @[lsu_bus_buffer.scala 466:31] + buf_nxtstate[1] <= _T_3826 @[lsu_bus_buffer.scala 466:25] + node _T_3827 = eq(bus_rsp_write_tag, UInt<3>("h01")) @[lsu_bus_buffer.scala 469:73] + node _T_3828 = and(bus_rsp_write, _T_3827) @[lsu_bus_buffer.scala 469:52] + node _T_3829 = eq(bus_rsp_read_tag, UInt<3>("h01")) @[lsu_bus_buffer.scala 470:46] + node _T_3830 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 471:23] + node _T_3831 = eq(bus_rsp_read_tag, buf_ldfwdtag[1]) @[lsu_bus_buffer.scala 471:47] + node _T_3832 = and(_T_3830, _T_3831) @[lsu_bus_buffer.scala 471:27] + node _T_3833 = or(_T_3829, _T_3832) @[lsu_bus_buffer.scala 470:77] + node _T_3834 = and(buf_dual[1], buf_dualhi[1]) @[lsu_bus_buffer.scala 472:26] + node _T_3835 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 472:54] + node _T_3836 = not(_T_3835) @[lsu_bus_buffer.scala 472:44] + node _T_3837 = and(_T_3834, _T_3836) @[lsu_bus_buffer.scala 472:42] + node _T_3838 = and(_T_3837, buf_samedw[1]) @[lsu_bus_buffer.scala 472:58] + node _T_3839 = eq(bus_rsp_read_tag, buf_dualtag[1]) @[lsu_bus_buffer.scala 472:94] + node _T_3840 = and(_T_3838, _T_3839) @[lsu_bus_buffer.scala 472:74] + node _T_3841 = or(_T_3833, _T_3840) @[lsu_bus_buffer.scala 471:71] + node _T_3842 = and(bus_rsp_read, _T_3841) @[lsu_bus_buffer.scala 470:25] + node _T_3843 = or(_T_3828, _T_3842) @[lsu_bus_buffer.scala 469:105] + buf_resp_state_bus_en[1] <= _T_3843 @[lsu_bus_buffer.scala 469:34] + buf_state_bus_en[1] <= buf_resp_state_bus_en[1] @[lsu_bus_buffer.scala 473:29] + node _T_3844 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 474:49] + node _T_3845 = or(_T_3844, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 474:70] + buf_state_en[1] <= _T_3845 @[lsu_bus_buffer.scala 474:25] + node _T_3846 = and(buf_state_bus_en[1], bus_rsp_read) @[lsu_bus_buffer.scala 475:47] + node _T_3847 = and(_T_3846, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 475:62] + buf_data_en[1] <= _T_3847 @[lsu_bus_buffer.scala 475:24] + node _T_3848 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 476:48] + node _T_3849 = eq(bus_rsp_read_tag, UInt<3>("h01")) @[lsu_bus_buffer.scala 476:111] + node _T_3850 = and(bus_rsp_read_error, _T_3849) @[lsu_bus_buffer.scala 476:91] + node _T_3851 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 477:42] + node _T_3852 = and(bus_rsp_read_error, _T_3851) @[lsu_bus_buffer.scala 477:31] + node _T_3853 = eq(bus_rsp_read_tag, buf_ldfwdtag[1]) @[lsu_bus_buffer.scala 477:66] + node _T_3854 = and(_T_3852, _T_3853) @[lsu_bus_buffer.scala 477:46] + node _T_3855 = or(_T_3850, _T_3854) @[lsu_bus_buffer.scala 476:143] + node _T_3856 = and(bus_rsp_write_error, UInt<1>("h01")) @[lsu_bus_buffer.scala 478:32] + node _T_3857 = eq(bus_rsp_write_tag, UInt<3>("h01")) @[lsu_bus_buffer.scala 478:74] + node _T_3858 = and(_T_3856, _T_3857) @[lsu_bus_buffer.scala 478:53] + node _T_3859 = or(_T_3855, _T_3858) @[lsu_bus_buffer.scala 477:88] + node _T_3860 = and(_T_3848, _T_3859) @[lsu_bus_buffer.scala 476:68] + buf_error_en[1] <= _T_3860 @[lsu_bus_buffer.scala 476:25] + node _T_3861 = eq(buf_error_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 479:50] + node _T_3862 = and(buf_state_en[1], _T_3861) @[lsu_bus_buffer.scala 479:48] + node _T_3863 = bits(buf_addr[1], 2, 2) @[lsu_bus_buffer.scala 479:84] + node _T_3864 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 479:102] + node _T_3865 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 479:125] + node _T_3866 = mux(_T_3863, _T_3864, _T_3865) @[lsu_bus_buffer.scala 479:72] + node _T_3867 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 479:148] + node _T_3868 = mux(_T_3862, _T_3866, _T_3867) @[lsu_bus_buffer.scala 479:30] + buf_data_in[1] <= _T_3868 @[lsu_bus_buffer.scala 479:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3869 = eq(UInt<3>("h04"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3869 : @[Conditional.scala 39:67] + node _T_3870 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 482:60] + node _T_3871 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 482:86] + node _T_3872 = dshr(buf_ldfwd, buf_dualtag[1]) @[lsu_bus_buffer.scala 482:101] + node _T_3873 = bits(_T_3872, 0, 0) @[lsu_bus_buffer.scala 482:101] + node _T_3874 = or(_T_3871, _T_3873) @[lsu_bus_buffer.scala 482:90] + node _T_3875 = or(_T_3874, any_done_wait_state) @[lsu_bus_buffer.scala 482:118] + node _T_3876 = mux(_T_3875, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 482:75] + node _T_3877 = mux(_T_3870, UInt<3>("h00"), _T_3876) @[lsu_bus_buffer.scala 482:31] + buf_nxtstate[1] <= _T_3877 @[lsu_bus_buffer.scala 482:25] + node _T_3878 = eq(bus_rsp_read_tag, buf_dualtag[1]) @[lsu_bus_buffer.scala 483:66] + node _T_3879 = dshr(buf_ldfwd, buf_dualtag[1]) @[lsu_bus_buffer.scala 484:21] + node _T_3880 = bits(_T_3879, 0, 0) @[lsu_bus_buffer.scala 484:21] + node _T_3881 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[1]]) @[lsu_bus_buffer.scala 484:58] + node _T_3882 = and(_T_3880, _T_3881) @[lsu_bus_buffer.scala 484:38] + node _T_3883 = or(_T_3878, _T_3882) @[lsu_bus_buffer.scala 483:95] + node _T_3884 = and(bus_rsp_read, _T_3883) @[lsu_bus_buffer.scala 483:45] + buf_state_bus_en[1] <= _T_3884 @[lsu_bus_buffer.scala 483:29] + node _T_3885 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 485:49] + node _T_3886 = or(_T_3885, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 485:70] + buf_state_en[1] <= _T_3886 @[lsu_bus_buffer.scala 485:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3887 = eq(UInt<3>("h05"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3887 : @[Conditional.scala 39:67] + node _T_3888 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 488:60] + node _T_3889 = mux(_T_3888, UInt<3>("h00"), UInt<3>("h06")) @[lsu_bus_buffer.scala 488:31] + buf_nxtstate[1] <= _T_3889 @[lsu_bus_buffer.scala 488:25] + node _T_3890 = eq(RspPtr, UInt<2>("h01")) @[lsu_bus_buffer.scala 489:37] + node _T_3891 = eq(buf_dualtag[1], RspPtr) @[lsu_bus_buffer.scala 489:98] + node _T_3892 = and(buf_dual[1], _T_3891) @[lsu_bus_buffer.scala 489:80] + node _T_3893 = or(_T_3890, _T_3892) @[lsu_bus_buffer.scala 489:65] + node _T_3894 = or(_T_3893, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 489:112] + buf_state_en[1] <= _T_3894 @[lsu_bus_buffer.scala 489:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3895 = eq(UInt<3>("h06"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3895 : @[Conditional.scala 39:67] + buf_nxtstate[1] <= UInt<3>("h00") @[lsu_bus_buffer.scala 492:25] + buf_rst[1] <= UInt<1>("h01") @[lsu_bus_buffer.scala 493:20] + buf_state_en[1] <= UInt<1>("h01") @[lsu_bus_buffer.scala 494:25] + buf_ldfwd_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 495:25] + buf_ldfwd_en[1] <= buf_state_en[1] @[lsu_bus_buffer.scala 496:25] + skip @[Conditional.scala 39:67] + node _T_3896 = bits(buf_state_en[1], 0, 0) @[lsu_bus_buffer.scala 499:108] + reg _T_3897 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3896 : @[Reg.scala 28:19] + _T_3897 <= buf_nxtstate[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_state[1] <= _T_3897 @[lsu_bus_buffer.scala 499:18] + reg _T_3898 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 500:60] + _T_3898 <= buf_age_in_1 @[lsu_bus_buffer.scala 500:60] + buf_ageQ[1] <= _T_3898 @[lsu_bus_buffer.scala 500:17] + reg _T_3899 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 501:63] + _T_3899 <= buf_rspage_in[1] @[lsu_bus_buffer.scala 501:63] + buf_rspageQ[1] <= _T_3899 @[lsu_bus_buffer.scala 501:20] + node _T_3900 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 502:109] + reg _T_3901 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3900 : @[Reg.scala 28:19] + _T_3901 <= buf_dualtag_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualtag[1] <= _T_3901 @[lsu_bus_buffer.scala 502:20] + node _T_3902 = bits(buf_dual_in, 1, 1) @[lsu_bus_buffer.scala 503:74] + node _T_3903 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 503:107] + reg _T_3904 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3903 : @[Reg.scala 28:19] + _T_3904 <= _T_3902 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dual[1] <= _T_3904 @[lsu_bus_buffer.scala 503:17] + node _T_3905 = bits(buf_samedw_in, 1, 1) @[lsu_bus_buffer.scala 504:78] + node _T_3906 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 504:111] + reg _T_3907 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3906 : @[Reg.scala 28:19] + _T_3907 <= _T_3905 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_samedw[1] <= _T_3907 @[lsu_bus_buffer.scala 504:19] + node _T_3908 = bits(buf_nomerge_in, 1, 1) @[lsu_bus_buffer.scala 505:80] + node _T_3909 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 505:113] + reg _T_3910 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3909 : @[Reg.scala 28:19] + _T_3910 <= _T_3908 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_nomerge[1] <= _T_3910 @[lsu_bus_buffer.scala 505:20] + node _T_3911 = bits(buf_dualhi_in, 1, 1) @[lsu_bus_buffer.scala 506:78] + node _T_3912 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 506:111] + reg _T_3913 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3912 : @[Reg.scala 28:19] + _T_3913 <= _T_3911 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualhi[1] <= _T_3913 @[lsu_bus_buffer.scala 506:19] + node _T_3914 = eq(UInt<3>("h00"), buf_state[2]) @[Conditional.scala 37:30] + when _T_3914 : @[Conditional.scala 40:58] + node _T_3915 = bits(io.lsu_bus_clk_en, 0, 0) @[lsu_bus_buffer.scala 443:56] + node _T_3916 = mux(_T_3915, UInt<3>("h02"), UInt<3>("h01")) @[lsu_bus_buffer.scala 443:31] + buf_nxtstate[2] <= _T_3916 @[lsu_bus_buffer.scala 443:25] + node _T_3917 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 444:45] + node _T_3918 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 444:77] + node _T_3919 = eq(ibuf_merge_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 444:97] + node _T_3920 = and(_T_3918, _T_3919) @[lsu_bus_buffer.scala 444:95] + node _T_3921 = eq(UInt<2>("h02"), WrPtr0_r) @[lsu_bus_buffer.scala 444:117] + node _T_3922 = and(_T_3920, _T_3921) @[lsu_bus_buffer.scala 444:112] + node _T_3923 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 444:144] + node _T_3924 = eq(UInt<2>("h02"), WrPtr1_r) @[lsu_bus_buffer.scala 444:166] + node _T_3925 = and(_T_3923, _T_3924) @[lsu_bus_buffer.scala 444:161] + node _T_3926 = or(_T_3922, _T_3925) @[lsu_bus_buffer.scala 444:132] + node _T_3927 = and(_T_3917, _T_3926) @[lsu_bus_buffer.scala 444:63] + node _T_3928 = eq(UInt<2>("h02"), ibuf_tag) @[lsu_bus_buffer.scala 444:206] + node _T_3929 = and(ibuf_drain_vld, _T_3928) @[lsu_bus_buffer.scala 444:201] + node _T_3930 = or(_T_3927, _T_3929) @[lsu_bus_buffer.scala 444:183] + buf_state_en[2] <= _T_3930 @[lsu_bus_buffer.scala 444:25] + buf_wr_en[2] <= buf_state_en[2] @[lsu_bus_buffer.scala 445:22] + buf_data_en[2] <= buf_state_en[2] @[lsu_bus_buffer.scala 446:24] + node _T_3931 = eq(UInt<2>("h02"), ibuf_tag) @[lsu_bus_buffer.scala 447:52] + node _T_3932 = and(ibuf_drain_vld, _T_3931) @[lsu_bus_buffer.scala 447:47] + node _T_3933 = bits(_T_3932, 0, 0) @[lsu_bus_buffer.scala 447:73] + node _T_3934 = bits(ibuf_data_out, 31, 0) @[lsu_bus_buffer.scala 447:90] + node _T_3935 = bits(store_data_lo_r, 31, 0) @[lsu_bus_buffer.scala 447:114] + node _T_3936 = mux(_T_3933, _T_3934, _T_3935) @[lsu_bus_buffer.scala 447:30] + buf_data_in[2] <= _T_3936 @[lsu_bus_buffer.scala 447:24] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_3937 = eq(UInt<3>("h01"), buf_state[2]) @[Conditional.scala 37:30] + when _T_3937 : @[Conditional.scala 39:67] + node _T_3938 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 450:60] + node _T_3939 = mux(_T_3938, UInt<3>("h00"), UInt<3>("h02")) @[lsu_bus_buffer.scala 450:31] + buf_nxtstate[2] <= _T_3939 @[lsu_bus_buffer.scala 450:25] + node _T_3940 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 451:46] + buf_state_en[2] <= _T_3940 @[lsu_bus_buffer.scala 451:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3941 = eq(UInt<3>("h02"), buf_state[2]) @[Conditional.scala 37:30] + when _T_3941 : @[Conditional.scala 39:67] + node _T_3942 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 454:60] + node _T_3943 = and(obuf_nosend, bus_rsp_read) @[lsu_bus_buffer.scala 454:89] + node _T_3944 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 454:124] + node _T_3945 = and(_T_3943, _T_3944) @[lsu_bus_buffer.scala 454:104] + node _T_3946 = mux(_T_3945, UInt<3>("h05"), UInt<3>("h03")) @[lsu_bus_buffer.scala 454:75] + node _T_3947 = mux(_T_3942, UInt<3>("h00"), _T_3946) @[lsu_bus_buffer.scala 454:31] + buf_nxtstate[2] <= _T_3947 @[lsu_bus_buffer.scala 454:25] + node _T_3948 = eq(obuf_tag0, UInt<3>("h02")) @[lsu_bus_buffer.scala 455:48] + node _T_3949 = eq(obuf_tag1, UInt<3>("h02")) @[lsu_bus_buffer.scala 455:104] + node _T_3950 = and(obuf_merge, _T_3949) @[lsu_bus_buffer.scala 455:91] + node _T_3951 = or(_T_3948, _T_3950) @[lsu_bus_buffer.scala 455:77] + node _T_3952 = and(_T_3951, obuf_valid) @[lsu_bus_buffer.scala 455:135] + node _T_3953 = and(_T_3952, obuf_wr_enQ) @[lsu_bus_buffer.scala 455:148] + buf_cmd_state_bus_en[2] <= _T_3953 @[lsu_bus_buffer.scala 455:33] + buf_state_bus_en[2] <= buf_cmd_state_bus_en[2] @[lsu_bus_buffer.scala 456:29] + node _T_3954 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 457:49] + node _T_3955 = or(_T_3954, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 457:70] + buf_state_en[2] <= _T_3955 @[lsu_bus_buffer.scala 457:25] + buf_ldfwd_in[2] <= UInt<1>("h01") @[lsu_bus_buffer.scala 458:25] + node _T_3956 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 459:56] + node _T_3957 = eq(_T_3956, UInt<1>("h00")) @[lsu_bus_buffer.scala 459:46] + node _T_3958 = and(buf_state_en[2], _T_3957) @[lsu_bus_buffer.scala 459:44] + node _T_3959 = and(_T_3958, obuf_nosend) @[lsu_bus_buffer.scala 459:60] + node _T_3960 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 459:76] + node _T_3961 = and(_T_3959, _T_3960) @[lsu_bus_buffer.scala 459:74] + buf_ldfwd_en[2] <= _T_3961 @[lsu_bus_buffer.scala 459:25] + node _T_3962 = bits(obuf_rdrsp_tag, 1, 0) @[lsu_bus_buffer.scala 460:46] + buf_ldfwdtag_in[2] <= _T_3962 @[lsu_bus_buffer.scala 460:28] + node _T_3963 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 461:47] + node _T_3964 = and(_T_3963, obuf_nosend) @[lsu_bus_buffer.scala 461:67] + node _T_3965 = and(_T_3964, bus_rsp_read) @[lsu_bus_buffer.scala 461:81] + buf_data_en[2] <= _T_3965 @[lsu_bus_buffer.scala 461:24] + node _T_3966 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 462:48] + node _T_3967 = and(_T_3966, obuf_nosend) @[lsu_bus_buffer.scala 462:68] + node _T_3968 = and(_T_3967, bus_rsp_read_error) @[lsu_bus_buffer.scala 462:82] + buf_error_en[2] <= _T_3968 @[lsu_bus_buffer.scala 462:25] + node _T_3969 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 463:61] + node _T_3970 = bits(buf_addr[2], 2, 2) @[lsu_bus_buffer.scala 463:85] + node _T_3971 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 463:103] + node _T_3972 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 463:126] + node _T_3973 = mux(_T_3970, _T_3971, _T_3972) @[lsu_bus_buffer.scala 463:73] + node _T_3974 = mux(buf_error_en[2], _T_3969, _T_3973) @[lsu_bus_buffer.scala 463:30] + buf_data_in[2] <= _T_3974 @[lsu_bus_buffer.scala 463:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3975 = eq(UInt<3>("h03"), buf_state[2]) @[Conditional.scala 37:30] + when _T_3975 : @[Conditional.scala 39:67] + node _T_3976 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 466:67] + node _T_3977 = and(UInt<1>("h01"), bus_rsp_write_error) @[lsu_bus_buffer.scala 466:94] + node _T_3978 = eq(_T_3977, UInt<1>("h00")) @[lsu_bus_buffer.scala 466:73] + node _T_3979 = and(_T_3976, _T_3978) @[lsu_bus_buffer.scala 466:71] + node _T_3980 = or(io.dec_tlu_force_halt, _T_3979) @[lsu_bus_buffer.scala 466:55] + node _T_3981 = bits(_T_3980, 0, 0) @[lsu_bus_buffer.scala 466:125] + node _T_3982 = eq(buf_samedw[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 467:30] + node _T_3983 = and(buf_dual[2], _T_3982) @[lsu_bus_buffer.scala 467:28] + node _T_3984 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 467:57] + node _T_3985 = eq(_T_3984, UInt<1>("h00")) @[lsu_bus_buffer.scala 467:47] + node _T_3986 = and(_T_3983, _T_3985) @[lsu_bus_buffer.scala 467:45] + node _T_3987 = neq(buf_state[buf_dualtag[2]], UInt<3>("h04")) @[lsu_bus_buffer.scala 467:90] + node _T_3988 = and(_T_3986, _T_3987) @[lsu_bus_buffer.scala 467:61] + node _T_3989 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 468:27] + node _T_3990 = or(_T_3989, any_done_wait_state) @[lsu_bus_buffer.scala 468:31] + node _T_3991 = eq(buf_samedw[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 468:70] + node _T_3992 = and(buf_dual[2], _T_3991) @[lsu_bus_buffer.scala 468:68] + node _T_3993 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 468:97] + node _T_3994 = eq(_T_3993, UInt<1>("h00")) @[lsu_bus_buffer.scala 468:87] + node _T_3995 = and(_T_3992, _T_3994) @[lsu_bus_buffer.scala 468:85] + node _T_3996 = eq(buf_dualtag[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_3997 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_3998 = eq(buf_dualtag[2], UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_3999 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_4000 = eq(buf_dualtag[2], UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_4001 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_4002 = eq(buf_dualtag[2], UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_4003 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 57:129] + node _T_4004 = mux(_T_3996, _T_3997, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4005 = mux(_T_3998, _T_3999, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4006 = mux(_T_4000, _T_4001, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4007 = mux(_T_4002, _T_4003, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4008 = or(_T_4004, _T_4005) @[Mux.scala 27:72] + node _T_4009 = or(_T_4008, _T_4006) @[Mux.scala 27:72] + node _T_4010 = or(_T_4009, _T_4007) @[Mux.scala 27:72] + wire _T_4011 : UInt<1> @[Mux.scala 27:72] + _T_4011 <= _T_4010 @[Mux.scala 27:72] + node _T_4012 = and(_T_3995, _T_4011) @[lsu_bus_buffer.scala 468:101] + node _T_4013 = eq(buf_state[buf_dualtag[2]], UInt<3>("h04")) @[lsu_bus_buffer.scala 468:167] + node _T_4014 = and(_T_4012, _T_4013) @[lsu_bus_buffer.scala 468:138] + node _T_4015 = and(_T_4014, any_done_wait_state) @[lsu_bus_buffer.scala 468:187] + node _T_4016 = or(_T_3990, _T_4015) @[lsu_bus_buffer.scala 468:53] + node _T_4017 = mux(_T_4016, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 468:16] + node _T_4018 = mux(_T_3988, UInt<3>("h04"), _T_4017) @[lsu_bus_buffer.scala 467:14] + node _T_4019 = mux(_T_3981, UInt<3>("h00"), _T_4018) @[lsu_bus_buffer.scala 466:31] + buf_nxtstate[2] <= _T_4019 @[lsu_bus_buffer.scala 466:25] + node _T_4020 = eq(bus_rsp_write_tag, UInt<3>("h02")) @[lsu_bus_buffer.scala 469:73] + node _T_4021 = and(bus_rsp_write, _T_4020) @[lsu_bus_buffer.scala 469:52] + node _T_4022 = eq(bus_rsp_read_tag, UInt<3>("h02")) @[lsu_bus_buffer.scala 470:46] + node _T_4023 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 471:23] + node _T_4024 = eq(bus_rsp_read_tag, buf_ldfwdtag[2]) @[lsu_bus_buffer.scala 471:47] + node _T_4025 = and(_T_4023, _T_4024) @[lsu_bus_buffer.scala 471:27] + node _T_4026 = or(_T_4022, _T_4025) @[lsu_bus_buffer.scala 470:77] + node _T_4027 = and(buf_dual[2], buf_dualhi[2]) @[lsu_bus_buffer.scala 472:26] + node _T_4028 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 472:54] + node _T_4029 = not(_T_4028) @[lsu_bus_buffer.scala 472:44] + node _T_4030 = and(_T_4027, _T_4029) @[lsu_bus_buffer.scala 472:42] + node _T_4031 = and(_T_4030, buf_samedw[2]) @[lsu_bus_buffer.scala 472:58] + node _T_4032 = eq(bus_rsp_read_tag, buf_dualtag[2]) @[lsu_bus_buffer.scala 472:94] + node _T_4033 = and(_T_4031, _T_4032) @[lsu_bus_buffer.scala 472:74] + node _T_4034 = or(_T_4026, _T_4033) @[lsu_bus_buffer.scala 471:71] + node _T_4035 = and(bus_rsp_read, _T_4034) @[lsu_bus_buffer.scala 470:25] + node _T_4036 = or(_T_4021, _T_4035) @[lsu_bus_buffer.scala 469:105] + buf_resp_state_bus_en[2] <= _T_4036 @[lsu_bus_buffer.scala 469:34] + buf_state_bus_en[2] <= buf_resp_state_bus_en[2] @[lsu_bus_buffer.scala 473:29] + node _T_4037 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 474:49] + node _T_4038 = or(_T_4037, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 474:70] + buf_state_en[2] <= _T_4038 @[lsu_bus_buffer.scala 474:25] + node _T_4039 = and(buf_state_bus_en[2], bus_rsp_read) @[lsu_bus_buffer.scala 475:47] + node _T_4040 = and(_T_4039, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 475:62] + buf_data_en[2] <= _T_4040 @[lsu_bus_buffer.scala 475:24] + node _T_4041 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 476:48] + node _T_4042 = eq(bus_rsp_read_tag, UInt<3>("h02")) @[lsu_bus_buffer.scala 476:111] + node _T_4043 = and(bus_rsp_read_error, _T_4042) @[lsu_bus_buffer.scala 476:91] + node _T_4044 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 477:42] + node _T_4045 = and(bus_rsp_read_error, _T_4044) @[lsu_bus_buffer.scala 477:31] + node _T_4046 = eq(bus_rsp_read_tag, buf_ldfwdtag[2]) @[lsu_bus_buffer.scala 477:66] + node _T_4047 = and(_T_4045, _T_4046) @[lsu_bus_buffer.scala 477:46] + node _T_4048 = or(_T_4043, _T_4047) @[lsu_bus_buffer.scala 476:143] + node _T_4049 = and(bus_rsp_write_error, UInt<1>("h01")) @[lsu_bus_buffer.scala 478:32] + node _T_4050 = eq(bus_rsp_write_tag, UInt<3>("h02")) @[lsu_bus_buffer.scala 478:74] + node _T_4051 = and(_T_4049, _T_4050) @[lsu_bus_buffer.scala 478:53] + node _T_4052 = or(_T_4048, _T_4051) @[lsu_bus_buffer.scala 477:88] + node _T_4053 = and(_T_4041, _T_4052) @[lsu_bus_buffer.scala 476:68] + buf_error_en[2] <= _T_4053 @[lsu_bus_buffer.scala 476:25] + node _T_4054 = eq(buf_error_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 479:50] + node _T_4055 = and(buf_state_en[2], _T_4054) @[lsu_bus_buffer.scala 479:48] + node _T_4056 = bits(buf_addr[2], 2, 2) @[lsu_bus_buffer.scala 479:84] + node _T_4057 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 479:102] + node _T_4058 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 479:125] + node _T_4059 = mux(_T_4056, _T_4057, _T_4058) @[lsu_bus_buffer.scala 479:72] + node _T_4060 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 479:148] + node _T_4061 = mux(_T_4055, _T_4059, _T_4060) @[lsu_bus_buffer.scala 479:30] + buf_data_in[2] <= _T_4061 @[lsu_bus_buffer.scala 479:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4062 = eq(UInt<3>("h04"), buf_state[2]) @[Conditional.scala 37:30] + when _T_4062 : @[Conditional.scala 39:67] + node _T_4063 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 482:60] + node _T_4064 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 482:86] + node _T_4065 = dshr(buf_ldfwd, buf_dualtag[2]) @[lsu_bus_buffer.scala 482:101] + node _T_4066 = bits(_T_4065, 0, 0) @[lsu_bus_buffer.scala 482:101] + node _T_4067 = or(_T_4064, _T_4066) @[lsu_bus_buffer.scala 482:90] + node _T_4068 = or(_T_4067, any_done_wait_state) @[lsu_bus_buffer.scala 482:118] + node _T_4069 = mux(_T_4068, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 482:75] + node _T_4070 = mux(_T_4063, UInt<3>("h00"), _T_4069) @[lsu_bus_buffer.scala 482:31] + buf_nxtstate[2] <= _T_4070 @[lsu_bus_buffer.scala 482:25] + node _T_4071 = eq(bus_rsp_read_tag, buf_dualtag[2]) @[lsu_bus_buffer.scala 483:66] + node _T_4072 = dshr(buf_ldfwd, buf_dualtag[2]) @[lsu_bus_buffer.scala 484:21] + node _T_4073 = bits(_T_4072, 0, 0) @[lsu_bus_buffer.scala 484:21] + node _T_4074 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[2]]) @[lsu_bus_buffer.scala 484:58] + node _T_4075 = and(_T_4073, _T_4074) @[lsu_bus_buffer.scala 484:38] + node _T_4076 = or(_T_4071, _T_4075) @[lsu_bus_buffer.scala 483:95] + node _T_4077 = and(bus_rsp_read, _T_4076) @[lsu_bus_buffer.scala 483:45] + buf_state_bus_en[2] <= _T_4077 @[lsu_bus_buffer.scala 483:29] + node _T_4078 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 485:49] + node _T_4079 = or(_T_4078, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 485:70] + buf_state_en[2] <= _T_4079 @[lsu_bus_buffer.scala 485:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4080 = eq(UInt<3>("h05"), buf_state[2]) @[Conditional.scala 37:30] + when _T_4080 : @[Conditional.scala 39:67] + node _T_4081 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 488:60] + node _T_4082 = mux(_T_4081, UInt<3>("h00"), UInt<3>("h06")) @[lsu_bus_buffer.scala 488:31] + buf_nxtstate[2] <= _T_4082 @[lsu_bus_buffer.scala 488:25] + node _T_4083 = eq(RspPtr, UInt<2>("h02")) @[lsu_bus_buffer.scala 489:37] + node _T_4084 = eq(buf_dualtag[2], RspPtr) @[lsu_bus_buffer.scala 489:98] + node _T_4085 = and(buf_dual[2], _T_4084) @[lsu_bus_buffer.scala 489:80] + node _T_4086 = or(_T_4083, _T_4085) @[lsu_bus_buffer.scala 489:65] + node _T_4087 = or(_T_4086, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 489:112] + buf_state_en[2] <= _T_4087 @[lsu_bus_buffer.scala 489:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4088 = eq(UInt<3>("h06"), buf_state[2]) @[Conditional.scala 37:30] + when _T_4088 : @[Conditional.scala 39:67] + buf_nxtstate[2] <= UInt<3>("h00") @[lsu_bus_buffer.scala 492:25] + buf_rst[2] <= UInt<1>("h01") @[lsu_bus_buffer.scala 493:20] + buf_state_en[2] <= UInt<1>("h01") @[lsu_bus_buffer.scala 494:25] + buf_ldfwd_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 495:25] + buf_ldfwd_en[2] <= buf_state_en[2] @[lsu_bus_buffer.scala 496:25] + skip @[Conditional.scala 39:67] + node _T_4089 = bits(buf_state_en[2], 0, 0) @[lsu_bus_buffer.scala 499:108] + reg _T_4090 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4089 : @[Reg.scala 28:19] + _T_4090 <= buf_nxtstate[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_state[2] <= _T_4090 @[lsu_bus_buffer.scala 499:18] + reg _T_4091 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 500:60] + _T_4091 <= buf_age_in_2 @[lsu_bus_buffer.scala 500:60] + buf_ageQ[2] <= _T_4091 @[lsu_bus_buffer.scala 500:17] + reg _T_4092 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 501:63] + _T_4092 <= buf_rspage_in[2] @[lsu_bus_buffer.scala 501:63] + buf_rspageQ[2] <= _T_4092 @[lsu_bus_buffer.scala 501:20] + node _T_4093 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 502:109] + reg _T_4094 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4093 : @[Reg.scala 28:19] + _T_4094 <= buf_dualtag_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualtag[2] <= _T_4094 @[lsu_bus_buffer.scala 502:20] + node _T_4095 = bits(buf_dual_in, 2, 2) @[lsu_bus_buffer.scala 503:74] + node _T_4096 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 503:107] + reg _T_4097 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4096 : @[Reg.scala 28:19] + _T_4097 <= _T_4095 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dual[2] <= _T_4097 @[lsu_bus_buffer.scala 503:17] + node _T_4098 = bits(buf_samedw_in, 2, 2) @[lsu_bus_buffer.scala 504:78] + node _T_4099 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 504:111] + reg _T_4100 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4099 : @[Reg.scala 28:19] + _T_4100 <= _T_4098 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_samedw[2] <= _T_4100 @[lsu_bus_buffer.scala 504:19] + node _T_4101 = bits(buf_nomerge_in, 2, 2) @[lsu_bus_buffer.scala 505:80] + node _T_4102 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 505:113] + reg _T_4103 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4102 : @[Reg.scala 28:19] + _T_4103 <= _T_4101 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_nomerge[2] <= _T_4103 @[lsu_bus_buffer.scala 505:20] + node _T_4104 = bits(buf_dualhi_in, 2, 2) @[lsu_bus_buffer.scala 506:78] + node _T_4105 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 506:111] + reg _T_4106 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4105 : @[Reg.scala 28:19] + _T_4106 <= _T_4104 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualhi[2] <= _T_4106 @[lsu_bus_buffer.scala 506:19] + node _T_4107 = eq(UInt<3>("h00"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4107 : @[Conditional.scala 40:58] + node _T_4108 = bits(io.lsu_bus_clk_en, 0, 0) @[lsu_bus_buffer.scala 443:56] + node _T_4109 = mux(_T_4108, UInt<3>("h02"), UInt<3>("h01")) @[lsu_bus_buffer.scala 443:31] + buf_nxtstate[3] <= _T_4109 @[lsu_bus_buffer.scala 443:25] + node _T_4110 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 444:45] + node _T_4111 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 444:77] + node _T_4112 = eq(ibuf_merge_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 444:97] + node _T_4113 = and(_T_4111, _T_4112) @[lsu_bus_buffer.scala 444:95] + node _T_4114 = eq(UInt<2>("h03"), WrPtr0_r) @[lsu_bus_buffer.scala 444:117] + node _T_4115 = and(_T_4113, _T_4114) @[lsu_bus_buffer.scala 444:112] + node _T_4116 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 444:144] + node _T_4117 = eq(UInt<2>("h03"), WrPtr1_r) @[lsu_bus_buffer.scala 444:166] + node _T_4118 = and(_T_4116, _T_4117) @[lsu_bus_buffer.scala 444:161] + node _T_4119 = or(_T_4115, _T_4118) @[lsu_bus_buffer.scala 444:132] + node _T_4120 = and(_T_4110, _T_4119) @[lsu_bus_buffer.scala 444:63] + node _T_4121 = eq(UInt<2>("h03"), ibuf_tag) @[lsu_bus_buffer.scala 444:206] + node _T_4122 = and(ibuf_drain_vld, _T_4121) @[lsu_bus_buffer.scala 444:201] + node _T_4123 = or(_T_4120, _T_4122) @[lsu_bus_buffer.scala 444:183] + buf_state_en[3] <= _T_4123 @[lsu_bus_buffer.scala 444:25] + buf_wr_en[3] <= buf_state_en[3] @[lsu_bus_buffer.scala 445:22] + buf_data_en[3] <= buf_state_en[3] @[lsu_bus_buffer.scala 446:24] + node _T_4124 = eq(UInt<2>("h03"), ibuf_tag) @[lsu_bus_buffer.scala 447:52] + node _T_4125 = and(ibuf_drain_vld, _T_4124) @[lsu_bus_buffer.scala 447:47] + node _T_4126 = bits(_T_4125, 0, 0) @[lsu_bus_buffer.scala 447:73] + node _T_4127 = bits(ibuf_data_out, 31, 0) @[lsu_bus_buffer.scala 447:90] + node _T_4128 = bits(store_data_lo_r, 31, 0) @[lsu_bus_buffer.scala 447:114] + node _T_4129 = mux(_T_4126, _T_4127, _T_4128) @[lsu_bus_buffer.scala 447:30] + buf_data_in[3] <= _T_4129 @[lsu_bus_buffer.scala 447:24] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_4130 = eq(UInt<3>("h01"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4130 : @[Conditional.scala 39:67] + node _T_4131 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 450:60] + node _T_4132 = mux(_T_4131, UInt<3>("h00"), UInt<3>("h02")) @[lsu_bus_buffer.scala 450:31] + buf_nxtstate[3] <= _T_4132 @[lsu_bus_buffer.scala 450:25] + node _T_4133 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 451:46] + buf_state_en[3] <= _T_4133 @[lsu_bus_buffer.scala 451:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4134 = eq(UInt<3>("h02"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4134 : @[Conditional.scala 39:67] + node _T_4135 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 454:60] + node _T_4136 = and(obuf_nosend, bus_rsp_read) @[lsu_bus_buffer.scala 454:89] + node _T_4137 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 454:124] + node _T_4138 = and(_T_4136, _T_4137) @[lsu_bus_buffer.scala 454:104] + node _T_4139 = mux(_T_4138, UInt<3>("h05"), UInt<3>("h03")) @[lsu_bus_buffer.scala 454:75] + node _T_4140 = mux(_T_4135, UInt<3>("h00"), _T_4139) @[lsu_bus_buffer.scala 454:31] + buf_nxtstate[3] <= _T_4140 @[lsu_bus_buffer.scala 454:25] + node _T_4141 = eq(obuf_tag0, UInt<3>("h03")) @[lsu_bus_buffer.scala 455:48] + node _T_4142 = eq(obuf_tag1, UInt<3>("h03")) @[lsu_bus_buffer.scala 455:104] + node _T_4143 = and(obuf_merge, _T_4142) @[lsu_bus_buffer.scala 455:91] + node _T_4144 = or(_T_4141, _T_4143) @[lsu_bus_buffer.scala 455:77] + node _T_4145 = and(_T_4144, obuf_valid) @[lsu_bus_buffer.scala 455:135] + node _T_4146 = and(_T_4145, obuf_wr_enQ) @[lsu_bus_buffer.scala 455:148] + buf_cmd_state_bus_en[3] <= _T_4146 @[lsu_bus_buffer.scala 455:33] + buf_state_bus_en[3] <= buf_cmd_state_bus_en[3] @[lsu_bus_buffer.scala 456:29] + node _T_4147 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 457:49] + node _T_4148 = or(_T_4147, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 457:70] + buf_state_en[3] <= _T_4148 @[lsu_bus_buffer.scala 457:25] + buf_ldfwd_in[3] <= UInt<1>("h01") @[lsu_bus_buffer.scala 458:25] + node _T_4149 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 459:56] + node _T_4150 = eq(_T_4149, UInt<1>("h00")) @[lsu_bus_buffer.scala 459:46] + node _T_4151 = and(buf_state_en[3], _T_4150) @[lsu_bus_buffer.scala 459:44] + node _T_4152 = and(_T_4151, obuf_nosend) @[lsu_bus_buffer.scala 459:60] + node _T_4153 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 459:76] + node _T_4154 = and(_T_4152, _T_4153) @[lsu_bus_buffer.scala 459:74] + buf_ldfwd_en[3] <= _T_4154 @[lsu_bus_buffer.scala 459:25] + node _T_4155 = bits(obuf_rdrsp_tag, 1, 0) @[lsu_bus_buffer.scala 460:46] + buf_ldfwdtag_in[3] <= _T_4155 @[lsu_bus_buffer.scala 460:28] + node _T_4156 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 461:47] + node _T_4157 = and(_T_4156, obuf_nosend) @[lsu_bus_buffer.scala 461:67] + node _T_4158 = and(_T_4157, bus_rsp_read) @[lsu_bus_buffer.scala 461:81] + buf_data_en[3] <= _T_4158 @[lsu_bus_buffer.scala 461:24] + node _T_4159 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 462:48] + node _T_4160 = and(_T_4159, obuf_nosend) @[lsu_bus_buffer.scala 462:68] + node _T_4161 = and(_T_4160, bus_rsp_read_error) @[lsu_bus_buffer.scala 462:82] + buf_error_en[3] <= _T_4161 @[lsu_bus_buffer.scala 462:25] + node _T_4162 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 463:61] + node _T_4163 = bits(buf_addr[3], 2, 2) @[lsu_bus_buffer.scala 463:85] + node _T_4164 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 463:103] + node _T_4165 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 463:126] + node _T_4166 = mux(_T_4163, _T_4164, _T_4165) @[lsu_bus_buffer.scala 463:73] + node _T_4167 = mux(buf_error_en[3], _T_4162, _T_4166) @[lsu_bus_buffer.scala 463:30] + buf_data_in[3] <= _T_4167 @[lsu_bus_buffer.scala 463:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4168 = eq(UInt<3>("h03"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4168 : @[Conditional.scala 39:67] + node _T_4169 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 466:67] + node _T_4170 = and(UInt<1>("h01"), bus_rsp_write_error) @[lsu_bus_buffer.scala 466:94] + node _T_4171 = eq(_T_4170, UInt<1>("h00")) @[lsu_bus_buffer.scala 466:73] + node _T_4172 = and(_T_4169, _T_4171) @[lsu_bus_buffer.scala 466:71] + node _T_4173 = or(io.dec_tlu_force_halt, _T_4172) @[lsu_bus_buffer.scala 466:55] + node _T_4174 = bits(_T_4173, 0, 0) @[lsu_bus_buffer.scala 466:125] + node _T_4175 = eq(buf_samedw[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 467:30] + node _T_4176 = and(buf_dual[3], _T_4175) @[lsu_bus_buffer.scala 467:28] + node _T_4177 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 467:57] + node _T_4178 = eq(_T_4177, UInt<1>("h00")) @[lsu_bus_buffer.scala 467:47] + node _T_4179 = and(_T_4176, _T_4178) @[lsu_bus_buffer.scala 467:45] + node _T_4180 = neq(buf_state[buf_dualtag[3]], UInt<3>("h04")) @[lsu_bus_buffer.scala 467:90] + node _T_4181 = and(_T_4179, _T_4180) @[lsu_bus_buffer.scala 467:61] + node _T_4182 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 468:27] + node _T_4183 = or(_T_4182, any_done_wait_state) @[lsu_bus_buffer.scala 468:31] + node _T_4184 = eq(buf_samedw[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 468:70] + node _T_4185 = and(buf_dual[3], _T_4184) @[lsu_bus_buffer.scala 468:68] + node _T_4186 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 468:97] + node _T_4187 = eq(_T_4186, UInt<1>("h00")) @[lsu_bus_buffer.scala 468:87] + node _T_4188 = and(_T_4185, _T_4187) @[lsu_bus_buffer.scala 468:85] + node _T_4189 = eq(buf_dualtag[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_4190 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_4191 = eq(buf_dualtag[3], UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_4192 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_4193 = eq(buf_dualtag[3], UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_4194 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_4195 = eq(buf_dualtag[3], UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_4196 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 57:129] + node _T_4197 = mux(_T_4189, _T_4190, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4198 = mux(_T_4191, _T_4192, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4199 = mux(_T_4193, _T_4194, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4200 = mux(_T_4195, _T_4196, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4201 = or(_T_4197, _T_4198) @[Mux.scala 27:72] + node _T_4202 = or(_T_4201, _T_4199) @[Mux.scala 27:72] + node _T_4203 = or(_T_4202, _T_4200) @[Mux.scala 27:72] + wire _T_4204 : UInt<1> @[Mux.scala 27:72] + _T_4204 <= _T_4203 @[Mux.scala 27:72] + node _T_4205 = and(_T_4188, _T_4204) @[lsu_bus_buffer.scala 468:101] + node _T_4206 = eq(buf_state[buf_dualtag[3]], UInt<3>("h04")) @[lsu_bus_buffer.scala 468:167] + node _T_4207 = and(_T_4205, _T_4206) @[lsu_bus_buffer.scala 468:138] + node _T_4208 = and(_T_4207, any_done_wait_state) @[lsu_bus_buffer.scala 468:187] + node _T_4209 = or(_T_4183, _T_4208) @[lsu_bus_buffer.scala 468:53] + node _T_4210 = mux(_T_4209, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 468:16] + node _T_4211 = mux(_T_4181, UInt<3>("h04"), _T_4210) @[lsu_bus_buffer.scala 467:14] + node _T_4212 = mux(_T_4174, UInt<3>("h00"), _T_4211) @[lsu_bus_buffer.scala 466:31] + buf_nxtstate[3] <= _T_4212 @[lsu_bus_buffer.scala 466:25] + node _T_4213 = eq(bus_rsp_write_tag, UInt<3>("h03")) @[lsu_bus_buffer.scala 469:73] + node _T_4214 = and(bus_rsp_write, _T_4213) @[lsu_bus_buffer.scala 469:52] + node _T_4215 = eq(bus_rsp_read_tag, UInt<3>("h03")) @[lsu_bus_buffer.scala 470:46] + node _T_4216 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 471:23] + node _T_4217 = eq(bus_rsp_read_tag, buf_ldfwdtag[3]) @[lsu_bus_buffer.scala 471:47] + node _T_4218 = and(_T_4216, _T_4217) @[lsu_bus_buffer.scala 471:27] + node _T_4219 = or(_T_4215, _T_4218) @[lsu_bus_buffer.scala 470:77] + node _T_4220 = and(buf_dual[3], buf_dualhi[3]) @[lsu_bus_buffer.scala 472:26] + node _T_4221 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 472:54] + node _T_4222 = not(_T_4221) @[lsu_bus_buffer.scala 472:44] + node _T_4223 = and(_T_4220, _T_4222) @[lsu_bus_buffer.scala 472:42] + node _T_4224 = and(_T_4223, buf_samedw[3]) @[lsu_bus_buffer.scala 472:58] + node _T_4225 = eq(bus_rsp_read_tag, buf_dualtag[3]) @[lsu_bus_buffer.scala 472:94] + node _T_4226 = and(_T_4224, _T_4225) @[lsu_bus_buffer.scala 472:74] + node _T_4227 = or(_T_4219, _T_4226) @[lsu_bus_buffer.scala 471:71] + node _T_4228 = and(bus_rsp_read, _T_4227) @[lsu_bus_buffer.scala 470:25] + node _T_4229 = or(_T_4214, _T_4228) @[lsu_bus_buffer.scala 469:105] + buf_resp_state_bus_en[3] <= _T_4229 @[lsu_bus_buffer.scala 469:34] + buf_state_bus_en[3] <= buf_resp_state_bus_en[3] @[lsu_bus_buffer.scala 473:29] + node _T_4230 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 474:49] + node _T_4231 = or(_T_4230, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 474:70] + buf_state_en[3] <= _T_4231 @[lsu_bus_buffer.scala 474:25] + node _T_4232 = and(buf_state_bus_en[3], bus_rsp_read) @[lsu_bus_buffer.scala 475:47] + node _T_4233 = and(_T_4232, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 475:62] + buf_data_en[3] <= _T_4233 @[lsu_bus_buffer.scala 475:24] + node _T_4234 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 476:48] + node _T_4235 = eq(bus_rsp_read_tag, UInt<3>("h03")) @[lsu_bus_buffer.scala 476:111] + node _T_4236 = and(bus_rsp_read_error, _T_4235) @[lsu_bus_buffer.scala 476:91] + node _T_4237 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 477:42] + node _T_4238 = and(bus_rsp_read_error, _T_4237) @[lsu_bus_buffer.scala 477:31] + node _T_4239 = eq(bus_rsp_read_tag, buf_ldfwdtag[3]) @[lsu_bus_buffer.scala 477:66] + node _T_4240 = and(_T_4238, _T_4239) @[lsu_bus_buffer.scala 477:46] + node _T_4241 = or(_T_4236, _T_4240) @[lsu_bus_buffer.scala 476:143] + node _T_4242 = and(bus_rsp_write_error, UInt<1>("h01")) @[lsu_bus_buffer.scala 478:32] + node _T_4243 = eq(bus_rsp_write_tag, UInt<3>("h03")) @[lsu_bus_buffer.scala 478:74] + node _T_4244 = and(_T_4242, _T_4243) @[lsu_bus_buffer.scala 478:53] + node _T_4245 = or(_T_4241, _T_4244) @[lsu_bus_buffer.scala 477:88] + node _T_4246 = and(_T_4234, _T_4245) @[lsu_bus_buffer.scala 476:68] + buf_error_en[3] <= _T_4246 @[lsu_bus_buffer.scala 476:25] + node _T_4247 = eq(buf_error_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 479:50] + node _T_4248 = and(buf_state_en[3], _T_4247) @[lsu_bus_buffer.scala 479:48] + node _T_4249 = bits(buf_addr[3], 2, 2) @[lsu_bus_buffer.scala 479:84] + node _T_4250 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 479:102] + node _T_4251 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 479:125] + node _T_4252 = mux(_T_4249, _T_4250, _T_4251) @[lsu_bus_buffer.scala 479:72] + node _T_4253 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 479:148] + node _T_4254 = mux(_T_4248, _T_4252, _T_4253) @[lsu_bus_buffer.scala 479:30] + buf_data_in[3] <= _T_4254 @[lsu_bus_buffer.scala 479:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4255 = eq(UInt<3>("h04"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4255 : @[Conditional.scala 39:67] + node _T_4256 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 482:60] + node _T_4257 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 482:86] + node _T_4258 = dshr(buf_ldfwd, buf_dualtag[3]) @[lsu_bus_buffer.scala 482:101] + node _T_4259 = bits(_T_4258, 0, 0) @[lsu_bus_buffer.scala 482:101] + node _T_4260 = or(_T_4257, _T_4259) @[lsu_bus_buffer.scala 482:90] + node _T_4261 = or(_T_4260, any_done_wait_state) @[lsu_bus_buffer.scala 482:118] + node _T_4262 = mux(_T_4261, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 482:75] + node _T_4263 = mux(_T_4256, UInt<3>("h00"), _T_4262) @[lsu_bus_buffer.scala 482:31] + buf_nxtstate[3] <= _T_4263 @[lsu_bus_buffer.scala 482:25] + node _T_4264 = eq(bus_rsp_read_tag, buf_dualtag[3]) @[lsu_bus_buffer.scala 483:66] + node _T_4265 = dshr(buf_ldfwd, buf_dualtag[3]) @[lsu_bus_buffer.scala 484:21] + node _T_4266 = bits(_T_4265, 0, 0) @[lsu_bus_buffer.scala 484:21] + node _T_4267 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[3]]) @[lsu_bus_buffer.scala 484:58] + node _T_4268 = and(_T_4266, _T_4267) @[lsu_bus_buffer.scala 484:38] + node _T_4269 = or(_T_4264, _T_4268) @[lsu_bus_buffer.scala 483:95] + node _T_4270 = and(bus_rsp_read, _T_4269) @[lsu_bus_buffer.scala 483:45] + buf_state_bus_en[3] <= _T_4270 @[lsu_bus_buffer.scala 483:29] + node _T_4271 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 485:49] + node _T_4272 = or(_T_4271, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 485:70] + buf_state_en[3] <= _T_4272 @[lsu_bus_buffer.scala 485:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4273 = eq(UInt<3>("h05"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4273 : @[Conditional.scala 39:67] + node _T_4274 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 488:60] + node _T_4275 = mux(_T_4274, UInt<3>("h00"), UInt<3>("h06")) @[lsu_bus_buffer.scala 488:31] + buf_nxtstate[3] <= _T_4275 @[lsu_bus_buffer.scala 488:25] + node _T_4276 = eq(RspPtr, UInt<2>("h03")) @[lsu_bus_buffer.scala 489:37] + node _T_4277 = eq(buf_dualtag[3], RspPtr) @[lsu_bus_buffer.scala 489:98] + node _T_4278 = and(buf_dual[3], _T_4277) @[lsu_bus_buffer.scala 489:80] + node _T_4279 = or(_T_4276, _T_4278) @[lsu_bus_buffer.scala 489:65] + node _T_4280 = or(_T_4279, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 489:112] + buf_state_en[3] <= _T_4280 @[lsu_bus_buffer.scala 489:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4281 = eq(UInt<3>("h06"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4281 : @[Conditional.scala 39:67] + buf_nxtstate[3] <= UInt<3>("h00") @[lsu_bus_buffer.scala 492:25] + buf_rst[3] <= UInt<1>("h01") @[lsu_bus_buffer.scala 493:20] + buf_state_en[3] <= UInt<1>("h01") @[lsu_bus_buffer.scala 494:25] + buf_ldfwd_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 495:25] + buf_ldfwd_en[3] <= buf_state_en[3] @[lsu_bus_buffer.scala 496:25] + skip @[Conditional.scala 39:67] + node _T_4282 = bits(buf_state_en[3], 0, 0) @[lsu_bus_buffer.scala 499:108] + reg _T_4283 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4282 : @[Reg.scala 28:19] + _T_4283 <= buf_nxtstate[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_state[3] <= _T_4283 @[lsu_bus_buffer.scala 499:18] + reg _T_4284 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 500:60] + _T_4284 <= buf_age_in_3 @[lsu_bus_buffer.scala 500:60] + buf_ageQ[3] <= _T_4284 @[lsu_bus_buffer.scala 500:17] + reg _T_4285 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 501:63] + _T_4285 <= buf_rspage_in[3] @[lsu_bus_buffer.scala 501:63] + buf_rspageQ[3] <= _T_4285 @[lsu_bus_buffer.scala 501:20] + node _T_4286 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 502:109] + reg _T_4287 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4286 : @[Reg.scala 28:19] + _T_4287 <= buf_dualtag_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualtag[3] <= _T_4287 @[lsu_bus_buffer.scala 502:20] + node _T_4288 = bits(buf_dual_in, 3, 3) @[lsu_bus_buffer.scala 503:74] + node _T_4289 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 503:107] + reg _T_4290 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4289 : @[Reg.scala 28:19] + _T_4290 <= _T_4288 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dual[3] <= _T_4290 @[lsu_bus_buffer.scala 503:17] + node _T_4291 = bits(buf_samedw_in, 3, 3) @[lsu_bus_buffer.scala 504:78] + node _T_4292 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 504:111] + reg _T_4293 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4292 : @[Reg.scala 28:19] + _T_4293 <= _T_4291 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_samedw[3] <= _T_4293 @[lsu_bus_buffer.scala 504:19] + node _T_4294 = bits(buf_nomerge_in, 3, 3) @[lsu_bus_buffer.scala 505:80] + node _T_4295 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 505:113] + reg _T_4296 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4295 : @[Reg.scala 28:19] + _T_4296 <= _T_4294 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_nomerge[3] <= _T_4296 @[lsu_bus_buffer.scala 505:20] + node _T_4297 = bits(buf_dualhi_in, 3, 3) @[lsu_bus_buffer.scala 506:78] + node _T_4298 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 506:111] + reg _T_4299 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4298 : @[Reg.scala 28:19] + _T_4299 <= _T_4297 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualhi[3] <= _T_4299 @[lsu_bus_buffer.scala 506:19] + node _T_4300 = bits(buf_ldfwd_en[0], 0, 0) @[lsu_bus_buffer.scala 509:131] + reg _T_4301 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4300 : @[Reg.scala 28:19] + _T_4301 <= buf_ldfwd_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4302 = bits(buf_ldfwd_en[1], 0, 0) @[lsu_bus_buffer.scala 509:131] + reg _T_4303 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4302 : @[Reg.scala 28:19] + _T_4303 <= buf_ldfwd_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4304 = bits(buf_ldfwd_en[2], 0, 0) @[lsu_bus_buffer.scala 509:131] + reg _T_4305 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4304 : @[Reg.scala 28:19] + _T_4305 <= buf_ldfwd_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4306 = bits(buf_ldfwd_en[3], 0, 0) @[lsu_bus_buffer.scala 509:131] + reg _T_4307 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4306 : @[Reg.scala 28:19] + _T_4307 <= buf_ldfwd_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4308 = cat(_T_4307, _T_4305) @[Cat.scala 29:58] + node _T_4309 = cat(_T_4308, _T_4303) @[Cat.scala 29:58] + node _T_4310 = cat(_T_4309, _T_4301) @[Cat.scala 29:58] + buf_ldfwd <= _T_4310 @[lsu_bus_buffer.scala 509:13] + node _T_4311 = bits(buf_ldfwd_en[0], 0, 0) @[lsu_bus_buffer.scala 510:132] + reg _T_4312 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4311 : @[Reg.scala 28:19] + _T_4312 <= buf_ldfwdtag_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4313 = bits(buf_ldfwd_en[1], 0, 0) @[lsu_bus_buffer.scala 510:132] + reg _T_4314 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4313 : @[Reg.scala 28:19] + _T_4314 <= buf_ldfwdtag_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4315 = bits(buf_ldfwd_en[2], 0, 0) @[lsu_bus_buffer.scala 510:132] + reg _T_4316 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4315 : @[Reg.scala 28:19] + _T_4316 <= buf_ldfwdtag_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4317 = bits(buf_ldfwd_en[3], 0, 0) @[lsu_bus_buffer.scala 510:132] + reg _T_4318 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4317 : @[Reg.scala 28:19] + _T_4318 <= buf_ldfwdtag_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_ldfwdtag[0] <= _T_4312 @[lsu_bus_buffer.scala 510:16] + buf_ldfwdtag[1] <= _T_4314 @[lsu_bus_buffer.scala 510:16] + buf_ldfwdtag[2] <= _T_4316 @[lsu_bus_buffer.scala 510:16] + buf_ldfwdtag[3] <= _T_4318 @[lsu_bus_buffer.scala 510:16] + node _T_4319 = bits(buf_sideeffect_in, 0, 0) @[lsu_bus_buffer.scala 511:105] + node _T_4320 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 511:138] + reg _T_4321 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4320 : @[Reg.scala 28:19] + _T_4321 <= _T_4319 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4322 = bits(buf_sideeffect_in, 1, 1) @[lsu_bus_buffer.scala 511:105] + node _T_4323 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 511:138] + reg _T_4324 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4323 : @[Reg.scala 28:19] + _T_4324 <= _T_4322 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4325 = bits(buf_sideeffect_in, 2, 2) @[lsu_bus_buffer.scala 511:105] + node _T_4326 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 511:138] + reg _T_4327 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4326 : @[Reg.scala 28:19] + _T_4327 <= _T_4325 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4328 = bits(buf_sideeffect_in, 3, 3) @[lsu_bus_buffer.scala 511:105] + node _T_4329 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 511:138] + reg _T_4330 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4329 : @[Reg.scala 28:19] + _T_4330 <= _T_4328 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4331 = cat(_T_4330, _T_4327) @[Cat.scala 29:58] + node _T_4332 = cat(_T_4331, _T_4324) @[Cat.scala 29:58] + node _T_4333 = cat(_T_4332, _T_4321) @[Cat.scala 29:58] + buf_sideeffect <= _T_4333 @[lsu_bus_buffer.scala 511:18] + node _T_4334 = bits(buf_unsign_in, 0, 0) @[lsu_bus_buffer.scala 512:97] + node _T_4335 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 512:130] + reg _T_4336 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4335 : @[Reg.scala 28:19] + _T_4336 <= _T_4334 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4337 = bits(buf_unsign_in, 1, 1) @[lsu_bus_buffer.scala 512:97] + node _T_4338 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 512:130] + reg _T_4339 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4338 : @[Reg.scala 28:19] + _T_4339 <= _T_4337 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4340 = bits(buf_unsign_in, 2, 2) @[lsu_bus_buffer.scala 512:97] + node _T_4341 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 512:130] + reg _T_4342 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4341 : @[Reg.scala 28:19] + _T_4342 <= _T_4340 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4343 = bits(buf_unsign_in, 3, 3) @[lsu_bus_buffer.scala 512:97] + node _T_4344 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 512:130] + reg _T_4345 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4344 : @[Reg.scala 28:19] + _T_4345 <= _T_4343 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4346 = cat(_T_4345, _T_4342) @[Cat.scala 29:58] + node _T_4347 = cat(_T_4346, _T_4339) @[Cat.scala 29:58] + node _T_4348 = cat(_T_4347, _T_4336) @[Cat.scala 29:58] + buf_unsign <= _T_4348 @[lsu_bus_buffer.scala 512:14] + node _T_4349 = bits(buf_write_in, 0, 0) @[lsu_bus_buffer.scala 513:95] + node _T_4350 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 513:128] + reg _T_4351 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4350 : @[Reg.scala 28:19] + _T_4351 <= _T_4349 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4352 = bits(buf_write_in, 1, 1) @[lsu_bus_buffer.scala 513:95] + node _T_4353 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 513:128] + reg _T_4354 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4353 : @[Reg.scala 28:19] + _T_4354 <= _T_4352 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4355 = bits(buf_write_in, 2, 2) @[lsu_bus_buffer.scala 513:95] + node _T_4356 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 513:128] + reg _T_4357 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4356 : @[Reg.scala 28:19] + _T_4357 <= _T_4355 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4358 = bits(buf_write_in, 3, 3) @[lsu_bus_buffer.scala 513:95] + node _T_4359 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 513:128] + reg _T_4360 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4359 : @[Reg.scala 28:19] + _T_4360 <= _T_4358 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4361 = cat(_T_4360, _T_4357) @[Cat.scala 29:58] + node _T_4362 = cat(_T_4361, _T_4354) @[Cat.scala 29:58] + node _T_4363 = cat(_T_4362, _T_4351) @[Cat.scala 29:58] + buf_write <= _T_4363 @[lsu_bus_buffer.scala 513:13] + node _T_4364 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 514:117] + reg _T_4365 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4364 : @[Reg.scala 28:19] + _T_4365 <= buf_sz_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4366 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 514:117] + reg _T_4367 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4366 : @[Reg.scala 28:19] + _T_4367 <= buf_sz_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4368 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 514:117] + reg _T_4369 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4368 : @[Reg.scala 28:19] + _T_4369 <= buf_sz_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4370 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 514:117] + reg _T_4371 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4370 : @[Reg.scala 28:19] + _T_4371 <= buf_sz_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_sz[0] <= _T_4365 @[lsu_bus_buffer.scala 514:10] + buf_sz[1] <= _T_4367 @[lsu_bus_buffer.scala 514:10] + buf_sz[2] <= _T_4369 @[lsu_bus_buffer.scala 514:10] + buf_sz[3] <= _T_4371 @[lsu_bus_buffer.scala 514:10] + node _T_4372 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 515:80] + inst rvclkhdr_4 of rvclkhdr_28 @[lib.scala 368:23] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= reset + rvclkhdr_4.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_4.io.en <= _T_4372 @[lib.scala 371:17] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_4373 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_4373 <= buf_addr_in[0] @[lib.scala 374:16] + node _T_4374 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 515:80] + inst rvclkhdr_5 of rvclkhdr_29 @[lib.scala 368:23] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= reset + rvclkhdr_5.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_5.io.en <= _T_4374 @[lib.scala 371:17] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_4375 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_4375 <= buf_addr_in[1] @[lib.scala 374:16] + node _T_4376 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 515:80] + inst rvclkhdr_6 of rvclkhdr_30 @[lib.scala 368:23] + rvclkhdr_6.clock <= clock + rvclkhdr_6.reset <= reset + rvclkhdr_6.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_6.io.en <= _T_4376 @[lib.scala 371:17] + rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_4377 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_4377 <= buf_addr_in[2] @[lib.scala 374:16] + node _T_4378 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 515:80] + inst rvclkhdr_7 of rvclkhdr_31 @[lib.scala 368:23] + rvclkhdr_7.clock <= clock + rvclkhdr_7.reset <= reset + rvclkhdr_7.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_7.io.en <= _T_4378 @[lib.scala 371:17] + rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_4379 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_4379 <= buf_addr_in[3] @[lib.scala 374:16] + buf_addr[0] <= _T_4373 @[lsu_bus_buffer.scala 515:12] + buf_addr[1] <= _T_4375 @[lsu_bus_buffer.scala 515:12] + buf_addr[2] <= _T_4377 @[lsu_bus_buffer.scala 515:12] + buf_addr[3] <= _T_4379 @[lsu_bus_buffer.scala 515:12] + node _T_4380 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 516:125] + reg _T_4381 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4380 : @[Reg.scala 28:19] + _T_4381 <= buf_byteen_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4382 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 516:125] + reg _T_4383 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4382 : @[Reg.scala 28:19] + _T_4383 <= buf_byteen_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4384 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 516:125] + reg _T_4385 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4384 : @[Reg.scala 28:19] + _T_4385 <= buf_byteen_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4386 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 516:125] + reg _T_4387 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4386 : @[Reg.scala 28:19] + _T_4387 <= buf_byteen_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_byteen[0] <= _T_4381 @[lsu_bus_buffer.scala 516:14] + buf_byteen[1] <= _T_4383 @[lsu_bus_buffer.scala 516:14] + buf_byteen[2] <= _T_4385 @[lsu_bus_buffer.scala 516:14] + buf_byteen[3] <= _T_4387 @[lsu_bus_buffer.scala 516:14] + inst rvclkhdr_8 of rvclkhdr_32 @[lib.scala 368:23] + rvclkhdr_8.clock <= clock + rvclkhdr_8.reset <= reset + rvclkhdr_8.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_8.io.en <= buf_data_en[0] @[lib.scala 371:17] + rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_4388 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_4388 <= buf_data_in[0] @[lib.scala 374:16] + inst rvclkhdr_9 of rvclkhdr_33 @[lib.scala 368:23] + rvclkhdr_9.clock <= clock + rvclkhdr_9.reset <= reset + rvclkhdr_9.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_9.io.en <= buf_data_en[1] @[lib.scala 371:17] + rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_4389 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_4389 <= buf_data_in[1] @[lib.scala 374:16] + inst rvclkhdr_10 of rvclkhdr_34 @[lib.scala 368:23] + rvclkhdr_10.clock <= clock + rvclkhdr_10.reset <= reset + rvclkhdr_10.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_10.io.en <= buf_data_en[2] @[lib.scala 371:17] + rvclkhdr_10.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_4390 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_4390 <= buf_data_in[2] @[lib.scala 374:16] + inst rvclkhdr_11 of rvclkhdr_35 @[lib.scala 368:23] + rvclkhdr_11.clock <= clock + rvclkhdr_11.reset <= reset + rvclkhdr_11.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_11.io.en <= buf_data_en[3] @[lib.scala 371:17] + rvclkhdr_11.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_4391 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_4391 <= buf_data_in[3] @[lib.scala 374:16] + buf_data[0] <= _T_4388 @[lsu_bus_buffer.scala 517:12] + buf_data[1] <= _T_4389 @[lsu_bus_buffer.scala 517:12] + buf_data[2] <= _T_4390 @[lsu_bus_buffer.scala 517:12] + buf_data[3] <= _T_4391 @[lsu_bus_buffer.scala 517:12] + node _T_4392 = bits(buf_error, 0, 0) @[lsu_bus_buffer.scala 518:119] + node _T_4393 = mux(buf_error_en[0], UInt<1>("h01"), _T_4392) @[lsu_bus_buffer.scala 518:84] + node _T_4394 = eq(buf_rst[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 518:126] + node _T_4395 = and(_T_4393, _T_4394) @[lsu_bus_buffer.scala 518:124] + reg _T_4396 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 518:80] + _T_4396 <= _T_4395 @[lsu_bus_buffer.scala 518:80] + node _T_4397 = bits(buf_error, 1, 1) @[lsu_bus_buffer.scala 518:119] + node _T_4398 = mux(buf_error_en[1], UInt<1>("h01"), _T_4397) @[lsu_bus_buffer.scala 518:84] + node _T_4399 = eq(buf_rst[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 518:126] + node _T_4400 = and(_T_4398, _T_4399) @[lsu_bus_buffer.scala 518:124] + reg _T_4401 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 518:80] + _T_4401 <= _T_4400 @[lsu_bus_buffer.scala 518:80] + node _T_4402 = bits(buf_error, 2, 2) @[lsu_bus_buffer.scala 518:119] + node _T_4403 = mux(buf_error_en[2], UInt<1>("h01"), _T_4402) @[lsu_bus_buffer.scala 518:84] + node _T_4404 = eq(buf_rst[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 518:126] + node _T_4405 = and(_T_4403, _T_4404) @[lsu_bus_buffer.scala 518:124] + reg _T_4406 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 518:80] + _T_4406 <= _T_4405 @[lsu_bus_buffer.scala 518:80] + node _T_4407 = bits(buf_error, 3, 3) @[lsu_bus_buffer.scala 518:119] + node _T_4408 = mux(buf_error_en[3], UInt<1>("h01"), _T_4407) @[lsu_bus_buffer.scala 518:84] + node _T_4409 = eq(buf_rst[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 518:126] + node _T_4410 = and(_T_4408, _T_4409) @[lsu_bus_buffer.scala 518:124] + reg _T_4411 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 518:80] + _T_4411 <= _T_4410 @[lsu_bus_buffer.scala 518:80] + node _T_4412 = cat(_T_4411, _T_4406) @[Cat.scala 29:58] + node _T_4413 = cat(_T_4412, _T_4401) @[Cat.scala 29:58] + node _T_4414 = cat(_T_4413, _T_4396) @[Cat.scala 29:58] + buf_error <= _T_4414 @[lsu_bus_buffer.scala 518:13] + node _T_4415 = cat(io.lsu_busreq_m, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_4416 = mux(io.ldst_dual_m, _T_4415, io.lsu_busreq_m) @[lsu_bus_buffer.scala 521:28] + node _T_4417 = cat(io.lsu_busreq_r, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_4418 = mux(io.ldst_dual_r, _T_4417, io.lsu_busreq_r) @[lsu_bus_buffer.scala 521:94] + node _T_4419 = add(_T_4416, _T_4418) @[lsu_bus_buffer.scala 521:88] + node _T_4420 = add(_T_4419, ibuf_valid) @[lsu_bus_buffer.scala 521:154] + node _T_4421 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 521:190] + node _T_4422 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 521:190] + node _T_4423 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 521:190] + node _T_4424 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 521:190] + node _T_4425 = add(_T_4421, _T_4422) @[lsu_bus_buffer.scala 521:217] + node _T_4426 = add(_T_4425, _T_4423) @[lsu_bus_buffer.scala 521:217] + node _T_4427 = add(_T_4426, _T_4424) @[lsu_bus_buffer.scala 521:217] + node _T_4428 = add(_T_4420, _T_4427) @[lsu_bus_buffer.scala 521:169] + node buf_numvld_any = tail(_T_4428, 1) @[lsu_bus_buffer.scala 521:169] + node _T_4429 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 522:60] + node _T_4430 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 522:79] + node _T_4431 = and(_T_4429, _T_4430) @[lsu_bus_buffer.scala 522:64] + node _T_4432 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 522:91] + node _T_4433 = and(_T_4431, _T_4432) @[lsu_bus_buffer.scala 522:89] + node _T_4434 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 522:60] + node _T_4435 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 522:79] + node _T_4436 = and(_T_4434, _T_4435) @[lsu_bus_buffer.scala 522:64] + node _T_4437 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 522:91] + node _T_4438 = and(_T_4436, _T_4437) @[lsu_bus_buffer.scala 522:89] + node _T_4439 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 522:60] + node _T_4440 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 522:79] + node _T_4441 = and(_T_4439, _T_4440) @[lsu_bus_buffer.scala 522:64] + node _T_4442 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 522:91] + node _T_4443 = and(_T_4441, _T_4442) @[lsu_bus_buffer.scala 522:89] + node _T_4444 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 522:60] + node _T_4445 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 522:79] + node _T_4446 = and(_T_4444, _T_4445) @[lsu_bus_buffer.scala 522:64] + node _T_4447 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 522:91] + node _T_4448 = and(_T_4446, _T_4447) @[lsu_bus_buffer.scala 522:89] + node _T_4449 = add(_T_4448, _T_4443) @[lsu_bus_buffer.scala 522:142] + node _T_4450 = add(_T_4449, _T_4438) @[lsu_bus_buffer.scala 522:142] + node _T_4451 = add(_T_4450, _T_4433) @[lsu_bus_buffer.scala 522:142] + buf_numvld_wrcmd_any <= _T_4451 @[lsu_bus_buffer.scala 522:24] + node _T_4452 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 523:63] + node _T_4453 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 523:75] + node _T_4454 = and(_T_4452, _T_4453) @[lsu_bus_buffer.scala 523:73] + node _T_4455 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 523:63] + node _T_4456 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 523:75] + node _T_4457 = and(_T_4455, _T_4456) @[lsu_bus_buffer.scala 523:73] + node _T_4458 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 523:63] + node _T_4459 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 523:75] + node _T_4460 = and(_T_4458, _T_4459) @[lsu_bus_buffer.scala 523:73] + node _T_4461 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 523:63] + node _T_4462 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 523:75] + node _T_4463 = and(_T_4461, _T_4462) @[lsu_bus_buffer.scala 523:73] + node _T_4464 = add(_T_4463, _T_4460) @[lsu_bus_buffer.scala 523:126] + node _T_4465 = add(_T_4464, _T_4457) @[lsu_bus_buffer.scala 523:126] + node _T_4466 = add(_T_4465, _T_4454) @[lsu_bus_buffer.scala 523:126] + buf_numvld_cmd_any <= _T_4466 @[lsu_bus_buffer.scala 523:22] + node _T_4467 = eq(buf_state[0], UInt<3>("h01")) @[lsu_bus_buffer.scala 524:63] + node _T_4468 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 524:90] + node _T_4469 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 524:102] + node _T_4470 = and(_T_4468, _T_4469) @[lsu_bus_buffer.scala 524:100] + node _T_4471 = or(_T_4467, _T_4470) @[lsu_bus_buffer.scala 524:74] + node _T_4472 = eq(buf_state[1], UInt<3>("h01")) @[lsu_bus_buffer.scala 524:63] + node _T_4473 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 524:90] + node _T_4474 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 524:102] + node _T_4475 = and(_T_4473, _T_4474) @[lsu_bus_buffer.scala 524:100] + node _T_4476 = or(_T_4472, _T_4475) @[lsu_bus_buffer.scala 524:74] + node _T_4477 = eq(buf_state[2], UInt<3>("h01")) @[lsu_bus_buffer.scala 524:63] + node _T_4478 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 524:90] + node _T_4479 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 524:102] + node _T_4480 = and(_T_4478, _T_4479) @[lsu_bus_buffer.scala 524:100] + node _T_4481 = or(_T_4477, _T_4480) @[lsu_bus_buffer.scala 524:74] + node _T_4482 = eq(buf_state[3], UInt<3>("h01")) @[lsu_bus_buffer.scala 524:63] + node _T_4483 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 524:90] + node _T_4484 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 524:102] + node _T_4485 = and(_T_4483, _T_4484) @[lsu_bus_buffer.scala 524:100] + node _T_4486 = or(_T_4482, _T_4485) @[lsu_bus_buffer.scala 524:74] + node _T_4487 = add(_T_4486, _T_4481) @[lsu_bus_buffer.scala 524:154] + node _T_4488 = add(_T_4487, _T_4476) @[lsu_bus_buffer.scala 524:154] + node _T_4489 = add(_T_4488, _T_4471) @[lsu_bus_buffer.scala 524:154] + buf_numvld_pend_any <= _T_4489 @[lsu_bus_buffer.scala 524:23] + node _T_4490 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 525:61] + node _T_4491 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 525:61] + node _T_4492 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 525:61] + node _T_4493 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 525:61] + node _T_4494 = or(_T_4493, _T_4492) @[lsu_bus_buffer.scala 525:93] + node _T_4495 = or(_T_4494, _T_4491) @[lsu_bus_buffer.scala 525:93] + node _T_4496 = or(_T_4495, _T_4490) @[lsu_bus_buffer.scala 525:93] + any_done_wait_state <= _T_4496 @[lsu_bus_buffer.scala 525:23] + node _T_4497 = orr(buf_numvld_pend_any) @[lsu_bus_buffer.scala 526:53] + io.lsu_bus_buffer_pend_any <= _T_4497 @[lsu_bus_buffer.scala 526:30] + node _T_4498 = and(io.ldst_dual_d, io.dec_lsu_valid_raw_d) @[lsu_bus_buffer.scala 527:52] + node _T_4499 = geq(buf_numvld_any, UInt<2>("h03")) @[lsu_bus_buffer.scala 527:92] + node _T_4500 = eq(buf_numvld_any, UInt<3>("h04")) @[lsu_bus_buffer.scala 527:121] + node _T_4501 = mux(_T_4498, _T_4499, _T_4500) @[lsu_bus_buffer.scala 527:36] + io.lsu_bus_buffer_full_any <= _T_4501 @[lsu_bus_buffer.scala 527:30] + node _T_4502 = orr(buf_state[0]) @[lsu_bus_buffer.scala 528:52] + node _T_4503 = orr(buf_state[1]) @[lsu_bus_buffer.scala 528:52] + node _T_4504 = orr(buf_state[2]) @[lsu_bus_buffer.scala 528:52] + node _T_4505 = orr(buf_state[3]) @[lsu_bus_buffer.scala 528:52] + node _T_4506 = or(_T_4502, _T_4503) @[lsu_bus_buffer.scala 528:65] + node _T_4507 = or(_T_4506, _T_4504) @[lsu_bus_buffer.scala 528:65] + node _T_4508 = or(_T_4507, _T_4505) @[lsu_bus_buffer.scala 528:65] + node _T_4509 = eq(_T_4508, UInt<1>("h00")) @[lsu_bus_buffer.scala 528:34] + node _T_4510 = eq(ibuf_valid, UInt<1>("h00")) @[lsu_bus_buffer.scala 528:72] + node _T_4511 = and(_T_4509, _T_4510) @[lsu_bus_buffer.scala 528:70] + node _T_4512 = eq(obuf_valid, UInt<1>("h00")) @[lsu_bus_buffer.scala 528:86] + node _T_4513 = and(_T_4511, _T_4512) @[lsu_bus_buffer.scala 528:84] + io.lsu_bus_buffer_empty_any <= _T_4513 @[lsu_bus_buffer.scala 528:31] + node _T_4514 = and(io.lsu_busreq_m, io.lsu_pkt_m.valid) @[lsu_bus_buffer.scala 530:64] + node _T_4515 = and(_T_4514, io.lsu_pkt_m.bits.load) @[lsu_bus_buffer.scala 530:85] + node _T_4516 = eq(io.flush_m_up, UInt<1>("h00")) @[lsu_bus_buffer.scala 530:112] + node _T_4517 = and(_T_4515, _T_4516) @[lsu_bus_buffer.scala 530:110] + node _T_4518 = eq(io.ld_full_hit_m, UInt<1>("h00")) @[lsu_bus_buffer.scala 530:129] + node _T_4519 = and(_T_4517, _T_4518) @[lsu_bus_buffer.scala 530:127] + io.dctl_busbuff.lsu_nonblock_load_valid_m <= _T_4519 @[lsu_bus_buffer.scala 530:45] + io.dctl_busbuff.lsu_nonblock_load_tag_m <= WrPtr0_m @[lsu_bus_buffer.scala 531:43] + wire lsu_nonblock_load_valid_r : UInt<1> + lsu_nonblock_load_valid_r <= UInt<1>("h00") + node _T_4520 = eq(io.lsu_commit_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 533:74] + node _T_4521 = and(lsu_nonblock_load_valid_r, _T_4520) @[lsu_bus_buffer.scala 533:72] + io.dctl_busbuff.lsu_nonblock_load_inv_r <= _T_4521 @[lsu_bus_buffer.scala 533:43] + io.dctl_busbuff.lsu_nonblock_load_inv_tag_r <= WrPtr0_r @[lsu_bus_buffer.scala 534:47] + node _T_4522 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 535:80] + node _T_4523 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 535:127] + node _T_4524 = and(UInt<1>("h01"), _T_4523) @[lsu_bus_buffer.scala 535:116] + node _T_4525 = eq(_T_4524, UInt<1>("h00")) @[lsu_bus_buffer.scala 535:95] + node _T_4526 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 535:80] + node _T_4527 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 535:127] + node _T_4528 = and(UInt<1>("h01"), _T_4527) @[lsu_bus_buffer.scala 535:116] + node _T_4529 = eq(_T_4528, UInt<1>("h00")) @[lsu_bus_buffer.scala 535:95] + node _T_4530 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 535:80] + node _T_4531 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 535:127] + node _T_4532 = and(UInt<1>("h01"), _T_4531) @[lsu_bus_buffer.scala 535:116] + node _T_4533 = eq(_T_4532, UInt<1>("h00")) @[lsu_bus_buffer.scala 535:95] + node _T_4534 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 535:80] + node _T_4535 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 535:127] + node _T_4536 = and(UInt<1>("h01"), _T_4535) @[lsu_bus_buffer.scala 535:116] + node _T_4537 = eq(_T_4536, UInt<1>("h00")) @[lsu_bus_buffer.scala 535:95] + node _T_4538 = mux(_T_4522, _T_4525, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4539 = mux(_T_4526, _T_4529, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4540 = mux(_T_4530, _T_4533, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4541 = mux(_T_4534, _T_4537, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4542 = or(_T_4538, _T_4539) @[Mux.scala 27:72] + node _T_4543 = or(_T_4542, _T_4540) @[Mux.scala 27:72] + node _T_4544 = or(_T_4543, _T_4541) @[Mux.scala 27:72] + wire lsu_nonblock_load_data_ready : UInt<1> @[Mux.scala 27:72] + lsu_nonblock_load_data_ready <= _T_4544 @[Mux.scala 27:72] + node _T_4545 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 536:93] + node _T_4546 = bits(buf_error, 0, 0) @[lsu_bus_buffer.scala 536:117] + node _T_4547 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 536:133] + node _T_4548 = eq(_T_4547, UInt<1>("h00")) @[lsu_bus_buffer.scala 536:123] + node _T_4549 = and(_T_4546, _T_4548) @[lsu_bus_buffer.scala 536:121] + node _T_4550 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 536:93] + node _T_4551 = bits(buf_error, 1, 1) @[lsu_bus_buffer.scala 536:117] + node _T_4552 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 536:133] + node _T_4553 = eq(_T_4552, UInt<1>("h00")) @[lsu_bus_buffer.scala 536:123] + node _T_4554 = and(_T_4551, _T_4553) @[lsu_bus_buffer.scala 536:121] + node _T_4555 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 536:93] + node _T_4556 = bits(buf_error, 2, 2) @[lsu_bus_buffer.scala 536:117] + node _T_4557 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 536:133] + node _T_4558 = eq(_T_4557, UInt<1>("h00")) @[lsu_bus_buffer.scala 536:123] + node _T_4559 = and(_T_4556, _T_4558) @[lsu_bus_buffer.scala 536:121] + node _T_4560 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 536:93] + node _T_4561 = bits(buf_error, 3, 3) @[lsu_bus_buffer.scala 536:117] + node _T_4562 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 536:133] + node _T_4563 = eq(_T_4562, UInt<1>("h00")) @[lsu_bus_buffer.scala 536:123] + node _T_4564 = and(_T_4561, _T_4563) @[lsu_bus_buffer.scala 536:121] + node _T_4565 = mux(_T_4545, _T_4549, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4566 = mux(_T_4550, _T_4554, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4567 = mux(_T_4555, _T_4559, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4568 = mux(_T_4560, _T_4564, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4569 = or(_T_4565, _T_4566) @[Mux.scala 27:72] + node _T_4570 = or(_T_4569, _T_4567) @[Mux.scala 27:72] + node _T_4571 = or(_T_4570, _T_4568) @[Mux.scala 27:72] + wire _T_4572 : UInt<1> @[Mux.scala 27:72] + _T_4572 <= _T_4571 @[Mux.scala 27:72] + io.dctl_busbuff.lsu_nonblock_load_data_error <= _T_4572 @[lsu_bus_buffer.scala 536:48] + node _T_4573 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 537:92] + node _T_4574 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 537:115] + node _T_4575 = eq(_T_4574, UInt<1>("h00")) @[lsu_bus_buffer.scala 537:105] + node _T_4576 = and(_T_4573, _T_4575) @[lsu_bus_buffer.scala 537:103] + node _T_4577 = eq(buf_dual[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 537:122] + node _T_4578 = eq(buf_dualhi[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 537:137] + node _T_4579 = or(_T_4577, _T_4578) @[lsu_bus_buffer.scala 537:135] + node _T_4580 = and(_T_4576, _T_4579) @[lsu_bus_buffer.scala 537:119] + node _T_4581 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 537:92] + node _T_4582 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 537:115] + node _T_4583 = eq(_T_4582, UInt<1>("h00")) @[lsu_bus_buffer.scala 537:105] + node _T_4584 = and(_T_4581, _T_4583) @[lsu_bus_buffer.scala 537:103] + node _T_4585 = eq(buf_dual[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 537:122] + node _T_4586 = eq(buf_dualhi[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 537:137] + node _T_4587 = or(_T_4585, _T_4586) @[lsu_bus_buffer.scala 537:135] + node _T_4588 = and(_T_4584, _T_4587) @[lsu_bus_buffer.scala 537:119] + node _T_4589 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 537:92] + node _T_4590 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 537:115] + node _T_4591 = eq(_T_4590, UInt<1>("h00")) @[lsu_bus_buffer.scala 537:105] + node _T_4592 = and(_T_4589, _T_4591) @[lsu_bus_buffer.scala 537:103] + node _T_4593 = eq(buf_dual[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 537:122] + node _T_4594 = eq(buf_dualhi[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 537:137] + node _T_4595 = or(_T_4593, _T_4594) @[lsu_bus_buffer.scala 537:135] + node _T_4596 = and(_T_4592, _T_4595) @[lsu_bus_buffer.scala 537:119] + node _T_4597 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 537:92] + node _T_4598 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 537:115] + node _T_4599 = eq(_T_4598, UInt<1>("h00")) @[lsu_bus_buffer.scala 537:105] + node _T_4600 = and(_T_4597, _T_4599) @[lsu_bus_buffer.scala 537:103] + node _T_4601 = eq(buf_dual[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 537:122] + node _T_4602 = eq(buf_dualhi[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 537:137] + node _T_4603 = or(_T_4601, _T_4602) @[lsu_bus_buffer.scala 537:135] + node _T_4604 = and(_T_4600, _T_4603) @[lsu_bus_buffer.scala 537:119] + node _T_4605 = mux(_T_4580, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4606 = mux(_T_4588, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4607 = mux(_T_4596, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4608 = mux(_T_4604, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4609 = or(_T_4605, _T_4606) @[Mux.scala 27:72] + node _T_4610 = or(_T_4609, _T_4607) @[Mux.scala 27:72] + node _T_4611 = or(_T_4610, _T_4608) @[Mux.scala 27:72] + wire _T_4612 : UInt<2> @[Mux.scala 27:72] + _T_4612 <= _T_4611 @[Mux.scala 27:72] + io.dctl_busbuff.lsu_nonblock_load_data_tag <= _T_4612 @[lsu_bus_buffer.scala 537:46] + node _T_4613 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 538:78] + node _T_4614 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 538:101] + node _T_4615 = eq(_T_4614, UInt<1>("h00")) @[lsu_bus_buffer.scala 538:91] + node _T_4616 = and(_T_4613, _T_4615) @[lsu_bus_buffer.scala 538:89] + node _T_4617 = eq(buf_dual[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 538:108] + node _T_4618 = eq(buf_dualhi[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 538:123] + node _T_4619 = or(_T_4617, _T_4618) @[lsu_bus_buffer.scala 538:121] + node _T_4620 = and(_T_4616, _T_4619) @[lsu_bus_buffer.scala 538:105] + node _T_4621 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 538:78] + node _T_4622 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 538:101] + node _T_4623 = eq(_T_4622, UInt<1>("h00")) @[lsu_bus_buffer.scala 538:91] + node _T_4624 = and(_T_4621, _T_4623) @[lsu_bus_buffer.scala 538:89] + node _T_4625 = eq(buf_dual[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 538:108] + node _T_4626 = eq(buf_dualhi[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 538:123] + node _T_4627 = or(_T_4625, _T_4626) @[lsu_bus_buffer.scala 538:121] + node _T_4628 = and(_T_4624, _T_4627) @[lsu_bus_buffer.scala 538:105] + node _T_4629 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 538:78] + node _T_4630 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 538:101] + node _T_4631 = eq(_T_4630, UInt<1>("h00")) @[lsu_bus_buffer.scala 538:91] + node _T_4632 = and(_T_4629, _T_4631) @[lsu_bus_buffer.scala 538:89] + node _T_4633 = eq(buf_dual[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 538:108] + node _T_4634 = eq(buf_dualhi[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 538:123] + node _T_4635 = or(_T_4633, _T_4634) @[lsu_bus_buffer.scala 538:121] + node _T_4636 = and(_T_4632, _T_4635) @[lsu_bus_buffer.scala 538:105] + node _T_4637 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 538:78] + node _T_4638 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 538:101] + node _T_4639 = eq(_T_4638, UInt<1>("h00")) @[lsu_bus_buffer.scala 538:91] + node _T_4640 = and(_T_4637, _T_4639) @[lsu_bus_buffer.scala 538:89] + node _T_4641 = eq(buf_dual[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 538:108] + node _T_4642 = eq(buf_dualhi[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 538:123] + node _T_4643 = or(_T_4641, _T_4642) @[lsu_bus_buffer.scala 538:121] + node _T_4644 = and(_T_4640, _T_4643) @[lsu_bus_buffer.scala 538:105] + node _T_4645 = mux(_T_4620, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4646 = mux(_T_4628, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4647 = mux(_T_4636, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4648 = mux(_T_4644, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4649 = or(_T_4645, _T_4646) @[Mux.scala 27:72] + node _T_4650 = or(_T_4649, _T_4647) @[Mux.scala 27:72] + node _T_4651 = or(_T_4650, _T_4648) @[Mux.scala 27:72] + wire lsu_nonblock_load_data_lo : UInt<32> @[Mux.scala 27:72] + lsu_nonblock_load_data_lo <= _T_4651 @[Mux.scala 27:72] + node _T_4652 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 539:78] + node _T_4653 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 539:101] + node _T_4654 = eq(_T_4653, UInt<1>("h00")) @[lsu_bus_buffer.scala 539:91] + node _T_4655 = and(_T_4652, _T_4654) @[lsu_bus_buffer.scala 539:89] + node _T_4656 = and(buf_dual[0], buf_dualhi[0]) @[lsu_bus_buffer.scala 539:120] + node _T_4657 = and(_T_4655, _T_4656) @[lsu_bus_buffer.scala 539:105] + node _T_4658 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 539:78] + node _T_4659 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 539:101] + node _T_4660 = eq(_T_4659, UInt<1>("h00")) @[lsu_bus_buffer.scala 539:91] + node _T_4661 = and(_T_4658, _T_4660) @[lsu_bus_buffer.scala 539:89] + node _T_4662 = and(buf_dual[1], buf_dualhi[1]) @[lsu_bus_buffer.scala 539:120] + node _T_4663 = and(_T_4661, _T_4662) @[lsu_bus_buffer.scala 539:105] + node _T_4664 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 539:78] + node _T_4665 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 539:101] + node _T_4666 = eq(_T_4665, UInt<1>("h00")) @[lsu_bus_buffer.scala 539:91] + node _T_4667 = and(_T_4664, _T_4666) @[lsu_bus_buffer.scala 539:89] + node _T_4668 = and(buf_dual[2], buf_dualhi[2]) @[lsu_bus_buffer.scala 539:120] + node _T_4669 = and(_T_4667, _T_4668) @[lsu_bus_buffer.scala 539:105] + node _T_4670 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 539:78] + node _T_4671 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 539:101] + node _T_4672 = eq(_T_4671, UInt<1>("h00")) @[lsu_bus_buffer.scala 539:91] + node _T_4673 = and(_T_4670, _T_4672) @[lsu_bus_buffer.scala 539:89] + node _T_4674 = and(buf_dual[3], buf_dualhi[3]) @[lsu_bus_buffer.scala 539:120] + node _T_4675 = and(_T_4673, _T_4674) @[lsu_bus_buffer.scala 539:105] + node _T_4676 = mux(_T_4657, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4677 = mux(_T_4663, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4678 = mux(_T_4669, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4679 = mux(_T_4675, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4680 = or(_T_4676, _T_4677) @[Mux.scala 27:72] + node _T_4681 = or(_T_4680, _T_4678) @[Mux.scala 27:72] + node _T_4682 = or(_T_4681, _T_4679) @[Mux.scala 27:72] + wire lsu_nonblock_load_data_hi : UInt<32> @[Mux.scala 27:72] + lsu_nonblock_load_data_hi <= _T_4682 @[Mux.scala 27:72] + node _T_4683 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_4684 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_4685 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_4686 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] + node _T_4687 = mux(_T_4683, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4688 = mux(_T_4684, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4689 = mux(_T_4685, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4690 = mux(_T_4686, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4691 = or(_T_4687, _T_4688) @[Mux.scala 27:72] + node _T_4692 = or(_T_4691, _T_4689) @[Mux.scala 27:72] + node _T_4693 = or(_T_4692, _T_4690) @[Mux.scala 27:72] + wire _T_4694 : UInt<32> @[Mux.scala 27:72] + _T_4694 <= _T_4693 @[Mux.scala 27:72] + node lsu_nonblock_addr_offset = bits(_T_4694, 1, 0) @[lsu_bus_buffer.scala 540:96] + node _T_4695 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_4696 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_4697 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_4698 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] + node _T_4699 = mux(_T_4695, buf_sz[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4700 = mux(_T_4696, buf_sz[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4701 = mux(_T_4697, buf_sz[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4702 = mux(_T_4698, buf_sz[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4703 = or(_T_4699, _T_4700) @[Mux.scala 27:72] + node _T_4704 = or(_T_4703, _T_4701) @[Mux.scala 27:72] + node _T_4705 = or(_T_4704, _T_4702) @[Mux.scala 27:72] + wire lsu_nonblock_sz : UInt<2> @[Mux.scala 27:72] + lsu_nonblock_sz <= _T_4705 @[Mux.scala 27:72] + node _T_4706 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_4707 = bits(buf_unsign, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_4708 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_4709 = bits(buf_unsign, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_4710 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_4711 = bits(buf_unsign, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_4712 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_4713 = bits(buf_unsign, 3, 3) @[lsu_bus_buffer.scala 57:129] + node _T_4714 = mux(_T_4706, _T_4707, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4715 = mux(_T_4708, _T_4709, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4716 = mux(_T_4710, _T_4711, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4717 = mux(_T_4712, _T_4713, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4718 = or(_T_4714, _T_4715) @[Mux.scala 27:72] + node _T_4719 = or(_T_4718, _T_4716) @[Mux.scala 27:72] + node _T_4720 = or(_T_4719, _T_4717) @[Mux.scala 27:72] + wire lsu_nonblock_unsign : UInt<1> @[Mux.scala 27:72] + lsu_nonblock_unsign <= _T_4720 @[Mux.scala 27:72] + node _T_4721 = cat(buf_dual[3], buf_dual[2]) @[Cat.scala 29:58] + node _T_4722 = cat(_T_4721, buf_dual[1]) @[Cat.scala 29:58] + node _T_4723 = cat(_T_4722, buf_dual[0]) @[Cat.scala 29:58] + node _T_4724 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_4725 = bits(_T_4723, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_4726 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_4727 = bits(_T_4723, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_4728 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_4729 = bits(_T_4723, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_4730 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_4731 = bits(_T_4723, 3, 3) @[lsu_bus_buffer.scala 57:129] + node _T_4732 = mux(_T_4724, _T_4725, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4733 = mux(_T_4726, _T_4727, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4734 = mux(_T_4728, _T_4729, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4735 = mux(_T_4730, _T_4731, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4736 = or(_T_4732, _T_4733) @[Mux.scala 27:72] + node _T_4737 = or(_T_4736, _T_4734) @[Mux.scala 27:72] + node _T_4738 = or(_T_4737, _T_4735) @[Mux.scala 27:72] + wire lsu_nonblock_dual : UInt<1> @[Mux.scala 27:72] + lsu_nonblock_dual <= _T_4738 @[Mux.scala 27:72] + node _T_4739 = cat(lsu_nonblock_load_data_hi, lsu_nonblock_load_data_lo) @[Cat.scala 29:58] + node _T_4740 = mul(lsu_nonblock_addr_offset, UInt<4>("h08")) @[lsu_bus_buffer.scala 544:121] + node lsu_nonblock_data_unalgn = dshr(_T_4739, _T_4740) @[lsu_bus_buffer.scala 544:92] + node _T_4741 = eq(io.dctl_busbuff.lsu_nonblock_load_data_error, UInt<1>("h00")) @[lsu_bus_buffer.scala 546:82] + node _T_4742 = and(lsu_nonblock_load_data_ready, _T_4741) @[lsu_bus_buffer.scala 546:80] + io.dctl_busbuff.lsu_nonblock_load_data_valid <= _T_4742 @[lsu_bus_buffer.scala 546:48] + node _T_4743 = eq(lsu_nonblock_sz, UInt<1>("h00")) @[lsu_bus_buffer.scala 547:94] + node _T_4744 = and(lsu_nonblock_unsign, _T_4743) @[lsu_bus_buffer.scala 547:76] + node _T_4745 = bits(lsu_nonblock_data_unalgn, 7, 0) @[lsu_bus_buffer.scala 547:144] + node _T_4746 = cat(UInt<24>("h00"), _T_4745) @[Cat.scala 29:58] + node _T_4747 = eq(lsu_nonblock_sz, UInt<1>("h01")) @[lsu_bus_buffer.scala 548:45] + node _T_4748 = and(lsu_nonblock_unsign, _T_4747) @[lsu_bus_buffer.scala 548:26] + node _T_4749 = bits(lsu_nonblock_data_unalgn, 15, 0) @[lsu_bus_buffer.scala 548:95] + node _T_4750 = cat(UInt<16>("h00"), _T_4749) @[Cat.scala 29:58] + node _T_4751 = eq(lsu_nonblock_unsign, UInt<1>("h00")) @[lsu_bus_buffer.scala 549:6] + node _T_4752 = eq(lsu_nonblock_sz, UInt<1>("h00")) @[lsu_bus_buffer.scala 549:45] + node _T_4753 = and(_T_4751, _T_4752) @[lsu_bus_buffer.scala 549:27] + node _T_4754 = bits(lsu_nonblock_data_unalgn, 7, 7) @[lsu_bus_buffer.scala 549:93] + node _T_4755 = bits(_T_4754, 0, 0) @[Bitwise.scala 72:15] + node _T_4756 = mux(_T_4755, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12] + node _T_4757 = bits(lsu_nonblock_data_unalgn, 7, 0) @[lsu_bus_buffer.scala 549:123] + node _T_4758 = cat(_T_4756, _T_4757) @[Cat.scala 29:58] + node _T_4759 = eq(lsu_nonblock_unsign, UInt<1>("h00")) @[lsu_bus_buffer.scala 550:6] + node _T_4760 = eq(lsu_nonblock_sz, UInt<1>("h01")) @[lsu_bus_buffer.scala 550:45] + node _T_4761 = and(_T_4759, _T_4760) @[lsu_bus_buffer.scala 550:27] + node _T_4762 = bits(lsu_nonblock_data_unalgn, 15, 15) @[lsu_bus_buffer.scala 550:93] + node _T_4763 = bits(_T_4762, 0, 0) @[Bitwise.scala 72:15] + node _T_4764 = mux(_T_4763, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] + node _T_4765 = bits(lsu_nonblock_data_unalgn, 15, 0) @[lsu_bus_buffer.scala 550:124] + node _T_4766 = cat(_T_4764, _T_4765) @[Cat.scala 29:58] + node _T_4767 = eq(lsu_nonblock_sz, UInt<2>("h02")) @[lsu_bus_buffer.scala 551:21] + node _T_4768 = mux(_T_4744, _T_4746, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4769 = mux(_T_4748, _T_4750, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4770 = mux(_T_4753, _T_4758, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4771 = mux(_T_4761, _T_4766, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4772 = mux(_T_4767, lsu_nonblock_data_unalgn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4773 = or(_T_4768, _T_4769) @[Mux.scala 27:72] + node _T_4774 = or(_T_4773, _T_4770) @[Mux.scala 27:72] + node _T_4775 = or(_T_4774, _T_4771) @[Mux.scala 27:72] + node _T_4776 = or(_T_4775, _T_4772) @[Mux.scala 27:72] + wire _T_4777 : UInt<64> @[Mux.scala 27:72] + _T_4777 <= _T_4776 @[Mux.scala 27:72] + io.dctl_busbuff.lsu_nonblock_load_data <= _T_4777 @[lsu_bus_buffer.scala 547:42] + node _T_4778 = eq(buf_state[0], UInt<3>("h03")) @[lsu_bus_buffer.scala 552:62] + node _T_4779 = bits(buf_sideeffect, 0, 0) @[lsu_bus_buffer.scala 552:89] + node _T_4780 = and(_T_4778, _T_4779) @[lsu_bus_buffer.scala 552:73] + node _T_4781 = and(_T_4780, io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) @[lsu_bus_buffer.scala 552:93] + node _T_4782 = eq(buf_state[1], UInt<3>("h03")) @[lsu_bus_buffer.scala 552:62] + node _T_4783 = bits(buf_sideeffect, 1, 1) @[lsu_bus_buffer.scala 552:89] + node _T_4784 = and(_T_4782, _T_4783) @[lsu_bus_buffer.scala 552:73] + node _T_4785 = and(_T_4784, io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) @[lsu_bus_buffer.scala 552:93] + node _T_4786 = eq(buf_state[2], UInt<3>("h03")) @[lsu_bus_buffer.scala 552:62] + node _T_4787 = bits(buf_sideeffect, 2, 2) @[lsu_bus_buffer.scala 552:89] + node _T_4788 = and(_T_4786, _T_4787) @[lsu_bus_buffer.scala 552:73] + node _T_4789 = and(_T_4788, io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) @[lsu_bus_buffer.scala 552:93] + node _T_4790 = eq(buf_state[3], UInt<3>("h03")) @[lsu_bus_buffer.scala 552:62] + node _T_4791 = bits(buf_sideeffect, 3, 3) @[lsu_bus_buffer.scala 552:89] + node _T_4792 = and(_T_4790, _T_4791) @[lsu_bus_buffer.scala 552:73] + node _T_4793 = and(_T_4792, io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) @[lsu_bus_buffer.scala 552:93] + node _T_4794 = or(_T_4781, _T_4785) @[lsu_bus_buffer.scala 552:153] + node _T_4795 = or(_T_4794, _T_4789) @[lsu_bus_buffer.scala 552:153] + node _T_4796 = or(_T_4795, _T_4793) @[lsu_bus_buffer.scala 552:153] + node _T_4797 = and(obuf_valid, obuf_sideeffect) @[lsu_bus_buffer.scala 552:171] + node _T_4798 = and(_T_4797, io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) @[lsu_bus_buffer.scala 552:189] + node _T_4799 = or(_T_4796, _T_4798) @[lsu_bus_buffer.scala 552:157] + bus_sideeffect_pend <= _T_4799 @[lsu_bus_buffer.scala 552:23] + node _T_4800 = eq(buf_state[0], UInt<3>("h03")) @[lsu_bus_buffer.scala 553:71] + node _T_4801 = and(UInt<1>("h01"), obuf_valid) @[lsu_bus_buffer.scala 554:25] + node _T_4802 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 554:50] + node _T_4803 = bits(buf_addr[0], 31, 3) @[lsu_bus_buffer.scala 554:70] + node _T_4804 = eq(_T_4802, _T_4803) @[lsu_bus_buffer.scala 554:56] + node _T_4805 = and(_T_4801, _T_4804) @[lsu_bus_buffer.scala 554:38] + node _T_4806 = eq(obuf_tag0, UInt<1>("h00")) @[lsu_bus_buffer.scala 554:92] + node _T_4807 = eq(obuf_tag1, UInt<1>("h00")) @[lsu_bus_buffer.scala 554:126] + node _T_4808 = and(obuf_merge, _T_4807) @[lsu_bus_buffer.scala 554:114] + node _T_4809 = or(_T_4806, _T_4808) @[lsu_bus_buffer.scala 554:100] + node _T_4810 = eq(_T_4809, UInt<1>("h00")) @[lsu_bus_buffer.scala 554:80] + node _T_4811 = and(_T_4805, _T_4810) @[lsu_bus_buffer.scala 554:78] + node _T_4812 = eq(buf_state[1], UInt<3>("h03")) @[lsu_bus_buffer.scala 553:71] + node _T_4813 = and(UInt<1>("h01"), obuf_valid) @[lsu_bus_buffer.scala 554:25] + node _T_4814 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 554:50] + node _T_4815 = bits(buf_addr[1], 31, 3) @[lsu_bus_buffer.scala 554:70] + node _T_4816 = eq(_T_4814, _T_4815) @[lsu_bus_buffer.scala 554:56] + node _T_4817 = and(_T_4813, _T_4816) @[lsu_bus_buffer.scala 554:38] + node _T_4818 = eq(obuf_tag0, UInt<1>("h01")) @[lsu_bus_buffer.scala 554:92] + node _T_4819 = eq(obuf_tag1, UInt<1>("h01")) @[lsu_bus_buffer.scala 554:126] + node _T_4820 = and(obuf_merge, _T_4819) @[lsu_bus_buffer.scala 554:114] + node _T_4821 = or(_T_4818, _T_4820) @[lsu_bus_buffer.scala 554:100] + node _T_4822 = eq(_T_4821, UInt<1>("h00")) @[lsu_bus_buffer.scala 554:80] + node _T_4823 = and(_T_4817, _T_4822) @[lsu_bus_buffer.scala 554:78] + node _T_4824 = eq(buf_state[2], UInt<3>("h03")) @[lsu_bus_buffer.scala 553:71] + node _T_4825 = and(UInt<1>("h01"), obuf_valid) @[lsu_bus_buffer.scala 554:25] + node _T_4826 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 554:50] + node _T_4827 = bits(buf_addr[2], 31, 3) @[lsu_bus_buffer.scala 554:70] + node _T_4828 = eq(_T_4826, _T_4827) @[lsu_bus_buffer.scala 554:56] + node _T_4829 = and(_T_4825, _T_4828) @[lsu_bus_buffer.scala 554:38] + node _T_4830 = eq(obuf_tag0, UInt<2>("h02")) @[lsu_bus_buffer.scala 554:92] + node _T_4831 = eq(obuf_tag1, UInt<2>("h02")) @[lsu_bus_buffer.scala 554:126] + node _T_4832 = and(obuf_merge, _T_4831) @[lsu_bus_buffer.scala 554:114] + node _T_4833 = or(_T_4830, _T_4832) @[lsu_bus_buffer.scala 554:100] + node _T_4834 = eq(_T_4833, UInt<1>("h00")) @[lsu_bus_buffer.scala 554:80] + node _T_4835 = and(_T_4829, _T_4834) @[lsu_bus_buffer.scala 554:78] + node _T_4836 = eq(buf_state[3], UInt<3>("h03")) @[lsu_bus_buffer.scala 553:71] + node _T_4837 = and(UInt<1>("h01"), obuf_valid) @[lsu_bus_buffer.scala 554:25] + node _T_4838 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 554:50] + node _T_4839 = bits(buf_addr[3], 31, 3) @[lsu_bus_buffer.scala 554:70] + node _T_4840 = eq(_T_4838, _T_4839) @[lsu_bus_buffer.scala 554:56] + node _T_4841 = and(_T_4837, _T_4840) @[lsu_bus_buffer.scala 554:38] + node _T_4842 = eq(obuf_tag0, UInt<2>("h03")) @[lsu_bus_buffer.scala 554:92] + node _T_4843 = eq(obuf_tag1, UInt<2>("h03")) @[lsu_bus_buffer.scala 554:126] + node _T_4844 = and(obuf_merge, _T_4843) @[lsu_bus_buffer.scala 554:114] + node _T_4845 = or(_T_4842, _T_4844) @[lsu_bus_buffer.scala 554:100] + node _T_4846 = eq(_T_4845, UInt<1>("h00")) @[lsu_bus_buffer.scala 554:80] + node _T_4847 = and(_T_4841, _T_4846) @[lsu_bus_buffer.scala 554:78] + node _T_4848 = mux(_T_4800, _T_4811, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4849 = mux(_T_4812, _T_4823, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4850 = mux(_T_4824, _T_4835, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4851 = mux(_T_4836, _T_4847, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4852 = or(_T_4848, _T_4849) @[Mux.scala 27:72] + node _T_4853 = or(_T_4852, _T_4850) @[Mux.scala 27:72] + node _T_4854 = or(_T_4853, _T_4851) @[Mux.scala 27:72] + wire _T_4855 : UInt<1> @[Mux.scala 27:72] + _T_4855 <= _T_4854 @[Mux.scala 27:72] + bus_addr_match_pending <= _T_4855 @[lsu_bus_buffer.scala 553:26] + node _T_4856 = or(obuf_cmd_done, obuf_data_done) @[lsu_bus_buffer.scala 556:54] + node _T_4857 = mux(obuf_cmd_done, io.lsu_axi.w.ready, io.lsu_axi.aw.ready) @[lsu_bus_buffer.scala 556:75] + node _T_4858 = and(io.lsu_axi.aw.ready, io.lsu_axi.w.ready) @[lsu_bus_buffer.scala 556:153] + node _T_4859 = mux(_T_4856, _T_4857, _T_4858) @[lsu_bus_buffer.scala 556:39] + node _T_4860 = mux(obuf_write, _T_4859, io.lsu_axi.ar.ready) @[lsu_bus_buffer.scala 556:23] + bus_cmd_ready <= _T_4860 @[lsu_bus_buffer.scala 556:17] + node _T_4861 = and(io.lsu_axi.aw.valid, io.lsu_axi.aw.ready) @[lsu_bus_buffer.scala 557:40] + bus_wcmd_sent <= _T_4861 @[lsu_bus_buffer.scala 557:17] + node _T_4862 = and(io.lsu_axi.w.valid, io.lsu_axi.w.ready) @[lsu_bus_buffer.scala 558:40] + bus_wdata_sent <= _T_4862 @[lsu_bus_buffer.scala 558:18] + node _T_4863 = or(obuf_cmd_done, bus_wcmd_sent) @[lsu_bus_buffer.scala 559:35] + node _T_4864 = or(obuf_data_done, bus_wdata_sent) @[lsu_bus_buffer.scala 559:70] + node _T_4865 = and(_T_4863, _T_4864) @[lsu_bus_buffer.scala 559:52] + node _T_4866 = and(io.lsu_axi.ar.valid, io.lsu_axi.ar.ready) @[lsu_bus_buffer.scala 559:112] + node _T_4867 = or(_T_4865, _T_4866) @[lsu_bus_buffer.scala 559:89] + bus_cmd_sent <= _T_4867 @[lsu_bus_buffer.scala 559:16] + node _T_4868 = and(io.lsu_axi.r.valid, io.lsu_axi.r.ready) @[lsu_bus_buffer.scala 560:38] + bus_rsp_read <= _T_4868 @[lsu_bus_buffer.scala 560:16] + node _T_4869 = and(io.lsu_axi.b.valid, io.lsu_axi.b.ready) @[lsu_bus_buffer.scala 561:39] + bus_rsp_write <= _T_4869 @[lsu_bus_buffer.scala 561:17] + bus_rsp_read_tag <= io.lsu_axi.r.bits.id @[lsu_bus_buffer.scala 562:20] + bus_rsp_write_tag <= io.lsu_axi.b.bits.id @[lsu_bus_buffer.scala 563:21] + node _T_4870 = neq(io.lsu_axi.b.bits.resp, UInt<1>("h00")) @[lsu_bus_buffer.scala 564:66] + node _T_4871 = and(bus_rsp_write, _T_4870) @[lsu_bus_buffer.scala 564:40] + bus_rsp_write_error <= _T_4871 @[lsu_bus_buffer.scala 564:23] + node _T_4872 = neq(io.lsu_axi.r.bits.resp, UInt<1>("h00")) @[lsu_bus_buffer.scala 565:64] + node _T_4873 = and(bus_rsp_read, _T_4872) @[lsu_bus_buffer.scala 565:38] + bus_rsp_read_error <= _T_4873 @[lsu_bus_buffer.scala 565:22] + bus_rsp_rdata <= io.lsu_axi.r.bits.data @[lsu_bus_buffer.scala 566:17] + node _T_4874 = and(obuf_valid, obuf_write) @[lsu_bus_buffer.scala 569:37] + node _T_4875 = eq(obuf_cmd_done, UInt<1>("h00")) @[lsu_bus_buffer.scala 569:52] + node _T_4876 = and(_T_4874, _T_4875) @[lsu_bus_buffer.scala 569:50] + node _T_4877 = eq(bus_addr_match_pending, UInt<1>("h00")) @[lsu_bus_buffer.scala 569:69] + node _T_4878 = and(_T_4876, _T_4877) @[lsu_bus_buffer.scala 569:67] + io.lsu_axi.aw.valid <= _T_4878 @[lsu_bus_buffer.scala 569:23] + io.lsu_axi.aw.bits.id <= obuf_tag0 @[lsu_bus_buffer.scala 570:25] + node _T_4879 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 571:75] + node _T_4880 = cat(_T_4879, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_4881 = mux(obuf_sideeffect, obuf_addr, _T_4880) @[lsu_bus_buffer.scala 571:33] + io.lsu_axi.aw.bits.addr <= _T_4881 @[lsu_bus_buffer.scala 571:27] + node _T_4882 = cat(UInt<1>("h00"), obuf_sz) @[Cat.scala 29:58] + node _T_4883 = mux(obuf_sideeffect, _T_4882, UInt<3>("h03")) @[lsu_bus_buffer.scala 572:33] + io.lsu_axi.aw.bits.size <= _T_4883 @[lsu_bus_buffer.scala 572:27] + io.lsu_axi.aw.bits.prot <= UInt<1>("h00") @[lsu_bus_buffer.scala 573:27] + node _T_4884 = mux(obuf_sideeffect, UInt<1>("h00"), UInt<4>("h0f")) @[lsu_bus_buffer.scala 574:34] + io.lsu_axi.aw.bits.cache <= _T_4884 @[lsu_bus_buffer.scala 574:28] + node _T_4885 = bits(obuf_addr, 31, 28) @[lsu_bus_buffer.scala 575:41] + io.lsu_axi.aw.bits.region <= _T_4885 @[lsu_bus_buffer.scala 575:29] + io.lsu_axi.aw.bits.len <= UInt<1>("h00") @[lsu_bus_buffer.scala 576:26] + io.lsu_axi.aw.bits.burst <= UInt<2>("h01") @[lsu_bus_buffer.scala 577:28] + io.lsu_axi.aw.bits.qos <= UInt<1>("h00") @[lsu_bus_buffer.scala 578:26] + io.lsu_axi.aw.bits.lock <= UInt<1>("h00") @[lsu_bus_buffer.scala 579:27] + node _T_4886 = and(obuf_valid, obuf_write) @[lsu_bus_buffer.scala 581:36] + node _T_4887 = eq(obuf_data_done, UInt<1>("h00")) @[lsu_bus_buffer.scala 581:51] + node _T_4888 = and(_T_4886, _T_4887) @[lsu_bus_buffer.scala 581:49] + node _T_4889 = eq(bus_addr_match_pending, UInt<1>("h00")) @[lsu_bus_buffer.scala 581:69] + node _T_4890 = and(_T_4888, _T_4889) @[lsu_bus_buffer.scala 581:67] + io.lsu_axi.w.valid <= _T_4890 @[lsu_bus_buffer.scala 581:22] + node _T_4891 = bits(obuf_write, 0, 0) @[Bitwise.scala 72:15] + node _T_4892 = mux(_T_4891, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_4893 = and(obuf_byteen, _T_4892) @[lsu_bus_buffer.scala 582:41] + io.lsu_axi.w.bits.strb <= _T_4893 @[lsu_bus_buffer.scala 582:26] + io.lsu_axi.w.bits.data <= obuf_data @[lsu_bus_buffer.scala 583:26] + io.lsu_axi.w.bits.last <= UInt<1>("h01") @[lsu_bus_buffer.scala 584:26] + node _T_4894 = eq(obuf_write, UInt<1>("h00")) @[lsu_bus_buffer.scala 586:39] + node _T_4895 = and(obuf_valid, _T_4894) @[lsu_bus_buffer.scala 586:37] + node _T_4896 = eq(obuf_nosend, UInt<1>("h00")) @[lsu_bus_buffer.scala 586:53] + node _T_4897 = and(_T_4895, _T_4896) @[lsu_bus_buffer.scala 586:51] + node _T_4898 = eq(bus_addr_match_pending, UInt<1>("h00")) @[lsu_bus_buffer.scala 586:68] + node _T_4899 = and(_T_4897, _T_4898) @[lsu_bus_buffer.scala 586:66] + io.lsu_axi.ar.valid <= _T_4899 @[lsu_bus_buffer.scala 586:23] + io.lsu_axi.ar.bits.id <= obuf_tag0 @[lsu_bus_buffer.scala 587:25] + node _T_4900 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 588:75] + node _T_4901 = cat(_T_4900, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_4902 = mux(obuf_sideeffect, obuf_addr, _T_4901) @[lsu_bus_buffer.scala 588:33] + io.lsu_axi.ar.bits.addr <= _T_4902 @[lsu_bus_buffer.scala 588:27] + node _T_4903 = cat(UInt<1>("h00"), obuf_sz) @[Cat.scala 29:58] + node _T_4904 = mux(obuf_sideeffect, _T_4903, UInt<3>("h03")) @[lsu_bus_buffer.scala 589:33] + io.lsu_axi.ar.bits.size <= _T_4904 @[lsu_bus_buffer.scala 589:27] + io.lsu_axi.ar.bits.prot <= UInt<1>("h00") @[lsu_bus_buffer.scala 590:27] + node _T_4905 = mux(obuf_sideeffect, UInt<4>("h00"), UInt<4>("h0f")) @[lsu_bus_buffer.scala 591:34] + io.lsu_axi.ar.bits.cache <= _T_4905 @[lsu_bus_buffer.scala 591:28] + node _T_4906 = bits(obuf_addr, 31, 28) @[lsu_bus_buffer.scala 592:41] + io.lsu_axi.ar.bits.region <= _T_4906 @[lsu_bus_buffer.scala 592:29] + io.lsu_axi.ar.bits.len <= UInt<1>("h00") @[lsu_bus_buffer.scala 593:26] + io.lsu_axi.ar.bits.burst <= UInt<2>("h01") @[lsu_bus_buffer.scala 594:28] + io.lsu_axi.ar.bits.qos <= UInt<1>("h00") @[lsu_bus_buffer.scala 595:26] + io.lsu_axi.ar.bits.lock <= UInt<1>("h00") @[lsu_bus_buffer.scala 596:27] + io.lsu_axi.b.ready <= UInt<1>("h01") @[lsu_bus_buffer.scala 597:22] + io.lsu_axi.r.ready <= UInt<1>("h01") @[lsu_bus_buffer.scala 598:22] + node _T_4907 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 599:93] + node _T_4908 = bits(buf_error, 0, 0) @[lsu_bus_buffer.scala 599:137] + node _T_4909 = and(io.lsu_bus_clk_en_q, _T_4908) @[lsu_bus_buffer.scala 599:126] + node _T_4910 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 599:152] + node _T_4911 = and(_T_4909, _T_4910) @[lsu_bus_buffer.scala 599:141] + node _T_4912 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 599:93] + node _T_4913 = bits(buf_error, 1, 1) @[lsu_bus_buffer.scala 599:137] + node _T_4914 = and(io.lsu_bus_clk_en_q, _T_4913) @[lsu_bus_buffer.scala 599:126] + node _T_4915 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 599:152] + node _T_4916 = and(_T_4914, _T_4915) @[lsu_bus_buffer.scala 599:141] + node _T_4917 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 599:93] + node _T_4918 = bits(buf_error, 2, 2) @[lsu_bus_buffer.scala 599:137] + node _T_4919 = and(io.lsu_bus_clk_en_q, _T_4918) @[lsu_bus_buffer.scala 599:126] + node _T_4920 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 599:152] + node _T_4921 = and(_T_4919, _T_4920) @[lsu_bus_buffer.scala 599:141] + node _T_4922 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 599:93] + node _T_4923 = bits(buf_error, 3, 3) @[lsu_bus_buffer.scala 599:137] + node _T_4924 = and(io.lsu_bus_clk_en_q, _T_4923) @[lsu_bus_buffer.scala 599:126] + node _T_4925 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 599:152] + node _T_4926 = and(_T_4924, _T_4925) @[lsu_bus_buffer.scala 599:141] + node _T_4927 = mux(_T_4907, _T_4911, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4928 = mux(_T_4912, _T_4916, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4929 = mux(_T_4917, _T_4921, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4930 = mux(_T_4922, _T_4926, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4931 = or(_T_4927, _T_4928) @[Mux.scala 27:72] + node _T_4932 = or(_T_4931, _T_4929) @[Mux.scala 27:72] + node _T_4933 = or(_T_4932, _T_4930) @[Mux.scala 27:72] + wire _T_4934 : UInt<1> @[Mux.scala 27:72] + _T_4934 <= _T_4933 @[Mux.scala 27:72] + io.tlu_busbuff.lsu_imprecise_error_store_any <= _T_4934 @[lsu_bus_buffer.scala 599:48] + node _T_4935 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 600:82] + node _T_4936 = bits(buf_error, 0, 0) @[lsu_bus_buffer.scala 600:104] + node _T_4937 = and(_T_4935, _T_4936) @[lsu_bus_buffer.scala 600:93] + node _T_4938 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 600:119] + node _T_4939 = and(_T_4937, _T_4938) @[lsu_bus_buffer.scala 600:108] + node _T_4940 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 600:82] + node _T_4941 = bits(buf_error, 1, 1) @[lsu_bus_buffer.scala 600:104] + node _T_4942 = and(_T_4940, _T_4941) @[lsu_bus_buffer.scala 600:93] + node _T_4943 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 600:119] + node _T_4944 = and(_T_4942, _T_4943) @[lsu_bus_buffer.scala 600:108] + node _T_4945 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 600:82] + node _T_4946 = bits(buf_error, 2, 2) @[lsu_bus_buffer.scala 600:104] + node _T_4947 = and(_T_4945, _T_4946) @[lsu_bus_buffer.scala 600:93] + node _T_4948 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 600:119] + node _T_4949 = and(_T_4947, _T_4948) @[lsu_bus_buffer.scala 600:108] + node _T_4950 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 600:82] + node _T_4951 = bits(buf_error, 3, 3) @[lsu_bus_buffer.scala 600:104] + node _T_4952 = and(_T_4950, _T_4951) @[lsu_bus_buffer.scala 600:93] + node _T_4953 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 600:119] + node _T_4954 = and(_T_4952, _T_4953) @[lsu_bus_buffer.scala 600:108] + node _T_4955 = mux(_T_4939, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4956 = mux(_T_4944, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4957 = mux(_T_4949, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4958 = mux(_T_4954, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4959 = or(_T_4955, _T_4956) @[Mux.scala 27:72] + node _T_4960 = or(_T_4959, _T_4957) @[Mux.scala 27:72] + node _T_4961 = or(_T_4960, _T_4958) @[Mux.scala 27:72] + wire lsu_imprecise_error_store_tag : UInt<2> @[Mux.scala 27:72] + lsu_imprecise_error_store_tag <= _T_4961 @[Mux.scala 27:72] + node _T_4962 = eq(io.tlu_busbuff.lsu_imprecise_error_store_any, UInt<1>("h00")) @[lsu_bus_buffer.scala 602:97] + node _T_4963 = and(io.dctl_busbuff.lsu_nonblock_load_data_error, _T_4962) @[lsu_bus_buffer.scala 602:95] + io.tlu_busbuff.lsu_imprecise_error_load_any <= _T_4963 @[lsu_bus_buffer.scala 602:47] + node _T_4964 = mux(io.tlu_busbuff.lsu_imprecise_error_store_any, buf_addr[lsu_imprecise_error_store_tag], buf_addr[io.dctl_busbuff.lsu_nonblock_load_data_tag]) @[lsu_bus_buffer.scala 603:53] + io.tlu_busbuff.lsu_imprecise_error_addr_any <= _T_4964 @[lsu_bus_buffer.scala 603:47] + lsu_bus_cntr_overflow <= UInt<1>("h00") @[lsu_bus_buffer.scala 604:25] + io.lsu_bus_idle_any <= UInt<1>("h01") @[lsu_bus_buffer.scala 606:23] + node _T_4965 = and(io.lsu_axi.aw.valid, io.lsu_axi.aw.ready) @[lsu_bus_buffer.scala 609:59] + node _T_4966 = and(io.lsu_axi.w.valid, io.lsu_axi.w.ready) @[lsu_bus_buffer.scala 609:104] + node _T_4967 = or(_T_4965, _T_4966) @[lsu_bus_buffer.scala 609:82] + node _T_4968 = and(io.lsu_axi.ar.valid, io.lsu_axi.ar.ready) @[lsu_bus_buffer.scala 609:149] + node _T_4969 = or(_T_4967, _T_4968) @[lsu_bus_buffer.scala 609:126] + io.tlu_busbuff.lsu_pmu_bus_trxn <= _T_4969 @[lsu_bus_buffer.scala 609:35] + node _T_4970 = and(io.lsu_busreq_r, io.ldst_dual_r) @[lsu_bus_buffer.scala 610:60] + node _T_4971 = and(_T_4970, io.lsu_commit_r) @[lsu_bus_buffer.scala 610:77] + io.tlu_busbuff.lsu_pmu_bus_misaligned <= _T_4971 @[lsu_bus_buffer.scala 610:41] + node _T_4972 = or(io.tlu_busbuff.lsu_imprecise_error_load_any, io.tlu_busbuff.lsu_imprecise_error_store_any) @[lsu_bus_buffer.scala 611:83] + io.tlu_busbuff.lsu_pmu_bus_error <= _T_4972 @[lsu_bus_buffer.scala 611:36] + node _T_4973 = eq(io.lsu_axi.aw.ready, UInt<1>("h00")) @[lsu_bus_buffer.scala 613:61] + node _T_4974 = and(io.lsu_axi.aw.valid, _T_4973) @[lsu_bus_buffer.scala 613:59] + node _T_4975 = eq(io.lsu_axi.w.ready, UInt<1>("h00")) @[lsu_bus_buffer.scala 613:107] + node _T_4976 = and(io.lsu_axi.w.valid, _T_4975) @[lsu_bus_buffer.scala 613:105] + node _T_4977 = or(_T_4974, _T_4976) @[lsu_bus_buffer.scala 613:83] + node _T_4978 = eq(io.lsu_axi.ar.ready, UInt<1>("h00")) @[lsu_bus_buffer.scala 613:153] + node _T_4979 = and(io.lsu_axi.ar.valid, _T_4978) @[lsu_bus_buffer.scala 613:151] + node _T_4980 = or(_T_4977, _T_4979) @[lsu_bus_buffer.scala 613:128] + io.tlu_busbuff.lsu_pmu_bus_busy <= _T_4980 @[lsu_bus_buffer.scala 613:35] + reg _T_4981 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 615:49] + _T_4981 <= WrPtr0_m @[lsu_bus_buffer.scala 615:49] + WrPtr0_r <= _T_4981 @[lsu_bus_buffer.scala 615:12] + reg _T_4982 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 616:49] + _T_4982 <= WrPtr1_m @[lsu_bus_buffer.scala 616:49] + WrPtr1_r <= _T_4982 @[lsu_bus_buffer.scala 616:12] + node _T_4983 = eq(io.flush_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 617:75] + node _T_4984 = and(io.lsu_busreq_m, _T_4983) @[lsu_bus_buffer.scala 617:73] + node _T_4985 = eq(io.ld_full_hit_m, UInt<1>("h00")) @[lsu_bus_buffer.scala 617:89] + node _T_4986 = and(_T_4984, _T_4985) @[lsu_bus_buffer.scala 617:87] + reg _T_4987 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 617:56] + _T_4987 <= _T_4986 @[lsu_bus_buffer.scala 617:56] + io.lsu_busreq_r <= _T_4987 @[lsu_bus_buffer.scala 617:19] + reg _T_4988 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 618:66] + _T_4988 <= io.dctl_busbuff.lsu_nonblock_load_valid_m @[lsu_bus_buffer.scala 618:66] + lsu_nonblock_load_valid_r <= _T_4988 @[lsu_bus_buffer.scala 618:29] + + module lsu_bus_intf : + input clock : Clock + input reset : AsyncReset + output io : {flip scan_mode : UInt<1>, tlu_busbuff : {lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>}, flip lsu_c1_m_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_bus_ibuf_c1_clk : Clock, flip lsu_bus_obuf_c1_clk : Clock, flip lsu_bus_buf_c1_clk : Clock, flip lsu_free_c2_clk : Clock, flip free_clk : Clock, flip lsu_busm_clk : Clock, axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dec_lsu_valid_raw_d : UInt<1>, flip lsu_busreq_m : UInt<1>, flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_addr_d : UInt<32>, flip lsu_addr_m : UInt<32>, flip lsu_addr_r : UInt<32>, flip end_addr_d : UInt<32>, flip end_addr_m : UInt<32>, flip end_addr_r : UInt<32>, flip store_data_r : UInt<32>, flip dec_tlu_force_halt : UInt<1>, flip lsu_commit_r : UInt<1>, flip is_sideeffects_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, lsu_busreq_r : UInt<1>, lsu_bus_buffer_pend_any : UInt<1>, lsu_bus_buffer_full_any : UInt<1>, lsu_bus_buffer_empty_any : UInt<1>, lsu_bus_idle_any : UInt<1>, bus_read_data_m : UInt<32>, dctl_busbuff : {lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>}, flip lsu_bus_clk_en : UInt<1>} + + wire lsu_bus_clk_en_q : UInt<1> + lsu_bus_clk_en_q <= UInt<1>("h00") + wire ldst_dual_d : UInt<1> + ldst_dual_d <= UInt<1>("h00") + wire ldst_dual_m : UInt<1> + ldst_dual_m <= UInt<1>("h00") + wire ldst_dual_r : UInt<1> + ldst_dual_r <= UInt<1>("h00") + wire ldst_byteen_m : UInt<4> + ldst_byteen_m <= UInt<1>("h00") + wire ldst_byteen_r : UInt<4> + ldst_byteen_r <= UInt<1>("h00") + wire ldst_byteen_ext_m : UInt<8> + ldst_byteen_ext_m <= UInt<1>("h00") + wire ldst_byteen_ext_r : UInt<8> + ldst_byteen_ext_r <= UInt<1>("h00") + wire ldst_byteen_hi_m : UInt<4> + ldst_byteen_hi_m <= UInt<1>("h00") + wire ldst_byteen_hi_r : UInt<4> + ldst_byteen_hi_r <= UInt<1>("h00") + wire ldst_byteen_lo_m : UInt<4> + ldst_byteen_lo_m <= UInt<1>("h00") + wire ldst_byteen_lo_r : UInt<4> + ldst_byteen_lo_r <= UInt<1>("h00") + wire is_sideeffects_r : UInt<1> + is_sideeffects_r <= UInt<1>("h00") + wire store_data_ext_r : UInt<64> + store_data_ext_r <= UInt<1>("h00") + wire store_data_hi_r : UInt<32> + store_data_hi_r <= UInt<1>("h00") + wire store_data_lo_r : UInt<32> + store_data_lo_r <= UInt<1>("h00") + wire addr_match_dw_lo_r_m : UInt<1> + addr_match_dw_lo_r_m <= UInt<1>("h00") + wire addr_match_word_lo_r_m : UInt<1> + addr_match_word_lo_r_m <= UInt<1>("h00") + wire no_word_merge_r : UInt<1> + no_word_merge_r <= UInt<1>("h00") + wire no_dword_merge_r : UInt<1> + no_dword_merge_r <= UInt<1>("h00") + wire ld_addr_rhit_lo_lo : UInt<1> + ld_addr_rhit_lo_lo <= UInt<1>("h00") + wire ld_addr_rhit_hi_lo : UInt<1> + ld_addr_rhit_hi_lo <= UInt<1>("h00") + wire ld_addr_rhit_lo_hi : UInt<1> + ld_addr_rhit_lo_hi <= UInt<1>("h00") + wire ld_addr_rhit_hi_hi : UInt<1> + ld_addr_rhit_hi_hi <= UInt<1>("h00") + wire ld_byte_rhit_lo_lo : UInt<4> + ld_byte_rhit_lo_lo <= UInt<1>("h00") + wire ld_byte_rhit_hi_lo : UInt<4> + ld_byte_rhit_hi_lo <= UInt<1>("h00") + wire ld_byte_rhit_lo_hi : UInt<4> + ld_byte_rhit_lo_hi <= UInt<1>("h00") + wire ld_byte_rhit_hi_hi : UInt<4> + ld_byte_rhit_hi_hi <= UInt<1>("h00") + wire ld_byte_hit_lo : UInt<4> + ld_byte_hit_lo <= UInt<1>("h00") + wire ld_byte_rhit_lo : UInt<4> + ld_byte_rhit_lo <= UInt<1>("h00") + wire ld_byte_hit_hi : UInt<4> + ld_byte_hit_hi <= UInt<1>("h00") + wire ld_byte_rhit_hi : UInt<4> + ld_byte_rhit_hi <= UInt<1>("h00") + wire ld_fwddata_rpipe_lo : UInt<32> + ld_fwddata_rpipe_lo <= UInt<1>("h00") + wire ld_fwddata_rpipe_hi : UInt<32> + ld_fwddata_rpipe_hi <= UInt<1>("h00") + wire ld_byte_hit_buf_lo : UInt<4> + ld_byte_hit_buf_lo <= UInt<1>("h00") + wire ld_byte_hit_buf_hi : UInt<4> + ld_byte_hit_buf_hi <= UInt<1>("h00") + wire ld_fwddata_buf_lo : UInt<32> + ld_fwddata_buf_lo <= UInt<1>("h00") + wire ld_fwddata_buf_hi : UInt<32> + ld_fwddata_buf_hi <= UInt<1>("h00") + wire ld_fwddata_lo : UInt<64> + ld_fwddata_lo <= UInt<1>("h00") + wire ld_fwddata_hi : UInt<64> + ld_fwddata_hi <= UInt<1>("h00") + wire ld_fwddata_m : UInt<64> + ld_fwddata_m <= UInt<1>("h00") + wire ld_full_hit_hi_m : UInt<1> + ld_full_hit_hi_m <= UInt<1>("h01") + wire ld_full_hit_lo_m : UInt<1> + ld_full_hit_lo_m <= UInt<1>("h01") + wire ld_full_hit_m : UInt<1> + ld_full_hit_m <= UInt<1>("h00") + inst bus_buffer of lsu_bus_buffer @[lsu_bus_intf.scala 100:39] + bus_buffer.clock <= clock + bus_buffer.reset <= reset + bus_buffer.io.scan_mode <= io.scan_mode @[lsu_bus_intf.scala 102:29] + io.tlu_busbuff.lsu_imprecise_error_addr_any <= bus_buffer.io.tlu_busbuff.lsu_imprecise_error_addr_any @[lsu_bus_intf.scala 103:18] + io.tlu_busbuff.lsu_imprecise_error_store_any <= bus_buffer.io.tlu_busbuff.lsu_imprecise_error_store_any @[lsu_bus_intf.scala 103:18] + io.tlu_busbuff.lsu_imprecise_error_load_any <= bus_buffer.io.tlu_busbuff.lsu_imprecise_error_load_any @[lsu_bus_intf.scala 103:18] + bus_buffer.io.tlu_busbuff.dec_tlu_sideeffect_posted_disable <= io.tlu_busbuff.dec_tlu_sideeffect_posted_disable @[lsu_bus_intf.scala 103:18] + bus_buffer.io.tlu_busbuff.dec_tlu_wb_coalescing_disable <= io.tlu_busbuff.dec_tlu_wb_coalescing_disable @[lsu_bus_intf.scala 103:18] + bus_buffer.io.tlu_busbuff.dec_tlu_external_ldfwd_disable <= io.tlu_busbuff.dec_tlu_external_ldfwd_disable @[lsu_bus_intf.scala 103:18] + io.tlu_busbuff.lsu_pmu_bus_busy <= bus_buffer.io.tlu_busbuff.lsu_pmu_bus_busy @[lsu_bus_intf.scala 103:18] + io.tlu_busbuff.lsu_pmu_bus_error <= bus_buffer.io.tlu_busbuff.lsu_pmu_bus_error @[lsu_bus_intf.scala 103:18] + io.tlu_busbuff.lsu_pmu_bus_misaligned <= bus_buffer.io.tlu_busbuff.lsu_pmu_bus_misaligned @[lsu_bus_intf.scala 103:18] + io.tlu_busbuff.lsu_pmu_bus_trxn <= bus_buffer.io.tlu_busbuff.lsu_pmu_bus_trxn @[lsu_bus_intf.scala 103:18] + bus_buffer.io.dec_tlu_force_halt <= io.dec_tlu_force_halt @[lsu_bus_intf.scala 105:51] + bus_buffer.io.lsu_c2_r_clk <= io.lsu_c2_r_clk @[lsu_bus_intf.scala 106:51] + bus_buffer.io.lsu_bus_ibuf_c1_clk <= io.lsu_bus_ibuf_c1_clk @[lsu_bus_intf.scala 107:51] + bus_buffer.io.lsu_bus_obuf_c1_clk <= io.lsu_bus_obuf_c1_clk @[lsu_bus_intf.scala 108:51] + bus_buffer.io.lsu_bus_buf_c1_clk <= io.lsu_bus_buf_c1_clk @[lsu_bus_intf.scala 109:51] + bus_buffer.io.lsu_free_c2_clk <= io.lsu_free_c2_clk @[lsu_bus_intf.scala 110:51] + bus_buffer.io.lsu_busm_clk <= io.lsu_busm_clk @[lsu_bus_intf.scala 111:51] + bus_buffer.io.dec_lsu_valid_raw_d <= io.dec_lsu_valid_raw_d @[lsu_bus_intf.scala 112:51] + bus_buffer.io.lsu_pkt_m.bits.store_data_bypass_m <= io.lsu_pkt_m.bits.store_data_bypass_m @[lsu_bus_intf.scala 115:27] + bus_buffer.io.lsu_pkt_m.bits.load_ldst_bypass_d <= io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu_bus_intf.scala 115:27] + bus_buffer.io.lsu_pkt_m.bits.store_data_bypass_d <= io.lsu_pkt_m.bits.store_data_bypass_d @[lsu_bus_intf.scala 115:27] + bus_buffer.io.lsu_pkt_m.bits.dma <= io.lsu_pkt_m.bits.dma @[lsu_bus_intf.scala 115:27] + bus_buffer.io.lsu_pkt_m.bits.unsign <= io.lsu_pkt_m.bits.unsign @[lsu_bus_intf.scala 115:27] + bus_buffer.io.lsu_pkt_m.bits.store <= io.lsu_pkt_m.bits.store @[lsu_bus_intf.scala 115:27] + bus_buffer.io.lsu_pkt_m.bits.load <= io.lsu_pkt_m.bits.load @[lsu_bus_intf.scala 115:27] + bus_buffer.io.lsu_pkt_m.bits.dword <= io.lsu_pkt_m.bits.dword @[lsu_bus_intf.scala 115:27] + bus_buffer.io.lsu_pkt_m.bits.word <= io.lsu_pkt_m.bits.word @[lsu_bus_intf.scala 115:27] + bus_buffer.io.lsu_pkt_m.bits.half <= io.lsu_pkt_m.bits.half @[lsu_bus_intf.scala 115:27] + bus_buffer.io.lsu_pkt_m.bits.by <= io.lsu_pkt_m.bits.by @[lsu_bus_intf.scala 115:27] + bus_buffer.io.lsu_pkt_m.bits.fast_int <= io.lsu_pkt_m.bits.fast_int @[lsu_bus_intf.scala 115:27] + bus_buffer.io.lsu_pkt_m.valid <= io.lsu_pkt_m.valid @[lsu_bus_intf.scala 115:27] + bus_buffer.io.lsu_pkt_r.bits.store_data_bypass_m <= io.lsu_pkt_r.bits.store_data_bypass_m @[lsu_bus_intf.scala 116:27] + bus_buffer.io.lsu_pkt_r.bits.load_ldst_bypass_d <= io.lsu_pkt_r.bits.load_ldst_bypass_d @[lsu_bus_intf.scala 116:27] + bus_buffer.io.lsu_pkt_r.bits.store_data_bypass_d <= io.lsu_pkt_r.bits.store_data_bypass_d @[lsu_bus_intf.scala 116:27] + bus_buffer.io.lsu_pkt_r.bits.dma <= io.lsu_pkt_r.bits.dma @[lsu_bus_intf.scala 116:27] + bus_buffer.io.lsu_pkt_r.bits.unsign <= io.lsu_pkt_r.bits.unsign @[lsu_bus_intf.scala 116:27] + bus_buffer.io.lsu_pkt_r.bits.store <= io.lsu_pkt_r.bits.store @[lsu_bus_intf.scala 116:27] + bus_buffer.io.lsu_pkt_r.bits.load <= io.lsu_pkt_r.bits.load @[lsu_bus_intf.scala 116:27] + bus_buffer.io.lsu_pkt_r.bits.dword <= io.lsu_pkt_r.bits.dword @[lsu_bus_intf.scala 116:27] + bus_buffer.io.lsu_pkt_r.bits.word <= io.lsu_pkt_r.bits.word @[lsu_bus_intf.scala 116:27] + bus_buffer.io.lsu_pkt_r.bits.half <= io.lsu_pkt_r.bits.half @[lsu_bus_intf.scala 116:27] + bus_buffer.io.lsu_pkt_r.bits.by <= io.lsu_pkt_r.bits.by @[lsu_bus_intf.scala 116:27] + bus_buffer.io.lsu_pkt_r.bits.fast_int <= io.lsu_pkt_r.bits.fast_int @[lsu_bus_intf.scala 116:27] + bus_buffer.io.lsu_pkt_r.valid <= io.lsu_pkt_r.valid @[lsu_bus_intf.scala 116:27] + bus_buffer.io.lsu_addr_m <= io.lsu_addr_m @[lsu_bus_intf.scala 119:51] + bus_buffer.io.end_addr_m <= io.end_addr_m @[lsu_bus_intf.scala 120:51] + bus_buffer.io.lsu_addr_r <= io.lsu_addr_r @[lsu_bus_intf.scala 121:51] + bus_buffer.io.end_addr_r <= io.end_addr_r @[lsu_bus_intf.scala 122:51] + bus_buffer.io.store_data_r <= io.store_data_r @[lsu_bus_intf.scala 123:51] + bus_buffer.io.lsu_busreq_m <= io.lsu_busreq_m @[lsu_bus_intf.scala 125:51] + bus_buffer.io.flush_m_up <= io.flush_m_up @[lsu_bus_intf.scala 126:51] + bus_buffer.io.flush_r <= io.flush_r @[lsu_bus_intf.scala 127:51] + bus_buffer.io.lsu_commit_r <= io.lsu_commit_r @[lsu_bus_intf.scala 128:51] + bus_buffer.io.lsu_axi.r.bits.last <= io.axi.r.bits.last @[lsu_bus_intf.scala 129:43] + bus_buffer.io.lsu_axi.r.bits.resp <= io.axi.r.bits.resp @[lsu_bus_intf.scala 129:43] + bus_buffer.io.lsu_axi.r.bits.data <= io.axi.r.bits.data @[lsu_bus_intf.scala 129:43] + bus_buffer.io.lsu_axi.r.bits.id <= io.axi.r.bits.id @[lsu_bus_intf.scala 129:43] + bus_buffer.io.lsu_axi.r.valid <= io.axi.r.valid @[lsu_bus_intf.scala 129:43] + io.axi.r.ready <= bus_buffer.io.lsu_axi.r.ready @[lsu_bus_intf.scala 129:43] + io.axi.ar.bits.qos <= bus_buffer.io.lsu_axi.ar.bits.qos @[lsu_bus_intf.scala 129:43] + io.axi.ar.bits.prot <= bus_buffer.io.lsu_axi.ar.bits.prot @[lsu_bus_intf.scala 129:43] + io.axi.ar.bits.cache <= bus_buffer.io.lsu_axi.ar.bits.cache @[lsu_bus_intf.scala 129:43] + io.axi.ar.bits.lock <= bus_buffer.io.lsu_axi.ar.bits.lock @[lsu_bus_intf.scala 129:43] + io.axi.ar.bits.burst <= bus_buffer.io.lsu_axi.ar.bits.burst @[lsu_bus_intf.scala 129:43] + io.axi.ar.bits.size <= bus_buffer.io.lsu_axi.ar.bits.size @[lsu_bus_intf.scala 129:43] + io.axi.ar.bits.len <= bus_buffer.io.lsu_axi.ar.bits.len @[lsu_bus_intf.scala 129:43] + io.axi.ar.bits.region <= bus_buffer.io.lsu_axi.ar.bits.region @[lsu_bus_intf.scala 129:43] + io.axi.ar.bits.addr <= bus_buffer.io.lsu_axi.ar.bits.addr @[lsu_bus_intf.scala 129:43] + io.axi.ar.bits.id <= bus_buffer.io.lsu_axi.ar.bits.id @[lsu_bus_intf.scala 129:43] + io.axi.ar.valid <= bus_buffer.io.lsu_axi.ar.valid @[lsu_bus_intf.scala 129:43] + bus_buffer.io.lsu_axi.ar.ready <= io.axi.ar.ready @[lsu_bus_intf.scala 129:43] + bus_buffer.io.lsu_axi.b.bits.id <= io.axi.b.bits.id @[lsu_bus_intf.scala 129:43] + bus_buffer.io.lsu_axi.b.bits.resp <= io.axi.b.bits.resp @[lsu_bus_intf.scala 129:43] + bus_buffer.io.lsu_axi.b.valid <= io.axi.b.valid @[lsu_bus_intf.scala 129:43] + io.axi.b.ready <= bus_buffer.io.lsu_axi.b.ready @[lsu_bus_intf.scala 129:43] + io.axi.w.bits.last <= bus_buffer.io.lsu_axi.w.bits.last @[lsu_bus_intf.scala 129:43] + io.axi.w.bits.strb <= bus_buffer.io.lsu_axi.w.bits.strb @[lsu_bus_intf.scala 129:43] + io.axi.w.bits.data <= bus_buffer.io.lsu_axi.w.bits.data @[lsu_bus_intf.scala 129:43] + io.axi.w.valid <= bus_buffer.io.lsu_axi.w.valid @[lsu_bus_intf.scala 129:43] + bus_buffer.io.lsu_axi.w.ready <= io.axi.w.ready @[lsu_bus_intf.scala 129:43] + io.axi.aw.bits.qos <= bus_buffer.io.lsu_axi.aw.bits.qos @[lsu_bus_intf.scala 129:43] + io.axi.aw.bits.prot <= bus_buffer.io.lsu_axi.aw.bits.prot @[lsu_bus_intf.scala 129:43] + io.axi.aw.bits.cache <= bus_buffer.io.lsu_axi.aw.bits.cache @[lsu_bus_intf.scala 129:43] + io.axi.aw.bits.lock <= bus_buffer.io.lsu_axi.aw.bits.lock @[lsu_bus_intf.scala 129:43] + io.axi.aw.bits.burst <= bus_buffer.io.lsu_axi.aw.bits.burst @[lsu_bus_intf.scala 129:43] + io.axi.aw.bits.size <= bus_buffer.io.lsu_axi.aw.bits.size @[lsu_bus_intf.scala 129:43] + io.axi.aw.bits.len <= bus_buffer.io.lsu_axi.aw.bits.len @[lsu_bus_intf.scala 129:43] + io.axi.aw.bits.region <= bus_buffer.io.lsu_axi.aw.bits.region @[lsu_bus_intf.scala 129:43] + io.axi.aw.bits.addr <= bus_buffer.io.lsu_axi.aw.bits.addr @[lsu_bus_intf.scala 129:43] + io.axi.aw.bits.id <= bus_buffer.io.lsu_axi.aw.bits.id @[lsu_bus_intf.scala 129:43] + io.axi.aw.valid <= bus_buffer.io.lsu_axi.aw.valid @[lsu_bus_intf.scala 129:43] + bus_buffer.io.lsu_axi.aw.ready <= io.axi.aw.ready @[lsu_bus_intf.scala 129:43] + bus_buffer.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[lsu_bus_intf.scala 130:51] + io.lsu_busreq_r <= bus_buffer.io.lsu_busreq_r @[lsu_bus_intf.scala 132:38] + io.lsu_bus_buffer_pend_any <= bus_buffer.io.lsu_bus_buffer_pend_any @[lsu_bus_intf.scala 133:38] + io.lsu_bus_buffer_full_any <= bus_buffer.io.lsu_bus_buffer_full_any @[lsu_bus_intf.scala 134:38] + io.lsu_bus_buffer_empty_any <= bus_buffer.io.lsu_bus_buffer_empty_any @[lsu_bus_intf.scala 135:38] + io.lsu_bus_idle_any <= bus_buffer.io.lsu_bus_idle_any @[lsu_bus_intf.scala 136:38] + ld_byte_hit_buf_lo <= bus_buffer.io.ld_byte_hit_buf_lo @[lsu_bus_intf.scala 137:38] + ld_byte_hit_buf_hi <= bus_buffer.io.ld_byte_hit_buf_hi @[lsu_bus_intf.scala 138:38] + ld_fwddata_buf_lo <= bus_buffer.io.ld_fwddata_buf_lo @[lsu_bus_intf.scala 139:38] + ld_fwddata_buf_hi <= bus_buffer.io.ld_fwddata_buf_hi @[lsu_bus_intf.scala 140:38] + io.dctl_busbuff.lsu_nonblock_load_data <= bus_buffer.io.dctl_busbuff.lsu_nonblock_load_data @[lsu_bus_intf.scala 141:19] + io.dctl_busbuff.lsu_nonblock_load_data_tag <= bus_buffer.io.dctl_busbuff.lsu_nonblock_load_data_tag @[lsu_bus_intf.scala 141:19] + io.dctl_busbuff.lsu_nonblock_load_data_error <= bus_buffer.io.dctl_busbuff.lsu_nonblock_load_data_error @[lsu_bus_intf.scala 141:19] + io.dctl_busbuff.lsu_nonblock_load_data_valid <= bus_buffer.io.dctl_busbuff.lsu_nonblock_load_data_valid @[lsu_bus_intf.scala 141:19] + io.dctl_busbuff.lsu_nonblock_load_inv_tag_r <= bus_buffer.io.dctl_busbuff.lsu_nonblock_load_inv_tag_r @[lsu_bus_intf.scala 141:19] + io.dctl_busbuff.lsu_nonblock_load_inv_r <= bus_buffer.io.dctl_busbuff.lsu_nonblock_load_inv_r @[lsu_bus_intf.scala 141:19] + io.dctl_busbuff.lsu_nonblock_load_tag_m <= bus_buffer.io.dctl_busbuff.lsu_nonblock_load_tag_m @[lsu_bus_intf.scala 141:19] + io.dctl_busbuff.lsu_nonblock_load_valid_m <= bus_buffer.io.dctl_busbuff.lsu_nonblock_load_valid_m @[lsu_bus_intf.scala 141:19] + bus_buffer.io.no_word_merge_r <= no_word_merge_r @[lsu_bus_intf.scala 142:51] + bus_buffer.io.no_dword_merge_r <= no_dword_merge_r @[lsu_bus_intf.scala 143:51] + bus_buffer.io.is_sideeffects_r <= is_sideeffects_r @[lsu_bus_intf.scala 144:51] + bus_buffer.io.ldst_dual_d <= ldst_dual_d @[lsu_bus_intf.scala 145:51] + bus_buffer.io.ldst_dual_m <= ldst_dual_m @[lsu_bus_intf.scala 146:51] + bus_buffer.io.ldst_dual_r <= ldst_dual_r @[lsu_bus_intf.scala 147:51] + bus_buffer.io.ldst_byteen_ext_m <= ldst_byteen_ext_m @[lsu_bus_intf.scala 148:51] + bus_buffer.io.ld_full_hit_m <= ld_full_hit_m @[lsu_bus_intf.scala 149:51] + bus_buffer.io.lsu_bus_clk_en_q <= lsu_bus_clk_en_q @[lsu_bus_intf.scala 150:51] + node _T = bits(io.lsu_pkt_m.bits.word, 0, 0) @[lsu_bus_intf.scala 152:63] + node _T_1 = bits(io.lsu_pkt_m.bits.half, 0, 0) @[lsu_bus_intf.scala 152:107] + node _T_2 = bits(io.lsu_pkt_m.bits.by, 0, 0) @[lsu_bus_intf.scala 152:148] + node _T_3 = mux(_T, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4 = mux(_T_1, UInt<4>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_5 = mux(_T_2, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_6 = or(_T_3, _T_4) @[Mux.scala 27:72] + node _T_7 = or(_T_6, _T_5) @[Mux.scala 27:72] + wire _T_8 : UInt<4> @[Mux.scala 27:72] + _T_8 <= _T_7 @[Mux.scala 27:72] + ldst_byteen_m <= _T_8 @[lsu_bus_intf.scala 152:27] + node _T_9 = bits(io.lsu_addr_d, 2, 2) @[lsu_bus_intf.scala 153:43] + node _T_10 = bits(io.end_addr_d, 2, 2) @[lsu_bus_intf.scala 153:64] + node _T_11 = neq(_T_9, _T_10) @[lsu_bus_intf.scala 153:47] + ldst_dual_d <= _T_11 @[lsu_bus_intf.scala 153:27] + node _T_12 = bits(io.lsu_addr_r, 31, 3) @[lsu_bus_intf.scala 154:44] + node _T_13 = bits(io.lsu_addr_m, 31, 3) @[lsu_bus_intf.scala 154:68] + node _T_14 = eq(_T_12, _T_13) @[lsu_bus_intf.scala 154:51] + addr_match_dw_lo_r_m <= _T_14 @[lsu_bus_intf.scala 154:27] + node _T_15 = bits(io.lsu_addr_r, 2, 2) @[lsu_bus_intf.scala 155:68] + node _T_16 = bits(io.lsu_addr_m, 2, 2) @[lsu_bus_intf.scala 155:85] + node _T_17 = xor(_T_15, _T_16) @[lsu_bus_intf.scala 155:71] + node _T_18 = eq(_T_17, UInt<1>("h00")) @[lsu_bus_intf.scala 155:53] + node _T_19 = and(addr_match_dw_lo_r_m, _T_18) @[lsu_bus_intf.scala 155:51] + addr_match_word_lo_r_m <= _T_19 @[lsu_bus_intf.scala 155:27] + node _T_20 = eq(ldst_dual_r, UInt<1>("h00")) @[lsu_bus_intf.scala 156:48] + node _T_21 = and(io.lsu_busreq_r, _T_20) @[lsu_bus_intf.scala 156:46] + node _T_22 = and(_T_21, io.lsu_busreq_m) @[lsu_bus_intf.scala 156:61] + node _T_23 = eq(addr_match_word_lo_r_m, UInt<1>("h00")) @[lsu_bus_intf.scala 156:107] + node _T_24 = or(io.lsu_pkt_m.bits.load, _T_23) @[lsu_bus_intf.scala 156:105] + node _T_25 = and(_T_22, _T_24) @[lsu_bus_intf.scala 156:79] + no_word_merge_r <= _T_25 @[lsu_bus_intf.scala 156:27] + node _T_26 = eq(ldst_dual_r, UInt<1>("h00")) @[lsu_bus_intf.scala 157:48] + node _T_27 = and(io.lsu_busreq_r, _T_26) @[lsu_bus_intf.scala 157:46] + node _T_28 = and(_T_27, io.lsu_busreq_m) @[lsu_bus_intf.scala 157:61] + node _T_29 = eq(addr_match_dw_lo_r_m, UInt<1>("h00")) @[lsu_bus_intf.scala 157:107] + node _T_30 = or(io.lsu_pkt_m.bits.load, _T_29) @[lsu_bus_intf.scala 157:105] + node _T_31 = and(_T_28, _T_30) @[lsu_bus_intf.scala 157:79] + no_dword_merge_r <= _T_31 @[lsu_bus_intf.scala 157:27] + node _T_32 = bits(ldst_byteen_m, 3, 0) @[lsu_bus_intf.scala 159:43] + node _T_33 = bits(io.lsu_addr_m, 1, 0) @[lsu_bus_intf.scala 159:65] + node _T_34 = dshl(_T_32, _T_33) @[lsu_bus_intf.scala 159:49] + ldst_byteen_ext_m <= _T_34 @[lsu_bus_intf.scala 159:27] + node _T_35 = bits(ldst_byteen_r, 3, 0) @[lsu_bus_intf.scala 160:43] + node _T_36 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_intf.scala 160:65] + node _T_37 = dshl(_T_35, _T_36) @[lsu_bus_intf.scala 160:49] + ldst_byteen_ext_r <= _T_37 @[lsu_bus_intf.scala 160:27] + node _T_38 = bits(io.store_data_r, 31, 0) @[lsu_bus_intf.scala 161:45] + node _T_39 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_intf.scala 161:72] + node _T_40 = cat(_T_39, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_41 = dshl(_T_38, _T_40) @[lsu_bus_intf.scala 161:52] + store_data_ext_r <= _T_41 @[lsu_bus_intf.scala 161:27] + node _T_42 = bits(ldst_byteen_ext_m, 7, 4) @[lsu_bus_intf.scala 162:47] + ldst_byteen_hi_m <= _T_42 @[lsu_bus_intf.scala 162:27] + node _T_43 = bits(ldst_byteen_ext_m, 3, 0) @[lsu_bus_intf.scala 163:47] + ldst_byteen_lo_m <= _T_43 @[lsu_bus_intf.scala 163:27] + node _T_44 = bits(ldst_byteen_ext_r, 7, 4) @[lsu_bus_intf.scala 164:47] + ldst_byteen_hi_r <= _T_44 @[lsu_bus_intf.scala 164:27] + node _T_45 = bits(ldst_byteen_ext_r, 3, 0) @[lsu_bus_intf.scala 165:47] + ldst_byteen_lo_r <= _T_45 @[lsu_bus_intf.scala 165:27] + node _T_46 = bits(store_data_ext_r, 63, 32) @[lsu_bus_intf.scala 167:46] + store_data_hi_r <= _T_46 @[lsu_bus_intf.scala 167:27] + node _T_47 = bits(store_data_ext_r, 31, 0) @[lsu_bus_intf.scala 168:46] + store_data_lo_r <= _T_47 @[lsu_bus_intf.scala 168:27] + node _T_48 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_intf.scala 169:44] + node _T_49 = bits(io.lsu_addr_r, 31, 2) @[lsu_bus_intf.scala 169:68] + node _T_50 = eq(_T_48, _T_49) @[lsu_bus_intf.scala 169:51] + node _T_51 = and(_T_50, io.lsu_pkt_r.valid) @[lsu_bus_intf.scala 169:76] + node _T_52 = and(_T_51, io.lsu_pkt_r.bits.store) @[lsu_bus_intf.scala 169:97] + node _T_53 = and(_T_52, io.lsu_busreq_m) @[lsu_bus_intf.scala 169:123] + ld_addr_rhit_lo_lo <= _T_53 @[lsu_bus_intf.scala 169:27] + node _T_54 = bits(io.end_addr_m, 31, 2) @[lsu_bus_intf.scala 170:44] + node _T_55 = bits(io.lsu_addr_r, 31, 2) @[lsu_bus_intf.scala 170:68] + node _T_56 = eq(_T_54, _T_55) @[lsu_bus_intf.scala 170:51] + node _T_57 = and(_T_56, io.lsu_pkt_r.valid) @[lsu_bus_intf.scala 170:76] + node _T_58 = and(_T_57, io.lsu_pkt_r.bits.store) @[lsu_bus_intf.scala 170:97] + node _T_59 = and(_T_58, io.lsu_busreq_m) @[lsu_bus_intf.scala 170:123] + ld_addr_rhit_lo_hi <= _T_59 @[lsu_bus_intf.scala 170:27] + node _T_60 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_intf.scala 171:44] + node _T_61 = bits(io.end_addr_r, 31, 2) @[lsu_bus_intf.scala 171:68] + node _T_62 = eq(_T_60, _T_61) @[lsu_bus_intf.scala 171:51] + node _T_63 = and(_T_62, io.lsu_pkt_r.valid) @[lsu_bus_intf.scala 171:76] + node _T_64 = and(_T_63, io.lsu_pkt_r.bits.store) @[lsu_bus_intf.scala 171:97] + node _T_65 = and(_T_64, io.lsu_busreq_m) @[lsu_bus_intf.scala 171:123] + ld_addr_rhit_hi_lo <= _T_65 @[lsu_bus_intf.scala 171:27] + node _T_66 = bits(io.end_addr_m, 31, 2) @[lsu_bus_intf.scala 172:44] + node _T_67 = bits(io.end_addr_r, 31, 2) @[lsu_bus_intf.scala 172:68] + node _T_68 = eq(_T_66, _T_67) @[lsu_bus_intf.scala 172:51] + node _T_69 = and(_T_68, io.lsu_pkt_r.valid) @[lsu_bus_intf.scala 172:76] + node _T_70 = and(_T_69, io.lsu_pkt_r.bits.store) @[lsu_bus_intf.scala 172:97] + node _T_71 = and(_T_70, io.lsu_busreq_m) @[lsu_bus_intf.scala 172:123] + ld_addr_rhit_hi_hi <= _T_71 @[lsu_bus_intf.scala 172:27] + node _T_72 = bits(ldst_byteen_lo_r, 0, 0) @[lsu_bus_intf.scala 174:88] + node _T_73 = and(ld_addr_rhit_lo_lo, _T_72) @[lsu_bus_intf.scala 174:70] + node _T_74 = bits(ldst_byteen_lo_m, 0, 0) @[lsu_bus_intf.scala 174:110] + node _T_75 = and(_T_73, _T_74) @[lsu_bus_intf.scala 174:92] + node _T_76 = bits(ldst_byteen_lo_r, 1, 1) @[lsu_bus_intf.scala 174:88] + node _T_77 = and(ld_addr_rhit_lo_lo, _T_76) @[lsu_bus_intf.scala 174:70] + node _T_78 = bits(ldst_byteen_lo_m, 1, 1) @[lsu_bus_intf.scala 174:110] + node _T_79 = and(_T_77, _T_78) @[lsu_bus_intf.scala 174:92] + node _T_80 = bits(ldst_byteen_lo_r, 2, 2) @[lsu_bus_intf.scala 174:88] + node _T_81 = and(ld_addr_rhit_lo_lo, _T_80) @[lsu_bus_intf.scala 174:70] + node _T_82 = bits(ldst_byteen_lo_m, 2, 2) @[lsu_bus_intf.scala 174:110] + node _T_83 = and(_T_81, _T_82) @[lsu_bus_intf.scala 174:92] + node _T_84 = bits(ldst_byteen_lo_r, 3, 3) @[lsu_bus_intf.scala 174:88] + node _T_85 = and(ld_addr_rhit_lo_lo, _T_84) @[lsu_bus_intf.scala 174:70] + node _T_86 = bits(ldst_byteen_lo_m, 3, 3) @[lsu_bus_intf.scala 174:110] + node _T_87 = and(_T_85, _T_86) @[lsu_bus_intf.scala 174:92] + node _T_88 = cat(_T_87, _T_83) @[Cat.scala 29:58] + node _T_89 = cat(_T_88, _T_79) @[Cat.scala 29:58] + node _T_90 = cat(_T_89, _T_75) @[Cat.scala 29:58] + ld_byte_rhit_lo_lo <= _T_90 @[lsu_bus_intf.scala 174:27] + node _T_91 = bits(ldst_byteen_lo_r, 0, 0) @[lsu_bus_intf.scala 175:88] + node _T_92 = and(ld_addr_rhit_lo_hi, _T_91) @[lsu_bus_intf.scala 175:70] + node _T_93 = bits(ldst_byteen_hi_m, 0, 0) @[lsu_bus_intf.scala 175:110] + node _T_94 = and(_T_92, _T_93) @[lsu_bus_intf.scala 175:92] + node _T_95 = bits(ldst_byteen_lo_r, 1, 1) @[lsu_bus_intf.scala 175:88] + node _T_96 = and(ld_addr_rhit_lo_hi, _T_95) @[lsu_bus_intf.scala 175:70] + node _T_97 = bits(ldst_byteen_hi_m, 1, 1) @[lsu_bus_intf.scala 175:110] + node _T_98 = and(_T_96, _T_97) @[lsu_bus_intf.scala 175:92] + node _T_99 = bits(ldst_byteen_lo_r, 2, 2) @[lsu_bus_intf.scala 175:88] + node _T_100 = and(ld_addr_rhit_lo_hi, _T_99) @[lsu_bus_intf.scala 175:70] + node _T_101 = bits(ldst_byteen_hi_m, 2, 2) @[lsu_bus_intf.scala 175:110] + node _T_102 = and(_T_100, _T_101) @[lsu_bus_intf.scala 175:92] + node _T_103 = bits(ldst_byteen_lo_r, 3, 3) @[lsu_bus_intf.scala 175:88] + node _T_104 = and(ld_addr_rhit_lo_hi, _T_103) @[lsu_bus_intf.scala 175:70] + node _T_105 = bits(ldst_byteen_hi_m, 3, 3) @[lsu_bus_intf.scala 175:110] + node _T_106 = and(_T_104, _T_105) @[lsu_bus_intf.scala 175:92] + node _T_107 = cat(_T_106, _T_102) @[Cat.scala 29:58] + node _T_108 = cat(_T_107, _T_98) @[Cat.scala 29:58] + node _T_109 = cat(_T_108, _T_94) @[Cat.scala 29:58] + ld_byte_rhit_lo_hi <= _T_109 @[lsu_bus_intf.scala 175:27] + node _T_110 = bits(ldst_byteen_hi_r, 0, 0) @[lsu_bus_intf.scala 176:88] + node _T_111 = and(ld_addr_rhit_hi_lo, _T_110) @[lsu_bus_intf.scala 176:70] + node _T_112 = bits(ldst_byteen_lo_m, 0, 0) @[lsu_bus_intf.scala 176:110] + node _T_113 = and(_T_111, _T_112) @[lsu_bus_intf.scala 176:92] + node _T_114 = bits(ldst_byteen_hi_r, 1, 1) @[lsu_bus_intf.scala 176:88] + node _T_115 = and(ld_addr_rhit_hi_lo, _T_114) @[lsu_bus_intf.scala 176:70] + node _T_116 = bits(ldst_byteen_lo_m, 1, 1) @[lsu_bus_intf.scala 176:110] + node _T_117 = and(_T_115, _T_116) @[lsu_bus_intf.scala 176:92] + node _T_118 = bits(ldst_byteen_hi_r, 2, 2) @[lsu_bus_intf.scala 176:88] + node _T_119 = and(ld_addr_rhit_hi_lo, _T_118) @[lsu_bus_intf.scala 176:70] + node _T_120 = bits(ldst_byteen_lo_m, 2, 2) @[lsu_bus_intf.scala 176:110] + node _T_121 = and(_T_119, _T_120) @[lsu_bus_intf.scala 176:92] + node _T_122 = bits(ldst_byteen_hi_r, 3, 3) @[lsu_bus_intf.scala 176:88] + node _T_123 = and(ld_addr_rhit_hi_lo, _T_122) @[lsu_bus_intf.scala 176:70] + node _T_124 = bits(ldst_byteen_lo_m, 3, 3) @[lsu_bus_intf.scala 176:110] + node _T_125 = and(_T_123, _T_124) @[lsu_bus_intf.scala 176:92] + node _T_126 = cat(_T_125, _T_121) @[Cat.scala 29:58] + node _T_127 = cat(_T_126, _T_117) @[Cat.scala 29:58] + node _T_128 = cat(_T_127, _T_113) @[Cat.scala 29:58] + ld_byte_rhit_hi_lo <= _T_128 @[lsu_bus_intf.scala 176:27] + node _T_129 = bits(ldst_byteen_hi_r, 0, 0) @[lsu_bus_intf.scala 177:88] + node _T_130 = and(ld_addr_rhit_hi_hi, _T_129) @[lsu_bus_intf.scala 177:70] + node _T_131 = bits(ldst_byteen_hi_m, 0, 0) @[lsu_bus_intf.scala 177:110] + node _T_132 = and(_T_130, _T_131) @[lsu_bus_intf.scala 177:92] + node _T_133 = bits(ldst_byteen_hi_r, 1, 1) @[lsu_bus_intf.scala 177:88] + node _T_134 = and(ld_addr_rhit_hi_hi, _T_133) @[lsu_bus_intf.scala 177:70] + node _T_135 = bits(ldst_byteen_hi_m, 1, 1) @[lsu_bus_intf.scala 177:110] + node _T_136 = and(_T_134, _T_135) @[lsu_bus_intf.scala 177:92] + node _T_137 = bits(ldst_byteen_hi_r, 2, 2) @[lsu_bus_intf.scala 177:88] + node _T_138 = and(ld_addr_rhit_hi_hi, _T_137) @[lsu_bus_intf.scala 177:70] + node _T_139 = bits(ldst_byteen_hi_m, 2, 2) @[lsu_bus_intf.scala 177:110] + node _T_140 = and(_T_138, _T_139) @[lsu_bus_intf.scala 177:92] + node _T_141 = bits(ldst_byteen_hi_r, 3, 3) @[lsu_bus_intf.scala 177:88] + node _T_142 = and(ld_addr_rhit_hi_hi, _T_141) @[lsu_bus_intf.scala 177:70] + node _T_143 = bits(ldst_byteen_hi_m, 3, 3) @[lsu_bus_intf.scala 177:110] + node _T_144 = and(_T_142, _T_143) @[lsu_bus_intf.scala 177:92] + node _T_145 = cat(_T_144, _T_140) @[Cat.scala 29:58] + node _T_146 = cat(_T_145, _T_136) @[Cat.scala 29:58] + node _T_147 = cat(_T_146, _T_132) @[Cat.scala 29:58] + ld_byte_rhit_hi_hi <= _T_147 @[lsu_bus_intf.scala 177:27] + node _T_148 = bits(ld_byte_rhit_lo_lo, 0, 0) @[lsu_bus_intf.scala 179:69] + node _T_149 = bits(ld_byte_rhit_hi_lo, 0, 0) @[lsu_bus_intf.scala 179:93] + node _T_150 = or(_T_148, _T_149) @[lsu_bus_intf.scala 179:73] + node _T_151 = bits(ld_byte_hit_buf_lo, 0, 0) @[lsu_bus_intf.scala 179:117] + node _T_152 = or(_T_150, _T_151) @[lsu_bus_intf.scala 179:97] + node _T_153 = bits(ld_byte_rhit_lo_lo, 1, 1) @[lsu_bus_intf.scala 179:69] + node _T_154 = bits(ld_byte_rhit_hi_lo, 1, 1) @[lsu_bus_intf.scala 179:93] + node _T_155 = or(_T_153, _T_154) @[lsu_bus_intf.scala 179:73] + node _T_156 = bits(ld_byte_hit_buf_lo, 1, 1) @[lsu_bus_intf.scala 179:117] + node _T_157 = or(_T_155, _T_156) @[lsu_bus_intf.scala 179:97] + node _T_158 = bits(ld_byte_rhit_lo_lo, 2, 2) @[lsu_bus_intf.scala 179:69] + node _T_159 = bits(ld_byte_rhit_hi_lo, 2, 2) @[lsu_bus_intf.scala 179:93] + node _T_160 = or(_T_158, _T_159) @[lsu_bus_intf.scala 179:73] + node _T_161 = bits(ld_byte_hit_buf_lo, 2, 2) @[lsu_bus_intf.scala 179:117] + node _T_162 = or(_T_160, _T_161) @[lsu_bus_intf.scala 179:97] + node _T_163 = bits(ld_byte_rhit_lo_lo, 3, 3) @[lsu_bus_intf.scala 179:69] + node _T_164 = bits(ld_byte_rhit_hi_lo, 3, 3) @[lsu_bus_intf.scala 179:93] + node _T_165 = or(_T_163, _T_164) @[lsu_bus_intf.scala 179:73] + node _T_166 = bits(ld_byte_hit_buf_lo, 3, 3) @[lsu_bus_intf.scala 179:117] + node _T_167 = or(_T_165, _T_166) @[lsu_bus_intf.scala 179:97] + node _T_168 = cat(_T_167, _T_162) @[Cat.scala 29:58] + node _T_169 = cat(_T_168, _T_157) @[Cat.scala 29:58] + node _T_170 = cat(_T_169, _T_152) @[Cat.scala 29:58] + ld_byte_hit_lo <= _T_170 @[lsu_bus_intf.scala 179:27] + node _T_171 = bits(ld_byte_rhit_lo_hi, 0, 0) @[lsu_bus_intf.scala 180:69] + node _T_172 = bits(ld_byte_rhit_hi_hi, 0, 0) @[lsu_bus_intf.scala 180:93] + node _T_173 = or(_T_171, _T_172) @[lsu_bus_intf.scala 180:73] + node _T_174 = bits(ld_byte_hit_buf_hi, 0, 0) @[lsu_bus_intf.scala 180:117] + node _T_175 = or(_T_173, _T_174) @[lsu_bus_intf.scala 180:97] + node _T_176 = bits(ld_byte_rhit_lo_hi, 1, 1) @[lsu_bus_intf.scala 180:69] + node _T_177 = bits(ld_byte_rhit_hi_hi, 1, 1) @[lsu_bus_intf.scala 180:93] + node _T_178 = or(_T_176, _T_177) @[lsu_bus_intf.scala 180:73] + node _T_179 = bits(ld_byte_hit_buf_hi, 1, 1) @[lsu_bus_intf.scala 180:117] + node _T_180 = or(_T_178, _T_179) @[lsu_bus_intf.scala 180:97] + node _T_181 = bits(ld_byte_rhit_lo_hi, 2, 2) @[lsu_bus_intf.scala 180:69] + node _T_182 = bits(ld_byte_rhit_hi_hi, 2, 2) @[lsu_bus_intf.scala 180:93] + node _T_183 = or(_T_181, _T_182) @[lsu_bus_intf.scala 180:73] + node _T_184 = bits(ld_byte_hit_buf_hi, 2, 2) @[lsu_bus_intf.scala 180:117] + node _T_185 = or(_T_183, _T_184) @[lsu_bus_intf.scala 180:97] + node _T_186 = bits(ld_byte_rhit_lo_hi, 3, 3) @[lsu_bus_intf.scala 180:69] + node _T_187 = bits(ld_byte_rhit_hi_hi, 3, 3) @[lsu_bus_intf.scala 180:93] + node _T_188 = or(_T_186, _T_187) @[lsu_bus_intf.scala 180:73] + node _T_189 = bits(ld_byte_hit_buf_hi, 3, 3) @[lsu_bus_intf.scala 180:117] + node _T_190 = or(_T_188, _T_189) @[lsu_bus_intf.scala 180:97] + node _T_191 = cat(_T_190, _T_185) @[Cat.scala 29:58] + node _T_192 = cat(_T_191, _T_180) @[Cat.scala 29:58] + node _T_193 = cat(_T_192, _T_175) @[Cat.scala 29:58] + ld_byte_hit_hi <= _T_193 @[lsu_bus_intf.scala 180:27] + node _T_194 = bits(ld_byte_rhit_lo_lo, 0, 0) @[lsu_bus_intf.scala 181:69] + node _T_195 = bits(ld_byte_rhit_hi_lo, 0, 0) @[lsu_bus_intf.scala 181:93] + node _T_196 = or(_T_194, _T_195) @[lsu_bus_intf.scala 181:73] + node _T_197 = bits(ld_byte_rhit_lo_lo, 1, 1) @[lsu_bus_intf.scala 181:69] + node _T_198 = bits(ld_byte_rhit_hi_lo, 1, 1) @[lsu_bus_intf.scala 181:93] + node _T_199 = or(_T_197, _T_198) @[lsu_bus_intf.scala 181:73] + node _T_200 = bits(ld_byte_rhit_lo_lo, 2, 2) @[lsu_bus_intf.scala 181:69] + node _T_201 = bits(ld_byte_rhit_hi_lo, 2, 2) @[lsu_bus_intf.scala 181:93] + node _T_202 = or(_T_200, _T_201) @[lsu_bus_intf.scala 181:73] + node _T_203 = bits(ld_byte_rhit_lo_lo, 3, 3) @[lsu_bus_intf.scala 181:69] + node _T_204 = bits(ld_byte_rhit_hi_lo, 3, 3) @[lsu_bus_intf.scala 181:93] + node _T_205 = or(_T_203, _T_204) @[lsu_bus_intf.scala 181:73] + node _T_206 = cat(_T_205, _T_202) @[Cat.scala 29:58] + node _T_207 = cat(_T_206, _T_199) @[Cat.scala 29:58] + node _T_208 = cat(_T_207, _T_196) @[Cat.scala 29:58] + ld_byte_rhit_lo <= _T_208 @[lsu_bus_intf.scala 181:27] + node _T_209 = bits(ld_byte_rhit_lo_hi, 0, 0) @[lsu_bus_intf.scala 182:69] + node _T_210 = bits(ld_byte_rhit_hi_hi, 0, 0) @[lsu_bus_intf.scala 182:93] + node _T_211 = or(_T_209, _T_210) @[lsu_bus_intf.scala 182:73] + node _T_212 = bits(ld_byte_rhit_lo_hi, 1, 1) @[lsu_bus_intf.scala 182:69] + node _T_213 = bits(ld_byte_rhit_hi_hi, 1, 1) @[lsu_bus_intf.scala 182:93] + node _T_214 = or(_T_212, _T_213) @[lsu_bus_intf.scala 182:73] + node _T_215 = bits(ld_byte_rhit_lo_hi, 2, 2) @[lsu_bus_intf.scala 182:69] + node _T_216 = bits(ld_byte_rhit_hi_hi, 2, 2) @[lsu_bus_intf.scala 182:93] + node _T_217 = or(_T_215, _T_216) @[lsu_bus_intf.scala 182:73] + node _T_218 = bits(ld_byte_rhit_lo_hi, 3, 3) @[lsu_bus_intf.scala 182:69] + node _T_219 = bits(ld_byte_rhit_hi_hi, 3, 3) @[lsu_bus_intf.scala 182:93] + node _T_220 = or(_T_218, _T_219) @[lsu_bus_intf.scala 182:73] + node _T_221 = cat(_T_220, _T_217) @[Cat.scala 29:58] + node _T_222 = cat(_T_221, _T_214) @[Cat.scala 29:58] + node _T_223 = cat(_T_222, _T_211) @[Cat.scala 29:58] + ld_byte_rhit_hi <= _T_223 @[lsu_bus_intf.scala 182:27] + node _T_224 = bits(ld_byte_rhit_lo_lo, 0, 0) @[lsu_bus_intf.scala 183:79] + node _T_225 = bits(store_data_lo_r, 7, 0) @[lsu_bus_intf.scala 183:101] + node _T_226 = bits(ld_byte_rhit_hi_lo, 0, 0) @[lsu_bus_intf.scala 183:136] + node _T_227 = bits(store_data_hi_r, 7, 0) @[lsu_bus_intf.scala 183:158] + node _T_228 = mux(_T_224, _T_225, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_229 = mux(_T_226, _T_227, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_230 = or(_T_228, _T_229) @[Mux.scala 27:72] + wire _T_231 : UInt<8> @[Mux.scala 27:72] + _T_231 <= _T_230 @[Mux.scala 27:72] + node _T_232 = bits(ld_byte_rhit_lo_lo, 1, 1) @[lsu_bus_intf.scala 183:79] + node _T_233 = bits(store_data_lo_r, 15, 8) @[lsu_bus_intf.scala 183:101] + node _T_234 = bits(ld_byte_rhit_hi_lo, 1, 1) @[lsu_bus_intf.scala 183:136] + node _T_235 = bits(store_data_hi_r, 15, 8) @[lsu_bus_intf.scala 183:158] + node _T_236 = mux(_T_232, _T_233, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_237 = mux(_T_234, _T_235, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_238 = or(_T_236, _T_237) @[Mux.scala 27:72] + wire _T_239 : UInt<8> @[Mux.scala 27:72] + _T_239 <= _T_238 @[Mux.scala 27:72] + node _T_240 = bits(ld_byte_rhit_lo_lo, 2, 2) @[lsu_bus_intf.scala 183:79] + node _T_241 = bits(store_data_lo_r, 23, 16) @[lsu_bus_intf.scala 183:101] + node _T_242 = bits(ld_byte_rhit_hi_lo, 2, 2) @[lsu_bus_intf.scala 183:136] + node _T_243 = bits(store_data_hi_r, 23, 16) @[lsu_bus_intf.scala 183:158] + node _T_244 = mux(_T_240, _T_241, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_245 = mux(_T_242, _T_243, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_246 = or(_T_244, _T_245) @[Mux.scala 27:72] + wire _T_247 : UInt<8> @[Mux.scala 27:72] + _T_247 <= _T_246 @[Mux.scala 27:72] + node _T_248 = bits(ld_byte_rhit_lo_lo, 3, 3) @[lsu_bus_intf.scala 183:79] + node _T_249 = bits(store_data_lo_r, 31, 24) @[lsu_bus_intf.scala 183:101] + node _T_250 = bits(ld_byte_rhit_hi_lo, 3, 3) @[lsu_bus_intf.scala 183:136] + node _T_251 = bits(store_data_hi_r, 31, 24) @[lsu_bus_intf.scala 183:158] + node _T_252 = mux(_T_248, _T_249, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_253 = mux(_T_250, _T_251, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_254 = or(_T_252, _T_253) @[Mux.scala 27:72] + wire _T_255 : UInt<8> @[Mux.scala 27:72] + _T_255 <= _T_254 @[Mux.scala 27:72] + node _T_256 = cat(_T_255, _T_247) @[Cat.scala 29:58] + node _T_257 = cat(_T_256, _T_239) @[Cat.scala 29:58] + node _T_258 = cat(_T_257, _T_231) @[Cat.scala 29:58] + ld_fwddata_rpipe_lo <= _T_258 @[lsu_bus_intf.scala 183:27] + node _T_259 = bits(ld_byte_rhit_lo_hi, 0, 0) @[lsu_bus_intf.scala 184:79] + node _T_260 = bits(store_data_lo_r, 7, 0) @[lsu_bus_intf.scala 184:101] + node _T_261 = bits(ld_byte_rhit_hi_hi, 0, 0) @[lsu_bus_intf.scala 184:136] + node _T_262 = bits(store_data_hi_r, 7, 0) @[lsu_bus_intf.scala 184:158] + node _T_263 = mux(_T_259, _T_260, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_264 = mux(_T_261, _T_262, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_265 = or(_T_263, _T_264) @[Mux.scala 27:72] + wire _T_266 : UInt<8> @[Mux.scala 27:72] + _T_266 <= _T_265 @[Mux.scala 27:72] + node _T_267 = bits(ld_byte_rhit_lo_hi, 1, 1) @[lsu_bus_intf.scala 184:79] + node _T_268 = bits(store_data_lo_r, 15, 8) @[lsu_bus_intf.scala 184:101] + node _T_269 = bits(ld_byte_rhit_hi_hi, 1, 1) @[lsu_bus_intf.scala 184:136] + node _T_270 = bits(store_data_hi_r, 15, 8) @[lsu_bus_intf.scala 184:158] + node _T_271 = mux(_T_267, _T_268, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_272 = mux(_T_269, _T_270, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_273 = or(_T_271, _T_272) @[Mux.scala 27:72] + wire _T_274 : UInt<8> @[Mux.scala 27:72] + _T_274 <= _T_273 @[Mux.scala 27:72] + node _T_275 = bits(ld_byte_rhit_lo_hi, 2, 2) @[lsu_bus_intf.scala 184:79] + node _T_276 = bits(store_data_lo_r, 23, 16) @[lsu_bus_intf.scala 184:101] + node _T_277 = bits(ld_byte_rhit_hi_hi, 2, 2) @[lsu_bus_intf.scala 184:136] + node _T_278 = bits(store_data_hi_r, 23, 16) @[lsu_bus_intf.scala 184:158] + node _T_279 = mux(_T_275, _T_276, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_280 = mux(_T_277, _T_278, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_281 = or(_T_279, _T_280) @[Mux.scala 27:72] + wire _T_282 : UInt<8> @[Mux.scala 27:72] + _T_282 <= _T_281 @[Mux.scala 27:72] + node _T_283 = bits(ld_byte_rhit_lo_hi, 3, 3) @[lsu_bus_intf.scala 184:79] + node _T_284 = bits(store_data_lo_r, 31, 24) @[lsu_bus_intf.scala 184:101] + node _T_285 = bits(ld_byte_rhit_hi_hi, 3, 3) @[lsu_bus_intf.scala 184:136] + node _T_286 = bits(store_data_hi_r, 31, 24) @[lsu_bus_intf.scala 184:158] + node _T_287 = mux(_T_283, _T_284, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_288 = mux(_T_285, _T_286, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_289 = or(_T_287, _T_288) @[Mux.scala 27:72] + wire _T_290 : UInt<8> @[Mux.scala 27:72] + _T_290 <= _T_289 @[Mux.scala 27:72] + node _T_291 = cat(_T_290, _T_282) @[Cat.scala 29:58] + node _T_292 = cat(_T_291, _T_274) @[Cat.scala 29:58] + node _T_293 = cat(_T_292, _T_266) @[Cat.scala 29:58] + ld_fwddata_rpipe_hi <= _T_293 @[lsu_bus_intf.scala 184:27] + node _T_294 = bits(ld_byte_rhit_lo, 0, 0) @[lsu_bus_intf.scala 185:70] + node _T_295 = bits(ld_fwddata_rpipe_lo, 7, 0) @[lsu_bus_intf.scala 185:94] + node _T_296 = bits(ld_fwddata_buf_lo, 7, 0) @[lsu_bus_intf.scala 185:128] + node _T_297 = mux(_T_294, _T_295, _T_296) @[lsu_bus_intf.scala 185:54] + node _T_298 = bits(ld_byte_rhit_lo, 1, 1) @[lsu_bus_intf.scala 185:70] + node _T_299 = bits(ld_fwddata_rpipe_lo, 15, 8) @[lsu_bus_intf.scala 185:94] + node _T_300 = bits(ld_fwddata_buf_lo, 15, 8) @[lsu_bus_intf.scala 185:128] + node _T_301 = mux(_T_298, _T_299, _T_300) @[lsu_bus_intf.scala 185:54] + node _T_302 = bits(ld_byte_rhit_lo, 2, 2) @[lsu_bus_intf.scala 185:70] + node _T_303 = bits(ld_fwddata_rpipe_lo, 23, 16) @[lsu_bus_intf.scala 185:94] + node _T_304 = bits(ld_fwddata_buf_lo, 23, 16) @[lsu_bus_intf.scala 185:128] + node _T_305 = mux(_T_302, _T_303, _T_304) @[lsu_bus_intf.scala 185:54] + node _T_306 = bits(ld_byte_rhit_lo, 3, 3) @[lsu_bus_intf.scala 185:70] + node _T_307 = bits(ld_fwddata_rpipe_lo, 31, 24) @[lsu_bus_intf.scala 185:94] + node _T_308 = bits(ld_fwddata_buf_lo, 31, 24) @[lsu_bus_intf.scala 185:128] + node _T_309 = mux(_T_306, _T_307, _T_308) @[lsu_bus_intf.scala 185:54] + node _T_310 = cat(_T_309, _T_305) @[Cat.scala 29:58] + node _T_311 = cat(_T_310, _T_301) @[Cat.scala 29:58] + node _T_312 = cat(_T_311, _T_297) @[Cat.scala 29:58] + ld_fwddata_lo <= _T_312 @[lsu_bus_intf.scala 185:27] + node _T_313 = bits(ld_byte_rhit_hi, 0, 0) @[lsu_bus_intf.scala 186:70] + node _T_314 = bits(ld_fwddata_rpipe_hi, 7, 0) @[lsu_bus_intf.scala 186:94] + node _T_315 = bits(ld_fwddata_buf_hi, 7, 0) @[lsu_bus_intf.scala 186:128] + node _T_316 = mux(_T_313, _T_314, _T_315) @[lsu_bus_intf.scala 186:54] + node _T_317 = bits(ld_byte_rhit_hi, 1, 1) @[lsu_bus_intf.scala 186:70] + node _T_318 = bits(ld_fwddata_rpipe_hi, 15, 8) @[lsu_bus_intf.scala 186:94] + node _T_319 = bits(ld_fwddata_buf_hi, 15, 8) @[lsu_bus_intf.scala 186:128] + node _T_320 = mux(_T_317, _T_318, _T_319) @[lsu_bus_intf.scala 186:54] + node _T_321 = bits(ld_byte_rhit_hi, 2, 2) @[lsu_bus_intf.scala 186:70] + node _T_322 = bits(ld_fwddata_rpipe_hi, 23, 16) @[lsu_bus_intf.scala 186:94] + node _T_323 = bits(ld_fwddata_buf_hi, 23, 16) @[lsu_bus_intf.scala 186:128] + node _T_324 = mux(_T_321, _T_322, _T_323) @[lsu_bus_intf.scala 186:54] + node _T_325 = bits(ld_byte_rhit_hi, 3, 3) @[lsu_bus_intf.scala 186:70] + node _T_326 = bits(ld_fwddata_rpipe_hi, 31, 24) @[lsu_bus_intf.scala 186:94] + node _T_327 = bits(ld_fwddata_buf_hi, 31, 24) @[lsu_bus_intf.scala 186:128] + node _T_328 = mux(_T_325, _T_326, _T_327) @[lsu_bus_intf.scala 186:54] + node _T_329 = cat(_T_328, _T_324) @[Cat.scala 29:58] + node _T_330 = cat(_T_329, _T_320) @[Cat.scala 29:58] + node _T_331 = cat(_T_330, _T_316) @[Cat.scala 29:58] + ld_fwddata_hi <= _T_331 @[lsu_bus_intf.scala 186:27] + node _T_332 = bits(ld_byte_hit_lo, 0, 0) @[lsu_bus_intf.scala 187:66] + node _T_333 = bits(ldst_byteen_lo_m, 0, 0) @[lsu_bus_intf.scala 187:89] + node _T_334 = eq(_T_333, UInt<1>("h00")) @[lsu_bus_intf.scala 187:72] + node _T_335 = or(_T_332, _T_334) @[lsu_bus_intf.scala 187:70] + node _T_336 = bits(ld_byte_hit_lo, 1, 1) @[lsu_bus_intf.scala 187:66] + node _T_337 = bits(ldst_byteen_lo_m, 1, 1) @[lsu_bus_intf.scala 187:89] + node _T_338 = eq(_T_337, UInt<1>("h00")) @[lsu_bus_intf.scala 187:72] + node _T_339 = or(_T_336, _T_338) @[lsu_bus_intf.scala 187:70] + node _T_340 = bits(ld_byte_hit_lo, 2, 2) @[lsu_bus_intf.scala 187:66] + node _T_341 = bits(ldst_byteen_lo_m, 2, 2) @[lsu_bus_intf.scala 187:89] + node _T_342 = eq(_T_341, UInt<1>("h00")) @[lsu_bus_intf.scala 187:72] + node _T_343 = or(_T_340, _T_342) @[lsu_bus_intf.scala 187:70] + node _T_344 = bits(ld_byte_hit_lo, 3, 3) @[lsu_bus_intf.scala 187:66] + node _T_345 = bits(ldst_byteen_lo_m, 3, 3) @[lsu_bus_intf.scala 187:89] + node _T_346 = eq(_T_345, UInt<1>("h00")) @[lsu_bus_intf.scala 187:72] + node _T_347 = or(_T_344, _T_346) @[lsu_bus_intf.scala 187:70] + node _T_348 = and(_T_335, _T_339) @[lsu_bus_intf.scala 187:111] + node _T_349 = and(_T_348, _T_343) @[lsu_bus_intf.scala 187:111] + node _T_350 = and(_T_349, _T_347) @[lsu_bus_intf.scala 187:111] + ld_full_hit_lo_m <= _T_350 @[lsu_bus_intf.scala 187:27] + node _T_351 = bits(ld_byte_hit_hi, 0, 0) @[lsu_bus_intf.scala 188:66] + node _T_352 = bits(ldst_byteen_hi_m, 0, 0) @[lsu_bus_intf.scala 188:89] + node _T_353 = eq(_T_352, UInt<1>("h00")) @[lsu_bus_intf.scala 188:72] + node _T_354 = or(_T_351, _T_353) @[lsu_bus_intf.scala 188:70] + node _T_355 = bits(ld_byte_hit_hi, 1, 1) @[lsu_bus_intf.scala 188:66] + node _T_356 = bits(ldst_byteen_hi_m, 1, 1) @[lsu_bus_intf.scala 188:89] + node _T_357 = eq(_T_356, UInt<1>("h00")) @[lsu_bus_intf.scala 188:72] + node _T_358 = or(_T_355, _T_357) @[lsu_bus_intf.scala 188:70] + node _T_359 = bits(ld_byte_hit_hi, 2, 2) @[lsu_bus_intf.scala 188:66] + node _T_360 = bits(ldst_byteen_hi_m, 2, 2) @[lsu_bus_intf.scala 188:89] + node _T_361 = eq(_T_360, UInt<1>("h00")) @[lsu_bus_intf.scala 188:72] + node _T_362 = or(_T_359, _T_361) @[lsu_bus_intf.scala 188:70] + node _T_363 = bits(ld_byte_hit_hi, 3, 3) @[lsu_bus_intf.scala 188:66] + node _T_364 = bits(ldst_byteen_hi_m, 3, 3) @[lsu_bus_intf.scala 188:89] + node _T_365 = eq(_T_364, UInt<1>("h00")) @[lsu_bus_intf.scala 188:72] + node _T_366 = or(_T_363, _T_365) @[lsu_bus_intf.scala 188:70] + node _T_367 = and(_T_354, _T_358) @[lsu_bus_intf.scala 188:111] + node _T_368 = and(_T_367, _T_362) @[lsu_bus_intf.scala 188:111] + node _T_369 = and(_T_368, _T_366) @[lsu_bus_intf.scala 188:111] + ld_full_hit_hi_m <= _T_369 @[lsu_bus_intf.scala 188:27] + node _T_370 = and(ld_full_hit_lo_m, ld_full_hit_hi_m) @[lsu_bus_intf.scala 189:47] + node _T_371 = and(_T_370, io.lsu_busreq_m) @[lsu_bus_intf.scala 189:66] + node _T_372 = and(_T_371, io.lsu_pkt_m.bits.load) @[lsu_bus_intf.scala 189:84] + node _T_373 = eq(io.is_sideeffects_m, UInt<1>("h00")) @[lsu_bus_intf.scala 189:111] + node _T_374 = and(_T_372, _T_373) @[lsu_bus_intf.scala 189:109] + ld_full_hit_m <= _T_374 @[lsu_bus_intf.scala 189:27] + node _T_375 = bits(ld_fwddata_hi, 31, 0) @[lsu_bus_intf.scala 190:47] + node _T_376 = bits(ld_fwddata_lo, 31, 0) @[lsu_bus_intf.scala 190:68] + node _T_377 = cat(_T_375, _T_376) @[Cat.scala 29:58] + node _T_378 = bits(io.lsu_addr_m, 1, 0) @[lsu_bus_intf.scala 190:97] + node _T_379 = mul(UInt<4>("h08"), _T_378) @[lsu_bus_intf.scala 190:83] + node _T_380 = dshr(_T_377, _T_379) @[lsu_bus_intf.scala 190:76] + ld_fwddata_m <= _T_380 @[lsu_bus_intf.scala 190:27] + node _T_381 = bits(ld_fwddata_m, 31, 0) @[lsu_bus_intf.scala 191:42] + io.bus_read_data_m <= _T_381 @[lsu_bus_intf.scala 191:27] + reg _T_382 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_intf.scala 194:32] + _T_382 <= io.lsu_bus_clk_en @[lsu_bus_intf.scala 194:32] + lsu_bus_clk_en_q <= _T_382 @[lsu_bus_intf.scala 194:22] + reg _T_383 : UInt<1>, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_intf.scala 197:27] + _T_383 <= ldst_dual_d @[lsu_bus_intf.scala 197:27] + ldst_dual_m <= _T_383 @[lsu_bus_intf.scala 197:17] + reg _T_384 : UInt<1>, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_intf.scala 200:33] + _T_384 <= ldst_dual_m @[lsu_bus_intf.scala 200:33] + ldst_dual_r <= _T_384 @[lsu_bus_intf.scala 200:23] + reg _T_385 : UInt<1>, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_intf.scala 201:33] + _T_385 <= io.is_sideeffects_m @[lsu_bus_intf.scala 201:33] + is_sideeffects_r <= _T_385 @[lsu_bus_intf.scala 201:23] + reg _T_386 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<4>("h00"))) @[lsu_bus_intf.scala 202:33] + _T_386 <= ldst_byteen_m @[lsu_bus_intf.scala 202:33] + ldst_byteen_r <= _T_386 @[lsu_bus_intf.scala 202:23] + + module lsu : + input clock : Clock + input reset : AsyncReset + output io : {flip clk_override : UInt<1>, lsu_dma : {dma_lsc_ctl : {flip dma_dccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>}, dma_dccm_ctl : {flip dma_mem_addr : UInt<32>, flip dma_mem_wdata : UInt<64>, dccm_dma_rvalid : UInt<1>, dccm_dma_ecc_error : UInt<1>, dccm_dma_rtag : UInt<3>, dccm_dma_rdata : UInt<64>}, dccm_ready : UInt<1>, flip dma_mem_tag : UInt<3>}, lsu_pic : {picm_wren : UInt<1>, picm_rden : UInt<1>, picm_mken : UInt<1>, picm_rdaddr : UInt<32>, picm_wraddr : UInt<32>, picm_wr_data : UInt<32>, flip picm_rd_data : UInt<32>}, lsu_exu : {flip exu_lsu_rs1_d : UInt<32>, flip exu_lsu_rs2_d : UInt<32>}, lsu_dec : {tlu_busbuff : {lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>}, dctl_busbuff : {lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>}}, flip dccm : {flip wren : UInt<1>, flip rden : UInt<1>, flip wr_addr_lo : UInt<16>, flip wr_addr_hi : UInt<16>, flip rd_addr_lo : UInt<16>, flip rd_addr_hi : UInt<16>, flip wr_data_lo : UInt<39>, flip wr_data_hi : UInt<39>, rd_data_lo : UInt<39>, rd_data_hi : UInt<39>}, lsu_tlu : {lsu_pmu_load_external_m : UInt<1>, lsu_pmu_store_external_m : UInt<1>}, axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_i0_kill_writeb_r : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip dec_tlu_core_ecc_disable : UInt<1>, flip dec_lsu_offset_d : UInt<12>, flip lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip dec_lsu_valid_raw_d : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, lsu_result_m : UInt<32>, lsu_result_corr_r : UInt<32>, lsu_load_stall_any : UInt<1>, lsu_store_stall_any : UInt<1>, lsu_fastint_stall_any : UInt<1>, lsu_idle_any : UInt<1>, lsu_fir_addr : UInt<31>, lsu_fir_error : UInt<2>, lsu_single_ecc_error_incr : UInt<1>, lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, lsu_pmu_misaligned_m : UInt<1>, lsu_trigger_match_m : UInt<4>, flip lsu_bus_clk_en : UInt<1>, flip scan_mode : UInt<1>, flip free_clk : Clock} + + wire dma_dccm_wdata : UInt<64> + dma_dccm_wdata <= UInt<64>("h00") + wire dma_dccm_wdata_lo : UInt<32> + dma_dccm_wdata_lo <= UInt<32>("h00") + wire dma_dccm_wdata_hi : UInt<32> + dma_dccm_wdata_hi <= UInt<32>("h00") + wire dma_mem_tag_m : UInt<3> + dma_mem_tag_m <= UInt<3>("h00") + wire lsu_raw_fwd_lo_r : UInt<1> + lsu_raw_fwd_lo_r <= UInt<1>("h00") + wire lsu_raw_fwd_hi_r : UInt<1> + lsu_raw_fwd_hi_r <= UInt<1>("h00") + inst lsu_lsc_ctl of lsu_lsc_ctl @[lsu.scala 60:30] + lsu_lsc_ctl.clock <= clock + lsu_lsc_ctl.reset <= reset + io.lsu_result_m <= lsu_lsc_ctl.io.lsu_result_m @[lsu.scala 61:19] + io.lsu_result_corr_r <= lsu_lsc_ctl.io.lsu_result_corr_r @[lsu.scala 62:24] + inst dccm_ctl of lsu_dccm_ctl @[lsu.scala 63:30] + dccm_ctl.clock <= clock + dccm_ctl.reset <= reset + inst stbuf of lsu_stbuf @[lsu.scala 64:30] + stbuf.clock <= clock + stbuf.reset <= reset + inst ecc of lsu_ecc @[lsu.scala 65:30] + ecc.clock <= clock + ecc.reset <= reset + inst trigger of lsu_trigger @[lsu.scala 66:30] + trigger.clock <= clock + trigger.reset <= reset + inst clkdomain of lsu_clkdomain @[lsu.scala 67:30] + clkdomain.clock <= clock + clkdomain.reset <= reset + inst bus_intf of lsu_bus_intf @[lsu.scala 68:30] + bus_intf.clock <= clock + bus_intf.reset <= reset + node lsu_raw_fwd_lo_m = orr(stbuf.io.stbuf_fwdbyteen_lo_m) @[lsu.scala 70:56] + node lsu_raw_fwd_hi_m = orr(stbuf.io.stbuf_fwdbyteen_hi_m) @[lsu.scala 71:56] + node _T = or(stbuf.io.lsu_stbuf_full_any, bus_intf.io.lsu_bus_buffer_full_any) @[lsu.scala 74:57] + node _T_1 = or(_T, dccm_ctl.io.ld_single_ecc_error_r_ff) @[lsu.scala 74:95] + io.lsu_store_stall_any <= _T_1 @[lsu.scala 74:26] + node _T_2 = or(bus_intf.io.lsu_bus_buffer_full_any, dccm_ctl.io.ld_single_ecc_error_r_ff) @[lsu.scala 75:64] + io.lsu_load_stall_any <= _T_2 @[lsu.scala 75:25] + io.lsu_fastint_stall_any <= dccm_ctl.io.ld_single_ecc_error_r @[lsu.scala 76:28] + node _T_3 = eq(lsu_lsc_ctl.io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu.scala 81:58] + node _T_4 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, _T_3) @[lsu.scala 81:56] + node _T_5 = or(lsu_lsc_ctl.io.addr_in_dccm_m, lsu_lsc_ctl.io.addr_in_pic_m) @[lsu.scala 81:126] + node _T_6 = and(_T_4, _T_5) @[lsu.scala 81:93] + node ldst_nodma_mtor = and(_T_6, lsu_lsc_ctl.io.lsu_pkt_m.bits.store) @[lsu.scala 81:158] + node _T_7 = or(io.dec_lsu_valid_raw_d, ldst_nodma_mtor) @[lsu.scala 82:53] + node _T_8 = or(_T_7, dccm_ctl.io.ld_single_ecc_error_r_ff) @[lsu.scala 82:71] + node _T_9 = eq(_T_8, UInt<1>("h00")) @[lsu.scala 82:28] + io.lsu_dma.dccm_ready <= _T_9 @[lsu.scala 82:25] + node _T_10 = and(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.lsu_dma.dma_lsc_ctl.dma_mem_write) @[lsu.scala 83:58] + node dma_dccm_wen = and(_T_10, lsu_lsc_ctl.io.addr_in_dccm_d) @[lsu.scala 83:97] + node _T_11 = and(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.lsu_dma.dma_lsc_ctl.dma_mem_write) @[lsu.scala 84:58] + node dma_pic_wen = and(_T_11, lsu_lsc_ctl.io.addr_in_pic_d) @[lsu.scala 84:97] + node _T_12 = bits(io.lsu_dma.dma_lsc_ctl.dma_mem_addr, 2, 0) @[lsu.scala 85:100] + node _T_13 = cat(_T_12, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_14 = dshr(io.lsu_dma.dma_lsc_ctl.dma_mem_wdata, _T_13) @[lsu.scala 85:58] + dma_dccm_wdata <= _T_14 @[lsu.scala 85:18] + node _T_15 = bits(dma_dccm_wdata, 63, 32) @[lsu.scala 86:38] + dma_dccm_wdata_hi <= _T_15 @[lsu.scala 86:21] + node _T_16 = bits(dma_dccm_wdata, 31, 0) @[lsu.scala 87:38] + dma_dccm_wdata_lo <= _T_16 @[lsu.scala 87:21] + node _T_17 = eq(lsu_lsc_ctl.io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu.scala 96:58] + node _T_18 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, _T_17) @[lsu.scala 96:56] + node _T_19 = eq(lsu_lsc_ctl.io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu.scala 96:130] + node _T_20 = and(lsu_lsc_ctl.io.lsu_pkt_r.valid, _T_19) @[lsu.scala 96:128] + node _T_21 = or(_T_18, _T_20) @[lsu.scala 96:94] + node _T_22 = eq(_T_21, UInt<1>("h00")) @[lsu.scala 96:22] + node _T_23 = and(_T_22, bus_intf.io.lsu_bus_buffer_empty_any) @[lsu.scala 96:167] + node _T_24 = and(_T_23, bus_intf.io.lsu_bus_idle_any) @[lsu.scala 96:206] + io.lsu_idle_any <= _T_24 @[lsu.scala 96:19] + node _T_25 = and(lsu_lsc_ctl.io.lsu_pkt_r.valid, lsu_lsc_ctl.io.lsu_pkt_r.bits.store) @[lsu.scala 98:61] + node _T_26 = and(_T_25, lsu_lsc_ctl.io.addr_in_dccm_r) @[lsu.scala 98:99] + node _T_27 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[lsu.scala 98:133] + node _T_28 = and(_T_26, _T_27) @[lsu.scala 98:131] + node _T_29 = eq(lsu_lsc_ctl.io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu.scala 98:144] + node store_stbuf_reqvld_r = and(_T_28, _T_29) @[lsu.scala 98:142] + node _T_30 = or(lsu_lsc_ctl.io.lsu_pkt_m.bits.load, lsu_lsc_ctl.io.lsu_pkt_m.bits.store) @[lsu.scala 100:90] + node _T_31 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, _T_30) @[lsu.scala 100:52] + node _T_32 = or(lsu_lsc_ctl.io.addr_in_dccm_m, lsu_lsc_ctl.io.addr_in_pic_m) @[lsu.scala 100:162] + node lsu_cmpen_m = and(_T_31, _T_32) @[lsu.scala 100:129] + node _T_33 = or(lsu_lsc_ctl.io.lsu_pkt_m.bits.load, lsu_lsc_ctl.io.lsu_pkt_m.bits.store) @[lsu.scala 102:92] + node _T_34 = and(_T_33, lsu_lsc_ctl.io.addr_external_m) @[lsu.scala 102:131] + node _T_35 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, _T_34) @[lsu.scala 102:53] + node _T_36 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[lsu.scala 102:167] + node _T_37 = and(_T_35, _T_36) @[lsu.scala 102:165] + node _T_38 = eq(lsu_lsc_ctl.io.lsu_exc_m, UInt<1>("h00")) @[lsu.scala 102:181] + node _T_39 = and(_T_37, _T_38) @[lsu.scala 102:179] + node _T_40 = eq(lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int, UInt<1>("h00")) @[lsu.scala 102:209] + node lsu_busreq_m = and(_T_39, _T_40) @[lsu.scala 102:207] + node _T_41 = bits(lsu_lsc_ctl.io.lsu_addr_m, 0, 0) @[lsu.scala 104:127] + node _T_42 = and(lsu_lsc_ctl.io.lsu_pkt_m.bits.half, _T_41) @[lsu.scala 104:100] + node _T_43 = bits(lsu_lsc_ctl.io.lsu_addr_m, 1, 0) @[lsu.scala 104:197] + node _T_44 = orr(_T_43) @[lsu.scala 104:203] + node _T_45 = and(lsu_lsc_ctl.io.lsu_pkt_m.bits.word, _T_44) @[lsu.scala 104:170] + node _T_46 = or(_T_42, _T_45) @[lsu.scala 104:132] + node _T_47 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, _T_46) @[lsu.scala 104:61] + io.lsu_pmu_misaligned_m <= _T_47 @[lsu.scala 104:27] + node _T_48 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, lsu_lsc_ctl.io.lsu_pkt_m.bits.load) @[lsu.scala 105:73] + node _T_49 = and(_T_48, lsu_lsc_ctl.io.addr_external_m) @[lsu.scala 105:110] + io.lsu_tlu.lsu_pmu_load_external_m <= _T_49 @[lsu.scala 105:39] + node _T_50 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, lsu_lsc_ctl.io.lsu_pkt_m.bits.store) @[lsu.scala 106:73] + node _T_51 = and(_T_50, lsu_lsc_ctl.io.addr_external_m) @[lsu.scala 106:111] + io.lsu_tlu.lsu_pmu_store_external_m <= _T_51 @[lsu.scala 106:39] + lsu_lsc_ctl.io.lsu_c1_m_clk <= clkdomain.io.lsu_c1_m_clk @[lsu.scala 110:46] + lsu_lsc_ctl.io.lsu_c1_r_clk <= clkdomain.io.lsu_c1_r_clk @[lsu.scala 111:46] + lsu_lsc_ctl.io.lsu_c2_m_clk <= clkdomain.io.lsu_c2_m_clk @[lsu.scala 112:46] + lsu_lsc_ctl.io.lsu_c2_r_clk <= clkdomain.io.lsu_c2_r_clk @[lsu.scala 113:46] + lsu_lsc_ctl.io.lsu_store_c1_m_clk <= clkdomain.io.lsu_store_c1_m_clk @[lsu.scala 114:46] + lsu_lsc_ctl.io.lsu_ld_data_r <= dccm_ctl.io.lsu_ld_data_r @[lsu.scala 115:46] + lsu_lsc_ctl.io.lsu_ld_data_corr_r <= dccm_ctl.io.lsu_ld_data_corr_r @[lsu.scala 116:46] + lsu_lsc_ctl.io.lsu_single_ecc_error_r <= ecc.io.lsu_single_ecc_error_r @[lsu.scala 117:46] + lsu_lsc_ctl.io.lsu_double_ecc_error_r <= ecc.io.lsu_double_ecc_error_r @[lsu.scala 118:46] + lsu_lsc_ctl.io.lsu_ld_data_m <= dccm_ctl.io.lsu_ld_data_m @[lsu.scala 119:46] + lsu_lsc_ctl.io.lsu_single_ecc_error_m <= ecc.io.lsu_single_ecc_error_m @[lsu.scala 120:46] + lsu_lsc_ctl.io.lsu_double_ecc_error_m <= ecc.io.lsu_double_ecc_error_m @[lsu.scala 121:46] + lsu_lsc_ctl.io.flush_m_up <= io.dec_tlu_flush_lower_r @[lsu.scala 122:46] + lsu_lsc_ctl.io.flush_r <= io.dec_tlu_i0_kill_writeb_r @[lsu.scala 123:46] + lsu_lsc_ctl.io.lsu_exu.exu_lsu_rs2_d <= io.lsu_exu.exu_lsu_rs2_d @[lsu.scala 124:46] + lsu_lsc_ctl.io.lsu_exu.exu_lsu_rs1_d <= io.lsu_exu.exu_lsu_rs1_d @[lsu.scala 124:46] + lsu_lsc_ctl.io.lsu_p.bits.store_data_bypass_m <= io.lsu_p.bits.store_data_bypass_m @[lsu.scala 125:46] + lsu_lsc_ctl.io.lsu_p.bits.load_ldst_bypass_d <= io.lsu_p.bits.load_ldst_bypass_d @[lsu.scala 125:46] + lsu_lsc_ctl.io.lsu_p.bits.store_data_bypass_d <= io.lsu_p.bits.store_data_bypass_d @[lsu.scala 125:46] + lsu_lsc_ctl.io.lsu_p.bits.dma <= io.lsu_p.bits.dma @[lsu.scala 125:46] + lsu_lsc_ctl.io.lsu_p.bits.unsign <= io.lsu_p.bits.unsign @[lsu.scala 125:46] + lsu_lsc_ctl.io.lsu_p.bits.store <= io.lsu_p.bits.store @[lsu.scala 125:46] + lsu_lsc_ctl.io.lsu_p.bits.load <= io.lsu_p.bits.load @[lsu.scala 125:46] + lsu_lsc_ctl.io.lsu_p.bits.dword <= io.lsu_p.bits.dword @[lsu.scala 125:46] + lsu_lsc_ctl.io.lsu_p.bits.word <= io.lsu_p.bits.word @[lsu.scala 125:46] + lsu_lsc_ctl.io.lsu_p.bits.half <= io.lsu_p.bits.half @[lsu.scala 125:46] + lsu_lsc_ctl.io.lsu_p.bits.by <= io.lsu_p.bits.by @[lsu.scala 125:46] + lsu_lsc_ctl.io.lsu_p.bits.fast_int <= io.lsu_p.bits.fast_int @[lsu.scala 125:46] + lsu_lsc_ctl.io.lsu_p.valid <= io.lsu_p.valid @[lsu.scala 125:46] + lsu_lsc_ctl.io.dec_lsu_valid_raw_d <= io.dec_lsu_valid_raw_d @[lsu.scala 126:46] + lsu_lsc_ctl.io.dec_lsu_offset_d <= io.dec_lsu_offset_d @[lsu.scala 127:46] + lsu_lsc_ctl.io.picm_mask_data_m <= dccm_ctl.io.picm_mask_data_m @[lsu.scala 128:46] + lsu_lsc_ctl.io.bus_read_data_m <= bus_intf.io.bus_read_data_m @[lsu.scala 129:46] + lsu_lsc_ctl.io.dma_lsc_ctl.dma_mem_wdata <= io.lsu_dma.dma_lsc_ctl.dma_mem_wdata @[lsu.scala 130:38] + lsu_lsc_ctl.io.dma_lsc_ctl.dma_mem_write <= io.lsu_dma.dma_lsc_ctl.dma_mem_write @[lsu.scala 130:38] + lsu_lsc_ctl.io.dma_lsc_ctl.dma_mem_sz <= io.lsu_dma.dma_lsc_ctl.dma_mem_sz @[lsu.scala 130:38] + lsu_lsc_ctl.io.dma_lsc_ctl.dma_mem_addr <= io.lsu_dma.dma_lsc_ctl.dma_mem_addr @[lsu.scala 130:38] + lsu_lsc_ctl.io.dma_lsc_ctl.dma_dccm_req <= io.lsu_dma.dma_lsc_ctl.dma_dccm_req @[lsu.scala 130:38] + lsu_lsc_ctl.io.dec_tlu_mrac_ff <= io.dec_tlu_mrac_ff @[lsu.scala 131:46] + lsu_lsc_ctl.io.scan_mode <= io.scan_mode @[lsu.scala 132:46] + io.lsu_single_ecc_error_incr <= lsu_lsc_ctl.io.lsu_single_ecc_error_incr @[lsu.scala 135:49] + io.lsu_error_pkt_r.bits.addr <= lsu_lsc_ctl.io.lsu_error_pkt_r.bits.addr @[lsu.scala 136:49] + io.lsu_error_pkt_r.bits.mscause <= lsu_lsc_ctl.io.lsu_error_pkt_r.bits.mscause @[lsu.scala 136:49] + io.lsu_error_pkt_r.bits.exc_type <= lsu_lsc_ctl.io.lsu_error_pkt_r.bits.exc_type @[lsu.scala 136:49] + io.lsu_error_pkt_r.bits.inst_type <= lsu_lsc_ctl.io.lsu_error_pkt_r.bits.inst_type @[lsu.scala 136:49] + io.lsu_error_pkt_r.bits.single_ecc_error <= lsu_lsc_ctl.io.lsu_error_pkt_r.bits.single_ecc_error @[lsu.scala 136:49] + io.lsu_error_pkt_r.valid <= lsu_lsc_ctl.io.lsu_error_pkt_r.valid @[lsu.scala 136:49] + io.lsu_fir_addr <= lsu_lsc_ctl.io.lsu_fir_addr @[lsu.scala 137:49] + io.lsu_fir_error <= lsu_lsc_ctl.io.lsu_fir_error @[lsu.scala 138:49] + dccm_ctl.io.lsu_c2_m_clk <= clkdomain.io.lsu_c2_m_clk @[lsu.scala 141:46] + dccm_ctl.io.lsu_c2_r_clk <= clkdomain.io.lsu_c2_r_clk @[lsu.scala 142:46] + dccm_ctl.io.lsu_free_c2_clk <= clkdomain.io.lsu_free_c2_clk @[lsu.scala 143:46] + dccm_ctl.io.lsu_c1_r_clk <= clkdomain.io.lsu_c1_r_clk @[lsu.scala 144:46] + dccm_ctl.io.lsu_store_c1_r_clk <= clkdomain.io.lsu_store_c1_r_clk @[lsu.scala 145:46] + dccm_ctl.io.lsu_pkt_d.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_d.bits.store_data_bypass_m @[lsu.scala 146:46] + dccm_ctl.io.lsu_pkt_d.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_d.bits.load_ldst_bypass_d @[lsu.scala 146:46] + dccm_ctl.io.lsu_pkt_d.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_d.bits.store_data_bypass_d @[lsu.scala 146:46] + dccm_ctl.io.lsu_pkt_d.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_d.bits.dma @[lsu.scala 146:46] + dccm_ctl.io.lsu_pkt_d.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_d.bits.unsign @[lsu.scala 146:46] + dccm_ctl.io.lsu_pkt_d.bits.store <= lsu_lsc_ctl.io.lsu_pkt_d.bits.store @[lsu.scala 146:46] + dccm_ctl.io.lsu_pkt_d.bits.load <= lsu_lsc_ctl.io.lsu_pkt_d.bits.load @[lsu.scala 146:46] + dccm_ctl.io.lsu_pkt_d.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_d.bits.dword @[lsu.scala 146:46] + dccm_ctl.io.lsu_pkt_d.bits.word <= lsu_lsc_ctl.io.lsu_pkt_d.bits.word @[lsu.scala 146:46] + dccm_ctl.io.lsu_pkt_d.bits.half <= lsu_lsc_ctl.io.lsu_pkt_d.bits.half @[lsu.scala 146:46] + dccm_ctl.io.lsu_pkt_d.bits.by <= lsu_lsc_ctl.io.lsu_pkt_d.bits.by @[lsu.scala 146:46] + dccm_ctl.io.lsu_pkt_d.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_d.bits.fast_int @[lsu.scala 146:46] + dccm_ctl.io.lsu_pkt_d.valid <= lsu_lsc_ctl.io.lsu_pkt_d.valid @[lsu.scala 146:46] + dccm_ctl.io.lsu_pkt_m.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_m @[lsu.scala 147:46] + dccm_ctl.io.lsu_pkt_m.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu.scala 147:46] + dccm_ctl.io.lsu_pkt_m.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_d @[lsu.scala 147:46] + dccm_ctl.io.lsu_pkt_m.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dma @[lsu.scala 147:46] + dccm_ctl.io.lsu_pkt_m.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_m.bits.unsign @[lsu.scala 147:46] + dccm_ctl.io.lsu_pkt_m.bits.store <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store @[lsu.scala 147:46] + dccm_ctl.io.lsu_pkt_m.bits.load <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load @[lsu.scala 147:46] + dccm_ctl.io.lsu_pkt_m.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dword @[lsu.scala 147:46] + dccm_ctl.io.lsu_pkt_m.bits.word <= lsu_lsc_ctl.io.lsu_pkt_m.bits.word @[lsu.scala 147:46] + dccm_ctl.io.lsu_pkt_m.bits.half <= lsu_lsc_ctl.io.lsu_pkt_m.bits.half @[lsu.scala 147:46] + dccm_ctl.io.lsu_pkt_m.bits.by <= lsu_lsc_ctl.io.lsu_pkt_m.bits.by @[lsu.scala 147:46] + dccm_ctl.io.lsu_pkt_m.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int @[lsu.scala 147:46] + dccm_ctl.io.lsu_pkt_m.valid <= lsu_lsc_ctl.io.lsu_pkt_m.valid @[lsu.scala 147:46] + dccm_ctl.io.lsu_pkt_r.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store_data_bypass_m @[lsu.scala 148:46] + dccm_ctl.io.lsu_pkt_r.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.bits.load_ldst_bypass_d @[lsu.scala 148:46] + dccm_ctl.io.lsu_pkt_r.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store_data_bypass_d @[lsu.scala 148:46] + dccm_ctl.io.lsu_pkt_r.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_r.bits.dma @[lsu.scala 148:46] + dccm_ctl.io.lsu_pkt_r.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_r.bits.unsign @[lsu.scala 148:46] + dccm_ctl.io.lsu_pkt_r.bits.store <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store @[lsu.scala 148:46] + dccm_ctl.io.lsu_pkt_r.bits.load <= lsu_lsc_ctl.io.lsu_pkt_r.bits.load @[lsu.scala 148:46] + dccm_ctl.io.lsu_pkt_r.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_r.bits.dword @[lsu.scala 148:46] + dccm_ctl.io.lsu_pkt_r.bits.word <= lsu_lsc_ctl.io.lsu_pkt_r.bits.word @[lsu.scala 148:46] + dccm_ctl.io.lsu_pkt_r.bits.half <= lsu_lsc_ctl.io.lsu_pkt_r.bits.half @[lsu.scala 148:46] + dccm_ctl.io.lsu_pkt_r.bits.by <= lsu_lsc_ctl.io.lsu_pkt_r.bits.by @[lsu.scala 148:46] + dccm_ctl.io.lsu_pkt_r.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_r.bits.fast_int @[lsu.scala 148:46] + dccm_ctl.io.lsu_pkt_r.valid <= lsu_lsc_ctl.io.lsu_pkt_r.valid @[lsu.scala 148:46] + dccm_ctl.io.addr_in_dccm_d <= lsu_lsc_ctl.io.addr_in_dccm_d @[lsu.scala 149:46] + dccm_ctl.io.addr_in_dccm_m <= lsu_lsc_ctl.io.addr_in_dccm_m @[lsu.scala 150:46] + dccm_ctl.io.addr_in_dccm_r <= lsu_lsc_ctl.io.addr_in_dccm_r @[lsu.scala 151:46] + dccm_ctl.io.addr_in_pic_d <= lsu_lsc_ctl.io.addr_in_pic_d @[lsu.scala 152:46] + dccm_ctl.io.addr_in_pic_m <= lsu_lsc_ctl.io.addr_in_pic_m @[lsu.scala 153:46] + dccm_ctl.io.addr_in_pic_r <= lsu_lsc_ctl.io.addr_in_pic_r @[lsu.scala 154:46] + dccm_ctl.io.lsu_raw_fwd_lo_r <= lsu_raw_fwd_lo_r @[lsu.scala 155:46] + dccm_ctl.io.lsu_raw_fwd_hi_r <= lsu_raw_fwd_hi_r @[lsu.scala 156:46] + dccm_ctl.io.lsu_commit_r <= lsu_lsc_ctl.io.lsu_commit_r @[lsu.scala 157:46] + dccm_ctl.io.lsu_addr_d <= lsu_lsc_ctl.io.lsu_addr_d @[lsu.scala 158:46] + dccm_ctl.io.lsu_addr_m <= lsu_lsc_ctl.io.lsu_addr_m @[lsu.scala 159:46] + dccm_ctl.io.lsu_addr_r <= lsu_lsc_ctl.io.lsu_addr_r @[lsu.scala 160:46] + dccm_ctl.io.end_addr_d <= lsu_lsc_ctl.io.end_addr_d @[lsu.scala 161:46] + dccm_ctl.io.end_addr_m <= lsu_lsc_ctl.io.end_addr_m @[lsu.scala 162:46] + dccm_ctl.io.end_addr_r <= lsu_lsc_ctl.io.end_addr_r @[lsu.scala 163:46] + dccm_ctl.io.stbuf_reqvld_any <= stbuf.io.stbuf_reqvld_any @[lsu.scala 164:46] + dccm_ctl.io.stbuf_addr_any <= stbuf.io.stbuf_addr_any @[lsu.scala 165:46] + dccm_ctl.io.stbuf_data_any <= stbuf.io.stbuf_data_any @[lsu.scala 166:46] + dccm_ctl.io.stbuf_ecc_any <= ecc.io.stbuf_ecc_any @[lsu.scala 167:46] + dccm_ctl.io.stbuf_fwddata_hi_m <= stbuf.io.stbuf_fwddata_hi_m @[lsu.scala 168:46] + dccm_ctl.io.stbuf_fwddata_lo_m <= stbuf.io.stbuf_fwddata_lo_m @[lsu.scala 169:46] + dccm_ctl.io.stbuf_fwdbyteen_lo_m <= stbuf.io.stbuf_fwdbyteen_lo_m @[lsu.scala 170:46] + dccm_ctl.io.stbuf_fwdbyteen_hi_m <= stbuf.io.stbuf_fwdbyteen_hi_m @[lsu.scala 171:46] + dccm_ctl.io.lsu_double_ecc_error_r <= ecc.io.lsu_double_ecc_error_r @[lsu.scala 172:46] + dccm_ctl.io.single_ecc_error_hi_r <= ecc.io.single_ecc_error_hi_r @[lsu.scala 173:46] + dccm_ctl.io.single_ecc_error_lo_r <= ecc.io.single_ecc_error_lo_r @[lsu.scala 174:46] + dccm_ctl.io.sec_data_hi_r <= ecc.io.sec_data_hi_r @[lsu.scala 175:46] + dccm_ctl.io.sec_data_lo_r <= ecc.io.sec_data_lo_r @[lsu.scala 176:46] + dccm_ctl.io.sec_data_hi_r_ff <= ecc.io.sec_data_hi_r_ff @[lsu.scala 177:46] + dccm_ctl.io.sec_data_lo_r_ff <= ecc.io.sec_data_lo_r_ff @[lsu.scala 178:46] + dccm_ctl.io.sec_data_ecc_hi_r_ff <= ecc.io.sec_data_ecc_hi_r_ff @[lsu.scala 179:46] + dccm_ctl.io.sec_data_ecc_lo_r_ff <= ecc.io.sec_data_ecc_lo_r_ff @[lsu.scala 180:46] + dccm_ctl.io.lsu_double_ecc_error_m <= ecc.io.lsu_double_ecc_error_m @[lsu.scala 181:46] + dccm_ctl.io.sec_data_hi_m <= ecc.io.sec_data_hi_m @[lsu.scala 182:46] + dccm_ctl.io.sec_data_lo_m <= ecc.io.sec_data_lo_m @[lsu.scala 183:46] + dccm_ctl.io.store_data_m <= lsu_lsc_ctl.io.store_data_m @[lsu.scala 184:46] + dccm_ctl.io.dma_dccm_wen <= dma_dccm_wen @[lsu.scala 185:46] + dccm_ctl.io.dma_pic_wen <= dma_pic_wen @[lsu.scala 186:46] + dccm_ctl.io.dma_mem_tag_m <= dma_mem_tag_m @[lsu.scala 187:46] + dccm_ctl.io.dma_dccm_wdata_lo <= dma_dccm_wdata_lo @[lsu.scala 188:46] + dccm_ctl.io.dma_dccm_wdata_hi <= dma_dccm_wdata_hi @[lsu.scala 189:46] + dccm_ctl.io.dma_dccm_wdata_ecc_hi <= ecc.io.dma_dccm_wdata_ecc_hi @[lsu.scala 190:46] + dccm_ctl.io.dma_dccm_wdata_ecc_lo <= ecc.io.dma_dccm_wdata_ecc_lo @[lsu.scala 191:46] + dccm_ctl.io.scan_mode <= io.scan_mode @[lsu.scala 192:46] + io.lsu_dma.dma_dccm_ctl.dccm_dma_rdata <= dccm_ctl.io.dma_dccm_ctl.dccm_dma_rdata @[lsu.scala 194:27] + io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag <= dccm_ctl.io.dma_dccm_ctl.dccm_dma_rtag @[lsu.scala 194:27] + io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error <= dccm_ctl.io.dma_dccm_ctl.dccm_dma_ecc_error @[lsu.scala 194:27] + io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid <= dccm_ctl.io.dma_dccm_ctl.dccm_dma_rvalid @[lsu.scala 194:27] + dccm_ctl.io.dma_dccm_ctl.dma_mem_wdata <= io.lsu_dma.dma_dccm_ctl.dma_mem_wdata @[lsu.scala 194:27] + dccm_ctl.io.dma_dccm_ctl.dma_mem_addr <= io.lsu_dma.dma_dccm_ctl.dma_mem_addr @[lsu.scala 194:27] + dccm_ctl.io.dccm.rd_data_hi <= io.dccm.rd_data_hi @[lsu.scala 195:11] + dccm_ctl.io.dccm.rd_data_lo <= io.dccm.rd_data_lo @[lsu.scala 195:11] + io.dccm.wr_data_hi <= dccm_ctl.io.dccm.wr_data_hi @[lsu.scala 195:11] + io.dccm.wr_data_lo <= dccm_ctl.io.dccm.wr_data_lo @[lsu.scala 195:11] + io.dccm.rd_addr_hi <= dccm_ctl.io.dccm.rd_addr_hi @[lsu.scala 195:11] + io.dccm.rd_addr_lo <= dccm_ctl.io.dccm.rd_addr_lo @[lsu.scala 195:11] + io.dccm.wr_addr_hi <= dccm_ctl.io.dccm.wr_addr_hi @[lsu.scala 195:11] + io.dccm.wr_addr_lo <= dccm_ctl.io.dccm.wr_addr_lo @[lsu.scala 195:11] + io.dccm.rden <= dccm_ctl.io.dccm.rden @[lsu.scala 195:11] + io.dccm.wren <= dccm_ctl.io.dccm.wren @[lsu.scala 195:11] + dccm_ctl.io.lsu_pic.picm_rd_data <= io.lsu_pic.picm_rd_data @[lsu.scala 196:14] + io.lsu_pic.picm_wr_data <= dccm_ctl.io.lsu_pic.picm_wr_data @[lsu.scala 196:14] + io.lsu_pic.picm_wraddr <= dccm_ctl.io.lsu_pic.picm_wraddr @[lsu.scala 196:14] + io.lsu_pic.picm_rdaddr <= dccm_ctl.io.lsu_pic.picm_rdaddr @[lsu.scala 196:14] + io.lsu_pic.picm_mken <= dccm_ctl.io.lsu_pic.picm_mken @[lsu.scala 196:14] + io.lsu_pic.picm_rden <= dccm_ctl.io.lsu_pic.picm_rden @[lsu.scala 196:14] + io.lsu_pic.picm_wren <= dccm_ctl.io.lsu_pic.picm_wren @[lsu.scala 196:14] + stbuf.io.lsu_c1_m_clk <= clkdomain.io.lsu_c1_m_clk @[lsu.scala 199:49] + stbuf.io.lsu_c1_r_clk <= clkdomain.io.lsu_c1_r_clk @[lsu.scala 200:48] + stbuf.io.lsu_stbuf_c1_clk <= clkdomain.io.lsu_stbuf_c1_clk @[lsu.scala 201:54] + stbuf.io.lsu_free_c2_clk <= clkdomain.io.lsu_free_c2_clk @[lsu.scala 202:54] + stbuf.io.lsu_pkt_m.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_m @[lsu.scala 203:48] + stbuf.io.lsu_pkt_m.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu.scala 203:48] + stbuf.io.lsu_pkt_m.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_d @[lsu.scala 203:48] + stbuf.io.lsu_pkt_m.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dma @[lsu.scala 203:48] + stbuf.io.lsu_pkt_m.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_m.bits.unsign @[lsu.scala 203:48] + stbuf.io.lsu_pkt_m.bits.store <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store @[lsu.scala 203:48] + stbuf.io.lsu_pkt_m.bits.load <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load @[lsu.scala 203:48] + stbuf.io.lsu_pkt_m.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dword @[lsu.scala 203:48] + stbuf.io.lsu_pkt_m.bits.word <= lsu_lsc_ctl.io.lsu_pkt_m.bits.word @[lsu.scala 203:48] + stbuf.io.lsu_pkt_m.bits.half <= lsu_lsc_ctl.io.lsu_pkt_m.bits.half @[lsu.scala 203:48] + stbuf.io.lsu_pkt_m.bits.by <= lsu_lsc_ctl.io.lsu_pkt_m.bits.by @[lsu.scala 203:48] + stbuf.io.lsu_pkt_m.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int @[lsu.scala 203:48] + stbuf.io.lsu_pkt_m.valid <= lsu_lsc_ctl.io.lsu_pkt_m.valid @[lsu.scala 203:48] + stbuf.io.lsu_pkt_r.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store_data_bypass_m @[lsu.scala 204:48] + stbuf.io.lsu_pkt_r.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.bits.load_ldst_bypass_d @[lsu.scala 204:48] + stbuf.io.lsu_pkt_r.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store_data_bypass_d @[lsu.scala 204:48] + stbuf.io.lsu_pkt_r.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_r.bits.dma @[lsu.scala 204:48] + stbuf.io.lsu_pkt_r.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_r.bits.unsign @[lsu.scala 204:48] + stbuf.io.lsu_pkt_r.bits.store <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store @[lsu.scala 204:48] + stbuf.io.lsu_pkt_r.bits.load <= lsu_lsc_ctl.io.lsu_pkt_r.bits.load @[lsu.scala 204:48] + stbuf.io.lsu_pkt_r.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_r.bits.dword @[lsu.scala 204:48] + stbuf.io.lsu_pkt_r.bits.word <= lsu_lsc_ctl.io.lsu_pkt_r.bits.word @[lsu.scala 204:48] + stbuf.io.lsu_pkt_r.bits.half <= lsu_lsc_ctl.io.lsu_pkt_r.bits.half @[lsu.scala 204:48] + stbuf.io.lsu_pkt_r.bits.by <= lsu_lsc_ctl.io.lsu_pkt_r.bits.by @[lsu.scala 204:48] + stbuf.io.lsu_pkt_r.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_r.bits.fast_int @[lsu.scala 204:48] + stbuf.io.lsu_pkt_r.valid <= lsu_lsc_ctl.io.lsu_pkt_r.valid @[lsu.scala 204:48] + stbuf.io.store_stbuf_reqvld_r <= store_stbuf_reqvld_r @[lsu.scala 205:48] + stbuf.io.lsu_commit_r <= lsu_lsc_ctl.io.lsu_commit_r @[lsu.scala 206:49] + stbuf.io.dec_lsu_valid_raw_d <= io.dec_lsu_valid_raw_d @[lsu.scala 207:49] + stbuf.io.store_data_hi_r <= dccm_ctl.io.store_data_hi_r @[lsu.scala 208:62] + stbuf.io.store_data_lo_r <= dccm_ctl.io.store_data_lo_r @[lsu.scala 209:62] + stbuf.io.store_datafn_hi_r <= dccm_ctl.io.store_datafn_hi_r @[lsu.scala 210:49] + stbuf.io.store_datafn_lo_r <= dccm_ctl.io.store_datafn_lo_r @[lsu.scala 211:56] + stbuf.io.lsu_stbuf_commit_any <= dccm_ctl.io.lsu_stbuf_commit_any @[lsu.scala 212:52] + stbuf.io.lsu_addr_d <= lsu_lsc_ctl.io.lsu_addr_d @[lsu.scala 213:64] + stbuf.io.lsu_addr_m <= lsu_lsc_ctl.io.lsu_addr_m @[lsu.scala 214:64] + stbuf.io.lsu_addr_r <= lsu_lsc_ctl.io.lsu_addr_r @[lsu.scala 215:64] + stbuf.io.end_addr_d <= lsu_lsc_ctl.io.end_addr_d @[lsu.scala 216:64] + stbuf.io.end_addr_m <= lsu_lsc_ctl.io.end_addr_m @[lsu.scala 217:64] + stbuf.io.end_addr_r <= lsu_lsc_ctl.io.end_addr_r @[lsu.scala 218:64] + stbuf.io.addr_in_dccm_m <= lsu_lsc_ctl.io.addr_in_dccm_m @[lsu.scala 219:49] + stbuf.io.addr_in_dccm_r <= lsu_lsc_ctl.io.addr_in_dccm_r @[lsu.scala 220:56] + stbuf.io.lsu_cmpen_m <= lsu_cmpen_m @[lsu.scala 221:54] + stbuf.io.scan_mode <= io.scan_mode @[lsu.scala 222:49] + ecc.io.lsu_c2_r_clk <= clkdomain.io.lsu_c2_r_clk @[lsu.scala 226:52] + ecc.io.lsu_pkt_m.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_m @[lsu.scala 227:52] + ecc.io.lsu_pkt_m.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu.scala 227:52] + ecc.io.lsu_pkt_m.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_d @[lsu.scala 227:52] + ecc.io.lsu_pkt_m.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dma @[lsu.scala 227:52] + ecc.io.lsu_pkt_m.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_m.bits.unsign @[lsu.scala 227:52] + ecc.io.lsu_pkt_m.bits.store <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store @[lsu.scala 227:52] + ecc.io.lsu_pkt_m.bits.load <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load @[lsu.scala 227:52] + ecc.io.lsu_pkt_m.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dword @[lsu.scala 227:52] + ecc.io.lsu_pkt_m.bits.word <= lsu_lsc_ctl.io.lsu_pkt_m.bits.word @[lsu.scala 227:52] + ecc.io.lsu_pkt_m.bits.half <= lsu_lsc_ctl.io.lsu_pkt_m.bits.half @[lsu.scala 227:52] + ecc.io.lsu_pkt_m.bits.by <= lsu_lsc_ctl.io.lsu_pkt_m.bits.by @[lsu.scala 227:52] + ecc.io.lsu_pkt_m.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int @[lsu.scala 227:52] + ecc.io.lsu_pkt_m.valid <= lsu_lsc_ctl.io.lsu_pkt_m.valid @[lsu.scala 227:52] + ecc.io.lsu_pkt_r.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store_data_bypass_m @[lsu.scala 228:52] + ecc.io.lsu_pkt_r.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.bits.load_ldst_bypass_d @[lsu.scala 228:52] + ecc.io.lsu_pkt_r.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store_data_bypass_d @[lsu.scala 228:52] + ecc.io.lsu_pkt_r.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_r.bits.dma @[lsu.scala 228:52] + ecc.io.lsu_pkt_r.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_r.bits.unsign @[lsu.scala 228:52] + ecc.io.lsu_pkt_r.bits.store <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store @[lsu.scala 228:52] + ecc.io.lsu_pkt_r.bits.load <= lsu_lsc_ctl.io.lsu_pkt_r.bits.load @[lsu.scala 228:52] + ecc.io.lsu_pkt_r.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_r.bits.dword @[lsu.scala 228:52] + ecc.io.lsu_pkt_r.bits.word <= lsu_lsc_ctl.io.lsu_pkt_r.bits.word @[lsu.scala 228:52] + ecc.io.lsu_pkt_r.bits.half <= lsu_lsc_ctl.io.lsu_pkt_r.bits.half @[lsu.scala 228:52] + ecc.io.lsu_pkt_r.bits.by <= lsu_lsc_ctl.io.lsu_pkt_r.bits.by @[lsu.scala 228:52] + ecc.io.lsu_pkt_r.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_r.bits.fast_int @[lsu.scala 228:52] + ecc.io.lsu_pkt_r.valid <= lsu_lsc_ctl.io.lsu_pkt_r.valid @[lsu.scala 228:52] + ecc.io.stbuf_data_any <= stbuf.io.stbuf_data_any @[lsu.scala 229:54] + ecc.io.dec_tlu_core_ecc_disable <= io.dec_tlu_core_ecc_disable @[lsu.scala 230:50] + ecc.io.lsu_dccm_rden_r <= dccm_ctl.io.lsu_dccm_rden_r @[lsu.scala 231:56] + ecc.io.addr_in_dccm_r <= lsu_lsc_ctl.io.addr_in_dccm_r @[lsu.scala 232:50] + ecc.io.lsu_addr_r <= lsu_lsc_ctl.io.lsu_addr_r @[lsu.scala 233:58] + ecc.io.end_addr_r <= lsu_lsc_ctl.io.end_addr_r @[lsu.scala 234:58] + ecc.io.lsu_addr_m <= lsu_lsc_ctl.io.lsu_addr_m @[lsu.scala 235:58] + ecc.io.end_addr_m <= lsu_lsc_ctl.io.end_addr_m @[lsu.scala 236:58] + ecc.io.dccm_rdata_hi_r <= dccm_ctl.io.dccm_rdata_hi_r @[lsu.scala 237:54] + ecc.io.dccm_rdata_lo_r <= dccm_ctl.io.dccm_rdata_lo_r @[lsu.scala 238:54] + ecc.io.dccm_rdata_hi_m <= dccm_ctl.io.dccm_rdata_hi_m @[lsu.scala 239:54] + ecc.io.dccm_rdata_lo_m <= dccm_ctl.io.dccm_rdata_lo_m @[lsu.scala 240:54] + ecc.io.dccm_data_ecc_hi_r <= dccm_ctl.io.dccm_data_ecc_hi_r @[lsu.scala 241:50] + ecc.io.dccm_data_ecc_lo_r <= dccm_ctl.io.dccm_data_ecc_lo_r @[lsu.scala 242:50] + ecc.io.dccm_data_ecc_hi_m <= dccm_ctl.io.dccm_data_ecc_hi_m @[lsu.scala 243:50] + ecc.io.dccm_data_ecc_lo_m <= dccm_ctl.io.dccm_data_ecc_lo_m @[lsu.scala 244:50] + ecc.io.ld_single_ecc_error_r <= dccm_ctl.io.ld_single_ecc_error_r @[lsu.scala 245:50] + ecc.io.ld_single_ecc_error_r_ff <= dccm_ctl.io.ld_single_ecc_error_r_ff @[lsu.scala 246:50] + ecc.io.lsu_dccm_rden_m <= dccm_ctl.io.lsu_dccm_rden_m @[lsu.scala 247:50] + ecc.io.addr_in_dccm_m <= lsu_lsc_ctl.io.addr_in_dccm_m @[lsu.scala 248:50] + ecc.io.dma_dccm_wen <= dma_dccm_wen @[lsu.scala 249:50] + ecc.io.dma_dccm_wdata_lo <= dma_dccm_wdata_lo @[lsu.scala 250:50] + ecc.io.dma_dccm_wdata_hi <= dma_dccm_wdata_hi @[lsu.scala 251:50] + ecc.io.scan_mode <= io.scan_mode @[lsu.scala 252:50] + trigger.io.trigger_pkt_any[0].tdata2 <= io.trigger_pkt_any[0].tdata2 @[lsu.scala 256:50] + trigger.io.trigger_pkt_any[0].m <= io.trigger_pkt_any[0].m @[lsu.scala 256:50] + trigger.io.trigger_pkt_any[0].execute <= io.trigger_pkt_any[0].execute @[lsu.scala 256:50] + trigger.io.trigger_pkt_any[0].load <= io.trigger_pkt_any[0].load @[lsu.scala 256:50] + trigger.io.trigger_pkt_any[0].store <= io.trigger_pkt_any[0].store @[lsu.scala 256:50] + trigger.io.trigger_pkt_any[0].match_pkt <= io.trigger_pkt_any[0].match_pkt @[lsu.scala 256:50] + trigger.io.trigger_pkt_any[0].select <= io.trigger_pkt_any[0].select @[lsu.scala 256:50] + trigger.io.trigger_pkt_any[1].tdata2 <= io.trigger_pkt_any[1].tdata2 @[lsu.scala 256:50] + trigger.io.trigger_pkt_any[1].m <= io.trigger_pkt_any[1].m @[lsu.scala 256:50] + trigger.io.trigger_pkt_any[1].execute <= io.trigger_pkt_any[1].execute @[lsu.scala 256:50] + trigger.io.trigger_pkt_any[1].load <= io.trigger_pkt_any[1].load @[lsu.scala 256:50] + trigger.io.trigger_pkt_any[1].store <= io.trigger_pkt_any[1].store @[lsu.scala 256:50] + trigger.io.trigger_pkt_any[1].match_pkt <= io.trigger_pkt_any[1].match_pkt @[lsu.scala 256:50] + trigger.io.trigger_pkt_any[1].select <= io.trigger_pkt_any[1].select @[lsu.scala 256:50] + trigger.io.trigger_pkt_any[2].tdata2 <= io.trigger_pkt_any[2].tdata2 @[lsu.scala 256:50] + trigger.io.trigger_pkt_any[2].m <= io.trigger_pkt_any[2].m @[lsu.scala 256:50] + trigger.io.trigger_pkt_any[2].execute <= io.trigger_pkt_any[2].execute @[lsu.scala 256:50] + trigger.io.trigger_pkt_any[2].load <= io.trigger_pkt_any[2].load @[lsu.scala 256:50] + trigger.io.trigger_pkt_any[2].store <= io.trigger_pkt_any[2].store @[lsu.scala 256:50] + trigger.io.trigger_pkt_any[2].match_pkt <= io.trigger_pkt_any[2].match_pkt @[lsu.scala 256:50] + trigger.io.trigger_pkt_any[2].select <= io.trigger_pkt_any[2].select @[lsu.scala 256:50] + trigger.io.trigger_pkt_any[3].tdata2 <= io.trigger_pkt_any[3].tdata2 @[lsu.scala 256:50] + trigger.io.trigger_pkt_any[3].m <= io.trigger_pkt_any[3].m @[lsu.scala 256:50] + trigger.io.trigger_pkt_any[3].execute <= io.trigger_pkt_any[3].execute @[lsu.scala 256:50] + trigger.io.trigger_pkt_any[3].load <= io.trigger_pkt_any[3].load @[lsu.scala 256:50] + trigger.io.trigger_pkt_any[3].store <= io.trigger_pkt_any[3].store @[lsu.scala 256:50] + trigger.io.trigger_pkt_any[3].match_pkt <= io.trigger_pkt_any[3].match_pkt @[lsu.scala 256:50] + trigger.io.trigger_pkt_any[3].select <= io.trigger_pkt_any[3].select @[lsu.scala 256:50] + trigger.io.lsu_pkt_m.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_m @[lsu.scala 257:50] + trigger.io.lsu_pkt_m.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu.scala 257:50] + trigger.io.lsu_pkt_m.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_d @[lsu.scala 257:50] + trigger.io.lsu_pkt_m.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dma @[lsu.scala 257:50] + trigger.io.lsu_pkt_m.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_m.bits.unsign @[lsu.scala 257:50] + trigger.io.lsu_pkt_m.bits.store <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store @[lsu.scala 257:50] + trigger.io.lsu_pkt_m.bits.load <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load @[lsu.scala 257:50] + trigger.io.lsu_pkt_m.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dword @[lsu.scala 257:50] + trigger.io.lsu_pkt_m.bits.word <= lsu_lsc_ctl.io.lsu_pkt_m.bits.word @[lsu.scala 257:50] + trigger.io.lsu_pkt_m.bits.half <= lsu_lsc_ctl.io.lsu_pkt_m.bits.half @[lsu.scala 257:50] + trigger.io.lsu_pkt_m.bits.by <= lsu_lsc_ctl.io.lsu_pkt_m.bits.by @[lsu.scala 257:50] + trigger.io.lsu_pkt_m.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int @[lsu.scala 257:50] + trigger.io.lsu_pkt_m.valid <= lsu_lsc_ctl.io.lsu_pkt_m.valid @[lsu.scala 257:50] + trigger.io.lsu_addr_m <= lsu_lsc_ctl.io.lsu_addr_m @[lsu.scala 258:50] + trigger.io.store_data_m <= lsu_lsc_ctl.io.store_data_m @[lsu.scala 259:50] + io.lsu_trigger_match_m <= trigger.io.lsu_trigger_match_m @[lsu.scala 261:50] + clkdomain.io.free_clk <= io.free_clk @[lsu.scala 265:50] + clkdomain.io.clk_override <= io.clk_override @[lsu.scala 266:50] + clkdomain.io.addr_in_dccm_m <= lsu_lsc_ctl.io.addr_in_dccm_m @[lsu.scala 267:50] + clkdomain.io.dma_dccm_req <= io.lsu_dma.dma_lsc_ctl.dma_dccm_req @[lsu.scala 268:50] + clkdomain.io.ldst_stbuf_reqvld_r <= stbuf.io.ldst_stbuf_reqvld_r @[lsu.scala 269:50] + clkdomain.io.stbuf_reqvld_any <= stbuf.io.stbuf_reqvld_any @[lsu.scala 270:50] + clkdomain.io.stbuf_reqvld_flushed_any <= stbuf.io.stbuf_reqvld_flushed_any @[lsu.scala 271:50] + clkdomain.io.lsu_busreq_r <= bus_intf.io.lsu_busreq_r @[lsu.scala 272:50] + clkdomain.io.lsu_bus_buffer_pend_any <= bus_intf.io.lsu_bus_buffer_pend_any @[lsu.scala 273:50] + clkdomain.io.lsu_bus_buffer_empty_any <= bus_intf.io.lsu_bus_buffer_empty_any @[lsu.scala 274:50] + clkdomain.io.lsu_stbuf_empty_any <= stbuf.io.lsu_stbuf_empty_any @[lsu.scala 275:50] + clkdomain.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[lsu.scala 276:50] + clkdomain.io.lsu_p.bits.store_data_bypass_m <= io.lsu_p.bits.store_data_bypass_m @[lsu.scala 277:50] + clkdomain.io.lsu_p.bits.load_ldst_bypass_d <= io.lsu_p.bits.load_ldst_bypass_d @[lsu.scala 277:50] + clkdomain.io.lsu_p.bits.store_data_bypass_d <= io.lsu_p.bits.store_data_bypass_d @[lsu.scala 277:50] + clkdomain.io.lsu_p.bits.dma <= io.lsu_p.bits.dma @[lsu.scala 277:50] + clkdomain.io.lsu_p.bits.unsign <= io.lsu_p.bits.unsign @[lsu.scala 277:50] + clkdomain.io.lsu_p.bits.store <= io.lsu_p.bits.store @[lsu.scala 277:50] + clkdomain.io.lsu_p.bits.load <= io.lsu_p.bits.load @[lsu.scala 277:50] + clkdomain.io.lsu_p.bits.dword <= io.lsu_p.bits.dword @[lsu.scala 277:50] + clkdomain.io.lsu_p.bits.word <= io.lsu_p.bits.word @[lsu.scala 277:50] + clkdomain.io.lsu_p.bits.half <= io.lsu_p.bits.half @[lsu.scala 277:50] + clkdomain.io.lsu_p.bits.by <= io.lsu_p.bits.by @[lsu.scala 277:50] + clkdomain.io.lsu_p.bits.fast_int <= io.lsu_p.bits.fast_int @[lsu.scala 277:50] + clkdomain.io.lsu_p.valid <= io.lsu_p.valid @[lsu.scala 277:50] + clkdomain.io.lsu_pkt_d.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_d.bits.store_data_bypass_m @[lsu.scala 278:50] + clkdomain.io.lsu_pkt_d.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_d.bits.load_ldst_bypass_d @[lsu.scala 278:50] + clkdomain.io.lsu_pkt_d.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_d.bits.store_data_bypass_d @[lsu.scala 278:50] + clkdomain.io.lsu_pkt_d.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_d.bits.dma @[lsu.scala 278:50] + clkdomain.io.lsu_pkt_d.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_d.bits.unsign @[lsu.scala 278:50] + clkdomain.io.lsu_pkt_d.bits.store <= lsu_lsc_ctl.io.lsu_pkt_d.bits.store @[lsu.scala 278:50] + clkdomain.io.lsu_pkt_d.bits.load <= lsu_lsc_ctl.io.lsu_pkt_d.bits.load @[lsu.scala 278:50] + clkdomain.io.lsu_pkt_d.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_d.bits.dword @[lsu.scala 278:50] + clkdomain.io.lsu_pkt_d.bits.word <= lsu_lsc_ctl.io.lsu_pkt_d.bits.word @[lsu.scala 278:50] + clkdomain.io.lsu_pkt_d.bits.half <= lsu_lsc_ctl.io.lsu_pkt_d.bits.half @[lsu.scala 278:50] + clkdomain.io.lsu_pkt_d.bits.by <= lsu_lsc_ctl.io.lsu_pkt_d.bits.by @[lsu.scala 278:50] + clkdomain.io.lsu_pkt_d.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_d.bits.fast_int @[lsu.scala 278:50] + clkdomain.io.lsu_pkt_d.valid <= lsu_lsc_ctl.io.lsu_pkt_d.valid @[lsu.scala 278:50] + clkdomain.io.lsu_pkt_m.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_m @[lsu.scala 279:50] + clkdomain.io.lsu_pkt_m.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu.scala 279:50] + clkdomain.io.lsu_pkt_m.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_d @[lsu.scala 279:50] + clkdomain.io.lsu_pkt_m.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dma @[lsu.scala 279:50] + clkdomain.io.lsu_pkt_m.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_m.bits.unsign @[lsu.scala 279:50] + clkdomain.io.lsu_pkt_m.bits.store <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store @[lsu.scala 279:50] + clkdomain.io.lsu_pkt_m.bits.load <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load @[lsu.scala 279:50] + clkdomain.io.lsu_pkt_m.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dword @[lsu.scala 279:50] + clkdomain.io.lsu_pkt_m.bits.word <= lsu_lsc_ctl.io.lsu_pkt_m.bits.word @[lsu.scala 279:50] + clkdomain.io.lsu_pkt_m.bits.half <= lsu_lsc_ctl.io.lsu_pkt_m.bits.half @[lsu.scala 279:50] + clkdomain.io.lsu_pkt_m.bits.by <= lsu_lsc_ctl.io.lsu_pkt_m.bits.by @[lsu.scala 279:50] + clkdomain.io.lsu_pkt_m.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int @[lsu.scala 279:50] + clkdomain.io.lsu_pkt_m.valid <= lsu_lsc_ctl.io.lsu_pkt_m.valid @[lsu.scala 279:50] + clkdomain.io.lsu_pkt_r.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store_data_bypass_m @[lsu.scala 280:50] + clkdomain.io.lsu_pkt_r.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.bits.load_ldst_bypass_d @[lsu.scala 280:50] + clkdomain.io.lsu_pkt_r.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store_data_bypass_d @[lsu.scala 280:50] + clkdomain.io.lsu_pkt_r.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_r.bits.dma @[lsu.scala 280:50] + clkdomain.io.lsu_pkt_r.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_r.bits.unsign @[lsu.scala 280:50] + clkdomain.io.lsu_pkt_r.bits.store <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store @[lsu.scala 280:50] + clkdomain.io.lsu_pkt_r.bits.load <= lsu_lsc_ctl.io.lsu_pkt_r.bits.load @[lsu.scala 280:50] + clkdomain.io.lsu_pkt_r.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_r.bits.dword @[lsu.scala 280:50] + clkdomain.io.lsu_pkt_r.bits.word <= lsu_lsc_ctl.io.lsu_pkt_r.bits.word @[lsu.scala 280:50] + clkdomain.io.lsu_pkt_r.bits.half <= lsu_lsc_ctl.io.lsu_pkt_r.bits.half @[lsu.scala 280:50] + clkdomain.io.lsu_pkt_r.bits.by <= lsu_lsc_ctl.io.lsu_pkt_r.bits.by @[lsu.scala 280:50] + clkdomain.io.lsu_pkt_r.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_r.bits.fast_int @[lsu.scala 280:50] + clkdomain.io.lsu_pkt_r.valid <= lsu_lsc_ctl.io.lsu_pkt_r.valid @[lsu.scala 280:50] + clkdomain.io.scan_mode <= io.scan_mode @[lsu.scala 281:50] + bus_intf.io.scan_mode <= io.scan_mode @[lsu.scala 285:49] + io.lsu_dec.tlu_busbuff.lsu_imprecise_error_addr_any <= bus_intf.io.tlu_busbuff.lsu_imprecise_error_addr_any @[lsu.scala 286:26] + io.lsu_dec.tlu_busbuff.lsu_imprecise_error_store_any <= bus_intf.io.tlu_busbuff.lsu_imprecise_error_store_any @[lsu.scala 286:26] + io.lsu_dec.tlu_busbuff.lsu_imprecise_error_load_any <= bus_intf.io.tlu_busbuff.lsu_imprecise_error_load_any @[lsu.scala 286:26] + bus_intf.io.tlu_busbuff.dec_tlu_sideeffect_posted_disable <= io.lsu_dec.tlu_busbuff.dec_tlu_sideeffect_posted_disable @[lsu.scala 286:26] + bus_intf.io.tlu_busbuff.dec_tlu_wb_coalescing_disable <= io.lsu_dec.tlu_busbuff.dec_tlu_wb_coalescing_disable @[lsu.scala 286:26] + bus_intf.io.tlu_busbuff.dec_tlu_external_ldfwd_disable <= io.lsu_dec.tlu_busbuff.dec_tlu_external_ldfwd_disable @[lsu.scala 286:26] + io.lsu_dec.tlu_busbuff.lsu_pmu_bus_busy <= bus_intf.io.tlu_busbuff.lsu_pmu_bus_busy @[lsu.scala 286:26] + io.lsu_dec.tlu_busbuff.lsu_pmu_bus_error <= bus_intf.io.tlu_busbuff.lsu_pmu_bus_error @[lsu.scala 286:26] + io.lsu_dec.tlu_busbuff.lsu_pmu_bus_misaligned <= bus_intf.io.tlu_busbuff.lsu_pmu_bus_misaligned @[lsu.scala 286:26] + io.lsu_dec.tlu_busbuff.lsu_pmu_bus_trxn <= bus_intf.io.tlu_busbuff.lsu_pmu_bus_trxn @[lsu.scala 286:26] + bus_intf.io.lsu_c1_m_clk <= clkdomain.io.lsu_c1_m_clk @[lsu.scala 287:49] + bus_intf.io.lsu_c1_r_clk <= clkdomain.io.lsu_c1_r_clk @[lsu.scala 288:49] + bus_intf.io.lsu_c2_r_clk <= clkdomain.io.lsu_c2_r_clk @[lsu.scala 289:49] + bus_intf.io.lsu_bus_ibuf_c1_clk <= clkdomain.io.lsu_bus_ibuf_c1_clk @[lsu.scala 290:49] + bus_intf.io.lsu_bus_obuf_c1_clk <= clkdomain.io.lsu_bus_obuf_c1_clk @[lsu.scala 291:49] + bus_intf.io.lsu_bus_buf_c1_clk <= clkdomain.io.lsu_bus_buf_c1_clk @[lsu.scala 292:49] + bus_intf.io.lsu_free_c2_clk <= clkdomain.io.lsu_free_c2_clk @[lsu.scala 293:49] + bus_intf.io.free_clk <= io.free_clk @[lsu.scala 294:49] + bus_intf.io.lsu_busm_clk <= clkdomain.io.lsu_busm_clk @[lsu.scala 295:49] + bus_intf.io.dec_lsu_valid_raw_d <= io.dec_lsu_valid_raw_d @[lsu.scala 296:49] + bus_intf.io.lsu_busreq_m <= lsu_busreq_m @[lsu.scala 297:49] + bus_intf.io.lsu_addr_d <= lsu_lsc_ctl.io.lsu_addr_d @[lsu.scala 298:49] + bus_intf.io.lsu_addr_m <= lsu_lsc_ctl.io.lsu_addr_m @[lsu.scala 299:49] + bus_intf.io.lsu_addr_r <= lsu_lsc_ctl.io.lsu_addr_r @[lsu.scala 300:49] + bus_intf.io.end_addr_d <= lsu_lsc_ctl.io.end_addr_d @[lsu.scala 301:49] + bus_intf.io.end_addr_m <= lsu_lsc_ctl.io.end_addr_m @[lsu.scala 302:49] + bus_intf.io.end_addr_r <= lsu_lsc_ctl.io.end_addr_r @[lsu.scala 303:49] + bus_intf.io.store_data_r <= dccm_ctl.io.store_data_r @[lsu.scala 304:49] + bus_intf.io.lsu_pkt_m.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_m @[lsu.scala 305:49] + bus_intf.io.lsu_pkt_m.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu.scala 305:49] + bus_intf.io.lsu_pkt_m.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_d @[lsu.scala 305:49] + bus_intf.io.lsu_pkt_m.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dma @[lsu.scala 305:49] + bus_intf.io.lsu_pkt_m.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_m.bits.unsign @[lsu.scala 305:49] + bus_intf.io.lsu_pkt_m.bits.store <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store @[lsu.scala 305:49] + bus_intf.io.lsu_pkt_m.bits.load <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load @[lsu.scala 305:49] + bus_intf.io.lsu_pkt_m.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dword @[lsu.scala 305:49] + bus_intf.io.lsu_pkt_m.bits.word <= lsu_lsc_ctl.io.lsu_pkt_m.bits.word @[lsu.scala 305:49] + bus_intf.io.lsu_pkt_m.bits.half <= lsu_lsc_ctl.io.lsu_pkt_m.bits.half @[lsu.scala 305:49] + bus_intf.io.lsu_pkt_m.bits.by <= lsu_lsc_ctl.io.lsu_pkt_m.bits.by @[lsu.scala 305:49] + bus_intf.io.lsu_pkt_m.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int @[lsu.scala 305:49] + bus_intf.io.lsu_pkt_m.valid <= lsu_lsc_ctl.io.lsu_pkt_m.valid @[lsu.scala 305:49] + bus_intf.io.lsu_pkt_r.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store_data_bypass_m @[lsu.scala 306:49] + bus_intf.io.lsu_pkt_r.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.bits.load_ldst_bypass_d @[lsu.scala 306:49] + bus_intf.io.lsu_pkt_r.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store_data_bypass_d @[lsu.scala 306:49] + bus_intf.io.lsu_pkt_r.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_r.bits.dma @[lsu.scala 306:49] + bus_intf.io.lsu_pkt_r.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_r.bits.unsign @[lsu.scala 306:49] + bus_intf.io.lsu_pkt_r.bits.store <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store @[lsu.scala 306:49] + bus_intf.io.lsu_pkt_r.bits.load <= lsu_lsc_ctl.io.lsu_pkt_r.bits.load @[lsu.scala 306:49] + bus_intf.io.lsu_pkt_r.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_r.bits.dword @[lsu.scala 306:49] + bus_intf.io.lsu_pkt_r.bits.word <= lsu_lsc_ctl.io.lsu_pkt_r.bits.word @[lsu.scala 306:49] + bus_intf.io.lsu_pkt_r.bits.half <= lsu_lsc_ctl.io.lsu_pkt_r.bits.half @[lsu.scala 306:49] + bus_intf.io.lsu_pkt_r.bits.by <= lsu_lsc_ctl.io.lsu_pkt_r.bits.by @[lsu.scala 306:49] + bus_intf.io.lsu_pkt_r.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_r.bits.fast_int @[lsu.scala 306:49] + bus_intf.io.lsu_pkt_r.valid <= lsu_lsc_ctl.io.lsu_pkt_r.valid @[lsu.scala 306:49] + bus_intf.io.dec_tlu_force_halt <= io.dec_tlu_force_halt @[lsu.scala 307:49] + bus_intf.io.lsu_commit_r <= lsu_lsc_ctl.io.lsu_commit_r @[lsu.scala 308:49] + bus_intf.io.is_sideeffects_m <= lsu_lsc_ctl.io.is_sideeffects_m @[lsu.scala 309:49] + bus_intf.io.flush_m_up <= io.dec_tlu_flush_lower_r @[lsu.scala 310:49] + bus_intf.io.flush_r <= io.dec_tlu_i0_kill_writeb_r @[lsu.scala 311:49] + io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data <= bus_intf.io.dctl_busbuff.lsu_nonblock_load_data @[lsu.scala 313:27] + io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_tag <= bus_intf.io.dctl_busbuff.lsu_nonblock_load_data_tag @[lsu.scala 313:27] + io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_error <= bus_intf.io.dctl_busbuff.lsu_nonblock_load_data_error @[lsu.scala 313:27] + io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_valid <= bus_intf.io.dctl_busbuff.lsu_nonblock_load_data_valid @[lsu.scala 313:27] + io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_tag_r <= bus_intf.io.dctl_busbuff.lsu_nonblock_load_inv_tag_r @[lsu.scala 313:27] + io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_r <= bus_intf.io.dctl_busbuff.lsu_nonblock_load_inv_r @[lsu.scala 313:27] + io.lsu_dec.dctl_busbuff.lsu_nonblock_load_tag_m <= bus_intf.io.dctl_busbuff.lsu_nonblock_load_tag_m @[lsu.scala 313:27] + io.lsu_dec.dctl_busbuff.lsu_nonblock_load_valid_m <= bus_intf.io.dctl_busbuff.lsu_nonblock_load_valid_m @[lsu.scala 313:27] + bus_intf.io.axi.r.bits.last <= io.axi.r.bits.last @[lsu.scala 314:49] + bus_intf.io.axi.r.bits.resp <= io.axi.r.bits.resp @[lsu.scala 314:49] + bus_intf.io.axi.r.bits.data <= io.axi.r.bits.data @[lsu.scala 314:49] + bus_intf.io.axi.r.bits.id <= io.axi.r.bits.id @[lsu.scala 314:49] + bus_intf.io.axi.r.valid <= io.axi.r.valid @[lsu.scala 314:49] + io.axi.r.ready <= bus_intf.io.axi.r.ready @[lsu.scala 314:49] + io.axi.ar.bits.qos <= bus_intf.io.axi.ar.bits.qos @[lsu.scala 314:49] + io.axi.ar.bits.prot <= bus_intf.io.axi.ar.bits.prot @[lsu.scala 314:49] + io.axi.ar.bits.cache <= bus_intf.io.axi.ar.bits.cache @[lsu.scala 314:49] + io.axi.ar.bits.lock <= bus_intf.io.axi.ar.bits.lock @[lsu.scala 314:49] + io.axi.ar.bits.burst <= bus_intf.io.axi.ar.bits.burst @[lsu.scala 314:49] + io.axi.ar.bits.size <= bus_intf.io.axi.ar.bits.size @[lsu.scala 314:49] + io.axi.ar.bits.len <= bus_intf.io.axi.ar.bits.len @[lsu.scala 314:49] + io.axi.ar.bits.region <= bus_intf.io.axi.ar.bits.region @[lsu.scala 314:49] + io.axi.ar.bits.addr <= bus_intf.io.axi.ar.bits.addr @[lsu.scala 314:49] + io.axi.ar.bits.id <= bus_intf.io.axi.ar.bits.id @[lsu.scala 314:49] + io.axi.ar.valid <= bus_intf.io.axi.ar.valid @[lsu.scala 314:49] + bus_intf.io.axi.ar.ready <= io.axi.ar.ready @[lsu.scala 314:49] + bus_intf.io.axi.b.bits.id <= io.axi.b.bits.id @[lsu.scala 314:49] + bus_intf.io.axi.b.bits.resp <= io.axi.b.bits.resp @[lsu.scala 314:49] + bus_intf.io.axi.b.valid <= io.axi.b.valid @[lsu.scala 314:49] + io.axi.b.ready <= bus_intf.io.axi.b.ready @[lsu.scala 314:49] + io.axi.w.bits.last <= bus_intf.io.axi.w.bits.last @[lsu.scala 314:49] + io.axi.w.bits.strb <= bus_intf.io.axi.w.bits.strb @[lsu.scala 314:49] + io.axi.w.bits.data <= bus_intf.io.axi.w.bits.data @[lsu.scala 314:49] + io.axi.w.valid <= bus_intf.io.axi.w.valid @[lsu.scala 314:49] + bus_intf.io.axi.w.ready <= io.axi.w.ready @[lsu.scala 314:49] + io.axi.aw.bits.qos <= bus_intf.io.axi.aw.bits.qos @[lsu.scala 314:49] + io.axi.aw.bits.prot <= bus_intf.io.axi.aw.bits.prot @[lsu.scala 314:49] + io.axi.aw.bits.cache <= bus_intf.io.axi.aw.bits.cache @[lsu.scala 314:49] + io.axi.aw.bits.lock <= bus_intf.io.axi.aw.bits.lock @[lsu.scala 314:49] + io.axi.aw.bits.burst <= bus_intf.io.axi.aw.bits.burst @[lsu.scala 314:49] + io.axi.aw.bits.size <= bus_intf.io.axi.aw.bits.size @[lsu.scala 314:49] + io.axi.aw.bits.len <= bus_intf.io.axi.aw.bits.len @[lsu.scala 314:49] + io.axi.aw.bits.region <= bus_intf.io.axi.aw.bits.region @[lsu.scala 314:49] + io.axi.aw.bits.addr <= bus_intf.io.axi.aw.bits.addr @[lsu.scala 314:49] + io.axi.aw.bits.id <= bus_intf.io.axi.aw.bits.id @[lsu.scala 314:49] + io.axi.aw.valid <= bus_intf.io.axi.aw.valid @[lsu.scala 314:49] + bus_intf.io.axi.aw.ready <= io.axi.aw.ready @[lsu.scala 314:49] + bus_intf.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[lsu.scala 315:49] + reg _T_52 : UInt, clkdomain.io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu.scala 317:67] + _T_52 <= io.lsu_dma.dma_mem_tag @[lsu.scala 317:67] + dma_mem_tag_m <= _T_52 @[lsu.scala 317:57] + reg _T_53 : UInt<1>, clkdomain.io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu.scala 318:67] + _T_53 <= lsu_raw_fwd_hi_m @[lsu.scala 318:67] + lsu_raw_fwd_hi_r <= _T_53 @[lsu.scala 318:57] + reg _T_54 : UInt<1>, clkdomain.io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu.scala 319:67] + _T_54 <= lsu_raw_fwd_lo_m @[lsu.scala 319:67] + lsu_raw_fwd_lo_r <= _T_54 @[lsu.scala 319:57] + diff --git a/lsu.v b/lsu.v new file mode 100644 index 00000000..cc5a287f --- /dev/null +++ b/lsu.v @@ -0,0 +1,11868 @@ +module lsu_addrcheck( + input reset, + input io_lsu_c2_m_clk, + input [31:0] io_start_addr_d, + input [31:0] io_end_addr_d, + input io_lsu_pkt_d_valid, + input io_lsu_pkt_d_bits_fast_int, + input io_lsu_pkt_d_bits_by, + input io_lsu_pkt_d_bits_half, + input io_lsu_pkt_d_bits_word, + input io_lsu_pkt_d_bits_load, + input io_lsu_pkt_d_bits_store, + input io_lsu_pkt_d_bits_dma, + input [31:0] io_dec_tlu_mrac_ff, + input [3:0] io_rs1_region_d, + output io_is_sideeffects_m, + output io_addr_in_dccm_d, + output io_addr_in_pic_d, + output io_addr_external_d, + output io_access_fault_d, + output io_misaligned_fault_d, + output [3:0] io_exc_mscause_d, + output io_fir_dccm_access_error_d, + output io_fir_nondccm_access_error_d +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; +`endif // RANDOMIZE_REG_INIT + wire start_addr_in_dccm_region_d = io_start_addr_d[31:28] == 4'hf; // @[lib.scala 356:49] + wire start_addr_in_dccm_d = io_start_addr_d[31:16] == 16'hf004; // @[lib.scala 361:39] + wire end_addr_in_dccm_region_d = io_end_addr_d[31:28] == 4'hf; // @[lib.scala 356:49] + wire end_addr_in_dccm_d = io_end_addr_d[31:16] == 16'hf004; // @[lib.scala 361:39] + wire addr_in_iccm = io_start_addr_d[31:28] == 4'he; // @[lsu_addrcheck.scala 42:45] + wire start_addr_in_pic_d = io_start_addr_d[31:15] == 17'h1e018; // @[lib.scala 361:39] + wire end_addr_in_pic_d = io_end_addr_d[31:15] == 17'h1e018; // @[lib.scala 361:39] + wire start_addr_dccm_or_pic = start_addr_in_dccm_region_d | start_addr_in_dccm_region_d; // @[lsu_addrcheck.scala 54:60] + wire _T_17 = io_rs1_region_d == 4'hf; // @[lsu_addrcheck.scala 55:54] + wire base_reg_dccm_or_pic = _T_17 | _T_17; // @[lsu_addrcheck.scala 55:73] + wire [4:0] csr_idx = {io_start_addr_d[31:28],1'h1}; // @[Cat.scala 29:58] + wire [31:0] _T_25 = io_dec_tlu_mrac_ff >> csr_idx; // @[lsu_addrcheck.scala 61:50] + wire _T_28 = start_addr_dccm_or_pic | addr_in_iccm; // @[lsu_addrcheck.scala 61:121] + wire _T_29 = ~_T_28; // @[lsu_addrcheck.scala 61:62] + wire _T_30 = _T_25[0] & _T_29; // @[lsu_addrcheck.scala 61:60] + wire _T_31 = _T_30 & io_lsu_pkt_d_valid; // @[lsu_addrcheck.scala 61:137] + wire _T_32 = io_lsu_pkt_d_bits_store | io_lsu_pkt_d_bits_load; // @[lsu_addrcheck.scala 61:185] + wire is_sideeffects_d = _T_31 & _T_32; // @[lsu_addrcheck.scala 61:158] + wire _T_34 = io_start_addr_d[1:0] == 2'h0; // @[lsu_addrcheck.scala 62:80] + wire _T_35 = io_lsu_pkt_d_bits_word & _T_34; // @[lsu_addrcheck.scala 62:56] + wire _T_37 = ~io_start_addr_d[0]; // @[lsu_addrcheck.scala 62:138] + wire _T_38 = io_lsu_pkt_d_bits_half & _T_37; // @[lsu_addrcheck.scala 62:116] + wire _T_39 = _T_35 | _T_38; // @[lsu_addrcheck.scala 62:90] + wire is_aligned_d = _T_39 | io_lsu_pkt_d_bits_by; // @[lsu_addrcheck.scala 62:148] + wire [31:0] _T_50 = io_start_addr_d | 32'h7fffffff; // @[lsu_addrcheck.scala 67:56] + wire _T_52 = _T_50 == 32'h7fffffff; // @[lsu_addrcheck.scala 67:88] + wire [31:0] _T_55 = io_start_addr_d | 32'h3fffffff; // @[lsu_addrcheck.scala 68:56] + wire _T_57 = _T_55 == 32'hffffffff; // @[lsu_addrcheck.scala 68:88] + wire _T_59 = _T_52 | _T_57; // @[lsu_addrcheck.scala 67:153] + wire [31:0] _T_61 = io_start_addr_d | 32'h1fffffff; // @[lsu_addrcheck.scala 69:56] + wire _T_63 = _T_61 == 32'hbfffffff; // @[lsu_addrcheck.scala 69:88] + wire _T_65 = _T_59 | _T_63; // @[lsu_addrcheck.scala 68:153] + wire [31:0] _T_67 = io_start_addr_d | 32'hfffffff; // @[lsu_addrcheck.scala 70:56] + wire _T_69 = _T_67 == 32'h8fffffff; // @[lsu_addrcheck.scala 70:88] + wire _T_71 = _T_65 | _T_69; // @[lsu_addrcheck.scala 69:153] + wire [31:0] _T_97 = io_end_addr_d | 32'h7fffffff; // @[lsu_addrcheck.scala 76:57] + wire _T_99 = _T_97 == 32'h7fffffff; // @[lsu_addrcheck.scala 76:89] + wire [31:0] _T_102 = io_end_addr_d | 32'h3fffffff; // @[lsu_addrcheck.scala 77:58] + wire _T_104 = _T_102 == 32'hffffffff; // @[lsu_addrcheck.scala 77:90] + wire _T_106 = _T_99 | _T_104; // @[lsu_addrcheck.scala 76:154] + wire [31:0] _T_108 = io_end_addr_d | 32'h1fffffff; // @[lsu_addrcheck.scala 78:58] + wire _T_110 = _T_108 == 32'hbfffffff; // @[lsu_addrcheck.scala 78:90] + wire _T_112 = _T_106 | _T_110; // @[lsu_addrcheck.scala 77:155] + wire [31:0] _T_114 = io_end_addr_d | 32'hfffffff; // @[lsu_addrcheck.scala 79:58] + wire _T_116 = _T_114 == 32'h8fffffff; // @[lsu_addrcheck.scala 79:90] + wire _T_118 = _T_112 | _T_116; // @[lsu_addrcheck.scala 78:155] + wire non_dccm_access_ok = _T_71 & _T_118; // @[lsu_addrcheck.scala 75:7] + wire regpred_access_fault_d = start_addr_dccm_or_pic ^ base_reg_dccm_or_pic; // @[lsu_addrcheck.scala 85:57] + wire _T_145 = io_start_addr_d[1:0] != 2'h0; // @[lsu_addrcheck.scala 86:76] + wire _T_146 = ~io_lsu_pkt_d_bits_word; // @[lsu_addrcheck.scala 86:92] + wire _T_147 = _T_145 | _T_146; // @[lsu_addrcheck.scala 86:90] + wire picm_access_fault_d = io_addr_in_pic_d & _T_147; // @[lsu_addrcheck.scala 86:51] + wire _T_148 = start_addr_in_dccm_d | start_addr_in_pic_d; // @[lsu_addrcheck.scala 91:87] + wire _T_149 = ~_T_148; // @[lsu_addrcheck.scala 91:64] + wire _T_150 = start_addr_in_dccm_region_d & _T_149; // @[lsu_addrcheck.scala 91:62] + wire _T_151 = end_addr_in_dccm_d | end_addr_in_pic_d; // @[lsu_addrcheck.scala 93:57] + wire _T_152 = ~_T_151; // @[lsu_addrcheck.scala 93:36] + wire _T_153 = end_addr_in_dccm_region_d & _T_152; // @[lsu_addrcheck.scala 93:34] + wire _T_154 = _T_150 | _T_153; // @[lsu_addrcheck.scala 91:112] + wire _T_155 = start_addr_in_dccm_d & end_addr_in_pic_d; // @[lsu_addrcheck.scala 95:29] + wire _T_156 = _T_154 | _T_155; // @[lsu_addrcheck.scala 93:85] + wire _T_157 = start_addr_in_pic_d & end_addr_in_dccm_d; // @[lsu_addrcheck.scala 97:29] + wire unmapped_access_fault_d = _T_156 | _T_157; // @[lsu_addrcheck.scala 95:85] + wire _T_159 = ~start_addr_in_dccm_region_d; // @[lsu_addrcheck.scala 99:33] + wire _T_160 = ~non_dccm_access_ok; // @[lsu_addrcheck.scala 99:64] + wire mpu_access_fault_d = _T_159 & _T_160; // @[lsu_addrcheck.scala 99:62] + wire _T_162 = unmapped_access_fault_d | mpu_access_fault_d; // @[lsu_addrcheck.scala 111:49] + wire _T_163 = _T_162 | picm_access_fault_d; // @[lsu_addrcheck.scala 111:70] + wire _T_164 = _T_163 | regpred_access_fault_d; // @[lsu_addrcheck.scala 111:92] + wire _T_165 = _T_164 & io_lsu_pkt_d_valid; // @[lsu_addrcheck.scala 111:118] + wire _T_166 = ~io_lsu_pkt_d_bits_dma; // @[lsu_addrcheck.scala 111:141] + wire [3:0] _T_172 = picm_access_fault_d ? 4'h6 : 4'h0; // @[lsu_addrcheck.scala 112:164] + wire [3:0] _T_173 = regpred_access_fault_d ? 4'h5 : _T_172; // @[lsu_addrcheck.scala 112:120] + wire [3:0] _T_174 = mpu_access_fault_d ? 4'h3 : _T_173; // @[lsu_addrcheck.scala 112:80] + wire [3:0] access_fault_mscause_d = unmapped_access_fault_d ? 4'h2 : _T_174; // @[lsu_addrcheck.scala 112:35] + wire regcross_misaligned_fault_d = io_start_addr_d[31:28] != io_end_addr_d[31:28]; // @[lsu_addrcheck.scala 113:61] + wire _T_177 = ~is_aligned_d; // @[lsu_addrcheck.scala 114:59] + wire sideeffect_misaligned_fault_d = is_sideeffects_d & _T_177; // @[lsu_addrcheck.scala 114:57] + wire _T_178 = sideeffect_misaligned_fault_d & io_addr_external_d; // @[lsu_addrcheck.scala 115:90] + wire _T_179 = regcross_misaligned_fault_d | _T_178; // @[lsu_addrcheck.scala 115:57] + wire _T_180 = _T_179 & io_lsu_pkt_d_valid; // @[lsu_addrcheck.scala 115:113] + wire [3:0] _T_184 = sideeffect_misaligned_fault_d ? 4'h1 : 4'h0; // @[lsu_addrcheck.scala 116:80] + wire [3:0] misaligned_fault_mscause_d = regcross_misaligned_fault_d ? 4'h2 : _T_184; // @[lsu_addrcheck.scala 116:39] + wire _T_189 = ~start_addr_in_dccm_d; // @[lsu_addrcheck.scala 118:66] + wire _T_190 = start_addr_in_dccm_region_d & _T_189; // @[lsu_addrcheck.scala 118:64] + wire _T_191 = ~end_addr_in_dccm_d; // @[lsu_addrcheck.scala 118:120] + wire _T_192 = end_addr_in_dccm_region_d & _T_191; // @[lsu_addrcheck.scala 118:118] + wire _T_193 = _T_190 | _T_192; // @[lsu_addrcheck.scala 118:88] + wire _T_194 = _T_193 & io_lsu_pkt_d_valid; // @[lsu_addrcheck.scala 118:142] + wire _T_196 = start_addr_in_dccm_region_d & end_addr_in_dccm_region_d; // @[lsu_addrcheck.scala 119:66] + wire _T_197 = ~_T_196; // @[lsu_addrcheck.scala 119:36] + wire _T_198 = _T_197 & io_lsu_pkt_d_valid; // @[lsu_addrcheck.scala 119:95] + reg _T_200; // @[lsu_addrcheck.scala 121:60] + assign io_is_sideeffects_m = _T_200; // @[lsu_addrcheck.scala 121:50] + assign io_addr_in_dccm_d = start_addr_in_dccm_d & end_addr_in_dccm_d; // @[lsu_addrcheck.scala 56:32] + assign io_addr_in_pic_d = start_addr_in_pic_d & end_addr_in_pic_d; // @[lsu_addrcheck.scala 57:32] + assign io_addr_external_d = ~start_addr_dccm_or_pic; // @[lsu_addrcheck.scala 59:30] + assign io_access_fault_d = _T_165 & _T_166; // @[lsu_addrcheck.scala 111:21] + assign io_misaligned_fault_d = _T_180 & _T_166; // @[lsu_addrcheck.scala 115:25] + assign io_exc_mscause_d = io_misaligned_fault_d ? misaligned_fault_mscause_d : access_fault_mscause_d; // @[lsu_addrcheck.scala 117:21] + assign io_fir_dccm_access_error_d = _T_194 & io_lsu_pkt_d_bits_fast_int; // @[lsu_addrcheck.scala 118:31] + assign io_fir_nondccm_access_error_d = _T_198 & io_lsu_pkt_d_bits_fast_int; // @[lsu_addrcheck.scala 119:33] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + _T_200 = _RAND_0[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + _T_200 = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge io_lsu_c2_m_clk or posedge reset) begin + if (reset) begin + _T_200 <= 1'h0; + end else begin + _T_200 <= _T_31 & _T_32; + end + end +endmodule +module lsu_lsc_ctl( + input reset, + input io_lsu_c1_m_clk, + input io_lsu_c1_r_clk, + input io_lsu_c2_m_clk, + input io_lsu_c2_r_clk, + input io_lsu_store_c1_m_clk, + input [31:0] io_lsu_ld_data_corr_r, + input io_lsu_single_ecc_error_r, + input io_lsu_double_ecc_error_r, + input [31:0] io_lsu_ld_data_m, + input io_lsu_single_ecc_error_m, + input io_lsu_double_ecc_error_m, + input io_flush_m_up, + input io_flush_r, + input [31:0] io_lsu_exu_exu_lsu_rs1_d, + input [31:0] io_lsu_exu_exu_lsu_rs2_d, + input io_lsu_p_valid, + input io_lsu_p_bits_fast_int, + input io_lsu_p_bits_by, + input io_lsu_p_bits_half, + input io_lsu_p_bits_word, + input io_lsu_p_bits_dword, + input io_lsu_p_bits_load, + input io_lsu_p_bits_store, + input io_lsu_p_bits_unsign, + input io_lsu_p_bits_dma, + input io_lsu_p_bits_store_data_bypass_d, + input io_lsu_p_bits_load_ldst_bypass_d, + input io_lsu_p_bits_store_data_bypass_m, + input io_dec_lsu_valid_raw_d, + input [11:0] io_dec_lsu_offset_d, + input [31:0] io_picm_mask_data_m, + input [31:0] io_bus_read_data_m, + output [31:0] io_lsu_result_m, + output [31:0] io_lsu_result_corr_r, + output [31:0] io_lsu_addr_d, + output [31:0] io_lsu_addr_m, + output [31:0] io_lsu_addr_r, + output [31:0] io_end_addr_d, + output [31:0] io_end_addr_m, + output [31:0] io_end_addr_r, + output [31:0] io_store_data_m, + input [31:0] io_dec_tlu_mrac_ff, + output io_lsu_exc_m, + output io_is_sideeffects_m, + output io_lsu_commit_r, + output io_lsu_single_ecc_error_incr, + output io_lsu_error_pkt_r_valid, + output io_lsu_error_pkt_r_bits_single_ecc_error, + output io_lsu_error_pkt_r_bits_inst_type, + output io_lsu_error_pkt_r_bits_exc_type, + output [3:0] io_lsu_error_pkt_r_bits_mscause, + output [31:0] io_lsu_error_pkt_r_bits_addr, + output [30:0] io_lsu_fir_addr, + output [1:0] io_lsu_fir_error, + output io_addr_in_dccm_d, + output io_addr_in_dccm_m, + output io_addr_in_dccm_r, + output io_addr_in_pic_d, + output io_addr_in_pic_m, + output io_addr_in_pic_r, + output io_addr_external_m, + input io_dma_lsc_ctl_dma_dccm_req, + input [31:0] io_dma_lsc_ctl_dma_mem_addr, + input [2:0] io_dma_lsc_ctl_dma_mem_sz, + input io_dma_lsc_ctl_dma_mem_write, + input [63:0] io_dma_lsc_ctl_dma_mem_wdata, + output io_lsu_pkt_d_valid, + output io_lsu_pkt_d_bits_fast_int, + output io_lsu_pkt_d_bits_by, + output io_lsu_pkt_d_bits_half, + output io_lsu_pkt_d_bits_word, + output io_lsu_pkt_d_bits_dword, + output io_lsu_pkt_d_bits_load, + output io_lsu_pkt_d_bits_store, + output io_lsu_pkt_d_bits_unsign, + output io_lsu_pkt_d_bits_dma, + output io_lsu_pkt_d_bits_store_data_bypass_d, + output io_lsu_pkt_d_bits_load_ldst_bypass_d, + output io_lsu_pkt_d_bits_store_data_bypass_m, + output io_lsu_pkt_m_valid, + output io_lsu_pkt_m_bits_fast_int, + output io_lsu_pkt_m_bits_by, + output io_lsu_pkt_m_bits_half, + output io_lsu_pkt_m_bits_word, + output io_lsu_pkt_m_bits_dword, + output io_lsu_pkt_m_bits_load, + output io_lsu_pkt_m_bits_store, + output io_lsu_pkt_m_bits_unsign, + output io_lsu_pkt_m_bits_dma, + output io_lsu_pkt_m_bits_store_data_bypass_m, + output io_lsu_pkt_r_valid, + output io_lsu_pkt_r_bits_by, + output io_lsu_pkt_r_bits_half, + output io_lsu_pkt_r_bits_word, + output io_lsu_pkt_r_bits_dword, + output io_lsu_pkt_r_bits_load, + output io_lsu_pkt_r_bits_store, + output io_lsu_pkt_r_bits_unsign, + output io_lsu_pkt_r_bits_dma +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; + reg [31:0] _RAND_15; + reg [31:0] _RAND_16; + reg [31:0] _RAND_17; + reg [31:0] _RAND_18; + reg [31:0] _RAND_19; + reg [31:0] _RAND_20; + reg [31:0] _RAND_21; + reg [31:0] _RAND_22; + reg [31:0] _RAND_23; + reg [31:0] _RAND_24; + reg [31:0] _RAND_25; + reg [31:0] _RAND_26; + reg [31:0] _RAND_27; + reg [31:0] _RAND_28; + reg [31:0] _RAND_29; + reg [31:0] _RAND_30; + reg [31:0] _RAND_31; + reg [31:0] _RAND_32; + reg [31:0] _RAND_33; + reg [31:0] _RAND_34; + reg [31:0] _RAND_35; + reg [31:0] _RAND_36; + reg [31:0] _RAND_37; + reg [31:0] _RAND_38; + reg [31:0] _RAND_39; + reg [31:0] _RAND_40; + reg [31:0] _RAND_41; + reg [31:0] _RAND_42; + reg [31:0] _RAND_43; +`endif // RANDOMIZE_REG_INIT + wire addrcheck_reset; // @[lsu_lsc_ctl.scala 113:25] + wire addrcheck_io_lsu_c2_m_clk; // @[lsu_lsc_ctl.scala 113:25] + wire [31:0] addrcheck_io_start_addr_d; // @[lsu_lsc_ctl.scala 113:25] + wire [31:0] addrcheck_io_end_addr_d; // @[lsu_lsc_ctl.scala 113:25] + wire addrcheck_io_lsu_pkt_d_valid; // @[lsu_lsc_ctl.scala 113:25] + wire addrcheck_io_lsu_pkt_d_bits_fast_int; // @[lsu_lsc_ctl.scala 113:25] + wire addrcheck_io_lsu_pkt_d_bits_by; // @[lsu_lsc_ctl.scala 113:25] + wire addrcheck_io_lsu_pkt_d_bits_half; // @[lsu_lsc_ctl.scala 113:25] + wire addrcheck_io_lsu_pkt_d_bits_word; // @[lsu_lsc_ctl.scala 113:25] + wire addrcheck_io_lsu_pkt_d_bits_load; // @[lsu_lsc_ctl.scala 113:25] + wire addrcheck_io_lsu_pkt_d_bits_store; // @[lsu_lsc_ctl.scala 113:25] + wire addrcheck_io_lsu_pkt_d_bits_dma; // @[lsu_lsc_ctl.scala 113:25] + wire [31:0] addrcheck_io_dec_tlu_mrac_ff; // @[lsu_lsc_ctl.scala 113:25] + wire [3:0] addrcheck_io_rs1_region_d; // @[lsu_lsc_ctl.scala 113:25] + wire addrcheck_io_is_sideeffects_m; // @[lsu_lsc_ctl.scala 113:25] + wire addrcheck_io_addr_in_dccm_d; // @[lsu_lsc_ctl.scala 113:25] + wire addrcheck_io_addr_in_pic_d; // @[lsu_lsc_ctl.scala 113:25] + wire addrcheck_io_addr_external_d; // @[lsu_lsc_ctl.scala 113:25] + wire addrcheck_io_access_fault_d; // @[lsu_lsc_ctl.scala 113:25] + wire addrcheck_io_misaligned_fault_d; // @[lsu_lsc_ctl.scala 113:25] + wire [3:0] addrcheck_io_exc_mscause_d; // @[lsu_lsc_ctl.scala 113:25] + wire addrcheck_io_fir_dccm_access_error_d; // @[lsu_lsc_ctl.scala 113:25] + wire addrcheck_io_fir_nondccm_access_error_d; // @[lsu_lsc_ctl.scala 113:25] + wire [31:0] lsu_rs1_d = io_dec_lsu_valid_raw_d ? io_lsu_exu_exu_lsu_rs1_d : io_dma_lsc_ctl_dma_mem_addr; // @[lsu_lsc_ctl.scala 95:28] + wire [11:0] _T_3 = io_dec_lsu_valid_raw_d ? 12'hfff : 12'h0; // @[Bitwise.scala 72:12] + wire [11:0] lsu_offset_d = io_dec_lsu_offset_d & _T_3; // @[lsu_lsc_ctl.scala 96:51] + wire [31:0] rs1_d = io_lsu_pkt_d_bits_load_ldst_bypass_d ? io_lsu_result_m : lsu_rs1_d; // @[lsu_lsc_ctl.scala 99:28] + wire [12:0] _T_6 = {1'h0,rs1_d[11:0]}; // @[Cat.scala 29:58] + wire [12:0] _T_8 = {1'h0,lsu_offset_d}; // @[Cat.scala 29:58] + wire [12:0] _T_10 = _T_6 + _T_8; // @[lib.scala 92:39] + wire _T_13 = lsu_offset_d[11] ^ _T_10[12]; // @[lib.scala 93:46] + wire _T_14 = ~_T_13; // @[lib.scala 93:33] + wire [19:0] _T_16 = _T_14 ? 20'hfffff : 20'h0; // @[Bitwise.scala 72:12] + wire [19:0] _T_18 = _T_16 & rs1_d[31:12]; // @[lib.scala 93:58] + wire _T_20 = ~lsu_offset_d[11]; // @[lib.scala 94:18] + wire _T_22 = _T_20 & _T_10[12]; // @[lib.scala 94:30] + wire [19:0] _T_24 = _T_22 ? 20'hfffff : 20'h0; // @[Bitwise.scala 72:12] + wire [19:0] _T_27 = rs1_d[31:12] + 20'h1; // @[lib.scala 94:54] + wire [19:0] _T_28 = _T_24 & _T_27; // @[lib.scala 94:41] + wire [19:0] _T_29 = _T_18 | _T_28; // @[lib.scala 93:72] + wire _T_32 = ~_T_10[12]; // @[lib.scala 95:31] + wire _T_33 = lsu_offset_d[11] & _T_32; // @[lib.scala 95:29] + wire [19:0] _T_35 = _T_33 ? 20'hfffff : 20'h0; // @[Bitwise.scala 72:12] + wire [19:0] _T_38 = rs1_d[31:12] - 20'h1; // @[lib.scala 95:54] + wire [19:0] _T_39 = _T_35 & _T_38; // @[lib.scala 95:41] + wire [19:0] _T_40 = _T_29 | _T_39; // @[lib.scala 94:61] + wire [2:0] _T_43 = io_lsu_pkt_d_bits_half ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_44 = _T_43 & 3'h1; // @[lsu_lsc_ctl.scala 104:58] + wire [2:0] _T_46 = io_lsu_pkt_d_bits_word ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_47 = _T_46 & 3'h3; // @[lsu_lsc_ctl.scala 105:40] + wire [2:0] _T_48 = _T_44 | _T_47; // @[lsu_lsc_ctl.scala 104:70] + wire [2:0] _T_50 = io_lsu_pkt_d_bits_dword ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] addr_offset_d = _T_48 | _T_50; // @[lsu_lsc_ctl.scala 105:52] + wire [12:0] _T_54 = {lsu_offset_d[11],lsu_offset_d}; // @[Cat.scala 29:58] + wire [11:0] _T_57 = {9'h0,addr_offset_d}; // @[Cat.scala 29:58] + wire [12:0] _GEN_0 = {{1'd0}, _T_57}; // @[lsu_lsc_ctl.scala 108:60] + wire [12:0] end_addr_offset_d = _T_54 + _GEN_0; // @[lsu_lsc_ctl.scala 108:60] + wire [18:0] _T_62 = end_addr_offset_d[12] ? 19'h7ffff : 19'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_64 = {_T_62,end_addr_offset_d}; // @[Cat.scala 29:58] + reg access_fault_m; // @[lsu_lsc_ctl.scala 144:75] + reg misaligned_fault_m; // @[lsu_lsc_ctl.scala 145:75] + reg [3:0] exc_mscause_m; // @[lsu_lsc_ctl.scala 146:75] + reg fir_dccm_access_error_m; // @[lsu_lsc_ctl.scala 147:75] + reg fir_nondccm_access_error_m; // @[lsu_lsc_ctl.scala 148:75] + wire _T_69 = access_fault_m | misaligned_fault_m; // @[lsu_lsc_ctl.scala 150:34] + wire _T_70 = ~io_lsu_double_ecc_error_r; // @[lsu_lsc_ctl.scala 151:64] + wire _T_71 = io_lsu_single_ecc_error_r & _T_70; // @[lsu_lsc_ctl.scala 151:62] + wire _T_72 = io_lsu_commit_r | io_lsu_pkt_r_bits_dma; // @[lsu_lsc_ctl.scala 151:111] + wire _T_73 = _T_71 & _T_72; // @[lsu_lsc_ctl.scala 151:92] + wire _T_76 = _T_69 | io_lsu_double_ecc_error_m; // @[lsu_lsc_ctl.scala 173:67] + wire _T_77 = _T_76 & io_lsu_pkt_m_valid; // @[lsu_lsc_ctl.scala 173:96] + wire _T_78 = ~io_lsu_pkt_m_bits_dma; // @[lsu_lsc_ctl.scala 173:119] + wire _T_79 = _T_77 & _T_78; // @[lsu_lsc_ctl.scala 173:117] + wire _T_80 = ~io_lsu_pkt_m_bits_fast_int; // @[lsu_lsc_ctl.scala 173:144] + wire _T_81 = _T_79 & _T_80; // @[lsu_lsc_ctl.scala 173:142] + wire _T_82 = ~io_flush_m_up; // @[lsu_lsc_ctl.scala 173:174] + wire lsu_error_pkt_m_valid = _T_81 & _T_82; // @[lsu_lsc_ctl.scala 173:172] + wire _T_84 = ~lsu_error_pkt_m_valid; // @[lsu_lsc_ctl.scala 174:75] + wire _T_85 = io_lsu_single_ecc_error_m & _T_84; // @[lsu_lsc_ctl.scala 174:73] + wire lsu_error_pkt_m_bits_exc_type = ~misaligned_fault_m; // @[lsu_lsc_ctl.scala 176:46] + wire _T_90 = io_lsu_double_ecc_error_m & lsu_error_pkt_m_bits_exc_type; // @[lsu_lsc_ctl.scala 177:78] + wire _T_91 = ~access_fault_m; // @[lsu_lsc_ctl.scala 177:102] + wire _T_92 = _T_90 & _T_91; // @[lsu_lsc_ctl.scala 177:100] + wire _T_99 = io_lsu_pkt_m_bits_fast_int & io_lsu_double_ecc_error_m; // @[lsu_lsc_ctl.scala 179:166] + reg _T_105_valid; // @[lsu_lsc_ctl.scala 180:75] + reg _T_105_bits_single_ecc_error; // @[lsu_lsc_ctl.scala 180:75] + reg _T_105_bits_inst_type; // @[lsu_lsc_ctl.scala 180:75] + reg _T_105_bits_exc_type; // @[lsu_lsc_ctl.scala 180:75] + reg [3:0] _T_105_bits_mscause; // @[lsu_lsc_ctl.scala 180:75] + reg [31:0] _T_105_bits_addr; // @[lsu_lsc_ctl.scala 180:75] + reg [1:0] _T_106; // @[lsu_lsc_ctl.scala 181:75] + wire dma_pkt_d_bits_load = ~io_dma_lsc_ctl_dma_mem_write; // @[lsu_lsc_ctl.scala 188:30] + wire dma_pkt_d_bits_by = io_dma_lsc_ctl_dma_mem_sz == 3'h0; // @[lsu_lsc_ctl.scala 189:62] + wire dma_pkt_d_bits_half = io_dma_lsc_ctl_dma_mem_sz == 3'h1; // @[lsu_lsc_ctl.scala 190:62] + wire dma_pkt_d_bits_word = io_dma_lsc_ctl_dma_mem_sz == 3'h2; // @[lsu_lsc_ctl.scala 191:62] + wire dma_pkt_d_bits_dword = io_dma_lsc_ctl_dma_mem_sz == 3'h3; // @[lsu_lsc_ctl.scala 192:62] + wire _T_118 = ~io_lsu_p_bits_fast_int; // @[lsu_lsc_ctl.scala 205:64] + wire _T_119 = io_flush_m_up & _T_118; // @[lsu_lsc_ctl.scala 205:61] + wire _T_120 = ~_T_119; // @[lsu_lsc_ctl.scala 205:45] + wire _T_121 = io_lsu_p_valid & _T_120; // @[lsu_lsc_ctl.scala 205:43] + wire _T_123 = ~io_lsu_pkt_d_bits_dma; // @[lsu_lsc_ctl.scala 206:68] + wire _T_124 = io_flush_m_up & _T_123; // @[lsu_lsc_ctl.scala 206:65] + wire _T_125 = ~_T_124; // @[lsu_lsc_ctl.scala 206:49] + wire _T_128 = io_flush_m_up & _T_78; // @[lsu_lsc_ctl.scala 207:65] + wire _T_129 = ~_T_128; // @[lsu_lsc_ctl.scala 207:49] + reg _T_132_bits_fast_int; // @[lsu_lsc_ctl.scala 209:65] + reg _T_132_bits_by; // @[lsu_lsc_ctl.scala 209:65] + reg _T_132_bits_half; // @[lsu_lsc_ctl.scala 209:65] + reg _T_132_bits_word; // @[lsu_lsc_ctl.scala 209:65] + reg _T_132_bits_dword; // @[lsu_lsc_ctl.scala 209:65] + reg _T_132_bits_load; // @[lsu_lsc_ctl.scala 209:65] + reg _T_132_bits_store; // @[lsu_lsc_ctl.scala 209:65] + reg _T_132_bits_unsign; // @[lsu_lsc_ctl.scala 209:65] + reg _T_132_bits_dma; // @[lsu_lsc_ctl.scala 209:65] + reg _T_132_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 209:65] + reg _T_134_bits_by; // @[lsu_lsc_ctl.scala 210:65] + reg _T_134_bits_half; // @[lsu_lsc_ctl.scala 210:65] + reg _T_134_bits_word; // @[lsu_lsc_ctl.scala 210:65] + reg _T_134_bits_dword; // @[lsu_lsc_ctl.scala 210:65] + reg _T_134_bits_load; // @[lsu_lsc_ctl.scala 210:65] + reg _T_134_bits_store; // @[lsu_lsc_ctl.scala 210:65] + reg _T_134_bits_unsign; // @[lsu_lsc_ctl.scala 210:65] + reg _T_134_bits_dma; // @[lsu_lsc_ctl.scala 210:65] + reg _T_135; // @[lsu_lsc_ctl.scala 211:65] + reg _T_136; // @[lsu_lsc_ctl.scala 212:65] + wire [5:0] _T_139 = {io_dma_lsc_ctl_dma_mem_addr[2:0],3'h0}; // @[Cat.scala 29:58] + wire [63:0] dma_mem_wdata_shifted = io_dma_lsc_ctl_dma_mem_wdata >> _T_139; // @[lsu_lsc_ctl.scala 214:66] + reg [31:0] store_data_pre_m; // @[lsu_lsc_ctl.scala 218:72] + reg [31:0] _T_146; // @[lsu_lsc_ctl.scala 219:62] + reg [31:0] _T_147; // @[lsu_lsc_ctl.scala 220:62] + reg [31:0] _T_148; // @[lsu_lsc_ctl.scala 221:62] + reg [31:0] _T_149; // @[lsu_lsc_ctl.scala 222:62] + reg _T_150; // @[lsu_lsc_ctl.scala 223:62] + reg _T_151; // @[lsu_lsc_ctl.scala 224:62] + reg _T_152; // @[lsu_lsc_ctl.scala 225:62] + reg _T_153; // @[lsu_lsc_ctl.scala 226:62] + reg _T_154; // @[lsu_lsc_ctl.scala 227:62] + reg addr_external_r; // @[lsu_lsc_ctl.scala 228:66] + reg [31:0] bus_read_data_r; // @[lsu_lsc_ctl.scala 229:66] + wire _T_156 = io_lsu_pkt_r_bits_store | io_lsu_pkt_r_bits_load; // @[lsu_lsc_ctl.scala 235:68] + wire _T_157 = io_lsu_pkt_r_valid & _T_156; // @[lsu_lsc_ctl.scala 235:41] + wire _T_158 = ~io_flush_r; // @[lsu_lsc_ctl.scala 235:96] + wire _T_159 = _T_157 & _T_158; // @[lsu_lsc_ctl.scala 235:94] + wire _T_160 = ~io_lsu_pkt_r_bits_dma; // @[lsu_lsc_ctl.scala 235:110] + wire _T_163 = ~io_addr_in_pic_m; // @[lsu_lsc_ctl.scala 236:69] + wire [31:0] _T_165 = _T_163 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_166 = io_picm_mask_data_m | _T_165; // @[lsu_lsc_ctl.scala 236:59] + wire [31:0] _T_168 = io_lsu_pkt_m_bits_store_data_bypass_m ? io_lsu_result_m : store_data_pre_m; // @[lsu_lsc_ctl.scala 236:94] + wire [31:0] lsu_ld_datafn_m = io_addr_external_m ? io_bus_read_data_m : io_lsu_ld_data_m; // @[lsu_lsc_ctl.scala 257:33] + wire [31:0] lsu_ld_datafn_corr_r = addr_external_r ? bus_read_data_r : io_lsu_ld_data_corr_r; // @[lsu_lsc_ctl.scala 258:33] + wire _T_174 = io_lsu_pkt_m_bits_unsign & io_lsu_pkt_m_bits_by; // @[lsu_lsc_ctl.scala 259:66] + wire [31:0] _T_176 = _T_174 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_178 = {24'h0,lsu_ld_datafn_m[7:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_179 = _T_176 & _T_178; // @[lsu_lsc_ctl.scala 259:94] + wire _T_180 = io_lsu_pkt_m_bits_unsign & io_lsu_pkt_m_bits_half; // @[lsu_lsc_ctl.scala 260:43] + wire [31:0] _T_182 = _T_180 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_184 = {16'h0,lsu_ld_datafn_m[15:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_185 = _T_182 & _T_184; // @[lsu_lsc_ctl.scala 260:71] + wire [31:0] _T_186 = _T_179 | _T_185; // @[lsu_lsc_ctl.scala 259:133] + wire _T_187 = ~io_lsu_pkt_m_bits_unsign; // @[lsu_lsc_ctl.scala 261:17] + wire _T_188 = _T_187 & io_lsu_pkt_m_bits_by; // @[lsu_lsc_ctl.scala 261:43] + wire [31:0] _T_190 = _T_188 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [23:0] _T_193 = lsu_ld_datafn_m[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_195 = {_T_193,lsu_ld_datafn_m[7:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_196 = _T_190 & _T_195; // @[lsu_lsc_ctl.scala 261:71] + wire [31:0] _T_197 = _T_186 | _T_196; // @[lsu_lsc_ctl.scala 260:114] + wire _T_199 = _T_187 & io_lsu_pkt_m_bits_half; // @[lsu_lsc_ctl.scala 262:43] + wire [31:0] _T_201 = _T_199 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [15:0] _T_204 = lsu_ld_datafn_m[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_206 = {_T_204,lsu_ld_datafn_m[15:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_207 = _T_201 & _T_206; // @[lsu_lsc_ctl.scala 262:71] + wire [31:0] _T_208 = _T_197 | _T_207; // @[lsu_lsc_ctl.scala 261:134] + wire [31:0] _T_210 = io_lsu_pkt_m_bits_word ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_212 = _T_210 & lsu_ld_datafn_m; // @[lsu_lsc_ctl.scala 263:43] + wire _T_214 = io_lsu_pkt_r_bits_unsign & io_lsu_pkt_r_bits_by; // @[lsu_lsc_ctl.scala 264:66] + wire [31:0] _T_216 = _T_214 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_218 = {24'h0,lsu_ld_datafn_corr_r[7:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_219 = _T_216 & _T_218; // @[lsu_lsc_ctl.scala 264:94] + wire _T_220 = io_lsu_pkt_r_bits_unsign & io_lsu_pkt_r_bits_half; // @[lsu_lsc_ctl.scala 265:43] + wire [31:0] _T_222 = _T_220 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_224 = {16'h0,lsu_ld_datafn_corr_r[15:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_225 = _T_222 & _T_224; // @[lsu_lsc_ctl.scala 265:71] + wire [31:0] _T_226 = _T_219 | _T_225; // @[lsu_lsc_ctl.scala 264:138] + wire _T_227 = ~io_lsu_pkt_r_bits_unsign; // @[lsu_lsc_ctl.scala 266:17] + wire _T_228 = _T_227 & io_lsu_pkt_r_bits_by; // @[lsu_lsc_ctl.scala 266:43] + wire [31:0] _T_230 = _T_228 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [23:0] _T_233 = lsu_ld_datafn_corr_r[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_235 = {_T_233,lsu_ld_datafn_corr_r[7:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_236 = _T_230 & _T_235; // @[lsu_lsc_ctl.scala 266:71] + wire [31:0] _T_237 = _T_226 | _T_236; // @[lsu_lsc_ctl.scala 265:119] + wire _T_239 = _T_227 & io_lsu_pkt_r_bits_half; // @[lsu_lsc_ctl.scala 267:43] + wire [31:0] _T_241 = _T_239 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [15:0] _T_244 = lsu_ld_datafn_corr_r[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_246 = {_T_244,lsu_ld_datafn_corr_r[15:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_247 = _T_241 & _T_246; // @[lsu_lsc_ctl.scala 267:71] + wire [31:0] _T_248 = _T_237 | _T_247; // @[lsu_lsc_ctl.scala 266:144] + wire [31:0] _T_250 = io_lsu_pkt_r_bits_word ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_252 = _T_250 & lsu_ld_datafn_corr_r; // @[lsu_lsc_ctl.scala 268:43] + lsu_addrcheck addrcheck ( // @[lsu_lsc_ctl.scala 113:25] + .reset(addrcheck_reset), + .io_lsu_c2_m_clk(addrcheck_io_lsu_c2_m_clk), + .io_start_addr_d(addrcheck_io_start_addr_d), + .io_end_addr_d(addrcheck_io_end_addr_d), + .io_lsu_pkt_d_valid(addrcheck_io_lsu_pkt_d_valid), + .io_lsu_pkt_d_bits_fast_int(addrcheck_io_lsu_pkt_d_bits_fast_int), + .io_lsu_pkt_d_bits_by(addrcheck_io_lsu_pkt_d_bits_by), + .io_lsu_pkt_d_bits_half(addrcheck_io_lsu_pkt_d_bits_half), + .io_lsu_pkt_d_bits_word(addrcheck_io_lsu_pkt_d_bits_word), + .io_lsu_pkt_d_bits_load(addrcheck_io_lsu_pkt_d_bits_load), + .io_lsu_pkt_d_bits_store(addrcheck_io_lsu_pkt_d_bits_store), + .io_lsu_pkt_d_bits_dma(addrcheck_io_lsu_pkt_d_bits_dma), + .io_dec_tlu_mrac_ff(addrcheck_io_dec_tlu_mrac_ff), + .io_rs1_region_d(addrcheck_io_rs1_region_d), + .io_is_sideeffects_m(addrcheck_io_is_sideeffects_m), + .io_addr_in_dccm_d(addrcheck_io_addr_in_dccm_d), + .io_addr_in_pic_d(addrcheck_io_addr_in_pic_d), + .io_addr_external_d(addrcheck_io_addr_external_d), + .io_access_fault_d(addrcheck_io_access_fault_d), + .io_misaligned_fault_d(addrcheck_io_misaligned_fault_d), + .io_exc_mscause_d(addrcheck_io_exc_mscause_d), + .io_fir_dccm_access_error_d(addrcheck_io_fir_dccm_access_error_d), + .io_fir_nondccm_access_error_d(addrcheck_io_fir_nondccm_access_error_d) + ); + assign io_lsu_result_m = _T_208 | _T_212; // @[lsu_lsc_ctl.scala 259:27] + assign io_lsu_result_corr_r = _T_248 | _T_252; // @[lsu_lsc_ctl.scala 264:27] + assign io_lsu_addr_d = {_T_40,_T_10[11:0]}; // @[lsu_lsc_ctl.scala 233:28] + assign io_lsu_addr_m = _T_146; // @[lsu_lsc_ctl.scala 219:24] + assign io_lsu_addr_r = _T_147; // @[lsu_lsc_ctl.scala 220:24] + assign io_end_addr_d = rs1_d + _T_64; // @[lsu_lsc_ctl.scala 110:24] + assign io_end_addr_m = _T_148; // @[lsu_lsc_ctl.scala 221:24] + assign io_end_addr_r = _T_149; // @[lsu_lsc_ctl.scala 222:24] + assign io_store_data_m = _T_166 & _T_168; // @[lsu_lsc_ctl.scala 236:29] + assign io_lsu_exc_m = access_fault_m | misaligned_fault_m; // @[lsu_lsc_ctl.scala 150:16] + assign io_is_sideeffects_m = addrcheck_io_is_sideeffects_m; // @[lsu_lsc_ctl.scala 123:42] + assign io_lsu_commit_r = _T_159 & _T_160; // @[lsu_lsc_ctl.scala 235:19] + assign io_lsu_single_ecc_error_incr = _T_73 & io_lsu_pkt_r_valid; // @[lsu_lsc_ctl.scala 151:32] + assign io_lsu_error_pkt_r_valid = _T_105_valid; // @[lsu_lsc_ctl.scala 180:38] + assign io_lsu_error_pkt_r_bits_single_ecc_error = _T_105_bits_single_ecc_error; // @[lsu_lsc_ctl.scala 180:38] + assign io_lsu_error_pkt_r_bits_inst_type = _T_105_bits_inst_type; // @[lsu_lsc_ctl.scala 180:38] + assign io_lsu_error_pkt_r_bits_exc_type = _T_105_bits_exc_type; // @[lsu_lsc_ctl.scala 180:38] + assign io_lsu_error_pkt_r_bits_mscause = _T_105_bits_mscause; // @[lsu_lsc_ctl.scala 180:38] + assign io_lsu_error_pkt_r_bits_addr = _T_105_bits_addr; // @[lsu_lsc_ctl.scala 180:38] + assign io_lsu_fir_addr = io_lsu_ld_data_corr_r[31:1]; // @[lsu_lsc_ctl.scala 231:28] + assign io_lsu_fir_error = _T_106; // @[lsu_lsc_ctl.scala 181:38] + assign io_addr_in_dccm_d = addrcheck_io_addr_in_dccm_d; // @[lsu_lsc_ctl.scala 124:42] + assign io_addr_in_dccm_m = _T_150; // @[lsu_lsc_ctl.scala 223:24] + assign io_addr_in_dccm_r = _T_151; // @[lsu_lsc_ctl.scala 224:24] + assign io_addr_in_pic_d = addrcheck_io_addr_in_pic_d; // @[lsu_lsc_ctl.scala 125:42] + assign io_addr_in_pic_m = _T_152; // @[lsu_lsc_ctl.scala 225:24] + assign io_addr_in_pic_r = _T_153; // @[lsu_lsc_ctl.scala 226:24] + assign io_addr_external_m = _T_154; // @[lsu_lsc_ctl.scala 227:24] + assign io_lsu_pkt_d_valid = _T_121 | io_dma_lsc_ctl_dma_dccm_req; // @[lsu_lsc_ctl.scala 201:20 lsu_lsc_ctl.scala 205:24] + assign io_lsu_pkt_d_bits_fast_int = io_dec_lsu_valid_raw_d & io_lsu_p_bits_fast_int; // @[lsu_lsc_ctl.scala 201:20] + assign io_lsu_pkt_d_bits_by = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_by : dma_pkt_d_bits_by; // @[lsu_lsc_ctl.scala 201:20] + assign io_lsu_pkt_d_bits_half = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_half : dma_pkt_d_bits_half; // @[lsu_lsc_ctl.scala 201:20] + assign io_lsu_pkt_d_bits_word = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_word : dma_pkt_d_bits_word; // @[lsu_lsc_ctl.scala 201:20] + assign io_lsu_pkt_d_bits_dword = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_dword : dma_pkt_d_bits_dword; // @[lsu_lsc_ctl.scala 201:20] + assign io_lsu_pkt_d_bits_load = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_load : dma_pkt_d_bits_load; // @[lsu_lsc_ctl.scala 201:20] + assign io_lsu_pkt_d_bits_store = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_store : io_dma_lsc_ctl_dma_mem_write; // @[lsu_lsc_ctl.scala 201:20] + assign io_lsu_pkt_d_bits_unsign = io_dec_lsu_valid_raw_d & io_lsu_p_bits_unsign; // @[lsu_lsc_ctl.scala 201:20] + assign io_lsu_pkt_d_bits_dma = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_dma : 1'h1; // @[lsu_lsc_ctl.scala 201:20] + assign io_lsu_pkt_d_bits_store_data_bypass_d = io_dec_lsu_valid_raw_d & io_lsu_p_bits_store_data_bypass_d; // @[lsu_lsc_ctl.scala 201:20] + assign io_lsu_pkt_d_bits_load_ldst_bypass_d = io_dec_lsu_valid_raw_d & io_lsu_p_bits_load_ldst_bypass_d; // @[lsu_lsc_ctl.scala 201:20] + assign io_lsu_pkt_d_bits_store_data_bypass_m = io_dec_lsu_valid_raw_d & io_lsu_p_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 201:20] + assign io_lsu_pkt_m_valid = _T_135; // @[lsu_lsc_ctl.scala 209:28 lsu_lsc_ctl.scala 211:28] + assign io_lsu_pkt_m_bits_fast_int = _T_132_bits_fast_int; // @[lsu_lsc_ctl.scala 209:28] + assign io_lsu_pkt_m_bits_by = _T_132_bits_by; // @[lsu_lsc_ctl.scala 209:28] + assign io_lsu_pkt_m_bits_half = _T_132_bits_half; // @[lsu_lsc_ctl.scala 209:28] + assign io_lsu_pkt_m_bits_word = _T_132_bits_word; // @[lsu_lsc_ctl.scala 209:28] + assign io_lsu_pkt_m_bits_dword = _T_132_bits_dword; // @[lsu_lsc_ctl.scala 209:28] + assign io_lsu_pkt_m_bits_load = _T_132_bits_load; // @[lsu_lsc_ctl.scala 209:28] + assign io_lsu_pkt_m_bits_store = _T_132_bits_store; // @[lsu_lsc_ctl.scala 209:28] + assign io_lsu_pkt_m_bits_unsign = _T_132_bits_unsign; // @[lsu_lsc_ctl.scala 209:28] + assign io_lsu_pkt_m_bits_dma = _T_132_bits_dma; // @[lsu_lsc_ctl.scala 209:28] + assign io_lsu_pkt_m_bits_store_data_bypass_m = _T_132_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 209:28] + assign io_lsu_pkt_r_valid = _T_136; // @[lsu_lsc_ctl.scala 210:28 lsu_lsc_ctl.scala 212:28] + assign io_lsu_pkt_r_bits_by = _T_134_bits_by; // @[lsu_lsc_ctl.scala 210:28] + assign io_lsu_pkt_r_bits_half = _T_134_bits_half; // @[lsu_lsc_ctl.scala 210:28] + assign io_lsu_pkt_r_bits_word = _T_134_bits_word; // @[lsu_lsc_ctl.scala 210:28] + assign io_lsu_pkt_r_bits_dword = _T_134_bits_dword; // @[lsu_lsc_ctl.scala 210:28] + assign io_lsu_pkt_r_bits_load = _T_134_bits_load; // @[lsu_lsc_ctl.scala 210:28] + assign io_lsu_pkt_r_bits_store = _T_134_bits_store; // @[lsu_lsc_ctl.scala 210:28] + assign io_lsu_pkt_r_bits_unsign = _T_134_bits_unsign; // @[lsu_lsc_ctl.scala 210:28] + assign io_lsu_pkt_r_bits_dma = _T_134_bits_dma; // @[lsu_lsc_ctl.scala 210:28] + assign addrcheck_reset = reset; + assign addrcheck_io_lsu_c2_m_clk = io_lsu_c2_m_clk; // @[lsu_lsc_ctl.scala 115:42] + assign addrcheck_io_start_addr_d = {_T_40,_T_10[11:0]}; // @[lsu_lsc_ctl.scala 117:42] + assign addrcheck_io_end_addr_d = rs1_d + _T_64; // @[lsu_lsc_ctl.scala 118:42] + assign addrcheck_io_lsu_pkt_d_valid = io_lsu_pkt_d_valid; // @[lsu_lsc_ctl.scala 119:42] + assign addrcheck_io_lsu_pkt_d_bits_fast_int = io_lsu_pkt_d_bits_fast_int; // @[lsu_lsc_ctl.scala 119:42] + assign addrcheck_io_lsu_pkt_d_bits_by = io_lsu_pkt_d_bits_by; // @[lsu_lsc_ctl.scala 119:42] + assign addrcheck_io_lsu_pkt_d_bits_half = io_lsu_pkt_d_bits_half; // @[lsu_lsc_ctl.scala 119:42] + assign addrcheck_io_lsu_pkt_d_bits_word = io_lsu_pkt_d_bits_word; // @[lsu_lsc_ctl.scala 119:42] + assign addrcheck_io_lsu_pkt_d_bits_load = io_lsu_pkt_d_bits_load; // @[lsu_lsc_ctl.scala 119:42] + assign addrcheck_io_lsu_pkt_d_bits_store = io_lsu_pkt_d_bits_store; // @[lsu_lsc_ctl.scala 119:42] + assign addrcheck_io_lsu_pkt_d_bits_dma = io_lsu_pkt_d_bits_dma; // @[lsu_lsc_ctl.scala 119:42] + assign addrcheck_io_dec_tlu_mrac_ff = io_dec_tlu_mrac_ff; // @[lsu_lsc_ctl.scala 120:42] + assign addrcheck_io_rs1_region_d = rs1_d[31:28]; // @[lsu_lsc_ctl.scala 121:42] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + access_fault_m = _RAND_0[0:0]; + _RAND_1 = {1{`RANDOM}}; + misaligned_fault_m = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + exc_mscause_m = _RAND_2[3:0]; + _RAND_3 = {1{`RANDOM}}; + fir_dccm_access_error_m = _RAND_3[0:0]; + _RAND_4 = {1{`RANDOM}}; + fir_nondccm_access_error_m = _RAND_4[0:0]; + _RAND_5 = {1{`RANDOM}}; + _T_105_valid = _RAND_5[0:0]; + _RAND_6 = {1{`RANDOM}}; + _T_105_bits_single_ecc_error = _RAND_6[0:0]; + _RAND_7 = {1{`RANDOM}}; + _T_105_bits_inst_type = _RAND_7[0:0]; + _RAND_8 = {1{`RANDOM}}; + _T_105_bits_exc_type = _RAND_8[0:0]; + _RAND_9 = {1{`RANDOM}}; + _T_105_bits_mscause = _RAND_9[3:0]; + _RAND_10 = {1{`RANDOM}}; + _T_105_bits_addr = _RAND_10[31:0]; + _RAND_11 = {1{`RANDOM}}; + _T_106 = _RAND_11[1:0]; + _RAND_12 = {1{`RANDOM}}; + _T_132_bits_fast_int = _RAND_12[0:0]; + _RAND_13 = {1{`RANDOM}}; + _T_132_bits_by = _RAND_13[0:0]; + _RAND_14 = {1{`RANDOM}}; + _T_132_bits_half = _RAND_14[0:0]; + _RAND_15 = {1{`RANDOM}}; + _T_132_bits_word = _RAND_15[0:0]; + _RAND_16 = {1{`RANDOM}}; + _T_132_bits_dword = _RAND_16[0:0]; + _RAND_17 = {1{`RANDOM}}; + _T_132_bits_load = _RAND_17[0:0]; + _RAND_18 = {1{`RANDOM}}; + _T_132_bits_store = _RAND_18[0:0]; + _RAND_19 = {1{`RANDOM}}; + _T_132_bits_unsign = _RAND_19[0:0]; + _RAND_20 = {1{`RANDOM}}; + _T_132_bits_dma = _RAND_20[0:0]; + _RAND_21 = {1{`RANDOM}}; + _T_132_bits_store_data_bypass_m = _RAND_21[0:0]; + _RAND_22 = {1{`RANDOM}}; + _T_134_bits_by = _RAND_22[0:0]; + _RAND_23 = {1{`RANDOM}}; + _T_134_bits_half = _RAND_23[0:0]; + _RAND_24 = {1{`RANDOM}}; + _T_134_bits_word = _RAND_24[0:0]; + _RAND_25 = {1{`RANDOM}}; + _T_134_bits_dword = _RAND_25[0:0]; + _RAND_26 = {1{`RANDOM}}; + _T_134_bits_load = _RAND_26[0:0]; + _RAND_27 = {1{`RANDOM}}; + _T_134_bits_store = _RAND_27[0:0]; + _RAND_28 = {1{`RANDOM}}; + _T_134_bits_unsign = _RAND_28[0:0]; + _RAND_29 = {1{`RANDOM}}; + _T_134_bits_dma = _RAND_29[0:0]; + _RAND_30 = {1{`RANDOM}}; + _T_135 = _RAND_30[0:0]; + _RAND_31 = {1{`RANDOM}}; + _T_136 = _RAND_31[0:0]; + _RAND_32 = {1{`RANDOM}}; + store_data_pre_m = _RAND_32[31:0]; + _RAND_33 = {1{`RANDOM}}; + _T_146 = _RAND_33[31:0]; + _RAND_34 = {1{`RANDOM}}; + _T_147 = _RAND_34[31:0]; + _RAND_35 = {1{`RANDOM}}; + _T_148 = _RAND_35[31:0]; + _RAND_36 = {1{`RANDOM}}; + _T_149 = _RAND_36[31:0]; + _RAND_37 = {1{`RANDOM}}; + _T_150 = _RAND_37[0:0]; + _RAND_38 = {1{`RANDOM}}; + _T_151 = _RAND_38[0:0]; + _RAND_39 = {1{`RANDOM}}; + _T_152 = _RAND_39[0:0]; + _RAND_40 = {1{`RANDOM}}; + _T_153 = _RAND_40[0:0]; + _RAND_41 = {1{`RANDOM}}; + _T_154 = _RAND_41[0:0]; + _RAND_42 = {1{`RANDOM}}; + addr_external_r = _RAND_42[0:0]; + _RAND_43 = {1{`RANDOM}}; + bus_read_data_r = _RAND_43[31:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + access_fault_m = 1'h0; + end + if (reset) begin + misaligned_fault_m = 1'h0; + end + if (reset) begin + exc_mscause_m = 4'h0; + end + if (reset) begin + fir_dccm_access_error_m = 1'h0; + end + if (reset) begin + fir_nondccm_access_error_m = 1'h0; + end + if (reset) begin + _T_105_valid = 1'h0; + end + if (reset) begin + _T_105_bits_single_ecc_error = 1'h0; + end + if (reset) begin + _T_105_bits_inst_type = 1'h0; + end + if (reset) begin + _T_105_bits_exc_type = 1'h0; + end + if (reset) begin + _T_105_bits_mscause = 4'h0; + end + if (reset) begin + _T_105_bits_addr = 32'h0; + end + if (reset) begin + _T_106 = 2'h0; + end + if (reset) begin + _T_132_bits_fast_int = 1'h0; + end + if (reset) begin + _T_132_bits_by = 1'h0; + end + if (reset) begin + _T_132_bits_half = 1'h0; + end + if (reset) begin + _T_132_bits_word = 1'h0; + end + if (reset) begin + _T_132_bits_dword = 1'h0; + end + if (reset) begin + _T_132_bits_load = 1'h0; + end + if (reset) begin + _T_132_bits_store = 1'h0; + end + if (reset) begin + _T_132_bits_unsign = 1'h0; + end + if (reset) begin + _T_132_bits_dma = 1'h0; + end + if (reset) begin + _T_132_bits_store_data_bypass_m = 1'h0; + end + if (reset) begin + _T_134_bits_by = 1'h0; + end + if (reset) begin + _T_134_bits_half = 1'h0; + end + if (reset) begin + _T_134_bits_word = 1'h0; + end + if (reset) begin + _T_134_bits_dword = 1'h0; + end + if (reset) begin + _T_134_bits_load = 1'h0; + end + if (reset) begin + _T_134_bits_store = 1'h0; + end + if (reset) begin + _T_134_bits_unsign = 1'h0; + end + if (reset) begin + _T_134_bits_dma = 1'h0; + end + if (reset) begin + _T_135 = 1'h0; + end + if (reset) begin + _T_136 = 1'h0; + end + if (reset) begin + store_data_pre_m = 32'h0; + end + if (reset) begin + _T_146 = 32'h0; + end + if (reset) begin + _T_147 = 32'h0; + end + if (reset) begin + _T_148 = 32'h0; + end + if (reset) begin + _T_149 = 32'h0; + end + if (reset) begin + _T_150 = 1'h0; + end + if (reset) begin + _T_151 = 1'h0; + end + if (reset) begin + _T_152 = 1'h0; + end + if (reset) begin + _T_153 = 1'h0; + end + if (reset) begin + _T_154 = 1'h0; + end + if (reset) begin + addr_external_r = 1'h0; + end + if (reset) begin + bus_read_data_r = 32'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + access_fault_m <= 1'h0; + end else begin + access_fault_m <= addrcheck_io_access_fault_d; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + misaligned_fault_m <= 1'h0; + end else begin + misaligned_fault_m <= addrcheck_io_misaligned_fault_d; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + exc_mscause_m <= 4'h0; + end else begin + exc_mscause_m <= addrcheck_io_exc_mscause_d; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + fir_dccm_access_error_m <= 1'h0; + end else begin + fir_dccm_access_error_m <= addrcheck_io_fir_dccm_access_error_d; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + fir_nondccm_access_error_m <= 1'h0; + end else begin + fir_nondccm_access_error_m <= addrcheck_io_fir_nondccm_access_error_d; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_105_valid <= 1'h0; + end else begin + _T_105_valid <= _T_81 & _T_82; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_105_bits_single_ecc_error <= 1'h0; + end else begin + _T_105_bits_single_ecc_error <= _T_85 & _T_78; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_105_bits_inst_type <= 1'h0; + end else begin + _T_105_bits_inst_type <= io_lsu_pkt_m_bits_store; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_105_bits_exc_type <= 1'h0; + end else begin + _T_105_bits_exc_type <= ~misaligned_fault_m; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_105_bits_mscause <= 4'h0; + end else if (_T_92) begin + _T_105_bits_mscause <= 4'h1; + end else begin + _T_105_bits_mscause <= exc_mscause_m; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_105_bits_addr <= 32'h0; + end else begin + _T_105_bits_addr <= io_lsu_addr_m; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_106 <= 2'h0; + end else if (fir_nondccm_access_error_m) begin + _T_106 <= 2'h3; + end else if (fir_dccm_access_error_m) begin + _T_106 <= 2'h2; + end else if (_T_99) begin + _T_106 <= 2'h1; + end else begin + _T_106 <= 2'h0; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_132_bits_fast_int <= 1'h0; + end else begin + _T_132_bits_fast_int <= io_lsu_pkt_d_bits_fast_int; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_132_bits_by <= 1'h0; + end else begin + _T_132_bits_by <= io_lsu_pkt_d_bits_by; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_132_bits_half <= 1'h0; + end else begin + _T_132_bits_half <= io_lsu_pkt_d_bits_half; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_132_bits_word <= 1'h0; + end else begin + _T_132_bits_word <= io_lsu_pkt_d_bits_word; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_132_bits_dword <= 1'h0; + end else begin + _T_132_bits_dword <= io_lsu_pkt_d_bits_dword; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_132_bits_load <= 1'h0; + end else begin + _T_132_bits_load <= io_lsu_pkt_d_bits_load; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_132_bits_store <= 1'h0; + end else begin + _T_132_bits_store <= io_lsu_pkt_d_bits_store; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_132_bits_unsign <= 1'h0; + end else begin + _T_132_bits_unsign <= io_lsu_pkt_d_bits_unsign; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_132_bits_dma <= 1'h0; + end else begin + _T_132_bits_dma <= io_lsu_pkt_d_bits_dma; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_132_bits_store_data_bypass_m <= 1'h0; + end else begin + _T_132_bits_store_data_bypass_m <= io_lsu_pkt_d_bits_store_data_bypass_m; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_134_bits_by <= 1'h0; + end else begin + _T_134_bits_by <= io_lsu_pkt_m_bits_by; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_134_bits_half <= 1'h0; + end else begin + _T_134_bits_half <= io_lsu_pkt_m_bits_half; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_134_bits_word <= 1'h0; + end else begin + _T_134_bits_word <= io_lsu_pkt_m_bits_word; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_134_bits_dword <= 1'h0; + end else begin + _T_134_bits_dword <= io_lsu_pkt_m_bits_dword; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_134_bits_load <= 1'h0; + end else begin + _T_134_bits_load <= io_lsu_pkt_m_bits_load; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_134_bits_store <= 1'h0; + end else begin + _T_134_bits_store <= io_lsu_pkt_m_bits_store; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_134_bits_unsign <= 1'h0; + end else begin + _T_134_bits_unsign <= io_lsu_pkt_m_bits_unsign; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_134_bits_dma <= 1'h0; + end else begin + _T_134_bits_dma <= io_lsu_pkt_m_bits_dma; + end + end + always @(posedge io_lsu_c2_m_clk or posedge reset) begin + if (reset) begin + _T_135 <= 1'h0; + end else begin + _T_135 <= io_lsu_pkt_d_valid & _T_125; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_136 <= 1'h0; + end else begin + _T_136 <= io_lsu_pkt_m_valid & _T_129; + end + end + always @(posedge io_lsu_store_c1_m_clk or posedge reset) begin + if (reset) begin + store_data_pre_m <= 32'h0; + end else if (io_lsu_pkt_d_bits_store_data_bypass_d) begin + store_data_pre_m <= io_lsu_result_m; + end else if (io_dma_lsc_ctl_dma_dccm_req) begin + store_data_pre_m <= dma_mem_wdata_shifted[31:0]; + end else begin + store_data_pre_m <= io_lsu_exu_exu_lsu_rs2_d; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_146 <= 32'h0; + end else begin + _T_146 <= io_lsu_addr_d; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_147 <= 32'h0; + end else begin + _T_147 <= io_lsu_addr_m; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_148 <= 32'h0; + end else begin + _T_148 <= io_end_addr_d; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_149 <= 32'h0; + end else begin + _T_149 <= io_end_addr_m; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_150 <= 1'h0; + end else begin + _T_150 <= io_addr_in_dccm_d; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_151 <= 1'h0; + end else begin + _T_151 <= io_addr_in_dccm_m; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_152 <= 1'h0; + end else begin + _T_152 <= io_addr_in_pic_d; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_153 <= 1'h0; + end else begin + _T_153 <= io_addr_in_pic_m; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_154 <= 1'h0; + end else begin + _T_154 <= addrcheck_io_addr_external_d; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + addr_external_r <= 1'h0; + end else begin + addr_external_r <= io_addr_external_m; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + bus_read_data_r <= 32'h0; + end else begin + bus_read_data_r <= io_bus_read_data_m; + end + end +endmodule +module rvclkhdr( + output io_l1clk, + input io_clk, + input io_en, + input io_scan_mode +); + wire clkhdr_Q; // @[lib.scala 334:26] + wire clkhdr_CK; // @[lib.scala 334:26] + wire clkhdr_EN; // @[lib.scala 334:26] + wire clkhdr_SE; // @[lib.scala 334:26] + gated_latch clkhdr ( // @[lib.scala 334:26] + .Q(clkhdr_Q), + .CK(clkhdr_CK), + .EN(clkhdr_EN), + .SE(clkhdr_SE) + ); + assign io_l1clk = clkhdr_Q; // @[lib.scala 335:14] + assign clkhdr_CK = io_clk; // @[lib.scala 336:18] + assign clkhdr_EN = io_en; // @[lib.scala 337:18] + assign clkhdr_SE = io_scan_mode; // @[lib.scala 338:18] +endmodule +module lsu_dccm_ctl( + input clock, + input reset, + input io_lsu_c2_m_clk, + input io_lsu_c2_r_clk, + input io_lsu_free_c2_clk, + input io_lsu_store_c1_r_clk, + input io_lsu_pkt_d_valid, + input io_lsu_pkt_d_bits_word, + input io_lsu_pkt_d_bits_dword, + input io_lsu_pkt_d_bits_load, + input io_lsu_pkt_d_bits_store, + input io_lsu_pkt_d_bits_dma, + input io_lsu_pkt_m_valid, + input io_lsu_pkt_m_bits_by, + input io_lsu_pkt_m_bits_half, + input io_lsu_pkt_m_bits_word, + input io_lsu_pkt_m_bits_load, + input io_lsu_pkt_m_bits_store, + input io_lsu_pkt_m_bits_dma, + input io_lsu_pkt_r_valid, + input io_lsu_pkt_r_bits_by, + input io_lsu_pkt_r_bits_half, + input io_lsu_pkt_r_bits_word, + input io_lsu_pkt_r_bits_load, + input io_lsu_pkt_r_bits_store, + input io_lsu_pkt_r_bits_dma, + input io_addr_in_dccm_d, + input io_addr_in_dccm_m, + input io_addr_in_dccm_r, + input io_addr_in_pic_d, + input io_addr_in_pic_m, + input io_addr_in_pic_r, + input io_lsu_raw_fwd_lo_r, + input io_lsu_raw_fwd_hi_r, + input io_lsu_commit_r, + input [31:0] io_lsu_addr_d, + input [15:0] io_lsu_addr_m, + input [31:0] io_lsu_addr_r, + input [15:0] io_end_addr_d, + input [15:0] io_end_addr_m, + input [15:0] io_end_addr_r, + input io_stbuf_reqvld_any, + input [15:0] io_stbuf_addr_any, + input [31:0] io_stbuf_data_any, + input [6:0] io_stbuf_ecc_any, + input [31:0] io_stbuf_fwddata_hi_m, + input [31:0] io_stbuf_fwddata_lo_m, + input [3:0] io_stbuf_fwdbyteen_lo_m, + input [3:0] io_stbuf_fwdbyteen_hi_m, + output [31:0] io_lsu_ld_data_corr_r, + input io_lsu_double_ecc_error_r, + input io_single_ecc_error_hi_r, + input io_single_ecc_error_lo_r, + input [31:0] io_sec_data_hi_r_ff, + input [31:0] io_sec_data_lo_r_ff, + input [6:0] io_sec_data_ecc_hi_r_ff, + input [6:0] io_sec_data_ecc_lo_r_ff, + output [31:0] io_dccm_rdata_hi_m, + output [31:0] io_dccm_rdata_lo_m, + output [6:0] io_dccm_data_ecc_hi_m, + output [6:0] io_dccm_data_ecc_lo_m, + output [31:0] io_lsu_ld_data_m, + input io_lsu_double_ecc_error_m, + input [31:0] io_sec_data_hi_m, + input [31:0] io_sec_data_lo_m, + input [31:0] io_store_data_m, + input io_dma_dccm_wen, + input io_dma_pic_wen, + input [2:0] io_dma_mem_tag_m, + input [31:0] io_dma_dccm_wdata_lo, + input [31:0] io_dma_dccm_wdata_hi, + input [6:0] io_dma_dccm_wdata_ecc_hi, + input [6:0] io_dma_dccm_wdata_ecc_lo, + output [31:0] io_store_data_hi_r, + output [31:0] io_store_data_lo_r, + output [31:0] io_store_datafn_hi_r, + output [31:0] io_store_datafn_lo_r, + output [31:0] io_store_data_r, + output io_ld_single_ecc_error_r, + output io_ld_single_ecc_error_r_ff, + output [31:0] io_picm_mask_data_m, + output io_lsu_stbuf_commit_any, + output io_lsu_dccm_rden_m, + input [31:0] io_dma_dccm_ctl_dma_mem_addr, + input [63:0] io_dma_dccm_ctl_dma_mem_wdata, + output io_dma_dccm_ctl_dccm_dma_rvalid, + output io_dma_dccm_ctl_dccm_dma_ecc_error, + output [2:0] io_dma_dccm_ctl_dccm_dma_rtag, + output [63:0] io_dma_dccm_ctl_dccm_dma_rdata, + output io_dccm_wren, + output io_dccm_rden, + output [15:0] io_dccm_wr_addr_lo, + output [15:0] io_dccm_wr_addr_hi, + output [15:0] io_dccm_rd_addr_lo, + output [15:0] io_dccm_rd_addr_hi, + output [38:0] io_dccm_wr_data_lo, + output [38:0] io_dccm_wr_data_hi, + input [38:0] io_dccm_rd_data_lo, + input [38:0] io_dccm_rd_data_hi, + output io_lsu_pic_picm_wren, + output io_lsu_pic_picm_rden, + output io_lsu_pic_picm_mken, + output [31:0] io_lsu_pic_picm_rdaddr, + output [31:0] io_lsu_pic_picm_wraddr, + output [31:0] io_lsu_pic_picm_wr_data, + input [31:0] io_lsu_pic_picm_rd_data, + input io_scan_mode +); +`ifdef RANDOMIZE_REG_INIT + reg [63:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_io_en; // @[lib.scala 368:23] + wire rvclkhdr_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_1_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_1_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_1_io_en; // @[lib.scala 368:23] + wire rvclkhdr_1_io_scan_mode; // @[lib.scala 368:23] + wire [63:0] picm_rd_data_m = {io_lsu_pic_picm_rd_data,io_lsu_pic_picm_rd_data}; // @[Cat.scala 29:58] + wire [63:0] dccm_rdata_corr_m = {io_sec_data_hi_m,io_sec_data_lo_m}; // @[Cat.scala 29:58] + wire [63:0] dccm_rdata_m = {io_dccm_rdata_hi_m,io_dccm_rdata_lo_m}; // @[Cat.scala 29:58] + wire _T = io_lsu_pkt_m_valid & io_lsu_pkt_m_bits_load; // @[lsu_dccm_ctl.scala 137:63] + reg [63:0] _T_2; // @[lsu_dccm_ctl.scala 147:65] + wire [7:0] _T_3 = {io_stbuf_fwdbyteen_hi_m,io_stbuf_fwdbyteen_lo_m}; // @[Cat.scala 29:58] + wire [63:0] _T_6 = {io_stbuf_fwddata_hi_m,io_stbuf_fwddata_lo_m}; // @[Cat.scala 29:58] + wire [7:0] _T_11 = io_addr_in_pic_m ? picm_rd_data_m[7:0] : dccm_rdata_corr_m[7:0]; // @[lsu_dccm_ctl.scala 148:213] + wire [7:0] _T_12 = _T_3[0] ? _T_6[7:0] : _T_11; // @[lsu_dccm_ctl.scala 148:78] + wire [7:0] _T_16 = {{4'd0}, _T_12[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_18 = {_T_12[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_20 = _T_18 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_21 = _T_16 | _T_20; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_0 = {{2'd0}, _T_21[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_26 = _GEN_0 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_28 = {_T_21[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_30 = _T_28 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_31 = _T_26 | _T_30; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_1 = {{1'd0}, _T_31[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_36 = _GEN_1 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_38 = {_T_31[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_40 = _T_38 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_41 = _T_36 | _T_40; // @[Bitwise.scala 103:39] + wire [7:0] _T_50 = io_addr_in_pic_m ? picm_rd_data_m[15:8] : dccm_rdata_corr_m[15:8]; // @[lsu_dccm_ctl.scala 148:213] + wire [7:0] _T_51 = _T_3[1] ? _T_6[15:8] : _T_50; // @[lsu_dccm_ctl.scala 148:78] + wire [7:0] _T_55 = {{4'd0}, _T_51[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_57 = {_T_51[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_59 = _T_57 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_60 = _T_55 | _T_59; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_2 = {{2'd0}, _T_60[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_65 = _GEN_2 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_67 = {_T_60[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_69 = _T_67 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_70 = _T_65 | _T_69; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_3 = {{1'd0}, _T_70[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_75 = _GEN_3 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_77 = {_T_70[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_79 = _T_77 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_80 = _T_75 | _T_79; // @[Bitwise.scala 103:39] + wire [7:0] _T_89 = io_addr_in_pic_m ? picm_rd_data_m[23:16] : dccm_rdata_corr_m[23:16]; // @[lsu_dccm_ctl.scala 148:213] + wire [7:0] _T_90 = _T_3[2] ? _T_6[23:16] : _T_89; // @[lsu_dccm_ctl.scala 148:78] + wire [7:0] _T_94 = {{4'd0}, _T_90[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_96 = {_T_90[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_98 = _T_96 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_99 = _T_94 | _T_98; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_4 = {{2'd0}, _T_99[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_104 = _GEN_4 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_106 = {_T_99[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_108 = _T_106 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_109 = _T_104 | _T_108; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_5 = {{1'd0}, _T_109[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_114 = _GEN_5 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_116 = {_T_109[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_118 = _T_116 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_119 = _T_114 | _T_118; // @[Bitwise.scala 103:39] + wire [7:0] _T_128 = io_addr_in_pic_m ? picm_rd_data_m[31:24] : dccm_rdata_corr_m[31:24]; // @[lsu_dccm_ctl.scala 148:213] + wire [7:0] _T_129 = _T_3[3] ? _T_6[31:24] : _T_128; // @[lsu_dccm_ctl.scala 148:78] + wire [7:0] _T_133 = {{4'd0}, _T_129[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_135 = {_T_129[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_137 = _T_135 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_138 = _T_133 | _T_137; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_6 = {{2'd0}, _T_138[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_143 = _GEN_6 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_145 = {_T_138[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_147 = _T_145 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_148 = _T_143 | _T_147; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_7 = {{1'd0}, _T_148[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_153 = _GEN_7 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_155 = {_T_148[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_157 = _T_155 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_158 = _T_153 | _T_157; // @[Bitwise.scala 103:39] + wire [7:0] _T_167 = io_addr_in_pic_m ? picm_rd_data_m[39:32] : dccm_rdata_corr_m[39:32]; // @[lsu_dccm_ctl.scala 148:213] + wire [7:0] _T_168 = _T_3[4] ? _T_6[39:32] : _T_167; // @[lsu_dccm_ctl.scala 148:78] + wire [7:0] _T_172 = {{4'd0}, _T_168[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_174 = {_T_168[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_176 = _T_174 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_177 = _T_172 | _T_176; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_8 = {{2'd0}, _T_177[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_182 = _GEN_8 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_184 = {_T_177[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_186 = _T_184 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_187 = _T_182 | _T_186; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_9 = {{1'd0}, _T_187[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_192 = _GEN_9 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_194 = {_T_187[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_196 = _T_194 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_197 = _T_192 | _T_196; // @[Bitwise.scala 103:39] + wire [7:0] _T_206 = io_addr_in_pic_m ? picm_rd_data_m[47:40] : dccm_rdata_corr_m[47:40]; // @[lsu_dccm_ctl.scala 148:213] + wire [7:0] _T_207 = _T_3[5] ? _T_6[47:40] : _T_206; // @[lsu_dccm_ctl.scala 148:78] + wire [7:0] _T_211 = {{4'd0}, _T_207[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_213 = {_T_207[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_215 = _T_213 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_216 = _T_211 | _T_215; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_10 = {{2'd0}, _T_216[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_221 = _GEN_10 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_223 = {_T_216[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_225 = _T_223 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_226 = _T_221 | _T_225; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_11 = {{1'd0}, _T_226[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_231 = _GEN_11 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_233 = {_T_226[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_235 = _T_233 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_236 = _T_231 | _T_235; // @[Bitwise.scala 103:39] + wire [7:0] _T_245 = io_addr_in_pic_m ? picm_rd_data_m[55:48] : dccm_rdata_corr_m[55:48]; // @[lsu_dccm_ctl.scala 148:213] + wire [7:0] _T_246 = _T_3[6] ? _T_6[55:48] : _T_245; // @[lsu_dccm_ctl.scala 148:78] + wire [7:0] _T_250 = {{4'd0}, _T_246[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_252 = {_T_246[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_254 = _T_252 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_255 = _T_250 | _T_254; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_12 = {{2'd0}, _T_255[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_260 = _GEN_12 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_262 = {_T_255[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_264 = _T_262 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_265 = _T_260 | _T_264; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_13 = {{1'd0}, _T_265[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_270 = _GEN_13 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_272 = {_T_265[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_274 = _T_272 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_275 = _T_270 | _T_274; // @[Bitwise.scala 103:39] + wire [7:0] _T_284 = io_addr_in_pic_m ? picm_rd_data_m[63:56] : dccm_rdata_corr_m[63:56]; // @[lsu_dccm_ctl.scala 148:213] + wire [7:0] _T_285 = _T_3[7] ? _T_6[63:56] : _T_284; // @[lsu_dccm_ctl.scala 148:78] + wire [7:0] _T_289 = {{4'd0}, _T_285[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_291 = {_T_285[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_293 = _T_291 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_294 = _T_289 | _T_293; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_14 = {{2'd0}, _T_294[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_299 = _GEN_14 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_301 = {_T_294[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_303 = _T_301 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_304 = _T_299 | _T_303; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_15 = {{1'd0}, _T_304[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_309 = _GEN_15 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_311 = {_T_304[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_313 = _T_311 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_314 = _T_309 | _T_313; // @[Bitwise.scala 103:39] + wire [63:0] _T_322 = {_T_41,_T_80,_T_119,_T_158,_T_197,_T_236,_T_275,_T_314}; // @[Cat.scala 29:58] + wire [63:0] _T_326 = {{32'd0}, _T_322[63:32]}; // @[Bitwise.scala 103:31] + wire [63:0] _T_328 = {_T_322[31:0], 32'h0}; // @[Bitwise.scala 103:65] + wire [63:0] _T_330 = _T_328 & 64'hffffffff00000000; // @[Bitwise.scala 103:75] + wire [63:0] _T_331 = _T_326 | _T_330; // @[Bitwise.scala 103:39] + wire [63:0] _GEN_16 = {{16'd0}, _T_331[63:16]}; // @[Bitwise.scala 103:31] + wire [63:0] _T_336 = _GEN_16 & 64'hffff0000ffff; // @[Bitwise.scala 103:31] + wire [63:0] _T_338 = {_T_331[47:0], 16'h0}; // @[Bitwise.scala 103:65] + wire [63:0] _T_340 = _T_338 & 64'hffff0000ffff0000; // @[Bitwise.scala 103:75] + wire [63:0] _T_341 = _T_336 | _T_340; // @[Bitwise.scala 103:39] + wire [63:0] _GEN_17 = {{8'd0}, _T_341[63:8]}; // @[Bitwise.scala 103:31] + wire [63:0] _T_346 = _GEN_17 & 64'hff00ff00ff00ff; // @[Bitwise.scala 103:31] + wire [63:0] _T_348 = {_T_341[55:0], 8'h0}; // @[Bitwise.scala 103:65] + wire [63:0] _T_350 = _T_348 & 64'hff00ff00ff00ff00; // @[Bitwise.scala 103:75] + wire [63:0] _T_351 = _T_346 | _T_350; // @[Bitwise.scala 103:39] + wire [63:0] _GEN_18 = {{4'd0}, _T_351[63:4]}; // @[Bitwise.scala 103:31] + wire [63:0] _T_356 = _GEN_18 & 64'hf0f0f0f0f0f0f0f; // @[Bitwise.scala 103:31] + wire [63:0] _T_358 = {_T_351[59:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [63:0] _T_360 = _T_358 & 64'hf0f0f0f0f0f0f0f0; // @[Bitwise.scala 103:75] + wire [63:0] _T_361 = _T_356 | _T_360; // @[Bitwise.scala 103:39] + wire [63:0] _GEN_19 = {{2'd0}, _T_361[63:2]}; // @[Bitwise.scala 103:31] + wire [63:0] _T_366 = _GEN_19 & 64'h3333333333333333; // @[Bitwise.scala 103:31] + wire [63:0] _T_368 = {_T_361[61:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [63:0] _T_370 = _T_368 & 64'hcccccccccccccccc; // @[Bitwise.scala 103:75] + wire [63:0] _T_371 = _T_366 | _T_370; // @[Bitwise.scala 103:39] + wire [63:0] _GEN_20 = {{1'd0}, _T_371[63:1]}; // @[Bitwise.scala 103:31] + wire [63:0] _T_376 = _GEN_20 & 64'h5555555555555555; // @[Bitwise.scala 103:31] + wire [63:0] _T_378 = {_T_371[62:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [63:0] _T_380 = _T_378 & 64'haaaaaaaaaaaaaaaa; // @[Bitwise.scala 103:75] + wire [63:0] lsu_rdata_corr_m = _T_376 | _T_380; // @[Bitwise.scala 103:39] + wire [7:0] _T_390 = io_addr_in_pic_m ? picm_rd_data_m[7:0] : dccm_rdata_m[7:0]; // @[lsu_dccm_ctl.scala 149:213] + wire [7:0] _T_391 = _T_3[0] ? _T_6[7:0] : _T_390; // @[lsu_dccm_ctl.scala 149:78] + wire [7:0] _T_395 = {{4'd0}, _T_391[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_397 = {_T_391[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_399 = _T_397 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_400 = _T_395 | _T_399; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_21 = {{2'd0}, _T_400[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_405 = _GEN_21 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_407 = {_T_400[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_409 = _T_407 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_410 = _T_405 | _T_409; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_22 = {{1'd0}, _T_410[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_415 = _GEN_22 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_417 = {_T_410[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_419 = _T_417 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_420 = _T_415 | _T_419; // @[Bitwise.scala 103:39] + wire [7:0] _T_429 = io_addr_in_pic_m ? picm_rd_data_m[15:8] : dccm_rdata_m[15:8]; // @[lsu_dccm_ctl.scala 149:213] + wire [7:0] _T_430 = _T_3[1] ? _T_6[15:8] : _T_429; // @[lsu_dccm_ctl.scala 149:78] + wire [7:0] _T_434 = {{4'd0}, _T_430[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_436 = {_T_430[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_438 = _T_436 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_439 = _T_434 | _T_438; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_23 = {{2'd0}, _T_439[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_444 = _GEN_23 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_446 = {_T_439[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_448 = _T_446 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_449 = _T_444 | _T_448; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_24 = {{1'd0}, _T_449[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_454 = _GEN_24 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_456 = {_T_449[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_458 = _T_456 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_459 = _T_454 | _T_458; // @[Bitwise.scala 103:39] + wire [7:0] _T_468 = io_addr_in_pic_m ? picm_rd_data_m[23:16] : dccm_rdata_m[23:16]; // @[lsu_dccm_ctl.scala 149:213] + wire [7:0] _T_469 = _T_3[2] ? _T_6[23:16] : _T_468; // @[lsu_dccm_ctl.scala 149:78] + wire [7:0] _T_473 = {{4'd0}, _T_469[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_475 = {_T_469[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_477 = _T_475 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_478 = _T_473 | _T_477; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_25 = {{2'd0}, _T_478[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_483 = _GEN_25 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_485 = {_T_478[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_487 = _T_485 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_488 = _T_483 | _T_487; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_26 = {{1'd0}, _T_488[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_493 = _GEN_26 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_495 = {_T_488[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_497 = _T_495 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_498 = _T_493 | _T_497; // @[Bitwise.scala 103:39] + wire [7:0] _T_507 = io_addr_in_pic_m ? picm_rd_data_m[31:24] : dccm_rdata_m[31:24]; // @[lsu_dccm_ctl.scala 149:213] + wire [7:0] _T_508 = _T_3[3] ? _T_6[31:24] : _T_507; // @[lsu_dccm_ctl.scala 149:78] + wire [7:0] _T_512 = {{4'd0}, _T_508[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_514 = {_T_508[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_516 = _T_514 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_517 = _T_512 | _T_516; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_27 = {{2'd0}, _T_517[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_522 = _GEN_27 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_524 = {_T_517[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_526 = _T_524 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_527 = _T_522 | _T_526; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_28 = {{1'd0}, _T_527[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_532 = _GEN_28 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_534 = {_T_527[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_536 = _T_534 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_537 = _T_532 | _T_536; // @[Bitwise.scala 103:39] + wire [7:0] _T_546 = io_addr_in_pic_m ? picm_rd_data_m[39:32] : dccm_rdata_m[39:32]; // @[lsu_dccm_ctl.scala 149:213] + wire [7:0] _T_547 = _T_3[4] ? _T_6[39:32] : _T_546; // @[lsu_dccm_ctl.scala 149:78] + wire [7:0] _T_551 = {{4'd0}, _T_547[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_553 = {_T_547[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_555 = _T_553 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_556 = _T_551 | _T_555; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_29 = {{2'd0}, _T_556[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_561 = _GEN_29 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_563 = {_T_556[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_565 = _T_563 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_566 = _T_561 | _T_565; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_30 = {{1'd0}, _T_566[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_571 = _GEN_30 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_573 = {_T_566[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_575 = _T_573 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_576 = _T_571 | _T_575; // @[Bitwise.scala 103:39] + wire [7:0] _T_585 = io_addr_in_pic_m ? picm_rd_data_m[47:40] : dccm_rdata_m[47:40]; // @[lsu_dccm_ctl.scala 149:213] + wire [7:0] _T_586 = _T_3[5] ? _T_6[47:40] : _T_585; // @[lsu_dccm_ctl.scala 149:78] + wire [7:0] _T_590 = {{4'd0}, _T_586[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_592 = {_T_586[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_594 = _T_592 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_595 = _T_590 | _T_594; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_31 = {{2'd0}, _T_595[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_600 = _GEN_31 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_602 = {_T_595[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_604 = _T_602 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_605 = _T_600 | _T_604; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_32 = {{1'd0}, _T_605[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_610 = _GEN_32 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_612 = {_T_605[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_614 = _T_612 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_615 = _T_610 | _T_614; // @[Bitwise.scala 103:39] + wire [7:0] _T_624 = io_addr_in_pic_m ? picm_rd_data_m[55:48] : dccm_rdata_m[55:48]; // @[lsu_dccm_ctl.scala 149:213] + wire [7:0] _T_625 = _T_3[6] ? _T_6[55:48] : _T_624; // @[lsu_dccm_ctl.scala 149:78] + wire [7:0] _T_629 = {{4'd0}, _T_625[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_631 = {_T_625[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_633 = _T_631 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_634 = _T_629 | _T_633; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_33 = {{2'd0}, _T_634[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_639 = _GEN_33 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_641 = {_T_634[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_643 = _T_641 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_644 = _T_639 | _T_643; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_34 = {{1'd0}, _T_644[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_649 = _GEN_34 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_651 = {_T_644[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_653 = _T_651 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_654 = _T_649 | _T_653; // @[Bitwise.scala 103:39] + wire [7:0] _T_663 = io_addr_in_pic_m ? picm_rd_data_m[63:56] : dccm_rdata_m[63:56]; // @[lsu_dccm_ctl.scala 149:213] + wire [7:0] _T_664 = _T_3[7] ? _T_6[63:56] : _T_663; // @[lsu_dccm_ctl.scala 149:78] + wire [7:0] _T_668 = {{4'd0}, _T_664[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_670 = {_T_664[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_672 = _T_670 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_673 = _T_668 | _T_672; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_35 = {{2'd0}, _T_673[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_678 = _GEN_35 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_680 = {_T_673[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_682 = _T_680 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_683 = _T_678 | _T_682; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_36 = {{1'd0}, _T_683[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_688 = _GEN_36 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_690 = {_T_683[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_692 = _T_690 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_693 = _T_688 | _T_692; // @[Bitwise.scala 103:39] + wire [63:0] _T_701 = {_T_420,_T_459,_T_498,_T_537,_T_576,_T_615,_T_654,_T_693}; // @[Cat.scala 29:58] + wire [63:0] _T_705 = {{32'd0}, _T_701[63:32]}; // @[Bitwise.scala 103:31] + wire [63:0] _T_707 = {_T_701[31:0], 32'h0}; // @[Bitwise.scala 103:65] + wire [63:0] _T_709 = _T_707 & 64'hffffffff00000000; // @[Bitwise.scala 103:75] + wire [63:0] _T_710 = _T_705 | _T_709; // @[Bitwise.scala 103:39] + wire [63:0] _GEN_37 = {{16'd0}, _T_710[63:16]}; // @[Bitwise.scala 103:31] + wire [63:0] _T_715 = _GEN_37 & 64'hffff0000ffff; // @[Bitwise.scala 103:31] + wire [63:0] _T_717 = {_T_710[47:0], 16'h0}; // @[Bitwise.scala 103:65] + wire [63:0] _T_719 = _T_717 & 64'hffff0000ffff0000; // @[Bitwise.scala 103:75] + wire [63:0] _T_720 = _T_715 | _T_719; // @[Bitwise.scala 103:39] + wire [63:0] _GEN_38 = {{8'd0}, _T_720[63:8]}; // @[Bitwise.scala 103:31] + wire [63:0] _T_725 = _GEN_38 & 64'hff00ff00ff00ff; // @[Bitwise.scala 103:31] + wire [63:0] _T_727 = {_T_720[55:0], 8'h0}; // @[Bitwise.scala 103:65] + wire [63:0] _T_729 = _T_727 & 64'hff00ff00ff00ff00; // @[Bitwise.scala 103:75] + wire [63:0] _T_730 = _T_725 | _T_729; // @[Bitwise.scala 103:39] + wire [63:0] _GEN_39 = {{4'd0}, _T_730[63:4]}; // @[Bitwise.scala 103:31] + wire [63:0] _T_735 = _GEN_39 & 64'hf0f0f0f0f0f0f0f; // @[Bitwise.scala 103:31] + wire [63:0] _T_737 = {_T_730[59:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [63:0] _T_739 = _T_737 & 64'hf0f0f0f0f0f0f0f0; // @[Bitwise.scala 103:75] + wire [63:0] _T_740 = _T_735 | _T_739; // @[Bitwise.scala 103:39] + wire [63:0] _GEN_40 = {{2'd0}, _T_740[63:2]}; // @[Bitwise.scala 103:31] + wire [63:0] _T_745 = _GEN_40 & 64'h3333333333333333; // @[Bitwise.scala 103:31] + wire [63:0] _T_747 = {_T_740[61:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [63:0] _T_749 = _T_747 & 64'hcccccccccccccccc; // @[Bitwise.scala 103:75] + wire [63:0] _T_750 = _T_745 | _T_749; // @[Bitwise.scala 103:39] + wire [63:0] _GEN_41 = {{1'd0}, _T_750[63:1]}; // @[Bitwise.scala 103:31] + wire [63:0] _T_755 = _GEN_41 & 64'h5555555555555555; // @[Bitwise.scala 103:31] + wire [63:0] _T_757 = {_T_750[62:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [63:0] _T_759 = _T_757 & 64'haaaaaaaaaaaaaaaa; // @[Bitwise.scala 103:75] + wire [63:0] lsu_rdata_m = _T_755 | _T_759; // @[Bitwise.scala 103:39] + wire [3:0] _GEN_42 = {{2'd0}, io_lsu_addr_m[1:0]}; // @[lsu_dccm_ctl.scala 150:49] + wire [5:0] _T_762 = 4'h8 * _GEN_42; // @[lsu_dccm_ctl.scala 150:49] + wire [63:0] _T_763 = lsu_rdata_m >> _T_762; // @[lsu_dccm_ctl.scala 150:43] + wire _T_769 = io_lsu_addr_d[15:2] == io_lsu_addr_r[15:2]; // @[lsu_dccm_ctl.scala 155:60] + wire _T_772 = io_end_addr_d[15:2] == io_lsu_addr_r[15:2]; // @[lsu_dccm_ctl.scala 155:133] + wire _T_773 = _T_769 | _T_772; // @[lsu_dccm_ctl.scala 155:101] + wire _T_774 = _T_773 & io_lsu_pkt_d_valid; // @[lsu_dccm_ctl.scala 155:175] + wire _T_775 = _T_774 & io_lsu_pkt_d_bits_store; // @[lsu_dccm_ctl.scala 155:196] + wire _T_776 = _T_775 & io_lsu_pkt_d_bits_dma; // @[lsu_dccm_ctl.scala 155:222] + wire _T_777 = _T_776 & io_addr_in_dccm_d; // @[lsu_dccm_ctl.scala 155:246] + wire _T_780 = io_lsu_addr_m[15:2] == io_lsu_addr_r[15:2]; // @[lsu_dccm_ctl.scala 156:37] + wire _T_783 = io_end_addr_m[15:2] == io_lsu_addr_r[15:2]; // @[lsu_dccm_ctl.scala 156:110] + wire _T_784 = _T_780 | _T_783; // @[lsu_dccm_ctl.scala 156:78] + wire _T_785 = _T_784 & io_lsu_pkt_m_valid; // @[lsu_dccm_ctl.scala 156:152] + wire _T_786 = _T_785 & io_lsu_pkt_m_bits_store; // @[lsu_dccm_ctl.scala 156:173] + wire _T_787 = _T_786 & io_lsu_pkt_m_bits_dma; // @[lsu_dccm_ctl.scala 156:199] + wire _T_788 = _T_787 & io_addr_in_dccm_m; // @[lsu_dccm_ctl.scala 156:223] + wire kill_ecc_corr_lo_r = _T_777 | _T_788; // @[lsu_dccm_ctl.scala 155:267] + wire _T_791 = io_lsu_addr_d[15:2] == io_end_addr_r[15:2]; // @[lsu_dccm_ctl.scala 158:60] + wire _T_794 = io_end_addr_d[15:2] == io_end_addr_r[15:2]; // @[lsu_dccm_ctl.scala 158:133] + wire _T_795 = _T_791 | _T_794; // @[lsu_dccm_ctl.scala 158:101] + wire _T_796 = _T_795 & io_lsu_pkt_d_valid; // @[lsu_dccm_ctl.scala 158:175] + wire _T_797 = _T_796 & io_lsu_pkt_d_bits_store; // @[lsu_dccm_ctl.scala 158:196] + wire _T_798 = _T_797 & io_lsu_pkt_d_bits_dma; // @[lsu_dccm_ctl.scala 158:222] + wire _T_799 = _T_798 & io_addr_in_dccm_d; // @[lsu_dccm_ctl.scala 158:246] + wire _T_802 = io_lsu_addr_m[15:2] == io_end_addr_r[15:2]; // @[lsu_dccm_ctl.scala 159:37] + wire _T_805 = io_end_addr_m[15:2] == io_end_addr_r[15:2]; // @[lsu_dccm_ctl.scala 159:110] + wire _T_806 = _T_802 | _T_805; // @[lsu_dccm_ctl.scala 159:78] + wire _T_807 = _T_806 & io_lsu_pkt_m_valid; // @[lsu_dccm_ctl.scala 159:152] + wire _T_808 = _T_807 & io_lsu_pkt_m_bits_store; // @[lsu_dccm_ctl.scala 159:173] + wire _T_809 = _T_808 & io_lsu_pkt_m_bits_dma; // @[lsu_dccm_ctl.scala 159:199] + wire _T_810 = _T_809 & io_addr_in_dccm_m; // @[lsu_dccm_ctl.scala 159:223] + wire kill_ecc_corr_hi_r = _T_799 | _T_810; // @[lsu_dccm_ctl.scala 158:267] + wire _T_811 = io_lsu_pkt_r_bits_load & io_single_ecc_error_lo_r; // @[lsu_dccm_ctl.scala 161:60] + wire _T_812 = ~io_lsu_raw_fwd_lo_r; // @[lsu_dccm_ctl.scala 161:89] + wire ld_single_ecc_error_lo_r = _T_811 & _T_812; // @[lsu_dccm_ctl.scala 161:87] + wire _T_813 = io_lsu_pkt_r_bits_load & io_single_ecc_error_hi_r; // @[lsu_dccm_ctl.scala 162:60] + wire _T_814 = ~io_lsu_raw_fwd_hi_r; // @[lsu_dccm_ctl.scala 162:89] + wire ld_single_ecc_error_hi_r = _T_813 & _T_814; // @[lsu_dccm_ctl.scala 162:87] + wire _T_815 = ld_single_ecc_error_lo_r | ld_single_ecc_error_hi_r; // @[lsu_dccm_ctl.scala 163:63] + wire _T_816 = ~io_lsu_double_ecc_error_r; // @[lsu_dccm_ctl.scala 163:93] + wire _T_818 = io_lsu_commit_r | io_lsu_pkt_r_bits_dma; // @[lsu_dccm_ctl.scala 164:81] + wire _T_819 = ld_single_ecc_error_lo_r & _T_818; // @[lsu_dccm_ctl.scala 164:62] + wire _T_820 = ~kill_ecc_corr_lo_r; // @[lsu_dccm_ctl.scala 164:108] + wire _T_822 = ld_single_ecc_error_hi_r & _T_818; // @[lsu_dccm_ctl.scala 165:62] + wire _T_823 = ~kill_ecc_corr_hi_r; // @[lsu_dccm_ctl.scala 165:108] + reg lsu_double_ecc_error_r_ff; // @[lsu_dccm_ctl.scala 167:74] + reg ld_single_ecc_error_hi_r_ff; // @[lsu_dccm_ctl.scala 168:74] + reg ld_single_ecc_error_lo_r_ff; // @[lsu_dccm_ctl.scala 169:74] + reg [15:0] ld_sec_addr_hi_r_ff; // @[lib.scala 374:16] + reg [15:0] ld_sec_addr_lo_r_ff; // @[lib.scala 374:16] + wire _T_830 = io_lsu_pkt_d_bits_word | io_lsu_pkt_d_bits_dword; // @[lsu_dccm_ctl.scala 173:125] + wire _T_831 = ~_T_830; // @[lsu_dccm_ctl.scala 173:100] + wire _T_833 = io_lsu_addr_d[1:0] != 2'h0; // @[lsu_dccm_ctl.scala 173:174] + wire _T_834 = _T_831 | _T_833; // @[lsu_dccm_ctl.scala 173:152] + wire _T_835 = io_lsu_pkt_d_bits_store & _T_834; // @[lsu_dccm_ctl.scala 173:97] + wire _T_836 = io_lsu_pkt_d_bits_load | _T_835; // @[lsu_dccm_ctl.scala 173:70] + wire _T_837 = io_lsu_pkt_d_valid & _T_836; // @[lsu_dccm_ctl.scala 173:44] + wire lsu_dccm_rden_d = _T_837 & io_addr_in_dccm_d; // @[lsu_dccm_ctl.scala 173:191] + wire _T_838 = ld_single_ecc_error_lo_r_ff | ld_single_ecc_error_hi_r_ff; // @[lsu_dccm_ctl.scala 176:63] + wire _T_839 = ~lsu_double_ecc_error_r_ff; // @[lsu_dccm_ctl.scala 176:96] + wire _T_841 = lsu_dccm_rden_d | io_dma_dccm_wen; // @[lsu_dccm_ctl.scala 177:75] + wire _T_842 = _T_841 | io_ld_single_ecc_error_r_ff; // @[lsu_dccm_ctl.scala 177:93] + wire _T_843 = ~_T_842; // @[lsu_dccm_ctl.scala 177:57] + wire _T_846 = io_stbuf_addr_any[3:2] == io_lsu_addr_d[3:2]; // @[lsu_dccm_ctl.scala 178:95] + wire _T_849 = io_stbuf_addr_any[3:2] == io_end_addr_d[3:2]; // @[lsu_dccm_ctl.scala 179:76] + wire _T_850 = _T_846 | _T_849; // @[lsu_dccm_ctl.scala 178:171] + wire _T_851 = ~_T_850; // @[lsu_dccm_ctl.scala 178:24] + wire _T_852 = lsu_dccm_rden_d & _T_851; // @[lsu_dccm_ctl.scala 178:22] + wire _T_853 = _T_843 | _T_852; // @[lsu_dccm_ctl.scala 177:124] + wire _T_855 = io_dma_dccm_wen | io_lsu_stbuf_commit_any; // @[lsu_dccm_ctl.scala 183:41] + wire [15:0] _T_862 = ld_single_ecc_error_lo_r_ff ? ld_sec_addr_lo_r_ff : ld_sec_addr_hi_r_ff; // @[lsu_dccm_ctl.scala 187:8] + wire [15:0] _T_866 = io_dma_dccm_wen ? io_lsu_addr_d[15:0] : io_stbuf_addr_any; // @[lsu_dccm_ctl.scala 188:8] + wire [15:0] _T_872 = ld_single_ecc_error_hi_r_ff ? ld_sec_addr_hi_r_ff : ld_sec_addr_lo_r_ff; // @[lsu_dccm_ctl.scala 191:8] + wire [15:0] _T_876 = io_dma_dccm_wen ? io_end_addr_d : io_stbuf_addr_any; // @[lsu_dccm_ctl.scala 192:8] + wire [38:0] _T_884 = {io_sec_data_ecc_lo_r_ff,io_sec_data_lo_r_ff}; // @[Cat.scala 29:58] + wire [38:0] _T_887 = {io_sec_data_ecc_hi_r_ff,io_sec_data_hi_r_ff}; // @[Cat.scala 29:58] + wire [38:0] _T_888 = ld_single_ecc_error_lo_r_ff ? _T_884 : _T_887; // @[lsu_dccm_ctl.scala 198:8] + wire [38:0] _T_892 = {io_dma_dccm_wdata_ecc_lo,io_dma_dccm_wdata_lo}; // @[Cat.scala 29:58] + wire [38:0] _T_895 = {io_stbuf_ecc_any,io_stbuf_data_any}; // @[Cat.scala 29:58] + wire [38:0] _T_896 = io_dma_dccm_wen ? _T_892 : _T_895; // @[lsu_dccm_ctl.scala 200:8] + wire [38:0] _T_906 = ld_single_ecc_error_hi_r_ff ? _T_887 : _T_884; // @[lsu_dccm_ctl.scala 204:8] + wire [38:0] _T_910 = {io_dma_dccm_wdata_ecc_hi,io_dma_dccm_wdata_hi}; // @[Cat.scala 29:58] + wire [38:0] _T_914 = io_dma_dccm_wen ? _T_910 : _T_895; // @[lsu_dccm_ctl.scala 206:8] + wire [3:0] _T_917 = io_lsu_pkt_m_bits_store ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_919 = io_lsu_pkt_m_bits_by ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_920 = _T_919 & 4'h1; // @[lsu_dccm_ctl.scala 210:94] + wire [3:0] _T_922 = io_lsu_pkt_m_bits_half ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_923 = _T_922 & 4'h3; // @[lsu_dccm_ctl.scala 211:38] + wire [3:0] _T_924 = _T_920 | _T_923; // @[lsu_dccm_ctl.scala 210:107] + wire [3:0] _T_926 = io_lsu_pkt_m_bits_word ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_928 = _T_924 | _T_926; // @[lsu_dccm_ctl.scala 211:51] + wire [3:0] store_byteen_m = _T_917 & _T_928; // @[lsu_dccm_ctl.scala 210:58] + wire [3:0] _T_930 = io_lsu_pkt_r_bits_store ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_932 = io_lsu_pkt_r_bits_by ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_933 = _T_932 & 4'h1; // @[lsu_dccm_ctl.scala 214:94] + wire [3:0] _T_935 = io_lsu_pkt_r_bits_half ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_936 = _T_935 & 4'h3; // @[lsu_dccm_ctl.scala 215:38] + wire [3:0] _T_937 = _T_933 | _T_936; // @[lsu_dccm_ctl.scala 214:107] + wire [3:0] _T_939 = io_lsu_pkt_r_bits_word ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_941 = _T_937 | _T_939; // @[lsu_dccm_ctl.scala 215:51] + wire [3:0] store_byteen_r = _T_930 & _T_941; // @[lsu_dccm_ctl.scala 214:58] + wire [6:0] _GEN_44 = {{3'd0}, store_byteen_m}; // @[lsu_dccm_ctl.scala 218:45] + wire [6:0] _T_944 = _GEN_44 << io_lsu_addr_m[1:0]; // @[lsu_dccm_ctl.scala 218:45] + wire [6:0] _GEN_45 = {{3'd0}, store_byteen_r}; // @[lsu_dccm_ctl.scala 220:45] + wire [6:0] _T_947 = _GEN_45 << io_lsu_addr_r[1:0]; // @[lsu_dccm_ctl.scala 220:45] + wire _T_950 = io_stbuf_addr_any[15:2] == io_lsu_addr_m[15:2]; // @[lsu_dccm_ctl.scala 223:67] + wire dccm_wr_bypass_d_m_lo = _T_950 & io_addr_in_dccm_m; // @[lsu_dccm_ctl.scala 223:101] + wire _T_953 = io_stbuf_addr_any[15:2] == io_end_addr_m[15:2]; // @[lsu_dccm_ctl.scala 224:67] + wire dccm_wr_bypass_d_m_hi = _T_953 & io_addr_in_dccm_m; // @[lsu_dccm_ctl.scala 224:101] + wire _T_956 = io_stbuf_addr_any[15:2] == io_lsu_addr_r[15:2]; // @[lsu_dccm_ctl.scala 226:67] + wire dccm_wr_bypass_d_r_lo = _T_956 & io_addr_in_dccm_r; // @[lsu_dccm_ctl.scala 226:101] + wire _T_959 = io_stbuf_addr_any[15:2] == io_end_addr_r[15:2]; // @[lsu_dccm_ctl.scala 227:67] + wire dccm_wr_bypass_d_r_hi = _T_959 & io_addr_in_dccm_r; // @[lsu_dccm_ctl.scala 227:101] + wire [63:0] _T_962 = {32'h0,io_store_data_m}; // @[Cat.scala 29:58] + wire [126:0] _GEN_47 = {{63'd0}, _T_962}; // @[lsu_dccm_ctl.scala 256:72] + wire [126:0] _T_965 = _GEN_47 << _T_762; // @[lsu_dccm_ctl.scala 256:72] + wire [63:0] store_data_pre_m = _T_965[63:0]; // @[lsu_dccm_ctl.scala 256:29] + wire [31:0] store_data_hi_m = store_data_pre_m[63:32]; // @[lsu_dccm_ctl.scala 257:48] + wire [31:0] store_data_lo_m = store_data_pre_m[31:0]; // @[lsu_dccm_ctl.scala 258:48] + wire [7:0] store_byteen_ext_m = {{1'd0}, _T_944}; // @[lsu_dccm_ctl.scala 218:22] + wire _T_971 = io_lsu_stbuf_commit_any & dccm_wr_bypass_d_m_lo; // @[lsu_dccm_ctl.scala 259:211] + wire [7:0] _T_975 = _T_971 ? io_stbuf_data_any[7:0] : io_sec_data_lo_m[7:0]; // @[lsu_dccm_ctl.scala 259:185] + wire [7:0] _T_976 = store_byteen_ext_m[0] ? store_data_lo_m[7:0] : _T_975; // @[lsu_dccm_ctl.scala 259:120] + wire [7:0] _T_980 = {{4'd0}, _T_976[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_982 = {_T_976[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_984 = _T_982 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_985 = _T_980 | _T_984; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_48 = {{2'd0}, _T_985[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_990 = _GEN_48 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_992 = {_T_985[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_994 = _T_992 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_995 = _T_990 | _T_994; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_49 = {{1'd0}, _T_995[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1000 = _GEN_49 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1002 = {_T_995[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1004 = _T_1002 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1005 = _T_1000 | _T_1004; // @[Bitwise.scala 103:39] + wire [7:0] _T_1013 = _T_971 ? io_stbuf_data_any[15:8] : io_sec_data_lo_m[15:8]; // @[lsu_dccm_ctl.scala 259:185] + wire [7:0] _T_1014 = store_byteen_ext_m[1] ? store_data_lo_m[15:8] : _T_1013; // @[lsu_dccm_ctl.scala 259:120] + wire [7:0] _T_1018 = {{4'd0}, _T_1014[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1020 = {_T_1014[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1022 = _T_1020 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1023 = _T_1018 | _T_1022; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_50 = {{2'd0}, _T_1023[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1028 = _GEN_50 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1030 = {_T_1023[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1032 = _T_1030 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1033 = _T_1028 | _T_1032; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_51 = {{1'd0}, _T_1033[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1038 = _GEN_51 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1040 = {_T_1033[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1042 = _T_1040 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1043 = _T_1038 | _T_1042; // @[Bitwise.scala 103:39] + wire [7:0] _T_1051 = _T_971 ? io_stbuf_data_any[23:16] : io_sec_data_lo_m[23:16]; // @[lsu_dccm_ctl.scala 259:185] + wire [7:0] _T_1052 = store_byteen_ext_m[2] ? store_data_lo_m[23:16] : _T_1051; // @[lsu_dccm_ctl.scala 259:120] + wire [7:0] _T_1056 = {{4'd0}, _T_1052[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1058 = {_T_1052[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1060 = _T_1058 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1061 = _T_1056 | _T_1060; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_52 = {{2'd0}, _T_1061[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1066 = _GEN_52 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1068 = {_T_1061[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1070 = _T_1068 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1071 = _T_1066 | _T_1070; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_53 = {{1'd0}, _T_1071[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1076 = _GEN_53 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1078 = {_T_1071[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1080 = _T_1078 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1081 = _T_1076 | _T_1080; // @[Bitwise.scala 103:39] + wire [7:0] _T_1089 = _T_971 ? io_stbuf_data_any[31:24] : io_sec_data_lo_m[31:24]; // @[lsu_dccm_ctl.scala 259:185] + wire [7:0] _T_1090 = store_byteen_ext_m[3] ? store_data_lo_m[31:24] : _T_1089; // @[lsu_dccm_ctl.scala 259:120] + wire [7:0] _T_1094 = {{4'd0}, _T_1090[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1096 = {_T_1090[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1098 = _T_1096 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1099 = _T_1094 | _T_1098; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_54 = {{2'd0}, _T_1099[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1104 = _GEN_54 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1106 = {_T_1099[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1108 = _T_1106 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1109 = _T_1104 | _T_1108; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_55 = {{1'd0}, _T_1109[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1114 = _GEN_55 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1116 = {_T_1109[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1118 = _T_1116 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1119 = _T_1114 | _T_1118; // @[Bitwise.scala 103:39] + wire [31:0] _T_1123 = {_T_1005,_T_1043,_T_1081,_T_1119}; // @[Cat.scala 29:58] + wire [31:0] _T_1127 = {{16'd0}, _T_1123[31:16]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1129 = {_T_1123[15:0], 16'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1131 = _T_1129 & 32'hffff0000; // @[Bitwise.scala 103:75] + wire [31:0] _T_1132 = _T_1127 | _T_1131; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_56 = {{8'd0}, _T_1132[31:8]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1137 = _GEN_56 & 32'hff00ff; // @[Bitwise.scala 103:31] + wire [31:0] _T_1139 = {_T_1132[23:0], 8'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1141 = _T_1139 & 32'hff00ff00; // @[Bitwise.scala 103:75] + wire [31:0] _T_1142 = _T_1137 | _T_1141; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_57 = {{4'd0}, _T_1142[31:4]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1147 = _GEN_57 & 32'hf0f0f0f; // @[Bitwise.scala 103:31] + wire [31:0] _T_1149 = {_T_1142[27:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1151 = _T_1149 & 32'hf0f0f0f0; // @[Bitwise.scala 103:75] + wire [31:0] _T_1152 = _T_1147 | _T_1151; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_58 = {{2'd0}, _T_1152[31:2]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1157 = _GEN_58 & 32'h33333333; // @[Bitwise.scala 103:31] + wire [31:0] _T_1159 = {_T_1152[29:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1161 = _T_1159 & 32'hcccccccc; // @[Bitwise.scala 103:75] + wire [31:0] _T_1162 = _T_1157 | _T_1161; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_59 = {{1'd0}, _T_1162[31:1]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1167 = _GEN_59 & 32'h55555555; // @[Bitwise.scala 103:31] + wire [31:0] _T_1169 = {_T_1162[30:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1171 = _T_1169 & 32'haaaaaaaa; // @[Bitwise.scala 103:75] + reg [31:0] _T_1173; // @[lsu_dccm_ctl.scala 259:72] + wire _T_1177 = io_lsu_stbuf_commit_any & dccm_wr_bypass_d_m_hi; // @[lsu_dccm_ctl.scala 260:211] + wire [7:0] _T_1181 = _T_1177 ? io_stbuf_data_any[7:0] : io_sec_data_hi_m[7:0]; // @[lsu_dccm_ctl.scala 260:185] + wire [7:0] _T_1182 = store_byteen_ext_m[4] ? store_data_hi_m[7:0] : _T_1181; // @[lsu_dccm_ctl.scala 260:120] + wire [7:0] _T_1186 = {{4'd0}, _T_1182[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1188 = {_T_1182[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1190 = _T_1188 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1191 = _T_1186 | _T_1190; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_60 = {{2'd0}, _T_1191[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1196 = _GEN_60 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1198 = {_T_1191[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1200 = _T_1198 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1201 = _T_1196 | _T_1200; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_61 = {{1'd0}, _T_1201[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1206 = _GEN_61 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1208 = {_T_1201[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1210 = _T_1208 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1211 = _T_1206 | _T_1210; // @[Bitwise.scala 103:39] + wire [7:0] _T_1219 = _T_1177 ? io_stbuf_data_any[15:8] : io_sec_data_hi_m[15:8]; // @[lsu_dccm_ctl.scala 260:185] + wire [7:0] _T_1220 = store_byteen_ext_m[5] ? store_data_hi_m[15:8] : _T_1219; // @[lsu_dccm_ctl.scala 260:120] + wire [7:0] _T_1224 = {{4'd0}, _T_1220[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1226 = {_T_1220[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1228 = _T_1226 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1229 = _T_1224 | _T_1228; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_62 = {{2'd0}, _T_1229[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1234 = _GEN_62 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1236 = {_T_1229[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1238 = _T_1236 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1239 = _T_1234 | _T_1238; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_63 = {{1'd0}, _T_1239[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1244 = _GEN_63 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1246 = {_T_1239[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1248 = _T_1246 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1249 = _T_1244 | _T_1248; // @[Bitwise.scala 103:39] + wire [7:0] _T_1257 = _T_1177 ? io_stbuf_data_any[23:16] : io_sec_data_hi_m[23:16]; // @[lsu_dccm_ctl.scala 260:185] + wire [7:0] _T_1258 = store_byteen_ext_m[6] ? store_data_hi_m[23:16] : _T_1257; // @[lsu_dccm_ctl.scala 260:120] + wire [7:0] _T_1262 = {{4'd0}, _T_1258[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1264 = {_T_1258[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1266 = _T_1264 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1267 = _T_1262 | _T_1266; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_64 = {{2'd0}, _T_1267[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1272 = _GEN_64 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1274 = {_T_1267[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1276 = _T_1274 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1277 = _T_1272 | _T_1276; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_65 = {{1'd0}, _T_1277[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1282 = _GEN_65 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1284 = {_T_1277[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1286 = _T_1284 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1287 = _T_1282 | _T_1286; // @[Bitwise.scala 103:39] + wire [7:0] _T_1295 = _T_1177 ? io_stbuf_data_any[31:24] : io_sec_data_hi_m[31:24]; // @[lsu_dccm_ctl.scala 260:185] + wire [7:0] _T_1296 = store_byteen_ext_m[7] ? store_data_hi_m[31:24] : _T_1295; // @[lsu_dccm_ctl.scala 260:120] + wire [7:0] _T_1300 = {{4'd0}, _T_1296[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1302 = {_T_1296[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1304 = _T_1302 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1305 = _T_1300 | _T_1304; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_66 = {{2'd0}, _T_1305[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1310 = _GEN_66 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1312 = {_T_1305[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1314 = _T_1312 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1315 = _T_1310 | _T_1314; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_67 = {{1'd0}, _T_1315[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1320 = _GEN_67 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1322 = {_T_1315[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1324 = _T_1322 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1325 = _T_1320 | _T_1324; // @[Bitwise.scala 103:39] + wire [31:0] _T_1329 = {_T_1211,_T_1249,_T_1287,_T_1325}; // @[Cat.scala 29:58] + wire [31:0] _T_1333 = {{16'd0}, _T_1329[31:16]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1335 = {_T_1329[15:0], 16'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1337 = _T_1335 & 32'hffff0000; // @[Bitwise.scala 103:75] + wire [31:0] _T_1338 = _T_1333 | _T_1337; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_68 = {{8'd0}, _T_1338[31:8]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1343 = _GEN_68 & 32'hff00ff; // @[Bitwise.scala 103:31] + wire [31:0] _T_1345 = {_T_1338[23:0], 8'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1347 = _T_1345 & 32'hff00ff00; // @[Bitwise.scala 103:75] + wire [31:0] _T_1348 = _T_1343 | _T_1347; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_69 = {{4'd0}, _T_1348[31:4]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1353 = _GEN_69 & 32'hf0f0f0f; // @[Bitwise.scala 103:31] + wire [31:0] _T_1355 = {_T_1348[27:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1357 = _T_1355 & 32'hf0f0f0f0; // @[Bitwise.scala 103:75] + wire [31:0] _T_1358 = _T_1353 | _T_1357; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_70 = {{2'd0}, _T_1358[31:2]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1363 = _GEN_70 & 32'h33333333; // @[Bitwise.scala 103:31] + wire [31:0] _T_1365 = {_T_1358[29:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1367 = _T_1365 & 32'hcccccccc; // @[Bitwise.scala 103:75] + wire [31:0] _T_1368 = _T_1363 | _T_1367; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_71 = {{1'd0}, _T_1368[31:1]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1373 = _GEN_71 & 32'h55555555; // @[Bitwise.scala 103:31] + wire [31:0] _T_1375 = {_T_1368[30:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1377 = _T_1375 & 32'haaaaaaaa; // @[Bitwise.scala 103:75] + reg [31:0] _T_1379; // @[lsu_dccm_ctl.scala 260:72] + wire _T_1380 = io_lsu_stbuf_commit_any & dccm_wr_bypass_d_r_lo; // @[lsu_dccm_ctl.scala 261:105] + wire [7:0] store_byteen_ext_r = {{1'd0}, _T_947}; // @[lsu_dccm_ctl.scala 220:22] + wire _T_1382 = ~store_byteen_ext_r[0]; // @[lsu_dccm_ctl.scala 261:131] + wire _T_1383 = _T_1380 & _T_1382; // @[lsu_dccm_ctl.scala 261:129] + wire [7:0] _T_1387 = _T_1383 ? io_stbuf_data_any[7:0] : io_store_data_lo_r[7:0]; // @[lsu_dccm_ctl.scala 261:79] + wire [7:0] _T_1391 = {{4'd0}, _T_1387[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1393 = {_T_1387[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1395 = _T_1393 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1396 = _T_1391 | _T_1395; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_72 = {{2'd0}, _T_1396[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1401 = _GEN_72 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1403 = {_T_1396[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1405 = _T_1403 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1406 = _T_1401 | _T_1405; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_73 = {{1'd0}, _T_1406[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1411 = _GEN_73 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1413 = {_T_1406[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1415 = _T_1413 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1416 = _T_1411 | _T_1415; // @[Bitwise.scala 103:39] + wire _T_1419 = ~store_byteen_ext_r[1]; // @[lsu_dccm_ctl.scala 261:131] + wire _T_1420 = _T_1380 & _T_1419; // @[lsu_dccm_ctl.scala 261:129] + wire [7:0] _T_1424 = _T_1420 ? io_stbuf_data_any[15:8] : io_store_data_lo_r[15:8]; // @[lsu_dccm_ctl.scala 261:79] + wire [7:0] _T_1428 = {{4'd0}, _T_1424[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1430 = {_T_1424[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1432 = _T_1430 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1433 = _T_1428 | _T_1432; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_74 = {{2'd0}, _T_1433[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1438 = _GEN_74 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1440 = {_T_1433[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1442 = _T_1440 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1443 = _T_1438 | _T_1442; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_75 = {{1'd0}, _T_1443[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1448 = _GEN_75 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1450 = {_T_1443[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1452 = _T_1450 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1453 = _T_1448 | _T_1452; // @[Bitwise.scala 103:39] + wire _T_1456 = ~store_byteen_ext_r[2]; // @[lsu_dccm_ctl.scala 261:131] + wire _T_1457 = _T_1380 & _T_1456; // @[lsu_dccm_ctl.scala 261:129] + wire [7:0] _T_1461 = _T_1457 ? io_stbuf_data_any[23:16] : io_store_data_lo_r[23:16]; // @[lsu_dccm_ctl.scala 261:79] + wire [7:0] _T_1465 = {{4'd0}, _T_1461[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1467 = {_T_1461[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1469 = _T_1467 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1470 = _T_1465 | _T_1469; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_76 = {{2'd0}, _T_1470[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1475 = _GEN_76 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1477 = {_T_1470[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1479 = _T_1477 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1480 = _T_1475 | _T_1479; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_77 = {{1'd0}, _T_1480[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1485 = _GEN_77 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1487 = {_T_1480[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1489 = _T_1487 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1490 = _T_1485 | _T_1489; // @[Bitwise.scala 103:39] + wire _T_1493 = ~store_byteen_ext_r[3]; // @[lsu_dccm_ctl.scala 261:131] + wire _T_1494 = _T_1380 & _T_1493; // @[lsu_dccm_ctl.scala 261:129] + wire [7:0] _T_1498 = _T_1494 ? io_stbuf_data_any[31:24] : io_store_data_lo_r[31:24]; // @[lsu_dccm_ctl.scala 261:79] + wire [7:0] _T_1502 = {{4'd0}, _T_1498[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1504 = {_T_1498[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1506 = _T_1504 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1507 = _T_1502 | _T_1506; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_78 = {{2'd0}, _T_1507[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1512 = _GEN_78 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1514 = {_T_1507[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1516 = _T_1514 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1517 = _T_1512 | _T_1516; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_79 = {{1'd0}, _T_1517[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1522 = _GEN_79 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1524 = {_T_1517[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1526 = _T_1524 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1527 = _T_1522 | _T_1526; // @[Bitwise.scala 103:39] + wire [31:0] _T_1531 = {_T_1416,_T_1453,_T_1490,_T_1527}; // @[Cat.scala 29:58] + wire [31:0] _T_1535 = {{16'd0}, _T_1531[31:16]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1537 = {_T_1531[15:0], 16'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1539 = _T_1537 & 32'hffff0000; // @[Bitwise.scala 103:75] + wire [31:0] _T_1540 = _T_1535 | _T_1539; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_80 = {{8'd0}, _T_1540[31:8]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1545 = _GEN_80 & 32'hff00ff; // @[Bitwise.scala 103:31] + wire [31:0] _T_1547 = {_T_1540[23:0], 8'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1549 = _T_1547 & 32'hff00ff00; // @[Bitwise.scala 103:75] + wire [31:0] _T_1550 = _T_1545 | _T_1549; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_81 = {{4'd0}, _T_1550[31:4]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1555 = _GEN_81 & 32'hf0f0f0f; // @[Bitwise.scala 103:31] + wire [31:0] _T_1557 = {_T_1550[27:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1559 = _T_1557 & 32'hf0f0f0f0; // @[Bitwise.scala 103:75] + wire [31:0] _T_1560 = _T_1555 | _T_1559; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_82 = {{2'd0}, _T_1560[31:2]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1565 = _GEN_82 & 32'h33333333; // @[Bitwise.scala 103:31] + wire [31:0] _T_1567 = {_T_1560[29:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1569 = _T_1567 & 32'hcccccccc; // @[Bitwise.scala 103:75] + wire [31:0] _T_1570 = _T_1565 | _T_1569; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_83 = {{1'd0}, _T_1570[31:1]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1575 = _GEN_83 & 32'h55555555; // @[Bitwise.scala 103:31] + wire [31:0] _T_1577 = {_T_1570[30:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1579 = _T_1577 & 32'haaaaaaaa; // @[Bitwise.scala 103:75] + wire _T_1581 = io_lsu_stbuf_commit_any & dccm_wr_bypass_d_r_hi; // @[lsu_dccm_ctl.scala 262:105] + wire _T_1583 = ~store_byteen_ext_r[4]; // @[lsu_dccm_ctl.scala 262:131] + wire _T_1584 = _T_1581 & _T_1583; // @[lsu_dccm_ctl.scala 262:129] + wire [7:0] _T_1588 = _T_1584 ? io_stbuf_data_any[7:0] : io_store_data_hi_r[7:0]; // @[lsu_dccm_ctl.scala 262:79] + wire [7:0] _T_1592 = {{4'd0}, _T_1588[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1594 = {_T_1588[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1596 = _T_1594 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1597 = _T_1592 | _T_1596; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_84 = {{2'd0}, _T_1597[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1602 = _GEN_84 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1604 = {_T_1597[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1606 = _T_1604 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1607 = _T_1602 | _T_1606; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_85 = {{1'd0}, _T_1607[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1612 = _GEN_85 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1614 = {_T_1607[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1616 = _T_1614 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1617 = _T_1612 | _T_1616; // @[Bitwise.scala 103:39] + wire _T_1620 = ~store_byteen_ext_r[5]; // @[lsu_dccm_ctl.scala 262:131] + wire _T_1621 = _T_1581 & _T_1620; // @[lsu_dccm_ctl.scala 262:129] + wire [7:0] _T_1625 = _T_1621 ? io_stbuf_data_any[15:8] : io_store_data_hi_r[15:8]; // @[lsu_dccm_ctl.scala 262:79] + wire [7:0] _T_1629 = {{4'd0}, _T_1625[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1631 = {_T_1625[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1633 = _T_1631 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1634 = _T_1629 | _T_1633; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_86 = {{2'd0}, _T_1634[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1639 = _GEN_86 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1641 = {_T_1634[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1643 = _T_1641 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1644 = _T_1639 | _T_1643; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_87 = {{1'd0}, _T_1644[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1649 = _GEN_87 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1651 = {_T_1644[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1653 = _T_1651 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1654 = _T_1649 | _T_1653; // @[Bitwise.scala 103:39] + wire _T_1657 = ~store_byteen_ext_r[6]; // @[lsu_dccm_ctl.scala 262:131] + wire _T_1658 = _T_1581 & _T_1657; // @[lsu_dccm_ctl.scala 262:129] + wire [7:0] _T_1662 = _T_1658 ? io_stbuf_data_any[23:16] : io_store_data_hi_r[23:16]; // @[lsu_dccm_ctl.scala 262:79] + wire [7:0] _T_1666 = {{4'd0}, _T_1662[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1668 = {_T_1662[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1670 = _T_1668 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1671 = _T_1666 | _T_1670; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_88 = {{2'd0}, _T_1671[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1676 = _GEN_88 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1678 = {_T_1671[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1680 = _T_1678 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1681 = _T_1676 | _T_1680; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_89 = {{1'd0}, _T_1681[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1686 = _GEN_89 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1688 = {_T_1681[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1690 = _T_1688 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1691 = _T_1686 | _T_1690; // @[Bitwise.scala 103:39] + wire _T_1694 = ~store_byteen_ext_r[7]; // @[lsu_dccm_ctl.scala 262:131] + wire _T_1695 = _T_1581 & _T_1694; // @[lsu_dccm_ctl.scala 262:129] + wire [7:0] _T_1699 = _T_1695 ? io_stbuf_data_any[31:24] : io_store_data_hi_r[31:24]; // @[lsu_dccm_ctl.scala 262:79] + wire [7:0] _T_1703 = {{4'd0}, _T_1699[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1705 = {_T_1699[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1707 = _T_1705 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1708 = _T_1703 | _T_1707; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_90 = {{2'd0}, _T_1708[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1713 = _GEN_90 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1715 = {_T_1708[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1717 = _T_1715 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1718 = _T_1713 | _T_1717; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_91 = {{1'd0}, _T_1718[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1723 = _GEN_91 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1725 = {_T_1718[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1727 = _T_1725 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1728 = _T_1723 | _T_1727; // @[Bitwise.scala 103:39] + wire [31:0] _T_1732 = {_T_1617,_T_1654,_T_1691,_T_1728}; // @[Cat.scala 29:58] + wire [31:0] _T_1736 = {{16'd0}, _T_1732[31:16]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1738 = {_T_1732[15:0], 16'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1740 = _T_1738 & 32'hffff0000; // @[Bitwise.scala 103:75] + wire [31:0] _T_1741 = _T_1736 | _T_1740; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_92 = {{8'd0}, _T_1741[31:8]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1746 = _GEN_92 & 32'hff00ff; // @[Bitwise.scala 103:31] + wire [31:0] _T_1748 = {_T_1741[23:0], 8'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1750 = _T_1748 & 32'hff00ff00; // @[Bitwise.scala 103:75] + wire [31:0] _T_1751 = _T_1746 | _T_1750; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_93 = {{4'd0}, _T_1751[31:4]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1756 = _GEN_93 & 32'hf0f0f0f; // @[Bitwise.scala 103:31] + wire [31:0] _T_1758 = {_T_1751[27:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1760 = _T_1758 & 32'hf0f0f0f0; // @[Bitwise.scala 103:75] + wire [31:0] _T_1761 = _T_1756 | _T_1760; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_94 = {{2'd0}, _T_1761[31:2]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1766 = _GEN_94 & 32'h33333333; // @[Bitwise.scala 103:31] + wire [31:0] _T_1768 = {_T_1761[29:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1770 = _T_1768 & 32'hcccccccc; // @[Bitwise.scala 103:75] + wire [31:0] _T_1771 = _T_1766 | _T_1770; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_95 = {{1'd0}, _T_1771[31:1]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1776 = _GEN_95 & 32'h55555555; // @[Bitwise.scala 103:31] + wire [31:0] _T_1778 = {_T_1771[30:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1780 = _T_1778 & 32'haaaaaaaa; // @[Bitwise.scala 103:75] + wire [63:0] _T_1784 = {io_store_data_hi_r,io_store_data_lo_r}; // @[Cat.scala 29:58] + wire [3:0] _GEN_96 = {{2'd0}, io_lsu_addr_r[1:0]}; // @[lsu_dccm_ctl.scala 263:94] + wire [5:0] _T_1786 = 4'h8 * _GEN_96; // @[lsu_dccm_ctl.scala 263:94] + wire [63:0] _T_1787 = _T_1784 >> _T_1786; // @[lsu_dccm_ctl.scala 263:88] + wire [7:0] _T_1790 = store_byteen_r[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1793 = store_byteen_r[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1796 = store_byteen_r[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1799 = store_byteen_r[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_1803 = {_T_1790,_T_1793,_T_1796,_T_1799}; // @[Cat.scala 29:58] + wire [31:0] _T_1807 = {{16'd0}, _T_1803[31:16]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1809 = {_T_1803[15:0], 16'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1811 = _T_1809 & 32'hffff0000; // @[Bitwise.scala 103:75] + wire [31:0] _T_1812 = _T_1807 | _T_1811; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_97 = {{8'd0}, _T_1812[31:8]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1817 = _GEN_97 & 32'hff00ff; // @[Bitwise.scala 103:31] + wire [31:0] _T_1819 = {_T_1812[23:0], 8'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1821 = _T_1819 & 32'hff00ff00; // @[Bitwise.scala 103:75] + wire [31:0] _T_1822 = _T_1817 | _T_1821; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_98 = {{4'd0}, _T_1822[31:4]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1827 = _GEN_98 & 32'hf0f0f0f; // @[Bitwise.scala 103:31] + wire [31:0] _T_1829 = {_T_1822[27:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1831 = _T_1829 & 32'hf0f0f0f0; // @[Bitwise.scala 103:75] + wire [31:0] _T_1832 = _T_1827 | _T_1831; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_99 = {{2'd0}, _T_1832[31:2]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1837 = _GEN_99 & 32'h33333333; // @[Bitwise.scala 103:31] + wire [31:0] _T_1839 = {_T_1832[29:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1841 = _T_1839 & 32'hcccccccc; // @[Bitwise.scala 103:75] + wire [31:0] _T_1842 = _T_1837 | _T_1841; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_100 = {{1'd0}, _T_1842[31:1]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1847 = _GEN_100 & 32'h55555555; // @[Bitwise.scala 103:31] + wire [31:0] _T_1849 = {_T_1842[30:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1851 = _T_1849 & 32'haaaaaaaa; // @[Bitwise.scala 103:75] + wire [31:0] _T_1852 = _T_1847 | _T_1851; // @[Bitwise.scala 103:39] + wire [63:0] _GEN_101 = {{32'd0}, _T_1852}; // @[lsu_dccm_ctl.scala 263:115] + wire [63:0] _T_1853 = _T_1787 & _GEN_101; // @[lsu_dccm_ctl.scala 263:115] + wire _T_1858 = io_lsu_pkt_r_valid & io_lsu_pkt_r_bits_store; // @[lsu_dccm_ctl.scala 270:58] + wire _T_1859 = _T_1858 & io_addr_in_pic_r; // @[lsu_dccm_ctl.scala 270:84] + wire _T_1860 = _T_1859 & io_lsu_commit_r; // @[lsu_dccm_ctl.scala 270:103] + wire _T_1862 = io_lsu_pkt_d_valid & io_lsu_pkt_d_bits_load; // @[lsu_dccm_ctl.scala 271:58] + wire _T_1864 = io_lsu_pkt_d_valid & io_lsu_pkt_d_bits_store; // @[lsu_dccm_ctl.scala 272:58] + wire [31:0] _T_1868 = {17'h0,io_lsu_addr_d[14:0]}; // @[Cat.scala 29:58] + wire [14:0] _T_1874 = io_dma_pic_wen ? io_dma_dccm_ctl_dma_mem_addr[14:0] : io_lsu_addr_r[14:0]; // @[lsu_dccm_ctl.scala 274:93] + wire [31:0] _T_1875 = {17'h0,_T_1874}; // @[Cat.scala 29:58] + reg _T_1882; // @[lsu_dccm_ctl.scala 279:61] + rvclkhdr rvclkhdr ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) + ); + rvclkhdr rvclkhdr_1 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_1_io_l1clk), + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en), + .io_scan_mode(rvclkhdr_1_io_scan_mode) + ); + assign io_lsu_ld_data_corr_r = _T_2[31:0]; // @[lsu_dccm_ctl.scala 147:28] + assign io_dccm_rdata_hi_m = io_dccm_rd_data_hi[31:0]; // @[lsu_dccm_ctl.scala 266:27] + assign io_dccm_rdata_lo_m = io_dccm_rd_data_lo[31:0]; // @[lsu_dccm_ctl.scala 265:27] + assign io_dccm_data_ecc_hi_m = io_dccm_rd_data_hi[38:32]; // @[lsu_dccm_ctl.scala 268:27] + assign io_dccm_data_ecc_lo_m = io_dccm_rd_data_lo[38:32]; // @[lsu_dccm_ctl.scala 267:27] + assign io_lsu_ld_data_m = _T_763[31:0]; // @[lsu_dccm_ctl.scala 150:28] + assign io_store_data_hi_r = _T_1379; // @[lsu_dccm_ctl.scala 260:29] + assign io_store_data_lo_r = _T_1173; // @[lsu_dccm_ctl.scala 259:29] + assign io_store_datafn_hi_r = _T_1776 | _T_1780; // @[lsu_dccm_ctl.scala 262:29] + assign io_store_datafn_lo_r = _T_1575 | _T_1579; // @[lsu_dccm_ctl.scala 261:29] + assign io_store_data_r = _T_1853[31:0]; // @[lsu_dccm_ctl.scala 263:29] + assign io_ld_single_ecc_error_r = _T_815 & _T_816; // @[lsu_dccm_ctl.scala 163:34] + assign io_ld_single_ecc_error_r_ff = _T_838 & _T_839; // @[lsu_dccm_ctl.scala 176:31] + assign io_picm_mask_data_m = picm_rd_data_m[31:0]; // @[lsu_dccm_ctl.scala 275:27] + assign io_lsu_stbuf_commit_any = io_stbuf_reqvld_any & _T_853; // @[lsu_dccm_ctl.scala 177:31] + assign io_lsu_dccm_rden_m = _T_1882; // @[lsu_dccm_ctl.scala 279:24] + assign io_dma_dccm_ctl_dccm_dma_rvalid = _T & io_lsu_pkt_m_bits_dma; // @[lsu_dccm_ctl.scala 137:41] + assign io_dma_dccm_ctl_dccm_dma_ecc_error = io_lsu_double_ecc_error_m; // @[lsu_dccm_ctl.scala 138:41] + assign io_dma_dccm_ctl_dccm_dma_rtag = io_dma_mem_tag_m; // @[lsu_dccm_ctl.scala 140:41] + assign io_dma_dccm_ctl_dccm_dma_rdata = _T_376 | _T_380; // @[lsu_dccm_ctl.scala 139:41] + assign io_dccm_wren = _T_855 | io_ld_single_ecc_error_r_ff; // @[lsu_dccm_ctl.scala 183:22] + assign io_dccm_rden = lsu_dccm_rden_d & io_addr_in_dccm_d; // @[lsu_dccm_ctl.scala 184:22] + assign io_dccm_wr_addr_lo = io_ld_single_ecc_error_r_ff ? _T_862 : _T_866; // @[lsu_dccm_ctl.scala 186:22] + assign io_dccm_wr_addr_hi = io_ld_single_ecc_error_r_ff ? _T_872 : _T_876; // @[lsu_dccm_ctl.scala 190:22] + assign io_dccm_rd_addr_lo = io_lsu_addr_d[15:0]; // @[lsu_dccm_ctl.scala 194:22] + assign io_dccm_rd_addr_hi = io_end_addr_d; // @[lsu_dccm_ctl.scala 195:22] + assign io_dccm_wr_data_lo = io_ld_single_ecc_error_r_ff ? _T_888 : _T_896; // @[lsu_dccm_ctl.scala 197:22] + assign io_dccm_wr_data_hi = io_ld_single_ecc_error_r_ff ? _T_906 : _T_914; // @[lsu_dccm_ctl.scala 203:22] + assign io_lsu_pic_picm_wren = _T_1860 | io_dma_pic_wen; // @[lsu_dccm_ctl.scala 270:35] + assign io_lsu_pic_picm_rden = _T_1862 & io_addr_in_pic_d; // @[lsu_dccm_ctl.scala 271:35] + assign io_lsu_pic_picm_mken = _T_1864 & io_addr_in_pic_d; // @[lsu_dccm_ctl.scala 272:35] + assign io_lsu_pic_picm_rdaddr = 32'hf00c0000 | _T_1868; // @[lsu_dccm_ctl.scala 273:35] + assign io_lsu_pic_picm_wraddr = 32'hf00c0000 | _T_1875; // @[lsu_dccm_ctl.scala 274:35] + assign io_lsu_pic_picm_wr_data = io_dma_pic_wen ? io_dma_dccm_ctl_dma_mem_wdata[31:0] : io_store_datafn_lo_r; // @[lsu_dccm_ctl.scala 276:35] + assign rvclkhdr_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_io_en = io_ld_single_ecc_error_r; // @[lib.scala 371:17] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_1_io_en = io_ld_single_ecc_error_r; // @[lib.scala 371:17] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {2{`RANDOM}}; + _T_2 = _RAND_0[63:0]; + _RAND_1 = {1{`RANDOM}}; + lsu_double_ecc_error_r_ff = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + ld_single_ecc_error_hi_r_ff = _RAND_2[0:0]; + _RAND_3 = {1{`RANDOM}}; + ld_single_ecc_error_lo_r_ff = _RAND_3[0:0]; + _RAND_4 = {1{`RANDOM}}; + ld_sec_addr_hi_r_ff = _RAND_4[15:0]; + _RAND_5 = {1{`RANDOM}}; + ld_sec_addr_lo_r_ff = _RAND_5[15:0]; + _RAND_6 = {1{`RANDOM}}; + _T_1173 = _RAND_6[31:0]; + _RAND_7 = {1{`RANDOM}}; + _T_1379 = _RAND_7[31:0]; + _RAND_8 = {1{`RANDOM}}; + _T_1882 = _RAND_8[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + _T_2 = 64'h0; + end + if (reset) begin + lsu_double_ecc_error_r_ff = 1'h0; + end + if (reset) begin + ld_single_ecc_error_hi_r_ff = 1'h0; + end + if (reset) begin + ld_single_ecc_error_lo_r_ff = 1'h0; + end + if (reset) begin + ld_sec_addr_hi_r_ff = 16'h0; + end + if (reset) begin + ld_sec_addr_lo_r_ff = 16'h0; + end + if (reset) begin + _T_1173 = 32'h0; + end + if (reset) begin + _T_1379 = 32'h0; + end + if (reset) begin + _T_1882 = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_2 <= 64'h0; + end else begin + _T_2 <= lsu_rdata_corr_m >> _T_762; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + lsu_double_ecc_error_r_ff <= 1'h0; + end else begin + lsu_double_ecc_error_r_ff <= io_lsu_double_ecc_error_r; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + ld_single_ecc_error_hi_r_ff <= 1'h0; + end else begin + ld_single_ecc_error_hi_r_ff <= _T_822 & _T_823; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + ld_single_ecc_error_lo_r_ff <= 1'h0; + end else begin + ld_single_ecc_error_lo_r_ff <= _T_819 & _T_820; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + if (reset) begin + ld_sec_addr_hi_r_ff <= 16'h0; + end else begin + ld_sec_addr_hi_r_ff <= io_end_addr_r; + end + end + always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin + if (reset) begin + ld_sec_addr_lo_r_ff <= 16'h0; + end else begin + ld_sec_addr_lo_r_ff <= io_lsu_addr_r[15:0]; + end + end + always @(posedge io_lsu_store_c1_r_clk or posedge reset) begin + if (reset) begin + _T_1173 <= 32'h0; + end else begin + _T_1173 <= _T_1167 | _T_1171; + end + end + always @(posedge io_lsu_store_c1_r_clk or posedge reset) begin + if (reset) begin + _T_1379 <= 32'h0; + end else begin + _T_1379 <= _T_1373 | _T_1377; + end + end + always @(posedge io_lsu_c2_m_clk or posedge reset) begin + if (reset) begin + _T_1882 <= 1'h0; + end else begin + _T_1882 <= _T_837 & io_addr_in_dccm_d; + end + end +endmodule +module lsu_stbuf( + input clock, + input reset, + input io_lsu_c1_m_clk, + input io_lsu_c1_r_clk, + input io_lsu_stbuf_c1_clk, + input io_lsu_free_c2_clk, + input io_lsu_pkt_m_valid, + input io_lsu_pkt_m_bits_store, + input io_lsu_pkt_m_bits_dma, + input io_lsu_pkt_r_valid, + input io_lsu_pkt_r_bits_by, + input io_lsu_pkt_r_bits_half, + input io_lsu_pkt_r_bits_word, + input io_lsu_pkt_r_bits_dword, + input io_lsu_pkt_r_bits_store, + input io_lsu_pkt_r_bits_dma, + input io_store_stbuf_reqvld_r, + input io_lsu_commit_r, + input io_dec_lsu_valid_raw_d, + input [31:0] io_store_data_hi_r, + input [31:0] io_store_data_lo_r, + input [31:0] io_store_datafn_hi_r, + input [31:0] io_store_datafn_lo_r, + input io_lsu_stbuf_commit_any, + input [15:0] io_lsu_addr_d, + input [31:0] io_lsu_addr_m, + input [31:0] io_lsu_addr_r, + input [15:0] io_end_addr_d, + input [31:0] io_end_addr_m, + input [31:0] io_end_addr_r, + input io_addr_in_dccm_m, + input io_addr_in_dccm_r, + input io_scan_mode, + output io_stbuf_reqvld_any, + output io_stbuf_reqvld_flushed_any, + output [15:0] io_stbuf_addr_any, + output [31:0] io_stbuf_data_any, + output io_lsu_stbuf_full_any, + output io_lsu_stbuf_empty_any, + output io_ldst_stbuf_reqvld_r, + output [31:0] io_stbuf_fwddata_hi_m, + output [31:0] io_stbuf_fwddata_lo_m, + output [3:0] io_stbuf_fwdbyteen_hi_m, + output [3:0] io_stbuf_fwdbyteen_lo_m +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; + reg [31:0] _RAND_15; + reg [31:0] _RAND_16; + reg [31:0] _RAND_17; + reg [31:0] _RAND_18; + reg [31:0] _RAND_19; + reg [31:0] _RAND_20; + reg [31:0] _RAND_21; + reg [31:0] _RAND_22; + reg [31:0] _RAND_23; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_io_en; // @[lib.scala 368:23] + wire rvclkhdr_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_1_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_1_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_1_io_en; // @[lib.scala 368:23] + wire rvclkhdr_1_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_2_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_2_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_2_io_en; // @[lib.scala 368:23] + wire rvclkhdr_2_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_3_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_3_io_en; // @[lib.scala 368:23] + wire rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_4_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_4_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_4_io_en; // @[lib.scala 368:23] + wire rvclkhdr_4_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_5_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_5_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_5_io_en; // @[lib.scala 368:23] + wire rvclkhdr_5_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_6_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_6_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_6_io_en; // @[lib.scala 368:23] + wire rvclkhdr_6_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_7_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_7_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_7_io_en; // @[lib.scala 368:23] + wire rvclkhdr_7_io_scan_mode; // @[lib.scala 368:23] + wire [1:0] _T_5 = io_lsu_pkt_r_bits_half ? 2'h3 : 2'h0; // @[Mux.scala 27:72] + wire [3:0] _T_6 = io_lsu_pkt_r_bits_word ? 4'hf : 4'h0; // @[Mux.scala 27:72] + wire [7:0] _T_7 = io_lsu_pkt_r_bits_dword ? 8'hff : 8'h0; // @[Mux.scala 27:72] + wire [1:0] _GEN_10 = {{1'd0}, io_lsu_pkt_r_bits_by}; // @[Mux.scala 27:72] + wire [1:0] _T_8 = _GEN_10 | _T_5; // @[Mux.scala 27:72] + wire [3:0] _GEN_11 = {{2'd0}, _T_8}; // @[Mux.scala 27:72] + wire [3:0] _T_9 = _GEN_11 | _T_6; // @[Mux.scala 27:72] + wire [7:0] _GEN_12 = {{4'd0}, _T_9}; // @[Mux.scala 27:72] + wire [7:0] ldst_byteen_r = _GEN_12 | _T_7; // @[Mux.scala 27:72] + wire ldst_dual_d = io_lsu_addr_d[2] != io_end_addr_d[2]; // @[lsu_stbuf.scala 117:39] + reg ldst_dual_r; // @[lsu_stbuf.scala 171:52] + wire dual_stbuf_write_r = ldst_dual_r & io_store_stbuf_reqvld_r; // @[lsu_stbuf.scala 118:40] + wire [10:0] _GEN_13 = {{3'd0}, ldst_byteen_r}; // @[lsu_stbuf.scala 120:39] + wire [10:0] _T_14 = _GEN_13 << io_lsu_addr_r[1:0]; // @[lsu_stbuf.scala 120:39] + wire [7:0] store_byteen_ext_r = _T_14[7:0]; // @[lsu_stbuf.scala 120:22] + wire [3:0] _T_17 = io_lsu_pkt_r_bits_store ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] store_byteen_hi_r = store_byteen_ext_r[7:4] & _T_17; // @[lsu_stbuf.scala 121:52] + wire [3:0] store_byteen_lo_r = store_byteen_ext_r[3:0] & _T_17; // @[lsu_stbuf.scala 122:52] + reg [1:0] RdPtr; // @[Reg.scala 27:20] + wire [1:0] RdPtrPlus1 = RdPtr + 2'h1; // @[lsu_stbuf.scala 124:26] + reg [1:0] WrPtr; // @[Reg.scala 27:20] + wire [1:0] WrPtrPlus1 = WrPtr + 2'h1; // @[lsu_stbuf.scala 125:26] + wire [1:0] WrPtrPlus2 = WrPtr + 2'h2; // @[lsu_stbuf.scala 126:26] + reg [15:0] stbuf_addr_0; // @[lib.scala 374:16] + wire _T_27 = stbuf_addr_0[15:2] == io_lsu_addr_r[15:2]; // @[lsu_stbuf.scala 130:120] + reg _T_588; // @[lsu_stbuf.scala 163:88] + reg _T_580; // @[lsu_stbuf.scala 163:88] + reg _T_572; // @[lsu_stbuf.scala 163:88] + reg _T_564; // @[lsu_stbuf.scala 163:88] + wire [3:0] stbuf_vld = {_T_588,_T_580,_T_572,_T_564}; // @[Cat.scala 29:58] + wire _T_29 = _T_27 & stbuf_vld[0]; // @[lsu_stbuf.scala 130:179] + reg _T_623; // @[lsu_stbuf.scala 164:92] + reg _T_615; // @[lsu_stbuf.scala 164:92] + reg _T_607; // @[lsu_stbuf.scala 164:92] + reg _T_599; // @[lsu_stbuf.scala 164:92] + wire [3:0] stbuf_dma_kill = {_T_623,_T_615,_T_607,_T_599}; // @[Cat.scala 29:58] + wire _T_31 = ~stbuf_dma_kill[0]; // @[lsu_stbuf.scala 130:197] + wire _T_32 = _T_29 & _T_31; // @[lsu_stbuf.scala 130:195] + wire _T_212 = io_lsu_stbuf_commit_any | io_stbuf_reqvld_flushed_any; // @[lsu_stbuf.scala 141:78] + wire _T_213 = 2'h3 == RdPtr; // @[lsu_stbuf.scala 141:121] + wire _T_215 = _T_212 & _T_213; // @[lsu_stbuf.scala 141:109] + wire _T_209 = 2'h2 == RdPtr; // @[lsu_stbuf.scala 141:121] + wire _T_211 = _T_212 & _T_209; // @[lsu_stbuf.scala 141:109] + wire _T_205 = 2'h1 == RdPtr; // @[lsu_stbuf.scala 141:121] + wire _T_207 = _T_212 & _T_205; // @[lsu_stbuf.scala 141:109] + wire _T_201 = 2'h0 == RdPtr; // @[lsu_stbuf.scala 141:121] + wire _T_203 = _T_212 & _T_201; // @[lsu_stbuf.scala 141:109] + wire [3:0] stbuf_reset = {_T_215,_T_211,_T_207,_T_203}; // @[Cat.scala 29:58] + wire _T_34 = ~stbuf_reset[0]; // @[lsu_stbuf.scala 130:218] + wire _T_35 = _T_32 & _T_34; // @[lsu_stbuf.scala 130:216] + reg [15:0] stbuf_addr_1; // @[lib.scala 374:16] + wire _T_38 = stbuf_addr_1[15:2] == io_lsu_addr_r[15:2]; // @[lsu_stbuf.scala 130:120] + wire _T_40 = _T_38 & stbuf_vld[1]; // @[lsu_stbuf.scala 130:179] + wire _T_42 = ~stbuf_dma_kill[1]; // @[lsu_stbuf.scala 130:197] + wire _T_43 = _T_40 & _T_42; // @[lsu_stbuf.scala 130:195] + wire _T_45 = ~stbuf_reset[1]; // @[lsu_stbuf.scala 130:218] + wire _T_46 = _T_43 & _T_45; // @[lsu_stbuf.scala 130:216] + reg [15:0] stbuf_addr_2; // @[lib.scala 374:16] + wire _T_49 = stbuf_addr_2[15:2] == io_lsu_addr_r[15:2]; // @[lsu_stbuf.scala 130:120] + wire _T_51 = _T_49 & stbuf_vld[2]; // @[lsu_stbuf.scala 130:179] + wire _T_53 = ~stbuf_dma_kill[2]; // @[lsu_stbuf.scala 130:197] + wire _T_54 = _T_51 & _T_53; // @[lsu_stbuf.scala 130:195] + wire _T_56 = ~stbuf_reset[2]; // @[lsu_stbuf.scala 130:218] + wire _T_57 = _T_54 & _T_56; // @[lsu_stbuf.scala 130:216] + reg [15:0] stbuf_addr_3; // @[lib.scala 374:16] + wire _T_60 = stbuf_addr_3[15:2] == io_lsu_addr_r[15:2]; // @[lsu_stbuf.scala 130:120] + wire _T_62 = _T_60 & stbuf_vld[3]; // @[lsu_stbuf.scala 130:179] + wire _T_64 = ~stbuf_dma_kill[3]; // @[lsu_stbuf.scala 130:197] + wire _T_65 = _T_62 & _T_64; // @[lsu_stbuf.scala 130:195] + wire _T_67 = ~stbuf_reset[3]; // @[lsu_stbuf.scala 130:218] + wire _T_68 = _T_65 & _T_67; // @[lsu_stbuf.scala 130:216] + wire [3:0] store_matchvec_lo_r = {_T_68,_T_57,_T_46,_T_35}; // @[Cat.scala 29:58] + wire _T_73 = stbuf_addr_0[15:2] == io_end_addr_r[15:2]; // @[lsu_stbuf.scala 131:120] + wire _T_75 = _T_73 & stbuf_vld[0]; // @[lsu_stbuf.scala 131:179] + wire _T_78 = _T_75 & _T_31; // @[lsu_stbuf.scala 131:194] + wire _T_79 = _T_78 & dual_stbuf_write_r; // @[lsu_stbuf.scala 131:215] + wire _T_82 = _T_79 & _T_34; // @[lsu_stbuf.scala 131:236] + wire _T_85 = stbuf_addr_1[15:2] == io_end_addr_r[15:2]; // @[lsu_stbuf.scala 131:120] + wire _T_87 = _T_85 & stbuf_vld[1]; // @[lsu_stbuf.scala 131:179] + wire _T_90 = _T_87 & _T_42; // @[lsu_stbuf.scala 131:194] + wire _T_91 = _T_90 & dual_stbuf_write_r; // @[lsu_stbuf.scala 131:215] + wire _T_94 = _T_91 & _T_45; // @[lsu_stbuf.scala 131:236] + wire _T_97 = stbuf_addr_2[15:2] == io_end_addr_r[15:2]; // @[lsu_stbuf.scala 131:120] + wire _T_99 = _T_97 & stbuf_vld[2]; // @[lsu_stbuf.scala 131:179] + wire _T_102 = _T_99 & _T_53; // @[lsu_stbuf.scala 131:194] + wire _T_103 = _T_102 & dual_stbuf_write_r; // @[lsu_stbuf.scala 131:215] + wire _T_106 = _T_103 & _T_56; // @[lsu_stbuf.scala 131:236] + wire _T_109 = stbuf_addr_3[15:2] == io_end_addr_r[15:2]; // @[lsu_stbuf.scala 131:120] + wire _T_111 = _T_109 & stbuf_vld[3]; // @[lsu_stbuf.scala 131:179] + wire _T_114 = _T_111 & _T_64; // @[lsu_stbuf.scala 131:194] + wire _T_115 = _T_114 & dual_stbuf_write_r; // @[lsu_stbuf.scala 131:215] + wire _T_118 = _T_115 & _T_67; // @[lsu_stbuf.scala 131:236] + wire [3:0] store_matchvec_hi_r = {_T_118,_T_106,_T_94,_T_82}; // @[Cat.scala 29:58] + wire store_coalesce_lo_r = |store_matchvec_lo_r; // @[lsu_stbuf.scala 133:49] + wire store_coalesce_hi_r = |store_matchvec_hi_r; // @[lsu_stbuf.scala 134:49] + wire _T_121 = 2'h0 == WrPtr; // @[lsu_stbuf.scala 137:16] + wire _T_122 = ~store_coalesce_lo_r; // @[lsu_stbuf.scala 137:29] + wire _T_123 = _T_121 & _T_122; // @[lsu_stbuf.scala 137:27] + wire _T_125 = _T_121 & dual_stbuf_write_r; // @[lsu_stbuf.scala 138:29] + wire _T_126 = ~store_coalesce_hi_r; // @[lsu_stbuf.scala 138:52] + wire _T_127 = _T_125 & _T_126; // @[lsu_stbuf.scala 138:50] + wire _T_128 = _T_123 | _T_127; // @[lsu_stbuf.scala 137:51] + wire _T_129 = 2'h0 == WrPtrPlus1; // @[lsu_stbuf.scala 139:18] + wire _T_130 = _T_129 & dual_stbuf_write_r; // @[lsu_stbuf.scala 139:34] + wire _T_131 = store_coalesce_lo_r | store_coalesce_hi_r; // @[lsu_stbuf.scala 139:79] + wire _T_132 = ~_T_131; // @[lsu_stbuf.scala 139:57] + wire _T_133 = _T_130 & _T_132; // @[lsu_stbuf.scala 139:55] + wire _T_134 = _T_128 | _T_133; // @[lsu_stbuf.scala 138:74] + wire _T_136 = _T_134 | store_matchvec_lo_r[0]; // @[lsu_stbuf.scala 139:103] + wire _T_138 = _T_136 | store_matchvec_hi_r[0]; // @[lsu_stbuf.scala 140:30] + wire _T_139 = io_ldst_stbuf_reqvld_r & _T_138; // @[lsu_stbuf.scala 136:76] + wire _T_140 = 2'h1 == WrPtr; // @[lsu_stbuf.scala 137:16] + wire _T_142 = _T_140 & _T_122; // @[lsu_stbuf.scala 137:27] + wire _T_144 = _T_140 & dual_stbuf_write_r; // @[lsu_stbuf.scala 138:29] + wire _T_146 = _T_144 & _T_126; // @[lsu_stbuf.scala 138:50] + wire _T_147 = _T_142 | _T_146; // @[lsu_stbuf.scala 137:51] + wire _T_148 = 2'h1 == WrPtrPlus1; // @[lsu_stbuf.scala 139:18] + wire _T_149 = _T_148 & dual_stbuf_write_r; // @[lsu_stbuf.scala 139:34] + wire _T_152 = _T_149 & _T_132; // @[lsu_stbuf.scala 139:55] + wire _T_153 = _T_147 | _T_152; // @[lsu_stbuf.scala 138:74] + wire _T_155 = _T_153 | store_matchvec_lo_r[1]; // @[lsu_stbuf.scala 139:103] + wire _T_157 = _T_155 | store_matchvec_hi_r[1]; // @[lsu_stbuf.scala 140:30] + wire _T_158 = io_ldst_stbuf_reqvld_r & _T_157; // @[lsu_stbuf.scala 136:76] + wire _T_159 = 2'h2 == WrPtr; // @[lsu_stbuf.scala 137:16] + wire _T_161 = _T_159 & _T_122; // @[lsu_stbuf.scala 137:27] + wire _T_163 = _T_159 & dual_stbuf_write_r; // @[lsu_stbuf.scala 138:29] + wire _T_165 = _T_163 & _T_126; // @[lsu_stbuf.scala 138:50] + wire _T_166 = _T_161 | _T_165; // @[lsu_stbuf.scala 137:51] + wire _T_167 = 2'h2 == WrPtrPlus1; // @[lsu_stbuf.scala 139:18] + wire _T_168 = _T_167 & dual_stbuf_write_r; // @[lsu_stbuf.scala 139:34] + wire _T_171 = _T_168 & _T_132; // @[lsu_stbuf.scala 139:55] + wire _T_172 = _T_166 | _T_171; // @[lsu_stbuf.scala 138:74] + wire _T_174 = _T_172 | store_matchvec_lo_r[2]; // @[lsu_stbuf.scala 139:103] + wire _T_176 = _T_174 | store_matchvec_hi_r[2]; // @[lsu_stbuf.scala 140:30] + wire _T_177 = io_ldst_stbuf_reqvld_r & _T_176; // @[lsu_stbuf.scala 136:76] + wire _T_178 = 2'h3 == WrPtr; // @[lsu_stbuf.scala 137:16] + wire _T_180 = _T_178 & _T_122; // @[lsu_stbuf.scala 137:27] + wire _T_182 = _T_178 & dual_stbuf_write_r; // @[lsu_stbuf.scala 138:29] + wire _T_184 = _T_182 & _T_126; // @[lsu_stbuf.scala 138:50] + wire _T_185 = _T_180 | _T_184; // @[lsu_stbuf.scala 137:51] + wire _T_186 = 2'h3 == WrPtrPlus1; // @[lsu_stbuf.scala 139:18] + wire _T_187 = _T_186 & dual_stbuf_write_r; // @[lsu_stbuf.scala 139:34] + wire _T_190 = _T_187 & _T_132; // @[lsu_stbuf.scala 139:55] + wire _T_191 = _T_185 | _T_190; // @[lsu_stbuf.scala 138:74] + wire _T_193 = _T_191 | store_matchvec_lo_r[3]; // @[lsu_stbuf.scala 139:103] + wire _T_195 = _T_193 | store_matchvec_hi_r[3]; // @[lsu_stbuf.scala 140:30] + wire _T_196 = io_ldst_stbuf_reqvld_r & _T_195; // @[lsu_stbuf.scala 136:76] + wire [3:0] stbuf_wr_en = {_T_196,_T_177,_T_158,_T_139}; // @[Cat.scala 29:58] + wire _T_219 = ~ldst_dual_r; // @[lsu_stbuf.scala 142:53] + wire _T_220 = _T_219 | io_store_stbuf_reqvld_r; // @[lsu_stbuf.scala 142:66] + wire _T_223 = _T_220 & _T_121; // @[lsu_stbuf.scala 142:93] + wire _T_225 = _T_223 & _T_122; // @[lsu_stbuf.scala 142:123] + wire _T_227 = _T_225 | store_matchvec_lo_r[0]; // @[lsu_stbuf.scala 142:147] + wire _T_232 = _T_220 & _T_140; // @[lsu_stbuf.scala 142:93] + wire _T_234 = _T_232 & _T_122; // @[lsu_stbuf.scala 142:123] + wire _T_236 = _T_234 | store_matchvec_lo_r[1]; // @[lsu_stbuf.scala 142:147] + wire _T_241 = _T_220 & _T_159; // @[lsu_stbuf.scala 142:93] + wire _T_243 = _T_241 & _T_122; // @[lsu_stbuf.scala 142:123] + wire _T_245 = _T_243 | store_matchvec_lo_r[2]; // @[lsu_stbuf.scala 142:147] + wire _T_250 = _T_220 & _T_178; // @[lsu_stbuf.scala 142:93] + wire _T_252 = _T_250 & _T_122; // @[lsu_stbuf.scala 142:123] + wire _T_254 = _T_252 | store_matchvec_lo_r[3]; // @[lsu_stbuf.scala 142:147] + wire [3:0] sel_lo = {_T_254,_T_245,_T_236,_T_227}; // @[Cat.scala 29:58] + reg [3:0] stbuf_byteen_0; // @[lsu_stbuf.scala 165:92] + wire [3:0] _T_274 = stbuf_byteen_0 | store_byteen_lo_r; // @[lsu_stbuf.scala 145:86] + wire [3:0] _T_275 = stbuf_byteen_0 | store_byteen_hi_r; // @[lsu_stbuf.scala 145:123] + wire [3:0] stbuf_byteenin_0 = sel_lo[0] ? _T_274 : _T_275; // @[lsu_stbuf.scala 145:58] + reg [3:0] stbuf_byteen_1; // @[lsu_stbuf.scala 165:92] + wire [3:0] _T_278 = stbuf_byteen_1 | store_byteen_lo_r; // @[lsu_stbuf.scala 145:86] + wire [3:0] _T_279 = stbuf_byteen_1 | store_byteen_hi_r; // @[lsu_stbuf.scala 145:123] + wire [3:0] stbuf_byteenin_1 = sel_lo[1] ? _T_278 : _T_279; // @[lsu_stbuf.scala 145:58] + reg [3:0] stbuf_byteen_2; // @[lsu_stbuf.scala 165:92] + wire [3:0] _T_282 = stbuf_byteen_2 | store_byteen_lo_r; // @[lsu_stbuf.scala 145:86] + wire [3:0] _T_283 = stbuf_byteen_2 | store_byteen_hi_r; // @[lsu_stbuf.scala 145:123] + wire [3:0] stbuf_byteenin_2 = sel_lo[2] ? _T_282 : _T_283; // @[lsu_stbuf.scala 145:58] + reg [3:0] stbuf_byteen_3; // @[lsu_stbuf.scala 165:92] + wire [3:0] _T_286 = stbuf_byteen_3 | store_byteen_lo_r; // @[lsu_stbuf.scala 145:86] + wire [3:0] _T_287 = stbuf_byteen_3 | store_byteen_hi_r; // @[lsu_stbuf.scala 145:123] + wire [3:0] stbuf_byteenin_3 = sel_lo[3] ? _T_286 : _T_287; // @[lsu_stbuf.scala 145:58] + wire _T_291 = ~stbuf_byteen_0[0]; // @[lsu_stbuf.scala 147:67] + wire _T_293 = _T_291 | store_byteen_lo_r[0]; // @[lsu_stbuf.scala 147:87] + reg [31:0] stbuf_data_0; // @[lib.scala 374:16] + wire [7:0] _T_296 = _T_293 ? io_store_datafn_lo_r[7:0] : stbuf_data_0[7:0]; // @[lsu_stbuf.scala 147:66] + wire _T_300 = _T_291 | store_byteen_hi_r[0]; // @[lsu_stbuf.scala 148:29] + wire [7:0] _T_303 = _T_300 ? io_store_datafn_hi_r[7:0] : stbuf_data_0[7:0]; // @[lsu_stbuf.scala 148:8] + wire [7:0] datain1_0 = sel_lo[0] ? _T_296 : _T_303; // @[lsu_stbuf.scala 147:51] + wire _T_307 = ~stbuf_byteen_1[0]; // @[lsu_stbuf.scala 147:67] + wire _T_309 = _T_307 | store_byteen_lo_r[0]; // @[lsu_stbuf.scala 147:87] + reg [31:0] stbuf_data_1; // @[lib.scala 374:16] + wire [7:0] _T_312 = _T_309 ? io_store_datafn_lo_r[7:0] : stbuf_data_1[7:0]; // @[lsu_stbuf.scala 147:66] + wire _T_316 = _T_307 | store_byteen_hi_r[0]; // @[lsu_stbuf.scala 148:29] + wire [7:0] _T_319 = _T_316 ? io_store_datafn_hi_r[7:0] : stbuf_data_1[7:0]; // @[lsu_stbuf.scala 148:8] + wire [7:0] datain1_1 = sel_lo[1] ? _T_312 : _T_319; // @[lsu_stbuf.scala 147:51] + wire _T_323 = ~stbuf_byteen_2[0]; // @[lsu_stbuf.scala 147:67] + wire _T_325 = _T_323 | store_byteen_lo_r[0]; // @[lsu_stbuf.scala 147:87] + reg [31:0] stbuf_data_2; // @[lib.scala 374:16] + wire [7:0] _T_328 = _T_325 ? io_store_datafn_lo_r[7:0] : stbuf_data_2[7:0]; // @[lsu_stbuf.scala 147:66] + wire _T_332 = _T_323 | store_byteen_hi_r[0]; // @[lsu_stbuf.scala 148:29] + wire [7:0] _T_335 = _T_332 ? io_store_datafn_hi_r[7:0] : stbuf_data_2[7:0]; // @[lsu_stbuf.scala 148:8] + wire [7:0] datain1_2 = sel_lo[2] ? _T_328 : _T_335; // @[lsu_stbuf.scala 147:51] + wire _T_339 = ~stbuf_byteen_3[0]; // @[lsu_stbuf.scala 147:67] + wire _T_341 = _T_339 | store_byteen_lo_r[0]; // @[lsu_stbuf.scala 147:87] + reg [31:0] stbuf_data_3; // @[lib.scala 374:16] + wire [7:0] _T_344 = _T_341 ? io_store_datafn_lo_r[7:0] : stbuf_data_3[7:0]; // @[lsu_stbuf.scala 147:66] + wire _T_348 = _T_339 | store_byteen_hi_r[0]; // @[lsu_stbuf.scala 148:29] + wire [7:0] _T_351 = _T_348 ? io_store_datafn_hi_r[7:0] : stbuf_data_3[7:0]; // @[lsu_stbuf.scala 148:8] + wire [7:0] datain1_3 = sel_lo[3] ? _T_344 : _T_351; // @[lsu_stbuf.scala 147:51] + wire _T_355 = ~stbuf_byteen_0[1]; // @[lsu_stbuf.scala 150:68] + wire _T_357 = _T_355 | store_byteen_lo_r[1]; // @[lsu_stbuf.scala 150:88] + wire [7:0] _T_360 = _T_357 ? io_store_datafn_lo_r[15:8] : stbuf_data_0[15:8]; // @[lsu_stbuf.scala 150:67] + wire _T_364 = _T_355 | store_byteen_hi_r[1]; // @[lsu_stbuf.scala 151:29] + wire [7:0] _T_367 = _T_364 ? io_store_datafn_hi_r[15:8] : stbuf_data_0[15:8]; // @[lsu_stbuf.scala 151:8] + wire [7:0] datain2_0 = sel_lo[0] ? _T_360 : _T_367; // @[lsu_stbuf.scala 150:52] + wire _T_371 = ~stbuf_byteen_1[1]; // @[lsu_stbuf.scala 150:68] + wire _T_373 = _T_371 | store_byteen_lo_r[1]; // @[lsu_stbuf.scala 150:88] + wire [7:0] _T_376 = _T_373 ? io_store_datafn_lo_r[15:8] : stbuf_data_1[15:8]; // @[lsu_stbuf.scala 150:67] + wire _T_380 = _T_371 | store_byteen_hi_r[1]; // @[lsu_stbuf.scala 151:29] + wire [7:0] _T_383 = _T_380 ? io_store_datafn_hi_r[15:8] : stbuf_data_1[15:8]; // @[lsu_stbuf.scala 151:8] + wire [7:0] datain2_1 = sel_lo[1] ? _T_376 : _T_383; // @[lsu_stbuf.scala 150:52] + wire _T_387 = ~stbuf_byteen_2[1]; // @[lsu_stbuf.scala 150:68] + wire _T_389 = _T_387 | store_byteen_lo_r[1]; // @[lsu_stbuf.scala 150:88] + wire [7:0] _T_392 = _T_389 ? io_store_datafn_lo_r[15:8] : stbuf_data_2[15:8]; // @[lsu_stbuf.scala 150:67] + wire _T_396 = _T_387 | store_byteen_hi_r[1]; // @[lsu_stbuf.scala 151:29] + wire [7:0] _T_399 = _T_396 ? io_store_datafn_hi_r[15:8] : stbuf_data_2[15:8]; // @[lsu_stbuf.scala 151:8] + wire [7:0] datain2_2 = sel_lo[2] ? _T_392 : _T_399; // @[lsu_stbuf.scala 150:52] + wire _T_403 = ~stbuf_byteen_3[1]; // @[lsu_stbuf.scala 150:68] + wire _T_405 = _T_403 | store_byteen_lo_r[1]; // @[lsu_stbuf.scala 150:88] + wire [7:0] _T_408 = _T_405 ? io_store_datafn_lo_r[15:8] : stbuf_data_3[15:8]; // @[lsu_stbuf.scala 150:67] + wire _T_412 = _T_403 | store_byteen_hi_r[1]; // @[lsu_stbuf.scala 151:29] + wire [7:0] _T_415 = _T_412 ? io_store_datafn_hi_r[15:8] : stbuf_data_3[15:8]; // @[lsu_stbuf.scala 151:8] + wire [7:0] datain2_3 = sel_lo[3] ? _T_408 : _T_415; // @[lsu_stbuf.scala 150:52] + wire _T_419 = ~stbuf_byteen_0[2]; // @[lsu_stbuf.scala 153:68] + wire _T_421 = _T_419 | store_byteen_lo_r[2]; // @[lsu_stbuf.scala 153:88] + wire [7:0] _T_424 = _T_421 ? io_store_datafn_lo_r[23:16] : stbuf_data_0[23:16]; // @[lsu_stbuf.scala 153:67] + wire _T_428 = _T_419 | store_byteen_hi_r[2]; // @[lsu_stbuf.scala 154:29] + wire [7:0] _T_431 = _T_428 ? io_store_datafn_hi_r[23:16] : stbuf_data_0[23:16]; // @[lsu_stbuf.scala 154:8] + wire [7:0] datain3_0 = sel_lo[0] ? _T_424 : _T_431; // @[lsu_stbuf.scala 153:52] + wire _T_435 = ~stbuf_byteen_1[2]; // @[lsu_stbuf.scala 153:68] + wire _T_437 = _T_435 | store_byteen_lo_r[2]; // @[lsu_stbuf.scala 153:88] + wire [7:0] _T_440 = _T_437 ? io_store_datafn_lo_r[23:16] : stbuf_data_1[23:16]; // @[lsu_stbuf.scala 153:67] + wire _T_444 = _T_435 | store_byteen_hi_r[2]; // @[lsu_stbuf.scala 154:29] + wire [7:0] _T_447 = _T_444 ? io_store_datafn_hi_r[23:16] : stbuf_data_1[23:16]; // @[lsu_stbuf.scala 154:8] + wire [7:0] datain3_1 = sel_lo[1] ? _T_440 : _T_447; // @[lsu_stbuf.scala 153:52] + wire _T_451 = ~stbuf_byteen_2[2]; // @[lsu_stbuf.scala 153:68] + wire _T_453 = _T_451 | store_byteen_lo_r[2]; // @[lsu_stbuf.scala 153:88] + wire [7:0] _T_456 = _T_453 ? io_store_datafn_lo_r[23:16] : stbuf_data_2[23:16]; // @[lsu_stbuf.scala 153:67] + wire _T_460 = _T_451 | store_byteen_hi_r[2]; // @[lsu_stbuf.scala 154:29] + wire [7:0] _T_463 = _T_460 ? io_store_datafn_hi_r[23:16] : stbuf_data_2[23:16]; // @[lsu_stbuf.scala 154:8] + wire [7:0] datain3_2 = sel_lo[2] ? _T_456 : _T_463; // @[lsu_stbuf.scala 153:52] + wire _T_467 = ~stbuf_byteen_3[2]; // @[lsu_stbuf.scala 153:68] + wire _T_469 = _T_467 | store_byteen_lo_r[2]; // @[lsu_stbuf.scala 153:88] + wire [7:0] _T_472 = _T_469 ? io_store_datafn_lo_r[23:16] : stbuf_data_3[23:16]; // @[lsu_stbuf.scala 153:67] + wire _T_476 = _T_467 | store_byteen_hi_r[2]; // @[lsu_stbuf.scala 154:29] + wire [7:0] _T_479 = _T_476 ? io_store_datafn_hi_r[23:16] : stbuf_data_3[23:16]; // @[lsu_stbuf.scala 154:8] + wire [7:0] datain3_3 = sel_lo[3] ? _T_472 : _T_479; // @[lsu_stbuf.scala 153:52] + wire _T_483 = ~stbuf_byteen_0[3]; // @[lsu_stbuf.scala 156:68] + wire _T_485 = _T_483 | store_byteen_lo_r[3]; // @[lsu_stbuf.scala 156:88] + wire [7:0] _T_488 = _T_485 ? io_store_datafn_lo_r[31:24] : stbuf_data_0[31:24]; // @[lsu_stbuf.scala 156:67] + wire _T_492 = _T_483 | store_byteen_hi_r[3]; // @[lsu_stbuf.scala 157:29] + wire [7:0] _T_495 = _T_492 ? io_store_datafn_hi_r[31:24] : stbuf_data_0[31:24]; // @[lsu_stbuf.scala 157:8] + wire [7:0] datain4_0 = sel_lo[0] ? _T_488 : _T_495; // @[lsu_stbuf.scala 156:52] + wire _T_499 = ~stbuf_byteen_1[3]; // @[lsu_stbuf.scala 156:68] + wire _T_501 = _T_499 | store_byteen_lo_r[3]; // @[lsu_stbuf.scala 156:88] + wire [7:0] _T_504 = _T_501 ? io_store_datafn_lo_r[31:24] : stbuf_data_1[31:24]; // @[lsu_stbuf.scala 156:67] + wire _T_508 = _T_499 | store_byteen_hi_r[3]; // @[lsu_stbuf.scala 157:29] + wire [7:0] _T_511 = _T_508 ? io_store_datafn_hi_r[31:24] : stbuf_data_1[31:24]; // @[lsu_stbuf.scala 157:8] + wire [7:0] datain4_1 = sel_lo[1] ? _T_504 : _T_511; // @[lsu_stbuf.scala 156:52] + wire _T_515 = ~stbuf_byteen_2[3]; // @[lsu_stbuf.scala 156:68] + wire _T_517 = _T_515 | store_byteen_lo_r[3]; // @[lsu_stbuf.scala 156:88] + wire [7:0] _T_520 = _T_517 ? io_store_datafn_lo_r[31:24] : stbuf_data_2[31:24]; // @[lsu_stbuf.scala 156:67] + wire _T_524 = _T_515 | store_byteen_hi_r[3]; // @[lsu_stbuf.scala 157:29] + wire [7:0] _T_527 = _T_524 ? io_store_datafn_hi_r[31:24] : stbuf_data_2[31:24]; // @[lsu_stbuf.scala 157:8] + wire [7:0] datain4_2 = sel_lo[2] ? _T_520 : _T_527; // @[lsu_stbuf.scala 156:52] + wire _T_531 = ~stbuf_byteen_3[3]; // @[lsu_stbuf.scala 156:68] + wire _T_533 = _T_531 | store_byteen_lo_r[3]; // @[lsu_stbuf.scala 156:88] + wire [7:0] _T_536 = _T_533 ? io_store_datafn_lo_r[31:24] : stbuf_data_3[31:24]; // @[lsu_stbuf.scala 156:67] + wire _T_540 = _T_531 | store_byteen_hi_r[3]; // @[lsu_stbuf.scala 157:29] + wire [7:0] _T_543 = _T_540 ? io_store_datafn_hi_r[31:24] : stbuf_data_3[31:24]; // @[lsu_stbuf.scala 157:8] + wire [7:0] datain4_3 = sel_lo[3] ? _T_536 : _T_543; // @[lsu_stbuf.scala 156:52] + wire [15:0] _T_545 = {datain2_0,datain1_0}; // @[Cat.scala 29:58] + wire [15:0] _T_546 = {datain4_0,datain3_0}; // @[Cat.scala 29:58] + wire [15:0] _T_548 = {datain2_1,datain1_1}; // @[Cat.scala 29:58] + wire [15:0] _T_549 = {datain4_1,datain3_1}; // @[Cat.scala 29:58] + wire [15:0] _T_551 = {datain2_2,datain1_2}; // @[Cat.scala 29:58] + wire [15:0] _T_552 = {datain4_2,datain3_2}; // @[Cat.scala 29:58] + wire [15:0] _T_554 = {datain2_3,datain1_3}; // @[Cat.scala 29:58] + wire [15:0] _T_555 = {datain4_3,datain3_3}; // @[Cat.scala 29:58] + wire _T_560 = stbuf_wr_en[0] | stbuf_vld[0]; // @[lsu_stbuf.scala 163:92] + wire _T_568 = stbuf_wr_en[1] | stbuf_vld[1]; // @[lsu_stbuf.scala 163:92] + wire _T_576 = stbuf_wr_en[2] | stbuf_vld[2]; // @[lsu_stbuf.scala 163:92] + wire _T_584 = stbuf_wr_en[3] | stbuf_vld[3]; // @[lsu_stbuf.scala 163:92] + wire [15:0] cmpaddr_hi_m = {{2'd0}, io_end_addr_m[15:2]}; // @[lsu_stbuf.scala 200:16] + wire _T_789 = stbuf_addr_3[15:2] == cmpaddr_hi_m[13:0]; // @[lsu_stbuf.scala 206:115] + wire _T_791 = _T_789 & stbuf_vld[3]; // @[lsu_stbuf.scala 206:139] + wire _T_794 = _T_791 & _T_64; // @[lsu_stbuf.scala 206:154] + wire _T_795 = _T_794 & io_addr_in_dccm_m; // @[lsu_stbuf.scala 206:175] + wire _T_780 = stbuf_addr_2[15:2] == cmpaddr_hi_m[13:0]; // @[lsu_stbuf.scala 206:115] + wire _T_782 = _T_780 & stbuf_vld[2]; // @[lsu_stbuf.scala 206:139] + wire _T_785 = _T_782 & _T_53; // @[lsu_stbuf.scala 206:154] + wire _T_786 = _T_785 & io_addr_in_dccm_m; // @[lsu_stbuf.scala 206:175] + wire _T_771 = stbuf_addr_1[15:2] == cmpaddr_hi_m[13:0]; // @[lsu_stbuf.scala 206:115] + wire _T_773 = _T_771 & stbuf_vld[1]; // @[lsu_stbuf.scala 206:139] + wire _T_776 = _T_773 & _T_42; // @[lsu_stbuf.scala 206:154] + wire _T_777 = _T_776 & io_addr_in_dccm_m; // @[lsu_stbuf.scala 206:175] + wire _T_762 = stbuf_addr_0[15:2] == cmpaddr_hi_m[13:0]; // @[lsu_stbuf.scala 206:115] + wire _T_764 = _T_762 & stbuf_vld[0]; // @[lsu_stbuf.scala 206:139] + wire _T_767 = _T_764 & _T_31; // @[lsu_stbuf.scala 206:154] + wire _T_768 = _T_767 & io_addr_in_dccm_m; // @[lsu_stbuf.scala 206:175] + wire [3:0] stbuf_match_hi = {_T_795,_T_786,_T_777,_T_768}; // @[Cat.scala 29:58] + wire [15:0] cmpaddr_lo_m = {{2'd0}, io_lsu_addr_m[15:2]}; // @[lsu_stbuf.scala 203:17] + wire _T_827 = stbuf_addr_3[15:2] == cmpaddr_lo_m[13:0]; // @[lsu_stbuf.scala 207:115] + wire _T_829 = _T_827 & stbuf_vld[3]; // @[lsu_stbuf.scala 207:139] + wire _T_832 = _T_829 & _T_64; // @[lsu_stbuf.scala 207:154] + wire _T_833 = _T_832 & io_addr_in_dccm_m; // @[lsu_stbuf.scala 207:175] + wire _T_818 = stbuf_addr_2[15:2] == cmpaddr_lo_m[13:0]; // @[lsu_stbuf.scala 207:115] + wire _T_820 = _T_818 & stbuf_vld[2]; // @[lsu_stbuf.scala 207:139] + wire _T_823 = _T_820 & _T_53; // @[lsu_stbuf.scala 207:154] + wire _T_824 = _T_823 & io_addr_in_dccm_m; // @[lsu_stbuf.scala 207:175] + wire _T_809 = stbuf_addr_1[15:2] == cmpaddr_lo_m[13:0]; // @[lsu_stbuf.scala 207:115] + wire _T_811 = _T_809 & stbuf_vld[1]; // @[lsu_stbuf.scala 207:139] + wire _T_814 = _T_811 & _T_42; // @[lsu_stbuf.scala 207:154] + wire _T_815 = _T_814 & io_addr_in_dccm_m; // @[lsu_stbuf.scala 207:175] + wire _T_800 = stbuf_addr_0[15:2] == cmpaddr_lo_m[13:0]; // @[lsu_stbuf.scala 207:115] + wire _T_802 = _T_800 & stbuf_vld[0]; // @[lsu_stbuf.scala 207:139] + wire _T_805 = _T_802 & _T_31; // @[lsu_stbuf.scala 207:154] + wire _T_806 = _T_805 & io_addr_in_dccm_m; // @[lsu_stbuf.scala 207:175] + wire [3:0] stbuf_match_lo = {_T_833,_T_824,_T_815,_T_806}; // @[Cat.scala 29:58] + wire _T_856 = stbuf_match_hi[3] | stbuf_match_lo[3]; // @[lsu_stbuf.scala 208:78] + wire _T_857 = _T_856 & io_lsu_pkt_m_valid; // @[lsu_stbuf.scala 208:99] + wire _T_858 = _T_857 & io_lsu_pkt_m_bits_dma; // @[lsu_stbuf.scala 208:120] + wire _T_859 = _T_858 & io_lsu_pkt_m_bits_store; // @[lsu_stbuf.scala 208:144] + wire _T_850 = stbuf_match_hi[2] | stbuf_match_lo[2]; // @[lsu_stbuf.scala 208:78] + wire _T_851 = _T_850 & io_lsu_pkt_m_valid; // @[lsu_stbuf.scala 208:99] + wire _T_852 = _T_851 & io_lsu_pkt_m_bits_dma; // @[lsu_stbuf.scala 208:120] + wire _T_853 = _T_852 & io_lsu_pkt_m_bits_store; // @[lsu_stbuf.scala 208:144] + wire _T_844 = stbuf_match_hi[1] | stbuf_match_lo[1]; // @[lsu_stbuf.scala 208:78] + wire _T_845 = _T_844 & io_lsu_pkt_m_valid; // @[lsu_stbuf.scala 208:99] + wire _T_846 = _T_845 & io_lsu_pkt_m_bits_dma; // @[lsu_stbuf.scala 208:120] + wire _T_847 = _T_846 & io_lsu_pkt_m_bits_store; // @[lsu_stbuf.scala 208:144] + wire _T_838 = stbuf_match_hi[0] | stbuf_match_lo[0]; // @[lsu_stbuf.scala 208:78] + wire _T_839 = _T_838 & io_lsu_pkt_m_valid; // @[lsu_stbuf.scala 208:99] + wire _T_840 = _T_839 & io_lsu_pkt_m_bits_dma; // @[lsu_stbuf.scala 208:120] + wire _T_841 = _T_840 & io_lsu_pkt_m_bits_store; // @[lsu_stbuf.scala 208:144] + wire [3:0] stbuf_dma_kill_en = {_T_859,_T_853,_T_847,_T_841}; // @[Cat.scala 29:58] + wire _T_595 = stbuf_dma_kill_en[0] | stbuf_dma_kill[0]; // @[lsu_stbuf.scala 164:96] + wire _T_603 = stbuf_dma_kill_en[1] | stbuf_dma_kill[1]; // @[lsu_stbuf.scala 164:96] + wire _T_611 = stbuf_dma_kill_en[2] | stbuf_dma_kill[2]; // @[lsu_stbuf.scala 164:96] + wire _T_619 = stbuf_dma_kill_en[3] | stbuf_dma_kill[3]; // @[lsu_stbuf.scala 164:96] + wire [3:0] _T_629 = stbuf_wr_en[0] ? stbuf_byteenin_0 : stbuf_byteen_0; // @[lsu_stbuf.scala 165:96] + wire [3:0] _T_633 = _T_34 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_638 = stbuf_wr_en[1] ? stbuf_byteenin_1 : stbuf_byteen_1; // @[lsu_stbuf.scala 165:96] + wire [3:0] _T_642 = _T_45 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_647 = stbuf_wr_en[2] ? stbuf_byteenin_2 : stbuf_byteen_2; // @[lsu_stbuf.scala 165:96] + wire [3:0] _T_651 = _T_56 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_656 = stbuf_wr_en[3] ? stbuf_byteenin_3 : stbuf_byteen_3; // @[lsu_stbuf.scala 165:96] + wire [3:0] _T_660 = _T_67 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + reg ldst_dual_m; // @[lsu_stbuf.scala 170:52] + wire [3:0] _T_689 = stbuf_vld >> RdPtr; // @[lsu_stbuf.scala 174:43] + wire [3:0] _T_691 = stbuf_dma_kill >> RdPtr; // @[lsu_stbuf.scala 174:67] + wire _T_698 = ~_T_691[0]; // @[lsu_stbuf.scala 175:46] + wire _T_699 = _T_689[0] & _T_698; // @[lsu_stbuf.scala 175:44] + wire _T_700 = |stbuf_dma_kill_en; // @[lsu_stbuf.scala 175:91] + wire _T_701 = ~_T_700; // @[lsu_stbuf.scala 175:71] + wire [15:0] _GEN_1 = 2'h1 == RdPtr ? stbuf_addr_1 : stbuf_addr_0; // @[lsu_stbuf.scala 176:22] + wire [15:0] _GEN_2 = 2'h2 == RdPtr ? stbuf_addr_2 : _GEN_1; // @[lsu_stbuf.scala 176:22] + wire [31:0] _GEN_5 = 2'h1 == RdPtr ? stbuf_data_1 : stbuf_data_0; // @[lsu_stbuf.scala 177:22] + wire [31:0] _GEN_6 = 2'h2 == RdPtr ? stbuf_data_2 : _GEN_5; // @[lsu_stbuf.scala 177:22] + wire _T_703 = ~dual_stbuf_write_r; // @[lsu_stbuf.scala 179:44] + wire _T_704 = io_ldst_stbuf_reqvld_r & _T_703; // @[lsu_stbuf.scala 179:42] + wire _T_705 = store_coalesce_hi_r | store_coalesce_lo_r; // @[lsu_stbuf.scala 179:88] + wire _T_706 = ~_T_705; // @[lsu_stbuf.scala 179:66] + wire _T_707 = _T_704 & _T_706; // @[lsu_stbuf.scala 179:64] + wire _T_708 = io_ldst_stbuf_reqvld_r & dual_stbuf_write_r; // @[lsu_stbuf.scala 180:30] + wire _T_709 = store_coalesce_hi_r & store_coalesce_lo_r; // @[lsu_stbuf.scala 180:76] + wire _T_710 = ~_T_709; // @[lsu_stbuf.scala 180:54] + wire _T_711 = _T_708 & _T_710; // @[lsu_stbuf.scala 180:52] + wire WrPtrEn = _T_707 | _T_711; // @[lsu_stbuf.scala 179:113] + wire _T_716 = _T_708 & _T_706; // @[lsu_stbuf.scala 181:67] + wire [3:0] _T_721 = {3'h0,stbuf_vld[0]}; // @[Cat.scala 29:58] + wire [3:0] _T_723 = {3'h0,stbuf_vld[1]}; // @[Cat.scala 29:58] + wire [3:0] _T_725 = {3'h0,stbuf_vld[2]}; // @[Cat.scala 29:58] + wire [3:0] _T_727 = {3'h0,stbuf_vld[3]}; // @[Cat.scala 29:58] + wire [3:0] _T_730 = _T_721 + _T_723; // @[lsu_stbuf.scala 188:101] + wire [3:0] _T_732 = _T_730 + _T_725; // @[lsu_stbuf.scala 188:101] + wire [3:0] stbuf_numvld_any = _T_732 + _T_727; // @[lsu_stbuf.scala 188:101] + wire _T_734 = io_lsu_pkt_m_valid & io_lsu_pkt_m_bits_store; // @[lsu_stbuf.scala 189:39] + wire _T_735 = _T_734 & io_addr_in_dccm_m; // @[lsu_stbuf.scala 189:65] + wire _T_736 = ~io_lsu_pkt_m_bits_dma; // @[lsu_stbuf.scala 189:87] + wire isdccmst_m = _T_735 & _T_736; // @[lsu_stbuf.scala 189:85] + wire _T_737 = io_lsu_pkt_r_valid & io_lsu_pkt_r_bits_store; // @[lsu_stbuf.scala 190:39] + wire _T_738 = _T_737 & io_addr_in_dccm_r; // @[lsu_stbuf.scala 190:65] + wire _T_739 = ~io_lsu_pkt_r_bits_dma; // @[lsu_stbuf.scala 190:87] + wire isdccmst_r = _T_738 & _T_739; // @[lsu_stbuf.scala 190:85] + wire [1:0] _T_740 = {1'h0,isdccmst_m}; // @[Cat.scala 29:58] + wire _T_741 = isdccmst_m & ldst_dual_m; // @[lsu_stbuf.scala 192:62] + wire [2:0] _GEN_14 = {{1'd0}, _T_740}; // @[lsu_stbuf.scala 192:47] + wire [2:0] _T_742 = _GEN_14 << _T_741; // @[lsu_stbuf.scala 192:47] + wire [1:0] _T_743 = {1'h0,isdccmst_r}; // @[Cat.scala 29:58] + wire _T_744 = isdccmst_r & ldst_dual_r; // @[lsu_stbuf.scala 193:62] + wire [2:0] _GEN_15 = {{1'd0}, _T_743}; // @[lsu_stbuf.scala 193:47] + wire [2:0] _T_745 = _GEN_15 << _T_744; // @[lsu_stbuf.scala 193:47] + wire [1:0] stbuf_specvld_m = _T_742[1:0]; // @[lsu_stbuf.scala 192:19] + wire [3:0] _T_746 = {2'h0,stbuf_specvld_m}; // @[Cat.scala 29:58] + wire [3:0] _T_748 = stbuf_numvld_any + _T_746; // @[lsu_stbuf.scala 194:44] + wire [1:0] stbuf_specvld_r = _T_745[1:0]; // @[lsu_stbuf.scala 193:19] + wire [3:0] _T_749 = {2'h0,stbuf_specvld_r}; // @[Cat.scala 29:58] + wire [3:0] stbuf_specvld_any = _T_748 + _T_749; // @[lsu_stbuf.scala 194:78] + wire _T_751 = ~ldst_dual_d; // @[lsu_stbuf.scala 196:34] + wire _T_752 = _T_751 & io_dec_lsu_valid_raw_d; // @[lsu_stbuf.scala 196:47] + wire _T_754 = stbuf_specvld_any >= 4'h4; // @[lsu_stbuf.scala 196:99] + wire _T_755 = stbuf_specvld_any >= 4'h3; // @[lsu_stbuf.scala 196:140] + wire _T_865 = stbuf_match_hi[0] & stbuf_byteen_0[0]; // @[lsu_stbuf.scala 211:116] + wire stbuf_fwdbyteenvec_hi_0_0 = _T_865 & stbuf_vld[0]; // @[lsu_stbuf.scala 211:137] + wire _T_869 = stbuf_match_hi[0] & stbuf_byteen_0[1]; // @[lsu_stbuf.scala 211:116] + wire stbuf_fwdbyteenvec_hi_0_1 = _T_869 & stbuf_vld[0]; // @[lsu_stbuf.scala 211:137] + wire _T_873 = stbuf_match_hi[0] & stbuf_byteen_0[2]; // @[lsu_stbuf.scala 211:116] + wire stbuf_fwdbyteenvec_hi_0_2 = _T_873 & stbuf_vld[0]; // @[lsu_stbuf.scala 211:137] + wire _T_877 = stbuf_match_hi[0] & stbuf_byteen_0[3]; // @[lsu_stbuf.scala 211:116] + wire stbuf_fwdbyteenvec_hi_0_3 = _T_877 & stbuf_vld[0]; // @[lsu_stbuf.scala 211:137] + wire _T_881 = stbuf_match_hi[1] & stbuf_byteen_1[0]; // @[lsu_stbuf.scala 211:116] + wire stbuf_fwdbyteenvec_hi_1_0 = _T_881 & stbuf_vld[1]; // @[lsu_stbuf.scala 211:137] + wire _T_885 = stbuf_match_hi[1] & stbuf_byteen_1[1]; // @[lsu_stbuf.scala 211:116] + wire stbuf_fwdbyteenvec_hi_1_1 = _T_885 & stbuf_vld[1]; // @[lsu_stbuf.scala 211:137] + wire _T_889 = stbuf_match_hi[1] & stbuf_byteen_1[2]; // @[lsu_stbuf.scala 211:116] + wire stbuf_fwdbyteenvec_hi_1_2 = _T_889 & stbuf_vld[1]; // @[lsu_stbuf.scala 211:137] + wire _T_893 = stbuf_match_hi[1] & stbuf_byteen_1[3]; // @[lsu_stbuf.scala 211:116] + wire stbuf_fwdbyteenvec_hi_1_3 = _T_893 & stbuf_vld[1]; // @[lsu_stbuf.scala 211:137] + wire _T_897 = stbuf_match_hi[2] & stbuf_byteen_2[0]; // @[lsu_stbuf.scala 211:116] + wire stbuf_fwdbyteenvec_hi_2_0 = _T_897 & stbuf_vld[2]; // @[lsu_stbuf.scala 211:137] + wire _T_901 = stbuf_match_hi[2] & stbuf_byteen_2[1]; // @[lsu_stbuf.scala 211:116] + wire stbuf_fwdbyteenvec_hi_2_1 = _T_901 & stbuf_vld[2]; // @[lsu_stbuf.scala 211:137] + wire _T_905 = stbuf_match_hi[2] & stbuf_byteen_2[2]; // @[lsu_stbuf.scala 211:116] + wire stbuf_fwdbyteenvec_hi_2_2 = _T_905 & stbuf_vld[2]; // @[lsu_stbuf.scala 211:137] + wire _T_909 = stbuf_match_hi[2] & stbuf_byteen_2[3]; // @[lsu_stbuf.scala 211:116] + wire stbuf_fwdbyteenvec_hi_2_3 = _T_909 & stbuf_vld[2]; // @[lsu_stbuf.scala 211:137] + wire _T_913 = stbuf_match_hi[3] & stbuf_byteen_3[0]; // @[lsu_stbuf.scala 211:116] + wire stbuf_fwdbyteenvec_hi_3_0 = _T_913 & stbuf_vld[3]; // @[lsu_stbuf.scala 211:137] + wire _T_917 = stbuf_match_hi[3] & stbuf_byteen_3[1]; // @[lsu_stbuf.scala 211:116] + wire stbuf_fwdbyteenvec_hi_3_1 = _T_917 & stbuf_vld[3]; // @[lsu_stbuf.scala 211:137] + wire _T_921 = stbuf_match_hi[3] & stbuf_byteen_3[2]; // @[lsu_stbuf.scala 211:116] + wire stbuf_fwdbyteenvec_hi_3_2 = _T_921 & stbuf_vld[3]; // @[lsu_stbuf.scala 211:137] + wire _T_925 = stbuf_match_hi[3] & stbuf_byteen_3[3]; // @[lsu_stbuf.scala 211:116] + wire stbuf_fwdbyteenvec_hi_3_3 = _T_925 & stbuf_vld[3]; // @[lsu_stbuf.scala 211:137] + wire _T_929 = stbuf_match_lo[0] & stbuf_byteen_0[0]; // @[lsu_stbuf.scala 212:116] + wire stbuf_fwdbyteenvec_lo_0_0 = _T_929 & stbuf_vld[0]; // @[lsu_stbuf.scala 212:137] + wire _T_933 = stbuf_match_lo[0] & stbuf_byteen_0[1]; // @[lsu_stbuf.scala 212:116] + wire stbuf_fwdbyteenvec_lo_0_1 = _T_933 & stbuf_vld[0]; // @[lsu_stbuf.scala 212:137] + wire _T_937 = stbuf_match_lo[0] & stbuf_byteen_0[2]; // @[lsu_stbuf.scala 212:116] + wire stbuf_fwdbyteenvec_lo_0_2 = _T_937 & stbuf_vld[0]; // @[lsu_stbuf.scala 212:137] + wire _T_941 = stbuf_match_lo[0] & stbuf_byteen_0[3]; // @[lsu_stbuf.scala 212:116] + wire stbuf_fwdbyteenvec_lo_0_3 = _T_941 & stbuf_vld[0]; // @[lsu_stbuf.scala 212:137] + wire _T_945 = stbuf_match_lo[1] & stbuf_byteen_1[0]; // @[lsu_stbuf.scala 212:116] + wire stbuf_fwdbyteenvec_lo_1_0 = _T_945 & stbuf_vld[1]; // @[lsu_stbuf.scala 212:137] + wire _T_949 = stbuf_match_lo[1] & stbuf_byteen_1[1]; // @[lsu_stbuf.scala 212:116] + wire stbuf_fwdbyteenvec_lo_1_1 = _T_949 & stbuf_vld[1]; // @[lsu_stbuf.scala 212:137] + wire _T_953 = stbuf_match_lo[1] & stbuf_byteen_1[2]; // @[lsu_stbuf.scala 212:116] + wire stbuf_fwdbyteenvec_lo_1_2 = _T_953 & stbuf_vld[1]; // @[lsu_stbuf.scala 212:137] + wire _T_957 = stbuf_match_lo[1] & stbuf_byteen_1[3]; // @[lsu_stbuf.scala 212:116] + wire stbuf_fwdbyteenvec_lo_1_3 = _T_957 & stbuf_vld[1]; // @[lsu_stbuf.scala 212:137] + wire _T_961 = stbuf_match_lo[2] & stbuf_byteen_2[0]; // @[lsu_stbuf.scala 212:116] + wire stbuf_fwdbyteenvec_lo_2_0 = _T_961 & stbuf_vld[2]; // @[lsu_stbuf.scala 212:137] + wire _T_965 = stbuf_match_lo[2] & stbuf_byteen_2[1]; // @[lsu_stbuf.scala 212:116] + wire stbuf_fwdbyteenvec_lo_2_1 = _T_965 & stbuf_vld[2]; // @[lsu_stbuf.scala 212:137] + wire _T_969 = stbuf_match_lo[2] & stbuf_byteen_2[2]; // @[lsu_stbuf.scala 212:116] + wire stbuf_fwdbyteenvec_lo_2_2 = _T_969 & stbuf_vld[2]; // @[lsu_stbuf.scala 212:137] + wire _T_973 = stbuf_match_lo[2] & stbuf_byteen_2[3]; // @[lsu_stbuf.scala 212:116] + wire stbuf_fwdbyteenvec_lo_2_3 = _T_973 & stbuf_vld[2]; // @[lsu_stbuf.scala 212:137] + wire _T_977 = stbuf_match_lo[3] & stbuf_byteen_3[0]; // @[lsu_stbuf.scala 212:116] + wire stbuf_fwdbyteenvec_lo_3_0 = _T_977 & stbuf_vld[3]; // @[lsu_stbuf.scala 212:137] + wire _T_981 = stbuf_match_lo[3] & stbuf_byteen_3[1]; // @[lsu_stbuf.scala 212:116] + wire stbuf_fwdbyteenvec_lo_3_1 = _T_981 & stbuf_vld[3]; // @[lsu_stbuf.scala 212:137] + wire _T_985 = stbuf_match_lo[3] & stbuf_byteen_3[2]; // @[lsu_stbuf.scala 212:116] + wire stbuf_fwdbyteenvec_lo_3_2 = _T_985 & stbuf_vld[3]; // @[lsu_stbuf.scala 212:137] + wire _T_989 = stbuf_match_lo[3] & stbuf_byteen_3[3]; // @[lsu_stbuf.scala 212:116] + wire stbuf_fwdbyteenvec_lo_3_3 = _T_989 & stbuf_vld[3]; // @[lsu_stbuf.scala 212:137] + wire _T_991 = stbuf_fwdbyteenvec_hi_0_0 | stbuf_fwdbyteenvec_hi_1_0; // @[lsu_stbuf.scala 213:147] + wire _T_992 = _T_991 | stbuf_fwdbyteenvec_hi_2_0; // @[lsu_stbuf.scala 213:147] + wire stbuf_fwdbyteen_hi_pre_m_0 = _T_992 | stbuf_fwdbyteenvec_hi_3_0; // @[lsu_stbuf.scala 213:147] + wire _T_993 = stbuf_fwdbyteenvec_hi_0_1 | stbuf_fwdbyteenvec_hi_1_1; // @[lsu_stbuf.scala 213:147] + wire _T_994 = _T_993 | stbuf_fwdbyteenvec_hi_2_1; // @[lsu_stbuf.scala 213:147] + wire stbuf_fwdbyteen_hi_pre_m_1 = _T_994 | stbuf_fwdbyteenvec_hi_3_1; // @[lsu_stbuf.scala 213:147] + wire _T_995 = stbuf_fwdbyteenvec_hi_0_2 | stbuf_fwdbyteenvec_hi_1_2; // @[lsu_stbuf.scala 213:147] + wire _T_996 = _T_995 | stbuf_fwdbyteenvec_hi_2_2; // @[lsu_stbuf.scala 213:147] + wire stbuf_fwdbyteen_hi_pre_m_2 = _T_996 | stbuf_fwdbyteenvec_hi_3_2; // @[lsu_stbuf.scala 213:147] + wire _T_997 = stbuf_fwdbyteenvec_hi_0_3 | stbuf_fwdbyteenvec_hi_1_3; // @[lsu_stbuf.scala 213:147] + wire _T_998 = _T_997 | stbuf_fwdbyteenvec_hi_2_3; // @[lsu_stbuf.scala 213:147] + wire stbuf_fwdbyteen_hi_pre_m_3 = _T_998 | stbuf_fwdbyteenvec_hi_3_3; // @[lsu_stbuf.scala 213:147] + wire _T_999 = stbuf_fwdbyteenvec_lo_0_0 | stbuf_fwdbyteenvec_lo_1_0; // @[lsu_stbuf.scala 214:147] + wire _T_1000 = _T_999 | stbuf_fwdbyteenvec_lo_2_0; // @[lsu_stbuf.scala 214:147] + wire stbuf_fwdbyteen_lo_pre_m_0 = _T_1000 | stbuf_fwdbyteenvec_lo_3_0; // @[lsu_stbuf.scala 214:147] + wire _T_1001 = stbuf_fwdbyteenvec_lo_0_1 | stbuf_fwdbyteenvec_lo_1_1; // @[lsu_stbuf.scala 214:147] + wire _T_1002 = _T_1001 | stbuf_fwdbyteenvec_lo_2_1; // @[lsu_stbuf.scala 214:147] + wire stbuf_fwdbyteen_lo_pre_m_1 = _T_1002 | stbuf_fwdbyteenvec_lo_3_1; // @[lsu_stbuf.scala 214:147] + wire _T_1003 = stbuf_fwdbyteenvec_lo_0_2 | stbuf_fwdbyteenvec_lo_1_2; // @[lsu_stbuf.scala 214:147] + wire _T_1004 = _T_1003 | stbuf_fwdbyteenvec_lo_2_2; // @[lsu_stbuf.scala 214:147] + wire stbuf_fwdbyteen_lo_pre_m_2 = _T_1004 | stbuf_fwdbyteenvec_lo_3_2; // @[lsu_stbuf.scala 214:147] + wire _T_1005 = stbuf_fwdbyteenvec_lo_0_3 | stbuf_fwdbyteenvec_lo_1_3; // @[lsu_stbuf.scala 214:147] + wire _T_1006 = _T_1005 | stbuf_fwdbyteenvec_lo_2_3; // @[lsu_stbuf.scala 214:147] + wire stbuf_fwdbyteen_lo_pre_m_3 = _T_1006 | stbuf_fwdbyteenvec_lo_3_3; // @[lsu_stbuf.scala 214:147] + wire [31:0] _T_1009 = stbuf_match_hi[0] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_1010 = _T_1009 & stbuf_data_0; // @[lsu_stbuf.scala 216:97] + wire [31:0] _T_1013 = stbuf_match_hi[1] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_1014 = _T_1013 & stbuf_data_1; // @[lsu_stbuf.scala 216:97] + wire [31:0] _T_1017 = stbuf_match_hi[2] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_1018 = _T_1017 & stbuf_data_2; // @[lsu_stbuf.scala 216:97] + wire [31:0] _T_1021 = stbuf_match_hi[3] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_1022 = _T_1021 & stbuf_data_3; // @[lsu_stbuf.scala 216:97] + wire [31:0] _T_1024 = _T_1022 | _T_1018; // @[lsu_stbuf.scala 216:130] + wire [31:0] _T_1025 = _T_1024 | _T_1014; // @[lsu_stbuf.scala 216:130] + wire [31:0] stbuf_fwddata_hi_pre_m = _T_1025 | _T_1010; // @[lsu_stbuf.scala 216:130] + wire [31:0] _T_1028 = stbuf_match_lo[0] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_1029 = _T_1028 & stbuf_data_0; // @[lsu_stbuf.scala 217:97] + wire [31:0] _T_1032 = stbuf_match_lo[1] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_1033 = _T_1032 & stbuf_data_1; // @[lsu_stbuf.scala 217:97] + wire [31:0] _T_1036 = stbuf_match_lo[2] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_1037 = _T_1036 & stbuf_data_2; // @[lsu_stbuf.scala 217:97] + wire [31:0] _T_1040 = stbuf_match_lo[3] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_1041 = _T_1040 & stbuf_data_3; // @[lsu_stbuf.scala 217:97] + wire [31:0] _T_1043 = _T_1041 | _T_1037; // @[lsu_stbuf.scala 217:130] + wire [31:0] _T_1044 = _T_1043 | _T_1033; // @[lsu_stbuf.scala 217:130] + wire [31:0] stbuf_fwddata_lo_pre_m = _T_1044 | _T_1029; // @[lsu_stbuf.scala 217:130] + wire _T_1049 = io_lsu_addr_m[31:2] == io_lsu_addr_r[31:2]; // @[lsu_stbuf.scala 224:49] + wire _T_1050 = _T_1049 & io_lsu_pkt_r_valid; // @[lsu_stbuf.scala 224:74] + wire _T_1051 = _T_1050 & io_lsu_pkt_r_bits_store; // @[lsu_stbuf.scala 224:95] + wire ld_addr_rhit_lo_lo = _T_1051 & _T_739; // @[lsu_stbuf.scala 224:121] + wire _T_1055 = io_end_addr_m[31:2] == io_lsu_addr_r[31:2]; // @[lsu_stbuf.scala 225:49] + wire _T_1056 = _T_1055 & io_lsu_pkt_r_valid; // @[lsu_stbuf.scala 225:74] + wire _T_1057 = _T_1056 & io_lsu_pkt_r_bits_store; // @[lsu_stbuf.scala 225:95] + wire ld_addr_rhit_lo_hi = _T_1057 & _T_739; // @[lsu_stbuf.scala 225:121] + wire _T_1061 = io_lsu_addr_m[31:2] == io_end_addr_r[31:2]; // @[lsu_stbuf.scala 226:49] + wire _T_1062 = _T_1061 & io_lsu_pkt_r_valid; // @[lsu_stbuf.scala 226:74] + wire _T_1063 = _T_1062 & io_lsu_pkt_r_bits_store; // @[lsu_stbuf.scala 226:95] + wire _T_1065 = _T_1063 & _T_739; // @[lsu_stbuf.scala 226:121] + wire ld_addr_rhit_hi_lo = _T_1065 & dual_stbuf_write_r; // @[lsu_stbuf.scala 226:146] + wire _T_1068 = io_end_addr_m[31:2] == io_end_addr_r[31:2]; // @[lsu_stbuf.scala 227:49] + wire _T_1069 = _T_1068 & io_lsu_pkt_r_valid; // @[lsu_stbuf.scala 227:74] + wire _T_1070 = _T_1069 & io_lsu_pkt_r_bits_store; // @[lsu_stbuf.scala 227:95] + wire _T_1072 = _T_1070 & _T_739; // @[lsu_stbuf.scala 227:121] + wire ld_addr_rhit_hi_hi = _T_1072 & dual_stbuf_write_r; // @[lsu_stbuf.scala 227:146] + wire _T_1074 = ld_addr_rhit_lo_lo & store_byteen_ext_r[0]; // @[lsu_stbuf.scala 229:79] + wire _T_1076 = ld_addr_rhit_lo_lo & store_byteen_ext_r[1]; // @[lsu_stbuf.scala 229:79] + wire _T_1078 = ld_addr_rhit_lo_lo & store_byteen_ext_r[2]; // @[lsu_stbuf.scala 229:79] + wire _T_1080 = ld_addr_rhit_lo_lo & store_byteen_ext_r[3]; // @[lsu_stbuf.scala 229:79] + wire [3:0] ld_byte_rhit_lo_lo = {_T_1080,_T_1078,_T_1076,_T_1074}; // @[Cat.scala 29:58] + wire _T_1085 = ld_addr_rhit_lo_hi & store_byteen_ext_r[0]; // @[lsu_stbuf.scala 230:79] + wire _T_1087 = ld_addr_rhit_lo_hi & store_byteen_ext_r[1]; // @[lsu_stbuf.scala 230:79] + wire _T_1089 = ld_addr_rhit_lo_hi & store_byteen_ext_r[2]; // @[lsu_stbuf.scala 230:79] + wire _T_1091 = ld_addr_rhit_lo_hi & store_byteen_ext_r[3]; // @[lsu_stbuf.scala 230:79] + wire [3:0] ld_byte_rhit_lo_hi = {_T_1091,_T_1089,_T_1087,_T_1085}; // @[Cat.scala 29:58] + wire _T_1096 = ld_addr_rhit_hi_lo & store_byteen_ext_r[4]; // @[lsu_stbuf.scala 231:79] + wire _T_1098 = ld_addr_rhit_hi_lo & store_byteen_ext_r[5]; // @[lsu_stbuf.scala 231:79] + wire _T_1100 = ld_addr_rhit_hi_lo & store_byteen_ext_r[6]; // @[lsu_stbuf.scala 231:79] + wire _T_1102 = ld_addr_rhit_hi_lo & store_byteen_ext_r[7]; // @[lsu_stbuf.scala 231:79] + wire [3:0] ld_byte_rhit_hi_lo = {_T_1102,_T_1100,_T_1098,_T_1096}; // @[Cat.scala 29:58] + wire _T_1107 = ld_addr_rhit_hi_hi & store_byteen_ext_r[4]; // @[lsu_stbuf.scala 232:79] + wire _T_1109 = ld_addr_rhit_hi_hi & store_byteen_ext_r[5]; // @[lsu_stbuf.scala 232:79] + wire _T_1111 = ld_addr_rhit_hi_hi & store_byteen_ext_r[6]; // @[lsu_stbuf.scala 232:79] + wire _T_1113 = ld_addr_rhit_hi_hi & store_byteen_ext_r[7]; // @[lsu_stbuf.scala 232:79] + wire [3:0] ld_byte_rhit_hi_hi = {_T_1113,_T_1111,_T_1109,_T_1107}; // @[Cat.scala 29:58] + wire _T_1119 = ld_byte_rhit_lo_lo[0] | ld_byte_rhit_hi_lo[0]; // @[lsu_stbuf.scala 234:79] + wire _T_1122 = ld_byte_rhit_lo_lo[1] | ld_byte_rhit_hi_lo[1]; // @[lsu_stbuf.scala 234:79] + wire _T_1125 = ld_byte_rhit_lo_lo[2] | ld_byte_rhit_hi_lo[2]; // @[lsu_stbuf.scala 234:79] + wire _T_1128 = ld_byte_rhit_lo_lo[3] | ld_byte_rhit_hi_lo[3]; // @[lsu_stbuf.scala 234:79] + wire [3:0] ld_byte_rhit_lo = {_T_1128,_T_1125,_T_1122,_T_1119}; // @[Cat.scala 29:58] + wire _T_1134 = ld_byte_rhit_lo_hi[0] | ld_byte_rhit_hi_hi[0]; // @[lsu_stbuf.scala 235:79] + wire _T_1137 = ld_byte_rhit_lo_hi[1] | ld_byte_rhit_hi_hi[1]; // @[lsu_stbuf.scala 235:79] + wire _T_1140 = ld_byte_rhit_lo_hi[2] | ld_byte_rhit_hi_hi[2]; // @[lsu_stbuf.scala 235:79] + wire _T_1143 = ld_byte_rhit_lo_hi[3] | ld_byte_rhit_hi_hi[3]; // @[lsu_stbuf.scala 235:79] + wire [3:0] ld_byte_rhit_hi = {_T_1143,_T_1140,_T_1137,_T_1134}; // @[Cat.scala 29:58] + wire [7:0] _T_1149 = ld_byte_rhit_lo_lo[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1151 = _T_1149 & io_store_data_lo_r[7:0]; // @[lsu_stbuf.scala 237:53] + wire [7:0] _T_1154 = ld_byte_rhit_hi_lo[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1156 = _T_1154 & io_store_data_hi_r[7:0]; // @[lsu_stbuf.scala 237:114] + wire [7:0] fwdpipe1_lo = _T_1151 | _T_1156; // @[lsu_stbuf.scala 237:80] + wire [7:0] _T_1159 = ld_byte_rhit_lo_lo[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1161 = _T_1159 & io_store_data_lo_r[15:8]; // @[lsu_stbuf.scala 238:53] + wire [7:0] _T_1164 = ld_byte_rhit_hi_lo[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1166 = _T_1164 & io_store_data_hi_r[15:8]; // @[lsu_stbuf.scala 238:115] + wire [7:0] fwdpipe2_lo = _T_1161 | _T_1166; // @[lsu_stbuf.scala 238:81] + wire [7:0] _T_1169 = ld_byte_rhit_lo_lo[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1171 = _T_1169 & io_store_data_lo_r[23:16]; // @[lsu_stbuf.scala 239:53] + wire [7:0] _T_1174 = ld_byte_rhit_hi_lo[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1176 = _T_1174 & io_store_data_hi_r[23:16]; // @[lsu_stbuf.scala 239:116] + wire [7:0] fwdpipe3_lo = _T_1171 | _T_1176; // @[lsu_stbuf.scala 239:82] + wire [7:0] _T_1179 = ld_byte_rhit_lo_lo[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1181 = _T_1179 & io_store_data_lo_r[31:24]; // @[lsu_stbuf.scala 240:53] + wire [7:0] _T_1184 = ld_byte_rhit_hi_lo[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1186 = _T_1184 & io_store_data_hi_r[31:24]; // @[lsu_stbuf.scala 240:116] + wire [7:0] fwdpipe4_lo = _T_1181 | _T_1186; // @[lsu_stbuf.scala 240:82] + wire [31:0] ld_fwddata_rpipe_lo = {fwdpipe4_lo,fwdpipe3_lo,fwdpipe2_lo,fwdpipe1_lo}; // @[Cat.scala 29:58] + wire [7:0] _T_1192 = ld_byte_rhit_lo_hi[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1194 = _T_1192 & io_store_data_lo_r[7:0]; // @[lsu_stbuf.scala 243:53] + wire [7:0] _T_1197 = ld_byte_rhit_hi_hi[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1199 = _T_1197 & io_store_data_hi_r[7:0]; // @[lsu_stbuf.scala 243:114] + wire [7:0] fwdpipe1_hi = _T_1194 | _T_1199; // @[lsu_stbuf.scala 243:80] + wire [7:0] _T_1202 = ld_byte_rhit_lo_hi[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1204 = _T_1202 & io_store_data_lo_r[15:8]; // @[lsu_stbuf.scala 244:53] + wire [7:0] _T_1207 = ld_byte_rhit_hi_hi[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1209 = _T_1207 & io_store_data_hi_r[15:8]; // @[lsu_stbuf.scala 244:115] + wire [7:0] fwdpipe2_hi = _T_1204 | _T_1209; // @[lsu_stbuf.scala 244:81] + wire [7:0] _T_1212 = ld_byte_rhit_lo_hi[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1214 = _T_1212 & io_store_data_lo_r[23:16]; // @[lsu_stbuf.scala 245:53] + wire [7:0] _T_1217 = ld_byte_rhit_hi_hi[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1219 = _T_1217 & io_store_data_hi_r[23:16]; // @[lsu_stbuf.scala 245:116] + wire [7:0] fwdpipe3_hi = _T_1214 | _T_1219; // @[lsu_stbuf.scala 245:82] + wire [7:0] _T_1222 = ld_byte_rhit_lo_hi[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1224 = _T_1222 & io_store_data_lo_r[31:24]; // @[lsu_stbuf.scala 246:53] + wire [7:0] _T_1227 = ld_byte_rhit_hi_hi[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1229 = _T_1227 & io_store_data_hi_r[31:24]; // @[lsu_stbuf.scala 246:116] + wire [7:0] fwdpipe4_hi = _T_1224 | _T_1229; // @[lsu_stbuf.scala 246:82] + wire [31:0] ld_fwddata_rpipe_hi = {fwdpipe4_hi,fwdpipe3_hi,fwdpipe2_hi,fwdpipe1_hi}; // @[Cat.scala 29:58] + wire _T_1264 = ld_byte_rhit_hi[0] | stbuf_fwdbyteen_hi_pre_m_0; // @[lsu_stbuf.scala 252:83] + wire _T_1266 = ld_byte_rhit_hi[1] | stbuf_fwdbyteen_hi_pre_m_1; // @[lsu_stbuf.scala 252:83] + wire _T_1268 = ld_byte_rhit_hi[2] | stbuf_fwdbyteen_hi_pre_m_2; // @[lsu_stbuf.scala 252:83] + wire _T_1270 = ld_byte_rhit_hi[3] | stbuf_fwdbyteen_hi_pre_m_3; // @[lsu_stbuf.scala 252:83] + wire [2:0] _T_1272 = {_T_1270,_T_1268,_T_1266}; // @[Cat.scala 29:58] + wire _T_1275 = ld_byte_rhit_lo[0] | stbuf_fwdbyteen_lo_pre_m_0; // @[lsu_stbuf.scala 253:83] + wire _T_1277 = ld_byte_rhit_lo[1] | stbuf_fwdbyteen_lo_pre_m_1; // @[lsu_stbuf.scala 253:83] + wire _T_1279 = ld_byte_rhit_lo[2] | stbuf_fwdbyteen_lo_pre_m_2; // @[lsu_stbuf.scala 253:83] + wire _T_1281 = ld_byte_rhit_lo[3] | stbuf_fwdbyteen_lo_pre_m_3; // @[lsu_stbuf.scala 253:83] + wire [2:0] _T_1283 = {_T_1281,_T_1279,_T_1277}; // @[Cat.scala 29:58] + wire [7:0] stbuf_fwdpipe1_lo = ld_byte_rhit_lo[0] ? ld_fwddata_rpipe_lo[7:0] : stbuf_fwddata_lo_pre_m[7:0]; // @[lsu_stbuf.scala 256:30] + wire [7:0] stbuf_fwdpipe2_lo = ld_byte_rhit_lo[1] ? ld_fwddata_rpipe_lo[15:8] : stbuf_fwddata_lo_pre_m[15:8]; // @[lsu_stbuf.scala 257:30] + wire [7:0] stbuf_fwdpipe3_lo = ld_byte_rhit_lo[2] ? ld_fwddata_rpipe_lo[23:16] : stbuf_fwddata_lo_pre_m[23:16]; // @[lsu_stbuf.scala 258:30] + wire [7:0] stbuf_fwdpipe4_lo = ld_byte_rhit_lo[3] ? ld_fwddata_rpipe_lo[31:24] : stbuf_fwddata_lo_pre_m[31:24]; // @[lsu_stbuf.scala 259:30] + wire [15:0] _T_1297 = {stbuf_fwdpipe2_lo,stbuf_fwdpipe1_lo}; // @[Cat.scala 29:58] + wire [15:0] _T_1298 = {stbuf_fwdpipe4_lo,stbuf_fwdpipe3_lo}; // @[Cat.scala 29:58] + wire [7:0] stbuf_fwdpipe1_hi = ld_byte_rhit_hi[0] ? ld_fwddata_rpipe_hi[7:0] : stbuf_fwddata_hi_pre_m[7:0]; // @[lsu_stbuf.scala 262:30] + wire [7:0] stbuf_fwdpipe2_hi = ld_byte_rhit_hi[1] ? ld_fwddata_rpipe_hi[15:8] : stbuf_fwddata_hi_pre_m[15:8]; // @[lsu_stbuf.scala 263:30] + wire [7:0] stbuf_fwdpipe3_hi = ld_byte_rhit_hi[2] ? ld_fwddata_rpipe_hi[23:16] : stbuf_fwddata_hi_pre_m[23:16]; // @[lsu_stbuf.scala 264:30] + wire [7:0] stbuf_fwdpipe4_hi = ld_byte_rhit_hi[3] ? ld_fwddata_rpipe_hi[31:24] : stbuf_fwddata_hi_pre_m[31:24]; // @[lsu_stbuf.scala 265:30] + wire [15:0] _T_1312 = {stbuf_fwdpipe2_hi,stbuf_fwdpipe1_hi}; // @[Cat.scala 29:58] + wire [15:0] _T_1313 = {stbuf_fwdpipe4_hi,stbuf_fwdpipe3_hi}; // @[Cat.scala 29:58] + rvclkhdr rvclkhdr ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) + ); + rvclkhdr rvclkhdr_1 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_1_io_l1clk), + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en), + .io_scan_mode(rvclkhdr_1_io_scan_mode) + ); + rvclkhdr rvclkhdr_2 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_2_io_l1clk), + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en), + .io_scan_mode(rvclkhdr_2_io_scan_mode) + ); + rvclkhdr rvclkhdr_3 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_3_io_l1clk), + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en), + .io_scan_mode(rvclkhdr_3_io_scan_mode) + ); + rvclkhdr rvclkhdr_4 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_4_io_l1clk), + .io_clk(rvclkhdr_4_io_clk), + .io_en(rvclkhdr_4_io_en), + .io_scan_mode(rvclkhdr_4_io_scan_mode) + ); + rvclkhdr rvclkhdr_5 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_5_io_l1clk), + .io_clk(rvclkhdr_5_io_clk), + .io_en(rvclkhdr_5_io_en), + .io_scan_mode(rvclkhdr_5_io_scan_mode) + ); + rvclkhdr rvclkhdr_6 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_6_io_l1clk), + .io_clk(rvclkhdr_6_io_clk), + .io_en(rvclkhdr_6_io_en), + .io_scan_mode(rvclkhdr_6_io_scan_mode) + ); + rvclkhdr rvclkhdr_7 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_7_io_l1clk), + .io_clk(rvclkhdr_7_io_clk), + .io_en(rvclkhdr_7_io_en), + .io_scan_mode(rvclkhdr_7_io_scan_mode) + ); + assign io_stbuf_reqvld_any = _T_699 & _T_701; // @[lsu_stbuf.scala 51:47 lsu_stbuf.scala 175:24] + assign io_stbuf_reqvld_flushed_any = _T_689[0] & _T_691[0]; // @[lsu_stbuf.scala 52:35 lsu_stbuf.scala 174:31] + assign io_stbuf_addr_any = 2'h3 == RdPtr ? stbuf_addr_3 : _GEN_2; // @[lsu_stbuf.scala 53:35 lsu_stbuf.scala 176:22] + assign io_stbuf_data_any = 2'h3 == RdPtr ? stbuf_data_3 : _GEN_6; // @[lsu_stbuf.scala 54:35 lsu_stbuf.scala 177:22] + assign io_lsu_stbuf_full_any = _T_752 ? _T_754 : _T_755; // @[lsu_stbuf.scala 55:43 lsu_stbuf.scala 196:26] + assign io_lsu_stbuf_empty_any = stbuf_numvld_any == 4'h0; // @[lsu_stbuf.scala 56:43 lsu_stbuf.scala 197:26] + assign io_ldst_stbuf_reqvld_r = io_lsu_commit_r & io_store_stbuf_reqvld_r; // @[lsu_stbuf.scala 57:43 lsu_stbuf.scala 128:26] + assign io_stbuf_fwddata_hi_m = {_T_1313,_T_1312}; // @[lsu_stbuf.scala 58:43 lsu_stbuf.scala 266:25] + assign io_stbuf_fwddata_lo_m = {_T_1298,_T_1297}; // @[lsu_stbuf.scala 59:43 lsu_stbuf.scala 260:25] + assign io_stbuf_fwdbyteen_hi_m = {_T_1272,_T_1264}; // @[lsu_stbuf.scala 60:37 lsu_stbuf.scala 252:27] + assign io_stbuf_fwdbyteen_lo_m = {_T_1283,_T_1275}; // @[lsu_stbuf.scala 61:37 lsu_stbuf.scala 253:27] + assign rvclkhdr_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_io_en = stbuf_wr_en[0]; // @[lib.scala 371:17] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_1_io_en = stbuf_wr_en[0]; // @[lib.scala 371:17] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_2_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_2_io_en = stbuf_wr_en[1]; // @[lib.scala 371:17] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_3_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_3_io_en = stbuf_wr_en[1]; // @[lib.scala 371:17] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_4_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_4_io_en = stbuf_wr_en[2]; // @[lib.scala 371:17] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_5_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_5_io_en = stbuf_wr_en[2]; // @[lib.scala 371:17] + assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_6_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_6_io_en = stbuf_wr_en[3]; // @[lib.scala 371:17] + assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_7_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_7_io_en = stbuf_wr_en[3]; // @[lib.scala 371:17] + assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + ldst_dual_r = _RAND_0[0:0]; + _RAND_1 = {1{`RANDOM}}; + RdPtr = _RAND_1[1:0]; + _RAND_2 = {1{`RANDOM}}; + WrPtr = _RAND_2[1:0]; + _RAND_3 = {1{`RANDOM}}; + stbuf_addr_0 = _RAND_3[15:0]; + _RAND_4 = {1{`RANDOM}}; + _T_588 = _RAND_4[0:0]; + _RAND_5 = {1{`RANDOM}}; + _T_580 = _RAND_5[0:0]; + _RAND_6 = {1{`RANDOM}}; + _T_572 = _RAND_6[0:0]; + _RAND_7 = {1{`RANDOM}}; + _T_564 = _RAND_7[0:0]; + _RAND_8 = {1{`RANDOM}}; + _T_623 = _RAND_8[0:0]; + _RAND_9 = {1{`RANDOM}}; + _T_615 = _RAND_9[0:0]; + _RAND_10 = {1{`RANDOM}}; + _T_607 = _RAND_10[0:0]; + _RAND_11 = {1{`RANDOM}}; + _T_599 = _RAND_11[0:0]; + _RAND_12 = {1{`RANDOM}}; + stbuf_addr_1 = _RAND_12[15:0]; + _RAND_13 = {1{`RANDOM}}; + stbuf_addr_2 = _RAND_13[15:0]; + _RAND_14 = {1{`RANDOM}}; + stbuf_addr_3 = _RAND_14[15:0]; + _RAND_15 = {1{`RANDOM}}; + stbuf_byteen_0 = _RAND_15[3:0]; + _RAND_16 = {1{`RANDOM}}; + stbuf_byteen_1 = _RAND_16[3:0]; + _RAND_17 = {1{`RANDOM}}; + stbuf_byteen_2 = _RAND_17[3:0]; + _RAND_18 = {1{`RANDOM}}; + stbuf_byteen_3 = _RAND_18[3:0]; + _RAND_19 = {1{`RANDOM}}; + stbuf_data_0 = _RAND_19[31:0]; + _RAND_20 = {1{`RANDOM}}; + stbuf_data_1 = _RAND_20[31:0]; + _RAND_21 = {1{`RANDOM}}; + stbuf_data_2 = _RAND_21[31:0]; + _RAND_22 = {1{`RANDOM}}; + stbuf_data_3 = _RAND_22[31:0]; + _RAND_23 = {1{`RANDOM}}; + ldst_dual_m = _RAND_23[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + ldst_dual_r = 1'h0; + end + if (reset) begin + RdPtr = 2'h0; + end + if (reset) begin + WrPtr = 2'h0; + end + if (reset) begin + stbuf_addr_0 = 16'h0; + end + if (reset) begin + _T_588 = 1'h0; + end + if (reset) begin + _T_580 = 1'h0; + end + if (reset) begin + _T_572 = 1'h0; + end + if (reset) begin + _T_564 = 1'h0; + end + if (reset) begin + _T_623 = 1'h0; + end + if (reset) begin + _T_615 = 1'h0; + end + if (reset) begin + _T_607 = 1'h0; + end + if (reset) begin + _T_599 = 1'h0; + end + if (reset) begin + stbuf_addr_1 = 16'h0; + end + if (reset) begin + stbuf_addr_2 = 16'h0; + end + if (reset) begin + stbuf_addr_3 = 16'h0; + end + if (reset) begin + stbuf_byteen_0 = 4'h0; + end + if (reset) begin + stbuf_byteen_1 = 4'h0; + end + if (reset) begin + stbuf_byteen_2 = 4'h0; + end + if (reset) begin + stbuf_byteen_3 = 4'h0; + end + if (reset) begin + stbuf_data_0 = 32'h0; + end + if (reset) begin + stbuf_data_1 = 32'h0; + end + if (reset) begin + stbuf_data_2 = 32'h0; + end + if (reset) begin + stbuf_data_3 = 32'h0; + end + if (reset) begin + ldst_dual_m = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + ldst_dual_r <= 1'h0; + end else begin + ldst_dual_r <= ldst_dual_m; + end + end + always @(posedge io_lsu_stbuf_c1_clk or posedge reset) begin + if (reset) begin + RdPtr <= 2'h0; + end else if (_T_212) begin + RdPtr <= RdPtrPlus1; + end + end + always @(posedge io_lsu_stbuf_c1_clk or posedge reset) begin + if (reset) begin + WrPtr <= 2'h0; + end else if (WrPtrEn) begin + if (_T_716) begin + WrPtr <= WrPtrPlus2; + end else begin + WrPtr <= WrPtrPlus1; + end + end + end + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + if (reset) begin + stbuf_addr_0 <= 16'h0; + end else if (sel_lo[0]) begin + stbuf_addr_0 <= io_lsu_addr_r[15:0]; + end else begin + stbuf_addr_0 <= io_end_addr_r[15:0]; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + _T_588 <= 1'h0; + end else begin + _T_588 <= _T_584 & _T_67; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + _T_580 <= 1'h0; + end else begin + _T_580 <= _T_576 & _T_56; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + _T_572 <= 1'h0; + end else begin + _T_572 <= _T_568 & _T_45; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + _T_564 <= 1'h0; + end else begin + _T_564 <= _T_560 & _T_34; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + _T_623 <= 1'h0; + end else begin + _T_623 <= _T_619 & _T_67; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + _T_615 <= 1'h0; + end else begin + _T_615 <= _T_611 & _T_56; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + _T_607 <= 1'h0; + end else begin + _T_607 <= _T_603 & _T_45; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + _T_599 <= 1'h0; + end else begin + _T_599 <= _T_595 & _T_34; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + stbuf_addr_1 <= 16'h0; + end else if (sel_lo[1]) begin + stbuf_addr_1 <= io_lsu_addr_r[15:0]; + end else begin + stbuf_addr_1 <= io_end_addr_r[15:0]; + end + end + always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + if (reset) begin + stbuf_addr_2 <= 16'h0; + end else if (sel_lo[2]) begin + stbuf_addr_2 <= io_lsu_addr_r[15:0]; + end else begin + stbuf_addr_2 <= io_end_addr_r[15:0]; + end + end + always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin + if (reset) begin + stbuf_addr_3 <= 16'h0; + end else if (sel_lo[3]) begin + stbuf_addr_3 <= io_lsu_addr_r[15:0]; + end else begin + stbuf_addr_3 <= io_end_addr_r[15:0]; + end + end + always @(posedge io_lsu_stbuf_c1_clk or posedge reset) begin + if (reset) begin + stbuf_byteen_0 <= 4'h0; + end else begin + stbuf_byteen_0 <= _T_629 & _T_633; + end + end + always @(posedge io_lsu_stbuf_c1_clk or posedge reset) begin + if (reset) begin + stbuf_byteen_1 <= 4'h0; + end else begin + stbuf_byteen_1 <= _T_638 & _T_642; + end + end + always @(posedge io_lsu_stbuf_c1_clk or posedge reset) begin + if (reset) begin + stbuf_byteen_2 <= 4'h0; + end else begin + stbuf_byteen_2 <= _T_647 & _T_651; + end + end + always @(posedge io_lsu_stbuf_c1_clk or posedge reset) begin + if (reset) begin + stbuf_byteen_3 <= 4'h0; + end else begin + stbuf_byteen_3 <= _T_656 & _T_660; + end + end + always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin + if (reset) begin + stbuf_data_0 <= 32'h0; + end else begin + stbuf_data_0 <= {_T_546,_T_545}; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + stbuf_data_1 <= 32'h0; + end else begin + stbuf_data_1 <= {_T_549,_T_548}; + end + end + always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + if (reset) begin + stbuf_data_2 <= 32'h0; + end else begin + stbuf_data_2 <= {_T_552,_T_551}; + end + end + always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin + if (reset) begin + stbuf_data_3 <= 32'h0; + end else begin + stbuf_data_3 <= {_T_555,_T_554}; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + ldst_dual_m <= 1'h0; + end else begin + ldst_dual_m <= io_lsu_addr_d[2] != io_end_addr_d[2]; + end + end +endmodule +module lsu_ecc( + input clock, + input reset, + input io_lsu_c2_r_clk, + input io_lsu_pkt_m_valid, + input io_lsu_pkt_m_bits_load, + input io_lsu_pkt_m_bits_store, + input io_lsu_pkt_m_bits_dma, + input [31:0] io_stbuf_data_any, + input io_dec_tlu_core_ecc_disable, + input [15:0] io_lsu_addr_m, + input [15:0] io_end_addr_m, + input [31:0] io_dccm_rdata_hi_m, + input [31:0] io_dccm_rdata_lo_m, + input [6:0] io_dccm_data_ecc_hi_m, + input [6:0] io_dccm_data_ecc_lo_m, + input io_ld_single_ecc_error_r, + input io_ld_single_ecc_error_r_ff, + input io_lsu_dccm_rden_m, + input io_addr_in_dccm_m, + input io_dma_dccm_wen, + input [31:0] io_dma_dccm_wdata_lo, + input [31:0] io_dma_dccm_wdata_hi, + input io_scan_mode, + output [31:0] io_sec_data_hi_r, + output [31:0] io_sec_data_lo_r, + output [31:0] io_sec_data_hi_m, + output [31:0] io_sec_data_lo_m, + output [31:0] io_sec_data_hi_r_ff, + output [31:0] io_sec_data_lo_r_ff, + output [6:0] io_dma_dccm_wdata_ecc_hi, + output [6:0] io_dma_dccm_wdata_ecc_lo, + output [6:0] io_stbuf_ecc_any, + output [6:0] io_sec_data_ecc_hi_r_ff, + output [6:0] io_sec_data_ecc_lo_r_ff, + output io_single_ecc_error_hi_r, + output io_single_ecc_error_lo_r, + output io_lsu_single_ecc_error_r, + output io_lsu_double_ecc_error_r, + output io_lsu_single_ecc_error_m, + output io_lsu_double_ecc_error_m +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_io_en; // @[lib.scala 368:23] + wire rvclkhdr_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_1_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_1_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_1_io_en; // @[lib.scala 368:23] + wire rvclkhdr_1_io_scan_mode; // @[lib.scala 368:23] + wire _T_96 = ^io_dccm_rdata_hi_m; // @[lib.scala 193:30] + wire _T_97 = ^io_dccm_data_ecc_hi_m; // @[lib.scala 193:44] + wire _T_98 = _T_96 ^ _T_97; // @[lib.scala 193:35] + wire [5:0] _T_106 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[29],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[27],io_dccm_rdata_hi_m[26]}; // @[lib.scala 193:76] + wire _T_107 = ^_T_106; // @[lib.scala 193:83] + wire _T_108 = io_dccm_data_ecc_hi_m[5] ^ _T_107; // @[lib.scala 193:71] + wire [6:0] _T_115 = {io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],io_dccm_rdata_hi_m[15],io_dccm_rdata_hi_m[14],io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[12],io_dccm_rdata_hi_m[11]}; // @[lib.scala 193:103] + wire [14:0] _T_123 = {io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[18],_T_115}; // @[lib.scala 193:103] + wire _T_124 = ^_T_123; // @[lib.scala 193:110] + wire _T_125 = io_dccm_data_ecc_hi_m[4] ^ _T_124; // @[lib.scala 193:98] + wire [6:0] _T_132 = {io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[7],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[5],io_dccm_rdata_hi_m[4]}; // @[lib.scala 193:130] + wire [14:0] _T_140 = {io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[18],_T_132}; // @[lib.scala 193:130] + wire _T_141 = ^_T_140; // @[lib.scala 193:137] + wire _T_142 = io_dccm_data_ecc_hi_m[3] ^ _T_141; // @[lib.scala 193:125] + wire [8:0] _T_151 = {io_dccm_rdata_hi_m[15],io_dccm_rdata_hi_m[14],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[7],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[2],io_dccm_rdata_hi_m[1]}; // @[lib.scala 193:157] + wire [17:0] _T_160 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[29],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],_T_151}; // @[lib.scala 193:157] + wire _T_161 = ^_T_160; // @[lib.scala 193:164] + wire _T_162 = io_dccm_data_ecc_hi_m[2] ^ _T_161; // @[lib.scala 193:152] + wire [8:0] _T_171 = {io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[12],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[5],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[2],io_dccm_rdata_hi_m[0]}; // @[lib.scala 193:184] + wire [17:0] _T_180 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[27],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],_T_171}; // @[lib.scala 193:184] + wire _T_181 = ^_T_180; // @[lib.scala 193:191] + wire _T_182 = io_dccm_data_ecc_hi_m[1] ^ _T_181; // @[lib.scala 193:179] + wire [8:0] _T_191 = {io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[11],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[4],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[1],io_dccm_rdata_hi_m[0]}; // @[lib.scala 193:211] + wire [17:0] _T_200 = {io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[26],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[15],_T_191}; // @[lib.scala 193:211] + wire _T_201 = ^_T_200; // @[lib.scala 193:218] + wire _T_202 = io_dccm_data_ecc_hi_m[0] ^ _T_201; // @[lib.scala 193:206] + wire [6:0] _T_208 = {_T_98,_T_108,_T_125,_T_142,_T_162,_T_182,_T_202}; // @[Cat.scala 29:58] + wire _T_209 = _T_208 != 7'h0; // @[lib.scala 194:44] + wire _T_1131 = ~io_dec_tlu_core_ecc_disable; // @[lsu_ecc.scala 107:73] + wire _T_1138 = io_lsu_pkt_m_bits_load | io_lsu_pkt_m_bits_store; // @[lsu_ecc.scala 125:65] + wire _T_1139 = io_lsu_pkt_m_valid & _T_1138; // @[lsu_ecc.scala 125:39] + wire _T_1140 = _T_1139 & io_addr_in_dccm_m; // @[lsu_ecc.scala 125:92] + wire is_ldst_m = _T_1140 & io_lsu_dccm_rden_m; // @[lsu_ecc.scala 125:112] + wire ldst_dual_m = io_lsu_addr_m[2] != io_end_addr_m[2]; // @[lsu_ecc.scala 124:39] + wire _T_1144 = ldst_dual_m | io_lsu_pkt_m_bits_dma; // @[lsu_ecc.scala 127:48] + wire _T_1145 = is_ldst_m & _T_1144; // @[lsu_ecc.scala 127:33] + wire is_ldst_hi_m = _T_1145 & _T_1131; // @[lsu_ecc.scala 127:73] + wire _T_210 = is_ldst_hi_m & _T_209; // @[lib.scala 194:32] + wire single_ecc_error_hi_any = _T_210 & _T_208[6]; // @[lib.scala 194:53] + wire _T_215 = ~_T_208[6]; // @[lib.scala 195:55] + wire double_ecc_error_hi_any = _T_210 & _T_215; // @[lib.scala 195:53] + wire _T_218 = _T_208[5:0] == 6'h1; // @[lib.scala 199:41] + wire _T_220 = _T_208[5:0] == 6'h2; // @[lib.scala 199:41] + wire _T_222 = _T_208[5:0] == 6'h3; // @[lib.scala 199:41] + wire _T_224 = _T_208[5:0] == 6'h4; // @[lib.scala 199:41] + wire _T_226 = _T_208[5:0] == 6'h5; // @[lib.scala 199:41] + wire _T_228 = _T_208[5:0] == 6'h6; // @[lib.scala 199:41] + wire _T_230 = _T_208[5:0] == 6'h7; // @[lib.scala 199:41] + wire _T_232 = _T_208[5:0] == 6'h8; // @[lib.scala 199:41] + wire _T_234 = _T_208[5:0] == 6'h9; // @[lib.scala 199:41] + wire _T_236 = _T_208[5:0] == 6'ha; // @[lib.scala 199:41] + wire _T_238 = _T_208[5:0] == 6'hb; // @[lib.scala 199:41] + wire _T_240 = _T_208[5:0] == 6'hc; // @[lib.scala 199:41] + wire _T_242 = _T_208[5:0] == 6'hd; // @[lib.scala 199:41] + wire _T_244 = _T_208[5:0] == 6'he; // @[lib.scala 199:41] + wire _T_246 = _T_208[5:0] == 6'hf; // @[lib.scala 199:41] + wire _T_248 = _T_208[5:0] == 6'h10; // @[lib.scala 199:41] + wire _T_250 = _T_208[5:0] == 6'h11; // @[lib.scala 199:41] + wire _T_252 = _T_208[5:0] == 6'h12; // @[lib.scala 199:41] + wire _T_254 = _T_208[5:0] == 6'h13; // @[lib.scala 199:41] + wire _T_256 = _T_208[5:0] == 6'h14; // @[lib.scala 199:41] + wire _T_258 = _T_208[5:0] == 6'h15; // @[lib.scala 199:41] + wire _T_260 = _T_208[5:0] == 6'h16; // @[lib.scala 199:41] + wire _T_262 = _T_208[5:0] == 6'h17; // @[lib.scala 199:41] + wire _T_264 = _T_208[5:0] == 6'h18; // @[lib.scala 199:41] + wire _T_266 = _T_208[5:0] == 6'h19; // @[lib.scala 199:41] + wire _T_268 = _T_208[5:0] == 6'h1a; // @[lib.scala 199:41] + wire _T_270 = _T_208[5:0] == 6'h1b; // @[lib.scala 199:41] + wire _T_272 = _T_208[5:0] == 6'h1c; // @[lib.scala 199:41] + wire _T_274 = _T_208[5:0] == 6'h1d; // @[lib.scala 199:41] + wire _T_276 = _T_208[5:0] == 6'h1e; // @[lib.scala 199:41] + wire _T_278 = _T_208[5:0] == 6'h1f; // @[lib.scala 199:41] + wire _T_280 = _T_208[5:0] == 6'h20; // @[lib.scala 199:41] + wire _T_282 = _T_208[5:0] == 6'h21; // @[lib.scala 199:41] + wire _T_284 = _T_208[5:0] == 6'h22; // @[lib.scala 199:41] + wire _T_286 = _T_208[5:0] == 6'h23; // @[lib.scala 199:41] + wire _T_288 = _T_208[5:0] == 6'h24; // @[lib.scala 199:41] + wire _T_290 = _T_208[5:0] == 6'h25; // @[lib.scala 199:41] + wire _T_292 = _T_208[5:0] == 6'h26; // @[lib.scala 199:41] + wire _T_294 = _T_208[5:0] == 6'h27; // @[lib.scala 199:41] + wire [7:0] _T_309 = {io_dccm_data_ecc_hi_m[3],io_dccm_rdata_hi_m[3:1],io_dccm_data_ecc_hi_m[2],io_dccm_rdata_hi_m[0],io_dccm_data_ecc_hi_m[1:0]}; // @[Cat.scala 29:58] + wire [38:0] _T_315 = {io_dccm_data_ecc_hi_m[6],io_dccm_rdata_hi_m[31:26],io_dccm_data_ecc_hi_m[5],io_dccm_rdata_hi_m[25:11],io_dccm_data_ecc_hi_m[4],io_dccm_rdata_hi_m[10:4],_T_309}; // @[Cat.scala 29:58] + wire [9:0] _T_333 = {_T_254,_T_252,_T_250,_T_248,_T_246,_T_244,_T_242,_T_240,_T_238,_T_236}; // @[lib.scala 202:69] + wire [18:0] _T_334 = {_T_333,_T_234,_T_232,_T_230,_T_228,_T_226,_T_224,_T_222,_T_220,_T_218}; // @[lib.scala 202:69] + wire [9:0] _T_343 = {_T_274,_T_272,_T_270,_T_268,_T_266,_T_264,_T_262,_T_260,_T_258,_T_256}; // @[lib.scala 202:69] + wire [9:0] _T_352 = {_T_294,_T_292,_T_290,_T_288,_T_286,_T_284,_T_282,_T_280,_T_278,_T_276}; // @[lib.scala 202:69] + wire [38:0] _T_354 = {_T_352,_T_343,_T_334}; // @[lib.scala 202:69] + wire [38:0] _T_355 = _T_354 ^ _T_315; // @[lib.scala 202:76] + wire [38:0] _T_356 = single_ecc_error_hi_any ? _T_355 : _T_315; // @[lib.scala 202:31] + wire [3:0] _T_362 = {_T_356[6:4],_T_356[2]}; // @[Cat.scala 29:58] + wire [27:0] _T_364 = {_T_356[37:32],_T_356[30:16],_T_356[14:8]}; // @[Cat.scala 29:58] + wire _T_474 = ^io_dccm_rdata_lo_m; // @[lib.scala 193:30] + wire _T_475 = ^io_dccm_data_ecc_lo_m; // @[lib.scala 193:44] + wire _T_476 = _T_474 ^ _T_475; // @[lib.scala 193:35] + wire [5:0] _T_484 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[29],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[27],io_dccm_rdata_lo_m[26]}; // @[lib.scala 193:76] + wire _T_485 = ^_T_484; // @[lib.scala 193:83] + wire _T_486 = io_dccm_data_ecc_lo_m[5] ^ _T_485; // @[lib.scala 193:71] + wire [6:0] _T_493 = {io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],io_dccm_rdata_lo_m[15],io_dccm_rdata_lo_m[14],io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[12],io_dccm_rdata_lo_m[11]}; // @[lib.scala 193:103] + wire [14:0] _T_501 = {io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[18],_T_493}; // @[lib.scala 193:103] + wire _T_502 = ^_T_501; // @[lib.scala 193:110] + wire _T_503 = io_dccm_data_ecc_lo_m[4] ^ _T_502; // @[lib.scala 193:98] + wire [6:0] _T_510 = {io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[7],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[5],io_dccm_rdata_lo_m[4]}; // @[lib.scala 193:130] + wire [14:0] _T_518 = {io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[18],_T_510}; // @[lib.scala 193:130] + wire _T_519 = ^_T_518; // @[lib.scala 193:137] + wire _T_520 = io_dccm_data_ecc_lo_m[3] ^ _T_519; // @[lib.scala 193:125] + wire [8:0] _T_529 = {io_dccm_rdata_lo_m[15],io_dccm_rdata_lo_m[14],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[7],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[2],io_dccm_rdata_lo_m[1]}; // @[lib.scala 193:157] + wire [17:0] _T_538 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[29],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],_T_529}; // @[lib.scala 193:157] + wire _T_539 = ^_T_538; // @[lib.scala 193:164] + wire _T_540 = io_dccm_data_ecc_lo_m[2] ^ _T_539; // @[lib.scala 193:152] + wire [8:0] _T_549 = {io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[12],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[5],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[2],io_dccm_rdata_lo_m[0]}; // @[lib.scala 193:184] + wire [17:0] _T_558 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[27],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],_T_549}; // @[lib.scala 193:184] + wire _T_559 = ^_T_558; // @[lib.scala 193:191] + wire _T_560 = io_dccm_data_ecc_lo_m[1] ^ _T_559; // @[lib.scala 193:179] + wire [8:0] _T_569 = {io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[11],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[4],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[1],io_dccm_rdata_lo_m[0]}; // @[lib.scala 193:211] + wire [17:0] _T_578 = {io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[26],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[15],_T_569}; // @[lib.scala 193:211] + wire _T_579 = ^_T_578; // @[lib.scala 193:218] + wire _T_580 = io_dccm_data_ecc_lo_m[0] ^ _T_579; // @[lib.scala 193:206] + wire [6:0] _T_586 = {_T_476,_T_486,_T_503,_T_520,_T_540,_T_560,_T_580}; // @[Cat.scala 29:58] + wire _T_587 = _T_586 != 7'h0; // @[lib.scala 194:44] + wire is_ldst_lo_m = is_ldst_m & _T_1131; // @[lsu_ecc.scala 126:33] + wire _T_588 = is_ldst_lo_m & _T_587; // @[lib.scala 194:32] + wire single_ecc_error_lo_any = _T_588 & _T_586[6]; // @[lib.scala 194:53] + wire _T_593 = ~_T_586[6]; // @[lib.scala 195:55] + wire double_ecc_error_lo_any = _T_588 & _T_593; // @[lib.scala 195:53] + wire _T_596 = _T_586[5:0] == 6'h1; // @[lib.scala 199:41] + wire _T_598 = _T_586[5:0] == 6'h2; // @[lib.scala 199:41] + wire _T_600 = _T_586[5:0] == 6'h3; // @[lib.scala 199:41] + wire _T_602 = _T_586[5:0] == 6'h4; // @[lib.scala 199:41] + wire _T_604 = _T_586[5:0] == 6'h5; // @[lib.scala 199:41] + wire _T_606 = _T_586[5:0] == 6'h6; // @[lib.scala 199:41] + wire _T_608 = _T_586[5:0] == 6'h7; // @[lib.scala 199:41] + wire _T_610 = _T_586[5:0] == 6'h8; // @[lib.scala 199:41] + wire _T_612 = _T_586[5:0] == 6'h9; // @[lib.scala 199:41] + wire _T_614 = _T_586[5:0] == 6'ha; // @[lib.scala 199:41] + wire _T_616 = _T_586[5:0] == 6'hb; // @[lib.scala 199:41] + wire _T_618 = _T_586[5:0] == 6'hc; // @[lib.scala 199:41] + wire _T_620 = _T_586[5:0] == 6'hd; // @[lib.scala 199:41] + wire _T_622 = _T_586[5:0] == 6'he; // @[lib.scala 199:41] + wire _T_624 = _T_586[5:0] == 6'hf; // @[lib.scala 199:41] + wire _T_626 = _T_586[5:0] == 6'h10; // @[lib.scala 199:41] + wire _T_628 = _T_586[5:0] == 6'h11; // @[lib.scala 199:41] + wire _T_630 = _T_586[5:0] == 6'h12; // @[lib.scala 199:41] + wire _T_632 = _T_586[5:0] == 6'h13; // @[lib.scala 199:41] + wire _T_634 = _T_586[5:0] == 6'h14; // @[lib.scala 199:41] + wire _T_636 = _T_586[5:0] == 6'h15; // @[lib.scala 199:41] + wire _T_638 = _T_586[5:0] == 6'h16; // @[lib.scala 199:41] + wire _T_640 = _T_586[5:0] == 6'h17; // @[lib.scala 199:41] + wire _T_642 = _T_586[5:0] == 6'h18; // @[lib.scala 199:41] + wire _T_644 = _T_586[5:0] == 6'h19; // @[lib.scala 199:41] + wire _T_646 = _T_586[5:0] == 6'h1a; // @[lib.scala 199:41] + wire _T_648 = _T_586[5:0] == 6'h1b; // @[lib.scala 199:41] + wire _T_650 = _T_586[5:0] == 6'h1c; // @[lib.scala 199:41] + wire _T_652 = _T_586[5:0] == 6'h1d; // @[lib.scala 199:41] + wire _T_654 = _T_586[5:0] == 6'h1e; // @[lib.scala 199:41] + wire _T_656 = _T_586[5:0] == 6'h1f; // @[lib.scala 199:41] + wire _T_658 = _T_586[5:0] == 6'h20; // @[lib.scala 199:41] + wire _T_660 = _T_586[5:0] == 6'h21; // @[lib.scala 199:41] + wire _T_662 = _T_586[5:0] == 6'h22; // @[lib.scala 199:41] + wire _T_664 = _T_586[5:0] == 6'h23; // @[lib.scala 199:41] + wire _T_666 = _T_586[5:0] == 6'h24; // @[lib.scala 199:41] + wire _T_668 = _T_586[5:0] == 6'h25; // @[lib.scala 199:41] + wire _T_670 = _T_586[5:0] == 6'h26; // @[lib.scala 199:41] + wire _T_672 = _T_586[5:0] == 6'h27; // @[lib.scala 199:41] + wire [7:0] _T_687 = {io_dccm_data_ecc_lo_m[3],io_dccm_rdata_lo_m[3:1],io_dccm_data_ecc_lo_m[2],io_dccm_rdata_lo_m[0],io_dccm_data_ecc_lo_m[1:0]}; // @[Cat.scala 29:58] + wire [38:0] _T_693 = {io_dccm_data_ecc_lo_m[6],io_dccm_rdata_lo_m[31:26],io_dccm_data_ecc_lo_m[5],io_dccm_rdata_lo_m[25:11],io_dccm_data_ecc_lo_m[4],io_dccm_rdata_lo_m[10:4],_T_687}; // @[Cat.scala 29:58] + wire [9:0] _T_711 = {_T_632,_T_630,_T_628,_T_626,_T_624,_T_622,_T_620,_T_618,_T_616,_T_614}; // @[lib.scala 202:69] + wire [18:0] _T_712 = {_T_711,_T_612,_T_610,_T_608,_T_606,_T_604,_T_602,_T_600,_T_598,_T_596}; // @[lib.scala 202:69] + wire [9:0] _T_721 = {_T_652,_T_650,_T_648,_T_646,_T_644,_T_642,_T_640,_T_638,_T_636,_T_634}; // @[lib.scala 202:69] + wire [9:0] _T_730 = {_T_672,_T_670,_T_668,_T_666,_T_664,_T_662,_T_660,_T_658,_T_656,_T_654}; // @[lib.scala 202:69] + wire [38:0] _T_732 = {_T_730,_T_721,_T_712}; // @[lib.scala 202:69] + wire [38:0] _T_733 = _T_732 ^ _T_693; // @[lib.scala 202:76] + wire [38:0] _T_734 = single_ecc_error_lo_any ? _T_733 : _T_693; // @[lib.scala 202:31] + wire [3:0] _T_740 = {_T_734[6:4],_T_734[2]}; // @[Cat.scala 29:58] + wire [27:0] _T_742 = {_T_734[37:32],_T_734[30:16],_T_734[14:8]}; // @[Cat.scala 29:58] + wire [31:0] _T_1158 = io_dma_dccm_wen ? io_dma_dccm_wdata_lo : io_stbuf_data_any; // @[lsu_ecc.scala 149:87] + wire [31:0] dccm_wdata_lo_any = io_ld_single_ecc_error_r_ff ? io_sec_data_lo_r_ff : _T_1158; // @[lsu_ecc.scala 149:27] + wire _T_774 = dccm_wdata_lo_any[0] ^ dccm_wdata_lo_any[1]; // @[lib.scala 119:74] + wire _T_775 = _T_774 ^ dccm_wdata_lo_any[3]; // @[lib.scala 119:74] + wire _T_776 = _T_775 ^ dccm_wdata_lo_any[4]; // @[lib.scala 119:74] + wire _T_777 = _T_776 ^ dccm_wdata_lo_any[6]; // @[lib.scala 119:74] + wire _T_778 = _T_777 ^ dccm_wdata_lo_any[8]; // @[lib.scala 119:74] + wire _T_779 = _T_778 ^ dccm_wdata_lo_any[10]; // @[lib.scala 119:74] + wire _T_780 = _T_779 ^ dccm_wdata_lo_any[11]; // @[lib.scala 119:74] + wire _T_781 = _T_780 ^ dccm_wdata_lo_any[13]; // @[lib.scala 119:74] + wire _T_782 = _T_781 ^ dccm_wdata_lo_any[15]; // @[lib.scala 119:74] + wire _T_783 = _T_782 ^ dccm_wdata_lo_any[17]; // @[lib.scala 119:74] + wire _T_784 = _T_783 ^ dccm_wdata_lo_any[19]; // @[lib.scala 119:74] + wire _T_785 = _T_784 ^ dccm_wdata_lo_any[21]; // @[lib.scala 119:74] + wire _T_786 = _T_785 ^ dccm_wdata_lo_any[23]; // @[lib.scala 119:74] + wire _T_787 = _T_786 ^ dccm_wdata_lo_any[25]; // @[lib.scala 119:74] + wire _T_788 = _T_787 ^ dccm_wdata_lo_any[26]; // @[lib.scala 119:74] + wire _T_789 = _T_788 ^ dccm_wdata_lo_any[28]; // @[lib.scala 119:74] + wire _T_790 = _T_789 ^ dccm_wdata_lo_any[30]; // @[lib.scala 119:74] + wire _T_809 = dccm_wdata_lo_any[0] ^ dccm_wdata_lo_any[2]; // @[lib.scala 119:74] + wire _T_810 = _T_809 ^ dccm_wdata_lo_any[3]; // @[lib.scala 119:74] + wire _T_811 = _T_810 ^ dccm_wdata_lo_any[5]; // @[lib.scala 119:74] + wire _T_812 = _T_811 ^ dccm_wdata_lo_any[6]; // @[lib.scala 119:74] + wire _T_813 = _T_812 ^ dccm_wdata_lo_any[9]; // @[lib.scala 119:74] + wire _T_814 = _T_813 ^ dccm_wdata_lo_any[10]; // @[lib.scala 119:74] + wire _T_815 = _T_814 ^ dccm_wdata_lo_any[12]; // @[lib.scala 119:74] + wire _T_816 = _T_815 ^ dccm_wdata_lo_any[13]; // @[lib.scala 119:74] + wire _T_817 = _T_816 ^ dccm_wdata_lo_any[16]; // @[lib.scala 119:74] + wire _T_818 = _T_817 ^ dccm_wdata_lo_any[17]; // @[lib.scala 119:74] + wire _T_819 = _T_818 ^ dccm_wdata_lo_any[20]; // @[lib.scala 119:74] + wire _T_820 = _T_819 ^ dccm_wdata_lo_any[21]; // @[lib.scala 119:74] + wire _T_821 = _T_820 ^ dccm_wdata_lo_any[24]; // @[lib.scala 119:74] + wire _T_822 = _T_821 ^ dccm_wdata_lo_any[25]; // @[lib.scala 119:74] + wire _T_823 = _T_822 ^ dccm_wdata_lo_any[27]; // @[lib.scala 119:74] + wire _T_824 = _T_823 ^ dccm_wdata_lo_any[28]; // @[lib.scala 119:74] + wire _T_825 = _T_824 ^ dccm_wdata_lo_any[31]; // @[lib.scala 119:74] + wire _T_844 = dccm_wdata_lo_any[1] ^ dccm_wdata_lo_any[2]; // @[lib.scala 119:74] + wire _T_845 = _T_844 ^ dccm_wdata_lo_any[3]; // @[lib.scala 119:74] + wire _T_846 = _T_845 ^ dccm_wdata_lo_any[7]; // @[lib.scala 119:74] + wire _T_847 = _T_846 ^ dccm_wdata_lo_any[8]; // @[lib.scala 119:74] + wire _T_848 = _T_847 ^ dccm_wdata_lo_any[9]; // @[lib.scala 119:74] + wire _T_849 = _T_848 ^ dccm_wdata_lo_any[10]; // @[lib.scala 119:74] + wire _T_850 = _T_849 ^ dccm_wdata_lo_any[14]; // @[lib.scala 119:74] + wire _T_851 = _T_850 ^ dccm_wdata_lo_any[15]; // @[lib.scala 119:74] + wire _T_852 = _T_851 ^ dccm_wdata_lo_any[16]; // @[lib.scala 119:74] + wire _T_853 = _T_852 ^ dccm_wdata_lo_any[17]; // @[lib.scala 119:74] + wire _T_854 = _T_853 ^ dccm_wdata_lo_any[22]; // @[lib.scala 119:74] + wire _T_855 = _T_854 ^ dccm_wdata_lo_any[23]; // @[lib.scala 119:74] + wire _T_856 = _T_855 ^ dccm_wdata_lo_any[24]; // @[lib.scala 119:74] + wire _T_857 = _T_856 ^ dccm_wdata_lo_any[25]; // @[lib.scala 119:74] + wire _T_858 = _T_857 ^ dccm_wdata_lo_any[29]; // @[lib.scala 119:74] + wire _T_859 = _T_858 ^ dccm_wdata_lo_any[30]; // @[lib.scala 119:74] + wire _T_860 = _T_859 ^ dccm_wdata_lo_any[31]; // @[lib.scala 119:74] + wire _T_876 = dccm_wdata_lo_any[4] ^ dccm_wdata_lo_any[5]; // @[lib.scala 119:74] + wire _T_877 = _T_876 ^ dccm_wdata_lo_any[6]; // @[lib.scala 119:74] + wire _T_878 = _T_877 ^ dccm_wdata_lo_any[7]; // @[lib.scala 119:74] + wire _T_879 = _T_878 ^ dccm_wdata_lo_any[8]; // @[lib.scala 119:74] + wire _T_880 = _T_879 ^ dccm_wdata_lo_any[9]; // @[lib.scala 119:74] + wire _T_881 = _T_880 ^ dccm_wdata_lo_any[10]; // @[lib.scala 119:74] + wire _T_882 = _T_881 ^ dccm_wdata_lo_any[18]; // @[lib.scala 119:74] + wire _T_883 = _T_882 ^ dccm_wdata_lo_any[19]; // @[lib.scala 119:74] + wire _T_884 = _T_883 ^ dccm_wdata_lo_any[20]; // @[lib.scala 119:74] + wire _T_885 = _T_884 ^ dccm_wdata_lo_any[21]; // @[lib.scala 119:74] + wire _T_886 = _T_885 ^ dccm_wdata_lo_any[22]; // @[lib.scala 119:74] + wire _T_887 = _T_886 ^ dccm_wdata_lo_any[23]; // @[lib.scala 119:74] + wire _T_888 = _T_887 ^ dccm_wdata_lo_any[24]; // @[lib.scala 119:74] + wire _T_889 = _T_888 ^ dccm_wdata_lo_any[25]; // @[lib.scala 119:74] + wire _T_905 = dccm_wdata_lo_any[11] ^ dccm_wdata_lo_any[12]; // @[lib.scala 119:74] + wire _T_906 = _T_905 ^ dccm_wdata_lo_any[13]; // @[lib.scala 119:74] + wire _T_907 = _T_906 ^ dccm_wdata_lo_any[14]; // @[lib.scala 119:74] + wire _T_908 = _T_907 ^ dccm_wdata_lo_any[15]; // @[lib.scala 119:74] + wire _T_909 = _T_908 ^ dccm_wdata_lo_any[16]; // @[lib.scala 119:74] + wire _T_910 = _T_909 ^ dccm_wdata_lo_any[17]; // @[lib.scala 119:74] + wire _T_911 = _T_910 ^ dccm_wdata_lo_any[18]; // @[lib.scala 119:74] + wire _T_912 = _T_911 ^ dccm_wdata_lo_any[19]; // @[lib.scala 119:74] + wire _T_913 = _T_912 ^ dccm_wdata_lo_any[20]; // @[lib.scala 119:74] + wire _T_914 = _T_913 ^ dccm_wdata_lo_any[21]; // @[lib.scala 119:74] + wire _T_915 = _T_914 ^ dccm_wdata_lo_any[22]; // @[lib.scala 119:74] + wire _T_916 = _T_915 ^ dccm_wdata_lo_any[23]; // @[lib.scala 119:74] + wire _T_917 = _T_916 ^ dccm_wdata_lo_any[24]; // @[lib.scala 119:74] + wire _T_918 = _T_917 ^ dccm_wdata_lo_any[25]; // @[lib.scala 119:74] + wire _T_925 = dccm_wdata_lo_any[26] ^ dccm_wdata_lo_any[27]; // @[lib.scala 119:74] + wire _T_926 = _T_925 ^ dccm_wdata_lo_any[28]; // @[lib.scala 119:74] + wire _T_927 = _T_926 ^ dccm_wdata_lo_any[29]; // @[lib.scala 119:74] + wire _T_928 = _T_927 ^ dccm_wdata_lo_any[30]; // @[lib.scala 119:74] + wire _T_929 = _T_928 ^ dccm_wdata_lo_any[31]; // @[lib.scala 119:74] + wire [5:0] _T_934 = {_T_929,_T_918,_T_889,_T_860,_T_825,_T_790}; // @[Cat.scala 29:58] + wire _T_935 = ^dccm_wdata_lo_any; // @[lib.scala 127:13] + wire _T_936 = ^_T_934; // @[lib.scala 127:23] + wire _T_937 = _T_935 ^ _T_936; // @[lib.scala 127:18] + wire [31:0] _T_1162 = io_dma_dccm_wen ? io_dma_dccm_wdata_hi : io_stbuf_data_any; // @[lsu_ecc.scala 150:87] + wire [31:0] dccm_wdata_hi_any = io_ld_single_ecc_error_r_ff ? io_sec_data_hi_r_ff : _T_1162; // @[lsu_ecc.scala 150:27] + wire _T_956 = dccm_wdata_hi_any[0] ^ dccm_wdata_hi_any[1]; // @[lib.scala 119:74] + wire _T_957 = _T_956 ^ dccm_wdata_hi_any[3]; // @[lib.scala 119:74] + wire _T_958 = _T_957 ^ dccm_wdata_hi_any[4]; // @[lib.scala 119:74] + wire _T_959 = _T_958 ^ dccm_wdata_hi_any[6]; // @[lib.scala 119:74] + wire _T_960 = _T_959 ^ dccm_wdata_hi_any[8]; // @[lib.scala 119:74] + wire _T_961 = _T_960 ^ dccm_wdata_hi_any[10]; // @[lib.scala 119:74] + wire _T_962 = _T_961 ^ dccm_wdata_hi_any[11]; // @[lib.scala 119:74] + wire _T_963 = _T_962 ^ dccm_wdata_hi_any[13]; // @[lib.scala 119:74] + wire _T_964 = _T_963 ^ dccm_wdata_hi_any[15]; // @[lib.scala 119:74] + wire _T_965 = _T_964 ^ dccm_wdata_hi_any[17]; // @[lib.scala 119:74] + wire _T_966 = _T_965 ^ dccm_wdata_hi_any[19]; // @[lib.scala 119:74] + wire _T_967 = _T_966 ^ dccm_wdata_hi_any[21]; // @[lib.scala 119:74] + wire _T_968 = _T_967 ^ dccm_wdata_hi_any[23]; // @[lib.scala 119:74] + wire _T_969 = _T_968 ^ dccm_wdata_hi_any[25]; // @[lib.scala 119:74] + wire _T_970 = _T_969 ^ dccm_wdata_hi_any[26]; // @[lib.scala 119:74] + wire _T_971 = _T_970 ^ dccm_wdata_hi_any[28]; // @[lib.scala 119:74] + wire _T_972 = _T_971 ^ dccm_wdata_hi_any[30]; // @[lib.scala 119:74] + wire _T_991 = dccm_wdata_hi_any[0] ^ dccm_wdata_hi_any[2]; // @[lib.scala 119:74] + wire _T_992 = _T_991 ^ dccm_wdata_hi_any[3]; // @[lib.scala 119:74] + wire _T_993 = _T_992 ^ dccm_wdata_hi_any[5]; // @[lib.scala 119:74] + wire _T_994 = _T_993 ^ dccm_wdata_hi_any[6]; // @[lib.scala 119:74] + wire _T_995 = _T_994 ^ dccm_wdata_hi_any[9]; // @[lib.scala 119:74] + wire _T_996 = _T_995 ^ dccm_wdata_hi_any[10]; // @[lib.scala 119:74] + wire _T_997 = _T_996 ^ dccm_wdata_hi_any[12]; // @[lib.scala 119:74] + wire _T_998 = _T_997 ^ dccm_wdata_hi_any[13]; // @[lib.scala 119:74] + wire _T_999 = _T_998 ^ dccm_wdata_hi_any[16]; // @[lib.scala 119:74] + wire _T_1000 = _T_999 ^ dccm_wdata_hi_any[17]; // @[lib.scala 119:74] + wire _T_1001 = _T_1000 ^ dccm_wdata_hi_any[20]; // @[lib.scala 119:74] + wire _T_1002 = _T_1001 ^ dccm_wdata_hi_any[21]; // @[lib.scala 119:74] + wire _T_1003 = _T_1002 ^ dccm_wdata_hi_any[24]; // @[lib.scala 119:74] + wire _T_1004 = _T_1003 ^ dccm_wdata_hi_any[25]; // @[lib.scala 119:74] + wire _T_1005 = _T_1004 ^ dccm_wdata_hi_any[27]; // @[lib.scala 119:74] + wire _T_1006 = _T_1005 ^ dccm_wdata_hi_any[28]; // @[lib.scala 119:74] + wire _T_1007 = _T_1006 ^ dccm_wdata_hi_any[31]; // @[lib.scala 119:74] + wire _T_1026 = dccm_wdata_hi_any[1] ^ dccm_wdata_hi_any[2]; // @[lib.scala 119:74] + wire _T_1027 = _T_1026 ^ dccm_wdata_hi_any[3]; // @[lib.scala 119:74] + wire _T_1028 = _T_1027 ^ dccm_wdata_hi_any[7]; // @[lib.scala 119:74] + wire _T_1029 = _T_1028 ^ dccm_wdata_hi_any[8]; // @[lib.scala 119:74] + wire _T_1030 = _T_1029 ^ dccm_wdata_hi_any[9]; // @[lib.scala 119:74] + wire _T_1031 = _T_1030 ^ dccm_wdata_hi_any[10]; // @[lib.scala 119:74] + wire _T_1032 = _T_1031 ^ dccm_wdata_hi_any[14]; // @[lib.scala 119:74] + wire _T_1033 = _T_1032 ^ dccm_wdata_hi_any[15]; // @[lib.scala 119:74] + wire _T_1034 = _T_1033 ^ dccm_wdata_hi_any[16]; // @[lib.scala 119:74] + wire _T_1035 = _T_1034 ^ dccm_wdata_hi_any[17]; // @[lib.scala 119:74] + wire _T_1036 = _T_1035 ^ dccm_wdata_hi_any[22]; // @[lib.scala 119:74] + wire _T_1037 = _T_1036 ^ dccm_wdata_hi_any[23]; // @[lib.scala 119:74] + wire _T_1038 = _T_1037 ^ dccm_wdata_hi_any[24]; // @[lib.scala 119:74] + wire _T_1039 = _T_1038 ^ dccm_wdata_hi_any[25]; // @[lib.scala 119:74] + wire _T_1040 = _T_1039 ^ dccm_wdata_hi_any[29]; // @[lib.scala 119:74] + wire _T_1041 = _T_1040 ^ dccm_wdata_hi_any[30]; // @[lib.scala 119:74] + wire _T_1042 = _T_1041 ^ dccm_wdata_hi_any[31]; // @[lib.scala 119:74] + wire _T_1058 = dccm_wdata_hi_any[4] ^ dccm_wdata_hi_any[5]; // @[lib.scala 119:74] + wire _T_1059 = _T_1058 ^ dccm_wdata_hi_any[6]; // @[lib.scala 119:74] + wire _T_1060 = _T_1059 ^ dccm_wdata_hi_any[7]; // @[lib.scala 119:74] + wire _T_1061 = _T_1060 ^ dccm_wdata_hi_any[8]; // @[lib.scala 119:74] + wire _T_1062 = _T_1061 ^ dccm_wdata_hi_any[9]; // @[lib.scala 119:74] + wire _T_1063 = _T_1062 ^ dccm_wdata_hi_any[10]; // @[lib.scala 119:74] + wire _T_1064 = _T_1063 ^ dccm_wdata_hi_any[18]; // @[lib.scala 119:74] + wire _T_1065 = _T_1064 ^ dccm_wdata_hi_any[19]; // @[lib.scala 119:74] + wire _T_1066 = _T_1065 ^ dccm_wdata_hi_any[20]; // @[lib.scala 119:74] + wire _T_1067 = _T_1066 ^ dccm_wdata_hi_any[21]; // @[lib.scala 119:74] + wire _T_1068 = _T_1067 ^ dccm_wdata_hi_any[22]; // @[lib.scala 119:74] + wire _T_1069 = _T_1068 ^ dccm_wdata_hi_any[23]; // @[lib.scala 119:74] + wire _T_1070 = _T_1069 ^ dccm_wdata_hi_any[24]; // @[lib.scala 119:74] + wire _T_1071 = _T_1070 ^ dccm_wdata_hi_any[25]; // @[lib.scala 119:74] + wire _T_1087 = dccm_wdata_hi_any[11] ^ dccm_wdata_hi_any[12]; // @[lib.scala 119:74] + wire _T_1088 = _T_1087 ^ dccm_wdata_hi_any[13]; // @[lib.scala 119:74] + wire _T_1089 = _T_1088 ^ dccm_wdata_hi_any[14]; // @[lib.scala 119:74] + wire _T_1090 = _T_1089 ^ dccm_wdata_hi_any[15]; // @[lib.scala 119:74] + wire _T_1091 = _T_1090 ^ dccm_wdata_hi_any[16]; // @[lib.scala 119:74] + wire _T_1092 = _T_1091 ^ dccm_wdata_hi_any[17]; // @[lib.scala 119:74] + wire _T_1093 = _T_1092 ^ dccm_wdata_hi_any[18]; // @[lib.scala 119:74] + wire _T_1094 = _T_1093 ^ dccm_wdata_hi_any[19]; // @[lib.scala 119:74] + wire _T_1095 = _T_1094 ^ dccm_wdata_hi_any[20]; // @[lib.scala 119:74] + wire _T_1096 = _T_1095 ^ dccm_wdata_hi_any[21]; // @[lib.scala 119:74] + wire _T_1097 = _T_1096 ^ dccm_wdata_hi_any[22]; // @[lib.scala 119:74] + wire _T_1098 = _T_1097 ^ dccm_wdata_hi_any[23]; // @[lib.scala 119:74] + wire _T_1099 = _T_1098 ^ dccm_wdata_hi_any[24]; // @[lib.scala 119:74] + wire _T_1100 = _T_1099 ^ dccm_wdata_hi_any[25]; // @[lib.scala 119:74] + wire _T_1107 = dccm_wdata_hi_any[26] ^ dccm_wdata_hi_any[27]; // @[lib.scala 119:74] + wire _T_1108 = _T_1107 ^ dccm_wdata_hi_any[28]; // @[lib.scala 119:74] + wire _T_1109 = _T_1108 ^ dccm_wdata_hi_any[29]; // @[lib.scala 119:74] + wire _T_1110 = _T_1109 ^ dccm_wdata_hi_any[30]; // @[lib.scala 119:74] + wire _T_1111 = _T_1110 ^ dccm_wdata_hi_any[31]; // @[lib.scala 119:74] + wire [5:0] _T_1116 = {_T_1111,_T_1100,_T_1071,_T_1042,_T_1007,_T_972}; // @[Cat.scala 29:58] + wire _T_1117 = ^dccm_wdata_hi_any; // @[lib.scala 127:13] + wire _T_1118 = ^_T_1116; // @[lib.scala 127:23] + wire _T_1119 = _T_1117 ^ _T_1118; // @[lib.scala 127:18] + reg _T_1150; // @[lsu_ecc.scala 141:72] + reg _T_1151; // @[lsu_ecc.scala 142:72] + reg _T_1152; // @[lsu_ecc.scala 143:72] + reg _T_1153; // @[lsu_ecc.scala 144:72] + reg [31:0] _T_1154; // @[lsu_ecc.scala 145:72] + reg [31:0] _T_1155; // @[lsu_ecc.scala 146:72] + reg [31:0] _T_1164; // @[lib.scala 374:16] + reg [31:0] _T_1165; // @[lib.scala 374:16] + rvclkhdr rvclkhdr ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) + ); + rvclkhdr rvclkhdr_1 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_1_io_l1clk), + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en), + .io_scan_mode(rvclkhdr_1_io_scan_mode) + ); + assign io_sec_data_hi_r = _T_1154; // @[lsu_ecc.scala 114:22 lsu_ecc.scala 145:62] + assign io_sec_data_lo_r = _T_1155; // @[lsu_ecc.scala 117:25 lsu_ecc.scala 146:62] + assign io_sec_data_hi_m = {_T_364,_T_362}; // @[lsu_ecc.scala 90:32 lsu_ecc.scala 134:27] + assign io_sec_data_lo_m = {_T_742,_T_740}; // @[lsu_ecc.scala 91:32 lsu_ecc.scala 136:27] + assign io_sec_data_hi_r_ff = _T_1164; // @[lsu_ecc.scala 157:23] + assign io_sec_data_lo_r_ff = _T_1165; // @[lsu_ecc.scala 158:23] + assign io_dma_dccm_wdata_ecc_hi = {_T_1119,_T_1116}; // @[lsu_ecc.scala 154:28] + assign io_dma_dccm_wdata_ecc_lo = {_T_937,_T_934}; // @[lsu_ecc.scala 155:28] + assign io_stbuf_ecc_any = {_T_937,_T_934}; // @[lsu_ecc.scala 153:28] + assign io_sec_data_ecc_hi_r_ff = {_T_1119,_T_1116}; // @[lsu_ecc.scala 151:28] + assign io_sec_data_ecc_lo_r_ff = {_T_937,_T_934}; // @[lsu_ecc.scala 152:28] + assign io_single_ecc_error_hi_r = _T_1153; // @[lsu_ecc.scala 115:31 lsu_ecc.scala 144:62] + assign io_single_ecc_error_lo_r = _T_1152; // @[lsu_ecc.scala 118:31 lsu_ecc.scala 143:62] + assign io_lsu_single_ecc_error_r = _T_1150; // @[lsu_ecc.scala 120:31 lsu_ecc.scala 141:62] + assign io_lsu_double_ecc_error_r = _T_1151; // @[lsu_ecc.scala 121:31 lsu_ecc.scala 142:62] + assign io_lsu_single_ecc_error_m = single_ecc_error_hi_any | single_ecc_error_lo_any; // @[lsu_ecc.scala 92:30 lsu_ecc.scala 138:33] + assign io_lsu_double_ecc_error_m = double_ecc_error_hi_any | double_ecc_error_lo_any; // @[lsu_ecc.scala 93:30 lsu_ecc.scala 139:33] + assign rvclkhdr_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_io_en = io_ld_single_ecc_error_r; // @[lib.scala 371:17] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_1_io_en = io_ld_single_ecc_error_r; // @[lib.scala 371:17] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + _T_1150 = _RAND_0[0:0]; + _RAND_1 = {1{`RANDOM}}; + _T_1151 = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + _T_1152 = _RAND_2[0:0]; + _RAND_3 = {1{`RANDOM}}; + _T_1153 = _RAND_3[0:0]; + _RAND_4 = {1{`RANDOM}}; + _T_1154 = _RAND_4[31:0]; + _RAND_5 = {1{`RANDOM}}; + _T_1155 = _RAND_5[31:0]; + _RAND_6 = {1{`RANDOM}}; + _T_1164 = _RAND_6[31:0]; + _RAND_7 = {1{`RANDOM}}; + _T_1165 = _RAND_7[31:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + _T_1150 = 1'h0; + end + if (reset) begin + _T_1151 = 1'h0; + end + if (reset) begin + _T_1152 = 1'h0; + end + if (reset) begin + _T_1153 = 1'h0; + end + if (reset) begin + _T_1154 = 32'h0; + end + if (reset) begin + _T_1155 = 32'h0; + end + if (reset) begin + _T_1164 = 32'h0; + end + if (reset) begin + _T_1165 = 32'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_1150 <= 1'h0; + end else begin + _T_1150 <= io_lsu_single_ecc_error_m; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_1151 <= 1'h0; + end else begin + _T_1151 <= io_lsu_double_ecc_error_m; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_1152 <= 1'h0; + end else begin + _T_1152 <= _T_588 & _T_586[6]; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_1153 <= 1'h0; + end else begin + _T_1153 <= _T_210 & _T_208[6]; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_1154 <= 32'h0; + end else begin + _T_1154 <= io_sec_data_hi_m; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_1155 <= 32'h0; + end else begin + _T_1155 <= io_sec_data_lo_m; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + if (reset) begin + _T_1164 <= 32'h0; + end else begin + _T_1164 <= io_sec_data_hi_r; + end + end + always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin + if (reset) begin + _T_1165 <= 32'h0; + end else begin + _T_1165 <= io_sec_data_lo_r; + end + end +endmodule +module lsu_trigger( + input io_trigger_pkt_any_0_select, + input io_trigger_pkt_any_0_match_pkt, + input io_trigger_pkt_any_0_store, + input io_trigger_pkt_any_0_load, + input [31:0] io_trigger_pkt_any_0_tdata2, + input io_trigger_pkt_any_1_select, + input io_trigger_pkt_any_1_match_pkt, + input io_trigger_pkt_any_1_store, + input io_trigger_pkt_any_1_load, + input [31:0] io_trigger_pkt_any_1_tdata2, + input io_trigger_pkt_any_2_select, + input io_trigger_pkt_any_2_match_pkt, + input io_trigger_pkt_any_2_store, + input io_trigger_pkt_any_2_load, + input [31:0] io_trigger_pkt_any_2_tdata2, + input io_trigger_pkt_any_3_select, + input io_trigger_pkt_any_3_match_pkt, + input io_trigger_pkt_any_3_store, + input io_trigger_pkt_any_3_load, + input [31:0] io_trigger_pkt_any_3_tdata2, + input io_lsu_pkt_m_valid, + input io_lsu_pkt_m_bits_half, + input io_lsu_pkt_m_bits_word, + input io_lsu_pkt_m_bits_load, + input io_lsu_pkt_m_bits_store, + input io_lsu_pkt_m_bits_dma, + input [31:0] io_lsu_addr_m, + input [31:0] io_store_data_m, + output [3:0] io_lsu_trigger_match_m +); + wire [15:0] _T_1 = io_lsu_pkt_m_bits_word ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12] + wire [15:0] _T_3 = _T_1 & io_store_data_m[31:16]; // @[lsu_trigger.scala 16:66] + wire _T_4 = io_lsu_pkt_m_bits_half | io_lsu_pkt_m_bits_word; // @[lsu_trigger.scala 16:124] + wire [7:0] _T_6 = _T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_8 = _T_6 & io_store_data_m[15:8]; // @[lsu_trigger.scala 16:151] + wire [31:0] store_data_trigger_m = {_T_3,_T_8,io_store_data_m[7:0]}; // @[Cat.scala 29:58] + wire _T_12 = ~io_trigger_pkt_any_0_select; // @[lsu_trigger.scala 17:53] + wire _T_13 = io_trigger_pkt_any_0_select & io_trigger_pkt_any_0_store; // @[lsu_trigger.scala 17:136] + wire [31:0] _T_15 = _T_12 ? io_lsu_addr_m : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_16 = _T_13 ? store_data_trigger_m : 32'h0; // @[Mux.scala 27:72] + wire [31:0] lsu_match_data_0 = _T_15 | _T_16; // @[Mux.scala 27:72] + wire _T_19 = ~io_trigger_pkt_any_1_select; // @[lsu_trigger.scala 17:53] + wire _T_20 = io_trigger_pkt_any_1_select & io_trigger_pkt_any_1_store; // @[lsu_trigger.scala 17:136] + wire [31:0] _T_22 = _T_19 ? io_lsu_addr_m : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_23 = _T_20 ? store_data_trigger_m : 32'h0; // @[Mux.scala 27:72] + wire [31:0] lsu_match_data_1 = _T_22 | _T_23; // @[Mux.scala 27:72] + wire _T_26 = ~io_trigger_pkt_any_2_select; // @[lsu_trigger.scala 17:53] + wire _T_27 = io_trigger_pkt_any_2_select & io_trigger_pkt_any_2_store; // @[lsu_trigger.scala 17:136] + wire [31:0] _T_29 = _T_26 ? io_lsu_addr_m : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_30 = _T_27 ? store_data_trigger_m : 32'h0; // @[Mux.scala 27:72] + wire [31:0] lsu_match_data_2 = _T_29 | _T_30; // @[Mux.scala 27:72] + wire _T_33 = ~io_trigger_pkt_any_3_select; // @[lsu_trigger.scala 17:53] + wire _T_34 = io_trigger_pkt_any_3_select & io_trigger_pkt_any_3_store; // @[lsu_trigger.scala 17:136] + wire [31:0] _T_36 = _T_33 ? io_lsu_addr_m : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_37 = _T_34 ? store_data_trigger_m : 32'h0; // @[Mux.scala 27:72] + wire [31:0] lsu_match_data_3 = _T_36 | _T_37; // @[Mux.scala 27:72] + wire _T_39 = ~io_lsu_pkt_m_bits_dma; // @[lsu_trigger.scala 18:71] + wire _T_40 = io_lsu_pkt_m_valid & _T_39; // @[lsu_trigger.scala 18:69] + wire _T_41 = io_trigger_pkt_any_0_store & io_lsu_pkt_m_bits_store; // @[lsu_trigger.scala 18:126] + wire _T_42 = io_trigger_pkt_any_0_load & io_lsu_pkt_m_bits_load; // @[lsu_trigger.scala 19:33] + wire _T_44 = _T_42 & _T_12; // @[lsu_trigger.scala 19:58] + wire _T_45 = _T_41 | _T_44; // @[lsu_trigger.scala 18:152] + wire _T_46 = _T_40 & _T_45; // @[lsu_trigger.scala 18:94] + wire _T_49 = &io_trigger_pkt_any_0_tdata2; // @[lib.scala 101:45] + wire _T_50 = ~_T_49; // @[lib.scala 101:39] + wire _T_51 = io_trigger_pkt_any_0_match_pkt & _T_50; // @[lib.scala 101:37] + wire _T_54 = io_trigger_pkt_any_0_tdata2[0] == lsu_match_data_0[0]; // @[lib.scala 102:52] + wire _T_55 = _T_51 | _T_54; // @[lib.scala 102:41] + wire _T_57 = &io_trigger_pkt_any_0_tdata2[0]; // @[lib.scala 104:36] + wire _T_58 = _T_57 & _T_51; // @[lib.scala 104:41] + wire _T_61 = io_trigger_pkt_any_0_tdata2[1] == lsu_match_data_0[1]; // @[lib.scala 104:78] + wire _T_62 = _T_58 | _T_61; // @[lib.scala 104:23] + wire _T_64 = &io_trigger_pkt_any_0_tdata2[1:0]; // @[lib.scala 104:36] + wire _T_65 = _T_64 & _T_51; // @[lib.scala 104:41] + wire _T_68 = io_trigger_pkt_any_0_tdata2[2] == lsu_match_data_0[2]; // @[lib.scala 104:78] + wire _T_69 = _T_65 | _T_68; // @[lib.scala 104:23] + wire _T_71 = &io_trigger_pkt_any_0_tdata2[2:0]; // @[lib.scala 104:36] + wire _T_72 = _T_71 & _T_51; // @[lib.scala 104:41] + wire _T_75 = io_trigger_pkt_any_0_tdata2[3] == lsu_match_data_0[3]; // @[lib.scala 104:78] + wire _T_76 = _T_72 | _T_75; // @[lib.scala 104:23] + wire _T_78 = &io_trigger_pkt_any_0_tdata2[3:0]; // @[lib.scala 104:36] + wire _T_79 = _T_78 & _T_51; // @[lib.scala 104:41] + wire _T_82 = io_trigger_pkt_any_0_tdata2[4] == lsu_match_data_0[4]; // @[lib.scala 104:78] + wire _T_83 = _T_79 | _T_82; // @[lib.scala 104:23] + wire _T_85 = &io_trigger_pkt_any_0_tdata2[4:0]; // @[lib.scala 104:36] + wire _T_86 = _T_85 & _T_51; // @[lib.scala 104:41] + wire _T_89 = io_trigger_pkt_any_0_tdata2[5] == lsu_match_data_0[5]; // @[lib.scala 104:78] + wire _T_90 = _T_86 | _T_89; // @[lib.scala 104:23] + wire _T_92 = &io_trigger_pkt_any_0_tdata2[5:0]; // @[lib.scala 104:36] + wire _T_93 = _T_92 & _T_51; // @[lib.scala 104:41] + wire _T_96 = io_trigger_pkt_any_0_tdata2[6] == lsu_match_data_0[6]; // @[lib.scala 104:78] + wire _T_97 = _T_93 | _T_96; // @[lib.scala 104:23] + wire _T_99 = &io_trigger_pkt_any_0_tdata2[6:0]; // @[lib.scala 104:36] + wire _T_100 = _T_99 & _T_51; // @[lib.scala 104:41] + wire _T_103 = io_trigger_pkt_any_0_tdata2[7] == lsu_match_data_0[7]; // @[lib.scala 104:78] + wire _T_104 = _T_100 | _T_103; // @[lib.scala 104:23] + wire _T_106 = &io_trigger_pkt_any_0_tdata2[7:0]; // @[lib.scala 104:36] + wire _T_107 = _T_106 & _T_51; // @[lib.scala 104:41] + wire _T_110 = io_trigger_pkt_any_0_tdata2[8] == lsu_match_data_0[8]; // @[lib.scala 104:78] + wire _T_111 = _T_107 | _T_110; // @[lib.scala 104:23] + wire _T_113 = &io_trigger_pkt_any_0_tdata2[8:0]; // @[lib.scala 104:36] + wire _T_114 = _T_113 & _T_51; // @[lib.scala 104:41] + wire _T_117 = io_trigger_pkt_any_0_tdata2[9] == lsu_match_data_0[9]; // @[lib.scala 104:78] + wire _T_118 = _T_114 | _T_117; // @[lib.scala 104:23] + wire _T_120 = &io_trigger_pkt_any_0_tdata2[9:0]; // @[lib.scala 104:36] + wire _T_121 = _T_120 & _T_51; // @[lib.scala 104:41] + wire _T_124 = io_trigger_pkt_any_0_tdata2[10] == lsu_match_data_0[10]; // @[lib.scala 104:78] + wire _T_125 = _T_121 | _T_124; // @[lib.scala 104:23] + wire _T_127 = &io_trigger_pkt_any_0_tdata2[10:0]; // @[lib.scala 104:36] + wire _T_128 = _T_127 & _T_51; // @[lib.scala 104:41] + wire _T_131 = io_trigger_pkt_any_0_tdata2[11] == lsu_match_data_0[11]; // @[lib.scala 104:78] + wire _T_132 = _T_128 | _T_131; // @[lib.scala 104:23] + wire _T_134 = &io_trigger_pkt_any_0_tdata2[11:0]; // @[lib.scala 104:36] + wire _T_135 = _T_134 & _T_51; // @[lib.scala 104:41] + wire _T_138 = io_trigger_pkt_any_0_tdata2[12] == lsu_match_data_0[12]; // @[lib.scala 104:78] + wire _T_139 = _T_135 | _T_138; // @[lib.scala 104:23] + wire _T_141 = &io_trigger_pkt_any_0_tdata2[12:0]; // @[lib.scala 104:36] + wire _T_142 = _T_141 & _T_51; // @[lib.scala 104:41] + wire _T_145 = io_trigger_pkt_any_0_tdata2[13] == lsu_match_data_0[13]; // @[lib.scala 104:78] + wire _T_146 = _T_142 | _T_145; // @[lib.scala 104:23] + wire _T_148 = &io_trigger_pkt_any_0_tdata2[13:0]; // @[lib.scala 104:36] + wire _T_149 = _T_148 & _T_51; // @[lib.scala 104:41] + wire _T_152 = io_trigger_pkt_any_0_tdata2[14] == lsu_match_data_0[14]; // @[lib.scala 104:78] + wire _T_153 = _T_149 | _T_152; // @[lib.scala 104:23] + wire _T_155 = &io_trigger_pkt_any_0_tdata2[14:0]; // @[lib.scala 104:36] + wire _T_156 = _T_155 & _T_51; // @[lib.scala 104:41] + wire _T_159 = io_trigger_pkt_any_0_tdata2[15] == lsu_match_data_0[15]; // @[lib.scala 104:78] + wire _T_160 = _T_156 | _T_159; // @[lib.scala 104:23] + wire _T_162 = &io_trigger_pkt_any_0_tdata2[15:0]; // @[lib.scala 104:36] + wire _T_163 = _T_162 & _T_51; // @[lib.scala 104:41] + wire _T_166 = io_trigger_pkt_any_0_tdata2[16] == lsu_match_data_0[16]; // @[lib.scala 104:78] + wire _T_167 = _T_163 | _T_166; // @[lib.scala 104:23] + wire _T_169 = &io_trigger_pkt_any_0_tdata2[16:0]; // @[lib.scala 104:36] + wire _T_170 = _T_169 & _T_51; // @[lib.scala 104:41] + wire _T_173 = io_trigger_pkt_any_0_tdata2[17] == lsu_match_data_0[17]; // @[lib.scala 104:78] + wire _T_174 = _T_170 | _T_173; // @[lib.scala 104:23] + wire _T_176 = &io_trigger_pkt_any_0_tdata2[17:0]; // @[lib.scala 104:36] + wire _T_177 = _T_176 & _T_51; // @[lib.scala 104:41] + wire _T_180 = io_trigger_pkt_any_0_tdata2[18] == lsu_match_data_0[18]; // @[lib.scala 104:78] + wire _T_181 = _T_177 | _T_180; // @[lib.scala 104:23] + wire _T_183 = &io_trigger_pkt_any_0_tdata2[18:0]; // @[lib.scala 104:36] + wire _T_184 = _T_183 & _T_51; // @[lib.scala 104:41] + wire _T_187 = io_trigger_pkt_any_0_tdata2[19] == lsu_match_data_0[19]; // @[lib.scala 104:78] + wire _T_188 = _T_184 | _T_187; // @[lib.scala 104:23] + wire _T_190 = &io_trigger_pkt_any_0_tdata2[19:0]; // @[lib.scala 104:36] + wire _T_191 = _T_190 & _T_51; // @[lib.scala 104:41] + wire _T_194 = io_trigger_pkt_any_0_tdata2[20] == lsu_match_data_0[20]; // @[lib.scala 104:78] + wire _T_195 = _T_191 | _T_194; // @[lib.scala 104:23] + wire _T_197 = &io_trigger_pkt_any_0_tdata2[20:0]; // @[lib.scala 104:36] + wire _T_198 = _T_197 & _T_51; // @[lib.scala 104:41] + wire _T_201 = io_trigger_pkt_any_0_tdata2[21] == lsu_match_data_0[21]; // @[lib.scala 104:78] + wire _T_202 = _T_198 | _T_201; // @[lib.scala 104:23] + wire _T_204 = &io_trigger_pkt_any_0_tdata2[21:0]; // @[lib.scala 104:36] + wire _T_205 = _T_204 & _T_51; // @[lib.scala 104:41] + wire _T_208 = io_trigger_pkt_any_0_tdata2[22] == lsu_match_data_0[22]; // @[lib.scala 104:78] + wire _T_209 = _T_205 | _T_208; // @[lib.scala 104:23] + wire _T_211 = &io_trigger_pkt_any_0_tdata2[22:0]; // @[lib.scala 104:36] + wire _T_212 = _T_211 & _T_51; // @[lib.scala 104:41] + wire _T_215 = io_trigger_pkt_any_0_tdata2[23] == lsu_match_data_0[23]; // @[lib.scala 104:78] + wire _T_216 = _T_212 | _T_215; // @[lib.scala 104:23] + wire _T_218 = &io_trigger_pkt_any_0_tdata2[23:0]; // @[lib.scala 104:36] + wire _T_219 = _T_218 & _T_51; // @[lib.scala 104:41] + wire _T_222 = io_trigger_pkt_any_0_tdata2[24] == lsu_match_data_0[24]; // @[lib.scala 104:78] + wire _T_223 = _T_219 | _T_222; // @[lib.scala 104:23] + wire _T_225 = &io_trigger_pkt_any_0_tdata2[24:0]; // @[lib.scala 104:36] + wire _T_226 = _T_225 & _T_51; // @[lib.scala 104:41] + wire _T_229 = io_trigger_pkt_any_0_tdata2[25] == lsu_match_data_0[25]; // @[lib.scala 104:78] + wire _T_230 = _T_226 | _T_229; // @[lib.scala 104:23] + wire _T_232 = &io_trigger_pkt_any_0_tdata2[25:0]; // @[lib.scala 104:36] + wire _T_233 = _T_232 & _T_51; // @[lib.scala 104:41] + wire _T_236 = io_trigger_pkt_any_0_tdata2[26] == lsu_match_data_0[26]; // @[lib.scala 104:78] + wire _T_237 = _T_233 | _T_236; // @[lib.scala 104:23] + wire _T_239 = &io_trigger_pkt_any_0_tdata2[26:0]; // @[lib.scala 104:36] + wire _T_240 = _T_239 & _T_51; // @[lib.scala 104:41] + wire _T_243 = io_trigger_pkt_any_0_tdata2[27] == lsu_match_data_0[27]; // @[lib.scala 104:78] + wire _T_244 = _T_240 | _T_243; // @[lib.scala 104:23] + wire _T_246 = &io_trigger_pkt_any_0_tdata2[27:0]; // @[lib.scala 104:36] + wire _T_247 = _T_246 & _T_51; // @[lib.scala 104:41] + wire _T_250 = io_trigger_pkt_any_0_tdata2[28] == lsu_match_data_0[28]; // @[lib.scala 104:78] + wire _T_251 = _T_247 | _T_250; // @[lib.scala 104:23] + wire _T_253 = &io_trigger_pkt_any_0_tdata2[28:0]; // @[lib.scala 104:36] + wire _T_254 = _T_253 & _T_51; // @[lib.scala 104:41] + wire _T_257 = io_trigger_pkt_any_0_tdata2[29] == lsu_match_data_0[29]; // @[lib.scala 104:78] + wire _T_258 = _T_254 | _T_257; // @[lib.scala 104:23] + wire _T_260 = &io_trigger_pkt_any_0_tdata2[29:0]; // @[lib.scala 104:36] + wire _T_261 = _T_260 & _T_51; // @[lib.scala 104:41] + wire _T_264 = io_trigger_pkt_any_0_tdata2[30] == lsu_match_data_0[30]; // @[lib.scala 104:78] + wire _T_265 = _T_261 | _T_264; // @[lib.scala 104:23] + wire _T_267 = &io_trigger_pkt_any_0_tdata2[30:0]; // @[lib.scala 104:36] + wire _T_268 = _T_267 & _T_51; // @[lib.scala 104:41] + wire _T_271 = io_trigger_pkt_any_0_tdata2[31] == lsu_match_data_0[31]; // @[lib.scala 104:78] + wire _T_272 = _T_268 | _T_271; // @[lib.scala 104:23] + wire [7:0] _T_279 = {_T_104,_T_97,_T_90,_T_83,_T_76,_T_69,_T_62,_T_55}; // @[lib.scala 105:14] + wire [15:0] _T_287 = {_T_160,_T_153,_T_146,_T_139,_T_132,_T_125,_T_118,_T_111,_T_279}; // @[lib.scala 105:14] + wire [7:0] _T_294 = {_T_216,_T_209,_T_202,_T_195,_T_188,_T_181,_T_174,_T_167}; // @[lib.scala 105:14] + wire [31:0] _T_303 = {_T_272,_T_265,_T_258,_T_251,_T_244,_T_237,_T_230,_T_223,_T_294,_T_287}; // @[lib.scala 105:14] + wire _T_304 = &_T_303; // @[lib.scala 105:25] + wire _T_305 = _T_46 & _T_304; // @[lsu_trigger.scala 19:92] + wire _T_308 = io_trigger_pkt_any_1_store & io_lsu_pkt_m_bits_store; // @[lsu_trigger.scala 18:126] + wire _T_309 = io_trigger_pkt_any_1_load & io_lsu_pkt_m_bits_load; // @[lsu_trigger.scala 19:33] + wire _T_311 = _T_309 & _T_19; // @[lsu_trigger.scala 19:58] + wire _T_312 = _T_308 | _T_311; // @[lsu_trigger.scala 18:152] + wire _T_313 = _T_40 & _T_312; // @[lsu_trigger.scala 18:94] + wire _T_316 = &io_trigger_pkt_any_1_tdata2; // @[lib.scala 101:45] + wire _T_317 = ~_T_316; // @[lib.scala 101:39] + wire _T_318 = io_trigger_pkt_any_1_match_pkt & _T_317; // @[lib.scala 101:37] + wire _T_321 = io_trigger_pkt_any_1_tdata2[0] == lsu_match_data_1[0]; // @[lib.scala 102:52] + wire _T_322 = _T_318 | _T_321; // @[lib.scala 102:41] + wire _T_324 = &io_trigger_pkt_any_1_tdata2[0]; // @[lib.scala 104:36] + wire _T_325 = _T_324 & _T_318; // @[lib.scala 104:41] + wire _T_328 = io_trigger_pkt_any_1_tdata2[1] == lsu_match_data_1[1]; // @[lib.scala 104:78] + wire _T_329 = _T_325 | _T_328; // @[lib.scala 104:23] + wire _T_331 = &io_trigger_pkt_any_1_tdata2[1:0]; // @[lib.scala 104:36] + wire _T_332 = _T_331 & _T_318; // @[lib.scala 104:41] + wire _T_335 = io_trigger_pkt_any_1_tdata2[2] == lsu_match_data_1[2]; // @[lib.scala 104:78] + wire _T_336 = _T_332 | _T_335; // @[lib.scala 104:23] + wire _T_338 = &io_trigger_pkt_any_1_tdata2[2:0]; // @[lib.scala 104:36] + wire _T_339 = _T_338 & _T_318; // @[lib.scala 104:41] + wire _T_342 = io_trigger_pkt_any_1_tdata2[3] == lsu_match_data_1[3]; // @[lib.scala 104:78] + wire _T_343 = _T_339 | _T_342; // @[lib.scala 104:23] + wire _T_345 = &io_trigger_pkt_any_1_tdata2[3:0]; // @[lib.scala 104:36] + wire _T_346 = _T_345 & _T_318; // @[lib.scala 104:41] + wire _T_349 = io_trigger_pkt_any_1_tdata2[4] == lsu_match_data_1[4]; // @[lib.scala 104:78] + wire _T_350 = _T_346 | _T_349; // @[lib.scala 104:23] + wire _T_352 = &io_trigger_pkt_any_1_tdata2[4:0]; // @[lib.scala 104:36] + wire _T_353 = _T_352 & _T_318; // @[lib.scala 104:41] + wire _T_356 = io_trigger_pkt_any_1_tdata2[5] == lsu_match_data_1[5]; // @[lib.scala 104:78] + wire _T_357 = _T_353 | _T_356; // @[lib.scala 104:23] + wire _T_359 = &io_trigger_pkt_any_1_tdata2[5:0]; // @[lib.scala 104:36] + wire _T_360 = _T_359 & _T_318; // @[lib.scala 104:41] + wire _T_363 = io_trigger_pkt_any_1_tdata2[6] == lsu_match_data_1[6]; // @[lib.scala 104:78] + wire _T_364 = _T_360 | _T_363; // @[lib.scala 104:23] + wire _T_366 = &io_trigger_pkt_any_1_tdata2[6:0]; // @[lib.scala 104:36] + wire _T_367 = _T_366 & _T_318; // @[lib.scala 104:41] + wire _T_370 = io_trigger_pkt_any_1_tdata2[7] == lsu_match_data_1[7]; // @[lib.scala 104:78] + wire _T_371 = _T_367 | _T_370; // @[lib.scala 104:23] + wire _T_373 = &io_trigger_pkt_any_1_tdata2[7:0]; // @[lib.scala 104:36] + wire _T_374 = _T_373 & _T_318; // @[lib.scala 104:41] + wire _T_377 = io_trigger_pkt_any_1_tdata2[8] == lsu_match_data_1[8]; // @[lib.scala 104:78] + wire _T_378 = _T_374 | _T_377; // @[lib.scala 104:23] + wire _T_380 = &io_trigger_pkt_any_1_tdata2[8:0]; // @[lib.scala 104:36] + wire _T_381 = _T_380 & _T_318; // @[lib.scala 104:41] + wire _T_384 = io_trigger_pkt_any_1_tdata2[9] == lsu_match_data_1[9]; // @[lib.scala 104:78] + wire _T_385 = _T_381 | _T_384; // @[lib.scala 104:23] + wire _T_387 = &io_trigger_pkt_any_1_tdata2[9:0]; // @[lib.scala 104:36] + wire _T_388 = _T_387 & _T_318; // @[lib.scala 104:41] + wire _T_391 = io_trigger_pkt_any_1_tdata2[10] == lsu_match_data_1[10]; // @[lib.scala 104:78] + wire _T_392 = _T_388 | _T_391; // @[lib.scala 104:23] + wire _T_394 = &io_trigger_pkt_any_1_tdata2[10:0]; // @[lib.scala 104:36] + wire _T_395 = _T_394 & _T_318; // @[lib.scala 104:41] + wire _T_398 = io_trigger_pkt_any_1_tdata2[11] == lsu_match_data_1[11]; // @[lib.scala 104:78] + wire _T_399 = _T_395 | _T_398; // @[lib.scala 104:23] + wire _T_401 = &io_trigger_pkt_any_1_tdata2[11:0]; // @[lib.scala 104:36] + wire _T_402 = _T_401 & _T_318; // @[lib.scala 104:41] + wire _T_405 = io_trigger_pkt_any_1_tdata2[12] == lsu_match_data_1[12]; // @[lib.scala 104:78] + wire _T_406 = _T_402 | _T_405; // @[lib.scala 104:23] + wire _T_408 = &io_trigger_pkt_any_1_tdata2[12:0]; // @[lib.scala 104:36] + wire _T_409 = _T_408 & _T_318; // @[lib.scala 104:41] + wire _T_412 = io_trigger_pkt_any_1_tdata2[13] == lsu_match_data_1[13]; // @[lib.scala 104:78] + wire _T_413 = _T_409 | _T_412; // @[lib.scala 104:23] + wire _T_415 = &io_trigger_pkt_any_1_tdata2[13:0]; // @[lib.scala 104:36] + wire _T_416 = _T_415 & _T_318; // @[lib.scala 104:41] + wire _T_419 = io_trigger_pkt_any_1_tdata2[14] == lsu_match_data_1[14]; // @[lib.scala 104:78] + wire _T_420 = _T_416 | _T_419; // @[lib.scala 104:23] + wire _T_422 = &io_trigger_pkt_any_1_tdata2[14:0]; // @[lib.scala 104:36] + wire _T_423 = _T_422 & _T_318; // @[lib.scala 104:41] + wire _T_426 = io_trigger_pkt_any_1_tdata2[15] == lsu_match_data_1[15]; // @[lib.scala 104:78] + wire _T_427 = _T_423 | _T_426; // @[lib.scala 104:23] + wire _T_429 = &io_trigger_pkt_any_1_tdata2[15:0]; // @[lib.scala 104:36] + wire _T_430 = _T_429 & _T_318; // @[lib.scala 104:41] + wire _T_433 = io_trigger_pkt_any_1_tdata2[16] == lsu_match_data_1[16]; // @[lib.scala 104:78] + wire _T_434 = _T_430 | _T_433; // @[lib.scala 104:23] + wire _T_436 = &io_trigger_pkt_any_1_tdata2[16:0]; // @[lib.scala 104:36] + wire _T_437 = _T_436 & _T_318; // @[lib.scala 104:41] + wire _T_440 = io_trigger_pkt_any_1_tdata2[17] == lsu_match_data_1[17]; // @[lib.scala 104:78] + wire _T_441 = _T_437 | _T_440; // @[lib.scala 104:23] + wire _T_443 = &io_trigger_pkt_any_1_tdata2[17:0]; // @[lib.scala 104:36] + wire _T_444 = _T_443 & _T_318; // @[lib.scala 104:41] + wire _T_447 = io_trigger_pkt_any_1_tdata2[18] == lsu_match_data_1[18]; // @[lib.scala 104:78] + wire _T_448 = _T_444 | _T_447; // @[lib.scala 104:23] + wire _T_450 = &io_trigger_pkt_any_1_tdata2[18:0]; // @[lib.scala 104:36] + wire _T_451 = _T_450 & _T_318; // @[lib.scala 104:41] + wire _T_454 = io_trigger_pkt_any_1_tdata2[19] == lsu_match_data_1[19]; // @[lib.scala 104:78] + wire _T_455 = _T_451 | _T_454; // @[lib.scala 104:23] + wire _T_457 = &io_trigger_pkt_any_1_tdata2[19:0]; // @[lib.scala 104:36] + wire _T_458 = _T_457 & _T_318; // @[lib.scala 104:41] + wire _T_461 = io_trigger_pkt_any_1_tdata2[20] == lsu_match_data_1[20]; // @[lib.scala 104:78] + wire _T_462 = _T_458 | _T_461; // @[lib.scala 104:23] + wire _T_464 = &io_trigger_pkt_any_1_tdata2[20:0]; // @[lib.scala 104:36] + wire _T_465 = _T_464 & _T_318; // @[lib.scala 104:41] + wire _T_468 = io_trigger_pkt_any_1_tdata2[21] == lsu_match_data_1[21]; // @[lib.scala 104:78] + wire _T_469 = _T_465 | _T_468; // @[lib.scala 104:23] + wire _T_471 = &io_trigger_pkt_any_1_tdata2[21:0]; // @[lib.scala 104:36] + wire _T_472 = _T_471 & _T_318; // @[lib.scala 104:41] + wire _T_475 = io_trigger_pkt_any_1_tdata2[22] == lsu_match_data_1[22]; // @[lib.scala 104:78] + wire _T_476 = _T_472 | _T_475; // @[lib.scala 104:23] + wire _T_478 = &io_trigger_pkt_any_1_tdata2[22:0]; // @[lib.scala 104:36] + wire _T_479 = _T_478 & _T_318; // @[lib.scala 104:41] + wire _T_482 = io_trigger_pkt_any_1_tdata2[23] == lsu_match_data_1[23]; // @[lib.scala 104:78] + wire _T_483 = _T_479 | _T_482; // @[lib.scala 104:23] + wire _T_485 = &io_trigger_pkt_any_1_tdata2[23:0]; // @[lib.scala 104:36] + wire _T_486 = _T_485 & _T_318; // @[lib.scala 104:41] + wire _T_489 = io_trigger_pkt_any_1_tdata2[24] == lsu_match_data_1[24]; // @[lib.scala 104:78] + wire _T_490 = _T_486 | _T_489; // @[lib.scala 104:23] + wire _T_492 = &io_trigger_pkt_any_1_tdata2[24:0]; // @[lib.scala 104:36] + wire _T_493 = _T_492 & _T_318; // @[lib.scala 104:41] + wire _T_496 = io_trigger_pkt_any_1_tdata2[25] == lsu_match_data_1[25]; // @[lib.scala 104:78] + wire _T_497 = _T_493 | _T_496; // @[lib.scala 104:23] + wire _T_499 = &io_trigger_pkt_any_1_tdata2[25:0]; // @[lib.scala 104:36] + wire _T_500 = _T_499 & _T_318; // @[lib.scala 104:41] + wire _T_503 = io_trigger_pkt_any_1_tdata2[26] == lsu_match_data_1[26]; // @[lib.scala 104:78] + wire _T_504 = _T_500 | _T_503; // @[lib.scala 104:23] + wire _T_506 = &io_trigger_pkt_any_1_tdata2[26:0]; // @[lib.scala 104:36] + wire _T_507 = _T_506 & _T_318; // @[lib.scala 104:41] + wire _T_510 = io_trigger_pkt_any_1_tdata2[27] == lsu_match_data_1[27]; // @[lib.scala 104:78] + wire _T_511 = _T_507 | _T_510; // @[lib.scala 104:23] + wire _T_513 = &io_trigger_pkt_any_1_tdata2[27:0]; // @[lib.scala 104:36] + wire _T_514 = _T_513 & _T_318; // @[lib.scala 104:41] + wire _T_517 = io_trigger_pkt_any_1_tdata2[28] == lsu_match_data_1[28]; // @[lib.scala 104:78] + wire _T_518 = _T_514 | _T_517; // @[lib.scala 104:23] + wire _T_520 = &io_trigger_pkt_any_1_tdata2[28:0]; // @[lib.scala 104:36] + wire _T_521 = _T_520 & _T_318; // @[lib.scala 104:41] + wire _T_524 = io_trigger_pkt_any_1_tdata2[29] == lsu_match_data_1[29]; // @[lib.scala 104:78] + wire _T_525 = _T_521 | _T_524; // @[lib.scala 104:23] + wire _T_527 = &io_trigger_pkt_any_1_tdata2[29:0]; // @[lib.scala 104:36] + wire _T_528 = _T_527 & _T_318; // @[lib.scala 104:41] + wire _T_531 = io_trigger_pkt_any_1_tdata2[30] == lsu_match_data_1[30]; // @[lib.scala 104:78] + wire _T_532 = _T_528 | _T_531; // @[lib.scala 104:23] + wire _T_534 = &io_trigger_pkt_any_1_tdata2[30:0]; // @[lib.scala 104:36] + wire _T_535 = _T_534 & _T_318; // @[lib.scala 104:41] + wire _T_538 = io_trigger_pkt_any_1_tdata2[31] == lsu_match_data_1[31]; // @[lib.scala 104:78] + wire _T_539 = _T_535 | _T_538; // @[lib.scala 104:23] + wire [7:0] _T_546 = {_T_371,_T_364,_T_357,_T_350,_T_343,_T_336,_T_329,_T_322}; // @[lib.scala 105:14] + wire [15:0] _T_554 = {_T_427,_T_420,_T_413,_T_406,_T_399,_T_392,_T_385,_T_378,_T_546}; // @[lib.scala 105:14] + wire [7:0] _T_561 = {_T_483,_T_476,_T_469,_T_462,_T_455,_T_448,_T_441,_T_434}; // @[lib.scala 105:14] + wire [31:0] _T_570 = {_T_539,_T_532,_T_525,_T_518,_T_511,_T_504,_T_497,_T_490,_T_561,_T_554}; // @[lib.scala 105:14] + wire _T_571 = &_T_570; // @[lib.scala 105:25] + wire _T_572 = _T_313 & _T_571; // @[lsu_trigger.scala 19:92] + wire _T_575 = io_trigger_pkt_any_2_store & io_lsu_pkt_m_bits_store; // @[lsu_trigger.scala 18:126] + wire _T_576 = io_trigger_pkt_any_2_load & io_lsu_pkt_m_bits_load; // @[lsu_trigger.scala 19:33] + wire _T_578 = _T_576 & _T_26; // @[lsu_trigger.scala 19:58] + wire _T_579 = _T_575 | _T_578; // @[lsu_trigger.scala 18:152] + wire _T_580 = _T_40 & _T_579; // @[lsu_trigger.scala 18:94] + wire _T_583 = &io_trigger_pkt_any_2_tdata2; // @[lib.scala 101:45] + wire _T_584 = ~_T_583; // @[lib.scala 101:39] + wire _T_585 = io_trigger_pkt_any_2_match_pkt & _T_584; // @[lib.scala 101:37] + wire _T_588 = io_trigger_pkt_any_2_tdata2[0] == lsu_match_data_2[0]; // @[lib.scala 102:52] + wire _T_589 = _T_585 | _T_588; // @[lib.scala 102:41] + wire _T_591 = &io_trigger_pkt_any_2_tdata2[0]; // @[lib.scala 104:36] + wire _T_592 = _T_591 & _T_585; // @[lib.scala 104:41] + wire _T_595 = io_trigger_pkt_any_2_tdata2[1] == lsu_match_data_2[1]; // @[lib.scala 104:78] + wire _T_596 = _T_592 | _T_595; // @[lib.scala 104:23] + wire _T_598 = &io_trigger_pkt_any_2_tdata2[1:0]; // @[lib.scala 104:36] + wire _T_599 = _T_598 & _T_585; // @[lib.scala 104:41] + wire _T_602 = io_trigger_pkt_any_2_tdata2[2] == lsu_match_data_2[2]; // @[lib.scala 104:78] + wire _T_603 = _T_599 | _T_602; // @[lib.scala 104:23] + wire _T_605 = &io_trigger_pkt_any_2_tdata2[2:0]; // @[lib.scala 104:36] + wire _T_606 = _T_605 & _T_585; // @[lib.scala 104:41] + wire _T_609 = io_trigger_pkt_any_2_tdata2[3] == lsu_match_data_2[3]; // @[lib.scala 104:78] + wire _T_610 = _T_606 | _T_609; // @[lib.scala 104:23] + wire _T_612 = &io_trigger_pkt_any_2_tdata2[3:0]; // @[lib.scala 104:36] + wire _T_613 = _T_612 & _T_585; // @[lib.scala 104:41] + wire _T_616 = io_trigger_pkt_any_2_tdata2[4] == lsu_match_data_2[4]; // @[lib.scala 104:78] + wire _T_617 = _T_613 | _T_616; // @[lib.scala 104:23] + wire _T_619 = &io_trigger_pkt_any_2_tdata2[4:0]; // @[lib.scala 104:36] + wire _T_620 = _T_619 & _T_585; // @[lib.scala 104:41] + wire _T_623 = io_trigger_pkt_any_2_tdata2[5] == lsu_match_data_2[5]; // @[lib.scala 104:78] + wire _T_624 = _T_620 | _T_623; // @[lib.scala 104:23] + wire _T_626 = &io_trigger_pkt_any_2_tdata2[5:0]; // @[lib.scala 104:36] + wire _T_627 = _T_626 & _T_585; // @[lib.scala 104:41] + wire _T_630 = io_trigger_pkt_any_2_tdata2[6] == lsu_match_data_2[6]; // @[lib.scala 104:78] + wire _T_631 = _T_627 | _T_630; // @[lib.scala 104:23] + wire _T_633 = &io_trigger_pkt_any_2_tdata2[6:0]; // @[lib.scala 104:36] + wire _T_634 = _T_633 & _T_585; // @[lib.scala 104:41] + wire _T_637 = io_trigger_pkt_any_2_tdata2[7] == lsu_match_data_2[7]; // @[lib.scala 104:78] + wire _T_638 = _T_634 | _T_637; // @[lib.scala 104:23] + wire _T_640 = &io_trigger_pkt_any_2_tdata2[7:0]; // @[lib.scala 104:36] + wire _T_641 = _T_640 & _T_585; // @[lib.scala 104:41] + wire _T_644 = io_trigger_pkt_any_2_tdata2[8] == lsu_match_data_2[8]; // @[lib.scala 104:78] + wire _T_645 = _T_641 | _T_644; // @[lib.scala 104:23] + wire _T_647 = &io_trigger_pkt_any_2_tdata2[8:0]; // @[lib.scala 104:36] + wire _T_648 = _T_647 & _T_585; // @[lib.scala 104:41] + wire _T_651 = io_trigger_pkt_any_2_tdata2[9] == lsu_match_data_2[9]; // @[lib.scala 104:78] + wire _T_652 = _T_648 | _T_651; // @[lib.scala 104:23] + wire _T_654 = &io_trigger_pkt_any_2_tdata2[9:0]; // @[lib.scala 104:36] + wire _T_655 = _T_654 & _T_585; // @[lib.scala 104:41] + wire _T_658 = io_trigger_pkt_any_2_tdata2[10] == lsu_match_data_2[10]; // @[lib.scala 104:78] + wire _T_659 = _T_655 | _T_658; // @[lib.scala 104:23] + wire _T_661 = &io_trigger_pkt_any_2_tdata2[10:0]; // @[lib.scala 104:36] + wire _T_662 = _T_661 & _T_585; // @[lib.scala 104:41] + wire _T_665 = io_trigger_pkt_any_2_tdata2[11] == lsu_match_data_2[11]; // @[lib.scala 104:78] + wire _T_666 = _T_662 | _T_665; // @[lib.scala 104:23] + wire _T_668 = &io_trigger_pkt_any_2_tdata2[11:0]; // @[lib.scala 104:36] + wire _T_669 = _T_668 & _T_585; // @[lib.scala 104:41] + wire _T_672 = io_trigger_pkt_any_2_tdata2[12] == lsu_match_data_2[12]; // @[lib.scala 104:78] + wire _T_673 = _T_669 | _T_672; // @[lib.scala 104:23] + wire _T_675 = &io_trigger_pkt_any_2_tdata2[12:0]; // @[lib.scala 104:36] + wire _T_676 = _T_675 & _T_585; // @[lib.scala 104:41] + wire _T_679 = io_trigger_pkt_any_2_tdata2[13] == lsu_match_data_2[13]; // @[lib.scala 104:78] + wire _T_680 = _T_676 | _T_679; // @[lib.scala 104:23] + wire _T_682 = &io_trigger_pkt_any_2_tdata2[13:0]; // @[lib.scala 104:36] + wire _T_683 = _T_682 & _T_585; // @[lib.scala 104:41] + wire _T_686 = io_trigger_pkt_any_2_tdata2[14] == lsu_match_data_2[14]; // @[lib.scala 104:78] + wire _T_687 = _T_683 | _T_686; // @[lib.scala 104:23] + wire _T_689 = &io_trigger_pkt_any_2_tdata2[14:0]; // @[lib.scala 104:36] + wire _T_690 = _T_689 & _T_585; // @[lib.scala 104:41] + wire _T_693 = io_trigger_pkt_any_2_tdata2[15] == lsu_match_data_2[15]; // @[lib.scala 104:78] + wire _T_694 = _T_690 | _T_693; // @[lib.scala 104:23] + wire _T_696 = &io_trigger_pkt_any_2_tdata2[15:0]; // @[lib.scala 104:36] + wire _T_697 = _T_696 & _T_585; // @[lib.scala 104:41] + wire _T_700 = io_trigger_pkt_any_2_tdata2[16] == lsu_match_data_2[16]; // @[lib.scala 104:78] + wire _T_701 = _T_697 | _T_700; // @[lib.scala 104:23] + wire _T_703 = &io_trigger_pkt_any_2_tdata2[16:0]; // @[lib.scala 104:36] + wire _T_704 = _T_703 & _T_585; // @[lib.scala 104:41] + wire _T_707 = io_trigger_pkt_any_2_tdata2[17] == lsu_match_data_2[17]; // @[lib.scala 104:78] + wire _T_708 = _T_704 | _T_707; // @[lib.scala 104:23] + wire _T_710 = &io_trigger_pkt_any_2_tdata2[17:0]; // @[lib.scala 104:36] + wire _T_711 = _T_710 & _T_585; // @[lib.scala 104:41] + wire _T_714 = io_trigger_pkt_any_2_tdata2[18] == lsu_match_data_2[18]; // @[lib.scala 104:78] + wire _T_715 = _T_711 | _T_714; // @[lib.scala 104:23] + wire _T_717 = &io_trigger_pkt_any_2_tdata2[18:0]; // @[lib.scala 104:36] + wire _T_718 = _T_717 & _T_585; // @[lib.scala 104:41] + wire _T_721 = io_trigger_pkt_any_2_tdata2[19] == lsu_match_data_2[19]; // @[lib.scala 104:78] + wire _T_722 = _T_718 | _T_721; // @[lib.scala 104:23] + wire _T_724 = &io_trigger_pkt_any_2_tdata2[19:0]; // @[lib.scala 104:36] + wire _T_725 = _T_724 & _T_585; // @[lib.scala 104:41] + wire _T_728 = io_trigger_pkt_any_2_tdata2[20] == lsu_match_data_2[20]; // @[lib.scala 104:78] + wire _T_729 = _T_725 | _T_728; // @[lib.scala 104:23] + wire _T_731 = &io_trigger_pkt_any_2_tdata2[20:0]; // @[lib.scala 104:36] + wire _T_732 = _T_731 & _T_585; // @[lib.scala 104:41] + wire _T_735 = io_trigger_pkt_any_2_tdata2[21] == lsu_match_data_2[21]; // @[lib.scala 104:78] + wire _T_736 = _T_732 | _T_735; // @[lib.scala 104:23] + wire _T_738 = &io_trigger_pkt_any_2_tdata2[21:0]; // @[lib.scala 104:36] + wire _T_739 = _T_738 & _T_585; // @[lib.scala 104:41] + wire _T_742 = io_trigger_pkt_any_2_tdata2[22] == lsu_match_data_2[22]; // @[lib.scala 104:78] + wire _T_743 = _T_739 | _T_742; // @[lib.scala 104:23] + wire _T_745 = &io_trigger_pkt_any_2_tdata2[22:0]; // @[lib.scala 104:36] + wire _T_746 = _T_745 & _T_585; // @[lib.scala 104:41] + wire _T_749 = io_trigger_pkt_any_2_tdata2[23] == lsu_match_data_2[23]; // @[lib.scala 104:78] + wire _T_750 = _T_746 | _T_749; // @[lib.scala 104:23] + wire _T_752 = &io_trigger_pkt_any_2_tdata2[23:0]; // @[lib.scala 104:36] + wire _T_753 = _T_752 & _T_585; // @[lib.scala 104:41] + wire _T_756 = io_trigger_pkt_any_2_tdata2[24] == lsu_match_data_2[24]; // @[lib.scala 104:78] + wire _T_757 = _T_753 | _T_756; // @[lib.scala 104:23] + wire _T_759 = &io_trigger_pkt_any_2_tdata2[24:0]; // @[lib.scala 104:36] + wire _T_760 = _T_759 & _T_585; // @[lib.scala 104:41] + wire _T_763 = io_trigger_pkt_any_2_tdata2[25] == lsu_match_data_2[25]; // @[lib.scala 104:78] + wire _T_764 = _T_760 | _T_763; // @[lib.scala 104:23] + wire _T_766 = &io_trigger_pkt_any_2_tdata2[25:0]; // @[lib.scala 104:36] + wire _T_767 = _T_766 & _T_585; // @[lib.scala 104:41] + wire _T_770 = io_trigger_pkt_any_2_tdata2[26] == lsu_match_data_2[26]; // @[lib.scala 104:78] + wire _T_771 = _T_767 | _T_770; // @[lib.scala 104:23] + wire _T_773 = &io_trigger_pkt_any_2_tdata2[26:0]; // @[lib.scala 104:36] + wire _T_774 = _T_773 & _T_585; // @[lib.scala 104:41] + wire _T_777 = io_trigger_pkt_any_2_tdata2[27] == lsu_match_data_2[27]; // @[lib.scala 104:78] + wire _T_778 = _T_774 | _T_777; // @[lib.scala 104:23] + wire _T_780 = &io_trigger_pkt_any_2_tdata2[27:0]; // @[lib.scala 104:36] + wire _T_781 = _T_780 & _T_585; // @[lib.scala 104:41] + wire _T_784 = io_trigger_pkt_any_2_tdata2[28] == lsu_match_data_2[28]; // @[lib.scala 104:78] + wire _T_785 = _T_781 | _T_784; // @[lib.scala 104:23] + wire _T_787 = &io_trigger_pkt_any_2_tdata2[28:0]; // @[lib.scala 104:36] + wire _T_788 = _T_787 & _T_585; // @[lib.scala 104:41] + wire _T_791 = io_trigger_pkt_any_2_tdata2[29] == lsu_match_data_2[29]; // @[lib.scala 104:78] + wire _T_792 = _T_788 | _T_791; // @[lib.scala 104:23] + wire _T_794 = &io_trigger_pkt_any_2_tdata2[29:0]; // @[lib.scala 104:36] + wire _T_795 = _T_794 & _T_585; // @[lib.scala 104:41] + wire _T_798 = io_trigger_pkt_any_2_tdata2[30] == lsu_match_data_2[30]; // @[lib.scala 104:78] + wire _T_799 = _T_795 | _T_798; // @[lib.scala 104:23] + wire _T_801 = &io_trigger_pkt_any_2_tdata2[30:0]; // @[lib.scala 104:36] + wire _T_802 = _T_801 & _T_585; // @[lib.scala 104:41] + wire _T_805 = io_trigger_pkt_any_2_tdata2[31] == lsu_match_data_2[31]; // @[lib.scala 104:78] + wire _T_806 = _T_802 | _T_805; // @[lib.scala 104:23] + wire [7:0] _T_813 = {_T_638,_T_631,_T_624,_T_617,_T_610,_T_603,_T_596,_T_589}; // @[lib.scala 105:14] + wire [15:0] _T_821 = {_T_694,_T_687,_T_680,_T_673,_T_666,_T_659,_T_652,_T_645,_T_813}; // @[lib.scala 105:14] + wire [7:0] _T_828 = {_T_750,_T_743,_T_736,_T_729,_T_722,_T_715,_T_708,_T_701}; // @[lib.scala 105:14] + wire [31:0] _T_837 = {_T_806,_T_799,_T_792,_T_785,_T_778,_T_771,_T_764,_T_757,_T_828,_T_821}; // @[lib.scala 105:14] + wire _T_838 = &_T_837; // @[lib.scala 105:25] + wire _T_839 = _T_580 & _T_838; // @[lsu_trigger.scala 19:92] + wire _T_842 = io_trigger_pkt_any_3_store & io_lsu_pkt_m_bits_store; // @[lsu_trigger.scala 18:126] + wire _T_843 = io_trigger_pkt_any_3_load & io_lsu_pkt_m_bits_load; // @[lsu_trigger.scala 19:33] + wire _T_845 = _T_843 & _T_33; // @[lsu_trigger.scala 19:58] + wire _T_846 = _T_842 | _T_845; // @[lsu_trigger.scala 18:152] + wire _T_847 = _T_40 & _T_846; // @[lsu_trigger.scala 18:94] + wire _T_850 = &io_trigger_pkt_any_3_tdata2; // @[lib.scala 101:45] + wire _T_851 = ~_T_850; // @[lib.scala 101:39] + wire _T_852 = io_trigger_pkt_any_3_match_pkt & _T_851; // @[lib.scala 101:37] + wire _T_855 = io_trigger_pkt_any_3_tdata2[0] == lsu_match_data_3[0]; // @[lib.scala 102:52] + wire _T_856 = _T_852 | _T_855; // @[lib.scala 102:41] + wire _T_858 = &io_trigger_pkt_any_3_tdata2[0]; // @[lib.scala 104:36] + wire _T_859 = _T_858 & _T_852; // @[lib.scala 104:41] + wire _T_862 = io_trigger_pkt_any_3_tdata2[1] == lsu_match_data_3[1]; // @[lib.scala 104:78] + wire _T_863 = _T_859 | _T_862; // @[lib.scala 104:23] + wire _T_865 = &io_trigger_pkt_any_3_tdata2[1:0]; // @[lib.scala 104:36] + wire _T_866 = _T_865 & _T_852; // @[lib.scala 104:41] + wire _T_869 = io_trigger_pkt_any_3_tdata2[2] == lsu_match_data_3[2]; // @[lib.scala 104:78] + wire _T_870 = _T_866 | _T_869; // @[lib.scala 104:23] + wire _T_872 = &io_trigger_pkt_any_3_tdata2[2:0]; // @[lib.scala 104:36] + wire _T_873 = _T_872 & _T_852; // @[lib.scala 104:41] + wire _T_876 = io_trigger_pkt_any_3_tdata2[3] == lsu_match_data_3[3]; // @[lib.scala 104:78] + wire _T_877 = _T_873 | _T_876; // @[lib.scala 104:23] + wire _T_879 = &io_trigger_pkt_any_3_tdata2[3:0]; // @[lib.scala 104:36] + wire _T_880 = _T_879 & _T_852; // @[lib.scala 104:41] + wire _T_883 = io_trigger_pkt_any_3_tdata2[4] == lsu_match_data_3[4]; // @[lib.scala 104:78] + wire _T_884 = _T_880 | _T_883; // @[lib.scala 104:23] + wire _T_886 = &io_trigger_pkt_any_3_tdata2[4:0]; // @[lib.scala 104:36] + wire _T_887 = _T_886 & _T_852; // @[lib.scala 104:41] + wire _T_890 = io_trigger_pkt_any_3_tdata2[5] == lsu_match_data_3[5]; // @[lib.scala 104:78] + wire _T_891 = _T_887 | _T_890; // @[lib.scala 104:23] + wire _T_893 = &io_trigger_pkt_any_3_tdata2[5:0]; // @[lib.scala 104:36] + wire _T_894 = _T_893 & _T_852; // @[lib.scala 104:41] + wire _T_897 = io_trigger_pkt_any_3_tdata2[6] == lsu_match_data_3[6]; // @[lib.scala 104:78] + wire _T_898 = _T_894 | _T_897; // @[lib.scala 104:23] + wire _T_900 = &io_trigger_pkt_any_3_tdata2[6:0]; // @[lib.scala 104:36] + wire _T_901 = _T_900 & _T_852; // @[lib.scala 104:41] + wire _T_904 = io_trigger_pkt_any_3_tdata2[7] == lsu_match_data_3[7]; // @[lib.scala 104:78] + wire _T_905 = _T_901 | _T_904; // @[lib.scala 104:23] + wire _T_907 = &io_trigger_pkt_any_3_tdata2[7:0]; // @[lib.scala 104:36] + wire _T_908 = _T_907 & _T_852; // @[lib.scala 104:41] + wire _T_911 = io_trigger_pkt_any_3_tdata2[8] == lsu_match_data_3[8]; // @[lib.scala 104:78] + wire _T_912 = _T_908 | _T_911; // @[lib.scala 104:23] + wire _T_914 = &io_trigger_pkt_any_3_tdata2[8:0]; // @[lib.scala 104:36] + wire _T_915 = _T_914 & _T_852; // @[lib.scala 104:41] + wire _T_918 = io_trigger_pkt_any_3_tdata2[9] == lsu_match_data_3[9]; // @[lib.scala 104:78] + wire _T_919 = _T_915 | _T_918; // @[lib.scala 104:23] + wire _T_921 = &io_trigger_pkt_any_3_tdata2[9:0]; // @[lib.scala 104:36] + wire _T_922 = _T_921 & _T_852; // @[lib.scala 104:41] + wire _T_925 = io_trigger_pkt_any_3_tdata2[10] == lsu_match_data_3[10]; // @[lib.scala 104:78] + wire _T_926 = _T_922 | _T_925; // @[lib.scala 104:23] + wire _T_928 = &io_trigger_pkt_any_3_tdata2[10:0]; // @[lib.scala 104:36] + wire _T_929 = _T_928 & _T_852; // @[lib.scala 104:41] + wire _T_932 = io_trigger_pkt_any_3_tdata2[11] == lsu_match_data_3[11]; // @[lib.scala 104:78] + wire _T_933 = _T_929 | _T_932; // @[lib.scala 104:23] + wire _T_935 = &io_trigger_pkt_any_3_tdata2[11:0]; // @[lib.scala 104:36] + wire _T_936 = _T_935 & _T_852; // @[lib.scala 104:41] + wire _T_939 = io_trigger_pkt_any_3_tdata2[12] == lsu_match_data_3[12]; // @[lib.scala 104:78] + wire _T_940 = _T_936 | _T_939; // @[lib.scala 104:23] + wire _T_942 = &io_trigger_pkt_any_3_tdata2[12:0]; // @[lib.scala 104:36] + wire _T_943 = _T_942 & _T_852; // @[lib.scala 104:41] + wire _T_946 = io_trigger_pkt_any_3_tdata2[13] == lsu_match_data_3[13]; // @[lib.scala 104:78] + wire _T_947 = _T_943 | _T_946; // @[lib.scala 104:23] + wire _T_949 = &io_trigger_pkt_any_3_tdata2[13:0]; // @[lib.scala 104:36] + wire _T_950 = _T_949 & _T_852; // @[lib.scala 104:41] + wire _T_953 = io_trigger_pkt_any_3_tdata2[14] == lsu_match_data_3[14]; // @[lib.scala 104:78] + wire _T_954 = _T_950 | _T_953; // @[lib.scala 104:23] + wire _T_956 = &io_trigger_pkt_any_3_tdata2[14:0]; // @[lib.scala 104:36] + wire _T_957 = _T_956 & _T_852; // @[lib.scala 104:41] + wire _T_960 = io_trigger_pkt_any_3_tdata2[15] == lsu_match_data_3[15]; // @[lib.scala 104:78] + wire _T_961 = _T_957 | _T_960; // @[lib.scala 104:23] + wire _T_963 = &io_trigger_pkt_any_3_tdata2[15:0]; // @[lib.scala 104:36] + wire _T_964 = _T_963 & _T_852; // @[lib.scala 104:41] + wire _T_967 = io_trigger_pkt_any_3_tdata2[16] == lsu_match_data_3[16]; // @[lib.scala 104:78] + wire _T_968 = _T_964 | _T_967; // @[lib.scala 104:23] + wire _T_970 = &io_trigger_pkt_any_3_tdata2[16:0]; // @[lib.scala 104:36] + wire _T_971 = _T_970 & _T_852; // @[lib.scala 104:41] + wire _T_974 = io_trigger_pkt_any_3_tdata2[17] == lsu_match_data_3[17]; // @[lib.scala 104:78] + wire _T_975 = _T_971 | _T_974; // @[lib.scala 104:23] + wire _T_977 = &io_trigger_pkt_any_3_tdata2[17:0]; // @[lib.scala 104:36] + wire _T_978 = _T_977 & _T_852; // @[lib.scala 104:41] + wire _T_981 = io_trigger_pkt_any_3_tdata2[18] == lsu_match_data_3[18]; // @[lib.scala 104:78] + wire _T_982 = _T_978 | _T_981; // @[lib.scala 104:23] + wire _T_984 = &io_trigger_pkt_any_3_tdata2[18:0]; // @[lib.scala 104:36] + wire _T_985 = _T_984 & _T_852; // @[lib.scala 104:41] + wire _T_988 = io_trigger_pkt_any_3_tdata2[19] == lsu_match_data_3[19]; // @[lib.scala 104:78] + wire _T_989 = _T_985 | _T_988; // @[lib.scala 104:23] + wire _T_991 = &io_trigger_pkt_any_3_tdata2[19:0]; // @[lib.scala 104:36] + wire _T_992 = _T_991 & _T_852; // @[lib.scala 104:41] + wire _T_995 = io_trigger_pkt_any_3_tdata2[20] == lsu_match_data_3[20]; // @[lib.scala 104:78] + wire _T_996 = _T_992 | _T_995; // @[lib.scala 104:23] + wire _T_998 = &io_trigger_pkt_any_3_tdata2[20:0]; // @[lib.scala 104:36] + wire _T_999 = _T_998 & _T_852; // @[lib.scala 104:41] + wire _T_1002 = io_trigger_pkt_any_3_tdata2[21] == lsu_match_data_3[21]; // @[lib.scala 104:78] + wire _T_1003 = _T_999 | _T_1002; // @[lib.scala 104:23] + wire _T_1005 = &io_trigger_pkt_any_3_tdata2[21:0]; // @[lib.scala 104:36] + wire _T_1006 = _T_1005 & _T_852; // @[lib.scala 104:41] + wire _T_1009 = io_trigger_pkt_any_3_tdata2[22] == lsu_match_data_3[22]; // @[lib.scala 104:78] + wire _T_1010 = _T_1006 | _T_1009; // @[lib.scala 104:23] + wire _T_1012 = &io_trigger_pkt_any_3_tdata2[22:0]; // @[lib.scala 104:36] + wire _T_1013 = _T_1012 & _T_852; // @[lib.scala 104:41] + wire _T_1016 = io_trigger_pkt_any_3_tdata2[23] == lsu_match_data_3[23]; // @[lib.scala 104:78] + wire _T_1017 = _T_1013 | _T_1016; // @[lib.scala 104:23] + wire _T_1019 = &io_trigger_pkt_any_3_tdata2[23:0]; // @[lib.scala 104:36] + wire _T_1020 = _T_1019 & _T_852; // @[lib.scala 104:41] + wire _T_1023 = io_trigger_pkt_any_3_tdata2[24] == lsu_match_data_3[24]; // @[lib.scala 104:78] + wire _T_1024 = _T_1020 | _T_1023; // @[lib.scala 104:23] + wire _T_1026 = &io_trigger_pkt_any_3_tdata2[24:0]; // @[lib.scala 104:36] + wire _T_1027 = _T_1026 & _T_852; // @[lib.scala 104:41] + wire _T_1030 = io_trigger_pkt_any_3_tdata2[25] == lsu_match_data_3[25]; // @[lib.scala 104:78] + wire _T_1031 = _T_1027 | _T_1030; // @[lib.scala 104:23] + wire _T_1033 = &io_trigger_pkt_any_3_tdata2[25:0]; // @[lib.scala 104:36] + wire _T_1034 = _T_1033 & _T_852; // @[lib.scala 104:41] + wire _T_1037 = io_trigger_pkt_any_3_tdata2[26] == lsu_match_data_3[26]; // @[lib.scala 104:78] + wire _T_1038 = _T_1034 | _T_1037; // @[lib.scala 104:23] + wire _T_1040 = &io_trigger_pkt_any_3_tdata2[26:0]; // @[lib.scala 104:36] + wire _T_1041 = _T_1040 & _T_852; // @[lib.scala 104:41] + wire _T_1044 = io_trigger_pkt_any_3_tdata2[27] == lsu_match_data_3[27]; // @[lib.scala 104:78] + wire _T_1045 = _T_1041 | _T_1044; // @[lib.scala 104:23] + wire _T_1047 = &io_trigger_pkt_any_3_tdata2[27:0]; // @[lib.scala 104:36] + wire _T_1048 = _T_1047 & _T_852; // @[lib.scala 104:41] + wire _T_1051 = io_trigger_pkt_any_3_tdata2[28] == lsu_match_data_3[28]; // @[lib.scala 104:78] + wire _T_1052 = _T_1048 | _T_1051; // @[lib.scala 104:23] + wire _T_1054 = &io_trigger_pkt_any_3_tdata2[28:0]; // @[lib.scala 104:36] + wire _T_1055 = _T_1054 & _T_852; // @[lib.scala 104:41] + wire _T_1058 = io_trigger_pkt_any_3_tdata2[29] == lsu_match_data_3[29]; // @[lib.scala 104:78] + wire _T_1059 = _T_1055 | _T_1058; // @[lib.scala 104:23] + wire _T_1061 = &io_trigger_pkt_any_3_tdata2[29:0]; // @[lib.scala 104:36] + wire _T_1062 = _T_1061 & _T_852; // @[lib.scala 104:41] + wire _T_1065 = io_trigger_pkt_any_3_tdata2[30] == lsu_match_data_3[30]; // @[lib.scala 104:78] + wire _T_1066 = _T_1062 | _T_1065; // @[lib.scala 104:23] + wire _T_1068 = &io_trigger_pkt_any_3_tdata2[30:0]; // @[lib.scala 104:36] + wire _T_1069 = _T_1068 & _T_852; // @[lib.scala 104:41] + wire _T_1072 = io_trigger_pkt_any_3_tdata2[31] == lsu_match_data_3[31]; // @[lib.scala 104:78] + wire _T_1073 = _T_1069 | _T_1072; // @[lib.scala 104:23] + wire [7:0] _T_1080 = {_T_905,_T_898,_T_891,_T_884,_T_877,_T_870,_T_863,_T_856}; // @[lib.scala 105:14] + wire [15:0] _T_1088 = {_T_961,_T_954,_T_947,_T_940,_T_933,_T_926,_T_919,_T_912,_T_1080}; // @[lib.scala 105:14] + wire [7:0] _T_1095 = {_T_1017,_T_1010,_T_1003,_T_996,_T_989,_T_982,_T_975,_T_968}; // @[lib.scala 105:14] + wire [31:0] _T_1104 = {_T_1073,_T_1066,_T_1059,_T_1052,_T_1045,_T_1038,_T_1031,_T_1024,_T_1095,_T_1088}; // @[lib.scala 105:14] + wire _T_1105 = &_T_1104; // @[lib.scala 105:25] + wire _T_1106 = _T_847 & _T_1105; // @[lsu_trigger.scala 19:92] + wire [2:0] _T_1108 = {_T_1106,_T_839,_T_572}; // @[Cat.scala 29:58] + assign io_lsu_trigger_match_m = {_T_1108,_T_305}; // @[lsu_trigger.scala 18:26] +endmodule +module lsu_clkdomain( + input clock, + input reset, + input io_free_clk, + input io_clk_override, + input io_dma_dccm_req, + input io_ldst_stbuf_reqvld_r, + input io_stbuf_reqvld_any, + input io_stbuf_reqvld_flushed_any, + input io_lsu_busreq_r, + input io_lsu_bus_buffer_pend_any, + input io_lsu_bus_buffer_empty_any, + input io_lsu_stbuf_empty_any, + input io_lsu_bus_clk_en, + input io_lsu_p_valid, + input io_lsu_pkt_d_valid, + input io_lsu_pkt_d_bits_store, + input io_lsu_pkt_m_valid, + input io_lsu_pkt_m_bits_store, + input io_lsu_pkt_r_valid, + output io_lsu_c1_m_clk, + output io_lsu_c1_r_clk, + output io_lsu_c2_m_clk, + output io_lsu_c2_r_clk, + output io_lsu_store_c1_m_clk, + output io_lsu_store_c1_r_clk, + output io_lsu_stbuf_c1_clk, + output io_lsu_bus_obuf_c1_clk, + output io_lsu_bus_ibuf_c1_clk, + output io_lsu_bus_buf_c1_clk, + output io_lsu_busm_clk, + output io_lsu_free_c2_clk, + input io_scan_mode +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_io_en; // @[lib.scala 343:22] + wire rvclkhdr_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_1_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_1_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_1_io_en; // @[lib.scala 343:22] + wire rvclkhdr_1_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_2_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_2_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_2_io_en; // @[lib.scala 343:22] + wire rvclkhdr_2_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_3_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_3_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_3_io_en; // @[lib.scala 343:22] + wire rvclkhdr_3_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_4_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_4_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_4_io_en; // @[lib.scala 343:22] + wire rvclkhdr_4_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_5_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_5_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_5_io_en; // @[lib.scala 343:22] + wire rvclkhdr_5_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_6_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_6_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_6_io_en; // @[lib.scala 343:22] + wire rvclkhdr_6_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_7_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_7_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_7_io_en; // @[lib.scala 343:22] + wire rvclkhdr_7_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_8_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_8_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_8_io_en; // @[lib.scala 343:22] + wire rvclkhdr_8_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_9_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_9_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_9_io_en; // @[lib.scala 343:22] + wire rvclkhdr_9_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_10_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_10_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_10_io_en; // @[lib.scala 343:22] + wire rvclkhdr_10_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_11_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_11_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_11_io_en; // @[lib.scala 343:22] + wire rvclkhdr_11_io_scan_mode; // @[lib.scala 343:22] + wire _T = io_lsu_p_valid | io_dma_dccm_req; // @[lsu_clkdomain.scala 62:51] + reg lsu_c1_d_clken_q; // @[lsu_clkdomain.scala 81:67] + wire _T_1 = io_lsu_pkt_d_valid | lsu_c1_d_clken_q; // @[lsu_clkdomain.scala 63:51] + wire lsu_c1_m_clken = _T_1 | io_clk_override; // @[lsu_clkdomain.scala 63:70] + reg lsu_c1_m_clken_q; // @[lsu_clkdomain.scala 82:67] + wire _T_2 = io_lsu_pkt_m_valid | lsu_c1_m_clken_q; // @[lsu_clkdomain.scala 64:51] + wire lsu_c1_r_clken = _T_2 | io_clk_override; // @[lsu_clkdomain.scala 64:70] + wire _T_3 = lsu_c1_m_clken | lsu_c1_m_clken_q; // @[lsu_clkdomain.scala 66:47] + reg lsu_c1_r_clken_q; // @[lsu_clkdomain.scala 83:67] + wire _T_4 = lsu_c1_r_clken | lsu_c1_r_clken_q; // @[lsu_clkdomain.scala 67:47] + wire _T_5 = lsu_c1_m_clken & io_lsu_pkt_d_bits_store; // @[lsu_clkdomain.scala 69:49] + wire _T_6 = lsu_c1_r_clken & io_lsu_pkt_m_bits_store; // @[lsu_clkdomain.scala 70:49] + wire _T_7 = io_ldst_stbuf_reqvld_r | io_stbuf_reqvld_any; // @[lsu_clkdomain.scala 71:55] + wire _T_8 = _T_7 | io_stbuf_reqvld_flushed_any; // @[lsu_clkdomain.scala 71:77] + wire _T_9 = io_lsu_bus_buffer_pend_any | io_lsu_busreq_r; // @[lsu_clkdomain.scala 73:61] + wire _T_10 = _T_9 | io_clk_override; // @[lsu_clkdomain.scala 73:79] + wire _T_11 = ~io_lsu_bus_buffer_empty_any; // @[lsu_clkdomain.scala 74:32] + wire _T_12 = _T_11 | io_lsu_busreq_r; // @[lsu_clkdomain.scala 74:61] + wire _T_13 = io_lsu_p_valid | io_lsu_pkt_d_valid; // @[lsu_clkdomain.scala 76:48] + wire _T_14 = _T_13 | io_lsu_pkt_m_valid; // @[lsu_clkdomain.scala 76:69] + wire _T_15 = _T_14 | io_lsu_pkt_r_valid; // @[lsu_clkdomain.scala 76:90] + wire _T_17 = _T_15 | _T_11; // @[lsu_clkdomain.scala 76:112] + wire _T_18 = ~io_lsu_stbuf_empty_any; // @[lsu_clkdomain.scala 76:145] + wire _T_19 = _T_17 | _T_18; // @[lsu_clkdomain.scala 76:143] + wire lsu_free_c1_clken = _T_19 | io_clk_override; // @[lsu_clkdomain.scala 76:169] + reg lsu_free_c1_clken_q; // @[lsu_clkdomain.scala 80:60] + wire _T_20 = lsu_free_c1_clken | lsu_free_c1_clken_q; // @[lsu_clkdomain.scala 77:50] + rvclkhdr rvclkhdr ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) + ); + rvclkhdr rvclkhdr_1 ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_1_io_l1clk), + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en), + .io_scan_mode(rvclkhdr_1_io_scan_mode) + ); + rvclkhdr rvclkhdr_2 ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_2_io_l1clk), + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en), + .io_scan_mode(rvclkhdr_2_io_scan_mode) + ); + rvclkhdr rvclkhdr_3 ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_3_io_l1clk), + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en), + .io_scan_mode(rvclkhdr_3_io_scan_mode) + ); + rvclkhdr rvclkhdr_4 ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_4_io_l1clk), + .io_clk(rvclkhdr_4_io_clk), + .io_en(rvclkhdr_4_io_en), + .io_scan_mode(rvclkhdr_4_io_scan_mode) + ); + rvclkhdr rvclkhdr_5 ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_5_io_l1clk), + .io_clk(rvclkhdr_5_io_clk), + .io_en(rvclkhdr_5_io_en), + .io_scan_mode(rvclkhdr_5_io_scan_mode) + ); + rvclkhdr rvclkhdr_6 ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_6_io_l1clk), + .io_clk(rvclkhdr_6_io_clk), + .io_en(rvclkhdr_6_io_en), + .io_scan_mode(rvclkhdr_6_io_scan_mode) + ); + rvclkhdr rvclkhdr_7 ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_7_io_l1clk), + .io_clk(rvclkhdr_7_io_clk), + .io_en(rvclkhdr_7_io_en), + .io_scan_mode(rvclkhdr_7_io_scan_mode) + ); + rvclkhdr rvclkhdr_8 ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_8_io_l1clk), + .io_clk(rvclkhdr_8_io_clk), + .io_en(rvclkhdr_8_io_en), + .io_scan_mode(rvclkhdr_8_io_scan_mode) + ); + rvclkhdr rvclkhdr_9 ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_9_io_l1clk), + .io_clk(rvclkhdr_9_io_clk), + .io_en(rvclkhdr_9_io_en), + .io_scan_mode(rvclkhdr_9_io_scan_mode) + ); + rvclkhdr rvclkhdr_10 ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_10_io_l1clk), + .io_clk(rvclkhdr_10_io_clk), + .io_en(rvclkhdr_10_io_en), + .io_scan_mode(rvclkhdr_10_io_scan_mode) + ); + rvclkhdr rvclkhdr_11 ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_11_io_l1clk), + .io_clk(rvclkhdr_11_io_clk), + .io_en(rvclkhdr_11_io_en), + .io_scan_mode(rvclkhdr_11_io_scan_mode) + ); + assign io_lsu_c1_m_clk = rvclkhdr_io_l1clk; // @[lsu_clkdomain.scala 85:26] + assign io_lsu_c1_r_clk = rvclkhdr_1_io_l1clk; // @[lsu_clkdomain.scala 86:26] + assign io_lsu_c2_m_clk = rvclkhdr_2_io_l1clk; // @[lsu_clkdomain.scala 87:26] + assign io_lsu_c2_r_clk = rvclkhdr_3_io_l1clk; // @[lsu_clkdomain.scala 88:26] + assign io_lsu_store_c1_m_clk = rvclkhdr_4_io_l1clk; // @[lsu_clkdomain.scala 89:26] + assign io_lsu_store_c1_r_clk = rvclkhdr_5_io_l1clk; // @[lsu_clkdomain.scala 90:26] + assign io_lsu_stbuf_c1_clk = rvclkhdr_6_io_l1clk; // @[lsu_clkdomain.scala 91:26] + assign io_lsu_bus_obuf_c1_clk = rvclkhdr_8_io_l1clk; // @[lsu_clkdomain.scala 93:26] + assign io_lsu_bus_ibuf_c1_clk = rvclkhdr_7_io_l1clk; // @[lsu_clkdomain.scala 92:26] + assign io_lsu_bus_buf_c1_clk = rvclkhdr_9_io_l1clk; // @[lsu_clkdomain.scala 94:26] + assign io_lsu_busm_clk = rvclkhdr_10_io_l1clk; // @[lsu_clkdomain.scala 95:26] + assign io_lsu_free_c2_clk = rvclkhdr_11_io_l1clk; // @[lsu_clkdomain.scala 96:26] + assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_io_en = _T_1 | io_clk_override; // @[lib.scala 345:16] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_1_io_en = _T_2 | io_clk_override; // @[lib.scala 345:16] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_2_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_2_io_en = _T_3 | io_clk_override; // @[lib.scala 345:16] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_3_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_3_io_en = _T_4 | io_clk_override; // @[lib.scala 345:16] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_4_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_4_io_en = _T_5 | io_clk_override; // @[lib.scala 345:16] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_5_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_5_io_en = _T_6 | io_clk_override; // @[lib.scala 345:16] + assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_6_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_6_io_en = _T_8 | io_clk_override; // @[lib.scala 345:16] + assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_7_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_7_io_en = io_lsu_busreq_r | io_clk_override; // @[lib.scala 345:16] + assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_8_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_8_io_en = _T_10 & io_lsu_bus_clk_en; // @[lib.scala 345:16] + assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_9_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_9_io_en = _T_12 | io_clk_override; // @[lib.scala 345:16] + assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_10_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_10_io_en = io_lsu_bus_clk_en; // @[lib.scala 345:16] + assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_11_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_11_io_en = _T_20 | io_clk_override; // @[lib.scala 345:16] + assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + lsu_c1_d_clken_q = _RAND_0[0:0]; + _RAND_1 = {1{`RANDOM}}; + lsu_c1_m_clken_q = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + lsu_c1_r_clken_q = _RAND_2[0:0]; + _RAND_3 = {1{`RANDOM}}; + lsu_free_c1_clken_q = _RAND_3[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + lsu_c1_d_clken_q = 1'h0; + end + if (reset) begin + lsu_c1_m_clken_q = 1'h0; + end + if (reset) begin + lsu_c1_r_clken_q = 1'h0; + end + if (reset) begin + lsu_free_c1_clken_q = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + lsu_c1_d_clken_q <= 1'h0; + end else begin + lsu_c1_d_clken_q <= _T | io_clk_override; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + lsu_c1_m_clken_q <= 1'h0; + end else begin + lsu_c1_m_clken_q <= _T_1 | io_clk_override; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + lsu_c1_r_clken_q <= 1'h0; + end else begin + lsu_c1_r_clken_q <= _T_2 | io_clk_override; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + lsu_free_c1_clken_q <= 1'h0; + end else begin + lsu_free_c1_clken_q <= _T_19 | io_clk_override; + end + end +endmodule +module lsu_bus_buffer( + input clock, + input reset, + input io_scan_mode, + output io_tlu_busbuff_lsu_pmu_bus_trxn, + output io_tlu_busbuff_lsu_pmu_bus_misaligned, + output io_tlu_busbuff_lsu_pmu_bus_error, + output io_tlu_busbuff_lsu_pmu_bus_busy, + input io_tlu_busbuff_dec_tlu_external_ldfwd_disable, + input io_tlu_busbuff_dec_tlu_wb_coalescing_disable, + input io_tlu_busbuff_dec_tlu_sideeffect_posted_disable, + output io_tlu_busbuff_lsu_imprecise_error_load_any, + output io_tlu_busbuff_lsu_imprecise_error_store_any, + output [31:0] io_tlu_busbuff_lsu_imprecise_error_addr_any, + output io_dctl_busbuff_lsu_nonblock_load_valid_m, + output [1:0] io_dctl_busbuff_lsu_nonblock_load_tag_m, + output io_dctl_busbuff_lsu_nonblock_load_inv_r, + output [1:0] io_dctl_busbuff_lsu_nonblock_load_inv_tag_r, + output io_dctl_busbuff_lsu_nonblock_load_data_valid, + output io_dctl_busbuff_lsu_nonblock_load_data_error, + output [1:0] io_dctl_busbuff_lsu_nonblock_load_data_tag, + output [31:0] io_dctl_busbuff_lsu_nonblock_load_data, + input io_dec_tlu_force_halt, + input io_lsu_c2_r_clk, + input io_lsu_bus_ibuf_c1_clk, + input io_lsu_bus_obuf_c1_clk, + input io_lsu_bus_buf_c1_clk, + input io_lsu_free_c2_clk, + input io_lsu_busm_clk, + input io_dec_lsu_valid_raw_d, + input io_lsu_pkt_m_valid, + input io_lsu_pkt_m_bits_load, + input io_lsu_pkt_r_bits_by, + input io_lsu_pkt_r_bits_half, + input io_lsu_pkt_r_bits_word, + input io_lsu_pkt_r_bits_load, + input io_lsu_pkt_r_bits_store, + input io_lsu_pkt_r_bits_unsign, + input [31:0] io_lsu_addr_m, + input [31:0] io_end_addr_m, + input [31:0] io_lsu_addr_r, + input [31:0] io_end_addr_r, + input [31:0] io_store_data_r, + input io_no_word_merge_r, + input io_no_dword_merge_r, + input io_lsu_busreq_m, + input io_ld_full_hit_m, + input io_flush_m_up, + input io_flush_r, + input io_lsu_commit_r, + input io_is_sideeffects_r, + input io_ldst_dual_d, + input io_ldst_dual_m, + input io_ldst_dual_r, + input [7:0] io_ldst_byteen_ext_m, + input io_lsu_axi_aw_ready, + output io_lsu_axi_aw_valid, + output [2:0] io_lsu_axi_aw_bits_id, + output [31:0] io_lsu_axi_aw_bits_addr, + output [3:0] io_lsu_axi_aw_bits_region, + output [2:0] io_lsu_axi_aw_bits_size, + output [3:0] io_lsu_axi_aw_bits_cache, + input io_lsu_axi_w_ready, + output io_lsu_axi_w_valid, + output [63:0] io_lsu_axi_w_bits_data, + output [7:0] io_lsu_axi_w_bits_strb, + output io_lsu_axi_b_ready, + input io_lsu_axi_b_valid, + input [1:0] io_lsu_axi_b_bits_resp, + input [2:0] io_lsu_axi_b_bits_id, + input io_lsu_axi_ar_ready, + output io_lsu_axi_ar_valid, + output [2:0] io_lsu_axi_ar_bits_id, + output [31:0] io_lsu_axi_ar_bits_addr, + output [3:0] io_lsu_axi_ar_bits_region, + output [2:0] io_lsu_axi_ar_bits_size, + output [3:0] io_lsu_axi_ar_bits_cache, + output io_lsu_axi_r_ready, + input io_lsu_axi_r_valid, + input [2:0] io_lsu_axi_r_bits_id, + input [63:0] io_lsu_axi_r_bits_data, + input [1:0] io_lsu_axi_r_bits_resp, + input io_lsu_bus_clk_en, + input io_lsu_bus_clk_en_q, + output io_lsu_busreq_r, + output io_lsu_bus_buffer_pend_any, + output io_lsu_bus_buffer_full_any, + output io_lsu_bus_buffer_empty_any, + output [3:0] io_ld_byte_hit_buf_lo, + output [3:0] io_ld_byte_hit_buf_hi, + output [31:0] io_ld_fwddata_buf_lo, + output [31:0] io_ld_fwddata_buf_hi +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; + reg [31:0] _RAND_15; + reg [31:0] _RAND_16; + reg [31:0] _RAND_17; + reg [31:0] _RAND_18; + reg [31:0] _RAND_19; + reg [31:0] _RAND_20; + reg [31:0] _RAND_21; + reg [31:0] _RAND_22; + reg [31:0] _RAND_23; + reg [31:0] _RAND_24; + reg [31:0] _RAND_25; + reg [31:0] _RAND_26; + reg [31:0] _RAND_27; + reg [31:0] _RAND_28; + reg [31:0] _RAND_29; + reg [31:0] _RAND_30; + reg [31:0] _RAND_31; + reg [31:0] _RAND_32; + reg [31:0] _RAND_33; + reg [31:0] _RAND_34; + reg [31:0] _RAND_35; + reg [31:0] _RAND_36; + reg [31:0] _RAND_37; + reg [31:0] _RAND_38; + reg [31:0] _RAND_39; + reg [31:0] _RAND_40; + reg [31:0] _RAND_41; + reg [31:0] _RAND_42; + reg [31:0] _RAND_43; + reg [31:0] _RAND_44; + reg [31:0] _RAND_45; + reg [31:0] _RAND_46; + reg [31:0] _RAND_47; + reg [31:0] _RAND_48; + reg [31:0] _RAND_49; + reg [31:0] _RAND_50; + reg [31:0] _RAND_51; + reg [31:0] _RAND_52; + reg [31:0] _RAND_53; + reg [31:0] _RAND_54; + reg [31:0] _RAND_55; + reg [31:0] _RAND_56; + reg [31:0] _RAND_57; + reg [31:0] _RAND_58; + reg [31:0] _RAND_59; + reg [31:0] _RAND_60; + reg [31:0] _RAND_61; + reg [31:0] _RAND_62; + reg [31:0] _RAND_63; + reg [31:0] _RAND_64; + reg [31:0] _RAND_65; + reg [31:0] _RAND_66; + reg [31:0] _RAND_67; + reg [31:0] _RAND_68; + reg [31:0] _RAND_69; + reg [31:0] _RAND_70; + reg [31:0] _RAND_71; + reg [31:0] _RAND_72; + reg [31:0] _RAND_73; + reg [31:0] _RAND_74; + reg [31:0] _RAND_75; + reg [31:0] _RAND_76; + reg [31:0] _RAND_77; + reg [31:0] _RAND_78; + reg [31:0] _RAND_79; + reg [63:0] _RAND_80; + reg [31:0] _RAND_81; + reg [31:0] _RAND_82; + reg [31:0] _RAND_83; + reg [31:0] _RAND_84; + reg [31:0] _RAND_85; + reg [31:0] _RAND_86; + reg [31:0] _RAND_87; + reg [31:0] _RAND_88; + reg [31:0] _RAND_89; + reg [31:0] _RAND_90; + reg [31:0] _RAND_91; + reg [31:0] _RAND_92; + reg [31:0] _RAND_93; + reg [31:0] _RAND_94; + reg [31:0] _RAND_95; + reg [31:0] _RAND_96; + reg [31:0] _RAND_97; + reg [31:0] _RAND_98; + reg [31:0] _RAND_99; + reg [31:0] _RAND_100; + reg [31:0] _RAND_101; + reg [31:0] _RAND_102; + reg [31:0] _RAND_103; + reg [31:0] _RAND_104; + reg [31:0] _RAND_105; + reg [31:0] _RAND_106; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_io_en; // @[lib.scala 368:23] + wire rvclkhdr_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_1_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_1_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_1_io_en; // @[lib.scala 368:23] + wire rvclkhdr_1_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_2_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_2_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_2_io_en; // @[lib.scala 368:23] + wire rvclkhdr_2_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_3_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_3_io_en; // @[lib.scala 368:23] + wire rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_4_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_4_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_4_io_en; // @[lib.scala 368:23] + wire rvclkhdr_4_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_5_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_5_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_5_io_en; // @[lib.scala 368:23] + wire rvclkhdr_5_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_6_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_6_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_6_io_en; // @[lib.scala 368:23] + wire rvclkhdr_6_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_7_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_7_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_7_io_en; // @[lib.scala 368:23] + wire rvclkhdr_7_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_8_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_8_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_8_io_en; // @[lib.scala 368:23] + wire rvclkhdr_8_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_9_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_9_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_9_io_en; // @[lib.scala 368:23] + wire rvclkhdr_9_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_10_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_10_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_10_io_en; // @[lib.scala 368:23] + wire rvclkhdr_10_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_11_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_11_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_11_io_en; // @[lib.scala 368:23] + wire rvclkhdr_11_io_scan_mode; // @[lib.scala 368:23] + wire [3:0] ldst_byteen_hi_m = io_ldst_byteen_ext_m[7:4]; // @[lsu_bus_buffer.scala 73:46] + wire [3:0] ldst_byteen_lo_m = io_ldst_byteen_ext_m[3:0]; // @[lsu_bus_buffer.scala 74:46] + reg [31:0] buf_addr_0; // @[lib.scala 374:16] + wire _T_2 = io_lsu_addr_m[31:2] == buf_addr_0[31:2]; // @[lsu_bus_buffer.scala 76:74] + reg _T_4360; // @[Reg.scala 27:20] + reg _T_4357; // @[Reg.scala 27:20] + reg _T_4354; // @[Reg.scala 27:20] + reg _T_4351; // @[Reg.scala 27:20] + wire [3:0] buf_write = {_T_4360,_T_4357,_T_4354,_T_4351}; // @[Cat.scala 29:58] + wire _T_4 = _T_2 & buf_write[0]; // @[lsu_bus_buffer.scala 76:98] + reg [2:0] buf_state_0; // @[Reg.scala 27:20] + wire _T_5 = buf_state_0 != 3'h0; // @[lsu_bus_buffer.scala 76:129] + wire _T_6 = _T_4 & _T_5; // @[lsu_bus_buffer.scala 76:113] + wire ld_addr_hitvec_lo_0 = _T_6 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 76:141] + reg [31:0] buf_addr_1; // @[lib.scala 374:16] + wire _T_9 = io_lsu_addr_m[31:2] == buf_addr_1[31:2]; // @[lsu_bus_buffer.scala 76:74] + wire _T_11 = _T_9 & buf_write[1]; // @[lsu_bus_buffer.scala 76:98] + reg [2:0] buf_state_1; // @[Reg.scala 27:20] + wire _T_12 = buf_state_1 != 3'h0; // @[lsu_bus_buffer.scala 76:129] + wire _T_13 = _T_11 & _T_12; // @[lsu_bus_buffer.scala 76:113] + wire ld_addr_hitvec_lo_1 = _T_13 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 76:141] + reg [31:0] buf_addr_2; // @[lib.scala 374:16] + wire _T_16 = io_lsu_addr_m[31:2] == buf_addr_2[31:2]; // @[lsu_bus_buffer.scala 76:74] + wire _T_18 = _T_16 & buf_write[2]; // @[lsu_bus_buffer.scala 76:98] + reg [2:0] buf_state_2; // @[Reg.scala 27:20] + wire _T_19 = buf_state_2 != 3'h0; // @[lsu_bus_buffer.scala 76:129] + wire _T_20 = _T_18 & _T_19; // @[lsu_bus_buffer.scala 76:113] + wire ld_addr_hitvec_lo_2 = _T_20 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 76:141] + reg [31:0] buf_addr_3; // @[lib.scala 374:16] + wire _T_23 = io_lsu_addr_m[31:2] == buf_addr_3[31:2]; // @[lsu_bus_buffer.scala 76:74] + wire _T_25 = _T_23 & buf_write[3]; // @[lsu_bus_buffer.scala 76:98] + reg [2:0] buf_state_3; // @[Reg.scala 27:20] + wire _T_26 = buf_state_3 != 3'h0; // @[lsu_bus_buffer.scala 76:129] + wire _T_27 = _T_25 & _T_26; // @[lsu_bus_buffer.scala 76:113] + wire ld_addr_hitvec_lo_3 = _T_27 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 76:141] + wire _T_30 = io_end_addr_m[31:2] == buf_addr_0[31:2]; // @[lsu_bus_buffer.scala 77:74] + wire _T_32 = _T_30 & buf_write[0]; // @[lsu_bus_buffer.scala 77:98] + wire _T_34 = _T_32 & _T_5; // @[lsu_bus_buffer.scala 77:113] + wire ld_addr_hitvec_hi_0 = _T_34 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 77:141] + wire _T_37 = io_end_addr_m[31:2] == buf_addr_1[31:2]; // @[lsu_bus_buffer.scala 77:74] + wire _T_39 = _T_37 & buf_write[1]; // @[lsu_bus_buffer.scala 77:98] + wire _T_41 = _T_39 & _T_12; // @[lsu_bus_buffer.scala 77:113] + wire ld_addr_hitvec_hi_1 = _T_41 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 77:141] + wire _T_44 = io_end_addr_m[31:2] == buf_addr_2[31:2]; // @[lsu_bus_buffer.scala 77:74] + wire _T_46 = _T_44 & buf_write[2]; // @[lsu_bus_buffer.scala 77:98] + wire _T_48 = _T_46 & _T_19; // @[lsu_bus_buffer.scala 77:113] + wire ld_addr_hitvec_hi_2 = _T_48 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 77:141] + wire _T_51 = io_end_addr_m[31:2] == buf_addr_3[31:2]; // @[lsu_bus_buffer.scala 77:74] + wire _T_53 = _T_51 & buf_write[3]; // @[lsu_bus_buffer.scala 77:98] + wire _T_55 = _T_53 & _T_26; // @[lsu_bus_buffer.scala 77:113] + wire ld_addr_hitvec_hi_3 = _T_55 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 77:141] + reg [3:0] buf_byteen_3; // @[Reg.scala 27:20] + wire _T_99 = ld_addr_hitvec_lo_3 & buf_byteen_3[0]; // @[lsu_bus_buffer.scala 141:95] + wire _T_101 = _T_99 & ldst_byteen_lo_m[0]; // @[lsu_bus_buffer.scala 141:114] + reg [3:0] buf_byteen_2; // @[Reg.scala 27:20] + wire _T_95 = ld_addr_hitvec_lo_2 & buf_byteen_2[0]; // @[lsu_bus_buffer.scala 141:95] + wire _T_97 = _T_95 & ldst_byteen_lo_m[0]; // @[lsu_bus_buffer.scala 141:114] + reg [3:0] buf_byteen_1; // @[Reg.scala 27:20] + wire _T_91 = ld_addr_hitvec_lo_1 & buf_byteen_1[0]; // @[lsu_bus_buffer.scala 141:95] + wire _T_93 = _T_91 & ldst_byteen_lo_m[0]; // @[lsu_bus_buffer.scala 141:114] + reg [3:0] buf_byteen_0; // @[Reg.scala 27:20] + wire _T_87 = ld_addr_hitvec_lo_0 & buf_byteen_0[0]; // @[lsu_bus_buffer.scala 141:95] + wire _T_89 = _T_87 & ldst_byteen_lo_m[0]; // @[lsu_bus_buffer.scala 141:114] + wire [3:0] ld_byte_hitvec_lo_0 = {_T_101,_T_97,_T_93,_T_89}; // @[Cat.scala 29:58] + reg [3:0] buf_ageQ_3; // @[lsu_bus_buffer.scala 500:60] + wire _T_2621 = buf_state_3 == 3'h2; // @[lsu_bus_buffer.scala 412:93] + wire _T_4107 = 3'h0 == buf_state_3; // @[Conditional.scala 37:30] + wire _T_4130 = 3'h1 == buf_state_3; // @[Conditional.scala 37:30] + wire _T_4134 = 3'h2 == buf_state_3; // @[Conditional.scala 37:30] + reg [1:0] _T_1848; // @[Reg.scala 27:20] + wire [2:0] obuf_tag0 = {{1'd0}, _T_1848}; // @[lsu_bus_buffer.scala 352:13] + wire _T_4141 = obuf_tag0 == 3'h3; // @[lsu_bus_buffer.scala 455:48] + reg obuf_merge; // @[Reg.scala 27:20] + reg [1:0] obuf_tag1; // @[Reg.scala 27:20] + wire [2:0] _GEN_358 = {{1'd0}, obuf_tag1}; // @[lsu_bus_buffer.scala 455:104] + wire _T_4142 = _GEN_358 == 3'h3; // @[lsu_bus_buffer.scala 455:104] + wire _T_4143 = obuf_merge & _T_4142; // @[lsu_bus_buffer.scala 455:91] + wire _T_4144 = _T_4141 | _T_4143; // @[lsu_bus_buffer.scala 455:77] + reg obuf_valid; // @[lsu_bus_buffer.scala 346:54] + wire _T_4145 = _T_4144 & obuf_valid; // @[lsu_bus_buffer.scala 455:135] + reg obuf_wr_enQ; // @[lsu_bus_buffer.scala 345:55] + wire _T_4146 = _T_4145 & obuf_wr_enQ; // @[lsu_bus_buffer.scala 455:148] + wire _GEN_280 = _T_4134 & _T_4146; // @[Conditional.scala 39:67] + wire _GEN_293 = _T_4130 ? 1'h0 : _GEN_280; // @[Conditional.scala 39:67] + wire buf_cmd_state_bus_en_3 = _T_4107 ? 1'h0 : _GEN_293; // @[Conditional.scala 40:58] + wire _T_2622 = _T_2621 & buf_cmd_state_bus_en_3; // @[lsu_bus_buffer.scala 412:103] + wire _T_2623 = ~_T_2622; // @[lsu_bus_buffer.scala 412:78] + wire _T_2624 = buf_ageQ_3[3] & _T_2623; // @[lsu_bus_buffer.scala 412:76] + wire _T_2616 = buf_state_2 == 3'h2; // @[lsu_bus_buffer.scala 412:93] + wire _T_3914 = 3'h0 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_3937 = 3'h1 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_3941 = 3'h2 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_3948 = obuf_tag0 == 3'h2; // @[lsu_bus_buffer.scala 455:48] + wire _T_3949 = _GEN_358 == 3'h2; // @[lsu_bus_buffer.scala 455:104] + wire _T_3950 = obuf_merge & _T_3949; // @[lsu_bus_buffer.scala 455:91] + wire _T_3951 = _T_3948 | _T_3950; // @[lsu_bus_buffer.scala 455:77] + wire _T_3952 = _T_3951 & obuf_valid; // @[lsu_bus_buffer.scala 455:135] + wire _T_3953 = _T_3952 & obuf_wr_enQ; // @[lsu_bus_buffer.scala 455:148] + wire _GEN_204 = _T_3941 & _T_3953; // @[Conditional.scala 39:67] + wire _GEN_217 = _T_3937 ? 1'h0 : _GEN_204; // @[Conditional.scala 39:67] + wire buf_cmd_state_bus_en_2 = _T_3914 ? 1'h0 : _GEN_217; // @[Conditional.scala 40:58] + wire _T_2617 = _T_2616 & buf_cmd_state_bus_en_2; // @[lsu_bus_buffer.scala 412:103] + wire _T_2618 = ~_T_2617; // @[lsu_bus_buffer.scala 412:78] + wire _T_2619 = buf_ageQ_3[2] & _T_2618; // @[lsu_bus_buffer.scala 412:76] + wire _T_2611 = buf_state_1 == 3'h2; // @[lsu_bus_buffer.scala 412:93] + wire _T_3721 = 3'h0 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_3744 = 3'h1 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_3748 = 3'h2 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_3755 = obuf_tag0 == 3'h1; // @[lsu_bus_buffer.scala 455:48] + wire _T_3756 = _GEN_358 == 3'h1; // @[lsu_bus_buffer.scala 455:104] + wire _T_3757 = obuf_merge & _T_3756; // @[lsu_bus_buffer.scala 455:91] + wire _T_3758 = _T_3755 | _T_3757; // @[lsu_bus_buffer.scala 455:77] + wire _T_3759 = _T_3758 & obuf_valid; // @[lsu_bus_buffer.scala 455:135] + wire _T_3760 = _T_3759 & obuf_wr_enQ; // @[lsu_bus_buffer.scala 455:148] + wire _GEN_128 = _T_3748 & _T_3760; // @[Conditional.scala 39:67] + wire _GEN_141 = _T_3744 ? 1'h0 : _GEN_128; // @[Conditional.scala 39:67] + wire buf_cmd_state_bus_en_1 = _T_3721 ? 1'h0 : _GEN_141; // @[Conditional.scala 40:58] + wire _T_2612 = _T_2611 & buf_cmd_state_bus_en_1; // @[lsu_bus_buffer.scala 412:103] + wire _T_2613 = ~_T_2612; // @[lsu_bus_buffer.scala 412:78] + wire _T_2614 = buf_ageQ_3[1] & _T_2613; // @[lsu_bus_buffer.scala 412:76] + wire _T_2606 = buf_state_0 == 3'h2; // @[lsu_bus_buffer.scala 412:93] + wire _T_3528 = 3'h0 == buf_state_0; // @[Conditional.scala 37:30] + wire _T_3551 = 3'h1 == buf_state_0; // @[Conditional.scala 37:30] + wire _T_3555 = 3'h2 == buf_state_0; // @[Conditional.scala 37:30] + wire _T_3562 = obuf_tag0 == 3'h0; // @[lsu_bus_buffer.scala 455:48] + wire _T_3563 = _GEN_358 == 3'h0; // @[lsu_bus_buffer.scala 455:104] + wire _T_3564 = obuf_merge & _T_3563; // @[lsu_bus_buffer.scala 455:91] + wire _T_3565 = _T_3562 | _T_3564; // @[lsu_bus_buffer.scala 455:77] + wire _T_3566 = _T_3565 & obuf_valid; // @[lsu_bus_buffer.scala 455:135] + wire _T_3567 = _T_3566 & obuf_wr_enQ; // @[lsu_bus_buffer.scala 455:148] + wire _GEN_52 = _T_3555 & _T_3567; // @[Conditional.scala 39:67] + wire _GEN_65 = _T_3551 ? 1'h0 : _GEN_52; // @[Conditional.scala 39:67] + wire buf_cmd_state_bus_en_0 = _T_3528 ? 1'h0 : _GEN_65; // @[Conditional.scala 40:58] + wire _T_2607 = _T_2606 & buf_cmd_state_bus_en_0; // @[lsu_bus_buffer.scala 412:103] + wire _T_2608 = ~_T_2607; // @[lsu_bus_buffer.scala 412:78] + wire _T_2609 = buf_ageQ_3[0] & _T_2608; // @[lsu_bus_buffer.scala 412:76] + wire [3:0] buf_age_3 = {_T_2624,_T_2619,_T_2614,_T_2609}; // @[Cat.scala 29:58] + wire _T_2723 = ~buf_age_3[2]; // @[lsu_bus_buffer.scala 413:89] + wire _T_2725 = _T_2723 & _T_19; // @[lsu_bus_buffer.scala 413:104] + wire _T_2717 = ~buf_age_3[1]; // @[lsu_bus_buffer.scala 413:89] + wire _T_2719 = _T_2717 & _T_12; // @[lsu_bus_buffer.scala 413:104] + wire _T_2711 = ~buf_age_3[0]; // @[lsu_bus_buffer.scala 413:89] + wire _T_2713 = _T_2711 & _T_5; // @[lsu_bus_buffer.scala 413:104] + wire [3:0] buf_age_younger_3 = {1'h0,_T_2725,_T_2719,_T_2713}; // @[Cat.scala 29:58] + wire [3:0] _T_255 = ld_byte_hitvec_lo_0 & buf_age_younger_3; // @[lsu_bus_buffer.scala 146:122] + wire _T_256 = |_T_255; // @[lsu_bus_buffer.scala 146:144] + wire _T_257 = ~_T_256; // @[lsu_bus_buffer.scala 146:99] + wire _T_258 = ld_byte_hitvec_lo_0[3] & _T_257; // @[lsu_bus_buffer.scala 146:97] + reg [31:0] ibuf_addr; // @[lib.scala 374:16] + wire _T_512 = io_lsu_addr_m[31:2] == ibuf_addr[31:2]; // @[lsu_bus_buffer.scala 152:51] + reg ibuf_write; // @[Reg.scala 27:20] + wire _T_513 = _T_512 & ibuf_write; // @[lsu_bus_buffer.scala 152:73] + reg ibuf_valid; // @[lsu_bus_buffer.scala 240:54] + wire _T_514 = _T_513 & ibuf_valid; // @[lsu_bus_buffer.scala 152:86] + wire ld_addr_ibuf_hit_lo = _T_514 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 152:99] + wire [3:0] _T_521 = ld_addr_ibuf_hit_lo ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + reg [3:0] ibuf_byteen; // @[Reg.scala 27:20] + wire [3:0] _T_522 = _T_521 & ibuf_byteen; // @[lsu_bus_buffer.scala 157:55] + wire [3:0] ld_byte_ibuf_hit_lo = _T_522 & ldst_byteen_lo_m; // @[lsu_bus_buffer.scala 157:69] + wire _T_260 = ~ld_byte_ibuf_hit_lo[0]; // @[lsu_bus_buffer.scala 146:150] + wire _T_261 = _T_258 & _T_260; // @[lsu_bus_buffer.scala 146:148] + reg [3:0] buf_ageQ_2; // @[lsu_bus_buffer.scala 500:60] + wire _T_2601 = buf_ageQ_2[3] & _T_2623; // @[lsu_bus_buffer.scala 412:76] + wire _T_2596 = buf_ageQ_2[2] & _T_2618; // @[lsu_bus_buffer.scala 412:76] + wire _T_2591 = buf_ageQ_2[1] & _T_2613; // @[lsu_bus_buffer.scala 412:76] + wire _T_2586 = buf_ageQ_2[0] & _T_2608; // @[lsu_bus_buffer.scala 412:76] + wire [3:0] buf_age_2 = {_T_2601,_T_2596,_T_2591,_T_2586}; // @[Cat.scala 29:58] + wire _T_2702 = ~buf_age_2[3]; // @[lsu_bus_buffer.scala 413:89] + wire _T_2704 = _T_2702 & _T_26; // @[lsu_bus_buffer.scala 413:104] + wire _T_2690 = ~buf_age_2[1]; // @[lsu_bus_buffer.scala 413:89] + wire _T_2692 = _T_2690 & _T_12; // @[lsu_bus_buffer.scala 413:104] + wire _T_2684 = ~buf_age_2[0]; // @[lsu_bus_buffer.scala 413:89] + wire _T_2686 = _T_2684 & _T_5; // @[lsu_bus_buffer.scala 413:104] + wire [3:0] buf_age_younger_2 = {_T_2704,1'h0,_T_2692,_T_2686}; // @[Cat.scala 29:58] + wire [3:0] _T_247 = ld_byte_hitvec_lo_0 & buf_age_younger_2; // @[lsu_bus_buffer.scala 146:122] + wire _T_248 = |_T_247; // @[lsu_bus_buffer.scala 146:144] + wire _T_249 = ~_T_248; // @[lsu_bus_buffer.scala 146:99] + wire _T_250 = ld_byte_hitvec_lo_0[2] & _T_249; // @[lsu_bus_buffer.scala 146:97] + wire _T_253 = _T_250 & _T_260; // @[lsu_bus_buffer.scala 146:148] + reg [3:0] buf_ageQ_1; // @[lsu_bus_buffer.scala 500:60] + wire _T_2578 = buf_ageQ_1[3] & _T_2623; // @[lsu_bus_buffer.scala 412:76] + wire _T_2573 = buf_ageQ_1[2] & _T_2618; // @[lsu_bus_buffer.scala 412:76] + wire _T_2568 = buf_ageQ_1[1] & _T_2613; // @[lsu_bus_buffer.scala 412:76] + wire _T_2563 = buf_ageQ_1[0] & _T_2608; // @[lsu_bus_buffer.scala 412:76] + wire [3:0] buf_age_1 = {_T_2578,_T_2573,_T_2568,_T_2563}; // @[Cat.scala 29:58] + wire _T_2675 = ~buf_age_1[3]; // @[lsu_bus_buffer.scala 413:89] + wire _T_2677 = _T_2675 & _T_26; // @[lsu_bus_buffer.scala 413:104] + wire _T_2669 = ~buf_age_1[2]; // @[lsu_bus_buffer.scala 413:89] + wire _T_2671 = _T_2669 & _T_19; // @[lsu_bus_buffer.scala 413:104] + wire _T_2657 = ~buf_age_1[0]; // @[lsu_bus_buffer.scala 413:89] + wire _T_2659 = _T_2657 & _T_5; // @[lsu_bus_buffer.scala 413:104] + wire [3:0] buf_age_younger_1 = {_T_2677,_T_2671,1'h0,_T_2659}; // @[Cat.scala 29:58] + wire [3:0] _T_239 = ld_byte_hitvec_lo_0 & buf_age_younger_1; // @[lsu_bus_buffer.scala 146:122] + wire _T_240 = |_T_239; // @[lsu_bus_buffer.scala 146:144] + wire _T_241 = ~_T_240; // @[lsu_bus_buffer.scala 146:99] + wire _T_242 = ld_byte_hitvec_lo_0[1] & _T_241; // @[lsu_bus_buffer.scala 146:97] + wire _T_245 = _T_242 & _T_260; // @[lsu_bus_buffer.scala 146:148] + reg [3:0] buf_ageQ_0; // @[lsu_bus_buffer.scala 500:60] + wire _T_2555 = buf_ageQ_0[3] & _T_2623; // @[lsu_bus_buffer.scala 412:76] + wire _T_2550 = buf_ageQ_0[2] & _T_2618; // @[lsu_bus_buffer.scala 412:76] + wire _T_2545 = buf_ageQ_0[1] & _T_2613; // @[lsu_bus_buffer.scala 412:76] + wire _T_2540 = buf_ageQ_0[0] & _T_2608; // @[lsu_bus_buffer.scala 412:76] + wire [3:0] buf_age_0 = {_T_2555,_T_2550,_T_2545,_T_2540}; // @[Cat.scala 29:58] + wire _T_2648 = ~buf_age_0[3]; // @[lsu_bus_buffer.scala 413:89] + wire _T_2650 = _T_2648 & _T_26; // @[lsu_bus_buffer.scala 413:104] + wire _T_2642 = ~buf_age_0[2]; // @[lsu_bus_buffer.scala 413:89] + wire _T_2644 = _T_2642 & _T_19; // @[lsu_bus_buffer.scala 413:104] + wire _T_2636 = ~buf_age_0[1]; // @[lsu_bus_buffer.scala 413:89] + wire _T_2638 = _T_2636 & _T_12; // @[lsu_bus_buffer.scala 413:104] + wire [3:0] buf_age_younger_0 = {_T_2650,_T_2644,_T_2638,1'h0}; // @[Cat.scala 29:58] + wire [3:0] _T_231 = ld_byte_hitvec_lo_0 & buf_age_younger_0; // @[lsu_bus_buffer.scala 146:122] + wire _T_232 = |_T_231; // @[lsu_bus_buffer.scala 146:144] + wire _T_233 = ~_T_232; // @[lsu_bus_buffer.scala 146:99] + wire _T_234 = ld_byte_hitvec_lo_0[0] & _T_233; // @[lsu_bus_buffer.scala 146:97] + wire _T_237 = _T_234 & _T_260; // @[lsu_bus_buffer.scala 146:148] + wire [3:0] ld_byte_hitvecfn_lo_0 = {_T_261,_T_253,_T_245,_T_237}; // @[Cat.scala 29:58] + wire _T_56 = |ld_byte_hitvecfn_lo_0; // @[lsu_bus_buffer.scala 138:73] + wire _T_58 = _T_56 | ld_byte_ibuf_hit_lo[0]; // @[lsu_bus_buffer.scala 138:77] + wire _T_117 = ld_addr_hitvec_lo_3 & buf_byteen_3[1]; // @[lsu_bus_buffer.scala 141:95] + wire _T_119 = _T_117 & ldst_byteen_lo_m[1]; // @[lsu_bus_buffer.scala 141:114] + wire _T_113 = ld_addr_hitvec_lo_2 & buf_byteen_2[1]; // @[lsu_bus_buffer.scala 141:95] + wire _T_115 = _T_113 & ldst_byteen_lo_m[1]; // @[lsu_bus_buffer.scala 141:114] + wire _T_109 = ld_addr_hitvec_lo_1 & buf_byteen_1[1]; // @[lsu_bus_buffer.scala 141:95] + wire _T_111 = _T_109 & ldst_byteen_lo_m[1]; // @[lsu_bus_buffer.scala 141:114] + wire _T_105 = ld_addr_hitvec_lo_0 & buf_byteen_0[1]; // @[lsu_bus_buffer.scala 141:95] + wire _T_107 = _T_105 & ldst_byteen_lo_m[1]; // @[lsu_bus_buffer.scala 141:114] + wire [3:0] ld_byte_hitvec_lo_1 = {_T_119,_T_115,_T_111,_T_107}; // @[Cat.scala 29:58] + wire [3:0] _T_290 = ld_byte_hitvec_lo_1 & buf_age_younger_3; // @[lsu_bus_buffer.scala 146:122] + wire _T_291 = |_T_290; // @[lsu_bus_buffer.scala 146:144] + wire _T_292 = ~_T_291; // @[lsu_bus_buffer.scala 146:99] + wire _T_293 = ld_byte_hitvec_lo_1[3] & _T_292; // @[lsu_bus_buffer.scala 146:97] + wire _T_295 = ~ld_byte_ibuf_hit_lo[1]; // @[lsu_bus_buffer.scala 146:150] + wire _T_296 = _T_293 & _T_295; // @[lsu_bus_buffer.scala 146:148] + wire [3:0] _T_282 = ld_byte_hitvec_lo_1 & buf_age_younger_2; // @[lsu_bus_buffer.scala 146:122] + wire _T_283 = |_T_282; // @[lsu_bus_buffer.scala 146:144] + wire _T_284 = ~_T_283; // @[lsu_bus_buffer.scala 146:99] + wire _T_285 = ld_byte_hitvec_lo_1[2] & _T_284; // @[lsu_bus_buffer.scala 146:97] + wire _T_288 = _T_285 & _T_295; // @[lsu_bus_buffer.scala 146:148] + wire [3:0] _T_274 = ld_byte_hitvec_lo_1 & buf_age_younger_1; // @[lsu_bus_buffer.scala 146:122] + wire _T_275 = |_T_274; // @[lsu_bus_buffer.scala 146:144] + wire _T_276 = ~_T_275; // @[lsu_bus_buffer.scala 146:99] + wire _T_277 = ld_byte_hitvec_lo_1[1] & _T_276; // @[lsu_bus_buffer.scala 146:97] + wire _T_280 = _T_277 & _T_295; // @[lsu_bus_buffer.scala 146:148] + wire [3:0] _T_266 = ld_byte_hitvec_lo_1 & buf_age_younger_0; // @[lsu_bus_buffer.scala 146:122] + wire _T_267 = |_T_266; // @[lsu_bus_buffer.scala 146:144] + wire _T_268 = ~_T_267; // @[lsu_bus_buffer.scala 146:99] + wire _T_269 = ld_byte_hitvec_lo_1[0] & _T_268; // @[lsu_bus_buffer.scala 146:97] + wire _T_272 = _T_269 & _T_295; // @[lsu_bus_buffer.scala 146:148] + wire [3:0] ld_byte_hitvecfn_lo_1 = {_T_296,_T_288,_T_280,_T_272}; // @[Cat.scala 29:58] + wire _T_59 = |ld_byte_hitvecfn_lo_1; // @[lsu_bus_buffer.scala 138:73] + wire _T_61 = _T_59 | ld_byte_ibuf_hit_lo[1]; // @[lsu_bus_buffer.scala 138:77] + wire _T_135 = ld_addr_hitvec_lo_3 & buf_byteen_3[2]; // @[lsu_bus_buffer.scala 141:95] + wire _T_137 = _T_135 & ldst_byteen_lo_m[2]; // @[lsu_bus_buffer.scala 141:114] + wire _T_131 = ld_addr_hitvec_lo_2 & buf_byteen_2[2]; // @[lsu_bus_buffer.scala 141:95] + wire _T_133 = _T_131 & ldst_byteen_lo_m[2]; // @[lsu_bus_buffer.scala 141:114] + wire _T_127 = ld_addr_hitvec_lo_1 & buf_byteen_1[2]; // @[lsu_bus_buffer.scala 141:95] + wire _T_129 = _T_127 & ldst_byteen_lo_m[2]; // @[lsu_bus_buffer.scala 141:114] + wire _T_123 = ld_addr_hitvec_lo_0 & buf_byteen_0[2]; // @[lsu_bus_buffer.scala 141:95] + wire _T_125 = _T_123 & ldst_byteen_lo_m[2]; // @[lsu_bus_buffer.scala 141:114] + wire [3:0] ld_byte_hitvec_lo_2 = {_T_137,_T_133,_T_129,_T_125}; // @[Cat.scala 29:58] + wire [3:0] _T_325 = ld_byte_hitvec_lo_2 & buf_age_younger_3; // @[lsu_bus_buffer.scala 146:122] + wire _T_326 = |_T_325; // @[lsu_bus_buffer.scala 146:144] + wire _T_327 = ~_T_326; // @[lsu_bus_buffer.scala 146:99] + wire _T_328 = ld_byte_hitvec_lo_2[3] & _T_327; // @[lsu_bus_buffer.scala 146:97] + wire _T_330 = ~ld_byte_ibuf_hit_lo[2]; // @[lsu_bus_buffer.scala 146:150] + wire _T_331 = _T_328 & _T_330; // @[lsu_bus_buffer.scala 146:148] + wire [3:0] _T_317 = ld_byte_hitvec_lo_2 & buf_age_younger_2; // @[lsu_bus_buffer.scala 146:122] + wire _T_318 = |_T_317; // @[lsu_bus_buffer.scala 146:144] + wire _T_319 = ~_T_318; // @[lsu_bus_buffer.scala 146:99] + wire _T_320 = ld_byte_hitvec_lo_2[2] & _T_319; // @[lsu_bus_buffer.scala 146:97] + wire _T_323 = _T_320 & _T_330; // @[lsu_bus_buffer.scala 146:148] + wire [3:0] _T_309 = ld_byte_hitvec_lo_2 & buf_age_younger_1; // @[lsu_bus_buffer.scala 146:122] + wire _T_310 = |_T_309; // @[lsu_bus_buffer.scala 146:144] + wire _T_311 = ~_T_310; // @[lsu_bus_buffer.scala 146:99] + wire _T_312 = ld_byte_hitvec_lo_2[1] & _T_311; // @[lsu_bus_buffer.scala 146:97] + wire _T_315 = _T_312 & _T_330; // @[lsu_bus_buffer.scala 146:148] + wire [3:0] _T_301 = ld_byte_hitvec_lo_2 & buf_age_younger_0; // @[lsu_bus_buffer.scala 146:122] + wire _T_302 = |_T_301; // @[lsu_bus_buffer.scala 146:144] + wire _T_303 = ~_T_302; // @[lsu_bus_buffer.scala 146:99] + wire _T_304 = ld_byte_hitvec_lo_2[0] & _T_303; // @[lsu_bus_buffer.scala 146:97] + wire _T_307 = _T_304 & _T_330; // @[lsu_bus_buffer.scala 146:148] + wire [3:0] ld_byte_hitvecfn_lo_2 = {_T_331,_T_323,_T_315,_T_307}; // @[Cat.scala 29:58] + wire _T_62 = |ld_byte_hitvecfn_lo_2; // @[lsu_bus_buffer.scala 138:73] + wire _T_64 = _T_62 | ld_byte_ibuf_hit_lo[2]; // @[lsu_bus_buffer.scala 138:77] + wire _T_153 = ld_addr_hitvec_lo_3 & buf_byteen_3[3]; // @[lsu_bus_buffer.scala 141:95] + wire _T_155 = _T_153 & ldst_byteen_lo_m[3]; // @[lsu_bus_buffer.scala 141:114] + wire _T_149 = ld_addr_hitvec_lo_2 & buf_byteen_2[3]; // @[lsu_bus_buffer.scala 141:95] + wire _T_151 = _T_149 & ldst_byteen_lo_m[3]; // @[lsu_bus_buffer.scala 141:114] + wire _T_145 = ld_addr_hitvec_lo_1 & buf_byteen_1[3]; // @[lsu_bus_buffer.scala 141:95] + wire _T_147 = _T_145 & ldst_byteen_lo_m[3]; // @[lsu_bus_buffer.scala 141:114] + wire _T_141 = ld_addr_hitvec_lo_0 & buf_byteen_0[3]; // @[lsu_bus_buffer.scala 141:95] + wire _T_143 = _T_141 & ldst_byteen_lo_m[3]; // @[lsu_bus_buffer.scala 141:114] + wire [3:0] ld_byte_hitvec_lo_3 = {_T_155,_T_151,_T_147,_T_143}; // @[Cat.scala 29:58] + wire [3:0] _T_360 = ld_byte_hitvec_lo_3 & buf_age_younger_3; // @[lsu_bus_buffer.scala 146:122] + wire _T_361 = |_T_360; // @[lsu_bus_buffer.scala 146:144] + wire _T_362 = ~_T_361; // @[lsu_bus_buffer.scala 146:99] + wire _T_363 = ld_byte_hitvec_lo_3[3] & _T_362; // @[lsu_bus_buffer.scala 146:97] + wire _T_365 = ~ld_byte_ibuf_hit_lo[3]; // @[lsu_bus_buffer.scala 146:150] + wire _T_366 = _T_363 & _T_365; // @[lsu_bus_buffer.scala 146:148] + wire [3:0] _T_352 = ld_byte_hitvec_lo_3 & buf_age_younger_2; // @[lsu_bus_buffer.scala 146:122] + wire _T_353 = |_T_352; // @[lsu_bus_buffer.scala 146:144] + wire _T_354 = ~_T_353; // @[lsu_bus_buffer.scala 146:99] + wire _T_355 = ld_byte_hitvec_lo_3[2] & _T_354; // @[lsu_bus_buffer.scala 146:97] + wire _T_358 = _T_355 & _T_365; // @[lsu_bus_buffer.scala 146:148] + wire [3:0] _T_344 = ld_byte_hitvec_lo_3 & buf_age_younger_1; // @[lsu_bus_buffer.scala 146:122] + wire _T_345 = |_T_344; // @[lsu_bus_buffer.scala 146:144] + wire _T_346 = ~_T_345; // @[lsu_bus_buffer.scala 146:99] + wire _T_347 = ld_byte_hitvec_lo_3[1] & _T_346; // @[lsu_bus_buffer.scala 146:97] + wire _T_350 = _T_347 & _T_365; // @[lsu_bus_buffer.scala 146:148] + wire [3:0] _T_336 = ld_byte_hitvec_lo_3 & buf_age_younger_0; // @[lsu_bus_buffer.scala 146:122] + wire _T_337 = |_T_336; // @[lsu_bus_buffer.scala 146:144] + wire _T_338 = ~_T_337; // @[lsu_bus_buffer.scala 146:99] + wire _T_339 = ld_byte_hitvec_lo_3[0] & _T_338; // @[lsu_bus_buffer.scala 146:97] + wire _T_342 = _T_339 & _T_365; // @[lsu_bus_buffer.scala 146:148] + wire [3:0] ld_byte_hitvecfn_lo_3 = {_T_366,_T_358,_T_350,_T_342}; // @[Cat.scala 29:58] + wire _T_65 = |ld_byte_hitvecfn_lo_3; // @[lsu_bus_buffer.scala 138:73] + wire _T_67 = _T_65 | ld_byte_ibuf_hit_lo[3]; // @[lsu_bus_buffer.scala 138:77] + wire [2:0] _T_69 = {_T_67,_T_64,_T_61}; // @[Cat.scala 29:58] + wire _T_171 = ld_addr_hitvec_hi_3 & buf_byteen_3[0]; // @[lsu_bus_buffer.scala 142:95] + wire _T_173 = _T_171 & ldst_byteen_hi_m[0]; // @[lsu_bus_buffer.scala 142:114] + wire _T_167 = ld_addr_hitvec_hi_2 & buf_byteen_2[0]; // @[lsu_bus_buffer.scala 142:95] + wire _T_169 = _T_167 & ldst_byteen_hi_m[0]; // @[lsu_bus_buffer.scala 142:114] + wire _T_163 = ld_addr_hitvec_hi_1 & buf_byteen_1[0]; // @[lsu_bus_buffer.scala 142:95] + wire _T_165 = _T_163 & ldst_byteen_hi_m[0]; // @[lsu_bus_buffer.scala 142:114] + wire _T_159 = ld_addr_hitvec_hi_0 & buf_byteen_0[0]; // @[lsu_bus_buffer.scala 142:95] + wire _T_161 = _T_159 & ldst_byteen_hi_m[0]; // @[lsu_bus_buffer.scala 142:114] + wire [3:0] ld_byte_hitvec_hi_0 = {_T_173,_T_169,_T_165,_T_161}; // @[Cat.scala 29:58] + wire [3:0] _T_395 = ld_byte_hitvec_hi_0 & buf_age_younger_3; // @[lsu_bus_buffer.scala 147:122] + wire _T_396 = |_T_395; // @[lsu_bus_buffer.scala 147:144] + wire _T_397 = ~_T_396; // @[lsu_bus_buffer.scala 147:99] + wire _T_398 = ld_byte_hitvec_hi_0[3] & _T_397; // @[lsu_bus_buffer.scala 147:97] + wire _T_517 = io_end_addr_m[31:2] == ibuf_addr[31:2]; // @[lsu_bus_buffer.scala 153:51] + wire _T_518 = _T_517 & ibuf_write; // @[lsu_bus_buffer.scala 153:73] + wire _T_519 = _T_518 & ibuf_valid; // @[lsu_bus_buffer.scala 153:86] + wire ld_addr_ibuf_hit_hi = _T_519 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 153:99] + wire [3:0] _T_525 = ld_addr_ibuf_hit_hi ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_526 = _T_525 & ibuf_byteen; // @[lsu_bus_buffer.scala 158:55] + wire [3:0] ld_byte_ibuf_hit_hi = _T_526 & ldst_byteen_hi_m; // @[lsu_bus_buffer.scala 158:69] + wire _T_400 = ~ld_byte_ibuf_hit_hi[0]; // @[lsu_bus_buffer.scala 147:150] + wire _T_401 = _T_398 & _T_400; // @[lsu_bus_buffer.scala 147:148] + wire [3:0] _T_387 = ld_byte_hitvec_hi_0 & buf_age_younger_2; // @[lsu_bus_buffer.scala 147:122] + wire _T_388 = |_T_387; // @[lsu_bus_buffer.scala 147:144] + wire _T_389 = ~_T_388; // @[lsu_bus_buffer.scala 147:99] + wire _T_390 = ld_byte_hitvec_hi_0[2] & _T_389; // @[lsu_bus_buffer.scala 147:97] + wire _T_393 = _T_390 & _T_400; // @[lsu_bus_buffer.scala 147:148] + wire [3:0] _T_379 = ld_byte_hitvec_hi_0 & buf_age_younger_1; // @[lsu_bus_buffer.scala 147:122] + wire _T_380 = |_T_379; // @[lsu_bus_buffer.scala 147:144] + wire _T_381 = ~_T_380; // @[lsu_bus_buffer.scala 147:99] + wire _T_382 = ld_byte_hitvec_hi_0[1] & _T_381; // @[lsu_bus_buffer.scala 147:97] + wire _T_385 = _T_382 & _T_400; // @[lsu_bus_buffer.scala 147:148] + wire [3:0] _T_371 = ld_byte_hitvec_hi_0 & buf_age_younger_0; // @[lsu_bus_buffer.scala 147:122] + wire _T_372 = |_T_371; // @[lsu_bus_buffer.scala 147:144] + wire _T_373 = ~_T_372; // @[lsu_bus_buffer.scala 147:99] + wire _T_374 = ld_byte_hitvec_hi_0[0] & _T_373; // @[lsu_bus_buffer.scala 147:97] + wire _T_377 = _T_374 & _T_400; // @[lsu_bus_buffer.scala 147:148] + wire [3:0] ld_byte_hitvecfn_hi_0 = {_T_401,_T_393,_T_385,_T_377}; // @[Cat.scala 29:58] + wire _T_71 = |ld_byte_hitvecfn_hi_0; // @[lsu_bus_buffer.scala 139:73] + wire _T_73 = _T_71 | ld_byte_ibuf_hit_hi[0]; // @[lsu_bus_buffer.scala 139:77] + wire _T_189 = ld_addr_hitvec_hi_3 & buf_byteen_3[1]; // @[lsu_bus_buffer.scala 142:95] + wire _T_191 = _T_189 & ldst_byteen_hi_m[1]; // @[lsu_bus_buffer.scala 142:114] + wire _T_185 = ld_addr_hitvec_hi_2 & buf_byteen_2[1]; // @[lsu_bus_buffer.scala 142:95] + wire _T_187 = _T_185 & ldst_byteen_hi_m[1]; // @[lsu_bus_buffer.scala 142:114] + wire _T_181 = ld_addr_hitvec_hi_1 & buf_byteen_1[1]; // @[lsu_bus_buffer.scala 142:95] + wire _T_183 = _T_181 & ldst_byteen_hi_m[1]; // @[lsu_bus_buffer.scala 142:114] + wire _T_177 = ld_addr_hitvec_hi_0 & buf_byteen_0[1]; // @[lsu_bus_buffer.scala 142:95] + wire _T_179 = _T_177 & ldst_byteen_hi_m[1]; // @[lsu_bus_buffer.scala 142:114] + wire [3:0] ld_byte_hitvec_hi_1 = {_T_191,_T_187,_T_183,_T_179}; // @[Cat.scala 29:58] + wire [3:0] _T_430 = ld_byte_hitvec_hi_1 & buf_age_younger_3; // @[lsu_bus_buffer.scala 147:122] + wire _T_431 = |_T_430; // @[lsu_bus_buffer.scala 147:144] + wire _T_432 = ~_T_431; // @[lsu_bus_buffer.scala 147:99] + wire _T_433 = ld_byte_hitvec_hi_1[3] & _T_432; // @[lsu_bus_buffer.scala 147:97] + wire _T_435 = ~ld_byte_ibuf_hit_hi[1]; // @[lsu_bus_buffer.scala 147:150] + wire _T_436 = _T_433 & _T_435; // @[lsu_bus_buffer.scala 147:148] + wire [3:0] _T_422 = ld_byte_hitvec_hi_1 & buf_age_younger_2; // @[lsu_bus_buffer.scala 147:122] + wire _T_423 = |_T_422; // @[lsu_bus_buffer.scala 147:144] + wire _T_424 = ~_T_423; // @[lsu_bus_buffer.scala 147:99] + wire _T_425 = ld_byte_hitvec_hi_1[2] & _T_424; // @[lsu_bus_buffer.scala 147:97] + wire _T_428 = _T_425 & _T_435; // @[lsu_bus_buffer.scala 147:148] + wire [3:0] _T_414 = ld_byte_hitvec_hi_1 & buf_age_younger_1; // @[lsu_bus_buffer.scala 147:122] + wire _T_415 = |_T_414; // @[lsu_bus_buffer.scala 147:144] + wire _T_416 = ~_T_415; // @[lsu_bus_buffer.scala 147:99] + wire _T_417 = ld_byte_hitvec_hi_1[1] & _T_416; // @[lsu_bus_buffer.scala 147:97] + wire _T_420 = _T_417 & _T_435; // @[lsu_bus_buffer.scala 147:148] + wire [3:0] _T_406 = ld_byte_hitvec_hi_1 & buf_age_younger_0; // @[lsu_bus_buffer.scala 147:122] + wire _T_407 = |_T_406; // @[lsu_bus_buffer.scala 147:144] + wire _T_408 = ~_T_407; // @[lsu_bus_buffer.scala 147:99] + wire _T_409 = ld_byte_hitvec_hi_1[0] & _T_408; // @[lsu_bus_buffer.scala 147:97] + wire _T_412 = _T_409 & _T_435; // @[lsu_bus_buffer.scala 147:148] + wire [3:0] ld_byte_hitvecfn_hi_1 = {_T_436,_T_428,_T_420,_T_412}; // @[Cat.scala 29:58] + wire _T_74 = |ld_byte_hitvecfn_hi_1; // @[lsu_bus_buffer.scala 139:73] + wire _T_76 = _T_74 | ld_byte_ibuf_hit_hi[1]; // @[lsu_bus_buffer.scala 139:77] + wire _T_207 = ld_addr_hitvec_hi_3 & buf_byteen_3[2]; // @[lsu_bus_buffer.scala 142:95] + wire _T_209 = _T_207 & ldst_byteen_hi_m[2]; // @[lsu_bus_buffer.scala 142:114] + wire _T_203 = ld_addr_hitvec_hi_2 & buf_byteen_2[2]; // @[lsu_bus_buffer.scala 142:95] + wire _T_205 = _T_203 & ldst_byteen_hi_m[2]; // @[lsu_bus_buffer.scala 142:114] + wire _T_199 = ld_addr_hitvec_hi_1 & buf_byteen_1[2]; // @[lsu_bus_buffer.scala 142:95] + wire _T_201 = _T_199 & ldst_byteen_hi_m[2]; // @[lsu_bus_buffer.scala 142:114] + wire _T_195 = ld_addr_hitvec_hi_0 & buf_byteen_0[2]; // @[lsu_bus_buffer.scala 142:95] + wire _T_197 = _T_195 & ldst_byteen_hi_m[2]; // @[lsu_bus_buffer.scala 142:114] + wire [3:0] ld_byte_hitvec_hi_2 = {_T_209,_T_205,_T_201,_T_197}; // @[Cat.scala 29:58] + wire [3:0] _T_465 = ld_byte_hitvec_hi_2 & buf_age_younger_3; // @[lsu_bus_buffer.scala 147:122] + wire _T_466 = |_T_465; // @[lsu_bus_buffer.scala 147:144] + wire _T_467 = ~_T_466; // @[lsu_bus_buffer.scala 147:99] + wire _T_468 = ld_byte_hitvec_hi_2[3] & _T_467; // @[lsu_bus_buffer.scala 147:97] + wire _T_470 = ~ld_byte_ibuf_hit_hi[2]; // @[lsu_bus_buffer.scala 147:150] + wire _T_471 = _T_468 & _T_470; // @[lsu_bus_buffer.scala 147:148] + wire [3:0] _T_457 = ld_byte_hitvec_hi_2 & buf_age_younger_2; // @[lsu_bus_buffer.scala 147:122] + wire _T_458 = |_T_457; // @[lsu_bus_buffer.scala 147:144] + wire _T_459 = ~_T_458; // @[lsu_bus_buffer.scala 147:99] + wire _T_460 = ld_byte_hitvec_hi_2[2] & _T_459; // @[lsu_bus_buffer.scala 147:97] + wire _T_463 = _T_460 & _T_470; // @[lsu_bus_buffer.scala 147:148] + wire [3:0] _T_449 = ld_byte_hitvec_hi_2 & buf_age_younger_1; // @[lsu_bus_buffer.scala 147:122] + wire _T_450 = |_T_449; // @[lsu_bus_buffer.scala 147:144] + wire _T_451 = ~_T_450; // @[lsu_bus_buffer.scala 147:99] + wire _T_452 = ld_byte_hitvec_hi_2[1] & _T_451; // @[lsu_bus_buffer.scala 147:97] + wire _T_455 = _T_452 & _T_470; // @[lsu_bus_buffer.scala 147:148] + wire [3:0] _T_441 = ld_byte_hitvec_hi_2 & buf_age_younger_0; // @[lsu_bus_buffer.scala 147:122] + wire _T_442 = |_T_441; // @[lsu_bus_buffer.scala 147:144] + wire _T_443 = ~_T_442; // @[lsu_bus_buffer.scala 147:99] + wire _T_444 = ld_byte_hitvec_hi_2[0] & _T_443; // @[lsu_bus_buffer.scala 147:97] + wire _T_447 = _T_444 & _T_470; // @[lsu_bus_buffer.scala 147:148] + wire [3:0] ld_byte_hitvecfn_hi_2 = {_T_471,_T_463,_T_455,_T_447}; // @[Cat.scala 29:58] + wire _T_77 = |ld_byte_hitvecfn_hi_2; // @[lsu_bus_buffer.scala 139:73] + wire _T_79 = _T_77 | ld_byte_ibuf_hit_hi[2]; // @[lsu_bus_buffer.scala 139:77] + wire _T_225 = ld_addr_hitvec_hi_3 & buf_byteen_3[3]; // @[lsu_bus_buffer.scala 142:95] + wire _T_227 = _T_225 & ldst_byteen_hi_m[3]; // @[lsu_bus_buffer.scala 142:114] + wire _T_221 = ld_addr_hitvec_hi_2 & buf_byteen_2[3]; // @[lsu_bus_buffer.scala 142:95] + wire _T_223 = _T_221 & ldst_byteen_hi_m[3]; // @[lsu_bus_buffer.scala 142:114] + wire _T_217 = ld_addr_hitvec_hi_1 & buf_byteen_1[3]; // @[lsu_bus_buffer.scala 142:95] + wire _T_219 = _T_217 & ldst_byteen_hi_m[3]; // @[lsu_bus_buffer.scala 142:114] + wire _T_213 = ld_addr_hitvec_hi_0 & buf_byteen_0[3]; // @[lsu_bus_buffer.scala 142:95] + wire _T_215 = _T_213 & ldst_byteen_hi_m[3]; // @[lsu_bus_buffer.scala 142:114] + wire [3:0] ld_byte_hitvec_hi_3 = {_T_227,_T_223,_T_219,_T_215}; // @[Cat.scala 29:58] + wire [3:0] _T_500 = ld_byte_hitvec_hi_3 & buf_age_younger_3; // @[lsu_bus_buffer.scala 147:122] + wire _T_501 = |_T_500; // @[lsu_bus_buffer.scala 147:144] + wire _T_502 = ~_T_501; // @[lsu_bus_buffer.scala 147:99] + wire _T_503 = ld_byte_hitvec_hi_3[3] & _T_502; // @[lsu_bus_buffer.scala 147:97] + wire _T_505 = ~ld_byte_ibuf_hit_hi[3]; // @[lsu_bus_buffer.scala 147:150] + wire _T_506 = _T_503 & _T_505; // @[lsu_bus_buffer.scala 147:148] + wire [3:0] _T_492 = ld_byte_hitvec_hi_3 & buf_age_younger_2; // @[lsu_bus_buffer.scala 147:122] + wire _T_493 = |_T_492; // @[lsu_bus_buffer.scala 147:144] + wire _T_494 = ~_T_493; // @[lsu_bus_buffer.scala 147:99] + wire _T_495 = ld_byte_hitvec_hi_3[2] & _T_494; // @[lsu_bus_buffer.scala 147:97] + wire _T_498 = _T_495 & _T_505; // @[lsu_bus_buffer.scala 147:148] + wire [3:0] _T_484 = ld_byte_hitvec_hi_3 & buf_age_younger_1; // @[lsu_bus_buffer.scala 147:122] + wire _T_485 = |_T_484; // @[lsu_bus_buffer.scala 147:144] + wire _T_486 = ~_T_485; // @[lsu_bus_buffer.scala 147:99] + wire _T_487 = ld_byte_hitvec_hi_3[1] & _T_486; // @[lsu_bus_buffer.scala 147:97] + wire _T_490 = _T_487 & _T_505; // @[lsu_bus_buffer.scala 147:148] + wire [3:0] _T_476 = ld_byte_hitvec_hi_3 & buf_age_younger_0; // @[lsu_bus_buffer.scala 147:122] + wire _T_477 = |_T_476; // @[lsu_bus_buffer.scala 147:144] + wire _T_478 = ~_T_477; // @[lsu_bus_buffer.scala 147:99] + wire _T_479 = ld_byte_hitvec_hi_3[0] & _T_478; // @[lsu_bus_buffer.scala 147:97] + wire _T_482 = _T_479 & _T_505; // @[lsu_bus_buffer.scala 147:148] + wire [3:0] ld_byte_hitvecfn_hi_3 = {_T_506,_T_498,_T_490,_T_482}; // @[Cat.scala 29:58] + wire _T_80 = |ld_byte_hitvecfn_hi_3; // @[lsu_bus_buffer.scala 139:73] + wire _T_82 = _T_80 | ld_byte_ibuf_hit_hi[3]; // @[lsu_bus_buffer.scala 139:77] + wire [2:0] _T_84 = {_T_82,_T_79,_T_76}; // @[Cat.scala 29:58] + wire [7:0] _T_530 = ld_byte_ibuf_hit_lo[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_533 = ld_byte_ibuf_hit_lo[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_536 = ld_byte_ibuf_hit_lo[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_539 = ld_byte_ibuf_hit_lo[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [31:0] ld_fwddata_buf_lo_initial = {_T_539,_T_536,_T_533,_T_530}; // @[Cat.scala 29:58] + wire [7:0] _T_544 = ld_byte_ibuf_hit_hi[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_547 = ld_byte_ibuf_hit_hi[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_550 = ld_byte_ibuf_hit_hi[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_553 = ld_byte_ibuf_hit_hi[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [31:0] ld_fwddata_buf_hi_initial = {_T_553,_T_550,_T_547,_T_544}; // @[Cat.scala 29:58] + wire [7:0] _T_558 = ld_byte_hitvecfn_lo_3[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + reg [31:0] buf_data_0; // @[lib.scala 374:16] + wire [7:0] _T_560 = _T_558 & buf_data_0[31:24]; // @[lsu_bus_buffer.scala 165:91] + wire [7:0] _T_563 = ld_byte_hitvecfn_lo_3[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + reg [31:0] buf_data_1; // @[lib.scala 374:16] + wire [7:0] _T_565 = _T_563 & buf_data_1[31:24]; // @[lsu_bus_buffer.scala 165:91] + wire [7:0] _T_568 = ld_byte_hitvecfn_lo_3[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + reg [31:0] buf_data_2; // @[lib.scala 374:16] + wire [7:0] _T_570 = _T_568 & buf_data_2[31:24]; // @[lsu_bus_buffer.scala 165:91] + wire [7:0] _T_573 = ld_byte_hitvecfn_lo_3[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + reg [31:0] buf_data_3; // @[lib.scala 374:16] + wire [7:0] _T_575 = _T_573 & buf_data_3[31:24]; // @[lsu_bus_buffer.scala 165:91] + wire [7:0] _T_576 = _T_560 | _T_565; // @[lsu_bus_buffer.scala 165:123] + wire [7:0] _T_577 = _T_576 | _T_570; // @[lsu_bus_buffer.scala 165:123] + wire [7:0] _T_578 = _T_577 | _T_575; // @[lsu_bus_buffer.scala 165:123] + wire [7:0] _T_581 = ld_byte_hitvecfn_lo_2[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_583 = _T_581 & buf_data_0[23:16]; // @[lsu_bus_buffer.scala 166:65] + wire [7:0] _T_586 = ld_byte_hitvecfn_lo_2[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_588 = _T_586 & buf_data_1[23:16]; // @[lsu_bus_buffer.scala 166:65] + wire [7:0] _T_591 = ld_byte_hitvecfn_lo_2[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_593 = _T_591 & buf_data_2[23:16]; // @[lsu_bus_buffer.scala 166:65] + wire [7:0] _T_596 = ld_byte_hitvecfn_lo_2[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_598 = _T_596 & buf_data_3[23:16]; // @[lsu_bus_buffer.scala 166:65] + wire [7:0] _T_599 = _T_583 | _T_588; // @[lsu_bus_buffer.scala 166:97] + wire [7:0] _T_600 = _T_599 | _T_593; // @[lsu_bus_buffer.scala 166:97] + wire [7:0] _T_601 = _T_600 | _T_598; // @[lsu_bus_buffer.scala 166:97] + wire [7:0] _T_604 = ld_byte_hitvecfn_lo_1[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_606 = _T_604 & buf_data_0[15:8]; // @[lsu_bus_buffer.scala 167:65] + wire [7:0] _T_609 = ld_byte_hitvecfn_lo_1[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_611 = _T_609 & buf_data_1[15:8]; // @[lsu_bus_buffer.scala 167:65] + wire [7:0] _T_614 = ld_byte_hitvecfn_lo_1[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_616 = _T_614 & buf_data_2[15:8]; // @[lsu_bus_buffer.scala 167:65] + wire [7:0] _T_619 = ld_byte_hitvecfn_lo_1[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_621 = _T_619 & buf_data_3[15:8]; // @[lsu_bus_buffer.scala 167:65] + wire [7:0] _T_622 = _T_606 | _T_611; // @[lsu_bus_buffer.scala 167:97] + wire [7:0] _T_623 = _T_622 | _T_616; // @[lsu_bus_buffer.scala 167:97] + wire [7:0] _T_624 = _T_623 | _T_621; // @[lsu_bus_buffer.scala 167:97] + wire [7:0] _T_627 = ld_byte_hitvecfn_lo_0[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_629 = _T_627 & buf_data_0[7:0]; // @[lsu_bus_buffer.scala 168:65] + wire [7:0] _T_632 = ld_byte_hitvecfn_lo_0[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_634 = _T_632 & buf_data_1[7:0]; // @[lsu_bus_buffer.scala 168:65] + wire [7:0] _T_637 = ld_byte_hitvecfn_lo_0[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_639 = _T_637 & buf_data_2[7:0]; // @[lsu_bus_buffer.scala 168:65] + wire [7:0] _T_642 = ld_byte_hitvecfn_lo_0[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_644 = _T_642 & buf_data_3[7:0]; // @[lsu_bus_buffer.scala 168:65] + wire [7:0] _T_645 = _T_629 | _T_634; // @[lsu_bus_buffer.scala 168:97] + wire [7:0] _T_646 = _T_645 | _T_639; // @[lsu_bus_buffer.scala 168:97] + wire [7:0] _T_647 = _T_646 | _T_644; // @[lsu_bus_buffer.scala 168:97] + wire [31:0] _T_650 = {_T_578,_T_601,_T_624,_T_647}; // @[Cat.scala 29:58] + reg [31:0] ibuf_data; // @[lib.scala 374:16] + wire [31:0] _T_651 = ld_fwddata_buf_lo_initial & ibuf_data; // @[lsu_bus_buffer.scala 169:32] + wire [7:0] _T_655 = ld_byte_hitvecfn_hi_3[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_657 = _T_655 & buf_data_0[31:24]; // @[lsu_bus_buffer.scala 171:91] + wire [7:0] _T_660 = ld_byte_hitvecfn_hi_3[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_662 = _T_660 & buf_data_1[31:24]; // @[lsu_bus_buffer.scala 171:91] + wire [7:0] _T_665 = ld_byte_hitvecfn_hi_3[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_667 = _T_665 & buf_data_2[31:24]; // @[lsu_bus_buffer.scala 171:91] + wire [7:0] _T_670 = ld_byte_hitvecfn_hi_3[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_672 = _T_670 & buf_data_3[31:24]; // @[lsu_bus_buffer.scala 171:91] + wire [7:0] _T_673 = _T_657 | _T_662; // @[lsu_bus_buffer.scala 171:123] + wire [7:0] _T_674 = _T_673 | _T_667; // @[lsu_bus_buffer.scala 171:123] + wire [7:0] _T_675 = _T_674 | _T_672; // @[lsu_bus_buffer.scala 171:123] + wire [7:0] _T_678 = ld_byte_hitvecfn_hi_2[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_680 = _T_678 & buf_data_0[23:16]; // @[lsu_bus_buffer.scala 172:65] + wire [7:0] _T_683 = ld_byte_hitvecfn_hi_2[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_685 = _T_683 & buf_data_1[23:16]; // @[lsu_bus_buffer.scala 172:65] + wire [7:0] _T_688 = ld_byte_hitvecfn_hi_2[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_690 = _T_688 & buf_data_2[23:16]; // @[lsu_bus_buffer.scala 172:65] + wire [7:0] _T_693 = ld_byte_hitvecfn_hi_2[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_695 = _T_693 & buf_data_3[23:16]; // @[lsu_bus_buffer.scala 172:65] + wire [7:0] _T_696 = _T_680 | _T_685; // @[lsu_bus_buffer.scala 172:97] + wire [7:0] _T_697 = _T_696 | _T_690; // @[lsu_bus_buffer.scala 172:97] + wire [7:0] _T_698 = _T_697 | _T_695; // @[lsu_bus_buffer.scala 172:97] + wire [7:0] _T_701 = ld_byte_hitvecfn_hi_1[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_703 = _T_701 & buf_data_0[15:8]; // @[lsu_bus_buffer.scala 173:65] + wire [7:0] _T_706 = ld_byte_hitvecfn_hi_1[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_708 = _T_706 & buf_data_1[15:8]; // @[lsu_bus_buffer.scala 173:65] + wire [7:0] _T_711 = ld_byte_hitvecfn_hi_1[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_713 = _T_711 & buf_data_2[15:8]; // @[lsu_bus_buffer.scala 173:65] + wire [7:0] _T_716 = ld_byte_hitvecfn_hi_1[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_718 = _T_716 & buf_data_3[15:8]; // @[lsu_bus_buffer.scala 173:65] + wire [7:0] _T_719 = _T_703 | _T_708; // @[lsu_bus_buffer.scala 173:97] + wire [7:0] _T_720 = _T_719 | _T_713; // @[lsu_bus_buffer.scala 173:97] + wire [7:0] _T_721 = _T_720 | _T_718; // @[lsu_bus_buffer.scala 173:97] + wire [7:0] _T_724 = ld_byte_hitvecfn_hi_0[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_726 = _T_724 & buf_data_0[7:0]; // @[lsu_bus_buffer.scala 174:65] + wire [7:0] _T_729 = ld_byte_hitvecfn_hi_0[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_731 = _T_729 & buf_data_1[7:0]; // @[lsu_bus_buffer.scala 174:65] + wire [7:0] _T_734 = ld_byte_hitvecfn_hi_0[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_736 = _T_734 & buf_data_2[7:0]; // @[lsu_bus_buffer.scala 174:65] + wire [7:0] _T_739 = ld_byte_hitvecfn_hi_0[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_741 = _T_739 & buf_data_3[7:0]; // @[lsu_bus_buffer.scala 174:65] + wire [7:0] _T_742 = _T_726 | _T_731; // @[lsu_bus_buffer.scala 174:97] + wire [7:0] _T_743 = _T_742 | _T_736; // @[lsu_bus_buffer.scala 174:97] + wire [7:0] _T_744 = _T_743 | _T_741; // @[lsu_bus_buffer.scala 174:97] + wire [31:0] _T_747 = {_T_675,_T_698,_T_721,_T_744}; // @[Cat.scala 29:58] + wire [31:0] _T_748 = ld_fwddata_buf_hi_initial & ibuf_data; // @[lsu_bus_buffer.scala 175:32] + wire [3:0] _T_750 = io_lsu_pkt_r_bits_by ? 4'h1 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_751 = io_lsu_pkt_r_bits_half ? 4'h3 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_752 = io_lsu_pkt_r_bits_word ? 4'hf : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_753 = _T_750 | _T_751; // @[Mux.scala 27:72] + wire [3:0] ldst_byteen_r = _T_753 | _T_752; // @[Mux.scala 27:72] + wire _T_756 = io_lsu_addr_r[1:0] == 2'h0; // @[lsu_bus_buffer.scala 182:55] + wire _T_758 = io_lsu_addr_r[1:0] == 2'h1; // @[lsu_bus_buffer.scala 183:24] + wire [3:0] _T_760 = {3'h0,ldst_byteen_r[3]}; // @[Cat.scala 29:58] + wire _T_762 = io_lsu_addr_r[1:0] == 2'h2; // @[lsu_bus_buffer.scala 184:24] + wire [3:0] _T_764 = {2'h0,ldst_byteen_r[3:2]}; // @[Cat.scala 29:58] + wire _T_766 = io_lsu_addr_r[1:0] == 2'h3; // @[lsu_bus_buffer.scala 185:24] + wire [3:0] _T_768 = {1'h0,ldst_byteen_r[3:1]}; // @[Cat.scala 29:58] + wire [3:0] _T_770 = _T_758 ? _T_760 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_771 = _T_762 ? _T_764 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_772 = _T_766 ? _T_768 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_774 = _T_770 | _T_771; // @[Mux.scala 27:72] + wire [3:0] ldst_byteen_hi_r = _T_774 | _T_772; // @[Mux.scala 27:72] + wire [3:0] _T_781 = {ldst_byteen_r[2:0],1'h0}; // @[Cat.scala 29:58] + wire [3:0] _T_785 = {ldst_byteen_r[1:0],2'h0}; // @[Cat.scala 29:58] + wire [3:0] _T_789 = {ldst_byteen_r[0],3'h0}; // @[Cat.scala 29:58] + wire [3:0] _T_790 = _T_756 ? ldst_byteen_r : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_791 = _T_758 ? _T_781 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_792 = _T_762 ? _T_785 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_793 = _T_766 ? _T_789 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_794 = _T_790 | _T_791; // @[Mux.scala 27:72] + wire [3:0] _T_795 = _T_794 | _T_792; // @[Mux.scala 27:72] + wire [3:0] ldst_byteen_lo_r = _T_795 | _T_793; // @[Mux.scala 27:72] + wire [31:0] _T_802 = {24'h0,io_store_data_r[31:24]}; // @[Cat.scala 29:58] + wire [31:0] _T_806 = {16'h0,io_store_data_r[31:16]}; // @[Cat.scala 29:58] + wire [31:0] _T_810 = {8'h0,io_store_data_r[31:8]}; // @[Cat.scala 29:58] + wire [31:0] _T_812 = _T_758 ? _T_802 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_813 = _T_762 ? _T_806 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_814 = _T_766 ? _T_810 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_816 = _T_812 | _T_813; // @[Mux.scala 27:72] + wire [31:0] store_data_hi_r = _T_816 | _T_814; // @[Mux.scala 27:72] + wire [31:0] _T_823 = {io_store_data_r[23:0],8'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_827 = {io_store_data_r[15:0],16'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_831 = {io_store_data_r[7:0],24'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_832 = _T_756 ? io_store_data_r : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_833 = _T_758 ? _T_823 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_834 = _T_762 ? _T_827 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_835 = _T_766 ? _T_831 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_836 = _T_832 | _T_833; // @[Mux.scala 27:72] + wire [31:0] _T_837 = _T_836 | _T_834; // @[Mux.scala 27:72] + wire [31:0] store_data_lo_r = _T_837 | _T_835; // @[Mux.scala 27:72] + wire ldst_samedw_r = io_lsu_addr_r[3] == io_end_addr_r[3]; // @[lsu_bus_buffer.scala 203:40] + wire _T_844 = ~io_lsu_addr_r[0]; // @[lsu_bus_buffer.scala 205:31] + wire _T_845 = io_lsu_pkt_r_bits_word & _T_756; // @[Mux.scala 27:72] + wire _T_846 = io_lsu_pkt_r_bits_half & _T_844; // @[Mux.scala 27:72] + wire _T_848 = _T_845 | _T_846; // @[Mux.scala 27:72] + wire is_aligned_r = _T_848 | io_lsu_pkt_r_bits_by; // @[Mux.scala 27:72] + wire _T_850 = io_lsu_pkt_r_bits_load | io_no_word_merge_r; // @[lsu_bus_buffer.scala 207:60] + wire _T_851 = io_lsu_busreq_r & _T_850; // @[lsu_bus_buffer.scala 207:34] + wire _T_852 = ~ibuf_valid; // @[lsu_bus_buffer.scala 207:84] + wire ibuf_byp = _T_851 & _T_852; // @[lsu_bus_buffer.scala 207:82] + wire _T_853 = io_lsu_busreq_r & io_lsu_commit_r; // @[lsu_bus_buffer.scala 208:36] + wire _T_854 = ~ibuf_byp; // @[lsu_bus_buffer.scala 208:56] + wire ibuf_wr_en = _T_853 & _T_854; // @[lsu_bus_buffer.scala 208:54] + wire _T_855 = ~ibuf_wr_en; // @[lsu_bus_buffer.scala 210:36] + reg [2:0] ibuf_timer; // @[lsu_bus_buffer.scala 253:55] + wire _T_864 = ibuf_timer == 3'h7; // @[lsu_bus_buffer.scala 216:62] + wire _T_865 = ibuf_wr_en | _T_864; // @[lsu_bus_buffer.scala 216:48] + wire _T_929 = _T_853 & io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 235:54] + wire _T_930 = _T_929 & ibuf_valid; // @[lsu_bus_buffer.scala 235:80] + wire _T_931 = _T_930 & ibuf_write; // @[lsu_bus_buffer.scala 235:93] + wire _T_934 = io_lsu_addr_r[31:2] == ibuf_addr[31:2]; // @[lsu_bus_buffer.scala 235:129] + wire _T_935 = _T_931 & _T_934; // @[lsu_bus_buffer.scala 235:106] + wire _T_936 = ~io_is_sideeffects_r; // @[lsu_bus_buffer.scala 235:152] + wire _T_937 = _T_935 & _T_936; // @[lsu_bus_buffer.scala 235:150] + wire _T_938 = ~io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_buffer.scala 235:175] + wire ibuf_merge_en = _T_937 & _T_938; // @[lsu_bus_buffer.scala 235:173] + wire ibuf_merge_in = ~io_ldst_dual_r; // @[lsu_bus_buffer.scala 236:20] + wire _T_866 = ibuf_merge_en & ibuf_merge_in; // @[lsu_bus_buffer.scala 216:98] + wire _T_867 = ~_T_866; // @[lsu_bus_buffer.scala 216:82] + wire _T_868 = _T_865 & _T_867; // @[lsu_bus_buffer.scala 216:80] + wire _T_869 = _T_868 | ibuf_byp; // @[lsu_bus_buffer.scala 217:5] + wire _T_857 = ~io_lsu_busreq_r; // @[lsu_bus_buffer.scala 211:44] + wire _T_858 = io_lsu_busreq_m & _T_857; // @[lsu_bus_buffer.scala 211:42] + wire _T_859 = _T_858 & ibuf_valid; // @[lsu_bus_buffer.scala 211:61] + wire _T_862 = ibuf_addr[31:2] != io_lsu_addr_m[31:2]; // @[lsu_bus_buffer.scala 211:120] + wire _T_863 = io_lsu_pkt_m_bits_load | _T_862; // @[lsu_bus_buffer.scala 211:100] + wire ibuf_force_drain = _T_859 & _T_863; // @[lsu_bus_buffer.scala 211:74] + wire _T_870 = _T_869 | ibuf_force_drain; // @[lsu_bus_buffer.scala 217:16] + reg ibuf_sideeffect; // @[Reg.scala 27:20] + wire _T_871 = _T_870 | ibuf_sideeffect; // @[lsu_bus_buffer.scala 217:35] + wire _T_872 = ~ibuf_write; // @[lsu_bus_buffer.scala 217:55] + wire _T_873 = _T_871 | _T_872; // @[lsu_bus_buffer.scala 217:53] + wire _T_874 = _T_873 | io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_buffer.scala 217:67] + wire ibuf_drain_vld = ibuf_valid & _T_874; // @[lsu_bus_buffer.scala 216:32] + wire _T_856 = ibuf_drain_vld & _T_855; // @[lsu_bus_buffer.scala 210:34] + wire ibuf_rst = _T_856 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 210:49] + reg [1:0] WrPtr1_r; // @[lsu_bus_buffer.scala 616:49] + reg [1:0] WrPtr0_r; // @[lsu_bus_buffer.scala 615:49] + reg [1:0] ibuf_tag; // @[Reg.scala 27:20] + wire [1:0] ibuf_sz_in = {io_lsu_pkt_r_bits_word,io_lsu_pkt_r_bits_half}; // @[Cat.scala 29:58] + wire [3:0] _T_881 = ibuf_byteen | ldst_byteen_lo_r; // @[lsu_bus_buffer.scala 226:77] + wire [7:0] _T_889 = ldst_byteen_lo_r[0] ? store_data_lo_r[7:0] : ibuf_data[7:0]; // @[lsu_bus_buffer.scala 231:8] + wire [7:0] _T_892 = io_ldst_dual_r ? store_data_hi_r[7:0] : store_data_lo_r[7:0]; // @[lsu_bus_buffer.scala 232:8] + wire [7:0] _T_893 = _T_866 ? _T_889 : _T_892; // @[lsu_bus_buffer.scala 230:46] + wire [7:0] _T_898 = ldst_byteen_lo_r[1] ? store_data_lo_r[15:8] : ibuf_data[15:8]; // @[lsu_bus_buffer.scala 231:8] + wire [7:0] _T_901 = io_ldst_dual_r ? store_data_hi_r[15:8] : store_data_lo_r[15:8]; // @[lsu_bus_buffer.scala 232:8] + wire [7:0] _T_902 = _T_866 ? _T_898 : _T_901; // @[lsu_bus_buffer.scala 230:46] + wire [7:0] _T_907 = ldst_byteen_lo_r[2] ? store_data_lo_r[23:16] : ibuf_data[23:16]; // @[lsu_bus_buffer.scala 231:8] + wire [7:0] _T_910 = io_ldst_dual_r ? store_data_hi_r[23:16] : store_data_lo_r[23:16]; // @[lsu_bus_buffer.scala 232:8] + wire [7:0] _T_911 = _T_866 ? _T_907 : _T_910; // @[lsu_bus_buffer.scala 230:46] + wire [7:0] _T_916 = ldst_byteen_lo_r[3] ? store_data_lo_r[31:24] : ibuf_data[31:24]; // @[lsu_bus_buffer.scala 231:8] + wire [7:0] _T_919 = io_ldst_dual_r ? store_data_hi_r[31:24] : store_data_lo_r[31:24]; // @[lsu_bus_buffer.scala 232:8] + wire [7:0] _T_920 = _T_866 ? _T_916 : _T_919; // @[lsu_bus_buffer.scala 230:46] + wire [23:0] _T_922 = {_T_920,_T_911,_T_902}; // @[Cat.scala 29:58] + wire _T_923 = ibuf_timer < 3'h7; // @[lsu_bus_buffer.scala 233:59] + wire [2:0] _T_926 = ibuf_timer + 3'h1; // @[lsu_bus_buffer.scala 233:93] + wire _T_941 = ~ibuf_merge_in; // @[lsu_bus_buffer.scala 237:65] + wire _T_942 = ibuf_merge_en & _T_941; // @[lsu_bus_buffer.scala 237:63] + wire _T_945 = ibuf_byteen[0] | ldst_byteen_lo_r[0]; // @[lsu_bus_buffer.scala 237:96] + wire _T_947 = _T_942 ? _T_945 : ibuf_byteen[0]; // @[lsu_bus_buffer.scala 237:48] + wire _T_952 = ibuf_byteen[1] | ldst_byteen_lo_r[1]; // @[lsu_bus_buffer.scala 237:96] + wire _T_954 = _T_942 ? _T_952 : ibuf_byteen[1]; // @[lsu_bus_buffer.scala 237:48] + wire _T_959 = ibuf_byteen[2] | ldst_byteen_lo_r[2]; // @[lsu_bus_buffer.scala 237:96] + wire _T_961 = _T_942 ? _T_959 : ibuf_byteen[2]; // @[lsu_bus_buffer.scala 237:48] + wire _T_966 = ibuf_byteen[3] | ldst_byteen_lo_r[3]; // @[lsu_bus_buffer.scala 237:96] + wire _T_968 = _T_942 ? _T_966 : ibuf_byteen[3]; // @[lsu_bus_buffer.scala 237:48] + wire [3:0] ibuf_byteen_out = {_T_968,_T_961,_T_954,_T_947}; // @[Cat.scala 29:58] + wire [7:0] _T_978 = _T_942 ? _T_889 : ibuf_data[7:0]; // @[lsu_bus_buffer.scala 238:45] + wire [7:0] _T_986 = _T_942 ? _T_898 : ibuf_data[15:8]; // @[lsu_bus_buffer.scala 238:45] + wire [7:0] _T_994 = _T_942 ? _T_907 : ibuf_data[23:16]; // @[lsu_bus_buffer.scala 238:45] + wire [7:0] _T_1002 = _T_942 ? _T_916 : ibuf_data[31:24]; // @[lsu_bus_buffer.scala 238:45] + wire [31:0] ibuf_data_out = {_T_1002,_T_994,_T_986,_T_978}; // @[Cat.scala 29:58] + wire _T_1005 = ibuf_wr_en | ibuf_valid; // @[lsu_bus_buffer.scala 240:58] + wire _T_1006 = ~ibuf_rst; // @[lsu_bus_buffer.scala 240:93] + reg [1:0] ibuf_dualtag; // @[Reg.scala 27:20] + reg ibuf_dual; // @[Reg.scala 27:20] + reg ibuf_samedw; // @[Reg.scala 27:20] + reg ibuf_nomerge; // @[Reg.scala 27:20] + reg ibuf_unsign; // @[Reg.scala 27:20] + reg [1:0] ibuf_sz; // @[Reg.scala 27:20] + wire _T_4446 = buf_write[3] & _T_2621; // @[lsu_bus_buffer.scala 522:64] + wire _T_4447 = ~buf_cmd_state_bus_en_3; // @[lsu_bus_buffer.scala 522:91] + wire _T_4448 = _T_4446 & _T_4447; // @[lsu_bus_buffer.scala 522:89] + wire _T_4441 = buf_write[2] & _T_2616; // @[lsu_bus_buffer.scala 522:64] + wire _T_4442 = ~buf_cmd_state_bus_en_2; // @[lsu_bus_buffer.scala 522:91] + wire _T_4443 = _T_4441 & _T_4442; // @[lsu_bus_buffer.scala 522:89] + wire [1:0] _T_4449 = _T_4448 + _T_4443; // @[lsu_bus_buffer.scala 522:142] + wire _T_4436 = buf_write[1] & _T_2611; // @[lsu_bus_buffer.scala 522:64] + wire _T_4437 = ~buf_cmd_state_bus_en_1; // @[lsu_bus_buffer.scala 522:91] + wire _T_4438 = _T_4436 & _T_4437; // @[lsu_bus_buffer.scala 522:89] + wire [1:0] _GEN_362 = {{1'd0}, _T_4438}; // @[lsu_bus_buffer.scala 522:142] + wire [2:0] _T_4450 = _T_4449 + _GEN_362; // @[lsu_bus_buffer.scala 522:142] + wire _T_4431 = buf_write[0] & _T_2606; // @[lsu_bus_buffer.scala 522:64] + wire _T_4432 = ~buf_cmd_state_bus_en_0; // @[lsu_bus_buffer.scala 522:91] + wire _T_4433 = _T_4431 & _T_4432; // @[lsu_bus_buffer.scala 522:89] + wire [2:0] _GEN_363 = {{2'd0}, _T_4433}; // @[lsu_bus_buffer.scala 522:142] + wire [3:0] buf_numvld_wrcmd_any = _T_4450 + _GEN_363; // @[lsu_bus_buffer.scala 522:142] + wire _T_1016 = buf_numvld_wrcmd_any == 4'h1; // @[lsu_bus_buffer.scala 263:43] + wire _T_4463 = _T_2621 & _T_4447; // @[lsu_bus_buffer.scala 523:73] + wire _T_4460 = _T_2616 & _T_4442; // @[lsu_bus_buffer.scala 523:73] + wire [1:0] _T_4464 = _T_4463 + _T_4460; // @[lsu_bus_buffer.scala 523:126] + wire _T_4457 = _T_2611 & _T_4437; // @[lsu_bus_buffer.scala 523:73] + wire [1:0] _GEN_364 = {{1'd0}, _T_4457}; // @[lsu_bus_buffer.scala 523:126] + wire [2:0] _T_4465 = _T_4464 + _GEN_364; // @[lsu_bus_buffer.scala 523:126] + wire _T_4454 = _T_2606 & _T_4432; // @[lsu_bus_buffer.scala 523:73] + wire [2:0] _GEN_365 = {{2'd0}, _T_4454}; // @[lsu_bus_buffer.scala 523:126] + wire [3:0] buf_numvld_cmd_any = _T_4465 + _GEN_365; // @[lsu_bus_buffer.scala 523:126] + wire _T_1017 = buf_numvld_cmd_any == 4'h1; // @[lsu_bus_buffer.scala 263:72] + wire _T_1018 = _T_1016 & _T_1017; // @[lsu_bus_buffer.scala 263:51] + reg [2:0] obuf_wr_timer; // @[lsu_bus_buffer.scala 361:54] + wire _T_1019 = obuf_wr_timer != 3'h7; // @[lsu_bus_buffer.scala 263:97] + wire _T_1020 = _T_1018 & _T_1019; // @[lsu_bus_buffer.scala 263:80] + wire _T_1022 = _T_1020 & _T_938; // @[lsu_bus_buffer.scala 263:114] + wire _T_1979 = |buf_age_3; // @[lsu_bus_buffer.scala 378:58] + wire _T_1980 = ~_T_1979; // @[lsu_bus_buffer.scala 378:45] + wire _T_1982 = _T_1980 & _T_2621; // @[lsu_bus_buffer.scala 378:63] + wire _T_1984 = _T_1982 & _T_4447; // @[lsu_bus_buffer.scala 378:88] + wire _T_1973 = |buf_age_2; // @[lsu_bus_buffer.scala 378:58] + wire _T_1974 = ~_T_1973; // @[lsu_bus_buffer.scala 378:45] + wire _T_1976 = _T_1974 & _T_2616; // @[lsu_bus_buffer.scala 378:63] + wire _T_1978 = _T_1976 & _T_4442; // @[lsu_bus_buffer.scala 378:88] + wire _T_1967 = |buf_age_1; // @[lsu_bus_buffer.scala 378:58] + wire _T_1968 = ~_T_1967; // @[lsu_bus_buffer.scala 378:45] + wire _T_1970 = _T_1968 & _T_2611; // @[lsu_bus_buffer.scala 378:63] + wire _T_1972 = _T_1970 & _T_4437; // @[lsu_bus_buffer.scala 378:88] + wire _T_1961 = |buf_age_0; // @[lsu_bus_buffer.scala 378:58] + wire _T_1962 = ~_T_1961; // @[lsu_bus_buffer.scala 378:45] + wire _T_1964 = _T_1962 & _T_2606; // @[lsu_bus_buffer.scala 378:63] + wire _T_1966 = _T_1964 & _T_4432; // @[lsu_bus_buffer.scala 378:88] + wire [3:0] CmdPtr0Dec = {_T_1984,_T_1978,_T_1972,_T_1966}; // @[Cat.scala 29:58] + wire [7:0] _T_2054 = {4'h0,_T_1984,_T_1978,_T_1972,_T_1966}; // @[Cat.scala 29:58] + wire _T_2057 = _T_2054[4] | _T_2054[5]; // @[lsu_bus_buffer.scala 386:42] + wire _T_2059 = _T_2057 | _T_2054[6]; // @[lsu_bus_buffer.scala 386:48] + wire _T_2061 = _T_2059 | _T_2054[7]; // @[lsu_bus_buffer.scala 386:54] + wire _T_2064 = _T_2054[2] | _T_2054[3]; // @[lsu_bus_buffer.scala 386:67] + wire _T_2066 = _T_2064 | _T_2054[6]; // @[lsu_bus_buffer.scala 386:73] + wire _T_2068 = _T_2066 | _T_2054[7]; // @[lsu_bus_buffer.scala 386:79] + wire _T_2071 = _T_2054[1] | _T_2054[3]; // @[lsu_bus_buffer.scala 386:92] + wire _T_2073 = _T_2071 | _T_2054[5]; // @[lsu_bus_buffer.scala 386:98] + wire _T_2075 = _T_2073 | _T_2054[7]; // @[lsu_bus_buffer.scala 386:104] + wire [2:0] _T_2077 = {_T_2061,_T_2068,_T_2075}; // @[Cat.scala 29:58] + wire [1:0] CmdPtr0 = _T_2077[1:0]; // @[lsu_bus_buffer.scala 391:11] + wire _T_1023 = CmdPtr0 == 2'h0; // @[lsu_bus_buffer.scala 264:114] + wire _T_1024 = CmdPtr0 == 2'h1; // @[lsu_bus_buffer.scala 264:114] + wire _T_1025 = CmdPtr0 == 2'h2; // @[lsu_bus_buffer.scala 264:114] + wire _T_1026 = CmdPtr0 == 2'h3; // @[lsu_bus_buffer.scala 264:114] + reg buf_nomerge_0; // @[Reg.scala 27:20] + wire _T_1027 = _T_1023 & buf_nomerge_0; // @[Mux.scala 27:72] + reg buf_nomerge_1; // @[Reg.scala 27:20] + wire _T_1028 = _T_1024 & buf_nomerge_1; // @[Mux.scala 27:72] + reg buf_nomerge_2; // @[Reg.scala 27:20] + wire _T_1029 = _T_1025 & buf_nomerge_2; // @[Mux.scala 27:72] + reg buf_nomerge_3; // @[Reg.scala 27:20] + wire _T_1030 = _T_1026 & buf_nomerge_3; // @[Mux.scala 27:72] + wire _T_1031 = _T_1027 | _T_1028; // @[Mux.scala 27:72] + wire _T_1032 = _T_1031 | _T_1029; // @[Mux.scala 27:72] + wire _T_1033 = _T_1032 | _T_1030; // @[Mux.scala 27:72] + wire _T_1035 = ~_T_1033; // @[lsu_bus_buffer.scala 264:31] + wire _T_1036 = _T_1022 & _T_1035; // @[lsu_bus_buffer.scala 264:29] + reg _T_4330; // @[Reg.scala 27:20] + reg _T_4327; // @[Reg.scala 27:20] + reg _T_4324; // @[Reg.scala 27:20] + reg _T_4321; // @[Reg.scala 27:20] + wire [3:0] buf_sideeffect = {_T_4330,_T_4327,_T_4324,_T_4321}; // @[Cat.scala 29:58] + wire _T_1045 = _T_1023 & buf_sideeffect[0]; // @[Mux.scala 27:72] + wire _T_1046 = _T_1024 & buf_sideeffect[1]; // @[Mux.scala 27:72] + wire _T_1047 = _T_1025 & buf_sideeffect[2]; // @[Mux.scala 27:72] + wire _T_1048 = _T_1026 & buf_sideeffect[3]; // @[Mux.scala 27:72] + wire _T_1049 = _T_1045 | _T_1046; // @[Mux.scala 27:72] + wire _T_1050 = _T_1049 | _T_1047; // @[Mux.scala 27:72] + wire _T_1051 = _T_1050 | _T_1048; // @[Mux.scala 27:72] + wire _T_1053 = ~_T_1051; // @[lsu_bus_buffer.scala 265:5] + wire _T_1054 = _T_1036 & _T_1053; // @[lsu_bus_buffer.scala 264:140] + wire _T_1065 = _T_858 & _T_852; // @[lsu_bus_buffer.scala 267:58] + wire _T_1067 = _T_1065 & _T_1017; // @[lsu_bus_buffer.scala 267:72] + wire [29:0] _T_1077 = _T_1023 ? buf_addr_0[31:2] : 30'h0; // @[Mux.scala 27:72] + wire [29:0] _T_1078 = _T_1024 ? buf_addr_1[31:2] : 30'h0; // @[Mux.scala 27:72] + wire [29:0] _T_1081 = _T_1077 | _T_1078; // @[Mux.scala 27:72] + wire [29:0] _T_1079 = _T_1025 ? buf_addr_2[31:2] : 30'h0; // @[Mux.scala 27:72] + wire [29:0] _T_1082 = _T_1081 | _T_1079; // @[Mux.scala 27:72] + wire [29:0] _T_1080 = _T_1026 ? buf_addr_3[31:2] : 30'h0; // @[Mux.scala 27:72] + wire [29:0] _T_1083 = _T_1082 | _T_1080; // @[Mux.scala 27:72] + wire _T_1085 = io_lsu_addr_m[31:2] != _T_1083; // @[lsu_bus_buffer.scala 267:123] + wire obuf_force_wr_en = _T_1067 & _T_1085; // @[lsu_bus_buffer.scala 267:101] + wire _T_1055 = ~obuf_force_wr_en; // @[lsu_bus_buffer.scala 265:119] + wire obuf_wr_wait = _T_1054 & _T_1055; // @[lsu_bus_buffer.scala 265:117] + wire _T_1056 = |buf_numvld_cmd_any; // @[lsu_bus_buffer.scala 266:75] + wire _T_1057 = obuf_wr_timer < 3'h7; // @[lsu_bus_buffer.scala 266:95] + wire _T_1058 = _T_1056 & _T_1057; // @[lsu_bus_buffer.scala 266:79] + wire [2:0] _T_1060 = obuf_wr_timer + 3'h1; // @[lsu_bus_buffer.scala 266:123] + wire _T_4482 = buf_state_3 == 3'h1; // @[lsu_bus_buffer.scala 524:63] + wire _T_4486 = _T_4482 | _T_4463; // @[lsu_bus_buffer.scala 524:74] + wire _T_4477 = buf_state_2 == 3'h1; // @[lsu_bus_buffer.scala 524:63] + wire _T_4481 = _T_4477 | _T_4460; // @[lsu_bus_buffer.scala 524:74] + wire [1:0] _T_4487 = _T_4486 + _T_4481; // @[lsu_bus_buffer.scala 524:154] + wire _T_4472 = buf_state_1 == 3'h1; // @[lsu_bus_buffer.scala 524:63] + wire _T_4476 = _T_4472 | _T_4457; // @[lsu_bus_buffer.scala 524:74] + wire [1:0] _GEN_366 = {{1'd0}, _T_4476}; // @[lsu_bus_buffer.scala 524:154] + wire [2:0] _T_4488 = _T_4487 + _GEN_366; // @[lsu_bus_buffer.scala 524:154] + wire _T_4467 = buf_state_0 == 3'h1; // @[lsu_bus_buffer.scala 524:63] + wire _T_4471 = _T_4467 | _T_4454; // @[lsu_bus_buffer.scala 524:74] + wire [2:0] _GEN_367 = {{2'd0}, _T_4471}; // @[lsu_bus_buffer.scala 524:154] + wire [3:0] buf_numvld_pend_any = _T_4488 + _GEN_367; // @[lsu_bus_buffer.scala 524:154] + wire _T_1087 = buf_numvld_pend_any == 4'h0; // @[lsu_bus_buffer.scala 269:53] + wire _T_1088 = ibuf_byp & _T_1087; // @[lsu_bus_buffer.scala 269:31] + wire _T_1089 = ~io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 269:64] + wire _T_1090 = _T_1089 | io_no_dword_merge_r; // @[lsu_bus_buffer.scala 269:89] + wire ibuf_buf_byp = _T_1088 & _T_1090; // @[lsu_bus_buffer.scala 269:61] + wire _T_1091 = ibuf_buf_byp & io_lsu_commit_r; // @[lsu_bus_buffer.scala 284:32] + wire _T_4778 = buf_state_0 == 3'h3; // @[lsu_bus_buffer.scala 552:62] + wire _T_4780 = _T_4778 & buf_sideeffect[0]; // @[lsu_bus_buffer.scala 552:73] + wire _T_4781 = _T_4780 & io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_buffer.scala 552:93] + wire _T_4782 = buf_state_1 == 3'h3; // @[lsu_bus_buffer.scala 552:62] + wire _T_4784 = _T_4782 & buf_sideeffect[1]; // @[lsu_bus_buffer.scala 552:73] + wire _T_4785 = _T_4784 & io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_buffer.scala 552:93] + wire _T_4794 = _T_4781 | _T_4785; // @[lsu_bus_buffer.scala 552:153] + wire _T_4786 = buf_state_2 == 3'h3; // @[lsu_bus_buffer.scala 552:62] + wire _T_4788 = _T_4786 & buf_sideeffect[2]; // @[lsu_bus_buffer.scala 552:73] + wire _T_4789 = _T_4788 & io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_buffer.scala 552:93] + wire _T_4795 = _T_4794 | _T_4789; // @[lsu_bus_buffer.scala 552:153] + wire _T_4790 = buf_state_3 == 3'h3; // @[lsu_bus_buffer.scala 552:62] + wire _T_4792 = _T_4790 & buf_sideeffect[3]; // @[lsu_bus_buffer.scala 552:73] + wire _T_4793 = _T_4792 & io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_buffer.scala 552:93] + wire _T_4796 = _T_4795 | _T_4793; // @[lsu_bus_buffer.scala 552:153] + reg obuf_sideeffect; // @[Reg.scala 27:20] + wire _T_4797 = obuf_valid & obuf_sideeffect; // @[lsu_bus_buffer.scala 552:171] + wire _T_4798 = _T_4797 & io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_buffer.scala 552:189] + wire bus_sideeffect_pend = _T_4796 | _T_4798; // @[lsu_bus_buffer.scala 552:157] + wire _T_1092 = io_is_sideeffects_r & bus_sideeffect_pend; // @[lsu_bus_buffer.scala 284:74] + wire _T_1093 = ~_T_1092; // @[lsu_bus_buffer.scala 284:52] + wire _T_1094 = _T_1091 & _T_1093; // @[lsu_bus_buffer.scala 284:50] + wire [2:0] _T_1099 = _T_1023 ? buf_state_0 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1100 = _T_1024 ? buf_state_1 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1103 = _T_1099 | _T_1100; // @[Mux.scala 27:72] + wire [2:0] _T_1101 = _T_1025 ? buf_state_2 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1104 = _T_1103 | _T_1101; // @[Mux.scala 27:72] + wire [2:0] _T_1102 = _T_1026 ? buf_state_3 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1105 = _T_1104 | _T_1102; // @[Mux.scala 27:72] + wire _T_1107 = _T_1105 == 3'h2; // @[lsu_bus_buffer.scala 285:36] + wire found_cmdptr0 = |CmdPtr0Dec; // @[lsu_bus_buffer.scala 383:31] + wire _T_1108 = _T_1107 & found_cmdptr0; // @[lsu_bus_buffer.scala 285:47] + wire [3:0] _T_1111 = {buf_cmd_state_bus_en_3,buf_cmd_state_bus_en_2,buf_cmd_state_bus_en_1,buf_cmd_state_bus_en_0}; // @[Cat.scala 29:58] + wire _T_1120 = _T_1023 & _T_1111[0]; // @[Mux.scala 27:72] + wire _T_1121 = _T_1024 & _T_1111[1]; // @[Mux.scala 27:72] + wire _T_1124 = _T_1120 | _T_1121; // @[Mux.scala 27:72] + wire _T_1122 = _T_1025 & _T_1111[2]; // @[Mux.scala 27:72] + wire _T_1125 = _T_1124 | _T_1122; // @[Mux.scala 27:72] + wire _T_1123 = _T_1026 & _T_1111[3]; // @[Mux.scala 27:72] + wire _T_1126 = _T_1125 | _T_1123; // @[Mux.scala 27:72] + wire _T_1128 = ~_T_1126; // @[lsu_bus_buffer.scala 286:23] + wire _T_1129 = _T_1108 & _T_1128; // @[lsu_bus_buffer.scala 286:21] + wire _T_1146 = _T_1051 & bus_sideeffect_pend; // @[lsu_bus_buffer.scala 286:141] + wire _T_1147 = ~_T_1146; // @[lsu_bus_buffer.scala 286:105] + wire _T_1148 = _T_1129 & _T_1147; // @[lsu_bus_buffer.scala 286:103] + reg buf_dual_3; // @[Reg.scala 27:20] + reg buf_dual_2; // @[Reg.scala 27:20] + reg buf_dual_1; // @[Reg.scala 27:20] + reg buf_dual_0; // @[Reg.scala 27:20] + wire [3:0] _T_1151 = {buf_dual_3,buf_dual_2,buf_dual_1,buf_dual_0}; // @[Cat.scala 29:58] + wire _T_1160 = _T_1023 & _T_1151[0]; // @[Mux.scala 27:72] + wire _T_1161 = _T_1024 & _T_1151[1]; // @[Mux.scala 27:72] + wire _T_1164 = _T_1160 | _T_1161; // @[Mux.scala 27:72] + wire _T_1162 = _T_1025 & _T_1151[2]; // @[Mux.scala 27:72] + wire _T_1165 = _T_1164 | _T_1162; // @[Mux.scala 27:72] + wire _T_1163 = _T_1026 & _T_1151[3]; // @[Mux.scala 27:72] + wire _T_1166 = _T_1165 | _T_1163; // @[Mux.scala 27:72] + reg buf_samedw_3; // @[Reg.scala 27:20] + reg buf_samedw_2; // @[Reg.scala 27:20] + reg buf_samedw_1; // @[Reg.scala 27:20] + reg buf_samedw_0; // @[Reg.scala 27:20] + wire [3:0] _T_1170 = {buf_samedw_3,buf_samedw_2,buf_samedw_1,buf_samedw_0}; // @[Cat.scala 29:58] + wire _T_1179 = _T_1023 & _T_1170[0]; // @[Mux.scala 27:72] + wire _T_1180 = _T_1024 & _T_1170[1]; // @[Mux.scala 27:72] + wire _T_1183 = _T_1179 | _T_1180; // @[Mux.scala 27:72] + wire _T_1181 = _T_1025 & _T_1170[2]; // @[Mux.scala 27:72] + wire _T_1184 = _T_1183 | _T_1181; // @[Mux.scala 27:72] + wire _T_1182 = _T_1026 & _T_1170[3]; // @[Mux.scala 27:72] + wire _T_1185 = _T_1184 | _T_1182; // @[Mux.scala 27:72] + wire _T_1187 = _T_1166 & _T_1185; // @[lsu_bus_buffer.scala 287:77] + wire _T_1196 = _T_1023 & buf_write[0]; // @[Mux.scala 27:72] + wire _T_1197 = _T_1024 & buf_write[1]; // @[Mux.scala 27:72] + wire _T_1200 = _T_1196 | _T_1197; // @[Mux.scala 27:72] + wire _T_1198 = _T_1025 & buf_write[2]; // @[Mux.scala 27:72] + wire _T_1201 = _T_1200 | _T_1198; // @[Mux.scala 27:72] + wire _T_1199 = _T_1026 & buf_write[3]; // @[Mux.scala 27:72] + wire _T_1202 = _T_1201 | _T_1199; // @[Mux.scala 27:72] + wire _T_1204 = ~_T_1202; // @[lsu_bus_buffer.scala 287:150] + wire _T_1205 = _T_1187 & _T_1204; // @[lsu_bus_buffer.scala 287:148] + wire _T_1206 = ~_T_1205; // @[lsu_bus_buffer.scala 287:8] + wire [3:0] _T_2020 = ~CmdPtr0Dec; // @[lsu_bus_buffer.scala 379:62] + wire [3:0] _T_2021 = buf_age_3 & _T_2020; // @[lsu_bus_buffer.scala 379:59] + wire _T_2022 = |_T_2021; // @[lsu_bus_buffer.scala 379:76] + wire _T_2023 = ~_T_2022; // @[lsu_bus_buffer.scala 379:45] + wire _T_2025 = ~CmdPtr0Dec[3]; // @[lsu_bus_buffer.scala 379:83] + wire _T_2026 = _T_2023 & _T_2025; // @[lsu_bus_buffer.scala 379:81] + wire _T_2028 = _T_2026 & _T_2621; // @[lsu_bus_buffer.scala 379:98] + wire _T_2030 = _T_2028 & _T_4447; // @[lsu_bus_buffer.scala 379:123] + wire [3:0] _T_2010 = buf_age_2 & _T_2020; // @[lsu_bus_buffer.scala 379:59] + wire _T_2011 = |_T_2010; // @[lsu_bus_buffer.scala 379:76] + wire _T_2012 = ~_T_2011; // @[lsu_bus_buffer.scala 379:45] + wire _T_2014 = ~CmdPtr0Dec[2]; // @[lsu_bus_buffer.scala 379:83] + wire _T_2015 = _T_2012 & _T_2014; // @[lsu_bus_buffer.scala 379:81] + wire _T_2017 = _T_2015 & _T_2616; // @[lsu_bus_buffer.scala 379:98] + wire _T_2019 = _T_2017 & _T_4442; // @[lsu_bus_buffer.scala 379:123] + wire [3:0] _T_1999 = buf_age_1 & _T_2020; // @[lsu_bus_buffer.scala 379:59] + wire _T_2000 = |_T_1999; // @[lsu_bus_buffer.scala 379:76] + wire _T_2001 = ~_T_2000; // @[lsu_bus_buffer.scala 379:45] + wire _T_2003 = ~CmdPtr0Dec[1]; // @[lsu_bus_buffer.scala 379:83] + wire _T_2004 = _T_2001 & _T_2003; // @[lsu_bus_buffer.scala 379:81] + wire _T_2006 = _T_2004 & _T_2611; // @[lsu_bus_buffer.scala 379:98] + wire _T_2008 = _T_2006 & _T_4437; // @[lsu_bus_buffer.scala 379:123] + wire [3:0] _T_1988 = buf_age_0 & _T_2020; // @[lsu_bus_buffer.scala 379:59] + wire _T_1989 = |_T_1988; // @[lsu_bus_buffer.scala 379:76] + wire _T_1990 = ~_T_1989; // @[lsu_bus_buffer.scala 379:45] + wire _T_1992 = ~CmdPtr0Dec[0]; // @[lsu_bus_buffer.scala 379:83] + wire _T_1993 = _T_1990 & _T_1992; // @[lsu_bus_buffer.scala 379:81] + wire _T_1995 = _T_1993 & _T_2606; // @[lsu_bus_buffer.scala 379:98] + wire _T_1997 = _T_1995 & _T_4432; // @[lsu_bus_buffer.scala 379:123] + wire [3:0] CmdPtr1Dec = {_T_2030,_T_2019,_T_2008,_T_1997}; // @[Cat.scala 29:58] + wire found_cmdptr1 = |CmdPtr1Dec; // @[lsu_bus_buffer.scala 384:31] + wire _T_1207 = _T_1206 | found_cmdptr1; // @[lsu_bus_buffer.scala 287:181] + wire [3:0] _T_1210 = {buf_nomerge_3,buf_nomerge_2,buf_nomerge_1,buf_nomerge_0}; // @[Cat.scala 29:58] + wire _T_1219 = _T_1023 & _T_1210[0]; // @[Mux.scala 27:72] + wire _T_1220 = _T_1024 & _T_1210[1]; // @[Mux.scala 27:72] + wire _T_1223 = _T_1219 | _T_1220; // @[Mux.scala 27:72] + wire _T_1221 = _T_1025 & _T_1210[2]; // @[Mux.scala 27:72] + wire _T_1224 = _T_1223 | _T_1221; // @[Mux.scala 27:72] + wire _T_1222 = _T_1026 & _T_1210[3]; // @[Mux.scala 27:72] + wire _T_1225 = _T_1224 | _T_1222; // @[Mux.scala 27:72] + wire _T_1227 = _T_1207 | _T_1225; // @[lsu_bus_buffer.scala 287:197] + wire _T_1228 = _T_1227 | obuf_force_wr_en; // @[lsu_bus_buffer.scala 287:269] + wire _T_1229 = _T_1148 & _T_1228; // @[lsu_bus_buffer.scala 286:164] + wire _T_1230 = _T_1094 | _T_1229; // @[lsu_bus_buffer.scala 284:98] + reg obuf_write; // @[Reg.scala 27:20] + reg obuf_cmd_done; // @[lsu_bus_buffer.scala 348:54] + reg obuf_data_done; // @[lsu_bus_buffer.scala 349:55] + wire _T_4856 = obuf_cmd_done | obuf_data_done; // @[lsu_bus_buffer.scala 556:54] + wire _T_4857 = obuf_cmd_done ? io_lsu_axi_w_ready : io_lsu_axi_aw_ready; // @[lsu_bus_buffer.scala 556:75] + wire _T_4858 = io_lsu_axi_aw_ready & io_lsu_axi_w_ready; // @[lsu_bus_buffer.scala 556:153] + wire _T_4859 = _T_4856 ? _T_4857 : _T_4858; // @[lsu_bus_buffer.scala 556:39] + wire bus_cmd_ready = obuf_write ? _T_4859 : io_lsu_axi_ar_ready; // @[lsu_bus_buffer.scala 556:23] + wire _T_1231 = ~obuf_valid; // @[lsu_bus_buffer.scala 288:48] + wire _T_1232 = bus_cmd_ready | _T_1231; // @[lsu_bus_buffer.scala 288:46] + reg obuf_nosend; // @[Reg.scala 27:20] + wire _T_1233 = _T_1232 | obuf_nosend; // @[lsu_bus_buffer.scala 288:60] + wire _T_1234 = _T_1230 & _T_1233; // @[lsu_bus_buffer.scala 288:29] + wire _T_1235 = ~obuf_wr_wait; // @[lsu_bus_buffer.scala 288:77] + wire _T_1236 = _T_1234 & _T_1235; // @[lsu_bus_buffer.scala 288:75] + reg [31:0] obuf_addr; // @[lib.scala 374:16] + wire _T_4804 = obuf_addr[31:3] == buf_addr_0[31:3]; // @[lsu_bus_buffer.scala 554:56] + wire _T_4805 = obuf_valid & _T_4804; // @[lsu_bus_buffer.scala 554:38] + wire _T_4807 = obuf_tag1 == 2'h0; // @[lsu_bus_buffer.scala 554:126] + wire _T_4808 = obuf_merge & _T_4807; // @[lsu_bus_buffer.scala 554:114] + wire _T_4809 = _T_3562 | _T_4808; // @[lsu_bus_buffer.scala 554:100] + wire _T_4810 = ~_T_4809; // @[lsu_bus_buffer.scala 554:80] + wire _T_4811 = _T_4805 & _T_4810; // @[lsu_bus_buffer.scala 554:78] + wire _T_4848 = _T_4778 & _T_4811; // @[Mux.scala 27:72] + wire _T_4816 = obuf_addr[31:3] == buf_addr_1[31:3]; // @[lsu_bus_buffer.scala 554:56] + wire _T_4817 = obuf_valid & _T_4816; // @[lsu_bus_buffer.scala 554:38] + wire _T_4819 = obuf_tag1 == 2'h1; // @[lsu_bus_buffer.scala 554:126] + wire _T_4820 = obuf_merge & _T_4819; // @[lsu_bus_buffer.scala 554:114] + wire _T_4821 = _T_3755 | _T_4820; // @[lsu_bus_buffer.scala 554:100] + wire _T_4822 = ~_T_4821; // @[lsu_bus_buffer.scala 554:80] + wire _T_4823 = _T_4817 & _T_4822; // @[lsu_bus_buffer.scala 554:78] + wire _T_4849 = _T_4782 & _T_4823; // @[Mux.scala 27:72] + wire _T_4852 = _T_4848 | _T_4849; // @[Mux.scala 27:72] + wire _T_4828 = obuf_addr[31:3] == buf_addr_2[31:3]; // @[lsu_bus_buffer.scala 554:56] + wire _T_4829 = obuf_valid & _T_4828; // @[lsu_bus_buffer.scala 554:38] + wire _T_4831 = obuf_tag1 == 2'h2; // @[lsu_bus_buffer.scala 554:126] + wire _T_4832 = obuf_merge & _T_4831; // @[lsu_bus_buffer.scala 554:114] + wire _T_4833 = _T_3948 | _T_4832; // @[lsu_bus_buffer.scala 554:100] + wire _T_4834 = ~_T_4833; // @[lsu_bus_buffer.scala 554:80] + wire _T_4835 = _T_4829 & _T_4834; // @[lsu_bus_buffer.scala 554:78] + wire _T_4850 = _T_4786 & _T_4835; // @[Mux.scala 27:72] + wire _T_4853 = _T_4852 | _T_4850; // @[Mux.scala 27:72] + wire _T_4840 = obuf_addr[31:3] == buf_addr_3[31:3]; // @[lsu_bus_buffer.scala 554:56] + wire _T_4841 = obuf_valid & _T_4840; // @[lsu_bus_buffer.scala 554:38] + wire _T_4843 = obuf_tag1 == 2'h3; // @[lsu_bus_buffer.scala 554:126] + wire _T_4844 = obuf_merge & _T_4843; // @[lsu_bus_buffer.scala 554:114] + wire _T_4845 = _T_4141 | _T_4844; // @[lsu_bus_buffer.scala 554:100] + wire _T_4846 = ~_T_4845; // @[lsu_bus_buffer.scala 554:80] + wire _T_4847 = _T_4841 & _T_4846; // @[lsu_bus_buffer.scala 554:78] + wire _T_4851 = _T_4790 & _T_4847; // @[Mux.scala 27:72] + wire bus_addr_match_pending = _T_4853 | _T_4851; // @[Mux.scala 27:72] + wire _T_1239 = ~bus_addr_match_pending; // @[lsu_bus_buffer.scala 288:118] + wire _T_1240 = _T_1236 & _T_1239; // @[lsu_bus_buffer.scala 288:116] + wire obuf_wr_en = _T_1240 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 288:142] + wire _T_1242 = obuf_valid & obuf_nosend; // @[lsu_bus_buffer.scala 290:47] + wire bus_wcmd_sent = io_lsu_axi_aw_valid & io_lsu_axi_aw_ready; // @[lsu_bus_buffer.scala 557:40] + wire _T_4863 = obuf_cmd_done | bus_wcmd_sent; // @[lsu_bus_buffer.scala 559:35] + wire bus_wdata_sent = io_lsu_axi_w_valid & io_lsu_axi_w_ready; // @[lsu_bus_buffer.scala 558:40] + wire _T_4864 = obuf_data_done | bus_wdata_sent; // @[lsu_bus_buffer.scala 559:70] + wire _T_4865 = _T_4863 & _T_4864; // @[lsu_bus_buffer.scala 559:52] + wire _T_4866 = io_lsu_axi_ar_valid & io_lsu_axi_ar_ready; // @[lsu_bus_buffer.scala 559:112] + wire bus_cmd_sent = _T_4865 | _T_4866; // @[lsu_bus_buffer.scala 559:89] + wire _T_1243 = bus_cmd_sent | _T_1242; // @[lsu_bus_buffer.scala 290:33] + wire _T_1244 = ~obuf_wr_en; // @[lsu_bus_buffer.scala 290:65] + wire _T_1245 = _T_1243 & _T_1244; // @[lsu_bus_buffer.scala 290:63] + wire _T_1246 = _T_1245 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 290:77] + wire obuf_rst = _T_1246 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 290:98] + wire obuf_write_in = ibuf_buf_byp ? io_lsu_pkt_r_bits_store : _T_1202; // @[lsu_bus_buffer.scala 291:26] + wire [31:0] _T_1283 = _T_1023 ? buf_addr_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1284 = _T_1024 ? buf_addr_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1285 = _T_1025 ? buf_addr_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1286 = _T_1026 ? buf_addr_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1287 = _T_1283 | _T_1284; // @[Mux.scala 27:72] + wire [31:0] _T_1288 = _T_1287 | _T_1285; // @[Mux.scala 27:72] + wire [31:0] _T_1289 = _T_1288 | _T_1286; // @[Mux.scala 27:72] + wire [31:0] obuf_addr_in = ibuf_buf_byp ? io_lsu_addr_r : _T_1289; // @[lsu_bus_buffer.scala 293:25] + reg [1:0] buf_sz_0; // @[Reg.scala 27:20] + wire [1:0] _T_1296 = _T_1023 ? buf_sz_0 : 2'h0; // @[Mux.scala 27:72] + reg [1:0] buf_sz_1; // @[Reg.scala 27:20] + wire [1:0] _T_1297 = _T_1024 ? buf_sz_1 : 2'h0; // @[Mux.scala 27:72] + reg [1:0] buf_sz_2; // @[Reg.scala 27:20] + wire [1:0] _T_1298 = _T_1025 ? buf_sz_2 : 2'h0; // @[Mux.scala 27:72] + reg [1:0] buf_sz_3; // @[Reg.scala 27:20] + wire [1:0] _T_1299 = _T_1026 ? buf_sz_3 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_1300 = _T_1296 | _T_1297; // @[Mux.scala 27:72] + wire [1:0] _T_1301 = _T_1300 | _T_1298; // @[Mux.scala 27:72] + wire [1:0] _T_1302 = _T_1301 | _T_1299; // @[Mux.scala 27:72] + wire [1:0] obuf_sz_in = ibuf_buf_byp ? ibuf_sz_in : _T_1302; // @[lsu_bus_buffer.scala 296:23] + wire [7:0] _T_2079 = {4'h0,_T_2030,_T_2019,_T_2008,_T_1997}; // @[Cat.scala 29:58] + wire _T_2082 = _T_2079[4] | _T_2079[5]; // @[lsu_bus_buffer.scala 386:42] + wire _T_2084 = _T_2082 | _T_2079[6]; // @[lsu_bus_buffer.scala 386:48] + wire _T_2086 = _T_2084 | _T_2079[7]; // @[lsu_bus_buffer.scala 386:54] + wire _T_2089 = _T_2079[2] | _T_2079[3]; // @[lsu_bus_buffer.scala 386:67] + wire _T_2091 = _T_2089 | _T_2079[6]; // @[lsu_bus_buffer.scala 386:73] + wire _T_2093 = _T_2091 | _T_2079[7]; // @[lsu_bus_buffer.scala 386:79] + wire _T_2096 = _T_2079[1] | _T_2079[3]; // @[lsu_bus_buffer.scala 386:92] + wire _T_2098 = _T_2096 | _T_2079[5]; // @[lsu_bus_buffer.scala 386:98] + wire _T_2100 = _T_2098 | _T_2079[7]; // @[lsu_bus_buffer.scala 386:104] + wire [2:0] _T_2102 = {_T_2086,_T_2093,_T_2100}; // @[Cat.scala 29:58] + wire [1:0] CmdPtr1 = _T_2102[1:0]; // @[lsu_bus_buffer.scala 393:11] + wire _T_1304 = obuf_wr_en | obuf_rst; // @[lsu_bus_buffer.scala 304:39] + wire _T_1305 = ~_T_1304; // @[lsu_bus_buffer.scala 304:26] + wire _T_1311 = obuf_sz_in == 2'h0; // @[lsu_bus_buffer.scala 308:72] + wire _T_1314 = ~obuf_addr_in[0]; // @[lsu_bus_buffer.scala 308:98] + wire _T_1315 = obuf_sz_in[0] & _T_1314; // @[lsu_bus_buffer.scala 308:96] + wire _T_1316 = _T_1311 | _T_1315; // @[lsu_bus_buffer.scala 308:79] + wire _T_1319 = |obuf_addr_in[1:0]; // @[lsu_bus_buffer.scala 308:153] + wire _T_1320 = ~_T_1319; // @[lsu_bus_buffer.scala 308:134] + wire _T_1321 = obuf_sz_in[1] & _T_1320; // @[lsu_bus_buffer.scala 308:132] + wire _T_1322 = _T_1316 | _T_1321; // @[lsu_bus_buffer.scala 308:116] + wire obuf_aligned_in = ibuf_buf_byp ? is_aligned_r : _T_1322; // @[lsu_bus_buffer.scala 308:28] + wire _T_1339 = obuf_addr_in[31:3] == obuf_addr[31:3]; // @[lsu_bus_buffer.scala 322:40] + wire _T_1340 = _T_1339 & obuf_aligned_in; // @[lsu_bus_buffer.scala 322:60] + wire _T_1341 = ~obuf_sideeffect; // @[lsu_bus_buffer.scala 322:80] + wire _T_1342 = _T_1340 & _T_1341; // @[lsu_bus_buffer.scala 322:78] + wire _T_1343 = ~obuf_write; // @[lsu_bus_buffer.scala 322:99] + wire _T_1344 = _T_1342 & _T_1343; // @[lsu_bus_buffer.scala 322:97] + wire _T_1345 = ~obuf_write_in; // @[lsu_bus_buffer.scala 322:113] + wire _T_1346 = _T_1344 & _T_1345; // @[lsu_bus_buffer.scala 322:111] + wire _T_1347 = ~io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu_bus_buffer.scala 322:130] + wire _T_1348 = _T_1346 & _T_1347; // @[lsu_bus_buffer.scala 322:128] + wire _T_1349 = ~obuf_nosend; // @[lsu_bus_buffer.scala 323:20] + wire _T_1350 = obuf_valid & _T_1349; // @[lsu_bus_buffer.scala 323:18] + reg obuf_rdrsp_pend; // @[lsu_bus_buffer.scala 350:56] + wire bus_rsp_read = io_lsu_axi_r_valid & io_lsu_axi_r_ready; // @[lsu_bus_buffer.scala 560:38] + reg [2:0] obuf_rdrsp_tag; // @[lsu_bus_buffer.scala 351:55] + wire _T_1351 = io_lsu_axi_r_bits_id == obuf_rdrsp_tag; // @[lsu_bus_buffer.scala 323:90] + wire _T_1352 = bus_rsp_read & _T_1351; // @[lsu_bus_buffer.scala 323:70] + wire _T_1353 = ~_T_1352; // @[lsu_bus_buffer.scala 323:55] + wire _T_1354 = obuf_rdrsp_pend & _T_1353; // @[lsu_bus_buffer.scala 323:53] + wire _T_1355 = _T_1350 | _T_1354; // @[lsu_bus_buffer.scala 323:34] + wire obuf_nosend_in = _T_1348 & _T_1355; // @[lsu_bus_buffer.scala 322:177] + wire _T_1323 = ~obuf_nosend_in; // @[lsu_bus_buffer.scala 316:44] + wire _T_1324 = obuf_wr_en & _T_1323; // @[lsu_bus_buffer.scala 316:42] + wire _T_1325 = ~_T_1324; // @[lsu_bus_buffer.scala 316:29] + wire _T_1326 = _T_1325 & obuf_rdrsp_pend; // @[lsu_bus_buffer.scala 316:61] + wire _T_1330 = _T_1326 & _T_1353; // @[lsu_bus_buffer.scala 316:79] + wire _T_1332 = bus_cmd_sent & _T_1343; // @[lsu_bus_buffer.scala 317:20] + wire _T_1333 = ~io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 317:37] + wire _T_1334 = _T_1332 & _T_1333; // @[lsu_bus_buffer.scala 317:35] + wire [7:0] _T_1358 = {ldst_byteen_lo_r,4'h0}; // @[Cat.scala 29:58] + wire [7:0] _T_1359 = {4'h0,ldst_byteen_lo_r}; // @[Cat.scala 29:58] + wire [7:0] _T_1360 = io_lsu_addr_r[2] ? _T_1358 : _T_1359; // @[lsu_bus_buffer.scala 324:46] + wire [3:0] _T_1379 = _T_1023 ? buf_byteen_0 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1380 = _T_1024 ? buf_byteen_1 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1381 = _T_1025 ? buf_byteen_2 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1382 = _T_1026 ? buf_byteen_3 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1383 = _T_1379 | _T_1380; // @[Mux.scala 27:72] + wire [3:0] _T_1384 = _T_1383 | _T_1381; // @[Mux.scala 27:72] + wire [3:0] _T_1385 = _T_1384 | _T_1382; // @[Mux.scala 27:72] + wire [7:0] _T_1387 = {_T_1385,4'h0}; // @[Cat.scala 29:58] + wire [7:0] _T_1400 = {4'h0,_T_1385}; // @[Cat.scala 29:58] + wire [7:0] _T_1401 = _T_1289[2] ? _T_1387 : _T_1400; // @[lsu_bus_buffer.scala 325:8] + wire [7:0] obuf_byteen0_in = ibuf_buf_byp ? _T_1360 : _T_1401; // @[lsu_bus_buffer.scala 324:28] + wire [7:0] _T_1403 = {ldst_byteen_hi_r,4'h0}; // @[Cat.scala 29:58] + wire [7:0] _T_1404 = {4'h0,ldst_byteen_hi_r}; // @[Cat.scala 29:58] + wire [7:0] _T_1405 = io_end_addr_r[2] ? _T_1403 : _T_1404; // @[lsu_bus_buffer.scala 326:46] + wire _T_1406 = CmdPtr1 == 2'h0; // @[lsu_bus_buffer.scala 58:123] + wire _T_1407 = CmdPtr1 == 2'h1; // @[lsu_bus_buffer.scala 58:123] + wire _T_1408 = CmdPtr1 == 2'h2; // @[lsu_bus_buffer.scala 58:123] + wire _T_1409 = CmdPtr1 == 2'h3; // @[lsu_bus_buffer.scala 58:123] + wire [31:0] _T_1410 = _T_1406 ? buf_addr_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1411 = _T_1407 ? buf_addr_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1412 = _T_1408 ? buf_addr_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1413 = _T_1409 ? buf_addr_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1414 = _T_1410 | _T_1411; // @[Mux.scala 27:72] + wire [31:0] _T_1415 = _T_1414 | _T_1412; // @[Mux.scala 27:72] + wire [31:0] _T_1416 = _T_1415 | _T_1413; // @[Mux.scala 27:72] + wire [3:0] _T_1424 = _T_1406 ? buf_byteen_0 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1425 = _T_1407 ? buf_byteen_1 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1426 = _T_1408 ? buf_byteen_2 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1427 = _T_1409 ? buf_byteen_3 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1428 = _T_1424 | _T_1425; // @[Mux.scala 27:72] + wire [3:0] _T_1429 = _T_1428 | _T_1426; // @[Mux.scala 27:72] + wire [3:0] _T_1430 = _T_1429 | _T_1427; // @[Mux.scala 27:72] + wire [7:0] _T_1432 = {_T_1430,4'h0}; // @[Cat.scala 29:58] + wire [7:0] _T_1445 = {4'h0,_T_1430}; // @[Cat.scala 29:58] + wire [7:0] _T_1446 = _T_1416[2] ? _T_1432 : _T_1445; // @[lsu_bus_buffer.scala 327:8] + wire [7:0] obuf_byteen1_in = ibuf_buf_byp ? _T_1405 : _T_1446; // @[lsu_bus_buffer.scala 326:28] + wire [63:0] _T_1448 = {store_data_lo_r,32'h0}; // @[Cat.scala 29:58] + wire [63:0] _T_1449 = {32'h0,store_data_lo_r}; // @[Cat.scala 29:58] + wire [63:0] _T_1450 = io_lsu_addr_r[2] ? _T_1448 : _T_1449; // @[lsu_bus_buffer.scala 329:44] + wire [31:0] _T_1469 = _T_1023 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1470 = _T_1024 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1471 = _T_1025 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1472 = _T_1026 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1473 = _T_1469 | _T_1470; // @[Mux.scala 27:72] + wire [31:0] _T_1474 = _T_1473 | _T_1471; // @[Mux.scala 27:72] + wire [31:0] _T_1475 = _T_1474 | _T_1472; // @[Mux.scala 27:72] + wire [63:0] _T_1477 = {_T_1475,32'h0}; // @[Cat.scala 29:58] + wire [63:0] _T_1490 = {32'h0,_T_1475}; // @[Cat.scala 29:58] + wire [63:0] _T_1491 = _T_1289[2] ? _T_1477 : _T_1490; // @[lsu_bus_buffer.scala 330:8] + wire [63:0] obuf_data0_in = ibuf_buf_byp ? _T_1450 : _T_1491; // @[lsu_bus_buffer.scala 329:26] + wire [63:0] _T_1493 = {store_data_hi_r,32'h0}; // @[Cat.scala 29:58] + wire [63:0] _T_1494 = {32'h0,store_data_hi_r}; // @[Cat.scala 29:58] + wire [63:0] _T_1495 = io_lsu_addr_r[2] ? _T_1493 : _T_1494; // @[lsu_bus_buffer.scala 331:44] + wire [31:0] _T_1514 = _T_1406 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1515 = _T_1407 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1516 = _T_1408 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1517 = _T_1409 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1518 = _T_1514 | _T_1515; // @[Mux.scala 27:72] + wire [31:0] _T_1519 = _T_1518 | _T_1516; // @[Mux.scala 27:72] + wire [31:0] _T_1520 = _T_1519 | _T_1517; // @[Mux.scala 27:72] + wire [63:0] _T_1522 = {_T_1520,32'h0}; // @[Cat.scala 29:58] + wire [63:0] _T_1535 = {32'h0,_T_1520}; // @[Cat.scala 29:58] + wire [63:0] _T_1536 = _T_1416[2] ? _T_1522 : _T_1535; // @[lsu_bus_buffer.scala 332:8] + wire [63:0] obuf_data1_in = ibuf_buf_byp ? _T_1495 : _T_1536; // @[lsu_bus_buffer.scala 331:26] + wire _T_1621 = CmdPtr0 != CmdPtr1; // @[lsu_bus_buffer.scala 338:30] + wire _T_1622 = _T_1621 & found_cmdptr0; // @[lsu_bus_buffer.scala 338:43] + wire _T_1623 = _T_1622 & found_cmdptr1; // @[lsu_bus_buffer.scala 338:59] + wire _T_1637 = _T_1623 & _T_1107; // @[lsu_bus_buffer.scala 338:75] + wire [2:0] _T_1642 = _T_1406 ? buf_state_0 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1643 = _T_1407 ? buf_state_1 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1646 = _T_1642 | _T_1643; // @[Mux.scala 27:72] + wire [2:0] _T_1644 = _T_1408 ? buf_state_2 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1647 = _T_1646 | _T_1644; // @[Mux.scala 27:72] + wire [2:0] _T_1645 = _T_1409 ? buf_state_3 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1648 = _T_1647 | _T_1645; // @[Mux.scala 27:72] + wire _T_1650 = _T_1648 == 3'h2; // @[lsu_bus_buffer.scala 338:150] + wire _T_1651 = _T_1637 & _T_1650; // @[lsu_bus_buffer.scala 338:118] + wire _T_1672 = _T_1651 & _T_1128; // @[lsu_bus_buffer.scala 338:161] + wire _T_1690 = _T_1672 & _T_1053; // @[lsu_bus_buffer.scala 339:85] + wire _T_1792 = _T_1204 & _T_1166; // @[lsu_bus_buffer.scala 342:38] + reg buf_dualhi_3; // @[Reg.scala 27:20] + reg buf_dualhi_2; // @[Reg.scala 27:20] + reg buf_dualhi_1; // @[Reg.scala 27:20] + reg buf_dualhi_0; // @[Reg.scala 27:20] + wire [3:0] _T_1795 = {buf_dualhi_3,buf_dualhi_2,buf_dualhi_1,buf_dualhi_0}; // @[Cat.scala 29:58] + wire _T_1804 = _T_1023 & _T_1795[0]; // @[Mux.scala 27:72] + wire _T_1805 = _T_1024 & _T_1795[1]; // @[Mux.scala 27:72] + wire _T_1808 = _T_1804 | _T_1805; // @[Mux.scala 27:72] + wire _T_1806 = _T_1025 & _T_1795[2]; // @[Mux.scala 27:72] + wire _T_1809 = _T_1808 | _T_1806; // @[Mux.scala 27:72] + wire _T_1807 = _T_1026 & _T_1795[3]; // @[Mux.scala 27:72] + wire _T_1810 = _T_1809 | _T_1807; // @[Mux.scala 27:72] + wire _T_1812 = ~_T_1810; // @[lsu_bus_buffer.scala 342:109] + wire _T_1813 = _T_1792 & _T_1812; // @[lsu_bus_buffer.scala 342:107] + wire _T_1833 = _T_1813 & _T_1185; // @[lsu_bus_buffer.scala 342:179] + wire _T_1835 = _T_1690 & _T_1833; // @[lsu_bus_buffer.scala 339:122] + wire _T_1836 = ibuf_buf_byp & ldst_samedw_r; // @[lsu_bus_buffer.scala 343:19] + wire _T_1837 = _T_1836 & io_ldst_dual_r; // @[lsu_bus_buffer.scala 343:35] + wire obuf_merge_en = _T_1835 | _T_1837; // @[lsu_bus_buffer.scala 342:253] + wire _T_1539 = obuf_merge_en & obuf_byteen1_in[0]; // @[lsu_bus_buffer.scala 333:80] + wire _T_1540 = obuf_byteen0_in[0] | _T_1539; // @[lsu_bus_buffer.scala 333:63] + wire _T_1543 = obuf_merge_en & obuf_byteen1_in[1]; // @[lsu_bus_buffer.scala 333:80] + wire _T_1544 = obuf_byteen0_in[1] | _T_1543; // @[lsu_bus_buffer.scala 333:63] + wire _T_1547 = obuf_merge_en & obuf_byteen1_in[2]; // @[lsu_bus_buffer.scala 333:80] + wire _T_1548 = obuf_byteen0_in[2] | _T_1547; // @[lsu_bus_buffer.scala 333:63] + wire _T_1551 = obuf_merge_en & obuf_byteen1_in[3]; // @[lsu_bus_buffer.scala 333:80] + wire _T_1552 = obuf_byteen0_in[3] | _T_1551; // @[lsu_bus_buffer.scala 333:63] + wire _T_1555 = obuf_merge_en & obuf_byteen1_in[4]; // @[lsu_bus_buffer.scala 333:80] + wire _T_1556 = obuf_byteen0_in[4] | _T_1555; // @[lsu_bus_buffer.scala 333:63] + wire _T_1559 = obuf_merge_en & obuf_byteen1_in[5]; // @[lsu_bus_buffer.scala 333:80] + wire _T_1560 = obuf_byteen0_in[5] | _T_1559; // @[lsu_bus_buffer.scala 333:63] + wire _T_1563 = obuf_merge_en & obuf_byteen1_in[6]; // @[lsu_bus_buffer.scala 333:80] + wire _T_1564 = obuf_byteen0_in[6] | _T_1563; // @[lsu_bus_buffer.scala 333:63] + wire _T_1567 = obuf_merge_en & obuf_byteen1_in[7]; // @[lsu_bus_buffer.scala 333:80] + wire _T_1568 = obuf_byteen0_in[7] | _T_1567; // @[lsu_bus_buffer.scala 333:63] + wire [7:0] obuf_byteen_in = {_T_1568,_T_1564,_T_1560,_T_1556,_T_1552,_T_1548,_T_1544,_T_1540}; // @[Cat.scala 29:58] + wire [7:0] _T_1579 = _T_1539 ? obuf_data1_in[7:0] : obuf_data0_in[7:0]; // @[lsu_bus_buffer.scala 334:44] + wire [7:0] _T_1584 = _T_1543 ? obuf_data1_in[15:8] : obuf_data0_in[15:8]; // @[lsu_bus_buffer.scala 334:44] + wire [7:0] _T_1589 = _T_1547 ? obuf_data1_in[23:16] : obuf_data0_in[23:16]; // @[lsu_bus_buffer.scala 334:44] + wire [7:0] _T_1594 = _T_1551 ? obuf_data1_in[31:24] : obuf_data0_in[31:24]; // @[lsu_bus_buffer.scala 334:44] + wire [7:0] _T_1599 = _T_1555 ? obuf_data1_in[39:32] : obuf_data0_in[39:32]; // @[lsu_bus_buffer.scala 334:44] + wire [7:0] _T_1604 = _T_1559 ? obuf_data1_in[47:40] : obuf_data0_in[47:40]; // @[lsu_bus_buffer.scala 334:44] + wire [7:0] _T_1609 = _T_1563 ? obuf_data1_in[55:48] : obuf_data0_in[55:48]; // @[lsu_bus_buffer.scala 334:44] + wire [7:0] _T_1614 = _T_1567 ? obuf_data1_in[63:56] : obuf_data0_in[63:56]; // @[lsu_bus_buffer.scala 334:44] + wire [55:0] _T_1620 = {_T_1614,_T_1609,_T_1604,_T_1599,_T_1594,_T_1589,_T_1584}; // @[Cat.scala 29:58] + wire _T_1839 = obuf_wr_en | obuf_valid; // @[lsu_bus_buffer.scala 346:58] + wire _T_1840 = ~obuf_rst; // @[lsu_bus_buffer.scala 346:93] + reg [1:0] obuf_sz; // @[Reg.scala 27:20] + reg [7:0] obuf_byteen; // @[Reg.scala 27:20] + reg [63:0] obuf_data; // @[lib.scala 374:16] + wire _T_1853 = buf_state_0 == 3'h0; // @[lsu_bus_buffer.scala 364:65] + wire _T_1854 = ibuf_tag == 2'h0; // @[lsu_bus_buffer.scala 365:30] + wire _T_1855 = ibuf_valid & _T_1854; // @[lsu_bus_buffer.scala 365:19] + wire _T_1856 = WrPtr0_r == 2'h0; // @[lsu_bus_buffer.scala 366:18] + wire _T_1857 = WrPtr1_r == 2'h0; // @[lsu_bus_buffer.scala 366:57] + wire _T_1858 = io_ldst_dual_r & _T_1857; // @[lsu_bus_buffer.scala 366:45] + wire _T_1859 = _T_1856 | _T_1858; // @[lsu_bus_buffer.scala 366:27] + wire _T_1860 = io_lsu_busreq_r & _T_1859; // @[lsu_bus_buffer.scala 365:58] + wire _T_1861 = _T_1855 | _T_1860; // @[lsu_bus_buffer.scala 365:39] + wire _T_1862 = ~_T_1861; // @[lsu_bus_buffer.scala 365:5] + wire _T_1863 = _T_1853 & _T_1862; // @[lsu_bus_buffer.scala 364:76] + wire _T_1864 = buf_state_1 == 3'h0; // @[lsu_bus_buffer.scala 364:65] + wire _T_1865 = ibuf_tag == 2'h1; // @[lsu_bus_buffer.scala 365:30] + wire _T_1866 = ibuf_valid & _T_1865; // @[lsu_bus_buffer.scala 365:19] + wire _T_1867 = WrPtr0_r == 2'h1; // @[lsu_bus_buffer.scala 366:18] + wire _T_1868 = WrPtr1_r == 2'h1; // @[lsu_bus_buffer.scala 366:57] + wire _T_1869 = io_ldst_dual_r & _T_1868; // @[lsu_bus_buffer.scala 366:45] + wire _T_1870 = _T_1867 | _T_1869; // @[lsu_bus_buffer.scala 366:27] + wire _T_1871 = io_lsu_busreq_r & _T_1870; // @[lsu_bus_buffer.scala 365:58] + wire _T_1872 = _T_1866 | _T_1871; // @[lsu_bus_buffer.scala 365:39] + wire _T_1873 = ~_T_1872; // @[lsu_bus_buffer.scala 365:5] + wire _T_1874 = _T_1864 & _T_1873; // @[lsu_bus_buffer.scala 364:76] + wire _T_1875 = buf_state_2 == 3'h0; // @[lsu_bus_buffer.scala 364:65] + wire _T_1876 = ibuf_tag == 2'h2; // @[lsu_bus_buffer.scala 365:30] + wire _T_1877 = ibuf_valid & _T_1876; // @[lsu_bus_buffer.scala 365:19] + wire _T_1878 = WrPtr0_r == 2'h2; // @[lsu_bus_buffer.scala 366:18] + wire _T_1879 = WrPtr1_r == 2'h2; // @[lsu_bus_buffer.scala 366:57] + wire _T_1880 = io_ldst_dual_r & _T_1879; // @[lsu_bus_buffer.scala 366:45] + wire _T_1881 = _T_1878 | _T_1880; // @[lsu_bus_buffer.scala 366:27] + wire _T_1882 = io_lsu_busreq_r & _T_1881; // @[lsu_bus_buffer.scala 365:58] + wire _T_1883 = _T_1877 | _T_1882; // @[lsu_bus_buffer.scala 365:39] + wire _T_1884 = ~_T_1883; // @[lsu_bus_buffer.scala 365:5] + wire _T_1885 = _T_1875 & _T_1884; // @[lsu_bus_buffer.scala 364:76] + wire _T_1886 = buf_state_3 == 3'h0; // @[lsu_bus_buffer.scala 364:65] + wire _T_1887 = ibuf_tag == 2'h3; // @[lsu_bus_buffer.scala 365:30] + wire _T_1889 = WrPtr0_r == 2'h3; // @[lsu_bus_buffer.scala 366:18] + wire _T_1890 = WrPtr1_r == 2'h3; // @[lsu_bus_buffer.scala 366:57] + wire [1:0] _T_1898 = _T_1885 ? 2'h2 : 2'h3; // @[Mux.scala 98:16] + wire [1:0] _T_1899 = _T_1874 ? 2'h1 : _T_1898; // @[Mux.scala 98:16] + wire [1:0] WrPtr0_m = _T_1863 ? 2'h0 : _T_1899; // @[Mux.scala 98:16] + wire _T_1904 = WrPtr0_m == 2'h0; // @[lsu_bus_buffer.scala 371:33] + wire _T_1905 = io_lsu_busreq_m & _T_1904; // @[lsu_bus_buffer.scala 371:22] + wire _T_1906 = _T_1855 | _T_1905; // @[lsu_bus_buffer.scala 370:112] + wire _T_1912 = _T_1906 | _T_1860; // @[lsu_bus_buffer.scala 371:42] + wire _T_1913 = ~_T_1912; // @[lsu_bus_buffer.scala 370:78] + wire _T_1914 = _T_1853 & _T_1913; // @[lsu_bus_buffer.scala 370:76] + wire _T_1918 = WrPtr0_m == 2'h1; // @[lsu_bus_buffer.scala 371:33] + wire _T_1919 = io_lsu_busreq_m & _T_1918; // @[lsu_bus_buffer.scala 371:22] + wire _T_1920 = _T_1866 | _T_1919; // @[lsu_bus_buffer.scala 370:112] + wire _T_1926 = _T_1920 | _T_1871; // @[lsu_bus_buffer.scala 371:42] + wire _T_1927 = ~_T_1926; // @[lsu_bus_buffer.scala 370:78] + wire _T_1928 = _T_1864 & _T_1927; // @[lsu_bus_buffer.scala 370:76] + wire _T_1932 = WrPtr0_m == 2'h2; // @[lsu_bus_buffer.scala 371:33] + wire _T_1933 = io_lsu_busreq_m & _T_1932; // @[lsu_bus_buffer.scala 371:22] + wire _T_1934 = _T_1877 | _T_1933; // @[lsu_bus_buffer.scala 370:112] + wire _T_1940 = _T_1934 | _T_1882; // @[lsu_bus_buffer.scala 371:42] + wire _T_1941 = ~_T_1940; // @[lsu_bus_buffer.scala 370:78] + wire _T_1942 = _T_1875 & _T_1941; // @[lsu_bus_buffer.scala 370:76] + reg [3:0] buf_rspageQ_0; // @[lsu_bus_buffer.scala 501:63] + wire _T_2746 = buf_state_3 == 3'h5; // @[lsu_bus_buffer.scala 414:102] + wire _T_2747 = buf_rspageQ_0[3] & _T_2746; // @[lsu_bus_buffer.scala 414:87] + wire _T_2743 = buf_state_2 == 3'h5; // @[lsu_bus_buffer.scala 414:102] + wire _T_2744 = buf_rspageQ_0[2] & _T_2743; // @[lsu_bus_buffer.scala 414:87] + wire _T_2740 = buf_state_1 == 3'h5; // @[lsu_bus_buffer.scala 414:102] + wire _T_2741 = buf_rspageQ_0[1] & _T_2740; // @[lsu_bus_buffer.scala 414:87] + wire _T_2737 = buf_state_0 == 3'h5; // @[lsu_bus_buffer.scala 414:102] + wire _T_2738 = buf_rspageQ_0[0] & _T_2737; // @[lsu_bus_buffer.scala 414:87] + wire [3:0] buf_rsp_pickage_0 = {_T_2747,_T_2744,_T_2741,_T_2738}; // @[Cat.scala 29:58] + wire _T_2033 = |buf_rsp_pickage_0; // @[lsu_bus_buffer.scala 382:65] + wire _T_2034 = ~_T_2033; // @[lsu_bus_buffer.scala 382:44] + wire _T_2036 = _T_2034 & _T_2737; // @[lsu_bus_buffer.scala 382:70] + reg [3:0] buf_rspageQ_1; // @[lsu_bus_buffer.scala 501:63] + wire _T_2762 = buf_rspageQ_1[3] & _T_2746; // @[lsu_bus_buffer.scala 414:87] + wire _T_2759 = buf_rspageQ_1[2] & _T_2743; // @[lsu_bus_buffer.scala 414:87] + wire _T_2756 = buf_rspageQ_1[1] & _T_2740; // @[lsu_bus_buffer.scala 414:87] + wire _T_2753 = buf_rspageQ_1[0] & _T_2737; // @[lsu_bus_buffer.scala 414:87] + wire [3:0] buf_rsp_pickage_1 = {_T_2762,_T_2759,_T_2756,_T_2753}; // @[Cat.scala 29:58] + wire _T_2037 = |buf_rsp_pickage_1; // @[lsu_bus_buffer.scala 382:65] + wire _T_2038 = ~_T_2037; // @[lsu_bus_buffer.scala 382:44] + wire _T_2040 = _T_2038 & _T_2740; // @[lsu_bus_buffer.scala 382:70] + reg [3:0] buf_rspageQ_2; // @[lsu_bus_buffer.scala 501:63] + wire _T_2777 = buf_rspageQ_2[3] & _T_2746; // @[lsu_bus_buffer.scala 414:87] + wire _T_2774 = buf_rspageQ_2[2] & _T_2743; // @[lsu_bus_buffer.scala 414:87] + wire _T_2771 = buf_rspageQ_2[1] & _T_2740; // @[lsu_bus_buffer.scala 414:87] + wire _T_2768 = buf_rspageQ_2[0] & _T_2737; // @[lsu_bus_buffer.scala 414:87] + wire [3:0] buf_rsp_pickage_2 = {_T_2777,_T_2774,_T_2771,_T_2768}; // @[Cat.scala 29:58] + wire _T_2041 = |buf_rsp_pickage_2; // @[lsu_bus_buffer.scala 382:65] + wire _T_2042 = ~_T_2041; // @[lsu_bus_buffer.scala 382:44] + wire _T_2044 = _T_2042 & _T_2743; // @[lsu_bus_buffer.scala 382:70] + reg [3:0] buf_rspageQ_3; // @[lsu_bus_buffer.scala 501:63] + wire _T_2792 = buf_rspageQ_3[3] & _T_2746; // @[lsu_bus_buffer.scala 414:87] + wire _T_2789 = buf_rspageQ_3[2] & _T_2743; // @[lsu_bus_buffer.scala 414:87] + wire _T_2786 = buf_rspageQ_3[1] & _T_2740; // @[lsu_bus_buffer.scala 414:87] + wire _T_2783 = buf_rspageQ_3[0] & _T_2737; // @[lsu_bus_buffer.scala 414:87] + wire [3:0] buf_rsp_pickage_3 = {_T_2792,_T_2789,_T_2786,_T_2783}; // @[Cat.scala 29:58] + wire _T_2045 = |buf_rsp_pickage_3; // @[lsu_bus_buffer.scala 382:65] + wire _T_2046 = ~_T_2045; // @[lsu_bus_buffer.scala 382:44] + wire _T_2048 = _T_2046 & _T_2746; // @[lsu_bus_buffer.scala 382:70] + wire [7:0] _T_2104 = {4'h0,_T_2048,_T_2044,_T_2040,_T_2036}; // @[Cat.scala 29:58] + wire _T_2107 = _T_2104[4] | _T_2104[5]; // @[lsu_bus_buffer.scala 386:42] + wire _T_2109 = _T_2107 | _T_2104[6]; // @[lsu_bus_buffer.scala 386:48] + wire _T_2111 = _T_2109 | _T_2104[7]; // @[lsu_bus_buffer.scala 386:54] + wire _T_2114 = _T_2104[2] | _T_2104[3]; // @[lsu_bus_buffer.scala 386:67] + wire _T_2116 = _T_2114 | _T_2104[6]; // @[lsu_bus_buffer.scala 386:73] + wire _T_2118 = _T_2116 | _T_2104[7]; // @[lsu_bus_buffer.scala 386:79] + wire _T_2121 = _T_2104[1] | _T_2104[3]; // @[lsu_bus_buffer.scala 386:92] + wire _T_2123 = _T_2121 | _T_2104[5]; // @[lsu_bus_buffer.scala 386:98] + wire _T_2125 = _T_2123 | _T_2104[7]; // @[lsu_bus_buffer.scala 386:104] + wire [2:0] _T_2127 = {_T_2111,_T_2118,_T_2125}; // @[Cat.scala 29:58] + wire _T_3532 = ibuf_byp | io_ldst_dual_r; // @[lsu_bus_buffer.scala 444:77] + wire _T_3533 = ~ibuf_merge_en; // @[lsu_bus_buffer.scala 444:97] + wire _T_3534 = _T_3532 & _T_3533; // @[lsu_bus_buffer.scala 444:95] + wire _T_3535 = 2'h0 == WrPtr0_r; // @[lsu_bus_buffer.scala 444:117] + wire _T_3536 = _T_3534 & _T_3535; // @[lsu_bus_buffer.scala 444:112] + wire _T_3537 = ibuf_byp & io_ldst_dual_r; // @[lsu_bus_buffer.scala 444:144] + wire _T_3538 = 2'h0 == WrPtr1_r; // @[lsu_bus_buffer.scala 444:166] + wire _T_3539 = _T_3537 & _T_3538; // @[lsu_bus_buffer.scala 444:161] + wire _T_3540 = _T_3536 | _T_3539; // @[lsu_bus_buffer.scala 444:132] + wire _T_3541 = _T_853 & _T_3540; // @[lsu_bus_buffer.scala 444:63] + wire _T_3542 = 2'h0 == ibuf_tag; // @[lsu_bus_buffer.scala 444:206] + wire _T_3543 = ibuf_drain_vld & _T_3542; // @[lsu_bus_buffer.scala 444:201] + wire _T_3544 = _T_3541 | _T_3543; // @[lsu_bus_buffer.scala 444:183] + wire _T_3554 = io_lsu_bus_clk_en | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 451:46] + wire _T_3589 = 3'h3 == buf_state_0; // @[Conditional.scala 37:30] + wire bus_rsp_write = io_lsu_axi_b_valid & io_lsu_axi_b_ready; // @[lsu_bus_buffer.scala 561:39] + wire _T_3634 = io_lsu_axi_b_bits_id == 3'h0; // @[lsu_bus_buffer.scala 469:73] + wire _T_3635 = bus_rsp_write & _T_3634; // @[lsu_bus_buffer.scala 469:52] + wire _T_3636 = io_lsu_axi_r_bits_id == 3'h0; // @[lsu_bus_buffer.scala 470:46] + reg _T_4307; // @[Reg.scala 27:20] + reg _T_4305; // @[Reg.scala 27:20] + reg _T_4303; // @[Reg.scala 27:20] + reg _T_4301; // @[Reg.scala 27:20] + wire [3:0] buf_ldfwd = {_T_4307,_T_4305,_T_4303,_T_4301}; // @[Cat.scala 29:58] + reg [1:0] buf_ldfwdtag_0; // @[Reg.scala 27:20] + wire [2:0] _GEN_368 = {{1'd0}, buf_ldfwdtag_0}; // @[lsu_bus_buffer.scala 471:47] + wire _T_3638 = io_lsu_axi_r_bits_id == _GEN_368; // @[lsu_bus_buffer.scala 471:47] + wire _T_3639 = buf_ldfwd[0] & _T_3638; // @[lsu_bus_buffer.scala 471:27] + wire _T_3640 = _T_3636 | _T_3639; // @[lsu_bus_buffer.scala 470:77] + wire _T_3641 = buf_dual_0 & buf_dualhi_0; // @[lsu_bus_buffer.scala 472:26] + wire _T_3643 = ~buf_write[0]; // @[lsu_bus_buffer.scala 472:44] + wire _T_3644 = _T_3641 & _T_3643; // @[lsu_bus_buffer.scala 472:42] + wire _T_3645 = _T_3644 & buf_samedw_0; // @[lsu_bus_buffer.scala 472:58] + reg [1:0] buf_dualtag_0; // @[Reg.scala 27:20] + wire [2:0] _GEN_369 = {{1'd0}, buf_dualtag_0}; // @[lsu_bus_buffer.scala 472:94] + wire _T_3646 = io_lsu_axi_r_bits_id == _GEN_369; // @[lsu_bus_buffer.scala 472:94] + wire _T_3647 = _T_3645 & _T_3646; // @[lsu_bus_buffer.scala 472:74] + wire _T_3648 = _T_3640 | _T_3647; // @[lsu_bus_buffer.scala 471:71] + wire _T_3649 = bus_rsp_read & _T_3648; // @[lsu_bus_buffer.scala 470:25] + wire _T_3650 = _T_3635 | _T_3649; // @[lsu_bus_buffer.scala 469:105] + wire _GEN_42 = _T_3589 & _T_3650; // @[Conditional.scala 39:67] + wire _GEN_61 = _T_3555 ? 1'h0 : _GEN_42; // @[Conditional.scala 39:67] + wire _GEN_73 = _T_3551 ? 1'h0 : _GEN_61; // @[Conditional.scala 39:67] + wire buf_resp_state_bus_en_0 = _T_3528 ? 1'h0 : _GEN_73; // @[Conditional.scala 40:58] + wire _T_3676 = 3'h4 == buf_state_0; // @[Conditional.scala 37:30] + wire [3:0] _T_3686 = buf_ldfwd >> buf_dualtag_0; // @[lsu_bus_buffer.scala 484:21] + reg [1:0] buf_ldfwdtag_3; // @[Reg.scala 27:20] + reg [1:0] buf_ldfwdtag_2; // @[Reg.scala 27:20] + reg [1:0] buf_ldfwdtag_1; // @[Reg.scala 27:20] + wire [1:0] _GEN_23 = 2'h1 == buf_dualtag_0 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[lsu_bus_buffer.scala 484:58] + wire [1:0] _GEN_24 = 2'h2 == buf_dualtag_0 ? buf_ldfwdtag_2 : _GEN_23; // @[lsu_bus_buffer.scala 484:58] + wire [1:0] _GEN_25 = 2'h3 == buf_dualtag_0 ? buf_ldfwdtag_3 : _GEN_24; // @[lsu_bus_buffer.scala 484:58] + wire [2:0] _GEN_371 = {{1'd0}, _GEN_25}; // @[lsu_bus_buffer.scala 484:58] + wire _T_3688 = io_lsu_axi_r_bits_id == _GEN_371; // @[lsu_bus_buffer.scala 484:58] + wire _T_3689 = _T_3686[0] & _T_3688; // @[lsu_bus_buffer.scala 484:38] + wire _T_3690 = _T_3646 | _T_3689; // @[lsu_bus_buffer.scala 483:95] + wire _T_3691 = bus_rsp_read & _T_3690; // @[lsu_bus_buffer.scala 483:45] + wire _GEN_36 = _T_3676 & _T_3691; // @[Conditional.scala 39:67] + wire _GEN_43 = _T_3589 ? buf_resp_state_bus_en_0 : _GEN_36; // @[Conditional.scala 39:67] + wire _GEN_53 = _T_3555 ? buf_cmd_state_bus_en_0 : _GEN_43; // @[Conditional.scala 39:67] + wire _GEN_66 = _T_3551 ? 1'h0 : _GEN_53; // @[Conditional.scala 39:67] + wire buf_state_bus_en_0 = _T_3528 ? 1'h0 : _GEN_66; // @[Conditional.scala 40:58] + wire _T_3568 = buf_state_bus_en_0 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 457:49] + wire _T_3569 = _T_3568 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 457:70] + wire _T_3694 = 3'h5 == buf_state_0; // @[Conditional.scala 37:30] + wire [1:0] RspPtr = _T_2127[1:0]; // @[lsu_bus_buffer.scala 394:10] + wire _T_3697 = RspPtr == 2'h0; // @[lsu_bus_buffer.scala 489:37] + wire _T_3698 = buf_dualtag_0 == RspPtr; // @[lsu_bus_buffer.scala 489:98] + wire _T_3699 = buf_dual_0 & _T_3698; // @[lsu_bus_buffer.scala 489:80] + wire _T_3700 = _T_3697 | _T_3699; // @[lsu_bus_buffer.scala 489:65] + wire _T_3701 = _T_3700 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 489:112] + wire _T_3702 = 3'h6 == buf_state_0; // @[Conditional.scala 37:30] + wire _GEN_31 = _T_3694 ? _T_3701 : _T_3702; // @[Conditional.scala 39:67] + wire _GEN_37 = _T_3676 ? _T_3569 : _GEN_31; // @[Conditional.scala 39:67] + wire _GEN_44 = _T_3589 ? _T_3569 : _GEN_37; // @[Conditional.scala 39:67] + wire _GEN_54 = _T_3555 ? _T_3569 : _GEN_44; // @[Conditional.scala 39:67] + wire _GEN_64 = _T_3551 ? _T_3554 : _GEN_54; // @[Conditional.scala 39:67] + wire buf_state_en_0 = _T_3528 ? _T_3544 : _GEN_64; // @[Conditional.scala 40:58] + wire _T_2129 = _T_1853 & buf_state_en_0; // @[lsu_bus_buffer.scala 406:94] + wire _T_2135 = ibuf_drain_vld & io_lsu_busreq_r; // @[lsu_bus_buffer.scala 408:23] + wire _T_2137 = _T_2135 & _T_3532; // @[lsu_bus_buffer.scala 408:41] + wire _T_2139 = _T_2137 & _T_1856; // @[lsu_bus_buffer.scala 408:71] + wire _T_2141 = _T_2139 & _T_1854; // @[lsu_bus_buffer.scala 408:92] + wire _T_2142 = _T_4471 | _T_2141; // @[lsu_bus_buffer.scala 407:86] + wire _T_2143 = ibuf_byp & io_lsu_busreq_r; // @[lsu_bus_buffer.scala 409:17] + wire _T_2144 = _T_2143 & io_ldst_dual_r; // @[lsu_bus_buffer.scala 409:35] + wire _T_2146 = _T_2144 & _T_1857; // @[lsu_bus_buffer.scala 409:52] + wire _T_2148 = _T_2146 & _T_1856; // @[lsu_bus_buffer.scala 409:73] + wire _T_2149 = _T_2142 | _T_2148; // @[lsu_bus_buffer.scala 408:114] + wire _T_2150 = _T_2129 & _T_2149; // @[lsu_bus_buffer.scala 406:113] + wire _T_2152 = _T_2150 | buf_age_0[0]; // @[lsu_bus_buffer.scala 409:97] + wire _T_2166 = _T_2139 & _T_1865; // @[lsu_bus_buffer.scala 408:92] + wire _T_2167 = _T_4476 | _T_2166; // @[lsu_bus_buffer.scala 407:86] + wire _T_2173 = _T_2146 & _T_1867; // @[lsu_bus_buffer.scala 409:73] + wire _T_2174 = _T_2167 | _T_2173; // @[lsu_bus_buffer.scala 408:114] + wire _T_2175 = _T_2129 & _T_2174; // @[lsu_bus_buffer.scala 406:113] + wire _T_2177 = _T_2175 | buf_age_0[1]; // @[lsu_bus_buffer.scala 409:97] + wire _T_2191 = _T_2139 & _T_1876; // @[lsu_bus_buffer.scala 408:92] + wire _T_2192 = _T_4481 | _T_2191; // @[lsu_bus_buffer.scala 407:86] + wire _T_2198 = _T_2146 & _T_1878; // @[lsu_bus_buffer.scala 409:73] + wire _T_2199 = _T_2192 | _T_2198; // @[lsu_bus_buffer.scala 408:114] + wire _T_2200 = _T_2129 & _T_2199; // @[lsu_bus_buffer.scala 406:113] + wire _T_2202 = _T_2200 | buf_age_0[2]; // @[lsu_bus_buffer.scala 409:97] + wire _T_2216 = _T_2139 & _T_1887; // @[lsu_bus_buffer.scala 408:92] + wire _T_2217 = _T_4486 | _T_2216; // @[lsu_bus_buffer.scala 407:86] + wire _T_2223 = _T_2146 & _T_1889; // @[lsu_bus_buffer.scala 409:73] + wire _T_2224 = _T_2217 | _T_2223; // @[lsu_bus_buffer.scala 408:114] + wire _T_2225 = _T_2129 & _T_2224; // @[lsu_bus_buffer.scala 406:113] + wire _T_2227 = _T_2225 | buf_age_0[3]; // @[lsu_bus_buffer.scala 409:97] + wire [2:0] _T_2229 = {_T_2227,_T_2202,_T_2177}; // @[Cat.scala 29:58] + wire _T_3728 = 2'h1 == WrPtr0_r; // @[lsu_bus_buffer.scala 444:117] + wire _T_3729 = _T_3534 & _T_3728; // @[lsu_bus_buffer.scala 444:112] + wire _T_3731 = 2'h1 == WrPtr1_r; // @[lsu_bus_buffer.scala 444:166] + wire _T_3732 = _T_3537 & _T_3731; // @[lsu_bus_buffer.scala 444:161] + wire _T_3733 = _T_3729 | _T_3732; // @[lsu_bus_buffer.scala 444:132] + wire _T_3734 = _T_853 & _T_3733; // @[lsu_bus_buffer.scala 444:63] + wire _T_3735 = 2'h1 == ibuf_tag; // @[lsu_bus_buffer.scala 444:206] + wire _T_3736 = ibuf_drain_vld & _T_3735; // @[lsu_bus_buffer.scala 444:201] + wire _T_3737 = _T_3734 | _T_3736; // @[lsu_bus_buffer.scala 444:183] + wire _T_3782 = 3'h3 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_3827 = io_lsu_axi_b_bits_id == 3'h1; // @[lsu_bus_buffer.scala 469:73] + wire _T_3828 = bus_rsp_write & _T_3827; // @[lsu_bus_buffer.scala 469:52] + wire _T_3829 = io_lsu_axi_r_bits_id == 3'h1; // @[lsu_bus_buffer.scala 470:46] + wire [2:0] _GEN_372 = {{1'd0}, buf_ldfwdtag_1}; // @[lsu_bus_buffer.scala 471:47] + wire _T_3831 = io_lsu_axi_r_bits_id == _GEN_372; // @[lsu_bus_buffer.scala 471:47] + wire _T_3832 = buf_ldfwd[1] & _T_3831; // @[lsu_bus_buffer.scala 471:27] + wire _T_3833 = _T_3829 | _T_3832; // @[lsu_bus_buffer.scala 470:77] + wire _T_3834 = buf_dual_1 & buf_dualhi_1; // @[lsu_bus_buffer.scala 472:26] + wire _T_3836 = ~buf_write[1]; // @[lsu_bus_buffer.scala 472:44] + wire _T_3837 = _T_3834 & _T_3836; // @[lsu_bus_buffer.scala 472:42] + wire _T_3838 = _T_3837 & buf_samedw_1; // @[lsu_bus_buffer.scala 472:58] + reg [1:0] buf_dualtag_1; // @[Reg.scala 27:20] + wire [2:0] _GEN_373 = {{1'd0}, buf_dualtag_1}; // @[lsu_bus_buffer.scala 472:94] + wire _T_3839 = io_lsu_axi_r_bits_id == _GEN_373; // @[lsu_bus_buffer.scala 472:94] + wire _T_3840 = _T_3838 & _T_3839; // @[lsu_bus_buffer.scala 472:74] + wire _T_3841 = _T_3833 | _T_3840; // @[lsu_bus_buffer.scala 471:71] + wire _T_3842 = bus_rsp_read & _T_3841; // @[lsu_bus_buffer.scala 470:25] + wire _T_3843 = _T_3828 | _T_3842; // @[lsu_bus_buffer.scala 469:105] + wire _GEN_118 = _T_3782 & _T_3843; // @[Conditional.scala 39:67] + wire _GEN_137 = _T_3748 ? 1'h0 : _GEN_118; // @[Conditional.scala 39:67] + wire _GEN_149 = _T_3744 ? 1'h0 : _GEN_137; // @[Conditional.scala 39:67] + wire buf_resp_state_bus_en_1 = _T_3721 ? 1'h0 : _GEN_149; // @[Conditional.scala 40:58] + wire _T_3869 = 3'h4 == buf_state_1; // @[Conditional.scala 37:30] + wire [3:0] _T_3879 = buf_ldfwd >> buf_dualtag_1; // @[lsu_bus_buffer.scala 484:21] + wire [1:0] _GEN_99 = 2'h1 == buf_dualtag_1 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[lsu_bus_buffer.scala 484:58] + wire [1:0] _GEN_100 = 2'h2 == buf_dualtag_1 ? buf_ldfwdtag_2 : _GEN_99; // @[lsu_bus_buffer.scala 484:58] + wire [1:0] _GEN_101 = 2'h3 == buf_dualtag_1 ? buf_ldfwdtag_3 : _GEN_100; // @[lsu_bus_buffer.scala 484:58] + wire [2:0] _GEN_375 = {{1'd0}, _GEN_101}; // @[lsu_bus_buffer.scala 484:58] + wire _T_3881 = io_lsu_axi_r_bits_id == _GEN_375; // @[lsu_bus_buffer.scala 484:58] + wire _T_3882 = _T_3879[0] & _T_3881; // @[lsu_bus_buffer.scala 484:38] + wire _T_3883 = _T_3839 | _T_3882; // @[lsu_bus_buffer.scala 483:95] + wire _T_3884 = bus_rsp_read & _T_3883; // @[lsu_bus_buffer.scala 483:45] + wire _GEN_112 = _T_3869 & _T_3884; // @[Conditional.scala 39:67] + wire _GEN_119 = _T_3782 ? buf_resp_state_bus_en_1 : _GEN_112; // @[Conditional.scala 39:67] + wire _GEN_129 = _T_3748 ? buf_cmd_state_bus_en_1 : _GEN_119; // @[Conditional.scala 39:67] + wire _GEN_142 = _T_3744 ? 1'h0 : _GEN_129; // @[Conditional.scala 39:67] + wire buf_state_bus_en_1 = _T_3721 ? 1'h0 : _GEN_142; // @[Conditional.scala 40:58] + wire _T_3761 = buf_state_bus_en_1 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 457:49] + wire _T_3762 = _T_3761 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 457:70] + wire _T_3887 = 3'h5 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_3890 = RspPtr == 2'h1; // @[lsu_bus_buffer.scala 489:37] + wire _T_3891 = buf_dualtag_1 == RspPtr; // @[lsu_bus_buffer.scala 489:98] + wire _T_3892 = buf_dual_1 & _T_3891; // @[lsu_bus_buffer.scala 489:80] + wire _T_3893 = _T_3890 | _T_3892; // @[lsu_bus_buffer.scala 489:65] + wire _T_3894 = _T_3893 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 489:112] + wire _T_3895 = 3'h6 == buf_state_1; // @[Conditional.scala 37:30] + wire _GEN_107 = _T_3887 ? _T_3894 : _T_3895; // @[Conditional.scala 39:67] + wire _GEN_113 = _T_3869 ? _T_3762 : _GEN_107; // @[Conditional.scala 39:67] + wire _GEN_120 = _T_3782 ? _T_3762 : _GEN_113; // @[Conditional.scala 39:67] + wire _GEN_130 = _T_3748 ? _T_3762 : _GEN_120; // @[Conditional.scala 39:67] + wire _GEN_140 = _T_3744 ? _T_3554 : _GEN_130; // @[Conditional.scala 39:67] + wire buf_state_en_1 = _T_3721 ? _T_3737 : _GEN_140; // @[Conditional.scala 40:58] + wire _T_2231 = _T_1864 & buf_state_en_1; // @[lsu_bus_buffer.scala 406:94] + wire _T_2241 = _T_2137 & _T_1867; // @[lsu_bus_buffer.scala 408:71] + wire _T_2243 = _T_2241 & _T_1854; // @[lsu_bus_buffer.scala 408:92] + wire _T_2244 = _T_4471 | _T_2243; // @[lsu_bus_buffer.scala 407:86] + wire _T_2248 = _T_2144 & _T_1868; // @[lsu_bus_buffer.scala 409:52] + wire _T_2250 = _T_2248 & _T_1856; // @[lsu_bus_buffer.scala 409:73] + wire _T_2251 = _T_2244 | _T_2250; // @[lsu_bus_buffer.scala 408:114] + wire _T_2252 = _T_2231 & _T_2251; // @[lsu_bus_buffer.scala 406:113] + wire _T_2254 = _T_2252 | buf_age_1[0]; // @[lsu_bus_buffer.scala 409:97] + wire _T_2268 = _T_2241 & _T_1865; // @[lsu_bus_buffer.scala 408:92] + wire _T_2269 = _T_4476 | _T_2268; // @[lsu_bus_buffer.scala 407:86] + wire _T_2275 = _T_2248 & _T_1867; // @[lsu_bus_buffer.scala 409:73] + wire _T_2276 = _T_2269 | _T_2275; // @[lsu_bus_buffer.scala 408:114] + wire _T_2277 = _T_2231 & _T_2276; // @[lsu_bus_buffer.scala 406:113] + wire _T_2279 = _T_2277 | buf_age_1[1]; // @[lsu_bus_buffer.scala 409:97] + wire _T_2293 = _T_2241 & _T_1876; // @[lsu_bus_buffer.scala 408:92] + wire _T_2294 = _T_4481 | _T_2293; // @[lsu_bus_buffer.scala 407:86] + wire _T_2300 = _T_2248 & _T_1878; // @[lsu_bus_buffer.scala 409:73] + wire _T_2301 = _T_2294 | _T_2300; // @[lsu_bus_buffer.scala 408:114] + wire _T_2302 = _T_2231 & _T_2301; // @[lsu_bus_buffer.scala 406:113] + wire _T_2304 = _T_2302 | buf_age_1[2]; // @[lsu_bus_buffer.scala 409:97] + wire _T_2318 = _T_2241 & _T_1887; // @[lsu_bus_buffer.scala 408:92] + wire _T_2319 = _T_4486 | _T_2318; // @[lsu_bus_buffer.scala 407:86] + wire _T_2325 = _T_2248 & _T_1889; // @[lsu_bus_buffer.scala 409:73] + wire _T_2326 = _T_2319 | _T_2325; // @[lsu_bus_buffer.scala 408:114] + wire _T_2327 = _T_2231 & _T_2326; // @[lsu_bus_buffer.scala 406:113] + wire _T_2329 = _T_2327 | buf_age_1[3]; // @[lsu_bus_buffer.scala 409:97] + wire [2:0] _T_2331 = {_T_2329,_T_2304,_T_2279}; // @[Cat.scala 29:58] + wire _T_3921 = 2'h2 == WrPtr0_r; // @[lsu_bus_buffer.scala 444:117] + wire _T_3922 = _T_3534 & _T_3921; // @[lsu_bus_buffer.scala 444:112] + wire _T_3924 = 2'h2 == WrPtr1_r; // @[lsu_bus_buffer.scala 444:166] + wire _T_3925 = _T_3537 & _T_3924; // @[lsu_bus_buffer.scala 444:161] + wire _T_3926 = _T_3922 | _T_3925; // @[lsu_bus_buffer.scala 444:132] + wire _T_3927 = _T_853 & _T_3926; // @[lsu_bus_buffer.scala 444:63] + wire _T_3928 = 2'h2 == ibuf_tag; // @[lsu_bus_buffer.scala 444:206] + wire _T_3929 = ibuf_drain_vld & _T_3928; // @[lsu_bus_buffer.scala 444:201] + wire _T_3930 = _T_3927 | _T_3929; // @[lsu_bus_buffer.scala 444:183] + wire _T_3975 = 3'h3 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_4020 = io_lsu_axi_b_bits_id == 3'h2; // @[lsu_bus_buffer.scala 469:73] + wire _T_4021 = bus_rsp_write & _T_4020; // @[lsu_bus_buffer.scala 469:52] + wire _T_4022 = io_lsu_axi_r_bits_id == 3'h2; // @[lsu_bus_buffer.scala 470:46] + wire [2:0] _GEN_376 = {{1'd0}, buf_ldfwdtag_2}; // @[lsu_bus_buffer.scala 471:47] + wire _T_4024 = io_lsu_axi_r_bits_id == _GEN_376; // @[lsu_bus_buffer.scala 471:47] + wire _T_4025 = buf_ldfwd[2] & _T_4024; // @[lsu_bus_buffer.scala 471:27] + wire _T_4026 = _T_4022 | _T_4025; // @[lsu_bus_buffer.scala 470:77] + wire _T_4027 = buf_dual_2 & buf_dualhi_2; // @[lsu_bus_buffer.scala 472:26] + wire _T_4029 = ~buf_write[2]; // @[lsu_bus_buffer.scala 472:44] + wire _T_4030 = _T_4027 & _T_4029; // @[lsu_bus_buffer.scala 472:42] + wire _T_4031 = _T_4030 & buf_samedw_2; // @[lsu_bus_buffer.scala 472:58] + reg [1:0] buf_dualtag_2; // @[Reg.scala 27:20] + wire [2:0] _GEN_377 = {{1'd0}, buf_dualtag_2}; // @[lsu_bus_buffer.scala 472:94] + wire _T_4032 = io_lsu_axi_r_bits_id == _GEN_377; // @[lsu_bus_buffer.scala 472:94] + wire _T_4033 = _T_4031 & _T_4032; // @[lsu_bus_buffer.scala 472:74] + wire _T_4034 = _T_4026 | _T_4033; // @[lsu_bus_buffer.scala 471:71] + wire _T_4035 = bus_rsp_read & _T_4034; // @[lsu_bus_buffer.scala 470:25] + wire _T_4036 = _T_4021 | _T_4035; // @[lsu_bus_buffer.scala 469:105] + wire _GEN_194 = _T_3975 & _T_4036; // @[Conditional.scala 39:67] + wire _GEN_213 = _T_3941 ? 1'h0 : _GEN_194; // @[Conditional.scala 39:67] + wire _GEN_225 = _T_3937 ? 1'h0 : _GEN_213; // @[Conditional.scala 39:67] + wire buf_resp_state_bus_en_2 = _T_3914 ? 1'h0 : _GEN_225; // @[Conditional.scala 40:58] + wire _T_4062 = 3'h4 == buf_state_2; // @[Conditional.scala 37:30] + wire [3:0] _T_4072 = buf_ldfwd >> buf_dualtag_2; // @[lsu_bus_buffer.scala 484:21] + wire [1:0] _GEN_175 = 2'h1 == buf_dualtag_2 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[lsu_bus_buffer.scala 484:58] + wire [1:0] _GEN_176 = 2'h2 == buf_dualtag_2 ? buf_ldfwdtag_2 : _GEN_175; // @[lsu_bus_buffer.scala 484:58] + wire [1:0] _GEN_177 = 2'h3 == buf_dualtag_2 ? buf_ldfwdtag_3 : _GEN_176; // @[lsu_bus_buffer.scala 484:58] + wire [2:0] _GEN_379 = {{1'd0}, _GEN_177}; // @[lsu_bus_buffer.scala 484:58] + wire _T_4074 = io_lsu_axi_r_bits_id == _GEN_379; // @[lsu_bus_buffer.scala 484:58] + wire _T_4075 = _T_4072[0] & _T_4074; // @[lsu_bus_buffer.scala 484:38] + wire _T_4076 = _T_4032 | _T_4075; // @[lsu_bus_buffer.scala 483:95] + wire _T_4077 = bus_rsp_read & _T_4076; // @[lsu_bus_buffer.scala 483:45] + wire _GEN_188 = _T_4062 & _T_4077; // @[Conditional.scala 39:67] + wire _GEN_195 = _T_3975 ? buf_resp_state_bus_en_2 : _GEN_188; // @[Conditional.scala 39:67] + wire _GEN_205 = _T_3941 ? buf_cmd_state_bus_en_2 : _GEN_195; // @[Conditional.scala 39:67] + wire _GEN_218 = _T_3937 ? 1'h0 : _GEN_205; // @[Conditional.scala 39:67] + wire buf_state_bus_en_2 = _T_3914 ? 1'h0 : _GEN_218; // @[Conditional.scala 40:58] + wire _T_3954 = buf_state_bus_en_2 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 457:49] + wire _T_3955 = _T_3954 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 457:70] + wire _T_4080 = 3'h5 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_4083 = RspPtr == 2'h2; // @[lsu_bus_buffer.scala 489:37] + wire _T_4084 = buf_dualtag_2 == RspPtr; // @[lsu_bus_buffer.scala 489:98] + wire _T_4085 = buf_dual_2 & _T_4084; // @[lsu_bus_buffer.scala 489:80] + wire _T_4086 = _T_4083 | _T_4085; // @[lsu_bus_buffer.scala 489:65] + wire _T_4087 = _T_4086 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 489:112] + wire _T_4088 = 3'h6 == buf_state_2; // @[Conditional.scala 37:30] + wire _GEN_183 = _T_4080 ? _T_4087 : _T_4088; // @[Conditional.scala 39:67] + wire _GEN_189 = _T_4062 ? _T_3955 : _GEN_183; // @[Conditional.scala 39:67] + wire _GEN_196 = _T_3975 ? _T_3955 : _GEN_189; // @[Conditional.scala 39:67] + wire _GEN_206 = _T_3941 ? _T_3955 : _GEN_196; // @[Conditional.scala 39:67] + wire _GEN_216 = _T_3937 ? _T_3554 : _GEN_206; // @[Conditional.scala 39:67] + wire buf_state_en_2 = _T_3914 ? _T_3930 : _GEN_216; // @[Conditional.scala 40:58] + wire _T_2333 = _T_1875 & buf_state_en_2; // @[lsu_bus_buffer.scala 406:94] + wire _T_2343 = _T_2137 & _T_1878; // @[lsu_bus_buffer.scala 408:71] + wire _T_2345 = _T_2343 & _T_1854; // @[lsu_bus_buffer.scala 408:92] + wire _T_2346 = _T_4471 | _T_2345; // @[lsu_bus_buffer.scala 407:86] + wire _T_2350 = _T_2144 & _T_1879; // @[lsu_bus_buffer.scala 409:52] + wire _T_2352 = _T_2350 & _T_1856; // @[lsu_bus_buffer.scala 409:73] + wire _T_2353 = _T_2346 | _T_2352; // @[lsu_bus_buffer.scala 408:114] + wire _T_2354 = _T_2333 & _T_2353; // @[lsu_bus_buffer.scala 406:113] + wire _T_2356 = _T_2354 | buf_age_2[0]; // @[lsu_bus_buffer.scala 409:97] + wire _T_2370 = _T_2343 & _T_1865; // @[lsu_bus_buffer.scala 408:92] + wire _T_2371 = _T_4476 | _T_2370; // @[lsu_bus_buffer.scala 407:86] + wire _T_2377 = _T_2350 & _T_1867; // @[lsu_bus_buffer.scala 409:73] + wire _T_2378 = _T_2371 | _T_2377; // @[lsu_bus_buffer.scala 408:114] + wire _T_2379 = _T_2333 & _T_2378; // @[lsu_bus_buffer.scala 406:113] + wire _T_2381 = _T_2379 | buf_age_2[1]; // @[lsu_bus_buffer.scala 409:97] + wire _T_2395 = _T_2343 & _T_1876; // @[lsu_bus_buffer.scala 408:92] + wire _T_2396 = _T_4481 | _T_2395; // @[lsu_bus_buffer.scala 407:86] + wire _T_2402 = _T_2350 & _T_1878; // @[lsu_bus_buffer.scala 409:73] + wire _T_2403 = _T_2396 | _T_2402; // @[lsu_bus_buffer.scala 408:114] + wire _T_2404 = _T_2333 & _T_2403; // @[lsu_bus_buffer.scala 406:113] + wire _T_2406 = _T_2404 | buf_age_2[2]; // @[lsu_bus_buffer.scala 409:97] + wire _T_2420 = _T_2343 & _T_1887; // @[lsu_bus_buffer.scala 408:92] + wire _T_2421 = _T_4486 | _T_2420; // @[lsu_bus_buffer.scala 407:86] + wire _T_2427 = _T_2350 & _T_1889; // @[lsu_bus_buffer.scala 409:73] + wire _T_2428 = _T_2421 | _T_2427; // @[lsu_bus_buffer.scala 408:114] + wire _T_2429 = _T_2333 & _T_2428; // @[lsu_bus_buffer.scala 406:113] + wire _T_2431 = _T_2429 | buf_age_2[3]; // @[lsu_bus_buffer.scala 409:97] + wire [2:0] _T_2433 = {_T_2431,_T_2406,_T_2381}; // @[Cat.scala 29:58] + wire _T_4114 = 2'h3 == WrPtr0_r; // @[lsu_bus_buffer.scala 444:117] + wire _T_4115 = _T_3534 & _T_4114; // @[lsu_bus_buffer.scala 444:112] + wire _T_4117 = 2'h3 == WrPtr1_r; // @[lsu_bus_buffer.scala 444:166] + wire _T_4118 = _T_3537 & _T_4117; // @[lsu_bus_buffer.scala 444:161] + wire _T_4119 = _T_4115 | _T_4118; // @[lsu_bus_buffer.scala 444:132] + wire _T_4120 = _T_853 & _T_4119; // @[lsu_bus_buffer.scala 444:63] + wire _T_4121 = 2'h3 == ibuf_tag; // @[lsu_bus_buffer.scala 444:206] + wire _T_4122 = ibuf_drain_vld & _T_4121; // @[lsu_bus_buffer.scala 444:201] + wire _T_4123 = _T_4120 | _T_4122; // @[lsu_bus_buffer.scala 444:183] + wire _T_4168 = 3'h3 == buf_state_3; // @[Conditional.scala 37:30] + wire _T_4213 = io_lsu_axi_b_bits_id == 3'h3; // @[lsu_bus_buffer.scala 469:73] + wire _T_4214 = bus_rsp_write & _T_4213; // @[lsu_bus_buffer.scala 469:52] + wire _T_4215 = io_lsu_axi_r_bits_id == 3'h3; // @[lsu_bus_buffer.scala 470:46] + wire [2:0] _GEN_380 = {{1'd0}, buf_ldfwdtag_3}; // @[lsu_bus_buffer.scala 471:47] + wire _T_4217 = io_lsu_axi_r_bits_id == _GEN_380; // @[lsu_bus_buffer.scala 471:47] + wire _T_4218 = buf_ldfwd[3] & _T_4217; // @[lsu_bus_buffer.scala 471:27] + wire _T_4219 = _T_4215 | _T_4218; // @[lsu_bus_buffer.scala 470:77] + wire _T_4220 = buf_dual_3 & buf_dualhi_3; // @[lsu_bus_buffer.scala 472:26] + wire _T_4222 = ~buf_write[3]; // @[lsu_bus_buffer.scala 472:44] + wire _T_4223 = _T_4220 & _T_4222; // @[lsu_bus_buffer.scala 472:42] + wire _T_4224 = _T_4223 & buf_samedw_3; // @[lsu_bus_buffer.scala 472:58] + reg [1:0] buf_dualtag_3; // @[Reg.scala 27:20] + wire [2:0] _GEN_381 = {{1'd0}, buf_dualtag_3}; // @[lsu_bus_buffer.scala 472:94] + wire _T_4225 = io_lsu_axi_r_bits_id == _GEN_381; // @[lsu_bus_buffer.scala 472:94] + wire _T_4226 = _T_4224 & _T_4225; // @[lsu_bus_buffer.scala 472:74] + wire _T_4227 = _T_4219 | _T_4226; // @[lsu_bus_buffer.scala 471:71] + wire _T_4228 = bus_rsp_read & _T_4227; // @[lsu_bus_buffer.scala 470:25] + wire _T_4229 = _T_4214 | _T_4228; // @[lsu_bus_buffer.scala 469:105] + wire _GEN_270 = _T_4168 & _T_4229; // @[Conditional.scala 39:67] + wire _GEN_289 = _T_4134 ? 1'h0 : _GEN_270; // @[Conditional.scala 39:67] + wire _GEN_301 = _T_4130 ? 1'h0 : _GEN_289; // @[Conditional.scala 39:67] + wire buf_resp_state_bus_en_3 = _T_4107 ? 1'h0 : _GEN_301; // @[Conditional.scala 40:58] + wire _T_4255 = 3'h4 == buf_state_3; // @[Conditional.scala 37:30] + wire [3:0] _T_4265 = buf_ldfwd >> buf_dualtag_3; // @[lsu_bus_buffer.scala 484:21] + wire [1:0] _GEN_251 = 2'h1 == buf_dualtag_3 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[lsu_bus_buffer.scala 484:58] + wire [1:0] _GEN_252 = 2'h2 == buf_dualtag_3 ? buf_ldfwdtag_2 : _GEN_251; // @[lsu_bus_buffer.scala 484:58] + wire [1:0] _GEN_253 = 2'h3 == buf_dualtag_3 ? buf_ldfwdtag_3 : _GEN_252; // @[lsu_bus_buffer.scala 484:58] + wire [2:0] _GEN_383 = {{1'd0}, _GEN_253}; // @[lsu_bus_buffer.scala 484:58] + wire _T_4267 = io_lsu_axi_r_bits_id == _GEN_383; // @[lsu_bus_buffer.scala 484:58] + wire _T_4268 = _T_4265[0] & _T_4267; // @[lsu_bus_buffer.scala 484:38] + wire _T_4269 = _T_4225 | _T_4268; // @[lsu_bus_buffer.scala 483:95] + wire _T_4270 = bus_rsp_read & _T_4269; // @[lsu_bus_buffer.scala 483:45] + wire _GEN_264 = _T_4255 & _T_4270; // @[Conditional.scala 39:67] + wire _GEN_271 = _T_4168 ? buf_resp_state_bus_en_3 : _GEN_264; // @[Conditional.scala 39:67] + wire _GEN_281 = _T_4134 ? buf_cmd_state_bus_en_3 : _GEN_271; // @[Conditional.scala 39:67] + wire _GEN_294 = _T_4130 ? 1'h0 : _GEN_281; // @[Conditional.scala 39:67] + wire buf_state_bus_en_3 = _T_4107 ? 1'h0 : _GEN_294; // @[Conditional.scala 40:58] + wire _T_4147 = buf_state_bus_en_3 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 457:49] + wire _T_4148 = _T_4147 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 457:70] + wire _T_4273 = 3'h5 == buf_state_3; // @[Conditional.scala 37:30] + wire _T_4276 = RspPtr == 2'h3; // @[lsu_bus_buffer.scala 489:37] + wire _T_4277 = buf_dualtag_3 == RspPtr; // @[lsu_bus_buffer.scala 489:98] + wire _T_4278 = buf_dual_3 & _T_4277; // @[lsu_bus_buffer.scala 489:80] + wire _T_4279 = _T_4276 | _T_4278; // @[lsu_bus_buffer.scala 489:65] + wire _T_4280 = _T_4279 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 489:112] + wire _T_4281 = 3'h6 == buf_state_3; // @[Conditional.scala 37:30] + wire _GEN_259 = _T_4273 ? _T_4280 : _T_4281; // @[Conditional.scala 39:67] + wire _GEN_265 = _T_4255 ? _T_4148 : _GEN_259; // @[Conditional.scala 39:67] + wire _GEN_272 = _T_4168 ? _T_4148 : _GEN_265; // @[Conditional.scala 39:67] + wire _GEN_282 = _T_4134 ? _T_4148 : _GEN_272; // @[Conditional.scala 39:67] + wire _GEN_292 = _T_4130 ? _T_3554 : _GEN_282; // @[Conditional.scala 39:67] + wire buf_state_en_3 = _T_4107 ? _T_4123 : _GEN_292; // @[Conditional.scala 40:58] + wire _T_2435 = _T_1886 & buf_state_en_3; // @[lsu_bus_buffer.scala 406:94] + wire _T_2445 = _T_2137 & _T_1889; // @[lsu_bus_buffer.scala 408:71] + wire _T_2447 = _T_2445 & _T_1854; // @[lsu_bus_buffer.scala 408:92] + wire _T_2448 = _T_4471 | _T_2447; // @[lsu_bus_buffer.scala 407:86] + wire _T_2452 = _T_2144 & _T_1890; // @[lsu_bus_buffer.scala 409:52] + wire _T_2454 = _T_2452 & _T_1856; // @[lsu_bus_buffer.scala 409:73] + wire _T_2455 = _T_2448 | _T_2454; // @[lsu_bus_buffer.scala 408:114] + wire _T_2456 = _T_2435 & _T_2455; // @[lsu_bus_buffer.scala 406:113] + wire _T_2458 = _T_2456 | buf_age_3[0]; // @[lsu_bus_buffer.scala 409:97] + wire _T_2472 = _T_2445 & _T_1865; // @[lsu_bus_buffer.scala 408:92] + wire _T_2473 = _T_4476 | _T_2472; // @[lsu_bus_buffer.scala 407:86] + wire _T_2479 = _T_2452 & _T_1867; // @[lsu_bus_buffer.scala 409:73] + wire _T_2480 = _T_2473 | _T_2479; // @[lsu_bus_buffer.scala 408:114] + wire _T_2481 = _T_2435 & _T_2480; // @[lsu_bus_buffer.scala 406:113] + wire _T_2483 = _T_2481 | buf_age_3[1]; // @[lsu_bus_buffer.scala 409:97] + wire _T_2497 = _T_2445 & _T_1876; // @[lsu_bus_buffer.scala 408:92] + wire _T_2498 = _T_4481 | _T_2497; // @[lsu_bus_buffer.scala 407:86] + wire _T_2504 = _T_2452 & _T_1878; // @[lsu_bus_buffer.scala 409:73] + wire _T_2505 = _T_2498 | _T_2504; // @[lsu_bus_buffer.scala 408:114] + wire _T_2506 = _T_2435 & _T_2505; // @[lsu_bus_buffer.scala 406:113] + wire _T_2508 = _T_2506 | buf_age_3[2]; // @[lsu_bus_buffer.scala 409:97] + wire _T_2522 = _T_2445 & _T_1887; // @[lsu_bus_buffer.scala 408:92] + wire _T_2523 = _T_4486 | _T_2522; // @[lsu_bus_buffer.scala 407:86] + wire _T_2529 = _T_2452 & _T_1889; // @[lsu_bus_buffer.scala 409:73] + wire _T_2530 = _T_2523 | _T_2529; // @[lsu_bus_buffer.scala 408:114] + wire _T_2531 = _T_2435 & _T_2530; // @[lsu_bus_buffer.scala 406:113] + wire _T_2533 = _T_2531 | buf_age_3[3]; // @[lsu_bus_buffer.scala 409:97] + wire [2:0] _T_2535 = {_T_2533,_T_2508,_T_2483}; // @[Cat.scala 29:58] + wire _T_2799 = buf_state_0 == 3'h6; // @[lsu_bus_buffer.scala 417:47] + wire _T_2800 = _T_1853 | _T_2799; // @[lsu_bus_buffer.scala 417:32] + wire _T_2801 = ~_T_2800; // @[lsu_bus_buffer.scala 417:6] + wire _T_2809 = _T_2801 | _T_2141; // @[lsu_bus_buffer.scala 417:59] + wire _T_2816 = _T_2809 | _T_2148; // @[lsu_bus_buffer.scala 418:110] + wire _T_2817 = _T_2129 & _T_2816; // @[lsu_bus_buffer.scala 416:112] + wire _T_2821 = buf_state_1 == 3'h6; // @[lsu_bus_buffer.scala 417:47] + wire _T_2822 = _T_1864 | _T_2821; // @[lsu_bus_buffer.scala 417:32] + wire _T_2823 = ~_T_2822; // @[lsu_bus_buffer.scala 417:6] + wire _T_2831 = _T_2823 | _T_2166; // @[lsu_bus_buffer.scala 417:59] + wire _T_2838 = _T_2831 | _T_2173; // @[lsu_bus_buffer.scala 418:110] + wire _T_2839 = _T_2129 & _T_2838; // @[lsu_bus_buffer.scala 416:112] + wire _T_2843 = buf_state_2 == 3'h6; // @[lsu_bus_buffer.scala 417:47] + wire _T_2844 = _T_1875 | _T_2843; // @[lsu_bus_buffer.scala 417:32] + wire _T_2845 = ~_T_2844; // @[lsu_bus_buffer.scala 417:6] + wire _T_2853 = _T_2845 | _T_2191; // @[lsu_bus_buffer.scala 417:59] + wire _T_2860 = _T_2853 | _T_2198; // @[lsu_bus_buffer.scala 418:110] + wire _T_2861 = _T_2129 & _T_2860; // @[lsu_bus_buffer.scala 416:112] + wire _T_2865 = buf_state_3 == 3'h6; // @[lsu_bus_buffer.scala 417:47] + wire _T_2866 = _T_1886 | _T_2865; // @[lsu_bus_buffer.scala 417:32] + wire _T_2867 = ~_T_2866; // @[lsu_bus_buffer.scala 417:6] + wire _T_2875 = _T_2867 | _T_2216; // @[lsu_bus_buffer.scala 417:59] + wire _T_2882 = _T_2875 | _T_2223; // @[lsu_bus_buffer.scala 418:110] + wire _T_2883 = _T_2129 & _T_2882; // @[lsu_bus_buffer.scala 416:112] + wire [3:0] buf_rspage_set_0 = {_T_2883,_T_2861,_T_2839,_T_2817}; // @[Cat.scala 29:58] + wire _T_2900 = _T_2801 | _T_2243; // @[lsu_bus_buffer.scala 417:59] + wire _T_2907 = _T_2900 | _T_2250; // @[lsu_bus_buffer.scala 418:110] + wire _T_2908 = _T_2231 & _T_2907; // @[lsu_bus_buffer.scala 416:112] + wire _T_2922 = _T_2823 | _T_2268; // @[lsu_bus_buffer.scala 417:59] + wire _T_2929 = _T_2922 | _T_2275; // @[lsu_bus_buffer.scala 418:110] + wire _T_2930 = _T_2231 & _T_2929; // @[lsu_bus_buffer.scala 416:112] + wire _T_2944 = _T_2845 | _T_2293; // @[lsu_bus_buffer.scala 417:59] + wire _T_2951 = _T_2944 | _T_2300; // @[lsu_bus_buffer.scala 418:110] + wire _T_2952 = _T_2231 & _T_2951; // @[lsu_bus_buffer.scala 416:112] + wire _T_2966 = _T_2867 | _T_2318; // @[lsu_bus_buffer.scala 417:59] + wire _T_2973 = _T_2966 | _T_2325; // @[lsu_bus_buffer.scala 418:110] + wire _T_2974 = _T_2231 & _T_2973; // @[lsu_bus_buffer.scala 416:112] + wire [3:0] buf_rspage_set_1 = {_T_2974,_T_2952,_T_2930,_T_2908}; // @[Cat.scala 29:58] + wire _T_2991 = _T_2801 | _T_2345; // @[lsu_bus_buffer.scala 417:59] + wire _T_2998 = _T_2991 | _T_2352; // @[lsu_bus_buffer.scala 418:110] + wire _T_2999 = _T_2333 & _T_2998; // @[lsu_bus_buffer.scala 416:112] + wire _T_3013 = _T_2823 | _T_2370; // @[lsu_bus_buffer.scala 417:59] + wire _T_3020 = _T_3013 | _T_2377; // @[lsu_bus_buffer.scala 418:110] + wire _T_3021 = _T_2333 & _T_3020; // @[lsu_bus_buffer.scala 416:112] + wire _T_3035 = _T_2845 | _T_2395; // @[lsu_bus_buffer.scala 417:59] + wire _T_3042 = _T_3035 | _T_2402; // @[lsu_bus_buffer.scala 418:110] + wire _T_3043 = _T_2333 & _T_3042; // @[lsu_bus_buffer.scala 416:112] + wire _T_3057 = _T_2867 | _T_2420; // @[lsu_bus_buffer.scala 417:59] + wire _T_3064 = _T_3057 | _T_2427; // @[lsu_bus_buffer.scala 418:110] + wire _T_3065 = _T_2333 & _T_3064; // @[lsu_bus_buffer.scala 416:112] + wire [3:0] buf_rspage_set_2 = {_T_3065,_T_3043,_T_3021,_T_2999}; // @[Cat.scala 29:58] + wire _T_3082 = _T_2801 | _T_2447; // @[lsu_bus_buffer.scala 417:59] + wire _T_3089 = _T_3082 | _T_2454; // @[lsu_bus_buffer.scala 418:110] + wire _T_3090 = _T_2435 & _T_3089; // @[lsu_bus_buffer.scala 416:112] + wire _T_3104 = _T_2823 | _T_2472; // @[lsu_bus_buffer.scala 417:59] + wire _T_3111 = _T_3104 | _T_2479; // @[lsu_bus_buffer.scala 418:110] + wire _T_3112 = _T_2435 & _T_3111; // @[lsu_bus_buffer.scala 416:112] + wire _T_3126 = _T_2845 | _T_2497; // @[lsu_bus_buffer.scala 417:59] + wire _T_3133 = _T_3126 | _T_2504; // @[lsu_bus_buffer.scala 418:110] + wire _T_3134 = _T_2435 & _T_3133; // @[lsu_bus_buffer.scala 416:112] + wire _T_3148 = _T_2867 | _T_2522; // @[lsu_bus_buffer.scala 417:59] + wire _T_3155 = _T_3148 | _T_2529; // @[lsu_bus_buffer.scala 418:110] + wire _T_3156 = _T_2435 & _T_3155; // @[lsu_bus_buffer.scala 416:112] + wire [3:0] buf_rspage_set_3 = {_T_3156,_T_3134,_T_3112,_T_3090}; // @[Cat.scala 29:58] + wire _T_3241 = _T_2865 | _T_1886; // @[lsu_bus_buffer.scala 421:110] + wire _T_3242 = ~_T_3241; // @[lsu_bus_buffer.scala 421:84] + wire _T_3243 = buf_rspageQ_0[3] & _T_3242; // @[lsu_bus_buffer.scala 421:82] + wire _T_3235 = _T_2843 | _T_1875; // @[lsu_bus_buffer.scala 421:110] + wire _T_3236 = ~_T_3235; // @[lsu_bus_buffer.scala 421:84] + wire _T_3237 = buf_rspageQ_0[2] & _T_3236; // @[lsu_bus_buffer.scala 421:82] + wire _T_3229 = _T_2821 | _T_1864; // @[lsu_bus_buffer.scala 421:110] + wire _T_3230 = ~_T_3229; // @[lsu_bus_buffer.scala 421:84] + wire _T_3231 = buf_rspageQ_0[1] & _T_3230; // @[lsu_bus_buffer.scala 421:82] + wire _T_3223 = _T_2799 | _T_1853; // @[lsu_bus_buffer.scala 421:110] + wire _T_3224 = ~_T_3223; // @[lsu_bus_buffer.scala 421:84] + wire _T_3225 = buf_rspageQ_0[0] & _T_3224; // @[lsu_bus_buffer.scala 421:82] + wire [3:0] buf_rspage_0 = {_T_3243,_T_3237,_T_3231,_T_3225}; // @[Cat.scala 29:58] + wire _T_3162 = buf_rspage_set_0[0] | buf_rspage_0[0]; // @[lsu_bus_buffer.scala 420:88] + wire _T_3165 = buf_rspage_set_0[1] | buf_rspage_0[1]; // @[lsu_bus_buffer.scala 420:88] + wire _T_3168 = buf_rspage_set_0[2] | buf_rspage_0[2]; // @[lsu_bus_buffer.scala 420:88] + wire _T_3171 = buf_rspage_set_0[3] | buf_rspage_0[3]; // @[lsu_bus_buffer.scala 420:88] + wire [2:0] _T_3173 = {_T_3171,_T_3168,_T_3165}; // @[Cat.scala 29:58] + wire _T_3270 = buf_rspageQ_1[3] & _T_3242; // @[lsu_bus_buffer.scala 421:82] + wire _T_3264 = buf_rspageQ_1[2] & _T_3236; // @[lsu_bus_buffer.scala 421:82] + wire _T_3258 = buf_rspageQ_1[1] & _T_3230; // @[lsu_bus_buffer.scala 421:82] + wire _T_3252 = buf_rspageQ_1[0] & _T_3224; // @[lsu_bus_buffer.scala 421:82] + wire [3:0] buf_rspage_1 = {_T_3270,_T_3264,_T_3258,_T_3252}; // @[Cat.scala 29:58] + wire _T_3177 = buf_rspage_set_1[0] | buf_rspage_1[0]; // @[lsu_bus_buffer.scala 420:88] + wire _T_3180 = buf_rspage_set_1[1] | buf_rspage_1[1]; // @[lsu_bus_buffer.scala 420:88] + wire _T_3183 = buf_rspage_set_1[2] | buf_rspage_1[2]; // @[lsu_bus_buffer.scala 420:88] + wire _T_3186 = buf_rspage_set_1[3] | buf_rspage_1[3]; // @[lsu_bus_buffer.scala 420:88] + wire [2:0] _T_3188 = {_T_3186,_T_3183,_T_3180}; // @[Cat.scala 29:58] + wire _T_3297 = buf_rspageQ_2[3] & _T_3242; // @[lsu_bus_buffer.scala 421:82] + wire _T_3291 = buf_rspageQ_2[2] & _T_3236; // @[lsu_bus_buffer.scala 421:82] + wire _T_3285 = buf_rspageQ_2[1] & _T_3230; // @[lsu_bus_buffer.scala 421:82] + wire _T_3279 = buf_rspageQ_2[0] & _T_3224; // @[lsu_bus_buffer.scala 421:82] + wire [3:0] buf_rspage_2 = {_T_3297,_T_3291,_T_3285,_T_3279}; // @[Cat.scala 29:58] + wire _T_3192 = buf_rspage_set_2[0] | buf_rspage_2[0]; // @[lsu_bus_buffer.scala 420:88] + wire _T_3195 = buf_rspage_set_2[1] | buf_rspage_2[1]; // @[lsu_bus_buffer.scala 420:88] + wire _T_3198 = buf_rspage_set_2[2] | buf_rspage_2[2]; // @[lsu_bus_buffer.scala 420:88] + wire _T_3201 = buf_rspage_set_2[3] | buf_rspage_2[3]; // @[lsu_bus_buffer.scala 420:88] + wire [2:0] _T_3203 = {_T_3201,_T_3198,_T_3195}; // @[Cat.scala 29:58] + wire _T_3324 = buf_rspageQ_3[3] & _T_3242; // @[lsu_bus_buffer.scala 421:82] + wire _T_3318 = buf_rspageQ_3[2] & _T_3236; // @[lsu_bus_buffer.scala 421:82] + wire _T_3312 = buf_rspageQ_3[1] & _T_3230; // @[lsu_bus_buffer.scala 421:82] + wire _T_3306 = buf_rspageQ_3[0] & _T_3224; // @[lsu_bus_buffer.scala 421:82] + wire [3:0] buf_rspage_3 = {_T_3324,_T_3318,_T_3312,_T_3306}; // @[Cat.scala 29:58] + wire _T_3207 = buf_rspage_set_3[0] | buf_rspage_3[0]; // @[lsu_bus_buffer.scala 420:88] + wire _T_3210 = buf_rspage_set_3[1] | buf_rspage_3[1]; // @[lsu_bus_buffer.scala 420:88] + wire _T_3213 = buf_rspage_set_3[2] | buf_rspage_3[2]; // @[lsu_bus_buffer.scala 420:88] + wire _T_3216 = buf_rspage_set_3[3] | buf_rspage_3[3]; // @[lsu_bus_buffer.scala 420:88] + wire [2:0] _T_3218 = {_T_3216,_T_3213,_T_3210}; // @[Cat.scala 29:58] + wire _T_3329 = ibuf_drain_vld & _T_1854; // @[lsu_bus_buffer.scala 426:63] + wire _T_3331 = ibuf_drain_vld & _T_1865; // @[lsu_bus_buffer.scala 426:63] + wire _T_3333 = ibuf_drain_vld & _T_1876; // @[lsu_bus_buffer.scala 426:63] + wire _T_3335 = ibuf_drain_vld & _T_1887; // @[lsu_bus_buffer.scala 426:63] + wire [3:0] ibuf_drainvec_vld = {_T_3335,_T_3333,_T_3331,_T_3329}; // @[Cat.scala 29:58] + wire _T_3343 = _T_3537 & _T_1857; // @[lsu_bus_buffer.scala 428:35] + wire _T_3352 = _T_3537 & _T_1868; // @[lsu_bus_buffer.scala 428:35] + wire _T_3361 = _T_3537 & _T_1879; // @[lsu_bus_buffer.scala 428:35] + wire _T_3370 = _T_3537 & _T_1890; // @[lsu_bus_buffer.scala 428:35] + wire _T_3400 = ibuf_drainvec_vld[0] ? ibuf_dual : io_ldst_dual_r; // @[lsu_bus_buffer.scala 430:45] + wire _T_3402 = ibuf_drainvec_vld[1] ? ibuf_dual : io_ldst_dual_r; // @[lsu_bus_buffer.scala 430:45] + wire _T_3404 = ibuf_drainvec_vld[2] ? ibuf_dual : io_ldst_dual_r; // @[lsu_bus_buffer.scala 430:45] + wire _T_3406 = ibuf_drainvec_vld[3] ? ibuf_dual : io_ldst_dual_r; // @[lsu_bus_buffer.scala 430:45] + wire [3:0] buf_dual_in = {_T_3406,_T_3404,_T_3402,_T_3400}; // @[Cat.scala 29:58] + wire _T_3411 = ibuf_drainvec_vld[0] ? ibuf_samedw : ldst_samedw_r; // @[lsu_bus_buffer.scala 431:47] + wire _T_3413 = ibuf_drainvec_vld[1] ? ibuf_samedw : ldst_samedw_r; // @[lsu_bus_buffer.scala 431:47] + wire _T_3415 = ibuf_drainvec_vld[2] ? ibuf_samedw : ldst_samedw_r; // @[lsu_bus_buffer.scala 431:47] + wire _T_3417 = ibuf_drainvec_vld[3] ? ibuf_samedw : ldst_samedw_r; // @[lsu_bus_buffer.scala 431:47] + wire [3:0] buf_samedw_in = {_T_3417,_T_3415,_T_3413,_T_3411}; // @[Cat.scala 29:58] + wire _T_3422 = ibuf_nomerge | ibuf_force_drain; // @[lsu_bus_buffer.scala 432:84] + wire _T_3423 = ibuf_drainvec_vld[0] ? _T_3422 : io_no_dword_merge_r; // @[lsu_bus_buffer.scala 432:48] + wire _T_3426 = ibuf_drainvec_vld[1] ? _T_3422 : io_no_dword_merge_r; // @[lsu_bus_buffer.scala 432:48] + wire _T_3429 = ibuf_drainvec_vld[2] ? _T_3422 : io_no_dword_merge_r; // @[lsu_bus_buffer.scala 432:48] + wire _T_3432 = ibuf_drainvec_vld[3] ? _T_3422 : io_no_dword_merge_r; // @[lsu_bus_buffer.scala 432:48] + wire [3:0] buf_nomerge_in = {_T_3432,_T_3429,_T_3426,_T_3423}; // @[Cat.scala 29:58] + wire _T_3440 = ibuf_drainvec_vld[0] ? ibuf_dual : _T_3343; // @[lsu_bus_buffer.scala 433:47] + wire _T_3445 = ibuf_drainvec_vld[1] ? ibuf_dual : _T_3352; // @[lsu_bus_buffer.scala 433:47] + wire _T_3450 = ibuf_drainvec_vld[2] ? ibuf_dual : _T_3361; // @[lsu_bus_buffer.scala 433:47] + wire _T_3455 = ibuf_drainvec_vld[3] ? ibuf_dual : _T_3370; // @[lsu_bus_buffer.scala 433:47] + wire [3:0] buf_dualhi_in = {_T_3455,_T_3450,_T_3445,_T_3440}; // @[Cat.scala 29:58] + wire _T_3484 = ibuf_drainvec_vld[0] ? ibuf_sideeffect : io_is_sideeffects_r; // @[lsu_bus_buffer.scala 435:51] + wire _T_3486 = ibuf_drainvec_vld[1] ? ibuf_sideeffect : io_is_sideeffects_r; // @[lsu_bus_buffer.scala 435:51] + wire _T_3488 = ibuf_drainvec_vld[2] ? ibuf_sideeffect : io_is_sideeffects_r; // @[lsu_bus_buffer.scala 435:51] + wire _T_3490 = ibuf_drainvec_vld[3] ? ibuf_sideeffect : io_is_sideeffects_r; // @[lsu_bus_buffer.scala 435:51] + wire [3:0] buf_sideeffect_in = {_T_3490,_T_3488,_T_3486,_T_3484}; // @[Cat.scala 29:58] + wire _T_3495 = ibuf_drainvec_vld[0] ? ibuf_unsign : io_lsu_pkt_r_bits_unsign; // @[lsu_bus_buffer.scala 436:47] + wire _T_3497 = ibuf_drainvec_vld[1] ? ibuf_unsign : io_lsu_pkt_r_bits_unsign; // @[lsu_bus_buffer.scala 436:47] + wire _T_3499 = ibuf_drainvec_vld[2] ? ibuf_unsign : io_lsu_pkt_r_bits_unsign; // @[lsu_bus_buffer.scala 436:47] + wire _T_3501 = ibuf_drainvec_vld[3] ? ibuf_unsign : io_lsu_pkt_r_bits_unsign; // @[lsu_bus_buffer.scala 436:47] + wire [3:0] buf_unsign_in = {_T_3501,_T_3499,_T_3497,_T_3495}; // @[Cat.scala 29:58] + wire _T_3518 = ibuf_drainvec_vld[0] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 438:46] + wire _T_3520 = ibuf_drainvec_vld[1] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 438:46] + wire _T_3522 = ibuf_drainvec_vld[2] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 438:46] + wire _T_3524 = ibuf_drainvec_vld[3] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 438:46] + wire [3:0] buf_write_in = {_T_3524,_T_3522,_T_3520,_T_3518}; // @[Cat.scala 29:58] + wire _T_3557 = obuf_nosend & bus_rsp_read; // @[lsu_bus_buffer.scala 454:89] + wire _T_3559 = _T_3557 & _T_1351; // @[lsu_bus_buffer.scala 454:104] + wire _T_3572 = buf_state_en_0 & _T_3643; // @[lsu_bus_buffer.scala 459:44] + wire _T_3573 = _T_3572 & obuf_nosend; // @[lsu_bus_buffer.scala 459:60] + wire _T_3575 = _T_3573 & _T_1333; // @[lsu_bus_buffer.scala 459:74] + wire _T_3578 = _T_3568 & obuf_nosend; // @[lsu_bus_buffer.scala 461:67] + wire _T_3579 = _T_3578 & bus_rsp_read; // @[lsu_bus_buffer.scala 461:81] + wire _T_4872 = io_lsu_axi_r_bits_resp != 2'h0; // @[lsu_bus_buffer.scala 565:64] + wire bus_rsp_read_error = bus_rsp_read & _T_4872; // @[lsu_bus_buffer.scala 565:38] + wire _T_3582 = _T_3578 & bus_rsp_read_error; // @[lsu_bus_buffer.scala 462:82] + wire _T_3657 = bus_rsp_read_error & _T_3636; // @[lsu_bus_buffer.scala 476:91] + wire _T_3659 = bus_rsp_read_error & buf_ldfwd[0]; // @[lsu_bus_buffer.scala 477:31] + wire _T_3661 = _T_3659 & _T_3638; // @[lsu_bus_buffer.scala 477:46] + wire _T_3662 = _T_3657 | _T_3661; // @[lsu_bus_buffer.scala 476:143] + wire _T_4870 = io_lsu_axi_b_bits_resp != 2'h0; // @[lsu_bus_buffer.scala 564:66] + wire bus_rsp_write_error = bus_rsp_write & _T_4870; // @[lsu_bus_buffer.scala 564:40] + wire _T_3665 = bus_rsp_write_error & _T_3634; // @[lsu_bus_buffer.scala 478:53] + wire _T_3666 = _T_3662 | _T_3665; // @[lsu_bus_buffer.scala 477:88] + wire _T_3667 = _T_3568 & _T_3666; // @[lsu_bus_buffer.scala 476:68] + wire _GEN_46 = _T_3589 & _T_3667; // @[Conditional.scala 39:67] + wire _GEN_59 = _T_3555 ? _T_3582 : _GEN_46; // @[Conditional.scala 39:67] + wire _GEN_71 = _T_3551 ? 1'h0 : _GEN_59; // @[Conditional.scala 39:67] + wire buf_error_en_0 = _T_3528 ? 1'h0 : _GEN_71; // @[Conditional.scala 40:58] + wire _T_3592 = ~bus_rsp_write_error; // @[lsu_bus_buffer.scala 466:73] + wire _T_3593 = buf_write[0] & _T_3592; // @[lsu_bus_buffer.scala 466:71] + wire _T_3594 = io_dec_tlu_force_halt | _T_3593; // @[lsu_bus_buffer.scala 466:55] + wire _T_3596 = ~buf_samedw_0; // @[lsu_bus_buffer.scala 467:30] + wire _T_3597 = buf_dual_0 & _T_3596; // @[lsu_bus_buffer.scala 467:28] + wire _T_3600 = _T_3597 & _T_3643; // @[lsu_bus_buffer.scala 467:45] + wire [2:0] _GEN_19 = 2'h1 == buf_dualtag_0 ? buf_state_1 : buf_state_0; // @[lsu_bus_buffer.scala 467:90] + wire [2:0] _GEN_20 = 2'h2 == buf_dualtag_0 ? buf_state_2 : _GEN_19; // @[lsu_bus_buffer.scala 467:90] + wire [2:0] _GEN_21 = 2'h3 == buf_dualtag_0 ? buf_state_3 : _GEN_20; // @[lsu_bus_buffer.scala 467:90] + wire _T_3601 = _GEN_21 != 3'h4; // @[lsu_bus_buffer.scala 467:90] + wire _T_3602 = _T_3600 & _T_3601; // @[lsu_bus_buffer.scala 467:61] + wire _T_4494 = _T_2746 | _T_2743; // @[lsu_bus_buffer.scala 525:93] + wire _T_4495 = _T_4494 | _T_2740; // @[lsu_bus_buffer.scala 525:93] + wire any_done_wait_state = _T_4495 | _T_2737; // @[lsu_bus_buffer.scala 525:93] + wire _T_3604 = buf_ldfwd[0] | any_done_wait_state; // @[lsu_bus_buffer.scala 468:31] + wire _T_3610 = buf_dualtag_0 == 2'h0; // @[lsu_bus_buffer.scala 57:118] + wire _T_3612 = buf_dualtag_0 == 2'h1; // @[lsu_bus_buffer.scala 57:118] + wire _T_3614 = buf_dualtag_0 == 2'h2; // @[lsu_bus_buffer.scala 57:118] + wire _T_3616 = buf_dualtag_0 == 2'h3; // @[lsu_bus_buffer.scala 57:118] + wire _T_3618 = _T_3610 & buf_ldfwd[0]; // @[Mux.scala 27:72] + wire _T_3619 = _T_3612 & buf_ldfwd[1]; // @[Mux.scala 27:72] + wire _T_3620 = _T_3614 & buf_ldfwd[2]; // @[Mux.scala 27:72] + wire _T_3621 = _T_3616 & buf_ldfwd[3]; // @[Mux.scala 27:72] + wire _T_3622 = _T_3618 | _T_3619; // @[Mux.scala 27:72] + wire _T_3623 = _T_3622 | _T_3620; // @[Mux.scala 27:72] + wire _T_3624 = _T_3623 | _T_3621; // @[Mux.scala 27:72] + wire _T_3626 = _T_3600 & _T_3624; // @[lsu_bus_buffer.scala 468:101] + wire _T_3627 = _GEN_21 == 3'h4; // @[lsu_bus_buffer.scala 468:167] + wire _T_3628 = _T_3626 & _T_3627; // @[lsu_bus_buffer.scala 468:138] + wire _T_3629 = _T_3628 & any_done_wait_state; // @[lsu_bus_buffer.scala 468:187] + wire _T_3630 = _T_3604 | _T_3629; // @[lsu_bus_buffer.scala 468:53] + wire _T_3653 = buf_state_bus_en_0 & bus_rsp_read; // @[lsu_bus_buffer.scala 475:47] + wire _T_3654 = _T_3653 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 475:62] + wire _T_3668 = ~buf_error_en_0; // @[lsu_bus_buffer.scala 479:50] + wire _T_3669 = buf_state_en_0 & _T_3668; // @[lsu_bus_buffer.scala 479:48] + wire _T_3681 = buf_ldfwd[0] | _T_3686[0]; // @[lsu_bus_buffer.scala 482:90] + wire _T_3682 = _T_3681 | any_done_wait_state; // @[lsu_bus_buffer.scala 482:118] + wire _GEN_29 = _T_3702 & buf_state_en_0; // @[Conditional.scala 39:67] + wire _GEN_32 = _T_3694 ? 1'h0 : _T_3702; // @[Conditional.scala 39:67] + wire _GEN_34 = _T_3694 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67] + wire _GEN_38 = _T_3676 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67] + wire _GEN_40 = _T_3676 ? 1'h0 : _GEN_34; // @[Conditional.scala 39:67] + wire _GEN_45 = _T_3589 & _T_3654; // @[Conditional.scala 39:67] + wire _GEN_48 = _T_3589 ? 1'h0 : _GEN_38; // @[Conditional.scala 39:67] + wire _GEN_50 = _T_3589 ? 1'h0 : _GEN_40; // @[Conditional.scala 39:67] + wire _GEN_56 = _T_3555 ? _T_3575 : _GEN_50; // @[Conditional.scala 39:67] + wire _GEN_58 = _T_3555 ? _T_3579 : _GEN_45; // @[Conditional.scala 39:67] + wire _GEN_62 = _T_3555 ? 1'h0 : _GEN_48; // @[Conditional.scala 39:67] + wire _GEN_68 = _T_3551 ? 1'h0 : _GEN_56; // @[Conditional.scala 39:67] + wire _GEN_70 = _T_3551 ? 1'h0 : _GEN_58; // @[Conditional.scala 39:67] + wire _GEN_74 = _T_3551 ? 1'h0 : _GEN_62; // @[Conditional.scala 39:67] + wire buf_wr_en_0 = _T_3528 & buf_state_en_0; // @[Conditional.scala 40:58] + wire buf_ldfwd_en_0 = _T_3528 ? 1'h0 : _GEN_68; // @[Conditional.scala 40:58] + wire buf_rst_0 = _T_3528 ? 1'h0 : _GEN_74; // @[Conditional.scala 40:58] + wire _T_3765 = buf_state_en_1 & _T_3836; // @[lsu_bus_buffer.scala 459:44] + wire _T_3766 = _T_3765 & obuf_nosend; // @[lsu_bus_buffer.scala 459:60] + wire _T_3768 = _T_3766 & _T_1333; // @[lsu_bus_buffer.scala 459:74] + wire _T_3771 = _T_3761 & obuf_nosend; // @[lsu_bus_buffer.scala 461:67] + wire _T_3772 = _T_3771 & bus_rsp_read; // @[lsu_bus_buffer.scala 461:81] + wire _T_3775 = _T_3771 & bus_rsp_read_error; // @[lsu_bus_buffer.scala 462:82] + wire _T_3850 = bus_rsp_read_error & _T_3829; // @[lsu_bus_buffer.scala 476:91] + wire _T_3852 = bus_rsp_read_error & buf_ldfwd[1]; // @[lsu_bus_buffer.scala 477:31] + wire _T_3854 = _T_3852 & _T_3831; // @[lsu_bus_buffer.scala 477:46] + wire _T_3855 = _T_3850 | _T_3854; // @[lsu_bus_buffer.scala 476:143] + wire _T_3858 = bus_rsp_write_error & _T_3827; // @[lsu_bus_buffer.scala 478:53] + wire _T_3859 = _T_3855 | _T_3858; // @[lsu_bus_buffer.scala 477:88] + wire _T_3860 = _T_3761 & _T_3859; // @[lsu_bus_buffer.scala 476:68] + wire _GEN_122 = _T_3782 & _T_3860; // @[Conditional.scala 39:67] + wire _GEN_135 = _T_3748 ? _T_3775 : _GEN_122; // @[Conditional.scala 39:67] + wire _GEN_147 = _T_3744 ? 1'h0 : _GEN_135; // @[Conditional.scala 39:67] + wire buf_error_en_1 = _T_3721 ? 1'h0 : _GEN_147; // @[Conditional.scala 40:58] + wire _T_3786 = buf_write[1] & _T_3592; // @[lsu_bus_buffer.scala 466:71] + wire _T_3787 = io_dec_tlu_force_halt | _T_3786; // @[lsu_bus_buffer.scala 466:55] + wire _T_3789 = ~buf_samedw_1; // @[lsu_bus_buffer.scala 467:30] + wire _T_3790 = buf_dual_1 & _T_3789; // @[lsu_bus_buffer.scala 467:28] + wire _T_3793 = _T_3790 & _T_3836; // @[lsu_bus_buffer.scala 467:45] + wire [2:0] _GEN_95 = 2'h1 == buf_dualtag_1 ? buf_state_1 : buf_state_0; // @[lsu_bus_buffer.scala 467:90] + wire [2:0] _GEN_96 = 2'h2 == buf_dualtag_1 ? buf_state_2 : _GEN_95; // @[lsu_bus_buffer.scala 467:90] + wire [2:0] _GEN_97 = 2'h3 == buf_dualtag_1 ? buf_state_3 : _GEN_96; // @[lsu_bus_buffer.scala 467:90] + wire _T_3794 = _GEN_97 != 3'h4; // @[lsu_bus_buffer.scala 467:90] + wire _T_3795 = _T_3793 & _T_3794; // @[lsu_bus_buffer.scala 467:61] + wire _T_3797 = buf_ldfwd[1] | any_done_wait_state; // @[lsu_bus_buffer.scala 468:31] + wire _T_3803 = buf_dualtag_1 == 2'h0; // @[lsu_bus_buffer.scala 57:118] + wire _T_3805 = buf_dualtag_1 == 2'h1; // @[lsu_bus_buffer.scala 57:118] + wire _T_3807 = buf_dualtag_1 == 2'h2; // @[lsu_bus_buffer.scala 57:118] + wire _T_3809 = buf_dualtag_1 == 2'h3; // @[lsu_bus_buffer.scala 57:118] + wire _T_3811 = _T_3803 & buf_ldfwd[0]; // @[Mux.scala 27:72] + wire _T_3812 = _T_3805 & buf_ldfwd[1]; // @[Mux.scala 27:72] + wire _T_3813 = _T_3807 & buf_ldfwd[2]; // @[Mux.scala 27:72] + wire _T_3814 = _T_3809 & buf_ldfwd[3]; // @[Mux.scala 27:72] + wire _T_3815 = _T_3811 | _T_3812; // @[Mux.scala 27:72] + wire _T_3816 = _T_3815 | _T_3813; // @[Mux.scala 27:72] + wire _T_3817 = _T_3816 | _T_3814; // @[Mux.scala 27:72] + wire _T_3819 = _T_3793 & _T_3817; // @[lsu_bus_buffer.scala 468:101] + wire _T_3820 = _GEN_97 == 3'h4; // @[lsu_bus_buffer.scala 468:167] + wire _T_3821 = _T_3819 & _T_3820; // @[lsu_bus_buffer.scala 468:138] + wire _T_3822 = _T_3821 & any_done_wait_state; // @[lsu_bus_buffer.scala 468:187] + wire _T_3823 = _T_3797 | _T_3822; // @[lsu_bus_buffer.scala 468:53] + wire _T_3846 = buf_state_bus_en_1 & bus_rsp_read; // @[lsu_bus_buffer.scala 475:47] + wire _T_3847 = _T_3846 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 475:62] + wire _T_3861 = ~buf_error_en_1; // @[lsu_bus_buffer.scala 479:50] + wire _T_3862 = buf_state_en_1 & _T_3861; // @[lsu_bus_buffer.scala 479:48] + wire _T_3874 = buf_ldfwd[1] | _T_3879[0]; // @[lsu_bus_buffer.scala 482:90] + wire _T_3875 = _T_3874 | any_done_wait_state; // @[lsu_bus_buffer.scala 482:118] + wire _GEN_105 = _T_3895 & buf_state_en_1; // @[Conditional.scala 39:67] + wire _GEN_108 = _T_3887 ? 1'h0 : _T_3895; // @[Conditional.scala 39:67] + wire _GEN_110 = _T_3887 ? 1'h0 : _GEN_105; // @[Conditional.scala 39:67] + wire _GEN_114 = _T_3869 ? 1'h0 : _GEN_108; // @[Conditional.scala 39:67] + wire _GEN_116 = _T_3869 ? 1'h0 : _GEN_110; // @[Conditional.scala 39:67] + wire _GEN_121 = _T_3782 & _T_3847; // @[Conditional.scala 39:67] + wire _GEN_124 = _T_3782 ? 1'h0 : _GEN_114; // @[Conditional.scala 39:67] + wire _GEN_126 = _T_3782 ? 1'h0 : _GEN_116; // @[Conditional.scala 39:67] + wire _GEN_132 = _T_3748 ? _T_3768 : _GEN_126; // @[Conditional.scala 39:67] + wire _GEN_134 = _T_3748 ? _T_3772 : _GEN_121; // @[Conditional.scala 39:67] + wire _GEN_138 = _T_3748 ? 1'h0 : _GEN_124; // @[Conditional.scala 39:67] + wire _GEN_144 = _T_3744 ? 1'h0 : _GEN_132; // @[Conditional.scala 39:67] + wire _GEN_146 = _T_3744 ? 1'h0 : _GEN_134; // @[Conditional.scala 39:67] + wire _GEN_150 = _T_3744 ? 1'h0 : _GEN_138; // @[Conditional.scala 39:67] + wire buf_wr_en_1 = _T_3721 & buf_state_en_1; // @[Conditional.scala 40:58] + wire buf_ldfwd_en_1 = _T_3721 ? 1'h0 : _GEN_144; // @[Conditional.scala 40:58] + wire buf_rst_1 = _T_3721 ? 1'h0 : _GEN_150; // @[Conditional.scala 40:58] + wire _T_3958 = buf_state_en_2 & _T_4029; // @[lsu_bus_buffer.scala 459:44] + wire _T_3959 = _T_3958 & obuf_nosend; // @[lsu_bus_buffer.scala 459:60] + wire _T_3961 = _T_3959 & _T_1333; // @[lsu_bus_buffer.scala 459:74] + wire _T_3964 = _T_3954 & obuf_nosend; // @[lsu_bus_buffer.scala 461:67] + wire _T_3965 = _T_3964 & bus_rsp_read; // @[lsu_bus_buffer.scala 461:81] + wire _T_3968 = _T_3964 & bus_rsp_read_error; // @[lsu_bus_buffer.scala 462:82] + wire _T_4043 = bus_rsp_read_error & _T_4022; // @[lsu_bus_buffer.scala 476:91] + wire _T_4045 = bus_rsp_read_error & buf_ldfwd[2]; // @[lsu_bus_buffer.scala 477:31] + wire _T_4047 = _T_4045 & _T_4024; // @[lsu_bus_buffer.scala 477:46] + wire _T_4048 = _T_4043 | _T_4047; // @[lsu_bus_buffer.scala 476:143] + wire _T_4051 = bus_rsp_write_error & _T_4020; // @[lsu_bus_buffer.scala 478:53] + wire _T_4052 = _T_4048 | _T_4051; // @[lsu_bus_buffer.scala 477:88] + wire _T_4053 = _T_3954 & _T_4052; // @[lsu_bus_buffer.scala 476:68] + wire _GEN_198 = _T_3975 & _T_4053; // @[Conditional.scala 39:67] + wire _GEN_211 = _T_3941 ? _T_3968 : _GEN_198; // @[Conditional.scala 39:67] + wire _GEN_223 = _T_3937 ? 1'h0 : _GEN_211; // @[Conditional.scala 39:67] + wire buf_error_en_2 = _T_3914 ? 1'h0 : _GEN_223; // @[Conditional.scala 40:58] + wire _T_3979 = buf_write[2] & _T_3592; // @[lsu_bus_buffer.scala 466:71] + wire _T_3980 = io_dec_tlu_force_halt | _T_3979; // @[lsu_bus_buffer.scala 466:55] + wire _T_3982 = ~buf_samedw_2; // @[lsu_bus_buffer.scala 467:30] + wire _T_3983 = buf_dual_2 & _T_3982; // @[lsu_bus_buffer.scala 467:28] + wire _T_3986 = _T_3983 & _T_4029; // @[lsu_bus_buffer.scala 467:45] + wire [2:0] _GEN_171 = 2'h1 == buf_dualtag_2 ? buf_state_1 : buf_state_0; // @[lsu_bus_buffer.scala 467:90] + wire [2:0] _GEN_172 = 2'h2 == buf_dualtag_2 ? buf_state_2 : _GEN_171; // @[lsu_bus_buffer.scala 467:90] + wire [2:0] _GEN_173 = 2'h3 == buf_dualtag_2 ? buf_state_3 : _GEN_172; // @[lsu_bus_buffer.scala 467:90] + wire _T_3987 = _GEN_173 != 3'h4; // @[lsu_bus_buffer.scala 467:90] + wire _T_3988 = _T_3986 & _T_3987; // @[lsu_bus_buffer.scala 467:61] + wire _T_3990 = buf_ldfwd[2] | any_done_wait_state; // @[lsu_bus_buffer.scala 468:31] + wire _T_3996 = buf_dualtag_2 == 2'h0; // @[lsu_bus_buffer.scala 57:118] + wire _T_3998 = buf_dualtag_2 == 2'h1; // @[lsu_bus_buffer.scala 57:118] + wire _T_4000 = buf_dualtag_2 == 2'h2; // @[lsu_bus_buffer.scala 57:118] + wire _T_4002 = buf_dualtag_2 == 2'h3; // @[lsu_bus_buffer.scala 57:118] + wire _T_4004 = _T_3996 & buf_ldfwd[0]; // @[Mux.scala 27:72] + wire _T_4005 = _T_3998 & buf_ldfwd[1]; // @[Mux.scala 27:72] + wire _T_4006 = _T_4000 & buf_ldfwd[2]; // @[Mux.scala 27:72] + wire _T_4007 = _T_4002 & buf_ldfwd[3]; // @[Mux.scala 27:72] + wire _T_4008 = _T_4004 | _T_4005; // @[Mux.scala 27:72] + wire _T_4009 = _T_4008 | _T_4006; // @[Mux.scala 27:72] + wire _T_4010 = _T_4009 | _T_4007; // @[Mux.scala 27:72] + wire _T_4012 = _T_3986 & _T_4010; // @[lsu_bus_buffer.scala 468:101] + wire _T_4013 = _GEN_173 == 3'h4; // @[lsu_bus_buffer.scala 468:167] + wire _T_4014 = _T_4012 & _T_4013; // @[lsu_bus_buffer.scala 468:138] + wire _T_4015 = _T_4014 & any_done_wait_state; // @[lsu_bus_buffer.scala 468:187] + wire _T_4016 = _T_3990 | _T_4015; // @[lsu_bus_buffer.scala 468:53] + wire _T_4039 = buf_state_bus_en_2 & bus_rsp_read; // @[lsu_bus_buffer.scala 475:47] + wire _T_4040 = _T_4039 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 475:62] + wire _T_4054 = ~buf_error_en_2; // @[lsu_bus_buffer.scala 479:50] + wire _T_4055 = buf_state_en_2 & _T_4054; // @[lsu_bus_buffer.scala 479:48] + wire _T_4067 = buf_ldfwd[2] | _T_4072[0]; // @[lsu_bus_buffer.scala 482:90] + wire _T_4068 = _T_4067 | any_done_wait_state; // @[lsu_bus_buffer.scala 482:118] + wire _GEN_181 = _T_4088 & buf_state_en_2; // @[Conditional.scala 39:67] + wire _GEN_184 = _T_4080 ? 1'h0 : _T_4088; // @[Conditional.scala 39:67] + wire _GEN_186 = _T_4080 ? 1'h0 : _GEN_181; // @[Conditional.scala 39:67] + wire _GEN_190 = _T_4062 ? 1'h0 : _GEN_184; // @[Conditional.scala 39:67] + wire _GEN_192 = _T_4062 ? 1'h0 : _GEN_186; // @[Conditional.scala 39:67] + wire _GEN_197 = _T_3975 & _T_4040; // @[Conditional.scala 39:67] + wire _GEN_200 = _T_3975 ? 1'h0 : _GEN_190; // @[Conditional.scala 39:67] + wire _GEN_202 = _T_3975 ? 1'h0 : _GEN_192; // @[Conditional.scala 39:67] + wire _GEN_208 = _T_3941 ? _T_3961 : _GEN_202; // @[Conditional.scala 39:67] + wire _GEN_210 = _T_3941 ? _T_3965 : _GEN_197; // @[Conditional.scala 39:67] + wire _GEN_214 = _T_3941 ? 1'h0 : _GEN_200; // @[Conditional.scala 39:67] + wire _GEN_220 = _T_3937 ? 1'h0 : _GEN_208; // @[Conditional.scala 39:67] + wire _GEN_222 = _T_3937 ? 1'h0 : _GEN_210; // @[Conditional.scala 39:67] + wire _GEN_226 = _T_3937 ? 1'h0 : _GEN_214; // @[Conditional.scala 39:67] + wire buf_wr_en_2 = _T_3914 & buf_state_en_2; // @[Conditional.scala 40:58] + wire buf_ldfwd_en_2 = _T_3914 ? 1'h0 : _GEN_220; // @[Conditional.scala 40:58] + wire buf_rst_2 = _T_3914 ? 1'h0 : _GEN_226; // @[Conditional.scala 40:58] + wire _T_4151 = buf_state_en_3 & _T_4222; // @[lsu_bus_buffer.scala 459:44] + wire _T_4152 = _T_4151 & obuf_nosend; // @[lsu_bus_buffer.scala 459:60] + wire _T_4154 = _T_4152 & _T_1333; // @[lsu_bus_buffer.scala 459:74] + wire _T_4157 = _T_4147 & obuf_nosend; // @[lsu_bus_buffer.scala 461:67] + wire _T_4158 = _T_4157 & bus_rsp_read; // @[lsu_bus_buffer.scala 461:81] + wire _T_4161 = _T_4157 & bus_rsp_read_error; // @[lsu_bus_buffer.scala 462:82] + wire _T_4236 = bus_rsp_read_error & _T_4215; // @[lsu_bus_buffer.scala 476:91] + wire _T_4238 = bus_rsp_read_error & buf_ldfwd[3]; // @[lsu_bus_buffer.scala 477:31] + wire _T_4240 = _T_4238 & _T_4217; // @[lsu_bus_buffer.scala 477:46] + wire _T_4241 = _T_4236 | _T_4240; // @[lsu_bus_buffer.scala 476:143] + wire _T_4244 = bus_rsp_write_error & _T_4213; // @[lsu_bus_buffer.scala 478:53] + wire _T_4245 = _T_4241 | _T_4244; // @[lsu_bus_buffer.scala 477:88] + wire _T_4246 = _T_4147 & _T_4245; // @[lsu_bus_buffer.scala 476:68] + wire _GEN_274 = _T_4168 & _T_4246; // @[Conditional.scala 39:67] + wire _GEN_287 = _T_4134 ? _T_4161 : _GEN_274; // @[Conditional.scala 39:67] + wire _GEN_299 = _T_4130 ? 1'h0 : _GEN_287; // @[Conditional.scala 39:67] + wire buf_error_en_3 = _T_4107 ? 1'h0 : _GEN_299; // @[Conditional.scala 40:58] + wire _T_4172 = buf_write[3] & _T_3592; // @[lsu_bus_buffer.scala 466:71] + wire _T_4173 = io_dec_tlu_force_halt | _T_4172; // @[lsu_bus_buffer.scala 466:55] + wire _T_4175 = ~buf_samedw_3; // @[lsu_bus_buffer.scala 467:30] + wire _T_4176 = buf_dual_3 & _T_4175; // @[lsu_bus_buffer.scala 467:28] + wire _T_4179 = _T_4176 & _T_4222; // @[lsu_bus_buffer.scala 467:45] + wire [2:0] _GEN_247 = 2'h1 == buf_dualtag_3 ? buf_state_1 : buf_state_0; // @[lsu_bus_buffer.scala 467:90] + wire [2:0] _GEN_248 = 2'h2 == buf_dualtag_3 ? buf_state_2 : _GEN_247; // @[lsu_bus_buffer.scala 467:90] + wire [2:0] _GEN_249 = 2'h3 == buf_dualtag_3 ? buf_state_3 : _GEN_248; // @[lsu_bus_buffer.scala 467:90] + wire _T_4180 = _GEN_249 != 3'h4; // @[lsu_bus_buffer.scala 467:90] + wire _T_4181 = _T_4179 & _T_4180; // @[lsu_bus_buffer.scala 467:61] + wire _T_4183 = buf_ldfwd[3] | any_done_wait_state; // @[lsu_bus_buffer.scala 468:31] + wire _T_4189 = buf_dualtag_3 == 2'h0; // @[lsu_bus_buffer.scala 57:118] + wire _T_4191 = buf_dualtag_3 == 2'h1; // @[lsu_bus_buffer.scala 57:118] + wire _T_4193 = buf_dualtag_3 == 2'h2; // @[lsu_bus_buffer.scala 57:118] + wire _T_4195 = buf_dualtag_3 == 2'h3; // @[lsu_bus_buffer.scala 57:118] + wire _T_4197 = _T_4189 & buf_ldfwd[0]; // @[Mux.scala 27:72] + wire _T_4198 = _T_4191 & buf_ldfwd[1]; // @[Mux.scala 27:72] + wire _T_4199 = _T_4193 & buf_ldfwd[2]; // @[Mux.scala 27:72] + wire _T_4200 = _T_4195 & buf_ldfwd[3]; // @[Mux.scala 27:72] + wire _T_4201 = _T_4197 | _T_4198; // @[Mux.scala 27:72] + wire _T_4202 = _T_4201 | _T_4199; // @[Mux.scala 27:72] + wire _T_4203 = _T_4202 | _T_4200; // @[Mux.scala 27:72] + wire _T_4205 = _T_4179 & _T_4203; // @[lsu_bus_buffer.scala 468:101] + wire _T_4206 = _GEN_249 == 3'h4; // @[lsu_bus_buffer.scala 468:167] + wire _T_4207 = _T_4205 & _T_4206; // @[lsu_bus_buffer.scala 468:138] + wire _T_4208 = _T_4207 & any_done_wait_state; // @[lsu_bus_buffer.scala 468:187] + wire _T_4209 = _T_4183 | _T_4208; // @[lsu_bus_buffer.scala 468:53] + wire _T_4232 = buf_state_bus_en_3 & bus_rsp_read; // @[lsu_bus_buffer.scala 475:47] + wire _T_4233 = _T_4232 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 475:62] + wire _T_4247 = ~buf_error_en_3; // @[lsu_bus_buffer.scala 479:50] + wire _T_4248 = buf_state_en_3 & _T_4247; // @[lsu_bus_buffer.scala 479:48] + wire _T_4260 = buf_ldfwd[3] | _T_4265[0]; // @[lsu_bus_buffer.scala 482:90] + wire _T_4261 = _T_4260 | any_done_wait_state; // @[lsu_bus_buffer.scala 482:118] + wire _GEN_257 = _T_4281 & buf_state_en_3; // @[Conditional.scala 39:67] + wire _GEN_260 = _T_4273 ? 1'h0 : _T_4281; // @[Conditional.scala 39:67] + wire _GEN_262 = _T_4273 ? 1'h0 : _GEN_257; // @[Conditional.scala 39:67] + wire _GEN_266 = _T_4255 ? 1'h0 : _GEN_260; // @[Conditional.scala 39:67] + wire _GEN_268 = _T_4255 ? 1'h0 : _GEN_262; // @[Conditional.scala 39:67] + wire _GEN_273 = _T_4168 & _T_4233; // @[Conditional.scala 39:67] + wire _GEN_276 = _T_4168 ? 1'h0 : _GEN_266; // @[Conditional.scala 39:67] + wire _GEN_278 = _T_4168 ? 1'h0 : _GEN_268; // @[Conditional.scala 39:67] + wire _GEN_284 = _T_4134 ? _T_4154 : _GEN_278; // @[Conditional.scala 39:67] + wire _GEN_286 = _T_4134 ? _T_4158 : _GEN_273; // @[Conditional.scala 39:67] + wire _GEN_290 = _T_4134 ? 1'h0 : _GEN_276; // @[Conditional.scala 39:67] + wire _GEN_296 = _T_4130 ? 1'h0 : _GEN_284; // @[Conditional.scala 39:67] + wire _GEN_298 = _T_4130 ? 1'h0 : _GEN_286; // @[Conditional.scala 39:67] + wire _GEN_302 = _T_4130 ? 1'h0 : _GEN_290; // @[Conditional.scala 39:67] + wire buf_wr_en_3 = _T_4107 & buf_state_en_3; // @[Conditional.scala 40:58] + wire buf_ldfwd_en_3 = _T_4107 ? 1'h0 : _GEN_296; // @[Conditional.scala 40:58] + wire buf_rst_3 = _T_4107 ? 1'h0 : _GEN_302; // @[Conditional.scala 40:58] + reg _T_4336; // @[Reg.scala 27:20] + reg _T_4339; // @[Reg.scala 27:20] + reg _T_4342; // @[Reg.scala 27:20] + reg _T_4345; // @[Reg.scala 27:20] + wire [3:0] buf_unsign = {_T_4345,_T_4342,_T_4339,_T_4336}; // @[Cat.scala 29:58] + reg _T_4411; // @[lsu_bus_buffer.scala 518:80] + reg _T_4406; // @[lsu_bus_buffer.scala 518:80] + reg _T_4401; // @[lsu_bus_buffer.scala 518:80] + reg _T_4396; // @[lsu_bus_buffer.scala 518:80] + wire [3:0] buf_error = {_T_4411,_T_4406,_T_4401,_T_4396}; // @[Cat.scala 29:58] + wire _T_4393 = buf_error_en_0 | buf_error[0]; // @[lsu_bus_buffer.scala 518:84] + wire _T_4394 = ~buf_rst_0; // @[lsu_bus_buffer.scala 518:126] + wire _T_4398 = buf_error_en_1 | buf_error[1]; // @[lsu_bus_buffer.scala 518:84] + wire _T_4399 = ~buf_rst_1; // @[lsu_bus_buffer.scala 518:126] + wire _T_4403 = buf_error_en_2 | buf_error[2]; // @[lsu_bus_buffer.scala 518:84] + wire _T_4404 = ~buf_rst_2; // @[lsu_bus_buffer.scala 518:126] + wire _T_4408 = buf_error_en_3 | buf_error[3]; // @[lsu_bus_buffer.scala 518:84] + wire _T_4409 = ~buf_rst_3; // @[lsu_bus_buffer.scala 518:126] + wire [1:0] _T_4415 = {io_lsu_busreq_m,1'h0}; // @[Cat.scala 29:58] + wire [1:0] _T_4416 = io_ldst_dual_m ? _T_4415 : {{1'd0}, io_lsu_busreq_m}; // @[lsu_bus_buffer.scala 521:28] + wire [1:0] _T_4417 = {io_lsu_busreq_r,1'h0}; // @[Cat.scala 29:58] + wire [1:0] _T_4418 = io_ldst_dual_r ? _T_4417 : {{1'd0}, io_lsu_busreq_r}; // @[lsu_bus_buffer.scala 521:94] + wire [2:0] _T_4419 = _T_4416 + _T_4418; // @[lsu_bus_buffer.scala 521:88] + wire [2:0] _GEN_388 = {{2'd0}, ibuf_valid}; // @[lsu_bus_buffer.scala 521:154] + wire [3:0] _T_4420 = _T_4419 + _GEN_388; // @[lsu_bus_buffer.scala 521:154] + wire [1:0] _T_4425 = _T_5 + _T_12; // @[lsu_bus_buffer.scala 521:217] + wire [1:0] _GEN_389 = {{1'd0}, _T_19}; // @[lsu_bus_buffer.scala 521:217] + wire [2:0] _T_4426 = _T_4425 + _GEN_389; // @[lsu_bus_buffer.scala 521:217] + wire [2:0] _GEN_390 = {{2'd0}, _T_26}; // @[lsu_bus_buffer.scala 521:217] + wire [3:0] _T_4427 = _T_4426 + _GEN_390; // @[lsu_bus_buffer.scala 521:217] + wire [3:0] buf_numvld_any = _T_4420 + _T_4427; // @[lsu_bus_buffer.scala 521:169] + wire _T_4498 = io_ldst_dual_d & io_dec_lsu_valid_raw_d; // @[lsu_bus_buffer.scala 527:52] + wire _T_4499 = buf_numvld_any >= 4'h3; // @[lsu_bus_buffer.scala 527:92] + wire _T_4500 = buf_numvld_any == 4'h4; // @[lsu_bus_buffer.scala 527:121] + wire _T_4502 = |buf_state_0; // @[lsu_bus_buffer.scala 528:52] + wire _T_4503 = |buf_state_1; // @[lsu_bus_buffer.scala 528:52] + wire _T_4504 = |buf_state_2; // @[lsu_bus_buffer.scala 528:52] + wire _T_4505 = |buf_state_3; // @[lsu_bus_buffer.scala 528:52] + wire _T_4506 = _T_4502 | _T_4503; // @[lsu_bus_buffer.scala 528:65] + wire _T_4507 = _T_4506 | _T_4504; // @[lsu_bus_buffer.scala 528:65] + wire _T_4508 = _T_4507 | _T_4505; // @[lsu_bus_buffer.scala 528:65] + wire _T_4509 = ~_T_4508; // @[lsu_bus_buffer.scala 528:34] + wire _T_4511 = _T_4509 & _T_852; // @[lsu_bus_buffer.scala 528:70] + wire _T_4514 = io_lsu_busreq_m & io_lsu_pkt_m_valid; // @[lsu_bus_buffer.scala 530:64] + wire _T_4515 = _T_4514 & io_lsu_pkt_m_bits_load; // @[lsu_bus_buffer.scala 530:85] + wire _T_4516 = ~io_flush_m_up; // @[lsu_bus_buffer.scala 530:112] + wire _T_4517 = _T_4515 & _T_4516; // @[lsu_bus_buffer.scala 530:110] + wire _T_4518 = ~io_ld_full_hit_m; // @[lsu_bus_buffer.scala 530:129] + wire _T_4520 = ~io_lsu_commit_r; // @[lsu_bus_buffer.scala 533:74] + reg lsu_nonblock_load_valid_r; // @[lsu_bus_buffer.scala 618:66] + wire _T_4538 = _T_2799 & _T_3643; // @[Mux.scala 27:72] + wire _T_4539 = _T_2821 & _T_3836; // @[Mux.scala 27:72] + wire _T_4540 = _T_2843 & _T_4029; // @[Mux.scala 27:72] + wire _T_4541 = _T_2865 & _T_4222; // @[Mux.scala 27:72] + wire _T_4542 = _T_4538 | _T_4539; // @[Mux.scala 27:72] + wire _T_4543 = _T_4542 | _T_4540; // @[Mux.scala 27:72] + wire lsu_nonblock_load_data_ready = _T_4543 | _T_4541; // @[Mux.scala 27:72] + wire _T_4549 = buf_error[0] & _T_3643; // @[lsu_bus_buffer.scala 536:121] + wire _T_4554 = buf_error[1] & _T_3836; // @[lsu_bus_buffer.scala 536:121] + wire _T_4559 = buf_error[2] & _T_4029; // @[lsu_bus_buffer.scala 536:121] + wire _T_4564 = buf_error[3] & _T_4222; // @[lsu_bus_buffer.scala 536:121] + wire _T_4565 = _T_2799 & _T_4549; // @[Mux.scala 27:72] + wire _T_4566 = _T_2821 & _T_4554; // @[Mux.scala 27:72] + wire _T_4567 = _T_2843 & _T_4559; // @[Mux.scala 27:72] + wire _T_4568 = _T_2865 & _T_4564; // @[Mux.scala 27:72] + wire _T_4569 = _T_4565 | _T_4566; // @[Mux.scala 27:72] + wire _T_4570 = _T_4569 | _T_4567; // @[Mux.scala 27:72] + wire _T_4577 = ~buf_dual_0; // @[lsu_bus_buffer.scala 537:122] + wire _T_4578 = ~buf_dualhi_0; // @[lsu_bus_buffer.scala 537:137] + wire _T_4579 = _T_4577 | _T_4578; // @[lsu_bus_buffer.scala 537:135] + wire _T_4580 = _T_4538 & _T_4579; // @[lsu_bus_buffer.scala 537:119] + wire _T_4585 = ~buf_dual_1; // @[lsu_bus_buffer.scala 537:122] + wire _T_4586 = ~buf_dualhi_1; // @[lsu_bus_buffer.scala 537:137] + wire _T_4587 = _T_4585 | _T_4586; // @[lsu_bus_buffer.scala 537:135] + wire _T_4588 = _T_4539 & _T_4587; // @[lsu_bus_buffer.scala 537:119] + wire _T_4593 = ~buf_dual_2; // @[lsu_bus_buffer.scala 537:122] + wire _T_4594 = ~buf_dualhi_2; // @[lsu_bus_buffer.scala 537:137] + wire _T_4595 = _T_4593 | _T_4594; // @[lsu_bus_buffer.scala 537:135] + wire _T_4596 = _T_4540 & _T_4595; // @[lsu_bus_buffer.scala 537:119] + wire _T_4601 = ~buf_dual_3; // @[lsu_bus_buffer.scala 537:122] + wire _T_4602 = ~buf_dualhi_3; // @[lsu_bus_buffer.scala 537:137] + wire _T_4603 = _T_4601 | _T_4602; // @[lsu_bus_buffer.scala 537:135] + wire _T_4604 = _T_4541 & _T_4603; // @[lsu_bus_buffer.scala 537:119] + wire [1:0] _T_4607 = _T_4596 ? 2'h2 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4608 = _T_4604 ? 2'h3 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _GEN_391 = {{1'd0}, _T_4588}; // @[Mux.scala 27:72] + wire [1:0] _T_4610 = _GEN_391 | _T_4607; // @[Mux.scala 27:72] + wire [31:0] _T_4645 = _T_4580 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4646 = _T_4588 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4647 = _T_4596 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4648 = _T_4604 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4649 = _T_4645 | _T_4646; // @[Mux.scala 27:72] + wire [31:0] _T_4650 = _T_4649 | _T_4647; // @[Mux.scala 27:72] + wire [31:0] lsu_nonblock_load_data_lo = _T_4650 | _T_4648; // @[Mux.scala 27:72] + wire _T_4657 = _T_4538 & _T_3641; // @[lsu_bus_buffer.scala 539:105] + wire _T_4663 = _T_4539 & _T_3834; // @[lsu_bus_buffer.scala 539:105] + wire _T_4669 = _T_4540 & _T_4027; // @[lsu_bus_buffer.scala 539:105] + wire _T_4675 = _T_4541 & _T_4220; // @[lsu_bus_buffer.scala 539:105] + wire [31:0] _T_4676 = _T_4657 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4677 = _T_4663 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4678 = _T_4669 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4679 = _T_4675 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4680 = _T_4676 | _T_4677; // @[Mux.scala 27:72] + wire [31:0] _T_4681 = _T_4680 | _T_4678; // @[Mux.scala 27:72] + wire [31:0] lsu_nonblock_load_data_hi = _T_4681 | _T_4679; // @[Mux.scala 27:72] + wire _T_4683 = io_dctl_busbuff_lsu_nonblock_load_data_tag == 2'h0; // @[lsu_bus_buffer.scala 58:123] + wire _T_4684 = io_dctl_busbuff_lsu_nonblock_load_data_tag == 2'h1; // @[lsu_bus_buffer.scala 58:123] + wire _T_4685 = io_dctl_busbuff_lsu_nonblock_load_data_tag == 2'h2; // @[lsu_bus_buffer.scala 58:123] + wire _T_4686 = io_dctl_busbuff_lsu_nonblock_load_data_tag == 2'h3; // @[lsu_bus_buffer.scala 58:123] + wire [31:0] _T_4687 = _T_4683 ? buf_addr_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4688 = _T_4684 ? buf_addr_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4689 = _T_4685 ? buf_addr_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4690 = _T_4686 ? buf_addr_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4691 = _T_4687 | _T_4688; // @[Mux.scala 27:72] + wire [31:0] _T_4692 = _T_4691 | _T_4689; // @[Mux.scala 27:72] + wire [31:0] _T_4693 = _T_4692 | _T_4690; // @[Mux.scala 27:72] + wire [1:0] lsu_nonblock_addr_offset = _T_4693[1:0]; // @[lsu_bus_buffer.scala 540:96] + wire [1:0] _T_4699 = _T_4683 ? buf_sz_0 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4700 = _T_4684 ? buf_sz_1 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4701 = _T_4685 ? buf_sz_2 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4702 = _T_4686 ? buf_sz_3 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4703 = _T_4699 | _T_4700; // @[Mux.scala 27:72] + wire [1:0] _T_4704 = _T_4703 | _T_4701; // @[Mux.scala 27:72] + wire [1:0] lsu_nonblock_sz = _T_4704 | _T_4702; // @[Mux.scala 27:72] + wire _T_4714 = _T_4683 & buf_unsign[0]; // @[Mux.scala 27:72] + wire _T_4715 = _T_4684 & buf_unsign[1]; // @[Mux.scala 27:72] + wire _T_4716 = _T_4685 & buf_unsign[2]; // @[Mux.scala 27:72] + wire _T_4717 = _T_4686 & buf_unsign[3]; // @[Mux.scala 27:72] + wire _T_4718 = _T_4714 | _T_4715; // @[Mux.scala 27:72] + wire _T_4719 = _T_4718 | _T_4716; // @[Mux.scala 27:72] + wire lsu_nonblock_unsign = _T_4719 | _T_4717; // @[Mux.scala 27:72] + wire [63:0] _T_4739 = {lsu_nonblock_load_data_hi,lsu_nonblock_load_data_lo}; // @[Cat.scala 29:58] + wire [3:0] _GEN_392 = {{2'd0}, lsu_nonblock_addr_offset}; // @[lsu_bus_buffer.scala 544:121] + wire [5:0] _T_4740 = _GEN_392 * 4'h8; // @[lsu_bus_buffer.scala 544:121] + wire [63:0] lsu_nonblock_data_unalgn = _T_4739 >> _T_4740; // @[lsu_bus_buffer.scala 544:92] + wire _T_4741 = ~io_dctl_busbuff_lsu_nonblock_load_data_error; // @[lsu_bus_buffer.scala 546:82] + wire _T_4743 = lsu_nonblock_sz == 2'h0; // @[lsu_bus_buffer.scala 547:94] + wire _T_4744 = lsu_nonblock_unsign & _T_4743; // @[lsu_bus_buffer.scala 547:76] + wire [31:0] _T_4746 = {24'h0,lsu_nonblock_data_unalgn[7:0]}; // @[Cat.scala 29:58] + wire _T_4747 = lsu_nonblock_sz == 2'h1; // @[lsu_bus_buffer.scala 548:45] + wire _T_4748 = lsu_nonblock_unsign & _T_4747; // @[lsu_bus_buffer.scala 548:26] + wire [31:0] _T_4750 = {16'h0,lsu_nonblock_data_unalgn[15:0]}; // @[Cat.scala 29:58] + wire _T_4751 = ~lsu_nonblock_unsign; // @[lsu_bus_buffer.scala 549:6] + wire _T_4753 = _T_4751 & _T_4743; // @[lsu_bus_buffer.scala 549:27] + wire [23:0] _T_4756 = lsu_nonblock_data_unalgn[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_4758 = {_T_4756,lsu_nonblock_data_unalgn[7:0]}; // @[Cat.scala 29:58] + wire _T_4761 = _T_4751 & _T_4747; // @[lsu_bus_buffer.scala 550:27] + wire [15:0] _T_4764 = lsu_nonblock_data_unalgn[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_4766 = {_T_4764,lsu_nonblock_data_unalgn[15:0]}; // @[Cat.scala 29:58] + wire _T_4767 = lsu_nonblock_sz == 2'h2; // @[lsu_bus_buffer.scala 551:21] + wire [31:0] _T_4768 = _T_4744 ? _T_4746 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4769 = _T_4748 ? _T_4750 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4770 = _T_4753 ? _T_4758 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4771 = _T_4761 ? _T_4766 : 32'h0; // @[Mux.scala 27:72] + wire [63:0] _T_4772 = _T_4767 ? lsu_nonblock_data_unalgn : 64'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4773 = _T_4768 | _T_4769; // @[Mux.scala 27:72] + wire [31:0] _T_4774 = _T_4773 | _T_4770; // @[Mux.scala 27:72] + wire [31:0] _T_4775 = _T_4774 | _T_4771; // @[Mux.scala 27:72] + wire [63:0] _GEN_393 = {{32'd0}, _T_4775}; // @[Mux.scala 27:72] + wire [63:0] _T_4776 = _GEN_393 | _T_4772; // @[Mux.scala 27:72] + wire _T_4874 = obuf_valid & obuf_write; // @[lsu_bus_buffer.scala 569:37] + wire _T_4875 = ~obuf_cmd_done; // @[lsu_bus_buffer.scala 569:52] + wire _T_4876 = _T_4874 & _T_4875; // @[lsu_bus_buffer.scala 569:50] + wire [31:0] _T_4880 = {obuf_addr[31:3],3'h0}; // @[Cat.scala 29:58] + wire [2:0] _T_4882 = {1'h0,obuf_sz}; // @[Cat.scala 29:58] + wire _T_4887 = ~obuf_data_done; // @[lsu_bus_buffer.scala 581:51] + wire _T_4888 = _T_4874 & _T_4887; // @[lsu_bus_buffer.scala 581:49] + wire [7:0] _T_4892 = obuf_write ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire _T_4895 = obuf_valid & _T_1343; // @[lsu_bus_buffer.scala 586:37] + wire _T_4897 = _T_4895 & _T_1349; // @[lsu_bus_buffer.scala 586:51] + wire _T_4909 = io_lsu_bus_clk_en_q & buf_error[0]; // @[lsu_bus_buffer.scala 599:126] + wire _T_4911 = _T_4909 & buf_write[0]; // @[lsu_bus_buffer.scala 599:141] + wire _T_4914 = io_lsu_bus_clk_en_q & buf_error[1]; // @[lsu_bus_buffer.scala 599:126] + wire _T_4916 = _T_4914 & buf_write[1]; // @[lsu_bus_buffer.scala 599:141] + wire _T_4919 = io_lsu_bus_clk_en_q & buf_error[2]; // @[lsu_bus_buffer.scala 599:126] + wire _T_4921 = _T_4919 & buf_write[2]; // @[lsu_bus_buffer.scala 599:141] + wire _T_4924 = io_lsu_bus_clk_en_q & buf_error[3]; // @[lsu_bus_buffer.scala 599:126] + wire _T_4926 = _T_4924 & buf_write[3]; // @[lsu_bus_buffer.scala 599:141] + wire _T_4927 = _T_2799 & _T_4911; // @[Mux.scala 27:72] + wire _T_4928 = _T_2821 & _T_4916; // @[Mux.scala 27:72] + wire _T_4929 = _T_2843 & _T_4921; // @[Mux.scala 27:72] + wire _T_4930 = _T_2865 & _T_4926; // @[Mux.scala 27:72] + wire _T_4931 = _T_4927 | _T_4928; // @[Mux.scala 27:72] + wire _T_4932 = _T_4931 | _T_4929; // @[Mux.scala 27:72] + wire _T_4942 = _T_2821 & buf_error[1]; // @[lsu_bus_buffer.scala 600:93] + wire _T_4944 = _T_4942 & buf_write[1]; // @[lsu_bus_buffer.scala 600:108] + wire _T_4947 = _T_2843 & buf_error[2]; // @[lsu_bus_buffer.scala 600:93] + wire _T_4949 = _T_4947 & buf_write[2]; // @[lsu_bus_buffer.scala 600:108] + wire _T_4952 = _T_2865 & buf_error[3]; // @[lsu_bus_buffer.scala 600:93] + wire _T_4954 = _T_4952 & buf_write[3]; // @[lsu_bus_buffer.scala 600:108] + wire [1:0] _T_4957 = _T_4949 ? 2'h2 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4958 = _T_4954 ? 2'h3 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _GEN_394 = {{1'd0}, _T_4944}; // @[Mux.scala 27:72] + wire [1:0] _T_4960 = _GEN_394 | _T_4957; // @[Mux.scala 27:72] + wire [1:0] lsu_imprecise_error_store_tag = _T_4960 | _T_4958; // @[Mux.scala 27:72] + wire _T_4962 = ~io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_buffer.scala 602:97] + wire [31:0] _GEN_351 = 2'h1 == lsu_imprecise_error_store_tag ? buf_addr_1 : buf_addr_0; // @[lsu_bus_buffer.scala 603:53] + wire [31:0] _GEN_352 = 2'h2 == lsu_imprecise_error_store_tag ? buf_addr_2 : _GEN_351; // @[lsu_bus_buffer.scala 603:53] + wire [31:0] _GEN_353 = 2'h3 == lsu_imprecise_error_store_tag ? buf_addr_3 : _GEN_352; // @[lsu_bus_buffer.scala 603:53] + wire [31:0] _GEN_355 = 2'h1 == io_dctl_busbuff_lsu_nonblock_load_data_tag ? buf_addr_1 : buf_addr_0; // @[lsu_bus_buffer.scala 603:53] + wire [31:0] _GEN_356 = 2'h2 == io_dctl_busbuff_lsu_nonblock_load_data_tag ? buf_addr_2 : _GEN_355; // @[lsu_bus_buffer.scala 603:53] + wire [31:0] _GEN_357 = 2'h3 == io_dctl_busbuff_lsu_nonblock_load_data_tag ? buf_addr_3 : _GEN_356; // @[lsu_bus_buffer.scala 603:53] + wire _T_4967 = bus_wcmd_sent | bus_wdata_sent; // @[lsu_bus_buffer.scala 609:82] + wire _T_4970 = io_lsu_busreq_r & io_ldst_dual_r; // @[lsu_bus_buffer.scala 610:60] + wire _T_4973 = ~io_lsu_axi_aw_ready; // @[lsu_bus_buffer.scala 613:61] + wire _T_4974 = io_lsu_axi_aw_valid & _T_4973; // @[lsu_bus_buffer.scala 613:59] + wire _T_4975 = ~io_lsu_axi_w_ready; // @[lsu_bus_buffer.scala 613:107] + wire _T_4976 = io_lsu_axi_w_valid & _T_4975; // @[lsu_bus_buffer.scala 613:105] + wire _T_4977 = _T_4974 | _T_4976; // @[lsu_bus_buffer.scala 613:83] + wire _T_4978 = ~io_lsu_axi_ar_ready; // @[lsu_bus_buffer.scala 613:153] + wire _T_4979 = io_lsu_axi_ar_valid & _T_4978; // @[lsu_bus_buffer.scala 613:151] + wire _T_4983 = ~io_flush_r; // @[lsu_bus_buffer.scala 617:75] + wire _T_4984 = io_lsu_busreq_m & _T_4983; // @[lsu_bus_buffer.scala 617:73] + reg _T_4987; // @[lsu_bus_buffer.scala 617:56] + rvclkhdr rvclkhdr ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) + ); + rvclkhdr rvclkhdr_1 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_1_io_l1clk), + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en), + .io_scan_mode(rvclkhdr_1_io_scan_mode) + ); + rvclkhdr rvclkhdr_2 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_2_io_l1clk), + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en), + .io_scan_mode(rvclkhdr_2_io_scan_mode) + ); + rvclkhdr rvclkhdr_3 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_3_io_l1clk), + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en), + .io_scan_mode(rvclkhdr_3_io_scan_mode) + ); + rvclkhdr rvclkhdr_4 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_4_io_l1clk), + .io_clk(rvclkhdr_4_io_clk), + .io_en(rvclkhdr_4_io_en), + .io_scan_mode(rvclkhdr_4_io_scan_mode) + ); + rvclkhdr rvclkhdr_5 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_5_io_l1clk), + .io_clk(rvclkhdr_5_io_clk), + .io_en(rvclkhdr_5_io_en), + .io_scan_mode(rvclkhdr_5_io_scan_mode) + ); + rvclkhdr rvclkhdr_6 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_6_io_l1clk), + .io_clk(rvclkhdr_6_io_clk), + .io_en(rvclkhdr_6_io_en), + .io_scan_mode(rvclkhdr_6_io_scan_mode) + ); + rvclkhdr rvclkhdr_7 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_7_io_l1clk), + .io_clk(rvclkhdr_7_io_clk), + .io_en(rvclkhdr_7_io_en), + .io_scan_mode(rvclkhdr_7_io_scan_mode) + ); + rvclkhdr rvclkhdr_8 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_8_io_l1clk), + .io_clk(rvclkhdr_8_io_clk), + .io_en(rvclkhdr_8_io_en), + .io_scan_mode(rvclkhdr_8_io_scan_mode) + ); + rvclkhdr rvclkhdr_9 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_9_io_l1clk), + .io_clk(rvclkhdr_9_io_clk), + .io_en(rvclkhdr_9_io_en), + .io_scan_mode(rvclkhdr_9_io_scan_mode) + ); + rvclkhdr rvclkhdr_10 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_10_io_l1clk), + .io_clk(rvclkhdr_10_io_clk), + .io_en(rvclkhdr_10_io_en), + .io_scan_mode(rvclkhdr_10_io_scan_mode) + ); + rvclkhdr rvclkhdr_11 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_11_io_l1clk), + .io_clk(rvclkhdr_11_io_clk), + .io_en(rvclkhdr_11_io_en), + .io_scan_mode(rvclkhdr_11_io_scan_mode) + ); + assign io_tlu_busbuff_lsu_pmu_bus_trxn = _T_4967 | _T_4866; // @[lsu_bus_buffer.scala 609:35] + assign io_tlu_busbuff_lsu_pmu_bus_misaligned = _T_4970 & io_lsu_commit_r; // @[lsu_bus_buffer.scala 610:41] + assign io_tlu_busbuff_lsu_pmu_bus_error = io_tlu_busbuff_lsu_imprecise_error_load_any | io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_buffer.scala 611:36] + assign io_tlu_busbuff_lsu_pmu_bus_busy = _T_4977 | _T_4979; // @[lsu_bus_buffer.scala 613:35] + assign io_tlu_busbuff_lsu_imprecise_error_load_any = io_dctl_busbuff_lsu_nonblock_load_data_error & _T_4962; // @[lsu_bus_buffer.scala 602:47] + assign io_tlu_busbuff_lsu_imprecise_error_store_any = _T_4932 | _T_4930; // @[lsu_bus_buffer.scala 599:48] + assign io_tlu_busbuff_lsu_imprecise_error_addr_any = io_tlu_busbuff_lsu_imprecise_error_store_any ? _GEN_353 : _GEN_357; // @[lsu_bus_buffer.scala 603:47] + assign io_dctl_busbuff_lsu_nonblock_load_valid_m = _T_4517 & _T_4518; // @[lsu_bus_buffer.scala 530:45] + assign io_dctl_busbuff_lsu_nonblock_load_tag_m = _T_1863 ? 2'h0 : _T_1899; // @[lsu_bus_buffer.scala 531:43] + assign io_dctl_busbuff_lsu_nonblock_load_inv_r = lsu_nonblock_load_valid_r & _T_4520; // @[lsu_bus_buffer.scala 533:43] + assign io_dctl_busbuff_lsu_nonblock_load_inv_tag_r = WrPtr0_r; // @[lsu_bus_buffer.scala 534:47] + assign io_dctl_busbuff_lsu_nonblock_load_data_valid = lsu_nonblock_load_data_ready & _T_4741; // @[lsu_bus_buffer.scala 546:48] + assign io_dctl_busbuff_lsu_nonblock_load_data_error = _T_4570 | _T_4568; // @[lsu_bus_buffer.scala 536:48] + assign io_dctl_busbuff_lsu_nonblock_load_data_tag = _T_4610 | _T_4608; // @[lsu_bus_buffer.scala 537:46] + assign io_dctl_busbuff_lsu_nonblock_load_data = _T_4776[31:0]; // @[lsu_bus_buffer.scala 547:42] + assign io_lsu_axi_aw_valid = _T_4876 & _T_1239; // @[lsu_bus_buffer.scala 569:23] + assign io_lsu_axi_aw_bits_id = {{1'd0}, _T_1848}; // @[lsu_bus_buffer.scala 570:25] + assign io_lsu_axi_aw_bits_addr = obuf_sideeffect ? obuf_addr : _T_4880; // @[lsu_bus_buffer.scala 571:27] + assign io_lsu_axi_aw_bits_region = obuf_addr[31:28]; // @[lsu_bus_buffer.scala 575:29] + assign io_lsu_axi_aw_bits_size = obuf_sideeffect ? _T_4882 : 3'h3; // @[lsu_bus_buffer.scala 572:27] + assign io_lsu_axi_aw_bits_cache = obuf_sideeffect ? 4'h0 : 4'hf; // @[lsu_bus_buffer.scala 574:28] + assign io_lsu_axi_w_valid = _T_4888 & _T_1239; // @[lsu_bus_buffer.scala 581:22] + assign io_lsu_axi_w_bits_data = obuf_data; // @[lsu_bus_buffer.scala 583:26] + assign io_lsu_axi_w_bits_strb = obuf_byteen & _T_4892; // @[lsu_bus_buffer.scala 582:26] + assign io_lsu_axi_b_ready = 1'h1; // @[lsu_bus_buffer.scala 597:22] + assign io_lsu_axi_ar_valid = _T_4897 & _T_1239; // @[lsu_bus_buffer.scala 586:23] + assign io_lsu_axi_ar_bits_id = {{1'd0}, _T_1848}; // @[lsu_bus_buffer.scala 587:25] + assign io_lsu_axi_ar_bits_addr = obuf_sideeffect ? obuf_addr : _T_4880; // @[lsu_bus_buffer.scala 588:27] + assign io_lsu_axi_ar_bits_region = obuf_addr[31:28]; // @[lsu_bus_buffer.scala 592:29] + assign io_lsu_axi_ar_bits_size = obuf_sideeffect ? _T_4882 : 3'h3; // @[lsu_bus_buffer.scala 589:27] + assign io_lsu_axi_ar_bits_cache = obuf_sideeffect ? 4'h0 : 4'hf; // @[lsu_bus_buffer.scala 591:28] + assign io_lsu_axi_r_ready = 1'h1; // @[lsu_bus_buffer.scala 598:22] + assign io_lsu_busreq_r = _T_4987; // @[lsu_bus_buffer.scala 617:19] + assign io_lsu_bus_buffer_pend_any = |buf_numvld_pend_any; // @[lsu_bus_buffer.scala 526:30] + assign io_lsu_bus_buffer_full_any = _T_4498 ? _T_4499 : _T_4500; // @[lsu_bus_buffer.scala 527:30] + assign io_lsu_bus_buffer_empty_any = _T_4511 & _T_1231; // @[lsu_bus_buffer.scala 528:31] + assign io_ld_byte_hit_buf_lo = {_T_69,_T_58}; // @[lsu_bus_buffer.scala 138:25] + assign io_ld_byte_hit_buf_hi = {_T_84,_T_73}; // @[lsu_bus_buffer.scala 139:25] + assign io_ld_fwddata_buf_lo = _T_650 | _T_651; // @[lsu_bus_buffer.scala 165:24] + assign io_ld_fwddata_buf_hi = _T_747 | _T_748; // @[lsu_bus_buffer.scala 171:24] + assign rvclkhdr_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_io_en = _T_853 & _T_854; // @[lib.scala 371:17] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_1_io_en = _T_853 & _T_854; // @[lib.scala 371:17] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_2_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_2_io_en = _T_1240 & io_lsu_bus_clk_en; // @[lib.scala 371:17] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_3_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_3_io_en = _T_1240 & io_lsu_bus_clk_en; // @[lib.scala 371:17] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_4_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_4_io_en = _T_3528 & buf_state_en_0; // @[lib.scala 371:17] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_5_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_5_io_en = _T_3721 & buf_state_en_1; // @[lib.scala 371:17] + assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_6_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_6_io_en = _T_3914 & buf_state_en_2; // @[lib.scala 371:17] + assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_7_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_7_io_en = _T_4107 & buf_state_en_3; // @[lib.scala 371:17] + assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_8_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_8_io_en = _T_3528 ? buf_state_en_0 : _GEN_70; // @[lib.scala 371:17] + assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_9_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_9_io_en = _T_3721 ? buf_state_en_1 : _GEN_146; // @[lib.scala 371:17] + assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_10_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_10_io_en = _T_3914 ? buf_state_en_2 : _GEN_222; // @[lib.scala 371:17] + assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_11_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_11_io_en = _T_4107 ? buf_state_en_3 : _GEN_298; // @[lib.scala 371:17] + assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + buf_addr_0 = _RAND_0[31:0]; + _RAND_1 = {1{`RANDOM}}; + _T_4360 = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + _T_4357 = _RAND_2[0:0]; + _RAND_3 = {1{`RANDOM}}; + _T_4354 = _RAND_3[0:0]; + _RAND_4 = {1{`RANDOM}}; + _T_4351 = _RAND_4[0:0]; + _RAND_5 = {1{`RANDOM}}; + buf_state_0 = _RAND_5[2:0]; + _RAND_6 = {1{`RANDOM}}; + buf_addr_1 = _RAND_6[31:0]; + _RAND_7 = {1{`RANDOM}}; + buf_state_1 = _RAND_7[2:0]; + _RAND_8 = {1{`RANDOM}}; + buf_addr_2 = _RAND_8[31:0]; + _RAND_9 = {1{`RANDOM}}; + buf_state_2 = _RAND_9[2:0]; + _RAND_10 = {1{`RANDOM}}; + buf_addr_3 = _RAND_10[31:0]; + _RAND_11 = {1{`RANDOM}}; + buf_state_3 = _RAND_11[2:0]; + _RAND_12 = {1{`RANDOM}}; + buf_byteen_3 = _RAND_12[3:0]; + _RAND_13 = {1{`RANDOM}}; + buf_byteen_2 = _RAND_13[3:0]; + _RAND_14 = {1{`RANDOM}}; + buf_byteen_1 = _RAND_14[3:0]; + _RAND_15 = {1{`RANDOM}}; + buf_byteen_0 = _RAND_15[3:0]; + _RAND_16 = {1{`RANDOM}}; + buf_ageQ_3 = _RAND_16[3:0]; + _RAND_17 = {1{`RANDOM}}; + _T_1848 = _RAND_17[1:0]; + _RAND_18 = {1{`RANDOM}}; + obuf_merge = _RAND_18[0:0]; + _RAND_19 = {1{`RANDOM}}; + obuf_tag1 = _RAND_19[1:0]; + _RAND_20 = {1{`RANDOM}}; + obuf_valid = _RAND_20[0:0]; + _RAND_21 = {1{`RANDOM}}; + obuf_wr_enQ = _RAND_21[0:0]; + _RAND_22 = {1{`RANDOM}}; + ibuf_addr = _RAND_22[31:0]; + _RAND_23 = {1{`RANDOM}}; + ibuf_write = _RAND_23[0:0]; + _RAND_24 = {1{`RANDOM}}; + ibuf_valid = _RAND_24[0:0]; + _RAND_25 = {1{`RANDOM}}; + ibuf_byteen = _RAND_25[3:0]; + _RAND_26 = {1{`RANDOM}}; + buf_ageQ_2 = _RAND_26[3:0]; + _RAND_27 = {1{`RANDOM}}; + buf_ageQ_1 = _RAND_27[3:0]; + _RAND_28 = {1{`RANDOM}}; + buf_ageQ_0 = _RAND_28[3:0]; + _RAND_29 = {1{`RANDOM}}; + buf_data_0 = _RAND_29[31:0]; + _RAND_30 = {1{`RANDOM}}; + buf_data_1 = _RAND_30[31:0]; + _RAND_31 = {1{`RANDOM}}; + buf_data_2 = _RAND_31[31:0]; + _RAND_32 = {1{`RANDOM}}; + buf_data_3 = _RAND_32[31:0]; + _RAND_33 = {1{`RANDOM}}; + ibuf_data = _RAND_33[31:0]; + _RAND_34 = {1{`RANDOM}}; + ibuf_timer = _RAND_34[2:0]; + _RAND_35 = {1{`RANDOM}}; + ibuf_sideeffect = _RAND_35[0:0]; + _RAND_36 = {1{`RANDOM}}; + WrPtr1_r = _RAND_36[1:0]; + _RAND_37 = {1{`RANDOM}}; + WrPtr0_r = _RAND_37[1:0]; + _RAND_38 = {1{`RANDOM}}; + ibuf_tag = _RAND_38[1:0]; + _RAND_39 = {1{`RANDOM}}; + ibuf_dualtag = _RAND_39[1:0]; + _RAND_40 = {1{`RANDOM}}; + ibuf_dual = _RAND_40[0:0]; + _RAND_41 = {1{`RANDOM}}; + ibuf_samedw = _RAND_41[0:0]; + _RAND_42 = {1{`RANDOM}}; + ibuf_nomerge = _RAND_42[0:0]; + _RAND_43 = {1{`RANDOM}}; + ibuf_unsign = _RAND_43[0:0]; + _RAND_44 = {1{`RANDOM}}; + ibuf_sz = _RAND_44[1:0]; + _RAND_45 = {1{`RANDOM}}; + obuf_wr_timer = _RAND_45[2:0]; + _RAND_46 = {1{`RANDOM}}; + buf_nomerge_0 = _RAND_46[0:0]; + _RAND_47 = {1{`RANDOM}}; + buf_nomerge_1 = _RAND_47[0:0]; + _RAND_48 = {1{`RANDOM}}; + buf_nomerge_2 = _RAND_48[0:0]; + _RAND_49 = {1{`RANDOM}}; + buf_nomerge_3 = _RAND_49[0:0]; + _RAND_50 = {1{`RANDOM}}; + _T_4330 = _RAND_50[0:0]; + _RAND_51 = {1{`RANDOM}}; + _T_4327 = _RAND_51[0:0]; + _RAND_52 = {1{`RANDOM}}; + _T_4324 = _RAND_52[0:0]; + _RAND_53 = {1{`RANDOM}}; + _T_4321 = _RAND_53[0:0]; + _RAND_54 = {1{`RANDOM}}; + obuf_sideeffect = _RAND_54[0:0]; + _RAND_55 = {1{`RANDOM}}; + buf_dual_3 = _RAND_55[0:0]; + _RAND_56 = {1{`RANDOM}}; + buf_dual_2 = _RAND_56[0:0]; + _RAND_57 = {1{`RANDOM}}; + buf_dual_1 = _RAND_57[0:0]; + _RAND_58 = {1{`RANDOM}}; + buf_dual_0 = _RAND_58[0:0]; + _RAND_59 = {1{`RANDOM}}; + buf_samedw_3 = _RAND_59[0:0]; + _RAND_60 = {1{`RANDOM}}; + buf_samedw_2 = _RAND_60[0:0]; + _RAND_61 = {1{`RANDOM}}; + buf_samedw_1 = _RAND_61[0:0]; + _RAND_62 = {1{`RANDOM}}; + buf_samedw_0 = _RAND_62[0:0]; + _RAND_63 = {1{`RANDOM}}; + obuf_write = _RAND_63[0:0]; + _RAND_64 = {1{`RANDOM}}; + obuf_cmd_done = _RAND_64[0:0]; + _RAND_65 = {1{`RANDOM}}; + obuf_data_done = _RAND_65[0:0]; + _RAND_66 = {1{`RANDOM}}; + obuf_nosend = _RAND_66[0:0]; + _RAND_67 = {1{`RANDOM}}; + obuf_addr = _RAND_67[31:0]; + _RAND_68 = {1{`RANDOM}}; + buf_sz_0 = _RAND_68[1:0]; + _RAND_69 = {1{`RANDOM}}; + buf_sz_1 = _RAND_69[1:0]; + _RAND_70 = {1{`RANDOM}}; + buf_sz_2 = _RAND_70[1:0]; + _RAND_71 = {1{`RANDOM}}; + buf_sz_3 = _RAND_71[1:0]; + _RAND_72 = {1{`RANDOM}}; + obuf_rdrsp_pend = _RAND_72[0:0]; + _RAND_73 = {1{`RANDOM}}; + obuf_rdrsp_tag = _RAND_73[2:0]; + _RAND_74 = {1{`RANDOM}}; + buf_dualhi_3 = _RAND_74[0:0]; + _RAND_75 = {1{`RANDOM}}; + buf_dualhi_2 = _RAND_75[0:0]; + _RAND_76 = {1{`RANDOM}}; + buf_dualhi_1 = _RAND_76[0:0]; + _RAND_77 = {1{`RANDOM}}; + buf_dualhi_0 = _RAND_77[0:0]; + _RAND_78 = {1{`RANDOM}}; + obuf_sz = _RAND_78[1:0]; + _RAND_79 = {1{`RANDOM}}; + obuf_byteen = _RAND_79[7:0]; + _RAND_80 = {2{`RANDOM}}; + obuf_data = _RAND_80[63:0]; + _RAND_81 = {1{`RANDOM}}; + buf_rspageQ_0 = _RAND_81[3:0]; + _RAND_82 = {1{`RANDOM}}; + buf_rspageQ_1 = _RAND_82[3:0]; + _RAND_83 = {1{`RANDOM}}; + buf_rspageQ_2 = _RAND_83[3:0]; + _RAND_84 = {1{`RANDOM}}; + buf_rspageQ_3 = _RAND_84[3:0]; + _RAND_85 = {1{`RANDOM}}; + _T_4307 = _RAND_85[0:0]; + _RAND_86 = {1{`RANDOM}}; + _T_4305 = _RAND_86[0:0]; + _RAND_87 = {1{`RANDOM}}; + _T_4303 = _RAND_87[0:0]; + _RAND_88 = {1{`RANDOM}}; + _T_4301 = _RAND_88[0:0]; + _RAND_89 = {1{`RANDOM}}; + buf_ldfwdtag_0 = _RAND_89[1:0]; + _RAND_90 = {1{`RANDOM}}; + buf_dualtag_0 = _RAND_90[1:0]; + _RAND_91 = {1{`RANDOM}}; + buf_ldfwdtag_3 = _RAND_91[1:0]; + _RAND_92 = {1{`RANDOM}}; + buf_ldfwdtag_2 = _RAND_92[1:0]; + _RAND_93 = {1{`RANDOM}}; + buf_ldfwdtag_1 = _RAND_93[1:0]; + _RAND_94 = {1{`RANDOM}}; + buf_dualtag_1 = _RAND_94[1:0]; + _RAND_95 = {1{`RANDOM}}; + buf_dualtag_2 = _RAND_95[1:0]; + _RAND_96 = {1{`RANDOM}}; + buf_dualtag_3 = _RAND_96[1:0]; + _RAND_97 = {1{`RANDOM}}; + _T_4336 = _RAND_97[0:0]; + _RAND_98 = {1{`RANDOM}}; + _T_4339 = _RAND_98[0:0]; + _RAND_99 = {1{`RANDOM}}; + _T_4342 = _RAND_99[0:0]; + _RAND_100 = {1{`RANDOM}}; + _T_4345 = _RAND_100[0:0]; + _RAND_101 = {1{`RANDOM}}; + _T_4411 = _RAND_101[0:0]; + _RAND_102 = {1{`RANDOM}}; + _T_4406 = _RAND_102[0:0]; + _RAND_103 = {1{`RANDOM}}; + _T_4401 = _RAND_103[0:0]; + _RAND_104 = {1{`RANDOM}}; + _T_4396 = _RAND_104[0:0]; + _RAND_105 = {1{`RANDOM}}; + lsu_nonblock_load_valid_r = _RAND_105[0:0]; + _RAND_106 = {1{`RANDOM}}; + _T_4987 = _RAND_106[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + buf_addr_0 = 32'h0; + end + if (reset) begin + _T_4360 = 1'h0; + end + if (reset) begin + _T_4357 = 1'h0; + end + if (reset) begin + _T_4354 = 1'h0; + end + if (reset) begin + _T_4351 = 1'h0; + end + if (reset) begin + buf_state_0 = 3'h0; + end + if (reset) begin + buf_addr_1 = 32'h0; + end + if (reset) begin + buf_state_1 = 3'h0; + end + if (reset) begin + buf_addr_2 = 32'h0; + end + if (reset) begin + buf_state_2 = 3'h0; + end + if (reset) begin + buf_addr_3 = 32'h0; + end + if (reset) begin + buf_state_3 = 3'h0; + end + if (reset) begin + buf_byteen_3 = 4'h0; + end + if (reset) begin + buf_byteen_2 = 4'h0; + end + if (reset) begin + buf_byteen_1 = 4'h0; + end + if (reset) begin + buf_byteen_0 = 4'h0; + end + if (reset) begin + buf_ageQ_3 = 4'h0; + end + if (reset) begin + _T_1848 = 2'h0; + end + if (reset) begin + obuf_merge = 1'h0; + end + if (reset) begin + obuf_tag1 = 2'h0; + end + if (reset) begin + obuf_valid = 1'h0; + end + if (reset) begin + obuf_wr_enQ = 1'h0; + end + if (reset) begin + ibuf_addr = 32'h0; + end + if (reset) begin + ibuf_write = 1'h0; + end + if (reset) begin + ibuf_valid = 1'h0; + end + if (reset) begin + ibuf_byteen = 4'h0; + end + if (reset) begin + buf_ageQ_2 = 4'h0; + end + if (reset) begin + buf_ageQ_1 = 4'h0; + end + if (reset) begin + buf_ageQ_0 = 4'h0; + end + if (reset) begin + buf_data_0 = 32'h0; + end + if (reset) begin + buf_data_1 = 32'h0; + end + if (reset) begin + buf_data_2 = 32'h0; + end + if (reset) begin + buf_data_3 = 32'h0; + end + if (reset) begin + ibuf_data = 32'h0; + end + if (reset) begin + ibuf_timer = 3'h0; + end + if (reset) begin + ibuf_sideeffect = 1'h0; + end + if (reset) begin + WrPtr1_r = 2'h0; + end + if (reset) begin + WrPtr0_r = 2'h0; + end + if (reset) begin + ibuf_tag = 2'h0; + end + if (reset) begin + ibuf_dualtag = 2'h0; + end + if (reset) begin + ibuf_dual = 1'h0; + end + if (reset) begin + ibuf_samedw = 1'h0; + end + if (reset) begin + ibuf_nomerge = 1'h0; + end + if (reset) begin + ibuf_unsign = 1'h0; + end + if (reset) begin + ibuf_sz = 2'h0; + end + if (reset) begin + obuf_wr_timer = 3'h0; + end + if (reset) begin + buf_nomerge_0 = 1'h0; + end + if (reset) begin + buf_nomerge_1 = 1'h0; + end + if (reset) begin + buf_nomerge_2 = 1'h0; + end + if (reset) begin + buf_nomerge_3 = 1'h0; + end + if (reset) begin + _T_4330 = 1'h0; + end + if (reset) begin + _T_4327 = 1'h0; + end + if (reset) begin + _T_4324 = 1'h0; + end + if (reset) begin + _T_4321 = 1'h0; + end + if (reset) begin + obuf_sideeffect = 1'h0; + end + if (reset) begin + buf_dual_3 = 1'h0; + end + if (reset) begin + buf_dual_2 = 1'h0; + end + if (reset) begin + buf_dual_1 = 1'h0; + end + if (reset) begin + buf_dual_0 = 1'h0; + end + if (reset) begin + buf_samedw_3 = 1'h0; + end + if (reset) begin + buf_samedw_2 = 1'h0; + end + if (reset) begin + buf_samedw_1 = 1'h0; + end + if (reset) begin + buf_samedw_0 = 1'h0; + end + if (reset) begin + obuf_write = 1'h0; + end + if (reset) begin + obuf_cmd_done = 1'h0; + end + if (reset) begin + obuf_data_done = 1'h0; + end + if (reset) begin + obuf_nosend = 1'h0; + end + if (reset) begin + obuf_addr = 32'h0; + end + if (reset) begin + buf_sz_0 = 2'h0; + end + if (reset) begin + buf_sz_1 = 2'h0; + end + if (reset) begin + buf_sz_2 = 2'h0; + end + if (reset) begin + buf_sz_3 = 2'h0; + end + if (reset) begin + obuf_rdrsp_pend = 1'h0; + end + if (reset) begin + obuf_rdrsp_tag = 3'h0; + end + if (reset) begin + buf_dualhi_3 = 1'h0; + end + if (reset) begin + buf_dualhi_2 = 1'h0; + end + if (reset) begin + buf_dualhi_1 = 1'h0; + end + if (reset) begin + buf_dualhi_0 = 1'h0; + end + if (reset) begin + obuf_sz = 2'h0; + end + if (reset) begin + obuf_byteen = 8'h0; + end + if (reset) begin + obuf_data = 64'h0; + end + if (reset) begin + buf_rspageQ_0 = 4'h0; + end + if (reset) begin + buf_rspageQ_1 = 4'h0; + end + if (reset) begin + buf_rspageQ_2 = 4'h0; + end + if (reset) begin + buf_rspageQ_3 = 4'h0; + end + if (reset) begin + _T_4307 = 1'h0; + end + if (reset) begin + _T_4305 = 1'h0; + end + if (reset) begin + _T_4303 = 1'h0; + end + if (reset) begin + _T_4301 = 1'h0; + end + if (reset) begin + buf_ldfwdtag_0 = 2'h0; + end + if (reset) begin + buf_dualtag_0 = 2'h0; + end + if (reset) begin + buf_ldfwdtag_3 = 2'h0; + end + if (reset) begin + buf_ldfwdtag_2 = 2'h0; + end + if (reset) begin + buf_ldfwdtag_1 = 2'h0; + end + if (reset) begin + buf_dualtag_1 = 2'h0; + end + if (reset) begin + buf_dualtag_2 = 2'h0; + end + if (reset) begin + buf_dualtag_3 = 2'h0; + end + if (reset) begin + _T_4336 = 1'h0; + end + if (reset) begin + _T_4339 = 1'h0; + end + if (reset) begin + _T_4342 = 1'h0; + end + if (reset) begin + _T_4345 = 1'h0; + end + if (reset) begin + _T_4411 = 1'h0; + end + if (reset) begin + _T_4406 = 1'h0; + end + if (reset) begin + _T_4401 = 1'h0; + end + if (reset) begin + _T_4396 = 1'h0; + end + if (reset) begin + lsu_nonblock_load_valid_r = 1'h0; + end + if (reset) begin + _T_4987 = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + if (reset) begin + buf_addr_0 <= 32'h0; + end else if (ibuf_drainvec_vld[0]) begin + buf_addr_0 <= ibuf_addr; + end else if (_T_3343) begin + buf_addr_0 <= io_end_addr_r; + end else begin + buf_addr_0 <= io_lsu_addr_r; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4360 <= 1'h0; + end else if (buf_wr_en_3) begin + _T_4360 <= buf_write_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4357 <= 1'h0; + end else if (buf_wr_en_2) begin + _T_4357 <= buf_write_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4354 <= 1'h0; + end else if (buf_wr_en_1) begin + _T_4354 <= buf_write_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4351 <= 1'h0; + end else if (buf_wr_en_0) begin + _T_4351 <= buf_write_in[0]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_state_0 <= 3'h0; + end else if (buf_state_en_0) begin + if (_T_3528) begin + if (io_lsu_bus_clk_en) begin + buf_state_0 <= 3'h2; + end else begin + buf_state_0 <= 3'h1; + end + end else if (_T_3551) begin + if (io_dec_tlu_force_halt) begin + buf_state_0 <= 3'h0; + end else begin + buf_state_0 <= 3'h2; + end + end else if (_T_3555) begin + if (io_dec_tlu_force_halt) begin + buf_state_0 <= 3'h0; + end else if (_T_3559) begin + buf_state_0 <= 3'h5; + end else begin + buf_state_0 <= 3'h3; + end + end else if (_T_3589) begin + if (_T_3594) begin + buf_state_0 <= 3'h0; + end else if (_T_3602) begin + buf_state_0 <= 3'h4; + end else if (_T_3630) begin + buf_state_0 <= 3'h5; + end else begin + buf_state_0 <= 3'h6; + end + end else if (_T_3676) begin + if (io_dec_tlu_force_halt) begin + buf_state_0 <= 3'h0; + end else if (_T_3682) begin + buf_state_0 <= 3'h5; + end else begin + buf_state_0 <= 3'h6; + end + end else if (_T_3694) begin + if (io_dec_tlu_force_halt) begin + buf_state_0 <= 3'h0; + end else begin + buf_state_0 <= 3'h6; + end + end else begin + buf_state_0 <= 3'h0; + end + end + end + always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + if (reset) begin + buf_addr_1 <= 32'h0; + end else if (ibuf_drainvec_vld[1]) begin + buf_addr_1 <= ibuf_addr; + end else if (_T_3352) begin + buf_addr_1 <= io_end_addr_r; + end else begin + buf_addr_1 <= io_lsu_addr_r; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_state_1 <= 3'h0; + end else if (buf_state_en_1) begin + if (_T_3721) begin + if (io_lsu_bus_clk_en) begin + buf_state_1 <= 3'h2; + end else begin + buf_state_1 <= 3'h1; + end + end else if (_T_3744) begin + if (io_dec_tlu_force_halt) begin + buf_state_1 <= 3'h0; + end else begin + buf_state_1 <= 3'h2; + end + end else if (_T_3748) begin + if (io_dec_tlu_force_halt) begin + buf_state_1 <= 3'h0; + end else if (_T_3559) begin + buf_state_1 <= 3'h5; + end else begin + buf_state_1 <= 3'h3; + end + end else if (_T_3782) begin + if (_T_3787) begin + buf_state_1 <= 3'h0; + end else if (_T_3795) begin + buf_state_1 <= 3'h4; + end else if (_T_3823) begin + buf_state_1 <= 3'h5; + end else begin + buf_state_1 <= 3'h6; + end + end else if (_T_3869) begin + if (io_dec_tlu_force_halt) begin + buf_state_1 <= 3'h0; + end else if (_T_3875) begin + buf_state_1 <= 3'h5; + end else begin + buf_state_1 <= 3'h6; + end + end else if (_T_3887) begin + if (io_dec_tlu_force_halt) begin + buf_state_1 <= 3'h0; + end else begin + buf_state_1 <= 3'h6; + end + end else begin + buf_state_1 <= 3'h0; + end + end + end + always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin + if (reset) begin + buf_addr_2 <= 32'h0; + end else if (ibuf_drainvec_vld[2]) begin + buf_addr_2 <= ibuf_addr; + end else if (_T_3361) begin + buf_addr_2 <= io_end_addr_r; + end else begin + buf_addr_2 <= io_lsu_addr_r; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_state_2 <= 3'h0; + end else if (buf_state_en_2) begin + if (_T_3914) begin + if (io_lsu_bus_clk_en) begin + buf_state_2 <= 3'h2; + end else begin + buf_state_2 <= 3'h1; + end + end else if (_T_3937) begin + if (io_dec_tlu_force_halt) begin + buf_state_2 <= 3'h0; + end else begin + buf_state_2 <= 3'h2; + end + end else if (_T_3941) begin + if (io_dec_tlu_force_halt) begin + buf_state_2 <= 3'h0; + end else if (_T_3559) begin + buf_state_2 <= 3'h5; + end else begin + buf_state_2 <= 3'h3; + end + end else if (_T_3975) begin + if (_T_3980) begin + buf_state_2 <= 3'h0; + end else if (_T_3988) begin + buf_state_2 <= 3'h4; + end else if (_T_4016) begin + buf_state_2 <= 3'h5; + end else begin + buf_state_2 <= 3'h6; + end + end else if (_T_4062) begin + if (io_dec_tlu_force_halt) begin + buf_state_2 <= 3'h0; + end else if (_T_4068) begin + buf_state_2 <= 3'h5; + end else begin + buf_state_2 <= 3'h6; + end + end else if (_T_4080) begin + if (io_dec_tlu_force_halt) begin + buf_state_2 <= 3'h0; + end else begin + buf_state_2 <= 3'h6; + end + end else begin + buf_state_2 <= 3'h0; + end + end + end + always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin + if (reset) begin + buf_addr_3 <= 32'h0; + end else if (ibuf_drainvec_vld[3]) begin + buf_addr_3 <= ibuf_addr; + end else if (_T_3370) begin + buf_addr_3 <= io_end_addr_r; + end else begin + buf_addr_3 <= io_lsu_addr_r; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_state_3 <= 3'h0; + end else if (buf_state_en_3) begin + if (_T_4107) begin + if (io_lsu_bus_clk_en) begin + buf_state_3 <= 3'h2; + end else begin + buf_state_3 <= 3'h1; + end + end else if (_T_4130) begin + if (io_dec_tlu_force_halt) begin + buf_state_3 <= 3'h0; + end else begin + buf_state_3 <= 3'h2; + end + end else if (_T_4134) begin + if (io_dec_tlu_force_halt) begin + buf_state_3 <= 3'h0; + end else if (_T_3559) begin + buf_state_3 <= 3'h5; + end else begin + buf_state_3 <= 3'h3; + end + end else if (_T_4168) begin + if (_T_4173) begin + buf_state_3 <= 3'h0; + end else if (_T_4181) begin + buf_state_3 <= 3'h4; + end else if (_T_4209) begin + buf_state_3 <= 3'h5; + end else begin + buf_state_3 <= 3'h6; + end + end else if (_T_4255) begin + if (io_dec_tlu_force_halt) begin + buf_state_3 <= 3'h0; + end else if (_T_4261) begin + buf_state_3 <= 3'h5; + end else begin + buf_state_3 <= 3'h6; + end + end else if (_T_4273) begin + if (io_dec_tlu_force_halt) begin + buf_state_3 <= 3'h0; + end else begin + buf_state_3 <= 3'h6; + end + end else begin + buf_state_3 <= 3'h0; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_byteen_3 <= 4'h0; + end else if (buf_wr_en_3) begin + if (ibuf_drainvec_vld[3]) begin + buf_byteen_3 <= ibuf_byteen_out; + end else if (_T_3370) begin + buf_byteen_3 <= ldst_byteen_hi_r; + end else begin + buf_byteen_3 <= ldst_byteen_lo_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_byteen_2 <= 4'h0; + end else if (buf_wr_en_2) begin + if (ibuf_drainvec_vld[2]) begin + buf_byteen_2 <= ibuf_byteen_out; + end else if (_T_3361) begin + buf_byteen_2 <= ldst_byteen_hi_r; + end else begin + buf_byteen_2 <= ldst_byteen_lo_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_byteen_1 <= 4'h0; + end else if (buf_wr_en_1) begin + if (ibuf_drainvec_vld[1]) begin + buf_byteen_1 <= ibuf_byteen_out; + end else if (_T_3352) begin + buf_byteen_1 <= ldst_byteen_hi_r; + end else begin + buf_byteen_1 <= ldst_byteen_lo_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_byteen_0 <= 4'h0; + end else if (buf_wr_en_0) begin + if (ibuf_drainvec_vld[0]) begin + buf_byteen_0 <= ibuf_byteen_out; + end else if (_T_3343) begin + buf_byteen_0 <= ldst_byteen_hi_r; + end else begin + buf_byteen_0 <= ldst_byteen_lo_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ageQ_3 <= 4'h0; + end else begin + buf_ageQ_3 <= {_T_2535,_T_2458}; + end + end + always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin + if (reset) begin + _T_1848 <= 2'h0; + end else if (obuf_wr_en) begin + if (ibuf_buf_byp) begin + _T_1848 <= WrPtr0_r; + end else begin + _T_1848 <= CmdPtr0; + end + end + end + always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin + if (reset) begin + obuf_merge <= 1'h0; + end else if (obuf_wr_en) begin + obuf_merge <= obuf_merge_en; + end + end + always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin + if (reset) begin + obuf_tag1 <= 2'h0; + end else if (obuf_wr_en) begin + if (ibuf_buf_byp) begin + obuf_tag1 <= WrPtr1_r; + end else begin + obuf_tag1 <= CmdPtr1; + end + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + obuf_valid <= 1'h0; + end else begin + obuf_valid <= _T_1839 & _T_1840; + end + end + always @(posedge io_lsu_busm_clk or posedge reset) begin + if (reset) begin + obuf_wr_enQ <= 1'h0; + end else begin + obuf_wr_enQ <= _T_1240 & io_lsu_bus_clk_en; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + if (reset) begin + ibuf_addr <= 32'h0; + end else if (io_ldst_dual_r) begin + ibuf_addr <= io_end_addr_r; + end else begin + ibuf_addr <= io_lsu_addr_r; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_write <= 1'h0; + end else if (ibuf_wr_en) begin + ibuf_write <= io_lsu_pkt_r_bits_store; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + ibuf_valid <= 1'h0; + end else begin + ibuf_valid <= _T_1005 & _T_1006; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_byteen <= 4'h0; + end else if (ibuf_wr_en) begin + if (_T_866) begin + ibuf_byteen <= _T_881; + end else if (io_ldst_dual_r) begin + ibuf_byteen <= ldst_byteen_hi_r; + end else begin + ibuf_byteen <= ldst_byteen_lo_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ageQ_2 <= 4'h0; + end else begin + buf_ageQ_2 <= {_T_2433,_T_2356}; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ageQ_1 <= 4'h0; + end else begin + buf_ageQ_1 <= {_T_2331,_T_2254}; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ageQ_0 <= 4'h0; + end else begin + buf_ageQ_0 <= {_T_2229,_T_2152}; + end + end + always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin + if (reset) begin + buf_data_0 <= 32'h0; + end else if (_T_3528) begin + if (_T_3543) begin + buf_data_0 <= ibuf_data_out; + end else begin + buf_data_0 <= store_data_lo_r; + end + end else if (_T_3551) begin + buf_data_0 <= 32'h0; + end else if (_T_3555) begin + if (buf_error_en_0) begin + buf_data_0 <= io_lsu_axi_r_bits_data[31:0]; + end else if (buf_addr_0[2]) begin + buf_data_0 <= io_lsu_axi_r_bits_data[63:32]; + end else begin + buf_data_0 <= io_lsu_axi_r_bits_data[31:0]; + end + end else if (_T_3589) begin + if (_T_3669) begin + if (buf_addr_0[2]) begin + buf_data_0 <= io_lsu_axi_r_bits_data[63:32]; + end else begin + buf_data_0 <= io_lsu_axi_r_bits_data[31:0]; + end + end else begin + buf_data_0 <= io_lsu_axi_r_bits_data[31:0]; + end + end else begin + buf_data_0 <= 32'h0; + end + end + always @(posedge rvclkhdr_9_io_l1clk or posedge reset) begin + if (reset) begin + buf_data_1 <= 32'h0; + end else if (_T_3721) begin + if (_T_3736) begin + buf_data_1 <= ibuf_data_out; + end else begin + buf_data_1 <= store_data_lo_r; + end + end else if (_T_3744) begin + buf_data_1 <= 32'h0; + end else if (_T_3748) begin + if (buf_error_en_1) begin + buf_data_1 <= io_lsu_axi_r_bits_data[31:0]; + end else if (buf_addr_1[2]) begin + buf_data_1 <= io_lsu_axi_r_bits_data[63:32]; + end else begin + buf_data_1 <= io_lsu_axi_r_bits_data[31:0]; + end + end else if (_T_3782) begin + if (_T_3862) begin + if (buf_addr_1[2]) begin + buf_data_1 <= io_lsu_axi_r_bits_data[63:32]; + end else begin + buf_data_1 <= io_lsu_axi_r_bits_data[31:0]; + end + end else begin + buf_data_1 <= io_lsu_axi_r_bits_data[31:0]; + end + end else begin + buf_data_1 <= 32'h0; + end + end + always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin + if (reset) begin + buf_data_2 <= 32'h0; + end else if (_T_3914) begin + if (_T_3929) begin + buf_data_2 <= ibuf_data_out; + end else begin + buf_data_2 <= store_data_lo_r; + end + end else if (_T_3937) begin + buf_data_2 <= 32'h0; + end else if (_T_3941) begin + if (buf_error_en_2) begin + buf_data_2 <= io_lsu_axi_r_bits_data[31:0]; + end else if (buf_addr_2[2]) begin + buf_data_2 <= io_lsu_axi_r_bits_data[63:32]; + end else begin + buf_data_2 <= io_lsu_axi_r_bits_data[31:0]; + end + end else if (_T_3975) begin + if (_T_4055) begin + if (buf_addr_2[2]) begin + buf_data_2 <= io_lsu_axi_r_bits_data[63:32]; + end else begin + buf_data_2 <= io_lsu_axi_r_bits_data[31:0]; + end + end else begin + buf_data_2 <= io_lsu_axi_r_bits_data[31:0]; + end + end else begin + buf_data_2 <= 32'h0; + end + end + always @(posedge rvclkhdr_11_io_l1clk or posedge reset) begin + if (reset) begin + buf_data_3 <= 32'h0; + end else if (_T_4107) begin + if (_T_4122) begin + buf_data_3 <= ibuf_data_out; + end else begin + buf_data_3 <= store_data_lo_r; + end + end else if (_T_4130) begin + buf_data_3 <= 32'h0; + end else if (_T_4134) begin + if (buf_error_en_3) begin + buf_data_3 <= io_lsu_axi_r_bits_data[31:0]; + end else if (buf_addr_3[2]) begin + buf_data_3 <= io_lsu_axi_r_bits_data[63:32]; + end else begin + buf_data_3 <= io_lsu_axi_r_bits_data[31:0]; + end + end else if (_T_4168) begin + if (_T_4248) begin + if (buf_addr_3[2]) begin + buf_data_3 <= io_lsu_axi_r_bits_data[63:32]; + end else begin + buf_data_3 <= io_lsu_axi_r_bits_data[31:0]; + end + end else begin + buf_data_3 <= io_lsu_axi_r_bits_data[31:0]; + end + end else begin + buf_data_3 <= 32'h0; + end + end + always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin + if (reset) begin + ibuf_data <= 32'h0; + end else begin + ibuf_data <= {_T_922,_T_893}; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + ibuf_timer <= 3'h0; + end else if (ibuf_wr_en) begin + ibuf_timer <= 3'h0; + end else if (_T_923) begin + ibuf_timer <= _T_926; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_sideeffect <= 1'h0; + end else if (ibuf_wr_en) begin + ibuf_sideeffect <= io_is_sideeffects_r; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + WrPtr1_r <= 2'h0; + end else if (_T_1914) begin + WrPtr1_r <= 2'h0; + end else if (_T_1928) begin + WrPtr1_r <= 2'h1; + end else if (_T_1942) begin + WrPtr1_r <= 2'h2; + end else begin + WrPtr1_r <= 2'h3; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + WrPtr0_r <= 2'h0; + end else if (_T_1863) begin + WrPtr0_r <= 2'h0; + end else if (_T_1874) begin + WrPtr0_r <= 2'h1; + end else if (_T_1885) begin + WrPtr0_r <= 2'h2; + end else begin + WrPtr0_r <= 2'h3; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_tag <= 2'h0; + end else if (ibuf_wr_en) begin + if (!(_T_866)) begin + if (io_ldst_dual_r) begin + ibuf_tag <= WrPtr1_r; + end else begin + ibuf_tag <= WrPtr0_r; + end + end + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_dualtag <= 2'h0; + end else if (ibuf_wr_en) begin + ibuf_dualtag <= WrPtr0_r; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_dual <= 1'h0; + end else if (ibuf_wr_en) begin + ibuf_dual <= io_ldst_dual_r; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_samedw <= 1'h0; + end else if (ibuf_wr_en) begin + ibuf_samedw <= ldst_samedw_r; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_nomerge <= 1'h0; + end else if (ibuf_wr_en) begin + ibuf_nomerge <= io_no_dword_merge_r; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_unsign <= 1'h0; + end else if (ibuf_wr_en) begin + ibuf_unsign <= io_lsu_pkt_r_bits_unsign; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_sz <= 2'h0; + end else if (ibuf_wr_en) begin + ibuf_sz <= ibuf_sz_in; + end + end + always @(posedge io_lsu_busm_clk or posedge reset) begin + if (reset) begin + obuf_wr_timer <= 3'h0; + end else if (obuf_wr_en) begin + obuf_wr_timer <= 3'h0; + end else if (_T_1058) begin + obuf_wr_timer <= _T_1060; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_nomerge_0 <= 1'h0; + end else if (buf_wr_en_0) begin + buf_nomerge_0 <= buf_nomerge_in[0]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_nomerge_1 <= 1'h0; + end else if (buf_wr_en_1) begin + buf_nomerge_1 <= buf_nomerge_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_nomerge_2 <= 1'h0; + end else if (buf_wr_en_2) begin + buf_nomerge_2 <= buf_nomerge_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_nomerge_3 <= 1'h0; + end else if (buf_wr_en_3) begin + buf_nomerge_3 <= buf_nomerge_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4330 <= 1'h0; + end else if (buf_wr_en_3) begin + _T_4330 <= buf_sideeffect_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4327 <= 1'h0; + end else if (buf_wr_en_2) begin + _T_4327 <= buf_sideeffect_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4324 <= 1'h0; + end else if (buf_wr_en_1) begin + _T_4324 <= buf_sideeffect_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4321 <= 1'h0; + end else if (buf_wr_en_0) begin + _T_4321 <= buf_sideeffect_in[0]; + end + end + always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin + if (reset) begin + obuf_sideeffect <= 1'h0; + end else if (obuf_wr_en) begin + if (ibuf_buf_byp) begin + obuf_sideeffect <= io_is_sideeffects_r; + end else begin + obuf_sideeffect <= _T_1051; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dual_3 <= 1'h0; + end else if (buf_wr_en_3) begin + buf_dual_3 <= buf_dual_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dual_2 <= 1'h0; + end else if (buf_wr_en_2) begin + buf_dual_2 <= buf_dual_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dual_1 <= 1'h0; + end else if (buf_wr_en_1) begin + buf_dual_1 <= buf_dual_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dual_0 <= 1'h0; + end else if (buf_wr_en_0) begin + buf_dual_0 <= buf_dual_in[0]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_samedw_3 <= 1'h0; + end else if (buf_wr_en_3) begin + buf_samedw_3 <= buf_samedw_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_samedw_2 <= 1'h0; + end else if (buf_wr_en_2) begin + buf_samedw_2 <= buf_samedw_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_samedw_1 <= 1'h0; + end else if (buf_wr_en_1) begin + buf_samedw_1 <= buf_samedw_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_samedw_0 <= 1'h0; + end else if (buf_wr_en_0) begin + buf_samedw_0 <= buf_samedw_in[0]; + end + end + always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin + if (reset) begin + obuf_write <= 1'h0; + end else if (obuf_wr_en) begin + if (ibuf_buf_byp) begin + obuf_write <= io_lsu_pkt_r_bits_store; + end else begin + obuf_write <= _T_1202; + end + end + end + always @(posedge io_lsu_busm_clk or posedge reset) begin + if (reset) begin + obuf_cmd_done <= 1'h0; + end else begin + obuf_cmd_done <= _T_1305 & _T_4863; + end + end + always @(posedge io_lsu_busm_clk or posedge reset) begin + if (reset) begin + obuf_data_done <= 1'h0; + end else begin + obuf_data_done <= _T_1305 & _T_4864; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + obuf_nosend <= 1'h0; + end else if (obuf_wr_en) begin + obuf_nosend <= obuf_nosend_in; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + obuf_addr <= 32'h0; + end else if (ibuf_buf_byp) begin + obuf_addr <= io_lsu_addr_r; + end else begin + obuf_addr <= _T_1289; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_sz_0 <= 2'h0; + end else if (buf_wr_en_0) begin + if (ibuf_drainvec_vld[0]) begin + buf_sz_0 <= ibuf_sz; + end else begin + buf_sz_0 <= ibuf_sz_in; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_sz_1 <= 2'h0; + end else if (buf_wr_en_1) begin + if (ibuf_drainvec_vld[1]) begin + buf_sz_1 <= ibuf_sz; + end else begin + buf_sz_1 <= ibuf_sz_in; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_sz_2 <= 2'h0; + end else if (buf_wr_en_2) begin + if (ibuf_drainvec_vld[2]) begin + buf_sz_2 <= ibuf_sz; + end else begin + buf_sz_2 <= ibuf_sz_in; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_sz_3 <= 2'h0; + end else if (buf_wr_en_3) begin + if (ibuf_drainvec_vld[3]) begin + buf_sz_3 <= ibuf_sz; + end else begin + buf_sz_3 <= ibuf_sz_in; + end + end + end + always @(posedge io_lsu_busm_clk or posedge reset) begin + if (reset) begin + obuf_rdrsp_pend <= 1'h0; + end else begin + obuf_rdrsp_pend <= _T_1330 | _T_1334; + end + end + always @(posedge io_lsu_busm_clk or posedge reset) begin + if (reset) begin + obuf_rdrsp_tag <= 3'h0; + end else if (_T_1332) begin + obuf_rdrsp_tag <= obuf_tag0; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualhi_3 <= 1'h0; + end else if (buf_wr_en_3) begin + buf_dualhi_3 <= buf_dualhi_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualhi_2 <= 1'h0; + end else if (buf_wr_en_2) begin + buf_dualhi_2 <= buf_dualhi_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualhi_1 <= 1'h0; + end else if (buf_wr_en_1) begin + buf_dualhi_1 <= buf_dualhi_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualhi_0 <= 1'h0; + end else if (buf_wr_en_0) begin + buf_dualhi_0 <= buf_dualhi_in[0]; + end + end + always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin + if (reset) begin + obuf_sz <= 2'h0; + end else if (obuf_wr_en) begin + if (ibuf_buf_byp) begin + obuf_sz <= ibuf_sz_in; + end else begin + obuf_sz <= _T_1302; + end + end + end + always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin + if (reset) begin + obuf_byteen <= 8'h0; + end else if (obuf_wr_en) begin + obuf_byteen <= obuf_byteen_in; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + obuf_data <= 64'h0; + end else begin + obuf_data <= {_T_1620,_T_1579}; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_rspageQ_0 <= 4'h0; + end else begin + buf_rspageQ_0 <= {_T_3173,_T_3162}; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_rspageQ_1 <= 4'h0; + end else begin + buf_rspageQ_1 <= {_T_3188,_T_3177}; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_rspageQ_2 <= 4'h0; + end else begin + buf_rspageQ_2 <= {_T_3203,_T_3192}; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_rspageQ_3 <= 4'h0; + end else begin + buf_rspageQ_3 <= {_T_3218,_T_3207}; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4307 <= 1'h0; + end else if (buf_ldfwd_en_3) begin + if (_T_4107) begin + _T_4307 <= 1'h0; + end else if (_T_4130) begin + _T_4307 <= 1'h0; + end else begin + _T_4307 <= _T_4134; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4305 <= 1'h0; + end else if (buf_ldfwd_en_2) begin + if (_T_3914) begin + _T_4305 <= 1'h0; + end else if (_T_3937) begin + _T_4305 <= 1'h0; + end else begin + _T_4305 <= _T_3941; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4303 <= 1'h0; + end else if (buf_ldfwd_en_1) begin + if (_T_3721) begin + _T_4303 <= 1'h0; + end else if (_T_3744) begin + _T_4303 <= 1'h0; + end else begin + _T_4303 <= _T_3748; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4301 <= 1'h0; + end else if (buf_ldfwd_en_0) begin + if (_T_3528) begin + _T_4301 <= 1'h0; + end else if (_T_3551) begin + _T_4301 <= 1'h0; + end else begin + _T_4301 <= _T_3555; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ldfwdtag_0 <= 2'h0; + end else if (buf_ldfwd_en_0) begin + if (_T_3528) begin + buf_ldfwdtag_0 <= 2'h0; + end else if (_T_3551) begin + buf_ldfwdtag_0 <= 2'h0; + end else if (_T_3555) begin + buf_ldfwdtag_0 <= obuf_rdrsp_tag[1:0]; + end else begin + buf_ldfwdtag_0 <= 2'h0; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualtag_0 <= 2'h0; + end else if (buf_wr_en_0) begin + if (ibuf_drainvec_vld[0]) begin + buf_dualtag_0 <= ibuf_dualtag; + end else if (_T_3343) begin + buf_dualtag_0 <= WrPtr0_r; + end else begin + buf_dualtag_0 <= WrPtr1_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ldfwdtag_3 <= 2'h0; + end else if (buf_ldfwd_en_3) begin + if (_T_4107) begin + buf_ldfwdtag_3 <= 2'h0; + end else if (_T_4130) begin + buf_ldfwdtag_3 <= 2'h0; + end else if (_T_4134) begin + buf_ldfwdtag_3 <= obuf_rdrsp_tag[1:0]; + end else begin + buf_ldfwdtag_3 <= 2'h0; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ldfwdtag_2 <= 2'h0; + end else if (buf_ldfwd_en_2) begin + if (_T_3914) begin + buf_ldfwdtag_2 <= 2'h0; + end else if (_T_3937) begin + buf_ldfwdtag_2 <= 2'h0; + end else if (_T_3941) begin + buf_ldfwdtag_2 <= obuf_rdrsp_tag[1:0]; + end else begin + buf_ldfwdtag_2 <= 2'h0; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ldfwdtag_1 <= 2'h0; + end else if (buf_ldfwd_en_1) begin + if (_T_3721) begin + buf_ldfwdtag_1 <= 2'h0; + end else if (_T_3744) begin + buf_ldfwdtag_1 <= 2'h0; + end else if (_T_3748) begin + buf_ldfwdtag_1 <= obuf_rdrsp_tag[1:0]; + end else begin + buf_ldfwdtag_1 <= 2'h0; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualtag_1 <= 2'h0; + end else if (buf_wr_en_1) begin + if (ibuf_drainvec_vld[1]) begin + buf_dualtag_1 <= ibuf_dualtag; + end else if (_T_3352) begin + buf_dualtag_1 <= WrPtr0_r; + end else begin + buf_dualtag_1 <= WrPtr1_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualtag_2 <= 2'h0; + end else if (buf_wr_en_2) begin + if (ibuf_drainvec_vld[2]) begin + buf_dualtag_2 <= ibuf_dualtag; + end else if (_T_3361) begin + buf_dualtag_2 <= WrPtr0_r; + end else begin + buf_dualtag_2 <= WrPtr1_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualtag_3 <= 2'h0; + end else if (buf_wr_en_3) begin + if (ibuf_drainvec_vld[3]) begin + buf_dualtag_3 <= ibuf_dualtag; + end else if (_T_3370) begin + buf_dualtag_3 <= WrPtr0_r; + end else begin + buf_dualtag_3 <= WrPtr1_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4336 <= 1'h0; + end else if (buf_wr_en_0) begin + _T_4336 <= buf_unsign_in[0]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4339 <= 1'h0; + end else if (buf_wr_en_1) begin + _T_4339 <= buf_unsign_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4342 <= 1'h0; + end else if (buf_wr_en_2) begin + _T_4342 <= buf_unsign_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4345 <= 1'h0; + end else if (buf_wr_en_3) begin + _T_4345 <= buf_unsign_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4411 <= 1'h0; + end else begin + _T_4411 <= _T_4408 & _T_4409; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4406 <= 1'h0; + end else begin + _T_4406 <= _T_4403 & _T_4404; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4401 <= 1'h0; + end else begin + _T_4401 <= _T_4398 & _T_4399; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4396 <= 1'h0; + end else begin + _T_4396 <= _T_4393 & _T_4394; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + lsu_nonblock_load_valid_r <= 1'h0; + end else begin + lsu_nonblock_load_valid_r <= io_dctl_busbuff_lsu_nonblock_load_valid_m; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_4987 <= 1'h0; + end else begin + _T_4987 <= _T_4984 & _T_4518; + end + end +endmodule +module lsu_bus_intf( + input clock, + input reset, + input io_scan_mode, + output io_tlu_busbuff_lsu_pmu_bus_trxn, + output io_tlu_busbuff_lsu_pmu_bus_misaligned, + output io_tlu_busbuff_lsu_pmu_bus_error, + output io_tlu_busbuff_lsu_pmu_bus_busy, + input io_tlu_busbuff_dec_tlu_external_ldfwd_disable, + input io_tlu_busbuff_dec_tlu_wb_coalescing_disable, + input io_tlu_busbuff_dec_tlu_sideeffect_posted_disable, + output io_tlu_busbuff_lsu_imprecise_error_load_any, + output io_tlu_busbuff_lsu_imprecise_error_store_any, + output [31:0] io_tlu_busbuff_lsu_imprecise_error_addr_any, + input io_lsu_c1_m_clk, + input io_lsu_c1_r_clk, + input io_lsu_c2_r_clk, + input io_lsu_bus_ibuf_c1_clk, + input io_lsu_bus_obuf_c1_clk, + input io_lsu_bus_buf_c1_clk, + input io_lsu_free_c2_clk, + input io_free_clk, + input io_lsu_busm_clk, + input io_axi_aw_ready, + output io_axi_aw_valid, + output [2:0] io_axi_aw_bits_id, + output [31:0] io_axi_aw_bits_addr, + output [3:0] io_axi_aw_bits_region, + output [2:0] io_axi_aw_bits_size, + output [3:0] io_axi_aw_bits_cache, + input io_axi_w_ready, + output io_axi_w_valid, + output [63:0] io_axi_w_bits_data, + output [7:0] io_axi_w_bits_strb, + input io_axi_b_valid, + input [1:0] io_axi_b_bits_resp, + input [2:0] io_axi_b_bits_id, + input io_axi_ar_ready, + output io_axi_ar_valid, + output [2:0] io_axi_ar_bits_id, + output [31:0] io_axi_ar_bits_addr, + output [3:0] io_axi_ar_bits_region, + output [2:0] io_axi_ar_bits_size, + output [3:0] io_axi_ar_bits_cache, + input io_axi_r_valid, + input [2:0] io_axi_r_bits_id, + input [63:0] io_axi_r_bits_data, + input [1:0] io_axi_r_bits_resp, + input io_dec_lsu_valid_raw_d, + input io_lsu_busreq_m, + input io_lsu_pkt_m_valid, + input io_lsu_pkt_m_bits_by, + input io_lsu_pkt_m_bits_half, + input io_lsu_pkt_m_bits_word, + input io_lsu_pkt_m_bits_load, + input io_lsu_pkt_r_valid, + input io_lsu_pkt_r_bits_by, + input io_lsu_pkt_r_bits_half, + input io_lsu_pkt_r_bits_word, + input io_lsu_pkt_r_bits_load, + input io_lsu_pkt_r_bits_store, + input io_lsu_pkt_r_bits_unsign, + input [31:0] io_lsu_addr_d, + input [31:0] io_lsu_addr_m, + input [31:0] io_lsu_addr_r, + input [31:0] io_end_addr_d, + input [31:0] io_end_addr_m, + input [31:0] io_end_addr_r, + input [31:0] io_store_data_r, + input io_dec_tlu_force_halt, + input io_lsu_commit_r, + input io_is_sideeffects_m, + input io_flush_m_up, + input io_flush_r, + output io_lsu_busreq_r, + output io_lsu_bus_buffer_pend_any, + output io_lsu_bus_buffer_full_any, + output io_lsu_bus_buffer_empty_any, + output [31:0] io_bus_read_data_m, + output io_dctl_busbuff_lsu_nonblock_load_valid_m, + output [1:0] io_dctl_busbuff_lsu_nonblock_load_tag_m, + output io_dctl_busbuff_lsu_nonblock_load_inv_r, + output [1:0] io_dctl_busbuff_lsu_nonblock_load_inv_tag_r, + output io_dctl_busbuff_lsu_nonblock_load_data_valid, + output io_dctl_busbuff_lsu_nonblock_load_data_error, + output [1:0] io_dctl_busbuff_lsu_nonblock_load_data_tag, + output [31:0] io_dctl_busbuff_lsu_nonblock_load_data, + input io_lsu_bus_clk_en +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; +`endif // RANDOMIZE_REG_INIT + wire bus_buffer_clock; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_reset; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_scan_mode; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_lsu_pmu_bus_trxn; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_lsu_pmu_bus_error; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_lsu_pmu_bus_busy; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[lsu_bus_intf.scala 100:39] + wire [1:0] bus_buffer_io_dctl_busbuff_lsu_nonblock_load_tag_m; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_dctl_busbuff_lsu_nonblock_load_inv_r; // @[lsu_bus_intf.scala 100:39] + wire [1:0] bus_buffer_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_valid; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_error; // @[lsu_bus_intf.scala 100:39] + wire [1:0] bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_tag; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_dec_tlu_force_halt; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_c2_r_clk; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_bus_ibuf_c1_clk; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_bus_obuf_c1_clk; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_bus_buf_c1_clk; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_free_c2_clk; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_busm_clk; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_dec_lsu_valid_raw_d; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_pkt_m_valid; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_pkt_m_bits_load; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_pkt_r_bits_by; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_pkt_r_bits_half; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_pkt_r_bits_word; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_pkt_r_bits_load; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_pkt_r_bits_unsign; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_lsu_addr_m; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_end_addr_m; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_lsu_addr_r; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_end_addr_r; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_store_data_r; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_no_word_merge_r; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_no_dword_merge_r; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_busreq_m; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_ld_full_hit_m; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_flush_m_up; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_flush_r; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_commit_r; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_is_sideeffects_r; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_ldst_dual_d; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_ldst_dual_m; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_ldst_dual_r; // @[lsu_bus_intf.scala 100:39] + wire [7:0] bus_buffer_io_ldst_byteen_ext_m; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_aw_ready; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_aw_valid; // @[lsu_bus_intf.scala 100:39] + wire [2:0] bus_buffer_io_lsu_axi_aw_bits_id; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_lsu_axi_aw_bits_addr; // @[lsu_bus_intf.scala 100:39] + wire [3:0] bus_buffer_io_lsu_axi_aw_bits_region; // @[lsu_bus_intf.scala 100:39] + wire [2:0] bus_buffer_io_lsu_axi_aw_bits_size; // @[lsu_bus_intf.scala 100:39] + wire [3:0] bus_buffer_io_lsu_axi_aw_bits_cache; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_w_ready; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_w_valid; // @[lsu_bus_intf.scala 100:39] + wire [63:0] bus_buffer_io_lsu_axi_w_bits_data; // @[lsu_bus_intf.scala 100:39] + wire [7:0] bus_buffer_io_lsu_axi_w_bits_strb; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_b_ready; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_b_valid; // @[lsu_bus_intf.scala 100:39] + wire [1:0] bus_buffer_io_lsu_axi_b_bits_resp; // @[lsu_bus_intf.scala 100:39] + wire [2:0] bus_buffer_io_lsu_axi_b_bits_id; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_ar_ready; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_ar_valid; // @[lsu_bus_intf.scala 100:39] + wire [2:0] bus_buffer_io_lsu_axi_ar_bits_id; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_lsu_axi_ar_bits_addr; // @[lsu_bus_intf.scala 100:39] + wire [3:0] bus_buffer_io_lsu_axi_ar_bits_region; // @[lsu_bus_intf.scala 100:39] + wire [2:0] bus_buffer_io_lsu_axi_ar_bits_size; // @[lsu_bus_intf.scala 100:39] + wire [3:0] bus_buffer_io_lsu_axi_ar_bits_cache; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_r_ready; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_r_valid; // @[lsu_bus_intf.scala 100:39] + wire [2:0] bus_buffer_io_lsu_axi_r_bits_id; // @[lsu_bus_intf.scala 100:39] + wire [63:0] bus_buffer_io_lsu_axi_r_bits_data; // @[lsu_bus_intf.scala 100:39] + wire [1:0] bus_buffer_io_lsu_axi_r_bits_resp; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_bus_clk_en; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_bus_clk_en_q; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_busreq_r; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_bus_buffer_pend_any; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_bus_buffer_full_any; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_bus_buffer_empty_any; // @[lsu_bus_intf.scala 100:39] + wire [3:0] bus_buffer_io_ld_byte_hit_buf_lo; // @[lsu_bus_intf.scala 100:39] + wire [3:0] bus_buffer_io_ld_byte_hit_buf_hi; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_ld_fwddata_buf_lo; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_ld_fwddata_buf_hi; // @[lsu_bus_intf.scala 100:39] + wire [3:0] _T_3 = io_lsu_pkt_m_bits_word ? 4'hf : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_4 = io_lsu_pkt_m_bits_half ? 4'h3 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_5 = io_lsu_pkt_m_bits_by ? 4'h1 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_6 = _T_3 | _T_4; // @[Mux.scala 27:72] + wire [3:0] ldst_byteen_m = _T_6 | _T_5; // @[Mux.scala 27:72] + wire addr_match_dw_lo_r_m = io_lsu_addr_r[31:3] == io_lsu_addr_m[31:3]; // @[lsu_bus_intf.scala 154:51] + wire _T_17 = io_lsu_addr_r[2] ^ io_lsu_addr_m[2]; // @[lsu_bus_intf.scala 155:71] + wire _T_18 = ~_T_17; // @[lsu_bus_intf.scala 155:53] + wire addr_match_word_lo_r_m = addr_match_dw_lo_r_m & _T_18; // @[lsu_bus_intf.scala 155:51] + reg ldst_dual_r; // @[lsu_bus_intf.scala 200:33] + wire _T_20 = ~ldst_dual_r; // @[lsu_bus_intf.scala 156:48] + wire _T_21 = io_lsu_busreq_r & _T_20; // @[lsu_bus_intf.scala 156:46] + wire _T_22 = _T_21 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 156:61] + wire _T_23 = ~addr_match_word_lo_r_m; // @[lsu_bus_intf.scala 156:107] + wire _T_24 = io_lsu_pkt_m_bits_load | _T_23; // @[lsu_bus_intf.scala 156:105] + wire _T_29 = ~addr_match_dw_lo_r_m; // @[lsu_bus_intf.scala 157:107] + wire _T_30 = io_lsu_pkt_m_bits_load | _T_29; // @[lsu_bus_intf.scala 157:105] + wire [6:0] _GEN_0 = {{3'd0}, ldst_byteen_m}; // @[lsu_bus_intf.scala 159:49] + wire [6:0] _T_34 = _GEN_0 << io_lsu_addr_m[1:0]; // @[lsu_bus_intf.scala 159:49] + reg [3:0] ldst_byteen_r; // @[lsu_bus_intf.scala 202:33] + wire [6:0] _GEN_1 = {{3'd0}, ldst_byteen_r}; // @[lsu_bus_intf.scala 160:49] + wire [6:0] _T_37 = _GEN_1 << io_lsu_addr_r[1:0]; // @[lsu_bus_intf.scala 160:49] + wire [4:0] _T_40 = {io_lsu_addr_r[1:0],3'h0}; // @[Cat.scala 29:58] + wire [62:0] _GEN_2 = {{31'd0}, io_store_data_r}; // @[lsu_bus_intf.scala 161:52] + wire [62:0] _T_41 = _GEN_2 << _T_40; // @[lsu_bus_intf.scala 161:52] + wire [7:0] ldst_byteen_ext_m = {{1'd0}, _T_34}; // @[lsu_bus_intf.scala 159:27] + wire [3:0] ldst_byteen_hi_m = ldst_byteen_ext_m[7:4]; // @[lsu_bus_intf.scala 162:47] + wire [3:0] ldst_byteen_lo_m = ldst_byteen_ext_m[3:0]; // @[lsu_bus_intf.scala 163:47] + wire [7:0] ldst_byteen_ext_r = {{1'd0}, _T_37}; // @[lsu_bus_intf.scala 160:27] + wire [3:0] ldst_byteen_hi_r = ldst_byteen_ext_r[7:4]; // @[lsu_bus_intf.scala 164:47] + wire [3:0] ldst_byteen_lo_r = ldst_byteen_ext_r[3:0]; // @[lsu_bus_intf.scala 165:47] + wire [63:0] store_data_ext_r = {{1'd0}, _T_41}; // @[lsu_bus_intf.scala 161:27] + wire [31:0] store_data_hi_r = store_data_ext_r[63:32]; // @[lsu_bus_intf.scala 167:46] + wire [31:0] store_data_lo_r = store_data_ext_r[31:0]; // @[lsu_bus_intf.scala 168:46] + wire _T_50 = io_lsu_addr_m[31:2] == io_lsu_addr_r[31:2]; // @[lsu_bus_intf.scala 169:51] + wire _T_51 = _T_50 & io_lsu_pkt_r_valid; // @[lsu_bus_intf.scala 169:76] + wire _T_52 = _T_51 & io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 169:97] + wire ld_addr_rhit_lo_lo = _T_52 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 169:123] + wire _T_56 = io_end_addr_m[31:2] == io_lsu_addr_r[31:2]; // @[lsu_bus_intf.scala 170:51] + wire _T_57 = _T_56 & io_lsu_pkt_r_valid; // @[lsu_bus_intf.scala 170:76] + wire _T_58 = _T_57 & io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 170:97] + wire ld_addr_rhit_lo_hi = _T_58 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 170:123] + wire _T_62 = io_lsu_addr_m[31:2] == io_end_addr_r[31:2]; // @[lsu_bus_intf.scala 171:51] + wire _T_63 = _T_62 & io_lsu_pkt_r_valid; // @[lsu_bus_intf.scala 171:76] + wire _T_64 = _T_63 & io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 171:97] + wire ld_addr_rhit_hi_lo = _T_64 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 171:123] + wire _T_68 = io_end_addr_m[31:2] == io_end_addr_r[31:2]; // @[lsu_bus_intf.scala 172:51] + wire _T_69 = _T_68 & io_lsu_pkt_r_valid; // @[lsu_bus_intf.scala 172:76] + wire _T_70 = _T_69 & io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 172:97] + wire ld_addr_rhit_hi_hi = _T_70 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 172:123] + wire _T_73 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[0]; // @[lsu_bus_intf.scala 174:70] + wire _T_75 = _T_73 & ldst_byteen_lo_m[0]; // @[lsu_bus_intf.scala 174:92] + wire _T_77 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[1]; // @[lsu_bus_intf.scala 174:70] + wire _T_79 = _T_77 & ldst_byteen_lo_m[1]; // @[lsu_bus_intf.scala 174:92] + wire _T_81 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[2]; // @[lsu_bus_intf.scala 174:70] + wire _T_83 = _T_81 & ldst_byteen_lo_m[2]; // @[lsu_bus_intf.scala 174:92] + wire _T_85 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[3]; // @[lsu_bus_intf.scala 174:70] + wire _T_87 = _T_85 & ldst_byteen_lo_m[3]; // @[lsu_bus_intf.scala 174:92] + wire [3:0] ld_byte_rhit_lo_lo = {_T_87,_T_83,_T_79,_T_75}; // @[Cat.scala 29:58] + wire _T_92 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[0]; // @[lsu_bus_intf.scala 175:70] + wire _T_94 = _T_92 & ldst_byteen_hi_m[0]; // @[lsu_bus_intf.scala 175:92] + wire _T_96 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[1]; // @[lsu_bus_intf.scala 175:70] + wire _T_98 = _T_96 & ldst_byteen_hi_m[1]; // @[lsu_bus_intf.scala 175:92] + wire _T_100 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[2]; // @[lsu_bus_intf.scala 175:70] + wire _T_102 = _T_100 & ldst_byteen_hi_m[2]; // @[lsu_bus_intf.scala 175:92] + wire _T_104 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[3]; // @[lsu_bus_intf.scala 175:70] + wire _T_106 = _T_104 & ldst_byteen_hi_m[3]; // @[lsu_bus_intf.scala 175:92] + wire [3:0] ld_byte_rhit_lo_hi = {_T_106,_T_102,_T_98,_T_94}; // @[Cat.scala 29:58] + wire _T_111 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[0]; // @[lsu_bus_intf.scala 176:70] + wire _T_113 = _T_111 & ldst_byteen_lo_m[0]; // @[lsu_bus_intf.scala 176:92] + wire _T_115 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[1]; // @[lsu_bus_intf.scala 176:70] + wire _T_117 = _T_115 & ldst_byteen_lo_m[1]; // @[lsu_bus_intf.scala 176:92] + wire _T_119 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[2]; // @[lsu_bus_intf.scala 176:70] + wire _T_121 = _T_119 & ldst_byteen_lo_m[2]; // @[lsu_bus_intf.scala 176:92] + wire _T_123 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[3]; // @[lsu_bus_intf.scala 176:70] + wire _T_125 = _T_123 & ldst_byteen_lo_m[3]; // @[lsu_bus_intf.scala 176:92] + wire [3:0] ld_byte_rhit_hi_lo = {_T_125,_T_121,_T_117,_T_113}; // @[Cat.scala 29:58] + wire _T_130 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[0]; // @[lsu_bus_intf.scala 177:70] + wire _T_132 = _T_130 & ldst_byteen_hi_m[0]; // @[lsu_bus_intf.scala 177:92] + wire _T_134 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[1]; // @[lsu_bus_intf.scala 177:70] + wire _T_136 = _T_134 & ldst_byteen_hi_m[1]; // @[lsu_bus_intf.scala 177:92] + wire _T_138 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[2]; // @[lsu_bus_intf.scala 177:70] + wire _T_140 = _T_138 & ldst_byteen_hi_m[2]; // @[lsu_bus_intf.scala 177:92] + wire _T_142 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[3]; // @[lsu_bus_intf.scala 177:70] + wire _T_144 = _T_142 & ldst_byteen_hi_m[3]; // @[lsu_bus_intf.scala 177:92] + wire [3:0] ld_byte_rhit_hi_hi = {_T_144,_T_140,_T_136,_T_132}; // @[Cat.scala 29:58] + wire _T_150 = ld_byte_rhit_lo_lo[0] | ld_byte_rhit_hi_lo[0]; // @[lsu_bus_intf.scala 179:73] + wire [3:0] ld_byte_hit_buf_lo = bus_buffer_io_ld_byte_hit_buf_lo; // @[lsu_bus_intf.scala 137:38] + wire _T_152 = _T_150 | ld_byte_hit_buf_lo[0]; // @[lsu_bus_intf.scala 179:97] + wire _T_155 = ld_byte_rhit_lo_lo[1] | ld_byte_rhit_hi_lo[1]; // @[lsu_bus_intf.scala 179:73] + wire _T_157 = _T_155 | ld_byte_hit_buf_lo[1]; // @[lsu_bus_intf.scala 179:97] + wire _T_160 = ld_byte_rhit_lo_lo[2] | ld_byte_rhit_hi_lo[2]; // @[lsu_bus_intf.scala 179:73] + wire _T_162 = _T_160 | ld_byte_hit_buf_lo[2]; // @[lsu_bus_intf.scala 179:97] + wire _T_165 = ld_byte_rhit_lo_lo[3] | ld_byte_rhit_hi_lo[3]; // @[lsu_bus_intf.scala 179:73] + wire _T_167 = _T_165 | ld_byte_hit_buf_lo[3]; // @[lsu_bus_intf.scala 179:97] + wire [3:0] ld_byte_hit_lo = {_T_167,_T_162,_T_157,_T_152}; // @[Cat.scala 29:58] + wire _T_173 = ld_byte_rhit_lo_hi[0] | ld_byte_rhit_hi_hi[0]; // @[lsu_bus_intf.scala 180:73] + wire [3:0] ld_byte_hit_buf_hi = bus_buffer_io_ld_byte_hit_buf_hi; // @[lsu_bus_intf.scala 138:38] + wire _T_175 = _T_173 | ld_byte_hit_buf_hi[0]; // @[lsu_bus_intf.scala 180:97] + wire _T_178 = ld_byte_rhit_lo_hi[1] | ld_byte_rhit_hi_hi[1]; // @[lsu_bus_intf.scala 180:73] + wire _T_180 = _T_178 | ld_byte_hit_buf_hi[1]; // @[lsu_bus_intf.scala 180:97] + wire _T_183 = ld_byte_rhit_lo_hi[2] | ld_byte_rhit_hi_hi[2]; // @[lsu_bus_intf.scala 180:73] + wire _T_185 = _T_183 | ld_byte_hit_buf_hi[2]; // @[lsu_bus_intf.scala 180:97] + wire _T_188 = ld_byte_rhit_lo_hi[3] | ld_byte_rhit_hi_hi[3]; // @[lsu_bus_intf.scala 180:73] + wire _T_190 = _T_188 | ld_byte_hit_buf_hi[3]; // @[lsu_bus_intf.scala 180:97] + wire [3:0] ld_byte_hit_hi = {_T_190,_T_185,_T_180,_T_175}; // @[Cat.scala 29:58] + wire [3:0] ld_byte_rhit_lo = {_T_165,_T_160,_T_155,_T_150}; // @[Cat.scala 29:58] + wire [3:0] ld_byte_rhit_hi = {_T_188,_T_183,_T_178,_T_173}; // @[Cat.scala 29:58] + wire [7:0] _T_228 = ld_byte_rhit_lo_lo[0] ? store_data_lo_r[7:0] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_229 = ld_byte_rhit_hi_lo[0] ? store_data_hi_r[7:0] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_230 = _T_228 | _T_229; // @[Mux.scala 27:72] + wire [7:0] _T_236 = ld_byte_rhit_lo_lo[1] ? store_data_lo_r[15:8] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_237 = ld_byte_rhit_hi_lo[1] ? store_data_hi_r[15:8] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_238 = _T_236 | _T_237; // @[Mux.scala 27:72] + wire [7:0] _T_244 = ld_byte_rhit_lo_lo[2] ? store_data_lo_r[23:16] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_245 = ld_byte_rhit_hi_lo[2] ? store_data_hi_r[23:16] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_246 = _T_244 | _T_245; // @[Mux.scala 27:72] + wire [7:0] _T_252 = ld_byte_rhit_lo_lo[3] ? store_data_lo_r[31:24] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_253 = ld_byte_rhit_hi_lo[3] ? store_data_hi_r[31:24] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_254 = _T_252 | _T_253; // @[Mux.scala 27:72] + wire [31:0] ld_fwddata_rpipe_lo = {_T_254,_T_246,_T_238,_T_230}; // @[Cat.scala 29:58] + wire [7:0] _T_263 = ld_byte_rhit_lo_hi[0] ? store_data_lo_r[7:0] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_264 = ld_byte_rhit_hi_hi[0] ? store_data_hi_r[7:0] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_265 = _T_263 | _T_264; // @[Mux.scala 27:72] + wire [7:0] _T_271 = ld_byte_rhit_lo_hi[1] ? store_data_lo_r[15:8] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_272 = ld_byte_rhit_hi_hi[1] ? store_data_hi_r[15:8] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_273 = _T_271 | _T_272; // @[Mux.scala 27:72] + wire [7:0] _T_279 = ld_byte_rhit_lo_hi[2] ? store_data_lo_r[23:16] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_280 = ld_byte_rhit_hi_hi[2] ? store_data_hi_r[23:16] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_281 = _T_279 | _T_280; // @[Mux.scala 27:72] + wire [7:0] _T_287 = ld_byte_rhit_lo_hi[3] ? store_data_lo_r[31:24] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_288 = ld_byte_rhit_hi_hi[3] ? store_data_hi_r[31:24] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_289 = _T_287 | _T_288; // @[Mux.scala 27:72] + wire [31:0] ld_fwddata_rpipe_hi = {_T_289,_T_281,_T_273,_T_265}; // @[Cat.scala 29:58] + wire [31:0] ld_fwddata_buf_lo = bus_buffer_io_ld_fwddata_buf_lo; // @[lsu_bus_intf.scala 139:38] + wire [7:0] _T_297 = ld_byte_rhit_lo[0] ? ld_fwddata_rpipe_lo[7:0] : ld_fwddata_buf_lo[7:0]; // @[lsu_bus_intf.scala 185:54] + wire [7:0] _T_301 = ld_byte_rhit_lo[1] ? ld_fwddata_rpipe_lo[15:8] : ld_fwddata_buf_lo[15:8]; // @[lsu_bus_intf.scala 185:54] + wire [7:0] _T_305 = ld_byte_rhit_lo[2] ? ld_fwddata_rpipe_lo[23:16] : ld_fwddata_buf_lo[23:16]; // @[lsu_bus_intf.scala 185:54] + wire [7:0] _T_309 = ld_byte_rhit_lo[3] ? ld_fwddata_rpipe_lo[31:24] : ld_fwddata_buf_lo[31:24]; // @[lsu_bus_intf.scala 185:54] + wire [31:0] _T_312 = {_T_309,_T_305,_T_301,_T_297}; // @[Cat.scala 29:58] + wire [31:0] ld_fwddata_buf_hi = bus_buffer_io_ld_fwddata_buf_hi; // @[lsu_bus_intf.scala 140:38] + wire [7:0] _T_316 = ld_byte_rhit_hi[0] ? ld_fwddata_rpipe_hi[7:0] : ld_fwddata_buf_hi[7:0]; // @[lsu_bus_intf.scala 186:54] + wire [7:0] _T_320 = ld_byte_rhit_hi[1] ? ld_fwddata_rpipe_hi[15:8] : ld_fwddata_buf_hi[15:8]; // @[lsu_bus_intf.scala 186:54] + wire [7:0] _T_324 = ld_byte_rhit_hi[2] ? ld_fwddata_rpipe_hi[23:16] : ld_fwddata_buf_hi[23:16]; // @[lsu_bus_intf.scala 186:54] + wire [7:0] _T_328 = ld_byte_rhit_hi[3] ? ld_fwddata_rpipe_hi[31:24] : ld_fwddata_buf_hi[31:24]; // @[lsu_bus_intf.scala 186:54] + wire [31:0] _T_331 = {_T_328,_T_324,_T_320,_T_316}; // @[Cat.scala 29:58] + wire _T_334 = ~ldst_byteen_lo_m[0]; // @[lsu_bus_intf.scala 187:72] + wire _T_335 = ld_byte_hit_lo[0] | _T_334; // @[lsu_bus_intf.scala 187:70] + wire _T_338 = ~ldst_byteen_lo_m[1]; // @[lsu_bus_intf.scala 187:72] + wire _T_339 = ld_byte_hit_lo[1] | _T_338; // @[lsu_bus_intf.scala 187:70] + wire _T_342 = ~ldst_byteen_lo_m[2]; // @[lsu_bus_intf.scala 187:72] + wire _T_343 = ld_byte_hit_lo[2] | _T_342; // @[lsu_bus_intf.scala 187:70] + wire _T_346 = ~ldst_byteen_lo_m[3]; // @[lsu_bus_intf.scala 187:72] + wire _T_347 = ld_byte_hit_lo[3] | _T_346; // @[lsu_bus_intf.scala 187:70] + wire _T_348 = _T_335 & _T_339; // @[lsu_bus_intf.scala 187:111] + wire _T_349 = _T_348 & _T_343; // @[lsu_bus_intf.scala 187:111] + wire ld_full_hit_lo_m = _T_349 & _T_347; // @[lsu_bus_intf.scala 187:111] + wire _T_353 = ~ldst_byteen_hi_m[0]; // @[lsu_bus_intf.scala 188:72] + wire _T_354 = ld_byte_hit_hi[0] | _T_353; // @[lsu_bus_intf.scala 188:70] + wire _T_357 = ~ldst_byteen_hi_m[1]; // @[lsu_bus_intf.scala 188:72] + wire _T_358 = ld_byte_hit_hi[1] | _T_357; // @[lsu_bus_intf.scala 188:70] + wire _T_361 = ~ldst_byteen_hi_m[2]; // @[lsu_bus_intf.scala 188:72] + wire _T_362 = ld_byte_hit_hi[2] | _T_361; // @[lsu_bus_intf.scala 188:70] + wire _T_365 = ~ldst_byteen_hi_m[3]; // @[lsu_bus_intf.scala 188:72] + wire _T_366 = ld_byte_hit_hi[3] | _T_365; // @[lsu_bus_intf.scala 188:70] + wire _T_367 = _T_354 & _T_358; // @[lsu_bus_intf.scala 188:111] + wire _T_368 = _T_367 & _T_362; // @[lsu_bus_intf.scala 188:111] + wire ld_full_hit_hi_m = _T_368 & _T_366; // @[lsu_bus_intf.scala 188:111] + wire _T_370 = ld_full_hit_lo_m & ld_full_hit_hi_m; // @[lsu_bus_intf.scala 189:47] + wire _T_371 = _T_370 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 189:66] + wire _T_372 = _T_371 & io_lsu_pkt_m_bits_load; // @[lsu_bus_intf.scala 189:84] + wire _T_373 = ~io_is_sideeffects_m; // @[lsu_bus_intf.scala 189:111] + wire [63:0] ld_fwddata_hi = {{32'd0}, _T_331}; // @[lsu_bus_intf.scala 186:27] + wire [63:0] ld_fwddata_lo = {{32'd0}, _T_312}; // @[lsu_bus_intf.scala 185:27] + wire [63:0] _T_377 = {ld_fwddata_hi[31:0],ld_fwddata_lo[31:0]}; // @[Cat.scala 29:58] + wire [3:0] _GEN_3 = {{2'd0}, io_lsu_addr_m[1:0]}; // @[lsu_bus_intf.scala 190:83] + wire [5:0] _T_379 = 4'h8 * _GEN_3; // @[lsu_bus_intf.scala 190:83] + wire [63:0] ld_fwddata_m = _T_377 >> _T_379; // @[lsu_bus_intf.scala 190:76] + reg lsu_bus_clk_en_q; // @[lsu_bus_intf.scala 194:32] + reg ldst_dual_m; // @[lsu_bus_intf.scala 197:27] + reg is_sideeffects_r; // @[lsu_bus_intf.scala 201:33] + lsu_bus_buffer bus_buffer ( // @[lsu_bus_intf.scala 100:39] + .clock(bus_buffer_clock), + .reset(bus_buffer_reset), + .io_scan_mode(bus_buffer_io_scan_mode), + .io_tlu_busbuff_lsu_pmu_bus_trxn(bus_buffer_io_tlu_busbuff_lsu_pmu_bus_trxn), + .io_tlu_busbuff_lsu_pmu_bus_misaligned(bus_buffer_io_tlu_busbuff_lsu_pmu_bus_misaligned), + .io_tlu_busbuff_lsu_pmu_bus_error(bus_buffer_io_tlu_busbuff_lsu_pmu_bus_error), + .io_tlu_busbuff_lsu_pmu_bus_busy(bus_buffer_io_tlu_busbuff_lsu_pmu_bus_busy), + .io_tlu_busbuff_dec_tlu_external_ldfwd_disable(bus_buffer_io_tlu_busbuff_dec_tlu_external_ldfwd_disable), + .io_tlu_busbuff_dec_tlu_wb_coalescing_disable(bus_buffer_io_tlu_busbuff_dec_tlu_wb_coalescing_disable), + .io_tlu_busbuff_dec_tlu_sideeffect_posted_disable(bus_buffer_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable), + .io_tlu_busbuff_lsu_imprecise_error_load_any(bus_buffer_io_tlu_busbuff_lsu_imprecise_error_load_any), + .io_tlu_busbuff_lsu_imprecise_error_store_any(bus_buffer_io_tlu_busbuff_lsu_imprecise_error_store_any), + .io_tlu_busbuff_lsu_imprecise_error_addr_any(bus_buffer_io_tlu_busbuff_lsu_imprecise_error_addr_any), + .io_dctl_busbuff_lsu_nonblock_load_valid_m(bus_buffer_io_dctl_busbuff_lsu_nonblock_load_valid_m), + .io_dctl_busbuff_lsu_nonblock_load_tag_m(bus_buffer_io_dctl_busbuff_lsu_nonblock_load_tag_m), + .io_dctl_busbuff_lsu_nonblock_load_inv_r(bus_buffer_io_dctl_busbuff_lsu_nonblock_load_inv_r), + .io_dctl_busbuff_lsu_nonblock_load_inv_tag_r(bus_buffer_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r), + .io_dctl_busbuff_lsu_nonblock_load_data_valid(bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_valid), + .io_dctl_busbuff_lsu_nonblock_load_data_error(bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_error), + .io_dctl_busbuff_lsu_nonblock_load_data_tag(bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_tag), + .io_dctl_busbuff_lsu_nonblock_load_data(bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data), + .io_dec_tlu_force_halt(bus_buffer_io_dec_tlu_force_halt), + .io_lsu_c2_r_clk(bus_buffer_io_lsu_c2_r_clk), + .io_lsu_bus_ibuf_c1_clk(bus_buffer_io_lsu_bus_ibuf_c1_clk), + .io_lsu_bus_obuf_c1_clk(bus_buffer_io_lsu_bus_obuf_c1_clk), + .io_lsu_bus_buf_c1_clk(bus_buffer_io_lsu_bus_buf_c1_clk), + .io_lsu_free_c2_clk(bus_buffer_io_lsu_free_c2_clk), + .io_lsu_busm_clk(bus_buffer_io_lsu_busm_clk), + .io_dec_lsu_valid_raw_d(bus_buffer_io_dec_lsu_valid_raw_d), + .io_lsu_pkt_m_valid(bus_buffer_io_lsu_pkt_m_valid), + .io_lsu_pkt_m_bits_load(bus_buffer_io_lsu_pkt_m_bits_load), + .io_lsu_pkt_r_bits_by(bus_buffer_io_lsu_pkt_r_bits_by), + .io_lsu_pkt_r_bits_half(bus_buffer_io_lsu_pkt_r_bits_half), + .io_lsu_pkt_r_bits_word(bus_buffer_io_lsu_pkt_r_bits_word), + .io_lsu_pkt_r_bits_load(bus_buffer_io_lsu_pkt_r_bits_load), + .io_lsu_pkt_r_bits_store(bus_buffer_io_lsu_pkt_r_bits_store), + .io_lsu_pkt_r_bits_unsign(bus_buffer_io_lsu_pkt_r_bits_unsign), + .io_lsu_addr_m(bus_buffer_io_lsu_addr_m), + .io_end_addr_m(bus_buffer_io_end_addr_m), + .io_lsu_addr_r(bus_buffer_io_lsu_addr_r), + .io_end_addr_r(bus_buffer_io_end_addr_r), + .io_store_data_r(bus_buffer_io_store_data_r), + .io_no_word_merge_r(bus_buffer_io_no_word_merge_r), + .io_no_dword_merge_r(bus_buffer_io_no_dword_merge_r), + .io_lsu_busreq_m(bus_buffer_io_lsu_busreq_m), + .io_ld_full_hit_m(bus_buffer_io_ld_full_hit_m), + .io_flush_m_up(bus_buffer_io_flush_m_up), + .io_flush_r(bus_buffer_io_flush_r), + .io_lsu_commit_r(bus_buffer_io_lsu_commit_r), + .io_is_sideeffects_r(bus_buffer_io_is_sideeffects_r), + .io_ldst_dual_d(bus_buffer_io_ldst_dual_d), + .io_ldst_dual_m(bus_buffer_io_ldst_dual_m), + .io_ldst_dual_r(bus_buffer_io_ldst_dual_r), + .io_ldst_byteen_ext_m(bus_buffer_io_ldst_byteen_ext_m), + .io_lsu_axi_aw_ready(bus_buffer_io_lsu_axi_aw_ready), + .io_lsu_axi_aw_valid(bus_buffer_io_lsu_axi_aw_valid), + .io_lsu_axi_aw_bits_id(bus_buffer_io_lsu_axi_aw_bits_id), + .io_lsu_axi_aw_bits_addr(bus_buffer_io_lsu_axi_aw_bits_addr), + .io_lsu_axi_aw_bits_region(bus_buffer_io_lsu_axi_aw_bits_region), + .io_lsu_axi_aw_bits_size(bus_buffer_io_lsu_axi_aw_bits_size), + .io_lsu_axi_aw_bits_cache(bus_buffer_io_lsu_axi_aw_bits_cache), + .io_lsu_axi_w_ready(bus_buffer_io_lsu_axi_w_ready), + .io_lsu_axi_w_valid(bus_buffer_io_lsu_axi_w_valid), + .io_lsu_axi_w_bits_data(bus_buffer_io_lsu_axi_w_bits_data), + .io_lsu_axi_w_bits_strb(bus_buffer_io_lsu_axi_w_bits_strb), + .io_lsu_axi_b_ready(bus_buffer_io_lsu_axi_b_ready), + .io_lsu_axi_b_valid(bus_buffer_io_lsu_axi_b_valid), + .io_lsu_axi_b_bits_resp(bus_buffer_io_lsu_axi_b_bits_resp), + .io_lsu_axi_b_bits_id(bus_buffer_io_lsu_axi_b_bits_id), + .io_lsu_axi_ar_ready(bus_buffer_io_lsu_axi_ar_ready), + .io_lsu_axi_ar_valid(bus_buffer_io_lsu_axi_ar_valid), + .io_lsu_axi_ar_bits_id(bus_buffer_io_lsu_axi_ar_bits_id), + .io_lsu_axi_ar_bits_addr(bus_buffer_io_lsu_axi_ar_bits_addr), + .io_lsu_axi_ar_bits_region(bus_buffer_io_lsu_axi_ar_bits_region), + .io_lsu_axi_ar_bits_size(bus_buffer_io_lsu_axi_ar_bits_size), + .io_lsu_axi_ar_bits_cache(bus_buffer_io_lsu_axi_ar_bits_cache), + .io_lsu_axi_r_ready(bus_buffer_io_lsu_axi_r_ready), + .io_lsu_axi_r_valid(bus_buffer_io_lsu_axi_r_valid), + .io_lsu_axi_r_bits_id(bus_buffer_io_lsu_axi_r_bits_id), + .io_lsu_axi_r_bits_data(bus_buffer_io_lsu_axi_r_bits_data), + .io_lsu_axi_r_bits_resp(bus_buffer_io_lsu_axi_r_bits_resp), + .io_lsu_bus_clk_en(bus_buffer_io_lsu_bus_clk_en), + .io_lsu_bus_clk_en_q(bus_buffer_io_lsu_bus_clk_en_q), + .io_lsu_busreq_r(bus_buffer_io_lsu_busreq_r), + .io_lsu_bus_buffer_pend_any(bus_buffer_io_lsu_bus_buffer_pend_any), + .io_lsu_bus_buffer_full_any(bus_buffer_io_lsu_bus_buffer_full_any), + .io_lsu_bus_buffer_empty_any(bus_buffer_io_lsu_bus_buffer_empty_any), + .io_ld_byte_hit_buf_lo(bus_buffer_io_ld_byte_hit_buf_lo), + .io_ld_byte_hit_buf_hi(bus_buffer_io_ld_byte_hit_buf_hi), + .io_ld_fwddata_buf_lo(bus_buffer_io_ld_fwddata_buf_lo), + .io_ld_fwddata_buf_hi(bus_buffer_io_ld_fwddata_buf_hi) + ); + assign io_tlu_busbuff_lsu_pmu_bus_trxn = bus_buffer_io_tlu_busbuff_lsu_pmu_bus_trxn; // @[lsu_bus_intf.scala 103:18] + assign io_tlu_busbuff_lsu_pmu_bus_misaligned = bus_buffer_io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[lsu_bus_intf.scala 103:18] + assign io_tlu_busbuff_lsu_pmu_bus_error = bus_buffer_io_tlu_busbuff_lsu_pmu_bus_error; // @[lsu_bus_intf.scala 103:18] + assign io_tlu_busbuff_lsu_pmu_bus_busy = bus_buffer_io_tlu_busbuff_lsu_pmu_bus_busy; // @[lsu_bus_intf.scala 103:18] + assign io_tlu_busbuff_lsu_imprecise_error_load_any = bus_buffer_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[lsu_bus_intf.scala 103:18] + assign io_tlu_busbuff_lsu_imprecise_error_store_any = bus_buffer_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_intf.scala 103:18] + assign io_tlu_busbuff_lsu_imprecise_error_addr_any = bus_buffer_io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[lsu_bus_intf.scala 103:18] + assign io_axi_aw_valid = bus_buffer_io_lsu_axi_aw_valid; // @[lsu_bus_intf.scala 129:43] + assign io_axi_aw_bits_id = bus_buffer_io_lsu_axi_aw_bits_id; // @[lsu_bus_intf.scala 129:43] + assign io_axi_aw_bits_addr = bus_buffer_io_lsu_axi_aw_bits_addr; // @[lsu_bus_intf.scala 129:43] + assign io_axi_aw_bits_region = bus_buffer_io_lsu_axi_aw_bits_region; // @[lsu_bus_intf.scala 129:43] + assign io_axi_aw_bits_size = bus_buffer_io_lsu_axi_aw_bits_size; // @[lsu_bus_intf.scala 129:43] + assign io_axi_aw_bits_cache = bus_buffer_io_lsu_axi_aw_bits_cache; // @[lsu_bus_intf.scala 129:43] + assign io_axi_w_valid = bus_buffer_io_lsu_axi_w_valid; // @[lsu_bus_intf.scala 129:43] + assign io_axi_w_bits_data = bus_buffer_io_lsu_axi_w_bits_data; // @[lsu_bus_intf.scala 129:43] + assign io_axi_w_bits_strb = bus_buffer_io_lsu_axi_w_bits_strb; // @[lsu_bus_intf.scala 129:43] + assign io_axi_ar_valid = bus_buffer_io_lsu_axi_ar_valid; // @[lsu_bus_intf.scala 129:43] + assign io_axi_ar_bits_id = bus_buffer_io_lsu_axi_ar_bits_id; // @[lsu_bus_intf.scala 129:43] + assign io_axi_ar_bits_addr = bus_buffer_io_lsu_axi_ar_bits_addr; // @[lsu_bus_intf.scala 129:43] + assign io_axi_ar_bits_region = bus_buffer_io_lsu_axi_ar_bits_region; // @[lsu_bus_intf.scala 129:43] + assign io_axi_ar_bits_size = bus_buffer_io_lsu_axi_ar_bits_size; // @[lsu_bus_intf.scala 129:43] + assign io_axi_ar_bits_cache = bus_buffer_io_lsu_axi_ar_bits_cache; // @[lsu_bus_intf.scala 129:43] + assign io_lsu_busreq_r = bus_buffer_io_lsu_busreq_r; // @[lsu_bus_intf.scala 132:38] + assign io_lsu_bus_buffer_pend_any = bus_buffer_io_lsu_bus_buffer_pend_any; // @[lsu_bus_intf.scala 133:38] + assign io_lsu_bus_buffer_full_any = bus_buffer_io_lsu_bus_buffer_full_any; // @[lsu_bus_intf.scala 134:38] + assign io_lsu_bus_buffer_empty_any = bus_buffer_io_lsu_bus_buffer_empty_any; // @[lsu_bus_intf.scala 135:38] + assign io_bus_read_data_m = ld_fwddata_m[31:0]; // @[lsu_bus_intf.scala 191:27] + assign io_dctl_busbuff_lsu_nonblock_load_valid_m = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[lsu_bus_intf.scala 141:19] + assign io_dctl_busbuff_lsu_nonblock_load_tag_m = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_tag_m; // @[lsu_bus_intf.scala 141:19] + assign io_dctl_busbuff_lsu_nonblock_load_inv_r = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_inv_r; // @[lsu_bus_intf.scala 141:19] + assign io_dctl_busbuff_lsu_nonblock_load_inv_tag_r = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[lsu_bus_intf.scala 141:19] + assign io_dctl_busbuff_lsu_nonblock_load_data_valid = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_valid; // @[lsu_bus_intf.scala 141:19] + assign io_dctl_busbuff_lsu_nonblock_load_data_error = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_error; // @[lsu_bus_intf.scala 141:19] + assign io_dctl_busbuff_lsu_nonblock_load_data_tag = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_tag; // @[lsu_bus_intf.scala 141:19] + assign io_dctl_busbuff_lsu_nonblock_load_data = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data; // @[lsu_bus_intf.scala 141:19] + assign bus_buffer_clock = clock; + assign bus_buffer_reset = reset; + assign bus_buffer_io_scan_mode = io_scan_mode; // @[lsu_bus_intf.scala 102:29] + assign bus_buffer_io_tlu_busbuff_dec_tlu_external_ldfwd_disable = io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu_bus_intf.scala 103:18] + assign bus_buffer_io_tlu_busbuff_dec_tlu_wb_coalescing_disable = io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_intf.scala 103:18] + assign bus_buffer_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable = io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_intf.scala 103:18] + assign bus_buffer_io_dec_tlu_force_halt = io_dec_tlu_force_halt; // @[lsu_bus_intf.scala 105:51] + assign bus_buffer_io_lsu_c2_r_clk = io_lsu_c2_r_clk; // @[lsu_bus_intf.scala 106:51] + assign bus_buffer_io_lsu_bus_ibuf_c1_clk = io_lsu_bus_ibuf_c1_clk; // @[lsu_bus_intf.scala 107:51] + assign bus_buffer_io_lsu_bus_obuf_c1_clk = io_lsu_bus_obuf_c1_clk; // @[lsu_bus_intf.scala 108:51] + assign bus_buffer_io_lsu_bus_buf_c1_clk = io_lsu_bus_buf_c1_clk; // @[lsu_bus_intf.scala 109:51] + assign bus_buffer_io_lsu_free_c2_clk = io_lsu_free_c2_clk; // @[lsu_bus_intf.scala 110:51] + assign bus_buffer_io_lsu_busm_clk = io_lsu_busm_clk; // @[lsu_bus_intf.scala 111:51] + assign bus_buffer_io_dec_lsu_valid_raw_d = io_dec_lsu_valid_raw_d; // @[lsu_bus_intf.scala 112:51] + assign bus_buffer_io_lsu_pkt_m_valid = io_lsu_pkt_m_valid; // @[lsu_bus_intf.scala 115:27] + assign bus_buffer_io_lsu_pkt_m_bits_load = io_lsu_pkt_m_bits_load; // @[lsu_bus_intf.scala 115:27] + assign bus_buffer_io_lsu_pkt_r_bits_by = io_lsu_pkt_r_bits_by; // @[lsu_bus_intf.scala 116:27] + assign bus_buffer_io_lsu_pkt_r_bits_half = io_lsu_pkt_r_bits_half; // @[lsu_bus_intf.scala 116:27] + assign bus_buffer_io_lsu_pkt_r_bits_word = io_lsu_pkt_r_bits_word; // @[lsu_bus_intf.scala 116:27] + assign bus_buffer_io_lsu_pkt_r_bits_load = io_lsu_pkt_r_bits_load; // @[lsu_bus_intf.scala 116:27] + assign bus_buffer_io_lsu_pkt_r_bits_store = io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 116:27] + assign bus_buffer_io_lsu_pkt_r_bits_unsign = io_lsu_pkt_r_bits_unsign; // @[lsu_bus_intf.scala 116:27] + assign bus_buffer_io_lsu_addr_m = io_lsu_addr_m; // @[lsu_bus_intf.scala 119:51] + assign bus_buffer_io_end_addr_m = io_end_addr_m; // @[lsu_bus_intf.scala 120:51] + assign bus_buffer_io_lsu_addr_r = io_lsu_addr_r; // @[lsu_bus_intf.scala 121:51] + assign bus_buffer_io_end_addr_r = io_end_addr_r; // @[lsu_bus_intf.scala 122:51] + assign bus_buffer_io_store_data_r = io_store_data_r; // @[lsu_bus_intf.scala 123:51] + assign bus_buffer_io_no_word_merge_r = _T_22 & _T_24; // @[lsu_bus_intf.scala 142:51] + assign bus_buffer_io_no_dword_merge_r = _T_22 & _T_30; // @[lsu_bus_intf.scala 143:51] + assign bus_buffer_io_lsu_busreq_m = io_lsu_busreq_m; // @[lsu_bus_intf.scala 125:51] + assign bus_buffer_io_ld_full_hit_m = _T_372 & _T_373; // @[lsu_bus_intf.scala 149:51] + assign bus_buffer_io_flush_m_up = io_flush_m_up; // @[lsu_bus_intf.scala 126:51] + assign bus_buffer_io_flush_r = io_flush_r; // @[lsu_bus_intf.scala 127:51] + assign bus_buffer_io_lsu_commit_r = io_lsu_commit_r; // @[lsu_bus_intf.scala 128:51] + assign bus_buffer_io_is_sideeffects_r = is_sideeffects_r; // @[lsu_bus_intf.scala 144:51] + assign bus_buffer_io_ldst_dual_d = io_lsu_addr_d[2] != io_end_addr_d[2]; // @[lsu_bus_intf.scala 145:51] + assign bus_buffer_io_ldst_dual_m = ldst_dual_m; // @[lsu_bus_intf.scala 146:51] + assign bus_buffer_io_ldst_dual_r = ldst_dual_r; // @[lsu_bus_intf.scala 147:51] + assign bus_buffer_io_ldst_byteen_ext_m = {{1'd0}, _T_34}; // @[lsu_bus_intf.scala 148:51] + assign bus_buffer_io_lsu_axi_aw_ready = io_axi_aw_ready; // @[lsu_bus_intf.scala 129:43] + assign bus_buffer_io_lsu_axi_w_ready = io_axi_w_ready; // @[lsu_bus_intf.scala 129:43] + assign bus_buffer_io_lsu_axi_b_valid = io_axi_b_valid; // @[lsu_bus_intf.scala 129:43] + assign bus_buffer_io_lsu_axi_b_bits_resp = io_axi_b_bits_resp; // @[lsu_bus_intf.scala 129:43] + assign bus_buffer_io_lsu_axi_b_bits_id = io_axi_b_bits_id; // @[lsu_bus_intf.scala 129:43] + assign bus_buffer_io_lsu_axi_ar_ready = io_axi_ar_ready; // @[lsu_bus_intf.scala 129:43] + assign bus_buffer_io_lsu_axi_r_valid = io_axi_r_valid; // @[lsu_bus_intf.scala 129:43] + assign bus_buffer_io_lsu_axi_r_bits_id = io_axi_r_bits_id; // @[lsu_bus_intf.scala 129:43] + assign bus_buffer_io_lsu_axi_r_bits_data = io_axi_r_bits_data; // @[lsu_bus_intf.scala 129:43] + assign bus_buffer_io_lsu_axi_r_bits_resp = io_axi_r_bits_resp; // @[lsu_bus_intf.scala 129:43] + assign bus_buffer_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[lsu_bus_intf.scala 130:51] + assign bus_buffer_io_lsu_bus_clk_en_q = lsu_bus_clk_en_q; // @[lsu_bus_intf.scala 150:51] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + ldst_dual_r = _RAND_0[0:0]; + _RAND_1 = {1{`RANDOM}}; + ldst_byteen_r = _RAND_1[3:0]; + _RAND_2 = {1{`RANDOM}}; + lsu_bus_clk_en_q = _RAND_2[0:0]; + _RAND_3 = {1{`RANDOM}}; + ldst_dual_m = _RAND_3[0:0]; + _RAND_4 = {1{`RANDOM}}; + is_sideeffects_r = _RAND_4[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + ldst_dual_r = 1'h0; + end + if (reset) begin + ldst_byteen_r = 4'h0; + end + if (reset) begin + lsu_bus_clk_en_q = 1'h0; + end + if (reset) begin + ldst_dual_m = 1'h0; + end + if (reset) begin + is_sideeffects_r = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + ldst_dual_r <= 1'h0; + end else begin + ldst_dual_r <= ldst_dual_m; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + ldst_byteen_r <= 4'h0; + end else begin + ldst_byteen_r <= _T_6 | _T_5; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + lsu_bus_clk_en_q <= 1'h0; + end else begin + lsu_bus_clk_en_q <= io_lsu_bus_clk_en; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + ldst_dual_m <= 1'h0; + end else begin + ldst_dual_m <= io_lsu_addr_d[2] != io_end_addr_d[2]; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + is_sideeffects_r <= 1'h0; + end else begin + is_sideeffects_r <= io_is_sideeffects_m; + end + end +endmodule +module lsu( + input clock, + input reset, + input io_clk_override, + input io_lsu_dma_dma_lsc_ctl_dma_dccm_req, + input [31:0] io_lsu_dma_dma_lsc_ctl_dma_mem_addr, + input [2:0] io_lsu_dma_dma_lsc_ctl_dma_mem_sz, + input io_lsu_dma_dma_lsc_ctl_dma_mem_write, + input [63:0] io_lsu_dma_dma_lsc_ctl_dma_mem_wdata, + input [31:0] io_lsu_dma_dma_dccm_ctl_dma_mem_addr, + input [63:0] io_lsu_dma_dma_dccm_ctl_dma_mem_wdata, + output io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid, + output io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error, + output [2:0] io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag, + output [63:0] io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata, + output io_lsu_dma_dccm_ready, + input [2:0] io_lsu_dma_dma_mem_tag, + output io_lsu_pic_picm_wren, + output io_lsu_pic_picm_rden, + output io_lsu_pic_picm_mken, + output [31:0] io_lsu_pic_picm_rdaddr, + output [31:0] io_lsu_pic_picm_wraddr, + output [31:0] io_lsu_pic_picm_wr_data, + input [31:0] io_lsu_pic_picm_rd_data, + input [31:0] io_lsu_exu_exu_lsu_rs1_d, + input [31:0] io_lsu_exu_exu_lsu_rs2_d, + output io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn, + output io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned, + output io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error, + output io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy, + input io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable, + input io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable, + input io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable, + output io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any, + output io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any, + output [31:0] io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any, + output io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m, + output [1:0] io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m, + output io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r, + output [1:0] io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r, + output io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid, + output io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error, + output [1:0] io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag, + output [31:0] io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data, + output io_dccm_wren, + output io_dccm_rden, + output [15:0] io_dccm_wr_addr_lo, + output [15:0] io_dccm_wr_addr_hi, + output [15:0] io_dccm_rd_addr_lo, + output [15:0] io_dccm_rd_addr_hi, + output [38:0] io_dccm_wr_data_lo, + output [38:0] io_dccm_wr_data_hi, + input [38:0] io_dccm_rd_data_lo, + input [38:0] io_dccm_rd_data_hi, + output io_lsu_tlu_lsu_pmu_load_external_m, + output io_lsu_tlu_lsu_pmu_store_external_m, + input io_axi_aw_ready, + output io_axi_aw_valid, + output [2:0] io_axi_aw_bits_id, + output [31:0] io_axi_aw_bits_addr, + output [3:0] io_axi_aw_bits_region, + output [7:0] io_axi_aw_bits_len, + output [2:0] io_axi_aw_bits_size, + output [1:0] io_axi_aw_bits_burst, + output io_axi_aw_bits_lock, + output [3:0] io_axi_aw_bits_cache, + output [2:0] io_axi_aw_bits_prot, + output [3:0] io_axi_aw_bits_qos, + input io_axi_w_ready, + output io_axi_w_valid, + output [63:0] io_axi_w_bits_data, + output [7:0] io_axi_w_bits_strb, + output io_axi_w_bits_last, + output io_axi_b_ready, + input io_axi_b_valid, + input [1:0] io_axi_b_bits_resp, + input [2:0] io_axi_b_bits_id, + input io_axi_ar_ready, + output io_axi_ar_valid, + output [2:0] io_axi_ar_bits_id, + output [31:0] io_axi_ar_bits_addr, + output [3:0] io_axi_ar_bits_region, + output [7:0] io_axi_ar_bits_len, + output [2:0] io_axi_ar_bits_size, + output [1:0] io_axi_ar_bits_burst, + output io_axi_ar_bits_lock, + output [3:0] io_axi_ar_bits_cache, + output [2:0] io_axi_ar_bits_prot, + output [3:0] io_axi_ar_bits_qos, + output io_axi_r_ready, + input io_axi_r_valid, + input [2:0] io_axi_r_bits_id, + input [63:0] io_axi_r_bits_data, + input [1:0] io_axi_r_bits_resp, + input io_axi_r_bits_last, + input io_dec_tlu_flush_lower_r, + input io_dec_tlu_i0_kill_writeb_r, + input io_dec_tlu_force_halt, + input io_dec_tlu_core_ecc_disable, + input [11:0] io_dec_lsu_offset_d, + input io_lsu_p_valid, + input io_lsu_p_bits_fast_int, + input io_lsu_p_bits_by, + input io_lsu_p_bits_half, + input io_lsu_p_bits_word, + input io_lsu_p_bits_dword, + input io_lsu_p_bits_load, + input io_lsu_p_bits_store, + input io_lsu_p_bits_unsign, + input io_lsu_p_bits_dma, + input io_lsu_p_bits_store_data_bypass_d, + input io_lsu_p_bits_load_ldst_bypass_d, + input io_lsu_p_bits_store_data_bypass_m, + input io_trigger_pkt_any_0_select, + input io_trigger_pkt_any_0_match_pkt, + input io_trigger_pkt_any_0_store, + input io_trigger_pkt_any_0_load, + input io_trigger_pkt_any_0_execute, + input io_trigger_pkt_any_0_m, + input [31:0] io_trigger_pkt_any_0_tdata2, + input io_trigger_pkt_any_1_select, + input io_trigger_pkt_any_1_match_pkt, + input io_trigger_pkt_any_1_store, + input io_trigger_pkt_any_1_load, + input io_trigger_pkt_any_1_execute, + input io_trigger_pkt_any_1_m, + input [31:0] io_trigger_pkt_any_1_tdata2, + input io_trigger_pkt_any_2_select, + input io_trigger_pkt_any_2_match_pkt, + input io_trigger_pkt_any_2_store, + input io_trigger_pkt_any_2_load, + input io_trigger_pkt_any_2_execute, + input io_trigger_pkt_any_2_m, + input [31:0] io_trigger_pkt_any_2_tdata2, + input io_trigger_pkt_any_3_select, + input io_trigger_pkt_any_3_match_pkt, + input io_trigger_pkt_any_3_store, + input io_trigger_pkt_any_3_load, + input io_trigger_pkt_any_3_execute, + input io_trigger_pkt_any_3_m, + input [31:0] io_trigger_pkt_any_3_tdata2, + input io_dec_lsu_valid_raw_d, + input [31:0] io_dec_tlu_mrac_ff, + output [31:0] io_lsu_result_m, + output [31:0] io_lsu_result_corr_r, + output io_lsu_load_stall_any, + output io_lsu_store_stall_any, + output io_lsu_fastint_stall_any, + output io_lsu_idle_any, + output [30:0] io_lsu_fir_addr, + output [1:0] io_lsu_fir_error, + output io_lsu_single_ecc_error_incr, + output io_lsu_error_pkt_r_valid, + output io_lsu_error_pkt_r_bits_single_ecc_error, + output io_lsu_error_pkt_r_bits_inst_type, + output io_lsu_error_pkt_r_bits_exc_type, + output [3:0] io_lsu_error_pkt_r_bits_mscause, + output [31:0] io_lsu_error_pkt_r_bits_addr, + output io_lsu_pmu_misaligned_m, + output [3:0] io_lsu_trigger_match_m, + input io_lsu_bus_clk_en, + input io_scan_mode, + input io_free_clk +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; +`endif // RANDOMIZE_REG_INIT + wire lsu_lsc_ctl_reset; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_c1_m_clk; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_c1_r_clk; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_c2_m_clk; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_c2_r_clk; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_store_c1_m_clk; // @[lsu.scala 60:30] + wire [31:0] lsu_lsc_ctl_io_lsu_ld_data_corr_r; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_single_ecc_error_r; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_double_ecc_error_r; // @[lsu.scala 60:30] + wire [31:0] lsu_lsc_ctl_io_lsu_ld_data_m; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_single_ecc_error_m; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_double_ecc_error_m; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_flush_m_up; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_flush_r; // @[lsu.scala 60:30] + wire [31:0] lsu_lsc_ctl_io_lsu_exu_exu_lsu_rs1_d; // @[lsu.scala 60:30] + wire [31:0] lsu_lsc_ctl_io_lsu_exu_exu_lsu_rs2_d; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_p_valid; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_p_bits_fast_int; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_p_bits_by; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_p_bits_half; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_p_bits_word; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_p_bits_dword; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_p_bits_load; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_p_bits_store; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_p_bits_unsign; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_p_bits_dma; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_p_bits_store_data_bypass_d; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_p_bits_load_ldst_bypass_d; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_p_bits_store_data_bypass_m; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_dec_lsu_valid_raw_d; // @[lsu.scala 60:30] + wire [11:0] lsu_lsc_ctl_io_dec_lsu_offset_d; // @[lsu.scala 60:30] + wire [31:0] lsu_lsc_ctl_io_picm_mask_data_m; // @[lsu.scala 60:30] + wire [31:0] lsu_lsc_ctl_io_bus_read_data_m; // @[lsu.scala 60:30] + wire [31:0] lsu_lsc_ctl_io_lsu_result_m; // @[lsu.scala 60:30] + wire [31:0] lsu_lsc_ctl_io_lsu_result_corr_r; // @[lsu.scala 60:30] + wire [31:0] lsu_lsc_ctl_io_lsu_addr_d; // @[lsu.scala 60:30] + wire [31:0] lsu_lsc_ctl_io_lsu_addr_m; // @[lsu.scala 60:30] + wire [31:0] lsu_lsc_ctl_io_lsu_addr_r; // @[lsu.scala 60:30] + wire [31:0] lsu_lsc_ctl_io_end_addr_d; // @[lsu.scala 60:30] + wire [31:0] lsu_lsc_ctl_io_end_addr_m; // @[lsu.scala 60:30] + wire [31:0] lsu_lsc_ctl_io_end_addr_r; // @[lsu.scala 60:30] + wire [31:0] lsu_lsc_ctl_io_store_data_m; // @[lsu.scala 60:30] + wire [31:0] lsu_lsc_ctl_io_dec_tlu_mrac_ff; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_exc_m; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_is_sideeffects_m; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_commit_r; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_single_ecc_error_incr; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_error_pkt_r_valid; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_error_pkt_r_bits_single_ecc_error; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_error_pkt_r_bits_inst_type; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_error_pkt_r_bits_exc_type; // @[lsu.scala 60:30] + wire [3:0] lsu_lsc_ctl_io_lsu_error_pkt_r_bits_mscause; // @[lsu.scala 60:30] + wire [31:0] lsu_lsc_ctl_io_lsu_error_pkt_r_bits_addr; // @[lsu.scala 60:30] + wire [30:0] lsu_lsc_ctl_io_lsu_fir_addr; // @[lsu.scala 60:30] + wire [1:0] lsu_lsc_ctl_io_lsu_fir_error; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_addr_in_dccm_d; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_addr_in_dccm_m; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_addr_in_dccm_r; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_addr_in_pic_d; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_addr_in_pic_m; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_addr_in_pic_r; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_addr_external_m; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_dma_lsc_ctl_dma_dccm_req; // @[lsu.scala 60:30] + wire [31:0] lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_addr; // @[lsu.scala 60:30] + wire [2:0] lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_sz; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_write; // @[lsu.scala 60:30] + wire [63:0] lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_wdata; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_pkt_d_valid; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_pkt_d_bits_fast_int; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_pkt_d_bits_by; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_pkt_d_bits_half; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_pkt_d_bits_word; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_pkt_d_bits_dword; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_pkt_d_bits_load; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_pkt_d_bits_store; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_pkt_d_bits_unsign; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_pkt_d_bits_dma; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_pkt_d_bits_store_data_bypass_d; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_pkt_d_bits_load_ldst_bypass_d; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_pkt_d_bits_store_data_bypass_m; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_pkt_m_bits_fast_int; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_pkt_m_bits_by; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_pkt_m_bits_half; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_pkt_m_bits_word; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_pkt_m_bits_dword; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_pkt_m_bits_load; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_pkt_m_bits_unsign; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_pkt_m_bits_dma; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_pkt_m_bits_store_data_bypass_m; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_pkt_r_valid; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_pkt_r_bits_by; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_pkt_r_bits_half; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_pkt_r_bits_word; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_pkt_r_bits_dword; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_pkt_r_bits_load; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_pkt_r_bits_store; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_pkt_r_bits_unsign; // @[lsu.scala 60:30] + wire lsu_lsc_ctl_io_lsu_pkt_r_bits_dma; // @[lsu.scala 60:30] + wire dccm_ctl_clock; // @[lsu.scala 63:30] + wire dccm_ctl_reset; // @[lsu.scala 63:30] + wire dccm_ctl_io_lsu_c2_m_clk; // @[lsu.scala 63:30] + wire dccm_ctl_io_lsu_c2_r_clk; // @[lsu.scala 63:30] + wire dccm_ctl_io_lsu_free_c2_clk; // @[lsu.scala 63:30] + wire dccm_ctl_io_lsu_store_c1_r_clk; // @[lsu.scala 63:30] + wire dccm_ctl_io_lsu_pkt_d_valid; // @[lsu.scala 63:30] + wire dccm_ctl_io_lsu_pkt_d_bits_word; // @[lsu.scala 63:30] + wire dccm_ctl_io_lsu_pkt_d_bits_dword; // @[lsu.scala 63:30] + wire dccm_ctl_io_lsu_pkt_d_bits_load; // @[lsu.scala 63:30] + wire dccm_ctl_io_lsu_pkt_d_bits_store; // @[lsu.scala 63:30] + wire dccm_ctl_io_lsu_pkt_d_bits_dma; // @[lsu.scala 63:30] + wire dccm_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 63:30] + wire dccm_ctl_io_lsu_pkt_m_bits_by; // @[lsu.scala 63:30] + wire dccm_ctl_io_lsu_pkt_m_bits_half; // @[lsu.scala 63:30] + wire dccm_ctl_io_lsu_pkt_m_bits_word; // @[lsu.scala 63:30] + wire dccm_ctl_io_lsu_pkt_m_bits_load; // @[lsu.scala 63:30] + wire dccm_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 63:30] + wire dccm_ctl_io_lsu_pkt_m_bits_dma; // @[lsu.scala 63:30] + wire dccm_ctl_io_lsu_pkt_r_valid; // @[lsu.scala 63:30] + wire dccm_ctl_io_lsu_pkt_r_bits_by; // @[lsu.scala 63:30] + wire dccm_ctl_io_lsu_pkt_r_bits_half; // @[lsu.scala 63:30] + wire dccm_ctl_io_lsu_pkt_r_bits_word; // @[lsu.scala 63:30] + wire dccm_ctl_io_lsu_pkt_r_bits_load; // @[lsu.scala 63:30] + wire dccm_ctl_io_lsu_pkt_r_bits_store; // @[lsu.scala 63:30] + wire dccm_ctl_io_lsu_pkt_r_bits_dma; // @[lsu.scala 63:30] + wire dccm_ctl_io_addr_in_dccm_d; // @[lsu.scala 63:30] + wire dccm_ctl_io_addr_in_dccm_m; // @[lsu.scala 63:30] + wire dccm_ctl_io_addr_in_dccm_r; // @[lsu.scala 63:30] + wire dccm_ctl_io_addr_in_pic_d; // @[lsu.scala 63:30] + wire dccm_ctl_io_addr_in_pic_m; // @[lsu.scala 63:30] + wire dccm_ctl_io_addr_in_pic_r; // @[lsu.scala 63:30] + wire dccm_ctl_io_lsu_raw_fwd_lo_r; // @[lsu.scala 63:30] + wire dccm_ctl_io_lsu_raw_fwd_hi_r; // @[lsu.scala 63:30] + wire dccm_ctl_io_lsu_commit_r; // @[lsu.scala 63:30] + wire [31:0] dccm_ctl_io_lsu_addr_d; // @[lsu.scala 63:30] + wire [15:0] dccm_ctl_io_lsu_addr_m; // @[lsu.scala 63:30] + wire [31:0] dccm_ctl_io_lsu_addr_r; // @[lsu.scala 63:30] + wire [15:0] dccm_ctl_io_end_addr_d; // @[lsu.scala 63:30] + wire [15:0] dccm_ctl_io_end_addr_m; // @[lsu.scala 63:30] + wire [15:0] dccm_ctl_io_end_addr_r; // @[lsu.scala 63:30] + wire dccm_ctl_io_stbuf_reqvld_any; // @[lsu.scala 63:30] + wire [15:0] dccm_ctl_io_stbuf_addr_any; // @[lsu.scala 63:30] + wire [31:0] dccm_ctl_io_stbuf_data_any; // @[lsu.scala 63:30] + wire [6:0] dccm_ctl_io_stbuf_ecc_any; // @[lsu.scala 63:30] + wire [31:0] dccm_ctl_io_stbuf_fwddata_hi_m; // @[lsu.scala 63:30] + wire [31:0] dccm_ctl_io_stbuf_fwddata_lo_m; // @[lsu.scala 63:30] + wire [3:0] dccm_ctl_io_stbuf_fwdbyteen_lo_m; // @[lsu.scala 63:30] + wire [3:0] dccm_ctl_io_stbuf_fwdbyteen_hi_m; // @[lsu.scala 63:30] + wire [31:0] dccm_ctl_io_lsu_ld_data_corr_r; // @[lsu.scala 63:30] + wire dccm_ctl_io_lsu_double_ecc_error_r; // @[lsu.scala 63:30] + wire dccm_ctl_io_single_ecc_error_hi_r; // @[lsu.scala 63:30] + wire dccm_ctl_io_single_ecc_error_lo_r; // @[lsu.scala 63:30] + wire [31:0] dccm_ctl_io_sec_data_hi_r_ff; // @[lsu.scala 63:30] + wire [31:0] dccm_ctl_io_sec_data_lo_r_ff; // @[lsu.scala 63:30] + wire [6:0] dccm_ctl_io_sec_data_ecc_hi_r_ff; // @[lsu.scala 63:30] + wire [6:0] dccm_ctl_io_sec_data_ecc_lo_r_ff; // @[lsu.scala 63:30] + wire [31:0] dccm_ctl_io_dccm_rdata_hi_m; // @[lsu.scala 63:30] + wire [31:0] dccm_ctl_io_dccm_rdata_lo_m; // @[lsu.scala 63:30] + wire [6:0] dccm_ctl_io_dccm_data_ecc_hi_m; // @[lsu.scala 63:30] + wire [6:0] dccm_ctl_io_dccm_data_ecc_lo_m; // @[lsu.scala 63:30] + wire [31:0] dccm_ctl_io_lsu_ld_data_m; // @[lsu.scala 63:30] + wire dccm_ctl_io_lsu_double_ecc_error_m; // @[lsu.scala 63:30] + wire [31:0] dccm_ctl_io_sec_data_hi_m; // @[lsu.scala 63:30] + wire [31:0] dccm_ctl_io_sec_data_lo_m; // @[lsu.scala 63:30] + wire [31:0] dccm_ctl_io_store_data_m; // @[lsu.scala 63:30] + wire dccm_ctl_io_dma_dccm_wen; // @[lsu.scala 63:30] + wire dccm_ctl_io_dma_pic_wen; // @[lsu.scala 63:30] + wire [2:0] dccm_ctl_io_dma_mem_tag_m; // @[lsu.scala 63:30] + wire [31:0] dccm_ctl_io_dma_dccm_wdata_lo; // @[lsu.scala 63:30] + wire [31:0] dccm_ctl_io_dma_dccm_wdata_hi; // @[lsu.scala 63:30] + wire [6:0] dccm_ctl_io_dma_dccm_wdata_ecc_hi; // @[lsu.scala 63:30] + wire [6:0] dccm_ctl_io_dma_dccm_wdata_ecc_lo; // @[lsu.scala 63:30] + wire [31:0] dccm_ctl_io_store_data_hi_r; // @[lsu.scala 63:30] + wire [31:0] dccm_ctl_io_store_data_lo_r; // @[lsu.scala 63:30] + wire [31:0] dccm_ctl_io_store_datafn_hi_r; // @[lsu.scala 63:30] + wire [31:0] dccm_ctl_io_store_datafn_lo_r; // @[lsu.scala 63:30] + wire [31:0] dccm_ctl_io_store_data_r; // @[lsu.scala 63:30] + wire dccm_ctl_io_ld_single_ecc_error_r; // @[lsu.scala 63:30] + wire dccm_ctl_io_ld_single_ecc_error_r_ff; // @[lsu.scala 63:30] + wire [31:0] dccm_ctl_io_picm_mask_data_m; // @[lsu.scala 63:30] + wire dccm_ctl_io_lsu_stbuf_commit_any; // @[lsu.scala 63:30] + wire dccm_ctl_io_lsu_dccm_rden_m; // @[lsu.scala 63:30] + wire [31:0] dccm_ctl_io_dma_dccm_ctl_dma_mem_addr; // @[lsu.scala 63:30] + wire [63:0] dccm_ctl_io_dma_dccm_ctl_dma_mem_wdata; // @[lsu.scala 63:30] + wire dccm_ctl_io_dma_dccm_ctl_dccm_dma_rvalid; // @[lsu.scala 63:30] + wire dccm_ctl_io_dma_dccm_ctl_dccm_dma_ecc_error; // @[lsu.scala 63:30] + wire [2:0] dccm_ctl_io_dma_dccm_ctl_dccm_dma_rtag; // @[lsu.scala 63:30] + wire [63:0] dccm_ctl_io_dma_dccm_ctl_dccm_dma_rdata; // @[lsu.scala 63:30] + wire dccm_ctl_io_dccm_wren; // @[lsu.scala 63:30] + wire dccm_ctl_io_dccm_rden; // @[lsu.scala 63:30] + wire [15:0] dccm_ctl_io_dccm_wr_addr_lo; // @[lsu.scala 63:30] + wire [15:0] dccm_ctl_io_dccm_wr_addr_hi; // @[lsu.scala 63:30] + wire [15:0] dccm_ctl_io_dccm_rd_addr_lo; // @[lsu.scala 63:30] + wire [15:0] dccm_ctl_io_dccm_rd_addr_hi; // @[lsu.scala 63:30] + wire [38:0] dccm_ctl_io_dccm_wr_data_lo; // @[lsu.scala 63:30] + wire [38:0] dccm_ctl_io_dccm_wr_data_hi; // @[lsu.scala 63:30] + wire [38:0] dccm_ctl_io_dccm_rd_data_lo; // @[lsu.scala 63:30] + wire [38:0] dccm_ctl_io_dccm_rd_data_hi; // @[lsu.scala 63:30] + wire dccm_ctl_io_lsu_pic_picm_wren; // @[lsu.scala 63:30] + wire dccm_ctl_io_lsu_pic_picm_rden; // @[lsu.scala 63:30] + wire dccm_ctl_io_lsu_pic_picm_mken; // @[lsu.scala 63:30] + wire [31:0] dccm_ctl_io_lsu_pic_picm_rdaddr; // @[lsu.scala 63:30] + wire [31:0] dccm_ctl_io_lsu_pic_picm_wraddr; // @[lsu.scala 63:30] + wire [31:0] dccm_ctl_io_lsu_pic_picm_wr_data; // @[lsu.scala 63:30] + wire [31:0] dccm_ctl_io_lsu_pic_picm_rd_data; // @[lsu.scala 63:30] + wire dccm_ctl_io_scan_mode; // @[lsu.scala 63:30] + wire stbuf_clock; // @[lsu.scala 64:30] + wire stbuf_reset; // @[lsu.scala 64:30] + wire stbuf_io_lsu_c1_m_clk; // @[lsu.scala 64:30] + wire stbuf_io_lsu_c1_r_clk; // @[lsu.scala 64:30] + wire stbuf_io_lsu_stbuf_c1_clk; // @[lsu.scala 64:30] + wire stbuf_io_lsu_free_c2_clk; // @[lsu.scala 64:30] + wire stbuf_io_lsu_pkt_m_valid; // @[lsu.scala 64:30] + wire stbuf_io_lsu_pkt_m_bits_store; // @[lsu.scala 64:30] + wire stbuf_io_lsu_pkt_m_bits_dma; // @[lsu.scala 64:30] + wire stbuf_io_lsu_pkt_r_valid; // @[lsu.scala 64:30] + wire stbuf_io_lsu_pkt_r_bits_by; // @[lsu.scala 64:30] + wire stbuf_io_lsu_pkt_r_bits_half; // @[lsu.scala 64:30] + wire stbuf_io_lsu_pkt_r_bits_word; // @[lsu.scala 64:30] + wire stbuf_io_lsu_pkt_r_bits_dword; // @[lsu.scala 64:30] + wire stbuf_io_lsu_pkt_r_bits_store; // @[lsu.scala 64:30] + wire stbuf_io_lsu_pkt_r_bits_dma; // @[lsu.scala 64:30] + wire stbuf_io_store_stbuf_reqvld_r; // @[lsu.scala 64:30] + wire stbuf_io_lsu_commit_r; // @[lsu.scala 64:30] + wire stbuf_io_dec_lsu_valid_raw_d; // @[lsu.scala 64:30] + wire [31:0] stbuf_io_store_data_hi_r; // @[lsu.scala 64:30] + wire [31:0] stbuf_io_store_data_lo_r; // @[lsu.scala 64:30] + wire [31:0] stbuf_io_store_datafn_hi_r; // @[lsu.scala 64:30] + wire [31:0] stbuf_io_store_datafn_lo_r; // @[lsu.scala 64:30] + wire stbuf_io_lsu_stbuf_commit_any; // @[lsu.scala 64:30] + wire [15:0] stbuf_io_lsu_addr_d; // @[lsu.scala 64:30] + wire [31:0] stbuf_io_lsu_addr_m; // @[lsu.scala 64:30] + wire [31:0] stbuf_io_lsu_addr_r; // @[lsu.scala 64:30] + wire [15:0] stbuf_io_end_addr_d; // @[lsu.scala 64:30] + wire [31:0] stbuf_io_end_addr_m; // @[lsu.scala 64:30] + wire [31:0] stbuf_io_end_addr_r; // @[lsu.scala 64:30] + wire stbuf_io_addr_in_dccm_m; // @[lsu.scala 64:30] + wire stbuf_io_addr_in_dccm_r; // @[lsu.scala 64:30] + wire stbuf_io_scan_mode; // @[lsu.scala 64:30] + wire stbuf_io_stbuf_reqvld_any; // @[lsu.scala 64:30] + wire stbuf_io_stbuf_reqvld_flushed_any; // @[lsu.scala 64:30] + wire [15:0] stbuf_io_stbuf_addr_any; // @[lsu.scala 64:30] + wire [31:0] stbuf_io_stbuf_data_any; // @[lsu.scala 64:30] + wire stbuf_io_lsu_stbuf_full_any; // @[lsu.scala 64:30] + wire stbuf_io_lsu_stbuf_empty_any; // @[lsu.scala 64:30] + wire stbuf_io_ldst_stbuf_reqvld_r; // @[lsu.scala 64:30] + wire [31:0] stbuf_io_stbuf_fwddata_hi_m; // @[lsu.scala 64:30] + wire [31:0] stbuf_io_stbuf_fwddata_lo_m; // @[lsu.scala 64:30] + wire [3:0] stbuf_io_stbuf_fwdbyteen_hi_m; // @[lsu.scala 64:30] + wire [3:0] stbuf_io_stbuf_fwdbyteen_lo_m; // @[lsu.scala 64:30] + wire ecc_clock; // @[lsu.scala 65:30] + wire ecc_reset; // @[lsu.scala 65:30] + wire ecc_io_lsu_c2_r_clk; // @[lsu.scala 65:30] + wire ecc_io_lsu_pkt_m_valid; // @[lsu.scala 65:30] + wire ecc_io_lsu_pkt_m_bits_load; // @[lsu.scala 65:30] + wire ecc_io_lsu_pkt_m_bits_store; // @[lsu.scala 65:30] + wire ecc_io_lsu_pkt_m_bits_dma; // @[lsu.scala 65:30] + wire [31:0] ecc_io_stbuf_data_any; // @[lsu.scala 65:30] + wire ecc_io_dec_tlu_core_ecc_disable; // @[lsu.scala 65:30] + wire [15:0] ecc_io_lsu_addr_m; // @[lsu.scala 65:30] + wire [15:0] ecc_io_end_addr_m; // @[lsu.scala 65:30] + wire [31:0] ecc_io_dccm_rdata_hi_m; // @[lsu.scala 65:30] + wire [31:0] ecc_io_dccm_rdata_lo_m; // @[lsu.scala 65:30] + wire [6:0] ecc_io_dccm_data_ecc_hi_m; // @[lsu.scala 65:30] + wire [6:0] ecc_io_dccm_data_ecc_lo_m; // @[lsu.scala 65:30] + wire ecc_io_ld_single_ecc_error_r; // @[lsu.scala 65:30] + wire ecc_io_ld_single_ecc_error_r_ff; // @[lsu.scala 65:30] + wire ecc_io_lsu_dccm_rden_m; // @[lsu.scala 65:30] + wire ecc_io_addr_in_dccm_m; // @[lsu.scala 65:30] + wire ecc_io_dma_dccm_wen; // @[lsu.scala 65:30] + wire [31:0] ecc_io_dma_dccm_wdata_lo; // @[lsu.scala 65:30] + wire [31:0] ecc_io_dma_dccm_wdata_hi; // @[lsu.scala 65:30] + wire ecc_io_scan_mode; // @[lsu.scala 65:30] + wire [31:0] ecc_io_sec_data_hi_r; // @[lsu.scala 65:30] + wire [31:0] ecc_io_sec_data_lo_r; // @[lsu.scala 65:30] + wire [31:0] ecc_io_sec_data_hi_m; // @[lsu.scala 65:30] + wire [31:0] ecc_io_sec_data_lo_m; // @[lsu.scala 65:30] + wire [31:0] ecc_io_sec_data_hi_r_ff; // @[lsu.scala 65:30] + wire [31:0] ecc_io_sec_data_lo_r_ff; // @[lsu.scala 65:30] + wire [6:0] ecc_io_dma_dccm_wdata_ecc_hi; // @[lsu.scala 65:30] + wire [6:0] ecc_io_dma_dccm_wdata_ecc_lo; // @[lsu.scala 65:30] + wire [6:0] ecc_io_stbuf_ecc_any; // @[lsu.scala 65:30] + wire [6:0] ecc_io_sec_data_ecc_hi_r_ff; // @[lsu.scala 65:30] + wire [6:0] ecc_io_sec_data_ecc_lo_r_ff; // @[lsu.scala 65:30] + wire ecc_io_single_ecc_error_hi_r; // @[lsu.scala 65:30] + wire ecc_io_single_ecc_error_lo_r; // @[lsu.scala 65:30] + wire ecc_io_lsu_single_ecc_error_r; // @[lsu.scala 65:30] + wire ecc_io_lsu_double_ecc_error_r; // @[lsu.scala 65:30] + wire ecc_io_lsu_single_ecc_error_m; // @[lsu.scala 65:30] + wire ecc_io_lsu_double_ecc_error_m; // @[lsu.scala 65:30] + wire trigger_io_trigger_pkt_any_0_select; // @[lsu.scala 66:30] + wire trigger_io_trigger_pkt_any_0_match_pkt; // @[lsu.scala 66:30] + wire trigger_io_trigger_pkt_any_0_store; // @[lsu.scala 66:30] + wire trigger_io_trigger_pkt_any_0_load; // @[lsu.scala 66:30] + wire [31:0] trigger_io_trigger_pkt_any_0_tdata2; // @[lsu.scala 66:30] + wire trigger_io_trigger_pkt_any_1_select; // @[lsu.scala 66:30] + wire trigger_io_trigger_pkt_any_1_match_pkt; // @[lsu.scala 66:30] + wire trigger_io_trigger_pkt_any_1_store; // @[lsu.scala 66:30] + wire trigger_io_trigger_pkt_any_1_load; // @[lsu.scala 66:30] + wire [31:0] trigger_io_trigger_pkt_any_1_tdata2; // @[lsu.scala 66:30] + wire trigger_io_trigger_pkt_any_2_select; // @[lsu.scala 66:30] + wire trigger_io_trigger_pkt_any_2_match_pkt; // @[lsu.scala 66:30] + wire trigger_io_trigger_pkt_any_2_store; // @[lsu.scala 66:30] + wire trigger_io_trigger_pkt_any_2_load; // @[lsu.scala 66:30] + wire [31:0] trigger_io_trigger_pkt_any_2_tdata2; // @[lsu.scala 66:30] + wire trigger_io_trigger_pkt_any_3_select; // @[lsu.scala 66:30] + wire trigger_io_trigger_pkt_any_3_match_pkt; // @[lsu.scala 66:30] + wire trigger_io_trigger_pkt_any_3_store; // @[lsu.scala 66:30] + wire trigger_io_trigger_pkt_any_3_load; // @[lsu.scala 66:30] + wire [31:0] trigger_io_trigger_pkt_any_3_tdata2; // @[lsu.scala 66:30] + wire trigger_io_lsu_pkt_m_valid; // @[lsu.scala 66:30] + wire trigger_io_lsu_pkt_m_bits_half; // @[lsu.scala 66:30] + wire trigger_io_lsu_pkt_m_bits_word; // @[lsu.scala 66:30] + wire trigger_io_lsu_pkt_m_bits_load; // @[lsu.scala 66:30] + wire trigger_io_lsu_pkt_m_bits_store; // @[lsu.scala 66:30] + wire trigger_io_lsu_pkt_m_bits_dma; // @[lsu.scala 66:30] + wire [31:0] trigger_io_lsu_addr_m; // @[lsu.scala 66:30] + wire [31:0] trigger_io_store_data_m; // @[lsu.scala 66:30] + wire [3:0] trigger_io_lsu_trigger_match_m; // @[lsu.scala 66:30] + wire clkdomain_clock; // @[lsu.scala 67:30] + wire clkdomain_reset; // @[lsu.scala 67:30] + wire clkdomain_io_free_clk; // @[lsu.scala 67:30] + wire clkdomain_io_clk_override; // @[lsu.scala 67:30] + wire clkdomain_io_dma_dccm_req; // @[lsu.scala 67:30] + wire clkdomain_io_ldst_stbuf_reqvld_r; // @[lsu.scala 67:30] + wire clkdomain_io_stbuf_reqvld_any; // @[lsu.scala 67:30] + wire clkdomain_io_stbuf_reqvld_flushed_any; // @[lsu.scala 67:30] + wire clkdomain_io_lsu_busreq_r; // @[lsu.scala 67:30] + wire clkdomain_io_lsu_bus_buffer_pend_any; // @[lsu.scala 67:30] + wire clkdomain_io_lsu_bus_buffer_empty_any; // @[lsu.scala 67:30] + wire clkdomain_io_lsu_stbuf_empty_any; // @[lsu.scala 67:30] + wire clkdomain_io_lsu_bus_clk_en; // @[lsu.scala 67:30] + wire clkdomain_io_lsu_p_valid; // @[lsu.scala 67:30] + wire clkdomain_io_lsu_pkt_d_valid; // @[lsu.scala 67:30] + wire clkdomain_io_lsu_pkt_d_bits_store; // @[lsu.scala 67:30] + wire clkdomain_io_lsu_pkt_m_valid; // @[lsu.scala 67:30] + wire clkdomain_io_lsu_pkt_m_bits_store; // @[lsu.scala 67:30] + wire clkdomain_io_lsu_pkt_r_valid; // @[lsu.scala 67:30] + wire clkdomain_io_lsu_c1_m_clk; // @[lsu.scala 67:30] + wire clkdomain_io_lsu_c1_r_clk; // @[lsu.scala 67:30] + wire clkdomain_io_lsu_c2_m_clk; // @[lsu.scala 67:30] + wire clkdomain_io_lsu_c2_r_clk; // @[lsu.scala 67:30] + wire clkdomain_io_lsu_store_c1_m_clk; // @[lsu.scala 67:30] + wire clkdomain_io_lsu_store_c1_r_clk; // @[lsu.scala 67:30] + wire clkdomain_io_lsu_stbuf_c1_clk; // @[lsu.scala 67:30] + wire clkdomain_io_lsu_bus_obuf_c1_clk; // @[lsu.scala 67:30] + wire clkdomain_io_lsu_bus_ibuf_c1_clk; // @[lsu.scala 67:30] + wire clkdomain_io_lsu_bus_buf_c1_clk; // @[lsu.scala 67:30] + wire clkdomain_io_lsu_busm_clk; // @[lsu.scala 67:30] + wire clkdomain_io_lsu_free_c2_clk; // @[lsu.scala 67:30] + wire clkdomain_io_scan_mode; // @[lsu.scala 67:30] + wire bus_intf_clock; // @[lsu.scala 68:30] + wire bus_intf_reset; // @[lsu.scala 68:30] + wire bus_intf_io_scan_mode; // @[lsu.scala 68:30] + wire bus_intf_io_tlu_busbuff_lsu_pmu_bus_trxn; // @[lsu.scala 68:30] + wire bus_intf_io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[lsu.scala 68:30] + wire bus_intf_io_tlu_busbuff_lsu_pmu_bus_error; // @[lsu.scala 68:30] + wire bus_intf_io_tlu_busbuff_lsu_pmu_bus_busy; // @[lsu.scala 68:30] + wire bus_intf_io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu.scala 68:30] + wire bus_intf_io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu.scala 68:30] + wire bus_intf_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu.scala 68:30] + wire bus_intf_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[lsu.scala 68:30] + wire bus_intf_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu.scala 68:30] + wire [31:0] bus_intf_io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[lsu.scala 68:30] + wire bus_intf_io_lsu_c1_m_clk; // @[lsu.scala 68:30] + wire bus_intf_io_lsu_c1_r_clk; // @[lsu.scala 68:30] + wire bus_intf_io_lsu_c2_r_clk; // @[lsu.scala 68:30] + wire bus_intf_io_lsu_bus_ibuf_c1_clk; // @[lsu.scala 68:30] + wire bus_intf_io_lsu_bus_obuf_c1_clk; // @[lsu.scala 68:30] + wire bus_intf_io_lsu_bus_buf_c1_clk; // @[lsu.scala 68:30] + wire bus_intf_io_lsu_free_c2_clk; // @[lsu.scala 68:30] + wire bus_intf_io_free_clk; // @[lsu.scala 68:30] + wire bus_intf_io_lsu_busm_clk; // @[lsu.scala 68:30] + wire bus_intf_io_axi_aw_ready; // @[lsu.scala 68:30] + wire bus_intf_io_axi_aw_valid; // @[lsu.scala 68:30] + wire [2:0] bus_intf_io_axi_aw_bits_id; // @[lsu.scala 68:30] + wire [31:0] bus_intf_io_axi_aw_bits_addr; // @[lsu.scala 68:30] + wire [3:0] bus_intf_io_axi_aw_bits_region; // @[lsu.scala 68:30] + wire [2:0] bus_intf_io_axi_aw_bits_size; // @[lsu.scala 68:30] + wire [3:0] bus_intf_io_axi_aw_bits_cache; // @[lsu.scala 68:30] + wire bus_intf_io_axi_w_ready; // @[lsu.scala 68:30] + wire bus_intf_io_axi_w_valid; // @[lsu.scala 68:30] + wire [63:0] bus_intf_io_axi_w_bits_data; // @[lsu.scala 68:30] + wire [7:0] bus_intf_io_axi_w_bits_strb; // @[lsu.scala 68:30] + wire bus_intf_io_axi_b_valid; // @[lsu.scala 68:30] + wire [1:0] bus_intf_io_axi_b_bits_resp; // @[lsu.scala 68:30] + wire [2:0] bus_intf_io_axi_b_bits_id; // @[lsu.scala 68:30] + wire bus_intf_io_axi_ar_ready; // @[lsu.scala 68:30] + wire bus_intf_io_axi_ar_valid; // @[lsu.scala 68:30] + wire [2:0] bus_intf_io_axi_ar_bits_id; // @[lsu.scala 68:30] + wire [31:0] bus_intf_io_axi_ar_bits_addr; // @[lsu.scala 68:30] + wire [3:0] bus_intf_io_axi_ar_bits_region; // @[lsu.scala 68:30] + wire [2:0] bus_intf_io_axi_ar_bits_size; // @[lsu.scala 68:30] + wire [3:0] bus_intf_io_axi_ar_bits_cache; // @[lsu.scala 68:30] + wire bus_intf_io_axi_r_valid; // @[lsu.scala 68:30] + wire [2:0] bus_intf_io_axi_r_bits_id; // @[lsu.scala 68:30] + wire [63:0] bus_intf_io_axi_r_bits_data; // @[lsu.scala 68:30] + wire [1:0] bus_intf_io_axi_r_bits_resp; // @[lsu.scala 68:30] + wire bus_intf_io_dec_lsu_valid_raw_d; // @[lsu.scala 68:30] + wire bus_intf_io_lsu_busreq_m; // @[lsu.scala 68:30] + wire bus_intf_io_lsu_pkt_m_valid; // @[lsu.scala 68:30] + wire bus_intf_io_lsu_pkt_m_bits_by; // @[lsu.scala 68:30] + wire bus_intf_io_lsu_pkt_m_bits_half; // @[lsu.scala 68:30] + wire bus_intf_io_lsu_pkt_m_bits_word; // @[lsu.scala 68:30] + wire bus_intf_io_lsu_pkt_m_bits_load; // @[lsu.scala 68:30] + wire bus_intf_io_lsu_pkt_r_valid; // @[lsu.scala 68:30] + wire bus_intf_io_lsu_pkt_r_bits_by; // @[lsu.scala 68:30] + wire bus_intf_io_lsu_pkt_r_bits_half; // @[lsu.scala 68:30] + wire bus_intf_io_lsu_pkt_r_bits_word; // @[lsu.scala 68:30] + wire bus_intf_io_lsu_pkt_r_bits_load; // @[lsu.scala 68:30] + wire bus_intf_io_lsu_pkt_r_bits_store; // @[lsu.scala 68:30] + wire bus_intf_io_lsu_pkt_r_bits_unsign; // @[lsu.scala 68:30] + wire [31:0] bus_intf_io_lsu_addr_d; // @[lsu.scala 68:30] + wire [31:0] bus_intf_io_lsu_addr_m; // @[lsu.scala 68:30] + wire [31:0] bus_intf_io_lsu_addr_r; // @[lsu.scala 68:30] + wire [31:0] bus_intf_io_end_addr_d; // @[lsu.scala 68:30] + wire [31:0] bus_intf_io_end_addr_m; // @[lsu.scala 68:30] + wire [31:0] bus_intf_io_end_addr_r; // @[lsu.scala 68:30] + wire [31:0] bus_intf_io_store_data_r; // @[lsu.scala 68:30] + wire bus_intf_io_dec_tlu_force_halt; // @[lsu.scala 68:30] + wire bus_intf_io_lsu_commit_r; // @[lsu.scala 68:30] + wire bus_intf_io_is_sideeffects_m; // @[lsu.scala 68:30] + wire bus_intf_io_flush_m_up; // @[lsu.scala 68:30] + wire bus_intf_io_flush_r; // @[lsu.scala 68:30] + wire bus_intf_io_lsu_busreq_r; // @[lsu.scala 68:30] + wire bus_intf_io_lsu_bus_buffer_pend_any; // @[lsu.scala 68:30] + wire bus_intf_io_lsu_bus_buffer_full_any; // @[lsu.scala 68:30] + wire bus_intf_io_lsu_bus_buffer_empty_any; // @[lsu.scala 68:30] + wire [31:0] bus_intf_io_bus_read_data_m; // @[lsu.scala 68:30] + wire bus_intf_io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[lsu.scala 68:30] + wire [1:0] bus_intf_io_dctl_busbuff_lsu_nonblock_load_tag_m; // @[lsu.scala 68:30] + wire bus_intf_io_dctl_busbuff_lsu_nonblock_load_inv_r; // @[lsu.scala 68:30] + wire [1:0] bus_intf_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[lsu.scala 68:30] + wire bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_valid; // @[lsu.scala 68:30] + wire bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_error; // @[lsu.scala 68:30] + wire [1:0] bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_tag; // @[lsu.scala 68:30] + wire [31:0] bus_intf_io_dctl_busbuff_lsu_nonblock_load_data; // @[lsu.scala 68:30] + wire bus_intf_io_lsu_bus_clk_en; // @[lsu.scala 68:30] + wire _T = stbuf_io_lsu_stbuf_full_any | bus_intf_io_lsu_bus_buffer_full_any; // @[lsu.scala 74:57] + wire _T_3 = ~lsu_lsc_ctl_io_lsu_pkt_m_bits_dma; // @[lsu.scala 81:58] + wire _T_4 = lsu_lsc_ctl_io_lsu_pkt_m_valid & _T_3; // @[lsu.scala 81:56] + wire _T_5 = lsu_lsc_ctl_io_addr_in_dccm_m | lsu_lsc_ctl_io_addr_in_pic_m; // @[lsu.scala 81:126] + wire _T_6 = _T_4 & _T_5; // @[lsu.scala 81:93] + wire ldst_nodma_mtor = _T_6 & lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 81:158] + wire _T_7 = io_dec_lsu_valid_raw_d | ldst_nodma_mtor; // @[lsu.scala 82:53] + wire _T_8 = _T_7 | dccm_ctl_io_ld_single_ecc_error_r_ff; // @[lsu.scala 82:71] + wire _T_10 = io_lsu_dma_dma_lsc_ctl_dma_dccm_req & io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[lsu.scala 83:58] + wire [5:0] _T_13 = {io_lsu_dma_dma_lsc_ctl_dma_mem_addr[2:0],3'h0}; // @[Cat.scala 29:58] + wire [63:0] dma_dccm_wdata = io_lsu_dma_dma_lsc_ctl_dma_mem_wdata >> _T_13; // @[lsu.scala 85:58] + wire _T_19 = ~lsu_lsc_ctl_io_lsu_pkt_r_bits_dma; // @[lsu.scala 96:130] + wire _T_20 = lsu_lsc_ctl_io_lsu_pkt_r_valid & _T_19; // @[lsu.scala 96:128] + wire _T_21 = _T_4 | _T_20; // @[lsu.scala 96:94] + wire _T_22 = ~_T_21; // @[lsu.scala 96:22] + wire _T_25 = lsu_lsc_ctl_io_lsu_pkt_r_valid & lsu_lsc_ctl_io_lsu_pkt_r_bits_store; // @[lsu.scala 98:61] + wire _T_26 = _T_25 & lsu_lsc_ctl_io_addr_in_dccm_r; // @[lsu.scala 98:99] + wire _T_27 = ~io_dec_tlu_i0_kill_writeb_r; // @[lsu.scala 98:133] + wire _T_28 = _T_26 & _T_27; // @[lsu.scala 98:131] + wire _T_30 = lsu_lsc_ctl_io_lsu_pkt_m_bits_load | lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 100:90] + wire _T_34 = _T_30 & lsu_lsc_ctl_io_addr_external_m; // @[lsu.scala 102:131] + wire _T_35 = lsu_lsc_ctl_io_lsu_pkt_m_valid & _T_34; // @[lsu.scala 102:53] + wire _T_36 = ~io_dec_tlu_flush_lower_r; // @[lsu.scala 102:167] + wire _T_37 = _T_35 & _T_36; // @[lsu.scala 102:165] + wire _T_38 = ~lsu_lsc_ctl_io_lsu_exc_m; // @[lsu.scala 102:181] + wire _T_39 = _T_37 & _T_38; // @[lsu.scala 102:179] + wire _T_40 = ~lsu_lsc_ctl_io_lsu_pkt_m_bits_fast_int; // @[lsu.scala 102:209] + wire _T_42 = lsu_lsc_ctl_io_lsu_pkt_m_bits_half & lsu_lsc_ctl_io_lsu_addr_m[0]; // @[lsu.scala 104:100] + wire _T_44 = |lsu_lsc_ctl_io_lsu_addr_m[1:0]; // @[lsu.scala 104:203] + wire _T_45 = lsu_lsc_ctl_io_lsu_pkt_m_bits_word & _T_44; // @[lsu.scala 104:170] + wire _T_46 = _T_42 | _T_45; // @[lsu.scala 104:132] + wire _T_48 = lsu_lsc_ctl_io_lsu_pkt_m_valid & lsu_lsc_ctl_io_lsu_pkt_m_bits_load; // @[lsu.scala 105:73] + wire _T_50 = lsu_lsc_ctl_io_lsu_pkt_m_valid & lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 106:73] + reg [2:0] dma_mem_tag_m; // @[lsu.scala 317:67] + reg lsu_raw_fwd_hi_r; // @[lsu.scala 318:67] + reg lsu_raw_fwd_lo_r; // @[lsu.scala 319:67] + lsu_lsc_ctl lsu_lsc_ctl ( // @[lsu.scala 60:30] + .reset(lsu_lsc_ctl_reset), + .io_lsu_c1_m_clk(lsu_lsc_ctl_io_lsu_c1_m_clk), + .io_lsu_c1_r_clk(lsu_lsc_ctl_io_lsu_c1_r_clk), + .io_lsu_c2_m_clk(lsu_lsc_ctl_io_lsu_c2_m_clk), + .io_lsu_c2_r_clk(lsu_lsc_ctl_io_lsu_c2_r_clk), + .io_lsu_store_c1_m_clk(lsu_lsc_ctl_io_lsu_store_c1_m_clk), + .io_lsu_ld_data_corr_r(lsu_lsc_ctl_io_lsu_ld_data_corr_r), + .io_lsu_single_ecc_error_r(lsu_lsc_ctl_io_lsu_single_ecc_error_r), + .io_lsu_double_ecc_error_r(lsu_lsc_ctl_io_lsu_double_ecc_error_r), + .io_lsu_ld_data_m(lsu_lsc_ctl_io_lsu_ld_data_m), + .io_lsu_single_ecc_error_m(lsu_lsc_ctl_io_lsu_single_ecc_error_m), + .io_lsu_double_ecc_error_m(lsu_lsc_ctl_io_lsu_double_ecc_error_m), + .io_flush_m_up(lsu_lsc_ctl_io_flush_m_up), + .io_flush_r(lsu_lsc_ctl_io_flush_r), + .io_lsu_exu_exu_lsu_rs1_d(lsu_lsc_ctl_io_lsu_exu_exu_lsu_rs1_d), + .io_lsu_exu_exu_lsu_rs2_d(lsu_lsc_ctl_io_lsu_exu_exu_lsu_rs2_d), + .io_lsu_p_valid(lsu_lsc_ctl_io_lsu_p_valid), + .io_lsu_p_bits_fast_int(lsu_lsc_ctl_io_lsu_p_bits_fast_int), + .io_lsu_p_bits_by(lsu_lsc_ctl_io_lsu_p_bits_by), + .io_lsu_p_bits_half(lsu_lsc_ctl_io_lsu_p_bits_half), + .io_lsu_p_bits_word(lsu_lsc_ctl_io_lsu_p_bits_word), + .io_lsu_p_bits_dword(lsu_lsc_ctl_io_lsu_p_bits_dword), + .io_lsu_p_bits_load(lsu_lsc_ctl_io_lsu_p_bits_load), + .io_lsu_p_bits_store(lsu_lsc_ctl_io_lsu_p_bits_store), + .io_lsu_p_bits_unsign(lsu_lsc_ctl_io_lsu_p_bits_unsign), + .io_lsu_p_bits_dma(lsu_lsc_ctl_io_lsu_p_bits_dma), + .io_lsu_p_bits_store_data_bypass_d(lsu_lsc_ctl_io_lsu_p_bits_store_data_bypass_d), + .io_lsu_p_bits_load_ldst_bypass_d(lsu_lsc_ctl_io_lsu_p_bits_load_ldst_bypass_d), + .io_lsu_p_bits_store_data_bypass_m(lsu_lsc_ctl_io_lsu_p_bits_store_data_bypass_m), + .io_dec_lsu_valid_raw_d(lsu_lsc_ctl_io_dec_lsu_valid_raw_d), + .io_dec_lsu_offset_d(lsu_lsc_ctl_io_dec_lsu_offset_d), + .io_picm_mask_data_m(lsu_lsc_ctl_io_picm_mask_data_m), + .io_bus_read_data_m(lsu_lsc_ctl_io_bus_read_data_m), + .io_lsu_result_m(lsu_lsc_ctl_io_lsu_result_m), + .io_lsu_result_corr_r(lsu_lsc_ctl_io_lsu_result_corr_r), + .io_lsu_addr_d(lsu_lsc_ctl_io_lsu_addr_d), + .io_lsu_addr_m(lsu_lsc_ctl_io_lsu_addr_m), + .io_lsu_addr_r(lsu_lsc_ctl_io_lsu_addr_r), + .io_end_addr_d(lsu_lsc_ctl_io_end_addr_d), + .io_end_addr_m(lsu_lsc_ctl_io_end_addr_m), + .io_end_addr_r(lsu_lsc_ctl_io_end_addr_r), + .io_store_data_m(lsu_lsc_ctl_io_store_data_m), + .io_dec_tlu_mrac_ff(lsu_lsc_ctl_io_dec_tlu_mrac_ff), + .io_lsu_exc_m(lsu_lsc_ctl_io_lsu_exc_m), + .io_is_sideeffects_m(lsu_lsc_ctl_io_is_sideeffects_m), + .io_lsu_commit_r(lsu_lsc_ctl_io_lsu_commit_r), + .io_lsu_single_ecc_error_incr(lsu_lsc_ctl_io_lsu_single_ecc_error_incr), + .io_lsu_error_pkt_r_valid(lsu_lsc_ctl_io_lsu_error_pkt_r_valid), + .io_lsu_error_pkt_r_bits_single_ecc_error(lsu_lsc_ctl_io_lsu_error_pkt_r_bits_single_ecc_error), + .io_lsu_error_pkt_r_bits_inst_type(lsu_lsc_ctl_io_lsu_error_pkt_r_bits_inst_type), + .io_lsu_error_pkt_r_bits_exc_type(lsu_lsc_ctl_io_lsu_error_pkt_r_bits_exc_type), + .io_lsu_error_pkt_r_bits_mscause(lsu_lsc_ctl_io_lsu_error_pkt_r_bits_mscause), + .io_lsu_error_pkt_r_bits_addr(lsu_lsc_ctl_io_lsu_error_pkt_r_bits_addr), + .io_lsu_fir_addr(lsu_lsc_ctl_io_lsu_fir_addr), + .io_lsu_fir_error(lsu_lsc_ctl_io_lsu_fir_error), + .io_addr_in_dccm_d(lsu_lsc_ctl_io_addr_in_dccm_d), + .io_addr_in_dccm_m(lsu_lsc_ctl_io_addr_in_dccm_m), + .io_addr_in_dccm_r(lsu_lsc_ctl_io_addr_in_dccm_r), + .io_addr_in_pic_d(lsu_lsc_ctl_io_addr_in_pic_d), + .io_addr_in_pic_m(lsu_lsc_ctl_io_addr_in_pic_m), + .io_addr_in_pic_r(lsu_lsc_ctl_io_addr_in_pic_r), + .io_addr_external_m(lsu_lsc_ctl_io_addr_external_m), + .io_dma_lsc_ctl_dma_dccm_req(lsu_lsc_ctl_io_dma_lsc_ctl_dma_dccm_req), + .io_dma_lsc_ctl_dma_mem_addr(lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_addr), + .io_dma_lsc_ctl_dma_mem_sz(lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_sz), + .io_dma_lsc_ctl_dma_mem_write(lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_write), + .io_dma_lsc_ctl_dma_mem_wdata(lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_wdata), + .io_lsu_pkt_d_valid(lsu_lsc_ctl_io_lsu_pkt_d_valid), + .io_lsu_pkt_d_bits_fast_int(lsu_lsc_ctl_io_lsu_pkt_d_bits_fast_int), + .io_lsu_pkt_d_bits_by(lsu_lsc_ctl_io_lsu_pkt_d_bits_by), + .io_lsu_pkt_d_bits_half(lsu_lsc_ctl_io_lsu_pkt_d_bits_half), + .io_lsu_pkt_d_bits_word(lsu_lsc_ctl_io_lsu_pkt_d_bits_word), + .io_lsu_pkt_d_bits_dword(lsu_lsc_ctl_io_lsu_pkt_d_bits_dword), + .io_lsu_pkt_d_bits_load(lsu_lsc_ctl_io_lsu_pkt_d_bits_load), + .io_lsu_pkt_d_bits_store(lsu_lsc_ctl_io_lsu_pkt_d_bits_store), + .io_lsu_pkt_d_bits_unsign(lsu_lsc_ctl_io_lsu_pkt_d_bits_unsign), + .io_lsu_pkt_d_bits_dma(lsu_lsc_ctl_io_lsu_pkt_d_bits_dma), + .io_lsu_pkt_d_bits_store_data_bypass_d(lsu_lsc_ctl_io_lsu_pkt_d_bits_store_data_bypass_d), + .io_lsu_pkt_d_bits_load_ldst_bypass_d(lsu_lsc_ctl_io_lsu_pkt_d_bits_load_ldst_bypass_d), + .io_lsu_pkt_d_bits_store_data_bypass_m(lsu_lsc_ctl_io_lsu_pkt_d_bits_store_data_bypass_m), + .io_lsu_pkt_m_valid(lsu_lsc_ctl_io_lsu_pkt_m_valid), + .io_lsu_pkt_m_bits_fast_int(lsu_lsc_ctl_io_lsu_pkt_m_bits_fast_int), + .io_lsu_pkt_m_bits_by(lsu_lsc_ctl_io_lsu_pkt_m_bits_by), + .io_lsu_pkt_m_bits_half(lsu_lsc_ctl_io_lsu_pkt_m_bits_half), + .io_lsu_pkt_m_bits_word(lsu_lsc_ctl_io_lsu_pkt_m_bits_word), + .io_lsu_pkt_m_bits_dword(lsu_lsc_ctl_io_lsu_pkt_m_bits_dword), + .io_lsu_pkt_m_bits_load(lsu_lsc_ctl_io_lsu_pkt_m_bits_load), + .io_lsu_pkt_m_bits_store(lsu_lsc_ctl_io_lsu_pkt_m_bits_store), + .io_lsu_pkt_m_bits_unsign(lsu_lsc_ctl_io_lsu_pkt_m_bits_unsign), + .io_lsu_pkt_m_bits_dma(lsu_lsc_ctl_io_lsu_pkt_m_bits_dma), + .io_lsu_pkt_m_bits_store_data_bypass_m(lsu_lsc_ctl_io_lsu_pkt_m_bits_store_data_bypass_m), + .io_lsu_pkt_r_valid(lsu_lsc_ctl_io_lsu_pkt_r_valid), + .io_lsu_pkt_r_bits_by(lsu_lsc_ctl_io_lsu_pkt_r_bits_by), + .io_lsu_pkt_r_bits_half(lsu_lsc_ctl_io_lsu_pkt_r_bits_half), + .io_lsu_pkt_r_bits_word(lsu_lsc_ctl_io_lsu_pkt_r_bits_word), + .io_lsu_pkt_r_bits_dword(lsu_lsc_ctl_io_lsu_pkt_r_bits_dword), + .io_lsu_pkt_r_bits_load(lsu_lsc_ctl_io_lsu_pkt_r_bits_load), + .io_lsu_pkt_r_bits_store(lsu_lsc_ctl_io_lsu_pkt_r_bits_store), + .io_lsu_pkt_r_bits_unsign(lsu_lsc_ctl_io_lsu_pkt_r_bits_unsign), + .io_lsu_pkt_r_bits_dma(lsu_lsc_ctl_io_lsu_pkt_r_bits_dma) + ); + lsu_dccm_ctl dccm_ctl ( // @[lsu.scala 63:30] + .clock(dccm_ctl_clock), + .reset(dccm_ctl_reset), + .io_lsu_c2_m_clk(dccm_ctl_io_lsu_c2_m_clk), + .io_lsu_c2_r_clk(dccm_ctl_io_lsu_c2_r_clk), + .io_lsu_free_c2_clk(dccm_ctl_io_lsu_free_c2_clk), + .io_lsu_store_c1_r_clk(dccm_ctl_io_lsu_store_c1_r_clk), + .io_lsu_pkt_d_valid(dccm_ctl_io_lsu_pkt_d_valid), + .io_lsu_pkt_d_bits_word(dccm_ctl_io_lsu_pkt_d_bits_word), + .io_lsu_pkt_d_bits_dword(dccm_ctl_io_lsu_pkt_d_bits_dword), + .io_lsu_pkt_d_bits_load(dccm_ctl_io_lsu_pkt_d_bits_load), + .io_lsu_pkt_d_bits_store(dccm_ctl_io_lsu_pkt_d_bits_store), + .io_lsu_pkt_d_bits_dma(dccm_ctl_io_lsu_pkt_d_bits_dma), + .io_lsu_pkt_m_valid(dccm_ctl_io_lsu_pkt_m_valid), + .io_lsu_pkt_m_bits_by(dccm_ctl_io_lsu_pkt_m_bits_by), + .io_lsu_pkt_m_bits_half(dccm_ctl_io_lsu_pkt_m_bits_half), + .io_lsu_pkt_m_bits_word(dccm_ctl_io_lsu_pkt_m_bits_word), + .io_lsu_pkt_m_bits_load(dccm_ctl_io_lsu_pkt_m_bits_load), + .io_lsu_pkt_m_bits_store(dccm_ctl_io_lsu_pkt_m_bits_store), + .io_lsu_pkt_m_bits_dma(dccm_ctl_io_lsu_pkt_m_bits_dma), + .io_lsu_pkt_r_valid(dccm_ctl_io_lsu_pkt_r_valid), + .io_lsu_pkt_r_bits_by(dccm_ctl_io_lsu_pkt_r_bits_by), + .io_lsu_pkt_r_bits_half(dccm_ctl_io_lsu_pkt_r_bits_half), + .io_lsu_pkt_r_bits_word(dccm_ctl_io_lsu_pkt_r_bits_word), + .io_lsu_pkt_r_bits_load(dccm_ctl_io_lsu_pkt_r_bits_load), + .io_lsu_pkt_r_bits_store(dccm_ctl_io_lsu_pkt_r_bits_store), + .io_lsu_pkt_r_bits_dma(dccm_ctl_io_lsu_pkt_r_bits_dma), + .io_addr_in_dccm_d(dccm_ctl_io_addr_in_dccm_d), + .io_addr_in_dccm_m(dccm_ctl_io_addr_in_dccm_m), + .io_addr_in_dccm_r(dccm_ctl_io_addr_in_dccm_r), + .io_addr_in_pic_d(dccm_ctl_io_addr_in_pic_d), + .io_addr_in_pic_m(dccm_ctl_io_addr_in_pic_m), + .io_addr_in_pic_r(dccm_ctl_io_addr_in_pic_r), + .io_lsu_raw_fwd_lo_r(dccm_ctl_io_lsu_raw_fwd_lo_r), + .io_lsu_raw_fwd_hi_r(dccm_ctl_io_lsu_raw_fwd_hi_r), + .io_lsu_commit_r(dccm_ctl_io_lsu_commit_r), + .io_lsu_addr_d(dccm_ctl_io_lsu_addr_d), + .io_lsu_addr_m(dccm_ctl_io_lsu_addr_m), + .io_lsu_addr_r(dccm_ctl_io_lsu_addr_r), + .io_end_addr_d(dccm_ctl_io_end_addr_d), + .io_end_addr_m(dccm_ctl_io_end_addr_m), + .io_end_addr_r(dccm_ctl_io_end_addr_r), + .io_stbuf_reqvld_any(dccm_ctl_io_stbuf_reqvld_any), + .io_stbuf_addr_any(dccm_ctl_io_stbuf_addr_any), + .io_stbuf_data_any(dccm_ctl_io_stbuf_data_any), + .io_stbuf_ecc_any(dccm_ctl_io_stbuf_ecc_any), + .io_stbuf_fwddata_hi_m(dccm_ctl_io_stbuf_fwddata_hi_m), + .io_stbuf_fwddata_lo_m(dccm_ctl_io_stbuf_fwddata_lo_m), + .io_stbuf_fwdbyteen_lo_m(dccm_ctl_io_stbuf_fwdbyteen_lo_m), + .io_stbuf_fwdbyteen_hi_m(dccm_ctl_io_stbuf_fwdbyteen_hi_m), + .io_lsu_ld_data_corr_r(dccm_ctl_io_lsu_ld_data_corr_r), + .io_lsu_double_ecc_error_r(dccm_ctl_io_lsu_double_ecc_error_r), + .io_single_ecc_error_hi_r(dccm_ctl_io_single_ecc_error_hi_r), + .io_single_ecc_error_lo_r(dccm_ctl_io_single_ecc_error_lo_r), + .io_sec_data_hi_r_ff(dccm_ctl_io_sec_data_hi_r_ff), + .io_sec_data_lo_r_ff(dccm_ctl_io_sec_data_lo_r_ff), + .io_sec_data_ecc_hi_r_ff(dccm_ctl_io_sec_data_ecc_hi_r_ff), + .io_sec_data_ecc_lo_r_ff(dccm_ctl_io_sec_data_ecc_lo_r_ff), + .io_dccm_rdata_hi_m(dccm_ctl_io_dccm_rdata_hi_m), + .io_dccm_rdata_lo_m(dccm_ctl_io_dccm_rdata_lo_m), + .io_dccm_data_ecc_hi_m(dccm_ctl_io_dccm_data_ecc_hi_m), + .io_dccm_data_ecc_lo_m(dccm_ctl_io_dccm_data_ecc_lo_m), + .io_lsu_ld_data_m(dccm_ctl_io_lsu_ld_data_m), + .io_lsu_double_ecc_error_m(dccm_ctl_io_lsu_double_ecc_error_m), + .io_sec_data_hi_m(dccm_ctl_io_sec_data_hi_m), + .io_sec_data_lo_m(dccm_ctl_io_sec_data_lo_m), + .io_store_data_m(dccm_ctl_io_store_data_m), + .io_dma_dccm_wen(dccm_ctl_io_dma_dccm_wen), + .io_dma_pic_wen(dccm_ctl_io_dma_pic_wen), + .io_dma_mem_tag_m(dccm_ctl_io_dma_mem_tag_m), + .io_dma_dccm_wdata_lo(dccm_ctl_io_dma_dccm_wdata_lo), + .io_dma_dccm_wdata_hi(dccm_ctl_io_dma_dccm_wdata_hi), + .io_dma_dccm_wdata_ecc_hi(dccm_ctl_io_dma_dccm_wdata_ecc_hi), + .io_dma_dccm_wdata_ecc_lo(dccm_ctl_io_dma_dccm_wdata_ecc_lo), + .io_store_data_hi_r(dccm_ctl_io_store_data_hi_r), + .io_store_data_lo_r(dccm_ctl_io_store_data_lo_r), + .io_store_datafn_hi_r(dccm_ctl_io_store_datafn_hi_r), + .io_store_datafn_lo_r(dccm_ctl_io_store_datafn_lo_r), + .io_store_data_r(dccm_ctl_io_store_data_r), + .io_ld_single_ecc_error_r(dccm_ctl_io_ld_single_ecc_error_r), + .io_ld_single_ecc_error_r_ff(dccm_ctl_io_ld_single_ecc_error_r_ff), + .io_picm_mask_data_m(dccm_ctl_io_picm_mask_data_m), + .io_lsu_stbuf_commit_any(dccm_ctl_io_lsu_stbuf_commit_any), + .io_lsu_dccm_rden_m(dccm_ctl_io_lsu_dccm_rden_m), + .io_dma_dccm_ctl_dma_mem_addr(dccm_ctl_io_dma_dccm_ctl_dma_mem_addr), + .io_dma_dccm_ctl_dma_mem_wdata(dccm_ctl_io_dma_dccm_ctl_dma_mem_wdata), + .io_dma_dccm_ctl_dccm_dma_rvalid(dccm_ctl_io_dma_dccm_ctl_dccm_dma_rvalid), + .io_dma_dccm_ctl_dccm_dma_ecc_error(dccm_ctl_io_dma_dccm_ctl_dccm_dma_ecc_error), + .io_dma_dccm_ctl_dccm_dma_rtag(dccm_ctl_io_dma_dccm_ctl_dccm_dma_rtag), + .io_dma_dccm_ctl_dccm_dma_rdata(dccm_ctl_io_dma_dccm_ctl_dccm_dma_rdata), + .io_dccm_wren(dccm_ctl_io_dccm_wren), + .io_dccm_rden(dccm_ctl_io_dccm_rden), + .io_dccm_wr_addr_lo(dccm_ctl_io_dccm_wr_addr_lo), + .io_dccm_wr_addr_hi(dccm_ctl_io_dccm_wr_addr_hi), + .io_dccm_rd_addr_lo(dccm_ctl_io_dccm_rd_addr_lo), + .io_dccm_rd_addr_hi(dccm_ctl_io_dccm_rd_addr_hi), + .io_dccm_wr_data_lo(dccm_ctl_io_dccm_wr_data_lo), + .io_dccm_wr_data_hi(dccm_ctl_io_dccm_wr_data_hi), + .io_dccm_rd_data_lo(dccm_ctl_io_dccm_rd_data_lo), + .io_dccm_rd_data_hi(dccm_ctl_io_dccm_rd_data_hi), + .io_lsu_pic_picm_wren(dccm_ctl_io_lsu_pic_picm_wren), + .io_lsu_pic_picm_rden(dccm_ctl_io_lsu_pic_picm_rden), + .io_lsu_pic_picm_mken(dccm_ctl_io_lsu_pic_picm_mken), + .io_lsu_pic_picm_rdaddr(dccm_ctl_io_lsu_pic_picm_rdaddr), + .io_lsu_pic_picm_wraddr(dccm_ctl_io_lsu_pic_picm_wraddr), + .io_lsu_pic_picm_wr_data(dccm_ctl_io_lsu_pic_picm_wr_data), + .io_lsu_pic_picm_rd_data(dccm_ctl_io_lsu_pic_picm_rd_data), + .io_scan_mode(dccm_ctl_io_scan_mode) + ); + lsu_stbuf stbuf ( // @[lsu.scala 64:30] + .clock(stbuf_clock), + .reset(stbuf_reset), + .io_lsu_c1_m_clk(stbuf_io_lsu_c1_m_clk), + .io_lsu_c1_r_clk(stbuf_io_lsu_c1_r_clk), + .io_lsu_stbuf_c1_clk(stbuf_io_lsu_stbuf_c1_clk), + .io_lsu_free_c2_clk(stbuf_io_lsu_free_c2_clk), + .io_lsu_pkt_m_valid(stbuf_io_lsu_pkt_m_valid), + .io_lsu_pkt_m_bits_store(stbuf_io_lsu_pkt_m_bits_store), + .io_lsu_pkt_m_bits_dma(stbuf_io_lsu_pkt_m_bits_dma), + .io_lsu_pkt_r_valid(stbuf_io_lsu_pkt_r_valid), + .io_lsu_pkt_r_bits_by(stbuf_io_lsu_pkt_r_bits_by), + .io_lsu_pkt_r_bits_half(stbuf_io_lsu_pkt_r_bits_half), + .io_lsu_pkt_r_bits_word(stbuf_io_lsu_pkt_r_bits_word), + .io_lsu_pkt_r_bits_dword(stbuf_io_lsu_pkt_r_bits_dword), + .io_lsu_pkt_r_bits_store(stbuf_io_lsu_pkt_r_bits_store), + .io_lsu_pkt_r_bits_dma(stbuf_io_lsu_pkt_r_bits_dma), + .io_store_stbuf_reqvld_r(stbuf_io_store_stbuf_reqvld_r), + .io_lsu_commit_r(stbuf_io_lsu_commit_r), + .io_dec_lsu_valid_raw_d(stbuf_io_dec_lsu_valid_raw_d), + .io_store_data_hi_r(stbuf_io_store_data_hi_r), + .io_store_data_lo_r(stbuf_io_store_data_lo_r), + .io_store_datafn_hi_r(stbuf_io_store_datafn_hi_r), + .io_store_datafn_lo_r(stbuf_io_store_datafn_lo_r), + .io_lsu_stbuf_commit_any(stbuf_io_lsu_stbuf_commit_any), + .io_lsu_addr_d(stbuf_io_lsu_addr_d), + .io_lsu_addr_m(stbuf_io_lsu_addr_m), + .io_lsu_addr_r(stbuf_io_lsu_addr_r), + .io_end_addr_d(stbuf_io_end_addr_d), + .io_end_addr_m(stbuf_io_end_addr_m), + .io_end_addr_r(stbuf_io_end_addr_r), + .io_addr_in_dccm_m(stbuf_io_addr_in_dccm_m), + .io_addr_in_dccm_r(stbuf_io_addr_in_dccm_r), + .io_scan_mode(stbuf_io_scan_mode), + .io_stbuf_reqvld_any(stbuf_io_stbuf_reqvld_any), + .io_stbuf_reqvld_flushed_any(stbuf_io_stbuf_reqvld_flushed_any), + .io_stbuf_addr_any(stbuf_io_stbuf_addr_any), + .io_stbuf_data_any(stbuf_io_stbuf_data_any), + .io_lsu_stbuf_full_any(stbuf_io_lsu_stbuf_full_any), + .io_lsu_stbuf_empty_any(stbuf_io_lsu_stbuf_empty_any), + .io_ldst_stbuf_reqvld_r(stbuf_io_ldst_stbuf_reqvld_r), + .io_stbuf_fwddata_hi_m(stbuf_io_stbuf_fwddata_hi_m), + .io_stbuf_fwddata_lo_m(stbuf_io_stbuf_fwddata_lo_m), + .io_stbuf_fwdbyteen_hi_m(stbuf_io_stbuf_fwdbyteen_hi_m), + .io_stbuf_fwdbyteen_lo_m(stbuf_io_stbuf_fwdbyteen_lo_m) + ); + lsu_ecc ecc ( // @[lsu.scala 65:30] + .clock(ecc_clock), + .reset(ecc_reset), + .io_lsu_c2_r_clk(ecc_io_lsu_c2_r_clk), + .io_lsu_pkt_m_valid(ecc_io_lsu_pkt_m_valid), + .io_lsu_pkt_m_bits_load(ecc_io_lsu_pkt_m_bits_load), + .io_lsu_pkt_m_bits_store(ecc_io_lsu_pkt_m_bits_store), + .io_lsu_pkt_m_bits_dma(ecc_io_lsu_pkt_m_bits_dma), + .io_stbuf_data_any(ecc_io_stbuf_data_any), + .io_dec_tlu_core_ecc_disable(ecc_io_dec_tlu_core_ecc_disable), + .io_lsu_addr_m(ecc_io_lsu_addr_m), + .io_end_addr_m(ecc_io_end_addr_m), + .io_dccm_rdata_hi_m(ecc_io_dccm_rdata_hi_m), + .io_dccm_rdata_lo_m(ecc_io_dccm_rdata_lo_m), + .io_dccm_data_ecc_hi_m(ecc_io_dccm_data_ecc_hi_m), + .io_dccm_data_ecc_lo_m(ecc_io_dccm_data_ecc_lo_m), + .io_ld_single_ecc_error_r(ecc_io_ld_single_ecc_error_r), + .io_ld_single_ecc_error_r_ff(ecc_io_ld_single_ecc_error_r_ff), + .io_lsu_dccm_rden_m(ecc_io_lsu_dccm_rden_m), + .io_addr_in_dccm_m(ecc_io_addr_in_dccm_m), + .io_dma_dccm_wen(ecc_io_dma_dccm_wen), + .io_dma_dccm_wdata_lo(ecc_io_dma_dccm_wdata_lo), + .io_dma_dccm_wdata_hi(ecc_io_dma_dccm_wdata_hi), + .io_scan_mode(ecc_io_scan_mode), + .io_sec_data_hi_r(ecc_io_sec_data_hi_r), + .io_sec_data_lo_r(ecc_io_sec_data_lo_r), + .io_sec_data_hi_m(ecc_io_sec_data_hi_m), + .io_sec_data_lo_m(ecc_io_sec_data_lo_m), + .io_sec_data_hi_r_ff(ecc_io_sec_data_hi_r_ff), + .io_sec_data_lo_r_ff(ecc_io_sec_data_lo_r_ff), + .io_dma_dccm_wdata_ecc_hi(ecc_io_dma_dccm_wdata_ecc_hi), + .io_dma_dccm_wdata_ecc_lo(ecc_io_dma_dccm_wdata_ecc_lo), + .io_stbuf_ecc_any(ecc_io_stbuf_ecc_any), + .io_sec_data_ecc_hi_r_ff(ecc_io_sec_data_ecc_hi_r_ff), + .io_sec_data_ecc_lo_r_ff(ecc_io_sec_data_ecc_lo_r_ff), + .io_single_ecc_error_hi_r(ecc_io_single_ecc_error_hi_r), + .io_single_ecc_error_lo_r(ecc_io_single_ecc_error_lo_r), + .io_lsu_single_ecc_error_r(ecc_io_lsu_single_ecc_error_r), + .io_lsu_double_ecc_error_r(ecc_io_lsu_double_ecc_error_r), + .io_lsu_single_ecc_error_m(ecc_io_lsu_single_ecc_error_m), + .io_lsu_double_ecc_error_m(ecc_io_lsu_double_ecc_error_m) + ); + lsu_trigger trigger ( // @[lsu.scala 66:30] + .io_trigger_pkt_any_0_select(trigger_io_trigger_pkt_any_0_select), + .io_trigger_pkt_any_0_match_pkt(trigger_io_trigger_pkt_any_0_match_pkt), + .io_trigger_pkt_any_0_store(trigger_io_trigger_pkt_any_0_store), + .io_trigger_pkt_any_0_load(trigger_io_trigger_pkt_any_0_load), + .io_trigger_pkt_any_0_tdata2(trigger_io_trigger_pkt_any_0_tdata2), + .io_trigger_pkt_any_1_select(trigger_io_trigger_pkt_any_1_select), + .io_trigger_pkt_any_1_match_pkt(trigger_io_trigger_pkt_any_1_match_pkt), + .io_trigger_pkt_any_1_store(trigger_io_trigger_pkt_any_1_store), + .io_trigger_pkt_any_1_load(trigger_io_trigger_pkt_any_1_load), + .io_trigger_pkt_any_1_tdata2(trigger_io_trigger_pkt_any_1_tdata2), + .io_trigger_pkt_any_2_select(trigger_io_trigger_pkt_any_2_select), + .io_trigger_pkt_any_2_match_pkt(trigger_io_trigger_pkt_any_2_match_pkt), + .io_trigger_pkt_any_2_store(trigger_io_trigger_pkt_any_2_store), + .io_trigger_pkt_any_2_load(trigger_io_trigger_pkt_any_2_load), + .io_trigger_pkt_any_2_tdata2(trigger_io_trigger_pkt_any_2_tdata2), + .io_trigger_pkt_any_3_select(trigger_io_trigger_pkt_any_3_select), + .io_trigger_pkt_any_3_match_pkt(trigger_io_trigger_pkt_any_3_match_pkt), + .io_trigger_pkt_any_3_store(trigger_io_trigger_pkt_any_3_store), + .io_trigger_pkt_any_3_load(trigger_io_trigger_pkt_any_3_load), + .io_trigger_pkt_any_3_tdata2(trigger_io_trigger_pkt_any_3_tdata2), + .io_lsu_pkt_m_valid(trigger_io_lsu_pkt_m_valid), + .io_lsu_pkt_m_bits_half(trigger_io_lsu_pkt_m_bits_half), + .io_lsu_pkt_m_bits_word(trigger_io_lsu_pkt_m_bits_word), + .io_lsu_pkt_m_bits_load(trigger_io_lsu_pkt_m_bits_load), + .io_lsu_pkt_m_bits_store(trigger_io_lsu_pkt_m_bits_store), + .io_lsu_pkt_m_bits_dma(trigger_io_lsu_pkt_m_bits_dma), + .io_lsu_addr_m(trigger_io_lsu_addr_m), + .io_store_data_m(trigger_io_store_data_m), + .io_lsu_trigger_match_m(trigger_io_lsu_trigger_match_m) + ); + lsu_clkdomain clkdomain ( // @[lsu.scala 67:30] + .clock(clkdomain_clock), + .reset(clkdomain_reset), + .io_free_clk(clkdomain_io_free_clk), + .io_clk_override(clkdomain_io_clk_override), + .io_dma_dccm_req(clkdomain_io_dma_dccm_req), + .io_ldst_stbuf_reqvld_r(clkdomain_io_ldst_stbuf_reqvld_r), + .io_stbuf_reqvld_any(clkdomain_io_stbuf_reqvld_any), + .io_stbuf_reqvld_flushed_any(clkdomain_io_stbuf_reqvld_flushed_any), + .io_lsu_busreq_r(clkdomain_io_lsu_busreq_r), + .io_lsu_bus_buffer_pend_any(clkdomain_io_lsu_bus_buffer_pend_any), + .io_lsu_bus_buffer_empty_any(clkdomain_io_lsu_bus_buffer_empty_any), + .io_lsu_stbuf_empty_any(clkdomain_io_lsu_stbuf_empty_any), + .io_lsu_bus_clk_en(clkdomain_io_lsu_bus_clk_en), + .io_lsu_p_valid(clkdomain_io_lsu_p_valid), + .io_lsu_pkt_d_valid(clkdomain_io_lsu_pkt_d_valid), + .io_lsu_pkt_d_bits_store(clkdomain_io_lsu_pkt_d_bits_store), + .io_lsu_pkt_m_valid(clkdomain_io_lsu_pkt_m_valid), + .io_lsu_pkt_m_bits_store(clkdomain_io_lsu_pkt_m_bits_store), + .io_lsu_pkt_r_valid(clkdomain_io_lsu_pkt_r_valid), + .io_lsu_c1_m_clk(clkdomain_io_lsu_c1_m_clk), + .io_lsu_c1_r_clk(clkdomain_io_lsu_c1_r_clk), + .io_lsu_c2_m_clk(clkdomain_io_lsu_c2_m_clk), + .io_lsu_c2_r_clk(clkdomain_io_lsu_c2_r_clk), + .io_lsu_store_c1_m_clk(clkdomain_io_lsu_store_c1_m_clk), + .io_lsu_store_c1_r_clk(clkdomain_io_lsu_store_c1_r_clk), + .io_lsu_stbuf_c1_clk(clkdomain_io_lsu_stbuf_c1_clk), + .io_lsu_bus_obuf_c1_clk(clkdomain_io_lsu_bus_obuf_c1_clk), + .io_lsu_bus_ibuf_c1_clk(clkdomain_io_lsu_bus_ibuf_c1_clk), + .io_lsu_bus_buf_c1_clk(clkdomain_io_lsu_bus_buf_c1_clk), + .io_lsu_busm_clk(clkdomain_io_lsu_busm_clk), + .io_lsu_free_c2_clk(clkdomain_io_lsu_free_c2_clk), + .io_scan_mode(clkdomain_io_scan_mode) + ); + lsu_bus_intf bus_intf ( // @[lsu.scala 68:30] + .clock(bus_intf_clock), + .reset(bus_intf_reset), + .io_scan_mode(bus_intf_io_scan_mode), + .io_tlu_busbuff_lsu_pmu_bus_trxn(bus_intf_io_tlu_busbuff_lsu_pmu_bus_trxn), + .io_tlu_busbuff_lsu_pmu_bus_misaligned(bus_intf_io_tlu_busbuff_lsu_pmu_bus_misaligned), + .io_tlu_busbuff_lsu_pmu_bus_error(bus_intf_io_tlu_busbuff_lsu_pmu_bus_error), + .io_tlu_busbuff_lsu_pmu_bus_busy(bus_intf_io_tlu_busbuff_lsu_pmu_bus_busy), + .io_tlu_busbuff_dec_tlu_external_ldfwd_disable(bus_intf_io_tlu_busbuff_dec_tlu_external_ldfwd_disable), + .io_tlu_busbuff_dec_tlu_wb_coalescing_disable(bus_intf_io_tlu_busbuff_dec_tlu_wb_coalescing_disable), + .io_tlu_busbuff_dec_tlu_sideeffect_posted_disable(bus_intf_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable), + .io_tlu_busbuff_lsu_imprecise_error_load_any(bus_intf_io_tlu_busbuff_lsu_imprecise_error_load_any), + .io_tlu_busbuff_lsu_imprecise_error_store_any(bus_intf_io_tlu_busbuff_lsu_imprecise_error_store_any), + .io_tlu_busbuff_lsu_imprecise_error_addr_any(bus_intf_io_tlu_busbuff_lsu_imprecise_error_addr_any), + .io_lsu_c1_m_clk(bus_intf_io_lsu_c1_m_clk), + .io_lsu_c1_r_clk(bus_intf_io_lsu_c1_r_clk), + .io_lsu_c2_r_clk(bus_intf_io_lsu_c2_r_clk), + .io_lsu_bus_ibuf_c1_clk(bus_intf_io_lsu_bus_ibuf_c1_clk), + .io_lsu_bus_obuf_c1_clk(bus_intf_io_lsu_bus_obuf_c1_clk), + .io_lsu_bus_buf_c1_clk(bus_intf_io_lsu_bus_buf_c1_clk), + .io_lsu_free_c2_clk(bus_intf_io_lsu_free_c2_clk), + .io_free_clk(bus_intf_io_free_clk), + .io_lsu_busm_clk(bus_intf_io_lsu_busm_clk), + .io_axi_aw_ready(bus_intf_io_axi_aw_ready), + .io_axi_aw_valid(bus_intf_io_axi_aw_valid), + .io_axi_aw_bits_id(bus_intf_io_axi_aw_bits_id), + .io_axi_aw_bits_addr(bus_intf_io_axi_aw_bits_addr), + .io_axi_aw_bits_region(bus_intf_io_axi_aw_bits_region), + .io_axi_aw_bits_size(bus_intf_io_axi_aw_bits_size), + .io_axi_aw_bits_cache(bus_intf_io_axi_aw_bits_cache), + .io_axi_w_ready(bus_intf_io_axi_w_ready), + .io_axi_w_valid(bus_intf_io_axi_w_valid), + .io_axi_w_bits_data(bus_intf_io_axi_w_bits_data), + .io_axi_w_bits_strb(bus_intf_io_axi_w_bits_strb), + .io_axi_b_valid(bus_intf_io_axi_b_valid), + .io_axi_b_bits_resp(bus_intf_io_axi_b_bits_resp), + .io_axi_b_bits_id(bus_intf_io_axi_b_bits_id), + .io_axi_ar_ready(bus_intf_io_axi_ar_ready), + .io_axi_ar_valid(bus_intf_io_axi_ar_valid), + .io_axi_ar_bits_id(bus_intf_io_axi_ar_bits_id), + .io_axi_ar_bits_addr(bus_intf_io_axi_ar_bits_addr), + .io_axi_ar_bits_region(bus_intf_io_axi_ar_bits_region), + .io_axi_ar_bits_size(bus_intf_io_axi_ar_bits_size), + .io_axi_ar_bits_cache(bus_intf_io_axi_ar_bits_cache), + .io_axi_r_valid(bus_intf_io_axi_r_valid), + .io_axi_r_bits_id(bus_intf_io_axi_r_bits_id), + .io_axi_r_bits_data(bus_intf_io_axi_r_bits_data), + .io_axi_r_bits_resp(bus_intf_io_axi_r_bits_resp), + .io_dec_lsu_valid_raw_d(bus_intf_io_dec_lsu_valid_raw_d), + .io_lsu_busreq_m(bus_intf_io_lsu_busreq_m), + .io_lsu_pkt_m_valid(bus_intf_io_lsu_pkt_m_valid), + .io_lsu_pkt_m_bits_by(bus_intf_io_lsu_pkt_m_bits_by), + .io_lsu_pkt_m_bits_half(bus_intf_io_lsu_pkt_m_bits_half), + .io_lsu_pkt_m_bits_word(bus_intf_io_lsu_pkt_m_bits_word), + .io_lsu_pkt_m_bits_load(bus_intf_io_lsu_pkt_m_bits_load), + .io_lsu_pkt_r_valid(bus_intf_io_lsu_pkt_r_valid), + .io_lsu_pkt_r_bits_by(bus_intf_io_lsu_pkt_r_bits_by), + .io_lsu_pkt_r_bits_half(bus_intf_io_lsu_pkt_r_bits_half), + .io_lsu_pkt_r_bits_word(bus_intf_io_lsu_pkt_r_bits_word), + .io_lsu_pkt_r_bits_load(bus_intf_io_lsu_pkt_r_bits_load), + .io_lsu_pkt_r_bits_store(bus_intf_io_lsu_pkt_r_bits_store), + .io_lsu_pkt_r_bits_unsign(bus_intf_io_lsu_pkt_r_bits_unsign), + .io_lsu_addr_d(bus_intf_io_lsu_addr_d), + .io_lsu_addr_m(bus_intf_io_lsu_addr_m), + .io_lsu_addr_r(bus_intf_io_lsu_addr_r), + .io_end_addr_d(bus_intf_io_end_addr_d), + .io_end_addr_m(bus_intf_io_end_addr_m), + .io_end_addr_r(bus_intf_io_end_addr_r), + .io_store_data_r(bus_intf_io_store_data_r), + .io_dec_tlu_force_halt(bus_intf_io_dec_tlu_force_halt), + .io_lsu_commit_r(bus_intf_io_lsu_commit_r), + .io_is_sideeffects_m(bus_intf_io_is_sideeffects_m), + .io_flush_m_up(bus_intf_io_flush_m_up), + .io_flush_r(bus_intf_io_flush_r), + .io_lsu_busreq_r(bus_intf_io_lsu_busreq_r), + .io_lsu_bus_buffer_pend_any(bus_intf_io_lsu_bus_buffer_pend_any), + .io_lsu_bus_buffer_full_any(bus_intf_io_lsu_bus_buffer_full_any), + .io_lsu_bus_buffer_empty_any(bus_intf_io_lsu_bus_buffer_empty_any), + .io_bus_read_data_m(bus_intf_io_bus_read_data_m), + .io_dctl_busbuff_lsu_nonblock_load_valid_m(bus_intf_io_dctl_busbuff_lsu_nonblock_load_valid_m), + .io_dctl_busbuff_lsu_nonblock_load_tag_m(bus_intf_io_dctl_busbuff_lsu_nonblock_load_tag_m), + .io_dctl_busbuff_lsu_nonblock_load_inv_r(bus_intf_io_dctl_busbuff_lsu_nonblock_load_inv_r), + .io_dctl_busbuff_lsu_nonblock_load_inv_tag_r(bus_intf_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r), + .io_dctl_busbuff_lsu_nonblock_load_data_valid(bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_valid), + .io_dctl_busbuff_lsu_nonblock_load_data_error(bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_error), + .io_dctl_busbuff_lsu_nonblock_load_data_tag(bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_tag), + .io_dctl_busbuff_lsu_nonblock_load_data(bus_intf_io_dctl_busbuff_lsu_nonblock_load_data), + .io_lsu_bus_clk_en(bus_intf_io_lsu_bus_clk_en) + ); + assign io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid = dccm_ctl_io_dma_dccm_ctl_dccm_dma_rvalid; // @[lsu.scala 194:27] + assign io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error = dccm_ctl_io_dma_dccm_ctl_dccm_dma_ecc_error; // @[lsu.scala 194:27] + assign io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag = dccm_ctl_io_dma_dccm_ctl_dccm_dma_rtag; // @[lsu.scala 194:27] + assign io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata = dccm_ctl_io_dma_dccm_ctl_dccm_dma_rdata; // @[lsu.scala 194:27] + assign io_lsu_dma_dccm_ready = ~_T_8; // @[lsu.scala 82:25] + assign io_lsu_pic_picm_wren = dccm_ctl_io_lsu_pic_picm_wren; // @[lsu.scala 196:14] + assign io_lsu_pic_picm_rden = dccm_ctl_io_lsu_pic_picm_rden; // @[lsu.scala 196:14] + assign io_lsu_pic_picm_mken = dccm_ctl_io_lsu_pic_picm_mken; // @[lsu.scala 196:14] + assign io_lsu_pic_picm_rdaddr = dccm_ctl_io_lsu_pic_picm_rdaddr; // @[lsu.scala 196:14] + assign io_lsu_pic_picm_wraddr = dccm_ctl_io_lsu_pic_picm_wraddr; // @[lsu.scala 196:14] + assign io_lsu_pic_picm_wr_data = dccm_ctl_io_lsu_pic_picm_wr_data; // @[lsu.scala 196:14] + assign io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn = bus_intf_io_tlu_busbuff_lsu_pmu_bus_trxn; // @[lsu.scala 286:26] + assign io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned = bus_intf_io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[lsu.scala 286:26] + assign io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error = bus_intf_io_tlu_busbuff_lsu_pmu_bus_error; // @[lsu.scala 286:26] + assign io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy = bus_intf_io_tlu_busbuff_lsu_pmu_bus_busy; // @[lsu.scala 286:26] + assign io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any = bus_intf_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[lsu.scala 286:26] + assign io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any = bus_intf_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu.scala 286:26] + assign io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any = bus_intf_io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[lsu.scala 286:26] + assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m = bus_intf_io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[lsu.scala 313:27] + assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m = bus_intf_io_dctl_busbuff_lsu_nonblock_load_tag_m; // @[lsu.scala 313:27] + assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r = bus_intf_io_dctl_busbuff_lsu_nonblock_load_inv_r; // @[lsu.scala 313:27] + assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r = bus_intf_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[lsu.scala 313:27] + assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid = bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_valid; // @[lsu.scala 313:27] + assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error = bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_error; // @[lsu.scala 313:27] + assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag = bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_tag; // @[lsu.scala 313:27] + assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data = bus_intf_io_dctl_busbuff_lsu_nonblock_load_data; // @[lsu.scala 313:27] + assign io_dccm_wren = dccm_ctl_io_dccm_wren; // @[lsu.scala 195:11] + assign io_dccm_rden = dccm_ctl_io_dccm_rden; // @[lsu.scala 195:11] + assign io_dccm_wr_addr_lo = dccm_ctl_io_dccm_wr_addr_lo; // @[lsu.scala 195:11] + assign io_dccm_wr_addr_hi = dccm_ctl_io_dccm_wr_addr_hi; // @[lsu.scala 195:11] + assign io_dccm_rd_addr_lo = dccm_ctl_io_dccm_rd_addr_lo; // @[lsu.scala 195:11] + assign io_dccm_rd_addr_hi = dccm_ctl_io_dccm_rd_addr_hi; // @[lsu.scala 195:11] + assign io_dccm_wr_data_lo = dccm_ctl_io_dccm_wr_data_lo; // @[lsu.scala 195:11] + assign io_dccm_wr_data_hi = dccm_ctl_io_dccm_wr_data_hi; // @[lsu.scala 195:11] + assign io_lsu_tlu_lsu_pmu_load_external_m = _T_48 & lsu_lsc_ctl_io_addr_external_m; // @[lsu.scala 105:39] + assign io_lsu_tlu_lsu_pmu_store_external_m = _T_50 & lsu_lsc_ctl_io_addr_external_m; // @[lsu.scala 106:39] + assign io_axi_aw_valid = bus_intf_io_axi_aw_valid; // @[lsu.scala 314:49] + assign io_axi_aw_bits_id = bus_intf_io_axi_aw_bits_id; // @[lsu.scala 314:49] + assign io_axi_aw_bits_addr = bus_intf_io_axi_aw_bits_addr; // @[lsu.scala 314:49] + assign io_axi_aw_bits_region = bus_intf_io_axi_aw_bits_region; // @[lsu.scala 314:49] + assign io_axi_aw_bits_len = 8'h0; // @[lsu.scala 314:49] + assign io_axi_aw_bits_size = bus_intf_io_axi_aw_bits_size; // @[lsu.scala 314:49] + assign io_axi_aw_bits_burst = 2'h1; // @[lsu.scala 314:49] + assign io_axi_aw_bits_lock = 1'h0; // @[lsu.scala 314:49] + assign io_axi_aw_bits_cache = bus_intf_io_axi_aw_bits_cache; // @[lsu.scala 314:49] + assign io_axi_aw_bits_prot = 3'h0; // @[lsu.scala 314:49] + assign io_axi_aw_bits_qos = 4'h0; // @[lsu.scala 314:49] + assign io_axi_w_valid = bus_intf_io_axi_w_valid; // @[lsu.scala 314:49] + assign io_axi_w_bits_data = bus_intf_io_axi_w_bits_data; // @[lsu.scala 314:49] + assign io_axi_w_bits_strb = bus_intf_io_axi_w_bits_strb; // @[lsu.scala 314:49] + assign io_axi_w_bits_last = 1'h1; // @[lsu.scala 314:49] + assign io_axi_b_ready = 1'h1; // @[lsu.scala 314:49] + assign io_axi_ar_valid = bus_intf_io_axi_ar_valid; // @[lsu.scala 314:49] + assign io_axi_ar_bits_id = bus_intf_io_axi_ar_bits_id; // @[lsu.scala 314:49] + assign io_axi_ar_bits_addr = bus_intf_io_axi_ar_bits_addr; // @[lsu.scala 314:49] + assign io_axi_ar_bits_region = bus_intf_io_axi_ar_bits_region; // @[lsu.scala 314:49] + assign io_axi_ar_bits_len = 8'h0; // @[lsu.scala 314:49] + assign io_axi_ar_bits_size = bus_intf_io_axi_ar_bits_size; // @[lsu.scala 314:49] + assign io_axi_ar_bits_burst = 2'h1; // @[lsu.scala 314:49] + assign io_axi_ar_bits_lock = 1'h0; // @[lsu.scala 314:49] + assign io_axi_ar_bits_cache = bus_intf_io_axi_ar_bits_cache; // @[lsu.scala 314:49] + assign io_axi_ar_bits_prot = 3'h0; // @[lsu.scala 314:49] + assign io_axi_ar_bits_qos = 4'h0; // @[lsu.scala 314:49] + assign io_axi_r_ready = 1'h1; // @[lsu.scala 314:49] + assign io_lsu_result_m = lsu_lsc_ctl_io_lsu_result_m; // @[lsu.scala 61:19] + assign io_lsu_result_corr_r = lsu_lsc_ctl_io_lsu_result_corr_r; // @[lsu.scala 62:24] + assign io_lsu_load_stall_any = bus_intf_io_lsu_bus_buffer_full_any | dccm_ctl_io_ld_single_ecc_error_r_ff; // @[lsu.scala 75:25] + assign io_lsu_store_stall_any = _T | dccm_ctl_io_ld_single_ecc_error_r_ff; // @[lsu.scala 74:26] + assign io_lsu_fastint_stall_any = dccm_ctl_io_ld_single_ecc_error_r; // @[lsu.scala 76:28] + assign io_lsu_idle_any = _T_22 & bus_intf_io_lsu_bus_buffer_empty_any; // @[lsu.scala 96:19] + assign io_lsu_fir_addr = lsu_lsc_ctl_io_lsu_fir_addr; // @[lsu.scala 137:49] + assign io_lsu_fir_error = lsu_lsc_ctl_io_lsu_fir_error; // @[lsu.scala 138:49] + assign io_lsu_single_ecc_error_incr = lsu_lsc_ctl_io_lsu_single_ecc_error_incr; // @[lsu.scala 135:49] + assign io_lsu_error_pkt_r_valid = lsu_lsc_ctl_io_lsu_error_pkt_r_valid; // @[lsu.scala 136:49] + assign io_lsu_error_pkt_r_bits_single_ecc_error = lsu_lsc_ctl_io_lsu_error_pkt_r_bits_single_ecc_error; // @[lsu.scala 136:49] + assign io_lsu_error_pkt_r_bits_inst_type = lsu_lsc_ctl_io_lsu_error_pkt_r_bits_inst_type; // @[lsu.scala 136:49] + assign io_lsu_error_pkt_r_bits_exc_type = lsu_lsc_ctl_io_lsu_error_pkt_r_bits_exc_type; // @[lsu.scala 136:49] + assign io_lsu_error_pkt_r_bits_mscause = lsu_lsc_ctl_io_lsu_error_pkt_r_bits_mscause; // @[lsu.scala 136:49] + assign io_lsu_error_pkt_r_bits_addr = lsu_lsc_ctl_io_lsu_error_pkt_r_bits_addr; // @[lsu.scala 136:49] + assign io_lsu_pmu_misaligned_m = lsu_lsc_ctl_io_lsu_pkt_m_valid & _T_46; // @[lsu.scala 104:27] + assign io_lsu_trigger_match_m = trigger_io_lsu_trigger_match_m; // @[lsu.scala 261:50] + assign lsu_lsc_ctl_reset = reset; + assign lsu_lsc_ctl_io_lsu_c1_m_clk = clkdomain_io_lsu_c1_m_clk; // @[lsu.scala 110:46] + assign lsu_lsc_ctl_io_lsu_c1_r_clk = clkdomain_io_lsu_c1_r_clk; // @[lsu.scala 111:46] + assign lsu_lsc_ctl_io_lsu_c2_m_clk = clkdomain_io_lsu_c2_m_clk; // @[lsu.scala 112:46] + assign lsu_lsc_ctl_io_lsu_c2_r_clk = clkdomain_io_lsu_c2_r_clk; // @[lsu.scala 113:46] + assign lsu_lsc_ctl_io_lsu_store_c1_m_clk = clkdomain_io_lsu_store_c1_m_clk; // @[lsu.scala 114:46] + assign lsu_lsc_ctl_io_lsu_ld_data_corr_r = dccm_ctl_io_lsu_ld_data_corr_r; // @[lsu.scala 116:46] + assign lsu_lsc_ctl_io_lsu_single_ecc_error_r = ecc_io_lsu_single_ecc_error_r; // @[lsu.scala 117:46] + assign lsu_lsc_ctl_io_lsu_double_ecc_error_r = ecc_io_lsu_double_ecc_error_r; // @[lsu.scala 118:46] + assign lsu_lsc_ctl_io_lsu_ld_data_m = dccm_ctl_io_lsu_ld_data_m; // @[lsu.scala 119:46] + assign lsu_lsc_ctl_io_lsu_single_ecc_error_m = ecc_io_lsu_single_ecc_error_m; // @[lsu.scala 120:46] + assign lsu_lsc_ctl_io_lsu_double_ecc_error_m = ecc_io_lsu_double_ecc_error_m; // @[lsu.scala 121:46] + assign lsu_lsc_ctl_io_flush_m_up = io_dec_tlu_flush_lower_r; // @[lsu.scala 122:46] + assign lsu_lsc_ctl_io_flush_r = io_dec_tlu_i0_kill_writeb_r; // @[lsu.scala 123:46] + assign lsu_lsc_ctl_io_lsu_exu_exu_lsu_rs1_d = io_lsu_exu_exu_lsu_rs1_d; // @[lsu.scala 124:46] + assign lsu_lsc_ctl_io_lsu_exu_exu_lsu_rs2_d = io_lsu_exu_exu_lsu_rs2_d; // @[lsu.scala 124:46] + assign lsu_lsc_ctl_io_lsu_p_valid = io_lsu_p_valid; // @[lsu.scala 125:46] + assign lsu_lsc_ctl_io_lsu_p_bits_fast_int = io_lsu_p_bits_fast_int; // @[lsu.scala 125:46] + assign lsu_lsc_ctl_io_lsu_p_bits_by = io_lsu_p_bits_by; // @[lsu.scala 125:46] + assign lsu_lsc_ctl_io_lsu_p_bits_half = io_lsu_p_bits_half; // @[lsu.scala 125:46] + assign lsu_lsc_ctl_io_lsu_p_bits_word = io_lsu_p_bits_word; // @[lsu.scala 125:46] + assign lsu_lsc_ctl_io_lsu_p_bits_dword = io_lsu_p_bits_dword; // @[lsu.scala 125:46] + assign lsu_lsc_ctl_io_lsu_p_bits_load = io_lsu_p_bits_load; // @[lsu.scala 125:46] + assign lsu_lsc_ctl_io_lsu_p_bits_store = io_lsu_p_bits_store; // @[lsu.scala 125:46] + assign lsu_lsc_ctl_io_lsu_p_bits_unsign = io_lsu_p_bits_unsign; // @[lsu.scala 125:46] + assign lsu_lsc_ctl_io_lsu_p_bits_dma = io_lsu_p_bits_dma; // @[lsu.scala 125:46] + assign lsu_lsc_ctl_io_lsu_p_bits_store_data_bypass_d = io_lsu_p_bits_store_data_bypass_d; // @[lsu.scala 125:46] + assign lsu_lsc_ctl_io_lsu_p_bits_load_ldst_bypass_d = io_lsu_p_bits_load_ldst_bypass_d; // @[lsu.scala 125:46] + assign lsu_lsc_ctl_io_lsu_p_bits_store_data_bypass_m = io_lsu_p_bits_store_data_bypass_m; // @[lsu.scala 125:46] + assign lsu_lsc_ctl_io_dec_lsu_valid_raw_d = io_dec_lsu_valid_raw_d; // @[lsu.scala 126:46] + assign lsu_lsc_ctl_io_dec_lsu_offset_d = io_dec_lsu_offset_d; // @[lsu.scala 127:46] + assign lsu_lsc_ctl_io_picm_mask_data_m = dccm_ctl_io_picm_mask_data_m; // @[lsu.scala 128:46] + assign lsu_lsc_ctl_io_bus_read_data_m = bus_intf_io_bus_read_data_m; // @[lsu.scala 129:46] + assign lsu_lsc_ctl_io_dec_tlu_mrac_ff = io_dec_tlu_mrac_ff; // @[lsu.scala 131:46] + assign lsu_lsc_ctl_io_dma_lsc_ctl_dma_dccm_req = io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[lsu.scala 130:38] + assign lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_addr = io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[lsu.scala 130:38] + assign lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_sz = io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[lsu.scala 130:38] + assign lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_write = io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[lsu.scala 130:38] + assign lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_wdata = io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[lsu.scala 130:38] + assign dccm_ctl_clock = clock; + assign dccm_ctl_reset = reset; + assign dccm_ctl_io_lsu_c2_m_clk = clkdomain_io_lsu_c2_m_clk; // @[lsu.scala 141:46] + assign dccm_ctl_io_lsu_c2_r_clk = clkdomain_io_lsu_c2_r_clk; // @[lsu.scala 142:46] + assign dccm_ctl_io_lsu_free_c2_clk = clkdomain_io_lsu_free_c2_clk; // @[lsu.scala 143:46] + assign dccm_ctl_io_lsu_store_c1_r_clk = clkdomain_io_lsu_store_c1_r_clk; // @[lsu.scala 145:46] + assign dccm_ctl_io_lsu_pkt_d_valid = lsu_lsc_ctl_io_lsu_pkt_d_valid; // @[lsu.scala 146:46] + assign dccm_ctl_io_lsu_pkt_d_bits_word = lsu_lsc_ctl_io_lsu_pkt_d_bits_word; // @[lsu.scala 146:46] + assign dccm_ctl_io_lsu_pkt_d_bits_dword = lsu_lsc_ctl_io_lsu_pkt_d_bits_dword; // @[lsu.scala 146:46] + assign dccm_ctl_io_lsu_pkt_d_bits_load = lsu_lsc_ctl_io_lsu_pkt_d_bits_load; // @[lsu.scala 146:46] + assign dccm_ctl_io_lsu_pkt_d_bits_store = lsu_lsc_ctl_io_lsu_pkt_d_bits_store; // @[lsu.scala 146:46] + assign dccm_ctl_io_lsu_pkt_d_bits_dma = lsu_lsc_ctl_io_lsu_pkt_d_bits_dma; // @[lsu.scala 146:46] + assign dccm_ctl_io_lsu_pkt_m_valid = lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 147:46] + assign dccm_ctl_io_lsu_pkt_m_bits_by = lsu_lsc_ctl_io_lsu_pkt_m_bits_by; // @[lsu.scala 147:46] + assign dccm_ctl_io_lsu_pkt_m_bits_half = lsu_lsc_ctl_io_lsu_pkt_m_bits_half; // @[lsu.scala 147:46] + assign dccm_ctl_io_lsu_pkt_m_bits_word = lsu_lsc_ctl_io_lsu_pkt_m_bits_word; // @[lsu.scala 147:46] + assign dccm_ctl_io_lsu_pkt_m_bits_load = lsu_lsc_ctl_io_lsu_pkt_m_bits_load; // @[lsu.scala 147:46] + assign dccm_ctl_io_lsu_pkt_m_bits_store = lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 147:46] + assign dccm_ctl_io_lsu_pkt_m_bits_dma = lsu_lsc_ctl_io_lsu_pkt_m_bits_dma; // @[lsu.scala 147:46] + assign dccm_ctl_io_lsu_pkt_r_valid = lsu_lsc_ctl_io_lsu_pkt_r_valid; // @[lsu.scala 148:46] + assign dccm_ctl_io_lsu_pkt_r_bits_by = lsu_lsc_ctl_io_lsu_pkt_r_bits_by; // @[lsu.scala 148:46] + assign dccm_ctl_io_lsu_pkt_r_bits_half = lsu_lsc_ctl_io_lsu_pkt_r_bits_half; // @[lsu.scala 148:46] + assign dccm_ctl_io_lsu_pkt_r_bits_word = lsu_lsc_ctl_io_lsu_pkt_r_bits_word; // @[lsu.scala 148:46] + assign dccm_ctl_io_lsu_pkt_r_bits_load = lsu_lsc_ctl_io_lsu_pkt_r_bits_load; // @[lsu.scala 148:46] + assign dccm_ctl_io_lsu_pkt_r_bits_store = lsu_lsc_ctl_io_lsu_pkt_r_bits_store; // @[lsu.scala 148:46] + assign dccm_ctl_io_lsu_pkt_r_bits_dma = lsu_lsc_ctl_io_lsu_pkt_r_bits_dma; // @[lsu.scala 148:46] + assign dccm_ctl_io_addr_in_dccm_d = lsu_lsc_ctl_io_addr_in_dccm_d; // @[lsu.scala 149:46] + assign dccm_ctl_io_addr_in_dccm_m = lsu_lsc_ctl_io_addr_in_dccm_m; // @[lsu.scala 150:46] + assign dccm_ctl_io_addr_in_dccm_r = lsu_lsc_ctl_io_addr_in_dccm_r; // @[lsu.scala 151:46] + assign dccm_ctl_io_addr_in_pic_d = lsu_lsc_ctl_io_addr_in_pic_d; // @[lsu.scala 152:46] + assign dccm_ctl_io_addr_in_pic_m = lsu_lsc_ctl_io_addr_in_pic_m; // @[lsu.scala 153:46] + assign dccm_ctl_io_addr_in_pic_r = lsu_lsc_ctl_io_addr_in_pic_r; // @[lsu.scala 154:46] + assign dccm_ctl_io_lsu_raw_fwd_lo_r = lsu_raw_fwd_lo_r; // @[lsu.scala 155:46] + assign dccm_ctl_io_lsu_raw_fwd_hi_r = lsu_raw_fwd_hi_r; // @[lsu.scala 156:46] + assign dccm_ctl_io_lsu_commit_r = lsu_lsc_ctl_io_lsu_commit_r; // @[lsu.scala 157:46] + assign dccm_ctl_io_lsu_addr_d = lsu_lsc_ctl_io_lsu_addr_d; // @[lsu.scala 158:46] + assign dccm_ctl_io_lsu_addr_m = lsu_lsc_ctl_io_lsu_addr_m[15:0]; // @[lsu.scala 159:46] + assign dccm_ctl_io_lsu_addr_r = lsu_lsc_ctl_io_lsu_addr_r; // @[lsu.scala 160:46] + assign dccm_ctl_io_end_addr_d = lsu_lsc_ctl_io_end_addr_d[15:0]; // @[lsu.scala 161:46] + assign dccm_ctl_io_end_addr_m = lsu_lsc_ctl_io_end_addr_m[15:0]; // @[lsu.scala 162:46] + assign dccm_ctl_io_end_addr_r = lsu_lsc_ctl_io_end_addr_r[15:0]; // @[lsu.scala 163:46] + assign dccm_ctl_io_stbuf_reqvld_any = stbuf_io_stbuf_reqvld_any; // @[lsu.scala 164:46] + assign dccm_ctl_io_stbuf_addr_any = stbuf_io_stbuf_addr_any; // @[lsu.scala 165:46] + assign dccm_ctl_io_stbuf_data_any = stbuf_io_stbuf_data_any; // @[lsu.scala 166:46] + assign dccm_ctl_io_stbuf_ecc_any = ecc_io_stbuf_ecc_any; // @[lsu.scala 167:46] + assign dccm_ctl_io_stbuf_fwddata_hi_m = stbuf_io_stbuf_fwddata_hi_m; // @[lsu.scala 168:46] + assign dccm_ctl_io_stbuf_fwddata_lo_m = stbuf_io_stbuf_fwddata_lo_m; // @[lsu.scala 169:46] + assign dccm_ctl_io_stbuf_fwdbyteen_lo_m = stbuf_io_stbuf_fwdbyteen_lo_m; // @[lsu.scala 170:46] + assign dccm_ctl_io_stbuf_fwdbyteen_hi_m = stbuf_io_stbuf_fwdbyteen_hi_m; // @[lsu.scala 171:46] + assign dccm_ctl_io_lsu_double_ecc_error_r = ecc_io_lsu_double_ecc_error_r; // @[lsu.scala 172:46] + assign dccm_ctl_io_single_ecc_error_hi_r = ecc_io_single_ecc_error_hi_r; // @[lsu.scala 173:46] + assign dccm_ctl_io_single_ecc_error_lo_r = ecc_io_single_ecc_error_lo_r; // @[lsu.scala 174:46] + assign dccm_ctl_io_sec_data_hi_r_ff = ecc_io_sec_data_hi_r_ff; // @[lsu.scala 177:46] + assign dccm_ctl_io_sec_data_lo_r_ff = ecc_io_sec_data_lo_r_ff; // @[lsu.scala 178:46] + assign dccm_ctl_io_sec_data_ecc_hi_r_ff = ecc_io_sec_data_ecc_hi_r_ff; // @[lsu.scala 179:46] + assign dccm_ctl_io_sec_data_ecc_lo_r_ff = ecc_io_sec_data_ecc_lo_r_ff; // @[lsu.scala 180:46] + assign dccm_ctl_io_lsu_double_ecc_error_m = ecc_io_lsu_double_ecc_error_m; // @[lsu.scala 181:46] + assign dccm_ctl_io_sec_data_hi_m = ecc_io_sec_data_hi_m; // @[lsu.scala 182:46] + assign dccm_ctl_io_sec_data_lo_m = ecc_io_sec_data_lo_m; // @[lsu.scala 183:46] + assign dccm_ctl_io_store_data_m = lsu_lsc_ctl_io_store_data_m; // @[lsu.scala 184:46] + assign dccm_ctl_io_dma_dccm_wen = _T_10 & lsu_lsc_ctl_io_addr_in_dccm_d; // @[lsu.scala 185:46] + assign dccm_ctl_io_dma_pic_wen = _T_10 & lsu_lsc_ctl_io_addr_in_pic_d; // @[lsu.scala 186:46] + assign dccm_ctl_io_dma_mem_tag_m = dma_mem_tag_m; // @[lsu.scala 187:46] + assign dccm_ctl_io_dma_dccm_wdata_lo = dma_dccm_wdata[31:0]; // @[lsu.scala 188:46] + assign dccm_ctl_io_dma_dccm_wdata_hi = dma_dccm_wdata[63:32]; // @[lsu.scala 189:46] + assign dccm_ctl_io_dma_dccm_wdata_ecc_hi = ecc_io_dma_dccm_wdata_ecc_hi; // @[lsu.scala 190:46] + assign dccm_ctl_io_dma_dccm_wdata_ecc_lo = ecc_io_dma_dccm_wdata_ecc_lo; // @[lsu.scala 191:46] + assign dccm_ctl_io_dma_dccm_ctl_dma_mem_addr = io_lsu_dma_dma_dccm_ctl_dma_mem_addr; // @[lsu.scala 194:27] + assign dccm_ctl_io_dma_dccm_ctl_dma_mem_wdata = io_lsu_dma_dma_dccm_ctl_dma_mem_wdata; // @[lsu.scala 194:27] + assign dccm_ctl_io_dccm_rd_data_lo = io_dccm_rd_data_lo; // @[lsu.scala 195:11] + assign dccm_ctl_io_dccm_rd_data_hi = io_dccm_rd_data_hi; // @[lsu.scala 195:11] + assign dccm_ctl_io_lsu_pic_picm_rd_data = io_lsu_pic_picm_rd_data; // @[lsu.scala 196:14] + assign dccm_ctl_io_scan_mode = io_scan_mode; // @[lsu.scala 192:46] + assign stbuf_clock = clock; + assign stbuf_reset = reset; + assign stbuf_io_lsu_c1_m_clk = clkdomain_io_lsu_c1_m_clk; // @[lsu.scala 199:49] + assign stbuf_io_lsu_c1_r_clk = clkdomain_io_lsu_c1_r_clk; // @[lsu.scala 200:48] + assign stbuf_io_lsu_stbuf_c1_clk = clkdomain_io_lsu_stbuf_c1_clk; // @[lsu.scala 201:54] + assign stbuf_io_lsu_free_c2_clk = clkdomain_io_lsu_free_c2_clk; // @[lsu.scala 202:54] + assign stbuf_io_lsu_pkt_m_valid = lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 203:48] + assign stbuf_io_lsu_pkt_m_bits_store = lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 203:48] + assign stbuf_io_lsu_pkt_m_bits_dma = lsu_lsc_ctl_io_lsu_pkt_m_bits_dma; // @[lsu.scala 203:48] + assign stbuf_io_lsu_pkt_r_valid = lsu_lsc_ctl_io_lsu_pkt_r_valid; // @[lsu.scala 204:48] + assign stbuf_io_lsu_pkt_r_bits_by = lsu_lsc_ctl_io_lsu_pkt_r_bits_by; // @[lsu.scala 204:48] + assign stbuf_io_lsu_pkt_r_bits_half = lsu_lsc_ctl_io_lsu_pkt_r_bits_half; // @[lsu.scala 204:48] + assign stbuf_io_lsu_pkt_r_bits_word = lsu_lsc_ctl_io_lsu_pkt_r_bits_word; // @[lsu.scala 204:48] + assign stbuf_io_lsu_pkt_r_bits_dword = lsu_lsc_ctl_io_lsu_pkt_r_bits_dword; // @[lsu.scala 204:48] + assign stbuf_io_lsu_pkt_r_bits_store = lsu_lsc_ctl_io_lsu_pkt_r_bits_store; // @[lsu.scala 204:48] + assign stbuf_io_lsu_pkt_r_bits_dma = lsu_lsc_ctl_io_lsu_pkt_r_bits_dma; // @[lsu.scala 204:48] + assign stbuf_io_store_stbuf_reqvld_r = _T_28 & _T_19; // @[lsu.scala 205:48] + assign stbuf_io_lsu_commit_r = lsu_lsc_ctl_io_lsu_commit_r; // @[lsu.scala 206:49] + assign stbuf_io_dec_lsu_valid_raw_d = io_dec_lsu_valid_raw_d; // @[lsu.scala 207:49] + assign stbuf_io_store_data_hi_r = dccm_ctl_io_store_data_hi_r; // @[lsu.scala 208:62] + assign stbuf_io_store_data_lo_r = dccm_ctl_io_store_data_lo_r; // @[lsu.scala 209:62] + assign stbuf_io_store_datafn_hi_r = dccm_ctl_io_store_datafn_hi_r; // @[lsu.scala 210:49] + assign stbuf_io_store_datafn_lo_r = dccm_ctl_io_store_datafn_lo_r; // @[lsu.scala 211:56] + assign stbuf_io_lsu_stbuf_commit_any = dccm_ctl_io_lsu_stbuf_commit_any; // @[lsu.scala 212:52] + assign stbuf_io_lsu_addr_d = lsu_lsc_ctl_io_lsu_addr_d[15:0]; // @[lsu.scala 213:64] + assign stbuf_io_lsu_addr_m = lsu_lsc_ctl_io_lsu_addr_m; // @[lsu.scala 214:64] + assign stbuf_io_lsu_addr_r = lsu_lsc_ctl_io_lsu_addr_r; // @[lsu.scala 215:64] + assign stbuf_io_end_addr_d = lsu_lsc_ctl_io_end_addr_d[15:0]; // @[lsu.scala 216:64] + assign stbuf_io_end_addr_m = lsu_lsc_ctl_io_end_addr_m; // @[lsu.scala 217:64] + assign stbuf_io_end_addr_r = lsu_lsc_ctl_io_end_addr_r; // @[lsu.scala 218:64] + assign stbuf_io_addr_in_dccm_m = lsu_lsc_ctl_io_addr_in_dccm_m; // @[lsu.scala 219:49] + assign stbuf_io_addr_in_dccm_r = lsu_lsc_ctl_io_addr_in_dccm_r; // @[lsu.scala 220:56] + assign stbuf_io_scan_mode = io_scan_mode; // @[lsu.scala 222:49] + assign ecc_clock = clock; + assign ecc_reset = reset; + assign ecc_io_lsu_c2_r_clk = clkdomain_io_lsu_c2_r_clk; // @[lsu.scala 226:52] + assign ecc_io_lsu_pkt_m_valid = lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 227:52] + assign ecc_io_lsu_pkt_m_bits_load = lsu_lsc_ctl_io_lsu_pkt_m_bits_load; // @[lsu.scala 227:52] + assign ecc_io_lsu_pkt_m_bits_store = lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 227:52] + assign ecc_io_lsu_pkt_m_bits_dma = lsu_lsc_ctl_io_lsu_pkt_m_bits_dma; // @[lsu.scala 227:52] + assign ecc_io_stbuf_data_any = stbuf_io_stbuf_data_any; // @[lsu.scala 229:54] + assign ecc_io_dec_tlu_core_ecc_disable = io_dec_tlu_core_ecc_disable; // @[lsu.scala 230:50] + assign ecc_io_lsu_addr_m = lsu_lsc_ctl_io_lsu_addr_m[15:0]; // @[lsu.scala 235:58] + assign ecc_io_end_addr_m = lsu_lsc_ctl_io_end_addr_m[15:0]; // @[lsu.scala 236:58] + assign ecc_io_dccm_rdata_hi_m = dccm_ctl_io_dccm_rdata_hi_m; // @[lsu.scala 239:54] + assign ecc_io_dccm_rdata_lo_m = dccm_ctl_io_dccm_rdata_lo_m; // @[lsu.scala 240:54] + assign ecc_io_dccm_data_ecc_hi_m = dccm_ctl_io_dccm_data_ecc_hi_m; // @[lsu.scala 243:50] + assign ecc_io_dccm_data_ecc_lo_m = dccm_ctl_io_dccm_data_ecc_lo_m; // @[lsu.scala 244:50] + assign ecc_io_ld_single_ecc_error_r = dccm_ctl_io_ld_single_ecc_error_r; // @[lsu.scala 245:50] + assign ecc_io_ld_single_ecc_error_r_ff = dccm_ctl_io_ld_single_ecc_error_r_ff; // @[lsu.scala 246:50] + assign ecc_io_lsu_dccm_rden_m = dccm_ctl_io_lsu_dccm_rden_m; // @[lsu.scala 247:50] + assign ecc_io_addr_in_dccm_m = lsu_lsc_ctl_io_addr_in_dccm_m; // @[lsu.scala 248:50] + assign ecc_io_dma_dccm_wen = _T_10 & lsu_lsc_ctl_io_addr_in_dccm_d; // @[lsu.scala 249:50] + assign ecc_io_dma_dccm_wdata_lo = dma_dccm_wdata[31:0]; // @[lsu.scala 250:50] + assign ecc_io_dma_dccm_wdata_hi = dma_dccm_wdata[63:32]; // @[lsu.scala 251:50] + assign ecc_io_scan_mode = io_scan_mode; // @[lsu.scala 252:50] + assign trigger_io_trigger_pkt_any_0_select = io_trigger_pkt_any_0_select; // @[lsu.scala 256:50] + assign trigger_io_trigger_pkt_any_0_match_pkt = io_trigger_pkt_any_0_match_pkt; // @[lsu.scala 256:50] + assign trigger_io_trigger_pkt_any_0_store = io_trigger_pkt_any_0_store; // @[lsu.scala 256:50] + assign trigger_io_trigger_pkt_any_0_load = io_trigger_pkt_any_0_load; // @[lsu.scala 256:50] + assign trigger_io_trigger_pkt_any_0_tdata2 = io_trigger_pkt_any_0_tdata2; // @[lsu.scala 256:50] + assign trigger_io_trigger_pkt_any_1_select = io_trigger_pkt_any_1_select; // @[lsu.scala 256:50] + assign trigger_io_trigger_pkt_any_1_match_pkt = io_trigger_pkt_any_1_match_pkt; // @[lsu.scala 256:50] + assign trigger_io_trigger_pkt_any_1_store = io_trigger_pkt_any_1_store; // @[lsu.scala 256:50] + assign trigger_io_trigger_pkt_any_1_load = io_trigger_pkt_any_1_load; // @[lsu.scala 256:50] + assign trigger_io_trigger_pkt_any_1_tdata2 = io_trigger_pkt_any_1_tdata2; // @[lsu.scala 256:50] + assign trigger_io_trigger_pkt_any_2_select = io_trigger_pkt_any_2_select; // @[lsu.scala 256:50] + assign trigger_io_trigger_pkt_any_2_match_pkt = io_trigger_pkt_any_2_match_pkt; // @[lsu.scala 256:50] + assign trigger_io_trigger_pkt_any_2_store = io_trigger_pkt_any_2_store; // @[lsu.scala 256:50] + assign trigger_io_trigger_pkt_any_2_load = io_trigger_pkt_any_2_load; // @[lsu.scala 256:50] + assign trigger_io_trigger_pkt_any_2_tdata2 = io_trigger_pkt_any_2_tdata2; // @[lsu.scala 256:50] + assign trigger_io_trigger_pkt_any_3_select = io_trigger_pkt_any_3_select; // @[lsu.scala 256:50] + assign trigger_io_trigger_pkt_any_3_match_pkt = io_trigger_pkt_any_3_match_pkt; // @[lsu.scala 256:50] + assign trigger_io_trigger_pkt_any_3_store = io_trigger_pkt_any_3_store; // @[lsu.scala 256:50] + assign trigger_io_trigger_pkt_any_3_load = io_trigger_pkt_any_3_load; // @[lsu.scala 256:50] + assign trigger_io_trigger_pkt_any_3_tdata2 = io_trigger_pkt_any_3_tdata2; // @[lsu.scala 256:50] + assign trigger_io_lsu_pkt_m_valid = lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 257:50] + assign trigger_io_lsu_pkt_m_bits_half = lsu_lsc_ctl_io_lsu_pkt_m_bits_half; // @[lsu.scala 257:50] + assign trigger_io_lsu_pkt_m_bits_word = lsu_lsc_ctl_io_lsu_pkt_m_bits_word; // @[lsu.scala 257:50] + assign trigger_io_lsu_pkt_m_bits_load = lsu_lsc_ctl_io_lsu_pkt_m_bits_load; // @[lsu.scala 257:50] + assign trigger_io_lsu_pkt_m_bits_store = lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 257:50] + assign trigger_io_lsu_pkt_m_bits_dma = lsu_lsc_ctl_io_lsu_pkt_m_bits_dma; // @[lsu.scala 257:50] + assign trigger_io_lsu_addr_m = lsu_lsc_ctl_io_lsu_addr_m; // @[lsu.scala 258:50] + assign trigger_io_store_data_m = lsu_lsc_ctl_io_store_data_m; // @[lsu.scala 259:50] + assign clkdomain_clock = clock; + assign clkdomain_reset = reset; + assign clkdomain_io_free_clk = io_free_clk; // @[lsu.scala 265:50] + assign clkdomain_io_clk_override = io_clk_override; // @[lsu.scala 266:50] + assign clkdomain_io_dma_dccm_req = io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[lsu.scala 268:50] + assign clkdomain_io_ldst_stbuf_reqvld_r = stbuf_io_ldst_stbuf_reqvld_r; // @[lsu.scala 269:50] + assign clkdomain_io_stbuf_reqvld_any = stbuf_io_stbuf_reqvld_any; // @[lsu.scala 270:50] + assign clkdomain_io_stbuf_reqvld_flushed_any = stbuf_io_stbuf_reqvld_flushed_any; // @[lsu.scala 271:50] + assign clkdomain_io_lsu_busreq_r = bus_intf_io_lsu_busreq_r; // @[lsu.scala 272:50] + assign clkdomain_io_lsu_bus_buffer_pend_any = bus_intf_io_lsu_bus_buffer_pend_any; // @[lsu.scala 273:50] + assign clkdomain_io_lsu_bus_buffer_empty_any = bus_intf_io_lsu_bus_buffer_empty_any; // @[lsu.scala 274:50] + assign clkdomain_io_lsu_stbuf_empty_any = stbuf_io_lsu_stbuf_empty_any; // @[lsu.scala 275:50] + assign clkdomain_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[lsu.scala 276:50] + assign clkdomain_io_lsu_p_valid = io_lsu_p_valid; // @[lsu.scala 277:50] + assign clkdomain_io_lsu_pkt_d_valid = lsu_lsc_ctl_io_lsu_pkt_d_valid; // @[lsu.scala 278:50] + assign clkdomain_io_lsu_pkt_d_bits_store = lsu_lsc_ctl_io_lsu_pkt_d_bits_store; // @[lsu.scala 278:50] + assign clkdomain_io_lsu_pkt_m_valid = lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 279:50] + assign clkdomain_io_lsu_pkt_m_bits_store = lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 279:50] + assign clkdomain_io_lsu_pkt_r_valid = lsu_lsc_ctl_io_lsu_pkt_r_valid; // @[lsu.scala 280:50] + assign clkdomain_io_scan_mode = io_scan_mode; // @[lsu.scala 281:50] + assign bus_intf_clock = clock; + assign bus_intf_reset = reset; + assign bus_intf_io_scan_mode = io_scan_mode; // @[lsu.scala 285:49] + assign bus_intf_io_tlu_busbuff_dec_tlu_external_ldfwd_disable = io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu.scala 286:26] + assign bus_intf_io_tlu_busbuff_dec_tlu_wb_coalescing_disable = io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu.scala 286:26] + assign bus_intf_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable = io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu.scala 286:26] + assign bus_intf_io_lsu_c1_m_clk = clkdomain_io_lsu_c1_m_clk; // @[lsu.scala 287:49] + assign bus_intf_io_lsu_c1_r_clk = clkdomain_io_lsu_c1_r_clk; // @[lsu.scala 288:49] + assign bus_intf_io_lsu_c2_r_clk = clkdomain_io_lsu_c2_r_clk; // @[lsu.scala 289:49] + assign bus_intf_io_lsu_bus_ibuf_c1_clk = clkdomain_io_lsu_bus_ibuf_c1_clk; // @[lsu.scala 290:49] + assign bus_intf_io_lsu_bus_obuf_c1_clk = clkdomain_io_lsu_bus_obuf_c1_clk; // @[lsu.scala 291:49] + assign bus_intf_io_lsu_bus_buf_c1_clk = clkdomain_io_lsu_bus_buf_c1_clk; // @[lsu.scala 292:49] + assign bus_intf_io_lsu_free_c2_clk = clkdomain_io_lsu_free_c2_clk; // @[lsu.scala 293:49] + assign bus_intf_io_free_clk = io_free_clk; // @[lsu.scala 294:49] + assign bus_intf_io_lsu_busm_clk = clkdomain_io_lsu_busm_clk; // @[lsu.scala 295:49] + assign bus_intf_io_axi_aw_ready = io_axi_aw_ready; // @[lsu.scala 314:49] + assign bus_intf_io_axi_w_ready = io_axi_w_ready; // @[lsu.scala 314:49] + assign bus_intf_io_axi_b_valid = io_axi_b_valid; // @[lsu.scala 314:49] + assign bus_intf_io_axi_b_bits_resp = io_axi_b_bits_resp; // @[lsu.scala 314:49] + assign bus_intf_io_axi_b_bits_id = io_axi_b_bits_id; // @[lsu.scala 314:49] + assign bus_intf_io_axi_ar_ready = io_axi_ar_ready; // @[lsu.scala 314:49] + assign bus_intf_io_axi_r_valid = io_axi_r_valid; // @[lsu.scala 314:49] + assign bus_intf_io_axi_r_bits_id = io_axi_r_bits_id; // @[lsu.scala 314:49] + assign bus_intf_io_axi_r_bits_data = io_axi_r_bits_data; // @[lsu.scala 314:49] + assign bus_intf_io_axi_r_bits_resp = io_axi_r_bits_resp; // @[lsu.scala 314:49] + assign bus_intf_io_dec_lsu_valid_raw_d = io_dec_lsu_valid_raw_d; // @[lsu.scala 296:49] + assign bus_intf_io_lsu_busreq_m = _T_39 & _T_40; // @[lsu.scala 297:49] + assign bus_intf_io_lsu_pkt_m_valid = lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 305:49] + assign bus_intf_io_lsu_pkt_m_bits_by = lsu_lsc_ctl_io_lsu_pkt_m_bits_by; // @[lsu.scala 305:49] + assign bus_intf_io_lsu_pkt_m_bits_half = lsu_lsc_ctl_io_lsu_pkt_m_bits_half; // @[lsu.scala 305:49] + assign bus_intf_io_lsu_pkt_m_bits_word = lsu_lsc_ctl_io_lsu_pkt_m_bits_word; // @[lsu.scala 305:49] + assign bus_intf_io_lsu_pkt_m_bits_load = lsu_lsc_ctl_io_lsu_pkt_m_bits_load; // @[lsu.scala 305:49] + assign bus_intf_io_lsu_pkt_r_valid = lsu_lsc_ctl_io_lsu_pkt_r_valid; // @[lsu.scala 306:49] + assign bus_intf_io_lsu_pkt_r_bits_by = lsu_lsc_ctl_io_lsu_pkt_r_bits_by; // @[lsu.scala 306:49] + assign bus_intf_io_lsu_pkt_r_bits_half = lsu_lsc_ctl_io_lsu_pkt_r_bits_half; // @[lsu.scala 306:49] + assign bus_intf_io_lsu_pkt_r_bits_word = lsu_lsc_ctl_io_lsu_pkt_r_bits_word; // @[lsu.scala 306:49] + assign bus_intf_io_lsu_pkt_r_bits_load = lsu_lsc_ctl_io_lsu_pkt_r_bits_load; // @[lsu.scala 306:49] + assign bus_intf_io_lsu_pkt_r_bits_store = lsu_lsc_ctl_io_lsu_pkt_r_bits_store; // @[lsu.scala 306:49] + assign bus_intf_io_lsu_pkt_r_bits_unsign = lsu_lsc_ctl_io_lsu_pkt_r_bits_unsign; // @[lsu.scala 306:49] + assign bus_intf_io_lsu_addr_d = lsu_lsc_ctl_io_lsu_addr_d; // @[lsu.scala 298:49] + assign bus_intf_io_lsu_addr_m = lsu_lsc_ctl_io_lsu_addr_m; // @[lsu.scala 299:49] + assign bus_intf_io_lsu_addr_r = lsu_lsc_ctl_io_lsu_addr_r; // @[lsu.scala 300:49] + assign bus_intf_io_end_addr_d = lsu_lsc_ctl_io_end_addr_d; // @[lsu.scala 301:49] + assign bus_intf_io_end_addr_m = lsu_lsc_ctl_io_end_addr_m; // @[lsu.scala 302:49] + assign bus_intf_io_end_addr_r = lsu_lsc_ctl_io_end_addr_r; // @[lsu.scala 303:49] + assign bus_intf_io_store_data_r = dccm_ctl_io_store_data_r; // @[lsu.scala 304:49] + assign bus_intf_io_dec_tlu_force_halt = io_dec_tlu_force_halt; // @[lsu.scala 307:49] + assign bus_intf_io_lsu_commit_r = lsu_lsc_ctl_io_lsu_commit_r; // @[lsu.scala 308:49] + assign bus_intf_io_is_sideeffects_m = lsu_lsc_ctl_io_is_sideeffects_m; // @[lsu.scala 309:49] + assign bus_intf_io_flush_m_up = io_dec_tlu_flush_lower_r; // @[lsu.scala 310:49] + assign bus_intf_io_flush_r = io_dec_tlu_i0_kill_writeb_r; // @[lsu.scala 311:49] + assign bus_intf_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[lsu.scala 315:49] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + dma_mem_tag_m = _RAND_0[2:0]; + _RAND_1 = {1{`RANDOM}}; + lsu_raw_fwd_hi_r = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + lsu_raw_fwd_lo_r = _RAND_2[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + dma_mem_tag_m = 3'h0; + end + if (reset) begin + lsu_raw_fwd_hi_r = 1'h0; + end + if (reset) begin + lsu_raw_fwd_lo_r = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge clkdomain_io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + dma_mem_tag_m <= 3'h0; + end else begin + dma_mem_tag_m <= io_lsu_dma_dma_mem_tag; + end + end + always @(posedge clkdomain_io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + lsu_raw_fwd_hi_r <= 1'h0; + end else begin + lsu_raw_fwd_hi_r <= |stbuf_io_stbuf_fwdbyteen_hi_m; + end + end + always @(posedge clkdomain_io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + lsu_raw_fwd_lo_r <= 1'h0; + end else begin + lsu_raw_fwd_lo_r <= |stbuf_io_stbuf_fwdbyteen_lo_m; + end + end +endmodule diff --git a/lsu_bus_buffer.anno.json b/lsu_bus_buffer.anno.json new file mode 100644 index 00000000..9fb58c94 --- /dev/null +++ b/lsu_bus_buffer.anno.json @@ -0,0 +1,179 @@ +[ + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_data_valid", + "sources":[ + "~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_data_error" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_bus_buffer|lsu_bus_buffer>io_ld_fwddata_buf_lo", + "sources":[ + "~lsu_bus_buffer|lsu_bus_buffer>io_ldst_byteen_ext_m", + "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_m", + "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_addr_m" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_bus_buffer|lsu_bus_buffer>io_ld_fwddata_buf_hi", + "sources":[ + "~lsu_bus_buffer|lsu_bus_buffer>io_ldst_byteen_ext_m", + "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_m", + "~lsu_bus_buffer|lsu_bus_buffer>io_end_addr_m" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_bus_buffer|lsu_bus_buffer>io_ld_byte_hit_buf_hi", + "sources":[ + "~lsu_bus_buffer|lsu_bus_buffer>io_ldst_byteen_ext_m", + "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_m", + "~lsu_bus_buffer|lsu_bus_buffer>io_end_addr_m" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_pmu_bus_busy", + "sources":[ + "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_ar_valid", + "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_aw_valid", + "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_w_valid", + "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_ar_ready", + "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_aw_ready", + "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_w_ready" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_tag_m", + "sources":[ + "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_r", + "~lsu_bus_buffer|lsu_bus_buffer>io_ldst_dual_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_bus_buffer|lsu_bus_buffer>io_ld_byte_hit_buf_lo", + "sources":[ + "~lsu_bus_buffer|lsu_bus_buffer>io_ldst_byteen_ext_m", + "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_m", + "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_addr_m" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_bus_buffer_full_any", + "sources":[ + "~lsu_bus_buffer|lsu_bus_buffer>io_ldst_dual_d", + "~lsu_bus_buffer|lsu_bus_buffer>io_dec_lsu_valid_raw_d", + "~lsu_bus_buffer|lsu_bus_buffer>io_ldst_dual_m", + "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_m", + "~lsu_bus_buffer|lsu_bus_buffer>io_ldst_dual_r", + "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_valid_m", + "sources":[ + "~lsu_bus_buffer|lsu_bus_buffer>io_ld_full_hit_m", + "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_pkt_m_bits_load", + "~lsu_bus_buffer|lsu_bus_buffer>io_flush_m_up", + "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_m", + "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_pkt_m_valid" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_load_any", + "sources":[ + "~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_data_error", + "~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_store_any", + "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_bus_clk_en_q" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_pmu_bus_misaligned", + "sources":[ + "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_commit_r", + "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_r", + "~lsu_bus_buffer|lsu_bus_buffer>io_ldst_dual_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_pmu_bus_trxn", + "sources":[ + "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_ar_valid", + "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_ar_ready", + "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_aw_valid", + "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_aw_ready", + "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_w_valid", + "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_w_ready" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_addr_any", + "sources":[ + "~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_store_any", + "~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_data_tag", + "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_bus_clk_en_q" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_inv_r", + "sources":[ + "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_commit_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_store_any", + "sources":[ + "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_bus_clk_en_q" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_pmu_bus_error", + "sources":[ + "~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_load_any", + "~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_store_any", + "~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_data_error", + "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_bus_clk_en_q" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_data", + "sources":[ + "~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_data_tag" + ] + }, + { + "class":"firrtl.EmitCircuitAnnotation", + "emitter":"firrtl.VerilogEmitter" + }, + { + "class":"firrtl.transforms.BlackBoxResourceAnno", + "target":"lsu_bus_buffer.gated_latch", + "resourceId":"/vsrc/gated_latch.v" + }, + { + "class":"firrtl.options.TargetDirAnnotation", + "directory":"." + }, + { + "class":"firrtl.options.OutputAnnotationFileAnnotation", + "file":"lsu_bus_buffer" + }, + { + "class":"firrtl.transforms.BlackBoxTargetDirAnno", + "targetDir":"." + } +] \ No newline at end of file diff --git a/lsu_bus_buffer.fir b/lsu_bus_buffer.fir new file mode 100644 index 00000000..456afdd7 --- /dev/null +++ b/lsu_bus_buffer.fir @@ -0,0 +1,6508 @@ +;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 +circuit lsu_bus_buffer : + extmodule gated_latch : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_1 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_1 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_1 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_2 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_2 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_2 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_3 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_3 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_3 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_4 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_4 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_4 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_5 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_5 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_5 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_6 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_6 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_6 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_7 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_7 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_7 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_8 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_8 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_8 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_9 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_9 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_9 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_10 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_10 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_10 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_11 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_11 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_11 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + module lsu_bus_buffer : + input clock : Clock + input reset : AsyncReset + output io : {flip scan_mode : UInt<1>, tlu_busbuff : {lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>}, dctl_busbuff : {lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>}, flip dec_tlu_force_halt : UInt<1>, flip lsu_c2_r_clk : Clock, flip lsu_bus_ibuf_c1_clk : Clock, flip lsu_bus_obuf_c1_clk : Clock, flip lsu_bus_buf_c1_clk : Clock, flip lsu_free_c2_clk : Clock, flip lsu_busm_clk : Clock, flip dec_lsu_valid_raw_d : UInt<1>, flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_addr_m : UInt<32>, flip end_addr_m : UInt<32>, flip lsu_addr_r : UInt<32>, flip end_addr_r : UInt<32>, flip store_data_r : UInt<32>, flip no_word_merge_r : UInt<1>, flip no_dword_merge_r : UInt<1>, flip lsu_busreq_m : UInt<1>, flip ld_full_hit_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, flip lsu_commit_r : UInt<1>, flip is_sideeffects_r : UInt<1>, flip ldst_dual_d : UInt<1>, flip ldst_dual_m : UInt<1>, flip ldst_dual_r : UInt<1>, flip ldst_byteen_ext_m : UInt<8>, lsu_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip lsu_bus_clk_en : UInt<1>, flip lsu_bus_clk_en_q : UInt<1>, lsu_busreq_r : UInt<1>, lsu_bus_buffer_pend_any : UInt<1>, lsu_bus_buffer_full_any : UInt<1>, lsu_bus_buffer_empty_any : UInt<1>, lsu_bus_idle_any : UInt<1>, ld_byte_hit_buf_lo : UInt<4>, ld_byte_hit_buf_hi : UInt<4>, ld_fwddata_buf_lo : UInt<32>, ld_fwddata_buf_hi : UInt<32>} + + wire buf_addr : UInt<32>[4] @[lsu_bus_buffer.scala 67:22] + wire buf_state : UInt<3>[4] @[lsu_bus_buffer.scala 68:23] + wire buf_write : UInt<4> + buf_write <= UInt<1>("h00") + wire CmdPtr0 : UInt<2> + CmdPtr0 <= UInt<1>("h00") + node ldst_byteen_hi_m = bits(io.ldst_byteen_ext_m, 7, 4) @[lsu_bus_buffer.scala 73:46] + node ldst_byteen_lo_m = bits(io.ldst_byteen_ext_m, 3, 0) @[lsu_bus_buffer.scala 74:46] + node _T = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 76:66] + node _T_1 = bits(buf_addr[0], 31, 2) @[lsu_bus_buffer.scala 76:89] + node _T_2 = eq(_T, _T_1) @[lsu_bus_buffer.scala 76:74] + node _T_3 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 76:109] + node _T_4 = and(_T_2, _T_3) @[lsu_bus_buffer.scala 76:98] + node _T_5 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 76:129] + node _T_6 = and(_T_4, _T_5) @[lsu_bus_buffer.scala 76:113] + node ld_addr_hitvec_lo_0 = and(_T_6, io.lsu_busreq_m) @[lsu_bus_buffer.scala 76:141] + node _T_7 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 76:66] + node _T_8 = bits(buf_addr[1], 31, 2) @[lsu_bus_buffer.scala 76:89] + node _T_9 = eq(_T_7, _T_8) @[lsu_bus_buffer.scala 76:74] + node _T_10 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 76:109] + node _T_11 = and(_T_9, _T_10) @[lsu_bus_buffer.scala 76:98] + node _T_12 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 76:129] + node _T_13 = and(_T_11, _T_12) @[lsu_bus_buffer.scala 76:113] + node ld_addr_hitvec_lo_1 = and(_T_13, io.lsu_busreq_m) @[lsu_bus_buffer.scala 76:141] + node _T_14 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 76:66] + node _T_15 = bits(buf_addr[2], 31, 2) @[lsu_bus_buffer.scala 76:89] + node _T_16 = eq(_T_14, _T_15) @[lsu_bus_buffer.scala 76:74] + node _T_17 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 76:109] + node _T_18 = and(_T_16, _T_17) @[lsu_bus_buffer.scala 76:98] + node _T_19 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 76:129] + node _T_20 = and(_T_18, _T_19) @[lsu_bus_buffer.scala 76:113] + node ld_addr_hitvec_lo_2 = and(_T_20, io.lsu_busreq_m) @[lsu_bus_buffer.scala 76:141] + node _T_21 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 76:66] + node _T_22 = bits(buf_addr[3], 31, 2) @[lsu_bus_buffer.scala 76:89] + node _T_23 = eq(_T_21, _T_22) @[lsu_bus_buffer.scala 76:74] + node _T_24 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 76:109] + node _T_25 = and(_T_23, _T_24) @[lsu_bus_buffer.scala 76:98] + node _T_26 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 76:129] + node _T_27 = and(_T_25, _T_26) @[lsu_bus_buffer.scala 76:113] + node ld_addr_hitvec_lo_3 = and(_T_27, io.lsu_busreq_m) @[lsu_bus_buffer.scala 76:141] + node _T_28 = bits(io.end_addr_m, 31, 2) @[lsu_bus_buffer.scala 77:66] + node _T_29 = bits(buf_addr[0], 31, 2) @[lsu_bus_buffer.scala 77:89] + node _T_30 = eq(_T_28, _T_29) @[lsu_bus_buffer.scala 77:74] + node _T_31 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 77:109] + node _T_32 = and(_T_30, _T_31) @[lsu_bus_buffer.scala 77:98] + node _T_33 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 77:129] + node _T_34 = and(_T_32, _T_33) @[lsu_bus_buffer.scala 77:113] + node ld_addr_hitvec_hi_0 = and(_T_34, io.lsu_busreq_m) @[lsu_bus_buffer.scala 77:141] + node _T_35 = bits(io.end_addr_m, 31, 2) @[lsu_bus_buffer.scala 77:66] + node _T_36 = bits(buf_addr[1], 31, 2) @[lsu_bus_buffer.scala 77:89] + node _T_37 = eq(_T_35, _T_36) @[lsu_bus_buffer.scala 77:74] + node _T_38 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 77:109] + node _T_39 = and(_T_37, _T_38) @[lsu_bus_buffer.scala 77:98] + node _T_40 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 77:129] + node _T_41 = and(_T_39, _T_40) @[lsu_bus_buffer.scala 77:113] + node ld_addr_hitvec_hi_1 = and(_T_41, io.lsu_busreq_m) @[lsu_bus_buffer.scala 77:141] + node _T_42 = bits(io.end_addr_m, 31, 2) @[lsu_bus_buffer.scala 77:66] + node _T_43 = bits(buf_addr[2], 31, 2) @[lsu_bus_buffer.scala 77:89] + node _T_44 = eq(_T_42, _T_43) @[lsu_bus_buffer.scala 77:74] + node _T_45 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 77:109] + node _T_46 = and(_T_44, _T_45) @[lsu_bus_buffer.scala 77:98] + node _T_47 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 77:129] + node _T_48 = and(_T_46, _T_47) @[lsu_bus_buffer.scala 77:113] + node ld_addr_hitvec_hi_2 = and(_T_48, io.lsu_busreq_m) @[lsu_bus_buffer.scala 77:141] + node _T_49 = bits(io.end_addr_m, 31, 2) @[lsu_bus_buffer.scala 77:66] + node _T_50 = bits(buf_addr[3], 31, 2) @[lsu_bus_buffer.scala 77:89] + node _T_51 = eq(_T_49, _T_50) @[lsu_bus_buffer.scala 77:74] + node _T_52 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 77:109] + node _T_53 = and(_T_51, _T_52) @[lsu_bus_buffer.scala 77:98] + node _T_54 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 77:129] + node _T_55 = and(_T_53, _T_54) @[lsu_bus_buffer.scala 77:113] + node ld_addr_hitvec_hi_3 = and(_T_55, io.lsu_busreq_m) @[lsu_bus_buffer.scala 77:141] + wire ld_byte_hitvecfn_lo : UInt<4>[4] @[lsu_bus_buffer.scala 78:33] + wire ld_byte_ibuf_hit_lo : UInt<4> + ld_byte_ibuf_hit_lo <= UInt<1>("h00") + wire ld_byte_hitvecfn_hi : UInt<4>[4] @[lsu_bus_buffer.scala 80:33] + wire ld_byte_ibuf_hit_hi : UInt<4> + ld_byte_ibuf_hit_hi <= UInt<1>("h00") + wire buf_byteen : UInt<4>[4] @[lsu_bus_buffer.scala 82:24] + buf_byteen[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 83:14] + buf_byteen[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 83:14] + buf_byteen[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 83:14] + buf_byteen[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 83:14] + wire buf_nxtstate : UInt<3>[4] @[lsu_bus_buffer.scala 84:26] + buf_nxtstate[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 85:16] + buf_nxtstate[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 85:16] + buf_nxtstate[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 85:16] + buf_nxtstate[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 85:16] + wire buf_wr_en : UInt<1>[4] @[lsu_bus_buffer.scala 86:23] + buf_wr_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 87:13] + buf_wr_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 87:13] + buf_wr_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 87:13] + buf_wr_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 87:13] + wire buf_data_en : UInt<1>[4] @[lsu_bus_buffer.scala 88:25] + buf_data_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 89:15] + buf_data_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 89:15] + buf_data_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 89:15] + buf_data_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 89:15] + wire buf_state_bus_en : UInt<1>[4] @[lsu_bus_buffer.scala 90:30] + buf_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 91:20] + buf_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 91:20] + buf_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 91:20] + buf_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 91:20] + wire buf_ldfwd_in : UInt<1>[4] @[lsu_bus_buffer.scala 92:26] + buf_ldfwd_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 93:16] + buf_ldfwd_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 93:16] + buf_ldfwd_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 93:16] + buf_ldfwd_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 93:16] + wire buf_ldfwd_en : UInt<1>[4] @[lsu_bus_buffer.scala 94:26] + buf_ldfwd_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 95:16] + buf_ldfwd_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 95:16] + buf_ldfwd_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 95:16] + buf_ldfwd_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 95:16] + wire buf_data_in : UInt<32>[4] @[lsu_bus_buffer.scala 96:25] + buf_data_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 97:15] + buf_data_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 97:15] + buf_data_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 97:15] + buf_data_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 97:15] + wire buf_ldfwdtag_in : UInt<2>[4] @[lsu_bus_buffer.scala 98:29] + buf_ldfwdtag_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 99:19] + buf_ldfwdtag_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 99:19] + buf_ldfwdtag_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 99:19] + buf_ldfwdtag_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 99:19] + wire buf_error_en : UInt<1>[4] @[lsu_bus_buffer.scala 100:26] + buf_error_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 101:16] + buf_error_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 101:16] + buf_error_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 101:16] + buf_error_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 101:16] + wire bus_rsp_read_error : UInt<1> + bus_rsp_read_error <= UInt<1>("h00") + wire bus_rsp_rdata : UInt<64> + bus_rsp_rdata <= UInt<1>("h00") + wire bus_rsp_write_error : UInt<1> + bus_rsp_write_error <= UInt<1>("h00") + wire buf_dualtag : UInt<2>[4] @[lsu_bus_buffer.scala 105:25] + buf_dualtag[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 106:15] + buf_dualtag[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 106:15] + buf_dualtag[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 106:15] + buf_dualtag[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 106:15] + wire buf_ldfwd : UInt<4> + buf_ldfwd <= UInt<1>("h00") + wire buf_resp_state_bus_en : UInt<1>[4] @[lsu_bus_buffer.scala 108:35] + buf_resp_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 109:25] + buf_resp_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 109:25] + buf_resp_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 109:25] + buf_resp_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 109:25] + wire any_done_wait_state : UInt<1> + any_done_wait_state <= UInt<1>("h00") + wire bus_rsp_write : UInt<1> + bus_rsp_write <= UInt<1>("h00") + wire bus_rsp_write_tag : UInt<3> + bus_rsp_write_tag <= UInt<1>("h00") + wire buf_ldfwdtag : UInt<2>[4] @[lsu_bus_buffer.scala 113:26] + buf_ldfwdtag[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 114:16] + buf_ldfwdtag[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 114:16] + buf_ldfwdtag[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 114:16] + buf_ldfwdtag[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 114:16] + wire buf_rst : UInt<1>[4] @[lsu_bus_buffer.scala 115:21] + buf_rst[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 116:11] + buf_rst[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 116:11] + buf_rst[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 116:11] + buf_rst[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 116:11] + wire ibuf_drainvec_vld : UInt<4> + ibuf_drainvec_vld <= UInt<1>("h00") + wire buf_byteen_in : UInt<4>[4] @[lsu_bus_buffer.scala 118:27] + buf_byteen_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 119:17] + buf_byteen_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 119:17] + buf_byteen_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 119:17] + buf_byteen_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 119:17] + wire buf_addr_in : UInt<32>[4] @[lsu_bus_buffer.scala 120:25] + buf_addr_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 121:15] + buf_addr_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 121:15] + buf_addr_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 121:15] + buf_addr_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 121:15] + wire buf_dual_in : UInt<4> + buf_dual_in <= UInt<1>("h00") + wire buf_samedw_in : UInt<4> + buf_samedw_in <= UInt<1>("h00") + wire buf_nomerge_in : UInt<4> + buf_nomerge_in <= UInt<1>("h00") + wire buf_dualhi_in : UInt<4> + buf_dualhi_in <= UInt<1>("h00") + wire buf_dualtag_in : UInt<2>[4] @[lsu_bus_buffer.scala 126:28] + buf_dualtag_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 127:18] + buf_dualtag_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 127:18] + buf_dualtag_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 127:18] + buf_dualtag_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 127:18] + wire buf_sideeffect_in : UInt<4> + buf_sideeffect_in <= UInt<1>("h00") + wire buf_unsign_in : UInt<4> + buf_unsign_in <= UInt<1>("h00") + wire buf_sz_in : UInt<2>[4] @[lsu_bus_buffer.scala 130:23] + buf_sz_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 131:13] + buf_sz_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 131:13] + buf_sz_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 131:13] + buf_sz_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 131:13] + wire buf_write_in : UInt<4> + buf_write_in <= UInt<1>("h00") + wire buf_unsign : UInt<4> + buf_unsign <= UInt<1>("h00") + wire buf_error : UInt<4> + buf_error <= UInt<1>("h00") + wire CmdPtr1 : UInt<2> + CmdPtr1 <= UInt<1>("h00") + wire ibuf_data : UInt<32> + ibuf_data <= UInt<1>("h00") + node _T_56 = orr(ld_byte_hitvecfn_lo[0]) @[lsu_bus_buffer.scala 138:73] + node _T_57 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[lsu_bus_buffer.scala 138:98] + node _T_58 = or(_T_56, _T_57) @[lsu_bus_buffer.scala 138:77] + node _T_59 = orr(ld_byte_hitvecfn_lo[1]) @[lsu_bus_buffer.scala 138:73] + node _T_60 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[lsu_bus_buffer.scala 138:98] + node _T_61 = or(_T_59, _T_60) @[lsu_bus_buffer.scala 138:77] + node _T_62 = orr(ld_byte_hitvecfn_lo[2]) @[lsu_bus_buffer.scala 138:73] + node _T_63 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[lsu_bus_buffer.scala 138:98] + node _T_64 = or(_T_62, _T_63) @[lsu_bus_buffer.scala 138:77] + node _T_65 = orr(ld_byte_hitvecfn_lo[3]) @[lsu_bus_buffer.scala 138:73] + node _T_66 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[lsu_bus_buffer.scala 138:98] + node _T_67 = or(_T_65, _T_66) @[lsu_bus_buffer.scala 138:77] + node _T_68 = cat(_T_67, _T_64) @[Cat.scala 29:58] + node _T_69 = cat(_T_68, _T_61) @[Cat.scala 29:58] + node _T_70 = cat(_T_69, _T_58) @[Cat.scala 29:58] + io.ld_byte_hit_buf_lo <= _T_70 @[lsu_bus_buffer.scala 138:25] + node _T_71 = orr(ld_byte_hitvecfn_hi[0]) @[lsu_bus_buffer.scala 139:73] + node _T_72 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[lsu_bus_buffer.scala 139:98] + node _T_73 = or(_T_71, _T_72) @[lsu_bus_buffer.scala 139:77] + node _T_74 = orr(ld_byte_hitvecfn_hi[1]) @[lsu_bus_buffer.scala 139:73] + node _T_75 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[lsu_bus_buffer.scala 139:98] + node _T_76 = or(_T_74, _T_75) @[lsu_bus_buffer.scala 139:77] + node _T_77 = orr(ld_byte_hitvecfn_hi[2]) @[lsu_bus_buffer.scala 139:73] + node _T_78 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[lsu_bus_buffer.scala 139:98] + node _T_79 = or(_T_77, _T_78) @[lsu_bus_buffer.scala 139:77] + node _T_80 = orr(ld_byte_hitvecfn_hi[3]) @[lsu_bus_buffer.scala 139:73] + node _T_81 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[lsu_bus_buffer.scala 139:98] + node _T_82 = or(_T_80, _T_81) @[lsu_bus_buffer.scala 139:77] + node _T_83 = cat(_T_82, _T_79) @[Cat.scala 29:58] + node _T_84 = cat(_T_83, _T_76) @[Cat.scala 29:58] + node _T_85 = cat(_T_84, _T_73) @[Cat.scala 29:58] + io.ld_byte_hit_buf_hi <= _T_85 @[lsu_bus_buffer.scala 139:25] + node _T_86 = bits(buf_byteen[0], 0, 0) @[lsu_bus_buffer.scala 141:110] + node _T_87 = and(ld_addr_hitvec_lo_0, _T_86) @[lsu_bus_buffer.scala 141:95] + node _T_88 = bits(ldst_byteen_lo_m, 0, 0) @[lsu_bus_buffer.scala 141:132] + node _T_89 = and(_T_87, _T_88) @[lsu_bus_buffer.scala 141:114] + node _T_90 = bits(buf_byteen[1], 0, 0) @[lsu_bus_buffer.scala 141:110] + node _T_91 = and(ld_addr_hitvec_lo_1, _T_90) @[lsu_bus_buffer.scala 141:95] + node _T_92 = bits(ldst_byteen_lo_m, 0, 0) @[lsu_bus_buffer.scala 141:132] + node _T_93 = and(_T_91, _T_92) @[lsu_bus_buffer.scala 141:114] + node _T_94 = bits(buf_byteen[2], 0, 0) @[lsu_bus_buffer.scala 141:110] + node _T_95 = and(ld_addr_hitvec_lo_2, _T_94) @[lsu_bus_buffer.scala 141:95] + node _T_96 = bits(ldst_byteen_lo_m, 0, 0) @[lsu_bus_buffer.scala 141:132] + node _T_97 = and(_T_95, _T_96) @[lsu_bus_buffer.scala 141:114] + node _T_98 = bits(buf_byteen[3], 0, 0) @[lsu_bus_buffer.scala 141:110] + node _T_99 = and(ld_addr_hitvec_lo_3, _T_98) @[lsu_bus_buffer.scala 141:95] + node _T_100 = bits(ldst_byteen_lo_m, 0, 0) @[lsu_bus_buffer.scala 141:132] + node _T_101 = and(_T_99, _T_100) @[lsu_bus_buffer.scala 141:114] + node _T_102 = cat(_T_101, _T_97) @[Cat.scala 29:58] + node _T_103 = cat(_T_102, _T_93) @[Cat.scala 29:58] + node ld_byte_hitvec_lo_0 = cat(_T_103, _T_89) @[Cat.scala 29:58] + node _T_104 = bits(buf_byteen[0], 1, 1) @[lsu_bus_buffer.scala 141:110] + node _T_105 = and(ld_addr_hitvec_lo_0, _T_104) @[lsu_bus_buffer.scala 141:95] + node _T_106 = bits(ldst_byteen_lo_m, 1, 1) @[lsu_bus_buffer.scala 141:132] + node _T_107 = and(_T_105, _T_106) @[lsu_bus_buffer.scala 141:114] + node _T_108 = bits(buf_byteen[1], 1, 1) @[lsu_bus_buffer.scala 141:110] + node _T_109 = and(ld_addr_hitvec_lo_1, _T_108) @[lsu_bus_buffer.scala 141:95] + node _T_110 = bits(ldst_byteen_lo_m, 1, 1) @[lsu_bus_buffer.scala 141:132] + node _T_111 = and(_T_109, _T_110) @[lsu_bus_buffer.scala 141:114] + node _T_112 = bits(buf_byteen[2], 1, 1) @[lsu_bus_buffer.scala 141:110] + node _T_113 = and(ld_addr_hitvec_lo_2, _T_112) @[lsu_bus_buffer.scala 141:95] + node _T_114 = bits(ldst_byteen_lo_m, 1, 1) @[lsu_bus_buffer.scala 141:132] + node _T_115 = and(_T_113, _T_114) @[lsu_bus_buffer.scala 141:114] + node _T_116 = bits(buf_byteen[3], 1, 1) @[lsu_bus_buffer.scala 141:110] + node _T_117 = and(ld_addr_hitvec_lo_3, _T_116) @[lsu_bus_buffer.scala 141:95] + node _T_118 = bits(ldst_byteen_lo_m, 1, 1) @[lsu_bus_buffer.scala 141:132] + node _T_119 = and(_T_117, _T_118) @[lsu_bus_buffer.scala 141:114] + node _T_120 = cat(_T_119, _T_115) @[Cat.scala 29:58] + node _T_121 = cat(_T_120, _T_111) @[Cat.scala 29:58] + node ld_byte_hitvec_lo_1 = cat(_T_121, _T_107) @[Cat.scala 29:58] + node _T_122 = bits(buf_byteen[0], 2, 2) @[lsu_bus_buffer.scala 141:110] + node _T_123 = and(ld_addr_hitvec_lo_0, _T_122) @[lsu_bus_buffer.scala 141:95] + node _T_124 = bits(ldst_byteen_lo_m, 2, 2) @[lsu_bus_buffer.scala 141:132] + node _T_125 = and(_T_123, _T_124) @[lsu_bus_buffer.scala 141:114] + node _T_126 = bits(buf_byteen[1], 2, 2) @[lsu_bus_buffer.scala 141:110] + node _T_127 = and(ld_addr_hitvec_lo_1, _T_126) @[lsu_bus_buffer.scala 141:95] + node _T_128 = bits(ldst_byteen_lo_m, 2, 2) @[lsu_bus_buffer.scala 141:132] + node _T_129 = and(_T_127, _T_128) @[lsu_bus_buffer.scala 141:114] + node _T_130 = bits(buf_byteen[2], 2, 2) @[lsu_bus_buffer.scala 141:110] + node _T_131 = and(ld_addr_hitvec_lo_2, _T_130) @[lsu_bus_buffer.scala 141:95] + node _T_132 = bits(ldst_byteen_lo_m, 2, 2) @[lsu_bus_buffer.scala 141:132] + node _T_133 = and(_T_131, _T_132) @[lsu_bus_buffer.scala 141:114] + node _T_134 = bits(buf_byteen[3], 2, 2) @[lsu_bus_buffer.scala 141:110] + node _T_135 = and(ld_addr_hitvec_lo_3, _T_134) @[lsu_bus_buffer.scala 141:95] + node _T_136 = bits(ldst_byteen_lo_m, 2, 2) @[lsu_bus_buffer.scala 141:132] + node _T_137 = and(_T_135, _T_136) @[lsu_bus_buffer.scala 141:114] + node _T_138 = cat(_T_137, _T_133) @[Cat.scala 29:58] + node _T_139 = cat(_T_138, _T_129) @[Cat.scala 29:58] + node ld_byte_hitvec_lo_2 = cat(_T_139, _T_125) @[Cat.scala 29:58] + node _T_140 = bits(buf_byteen[0], 3, 3) @[lsu_bus_buffer.scala 141:110] + node _T_141 = and(ld_addr_hitvec_lo_0, _T_140) @[lsu_bus_buffer.scala 141:95] + node _T_142 = bits(ldst_byteen_lo_m, 3, 3) @[lsu_bus_buffer.scala 141:132] + node _T_143 = and(_T_141, _T_142) @[lsu_bus_buffer.scala 141:114] + node _T_144 = bits(buf_byteen[1], 3, 3) @[lsu_bus_buffer.scala 141:110] + node _T_145 = and(ld_addr_hitvec_lo_1, _T_144) @[lsu_bus_buffer.scala 141:95] + node _T_146 = bits(ldst_byteen_lo_m, 3, 3) @[lsu_bus_buffer.scala 141:132] + node _T_147 = and(_T_145, _T_146) @[lsu_bus_buffer.scala 141:114] + node _T_148 = bits(buf_byteen[2], 3, 3) @[lsu_bus_buffer.scala 141:110] + node _T_149 = and(ld_addr_hitvec_lo_2, _T_148) @[lsu_bus_buffer.scala 141:95] + node _T_150 = bits(ldst_byteen_lo_m, 3, 3) @[lsu_bus_buffer.scala 141:132] + node _T_151 = and(_T_149, _T_150) @[lsu_bus_buffer.scala 141:114] + node _T_152 = bits(buf_byteen[3], 3, 3) @[lsu_bus_buffer.scala 141:110] + node _T_153 = and(ld_addr_hitvec_lo_3, _T_152) @[lsu_bus_buffer.scala 141:95] + node _T_154 = bits(ldst_byteen_lo_m, 3, 3) @[lsu_bus_buffer.scala 141:132] + node _T_155 = and(_T_153, _T_154) @[lsu_bus_buffer.scala 141:114] + node _T_156 = cat(_T_155, _T_151) @[Cat.scala 29:58] + node _T_157 = cat(_T_156, _T_147) @[Cat.scala 29:58] + node ld_byte_hitvec_lo_3 = cat(_T_157, _T_143) @[Cat.scala 29:58] + node _T_158 = bits(buf_byteen[0], 0, 0) @[lsu_bus_buffer.scala 142:110] + node _T_159 = and(ld_addr_hitvec_hi_0, _T_158) @[lsu_bus_buffer.scala 142:95] + node _T_160 = bits(ldst_byteen_hi_m, 0, 0) @[lsu_bus_buffer.scala 142:132] + node _T_161 = and(_T_159, _T_160) @[lsu_bus_buffer.scala 142:114] + node _T_162 = bits(buf_byteen[1], 0, 0) @[lsu_bus_buffer.scala 142:110] + node _T_163 = and(ld_addr_hitvec_hi_1, _T_162) @[lsu_bus_buffer.scala 142:95] + node _T_164 = bits(ldst_byteen_hi_m, 0, 0) @[lsu_bus_buffer.scala 142:132] + node _T_165 = and(_T_163, _T_164) @[lsu_bus_buffer.scala 142:114] + node _T_166 = bits(buf_byteen[2], 0, 0) @[lsu_bus_buffer.scala 142:110] + node _T_167 = and(ld_addr_hitvec_hi_2, _T_166) @[lsu_bus_buffer.scala 142:95] + node _T_168 = bits(ldst_byteen_hi_m, 0, 0) @[lsu_bus_buffer.scala 142:132] + node _T_169 = and(_T_167, _T_168) @[lsu_bus_buffer.scala 142:114] + node _T_170 = bits(buf_byteen[3], 0, 0) @[lsu_bus_buffer.scala 142:110] + node _T_171 = and(ld_addr_hitvec_hi_3, _T_170) @[lsu_bus_buffer.scala 142:95] + node _T_172 = bits(ldst_byteen_hi_m, 0, 0) @[lsu_bus_buffer.scala 142:132] + node _T_173 = and(_T_171, _T_172) @[lsu_bus_buffer.scala 142:114] + node _T_174 = cat(_T_173, _T_169) @[Cat.scala 29:58] + node _T_175 = cat(_T_174, _T_165) @[Cat.scala 29:58] + node ld_byte_hitvec_hi_0 = cat(_T_175, _T_161) @[Cat.scala 29:58] + node _T_176 = bits(buf_byteen[0], 1, 1) @[lsu_bus_buffer.scala 142:110] + node _T_177 = and(ld_addr_hitvec_hi_0, _T_176) @[lsu_bus_buffer.scala 142:95] + node _T_178 = bits(ldst_byteen_hi_m, 1, 1) @[lsu_bus_buffer.scala 142:132] + node _T_179 = and(_T_177, _T_178) @[lsu_bus_buffer.scala 142:114] + node _T_180 = bits(buf_byteen[1], 1, 1) @[lsu_bus_buffer.scala 142:110] + node _T_181 = and(ld_addr_hitvec_hi_1, _T_180) @[lsu_bus_buffer.scala 142:95] + node _T_182 = bits(ldst_byteen_hi_m, 1, 1) @[lsu_bus_buffer.scala 142:132] + node _T_183 = and(_T_181, _T_182) @[lsu_bus_buffer.scala 142:114] + node _T_184 = bits(buf_byteen[2], 1, 1) @[lsu_bus_buffer.scala 142:110] + node _T_185 = and(ld_addr_hitvec_hi_2, _T_184) @[lsu_bus_buffer.scala 142:95] + node _T_186 = bits(ldst_byteen_hi_m, 1, 1) @[lsu_bus_buffer.scala 142:132] + node _T_187 = and(_T_185, _T_186) @[lsu_bus_buffer.scala 142:114] + node _T_188 = bits(buf_byteen[3], 1, 1) @[lsu_bus_buffer.scala 142:110] + node _T_189 = and(ld_addr_hitvec_hi_3, _T_188) @[lsu_bus_buffer.scala 142:95] + node _T_190 = bits(ldst_byteen_hi_m, 1, 1) @[lsu_bus_buffer.scala 142:132] + node _T_191 = and(_T_189, _T_190) @[lsu_bus_buffer.scala 142:114] + node _T_192 = cat(_T_191, _T_187) @[Cat.scala 29:58] + node _T_193 = cat(_T_192, _T_183) @[Cat.scala 29:58] + node ld_byte_hitvec_hi_1 = cat(_T_193, _T_179) @[Cat.scala 29:58] + node _T_194 = bits(buf_byteen[0], 2, 2) @[lsu_bus_buffer.scala 142:110] + node _T_195 = and(ld_addr_hitvec_hi_0, _T_194) @[lsu_bus_buffer.scala 142:95] + node _T_196 = bits(ldst_byteen_hi_m, 2, 2) @[lsu_bus_buffer.scala 142:132] + node _T_197 = and(_T_195, _T_196) @[lsu_bus_buffer.scala 142:114] + node _T_198 = bits(buf_byteen[1], 2, 2) @[lsu_bus_buffer.scala 142:110] + node _T_199 = and(ld_addr_hitvec_hi_1, _T_198) @[lsu_bus_buffer.scala 142:95] + node _T_200 = bits(ldst_byteen_hi_m, 2, 2) @[lsu_bus_buffer.scala 142:132] + node _T_201 = and(_T_199, _T_200) @[lsu_bus_buffer.scala 142:114] + node _T_202 = bits(buf_byteen[2], 2, 2) @[lsu_bus_buffer.scala 142:110] + node _T_203 = and(ld_addr_hitvec_hi_2, _T_202) @[lsu_bus_buffer.scala 142:95] + node _T_204 = bits(ldst_byteen_hi_m, 2, 2) @[lsu_bus_buffer.scala 142:132] + node _T_205 = and(_T_203, _T_204) @[lsu_bus_buffer.scala 142:114] + node _T_206 = bits(buf_byteen[3], 2, 2) @[lsu_bus_buffer.scala 142:110] + node _T_207 = and(ld_addr_hitvec_hi_3, _T_206) @[lsu_bus_buffer.scala 142:95] + node _T_208 = bits(ldst_byteen_hi_m, 2, 2) @[lsu_bus_buffer.scala 142:132] + node _T_209 = and(_T_207, _T_208) @[lsu_bus_buffer.scala 142:114] + node _T_210 = cat(_T_209, _T_205) @[Cat.scala 29:58] + node _T_211 = cat(_T_210, _T_201) @[Cat.scala 29:58] + node ld_byte_hitvec_hi_2 = cat(_T_211, _T_197) @[Cat.scala 29:58] + node _T_212 = bits(buf_byteen[0], 3, 3) @[lsu_bus_buffer.scala 142:110] + node _T_213 = and(ld_addr_hitvec_hi_0, _T_212) @[lsu_bus_buffer.scala 142:95] + node _T_214 = bits(ldst_byteen_hi_m, 3, 3) @[lsu_bus_buffer.scala 142:132] + node _T_215 = and(_T_213, _T_214) @[lsu_bus_buffer.scala 142:114] + node _T_216 = bits(buf_byteen[1], 3, 3) @[lsu_bus_buffer.scala 142:110] + node _T_217 = and(ld_addr_hitvec_hi_1, _T_216) @[lsu_bus_buffer.scala 142:95] + node _T_218 = bits(ldst_byteen_hi_m, 3, 3) @[lsu_bus_buffer.scala 142:132] + node _T_219 = and(_T_217, _T_218) @[lsu_bus_buffer.scala 142:114] + node _T_220 = bits(buf_byteen[2], 3, 3) @[lsu_bus_buffer.scala 142:110] + node _T_221 = and(ld_addr_hitvec_hi_2, _T_220) @[lsu_bus_buffer.scala 142:95] + node _T_222 = bits(ldst_byteen_hi_m, 3, 3) @[lsu_bus_buffer.scala 142:132] + node _T_223 = and(_T_221, _T_222) @[lsu_bus_buffer.scala 142:114] + node _T_224 = bits(buf_byteen[3], 3, 3) @[lsu_bus_buffer.scala 142:110] + node _T_225 = and(ld_addr_hitvec_hi_3, _T_224) @[lsu_bus_buffer.scala 142:95] + node _T_226 = bits(ldst_byteen_hi_m, 3, 3) @[lsu_bus_buffer.scala 142:132] + node _T_227 = and(_T_225, _T_226) @[lsu_bus_buffer.scala 142:114] + node _T_228 = cat(_T_227, _T_223) @[Cat.scala 29:58] + node _T_229 = cat(_T_228, _T_219) @[Cat.scala 29:58] + node ld_byte_hitvec_hi_3 = cat(_T_229, _T_215) @[Cat.scala 29:58] + wire buf_age_younger : UInt<4>[4] @[lsu_bus_buffer.scala 144:29] + buf_age_younger[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 145:19] + buf_age_younger[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 145:19] + buf_age_younger[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 145:19] + buf_age_younger[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 145:19] + node _T_230 = bits(ld_byte_hitvec_lo_0, 0, 0) @[lsu_bus_buffer.scala 146:93] + node _T_231 = and(ld_byte_hitvec_lo_0, buf_age_younger[0]) @[lsu_bus_buffer.scala 146:122] + node _T_232 = orr(_T_231) @[lsu_bus_buffer.scala 146:144] + node _T_233 = eq(_T_232, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] + node _T_234 = and(_T_230, _T_233) @[lsu_bus_buffer.scala 146:97] + node _T_235 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[lsu_bus_buffer.scala 146:170] + node _T_236 = eq(_T_235, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] + node _T_237 = and(_T_234, _T_236) @[lsu_bus_buffer.scala 146:148] + node _T_238 = bits(ld_byte_hitvec_lo_0, 1, 1) @[lsu_bus_buffer.scala 146:93] + node _T_239 = and(ld_byte_hitvec_lo_0, buf_age_younger[1]) @[lsu_bus_buffer.scala 146:122] + node _T_240 = orr(_T_239) @[lsu_bus_buffer.scala 146:144] + node _T_241 = eq(_T_240, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] + node _T_242 = and(_T_238, _T_241) @[lsu_bus_buffer.scala 146:97] + node _T_243 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[lsu_bus_buffer.scala 146:170] + node _T_244 = eq(_T_243, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] + node _T_245 = and(_T_242, _T_244) @[lsu_bus_buffer.scala 146:148] + node _T_246 = bits(ld_byte_hitvec_lo_0, 2, 2) @[lsu_bus_buffer.scala 146:93] + node _T_247 = and(ld_byte_hitvec_lo_0, buf_age_younger[2]) @[lsu_bus_buffer.scala 146:122] + node _T_248 = orr(_T_247) @[lsu_bus_buffer.scala 146:144] + node _T_249 = eq(_T_248, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] + node _T_250 = and(_T_246, _T_249) @[lsu_bus_buffer.scala 146:97] + node _T_251 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[lsu_bus_buffer.scala 146:170] + node _T_252 = eq(_T_251, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] + node _T_253 = and(_T_250, _T_252) @[lsu_bus_buffer.scala 146:148] + node _T_254 = bits(ld_byte_hitvec_lo_0, 3, 3) @[lsu_bus_buffer.scala 146:93] + node _T_255 = and(ld_byte_hitvec_lo_0, buf_age_younger[3]) @[lsu_bus_buffer.scala 146:122] + node _T_256 = orr(_T_255) @[lsu_bus_buffer.scala 146:144] + node _T_257 = eq(_T_256, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] + node _T_258 = and(_T_254, _T_257) @[lsu_bus_buffer.scala 146:97] + node _T_259 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[lsu_bus_buffer.scala 146:170] + node _T_260 = eq(_T_259, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] + node _T_261 = and(_T_258, _T_260) @[lsu_bus_buffer.scala 146:148] + node _T_262 = cat(_T_261, _T_253) @[Cat.scala 29:58] + node _T_263 = cat(_T_262, _T_245) @[Cat.scala 29:58] + node _T_264 = cat(_T_263, _T_237) @[Cat.scala 29:58] + node _T_265 = bits(ld_byte_hitvec_lo_1, 0, 0) @[lsu_bus_buffer.scala 146:93] + node _T_266 = and(ld_byte_hitvec_lo_1, buf_age_younger[0]) @[lsu_bus_buffer.scala 146:122] + node _T_267 = orr(_T_266) @[lsu_bus_buffer.scala 146:144] + node _T_268 = eq(_T_267, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] + node _T_269 = and(_T_265, _T_268) @[lsu_bus_buffer.scala 146:97] + node _T_270 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[lsu_bus_buffer.scala 146:170] + node _T_271 = eq(_T_270, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] + node _T_272 = and(_T_269, _T_271) @[lsu_bus_buffer.scala 146:148] + node _T_273 = bits(ld_byte_hitvec_lo_1, 1, 1) @[lsu_bus_buffer.scala 146:93] + node _T_274 = and(ld_byte_hitvec_lo_1, buf_age_younger[1]) @[lsu_bus_buffer.scala 146:122] + node _T_275 = orr(_T_274) @[lsu_bus_buffer.scala 146:144] + node _T_276 = eq(_T_275, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] + node _T_277 = and(_T_273, _T_276) @[lsu_bus_buffer.scala 146:97] + node _T_278 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[lsu_bus_buffer.scala 146:170] + node _T_279 = eq(_T_278, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] + node _T_280 = and(_T_277, _T_279) @[lsu_bus_buffer.scala 146:148] + node _T_281 = bits(ld_byte_hitvec_lo_1, 2, 2) @[lsu_bus_buffer.scala 146:93] + node _T_282 = and(ld_byte_hitvec_lo_1, buf_age_younger[2]) @[lsu_bus_buffer.scala 146:122] + node _T_283 = orr(_T_282) @[lsu_bus_buffer.scala 146:144] + node _T_284 = eq(_T_283, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] + node _T_285 = and(_T_281, _T_284) @[lsu_bus_buffer.scala 146:97] + node _T_286 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[lsu_bus_buffer.scala 146:170] + node _T_287 = eq(_T_286, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] + node _T_288 = and(_T_285, _T_287) @[lsu_bus_buffer.scala 146:148] + node _T_289 = bits(ld_byte_hitvec_lo_1, 3, 3) @[lsu_bus_buffer.scala 146:93] + node _T_290 = and(ld_byte_hitvec_lo_1, buf_age_younger[3]) @[lsu_bus_buffer.scala 146:122] + node _T_291 = orr(_T_290) @[lsu_bus_buffer.scala 146:144] + node _T_292 = eq(_T_291, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] + node _T_293 = and(_T_289, _T_292) @[lsu_bus_buffer.scala 146:97] + node _T_294 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[lsu_bus_buffer.scala 146:170] + node _T_295 = eq(_T_294, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] + node _T_296 = and(_T_293, _T_295) @[lsu_bus_buffer.scala 146:148] + node _T_297 = cat(_T_296, _T_288) @[Cat.scala 29:58] + node _T_298 = cat(_T_297, _T_280) @[Cat.scala 29:58] + node _T_299 = cat(_T_298, _T_272) @[Cat.scala 29:58] + node _T_300 = bits(ld_byte_hitvec_lo_2, 0, 0) @[lsu_bus_buffer.scala 146:93] + node _T_301 = and(ld_byte_hitvec_lo_2, buf_age_younger[0]) @[lsu_bus_buffer.scala 146:122] + node _T_302 = orr(_T_301) @[lsu_bus_buffer.scala 146:144] + node _T_303 = eq(_T_302, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] + node _T_304 = and(_T_300, _T_303) @[lsu_bus_buffer.scala 146:97] + node _T_305 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[lsu_bus_buffer.scala 146:170] + node _T_306 = eq(_T_305, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] + node _T_307 = and(_T_304, _T_306) @[lsu_bus_buffer.scala 146:148] + node _T_308 = bits(ld_byte_hitvec_lo_2, 1, 1) @[lsu_bus_buffer.scala 146:93] + node _T_309 = and(ld_byte_hitvec_lo_2, buf_age_younger[1]) @[lsu_bus_buffer.scala 146:122] + node _T_310 = orr(_T_309) @[lsu_bus_buffer.scala 146:144] + node _T_311 = eq(_T_310, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] + node _T_312 = and(_T_308, _T_311) @[lsu_bus_buffer.scala 146:97] + node _T_313 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[lsu_bus_buffer.scala 146:170] + node _T_314 = eq(_T_313, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] + node _T_315 = and(_T_312, _T_314) @[lsu_bus_buffer.scala 146:148] + node _T_316 = bits(ld_byte_hitvec_lo_2, 2, 2) @[lsu_bus_buffer.scala 146:93] + node _T_317 = and(ld_byte_hitvec_lo_2, buf_age_younger[2]) @[lsu_bus_buffer.scala 146:122] + node _T_318 = orr(_T_317) @[lsu_bus_buffer.scala 146:144] + node _T_319 = eq(_T_318, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] + node _T_320 = and(_T_316, _T_319) @[lsu_bus_buffer.scala 146:97] + node _T_321 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[lsu_bus_buffer.scala 146:170] + node _T_322 = eq(_T_321, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] + node _T_323 = and(_T_320, _T_322) @[lsu_bus_buffer.scala 146:148] + node _T_324 = bits(ld_byte_hitvec_lo_2, 3, 3) @[lsu_bus_buffer.scala 146:93] + node _T_325 = and(ld_byte_hitvec_lo_2, buf_age_younger[3]) @[lsu_bus_buffer.scala 146:122] + node _T_326 = orr(_T_325) @[lsu_bus_buffer.scala 146:144] + node _T_327 = eq(_T_326, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] + node _T_328 = and(_T_324, _T_327) @[lsu_bus_buffer.scala 146:97] + node _T_329 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[lsu_bus_buffer.scala 146:170] + node _T_330 = eq(_T_329, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] + node _T_331 = and(_T_328, _T_330) @[lsu_bus_buffer.scala 146:148] + node _T_332 = cat(_T_331, _T_323) @[Cat.scala 29:58] + node _T_333 = cat(_T_332, _T_315) @[Cat.scala 29:58] + node _T_334 = cat(_T_333, _T_307) @[Cat.scala 29:58] + node _T_335 = bits(ld_byte_hitvec_lo_3, 0, 0) @[lsu_bus_buffer.scala 146:93] + node _T_336 = and(ld_byte_hitvec_lo_3, buf_age_younger[0]) @[lsu_bus_buffer.scala 146:122] + node _T_337 = orr(_T_336) @[lsu_bus_buffer.scala 146:144] + node _T_338 = eq(_T_337, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] + node _T_339 = and(_T_335, _T_338) @[lsu_bus_buffer.scala 146:97] + node _T_340 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[lsu_bus_buffer.scala 146:170] + node _T_341 = eq(_T_340, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] + node _T_342 = and(_T_339, _T_341) @[lsu_bus_buffer.scala 146:148] + node _T_343 = bits(ld_byte_hitvec_lo_3, 1, 1) @[lsu_bus_buffer.scala 146:93] + node _T_344 = and(ld_byte_hitvec_lo_3, buf_age_younger[1]) @[lsu_bus_buffer.scala 146:122] + node _T_345 = orr(_T_344) @[lsu_bus_buffer.scala 146:144] + node _T_346 = eq(_T_345, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] + node _T_347 = and(_T_343, _T_346) @[lsu_bus_buffer.scala 146:97] + node _T_348 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[lsu_bus_buffer.scala 146:170] + node _T_349 = eq(_T_348, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] + node _T_350 = and(_T_347, _T_349) @[lsu_bus_buffer.scala 146:148] + node _T_351 = bits(ld_byte_hitvec_lo_3, 2, 2) @[lsu_bus_buffer.scala 146:93] + node _T_352 = and(ld_byte_hitvec_lo_3, buf_age_younger[2]) @[lsu_bus_buffer.scala 146:122] + node _T_353 = orr(_T_352) @[lsu_bus_buffer.scala 146:144] + node _T_354 = eq(_T_353, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] + node _T_355 = and(_T_351, _T_354) @[lsu_bus_buffer.scala 146:97] + node _T_356 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[lsu_bus_buffer.scala 146:170] + node _T_357 = eq(_T_356, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] + node _T_358 = and(_T_355, _T_357) @[lsu_bus_buffer.scala 146:148] + node _T_359 = bits(ld_byte_hitvec_lo_3, 3, 3) @[lsu_bus_buffer.scala 146:93] + node _T_360 = and(ld_byte_hitvec_lo_3, buf_age_younger[3]) @[lsu_bus_buffer.scala 146:122] + node _T_361 = orr(_T_360) @[lsu_bus_buffer.scala 146:144] + node _T_362 = eq(_T_361, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] + node _T_363 = and(_T_359, _T_362) @[lsu_bus_buffer.scala 146:97] + node _T_364 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[lsu_bus_buffer.scala 146:170] + node _T_365 = eq(_T_364, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] + node _T_366 = and(_T_363, _T_365) @[lsu_bus_buffer.scala 146:148] + node _T_367 = cat(_T_366, _T_358) @[Cat.scala 29:58] + node _T_368 = cat(_T_367, _T_350) @[Cat.scala 29:58] + node _T_369 = cat(_T_368, _T_342) @[Cat.scala 29:58] + ld_byte_hitvecfn_lo[0] <= _T_264 @[lsu_bus_buffer.scala 146:23] + ld_byte_hitvecfn_lo[1] <= _T_299 @[lsu_bus_buffer.scala 146:23] + ld_byte_hitvecfn_lo[2] <= _T_334 @[lsu_bus_buffer.scala 146:23] + ld_byte_hitvecfn_lo[3] <= _T_369 @[lsu_bus_buffer.scala 146:23] + node _T_370 = bits(ld_byte_hitvec_hi_0, 0, 0) @[lsu_bus_buffer.scala 147:93] + node _T_371 = and(ld_byte_hitvec_hi_0, buf_age_younger[0]) @[lsu_bus_buffer.scala 147:122] + node _T_372 = orr(_T_371) @[lsu_bus_buffer.scala 147:144] + node _T_373 = eq(_T_372, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:99] + node _T_374 = and(_T_370, _T_373) @[lsu_bus_buffer.scala 147:97] + node _T_375 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[lsu_bus_buffer.scala 147:170] + node _T_376 = eq(_T_375, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:150] + node _T_377 = and(_T_374, _T_376) @[lsu_bus_buffer.scala 147:148] + node _T_378 = bits(ld_byte_hitvec_hi_0, 1, 1) @[lsu_bus_buffer.scala 147:93] + node _T_379 = and(ld_byte_hitvec_hi_0, buf_age_younger[1]) @[lsu_bus_buffer.scala 147:122] + node _T_380 = orr(_T_379) @[lsu_bus_buffer.scala 147:144] + node _T_381 = eq(_T_380, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:99] + node _T_382 = and(_T_378, _T_381) @[lsu_bus_buffer.scala 147:97] + node _T_383 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[lsu_bus_buffer.scala 147:170] + node _T_384 = eq(_T_383, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:150] + node _T_385 = and(_T_382, _T_384) @[lsu_bus_buffer.scala 147:148] + node _T_386 = bits(ld_byte_hitvec_hi_0, 2, 2) @[lsu_bus_buffer.scala 147:93] + node _T_387 = and(ld_byte_hitvec_hi_0, buf_age_younger[2]) @[lsu_bus_buffer.scala 147:122] + node _T_388 = orr(_T_387) @[lsu_bus_buffer.scala 147:144] + node _T_389 = eq(_T_388, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:99] + node _T_390 = and(_T_386, _T_389) @[lsu_bus_buffer.scala 147:97] + node _T_391 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[lsu_bus_buffer.scala 147:170] + node _T_392 = eq(_T_391, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:150] + node _T_393 = and(_T_390, _T_392) @[lsu_bus_buffer.scala 147:148] + node _T_394 = bits(ld_byte_hitvec_hi_0, 3, 3) @[lsu_bus_buffer.scala 147:93] + node _T_395 = and(ld_byte_hitvec_hi_0, buf_age_younger[3]) @[lsu_bus_buffer.scala 147:122] + node _T_396 = orr(_T_395) @[lsu_bus_buffer.scala 147:144] + node _T_397 = eq(_T_396, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:99] + node _T_398 = and(_T_394, _T_397) @[lsu_bus_buffer.scala 147:97] + node _T_399 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[lsu_bus_buffer.scala 147:170] + node _T_400 = eq(_T_399, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:150] + node _T_401 = and(_T_398, _T_400) @[lsu_bus_buffer.scala 147:148] + node _T_402 = cat(_T_401, _T_393) @[Cat.scala 29:58] + node _T_403 = cat(_T_402, _T_385) @[Cat.scala 29:58] + node _T_404 = cat(_T_403, _T_377) @[Cat.scala 29:58] + node _T_405 = bits(ld_byte_hitvec_hi_1, 0, 0) @[lsu_bus_buffer.scala 147:93] + node _T_406 = and(ld_byte_hitvec_hi_1, buf_age_younger[0]) @[lsu_bus_buffer.scala 147:122] + node _T_407 = orr(_T_406) @[lsu_bus_buffer.scala 147:144] + node _T_408 = eq(_T_407, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:99] + node _T_409 = and(_T_405, _T_408) @[lsu_bus_buffer.scala 147:97] + node _T_410 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[lsu_bus_buffer.scala 147:170] + node _T_411 = eq(_T_410, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:150] + node _T_412 = and(_T_409, _T_411) @[lsu_bus_buffer.scala 147:148] + node _T_413 = bits(ld_byte_hitvec_hi_1, 1, 1) @[lsu_bus_buffer.scala 147:93] + node _T_414 = and(ld_byte_hitvec_hi_1, buf_age_younger[1]) @[lsu_bus_buffer.scala 147:122] + node _T_415 = orr(_T_414) @[lsu_bus_buffer.scala 147:144] + node _T_416 = eq(_T_415, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:99] + node _T_417 = and(_T_413, _T_416) @[lsu_bus_buffer.scala 147:97] + node _T_418 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[lsu_bus_buffer.scala 147:170] + node _T_419 = eq(_T_418, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:150] + node _T_420 = and(_T_417, _T_419) @[lsu_bus_buffer.scala 147:148] + node _T_421 = bits(ld_byte_hitvec_hi_1, 2, 2) @[lsu_bus_buffer.scala 147:93] + node _T_422 = and(ld_byte_hitvec_hi_1, buf_age_younger[2]) @[lsu_bus_buffer.scala 147:122] + node _T_423 = orr(_T_422) @[lsu_bus_buffer.scala 147:144] + node _T_424 = eq(_T_423, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:99] + node _T_425 = and(_T_421, _T_424) @[lsu_bus_buffer.scala 147:97] + node _T_426 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[lsu_bus_buffer.scala 147:170] + node _T_427 = eq(_T_426, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:150] + node _T_428 = and(_T_425, _T_427) @[lsu_bus_buffer.scala 147:148] + node _T_429 = bits(ld_byte_hitvec_hi_1, 3, 3) @[lsu_bus_buffer.scala 147:93] + node _T_430 = and(ld_byte_hitvec_hi_1, buf_age_younger[3]) @[lsu_bus_buffer.scala 147:122] + node _T_431 = orr(_T_430) @[lsu_bus_buffer.scala 147:144] + node _T_432 = eq(_T_431, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:99] + node _T_433 = and(_T_429, _T_432) @[lsu_bus_buffer.scala 147:97] + node _T_434 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[lsu_bus_buffer.scala 147:170] + node _T_435 = eq(_T_434, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:150] + node _T_436 = and(_T_433, _T_435) @[lsu_bus_buffer.scala 147:148] + node _T_437 = cat(_T_436, _T_428) @[Cat.scala 29:58] + node _T_438 = cat(_T_437, _T_420) @[Cat.scala 29:58] + node _T_439 = cat(_T_438, _T_412) @[Cat.scala 29:58] + node _T_440 = bits(ld_byte_hitvec_hi_2, 0, 0) @[lsu_bus_buffer.scala 147:93] + node _T_441 = and(ld_byte_hitvec_hi_2, buf_age_younger[0]) @[lsu_bus_buffer.scala 147:122] + node _T_442 = orr(_T_441) @[lsu_bus_buffer.scala 147:144] + node _T_443 = eq(_T_442, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:99] + node _T_444 = and(_T_440, _T_443) @[lsu_bus_buffer.scala 147:97] + node _T_445 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[lsu_bus_buffer.scala 147:170] + node _T_446 = eq(_T_445, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:150] + node _T_447 = and(_T_444, _T_446) @[lsu_bus_buffer.scala 147:148] + node _T_448 = bits(ld_byte_hitvec_hi_2, 1, 1) @[lsu_bus_buffer.scala 147:93] + node _T_449 = and(ld_byte_hitvec_hi_2, buf_age_younger[1]) @[lsu_bus_buffer.scala 147:122] + node _T_450 = orr(_T_449) @[lsu_bus_buffer.scala 147:144] + node _T_451 = eq(_T_450, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:99] + node _T_452 = and(_T_448, _T_451) @[lsu_bus_buffer.scala 147:97] + node _T_453 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[lsu_bus_buffer.scala 147:170] + node _T_454 = eq(_T_453, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:150] + node _T_455 = and(_T_452, _T_454) @[lsu_bus_buffer.scala 147:148] + node _T_456 = bits(ld_byte_hitvec_hi_2, 2, 2) @[lsu_bus_buffer.scala 147:93] + node _T_457 = and(ld_byte_hitvec_hi_2, buf_age_younger[2]) @[lsu_bus_buffer.scala 147:122] + node _T_458 = orr(_T_457) @[lsu_bus_buffer.scala 147:144] + node _T_459 = eq(_T_458, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:99] + node _T_460 = and(_T_456, _T_459) @[lsu_bus_buffer.scala 147:97] + node _T_461 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[lsu_bus_buffer.scala 147:170] + node _T_462 = eq(_T_461, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:150] + node _T_463 = and(_T_460, _T_462) @[lsu_bus_buffer.scala 147:148] + node _T_464 = bits(ld_byte_hitvec_hi_2, 3, 3) @[lsu_bus_buffer.scala 147:93] + node _T_465 = and(ld_byte_hitvec_hi_2, buf_age_younger[3]) @[lsu_bus_buffer.scala 147:122] + node _T_466 = orr(_T_465) @[lsu_bus_buffer.scala 147:144] + node _T_467 = eq(_T_466, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:99] + node _T_468 = and(_T_464, _T_467) @[lsu_bus_buffer.scala 147:97] + node _T_469 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[lsu_bus_buffer.scala 147:170] + node _T_470 = eq(_T_469, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:150] + node _T_471 = and(_T_468, _T_470) @[lsu_bus_buffer.scala 147:148] + node _T_472 = cat(_T_471, _T_463) @[Cat.scala 29:58] + node _T_473 = cat(_T_472, _T_455) @[Cat.scala 29:58] + node _T_474 = cat(_T_473, _T_447) @[Cat.scala 29:58] + node _T_475 = bits(ld_byte_hitvec_hi_3, 0, 0) @[lsu_bus_buffer.scala 147:93] + node _T_476 = and(ld_byte_hitvec_hi_3, buf_age_younger[0]) @[lsu_bus_buffer.scala 147:122] + node _T_477 = orr(_T_476) @[lsu_bus_buffer.scala 147:144] + node _T_478 = eq(_T_477, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:99] + node _T_479 = and(_T_475, _T_478) @[lsu_bus_buffer.scala 147:97] + node _T_480 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[lsu_bus_buffer.scala 147:170] + node _T_481 = eq(_T_480, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:150] + node _T_482 = and(_T_479, _T_481) @[lsu_bus_buffer.scala 147:148] + node _T_483 = bits(ld_byte_hitvec_hi_3, 1, 1) @[lsu_bus_buffer.scala 147:93] + node _T_484 = and(ld_byte_hitvec_hi_3, buf_age_younger[1]) @[lsu_bus_buffer.scala 147:122] + node _T_485 = orr(_T_484) @[lsu_bus_buffer.scala 147:144] + node _T_486 = eq(_T_485, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:99] + node _T_487 = and(_T_483, _T_486) @[lsu_bus_buffer.scala 147:97] + node _T_488 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[lsu_bus_buffer.scala 147:170] + node _T_489 = eq(_T_488, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:150] + node _T_490 = and(_T_487, _T_489) @[lsu_bus_buffer.scala 147:148] + node _T_491 = bits(ld_byte_hitvec_hi_3, 2, 2) @[lsu_bus_buffer.scala 147:93] + node _T_492 = and(ld_byte_hitvec_hi_3, buf_age_younger[2]) @[lsu_bus_buffer.scala 147:122] + node _T_493 = orr(_T_492) @[lsu_bus_buffer.scala 147:144] + node _T_494 = eq(_T_493, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:99] + node _T_495 = and(_T_491, _T_494) @[lsu_bus_buffer.scala 147:97] + node _T_496 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[lsu_bus_buffer.scala 147:170] + node _T_497 = eq(_T_496, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:150] + node _T_498 = and(_T_495, _T_497) @[lsu_bus_buffer.scala 147:148] + node _T_499 = bits(ld_byte_hitvec_hi_3, 3, 3) @[lsu_bus_buffer.scala 147:93] + node _T_500 = and(ld_byte_hitvec_hi_3, buf_age_younger[3]) @[lsu_bus_buffer.scala 147:122] + node _T_501 = orr(_T_500) @[lsu_bus_buffer.scala 147:144] + node _T_502 = eq(_T_501, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:99] + node _T_503 = and(_T_499, _T_502) @[lsu_bus_buffer.scala 147:97] + node _T_504 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[lsu_bus_buffer.scala 147:170] + node _T_505 = eq(_T_504, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:150] + node _T_506 = and(_T_503, _T_505) @[lsu_bus_buffer.scala 147:148] + node _T_507 = cat(_T_506, _T_498) @[Cat.scala 29:58] + node _T_508 = cat(_T_507, _T_490) @[Cat.scala 29:58] + node _T_509 = cat(_T_508, _T_482) @[Cat.scala 29:58] + ld_byte_hitvecfn_hi[0] <= _T_404 @[lsu_bus_buffer.scala 147:23] + ld_byte_hitvecfn_hi[1] <= _T_439 @[lsu_bus_buffer.scala 147:23] + ld_byte_hitvecfn_hi[2] <= _T_474 @[lsu_bus_buffer.scala 147:23] + ld_byte_hitvecfn_hi[3] <= _T_509 @[lsu_bus_buffer.scala 147:23] + wire ibuf_addr : UInt<32> + ibuf_addr <= UInt<1>("h00") + wire ibuf_write : UInt<1> + ibuf_write <= UInt<1>("h00") + wire ibuf_valid : UInt<1> + ibuf_valid <= UInt<1>("h00") + node _T_510 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 152:43] + node _T_511 = bits(ibuf_addr, 31, 2) @[lsu_bus_buffer.scala 152:64] + node _T_512 = eq(_T_510, _T_511) @[lsu_bus_buffer.scala 152:51] + node _T_513 = and(_T_512, ibuf_write) @[lsu_bus_buffer.scala 152:73] + node _T_514 = and(_T_513, ibuf_valid) @[lsu_bus_buffer.scala 152:86] + node ld_addr_ibuf_hit_lo = and(_T_514, io.lsu_busreq_m) @[lsu_bus_buffer.scala 152:99] + node _T_515 = bits(io.end_addr_m, 31, 2) @[lsu_bus_buffer.scala 153:43] + node _T_516 = bits(ibuf_addr, 31, 2) @[lsu_bus_buffer.scala 153:64] + node _T_517 = eq(_T_515, _T_516) @[lsu_bus_buffer.scala 153:51] + node _T_518 = and(_T_517, ibuf_write) @[lsu_bus_buffer.scala 153:73] + node _T_519 = and(_T_518, ibuf_valid) @[lsu_bus_buffer.scala 153:86] + node ld_addr_ibuf_hit_hi = and(_T_519, io.lsu_busreq_m) @[lsu_bus_buffer.scala 153:99] + wire ibuf_byteen : UInt<4> + ibuf_byteen <= UInt<1>("h00") + node _T_520 = bits(ld_addr_ibuf_hit_lo, 0, 0) @[Bitwise.scala 72:15] + node _T_521 = mux(_T_520, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_522 = and(_T_521, ibuf_byteen) @[lsu_bus_buffer.scala 157:55] + node _T_523 = and(_T_522, ldst_byteen_lo_m) @[lsu_bus_buffer.scala 157:69] + ld_byte_ibuf_hit_lo <= _T_523 @[lsu_bus_buffer.scala 157:23] + node _T_524 = bits(ld_addr_ibuf_hit_hi, 0, 0) @[Bitwise.scala 72:15] + node _T_525 = mux(_T_524, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_526 = and(_T_525, ibuf_byteen) @[lsu_bus_buffer.scala 158:55] + node _T_527 = and(_T_526, ldst_byteen_hi_m) @[lsu_bus_buffer.scala 158:69] + ld_byte_ibuf_hit_hi <= _T_527 @[lsu_bus_buffer.scala 158:23] + wire buf_data : UInt<32>[4] @[lsu_bus_buffer.scala 160:22] + buf_data[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 161:12] + buf_data[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 161:12] + buf_data[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 161:12] + buf_data[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 161:12] + wire fwd_data : UInt<32> + fwd_data <= UInt<1>("h00") + node _T_528 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[lsu_bus_buffer.scala 163:81] + node _T_529 = bits(_T_528, 0, 0) @[Bitwise.scala 72:15] + node _T_530 = mux(_T_529, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_531 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[lsu_bus_buffer.scala 163:81] + node _T_532 = bits(_T_531, 0, 0) @[Bitwise.scala 72:15] + node _T_533 = mux(_T_532, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_534 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[lsu_bus_buffer.scala 163:81] + node _T_535 = bits(_T_534, 0, 0) @[Bitwise.scala 72:15] + node _T_536 = mux(_T_535, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_537 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[lsu_bus_buffer.scala 163:81] + node _T_538 = bits(_T_537, 0, 0) @[Bitwise.scala 72:15] + node _T_539 = mux(_T_538, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_540 = cat(_T_539, _T_536) @[Cat.scala 29:58] + node _T_541 = cat(_T_540, _T_533) @[Cat.scala 29:58] + node ld_fwddata_buf_lo_initial = cat(_T_541, _T_530) @[Cat.scala 29:58] + node _T_542 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[lsu_bus_buffer.scala 164:81] + node _T_543 = bits(_T_542, 0, 0) @[Bitwise.scala 72:15] + node _T_544 = mux(_T_543, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_545 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[lsu_bus_buffer.scala 164:81] + node _T_546 = bits(_T_545, 0, 0) @[Bitwise.scala 72:15] + node _T_547 = mux(_T_546, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_548 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[lsu_bus_buffer.scala 164:81] + node _T_549 = bits(_T_548, 0, 0) @[Bitwise.scala 72:15] + node _T_550 = mux(_T_549, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_551 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[lsu_bus_buffer.scala 164:81] + node _T_552 = bits(_T_551, 0, 0) @[Bitwise.scala 72:15] + node _T_553 = mux(_T_552, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_554 = cat(_T_553, _T_550) @[Cat.scala 29:58] + node _T_555 = cat(_T_554, _T_547) @[Cat.scala 29:58] + node ld_fwddata_buf_hi_initial = cat(_T_555, _T_544) @[Cat.scala 29:58] + node _T_556 = bits(ld_byte_hitvecfn_lo[3], 0, 0) @[lsu_bus_buffer.scala 165:86] + node _T_557 = bits(_T_556, 0, 0) @[Bitwise.scala 72:15] + node _T_558 = mux(_T_557, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_559 = bits(buf_data[0], 31, 24) @[lsu_bus_buffer.scala 165:104] + node _T_560 = and(_T_558, _T_559) @[lsu_bus_buffer.scala 165:91] + node _T_561 = bits(ld_byte_hitvecfn_lo[3], 1, 1) @[lsu_bus_buffer.scala 165:86] + node _T_562 = bits(_T_561, 0, 0) @[Bitwise.scala 72:15] + node _T_563 = mux(_T_562, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_564 = bits(buf_data[1], 31, 24) @[lsu_bus_buffer.scala 165:104] + node _T_565 = and(_T_563, _T_564) @[lsu_bus_buffer.scala 165:91] + node _T_566 = bits(ld_byte_hitvecfn_lo[3], 2, 2) @[lsu_bus_buffer.scala 165:86] + node _T_567 = bits(_T_566, 0, 0) @[Bitwise.scala 72:15] + node _T_568 = mux(_T_567, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_569 = bits(buf_data[2], 31, 24) @[lsu_bus_buffer.scala 165:104] + node _T_570 = and(_T_568, _T_569) @[lsu_bus_buffer.scala 165:91] + node _T_571 = bits(ld_byte_hitvecfn_lo[3], 3, 3) @[lsu_bus_buffer.scala 165:86] + node _T_572 = bits(_T_571, 0, 0) @[Bitwise.scala 72:15] + node _T_573 = mux(_T_572, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_574 = bits(buf_data[3], 31, 24) @[lsu_bus_buffer.scala 165:104] + node _T_575 = and(_T_573, _T_574) @[lsu_bus_buffer.scala 165:91] + node _T_576 = or(_T_560, _T_565) @[lsu_bus_buffer.scala 165:123] + node _T_577 = or(_T_576, _T_570) @[lsu_bus_buffer.scala 165:123] + node _T_578 = or(_T_577, _T_575) @[lsu_bus_buffer.scala 165:123] + node _T_579 = bits(ld_byte_hitvecfn_lo[2], 0, 0) @[lsu_bus_buffer.scala 166:60] + node _T_580 = bits(_T_579, 0, 0) @[Bitwise.scala 72:15] + node _T_581 = mux(_T_580, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_582 = bits(buf_data[0], 23, 16) @[lsu_bus_buffer.scala 166:78] + node _T_583 = and(_T_581, _T_582) @[lsu_bus_buffer.scala 166:65] + node _T_584 = bits(ld_byte_hitvecfn_lo[2], 1, 1) @[lsu_bus_buffer.scala 166:60] + node _T_585 = bits(_T_584, 0, 0) @[Bitwise.scala 72:15] + node _T_586 = mux(_T_585, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_587 = bits(buf_data[1], 23, 16) @[lsu_bus_buffer.scala 166:78] + node _T_588 = and(_T_586, _T_587) @[lsu_bus_buffer.scala 166:65] + node _T_589 = bits(ld_byte_hitvecfn_lo[2], 2, 2) @[lsu_bus_buffer.scala 166:60] + node _T_590 = bits(_T_589, 0, 0) @[Bitwise.scala 72:15] + node _T_591 = mux(_T_590, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_592 = bits(buf_data[2], 23, 16) @[lsu_bus_buffer.scala 166:78] + node _T_593 = and(_T_591, _T_592) @[lsu_bus_buffer.scala 166:65] + node _T_594 = bits(ld_byte_hitvecfn_lo[2], 3, 3) @[lsu_bus_buffer.scala 166:60] + node _T_595 = bits(_T_594, 0, 0) @[Bitwise.scala 72:15] + node _T_596 = mux(_T_595, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_597 = bits(buf_data[3], 23, 16) @[lsu_bus_buffer.scala 166:78] + node _T_598 = and(_T_596, _T_597) @[lsu_bus_buffer.scala 166:65] + node _T_599 = or(_T_583, _T_588) @[lsu_bus_buffer.scala 166:97] + node _T_600 = or(_T_599, _T_593) @[lsu_bus_buffer.scala 166:97] + node _T_601 = or(_T_600, _T_598) @[lsu_bus_buffer.scala 166:97] + node _T_602 = bits(ld_byte_hitvecfn_lo[1], 0, 0) @[lsu_bus_buffer.scala 167:60] + node _T_603 = bits(_T_602, 0, 0) @[Bitwise.scala 72:15] + node _T_604 = mux(_T_603, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_605 = bits(buf_data[0], 15, 8) @[lsu_bus_buffer.scala 167:78] + node _T_606 = and(_T_604, _T_605) @[lsu_bus_buffer.scala 167:65] + node _T_607 = bits(ld_byte_hitvecfn_lo[1], 1, 1) @[lsu_bus_buffer.scala 167:60] + node _T_608 = bits(_T_607, 0, 0) @[Bitwise.scala 72:15] + node _T_609 = mux(_T_608, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_610 = bits(buf_data[1], 15, 8) @[lsu_bus_buffer.scala 167:78] + node _T_611 = and(_T_609, _T_610) @[lsu_bus_buffer.scala 167:65] + node _T_612 = bits(ld_byte_hitvecfn_lo[1], 2, 2) @[lsu_bus_buffer.scala 167:60] + node _T_613 = bits(_T_612, 0, 0) @[Bitwise.scala 72:15] + node _T_614 = mux(_T_613, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_615 = bits(buf_data[2], 15, 8) @[lsu_bus_buffer.scala 167:78] + node _T_616 = and(_T_614, _T_615) @[lsu_bus_buffer.scala 167:65] + node _T_617 = bits(ld_byte_hitvecfn_lo[1], 3, 3) @[lsu_bus_buffer.scala 167:60] + node _T_618 = bits(_T_617, 0, 0) @[Bitwise.scala 72:15] + node _T_619 = mux(_T_618, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_620 = bits(buf_data[3], 15, 8) @[lsu_bus_buffer.scala 167:78] + node _T_621 = and(_T_619, _T_620) @[lsu_bus_buffer.scala 167:65] + node _T_622 = or(_T_606, _T_611) @[lsu_bus_buffer.scala 167:97] + node _T_623 = or(_T_622, _T_616) @[lsu_bus_buffer.scala 167:97] + node _T_624 = or(_T_623, _T_621) @[lsu_bus_buffer.scala 167:97] + node _T_625 = bits(ld_byte_hitvecfn_lo[0], 0, 0) @[lsu_bus_buffer.scala 168:60] + node _T_626 = bits(_T_625, 0, 0) @[Bitwise.scala 72:15] + node _T_627 = mux(_T_626, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_628 = bits(buf_data[0], 7, 0) @[lsu_bus_buffer.scala 168:78] + node _T_629 = and(_T_627, _T_628) @[lsu_bus_buffer.scala 168:65] + node _T_630 = bits(ld_byte_hitvecfn_lo[0], 1, 1) @[lsu_bus_buffer.scala 168:60] + node _T_631 = bits(_T_630, 0, 0) @[Bitwise.scala 72:15] + node _T_632 = mux(_T_631, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_633 = bits(buf_data[1], 7, 0) @[lsu_bus_buffer.scala 168:78] + node _T_634 = and(_T_632, _T_633) @[lsu_bus_buffer.scala 168:65] + node _T_635 = bits(ld_byte_hitvecfn_lo[0], 2, 2) @[lsu_bus_buffer.scala 168:60] + node _T_636 = bits(_T_635, 0, 0) @[Bitwise.scala 72:15] + node _T_637 = mux(_T_636, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_638 = bits(buf_data[2], 7, 0) @[lsu_bus_buffer.scala 168:78] + node _T_639 = and(_T_637, _T_638) @[lsu_bus_buffer.scala 168:65] + node _T_640 = bits(ld_byte_hitvecfn_lo[0], 3, 3) @[lsu_bus_buffer.scala 168:60] + node _T_641 = bits(_T_640, 0, 0) @[Bitwise.scala 72:15] + node _T_642 = mux(_T_641, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_643 = bits(buf_data[3], 7, 0) @[lsu_bus_buffer.scala 168:78] + node _T_644 = and(_T_642, _T_643) @[lsu_bus_buffer.scala 168:65] + node _T_645 = or(_T_629, _T_634) @[lsu_bus_buffer.scala 168:97] + node _T_646 = or(_T_645, _T_639) @[lsu_bus_buffer.scala 168:97] + node _T_647 = or(_T_646, _T_644) @[lsu_bus_buffer.scala 168:97] + node _T_648 = cat(_T_624, _T_647) @[Cat.scala 29:58] + node _T_649 = cat(_T_578, _T_601) @[Cat.scala 29:58] + node _T_650 = cat(_T_649, _T_648) @[Cat.scala 29:58] + node _T_651 = and(ld_fwddata_buf_lo_initial, ibuf_data) @[lsu_bus_buffer.scala 169:32] + node _T_652 = or(_T_650, _T_651) @[lsu_bus_buffer.scala 168:103] + io.ld_fwddata_buf_lo <= _T_652 @[lsu_bus_buffer.scala 165:24] + node _T_653 = bits(ld_byte_hitvecfn_hi[3], 0, 0) @[lsu_bus_buffer.scala 171:86] + node _T_654 = bits(_T_653, 0, 0) @[Bitwise.scala 72:15] + node _T_655 = mux(_T_654, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_656 = bits(buf_data[0], 31, 24) @[lsu_bus_buffer.scala 171:104] + node _T_657 = and(_T_655, _T_656) @[lsu_bus_buffer.scala 171:91] + node _T_658 = bits(ld_byte_hitvecfn_hi[3], 1, 1) @[lsu_bus_buffer.scala 171:86] + node _T_659 = bits(_T_658, 0, 0) @[Bitwise.scala 72:15] + node _T_660 = mux(_T_659, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_661 = bits(buf_data[1], 31, 24) @[lsu_bus_buffer.scala 171:104] + node _T_662 = and(_T_660, _T_661) @[lsu_bus_buffer.scala 171:91] + node _T_663 = bits(ld_byte_hitvecfn_hi[3], 2, 2) @[lsu_bus_buffer.scala 171:86] + node _T_664 = bits(_T_663, 0, 0) @[Bitwise.scala 72:15] + node _T_665 = mux(_T_664, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_666 = bits(buf_data[2], 31, 24) @[lsu_bus_buffer.scala 171:104] + node _T_667 = and(_T_665, _T_666) @[lsu_bus_buffer.scala 171:91] + node _T_668 = bits(ld_byte_hitvecfn_hi[3], 3, 3) @[lsu_bus_buffer.scala 171:86] + node _T_669 = bits(_T_668, 0, 0) @[Bitwise.scala 72:15] + node _T_670 = mux(_T_669, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_671 = bits(buf_data[3], 31, 24) @[lsu_bus_buffer.scala 171:104] + node _T_672 = and(_T_670, _T_671) @[lsu_bus_buffer.scala 171:91] + node _T_673 = or(_T_657, _T_662) @[lsu_bus_buffer.scala 171:123] + node _T_674 = or(_T_673, _T_667) @[lsu_bus_buffer.scala 171:123] + node _T_675 = or(_T_674, _T_672) @[lsu_bus_buffer.scala 171:123] + node _T_676 = bits(ld_byte_hitvecfn_hi[2], 0, 0) @[lsu_bus_buffer.scala 172:60] + node _T_677 = bits(_T_676, 0, 0) @[Bitwise.scala 72:15] + node _T_678 = mux(_T_677, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_679 = bits(buf_data[0], 23, 16) @[lsu_bus_buffer.scala 172:78] + node _T_680 = and(_T_678, _T_679) @[lsu_bus_buffer.scala 172:65] + node _T_681 = bits(ld_byte_hitvecfn_hi[2], 1, 1) @[lsu_bus_buffer.scala 172:60] + node _T_682 = bits(_T_681, 0, 0) @[Bitwise.scala 72:15] + node _T_683 = mux(_T_682, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_684 = bits(buf_data[1], 23, 16) @[lsu_bus_buffer.scala 172:78] + node _T_685 = and(_T_683, _T_684) @[lsu_bus_buffer.scala 172:65] + node _T_686 = bits(ld_byte_hitvecfn_hi[2], 2, 2) @[lsu_bus_buffer.scala 172:60] + node _T_687 = bits(_T_686, 0, 0) @[Bitwise.scala 72:15] + node _T_688 = mux(_T_687, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_689 = bits(buf_data[2], 23, 16) @[lsu_bus_buffer.scala 172:78] + node _T_690 = and(_T_688, _T_689) @[lsu_bus_buffer.scala 172:65] + node _T_691 = bits(ld_byte_hitvecfn_hi[2], 3, 3) @[lsu_bus_buffer.scala 172:60] + node _T_692 = bits(_T_691, 0, 0) @[Bitwise.scala 72:15] + node _T_693 = mux(_T_692, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_694 = bits(buf_data[3], 23, 16) @[lsu_bus_buffer.scala 172:78] + node _T_695 = and(_T_693, _T_694) @[lsu_bus_buffer.scala 172:65] + node _T_696 = or(_T_680, _T_685) @[lsu_bus_buffer.scala 172:97] + node _T_697 = or(_T_696, _T_690) @[lsu_bus_buffer.scala 172:97] + node _T_698 = or(_T_697, _T_695) @[lsu_bus_buffer.scala 172:97] + node _T_699 = bits(ld_byte_hitvecfn_hi[1], 0, 0) @[lsu_bus_buffer.scala 173:60] + node _T_700 = bits(_T_699, 0, 0) @[Bitwise.scala 72:15] + node _T_701 = mux(_T_700, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_702 = bits(buf_data[0], 15, 8) @[lsu_bus_buffer.scala 173:78] + node _T_703 = and(_T_701, _T_702) @[lsu_bus_buffer.scala 173:65] + node _T_704 = bits(ld_byte_hitvecfn_hi[1], 1, 1) @[lsu_bus_buffer.scala 173:60] + node _T_705 = bits(_T_704, 0, 0) @[Bitwise.scala 72:15] + node _T_706 = mux(_T_705, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_707 = bits(buf_data[1], 15, 8) @[lsu_bus_buffer.scala 173:78] + node _T_708 = and(_T_706, _T_707) @[lsu_bus_buffer.scala 173:65] + node _T_709 = bits(ld_byte_hitvecfn_hi[1], 2, 2) @[lsu_bus_buffer.scala 173:60] + node _T_710 = bits(_T_709, 0, 0) @[Bitwise.scala 72:15] + node _T_711 = mux(_T_710, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_712 = bits(buf_data[2], 15, 8) @[lsu_bus_buffer.scala 173:78] + node _T_713 = and(_T_711, _T_712) @[lsu_bus_buffer.scala 173:65] + node _T_714 = bits(ld_byte_hitvecfn_hi[1], 3, 3) @[lsu_bus_buffer.scala 173:60] + node _T_715 = bits(_T_714, 0, 0) @[Bitwise.scala 72:15] + node _T_716 = mux(_T_715, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_717 = bits(buf_data[3], 15, 8) @[lsu_bus_buffer.scala 173:78] + node _T_718 = and(_T_716, _T_717) @[lsu_bus_buffer.scala 173:65] + node _T_719 = or(_T_703, _T_708) @[lsu_bus_buffer.scala 173:97] + node _T_720 = or(_T_719, _T_713) @[lsu_bus_buffer.scala 173:97] + node _T_721 = or(_T_720, _T_718) @[lsu_bus_buffer.scala 173:97] + node _T_722 = bits(ld_byte_hitvecfn_hi[0], 0, 0) @[lsu_bus_buffer.scala 174:60] + node _T_723 = bits(_T_722, 0, 0) @[Bitwise.scala 72:15] + node _T_724 = mux(_T_723, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_725 = bits(buf_data[0], 7, 0) @[lsu_bus_buffer.scala 174:78] + node _T_726 = and(_T_724, _T_725) @[lsu_bus_buffer.scala 174:65] + node _T_727 = bits(ld_byte_hitvecfn_hi[0], 1, 1) @[lsu_bus_buffer.scala 174:60] + node _T_728 = bits(_T_727, 0, 0) @[Bitwise.scala 72:15] + node _T_729 = mux(_T_728, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_730 = bits(buf_data[1], 7, 0) @[lsu_bus_buffer.scala 174:78] + node _T_731 = and(_T_729, _T_730) @[lsu_bus_buffer.scala 174:65] + node _T_732 = bits(ld_byte_hitvecfn_hi[0], 2, 2) @[lsu_bus_buffer.scala 174:60] + node _T_733 = bits(_T_732, 0, 0) @[Bitwise.scala 72:15] + node _T_734 = mux(_T_733, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_735 = bits(buf_data[2], 7, 0) @[lsu_bus_buffer.scala 174:78] + node _T_736 = and(_T_734, _T_735) @[lsu_bus_buffer.scala 174:65] + node _T_737 = bits(ld_byte_hitvecfn_hi[0], 3, 3) @[lsu_bus_buffer.scala 174:60] + node _T_738 = bits(_T_737, 0, 0) @[Bitwise.scala 72:15] + node _T_739 = mux(_T_738, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_740 = bits(buf_data[3], 7, 0) @[lsu_bus_buffer.scala 174:78] + node _T_741 = and(_T_739, _T_740) @[lsu_bus_buffer.scala 174:65] + node _T_742 = or(_T_726, _T_731) @[lsu_bus_buffer.scala 174:97] + node _T_743 = or(_T_742, _T_736) @[lsu_bus_buffer.scala 174:97] + node _T_744 = or(_T_743, _T_741) @[lsu_bus_buffer.scala 174:97] + node _T_745 = cat(_T_721, _T_744) @[Cat.scala 29:58] + node _T_746 = cat(_T_675, _T_698) @[Cat.scala 29:58] + node _T_747 = cat(_T_746, _T_745) @[Cat.scala 29:58] + node _T_748 = and(ld_fwddata_buf_hi_initial, ibuf_data) @[lsu_bus_buffer.scala 175:32] + node _T_749 = or(_T_747, _T_748) @[lsu_bus_buffer.scala 174:103] + io.ld_fwddata_buf_hi <= _T_749 @[lsu_bus_buffer.scala 171:24] + node bus_coalescing_disable = or(io.tlu_busbuff.dec_tlu_wb_coalescing_disable, UInt<1>("h00")) @[lsu_bus_buffer.scala 177:77] + node _T_750 = mux(io.lsu_pkt_r.bits.by, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_751 = mux(io.lsu_pkt_r.bits.half, UInt<4>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_752 = mux(io.lsu_pkt_r.bits.word, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_753 = or(_T_750, _T_751) @[Mux.scala 27:72] + node _T_754 = or(_T_753, _T_752) @[Mux.scala 27:72] + wire ldst_byteen_r : UInt<4> @[Mux.scala 27:72] + ldst_byteen_r <= _T_754 @[Mux.scala 27:72] + node _T_755 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 182:50] + node _T_756 = eq(_T_755, UInt<1>("h00")) @[lsu_bus_buffer.scala 182:55] + node _T_757 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 183:19] + node _T_758 = eq(_T_757, UInt<1>("h01")) @[lsu_bus_buffer.scala 183:24] + node _T_759 = bits(ldst_byteen_r, 3, 3) @[lsu_bus_buffer.scala 183:60] + node _T_760 = cat(UInt<3>("h00"), _T_759) @[Cat.scala 29:58] + node _T_761 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 184:19] + node _T_762 = eq(_T_761, UInt<2>("h02")) @[lsu_bus_buffer.scala 184:24] + node _T_763 = bits(ldst_byteen_r, 3, 2) @[lsu_bus_buffer.scala 184:60] + node _T_764 = cat(UInt<2>("h00"), _T_763) @[Cat.scala 29:58] + node _T_765 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 185:19] + node _T_766 = eq(_T_765, UInt<2>("h03")) @[lsu_bus_buffer.scala 185:24] + node _T_767 = bits(ldst_byteen_r, 3, 1) @[lsu_bus_buffer.scala 185:60] + node _T_768 = cat(UInt<1>("h00"), _T_767) @[Cat.scala 29:58] + node _T_769 = mux(_T_756, UInt<4>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_770 = mux(_T_758, _T_760, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_771 = mux(_T_762, _T_764, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_772 = mux(_T_766, _T_768, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_773 = or(_T_769, _T_770) @[Mux.scala 27:72] + node _T_774 = or(_T_773, _T_771) @[Mux.scala 27:72] + node _T_775 = or(_T_774, _T_772) @[Mux.scala 27:72] + wire ldst_byteen_hi_r : UInt<4> @[Mux.scala 27:72] + ldst_byteen_hi_r <= _T_775 @[Mux.scala 27:72] + node _T_776 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 186:50] + node _T_777 = eq(_T_776, UInt<1>("h00")) @[lsu_bus_buffer.scala 186:55] + node _T_778 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 187:19] + node _T_779 = eq(_T_778, UInt<1>("h01")) @[lsu_bus_buffer.scala 187:24] + node _T_780 = bits(ldst_byteen_r, 2, 0) @[lsu_bus_buffer.scala 187:50] + node _T_781 = cat(_T_780, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_782 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 188:19] + node _T_783 = eq(_T_782, UInt<2>("h02")) @[lsu_bus_buffer.scala 188:24] + node _T_784 = bits(ldst_byteen_r, 1, 0) @[lsu_bus_buffer.scala 188:50] + node _T_785 = cat(_T_784, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_786 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 189:19] + node _T_787 = eq(_T_786, UInt<2>("h03")) @[lsu_bus_buffer.scala 189:24] + node _T_788 = bits(ldst_byteen_r, 0, 0) @[lsu_bus_buffer.scala 189:50] + node _T_789 = cat(_T_788, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_790 = mux(_T_777, ldst_byteen_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_791 = mux(_T_779, _T_781, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_792 = mux(_T_783, _T_785, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_793 = mux(_T_787, _T_789, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_794 = or(_T_790, _T_791) @[Mux.scala 27:72] + node _T_795 = or(_T_794, _T_792) @[Mux.scala 27:72] + node _T_796 = or(_T_795, _T_793) @[Mux.scala 27:72] + wire ldst_byteen_lo_r : UInt<4> @[Mux.scala 27:72] + ldst_byteen_lo_r <= _T_796 @[Mux.scala 27:72] + node _T_797 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 191:49] + node _T_798 = eq(_T_797, UInt<1>("h00")) @[lsu_bus_buffer.scala 191:54] + node _T_799 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 192:19] + node _T_800 = eq(_T_799, UInt<1>("h01")) @[lsu_bus_buffer.scala 192:24] + node _T_801 = bits(io.store_data_r, 31, 24) @[lsu_bus_buffer.scala 192:64] + node _T_802 = cat(UInt<24>("h00"), _T_801) @[Cat.scala 29:58] + node _T_803 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 193:19] + node _T_804 = eq(_T_803, UInt<2>("h02")) @[lsu_bus_buffer.scala 193:24] + node _T_805 = bits(io.store_data_r, 31, 16) @[lsu_bus_buffer.scala 193:63] + node _T_806 = cat(UInt<16>("h00"), _T_805) @[Cat.scala 29:58] + node _T_807 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 194:19] + node _T_808 = eq(_T_807, UInt<2>("h03")) @[lsu_bus_buffer.scala 194:24] + node _T_809 = bits(io.store_data_r, 31, 8) @[lsu_bus_buffer.scala 194:62] + node _T_810 = cat(UInt<8>("h00"), _T_809) @[Cat.scala 29:58] + node _T_811 = mux(_T_798, UInt<32>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_812 = mux(_T_800, _T_802, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_813 = mux(_T_804, _T_806, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_814 = mux(_T_808, _T_810, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_815 = or(_T_811, _T_812) @[Mux.scala 27:72] + node _T_816 = or(_T_815, _T_813) @[Mux.scala 27:72] + node _T_817 = or(_T_816, _T_814) @[Mux.scala 27:72] + wire store_data_hi_r : UInt<32> @[Mux.scala 27:72] + store_data_hi_r <= _T_817 @[Mux.scala 27:72] + node _T_818 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 196:49] + node _T_819 = eq(_T_818, UInt<1>("h00")) @[lsu_bus_buffer.scala 196:54] + node _T_820 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 197:19] + node _T_821 = eq(_T_820, UInt<1>("h01")) @[lsu_bus_buffer.scala 197:24] + node _T_822 = bits(io.store_data_r, 23, 0) @[lsu_bus_buffer.scala 197:52] + node _T_823 = cat(_T_822, UInt<8>("h00")) @[Cat.scala 29:58] + node _T_824 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 198:19] + node _T_825 = eq(_T_824, UInt<2>("h02")) @[lsu_bus_buffer.scala 198:24] + node _T_826 = bits(io.store_data_r, 15, 0) @[lsu_bus_buffer.scala 198:52] + node _T_827 = cat(_T_826, UInt<16>("h00")) @[Cat.scala 29:58] + node _T_828 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 199:19] + node _T_829 = eq(_T_828, UInt<2>("h03")) @[lsu_bus_buffer.scala 199:24] + node _T_830 = bits(io.store_data_r, 7, 0) @[lsu_bus_buffer.scala 199:52] + node _T_831 = cat(_T_830, UInt<24>("h00")) @[Cat.scala 29:58] + node _T_832 = mux(_T_819, io.store_data_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_833 = mux(_T_821, _T_823, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_834 = mux(_T_825, _T_827, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_835 = mux(_T_829, _T_831, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_836 = or(_T_832, _T_833) @[Mux.scala 27:72] + node _T_837 = or(_T_836, _T_834) @[Mux.scala 27:72] + node _T_838 = or(_T_837, _T_835) @[Mux.scala 27:72] + wire store_data_lo_r : UInt<32> @[Mux.scala 27:72] + store_data_lo_r <= _T_838 @[Mux.scala 27:72] + node _T_839 = bits(io.lsu_addr_r, 3, 3) @[lsu_bus_buffer.scala 202:36] + node _T_840 = bits(io.end_addr_r, 3, 3) @[lsu_bus_buffer.scala 202:57] + node ldst_samedw_r = eq(_T_839, _T_840) @[lsu_bus_buffer.scala 202:40] + node _T_841 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 203:72] + node _T_842 = eq(_T_841, UInt<1>("h00")) @[lsu_bus_buffer.scala 203:79] + node _T_843 = bits(io.lsu_addr_r, 0, 0) @[lsu_bus_buffer.scala 204:45] + node _T_844 = eq(_T_843, UInt<1>("h00")) @[lsu_bus_buffer.scala 204:31] + node _T_845 = mux(io.lsu_pkt_r.bits.word, _T_842, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_846 = mux(io.lsu_pkt_r.bits.half, _T_844, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_847 = mux(io.lsu_pkt_r.bits.by, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_848 = or(_T_845, _T_846) @[Mux.scala 27:72] + node _T_849 = or(_T_848, _T_847) @[Mux.scala 27:72] + wire is_aligned_r : UInt<1> @[Mux.scala 27:72] + is_aligned_r <= _T_849 @[Mux.scala 27:72] + node _T_850 = or(io.lsu_pkt_r.bits.load, io.no_word_merge_r) @[lsu_bus_buffer.scala 206:60] + node _T_851 = and(io.lsu_busreq_r, _T_850) @[lsu_bus_buffer.scala 206:34] + node _T_852 = eq(ibuf_valid, UInt<1>("h00")) @[lsu_bus_buffer.scala 206:84] + node ibuf_byp = and(_T_851, _T_852) @[lsu_bus_buffer.scala 206:82] + node _T_853 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 207:36] + node _T_854 = eq(ibuf_byp, UInt<1>("h00")) @[lsu_bus_buffer.scala 207:56] + node ibuf_wr_en = and(_T_853, _T_854) @[lsu_bus_buffer.scala 207:54] + wire ibuf_drain_vld : UInt<1> + ibuf_drain_vld <= UInt<1>("h00") + node _T_855 = eq(ibuf_wr_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 209:36] + node _T_856 = and(ibuf_drain_vld, _T_855) @[lsu_bus_buffer.scala 209:34] + node ibuf_rst = or(_T_856, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 209:49] + node _T_857 = eq(io.lsu_busreq_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 210:44] + node _T_858 = and(io.lsu_busreq_m, _T_857) @[lsu_bus_buffer.scala 210:42] + node _T_859 = and(_T_858, ibuf_valid) @[lsu_bus_buffer.scala 210:61] + node _T_860 = bits(ibuf_addr, 31, 2) @[lsu_bus_buffer.scala 210:112] + node _T_861 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 210:137] + node _T_862 = neq(_T_860, _T_861) @[lsu_bus_buffer.scala 210:120] + node _T_863 = or(io.lsu_pkt_m.bits.load, _T_862) @[lsu_bus_buffer.scala 210:100] + node ibuf_force_drain = and(_T_859, _T_863) @[lsu_bus_buffer.scala 210:74] + wire ibuf_sideeffect : UInt<1> + ibuf_sideeffect <= UInt<1>("h00") + wire ibuf_timer : UInt<3> + ibuf_timer <= UInt<1>("h00") + wire ibuf_merge_en : UInt<1> + ibuf_merge_en <= UInt<1>("h00") + wire ibuf_merge_in : UInt<1> + ibuf_merge_in <= UInt<1>("h00") + node _T_864 = eq(ibuf_timer, UInt<3>("h07")) @[lsu_bus_buffer.scala 215:62] + node _T_865 = or(ibuf_wr_en, _T_864) @[lsu_bus_buffer.scala 215:48] + node _T_866 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 215:98] + node _T_867 = eq(_T_866, UInt<1>("h00")) @[lsu_bus_buffer.scala 215:82] + node _T_868 = and(_T_865, _T_867) @[lsu_bus_buffer.scala 215:80] + node _T_869 = or(_T_868, ibuf_byp) @[lsu_bus_buffer.scala 216:5] + node _T_870 = or(_T_869, ibuf_force_drain) @[lsu_bus_buffer.scala 216:16] + node _T_871 = or(_T_870, ibuf_sideeffect) @[lsu_bus_buffer.scala 216:35] + node _T_872 = eq(ibuf_write, UInt<1>("h00")) @[lsu_bus_buffer.scala 216:55] + node _T_873 = or(_T_871, _T_872) @[lsu_bus_buffer.scala 216:53] + node _T_874 = or(_T_873, bus_coalescing_disable) @[lsu_bus_buffer.scala 216:67] + node _T_875 = and(ibuf_valid, _T_874) @[lsu_bus_buffer.scala 215:32] + ibuf_drain_vld <= _T_875 @[lsu_bus_buffer.scala 215:18] + wire ibuf_tag : UInt<2> + ibuf_tag <= UInt<1>("h00") + wire WrPtr1_r : UInt<2> + WrPtr1_r <= UInt<1>("h00") + wire WrPtr0_r : UInt<2> + WrPtr0_r <= UInt<1>("h00") + node _T_876 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 221:39] + node _T_877 = mux(io.ldst_dual_r, WrPtr1_r, WrPtr0_r) @[lsu_bus_buffer.scala 221:69] + node ibuf_tag_in = mux(_T_876, ibuf_tag, _T_877) @[lsu_bus_buffer.scala 221:24] + node ibuf_sz_in = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58] + node ibuf_addr_in = mux(io.ldst_dual_r, io.end_addr_r, io.lsu_addr_r) @[lsu_bus_buffer.scala 224:25] + node _T_878 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 225:42] + node _T_879 = bits(ibuf_byteen, 3, 0) @[lsu_bus_buffer.scala 225:70] + node _T_880 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 225:95] + node _T_881 = or(_T_879, _T_880) @[lsu_bus_buffer.scala 225:77] + node _T_882 = bits(ldst_byteen_hi_r, 3, 0) @[lsu_bus_buffer.scala 226:41] + node _T_883 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 226:65] + node _T_884 = mux(io.ldst_dual_r, _T_882, _T_883) @[lsu_bus_buffer.scala 226:8] + node ibuf_byteen_in = mux(_T_878, _T_881, _T_884) @[lsu_bus_buffer.scala 225:27] + node _T_885 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 229:61] + node _T_886 = bits(ldst_byteen_lo_r, 0, 0) @[lsu_bus_buffer.scala 230:25] + node _T_887 = bits(store_data_lo_r, 7, 0) @[lsu_bus_buffer.scala 230:45] + node _T_888 = bits(ibuf_data, 7, 0) @[lsu_bus_buffer.scala 230:76] + node _T_889 = mux(_T_886, _T_887, _T_888) @[lsu_bus_buffer.scala 230:8] + node _T_890 = bits(store_data_hi_r, 7, 0) @[lsu_bus_buffer.scala 231:40] + node _T_891 = bits(store_data_lo_r, 7, 0) @[lsu_bus_buffer.scala 231:77] + node _T_892 = mux(io.ldst_dual_r, _T_890, _T_891) @[lsu_bus_buffer.scala 231:8] + node _T_893 = mux(_T_885, _T_889, _T_892) @[lsu_bus_buffer.scala 229:46] + node _T_894 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 229:61] + node _T_895 = bits(ldst_byteen_lo_r, 1, 1) @[lsu_bus_buffer.scala 230:25] + node _T_896 = bits(store_data_lo_r, 15, 8) @[lsu_bus_buffer.scala 230:45] + node _T_897 = bits(ibuf_data, 15, 8) @[lsu_bus_buffer.scala 230:76] + node _T_898 = mux(_T_895, _T_896, _T_897) @[lsu_bus_buffer.scala 230:8] + node _T_899 = bits(store_data_hi_r, 15, 8) @[lsu_bus_buffer.scala 231:40] + node _T_900 = bits(store_data_lo_r, 15, 8) @[lsu_bus_buffer.scala 231:77] + node _T_901 = mux(io.ldst_dual_r, _T_899, _T_900) @[lsu_bus_buffer.scala 231:8] + node _T_902 = mux(_T_894, _T_898, _T_901) @[lsu_bus_buffer.scala 229:46] + node _T_903 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 229:61] + node _T_904 = bits(ldst_byteen_lo_r, 2, 2) @[lsu_bus_buffer.scala 230:25] + node _T_905 = bits(store_data_lo_r, 23, 16) @[lsu_bus_buffer.scala 230:45] + node _T_906 = bits(ibuf_data, 23, 16) @[lsu_bus_buffer.scala 230:76] + node _T_907 = mux(_T_904, _T_905, _T_906) @[lsu_bus_buffer.scala 230:8] + node _T_908 = bits(store_data_hi_r, 23, 16) @[lsu_bus_buffer.scala 231:40] + node _T_909 = bits(store_data_lo_r, 23, 16) @[lsu_bus_buffer.scala 231:77] + node _T_910 = mux(io.ldst_dual_r, _T_908, _T_909) @[lsu_bus_buffer.scala 231:8] + node _T_911 = mux(_T_903, _T_907, _T_910) @[lsu_bus_buffer.scala 229:46] + node _T_912 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 229:61] + node _T_913 = bits(ldst_byteen_lo_r, 3, 3) @[lsu_bus_buffer.scala 230:25] + node _T_914 = bits(store_data_lo_r, 31, 24) @[lsu_bus_buffer.scala 230:45] + node _T_915 = bits(ibuf_data, 31, 24) @[lsu_bus_buffer.scala 230:76] + node _T_916 = mux(_T_913, _T_914, _T_915) @[lsu_bus_buffer.scala 230:8] + node _T_917 = bits(store_data_hi_r, 31, 24) @[lsu_bus_buffer.scala 231:40] + node _T_918 = bits(store_data_lo_r, 31, 24) @[lsu_bus_buffer.scala 231:77] + node _T_919 = mux(io.ldst_dual_r, _T_917, _T_918) @[lsu_bus_buffer.scala 231:8] + node _T_920 = mux(_T_912, _T_916, _T_919) @[lsu_bus_buffer.scala 229:46] + node _T_921 = cat(_T_920, _T_911) @[Cat.scala 29:58] + node _T_922 = cat(_T_921, _T_902) @[Cat.scala 29:58] + node ibuf_data_in = cat(_T_922, _T_893) @[Cat.scala 29:58] + node _T_923 = lt(ibuf_timer, UInt<3>("h07")) @[lsu_bus_buffer.scala 232:59] + node _T_924 = bits(_T_923, 0, 0) @[lsu_bus_buffer.scala 232:79] + node _T_925 = add(ibuf_timer, UInt<1>("h01")) @[lsu_bus_buffer.scala 232:93] + node _T_926 = tail(_T_925, 1) @[lsu_bus_buffer.scala 232:93] + node _T_927 = mux(_T_924, _T_926, ibuf_timer) @[lsu_bus_buffer.scala 232:47] + node ibuf_timer_in = mux(ibuf_wr_en, UInt<1>("h00"), _T_927) @[lsu_bus_buffer.scala 232:26] + node _T_928 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 234:36] + node _T_929 = and(_T_928, io.lsu_pkt_r.bits.store) @[lsu_bus_buffer.scala 234:54] + node _T_930 = and(_T_929, ibuf_valid) @[lsu_bus_buffer.scala 234:80] + node _T_931 = and(_T_930, ibuf_write) @[lsu_bus_buffer.scala 234:93] + node _T_932 = bits(io.lsu_addr_r, 31, 2) @[lsu_bus_buffer.scala 234:122] + node _T_933 = bits(ibuf_addr, 31, 2) @[lsu_bus_buffer.scala 234:142] + node _T_934 = eq(_T_932, _T_933) @[lsu_bus_buffer.scala 234:129] + node _T_935 = and(_T_931, _T_934) @[lsu_bus_buffer.scala 234:106] + node _T_936 = eq(io.is_sideeffects_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 234:152] + node _T_937 = and(_T_935, _T_936) @[lsu_bus_buffer.scala 234:150] + node _T_938 = eq(bus_coalescing_disable, UInt<1>("h00")) @[lsu_bus_buffer.scala 234:175] + node _T_939 = and(_T_937, _T_938) @[lsu_bus_buffer.scala 234:173] + ibuf_merge_en <= _T_939 @[lsu_bus_buffer.scala 234:17] + node _T_940 = eq(io.ldst_dual_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 235:20] + ibuf_merge_in <= _T_940 @[lsu_bus_buffer.scala 235:17] + node _T_941 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 236:65] + node _T_942 = and(ibuf_merge_en, _T_941) @[lsu_bus_buffer.scala 236:63] + node _T_943 = bits(ibuf_byteen, 0, 0) @[lsu_bus_buffer.scala 236:92] + node _T_944 = bits(ldst_byteen_lo_r, 0, 0) @[lsu_bus_buffer.scala 236:114] + node _T_945 = or(_T_943, _T_944) @[lsu_bus_buffer.scala 236:96] + node _T_946 = bits(ibuf_byteen, 0, 0) @[lsu_bus_buffer.scala 236:130] + node _T_947 = mux(_T_942, _T_945, _T_946) @[lsu_bus_buffer.scala 236:48] + node _T_948 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 236:65] + node _T_949 = and(ibuf_merge_en, _T_948) @[lsu_bus_buffer.scala 236:63] + node _T_950 = bits(ibuf_byteen, 1, 1) @[lsu_bus_buffer.scala 236:92] + node _T_951 = bits(ldst_byteen_lo_r, 1, 1) @[lsu_bus_buffer.scala 236:114] + node _T_952 = or(_T_950, _T_951) @[lsu_bus_buffer.scala 236:96] + node _T_953 = bits(ibuf_byteen, 1, 1) @[lsu_bus_buffer.scala 236:130] + node _T_954 = mux(_T_949, _T_952, _T_953) @[lsu_bus_buffer.scala 236:48] + node _T_955 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 236:65] + node _T_956 = and(ibuf_merge_en, _T_955) @[lsu_bus_buffer.scala 236:63] + node _T_957 = bits(ibuf_byteen, 2, 2) @[lsu_bus_buffer.scala 236:92] + node _T_958 = bits(ldst_byteen_lo_r, 2, 2) @[lsu_bus_buffer.scala 236:114] + node _T_959 = or(_T_957, _T_958) @[lsu_bus_buffer.scala 236:96] + node _T_960 = bits(ibuf_byteen, 2, 2) @[lsu_bus_buffer.scala 236:130] + node _T_961 = mux(_T_956, _T_959, _T_960) @[lsu_bus_buffer.scala 236:48] + node _T_962 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 236:65] + node _T_963 = and(ibuf_merge_en, _T_962) @[lsu_bus_buffer.scala 236:63] + node _T_964 = bits(ibuf_byteen, 3, 3) @[lsu_bus_buffer.scala 236:92] + node _T_965 = bits(ldst_byteen_lo_r, 3, 3) @[lsu_bus_buffer.scala 236:114] + node _T_966 = or(_T_964, _T_965) @[lsu_bus_buffer.scala 236:96] + node _T_967 = bits(ibuf_byteen, 3, 3) @[lsu_bus_buffer.scala 236:130] + node _T_968 = mux(_T_963, _T_966, _T_967) @[lsu_bus_buffer.scala 236:48] + node _T_969 = cat(_T_968, _T_961) @[Cat.scala 29:58] + node _T_970 = cat(_T_969, _T_954) @[Cat.scala 29:58] + node ibuf_byteen_out = cat(_T_970, _T_947) @[Cat.scala 29:58] + node _T_971 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 237:62] + node _T_972 = and(ibuf_merge_en, _T_971) @[lsu_bus_buffer.scala 237:60] + node _T_973 = bits(ldst_byteen_lo_r, 0, 0) @[lsu_bus_buffer.scala 237:98] + node _T_974 = bits(store_data_lo_r, 7, 0) @[lsu_bus_buffer.scala 237:118] + node _T_975 = bits(ibuf_data, 7, 0) @[lsu_bus_buffer.scala 237:143] + node _T_976 = mux(_T_973, _T_974, _T_975) @[lsu_bus_buffer.scala 237:81] + node _T_977 = bits(ibuf_data, 7, 0) @[lsu_bus_buffer.scala 237:169] + node _T_978 = mux(_T_972, _T_976, _T_977) @[lsu_bus_buffer.scala 237:45] + node _T_979 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 237:62] + node _T_980 = and(ibuf_merge_en, _T_979) @[lsu_bus_buffer.scala 237:60] + node _T_981 = bits(ldst_byteen_lo_r, 1, 1) @[lsu_bus_buffer.scala 237:98] + node _T_982 = bits(store_data_lo_r, 15, 8) @[lsu_bus_buffer.scala 237:118] + node _T_983 = bits(ibuf_data, 15, 8) @[lsu_bus_buffer.scala 237:143] + node _T_984 = mux(_T_981, _T_982, _T_983) @[lsu_bus_buffer.scala 237:81] + node _T_985 = bits(ibuf_data, 15, 8) @[lsu_bus_buffer.scala 237:169] + node _T_986 = mux(_T_980, _T_984, _T_985) @[lsu_bus_buffer.scala 237:45] + node _T_987 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 237:62] + node _T_988 = and(ibuf_merge_en, _T_987) @[lsu_bus_buffer.scala 237:60] + node _T_989 = bits(ldst_byteen_lo_r, 2, 2) @[lsu_bus_buffer.scala 237:98] + node _T_990 = bits(store_data_lo_r, 23, 16) @[lsu_bus_buffer.scala 237:118] + node _T_991 = bits(ibuf_data, 23, 16) @[lsu_bus_buffer.scala 237:143] + node _T_992 = mux(_T_989, _T_990, _T_991) @[lsu_bus_buffer.scala 237:81] + node _T_993 = bits(ibuf_data, 23, 16) @[lsu_bus_buffer.scala 237:169] + node _T_994 = mux(_T_988, _T_992, _T_993) @[lsu_bus_buffer.scala 237:45] + node _T_995 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 237:62] + node _T_996 = and(ibuf_merge_en, _T_995) @[lsu_bus_buffer.scala 237:60] + node _T_997 = bits(ldst_byteen_lo_r, 3, 3) @[lsu_bus_buffer.scala 237:98] + node _T_998 = bits(store_data_lo_r, 31, 24) @[lsu_bus_buffer.scala 237:118] + node _T_999 = bits(ibuf_data, 31, 24) @[lsu_bus_buffer.scala 237:143] + node _T_1000 = mux(_T_997, _T_998, _T_999) @[lsu_bus_buffer.scala 237:81] + node _T_1001 = bits(ibuf_data, 31, 24) @[lsu_bus_buffer.scala 237:169] + node _T_1002 = mux(_T_996, _T_1000, _T_1001) @[lsu_bus_buffer.scala 237:45] + node _T_1003 = cat(_T_1002, _T_994) @[Cat.scala 29:58] + node _T_1004 = cat(_T_1003, _T_986) @[Cat.scala 29:58] + node ibuf_data_out = cat(_T_1004, _T_978) @[Cat.scala 29:58] + node _T_1005 = mux(ibuf_wr_en, UInt<1>("h01"), ibuf_valid) @[lsu_bus_buffer.scala 239:58] + node _T_1006 = eq(ibuf_rst, UInt<1>("h00")) @[lsu_bus_buffer.scala 239:93] + node _T_1007 = and(_T_1005, _T_1006) @[lsu_bus_buffer.scala 239:91] + reg _T_1008 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 239:54] + _T_1008 <= _T_1007 @[lsu_bus_buffer.scala 239:54] + ibuf_valid <= _T_1008 @[lsu_bus_buffer.scala 239:14] + reg _T_1009 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + _T_1009 <= ibuf_tag_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ibuf_tag <= _T_1009 @[lsu_bus_buffer.scala 240:12] + reg ibuf_dualtag : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_dualtag <= WrPtr0_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg ibuf_dual : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_dual <= io.ldst_dual_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg ibuf_samedw : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_samedw <= ldst_samedw_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg ibuf_nomerge : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_nomerge <= io.no_dword_merge_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg _T_1010 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + _T_1010 <= io.is_sideeffects_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ibuf_sideeffect <= _T_1010 @[lsu_bus_buffer.scala 245:19] + reg ibuf_unsign : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_unsign <= io.lsu_pkt_r.bits.unsign @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg _T_1011 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + _T_1011 <= io.lsu_pkt_r.bits.store @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ibuf_write <= _T_1011 @[lsu_bus_buffer.scala 247:14] + reg ibuf_sz : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_sz <= ibuf_sz_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + inst rvclkhdr of rvclkhdr @[lib.scala 368:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[lib.scala 370:18] + rvclkhdr.io.en <= ibuf_wr_en @[lib.scala 371:17] + rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_1012 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_1012 <= ibuf_addr_in @[lib.scala 374:16] + ibuf_addr <= _T_1012 @[lsu_bus_buffer.scala 249:13] + reg _T_1013 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + _T_1013 <= ibuf_byteen_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ibuf_byteen <= _T_1013 @[lsu_bus_buffer.scala 250:15] + inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 368:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_1.io.en <= ibuf_wr_en @[lib.scala 371:17] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_1014 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_1014 <= ibuf_data_in @[lib.scala 374:16] + ibuf_data <= _T_1014 @[lsu_bus_buffer.scala 251:13] + reg _T_1015 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 252:55] + _T_1015 <= ibuf_timer_in @[lsu_bus_buffer.scala 252:55] + ibuf_timer <= _T_1015 @[lsu_bus_buffer.scala 252:14] + wire buf_numvld_wrcmd_any : UInt<4> + buf_numvld_wrcmd_any <= UInt<1>("h00") + wire buf_numvld_cmd_any : UInt<4> + buf_numvld_cmd_any <= UInt<1>("h00") + wire obuf_wr_timer : UInt<3> + obuf_wr_timer <= UInt<1>("h00") + wire buf_nomerge : UInt<1>[4] @[lsu_bus_buffer.scala 256:25] + buf_nomerge[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 257:15] + buf_nomerge[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 257:15] + buf_nomerge[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 257:15] + buf_nomerge[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 257:15] + wire buf_sideeffect : UInt<4> + buf_sideeffect <= UInt<1>("h00") + wire obuf_force_wr_en : UInt<1> + obuf_force_wr_en <= UInt<1>("h00") + wire obuf_wr_en : UInt<1> + obuf_wr_en <= UInt<1>("h00") + node _T_1016 = eq(buf_numvld_wrcmd_any, UInt<1>("h01")) @[lsu_bus_buffer.scala 262:43] + node _T_1017 = eq(buf_numvld_cmd_any, UInt<1>("h01")) @[lsu_bus_buffer.scala 262:72] + node _T_1018 = and(_T_1016, _T_1017) @[lsu_bus_buffer.scala 262:51] + node _T_1019 = neq(obuf_wr_timer, UInt<3>("h07")) @[lsu_bus_buffer.scala 262:97] + node _T_1020 = and(_T_1018, _T_1019) @[lsu_bus_buffer.scala 262:80] + node _T_1021 = eq(bus_coalescing_disable, UInt<1>("h00")) @[lsu_bus_buffer.scala 263:5] + node _T_1022 = and(_T_1020, _T_1021) @[lsu_bus_buffer.scala 262:114] + node _T_1023 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 263:114] + node _T_1024 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 263:114] + node _T_1025 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 263:114] + node _T_1026 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 263:114] + node _T_1027 = mux(_T_1023, buf_nomerge[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1028 = mux(_T_1024, buf_nomerge[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1029 = mux(_T_1025, buf_nomerge[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1030 = mux(_T_1026, buf_nomerge[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1031 = or(_T_1027, _T_1028) @[Mux.scala 27:72] + node _T_1032 = or(_T_1031, _T_1029) @[Mux.scala 27:72] + node _T_1033 = or(_T_1032, _T_1030) @[Mux.scala 27:72] + wire _T_1034 : UInt<1> @[Mux.scala 27:72] + _T_1034 <= _T_1033 @[Mux.scala 27:72] + node _T_1035 = eq(_T_1034, UInt<1>("h00")) @[lsu_bus_buffer.scala 263:31] + node _T_1036 = and(_T_1022, _T_1035) @[lsu_bus_buffer.scala 263:29] + node _T_1037 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 264:88] + node _T_1038 = bits(buf_sideeffect, 0, 0) @[lsu_bus_buffer.scala 264:111] + node _T_1039 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 264:88] + node _T_1040 = bits(buf_sideeffect, 1, 1) @[lsu_bus_buffer.scala 264:111] + node _T_1041 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 264:88] + node _T_1042 = bits(buf_sideeffect, 2, 2) @[lsu_bus_buffer.scala 264:111] + node _T_1043 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 264:88] + node _T_1044 = bits(buf_sideeffect, 3, 3) @[lsu_bus_buffer.scala 264:111] + node _T_1045 = mux(_T_1037, _T_1038, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1046 = mux(_T_1039, _T_1040, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1047 = mux(_T_1041, _T_1042, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1048 = mux(_T_1043, _T_1044, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1049 = or(_T_1045, _T_1046) @[Mux.scala 27:72] + node _T_1050 = or(_T_1049, _T_1047) @[Mux.scala 27:72] + node _T_1051 = or(_T_1050, _T_1048) @[Mux.scala 27:72] + wire _T_1052 : UInt<1> @[Mux.scala 27:72] + _T_1052 <= _T_1051 @[Mux.scala 27:72] + node _T_1053 = eq(_T_1052, UInt<1>("h00")) @[lsu_bus_buffer.scala 264:5] + node _T_1054 = and(_T_1036, _T_1053) @[lsu_bus_buffer.scala 263:140] + node _T_1055 = eq(obuf_force_wr_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 264:119] + node obuf_wr_wait = and(_T_1054, _T_1055) @[lsu_bus_buffer.scala 264:117] + node _T_1056 = orr(buf_numvld_cmd_any) @[lsu_bus_buffer.scala 265:75] + node _T_1057 = lt(obuf_wr_timer, UInt<3>("h07")) @[lsu_bus_buffer.scala 265:95] + node _T_1058 = and(_T_1056, _T_1057) @[lsu_bus_buffer.scala 265:79] + node _T_1059 = add(obuf_wr_timer, UInt<1>("h01")) @[lsu_bus_buffer.scala 265:123] + node _T_1060 = tail(_T_1059, 1) @[lsu_bus_buffer.scala 265:123] + node _T_1061 = mux(_T_1058, _T_1060, obuf_wr_timer) @[lsu_bus_buffer.scala 265:55] + node obuf_wr_timer_in = mux(obuf_wr_en, UInt<3>("h00"), _T_1061) @[lsu_bus_buffer.scala 265:29] + node _T_1062 = eq(io.lsu_busreq_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 266:41] + node _T_1063 = and(io.lsu_busreq_m, _T_1062) @[lsu_bus_buffer.scala 266:39] + node _T_1064 = eq(ibuf_valid, UInt<1>("h00")) @[lsu_bus_buffer.scala 266:60] + node _T_1065 = and(_T_1063, _T_1064) @[lsu_bus_buffer.scala 266:58] + node _T_1066 = eq(buf_numvld_cmd_any, UInt<1>("h01")) @[lsu_bus_buffer.scala 266:93] + node _T_1067 = and(_T_1065, _T_1066) @[lsu_bus_buffer.scala 266:72] + node _T_1068 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 266:117] + node _T_1069 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 266:208] + node _T_1070 = bits(buf_addr[0], 31, 2) @[lsu_bus_buffer.scala 266:228] + node _T_1071 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 266:208] + node _T_1072 = bits(buf_addr[1], 31, 2) @[lsu_bus_buffer.scala 266:228] + node _T_1073 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 266:208] + node _T_1074 = bits(buf_addr[2], 31, 2) @[lsu_bus_buffer.scala 266:228] + node _T_1075 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 266:208] + node _T_1076 = bits(buf_addr[3], 31, 2) @[lsu_bus_buffer.scala 266:228] + node _T_1077 = mux(_T_1069, _T_1070, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1078 = mux(_T_1071, _T_1072, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1079 = mux(_T_1073, _T_1074, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1080 = mux(_T_1075, _T_1076, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1081 = or(_T_1077, _T_1078) @[Mux.scala 27:72] + node _T_1082 = or(_T_1081, _T_1079) @[Mux.scala 27:72] + node _T_1083 = or(_T_1082, _T_1080) @[Mux.scala 27:72] + wire _T_1084 : UInt<30> @[Mux.scala 27:72] + _T_1084 <= _T_1083 @[Mux.scala 27:72] + node _T_1085 = neq(_T_1068, _T_1084) @[lsu_bus_buffer.scala 266:123] + node _T_1086 = and(_T_1067, _T_1085) @[lsu_bus_buffer.scala 266:101] + obuf_force_wr_en <= _T_1086 @[lsu_bus_buffer.scala 266:20] + wire buf_numvld_pend_any : UInt<4> + buf_numvld_pend_any <= UInt<1>("h00") + node _T_1087 = eq(buf_numvld_pend_any, UInt<1>("h00")) @[lsu_bus_buffer.scala 268:53] + node _T_1088 = and(ibuf_byp, _T_1087) @[lsu_bus_buffer.scala 268:31] + node _T_1089 = eq(io.lsu_pkt_r.bits.store, UInt<1>("h00")) @[lsu_bus_buffer.scala 268:64] + node _T_1090 = or(_T_1089, io.no_dword_merge_r) @[lsu_bus_buffer.scala 268:89] + node ibuf_buf_byp = and(_T_1088, _T_1090) @[lsu_bus_buffer.scala 268:61] + wire bus_sideeffect_pend : UInt<1> + bus_sideeffect_pend <= UInt<1>("h00") + wire found_cmdptr0 : UInt<1> + found_cmdptr0 <= UInt<1>("h00") + wire buf_cmd_state_bus_en : UInt<1>[4] @[lsu_bus_buffer.scala 271:34] + buf_cmd_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 272:24] + buf_cmd_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 272:24] + buf_cmd_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 272:24] + buf_cmd_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 272:24] + wire buf_dual : UInt<1>[4] @[lsu_bus_buffer.scala 273:22] + buf_dual[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 274:12] + buf_dual[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 274:12] + buf_dual[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 274:12] + buf_dual[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 274:12] + wire buf_samedw : UInt<1>[4] @[lsu_bus_buffer.scala 275:24] + buf_samedw[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 276:14] + buf_samedw[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 276:14] + buf_samedw[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 276:14] + buf_samedw[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 276:14] + wire found_cmdptr1 : UInt<1> + found_cmdptr1 <= UInt<1>("h00") + wire bus_cmd_ready : UInt<1> + bus_cmd_ready <= UInt<1>("h00") + wire obuf_valid : UInt<1> + obuf_valid <= UInt<1>("h00") + wire obuf_nosend : UInt<1> + obuf_nosend <= UInt<1>("h00") + wire lsu_bus_cntr_overflow : UInt<1> + lsu_bus_cntr_overflow <= UInt<1>("h00") + wire bus_addr_match_pending : UInt<1> + bus_addr_match_pending <= UInt<1>("h00") + node _T_1091 = and(ibuf_buf_byp, io.lsu_commit_r) @[lsu_bus_buffer.scala 283:32] + node _T_1092 = and(io.is_sideeffects_r, bus_sideeffect_pend) @[lsu_bus_buffer.scala 283:74] + node _T_1093 = eq(_T_1092, UInt<1>("h00")) @[lsu_bus_buffer.scala 283:52] + node _T_1094 = and(_T_1091, _T_1093) @[lsu_bus_buffer.scala 283:50] + node _T_1095 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1096 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1097 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1098 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] + node _T_1099 = mux(_T_1095, buf_state[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1100 = mux(_T_1096, buf_state[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1101 = mux(_T_1097, buf_state[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1102 = mux(_T_1098, buf_state[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1103 = or(_T_1099, _T_1100) @[Mux.scala 27:72] + node _T_1104 = or(_T_1103, _T_1101) @[Mux.scala 27:72] + node _T_1105 = or(_T_1104, _T_1102) @[Mux.scala 27:72] + wire _T_1106 : UInt<3> @[Mux.scala 27:72] + _T_1106 <= _T_1105 @[Mux.scala 27:72] + node _T_1107 = eq(_T_1106, UInt<3>("h02")) @[lsu_bus_buffer.scala 284:36] + node _T_1108 = and(_T_1107, found_cmdptr0) @[lsu_bus_buffer.scala 284:47] + node _T_1109 = cat(buf_cmd_state_bus_en[3], buf_cmd_state_bus_en[2]) @[Cat.scala 29:58] + node _T_1110 = cat(_T_1109, buf_cmd_state_bus_en[1]) @[Cat.scala 29:58] + node _T_1111 = cat(_T_1110, buf_cmd_state_bus_en[0]) @[Cat.scala 29:58] + node _T_1112 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_1113 = bits(_T_1111, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_1114 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_1115 = bits(_T_1111, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_1116 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_1117 = bits(_T_1111, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_1118 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_1119 = bits(_T_1111, 3, 3) @[lsu_bus_buffer.scala 57:129] + node _T_1120 = mux(_T_1112, _T_1113, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1121 = mux(_T_1114, _T_1115, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1122 = mux(_T_1116, _T_1117, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1123 = mux(_T_1118, _T_1119, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1124 = or(_T_1120, _T_1121) @[Mux.scala 27:72] + node _T_1125 = or(_T_1124, _T_1122) @[Mux.scala 27:72] + node _T_1126 = or(_T_1125, _T_1123) @[Mux.scala 27:72] + wire _T_1127 : UInt<1> @[Mux.scala 27:72] + _T_1127 <= _T_1126 @[Mux.scala 27:72] + node _T_1128 = eq(_T_1127, UInt<1>("h00")) @[lsu_bus_buffer.scala 285:23] + node _T_1129 = and(_T_1108, _T_1128) @[lsu_bus_buffer.scala 285:21] + node _T_1130 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_1131 = bits(buf_sideeffect, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_1132 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_1133 = bits(buf_sideeffect, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_1134 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_1135 = bits(buf_sideeffect, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_1136 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_1137 = bits(buf_sideeffect, 3, 3) @[lsu_bus_buffer.scala 57:129] + node _T_1138 = mux(_T_1130, _T_1131, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1139 = mux(_T_1132, _T_1133, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1140 = mux(_T_1134, _T_1135, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1141 = mux(_T_1136, _T_1137, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1142 = or(_T_1138, _T_1139) @[Mux.scala 27:72] + node _T_1143 = or(_T_1142, _T_1140) @[Mux.scala 27:72] + node _T_1144 = or(_T_1143, _T_1141) @[Mux.scala 27:72] + wire _T_1145 : UInt<1> @[Mux.scala 27:72] + _T_1145 <= _T_1144 @[Mux.scala 27:72] + node _T_1146 = and(_T_1145, bus_sideeffect_pend) @[lsu_bus_buffer.scala 285:141] + node _T_1147 = eq(_T_1146, UInt<1>("h00")) @[lsu_bus_buffer.scala 285:105] + node _T_1148 = and(_T_1129, _T_1147) @[lsu_bus_buffer.scala 285:103] + node _T_1149 = cat(buf_dual[3], buf_dual[2]) @[Cat.scala 29:58] + node _T_1150 = cat(_T_1149, buf_dual[1]) @[Cat.scala 29:58] + node _T_1151 = cat(_T_1150, buf_dual[0]) @[Cat.scala 29:58] + node _T_1152 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_1153 = bits(_T_1151, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_1154 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_1155 = bits(_T_1151, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_1156 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_1157 = bits(_T_1151, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_1158 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_1159 = bits(_T_1151, 3, 3) @[lsu_bus_buffer.scala 57:129] + node _T_1160 = mux(_T_1152, _T_1153, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1161 = mux(_T_1154, _T_1155, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1162 = mux(_T_1156, _T_1157, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1163 = mux(_T_1158, _T_1159, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1164 = or(_T_1160, _T_1161) @[Mux.scala 27:72] + node _T_1165 = or(_T_1164, _T_1162) @[Mux.scala 27:72] + node _T_1166 = or(_T_1165, _T_1163) @[Mux.scala 27:72] + wire _T_1167 : UInt<1> @[Mux.scala 27:72] + _T_1167 <= _T_1166 @[Mux.scala 27:72] + node _T_1168 = cat(buf_samedw[3], buf_samedw[2]) @[Cat.scala 29:58] + node _T_1169 = cat(_T_1168, buf_samedw[1]) @[Cat.scala 29:58] + node _T_1170 = cat(_T_1169, buf_samedw[0]) @[Cat.scala 29:58] + node _T_1171 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_1172 = bits(_T_1170, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_1173 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_1174 = bits(_T_1170, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_1175 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_1176 = bits(_T_1170, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_1177 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_1178 = bits(_T_1170, 3, 3) @[lsu_bus_buffer.scala 57:129] + node _T_1179 = mux(_T_1171, _T_1172, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1180 = mux(_T_1173, _T_1174, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1181 = mux(_T_1175, _T_1176, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1182 = mux(_T_1177, _T_1178, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1183 = or(_T_1179, _T_1180) @[Mux.scala 27:72] + node _T_1184 = or(_T_1183, _T_1181) @[Mux.scala 27:72] + node _T_1185 = or(_T_1184, _T_1182) @[Mux.scala 27:72] + wire _T_1186 : UInt<1> @[Mux.scala 27:72] + _T_1186 <= _T_1185 @[Mux.scala 27:72] + node _T_1187 = and(_T_1167, _T_1186) @[lsu_bus_buffer.scala 286:77] + node _T_1188 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_1189 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_1190 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_1191 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_1192 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_1193 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_1194 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_1195 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 57:129] + node _T_1196 = mux(_T_1188, _T_1189, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1197 = mux(_T_1190, _T_1191, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1198 = mux(_T_1192, _T_1193, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1199 = mux(_T_1194, _T_1195, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1200 = or(_T_1196, _T_1197) @[Mux.scala 27:72] + node _T_1201 = or(_T_1200, _T_1198) @[Mux.scala 27:72] + node _T_1202 = or(_T_1201, _T_1199) @[Mux.scala 27:72] + wire _T_1203 : UInt<1> @[Mux.scala 27:72] + _T_1203 <= _T_1202 @[Mux.scala 27:72] + node _T_1204 = eq(_T_1203, UInt<1>("h00")) @[lsu_bus_buffer.scala 286:150] + node _T_1205 = and(_T_1187, _T_1204) @[lsu_bus_buffer.scala 286:148] + node _T_1206 = eq(_T_1205, UInt<1>("h00")) @[lsu_bus_buffer.scala 286:8] + node _T_1207 = or(_T_1206, found_cmdptr1) @[lsu_bus_buffer.scala 286:181] + node _T_1208 = cat(buf_nomerge[3], buf_nomerge[2]) @[Cat.scala 29:58] + node _T_1209 = cat(_T_1208, buf_nomerge[1]) @[Cat.scala 29:58] + node _T_1210 = cat(_T_1209, buf_nomerge[0]) @[Cat.scala 29:58] + node _T_1211 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_1212 = bits(_T_1210, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_1213 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_1214 = bits(_T_1210, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_1215 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_1216 = bits(_T_1210, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_1217 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_1218 = bits(_T_1210, 3, 3) @[lsu_bus_buffer.scala 57:129] + node _T_1219 = mux(_T_1211, _T_1212, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1220 = mux(_T_1213, _T_1214, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1221 = mux(_T_1215, _T_1216, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1222 = mux(_T_1217, _T_1218, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1223 = or(_T_1219, _T_1220) @[Mux.scala 27:72] + node _T_1224 = or(_T_1223, _T_1221) @[Mux.scala 27:72] + node _T_1225 = or(_T_1224, _T_1222) @[Mux.scala 27:72] + wire _T_1226 : UInt<1> @[Mux.scala 27:72] + _T_1226 <= _T_1225 @[Mux.scala 27:72] + node _T_1227 = or(_T_1207, _T_1226) @[lsu_bus_buffer.scala 286:197] + node _T_1228 = or(_T_1227, obuf_force_wr_en) @[lsu_bus_buffer.scala 286:269] + node _T_1229 = and(_T_1148, _T_1228) @[lsu_bus_buffer.scala 285:164] + node _T_1230 = or(_T_1094, _T_1229) @[lsu_bus_buffer.scala 283:98] + node _T_1231 = eq(obuf_valid, UInt<1>("h00")) @[lsu_bus_buffer.scala 287:48] + node _T_1232 = or(bus_cmd_ready, _T_1231) @[lsu_bus_buffer.scala 287:46] + node _T_1233 = or(_T_1232, obuf_nosend) @[lsu_bus_buffer.scala 287:60] + node _T_1234 = and(_T_1230, _T_1233) @[lsu_bus_buffer.scala 287:29] + node _T_1235 = eq(obuf_wr_wait, UInt<1>("h00")) @[lsu_bus_buffer.scala 287:77] + node _T_1236 = and(_T_1234, _T_1235) @[lsu_bus_buffer.scala 287:75] + node _T_1237 = eq(lsu_bus_cntr_overflow, UInt<1>("h00")) @[lsu_bus_buffer.scala 287:93] + node _T_1238 = and(_T_1236, _T_1237) @[lsu_bus_buffer.scala 287:91] + node _T_1239 = eq(bus_addr_match_pending, UInt<1>("h00")) @[lsu_bus_buffer.scala 287:118] + node _T_1240 = and(_T_1238, _T_1239) @[lsu_bus_buffer.scala 287:116] + node _T_1241 = and(_T_1240, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 287:142] + obuf_wr_en <= _T_1241 @[lsu_bus_buffer.scala 283:14] + wire bus_cmd_sent : UInt<1> + bus_cmd_sent <= UInt<1>("h00") + node _T_1242 = and(obuf_valid, obuf_nosend) @[lsu_bus_buffer.scala 289:47] + node _T_1243 = or(bus_cmd_sent, _T_1242) @[lsu_bus_buffer.scala 289:33] + node _T_1244 = eq(obuf_wr_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 289:65] + node _T_1245 = and(_T_1243, _T_1244) @[lsu_bus_buffer.scala 289:63] + node _T_1246 = and(_T_1245, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 289:77] + node obuf_rst = or(_T_1246, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 289:98] + node _T_1247 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_1248 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_1249 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_1250 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_1251 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_1252 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_1253 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_1254 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 57:129] + node _T_1255 = mux(_T_1247, _T_1248, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1256 = mux(_T_1249, _T_1250, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1257 = mux(_T_1251, _T_1252, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1258 = mux(_T_1253, _T_1254, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1259 = or(_T_1255, _T_1256) @[Mux.scala 27:72] + node _T_1260 = or(_T_1259, _T_1257) @[Mux.scala 27:72] + node _T_1261 = or(_T_1260, _T_1258) @[Mux.scala 27:72] + wire _T_1262 : UInt<1> @[Mux.scala 27:72] + _T_1262 <= _T_1261 @[Mux.scala 27:72] + node obuf_write_in = mux(ibuf_buf_byp, io.lsu_pkt_r.bits.store, _T_1262) @[lsu_bus_buffer.scala 290:26] + node _T_1263 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_1264 = bits(buf_sideeffect, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_1265 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_1266 = bits(buf_sideeffect, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_1267 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_1268 = bits(buf_sideeffect, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_1269 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_1270 = bits(buf_sideeffect, 3, 3) @[lsu_bus_buffer.scala 57:129] + node _T_1271 = mux(_T_1263, _T_1264, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1272 = mux(_T_1265, _T_1266, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1273 = mux(_T_1267, _T_1268, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1274 = mux(_T_1269, _T_1270, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1275 = or(_T_1271, _T_1272) @[Mux.scala 27:72] + node _T_1276 = or(_T_1275, _T_1273) @[Mux.scala 27:72] + node _T_1277 = or(_T_1276, _T_1274) @[Mux.scala 27:72] + wire _T_1278 : UInt<1> @[Mux.scala 27:72] + _T_1278 <= _T_1277 @[Mux.scala 27:72] + node obuf_sideeffect_in = mux(ibuf_buf_byp, io.is_sideeffects_r, _T_1278) @[lsu_bus_buffer.scala 291:31] + node _T_1279 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1280 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1281 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1282 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] + node _T_1283 = mux(_T_1279, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1284 = mux(_T_1280, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1285 = mux(_T_1281, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1286 = mux(_T_1282, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1287 = or(_T_1283, _T_1284) @[Mux.scala 27:72] + node _T_1288 = or(_T_1287, _T_1285) @[Mux.scala 27:72] + node _T_1289 = or(_T_1288, _T_1286) @[Mux.scala 27:72] + wire _T_1290 : UInt<32> @[Mux.scala 27:72] + _T_1290 <= _T_1289 @[Mux.scala 27:72] + node obuf_addr_in = mux(ibuf_buf_byp, io.lsu_addr_r, _T_1290) @[lsu_bus_buffer.scala 292:25] + wire buf_sz : UInt<2>[4] @[lsu_bus_buffer.scala 293:20] + buf_sz[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 294:10] + buf_sz[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 294:10] + buf_sz[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 294:10] + buf_sz[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 294:10] + node _T_1291 = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58] + node _T_1292 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1293 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1294 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1295 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] + node _T_1296 = mux(_T_1292, buf_sz[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1297 = mux(_T_1293, buf_sz[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1298 = mux(_T_1294, buf_sz[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1299 = mux(_T_1295, buf_sz[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1300 = or(_T_1296, _T_1297) @[Mux.scala 27:72] + node _T_1301 = or(_T_1300, _T_1298) @[Mux.scala 27:72] + node _T_1302 = or(_T_1301, _T_1299) @[Mux.scala 27:72] + wire _T_1303 : UInt<2> @[Mux.scala 27:72] + _T_1303 <= _T_1302 @[Mux.scala 27:72] + node obuf_sz_in = mux(ibuf_buf_byp, _T_1291, _T_1303) @[lsu_bus_buffer.scala 295:23] + wire obuf_merge_en : UInt<1> + obuf_merge_en <= UInt<1>("h00") + node obuf_tag0_in = mux(ibuf_buf_byp, WrPtr0_r, CmdPtr0) @[lsu_bus_buffer.scala 298:25] + node obuf_tag1_in = mux(ibuf_buf_byp, WrPtr1_r, CmdPtr1) @[lsu_bus_buffer.scala 300:25] + wire obuf_cmd_done : UInt<1> + obuf_cmd_done <= UInt<1>("h00") + wire bus_wcmd_sent : UInt<1> + bus_wcmd_sent <= UInt<1>("h00") + node _T_1304 = or(obuf_wr_en, obuf_rst) @[lsu_bus_buffer.scala 303:39] + node _T_1305 = eq(_T_1304, UInt<1>("h00")) @[lsu_bus_buffer.scala 303:26] + node _T_1306 = or(obuf_cmd_done, bus_wcmd_sent) @[lsu_bus_buffer.scala 303:68] + node obuf_cmd_done_in = and(_T_1305, _T_1306) @[lsu_bus_buffer.scala 303:51] + wire obuf_data_done : UInt<1> + obuf_data_done <= UInt<1>("h00") + wire bus_wdata_sent : UInt<1> + bus_wdata_sent <= UInt<1>("h00") + node _T_1307 = or(obuf_wr_en, obuf_rst) @[lsu_bus_buffer.scala 306:40] + node _T_1308 = eq(_T_1307, UInt<1>("h00")) @[lsu_bus_buffer.scala 306:27] + node _T_1309 = or(obuf_data_done, bus_wdata_sent) @[lsu_bus_buffer.scala 306:70] + node obuf_data_done_in = and(_T_1308, _T_1309) @[lsu_bus_buffer.scala 306:52] + node _T_1310 = bits(obuf_sz_in, 1, 0) @[lsu_bus_buffer.scala 307:67] + node _T_1311 = eq(_T_1310, UInt<1>("h00")) @[lsu_bus_buffer.scala 307:72] + node _T_1312 = bits(obuf_sz_in, 0, 0) @[lsu_bus_buffer.scala 307:92] + node _T_1313 = bits(obuf_addr_in, 0, 0) @[lsu_bus_buffer.scala 307:111] + node _T_1314 = eq(_T_1313, UInt<1>("h00")) @[lsu_bus_buffer.scala 307:98] + node _T_1315 = and(_T_1312, _T_1314) @[lsu_bus_buffer.scala 307:96] + node _T_1316 = or(_T_1311, _T_1315) @[lsu_bus_buffer.scala 307:79] + node _T_1317 = bits(obuf_sz_in, 1, 1) @[lsu_bus_buffer.scala 307:129] + node _T_1318 = bits(obuf_addr_in, 1, 0) @[lsu_bus_buffer.scala 307:147] + node _T_1319 = orr(_T_1318) @[lsu_bus_buffer.scala 307:153] + node _T_1320 = eq(_T_1319, UInt<1>("h00")) @[lsu_bus_buffer.scala 307:134] + node _T_1321 = and(_T_1317, _T_1320) @[lsu_bus_buffer.scala 307:132] + node _T_1322 = or(_T_1316, _T_1321) @[lsu_bus_buffer.scala 307:116] + node obuf_aligned_in = mux(ibuf_buf_byp, is_aligned_r, _T_1322) @[lsu_bus_buffer.scala 307:28] + wire obuf_nosend_in : UInt<1> + obuf_nosend_in <= UInt<1>("h00") + wire obuf_rdrsp_pend : UInt<1> + obuf_rdrsp_pend <= UInt<1>("h00") + wire bus_rsp_read : UInt<1> + bus_rsp_read <= UInt<1>("h00") + wire bus_rsp_read_tag : UInt<3> + bus_rsp_read_tag <= UInt<1>("h00") + wire obuf_rdrsp_tag : UInt<3> + obuf_rdrsp_tag <= UInt<1>("h00") + wire obuf_write : UInt<1> + obuf_write <= UInt<1>("h00") + node _T_1323 = eq(obuf_nosend_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 315:44] + node _T_1324 = and(obuf_wr_en, _T_1323) @[lsu_bus_buffer.scala 315:42] + node _T_1325 = eq(_T_1324, UInt<1>("h00")) @[lsu_bus_buffer.scala 315:29] + node _T_1326 = and(_T_1325, obuf_rdrsp_pend) @[lsu_bus_buffer.scala 315:61] + node _T_1327 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 315:116] + node _T_1328 = and(bus_rsp_read, _T_1327) @[lsu_bus_buffer.scala 315:96] + node _T_1329 = eq(_T_1328, UInt<1>("h00")) @[lsu_bus_buffer.scala 315:81] + node _T_1330 = and(_T_1326, _T_1329) @[lsu_bus_buffer.scala 315:79] + node _T_1331 = eq(obuf_write, UInt<1>("h00")) @[lsu_bus_buffer.scala 316:22] + node _T_1332 = and(bus_cmd_sent, _T_1331) @[lsu_bus_buffer.scala 316:20] + node _T_1333 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 316:37] + node _T_1334 = and(_T_1332, _T_1333) @[lsu_bus_buffer.scala 316:35] + node obuf_rdrsp_pend_in = or(_T_1330, _T_1334) @[lsu_bus_buffer.scala 315:138] + wire obuf_tag0 : UInt<3> + obuf_tag0 <= UInt<1>("h00") + node _T_1335 = eq(obuf_write, UInt<1>("h00")) @[lsu_bus_buffer.scala 318:46] + node _T_1336 = and(bus_cmd_sent, _T_1335) @[lsu_bus_buffer.scala 318:44] + node obuf_rdrsp_tag_in = mux(_T_1336, obuf_tag0, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 318:30] + wire obuf_addr : UInt<32> + obuf_addr <= UInt<1>("h00") + wire obuf_sideeffect : UInt<1> + obuf_sideeffect <= UInt<1>("h00") + node _T_1337 = bits(obuf_addr_in, 31, 3) @[lsu_bus_buffer.scala 321:34] + node _T_1338 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 321:52] + node _T_1339 = eq(_T_1337, _T_1338) @[lsu_bus_buffer.scala 321:40] + node _T_1340 = and(_T_1339, obuf_aligned_in) @[lsu_bus_buffer.scala 321:60] + node _T_1341 = eq(obuf_sideeffect, UInt<1>("h00")) @[lsu_bus_buffer.scala 321:80] + node _T_1342 = and(_T_1340, _T_1341) @[lsu_bus_buffer.scala 321:78] + node _T_1343 = eq(obuf_write, UInt<1>("h00")) @[lsu_bus_buffer.scala 321:99] + node _T_1344 = and(_T_1342, _T_1343) @[lsu_bus_buffer.scala 321:97] + node _T_1345 = eq(obuf_write_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 321:113] + node _T_1346 = and(_T_1344, _T_1345) @[lsu_bus_buffer.scala 321:111] + node _T_1347 = eq(io.tlu_busbuff.dec_tlu_external_ldfwd_disable, UInt<1>("h00")) @[lsu_bus_buffer.scala 321:130] + node _T_1348 = and(_T_1346, _T_1347) @[lsu_bus_buffer.scala 321:128] + node _T_1349 = eq(obuf_nosend, UInt<1>("h00")) @[lsu_bus_buffer.scala 322:20] + node _T_1350 = and(obuf_valid, _T_1349) @[lsu_bus_buffer.scala 322:18] + node _T_1351 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 322:90] + node _T_1352 = and(bus_rsp_read, _T_1351) @[lsu_bus_buffer.scala 322:70] + node _T_1353 = eq(_T_1352, UInt<1>("h00")) @[lsu_bus_buffer.scala 322:55] + node _T_1354 = and(obuf_rdrsp_pend, _T_1353) @[lsu_bus_buffer.scala 322:53] + node _T_1355 = or(_T_1350, _T_1354) @[lsu_bus_buffer.scala 322:34] + node _T_1356 = and(_T_1348, _T_1355) @[lsu_bus_buffer.scala 321:177] + obuf_nosend_in <= _T_1356 @[lsu_bus_buffer.scala 321:18] + node _T_1357 = bits(io.lsu_addr_r, 2, 2) @[lsu_bus_buffer.scala 323:60] + node _T_1358 = cat(ldst_byteen_lo_r, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_1359 = cat(UInt<4>("h00"), ldst_byteen_lo_r) @[Cat.scala 29:58] + node _T_1360 = mux(_T_1357, _T_1358, _T_1359) @[lsu_bus_buffer.scala 323:46] + node _T_1361 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1362 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1363 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1364 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] + node _T_1365 = mux(_T_1361, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1366 = mux(_T_1362, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1367 = mux(_T_1363, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1368 = mux(_T_1364, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1369 = or(_T_1365, _T_1366) @[Mux.scala 27:72] + node _T_1370 = or(_T_1369, _T_1367) @[Mux.scala 27:72] + node _T_1371 = or(_T_1370, _T_1368) @[Mux.scala 27:72] + wire _T_1372 : UInt<32> @[Mux.scala 27:72] + _T_1372 <= _T_1371 @[Mux.scala 27:72] + node _T_1373 = bits(_T_1372, 2, 2) @[lsu_bus_buffer.scala 324:36] + node _T_1374 = bits(_T_1373, 0, 0) @[lsu_bus_buffer.scala 324:46] + node _T_1375 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1376 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1377 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1378 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] + node _T_1379 = mux(_T_1375, buf_byteen[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1380 = mux(_T_1376, buf_byteen[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1381 = mux(_T_1377, buf_byteen[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1382 = mux(_T_1378, buf_byteen[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1383 = or(_T_1379, _T_1380) @[Mux.scala 27:72] + node _T_1384 = or(_T_1383, _T_1381) @[Mux.scala 27:72] + node _T_1385 = or(_T_1384, _T_1382) @[Mux.scala 27:72] + wire _T_1386 : UInt<4> @[Mux.scala 27:72] + _T_1386 <= _T_1385 @[Mux.scala 27:72] + node _T_1387 = cat(_T_1386, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_1388 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1389 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1390 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1391 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] + node _T_1392 = mux(_T_1388, buf_byteen[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1393 = mux(_T_1389, buf_byteen[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1394 = mux(_T_1390, buf_byteen[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1395 = mux(_T_1391, buf_byteen[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1396 = or(_T_1392, _T_1393) @[Mux.scala 27:72] + node _T_1397 = or(_T_1396, _T_1394) @[Mux.scala 27:72] + node _T_1398 = or(_T_1397, _T_1395) @[Mux.scala 27:72] + wire _T_1399 : UInt<4> @[Mux.scala 27:72] + _T_1399 <= _T_1398 @[Mux.scala 27:72] + node _T_1400 = cat(UInt<4>("h00"), _T_1399) @[Cat.scala 29:58] + node _T_1401 = mux(_T_1374, _T_1387, _T_1400) @[lsu_bus_buffer.scala 324:8] + node obuf_byteen0_in = mux(ibuf_buf_byp, _T_1360, _T_1401) @[lsu_bus_buffer.scala 323:28] + node _T_1402 = bits(io.end_addr_r, 2, 2) @[lsu_bus_buffer.scala 325:60] + node _T_1403 = cat(ldst_byteen_hi_r, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_1404 = cat(UInt<4>("h00"), ldst_byteen_hi_r) @[Cat.scala 29:58] + node _T_1405 = mux(_T_1402, _T_1403, _T_1404) @[lsu_bus_buffer.scala 325:46] + node _T_1406 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1407 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1408 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1409 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] + node _T_1410 = mux(_T_1406, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1411 = mux(_T_1407, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1412 = mux(_T_1408, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1413 = mux(_T_1409, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1414 = or(_T_1410, _T_1411) @[Mux.scala 27:72] + node _T_1415 = or(_T_1414, _T_1412) @[Mux.scala 27:72] + node _T_1416 = or(_T_1415, _T_1413) @[Mux.scala 27:72] + wire _T_1417 : UInt<32> @[Mux.scala 27:72] + _T_1417 <= _T_1416 @[Mux.scala 27:72] + node _T_1418 = bits(_T_1417, 2, 2) @[lsu_bus_buffer.scala 326:36] + node _T_1419 = bits(_T_1418, 0, 0) @[lsu_bus_buffer.scala 326:46] + node _T_1420 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1421 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1422 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1423 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] + node _T_1424 = mux(_T_1420, buf_byteen[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1425 = mux(_T_1421, buf_byteen[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1426 = mux(_T_1422, buf_byteen[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1427 = mux(_T_1423, buf_byteen[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1428 = or(_T_1424, _T_1425) @[Mux.scala 27:72] + node _T_1429 = or(_T_1428, _T_1426) @[Mux.scala 27:72] + node _T_1430 = or(_T_1429, _T_1427) @[Mux.scala 27:72] + wire _T_1431 : UInt<4> @[Mux.scala 27:72] + _T_1431 <= _T_1430 @[Mux.scala 27:72] + node _T_1432 = cat(_T_1431, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_1433 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1434 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1435 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1436 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] + node _T_1437 = mux(_T_1433, buf_byteen[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1438 = mux(_T_1434, buf_byteen[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1439 = mux(_T_1435, buf_byteen[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1440 = mux(_T_1436, buf_byteen[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1441 = or(_T_1437, _T_1438) @[Mux.scala 27:72] + node _T_1442 = or(_T_1441, _T_1439) @[Mux.scala 27:72] + node _T_1443 = or(_T_1442, _T_1440) @[Mux.scala 27:72] + wire _T_1444 : UInt<4> @[Mux.scala 27:72] + _T_1444 <= _T_1443 @[Mux.scala 27:72] + node _T_1445 = cat(UInt<4>("h00"), _T_1444) @[Cat.scala 29:58] + node _T_1446 = mux(_T_1419, _T_1432, _T_1445) @[lsu_bus_buffer.scala 326:8] + node obuf_byteen1_in = mux(ibuf_buf_byp, _T_1405, _T_1446) @[lsu_bus_buffer.scala 325:28] + node _T_1447 = bits(io.lsu_addr_r, 2, 2) @[lsu_bus_buffer.scala 328:58] + node _T_1448 = cat(store_data_lo_r, UInt<32>("h00")) @[Cat.scala 29:58] + node _T_1449 = cat(UInt<32>("h00"), store_data_lo_r) @[Cat.scala 29:58] + node _T_1450 = mux(_T_1447, _T_1448, _T_1449) @[lsu_bus_buffer.scala 328:44] + node _T_1451 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1452 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1453 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1454 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] + node _T_1455 = mux(_T_1451, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1456 = mux(_T_1452, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1457 = mux(_T_1453, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1458 = mux(_T_1454, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1459 = or(_T_1455, _T_1456) @[Mux.scala 27:72] + node _T_1460 = or(_T_1459, _T_1457) @[Mux.scala 27:72] + node _T_1461 = or(_T_1460, _T_1458) @[Mux.scala 27:72] + wire _T_1462 : UInt<32> @[Mux.scala 27:72] + _T_1462 <= _T_1461 @[Mux.scala 27:72] + node _T_1463 = bits(_T_1462, 2, 2) @[lsu_bus_buffer.scala 329:36] + node _T_1464 = bits(_T_1463, 0, 0) @[lsu_bus_buffer.scala 329:46] + node _T_1465 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1466 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1467 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1468 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] + node _T_1469 = mux(_T_1465, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1470 = mux(_T_1466, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1471 = mux(_T_1467, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1472 = mux(_T_1468, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1473 = or(_T_1469, _T_1470) @[Mux.scala 27:72] + node _T_1474 = or(_T_1473, _T_1471) @[Mux.scala 27:72] + node _T_1475 = or(_T_1474, _T_1472) @[Mux.scala 27:72] + wire _T_1476 : UInt<32> @[Mux.scala 27:72] + _T_1476 <= _T_1475 @[Mux.scala 27:72] + node _T_1477 = cat(_T_1476, UInt<32>("h00")) @[Cat.scala 29:58] + node _T_1478 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1479 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1480 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1481 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] + node _T_1482 = mux(_T_1478, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1483 = mux(_T_1479, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1484 = mux(_T_1480, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1485 = mux(_T_1481, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1486 = or(_T_1482, _T_1483) @[Mux.scala 27:72] + node _T_1487 = or(_T_1486, _T_1484) @[Mux.scala 27:72] + node _T_1488 = or(_T_1487, _T_1485) @[Mux.scala 27:72] + wire _T_1489 : UInt<32> @[Mux.scala 27:72] + _T_1489 <= _T_1488 @[Mux.scala 27:72] + node _T_1490 = cat(UInt<32>("h00"), _T_1489) @[Cat.scala 29:58] + node _T_1491 = mux(_T_1464, _T_1477, _T_1490) @[lsu_bus_buffer.scala 329:8] + node obuf_data0_in = mux(ibuf_buf_byp, _T_1450, _T_1491) @[lsu_bus_buffer.scala 328:26] + node _T_1492 = bits(io.lsu_addr_r, 2, 2) @[lsu_bus_buffer.scala 330:58] + node _T_1493 = cat(store_data_hi_r, UInt<32>("h00")) @[Cat.scala 29:58] + node _T_1494 = cat(UInt<32>("h00"), store_data_hi_r) @[Cat.scala 29:58] + node _T_1495 = mux(_T_1492, _T_1493, _T_1494) @[lsu_bus_buffer.scala 330:44] + node _T_1496 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1497 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1498 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1499 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] + node _T_1500 = mux(_T_1496, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1501 = mux(_T_1497, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1502 = mux(_T_1498, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1503 = mux(_T_1499, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1504 = or(_T_1500, _T_1501) @[Mux.scala 27:72] + node _T_1505 = or(_T_1504, _T_1502) @[Mux.scala 27:72] + node _T_1506 = or(_T_1505, _T_1503) @[Mux.scala 27:72] + wire _T_1507 : UInt<32> @[Mux.scala 27:72] + _T_1507 <= _T_1506 @[Mux.scala 27:72] + node _T_1508 = bits(_T_1507, 2, 2) @[lsu_bus_buffer.scala 331:36] + node _T_1509 = bits(_T_1508, 0, 0) @[lsu_bus_buffer.scala 331:46] + node _T_1510 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1511 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1512 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1513 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] + node _T_1514 = mux(_T_1510, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1515 = mux(_T_1511, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1516 = mux(_T_1512, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1517 = mux(_T_1513, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1518 = or(_T_1514, _T_1515) @[Mux.scala 27:72] + node _T_1519 = or(_T_1518, _T_1516) @[Mux.scala 27:72] + node _T_1520 = or(_T_1519, _T_1517) @[Mux.scala 27:72] + wire _T_1521 : UInt<32> @[Mux.scala 27:72] + _T_1521 <= _T_1520 @[Mux.scala 27:72] + node _T_1522 = cat(_T_1521, UInt<32>("h00")) @[Cat.scala 29:58] + node _T_1523 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1524 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1525 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1526 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] + node _T_1527 = mux(_T_1523, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1528 = mux(_T_1524, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1529 = mux(_T_1525, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1530 = mux(_T_1526, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1531 = or(_T_1527, _T_1528) @[Mux.scala 27:72] + node _T_1532 = or(_T_1531, _T_1529) @[Mux.scala 27:72] + node _T_1533 = or(_T_1532, _T_1530) @[Mux.scala 27:72] + wire _T_1534 : UInt<32> @[Mux.scala 27:72] + _T_1534 <= _T_1533 @[Mux.scala 27:72] + node _T_1535 = cat(UInt<32>("h00"), _T_1534) @[Cat.scala 29:58] + node _T_1536 = mux(_T_1509, _T_1522, _T_1535) @[lsu_bus_buffer.scala 331:8] + node obuf_data1_in = mux(ibuf_buf_byp, _T_1495, _T_1536) @[lsu_bus_buffer.scala 330:26] + node _T_1537 = bits(obuf_byteen0_in, 0, 0) @[lsu_bus_buffer.scala 332:59] + node _T_1538 = bits(obuf_byteen1_in, 0, 0) @[lsu_bus_buffer.scala 332:97] + node _T_1539 = and(obuf_merge_en, _T_1538) @[lsu_bus_buffer.scala 332:80] + node _T_1540 = or(_T_1537, _T_1539) @[lsu_bus_buffer.scala 332:63] + node _T_1541 = bits(obuf_byteen0_in, 1, 1) @[lsu_bus_buffer.scala 332:59] + node _T_1542 = bits(obuf_byteen1_in, 1, 1) @[lsu_bus_buffer.scala 332:97] + node _T_1543 = and(obuf_merge_en, _T_1542) @[lsu_bus_buffer.scala 332:80] + node _T_1544 = or(_T_1541, _T_1543) @[lsu_bus_buffer.scala 332:63] + node _T_1545 = bits(obuf_byteen0_in, 2, 2) @[lsu_bus_buffer.scala 332:59] + node _T_1546 = bits(obuf_byteen1_in, 2, 2) @[lsu_bus_buffer.scala 332:97] + node _T_1547 = and(obuf_merge_en, _T_1546) @[lsu_bus_buffer.scala 332:80] + node _T_1548 = or(_T_1545, _T_1547) @[lsu_bus_buffer.scala 332:63] + node _T_1549 = bits(obuf_byteen0_in, 3, 3) @[lsu_bus_buffer.scala 332:59] + node _T_1550 = bits(obuf_byteen1_in, 3, 3) @[lsu_bus_buffer.scala 332:97] + node _T_1551 = and(obuf_merge_en, _T_1550) @[lsu_bus_buffer.scala 332:80] + node _T_1552 = or(_T_1549, _T_1551) @[lsu_bus_buffer.scala 332:63] + node _T_1553 = bits(obuf_byteen0_in, 4, 4) @[lsu_bus_buffer.scala 332:59] + node _T_1554 = bits(obuf_byteen1_in, 4, 4) @[lsu_bus_buffer.scala 332:97] + node _T_1555 = and(obuf_merge_en, _T_1554) @[lsu_bus_buffer.scala 332:80] + node _T_1556 = or(_T_1553, _T_1555) @[lsu_bus_buffer.scala 332:63] + node _T_1557 = bits(obuf_byteen0_in, 5, 5) @[lsu_bus_buffer.scala 332:59] + node _T_1558 = bits(obuf_byteen1_in, 5, 5) @[lsu_bus_buffer.scala 332:97] + node _T_1559 = and(obuf_merge_en, _T_1558) @[lsu_bus_buffer.scala 332:80] + node _T_1560 = or(_T_1557, _T_1559) @[lsu_bus_buffer.scala 332:63] + node _T_1561 = bits(obuf_byteen0_in, 6, 6) @[lsu_bus_buffer.scala 332:59] + node _T_1562 = bits(obuf_byteen1_in, 6, 6) @[lsu_bus_buffer.scala 332:97] + node _T_1563 = and(obuf_merge_en, _T_1562) @[lsu_bus_buffer.scala 332:80] + node _T_1564 = or(_T_1561, _T_1563) @[lsu_bus_buffer.scala 332:63] + node _T_1565 = bits(obuf_byteen0_in, 7, 7) @[lsu_bus_buffer.scala 332:59] + node _T_1566 = bits(obuf_byteen1_in, 7, 7) @[lsu_bus_buffer.scala 332:97] + node _T_1567 = and(obuf_merge_en, _T_1566) @[lsu_bus_buffer.scala 332:80] + node _T_1568 = or(_T_1565, _T_1567) @[lsu_bus_buffer.scala 332:63] + node _T_1569 = cat(_T_1568, _T_1564) @[Cat.scala 29:58] + node _T_1570 = cat(_T_1569, _T_1560) @[Cat.scala 29:58] + node _T_1571 = cat(_T_1570, _T_1556) @[Cat.scala 29:58] + node _T_1572 = cat(_T_1571, _T_1552) @[Cat.scala 29:58] + node _T_1573 = cat(_T_1572, _T_1548) @[Cat.scala 29:58] + node _T_1574 = cat(_T_1573, _T_1544) @[Cat.scala 29:58] + node obuf_byteen_in = cat(_T_1574, _T_1540) @[Cat.scala 29:58] + node _T_1575 = bits(obuf_byteen1_in, 0, 0) @[lsu_bus_buffer.scala 333:76] + node _T_1576 = and(obuf_merge_en, _T_1575) @[lsu_bus_buffer.scala 333:59] + node _T_1577 = bits(obuf_data1_in, 7, 0) @[lsu_bus_buffer.scala 333:94] + node _T_1578 = bits(obuf_data0_in, 7, 0) @[lsu_bus_buffer.scala 333:123] + node _T_1579 = mux(_T_1576, _T_1577, _T_1578) @[lsu_bus_buffer.scala 333:44] + node _T_1580 = bits(obuf_byteen1_in, 1, 1) @[lsu_bus_buffer.scala 333:76] + node _T_1581 = and(obuf_merge_en, _T_1580) @[lsu_bus_buffer.scala 333:59] + node _T_1582 = bits(obuf_data1_in, 15, 8) @[lsu_bus_buffer.scala 333:94] + node _T_1583 = bits(obuf_data0_in, 15, 8) @[lsu_bus_buffer.scala 333:123] + node _T_1584 = mux(_T_1581, _T_1582, _T_1583) @[lsu_bus_buffer.scala 333:44] + node _T_1585 = bits(obuf_byteen1_in, 2, 2) @[lsu_bus_buffer.scala 333:76] + node _T_1586 = and(obuf_merge_en, _T_1585) @[lsu_bus_buffer.scala 333:59] + node _T_1587 = bits(obuf_data1_in, 23, 16) @[lsu_bus_buffer.scala 333:94] + node _T_1588 = bits(obuf_data0_in, 23, 16) @[lsu_bus_buffer.scala 333:123] + node _T_1589 = mux(_T_1586, _T_1587, _T_1588) @[lsu_bus_buffer.scala 333:44] + node _T_1590 = bits(obuf_byteen1_in, 3, 3) @[lsu_bus_buffer.scala 333:76] + node _T_1591 = and(obuf_merge_en, _T_1590) @[lsu_bus_buffer.scala 333:59] + node _T_1592 = bits(obuf_data1_in, 31, 24) @[lsu_bus_buffer.scala 333:94] + node _T_1593 = bits(obuf_data0_in, 31, 24) @[lsu_bus_buffer.scala 333:123] + node _T_1594 = mux(_T_1591, _T_1592, _T_1593) @[lsu_bus_buffer.scala 333:44] + node _T_1595 = bits(obuf_byteen1_in, 4, 4) @[lsu_bus_buffer.scala 333:76] + node _T_1596 = and(obuf_merge_en, _T_1595) @[lsu_bus_buffer.scala 333:59] + node _T_1597 = bits(obuf_data1_in, 39, 32) @[lsu_bus_buffer.scala 333:94] + node _T_1598 = bits(obuf_data0_in, 39, 32) @[lsu_bus_buffer.scala 333:123] + node _T_1599 = mux(_T_1596, _T_1597, _T_1598) @[lsu_bus_buffer.scala 333:44] + node _T_1600 = bits(obuf_byteen1_in, 5, 5) @[lsu_bus_buffer.scala 333:76] + node _T_1601 = and(obuf_merge_en, _T_1600) @[lsu_bus_buffer.scala 333:59] + node _T_1602 = bits(obuf_data1_in, 47, 40) @[lsu_bus_buffer.scala 333:94] + node _T_1603 = bits(obuf_data0_in, 47, 40) @[lsu_bus_buffer.scala 333:123] + node _T_1604 = mux(_T_1601, _T_1602, _T_1603) @[lsu_bus_buffer.scala 333:44] + node _T_1605 = bits(obuf_byteen1_in, 6, 6) @[lsu_bus_buffer.scala 333:76] + node _T_1606 = and(obuf_merge_en, _T_1605) @[lsu_bus_buffer.scala 333:59] + node _T_1607 = bits(obuf_data1_in, 55, 48) @[lsu_bus_buffer.scala 333:94] + node _T_1608 = bits(obuf_data0_in, 55, 48) @[lsu_bus_buffer.scala 333:123] + node _T_1609 = mux(_T_1606, _T_1607, _T_1608) @[lsu_bus_buffer.scala 333:44] + node _T_1610 = bits(obuf_byteen1_in, 7, 7) @[lsu_bus_buffer.scala 333:76] + node _T_1611 = and(obuf_merge_en, _T_1610) @[lsu_bus_buffer.scala 333:59] + node _T_1612 = bits(obuf_data1_in, 63, 56) @[lsu_bus_buffer.scala 333:94] + node _T_1613 = bits(obuf_data0_in, 63, 56) @[lsu_bus_buffer.scala 333:123] + node _T_1614 = mux(_T_1611, _T_1612, _T_1613) @[lsu_bus_buffer.scala 333:44] + node _T_1615 = cat(_T_1614, _T_1609) @[Cat.scala 29:58] + node _T_1616 = cat(_T_1615, _T_1604) @[Cat.scala 29:58] + node _T_1617 = cat(_T_1616, _T_1599) @[Cat.scala 29:58] + node _T_1618 = cat(_T_1617, _T_1594) @[Cat.scala 29:58] + node _T_1619 = cat(_T_1618, _T_1589) @[Cat.scala 29:58] + node _T_1620 = cat(_T_1619, _T_1584) @[Cat.scala 29:58] + node obuf_data_in = cat(_T_1620, _T_1579) @[Cat.scala 29:58] + wire buf_dualhi : UInt<1>[4] @[lsu_bus_buffer.scala 335:24] + buf_dualhi[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 336:14] + buf_dualhi[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 336:14] + buf_dualhi[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 336:14] + buf_dualhi[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 336:14] + node _T_1621 = neq(CmdPtr0, CmdPtr1) @[lsu_bus_buffer.scala 337:30] + node _T_1622 = and(_T_1621, found_cmdptr0) @[lsu_bus_buffer.scala 337:43] + node _T_1623 = and(_T_1622, found_cmdptr1) @[lsu_bus_buffer.scala 337:59] + node _T_1624 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1625 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1626 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1627 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] + node _T_1628 = mux(_T_1624, buf_state[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1629 = mux(_T_1625, buf_state[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1630 = mux(_T_1626, buf_state[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1631 = mux(_T_1627, buf_state[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1632 = or(_T_1628, _T_1629) @[Mux.scala 27:72] + node _T_1633 = or(_T_1632, _T_1630) @[Mux.scala 27:72] + node _T_1634 = or(_T_1633, _T_1631) @[Mux.scala 27:72] + wire _T_1635 : UInt<3> @[Mux.scala 27:72] + _T_1635 <= _T_1634 @[Mux.scala 27:72] + node _T_1636 = eq(_T_1635, UInt<3>("h02")) @[lsu_bus_buffer.scala 337:107] + node _T_1637 = and(_T_1623, _T_1636) @[lsu_bus_buffer.scala 337:75] + node _T_1638 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1639 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1640 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1641 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] + node _T_1642 = mux(_T_1638, buf_state[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1643 = mux(_T_1639, buf_state[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1644 = mux(_T_1640, buf_state[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1645 = mux(_T_1641, buf_state[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1646 = or(_T_1642, _T_1643) @[Mux.scala 27:72] + node _T_1647 = or(_T_1646, _T_1644) @[Mux.scala 27:72] + node _T_1648 = or(_T_1647, _T_1645) @[Mux.scala 27:72] + wire _T_1649 : UInt<3> @[Mux.scala 27:72] + _T_1649 <= _T_1648 @[Mux.scala 27:72] + node _T_1650 = eq(_T_1649, UInt<3>("h02")) @[lsu_bus_buffer.scala 337:150] + node _T_1651 = and(_T_1637, _T_1650) @[lsu_bus_buffer.scala 337:118] + node _T_1652 = cat(buf_cmd_state_bus_en[3], buf_cmd_state_bus_en[2]) @[Cat.scala 29:58] + node _T_1653 = cat(_T_1652, buf_cmd_state_bus_en[1]) @[Cat.scala 29:58] + node _T_1654 = cat(_T_1653, buf_cmd_state_bus_en[0]) @[Cat.scala 29:58] + node _T_1655 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_1656 = bits(_T_1654, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_1657 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_1658 = bits(_T_1654, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_1659 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_1660 = bits(_T_1654, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_1661 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_1662 = bits(_T_1654, 3, 3) @[lsu_bus_buffer.scala 57:129] + node _T_1663 = mux(_T_1655, _T_1656, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1664 = mux(_T_1657, _T_1658, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1665 = mux(_T_1659, _T_1660, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1666 = mux(_T_1661, _T_1662, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1667 = or(_T_1663, _T_1664) @[Mux.scala 27:72] + node _T_1668 = or(_T_1667, _T_1665) @[Mux.scala 27:72] + node _T_1669 = or(_T_1668, _T_1666) @[Mux.scala 27:72] + wire _T_1670 : UInt<1> @[Mux.scala 27:72] + _T_1670 <= _T_1669 @[Mux.scala 27:72] + node _T_1671 = eq(_T_1670, UInt<1>("h00")) @[lsu_bus_buffer.scala 338:5] + node _T_1672 = and(_T_1651, _T_1671) @[lsu_bus_buffer.scala 337:161] + node _T_1673 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_1674 = bits(buf_sideeffect, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_1675 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_1676 = bits(buf_sideeffect, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_1677 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_1678 = bits(buf_sideeffect, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_1679 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_1680 = bits(buf_sideeffect, 3, 3) @[lsu_bus_buffer.scala 57:129] + node _T_1681 = mux(_T_1673, _T_1674, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1682 = mux(_T_1675, _T_1676, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1683 = mux(_T_1677, _T_1678, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1684 = mux(_T_1679, _T_1680, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1685 = or(_T_1681, _T_1682) @[Mux.scala 27:72] + node _T_1686 = or(_T_1685, _T_1683) @[Mux.scala 27:72] + node _T_1687 = or(_T_1686, _T_1684) @[Mux.scala 27:72] + wire _T_1688 : UInt<1> @[Mux.scala 27:72] + _T_1688 <= _T_1687 @[Mux.scala 27:72] + node _T_1689 = eq(_T_1688, UInt<1>("h00")) @[lsu_bus_buffer.scala 338:87] + node _T_1690 = and(_T_1672, _T_1689) @[lsu_bus_buffer.scala 338:85] + node _T_1691 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_1692 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_1693 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_1694 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_1695 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_1696 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_1697 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_1698 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 57:129] + node _T_1699 = mux(_T_1691, _T_1692, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1700 = mux(_T_1693, _T_1694, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1701 = mux(_T_1695, _T_1696, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1702 = mux(_T_1697, _T_1698, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1703 = or(_T_1699, _T_1700) @[Mux.scala 27:72] + node _T_1704 = or(_T_1703, _T_1701) @[Mux.scala 27:72] + node _T_1705 = or(_T_1704, _T_1702) @[Mux.scala 27:72] + wire _T_1706 : UInt<1> @[Mux.scala 27:72] + _T_1706 <= _T_1705 @[Mux.scala 27:72] + node _T_1707 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_1708 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_1709 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_1710 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_1711 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_1712 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_1713 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_1714 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 57:129] + node _T_1715 = mux(_T_1707, _T_1708, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1716 = mux(_T_1709, _T_1710, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1717 = mux(_T_1711, _T_1712, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1718 = mux(_T_1713, _T_1714, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1719 = or(_T_1715, _T_1716) @[Mux.scala 27:72] + node _T_1720 = or(_T_1719, _T_1717) @[Mux.scala 27:72] + node _T_1721 = or(_T_1720, _T_1718) @[Mux.scala 27:72] + wire _T_1722 : UInt<1> @[Mux.scala 27:72] + _T_1722 <= _T_1721 @[Mux.scala 27:72] + node _T_1723 = and(_T_1706, _T_1722) @[lsu_bus_buffer.scala 339:36] + node _T_1724 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1725 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1726 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1727 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] + node _T_1728 = mux(_T_1724, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1729 = mux(_T_1725, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1730 = mux(_T_1726, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1731 = mux(_T_1727, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1732 = or(_T_1728, _T_1729) @[Mux.scala 27:72] + node _T_1733 = or(_T_1732, _T_1730) @[Mux.scala 27:72] + node _T_1734 = or(_T_1733, _T_1731) @[Mux.scala 27:72] + wire _T_1735 : UInt<32> @[Mux.scala 27:72] + _T_1735 <= _T_1734 @[Mux.scala 27:72] + node _T_1736 = bits(_T_1735, 31, 3) @[lsu_bus_buffer.scala 340:35] + node _T_1737 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1738 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1739 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1740 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] + node _T_1741 = mux(_T_1737, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1742 = mux(_T_1738, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1743 = mux(_T_1739, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1744 = mux(_T_1740, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1745 = or(_T_1741, _T_1742) @[Mux.scala 27:72] + node _T_1746 = or(_T_1745, _T_1743) @[Mux.scala 27:72] + node _T_1747 = or(_T_1746, _T_1744) @[Mux.scala 27:72] + wire _T_1748 : UInt<32> @[Mux.scala 27:72] + _T_1748 <= _T_1747 @[Mux.scala 27:72] + node _T_1749 = bits(_T_1748, 31, 3) @[lsu_bus_buffer.scala 340:71] + node _T_1750 = eq(_T_1736, _T_1749) @[lsu_bus_buffer.scala 340:41] + node _T_1751 = and(_T_1723, _T_1750) @[lsu_bus_buffer.scala 339:67] + node _T_1752 = eq(bus_coalescing_disable, UInt<1>("h00")) @[lsu_bus_buffer.scala 340:81] + node _T_1753 = and(_T_1751, _T_1752) @[lsu_bus_buffer.scala 340:79] + node _T_1754 = eq(UInt<1>("h00"), UInt<1>("h00")) @[lsu_bus_buffer.scala 340:107] + node _T_1755 = and(_T_1753, _T_1754) @[lsu_bus_buffer.scala 340:105] + node _T_1756 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_1757 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_1758 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_1759 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_1760 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_1761 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_1762 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_1763 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 57:129] + node _T_1764 = mux(_T_1756, _T_1757, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1765 = mux(_T_1758, _T_1759, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1766 = mux(_T_1760, _T_1761, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1767 = mux(_T_1762, _T_1763, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1768 = or(_T_1764, _T_1765) @[Mux.scala 27:72] + node _T_1769 = or(_T_1768, _T_1766) @[Mux.scala 27:72] + node _T_1770 = or(_T_1769, _T_1767) @[Mux.scala 27:72] + wire _T_1771 : UInt<1> @[Mux.scala 27:72] + _T_1771 <= _T_1770 @[Mux.scala 27:72] + node _T_1772 = eq(_T_1771, UInt<1>("h00")) @[lsu_bus_buffer.scala 341:8] + node _T_1773 = cat(buf_dual[3], buf_dual[2]) @[Cat.scala 29:58] + node _T_1774 = cat(_T_1773, buf_dual[1]) @[Cat.scala 29:58] + node _T_1775 = cat(_T_1774, buf_dual[0]) @[Cat.scala 29:58] + node _T_1776 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_1777 = bits(_T_1775, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_1778 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_1779 = bits(_T_1775, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_1780 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_1781 = bits(_T_1775, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_1782 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_1783 = bits(_T_1775, 3, 3) @[lsu_bus_buffer.scala 57:129] + node _T_1784 = mux(_T_1776, _T_1777, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1785 = mux(_T_1778, _T_1779, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1786 = mux(_T_1780, _T_1781, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1787 = mux(_T_1782, _T_1783, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1788 = or(_T_1784, _T_1785) @[Mux.scala 27:72] + node _T_1789 = or(_T_1788, _T_1786) @[Mux.scala 27:72] + node _T_1790 = or(_T_1789, _T_1787) @[Mux.scala 27:72] + wire _T_1791 : UInt<1> @[Mux.scala 27:72] + _T_1791 <= _T_1790 @[Mux.scala 27:72] + node _T_1792 = and(_T_1772, _T_1791) @[lsu_bus_buffer.scala 341:38] + node _T_1793 = cat(buf_dualhi[3], buf_dualhi[2]) @[Cat.scala 29:58] + node _T_1794 = cat(_T_1793, buf_dualhi[1]) @[Cat.scala 29:58] + node _T_1795 = cat(_T_1794, buf_dualhi[0]) @[Cat.scala 29:58] + node _T_1796 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_1797 = bits(_T_1795, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_1798 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_1799 = bits(_T_1795, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_1800 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_1801 = bits(_T_1795, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_1802 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_1803 = bits(_T_1795, 3, 3) @[lsu_bus_buffer.scala 57:129] + node _T_1804 = mux(_T_1796, _T_1797, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1805 = mux(_T_1798, _T_1799, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1806 = mux(_T_1800, _T_1801, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1807 = mux(_T_1802, _T_1803, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1808 = or(_T_1804, _T_1805) @[Mux.scala 27:72] + node _T_1809 = or(_T_1808, _T_1806) @[Mux.scala 27:72] + node _T_1810 = or(_T_1809, _T_1807) @[Mux.scala 27:72] + wire _T_1811 : UInt<1> @[Mux.scala 27:72] + _T_1811 <= _T_1810 @[Mux.scala 27:72] + node _T_1812 = eq(_T_1811, UInt<1>("h00")) @[lsu_bus_buffer.scala 341:109] + node _T_1813 = and(_T_1792, _T_1812) @[lsu_bus_buffer.scala 341:107] + node _T_1814 = cat(buf_samedw[3], buf_samedw[2]) @[Cat.scala 29:58] + node _T_1815 = cat(_T_1814, buf_samedw[1]) @[Cat.scala 29:58] + node _T_1816 = cat(_T_1815, buf_samedw[0]) @[Cat.scala 29:58] + node _T_1817 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_1818 = bits(_T_1816, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_1819 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_1820 = bits(_T_1816, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_1821 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_1822 = bits(_T_1816, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_1823 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_1824 = bits(_T_1816, 3, 3) @[lsu_bus_buffer.scala 57:129] + node _T_1825 = mux(_T_1817, _T_1818, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1826 = mux(_T_1819, _T_1820, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1827 = mux(_T_1821, _T_1822, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1828 = mux(_T_1823, _T_1824, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1829 = or(_T_1825, _T_1826) @[Mux.scala 27:72] + node _T_1830 = or(_T_1829, _T_1827) @[Mux.scala 27:72] + node _T_1831 = or(_T_1830, _T_1828) @[Mux.scala 27:72] + wire _T_1832 : UInt<1> @[Mux.scala 27:72] + _T_1832 <= _T_1831 @[Mux.scala 27:72] + node _T_1833 = and(_T_1813, _T_1832) @[lsu_bus_buffer.scala 341:179] + node _T_1834 = or(_T_1755, _T_1833) @[lsu_bus_buffer.scala 340:128] + node _T_1835 = and(_T_1690, _T_1834) @[lsu_bus_buffer.scala 338:122] + node _T_1836 = and(ibuf_buf_byp, ldst_samedw_r) @[lsu_bus_buffer.scala 342:19] + node _T_1837 = and(_T_1836, io.ldst_dual_r) @[lsu_bus_buffer.scala 342:35] + node _T_1838 = or(_T_1835, _T_1837) @[lsu_bus_buffer.scala 341:253] + obuf_merge_en <= _T_1838 @[lsu_bus_buffer.scala 337:17] + reg obuf_wr_enQ : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 344:55] + obuf_wr_enQ <= obuf_wr_en @[lsu_bus_buffer.scala 344:55] + node _T_1839 = mux(obuf_wr_en, UInt<1>("h01"), obuf_valid) @[lsu_bus_buffer.scala 345:58] + node _T_1840 = eq(obuf_rst, UInt<1>("h00")) @[lsu_bus_buffer.scala 345:93] + node _T_1841 = and(_T_1839, _T_1840) @[lsu_bus_buffer.scala 345:91] + reg _T_1842 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 345:54] + _T_1842 <= _T_1841 @[lsu_bus_buffer.scala 345:54] + obuf_valid <= _T_1842 @[lsu_bus_buffer.scala 345:14] + reg _T_1843 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when obuf_wr_en : @[Reg.scala 28:19] + _T_1843 <= obuf_nosend_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_nosend <= _T_1843 @[lsu_bus_buffer.scala 346:15] + reg _T_1844 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 347:54] + _T_1844 <= obuf_cmd_done_in @[lsu_bus_buffer.scala 347:54] + obuf_cmd_done <= _T_1844 @[lsu_bus_buffer.scala 347:17] + reg _T_1845 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 348:55] + _T_1845 <= obuf_data_done_in @[lsu_bus_buffer.scala 348:55] + obuf_data_done <= _T_1845 @[lsu_bus_buffer.scala 348:18] + reg _T_1846 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 349:56] + _T_1846 <= obuf_rdrsp_pend_in @[lsu_bus_buffer.scala 349:56] + obuf_rdrsp_pend <= _T_1846 @[lsu_bus_buffer.scala 349:19] + reg _T_1847 : UInt, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 350:55] + _T_1847 <= obuf_rdrsp_tag_in @[lsu_bus_buffer.scala 350:55] + obuf_rdrsp_tag <= _T_1847 @[lsu_bus_buffer.scala 350:18] + reg _T_1848 : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when obuf_wr_en : @[Reg.scala 28:19] + _T_1848 <= obuf_tag0_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_tag0 <= _T_1848 @[lsu_bus_buffer.scala 351:13] + reg obuf_tag1 : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when obuf_wr_en : @[Reg.scala 28:19] + obuf_tag1 <= obuf_tag1_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg obuf_merge : UInt<1>, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when obuf_wr_en : @[Reg.scala 28:19] + obuf_merge <= obuf_merge_en @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg _T_1849 : UInt<1>, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when obuf_wr_en : @[Reg.scala 28:19] + _T_1849 <= obuf_write_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_write <= _T_1849 @[lsu_bus_buffer.scala 354:14] + reg _T_1850 : UInt<1>, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when obuf_wr_en : @[Reg.scala 28:19] + _T_1850 <= obuf_sideeffect_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_sideeffect <= _T_1850 @[lsu_bus_buffer.scala 355:19] + reg obuf_sz : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when obuf_wr_en : @[Reg.scala 28:19] + obuf_sz <= obuf_sz_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 368:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_2.io.en <= obuf_wr_en @[lib.scala 371:17] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_1851 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_1851 <= obuf_addr_in @[lib.scala 374:16] + obuf_addr <= _T_1851 @[lsu_bus_buffer.scala 357:13] + reg obuf_byteen : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when obuf_wr_en : @[Reg.scala 28:19] + obuf_byteen <= obuf_byteen_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 368:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_3.io.en <= obuf_wr_en @[lib.scala 371:17] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg obuf_data : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + obuf_data <= obuf_data_in @[lib.scala 374:16] + reg _T_1852 : UInt, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 360:54] + _T_1852 <= obuf_wr_timer_in @[lsu_bus_buffer.scala 360:54] + obuf_wr_timer <= _T_1852 @[lsu_bus_buffer.scala 360:17] + wire WrPtr0_m : UInt<2> + WrPtr0_m <= UInt<1>("h00") + node _T_1853 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 363:65] + node _T_1854 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 364:30] + node _T_1855 = and(ibuf_valid, _T_1854) @[lsu_bus_buffer.scala 364:19] + node _T_1856 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 365:18] + node _T_1857 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 365:57] + node _T_1858 = and(io.ldst_dual_r, _T_1857) @[lsu_bus_buffer.scala 365:45] + node _T_1859 = or(_T_1856, _T_1858) @[lsu_bus_buffer.scala 365:27] + node _T_1860 = and(io.lsu_busreq_r, _T_1859) @[lsu_bus_buffer.scala 364:58] + node _T_1861 = or(_T_1855, _T_1860) @[lsu_bus_buffer.scala 364:39] + node _T_1862 = eq(_T_1861, UInt<1>("h00")) @[lsu_bus_buffer.scala 364:5] + node _T_1863 = and(_T_1853, _T_1862) @[lsu_bus_buffer.scala 363:76] + node _T_1864 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 363:65] + node _T_1865 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 364:30] + node _T_1866 = and(ibuf_valid, _T_1865) @[lsu_bus_buffer.scala 364:19] + node _T_1867 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 365:18] + node _T_1868 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 365:57] + node _T_1869 = and(io.ldst_dual_r, _T_1868) @[lsu_bus_buffer.scala 365:45] + node _T_1870 = or(_T_1867, _T_1869) @[lsu_bus_buffer.scala 365:27] + node _T_1871 = and(io.lsu_busreq_r, _T_1870) @[lsu_bus_buffer.scala 364:58] + node _T_1872 = or(_T_1866, _T_1871) @[lsu_bus_buffer.scala 364:39] + node _T_1873 = eq(_T_1872, UInt<1>("h00")) @[lsu_bus_buffer.scala 364:5] + node _T_1874 = and(_T_1864, _T_1873) @[lsu_bus_buffer.scala 363:76] + node _T_1875 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 363:65] + node _T_1876 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 364:30] + node _T_1877 = and(ibuf_valid, _T_1876) @[lsu_bus_buffer.scala 364:19] + node _T_1878 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 365:18] + node _T_1879 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 365:57] + node _T_1880 = and(io.ldst_dual_r, _T_1879) @[lsu_bus_buffer.scala 365:45] + node _T_1881 = or(_T_1878, _T_1880) @[lsu_bus_buffer.scala 365:27] + node _T_1882 = and(io.lsu_busreq_r, _T_1881) @[lsu_bus_buffer.scala 364:58] + node _T_1883 = or(_T_1877, _T_1882) @[lsu_bus_buffer.scala 364:39] + node _T_1884 = eq(_T_1883, UInt<1>("h00")) @[lsu_bus_buffer.scala 364:5] + node _T_1885 = and(_T_1875, _T_1884) @[lsu_bus_buffer.scala 363:76] + node _T_1886 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 363:65] + node _T_1887 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 364:30] + node _T_1888 = and(ibuf_valid, _T_1887) @[lsu_bus_buffer.scala 364:19] + node _T_1889 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 365:18] + node _T_1890 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 365:57] + node _T_1891 = and(io.ldst_dual_r, _T_1890) @[lsu_bus_buffer.scala 365:45] + node _T_1892 = or(_T_1889, _T_1891) @[lsu_bus_buffer.scala 365:27] + node _T_1893 = and(io.lsu_busreq_r, _T_1892) @[lsu_bus_buffer.scala 364:58] + node _T_1894 = or(_T_1888, _T_1893) @[lsu_bus_buffer.scala 364:39] + node _T_1895 = eq(_T_1894, UInt<1>("h00")) @[lsu_bus_buffer.scala 364:5] + node _T_1896 = and(_T_1886, _T_1895) @[lsu_bus_buffer.scala 363:76] + node _T_1897 = mux(_T_1896, UInt<2>("h03"), UInt<2>("h03")) @[Mux.scala 98:16] + node _T_1898 = mux(_T_1885, UInt<2>("h02"), _T_1897) @[Mux.scala 98:16] + node _T_1899 = mux(_T_1874, UInt<1>("h01"), _T_1898) @[Mux.scala 98:16] + node _T_1900 = mux(_T_1863, UInt<1>("h00"), _T_1899) @[Mux.scala 98:16] + WrPtr0_m <= _T_1900 @[lsu_bus_buffer.scala 363:12] + wire WrPtr1_m : UInt<2> + WrPtr1_m <= UInt<1>("h00") + node _T_1901 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 369:65] + node _T_1902 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 369:103] + node _T_1903 = and(ibuf_valid, _T_1902) @[lsu_bus_buffer.scala 369:92] + node _T_1904 = eq(WrPtr0_m, UInt<1>("h00")) @[lsu_bus_buffer.scala 370:33] + node _T_1905 = and(io.lsu_busreq_m, _T_1904) @[lsu_bus_buffer.scala 370:22] + node _T_1906 = or(_T_1903, _T_1905) @[lsu_bus_buffer.scala 369:112] + node _T_1907 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 371:36] + node _T_1908 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 372:34] + node _T_1909 = and(io.ldst_dual_r, _T_1908) @[lsu_bus_buffer.scala 372:23] + node _T_1910 = or(_T_1907, _T_1909) @[lsu_bus_buffer.scala 371:46] + node _T_1911 = and(io.lsu_busreq_r, _T_1910) @[lsu_bus_buffer.scala 371:22] + node _T_1912 = or(_T_1906, _T_1911) @[lsu_bus_buffer.scala 370:42] + node _T_1913 = eq(_T_1912, UInt<1>("h00")) @[lsu_bus_buffer.scala 369:78] + node _T_1914 = and(_T_1901, _T_1913) @[lsu_bus_buffer.scala 369:76] + node _T_1915 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 369:65] + node _T_1916 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 369:103] + node _T_1917 = and(ibuf_valid, _T_1916) @[lsu_bus_buffer.scala 369:92] + node _T_1918 = eq(WrPtr0_m, UInt<1>("h01")) @[lsu_bus_buffer.scala 370:33] + node _T_1919 = and(io.lsu_busreq_m, _T_1918) @[lsu_bus_buffer.scala 370:22] + node _T_1920 = or(_T_1917, _T_1919) @[lsu_bus_buffer.scala 369:112] + node _T_1921 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 371:36] + node _T_1922 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 372:34] + node _T_1923 = and(io.ldst_dual_r, _T_1922) @[lsu_bus_buffer.scala 372:23] + node _T_1924 = or(_T_1921, _T_1923) @[lsu_bus_buffer.scala 371:46] + node _T_1925 = and(io.lsu_busreq_r, _T_1924) @[lsu_bus_buffer.scala 371:22] + node _T_1926 = or(_T_1920, _T_1925) @[lsu_bus_buffer.scala 370:42] + node _T_1927 = eq(_T_1926, UInt<1>("h00")) @[lsu_bus_buffer.scala 369:78] + node _T_1928 = and(_T_1915, _T_1927) @[lsu_bus_buffer.scala 369:76] + node _T_1929 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 369:65] + node _T_1930 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 369:103] + node _T_1931 = and(ibuf_valid, _T_1930) @[lsu_bus_buffer.scala 369:92] + node _T_1932 = eq(WrPtr0_m, UInt<2>("h02")) @[lsu_bus_buffer.scala 370:33] + node _T_1933 = and(io.lsu_busreq_m, _T_1932) @[lsu_bus_buffer.scala 370:22] + node _T_1934 = or(_T_1931, _T_1933) @[lsu_bus_buffer.scala 369:112] + node _T_1935 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 371:36] + node _T_1936 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 372:34] + node _T_1937 = and(io.ldst_dual_r, _T_1936) @[lsu_bus_buffer.scala 372:23] + node _T_1938 = or(_T_1935, _T_1937) @[lsu_bus_buffer.scala 371:46] + node _T_1939 = and(io.lsu_busreq_r, _T_1938) @[lsu_bus_buffer.scala 371:22] + node _T_1940 = or(_T_1934, _T_1939) @[lsu_bus_buffer.scala 370:42] + node _T_1941 = eq(_T_1940, UInt<1>("h00")) @[lsu_bus_buffer.scala 369:78] + node _T_1942 = and(_T_1929, _T_1941) @[lsu_bus_buffer.scala 369:76] + node _T_1943 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 369:65] + node _T_1944 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 369:103] + node _T_1945 = and(ibuf_valid, _T_1944) @[lsu_bus_buffer.scala 369:92] + node _T_1946 = eq(WrPtr0_m, UInt<2>("h03")) @[lsu_bus_buffer.scala 370:33] + node _T_1947 = and(io.lsu_busreq_m, _T_1946) @[lsu_bus_buffer.scala 370:22] + node _T_1948 = or(_T_1945, _T_1947) @[lsu_bus_buffer.scala 369:112] + node _T_1949 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 371:36] + node _T_1950 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 372:34] + node _T_1951 = and(io.ldst_dual_r, _T_1950) @[lsu_bus_buffer.scala 372:23] + node _T_1952 = or(_T_1949, _T_1951) @[lsu_bus_buffer.scala 371:46] + node _T_1953 = and(io.lsu_busreq_r, _T_1952) @[lsu_bus_buffer.scala 371:22] + node _T_1954 = or(_T_1948, _T_1953) @[lsu_bus_buffer.scala 370:42] + node _T_1955 = eq(_T_1954, UInt<1>("h00")) @[lsu_bus_buffer.scala 369:78] + node _T_1956 = and(_T_1943, _T_1955) @[lsu_bus_buffer.scala 369:76] + node _T_1957 = mux(_T_1956, UInt<2>("h03"), UInt<2>("h03")) @[Mux.scala 98:16] + node _T_1958 = mux(_T_1942, UInt<2>("h02"), _T_1957) @[Mux.scala 98:16] + node _T_1959 = mux(_T_1928, UInt<1>("h01"), _T_1958) @[Mux.scala 98:16] + node _T_1960 = mux(_T_1914, UInt<1>("h00"), _T_1959) @[Mux.scala 98:16] + WrPtr1_m <= _T_1960 @[lsu_bus_buffer.scala 369:12] + wire buf_age : UInt<4>[4] @[lsu_bus_buffer.scala 374:21] + buf_age[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 375:11] + buf_age[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 375:11] + buf_age[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 375:11] + buf_age[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 375:11] + node _T_1961 = orr(buf_age[0]) @[lsu_bus_buffer.scala 377:58] + node _T_1962 = eq(_T_1961, UInt<1>("h00")) @[lsu_bus_buffer.scala 377:45] + node _T_1963 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 377:78] + node _T_1964 = and(_T_1962, _T_1963) @[lsu_bus_buffer.scala 377:63] + node _T_1965 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 377:90] + node _T_1966 = and(_T_1964, _T_1965) @[lsu_bus_buffer.scala 377:88] + node _T_1967 = orr(buf_age[1]) @[lsu_bus_buffer.scala 377:58] + node _T_1968 = eq(_T_1967, UInt<1>("h00")) @[lsu_bus_buffer.scala 377:45] + node _T_1969 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 377:78] + node _T_1970 = and(_T_1968, _T_1969) @[lsu_bus_buffer.scala 377:63] + node _T_1971 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 377:90] + node _T_1972 = and(_T_1970, _T_1971) @[lsu_bus_buffer.scala 377:88] + node _T_1973 = orr(buf_age[2]) @[lsu_bus_buffer.scala 377:58] + node _T_1974 = eq(_T_1973, UInt<1>("h00")) @[lsu_bus_buffer.scala 377:45] + node _T_1975 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 377:78] + node _T_1976 = and(_T_1974, _T_1975) @[lsu_bus_buffer.scala 377:63] + node _T_1977 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 377:90] + node _T_1978 = and(_T_1976, _T_1977) @[lsu_bus_buffer.scala 377:88] + node _T_1979 = orr(buf_age[3]) @[lsu_bus_buffer.scala 377:58] + node _T_1980 = eq(_T_1979, UInt<1>("h00")) @[lsu_bus_buffer.scala 377:45] + node _T_1981 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 377:78] + node _T_1982 = and(_T_1980, _T_1981) @[lsu_bus_buffer.scala 377:63] + node _T_1983 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 377:90] + node _T_1984 = and(_T_1982, _T_1983) @[lsu_bus_buffer.scala 377:88] + node _T_1985 = cat(_T_1984, _T_1978) @[Cat.scala 29:58] + node _T_1986 = cat(_T_1985, _T_1972) @[Cat.scala 29:58] + node CmdPtr0Dec = cat(_T_1986, _T_1966) @[Cat.scala 29:58] + node _T_1987 = not(CmdPtr0Dec) @[lsu_bus_buffer.scala 378:62] + node _T_1988 = and(buf_age[0], _T_1987) @[lsu_bus_buffer.scala 378:59] + node _T_1989 = orr(_T_1988) @[lsu_bus_buffer.scala 378:76] + node _T_1990 = eq(_T_1989, UInt<1>("h00")) @[lsu_bus_buffer.scala 378:45] + node _T_1991 = bits(CmdPtr0Dec, 0, 0) @[lsu_bus_buffer.scala 378:94] + node _T_1992 = eq(_T_1991, UInt<1>("h00")) @[lsu_bus_buffer.scala 378:83] + node _T_1993 = and(_T_1990, _T_1992) @[lsu_bus_buffer.scala 378:81] + node _T_1994 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 378:113] + node _T_1995 = and(_T_1993, _T_1994) @[lsu_bus_buffer.scala 378:98] + node _T_1996 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 378:125] + node _T_1997 = and(_T_1995, _T_1996) @[lsu_bus_buffer.scala 378:123] + node _T_1998 = not(CmdPtr0Dec) @[lsu_bus_buffer.scala 378:62] + node _T_1999 = and(buf_age[1], _T_1998) @[lsu_bus_buffer.scala 378:59] + node _T_2000 = orr(_T_1999) @[lsu_bus_buffer.scala 378:76] + node _T_2001 = eq(_T_2000, UInt<1>("h00")) @[lsu_bus_buffer.scala 378:45] + node _T_2002 = bits(CmdPtr0Dec, 1, 1) @[lsu_bus_buffer.scala 378:94] + node _T_2003 = eq(_T_2002, UInt<1>("h00")) @[lsu_bus_buffer.scala 378:83] + node _T_2004 = and(_T_2001, _T_2003) @[lsu_bus_buffer.scala 378:81] + node _T_2005 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 378:113] + node _T_2006 = and(_T_2004, _T_2005) @[lsu_bus_buffer.scala 378:98] + node _T_2007 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 378:125] + node _T_2008 = and(_T_2006, _T_2007) @[lsu_bus_buffer.scala 378:123] + node _T_2009 = not(CmdPtr0Dec) @[lsu_bus_buffer.scala 378:62] + node _T_2010 = and(buf_age[2], _T_2009) @[lsu_bus_buffer.scala 378:59] + node _T_2011 = orr(_T_2010) @[lsu_bus_buffer.scala 378:76] + node _T_2012 = eq(_T_2011, UInt<1>("h00")) @[lsu_bus_buffer.scala 378:45] + node _T_2013 = bits(CmdPtr0Dec, 2, 2) @[lsu_bus_buffer.scala 378:94] + node _T_2014 = eq(_T_2013, UInt<1>("h00")) @[lsu_bus_buffer.scala 378:83] + node _T_2015 = and(_T_2012, _T_2014) @[lsu_bus_buffer.scala 378:81] + node _T_2016 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 378:113] + node _T_2017 = and(_T_2015, _T_2016) @[lsu_bus_buffer.scala 378:98] + node _T_2018 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 378:125] + node _T_2019 = and(_T_2017, _T_2018) @[lsu_bus_buffer.scala 378:123] + node _T_2020 = not(CmdPtr0Dec) @[lsu_bus_buffer.scala 378:62] + node _T_2021 = and(buf_age[3], _T_2020) @[lsu_bus_buffer.scala 378:59] + node _T_2022 = orr(_T_2021) @[lsu_bus_buffer.scala 378:76] + node _T_2023 = eq(_T_2022, UInt<1>("h00")) @[lsu_bus_buffer.scala 378:45] + node _T_2024 = bits(CmdPtr0Dec, 3, 3) @[lsu_bus_buffer.scala 378:94] + node _T_2025 = eq(_T_2024, UInt<1>("h00")) @[lsu_bus_buffer.scala 378:83] + node _T_2026 = and(_T_2023, _T_2025) @[lsu_bus_buffer.scala 378:81] + node _T_2027 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 378:113] + node _T_2028 = and(_T_2026, _T_2027) @[lsu_bus_buffer.scala 378:98] + node _T_2029 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 378:125] + node _T_2030 = and(_T_2028, _T_2029) @[lsu_bus_buffer.scala 378:123] + node _T_2031 = cat(_T_2030, _T_2019) @[Cat.scala 29:58] + node _T_2032 = cat(_T_2031, _T_2008) @[Cat.scala 29:58] + node CmdPtr1Dec = cat(_T_2032, _T_1997) @[Cat.scala 29:58] + wire buf_rsp_pickage : UInt<4>[4] @[lsu_bus_buffer.scala 379:29] + buf_rsp_pickage[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 380:19] + buf_rsp_pickage[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 380:19] + buf_rsp_pickage[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 380:19] + buf_rsp_pickage[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 380:19] + node _T_2033 = orr(buf_rsp_pickage[0]) @[lsu_bus_buffer.scala 381:65] + node _T_2034 = eq(_T_2033, UInt<1>("h00")) @[lsu_bus_buffer.scala 381:44] + node _T_2035 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 381:85] + node _T_2036 = and(_T_2034, _T_2035) @[lsu_bus_buffer.scala 381:70] + node _T_2037 = orr(buf_rsp_pickage[1]) @[lsu_bus_buffer.scala 381:65] + node _T_2038 = eq(_T_2037, UInt<1>("h00")) @[lsu_bus_buffer.scala 381:44] + node _T_2039 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 381:85] + node _T_2040 = and(_T_2038, _T_2039) @[lsu_bus_buffer.scala 381:70] + node _T_2041 = orr(buf_rsp_pickage[2]) @[lsu_bus_buffer.scala 381:65] + node _T_2042 = eq(_T_2041, UInt<1>("h00")) @[lsu_bus_buffer.scala 381:44] + node _T_2043 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 381:85] + node _T_2044 = and(_T_2042, _T_2043) @[lsu_bus_buffer.scala 381:70] + node _T_2045 = orr(buf_rsp_pickage[3]) @[lsu_bus_buffer.scala 381:65] + node _T_2046 = eq(_T_2045, UInt<1>("h00")) @[lsu_bus_buffer.scala 381:44] + node _T_2047 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 381:85] + node _T_2048 = and(_T_2046, _T_2047) @[lsu_bus_buffer.scala 381:70] + node _T_2049 = cat(_T_2048, _T_2044) @[Cat.scala 29:58] + node _T_2050 = cat(_T_2049, _T_2040) @[Cat.scala 29:58] + node RspPtrDec = cat(_T_2050, _T_2036) @[Cat.scala 29:58] + node _T_2051 = orr(CmdPtr0Dec) @[lsu_bus_buffer.scala 382:31] + found_cmdptr0 <= _T_2051 @[lsu_bus_buffer.scala 382:17] + node _T_2052 = orr(CmdPtr1Dec) @[lsu_bus_buffer.scala 383:31] + found_cmdptr1 <= _T_2052 @[lsu_bus_buffer.scala 383:17] + wire RspPtr : UInt<2> + RspPtr <= UInt<1>("h00") + node _T_2053 = mux(UInt<1>("h00"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_2054 = cat(_T_2053, CmdPtr0Dec) @[Cat.scala 29:58] + node _T_2055 = bits(_T_2054, 4, 4) @[lsu_bus_buffer.scala 385:39] + node _T_2056 = bits(_T_2054, 5, 5) @[lsu_bus_buffer.scala 385:45] + node _T_2057 = or(_T_2055, _T_2056) @[lsu_bus_buffer.scala 385:42] + node _T_2058 = bits(_T_2054, 6, 6) @[lsu_bus_buffer.scala 385:51] + node _T_2059 = or(_T_2057, _T_2058) @[lsu_bus_buffer.scala 385:48] + node _T_2060 = bits(_T_2054, 7, 7) @[lsu_bus_buffer.scala 385:57] + node _T_2061 = or(_T_2059, _T_2060) @[lsu_bus_buffer.scala 385:54] + node _T_2062 = bits(_T_2054, 2, 2) @[lsu_bus_buffer.scala 385:64] + node _T_2063 = bits(_T_2054, 3, 3) @[lsu_bus_buffer.scala 385:70] + node _T_2064 = or(_T_2062, _T_2063) @[lsu_bus_buffer.scala 385:67] + node _T_2065 = bits(_T_2054, 6, 6) @[lsu_bus_buffer.scala 385:76] + node _T_2066 = or(_T_2064, _T_2065) @[lsu_bus_buffer.scala 385:73] + node _T_2067 = bits(_T_2054, 7, 7) @[lsu_bus_buffer.scala 385:82] + node _T_2068 = or(_T_2066, _T_2067) @[lsu_bus_buffer.scala 385:79] + node _T_2069 = bits(_T_2054, 1, 1) @[lsu_bus_buffer.scala 385:89] + node _T_2070 = bits(_T_2054, 3, 3) @[lsu_bus_buffer.scala 385:95] + node _T_2071 = or(_T_2069, _T_2070) @[lsu_bus_buffer.scala 385:92] + node _T_2072 = bits(_T_2054, 5, 5) @[lsu_bus_buffer.scala 385:101] + node _T_2073 = or(_T_2071, _T_2072) @[lsu_bus_buffer.scala 385:98] + node _T_2074 = bits(_T_2054, 7, 7) @[lsu_bus_buffer.scala 385:107] + node _T_2075 = or(_T_2073, _T_2074) @[lsu_bus_buffer.scala 385:104] + node _T_2076 = cat(_T_2061, _T_2068) @[Cat.scala 29:58] + node _T_2077 = cat(_T_2076, _T_2075) @[Cat.scala 29:58] + CmdPtr0 <= _T_2077 @[lsu_bus_buffer.scala 390:11] + node _T_2078 = mux(UInt<1>("h00"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_2079 = cat(_T_2078, CmdPtr1Dec) @[Cat.scala 29:58] + node _T_2080 = bits(_T_2079, 4, 4) @[lsu_bus_buffer.scala 385:39] + node _T_2081 = bits(_T_2079, 5, 5) @[lsu_bus_buffer.scala 385:45] + node _T_2082 = or(_T_2080, _T_2081) @[lsu_bus_buffer.scala 385:42] + node _T_2083 = bits(_T_2079, 6, 6) @[lsu_bus_buffer.scala 385:51] + node _T_2084 = or(_T_2082, _T_2083) @[lsu_bus_buffer.scala 385:48] + node _T_2085 = bits(_T_2079, 7, 7) @[lsu_bus_buffer.scala 385:57] + node _T_2086 = or(_T_2084, _T_2085) @[lsu_bus_buffer.scala 385:54] + node _T_2087 = bits(_T_2079, 2, 2) @[lsu_bus_buffer.scala 385:64] + node _T_2088 = bits(_T_2079, 3, 3) @[lsu_bus_buffer.scala 385:70] + node _T_2089 = or(_T_2087, _T_2088) @[lsu_bus_buffer.scala 385:67] + node _T_2090 = bits(_T_2079, 6, 6) @[lsu_bus_buffer.scala 385:76] + node _T_2091 = or(_T_2089, _T_2090) @[lsu_bus_buffer.scala 385:73] + node _T_2092 = bits(_T_2079, 7, 7) @[lsu_bus_buffer.scala 385:82] + node _T_2093 = or(_T_2091, _T_2092) @[lsu_bus_buffer.scala 385:79] + node _T_2094 = bits(_T_2079, 1, 1) @[lsu_bus_buffer.scala 385:89] + node _T_2095 = bits(_T_2079, 3, 3) @[lsu_bus_buffer.scala 385:95] + node _T_2096 = or(_T_2094, _T_2095) @[lsu_bus_buffer.scala 385:92] + node _T_2097 = bits(_T_2079, 5, 5) @[lsu_bus_buffer.scala 385:101] + node _T_2098 = or(_T_2096, _T_2097) @[lsu_bus_buffer.scala 385:98] + node _T_2099 = bits(_T_2079, 7, 7) @[lsu_bus_buffer.scala 385:107] + node _T_2100 = or(_T_2098, _T_2099) @[lsu_bus_buffer.scala 385:104] + node _T_2101 = cat(_T_2086, _T_2093) @[Cat.scala 29:58] + node _T_2102 = cat(_T_2101, _T_2100) @[Cat.scala 29:58] + CmdPtr1 <= _T_2102 @[lsu_bus_buffer.scala 392:11] + node _T_2103 = mux(UInt<1>("h00"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_2104 = cat(_T_2103, RspPtrDec) @[Cat.scala 29:58] + node _T_2105 = bits(_T_2104, 4, 4) @[lsu_bus_buffer.scala 385:39] + node _T_2106 = bits(_T_2104, 5, 5) @[lsu_bus_buffer.scala 385:45] + node _T_2107 = or(_T_2105, _T_2106) @[lsu_bus_buffer.scala 385:42] + node _T_2108 = bits(_T_2104, 6, 6) @[lsu_bus_buffer.scala 385:51] + node _T_2109 = or(_T_2107, _T_2108) @[lsu_bus_buffer.scala 385:48] + node _T_2110 = bits(_T_2104, 7, 7) @[lsu_bus_buffer.scala 385:57] + node _T_2111 = or(_T_2109, _T_2110) @[lsu_bus_buffer.scala 385:54] + node _T_2112 = bits(_T_2104, 2, 2) @[lsu_bus_buffer.scala 385:64] + node _T_2113 = bits(_T_2104, 3, 3) @[lsu_bus_buffer.scala 385:70] + node _T_2114 = or(_T_2112, _T_2113) @[lsu_bus_buffer.scala 385:67] + node _T_2115 = bits(_T_2104, 6, 6) @[lsu_bus_buffer.scala 385:76] + node _T_2116 = or(_T_2114, _T_2115) @[lsu_bus_buffer.scala 385:73] + node _T_2117 = bits(_T_2104, 7, 7) @[lsu_bus_buffer.scala 385:82] + node _T_2118 = or(_T_2116, _T_2117) @[lsu_bus_buffer.scala 385:79] + node _T_2119 = bits(_T_2104, 1, 1) @[lsu_bus_buffer.scala 385:89] + node _T_2120 = bits(_T_2104, 3, 3) @[lsu_bus_buffer.scala 385:95] + node _T_2121 = or(_T_2119, _T_2120) @[lsu_bus_buffer.scala 385:92] + node _T_2122 = bits(_T_2104, 5, 5) @[lsu_bus_buffer.scala 385:101] + node _T_2123 = or(_T_2121, _T_2122) @[lsu_bus_buffer.scala 385:98] + node _T_2124 = bits(_T_2104, 7, 7) @[lsu_bus_buffer.scala 385:107] + node _T_2125 = or(_T_2123, _T_2124) @[lsu_bus_buffer.scala 385:104] + node _T_2126 = cat(_T_2111, _T_2118) @[Cat.scala 29:58] + node _T_2127 = cat(_T_2126, _T_2125) @[Cat.scala 29:58] + RspPtr <= _T_2127 @[lsu_bus_buffer.scala 393:10] + wire buf_state_en : UInt<1>[4] @[lsu_bus_buffer.scala 394:26] + buf_state_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 395:16] + buf_state_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 395:16] + buf_state_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 395:16] + buf_state_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 395:16] + wire buf_rspageQ : UInt<4>[4] @[lsu_bus_buffer.scala 396:25] + buf_rspageQ[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 397:15] + buf_rspageQ[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 397:15] + buf_rspageQ[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 397:15] + buf_rspageQ[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 397:15] + wire buf_rspage_set : UInt<4>[4] @[lsu_bus_buffer.scala 398:28] + buf_rspage_set[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 399:18] + buf_rspage_set[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 399:18] + buf_rspage_set[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 399:18] + buf_rspage_set[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 399:18] + wire buf_rspage_in : UInt<4>[4] @[lsu_bus_buffer.scala 400:27] + buf_rspage_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 401:17] + buf_rspage_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 401:17] + buf_rspage_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 401:17] + buf_rspage_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 401:17] + wire buf_rspage : UInt<4>[4] @[lsu_bus_buffer.scala 402:24] + buf_rspage[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 403:14] + buf_rspage[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 403:14] + buf_rspage[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 403:14] + buf_rspage[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 403:14] + node _T_2128 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 405:83] + node _T_2129 = and(_T_2128, buf_state_en[0]) @[lsu_bus_buffer.scala 405:94] + node _T_2130 = eq(buf_state[0], UInt<3>("h01")) @[lsu_bus_buffer.scala 406:20] + node _T_2131 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 406:47] + node _T_2132 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 406:59] + node _T_2133 = and(_T_2131, _T_2132) @[lsu_bus_buffer.scala 406:57] + node _T_2134 = or(_T_2130, _T_2133) @[lsu_bus_buffer.scala 406:31] + node _T_2135 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 407:23] + node _T_2136 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 407:53] + node _T_2137 = and(_T_2135, _T_2136) @[lsu_bus_buffer.scala 407:41] + node _T_2138 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 407:83] + node _T_2139 = and(_T_2137, _T_2138) @[lsu_bus_buffer.scala 407:71] + node _T_2140 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 407:104] + node _T_2141 = and(_T_2139, _T_2140) @[lsu_bus_buffer.scala 407:92] + node _T_2142 = or(_T_2134, _T_2141) @[lsu_bus_buffer.scala 406:86] + node _T_2143 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:17] + node _T_2144 = and(_T_2143, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:35] + node _T_2145 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 408:64] + node _T_2146 = and(_T_2144, _T_2145) @[lsu_bus_buffer.scala 408:52] + node _T_2147 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 408:85] + node _T_2148 = and(_T_2146, _T_2147) @[lsu_bus_buffer.scala 408:73] + node _T_2149 = or(_T_2142, _T_2148) @[lsu_bus_buffer.scala 407:114] + node _T_2150 = and(_T_2129, _T_2149) @[lsu_bus_buffer.scala 405:113] + node _T_2151 = bits(buf_age[0], 0, 0) @[lsu_bus_buffer.scala 408:109] + node _T_2152 = or(_T_2150, _T_2151) @[lsu_bus_buffer.scala 408:97] + node _T_2153 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 405:83] + node _T_2154 = and(_T_2153, buf_state_en[0]) @[lsu_bus_buffer.scala 405:94] + node _T_2155 = eq(buf_state[1], UInt<3>("h01")) @[lsu_bus_buffer.scala 406:20] + node _T_2156 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 406:47] + node _T_2157 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 406:59] + node _T_2158 = and(_T_2156, _T_2157) @[lsu_bus_buffer.scala 406:57] + node _T_2159 = or(_T_2155, _T_2158) @[lsu_bus_buffer.scala 406:31] + node _T_2160 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 407:23] + node _T_2161 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 407:53] + node _T_2162 = and(_T_2160, _T_2161) @[lsu_bus_buffer.scala 407:41] + node _T_2163 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 407:83] + node _T_2164 = and(_T_2162, _T_2163) @[lsu_bus_buffer.scala 407:71] + node _T_2165 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 407:104] + node _T_2166 = and(_T_2164, _T_2165) @[lsu_bus_buffer.scala 407:92] + node _T_2167 = or(_T_2159, _T_2166) @[lsu_bus_buffer.scala 406:86] + node _T_2168 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:17] + node _T_2169 = and(_T_2168, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:35] + node _T_2170 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 408:64] + node _T_2171 = and(_T_2169, _T_2170) @[lsu_bus_buffer.scala 408:52] + node _T_2172 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 408:85] + node _T_2173 = and(_T_2171, _T_2172) @[lsu_bus_buffer.scala 408:73] + node _T_2174 = or(_T_2167, _T_2173) @[lsu_bus_buffer.scala 407:114] + node _T_2175 = and(_T_2154, _T_2174) @[lsu_bus_buffer.scala 405:113] + node _T_2176 = bits(buf_age[0], 1, 1) @[lsu_bus_buffer.scala 408:109] + node _T_2177 = or(_T_2175, _T_2176) @[lsu_bus_buffer.scala 408:97] + node _T_2178 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 405:83] + node _T_2179 = and(_T_2178, buf_state_en[0]) @[lsu_bus_buffer.scala 405:94] + node _T_2180 = eq(buf_state[2], UInt<3>("h01")) @[lsu_bus_buffer.scala 406:20] + node _T_2181 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 406:47] + node _T_2182 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 406:59] + node _T_2183 = and(_T_2181, _T_2182) @[lsu_bus_buffer.scala 406:57] + node _T_2184 = or(_T_2180, _T_2183) @[lsu_bus_buffer.scala 406:31] + node _T_2185 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 407:23] + node _T_2186 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 407:53] + node _T_2187 = and(_T_2185, _T_2186) @[lsu_bus_buffer.scala 407:41] + node _T_2188 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 407:83] + node _T_2189 = and(_T_2187, _T_2188) @[lsu_bus_buffer.scala 407:71] + node _T_2190 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 407:104] + node _T_2191 = and(_T_2189, _T_2190) @[lsu_bus_buffer.scala 407:92] + node _T_2192 = or(_T_2184, _T_2191) @[lsu_bus_buffer.scala 406:86] + node _T_2193 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:17] + node _T_2194 = and(_T_2193, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:35] + node _T_2195 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 408:64] + node _T_2196 = and(_T_2194, _T_2195) @[lsu_bus_buffer.scala 408:52] + node _T_2197 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 408:85] + node _T_2198 = and(_T_2196, _T_2197) @[lsu_bus_buffer.scala 408:73] + node _T_2199 = or(_T_2192, _T_2198) @[lsu_bus_buffer.scala 407:114] + node _T_2200 = and(_T_2179, _T_2199) @[lsu_bus_buffer.scala 405:113] + node _T_2201 = bits(buf_age[0], 2, 2) @[lsu_bus_buffer.scala 408:109] + node _T_2202 = or(_T_2200, _T_2201) @[lsu_bus_buffer.scala 408:97] + node _T_2203 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 405:83] + node _T_2204 = and(_T_2203, buf_state_en[0]) @[lsu_bus_buffer.scala 405:94] + node _T_2205 = eq(buf_state[3], UInt<3>("h01")) @[lsu_bus_buffer.scala 406:20] + node _T_2206 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 406:47] + node _T_2207 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 406:59] + node _T_2208 = and(_T_2206, _T_2207) @[lsu_bus_buffer.scala 406:57] + node _T_2209 = or(_T_2205, _T_2208) @[lsu_bus_buffer.scala 406:31] + node _T_2210 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 407:23] + node _T_2211 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 407:53] + node _T_2212 = and(_T_2210, _T_2211) @[lsu_bus_buffer.scala 407:41] + node _T_2213 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 407:83] + node _T_2214 = and(_T_2212, _T_2213) @[lsu_bus_buffer.scala 407:71] + node _T_2215 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 407:104] + node _T_2216 = and(_T_2214, _T_2215) @[lsu_bus_buffer.scala 407:92] + node _T_2217 = or(_T_2209, _T_2216) @[lsu_bus_buffer.scala 406:86] + node _T_2218 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:17] + node _T_2219 = and(_T_2218, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:35] + node _T_2220 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 408:64] + node _T_2221 = and(_T_2219, _T_2220) @[lsu_bus_buffer.scala 408:52] + node _T_2222 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 408:85] + node _T_2223 = and(_T_2221, _T_2222) @[lsu_bus_buffer.scala 408:73] + node _T_2224 = or(_T_2217, _T_2223) @[lsu_bus_buffer.scala 407:114] + node _T_2225 = and(_T_2204, _T_2224) @[lsu_bus_buffer.scala 405:113] + node _T_2226 = bits(buf_age[0], 3, 3) @[lsu_bus_buffer.scala 408:109] + node _T_2227 = or(_T_2225, _T_2226) @[lsu_bus_buffer.scala 408:97] + node _T_2228 = cat(_T_2227, _T_2202) @[Cat.scala 29:58] + node _T_2229 = cat(_T_2228, _T_2177) @[Cat.scala 29:58] + node buf_age_in_0 = cat(_T_2229, _T_2152) @[Cat.scala 29:58] + node _T_2230 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 405:83] + node _T_2231 = and(_T_2230, buf_state_en[1]) @[lsu_bus_buffer.scala 405:94] + node _T_2232 = eq(buf_state[0], UInt<3>("h01")) @[lsu_bus_buffer.scala 406:20] + node _T_2233 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 406:47] + node _T_2234 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 406:59] + node _T_2235 = and(_T_2233, _T_2234) @[lsu_bus_buffer.scala 406:57] + node _T_2236 = or(_T_2232, _T_2235) @[lsu_bus_buffer.scala 406:31] + node _T_2237 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 407:23] + node _T_2238 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 407:53] + node _T_2239 = and(_T_2237, _T_2238) @[lsu_bus_buffer.scala 407:41] + node _T_2240 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 407:83] + node _T_2241 = and(_T_2239, _T_2240) @[lsu_bus_buffer.scala 407:71] + node _T_2242 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 407:104] + node _T_2243 = and(_T_2241, _T_2242) @[lsu_bus_buffer.scala 407:92] + node _T_2244 = or(_T_2236, _T_2243) @[lsu_bus_buffer.scala 406:86] + node _T_2245 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:17] + node _T_2246 = and(_T_2245, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:35] + node _T_2247 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 408:64] + node _T_2248 = and(_T_2246, _T_2247) @[lsu_bus_buffer.scala 408:52] + node _T_2249 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 408:85] + node _T_2250 = and(_T_2248, _T_2249) @[lsu_bus_buffer.scala 408:73] + node _T_2251 = or(_T_2244, _T_2250) @[lsu_bus_buffer.scala 407:114] + node _T_2252 = and(_T_2231, _T_2251) @[lsu_bus_buffer.scala 405:113] + node _T_2253 = bits(buf_age[1], 0, 0) @[lsu_bus_buffer.scala 408:109] + node _T_2254 = or(_T_2252, _T_2253) @[lsu_bus_buffer.scala 408:97] + node _T_2255 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 405:83] + node _T_2256 = and(_T_2255, buf_state_en[1]) @[lsu_bus_buffer.scala 405:94] + node _T_2257 = eq(buf_state[1], UInt<3>("h01")) @[lsu_bus_buffer.scala 406:20] + node _T_2258 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 406:47] + node _T_2259 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 406:59] + node _T_2260 = and(_T_2258, _T_2259) @[lsu_bus_buffer.scala 406:57] + node _T_2261 = or(_T_2257, _T_2260) @[lsu_bus_buffer.scala 406:31] + node _T_2262 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 407:23] + node _T_2263 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 407:53] + node _T_2264 = and(_T_2262, _T_2263) @[lsu_bus_buffer.scala 407:41] + node _T_2265 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 407:83] + node _T_2266 = and(_T_2264, _T_2265) @[lsu_bus_buffer.scala 407:71] + node _T_2267 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 407:104] + node _T_2268 = and(_T_2266, _T_2267) @[lsu_bus_buffer.scala 407:92] + node _T_2269 = or(_T_2261, _T_2268) @[lsu_bus_buffer.scala 406:86] + node _T_2270 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:17] + node _T_2271 = and(_T_2270, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:35] + node _T_2272 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 408:64] + node _T_2273 = and(_T_2271, _T_2272) @[lsu_bus_buffer.scala 408:52] + node _T_2274 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 408:85] + node _T_2275 = and(_T_2273, _T_2274) @[lsu_bus_buffer.scala 408:73] + node _T_2276 = or(_T_2269, _T_2275) @[lsu_bus_buffer.scala 407:114] + node _T_2277 = and(_T_2256, _T_2276) @[lsu_bus_buffer.scala 405:113] + node _T_2278 = bits(buf_age[1], 1, 1) @[lsu_bus_buffer.scala 408:109] + node _T_2279 = or(_T_2277, _T_2278) @[lsu_bus_buffer.scala 408:97] + node _T_2280 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 405:83] + node _T_2281 = and(_T_2280, buf_state_en[1]) @[lsu_bus_buffer.scala 405:94] + node _T_2282 = eq(buf_state[2], UInt<3>("h01")) @[lsu_bus_buffer.scala 406:20] + node _T_2283 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 406:47] + node _T_2284 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 406:59] + node _T_2285 = and(_T_2283, _T_2284) @[lsu_bus_buffer.scala 406:57] + node _T_2286 = or(_T_2282, _T_2285) @[lsu_bus_buffer.scala 406:31] + node _T_2287 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 407:23] + node _T_2288 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 407:53] + node _T_2289 = and(_T_2287, _T_2288) @[lsu_bus_buffer.scala 407:41] + node _T_2290 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 407:83] + node _T_2291 = and(_T_2289, _T_2290) @[lsu_bus_buffer.scala 407:71] + node _T_2292 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 407:104] + node _T_2293 = and(_T_2291, _T_2292) @[lsu_bus_buffer.scala 407:92] + node _T_2294 = or(_T_2286, _T_2293) @[lsu_bus_buffer.scala 406:86] + node _T_2295 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:17] + node _T_2296 = and(_T_2295, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:35] + node _T_2297 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 408:64] + node _T_2298 = and(_T_2296, _T_2297) @[lsu_bus_buffer.scala 408:52] + node _T_2299 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 408:85] + node _T_2300 = and(_T_2298, _T_2299) @[lsu_bus_buffer.scala 408:73] + node _T_2301 = or(_T_2294, _T_2300) @[lsu_bus_buffer.scala 407:114] + node _T_2302 = and(_T_2281, _T_2301) @[lsu_bus_buffer.scala 405:113] + node _T_2303 = bits(buf_age[1], 2, 2) @[lsu_bus_buffer.scala 408:109] + node _T_2304 = or(_T_2302, _T_2303) @[lsu_bus_buffer.scala 408:97] + node _T_2305 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 405:83] + node _T_2306 = and(_T_2305, buf_state_en[1]) @[lsu_bus_buffer.scala 405:94] + node _T_2307 = eq(buf_state[3], UInt<3>("h01")) @[lsu_bus_buffer.scala 406:20] + node _T_2308 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 406:47] + node _T_2309 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 406:59] + node _T_2310 = and(_T_2308, _T_2309) @[lsu_bus_buffer.scala 406:57] + node _T_2311 = or(_T_2307, _T_2310) @[lsu_bus_buffer.scala 406:31] + node _T_2312 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 407:23] + node _T_2313 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 407:53] + node _T_2314 = and(_T_2312, _T_2313) @[lsu_bus_buffer.scala 407:41] + node _T_2315 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 407:83] + node _T_2316 = and(_T_2314, _T_2315) @[lsu_bus_buffer.scala 407:71] + node _T_2317 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 407:104] + node _T_2318 = and(_T_2316, _T_2317) @[lsu_bus_buffer.scala 407:92] + node _T_2319 = or(_T_2311, _T_2318) @[lsu_bus_buffer.scala 406:86] + node _T_2320 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:17] + node _T_2321 = and(_T_2320, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:35] + node _T_2322 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 408:64] + node _T_2323 = and(_T_2321, _T_2322) @[lsu_bus_buffer.scala 408:52] + node _T_2324 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 408:85] + node _T_2325 = and(_T_2323, _T_2324) @[lsu_bus_buffer.scala 408:73] + node _T_2326 = or(_T_2319, _T_2325) @[lsu_bus_buffer.scala 407:114] + node _T_2327 = and(_T_2306, _T_2326) @[lsu_bus_buffer.scala 405:113] + node _T_2328 = bits(buf_age[1], 3, 3) @[lsu_bus_buffer.scala 408:109] + node _T_2329 = or(_T_2327, _T_2328) @[lsu_bus_buffer.scala 408:97] + node _T_2330 = cat(_T_2329, _T_2304) @[Cat.scala 29:58] + node _T_2331 = cat(_T_2330, _T_2279) @[Cat.scala 29:58] + node buf_age_in_1 = cat(_T_2331, _T_2254) @[Cat.scala 29:58] + node _T_2332 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 405:83] + node _T_2333 = and(_T_2332, buf_state_en[2]) @[lsu_bus_buffer.scala 405:94] + node _T_2334 = eq(buf_state[0], UInt<3>("h01")) @[lsu_bus_buffer.scala 406:20] + node _T_2335 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 406:47] + node _T_2336 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 406:59] + node _T_2337 = and(_T_2335, _T_2336) @[lsu_bus_buffer.scala 406:57] + node _T_2338 = or(_T_2334, _T_2337) @[lsu_bus_buffer.scala 406:31] + node _T_2339 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 407:23] + node _T_2340 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 407:53] + node _T_2341 = and(_T_2339, _T_2340) @[lsu_bus_buffer.scala 407:41] + node _T_2342 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 407:83] + node _T_2343 = and(_T_2341, _T_2342) @[lsu_bus_buffer.scala 407:71] + node _T_2344 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 407:104] + node _T_2345 = and(_T_2343, _T_2344) @[lsu_bus_buffer.scala 407:92] + node _T_2346 = or(_T_2338, _T_2345) @[lsu_bus_buffer.scala 406:86] + node _T_2347 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:17] + node _T_2348 = and(_T_2347, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:35] + node _T_2349 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 408:64] + node _T_2350 = and(_T_2348, _T_2349) @[lsu_bus_buffer.scala 408:52] + node _T_2351 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 408:85] + node _T_2352 = and(_T_2350, _T_2351) @[lsu_bus_buffer.scala 408:73] + node _T_2353 = or(_T_2346, _T_2352) @[lsu_bus_buffer.scala 407:114] + node _T_2354 = and(_T_2333, _T_2353) @[lsu_bus_buffer.scala 405:113] + node _T_2355 = bits(buf_age[2], 0, 0) @[lsu_bus_buffer.scala 408:109] + node _T_2356 = or(_T_2354, _T_2355) @[lsu_bus_buffer.scala 408:97] + node _T_2357 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 405:83] + node _T_2358 = and(_T_2357, buf_state_en[2]) @[lsu_bus_buffer.scala 405:94] + node _T_2359 = eq(buf_state[1], UInt<3>("h01")) @[lsu_bus_buffer.scala 406:20] + node _T_2360 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 406:47] + node _T_2361 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 406:59] + node _T_2362 = and(_T_2360, _T_2361) @[lsu_bus_buffer.scala 406:57] + node _T_2363 = or(_T_2359, _T_2362) @[lsu_bus_buffer.scala 406:31] + node _T_2364 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 407:23] + node _T_2365 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 407:53] + node _T_2366 = and(_T_2364, _T_2365) @[lsu_bus_buffer.scala 407:41] + node _T_2367 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 407:83] + node _T_2368 = and(_T_2366, _T_2367) @[lsu_bus_buffer.scala 407:71] + node _T_2369 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 407:104] + node _T_2370 = and(_T_2368, _T_2369) @[lsu_bus_buffer.scala 407:92] + node _T_2371 = or(_T_2363, _T_2370) @[lsu_bus_buffer.scala 406:86] + node _T_2372 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:17] + node _T_2373 = and(_T_2372, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:35] + node _T_2374 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 408:64] + node _T_2375 = and(_T_2373, _T_2374) @[lsu_bus_buffer.scala 408:52] + node _T_2376 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 408:85] + node _T_2377 = and(_T_2375, _T_2376) @[lsu_bus_buffer.scala 408:73] + node _T_2378 = or(_T_2371, _T_2377) @[lsu_bus_buffer.scala 407:114] + node _T_2379 = and(_T_2358, _T_2378) @[lsu_bus_buffer.scala 405:113] + node _T_2380 = bits(buf_age[2], 1, 1) @[lsu_bus_buffer.scala 408:109] + node _T_2381 = or(_T_2379, _T_2380) @[lsu_bus_buffer.scala 408:97] + node _T_2382 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 405:83] + node _T_2383 = and(_T_2382, buf_state_en[2]) @[lsu_bus_buffer.scala 405:94] + node _T_2384 = eq(buf_state[2], UInt<3>("h01")) @[lsu_bus_buffer.scala 406:20] + node _T_2385 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 406:47] + node _T_2386 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 406:59] + node _T_2387 = and(_T_2385, _T_2386) @[lsu_bus_buffer.scala 406:57] + node _T_2388 = or(_T_2384, _T_2387) @[lsu_bus_buffer.scala 406:31] + node _T_2389 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 407:23] + node _T_2390 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 407:53] + node _T_2391 = and(_T_2389, _T_2390) @[lsu_bus_buffer.scala 407:41] + node _T_2392 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 407:83] + node _T_2393 = and(_T_2391, _T_2392) @[lsu_bus_buffer.scala 407:71] + node _T_2394 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 407:104] + node _T_2395 = and(_T_2393, _T_2394) @[lsu_bus_buffer.scala 407:92] + node _T_2396 = or(_T_2388, _T_2395) @[lsu_bus_buffer.scala 406:86] + node _T_2397 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:17] + node _T_2398 = and(_T_2397, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:35] + node _T_2399 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 408:64] + node _T_2400 = and(_T_2398, _T_2399) @[lsu_bus_buffer.scala 408:52] + node _T_2401 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 408:85] + node _T_2402 = and(_T_2400, _T_2401) @[lsu_bus_buffer.scala 408:73] + node _T_2403 = or(_T_2396, _T_2402) @[lsu_bus_buffer.scala 407:114] + node _T_2404 = and(_T_2383, _T_2403) @[lsu_bus_buffer.scala 405:113] + node _T_2405 = bits(buf_age[2], 2, 2) @[lsu_bus_buffer.scala 408:109] + node _T_2406 = or(_T_2404, _T_2405) @[lsu_bus_buffer.scala 408:97] + node _T_2407 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 405:83] + node _T_2408 = and(_T_2407, buf_state_en[2]) @[lsu_bus_buffer.scala 405:94] + node _T_2409 = eq(buf_state[3], UInt<3>("h01")) @[lsu_bus_buffer.scala 406:20] + node _T_2410 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 406:47] + node _T_2411 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 406:59] + node _T_2412 = and(_T_2410, _T_2411) @[lsu_bus_buffer.scala 406:57] + node _T_2413 = or(_T_2409, _T_2412) @[lsu_bus_buffer.scala 406:31] + node _T_2414 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 407:23] + node _T_2415 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 407:53] + node _T_2416 = and(_T_2414, _T_2415) @[lsu_bus_buffer.scala 407:41] + node _T_2417 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 407:83] + node _T_2418 = and(_T_2416, _T_2417) @[lsu_bus_buffer.scala 407:71] + node _T_2419 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 407:104] + node _T_2420 = and(_T_2418, _T_2419) @[lsu_bus_buffer.scala 407:92] + node _T_2421 = or(_T_2413, _T_2420) @[lsu_bus_buffer.scala 406:86] + node _T_2422 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:17] + node _T_2423 = and(_T_2422, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:35] + node _T_2424 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 408:64] + node _T_2425 = and(_T_2423, _T_2424) @[lsu_bus_buffer.scala 408:52] + node _T_2426 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 408:85] + node _T_2427 = and(_T_2425, _T_2426) @[lsu_bus_buffer.scala 408:73] + node _T_2428 = or(_T_2421, _T_2427) @[lsu_bus_buffer.scala 407:114] + node _T_2429 = and(_T_2408, _T_2428) @[lsu_bus_buffer.scala 405:113] + node _T_2430 = bits(buf_age[2], 3, 3) @[lsu_bus_buffer.scala 408:109] + node _T_2431 = or(_T_2429, _T_2430) @[lsu_bus_buffer.scala 408:97] + node _T_2432 = cat(_T_2431, _T_2406) @[Cat.scala 29:58] + node _T_2433 = cat(_T_2432, _T_2381) @[Cat.scala 29:58] + node buf_age_in_2 = cat(_T_2433, _T_2356) @[Cat.scala 29:58] + node _T_2434 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 405:83] + node _T_2435 = and(_T_2434, buf_state_en[3]) @[lsu_bus_buffer.scala 405:94] + node _T_2436 = eq(buf_state[0], UInt<3>("h01")) @[lsu_bus_buffer.scala 406:20] + node _T_2437 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 406:47] + node _T_2438 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 406:59] + node _T_2439 = and(_T_2437, _T_2438) @[lsu_bus_buffer.scala 406:57] + node _T_2440 = or(_T_2436, _T_2439) @[lsu_bus_buffer.scala 406:31] + node _T_2441 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 407:23] + node _T_2442 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 407:53] + node _T_2443 = and(_T_2441, _T_2442) @[lsu_bus_buffer.scala 407:41] + node _T_2444 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 407:83] + node _T_2445 = and(_T_2443, _T_2444) @[lsu_bus_buffer.scala 407:71] + node _T_2446 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 407:104] + node _T_2447 = and(_T_2445, _T_2446) @[lsu_bus_buffer.scala 407:92] + node _T_2448 = or(_T_2440, _T_2447) @[lsu_bus_buffer.scala 406:86] + node _T_2449 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:17] + node _T_2450 = and(_T_2449, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:35] + node _T_2451 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 408:64] + node _T_2452 = and(_T_2450, _T_2451) @[lsu_bus_buffer.scala 408:52] + node _T_2453 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 408:85] + node _T_2454 = and(_T_2452, _T_2453) @[lsu_bus_buffer.scala 408:73] + node _T_2455 = or(_T_2448, _T_2454) @[lsu_bus_buffer.scala 407:114] + node _T_2456 = and(_T_2435, _T_2455) @[lsu_bus_buffer.scala 405:113] + node _T_2457 = bits(buf_age[3], 0, 0) @[lsu_bus_buffer.scala 408:109] + node _T_2458 = or(_T_2456, _T_2457) @[lsu_bus_buffer.scala 408:97] + node _T_2459 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 405:83] + node _T_2460 = and(_T_2459, buf_state_en[3]) @[lsu_bus_buffer.scala 405:94] + node _T_2461 = eq(buf_state[1], UInt<3>("h01")) @[lsu_bus_buffer.scala 406:20] + node _T_2462 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 406:47] + node _T_2463 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 406:59] + node _T_2464 = and(_T_2462, _T_2463) @[lsu_bus_buffer.scala 406:57] + node _T_2465 = or(_T_2461, _T_2464) @[lsu_bus_buffer.scala 406:31] + node _T_2466 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 407:23] + node _T_2467 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 407:53] + node _T_2468 = and(_T_2466, _T_2467) @[lsu_bus_buffer.scala 407:41] + node _T_2469 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 407:83] + node _T_2470 = and(_T_2468, _T_2469) @[lsu_bus_buffer.scala 407:71] + node _T_2471 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 407:104] + node _T_2472 = and(_T_2470, _T_2471) @[lsu_bus_buffer.scala 407:92] + node _T_2473 = or(_T_2465, _T_2472) @[lsu_bus_buffer.scala 406:86] + node _T_2474 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:17] + node _T_2475 = and(_T_2474, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:35] + node _T_2476 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 408:64] + node _T_2477 = and(_T_2475, _T_2476) @[lsu_bus_buffer.scala 408:52] + node _T_2478 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 408:85] + node _T_2479 = and(_T_2477, _T_2478) @[lsu_bus_buffer.scala 408:73] + node _T_2480 = or(_T_2473, _T_2479) @[lsu_bus_buffer.scala 407:114] + node _T_2481 = and(_T_2460, _T_2480) @[lsu_bus_buffer.scala 405:113] + node _T_2482 = bits(buf_age[3], 1, 1) @[lsu_bus_buffer.scala 408:109] + node _T_2483 = or(_T_2481, _T_2482) @[lsu_bus_buffer.scala 408:97] + node _T_2484 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 405:83] + node _T_2485 = and(_T_2484, buf_state_en[3]) @[lsu_bus_buffer.scala 405:94] + node _T_2486 = eq(buf_state[2], UInt<3>("h01")) @[lsu_bus_buffer.scala 406:20] + node _T_2487 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 406:47] + node _T_2488 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 406:59] + node _T_2489 = and(_T_2487, _T_2488) @[lsu_bus_buffer.scala 406:57] + node _T_2490 = or(_T_2486, _T_2489) @[lsu_bus_buffer.scala 406:31] + node _T_2491 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 407:23] + node _T_2492 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 407:53] + node _T_2493 = and(_T_2491, _T_2492) @[lsu_bus_buffer.scala 407:41] + node _T_2494 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 407:83] + node _T_2495 = and(_T_2493, _T_2494) @[lsu_bus_buffer.scala 407:71] + node _T_2496 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 407:104] + node _T_2497 = and(_T_2495, _T_2496) @[lsu_bus_buffer.scala 407:92] + node _T_2498 = or(_T_2490, _T_2497) @[lsu_bus_buffer.scala 406:86] + node _T_2499 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:17] + node _T_2500 = and(_T_2499, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:35] + node _T_2501 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 408:64] + node _T_2502 = and(_T_2500, _T_2501) @[lsu_bus_buffer.scala 408:52] + node _T_2503 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 408:85] + node _T_2504 = and(_T_2502, _T_2503) @[lsu_bus_buffer.scala 408:73] + node _T_2505 = or(_T_2498, _T_2504) @[lsu_bus_buffer.scala 407:114] + node _T_2506 = and(_T_2485, _T_2505) @[lsu_bus_buffer.scala 405:113] + node _T_2507 = bits(buf_age[3], 2, 2) @[lsu_bus_buffer.scala 408:109] + node _T_2508 = or(_T_2506, _T_2507) @[lsu_bus_buffer.scala 408:97] + node _T_2509 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 405:83] + node _T_2510 = and(_T_2509, buf_state_en[3]) @[lsu_bus_buffer.scala 405:94] + node _T_2511 = eq(buf_state[3], UInt<3>("h01")) @[lsu_bus_buffer.scala 406:20] + node _T_2512 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 406:47] + node _T_2513 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 406:59] + node _T_2514 = and(_T_2512, _T_2513) @[lsu_bus_buffer.scala 406:57] + node _T_2515 = or(_T_2511, _T_2514) @[lsu_bus_buffer.scala 406:31] + node _T_2516 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 407:23] + node _T_2517 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 407:53] + node _T_2518 = and(_T_2516, _T_2517) @[lsu_bus_buffer.scala 407:41] + node _T_2519 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 407:83] + node _T_2520 = and(_T_2518, _T_2519) @[lsu_bus_buffer.scala 407:71] + node _T_2521 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 407:104] + node _T_2522 = and(_T_2520, _T_2521) @[lsu_bus_buffer.scala 407:92] + node _T_2523 = or(_T_2515, _T_2522) @[lsu_bus_buffer.scala 406:86] + node _T_2524 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:17] + node _T_2525 = and(_T_2524, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:35] + node _T_2526 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 408:64] + node _T_2527 = and(_T_2525, _T_2526) @[lsu_bus_buffer.scala 408:52] + node _T_2528 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 408:85] + node _T_2529 = and(_T_2527, _T_2528) @[lsu_bus_buffer.scala 408:73] + node _T_2530 = or(_T_2523, _T_2529) @[lsu_bus_buffer.scala 407:114] + node _T_2531 = and(_T_2510, _T_2530) @[lsu_bus_buffer.scala 405:113] + node _T_2532 = bits(buf_age[3], 3, 3) @[lsu_bus_buffer.scala 408:109] + node _T_2533 = or(_T_2531, _T_2532) @[lsu_bus_buffer.scala 408:97] + node _T_2534 = cat(_T_2533, _T_2508) @[Cat.scala 29:58] + node _T_2535 = cat(_T_2534, _T_2483) @[Cat.scala 29:58] + node buf_age_in_3 = cat(_T_2535, _T_2458) @[Cat.scala 29:58] + wire buf_ageQ : UInt<4>[4] @[lsu_bus_buffer.scala 409:22] + buf_ageQ[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 410:12] + buf_ageQ[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 410:12] + buf_ageQ[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 410:12] + buf_ageQ[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 410:12] + node _T_2536 = bits(buf_ageQ[0], 0, 0) @[lsu_bus_buffer.scala 411:72] + node _T_2537 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 411:93] + node _T_2538 = and(_T_2537, buf_cmd_state_bus_en[0]) @[lsu_bus_buffer.scala 411:103] + node _T_2539 = eq(_T_2538, UInt<1>("h00")) @[lsu_bus_buffer.scala 411:78] + node _T_2540 = and(_T_2536, _T_2539) @[lsu_bus_buffer.scala 411:76] + node _T_2541 = bits(buf_ageQ[0], 1, 1) @[lsu_bus_buffer.scala 411:72] + node _T_2542 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 411:93] + node _T_2543 = and(_T_2542, buf_cmd_state_bus_en[1]) @[lsu_bus_buffer.scala 411:103] + node _T_2544 = eq(_T_2543, UInt<1>("h00")) @[lsu_bus_buffer.scala 411:78] + node _T_2545 = and(_T_2541, _T_2544) @[lsu_bus_buffer.scala 411:76] + node _T_2546 = bits(buf_ageQ[0], 2, 2) @[lsu_bus_buffer.scala 411:72] + node _T_2547 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 411:93] + node _T_2548 = and(_T_2547, buf_cmd_state_bus_en[2]) @[lsu_bus_buffer.scala 411:103] + node _T_2549 = eq(_T_2548, UInt<1>("h00")) @[lsu_bus_buffer.scala 411:78] + node _T_2550 = and(_T_2546, _T_2549) @[lsu_bus_buffer.scala 411:76] + node _T_2551 = bits(buf_ageQ[0], 3, 3) @[lsu_bus_buffer.scala 411:72] + node _T_2552 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 411:93] + node _T_2553 = and(_T_2552, buf_cmd_state_bus_en[3]) @[lsu_bus_buffer.scala 411:103] + node _T_2554 = eq(_T_2553, UInt<1>("h00")) @[lsu_bus_buffer.scala 411:78] + node _T_2555 = and(_T_2551, _T_2554) @[lsu_bus_buffer.scala 411:76] + node _T_2556 = cat(_T_2555, _T_2550) @[Cat.scala 29:58] + node _T_2557 = cat(_T_2556, _T_2545) @[Cat.scala 29:58] + node _T_2558 = cat(_T_2557, _T_2540) @[Cat.scala 29:58] + node _T_2559 = bits(buf_ageQ[1], 0, 0) @[lsu_bus_buffer.scala 411:72] + node _T_2560 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 411:93] + node _T_2561 = and(_T_2560, buf_cmd_state_bus_en[0]) @[lsu_bus_buffer.scala 411:103] + node _T_2562 = eq(_T_2561, UInt<1>("h00")) @[lsu_bus_buffer.scala 411:78] + node _T_2563 = and(_T_2559, _T_2562) @[lsu_bus_buffer.scala 411:76] + node _T_2564 = bits(buf_ageQ[1], 1, 1) @[lsu_bus_buffer.scala 411:72] + node _T_2565 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 411:93] + node _T_2566 = and(_T_2565, buf_cmd_state_bus_en[1]) @[lsu_bus_buffer.scala 411:103] + node _T_2567 = eq(_T_2566, UInt<1>("h00")) @[lsu_bus_buffer.scala 411:78] + node _T_2568 = and(_T_2564, _T_2567) @[lsu_bus_buffer.scala 411:76] + node _T_2569 = bits(buf_ageQ[1], 2, 2) @[lsu_bus_buffer.scala 411:72] + node _T_2570 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 411:93] + node _T_2571 = and(_T_2570, buf_cmd_state_bus_en[2]) @[lsu_bus_buffer.scala 411:103] + node _T_2572 = eq(_T_2571, UInt<1>("h00")) @[lsu_bus_buffer.scala 411:78] + node _T_2573 = and(_T_2569, _T_2572) @[lsu_bus_buffer.scala 411:76] + node _T_2574 = bits(buf_ageQ[1], 3, 3) @[lsu_bus_buffer.scala 411:72] + node _T_2575 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 411:93] + node _T_2576 = and(_T_2575, buf_cmd_state_bus_en[3]) @[lsu_bus_buffer.scala 411:103] + node _T_2577 = eq(_T_2576, UInt<1>("h00")) @[lsu_bus_buffer.scala 411:78] + node _T_2578 = and(_T_2574, _T_2577) @[lsu_bus_buffer.scala 411:76] + node _T_2579 = cat(_T_2578, _T_2573) @[Cat.scala 29:58] + node _T_2580 = cat(_T_2579, _T_2568) @[Cat.scala 29:58] + node _T_2581 = cat(_T_2580, _T_2563) @[Cat.scala 29:58] + node _T_2582 = bits(buf_ageQ[2], 0, 0) @[lsu_bus_buffer.scala 411:72] + node _T_2583 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 411:93] + node _T_2584 = and(_T_2583, buf_cmd_state_bus_en[0]) @[lsu_bus_buffer.scala 411:103] + node _T_2585 = eq(_T_2584, UInt<1>("h00")) @[lsu_bus_buffer.scala 411:78] + node _T_2586 = and(_T_2582, _T_2585) @[lsu_bus_buffer.scala 411:76] + node _T_2587 = bits(buf_ageQ[2], 1, 1) @[lsu_bus_buffer.scala 411:72] + node _T_2588 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 411:93] + node _T_2589 = and(_T_2588, buf_cmd_state_bus_en[1]) @[lsu_bus_buffer.scala 411:103] + node _T_2590 = eq(_T_2589, UInt<1>("h00")) @[lsu_bus_buffer.scala 411:78] + node _T_2591 = and(_T_2587, _T_2590) @[lsu_bus_buffer.scala 411:76] + node _T_2592 = bits(buf_ageQ[2], 2, 2) @[lsu_bus_buffer.scala 411:72] + node _T_2593 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 411:93] + node _T_2594 = and(_T_2593, buf_cmd_state_bus_en[2]) @[lsu_bus_buffer.scala 411:103] + node _T_2595 = eq(_T_2594, UInt<1>("h00")) @[lsu_bus_buffer.scala 411:78] + node _T_2596 = and(_T_2592, _T_2595) @[lsu_bus_buffer.scala 411:76] + node _T_2597 = bits(buf_ageQ[2], 3, 3) @[lsu_bus_buffer.scala 411:72] + node _T_2598 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 411:93] + node _T_2599 = and(_T_2598, buf_cmd_state_bus_en[3]) @[lsu_bus_buffer.scala 411:103] + node _T_2600 = eq(_T_2599, UInt<1>("h00")) @[lsu_bus_buffer.scala 411:78] + node _T_2601 = and(_T_2597, _T_2600) @[lsu_bus_buffer.scala 411:76] + node _T_2602 = cat(_T_2601, _T_2596) @[Cat.scala 29:58] + node _T_2603 = cat(_T_2602, _T_2591) @[Cat.scala 29:58] + node _T_2604 = cat(_T_2603, _T_2586) @[Cat.scala 29:58] + node _T_2605 = bits(buf_ageQ[3], 0, 0) @[lsu_bus_buffer.scala 411:72] + node _T_2606 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 411:93] + node _T_2607 = and(_T_2606, buf_cmd_state_bus_en[0]) @[lsu_bus_buffer.scala 411:103] + node _T_2608 = eq(_T_2607, UInt<1>("h00")) @[lsu_bus_buffer.scala 411:78] + node _T_2609 = and(_T_2605, _T_2608) @[lsu_bus_buffer.scala 411:76] + node _T_2610 = bits(buf_ageQ[3], 1, 1) @[lsu_bus_buffer.scala 411:72] + node _T_2611 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 411:93] + node _T_2612 = and(_T_2611, buf_cmd_state_bus_en[1]) @[lsu_bus_buffer.scala 411:103] + node _T_2613 = eq(_T_2612, UInt<1>("h00")) @[lsu_bus_buffer.scala 411:78] + node _T_2614 = and(_T_2610, _T_2613) @[lsu_bus_buffer.scala 411:76] + node _T_2615 = bits(buf_ageQ[3], 2, 2) @[lsu_bus_buffer.scala 411:72] + node _T_2616 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 411:93] + node _T_2617 = and(_T_2616, buf_cmd_state_bus_en[2]) @[lsu_bus_buffer.scala 411:103] + node _T_2618 = eq(_T_2617, UInt<1>("h00")) @[lsu_bus_buffer.scala 411:78] + node _T_2619 = and(_T_2615, _T_2618) @[lsu_bus_buffer.scala 411:76] + node _T_2620 = bits(buf_ageQ[3], 3, 3) @[lsu_bus_buffer.scala 411:72] + node _T_2621 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 411:93] + node _T_2622 = and(_T_2621, buf_cmd_state_bus_en[3]) @[lsu_bus_buffer.scala 411:103] + node _T_2623 = eq(_T_2622, UInt<1>("h00")) @[lsu_bus_buffer.scala 411:78] + node _T_2624 = and(_T_2620, _T_2623) @[lsu_bus_buffer.scala 411:76] + node _T_2625 = cat(_T_2624, _T_2619) @[Cat.scala 29:58] + node _T_2626 = cat(_T_2625, _T_2614) @[Cat.scala 29:58] + node _T_2627 = cat(_T_2626, _T_2609) @[Cat.scala 29:58] + buf_age[0] <= _T_2558 @[lsu_bus_buffer.scala 411:11] + buf_age[1] <= _T_2581 @[lsu_bus_buffer.scala 411:11] + buf_age[2] <= _T_2604 @[lsu_bus_buffer.scala 411:11] + buf_age[3] <= _T_2627 @[lsu_bus_buffer.scala 411:11] + node _T_2628 = eq(UInt<1>("h00"), UInt<1>("h00")) @[lsu_bus_buffer.scala 412:76] + node _T_2629 = bits(buf_age[0], 0, 0) @[lsu_bus_buffer.scala 412:100] + node _T_2630 = eq(_T_2629, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:89] + node _T_2631 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 412:119] + node _T_2632 = and(_T_2630, _T_2631) @[lsu_bus_buffer.scala 412:104] + node _T_2633 = mux(_T_2628, UInt<1>("h00"), _T_2632) @[lsu_bus_buffer.scala 412:72] + node _T_2634 = eq(UInt<1>("h00"), UInt<1>("h01")) @[lsu_bus_buffer.scala 412:76] + node _T_2635 = bits(buf_age[0], 1, 1) @[lsu_bus_buffer.scala 412:100] + node _T_2636 = eq(_T_2635, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:89] + node _T_2637 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 412:119] + node _T_2638 = and(_T_2636, _T_2637) @[lsu_bus_buffer.scala 412:104] + node _T_2639 = mux(_T_2634, UInt<1>("h00"), _T_2638) @[lsu_bus_buffer.scala 412:72] + node _T_2640 = eq(UInt<1>("h00"), UInt<2>("h02")) @[lsu_bus_buffer.scala 412:76] + node _T_2641 = bits(buf_age[0], 2, 2) @[lsu_bus_buffer.scala 412:100] + node _T_2642 = eq(_T_2641, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:89] + node _T_2643 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 412:119] + node _T_2644 = and(_T_2642, _T_2643) @[lsu_bus_buffer.scala 412:104] + node _T_2645 = mux(_T_2640, UInt<1>("h00"), _T_2644) @[lsu_bus_buffer.scala 412:72] + node _T_2646 = eq(UInt<1>("h00"), UInt<2>("h03")) @[lsu_bus_buffer.scala 412:76] + node _T_2647 = bits(buf_age[0], 3, 3) @[lsu_bus_buffer.scala 412:100] + node _T_2648 = eq(_T_2647, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:89] + node _T_2649 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 412:119] + node _T_2650 = and(_T_2648, _T_2649) @[lsu_bus_buffer.scala 412:104] + node _T_2651 = mux(_T_2646, UInt<1>("h00"), _T_2650) @[lsu_bus_buffer.scala 412:72] + node _T_2652 = cat(_T_2651, _T_2645) @[Cat.scala 29:58] + node _T_2653 = cat(_T_2652, _T_2639) @[Cat.scala 29:58] + node _T_2654 = cat(_T_2653, _T_2633) @[Cat.scala 29:58] + node _T_2655 = eq(UInt<1>("h01"), UInt<1>("h00")) @[lsu_bus_buffer.scala 412:76] + node _T_2656 = bits(buf_age[1], 0, 0) @[lsu_bus_buffer.scala 412:100] + node _T_2657 = eq(_T_2656, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:89] + node _T_2658 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 412:119] + node _T_2659 = and(_T_2657, _T_2658) @[lsu_bus_buffer.scala 412:104] + node _T_2660 = mux(_T_2655, UInt<1>("h00"), _T_2659) @[lsu_bus_buffer.scala 412:72] + node _T_2661 = eq(UInt<1>("h01"), UInt<1>("h01")) @[lsu_bus_buffer.scala 412:76] + node _T_2662 = bits(buf_age[1], 1, 1) @[lsu_bus_buffer.scala 412:100] + node _T_2663 = eq(_T_2662, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:89] + node _T_2664 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 412:119] + node _T_2665 = and(_T_2663, _T_2664) @[lsu_bus_buffer.scala 412:104] + node _T_2666 = mux(_T_2661, UInt<1>("h00"), _T_2665) @[lsu_bus_buffer.scala 412:72] + node _T_2667 = eq(UInt<1>("h01"), UInt<2>("h02")) @[lsu_bus_buffer.scala 412:76] + node _T_2668 = bits(buf_age[1], 2, 2) @[lsu_bus_buffer.scala 412:100] + node _T_2669 = eq(_T_2668, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:89] + node _T_2670 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 412:119] + node _T_2671 = and(_T_2669, _T_2670) @[lsu_bus_buffer.scala 412:104] + node _T_2672 = mux(_T_2667, UInt<1>("h00"), _T_2671) @[lsu_bus_buffer.scala 412:72] + node _T_2673 = eq(UInt<1>("h01"), UInt<2>("h03")) @[lsu_bus_buffer.scala 412:76] + node _T_2674 = bits(buf_age[1], 3, 3) @[lsu_bus_buffer.scala 412:100] + node _T_2675 = eq(_T_2674, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:89] + node _T_2676 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 412:119] + node _T_2677 = and(_T_2675, _T_2676) @[lsu_bus_buffer.scala 412:104] + node _T_2678 = mux(_T_2673, UInt<1>("h00"), _T_2677) @[lsu_bus_buffer.scala 412:72] + node _T_2679 = cat(_T_2678, _T_2672) @[Cat.scala 29:58] + node _T_2680 = cat(_T_2679, _T_2666) @[Cat.scala 29:58] + node _T_2681 = cat(_T_2680, _T_2660) @[Cat.scala 29:58] + node _T_2682 = eq(UInt<2>("h02"), UInt<1>("h00")) @[lsu_bus_buffer.scala 412:76] + node _T_2683 = bits(buf_age[2], 0, 0) @[lsu_bus_buffer.scala 412:100] + node _T_2684 = eq(_T_2683, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:89] + node _T_2685 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 412:119] + node _T_2686 = and(_T_2684, _T_2685) @[lsu_bus_buffer.scala 412:104] + node _T_2687 = mux(_T_2682, UInt<1>("h00"), _T_2686) @[lsu_bus_buffer.scala 412:72] + node _T_2688 = eq(UInt<2>("h02"), UInt<1>("h01")) @[lsu_bus_buffer.scala 412:76] + node _T_2689 = bits(buf_age[2], 1, 1) @[lsu_bus_buffer.scala 412:100] + node _T_2690 = eq(_T_2689, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:89] + node _T_2691 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 412:119] + node _T_2692 = and(_T_2690, _T_2691) @[lsu_bus_buffer.scala 412:104] + node _T_2693 = mux(_T_2688, UInt<1>("h00"), _T_2692) @[lsu_bus_buffer.scala 412:72] + node _T_2694 = eq(UInt<2>("h02"), UInt<2>("h02")) @[lsu_bus_buffer.scala 412:76] + node _T_2695 = bits(buf_age[2], 2, 2) @[lsu_bus_buffer.scala 412:100] + node _T_2696 = eq(_T_2695, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:89] + node _T_2697 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 412:119] + node _T_2698 = and(_T_2696, _T_2697) @[lsu_bus_buffer.scala 412:104] + node _T_2699 = mux(_T_2694, UInt<1>("h00"), _T_2698) @[lsu_bus_buffer.scala 412:72] + node _T_2700 = eq(UInt<2>("h02"), UInt<2>("h03")) @[lsu_bus_buffer.scala 412:76] + node _T_2701 = bits(buf_age[2], 3, 3) @[lsu_bus_buffer.scala 412:100] + node _T_2702 = eq(_T_2701, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:89] + node _T_2703 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 412:119] + node _T_2704 = and(_T_2702, _T_2703) @[lsu_bus_buffer.scala 412:104] + node _T_2705 = mux(_T_2700, UInt<1>("h00"), _T_2704) @[lsu_bus_buffer.scala 412:72] + node _T_2706 = cat(_T_2705, _T_2699) @[Cat.scala 29:58] + node _T_2707 = cat(_T_2706, _T_2693) @[Cat.scala 29:58] + node _T_2708 = cat(_T_2707, _T_2687) @[Cat.scala 29:58] + node _T_2709 = eq(UInt<2>("h03"), UInt<1>("h00")) @[lsu_bus_buffer.scala 412:76] + node _T_2710 = bits(buf_age[3], 0, 0) @[lsu_bus_buffer.scala 412:100] + node _T_2711 = eq(_T_2710, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:89] + node _T_2712 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 412:119] + node _T_2713 = and(_T_2711, _T_2712) @[lsu_bus_buffer.scala 412:104] + node _T_2714 = mux(_T_2709, UInt<1>("h00"), _T_2713) @[lsu_bus_buffer.scala 412:72] + node _T_2715 = eq(UInt<2>("h03"), UInt<1>("h01")) @[lsu_bus_buffer.scala 412:76] + node _T_2716 = bits(buf_age[3], 1, 1) @[lsu_bus_buffer.scala 412:100] + node _T_2717 = eq(_T_2716, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:89] + node _T_2718 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 412:119] + node _T_2719 = and(_T_2717, _T_2718) @[lsu_bus_buffer.scala 412:104] + node _T_2720 = mux(_T_2715, UInt<1>("h00"), _T_2719) @[lsu_bus_buffer.scala 412:72] + node _T_2721 = eq(UInt<2>("h03"), UInt<2>("h02")) @[lsu_bus_buffer.scala 412:76] + node _T_2722 = bits(buf_age[3], 2, 2) @[lsu_bus_buffer.scala 412:100] + node _T_2723 = eq(_T_2722, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:89] + node _T_2724 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 412:119] + node _T_2725 = and(_T_2723, _T_2724) @[lsu_bus_buffer.scala 412:104] + node _T_2726 = mux(_T_2721, UInt<1>("h00"), _T_2725) @[lsu_bus_buffer.scala 412:72] + node _T_2727 = eq(UInt<2>("h03"), UInt<2>("h03")) @[lsu_bus_buffer.scala 412:76] + node _T_2728 = bits(buf_age[3], 3, 3) @[lsu_bus_buffer.scala 412:100] + node _T_2729 = eq(_T_2728, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:89] + node _T_2730 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 412:119] + node _T_2731 = and(_T_2729, _T_2730) @[lsu_bus_buffer.scala 412:104] + node _T_2732 = mux(_T_2727, UInt<1>("h00"), _T_2731) @[lsu_bus_buffer.scala 412:72] + node _T_2733 = cat(_T_2732, _T_2726) @[Cat.scala 29:58] + node _T_2734 = cat(_T_2733, _T_2720) @[Cat.scala 29:58] + node _T_2735 = cat(_T_2734, _T_2714) @[Cat.scala 29:58] + buf_age_younger[0] <= _T_2654 @[lsu_bus_buffer.scala 412:19] + buf_age_younger[1] <= _T_2681 @[lsu_bus_buffer.scala 412:19] + buf_age_younger[2] <= _T_2708 @[lsu_bus_buffer.scala 412:19] + buf_age_younger[3] <= _T_2735 @[lsu_bus_buffer.scala 412:19] + node _T_2736 = bits(buf_rspageQ[0], 0, 0) @[lsu_bus_buffer.scala 413:83] + node _T_2737 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 413:102] + node _T_2738 = and(_T_2736, _T_2737) @[lsu_bus_buffer.scala 413:87] + node _T_2739 = bits(buf_rspageQ[0], 1, 1) @[lsu_bus_buffer.scala 413:83] + node _T_2740 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 413:102] + node _T_2741 = and(_T_2739, _T_2740) @[lsu_bus_buffer.scala 413:87] + node _T_2742 = bits(buf_rspageQ[0], 2, 2) @[lsu_bus_buffer.scala 413:83] + node _T_2743 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 413:102] + node _T_2744 = and(_T_2742, _T_2743) @[lsu_bus_buffer.scala 413:87] + node _T_2745 = bits(buf_rspageQ[0], 3, 3) @[lsu_bus_buffer.scala 413:83] + node _T_2746 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 413:102] + node _T_2747 = and(_T_2745, _T_2746) @[lsu_bus_buffer.scala 413:87] + node _T_2748 = cat(_T_2747, _T_2744) @[Cat.scala 29:58] + node _T_2749 = cat(_T_2748, _T_2741) @[Cat.scala 29:58] + node _T_2750 = cat(_T_2749, _T_2738) @[Cat.scala 29:58] + node _T_2751 = bits(buf_rspageQ[1], 0, 0) @[lsu_bus_buffer.scala 413:83] + node _T_2752 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 413:102] + node _T_2753 = and(_T_2751, _T_2752) @[lsu_bus_buffer.scala 413:87] + node _T_2754 = bits(buf_rspageQ[1], 1, 1) @[lsu_bus_buffer.scala 413:83] + node _T_2755 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 413:102] + node _T_2756 = and(_T_2754, _T_2755) @[lsu_bus_buffer.scala 413:87] + node _T_2757 = bits(buf_rspageQ[1], 2, 2) @[lsu_bus_buffer.scala 413:83] + node _T_2758 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 413:102] + node _T_2759 = and(_T_2757, _T_2758) @[lsu_bus_buffer.scala 413:87] + node _T_2760 = bits(buf_rspageQ[1], 3, 3) @[lsu_bus_buffer.scala 413:83] + node _T_2761 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 413:102] + node _T_2762 = and(_T_2760, _T_2761) @[lsu_bus_buffer.scala 413:87] + node _T_2763 = cat(_T_2762, _T_2759) @[Cat.scala 29:58] + node _T_2764 = cat(_T_2763, _T_2756) @[Cat.scala 29:58] + node _T_2765 = cat(_T_2764, _T_2753) @[Cat.scala 29:58] + node _T_2766 = bits(buf_rspageQ[2], 0, 0) @[lsu_bus_buffer.scala 413:83] + node _T_2767 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 413:102] + node _T_2768 = and(_T_2766, _T_2767) @[lsu_bus_buffer.scala 413:87] + node _T_2769 = bits(buf_rspageQ[2], 1, 1) @[lsu_bus_buffer.scala 413:83] + node _T_2770 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 413:102] + node _T_2771 = and(_T_2769, _T_2770) @[lsu_bus_buffer.scala 413:87] + node _T_2772 = bits(buf_rspageQ[2], 2, 2) @[lsu_bus_buffer.scala 413:83] + node _T_2773 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 413:102] + node _T_2774 = and(_T_2772, _T_2773) @[lsu_bus_buffer.scala 413:87] + node _T_2775 = bits(buf_rspageQ[2], 3, 3) @[lsu_bus_buffer.scala 413:83] + node _T_2776 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 413:102] + node _T_2777 = and(_T_2775, _T_2776) @[lsu_bus_buffer.scala 413:87] + node _T_2778 = cat(_T_2777, _T_2774) @[Cat.scala 29:58] + node _T_2779 = cat(_T_2778, _T_2771) @[Cat.scala 29:58] + node _T_2780 = cat(_T_2779, _T_2768) @[Cat.scala 29:58] + node _T_2781 = bits(buf_rspageQ[3], 0, 0) @[lsu_bus_buffer.scala 413:83] + node _T_2782 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 413:102] + node _T_2783 = and(_T_2781, _T_2782) @[lsu_bus_buffer.scala 413:87] + node _T_2784 = bits(buf_rspageQ[3], 1, 1) @[lsu_bus_buffer.scala 413:83] + node _T_2785 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 413:102] + node _T_2786 = and(_T_2784, _T_2785) @[lsu_bus_buffer.scala 413:87] + node _T_2787 = bits(buf_rspageQ[3], 2, 2) @[lsu_bus_buffer.scala 413:83] + node _T_2788 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 413:102] + node _T_2789 = and(_T_2787, _T_2788) @[lsu_bus_buffer.scala 413:87] + node _T_2790 = bits(buf_rspageQ[3], 3, 3) @[lsu_bus_buffer.scala 413:83] + node _T_2791 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 413:102] + node _T_2792 = and(_T_2790, _T_2791) @[lsu_bus_buffer.scala 413:87] + node _T_2793 = cat(_T_2792, _T_2789) @[Cat.scala 29:58] + node _T_2794 = cat(_T_2793, _T_2786) @[Cat.scala 29:58] + node _T_2795 = cat(_T_2794, _T_2783) @[Cat.scala 29:58] + buf_rsp_pickage[0] <= _T_2750 @[lsu_bus_buffer.scala 413:19] + buf_rsp_pickage[1] <= _T_2765 @[lsu_bus_buffer.scala 413:19] + buf_rsp_pickage[2] <= _T_2780 @[lsu_bus_buffer.scala 413:19] + buf_rsp_pickage[3] <= _T_2795 @[lsu_bus_buffer.scala 413:19] + node _T_2796 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 415:82] + node _T_2797 = and(_T_2796, buf_state_en[0]) @[lsu_bus_buffer.scala 415:93] + node _T_2798 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:21] + node _T_2799 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 416:47] + node _T_2800 = or(_T_2798, _T_2799) @[lsu_bus_buffer.scala 416:32] + node _T_2801 = eq(_T_2800, UInt<1>("h00")) @[lsu_bus_buffer.scala 416:6] + node _T_2802 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 417:23] + node _T_2803 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 417:53] + node _T_2804 = and(_T_2802, _T_2803) @[lsu_bus_buffer.scala 417:41] + node _T_2805 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:82] + node _T_2806 = and(_T_2804, _T_2805) @[lsu_bus_buffer.scala 417:71] + node _T_2807 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:101] + node _T_2808 = and(_T_2806, _T_2807) @[lsu_bus_buffer.scala 417:90] + node _T_2809 = or(_T_2801, _T_2808) @[lsu_bus_buffer.scala 416:59] + node _T_2810 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:17] + node _T_2811 = and(_T_2810, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:35] + node _T_2812 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:63] + node _T_2813 = and(_T_2811, _T_2812) @[lsu_bus_buffer.scala 418:52] + node _T_2814 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:82] + node _T_2815 = and(_T_2813, _T_2814) @[lsu_bus_buffer.scala 418:71] + node _T_2816 = or(_T_2809, _T_2815) @[lsu_bus_buffer.scala 417:110] + node _T_2817 = and(_T_2797, _T_2816) @[lsu_bus_buffer.scala 415:112] + node _T_2818 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 415:82] + node _T_2819 = and(_T_2818, buf_state_en[0]) @[lsu_bus_buffer.scala 415:93] + node _T_2820 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:21] + node _T_2821 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 416:47] + node _T_2822 = or(_T_2820, _T_2821) @[lsu_bus_buffer.scala 416:32] + node _T_2823 = eq(_T_2822, UInt<1>("h00")) @[lsu_bus_buffer.scala 416:6] + node _T_2824 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 417:23] + node _T_2825 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 417:53] + node _T_2826 = and(_T_2824, _T_2825) @[lsu_bus_buffer.scala 417:41] + node _T_2827 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:82] + node _T_2828 = and(_T_2826, _T_2827) @[lsu_bus_buffer.scala 417:71] + node _T_2829 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 417:101] + node _T_2830 = and(_T_2828, _T_2829) @[lsu_bus_buffer.scala 417:90] + node _T_2831 = or(_T_2823, _T_2830) @[lsu_bus_buffer.scala 416:59] + node _T_2832 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:17] + node _T_2833 = and(_T_2832, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:35] + node _T_2834 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:63] + node _T_2835 = and(_T_2833, _T_2834) @[lsu_bus_buffer.scala 418:52] + node _T_2836 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 418:82] + node _T_2837 = and(_T_2835, _T_2836) @[lsu_bus_buffer.scala 418:71] + node _T_2838 = or(_T_2831, _T_2837) @[lsu_bus_buffer.scala 417:110] + node _T_2839 = and(_T_2819, _T_2838) @[lsu_bus_buffer.scala 415:112] + node _T_2840 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 415:82] + node _T_2841 = and(_T_2840, buf_state_en[0]) @[lsu_bus_buffer.scala 415:93] + node _T_2842 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:21] + node _T_2843 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 416:47] + node _T_2844 = or(_T_2842, _T_2843) @[lsu_bus_buffer.scala 416:32] + node _T_2845 = eq(_T_2844, UInt<1>("h00")) @[lsu_bus_buffer.scala 416:6] + node _T_2846 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 417:23] + node _T_2847 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 417:53] + node _T_2848 = and(_T_2846, _T_2847) @[lsu_bus_buffer.scala 417:41] + node _T_2849 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:82] + node _T_2850 = and(_T_2848, _T_2849) @[lsu_bus_buffer.scala 417:71] + node _T_2851 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 417:101] + node _T_2852 = and(_T_2850, _T_2851) @[lsu_bus_buffer.scala 417:90] + node _T_2853 = or(_T_2845, _T_2852) @[lsu_bus_buffer.scala 416:59] + node _T_2854 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:17] + node _T_2855 = and(_T_2854, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:35] + node _T_2856 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:63] + node _T_2857 = and(_T_2855, _T_2856) @[lsu_bus_buffer.scala 418:52] + node _T_2858 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 418:82] + node _T_2859 = and(_T_2857, _T_2858) @[lsu_bus_buffer.scala 418:71] + node _T_2860 = or(_T_2853, _T_2859) @[lsu_bus_buffer.scala 417:110] + node _T_2861 = and(_T_2841, _T_2860) @[lsu_bus_buffer.scala 415:112] + node _T_2862 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 415:82] + node _T_2863 = and(_T_2862, buf_state_en[0]) @[lsu_bus_buffer.scala 415:93] + node _T_2864 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:21] + node _T_2865 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 416:47] + node _T_2866 = or(_T_2864, _T_2865) @[lsu_bus_buffer.scala 416:32] + node _T_2867 = eq(_T_2866, UInt<1>("h00")) @[lsu_bus_buffer.scala 416:6] + node _T_2868 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 417:23] + node _T_2869 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 417:53] + node _T_2870 = and(_T_2868, _T_2869) @[lsu_bus_buffer.scala 417:41] + node _T_2871 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:82] + node _T_2872 = and(_T_2870, _T_2871) @[lsu_bus_buffer.scala 417:71] + node _T_2873 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 417:101] + node _T_2874 = and(_T_2872, _T_2873) @[lsu_bus_buffer.scala 417:90] + node _T_2875 = or(_T_2867, _T_2874) @[lsu_bus_buffer.scala 416:59] + node _T_2876 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:17] + node _T_2877 = and(_T_2876, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:35] + node _T_2878 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:63] + node _T_2879 = and(_T_2877, _T_2878) @[lsu_bus_buffer.scala 418:52] + node _T_2880 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 418:82] + node _T_2881 = and(_T_2879, _T_2880) @[lsu_bus_buffer.scala 418:71] + node _T_2882 = or(_T_2875, _T_2881) @[lsu_bus_buffer.scala 417:110] + node _T_2883 = and(_T_2863, _T_2882) @[lsu_bus_buffer.scala 415:112] + node _T_2884 = cat(_T_2883, _T_2861) @[Cat.scala 29:58] + node _T_2885 = cat(_T_2884, _T_2839) @[Cat.scala 29:58] + node _T_2886 = cat(_T_2885, _T_2817) @[Cat.scala 29:58] + node _T_2887 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 415:82] + node _T_2888 = and(_T_2887, buf_state_en[1]) @[lsu_bus_buffer.scala 415:93] + node _T_2889 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:21] + node _T_2890 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 416:47] + node _T_2891 = or(_T_2889, _T_2890) @[lsu_bus_buffer.scala 416:32] + node _T_2892 = eq(_T_2891, UInt<1>("h00")) @[lsu_bus_buffer.scala 416:6] + node _T_2893 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 417:23] + node _T_2894 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 417:53] + node _T_2895 = and(_T_2893, _T_2894) @[lsu_bus_buffer.scala 417:41] + node _T_2896 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 417:82] + node _T_2897 = and(_T_2895, _T_2896) @[lsu_bus_buffer.scala 417:71] + node _T_2898 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:101] + node _T_2899 = and(_T_2897, _T_2898) @[lsu_bus_buffer.scala 417:90] + node _T_2900 = or(_T_2892, _T_2899) @[lsu_bus_buffer.scala 416:59] + node _T_2901 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:17] + node _T_2902 = and(_T_2901, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:35] + node _T_2903 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 418:63] + node _T_2904 = and(_T_2902, _T_2903) @[lsu_bus_buffer.scala 418:52] + node _T_2905 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:82] + node _T_2906 = and(_T_2904, _T_2905) @[lsu_bus_buffer.scala 418:71] + node _T_2907 = or(_T_2900, _T_2906) @[lsu_bus_buffer.scala 417:110] + node _T_2908 = and(_T_2888, _T_2907) @[lsu_bus_buffer.scala 415:112] + node _T_2909 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 415:82] + node _T_2910 = and(_T_2909, buf_state_en[1]) @[lsu_bus_buffer.scala 415:93] + node _T_2911 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:21] + node _T_2912 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 416:47] + node _T_2913 = or(_T_2911, _T_2912) @[lsu_bus_buffer.scala 416:32] + node _T_2914 = eq(_T_2913, UInt<1>("h00")) @[lsu_bus_buffer.scala 416:6] + node _T_2915 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 417:23] + node _T_2916 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 417:53] + node _T_2917 = and(_T_2915, _T_2916) @[lsu_bus_buffer.scala 417:41] + node _T_2918 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 417:82] + node _T_2919 = and(_T_2917, _T_2918) @[lsu_bus_buffer.scala 417:71] + node _T_2920 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 417:101] + node _T_2921 = and(_T_2919, _T_2920) @[lsu_bus_buffer.scala 417:90] + node _T_2922 = or(_T_2914, _T_2921) @[lsu_bus_buffer.scala 416:59] + node _T_2923 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:17] + node _T_2924 = and(_T_2923, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:35] + node _T_2925 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 418:63] + node _T_2926 = and(_T_2924, _T_2925) @[lsu_bus_buffer.scala 418:52] + node _T_2927 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 418:82] + node _T_2928 = and(_T_2926, _T_2927) @[lsu_bus_buffer.scala 418:71] + node _T_2929 = or(_T_2922, _T_2928) @[lsu_bus_buffer.scala 417:110] + node _T_2930 = and(_T_2910, _T_2929) @[lsu_bus_buffer.scala 415:112] + node _T_2931 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 415:82] + node _T_2932 = and(_T_2931, buf_state_en[1]) @[lsu_bus_buffer.scala 415:93] + node _T_2933 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:21] + node _T_2934 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 416:47] + node _T_2935 = or(_T_2933, _T_2934) @[lsu_bus_buffer.scala 416:32] + node _T_2936 = eq(_T_2935, UInt<1>("h00")) @[lsu_bus_buffer.scala 416:6] + node _T_2937 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 417:23] + node _T_2938 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 417:53] + node _T_2939 = and(_T_2937, _T_2938) @[lsu_bus_buffer.scala 417:41] + node _T_2940 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 417:82] + node _T_2941 = and(_T_2939, _T_2940) @[lsu_bus_buffer.scala 417:71] + node _T_2942 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 417:101] + node _T_2943 = and(_T_2941, _T_2942) @[lsu_bus_buffer.scala 417:90] + node _T_2944 = or(_T_2936, _T_2943) @[lsu_bus_buffer.scala 416:59] + node _T_2945 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:17] + node _T_2946 = and(_T_2945, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:35] + node _T_2947 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 418:63] + node _T_2948 = and(_T_2946, _T_2947) @[lsu_bus_buffer.scala 418:52] + node _T_2949 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 418:82] + node _T_2950 = and(_T_2948, _T_2949) @[lsu_bus_buffer.scala 418:71] + node _T_2951 = or(_T_2944, _T_2950) @[lsu_bus_buffer.scala 417:110] + node _T_2952 = and(_T_2932, _T_2951) @[lsu_bus_buffer.scala 415:112] + node _T_2953 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 415:82] + node _T_2954 = and(_T_2953, buf_state_en[1]) @[lsu_bus_buffer.scala 415:93] + node _T_2955 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:21] + node _T_2956 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 416:47] + node _T_2957 = or(_T_2955, _T_2956) @[lsu_bus_buffer.scala 416:32] + node _T_2958 = eq(_T_2957, UInt<1>("h00")) @[lsu_bus_buffer.scala 416:6] + node _T_2959 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 417:23] + node _T_2960 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 417:53] + node _T_2961 = and(_T_2959, _T_2960) @[lsu_bus_buffer.scala 417:41] + node _T_2962 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 417:82] + node _T_2963 = and(_T_2961, _T_2962) @[lsu_bus_buffer.scala 417:71] + node _T_2964 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 417:101] + node _T_2965 = and(_T_2963, _T_2964) @[lsu_bus_buffer.scala 417:90] + node _T_2966 = or(_T_2958, _T_2965) @[lsu_bus_buffer.scala 416:59] + node _T_2967 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:17] + node _T_2968 = and(_T_2967, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:35] + node _T_2969 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 418:63] + node _T_2970 = and(_T_2968, _T_2969) @[lsu_bus_buffer.scala 418:52] + node _T_2971 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 418:82] + node _T_2972 = and(_T_2970, _T_2971) @[lsu_bus_buffer.scala 418:71] + node _T_2973 = or(_T_2966, _T_2972) @[lsu_bus_buffer.scala 417:110] + node _T_2974 = and(_T_2954, _T_2973) @[lsu_bus_buffer.scala 415:112] + node _T_2975 = cat(_T_2974, _T_2952) @[Cat.scala 29:58] + node _T_2976 = cat(_T_2975, _T_2930) @[Cat.scala 29:58] + node _T_2977 = cat(_T_2976, _T_2908) @[Cat.scala 29:58] + node _T_2978 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 415:82] + node _T_2979 = and(_T_2978, buf_state_en[2]) @[lsu_bus_buffer.scala 415:93] + node _T_2980 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:21] + node _T_2981 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 416:47] + node _T_2982 = or(_T_2980, _T_2981) @[lsu_bus_buffer.scala 416:32] + node _T_2983 = eq(_T_2982, UInt<1>("h00")) @[lsu_bus_buffer.scala 416:6] + node _T_2984 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 417:23] + node _T_2985 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 417:53] + node _T_2986 = and(_T_2984, _T_2985) @[lsu_bus_buffer.scala 417:41] + node _T_2987 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 417:82] + node _T_2988 = and(_T_2986, _T_2987) @[lsu_bus_buffer.scala 417:71] + node _T_2989 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:101] + node _T_2990 = and(_T_2988, _T_2989) @[lsu_bus_buffer.scala 417:90] + node _T_2991 = or(_T_2983, _T_2990) @[lsu_bus_buffer.scala 416:59] + node _T_2992 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:17] + node _T_2993 = and(_T_2992, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:35] + node _T_2994 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 418:63] + node _T_2995 = and(_T_2993, _T_2994) @[lsu_bus_buffer.scala 418:52] + node _T_2996 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:82] + node _T_2997 = and(_T_2995, _T_2996) @[lsu_bus_buffer.scala 418:71] + node _T_2998 = or(_T_2991, _T_2997) @[lsu_bus_buffer.scala 417:110] + node _T_2999 = and(_T_2979, _T_2998) @[lsu_bus_buffer.scala 415:112] + node _T_3000 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 415:82] + node _T_3001 = and(_T_3000, buf_state_en[2]) @[lsu_bus_buffer.scala 415:93] + node _T_3002 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:21] + node _T_3003 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 416:47] + node _T_3004 = or(_T_3002, _T_3003) @[lsu_bus_buffer.scala 416:32] + node _T_3005 = eq(_T_3004, UInt<1>("h00")) @[lsu_bus_buffer.scala 416:6] + node _T_3006 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 417:23] + node _T_3007 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 417:53] + node _T_3008 = and(_T_3006, _T_3007) @[lsu_bus_buffer.scala 417:41] + node _T_3009 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 417:82] + node _T_3010 = and(_T_3008, _T_3009) @[lsu_bus_buffer.scala 417:71] + node _T_3011 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 417:101] + node _T_3012 = and(_T_3010, _T_3011) @[lsu_bus_buffer.scala 417:90] + node _T_3013 = or(_T_3005, _T_3012) @[lsu_bus_buffer.scala 416:59] + node _T_3014 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:17] + node _T_3015 = and(_T_3014, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:35] + node _T_3016 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 418:63] + node _T_3017 = and(_T_3015, _T_3016) @[lsu_bus_buffer.scala 418:52] + node _T_3018 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 418:82] + node _T_3019 = and(_T_3017, _T_3018) @[lsu_bus_buffer.scala 418:71] + node _T_3020 = or(_T_3013, _T_3019) @[lsu_bus_buffer.scala 417:110] + node _T_3021 = and(_T_3001, _T_3020) @[lsu_bus_buffer.scala 415:112] + node _T_3022 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 415:82] + node _T_3023 = and(_T_3022, buf_state_en[2]) @[lsu_bus_buffer.scala 415:93] + node _T_3024 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:21] + node _T_3025 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 416:47] + node _T_3026 = or(_T_3024, _T_3025) @[lsu_bus_buffer.scala 416:32] + node _T_3027 = eq(_T_3026, UInt<1>("h00")) @[lsu_bus_buffer.scala 416:6] + node _T_3028 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 417:23] + node _T_3029 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 417:53] + node _T_3030 = and(_T_3028, _T_3029) @[lsu_bus_buffer.scala 417:41] + node _T_3031 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 417:82] + node _T_3032 = and(_T_3030, _T_3031) @[lsu_bus_buffer.scala 417:71] + node _T_3033 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 417:101] + node _T_3034 = and(_T_3032, _T_3033) @[lsu_bus_buffer.scala 417:90] + node _T_3035 = or(_T_3027, _T_3034) @[lsu_bus_buffer.scala 416:59] + node _T_3036 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:17] + node _T_3037 = and(_T_3036, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:35] + node _T_3038 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 418:63] + node _T_3039 = and(_T_3037, _T_3038) @[lsu_bus_buffer.scala 418:52] + node _T_3040 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 418:82] + node _T_3041 = and(_T_3039, _T_3040) @[lsu_bus_buffer.scala 418:71] + node _T_3042 = or(_T_3035, _T_3041) @[lsu_bus_buffer.scala 417:110] + node _T_3043 = and(_T_3023, _T_3042) @[lsu_bus_buffer.scala 415:112] + node _T_3044 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 415:82] + node _T_3045 = and(_T_3044, buf_state_en[2]) @[lsu_bus_buffer.scala 415:93] + node _T_3046 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:21] + node _T_3047 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 416:47] + node _T_3048 = or(_T_3046, _T_3047) @[lsu_bus_buffer.scala 416:32] + node _T_3049 = eq(_T_3048, UInt<1>("h00")) @[lsu_bus_buffer.scala 416:6] + node _T_3050 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 417:23] + node _T_3051 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 417:53] + node _T_3052 = and(_T_3050, _T_3051) @[lsu_bus_buffer.scala 417:41] + node _T_3053 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 417:82] + node _T_3054 = and(_T_3052, _T_3053) @[lsu_bus_buffer.scala 417:71] + node _T_3055 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 417:101] + node _T_3056 = and(_T_3054, _T_3055) @[lsu_bus_buffer.scala 417:90] + node _T_3057 = or(_T_3049, _T_3056) @[lsu_bus_buffer.scala 416:59] + node _T_3058 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:17] + node _T_3059 = and(_T_3058, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:35] + node _T_3060 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 418:63] + node _T_3061 = and(_T_3059, _T_3060) @[lsu_bus_buffer.scala 418:52] + node _T_3062 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 418:82] + node _T_3063 = and(_T_3061, _T_3062) @[lsu_bus_buffer.scala 418:71] + node _T_3064 = or(_T_3057, _T_3063) @[lsu_bus_buffer.scala 417:110] + node _T_3065 = and(_T_3045, _T_3064) @[lsu_bus_buffer.scala 415:112] + node _T_3066 = cat(_T_3065, _T_3043) @[Cat.scala 29:58] + node _T_3067 = cat(_T_3066, _T_3021) @[Cat.scala 29:58] + node _T_3068 = cat(_T_3067, _T_2999) @[Cat.scala 29:58] + node _T_3069 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 415:82] + node _T_3070 = and(_T_3069, buf_state_en[3]) @[lsu_bus_buffer.scala 415:93] + node _T_3071 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:21] + node _T_3072 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 416:47] + node _T_3073 = or(_T_3071, _T_3072) @[lsu_bus_buffer.scala 416:32] + node _T_3074 = eq(_T_3073, UInt<1>("h00")) @[lsu_bus_buffer.scala 416:6] + node _T_3075 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 417:23] + node _T_3076 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 417:53] + node _T_3077 = and(_T_3075, _T_3076) @[lsu_bus_buffer.scala 417:41] + node _T_3078 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 417:82] + node _T_3079 = and(_T_3077, _T_3078) @[lsu_bus_buffer.scala 417:71] + node _T_3080 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:101] + node _T_3081 = and(_T_3079, _T_3080) @[lsu_bus_buffer.scala 417:90] + node _T_3082 = or(_T_3074, _T_3081) @[lsu_bus_buffer.scala 416:59] + node _T_3083 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:17] + node _T_3084 = and(_T_3083, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:35] + node _T_3085 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 418:63] + node _T_3086 = and(_T_3084, _T_3085) @[lsu_bus_buffer.scala 418:52] + node _T_3087 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:82] + node _T_3088 = and(_T_3086, _T_3087) @[lsu_bus_buffer.scala 418:71] + node _T_3089 = or(_T_3082, _T_3088) @[lsu_bus_buffer.scala 417:110] + node _T_3090 = and(_T_3070, _T_3089) @[lsu_bus_buffer.scala 415:112] + node _T_3091 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 415:82] + node _T_3092 = and(_T_3091, buf_state_en[3]) @[lsu_bus_buffer.scala 415:93] + node _T_3093 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:21] + node _T_3094 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 416:47] + node _T_3095 = or(_T_3093, _T_3094) @[lsu_bus_buffer.scala 416:32] + node _T_3096 = eq(_T_3095, UInt<1>("h00")) @[lsu_bus_buffer.scala 416:6] + node _T_3097 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 417:23] + node _T_3098 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 417:53] + node _T_3099 = and(_T_3097, _T_3098) @[lsu_bus_buffer.scala 417:41] + node _T_3100 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 417:82] + node _T_3101 = and(_T_3099, _T_3100) @[lsu_bus_buffer.scala 417:71] + node _T_3102 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 417:101] + node _T_3103 = and(_T_3101, _T_3102) @[lsu_bus_buffer.scala 417:90] + node _T_3104 = or(_T_3096, _T_3103) @[lsu_bus_buffer.scala 416:59] + node _T_3105 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:17] + node _T_3106 = and(_T_3105, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:35] + node _T_3107 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 418:63] + node _T_3108 = and(_T_3106, _T_3107) @[lsu_bus_buffer.scala 418:52] + node _T_3109 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 418:82] + node _T_3110 = and(_T_3108, _T_3109) @[lsu_bus_buffer.scala 418:71] + node _T_3111 = or(_T_3104, _T_3110) @[lsu_bus_buffer.scala 417:110] + node _T_3112 = and(_T_3092, _T_3111) @[lsu_bus_buffer.scala 415:112] + node _T_3113 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 415:82] + node _T_3114 = and(_T_3113, buf_state_en[3]) @[lsu_bus_buffer.scala 415:93] + node _T_3115 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:21] + node _T_3116 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 416:47] + node _T_3117 = or(_T_3115, _T_3116) @[lsu_bus_buffer.scala 416:32] + node _T_3118 = eq(_T_3117, UInt<1>("h00")) @[lsu_bus_buffer.scala 416:6] + node _T_3119 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 417:23] + node _T_3120 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 417:53] + node _T_3121 = and(_T_3119, _T_3120) @[lsu_bus_buffer.scala 417:41] + node _T_3122 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 417:82] + node _T_3123 = and(_T_3121, _T_3122) @[lsu_bus_buffer.scala 417:71] + node _T_3124 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 417:101] + node _T_3125 = and(_T_3123, _T_3124) @[lsu_bus_buffer.scala 417:90] + node _T_3126 = or(_T_3118, _T_3125) @[lsu_bus_buffer.scala 416:59] + node _T_3127 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:17] + node _T_3128 = and(_T_3127, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:35] + node _T_3129 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 418:63] + node _T_3130 = and(_T_3128, _T_3129) @[lsu_bus_buffer.scala 418:52] + node _T_3131 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 418:82] + node _T_3132 = and(_T_3130, _T_3131) @[lsu_bus_buffer.scala 418:71] + node _T_3133 = or(_T_3126, _T_3132) @[lsu_bus_buffer.scala 417:110] + node _T_3134 = and(_T_3114, _T_3133) @[lsu_bus_buffer.scala 415:112] + node _T_3135 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 415:82] + node _T_3136 = and(_T_3135, buf_state_en[3]) @[lsu_bus_buffer.scala 415:93] + node _T_3137 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:21] + node _T_3138 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 416:47] + node _T_3139 = or(_T_3137, _T_3138) @[lsu_bus_buffer.scala 416:32] + node _T_3140 = eq(_T_3139, UInt<1>("h00")) @[lsu_bus_buffer.scala 416:6] + node _T_3141 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 417:23] + node _T_3142 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 417:53] + node _T_3143 = and(_T_3141, _T_3142) @[lsu_bus_buffer.scala 417:41] + node _T_3144 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 417:82] + node _T_3145 = and(_T_3143, _T_3144) @[lsu_bus_buffer.scala 417:71] + node _T_3146 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 417:101] + node _T_3147 = and(_T_3145, _T_3146) @[lsu_bus_buffer.scala 417:90] + node _T_3148 = or(_T_3140, _T_3147) @[lsu_bus_buffer.scala 416:59] + node _T_3149 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:17] + node _T_3150 = and(_T_3149, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:35] + node _T_3151 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 418:63] + node _T_3152 = and(_T_3150, _T_3151) @[lsu_bus_buffer.scala 418:52] + node _T_3153 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 418:82] + node _T_3154 = and(_T_3152, _T_3153) @[lsu_bus_buffer.scala 418:71] + node _T_3155 = or(_T_3148, _T_3154) @[lsu_bus_buffer.scala 417:110] + node _T_3156 = and(_T_3136, _T_3155) @[lsu_bus_buffer.scala 415:112] + node _T_3157 = cat(_T_3156, _T_3134) @[Cat.scala 29:58] + node _T_3158 = cat(_T_3157, _T_3112) @[Cat.scala 29:58] + node _T_3159 = cat(_T_3158, _T_3090) @[Cat.scala 29:58] + buf_rspage_set[0] <= _T_2886 @[lsu_bus_buffer.scala 415:18] + buf_rspage_set[1] <= _T_2977 @[lsu_bus_buffer.scala 415:18] + buf_rspage_set[2] <= _T_3068 @[lsu_bus_buffer.scala 415:18] + buf_rspage_set[3] <= _T_3159 @[lsu_bus_buffer.scala 415:18] + node _T_3160 = bits(buf_rspage_set[0], 0, 0) @[lsu_bus_buffer.scala 419:84] + node _T_3161 = bits(buf_rspage[0], 0, 0) @[lsu_bus_buffer.scala 419:103] + node _T_3162 = or(_T_3160, _T_3161) @[lsu_bus_buffer.scala 419:88] + node _T_3163 = bits(buf_rspage_set[0], 1, 1) @[lsu_bus_buffer.scala 419:84] + node _T_3164 = bits(buf_rspage[0], 1, 1) @[lsu_bus_buffer.scala 419:103] + node _T_3165 = or(_T_3163, _T_3164) @[lsu_bus_buffer.scala 419:88] + node _T_3166 = bits(buf_rspage_set[0], 2, 2) @[lsu_bus_buffer.scala 419:84] + node _T_3167 = bits(buf_rspage[0], 2, 2) @[lsu_bus_buffer.scala 419:103] + node _T_3168 = or(_T_3166, _T_3167) @[lsu_bus_buffer.scala 419:88] + node _T_3169 = bits(buf_rspage_set[0], 3, 3) @[lsu_bus_buffer.scala 419:84] + node _T_3170 = bits(buf_rspage[0], 3, 3) @[lsu_bus_buffer.scala 419:103] + node _T_3171 = or(_T_3169, _T_3170) @[lsu_bus_buffer.scala 419:88] + node _T_3172 = cat(_T_3171, _T_3168) @[Cat.scala 29:58] + node _T_3173 = cat(_T_3172, _T_3165) @[Cat.scala 29:58] + node _T_3174 = cat(_T_3173, _T_3162) @[Cat.scala 29:58] + node _T_3175 = bits(buf_rspage_set[1], 0, 0) @[lsu_bus_buffer.scala 419:84] + node _T_3176 = bits(buf_rspage[1], 0, 0) @[lsu_bus_buffer.scala 419:103] + node _T_3177 = or(_T_3175, _T_3176) @[lsu_bus_buffer.scala 419:88] + node _T_3178 = bits(buf_rspage_set[1], 1, 1) @[lsu_bus_buffer.scala 419:84] + node _T_3179 = bits(buf_rspage[1], 1, 1) @[lsu_bus_buffer.scala 419:103] + node _T_3180 = or(_T_3178, _T_3179) @[lsu_bus_buffer.scala 419:88] + node _T_3181 = bits(buf_rspage_set[1], 2, 2) @[lsu_bus_buffer.scala 419:84] + node _T_3182 = bits(buf_rspage[1], 2, 2) @[lsu_bus_buffer.scala 419:103] + node _T_3183 = or(_T_3181, _T_3182) @[lsu_bus_buffer.scala 419:88] + node _T_3184 = bits(buf_rspage_set[1], 3, 3) @[lsu_bus_buffer.scala 419:84] + node _T_3185 = bits(buf_rspage[1], 3, 3) @[lsu_bus_buffer.scala 419:103] + node _T_3186 = or(_T_3184, _T_3185) @[lsu_bus_buffer.scala 419:88] + node _T_3187 = cat(_T_3186, _T_3183) @[Cat.scala 29:58] + node _T_3188 = cat(_T_3187, _T_3180) @[Cat.scala 29:58] + node _T_3189 = cat(_T_3188, _T_3177) @[Cat.scala 29:58] + node _T_3190 = bits(buf_rspage_set[2], 0, 0) @[lsu_bus_buffer.scala 419:84] + node _T_3191 = bits(buf_rspage[2], 0, 0) @[lsu_bus_buffer.scala 419:103] + node _T_3192 = or(_T_3190, _T_3191) @[lsu_bus_buffer.scala 419:88] + node _T_3193 = bits(buf_rspage_set[2], 1, 1) @[lsu_bus_buffer.scala 419:84] + node _T_3194 = bits(buf_rspage[2], 1, 1) @[lsu_bus_buffer.scala 419:103] + node _T_3195 = or(_T_3193, _T_3194) @[lsu_bus_buffer.scala 419:88] + node _T_3196 = bits(buf_rspage_set[2], 2, 2) @[lsu_bus_buffer.scala 419:84] + node _T_3197 = bits(buf_rspage[2], 2, 2) @[lsu_bus_buffer.scala 419:103] + node _T_3198 = or(_T_3196, _T_3197) @[lsu_bus_buffer.scala 419:88] + node _T_3199 = bits(buf_rspage_set[2], 3, 3) @[lsu_bus_buffer.scala 419:84] + node _T_3200 = bits(buf_rspage[2], 3, 3) @[lsu_bus_buffer.scala 419:103] + node _T_3201 = or(_T_3199, _T_3200) @[lsu_bus_buffer.scala 419:88] + node _T_3202 = cat(_T_3201, _T_3198) @[Cat.scala 29:58] + node _T_3203 = cat(_T_3202, _T_3195) @[Cat.scala 29:58] + node _T_3204 = cat(_T_3203, _T_3192) @[Cat.scala 29:58] + node _T_3205 = bits(buf_rspage_set[3], 0, 0) @[lsu_bus_buffer.scala 419:84] + node _T_3206 = bits(buf_rspage[3], 0, 0) @[lsu_bus_buffer.scala 419:103] + node _T_3207 = or(_T_3205, _T_3206) @[lsu_bus_buffer.scala 419:88] + node _T_3208 = bits(buf_rspage_set[3], 1, 1) @[lsu_bus_buffer.scala 419:84] + node _T_3209 = bits(buf_rspage[3], 1, 1) @[lsu_bus_buffer.scala 419:103] + node _T_3210 = or(_T_3208, _T_3209) @[lsu_bus_buffer.scala 419:88] + node _T_3211 = bits(buf_rspage_set[3], 2, 2) @[lsu_bus_buffer.scala 419:84] + node _T_3212 = bits(buf_rspage[3], 2, 2) @[lsu_bus_buffer.scala 419:103] + node _T_3213 = or(_T_3211, _T_3212) @[lsu_bus_buffer.scala 419:88] + node _T_3214 = bits(buf_rspage_set[3], 3, 3) @[lsu_bus_buffer.scala 419:84] + node _T_3215 = bits(buf_rspage[3], 3, 3) @[lsu_bus_buffer.scala 419:103] + node _T_3216 = or(_T_3214, _T_3215) @[lsu_bus_buffer.scala 419:88] + node _T_3217 = cat(_T_3216, _T_3213) @[Cat.scala 29:58] + node _T_3218 = cat(_T_3217, _T_3210) @[Cat.scala 29:58] + node _T_3219 = cat(_T_3218, _T_3207) @[Cat.scala 29:58] + buf_rspage_in[0] <= _T_3174 @[lsu_bus_buffer.scala 419:17] + buf_rspage_in[1] <= _T_3189 @[lsu_bus_buffer.scala 419:17] + buf_rspage_in[2] <= _T_3204 @[lsu_bus_buffer.scala 419:17] + buf_rspage_in[3] <= _T_3219 @[lsu_bus_buffer.scala 419:17] + node _T_3220 = bits(buf_rspageQ[0], 0, 0) @[lsu_bus_buffer.scala 420:78] + node _T_3221 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 420:99] + node _T_3222 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 420:125] + node _T_3223 = or(_T_3221, _T_3222) @[lsu_bus_buffer.scala 420:110] + node _T_3224 = eq(_T_3223, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:84] + node _T_3225 = and(_T_3220, _T_3224) @[lsu_bus_buffer.scala 420:82] + node _T_3226 = bits(buf_rspageQ[0], 1, 1) @[lsu_bus_buffer.scala 420:78] + node _T_3227 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 420:99] + node _T_3228 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 420:125] + node _T_3229 = or(_T_3227, _T_3228) @[lsu_bus_buffer.scala 420:110] + node _T_3230 = eq(_T_3229, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:84] + node _T_3231 = and(_T_3226, _T_3230) @[lsu_bus_buffer.scala 420:82] + node _T_3232 = bits(buf_rspageQ[0], 2, 2) @[lsu_bus_buffer.scala 420:78] + node _T_3233 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 420:99] + node _T_3234 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 420:125] + node _T_3235 = or(_T_3233, _T_3234) @[lsu_bus_buffer.scala 420:110] + node _T_3236 = eq(_T_3235, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:84] + node _T_3237 = and(_T_3232, _T_3236) @[lsu_bus_buffer.scala 420:82] + node _T_3238 = bits(buf_rspageQ[0], 3, 3) @[lsu_bus_buffer.scala 420:78] + node _T_3239 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 420:99] + node _T_3240 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 420:125] + node _T_3241 = or(_T_3239, _T_3240) @[lsu_bus_buffer.scala 420:110] + node _T_3242 = eq(_T_3241, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:84] + node _T_3243 = and(_T_3238, _T_3242) @[lsu_bus_buffer.scala 420:82] + node _T_3244 = cat(_T_3243, _T_3237) @[Cat.scala 29:58] + node _T_3245 = cat(_T_3244, _T_3231) @[Cat.scala 29:58] + node _T_3246 = cat(_T_3245, _T_3225) @[Cat.scala 29:58] + node _T_3247 = bits(buf_rspageQ[1], 0, 0) @[lsu_bus_buffer.scala 420:78] + node _T_3248 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 420:99] + node _T_3249 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 420:125] + node _T_3250 = or(_T_3248, _T_3249) @[lsu_bus_buffer.scala 420:110] + node _T_3251 = eq(_T_3250, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:84] + node _T_3252 = and(_T_3247, _T_3251) @[lsu_bus_buffer.scala 420:82] + node _T_3253 = bits(buf_rspageQ[1], 1, 1) @[lsu_bus_buffer.scala 420:78] + node _T_3254 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 420:99] + node _T_3255 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 420:125] + node _T_3256 = or(_T_3254, _T_3255) @[lsu_bus_buffer.scala 420:110] + node _T_3257 = eq(_T_3256, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:84] + node _T_3258 = and(_T_3253, _T_3257) @[lsu_bus_buffer.scala 420:82] + node _T_3259 = bits(buf_rspageQ[1], 2, 2) @[lsu_bus_buffer.scala 420:78] + node _T_3260 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 420:99] + node _T_3261 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 420:125] + node _T_3262 = or(_T_3260, _T_3261) @[lsu_bus_buffer.scala 420:110] + node _T_3263 = eq(_T_3262, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:84] + node _T_3264 = and(_T_3259, _T_3263) @[lsu_bus_buffer.scala 420:82] + node _T_3265 = bits(buf_rspageQ[1], 3, 3) @[lsu_bus_buffer.scala 420:78] + node _T_3266 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 420:99] + node _T_3267 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 420:125] + node _T_3268 = or(_T_3266, _T_3267) @[lsu_bus_buffer.scala 420:110] + node _T_3269 = eq(_T_3268, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:84] + node _T_3270 = and(_T_3265, _T_3269) @[lsu_bus_buffer.scala 420:82] + node _T_3271 = cat(_T_3270, _T_3264) @[Cat.scala 29:58] + node _T_3272 = cat(_T_3271, _T_3258) @[Cat.scala 29:58] + node _T_3273 = cat(_T_3272, _T_3252) @[Cat.scala 29:58] + node _T_3274 = bits(buf_rspageQ[2], 0, 0) @[lsu_bus_buffer.scala 420:78] + node _T_3275 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 420:99] + node _T_3276 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 420:125] + node _T_3277 = or(_T_3275, _T_3276) @[lsu_bus_buffer.scala 420:110] + node _T_3278 = eq(_T_3277, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:84] + node _T_3279 = and(_T_3274, _T_3278) @[lsu_bus_buffer.scala 420:82] + node _T_3280 = bits(buf_rspageQ[2], 1, 1) @[lsu_bus_buffer.scala 420:78] + node _T_3281 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 420:99] + node _T_3282 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 420:125] + node _T_3283 = or(_T_3281, _T_3282) @[lsu_bus_buffer.scala 420:110] + node _T_3284 = eq(_T_3283, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:84] + node _T_3285 = and(_T_3280, _T_3284) @[lsu_bus_buffer.scala 420:82] + node _T_3286 = bits(buf_rspageQ[2], 2, 2) @[lsu_bus_buffer.scala 420:78] + node _T_3287 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 420:99] + node _T_3288 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 420:125] + node _T_3289 = or(_T_3287, _T_3288) @[lsu_bus_buffer.scala 420:110] + node _T_3290 = eq(_T_3289, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:84] + node _T_3291 = and(_T_3286, _T_3290) @[lsu_bus_buffer.scala 420:82] + node _T_3292 = bits(buf_rspageQ[2], 3, 3) @[lsu_bus_buffer.scala 420:78] + node _T_3293 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 420:99] + node _T_3294 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 420:125] + node _T_3295 = or(_T_3293, _T_3294) @[lsu_bus_buffer.scala 420:110] + node _T_3296 = eq(_T_3295, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:84] + node _T_3297 = and(_T_3292, _T_3296) @[lsu_bus_buffer.scala 420:82] + node _T_3298 = cat(_T_3297, _T_3291) @[Cat.scala 29:58] + node _T_3299 = cat(_T_3298, _T_3285) @[Cat.scala 29:58] + node _T_3300 = cat(_T_3299, _T_3279) @[Cat.scala 29:58] + node _T_3301 = bits(buf_rspageQ[3], 0, 0) @[lsu_bus_buffer.scala 420:78] + node _T_3302 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 420:99] + node _T_3303 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 420:125] + node _T_3304 = or(_T_3302, _T_3303) @[lsu_bus_buffer.scala 420:110] + node _T_3305 = eq(_T_3304, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:84] + node _T_3306 = and(_T_3301, _T_3305) @[lsu_bus_buffer.scala 420:82] + node _T_3307 = bits(buf_rspageQ[3], 1, 1) @[lsu_bus_buffer.scala 420:78] + node _T_3308 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 420:99] + node _T_3309 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 420:125] + node _T_3310 = or(_T_3308, _T_3309) @[lsu_bus_buffer.scala 420:110] + node _T_3311 = eq(_T_3310, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:84] + node _T_3312 = and(_T_3307, _T_3311) @[lsu_bus_buffer.scala 420:82] + node _T_3313 = bits(buf_rspageQ[3], 2, 2) @[lsu_bus_buffer.scala 420:78] + node _T_3314 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 420:99] + node _T_3315 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 420:125] + node _T_3316 = or(_T_3314, _T_3315) @[lsu_bus_buffer.scala 420:110] + node _T_3317 = eq(_T_3316, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:84] + node _T_3318 = and(_T_3313, _T_3317) @[lsu_bus_buffer.scala 420:82] + node _T_3319 = bits(buf_rspageQ[3], 3, 3) @[lsu_bus_buffer.scala 420:78] + node _T_3320 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 420:99] + node _T_3321 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 420:125] + node _T_3322 = or(_T_3320, _T_3321) @[lsu_bus_buffer.scala 420:110] + node _T_3323 = eq(_T_3322, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:84] + node _T_3324 = and(_T_3319, _T_3323) @[lsu_bus_buffer.scala 420:82] + node _T_3325 = cat(_T_3324, _T_3318) @[Cat.scala 29:58] + node _T_3326 = cat(_T_3325, _T_3312) @[Cat.scala 29:58] + node _T_3327 = cat(_T_3326, _T_3306) @[Cat.scala 29:58] + buf_rspage[0] <= _T_3246 @[lsu_bus_buffer.scala 420:14] + buf_rspage[1] <= _T_3273 @[lsu_bus_buffer.scala 420:14] + buf_rspage[2] <= _T_3300 @[lsu_bus_buffer.scala 420:14] + buf_rspage[3] <= _T_3327 @[lsu_bus_buffer.scala 420:14] + node _T_3328 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 425:75] + node _T_3329 = and(ibuf_drain_vld, _T_3328) @[lsu_bus_buffer.scala 425:63] + node _T_3330 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 425:75] + node _T_3331 = and(ibuf_drain_vld, _T_3330) @[lsu_bus_buffer.scala 425:63] + node _T_3332 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 425:75] + node _T_3333 = and(ibuf_drain_vld, _T_3332) @[lsu_bus_buffer.scala 425:63] + node _T_3334 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 425:75] + node _T_3335 = and(ibuf_drain_vld, _T_3334) @[lsu_bus_buffer.scala 425:63] + node _T_3336 = cat(_T_3335, _T_3333) @[Cat.scala 29:58] + node _T_3337 = cat(_T_3336, _T_3331) @[Cat.scala 29:58] + node _T_3338 = cat(_T_3337, _T_3329) @[Cat.scala 29:58] + ibuf_drainvec_vld <= _T_3338 @[lsu_bus_buffer.scala 425:21] + node _T_3339 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 426:64] + node _T_3340 = bits(ibuf_byteen_out, 3, 0) @[lsu_bus_buffer.scala 426:84] + node _T_3341 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 427:18] + node _T_3342 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 427:46] + node _T_3343 = and(_T_3341, _T_3342) @[lsu_bus_buffer.scala 427:35] + node _T_3344 = bits(ldst_byteen_hi_r, 3, 0) @[lsu_bus_buffer.scala 427:71] + node _T_3345 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 427:94] + node _T_3346 = mux(_T_3343, _T_3344, _T_3345) @[lsu_bus_buffer.scala 427:8] + node _T_3347 = mux(_T_3339, _T_3340, _T_3346) @[lsu_bus_buffer.scala 426:46] + node _T_3348 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 426:64] + node _T_3349 = bits(ibuf_byteen_out, 3, 0) @[lsu_bus_buffer.scala 426:84] + node _T_3350 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 427:18] + node _T_3351 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 427:46] + node _T_3352 = and(_T_3350, _T_3351) @[lsu_bus_buffer.scala 427:35] + node _T_3353 = bits(ldst_byteen_hi_r, 3, 0) @[lsu_bus_buffer.scala 427:71] + node _T_3354 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 427:94] + node _T_3355 = mux(_T_3352, _T_3353, _T_3354) @[lsu_bus_buffer.scala 427:8] + node _T_3356 = mux(_T_3348, _T_3349, _T_3355) @[lsu_bus_buffer.scala 426:46] + node _T_3357 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 426:64] + node _T_3358 = bits(ibuf_byteen_out, 3, 0) @[lsu_bus_buffer.scala 426:84] + node _T_3359 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 427:18] + node _T_3360 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 427:46] + node _T_3361 = and(_T_3359, _T_3360) @[lsu_bus_buffer.scala 427:35] + node _T_3362 = bits(ldst_byteen_hi_r, 3, 0) @[lsu_bus_buffer.scala 427:71] + node _T_3363 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 427:94] + node _T_3364 = mux(_T_3361, _T_3362, _T_3363) @[lsu_bus_buffer.scala 427:8] + node _T_3365 = mux(_T_3357, _T_3358, _T_3364) @[lsu_bus_buffer.scala 426:46] + node _T_3366 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 426:64] + node _T_3367 = bits(ibuf_byteen_out, 3, 0) @[lsu_bus_buffer.scala 426:84] + node _T_3368 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 427:18] + node _T_3369 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 427:46] + node _T_3370 = and(_T_3368, _T_3369) @[lsu_bus_buffer.scala 427:35] + node _T_3371 = bits(ldst_byteen_hi_r, 3, 0) @[lsu_bus_buffer.scala 427:71] + node _T_3372 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 427:94] + node _T_3373 = mux(_T_3370, _T_3371, _T_3372) @[lsu_bus_buffer.scala 427:8] + node _T_3374 = mux(_T_3366, _T_3367, _T_3373) @[lsu_bus_buffer.scala 426:46] + buf_byteen_in[0] <= _T_3347 @[lsu_bus_buffer.scala 426:17] + buf_byteen_in[1] <= _T_3356 @[lsu_bus_buffer.scala 426:17] + buf_byteen_in[2] <= _T_3365 @[lsu_bus_buffer.scala 426:17] + buf_byteen_in[3] <= _T_3374 @[lsu_bus_buffer.scala 426:17] + node _T_3375 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 428:62] + node _T_3376 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 428:91] + node _T_3377 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 428:119] + node _T_3378 = and(_T_3376, _T_3377) @[lsu_bus_buffer.scala 428:108] + node _T_3379 = mux(_T_3378, io.end_addr_r, io.lsu_addr_r) @[lsu_bus_buffer.scala 428:81] + node _T_3380 = mux(_T_3375, ibuf_addr, _T_3379) @[lsu_bus_buffer.scala 428:44] + node _T_3381 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 428:62] + node _T_3382 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 428:91] + node _T_3383 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 428:119] + node _T_3384 = and(_T_3382, _T_3383) @[lsu_bus_buffer.scala 428:108] + node _T_3385 = mux(_T_3384, io.end_addr_r, io.lsu_addr_r) @[lsu_bus_buffer.scala 428:81] + node _T_3386 = mux(_T_3381, ibuf_addr, _T_3385) @[lsu_bus_buffer.scala 428:44] + node _T_3387 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 428:62] + node _T_3388 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 428:91] + node _T_3389 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 428:119] + node _T_3390 = and(_T_3388, _T_3389) @[lsu_bus_buffer.scala 428:108] + node _T_3391 = mux(_T_3390, io.end_addr_r, io.lsu_addr_r) @[lsu_bus_buffer.scala 428:81] + node _T_3392 = mux(_T_3387, ibuf_addr, _T_3391) @[lsu_bus_buffer.scala 428:44] + node _T_3393 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 428:62] + node _T_3394 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 428:91] + node _T_3395 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 428:119] + node _T_3396 = and(_T_3394, _T_3395) @[lsu_bus_buffer.scala 428:108] + node _T_3397 = mux(_T_3396, io.end_addr_r, io.lsu_addr_r) @[lsu_bus_buffer.scala 428:81] + node _T_3398 = mux(_T_3393, ibuf_addr, _T_3397) @[lsu_bus_buffer.scala 428:44] + buf_addr_in[0] <= _T_3380 @[lsu_bus_buffer.scala 428:15] + buf_addr_in[1] <= _T_3386 @[lsu_bus_buffer.scala 428:15] + buf_addr_in[2] <= _T_3392 @[lsu_bus_buffer.scala 428:15] + buf_addr_in[3] <= _T_3398 @[lsu_bus_buffer.scala 428:15] + node _T_3399 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 429:63] + node _T_3400 = mux(_T_3399, ibuf_dual, io.ldst_dual_r) @[lsu_bus_buffer.scala 429:45] + node _T_3401 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 429:63] + node _T_3402 = mux(_T_3401, ibuf_dual, io.ldst_dual_r) @[lsu_bus_buffer.scala 429:45] + node _T_3403 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 429:63] + node _T_3404 = mux(_T_3403, ibuf_dual, io.ldst_dual_r) @[lsu_bus_buffer.scala 429:45] + node _T_3405 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 429:63] + node _T_3406 = mux(_T_3405, ibuf_dual, io.ldst_dual_r) @[lsu_bus_buffer.scala 429:45] + node _T_3407 = cat(_T_3406, _T_3404) @[Cat.scala 29:58] + node _T_3408 = cat(_T_3407, _T_3402) @[Cat.scala 29:58] + node _T_3409 = cat(_T_3408, _T_3400) @[Cat.scala 29:58] + buf_dual_in <= _T_3409 @[lsu_bus_buffer.scala 429:15] + node _T_3410 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 430:65] + node _T_3411 = mux(_T_3410, ibuf_samedw, ldst_samedw_r) @[lsu_bus_buffer.scala 430:47] + node _T_3412 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 430:65] + node _T_3413 = mux(_T_3412, ibuf_samedw, ldst_samedw_r) @[lsu_bus_buffer.scala 430:47] + node _T_3414 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 430:65] + node _T_3415 = mux(_T_3414, ibuf_samedw, ldst_samedw_r) @[lsu_bus_buffer.scala 430:47] + node _T_3416 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 430:65] + node _T_3417 = mux(_T_3416, ibuf_samedw, ldst_samedw_r) @[lsu_bus_buffer.scala 430:47] + node _T_3418 = cat(_T_3417, _T_3415) @[Cat.scala 29:58] + node _T_3419 = cat(_T_3418, _T_3413) @[Cat.scala 29:58] + node _T_3420 = cat(_T_3419, _T_3411) @[Cat.scala 29:58] + buf_samedw_in <= _T_3420 @[lsu_bus_buffer.scala 430:17] + node _T_3421 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 431:66] + node _T_3422 = or(ibuf_nomerge, ibuf_force_drain) @[lsu_bus_buffer.scala 431:84] + node _T_3423 = mux(_T_3421, _T_3422, io.no_dword_merge_r) @[lsu_bus_buffer.scala 431:48] + node _T_3424 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 431:66] + node _T_3425 = or(ibuf_nomerge, ibuf_force_drain) @[lsu_bus_buffer.scala 431:84] + node _T_3426 = mux(_T_3424, _T_3425, io.no_dword_merge_r) @[lsu_bus_buffer.scala 431:48] + node _T_3427 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 431:66] + node _T_3428 = or(ibuf_nomerge, ibuf_force_drain) @[lsu_bus_buffer.scala 431:84] + node _T_3429 = mux(_T_3427, _T_3428, io.no_dword_merge_r) @[lsu_bus_buffer.scala 431:48] + node _T_3430 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 431:66] + node _T_3431 = or(ibuf_nomerge, ibuf_force_drain) @[lsu_bus_buffer.scala 431:84] + node _T_3432 = mux(_T_3430, _T_3431, io.no_dword_merge_r) @[lsu_bus_buffer.scala 431:48] + node _T_3433 = cat(_T_3432, _T_3429) @[Cat.scala 29:58] + node _T_3434 = cat(_T_3433, _T_3426) @[Cat.scala 29:58] + node _T_3435 = cat(_T_3434, _T_3423) @[Cat.scala 29:58] + buf_nomerge_in <= _T_3435 @[lsu_bus_buffer.scala 431:18] + node _T_3436 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 432:65] + node _T_3437 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 432:90] + node _T_3438 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 432:118] + node _T_3439 = and(_T_3437, _T_3438) @[lsu_bus_buffer.scala 432:107] + node _T_3440 = mux(_T_3436, ibuf_dual, _T_3439) @[lsu_bus_buffer.scala 432:47] + node _T_3441 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 432:65] + node _T_3442 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 432:90] + node _T_3443 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 432:118] + node _T_3444 = and(_T_3442, _T_3443) @[lsu_bus_buffer.scala 432:107] + node _T_3445 = mux(_T_3441, ibuf_dual, _T_3444) @[lsu_bus_buffer.scala 432:47] + node _T_3446 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 432:65] + node _T_3447 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 432:90] + node _T_3448 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 432:118] + node _T_3449 = and(_T_3447, _T_3448) @[lsu_bus_buffer.scala 432:107] + node _T_3450 = mux(_T_3446, ibuf_dual, _T_3449) @[lsu_bus_buffer.scala 432:47] + node _T_3451 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 432:65] + node _T_3452 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 432:90] + node _T_3453 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 432:118] + node _T_3454 = and(_T_3452, _T_3453) @[lsu_bus_buffer.scala 432:107] + node _T_3455 = mux(_T_3451, ibuf_dual, _T_3454) @[lsu_bus_buffer.scala 432:47] + node _T_3456 = cat(_T_3455, _T_3450) @[Cat.scala 29:58] + node _T_3457 = cat(_T_3456, _T_3445) @[Cat.scala 29:58] + node _T_3458 = cat(_T_3457, _T_3440) @[Cat.scala 29:58] + buf_dualhi_in <= _T_3458 @[lsu_bus_buffer.scala 432:17] + node _T_3459 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 433:65] + node _T_3460 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 433:97] + node _T_3461 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 433:125] + node _T_3462 = and(_T_3460, _T_3461) @[lsu_bus_buffer.scala 433:114] + node _T_3463 = mux(_T_3462, WrPtr0_r, WrPtr1_r) @[lsu_bus_buffer.scala 433:87] + node _T_3464 = mux(_T_3459, ibuf_dualtag, _T_3463) @[lsu_bus_buffer.scala 433:47] + node _T_3465 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 433:65] + node _T_3466 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 433:97] + node _T_3467 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 433:125] + node _T_3468 = and(_T_3466, _T_3467) @[lsu_bus_buffer.scala 433:114] + node _T_3469 = mux(_T_3468, WrPtr0_r, WrPtr1_r) @[lsu_bus_buffer.scala 433:87] + node _T_3470 = mux(_T_3465, ibuf_dualtag, _T_3469) @[lsu_bus_buffer.scala 433:47] + node _T_3471 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 433:65] + node _T_3472 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 433:97] + node _T_3473 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 433:125] + node _T_3474 = and(_T_3472, _T_3473) @[lsu_bus_buffer.scala 433:114] + node _T_3475 = mux(_T_3474, WrPtr0_r, WrPtr1_r) @[lsu_bus_buffer.scala 433:87] + node _T_3476 = mux(_T_3471, ibuf_dualtag, _T_3475) @[lsu_bus_buffer.scala 433:47] + node _T_3477 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 433:65] + node _T_3478 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 433:97] + node _T_3479 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 433:125] + node _T_3480 = and(_T_3478, _T_3479) @[lsu_bus_buffer.scala 433:114] + node _T_3481 = mux(_T_3480, WrPtr0_r, WrPtr1_r) @[lsu_bus_buffer.scala 433:87] + node _T_3482 = mux(_T_3477, ibuf_dualtag, _T_3481) @[lsu_bus_buffer.scala 433:47] + buf_dualtag_in[0] <= _T_3464 @[lsu_bus_buffer.scala 433:18] + buf_dualtag_in[1] <= _T_3470 @[lsu_bus_buffer.scala 433:18] + buf_dualtag_in[2] <= _T_3476 @[lsu_bus_buffer.scala 433:18] + buf_dualtag_in[3] <= _T_3482 @[lsu_bus_buffer.scala 433:18] + node _T_3483 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 434:69] + node _T_3484 = mux(_T_3483, ibuf_sideeffect, io.is_sideeffects_r) @[lsu_bus_buffer.scala 434:51] + node _T_3485 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 434:69] + node _T_3486 = mux(_T_3485, ibuf_sideeffect, io.is_sideeffects_r) @[lsu_bus_buffer.scala 434:51] + node _T_3487 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 434:69] + node _T_3488 = mux(_T_3487, ibuf_sideeffect, io.is_sideeffects_r) @[lsu_bus_buffer.scala 434:51] + node _T_3489 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 434:69] + node _T_3490 = mux(_T_3489, ibuf_sideeffect, io.is_sideeffects_r) @[lsu_bus_buffer.scala 434:51] + node _T_3491 = cat(_T_3490, _T_3488) @[Cat.scala 29:58] + node _T_3492 = cat(_T_3491, _T_3486) @[Cat.scala 29:58] + node _T_3493 = cat(_T_3492, _T_3484) @[Cat.scala 29:58] + buf_sideeffect_in <= _T_3493 @[lsu_bus_buffer.scala 434:21] + node _T_3494 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 435:65] + node _T_3495 = mux(_T_3494, ibuf_unsign, io.lsu_pkt_r.bits.unsign) @[lsu_bus_buffer.scala 435:47] + node _T_3496 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 435:65] + node _T_3497 = mux(_T_3496, ibuf_unsign, io.lsu_pkt_r.bits.unsign) @[lsu_bus_buffer.scala 435:47] + node _T_3498 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 435:65] + node _T_3499 = mux(_T_3498, ibuf_unsign, io.lsu_pkt_r.bits.unsign) @[lsu_bus_buffer.scala 435:47] + node _T_3500 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 435:65] + node _T_3501 = mux(_T_3500, ibuf_unsign, io.lsu_pkt_r.bits.unsign) @[lsu_bus_buffer.scala 435:47] + node _T_3502 = cat(_T_3501, _T_3499) @[Cat.scala 29:58] + node _T_3503 = cat(_T_3502, _T_3497) @[Cat.scala 29:58] + node _T_3504 = cat(_T_3503, _T_3495) @[Cat.scala 29:58] + buf_unsign_in <= _T_3504 @[lsu_bus_buffer.scala 435:17] + node _T_3505 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 436:60] + node _T_3506 = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58] + node _T_3507 = mux(_T_3505, ibuf_sz, _T_3506) @[lsu_bus_buffer.scala 436:42] + node _T_3508 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 436:60] + node _T_3509 = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58] + node _T_3510 = mux(_T_3508, ibuf_sz, _T_3509) @[lsu_bus_buffer.scala 436:42] + node _T_3511 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 436:60] + node _T_3512 = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58] + node _T_3513 = mux(_T_3511, ibuf_sz, _T_3512) @[lsu_bus_buffer.scala 436:42] + node _T_3514 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 436:60] + node _T_3515 = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58] + node _T_3516 = mux(_T_3514, ibuf_sz, _T_3515) @[lsu_bus_buffer.scala 436:42] + buf_sz_in[0] <= _T_3507 @[lsu_bus_buffer.scala 436:13] + buf_sz_in[1] <= _T_3510 @[lsu_bus_buffer.scala 436:13] + buf_sz_in[2] <= _T_3513 @[lsu_bus_buffer.scala 436:13] + buf_sz_in[3] <= _T_3516 @[lsu_bus_buffer.scala 436:13] + node _T_3517 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 437:64] + node _T_3518 = mux(_T_3517, ibuf_write, io.lsu_pkt_r.bits.store) @[lsu_bus_buffer.scala 437:46] + node _T_3519 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 437:64] + node _T_3520 = mux(_T_3519, ibuf_write, io.lsu_pkt_r.bits.store) @[lsu_bus_buffer.scala 437:46] + node _T_3521 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 437:64] + node _T_3522 = mux(_T_3521, ibuf_write, io.lsu_pkt_r.bits.store) @[lsu_bus_buffer.scala 437:46] + node _T_3523 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 437:64] + node _T_3524 = mux(_T_3523, ibuf_write, io.lsu_pkt_r.bits.store) @[lsu_bus_buffer.scala 437:46] + node _T_3525 = cat(_T_3524, _T_3522) @[Cat.scala 29:58] + node _T_3526 = cat(_T_3525, _T_3520) @[Cat.scala 29:58] + node _T_3527 = cat(_T_3526, _T_3518) @[Cat.scala 29:58] + buf_write_in <= _T_3527 @[lsu_bus_buffer.scala 437:16] + node _T_3528 = eq(UInt<3>("h00"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3528 : @[Conditional.scala 40:58] + node _T_3529 = bits(io.lsu_bus_clk_en, 0, 0) @[lsu_bus_buffer.scala 442:56] + node _T_3530 = mux(_T_3529, UInt<3>("h02"), UInt<3>("h01")) @[lsu_bus_buffer.scala 442:31] + buf_nxtstate[0] <= _T_3530 @[lsu_bus_buffer.scala 442:25] + node _T_3531 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 443:45] + node _T_3532 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 443:77] + node _T_3533 = eq(ibuf_merge_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 443:97] + node _T_3534 = and(_T_3532, _T_3533) @[lsu_bus_buffer.scala 443:95] + node _T_3535 = eq(UInt<1>("h00"), WrPtr0_r) @[lsu_bus_buffer.scala 443:117] + node _T_3536 = and(_T_3534, _T_3535) @[lsu_bus_buffer.scala 443:112] + node _T_3537 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 443:144] + node _T_3538 = eq(UInt<1>("h00"), WrPtr1_r) @[lsu_bus_buffer.scala 443:166] + node _T_3539 = and(_T_3537, _T_3538) @[lsu_bus_buffer.scala 443:161] + node _T_3540 = or(_T_3536, _T_3539) @[lsu_bus_buffer.scala 443:132] + node _T_3541 = and(_T_3531, _T_3540) @[lsu_bus_buffer.scala 443:63] + node _T_3542 = eq(UInt<1>("h00"), ibuf_tag) @[lsu_bus_buffer.scala 443:206] + node _T_3543 = and(ibuf_drain_vld, _T_3542) @[lsu_bus_buffer.scala 443:201] + node _T_3544 = or(_T_3541, _T_3543) @[lsu_bus_buffer.scala 443:183] + buf_state_en[0] <= _T_3544 @[lsu_bus_buffer.scala 443:25] + buf_wr_en[0] <= buf_state_en[0] @[lsu_bus_buffer.scala 444:22] + buf_data_en[0] <= buf_state_en[0] @[lsu_bus_buffer.scala 445:24] + node _T_3545 = eq(UInt<1>("h00"), ibuf_tag) @[lsu_bus_buffer.scala 446:52] + node _T_3546 = and(ibuf_drain_vld, _T_3545) @[lsu_bus_buffer.scala 446:47] + node _T_3547 = bits(_T_3546, 0, 0) @[lsu_bus_buffer.scala 446:73] + node _T_3548 = bits(ibuf_data_out, 31, 0) @[lsu_bus_buffer.scala 446:90] + node _T_3549 = bits(store_data_lo_r, 31, 0) @[lsu_bus_buffer.scala 446:114] + node _T_3550 = mux(_T_3547, _T_3548, _T_3549) @[lsu_bus_buffer.scala 446:30] + buf_data_in[0] <= _T_3550 @[lsu_bus_buffer.scala 446:24] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_3551 = eq(UInt<3>("h01"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3551 : @[Conditional.scala 39:67] + node _T_3552 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 449:60] + node _T_3553 = mux(_T_3552, UInt<3>("h00"), UInt<3>("h02")) @[lsu_bus_buffer.scala 449:31] + buf_nxtstate[0] <= _T_3553 @[lsu_bus_buffer.scala 449:25] + node _T_3554 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 450:46] + buf_state_en[0] <= _T_3554 @[lsu_bus_buffer.scala 450:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3555 = eq(UInt<3>("h02"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3555 : @[Conditional.scala 39:67] + node _T_3556 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 453:60] + node _T_3557 = and(obuf_nosend, bus_rsp_read) @[lsu_bus_buffer.scala 453:89] + node _T_3558 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 453:124] + node _T_3559 = and(_T_3557, _T_3558) @[lsu_bus_buffer.scala 453:104] + node _T_3560 = mux(_T_3559, UInt<3>("h05"), UInt<3>("h03")) @[lsu_bus_buffer.scala 453:75] + node _T_3561 = mux(_T_3556, UInt<3>("h00"), _T_3560) @[lsu_bus_buffer.scala 453:31] + buf_nxtstate[0] <= _T_3561 @[lsu_bus_buffer.scala 453:25] + node _T_3562 = eq(obuf_tag0, UInt<3>("h00")) @[lsu_bus_buffer.scala 454:48] + node _T_3563 = eq(obuf_tag1, UInt<3>("h00")) @[lsu_bus_buffer.scala 454:104] + node _T_3564 = and(obuf_merge, _T_3563) @[lsu_bus_buffer.scala 454:91] + node _T_3565 = or(_T_3562, _T_3564) @[lsu_bus_buffer.scala 454:77] + node _T_3566 = and(_T_3565, obuf_valid) @[lsu_bus_buffer.scala 454:135] + node _T_3567 = and(_T_3566, obuf_wr_enQ) @[lsu_bus_buffer.scala 454:148] + buf_cmd_state_bus_en[0] <= _T_3567 @[lsu_bus_buffer.scala 454:33] + buf_state_bus_en[0] <= buf_cmd_state_bus_en[0] @[lsu_bus_buffer.scala 455:29] + node _T_3568 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 456:49] + node _T_3569 = or(_T_3568, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 456:70] + buf_state_en[0] <= _T_3569 @[lsu_bus_buffer.scala 456:25] + buf_ldfwd_in[0] <= UInt<1>("h01") @[lsu_bus_buffer.scala 457:25] + node _T_3570 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 458:56] + node _T_3571 = eq(_T_3570, UInt<1>("h00")) @[lsu_bus_buffer.scala 458:46] + node _T_3572 = and(buf_state_en[0], _T_3571) @[lsu_bus_buffer.scala 458:44] + node _T_3573 = and(_T_3572, obuf_nosend) @[lsu_bus_buffer.scala 458:60] + node _T_3574 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 458:76] + node _T_3575 = and(_T_3573, _T_3574) @[lsu_bus_buffer.scala 458:74] + buf_ldfwd_en[0] <= _T_3575 @[lsu_bus_buffer.scala 458:25] + node _T_3576 = bits(obuf_rdrsp_tag, 1, 0) @[lsu_bus_buffer.scala 459:46] + buf_ldfwdtag_in[0] <= _T_3576 @[lsu_bus_buffer.scala 459:28] + node _T_3577 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 460:47] + node _T_3578 = and(_T_3577, obuf_nosend) @[lsu_bus_buffer.scala 460:67] + node _T_3579 = and(_T_3578, bus_rsp_read) @[lsu_bus_buffer.scala 460:81] + buf_data_en[0] <= _T_3579 @[lsu_bus_buffer.scala 460:24] + node _T_3580 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 461:48] + node _T_3581 = and(_T_3580, obuf_nosend) @[lsu_bus_buffer.scala 461:68] + node _T_3582 = and(_T_3581, bus_rsp_read_error) @[lsu_bus_buffer.scala 461:82] + buf_error_en[0] <= _T_3582 @[lsu_bus_buffer.scala 461:25] + node _T_3583 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 462:61] + node _T_3584 = bits(buf_addr[0], 2, 2) @[lsu_bus_buffer.scala 462:85] + node _T_3585 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 462:103] + node _T_3586 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 462:126] + node _T_3587 = mux(_T_3584, _T_3585, _T_3586) @[lsu_bus_buffer.scala 462:73] + node _T_3588 = mux(buf_error_en[0], _T_3583, _T_3587) @[lsu_bus_buffer.scala 462:30] + buf_data_in[0] <= _T_3588 @[lsu_bus_buffer.scala 462:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3589 = eq(UInt<3>("h03"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3589 : @[Conditional.scala 39:67] + node _T_3590 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 465:67] + node _T_3591 = and(UInt<1>("h00"), bus_rsp_write_error) @[lsu_bus_buffer.scala 465:94] + node _T_3592 = eq(_T_3591, UInt<1>("h00")) @[lsu_bus_buffer.scala 465:73] + node _T_3593 = and(_T_3590, _T_3592) @[lsu_bus_buffer.scala 465:71] + node _T_3594 = or(io.dec_tlu_force_halt, _T_3593) @[lsu_bus_buffer.scala 465:55] + node _T_3595 = bits(_T_3594, 0, 0) @[lsu_bus_buffer.scala 465:125] + node _T_3596 = eq(buf_samedw[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 466:30] + node _T_3597 = and(buf_dual[0], _T_3596) @[lsu_bus_buffer.scala 466:28] + node _T_3598 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 466:57] + node _T_3599 = eq(_T_3598, UInt<1>("h00")) @[lsu_bus_buffer.scala 466:47] + node _T_3600 = and(_T_3597, _T_3599) @[lsu_bus_buffer.scala 466:45] + node _T_3601 = neq(buf_state[buf_dualtag[0]], UInt<3>("h04")) @[lsu_bus_buffer.scala 466:90] + node _T_3602 = and(_T_3600, _T_3601) @[lsu_bus_buffer.scala 466:61] + node _T_3603 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 467:27] + node _T_3604 = or(_T_3603, any_done_wait_state) @[lsu_bus_buffer.scala 467:31] + node _T_3605 = eq(buf_samedw[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 467:70] + node _T_3606 = and(buf_dual[0], _T_3605) @[lsu_bus_buffer.scala 467:68] + node _T_3607 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 467:97] + node _T_3608 = eq(_T_3607, UInt<1>("h00")) @[lsu_bus_buffer.scala 467:87] + node _T_3609 = and(_T_3606, _T_3608) @[lsu_bus_buffer.scala 467:85] + node _T_3610 = eq(buf_dualtag[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_3611 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_3612 = eq(buf_dualtag[0], UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_3613 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_3614 = eq(buf_dualtag[0], UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_3615 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_3616 = eq(buf_dualtag[0], UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_3617 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 57:129] + node _T_3618 = mux(_T_3610, _T_3611, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3619 = mux(_T_3612, _T_3613, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3620 = mux(_T_3614, _T_3615, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3621 = mux(_T_3616, _T_3617, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3622 = or(_T_3618, _T_3619) @[Mux.scala 27:72] + node _T_3623 = or(_T_3622, _T_3620) @[Mux.scala 27:72] + node _T_3624 = or(_T_3623, _T_3621) @[Mux.scala 27:72] + wire _T_3625 : UInt<1> @[Mux.scala 27:72] + _T_3625 <= _T_3624 @[Mux.scala 27:72] + node _T_3626 = and(_T_3609, _T_3625) @[lsu_bus_buffer.scala 467:101] + node _T_3627 = eq(buf_state[buf_dualtag[0]], UInt<3>("h04")) @[lsu_bus_buffer.scala 467:167] + node _T_3628 = and(_T_3626, _T_3627) @[lsu_bus_buffer.scala 467:138] + node _T_3629 = and(_T_3628, any_done_wait_state) @[lsu_bus_buffer.scala 467:187] + node _T_3630 = or(_T_3604, _T_3629) @[lsu_bus_buffer.scala 467:53] + node _T_3631 = mux(_T_3630, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 467:16] + node _T_3632 = mux(_T_3602, UInt<3>("h04"), _T_3631) @[lsu_bus_buffer.scala 466:14] + node _T_3633 = mux(_T_3595, UInt<3>("h00"), _T_3632) @[lsu_bus_buffer.scala 465:31] + buf_nxtstate[0] <= _T_3633 @[lsu_bus_buffer.scala 465:25] + node _T_3634 = eq(bus_rsp_write_tag, UInt<3>("h00")) @[lsu_bus_buffer.scala 468:73] + node _T_3635 = and(bus_rsp_write, _T_3634) @[lsu_bus_buffer.scala 468:52] + node _T_3636 = eq(bus_rsp_read_tag, UInt<3>("h00")) @[lsu_bus_buffer.scala 469:46] + node _T_3637 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 470:23] + node _T_3638 = eq(bus_rsp_read_tag, buf_ldfwdtag[0]) @[lsu_bus_buffer.scala 470:47] + node _T_3639 = and(_T_3637, _T_3638) @[lsu_bus_buffer.scala 470:27] + node _T_3640 = or(_T_3636, _T_3639) @[lsu_bus_buffer.scala 469:77] + node _T_3641 = and(buf_dual[0], buf_dualhi[0]) @[lsu_bus_buffer.scala 471:26] + node _T_3642 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 471:54] + node _T_3643 = not(_T_3642) @[lsu_bus_buffer.scala 471:44] + node _T_3644 = and(_T_3641, _T_3643) @[lsu_bus_buffer.scala 471:42] + node _T_3645 = and(_T_3644, buf_samedw[0]) @[lsu_bus_buffer.scala 471:58] + node _T_3646 = eq(bus_rsp_read_tag, buf_dualtag[0]) @[lsu_bus_buffer.scala 471:94] + node _T_3647 = and(_T_3645, _T_3646) @[lsu_bus_buffer.scala 471:74] + node _T_3648 = or(_T_3640, _T_3647) @[lsu_bus_buffer.scala 470:71] + node _T_3649 = and(bus_rsp_read, _T_3648) @[lsu_bus_buffer.scala 469:25] + node _T_3650 = or(_T_3635, _T_3649) @[lsu_bus_buffer.scala 468:105] + buf_resp_state_bus_en[0] <= _T_3650 @[lsu_bus_buffer.scala 468:34] + buf_state_bus_en[0] <= buf_resp_state_bus_en[0] @[lsu_bus_buffer.scala 472:29] + node _T_3651 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 473:49] + node _T_3652 = or(_T_3651, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 473:70] + buf_state_en[0] <= _T_3652 @[lsu_bus_buffer.scala 473:25] + node _T_3653 = and(buf_state_bus_en[0], bus_rsp_read) @[lsu_bus_buffer.scala 474:47] + node _T_3654 = and(_T_3653, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 474:62] + buf_data_en[0] <= _T_3654 @[lsu_bus_buffer.scala 474:24] + node _T_3655 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 475:48] + node _T_3656 = eq(bus_rsp_read_tag, UInt<3>("h00")) @[lsu_bus_buffer.scala 475:111] + node _T_3657 = and(bus_rsp_read_error, _T_3656) @[lsu_bus_buffer.scala 475:91] + node _T_3658 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 476:42] + node _T_3659 = and(bus_rsp_read_error, _T_3658) @[lsu_bus_buffer.scala 476:31] + node _T_3660 = eq(bus_rsp_read_tag, buf_ldfwdtag[0]) @[lsu_bus_buffer.scala 476:66] + node _T_3661 = and(_T_3659, _T_3660) @[lsu_bus_buffer.scala 476:46] + node _T_3662 = or(_T_3657, _T_3661) @[lsu_bus_buffer.scala 475:143] + node _T_3663 = and(bus_rsp_write_error, UInt<1>("h00")) @[lsu_bus_buffer.scala 477:32] + node _T_3664 = eq(bus_rsp_write_tag, UInt<3>("h00")) @[lsu_bus_buffer.scala 477:74] + node _T_3665 = and(_T_3663, _T_3664) @[lsu_bus_buffer.scala 477:53] + node _T_3666 = or(_T_3662, _T_3665) @[lsu_bus_buffer.scala 476:88] + node _T_3667 = and(_T_3655, _T_3666) @[lsu_bus_buffer.scala 475:68] + buf_error_en[0] <= _T_3667 @[lsu_bus_buffer.scala 475:25] + node _T_3668 = eq(buf_error_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 478:50] + node _T_3669 = and(buf_state_en[0], _T_3668) @[lsu_bus_buffer.scala 478:48] + node _T_3670 = bits(buf_addr[0], 2, 2) @[lsu_bus_buffer.scala 478:84] + node _T_3671 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 478:102] + node _T_3672 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 478:125] + node _T_3673 = mux(_T_3670, _T_3671, _T_3672) @[lsu_bus_buffer.scala 478:72] + node _T_3674 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 478:148] + node _T_3675 = mux(_T_3669, _T_3673, _T_3674) @[lsu_bus_buffer.scala 478:30] + buf_data_in[0] <= _T_3675 @[lsu_bus_buffer.scala 478:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3676 = eq(UInt<3>("h04"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3676 : @[Conditional.scala 39:67] + node _T_3677 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 481:60] + node _T_3678 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 481:86] + node _T_3679 = dshr(buf_ldfwd, buf_dualtag[0]) @[lsu_bus_buffer.scala 481:101] + node _T_3680 = bits(_T_3679, 0, 0) @[lsu_bus_buffer.scala 481:101] + node _T_3681 = or(_T_3678, _T_3680) @[lsu_bus_buffer.scala 481:90] + node _T_3682 = or(_T_3681, any_done_wait_state) @[lsu_bus_buffer.scala 481:118] + node _T_3683 = mux(_T_3682, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 481:75] + node _T_3684 = mux(_T_3677, UInt<3>("h00"), _T_3683) @[lsu_bus_buffer.scala 481:31] + buf_nxtstate[0] <= _T_3684 @[lsu_bus_buffer.scala 481:25] + node _T_3685 = eq(bus_rsp_read_tag, buf_dualtag[0]) @[lsu_bus_buffer.scala 482:66] + node _T_3686 = dshr(buf_ldfwd, buf_dualtag[0]) @[lsu_bus_buffer.scala 483:21] + node _T_3687 = bits(_T_3686, 0, 0) @[lsu_bus_buffer.scala 483:21] + node _T_3688 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[0]]) @[lsu_bus_buffer.scala 483:58] + node _T_3689 = and(_T_3687, _T_3688) @[lsu_bus_buffer.scala 483:38] + node _T_3690 = or(_T_3685, _T_3689) @[lsu_bus_buffer.scala 482:95] + node _T_3691 = and(bus_rsp_read, _T_3690) @[lsu_bus_buffer.scala 482:45] + buf_state_bus_en[0] <= _T_3691 @[lsu_bus_buffer.scala 482:29] + node _T_3692 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 484:49] + node _T_3693 = or(_T_3692, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 484:70] + buf_state_en[0] <= _T_3693 @[lsu_bus_buffer.scala 484:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3694 = eq(UInt<3>("h05"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3694 : @[Conditional.scala 39:67] + node _T_3695 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 487:60] + node _T_3696 = mux(_T_3695, UInt<3>("h00"), UInt<3>("h06")) @[lsu_bus_buffer.scala 487:31] + buf_nxtstate[0] <= _T_3696 @[lsu_bus_buffer.scala 487:25] + node _T_3697 = eq(RspPtr, UInt<2>("h00")) @[lsu_bus_buffer.scala 488:37] + node _T_3698 = eq(buf_dualtag[0], RspPtr) @[lsu_bus_buffer.scala 488:98] + node _T_3699 = and(buf_dual[0], _T_3698) @[lsu_bus_buffer.scala 488:80] + node _T_3700 = or(_T_3697, _T_3699) @[lsu_bus_buffer.scala 488:65] + node _T_3701 = or(_T_3700, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 488:112] + buf_state_en[0] <= _T_3701 @[lsu_bus_buffer.scala 488:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3702 = eq(UInt<3>("h06"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3702 : @[Conditional.scala 39:67] + buf_nxtstate[0] <= UInt<3>("h00") @[lsu_bus_buffer.scala 491:25] + buf_rst[0] <= UInt<1>("h01") @[lsu_bus_buffer.scala 492:20] + buf_state_en[0] <= UInt<1>("h01") @[lsu_bus_buffer.scala 493:25] + buf_ldfwd_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 494:25] + buf_ldfwd_en[0] <= buf_state_en[0] @[lsu_bus_buffer.scala 495:25] + skip @[Conditional.scala 39:67] + node _T_3703 = bits(buf_state_en[0], 0, 0) @[lsu_bus_buffer.scala 498:108] + reg _T_3704 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3703 : @[Reg.scala 28:19] + _T_3704 <= buf_nxtstate[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_state[0] <= _T_3704 @[lsu_bus_buffer.scala 498:18] + reg _T_3705 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 499:60] + _T_3705 <= buf_age_in_0 @[lsu_bus_buffer.scala 499:60] + buf_ageQ[0] <= _T_3705 @[lsu_bus_buffer.scala 499:17] + reg _T_3706 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 500:63] + _T_3706 <= buf_rspage_in[0] @[lsu_bus_buffer.scala 500:63] + buf_rspageQ[0] <= _T_3706 @[lsu_bus_buffer.scala 500:20] + node _T_3707 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 501:109] + reg _T_3708 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3707 : @[Reg.scala 28:19] + _T_3708 <= buf_dualtag_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualtag[0] <= _T_3708 @[lsu_bus_buffer.scala 501:20] + node _T_3709 = bits(buf_dual_in, 0, 0) @[lsu_bus_buffer.scala 502:74] + node _T_3710 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 502:107] + reg _T_3711 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3710 : @[Reg.scala 28:19] + _T_3711 <= _T_3709 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dual[0] <= _T_3711 @[lsu_bus_buffer.scala 502:17] + node _T_3712 = bits(buf_samedw_in, 0, 0) @[lsu_bus_buffer.scala 503:78] + node _T_3713 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 503:111] + reg _T_3714 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3713 : @[Reg.scala 28:19] + _T_3714 <= _T_3712 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_samedw[0] <= _T_3714 @[lsu_bus_buffer.scala 503:19] + node _T_3715 = bits(buf_nomerge_in, 0, 0) @[lsu_bus_buffer.scala 504:80] + node _T_3716 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 504:113] + reg _T_3717 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3716 : @[Reg.scala 28:19] + _T_3717 <= _T_3715 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_nomerge[0] <= _T_3717 @[lsu_bus_buffer.scala 504:20] + node _T_3718 = bits(buf_dualhi_in, 0, 0) @[lsu_bus_buffer.scala 505:78] + node _T_3719 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 505:111] + reg _T_3720 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3719 : @[Reg.scala 28:19] + _T_3720 <= _T_3718 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualhi[0] <= _T_3720 @[lsu_bus_buffer.scala 505:19] + node _T_3721 = eq(UInt<3>("h00"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3721 : @[Conditional.scala 40:58] + node _T_3722 = bits(io.lsu_bus_clk_en, 0, 0) @[lsu_bus_buffer.scala 442:56] + node _T_3723 = mux(_T_3722, UInt<3>("h02"), UInt<3>("h01")) @[lsu_bus_buffer.scala 442:31] + buf_nxtstate[1] <= _T_3723 @[lsu_bus_buffer.scala 442:25] + node _T_3724 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 443:45] + node _T_3725 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 443:77] + node _T_3726 = eq(ibuf_merge_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 443:97] + node _T_3727 = and(_T_3725, _T_3726) @[lsu_bus_buffer.scala 443:95] + node _T_3728 = eq(UInt<1>("h01"), WrPtr0_r) @[lsu_bus_buffer.scala 443:117] + node _T_3729 = and(_T_3727, _T_3728) @[lsu_bus_buffer.scala 443:112] + node _T_3730 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 443:144] + node _T_3731 = eq(UInt<1>("h01"), WrPtr1_r) @[lsu_bus_buffer.scala 443:166] + node _T_3732 = and(_T_3730, _T_3731) @[lsu_bus_buffer.scala 443:161] + node _T_3733 = or(_T_3729, _T_3732) @[lsu_bus_buffer.scala 443:132] + node _T_3734 = and(_T_3724, _T_3733) @[lsu_bus_buffer.scala 443:63] + node _T_3735 = eq(UInt<1>("h01"), ibuf_tag) @[lsu_bus_buffer.scala 443:206] + node _T_3736 = and(ibuf_drain_vld, _T_3735) @[lsu_bus_buffer.scala 443:201] + node _T_3737 = or(_T_3734, _T_3736) @[lsu_bus_buffer.scala 443:183] + buf_state_en[1] <= _T_3737 @[lsu_bus_buffer.scala 443:25] + buf_wr_en[1] <= buf_state_en[1] @[lsu_bus_buffer.scala 444:22] + buf_data_en[1] <= buf_state_en[1] @[lsu_bus_buffer.scala 445:24] + node _T_3738 = eq(UInt<1>("h01"), ibuf_tag) @[lsu_bus_buffer.scala 446:52] + node _T_3739 = and(ibuf_drain_vld, _T_3738) @[lsu_bus_buffer.scala 446:47] + node _T_3740 = bits(_T_3739, 0, 0) @[lsu_bus_buffer.scala 446:73] + node _T_3741 = bits(ibuf_data_out, 31, 0) @[lsu_bus_buffer.scala 446:90] + node _T_3742 = bits(store_data_lo_r, 31, 0) @[lsu_bus_buffer.scala 446:114] + node _T_3743 = mux(_T_3740, _T_3741, _T_3742) @[lsu_bus_buffer.scala 446:30] + buf_data_in[1] <= _T_3743 @[lsu_bus_buffer.scala 446:24] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_3744 = eq(UInt<3>("h01"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3744 : @[Conditional.scala 39:67] + node _T_3745 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 449:60] + node _T_3746 = mux(_T_3745, UInt<3>("h00"), UInt<3>("h02")) @[lsu_bus_buffer.scala 449:31] + buf_nxtstate[1] <= _T_3746 @[lsu_bus_buffer.scala 449:25] + node _T_3747 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 450:46] + buf_state_en[1] <= _T_3747 @[lsu_bus_buffer.scala 450:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3748 = eq(UInt<3>("h02"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3748 : @[Conditional.scala 39:67] + node _T_3749 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 453:60] + node _T_3750 = and(obuf_nosend, bus_rsp_read) @[lsu_bus_buffer.scala 453:89] + node _T_3751 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 453:124] + node _T_3752 = and(_T_3750, _T_3751) @[lsu_bus_buffer.scala 453:104] + node _T_3753 = mux(_T_3752, UInt<3>("h05"), UInt<3>("h03")) @[lsu_bus_buffer.scala 453:75] + node _T_3754 = mux(_T_3749, UInt<3>("h00"), _T_3753) @[lsu_bus_buffer.scala 453:31] + buf_nxtstate[1] <= _T_3754 @[lsu_bus_buffer.scala 453:25] + node _T_3755 = eq(obuf_tag0, UInt<3>("h01")) @[lsu_bus_buffer.scala 454:48] + node _T_3756 = eq(obuf_tag1, UInt<3>("h01")) @[lsu_bus_buffer.scala 454:104] + node _T_3757 = and(obuf_merge, _T_3756) @[lsu_bus_buffer.scala 454:91] + node _T_3758 = or(_T_3755, _T_3757) @[lsu_bus_buffer.scala 454:77] + node _T_3759 = and(_T_3758, obuf_valid) @[lsu_bus_buffer.scala 454:135] + node _T_3760 = and(_T_3759, obuf_wr_enQ) @[lsu_bus_buffer.scala 454:148] + buf_cmd_state_bus_en[1] <= _T_3760 @[lsu_bus_buffer.scala 454:33] + buf_state_bus_en[1] <= buf_cmd_state_bus_en[1] @[lsu_bus_buffer.scala 455:29] + node _T_3761 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 456:49] + node _T_3762 = or(_T_3761, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 456:70] + buf_state_en[1] <= _T_3762 @[lsu_bus_buffer.scala 456:25] + buf_ldfwd_in[1] <= UInt<1>("h01") @[lsu_bus_buffer.scala 457:25] + node _T_3763 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 458:56] + node _T_3764 = eq(_T_3763, UInt<1>("h00")) @[lsu_bus_buffer.scala 458:46] + node _T_3765 = and(buf_state_en[1], _T_3764) @[lsu_bus_buffer.scala 458:44] + node _T_3766 = and(_T_3765, obuf_nosend) @[lsu_bus_buffer.scala 458:60] + node _T_3767 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 458:76] + node _T_3768 = and(_T_3766, _T_3767) @[lsu_bus_buffer.scala 458:74] + buf_ldfwd_en[1] <= _T_3768 @[lsu_bus_buffer.scala 458:25] + node _T_3769 = bits(obuf_rdrsp_tag, 1, 0) @[lsu_bus_buffer.scala 459:46] + buf_ldfwdtag_in[1] <= _T_3769 @[lsu_bus_buffer.scala 459:28] + node _T_3770 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 460:47] + node _T_3771 = and(_T_3770, obuf_nosend) @[lsu_bus_buffer.scala 460:67] + node _T_3772 = and(_T_3771, bus_rsp_read) @[lsu_bus_buffer.scala 460:81] + buf_data_en[1] <= _T_3772 @[lsu_bus_buffer.scala 460:24] + node _T_3773 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 461:48] + node _T_3774 = and(_T_3773, obuf_nosend) @[lsu_bus_buffer.scala 461:68] + node _T_3775 = and(_T_3774, bus_rsp_read_error) @[lsu_bus_buffer.scala 461:82] + buf_error_en[1] <= _T_3775 @[lsu_bus_buffer.scala 461:25] + node _T_3776 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 462:61] + node _T_3777 = bits(buf_addr[1], 2, 2) @[lsu_bus_buffer.scala 462:85] + node _T_3778 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 462:103] + node _T_3779 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 462:126] + node _T_3780 = mux(_T_3777, _T_3778, _T_3779) @[lsu_bus_buffer.scala 462:73] + node _T_3781 = mux(buf_error_en[1], _T_3776, _T_3780) @[lsu_bus_buffer.scala 462:30] + buf_data_in[1] <= _T_3781 @[lsu_bus_buffer.scala 462:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3782 = eq(UInt<3>("h03"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3782 : @[Conditional.scala 39:67] + node _T_3783 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 465:67] + node _T_3784 = and(UInt<1>("h00"), bus_rsp_write_error) @[lsu_bus_buffer.scala 465:94] + node _T_3785 = eq(_T_3784, UInt<1>("h00")) @[lsu_bus_buffer.scala 465:73] + node _T_3786 = and(_T_3783, _T_3785) @[lsu_bus_buffer.scala 465:71] + node _T_3787 = or(io.dec_tlu_force_halt, _T_3786) @[lsu_bus_buffer.scala 465:55] + node _T_3788 = bits(_T_3787, 0, 0) @[lsu_bus_buffer.scala 465:125] + node _T_3789 = eq(buf_samedw[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 466:30] + node _T_3790 = and(buf_dual[1], _T_3789) @[lsu_bus_buffer.scala 466:28] + node _T_3791 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 466:57] + node _T_3792 = eq(_T_3791, UInt<1>("h00")) @[lsu_bus_buffer.scala 466:47] + node _T_3793 = and(_T_3790, _T_3792) @[lsu_bus_buffer.scala 466:45] + node _T_3794 = neq(buf_state[buf_dualtag[1]], UInt<3>("h04")) @[lsu_bus_buffer.scala 466:90] + node _T_3795 = and(_T_3793, _T_3794) @[lsu_bus_buffer.scala 466:61] + node _T_3796 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 467:27] + node _T_3797 = or(_T_3796, any_done_wait_state) @[lsu_bus_buffer.scala 467:31] + node _T_3798 = eq(buf_samedw[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 467:70] + node _T_3799 = and(buf_dual[1], _T_3798) @[lsu_bus_buffer.scala 467:68] + node _T_3800 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 467:97] + node _T_3801 = eq(_T_3800, UInt<1>("h00")) @[lsu_bus_buffer.scala 467:87] + node _T_3802 = and(_T_3799, _T_3801) @[lsu_bus_buffer.scala 467:85] + node _T_3803 = eq(buf_dualtag[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_3804 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_3805 = eq(buf_dualtag[1], UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_3806 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_3807 = eq(buf_dualtag[1], UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_3808 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_3809 = eq(buf_dualtag[1], UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_3810 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 57:129] + node _T_3811 = mux(_T_3803, _T_3804, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3812 = mux(_T_3805, _T_3806, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3813 = mux(_T_3807, _T_3808, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3814 = mux(_T_3809, _T_3810, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3815 = or(_T_3811, _T_3812) @[Mux.scala 27:72] + node _T_3816 = or(_T_3815, _T_3813) @[Mux.scala 27:72] + node _T_3817 = or(_T_3816, _T_3814) @[Mux.scala 27:72] + wire _T_3818 : UInt<1> @[Mux.scala 27:72] + _T_3818 <= _T_3817 @[Mux.scala 27:72] + node _T_3819 = and(_T_3802, _T_3818) @[lsu_bus_buffer.scala 467:101] + node _T_3820 = eq(buf_state[buf_dualtag[1]], UInt<3>("h04")) @[lsu_bus_buffer.scala 467:167] + node _T_3821 = and(_T_3819, _T_3820) @[lsu_bus_buffer.scala 467:138] + node _T_3822 = and(_T_3821, any_done_wait_state) @[lsu_bus_buffer.scala 467:187] + node _T_3823 = or(_T_3797, _T_3822) @[lsu_bus_buffer.scala 467:53] + node _T_3824 = mux(_T_3823, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 467:16] + node _T_3825 = mux(_T_3795, UInt<3>("h04"), _T_3824) @[lsu_bus_buffer.scala 466:14] + node _T_3826 = mux(_T_3788, UInt<3>("h00"), _T_3825) @[lsu_bus_buffer.scala 465:31] + buf_nxtstate[1] <= _T_3826 @[lsu_bus_buffer.scala 465:25] + node _T_3827 = eq(bus_rsp_write_tag, UInt<3>("h01")) @[lsu_bus_buffer.scala 468:73] + node _T_3828 = and(bus_rsp_write, _T_3827) @[lsu_bus_buffer.scala 468:52] + node _T_3829 = eq(bus_rsp_read_tag, UInt<3>("h01")) @[lsu_bus_buffer.scala 469:46] + node _T_3830 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 470:23] + node _T_3831 = eq(bus_rsp_read_tag, buf_ldfwdtag[1]) @[lsu_bus_buffer.scala 470:47] + node _T_3832 = and(_T_3830, _T_3831) @[lsu_bus_buffer.scala 470:27] + node _T_3833 = or(_T_3829, _T_3832) @[lsu_bus_buffer.scala 469:77] + node _T_3834 = and(buf_dual[1], buf_dualhi[1]) @[lsu_bus_buffer.scala 471:26] + node _T_3835 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 471:54] + node _T_3836 = not(_T_3835) @[lsu_bus_buffer.scala 471:44] + node _T_3837 = and(_T_3834, _T_3836) @[lsu_bus_buffer.scala 471:42] + node _T_3838 = and(_T_3837, buf_samedw[1]) @[lsu_bus_buffer.scala 471:58] + node _T_3839 = eq(bus_rsp_read_tag, buf_dualtag[1]) @[lsu_bus_buffer.scala 471:94] + node _T_3840 = and(_T_3838, _T_3839) @[lsu_bus_buffer.scala 471:74] + node _T_3841 = or(_T_3833, _T_3840) @[lsu_bus_buffer.scala 470:71] + node _T_3842 = and(bus_rsp_read, _T_3841) @[lsu_bus_buffer.scala 469:25] + node _T_3843 = or(_T_3828, _T_3842) @[lsu_bus_buffer.scala 468:105] + buf_resp_state_bus_en[1] <= _T_3843 @[lsu_bus_buffer.scala 468:34] + buf_state_bus_en[1] <= buf_resp_state_bus_en[1] @[lsu_bus_buffer.scala 472:29] + node _T_3844 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 473:49] + node _T_3845 = or(_T_3844, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 473:70] + buf_state_en[1] <= _T_3845 @[lsu_bus_buffer.scala 473:25] + node _T_3846 = and(buf_state_bus_en[1], bus_rsp_read) @[lsu_bus_buffer.scala 474:47] + node _T_3847 = and(_T_3846, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 474:62] + buf_data_en[1] <= _T_3847 @[lsu_bus_buffer.scala 474:24] + node _T_3848 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 475:48] + node _T_3849 = eq(bus_rsp_read_tag, UInt<3>("h01")) @[lsu_bus_buffer.scala 475:111] + node _T_3850 = and(bus_rsp_read_error, _T_3849) @[lsu_bus_buffer.scala 475:91] + node _T_3851 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 476:42] + node _T_3852 = and(bus_rsp_read_error, _T_3851) @[lsu_bus_buffer.scala 476:31] + node _T_3853 = eq(bus_rsp_read_tag, buf_ldfwdtag[1]) @[lsu_bus_buffer.scala 476:66] + node _T_3854 = and(_T_3852, _T_3853) @[lsu_bus_buffer.scala 476:46] + node _T_3855 = or(_T_3850, _T_3854) @[lsu_bus_buffer.scala 475:143] + node _T_3856 = and(bus_rsp_write_error, UInt<1>("h00")) @[lsu_bus_buffer.scala 477:32] + node _T_3857 = eq(bus_rsp_write_tag, UInt<3>("h01")) @[lsu_bus_buffer.scala 477:74] + node _T_3858 = and(_T_3856, _T_3857) @[lsu_bus_buffer.scala 477:53] + node _T_3859 = or(_T_3855, _T_3858) @[lsu_bus_buffer.scala 476:88] + node _T_3860 = and(_T_3848, _T_3859) @[lsu_bus_buffer.scala 475:68] + buf_error_en[1] <= _T_3860 @[lsu_bus_buffer.scala 475:25] + node _T_3861 = eq(buf_error_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 478:50] + node _T_3862 = and(buf_state_en[1], _T_3861) @[lsu_bus_buffer.scala 478:48] + node _T_3863 = bits(buf_addr[1], 2, 2) @[lsu_bus_buffer.scala 478:84] + node _T_3864 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 478:102] + node _T_3865 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 478:125] + node _T_3866 = mux(_T_3863, _T_3864, _T_3865) @[lsu_bus_buffer.scala 478:72] + node _T_3867 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 478:148] + node _T_3868 = mux(_T_3862, _T_3866, _T_3867) @[lsu_bus_buffer.scala 478:30] + buf_data_in[1] <= _T_3868 @[lsu_bus_buffer.scala 478:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3869 = eq(UInt<3>("h04"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3869 : @[Conditional.scala 39:67] + node _T_3870 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 481:60] + node _T_3871 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 481:86] + node _T_3872 = dshr(buf_ldfwd, buf_dualtag[1]) @[lsu_bus_buffer.scala 481:101] + node _T_3873 = bits(_T_3872, 0, 0) @[lsu_bus_buffer.scala 481:101] + node _T_3874 = or(_T_3871, _T_3873) @[lsu_bus_buffer.scala 481:90] + node _T_3875 = or(_T_3874, any_done_wait_state) @[lsu_bus_buffer.scala 481:118] + node _T_3876 = mux(_T_3875, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 481:75] + node _T_3877 = mux(_T_3870, UInt<3>("h00"), _T_3876) @[lsu_bus_buffer.scala 481:31] + buf_nxtstate[1] <= _T_3877 @[lsu_bus_buffer.scala 481:25] + node _T_3878 = eq(bus_rsp_read_tag, buf_dualtag[1]) @[lsu_bus_buffer.scala 482:66] + node _T_3879 = dshr(buf_ldfwd, buf_dualtag[1]) @[lsu_bus_buffer.scala 483:21] + node _T_3880 = bits(_T_3879, 0, 0) @[lsu_bus_buffer.scala 483:21] + node _T_3881 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[1]]) @[lsu_bus_buffer.scala 483:58] + node _T_3882 = and(_T_3880, _T_3881) @[lsu_bus_buffer.scala 483:38] + node _T_3883 = or(_T_3878, _T_3882) @[lsu_bus_buffer.scala 482:95] + node _T_3884 = and(bus_rsp_read, _T_3883) @[lsu_bus_buffer.scala 482:45] + buf_state_bus_en[1] <= _T_3884 @[lsu_bus_buffer.scala 482:29] + node _T_3885 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 484:49] + node _T_3886 = or(_T_3885, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 484:70] + buf_state_en[1] <= _T_3886 @[lsu_bus_buffer.scala 484:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3887 = eq(UInt<3>("h05"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3887 : @[Conditional.scala 39:67] + node _T_3888 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 487:60] + node _T_3889 = mux(_T_3888, UInt<3>("h00"), UInt<3>("h06")) @[lsu_bus_buffer.scala 487:31] + buf_nxtstate[1] <= _T_3889 @[lsu_bus_buffer.scala 487:25] + node _T_3890 = eq(RspPtr, UInt<2>("h01")) @[lsu_bus_buffer.scala 488:37] + node _T_3891 = eq(buf_dualtag[1], RspPtr) @[lsu_bus_buffer.scala 488:98] + node _T_3892 = and(buf_dual[1], _T_3891) @[lsu_bus_buffer.scala 488:80] + node _T_3893 = or(_T_3890, _T_3892) @[lsu_bus_buffer.scala 488:65] + node _T_3894 = or(_T_3893, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 488:112] + buf_state_en[1] <= _T_3894 @[lsu_bus_buffer.scala 488:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3895 = eq(UInt<3>("h06"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3895 : @[Conditional.scala 39:67] + buf_nxtstate[1] <= UInt<3>("h00") @[lsu_bus_buffer.scala 491:25] + buf_rst[1] <= UInt<1>("h01") @[lsu_bus_buffer.scala 492:20] + buf_state_en[1] <= UInt<1>("h01") @[lsu_bus_buffer.scala 493:25] + buf_ldfwd_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 494:25] + buf_ldfwd_en[1] <= buf_state_en[1] @[lsu_bus_buffer.scala 495:25] + skip @[Conditional.scala 39:67] + node _T_3896 = bits(buf_state_en[1], 0, 0) @[lsu_bus_buffer.scala 498:108] + reg _T_3897 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3896 : @[Reg.scala 28:19] + _T_3897 <= buf_nxtstate[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_state[1] <= _T_3897 @[lsu_bus_buffer.scala 498:18] + reg _T_3898 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 499:60] + _T_3898 <= buf_age_in_1 @[lsu_bus_buffer.scala 499:60] + buf_ageQ[1] <= _T_3898 @[lsu_bus_buffer.scala 499:17] + reg _T_3899 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 500:63] + _T_3899 <= buf_rspage_in[1] @[lsu_bus_buffer.scala 500:63] + buf_rspageQ[1] <= _T_3899 @[lsu_bus_buffer.scala 500:20] + node _T_3900 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 501:109] + reg _T_3901 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3900 : @[Reg.scala 28:19] + _T_3901 <= buf_dualtag_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualtag[1] <= _T_3901 @[lsu_bus_buffer.scala 501:20] + node _T_3902 = bits(buf_dual_in, 1, 1) @[lsu_bus_buffer.scala 502:74] + node _T_3903 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 502:107] + reg _T_3904 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3903 : @[Reg.scala 28:19] + _T_3904 <= _T_3902 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dual[1] <= _T_3904 @[lsu_bus_buffer.scala 502:17] + node _T_3905 = bits(buf_samedw_in, 1, 1) @[lsu_bus_buffer.scala 503:78] + node _T_3906 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 503:111] + reg _T_3907 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3906 : @[Reg.scala 28:19] + _T_3907 <= _T_3905 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_samedw[1] <= _T_3907 @[lsu_bus_buffer.scala 503:19] + node _T_3908 = bits(buf_nomerge_in, 1, 1) @[lsu_bus_buffer.scala 504:80] + node _T_3909 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 504:113] + reg _T_3910 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3909 : @[Reg.scala 28:19] + _T_3910 <= _T_3908 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_nomerge[1] <= _T_3910 @[lsu_bus_buffer.scala 504:20] + node _T_3911 = bits(buf_dualhi_in, 1, 1) @[lsu_bus_buffer.scala 505:78] + node _T_3912 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 505:111] + reg _T_3913 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3912 : @[Reg.scala 28:19] + _T_3913 <= _T_3911 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualhi[1] <= _T_3913 @[lsu_bus_buffer.scala 505:19] + node _T_3914 = eq(UInt<3>("h00"), buf_state[2]) @[Conditional.scala 37:30] + when _T_3914 : @[Conditional.scala 40:58] + node _T_3915 = bits(io.lsu_bus_clk_en, 0, 0) @[lsu_bus_buffer.scala 442:56] + node _T_3916 = mux(_T_3915, UInt<3>("h02"), UInt<3>("h01")) @[lsu_bus_buffer.scala 442:31] + buf_nxtstate[2] <= _T_3916 @[lsu_bus_buffer.scala 442:25] + node _T_3917 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 443:45] + node _T_3918 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 443:77] + node _T_3919 = eq(ibuf_merge_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 443:97] + node _T_3920 = and(_T_3918, _T_3919) @[lsu_bus_buffer.scala 443:95] + node _T_3921 = eq(UInt<2>("h02"), WrPtr0_r) @[lsu_bus_buffer.scala 443:117] + node _T_3922 = and(_T_3920, _T_3921) @[lsu_bus_buffer.scala 443:112] + node _T_3923 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 443:144] + node _T_3924 = eq(UInt<2>("h02"), WrPtr1_r) @[lsu_bus_buffer.scala 443:166] + node _T_3925 = and(_T_3923, _T_3924) @[lsu_bus_buffer.scala 443:161] + node _T_3926 = or(_T_3922, _T_3925) @[lsu_bus_buffer.scala 443:132] + node _T_3927 = and(_T_3917, _T_3926) @[lsu_bus_buffer.scala 443:63] + node _T_3928 = eq(UInt<2>("h02"), ibuf_tag) @[lsu_bus_buffer.scala 443:206] + node _T_3929 = and(ibuf_drain_vld, _T_3928) @[lsu_bus_buffer.scala 443:201] + node _T_3930 = or(_T_3927, _T_3929) @[lsu_bus_buffer.scala 443:183] + buf_state_en[2] <= _T_3930 @[lsu_bus_buffer.scala 443:25] + buf_wr_en[2] <= buf_state_en[2] @[lsu_bus_buffer.scala 444:22] + buf_data_en[2] <= buf_state_en[2] @[lsu_bus_buffer.scala 445:24] + node _T_3931 = eq(UInt<2>("h02"), ibuf_tag) @[lsu_bus_buffer.scala 446:52] + node _T_3932 = and(ibuf_drain_vld, _T_3931) @[lsu_bus_buffer.scala 446:47] + node _T_3933 = bits(_T_3932, 0, 0) @[lsu_bus_buffer.scala 446:73] + node _T_3934 = bits(ibuf_data_out, 31, 0) @[lsu_bus_buffer.scala 446:90] + node _T_3935 = bits(store_data_lo_r, 31, 0) @[lsu_bus_buffer.scala 446:114] + node _T_3936 = mux(_T_3933, _T_3934, _T_3935) @[lsu_bus_buffer.scala 446:30] + buf_data_in[2] <= _T_3936 @[lsu_bus_buffer.scala 446:24] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_3937 = eq(UInt<3>("h01"), buf_state[2]) @[Conditional.scala 37:30] + when _T_3937 : @[Conditional.scala 39:67] + node _T_3938 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 449:60] + node _T_3939 = mux(_T_3938, UInt<3>("h00"), UInt<3>("h02")) @[lsu_bus_buffer.scala 449:31] + buf_nxtstate[2] <= _T_3939 @[lsu_bus_buffer.scala 449:25] + node _T_3940 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 450:46] + buf_state_en[2] <= _T_3940 @[lsu_bus_buffer.scala 450:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3941 = eq(UInt<3>("h02"), buf_state[2]) @[Conditional.scala 37:30] + when _T_3941 : @[Conditional.scala 39:67] + node _T_3942 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 453:60] + node _T_3943 = and(obuf_nosend, bus_rsp_read) @[lsu_bus_buffer.scala 453:89] + node _T_3944 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 453:124] + node _T_3945 = and(_T_3943, _T_3944) @[lsu_bus_buffer.scala 453:104] + node _T_3946 = mux(_T_3945, UInt<3>("h05"), UInt<3>("h03")) @[lsu_bus_buffer.scala 453:75] + node _T_3947 = mux(_T_3942, UInt<3>("h00"), _T_3946) @[lsu_bus_buffer.scala 453:31] + buf_nxtstate[2] <= _T_3947 @[lsu_bus_buffer.scala 453:25] + node _T_3948 = eq(obuf_tag0, UInt<3>("h02")) @[lsu_bus_buffer.scala 454:48] + node _T_3949 = eq(obuf_tag1, UInt<3>("h02")) @[lsu_bus_buffer.scala 454:104] + node _T_3950 = and(obuf_merge, _T_3949) @[lsu_bus_buffer.scala 454:91] + node _T_3951 = or(_T_3948, _T_3950) @[lsu_bus_buffer.scala 454:77] + node _T_3952 = and(_T_3951, obuf_valid) @[lsu_bus_buffer.scala 454:135] + node _T_3953 = and(_T_3952, obuf_wr_enQ) @[lsu_bus_buffer.scala 454:148] + buf_cmd_state_bus_en[2] <= _T_3953 @[lsu_bus_buffer.scala 454:33] + buf_state_bus_en[2] <= buf_cmd_state_bus_en[2] @[lsu_bus_buffer.scala 455:29] + node _T_3954 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 456:49] + node _T_3955 = or(_T_3954, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 456:70] + buf_state_en[2] <= _T_3955 @[lsu_bus_buffer.scala 456:25] + buf_ldfwd_in[2] <= UInt<1>("h01") @[lsu_bus_buffer.scala 457:25] + node _T_3956 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 458:56] + node _T_3957 = eq(_T_3956, UInt<1>("h00")) @[lsu_bus_buffer.scala 458:46] + node _T_3958 = and(buf_state_en[2], _T_3957) @[lsu_bus_buffer.scala 458:44] + node _T_3959 = and(_T_3958, obuf_nosend) @[lsu_bus_buffer.scala 458:60] + node _T_3960 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 458:76] + node _T_3961 = and(_T_3959, _T_3960) @[lsu_bus_buffer.scala 458:74] + buf_ldfwd_en[2] <= _T_3961 @[lsu_bus_buffer.scala 458:25] + node _T_3962 = bits(obuf_rdrsp_tag, 1, 0) @[lsu_bus_buffer.scala 459:46] + buf_ldfwdtag_in[2] <= _T_3962 @[lsu_bus_buffer.scala 459:28] + node _T_3963 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 460:47] + node _T_3964 = and(_T_3963, obuf_nosend) @[lsu_bus_buffer.scala 460:67] + node _T_3965 = and(_T_3964, bus_rsp_read) @[lsu_bus_buffer.scala 460:81] + buf_data_en[2] <= _T_3965 @[lsu_bus_buffer.scala 460:24] + node _T_3966 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 461:48] + node _T_3967 = and(_T_3966, obuf_nosend) @[lsu_bus_buffer.scala 461:68] + node _T_3968 = and(_T_3967, bus_rsp_read_error) @[lsu_bus_buffer.scala 461:82] + buf_error_en[2] <= _T_3968 @[lsu_bus_buffer.scala 461:25] + node _T_3969 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 462:61] + node _T_3970 = bits(buf_addr[2], 2, 2) @[lsu_bus_buffer.scala 462:85] + node _T_3971 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 462:103] + node _T_3972 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 462:126] + node _T_3973 = mux(_T_3970, _T_3971, _T_3972) @[lsu_bus_buffer.scala 462:73] + node _T_3974 = mux(buf_error_en[2], _T_3969, _T_3973) @[lsu_bus_buffer.scala 462:30] + buf_data_in[2] <= _T_3974 @[lsu_bus_buffer.scala 462:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3975 = eq(UInt<3>("h03"), buf_state[2]) @[Conditional.scala 37:30] + when _T_3975 : @[Conditional.scala 39:67] + node _T_3976 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 465:67] + node _T_3977 = and(UInt<1>("h00"), bus_rsp_write_error) @[lsu_bus_buffer.scala 465:94] + node _T_3978 = eq(_T_3977, UInt<1>("h00")) @[lsu_bus_buffer.scala 465:73] + node _T_3979 = and(_T_3976, _T_3978) @[lsu_bus_buffer.scala 465:71] + node _T_3980 = or(io.dec_tlu_force_halt, _T_3979) @[lsu_bus_buffer.scala 465:55] + node _T_3981 = bits(_T_3980, 0, 0) @[lsu_bus_buffer.scala 465:125] + node _T_3982 = eq(buf_samedw[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 466:30] + node _T_3983 = and(buf_dual[2], _T_3982) @[lsu_bus_buffer.scala 466:28] + node _T_3984 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 466:57] + node _T_3985 = eq(_T_3984, UInt<1>("h00")) @[lsu_bus_buffer.scala 466:47] + node _T_3986 = and(_T_3983, _T_3985) @[lsu_bus_buffer.scala 466:45] + node _T_3987 = neq(buf_state[buf_dualtag[2]], UInt<3>("h04")) @[lsu_bus_buffer.scala 466:90] + node _T_3988 = and(_T_3986, _T_3987) @[lsu_bus_buffer.scala 466:61] + node _T_3989 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 467:27] + node _T_3990 = or(_T_3989, any_done_wait_state) @[lsu_bus_buffer.scala 467:31] + node _T_3991 = eq(buf_samedw[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 467:70] + node _T_3992 = and(buf_dual[2], _T_3991) @[lsu_bus_buffer.scala 467:68] + node _T_3993 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 467:97] + node _T_3994 = eq(_T_3993, UInt<1>("h00")) @[lsu_bus_buffer.scala 467:87] + node _T_3995 = and(_T_3992, _T_3994) @[lsu_bus_buffer.scala 467:85] + node _T_3996 = eq(buf_dualtag[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_3997 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_3998 = eq(buf_dualtag[2], UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_3999 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_4000 = eq(buf_dualtag[2], UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_4001 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_4002 = eq(buf_dualtag[2], UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_4003 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 57:129] + node _T_4004 = mux(_T_3996, _T_3997, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4005 = mux(_T_3998, _T_3999, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4006 = mux(_T_4000, _T_4001, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4007 = mux(_T_4002, _T_4003, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4008 = or(_T_4004, _T_4005) @[Mux.scala 27:72] + node _T_4009 = or(_T_4008, _T_4006) @[Mux.scala 27:72] + node _T_4010 = or(_T_4009, _T_4007) @[Mux.scala 27:72] + wire _T_4011 : UInt<1> @[Mux.scala 27:72] + _T_4011 <= _T_4010 @[Mux.scala 27:72] + node _T_4012 = and(_T_3995, _T_4011) @[lsu_bus_buffer.scala 467:101] + node _T_4013 = eq(buf_state[buf_dualtag[2]], UInt<3>("h04")) @[lsu_bus_buffer.scala 467:167] + node _T_4014 = and(_T_4012, _T_4013) @[lsu_bus_buffer.scala 467:138] + node _T_4015 = and(_T_4014, any_done_wait_state) @[lsu_bus_buffer.scala 467:187] + node _T_4016 = or(_T_3990, _T_4015) @[lsu_bus_buffer.scala 467:53] + node _T_4017 = mux(_T_4016, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 467:16] + node _T_4018 = mux(_T_3988, UInt<3>("h04"), _T_4017) @[lsu_bus_buffer.scala 466:14] + node _T_4019 = mux(_T_3981, UInt<3>("h00"), _T_4018) @[lsu_bus_buffer.scala 465:31] + buf_nxtstate[2] <= _T_4019 @[lsu_bus_buffer.scala 465:25] + node _T_4020 = eq(bus_rsp_write_tag, UInt<3>("h02")) @[lsu_bus_buffer.scala 468:73] + node _T_4021 = and(bus_rsp_write, _T_4020) @[lsu_bus_buffer.scala 468:52] + node _T_4022 = eq(bus_rsp_read_tag, UInt<3>("h02")) @[lsu_bus_buffer.scala 469:46] + node _T_4023 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 470:23] + node _T_4024 = eq(bus_rsp_read_tag, buf_ldfwdtag[2]) @[lsu_bus_buffer.scala 470:47] + node _T_4025 = and(_T_4023, _T_4024) @[lsu_bus_buffer.scala 470:27] + node _T_4026 = or(_T_4022, _T_4025) @[lsu_bus_buffer.scala 469:77] + node _T_4027 = and(buf_dual[2], buf_dualhi[2]) @[lsu_bus_buffer.scala 471:26] + node _T_4028 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 471:54] + node _T_4029 = not(_T_4028) @[lsu_bus_buffer.scala 471:44] + node _T_4030 = and(_T_4027, _T_4029) @[lsu_bus_buffer.scala 471:42] + node _T_4031 = and(_T_4030, buf_samedw[2]) @[lsu_bus_buffer.scala 471:58] + node _T_4032 = eq(bus_rsp_read_tag, buf_dualtag[2]) @[lsu_bus_buffer.scala 471:94] + node _T_4033 = and(_T_4031, _T_4032) @[lsu_bus_buffer.scala 471:74] + node _T_4034 = or(_T_4026, _T_4033) @[lsu_bus_buffer.scala 470:71] + node _T_4035 = and(bus_rsp_read, _T_4034) @[lsu_bus_buffer.scala 469:25] + node _T_4036 = or(_T_4021, _T_4035) @[lsu_bus_buffer.scala 468:105] + buf_resp_state_bus_en[2] <= _T_4036 @[lsu_bus_buffer.scala 468:34] + buf_state_bus_en[2] <= buf_resp_state_bus_en[2] @[lsu_bus_buffer.scala 472:29] + node _T_4037 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 473:49] + node _T_4038 = or(_T_4037, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 473:70] + buf_state_en[2] <= _T_4038 @[lsu_bus_buffer.scala 473:25] + node _T_4039 = and(buf_state_bus_en[2], bus_rsp_read) @[lsu_bus_buffer.scala 474:47] + node _T_4040 = and(_T_4039, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 474:62] + buf_data_en[2] <= _T_4040 @[lsu_bus_buffer.scala 474:24] + node _T_4041 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 475:48] + node _T_4042 = eq(bus_rsp_read_tag, UInt<3>("h02")) @[lsu_bus_buffer.scala 475:111] + node _T_4043 = and(bus_rsp_read_error, _T_4042) @[lsu_bus_buffer.scala 475:91] + node _T_4044 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 476:42] + node _T_4045 = and(bus_rsp_read_error, _T_4044) @[lsu_bus_buffer.scala 476:31] + node _T_4046 = eq(bus_rsp_read_tag, buf_ldfwdtag[2]) @[lsu_bus_buffer.scala 476:66] + node _T_4047 = and(_T_4045, _T_4046) @[lsu_bus_buffer.scala 476:46] + node _T_4048 = or(_T_4043, _T_4047) @[lsu_bus_buffer.scala 475:143] + node _T_4049 = and(bus_rsp_write_error, UInt<1>("h00")) @[lsu_bus_buffer.scala 477:32] + node _T_4050 = eq(bus_rsp_write_tag, UInt<3>("h02")) @[lsu_bus_buffer.scala 477:74] + node _T_4051 = and(_T_4049, _T_4050) @[lsu_bus_buffer.scala 477:53] + node _T_4052 = or(_T_4048, _T_4051) @[lsu_bus_buffer.scala 476:88] + node _T_4053 = and(_T_4041, _T_4052) @[lsu_bus_buffer.scala 475:68] + buf_error_en[2] <= _T_4053 @[lsu_bus_buffer.scala 475:25] + node _T_4054 = eq(buf_error_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 478:50] + node _T_4055 = and(buf_state_en[2], _T_4054) @[lsu_bus_buffer.scala 478:48] + node _T_4056 = bits(buf_addr[2], 2, 2) @[lsu_bus_buffer.scala 478:84] + node _T_4057 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 478:102] + node _T_4058 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 478:125] + node _T_4059 = mux(_T_4056, _T_4057, _T_4058) @[lsu_bus_buffer.scala 478:72] + node _T_4060 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 478:148] + node _T_4061 = mux(_T_4055, _T_4059, _T_4060) @[lsu_bus_buffer.scala 478:30] + buf_data_in[2] <= _T_4061 @[lsu_bus_buffer.scala 478:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4062 = eq(UInt<3>("h04"), buf_state[2]) @[Conditional.scala 37:30] + when _T_4062 : @[Conditional.scala 39:67] + node _T_4063 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 481:60] + node _T_4064 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 481:86] + node _T_4065 = dshr(buf_ldfwd, buf_dualtag[2]) @[lsu_bus_buffer.scala 481:101] + node _T_4066 = bits(_T_4065, 0, 0) @[lsu_bus_buffer.scala 481:101] + node _T_4067 = or(_T_4064, _T_4066) @[lsu_bus_buffer.scala 481:90] + node _T_4068 = or(_T_4067, any_done_wait_state) @[lsu_bus_buffer.scala 481:118] + node _T_4069 = mux(_T_4068, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 481:75] + node _T_4070 = mux(_T_4063, UInt<3>("h00"), _T_4069) @[lsu_bus_buffer.scala 481:31] + buf_nxtstate[2] <= _T_4070 @[lsu_bus_buffer.scala 481:25] + node _T_4071 = eq(bus_rsp_read_tag, buf_dualtag[2]) @[lsu_bus_buffer.scala 482:66] + node _T_4072 = dshr(buf_ldfwd, buf_dualtag[2]) @[lsu_bus_buffer.scala 483:21] + node _T_4073 = bits(_T_4072, 0, 0) @[lsu_bus_buffer.scala 483:21] + node _T_4074 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[2]]) @[lsu_bus_buffer.scala 483:58] + node _T_4075 = and(_T_4073, _T_4074) @[lsu_bus_buffer.scala 483:38] + node _T_4076 = or(_T_4071, _T_4075) @[lsu_bus_buffer.scala 482:95] + node _T_4077 = and(bus_rsp_read, _T_4076) @[lsu_bus_buffer.scala 482:45] + buf_state_bus_en[2] <= _T_4077 @[lsu_bus_buffer.scala 482:29] + node _T_4078 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 484:49] + node _T_4079 = or(_T_4078, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 484:70] + buf_state_en[2] <= _T_4079 @[lsu_bus_buffer.scala 484:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4080 = eq(UInt<3>("h05"), buf_state[2]) @[Conditional.scala 37:30] + when _T_4080 : @[Conditional.scala 39:67] + node _T_4081 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 487:60] + node _T_4082 = mux(_T_4081, UInt<3>("h00"), UInt<3>("h06")) @[lsu_bus_buffer.scala 487:31] + buf_nxtstate[2] <= _T_4082 @[lsu_bus_buffer.scala 487:25] + node _T_4083 = eq(RspPtr, UInt<2>("h02")) @[lsu_bus_buffer.scala 488:37] + node _T_4084 = eq(buf_dualtag[2], RspPtr) @[lsu_bus_buffer.scala 488:98] + node _T_4085 = and(buf_dual[2], _T_4084) @[lsu_bus_buffer.scala 488:80] + node _T_4086 = or(_T_4083, _T_4085) @[lsu_bus_buffer.scala 488:65] + node _T_4087 = or(_T_4086, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 488:112] + buf_state_en[2] <= _T_4087 @[lsu_bus_buffer.scala 488:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4088 = eq(UInt<3>("h06"), buf_state[2]) @[Conditional.scala 37:30] + when _T_4088 : @[Conditional.scala 39:67] + buf_nxtstate[2] <= UInt<3>("h00") @[lsu_bus_buffer.scala 491:25] + buf_rst[2] <= UInt<1>("h01") @[lsu_bus_buffer.scala 492:20] + buf_state_en[2] <= UInt<1>("h01") @[lsu_bus_buffer.scala 493:25] + buf_ldfwd_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 494:25] + buf_ldfwd_en[2] <= buf_state_en[2] @[lsu_bus_buffer.scala 495:25] + skip @[Conditional.scala 39:67] + node _T_4089 = bits(buf_state_en[2], 0, 0) @[lsu_bus_buffer.scala 498:108] + reg _T_4090 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4089 : @[Reg.scala 28:19] + _T_4090 <= buf_nxtstate[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_state[2] <= _T_4090 @[lsu_bus_buffer.scala 498:18] + reg _T_4091 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 499:60] + _T_4091 <= buf_age_in_2 @[lsu_bus_buffer.scala 499:60] + buf_ageQ[2] <= _T_4091 @[lsu_bus_buffer.scala 499:17] + reg _T_4092 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 500:63] + _T_4092 <= buf_rspage_in[2] @[lsu_bus_buffer.scala 500:63] + buf_rspageQ[2] <= _T_4092 @[lsu_bus_buffer.scala 500:20] + node _T_4093 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 501:109] + reg _T_4094 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4093 : @[Reg.scala 28:19] + _T_4094 <= buf_dualtag_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualtag[2] <= _T_4094 @[lsu_bus_buffer.scala 501:20] + node _T_4095 = bits(buf_dual_in, 2, 2) @[lsu_bus_buffer.scala 502:74] + node _T_4096 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 502:107] + reg _T_4097 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4096 : @[Reg.scala 28:19] + _T_4097 <= _T_4095 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dual[2] <= _T_4097 @[lsu_bus_buffer.scala 502:17] + node _T_4098 = bits(buf_samedw_in, 2, 2) @[lsu_bus_buffer.scala 503:78] + node _T_4099 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 503:111] + reg _T_4100 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4099 : @[Reg.scala 28:19] + _T_4100 <= _T_4098 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_samedw[2] <= _T_4100 @[lsu_bus_buffer.scala 503:19] + node _T_4101 = bits(buf_nomerge_in, 2, 2) @[lsu_bus_buffer.scala 504:80] + node _T_4102 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 504:113] + reg _T_4103 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4102 : @[Reg.scala 28:19] + _T_4103 <= _T_4101 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_nomerge[2] <= _T_4103 @[lsu_bus_buffer.scala 504:20] + node _T_4104 = bits(buf_dualhi_in, 2, 2) @[lsu_bus_buffer.scala 505:78] + node _T_4105 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 505:111] + reg _T_4106 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4105 : @[Reg.scala 28:19] + _T_4106 <= _T_4104 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualhi[2] <= _T_4106 @[lsu_bus_buffer.scala 505:19] + node _T_4107 = eq(UInt<3>("h00"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4107 : @[Conditional.scala 40:58] + node _T_4108 = bits(io.lsu_bus_clk_en, 0, 0) @[lsu_bus_buffer.scala 442:56] + node _T_4109 = mux(_T_4108, UInt<3>("h02"), UInt<3>("h01")) @[lsu_bus_buffer.scala 442:31] + buf_nxtstate[3] <= _T_4109 @[lsu_bus_buffer.scala 442:25] + node _T_4110 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 443:45] + node _T_4111 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 443:77] + node _T_4112 = eq(ibuf_merge_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 443:97] + node _T_4113 = and(_T_4111, _T_4112) @[lsu_bus_buffer.scala 443:95] + node _T_4114 = eq(UInt<2>("h03"), WrPtr0_r) @[lsu_bus_buffer.scala 443:117] + node _T_4115 = and(_T_4113, _T_4114) @[lsu_bus_buffer.scala 443:112] + node _T_4116 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 443:144] + node _T_4117 = eq(UInt<2>("h03"), WrPtr1_r) @[lsu_bus_buffer.scala 443:166] + node _T_4118 = and(_T_4116, _T_4117) @[lsu_bus_buffer.scala 443:161] + node _T_4119 = or(_T_4115, _T_4118) @[lsu_bus_buffer.scala 443:132] + node _T_4120 = and(_T_4110, _T_4119) @[lsu_bus_buffer.scala 443:63] + node _T_4121 = eq(UInt<2>("h03"), ibuf_tag) @[lsu_bus_buffer.scala 443:206] + node _T_4122 = and(ibuf_drain_vld, _T_4121) @[lsu_bus_buffer.scala 443:201] + node _T_4123 = or(_T_4120, _T_4122) @[lsu_bus_buffer.scala 443:183] + buf_state_en[3] <= _T_4123 @[lsu_bus_buffer.scala 443:25] + buf_wr_en[3] <= buf_state_en[3] @[lsu_bus_buffer.scala 444:22] + buf_data_en[3] <= buf_state_en[3] @[lsu_bus_buffer.scala 445:24] + node _T_4124 = eq(UInt<2>("h03"), ibuf_tag) @[lsu_bus_buffer.scala 446:52] + node _T_4125 = and(ibuf_drain_vld, _T_4124) @[lsu_bus_buffer.scala 446:47] + node _T_4126 = bits(_T_4125, 0, 0) @[lsu_bus_buffer.scala 446:73] + node _T_4127 = bits(ibuf_data_out, 31, 0) @[lsu_bus_buffer.scala 446:90] + node _T_4128 = bits(store_data_lo_r, 31, 0) @[lsu_bus_buffer.scala 446:114] + node _T_4129 = mux(_T_4126, _T_4127, _T_4128) @[lsu_bus_buffer.scala 446:30] + buf_data_in[3] <= _T_4129 @[lsu_bus_buffer.scala 446:24] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_4130 = eq(UInt<3>("h01"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4130 : @[Conditional.scala 39:67] + node _T_4131 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 449:60] + node _T_4132 = mux(_T_4131, UInt<3>("h00"), UInt<3>("h02")) @[lsu_bus_buffer.scala 449:31] + buf_nxtstate[3] <= _T_4132 @[lsu_bus_buffer.scala 449:25] + node _T_4133 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 450:46] + buf_state_en[3] <= _T_4133 @[lsu_bus_buffer.scala 450:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4134 = eq(UInt<3>("h02"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4134 : @[Conditional.scala 39:67] + node _T_4135 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 453:60] + node _T_4136 = and(obuf_nosend, bus_rsp_read) @[lsu_bus_buffer.scala 453:89] + node _T_4137 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 453:124] + node _T_4138 = and(_T_4136, _T_4137) @[lsu_bus_buffer.scala 453:104] + node _T_4139 = mux(_T_4138, UInt<3>("h05"), UInt<3>("h03")) @[lsu_bus_buffer.scala 453:75] + node _T_4140 = mux(_T_4135, UInt<3>("h00"), _T_4139) @[lsu_bus_buffer.scala 453:31] + buf_nxtstate[3] <= _T_4140 @[lsu_bus_buffer.scala 453:25] + node _T_4141 = eq(obuf_tag0, UInt<3>("h03")) @[lsu_bus_buffer.scala 454:48] + node _T_4142 = eq(obuf_tag1, UInt<3>("h03")) @[lsu_bus_buffer.scala 454:104] + node _T_4143 = and(obuf_merge, _T_4142) @[lsu_bus_buffer.scala 454:91] + node _T_4144 = or(_T_4141, _T_4143) @[lsu_bus_buffer.scala 454:77] + node _T_4145 = and(_T_4144, obuf_valid) @[lsu_bus_buffer.scala 454:135] + node _T_4146 = and(_T_4145, obuf_wr_enQ) @[lsu_bus_buffer.scala 454:148] + buf_cmd_state_bus_en[3] <= _T_4146 @[lsu_bus_buffer.scala 454:33] + buf_state_bus_en[3] <= buf_cmd_state_bus_en[3] @[lsu_bus_buffer.scala 455:29] + node _T_4147 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 456:49] + node _T_4148 = or(_T_4147, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 456:70] + buf_state_en[3] <= _T_4148 @[lsu_bus_buffer.scala 456:25] + buf_ldfwd_in[3] <= UInt<1>("h01") @[lsu_bus_buffer.scala 457:25] + node _T_4149 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 458:56] + node _T_4150 = eq(_T_4149, UInt<1>("h00")) @[lsu_bus_buffer.scala 458:46] + node _T_4151 = and(buf_state_en[3], _T_4150) @[lsu_bus_buffer.scala 458:44] + node _T_4152 = and(_T_4151, obuf_nosend) @[lsu_bus_buffer.scala 458:60] + node _T_4153 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 458:76] + node _T_4154 = and(_T_4152, _T_4153) @[lsu_bus_buffer.scala 458:74] + buf_ldfwd_en[3] <= _T_4154 @[lsu_bus_buffer.scala 458:25] + node _T_4155 = bits(obuf_rdrsp_tag, 1, 0) @[lsu_bus_buffer.scala 459:46] + buf_ldfwdtag_in[3] <= _T_4155 @[lsu_bus_buffer.scala 459:28] + node _T_4156 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 460:47] + node _T_4157 = and(_T_4156, obuf_nosend) @[lsu_bus_buffer.scala 460:67] + node _T_4158 = and(_T_4157, bus_rsp_read) @[lsu_bus_buffer.scala 460:81] + buf_data_en[3] <= _T_4158 @[lsu_bus_buffer.scala 460:24] + node _T_4159 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 461:48] + node _T_4160 = and(_T_4159, obuf_nosend) @[lsu_bus_buffer.scala 461:68] + node _T_4161 = and(_T_4160, bus_rsp_read_error) @[lsu_bus_buffer.scala 461:82] + buf_error_en[3] <= _T_4161 @[lsu_bus_buffer.scala 461:25] + node _T_4162 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 462:61] + node _T_4163 = bits(buf_addr[3], 2, 2) @[lsu_bus_buffer.scala 462:85] + node _T_4164 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 462:103] + node _T_4165 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 462:126] + node _T_4166 = mux(_T_4163, _T_4164, _T_4165) @[lsu_bus_buffer.scala 462:73] + node _T_4167 = mux(buf_error_en[3], _T_4162, _T_4166) @[lsu_bus_buffer.scala 462:30] + buf_data_in[3] <= _T_4167 @[lsu_bus_buffer.scala 462:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4168 = eq(UInt<3>("h03"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4168 : @[Conditional.scala 39:67] + node _T_4169 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 465:67] + node _T_4170 = and(UInt<1>("h00"), bus_rsp_write_error) @[lsu_bus_buffer.scala 465:94] + node _T_4171 = eq(_T_4170, UInt<1>("h00")) @[lsu_bus_buffer.scala 465:73] + node _T_4172 = and(_T_4169, _T_4171) @[lsu_bus_buffer.scala 465:71] + node _T_4173 = or(io.dec_tlu_force_halt, _T_4172) @[lsu_bus_buffer.scala 465:55] + node _T_4174 = bits(_T_4173, 0, 0) @[lsu_bus_buffer.scala 465:125] + node _T_4175 = eq(buf_samedw[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 466:30] + node _T_4176 = and(buf_dual[3], _T_4175) @[lsu_bus_buffer.scala 466:28] + node _T_4177 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 466:57] + node _T_4178 = eq(_T_4177, UInt<1>("h00")) @[lsu_bus_buffer.scala 466:47] + node _T_4179 = and(_T_4176, _T_4178) @[lsu_bus_buffer.scala 466:45] + node _T_4180 = neq(buf_state[buf_dualtag[3]], UInt<3>("h04")) @[lsu_bus_buffer.scala 466:90] + node _T_4181 = and(_T_4179, _T_4180) @[lsu_bus_buffer.scala 466:61] + node _T_4182 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 467:27] + node _T_4183 = or(_T_4182, any_done_wait_state) @[lsu_bus_buffer.scala 467:31] + node _T_4184 = eq(buf_samedw[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 467:70] + node _T_4185 = and(buf_dual[3], _T_4184) @[lsu_bus_buffer.scala 467:68] + node _T_4186 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 467:97] + node _T_4187 = eq(_T_4186, UInt<1>("h00")) @[lsu_bus_buffer.scala 467:87] + node _T_4188 = and(_T_4185, _T_4187) @[lsu_bus_buffer.scala 467:85] + node _T_4189 = eq(buf_dualtag[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_4190 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_4191 = eq(buf_dualtag[3], UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_4192 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_4193 = eq(buf_dualtag[3], UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_4194 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_4195 = eq(buf_dualtag[3], UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_4196 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 57:129] + node _T_4197 = mux(_T_4189, _T_4190, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4198 = mux(_T_4191, _T_4192, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4199 = mux(_T_4193, _T_4194, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4200 = mux(_T_4195, _T_4196, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4201 = or(_T_4197, _T_4198) @[Mux.scala 27:72] + node _T_4202 = or(_T_4201, _T_4199) @[Mux.scala 27:72] + node _T_4203 = or(_T_4202, _T_4200) @[Mux.scala 27:72] + wire _T_4204 : UInt<1> @[Mux.scala 27:72] + _T_4204 <= _T_4203 @[Mux.scala 27:72] + node _T_4205 = and(_T_4188, _T_4204) @[lsu_bus_buffer.scala 467:101] + node _T_4206 = eq(buf_state[buf_dualtag[3]], UInt<3>("h04")) @[lsu_bus_buffer.scala 467:167] + node _T_4207 = and(_T_4205, _T_4206) @[lsu_bus_buffer.scala 467:138] + node _T_4208 = and(_T_4207, any_done_wait_state) @[lsu_bus_buffer.scala 467:187] + node _T_4209 = or(_T_4183, _T_4208) @[lsu_bus_buffer.scala 467:53] + node _T_4210 = mux(_T_4209, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 467:16] + node _T_4211 = mux(_T_4181, UInt<3>("h04"), _T_4210) @[lsu_bus_buffer.scala 466:14] + node _T_4212 = mux(_T_4174, UInt<3>("h00"), _T_4211) @[lsu_bus_buffer.scala 465:31] + buf_nxtstate[3] <= _T_4212 @[lsu_bus_buffer.scala 465:25] + node _T_4213 = eq(bus_rsp_write_tag, UInt<3>("h03")) @[lsu_bus_buffer.scala 468:73] + node _T_4214 = and(bus_rsp_write, _T_4213) @[lsu_bus_buffer.scala 468:52] + node _T_4215 = eq(bus_rsp_read_tag, UInt<3>("h03")) @[lsu_bus_buffer.scala 469:46] + node _T_4216 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 470:23] + node _T_4217 = eq(bus_rsp_read_tag, buf_ldfwdtag[3]) @[lsu_bus_buffer.scala 470:47] + node _T_4218 = and(_T_4216, _T_4217) @[lsu_bus_buffer.scala 470:27] + node _T_4219 = or(_T_4215, _T_4218) @[lsu_bus_buffer.scala 469:77] + node _T_4220 = and(buf_dual[3], buf_dualhi[3]) @[lsu_bus_buffer.scala 471:26] + node _T_4221 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 471:54] + node _T_4222 = not(_T_4221) @[lsu_bus_buffer.scala 471:44] + node _T_4223 = and(_T_4220, _T_4222) @[lsu_bus_buffer.scala 471:42] + node _T_4224 = and(_T_4223, buf_samedw[3]) @[lsu_bus_buffer.scala 471:58] + node _T_4225 = eq(bus_rsp_read_tag, buf_dualtag[3]) @[lsu_bus_buffer.scala 471:94] + node _T_4226 = and(_T_4224, _T_4225) @[lsu_bus_buffer.scala 471:74] + node _T_4227 = or(_T_4219, _T_4226) @[lsu_bus_buffer.scala 470:71] + node _T_4228 = and(bus_rsp_read, _T_4227) @[lsu_bus_buffer.scala 469:25] + node _T_4229 = or(_T_4214, _T_4228) @[lsu_bus_buffer.scala 468:105] + buf_resp_state_bus_en[3] <= _T_4229 @[lsu_bus_buffer.scala 468:34] + buf_state_bus_en[3] <= buf_resp_state_bus_en[3] @[lsu_bus_buffer.scala 472:29] + node _T_4230 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 473:49] + node _T_4231 = or(_T_4230, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 473:70] + buf_state_en[3] <= _T_4231 @[lsu_bus_buffer.scala 473:25] + node _T_4232 = and(buf_state_bus_en[3], bus_rsp_read) @[lsu_bus_buffer.scala 474:47] + node _T_4233 = and(_T_4232, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 474:62] + buf_data_en[3] <= _T_4233 @[lsu_bus_buffer.scala 474:24] + node _T_4234 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 475:48] + node _T_4235 = eq(bus_rsp_read_tag, UInt<3>("h03")) @[lsu_bus_buffer.scala 475:111] + node _T_4236 = and(bus_rsp_read_error, _T_4235) @[lsu_bus_buffer.scala 475:91] + node _T_4237 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 476:42] + node _T_4238 = and(bus_rsp_read_error, _T_4237) @[lsu_bus_buffer.scala 476:31] + node _T_4239 = eq(bus_rsp_read_tag, buf_ldfwdtag[3]) @[lsu_bus_buffer.scala 476:66] + node _T_4240 = and(_T_4238, _T_4239) @[lsu_bus_buffer.scala 476:46] + node _T_4241 = or(_T_4236, _T_4240) @[lsu_bus_buffer.scala 475:143] + node _T_4242 = and(bus_rsp_write_error, UInt<1>("h00")) @[lsu_bus_buffer.scala 477:32] + node _T_4243 = eq(bus_rsp_write_tag, UInt<3>("h03")) @[lsu_bus_buffer.scala 477:74] + node _T_4244 = and(_T_4242, _T_4243) @[lsu_bus_buffer.scala 477:53] + node _T_4245 = or(_T_4241, _T_4244) @[lsu_bus_buffer.scala 476:88] + node _T_4246 = and(_T_4234, _T_4245) @[lsu_bus_buffer.scala 475:68] + buf_error_en[3] <= _T_4246 @[lsu_bus_buffer.scala 475:25] + node _T_4247 = eq(buf_error_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 478:50] + node _T_4248 = and(buf_state_en[3], _T_4247) @[lsu_bus_buffer.scala 478:48] + node _T_4249 = bits(buf_addr[3], 2, 2) @[lsu_bus_buffer.scala 478:84] + node _T_4250 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 478:102] + node _T_4251 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 478:125] + node _T_4252 = mux(_T_4249, _T_4250, _T_4251) @[lsu_bus_buffer.scala 478:72] + node _T_4253 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 478:148] + node _T_4254 = mux(_T_4248, _T_4252, _T_4253) @[lsu_bus_buffer.scala 478:30] + buf_data_in[3] <= _T_4254 @[lsu_bus_buffer.scala 478:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4255 = eq(UInt<3>("h04"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4255 : @[Conditional.scala 39:67] + node _T_4256 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 481:60] + node _T_4257 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 481:86] + node _T_4258 = dshr(buf_ldfwd, buf_dualtag[3]) @[lsu_bus_buffer.scala 481:101] + node _T_4259 = bits(_T_4258, 0, 0) @[lsu_bus_buffer.scala 481:101] + node _T_4260 = or(_T_4257, _T_4259) @[lsu_bus_buffer.scala 481:90] + node _T_4261 = or(_T_4260, any_done_wait_state) @[lsu_bus_buffer.scala 481:118] + node _T_4262 = mux(_T_4261, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 481:75] + node _T_4263 = mux(_T_4256, UInt<3>("h00"), _T_4262) @[lsu_bus_buffer.scala 481:31] + buf_nxtstate[3] <= _T_4263 @[lsu_bus_buffer.scala 481:25] + node _T_4264 = eq(bus_rsp_read_tag, buf_dualtag[3]) @[lsu_bus_buffer.scala 482:66] + node _T_4265 = dshr(buf_ldfwd, buf_dualtag[3]) @[lsu_bus_buffer.scala 483:21] + node _T_4266 = bits(_T_4265, 0, 0) @[lsu_bus_buffer.scala 483:21] + node _T_4267 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[3]]) @[lsu_bus_buffer.scala 483:58] + node _T_4268 = and(_T_4266, _T_4267) @[lsu_bus_buffer.scala 483:38] + node _T_4269 = or(_T_4264, _T_4268) @[lsu_bus_buffer.scala 482:95] + node _T_4270 = and(bus_rsp_read, _T_4269) @[lsu_bus_buffer.scala 482:45] + buf_state_bus_en[3] <= _T_4270 @[lsu_bus_buffer.scala 482:29] + node _T_4271 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 484:49] + node _T_4272 = or(_T_4271, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 484:70] + buf_state_en[3] <= _T_4272 @[lsu_bus_buffer.scala 484:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4273 = eq(UInt<3>("h05"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4273 : @[Conditional.scala 39:67] + node _T_4274 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 487:60] + node _T_4275 = mux(_T_4274, UInt<3>("h00"), UInt<3>("h06")) @[lsu_bus_buffer.scala 487:31] + buf_nxtstate[3] <= _T_4275 @[lsu_bus_buffer.scala 487:25] + node _T_4276 = eq(RspPtr, UInt<2>("h03")) @[lsu_bus_buffer.scala 488:37] + node _T_4277 = eq(buf_dualtag[3], RspPtr) @[lsu_bus_buffer.scala 488:98] + node _T_4278 = and(buf_dual[3], _T_4277) @[lsu_bus_buffer.scala 488:80] + node _T_4279 = or(_T_4276, _T_4278) @[lsu_bus_buffer.scala 488:65] + node _T_4280 = or(_T_4279, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 488:112] + buf_state_en[3] <= _T_4280 @[lsu_bus_buffer.scala 488:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4281 = eq(UInt<3>("h06"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4281 : @[Conditional.scala 39:67] + buf_nxtstate[3] <= UInt<3>("h00") @[lsu_bus_buffer.scala 491:25] + buf_rst[3] <= UInt<1>("h01") @[lsu_bus_buffer.scala 492:20] + buf_state_en[3] <= UInt<1>("h01") @[lsu_bus_buffer.scala 493:25] + buf_ldfwd_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 494:25] + buf_ldfwd_en[3] <= buf_state_en[3] @[lsu_bus_buffer.scala 495:25] + skip @[Conditional.scala 39:67] + node _T_4282 = bits(buf_state_en[3], 0, 0) @[lsu_bus_buffer.scala 498:108] + reg _T_4283 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4282 : @[Reg.scala 28:19] + _T_4283 <= buf_nxtstate[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_state[3] <= _T_4283 @[lsu_bus_buffer.scala 498:18] + reg _T_4284 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 499:60] + _T_4284 <= buf_age_in_3 @[lsu_bus_buffer.scala 499:60] + buf_ageQ[3] <= _T_4284 @[lsu_bus_buffer.scala 499:17] + reg _T_4285 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 500:63] + _T_4285 <= buf_rspage_in[3] @[lsu_bus_buffer.scala 500:63] + buf_rspageQ[3] <= _T_4285 @[lsu_bus_buffer.scala 500:20] + node _T_4286 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 501:109] + reg _T_4287 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4286 : @[Reg.scala 28:19] + _T_4287 <= buf_dualtag_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualtag[3] <= _T_4287 @[lsu_bus_buffer.scala 501:20] + node _T_4288 = bits(buf_dual_in, 3, 3) @[lsu_bus_buffer.scala 502:74] + node _T_4289 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 502:107] + reg _T_4290 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4289 : @[Reg.scala 28:19] + _T_4290 <= _T_4288 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dual[3] <= _T_4290 @[lsu_bus_buffer.scala 502:17] + node _T_4291 = bits(buf_samedw_in, 3, 3) @[lsu_bus_buffer.scala 503:78] + node _T_4292 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 503:111] + reg _T_4293 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4292 : @[Reg.scala 28:19] + _T_4293 <= _T_4291 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_samedw[3] <= _T_4293 @[lsu_bus_buffer.scala 503:19] + node _T_4294 = bits(buf_nomerge_in, 3, 3) @[lsu_bus_buffer.scala 504:80] + node _T_4295 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 504:113] + reg _T_4296 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4295 : @[Reg.scala 28:19] + _T_4296 <= _T_4294 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_nomerge[3] <= _T_4296 @[lsu_bus_buffer.scala 504:20] + node _T_4297 = bits(buf_dualhi_in, 3, 3) @[lsu_bus_buffer.scala 505:78] + node _T_4298 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 505:111] + reg _T_4299 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4298 : @[Reg.scala 28:19] + _T_4299 <= _T_4297 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualhi[3] <= _T_4299 @[lsu_bus_buffer.scala 505:19] + node _T_4300 = bits(buf_ldfwd_en[0], 0, 0) @[lsu_bus_buffer.scala 508:131] + reg _T_4301 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4300 : @[Reg.scala 28:19] + _T_4301 <= buf_ldfwd_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4302 = bits(buf_ldfwd_en[1], 0, 0) @[lsu_bus_buffer.scala 508:131] + reg _T_4303 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4302 : @[Reg.scala 28:19] + _T_4303 <= buf_ldfwd_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4304 = bits(buf_ldfwd_en[2], 0, 0) @[lsu_bus_buffer.scala 508:131] + reg _T_4305 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4304 : @[Reg.scala 28:19] + _T_4305 <= buf_ldfwd_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4306 = bits(buf_ldfwd_en[3], 0, 0) @[lsu_bus_buffer.scala 508:131] + reg _T_4307 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4306 : @[Reg.scala 28:19] + _T_4307 <= buf_ldfwd_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4308 = cat(_T_4307, _T_4305) @[Cat.scala 29:58] + node _T_4309 = cat(_T_4308, _T_4303) @[Cat.scala 29:58] + node _T_4310 = cat(_T_4309, _T_4301) @[Cat.scala 29:58] + buf_ldfwd <= _T_4310 @[lsu_bus_buffer.scala 508:13] + node _T_4311 = bits(buf_ldfwd_en[0], 0, 0) @[lsu_bus_buffer.scala 509:132] + reg _T_4312 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4311 : @[Reg.scala 28:19] + _T_4312 <= buf_ldfwdtag_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4313 = bits(buf_ldfwd_en[1], 0, 0) @[lsu_bus_buffer.scala 509:132] + reg _T_4314 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4313 : @[Reg.scala 28:19] + _T_4314 <= buf_ldfwdtag_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4315 = bits(buf_ldfwd_en[2], 0, 0) @[lsu_bus_buffer.scala 509:132] + reg _T_4316 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4315 : @[Reg.scala 28:19] + _T_4316 <= buf_ldfwdtag_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4317 = bits(buf_ldfwd_en[3], 0, 0) @[lsu_bus_buffer.scala 509:132] + reg _T_4318 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4317 : @[Reg.scala 28:19] + _T_4318 <= buf_ldfwdtag_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_ldfwdtag[0] <= _T_4312 @[lsu_bus_buffer.scala 509:16] + buf_ldfwdtag[1] <= _T_4314 @[lsu_bus_buffer.scala 509:16] + buf_ldfwdtag[2] <= _T_4316 @[lsu_bus_buffer.scala 509:16] + buf_ldfwdtag[3] <= _T_4318 @[lsu_bus_buffer.scala 509:16] + node _T_4319 = bits(buf_sideeffect_in, 0, 0) @[lsu_bus_buffer.scala 510:105] + node _T_4320 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 510:138] + reg _T_4321 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4320 : @[Reg.scala 28:19] + _T_4321 <= _T_4319 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4322 = bits(buf_sideeffect_in, 1, 1) @[lsu_bus_buffer.scala 510:105] + node _T_4323 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 510:138] + reg _T_4324 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4323 : @[Reg.scala 28:19] + _T_4324 <= _T_4322 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4325 = bits(buf_sideeffect_in, 2, 2) @[lsu_bus_buffer.scala 510:105] + node _T_4326 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 510:138] + reg _T_4327 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4326 : @[Reg.scala 28:19] + _T_4327 <= _T_4325 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4328 = bits(buf_sideeffect_in, 3, 3) @[lsu_bus_buffer.scala 510:105] + node _T_4329 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 510:138] + reg _T_4330 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4329 : @[Reg.scala 28:19] + _T_4330 <= _T_4328 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4331 = cat(_T_4330, _T_4327) @[Cat.scala 29:58] + node _T_4332 = cat(_T_4331, _T_4324) @[Cat.scala 29:58] + node _T_4333 = cat(_T_4332, _T_4321) @[Cat.scala 29:58] + buf_sideeffect <= _T_4333 @[lsu_bus_buffer.scala 510:18] + node _T_4334 = bits(buf_unsign_in, 0, 0) @[lsu_bus_buffer.scala 511:97] + node _T_4335 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 511:130] + reg _T_4336 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4335 : @[Reg.scala 28:19] + _T_4336 <= _T_4334 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4337 = bits(buf_unsign_in, 1, 1) @[lsu_bus_buffer.scala 511:97] + node _T_4338 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 511:130] + reg _T_4339 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4338 : @[Reg.scala 28:19] + _T_4339 <= _T_4337 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4340 = bits(buf_unsign_in, 2, 2) @[lsu_bus_buffer.scala 511:97] + node _T_4341 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 511:130] + reg _T_4342 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4341 : @[Reg.scala 28:19] + _T_4342 <= _T_4340 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4343 = bits(buf_unsign_in, 3, 3) @[lsu_bus_buffer.scala 511:97] + node _T_4344 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 511:130] + reg _T_4345 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4344 : @[Reg.scala 28:19] + _T_4345 <= _T_4343 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4346 = cat(_T_4345, _T_4342) @[Cat.scala 29:58] + node _T_4347 = cat(_T_4346, _T_4339) @[Cat.scala 29:58] + node _T_4348 = cat(_T_4347, _T_4336) @[Cat.scala 29:58] + buf_unsign <= _T_4348 @[lsu_bus_buffer.scala 511:14] + node _T_4349 = bits(buf_write_in, 0, 0) @[lsu_bus_buffer.scala 512:95] + node _T_4350 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 512:128] + reg _T_4351 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4350 : @[Reg.scala 28:19] + _T_4351 <= _T_4349 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4352 = bits(buf_write_in, 1, 1) @[lsu_bus_buffer.scala 512:95] + node _T_4353 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 512:128] + reg _T_4354 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4353 : @[Reg.scala 28:19] + _T_4354 <= _T_4352 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4355 = bits(buf_write_in, 2, 2) @[lsu_bus_buffer.scala 512:95] + node _T_4356 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 512:128] + reg _T_4357 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4356 : @[Reg.scala 28:19] + _T_4357 <= _T_4355 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4358 = bits(buf_write_in, 3, 3) @[lsu_bus_buffer.scala 512:95] + node _T_4359 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 512:128] + reg _T_4360 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4359 : @[Reg.scala 28:19] + _T_4360 <= _T_4358 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4361 = cat(_T_4360, _T_4357) @[Cat.scala 29:58] + node _T_4362 = cat(_T_4361, _T_4354) @[Cat.scala 29:58] + node _T_4363 = cat(_T_4362, _T_4351) @[Cat.scala 29:58] + buf_write <= _T_4363 @[lsu_bus_buffer.scala 512:13] + node _T_4364 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 513:117] + reg _T_4365 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4364 : @[Reg.scala 28:19] + _T_4365 <= buf_sz_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4366 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 513:117] + reg _T_4367 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4366 : @[Reg.scala 28:19] + _T_4367 <= buf_sz_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4368 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 513:117] + reg _T_4369 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4368 : @[Reg.scala 28:19] + _T_4369 <= buf_sz_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4370 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 513:117] + reg _T_4371 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4370 : @[Reg.scala 28:19] + _T_4371 <= buf_sz_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_sz[0] <= _T_4365 @[lsu_bus_buffer.scala 513:10] + buf_sz[1] <= _T_4367 @[lsu_bus_buffer.scala 513:10] + buf_sz[2] <= _T_4369 @[lsu_bus_buffer.scala 513:10] + buf_sz[3] <= _T_4371 @[lsu_bus_buffer.scala 513:10] + node _T_4372 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 514:80] + inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 368:23] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= reset + rvclkhdr_4.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_4.io.en <= _T_4372 @[lib.scala 371:17] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_4373 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_4373 <= buf_addr_in[0] @[lib.scala 374:16] + node _T_4374 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 514:80] + inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 368:23] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= reset + rvclkhdr_5.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_5.io.en <= _T_4374 @[lib.scala 371:17] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_4375 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_4375 <= buf_addr_in[1] @[lib.scala 374:16] + node _T_4376 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 514:80] + inst rvclkhdr_6 of rvclkhdr_6 @[lib.scala 368:23] + rvclkhdr_6.clock <= clock + rvclkhdr_6.reset <= reset + rvclkhdr_6.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_6.io.en <= _T_4376 @[lib.scala 371:17] + rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_4377 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_4377 <= buf_addr_in[2] @[lib.scala 374:16] + node _T_4378 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 514:80] + inst rvclkhdr_7 of rvclkhdr_7 @[lib.scala 368:23] + rvclkhdr_7.clock <= clock + rvclkhdr_7.reset <= reset + rvclkhdr_7.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_7.io.en <= _T_4378 @[lib.scala 371:17] + rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_4379 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_4379 <= buf_addr_in[3] @[lib.scala 374:16] + buf_addr[0] <= _T_4373 @[lsu_bus_buffer.scala 514:12] + buf_addr[1] <= _T_4375 @[lsu_bus_buffer.scala 514:12] + buf_addr[2] <= _T_4377 @[lsu_bus_buffer.scala 514:12] + buf_addr[3] <= _T_4379 @[lsu_bus_buffer.scala 514:12] + node _T_4380 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 515:125] + reg _T_4381 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4380 : @[Reg.scala 28:19] + _T_4381 <= buf_byteen_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4382 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 515:125] + reg _T_4383 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4382 : @[Reg.scala 28:19] + _T_4383 <= buf_byteen_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4384 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 515:125] + reg _T_4385 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4384 : @[Reg.scala 28:19] + _T_4385 <= buf_byteen_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4386 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 515:125] + reg _T_4387 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4386 : @[Reg.scala 28:19] + _T_4387 <= buf_byteen_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_byteen[0] <= _T_4381 @[lsu_bus_buffer.scala 515:14] + buf_byteen[1] <= _T_4383 @[lsu_bus_buffer.scala 515:14] + buf_byteen[2] <= _T_4385 @[lsu_bus_buffer.scala 515:14] + buf_byteen[3] <= _T_4387 @[lsu_bus_buffer.scala 515:14] + inst rvclkhdr_8 of rvclkhdr_8 @[lib.scala 368:23] + rvclkhdr_8.clock <= clock + rvclkhdr_8.reset <= reset + rvclkhdr_8.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_8.io.en <= buf_data_en[0] @[lib.scala 371:17] + rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_4388 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_4388 <= buf_data_in[0] @[lib.scala 374:16] + inst rvclkhdr_9 of rvclkhdr_9 @[lib.scala 368:23] + rvclkhdr_9.clock <= clock + rvclkhdr_9.reset <= reset + rvclkhdr_9.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_9.io.en <= buf_data_en[1] @[lib.scala 371:17] + rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_4389 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_4389 <= buf_data_in[1] @[lib.scala 374:16] + inst rvclkhdr_10 of rvclkhdr_10 @[lib.scala 368:23] + rvclkhdr_10.clock <= clock + rvclkhdr_10.reset <= reset + rvclkhdr_10.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_10.io.en <= buf_data_en[2] @[lib.scala 371:17] + rvclkhdr_10.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_4390 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_4390 <= buf_data_in[2] @[lib.scala 374:16] + inst rvclkhdr_11 of rvclkhdr_11 @[lib.scala 368:23] + rvclkhdr_11.clock <= clock + rvclkhdr_11.reset <= reset + rvclkhdr_11.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_11.io.en <= buf_data_en[3] @[lib.scala 371:17] + rvclkhdr_11.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_4391 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_4391 <= buf_data_in[3] @[lib.scala 374:16] + buf_data[0] <= _T_4388 @[lsu_bus_buffer.scala 516:12] + buf_data[1] <= _T_4389 @[lsu_bus_buffer.scala 516:12] + buf_data[2] <= _T_4390 @[lsu_bus_buffer.scala 516:12] + buf_data[3] <= _T_4391 @[lsu_bus_buffer.scala 516:12] + node _T_4392 = bits(buf_error, 0, 0) @[lsu_bus_buffer.scala 517:119] + node _T_4393 = mux(buf_error_en[0], UInt<1>("h01"), _T_4392) @[lsu_bus_buffer.scala 517:84] + node _T_4394 = eq(buf_rst[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 517:126] + node _T_4395 = and(_T_4393, _T_4394) @[lsu_bus_buffer.scala 517:124] + reg _T_4396 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 517:80] + _T_4396 <= _T_4395 @[lsu_bus_buffer.scala 517:80] + node _T_4397 = bits(buf_error, 1, 1) @[lsu_bus_buffer.scala 517:119] + node _T_4398 = mux(buf_error_en[1], UInt<1>("h01"), _T_4397) @[lsu_bus_buffer.scala 517:84] + node _T_4399 = eq(buf_rst[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 517:126] + node _T_4400 = and(_T_4398, _T_4399) @[lsu_bus_buffer.scala 517:124] + reg _T_4401 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 517:80] + _T_4401 <= _T_4400 @[lsu_bus_buffer.scala 517:80] + node _T_4402 = bits(buf_error, 2, 2) @[lsu_bus_buffer.scala 517:119] + node _T_4403 = mux(buf_error_en[2], UInt<1>("h01"), _T_4402) @[lsu_bus_buffer.scala 517:84] + node _T_4404 = eq(buf_rst[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 517:126] + node _T_4405 = and(_T_4403, _T_4404) @[lsu_bus_buffer.scala 517:124] + reg _T_4406 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 517:80] + _T_4406 <= _T_4405 @[lsu_bus_buffer.scala 517:80] + node _T_4407 = bits(buf_error, 3, 3) @[lsu_bus_buffer.scala 517:119] + node _T_4408 = mux(buf_error_en[3], UInt<1>("h01"), _T_4407) @[lsu_bus_buffer.scala 517:84] + node _T_4409 = eq(buf_rst[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 517:126] + node _T_4410 = and(_T_4408, _T_4409) @[lsu_bus_buffer.scala 517:124] + reg _T_4411 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 517:80] + _T_4411 <= _T_4410 @[lsu_bus_buffer.scala 517:80] + node _T_4412 = cat(_T_4411, _T_4406) @[Cat.scala 29:58] + node _T_4413 = cat(_T_4412, _T_4401) @[Cat.scala 29:58] + node _T_4414 = cat(_T_4413, _T_4396) @[Cat.scala 29:58] + buf_error <= _T_4414 @[lsu_bus_buffer.scala 517:13] + node _T_4415 = cat(io.lsu_busreq_m, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_4416 = mux(io.ldst_dual_m, _T_4415, io.lsu_busreq_m) @[lsu_bus_buffer.scala 520:28] + node _T_4417 = cat(io.lsu_busreq_r, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_4418 = mux(io.ldst_dual_r, _T_4417, io.lsu_busreq_r) @[lsu_bus_buffer.scala 520:94] + node _T_4419 = add(_T_4416, _T_4418) @[lsu_bus_buffer.scala 520:88] + node _T_4420 = add(_T_4419, ibuf_valid) @[lsu_bus_buffer.scala 520:154] + node _T_4421 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 520:190] + node _T_4422 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 520:190] + node _T_4423 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 520:190] + node _T_4424 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 520:190] + node _T_4425 = add(_T_4421, _T_4422) @[lsu_bus_buffer.scala 520:217] + node _T_4426 = add(_T_4425, _T_4423) @[lsu_bus_buffer.scala 520:217] + node _T_4427 = add(_T_4426, _T_4424) @[lsu_bus_buffer.scala 520:217] + node _T_4428 = add(_T_4420, _T_4427) @[lsu_bus_buffer.scala 520:169] + node buf_numvld_any = tail(_T_4428, 1) @[lsu_bus_buffer.scala 520:169] + node _T_4429 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 521:60] + node _T_4430 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 521:79] + node _T_4431 = and(_T_4429, _T_4430) @[lsu_bus_buffer.scala 521:64] + node _T_4432 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 521:91] + node _T_4433 = and(_T_4431, _T_4432) @[lsu_bus_buffer.scala 521:89] + node _T_4434 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 521:60] + node _T_4435 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 521:79] + node _T_4436 = and(_T_4434, _T_4435) @[lsu_bus_buffer.scala 521:64] + node _T_4437 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 521:91] + node _T_4438 = and(_T_4436, _T_4437) @[lsu_bus_buffer.scala 521:89] + node _T_4439 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 521:60] + node _T_4440 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 521:79] + node _T_4441 = and(_T_4439, _T_4440) @[lsu_bus_buffer.scala 521:64] + node _T_4442 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 521:91] + node _T_4443 = and(_T_4441, _T_4442) @[lsu_bus_buffer.scala 521:89] + node _T_4444 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 521:60] + node _T_4445 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 521:79] + node _T_4446 = and(_T_4444, _T_4445) @[lsu_bus_buffer.scala 521:64] + node _T_4447 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 521:91] + node _T_4448 = and(_T_4446, _T_4447) @[lsu_bus_buffer.scala 521:89] + node _T_4449 = add(_T_4448, _T_4443) @[lsu_bus_buffer.scala 521:142] + node _T_4450 = add(_T_4449, _T_4438) @[lsu_bus_buffer.scala 521:142] + node _T_4451 = add(_T_4450, _T_4433) @[lsu_bus_buffer.scala 521:142] + buf_numvld_wrcmd_any <= _T_4451 @[lsu_bus_buffer.scala 521:24] + node _T_4452 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 522:63] + node _T_4453 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 522:75] + node _T_4454 = and(_T_4452, _T_4453) @[lsu_bus_buffer.scala 522:73] + node _T_4455 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 522:63] + node _T_4456 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 522:75] + node _T_4457 = and(_T_4455, _T_4456) @[lsu_bus_buffer.scala 522:73] + node _T_4458 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 522:63] + node _T_4459 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 522:75] + node _T_4460 = and(_T_4458, _T_4459) @[lsu_bus_buffer.scala 522:73] + node _T_4461 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 522:63] + node _T_4462 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 522:75] + node _T_4463 = and(_T_4461, _T_4462) @[lsu_bus_buffer.scala 522:73] + node _T_4464 = add(_T_4463, _T_4460) @[lsu_bus_buffer.scala 522:126] + node _T_4465 = add(_T_4464, _T_4457) @[lsu_bus_buffer.scala 522:126] + node _T_4466 = add(_T_4465, _T_4454) @[lsu_bus_buffer.scala 522:126] + buf_numvld_cmd_any <= _T_4466 @[lsu_bus_buffer.scala 522:22] + node _T_4467 = eq(buf_state[0], UInt<3>("h01")) @[lsu_bus_buffer.scala 523:63] + node _T_4468 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 523:90] + node _T_4469 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 523:102] + node _T_4470 = and(_T_4468, _T_4469) @[lsu_bus_buffer.scala 523:100] + node _T_4471 = or(_T_4467, _T_4470) @[lsu_bus_buffer.scala 523:74] + node _T_4472 = eq(buf_state[1], UInt<3>("h01")) @[lsu_bus_buffer.scala 523:63] + node _T_4473 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 523:90] + node _T_4474 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 523:102] + node _T_4475 = and(_T_4473, _T_4474) @[lsu_bus_buffer.scala 523:100] + node _T_4476 = or(_T_4472, _T_4475) @[lsu_bus_buffer.scala 523:74] + node _T_4477 = eq(buf_state[2], UInt<3>("h01")) @[lsu_bus_buffer.scala 523:63] + node _T_4478 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 523:90] + node _T_4479 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 523:102] + node _T_4480 = and(_T_4478, _T_4479) @[lsu_bus_buffer.scala 523:100] + node _T_4481 = or(_T_4477, _T_4480) @[lsu_bus_buffer.scala 523:74] + node _T_4482 = eq(buf_state[3], UInt<3>("h01")) @[lsu_bus_buffer.scala 523:63] + node _T_4483 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 523:90] + node _T_4484 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 523:102] + node _T_4485 = and(_T_4483, _T_4484) @[lsu_bus_buffer.scala 523:100] + node _T_4486 = or(_T_4482, _T_4485) @[lsu_bus_buffer.scala 523:74] + node _T_4487 = add(_T_4486, _T_4481) @[lsu_bus_buffer.scala 523:154] + node _T_4488 = add(_T_4487, _T_4476) @[lsu_bus_buffer.scala 523:154] + node _T_4489 = add(_T_4488, _T_4471) @[lsu_bus_buffer.scala 523:154] + buf_numvld_pend_any <= _T_4489 @[lsu_bus_buffer.scala 523:23] + node _T_4490 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 524:61] + node _T_4491 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 524:61] + node _T_4492 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 524:61] + node _T_4493 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 524:61] + node _T_4494 = or(_T_4493, _T_4492) @[lsu_bus_buffer.scala 524:93] + node _T_4495 = or(_T_4494, _T_4491) @[lsu_bus_buffer.scala 524:93] + node _T_4496 = or(_T_4495, _T_4490) @[lsu_bus_buffer.scala 524:93] + any_done_wait_state <= _T_4496 @[lsu_bus_buffer.scala 524:23] + node _T_4497 = orr(buf_numvld_pend_any) @[lsu_bus_buffer.scala 525:53] + io.lsu_bus_buffer_pend_any <= _T_4497 @[lsu_bus_buffer.scala 525:30] + node _T_4498 = and(io.ldst_dual_d, io.dec_lsu_valid_raw_d) @[lsu_bus_buffer.scala 526:52] + node _T_4499 = geq(buf_numvld_any, UInt<2>("h03")) @[lsu_bus_buffer.scala 526:92] + node _T_4500 = eq(buf_numvld_any, UInt<3>("h04")) @[lsu_bus_buffer.scala 526:121] + node _T_4501 = mux(_T_4498, _T_4499, _T_4500) @[lsu_bus_buffer.scala 526:36] + io.lsu_bus_buffer_full_any <= _T_4501 @[lsu_bus_buffer.scala 526:30] + node _T_4502 = orr(buf_state[0]) @[lsu_bus_buffer.scala 527:52] + node _T_4503 = orr(buf_state[1]) @[lsu_bus_buffer.scala 527:52] + node _T_4504 = orr(buf_state[2]) @[lsu_bus_buffer.scala 527:52] + node _T_4505 = orr(buf_state[3]) @[lsu_bus_buffer.scala 527:52] + node _T_4506 = or(_T_4502, _T_4503) @[lsu_bus_buffer.scala 527:65] + node _T_4507 = or(_T_4506, _T_4504) @[lsu_bus_buffer.scala 527:65] + node _T_4508 = or(_T_4507, _T_4505) @[lsu_bus_buffer.scala 527:65] + node _T_4509 = eq(_T_4508, UInt<1>("h00")) @[lsu_bus_buffer.scala 527:34] + node _T_4510 = eq(ibuf_valid, UInt<1>("h00")) @[lsu_bus_buffer.scala 527:72] + node _T_4511 = and(_T_4509, _T_4510) @[lsu_bus_buffer.scala 527:70] + node _T_4512 = eq(obuf_valid, UInt<1>("h00")) @[lsu_bus_buffer.scala 527:86] + node _T_4513 = and(_T_4511, _T_4512) @[lsu_bus_buffer.scala 527:84] + io.lsu_bus_buffer_empty_any <= _T_4513 @[lsu_bus_buffer.scala 527:31] + node _T_4514 = and(io.lsu_busreq_m, io.lsu_pkt_m.valid) @[lsu_bus_buffer.scala 529:64] + node _T_4515 = and(_T_4514, io.lsu_pkt_m.bits.load) @[lsu_bus_buffer.scala 529:85] + node _T_4516 = eq(io.flush_m_up, UInt<1>("h00")) @[lsu_bus_buffer.scala 529:112] + node _T_4517 = and(_T_4515, _T_4516) @[lsu_bus_buffer.scala 529:110] + node _T_4518 = eq(io.ld_full_hit_m, UInt<1>("h00")) @[lsu_bus_buffer.scala 529:129] + node _T_4519 = and(_T_4517, _T_4518) @[lsu_bus_buffer.scala 529:127] + io.dctl_busbuff.lsu_nonblock_load_valid_m <= _T_4519 @[lsu_bus_buffer.scala 529:45] + io.dctl_busbuff.lsu_nonblock_load_tag_m <= WrPtr0_m @[lsu_bus_buffer.scala 530:43] + wire lsu_nonblock_load_valid_r : UInt<1> + lsu_nonblock_load_valid_r <= UInt<1>("h00") + node _T_4520 = eq(io.lsu_commit_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 532:74] + node _T_4521 = and(lsu_nonblock_load_valid_r, _T_4520) @[lsu_bus_buffer.scala 532:72] + io.dctl_busbuff.lsu_nonblock_load_inv_r <= _T_4521 @[lsu_bus_buffer.scala 532:43] + io.dctl_busbuff.lsu_nonblock_load_inv_tag_r <= WrPtr0_r @[lsu_bus_buffer.scala 533:47] + node _T_4522 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 534:80] + node _T_4523 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 534:127] + node _T_4524 = and(UInt<1>("h00"), _T_4523) @[lsu_bus_buffer.scala 534:116] + node _T_4525 = eq(_T_4524, UInt<1>("h00")) @[lsu_bus_buffer.scala 534:95] + node _T_4526 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 534:80] + node _T_4527 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 534:127] + node _T_4528 = and(UInt<1>("h00"), _T_4527) @[lsu_bus_buffer.scala 534:116] + node _T_4529 = eq(_T_4528, UInt<1>("h00")) @[lsu_bus_buffer.scala 534:95] + node _T_4530 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 534:80] + node _T_4531 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 534:127] + node _T_4532 = and(UInt<1>("h00"), _T_4531) @[lsu_bus_buffer.scala 534:116] + node _T_4533 = eq(_T_4532, UInt<1>("h00")) @[lsu_bus_buffer.scala 534:95] + node _T_4534 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 534:80] + node _T_4535 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 534:127] + node _T_4536 = and(UInt<1>("h00"), _T_4535) @[lsu_bus_buffer.scala 534:116] + node _T_4537 = eq(_T_4536, UInt<1>("h00")) @[lsu_bus_buffer.scala 534:95] + node _T_4538 = mux(_T_4522, _T_4525, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4539 = mux(_T_4526, _T_4529, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4540 = mux(_T_4530, _T_4533, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4541 = mux(_T_4534, _T_4537, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4542 = or(_T_4538, _T_4539) @[Mux.scala 27:72] + node _T_4543 = or(_T_4542, _T_4540) @[Mux.scala 27:72] + node _T_4544 = or(_T_4543, _T_4541) @[Mux.scala 27:72] + wire lsu_nonblock_load_data_ready : UInt<1> @[Mux.scala 27:72] + lsu_nonblock_load_data_ready <= _T_4544 @[Mux.scala 27:72] + node _T_4545 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 535:93] + node _T_4546 = bits(buf_error, 0, 0) @[lsu_bus_buffer.scala 535:117] + node _T_4547 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 535:133] + node _T_4548 = eq(_T_4547, UInt<1>("h00")) @[lsu_bus_buffer.scala 535:123] + node _T_4549 = and(_T_4546, _T_4548) @[lsu_bus_buffer.scala 535:121] + node _T_4550 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 535:93] + node _T_4551 = bits(buf_error, 1, 1) @[lsu_bus_buffer.scala 535:117] + node _T_4552 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 535:133] + node _T_4553 = eq(_T_4552, UInt<1>("h00")) @[lsu_bus_buffer.scala 535:123] + node _T_4554 = and(_T_4551, _T_4553) @[lsu_bus_buffer.scala 535:121] + node _T_4555 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 535:93] + node _T_4556 = bits(buf_error, 2, 2) @[lsu_bus_buffer.scala 535:117] + node _T_4557 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 535:133] + node _T_4558 = eq(_T_4557, UInt<1>("h00")) @[lsu_bus_buffer.scala 535:123] + node _T_4559 = and(_T_4556, _T_4558) @[lsu_bus_buffer.scala 535:121] + node _T_4560 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 535:93] + node _T_4561 = bits(buf_error, 3, 3) @[lsu_bus_buffer.scala 535:117] + node _T_4562 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 535:133] + node _T_4563 = eq(_T_4562, UInt<1>("h00")) @[lsu_bus_buffer.scala 535:123] + node _T_4564 = and(_T_4561, _T_4563) @[lsu_bus_buffer.scala 535:121] + node _T_4565 = mux(_T_4545, _T_4549, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4566 = mux(_T_4550, _T_4554, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4567 = mux(_T_4555, _T_4559, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4568 = mux(_T_4560, _T_4564, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4569 = or(_T_4565, _T_4566) @[Mux.scala 27:72] + node _T_4570 = or(_T_4569, _T_4567) @[Mux.scala 27:72] + node _T_4571 = or(_T_4570, _T_4568) @[Mux.scala 27:72] + wire _T_4572 : UInt<1> @[Mux.scala 27:72] + _T_4572 <= _T_4571 @[Mux.scala 27:72] + io.dctl_busbuff.lsu_nonblock_load_data_error <= _T_4572 @[lsu_bus_buffer.scala 535:48] + node _T_4573 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 536:92] + node _T_4574 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 536:115] + node _T_4575 = eq(_T_4574, UInt<1>("h00")) @[lsu_bus_buffer.scala 536:105] + node _T_4576 = and(_T_4573, _T_4575) @[lsu_bus_buffer.scala 536:103] + node _T_4577 = eq(buf_dual[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 536:122] + node _T_4578 = eq(buf_dualhi[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 536:137] + node _T_4579 = or(_T_4577, _T_4578) @[lsu_bus_buffer.scala 536:135] + node _T_4580 = and(_T_4576, _T_4579) @[lsu_bus_buffer.scala 536:119] + node _T_4581 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 536:92] + node _T_4582 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 536:115] + node _T_4583 = eq(_T_4582, UInt<1>("h00")) @[lsu_bus_buffer.scala 536:105] + node _T_4584 = and(_T_4581, _T_4583) @[lsu_bus_buffer.scala 536:103] + node _T_4585 = eq(buf_dual[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 536:122] + node _T_4586 = eq(buf_dualhi[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 536:137] + node _T_4587 = or(_T_4585, _T_4586) @[lsu_bus_buffer.scala 536:135] + node _T_4588 = and(_T_4584, _T_4587) @[lsu_bus_buffer.scala 536:119] + node _T_4589 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 536:92] + node _T_4590 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 536:115] + node _T_4591 = eq(_T_4590, UInt<1>("h00")) @[lsu_bus_buffer.scala 536:105] + node _T_4592 = and(_T_4589, _T_4591) @[lsu_bus_buffer.scala 536:103] + node _T_4593 = eq(buf_dual[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 536:122] + node _T_4594 = eq(buf_dualhi[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 536:137] + node _T_4595 = or(_T_4593, _T_4594) @[lsu_bus_buffer.scala 536:135] + node _T_4596 = and(_T_4592, _T_4595) @[lsu_bus_buffer.scala 536:119] + node _T_4597 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 536:92] + node _T_4598 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 536:115] + node _T_4599 = eq(_T_4598, UInt<1>("h00")) @[lsu_bus_buffer.scala 536:105] + node _T_4600 = and(_T_4597, _T_4599) @[lsu_bus_buffer.scala 536:103] + node _T_4601 = eq(buf_dual[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 536:122] + node _T_4602 = eq(buf_dualhi[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 536:137] + node _T_4603 = or(_T_4601, _T_4602) @[lsu_bus_buffer.scala 536:135] + node _T_4604 = and(_T_4600, _T_4603) @[lsu_bus_buffer.scala 536:119] + node _T_4605 = mux(_T_4580, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4606 = mux(_T_4588, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4607 = mux(_T_4596, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4608 = mux(_T_4604, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4609 = or(_T_4605, _T_4606) @[Mux.scala 27:72] + node _T_4610 = or(_T_4609, _T_4607) @[Mux.scala 27:72] + node _T_4611 = or(_T_4610, _T_4608) @[Mux.scala 27:72] + wire _T_4612 : UInt<2> @[Mux.scala 27:72] + _T_4612 <= _T_4611 @[Mux.scala 27:72] + io.dctl_busbuff.lsu_nonblock_load_data_tag <= _T_4612 @[lsu_bus_buffer.scala 536:46] + node _T_4613 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 537:78] + node _T_4614 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 537:101] + node _T_4615 = eq(_T_4614, UInt<1>("h00")) @[lsu_bus_buffer.scala 537:91] + node _T_4616 = and(_T_4613, _T_4615) @[lsu_bus_buffer.scala 537:89] + node _T_4617 = eq(buf_dual[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 537:108] + node _T_4618 = eq(buf_dualhi[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 537:123] + node _T_4619 = or(_T_4617, _T_4618) @[lsu_bus_buffer.scala 537:121] + node _T_4620 = and(_T_4616, _T_4619) @[lsu_bus_buffer.scala 537:105] + node _T_4621 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 537:78] + node _T_4622 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 537:101] + node _T_4623 = eq(_T_4622, UInt<1>("h00")) @[lsu_bus_buffer.scala 537:91] + node _T_4624 = and(_T_4621, _T_4623) @[lsu_bus_buffer.scala 537:89] + node _T_4625 = eq(buf_dual[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 537:108] + node _T_4626 = eq(buf_dualhi[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 537:123] + node _T_4627 = or(_T_4625, _T_4626) @[lsu_bus_buffer.scala 537:121] + node _T_4628 = and(_T_4624, _T_4627) @[lsu_bus_buffer.scala 537:105] + node _T_4629 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 537:78] + node _T_4630 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 537:101] + node _T_4631 = eq(_T_4630, UInt<1>("h00")) @[lsu_bus_buffer.scala 537:91] + node _T_4632 = and(_T_4629, _T_4631) @[lsu_bus_buffer.scala 537:89] + node _T_4633 = eq(buf_dual[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 537:108] + node _T_4634 = eq(buf_dualhi[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 537:123] + node _T_4635 = or(_T_4633, _T_4634) @[lsu_bus_buffer.scala 537:121] + node _T_4636 = and(_T_4632, _T_4635) @[lsu_bus_buffer.scala 537:105] + node _T_4637 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 537:78] + node _T_4638 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 537:101] + node _T_4639 = eq(_T_4638, UInt<1>("h00")) @[lsu_bus_buffer.scala 537:91] + node _T_4640 = and(_T_4637, _T_4639) @[lsu_bus_buffer.scala 537:89] + node _T_4641 = eq(buf_dual[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 537:108] + node _T_4642 = eq(buf_dualhi[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 537:123] + node _T_4643 = or(_T_4641, _T_4642) @[lsu_bus_buffer.scala 537:121] + node _T_4644 = and(_T_4640, _T_4643) @[lsu_bus_buffer.scala 537:105] + node _T_4645 = mux(_T_4620, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4646 = mux(_T_4628, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4647 = mux(_T_4636, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4648 = mux(_T_4644, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4649 = or(_T_4645, _T_4646) @[Mux.scala 27:72] + node _T_4650 = or(_T_4649, _T_4647) @[Mux.scala 27:72] + node _T_4651 = or(_T_4650, _T_4648) @[Mux.scala 27:72] + wire lsu_nonblock_load_data_lo : UInt<32> @[Mux.scala 27:72] + lsu_nonblock_load_data_lo <= _T_4651 @[Mux.scala 27:72] + node _T_4652 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 538:78] + node _T_4653 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 538:101] + node _T_4654 = eq(_T_4653, UInt<1>("h00")) @[lsu_bus_buffer.scala 538:91] + node _T_4655 = and(_T_4652, _T_4654) @[lsu_bus_buffer.scala 538:89] + node _T_4656 = and(buf_dual[0], buf_dualhi[0]) @[lsu_bus_buffer.scala 538:120] + node _T_4657 = and(_T_4655, _T_4656) @[lsu_bus_buffer.scala 538:105] + node _T_4658 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 538:78] + node _T_4659 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 538:101] + node _T_4660 = eq(_T_4659, UInt<1>("h00")) @[lsu_bus_buffer.scala 538:91] + node _T_4661 = and(_T_4658, _T_4660) @[lsu_bus_buffer.scala 538:89] + node _T_4662 = and(buf_dual[1], buf_dualhi[1]) @[lsu_bus_buffer.scala 538:120] + node _T_4663 = and(_T_4661, _T_4662) @[lsu_bus_buffer.scala 538:105] + node _T_4664 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 538:78] + node _T_4665 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 538:101] + node _T_4666 = eq(_T_4665, UInt<1>("h00")) @[lsu_bus_buffer.scala 538:91] + node _T_4667 = and(_T_4664, _T_4666) @[lsu_bus_buffer.scala 538:89] + node _T_4668 = and(buf_dual[2], buf_dualhi[2]) @[lsu_bus_buffer.scala 538:120] + node _T_4669 = and(_T_4667, _T_4668) @[lsu_bus_buffer.scala 538:105] + node _T_4670 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 538:78] + node _T_4671 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 538:101] + node _T_4672 = eq(_T_4671, UInt<1>("h00")) @[lsu_bus_buffer.scala 538:91] + node _T_4673 = and(_T_4670, _T_4672) @[lsu_bus_buffer.scala 538:89] + node _T_4674 = and(buf_dual[3], buf_dualhi[3]) @[lsu_bus_buffer.scala 538:120] + node _T_4675 = and(_T_4673, _T_4674) @[lsu_bus_buffer.scala 538:105] + node _T_4676 = mux(_T_4657, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4677 = mux(_T_4663, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4678 = mux(_T_4669, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4679 = mux(_T_4675, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4680 = or(_T_4676, _T_4677) @[Mux.scala 27:72] + node _T_4681 = or(_T_4680, _T_4678) @[Mux.scala 27:72] + node _T_4682 = or(_T_4681, _T_4679) @[Mux.scala 27:72] + wire lsu_nonblock_load_data_hi : UInt<32> @[Mux.scala 27:72] + lsu_nonblock_load_data_hi <= _T_4682 @[Mux.scala 27:72] + node _T_4683 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_4684 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_4685 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_4686 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] + node _T_4687 = mux(_T_4683, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4688 = mux(_T_4684, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4689 = mux(_T_4685, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4690 = mux(_T_4686, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4691 = or(_T_4687, _T_4688) @[Mux.scala 27:72] + node _T_4692 = or(_T_4691, _T_4689) @[Mux.scala 27:72] + node _T_4693 = or(_T_4692, _T_4690) @[Mux.scala 27:72] + wire _T_4694 : UInt<32> @[Mux.scala 27:72] + _T_4694 <= _T_4693 @[Mux.scala 27:72] + node lsu_nonblock_addr_offset = bits(_T_4694, 1, 0) @[lsu_bus_buffer.scala 539:96] + node _T_4695 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_4696 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_4697 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_4698 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] + node _T_4699 = mux(_T_4695, buf_sz[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4700 = mux(_T_4696, buf_sz[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4701 = mux(_T_4697, buf_sz[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4702 = mux(_T_4698, buf_sz[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4703 = or(_T_4699, _T_4700) @[Mux.scala 27:72] + node _T_4704 = or(_T_4703, _T_4701) @[Mux.scala 27:72] + node _T_4705 = or(_T_4704, _T_4702) @[Mux.scala 27:72] + wire lsu_nonblock_sz : UInt<2> @[Mux.scala 27:72] + lsu_nonblock_sz <= _T_4705 @[Mux.scala 27:72] + node _T_4706 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_4707 = bits(buf_unsign, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_4708 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_4709 = bits(buf_unsign, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_4710 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_4711 = bits(buf_unsign, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_4712 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_4713 = bits(buf_unsign, 3, 3) @[lsu_bus_buffer.scala 57:129] + node _T_4714 = mux(_T_4706, _T_4707, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4715 = mux(_T_4708, _T_4709, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4716 = mux(_T_4710, _T_4711, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4717 = mux(_T_4712, _T_4713, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4718 = or(_T_4714, _T_4715) @[Mux.scala 27:72] + node _T_4719 = or(_T_4718, _T_4716) @[Mux.scala 27:72] + node _T_4720 = or(_T_4719, _T_4717) @[Mux.scala 27:72] + wire lsu_nonblock_unsign : UInt<1> @[Mux.scala 27:72] + lsu_nonblock_unsign <= _T_4720 @[Mux.scala 27:72] + node _T_4721 = cat(buf_dual[3], buf_dual[2]) @[Cat.scala 29:58] + node _T_4722 = cat(_T_4721, buf_dual[1]) @[Cat.scala 29:58] + node _T_4723 = cat(_T_4722, buf_dual[0]) @[Cat.scala 29:58] + node _T_4724 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_4725 = bits(_T_4723, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_4726 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_4727 = bits(_T_4723, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_4728 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_4729 = bits(_T_4723, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_4730 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_4731 = bits(_T_4723, 3, 3) @[lsu_bus_buffer.scala 57:129] + node _T_4732 = mux(_T_4724, _T_4725, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4733 = mux(_T_4726, _T_4727, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4734 = mux(_T_4728, _T_4729, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4735 = mux(_T_4730, _T_4731, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4736 = or(_T_4732, _T_4733) @[Mux.scala 27:72] + node _T_4737 = or(_T_4736, _T_4734) @[Mux.scala 27:72] + node _T_4738 = or(_T_4737, _T_4735) @[Mux.scala 27:72] + wire lsu_nonblock_dual : UInt<1> @[Mux.scala 27:72] + lsu_nonblock_dual <= _T_4738 @[Mux.scala 27:72] + node _T_4739 = cat(lsu_nonblock_load_data_hi, lsu_nonblock_load_data_lo) @[Cat.scala 29:58] + node _T_4740 = mul(lsu_nonblock_addr_offset, UInt<4>("h08")) @[lsu_bus_buffer.scala 543:121] + node lsu_nonblock_data_unalgn = dshr(_T_4739, _T_4740) @[lsu_bus_buffer.scala 543:92] + node _T_4741 = eq(io.dctl_busbuff.lsu_nonblock_load_data_error, UInt<1>("h00")) @[lsu_bus_buffer.scala 545:82] + node _T_4742 = and(lsu_nonblock_load_data_ready, _T_4741) @[lsu_bus_buffer.scala 545:80] + io.dctl_busbuff.lsu_nonblock_load_data_valid <= _T_4742 @[lsu_bus_buffer.scala 545:48] + node _T_4743 = eq(lsu_nonblock_sz, UInt<1>("h00")) @[lsu_bus_buffer.scala 546:94] + node _T_4744 = and(lsu_nonblock_unsign, _T_4743) @[lsu_bus_buffer.scala 546:76] + node _T_4745 = bits(lsu_nonblock_data_unalgn, 7, 0) @[lsu_bus_buffer.scala 546:144] + node _T_4746 = cat(UInt<24>("h00"), _T_4745) @[Cat.scala 29:58] + node _T_4747 = eq(lsu_nonblock_sz, UInt<1>("h01")) @[lsu_bus_buffer.scala 547:45] + node _T_4748 = and(lsu_nonblock_unsign, _T_4747) @[lsu_bus_buffer.scala 547:26] + node _T_4749 = bits(lsu_nonblock_data_unalgn, 15, 0) @[lsu_bus_buffer.scala 547:95] + node _T_4750 = cat(UInt<16>("h00"), _T_4749) @[Cat.scala 29:58] + node _T_4751 = eq(lsu_nonblock_unsign, UInt<1>("h00")) @[lsu_bus_buffer.scala 548:6] + node _T_4752 = eq(lsu_nonblock_sz, UInt<1>("h00")) @[lsu_bus_buffer.scala 548:45] + node _T_4753 = and(_T_4751, _T_4752) @[lsu_bus_buffer.scala 548:27] + node _T_4754 = bits(lsu_nonblock_data_unalgn, 7, 7) @[lsu_bus_buffer.scala 548:93] + node _T_4755 = bits(_T_4754, 0, 0) @[Bitwise.scala 72:15] + node _T_4756 = mux(_T_4755, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12] + node _T_4757 = bits(lsu_nonblock_data_unalgn, 7, 0) @[lsu_bus_buffer.scala 548:123] + node _T_4758 = cat(_T_4756, _T_4757) @[Cat.scala 29:58] + node _T_4759 = eq(lsu_nonblock_unsign, UInt<1>("h00")) @[lsu_bus_buffer.scala 549:6] + node _T_4760 = eq(lsu_nonblock_sz, UInt<1>("h01")) @[lsu_bus_buffer.scala 549:45] + node _T_4761 = and(_T_4759, _T_4760) @[lsu_bus_buffer.scala 549:27] + node _T_4762 = bits(lsu_nonblock_data_unalgn, 15, 15) @[lsu_bus_buffer.scala 549:93] + node _T_4763 = bits(_T_4762, 0, 0) @[Bitwise.scala 72:15] + node _T_4764 = mux(_T_4763, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] + node _T_4765 = bits(lsu_nonblock_data_unalgn, 15, 0) @[lsu_bus_buffer.scala 549:124] + node _T_4766 = cat(_T_4764, _T_4765) @[Cat.scala 29:58] + node _T_4767 = eq(lsu_nonblock_sz, UInt<2>("h02")) @[lsu_bus_buffer.scala 550:21] + node _T_4768 = mux(_T_4744, _T_4746, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4769 = mux(_T_4748, _T_4750, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4770 = mux(_T_4753, _T_4758, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4771 = mux(_T_4761, _T_4766, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4772 = mux(_T_4767, lsu_nonblock_data_unalgn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4773 = or(_T_4768, _T_4769) @[Mux.scala 27:72] + node _T_4774 = or(_T_4773, _T_4770) @[Mux.scala 27:72] + node _T_4775 = or(_T_4774, _T_4771) @[Mux.scala 27:72] + node _T_4776 = or(_T_4775, _T_4772) @[Mux.scala 27:72] + wire _T_4777 : UInt<64> @[Mux.scala 27:72] + _T_4777 <= _T_4776 @[Mux.scala 27:72] + io.dctl_busbuff.lsu_nonblock_load_data <= _T_4777 @[lsu_bus_buffer.scala 546:42] + node _T_4778 = eq(buf_state[0], UInt<3>("h03")) @[lsu_bus_buffer.scala 551:62] + node _T_4779 = bits(buf_sideeffect, 0, 0) @[lsu_bus_buffer.scala 551:89] + node _T_4780 = and(_T_4778, _T_4779) @[lsu_bus_buffer.scala 551:73] + node _T_4781 = and(_T_4780, io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) @[lsu_bus_buffer.scala 551:93] + node _T_4782 = eq(buf_state[1], UInt<3>("h03")) @[lsu_bus_buffer.scala 551:62] + node _T_4783 = bits(buf_sideeffect, 1, 1) @[lsu_bus_buffer.scala 551:89] + node _T_4784 = and(_T_4782, _T_4783) @[lsu_bus_buffer.scala 551:73] + node _T_4785 = and(_T_4784, io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) @[lsu_bus_buffer.scala 551:93] + node _T_4786 = eq(buf_state[2], UInt<3>("h03")) @[lsu_bus_buffer.scala 551:62] + node _T_4787 = bits(buf_sideeffect, 2, 2) @[lsu_bus_buffer.scala 551:89] + node _T_4788 = and(_T_4786, _T_4787) @[lsu_bus_buffer.scala 551:73] + node _T_4789 = and(_T_4788, io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) @[lsu_bus_buffer.scala 551:93] + node _T_4790 = eq(buf_state[3], UInt<3>("h03")) @[lsu_bus_buffer.scala 551:62] + node _T_4791 = bits(buf_sideeffect, 3, 3) @[lsu_bus_buffer.scala 551:89] + node _T_4792 = and(_T_4790, _T_4791) @[lsu_bus_buffer.scala 551:73] + node _T_4793 = and(_T_4792, io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) @[lsu_bus_buffer.scala 551:93] + node _T_4794 = or(_T_4781, _T_4785) @[lsu_bus_buffer.scala 551:153] + node _T_4795 = or(_T_4794, _T_4789) @[lsu_bus_buffer.scala 551:153] + node _T_4796 = or(_T_4795, _T_4793) @[lsu_bus_buffer.scala 551:153] + node _T_4797 = and(obuf_valid, obuf_sideeffect) @[lsu_bus_buffer.scala 551:171] + node _T_4798 = and(_T_4797, io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) @[lsu_bus_buffer.scala 551:189] + node _T_4799 = or(_T_4796, _T_4798) @[lsu_bus_buffer.scala 551:157] + bus_sideeffect_pend <= _T_4799 @[lsu_bus_buffer.scala 551:23] + node _T_4800 = eq(buf_state[0], UInt<3>("h03")) @[lsu_bus_buffer.scala 552:71] + node _T_4801 = and(UInt<1>("h00"), obuf_valid) @[lsu_bus_buffer.scala 553:25] + node _T_4802 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 553:50] + node _T_4803 = bits(buf_addr[0], 31, 3) @[lsu_bus_buffer.scala 553:70] + node _T_4804 = eq(_T_4802, _T_4803) @[lsu_bus_buffer.scala 553:56] + node _T_4805 = and(_T_4801, _T_4804) @[lsu_bus_buffer.scala 553:38] + node _T_4806 = eq(obuf_tag0, UInt<1>("h00")) @[lsu_bus_buffer.scala 553:92] + node _T_4807 = eq(obuf_tag1, UInt<1>("h00")) @[lsu_bus_buffer.scala 553:126] + node _T_4808 = and(obuf_merge, _T_4807) @[lsu_bus_buffer.scala 553:114] + node _T_4809 = or(_T_4806, _T_4808) @[lsu_bus_buffer.scala 553:100] + node _T_4810 = eq(_T_4809, UInt<1>("h00")) @[lsu_bus_buffer.scala 553:80] + node _T_4811 = and(_T_4805, _T_4810) @[lsu_bus_buffer.scala 553:78] + node _T_4812 = eq(buf_state[1], UInt<3>("h03")) @[lsu_bus_buffer.scala 552:71] + node _T_4813 = and(UInt<1>("h00"), obuf_valid) @[lsu_bus_buffer.scala 553:25] + node _T_4814 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 553:50] + node _T_4815 = bits(buf_addr[1], 31, 3) @[lsu_bus_buffer.scala 553:70] + node _T_4816 = eq(_T_4814, _T_4815) @[lsu_bus_buffer.scala 553:56] + node _T_4817 = and(_T_4813, _T_4816) @[lsu_bus_buffer.scala 553:38] + node _T_4818 = eq(obuf_tag0, UInt<1>("h01")) @[lsu_bus_buffer.scala 553:92] + node _T_4819 = eq(obuf_tag1, UInt<1>("h01")) @[lsu_bus_buffer.scala 553:126] + node _T_4820 = and(obuf_merge, _T_4819) @[lsu_bus_buffer.scala 553:114] + node _T_4821 = or(_T_4818, _T_4820) @[lsu_bus_buffer.scala 553:100] + node _T_4822 = eq(_T_4821, UInt<1>("h00")) @[lsu_bus_buffer.scala 553:80] + node _T_4823 = and(_T_4817, _T_4822) @[lsu_bus_buffer.scala 553:78] + node _T_4824 = eq(buf_state[2], UInt<3>("h03")) @[lsu_bus_buffer.scala 552:71] + node _T_4825 = and(UInt<1>("h00"), obuf_valid) @[lsu_bus_buffer.scala 553:25] + node _T_4826 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 553:50] + node _T_4827 = bits(buf_addr[2], 31, 3) @[lsu_bus_buffer.scala 553:70] + node _T_4828 = eq(_T_4826, _T_4827) @[lsu_bus_buffer.scala 553:56] + node _T_4829 = and(_T_4825, _T_4828) @[lsu_bus_buffer.scala 553:38] + node _T_4830 = eq(obuf_tag0, UInt<2>("h02")) @[lsu_bus_buffer.scala 553:92] + node _T_4831 = eq(obuf_tag1, UInt<2>("h02")) @[lsu_bus_buffer.scala 553:126] + node _T_4832 = and(obuf_merge, _T_4831) @[lsu_bus_buffer.scala 553:114] + node _T_4833 = or(_T_4830, _T_4832) @[lsu_bus_buffer.scala 553:100] + node _T_4834 = eq(_T_4833, UInt<1>("h00")) @[lsu_bus_buffer.scala 553:80] + node _T_4835 = and(_T_4829, _T_4834) @[lsu_bus_buffer.scala 553:78] + node _T_4836 = eq(buf_state[3], UInt<3>("h03")) @[lsu_bus_buffer.scala 552:71] + node _T_4837 = and(UInt<1>("h00"), obuf_valid) @[lsu_bus_buffer.scala 553:25] + node _T_4838 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 553:50] + node _T_4839 = bits(buf_addr[3], 31, 3) @[lsu_bus_buffer.scala 553:70] + node _T_4840 = eq(_T_4838, _T_4839) @[lsu_bus_buffer.scala 553:56] + node _T_4841 = and(_T_4837, _T_4840) @[lsu_bus_buffer.scala 553:38] + node _T_4842 = eq(obuf_tag0, UInt<2>("h03")) @[lsu_bus_buffer.scala 553:92] + node _T_4843 = eq(obuf_tag1, UInt<2>("h03")) @[lsu_bus_buffer.scala 553:126] + node _T_4844 = and(obuf_merge, _T_4843) @[lsu_bus_buffer.scala 553:114] + node _T_4845 = or(_T_4842, _T_4844) @[lsu_bus_buffer.scala 553:100] + node _T_4846 = eq(_T_4845, UInt<1>("h00")) @[lsu_bus_buffer.scala 553:80] + node _T_4847 = and(_T_4841, _T_4846) @[lsu_bus_buffer.scala 553:78] + node _T_4848 = mux(_T_4800, _T_4811, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4849 = mux(_T_4812, _T_4823, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4850 = mux(_T_4824, _T_4835, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4851 = mux(_T_4836, _T_4847, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4852 = or(_T_4848, _T_4849) @[Mux.scala 27:72] + node _T_4853 = or(_T_4852, _T_4850) @[Mux.scala 27:72] + node _T_4854 = or(_T_4853, _T_4851) @[Mux.scala 27:72] + wire _T_4855 : UInt<1> @[Mux.scala 27:72] + _T_4855 <= _T_4854 @[Mux.scala 27:72] + bus_addr_match_pending <= _T_4855 @[lsu_bus_buffer.scala 552:26] + node _T_4856 = or(obuf_cmd_done, obuf_data_done) @[lsu_bus_buffer.scala 555:54] + node _T_4857 = mux(obuf_cmd_done, io.lsu_axi.w.ready, io.lsu_axi.aw.ready) @[lsu_bus_buffer.scala 555:75] + node _T_4858 = and(io.lsu_axi.aw.ready, io.lsu_axi.w.ready) @[lsu_bus_buffer.scala 555:153] + node _T_4859 = mux(_T_4856, _T_4857, _T_4858) @[lsu_bus_buffer.scala 555:39] + node _T_4860 = mux(obuf_write, _T_4859, io.lsu_axi.ar.ready) @[lsu_bus_buffer.scala 555:23] + bus_cmd_ready <= _T_4860 @[lsu_bus_buffer.scala 555:17] + node _T_4861 = and(io.lsu_axi.aw.valid, io.lsu_axi.aw.ready) @[lsu_bus_buffer.scala 556:40] + bus_wcmd_sent <= _T_4861 @[lsu_bus_buffer.scala 556:17] + node _T_4862 = and(io.lsu_axi.w.valid, io.lsu_axi.w.ready) @[lsu_bus_buffer.scala 557:40] + bus_wdata_sent <= _T_4862 @[lsu_bus_buffer.scala 557:18] + node _T_4863 = or(obuf_cmd_done, bus_wcmd_sent) @[lsu_bus_buffer.scala 558:35] + node _T_4864 = or(obuf_data_done, bus_wdata_sent) @[lsu_bus_buffer.scala 558:70] + node _T_4865 = and(_T_4863, _T_4864) @[lsu_bus_buffer.scala 558:52] + node _T_4866 = and(io.lsu_axi.ar.valid, io.lsu_axi.ar.ready) @[lsu_bus_buffer.scala 558:112] + node _T_4867 = or(_T_4865, _T_4866) @[lsu_bus_buffer.scala 558:89] + bus_cmd_sent <= _T_4867 @[lsu_bus_buffer.scala 558:16] + node _T_4868 = and(io.lsu_axi.r.valid, io.lsu_axi.r.ready) @[lsu_bus_buffer.scala 559:38] + bus_rsp_read <= _T_4868 @[lsu_bus_buffer.scala 559:16] + node _T_4869 = and(io.lsu_axi.b.valid, io.lsu_axi.b.ready) @[lsu_bus_buffer.scala 560:39] + bus_rsp_write <= _T_4869 @[lsu_bus_buffer.scala 560:17] + bus_rsp_read_tag <= io.lsu_axi.r.bits.id @[lsu_bus_buffer.scala 561:20] + bus_rsp_write_tag <= io.lsu_axi.b.bits.id @[lsu_bus_buffer.scala 562:21] + node _T_4870 = neq(io.lsu_axi.b.bits.resp, UInt<1>("h00")) @[lsu_bus_buffer.scala 563:66] + node _T_4871 = and(bus_rsp_write, _T_4870) @[lsu_bus_buffer.scala 563:40] + bus_rsp_write_error <= _T_4871 @[lsu_bus_buffer.scala 563:23] + node _T_4872 = neq(io.lsu_axi.r.bits.resp, UInt<1>("h00")) @[lsu_bus_buffer.scala 564:64] + node _T_4873 = and(bus_rsp_read, _T_4872) @[lsu_bus_buffer.scala 564:38] + bus_rsp_read_error <= _T_4873 @[lsu_bus_buffer.scala 564:22] + bus_rsp_rdata <= io.lsu_axi.r.bits.data @[lsu_bus_buffer.scala 565:17] + node _T_4874 = and(obuf_valid, obuf_write) @[lsu_bus_buffer.scala 568:37] + node _T_4875 = eq(obuf_cmd_done, UInt<1>("h00")) @[lsu_bus_buffer.scala 568:52] + node _T_4876 = and(_T_4874, _T_4875) @[lsu_bus_buffer.scala 568:50] + node _T_4877 = eq(bus_addr_match_pending, UInt<1>("h00")) @[lsu_bus_buffer.scala 568:69] + node _T_4878 = and(_T_4876, _T_4877) @[lsu_bus_buffer.scala 568:67] + io.lsu_axi.aw.valid <= _T_4878 @[lsu_bus_buffer.scala 568:23] + io.lsu_axi.aw.bits.id <= obuf_tag0 @[lsu_bus_buffer.scala 569:25] + node _T_4879 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 570:75] + node _T_4880 = cat(_T_4879, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_4881 = mux(obuf_sideeffect, obuf_addr, _T_4880) @[lsu_bus_buffer.scala 570:33] + io.lsu_axi.aw.bits.addr <= _T_4881 @[lsu_bus_buffer.scala 570:27] + node _T_4882 = cat(UInt<1>("h00"), obuf_sz) @[Cat.scala 29:58] + node _T_4883 = mux(obuf_sideeffect, _T_4882, UInt<3>("h03")) @[lsu_bus_buffer.scala 571:33] + io.lsu_axi.aw.bits.size <= _T_4883 @[lsu_bus_buffer.scala 571:27] + io.lsu_axi.aw.bits.prot <= UInt<1>("h00") @[lsu_bus_buffer.scala 572:27] + node _T_4884 = mux(obuf_sideeffect, UInt<1>("h00"), UInt<4>("h0f")) @[lsu_bus_buffer.scala 573:34] + io.lsu_axi.aw.bits.cache <= _T_4884 @[lsu_bus_buffer.scala 573:28] + node _T_4885 = bits(obuf_addr, 31, 28) @[lsu_bus_buffer.scala 574:41] + io.lsu_axi.aw.bits.region <= _T_4885 @[lsu_bus_buffer.scala 574:29] + io.lsu_axi.aw.bits.len <= UInt<1>("h00") @[lsu_bus_buffer.scala 575:26] + io.lsu_axi.aw.bits.burst <= UInt<2>("h01") @[lsu_bus_buffer.scala 576:28] + io.lsu_axi.aw.bits.qos <= UInt<1>("h00") @[lsu_bus_buffer.scala 577:26] + io.lsu_axi.aw.bits.lock <= UInt<1>("h00") @[lsu_bus_buffer.scala 578:27] + node _T_4886 = and(obuf_valid, obuf_write) @[lsu_bus_buffer.scala 580:36] + node _T_4887 = eq(obuf_data_done, UInt<1>("h00")) @[lsu_bus_buffer.scala 580:51] + node _T_4888 = and(_T_4886, _T_4887) @[lsu_bus_buffer.scala 580:49] + node _T_4889 = eq(bus_addr_match_pending, UInt<1>("h00")) @[lsu_bus_buffer.scala 580:69] + node _T_4890 = and(_T_4888, _T_4889) @[lsu_bus_buffer.scala 580:67] + io.lsu_axi.w.valid <= _T_4890 @[lsu_bus_buffer.scala 580:22] + node _T_4891 = bits(obuf_write, 0, 0) @[Bitwise.scala 72:15] + node _T_4892 = mux(_T_4891, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_4893 = and(obuf_byteen, _T_4892) @[lsu_bus_buffer.scala 581:41] + io.lsu_axi.w.bits.strb <= _T_4893 @[lsu_bus_buffer.scala 581:26] + io.lsu_axi.w.bits.data <= obuf_data @[lsu_bus_buffer.scala 582:26] + io.lsu_axi.w.bits.last <= UInt<1>("h01") @[lsu_bus_buffer.scala 583:26] + node _T_4894 = eq(obuf_write, UInt<1>("h00")) @[lsu_bus_buffer.scala 585:39] + node _T_4895 = and(obuf_valid, _T_4894) @[lsu_bus_buffer.scala 585:37] + node _T_4896 = eq(obuf_nosend, UInt<1>("h00")) @[lsu_bus_buffer.scala 585:53] + node _T_4897 = and(_T_4895, _T_4896) @[lsu_bus_buffer.scala 585:51] + node _T_4898 = eq(bus_addr_match_pending, UInt<1>("h00")) @[lsu_bus_buffer.scala 585:68] + node _T_4899 = and(_T_4897, _T_4898) @[lsu_bus_buffer.scala 585:66] + io.lsu_axi.ar.valid <= _T_4899 @[lsu_bus_buffer.scala 585:23] + io.lsu_axi.ar.bits.id <= obuf_tag0 @[lsu_bus_buffer.scala 586:25] + node _T_4900 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 587:75] + node _T_4901 = cat(_T_4900, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_4902 = mux(obuf_sideeffect, obuf_addr, _T_4901) @[lsu_bus_buffer.scala 587:33] + io.lsu_axi.ar.bits.addr <= _T_4902 @[lsu_bus_buffer.scala 587:27] + node _T_4903 = cat(UInt<1>("h00"), obuf_sz) @[Cat.scala 29:58] + node _T_4904 = mux(obuf_sideeffect, _T_4903, UInt<3>("h03")) @[lsu_bus_buffer.scala 588:33] + io.lsu_axi.ar.bits.size <= _T_4904 @[lsu_bus_buffer.scala 588:27] + io.lsu_axi.ar.bits.prot <= UInt<1>("h00") @[lsu_bus_buffer.scala 589:27] + node _T_4905 = mux(obuf_sideeffect, UInt<4>("h00"), UInt<4>("h0f")) @[lsu_bus_buffer.scala 590:34] + io.lsu_axi.ar.bits.cache <= _T_4905 @[lsu_bus_buffer.scala 590:28] + node _T_4906 = bits(obuf_addr, 31, 28) @[lsu_bus_buffer.scala 591:41] + io.lsu_axi.ar.bits.region <= _T_4906 @[lsu_bus_buffer.scala 591:29] + io.lsu_axi.ar.bits.len <= UInt<1>("h00") @[lsu_bus_buffer.scala 592:26] + io.lsu_axi.ar.bits.burst <= UInt<2>("h01") @[lsu_bus_buffer.scala 593:28] + io.lsu_axi.ar.bits.qos <= UInt<1>("h00") @[lsu_bus_buffer.scala 594:26] + io.lsu_axi.ar.bits.lock <= UInt<1>("h00") @[lsu_bus_buffer.scala 595:27] + io.lsu_axi.b.ready <= UInt<1>("h01") @[lsu_bus_buffer.scala 596:22] + io.lsu_axi.r.ready <= UInt<1>("h01") @[lsu_bus_buffer.scala 597:22] + node _T_4907 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 598:93] + node _T_4908 = bits(buf_error, 0, 0) @[lsu_bus_buffer.scala 598:137] + node _T_4909 = and(io.lsu_bus_clk_en_q, _T_4908) @[lsu_bus_buffer.scala 598:126] + node _T_4910 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 598:152] + node _T_4911 = and(_T_4909, _T_4910) @[lsu_bus_buffer.scala 598:141] + node _T_4912 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 598:93] + node _T_4913 = bits(buf_error, 1, 1) @[lsu_bus_buffer.scala 598:137] + node _T_4914 = and(io.lsu_bus_clk_en_q, _T_4913) @[lsu_bus_buffer.scala 598:126] + node _T_4915 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 598:152] + node _T_4916 = and(_T_4914, _T_4915) @[lsu_bus_buffer.scala 598:141] + node _T_4917 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 598:93] + node _T_4918 = bits(buf_error, 2, 2) @[lsu_bus_buffer.scala 598:137] + node _T_4919 = and(io.lsu_bus_clk_en_q, _T_4918) @[lsu_bus_buffer.scala 598:126] + node _T_4920 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 598:152] + node _T_4921 = and(_T_4919, _T_4920) @[lsu_bus_buffer.scala 598:141] + node _T_4922 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 598:93] + node _T_4923 = bits(buf_error, 3, 3) @[lsu_bus_buffer.scala 598:137] + node _T_4924 = and(io.lsu_bus_clk_en_q, _T_4923) @[lsu_bus_buffer.scala 598:126] + node _T_4925 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 598:152] + node _T_4926 = and(_T_4924, _T_4925) @[lsu_bus_buffer.scala 598:141] + node _T_4927 = mux(_T_4907, _T_4911, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4928 = mux(_T_4912, _T_4916, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4929 = mux(_T_4917, _T_4921, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4930 = mux(_T_4922, _T_4926, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4931 = or(_T_4927, _T_4928) @[Mux.scala 27:72] + node _T_4932 = or(_T_4931, _T_4929) @[Mux.scala 27:72] + node _T_4933 = or(_T_4932, _T_4930) @[Mux.scala 27:72] + wire _T_4934 : UInt<1> @[Mux.scala 27:72] + _T_4934 <= _T_4933 @[Mux.scala 27:72] + io.tlu_busbuff.lsu_imprecise_error_store_any <= _T_4934 @[lsu_bus_buffer.scala 598:48] + node _T_4935 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 599:82] + node _T_4936 = bits(buf_error, 0, 0) @[lsu_bus_buffer.scala 599:104] + node _T_4937 = and(_T_4935, _T_4936) @[lsu_bus_buffer.scala 599:93] + node _T_4938 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 599:119] + node _T_4939 = and(_T_4937, _T_4938) @[lsu_bus_buffer.scala 599:108] + node _T_4940 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 599:82] + node _T_4941 = bits(buf_error, 1, 1) @[lsu_bus_buffer.scala 599:104] + node _T_4942 = and(_T_4940, _T_4941) @[lsu_bus_buffer.scala 599:93] + node _T_4943 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 599:119] + node _T_4944 = and(_T_4942, _T_4943) @[lsu_bus_buffer.scala 599:108] + node _T_4945 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 599:82] + node _T_4946 = bits(buf_error, 2, 2) @[lsu_bus_buffer.scala 599:104] + node _T_4947 = and(_T_4945, _T_4946) @[lsu_bus_buffer.scala 599:93] + node _T_4948 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 599:119] + node _T_4949 = and(_T_4947, _T_4948) @[lsu_bus_buffer.scala 599:108] + node _T_4950 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 599:82] + node _T_4951 = bits(buf_error, 3, 3) @[lsu_bus_buffer.scala 599:104] + node _T_4952 = and(_T_4950, _T_4951) @[lsu_bus_buffer.scala 599:93] + node _T_4953 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 599:119] + node _T_4954 = and(_T_4952, _T_4953) @[lsu_bus_buffer.scala 599:108] + node _T_4955 = mux(_T_4939, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4956 = mux(_T_4944, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4957 = mux(_T_4949, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4958 = mux(_T_4954, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4959 = or(_T_4955, _T_4956) @[Mux.scala 27:72] + node _T_4960 = or(_T_4959, _T_4957) @[Mux.scala 27:72] + node _T_4961 = or(_T_4960, _T_4958) @[Mux.scala 27:72] + wire lsu_imprecise_error_store_tag : UInt<2> @[Mux.scala 27:72] + lsu_imprecise_error_store_tag <= _T_4961 @[Mux.scala 27:72] + node _T_4962 = eq(io.tlu_busbuff.lsu_imprecise_error_store_any, UInt<1>("h00")) @[lsu_bus_buffer.scala 601:97] + node _T_4963 = and(io.dctl_busbuff.lsu_nonblock_load_data_error, _T_4962) @[lsu_bus_buffer.scala 601:95] + io.tlu_busbuff.lsu_imprecise_error_load_any <= _T_4963 @[lsu_bus_buffer.scala 601:47] + node _T_4964 = mux(io.tlu_busbuff.lsu_imprecise_error_store_any, buf_addr[lsu_imprecise_error_store_tag], buf_addr[io.dctl_busbuff.lsu_nonblock_load_data_tag]) @[lsu_bus_buffer.scala 602:53] + io.tlu_busbuff.lsu_imprecise_error_addr_any <= _T_4964 @[lsu_bus_buffer.scala 602:47] + lsu_bus_cntr_overflow <= UInt<1>("h00") @[lsu_bus_buffer.scala 603:25] + io.lsu_bus_idle_any <= UInt<1>("h01") @[lsu_bus_buffer.scala 605:23] + node _T_4965 = and(io.lsu_axi.aw.valid, io.lsu_axi.aw.ready) @[lsu_bus_buffer.scala 608:59] + node _T_4966 = and(io.lsu_axi.w.valid, io.lsu_axi.w.ready) @[lsu_bus_buffer.scala 608:104] + node _T_4967 = or(_T_4965, _T_4966) @[lsu_bus_buffer.scala 608:82] + node _T_4968 = and(io.lsu_axi.ar.valid, io.lsu_axi.ar.ready) @[lsu_bus_buffer.scala 608:149] + node _T_4969 = or(_T_4967, _T_4968) @[lsu_bus_buffer.scala 608:126] + io.tlu_busbuff.lsu_pmu_bus_trxn <= _T_4969 @[lsu_bus_buffer.scala 608:35] + node _T_4970 = and(io.lsu_busreq_r, io.ldst_dual_r) @[lsu_bus_buffer.scala 609:60] + node _T_4971 = and(_T_4970, io.lsu_commit_r) @[lsu_bus_buffer.scala 609:77] + io.tlu_busbuff.lsu_pmu_bus_misaligned <= _T_4971 @[lsu_bus_buffer.scala 609:41] + node _T_4972 = or(io.tlu_busbuff.lsu_imprecise_error_load_any, io.tlu_busbuff.lsu_imprecise_error_store_any) @[lsu_bus_buffer.scala 610:83] + io.tlu_busbuff.lsu_pmu_bus_error <= _T_4972 @[lsu_bus_buffer.scala 610:36] + node _T_4973 = eq(io.lsu_axi.aw.ready, UInt<1>("h00")) @[lsu_bus_buffer.scala 612:61] + node _T_4974 = and(io.lsu_axi.aw.valid, _T_4973) @[lsu_bus_buffer.scala 612:59] + node _T_4975 = eq(io.lsu_axi.w.ready, UInt<1>("h00")) @[lsu_bus_buffer.scala 612:107] + node _T_4976 = and(io.lsu_axi.w.valid, _T_4975) @[lsu_bus_buffer.scala 612:105] + node _T_4977 = or(_T_4974, _T_4976) @[lsu_bus_buffer.scala 612:83] + node _T_4978 = eq(io.lsu_axi.ar.ready, UInt<1>("h00")) @[lsu_bus_buffer.scala 612:153] + node _T_4979 = and(io.lsu_axi.ar.valid, _T_4978) @[lsu_bus_buffer.scala 612:151] + node _T_4980 = or(_T_4977, _T_4979) @[lsu_bus_buffer.scala 612:128] + io.tlu_busbuff.lsu_pmu_bus_busy <= _T_4980 @[lsu_bus_buffer.scala 612:35] + reg _T_4981 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 614:49] + _T_4981 <= WrPtr0_m @[lsu_bus_buffer.scala 614:49] + WrPtr0_r <= _T_4981 @[lsu_bus_buffer.scala 614:12] + reg _T_4982 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 615:49] + _T_4982 <= WrPtr1_m @[lsu_bus_buffer.scala 615:49] + WrPtr1_r <= _T_4982 @[lsu_bus_buffer.scala 615:12] + node _T_4983 = eq(io.flush_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 616:75] + node _T_4984 = and(io.lsu_busreq_m, _T_4983) @[lsu_bus_buffer.scala 616:73] + node _T_4985 = eq(io.ld_full_hit_m, UInt<1>("h00")) @[lsu_bus_buffer.scala 616:89] + node _T_4986 = and(_T_4984, _T_4985) @[lsu_bus_buffer.scala 616:87] + reg _T_4987 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 616:56] + _T_4987 <= _T_4986 @[lsu_bus_buffer.scala 616:56] + io.lsu_busreq_r <= _T_4987 @[lsu_bus_buffer.scala 616:19] + reg _T_4988 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 617:66] + _T_4988 <= io.dctl_busbuff.lsu_nonblock_load_valid_m @[lsu_bus_buffer.scala 617:66] + lsu_nonblock_load_valid_r <= _T_4988 @[lsu_bus_buffer.scala 617:29] + diff --git a/lsu_bus_buffer.v b/lsu_bus_buffer.v new file mode 100644 index 00000000..c27ee5f6 --- /dev/null +++ b/lsu_bus_buffer.v @@ -0,0 +1,4586 @@ +module rvclkhdr( + output io_l1clk, + input io_clk, + input io_en, + input io_scan_mode +); + wire clkhdr_Q; // @[lib.scala 334:26] + wire clkhdr_CK; // @[lib.scala 334:26] + wire clkhdr_EN; // @[lib.scala 334:26] + wire clkhdr_SE; // @[lib.scala 334:26] + gated_latch clkhdr ( // @[lib.scala 334:26] + .Q(clkhdr_Q), + .CK(clkhdr_CK), + .EN(clkhdr_EN), + .SE(clkhdr_SE) + ); + assign io_l1clk = clkhdr_Q; // @[lib.scala 335:14] + assign clkhdr_CK = io_clk; // @[lib.scala 336:18] + assign clkhdr_EN = io_en; // @[lib.scala 337:18] + assign clkhdr_SE = io_scan_mode; // @[lib.scala 338:18] +endmodule +module lsu_bus_buffer( + input clock, + input reset, + input io_scan_mode, + output io_tlu_busbuff_lsu_pmu_bus_trxn, + output io_tlu_busbuff_lsu_pmu_bus_misaligned, + output io_tlu_busbuff_lsu_pmu_bus_error, + output io_tlu_busbuff_lsu_pmu_bus_busy, + input io_tlu_busbuff_dec_tlu_external_ldfwd_disable, + input io_tlu_busbuff_dec_tlu_wb_coalescing_disable, + input io_tlu_busbuff_dec_tlu_sideeffect_posted_disable, + output io_tlu_busbuff_lsu_imprecise_error_load_any, + output io_tlu_busbuff_lsu_imprecise_error_store_any, + output [31:0] io_tlu_busbuff_lsu_imprecise_error_addr_any, + output io_dctl_busbuff_lsu_nonblock_load_valid_m, + output [1:0] io_dctl_busbuff_lsu_nonblock_load_tag_m, + output io_dctl_busbuff_lsu_nonblock_load_inv_r, + output [1:0] io_dctl_busbuff_lsu_nonblock_load_inv_tag_r, + output io_dctl_busbuff_lsu_nonblock_load_data_valid, + output io_dctl_busbuff_lsu_nonblock_load_data_error, + output [1:0] io_dctl_busbuff_lsu_nonblock_load_data_tag, + output [31:0] io_dctl_busbuff_lsu_nonblock_load_data, + input io_dec_tlu_force_halt, + input io_lsu_c2_r_clk, + input io_lsu_bus_ibuf_c1_clk, + input io_lsu_bus_obuf_c1_clk, + input io_lsu_bus_buf_c1_clk, + input io_lsu_free_c2_clk, + input io_lsu_busm_clk, + input io_dec_lsu_valid_raw_d, + input io_lsu_pkt_m_valid, + input io_lsu_pkt_m_bits_fast_int, + input io_lsu_pkt_m_bits_by, + input io_lsu_pkt_m_bits_half, + input io_lsu_pkt_m_bits_word, + input io_lsu_pkt_m_bits_dword, + input io_lsu_pkt_m_bits_load, + input io_lsu_pkt_m_bits_store, + input io_lsu_pkt_m_bits_unsign, + input io_lsu_pkt_m_bits_dma, + input io_lsu_pkt_m_bits_store_data_bypass_d, + input io_lsu_pkt_m_bits_load_ldst_bypass_d, + input io_lsu_pkt_m_bits_store_data_bypass_m, + input io_lsu_pkt_r_valid, + input io_lsu_pkt_r_bits_fast_int, + input io_lsu_pkt_r_bits_by, + input io_lsu_pkt_r_bits_half, + input io_lsu_pkt_r_bits_word, + input io_lsu_pkt_r_bits_dword, + input io_lsu_pkt_r_bits_load, + input io_lsu_pkt_r_bits_store, + input io_lsu_pkt_r_bits_unsign, + input io_lsu_pkt_r_bits_dma, + input io_lsu_pkt_r_bits_store_data_bypass_d, + input io_lsu_pkt_r_bits_load_ldst_bypass_d, + input io_lsu_pkt_r_bits_store_data_bypass_m, + input [31:0] io_lsu_addr_m, + input [31:0] io_end_addr_m, + input [31:0] io_lsu_addr_r, + input [31:0] io_end_addr_r, + input [31:0] io_store_data_r, + input io_no_word_merge_r, + input io_no_dword_merge_r, + input io_lsu_busreq_m, + input io_ld_full_hit_m, + input io_flush_m_up, + input io_flush_r, + input io_lsu_commit_r, + input io_is_sideeffects_r, + input io_ldst_dual_d, + input io_ldst_dual_m, + input io_ldst_dual_r, + input [7:0] io_ldst_byteen_ext_m, + input io_lsu_axi_aw_ready, + output io_lsu_axi_aw_valid, + output [2:0] io_lsu_axi_aw_bits_id, + output [31:0] io_lsu_axi_aw_bits_addr, + output [3:0] io_lsu_axi_aw_bits_region, + output [7:0] io_lsu_axi_aw_bits_len, + output [2:0] io_lsu_axi_aw_bits_size, + output [1:0] io_lsu_axi_aw_bits_burst, + output io_lsu_axi_aw_bits_lock, + output [3:0] io_lsu_axi_aw_bits_cache, + output [2:0] io_lsu_axi_aw_bits_prot, + output [3:0] io_lsu_axi_aw_bits_qos, + input io_lsu_axi_w_ready, + output io_lsu_axi_w_valid, + output [63:0] io_lsu_axi_w_bits_data, + output [7:0] io_lsu_axi_w_bits_strb, + output io_lsu_axi_w_bits_last, + output io_lsu_axi_b_ready, + input io_lsu_axi_b_valid, + input [1:0] io_lsu_axi_b_bits_resp, + input [2:0] io_lsu_axi_b_bits_id, + input io_lsu_axi_ar_ready, + output io_lsu_axi_ar_valid, + output [2:0] io_lsu_axi_ar_bits_id, + output [31:0] io_lsu_axi_ar_bits_addr, + output [3:0] io_lsu_axi_ar_bits_region, + output [7:0] io_lsu_axi_ar_bits_len, + output [2:0] io_lsu_axi_ar_bits_size, + output [1:0] io_lsu_axi_ar_bits_burst, + output io_lsu_axi_ar_bits_lock, + output [3:0] io_lsu_axi_ar_bits_cache, + output [2:0] io_lsu_axi_ar_bits_prot, + output [3:0] io_lsu_axi_ar_bits_qos, + output io_lsu_axi_r_ready, + input io_lsu_axi_r_valid, + input [2:0] io_lsu_axi_r_bits_id, + input [63:0] io_lsu_axi_r_bits_data, + input [1:0] io_lsu_axi_r_bits_resp, + input io_lsu_axi_r_bits_last, + input io_lsu_bus_clk_en, + input io_lsu_bus_clk_en_q, + output io_lsu_busreq_r, + output io_lsu_bus_buffer_pend_any, + output io_lsu_bus_buffer_full_any, + output io_lsu_bus_buffer_empty_any, + output io_lsu_bus_idle_any, + output [3:0] io_ld_byte_hit_buf_lo, + output [3:0] io_ld_byte_hit_buf_hi, + output [31:0] io_ld_fwddata_buf_lo, + output [31:0] io_ld_fwddata_buf_hi +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; + reg [31:0] _RAND_15; + reg [31:0] _RAND_16; + reg [31:0] _RAND_17; + reg [31:0] _RAND_18; + reg [31:0] _RAND_19; + reg [31:0] _RAND_20; + reg [31:0] _RAND_21; + reg [31:0] _RAND_22; + reg [31:0] _RAND_23; + reg [31:0] _RAND_24; + reg [31:0] _RAND_25; + reg [31:0] _RAND_26; + reg [31:0] _RAND_27; + reg [31:0] _RAND_28; + reg [31:0] _RAND_29; + reg [31:0] _RAND_30; + reg [31:0] _RAND_31; + reg [31:0] _RAND_32; + reg [31:0] _RAND_33; + reg [31:0] _RAND_34; + reg [31:0] _RAND_35; + reg [31:0] _RAND_36; + reg [31:0] _RAND_37; + reg [31:0] _RAND_38; + reg [31:0] _RAND_39; + reg [31:0] _RAND_40; + reg [31:0] _RAND_41; + reg [31:0] _RAND_42; + reg [31:0] _RAND_43; + reg [31:0] _RAND_44; + reg [31:0] _RAND_45; + reg [31:0] _RAND_46; + reg [31:0] _RAND_47; + reg [31:0] _RAND_48; + reg [31:0] _RAND_49; + reg [31:0] _RAND_50; + reg [31:0] _RAND_51; + reg [31:0] _RAND_52; + reg [31:0] _RAND_53; + reg [31:0] _RAND_54; + reg [31:0] _RAND_55; + reg [31:0] _RAND_56; + reg [31:0] _RAND_57; + reg [31:0] _RAND_58; + reg [31:0] _RAND_59; + reg [31:0] _RAND_60; + reg [31:0] _RAND_61; + reg [31:0] _RAND_62; + reg [31:0] _RAND_63; + reg [31:0] _RAND_64; + reg [31:0] _RAND_65; + reg [31:0] _RAND_66; + reg [31:0] _RAND_67; + reg [31:0] _RAND_68; + reg [31:0] _RAND_69; + reg [31:0] _RAND_70; + reg [31:0] _RAND_71; + reg [31:0] _RAND_72; + reg [31:0] _RAND_73; + reg [31:0] _RAND_74; + reg [31:0] _RAND_75; + reg [31:0] _RAND_76; + reg [31:0] _RAND_77; + reg [31:0] _RAND_78; + reg [31:0] _RAND_79; + reg [63:0] _RAND_80; + reg [31:0] _RAND_81; + reg [31:0] _RAND_82; + reg [31:0] _RAND_83; + reg [31:0] _RAND_84; + reg [31:0] _RAND_85; + reg [31:0] _RAND_86; + reg [31:0] _RAND_87; + reg [31:0] _RAND_88; + reg [31:0] _RAND_89; + reg [31:0] _RAND_90; + reg [31:0] _RAND_91; + reg [31:0] _RAND_92; + reg [31:0] _RAND_93; + reg [31:0] _RAND_94; + reg [31:0] _RAND_95; + reg [31:0] _RAND_96; + reg [31:0] _RAND_97; + reg [31:0] _RAND_98; + reg [31:0] _RAND_99; + reg [31:0] _RAND_100; + reg [31:0] _RAND_101; + reg [31:0] _RAND_102; + reg [31:0] _RAND_103; + reg [31:0] _RAND_104; + reg [31:0] _RAND_105; + reg [31:0] _RAND_106; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_io_en; // @[lib.scala 368:23] + wire rvclkhdr_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_1_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_1_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_1_io_en; // @[lib.scala 368:23] + wire rvclkhdr_1_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_2_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_2_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_2_io_en; // @[lib.scala 368:23] + wire rvclkhdr_2_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_3_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_3_io_en; // @[lib.scala 368:23] + wire rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_4_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_4_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_4_io_en; // @[lib.scala 368:23] + wire rvclkhdr_4_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_5_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_5_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_5_io_en; // @[lib.scala 368:23] + wire rvclkhdr_5_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_6_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_6_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_6_io_en; // @[lib.scala 368:23] + wire rvclkhdr_6_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_7_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_7_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_7_io_en; // @[lib.scala 368:23] + wire rvclkhdr_7_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_8_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_8_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_8_io_en; // @[lib.scala 368:23] + wire rvclkhdr_8_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_9_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_9_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_9_io_en; // @[lib.scala 368:23] + wire rvclkhdr_9_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_10_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_10_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_10_io_en; // @[lib.scala 368:23] + wire rvclkhdr_10_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_11_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_11_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_11_io_en; // @[lib.scala 368:23] + wire rvclkhdr_11_io_scan_mode; // @[lib.scala 368:23] + wire [3:0] ldst_byteen_hi_m = io_ldst_byteen_ext_m[7:4]; // @[lsu_bus_buffer.scala 73:46] + wire [3:0] ldst_byteen_lo_m = io_ldst_byteen_ext_m[3:0]; // @[lsu_bus_buffer.scala 74:46] + reg [31:0] buf_addr_0; // @[lib.scala 374:16] + wire _T_2 = io_lsu_addr_m[31:2] == buf_addr_0[31:2]; // @[lsu_bus_buffer.scala 76:74] + reg _T_4360; // @[Reg.scala 27:20] + reg _T_4357; // @[Reg.scala 27:20] + reg _T_4354; // @[Reg.scala 27:20] + reg _T_4351; // @[Reg.scala 27:20] + wire [3:0] buf_write = {_T_4360,_T_4357,_T_4354,_T_4351}; // @[Cat.scala 29:58] + wire _T_4 = _T_2 & buf_write[0]; // @[lsu_bus_buffer.scala 76:98] + reg [2:0] buf_state_0; // @[Reg.scala 27:20] + wire _T_5 = buf_state_0 != 3'h0; // @[lsu_bus_buffer.scala 76:129] + wire _T_6 = _T_4 & _T_5; // @[lsu_bus_buffer.scala 76:113] + wire ld_addr_hitvec_lo_0 = _T_6 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 76:141] + reg [31:0] buf_addr_1; // @[lib.scala 374:16] + wire _T_9 = io_lsu_addr_m[31:2] == buf_addr_1[31:2]; // @[lsu_bus_buffer.scala 76:74] + wire _T_11 = _T_9 & buf_write[1]; // @[lsu_bus_buffer.scala 76:98] + reg [2:0] buf_state_1; // @[Reg.scala 27:20] + wire _T_12 = buf_state_1 != 3'h0; // @[lsu_bus_buffer.scala 76:129] + wire _T_13 = _T_11 & _T_12; // @[lsu_bus_buffer.scala 76:113] + wire ld_addr_hitvec_lo_1 = _T_13 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 76:141] + reg [31:0] buf_addr_2; // @[lib.scala 374:16] + wire _T_16 = io_lsu_addr_m[31:2] == buf_addr_2[31:2]; // @[lsu_bus_buffer.scala 76:74] + wire _T_18 = _T_16 & buf_write[2]; // @[lsu_bus_buffer.scala 76:98] + reg [2:0] buf_state_2; // @[Reg.scala 27:20] + wire _T_19 = buf_state_2 != 3'h0; // @[lsu_bus_buffer.scala 76:129] + wire _T_20 = _T_18 & _T_19; // @[lsu_bus_buffer.scala 76:113] + wire ld_addr_hitvec_lo_2 = _T_20 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 76:141] + reg [31:0] buf_addr_3; // @[lib.scala 374:16] + wire _T_23 = io_lsu_addr_m[31:2] == buf_addr_3[31:2]; // @[lsu_bus_buffer.scala 76:74] + wire _T_25 = _T_23 & buf_write[3]; // @[lsu_bus_buffer.scala 76:98] + reg [2:0] buf_state_3; // @[Reg.scala 27:20] + wire _T_26 = buf_state_3 != 3'h0; // @[lsu_bus_buffer.scala 76:129] + wire _T_27 = _T_25 & _T_26; // @[lsu_bus_buffer.scala 76:113] + wire ld_addr_hitvec_lo_3 = _T_27 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 76:141] + wire _T_30 = io_end_addr_m[31:2] == buf_addr_0[31:2]; // @[lsu_bus_buffer.scala 77:74] + wire _T_32 = _T_30 & buf_write[0]; // @[lsu_bus_buffer.scala 77:98] + wire _T_34 = _T_32 & _T_5; // @[lsu_bus_buffer.scala 77:113] + wire ld_addr_hitvec_hi_0 = _T_34 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 77:141] + wire _T_37 = io_end_addr_m[31:2] == buf_addr_1[31:2]; // @[lsu_bus_buffer.scala 77:74] + wire _T_39 = _T_37 & buf_write[1]; // @[lsu_bus_buffer.scala 77:98] + wire _T_41 = _T_39 & _T_12; // @[lsu_bus_buffer.scala 77:113] + wire ld_addr_hitvec_hi_1 = _T_41 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 77:141] + wire _T_44 = io_end_addr_m[31:2] == buf_addr_2[31:2]; // @[lsu_bus_buffer.scala 77:74] + wire _T_46 = _T_44 & buf_write[2]; // @[lsu_bus_buffer.scala 77:98] + wire _T_48 = _T_46 & _T_19; // @[lsu_bus_buffer.scala 77:113] + wire ld_addr_hitvec_hi_2 = _T_48 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 77:141] + wire _T_51 = io_end_addr_m[31:2] == buf_addr_3[31:2]; // @[lsu_bus_buffer.scala 77:74] + wire _T_53 = _T_51 & buf_write[3]; // @[lsu_bus_buffer.scala 77:98] + wire _T_55 = _T_53 & _T_26; // @[lsu_bus_buffer.scala 77:113] + wire ld_addr_hitvec_hi_3 = _T_55 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 77:141] + reg [3:0] buf_byteen_3; // @[Reg.scala 27:20] + wire _T_99 = ld_addr_hitvec_lo_3 & buf_byteen_3[0]; // @[lsu_bus_buffer.scala 141:95] + wire _T_101 = _T_99 & ldst_byteen_lo_m[0]; // @[lsu_bus_buffer.scala 141:114] + reg [3:0] buf_byteen_2; // @[Reg.scala 27:20] + wire _T_95 = ld_addr_hitvec_lo_2 & buf_byteen_2[0]; // @[lsu_bus_buffer.scala 141:95] + wire _T_97 = _T_95 & ldst_byteen_lo_m[0]; // @[lsu_bus_buffer.scala 141:114] + reg [3:0] buf_byteen_1; // @[Reg.scala 27:20] + wire _T_91 = ld_addr_hitvec_lo_1 & buf_byteen_1[0]; // @[lsu_bus_buffer.scala 141:95] + wire _T_93 = _T_91 & ldst_byteen_lo_m[0]; // @[lsu_bus_buffer.scala 141:114] + reg [3:0] buf_byteen_0; // @[Reg.scala 27:20] + wire _T_87 = ld_addr_hitvec_lo_0 & buf_byteen_0[0]; // @[lsu_bus_buffer.scala 141:95] + wire _T_89 = _T_87 & ldst_byteen_lo_m[0]; // @[lsu_bus_buffer.scala 141:114] + wire [3:0] ld_byte_hitvec_lo_0 = {_T_101,_T_97,_T_93,_T_89}; // @[Cat.scala 29:58] + reg [3:0] buf_ageQ_3; // @[lsu_bus_buffer.scala 499:60] + wire _T_2621 = buf_state_3 == 3'h2; // @[lsu_bus_buffer.scala 411:93] + wire _T_4107 = 3'h0 == buf_state_3; // @[Conditional.scala 37:30] + wire _T_4130 = 3'h1 == buf_state_3; // @[Conditional.scala 37:30] + wire _T_4134 = 3'h2 == buf_state_3; // @[Conditional.scala 37:30] + reg [1:0] _T_1848; // @[Reg.scala 27:20] + wire [2:0] obuf_tag0 = {{1'd0}, _T_1848}; // @[lsu_bus_buffer.scala 351:13] + wire _T_4141 = obuf_tag0 == 3'h3; // @[lsu_bus_buffer.scala 454:48] + reg obuf_merge; // @[Reg.scala 27:20] + reg [1:0] obuf_tag1; // @[Reg.scala 27:20] + wire [2:0] _GEN_358 = {{1'd0}, obuf_tag1}; // @[lsu_bus_buffer.scala 454:104] + wire _T_4142 = _GEN_358 == 3'h3; // @[lsu_bus_buffer.scala 454:104] + wire _T_4143 = obuf_merge & _T_4142; // @[lsu_bus_buffer.scala 454:91] + wire _T_4144 = _T_4141 | _T_4143; // @[lsu_bus_buffer.scala 454:77] + reg obuf_valid; // @[lsu_bus_buffer.scala 345:54] + wire _T_4145 = _T_4144 & obuf_valid; // @[lsu_bus_buffer.scala 454:135] + reg obuf_wr_enQ; // @[lsu_bus_buffer.scala 344:55] + wire _T_4146 = _T_4145 & obuf_wr_enQ; // @[lsu_bus_buffer.scala 454:148] + wire _GEN_280 = _T_4134 & _T_4146; // @[Conditional.scala 39:67] + wire _GEN_293 = _T_4130 ? 1'h0 : _GEN_280; // @[Conditional.scala 39:67] + wire buf_cmd_state_bus_en_3 = _T_4107 ? 1'h0 : _GEN_293; // @[Conditional.scala 40:58] + wire _T_2622 = _T_2621 & buf_cmd_state_bus_en_3; // @[lsu_bus_buffer.scala 411:103] + wire _T_2623 = ~_T_2622; // @[lsu_bus_buffer.scala 411:78] + wire _T_2624 = buf_ageQ_3[3] & _T_2623; // @[lsu_bus_buffer.scala 411:76] + wire _T_2616 = buf_state_2 == 3'h2; // @[lsu_bus_buffer.scala 411:93] + wire _T_3914 = 3'h0 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_3937 = 3'h1 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_3941 = 3'h2 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_3948 = obuf_tag0 == 3'h2; // @[lsu_bus_buffer.scala 454:48] + wire _T_3949 = _GEN_358 == 3'h2; // @[lsu_bus_buffer.scala 454:104] + wire _T_3950 = obuf_merge & _T_3949; // @[lsu_bus_buffer.scala 454:91] + wire _T_3951 = _T_3948 | _T_3950; // @[lsu_bus_buffer.scala 454:77] + wire _T_3952 = _T_3951 & obuf_valid; // @[lsu_bus_buffer.scala 454:135] + wire _T_3953 = _T_3952 & obuf_wr_enQ; // @[lsu_bus_buffer.scala 454:148] + wire _GEN_204 = _T_3941 & _T_3953; // @[Conditional.scala 39:67] + wire _GEN_217 = _T_3937 ? 1'h0 : _GEN_204; // @[Conditional.scala 39:67] + wire buf_cmd_state_bus_en_2 = _T_3914 ? 1'h0 : _GEN_217; // @[Conditional.scala 40:58] + wire _T_2617 = _T_2616 & buf_cmd_state_bus_en_2; // @[lsu_bus_buffer.scala 411:103] + wire _T_2618 = ~_T_2617; // @[lsu_bus_buffer.scala 411:78] + wire _T_2619 = buf_ageQ_3[2] & _T_2618; // @[lsu_bus_buffer.scala 411:76] + wire _T_2611 = buf_state_1 == 3'h2; // @[lsu_bus_buffer.scala 411:93] + wire _T_3721 = 3'h0 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_3744 = 3'h1 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_3748 = 3'h2 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_3755 = obuf_tag0 == 3'h1; // @[lsu_bus_buffer.scala 454:48] + wire _T_3756 = _GEN_358 == 3'h1; // @[lsu_bus_buffer.scala 454:104] + wire _T_3757 = obuf_merge & _T_3756; // @[lsu_bus_buffer.scala 454:91] + wire _T_3758 = _T_3755 | _T_3757; // @[lsu_bus_buffer.scala 454:77] + wire _T_3759 = _T_3758 & obuf_valid; // @[lsu_bus_buffer.scala 454:135] + wire _T_3760 = _T_3759 & obuf_wr_enQ; // @[lsu_bus_buffer.scala 454:148] + wire _GEN_128 = _T_3748 & _T_3760; // @[Conditional.scala 39:67] + wire _GEN_141 = _T_3744 ? 1'h0 : _GEN_128; // @[Conditional.scala 39:67] + wire buf_cmd_state_bus_en_1 = _T_3721 ? 1'h0 : _GEN_141; // @[Conditional.scala 40:58] + wire _T_2612 = _T_2611 & buf_cmd_state_bus_en_1; // @[lsu_bus_buffer.scala 411:103] + wire _T_2613 = ~_T_2612; // @[lsu_bus_buffer.scala 411:78] + wire _T_2614 = buf_ageQ_3[1] & _T_2613; // @[lsu_bus_buffer.scala 411:76] + wire _T_2606 = buf_state_0 == 3'h2; // @[lsu_bus_buffer.scala 411:93] + wire _T_3528 = 3'h0 == buf_state_0; // @[Conditional.scala 37:30] + wire _T_3551 = 3'h1 == buf_state_0; // @[Conditional.scala 37:30] + wire _T_3555 = 3'h2 == buf_state_0; // @[Conditional.scala 37:30] + wire _T_3562 = obuf_tag0 == 3'h0; // @[lsu_bus_buffer.scala 454:48] + wire _T_3563 = _GEN_358 == 3'h0; // @[lsu_bus_buffer.scala 454:104] + wire _T_3564 = obuf_merge & _T_3563; // @[lsu_bus_buffer.scala 454:91] + wire _T_3565 = _T_3562 | _T_3564; // @[lsu_bus_buffer.scala 454:77] + wire _T_3566 = _T_3565 & obuf_valid; // @[lsu_bus_buffer.scala 454:135] + wire _T_3567 = _T_3566 & obuf_wr_enQ; // @[lsu_bus_buffer.scala 454:148] + wire _GEN_52 = _T_3555 & _T_3567; // @[Conditional.scala 39:67] + wire _GEN_65 = _T_3551 ? 1'h0 : _GEN_52; // @[Conditional.scala 39:67] + wire buf_cmd_state_bus_en_0 = _T_3528 ? 1'h0 : _GEN_65; // @[Conditional.scala 40:58] + wire _T_2607 = _T_2606 & buf_cmd_state_bus_en_0; // @[lsu_bus_buffer.scala 411:103] + wire _T_2608 = ~_T_2607; // @[lsu_bus_buffer.scala 411:78] + wire _T_2609 = buf_ageQ_3[0] & _T_2608; // @[lsu_bus_buffer.scala 411:76] + wire [3:0] buf_age_3 = {_T_2624,_T_2619,_T_2614,_T_2609}; // @[Cat.scala 29:58] + wire _T_2723 = ~buf_age_3[2]; // @[lsu_bus_buffer.scala 412:89] + wire _T_2725 = _T_2723 & _T_19; // @[lsu_bus_buffer.scala 412:104] + wire _T_2717 = ~buf_age_3[1]; // @[lsu_bus_buffer.scala 412:89] + wire _T_2719 = _T_2717 & _T_12; // @[lsu_bus_buffer.scala 412:104] + wire _T_2711 = ~buf_age_3[0]; // @[lsu_bus_buffer.scala 412:89] + wire _T_2713 = _T_2711 & _T_5; // @[lsu_bus_buffer.scala 412:104] + wire [3:0] buf_age_younger_3 = {1'h0,_T_2725,_T_2719,_T_2713}; // @[Cat.scala 29:58] + wire [3:0] _T_255 = ld_byte_hitvec_lo_0 & buf_age_younger_3; // @[lsu_bus_buffer.scala 146:122] + wire _T_256 = |_T_255; // @[lsu_bus_buffer.scala 146:144] + wire _T_257 = ~_T_256; // @[lsu_bus_buffer.scala 146:99] + wire _T_258 = ld_byte_hitvec_lo_0[3] & _T_257; // @[lsu_bus_buffer.scala 146:97] + reg [31:0] ibuf_addr; // @[lib.scala 374:16] + wire _T_512 = io_lsu_addr_m[31:2] == ibuf_addr[31:2]; // @[lsu_bus_buffer.scala 152:51] + reg ibuf_write; // @[Reg.scala 27:20] + wire _T_513 = _T_512 & ibuf_write; // @[lsu_bus_buffer.scala 152:73] + reg ibuf_valid; // @[lsu_bus_buffer.scala 239:54] + wire _T_514 = _T_513 & ibuf_valid; // @[lsu_bus_buffer.scala 152:86] + wire ld_addr_ibuf_hit_lo = _T_514 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 152:99] + wire [3:0] _T_521 = ld_addr_ibuf_hit_lo ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + reg [3:0] ibuf_byteen; // @[Reg.scala 27:20] + wire [3:0] _T_522 = _T_521 & ibuf_byteen; // @[lsu_bus_buffer.scala 157:55] + wire [3:0] ld_byte_ibuf_hit_lo = _T_522 & ldst_byteen_lo_m; // @[lsu_bus_buffer.scala 157:69] + wire _T_260 = ~ld_byte_ibuf_hit_lo[0]; // @[lsu_bus_buffer.scala 146:150] + wire _T_261 = _T_258 & _T_260; // @[lsu_bus_buffer.scala 146:148] + reg [3:0] buf_ageQ_2; // @[lsu_bus_buffer.scala 499:60] + wire _T_2601 = buf_ageQ_2[3] & _T_2623; // @[lsu_bus_buffer.scala 411:76] + wire _T_2596 = buf_ageQ_2[2] & _T_2618; // @[lsu_bus_buffer.scala 411:76] + wire _T_2591 = buf_ageQ_2[1] & _T_2613; // @[lsu_bus_buffer.scala 411:76] + wire _T_2586 = buf_ageQ_2[0] & _T_2608; // @[lsu_bus_buffer.scala 411:76] + wire [3:0] buf_age_2 = {_T_2601,_T_2596,_T_2591,_T_2586}; // @[Cat.scala 29:58] + wire _T_2702 = ~buf_age_2[3]; // @[lsu_bus_buffer.scala 412:89] + wire _T_2704 = _T_2702 & _T_26; // @[lsu_bus_buffer.scala 412:104] + wire _T_2690 = ~buf_age_2[1]; // @[lsu_bus_buffer.scala 412:89] + wire _T_2692 = _T_2690 & _T_12; // @[lsu_bus_buffer.scala 412:104] + wire _T_2684 = ~buf_age_2[0]; // @[lsu_bus_buffer.scala 412:89] + wire _T_2686 = _T_2684 & _T_5; // @[lsu_bus_buffer.scala 412:104] + wire [3:0] buf_age_younger_2 = {_T_2704,1'h0,_T_2692,_T_2686}; // @[Cat.scala 29:58] + wire [3:0] _T_247 = ld_byte_hitvec_lo_0 & buf_age_younger_2; // @[lsu_bus_buffer.scala 146:122] + wire _T_248 = |_T_247; // @[lsu_bus_buffer.scala 146:144] + wire _T_249 = ~_T_248; // @[lsu_bus_buffer.scala 146:99] + wire _T_250 = ld_byte_hitvec_lo_0[2] & _T_249; // @[lsu_bus_buffer.scala 146:97] + wire _T_253 = _T_250 & _T_260; // @[lsu_bus_buffer.scala 146:148] + reg [3:0] buf_ageQ_1; // @[lsu_bus_buffer.scala 499:60] + wire _T_2578 = buf_ageQ_1[3] & _T_2623; // @[lsu_bus_buffer.scala 411:76] + wire _T_2573 = buf_ageQ_1[2] & _T_2618; // @[lsu_bus_buffer.scala 411:76] + wire _T_2568 = buf_ageQ_1[1] & _T_2613; // @[lsu_bus_buffer.scala 411:76] + wire _T_2563 = buf_ageQ_1[0] & _T_2608; // @[lsu_bus_buffer.scala 411:76] + wire [3:0] buf_age_1 = {_T_2578,_T_2573,_T_2568,_T_2563}; // @[Cat.scala 29:58] + wire _T_2675 = ~buf_age_1[3]; // @[lsu_bus_buffer.scala 412:89] + wire _T_2677 = _T_2675 & _T_26; // @[lsu_bus_buffer.scala 412:104] + wire _T_2669 = ~buf_age_1[2]; // @[lsu_bus_buffer.scala 412:89] + wire _T_2671 = _T_2669 & _T_19; // @[lsu_bus_buffer.scala 412:104] + wire _T_2657 = ~buf_age_1[0]; // @[lsu_bus_buffer.scala 412:89] + wire _T_2659 = _T_2657 & _T_5; // @[lsu_bus_buffer.scala 412:104] + wire [3:0] buf_age_younger_1 = {_T_2677,_T_2671,1'h0,_T_2659}; // @[Cat.scala 29:58] + wire [3:0] _T_239 = ld_byte_hitvec_lo_0 & buf_age_younger_1; // @[lsu_bus_buffer.scala 146:122] + wire _T_240 = |_T_239; // @[lsu_bus_buffer.scala 146:144] + wire _T_241 = ~_T_240; // @[lsu_bus_buffer.scala 146:99] + wire _T_242 = ld_byte_hitvec_lo_0[1] & _T_241; // @[lsu_bus_buffer.scala 146:97] + wire _T_245 = _T_242 & _T_260; // @[lsu_bus_buffer.scala 146:148] + reg [3:0] buf_ageQ_0; // @[lsu_bus_buffer.scala 499:60] + wire _T_2555 = buf_ageQ_0[3] & _T_2623; // @[lsu_bus_buffer.scala 411:76] + wire _T_2550 = buf_ageQ_0[2] & _T_2618; // @[lsu_bus_buffer.scala 411:76] + wire _T_2545 = buf_ageQ_0[1] & _T_2613; // @[lsu_bus_buffer.scala 411:76] + wire _T_2540 = buf_ageQ_0[0] & _T_2608; // @[lsu_bus_buffer.scala 411:76] + wire [3:0] buf_age_0 = {_T_2555,_T_2550,_T_2545,_T_2540}; // @[Cat.scala 29:58] + wire _T_2648 = ~buf_age_0[3]; // @[lsu_bus_buffer.scala 412:89] + wire _T_2650 = _T_2648 & _T_26; // @[lsu_bus_buffer.scala 412:104] + wire _T_2642 = ~buf_age_0[2]; // @[lsu_bus_buffer.scala 412:89] + wire _T_2644 = _T_2642 & _T_19; // @[lsu_bus_buffer.scala 412:104] + wire _T_2636 = ~buf_age_0[1]; // @[lsu_bus_buffer.scala 412:89] + wire _T_2638 = _T_2636 & _T_12; // @[lsu_bus_buffer.scala 412:104] + wire [3:0] buf_age_younger_0 = {_T_2650,_T_2644,_T_2638,1'h0}; // @[Cat.scala 29:58] + wire [3:0] _T_231 = ld_byte_hitvec_lo_0 & buf_age_younger_0; // @[lsu_bus_buffer.scala 146:122] + wire _T_232 = |_T_231; // @[lsu_bus_buffer.scala 146:144] + wire _T_233 = ~_T_232; // @[lsu_bus_buffer.scala 146:99] + wire _T_234 = ld_byte_hitvec_lo_0[0] & _T_233; // @[lsu_bus_buffer.scala 146:97] + wire _T_237 = _T_234 & _T_260; // @[lsu_bus_buffer.scala 146:148] + wire [3:0] ld_byte_hitvecfn_lo_0 = {_T_261,_T_253,_T_245,_T_237}; // @[Cat.scala 29:58] + wire _T_56 = |ld_byte_hitvecfn_lo_0; // @[lsu_bus_buffer.scala 138:73] + wire _T_58 = _T_56 | ld_byte_ibuf_hit_lo[0]; // @[lsu_bus_buffer.scala 138:77] + wire _T_117 = ld_addr_hitvec_lo_3 & buf_byteen_3[1]; // @[lsu_bus_buffer.scala 141:95] + wire _T_119 = _T_117 & ldst_byteen_lo_m[1]; // @[lsu_bus_buffer.scala 141:114] + wire _T_113 = ld_addr_hitvec_lo_2 & buf_byteen_2[1]; // @[lsu_bus_buffer.scala 141:95] + wire _T_115 = _T_113 & ldst_byteen_lo_m[1]; // @[lsu_bus_buffer.scala 141:114] + wire _T_109 = ld_addr_hitvec_lo_1 & buf_byteen_1[1]; // @[lsu_bus_buffer.scala 141:95] + wire _T_111 = _T_109 & ldst_byteen_lo_m[1]; // @[lsu_bus_buffer.scala 141:114] + wire _T_105 = ld_addr_hitvec_lo_0 & buf_byteen_0[1]; // @[lsu_bus_buffer.scala 141:95] + wire _T_107 = _T_105 & ldst_byteen_lo_m[1]; // @[lsu_bus_buffer.scala 141:114] + wire [3:0] ld_byte_hitvec_lo_1 = {_T_119,_T_115,_T_111,_T_107}; // @[Cat.scala 29:58] + wire [3:0] _T_290 = ld_byte_hitvec_lo_1 & buf_age_younger_3; // @[lsu_bus_buffer.scala 146:122] + wire _T_291 = |_T_290; // @[lsu_bus_buffer.scala 146:144] + wire _T_292 = ~_T_291; // @[lsu_bus_buffer.scala 146:99] + wire _T_293 = ld_byte_hitvec_lo_1[3] & _T_292; // @[lsu_bus_buffer.scala 146:97] + wire _T_295 = ~ld_byte_ibuf_hit_lo[1]; // @[lsu_bus_buffer.scala 146:150] + wire _T_296 = _T_293 & _T_295; // @[lsu_bus_buffer.scala 146:148] + wire [3:0] _T_282 = ld_byte_hitvec_lo_1 & buf_age_younger_2; // @[lsu_bus_buffer.scala 146:122] + wire _T_283 = |_T_282; // @[lsu_bus_buffer.scala 146:144] + wire _T_284 = ~_T_283; // @[lsu_bus_buffer.scala 146:99] + wire _T_285 = ld_byte_hitvec_lo_1[2] & _T_284; // @[lsu_bus_buffer.scala 146:97] + wire _T_288 = _T_285 & _T_295; // @[lsu_bus_buffer.scala 146:148] + wire [3:0] _T_274 = ld_byte_hitvec_lo_1 & buf_age_younger_1; // @[lsu_bus_buffer.scala 146:122] + wire _T_275 = |_T_274; // @[lsu_bus_buffer.scala 146:144] + wire _T_276 = ~_T_275; // @[lsu_bus_buffer.scala 146:99] + wire _T_277 = ld_byte_hitvec_lo_1[1] & _T_276; // @[lsu_bus_buffer.scala 146:97] + wire _T_280 = _T_277 & _T_295; // @[lsu_bus_buffer.scala 146:148] + wire [3:0] _T_266 = ld_byte_hitvec_lo_1 & buf_age_younger_0; // @[lsu_bus_buffer.scala 146:122] + wire _T_267 = |_T_266; // @[lsu_bus_buffer.scala 146:144] + wire _T_268 = ~_T_267; // @[lsu_bus_buffer.scala 146:99] + wire _T_269 = ld_byte_hitvec_lo_1[0] & _T_268; // @[lsu_bus_buffer.scala 146:97] + wire _T_272 = _T_269 & _T_295; // @[lsu_bus_buffer.scala 146:148] + wire [3:0] ld_byte_hitvecfn_lo_1 = {_T_296,_T_288,_T_280,_T_272}; // @[Cat.scala 29:58] + wire _T_59 = |ld_byte_hitvecfn_lo_1; // @[lsu_bus_buffer.scala 138:73] + wire _T_61 = _T_59 | ld_byte_ibuf_hit_lo[1]; // @[lsu_bus_buffer.scala 138:77] + wire _T_135 = ld_addr_hitvec_lo_3 & buf_byteen_3[2]; // @[lsu_bus_buffer.scala 141:95] + wire _T_137 = _T_135 & ldst_byteen_lo_m[2]; // @[lsu_bus_buffer.scala 141:114] + wire _T_131 = ld_addr_hitvec_lo_2 & buf_byteen_2[2]; // @[lsu_bus_buffer.scala 141:95] + wire _T_133 = _T_131 & ldst_byteen_lo_m[2]; // @[lsu_bus_buffer.scala 141:114] + wire _T_127 = ld_addr_hitvec_lo_1 & buf_byteen_1[2]; // @[lsu_bus_buffer.scala 141:95] + wire _T_129 = _T_127 & ldst_byteen_lo_m[2]; // @[lsu_bus_buffer.scala 141:114] + wire _T_123 = ld_addr_hitvec_lo_0 & buf_byteen_0[2]; // @[lsu_bus_buffer.scala 141:95] + wire _T_125 = _T_123 & ldst_byteen_lo_m[2]; // @[lsu_bus_buffer.scala 141:114] + wire [3:0] ld_byte_hitvec_lo_2 = {_T_137,_T_133,_T_129,_T_125}; // @[Cat.scala 29:58] + wire [3:0] _T_325 = ld_byte_hitvec_lo_2 & buf_age_younger_3; // @[lsu_bus_buffer.scala 146:122] + wire _T_326 = |_T_325; // @[lsu_bus_buffer.scala 146:144] + wire _T_327 = ~_T_326; // @[lsu_bus_buffer.scala 146:99] + wire _T_328 = ld_byte_hitvec_lo_2[3] & _T_327; // @[lsu_bus_buffer.scala 146:97] + wire _T_330 = ~ld_byte_ibuf_hit_lo[2]; // @[lsu_bus_buffer.scala 146:150] + wire _T_331 = _T_328 & _T_330; // @[lsu_bus_buffer.scala 146:148] + wire [3:0] _T_317 = ld_byte_hitvec_lo_2 & buf_age_younger_2; // @[lsu_bus_buffer.scala 146:122] + wire _T_318 = |_T_317; // @[lsu_bus_buffer.scala 146:144] + wire _T_319 = ~_T_318; // @[lsu_bus_buffer.scala 146:99] + wire _T_320 = ld_byte_hitvec_lo_2[2] & _T_319; // @[lsu_bus_buffer.scala 146:97] + wire _T_323 = _T_320 & _T_330; // @[lsu_bus_buffer.scala 146:148] + wire [3:0] _T_309 = ld_byte_hitvec_lo_2 & buf_age_younger_1; // @[lsu_bus_buffer.scala 146:122] + wire _T_310 = |_T_309; // @[lsu_bus_buffer.scala 146:144] + wire _T_311 = ~_T_310; // @[lsu_bus_buffer.scala 146:99] + wire _T_312 = ld_byte_hitvec_lo_2[1] & _T_311; // @[lsu_bus_buffer.scala 146:97] + wire _T_315 = _T_312 & _T_330; // @[lsu_bus_buffer.scala 146:148] + wire [3:0] _T_301 = ld_byte_hitvec_lo_2 & buf_age_younger_0; // @[lsu_bus_buffer.scala 146:122] + wire _T_302 = |_T_301; // @[lsu_bus_buffer.scala 146:144] + wire _T_303 = ~_T_302; // @[lsu_bus_buffer.scala 146:99] + wire _T_304 = ld_byte_hitvec_lo_2[0] & _T_303; // @[lsu_bus_buffer.scala 146:97] + wire _T_307 = _T_304 & _T_330; // @[lsu_bus_buffer.scala 146:148] + wire [3:0] ld_byte_hitvecfn_lo_2 = {_T_331,_T_323,_T_315,_T_307}; // @[Cat.scala 29:58] + wire _T_62 = |ld_byte_hitvecfn_lo_2; // @[lsu_bus_buffer.scala 138:73] + wire _T_64 = _T_62 | ld_byte_ibuf_hit_lo[2]; // @[lsu_bus_buffer.scala 138:77] + wire _T_153 = ld_addr_hitvec_lo_3 & buf_byteen_3[3]; // @[lsu_bus_buffer.scala 141:95] + wire _T_155 = _T_153 & ldst_byteen_lo_m[3]; // @[lsu_bus_buffer.scala 141:114] + wire _T_149 = ld_addr_hitvec_lo_2 & buf_byteen_2[3]; // @[lsu_bus_buffer.scala 141:95] + wire _T_151 = _T_149 & ldst_byteen_lo_m[3]; // @[lsu_bus_buffer.scala 141:114] + wire _T_145 = ld_addr_hitvec_lo_1 & buf_byteen_1[3]; // @[lsu_bus_buffer.scala 141:95] + wire _T_147 = _T_145 & ldst_byteen_lo_m[3]; // @[lsu_bus_buffer.scala 141:114] + wire _T_141 = ld_addr_hitvec_lo_0 & buf_byteen_0[3]; // @[lsu_bus_buffer.scala 141:95] + wire _T_143 = _T_141 & ldst_byteen_lo_m[3]; // @[lsu_bus_buffer.scala 141:114] + wire [3:0] ld_byte_hitvec_lo_3 = {_T_155,_T_151,_T_147,_T_143}; // @[Cat.scala 29:58] + wire [3:0] _T_360 = ld_byte_hitvec_lo_3 & buf_age_younger_3; // @[lsu_bus_buffer.scala 146:122] + wire _T_361 = |_T_360; // @[lsu_bus_buffer.scala 146:144] + wire _T_362 = ~_T_361; // @[lsu_bus_buffer.scala 146:99] + wire _T_363 = ld_byte_hitvec_lo_3[3] & _T_362; // @[lsu_bus_buffer.scala 146:97] + wire _T_365 = ~ld_byte_ibuf_hit_lo[3]; // @[lsu_bus_buffer.scala 146:150] + wire _T_366 = _T_363 & _T_365; // @[lsu_bus_buffer.scala 146:148] + wire [3:0] _T_352 = ld_byte_hitvec_lo_3 & buf_age_younger_2; // @[lsu_bus_buffer.scala 146:122] + wire _T_353 = |_T_352; // @[lsu_bus_buffer.scala 146:144] + wire _T_354 = ~_T_353; // @[lsu_bus_buffer.scala 146:99] + wire _T_355 = ld_byte_hitvec_lo_3[2] & _T_354; // @[lsu_bus_buffer.scala 146:97] + wire _T_358 = _T_355 & _T_365; // @[lsu_bus_buffer.scala 146:148] + wire [3:0] _T_344 = ld_byte_hitvec_lo_3 & buf_age_younger_1; // @[lsu_bus_buffer.scala 146:122] + wire _T_345 = |_T_344; // @[lsu_bus_buffer.scala 146:144] + wire _T_346 = ~_T_345; // @[lsu_bus_buffer.scala 146:99] + wire _T_347 = ld_byte_hitvec_lo_3[1] & _T_346; // @[lsu_bus_buffer.scala 146:97] + wire _T_350 = _T_347 & _T_365; // @[lsu_bus_buffer.scala 146:148] + wire [3:0] _T_336 = ld_byte_hitvec_lo_3 & buf_age_younger_0; // @[lsu_bus_buffer.scala 146:122] + wire _T_337 = |_T_336; // @[lsu_bus_buffer.scala 146:144] + wire _T_338 = ~_T_337; // @[lsu_bus_buffer.scala 146:99] + wire _T_339 = ld_byte_hitvec_lo_3[0] & _T_338; // @[lsu_bus_buffer.scala 146:97] + wire _T_342 = _T_339 & _T_365; // @[lsu_bus_buffer.scala 146:148] + wire [3:0] ld_byte_hitvecfn_lo_3 = {_T_366,_T_358,_T_350,_T_342}; // @[Cat.scala 29:58] + wire _T_65 = |ld_byte_hitvecfn_lo_3; // @[lsu_bus_buffer.scala 138:73] + wire _T_67 = _T_65 | ld_byte_ibuf_hit_lo[3]; // @[lsu_bus_buffer.scala 138:77] + wire [2:0] _T_69 = {_T_67,_T_64,_T_61}; // @[Cat.scala 29:58] + wire _T_171 = ld_addr_hitvec_hi_3 & buf_byteen_3[0]; // @[lsu_bus_buffer.scala 142:95] + wire _T_173 = _T_171 & ldst_byteen_hi_m[0]; // @[lsu_bus_buffer.scala 142:114] + wire _T_167 = ld_addr_hitvec_hi_2 & buf_byteen_2[0]; // @[lsu_bus_buffer.scala 142:95] + wire _T_169 = _T_167 & ldst_byteen_hi_m[0]; // @[lsu_bus_buffer.scala 142:114] + wire _T_163 = ld_addr_hitvec_hi_1 & buf_byteen_1[0]; // @[lsu_bus_buffer.scala 142:95] + wire _T_165 = _T_163 & ldst_byteen_hi_m[0]; // @[lsu_bus_buffer.scala 142:114] + wire _T_159 = ld_addr_hitvec_hi_0 & buf_byteen_0[0]; // @[lsu_bus_buffer.scala 142:95] + wire _T_161 = _T_159 & ldst_byteen_hi_m[0]; // @[lsu_bus_buffer.scala 142:114] + wire [3:0] ld_byte_hitvec_hi_0 = {_T_173,_T_169,_T_165,_T_161}; // @[Cat.scala 29:58] + wire [3:0] _T_395 = ld_byte_hitvec_hi_0 & buf_age_younger_3; // @[lsu_bus_buffer.scala 147:122] + wire _T_396 = |_T_395; // @[lsu_bus_buffer.scala 147:144] + wire _T_397 = ~_T_396; // @[lsu_bus_buffer.scala 147:99] + wire _T_398 = ld_byte_hitvec_hi_0[3] & _T_397; // @[lsu_bus_buffer.scala 147:97] + wire _T_517 = io_end_addr_m[31:2] == ibuf_addr[31:2]; // @[lsu_bus_buffer.scala 153:51] + wire _T_518 = _T_517 & ibuf_write; // @[lsu_bus_buffer.scala 153:73] + wire _T_519 = _T_518 & ibuf_valid; // @[lsu_bus_buffer.scala 153:86] + wire ld_addr_ibuf_hit_hi = _T_519 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 153:99] + wire [3:0] _T_525 = ld_addr_ibuf_hit_hi ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_526 = _T_525 & ibuf_byteen; // @[lsu_bus_buffer.scala 158:55] + wire [3:0] ld_byte_ibuf_hit_hi = _T_526 & ldst_byteen_hi_m; // @[lsu_bus_buffer.scala 158:69] + wire _T_400 = ~ld_byte_ibuf_hit_hi[0]; // @[lsu_bus_buffer.scala 147:150] + wire _T_401 = _T_398 & _T_400; // @[lsu_bus_buffer.scala 147:148] + wire [3:0] _T_387 = ld_byte_hitvec_hi_0 & buf_age_younger_2; // @[lsu_bus_buffer.scala 147:122] + wire _T_388 = |_T_387; // @[lsu_bus_buffer.scala 147:144] + wire _T_389 = ~_T_388; // @[lsu_bus_buffer.scala 147:99] + wire _T_390 = ld_byte_hitvec_hi_0[2] & _T_389; // @[lsu_bus_buffer.scala 147:97] + wire _T_393 = _T_390 & _T_400; // @[lsu_bus_buffer.scala 147:148] + wire [3:0] _T_379 = ld_byte_hitvec_hi_0 & buf_age_younger_1; // @[lsu_bus_buffer.scala 147:122] + wire _T_380 = |_T_379; // @[lsu_bus_buffer.scala 147:144] + wire _T_381 = ~_T_380; // @[lsu_bus_buffer.scala 147:99] + wire _T_382 = ld_byte_hitvec_hi_0[1] & _T_381; // @[lsu_bus_buffer.scala 147:97] + wire _T_385 = _T_382 & _T_400; // @[lsu_bus_buffer.scala 147:148] + wire [3:0] _T_371 = ld_byte_hitvec_hi_0 & buf_age_younger_0; // @[lsu_bus_buffer.scala 147:122] + wire _T_372 = |_T_371; // @[lsu_bus_buffer.scala 147:144] + wire _T_373 = ~_T_372; // @[lsu_bus_buffer.scala 147:99] + wire _T_374 = ld_byte_hitvec_hi_0[0] & _T_373; // @[lsu_bus_buffer.scala 147:97] + wire _T_377 = _T_374 & _T_400; // @[lsu_bus_buffer.scala 147:148] + wire [3:0] ld_byte_hitvecfn_hi_0 = {_T_401,_T_393,_T_385,_T_377}; // @[Cat.scala 29:58] + wire _T_71 = |ld_byte_hitvecfn_hi_0; // @[lsu_bus_buffer.scala 139:73] + wire _T_73 = _T_71 | ld_byte_ibuf_hit_hi[0]; // @[lsu_bus_buffer.scala 139:77] + wire _T_189 = ld_addr_hitvec_hi_3 & buf_byteen_3[1]; // @[lsu_bus_buffer.scala 142:95] + wire _T_191 = _T_189 & ldst_byteen_hi_m[1]; // @[lsu_bus_buffer.scala 142:114] + wire _T_185 = ld_addr_hitvec_hi_2 & buf_byteen_2[1]; // @[lsu_bus_buffer.scala 142:95] + wire _T_187 = _T_185 & ldst_byteen_hi_m[1]; // @[lsu_bus_buffer.scala 142:114] + wire _T_181 = ld_addr_hitvec_hi_1 & buf_byteen_1[1]; // @[lsu_bus_buffer.scala 142:95] + wire _T_183 = _T_181 & ldst_byteen_hi_m[1]; // @[lsu_bus_buffer.scala 142:114] + wire _T_177 = ld_addr_hitvec_hi_0 & buf_byteen_0[1]; // @[lsu_bus_buffer.scala 142:95] + wire _T_179 = _T_177 & ldst_byteen_hi_m[1]; // @[lsu_bus_buffer.scala 142:114] + wire [3:0] ld_byte_hitvec_hi_1 = {_T_191,_T_187,_T_183,_T_179}; // @[Cat.scala 29:58] + wire [3:0] _T_430 = ld_byte_hitvec_hi_1 & buf_age_younger_3; // @[lsu_bus_buffer.scala 147:122] + wire _T_431 = |_T_430; // @[lsu_bus_buffer.scala 147:144] + wire _T_432 = ~_T_431; // @[lsu_bus_buffer.scala 147:99] + wire _T_433 = ld_byte_hitvec_hi_1[3] & _T_432; // @[lsu_bus_buffer.scala 147:97] + wire _T_435 = ~ld_byte_ibuf_hit_hi[1]; // @[lsu_bus_buffer.scala 147:150] + wire _T_436 = _T_433 & _T_435; // @[lsu_bus_buffer.scala 147:148] + wire [3:0] _T_422 = ld_byte_hitvec_hi_1 & buf_age_younger_2; // @[lsu_bus_buffer.scala 147:122] + wire _T_423 = |_T_422; // @[lsu_bus_buffer.scala 147:144] + wire _T_424 = ~_T_423; // @[lsu_bus_buffer.scala 147:99] + wire _T_425 = ld_byte_hitvec_hi_1[2] & _T_424; // @[lsu_bus_buffer.scala 147:97] + wire _T_428 = _T_425 & _T_435; // @[lsu_bus_buffer.scala 147:148] + wire [3:0] _T_414 = ld_byte_hitvec_hi_1 & buf_age_younger_1; // @[lsu_bus_buffer.scala 147:122] + wire _T_415 = |_T_414; // @[lsu_bus_buffer.scala 147:144] + wire _T_416 = ~_T_415; // @[lsu_bus_buffer.scala 147:99] + wire _T_417 = ld_byte_hitvec_hi_1[1] & _T_416; // @[lsu_bus_buffer.scala 147:97] + wire _T_420 = _T_417 & _T_435; // @[lsu_bus_buffer.scala 147:148] + wire [3:0] _T_406 = ld_byte_hitvec_hi_1 & buf_age_younger_0; // @[lsu_bus_buffer.scala 147:122] + wire _T_407 = |_T_406; // @[lsu_bus_buffer.scala 147:144] + wire _T_408 = ~_T_407; // @[lsu_bus_buffer.scala 147:99] + wire _T_409 = ld_byte_hitvec_hi_1[0] & _T_408; // @[lsu_bus_buffer.scala 147:97] + wire _T_412 = _T_409 & _T_435; // @[lsu_bus_buffer.scala 147:148] + wire [3:0] ld_byte_hitvecfn_hi_1 = {_T_436,_T_428,_T_420,_T_412}; // @[Cat.scala 29:58] + wire _T_74 = |ld_byte_hitvecfn_hi_1; // @[lsu_bus_buffer.scala 139:73] + wire _T_76 = _T_74 | ld_byte_ibuf_hit_hi[1]; // @[lsu_bus_buffer.scala 139:77] + wire _T_207 = ld_addr_hitvec_hi_3 & buf_byteen_3[2]; // @[lsu_bus_buffer.scala 142:95] + wire _T_209 = _T_207 & ldst_byteen_hi_m[2]; // @[lsu_bus_buffer.scala 142:114] + wire _T_203 = ld_addr_hitvec_hi_2 & buf_byteen_2[2]; // @[lsu_bus_buffer.scala 142:95] + wire _T_205 = _T_203 & ldst_byteen_hi_m[2]; // @[lsu_bus_buffer.scala 142:114] + wire _T_199 = ld_addr_hitvec_hi_1 & buf_byteen_1[2]; // @[lsu_bus_buffer.scala 142:95] + wire _T_201 = _T_199 & ldst_byteen_hi_m[2]; // @[lsu_bus_buffer.scala 142:114] + wire _T_195 = ld_addr_hitvec_hi_0 & buf_byteen_0[2]; // @[lsu_bus_buffer.scala 142:95] + wire _T_197 = _T_195 & ldst_byteen_hi_m[2]; // @[lsu_bus_buffer.scala 142:114] + wire [3:0] ld_byte_hitvec_hi_2 = {_T_209,_T_205,_T_201,_T_197}; // @[Cat.scala 29:58] + wire [3:0] _T_465 = ld_byte_hitvec_hi_2 & buf_age_younger_3; // @[lsu_bus_buffer.scala 147:122] + wire _T_466 = |_T_465; // @[lsu_bus_buffer.scala 147:144] + wire _T_467 = ~_T_466; // @[lsu_bus_buffer.scala 147:99] + wire _T_468 = ld_byte_hitvec_hi_2[3] & _T_467; // @[lsu_bus_buffer.scala 147:97] + wire _T_470 = ~ld_byte_ibuf_hit_hi[2]; // @[lsu_bus_buffer.scala 147:150] + wire _T_471 = _T_468 & _T_470; // @[lsu_bus_buffer.scala 147:148] + wire [3:0] _T_457 = ld_byte_hitvec_hi_2 & buf_age_younger_2; // @[lsu_bus_buffer.scala 147:122] + wire _T_458 = |_T_457; // @[lsu_bus_buffer.scala 147:144] + wire _T_459 = ~_T_458; // @[lsu_bus_buffer.scala 147:99] + wire _T_460 = ld_byte_hitvec_hi_2[2] & _T_459; // @[lsu_bus_buffer.scala 147:97] + wire _T_463 = _T_460 & _T_470; // @[lsu_bus_buffer.scala 147:148] + wire [3:0] _T_449 = ld_byte_hitvec_hi_2 & buf_age_younger_1; // @[lsu_bus_buffer.scala 147:122] + wire _T_450 = |_T_449; // @[lsu_bus_buffer.scala 147:144] + wire _T_451 = ~_T_450; // @[lsu_bus_buffer.scala 147:99] + wire _T_452 = ld_byte_hitvec_hi_2[1] & _T_451; // @[lsu_bus_buffer.scala 147:97] + wire _T_455 = _T_452 & _T_470; // @[lsu_bus_buffer.scala 147:148] + wire [3:0] _T_441 = ld_byte_hitvec_hi_2 & buf_age_younger_0; // @[lsu_bus_buffer.scala 147:122] + wire _T_442 = |_T_441; // @[lsu_bus_buffer.scala 147:144] + wire _T_443 = ~_T_442; // @[lsu_bus_buffer.scala 147:99] + wire _T_444 = ld_byte_hitvec_hi_2[0] & _T_443; // @[lsu_bus_buffer.scala 147:97] + wire _T_447 = _T_444 & _T_470; // @[lsu_bus_buffer.scala 147:148] + wire [3:0] ld_byte_hitvecfn_hi_2 = {_T_471,_T_463,_T_455,_T_447}; // @[Cat.scala 29:58] + wire _T_77 = |ld_byte_hitvecfn_hi_2; // @[lsu_bus_buffer.scala 139:73] + wire _T_79 = _T_77 | ld_byte_ibuf_hit_hi[2]; // @[lsu_bus_buffer.scala 139:77] + wire _T_225 = ld_addr_hitvec_hi_3 & buf_byteen_3[3]; // @[lsu_bus_buffer.scala 142:95] + wire _T_227 = _T_225 & ldst_byteen_hi_m[3]; // @[lsu_bus_buffer.scala 142:114] + wire _T_221 = ld_addr_hitvec_hi_2 & buf_byteen_2[3]; // @[lsu_bus_buffer.scala 142:95] + wire _T_223 = _T_221 & ldst_byteen_hi_m[3]; // @[lsu_bus_buffer.scala 142:114] + wire _T_217 = ld_addr_hitvec_hi_1 & buf_byteen_1[3]; // @[lsu_bus_buffer.scala 142:95] + wire _T_219 = _T_217 & ldst_byteen_hi_m[3]; // @[lsu_bus_buffer.scala 142:114] + wire _T_213 = ld_addr_hitvec_hi_0 & buf_byteen_0[3]; // @[lsu_bus_buffer.scala 142:95] + wire _T_215 = _T_213 & ldst_byteen_hi_m[3]; // @[lsu_bus_buffer.scala 142:114] + wire [3:0] ld_byte_hitvec_hi_3 = {_T_227,_T_223,_T_219,_T_215}; // @[Cat.scala 29:58] + wire [3:0] _T_500 = ld_byte_hitvec_hi_3 & buf_age_younger_3; // @[lsu_bus_buffer.scala 147:122] + wire _T_501 = |_T_500; // @[lsu_bus_buffer.scala 147:144] + wire _T_502 = ~_T_501; // @[lsu_bus_buffer.scala 147:99] + wire _T_503 = ld_byte_hitvec_hi_3[3] & _T_502; // @[lsu_bus_buffer.scala 147:97] + wire _T_505 = ~ld_byte_ibuf_hit_hi[3]; // @[lsu_bus_buffer.scala 147:150] + wire _T_506 = _T_503 & _T_505; // @[lsu_bus_buffer.scala 147:148] + wire [3:0] _T_492 = ld_byte_hitvec_hi_3 & buf_age_younger_2; // @[lsu_bus_buffer.scala 147:122] + wire _T_493 = |_T_492; // @[lsu_bus_buffer.scala 147:144] + wire _T_494 = ~_T_493; // @[lsu_bus_buffer.scala 147:99] + wire _T_495 = ld_byte_hitvec_hi_3[2] & _T_494; // @[lsu_bus_buffer.scala 147:97] + wire _T_498 = _T_495 & _T_505; // @[lsu_bus_buffer.scala 147:148] + wire [3:0] _T_484 = ld_byte_hitvec_hi_3 & buf_age_younger_1; // @[lsu_bus_buffer.scala 147:122] + wire _T_485 = |_T_484; // @[lsu_bus_buffer.scala 147:144] + wire _T_486 = ~_T_485; // @[lsu_bus_buffer.scala 147:99] + wire _T_487 = ld_byte_hitvec_hi_3[1] & _T_486; // @[lsu_bus_buffer.scala 147:97] + wire _T_490 = _T_487 & _T_505; // @[lsu_bus_buffer.scala 147:148] + wire [3:0] _T_476 = ld_byte_hitvec_hi_3 & buf_age_younger_0; // @[lsu_bus_buffer.scala 147:122] + wire _T_477 = |_T_476; // @[lsu_bus_buffer.scala 147:144] + wire _T_478 = ~_T_477; // @[lsu_bus_buffer.scala 147:99] + wire _T_479 = ld_byte_hitvec_hi_3[0] & _T_478; // @[lsu_bus_buffer.scala 147:97] + wire _T_482 = _T_479 & _T_505; // @[lsu_bus_buffer.scala 147:148] + wire [3:0] ld_byte_hitvecfn_hi_3 = {_T_506,_T_498,_T_490,_T_482}; // @[Cat.scala 29:58] + wire _T_80 = |ld_byte_hitvecfn_hi_3; // @[lsu_bus_buffer.scala 139:73] + wire _T_82 = _T_80 | ld_byte_ibuf_hit_hi[3]; // @[lsu_bus_buffer.scala 139:77] + wire [2:0] _T_84 = {_T_82,_T_79,_T_76}; // @[Cat.scala 29:58] + wire [7:0] _T_530 = ld_byte_ibuf_hit_lo[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_533 = ld_byte_ibuf_hit_lo[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_536 = ld_byte_ibuf_hit_lo[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_539 = ld_byte_ibuf_hit_lo[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [31:0] ld_fwddata_buf_lo_initial = {_T_539,_T_536,_T_533,_T_530}; // @[Cat.scala 29:58] + wire [7:0] _T_544 = ld_byte_ibuf_hit_hi[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_547 = ld_byte_ibuf_hit_hi[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_550 = ld_byte_ibuf_hit_hi[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_553 = ld_byte_ibuf_hit_hi[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [31:0] ld_fwddata_buf_hi_initial = {_T_553,_T_550,_T_547,_T_544}; // @[Cat.scala 29:58] + wire [7:0] _T_558 = ld_byte_hitvecfn_lo_3[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + reg [31:0] buf_data_0; // @[lib.scala 374:16] + wire [7:0] _T_560 = _T_558 & buf_data_0[31:24]; // @[lsu_bus_buffer.scala 165:91] + wire [7:0] _T_563 = ld_byte_hitvecfn_lo_3[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + reg [31:0] buf_data_1; // @[lib.scala 374:16] + wire [7:0] _T_565 = _T_563 & buf_data_1[31:24]; // @[lsu_bus_buffer.scala 165:91] + wire [7:0] _T_568 = ld_byte_hitvecfn_lo_3[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + reg [31:0] buf_data_2; // @[lib.scala 374:16] + wire [7:0] _T_570 = _T_568 & buf_data_2[31:24]; // @[lsu_bus_buffer.scala 165:91] + wire [7:0] _T_573 = ld_byte_hitvecfn_lo_3[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + reg [31:0] buf_data_3; // @[lib.scala 374:16] + wire [7:0] _T_575 = _T_573 & buf_data_3[31:24]; // @[lsu_bus_buffer.scala 165:91] + wire [7:0] _T_576 = _T_560 | _T_565; // @[lsu_bus_buffer.scala 165:123] + wire [7:0] _T_577 = _T_576 | _T_570; // @[lsu_bus_buffer.scala 165:123] + wire [7:0] _T_578 = _T_577 | _T_575; // @[lsu_bus_buffer.scala 165:123] + wire [7:0] _T_581 = ld_byte_hitvecfn_lo_2[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_583 = _T_581 & buf_data_0[23:16]; // @[lsu_bus_buffer.scala 166:65] + wire [7:0] _T_586 = ld_byte_hitvecfn_lo_2[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_588 = _T_586 & buf_data_1[23:16]; // @[lsu_bus_buffer.scala 166:65] + wire [7:0] _T_591 = ld_byte_hitvecfn_lo_2[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_593 = _T_591 & buf_data_2[23:16]; // @[lsu_bus_buffer.scala 166:65] + wire [7:0] _T_596 = ld_byte_hitvecfn_lo_2[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_598 = _T_596 & buf_data_3[23:16]; // @[lsu_bus_buffer.scala 166:65] + wire [7:0] _T_599 = _T_583 | _T_588; // @[lsu_bus_buffer.scala 166:97] + wire [7:0] _T_600 = _T_599 | _T_593; // @[lsu_bus_buffer.scala 166:97] + wire [7:0] _T_601 = _T_600 | _T_598; // @[lsu_bus_buffer.scala 166:97] + wire [7:0] _T_604 = ld_byte_hitvecfn_lo_1[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_606 = _T_604 & buf_data_0[15:8]; // @[lsu_bus_buffer.scala 167:65] + wire [7:0] _T_609 = ld_byte_hitvecfn_lo_1[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_611 = _T_609 & buf_data_1[15:8]; // @[lsu_bus_buffer.scala 167:65] + wire [7:0] _T_614 = ld_byte_hitvecfn_lo_1[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_616 = _T_614 & buf_data_2[15:8]; // @[lsu_bus_buffer.scala 167:65] + wire [7:0] _T_619 = ld_byte_hitvecfn_lo_1[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_621 = _T_619 & buf_data_3[15:8]; // @[lsu_bus_buffer.scala 167:65] + wire [7:0] _T_622 = _T_606 | _T_611; // @[lsu_bus_buffer.scala 167:97] + wire [7:0] _T_623 = _T_622 | _T_616; // @[lsu_bus_buffer.scala 167:97] + wire [7:0] _T_624 = _T_623 | _T_621; // @[lsu_bus_buffer.scala 167:97] + wire [7:0] _T_627 = ld_byte_hitvecfn_lo_0[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_629 = _T_627 & buf_data_0[7:0]; // @[lsu_bus_buffer.scala 168:65] + wire [7:0] _T_632 = ld_byte_hitvecfn_lo_0[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_634 = _T_632 & buf_data_1[7:0]; // @[lsu_bus_buffer.scala 168:65] + wire [7:0] _T_637 = ld_byte_hitvecfn_lo_0[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_639 = _T_637 & buf_data_2[7:0]; // @[lsu_bus_buffer.scala 168:65] + wire [7:0] _T_642 = ld_byte_hitvecfn_lo_0[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_644 = _T_642 & buf_data_3[7:0]; // @[lsu_bus_buffer.scala 168:65] + wire [7:0] _T_645 = _T_629 | _T_634; // @[lsu_bus_buffer.scala 168:97] + wire [7:0] _T_646 = _T_645 | _T_639; // @[lsu_bus_buffer.scala 168:97] + wire [7:0] _T_647 = _T_646 | _T_644; // @[lsu_bus_buffer.scala 168:97] + wire [31:0] _T_650 = {_T_578,_T_601,_T_624,_T_647}; // @[Cat.scala 29:58] + reg [31:0] ibuf_data; // @[lib.scala 374:16] + wire [31:0] _T_651 = ld_fwddata_buf_lo_initial & ibuf_data; // @[lsu_bus_buffer.scala 169:32] + wire [7:0] _T_655 = ld_byte_hitvecfn_hi_3[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_657 = _T_655 & buf_data_0[31:24]; // @[lsu_bus_buffer.scala 171:91] + wire [7:0] _T_660 = ld_byte_hitvecfn_hi_3[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_662 = _T_660 & buf_data_1[31:24]; // @[lsu_bus_buffer.scala 171:91] + wire [7:0] _T_665 = ld_byte_hitvecfn_hi_3[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_667 = _T_665 & buf_data_2[31:24]; // @[lsu_bus_buffer.scala 171:91] + wire [7:0] _T_670 = ld_byte_hitvecfn_hi_3[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_672 = _T_670 & buf_data_3[31:24]; // @[lsu_bus_buffer.scala 171:91] + wire [7:0] _T_673 = _T_657 | _T_662; // @[lsu_bus_buffer.scala 171:123] + wire [7:0] _T_674 = _T_673 | _T_667; // @[lsu_bus_buffer.scala 171:123] + wire [7:0] _T_675 = _T_674 | _T_672; // @[lsu_bus_buffer.scala 171:123] + wire [7:0] _T_678 = ld_byte_hitvecfn_hi_2[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_680 = _T_678 & buf_data_0[23:16]; // @[lsu_bus_buffer.scala 172:65] + wire [7:0] _T_683 = ld_byte_hitvecfn_hi_2[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_685 = _T_683 & buf_data_1[23:16]; // @[lsu_bus_buffer.scala 172:65] + wire [7:0] _T_688 = ld_byte_hitvecfn_hi_2[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_690 = _T_688 & buf_data_2[23:16]; // @[lsu_bus_buffer.scala 172:65] + wire [7:0] _T_693 = ld_byte_hitvecfn_hi_2[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_695 = _T_693 & buf_data_3[23:16]; // @[lsu_bus_buffer.scala 172:65] + wire [7:0] _T_696 = _T_680 | _T_685; // @[lsu_bus_buffer.scala 172:97] + wire [7:0] _T_697 = _T_696 | _T_690; // @[lsu_bus_buffer.scala 172:97] + wire [7:0] _T_698 = _T_697 | _T_695; // @[lsu_bus_buffer.scala 172:97] + wire [7:0] _T_701 = ld_byte_hitvecfn_hi_1[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_703 = _T_701 & buf_data_0[15:8]; // @[lsu_bus_buffer.scala 173:65] + wire [7:0] _T_706 = ld_byte_hitvecfn_hi_1[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_708 = _T_706 & buf_data_1[15:8]; // @[lsu_bus_buffer.scala 173:65] + wire [7:0] _T_711 = ld_byte_hitvecfn_hi_1[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_713 = _T_711 & buf_data_2[15:8]; // @[lsu_bus_buffer.scala 173:65] + wire [7:0] _T_716 = ld_byte_hitvecfn_hi_1[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_718 = _T_716 & buf_data_3[15:8]; // @[lsu_bus_buffer.scala 173:65] + wire [7:0] _T_719 = _T_703 | _T_708; // @[lsu_bus_buffer.scala 173:97] + wire [7:0] _T_720 = _T_719 | _T_713; // @[lsu_bus_buffer.scala 173:97] + wire [7:0] _T_721 = _T_720 | _T_718; // @[lsu_bus_buffer.scala 173:97] + wire [7:0] _T_724 = ld_byte_hitvecfn_hi_0[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_726 = _T_724 & buf_data_0[7:0]; // @[lsu_bus_buffer.scala 174:65] + wire [7:0] _T_729 = ld_byte_hitvecfn_hi_0[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_731 = _T_729 & buf_data_1[7:0]; // @[lsu_bus_buffer.scala 174:65] + wire [7:0] _T_734 = ld_byte_hitvecfn_hi_0[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_736 = _T_734 & buf_data_2[7:0]; // @[lsu_bus_buffer.scala 174:65] + wire [7:0] _T_739 = ld_byte_hitvecfn_hi_0[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_741 = _T_739 & buf_data_3[7:0]; // @[lsu_bus_buffer.scala 174:65] + wire [7:0] _T_742 = _T_726 | _T_731; // @[lsu_bus_buffer.scala 174:97] + wire [7:0] _T_743 = _T_742 | _T_736; // @[lsu_bus_buffer.scala 174:97] + wire [7:0] _T_744 = _T_743 | _T_741; // @[lsu_bus_buffer.scala 174:97] + wire [31:0] _T_747 = {_T_675,_T_698,_T_721,_T_744}; // @[Cat.scala 29:58] + wire [31:0] _T_748 = ld_fwddata_buf_hi_initial & ibuf_data; // @[lsu_bus_buffer.scala 175:32] + wire [3:0] _T_750 = io_lsu_pkt_r_bits_by ? 4'h1 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_751 = io_lsu_pkt_r_bits_half ? 4'h3 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_752 = io_lsu_pkt_r_bits_word ? 4'hf : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_753 = _T_750 | _T_751; // @[Mux.scala 27:72] + wire [3:0] ldst_byteen_r = _T_753 | _T_752; // @[Mux.scala 27:72] + wire _T_756 = io_lsu_addr_r[1:0] == 2'h0; // @[lsu_bus_buffer.scala 182:55] + wire _T_758 = io_lsu_addr_r[1:0] == 2'h1; // @[lsu_bus_buffer.scala 183:24] + wire [3:0] _T_760 = {3'h0,ldst_byteen_r[3]}; // @[Cat.scala 29:58] + wire _T_762 = io_lsu_addr_r[1:0] == 2'h2; // @[lsu_bus_buffer.scala 184:24] + wire [3:0] _T_764 = {2'h0,ldst_byteen_r[3:2]}; // @[Cat.scala 29:58] + wire _T_766 = io_lsu_addr_r[1:0] == 2'h3; // @[lsu_bus_buffer.scala 185:24] + wire [3:0] _T_768 = {1'h0,ldst_byteen_r[3:1]}; // @[Cat.scala 29:58] + wire [3:0] _T_770 = _T_758 ? _T_760 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_771 = _T_762 ? _T_764 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_772 = _T_766 ? _T_768 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_774 = _T_770 | _T_771; // @[Mux.scala 27:72] + wire [3:0] ldst_byteen_hi_r = _T_774 | _T_772; // @[Mux.scala 27:72] + wire [3:0] _T_781 = {ldst_byteen_r[2:0],1'h0}; // @[Cat.scala 29:58] + wire [3:0] _T_785 = {ldst_byteen_r[1:0],2'h0}; // @[Cat.scala 29:58] + wire [3:0] _T_789 = {ldst_byteen_r[0],3'h0}; // @[Cat.scala 29:58] + wire [3:0] _T_790 = _T_756 ? ldst_byteen_r : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_791 = _T_758 ? _T_781 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_792 = _T_762 ? _T_785 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_793 = _T_766 ? _T_789 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_794 = _T_790 | _T_791; // @[Mux.scala 27:72] + wire [3:0] _T_795 = _T_794 | _T_792; // @[Mux.scala 27:72] + wire [3:0] ldst_byteen_lo_r = _T_795 | _T_793; // @[Mux.scala 27:72] + wire [31:0] _T_802 = {24'h0,io_store_data_r[31:24]}; // @[Cat.scala 29:58] + wire [31:0] _T_806 = {16'h0,io_store_data_r[31:16]}; // @[Cat.scala 29:58] + wire [31:0] _T_810 = {8'h0,io_store_data_r[31:8]}; // @[Cat.scala 29:58] + wire [31:0] _T_812 = _T_758 ? _T_802 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_813 = _T_762 ? _T_806 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_814 = _T_766 ? _T_810 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_816 = _T_812 | _T_813; // @[Mux.scala 27:72] + wire [31:0] store_data_hi_r = _T_816 | _T_814; // @[Mux.scala 27:72] + wire [31:0] _T_823 = {io_store_data_r[23:0],8'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_827 = {io_store_data_r[15:0],16'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_831 = {io_store_data_r[7:0],24'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_832 = _T_756 ? io_store_data_r : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_833 = _T_758 ? _T_823 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_834 = _T_762 ? _T_827 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_835 = _T_766 ? _T_831 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_836 = _T_832 | _T_833; // @[Mux.scala 27:72] + wire [31:0] _T_837 = _T_836 | _T_834; // @[Mux.scala 27:72] + wire [31:0] store_data_lo_r = _T_837 | _T_835; // @[Mux.scala 27:72] + wire ldst_samedw_r = io_lsu_addr_r[3] == io_end_addr_r[3]; // @[lsu_bus_buffer.scala 202:40] + wire _T_844 = ~io_lsu_addr_r[0]; // @[lsu_bus_buffer.scala 204:31] + wire _T_845 = io_lsu_pkt_r_bits_word & _T_756; // @[Mux.scala 27:72] + wire _T_846 = io_lsu_pkt_r_bits_half & _T_844; // @[Mux.scala 27:72] + wire _T_848 = _T_845 | _T_846; // @[Mux.scala 27:72] + wire is_aligned_r = _T_848 | io_lsu_pkt_r_bits_by; // @[Mux.scala 27:72] + wire _T_850 = io_lsu_pkt_r_bits_load | io_no_word_merge_r; // @[lsu_bus_buffer.scala 206:60] + wire _T_851 = io_lsu_busreq_r & _T_850; // @[lsu_bus_buffer.scala 206:34] + wire _T_852 = ~ibuf_valid; // @[lsu_bus_buffer.scala 206:84] + wire ibuf_byp = _T_851 & _T_852; // @[lsu_bus_buffer.scala 206:82] + wire _T_853 = io_lsu_busreq_r & io_lsu_commit_r; // @[lsu_bus_buffer.scala 207:36] + wire _T_854 = ~ibuf_byp; // @[lsu_bus_buffer.scala 207:56] + wire ibuf_wr_en = _T_853 & _T_854; // @[lsu_bus_buffer.scala 207:54] + wire _T_855 = ~ibuf_wr_en; // @[lsu_bus_buffer.scala 209:36] + reg [2:0] ibuf_timer; // @[lsu_bus_buffer.scala 252:55] + wire _T_864 = ibuf_timer == 3'h7; // @[lsu_bus_buffer.scala 215:62] + wire _T_865 = ibuf_wr_en | _T_864; // @[lsu_bus_buffer.scala 215:48] + wire _T_929 = _T_853 & io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 234:54] + wire _T_930 = _T_929 & ibuf_valid; // @[lsu_bus_buffer.scala 234:80] + wire _T_931 = _T_930 & ibuf_write; // @[lsu_bus_buffer.scala 234:93] + wire _T_934 = io_lsu_addr_r[31:2] == ibuf_addr[31:2]; // @[lsu_bus_buffer.scala 234:129] + wire _T_935 = _T_931 & _T_934; // @[lsu_bus_buffer.scala 234:106] + wire _T_936 = ~io_is_sideeffects_r; // @[lsu_bus_buffer.scala 234:152] + wire _T_937 = _T_935 & _T_936; // @[lsu_bus_buffer.scala 234:150] + wire _T_938 = ~io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_buffer.scala 234:175] + wire ibuf_merge_en = _T_937 & _T_938; // @[lsu_bus_buffer.scala 234:173] + wire ibuf_merge_in = ~io_ldst_dual_r; // @[lsu_bus_buffer.scala 235:20] + wire _T_866 = ibuf_merge_en & ibuf_merge_in; // @[lsu_bus_buffer.scala 215:98] + wire _T_867 = ~_T_866; // @[lsu_bus_buffer.scala 215:82] + wire _T_868 = _T_865 & _T_867; // @[lsu_bus_buffer.scala 215:80] + wire _T_869 = _T_868 | ibuf_byp; // @[lsu_bus_buffer.scala 216:5] + wire _T_857 = ~io_lsu_busreq_r; // @[lsu_bus_buffer.scala 210:44] + wire _T_858 = io_lsu_busreq_m & _T_857; // @[lsu_bus_buffer.scala 210:42] + wire _T_859 = _T_858 & ibuf_valid; // @[lsu_bus_buffer.scala 210:61] + wire _T_862 = ibuf_addr[31:2] != io_lsu_addr_m[31:2]; // @[lsu_bus_buffer.scala 210:120] + wire _T_863 = io_lsu_pkt_m_bits_load | _T_862; // @[lsu_bus_buffer.scala 210:100] + wire ibuf_force_drain = _T_859 & _T_863; // @[lsu_bus_buffer.scala 210:74] + wire _T_870 = _T_869 | ibuf_force_drain; // @[lsu_bus_buffer.scala 216:16] + reg ibuf_sideeffect; // @[Reg.scala 27:20] + wire _T_871 = _T_870 | ibuf_sideeffect; // @[lsu_bus_buffer.scala 216:35] + wire _T_872 = ~ibuf_write; // @[lsu_bus_buffer.scala 216:55] + wire _T_873 = _T_871 | _T_872; // @[lsu_bus_buffer.scala 216:53] + wire _T_874 = _T_873 | io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_buffer.scala 216:67] + wire ibuf_drain_vld = ibuf_valid & _T_874; // @[lsu_bus_buffer.scala 215:32] + wire _T_856 = ibuf_drain_vld & _T_855; // @[lsu_bus_buffer.scala 209:34] + wire ibuf_rst = _T_856 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 209:49] + reg [1:0] WrPtr1_r; // @[lsu_bus_buffer.scala 615:49] + reg [1:0] WrPtr0_r; // @[lsu_bus_buffer.scala 614:49] + reg [1:0] ibuf_tag; // @[Reg.scala 27:20] + wire [1:0] ibuf_sz_in = {io_lsu_pkt_r_bits_word,io_lsu_pkt_r_bits_half}; // @[Cat.scala 29:58] + wire [3:0] _T_881 = ibuf_byteen | ldst_byteen_lo_r; // @[lsu_bus_buffer.scala 225:77] + wire [7:0] _T_889 = ldst_byteen_lo_r[0] ? store_data_lo_r[7:0] : ibuf_data[7:0]; // @[lsu_bus_buffer.scala 230:8] + wire [7:0] _T_892 = io_ldst_dual_r ? store_data_hi_r[7:0] : store_data_lo_r[7:0]; // @[lsu_bus_buffer.scala 231:8] + wire [7:0] _T_893 = _T_866 ? _T_889 : _T_892; // @[lsu_bus_buffer.scala 229:46] + wire [7:0] _T_898 = ldst_byteen_lo_r[1] ? store_data_lo_r[15:8] : ibuf_data[15:8]; // @[lsu_bus_buffer.scala 230:8] + wire [7:0] _T_901 = io_ldst_dual_r ? store_data_hi_r[15:8] : store_data_lo_r[15:8]; // @[lsu_bus_buffer.scala 231:8] + wire [7:0] _T_902 = _T_866 ? _T_898 : _T_901; // @[lsu_bus_buffer.scala 229:46] + wire [7:0] _T_907 = ldst_byteen_lo_r[2] ? store_data_lo_r[23:16] : ibuf_data[23:16]; // @[lsu_bus_buffer.scala 230:8] + wire [7:0] _T_910 = io_ldst_dual_r ? store_data_hi_r[23:16] : store_data_lo_r[23:16]; // @[lsu_bus_buffer.scala 231:8] + wire [7:0] _T_911 = _T_866 ? _T_907 : _T_910; // @[lsu_bus_buffer.scala 229:46] + wire [7:0] _T_916 = ldst_byteen_lo_r[3] ? store_data_lo_r[31:24] : ibuf_data[31:24]; // @[lsu_bus_buffer.scala 230:8] + wire [7:0] _T_919 = io_ldst_dual_r ? store_data_hi_r[31:24] : store_data_lo_r[31:24]; // @[lsu_bus_buffer.scala 231:8] + wire [7:0] _T_920 = _T_866 ? _T_916 : _T_919; // @[lsu_bus_buffer.scala 229:46] + wire [23:0] _T_922 = {_T_920,_T_911,_T_902}; // @[Cat.scala 29:58] + wire _T_923 = ibuf_timer < 3'h7; // @[lsu_bus_buffer.scala 232:59] + wire [2:0] _T_926 = ibuf_timer + 3'h1; // @[lsu_bus_buffer.scala 232:93] + wire _T_941 = ~ibuf_merge_in; // @[lsu_bus_buffer.scala 236:65] + wire _T_942 = ibuf_merge_en & _T_941; // @[lsu_bus_buffer.scala 236:63] + wire _T_945 = ibuf_byteen[0] | ldst_byteen_lo_r[0]; // @[lsu_bus_buffer.scala 236:96] + wire _T_947 = _T_942 ? _T_945 : ibuf_byteen[0]; // @[lsu_bus_buffer.scala 236:48] + wire _T_952 = ibuf_byteen[1] | ldst_byteen_lo_r[1]; // @[lsu_bus_buffer.scala 236:96] + wire _T_954 = _T_942 ? _T_952 : ibuf_byteen[1]; // @[lsu_bus_buffer.scala 236:48] + wire _T_959 = ibuf_byteen[2] | ldst_byteen_lo_r[2]; // @[lsu_bus_buffer.scala 236:96] + wire _T_961 = _T_942 ? _T_959 : ibuf_byteen[2]; // @[lsu_bus_buffer.scala 236:48] + wire _T_966 = ibuf_byteen[3] | ldst_byteen_lo_r[3]; // @[lsu_bus_buffer.scala 236:96] + wire _T_968 = _T_942 ? _T_966 : ibuf_byteen[3]; // @[lsu_bus_buffer.scala 236:48] + wire [3:0] ibuf_byteen_out = {_T_968,_T_961,_T_954,_T_947}; // @[Cat.scala 29:58] + wire [7:0] _T_978 = _T_942 ? _T_889 : ibuf_data[7:0]; // @[lsu_bus_buffer.scala 237:45] + wire [7:0] _T_986 = _T_942 ? _T_898 : ibuf_data[15:8]; // @[lsu_bus_buffer.scala 237:45] + wire [7:0] _T_994 = _T_942 ? _T_907 : ibuf_data[23:16]; // @[lsu_bus_buffer.scala 237:45] + wire [7:0] _T_1002 = _T_942 ? _T_916 : ibuf_data[31:24]; // @[lsu_bus_buffer.scala 237:45] + wire [31:0] ibuf_data_out = {_T_1002,_T_994,_T_986,_T_978}; // @[Cat.scala 29:58] + wire _T_1005 = ibuf_wr_en | ibuf_valid; // @[lsu_bus_buffer.scala 239:58] + wire _T_1006 = ~ibuf_rst; // @[lsu_bus_buffer.scala 239:93] + reg [1:0] ibuf_dualtag; // @[Reg.scala 27:20] + reg ibuf_dual; // @[Reg.scala 27:20] + reg ibuf_samedw; // @[Reg.scala 27:20] + reg ibuf_nomerge; // @[Reg.scala 27:20] + reg ibuf_unsign; // @[Reg.scala 27:20] + reg [1:0] ibuf_sz; // @[Reg.scala 27:20] + wire _T_4446 = buf_write[3] & _T_2621; // @[lsu_bus_buffer.scala 521:64] + wire _T_4447 = ~buf_cmd_state_bus_en_3; // @[lsu_bus_buffer.scala 521:91] + wire _T_4448 = _T_4446 & _T_4447; // @[lsu_bus_buffer.scala 521:89] + wire _T_4441 = buf_write[2] & _T_2616; // @[lsu_bus_buffer.scala 521:64] + wire _T_4442 = ~buf_cmd_state_bus_en_2; // @[lsu_bus_buffer.scala 521:91] + wire _T_4443 = _T_4441 & _T_4442; // @[lsu_bus_buffer.scala 521:89] + wire [1:0] _T_4449 = _T_4448 + _T_4443; // @[lsu_bus_buffer.scala 521:142] + wire _T_4436 = buf_write[1] & _T_2611; // @[lsu_bus_buffer.scala 521:64] + wire _T_4437 = ~buf_cmd_state_bus_en_1; // @[lsu_bus_buffer.scala 521:91] + wire _T_4438 = _T_4436 & _T_4437; // @[lsu_bus_buffer.scala 521:89] + wire [1:0] _GEN_362 = {{1'd0}, _T_4438}; // @[lsu_bus_buffer.scala 521:142] + wire [2:0] _T_4450 = _T_4449 + _GEN_362; // @[lsu_bus_buffer.scala 521:142] + wire _T_4431 = buf_write[0] & _T_2606; // @[lsu_bus_buffer.scala 521:64] + wire _T_4432 = ~buf_cmd_state_bus_en_0; // @[lsu_bus_buffer.scala 521:91] + wire _T_4433 = _T_4431 & _T_4432; // @[lsu_bus_buffer.scala 521:89] + wire [2:0] _GEN_363 = {{2'd0}, _T_4433}; // @[lsu_bus_buffer.scala 521:142] + wire [3:0] buf_numvld_wrcmd_any = _T_4450 + _GEN_363; // @[lsu_bus_buffer.scala 521:142] + wire _T_1016 = buf_numvld_wrcmd_any == 4'h1; // @[lsu_bus_buffer.scala 262:43] + wire _T_4463 = _T_2621 & _T_4447; // @[lsu_bus_buffer.scala 522:73] + wire _T_4460 = _T_2616 & _T_4442; // @[lsu_bus_buffer.scala 522:73] + wire [1:0] _T_4464 = _T_4463 + _T_4460; // @[lsu_bus_buffer.scala 522:126] + wire _T_4457 = _T_2611 & _T_4437; // @[lsu_bus_buffer.scala 522:73] + wire [1:0] _GEN_364 = {{1'd0}, _T_4457}; // @[lsu_bus_buffer.scala 522:126] + wire [2:0] _T_4465 = _T_4464 + _GEN_364; // @[lsu_bus_buffer.scala 522:126] + wire _T_4454 = _T_2606 & _T_4432; // @[lsu_bus_buffer.scala 522:73] + wire [2:0] _GEN_365 = {{2'd0}, _T_4454}; // @[lsu_bus_buffer.scala 522:126] + wire [3:0] buf_numvld_cmd_any = _T_4465 + _GEN_365; // @[lsu_bus_buffer.scala 522:126] + wire _T_1017 = buf_numvld_cmd_any == 4'h1; // @[lsu_bus_buffer.scala 262:72] + wire _T_1018 = _T_1016 & _T_1017; // @[lsu_bus_buffer.scala 262:51] + reg [2:0] obuf_wr_timer; // @[lsu_bus_buffer.scala 360:54] + wire _T_1019 = obuf_wr_timer != 3'h7; // @[lsu_bus_buffer.scala 262:97] + wire _T_1020 = _T_1018 & _T_1019; // @[lsu_bus_buffer.scala 262:80] + wire _T_1022 = _T_1020 & _T_938; // @[lsu_bus_buffer.scala 262:114] + wire _T_1979 = |buf_age_3; // @[lsu_bus_buffer.scala 377:58] + wire _T_1980 = ~_T_1979; // @[lsu_bus_buffer.scala 377:45] + wire _T_1982 = _T_1980 & _T_2621; // @[lsu_bus_buffer.scala 377:63] + wire _T_1984 = _T_1982 & _T_4447; // @[lsu_bus_buffer.scala 377:88] + wire _T_1973 = |buf_age_2; // @[lsu_bus_buffer.scala 377:58] + wire _T_1974 = ~_T_1973; // @[lsu_bus_buffer.scala 377:45] + wire _T_1976 = _T_1974 & _T_2616; // @[lsu_bus_buffer.scala 377:63] + wire _T_1978 = _T_1976 & _T_4442; // @[lsu_bus_buffer.scala 377:88] + wire _T_1967 = |buf_age_1; // @[lsu_bus_buffer.scala 377:58] + wire _T_1968 = ~_T_1967; // @[lsu_bus_buffer.scala 377:45] + wire _T_1970 = _T_1968 & _T_2611; // @[lsu_bus_buffer.scala 377:63] + wire _T_1972 = _T_1970 & _T_4437; // @[lsu_bus_buffer.scala 377:88] + wire _T_1961 = |buf_age_0; // @[lsu_bus_buffer.scala 377:58] + wire _T_1962 = ~_T_1961; // @[lsu_bus_buffer.scala 377:45] + wire _T_1964 = _T_1962 & _T_2606; // @[lsu_bus_buffer.scala 377:63] + wire _T_1966 = _T_1964 & _T_4432; // @[lsu_bus_buffer.scala 377:88] + wire [3:0] CmdPtr0Dec = {_T_1984,_T_1978,_T_1972,_T_1966}; // @[Cat.scala 29:58] + wire [7:0] _T_2054 = {4'h0,_T_1984,_T_1978,_T_1972,_T_1966}; // @[Cat.scala 29:58] + wire _T_2057 = _T_2054[4] | _T_2054[5]; // @[lsu_bus_buffer.scala 385:42] + wire _T_2059 = _T_2057 | _T_2054[6]; // @[lsu_bus_buffer.scala 385:48] + wire _T_2061 = _T_2059 | _T_2054[7]; // @[lsu_bus_buffer.scala 385:54] + wire _T_2064 = _T_2054[2] | _T_2054[3]; // @[lsu_bus_buffer.scala 385:67] + wire _T_2066 = _T_2064 | _T_2054[6]; // @[lsu_bus_buffer.scala 385:73] + wire _T_2068 = _T_2066 | _T_2054[7]; // @[lsu_bus_buffer.scala 385:79] + wire _T_2071 = _T_2054[1] | _T_2054[3]; // @[lsu_bus_buffer.scala 385:92] + wire _T_2073 = _T_2071 | _T_2054[5]; // @[lsu_bus_buffer.scala 385:98] + wire _T_2075 = _T_2073 | _T_2054[7]; // @[lsu_bus_buffer.scala 385:104] + wire [2:0] _T_2077 = {_T_2061,_T_2068,_T_2075}; // @[Cat.scala 29:58] + wire [1:0] CmdPtr0 = _T_2077[1:0]; // @[lsu_bus_buffer.scala 390:11] + wire _T_1023 = CmdPtr0 == 2'h0; // @[lsu_bus_buffer.scala 263:114] + wire _T_1024 = CmdPtr0 == 2'h1; // @[lsu_bus_buffer.scala 263:114] + wire _T_1025 = CmdPtr0 == 2'h2; // @[lsu_bus_buffer.scala 263:114] + wire _T_1026 = CmdPtr0 == 2'h3; // @[lsu_bus_buffer.scala 263:114] + reg buf_nomerge_0; // @[Reg.scala 27:20] + wire _T_1027 = _T_1023 & buf_nomerge_0; // @[Mux.scala 27:72] + reg buf_nomerge_1; // @[Reg.scala 27:20] + wire _T_1028 = _T_1024 & buf_nomerge_1; // @[Mux.scala 27:72] + reg buf_nomerge_2; // @[Reg.scala 27:20] + wire _T_1029 = _T_1025 & buf_nomerge_2; // @[Mux.scala 27:72] + reg buf_nomerge_3; // @[Reg.scala 27:20] + wire _T_1030 = _T_1026 & buf_nomerge_3; // @[Mux.scala 27:72] + wire _T_1031 = _T_1027 | _T_1028; // @[Mux.scala 27:72] + wire _T_1032 = _T_1031 | _T_1029; // @[Mux.scala 27:72] + wire _T_1033 = _T_1032 | _T_1030; // @[Mux.scala 27:72] + wire _T_1035 = ~_T_1033; // @[lsu_bus_buffer.scala 263:31] + wire _T_1036 = _T_1022 & _T_1035; // @[lsu_bus_buffer.scala 263:29] + reg _T_4330; // @[Reg.scala 27:20] + reg _T_4327; // @[Reg.scala 27:20] + reg _T_4324; // @[Reg.scala 27:20] + reg _T_4321; // @[Reg.scala 27:20] + wire [3:0] buf_sideeffect = {_T_4330,_T_4327,_T_4324,_T_4321}; // @[Cat.scala 29:58] + wire _T_1045 = _T_1023 & buf_sideeffect[0]; // @[Mux.scala 27:72] + wire _T_1046 = _T_1024 & buf_sideeffect[1]; // @[Mux.scala 27:72] + wire _T_1047 = _T_1025 & buf_sideeffect[2]; // @[Mux.scala 27:72] + wire _T_1048 = _T_1026 & buf_sideeffect[3]; // @[Mux.scala 27:72] + wire _T_1049 = _T_1045 | _T_1046; // @[Mux.scala 27:72] + wire _T_1050 = _T_1049 | _T_1047; // @[Mux.scala 27:72] + wire _T_1051 = _T_1050 | _T_1048; // @[Mux.scala 27:72] + wire _T_1053 = ~_T_1051; // @[lsu_bus_buffer.scala 264:5] + wire _T_1054 = _T_1036 & _T_1053; // @[lsu_bus_buffer.scala 263:140] + wire _T_1065 = _T_858 & _T_852; // @[lsu_bus_buffer.scala 266:58] + wire _T_1067 = _T_1065 & _T_1017; // @[lsu_bus_buffer.scala 266:72] + wire [29:0] _T_1077 = _T_1023 ? buf_addr_0[31:2] : 30'h0; // @[Mux.scala 27:72] + wire [29:0] _T_1078 = _T_1024 ? buf_addr_1[31:2] : 30'h0; // @[Mux.scala 27:72] + wire [29:0] _T_1081 = _T_1077 | _T_1078; // @[Mux.scala 27:72] + wire [29:0] _T_1079 = _T_1025 ? buf_addr_2[31:2] : 30'h0; // @[Mux.scala 27:72] + wire [29:0] _T_1082 = _T_1081 | _T_1079; // @[Mux.scala 27:72] + wire [29:0] _T_1080 = _T_1026 ? buf_addr_3[31:2] : 30'h0; // @[Mux.scala 27:72] + wire [29:0] _T_1083 = _T_1082 | _T_1080; // @[Mux.scala 27:72] + wire _T_1085 = io_lsu_addr_m[31:2] != _T_1083; // @[lsu_bus_buffer.scala 266:123] + wire obuf_force_wr_en = _T_1067 & _T_1085; // @[lsu_bus_buffer.scala 266:101] + wire _T_1055 = ~obuf_force_wr_en; // @[lsu_bus_buffer.scala 264:119] + wire obuf_wr_wait = _T_1054 & _T_1055; // @[lsu_bus_buffer.scala 264:117] + wire _T_1056 = |buf_numvld_cmd_any; // @[lsu_bus_buffer.scala 265:75] + wire _T_1057 = obuf_wr_timer < 3'h7; // @[lsu_bus_buffer.scala 265:95] + wire _T_1058 = _T_1056 & _T_1057; // @[lsu_bus_buffer.scala 265:79] + wire [2:0] _T_1060 = obuf_wr_timer + 3'h1; // @[lsu_bus_buffer.scala 265:123] + wire _T_4482 = buf_state_3 == 3'h1; // @[lsu_bus_buffer.scala 523:63] + wire _T_4486 = _T_4482 | _T_4463; // @[lsu_bus_buffer.scala 523:74] + wire _T_4477 = buf_state_2 == 3'h1; // @[lsu_bus_buffer.scala 523:63] + wire _T_4481 = _T_4477 | _T_4460; // @[lsu_bus_buffer.scala 523:74] + wire [1:0] _T_4487 = _T_4486 + _T_4481; // @[lsu_bus_buffer.scala 523:154] + wire _T_4472 = buf_state_1 == 3'h1; // @[lsu_bus_buffer.scala 523:63] + wire _T_4476 = _T_4472 | _T_4457; // @[lsu_bus_buffer.scala 523:74] + wire [1:0] _GEN_366 = {{1'd0}, _T_4476}; // @[lsu_bus_buffer.scala 523:154] + wire [2:0] _T_4488 = _T_4487 + _GEN_366; // @[lsu_bus_buffer.scala 523:154] + wire _T_4467 = buf_state_0 == 3'h1; // @[lsu_bus_buffer.scala 523:63] + wire _T_4471 = _T_4467 | _T_4454; // @[lsu_bus_buffer.scala 523:74] + wire [2:0] _GEN_367 = {{2'd0}, _T_4471}; // @[lsu_bus_buffer.scala 523:154] + wire [3:0] buf_numvld_pend_any = _T_4488 + _GEN_367; // @[lsu_bus_buffer.scala 523:154] + wire _T_1087 = buf_numvld_pend_any == 4'h0; // @[lsu_bus_buffer.scala 268:53] + wire _T_1088 = ibuf_byp & _T_1087; // @[lsu_bus_buffer.scala 268:31] + wire _T_1089 = ~io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 268:64] + wire _T_1090 = _T_1089 | io_no_dword_merge_r; // @[lsu_bus_buffer.scala 268:89] + wire ibuf_buf_byp = _T_1088 & _T_1090; // @[lsu_bus_buffer.scala 268:61] + wire _T_1091 = ibuf_buf_byp & io_lsu_commit_r; // @[lsu_bus_buffer.scala 283:32] + wire _T_4778 = buf_state_0 == 3'h3; // @[lsu_bus_buffer.scala 551:62] + wire _T_4780 = _T_4778 & buf_sideeffect[0]; // @[lsu_bus_buffer.scala 551:73] + wire _T_4781 = _T_4780 & io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_buffer.scala 551:93] + wire _T_4782 = buf_state_1 == 3'h3; // @[lsu_bus_buffer.scala 551:62] + wire _T_4784 = _T_4782 & buf_sideeffect[1]; // @[lsu_bus_buffer.scala 551:73] + wire _T_4785 = _T_4784 & io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_buffer.scala 551:93] + wire _T_4794 = _T_4781 | _T_4785; // @[lsu_bus_buffer.scala 551:153] + wire _T_4786 = buf_state_2 == 3'h3; // @[lsu_bus_buffer.scala 551:62] + wire _T_4788 = _T_4786 & buf_sideeffect[2]; // @[lsu_bus_buffer.scala 551:73] + wire _T_4789 = _T_4788 & io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_buffer.scala 551:93] + wire _T_4795 = _T_4794 | _T_4789; // @[lsu_bus_buffer.scala 551:153] + wire _T_4790 = buf_state_3 == 3'h3; // @[lsu_bus_buffer.scala 551:62] + wire _T_4792 = _T_4790 & buf_sideeffect[3]; // @[lsu_bus_buffer.scala 551:73] + wire _T_4793 = _T_4792 & io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_buffer.scala 551:93] + wire _T_4796 = _T_4795 | _T_4793; // @[lsu_bus_buffer.scala 551:153] + reg obuf_sideeffect; // @[Reg.scala 27:20] + wire _T_4797 = obuf_valid & obuf_sideeffect; // @[lsu_bus_buffer.scala 551:171] + wire _T_4798 = _T_4797 & io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_buffer.scala 551:189] + wire bus_sideeffect_pend = _T_4796 | _T_4798; // @[lsu_bus_buffer.scala 551:157] + wire _T_1092 = io_is_sideeffects_r & bus_sideeffect_pend; // @[lsu_bus_buffer.scala 283:74] + wire _T_1093 = ~_T_1092; // @[lsu_bus_buffer.scala 283:52] + wire _T_1094 = _T_1091 & _T_1093; // @[lsu_bus_buffer.scala 283:50] + wire [2:0] _T_1099 = _T_1023 ? buf_state_0 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1100 = _T_1024 ? buf_state_1 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1103 = _T_1099 | _T_1100; // @[Mux.scala 27:72] + wire [2:0] _T_1101 = _T_1025 ? buf_state_2 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1104 = _T_1103 | _T_1101; // @[Mux.scala 27:72] + wire [2:0] _T_1102 = _T_1026 ? buf_state_3 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1105 = _T_1104 | _T_1102; // @[Mux.scala 27:72] + wire _T_1107 = _T_1105 == 3'h2; // @[lsu_bus_buffer.scala 284:36] + wire found_cmdptr0 = |CmdPtr0Dec; // @[lsu_bus_buffer.scala 382:31] + wire _T_1108 = _T_1107 & found_cmdptr0; // @[lsu_bus_buffer.scala 284:47] + wire [3:0] _T_1111 = {buf_cmd_state_bus_en_3,buf_cmd_state_bus_en_2,buf_cmd_state_bus_en_1,buf_cmd_state_bus_en_0}; // @[Cat.scala 29:58] + wire _T_1120 = _T_1023 & _T_1111[0]; // @[Mux.scala 27:72] + wire _T_1121 = _T_1024 & _T_1111[1]; // @[Mux.scala 27:72] + wire _T_1124 = _T_1120 | _T_1121; // @[Mux.scala 27:72] + wire _T_1122 = _T_1025 & _T_1111[2]; // @[Mux.scala 27:72] + wire _T_1125 = _T_1124 | _T_1122; // @[Mux.scala 27:72] + wire _T_1123 = _T_1026 & _T_1111[3]; // @[Mux.scala 27:72] + wire _T_1126 = _T_1125 | _T_1123; // @[Mux.scala 27:72] + wire _T_1128 = ~_T_1126; // @[lsu_bus_buffer.scala 285:23] + wire _T_1129 = _T_1108 & _T_1128; // @[lsu_bus_buffer.scala 285:21] + wire _T_1146 = _T_1051 & bus_sideeffect_pend; // @[lsu_bus_buffer.scala 285:141] + wire _T_1147 = ~_T_1146; // @[lsu_bus_buffer.scala 285:105] + wire _T_1148 = _T_1129 & _T_1147; // @[lsu_bus_buffer.scala 285:103] + reg buf_dual_3; // @[Reg.scala 27:20] + reg buf_dual_2; // @[Reg.scala 27:20] + reg buf_dual_1; // @[Reg.scala 27:20] + reg buf_dual_0; // @[Reg.scala 27:20] + wire [3:0] _T_1151 = {buf_dual_3,buf_dual_2,buf_dual_1,buf_dual_0}; // @[Cat.scala 29:58] + wire _T_1160 = _T_1023 & _T_1151[0]; // @[Mux.scala 27:72] + wire _T_1161 = _T_1024 & _T_1151[1]; // @[Mux.scala 27:72] + wire _T_1164 = _T_1160 | _T_1161; // @[Mux.scala 27:72] + wire _T_1162 = _T_1025 & _T_1151[2]; // @[Mux.scala 27:72] + wire _T_1165 = _T_1164 | _T_1162; // @[Mux.scala 27:72] + wire _T_1163 = _T_1026 & _T_1151[3]; // @[Mux.scala 27:72] + wire _T_1166 = _T_1165 | _T_1163; // @[Mux.scala 27:72] + reg buf_samedw_3; // @[Reg.scala 27:20] + reg buf_samedw_2; // @[Reg.scala 27:20] + reg buf_samedw_1; // @[Reg.scala 27:20] + reg buf_samedw_0; // @[Reg.scala 27:20] + wire [3:0] _T_1170 = {buf_samedw_3,buf_samedw_2,buf_samedw_1,buf_samedw_0}; // @[Cat.scala 29:58] + wire _T_1179 = _T_1023 & _T_1170[0]; // @[Mux.scala 27:72] + wire _T_1180 = _T_1024 & _T_1170[1]; // @[Mux.scala 27:72] + wire _T_1183 = _T_1179 | _T_1180; // @[Mux.scala 27:72] + wire _T_1181 = _T_1025 & _T_1170[2]; // @[Mux.scala 27:72] + wire _T_1184 = _T_1183 | _T_1181; // @[Mux.scala 27:72] + wire _T_1182 = _T_1026 & _T_1170[3]; // @[Mux.scala 27:72] + wire _T_1185 = _T_1184 | _T_1182; // @[Mux.scala 27:72] + wire _T_1187 = _T_1166 & _T_1185; // @[lsu_bus_buffer.scala 286:77] + wire _T_1196 = _T_1023 & buf_write[0]; // @[Mux.scala 27:72] + wire _T_1197 = _T_1024 & buf_write[1]; // @[Mux.scala 27:72] + wire _T_1200 = _T_1196 | _T_1197; // @[Mux.scala 27:72] + wire _T_1198 = _T_1025 & buf_write[2]; // @[Mux.scala 27:72] + wire _T_1201 = _T_1200 | _T_1198; // @[Mux.scala 27:72] + wire _T_1199 = _T_1026 & buf_write[3]; // @[Mux.scala 27:72] + wire _T_1202 = _T_1201 | _T_1199; // @[Mux.scala 27:72] + wire _T_1204 = ~_T_1202; // @[lsu_bus_buffer.scala 286:150] + wire _T_1205 = _T_1187 & _T_1204; // @[lsu_bus_buffer.scala 286:148] + wire _T_1206 = ~_T_1205; // @[lsu_bus_buffer.scala 286:8] + wire [3:0] _T_2020 = ~CmdPtr0Dec; // @[lsu_bus_buffer.scala 378:62] + wire [3:0] _T_2021 = buf_age_3 & _T_2020; // @[lsu_bus_buffer.scala 378:59] + wire _T_2022 = |_T_2021; // @[lsu_bus_buffer.scala 378:76] + wire _T_2023 = ~_T_2022; // @[lsu_bus_buffer.scala 378:45] + wire _T_2025 = ~CmdPtr0Dec[3]; // @[lsu_bus_buffer.scala 378:83] + wire _T_2026 = _T_2023 & _T_2025; // @[lsu_bus_buffer.scala 378:81] + wire _T_2028 = _T_2026 & _T_2621; // @[lsu_bus_buffer.scala 378:98] + wire _T_2030 = _T_2028 & _T_4447; // @[lsu_bus_buffer.scala 378:123] + wire [3:0] _T_2010 = buf_age_2 & _T_2020; // @[lsu_bus_buffer.scala 378:59] + wire _T_2011 = |_T_2010; // @[lsu_bus_buffer.scala 378:76] + wire _T_2012 = ~_T_2011; // @[lsu_bus_buffer.scala 378:45] + wire _T_2014 = ~CmdPtr0Dec[2]; // @[lsu_bus_buffer.scala 378:83] + wire _T_2015 = _T_2012 & _T_2014; // @[lsu_bus_buffer.scala 378:81] + wire _T_2017 = _T_2015 & _T_2616; // @[lsu_bus_buffer.scala 378:98] + wire _T_2019 = _T_2017 & _T_4442; // @[lsu_bus_buffer.scala 378:123] + wire [3:0] _T_1999 = buf_age_1 & _T_2020; // @[lsu_bus_buffer.scala 378:59] + wire _T_2000 = |_T_1999; // @[lsu_bus_buffer.scala 378:76] + wire _T_2001 = ~_T_2000; // @[lsu_bus_buffer.scala 378:45] + wire _T_2003 = ~CmdPtr0Dec[1]; // @[lsu_bus_buffer.scala 378:83] + wire _T_2004 = _T_2001 & _T_2003; // @[lsu_bus_buffer.scala 378:81] + wire _T_2006 = _T_2004 & _T_2611; // @[lsu_bus_buffer.scala 378:98] + wire _T_2008 = _T_2006 & _T_4437; // @[lsu_bus_buffer.scala 378:123] + wire [3:0] _T_1988 = buf_age_0 & _T_2020; // @[lsu_bus_buffer.scala 378:59] + wire _T_1989 = |_T_1988; // @[lsu_bus_buffer.scala 378:76] + wire _T_1990 = ~_T_1989; // @[lsu_bus_buffer.scala 378:45] + wire _T_1992 = ~CmdPtr0Dec[0]; // @[lsu_bus_buffer.scala 378:83] + wire _T_1993 = _T_1990 & _T_1992; // @[lsu_bus_buffer.scala 378:81] + wire _T_1995 = _T_1993 & _T_2606; // @[lsu_bus_buffer.scala 378:98] + wire _T_1997 = _T_1995 & _T_4432; // @[lsu_bus_buffer.scala 378:123] + wire [3:0] CmdPtr1Dec = {_T_2030,_T_2019,_T_2008,_T_1997}; // @[Cat.scala 29:58] + wire found_cmdptr1 = |CmdPtr1Dec; // @[lsu_bus_buffer.scala 383:31] + wire _T_1207 = _T_1206 | found_cmdptr1; // @[lsu_bus_buffer.scala 286:181] + wire [3:0] _T_1210 = {buf_nomerge_3,buf_nomerge_2,buf_nomerge_1,buf_nomerge_0}; // @[Cat.scala 29:58] + wire _T_1219 = _T_1023 & _T_1210[0]; // @[Mux.scala 27:72] + wire _T_1220 = _T_1024 & _T_1210[1]; // @[Mux.scala 27:72] + wire _T_1223 = _T_1219 | _T_1220; // @[Mux.scala 27:72] + wire _T_1221 = _T_1025 & _T_1210[2]; // @[Mux.scala 27:72] + wire _T_1224 = _T_1223 | _T_1221; // @[Mux.scala 27:72] + wire _T_1222 = _T_1026 & _T_1210[3]; // @[Mux.scala 27:72] + wire _T_1225 = _T_1224 | _T_1222; // @[Mux.scala 27:72] + wire _T_1227 = _T_1207 | _T_1225; // @[lsu_bus_buffer.scala 286:197] + wire _T_1228 = _T_1227 | obuf_force_wr_en; // @[lsu_bus_buffer.scala 286:269] + wire _T_1229 = _T_1148 & _T_1228; // @[lsu_bus_buffer.scala 285:164] + wire _T_1230 = _T_1094 | _T_1229; // @[lsu_bus_buffer.scala 283:98] + reg obuf_write; // @[Reg.scala 27:20] + reg obuf_cmd_done; // @[lsu_bus_buffer.scala 347:54] + reg obuf_data_done; // @[lsu_bus_buffer.scala 348:55] + wire _T_4856 = obuf_cmd_done | obuf_data_done; // @[lsu_bus_buffer.scala 555:54] + wire _T_4857 = obuf_cmd_done ? io_lsu_axi_w_ready : io_lsu_axi_aw_ready; // @[lsu_bus_buffer.scala 555:75] + wire _T_4858 = io_lsu_axi_aw_ready & io_lsu_axi_w_ready; // @[lsu_bus_buffer.scala 555:153] + wire _T_4859 = _T_4856 ? _T_4857 : _T_4858; // @[lsu_bus_buffer.scala 555:39] + wire bus_cmd_ready = obuf_write ? _T_4859 : io_lsu_axi_ar_ready; // @[lsu_bus_buffer.scala 555:23] + wire _T_1231 = ~obuf_valid; // @[lsu_bus_buffer.scala 287:48] + wire _T_1232 = bus_cmd_ready | _T_1231; // @[lsu_bus_buffer.scala 287:46] + reg obuf_nosend; // @[Reg.scala 27:20] + wire _T_1233 = _T_1232 | obuf_nosend; // @[lsu_bus_buffer.scala 287:60] + wire _T_1234 = _T_1230 & _T_1233; // @[lsu_bus_buffer.scala 287:29] + wire _T_1235 = ~obuf_wr_wait; // @[lsu_bus_buffer.scala 287:77] + wire _T_1236 = _T_1234 & _T_1235; // @[lsu_bus_buffer.scala 287:75] + reg [31:0] obuf_addr; // @[lib.scala 374:16] + wire obuf_wr_en = _T_1236 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 287:142] + wire _T_1242 = obuf_valid & obuf_nosend; // @[lsu_bus_buffer.scala 289:47] + wire bus_wcmd_sent = io_lsu_axi_aw_valid & io_lsu_axi_aw_ready; // @[lsu_bus_buffer.scala 556:40] + wire _T_4863 = obuf_cmd_done | bus_wcmd_sent; // @[lsu_bus_buffer.scala 558:35] + wire bus_wdata_sent = io_lsu_axi_w_valid & io_lsu_axi_w_ready; // @[lsu_bus_buffer.scala 557:40] + wire _T_4864 = obuf_data_done | bus_wdata_sent; // @[lsu_bus_buffer.scala 558:70] + wire _T_4865 = _T_4863 & _T_4864; // @[lsu_bus_buffer.scala 558:52] + wire _T_4866 = io_lsu_axi_ar_valid & io_lsu_axi_ar_ready; // @[lsu_bus_buffer.scala 558:112] + wire bus_cmd_sent = _T_4865 | _T_4866; // @[lsu_bus_buffer.scala 558:89] + wire _T_1243 = bus_cmd_sent | _T_1242; // @[lsu_bus_buffer.scala 289:33] + wire _T_1244 = ~obuf_wr_en; // @[lsu_bus_buffer.scala 289:65] + wire _T_1245 = _T_1243 & _T_1244; // @[lsu_bus_buffer.scala 289:63] + wire _T_1246 = _T_1245 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 289:77] + wire obuf_rst = _T_1246 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 289:98] + wire obuf_write_in = ibuf_buf_byp ? io_lsu_pkt_r_bits_store : _T_1202; // @[lsu_bus_buffer.scala 290:26] + wire [31:0] _T_1283 = _T_1023 ? buf_addr_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1284 = _T_1024 ? buf_addr_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1285 = _T_1025 ? buf_addr_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1286 = _T_1026 ? buf_addr_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1287 = _T_1283 | _T_1284; // @[Mux.scala 27:72] + wire [31:0] _T_1288 = _T_1287 | _T_1285; // @[Mux.scala 27:72] + wire [31:0] _T_1289 = _T_1288 | _T_1286; // @[Mux.scala 27:72] + wire [31:0] obuf_addr_in = ibuf_buf_byp ? io_lsu_addr_r : _T_1289; // @[lsu_bus_buffer.scala 292:25] + reg [1:0] buf_sz_0; // @[Reg.scala 27:20] + wire [1:0] _T_1296 = _T_1023 ? buf_sz_0 : 2'h0; // @[Mux.scala 27:72] + reg [1:0] buf_sz_1; // @[Reg.scala 27:20] + wire [1:0] _T_1297 = _T_1024 ? buf_sz_1 : 2'h0; // @[Mux.scala 27:72] + reg [1:0] buf_sz_2; // @[Reg.scala 27:20] + wire [1:0] _T_1298 = _T_1025 ? buf_sz_2 : 2'h0; // @[Mux.scala 27:72] + reg [1:0] buf_sz_3; // @[Reg.scala 27:20] + wire [1:0] _T_1299 = _T_1026 ? buf_sz_3 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_1300 = _T_1296 | _T_1297; // @[Mux.scala 27:72] + wire [1:0] _T_1301 = _T_1300 | _T_1298; // @[Mux.scala 27:72] + wire [1:0] _T_1302 = _T_1301 | _T_1299; // @[Mux.scala 27:72] + wire [1:0] obuf_sz_in = ibuf_buf_byp ? ibuf_sz_in : _T_1302; // @[lsu_bus_buffer.scala 295:23] + wire [7:0] _T_2079 = {4'h0,_T_2030,_T_2019,_T_2008,_T_1997}; // @[Cat.scala 29:58] + wire _T_2082 = _T_2079[4] | _T_2079[5]; // @[lsu_bus_buffer.scala 385:42] + wire _T_2084 = _T_2082 | _T_2079[6]; // @[lsu_bus_buffer.scala 385:48] + wire _T_2086 = _T_2084 | _T_2079[7]; // @[lsu_bus_buffer.scala 385:54] + wire _T_2089 = _T_2079[2] | _T_2079[3]; // @[lsu_bus_buffer.scala 385:67] + wire _T_2091 = _T_2089 | _T_2079[6]; // @[lsu_bus_buffer.scala 385:73] + wire _T_2093 = _T_2091 | _T_2079[7]; // @[lsu_bus_buffer.scala 385:79] + wire _T_2096 = _T_2079[1] | _T_2079[3]; // @[lsu_bus_buffer.scala 385:92] + wire _T_2098 = _T_2096 | _T_2079[5]; // @[lsu_bus_buffer.scala 385:98] + wire _T_2100 = _T_2098 | _T_2079[7]; // @[lsu_bus_buffer.scala 385:104] + wire [2:0] _T_2102 = {_T_2086,_T_2093,_T_2100}; // @[Cat.scala 29:58] + wire [1:0] CmdPtr1 = _T_2102[1:0]; // @[lsu_bus_buffer.scala 392:11] + wire _T_1304 = obuf_wr_en | obuf_rst; // @[lsu_bus_buffer.scala 303:39] + wire _T_1305 = ~_T_1304; // @[lsu_bus_buffer.scala 303:26] + wire _T_1311 = obuf_sz_in == 2'h0; // @[lsu_bus_buffer.scala 307:72] + wire _T_1314 = ~obuf_addr_in[0]; // @[lsu_bus_buffer.scala 307:98] + wire _T_1315 = obuf_sz_in[0] & _T_1314; // @[lsu_bus_buffer.scala 307:96] + wire _T_1316 = _T_1311 | _T_1315; // @[lsu_bus_buffer.scala 307:79] + wire _T_1319 = |obuf_addr_in[1:0]; // @[lsu_bus_buffer.scala 307:153] + wire _T_1320 = ~_T_1319; // @[lsu_bus_buffer.scala 307:134] + wire _T_1321 = obuf_sz_in[1] & _T_1320; // @[lsu_bus_buffer.scala 307:132] + wire _T_1322 = _T_1316 | _T_1321; // @[lsu_bus_buffer.scala 307:116] + wire obuf_aligned_in = ibuf_buf_byp ? is_aligned_r : _T_1322; // @[lsu_bus_buffer.scala 307:28] + wire _T_1339 = obuf_addr_in[31:3] == obuf_addr[31:3]; // @[lsu_bus_buffer.scala 321:40] + wire _T_1340 = _T_1339 & obuf_aligned_in; // @[lsu_bus_buffer.scala 321:60] + wire _T_1341 = ~obuf_sideeffect; // @[lsu_bus_buffer.scala 321:80] + wire _T_1342 = _T_1340 & _T_1341; // @[lsu_bus_buffer.scala 321:78] + wire _T_1343 = ~obuf_write; // @[lsu_bus_buffer.scala 321:99] + wire _T_1344 = _T_1342 & _T_1343; // @[lsu_bus_buffer.scala 321:97] + wire _T_1345 = ~obuf_write_in; // @[lsu_bus_buffer.scala 321:113] + wire _T_1346 = _T_1344 & _T_1345; // @[lsu_bus_buffer.scala 321:111] + wire _T_1347 = ~io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu_bus_buffer.scala 321:130] + wire _T_1348 = _T_1346 & _T_1347; // @[lsu_bus_buffer.scala 321:128] + wire _T_1349 = ~obuf_nosend; // @[lsu_bus_buffer.scala 322:20] + wire _T_1350 = obuf_valid & _T_1349; // @[lsu_bus_buffer.scala 322:18] + reg obuf_rdrsp_pend; // @[lsu_bus_buffer.scala 349:56] + wire bus_rsp_read = io_lsu_axi_r_valid & io_lsu_axi_r_ready; // @[lsu_bus_buffer.scala 559:38] + reg [2:0] obuf_rdrsp_tag; // @[lsu_bus_buffer.scala 350:55] + wire _T_1351 = io_lsu_axi_r_bits_id == obuf_rdrsp_tag; // @[lsu_bus_buffer.scala 322:90] + wire _T_1352 = bus_rsp_read & _T_1351; // @[lsu_bus_buffer.scala 322:70] + wire _T_1353 = ~_T_1352; // @[lsu_bus_buffer.scala 322:55] + wire _T_1354 = obuf_rdrsp_pend & _T_1353; // @[lsu_bus_buffer.scala 322:53] + wire _T_1355 = _T_1350 | _T_1354; // @[lsu_bus_buffer.scala 322:34] + wire obuf_nosend_in = _T_1348 & _T_1355; // @[lsu_bus_buffer.scala 321:177] + wire _T_1323 = ~obuf_nosend_in; // @[lsu_bus_buffer.scala 315:44] + wire _T_1324 = obuf_wr_en & _T_1323; // @[lsu_bus_buffer.scala 315:42] + wire _T_1325 = ~_T_1324; // @[lsu_bus_buffer.scala 315:29] + wire _T_1326 = _T_1325 & obuf_rdrsp_pend; // @[lsu_bus_buffer.scala 315:61] + wire _T_1330 = _T_1326 & _T_1353; // @[lsu_bus_buffer.scala 315:79] + wire _T_1332 = bus_cmd_sent & _T_1343; // @[lsu_bus_buffer.scala 316:20] + wire _T_1333 = ~io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 316:37] + wire _T_1334 = _T_1332 & _T_1333; // @[lsu_bus_buffer.scala 316:35] + wire [7:0] _T_1358 = {ldst_byteen_lo_r,4'h0}; // @[Cat.scala 29:58] + wire [7:0] _T_1359 = {4'h0,ldst_byteen_lo_r}; // @[Cat.scala 29:58] + wire [7:0] _T_1360 = io_lsu_addr_r[2] ? _T_1358 : _T_1359; // @[lsu_bus_buffer.scala 323:46] + wire [3:0] _T_1379 = _T_1023 ? buf_byteen_0 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1380 = _T_1024 ? buf_byteen_1 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1381 = _T_1025 ? buf_byteen_2 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1382 = _T_1026 ? buf_byteen_3 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1383 = _T_1379 | _T_1380; // @[Mux.scala 27:72] + wire [3:0] _T_1384 = _T_1383 | _T_1381; // @[Mux.scala 27:72] + wire [3:0] _T_1385 = _T_1384 | _T_1382; // @[Mux.scala 27:72] + wire [7:0] _T_1387 = {_T_1385,4'h0}; // @[Cat.scala 29:58] + wire [7:0] _T_1400 = {4'h0,_T_1385}; // @[Cat.scala 29:58] + wire [7:0] _T_1401 = _T_1289[2] ? _T_1387 : _T_1400; // @[lsu_bus_buffer.scala 324:8] + wire [7:0] obuf_byteen0_in = ibuf_buf_byp ? _T_1360 : _T_1401; // @[lsu_bus_buffer.scala 323:28] + wire [7:0] _T_1403 = {ldst_byteen_hi_r,4'h0}; // @[Cat.scala 29:58] + wire [7:0] _T_1404 = {4'h0,ldst_byteen_hi_r}; // @[Cat.scala 29:58] + wire [7:0] _T_1405 = io_end_addr_r[2] ? _T_1403 : _T_1404; // @[lsu_bus_buffer.scala 325:46] + wire _T_1406 = CmdPtr1 == 2'h0; // @[lsu_bus_buffer.scala 58:123] + wire _T_1407 = CmdPtr1 == 2'h1; // @[lsu_bus_buffer.scala 58:123] + wire _T_1408 = CmdPtr1 == 2'h2; // @[lsu_bus_buffer.scala 58:123] + wire _T_1409 = CmdPtr1 == 2'h3; // @[lsu_bus_buffer.scala 58:123] + wire [31:0] _T_1410 = _T_1406 ? buf_addr_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1411 = _T_1407 ? buf_addr_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1412 = _T_1408 ? buf_addr_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1413 = _T_1409 ? buf_addr_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1414 = _T_1410 | _T_1411; // @[Mux.scala 27:72] + wire [31:0] _T_1415 = _T_1414 | _T_1412; // @[Mux.scala 27:72] + wire [31:0] _T_1416 = _T_1415 | _T_1413; // @[Mux.scala 27:72] + wire [3:0] _T_1424 = _T_1406 ? buf_byteen_0 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1425 = _T_1407 ? buf_byteen_1 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1426 = _T_1408 ? buf_byteen_2 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1427 = _T_1409 ? buf_byteen_3 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1428 = _T_1424 | _T_1425; // @[Mux.scala 27:72] + wire [3:0] _T_1429 = _T_1428 | _T_1426; // @[Mux.scala 27:72] + wire [3:0] _T_1430 = _T_1429 | _T_1427; // @[Mux.scala 27:72] + wire [7:0] _T_1432 = {_T_1430,4'h0}; // @[Cat.scala 29:58] + wire [7:0] _T_1445 = {4'h0,_T_1430}; // @[Cat.scala 29:58] + wire [7:0] _T_1446 = _T_1416[2] ? _T_1432 : _T_1445; // @[lsu_bus_buffer.scala 326:8] + wire [7:0] obuf_byteen1_in = ibuf_buf_byp ? _T_1405 : _T_1446; // @[lsu_bus_buffer.scala 325:28] + wire [63:0] _T_1448 = {store_data_lo_r,32'h0}; // @[Cat.scala 29:58] + wire [63:0] _T_1449 = {32'h0,store_data_lo_r}; // @[Cat.scala 29:58] + wire [63:0] _T_1450 = io_lsu_addr_r[2] ? _T_1448 : _T_1449; // @[lsu_bus_buffer.scala 328:44] + wire [31:0] _T_1469 = _T_1023 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1470 = _T_1024 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1471 = _T_1025 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1472 = _T_1026 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1473 = _T_1469 | _T_1470; // @[Mux.scala 27:72] + wire [31:0] _T_1474 = _T_1473 | _T_1471; // @[Mux.scala 27:72] + wire [31:0] _T_1475 = _T_1474 | _T_1472; // @[Mux.scala 27:72] + wire [63:0] _T_1477 = {_T_1475,32'h0}; // @[Cat.scala 29:58] + wire [63:0] _T_1490 = {32'h0,_T_1475}; // @[Cat.scala 29:58] + wire [63:0] _T_1491 = _T_1289[2] ? _T_1477 : _T_1490; // @[lsu_bus_buffer.scala 329:8] + wire [63:0] obuf_data0_in = ibuf_buf_byp ? _T_1450 : _T_1491; // @[lsu_bus_buffer.scala 328:26] + wire [63:0] _T_1493 = {store_data_hi_r,32'h0}; // @[Cat.scala 29:58] + wire [63:0] _T_1494 = {32'h0,store_data_hi_r}; // @[Cat.scala 29:58] + wire [63:0] _T_1495 = io_lsu_addr_r[2] ? _T_1493 : _T_1494; // @[lsu_bus_buffer.scala 330:44] + wire [31:0] _T_1514 = _T_1406 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1515 = _T_1407 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1516 = _T_1408 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1517 = _T_1409 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1518 = _T_1514 | _T_1515; // @[Mux.scala 27:72] + wire [31:0] _T_1519 = _T_1518 | _T_1516; // @[Mux.scala 27:72] + wire [31:0] _T_1520 = _T_1519 | _T_1517; // @[Mux.scala 27:72] + wire [63:0] _T_1522 = {_T_1520,32'h0}; // @[Cat.scala 29:58] + wire [63:0] _T_1535 = {32'h0,_T_1520}; // @[Cat.scala 29:58] + wire [63:0] _T_1536 = _T_1416[2] ? _T_1522 : _T_1535; // @[lsu_bus_buffer.scala 331:8] + wire [63:0] obuf_data1_in = ibuf_buf_byp ? _T_1495 : _T_1536; // @[lsu_bus_buffer.scala 330:26] + wire _T_1621 = CmdPtr0 != CmdPtr1; // @[lsu_bus_buffer.scala 337:30] + wire _T_1622 = _T_1621 & found_cmdptr0; // @[lsu_bus_buffer.scala 337:43] + wire _T_1623 = _T_1622 & found_cmdptr1; // @[lsu_bus_buffer.scala 337:59] + wire _T_1637 = _T_1623 & _T_1107; // @[lsu_bus_buffer.scala 337:75] + wire [2:0] _T_1642 = _T_1406 ? buf_state_0 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1643 = _T_1407 ? buf_state_1 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1646 = _T_1642 | _T_1643; // @[Mux.scala 27:72] + wire [2:0] _T_1644 = _T_1408 ? buf_state_2 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1647 = _T_1646 | _T_1644; // @[Mux.scala 27:72] + wire [2:0] _T_1645 = _T_1409 ? buf_state_3 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1648 = _T_1647 | _T_1645; // @[Mux.scala 27:72] + wire _T_1650 = _T_1648 == 3'h2; // @[lsu_bus_buffer.scala 337:150] + wire _T_1651 = _T_1637 & _T_1650; // @[lsu_bus_buffer.scala 337:118] + wire _T_1672 = _T_1651 & _T_1128; // @[lsu_bus_buffer.scala 337:161] + wire _T_1690 = _T_1672 & _T_1053; // @[lsu_bus_buffer.scala 338:85] + wire _T_1715 = _T_1406 & buf_write[0]; // @[Mux.scala 27:72] + wire _T_1716 = _T_1407 & buf_write[1]; // @[Mux.scala 27:72] + wire _T_1719 = _T_1715 | _T_1716; // @[Mux.scala 27:72] + wire _T_1717 = _T_1408 & buf_write[2]; // @[Mux.scala 27:72] + wire _T_1720 = _T_1719 | _T_1717; // @[Mux.scala 27:72] + wire _T_1718 = _T_1409 & buf_write[3]; // @[Mux.scala 27:72] + wire _T_1721 = _T_1720 | _T_1718; // @[Mux.scala 27:72] + wire _T_1723 = _T_1202 & _T_1721; // @[lsu_bus_buffer.scala 339:36] + wire _T_1750 = _T_1289[31:3] == _T_1416[31:3]; // @[lsu_bus_buffer.scala 340:41] + wire _T_1751 = _T_1723 & _T_1750; // @[lsu_bus_buffer.scala 339:67] + wire _T_1753 = _T_1751 & _T_938; // @[lsu_bus_buffer.scala 340:79] + wire _T_1792 = _T_1204 & _T_1166; // @[lsu_bus_buffer.scala 341:38] + reg buf_dualhi_3; // @[Reg.scala 27:20] + reg buf_dualhi_2; // @[Reg.scala 27:20] + reg buf_dualhi_1; // @[Reg.scala 27:20] + reg buf_dualhi_0; // @[Reg.scala 27:20] + wire [3:0] _T_1795 = {buf_dualhi_3,buf_dualhi_2,buf_dualhi_1,buf_dualhi_0}; // @[Cat.scala 29:58] + wire _T_1804 = _T_1023 & _T_1795[0]; // @[Mux.scala 27:72] + wire _T_1805 = _T_1024 & _T_1795[1]; // @[Mux.scala 27:72] + wire _T_1808 = _T_1804 | _T_1805; // @[Mux.scala 27:72] + wire _T_1806 = _T_1025 & _T_1795[2]; // @[Mux.scala 27:72] + wire _T_1809 = _T_1808 | _T_1806; // @[Mux.scala 27:72] + wire _T_1807 = _T_1026 & _T_1795[3]; // @[Mux.scala 27:72] + wire _T_1810 = _T_1809 | _T_1807; // @[Mux.scala 27:72] + wire _T_1812 = ~_T_1810; // @[lsu_bus_buffer.scala 341:109] + wire _T_1813 = _T_1792 & _T_1812; // @[lsu_bus_buffer.scala 341:107] + wire _T_1833 = _T_1813 & _T_1185; // @[lsu_bus_buffer.scala 341:179] + wire _T_1834 = _T_1753 | _T_1833; // @[lsu_bus_buffer.scala 340:128] + wire _T_1835 = _T_1690 & _T_1834; // @[lsu_bus_buffer.scala 338:122] + wire _T_1836 = ibuf_buf_byp & ldst_samedw_r; // @[lsu_bus_buffer.scala 342:19] + wire _T_1837 = _T_1836 & io_ldst_dual_r; // @[lsu_bus_buffer.scala 342:35] + wire obuf_merge_en = _T_1835 | _T_1837; // @[lsu_bus_buffer.scala 341:253] + wire _T_1539 = obuf_merge_en & obuf_byteen1_in[0]; // @[lsu_bus_buffer.scala 332:80] + wire _T_1540 = obuf_byteen0_in[0] | _T_1539; // @[lsu_bus_buffer.scala 332:63] + wire _T_1543 = obuf_merge_en & obuf_byteen1_in[1]; // @[lsu_bus_buffer.scala 332:80] + wire _T_1544 = obuf_byteen0_in[1] | _T_1543; // @[lsu_bus_buffer.scala 332:63] + wire _T_1547 = obuf_merge_en & obuf_byteen1_in[2]; // @[lsu_bus_buffer.scala 332:80] + wire _T_1548 = obuf_byteen0_in[2] | _T_1547; // @[lsu_bus_buffer.scala 332:63] + wire _T_1551 = obuf_merge_en & obuf_byteen1_in[3]; // @[lsu_bus_buffer.scala 332:80] + wire _T_1552 = obuf_byteen0_in[3] | _T_1551; // @[lsu_bus_buffer.scala 332:63] + wire _T_1555 = obuf_merge_en & obuf_byteen1_in[4]; // @[lsu_bus_buffer.scala 332:80] + wire _T_1556 = obuf_byteen0_in[4] | _T_1555; // @[lsu_bus_buffer.scala 332:63] + wire _T_1559 = obuf_merge_en & obuf_byteen1_in[5]; // @[lsu_bus_buffer.scala 332:80] + wire _T_1560 = obuf_byteen0_in[5] | _T_1559; // @[lsu_bus_buffer.scala 332:63] + wire _T_1563 = obuf_merge_en & obuf_byteen1_in[6]; // @[lsu_bus_buffer.scala 332:80] + wire _T_1564 = obuf_byteen0_in[6] | _T_1563; // @[lsu_bus_buffer.scala 332:63] + wire _T_1567 = obuf_merge_en & obuf_byteen1_in[7]; // @[lsu_bus_buffer.scala 332:80] + wire _T_1568 = obuf_byteen0_in[7] | _T_1567; // @[lsu_bus_buffer.scala 332:63] + wire [7:0] obuf_byteen_in = {_T_1568,_T_1564,_T_1560,_T_1556,_T_1552,_T_1548,_T_1544,_T_1540}; // @[Cat.scala 29:58] + wire [7:0] _T_1579 = _T_1539 ? obuf_data1_in[7:0] : obuf_data0_in[7:0]; // @[lsu_bus_buffer.scala 333:44] + wire [7:0] _T_1584 = _T_1543 ? obuf_data1_in[15:8] : obuf_data0_in[15:8]; // @[lsu_bus_buffer.scala 333:44] + wire [7:0] _T_1589 = _T_1547 ? obuf_data1_in[23:16] : obuf_data0_in[23:16]; // @[lsu_bus_buffer.scala 333:44] + wire [7:0] _T_1594 = _T_1551 ? obuf_data1_in[31:24] : obuf_data0_in[31:24]; // @[lsu_bus_buffer.scala 333:44] + wire [7:0] _T_1599 = _T_1555 ? obuf_data1_in[39:32] : obuf_data0_in[39:32]; // @[lsu_bus_buffer.scala 333:44] + wire [7:0] _T_1604 = _T_1559 ? obuf_data1_in[47:40] : obuf_data0_in[47:40]; // @[lsu_bus_buffer.scala 333:44] + wire [7:0] _T_1609 = _T_1563 ? obuf_data1_in[55:48] : obuf_data0_in[55:48]; // @[lsu_bus_buffer.scala 333:44] + wire [7:0] _T_1614 = _T_1567 ? obuf_data1_in[63:56] : obuf_data0_in[63:56]; // @[lsu_bus_buffer.scala 333:44] + wire [55:0] _T_1620 = {_T_1614,_T_1609,_T_1604,_T_1599,_T_1594,_T_1589,_T_1584}; // @[Cat.scala 29:58] + wire _T_1839 = obuf_wr_en | obuf_valid; // @[lsu_bus_buffer.scala 345:58] + wire _T_1840 = ~obuf_rst; // @[lsu_bus_buffer.scala 345:93] + reg [1:0] obuf_sz; // @[Reg.scala 27:20] + reg [7:0] obuf_byteen; // @[Reg.scala 27:20] + reg [63:0] obuf_data; // @[lib.scala 374:16] + wire _T_1853 = buf_state_0 == 3'h0; // @[lsu_bus_buffer.scala 363:65] + wire _T_1854 = ibuf_tag == 2'h0; // @[lsu_bus_buffer.scala 364:30] + wire _T_1855 = ibuf_valid & _T_1854; // @[lsu_bus_buffer.scala 364:19] + wire _T_1856 = WrPtr0_r == 2'h0; // @[lsu_bus_buffer.scala 365:18] + wire _T_1857 = WrPtr1_r == 2'h0; // @[lsu_bus_buffer.scala 365:57] + wire _T_1858 = io_ldst_dual_r & _T_1857; // @[lsu_bus_buffer.scala 365:45] + wire _T_1859 = _T_1856 | _T_1858; // @[lsu_bus_buffer.scala 365:27] + wire _T_1860 = io_lsu_busreq_r & _T_1859; // @[lsu_bus_buffer.scala 364:58] + wire _T_1861 = _T_1855 | _T_1860; // @[lsu_bus_buffer.scala 364:39] + wire _T_1862 = ~_T_1861; // @[lsu_bus_buffer.scala 364:5] + wire _T_1863 = _T_1853 & _T_1862; // @[lsu_bus_buffer.scala 363:76] + wire _T_1864 = buf_state_1 == 3'h0; // @[lsu_bus_buffer.scala 363:65] + wire _T_1865 = ibuf_tag == 2'h1; // @[lsu_bus_buffer.scala 364:30] + wire _T_1866 = ibuf_valid & _T_1865; // @[lsu_bus_buffer.scala 364:19] + wire _T_1867 = WrPtr0_r == 2'h1; // @[lsu_bus_buffer.scala 365:18] + wire _T_1868 = WrPtr1_r == 2'h1; // @[lsu_bus_buffer.scala 365:57] + wire _T_1869 = io_ldst_dual_r & _T_1868; // @[lsu_bus_buffer.scala 365:45] + wire _T_1870 = _T_1867 | _T_1869; // @[lsu_bus_buffer.scala 365:27] + wire _T_1871 = io_lsu_busreq_r & _T_1870; // @[lsu_bus_buffer.scala 364:58] + wire _T_1872 = _T_1866 | _T_1871; // @[lsu_bus_buffer.scala 364:39] + wire _T_1873 = ~_T_1872; // @[lsu_bus_buffer.scala 364:5] + wire _T_1874 = _T_1864 & _T_1873; // @[lsu_bus_buffer.scala 363:76] + wire _T_1875 = buf_state_2 == 3'h0; // @[lsu_bus_buffer.scala 363:65] + wire _T_1876 = ibuf_tag == 2'h2; // @[lsu_bus_buffer.scala 364:30] + wire _T_1877 = ibuf_valid & _T_1876; // @[lsu_bus_buffer.scala 364:19] + wire _T_1878 = WrPtr0_r == 2'h2; // @[lsu_bus_buffer.scala 365:18] + wire _T_1879 = WrPtr1_r == 2'h2; // @[lsu_bus_buffer.scala 365:57] + wire _T_1880 = io_ldst_dual_r & _T_1879; // @[lsu_bus_buffer.scala 365:45] + wire _T_1881 = _T_1878 | _T_1880; // @[lsu_bus_buffer.scala 365:27] + wire _T_1882 = io_lsu_busreq_r & _T_1881; // @[lsu_bus_buffer.scala 364:58] + wire _T_1883 = _T_1877 | _T_1882; // @[lsu_bus_buffer.scala 364:39] + wire _T_1884 = ~_T_1883; // @[lsu_bus_buffer.scala 364:5] + wire _T_1885 = _T_1875 & _T_1884; // @[lsu_bus_buffer.scala 363:76] + wire _T_1886 = buf_state_3 == 3'h0; // @[lsu_bus_buffer.scala 363:65] + wire _T_1887 = ibuf_tag == 2'h3; // @[lsu_bus_buffer.scala 364:30] + wire _T_1889 = WrPtr0_r == 2'h3; // @[lsu_bus_buffer.scala 365:18] + wire _T_1890 = WrPtr1_r == 2'h3; // @[lsu_bus_buffer.scala 365:57] + wire [1:0] _T_1898 = _T_1885 ? 2'h2 : 2'h3; // @[Mux.scala 98:16] + wire [1:0] _T_1899 = _T_1874 ? 2'h1 : _T_1898; // @[Mux.scala 98:16] + wire [1:0] WrPtr0_m = _T_1863 ? 2'h0 : _T_1899; // @[Mux.scala 98:16] + wire _T_1904 = WrPtr0_m == 2'h0; // @[lsu_bus_buffer.scala 370:33] + wire _T_1905 = io_lsu_busreq_m & _T_1904; // @[lsu_bus_buffer.scala 370:22] + wire _T_1906 = _T_1855 | _T_1905; // @[lsu_bus_buffer.scala 369:112] + wire _T_1912 = _T_1906 | _T_1860; // @[lsu_bus_buffer.scala 370:42] + wire _T_1913 = ~_T_1912; // @[lsu_bus_buffer.scala 369:78] + wire _T_1914 = _T_1853 & _T_1913; // @[lsu_bus_buffer.scala 369:76] + wire _T_1918 = WrPtr0_m == 2'h1; // @[lsu_bus_buffer.scala 370:33] + wire _T_1919 = io_lsu_busreq_m & _T_1918; // @[lsu_bus_buffer.scala 370:22] + wire _T_1920 = _T_1866 | _T_1919; // @[lsu_bus_buffer.scala 369:112] + wire _T_1926 = _T_1920 | _T_1871; // @[lsu_bus_buffer.scala 370:42] + wire _T_1927 = ~_T_1926; // @[lsu_bus_buffer.scala 369:78] + wire _T_1928 = _T_1864 & _T_1927; // @[lsu_bus_buffer.scala 369:76] + wire _T_1932 = WrPtr0_m == 2'h2; // @[lsu_bus_buffer.scala 370:33] + wire _T_1933 = io_lsu_busreq_m & _T_1932; // @[lsu_bus_buffer.scala 370:22] + wire _T_1934 = _T_1877 | _T_1933; // @[lsu_bus_buffer.scala 369:112] + wire _T_1940 = _T_1934 | _T_1882; // @[lsu_bus_buffer.scala 370:42] + wire _T_1941 = ~_T_1940; // @[lsu_bus_buffer.scala 369:78] + wire _T_1942 = _T_1875 & _T_1941; // @[lsu_bus_buffer.scala 369:76] + reg [3:0] buf_rspageQ_0; // @[lsu_bus_buffer.scala 500:63] + wire _T_2746 = buf_state_3 == 3'h5; // @[lsu_bus_buffer.scala 413:102] + wire _T_2747 = buf_rspageQ_0[3] & _T_2746; // @[lsu_bus_buffer.scala 413:87] + wire _T_2743 = buf_state_2 == 3'h5; // @[lsu_bus_buffer.scala 413:102] + wire _T_2744 = buf_rspageQ_0[2] & _T_2743; // @[lsu_bus_buffer.scala 413:87] + wire _T_2740 = buf_state_1 == 3'h5; // @[lsu_bus_buffer.scala 413:102] + wire _T_2741 = buf_rspageQ_0[1] & _T_2740; // @[lsu_bus_buffer.scala 413:87] + wire _T_2737 = buf_state_0 == 3'h5; // @[lsu_bus_buffer.scala 413:102] + wire _T_2738 = buf_rspageQ_0[0] & _T_2737; // @[lsu_bus_buffer.scala 413:87] + wire [3:0] buf_rsp_pickage_0 = {_T_2747,_T_2744,_T_2741,_T_2738}; // @[Cat.scala 29:58] + wire _T_2033 = |buf_rsp_pickage_0; // @[lsu_bus_buffer.scala 381:65] + wire _T_2034 = ~_T_2033; // @[lsu_bus_buffer.scala 381:44] + wire _T_2036 = _T_2034 & _T_2737; // @[lsu_bus_buffer.scala 381:70] + reg [3:0] buf_rspageQ_1; // @[lsu_bus_buffer.scala 500:63] + wire _T_2762 = buf_rspageQ_1[3] & _T_2746; // @[lsu_bus_buffer.scala 413:87] + wire _T_2759 = buf_rspageQ_1[2] & _T_2743; // @[lsu_bus_buffer.scala 413:87] + wire _T_2756 = buf_rspageQ_1[1] & _T_2740; // @[lsu_bus_buffer.scala 413:87] + wire _T_2753 = buf_rspageQ_1[0] & _T_2737; // @[lsu_bus_buffer.scala 413:87] + wire [3:0] buf_rsp_pickage_1 = {_T_2762,_T_2759,_T_2756,_T_2753}; // @[Cat.scala 29:58] + wire _T_2037 = |buf_rsp_pickage_1; // @[lsu_bus_buffer.scala 381:65] + wire _T_2038 = ~_T_2037; // @[lsu_bus_buffer.scala 381:44] + wire _T_2040 = _T_2038 & _T_2740; // @[lsu_bus_buffer.scala 381:70] + reg [3:0] buf_rspageQ_2; // @[lsu_bus_buffer.scala 500:63] + wire _T_2777 = buf_rspageQ_2[3] & _T_2746; // @[lsu_bus_buffer.scala 413:87] + wire _T_2774 = buf_rspageQ_2[2] & _T_2743; // @[lsu_bus_buffer.scala 413:87] + wire _T_2771 = buf_rspageQ_2[1] & _T_2740; // @[lsu_bus_buffer.scala 413:87] + wire _T_2768 = buf_rspageQ_2[0] & _T_2737; // @[lsu_bus_buffer.scala 413:87] + wire [3:0] buf_rsp_pickage_2 = {_T_2777,_T_2774,_T_2771,_T_2768}; // @[Cat.scala 29:58] + wire _T_2041 = |buf_rsp_pickage_2; // @[lsu_bus_buffer.scala 381:65] + wire _T_2042 = ~_T_2041; // @[lsu_bus_buffer.scala 381:44] + wire _T_2044 = _T_2042 & _T_2743; // @[lsu_bus_buffer.scala 381:70] + reg [3:0] buf_rspageQ_3; // @[lsu_bus_buffer.scala 500:63] + wire _T_2792 = buf_rspageQ_3[3] & _T_2746; // @[lsu_bus_buffer.scala 413:87] + wire _T_2789 = buf_rspageQ_3[2] & _T_2743; // @[lsu_bus_buffer.scala 413:87] + wire _T_2786 = buf_rspageQ_3[1] & _T_2740; // @[lsu_bus_buffer.scala 413:87] + wire _T_2783 = buf_rspageQ_3[0] & _T_2737; // @[lsu_bus_buffer.scala 413:87] + wire [3:0] buf_rsp_pickage_3 = {_T_2792,_T_2789,_T_2786,_T_2783}; // @[Cat.scala 29:58] + wire _T_2045 = |buf_rsp_pickage_3; // @[lsu_bus_buffer.scala 381:65] + wire _T_2046 = ~_T_2045; // @[lsu_bus_buffer.scala 381:44] + wire _T_2048 = _T_2046 & _T_2746; // @[lsu_bus_buffer.scala 381:70] + wire [7:0] _T_2104 = {4'h0,_T_2048,_T_2044,_T_2040,_T_2036}; // @[Cat.scala 29:58] + wire _T_2107 = _T_2104[4] | _T_2104[5]; // @[lsu_bus_buffer.scala 385:42] + wire _T_2109 = _T_2107 | _T_2104[6]; // @[lsu_bus_buffer.scala 385:48] + wire _T_2111 = _T_2109 | _T_2104[7]; // @[lsu_bus_buffer.scala 385:54] + wire _T_2114 = _T_2104[2] | _T_2104[3]; // @[lsu_bus_buffer.scala 385:67] + wire _T_2116 = _T_2114 | _T_2104[6]; // @[lsu_bus_buffer.scala 385:73] + wire _T_2118 = _T_2116 | _T_2104[7]; // @[lsu_bus_buffer.scala 385:79] + wire _T_2121 = _T_2104[1] | _T_2104[3]; // @[lsu_bus_buffer.scala 385:92] + wire _T_2123 = _T_2121 | _T_2104[5]; // @[lsu_bus_buffer.scala 385:98] + wire _T_2125 = _T_2123 | _T_2104[7]; // @[lsu_bus_buffer.scala 385:104] + wire [2:0] _T_2127 = {_T_2111,_T_2118,_T_2125}; // @[Cat.scala 29:58] + wire _T_3532 = ibuf_byp | io_ldst_dual_r; // @[lsu_bus_buffer.scala 443:77] + wire _T_3533 = ~ibuf_merge_en; // @[lsu_bus_buffer.scala 443:97] + wire _T_3534 = _T_3532 & _T_3533; // @[lsu_bus_buffer.scala 443:95] + wire _T_3535 = 2'h0 == WrPtr0_r; // @[lsu_bus_buffer.scala 443:117] + wire _T_3536 = _T_3534 & _T_3535; // @[lsu_bus_buffer.scala 443:112] + wire _T_3537 = ibuf_byp & io_ldst_dual_r; // @[lsu_bus_buffer.scala 443:144] + wire _T_3538 = 2'h0 == WrPtr1_r; // @[lsu_bus_buffer.scala 443:166] + wire _T_3539 = _T_3537 & _T_3538; // @[lsu_bus_buffer.scala 443:161] + wire _T_3540 = _T_3536 | _T_3539; // @[lsu_bus_buffer.scala 443:132] + wire _T_3541 = _T_853 & _T_3540; // @[lsu_bus_buffer.scala 443:63] + wire _T_3542 = 2'h0 == ibuf_tag; // @[lsu_bus_buffer.scala 443:206] + wire _T_3543 = ibuf_drain_vld & _T_3542; // @[lsu_bus_buffer.scala 443:201] + wire _T_3544 = _T_3541 | _T_3543; // @[lsu_bus_buffer.scala 443:183] + wire _T_3554 = io_lsu_bus_clk_en | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 450:46] + wire _T_3589 = 3'h3 == buf_state_0; // @[Conditional.scala 37:30] + wire bus_rsp_write = io_lsu_axi_b_valid & io_lsu_axi_b_ready; // @[lsu_bus_buffer.scala 560:39] + wire _T_3634 = io_lsu_axi_b_bits_id == 3'h0; // @[lsu_bus_buffer.scala 468:73] + wire _T_3635 = bus_rsp_write & _T_3634; // @[lsu_bus_buffer.scala 468:52] + wire _T_3636 = io_lsu_axi_r_bits_id == 3'h0; // @[lsu_bus_buffer.scala 469:46] + reg _T_4307; // @[Reg.scala 27:20] + reg _T_4305; // @[Reg.scala 27:20] + reg _T_4303; // @[Reg.scala 27:20] + reg _T_4301; // @[Reg.scala 27:20] + wire [3:0] buf_ldfwd = {_T_4307,_T_4305,_T_4303,_T_4301}; // @[Cat.scala 29:58] + reg [1:0] buf_ldfwdtag_0; // @[Reg.scala 27:20] + wire [2:0] _GEN_368 = {{1'd0}, buf_ldfwdtag_0}; // @[lsu_bus_buffer.scala 470:47] + wire _T_3638 = io_lsu_axi_r_bits_id == _GEN_368; // @[lsu_bus_buffer.scala 470:47] + wire _T_3639 = buf_ldfwd[0] & _T_3638; // @[lsu_bus_buffer.scala 470:27] + wire _T_3640 = _T_3636 | _T_3639; // @[lsu_bus_buffer.scala 469:77] + wire _T_3641 = buf_dual_0 & buf_dualhi_0; // @[lsu_bus_buffer.scala 471:26] + wire _T_3643 = ~buf_write[0]; // @[lsu_bus_buffer.scala 471:44] + wire _T_3644 = _T_3641 & _T_3643; // @[lsu_bus_buffer.scala 471:42] + wire _T_3645 = _T_3644 & buf_samedw_0; // @[lsu_bus_buffer.scala 471:58] + reg [1:0] buf_dualtag_0; // @[Reg.scala 27:20] + wire [2:0] _GEN_369 = {{1'd0}, buf_dualtag_0}; // @[lsu_bus_buffer.scala 471:94] + wire _T_3646 = io_lsu_axi_r_bits_id == _GEN_369; // @[lsu_bus_buffer.scala 471:94] + wire _T_3647 = _T_3645 & _T_3646; // @[lsu_bus_buffer.scala 471:74] + wire _T_3648 = _T_3640 | _T_3647; // @[lsu_bus_buffer.scala 470:71] + wire _T_3649 = bus_rsp_read & _T_3648; // @[lsu_bus_buffer.scala 469:25] + wire _T_3650 = _T_3635 | _T_3649; // @[lsu_bus_buffer.scala 468:105] + wire _GEN_42 = _T_3589 & _T_3650; // @[Conditional.scala 39:67] + wire _GEN_61 = _T_3555 ? 1'h0 : _GEN_42; // @[Conditional.scala 39:67] + wire _GEN_73 = _T_3551 ? 1'h0 : _GEN_61; // @[Conditional.scala 39:67] + wire buf_resp_state_bus_en_0 = _T_3528 ? 1'h0 : _GEN_73; // @[Conditional.scala 40:58] + wire _T_3676 = 3'h4 == buf_state_0; // @[Conditional.scala 37:30] + wire [3:0] _T_3686 = buf_ldfwd >> buf_dualtag_0; // @[lsu_bus_buffer.scala 483:21] + reg [1:0] buf_ldfwdtag_3; // @[Reg.scala 27:20] + reg [1:0] buf_ldfwdtag_2; // @[Reg.scala 27:20] + reg [1:0] buf_ldfwdtag_1; // @[Reg.scala 27:20] + wire [1:0] _GEN_23 = 2'h1 == buf_dualtag_0 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[lsu_bus_buffer.scala 483:58] + wire [1:0] _GEN_24 = 2'h2 == buf_dualtag_0 ? buf_ldfwdtag_2 : _GEN_23; // @[lsu_bus_buffer.scala 483:58] + wire [1:0] _GEN_25 = 2'h3 == buf_dualtag_0 ? buf_ldfwdtag_3 : _GEN_24; // @[lsu_bus_buffer.scala 483:58] + wire [2:0] _GEN_371 = {{1'd0}, _GEN_25}; // @[lsu_bus_buffer.scala 483:58] + wire _T_3688 = io_lsu_axi_r_bits_id == _GEN_371; // @[lsu_bus_buffer.scala 483:58] + wire _T_3689 = _T_3686[0] & _T_3688; // @[lsu_bus_buffer.scala 483:38] + wire _T_3690 = _T_3646 | _T_3689; // @[lsu_bus_buffer.scala 482:95] + wire _T_3691 = bus_rsp_read & _T_3690; // @[lsu_bus_buffer.scala 482:45] + wire _GEN_36 = _T_3676 & _T_3691; // @[Conditional.scala 39:67] + wire _GEN_43 = _T_3589 ? buf_resp_state_bus_en_0 : _GEN_36; // @[Conditional.scala 39:67] + wire _GEN_53 = _T_3555 ? buf_cmd_state_bus_en_0 : _GEN_43; // @[Conditional.scala 39:67] + wire _GEN_66 = _T_3551 ? 1'h0 : _GEN_53; // @[Conditional.scala 39:67] + wire buf_state_bus_en_0 = _T_3528 ? 1'h0 : _GEN_66; // @[Conditional.scala 40:58] + wire _T_3568 = buf_state_bus_en_0 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 456:49] + wire _T_3569 = _T_3568 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 456:70] + wire _T_3694 = 3'h5 == buf_state_0; // @[Conditional.scala 37:30] + wire [1:0] RspPtr = _T_2127[1:0]; // @[lsu_bus_buffer.scala 393:10] + wire _T_3697 = RspPtr == 2'h0; // @[lsu_bus_buffer.scala 488:37] + wire _T_3698 = buf_dualtag_0 == RspPtr; // @[lsu_bus_buffer.scala 488:98] + wire _T_3699 = buf_dual_0 & _T_3698; // @[lsu_bus_buffer.scala 488:80] + wire _T_3700 = _T_3697 | _T_3699; // @[lsu_bus_buffer.scala 488:65] + wire _T_3701 = _T_3700 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 488:112] + wire _T_3702 = 3'h6 == buf_state_0; // @[Conditional.scala 37:30] + wire _GEN_31 = _T_3694 ? _T_3701 : _T_3702; // @[Conditional.scala 39:67] + wire _GEN_37 = _T_3676 ? _T_3569 : _GEN_31; // @[Conditional.scala 39:67] + wire _GEN_44 = _T_3589 ? _T_3569 : _GEN_37; // @[Conditional.scala 39:67] + wire _GEN_54 = _T_3555 ? _T_3569 : _GEN_44; // @[Conditional.scala 39:67] + wire _GEN_64 = _T_3551 ? _T_3554 : _GEN_54; // @[Conditional.scala 39:67] + wire buf_state_en_0 = _T_3528 ? _T_3544 : _GEN_64; // @[Conditional.scala 40:58] + wire _T_2129 = _T_1853 & buf_state_en_0; // @[lsu_bus_buffer.scala 405:94] + wire _T_2135 = ibuf_drain_vld & io_lsu_busreq_r; // @[lsu_bus_buffer.scala 407:23] + wire _T_2137 = _T_2135 & _T_3532; // @[lsu_bus_buffer.scala 407:41] + wire _T_2139 = _T_2137 & _T_1856; // @[lsu_bus_buffer.scala 407:71] + wire _T_2141 = _T_2139 & _T_1854; // @[lsu_bus_buffer.scala 407:92] + wire _T_2142 = _T_4471 | _T_2141; // @[lsu_bus_buffer.scala 406:86] + wire _T_2143 = ibuf_byp & io_lsu_busreq_r; // @[lsu_bus_buffer.scala 408:17] + wire _T_2144 = _T_2143 & io_ldst_dual_r; // @[lsu_bus_buffer.scala 408:35] + wire _T_2146 = _T_2144 & _T_1857; // @[lsu_bus_buffer.scala 408:52] + wire _T_2148 = _T_2146 & _T_1856; // @[lsu_bus_buffer.scala 408:73] + wire _T_2149 = _T_2142 | _T_2148; // @[lsu_bus_buffer.scala 407:114] + wire _T_2150 = _T_2129 & _T_2149; // @[lsu_bus_buffer.scala 405:113] + wire _T_2152 = _T_2150 | buf_age_0[0]; // @[lsu_bus_buffer.scala 408:97] + wire _T_2166 = _T_2139 & _T_1865; // @[lsu_bus_buffer.scala 407:92] + wire _T_2167 = _T_4476 | _T_2166; // @[lsu_bus_buffer.scala 406:86] + wire _T_2173 = _T_2146 & _T_1867; // @[lsu_bus_buffer.scala 408:73] + wire _T_2174 = _T_2167 | _T_2173; // @[lsu_bus_buffer.scala 407:114] + wire _T_2175 = _T_2129 & _T_2174; // @[lsu_bus_buffer.scala 405:113] + wire _T_2177 = _T_2175 | buf_age_0[1]; // @[lsu_bus_buffer.scala 408:97] + wire _T_2191 = _T_2139 & _T_1876; // @[lsu_bus_buffer.scala 407:92] + wire _T_2192 = _T_4481 | _T_2191; // @[lsu_bus_buffer.scala 406:86] + wire _T_2198 = _T_2146 & _T_1878; // @[lsu_bus_buffer.scala 408:73] + wire _T_2199 = _T_2192 | _T_2198; // @[lsu_bus_buffer.scala 407:114] + wire _T_2200 = _T_2129 & _T_2199; // @[lsu_bus_buffer.scala 405:113] + wire _T_2202 = _T_2200 | buf_age_0[2]; // @[lsu_bus_buffer.scala 408:97] + wire _T_2216 = _T_2139 & _T_1887; // @[lsu_bus_buffer.scala 407:92] + wire _T_2217 = _T_4486 | _T_2216; // @[lsu_bus_buffer.scala 406:86] + wire _T_2223 = _T_2146 & _T_1889; // @[lsu_bus_buffer.scala 408:73] + wire _T_2224 = _T_2217 | _T_2223; // @[lsu_bus_buffer.scala 407:114] + wire _T_2225 = _T_2129 & _T_2224; // @[lsu_bus_buffer.scala 405:113] + wire _T_2227 = _T_2225 | buf_age_0[3]; // @[lsu_bus_buffer.scala 408:97] + wire [2:0] _T_2229 = {_T_2227,_T_2202,_T_2177}; // @[Cat.scala 29:58] + wire _T_3728 = 2'h1 == WrPtr0_r; // @[lsu_bus_buffer.scala 443:117] + wire _T_3729 = _T_3534 & _T_3728; // @[lsu_bus_buffer.scala 443:112] + wire _T_3731 = 2'h1 == WrPtr1_r; // @[lsu_bus_buffer.scala 443:166] + wire _T_3732 = _T_3537 & _T_3731; // @[lsu_bus_buffer.scala 443:161] + wire _T_3733 = _T_3729 | _T_3732; // @[lsu_bus_buffer.scala 443:132] + wire _T_3734 = _T_853 & _T_3733; // @[lsu_bus_buffer.scala 443:63] + wire _T_3735 = 2'h1 == ibuf_tag; // @[lsu_bus_buffer.scala 443:206] + wire _T_3736 = ibuf_drain_vld & _T_3735; // @[lsu_bus_buffer.scala 443:201] + wire _T_3737 = _T_3734 | _T_3736; // @[lsu_bus_buffer.scala 443:183] + wire _T_3782 = 3'h3 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_3827 = io_lsu_axi_b_bits_id == 3'h1; // @[lsu_bus_buffer.scala 468:73] + wire _T_3828 = bus_rsp_write & _T_3827; // @[lsu_bus_buffer.scala 468:52] + wire _T_3829 = io_lsu_axi_r_bits_id == 3'h1; // @[lsu_bus_buffer.scala 469:46] + wire [2:0] _GEN_372 = {{1'd0}, buf_ldfwdtag_1}; // @[lsu_bus_buffer.scala 470:47] + wire _T_3831 = io_lsu_axi_r_bits_id == _GEN_372; // @[lsu_bus_buffer.scala 470:47] + wire _T_3832 = buf_ldfwd[1] & _T_3831; // @[lsu_bus_buffer.scala 470:27] + wire _T_3833 = _T_3829 | _T_3832; // @[lsu_bus_buffer.scala 469:77] + wire _T_3834 = buf_dual_1 & buf_dualhi_1; // @[lsu_bus_buffer.scala 471:26] + wire _T_3836 = ~buf_write[1]; // @[lsu_bus_buffer.scala 471:44] + wire _T_3837 = _T_3834 & _T_3836; // @[lsu_bus_buffer.scala 471:42] + wire _T_3838 = _T_3837 & buf_samedw_1; // @[lsu_bus_buffer.scala 471:58] + reg [1:0] buf_dualtag_1; // @[Reg.scala 27:20] + wire [2:0] _GEN_373 = {{1'd0}, buf_dualtag_1}; // @[lsu_bus_buffer.scala 471:94] + wire _T_3839 = io_lsu_axi_r_bits_id == _GEN_373; // @[lsu_bus_buffer.scala 471:94] + wire _T_3840 = _T_3838 & _T_3839; // @[lsu_bus_buffer.scala 471:74] + wire _T_3841 = _T_3833 | _T_3840; // @[lsu_bus_buffer.scala 470:71] + wire _T_3842 = bus_rsp_read & _T_3841; // @[lsu_bus_buffer.scala 469:25] + wire _T_3843 = _T_3828 | _T_3842; // @[lsu_bus_buffer.scala 468:105] + wire _GEN_118 = _T_3782 & _T_3843; // @[Conditional.scala 39:67] + wire _GEN_137 = _T_3748 ? 1'h0 : _GEN_118; // @[Conditional.scala 39:67] + wire _GEN_149 = _T_3744 ? 1'h0 : _GEN_137; // @[Conditional.scala 39:67] + wire buf_resp_state_bus_en_1 = _T_3721 ? 1'h0 : _GEN_149; // @[Conditional.scala 40:58] + wire _T_3869 = 3'h4 == buf_state_1; // @[Conditional.scala 37:30] + wire [3:0] _T_3879 = buf_ldfwd >> buf_dualtag_1; // @[lsu_bus_buffer.scala 483:21] + wire [1:0] _GEN_99 = 2'h1 == buf_dualtag_1 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[lsu_bus_buffer.scala 483:58] + wire [1:0] _GEN_100 = 2'h2 == buf_dualtag_1 ? buf_ldfwdtag_2 : _GEN_99; // @[lsu_bus_buffer.scala 483:58] + wire [1:0] _GEN_101 = 2'h3 == buf_dualtag_1 ? buf_ldfwdtag_3 : _GEN_100; // @[lsu_bus_buffer.scala 483:58] + wire [2:0] _GEN_375 = {{1'd0}, _GEN_101}; // @[lsu_bus_buffer.scala 483:58] + wire _T_3881 = io_lsu_axi_r_bits_id == _GEN_375; // @[lsu_bus_buffer.scala 483:58] + wire _T_3882 = _T_3879[0] & _T_3881; // @[lsu_bus_buffer.scala 483:38] + wire _T_3883 = _T_3839 | _T_3882; // @[lsu_bus_buffer.scala 482:95] + wire _T_3884 = bus_rsp_read & _T_3883; // @[lsu_bus_buffer.scala 482:45] + wire _GEN_112 = _T_3869 & _T_3884; // @[Conditional.scala 39:67] + wire _GEN_119 = _T_3782 ? buf_resp_state_bus_en_1 : _GEN_112; // @[Conditional.scala 39:67] + wire _GEN_129 = _T_3748 ? buf_cmd_state_bus_en_1 : _GEN_119; // @[Conditional.scala 39:67] + wire _GEN_142 = _T_3744 ? 1'h0 : _GEN_129; // @[Conditional.scala 39:67] + wire buf_state_bus_en_1 = _T_3721 ? 1'h0 : _GEN_142; // @[Conditional.scala 40:58] + wire _T_3761 = buf_state_bus_en_1 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 456:49] + wire _T_3762 = _T_3761 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 456:70] + wire _T_3887 = 3'h5 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_3890 = RspPtr == 2'h1; // @[lsu_bus_buffer.scala 488:37] + wire _T_3891 = buf_dualtag_1 == RspPtr; // @[lsu_bus_buffer.scala 488:98] + wire _T_3892 = buf_dual_1 & _T_3891; // @[lsu_bus_buffer.scala 488:80] + wire _T_3893 = _T_3890 | _T_3892; // @[lsu_bus_buffer.scala 488:65] + wire _T_3894 = _T_3893 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 488:112] + wire _T_3895 = 3'h6 == buf_state_1; // @[Conditional.scala 37:30] + wire _GEN_107 = _T_3887 ? _T_3894 : _T_3895; // @[Conditional.scala 39:67] + wire _GEN_113 = _T_3869 ? _T_3762 : _GEN_107; // @[Conditional.scala 39:67] + wire _GEN_120 = _T_3782 ? _T_3762 : _GEN_113; // @[Conditional.scala 39:67] + wire _GEN_130 = _T_3748 ? _T_3762 : _GEN_120; // @[Conditional.scala 39:67] + wire _GEN_140 = _T_3744 ? _T_3554 : _GEN_130; // @[Conditional.scala 39:67] + wire buf_state_en_1 = _T_3721 ? _T_3737 : _GEN_140; // @[Conditional.scala 40:58] + wire _T_2231 = _T_1864 & buf_state_en_1; // @[lsu_bus_buffer.scala 405:94] + wire _T_2241 = _T_2137 & _T_1867; // @[lsu_bus_buffer.scala 407:71] + wire _T_2243 = _T_2241 & _T_1854; // @[lsu_bus_buffer.scala 407:92] + wire _T_2244 = _T_4471 | _T_2243; // @[lsu_bus_buffer.scala 406:86] + wire _T_2248 = _T_2144 & _T_1868; // @[lsu_bus_buffer.scala 408:52] + wire _T_2250 = _T_2248 & _T_1856; // @[lsu_bus_buffer.scala 408:73] + wire _T_2251 = _T_2244 | _T_2250; // @[lsu_bus_buffer.scala 407:114] + wire _T_2252 = _T_2231 & _T_2251; // @[lsu_bus_buffer.scala 405:113] + wire _T_2254 = _T_2252 | buf_age_1[0]; // @[lsu_bus_buffer.scala 408:97] + wire _T_2268 = _T_2241 & _T_1865; // @[lsu_bus_buffer.scala 407:92] + wire _T_2269 = _T_4476 | _T_2268; // @[lsu_bus_buffer.scala 406:86] + wire _T_2275 = _T_2248 & _T_1867; // @[lsu_bus_buffer.scala 408:73] + wire _T_2276 = _T_2269 | _T_2275; // @[lsu_bus_buffer.scala 407:114] + wire _T_2277 = _T_2231 & _T_2276; // @[lsu_bus_buffer.scala 405:113] + wire _T_2279 = _T_2277 | buf_age_1[1]; // @[lsu_bus_buffer.scala 408:97] + wire _T_2293 = _T_2241 & _T_1876; // @[lsu_bus_buffer.scala 407:92] + wire _T_2294 = _T_4481 | _T_2293; // @[lsu_bus_buffer.scala 406:86] + wire _T_2300 = _T_2248 & _T_1878; // @[lsu_bus_buffer.scala 408:73] + wire _T_2301 = _T_2294 | _T_2300; // @[lsu_bus_buffer.scala 407:114] + wire _T_2302 = _T_2231 & _T_2301; // @[lsu_bus_buffer.scala 405:113] + wire _T_2304 = _T_2302 | buf_age_1[2]; // @[lsu_bus_buffer.scala 408:97] + wire _T_2318 = _T_2241 & _T_1887; // @[lsu_bus_buffer.scala 407:92] + wire _T_2319 = _T_4486 | _T_2318; // @[lsu_bus_buffer.scala 406:86] + wire _T_2325 = _T_2248 & _T_1889; // @[lsu_bus_buffer.scala 408:73] + wire _T_2326 = _T_2319 | _T_2325; // @[lsu_bus_buffer.scala 407:114] + wire _T_2327 = _T_2231 & _T_2326; // @[lsu_bus_buffer.scala 405:113] + wire _T_2329 = _T_2327 | buf_age_1[3]; // @[lsu_bus_buffer.scala 408:97] + wire [2:0] _T_2331 = {_T_2329,_T_2304,_T_2279}; // @[Cat.scala 29:58] + wire _T_3921 = 2'h2 == WrPtr0_r; // @[lsu_bus_buffer.scala 443:117] + wire _T_3922 = _T_3534 & _T_3921; // @[lsu_bus_buffer.scala 443:112] + wire _T_3924 = 2'h2 == WrPtr1_r; // @[lsu_bus_buffer.scala 443:166] + wire _T_3925 = _T_3537 & _T_3924; // @[lsu_bus_buffer.scala 443:161] + wire _T_3926 = _T_3922 | _T_3925; // @[lsu_bus_buffer.scala 443:132] + wire _T_3927 = _T_853 & _T_3926; // @[lsu_bus_buffer.scala 443:63] + wire _T_3928 = 2'h2 == ibuf_tag; // @[lsu_bus_buffer.scala 443:206] + wire _T_3929 = ibuf_drain_vld & _T_3928; // @[lsu_bus_buffer.scala 443:201] + wire _T_3930 = _T_3927 | _T_3929; // @[lsu_bus_buffer.scala 443:183] + wire _T_3975 = 3'h3 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_4020 = io_lsu_axi_b_bits_id == 3'h2; // @[lsu_bus_buffer.scala 468:73] + wire _T_4021 = bus_rsp_write & _T_4020; // @[lsu_bus_buffer.scala 468:52] + wire _T_4022 = io_lsu_axi_r_bits_id == 3'h2; // @[lsu_bus_buffer.scala 469:46] + wire [2:0] _GEN_376 = {{1'd0}, buf_ldfwdtag_2}; // @[lsu_bus_buffer.scala 470:47] + wire _T_4024 = io_lsu_axi_r_bits_id == _GEN_376; // @[lsu_bus_buffer.scala 470:47] + wire _T_4025 = buf_ldfwd[2] & _T_4024; // @[lsu_bus_buffer.scala 470:27] + wire _T_4026 = _T_4022 | _T_4025; // @[lsu_bus_buffer.scala 469:77] + wire _T_4027 = buf_dual_2 & buf_dualhi_2; // @[lsu_bus_buffer.scala 471:26] + wire _T_4029 = ~buf_write[2]; // @[lsu_bus_buffer.scala 471:44] + wire _T_4030 = _T_4027 & _T_4029; // @[lsu_bus_buffer.scala 471:42] + wire _T_4031 = _T_4030 & buf_samedw_2; // @[lsu_bus_buffer.scala 471:58] + reg [1:0] buf_dualtag_2; // @[Reg.scala 27:20] + wire [2:0] _GEN_377 = {{1'd0}, buf_dualtag_2}; // @[lsu_bus_buffer.scala 471:94] + wire _T_4032 = io_lsu_axi_r_bits_id == _GEN_377; // @[lsu_bus_buffer.scala 471:94] + wire _T_4033 = _T_4031 & _T_4032; // @[lsu_bus_buffer.scala 471:74] + wire _T_4034 = _T_4026 | _T_4033; // @[lsu_bus_buffer.scala 470:71] + wire _T_4035 = bus_rsp_read & _T_4034; // @[lsu_bus_buffer.scala 469:25] + wire _T_4036 = _T_4021 | _T_4035; // @[lsu_bus_buffer.scala 468:105] + wire _GEN_194 = _T_3975 & _T_4036; // @[Conditional.scala 39:67] + wire _GEN_213 = _T_3941 ? 1'h0 : _GEN_194; // @[Conditional.scala 39:67] + wire _GEN_225 = _T_3937 ? 1'h0 : _GEN_213; // @[Conditional.scala 39:67] + wire buf_resp_state_bus_en_2 = _T_3914 ? 1'h0 : _GEN_225; // @[Conditional.scala 40:58] + wire _T_4062 = 3'h4 == buf_state_2; // @[Conditional.scala 37:30] + wire [3:0] _T_4072 = buf_ldfwd >> buf_dualtag_2; // @[lsu_bus_buffer.scala 483:21] + wire [1:0] _GEN_175 = 2'h1 == buf_dualtag_2 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[lsu_bus_buffer.scala 483:58] + wire [1:0] _GEN_176 = 2'h2 == buf_dualtag_2 ? buf_ldfwdtag_2 : _GEN_175; // @[lsu_bus_buffer.scala 483:58] + wire [1:0] _GEN_177 = 2'h3 == buf_dualtag_2 ? buf_ldfwdtag_3 : _GEN_176; // @[lsu_bus_buffer.scala 483:58] + wire [2:0] _GEN_379 = {{1'd0}, _GEN_177}; // @[lsu_bus_buffer.scala 483:58] + wire _T_4074 = io_lsu_axi_r_bits_id == _GEN_379; // @[lsu_bus_buffer.scala 483:58] + wire _T_4075 = _T_4072[0] & _T_4074; // @[lsu_bus_buffer.scala 483:38] + wire _T_4076 = _T_4032 | _T_4075; // @[lsu_bus_buffer.scala 482:95] + wire _T_4077 = bus_rsp_read & _T_4076; // @[lsu_bus_buffer.scala 482:45] + wire _GEN_188 = _T_4062 & _T_4077; // @[Conditional.scala 39:67] + wire _GEN_195 = _T_3975 ? buf_resp_state_bus_en_2 : _GEN_188; // @[Conditional.scala 39:67] + wire _GEN_205 = _T_3941 ? buf_cmd_state_bus_en_2 : _GEN_195; // @[Conditional.scala 39:67] + wire _GEN_218 = _T_3937 ? 1'h0 : _GEN_205; // @[Conditional.scala 39:67] + wire buf_state_bus_en_2 = _T_3914 ? 1'h0 : _GEN_218; // @[Conditional.scala 40:58] + wire _T_3954 = buf_state_bus_en_2 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 456:49] + wire _T_3955 = _T_3954 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 456:70] + wire _T_4080 = 3'h5 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_4083 = RspPtr == 2'h2; // @[lsu_bus_buffer.scala 488:37] + wire _T_4084 = buf_dualtag_2 == RspPtr; // @[lsu_bus_buffer.scala 488:98] + wire _T_4085 = buf_dual_2 & _T_4084; // @[lsu_bus_buffer.scala 488:80] + wire _T_4086 = _T_4083 | _T_4085; // @[lsu_bus_buffer.scala 488:65] + wire _T_4087 = _T_4086 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 488:112] + wire _T_4088 = 3'h6 == buf_state_2; // @[Conditional.scala 37:30] + wire _GEN_183 = _T_4080 ? _T_4087 : _T_4088; // @[Conditional.scala 39:67] + wire _GEN_189 = _T_4062 ? _T_3955 : _GEN_183; // @[Conditional.scala 39:67] + wire _GEN_196 = _T_3975 ? _T_3955 : _GEN_189; // @[Conditional.scala 39:67] + wire _GEN_206 = _T_3941 ? _T_3955 : _GEN_196; // @[Conditional.scala 39:67] + wire _GEN_216 = _T_3937 ? _T_3554 : _GEN_206; // @[Conditional.scala 39:67] + wire buf_state_en_2 = _T_3914 ? _T_3930 : _GEN_216; // @[Conditional.scala 40:58] + wire _T_2333 = _T_1875 & buf_state_en_2; // @[lsu_bus_buffer.scala 405:94] + wire _T_2343 = _T_2137 & _T_1878; // @[lsu_bus_buffer.scala 407:71] + wire _T_2345 = _T_2343 & _T_1854; // @[lsu_bus_buffer.scala 407:92] + wire _T_2346 = _T_4471 | _T_2345; // @[lsu_bus_buffer.scala 406:86] + wire _T_2350 = _T_2144 & _T_1879; // @[lsu_bus_buffer.scala 408:52] + wire _T_2352 = _T_2350 & _T_1856; // @[lsu_bus_buffer.scala 408:73] + wire _T_2353 = _T_2346 | _T_2352; // @[lsu_bus_buffer.scala 407:114] + wire _T_2354 = _T_2333 & _T_2353; // @[lsu_bus_buffer.scala 405:113] + wire _T_2356 = _T_2354 | buf_age_2[0]; // @[lsu_bus_buffer.scala 408:97] + wire _T_2370 = _T_2343 & _T_1865; // @[lsu_bus_buffer.scala 407:92] + wire _T_2371 = _T_4476 | _T_2370; // @[lsu_bus_buffer.scala 406:86] + wire _T_2377 = _T_2350 & _T_1867; // @[lsu_bus_buffer.scala 408:73] + wire _T_2378 = _T_2371 | _T_2377; // @[lsu_bus_buffer.scala 407:114] + wire _T_2379 = _T_2333 & _T_2378; // @[lsu_bus_buffer.scala 405:113] + wire _T_2381 = _T_2379 | buf_age_2[1]; // @[lsu_bus_buffer.scala 408:97] + wire _T_2395 = _T_2343 & _T_1876; // @[lsu_bus_buffer.scala 407:92] + wire _T_2396 = _T_4481 | _T_2395; // @[lsu_bus_buffer.scala 406:86] + wire _T_2402 = _T_2350 & _T_1878; // @[lsu_bus_buffer.scala 408:73] + wire _T_2403 = _T_2396 | _T_2402; // @[lsu_bus_buffer.scala 407:114] + wire _T_2404 = _T_2333 & _T_2403; // @[lsu_bus_buffer.scala 405:113] + wire _T_2406 = _T_2404 | buf_age_2[2]; // @[lsu_bus_buffer.scala 408:97] + wire _T_2420 = _T_2343 & _T_1887; // @[lsu_bus_buffer.scala 407:92] + wire _T_2421 = _T_4486 | _T_2420; // @[lsu_bus_buffer.scala 406:86] + wire _T_2427 = _T_2350 & _T_1889; // @[lsu_bus_buffer.scala 408:73] + wire _T_2428 = _T_2421 | _T_2427; // @[lsu_bus_buffer.scala 407:114] + wire _T_2429 = _T_2333 & _T_2428; // @[lsu_bus_buffer.scala 405:113] + wire _T_2431 = _T_2429 | buf_age_2[3]; // @[lsu_bus_buffer.scala 408:97] + wire [2:0] _T_2433 = {_T_2431,_T_2406,_T_2381}; // @[Cat.scala 29:58] + wire _T_4114 = 2'h3 == WrPtr0_r; // @[lsu_bus_buffer.scala 443:117] + wire _T_4115 = _T_3534 & _T_4114; // @[lsu_bus_buffer.scala 443:112] + wire _T_4117 = 2'h3 == WrPtr1_r; // @[lsu_bus_buffer.scala 443:166] + wire _T_4118 = _T_3537 & _T_4117; // @[lsu_bus_buffer.scala 443:161] + wire _T_4119 = _T_4115 | _T_4118; // @[lsu_bus_buffer.scala 443:132] + wire _T_4120 = _T_853 & _T_4119; // @[lsu_bus_buffer.scala 443:63] + wire _T_4121 = 2'h3 == ibuf_tag; // @[lsu_bus_buffer.scala 443:206] + wire _T_4122 = ibuf_drain_vld & _T_4121; // @[lsu_bus_buffer.scala 443:201] + wire _T_4123 = _T_4120 | _T_4122; // @[lsu_bus_buffer.scala 443:183] + wire _T_4168 = 3'h3 == buf_state_3; // @[Conditional.scala 37:30] + wire _T_4213 = io_lsu_axi_b_bits_id == 3'h3; // @[lsu_bus_buffer.scala 468:73] + wire _T_4214 = bus_rsp_write & _T_4213; // @[lsu_bus_buffer.scala 468:52] + wire _T_4215 = io_lsu_axi_r_bits_id == 3'h3; // @[lsu_bus_buffer.scala 469:46] + wire [2:0] _GEN_380 = {{1'd0}, buf_ldfwdtag_3}; // @[lsu_bus_buffer.scala 470:47] + wire _T_4217 = io_lsu_axi_r_bits_id == _GEN_380; // @[lsu_bus_buffer.scala 470:47] + wire _T_4218 = buf_ldfwd[3] & _T_4217; // @[lsu_bus_buffer.scala 470:27] + wire _T_4219 = _T_4215 | _T_4218; // @[lsu_bus_buffer.scala 469:77] + wire _T_4220 = buf_dual_3 & buf_dualhi_3; // @[lsu_bus_buffer.scala 471:26] + wire _T_4222 = ~buf_write[3]; // @[lsu_bus_buffer.scala 471:44] + wire _T_4223 = _T_4220 & _T_4222; // @[lsu_bus_buffer.scala 471:42] + wire _T_4224 = _T_4223 & buf_samedw_3; // @[lsu_bus_buffer.scala 471:58] + reg [1:0] buf_dualtag_3; // @[Reg.scala 27:20] + wire [2:0] _GEN_381 = {{1'd0}, buf_dualtag_3}; // @[lsu_bus_buffer.scala 471:94] + wire _T_4225 = io_lsu_axi_r_bits_id == _GEN_381; // @[lsu_bus_buffer.scala 471:94] + wire _T_4226 = _T_4224 & _T_4225; // @[lsu_bus_buffer.scala 471:74] + wire _T_4227 = _T_4219 | _T_4226; // @[lsu_bus_buffer.scala 470:71] + wire _T_4228 = bus_rsp_read & _T_4227; // @[lsu_bus_buffer.scala 469:25] + wire _T_4229 = _T_4214 | _T_4228; // @[lsu_bus_buffer.scala 468:105] + wire _GEN_270 = _T_4168 & _T_4229; // @[Conditional.scala 39:67] + wire _GEN_289 = _T_4134 ? 1'h0 : _GEN_270; // @[Conditional.scala 39:67] + wire _GEN_301 = _T_4130 ? 1'h0 : _GEN_289; // @[Conditional.scala 39:67] + wire buf_resp_state_bus_en_3 = _T_4107 ? 1'h0 : _GEN_301; // @[Conditional.scala 40:58] + wire _T_4255 = 3'h4 == buf_state_3; // @[Conditional.scala 37:30] + wire [3:0] _T_4265 = buf_ldfwd >> buf_dualtag_3; // @[lsu_bus_buffer.scala 483:21] + wire [1:0] _GEN_251 = 2'h1 == buf_dualtag_3 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[lsu_bus_buffer.scala 483:58] + wire [1:0] _GEN_252 = 2'h2 == buf_dualtag_3 ? buf_ldfwdtag_2 : _GEN_251; // @[lsu_bus_buffer.scala 483:58] + wire [1:0] _GEN_253 = 2'h3 == buf_dualtag_3 ? buf_ldfwdtag_3 : _GEN_252; // @[lsu_bus_buffer.scala 483:58] + wire [2:0] _GEN_383 = {{1'd0}, _GEN_253}; // @[lsu_bus_buffer.scala 483:58] + wire _T_4267 = io_lsu_axi_r_bits_id == _GEN_383; // @[lsu_bus_buffer.scala 483:58] + wire _T_4268 = _T_4265[0] & _T_4267; // @[lsu_bus_buffer.scala 483:38] + wire _T_4269 = _T_4225 | _T_4268; // @[lsu_bus_buffer.scala 482:95] + wire _T_4270 = bus_rsp_read & _T_4269; // @[lsu_bus_buffer.scala 482:45] + wire _GEN_264 = _T_4255 & _T_4270; // @[Conditional.scala 39:67] + wire _GEN_271 = _T_4168 ? buf_resp_state_bus_en_3 : _GEN_264; // @[Conditional.scala 39:67] + wire _GEN_281 = _T_4134 ? buf_cmd_state_bus_en_3 : _GEN_271; // @[Conditional.scala 39:67] + wire _GEN_294 = _T_4130 ? 1'h0 : _GEN_281; // @[Conditional.scala 39:67] + wire buf_state_bus_en_3 = _T_4107 ? 1'h0 : _GEN_294; // @[Conditional.scala 40:58] + wire _T_4147 = buf_state_bus_en_3 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 456:49] + wire _T_4148 = _T_4147 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 456:70] + wire _T_4273 = 3'h5 == buf_state_3; // @[Conditional.scala 37:30] + wire _T_4276 = RspPtr == 2'h3; // @[lsu_bus_buffer.scala 488:37] + wire _T_4277 = buf_dualtag_3 == RspPtr; // @[lsu_bus_buffer.scala 488:98] + wire _T_4278 = buf_dual_3 & _T_4277; // @[lsu_bus_buffer.scala 488:80] + wire _T_4279 = _T_4276 | _T_4278; // @[lsu_bus_buffer.scala 488:65] + wire _T_4280 = _T_4279 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 488:112] + wire _T_4281 = 3'h6 == buf_state_3; // @[Conditional.scala 37:30] + wire _GEN_259 = _T_4273 ? _T_4280 : _T_4281; // @[Conditional.scala 39:67] + wire _GEN_265 = _T_4255 ? _T_4148 : _GEN_259; // @[Conditional.scala 39:67] + wire _GEN_272 = _T_4168 ? _T_4148 : _GEN_265; // @[Conditional.scala 39:67] + wire _GEN_282 = _T_4134 ? _T_4148 : _GEN_272; // @[Conditional.scala 39:67] + wire _GEN_292 = _T_4130 ? _T_3554 : _GEN_282; // @[Conditional.scala 39:67] + wire buf_state_en_3 = _T_4107 ? _T_4123 : _GEN_292; // @[Conditional.scala 40:58] + wire _T_2435 = _T_1886 & buf_state_en_3; // @[lsu_bus_buffer.scala 405:94] + wire _T_2445 = _T_2137 & _T_1889; // @[lsu_bus_buffer.scala 407:71] + wire _T_2447 = _T_2445 & _T_1854; // @[lsu_bus_buffer.scala 407:92] + wire _T_2448 = _T_4471 | _T_2447; // @[lsu_bus_buffer.scala 406:86] + wire _T_2452 = _T_2144 & _T_1890; // @[lsu_bus_buffer.scala 408:52] + wire _T_2454 = _T_2452 & _T_1856; // @[lsu_bus_buffer.scala 408:73] + wire _T_2455 = _T_2448 | _T_2454; // @[lsu_bus_buffer.scala 407:114] + wire _T_2456 = _T_2435 & _T_2455; // @[lsu_bus_buffer.scala 405:113] + wire _T_2458 = _T_2456 | buf_age_3[0]; // @[lsu_bus_buffer.scala 408:97] + wire _T_2472 = _T_2445 & _T_1865; // @[lsu_bus_buffer.scala 407:92] + wire _T_2473 = _T_4476 | _T_2472; // @[lsu_bus_buffer.scala 406:86] + wire _T_2479 = _T_2452 & _T_1867; // @[lsu_bus_buffer.scala 408:73] + wire _T_2480 = _T_2473 | _T_2479; // @[lsu_bus_buffer.scala 407:114] + wire _T_2481 = _T_2435 & _T_2480; // @[lsu_bus_buffer.scala 405:113] + wire _T_2483 = _T_2481 | buf_age_3[1]; // @[lsu_bus_buffer.scala 408:97] + wire _T_2497 = _T_2445 & _T_1876; // @[lsu_bus_buffer.scala 407:92] + wire _T_2498 = _T_4481 | _T_2497; // @[lsu_bus_buffer.scala 406:86] + wire _T_2504 = _T_2452 & _T_1878; // @[lsu_bus_buffer.scala 408:73] + wire _T_2505 = _T_2498 | _T_2504; // @[lsu_bus_buffer.scala 407:114] + wire _T_2506 = _T_2435 & _T_2505; // @[lsu_bus_buffer.scala 405:113] + wire _T_2508 = _T_2506 | buf_age_3[2]; // @[lsu_bus_buffer.scala 408:97] + wire _T_2522 = _T_2445 & _T_1887; // @[lsu_bus_buffer.scala 407:92] + wire _T_2523 = _T_4486 | _T_2522; // @[lsu_bus_buffer.scala 406:86] + wire _T_2529 = _T_2452 & _T_1889; // @[lsu_bus_buffer.scala 408:73] + wire _T_2530 = _T_2523 | _T_2529; // @[lsu_bus_buffer.scala 407:114] + wire _T_2531 = _T_2435 & _T_2530; // @[lsu_bus_buffer.scala 405:113] + wire _T_2533 = _T_2531 | buf_age_3[3]; // @[lsu_bus_buffer.scala 408:97] + wire [2:0] _T_2535 = {_T_2533,_T_2508,_T_2483}; // @[Cat.scala 29:58] + wire _T_2799 = buf_state_0 == 3'h6; // @[lsu_bus_buffer.scala 416:47] + wire _T_2800 = _T_1853 | _T_2799; // @[lsu_bus_buffer.scala 416:32] + wire _T_2801 = ~_T_2800; // @[lsu_bus_buffer.scala 416:6] + wire _T_2809 = _T_2801 | _T_2141; // @[lsu_bus_buffer.scala 416:59] + wire _T_2816 = _T_2809 | _T_2148; // @[lsu_bus_buffer.scala 417:110] + wire _T_2817 = _T_2129 & _T_2816; // @[lsu_bus_buffer.scala 415:112] + wire _T_2821 = buf_state_1 == 3'h6; // @[lsu_bus_buffer.scala 416:47] + wire _T_2822 = _T_1864 | _T_2821; // @[lsu_bus_buffer.scala 416:32] + wire _T_2823 = ~_T_2822; // @[lsu_bus_buffer.scala 416:6] + wire _T_2831 = _T_2823 | _T_2166; // @[lsu_bus_buffer.scala 416:59] + wire _T_2838 = _T_2831 | _T_2173; // @[lsu_bus_buffer.scala 417:110] + wire _T_2839 = _T_2129 & _T_2838; // @[lsu_bus_buffer.scala 415:112] + wire _T_2843 = buf_state_2 == 3'h6; // @[lsu_bus_buffer.scala 416:47] + wire _T_2844 = _T_1875 | _T_2843; // @[lsu_bus_buffer.scala 416:32] + wire _T_2845 = ~_T_2844; // @[lsu_bus_buffer.scala 416:6] + wire _T_2853 = _T_2845 | _T_2191; // @[lsu_bus_buffer.scala 416:59] + wire _T_2860 = _T_2853 | _T_2198; // @[lsu_bus_buffer.scala 417:110] + wire _T_2861 = _T_2129 & _T_2860; // @[lsu_bus_buffer.scala 415:112] + wire _T_2865 = buf_state_3 == 3'h6; // @[lsu_bus_buffer.scala 416:47] + wire _T_2866 = _T_1886 | _T_2865; // @[lsu_bus_buffer.scala 416:32] + wire _T_2867 = ~_T_2866; // @[lsu_bus_buffer.scala 416:6] + wire _T_2875 = _T_2867 | _T_2216; // @[lsu_bus_buffer.scala 416:59] + wire _T_2882 = _T_2875 | _T_2223; // @[lsu_bus_buffer.scala 417:110] + wire _T_2883 = _T_2129 & _T_2882; // @[lsu_bus_buffer.scala 415:112] + wire [3:0] buf_rspage_set_0 = {_T_2883,_T_2861,_T_2839,_T_2817}; // @[Cat.scala 29:58] + wire _T_2900 = _T_2801 | _T_2243; // @[lsu_bus_buffer.scala 416:59] + wire _T_2907 = _T_2900 | _T_2250; // @[lsu_bus_buffer.scala 417:110] + wire _T_2908 = _T_2231 & _T_2907; // @[lsu_bus_buffer.scala 415:112] + wire _T_2922 = _T_2823 | _T_2268; // @[lsu_bus_buffer.scala 416:59] + wire _T_2929 = _T_2922 | _T_2275; // @[lsu_bus_buffer.scala 417:110] + wire _T_2930 = _T_2231 & _T_2929; // @[lsu_bus_buffer.scala 415:112] + wire _T_2944 = _T_2845 | _T_2293; // @[lsu_bus_buffer.scala 416:59] + wire _T_2951 = _T_2944 | _T_2300; // @[lsu_bus_buffer.scala 417:110] + wire _T_2952 = _T_2231 & _T_2951; // @[lsu_bus_buffer.scala 415:112] + wire _T_2966 = _T_2867 | _T_2318; // @[lsu_bus_buffer.scala 416:59] + wire _T_2973 = _T_2966 | _T_2325; // @[lsu_bus_buffer.scala 417:110] + wire _T_2974 = _T_2231 & _T_2973; // @[lsu_bus_buffer.scala 415:112] + wire [3:0] buf_rspage_set_1 = {_T_2974,_T_2952,_T_2930,_T_2908}; // @[Cat.scala 29:58] + wire _T_2991 = _T_2801 | _T_2345; // @[lsu_bus_buffer.scala 416:59] + wire _T_2998 = _T_2991 | _T_2352; // @[lsu_bus_buffer.scala 417:110] + wire _T_2999 = _T_2333 & _T_2998; // @[lsu_bus_buffer.scala 415:112] + wire _T_3013 = _T_2823 | _T_2370; // @[lsu_bus_buffer.scala 416:59] + wire _T_3020 = _T_3013 | _T_2377; // @[lsu_bus_buffer.scala 417:110] + wire _T_3021 = _T_2333 & _T_3020; // @[lsu_bus_buffer.scala 415:112] + wire _T_3035 = _T_2845 | _T_2395; // @[lsu_bus_buffer.scala 416:59] + wire _T_3042 = _T_3035 | _T_2402; // @[lsu_bus_buffer.scala 417:110] + wire _T_3043 = _T_2333 & _T_3042; // @[lsu_bus_buffer.scala 415:112] + wire _T_3057 = _T_2867 | _T_2420; // @[lsu_bus_buffer.scala 416:59] + wire _T_3064 = _T_3057 | _T_2427; // @[lsu_bus_buffer.scala 417:110] + wire _T_3065 = _T_2333 & _T_3064; // @[lsu_bus_buffer.scala 415:112] + wire [3:0] buf_rspage_set_2 = {_T_3065,_T_3043,_T_3021,_T_2999}; // @[Cat.scala 29:58] + wire _T_3082 = _T_2801 | _T_2447; // @[lsu_bus_buffer.scala 416:59] + wire _T_3089 = _T_3082 | _T_2454; // @[lsu_bus_buffer.scala 417:110] + wire _T_3090 = _T_2435 & _T_3089; // @[lsu_bus_buffer.scala 415:112] + wire _T_3104 = _T_2823 | _T_2472; // @[lsu_bus_buffer.scala 416:59] + wire _T_3111 = _T_3104 | _T_2479; // @[lsu_bus_buffer.scala 417:110] + wire _T_3112 = _T_2435 & _T_3111; // @[lsu_bus_buffer.scala 415:112] + wire _T_3126 = _T_2845 | _T_2497; // @[lsu_bus_buffer.scala 416:59] + wire _T_3133 = _T_3126 | _T_2504; // @[lsu_bus_buffer.scala 417:110] + wire _T_3134 = _T_2435 & _T_3133; // @[lsu_bus_buffer.scala 415:112] + wire _T_3148 = _T_2867 | _T_2522; // @[lsu_bus_buffer.scala 416:59] + wire _T_3155 = _T_3148 | _T_2529; // @[lsu_bus_buffer.scala 417:110] + wire _T_3156 = _T_2435 & _T_3155; // @[lsu_bus_buffer.scala 415:112] + wire [3:0] buf_rspage_set_3 = {_T_3156,_T_3134,_T_3112,_T_3090}; // @[Cat.scala 29:58] + wire _T_3241 = _T_2865 | _T_1886; // @[lsu_bus_buffer.scala 420:110] + wire _T_3242 = ~_T_3241; // @[lsu_bus_buffer.scala 420:84] + wire _T_3243 = buf_rspageQ_0[3] & _T_3242; // @[lsu_bus_buffer.scala 420:82] + wire _T_3235 = _T_2843 | _T_1875; // @[lsu_bus_buffer.scala 420:110] + wire _T_3236 = ~_T_3235; // @[lsu_bus_buffer.scala 420:84] + wire _T_3237 = buf_rspageQ_0[2] & _T_3236; // @[lsu_bus_buffer.scala 420:82] + wire _T_3229 = _T_2821 | _T_1864; // @[lsu_bus_buffer.scala 420:110] + wire _T_3230 = ~_T_3229; // @[lsu_bus_buffer.scala 420:84] + wire _T_3231 = buf_rspageQ_0[1] & _T_3230; // @[lsu_bus_buffer.scala 420:82] + wire _T_3223 = _T_2799 | _T_1853; // @[lsu_bus_buffer.scala 420:110] + wire _T_3224 = ~_T_3223; // @[lsu_bus_buffer.scala 420:84] + wire _T_3225 = buf_rspageQ_0[0] & _T_3224; // @[lsu_bus_buffer.scala 420:82] + wire [3:0] buf_rspage_0 = {_T_3243,_T_3237,_T_3231,_T_3225}; // @[Cat.scala 29:58] + wire _T_3162 = buf_rspage_set_0[0] | buf_rspage_0[0]; // @[lsu_bus_buffer.scala 419:88] + wire _T_3165 = buf_rspage_set_0[1] | buf_rspage_0[1]; // @[lsu_bus_buffer.scala 419:88] + wire _T_3168 = buf_rspage_set_0[2] | buf_rspage_0[2]; // @[lsu_bus_buffer.scala 419:88] + wire _T_3171 = buf_rspage_set_0[3] | buf_rspage_0[3]; // @[lsu_bus_buffer.scala 419:88] + wire [2:0] _T_3173 = {_T_3171,_T_3168,_T_3165}; // @[Cat.scala 29:58] + wire _T_3270 = buf_rspageQ_1[3] & _T_3242; // @[lsu_bus_buffer.scala 420:82] + wire _T_3264 = buf_rspageQ_1[2] & _T_3236; // @[lsu_bus_buffer.scala 420:82] + wire _T_3258 = buf_rspageQ_1[1] & _T_3230; // @[lsu_bus_buffer.scala 420:82] + wire _T_3252 = buf_rspageQ_1[0] & _T_3224; // @[lsu_bus_buffer.scala 420:82] + wire [3:0] buf_rspage_1 = {_T_3270,_T_3264,_T_3258,_T_3252}; // @[Cat.scala 29:58] + wire _T_3177 = buf_rspage_set_1[0] | buf_rspage_1[0]; // @[lsu_bus_buffer.scala 419:88] + wire _T_3180 = buf_rspage_set_1[1] | buf_rspage_1[1]; // @[lsu_bus_buffer.scala 419:88] + wire _T_3183 = buf_rspage_set_1[2] | buf_rspage_1[2]; // @[lsu_bus_buffer.scala 419:88] + wire _T_3186 = buf_rspage_set_1[3] | buf_rspage_1[3]; // @[lsu_bus_buffer.scala 419:88] + wire [2:0] _T_3188 = {_T_3186,_T_3183,_T_3180}; // @[Cat.scala 29:58] + wire _T_3297 = buf_rspageQ_2[3] & _T_3242; // @[lsu_bus_buffer.scala 420:82] + wire _T_3291 = buf_rspageQ_2[2] & _T_3236; // @[lsu_bus_buffer.scala 420:82] + wire _T_3285 = buf_rspageQ_2[1] & _T_3230; // @[lsu_bus_buffer.scala 420:82] + wire _T_3279 = buf_rspageQ_2[0] & _T_3224; // @[lsu_bus_buffer.scala 420:82] + wire [3:0] buf_rspage_2 = {_T_3297,_T_3291,_T_3285,_T_3279}; // @[Cat.scala 29:58] + wire _T_3192 = buf_rspage_set_2[0] | buf_rspage_2[0]; // @[lsu_bus_buffer.scala 419:88] + wire _T_3195 = buf_rspage_set_2[1] | buf_rspage_2[1]; // @[lsu_bus_buffer.scala 419:88] + wire _T_3198 = buf_rspage_set_2[2] | buf_rspage_2[2]; // @[lsu_bus_buffer.scala 419:88] + wire _T_3201 = buf_rspage_set_2[3] | buf_rspage_2[3]; // @[lsu_bus_buffer.scala 419:88] + wire [2:0] _T_3203 = {_T_3201,_T_3198,_T_3195}; // @[Cat.scala 29:58] + wire _T_3324 = buf_rspageQ_3[3] & _T_3242; // @[lsu_bus_buffer.scala 420:82] + wire _T_3318 = buf_rspageQ_3[2] & _T_3236; // @[lsu_bus_buffer.scala 420:82] + wire _T_3312 = buf_rspageQ_3[1] & _T_3230; // @[lsu_bus_buffer.scala 420:82] + wire _T_3306 = buf_rspageQ_3[0] & _T_3224; // @[lsu_bus_buffer.scala 420:82] + wire [3:0] buf_rspage_3 = {_T_3324,_T_3318,_T_3312,_T_3306}; // @[Cat.scala 29:58] + wire _T_3207 = buf_rspage_set_3[0] | buf_rspage_3[0]; // @[lsu_bus_buffer.scala 419:88] + wire _T_3210 = buf_rspage_set_3[1] | buf_rspage_3[1]; // @[lsu_bus_buffer.scala 419:88] + wire _T_3213 = buf_rspage_set_3[2] | buf_rspage_3[2]; // @[lsu_bus_buffer.scala 419:88] + wire _T_3216 = buf_rspage_set_3[3] | buf_rspage_3[3]; // @[lsu_bus_buffer.scala 419:88] + wire [2:0] _T_3218 = {_T_3216,_T_3213,_T_3210}; // @[Cat.scala 29:58] + wire _T_3329 = ibuf_drain_vld & _T_1854; // @[lsu_bus_buffer.scala 425:63] + wire _T_3331 = ibuf_drain_vld & _T_1865; // @[lsu_bus_buffer.scala 425:63] + wire _T_3333 = ibuf_drain_vld & _T_1876; // @[lsu_bus_buffer.scala 425:63] + wire _T_3335 = ibuf_drain_vld & _T_1887; // @[lsu_bus_buffer.scala 425:63] + wire [3:0] ibuf_drainvec_vld = {_T_3335,_T_3333,_T_3331,_T_3329}; // @[Cat.scala 29:58] + wire _T_3343 = _T_3537 & _T_1857; // @[lsu_bus_buffer.scala 427:35] + wire _T_3352 = _T_3537 & _T_1868; // @[lsu_bus_buffer.scala 427:35] + wire _T_3361 = _T_3537 & _T_1879; // @[lsu_bus_buffer.scala 427:35] + wire _T_3370 = _T_3537 & _T_1890; // @[lsu_bus_buffer.scala 427:35] + wire _T_3400 = ibuf_drainvec_vld[0] ? ibuf_dual : io_ldst_dual_r; // @[lsu_bus_buffer.scala 429:45] + wire _T_3402 = ibuf_drainvec_vld[1] ? ibuf_dual : io_ldst_dual_r; // @[lsu_bus_buffer.scala 429:45] + wire _T_3404 = ibuf_drainvec_vld[2] ? ibuf_dual : io_ldst_dual_r; // @[lsu_bus_buffer.scala 429:45] + wire _T_3406 = ibuf_drainvec_vld[3] ? ibuf_dual : io_ldst_dual_r; // @[lsu_bus_buffer.scala 429:45] + wire [3:0] buf_dual_in = {_T_3406,_T_3404,_T_3402,_T_3400}; // @[Cat.scala 29:58] + wire _T_3411 = ibuf_drainvec_vld[0] ? ibuf_samedw : ldst_samedw_r; // @[lsu_bus_buffer.scala 430:47] + wire _T_3413 = ibuf_drainvec_vld[1] ? ibuf_samedw : ldst_samedw_r; // @[lsu_bus_buffer.scala 430:47] + wire _T_3415 = ibuf_drainvec_vld[2] ? ibuf_samedw : ldst_samedw_r; // @[lsu_bus_buffer.scala 430:47] + wire _T_3417 = ibuf_drainvec_vld[3] ? ibuf_samedw : ldst_samedw_r; // @[lsu_bus_buffer.scala 430:47] + wire [3:0] buf_samedw_in = {_T_3417,_T_3415,_T_3413,_T_3411}; // @[Cat.scala 29:58] + wire _T_3422 = ibuf_nomerge | ibuf_force_drain; // @[lsu_bus_buffer.scala 431:84] + wire _T_3423 = ibuf_drainvec_vld[0] ? _T_3422 : io_no_dword_merge_r; // @[lsu_bus_buffer.scala 431:48] + wire _T_3426 = ibuf_drainvec_vld[1] ? _T_3422 : io_no_dword_merge_r; // @[lsu_bus_buffer.scala 431:48] + wire _T_3429 = ibuf_drainvec_vld[2] ? _T_3422 : io_no_dword_merge_r; // @[lsu_bus_buffer.scala 431:48] + wire _T_3432 = ibuf_drainvec_vld[3] ? _T_3422 : io_no_dword_merge_r; // @[lsu_bus_buffer.scala 431:48] + wire [3:0] buf_nomerge_in = {_T_3432,_T_3429,_T_3426,_T_3423}; // @[Cat.scala 29:58] + wire _T_3440 = ibuf_drainvec_vld[0] ? ibuf_dual : _T_3343; // @[lsu_bus_buffer.scala 432:47] + wire _T_3445 = ibuf_drainvec_vld[1] ? ibuf_dual : _T_3352; // @[lsu_bus_buffer.scala 432:47] + wire _T_3450 = ibuf_drainvec_vld[2] ? ibuf_dual : _T_3361; // @[lsu_bus_buffer.scala 432:47] + wire _T_3455 = ibuf_drainvec_vld[3] ? ibuf_dual : _T_3370; // @[lsu_bus_buffer.scala 432:47] + wire [3:0] buf_dualhi_in = {_T_3455,_T_3450,_T_3445,_T_3440}; // @[Cat.scala 29:58] + wire _T_3484 = ibuf_drainvec_vld[0] ? ibuf_sideeffect : io_is_sideeffects_r; // @[lsu_bus_buffer.scala 434:51] + wire _T_3486 = ibuf_drainvec_vld[1] ? ibuf_sideeffect : io_is_sideeffects_r; // @[lsu_bus_buffer.scala 434:51] + wire _T_3488 = ibuf_drainvec_vld[2] ? ibuf_sideeffect : io_is_sideeffects_r; // @[lsu_bus_buffer.scala 434:51] + wire _T_3490 = ibuf_drainvec_vld[3] ? ibuf_sideeffect : io_is_sideeffects_r; // @[lsu_bus_buffer.scala 434:51] + wire [3:0] buf_sideeffect_in = {_T_3490,_T_3488,_T_3486,_T_3484}; // @[Cat.scala 29:58] + wire _T_3495 = ibuf_drainvec_vld[0] ? ibuf_unsign : io_lsu_pkt_r_bits_unsign; // @[lsu_bus_buffer.scala 435:47] + wire _T_3497 = ibuf_drainvec_vld[1] ? ibuf_unsign : io_lsu_pkt_r_bits_unsign; // @[lsu_bus_buffer.scala 435:47] + wire _T_3499 = ibuf_drainvec_vld[2] ? ibuf_unsign : io_lsu_pkt_r_bits_unsign; // @[lsu_bus_buffer.scala 435:47] + wire _T_3501 = ibuf_drainvec_vld[3] ? ibuf_unsign : io_lsu_pkt_r_bits_unsign; // @[lsu_bus_buffer.scala 435:47] + wire [3:0] buf_unsign_in = {_T_3501,_T_3499,_T_3497,_T_3495}; // @[Cat.scala 29:58] + wire _T_3518 = ibuf_drainvec_vld[0] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 437:46] + wire _T_3520 = ibuf_drainvec_vld[1] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 437:46] + wire _T_3522 = ibuf_drainvec_vld[2] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 437:46] + wire _T_3524 = ibuf_drainvec_vld[3] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 437:46] + wire [3:0] buf_write_in = {_T_3524,_T_3522,_T_3520,_T_3518}; // @[Cat.scala 29:58] + wire _T_3557 = obuf_nosend & bus_rsp_read; // @[lsu_bus_buffer.scala 453:89] + wire _T_3559 = _T_3557 & _T_1351; // @[lsu_bus_buffer.scala 453:104] + wire _T_3572 = buf_state_en_0 & _T_3643; // @[lsu_bus_buffer.scala 458:44] + wire _T_3573 = _T_3572 & obuf_nosend; // @[lsu_bus_buffer.scala 458:60] + wire _T_3575 = _T_3573 & _T_1333; // @[lsu_bus_buffer.scala 458:74] + wire _T_3578 = _T_3568 & obuf_nosend; // @[lsu_bus_buffer.scala 460:67] + wire _T_3579 = _T_3578 & bus_rsp_read; // @[lsu_bus_buffer.scala 460:81] + wire _T_4872 = io_lsu_axi_r_bits_resp != 2'h0; // @[lsu_bus_buffer.scala 564:64] + wire bus_rsp_read_error = bus_rsp_read & _T_4872; // @[lsu_bus_buffer.scala 564:38] + wire _T_3582 = _T_3578 & bus_rsp_read_error; // @[lsu_bus_buffer.scala 461:82] + wire _T_3657 = bus_rsp_read_error & _T_3636; // @[lsu_bus_buffer.scala 475:91] + wire _T_3659 = bus_rsp_read_error & buf_ldfwd[0]; // @[lsu_bus_buffer.scala 476:31] + wire _T_3661 = _T_3659 & _T_3638; // @[lsu_bus_buffer.scala 476:46] + wire _T_3662 = _T_3657 | _T_3661; // @[lsu_bus_buffer.scala 475:143] + wire _T_3667 = _T_3568 & _T_3662; // @[lsu_bus_buffer.scala 475:68] + wire _GEN_46 = _T_3589 & _T_3667; // @[Conditional.scala 39:67] + wire _GEN_59 = _T_3555 ? _T_3582 : _GEN_46; // @[Conditional.scala 39:67] + wire _GEN_71 = _T_3551 ? 1'h0 : _GEN_59; // @[Conditional.scala 39:67] + wire buf_error_en_0 = _T_3528 ? 1'h0 : _GEN_71; // @[Conditional.scala 40:58] + wire _T_3594 = io_dec_tlu_force_halt | buf_write[0]; // @[lsu_bus_buffer.scala 465:55] + wire _T_3596 = ~buf_samedw_0; // @[lsu_bus_buffer.scala 466:30] + wire _T_3597 = buf_dual_0 & _T_3596; // @[lsu_bus_buffer.scala 466:28] + wire _T_3600 = _T_3597 & _T_3643; // @[lsu_bus_buffer.scala 466:45] + wire [2:0] _GEN_19 = 2'h1 == buf_dualtag_0 ? buf_state_1 : buf_state_0; // @[lsu_bus_buffer.scala 466:90] + wire [2:0] _GEN_20 = 2'h2 == buf_dualtag_0 ? buf_state_2 : _GEN_19; // @[lsu_bus_buffer.scala 466:90] + wire [2:0] _GEN_21 = 2'h3 == buf_dualtag_0 ? buf_state_3 : _GEN_20; // @[lsu_bus_buffer.scala 466:90] + wire _T_3601 = _GEN_21 != 3'h4; // @[lsu_bus_buffer.scala 466:90] + wire _T_3602 = _T_3600 & _T_3601; // @[lsu_bus_buffer.scala 466:61] + wire _T_4494 = _T_2746 | _T_2743; // @[lsu_bus_buffer.scala 524:93] + wire _T_4495 = _T_4494 | _T_2740; // @[lsu_bus_buffer.scala 524:93] + wire any_done_wait_state = _T_4495 | _T_2737; // @[lsu_bus_buffer.scala 524:93] + wire _T_3604 = buf_ldfwd[0] | any_done_wait_state; // @[lsu_bus_buffer.scala 467:31] + wire _T_3610 = buf_dualtag_0 == 2'h0; // @[lsu_bus_buffer.scala 57:118] + wire _T_3612 = buf_dualtag_0 == 2'h1; // @[lsu_bus_buffer.scala 57:118] + wire _T_3614 = buf_dualtag_0 == 2'h2; // @[lsu_bus_buffer.scala 57:118] + wire _T_3616 = buf_dualtag_0 == 2'h3; // @[lsu_bus_buffer.scala 57:118] + wire _T_3618 = _T_3610 & buf_ldfwd[0]; // @[Mux.scala 27:72] + wire _T_3619 = _T_3612 & buf_ldfwd[1]; // @[Mux.scala 27:72] + wire _T_3620 = _T_3614 & buf_ldfwd[2]; // @[Mux.scala 27:72] + wire _T_3621 = _T_3616 & buf_ldfwd[3]; // @[Mux.scala 27:72] + wire _T_3622 = _T_3618 | _T_3619; // @[Mux.scala 27:72] + wire _T_3623 = _T_3622 | _T_3620; // @[Mux.scala 27:72] + wire _T_3624 = _T_3623 | _T_3621; // @[Mux.scala 27:72] + wire _T_3626 = _T_3600 & _T_3624; // @[lsu_bus_buffer.scala 467:101] + wire _T_3627 = _GEN_21 == 3'h4; // @[lsu_bus_buffer.scala 467:167] + wire _T_3628 = _T_3626 & _T_3627; // @[lsu_bus_buffer.scala 467:138] + wire _T_3629 = _T_3628 & any_done_wait_state; // @[lsu_bus_buffer.scala 467:187] + wire _T_3630 = _T_3604 | _T_3629; // @[lsu_bus_buffer.scala 467:53] + wire _T_3653 = buf_state_bus_en_0 & bus_rsp_read; // @[lsu_bus_buffer.scala 474:47] + wire _T_3654 = _T_3653 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 474:62] + wire _T_3668 = ~buf_error_en_0; // @[lsu_bus_buffer.scala 478:50] + wire _T_3669 = buf_state_en_0 & _T_3668; // @[lsu_bus_buffer.scala 478:48] + wire _T_3681 = buf_ldfwd[0] | _T_3686[0]; // @[lsu_bus_buffer.scala 481:90] + wire _T_3682 = _T_3681 | any_done_wait_state; // @[lsu_bus_buffer.scala 481:118] + wire _GEN_29 = _T_3702 & buf_state_en_0; // @[Conditional.scala 39:67] + wire _GEN_32 = _T_3694 ? 1'h0 : _T_3702; // @[Conditional.scala 39:67] + wire _GEN_34 = _T_3694 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67] + wire _GEN_38 = _T_3676 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67] + wire _GEN_40 = _T_3676 ? 1'h0 : _GEN_34; // @[Conditional.scala 39:67] + wire _GEN_45 = _T_3589 & _T_3654; // @[Conditional.scala 39:67] + wire _GEN_48 = _T_3589 ? 1'h0 : _GEN_38; // @[Conditional.scala 39:67] + wire _GEN_50 = _T_3589 ? 1'h0 : _GEN_40; // @[Conditional.scala 39:67] + wire _GEN_56 = _T_3555 ? _T_3575 : _GEN_50; // @[Conditional.scala 39:67] + wire _GEN_58 = _T_3555 ? _T_3579 : _GEN_45; // @[Conditional.scala 39:67] + wire _GEN_62 = _T_3555 ? 1'h0 : _GEN_48; // @[Conditional.scala 39:67] + wire _GEN_68 = _T_3551 ? 1'h0 : _GEN_56; // @[Conditional.scala 39:67] + wire _GEN_70 = _T_3551 ? 1'h0 : _GEN_58; // @[Conditional.scala 39:67] + wire _GEN_74 = _T_3551 ? 1'h0 : _GEN_62; // @[Conditional.scala 39:67] + wire buf_wr_en_0 = _T_3528 & buf_state_en_0; // @[Conditional.scala 40:58] + wire buf_ldfwd_en_0 = _T_3528 ? 1'h0 : _GEN_68; // @[Conditional.scala 40:58] + wire buf_rst_0 = _T_3528 ? 1'h0 : _GEN_74; // @[Conditional.scala 40:58] + wire _T_3765 = buf_state_en_1 & _T_3836; // @[lsu_bus_buffer.scala 458:44] + wire _T_3766 = _T_3765 & obuf_nosend; // @[lsu_bus_buffer.scala 458:60] + wire _T_3768 = _T_3766 & _T_1333; // @[lsu_bus_buffer.scala 458:74] + wire _T_3771 = _T_3761 & obuf_nosend; // @[lsu_bus_buffer.scala 460:67] + wire _T_3772 = _T_3771 & bus_rsp_read; // @[lsu_bus_buffer.scala 460:81] + wire _T_3775 = _T_3771 & bus_rsp_read_error; // @[lsu_bus_buffer.scala 461:82] + wire _T_3850 = bus_rsp_read_error & _T_3829; // @[lsu_bus_buffer.scala 475:91] + wire _T_3852 = bus_rsp_read_error & buf_ldfwd[1]; // @[lsu_bus_buffer.scala 476:31] + wire _T_3854 = _T_3852 & _T_3831; // @[lsu_bus_buffer.scala 476:46] + wire _T_3855 = _T_3850 | _T_3854; // @[lsu_bus_buffer.scala 475:143] + wire _T_3860 = _T_3761 & _T_3855; // @[lsu_bus_buffer.scala 475:68] + wire _GEN_122 = _T_3782 & _T_3860; // @[Conditional.scala 39:67] + wire _GEN_135 = _T_3748 ? _T_3775 : _GEN_122; // @[Conditional.scala 39:67] + wire _GEN_147 = _T_3744 ? 1'h0 : _GEN_135; // @[Conditional.scala 39:67] + wire buf_error_en_1 = _T_3721 ? 1'h0 : _GEN_147; // @[Conditional.scala 40:58] + wire _T_3787 = io_dec_tlu_force_halt | buf_write[1]; // @[lsu_bus_buffer.scala 465:55] + wire _T_3789 = ~buf_samedw_1; // @[lsu_bus_buffer.scala 466:30] + wire _T_3790 = buf_dual_1 & _T_3789; // @[lsu_bus_buffer.scala 466:28] + wire _T_3793 = _T_3790 & _T_3836; // @[lsu_bus_buffer.scala 466:45] + wire [2:0] _GEN_95 = 2'h1 == buf_dualtag_1 ? buf_state_1 : buf_state_0; // @[lsu_bus_buffer.scala 466:90] + wire [2:0] _GEN_96 = 2'h2 == buf_dualtag_1 ? buf_state_2 : _GEN_95; // @[lsu_bus_buffer.scala 466:90] + wire [2:0] _GEN_97 = 2'h3 == buf_dualtag_1 ? buf_state_3 : _GEN_96; // @[lsu_bus_buffer.scala 466:90] + wire _T_3794 = _GEN_97 != 3'h4; // @[lsu_bus_buffer.scala 466:90] + wire _T_3795 = _T_3793 & _T_3794; // @[lsu_bus_buffer.scala 466:61] + wire _T_3797 = buf_ldfwd[1] | any_done_wait_state; // @[lsu_bus_buffer.scala 467:31] + wire _T_3803 = buf_dualtag_1 == 2'h0; // @[lsu_bus_buffer.scala 57:118] + wire _T_3805 = buf_dualtag_1 == 2'h1; // @[lsu_bus_buffer.scala 57:118] + wire _T_3807 = buf_dualtag_1 == 2'h2; // @[lsu_bus_buffer.scala 57:118] + wire _T_3809 = buf_dualtag_1 == 2'h3; // @[lsu_bus_buffer.scala 57:118] + wire _T_3811 = _T_3803 & buf_ldfwd[0]; // @[Mux.scala 27:72] + wire _T_3812 = _T_3805 & buf_ldfwd[1]; // @[Mux.scala 27:72] + wire _T_3813 = _T_3807 & buf_ldfwd[2]; // @[Mux.scala 27:72] + wire _T_3814 = _T_3809 & buf_ldfwd[3]; // @[Mux.scala 27:72] + wire _T_3815 = _T_3811 | _T_3812; // @[Mux.scala 27:72] + wire _T_3816 = _T_3815 | _T_3813; // @[Mux.scala 27:72] + wire _T_3817 = _T_3816 | _T_3814; // @[Mux.scala 27:72] + wire _T_3819 = _T_3793 & _T_3817; // @[lsu_bus_buffer.scala 467:101] + wire _T_3820 = _GEN_97 == 3'h4; // @[lsu_bus_buffer.scala 467:167] + wire _T_3821 = _T_3819 & _T_3820; // @[lsu_bus_buffer.scala 467:138] + wire _T_3822 = _T_3821 & any_done_wait_state; // @[lsu_bus_buffer.scala 467:187] + wire _T_3823 = _T_3797 | _T_3822; // @[lsu_bus_buffer.scala 467:53] + wire _T_3846 = buf_state_bus_en_1 & bus_rsp_read; // @[lsu_bus_buffer.scala 474:47] + wire _T_3847 = _T_3846 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 474:62] + wire _T_3861 = ~buf_error_en_1; // @[lsu_bus_buffer.scala 478:50] + wire _T_3862 = buf_state_en_1 & _T_3861; // @[lsu_bus_buffer.scala 478:48] + wire _T_3874 = buf_ldfwd[1] | _T_3879[0]; // @[lsu_bus_buffer.scala 481:90] + wire _T_3875 = _T_3874 | any_done_wait_state; // @[lsu_bus_buffer.scala 481:118] + wire _GEN_105 = _T_3895 & buf_state_en_1; // @[Conditional.scala 39:67] + wire _GEN_108 = _T_3887 ? 1'h0 : _T_3895; // @[Conditional.scala 39:67] + wire _GEN_110 = _T_3887 ? 1'h0 : _GEN_105; // @[Conditional.scala 39:67] + wire _GEN_114 = _T_3869 ? 1'h0 : _GEN_108; // @[Conditional.scala 39:67] + wire _GEN_116 = _T_3869 ? 1'h0 : _GEN_110; // @[Conditional.scala 39:67] + wire _GEN_121 = _T_3782 & _T_3847; // @[Conditional.scala 39:67] + wire _GEN_124 = _T_3782 ? 1'h0 : _GEN_114; // @[Conditional.scala 39:67] + wire _GEN_126 = _T_3782 ? 1'h0 : _GEN_116; // @[Conditional.scala 39:67] + wire _GEN_132 = _T_3748 ? _T_3768 : _GEN_126; // @[Conditional.scala 39:67] + wire _GEN_134 = _T_3748 ? _T_3772 : _GEN_121; // @[Conditional.scala 39:67] + wire _GEN_138 = _T_3748 ? 1'h0 : _GEN_124; // @[Conditional.scala 39:67] + wire _GEN_144 = _T_3744 ? 1'h0 : _GEN_132; // @[Conditional.scala 39:67] + wire _GEN_146 = _T_3744 ? 1'h0 : _GEN_134; // @[Conditional.scala 39:67] + wire _GEN_150 = _T_3744 ? 1'h0 : _GEN_138; // @[Conditional.scala 39:67] + wire buf_wr_en_1 = _T_3721 & buf_state_en_1; // @[Conditional.scala 40:58] + wire buf_ldfwd_en_1 = _T_3721 ? 1'h0 : _GEN_144; // @[Conditional.scala 40:58] + wire buf_rst_1 = _T_3721 ? 1'h0 : _GEN_150; // @[Conditional.scala 40:58] + wire _T_3958 = buf_state_en_2 & _T_4029; // @[lsu_bus_buffer.scala 458:44] + wire _T_3959 = _T_3958 & obuf_nosend; // @[lsu_bus_buffer.scala 458:60] + wire _T_3961 = _T_3959 & _T_1333; // @[lsu_bus_buffer.scala 458:74] + wire _T_3964 = _T_3954 & obuf_nosend; // @[lsu_bus_buffer.scala 460:67] + wire _T_3965 = _T_3964 & bus_rsp_read; // @[lsu_bus_buffer.scala 460:81] + wire _T_3968 = _T_3964 & bus_rsp_read_error; // @[lsu_bus_buffer.scala 461:82] + wire _T_4043 = bus_rsp_read_error & _T_4022; // @[lsu_bus_buffer.scala 475:91] + wire _T_4045 = bus_rsp_read_error & buf_ldfwd[2]; // @[lsu_bus_buffer.scala 476:31] + wire _T_4047 = _T_4045 & _T_4024; // @[lsu_bus_buffer.scala 476:46] + wire _T_4048 = _T_4043 | _T_4047; // @[lsu_bus_buffer.scala 475:143] + wire _T_4053 = _T_3954 & _T_4048; // @[lsu_bus_buffer.scala 475:68] + wire _GEN_198 = _T_3975 & _T_4053; // @[Conditional.scala 39:67] + wire _GEN_211 = _T_3941 ? _T_3968 : _GEN_198; // @[Conditional.scala 39:67] + wire _GEN_223 = _T_3937 ? 1'h0 : _GEN_211; // @[Conditional.scala 39:67] + wire buf_error_en_2 = _T_3914 ? 1'h0 : _GEN_223; // @[Conditional.scala 40:58] + wire _T_3980 = io_dec_tlu_force_halt | buf_write[2]; // @[lsu_bus_buffer.scala 465:55] + wire _T_3982 = ~buf_samedw_2; // @[lsu_bus_buffer.scala 466:30] + wire _T_3983 = buf_dual_2 & _T_3982; // @[lsu_bus_buffer.scala 466:28] + wire _T_3986 = _T_3983 & _T_4029; // @[lsu_bus_buffer.scala 466:45] + wire [2:0] _GEN_171 = 2'h1 == buf_dualtag_2 ? buf_state_1 : buf_state_0; // @[lsu_bus_buffer.scala 466:90] + wire [2:0] _GEN_172 = 2'h2 == buf_dualtag_2 ? buf_state_2 : _GEN_171; // @[lsu_bus_buffer.scala 466:90] + wire [2:0] _GEN_173 = 2'h3 == buf_dualtag_2 ? buf_state_3 : _GEN_172; // @[lsu_bus_buffer.scala 466:90] + wire _T_3987 = _GEN_173 != 3'h4; // @[lsu_bus_buffer.scala 466:90] + wire _T_3988 = _T_3986 & _T_3987; // @[lsu_bus_buffer.scala 466:61] + wire _T_3990 = buf_ldfwd[2] | any_done_wait_state; // @[lsu_bus_buffer.scala 467:31] + wire _T_3996 = buf_dualtag_2 == 2'h0; // @[lsu_bus_buffer.scala 57:118] + wire _T_3998 = buf_dualtag_2 == 2'h1; // @[lsu_bus_buffer.scala 57:118] + wire _T_4000 = buf_dualtag_2 == 2'h2; // @[lsu_bus_buffer.scala 57:118] + wire _T_4002 = buf_dualtag_2 == 2'h3; // @[lsu_bus_buffer.scala 57:118] + wire _T_4004 = _T_3996 & buf_ldfwd[0]; // @[Mux.scala 27:72] + wire _T_4005 = _T_3998 & buf_ldfwd[1]; // @[Mux.scala 27:72] + wire _T_4006 = _T_4000 & buf_ldfwd[2]; // @[Mux.scala 27:72] + wire _T_4007 = _T_4002 & buf_ldfwd[3]; // @[Mux.scala 27:72] + wire _T_4008 = _T_4004 | _T_4005; // @[Mux.scala 27:72] + wire _T_4009 = _T_4008 | _T_4006; // @[Mux.scala 27:72] + wire _T_4010 = _T_4009 | _T_4007; // @[Mux.scala 27:72] + wire _T_4012 = _T_3986 & _T_4010; // @[lsu_bus_buffer.scala 467:101] + wire _T_4013 = _GEN_173 == 3'h4; // @[lsu_bus_buffer.scala 467:167] + wire _T_4014 = _T_4012 & _T_4013; // @[lsu_bus_buffer.scala 467:138] + wire _T_4015 = _T_4014 & any_done_wait_state; // @[lsu_bus_buffer.scala 467:187] + wire _T_4016 = _T_3990 | _T_4015; // @[lsu_bus_buffer.scala 467:53] + wire _T_4039 = buf_state_bus_en_2 & bus_rsp_read; // @[lsu_bus_buffer.scala 474:47] + wire _T_4040 = _T_4039 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 474:62] + wire _T_4054 = ~buf_error_en_2; // @[lsu_bus_buffer.scala 478:50] + wire _T_4055 = buf_state_en_2 & _T_4054; // @[lsu_bus_buffer.scala 478:48] + wire _T_4067 = buf_ldfwd[2] | _T_4072[0]; // @[lsu_bus_buffer.scala 481:90] + wire _T_4068 = _T_4067 | any_done_wait_state; // @[lsu_bus_buffer.scala 481:118] + wire _GEN_181 = _T_4088 & buf_state_en_2; // @[Conditional.scala 39:67] + wire _GEN_184 = _T_4080 ? 1'h0 : _T_4088; // @[Conditional.scala 39:67] + wire _GEN_186 = _T_4080 ? 1'h0 : _GEN_181; // @[Conditional.scala 39:67] + wire _GEN_190 = _T_4062 ? 1'h0 : _GEN_184; // @[Conditional.scala 39:67] + wire _GEN_192 = _T_4062 ? 1'h0 : _GEN_186; // @[Conditional.scala 39:67] + wire _GEN_197 = _T_3975 & _T_4040; // @[Conditional.scala 39:67] + wire _GEN_200 = _T_3975 ? 1'h0 : _GEN_190; // @[Conditional.scala 39:67] + wire _GEN_202 = _T_3975 ? 1'h0 : _GEN_192; // @[Conditional.scala 39:67] + wire _GEN_208 = _T_3941 ? _T_3961 : _GEN_202; // @[Conditional.scala 39:67] + wire _GEN_210 = _T_3941 ? _T_3965 : _GEN_197; // @[Conditional.scala 39:67] + wire _GEN_214 = _T_3941 ? 1'h0 : _GEN_200; // @[Conditional.scala 39:67] + wire _GEN_220 = _T_3937 ? 1'h0 : _GEN_208; // @[Conditional.scala 39:67] + wire _GEN_222 = _T_3937 ? 1'h0 : _GEN_210; // @[Conditional.scala 39:67] + wire _GEN_226 = _T_3937 ? 1'h0 : _GEN_214; // @[Conditional.scala 39:67] + wire buf_wr_en_2 = _T_3914 & buf_state_en_2; // @[Conditional.scala 40:58] + wire buf_ldfwd_en_2 = _T_3914 ? 1'h0 : _GEN_220; // @[Conditional.scala 40:58] + wire buf_rst_2 = _T_3914 ? 1'h0 : _GEN_226; // @[Conditional.scala 40:58] + wire _T_4151 = buf_state_en_3 & _T_4222; // @[lsu_bus_buffer.scala 458:44] + wire _T_4152 = _T_4151 & obuf_nosend; // @[lsu_bus_buffer.scala 458:60] + wire _T_4154 = _T_4152 & _T_1333; // @[lsu_bus_buffer.scala 458:74] + wire _T_4157 = _T_4147 & obuf_nosend; // @[lsu_bus_buffer.scala 460:67] + wire _T_4158 = _T_4157 & bus_rsp_read; // @[lsu_bus_buffer.scala 460:81] + wire _T_4161 = _T_4157 & bus_rsp_read_error; // @[lsu_bus_buffer.scala 461:82] + wire _T_4236 = bus_rsp_read_error & _T_4215; // @[lsu_bus_buffer.scala 475:91] + wire _T_4238 = bus_rsp_read_error & buf_ldfwd[3]; // @[lsu_bus_buffer.scala 476:31] + wire _T_4240 = _T_4238 & _T_4217; // @[lsu_bus_buffer.scala 476:46] + wire _T_4241 = _T_4236 | _T_4240; // @[lsu_bus_buffer.scala 475:143] + wire _T_4246 = _T_4147 & _T_4241; // @[lsu_bus_buffer.scala 475:68] + wire _GEN_274 = _T_4168 & _T_4246; // @[Conditional.scala 39:67] + wire _GEN_287 = _T_4134 ? _T_4161 : _GEN_274; // @[Conditional.scala 39:67] + wire _GEN_299 = _T_4130 ? 1'h0 : _GEN_287; // @[Conditional.scala 39:67] + wire buf_error_en_3 = _T_4107 ? 1'h0 : _GEN_299; // @[Conditional.scala 40:58] + wire _T_4173 = io_dec_tlu_force_halt | buf_write[3]; // @[lsu_bus_buffer.scala 465:55] + wire _T_4175 = ~buf_samedw_3; // @[lsu_bus_buffer.scala 466:30] + wire _T_4176 = buf_dual_3 & _T_4175; // @[lsu_bus_buffer.scala 466:28] + wire _T_4179 = _T_4176 & _T_4222; // @[lsu_bus_buffer.scala 466:45] + wire [2:0] _GEN_247 = 2'h1 == buf_dualtag_3 ? buf_state_1 : buf_state_0; // @[lsu_bus_buffer.scala 466:90] + wire [2:0] _GEN_248 = 2'h2 == buf_dualtag_3 ? buf_state_2 : _GEN_247; // @[lsu_bus_buffer.scala 466:90] + wire [2:0] _GEN_249 = 2'h3 == buf_dualtag_3 ? buf_state_3 : _GEN_248; // @[lsu_bus_buffer.scala 466:90] + wire _T_4180 = _GEN_249 != 3'h4; // @[lsu_bus_buffer.scala 466:90] + wire _T_4181 = _T_4179 & _T_4180; // @[lsu_bus_buffer.scala 466:61] + wire _T_4183 = buf_ldfwd[3] | any_done_wait_state; // @[lsu_bus_buffer.scala 467:31] + wire _T_4189 = buf_dualtag_3 == 2'h0; // @[lsu_bus_buffer.scala 57:118] + wire _T_4191 = buf_dualtag_3 == 2'h1; // @[lsu_bus_buffer.scala 57:118] + wire _T_4193 = buf_dualtag_3 == 2'h2; // @[lsu_bus_buffer.scala 57:118] + wire _T_4195 = buf_dualtag_3 == 2'h3; // @[lsu_bus_buffer.scala 57:118] + wire _T_4197 = _T_4189 & buf_ldfwd[0]; // @[Mux.scala 27:72] + wire _T_4198 = _T_4191 & buf_ldfwd[1]; // @[Mux.scala 27:72] + wire _T_4199 = _T_4193 & buf_ldfwd[2]; // @[Mux.scala 27:72] + wire _T_4200 = _T_4195 & buf_ldfwd[3]; // @[Mux.scala 27:72] + wire _T_4201 = _T_4197 | _T_4198; // @[Mux.scala 27:72] + wire _T_4202 = _T_4201 | _T_4199; // @[Mux.scala 27:72] + wire _T_4203 = _T_4202 | _T_4200; // @[Mux.scala 27:72] + wire _T_4205 = _T_4179 & _T_4203; // @[lsu_bus_buffer.scala 467:101] + wire _T_4206 = _GEN_249 == 3'h4; // @[lsu_bus_buffer.scala 467:167] + wire _T_4207 = _T_4205 & _T_4206; // @[lsu_bus_buffer.scala 467:138] + wire _T_4208 = _T_4207 & any_done_wait_state; // @[lsu_bus_buffer.scala 467:187] + wire _T_4209 = _T_4183 | _T_4208; // @[lsu_bus_buffer.scala 467:53] + wire _T_4232 = buf_state_bus_en_3 & bus_rsp_read; // @[lsu_bus_buffer.scala 474:47] + wire _T_4233 = _T_4232 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 474:62] + wire _T_4247 = ~buf_error_en_3; // @[lsu_bus_buffer.scala 478:50] + wire _T_4248 = buf_state_en_3 & _T_4247; // @[lsu_bus_buffer.scala 478:48] + wire _T_4260 = buf_ldfwd[3] | _T_4265[0]; // @[lsu_bus_buffer.scala 481:90] + wire _T_4261 = _T_4260 | any_done_wait_state; // @[lsu_bus_buffer.scala 481:118] + wire _GEN_257 = _T_4281 & buf_state_en_3; // @[Conditional.scala 39:67] + wire _GEN_260 = _T_4273 ? 1'h0 : _T_4281; // @[Conditional.scala 39:67] + wire _GEN_262 = _T_4273 ? 1'h0 : _GEN_257; // @[Conditional.scala 39:67] + wire _GEN_266 = _T_4255 ? 1'h0 : _GEN_260; // @[Conditional.scala 39:67] + wire _GEN_268 = _T_4255 ? 1'h0 : _GEN_262; // @[Conditional.scala 39:67] + wire _GEN_273 = _T_4168 & _T_4233; // @[Conditional.scala 39:67] + wire _GEN_276 = _T_4168 ? 1'h0 : _GEN_266; // @[Conditional.scala 39:67] + wire _GEN_278 = _T_4168 ? 1'h0 : _GEN_268; // @[Conditional.scala 39:67] + wire _GEN_284 = _T_4134 ? _T_4154 : _GEN_278; // @[Conditional.scala 39:67] + wire _GEN_286 = _T_4134 ? _T_4158 : _GEN_273; // @[Conditional.scala 39:67] + wire _GEN_290 = _T_4134 ? 1'h0 : _GEN_276; // @[Conditional.scala 39:67] + wire _GEN_296 = _T_4130 ? 1'h0 : _GEN_284; // @[Conditional.scala 39:67] + wire _GEN_298 = _T_4130 ? 1'h0 : _GEN_286; // @[Conditional.scala 39:67] + wire _GEN_302 = _T_4130 ? 1'h0 : _GEN_290; // @[Conditional.scala 39:67] + wire buf_wr_en_3 = _T_4107 & buf_state_en_3; // @[Conditional.scala 40:58] + wire buf_ldfwd_en_3 = _T_4107 ? 1'h0 : _GEN_296; // @[Conditional.scala 40:58] + wire buf_rst_3 = _T_4107 ? 1'h0 : _GEN_302; // @[Conditional.scala 40:58] + reg _T_4336; // @[Reg.scala 27:20] + reg _T_4339; // @[Reg.scala 27:20] + reg _T_4342; // @[Reg.scala 27:20] + reg _T_4345; // @[Reg.scala 27:20] + wire [3:0] buf_unsign = {_T_4345,_T_4342,_T_4339,_T_4336}; // @[Cat.scala 29:58] + reg _T_4411; // @[lsu_bus_buffer.scala 517:80] + reg _T_4406; // @[lsu_bus_buffer.scala 517:80] + reg _T_4401; // @[lsu_bus_buffer.scala 517:80] + reg _T_4396; // @[lsu_bus_buffer.scala 517:80] + wire [3:0] buf_error = {_T_4411,_T_4406,_T_4401,_T_4396}; // @[Cat.scala 29:58] + wire _T_4393 = buf_error_en_0 | buf_error[0]; // @[lsu_bus_buffer.scala 517:84] + wire _T_4394 = ~buf_rst_0; // @[lsu_bus_buffer.scala 517:126] + wire _T_4398 = buf_error_en_1 | buf_error[1]; // @[lsu_bus_buffer.scala 517:84] + wire _T_4399 = ~buf_rst_1; // @[lsu_bus_buffer.scala 517:126] + wire _T_4403 = buf_error_en_2 | buf_error[2]; // @[lsu_bus_buffer.scala 517:84] + wire _T_4404 = ~buf_rst_2; // @[lsu_bus_buffer.scala 517:126] + wire _T_4408 = buf_error_en_3 | buf_error[3]; // @[lsu_bus_buffer.scala 517:84] + wire _T_4409 = ~buf_rst_3; // @[lsu_bus_buffer.scala 517:126] + wire [1:0] _T_4415 = {io_lsu_busreq_m,1'h0}; // @[Cat.scala 29:58] + wire [1:0] _T_4416 = io_ldst_dual_m ? _T_4415 : {{1'd0}, io_lsu_busreq_m}; // @[lsu_bus_buffer.scala 520:28] + wire [1:0] _T_4417 = {io_lsu_busreq_r,1'h0}; // @[Cat.scala 29:58] + wire [1:0] _T_4418 = io_ldst_dual_r ? _T_4417 : {{1'd0}, io_lsu_busreq_r}; // @[lsu_bus_buffer.scala 520:94] + wire [2:0] _T_4419 = _T_4416 + _T_4418; // @[lsu_bus_buffer.scala 520:88] + wire [2:0] _GEN_388 = {{2'd0}, ibuf_valid}; // @[lsu_bus_buffer.scala 520:154] + wire [3:0] _T_4420 = _T_4419 + _GEN_388; // @[lsu_bus_buffer.scala 520:154] + wire [1:0] _T_4425 = _T_5 + _T_12; // @[lsu_bus_buffer.scala 520:217] + wire [1:0] _GEN_389 = {{1'd0}, _T_19}; // @[lsu_bus_buffer.scala 520:217] + wire [2:0] _T_4426 = _T_4425 + _GEN_389; // @[lsu_bus_buffer.scala 520:217] + wire [2:0] _GEN_390 = {{2'd0}, _T_26}; // @[lsu_bus_buffer.scala 520:217] + wire [3:0] _T_4427 = _T_4426 + _GEN_390; // @[lsu_bus_buffer.scala 520:217] + wire [3:0] buf_numvld_any = _T_4420 + _T_4427; // @[lsu_bus_buffer.scala 520:169] + wire _T_4498 = io_ldst_dual_d & io_dec_lsu_valid_raw_d; // @[lsu_bus_buffer.scala 526:52] + wire _T_4499 = buf_numvld_any >= 4'h3; // @[lsu_bus_buffer.scala 526:92] + wire _T_4500 = buf_numvld_any == 4'h4; // @[lsu_bus_buffer.scala 526:121] + wire _T_4502 = |buf_state_0; // @[lsu_bus_buffer.scala 527:52] + wire _T_4503 = |buf_state_1; // @[lsu_bus_buffer.scala 527:52] + wire _T_4504 = |buf_state_2; // @[lsu_bus_buffer.scala 527:52] + wire _T_4505 = |buf_state_3; // @[lsu_bus_buffer.scala 527:52] + wire _T_4506 = _T_4502 | _T_4503; // @[lsu_bus_buffer.scala 527:65] + wire _T_4507 = _T_4506 | _T_4504; // @[lsu_bus_buffer.scala 527:65] + wire _T_4508 = _T_4507 | _T_4505; // @[lsu_bus_buffer.scala 527:65] + wire _T_4509 = ~_T_4508; // @[lsu_bus_buffer.scala 527:34] + wire _T_4511 = _T_4509 & _T_852; // @[lsu_bus_buffer.scala 527:70] + wire _T_4514 = io_lsu_busreq_m & io_lsu_pkt_m_valid; // @[lsu_bus_buffer.scala 529:64] + wire _T_4515 = _T_4514 & io_lsu_pkt_m_bits_load; // @[lsu_bus_buffer.scala 529:85] + wire _T_4516 = ~io_flush_m_up; // @[lsu_bus_buffer.scala 529:112] + wire _T_4517 = _T_4515 & _T_4516; // @[lsu_bus_buffer.scala 529:110] + wire _T_4518 = ~io_ld_full_hit_m; // @[lsu_bus_buffer.scala 529:129] + wire _T_4520 = ~io_lsu_commit_r; // @[lsu_bus_buffer.scala 532:74] + reg lsu_nonblock_load_valid_r; // @[lsu_bus_buffer.scala 617:66] + wire _T_4542 = _T_2799 | _T_2821; // @[Mux.scala 27:72] + wire _T_4543 = _T_4542 | _T_2843; // @[Mux.scala 27:72] + wire lsu_nonblock_load_data_ready = _T_4543 | _T_2865; // @[Mux.scala 27:72] + wire _T_4549 = buf_error[0] & _T_3643; // @[lsu_bus_buffer.scala 535:121] + wire _T_4554 = buf_error[1] & _T_3836; // @[lsu_bus_buffer.scala 535:121] + wire _T_4559 = buf_error[2] & _T_4029; // @[lsu_bus_buffer.scala 535:121] + wire _T_4564 = buf_error[3] & _T_4222; // @[lsu_bus_buffer.scala 535:121] + wire _T_4565 = _T_2799 & _T_4549; // @[Mux.scala 27:72] + wire _T_4566 = _T_2821 & _T_4554; // @[Mux.scala 27:72] + wire _T_4567 = _T_2843 & _T_4559; // @[Mux.scala 27:72] + wire _T_4568 = _T_2865 & _T_4564; // @[Mux.scala 27:72] + wire _T_4569 = _T_4565 | _T_4566; // @[Mux.scala 27:72] + wire _T_4570 = _T_4569 | _T_4567; // @[Mux.scala 27:72] + wire _T_4576 = _T_2799 & _T_3643; // @[lsu_bus_buffer.scala 536:103] + wire _T_4577 = ~buf_dual_0; // @[lsu_bus_buffer.scala 536:122] + wire _T_4578 = ~buf_dualhi_0; // @[lsu_bus_buffer.scala 536:137] + wire _T_4579 = _T_4577 | _T_4578; // @[lsu_bus_buffer.scala 536:135] + wire _T_4580 = _T_4576 & _T_4579; // @[lsu_bus_buffer.scala 536:119] + wire _T_4584 = _T_2821 & _T_3836; // @[lsu_bus_buffer.scala 536:103] + wire _T_4585 = ~buf_dual_1; // @[lsu_bus_buffer.scala 536:122] + wire _T_4586 = ~buf_dualhi_1; // @[lsu_bus_buffer.scala 536:137] + wire _T_4587 = _T_4585 | _T_4586; // @[lsu_bus_buffer.scala 536:135] + wire _T_4588 = _T_4584 & _T_4587; // @[lsu_bus_buffer.scala 536:119] + wire _T_4592 = _T_2843 & _T_4029; // @[lsu_bus_buffer.scala 536:103] + wire _T_4593 = ~buf_dual_2; // @[lsu_bus_buffer.scala 536:122] + wire _T_4594 = ~buf_dualhi_2; // @[lsu_bus_buffer.scala 536:137] + wire _T_4595 = _T_4593 | _T_4594; // @[lsu_bus_buffer.scala 536:135] + wire _T_4596 = _T_4592 & _T_4595; // @[lsu_bus_buffer.scala 536:119] + wire _T_4600 = _T_2865 & _T_4222; // @[lsu_bus_buffer.scala 536:103] + wire _T_4601 = ~buf_dual_3; // @[lsu_bus_buffer.scala 536:122] + wire _T_4602 = ~buf_dualhi_3; // @[lsu_bus_buffer.scala 536:137] + wire _T_4603 = _T_4601 | _T_4602; // @[lsu_bus_buffer.scala 536:135] + wire _T_4604 = _T_4600 & _T_4603; // @[lsu_bus_buffer.scala 536:119] + wire [1:0] _T_4607 = _T_4596 ? 2'h2 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4608 = _T_4604 ? 2'h3 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _GEN_391 = {{1'd0}, _T_4588}; // @[Mux.scala 27:72] + wire [1:0] _T_4610 = _GEN_391 | _T_4607; // @[Mux.scala 27:72] + wire [31:0] _T_4645 = _T_4580 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4646 = _T_4588 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4647 = _T_4596 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4648 = _T_4604 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4649 = _T_4645 | _T_4646; // @[Mux.scala 27:72] + wire [31:0] _T_4650 = _T_4649 | _T_4647; // @[Mux.scala 27:72] + wire [31:0] lsu_nonblock_load_data_lo = _T_4650 | _T_4648; // @[Mux.scala 27:72] + wire _T_4657 = _T_4576 & _T_3641; // @[lsu_bus_buffer.scala 538:105] + wire _T_4663 = _T_4584 & _T_3834; // @[lsu_bus_buffer.scala 538:105] + wire _T_4669 = _T_4592 & _T_4027; // @[lsu_bus_buffer.scala 538:105] + wire _T_4675 = _T_4600 & _T_4220; // @[lsu_bus_buffer.scala 538:105] + wire [31:0] _T_4676 = _T_4657 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4677 = _T_4663 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4678 = _T_4669 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4679 = _T_4675 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4680 = _T_4676 | _T_4677; // @[Mux.scala 27:72] + wire [31:0] _T_4681 = _T_4680 | _T_4678; // @[Mux.scala 27:72] + wire [31:0] lsu_nonblock_load_data_hi = _T_4681 | _T_4679; // @[Mux.scala 27:72] + wire _T_4683 = io_dctl_busbuff_lsu_nonblock_load_data_tag == 2'h0; // @[lsu_bus_buffer.scala 58:123] + wire _T_4684 = io_dctl_busbuff_lsu_nonblock_load_data_tag == 2'h1; // @[lsu_bus_buffer.scala 58:123] + wire _T_4685 = io_dctl_busbuff_lsu_nonblock_load_data_tag == 2'h2; // @[lsu_bus_buffer.scala 58:123] + wire _T_4686 = io_dctl_busbuff_lsu_nonblock_load_data_tag == 2'h3; // @[lsu_bus_buffer.scala 58:123] + wire [31:0] _T_4687 = _T_4683 ? buf_addr_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4688 = _T_4684 ? buf_addr_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4689 = _T_4685 ? buf_addr_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4690 = _T_4686 ? buf_addr_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4691 = _T_4687 | _T_4688; // @[Mux.scala 27:72] + wire [31:0] _T_4692 = _T_4691 | _T_4689; // @[Mux.scala 27:72] + wire [31:0] _T_4693 = _T_4692 | _T_4690; // @[Mux.scala 27:72] + wire [1:0] lsu_nonblock_addr_offset = _T_4693[1:0]; // @[lsu_bus_buffer.scala 539:96] + wire [1:0] _T_4699 = _T_4683 ? buf_sz_0 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4700 = _T_4684 ? buf_sz_1 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4701 = _T_4685 ? buf_sz_2 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4702 = _T_4686 ? buf_sz_3 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4703 = _T_4699 | _T_4700; // @[Mux.scala 27:72] + wire [1:0] _T_4704 = _T_4703 | _T_4701; // @[Mux.scala 27:72] + wire [1:0] lsu_nonblock_sz = _T_4704 | _T_4702; // @[Mux.scala 27:72] + wire _T_4714 = _T_4683 & buf_unsign[0]; // @[Mux.scala 27:72] + wire _T_4715 = _T_4684 & buf_unsign[1]; // @[Mux.scala 27:72] + wire _T_4716 = _T_4685 & buf_unsign[2]; // @[Mux.scala 27:72] + wire _T_4717 = _T_4686 & buf_unsign[3]; // @[Mux.scala 27:72] + wire _T_4718 = _T_4714 | _T_4715; // @[Mux.scala 27:72] + wire _T_4719 = _T_4718 | _T_4716; // @[Mux.scala 27:72] + wire lsu_nonblock_unsign = _T_4719 | _T_4717; // @[Mux.scala 27:72] + wire [63:0] _T_4739 = {lsu_nonblock_load_data_hi,lsu_nonblock_load_data_lo}; // @[Cat.scala 29:58] + wire [3:0] _GEN_392 = {{2'd0}, lsu_nonblock_addr_offset}; // @[lsu_bus_buffer.scala 543:121] + wire [5:0] _T_4740 = _GEN_392 * 4'h8; // @[lsu_bus_buffer.scala 543:121] + wire [63:0] lsu_nonblock_data_unalgn = _T_4739 >> _T_4740; // @[lsu_bus_buffer.scala 543:92] + wire _T_4741 = ~io_dctl_busbuff_lsu_nonblock_load_data_error; // @[lsu_bus_buffer.scala 545:82] + wire _T_4743 = lsu_nonblock_sz == 2'h0; // @[lsu_bus_buffer.scala 546:94] + wire _T_4744 = lsu_nonblock_unsign & _T_4743; // @[lsu_bus_buffer.scala 546:76] + wire [31:0] _T_4746 = {24'h0,lsu_nonblock_data_unalgn[7:0]}; // @[Cat.scala 29:58] + wire _T_4747 = lsu_nonblock_sz == 2'h1; // @[lsu_bus_buffer.scala 547:45] + wire _T_4748 = lsu_nonblock_unsign & _T_4747; // @[lsu_bus_buffer.scala 547:26] + wire [31:0] _T_4750 = {16'h0,lsu_nonblock_data_unalgn[15:0]}; // @[Cat.scala 29:58] + wire _T_4751 = ~lsu_nonblock_unsign; // @[lsu_bus_buffer.scala 548:6] + wire _T_4753 = _T_4751 & _T_4743; // @[lsu_bus_buffer.scala 548:27] + wire [23:0] _T_4756 = lsu_nonblock_data_unalgn[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_4758 = {_T_4756,lsu_nonblock_data_unalgn[7:0]}; // @[Cat.scala 29:58] + wire _T_4761 = _T_4751 & _T_4747; // @[lsu_bus_buffer.scala 549:27] + wire [15:0] _T_4764 = lsu_nonblock_data_unalgn[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_4766 = {_T_4764,lsu_nonblock_data_unalgn[15:0]}; // @[Cat.scala 29:58] + wire _T_4767 = lsu_nonblock_sz == 2'h2; // @[lsu_bus_buffer.scala 550:21] + wire [31:0] _T_4768 = _T_4744 ? _T_4746 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4769 = _T_4748 ? _T_4750 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4770 = _T_4753 ? _T_4758 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4771 = _T_4761 ? _T_4766 : 32'h0; // @[Mux.scala 27:72] + wire [63:0] _T_4772 = _T_4767 ? lsu_nonblock_data_unalgn : 64'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4773 = _T_4768 | _T_4769; // @[Mux.scala 27:72] + wire [31:0] _T_4774 = _T_4773 | _T_4770; // @[Mux.scala 27:72] + wire [31:0] _T_4775 = _T_4774 | _T_4771; // @[Mux.scala 27:72] + wire [63:0] _GEN_393 = {{32'd0}, _T_4775}; // @[Mux.scala 27:72] + wire [63:0] _T_4776 = _GEN_393 | _T_4772; // @[Mux.scala 27:72] + wire _T_4874 = obuf_valid & obuf_write; // @[lsu_bus_buffer.scala 568:37] + wire _T_4875 = ~obuf_cmd_done; // @[lsu_bus_buffer.scala 568:52] + wire [31:0] _T_4880 = {obuf_addr[31:3],3'h0}; // @[Cat.scala 29:58] + wire [2:0] _T_4882 = {1'h0,obuf_sz}; // @[Cat.scala 29:58] + wire _T_4887 = ~obuf_data_done; // @[lsu_bus_buffer.scala 580:51] + wire [7:0] _T_4892 = obuf_write ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire _T_4895 = obuf_valid & _T_1343; // @[lsu_bus_buffer.scala 585:37] + wire _T_4909 = io_lsu_bus_clk_en_q & buf_error[0]; // @[lsu_bus_buffer.scala 598:126] + wire _T_4911 = _T_4909 & buf_write[0]; // @[lsu_bus_buffer.scala 598:141] + wire _T_4914 = io_lsu_bus_clk_en_q & buf_error[1]; // @[lsu_bus_buffer.scala 598:126] + wire _T_4916 = _T_4914 & buf_write[1]; // @[lsu_bus_buffer.scala 598:141] + wire _T_4919 = io_lsu_bus_clk_en_q & buf_error[2]; // @[lsu_bus_buffer.scala 598:126] + wire _T_4921 = _T_4919 & buf_write[2]; // @[lsu_bus_buffer.scala 598:141] + wire _T_4924 = io_lsu_bus_clk_en_q & buf_error[3]; // @[lsu_bus_buffer.scala 598:126] + wire _T_4926 = _T_4924 & buf_write[3]; // @[lsu_bus_buffer.scala 598:141] + wire _T_4927 = _T_2799 & _T_4911; // @[Mux.scala 27:72] + wire _T_4928 = _T_2821 & _T_4916; // @[Mux.scala 27:72] + wire _T_4929 = _T_2843 & _T_4921; // @[Mux.scala 27:72] + wire _T_4930 = _T_2865 & _T_4926; // @[Mux.scala 27:72] + wire _T_4931 = _T_4927 | _T_4928; // @[Mux.scala 27:72] + wire _T_4932 = _T_4931 | _T_4929; // @[Mux.scala 27:72] + wire _T_4942 = _T_2821 & buf_error[1]; // @[lsu_bus_buffer.scala 599:93] + wire _T_4944 = _T_4942 & buf_write[1]; // @[lsu_bus_buffer.scala 599:108] + wire _T_4947 = _T_2843 & buf_error[2]; // @[lsu_bus_buffer.scala 599:93] + wire _T_4949 = _T_4947 & buf_write[2]; // @[lsu_bus_buffer.scala 599:108] + wire _T_4952 = _T_2865 & buf_error[3]; // @[lsu_bus_buffer.scala 599:93] + wire _T_4954 = _T_4952 & buf_write[3]; // @[lsu_bus_buffer.scala 599:108] + wire [1:0] _T_4957 = _T_4949 ? 2'h2 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4958 = _T_4954 ? 2'h3 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _GEN_394 = {{1'd0}, _T_4944}; // @[Mux.scala 27:72] + wire [1:0] _T_4960 = _GEN_394 | _T_4957; // @[Mux.scala 27:72] + wire [1:0] lsu_imprecise_error_store_tag = _T_4960 | _T_4958; // @[Mux.scala 27:72] + wire _T_4962 = ~io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_buffer.scala 601:97] + wire [31:0] _GEN_351 = 2'h1 == lsu_imprecise_error_store_tag ? buf_addr_1 : buf_addr_0; // @[lsu_bus_buffer.scala 602:53] + wire [31:0] _GEN_352 = 2'h2 == lsu_imprecise_error_store_tag ? buf_addr_2 : _GEN_351; // @[lsu_bus_buffer.scala 602:53] + wire [31:0] _GEN_353 = 2'h3 == lsu_imprecise_error_store_tag ? buf_addr_3 : _GEN_352; // @[lsu_bus_buffer.scala 602:53] + wire [31:0] _GEN_355 = 2'h1 == io_dctl_busbuff_lsu_nonblock_load_data_tag ? buf_addr_1 : buf_addr_0; // @[lsu_bus_buffer.scala 602:53] + wire [31:0] _GEN_356 = 2'h2 == io_dctl_busbuff_lsu_nonblock_load_data_tag ? buf_addr_2 : _GEN_355; // @[lsu_bus_buffer.scala 602:53] + wire [31:0] _GEN_357 = 2'h3 == io_dctl_busbuff_lsu_nonblock_load_data_tag ? buf_addr_3 : _GEN_356; // @[lsu_bus_buffer.scala 602:53] + wire _T_4967 = bus_wcmd_sent | bus_wdata_sent; // @[lsu_bus_buffer.scala 608:82] + wire _T_4970 = io_lsu_busreq_r & io_ldst_dual_r; // @[lsu_bus_buffer.scala 609:60] + wire _T_4973 = ~io_lsu_axi_aw_ready; // @[lsu_bus_buffer.scala 612:61] + wire _T_4974 = io_lsu_axi_aw_valid & _T_4973; // @[lsu_bus_buffer.scala 612:59] + wire _T_4975 = ~io_lsu_axi_w_ready; // @[lsu_bus_buffer.scala 612:107] + wire _T_4976 = io_lsu_axi_w_valid & _T_4975; // @[lsu_bus_buffer.scala 612:105] + wire _T_4977 = _T_4974 | _T_4976; // @[lsu_bus_buffer.scala 612:83] + wire _T_4978 = ~io_lsu_axi_ar_ready; // @[lsu_bus_buffer.scala 612:153] + wire _T_4979 = io_lsu_axi_ar_valid & _T_4978; // @[lsu_bus_buffer.scala 612:151] + wire _T_4983 = ~io_flush_r; // @[lsu_bus_buffer.scala 616:75] + wire _T_4984 = io_lsu_busreq_m & _T_4983; // @[lsu_bus_buffer.scala 616:73] + reg _T_4987; // @[lsu_bus_buffer.scala 616:56] + rvclkhdr rvclkhdr ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) + ); + rvclkhdr rvclkhdr_1 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_1_io_l1clk), + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en), + .io_scan_mode(rvclkhdr_1_io_scan_mode) + ); + rvclkhdr rvclkhdr_2 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_2_io_l1clk), + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en), + .io_scan_mode(rvclkhdr_2_io_scan_mode) + ); + rvclkhdr rvclkhdr_3 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_3_io_l1clk), + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en), + .io_scan_mode(rvclkhdr_3_io_scan_mode) + ); + rvclkhdr rvclkhdr_4 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_4_io_l1clk), + .io_clk(rvclkhdr_4_io_clk), + .io_en(rvclkhdr_4_io_en), + .io_scan_mode(rvclkhdr_4_io_scan_mode) + ); + rvclkhdr rvclkhdr_5 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_5_io_l1clk), + .io_clk(rvclkhdr_5_io_clk), + .io_en(rvclkhdr_5_io_en), + .io_scan_mode(rvclkhdr_5_io_scan_mode) + ); + rvclkhdr rvclkhdr_6 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_6_io_l1clk), + .io_clk(rvclkhdr_6_io_clk), + .io_en(rvclkhdr_6_io_en), + .io_scan_mode(rvclkhdr_6_io_scan_mode) + ); + rvclkhdr rvclkhdr_7 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_7_io_l1clk), + .io_clk(rvclkhdr_7_io_clk), + .io_en(rvclkhdr_7_io_en), + .io_scan_mode(rvclkhdr_7_io_scan_mode) + ); + rvclkhdr rvclkhdr_8 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_8_io_l1clk), + .io_clk(rvclkhdr_8_io_clk), + .io_en(rvclkhdr_8_io_en), + .io_scan_mode(rvclkhdr_8_io_scan_mode) + ); + rvclkhdr rvclkhdr_9 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_9_io_l1clk), + .io_clk(rvclkhdr_9_io_clk), + .io_en(rvclkhdr_9_io_en), + .io_scan_mode(rvclkhdr_9_io_scan_mode) + ); + rvclkhdr rvclkhdr_10 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_10_io_l1clk), + .io_clk(rvclkhdr_10_io_clk), + .io_en(rvclkhdr_10_io_en), + .io_scan_mode(rvclkhdr_10_io_scan_mode) + ); + rvclkhdr rvclkhdr_11 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_11_io_l1clk), + .io_clk(rvclkhdr_11_io_clk), + .io_en(rvclkhdr_11_io_en), + .io_scan_mode(rvclkhdr_11_io_scan_mode) + ); + assign io_tlu_busbuff_lsu_pmu_bus_trxn = _T_4967 | _T_4866; // @[lsu_bus_buffer.scala 608:35] + assign io_tlu_busbuff_lsu_pmu_bus_misaligned = _T_4970 & io_lsu_commit_r; // @[lsu_bus_buffer.scala 609:41] + assign io_tlu_busbuff_lsu_pmu_bus_error = io_tlu_busbuff_lsu_imprecise_error_load_any | io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_buffer.scala 610:36] + assign io_tlu_busbuff_lsu_pmu_bus_busy = _T_4977 | _T_4979; // @[lsu_bus_buffer.scala 612:35] + assign io_tlu_busbuff_lsu_imprecise_error_load_any = io_dctl_busbuff_lsu_nonblock_load_data_error & _T_4962; // @[lsu_bus_buffer.scala 601:47] + assign io_tlu_busbuff_lsu_imprecise_error_store_any = _T_4932 | _T_4930; // @[lsu_bus_buffer.scala 598:48] + assign io_tlu_busbuff_lsu_imprecise_error_addr_any = io_tlu_busbuff_lsu_imprecise_error_store_any ? _GEN_353 : _GEN_357; // @[lsu_bus_buffer.scala 602:47] + assign io_dctl_busbuff_lsu_nonblock_load_valid_m = _T_4517 & _T_4518; // @[lsu_bus_buffer.scala 529:45] + assign io_dctl_busbuff_lsu_nonblock_load_tag_m = _T_1863 ? 2'h0 : _T_1899; // @[lsu_bus_buffer.scala 530:43] + assign io_dctl_busbuff_lsu_nonblock_load_inv_r = lsu_nonblock_load_valid_r & _T_4520; // @[lsu_bus_buffer.scala 532:43] + assign io_dctl_busbuff_lsu_nonblock_load_inv_tag_r = WrPtr0_r; // @[lsu_bus_buffer.scala 533:47] + assign io_dctl_busbuff_lsu_nonblock_load_data_valid = lsu_nonblock_load_data_ready & _T_4741; // @[lsu_bus_buffer.scala 545:48] + assign io_dctl_busbuff_lsu_nonblock_load_data_error = _T_4570 | _T_4568; // @[lsu_bus_buffer.scala 535:48] + assign io_dctl_busbuff_lsu_nonblock_load_data_tag = _T_4610 | _T_4608; // @[lsu_bus_buffer.scala 536:46] + assign io_dctl_busbuff_lsu_nonblock_load_data = _T_4776[31:0]; // @[lsu_bus_buffer.scala 546:42] + assign io_lsu_axi_aw_valid = _T_4874 & _T_4875; // @[lsu_bus_buffer.scala 568:23] + assign io_lsu_axi_aw_bits_id = {{1'd0}, _T_1848}; // @[lsu_bus_buffer.scala 569:25] + assign io_lsu_axi_aw_bits_addr = obuf_sideeffect ? obuf_addr : _T_4880; // @[lsu_bus_buffer.scala 570:27] + assign io_lsu_axi_aw_bits_region = obuf_addr[31:28]; // @[lsu_bus_buffer.scala 574:29] + assign io_lsu_axi_aw_bits_len = 8'h0; // @[lsu_bus_buffer.scala 575:26] + assign io_lsu_axi_aw_bits_size = obuf_sideeffect ? _T_4882 : 3'h3; // @[lsu_bus_buffer.scala 571:27] + assign io_lsu_axi_aw_bits_burst = 2'h1; // @[lsu_bus_buffer.scala 576:28] + assign io_lsu_axi_aw_bits_lock = 1'h0; // @[lsu_bus_buffer.scala 578:27] + assign io_lsu_axi_aw_bits_cache = obuf_sideeffect ? 4'h0 : 4'hf; // @[lsu_bus_buffer.scala 573:28] + assign io_lsu_axi_aw_bits_prot = 3'h0; // @[lsu_bus_buffer.scala 572:27] + assign io_lsu_axi_aw_bits_qos = 4'h0; // @[lsu_bus_buffer.scala 577:26] + assign io_lsu_axi_w_valid = _T_4874 & _T_4887; // @[lsu_bus_buffer.scala 580:22] + assign io_lsu_axi_w_bits_data = obuf_data; // @[lsu_bus_buffer.scala 582:26] + assign io_lsu_axi_w_bits_strb = obuf_byteen & _T_4892; // @[lsu_bus_buffer.scala 581:26] + assign io_lsu_axi_w_bits_last = 1'h1; // @[lsu_bus_buffer.scala 583:26] + assign io_lsu_axi_b_ready = 1'h1; // @[lsu_bus_buffer.scala 596:22] + assign io_lsu_axi_ar_valid = _T_4895 & _T_1349; // @[lsu_bus_buffer.scala 585:23] + assign io_lsu_axi_ar_bits_id = {{1'd0}, _T_1848}; // @[lsu_bus_buffer.scala 586:25] + assign io_lsu_axi_ar_bits_addr = obuf_sideeffect ? obuf_addr : _T_4880; // @[lsu_bus_buffer.scala 587:27] + assign io_lsu_axi_ar_bits_region = obuf_addr[31:28]; // @[lsu_bus_buffer.scala 591:29] + assign io_lsu_axi_ar_bits_len = 8'h0; // @[lsu_bus_buffer.scala 592:26] + assign io_lsu_axi_ar_bits_size = obuf_sideeffect ? _T_4882 : 3'h3; // @[lsu_bus_buffer.scala 588:27] + assign io_lsu_axi_ar_bits_burst = 2'h1; // @[lsu_bus_buffer.scala 593:28] + assign io_lsu_axi_ar_bits_lock = 1'h0; // @[lsu_bus_buffer.scala 595:27] + assign io_lsu_axi_ar_bits_cache = obuf_sideeffect ? 4'h0 : 4'hf; // @[lsu_bus_buffer.scala 590:28] + assign io_lsu_axi_ar_bits_prot = 3'h0; // @[lsu_bus_buffer.scala 589:27] + assign io_lsu_axi_ar_bits_qos = 4'h0; // @[lsu_bus_buffer.scala 594:26] + assign io_lsu_axi_r_ready = 1'h1; // @[lsu_bus_buffer.scala 597:22] + assign io_lsu_busreq_r = _T_4987; // @[lsu_bus_buffer.scala 616:19] + assign io_lsu_bus_buffer_pend_any = |buf_numvld_pend_any; // @[lsu_bus_buffer.scala 525:30] + assign io_lsu_bus_buffer_full_any = _T_4498 ? _T_4499 : _T_4500; // @[lsu_bus_buffer.scala 526:30] + assign io_lsu_bus_buffer_empty_any = _T_4511 & _T_1231; // @[lsu_bus_buffer.scala 527:31] + assign io_lsu_bus_idle_any = 1'h1; // @[lsu_bus_buffer.scala 605:23] + assign io_ld_byte_hit_buf_lo = {_T_69,_T_58}; // @[lsu_bus_buffer.scala 138:25] + assign io_ld_byte_hit_buf_hi = {_T_84,_T_73}; // @[lsu_bus_buffer.scala 139:25] + assign io_ld_fwddata_buf_lo = _T_650 | _T_651; // @[lsu_bus_buffer.scala 165:24] + assign io_ld_fwddata_buf_hi = _T_747 | _T_748; // @[lsu_bus_buffer.scala 171:24] + assign rvclkhdr_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_io_en = _T_853 & _T_854; // @[lib.scala 371:17] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_1_io_en = _T_853 & _T_854; // @[lib.scala 371:17] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_2_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_2_io_en = _T_1236 & io_lsu_bus_clk_en; // @[lib.scala 371:17] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_3_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_3_io_en = _T_1236 & io_lsu_bus_clk_en; // @[lib.scala 371:17] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_4_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_4_io_en = _T_3528 & buf_state_en_0; // @[lib.scala 371:17] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_5_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_5_io_en = _T_3721 & buf_state_en_1; // @[lib.scala 371:17] + assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_6_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_6_io_en = _T_3914 & buf_state_en_2; // @[lib.scala 371:17] + assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_7_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_7_io_en = _T_4107 & buf_state_en_3; // @[lib.scala 371:17] + assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_8_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_8_io_en = _T_3528 ? buf_state_en_0 : _GEN_70; // @[lib.scala 371:17] + assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_9_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_9_io_en = _T_3721 ? buf_state_en_1 : _GEN_146; // @[lib.scala 371:17] + assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_10_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_10_io_en = _T_3914 ? buf_state_en_2 : _GEN_222; // @[lib.scala 371:17] + assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_11_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_11_io_en = _T_4107 ? buf_state_en_3 : _GEN_298; // @[lib.scala 371:17] + assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + buf_addr_0 = _RAND_0[31:0]; + _RAND_1 = {1{`RANDOM}}; + _T_4360 = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + _T_4357 = _RAND_2[0:0]; + _RAND_3 = {1{`RANDOM}}; + _T_4354 = _RAND_3[0:0]; + _RAND_4 = {1{`RANDOM}}; + _T_4351 = _RAND_4[0:0]; + _RAND_5 = {1{`RANDOM}}; + buf_state_0 = _RAND_5[2:0]; + _RAND_6 = {1{`RANDOM}}; + buf_addr_1 = _RAND_6[31:0]; + _RAND_7 = {1{`RANDOM}}; + buf_state_1 = _RAND_7[2:0]; + _RAND_8 = {1{`RANDOM}}; + buf_addr_2 = _RAND_8[31:0]; + _RAND_9 = {1{`RANDOM}}; + buf_state_2 = _RAND_9[2:0]; + _RAND_10 = {1{`RANDOM}}; + buf_addr_3 = _RAND_10[31:0]; + _RAND_11 = {1{`RANDOM}}; + buf_state_3 = _RAND_11[2:0]; + _RAND_12 = {1{`RANDOM}}; + buf_byteen_3 = _RAND_12[3:0]; + _RAND_13 = {1{`RANDOM}}; + buf_byteen_2 = _RAND_13[3:0]; + _RAND_14 = {1{`RANDOM}}; + buf_byteen_1 = _RAND_14[3:0]; + _RAND_15 = {1{`RANDOM}}; + buf_byteen_0 = _RAND_15[3:0]; + _RAND_16 = {1{`RANDOM}}; + buf_ageQ_3 = _RAND_16[3:0]; + _RAND_17 = {1{`RANDOM}}; + _T_1848 = _RAND_17[1:0]; + _RAND_18 = {1{`RANDOM}}; + obuf_merge = _RAND_18[0:0]; + _RAND_19 = {1{`RANDOM}}; + obuf_tag1 = _RAND_19[1:0]; + _RAND_20 = {1{`RANDOM}}; + obuf_valid = _RAND_20[0:0]; + _RAND_21 = {1{`RANDOM}}; + obuf_wr_enQ = _RAND_21[0:0]; + _RAND_22 = {1{`RANDOM}}; + ibuf_addr = _RAND_22[31:0]; + _RAND_23 = {1{`RANDOM}}; + ibuf_write = _RAND_23[0:0]; + _RAND_24 = {1{`RANDOM}}; + ibuf_valid = _RAND_24[0:0]; + _RAND_25 = {1{`RANDOM}}; + ibuf_byteen = _RAND_25[3:0]; + _RAND_26 = {1{`RANDOM}}; + buf_ageQ_2 = _RAND_26[3:0]; + _RAND_27 = {1{`RANDOM}}; + buf_ageQ_1 = _RAND_27[3:0]; + _RAND_28 = {1{`RANDOM}}; + buf_ageQ_0 = _RAND_28[3:0]; + _RAND_29 = {1{`RANDOM}}; + buf_data_0 = _RAND_29[31:0]; + _RAND_30 = {1{`RANDOM}}; + buf_data_1 = _RAND_30[31:0]; + _RAND_31 = {1{`RANDOM}}; + buf_data_2 = _RAND_31[31:0]; + _RAND_32 = {1{`RANDOM}}; + buf_data_3 = _RAND_32[31:0]; + _RAND_33 = {1{`RANDOM}}; + ibuf_data = _RAND_33[31:0]; + _RAND_34 = {1{`RANDOM}}; + ibuf_timer = _RAND_34[2:0]; + _RAND_35 = {1{`RANDOM}}; + ibuf_sideeffect = _RAND_35[0:0]; + _RAND_36 = {1{`RANDOM}}; + WrPtr1_r = _RAND_36[1:0]; + _RAND_37 = {1{`RANDOM}}; + WrPtr0_r = _RAND_37[1:0]; + _RAND_38 = {1{`RANDOM}}; + ibuf_tag = _RAND_38[1:0]; + _RAND_39 = {1{`RANDOM}}; + ibuf_dualtag = _RAND_39[1:0]; + _RAND_40 = {1{`RANDOM}}; + ibuf_dual = _RAND_40[0:0]; + _RAND_41 = {1{`RANDOM}}; + ibuf_samedw = _RAND_41[0:0]; + _RAND_42 = {1{`RANDOM}}; + ibuf_nomerge = _RAND_42[0:0]; + _RAND_43 = {1{`RANDOM}}; + ibuf_unsign = _RAND_43[0:0]; + _RAND_44 = {1{`RANDOM}}; + ibuf_sz = _RAND_44[1:0]; + _RAND_45 = {1{`RANDOM}}; + obuf_wr_timer = _RAND_45[2:0]; + _RAND_46 = {1{`RANDOM}}; + buf_nomerge_0 = _RAND_46[0:0]; + _RAND_47 = {1{`RANDOM}}; + buf_nomerge_1 = _RAND_47[0:0]; + _RAND_48 = {1{`RANDOM}}; + buf_nomerge_2 = _RAND_48[0:0]; + _RAND_49 = {1{`RANDOM}}; + buf_nomerge_3 = _RAND_49[0:0]; + _RAND_50 = {1{`RANDOM}}; + _T_4330 = _RAND_50[0:0]; + _RAND_51 = {1{`RANDOM}}; + _T_4327 = _RAND_51[0:0]; + _RAND_52 = {1{`RANDOM}}; + _T_4324 = _RAND_52[0:0]; + _RAND_53 = {1{`RANDOM}}; + _T_4321 = _RAND_53[0:0]; + _RAND_54 = {1{`RANDOM}}; + obuf_sideeffect = _RAND_54[0:0]; + _RAND_55 = {1{`RANDOM}}; + buf_dual_3 = _RAND_55[0:0]; + _RAND_56 = {1{`RANDOM}}; + buf_dual_2 = _RAND_56[0:0]; + _RAND_57 = {1{`RANDOM}}; + buf_dual_1 = _RAND_57[0:0]; + _RAND_58 = {1{`RANDOM}}; + buf_dual_0 = _RAND_58[0:0]; + _RAND_59 = {1{`RANDOM}}; + buf_samedw_3 = _RAND_59[0:0]; + _RAND_60 = {1{`RANDOM}}; + buf_samedw_2 = _RAND_60[0:0]; + _RAND_61 = {1{`RANDOM}}; + buf_samedw_1 = _RAND_61[0:0]; + _RAND_62 = {1{`RANDOM}}; + buf_samedw_0 = _RAND_62[0:0]; + _RAND_63 = {1{`RANDOM}}; + obuf_write = _RAND_63[0:0]; + _RAND_64 = {1{`RANDOM}}; + obuf_cmd_done = _RAND_64[0:0]; + _RAND_65 = {1{`RANDOM}}; + obuf_data_done = _RAND_65[0:0]; + _RAND_66 = {1{`RANDOM}}; + obuf_nosend = _RAND_66[0:0]; + _RAND_67 = {1{`RANDOM}}; + obuf_addr = _RAND_67[31:0]; + _RAND_68 = {1{`RANDOM}}; + buf_sz_0 = _RAND_68[1:0]; + _RAND_69 = {1{`RANDOM}}; + buf_sz_1 = _RAND_69[1:0]; + _RAND_70 = {1{`RANDOM}}; + buf_sz_2 = _RAND_70[1:0]; + _RAND_71 = {1{`RANDOM}}; + buf_sz_3 = _RAND_71[1:0]; + _RAND_72 = {1{`RANDOM}}; + obuf_rdrsp_pend = _RAND_72[0:0]; + _RAND_73 = {1{`RANDOM}}; + obuf_rdrsp_tag = _RAND_73[2:0]; + _RAND_74 = {1{`RANDOM}}; + buf_dualhi_3 = _RAND_74[0:0]; + _RAND_75 = {1{`RANDOM}}; + buf_dualhi_2 = _RAND_75[0:0]; + _RAND_76 = {1{`RANDOM}}; + buf_dualhi_1 = _RAND_76[0:0]; + _RAND_77 = {1{`RANDOM}}; + buf_dualhi_0 = _RAND_77[0:0]; + _RAND_78 = {1{`RANDOM}}; + obuf_sz = _RAND_78[1:0]; + _RAND_79 = {1{`RANDOM}}; + obuf_byteen = _RAND_79[7:0]; + _RAND_80 = {2{`RANDOM}}; + obuf_data = _RAND_80[63:0]; + _RAND_81 = {1{`RANDOM}}; + buf_rspageQ_0 = _RAND_81[3:0]; + _RAND_82 = {1{`RANDOM}}; + buf_rspageQ_1 = _RAND_82[3:0]; + _RAND_83 = {1{`RANDOM}}; + buf_rspageQ_2 = _RAND_83[3:0]; + _RAND_84 = {1{`RANDOM}}; + buf_rspageQ_3 = _RAND_84[3:0]; + _RAND_85 = {1{`RANDOM}}; + _T_4307 = _RAND_85[0:0]; + _RAND_86 = {1{`RANDOM}}; + _T_4305 = _RAND_86[0:0]; + _RAND_87 = {1{`RANDOM}}; + _T_4303 = _RAND_87[0:0]; + _RAND_88 = {1{`RANDOM}}; + _T_4301 = _RAND_88[0:0]; + _RAND_89 = {1{`RANDOM}}; + buf_ldfwdtag_0 = _RAND_89[1:0]; + _RAND_90 = {1{`RANDOM}}; + buf_dualtag_0 = _RAND_90[1:0]; + _RAND_91 = {1{`RANDOM}}; + buf_ldfwdtag_3 = _RAND_91[1:0]; + _RAND_92 = {1{`RANDOM}}; + buf_ldfwdtag_2 = _RAND_92[1:0]; + _RAND_93 = {1{`RANDOM}}; + buf_ldfwdtag_1 = _RAND_93[1:0]; + _RAND_94 = {1{`RANDOM}}; + buf_dualtag_1 = _RAND_94[1:0]; + _RAND_95 = {1{`RANDOM}}; + buf_dualtag_2 = _RAND_95[1:0]; + _RAND_96 = {1{`RANDOM}}; + buf_dualtag_3 = _RAND_96[1:0]; + _RAND_97 = {1{`RANDOM}}; + _T_4336 = _RAND_97[0:0]; + _RAND_98 = {1{`RANDOM}}; + _T_4339 = _RAND_98[0:0]; + _RAND_99 = {1{`RANDOM}}; + _T_4342 = _RAND_99[0:0]; + _RAND_100 = {1{`RANDOM}}; + _T_4345 = _RAND_100[0:0]; + _RAND_101 = {1{`RANDOM}}; + _T_4411 = _RAND_101[0:0]; + _RAND_102 = {1{`RANDOM}}; + _T_4406 = _RAND_102[0:0]; + _RAND_103 = {1{`RANDOM}}; + _T_4401 = _RAND_103[0:0]; + _RAND_104 = {1{`RANDOM}}; + _T_4396 = _RAND_104[0:0]; + _RAND_105 = {1{`RANDOM}}; + lsu_nonblock_load_valid_r = _RAND_105[0:0]; + _RAND_106 = {1{`RANDOM}}; + _T_4987 = _RAND_106[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + buf_addr_0 = 32'h0; + end + if (reset) begin + _T_4360 = 1'h0; + end + if (reset) begin + _T_4357 = 1'h0; + end + if (reset) begin + _T_4354 = 1'h0; + end + if (reset) begin + _T_4351 = 1'h0; + end + if (reset) begin + buf_state_0 = 3'h0; + end + if (reset) begin + buf_addr_1 = 32'h0; + end + if (reset) begin + buf_state_1 = 3'h0; + end + if (reset) begin + buf_addr_2 = 32'h0; + end + if (reset) begin + buf_state_2 = 3'h0; + end + if (reset) begin + buf_addr_3 = 32'h0; + end + if (reset) begin + buf_state_3 = 3'h0; + end + if (reset) begin + buf_byteen_3 = 4'h0; + end + if (reset) begin + buf_byteen_2 = 4'h0; + end + if (reset) begin + buf_byteen_1 = 4'h0; + end + if (reset) begin + buf_byteen_0 = 4'h0; + end + if (reset) begin + buf_ageQ_3 = 4'h0; + end + if (reset) begin + _T_1848 = 2'h0; + end + if (reset) begin + obuf_merge = 1'h0; + end + if (reset) begin + obuf_tag1 = 2'h0; + end + if (reset) begin + obuf_valid = 1'h0; + end + if (reset) begin + obuf_wr_enQ = 1'h0; + end + if (reset) begin + ibuf_addr = 32'h0; + end + if (reset) begin + ibuf_write = 1'h0; + end + if (reset) begin + ibuf_valid = 1'h0; + end + if (reset) begin + ibuf_byteen = 4'h0; + end + if (reset) begin + buf_ageQ_2 = 4'h0; + end + if (reset) begin + buf_ageQ_1 = 4'h0; + end + if (reset) begin + buf_ageQ_0 = 4'h0; + end + if (reset) begin + buf_data_0 = 32'h0; + end + if (reset) begin + buf_data_1 = 32'h0; + end + if (reset) begin + buf_data_2 = 32'h0; + end + if (reset) begin + buf_data_3 = 32'h0; + end + if (reset) begin + ibuf_data = 32'h0; + end + if (reset) begin + ibuf_timer = 3'h0; + end + if (reset) begin + ibuf_sideeffect = 1'h0; + end + if (reset) begin + WrPtr1_r = 2'h0; + end + if (reset) begin + WrPtr0_r = 2'h0; + end + if (reset) begin + ibuf_tag = 2'h0; + end + if (reset) begin + ibuf_dualtag = 2'h0; + end + if (reset) begin + ibuf_dual = 1'h0; + end + if (reset) begin + ibuf_samedw = 1'h0; + end + if (reset) begin + ibuf_nomerge = 1'h0; + end + if (reset) begin + ibuf_unsign = 1'h0; + end + if (reset) begin + ibuf_sz = 2'h0; + end + if (reset) begin + obuf_wr_timer = 3'h0; + end + if (reset) begin + buf_nomerge_0 = 1'h0; + end + if (reset) begin + buf_nomerge_1 = 1'h0; + end + if (reset) begin + buf_nomerge_2 = 1'h0; + end + if (reset) begin + buf_nomerge_3 = 1'h0; + end + if (reset) begin + _T_4330 = 1'h0; + end + if (reset) begin + _T_4327 = 1'h0; + end + if (reset) begin + _T_4324 = 1'h0; + end + if (reset) begin + _T_4321 = 1'h0; + end + if (reset) begin + obuf_sideeffect = 1'h0; + end + if (reset) begin + buf_dual_3 = 1'h0; + end + if (reset) begin + buf_dual_2 = 1'h0; + end + if (reset) begin + buf_dual_1 = 1'h0; + end + if (reset) begin + buf_dual_0 = 1'h0; + end + if (reset) begin + buf_samedw_3 = 1'h0; + end + if (reset) begin + buf_samedw_2 = 1'h0; + end + if (reset) begin + buf_samedw_1 = 1'h0; + end + if (reset) begin + buf_samedw_0 = 1'h0; + end + if (reset) begin + obuf_write = 1'h0; + end + if (reset) begin + obuf_cmd_done = 1'h0; + end + if (reset) begin + obuf_data_done = 1'h0; + end + if (reset) begin + obuf_nosend = 1'h0; + end + if (reset) begin + obuf_addr = 32'h0; + end + if (reset) begin + buf_sz_0 = 2'h0; + end + if (reset) begin + buf_sz_1 = 2'h0; + end + if (reset) begin + buf_sz_2 = 2'h0; + end + if (reset) begin + buf_sz_3 = 2'h0; + end + if (reset) begin + obuf_rdrsp_pend = 1'h0; + end + if (reset) begin + obuf_rdrsp_tag = 3'h0; + end + if (reset) begin + buf_dualhi_3 = 1'h0; + end + if (reset) begin + buf_dualhi_2 = 1'h0; + end + if (reset) begin + buf_dualhi_1 = 1'h0; + end + if (reset) begin + buf_dualhi_0 = 1'h0; + end + if (reset) begin + obuf_sz = 2'h0; + end + if (reset) begin + obuf_byteen = 8'h0; + end + if (reset) begin + obuf_data = 64'h0; + end + if (reset) begin + buf_rspageQ_0 = 4'h0; + end + if (reset) begin + buf_rspageQ_1 = 4'h0; + end + if (reset) begin + buf_rspageQ_2 = 4'h0; + end + if (reset) begin + buf_rspageQ_3 = 4'h0; + end + if (reset) begin + _T_4307 = 1'h0; + end + if (reset) begin + _T_4305 = 1'h0; + end + if (reset) begin + _T_4303 = 1'h0; + end + if (reset) begin + _T_4301 = 1'h0; + end + if (reset) begin + buf_ldfwdtag_0 = 2'h0; + end + if (reset) begin + buf_dualtag_0 = 2'h0; + end + if (reset) begin + buf_ldfwdtag_3 = 2'h0; + end + if (reset) begin + buf_ldfwdtag_2 = 2'h0; + end + if (reset) begin + buf_ldfwdtag_1 = 2'h0; + end + if (reset) begin + buf_dualtag_1 = 2'h0; + end + if (reset) begin + buf_dualtag_2 = 2'h0; + end + if (reset) begin + buf_dualtag_3 = 2'h0; + end + if (reset) begin + _T_4336 = 1'h0; + end + if (reset) begin + _T_4339 = 1'h0; + end + if (reset) begin + _T_4342 = 1'h0; + end + if (reset) begin + _T_4345 = 1'h0; + end + if (reset) begin + _T_4411 = 1'h0; + end + if (reset) begin + _T_4406 = 1'h0; + end + if (reset) begin + _T_4401 = 1'h0; + end + if (reset) begin + _T_4396 = 1'h0; + end + if (reset) begin + lsu_nonblock_load_valid_r = 1'h0; + end + if (reset) begin + _T_4987 = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + if (reset) begin + buf_addr_0 <= 32'h0; + end else if (ibuf_drainvec_vld[0]) begin + buf_addr_0 <= ibuf_addr; + end else if (_T_3343) begin + buf_addr_0 <= io_end_addr_r; + end else begin + buf_addr_0 <= io_lsu_addr_r; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4360 <= 1'h0; + end else if (buf_wr_en_3) begin + _T_4360 <= buf_write_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4357 <= 1'h0; + end else if (buf_wr_en_2) begin + _T_4357 <= buf_write_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4354 <= 1'h0; + end else if (buf_wr_en_1) begin + _T_4354 <= buf_write_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4351 <= 1'h0; + end else if (buf_wr_en_0) begin + _T_4351 <= buf_write_in[0]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_state_0 <= 3'h0; + end else if (buf_state_en_0) begin + if (_T_3528) begin + if (io_lsu_bus_clk_en) begin + buf_state_0 <= 3'h2; + end else begin + buf_state_0 <= 3'h1; + end + end else if (_T_3551) begin + if (io_dec_tlu_force_halt) begin + buf_state_0 <= 3'h0; + end else begin + buf_state_0 <= 3'h2; + end + end else if (_T_3555) begin + if (io_dec_tlu_force_halt) begin + buf_state_0 <= 3'h0; + end else if (_T_3559) begin + buf_state_0 <= 3'h5; + end else begin + buf_state_0 <= 3'h3; + end + end else if (_T_3589) begin + if (_T_3594) begin + buf_state_0 <= 3'h0; + end else if (_T_3602) begin + buf_state_0 <= 3'h4; + end else if (_T_3630) begin + buf_state_0 <= 3'h5; + end else begin + buf_state_0 <= 3'h6; + end + end else if (_T_3676) begin + if (io_dec_tlu_force_halt) begin + buf_state_0 <= 3'h0; + end else if (_T_3682) begin + buf_state_0 <= 3'h5; + end else begin + buf_state_0 <= 3'h6; + end + end else if (_T_3694) begin + if (io_dec_tlu_force_halt) begin + buf_state_0 <= 3'h0; + end else begin + buf_state_0 <= 3'h6; + end + end else begin + buf_state_0 <= 3'h0; + end + end + end + always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + if (reset) begin + buf_addr_1 <= 32'h0; + end else if (ibuf_drainvec_vld[1]) begin + buf_addr_1 <= ibuf_addr; + end else if (_T_3352) begin + buf_addr_1 <= io_end_addr_r; + end else begin + buf_addr_1 <= io_lsu_addr_r; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_state_1 <= 3'h0; + end else if (buf_state_en_1) begin + if (_T_3721) begin + if (io_lsu_bus_clk_en) begin + buf_state_1 <= 3'h2; + end else begin + buf_state_1 <= 3'h1; + end + end else if (_T_3744) begin + if (io_dec_tlu_force_halt) begin + buf_state_1 <= 3'h0; + end else begin + buf_state_1 <= 3'h2; + end + end else if (_T_3748) begin + if (io_dec_tlu_force_halt) begin + buf_state_1 <= 3'h0; + end else if (_T_3559) begin + buf_state_1 <= 3'h5; + end else begin + buf_state_1 <= 3'h3; + end + end else if (_T_3782) begin + if (_T_3787) begin + buf_state_1 <= 3'h0; + end else if (_T_3795) begin + buf_state_1 <= 3'h4; + end else if (_T_3823) begin + buf_state_1 <= 3'h5; + end else begin + buf_state_1 <= 3'h6; + end + end else if (_T_3869) begin + if (io_dec_tlu_force_halt) begin + buf_state_1 <= 3'h0; + end else if (_T_3875) begin + buf_state_1 <= 3'h5; + end else begin + buf_state_1 <= 3'h6; + end + end else if (_T_3887) begin + if (io_dec_tlu_force_halt) begin + buf_state_1 <= 3'h0; + end else begin + buf_state_1 <= 3'h6; + end + end else begin + buf_state_1 <= 3'h0; + end + end + end + always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin + if (reset) begin + buf_addr_2 <= 32'h0; + end else if (ibuf_drainvec_vld[2]) begin + buf_addr_2 <= ibuf_addr; + end else if (_T_3361) begin + buf_addr_2 <= io_end_addr_r; + end else begin + buf_addr_2 <= io_lsu_addr_r; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_state_2 <= 3'h0; + end else if (buf_state_en_2) begin + if (_T_3914) begin + if (io_lsu_bus_clk_en) begin + buf_state_2 <= 3'h2; + end else begin + buf_state_2 <= 3'h1; + end + end else if (_T_3937) begin + if (io_dec_tlu_force_halt) begin + buf_state_2 <= 3'h0; + end else begin + buf_state_2 <= 3'h2; + end + end else if (_T_3941) begin + if (io_dec_tlu_force_halt) begin + buf_state_2 <= 3'h0; + end else if (_T_3559) begin + buf_state_2 <= 3'h5; + end else begin + buf_state_2 <= 3'h3; + end + end else if (_T_3975) begin + if (_T_3980) begin + buf_state_2 <= 3'h0; + end else if (_T_3988) begin + buf_state_2 <= 3'h4; + end else if (_T_4016) begin + buf_state_2 <= 3'h5; + end else begin + buf_state_2 <= 3'h6; + end + end else if (_T_4062) begin + if (io_dec_tlu_force_halt) begin + buf_state_2 <= 3'h0; + end else if (_T_4068) begin + buf_state_2 <= 3'h5; + end else begin + buf_state_2 <= 3'h6; + end + end else if (_T_4080) begin + if (io_dec_tlu_force_halt) begin + buf_state_2 <= 3'h0; + end else begin + buf_state_2 <= 3'h6; + end + end else begin + buf_state_2 <= 3'h0; + end + end + end + always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin + if (reset) begin + buf_addr_3 <= 32'h0; + end else if (ibuf_drainvec_vld[3]) begin + buf_addr_3 <= ibuf_addr; + end else if (_T_3370) begin + buf_addr_3 <= io_end_addr_r; + end else begin + buf_addr_3 <= io_lsu_addr_r; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_state_3 <= 3'h0; + end else if (buf_state_en_3) begin + if (_T_4107) begin + if (io_lsu_bus_clk_en) begin + buf_state_3 <= 3'h2; + end else begin + buf_state_3 <= 3'h1; + end + end else if (_T_4130) begin + if (io_dec_tlu_force_halt) begin + buf_state_3 <= 3'h0; + end else begin + buf_state_3 <= 3'h2; + end + end else if (_T_4134) begin + if (io_dec_tlu_force_halt) begin + buf_state_3 <= 3'h0; + end else if (_T_3559) begin + buf_state_3 <= 3'h5; + end else begin + buf_state_3 <= 3'h3; + end + end else if (_T_4168) begin + if (_T_4173) begin + buf_state_3 <= 3'h0; + end else if (_T_4181) begin + buf_state_3 <= 3'h4; + end else if (_T_4209) begin + buf_state_3 <= 3'h5; + end else begin + buf_state_3 <= 3'h6; + end + end else if (_T_4255) begin + if (io_dec_tlu_force_halt) begin + buf_state_3 <= 3'h0; + end else if (_T_4261) begin + buf_state_3 <= 3'h5; + end else begin + buf_state_3 <= 3'h6; + end + end else if (_T_4273) begin + if (io_dec_tlu_force_halt) begin + buf_state_3 <= 3'h0; + end else begin + buf_state_3 <= 3'h6; + end + end else begin + buf_state_3 <= 3'h0; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_byteen_3 <= 4'h0; + end else if (buf_wr_en_3) begin + if (ibuf_drainvec_vld[3]) begin + buf_byteen_3 <= ibuf_byteen_out; + end else if (_T_3370) begin + buf_byteen_3 <= ldst_byteen_hi_r; + end else begin + buf_byteen_3 <= ldst_byteen_lo_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_byteen_2 <= 4'h0; + end else if (buf_wr_en_2) begin + if (ibuf_drainvec_vld[2]) begin + buf_byteen_2 <= ibuf_byteen_out; + end else if (_T_3361) begin + buf_byteen_2 <= ldst_byteen_hi_r; + end else begin + buf_byteen_2 <= ldst_byteen_lo_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_byteen_1 <= 4'h0; + end else if (buf_wr_en_1) begin + if (ibuf_drainvec_vld[1]) begin + buf_byteen_1 <= ibuf_byteen_out; + end else if (_T_3352) begin + buf_byteen_1 <= ldst_byteen_hi_r; + end else begin + buf_byteen_1 <= ldst_byteen_lo_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_byteen_0 <= 4'h0; + end else if (buf_wr_en_0) begin + if (ibuf_drainvec_vld[0]) begin + buf_byteen_0 <= ibuf_byteen_out; + end else if (_T_3343) begin + buf_byteen_0 <= ldst_byteen_hi_r; + end else begin + buf_byteen_0 <= ldst_byteen_lo_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ageQ_3 <= 4'h0; + end else begin + buf_ageQ_3 <= {_T_2535,_T_2458}; + end + end + always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin + if (reset) begin + _T_1848 <= 2'h0; + end else if (obuf_wr_en) begin + if (ibuf_buf_byp) begin + _T_1848 <= WrPtr0_r; + end else begin + _T_1848 <= CmdPtr0; + end + end + end + always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin + if (reset) begin + obuf_merge <= 1'h0; + end else if (obuf_wr_en) begin + obuf_merge <= obuf_merge_en; + end + end + always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin + if (reset) begin + obuf_tag1 <= 2'h0; + end else if (obuf_wr_en) begin + if (ibuf_buf_byp) begin + obuf_tag1 <= WrPtr1_r; + end else begin + obuf_tag1 <= CmdPtr1; + end + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + obuf_valid <= 1'h0; + end else begin + obuf_valid <= _T_1839 & _T_1840; + end + end + always @(posedge io_lsu_busm_clk or posedge reset) begin + if (reset) begin + obuf_wr_enQ <= 1'h0; + end else begin + obuf_wr_enQ <= _T_1236 & io_lsu_bus_clk_en; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + if (reset) begin + ibuf_addr <= 32'h0; + end else if (io_ldst_dual_r) begin + ibuf_addr <= io_end_addr_r; + end else begin + ibuf_addr <= io_lsu_addr_r; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_write <= 1'h0; + end else if (ibuf_wr_en) begin + ibuf_write <= io_lsu_pkt_r_bits_store; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + ibuf_valid <= 1'h0; + end else begin + ibuf_valid <= _T_1005 & _T_1006; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_byteen <= 4'h0; + end else if (ibuf_wr_en) begin + if (_T_866) begin + ibuf_byteen <= _T_881; + end else if (io_ldst_dual_r) begin + ibuf_byteen <= ldst_byteen_hi_r; + end else begin + ibuf_byteen <= ldst_byteen_lo_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ageQ_2 <= 4'h0; + end else begin + buf_ageQ_2 <= {_T_2433,_T_2356}; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ageQ_1 <= 4'h0; + end else begin + buf_ageQ_1 <= {_T_2331,_T_2254}; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ageQ_0 <= 4'h0; + end else begin + buf_ageQ_0 <= {_T_2229,_T_2152}; + end + end + always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin + if (reset) begin + buf_data_0 <= 32'h0; + end else if (_T_3528) begin + if (_T_3543) begin + buf_data_0 <= ibuf_data_out; + end else begin + buf_data_0 <= store_data_lo_r; + end + end else if (_T_3551) begin + buf_data_0 <= 32'h0; + end else if (_T_3555) begin + if (buf_error_en_0) begin + buf_data_0 <= io_lsu_axi_r_bits_data[31:0]; + end else if (buf_addr_0[2]) begin + buf_data_0 <= io_lsu_axi_r_bits_data[63:32]; + end else begin + buf_data_0 <= io_lsu_axi_r_bits_data[31:0]; + end + end else if (_T_3589) begin + if (_T_3669) begin + if (buf_addr_0[2]) begin + buf_data_0 <= io_lsu_axi_r_bits_data[63:32]; + end else begin + buf_data_0 <= io_lsu_axi_r_bits_data[31:0]; + end + end else begin + buf_data_0 <= io_lsu_axi_r_bits_data[31:0]; + end + end else begin + buf_data_0 <= 32'h0; + end + end + always @(posedge rvclkhdr_9_io_l1clk or posedge reset) begin + if (reset) begin + buf_data_1 <= 32'h0; + end else if (_T_3721) begin + if (_T_3736) begin + buf_data_1 <= ibuf_data_out; + end else begin + buf_data_1 <= store_data_lo_r; + end + end else if (_T_3744) begin + buf_data_1 <= 32'h0; + end else if (_T_3748) begin + if (buf_error_en_1) begin + buf_data_1 <= io_lsu_axi_r_bits_data[31:0]; + end else if (buf_addr_1[2]) begin + buf_data_1 <= io_lsu_axi_r_bits_data[63:32]; + end else begin + buf_data_1 <= io_lsu_axi_r_bits_data[31:0]; + end + end else if (_T_3782) begin + if (_T_3862) begin + if (buf_addr_1[2]) begin + buf_data_1 <= io_lsu_axi_r_bits_data[63:32]; + end else begin + buf_data_1 <= io_lsu_axi_r_bits_data[31:0]; + end + end else begin + buf_data_1 <= io_lsu_axi_r_bits_data[31:0]; + end + end else begin + buf_data_1 <= 32'h0; + end + end + always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin + if (reset) begin + buf_data_2 <= 32'h0; + end else if (_T_3914) begin + if (_T_3929) begin + buf_data_2 <= ibuf_data_out; + end else begin + buf_data_2 <= store_data_lo_r; + end + end else if (_T_3937) begin + buf_data_2 <= 32'h0; + end else if (_T_3941) begin + if (buf_error_en_2) begin + buf_data_2 <= io_lsu_axi_r_bits_data[31:0]; + end else if (buf_addr_2[2]) begin + buf_data_2 <= io_lsu_axi_r_bits_data[63:32]; + end else begin + buf_data_2 <= io_lsu_axi_r_bits_data[31:0]; + end + end else if (_T_3975) begin + if (_T_4055) begin + if (buf_addr_2[2]) begin + buf_data_2 <= io_lsu_axi_r_bits_data[63:32]; + end else begin + buf_data_2 <= io_lsu_axi_r_bits_data[31:0]; + end + end else begin + buf_data_2 <= io_lsu_axi_r_bits_data[31:0]; + end + end else begin + buf_data_2 <= 32'h0; + end + end + always @(posedge rvclkhdr_11_io_l1clk or posedge reset) begin + if (reset) begin + buf_data_3 <= 32'h0; + end else if (_T_4107) begin + if (_T_4122) begin + buf_data_3 <= ibuf_data_out; + end else begin + buf_data_3 <= store_data_lo_r; + end + end else if (_T_4130) begin + buf_data_3 <= 32'h0; + end else if (_T_4134) begin + if (buf_error_en_3) begin + buf_data_3 <= io_lsu_axi_r_bits_data[31:0]; + end else if (buf_addr_3[2]) begin + buf_data_3 <= io_lsu_axi_r_bits_data[63:32]; + end else begin + buf_data_3 <= io_lsu_axi_r_bits_data[31:0]; + end + end else if (_T_4168) begin + if (_T_4248) begin + if (buf_addr_3[2]) begin + buf_data_3 <= io_lsu_axi_r_bits_data[63:32]; + end else begin + buf_data_3 <= io_lsu_axi_r_bits_data[31:0]; + end + end else begin + buf_data_3 <= io_lsu_axi_r_bits_data[31:0]; + end + end else begin + buf_data_3 <= 32'h0; + end + end + always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin + if (reset) begin + ibuf_data <= 32'h0; + end else begin + ibuf_data <= {_T_922,_T_893}; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + ibuf_timer <= 3'h0; + end else if (ibuf_wr_en) begin + ibuf_timer <= 3'h0; + end else if (_T_923) begin + ibuf_timer <= _T_926; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_sideeffect <= 1'h0; + end else if (ibuf_wr_en) begin + ibuf_sideeffect <= io_is_sideeffects_r; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + WrPtr1_r <= 2'h0; + end else if (_T_1914) begin + WrPtr1_r <= 2'h0; + end else if (_T_1928) begin + WrPtr1_r <= 2'h1; + end else if (_T_1942) begin + WrPtr1_r <= 2'h2; + end else begin + WrPtr1_r <= 2'h3; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + WrPtr0_r <= 2'h0; + end else if (_T_1863) begin + WrPtr0_r <= 2'h0; + end else if (_T_1874) begin + WrPtr0_r <= 2'h1; + end else if (_T_1885) begin + WrPtr0_r <= 2'h2; + end else begin + WrPtr0_r <= 2'h3; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_tag <= 2'h0; + end else if (ibuf_wr_en) begin + if (!(_T_866)) begin + if (io_ldst_dual_r) begin + ibuf_tag <= WrPtr1_r; + end else begin + ibuf_tag <= WrPtr0_r; + end + end + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_dualtag <= 2'h0; + end else if (ibuf_wr_en) begin + ibuf_dualtag <= WrPtr0_r; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_dual <= 1'h0; + end else if (ibuf_wr_en) begin + ibuf_dual <= io_ldst_dual_r; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_samedw <= 1'h0; + end else if (ibuf_wr_en) begin + ibuf_samedw <= ldst_samedw_r; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_nomerge <= 1'h0; + end else if (ibuf_wr_en) begin + ibuf_nomerge <= io_no_dword_merge_r; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_unsign <= 1'h0; + end else if (ibuf_wr_en) begin + ibuf_unsign <= io_lsu_pkt_r_bits_unsign; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_sz <= 2'h0; + end else if (ibuf_wr_en) begin + ibuf_sz <= ibuf_sz_in; + end + end + always @(posedge io_lsu_busm_clk or posedge reset) begin + if (reset) begin + obuf_wr_timer <= 3'h0; + end else if (obuf_wr_en) begin + obuf_wr_timer <= 3'h0; + end else if (_T_1058) begin + obuf_wr_timer <= _T_1060; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_nomerge_0 <= 1'h0; + end else if (buf_wr_en_0) begin + buf_nomerge_0 <= buf_nomerge_in[0]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_nomerge_1 <= 1'h0; + end else if (buf_wr_en_1) begin + buf_nomerge_1 <= buf_nomerge_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_nomerge_2 <= 1'h0; + end else if (buf_wr_en_2) begin + buf_nomerge_2 <= buf_nomerge_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_nomerge_3 <= 1'h0; + end else if (buf_wr_en_3) begin + buf_nomerge_3 <= buf_nomerge_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4330 <= 1'h0; + end else if (buf_wr_en_3) begin + _T_4330 <= buf_sideeffect_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4327 <= 1'h0; + end else if (buf_wr_en_2) begin + _T_4327 <= buf_sideeffect_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4324 <= 1'h0; + end else if (buf_wr_en_1) begin + _T_4324 <= buf_sideeffect_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4321 <= 1'h0; + end else if (buf_wr_en_0) begin + _T_4321 <= buf_sideeffect_in[0]; + end + end + always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin + if (reset) begin + obuf_sideeffect <= 1'h0; + end else if (obuf_wr_en) begin + if (ibuf_buf_byp) begin + obuf_sideeffect <= io_is_sideeffects_r; + end else begin + obuf_sideeffect <= _T_1051; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dual_3 <= 1'h0; + end else if (buf_wr_en_3) begin + buf_dual_3 <= buf_dual_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dual_2 <= 1'h0; + end else if (buf_wr_en_2) begin + buf_dual_2 <= buf_dual_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dual_1 <= 1'h0; + end else if (buf_wr_en_1) begin + buf_dual_1 <= buf_dual_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dual_0 <= 1'h0; + end else if (buf_wr_en_0) begin + buf_dual_0 <= buf_dual_in[0]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_samedw_3 <= 1'h0; + end else if (buf_wr_en_3) begin + buf_samedw_3 <= buf_samedw_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_samedw_2 <= 1'h0; + end else if (buf_wr_en_2) begin + buf_samedw_2 <= buf_samedw_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_samedw_1 <= 1'h0; + end else if (buf_wr_en_1) begin + buf_samedw_1 <= buf_samedw_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_samedw_0 <= 1'h0; + end else if (buf_wr_en_0) begin + buf_samedw_0 <= buf_samedw_in[0]; + end + end + always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin + if (reset) begin + obuf_write <= 1'h0; + end else if (obuf_wr_en) begin + if (ibuf_buf_byp) begin + obuf_write <= io_lsu_pkt_r_bits_store; + end else begin + obuf_write <= _T_1202; + end + end + end + always @(posedge io_lsu_busm_clk or posedge reset) begin + if (reset) begin + obuf_cmd_done <= 1'h0; + end else begin + obuf_cmd_done <= _T_1305 & _T_4863; + end + end + always @(posedge io_lsu_busm_clk or posedge reset) begin + if (reset) begin + obuf_data_done <= 1'h0; + end else begin + obuf_data_done <= _T_1305 & _T_4864; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + obuf_nosend <= 1'h0; + end else if (obuf_wr_en) begin + obuf_nosend <= obuf_nosend_in; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + obuf_addr <= 32'h0; + end else if (ibuf_buf_byp) begin + obuf_addr <= io_lsu_addr_r; + end else begin + obuf_addr <= _T_1289; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_sz_0 <= 2'h0; + end else if (buf_wr_en_0) begin + if (ibuf_drainvec_vld[0]) begin + buf_sz_0 <= ibuf_sz; + end else begin + buf_sz_0 <= ibuf_sz_in; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_sz_1 <= 2'h0; + end else if (buf_wr_en_1) begin + if (ibuf_drainvec_vld[1]) begin + buf_sz_1 <= ibuf_sz; + end else begin + buf_sz_1 <= ibuf_sz_in; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_sz_2 <= 2'h0; + end else if (buf_wr_en_2) begin + if (ibuf_drainvec_vld[2]) begin + buf_sz_2 <= ibuf_sz; + end else begin + buf_sz_2 <= ibuf_sz_in; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_sz_3 <= 2'h0; + end else if (buf_wr_en_3) begin + if (ibuf_drainvec_vld[3]) begin + buf_sz_3 <= ibuf_sz; + end else begin + buf_sz_3 <= ibuf_sz_in; + end + end + end + always @(posedge io_lsu_busm_clk or posedge reset) begin + if (reset) begin + obuf_rdrsp_pend <= 1'h0; + end else begin + obuf_rdrsp_pend <= _T_1330 | _T_1334; + end + end + always @(posedge io_lsu_busm_clk or posedge reset) begin + if (reset) begin + obuf_rdrsp_tag <= 3'h0; + end else if (_T_1332) begin + obuf_rdrsp_tag <= obuf_tag0; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualhi_3 <= 1'h0; + end else if (buf_wr_en_3) begin + buf_dualhi_3 <= buf_dualhi_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualhi_2 <= 1'h0; + end else if (buf_wr_en_2) begin + buf_dualhi_2 <= buf_dualhi_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualhi_1 <= 1'h0; + end else if (buf_wr_en_1) begin + buf_dualhi_1 <= buf_dualhi_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualhi_0 <= 1'h0; + end else if (buf_wr_en_0) begin + buf_dualhi_0 <= buf_dualhi_in[0]; + end + end + always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin + if (reset) begin + obuf_sz <= 2'h0; + end else if (obuf_wr_en) begin + if (ibuf_buf_byp) begin + obuf_sz <= ibuf_sz_in; + end else begin + obuf_sz <= _T_1302; + end + end + end + always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin + if (reset) begin + obuf_byteen <= 8'h0; + end else if (obuf_wr_en) begin + obuf_byteen <= obuf_byteen_in; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + obuf_data <= 64'h0; + end else begin + obuf_data <= {_T_1620,_T_1579}; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_rspageQ_0 <= 4'h0; + end else begin + buf_rspageQ_0 <= {_T_3173,_T_3162}; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_rspageQ_1 <= 4'h0; + end else begin + buf_rspageQ_1 <= {_T_3188,_T_3177}; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_rspageQ_2 <= 4'h0; + end else begin + buf_rspageQ_2 <= {_T_3203,_T_3192}; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_rspageQ_3 <= 4'h0; + end else begin + buf_rspageQ_3 <= {_T_3218,_T_3207}; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4307 <= 1'h0; + end else if (buf_ldfwd_en_3) begin + if (_T_4107) begin + _T_4307 <= 1'h0; + end else if (_T_4130) begin + _T_4307 <= 1'h0; + end else begin + _T_4307 <= _T_4134; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4305 <= 1'h0; + end else if (buf_ldfwd_en_2) begin + if (_T_3914) begin + _T_4305 <= 1'h0; + end else if (_T_3937) begin + _T_4305 <= 1'h0; + end else begin + _T_4305 <= _T_3941; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4303 <= 1'h0; + end else if (buf_ldfwd_en_1) begin + if (_T_3721) begin + _T_4303 <= 1'h0; + end else if (_T_3744) begin + _T_4303 <= 1'h0; + end else begin + _T_4303 <= _T_3748; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4301 <= 1'h0; + end else if (buf_ldfwd_en_0) begin + if (_T_3528) begin + _T_4301 <= 1'h0; + end else if (_T_3551) begin + _T_4301 <= 1'h0; + end else begin + _T_4301 <= _T_3555; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ldfwdtag_0 <= 2'h0; + end else if (buf_ldfwd_en_0) begin + if (_T_3528) begin + buf_ldfwdtag_0 <= 2'h0; + end else if (_T_3551) begin + buf_ldfwdtag_0 <= 2'h0; + end else if (_T_3555) begin + buf_ldfwdtag_0 <= obuf_rdrsp_tag[1:0]; + end else begin + buf_ldfwdtag_0 <= 2'h0; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualtag_0 <= 2'h0; + end else if (buf_wr_en_0) begin + if (ibuf_drainvec_vld[0]) begin + buf_dualtag_0 <= ibuf_dualtag; + end else if (_T_3343) begin + buf_dualtag_0 <= WrPtr0_r; + end else begin + buf_dualtag_0 <= WrPtr1_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ldfwdtag_3 <= 2'h0; + end else if (buf_ldfwd_en_3) begin + if (_T_4107) begin + buf_ldfwdtag_3 <= 2'h0; + end else if (_T_4130) begin + buf_ldfwdtag_3 <= 2'h0; + end else if (_T_4134) begin + buf_ldfwdtag_3 <= obuf_rdrsp_tag[1:0]; + end else begin + buf_ldfwdtag_3 <= 2'h0; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ldfwdtag_2 <= 2'h0; + end else if (buf_ldfwd_en_2) begin + if (_T_3914) begin + buf_ldfwdtag_2 <= 2'h0; + end else if (_T_3937) begin + buf_ldfwdtag_2 <= 2'h0; + end else if (_T_3941) begin + buf_ldfwdtag_2 <= obuf_rdrsp_tag[1:0]; + end else begin + buf_ldfwdtag_2 <= 2'h0; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ldfwdtag_1 <= 2'h0; + end else if (buf_ldfwd_en_1) begin + if (_T_3721) begin + buf_ldfwdtag_1 <= 2'h0; + end else if (_T_3744) begin + buf_ldfwdtag_1 <= 2'h0; + end else if (_T_3748) begin + buf_ldfwdtag_1 <= obuf_rdrsp_tag[1:0]; + end else begin + buf_ldfwdtag_1 <= 2'h0; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualtag_1 <= 2'h0; + end else if (buf_wr_en_1) begin + if (ibuf_drainvec_vld[1]) begin + buf_dualtag_1 <= ibuf_dualtag; + end else if (_T_3352) begin + buf_dualtag_1 <= WrPtr0_r; + end else begin + buf_dualtag_1 <= WrPtr1_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualtag_2 <= 2'h0; + end else if (buf_wr_en_2) begin + if (ibuf_drainvec_vld[2]) begin + buf_dualtag_2 <= ibuf_dualtag; + end else if (_T_3361) begin + buf_dualtag_2 <= WrPtr0_r; + end else begin + buf_dualtag_2 <= WrPtr1_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualtag_3 <= 2'h0; + end else if (buf_wr_en_3) begin + if (ibuf_drainvec_vld[3]) begin + buf_dualtag_3 <= ibuf_dualtag; + end else if (_T_3370) begin + buf_dualtag_3 <= WrPtr0_r; + end else begin + buf_dualtag_3 <= WrPtr1_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4336 <= 1'h0; + end else if (buf_wr_en_0) begin + _T_4336 <= buf_unsign_in[0]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4339 <= 1'h0; + end else if (buf_wr_en_1) begin + _T_4339 <= buf_unsign_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4342 <= 1'h0; + end else if (buf_wr_en_2) begin + _T_4342 <= buf_unsign_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4345 <= 1'h0; + end else if (buf_wr_en_3) begin + _T_4345 <= buf_unsign_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4411 <= 1'h0; + end else begin + _T_4411 <= _T_4408 & _T_4409; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4406 <= 1'h0; + end else begin + _T_4406 <= _T_4403 & _T_4404; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4401 <= 1'h0; + end else begin + _T_4401 <= _T_4398 & _T_4399; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4396 <= 1'h0; + end else begin + _T_4396 <= _T_4393 & _T_4394; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + lsu_nonblock_load_valid_r <= 1'h0; + end else begin + lsu_nonblock_load_valid_r <= io_dctl_busbuff_lsu_nonblock_load_valid_m; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_4987 <= 1'h0; + end else begin + _T_4987 <= _T_4984 & _T_4518; + end + end +endmodule diff --git a/project/project/target/config-classes/$8f8b1ccfdfa3315fc811.class b/project/project/target/config-classes/$8f8b1ccfdfa3315fc811.class deleted file mode 100644 index 32c45951539de56e9cf5bd25689537987d576d0b..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 650 zcmZuv&2HL282r}8F}5M)FHk2CiIl3TT4I?P1rqh(06~qgkVDg6+QZtcjT2*oe_D~J zs(R?5hdw|bqYqMbsnlCmTFp1RvvZi)Uw?l51ON?c2=-b%r)R0Q?aUo~da8CEyQiu= zAOwXw{241g4qRnw-4Q$CfkkkpEW#yGzF?n_x#b095#vA^lK4IeSBjb97)Qz~3bzlG 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b/project/target/scala-2.12/sbt-1.0/update/update_cache_2.12/inputs index 65fd739d..023ab674 100644 --- a/project/target/scala-2.12/sbt-1.0/update/update_cache_2.12/inputs +++ b/project/target/scala-2.12/sbt-1.0/update/update_cache_2.12/inputs @@ -1 +1 @@ -38779017 \ No newline at end of file +-1895719532 \ No newline at end of file diff --git a/project/target/streams/_global/update/_global/streams/out b/project/target/streams/_global/update/_global/streams/out index 973e5828..1ba188cd 100644 --- a/project/target/streams/_global/update/_global/streams/out +++ b/project/target/streams/_global/update/_global/streams/out @@ -1,3 +1,3 @@ [debug] "not up to date. inChanged = true, force = false -[debug] Updating ProjectRef(uri("file:/home/waleedbinehsan/Desktop/Quasar/project/"), "quasar-build")... -[debug] Done updating ProjectRef(uri("file:/home/waleedbinehsan/Desktop/Quasar/project/"), "quasar-build") +[debug] Updating ProjectRef(uri("file:/home/waleedbinehsan/Desktop/Quasar-master/project/"), "quasar-master-build")... +[debug] Done updating ProjectRef(uri("file:/home/waleedbinehsan/Desktop/Quasar-master/project/"), "quasar-master-build") diff --git a/project/target/streams/compile/_global/_global/compileOutputs/previous b/project/target/streams/compile/_global/_global/compileOutputs/previous index e2319964..8ad8608d 100644 --- a/project/target/streams/compile/_global/_global/compileOutputs/previous +++ b/project/target/streams/compile/_global/_global/compileOutputs/previous @@ -1 +1 @@ -["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/waleedbinehsan/Desktop/Quasar/project/target/streams/compile/compileOutputs/_global/streams/inc_compile_2.12.zip"]] \ No newline at end of file +["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/waleedbinehsan/Desktop/Quasar-master/project/target/streams/compile/compileOutputs/_global/streams/inc_compile_2.12.zip"]] \ No newline at end of file diff --git a/project/target/streams/compile/compileIncremental/_global/streams/out b/project/target/streams/compile/compileIncremental/_global/streams/out index 6db8e09d..a24bed6f 100644 --- a/project/target/streams/compile/compileIncremental/_global/streams/out +++ b/project/target/streams/compile/compileIncremental/_global/streams/out @@ -1 +1 @@ -[debug] Full compilation, no sources in previous analysis. +[debug] Full compilation, no sources in previous analysis. diff --git a/project/target/streams/compile/copyResources/_global/streams/out b/project/target/streams/compile/copyResources/_global/streams/out index f25042f2..49995276 100644 --- a/project/target/streams/compile/copyResources/_global/streams/out +++ b/project/target/streams/compile/copyResources/_global/streams/out @@ -1,2 +1,2 @@ -[debug] Copy resource mappings:  -[debug]   +[debug] Copy resource mappings: +[debug] diff --git a/project/target/streams/compile/exportedProducts/_global/streams/export b/project/target/streams/compile/exportedProducts/_global/streams/export index 21b0f701..5f8a3c9f 100644 --- a/project/target/streams/compile/exportedProducts/_global/streams/export +++ b/project/target/streams/compile/exportedProducts/_global/streams/export @@ -1 +1 @@ -/home/waleedbinehsan/Desktop/Quasar/project/target/scala-2.12/sbt-1.0/classes +/home/waleedbinehsan/Desktop/Quasar-master/project/target/scala-2.12/sbt-1.0/classes diff --git a/project/target/streams/runtime/dependencyClasspath/_global/streams/export b/project/target/streams/runtime/dependencyClasspath/_global/streams/export index 098804aa..701f5489 100644 --- a/project/target/streams/runtime/dependencyClasspath/_global/streams/export +++ b/project/target/streams/runtime/dependencyClasspath/_global/streams/export @@ -1 +1 @@ -/home/waleedbinehsan/Desktop/Quasar/project/target/scala-2.12/sbt-1.0/classes:/home/waleedbinehsan/.sbt/1.0/plugins/target/scala-2.12/sbt-1.0/classes +/home/waleedbinehsan/Desktop/Quasar-master/project/target/scala-2.12/sbt-1.0/classes:/home/waleedbinehsan/.sbt/1.0/plugins/target/scala-2.12/sbt-1.0/classes diff --git a/project/target/streams/runtime/exportedProducts/_global/streams/export b/project/target/streams/runtime/exportedProducts/_global/streams/export index 21b0f701..5f8a3c9f 100644 --- a/project/target/streams/runtime/exportedProducts/_global/streams/export +++ b/project/target/streams/runtime/exportedProducts/_global/streams/export @@ -1 +1 @@ -/home/waleedbinehsan/Desktop/Quasar/project/target/scala-2.12/sbt-1.0/classes +/home/waleedbinehsan/Desktop/Quasar-master/project/target/scala-2.12/sbt-1.0/classes diff --git a/project/target/streams/runtime/fullClasspath/_global/streams/export b/project/target/streams/runtime/fullClasspath/_global/streams/export index 098804aa..701f5489 100644 --- a/project/target/streams/runtime/fullClasspath/_global/streams/export +++ b/project/target/streams/runtime/fullClasspath/_global/streams/export @@ -1 +1 @@ -/home/waleedbinehsan/Desktop/Quasar/project/target/scala-2.12/sbt-1.0/classes:/home/waleedbinehsan/.sbt/1.0/plugins/target/scala-2.12/sbt-1.0/classes +/home/waleedbinehsan/Desktop/Quasar-master/project/target/scala-2.12/sbt-1.0/classes:/home/waleedbinehsan/.sbt/1.0/plugins/target/scala-2.12/sbt-1.0/classes diff --git a/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export b/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export index 21b0f701..5f8a3c9f 100644 --- a/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export +++ b/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export @@ -1 +1 @@ -/home/waleedbinehsan/Desktop/Quasar/project/target/scala-2.12/sbt-1.0/classes +/home/waleedbinehsan/Desktop/Quasar-master/project/target/scala-2.12/sbt-1.0/classes diff --git a/quasar_wrapper.anno.json b/quasar_wrapper.anno.json index 7c6bb0c8..50a67c3d 100644 --- a/quasar_wrapper.anno.json +++ b/quasar_wrapper.anno.json @@ -968,10 +968,6 @@ "class":"firrtl.transforms.DontTouchAnnotation", "target":"~quasar_wrapper|exu>i0_rs2_d" }, - { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~quasar_wrapper|dbg>rst_not" - }, { "class":"firrtl.transforms.DontTouchAnnotation", "target":"~quasar_wrapper|dbg>rst_temp" diff --git a/quasar_wrapper.fir b/quasar_wrapper.fir index 04602610..128ec272 100644 --- a/quasar_wrapper.fir +++ b/quasar_wrapper.fir @@ -71689,32 +71689,32 @@ circuit quasar_wrapper : mitcnt1 <= UInt<1>("h00") wire mitcnt0 : UInt<32> mitcnt0 <= UInt<1>("h00") - node mit0_match_ns = geq(mitcnt0, mitb0) @[dec_tlu_ctl.scala 2674:36] - node mit1_match_ns = geq(mitcnt1, mitb1) @[dec_tlu_ctl.scala 2675:36] - io.dec_timer_t0_pulse <= mit0_match_ns @[dec_tlu_ctl.scala 2677:31] - io.dec_timer_t1_pulse <= mit1_match_ns @[dec_tlu_ctl.scala 2678:31] - node _T = eq(io.dec_csr_wraddr_r, UInt<12>("h07d2")) @[dec_tlu_ctl.scala 2685:72] - node wr_mitcnt0_r = and(io.dec_csr_wen_r_mod, _T) @[dec_tlu_ctl.scala 2685:49] - node _T_1 = bits(mitctl0, 0, 0) @[dec_tlu_ctl.scala 2687:37] - node _T_2 = not(io.dec_pause_state) @[dec_tlu_ctl.scala 2687:56] - node _T_3 = bits(mitctl0, 2, 2) @[dec_tlu_ctl.scala 2687:85] - node _T_4 = or(_T_2, _T_3) @[dec_tlu_ctl.scala 2687:76] - node _T_5 = and(_T_1, _T_4) @[dec_tlu_ctl.scala 2687:53] - node _T_6 = not(io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2687:112] - node _T_7 = bits(mitctl0, 1, 1) @[dec_tlu_ctl.scala 2687:147] - node _T_8 = or(_T_6, _T_7) @[dec_tlu_ctl.scala 2687:138] - node _T_9 = and(_T_5, _T_8) @[dec_tlu_ctl.scala 2687:109] - node _T_10 = not(io.internal_dbg_halt_timers) @[dec_tlu_ctl.scala 2687:173] - node mitcnt0_inc_ok = and(_T_9, _T_10) @[dec_tlu_ctl.scala 2687:171] - node _T_11 = add(mitcnt0, UInt<32>("h01")) @[dec_tlu_ctl.scala 2688:35] - node mitcnt0_inc = tail(_T_11, 1) @[dec_tlu_ctl.scala 2688:35] - node _T_12 = bits(mit0_match_ns, 0, 0) @[dec_tlu_ctl.scala 2689:44] - node _T_13 = bits(wr_mitcnt0_r, 0, 0) @[dec_tlu_ctl.scala 2689:74] - node _T_14 = mux(_T_13, io.dec_csr_wrdata_r, mitcnt0_inc) @[dec_tlu_ctl.scala 2689:60] - node mitcnt0_ns = mux(_T_12, UInt<1>("h00"), _T_14) @[dec_tlu_ctl.scala 2689:29] - node _T_15 = or(wr_mitcnt0_r, mitcnt0_inc_ok) @[dec_tlu_ctl.scala 2690:59] - node _T_16 = or(_T_15, mit0_match_ns) @[dec_tlu_ctl.scala 2690:76] - node _T_17 = bits(_T_16, 0, 0) @[dec_tlu_ctl.scala 2690:93] + node mit0_match_ns = geq(mitcnt0, mitb0) @[dec_tlu_ctl.scala 2672:36] + node mit1_match_ns = geq(mitcnt1, mitb1) @[dec_tlu_ctl.scala 2673:36] + io.dec_timer_t0_pulse <= mit0_match_ns @[dec_tlu_ctl.scala 2675:31] + io.dec_timer_t1_pulse <= mit1_match_ns @[dec_tlu_ctl.scala 2676:31] + node _T = eq(io.dec_csr_wraddr_r, UInt<12>("h07d2")) @[dec_tlu_ctl.scala 2683:72] + node wr_mitcnt0_r = and(io.dec_csr_wen_r_mod, _T) @[dec_tlu_ctl.scala 2683:49] + node _T_1 = bits(mitctl0, 0, 0) @[dec_tlu_ctl.scala 2685:37] + node _T_2 = not(io.dec_pause_state) @[dec_tlu_ctl.scala 2685:56] + node _T_3 = bits(mitctl0, 2, 2) @[dec_tlu_ctl.scala 2685:85] + node _T_4 = or(_T_2, _T_3) @[dec_tlu_ctl.scala 2685:76] + node _T_5 = and(_T_1, _T_4) @[dec_tlu_ctl.scala 2685:53] + node _T_6 = not(io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2685:112] + node _T_7 = bits(mitctl0, 1, 1) @[dec_tlu_ctl.scala 2685:147] + node _T_8 = or(_T_6, _T_7) @[dec_tlu_ctl.scala 2685:138] + node _T_9 = and(_T_5, _T_8) @[dec_tlu_ctl.scala 2685:109] + node _T_10 = not(io.internal_dbg_halt_timers) @[dec_tlu_ctl.scala 2685:173] + node mitcnt0_inc_ok = and(_T_9, _T_10) @[dec_tlu_ctl.scala 2685:171] + node _T_11 = add(mitcnt0, UInt<32>("h01")) @[dec_tlu_ctl.scala 2686:35] + node mitcnt0_inc = tail(_T_11, 1) @[dec_tlu_ctl.scala 2686:35] + node _T_12 = bits(mit0_match_ns, 0, 0) @[dec_tlu_ctl.scala 2687:44] + node _T_13 = bits(wr_mitcnt0_r, 0, 0) @[dec_tlu_ctl.scala 2687:74] + node _T_14 = mux(_T_13, io.dec_csr_wrdata_r, mitcnt0_inc) @[dec_tlu_ctl.scala 2687:60] + node mitcnt0_ns = mux(_T_12, UInt<1>("h00"), _T_14) @[dec_tlu_ctl.scala 2687:29] + node _T_15 = or(wr_mitcnt0_r, mitcnt0_inc_ok) @[dec_tlu_ctl.scala 2688:59] + node _T_16 = or(_T_15, mit0_match_ns) @[dec_tlu_ctl.scala 2688:76] + node _T_17 = bits(_T_16, 0, 0) @[dec_tlu_ctl.scala 2688:93] inst rvclkhdr of rvclkhdr_712 @[lib.scala 368:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset @@ -71723,34 +71723,34 @@ circuit quasar_wrapper : rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_18 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_18 <= mitcnt0_ns @[lib.scala 374:16] - mitcnt0 <= _T_18 @[dec_tlu_ctl.scala 2690:25] - node _T_19 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d5")) @[dec_tlu_ctl.scala 2697:72] - node wr_mitcnt1_r = and(io.dec_csr_wen_r_mod, _T_19) @[dec_tlu_ctl.scala 2697:49] - node _T_20 = bits(mitctl1, 0, 0) @[dec_tlu_ctl.scala 2699:37] - node _T_21 = not(io.dec_pause_state) @[dec_tlu_ctl.scala 2699:56] - node _T_22 = bits(mitctl1, 2, 2) @[dec_tlu_ctl.scala 2699:85] - node _T_23 = or(_T_21, _T_22) @[dec_tlu_ctl.scala 2699:76] - node _T_24 = and(_T_20, _T_23) @[dec_tlu_ctl.scala 2699:53] - node _T_25 = not(io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2699:112] - node _T_26 = bits(mitctl1, 1, 1) @[dec_tlu_ctl.scala 2699:147] - node _T_27 = or(_T_25, _T_26) @[dec_tlu_ctl.scala 2699:138] - node _T_28 = and(_T_24, _T_27) @[dec_tlu_ctl.scala 2699:109] - node _T_29 = not(io.internal_dbg_halt_timers) @[dec_tlu_ctl.scala 2699:173] - node mitcnt1_inc_ok = and(_T_28, _T_29) @[dec_tlu_ctl.scala 2699:171] + mitcnt0 <= _T_18 @[dec_tlu_ctl.scala 2688:25] + node _T_19 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d5")) @[dec_tlu_ctl.scala 2695:72] + node wr_mitcnt1_r = and(io.dec_csr_wen_r_mod, _T_19) @[dec_tlu_ctl.scala 2695:49] + node _T_20 = bits(mitctl1, 0, 0) @[dec_tlu_ctl.scala 2697:37] + node _T_21 = not(io.dec_pause_state) @[dec_tlu_ctl.scala 2697:56] + node _T_22 = bits(mitctl1, 2, 2) @[dec_tlu_ctl.scala 2697:85] + node _T_23 = or(_T_21, _T_22) @[dec_tlu_ctl.scala 2697:76] + node _T_24 = and(_T_20, _T_23) @[dec_tlu_ctl.scala 2697:53] + node _T_25 = not(io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2697:112] + node _T_26 = bits(mitctl1, 1, 1) @[dec_tlu_ctl.scala 2697:147] + node _T_27 = or(_T_25, _T_26) @[dec_tlu_ctl.scala 2697:138] + node _T_28 = and(_T_24, _T_27) @[dec_tlu_ctl.scala 2697:109] + node _T_29 = not(io.internal_dbg_halt_timers) @[dec_tlu_ctl.scala 2697:173] + node mitcnt1_inc_ok = and(_T_28, _T_29) @[dec_tlu_ctl.scala 2697:171] node _T_30 = mux(UInt<1>("h00"), UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12] - node _T_31 = bits(mitctl1, 3, 3) @[dec_tlu_ctl.scala 2702:68] - node _T_32 = not(_T_31) @[dec_tlu_ctl.scala 2702:60] - node _T_33 = or(_T_32, mit0_match_ns) @[dec_tlu_ctl.scala 2702:72] + node _T_31 = bits(mitctl1, 3, 3) @[dec_tlu_ctl.scala 2700:68] + node _T_32 = not(_T_31) @[dec_tlu_ctl.scala 2700:60] + node _T_33 = or(_T_32, mit0_match_ns) @[dec_tlu_ctl.scala 2700:72] node _T_34 = cat(_T_30, _T_33) @[Cat.scala 29:58] - node _T_35 = add(mitcnt1, _T_34) @[dec_tlu_ctl.scala 2702:35] - node mitcnt1_inc = tail(_T_35, 1) @[dec_tlu_ctl.scala 2702:35] - node _T_36 = bits(mit1_match_ns, 0, 0) @[dec_tlu_ctl.scala 2703:45] - node _T_37 = bits(wr_mitcnt1_r, 0, 0) @[dec_tlu_ctl.scala 2703:75] - node _T_38 = mux(_T_37, io.dec_csr_wrdata_r, mitcnt1_inc) @[dec_tlu_ctl.scala 2703:61] - node mitcnt1_ns = mux(_T_36, UInt<1>("h00"), _T_38) @[dec_tlu_ctl.scala 2703:30] - node _T_39 = or(wr_mitcnt1_r, mitcnt1_inc_ok) @[dec_tlu_ctl.scala 2704:60] - node _T_40 = or(_T_39, mit1_match_ns) @[dec_tlu_ctl.scala 2704:77] - node _T_41 = bits(_T_40, 0, 0) @[dec_tlu_ctl.scala 2704:94] + node _T_35 = add(mitcnt1, _T_34) @[dec_tlu_ctl.scala 2700:35] + node mitcnt1_inc = tail(_T_35, 1) @[dec_tlu_ctl.scala 2700:35] + node _T_36 = bits(mit1_match_ns, 0, 0) @[dec_tlu_ctl.scala 2701:45] + node _T_37 = bits(wr_mitcnt1_r, 0, 0) @[dec_tlu_ctl.scala 2701:75] + node _T_38 = mux(_T_37, io.dec_csr_wrdata_r, mitcnt1_inc) @[dec_tlu_ctl.scala 2701:61] + node mitcnt1_ns = mux(_T_36, UInt<1>("h00"), _T_38) @[dec_tlu_ctl.scala 2701:30] + node _T_39 = or(wr_mitcnt1_r, mitcnt1_inc_ok) @[dec_tlu_ctl.scala 2702:60] + node _T_40 = or(_T_39, mit1_match_ns) @[dec_tlu_ctl.scala 2702:77] + node _T_41 = bits(_T_40, 0, 0) @[dec_tlu_ctl.scala 2702:94] inst rvclkhdr_1 of rvclkhdr_713 @[lib.scala 368:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset @@ -71759,11 +71759,11 @@ circuit quasar_wrapper : rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_42 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_42 <= mitcnt1_ns @[lib.scala 374:16] - mitcnt1 <= _T_42 @[dec_tlu_ctl.scala 2704:25] - node _T_43 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d3")) @[dec_tlu_ctl.scala 2711:70] - node wr_mitb0_r = and(io.dec_csr_wen_r_mod, _T_43) @[dec_tlu_ctl.scala 2711:47] - node _T_44 = not(io.dec_csr_wrdata_r) @[dec_tlu_ctl.scala 2712:38] - node _T_45 = bits(wr_mitb0_r, 0, 0) @[dec_tlu_ctl.scala 2712:71] + mitcnt1 <= _T_42 @[dec_tlu_ctl.scala 2702:25] + node _T_43 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d3")) @[dec_tlu_ctl.scala 2709:70] + node wr_mitb0_r = and(io.dec_csr_wen_r_mod, _T_43) @[dec_tlu_ctl.scala 2709:47] + node _T_44 = not(io.dec_csr_wrdata_r) @[dec_tlu_ctl.scala 2710:38] + node _T_45 = bits(wr_mitb0_r, 0, 0) @[dec_tlu_ctl.scala 2710:71] inst rvclkhdr_2 of rvclkhdr_714 @[lib.scala 368:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset @@ -71772,12 +71772,12 @@ circuit quasar_wrapper : rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg mitb0_b : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] mitb0_b <= _T_44 @[lib.scala 374:16] - node _T_46 = not(mitb0_b) @[dec_tlu_ctl.scala 2713:22] - mitb0 <= _T_46 @[dec_tlu_ctl.scala 2713:19] - node _T_47 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d6")) @[dec_tlu_ctl.scala 2720:69] - node wr_mitb1_r = and(io.dec_csr_wen_r_mod, _T_47) @[dec_tlu_ctl.scala 2720:47] - node _T_48 = not(io.dec_csr_wrdata_r) @[dec_tlu_ctl.scala 2721:29] - node _T_49 = bits(wr_mitb1_r, 0, 0) @[dec_tlu_ctl.scala 2721:62] + node _T_46 = not(mitb0_b) @[dec_tlu_ctl.scala 2711:22] + mitb0 <= _T_46 @[dec_tlu_ctl.scala 2711:19] + node _T_47 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d6")) @[dec_tlu_ctl.scala 2718:69] + node wr_mitb1_r = and(io.dec_csr_wen_r_mod, _T_47) @[dec_tlu_ctl.scala 2718:47] + node _T_48 = not(io.dec_csr_wrdata_r) @[dec_tlu_ctl.scala 2719:29] + node _T_49 = bits(wr_mitb1_r, 0, 0) @[dec_tlu_ctl.scala 2719:62] inst rvclkhdr_3 of rvclkhdr_715 @[lib.scala 368:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset @@ -71786,55 +71786,55 @@ circuit quasar_wrapper : rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg mitb1_b : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] mitb1_b <= _T_48 @[lib.scala 374:16] - node _T_50 = not(mitb1_b) @[dec_tlu_ctl.scala 2722:18] - mitb1 <= _T_50 @[dec_tlu_ctl.scala 2722:15] - node _T_51 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d4")) @[dec_tlu_ctl.scala 2733:72] - node wr_mitctl0_r = and(io.dec_csr_wen_r_mod, _T_51) @[dec_tlu_ctl.scala 2733:49] - node _T_52 = bits(wr_mitctl0_r, 0, 0) @[dec_tlu_ctl.scala 2734:45] - node _T_53 = bits(io.dec_csr_wrdata_r, 2, 0) @[dec_tlu_ctl.scala 2734:72] - node _T_54 = bits(mitctl0, 2, 0) @[dec_tlu_ctl.scala 2734:86] - node mitctl0_ns = mux(_T_52, _T_53, _T_54) @[dec_tlu_ctl.scala 2734:31] - node _T_55 = bits(mitctl0_ns, 0, 0) @[dec_tlu_ctl.scala 2736:41] - node mitctl0_0_b_ns = not(_T_55) @[dec_tlu_ctl.scala 2736:30] - reg mitctl0_0_b : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2737:60] - mitctl0_0_b <= mitctl0_0_b_ns @[dec_tlu_ctl.scala 2737:60] - node _T_56 = bits(mitctl0_ns, 2, 1) @[dec_tlu_ctl.scala 2738:78] - reg _T_57 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2738:67] - _T_57 <= _T_56 @[dec_tlu_ctl.scala 2738:67] - node _T_58 = not(mitctl0_0_b) @[dec_tlu_ctl.scala 2738:90] + node _T_50 = not(mitb1_b) @[dec_tlu_ctl.scala 2720:18] + mitb1 <= _T_50 @[dec_tlu_ctl.scala 2720:15] + node _T_51 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d4")) @[dec_tlu_ctl.scala 2731:72] + node wr_mitctl0_r = and(io.dec_csr_wen_r_mod, _T_51) @[dec_tlu_ctl.scala 2731:49] + node _T_52 = bits(wr_mitctl0_r, 0, 0) @[dec_tlu_ctl.scala 2732:45] + node _T_53 = bits(io.dec_csr_wrdata_r, 2, 0) @[dec_tlu_ctl.scala 2732:72] + node _T_54 = bits(mitctl0, 2, 0) @[dec_tlu_ctl.scala 2732:86] + node mitctl0_ns = mux(_T_52, _T_53, _T_54) @[dec_tlu_ctl.scala 2732:31] + node _T_55 = bits(mitctl0_ns, 0, 0) @[dec_tlu_ctl.scala 2734:41] + node mitctl0_0_b_ns = not(_T_55) @[dec_tlu_ctl.scala 2734:30] + reg mitctl0_0_b : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2735:60] + mitctl0_0_b <= mitctl0_0_b_ns @[dec_tlu_ctl.scala 2735:60] + node _T_56 = bits(mitctl0_ns, 2, 1) @[dec_tlu_ctl.scala 2736:78] + reg _T_57 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2736:67] + _T_57 <= _T_56 @[dec_tlu_ctl.scala 2736:67] + node _T_58 = not(mitctl0_0_b) @[dec_tlu_ctl.scala 2736:90] node _T_59 = cat(_T_57, _T_58) @[Cat.scala 29:58] - mitctl0 <= _T_59 @[dec_tlu_ctl.scala 2738:31] - node _T_60 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d7")) @[dec_tlu_ctl.scala 2748:71] - node wr_mitctl1_r = and(io.dec_csr_wen_r_mod, _T_60) @[dec_tlu_ctl.scala 2748:49] - node _T_61 = bits(wr_mitctl1_r, 0, 0) @[dec_tlu_ctl.scala 2749:45] - node _T_62 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 2749:71] - node _T_63 = bits(mitctl1, 3, 0) @[dec_tlu_ctl.scala 2749:85] - node mitctl1_ns = mux(_T_61, _T_62, _T_63) @[dec_tlu_ctl.scala 2749:31] - node _T_64 = bits(mitctl1_ns, 0, 0) @[dec_tlu_ctl.scala 2750:40] - node mitctl1_0_b_ns = not(_T_64) @[dec_tlu_ctl.scala 2750:29] - reg mitctl1_0_b : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2751:55] - mitctl1_0_b <= mitctl1_0_b_ns @[dec_tlu_ctl.scala 2751:55] - node _T_65 = bits(mitctl1_ns, 3, 1) @[dec_tlu_ctl.scala 2752:63] - reg _T_66 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2752:52] - _T_66 <= _T_65 @[dec_tlu_ctl.scala 2752:52] - node _T_67 = not(mitctl1_0_b) @[dec_tlu_ctl.scala 2752:75] + mitctl0 <= _T_59 @[dec_tlu_ctl.scala 2736:31] + node _T_60 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d7")) @[dec_tlu_ctl.scala 2746:71] + node wr_mitctl1_r = and(io.dec_csr_wen_r_mod, _T_60) @[dec_tlu_ctl.scala 2746:49] + node _T_61 = bits(wr_mitctl1_r, 0, 0) @[dec_tlu_ctl.scala 2747:45] + node _T_62 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 2747:71] + node _T_63 = bits(mitctl1, 3, 0) @[dec_tlu_ctl.scala 2747:85] + node mitctl1_ns = mux(_T_61, _T_62, _T_63) @[dec_tlu_ctl.scala 2747:31] + node _T_64 = bits(mitctl1_ns, 0, 0) @[dec_tlu_ctl.scala 2748:40] + node mitctl1_0_b_ns = not(_T_64) @[dec_tlu_ctl.scala 2748:29] + reg mitctl1_0_b : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2749:55] + mitctl1_0_b <= mitctl1_0_b_ns @[dec_tlu_ctl.scala 2749:55] + node _T_65 = bits(mitctl1_ns, 3, 1) @[dec_tlu_ctl.scala 2750:63] + reg _T_66 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2750:52] + _T_66 <= _T_65 @[dec_tlu_ctl.scala 2750:52] + node _T_67 = not(mitctl1_0_b) @[dec_tlu_ctl.scala 2750:75] node _T_68 = cat(_T_66, _T_67) @[Cat.scala 29:58] - mitctl1 <= _T_68 @[dec_tlu_ctl.scala 2752:16] - node _T_69 = or(io.csr_mitcnt1, io.csr_mitcnt0) @[dec_tlu_ctl.scala 2754:51] - node _T_70 = or(_T_69, io.csr_mitb1) @[dec_tlu_ctl.scala 2754:68] - node _T_71 = or(_T_70, io.csr_mitb0) @[dec_tlu_ctl.scala 2754:83] - node _T_72 = or(_T_71, io.csr_mitctl0) @[dec_tlu_ctl.scala 2754:98] - node _T_73 = or(_T_72, io.csr_mitctl1) @[dec_tlu_ctl.scala 2754:115] - io.dec_timer_read_d <= _T_73 @[dec_tlu_ctl.scala 2754:33] - node _T_74 = bits(io.csr_mitcnt0, 0, 0) @[dec_tlu_ctl.scala 2756:25] - node _T_75 = bits(mitcnt0, 31, 0) @[dec_tlu_ctl.scala 2756:44] - node _T_76 = bits(io.csr_mitcnt1, 0, 0) @[dec_tlu_ctl.scala 2757:32] - node _T_77 = bits(io.csr_mitb0, 0, 0) @[dec_tlu_ctl.scala 2758:30] - node _T_78 = bits(io.csr_mitb1, 0, 0) @[dec_tlu_ctl.scala 2759:30] - node _T_79 = bits(io.csr_mitctl0, 0, 0) @[dec_tlu_ctl.scala 2760:32] + mitctl1 <= _T_68 @[dec_tlu_ctl.scala 2750:16] + node _T_69 = or(io.csr_mitcnt1, io.csr_mitcnt0) @[dec_tlu_ctl.scala 2752:51] + node _T_70 = or(_T_69, io.csr_mitb1) @[dec_tlu_ctl.scala 2752:68] + node _T_71 = or(_T_70, io.csr_mitb0) @[dec_tlu_ctl.scala 2752:83] + node _T_72 = or(_T_71, io.csr_mitctl0) @[dec_tlu_ctl.scala 2752:98] + node _T_73 = or(_T_72, io.csr_mitctl1) @[dec_tlu_ctl.scala 2752:115] + io.dec_timer_read_d <= _T_73 @[dec_tlu_ctl.scala 2752:33] + node _T_74 = bits(io.csr_mitcnt0, 0, 0) @[dec_tlu_ctl.scala 2754:25] + node _T_75 = bits(mitcnt0, 31, 0) @[dec_tlu_ctl.scala 2754:44] + node _T_76 = bits(io.csr_mitcnt1, 0, 0) @[dec_tlu_ctl.scala 2755:32] + node _T_77 = bits(io.csr_mitb0, 0, 0) @[dec_tlu_ctl.scala 2756:30] + node _T_78 = bits(io.csr_mitb1, 0, 0) @[dec_tlu_ctl.scala 2757:30] + node _T_79 = bits(io.csr_mitctl0, 0, 0) @[dec_tlu_ctl.scala 2758:32] node _T_80 = mux(UInt<1>("h00"), UInt<29>("h01fffffff"), UInt<29>("h00")) @[Bitwise.scala 72:12] node _T_81 = cat(_T_80, mitctl0) @[Cat.scala 29:58] - node _T_82 = bits(io.csr_mitctl1, 0, 0) @[dec_tlu_ctl.scala 2761:32] + node _T_82 = bits(io.csr_mitctl1, 0, 0) @[dec_tlu_ctl.scala 2759:32] node _T_83 = mux(UInt<1>("h00"), UInt<28>("h0fffffff"), UInt<28>("h00")) @[Bitwise.scala 72:12] node _T_84 = cat(_T_83, mitctl1) @[Cat.scala 29:58] node _T_85 = mux(_T_74, _T_75, UInt<1>("h00")) @[Mux.scala 27:72] @@ -71850,7 +71850,7 @@ circuit quasar_wrapper : node _T_95 = or(_T_94, _T_90) @[Mux.scala 27:72] wire _T_96 : UInt<32> @[Mux.scala 27:72] _T_96 <= _T_95 @[Mux.scala 27:72] - io.dec_timer_rddata_d <= _T_96 @[dec_tlu_ctl.scala 2755:33] + io.dec_timer_rddata_d <= _T_96 @[dec_tlu_ctl.scala 2753:33] extmodule gated_latch_716 : output Q : Clock @@ -72833,8 +72833,8 @@ circuit quasar_wrapper : perfcnt_halted <= UInt<1>("h00") wire mhpmc3_incr : UInt<64> mhpmc3_incr <= UInt<1>("h00") - wire mhpme_vec : UInt<10>[4] @[dec_tlu_ctl.scala 1395:41] - wire mtdata2_t : UInt<32>[4] @[dec_tlu_ctl.scala 1396:65] + wire mhpme_vec : UInt<10>[4] @[dec_tlu_ctl.scala 1393:41] + wire mtdata2_t : UInt<32>[4] @[dec_tlu_ctl.scala 1394:65] wire wr_meicpct_r : UInt<1> wr_meicpct_r <= UInt<1>("h00") wire force_halt_ctr_f : UInt<32> @@ -72909,48 +72909,48 @@ circuit quasar_wrapper : mpmc <= UInt<1>("h00") wire dicad1 : UInt<32> dicad1 <= UInt<1>("h00") - node _T = eq(io.i0_trigger_hit_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1451:45] - node _T_1 = and(io.dec_csr_wen_r, _T) @[dec_tlu_ctl.scala 1451:43] - node _T_2 = eq(io.rfpc_i0_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1451:68] - node _T_3 = and(_T_1, _T_2) @[dec_tlu_ctl.scala 1451:66] - io.dec_csr_wen_r_mod <= _T_3 @[dec_tlu_ctl.scala 1451:23] - node _T_4 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1452:64] - node _T_5 = eq(_T_4, UInt<12>("h0300")) @[dec_tlu_ctl.scala 1452:71] - node wr_mstatus_r = and(io.dec_csr_wen_r_mod, _T_5) @[dec_tlu_ctl.scala 1452:42] - node _T_6 = eq(mpmc_b_ns, UInt<1>("h00")) @[dec_tlu_ctl.scala 1455:28] - node set_mie_pmu_fw_halt = and(_T_6, io.fw_halt_req) @[dec_tlu_ctl.scala 1455:39] - node _T_7 = eq(wr_mstatus_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1458:5] - node _T_8 = and(_T_7, io.exc_or_int_valid_r) @[dec_tlu_ctl.scala 1458:19] - node _T_9 = bits(_T_8, 0, 0) @[dec_tlu_ctl.scala 1458:44] - node _T_10 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 1458:68] - node _T_11 = bits(_T_10, 0, 0) @[dec_tlu_ctl.scala 1458:68] + node _T = eq(io.i0_trigger_hit_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1449:45] + node _T_1 = and(io.dec_csr_wen_r, _T) @[dec_tlu_ctl.scala 1449:43] + node _T_2 = eq(io.rfpc_i0_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1449:68] + node _T_3 = and(_T_1, _T_2) @[dec_tlu_ctl.scala 1449:66] + io.dec_csr_wen_r_mod <= _T_3 @[dec_tlu_ctl.scala 1449:23] + node _T_4 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1450:64] + node _T_5 = eq(_T_4, UInt<12>("h0300")) @[dec_tlu_ctl.scala 1450:71] + node wr_mstatus_r = and(io.dec_csr_wen_r_mod, _T_5) @[dec_tlu_ctl.scala 1450:42] + node _T_6 = eq(mpmc_b_ns, UInt<1>("h00")) @[dec_tlu_ctl.scala 1453:28] + node set_mie_pmu_fw_halt = and(_T_6, io.fw_halt_req) @[dec_tlu_ctl.scala 1453:39] + node _T_7 = eq(wr_mstatus_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1456:5] + node _T_8 = and(_T_7, io.exc_or_int_valid_r) @[dec_tlu_ctl.scala 1456:19] + node _T_9 = bits(_T_8, 0, 0) @[dec_tlu_ctl.scala 1456:44] + node _T_10 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 1456:68] + node _T_11 = bits(_T_10, 0, 0) @[dec_tlu_ctl.scala 1456:68] node _T_12 = cat(_T_11, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_13 = and(wr_mstatus_r, io.exc_or_int_valid_r) @[dec_tlu_ctl.scala 1459:18] - node _T_14 = bits(_T_13, 0, 0) @[dec_tlu_ctl.scala 1459:43] - node _T_15 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1459:76] + node _T_13 = and(wr_mstatus_r, io.exc_or_int_valid_r) @[dec_tlu_ctl.scala 1457:18] + node _T_14 = bits(_T_13, 0, 0) @[dec_tlu_ctl.scala 1457:43] + node _T_15 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1457:76] node _T_16 = cat(_T_15, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_17 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1460:17] - node _T_18 = and(io.mret_r, _T_17) @[dec_tlu_ctl.scala 1460:15] - node _T_19 = bits(_T_18, 0, 0) @[dec_tlu_ctl.scala 1460:41] - node _T_20 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 1460:70] + node _T_17 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1458:17] + node _T_18 = and(io.mret_r, _T_17) @[dec_tlu_ctl.scala 1458:15] + node _T_19 = bits(_T_18, 0, 0) @[dec_tlu_ctl.scala 1458:41] + node _T_20 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 1458:70] node _T_21 = cat(UInt<1>("h01"), _T_20) @[Cat.scala 29:58] - node _T_22 = bits(set_mie_pmu_fw_halt, 0, 0) @[dec_tlu_ctl.scala 1461:26] - node _T_23 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 1461:50] + node _T_22 = bits(set_mie_pmu_fw_halt, 0, 0) @[dec_tlu_ctl.scala 1459:26] + node _T_23 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 1459:50] node _T_24 = cat(_T_23, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_25 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1462:20] - node _T_26 = and(wr_mstatus_r, _T_25) @[dec_tlu_ctl.scala 1462:18] - node _T_27 = bits(_T_26, 0, 0) @[dec_tlu_ctl.scala 1462:44] - node _T_28 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1462:77] - node _T_29 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1462:101] + node _T_25 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1460:20] + node _T_26 = and(wr_mstatus_r, _T_25) @[dec_tlu_ctl.scala 1460:18] + node _T_27 = bits(_T_26, 0, 0) @[dec_tlu_ctl.scala 1460:44] + node _T_28 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1460:77] + node _T_29 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1460:101] node _T_30 = cat(_T_28, _T_29) @[Cat.scala 29:58] - node _T_31 = eq(wr_mstatus_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1463:5] - node _T_32 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1463:21] - node _T_33 = and(_T_31, _T_32) @[dec_tlu_ctl.scala 1463:19] - node _T_34 = eq(io.mret_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1463:46] - node _T_35 = and(_T_33, _T_34) @[dec_tlu_ctl.scala 1463:44] - node _T_36 = eq(set_mie_pmu_fw_halt, UInt<1>("h00")) @[dec_tlu_ctl.scala 1463:59] - node _T_37 = and(_T_35, _T_36) @[dec_tlu_ctl.scala 1463:57] - node _T_38 = bits(_T_37, 0, 0) @[dec_tlu_ctl.scala 1463:81] + node _T_31 = eq(wr_mstatus_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1461:5] + node _T_32 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1461:21] + node _T_33 = and(_T_31, _T_32) @[dec_tlu_ctl.scala 1461:19] + node _T_34 = eq(io.mret_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1461:46] + node _T_35 = and(_T_33, _T_34) @[dec_tlu_ctl.scala 1461:44] + node _T_36 = eq(set_mie_pmu_fw_halt, UInt<1>("h00")) @[dec_tlu_ctl.scala 1461:59] + node _T_37 = and(_T_35, _T_36) @[dec_tlu_ctl.scala 1461:57] + node _T_38 = bits(_T_37, 0, 0) @[dec_tlu_ctl.scala 1461:81] node _T_39 = mux(_T_9, _T_12, UInt<1>("h00")) @[Mux.scala 27:72] node _T_40 = mux(_T_14, _T_16, UInt<1>("h00")) @[Mux.scala 27:72] node _T_41 = mux(_T_19, _T_21, UInt<1>("h00")) @[Mux.scala 27:72] @@ -72964,23 +72964,23 @@ circuit quasar_wrapper : node _T_49 = or(_T_48, _T_44) @[Mux.scala 27:72] wire mstatus_ns : UInt<2> @[Mux.scala 27:72] mstatus_ns <= _T_49 @[Mux.scala 27:72] - node _T_50 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 1466:33] - node _T_51 = bits(_T_50, 0, 0) @[dec_tlu_ctl.scala 1466:33] - node _T_52 = not(io.dcsr_single_step_running_f) @[dec_tlu_ctl.scala 1466:50] - node _T_53 = bits(io.dcsr, 11, 11) @[dec_tlu_ctl.scala 1466:90] - node _T_54 = or(_T_52, _T_53) @[dec_tlu_ctl.scala 1466:81] - node _T_55 = and(_T_51, _T_54) @[dec_tlu_ctl.scala 1466:47] - io.mstatus_mie_ns <= _T_55 @[dec_tlu_ctl.scala 1466:20] - reg _T_56 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1468:11] - _T_56 <= mstatus_ns @[dec_tlu_ctl.scala 1468:11] - io.mstatus <= _T_56 @[dec_tlu_ctl.scala 1467:13] - node _T_57 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1477:62] - node _T_58 = eq(_T_57, UInt<12>("h0305")) @[dec_tlu_ctl.scala 1477:69] - node wr_mtvec_r = and(io.dec_csr_wen_r_mod, _T_58) @[dec_tlu_ctl.scala 1477:40] - node _T_59 = bits(io.dec_csr_wrdata_r, 31, 2) @[dec_tlu_ctl.scala 1478:40] - node _T_60 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1478:68] + node _T_50 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 1464:33] + node _T_51 = bits(_T_50, 0, 0) @[dec_tlu_ctl.scala 1464:33] + node _T_52 = not(io.dcsr_single_step_running_f) @[dec_tlu_ctl.scala 1464:50] + node _T_53 = bits(io.dcsr, 11, 11) @[dec_tlu_ctl.scala 1464:90] + node _T_54 = or(_T_52, _T_53) @[dec_tlu_ctl.scala 1464:81] + node _T_55 = and(_T_51, _T_54) @[dec_tlu_ctl.scala 1464:47] + io.mstatus_mie_ns <= _T_55 @[dec_tlu_ctl.scala 1464:20] + reg _T_56 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1466:11] + _T_56 <= mstatus_ns @[dec_tlu_ctl.scala 1466:11] + io.mstatus <= _T_56 @[dec_tlu_ctl.scala 1465:13] + node _T_57 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1475:62] + node _T_58 = eq(_T_57, UInt<12>("h0305")) @[dec_tlu_ctl.scala 1475:69] + node wr_mtvec_r = and(io.dec_csr_wen_r_mod, _T_58) @[dec_tlu_ctl.scala 1475:40] + node _T_59 = bits(io.dec_csr_wrdata_r, 31, 2) @[dec_tlu_ctl.scala 1476:40] + node _T_60 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1476:68] node mtvec_ns = cat(_T_59, _T_60) @[Cat.scala 29:58] - node _T_61 = bits(wr_mtvec_r, 0, 0) @[dec_tlu_ctl.scala 1479:42] + node _T_61 = bits(wr_mtvec_r, 0, 0) @[dec_tlu_ctl.scala 1477:42] inst rvclkhdr of rvclkhdr_720 @[lib.scala 368:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset @@ -72989,57 +72989,57 @@ circuit quasar_wrapper : rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_62 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_62 <= mtvec_ns @[lib.scala 374:16] - io.mtvec <= _T_62 @[dec_tlu_ctl.scala 1479:11] - node _T_63 = or(mdccme_ce_req, miccme_ce_req) @[dec_tlu_ctl.scala 1491:30] - node ce_int = or(_T_63, mice_ce_req) @[dec_tlu_ctl.scala 1491:46] + io.mtvec <= _T_62 @[dec_tlu_ctl.scala 1477:11] + node _T_63 = or(mdccme_ce_req, miccme_ce_req) @[dec_tlu_ctl.scala 1489:30] + node ce_int = or(_T_63, mice_ce_req) @[dec_tlu_ctl.scala 1489:46] node _T_64 = cat(io.mexintpend, io.timer_int_sync) @[Cat.scala 29:58] node _T_65 = cat(_T_64, io.soft_int_sync) @[Cat.scala 29:58] node _T_66 = cat(ce_int, io.dec_timer_t0_pulse) @[Cat.scala 29:58] node _T_67 = cat(_T_66, io.dec_timer_t1_pulse) @[Cat.scala 29:58] node mip_ns = cat(_T_67, _T_65) @[Cat.scala 29:58] - reg _T_68 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1495:11] - _T_68 <= mip_ns @[dec_tlu_ctl.scala 1495:11] - io.mip <= _T_68 @[dec_tlu_ctl.scala 1494:9] - node _T_69 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1507:60] - node _T_70 = eq(_T_69, UInt<12>("h0304")) @[dec_tlu_ctl.scala 1507:67] - node wr_mie_r = and(io.dec_csr_wen_r_mod, _T_70) @[dec_tlu_ctl.scala 1507:38] - node _T_71 = bits(wr_mie_r, 0, 0) @[dec_tlu_ctl.scala 1508:28] - node _T_72 = bits(io.dec_csr_wrdata_r, 30, 28) @[dec_tlu_ctl.scala 1508:59] - node _T_73 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1508:88] - node _T_74 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1508:113] - node _T_75 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1508:137] + reg _T_68 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1493:11] + _T_68 <= mip_ns @[dec_tlu_ctl.scala 1493:11] + io.mip <= _T_68 @[dec_tlu_ctl.scala 1492:9] + node _T_69 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1505:60] + node _T_70 = eq(_T_69, UInt<12>("h0304")) @[dec_tlu_ctl.scala 1505:67] + node wr_mie_r = and(io.dec_csr_wen_r_mod, _T_70) @[dec_tlu_ctl.scala 1505:38] + node _T_71 = bits(wr_mie_r, 0, 0) @[dec_tlu_ctl.scala 1506:28] + node _T_72 = bits(io.dec_csr_wrdata_r, 30, 28) @[dec_tlu_ctl.scala 1506:59] + node _T_73 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1506:88] + node _T_74 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1506:113] + node _T_75 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1506:137] node _T_76 = cat(_T_74, _T_75) @[Cat.scala 29:58] node _T_77 = cat(_T_72, _T_73) @[Cat.scala 29:58] node _T_78 = cat(_T_77, _T_76) @[Cat.scala 29:58] - node _T_79 = mux(_T_71, _T_78, mie) @[dec_tlu_ctl.scala 1508:18] - io.mie_ns <= _T_79 @[dec_tlu_ctl.scala 1508:12] - reg _T_80 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1510:11] - _T_80 <= io.mie_ns @[dec_tlu_ctl.scala 1510:11] - mie <= _T_80 @[dec_tlu_ctl.scala 1509:6] - node _T_81 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 1517:63] - node kill_ebreak_count_r = and(io.ebreak_to_debug_mode_r, _T_81) @[dec_tlu_ctl.scala 1517:54] - node _T_82 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1519:64] - node _T_83 = eq(_T_82, UInt<12>("h0b00")) @[dec_tlu_ctl.scala 1519:71] - node wr_mcyclel_r = and(io.dec_csr_wen_r_mod, _T_83) @[dec_tlu_ctl.scala 1519:42] - node _T_84 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 1521:80] - node _T_85 = and(io.dec_tlu_dbg_halted, _T_84) @[dec_tlu_ctl.scala 1521:71] - node _T_86 = or(kill_ebreak_count_r, _T_85) @[dec_tlu_ctl.scala 1521:46] - node _T_87 = or(_T_86, io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 1521:94] - node _T_88 = bits(mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 1521:136] - node _T_89 = or(_T_87, _T_88) @[dec_tlu_ctl.scala 1521:121] - node mcyclel_cout_in = not(_T_89) @[dec_tlu_ctl.scala 1521:24] + node _T_79 = mux(_T_71, _T_78, mie) @[dec_tlu_ctl.scala 1506:18] + io.mie_ns <= _T_79 @[dec_tlu_ctl.scala 1506:12] + reg _T_80 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1508:11] + _T_80 <= io.mie_ns @[dec_tlu_ctl.scala 1508:11] + mie <= _T_80 @[dec_tlu_ctl.scala 1507:6] + node _T_81 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 1515:63] + node kill_ebreak_count_r = and(io.ebreak_to_debug_mode_r, _T_81) @[dec_tlu_ctl.scala 1515:54] + node _T_82 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1517:64] + node _T_83 = eq(_T_82, UInt<12>("h0b00")) @[dec_tlu_ctl.scala 1517:71] + node wr_mcyclel_r = and(io.dec_csr_wen_r_mod, _T_83) @[dec_tlu_ctl.scala 1517:42] + node _T_84 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 1519:80] + node _T_85 = and(io.dec_tlu_dbg_halted, _T_84) @[dec_tlu_ctl.scala 1519:71] + node _T_86 = or(kill_ebreak_count_r, _T_85) @[dec_tlu_ctl.scala 1519:46] + node _T_87 = or(_T_86, io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 1519:94] + node _T_88 = bits(mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 1519:136] + node _T_89 = or(_T_87, _T_88) @[dec_tlu_ctl.scala 1519:121] + node mcyclel_cout_in = not(_T_89) @[dec_tlu_ctl.scala 1519:24] wire mcyclel_inc : UInt<33> mcyclel_inc <= UInt<1>("h00") node _T_90 = cat(UInt<31>("h00"), mcyclel_cout_in) @[Cat.scala 29:58] - node _T_91 = add(mcyclel, _T_90) @[dec_tlu_ctl.scala 1525:25] - mcyclel_inc <= _T_91 @[dec_tlu_ctl.scala 1525:14] - node _T_92 = bits(wr_mcyclel_r, 0, 0) @[dec_tlu_ctl.scala 1526:36] - node _T_93 = bits(mcyclel_inc, 31, 0) @[dec_tlu_ctl.scala 1526:76] - node mcyclel_ns = mux(_T_92, io.dec_csr_wrdata_r, _T_93) @[dec_tlu_ctl.scala 1526:22] - node _T_94 = bits(mcyclel_inc, 32, 32) @[dec_tlu_ctl.scala 1527:32] - node mcyclel_cout = bits(_T_94, 0, 0) @[dec_tlu_ctl.scala 1527:37] - node _T_95 = or(wr_mcyclel_r, mcyclel_cout_in) @[dec_tlu_ctl.scala 1528:46] - node _T_96 = bits(_T_95, 0, 0) @[dec_tlu_ctl.scala 1528:72] + node _T_91 = add(mcyclel, _T_90) @[dec_tlu_ctl.scala 1523:25] + mcyclel_inc <= _T_91 @[dec_tlu_ctl.scala 1523:14] + node _T_92 = bits(wr_mcyclel_r, 0, 0) @[dec_tlu_ctl.scala 1524:36] + node _T_93 = bits(mcyclel_inc, 31, 0) @[dec_tlu_ctl.scala 1524:76] + node mcyclel_ns = mux(_T_92, io.dec_csr_wrdata_r, _T_93) @[dec_tlu_ctl.scala 1524:22] + node _T_94 = bits(mcyclel_inc, 32, 32) @[dec_tlu_ctl.scala 1525:32] + node mcyclel_cout = bits(_T_94, 0, 0) @[dec_tlu_ctl.scala 1525:37] + node _T_95 = or(wr_mcyclel_r, mcyclel_cout_in) @[dec_tlu_ctl.scala 1526:46] + node _T_96 = bits(_T_95, 0, 0) @[dec_tlu_ctl.scala 1526:72] inst rvclkhdr_1 of rvclkhdr_721 @[lib.scala 368:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset @@ -73048,22 +73048,22 @@ circuit quasar_wrapper : rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_97 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_97 <= mcyclel_ns @[lib.scala 374:16] - mcyclel <= _T_97 @[dec_tlu_ctl.scala 1528:10] - node _T_98 = eq(wr_mcycleh_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1529:71] - node _T_99 = and(mcyclel_cout, _T_98) @[dec_tlu_ctl.scala 1529:69] - reg mcyclel_cout_f : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1529:54] - mcyclel_cout_f <= _T_99 @[dec_tlu_ctl.scala 1529:54] - node _T_100 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1535:61] - node _T_101 = eq(_T_100, UInt<12>("h0b80")) @[dec_tlu_ctl.scala 1535:68] - node _T_102 = and(io.dec_csr_wen_r_mod, _T_101) @[dec_tlu_ctl.scala 1535:39] - wr_mcycleh_r <= _T_102 @[dec_tlu_ctl.scala 1535:15] + mcyclel <= _T_97 @[dec_tlu_ctl.scala 1526:10] + node _T_98 = eq(wr_mcycleh_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1527:71] + node _T_99 = and(mcyclel_cout, _T_98) @[dec_tlu_ctl.scala 1527:69] + reg mcyclel_cout_f : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1527:54] + mcyclel_cout_f <= _T_99 @[dec_tlu_ctl.scala 1527:54] + node _T_100 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1533:61] + node _T_101 = eq(_T_100, UInt<12>("h0b80")) @[dec_tlu_ctl.scala 1533:68] + node _T_102 = and(io.dec_csr_wen_r_mod, _T_101) @[dec_tlu_ctl.scala 1533:39] + wr_mcycleh_r <= _T_102 @[dec_tlu_ctl.scala 1533:15] node _T_103 = cat(UInt<31>("h00"), mcyclel_cout_f) @[Cat.scala 29:58] - node _T_104 = add(mcycleh, _T_103) @[dec_tlu_ctl.scala 1537:28] - node mcycleh_inc = tail(_T_104, 1) @[dec_tlu_ctl.scala 1537:28] - node _T_105 = bits(wr_mcycleh_r, 0, 0) @[dec_tlu_ctl.scala 1538:36] - node mcycleh_ns = mux(_T_105, io.dec_csr_wrdata_r, mcycleh_inc) @[dec_tlu_ctl.scala 1538:22] - node _T_106 = or(wr_mcycleh_r, mcyclel_cout_f) @[dec_tlu_ctl.scala 1540:46] - node _T_107 = bits(_T_106, 0, 0) @[dec_tlu_ctl.scala 1540:64] + node _T_104 = add(mcycleh, _T_103) @[dec_tlu_ctl.scala 1535:28] + node mcycleh_inc = tail(_T_104, 1) @[dec_tlu_ctl.scala 1535:28] + node _T_105 = bits(wr_mcycleh_r, 0, 0) @[dec_tlu_ctl.scala 1536:36] + node mcycleh_ns = mux(_T_105, io.dec_csr_wrdata_r, mcycleh_inc) @[dec_tlu_ctl.scala 1536:22] + node _T_106 = or(wr_mcycleh_r, mcyclel_cout_f) @[dec_tlu_ctl.scala 1538:46] + node _T_107 = bits(_T_106, 0, 0) @[dec_tlu_ctl.scala 1538:64] inst rvclkhdr_2 of rvclkhdr_722 @[lib.scala 368:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset @@ -73072,28 +73072,28 @@ circuit quasar_wrapper : rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_108 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_108 <= mcycleh_ns @[lib.scala 374:16] - mcycleh <= _T_108 @[dec_tlu_ctl.scala 1540:10] - node _T_109 = or(io.ebreak_r, io.ecall_r) @[dec_tlu_ctl.scala 1554:72] - node _T_110 = or(_T_109, io.ebreak_to_debug_mode_r) @[dec_tlu_ctl.scala 1554:85] - node _T_111 = or(_T_110, io.illegal_r) @[dec_tlu_ctl.scala 1554:113] - node _T_112 = bits(mcountinhibit, 2, 2) @[dec_tlu_ctl.scala 1554:143] - node _T_113 = or(_T_111, _T_112) @[dec_tlu_ctl.scala 1554:128] - node _T_114 = bits(_T_113, 0, 0) @[dec_tlu_ctl.scala 1554:148] - node _T_115 = not(_T_114) @[dec_tlu_ctl.scala 1554:58] - node i0_valid_no_ebreak_ecall_r = and(io.tlu_i0_commit_cmt, _T_115) @[dec_tlu_ctl.scala 1554:56] - node _T_116 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1556:66] - node _T_117 = eq(_T_116, UInt<12>("h0b02")) @[dec_tlu_ctl.scala 1556:73] - node wr_minstretl_r = and(io.dec_csr_wen_r_mod, _T_117) @[dec_tlu_ctl.scala 1556:44] + mcycleh <= _T_108 @[dec_tlu_ctl.scala 1538:10] + node _T_109 = or(io.ebreak_r, io.ecall_r) @[dec_tlu_ctl.scala 1552:72] + node _T_110 = or(_T_109, io.ebreak_to_debug_mode_r) @[dec_tlu_ctl.scala 1552:85] + node _T_111 = or(_T_110, io.illegal_r) @[dec_tlu_ctl.scala 1552:113] + node _T_112 = bits(mcountinhibit, 2, 2) @[dec_tlu_ctl.scala 1552:143] + node _T_113 = or(_T_111, _T_112) @[dec_tlu_ctl.scala 1552:128] + node _T_114 = bits(_T_113, 0, 0) @[dec_tlu_ctl.scala 1552:148] + node _T_115 = not(_T_114) @[dec_tlu_ctl.scala 1552:58] + node i0_valid_no_ebreak_ecall_r = and(io.tlu_i0_commit_cmt, _T_115) @[dec_tlu_ctl.scala 1552:56] + node _T_116 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1554:66] + node _T_117 = eq(_T_116, UInt<12>("h0b02")) @[dec_tlu_ctl.scala 1554:73] + node wr_minstretl_r = and(io.dec_csr_wen_r_mod, _T_117) @[dec_tlu_ctl.scala 1554:44] node _T_118 = cat(UInt<31>("h00"), i0_valid_no_ebreak_ecall_r) @[Cat.scala 29:58] - node _T_119 = add(minstretl, _T_118) @[dec_tlu_ctl.scala 1558:29] - minstretl_inc <= _T_119 @[dec_tlu_ctl.scala 1558:16] - node minstretl_cout = bits(minstretl_inc, 32, 32) @[dec_tlu_ctl.scala 1559:36] - node _T_120 = or(i0_valid_no_ebreak_ecall_r, wr_minstretl_r) @[dec_tlu_ctl.scala 1560:52] - node minstret_enable = bits(_T_120, 0, 0) @[dec_tlu_ctl.scala 1560:70] - node _T_121 = bits(wr_minstretl_r, 0, 0) @[dec_tlu_ctl.scala 1562:40] - node _T_122 = bits(minstretl_inc, 31, 0) @[dec_tlu_ctl.scala 1562:83] - node minstretl_ns = mux(_T_121, io.dec_csr_wrdata_r, _T_122) @[dec_tlu_ctl.scala 1562:24] - node _T_123 = bits(minstret_enable, 0, 0) @[dec_tlu_ctl.scala 1563:51] + node _T_119 = add(minstretl, _T_118) @[dec_tlu_ctl.scala 1556:29] + minstretl_inc <= _T_119 @[dec_tlu_ctl.scala 1556:16] + node minstretl_cout = bits(minstretl_inc, 32, 32) @[dec_tlu_ctl.scala 1557:36] + node _T_120 = or(i0_valid_no_ebreak_ecall_r, wr_minstretl_r) @[dec_tlu_ctl.scala 1558:52] + node minstret_enable = bits(_T_120, 0, 0) @[dec_tlu_ctl.scala 1558:70] + node _T_121 = bits(wr_minstretl_r, 0, 0) @[dec_tlu_ctl.scala 1560:40] + node _T_122 = bits(minstretl_inc, 31, 0) @[dec_tlu_ctl.scala 1560:83] + node minstretl_ns = mux(_T_121, io.dec_csr_wrdata_r, _T_122) @[dec_tlu_ctl.scala 1560:24] + node _T_123 = bits(minstret_enable, 0, 0) @[dec_tlu_ctl.scala 1561:51] inst rvclkhdr_3 of rvclkhdr_723 @[lib.scala 368:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset @@ -73102,26 +73102,26 @@ circuit quasar_wrapper : rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_124 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_124 <= minstretl_ns @[lib.scala 374:16] - minstretl <= _T_124 @[dec_tlu_ctl.scala 1563:12] - reg minstret_enable_f : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1564:56] - minstret_enable_f <= minstret_enable @[dec_tlu_ctl.scala 1564:56] - node _T_125 = not(wr_minstreth_r) @[dec_tlu_ctl.scala 1565:75] - node _T_126 = and(minstretl_cout, _T_125) @[dec_tlu_ctl.scala 1565:73] - reg minstretl_cout_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1565:56] - minstretl_cout_f <= _T_126 @[dec_tlu_ctl.scala 1565:56] - node _T_127 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1573:64] - node _T_128 = eq(_T_127, UInt<12>("h0b82")) @[dec_tlu_ctl.scala 1573:71] - node _T_129 = and(io.dec_csr_wen_r_mod, _T_128) @[dec_tlu_ctl.scala 1573:42] - node _T_130 = bits(_T_129, 0, 0) @[dec_tlu_ctl.scala 1573:87] - wr_minstreth_r <= _T_130 @[dec_tlu_ctl.scala 1573:17] + minstretl <= _T_124 @[dec_tlu_ctl.scala 1561:12] + reg minstret_enable_f : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1562:56] + minstret_enable_f <= minstret_enable @[dec_tlu_ctl.scala 1562:56] + node _T_125 = not(wr_minstreth_r) @[dec_tlu_ctl.scala 1563:75] + node _T_126 = and(minstretl_cout, _T_125) @[dec_tlu_ctl.scala 1563:73] + reg minstretl_cout_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1563:56] + minstretl_cout_f <= _T_126 @[dec_tlu_ctl.scala 1563:56] + node _T_127 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1571:64] + node _T_128 = eq(_T_127, UInt<12>("h0b82")) @[dec_tlu_ctl.scala 1571:71] + node _T_129 = and(io.dec_csr_wen_r_mod, _T_128) @[dec_tlu_ctl.scala 1571:42] + node _T_130 = bits(_T_129, 0, 0) @[dec_tlu_ctl.scala 1571:87] + wr_minstreth_r <= _T_130 @[dec_tlu_ctl.scala 1571:17] node _T_131 = cat(UInt<31>("h00"), minstretl_cout_f) @[Cat.scala 29:58] - node _T_132 = add(minstreth, _T_131) @[dec_tlu_ctl.scala 1576:29] - node _T_133 = tail(_T_132, 1) @[dec_tlu_ctl.scala 1576:29] - minstreth_inc <= _T_133 @[dec_tlu_ctl.scala 1576:16] - node _T_134 = bits(wr_minstreth_r, 0, 0) @[dec_tlu_ctl.scala 1577:41] - node minstreth_ns = mux(_T_134, io.dec_csr_wrdata_r, minstreth_inc) @[dec_tlu_ctl.scala 1577:25] - node _T_135 = or(minstret_enable_f, wr_minstreth_r) @[dec_tlu_ctl.scala 1579:55] - node _T_136 = bits(_T_135, 0, 0) @[dec_tlu_ctl.scala 1579:73] + node _T_132 = add(minstreth, _T_131) @[dec_tlu_ctl.scala 1574:29] + node _T_133 = tail(_T_132, 1) @[dec_tlu_ctl.scala 1574:29] + minstreth_inc <= _T_133 @[dec_tlu_ctl.scala 1574:16] + node _T_134 = bits(wr_minstreth_r, 0, 0) @[dec_tlu_ctl.scala 1575:41] + node minstreth_ns = mux(_T_134, io.dec_csr_wrdata_r, minstreth_inc) @[dec_tlu_ctl.scala 1575:25] + node _T_135 = or(minstret_enable_f, wr_minstreth_r) @[dec_tlu_ctl.scala 1577:55] + node _T_136 = bits(_T_135, 0, 0) @[dec_tlu_ctl.scala 1577:73] inst rvclkhdr_4 of rvclkhdr_724 @[lib.scala 368:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset @@ -73130,11 +73130,11 @@ circuit quasar_wrapper : rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_137 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_137 <= minstreth_ns @[lib.scala 374:16] - minstreth <= _T_137 @[dec_tlu_ctl.scala 1579:12] - node _T_138 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1587:65] - node _T_139 = eq(_T_138, UInt<12>("h0340")) @[dec_tlu_ctl.scala 1587:72] - node wr_mscratch_r = and(io.dec_csr_wen_r_mod, _T_139) @[dec_tlu_ctl.scala 1587:43] - node _T_140 = bits(wr_mscratch_r, 0, 0) @[dec_tlu_ctl.scala 1589:55] + minstreth <= _T_137 @[dec_tlu_ctl.scala 1577:12] + node _T_138 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1585:65] + node _T_139 = eq(_T_138, UInt<12>("h0340")) @[dec_tlu_ctl.scala 1585:72] + node wr_mscratch_r = and(io.dec_csr_wen_r_mod, _T_139) @[dec_tlu_ctl.scala 1585:43] + node _T_140 = bits(wr_mscratch_r, 0, 0) @[dec_tlu_ctl.scala 1587:55] inst rvclkhdr_5 of rvclkhdr_725 @[lib.scala 368:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset @@ -73143,24 +73143,24 @@ circuit quasar_wrapper : rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_141 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_141 <= io.dec_csr_wrdata_r @[lib.scala 374:16] - mscratch <= _T_141 @[dec_tlu_ctl.scala 1589:11] - node _T_142 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[dec_tlu_ctl.scala 1598:22] - node _T_143 = eq(io.tlu_flush_lower_r_d1, UInt<1>("h00")) @[dec_tlu_ctl.scala 1598:47] - node _T_144 = and(_T_142, _T_143) @[dec_tlu_ctl.scala 1598:45] - node sel_exu_npc_r = and(_T_144, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 1598:72] - node _T_145 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[dec_tlu_ctl.scala 1599:24] - node _T_146 = and(_T_145, io.tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 1599:47] - node _T_147 = eq(io.dec_tlu_flush_noredir_r_d1, UInt<1>("h00")) @[dec_tlu_ctl.scala 1599:75] - node sel_flush_npc_r = and(_T_146, _T_147) @[dec_tlu_ctl.scala 1599:73] - node _T_148 = eq(sel_exu_npc_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1600:23] - node _T_149 = eq(sel_flush_npc_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1600:40] - node sel_hold_npc_r = and(_T_148, _T_149) @[dec_tlu_ctl.scala 1600:38] - node _T_150 = bits(sel_exu_npc_r, 0, 0) @[dec_tlu_ctl.scala 1603:26] - node _T_151 = eq(io.mpc_reset_run_req, UInt<1>("h00")) @[dec_tlu_ctl.scala 1604:13] - node _T_152 = and(_T_151, io.reset_delayed) @[dec_tlu_ctl.scala 1604:35] - node _T_153 = bits(_T_152, 0, 0) @[dec_tlu_ctl.scala 1604:55] - node _T_154 = bits(sel_flush_npc_r, 0, 0) @[dec_tlu_ctl.scala 1605:28] - node _T_155 = bits(sel_hold_npc_r, 0, 0) @[dec_tlu_ctl.scala 1606:27] + mscratch <= _T_141 @[dec_tlu_ctl.scala 1587:11] + node _T_142 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[dec_tlu_ctl.scala 1596:22] + node _T_143 = eq(io.tlu_flush_lower_r_d1, UInt<1>("h00")) @[dec_tlu_ctl.scala 1596:47] + node _T_144 = and(_T_142, _T_143) @[dec_tlu_ctl.scala 1596:45] + node sel_exu_npc_r = and(_T_144, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 1596:72] + node _T_145 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[dec_tlu_ctl.scala 1597:24] + node _T_146 = and(_T_145, io.tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 1597:47] + node _T_147 = eq(io.dec_tlu_flush_noredir_r_d1, UInt<1>("h00")) @[dec_tlu_ctl.scala 1597:75] + node sel_flush_npc_r = and(_T_146, _T_147) @[dec_tlu_ctl.scala 1597:73] + node _T_148 = eq(sel_exu_npc_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1598:23] + node _T_149 = eq(sel_flush_npc_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1598:40] + node sel_hold_npc_r = and(_T_148, _T_149) @[dec_tlu_ctl.scala 1598:38] + node _T_150 = bits(sel_exu_npc_r, 0, 0) @[dec_tlu_ctl.scala 1601:26] + node _T_151 = eq(io.mpc_reset_run_req, UInt<1>("h00")) @[dec_tlu_ctl.scala 1602:13] + node _T_152 = and(_T_151, io.reset_delayed) @[dec_tlu_ctl.scala 1602:35] + node _T_153 = bits(_T_152, 0, 0) @[dec_tlu_ctl.scala 1602:55] + node _T_154 = bits(sel_flush_npc_r, 0, 0) @[dec_tlu_ctl.scala 1603:28] + node _T_155 = bits(sel_hold_npc_r, 0, 0) @[dec_tlu_ctl.scala 1604:27] node _T_156 = mux(_T_150, io.exu_npc_r, UInt<1>("h00")) @[Mux.scala 27:72] node _T_157 = mux(_T_153, io.rst_vec, UInt<1>("h00")) @[Mux.scala 27:72] node _T_158 = mux(_T_154, io.tlu_flush_path_r_d1, UInt<1>("h00")) @[Mux.scala 27:72] @@ -73170,10 +73170,10 @@ circuit quasar_wrapper : node _T_162 = or(_T_161, _T_159) @[Mux.scala 27:72] wire _T_163 : UInt<31> @[Mux.scala 27:72] _T_163 <= _T_162 @[Mux.scala 27:72] - io.npc_r <= _T_163 @[dec_tlu_ctl.scala 1602:11] - node _T_164 = or(sel_exu_npc_r, sel_flush_npc_r) @[dec_tlu_ctl.scala 1608:48] - node _T_165 = or(_T_164, io.reset_delayed) @[dec_tlu_ctl.scala 1608:66] - node _T_166 = bits(_T_165, 0, 0) @[dec_tlu_ctl.scala 1608:86] + io.npc_r <= _T_163 @[dec_tlu_ctl.scala 1600:11] + node _T_164 = or(sel_exu_npc_r, sel_flush_npc_r) @[dec_tlu_ctl.scala 1606:48] + node _T_165 = or(_T_164, io.reset_delayed) @[dec_tlu_ctl.scala 1606:66] + node _T_166 = bits(_T_165, 0, 0) @[dec_tlu_ctl.scala 1606:86] inst rvclkhdr_6 of rvclkhdr_726 @[lib.scala 368:23] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset @@ -73182,11 +73182,11 @@ circuit quasar_wrapper : rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_167 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_167 <= io.npc_r @[lib.scala 374:16] - io.npc_r_d1 <= _T_167 @[dec_tlu_ctl.scala 1608:14] - node _T_168 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[dec_tlu_ctl.scala 1611:21] - node _T_169 = and(_T_168, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 1611:44] - node pc0_valid_r = bits(_T_169, 0, 0) @[dec_tlu_ctl.scala 1611:69] - node _T_170 = not(pc0_valid_r) @[dec_tlu_ctl.scala 1615:22] + io.npc_r_d1 <= _T_167 @[dec_tlu_ctl.scala 1606:14] + node _T_168 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[dec_tlu_ctl.scala 1609:21] + node _T_169 = and(_T_168, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 1609:44] + node pc0_valid_r = bits(_T_169, 0, 0) @[dec_tlu_ctl.scala 1609:69] + node _T_170 = not(pc0_valid_r) @[dec_tlu_ctl.scala 1613:22] node _T_171 = mux(pc0_valid_r, io.dec_tlu_i0_pc_r, UInt<1>("h00")) @[Mux.scala 27:72] node _T_172 = mux(_T_170, pc_r_d1, UInt<1>("h00")) @[Mux.scala 27:72] node _T_173 = or(_T_171, _T_172) @[Mux.scala 27:72] @@ -73200,22 +73200,22 @@ circuit quasar_wrapper : rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_174 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_174 <= pc_r @[lib.scala 374:16] - pc_r_d1 <= _T_174 @[dec_tlu_ctl.scala 1617:10] - node _T_175 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1619:61] - node _T_176 = eq(_T_175, UInt<12>("h0341")) @[dec_tlu_ctl.scala 1619:68] - node wr_mepc_r = and(io.dec_csr_wen_r_mod, _T_176) @[dec_tlu_ctl.scala 1619:39] - node _T_177 = or(io.i0_exception_valid_r, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 1622:27] - node _T_178 = or(_T_177, io.mepc_trigger_hit_sel_pc_r) @[dec_tlu_ctl.scala 1622:48] - node _T_179 = bits(_T_178, 0, 0) @[dec_tlu_ctl.scala 1622:80] - node _T_180 = bits(io.interrupt_valid_r, 0, 0) @[dec_tlu_ctl.scala 1623:25] - node _T_181 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1624:15] - node _T_182 = and(wr_mepc_r, _T_181) @[dec_tlu_ctl.scala 1624:13] - node _T_183 = bits(_T_182, 0, 0) @[dec_tlu_ctl.scala 1624:39] - node _T_184 = bits(io.dec_csr_wrdata_r, 31, 1) @[dec_tlu_ctl.scala 1624:104] - node _T_185 = eq(wr_mepc_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1625:3] - node _T_186 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1625:16] - node _T_187 = and(_T_185, _T_186) @[dec_tlu_ctl.scala 1625:14] - node _T_188 = bits(_T_187, 0, 0) @[dec_tlu_ctl.scala 1625:40] + pc_r_d1 <= _T_174 @[dec_tlu_ctl.scala 1615:10] + node _T_175 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1617:61] + node _T_176 = eq(_T_175, UInt<12>("h0341")) @[dec_tlu_ctl.scala 1617:68] + node wr_mepc_r = and(io.dec_csr_wen_r_mod, _T_176) @[dec_tlu_ctl.scala 1617:39] + node _T_177 = or(io.i0_exception_valid_r, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 1620:27] + node _T_178 = or(_T_177, io.mepc_trigger_hit_sel_pc_r) @[dec_tlu_ctl.scala 1620:48] + node _T_179 = bits(_T_178, 0, 0) @[dec_tlu_ctl.scala 1620:80] + node _T_180 = bits(io.interrupt_valid_r, 0, 0) @[dec_tlu_ctl.scala 1621:25] + node _T_181 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1622:15] + node _T_182 = and(wr_mepc_r, _T_181) @[dec_tlu_ctl.scala 1622:13] + node _T_183 = bits(_T_182, 0, 0) @[dec_tlu_ctl.scala 1622:39] + node _T_184 = bits(io.dec_csr_wrdata_r, 31, 1) @[dec_tlu_ctl.scala 1622:104] + node _T_185 = eq(wr_mepc_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1623:3] + node _T_186 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1623:16] + node _T_187 = and(_T_185, _T_186) @[dec_tlu_ctl.scala 1623:14] + node _T_188 = bits(_T_187, 0, 0) @[dec_tlu_ctl.scala 1623:40] node _T_189 = mux(_T_179, pc_r, UInt<1>("h00")) @[Mux.scala 27:72] node _T_190 = mux(_T_180, io.npc_r, UInt<1>("h00")) @[Mux.scala 27:72] node _T_191 = mux(_T_183, _T_184, UInt<1>("h00")) @[Mux.scala 27:72] @@ -73225,42 +73225,42 @@ circuit quasar_wrapper : node _T_195 = or(_T_194, _T_192) @[Mux.scala 27:72] wire mepc_ns : UInt<31> @[Mux.scala 27:72] mepc_ns <= _T_195 @[Mux.scala 27:72] - reg _T_196 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1627:47] - _T_196 <= mepc_ns @[dec_tlu_ctl.scala 1627:47] - io.mepc <= _T_196 @[dec_tlu_ctl.scala 1627:10] - node _T_197 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1634:65] - node _T_198 = eq(_T_197, UInt<12>("h0342")) @[dec_tlu_ctl.scala 1634:72] - node wr_mcause_r = and(io.dec_csr_wen_r_mod, _T_198) @[dec_tlu_ctl.scala 1634:43] - node _T_199 = and(io.exc_or_int_valid_r, io.take_nmi) @[dec_tlu_ctl.scala 1635:53] - node mcause_sel_nmi_store = and(_T_199, io.nmi_lsu_store_type) @[dec_tlu_ctl.scala 1635:67] - node _T_200 = and(io.exc_or_int_valid_r, io.take_nmi) @[dec_tlu_ctl.scala 1636:52] - node mcause_sel_nmi_load = and(_T_200, io.nmi_lsu_load_type) @[dec_tlu_ctl.scala 1636:66] - node _T_201 = and(io.exc_or_int_valid_r, io.take_nmi) @[dec_tlu_ctl.scala 1637:51] - node _T_202 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 1637:84] - node mcause_sel_nmi_ext = and(_T_201, _T_202) @[dec_tlu_ctl.scala 1637:65] - node _T_203 = andr(io.lsu_fir_error) @[dec_tlu_ctl.scala 1643:53] - node _T_204 = bits(io.lsu_fir_error, 1, 1) @[dec_tlu_ctl.scala 1643:76] - node _T_205 = bits(io.lsu_fir_error, 0, 0) @[dec_tlu_ctl.scala 1643:99] - node _T_206 = not(_T_205) @[dec_tlu_ctl.scala 1643:82] - node _T_207 = and(_T_204, _T_206) @[dec_tlu_ctl.scala 1643:80] + reg _T_196 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1625:47] + _T_196 <= mepc_ns @[dec_tlu_ctl.scala 1625:47] + io.mepc <= _T_196 @[dec_tlu_ctl.scala 1625:10] + node _T_197 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1632:65] + node _T_198 = eq(_T_197, UInt<12>("h0342")) @[dec_tlu_ctl.scala 1632:72] + node wr_mcause_r = and(io.dec_csr_wen_r_mod, _T_198) @[dec_tlu_ctl.scala 1632:43] + node _T_199 = and(io.exc_or_int_valid_r, io.take_nmi) @[dec_tlu_ctl.scala 1633:53] + node mcause_sel_nmi_store = and(_T_199, io.nmi_lsu_store_type) @[dec_tlu_ctl.scala 1633:67] + node _T_200 = and(io.exc_or_int_valid_r, io.take_nmi) @[dec_tlu_ctl.scala 1634:52] + node mcause_sel_nmi_load = and(_T_200, io.nmi_lsu_load_type) @[dec_tlu_ctl.scala 1634:66] + node _T_201 = and(io.exc_or_int_valid_r, io.take_nmi) @[dec_tlu_ctl.scala 1635:51] + node _T_202 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 1635:84] + node mcause_sel_nmi_ext = and(_T_201, _T_202) @[dec_tlu_ctl.scala 1635:65] + node _T_203 = andr(io.lsu_fir_error) @[dec_tlu_ctl.scala 1641:53] + node _T_204 = bits(io.lsu_fir_error, 1, 1) @[dec_tlu_ctl.scala 1641:76] + node _T_205 = bits(io.lsu_fir_error, 0, 0) @[dec_tlu_ctl.scala 1641:99] + node _T_206 = not(_T_205) @[dec_tlu_ctl.scala 1641:82] + node _T_207 = and(_T_204, _T_206) @[dec_tlu_ctl.scala 1641:80] node mcause_fir_error_type = cat(_T_203, _T_207) @[Cat.scala 29:58] - node _T_208 = bits(mcause_sel_nmi_store, 0, 0) @[dec_tlu_ctl.scala 1646:52] - node _T_209 = bits(mcause_sel_nmi_load, 0, 0) @[dec_tlu_ctl.scala 1647:51] - node _T_210 = bits(mcause_sel_nmi_ext, 0, 0) @[dec_tlu_ctl.scala 1648:50] + node _T_208 = bits(mcause_sel_nmi_store, 0, 0) @[dec_tlu_ctl.scala 1644:52] + node _T_209 = bits(mcause_sel_nmi_load, 0, 0) @[dec_tlu_ctl.scala 1645:51] + node _T_210 = bits(mcause_sel_nmi_ext, 0, 0) @[dec_tlu_ctl.scala 1646:50] node _T_211 = cat(UInt<28>("h0f000100"), UInt<2>("h00")) @[Cat.scala 29:58] node _T_212 = cat(_T_211, mcause_fir_error_type) @[Cat.scala 29:58] - node _T_213 = not(io.take_nmi) @[dec_tlu_ctl.scala 1649:56] - node _T_214 = and(io.exc_or_int_valid_r, _T_213) @[dec_tlu_ctl.scala 1649:54] - node _T_215 = bits(_T_214, 0, 0) @[dec_tlu_ctl.scala 1649:70] + node _T_213 = not(io.take_nmi) @[dec_tlu_ctl.scala 1647:56] + node _T_214 = and(io.exc_or_int_valid_r, _T_213) @[dec_tlu_ctl.scala 1647:54] + node _T_215 = bits(_T_214, 0, 0) @[dec_tlu_ctl.scala 1647:70] node _T_216 = cat(io.interrupt_valid_r, UInt<26>("h00")) @[Cat.scala 29:58] node _T_217 = cat(_T_216, io.exc_cause_r) @[Cat.scala 29:58] - node _T_218 = not(io.exc_or_int_valid_r) @[dec_tlu_ctl.scala 1650:46] - node _T_219 = and(wr_mcause_r, _T_218) @[dec_tlu_ctl.scala 1650:44] - node _T_220 = bits(_T_219, 0, 0) @[dec_tlu_ctl.scala 1650:70] - node _T_221 = not(wr_mcause_r) @[dec_tlu_ctl.scala 1651:32] - node _T_222 = not(io.exc_or_int_valid_r) @[dec_tlu_ctl.scala 1651:47] - node _T_223 = and(_T_221, _T_222) @[dec_tlu_ctl.scala 1651:45] - node _T_224 = bits(_T_223, 0, 0) @[dec_tlu_ctl.scala 1651:71] + node _T_218 = not(io.exc_or_int_valid_r) @[dec_tlu_ctl.scala 1648:46] + node _T_219 = and(wr_mcause_r, _T_218) @[dec_tlu_ctl.scala 1648:44] + node _T_220 = bits(_T_219, 0, 0) @[dec_tlu_ctl.scala 1648:70] + node _T_221 = not(wr_mcause_r) @[dec_tlu_ctl.scala 1649:32] + node _T_222 = not(io.exc_or_int_valid_r) @[dec_tlu_ctl.scala 1649:47] + node _T_223 = and(_T_221, _T_222) @[dec_tlu_ctl.scala 1649:45] + node _T_224 = bits(_T_223, 0, 0) @[dec_tlu_ctl.scala 1649:71] node _T_225 = mux(_T_208, UInt<32>("h0f0000000"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_226 = mux(_T_209, UInt<32>("h0f0000001"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_227 = mux(_T_210, _T_212, UInt<1>("h00")) @[Mux.scala 27:72] @@ -73274,19 +73274,19 @@ circuit quasar_wrapper : node _T_235 = or(_T_234, _T_230) @[Mux.scala 27:72] wire mcause_ns : UInt<32> @[Mux.scala 27:72] mcause_ns <= _T_235 @[Mux.scala 27:72] - reg _T_236 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1653:49] - _T_236 <= mcause_ns @[dec_tlu_ctl.scala 1653:49] - mcause <= _T_236 @[dec_tlu_ctl.scala 1653:12] - node _T_237 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1660:64] - node _T_238 = eq(_T_237, UInt<12>("h07ff")) @[dec_tlu_ctl.scala 1660:71] - node wr_mscause_r = and(io.dec_csr_wen_r_mod, _T_238) @[dec_tlu_ctl.scala 1660:42] - node _T_239 = eq(io.dec_tlu_packet_r.icaf_type, UInt<2>("h00")) @[dec_tlu_ctl.scala 1662:56] + reg _T_236 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1651:49] + _T_236 <= mcause_ns @[dec_tlu_ctl.scala 1651:49] + mcause <= _T_236 @[dec_tlu_ctl.scala 1651:12] + node _T_237 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1658:64] + node _T_238 = eq(_T_237, UInt<12>("h07ff")) @[dec_tlu_ctl.scala 1658:71] + node wr_mscause_r = and(io.dec_csr_wen_r_mod, _T_238) @[dec_tlu_ctl.scala 1658:42] + node _T_239 = eq(io.dec_tlu_packet_r.icaf_type, UInt<2>("h00")) @[dec_tlu_ctl.scala 1660:56] node _T_240 = cat(UInt<2>("h00"), io.dec_tlu_packet_r.icaf_type) @[Cat.scala 29:58] - node ifu_mscause = mux(_T_239, UInt<4>("h09"), _T_240) @[dec_tlu_ctl.scala 1662:24] - node _T_241 = bits(io.lsu_i0_exc_r, 0, 0) @[dec_tlu_ctl.scala 1665:36] - node _T_242 = bits(io.i0_trigger_hit_r, 0, 0) @[dec_tlu_ctl.scala 1666:40] - node _T_243 = bits(io.ebreak_r, 0, 0) @[dec_tlu_ctl.scala 1667:32] - node _T_244 = bits(io.inst_acc_r, 0, 0) @[dec_tlu_ctl.scala 1668:34] + node ifu_mscause = mux(_T_239, UInt<4>("h09"), _T_240) @[dec_tlu_ctl.scala 1660:24] + node _T_241 = bits(io.lsu_i0_exc_r, 0, 0) @[dec_tlu_ctl.scala 1663:36] + node _T_242 = bits(io.i0_trigger_hit_r, 0, 0) @[dec_tlu_ctl.scala 1664:40] + node _T_243 = bits(io.ebreak_r, 0, 0) @[dec_tlu_ctl.scala 1665:32] + node _T_244 = bits(io.inst_acc_r, 0, 0) @[dec_tlu_ctl.scala 1666:34] node _T_245 = mux(_T_241, io.lsu_error_pkt_r.bits.mscause, UInt<1>("h00")) @[Mux.scala 27:72] node _T_246 = mux(_T_242, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_247 = mux(_T_243, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] @@ -73296,15 +73296,15 @@ circuit quasar_wrapper : node _T_251 = or(_T_250, _T_248) @[Mux.scala 27:72] wire mscause_type : UInt<4> @[Mux.scala 27:72] mscause_type <= _T_251 @[Mux.scala 27:72] - node _T_252 = bits(io.exc_or_int_valid_r, 0, 0) @[dec_tlu_ctl.scala 1672:48] - node _T_253 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1673:40] - node _T_254 = and(wr_mscause_r, _T_253) @[dec_tlu_ctl.scala 1673:38] - node _T_255 = bits(_T_254, 0, 0) @[dec_tlu_ctl.scala 1673:64] - node _T_256 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1673:103] - node _T_257 = eq(wr_mscause_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1674:25] - node _T_258 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1674:41] - node _T_259 = and(_T_257, _T_258) @[dec_tlu_ctl.scala 1674:39] - node _T_260 = bits(_T_259, 0, 0) @[dec_tlu_ctl.scala 1674:65] + node _T_252 = bits(io.exc_or_int_valid_r, 0, 0) @[dec_tlu_ctl.scala 1670:48] + node _T_253 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1671:40] + node _T_254 = and(wr_mscause_r, _T_253) @[dec_tlu_ctl.scala 1671:38] + node _T_255 = bits(_T_254, 0, 0) @[dec_tlu_ctl.scala 1671:64] + node _T_256 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1671:103] + node _T_257 = eq(wr_mscause_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1672:25] + node _T_258 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1672:41] + node _T_259 = and(_T_257, _T_258) @[dec_tlu_ctl.scala 1672:39] + node _T_260 = bits(_T_259, 0, 0) @[dec_tlu_ctl.scala 1672:65] node _T_261 = mux(_T_252, mscause_type, UInt<1>("h00")) @[Mux.scala 27:72] node _T_262 = mux(_T_255, _T_256, UInt<1>("h00")) @[Mux.scala 27:72] node _T_263 = mux(_T_260, mscause, UInt<1>("h00")) @[Mux.scala 27:72] @@ -73312,60 +73312,60 @@ circuit quasar_wrapper : node _T_265 = or(_T_264, _T_263) @[Mux.scala 27:72] wire mscause_ns : UInt<4> @[Mux.scala 27:72] mscause_ns <= _T_265 @[Mux.scala 27:72] - reg _T_266 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1676:47] - _T_266 <= mscause_ns @[dec_tlu_ctl.scala 1676:47] - mscause <= _T_266 @[dec_tlu_ctl.scala 1676:10] - node _T_267 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1683:62] - node _T_268 = eq(_T_267, UInt<12>("h0343")) @[dec_tlu_ctl.scala 1683:69] - node wr_mtval_r = and(io.dec_csr_wen_r_mod, _T_268) @[dec_tlu_ctl.scala 1683:40] - node _T_269 = not(io.inst_acc_second_r) @[dec_tlu_ctl.scala 1684:83] - node _T_270 = and(io.inst_acc_r, _T_269) @[dec_tlu_ctl.scala 1684:81] - node _T_271 = or(io.ebreak_r, _T_270) @[dec_tlu_ctl.scala 1684:64] - node _T_272 = or(_T_271, io.mepc_trigger_hit_sel_pc_r) @[dec_tlu_ctl.scala 1684:106] - node _T_273 = and(io.exc_or_int_valid_r, _T_272) @[dec_tlu_ctl.scala 1684:49] - node _T_274 = not(io.take_nmi) @[dec_tlu_ctl.scala 1684:140] - node mtval_capture_pc_r = and(_T_273, _T_274) @[dec_tlu_ctl.scala 1684:138] - node _T_275 = and(io.inst_acc_r, io.inst_acc_second_r) @[dec_tlu_ctl.scala 1685:72] - node _T_276 = and(io.exc_or_int_valid_r, _T_275) @[dec_tlu_ctl.scala 1685:55] - node _T_277 = not(io.take_nmi) @[dec_tlu_ctl.scala 1685:98] - node mtval_capture_pc_plus2_r = and(_T_276, _T_277) @[dec_tlu_ctl.scala 1685:96] - node _T_278 = and(io.exc_or_int_valid_r, io.illegal_r) @[dec_tlu_ctl.scala 1686:51] - node _T_279 = not(io.take_nmi) @[dec_tlu_ctl.scala 1686:68] - node mtval_capture_inst_r = and(_T_278, _T_279) @[dec_tlu_ctl.scala 1686:66] - node _T_280 = and(io.exc_or_int_valid_r, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 1687:50] - node _T_281 = not(io.take_nmi) @[dec_tlu_ctl.scala 1687:73] - node mtval_capture_lsu_r = and(_T_280, _T_281) @[dec_tlu_ctl.scala 1687:71] - node _T_282 = not(mtval_capture_pc_r) @[dec_tlu_ctl.scala 1688:46] - node _T_283 = and(io.exc_or_int_valid_r, _T_282) @[dec_tlu_ctl.scala 1688:44] - node _T_284 = not(mtval_capture_inst_r) @[dec_tlu_ctl.scala 1688:68] - node _T_285 = and(_T_283, _T_284) @[dec_tlu_ctl.scala 1688:66] - node _T_286 = not(mtval_capture_lsu_r) @[dec_tlu_ctl.scala 1688:92] - node _T_287 = and(_T_285, _T_286) @[dec_tlu_ctl.scala 1688:90] - node _T_288 = not(io.mepc_trigger_hit_sel_pc_r) @[dec_tlu_ctl.scala 1688:115] - node mtval_clear_r = and(_T_287, _T_288) @[dec_tlu_ctl.scala 1688:113] - node _T_289 = bits(mtval_capture_pc_r, 0, 0) @[dec_tlu_ctl.scala 1692:25] + reg _T_266 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1674:47] + _T_266 <= mscause_ns @[dec_tlu_ctl.scala 1674:47] + mscause <= _T_266 @[dec_tlu_ctl.scala 1674:10] + node _T_267 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1681:62] + node _T_268 = eq(_T_267, UInt<12>("h0343")) @[dec_tlu_ctl.scala 1681:69] + node wr_mtval_r = and(io.dec_csr_wen_r_mod, _T_268) @[dec_tlu_ctl.scala 1681:40] + node _T_269 = not(io.inst_acc_second_r) @[dec_tlu_ctl.scala 1682:83] + node _T_270 = and(io.inst_acc_r, _T_269) @[dec_tlu_ctl.scala 1682:81] + node _T_271 = or(io.ebreak_r, _T_270) @[dec_tlu_ctl.scala 1682:64] + node _T_272 = or(_T_271, io.mepc_trigger_hit_sel_pc_r) @[dec_tlu_ctl.scala 1682:106] + node _T_273 = and(io.exc_or_int_valid_r, _T_272) @[dec_tlu_ctl.scala 1682:49] + node _T_274 = not(io.take_nmi) @[dec_tlu_ctl.scala 1682:140] + node mtval_capture_pc_r = and(_T_273, _T_274) @[dec_tlu_ctl.scala 1682:138] + node _T_275 = and(io.inst_acc_r, io.inst_acc_second_r) @[dec_tlu_ctl.scala 1683:72] + node _T_276 = and(io.exc_or_int_valid_r, _T_275) @[dec_tlu_ctl.scala 1683:55] + node _T_277 = not(io.take_nmi) @[dec_tlu_ctl.scala 1683:98] + node mtval_capture_pc_plus2_r = and(_T_276, _T_277) @[dec_tlu_ctl.scala 1683:96] + node _T_278 = and(io.exc_or_int_valid_r, io.illegal_r) @[dec_tlu_ctl.scala 1684:51] + node _T_279 = not(io.take_nmi) @[dec_tlu_ctl.scala 1684:68] + node mtval_capture_inst_r = and(_T_278, _T_279) @[dec_tlu_ctl.scala 1684:66] + node _T_280 = and(io.exc_or_int_valid_r, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 1685:50] + node _T_281 = not(io.take_nmi) @[dec_tlu_ctl.scala 1685:73] + node mtval_capture_lsu_r = and(_T_280, _T_281) @[dec_tlu_ctl.scala 1685:71] + node _T_282 = not(mtval_capture_pc_r) @[dec_tlu_ctl.scala 1686:46] + node _T_283 = and(io.exc_or_int_valid_r, _T_282) @[dec_tlu_ctl.scala 1686:44] + node _T_284 = not(mtval_capture_inst_r) @[dec_tlu_ctl.scala 1686:68] + node _T_285 = and(_T_283, _T_284) @[dec_tlu_ctl.scala 1686:66] + node _T_286 = not(mtval_capture_lsu_r) @[dec_tlu_ctl.scala 1686:92] + node _T_287 = and(_T_285, _T_286) @[dec_tlu_ctl.scala 1686:90] + node _T_288 = not(io.mepc_trigger_hit_sel_pc_r) @[dec_tlu_ctl.scala 1686:115] + node mtval_clear_r = and(_T_287, _T_288) @[dec_tlu_ctl.scala 1686:113] + node _T_289 = bits(mtval_capture_pc_r, 0, 0) @[dec_tlu_ctl.scala 1690:25] node _T_290 = cat(pc_r, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_291 = bits(mtval_capture_pc_plus2_r, 0, 0) @[dec_tlu_ctl.scala 1693:31] - node _T_292 = add(pc_r, UInt<31>("h01")) @[dec_tlu_ctl.scala 1693:83] - node _T_293 = tail(_T_292, 1) @[dec_tlu_ctl.scala 1693:83] + node _T_291 = bits(mtval_capture_pc_plus2_r, 0, 0) @[dec_tlu_ctl.scala 1691:31] + node _T_292 = add(pc_r, UInt<31>("h01")) @[dec_tlu_ctl.scala 1691:83] + node _T_293 = tail(_T_292, 1) @[dec_tlu_ctl.scala 1691:83] node _T_294 = cat(_T_293, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_295 = bits(mtval_capture_inst_r, 0, 0) @[dec_tlu_ctl.scala 1694:27] - node _T_296 = bits(mtval_capture_lsu_r, 0, 0) @[dec_tlu_ctl.scala 1695:26] - node _T_297 = not(io.interrupt_valid_r) @[dec_tlu_ctl.scala 1696:18] - node _T_298 = and(wr_mtval_r, _T_297) @[dec_tlu_ctl.scala 1696:16] - node _T_299 = bits(_T_298, 0, 0) @[dec_tlu_ctl.scala 1696:48] - node _T_300 = not(io.take_nmi) @[dec_tlu_ctl.scala 1697:5] - node _T_301 = not(wr_mtval_r) @[dec_tlu_ctl.scala 1697:20] - node _T_302 = and(_T_300, _T_301) @[dec_tlu_ctl.scala 1697:18] - node _T_303 = not(mtval_capture_pc_r) @[dec_tlu_ctl.scala 1697:34] - node _T_304 = and(_T_302, _T_303) @[dec_tlu_ctl.scala 1697:32] - node _T_305 = not(mtval_capture_inst_r) @[dec_tlu_ctl.scala 1697:56] - node _T_306 = and(_T_304, _T_305) @[dec_tlu_ctl.scala 1697:54] - node _T_307 = not(mtval_clear_r) @[dec_tlu_ctl.scala 1697:80] - node _T_308 = and(_T_306, _T_307) @[dec_tlu_ctl.scala 1697:78] - node _T_309 = not(mtval_capture_lsu_r) @[dec_tlu_ctl.scala 1697:97] - node _T_310 = and(_T_308, _T_309) @[dec_tlu_ctl.scala 1697:95] - node _T_311 = bits(_T_310, 0, 0) @[dec_tlu_ctl.scala 1697:119] + node _T_295 = bits(mtval_capture_inst_r, 0, 0) @[dec_tlu_ctl.scala 1692:27] + node _T_296 = bits(mtval_capture_lsu_r, 0, 0) @[dec_tlu_ctl.scala 1693:26] + node _T_297 = not(io.interrupt_valid_r) @[dec_tlu_ctl.scala 1694:18] + node _T_298 = and(wr_mtval_r, _T_297) @[dec_tlu_ctl.scala 1694:16] + node _T_299 = bits(_T_298, 0, 0) @[dec_tlu_ctl.scala 1694:48] + node _T_300 = not(io.take_nmi) @[dec_tlu_ctl.scala 1695:5] + node _T_301 = not(wr_mtval_r) @[dec_tlu_ctl.scala 1695:20] + node _T_302 = and(_T_300, _T_301) @[dec_tlu_ctl.scala 1695:18] + node _T_303 = not(mtval_capture_pc_r) @[dec_tlu_ctl.scala 1695:34] + node _T_304 = and(_T_302, _T_303) @[dec_tlu_ctl.scala 1695:32] + node _T_305 = not(mtval_capture_inst_r) @[dec_tlu_ctl.scala 1695:56] + node _T_306 = and(_T_304, _T_305) @[dec_tlu_ctl.scala 1695:54] + node _T_307 = not(mtval_clear_r) @[dec_tlu_ctl.scala 1695:80] + node _T_308 = and(_T_306, _T_307) @[dec_tlu_ctl.scala 1695:78] + node _T_309 = not(mtval_capture_lsu_r) @[dec_tlu_ctl.scala 1695:97] + node _T_310 = and(_T_308, _T_309) @[dec_tlu_ctl.scala 1695:95] + node _T_311 = bits(_T_310, 0, 0) @[dec_tlu_ctl.scala 1695:119] node _T_312 = mux(_T_289, _T_290, UInt<1>("h00")) @[Mux.scala 27:72] node _T_313 = mux(_T_291, _T_294, UInt<1>("h00")) @[Mux.scala 27:72] node _T_314 = mux(_T_295, io.dec_illegal_inst, UInt<1>("h00")) @[Mux.scala 27:72] @@ -73379,14 +73379,14 @@ circuit quasar_wrapper : node _T_322 = or(_T_321, _T_317) @[Mux.scala 27:72] wire mtval_ns : UInt<32> @[Mux.scala 27:72] mtval_ns <= _T_322 @[Mux.scala 27:72] - reg _T_323 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1699:46] - _T_323 <= mtval_ns @[dec_tlu_ctl.scala 1699:46] - mtval <= _T_323 @[dec_tlu_ctl.scala 1699:8] - node _T_324 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1714:61] - node _T_325 = eq(_T_324, UInt<12>("h07f8")) @[dec_tlu_ctl.scala 1714:68] - node wr_mcgc_r = and(io.dec_csr_wen_r_mod, _T_325) @[dec_tlu_ctl.scala 1714:39] - node _T_326 = bits(io.dec_csr_wrdata_r, 8, 0) @[dec_tlu_ctl.scala 1716:39] - node _T_327 = bits(wr_mcgc_r, 0, 0) @[dec_tlu_ctl.scala 1716:55] + reg _T_323 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1697:46] + _T_323 <= mtval_ns @[dec_tlu_ctl.scala 1697:46] + mtval <= _T_323 @[dec_tlu_ctl.scala 1697:8] + node _T_324 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1712:61] + node _T_325 = eq(_T_324, UInt<12>("h07f8")) @[dec_tlu_ctl.scala 1712:68] + node wr_mcgc_r = and(io.dec_csr_wen_r_mod, _T_325) @[dec_tlu_ctl.scala 1712:39] + node _T_326 = bits(io.dec_csr_wrdata_r, 8, 0) @[dec_tlu_ctl.scala 1714:39] + node _T_327 = bits(wr_mcgc_r, 0, 0) @[dec_tlu_ctl.scala 1714:55] inst rvclkhdr_8 of rvclkhdr_728 @[lib.scala 368:23] rvclkhdr_8.clock <= clock rvclkhdr_8.reset <= reset @@ -73395,26 +73395,26 @@ circuit quasar_wrapper : rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg mcgc : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] mcgc <= _T_326 @[lib.scala 374:16] - node _T_328 = bits(mcgc, 8, 8) @[dec_tlu_ctl.scala 1718:38] - io.dec_tlu_misc_clk_override <= _T_328 @[dec_tlu_ctl.scala 1718:31] - node _T_329 = bits(mcgc, 7, 7) @[dec_tlu_ctl.scala 1719:38] - io.dec_tlu_dec_clk_override <= _T_329 @[dec_tlu_ctl.scala 1719:31] - node _T_330 = bits(mcgc, 5, 5) @[dec_tlu_ctl.scala 1720:38] - io.dec_tlu_ifu_clk_override <= _T_330 @[dec_tlu_ctl.scala 1720:31] - node _T_331 = bits(mcgc, 4, 4) @[dec_tlu_ctl.scala 1721:38] - io.dec_tlu_lsu_clk_override <= _T_331 @[dec_tlu_ctl.scala 1721:31] - node _T_332 = bits(mcgc, 3, 3) @[dec_tlu_ctl.scala 1722:38] - io.dec_tlu_bus_clk_override <= _T_332 @[dec_tlu_ctl.scala 1722:31] - node _T_333 = bits(mcgc, 2, 2) @[dec_tlu_ctl.scala 1723:38] - io.dec_tlu_pic_clk_override <= _T_333 @[dec_tlu_ctl.scala 1723:31] - node _T_334 = bits(mcgc, 1, 1) @[dec_tlu_ctl.scala 1724:38] - io.dec_tlu_dccm_clk_override <= _T_334 @[dec_tlu_ctl.scala 1724:31] - node _T_335 = bits(mcgc, 0, 0) @[dec_tlu_ctl.scala 1725:38] - io.dec_tlu_icm_clk_override <= _T_335 @[dec_tlu_ctl.scala 1725:31] - node _T_336 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1744:61] - node _T_337 = eq(_T_336, UInt<12>("h07f9")) @[dec_tlu_ctl.scala 1744:68] - node wr_mfdc_r = and(io.dec_csr_wen_r_mod, _T_337) @[dec_tlu_ctl.scala 1744:39] - node _T_338 = bits(wr_mfdc_r, 0, 0) @[dec_tlu_ctl.scala 1748:39] + node _T_328 = bits(mcgc, 8, 8) @[dec_tlu_ctl.scala 1716:38] + io.dec_tlu_misc_clk_override <= _T_328 @[dec_tlu_ctl.scala 1716:31] + node _T_329 = bits(mcgc, 7, 7) @[dec_tlu_ctl.scala 1717:38] + io.dec_tlu_dec_clk_override <= _T_329 @[dec_tlu_ctl.scala 1717:31] + node _T_330 = bits(mcgc, 5, 5) @[dec_tlu_ctl.scala 1718:38] + io.dec_tlu_ifu_clk_override <= _T_330 @[dec_tlu_ctl.scala 1718:31] + node _T_331 = bits(mcgc, 4, 4) @[dec_tlu_ctl.scala 1719:38] + io.dec_tlu_lsu_clk_override <= _T_331 @[dec_tlu_ctl.scala 1719:31] + node _T_332 = bits(mcgc, 3, 3) @[dec_tlu_ctl.scala 1720:38] + io.dec_tlu_bus_clk_override <= _T_332 @[dec_tlu_ctl.scala 1720:31] + node _T_333 = bits(mcgc, 2, 2) @[dec_tlu_ctl.scala 1721:38] + io.dec_tlu_pic_clk_override <= _T_333 @[dec_tlu_ctl.scala 1721:31] + node _T_334 = bits(mcgc, 1, 1) @[dec_tlu_ctl.scala 1722:38] + io.dec_tlu_dccm_clk_override <= _T_334 @[dec_tlu_ctl.scala 1722:31] + node _T_335 = bits(mcgc, 0, 0) @[dec_tlu_ctl.scala 1723:38] + io.dec_tlu_icm_clk_override <= _T_335 @[dec_tlu_ctl.scala 1723:31] + node _T_336 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1742:61] + node _T_337 = eq(_T_336, UInt<12>("h07f9")) @[dec_tlu_ctl.scala 1742:68] + node wr_mfdc_r = and(io.dec_csr_wen_r_mod, _T_337) @[dec_tlu_ctl.scala 1742:39] + node _T_338 = bits(wr_mfdc_r, 0, 0) @[dec_tlu_ctl.scala 1746:39] inst rvclkhdr_9 of rvclkhdr_729 @[lib.scala 368:23] rvclkhdr_9.clock <= clock rvclkhdr_9.reset <= reset @@ -73423,1224 +73423,1224 @@ circuit quasar_wrapper : rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_339 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_339 <= mfdc_ns @[lib.scala 374:16] - mfdc_int <= _T_339 @[dec_tlu_ctl.scala 1748:11] - node _T_340 = bits(io.dec_csr_wrdata_r, 18, 16) @[dec_tlu_ctl.scala 1757:39] - node _T_341 = not(_T_340) @[dec_tlu_ctl.scala 1757:19] - node _T_342 = bits(io.dec_csr_wrdata_r, 11, 0) @[dec_tlu_ctl.scala 1757:66] - node _T_343 = cat(_T_341, _T_342) @[Cat.scala 29:58] - mfdc_ns <= _T_343 @[dec_tlu_ctl.scala 1757:12] - node _T_344 = bits(mfdc_int, 14, 12) @[dec_tlu_ctl.scala 1758:28] - node _T_345 = not(_T_344) @[dec_tlu_ctl.scala 1758:19] - node _T_346 = bits(mfdc_int, 11, 0) @[dec_tlu_ctl.scala 1758:54] - node _T_347 = cat(_T_345, UInt<4>("h00")) @[Cat.scala 29:58] + mfdc_int <= _T_339 @[dec_tlu_ctl.scala 1746:11] + node _T_340 = bits(io.dec_csr_wrdata_r, 18, 16) @[dec_tlu_ctl.scala 1751:40] + node _T_341 = not(_T_340) @[dec_tlu_ctl.scala 1751:20] + node _T_342 = bits(io.dec_csr_wrdata_r, 11, 7) @[dec_tlu_ctl.scala 1751:67] + node _T_343 = bits(io.dec_csr_wrdata_r, 6, 6) @[dec_tlu_ctl.scala 1751:95] + node _T_344 = not(_T_343) @[dec_tlu_ctl.scala 1751:75] + node _T_345 = bits(io.dec_csr_wrdata_r, 5, 0) @[dec_tlu_ctl.scala 1751:119] + node _T_346 = cat(_T_344, _T_345) @[Cat.scala 29:58] + node _T_347 = cat(_T_341, _T_342) @[Cat.scala 29:58] node _T_348 = cat(_T_347, _T_346) @[Cat.scala 29:58] - mfdc <= _T_348 @[dec_tlu_ctl.scala 1758:12] - node _T_349 = bits(mfdc, 18, 16) @[dec_tlu_ctl.scala 1762:46] - io.dec_tlu_dma_qos_prty <= _T_349 @[dec_tlu_ctl.scala 1762:39] - node _T_350 = bits(mfdc, 11, 11) @[dec_tlu_ctl.scala 1763:46] - io.dec_tlu_external_ldfwd_disable <= _T_350 @[dec_tlu_ctl.scala 1763:39] - node _T_351 = bits(mfdc, 8, 8) @[dec_tlu_ctl.scala 1764:46] - io.dec_tlu_core_ecc_disable <= _T_351 @[dec_tlu_ctl.scala 1764:39] - node _T_352 = bits(mfdc, 6, 6) @[dec_tlu_ctl.scala 1765:46] - io.dec_tlu_sideeffect_posted_disable <= _T_352 @[dec_tlu_ctl.scala 1765:39] - node _T_353 = bits(mfdc, 3, 3) @[dec_tlu_ctl.scala 1766:46] - io.dec_tlu_bpred_disable <= _T_353 @[dec_tlu_ctl.scala 1766:39] - node _T_354 = bits(mfdc, 2, 2) @[dec_tlu_ctl.scala 1767:46] - io.dec_tlu_wb_coalescing_disable <= _T_354 @[dec_tlu_ctl.scala 1767:39] - node _T_355 = bits(mfdc, 0, 0) @[dec_tlu_ctl.scala 1768:46] - io.dec_tlu_pipelining_disable <= _T_355 @[dec_tlu_ctl.scala 1768:39] - node _T_356 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1777:70] - node _T_357 = eq(_T_356, UInt<12>("h07c2")) @[dec_tlu_ctl.scala 1777:77] - node _T_358 = and(io.dec_csr_wen_r_mod, _T_357) @[dec_tlu_ctl.scala 1777:48] - node _T_359 = not(io.interrupt_valid_r) @[dec_tlu_ctl.scala 1777:89] - node _T_360 = and(_T_358, _T_359) @[dec_tlu_ctl.scala 1777:87] - node _T_361 = not(io.take_ext_int_start) @[dec_tlu_ctl.scala 1777:113] - node _T_362 = and(_T_360, _T_361) @[dec_tlu_ctl.scala 1777:111] - io.dec_tlu_wr_pause_r <= _T_362 @[dec_tlu_ctl.scala 1777:24] - node _T_363 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1784:61] - node _T_364 = eq(_T_363, UInt<12>("h07c0")) @[dec_tlu_ctl.scala 1784:68] - node wr_mrac_r = and(io.dec_csr_wen_r_mod, _T_364) @[dec_tlu_ctl.scala 1784:39] - node _T_365 = bits(io.dec_csr_wrdata_r, 31, 31) @[dec_tlu_ctl.scala 1787:39] - node _T_366 = bits(io.dec_csr_wrdata_r, 30, 30) @[dec_tlu_ctl.scala 1787:64] - node _T_367 = bits(io.dec_csr_wrdata_r, 31, 31) @[dec_tlu_ctl.scala 1787:91] - node _T_368 = not(_T_367) @[dec_tlu_ctl.scala 1787:71] - node _T_369 = and(_T_366, _T_368) @[dec_tlu_ctl.scala 1787:69] - node _T_370 = bits(io.dec_csr_wrdata_r, 29, 29) @[dec_tlu_ctl.scala 1788:41] - node _T_371 = bits(io.dec_csr_wrdata_r, 28, 28) @[dec_tlu_ctl.scala 1788:66] - node _T_372 = bits(io.dec_csr_wrdata_r, 29, 29) @[dec_tlu_ctl.scala 1788:93] - node _T_373 = not(_T_372) @[dec_tlu_ctl.scala 1788:73] - node _T_374 = and(_T_371, _T_373) @[dec_tlu_ctl.scala 1788:71] - node _T_375 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 1789:41] - node _T_376 = bits(io.dec_csr_wrdata_r, 26, 26) @[dec_tlu_ctl.scala 1789:66] - node _T_377 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 1789:93] - node _T_378 = not(_T_377) @[dec_tlu_ctl.scala 1789:73] - node _T_379 = and(_T_376, _T_378) @[dec_tlu_ctl.scala 1789:71] - node _T_380 = bits(io.dec_csr_wrdata_r, 25, 25) @[dec_tlu_ctl.scala 1790:41] - node _T_381 = bits(io.dec_csr_wrdata_r, 24, 24) @[dec_tlu_ctl.scala 1790:66] - node _T_382 = bits(io.dec_csr_wrdata_r, 25, 25) @[dec_tlu_ctl.scala 1790:93] - node _T_383 = not(_T_382) @[dec_tlu_ctl.scala 1790:73] - node _T_384 = and(_T_381, _T_383) @[dec_tlu_ctl.scala 1790:71] - node _T_385 = bits(io.dec_csr_wrdata_r, 23, 23) @[dec_tlu_ctl.scala 1791:41] - node _T_386 = bits(io.dec_csr_wrdata_r, 22, 22) @[dec_tlu_ctl.scala 1791:66] - node _T_387 = bits(io.dec_csr_wrdata_r, 23, 23) @[dec_tlu_ctl.scala 1791:93] - node _T_388 = not(_T_387) @[dec_tlu_ctl.scala 1791:73] - node _T_389 = and(_T_386, _T_388) @[dec_tlu_ctl.scala 1791:71] - node _T_390 = bits(io.dec_csr_wrdata_r, 21, 21) @[dec_tlu_ctl.scala 1792:41] - node _T_391 = bits(io.dec_csr_wrdata_r, 20, 20) @[dec_tlu_ctl.scala 1792:66] - node _T_392 = bits(io.dec_csr_wrdata_r, 21, 21) @[dec_tlu_ctl.scala 1792:93] - node _T_393 = not(_T_392) @[dec_tlu_ctl.scala 1792:73] - node _T_394 = and(_T_391, _T_393) @[dec_tlu_ctl.scala 1792:71] - node _T_395 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 1793:41] - node _T_396 = bits(io.dec_csr_wrdata_r, 18, 18) @[dec_tlu_ctl.scala 1793:66] - node _T_397 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 1793:93] - node _T_398 = not(_T_397) @[dec_tlu_ctl.scala 1793:73] - node _T_399 = and(_T_396, _T_398) @[dec_tlu_ctl.scala 1793:71] - node _T_400 = bits(io.dec_csr_wrdata_r, 17, 17) @[dec_tlu_ctl.scala 1794:41] - node _T_401 = bits(io.dec_csr_wrdata_r, 16, 16) @[dec_tlu_ctl.scala 1794:66] - node _T_402 = bits(io.dec_csr_wrdata_r, 17, 17) @[dec_tlu_ctl.scala 1794:93] - node _T_403 = not(_T_402) @[dec_tlu_ctl.scala 1794:73] - node _T_404 = and(_T_401, _T_403) @[dec_tlu_ctl.scala 1794:71] - node _T_405 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 1795:41] - node _T_406 = bits(io.dec_csr_wrdata_r, 14, 14) @[dec_tlu_ctl.scala 1795:66] - node _T_407 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 1795:93] - node _T_408 = not(_T_407) @[dec_tlu_ctl.scala 1795:73] - node _T_409 = and(_T_406, _T_408) @[dec_tlu_ctl.scala 1795:71] - node _T_410 = bits(io.dec_csr_wrdata_r, 13, 13) @[dec_tlu_ctl.scala 1796:41] - node _T_411 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 1796:66] - node _T_412 = bits(io.dec_csr_wrdata_r, 13, 13) @[dec_tlu_ctl.scala 1796:93] - node _T_413 = not(_T_412) @[dec_tlu_ctl.scala 1796:73] - node _T_414 = and(_T_411, _T_413) @[dec_tlu_ctl.scala 1796:71] - node _T_415 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1797:41] - node _T_416 = bits(io.dec_csr_wrdata_r, 10, 10) @[dec_tlu_ctl.scala 1797:66] - node _T_417 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1797:93] - node _T_418 = not(_T_417) @[dec_tlu_ctl.scala 1797:73] - node _T_419 = and(_T_416, _T_418) @[dec_tlu_ctl.scala 1797:71] - node _T_420 = bits(io.dec_csr_wrdata_r, 9, 9) @[dec_tlu_ctl.scala 1798:41] - node _T_421 = bits(io.dec_csr_wrdata_r, 8, 8) @[dec_tlu_ctl.scala 1798:66] - node _T_422 = bits(io.dec_csr_wrdata_r, 9, 9) @[dec_tlu_ctl.scala 1798:93] - node _T_423 = not(_T_422) @[dec_tlu_ctl.scala 1798:73] - node _T_424 = and(_T_421, _T_423) @[dec_tlu_ctl.scala 1798:70] - node _T_425 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1799:41] - node _T_426 = bits(io.dec_csr_wrdata_r, 6, 6) @[dec_tlu_ctl.scala 1799:66] - node _T_427 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1799:93] - node _T_428 = not(_T_427) @[dec_tlu_ctl.scala 1799:73] - node _T_429 = and(_T_426, _T_428) @[dec_tlu_ctl.scala 1799:70] - node _T_430 = bits(io.dec_csr_wrdata_r, 5, 5) @[dec_tlu_ctl.scala 1800:41] - node _T_431 = bits(io.dec_csr_wrdata_r, 4, 4) @[dec_tlu_ctl.scala 1800:66] - node _T_432 = bits(io.dec_csr_wrdata_r, 5, 5) @[dec_tlu_ctl.scala 1800:93] - node _T_433 = not(_T_432) @[dec_tlu_ctl.scala 1800:73] - node _T_434 = and(_T_431, _T_433) @[dec_tlu_ctl.scala 1800:70] - node _T_435 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1801:41] - node _T_436 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 1801:66] - node _T_437 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1801:93] - node _T_438 = not(_T_437) @[dec_tlu_ctl.scala 1801:73] - node _T_439 = and(_T_436, _T_438) @[dec_tlu_ctl.scala 1801:70] - node _T_440 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1802:41] - node _T_441 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1802:66] - node _T_442 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1802:93] - node _T_443 = not(_T_442) @[dec_tlu_ctl.scala 1802:73] - node _T_444 = and(_T_441, _T_443) @[dec_tlu_ctl.scala 1802:70] - node _T_445 = cat(_T_440, _T_444) @[Cat.scala 29:58] - node _T_446 = cat(_T_435, _T_439) @[Cat.scala 29:58] - node _T_447 = cat(_T_446, _T_445) @[Cat.scala 29:58] - node _T_448 = cat(_T_430, _T_434) @[Cat.scala 29:58] - node _T_449 = cat(_T_425, _T_429) @[Cat.scala 29:58] - node _T_450 = cat(_T_449, _T_448) @[Cat.scala 29:58] - node _T_451 = cat(_T_450, _T_447) @[Cat.scala 29:58] - node _T_452 = cat(_T_420, _T_424) @[Cat.scala 29:58] - node _T_453 = cat(_T_415, _T_419) @[Cat.scala 29:58] - node _T_454 = cat(_T_453, _T_452) @[Cat.scala 29:58] - node _T_455 = cat(_T_410, _T_414) @[Cat.scala 29:58] - node _T_456 = cat(_T_405, _T_409) @[Cat.scala 29:58] + mfdc_ns <= _T_348 @[dec_tlu_ctl.scala 1751:13] + node _T_349 = bits(mfdc_int, 14, 12) @[dec_tlu_ctl.scala 1752:29] + node _T_350 = not(_T_349) @[dec_tlu_ctl.scala 1752:20] + node _T_351 = bits(mfdc_int, 11, 7) @[dec_tlu_ctl.scala 1752:55] + node _T_352 = bits(mfdc_int, 6, 6) @[dec_tlu_ctl.scala 1752:72] + node _T_353 = not(_T_352) @[dec_tlu_ctl.scala 1752:63] + node _T_354 = bits(mfdc_int, 5, 0) @[dec_tlu_ctl.scala 1752:85] + node _T_355 = cat(_T_353, _T_354) @[Cat.scala 29:58] + node _T_356 = cat(_T_350, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_357 = cat(_T_356, _T_351) @[Cat.scala 29:58] + node _T_358 = cat(_T_357, _T_355) @[Cat.scala 29:58] + mfdc <= _T_358 @[dec_tlu_ctl.scala 1752:13] + node _T_359 = bits(mfdc, 18, 16) @[dec_tlu_ctl.scala 1760:46] + io.dec_tlu_dma_qos_prty <= _T_359 @[dec_tlu_ctl.scala 1760:39] + node _T_360 = bits(mfdc, 11, 11) @[dec_tlu_ctl.scala 1761:46] + io.dec_tlu_external_ldfwd_disable <= _T_360 @[dec_tlu_ctl.scala 1761:39] + node _T_361 = bits(mfdc, 8, 8) @[dec_tlu_ctl.scala 1762:46] + io.dec_tlu_core_ecc_disable <= _T_361 @[dec_tlu_ctl.scala 1762:39] + node _T_362 = bits(mfdc, 6, 6) @[dec_tlu_ctl.scala 1763:46] + io.dec_tlu_sideeffect_posted_disable <= _T_362 @[dec_tlu_ctl.scala 1763:39] + node _T_363 = bits(mfdc, 3, 3) @[dec_tlu_ctl.scala 1764:46] + io.dec_tlu_bpred_disable <= _T_363 @[dec_tlu_ctl.scala 1764:39] + node _T_364 = bits(mfdc, 2, 2) @[dec_tlu_ctl.scala 1765:46] + io.dec_tlu_wb_coalescing_disable <= _T_364 @[dec_tlu_ctl.scala 1765:39] + node _T_365 = bits(mfdc, 0, 0) @[dec_tlu_ctl.scala 1766:46] + io.dec_tlu_pipelining_disable <= _T_365 @[dec_tlu_ctl.scala 1766:39] + node _T_366 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1775:70] + node _T_367 = eq(_T_366, UInt<12>("h07c2")) @[dec_tlu_ctl.scala 1775:77] + node _T_368 = and(io.dec_csr_wen_r_mod, _T_367) @[dec_tlu_ctl.scala 1775:48] + node _T_369 = not(io.interrupt_valid_r) @[dec_tlu_ctl.scala 1775:89] + node _T_370 = and(_T_368, _T_369) @[dec_tlu_ctl.scala 1775:87] + node _T_371 = not(io.take_ext_int_start) @[dec_tlu_ctl.scala 1775:113] + node _T_372 = and(_T_370, _T_371) @[dec_tlu_ctl.scala 1775:111] + io.dec_tlu_wr_pause_r <= _T_372 @[dec_tlu_ctl.scala 1775:24] + node _T_373 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1782:61] + node _T_374 = eq(_T_373, UInt<12>("h07c0")) @[dec_tlu_ctl.scala 1782:68] + node wr_mrac_r = and(io.dec_csr_wen_r_mod, _T_374) @[dec_tlu_ctl.scala 1782:39] + node _T_375 = bits(io.dec_csr_wrdata_r, 31, 31) @[dec_tlu_ctl.scala 1785:39] + node _T_376 = bits(io.dec_csr_wrdata_r, 30, 30) @[dec_tlu_ctl.scala 1785:64] + node _T_377 = bits(io.dec_csr_wrdata_r, 31, 31) @[dec_tlu_ctl.scala 1785:91] + node _T_378 = not(_T_377) @[dec_tlu_ctl.scala 1785:71] + node _T_379 = and(_T_376, _T_378) @[dec_tlu_ctl.scala 1785:69] + node _T_380 = bits(io.dec_csr_wrdata_r, 29, 29) @[dec_tlu_ctl.scala 1786:41] + node _T_381 = bits(io.dec_csr_wrdata_r, 28, 28) @[dec_tlu_ctl.scala 1786:66] + node _T_382 = bits(io.dec_csr_wrdata_r, 29, 29) @[dec_tlu_ctl.scala 1786:93] + node _T_383 = not(_T_382) @[dec_tlu_ctl.scala 1786:73] + node _T_384 = and(_T_381, _T_383) @[dec_tlu_ctl.scala 1786:71] + node _T_385 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 1787:41] + node _T_386 = bits(io.dec_csr_wrdata_r, 26, 26) @[dec_tlu_ctl.scala 1787:66] + node _T_387 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 1787:93] + node _T_388 = not(_T_387) @[dec_tlu_ctl.scala 1787:73] + node _T_389 = and(_T_386, _T_388) @[dec_tlu_ctl.scala 1787:71] + node _T_390 = bits(io.dec_csr_wrdata_r, 25, 25) @[dec_tlu_ctl.scala 1788:41] + node _T_391 = bits(io.dec_csr_wrdata_r, 24, 24) @[dec_tlu_ctl.scala 1788:66] + node _T_392 = bits(io.dec_csr_wrdata_r, 25, 25) @[dec_tlu_ctl.scala 1788:93] + node _T_393 = not(_T_392) @[dec_tlu_ctl.scala 1788:73] + node _T_394 = and(_T_391, _T_393) @[dec_tlu_ctl.scala 1788:71] + node _T_395 = bits(io.dec_csr_wrdata_r, 23, 23) @[dec_tlu_ctl.scala 1789:41] + node _T_396 = bits(io.dec_csr_wrdata_r, 22, 22) @[dec_tlu_ctl.scala 1789:66] + node _T_397 = bits(io.dec_csr_wrdata_r, 23, 23) @[dec_tlu_ctl.scala 1789:93] + node _T_398 = not(_T_397) @[dec_tlu_ctl.scala 1789:73] + node _T_399 = and(_T_396, _T_398) @[dec_tlu_ctl.scala 1789:71] + node _T_400 = bits(io.dec_csr_wrdata_r, 21, 21) @[dec_tlu_ctl.scala 1790:41] + node _T_401 = bits(io.dec_csr_wrdata_r, 20, 20) @[dec_tlu_ctl.scala 1790:66] + node _T_402 = bits(io.dec_csr_wrdata_r, 21, 21) @[dec_tlu_ctl.scala 1790:93] + node _T_403 = not(_T_402) @[dec_tlu_ctl.scala 1790:73] + node _T_404 = and(_T_401, _T_403) @[dec_tlu_ctl.scala 1790:71] + node _T_405 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 1791:41] + node _T_406 = bits(io.dec_csr_wrdata_r, 18, 18) @[dec_tlu_ctl.scala 1791:66] + node _T_407 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 1791:93] + node _T_408 = not(_T_407) @[dec_tlu_ctl.scala 1791:73] + node _T_409 = and(_T_406, _T_408) @[dec_tlu_ctl.scala 1791:71] + node _T_410 = bits(io.dec_csr_wrdata_r, 17, 17) @[dec_tlu_ctl.scala 1792:41] + node _T_411 = bits(io.dec_csr_wrdata_r, 16, 16) @[dec_tlu_ctl.scala 1792:66] + node _T_412 = bits(io.dec_csr_wrdata_r, 17, 17) @[dec_tlu_ctl.scala 1792:93] + node _T_413 = not(_T_412) @[dec_tlu_ctl.scala 1792:73] + node _T_414 = and(_T_411, _T_413) @[dec_tlu_ctl.scala 1792:71] + node _T_415 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 1793:41] + node _T_416 = bits(io.dec_csr_wrdata_r, 14, 14) @[dec_tlu_ctl.scala 1793:66] + node _T_417 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 1793:93] + node _T_418 = not(_T_417) @[dec_tlu_ctl.scala 1793:73] + node _T_419 = and(_T_416, _T_418) @[dec_tlu_ctl.scala 1793:71] + node _T_420 = bits(io.dec_csr_wrdata_r, 13, 13) @[dec_tlu_ctl.scala 1794:41] + node _T_421 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 1794:66] + node _T_422 = bits(io.dec_csr_wrdata_r, 13, 13) @[dec_tlu_ctl.scala 1794:93] + node _T_423 = not(_T_422) @[dec_tlu_ctl.scala 1794:73] + node _T_424 = and(_T_421, _T_423) @[dec_tlu_ctl.scala 1794:71] + node _T_425 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1795:41] + node _T_426 = bits(io.dec_csr_wrdata_r, 10, 10) @[dec_tlu_ctl.scala 1795:66] + node _T_427 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1795:93] + node _T_428 = not(_T_427) @[dec_tlu_ctl.scala 1795:73] + node _T_429 = and(_T_426, _T_428) @[dec_tlu_ctl.scala 1795:71] + node _T_430 = bits(io.dec_csr_wrdata_r, 9, 9) @[dec_tlu_ctl.scala 1796:41] + node _T_431 = bits(io.dec_csr_wrdata_r, 8, 8) @[dec_tlu_ctl.scala 1796:66] + node _T_432 = bits(io.dec_csr_wrdata_r, 9, 9) @[dec_tlu_ctl.scala 1796:93] + node _T_433 = not(_T_432) @[dec_tlu_ctl.scala 1796:73] + node _T_434 = and(_T_431, _T_433) @[dec_tlu_ctl.scala 1796:70] + node _T_435 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1797:41] + node _T_436 = bits(io.dec_csr_wrdata_r, 6, 6) @[dec_tlu_ctl.scala 1797:66] + node _T_437 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1797:93] + node _T_438 = not(_T_437) @[dec_tlu_ctl.scala 1797:73] + node _T_439 = and(_T_436, _T_438) @[dec_tlu_ctl.scala 1797:70] + node _T_440 = bits(io.dec_csr_wrdata_r, 5, 5) @[dec_tlu_ctl.scala 1798:41] + node _T_441 = bits(io.dec_csr_wrdata_r, 4, 4) @[dec_tlu_ctl.scala 1798:66] + node _T_442 = bits(io.dec_csr_wrdata_r, 5, 5) @[dec_tlu_ctl.scala 1798:93] + node _T_443 = not(_T_442) @[dec_tlu_ctl.scala 1798:73] + node _T_444 = and(_T_441, _T_443) @[dec_tlu_ctl.scala 1798:70] + node _T_445 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1799:41] + node _T_446 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 1799:66] + node _T_447 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1799:93] + node _T_448 = not(_T_447) @[dec_tlu_ctl.scala 1799:73] + node _T_449 = and(_T_446, _T_448) @[dec_tlu_ctl.scala 1799:70] + node _T_450 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1800:41] + node _T_451 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1800:66] + node _T_452 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1800:93] + node _T_453 = not(_T_452) @[dec_tlu_ctl.scala 1800:73] + node _T_454 = and(_T_451, _T_453) @[dec_tlu_ctl.scala 1800:70] + node _T_455 = cat(_T_450, _T_454) @[Cat.scala 29:58] + node _T_456 = cat(_T_445, _T_449) @[Cat.scala 29:58] node _T_457 = cat(_T_456, _T_455) @[Cat.scala 29:58] - node _T_458 = cat(_T_457, _T_454) @[Cat.scala 29:58] - node _T_459 = cat(_T_458, _T_451) @[Cat.scala 29:58] - node _T_460 = cat(_T_400, _T_404) @[Cat.scala 29:58] - node _T_461 = cat(_T_395, _T_399) @[Cat.scala 29:58] - node _T_462 = cat(_T_461, _T_460) @[Cat.scala 29:58] - node _T_463 = cat(_T_390, _T_394) @[Cat.scala 29:58] - node _T_464 = cat(_T_385, _T_389) @[Cat.scala 29:58] - node _T_465 = cat(_T_464, _T_463) @[Cat.scala 29:58] - node _T_466 = cat(_T_465, _T_462) @[Cat.scala 29:58] - node _T_467 = cat(_T_380, _T_384) @[Cat.scala 29:58] - node _T_468 = cat(_T_375, _T_379) @[Cat.scala 29:58] - node _T_469 = cat(_T_468, _T_467) @[Cat.scala 29:58] - node _T_470 = cat(_T_370, _T_374) @[Cat.scala 29:58] - node _T_471 = cat(_T_365, _T_369) @[Cat.scala 29:58] + node _T_458 = cat(_T_440, _T_444) @[Cat.scala 29:58] + node _T_459 = cat(_T_435, _T_439) @[Cat.scala 29:58] + node _T_460 = cat(_T_459, _T_458) @[Cat.scala 29:58] + node _T_461 = cat(_T_460, _T_457) @[Cat.scala 29:58] + node _T_462 = cat(_T_430, _T_434) @[Cat.scala 29:58] + node _T_463 = cat(_T_425, _T_429) @[Cat.scala 29:58] + node _T_464 = cat(_T_463, _T_462) @[Cat.scala 29:58] + node _T_465 = cat(_T_420, _T_424) @[Cat.scala 29:58] + node _T_466 = cat(_T_415, _T_419) @[Cat.scala 29:58] + node _T_467 = cat(_T_466, _T_465) @[Cat.scala 29:58] + node _T_468 = cat(_T_467, _T_464) @[Cat.scala 29:58] + node _T_469 = cat(_T_468, _T_461) @[Cat.scala 29:58] + node _T_470 = cat(_T_410, _T_414) @[Cat.scala 29:58] + node _T_471 = cat(_T_405, _T_409) @[Cat.scala 29:58] node _T_472 = cat(_T_471, _T_470) @[Cat.scala 29:58] - node _T_473 = cat(_T_472, _T_469) @[Cat.scala 29:58] - node _T_474 = cat(_T_473, _T_466) @[Cat.scala 29:58] - node mrac_in = cat(_T_474, _T_459) @[Cat.scala 29:58] - node _T_475 = bits(wr_mrac_r, 0, 0) @[dec_tlu_ctl.scala 1805:38] + node _T_473 = cat(_T_400, _T_404) @[Cat.scala 29:58] + node _T_474 = cat(_T_395, _T_399) @[Cat.scala 29:58] + node _T_475 = cat(_T_474, _T_473) @[Cat.scala 29:58] + node _T_476 = cat(_T_475, _T_472) @[Cat.scala 29:58] + node _T_477 = cat(_T_390, _T_394) @[Cat.scala 29:58] + node _T_478 = cat(_T_385, _T_389) @[Cat.scala 29:58] + node _T_479 = cat(_T_478, _T_477) @[Cat.scala 29:58] + node _T_480 = cat(_T_380, _T_384) @[Cat.scala 29:58] + node _T_481 = cat(_T_375, _T_379) @[Cat.scala 29:58] + node _T_482 = cat(_T_481, _T_480) @[Cat.scala 29:58] + node _T_483 = cat(_T_482, _T_479) @[Cat.scala 29:58] + node _T_484 = cat(_T_483, _T_476) @[Cat.scala 29:58] + node mrac_in = cat(_T_484, _T_469) @[Cat.scala 29:58] + node _T_485 = bits(wr_mrac_r, 0, 0) @[dec_tlu_ctl.scala 1803:38] inst rvclkhdr_10 of rvclkhdr_730 @[lib.scala 368:23] rvclkhdr_10.clock <= clock rvclkhdr_10.reset <= reset rvclkhdr_10.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_10.io.en <= _T_475 @[lib.scala 371:17] + rvclkhdr_10.io.en <= _T_485 @[lib.scala 371:17] rvclkhdr_10.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg mrac : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] mrac <= mrac_in @[lib.scala 374:16] - io.dec_tlu_mrac_ff <= mrac @[dec_tlu_ctl.scala 1807:21] - node _T_476 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1815:62] - node _T_477 = eq(_T_476, UInt<12>("h0bc0")) @[dec_tlu_ctl.scala 1815:69] - node wr_mdeau_r = and(io.dec_csr_wen_r_mod, _T_477) @[dec_tlu_ctl.scala 1815:40] - node _T_478 = not(wr_mdeau_r) @[dec_tlu_ctl.scala 1825:59] - node _T_479 = and(io.mdseac_locked_f, _T_478) @[dec_tlu_ctl.scala 1825:57] - node _T_480 = or(mdseac_en, _T_479) @[dec_tlu_ctl.scala 1825:35] - io.mdseac_locked_ns <= _T_480 @[dec_tlu_ctl.scala 1825:22] - node _T_481 = or(io.lsu_imprecise_error_store_any, io.lsu_imprecise_error_load_any) @[dec_tlu_ctl.scala 1827:49] - node _T_482 = not(io.nmi_int_detected_f) @[dec_tlu_ctl.scala 1827:86] - node _T_483 = and(_T_481, _T_482) @[dec_tlu_ctl.scala 1827:84] - node _T_484 = not(io.mdseac_locked_f) @[dec_tlu_ctl.scala 1827:111] - node _T_485 = and(_T_483, _T_484) @[dec_tlu_ctl.scala 1827:109] - mdseac_en <= _T_485 @[dec_tlu_ctl.scala 1827:12] - node _T_486 = bits(mdseac_en, 0, 0) @[dec_tlu_ctl.scala 1829:64] + io.dec_tlu_mrac_ff <= mrac @[dec_tlu_ctl.scala 1805:21] + node _T_486 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1813:62] + node _T_487 = eq(_T_486, UInt<12>("h0bc0")) @[dec_tlu_ctl.scala 1813:69] + node wr_mdeau_r = and(io.dec_csr_wen_r_mod, _T_487) @[dec_tlu_ctl.scala 1813:40] + node _T_488 = not(wr_mdeau_r) @[dec_tlu_ctl.scala 1823:59] + node _T_489 = and(io.mdseac_locked_f, _T_488) @[dec_tlu_ctl.scala 1823:57] + node _T_490 = or(mdseac_en, _T_489) @[dec_tlu_ctl.scala 1823:35] + io.mdseac_locked_ns <= _T_490 @[dec_tlu_ctl.scala 1823:22] + node _T_491 = or(io.lsu_imprecise_error_store_any, io.lsu_imprecise_error_load_any) @[dec_tlu_ctl.scala 1825:49] + node _T_492 = not(io.nmi_int_detected_f) @[dec_tlu_ctl.scala 1825:86] + node _T_493 = and(_T_491, _T_492) @[dec_tlu_ctl.scala 1825:84] + node _T_494 = not(io.mdseac_locked_f) @[dec_tlu_ctl.scala 1825:111] + node _T_495 = and(_T_493, _T_494) @[dec_tlu_ctl.scala 1825:109] + mdseac_en <= _T_495 @[dec_tlu_ctl.scala 1825:12] + node _T_496 = bits(mdseac_en, 0, 0) @[dec_tlu_ctl.scala 1827:64] inst rvclkhdr_11 of rvclkhdr_731 @[lib.scala 368:23] rvclkhdr_11.clock <= clock rvclkhdr_11.reset <= reset rvclkhdr_11.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_11.io.en <= _T_486 @[lib.scala 371:17] + rvclkhdr_11.io.en <= _T_496 @[lib.scala 371:17] rvclkhdr_11.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg mdseac : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] mdseac <= io.lsu_imprecise_error_addr_any @[lib.scala 374:16] - node _T_487 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1838:61] - node _T_488 = eq(_T_487, UInt<12>("h07c6")) @[dec_tlu_ctl.scala 1838:68] - node wr_mpmc_r = and(io.dec_csr_wen_r_mod, _T_488) @[dec_tlu_ctl.scala 1838:39] - node _T_489 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1842:51] - node _T_490 = and(wr_mpmc_r, _T_489) @[dec_tlu_ctl.scala 1842:30] - node _T_491 = not(io.internal_dbg_halt_mode_f2) @[dec_tlu_ctl.scala 1842:57] - node _T_492 = and(_T_490, _T_491) @[dec_tlu_ctl.scala 1842:55] - node _T_493 = not(io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 1842:89] - node _T_494 = and(_T_492, _T_493) @[dec_tlu_ctl.scala 1842:87] - io.fw_halt_req <= _T_494 @[dec_tlu_ctl.scala 1842:17] + node _T_497 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1836:61] + node _T_498 = eq(_T_497, UInt<12>("h07c6")) @[dec_tlu_ctl.scala 1836:68] + node wr_mpmc_r = and(io.dec_csr_wen_r_mod, _T_498) @[dec_tlu_ctl.scala 1836:39] + node _T_499 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1840:51] + node _T_500 = and(wr_mpmc_r, _T_499) @[dec_tlu_ctl.scala 1840:30] + node _T_501 = not(io.internal_dbg_halt_mode_f2) @[dec_tlu_ctl.scala 1840:57] + node _T_502 = and(_T_500, _T_501) @[dec_tlu_ctl.scala 1840:55] + node _T_503 = not(io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 1840:89] + node _T_504 = and(_T_502, _T_503) @[dec_tlu_ctl.scala 1840:87] + io.fw_halt_req <= _T_504 @[dec_tlu_ctl.scala 1840:17] wire fw_halted_ns : UInt<1> fw_halted_ns <= UInt<1>("h00") - reg fw_halted : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1844:48] - fw_halted <= fw_halted_ns @[dec_tlu_ctl.scala 1844:48] - node _T_495 = or(io.fw_halt_req, fw_halted) @[dec_tlu_ctl.scala 1845:34] - node _T_496 = not(set_mie_pmu_fw_halt) @[dec_tlu_ctl.scala 1845:49] - node _T_497 = and(_T_495, _T_496) @[dec_tlu_ctl.scala 1845:47] - fw_halted_ns <= _T_497 @[dec_tlu_ctl.scala 1845:15] - node _T_498 = bits(wr_mpmc_r, 0, 0) @[dec_tlu_ctl.scala 1846:29] - node _T_499 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1846:57] - node _T_500 = not(_T_499) @[dec_tlu_ctl.scala 1846:37] - node _T_501 = not(mpmc) @[dec_tlu_ctl.scala 1846:62] - node _T_502 = mux(_T_498, _T_500, _T_501) @[dec_tlu_ctl.scala 1846:18] - mpmc_b_ns <= _T_502 @[dec_tlu_ctl.scala 1846:12] - reg _T_503 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1848:44] - _T_503 <= mpmc_b_ns @[dec_tlu_ctl.scala 1848:44] - mpmc_b <= _T_503 @[dec_tlu_ctl.scala 1848:9] - node _T_504 = not(mpmc_b) @[dec_tlu_ctl.scala 1851:10] - mpmc <= _T_504 @[dec_tlu_ctl.scala 1851:7] - node _T_505 = bits(io.dec_csr_wrdata_r, 31, 27) @[dec_tlu_ctl.scala 1860:40] - node _T_506 = gt(_T_505, UInt<5>("h01a")) @[dec_tlu_ctl.scala 1860:48] - node _T_507 = bits(io.dec_csr_wrdata_r, 31, 27) @[dec_tlu_ctl.scala 1860:92] - node csr_sat = mux(_T_506, UInt<5>("h01a"), _T_507) @[dec_tlu_ctl.scala 1860:19] - node _T_508 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1862:63] - node _T_509 = eq(_T_508, UInt<12>("h07f0")) @[dec_tlu_ctl.scala 1862:70] - node wr_micect_r = and(io.dec_csr_wen_r_mod, _T_509) @[dec_tlu_ctl.scala 1862:41] - node _T_510 = cat(UInt<26>("h00"), io.ic_perr_r_d1) @[Cat.scala 29:58] - node _T_511 = add(micect, _T_510) @[dec_tlu_ctl.scala 1863:23] - node _T_512 = tail(_T_511, 1) @[dec_tlu_ctl.scala 1863:23] - micect_inc <= _T_512 @[dec_tlu_ctl.scala 1863:13] - node _T_513 = bits(wr_micect_r, 0, 0) @[dec_tlu_ctl.scala 1864:35] - node _T_514 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1864:75] - node _T_515 = cat(csr_sat, _T_514) @[Cat.scala 29:58] - node _T_516 = bits(micect, 31, 27) @[dec_tlu_ctl.scala 1864:95] - node _T_517 = cat(_T_516, micect_inc) @[Cat.scala 29:58] - node micect_ns = mux(_T_513, _T_515, _T_517) @[dec_tlu_ctl.scala 1864:22] - node _T_518 = or(wr_micect_r, io.ic_perr_r_d1) @[dec_tlu_ctl.scala 1866:42] - node _T_519 = bits(_T_518, 0, 0) @[dec_tlu_ctl.scala 1866:61] + reg fw_halted : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1842:48] + fw_halted <= fw_halted_ns @[dec_tlu_ctl.scala 1842:48] + node _T_505 = or(io.fw_halt_req, fw_halted) @[dec_tlu_ctl.scala 1843:34] + node _T_506 = not(set_mie_pmu_fw_halt) @[dec_tlu_ctl.scala 1843:49] + node _T_507 = and(_T_505, _T_506) @[dec_tlu_ctl.scala 1843:47] + fw_halted_ns <= _T_507 @[dec_tlu_ctl.scala 1843:15] + node _T_508 = bits(wr_mpmc_r, 0, 0) @[dec_tlu_ctl.scala 1844:29] + node _T_509 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1844:57] + node _T_510 = not(_T_509) @[dec_tlu_ctl.scala 1844:37] + node _T_511 = not(mpmc) @[dec_tlu_ctl.scala 1844:62] + node _T_512 = mux(_T_508, _T_510, _T_511) @[dec_tlu_ctl.scala 1844:18] + mpmc_b_ns <= _T_512 @[dec_tlu_ctl.scala 1844:12] + reg _T_513 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1846:44] + _T_513 <= mpmc_b_ns @[dec_tlu_ctl.scala 1846:44] + mpmc_b <= _T_513 @[dec_tlu_ctl.scala 1846:9] + node _T_514 = not(mpmc_b) @[dec_tlu_ctl.scala 1849:10] + mpmc <= _T_514 @[dec_tlu_ctl.scala 1849:7] + node _T_515 = bits(io.dec_csr_wrdata_r, 31, 27) @[dec_tlu_ctl.scala 1858:40] + node _T_516 = gt(_T_515, UInt<5>("h01a")) @[dec_tlu_ctl.scala 1858:48] + node _T_517 = bits(io.dec_csr_wrdata_r, 31, 27) @[dec_tlu_ctl.scala 1858:92] + node csr_sat = mux(_T_516, UInt<5>("h01a"), _T_517) @[dec_tlu_ctl.scala 1858:19] + node _T_518 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1860:63] + node _T_519 = eq(_T_518, UInt<12>("h07f0")) @[dec_tlu_ctl.scala 1860:70] + node wr_micect_r = and(io.dec_csr_wen_r_mod, _T_519) @[dec_tlu_ctl.scala 1860:41] + node _T_520 = cat(UInt<26>("h00"), io.ic_perr_r_d1) @[Cat.scala 29:58] + node _T_521 = add(micect, _T_520) @[dec_tlu_ctl.scala 1861:23] + node _T_522 = tail(_T_521, 1) @[dec_tlu_ctl.scala 1861:23] + micect_inc <= _T_522 @[dec_tlu_ctl.scala 1861:13] + node _T_523 = bits(wr_micect_r, 0, 0) @[dec_tlu_ctl.scala 1862:35] + node _T_524 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1862:75] + node _T_525 = cat(csr_sat, _T_524) @[Cat.scala 29:58] + node _T_526 = bits(micect, 31, 27) @[dec_tlu_ctl.scala 1862:95] + node _T_527 = cat(_T_526, micect_inc) @[Cat.scala 29:58] + node micect_ns = mux(_T_523, _T_525, _T_527) @[dec_tlu_ctl.scala 1862:22] + node _T_528 = or(wr_micect_r, io.ic_perr_r_d1) @[dec_tlu_ctl.scala 1864:42] + node _T_529 = bits(_T_528, 0, 0) @[dec_tlu_ctl.scala 1864:61] inst rvclkhdr_12 of rvclkhdr_732 @[lib.scala 368:23] rvclkhdr_12.clock <= clock rvclkhdr_12.reset <= reset rvclkhdr_12.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_12.io.en <= _T_519 @[lib.scala 371:17] + rvclkhdr_12.io.en <= _T_529 @[lib.scala 371:17] rvclkhdr_12.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_520 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_520 <= micect_ns @[lib.scala 374:16] - micect <= _T_520 @[dec_tlu_ctl.scala 1866:9] - node _T_521 = bits(micect, 31, 27) @[dec_tlu_ctl.scala 1868:48] - node _T_522 = dshl(UInt<32>("h0ffffffff"), _T_521) @[dec_tlu_ctl.scala 1868:39] - node _T_523 = bits(micect, 26, 0) @[dec_tlu_ctl.scala 1868:79] - node _T_524 = cat(UInt<5>("h00"), _T_523) @[Cat.scala 29:58] - node _T_525 = and(_T_522, _T_524) @[dec_tlu_ctl.scala 1868:57] - node _T_526 = orr(_T_525) @[dec_tlu_ctl.scala 1868:88] - mice_ce_req <= _T_526 @[dec_tlu_ctl.scala 1868:14] - node _T_527 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1877:69] - node _T_528 = eq(_T_527, UInt<12>("h07f1")) @[dec_tlu_ctl.scala 1877:76] - node wr_miccmect_r = and(io.dec_csr_wen_r_mod, _T_528) @[dec_tlu_ctl.scala 1877:47] - node _T_529 = bits(miccmect, 26, 0) @[dec_tlu_ctl.scala 1878:26] - node _T_530 = or(io.iccm_sbecc_r_d1, io.iccm_dma_sb_error) @[dec_tlu_ctl.scala 1878:70] - node _T_531 = cat(UInt<26>("h00"), _T_530) @[Cat.scala 29:58] - node _T_532 = add(_T_529, _T_531) @[dec_tlu_ctl.scala 1878:33] - node _T_533 = tail(_T_532, 1) @[dec_tlu_ctl.scala 1878:33] - miccmect_inc <= _T_533 @[dec_tlu_ctl.scala 1878:15] - node _T_534 = bits(wr_miccmect_r, 0, 0) @[dec_tlu_ctl.scala 1879:45] - node _T_535 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1879:85] - node _T_536 = cat(csr_sat, _T_535) @[Cat.scala 29:58] - node _T_537 = bits(miccmect, 31, 27) @[dec_tlu_ctl.scala 1879:107] - node _T_538 = cat(_T_537, miccmect_inc) @[Cat.scala 29:58] - node miccmect_ns = mux(_T_534, _T_536, _T_538) @[dec_tlu_ctl.scala 1879:30] - node _T_539 = or(wr_miccmect_r, io.iccm_sbecc_r_d1) @[dec_tlu_ctl.scala 1881:48] - node _T_540 = or(_T_539, io.iccm_dma_sb_error) @[dec_tlu_ctl.scala 1881:69] - node _T_541 = bits(_T_540, 0, 0) @[dec_tlu_ctl.scala 1881:93] + reg _T_530 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_530 <= micect_ns @[lib.scala 374:16] + micect <= _T_530 @[dec_tlu_ctl.scala 1864:9] + node _T_531 = bits(micect, 31, 27) @[dec_tlu_ctl.scala 1866:48] + node _T_532 = dshl(UInt<32>("h0ffffffff"), _T_531) @[dec_tlu_ctl.scala 1866:39] + node _T_533 = bits(micect, 26, 0) @[dec_tlu_ctl.scala 1866:79] + node _T_534 = cat(UInt<5>("h00"), _T_533) @[Cat.scala 29:58] + node _T_535 = and(_T_532, _T_534) @[dec_tlu_ctl.scala 1866:57] + node _T_536 = orr(_T_535) @[dec_tlu_ctl.scala 1866:88] + mice_ce_req <= _T_536 @[dec_tlu_ctl.scala 1866:14] + node _T_537 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1875:69] + node _T_538 = eq(_T_537, UInt<12>("h07f1")) @[dec_tlu_ctl.scala 1875:76] + node wr_miccmect_r = and(io.dec_csr_wen_r_mod, _T_538) @[dec_tlu_ctl.scala 1875:47] + node _T_539 = bits(miccmect, 26, 0) @[dec_tlu_ctl.scala 1876:26] + node _T_540 = or(io.iccm_sbecc_r_d1, io.iccm_dma_sb_error) @[dec_tlu_ctl.scala 1876:70] + node _T_541 = cat(UInt<26>("h00"), _T_540) @[Cat.scala 29:58] + node _T_542 = add(_T_539, _T_541) @[dec_tlu_ctl.scala 1876:33] + node _T_543 = tail(_T_542, 1) @[dec_tlu_ctl.scala 1876:33] + miccmect_inc <= _T_543 @[dec_tlu_ctl.scala 1876:15] + node _T_544 = bits(wr_miccmect_r, 0, 0) @[dec_tlu_ctl.scala 1877:45] + node _T_545 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1877:85] + node _T_546 = cat(csr_sat, _T_545) @[Cat.scala 29:58] + node _T_547 = bits(miccmect, 31, 27) @[dec_tlu_ctl.scala 1877:107] + node _T_548 = cat(_T_547, miccmect_inc) @[Cat.scala 29:58] + node miccmect_ns = mux(_T_544, _T_546, _T_548) @[dec_tlu_ctl.scala 1877:30] + node _T_549 = or(wr_miccmect_r, io.iccm_sbecc_r_d1) @[dec_tlu_ctl.scala 1879:48] + node _T_550 = or(_T_549, io.iccm_dma_sb_error) @[dec_tlu_ctl.scala 1879:69] + node _T_551 = bits(_T_550, 0, 0) @[dec_tlu_ctl.scala 1879:93] inst rvclkhdr_13 of rvclkhdr_733 @[lib.scala 368:23] rvclkhdr_13.clock <= clock rvclkhdr_13.reset <= reset rvclkhdr_13.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_13.io.en <= _T_541 @[lib.scala 371:17] + rvclkhdr_13.io.en <= _T_551 @[lib.scala 371:17] rvclkhdr_13.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_542 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_542 <= miccmect_ns @[lib.scala 374:16] - miccmect <= _T_542 @[dec_tlu_ctl.scala 1881:11] - node _T_543 = bits(miccmect, 31, 27) @[dec_tlu_ctl.scala 1883:51] - node _T_544 = dshl(UInt<32>("h0ffffffff"), _T_543) @[dec_tlu_ctl.scala 1883:40] - node _T_545 = bits(miccmect, 26, 0) @[dec_tlu_ctl.scala 1883:84] - node _T_546 = cat(UInt<5>("h00"), _T_545) @[Cat.scala 29:58] - node _T_547 = and(_T_544, _T_546) @[dec_tlu_ctl.scala 1883:60] - node _T_548 = orr(_T_547) @[dec_tlu_ctl.scala 1883:93] - miccme_ce_req <= _T_548 @[dec_tlu_ctl.scala 1883:15] - node _T_549 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1892:69] - node _T_550 = eq(_T_549, UInt<12>("h07f2")) @[dec_tlu_ctl.scala 1892:76] - node wr_mdccmect_r = and(io.dec_csr_wen_r_mod, _T_550) @[dec_tlu_ctl.scala 1892:47] - node _T_551 = bits(mdccmect, 26, 0) @[dec_tlu_ctl.scala 1893:26] - node _T_552 = cat(UInt<26>("h00"), io.lsu_single_ecc_error_r_d1) @[Cat.scala 29:58] - node _T_553 = add(_T_551, _T_552) @[dec_tlu_ctl.scala 1893:33] - node _T_554 = tail(_T_553, 1) @[dec_tlu_ctl.scala 1893:33] - mdccmect_inc <= _T_554 @[dec_tlu_ctl.scala 1893:15] - node _T_555 = bits(wr_mdccmect_r, 0, 0) @[dec_tlu_ctl.scala 1894:45] - node _T_556 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1894:85] - node _T_557 = cat(csr_sat, _T_556) @[Cat.scala 29:58] - node _T_558 = bits(mdccmect, 31, 27) @[dec_tlu_ctl.scala 1894:107] - node _T_559 = cat(_T_558, mdccmect_inc) @[Cat.scala 29:58] - node mdccmect_ns = mux(_T_555, _T_557, _T_559) @[dec_tlu_ctl.scala 1894:30] - node _T_560 = or(wr_mdccmect_r, io.lsu_single_ecc_error_r_d1) @[dec_tlu_ctl.scala 1896:49] - node _T_561 = bits(_T_560, 0, 0) @[dec_tlu_ctl.scala 1896:81] + reg _T_552 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_552 <= miccmect_ns @[lib.scala 374:16] + miccmect <= _T_552 @[dec_tlu_ctl.scala 1879:11] + node _T_553 = bits(miccmect, 31, 27) @[dec_tlu_ctl.scala 1881:51] + node _T_554 = dshl(UInt<32>("h0ffffffff"), _T_553) @[dec_tlu_ctl.scala 1881:40] + node _T_555 = bits(miccmect, 26, 0) @[dec_tlu_ctl.scala 1881:84] + node _T_556 = cat(UInt<5>("h00"), _T_555) @[Cat.scala 29:58] + node _T_557 = and(_T_554, _T_556) @[dec_tlu_ctl.scala 1881:60] + node _T_558 = orr(_T_557) @[dec_tlu_ctl.scala 1881:93] + miccme_ce_req <= _T_558 @[dec_tlu_ctl.scala 1881:15] + node _T_559 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1890:69] + node _T_560 = eq(_T_559, UInt<12>("h07f2")) @[dec_tlu_ctl.scala 1890:76] + node wr_mdccmect_r = and(io.dec_csr_wen_r_mod, _T_560) @[dec_tlu_ctl.scala 1890:47] + node _T_561 = bits(mdccmect, 26, 0) @[dec_tlu_ctl.scala 1891:26] + node _T_562 = cat(UInt<26>("h00"), io.lsu_single_ecc_error_r_d1) @[Cat.scala 29:58] + node _T_563 = add(_T_561, _T_562) @[dec_tlu_ctl.scala 1891:33] + node _T_564 = tail(_T_563, 1) @[dec_tlu_ctl.scala 1891:33] + mdccmect_inc <= _T_564 @[dec_tlu_ctl.scala 1891:15] + node _T_565 = bits(wr_mdccmect_r, 0, 0) @[dec_tlu_ctl.scala 1892:45] + node _T_566 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1892:85] + node _T_567 = cat(csr_sat, _T_566) @[Cat.scala 29:58] + node _T_568 = bits(mdccmect, 31, 27) @[dec_tlu_ctl.scala 1892:107] + node _T_569 = cat(_T_568, mdccmect_inc) @[Cat.scala 29:58] + node mdccmect_ns = mux(_T_565, _T_567, _T_569) @[dec_tlu_ctl.scala 1892:30] + node _T_570 = or(wr_mdccmect_r, io.lsu_single_ecc_error_r_d1) @[dec_tlu_ctl.scala 1894:49] + node _T_571 = bits(_T_570, 0, 0) @[dec_tlu_ctl.scala 1894:81] inst rvclkhdr_14 of rvclkhdr_734 @[lib.scala 368:23] rvclkhdr_14.clock <= clock rvclkhdr_14.reset <= reset rvclkhdr_14.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_14.io.en <= _T_561 @[lib.scala 371:17] + rvclkhdr_14.io.en <= _T_571 @[lib.scala 371:17] rvclkhdr_14.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_562 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_562 <= mdccmect_ns @[lib.scala 374:16] - mdccmect <= _T_562 @[dec_tlu_ctl.scala 1896:11] - node _T_563 = bits(mdccmect, 31, 27) @[dec_tlu_ctl.scala 1898:52] - node _T_564 = dshl(UInt<32>("h0ffffffff"), _T_563) @[dec_tlu_ctl.scala 1898:41] - node _T_565 = bits(mdccmect, 26, 0) @[dec_tlu_ctl.scala 1898:85] - node _T_566 = cat(UInt<5>("h00"), _T_565) @[Cat.scala 29:58] - node _T_567 = and(_T_564, _T_566) @[dec_tlu_ctl.scala 1898:61] - node _T_568 = orr(_T_567) @[dec_tlu_ctl.scala 1898:94] - mdccme_ce_req <= _T_568 @[dec_tlu_ctl.scala 1898:16] - node _T_569 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1908:62] - node _T_570 = eq(_T_569, UInt<12>("h07ce")) @[dec_tlu_ctl.scala 1908:69] - node wr_mfdht_r = and(io.dec_csr_wen_r_mod, _T_570) @[dec_tlu_ctl.scala 1908:40] - node _T_571 = bits(wr_mfdht_r, 0, 0) @[dec_tlu_ctl.scala 1910:32] - node _T_572 = bits(io.dec_csr_wrdata_r, 5, 0) @[dec_tlu_ctl.scala 1910:59] - node mfdht_ns = mux(_T_571, _T_572, mfdht) @[dec_tlu_ctl.scala 1910:20] - reg _T_573 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1912:43] - _T_573 <= mfdht_ns @[dec_tlu_ctl.scala 1912:43] - mfdht <= _T_573 @[dec_tlu_ctl.scala 1912:8] - node _T_574 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1921:62] - node _T_575 = eq(_T_574, UInt<12>("h07cf")) @[dec_tlu_ctl.scala 1921:69] - node wr_mfdhs_r = and(io.dec_csr_wen_r_mod, _T_575) @[dec_tlu_ctl.scala 1921:40] - node _T_576 = bits(wr_mfdhs_r, 0, 0) @[dec_tlu_ctl.scala 1923:32] - node _T_577 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 1923:60] - node _T_578 = not(io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 1924:43] - node _T_579 = and(io.dbg_tlu_halted, _T_578) @[dec_tlu_ctl.scala 1924:41] - node _T_580 = bits(_T_579, 0, 0) @[dec_tlu_ctl.scala 1924:65] - node _T_581 = not(io.lsu_idle_any_f) @[dec_tlu_ctl.scala 1924:78] - node _T_582 = not(io.ifu_miss_state_idle_f) @[dec_tlu_ctl.scala 1924:98] - node _T_583 = cat(_T_581, _T_582) @[Cat.scala 29:58] - node _T_584 = mux(_T_580, _T_583, mfdhs) @[dec_tlu_ctl.scala 1924:21] - node mfdhs_ns = mux(_T_576, _T_577, _T_584) @[dec_tlu_ctl.scala 1923:20] - node _T_585 = or(wr_mfdhs_r, io.dbg_tlu_halted) @[dec_tlu_ctl.scala 1926:71] - node _T_586 = bits(_T_585, 0, 0) @[dec_tlu_ctl.scala 1926:92] - reg _T_587 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_586 : @[Reg.scala 28:19] - _T_587 <= mfdhs_ns @[Reg.scala 28:23] + reg _T_572 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_572 <= mdccmect_ns @[lib.scala 374:16] + mdccmect <= _T_572 @[dec_tlu_ctl.scala 1894:11] + node _T_573 = bits(mdccmect, 31, 27) @[dec_tlu_ctl.scala 1896:52] + node _T_574 = dshl(UInt<32>("h0ffffffff"), _T_573) @[dec_tlu_ctl.scala 1896:41] + node _T_575 = bits(mdccmect, 26, 0) @[dec_tlu_ctl.scala 1896:85] + node _T_576 = cat(UInt<5>("h00"), _T_575) @[Cat.scala 29:58] + node _T_577 = and(_T_574, _T_576) @[dec_tlu_ctl.scala 1896:61] + node _T_578 = orr(_T_577) @[dec_tlu_ctl.scala 1896:94] + mdccme_ce_req <= _T_578 @[dec_tlu_ctl.scala 1896:16] + node _T_579 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1906:62] + node _T_580 = eq(_T_579, UInt<12>("h07ce")) @[dec_tlu_ctl.scala 1906:69] + node wr_mfdht_r = and(io.dec_csr_wen_r_mod, _T_580) @[dec_tlu_ctl.scala 1906:40] + node _T_581 = bits(wr_mfdht_r, 0, 0) @[dec_tlu_ctl.scala 1908:32] + node _T_582 = bits(io.dec_csr_wrdata_r, 5, 0) @[dec_tlu_ctl.scala 1908:59] + node mfdht_ns = mux(_T_581, _T_582, mfdht) @[dec_tlu_ctl.scala 1908:20] + reg _T_583 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1910:43] + _T_583 <= mfdht_ns @[dec_tlu_ctl.scala 1910:43] + mfdht <= _T_583 @[dec_tlu_ctl.scala 1910:8] + node _T_584 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1919:62] + node _T_585 = eq(_T_584, UInt<12>("h07cf")) @[dec_tlu_ctl.scala 1919:69] + node wr_mfdhs_r = and(io.dec_csr_wen_r_mod, _T_585) @[dec_tlu_ctl.scala 1919:40] + node _T_586 = bits(wr_mfdhs_r, 0, 0) @[dec_tlu_ctl.scala 1921:32] + node _T_587 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 1921:60] + node _T_588 = not(io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 1922:43] + node _T_589 = and(io.dbg_tlu_halted, _T_588) @[dec_tlu_ctl.scala 1922:41] + node _T_590 = bits(_T_589, 0, 0) @[dec_tlu_ctl.scala 1922:65] + node _T_591 = not(io.lsu_idle_any_f) @[dec_tlu_ctl.scala 1922:78] + node _T_592 = not(io.ifu_miss_state_idle_f) @[dec_tlu_ctl.scala 1922:98] + node _T_593 = cat(_T_591, _T_592) @[Cat.scala 29:58] + node _T_594 = mux(_T_590, _T_593, mfdhs) @[dec_tlu_ctl.scala 1922:21] + node mfdhs_ns = mux(_T_586, _T_587, _T_594) @[dec_tlu_ctl.scala 1921:20] + node _T_595 = or(wr_mfdhs_r, io.dbg_tlu_halted) @[dec_tlu_ctl.scala 1924:71] + node _T_596 = bits(_T_595, 0, 0) @[dec_tlu_ctl.scala 1924:92] + reg _T_597 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_596 : @[Reg.scala 28:19] + _T_597 <= mfdhs_ns @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mfdhs <= _T_587 @[dec_tlu_ctl.scala 1926:8] - node _T_588 = bits(io.debug_halt_req_f, 0, 0) @[dec_tlu_ctl.scala 1928:47] - node _T_589 = add(force_halt_ctr_f, UInt<32>("h01")) @[dec_tlu_ctl.scala 1928:74] - node _T_590 = tail(_T_589, 1) @[dec_tlu_ctl.scala 1928:74] - node _T_591 = bits(io.dbg_tlu_halted_f, 0, 0) @[dec_tlu_ctl.scala 1929:48] - node _T_592 = mux(_T_591, UInt<32>("h00"), force_halt_ctr_f) @[dec_tlu_ctl.scala 1929:27] - node force_halt_ctr = mux(_T_588, _T_590, _T_592) @[dec_tlu_ctl.scala 1928:26] - node _T_593 = bits(mfdht, 0, 0) @[dec_tlu_ctl.scala 1931:81] - reg _T_594 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_593 : @[Reg.scala 28:19] - _T_594 <= force_halt_ctr @[Reg.scala 28:23] + mfdhs <= _T_597 @[dec_tlu_ctl.scala 1924:8] + node _T_598 = bits(io.debug_halt_req_f, 0, 0) @[dec_tlu_ctl.scala 1926:47] + node _T_599 = add(force_halt_ctr_f, UInt<32>("h01")) @[dec_tlu_ctl.scala 1926:74] + node _T_600 = tail(_T_599, 1) @[dec_tlu_ctl.scala 1926:74] + node _T_601 = bits(io.dbg_tlu_halted_f, 0, 0) @[dec_tlu_ctl.scala 1927:48] + node _T_602 = mux(_T_601, UInt<32>("h00"), force_halt_ctr_f) @[dec_tlu_ctl.scala 1927:27] + node force_halt_ctr = mux(_T_598, _T_600, _T_602) @[dec_tlu_ctl.scala 1926:26] + node _T_603 = bits(mfdht, 0, 0) @[dec_tlu_ctl.scala 1929:81] + reg _T_604 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_603 : @[Reg.scala 28:19] + _T_604 <= force_halt_ctr @[Reg.scala 28:23] skip @[Reg.scala 28:19] - force_halt_ctr_f <= _T_594 @[dec_tlu_ctl.scala 1931:19] - node _T_595 = bits(mfdht, 0, 0) @[dec_tlu_ctl.scala 1933:24] - node _T_596 = bits(mfdht, 5, 1) @[dec_tlu_ctl.scala 1933:79] - node _T_597 = dshl(UInt<32>("h0ffffffff"), _T_596) @[dec_tlu_ctl.scala 1933:71] - node _T_598 = and(force_halt_ctr_f, _T_597) @[dec_tlu_ctl.scala 1933:48] - node _T_599 = orr(_T_598) @[dec_tlu_ctl.scala 1933:87] - node _T_600 = and(_T_595, _T_599) @[dec_tlu_ctl.scala 1933:28] - io.force_halt <= _T_600 @[dec_tlu_ctl.scala 1933:16] - node _T_601 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1941:62] - node _T_602 = eq(_T_601, UInt<12>("h0bc8")) @[dec_tlu_ctl.scala 1941:69] - node wr_meivt_r = and(io.dec_csr_wen_r_mod, _T_602) @[dec_tlu_ctl.scala 1941:40] - node _T_603 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 1943:40] - node _T_604 = bits(wr_meivt_r, 0, 0) @[dec_tlu_ctl.scala 1943:59] + force_halt_ctr_f <= _T_604 @[dec_tlu_ctl.scala 1929:19] + node _T_605 = bits(mfdht, 0, 0) @[dec_tlu_ctl.scala 1931:24] + node _T_606 = bits(mfdht, 5, 1) @[dec_tlu_ctl.scala 1931:79] + node _T_607 = dshl(UInt<32>("h0ffffffff"), _T_606) @[dec_tlu_ctl.scala 1931:71] + node _T_608 = and(force_halt_ctr_f, _T_607) @[dec_tlu_ctl.scala 1931:48] + node _T_609 = orr(_T_608) @[dec_tlu_ctl.scala 1931:87] + node _T_610 = and(_T_605, _T_609) @[dec_tlu_ctl.scala 1931:28] + io.force_halt <= _T_610 @[dec_tlu_ctl.scala 1931:16] + node _T_611 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1939:62] + node _T_612 = eq(_T_611, UInt<12>("h0bc8")) @[dec_tlu_ctl.scala 1939:69] + node wr_meivt_r = and(io.dec_csr_wen_r_mod, _T_612) @[dec_tlu_ctl.scala 1939:40] + node _T_613 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 1941:40] + node _T_614 = bits(wr_meivt_r, 0, 0) @[dec_tlu_ctl.scala 1941:59] inst rvclkhdr_15 of rvclkhdr_735 @[lib.scala 368:23] rvclkhdr_15.clock <= clock rvclkhdr_15.reset <= reset rvclkhdr_15.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_15.io.en <= _T_604 @[lib.scala 371:17] + rvclkhdr_15.io.en <= _T_614 @[lib.scala 371:17] rvclkhdr_15.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg meivt : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - meivt <= _T_603 @[lib.scala 374:16] - node _T_605 = bits(wr_meicpct_r, 0, 0) @[dec_tlu_ctl.scala 1955:49] + meivt <= _T_613 @[lib.scala 374:16] + node _T_615 = bits(wr_meicpct_r, 0, 0) @[dec_tlu_ctl.scala 1953:49] inst rvclkhdr_16 of rvclkhdr_736 @[lib.scala 368:23] rvclkhdr_16.clock <= clock rvclkhdr_16.reset <= reset rvclkhdr_16.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_16.io.en <= _T_605 @[lib.scala 371:17] + rvclkhdr_16.io.en <= _T_615 @[lib.scala 371:17] rvclkhdr_16.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg meihap : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] meihap <= io.pic_claimid @[lib.scala 374:16] - node _T_606 = cat(meivt, meihap) @[Cat.scala 29:58] - io.dec_tlu_meihap <= _T_606 @[dec_tlu_ctl.scala 1956:20] - node _T_607 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1965:65] - node _T_608 = eq(_T_607, UInt<12>("h0bcc")) @[dec_tlu_ctl.scala 1965:72] - node wr_meicurpl_r = and(io.dec_csr_wen_r_mod, _T_608) @[dec_tlu_ctl.scala 1965:43] - node _T_609 = bits(wr_meicurpl_r, 0, 0) @[dec_tlu_ctl.scala 1966:38] - node _T_610 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1966:65] - node meicurpl_ns = mux(_T_609, _T_610, meicurpl) @[dec_tlu_ctl.scala 1966:23] - reg _T_611 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1968:46] - _T_611 <= meicurpl_ns @[dec_tlu_ctl.scala 1968:46] - meicurpl <= _T_611 @[dec_tlu_ctl.scala 1968:11] - io.dec_tlu_meicurpl <= meicurpl @[dec_tlu_ctl.scala 1970:22] - node _T_612 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1980:66] - node _T_613 = eq(_T_612, UInt<12>("h0bcb")) @[dec_tlu_ctl.scala 1980:73] - node _T_614 = and(io.dec_csr_wen_r_mod, _T_613) @[dec_tlu_ctl.scala 1980:44] - node wr_meicidpl_r = or(_T_614, io.take_ext_int_start) @[dec_tlu_ctl.scala 1980:88] - node _T_615 = bits(wr_meicpct_r, 0, 0) @[dec_tlu_ctl.scala 1982:37] - node _T_616 = bits(wr_meicidpl_r, 0, 0) @[dec_tlu_ctl.scala 1983:38] - node _T_617 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1983:65] - node _T_618 = mux(_T_616, _T_617, meicidpl) @[dec_tlu_ctl.scala 1983:23] - node meicidpl_ns = mux(_T_615, io.pic_pl, _T_618) @[dec_tlu_ctl.scala 1982:23] - reg _T_619 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1985:44] - _T_619 <= meicidpl_ns @[dec_tlu_ctl.scala 1985:44] - meicidpl <= _T_619 @[dec_tlu_ctl.scala 1985:11] - node _T_620 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1992:62] - node _T_621 = eq(_T_620, UInt<12>("h0bca")) @[dec_tlu_ctl.scala 1992:69] - node _T_622 = and(io.dec_csr_wen_r_mod, _T_621) @[dec_tlu_ctl.scala 1992:40] - node _T_623 = or(_T_622, io.take_ext_int_start) @[dec_tlu_ctl.scala 1992:83] - wr_meicpct_r <= _T_623 @[dec_tlu_ctl.scala 1992:15] - node _T_624 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2001:62] - node _T_625 = eq(_T_624, UInt<12>("h0bc9")) @[dec_tlu_ctl.scala 2001:69] - node wr_meipt_r = and(io.dec_csr_wen_r_mod, _T_625) @[dec_tlu_ctl.scala 2001:40] - node _T_626 = bits(wr_meipt_r, 0, 0) @[dec_tlu_ctl.scala 2002:32] - node _T_627 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 2002:59] - node meipt_ns = mux(_T_626, _T_627, meipt) @[dec_tlu_ctl.scala 2002:20] - reg _T_628 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2004:43] - _T_628 <= meipt_ns @[dec_tlu_ctl.scala 2004:43] - meipt <= _T_628 @[dec_tlu_ctl.scala 2004:8] - io.dec_tlu_meipt <= meipt @[dec_tlu_ctl.scala 2006:19] - node _T_629 = and(io.trigger_hit_r_d1, io.dcsr_single_step_done_f) @[dec_tlu_ctl.scala 2032:89] - node trigger_hit_for_dscr_cause_r_d1 = or(io.trigger_hit_dmode_r_d1, _T_629) @[dec_tlu_ctl.scala 2032:66] - node _T_630 = not(io.ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 2035:31] - node _T_631 = and(io.dcsr_single_step_done_f, _T_630) @[dec_tlu_ctl.scala 2035:29] - node _T_632 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2035:63] - node _T_633 = and(_T_631, _T_632) @[dec_tlu_ctl.scala 2035:61] - node _T_634 = not(io.debug_halt_req) @[dec_tlu_ctl.scala 2035:98] - node _T_635 = and(_T_633, _T_634) @[dec_tlu_ctl.scala 2035:96] - node _T_636 = bits(_T_635, 0, 0) @[dec_tlu_ctl.scala 2035:118] - node _T_637 = not(io.ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 2036:48] - node _T_638 = and(io.debug_halt_req, _T_637) @[dec_tlu_ctl.scala 2036:46] - node _T_639 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2036:80] - node _T_640 = and(_T_638, _T_639) @[dec_tlu_ctl.scala 2036:78] - node _T_641 = bits(_T_640, 0, 0) @[dec_tlu_ctl.scala 2036:114] - node _T_642 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2037:77] - node _T_643 = and(io.ebreak_to_debug_mode_r_d1, _T_642) @[dec_tlu_ctl.scala 2037:75] - node _T_644 = bits(_T_643, 0, 0) @[dec_tlu_ctl.scala 2037:111] - node _T_645 = bits(trigger_hit_for_dscr_cause_r_d1, 0, 0) @[dec_tlu_ctl.scala 2038:108] - node _T_646 = mux(_T_636, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_647 = mux(_T_641, UInt<3>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_648 = mux(_T_644, UInt<3>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_649 = mux(_T_645, UInt<3>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_650 = or(_T_646, _T_647) @[Mux.scala 27:72] - node _T_651 = or(_T_650, _T_648) @[Mux.scala 27:72] - node _T_652 = or(_T_651, _T_649) @[Mux.scala 27:72] + node _T_616 = cat(meivt, meihap) @[Cat.scala 29:58] + io.dec_tlu_meihap <= _T_616 @[dec_tlu_ctl.scala 1954:20] + node _T_617 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1963:65] + node _T_618 = eq(_T_617, UInt<12>("h0bcc")) @[dec_tlu_ctl.scala 1963:72] + node wr_meicurpl_r = and(io.dec_csr_wen_r_mod, _T_618) @[dec_tlu_ctl.scala 1963:43] + node _T_619 = bits(wr_meicurpl_r, 0, 0) @[dec_tlu_ctl.scala 1964:38] + node _T_620 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1964:65] + node meicurpl_ns = mux(_T_619, _T_620, meicurpl) @[dec_tlu_ctl.scala 1964:23] + reg _T_621 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1966:46] + _T_621 <= meicurpl_ns @[dec_tlu_ctl.scala 1966:46] + meicurpl <= _T_621 @[dec_tlu_ctl.scala 1966:11] + io.dec_tlu_meicurpl <= meicurpl @[dec_tlu_ctl.scala 1968:22] + node _T_622 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1978:66] + node _T_623 = eq(_T_622, UInt<12>("h0bcb")) @[dec_tlu_ctl.scala 1978:73] + node _T_624 = and(io.dec_csr_wen_r_mod, _T_623) @[dec_tlu_ctl.scala 1978:44] + node wr_meicidpl_r = or(_T_624, io.take_ext_int_start) @[dec_tlu_ctl.scala 1978:88] + node _T_625 = bits(wr_meicpct_r, 0, 0) @[dec_tlu_ctl.scala 1980:37] + node _T_626 = bits(wr_meicidpl_r, 0, 0) @[dec_tlu_ctl.scala 1981:38] + node _T_627 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1981:65] + node _T_628 = mux(_T_626, _T_627, meicidpl) @[dec_tlu_ctl.scala 1981:23] + node meicidpl_ns = mux(_T_625, io.pic_pl, _T_628) @[dec_tlu_ctl.scala 1980:23] + reg _T_629 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1983:44] + _T_629 <= meicidpl_ns @[dec_tlu_ctl.scala 1983:44] + meicidpl <= _T_629 @[dec_tlu_ctl.scala 1983:11] + node _T_630 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1990:62] + node _T_631 = eq(_T_630, UInt<12>("h0bca")) @[dec_tlu_ctl.scala 1990:69] + node _T_632 = and(io.dec_csr_wen_r_mod, _T_631) @[dec_tlu_ctl.scala 1990:40] + node _T_633 = or(_T_632, io.take_ext_int_start) @[dec_tlu_ctl.scala 1990:83] + wr_meicpct_r <= _T_633 @[dec_tlu_ctl.scala 1990:15] + node _T_634 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1999:62] + node _T_635 = eq(_T_634, UInt<12>("h0bc9")) @[dec_tlu_ctl.scala 1999:69] + node wr_meipt_r = and(io.dec_csr_wen_r_mod, _T_635) @[dec_tlu_ctl.scala 1999:40] + node _T_636 = bits(wr_meipt_r, 0, 0) @[dec_tlu_ctl.scala 2000:32] + node _T_637 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 2000:59] + node meipt_ns = mux(_T_636, _T_637, meipt) @[dec_tlu_ctl.scala 2000:20] + reg _T_638 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2002:43] + _T_638 <= meipt_ns @[dec_tlu_ctl.scala 2002:43] + meipt <= _T_638 @[dec_tlu_ctl.scala 2002:8] + io.dec_tlu_meipt <= meipt @[dec_tlu_ctl.scala 2004:19] + node _T_639 = and(io.trigger_hit_r_d1, io.dcsr_single_step_done_f) @[dec_tlu_ctl.scala 2030:89] + node trigger_hit_for_dscr_cause_r_d1 = or(io.trigger_hit_dmode_r_d1, _T_639) @[dec_tlu_ctl.scala 2030:66] + node _T_640 = not(io.ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 2033:31] + node _T_641 = and(io.dcsr_single_step_done_f, _T_640) @[dec_tlu_ctl.scala 2033:29] + node _T_642 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2033:63] + node _T_643 = and(_T_641, _T_642) @[dec_tlu_ctl.scala 2033:61] + node _T_644 = not(io.debug_halt_req) @[dec_tlu_ctl.scala 2033:98] + node _T_645 = and(_T_643, _T_644) @[dec_tlu_ctl.scala 2033:96] + node _T_646 = bits(_T_645, 0, 0) @[dec_tlu_ctl.scala 2033:118] + node _T_647 = not(io.ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 2034:48] + node _T_648 = and(io.debug_halt_req, _T_647) @[dec_tlu_ctl.scala 2034:46] + node _T_649 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2034:80] + node _T_650 = and(_T_648, _T_649) @[dec_tlu_ctl.scala 2034:78] + node _T_651 = bits(_T_650, 0, 0) @[dec_tlu_ctl.scala 2034:114] + node _T_652 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2035:77] + node _T_653 = and(io.ebreak_to_debug_mode_r_d1, _T_652) @[dec_tlu_ctl.scala 2035:75] + node _T_654 = bits(_T_653, 0, 0) @[dec_tlu_ctl.scala 2035:111] + node _T_655 = bits(trigger_hit_for_dscr_cause_r_d1, 0, 0) @[dec_tlu_ctl.scala 2036:108] + node _T_656 = mux(_T_646, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_657 = mux(_T_651, UInt<3>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_658 = mux(_T_654, UInt<3>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_659 = mux(_T_655, UInt<3>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_660 = or(_T_656, _T_657) @[Mux.scala 27:72] + node _T_661 = or(_T_660, _T_658) @[Mux.scala 27:72] + node _T_662 = or(_T_661, _T_659) @[Mux.scala 27:72] wire dcsr_cause : UInt<3> @[Mux.scala 27:72] - dcsr_cause <= _T_652 @[Mux.scala 27:72] - node _T_653 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2040:46] - node _T_654 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2040:91] - node _T_655 = eq(_T_654, UInt<12>("h07b0")) @[dec_tlu_ctl.scala 2040:98] - node wr_dcsr_r = and(_T_653, _T_655) @[dec_tlu_ctl.scala 2040:69] - node _T_656 = bits(io.dcsr, 8, 6) @[dec_tlu_ctl.scala 2046:69] - node _T_657 = eq(_T_656, UInt<3>("h03")) @[dec_tlu_ctl.scala 2046:75] - node dcsr_cause_upgradeable = and(io.internal_dbg_halt_mode_f, _T_657) @[dec_tlu_ctl.scala 2046:59] - node _T_658 = not(io.dbg_tlu_halted) @[dec_tlu_ctl.scala 2047:59] - node _T_659 = or(_T_658, dcsr_cause_upgradeable) @[dec_tlu_ctl.scala 2047:78] - node enter_debug_halt_req_le = and(io.enter_debug_halt_req, _T_659) @[dec_tlu_ctl.scala 2047:56] - node nmi_in_debug_mode = and(io.nmi_int_detected_f, io.internal_dbg_halt_mode_f) @[dec_tlu_ctl.scala 2049:48] - node _T_660 = bits(enter_debug_halt_req_le, 0, 0) @[dec_tlu_ctl.scala 2050:44] - node _T_661 = bits(io.dcsr, 15, 9) @[dec_tlu_ctl.scala 2050:64] - node _T_662 = bits(io.dcsr, 5, 2) @[dec_tlu_ctl.scala 2050:91] - node _T_663 = cat(_T_662, UInt<2>("h03")) @[Cat.scala 29:58] - node _T_664 = cat(_T_661, dcsr_cause) @[Cat.scala 29:58] - node _T_665 = cat(_T_664, _T_663) @[Cat.scala 29:58] - node _T_666 = bits(wr_dcsr_r, 0, 0) @[dec_tlu_ctl.scala 2051:18] - node _T_667 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 2051:49] - node _T_668 = bits(io.dec_csr_wrdata_r, 11, 10) @[dec_tlu_ctl.scala 2051:84] - node _T_669 = bits(io.dcsr, 8, 6) @[dec_tlu_ctl.scala 2051:110] - node _T_670 = bits(io.dcsr, 3, 3) @[dec_tlu_ctl.scala 2051:154] - node _T_671 = or(nmi_in_debug_mode, _T_670) @[dec_tlu_ctl.scala 2051:145] - node _T_672 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2051:178] + dcsr_cause <= _T_662 @[Mux.scala 27:72] + node _T_663 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2038:46] + node _T_664 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2038:91] + node _T_665 = eq(_T_664, UInt<12>("h07b0")) @[dec_tlu_ctl.scala 2038:98] + node wr_dcsr_r = and(_T_663, _T_665) @[dec_tlu_ctl.scala 2038:69] + node _T_666 = bits(io.dcsr, 8, 6) @[dec_tlu_ctl.scala 2044:69] + node _T_667 = eq(_T_666, UInt<3>("h03")) @[dec_tlu_ctl.scala 2044:75] + node dcsr_cause_upgradeable = and(io.internal_dbg_halt_mode_f, _T_667) @[dec_tlu_ctl.scala 2044:59] + node _T_668 = not(io.dbg_tlu_halted) @[dec_tlu_ctl.scala 2045:59] + node _T_669 = or(_T_668, dcsr_cause_upgradeable) @[dec_tlu_ctl.scala 2045:78] + node enter_debug_halt_req_le = and(io.enter_debug_halt_req, _T_669) @[dec_tlu_ctl.scala 2045:56] + node nmi_in_debug_mode = and(io.nmi_int_detected_f, io.internal_dbg_halt_mode_f) @[dec_tlu_ctl.scala 2047:48] + node _T_670 = bits(enter_debug_halt_req_le, 0, 0) @[dec_tlu_ctl.scala 2048:44] + node _T_671 = bits(io.dcsr, 15, 9) @[dec_tlu_ctl.scala 2048:64] + node _T_672 = bits(io.dcsr, 5, 2) @[dec_tlu_ctl.scala 2048:91] node _T_673 = cat(_T_672, UInt<2>("h03")) @[Cat.scala 29:58] - node _T_674 = cat(UInt<2>("h00"), _T_671) @[Cat.scala 29:58] + node _T_674 = cat(_T_671, dcsr_cause) @[Cat.scala 29:58] node _T_675 = cat(_T_674, _T_673) @[Cat.scala 29:58] - node _T_676 = cat(UInt<1>("h00"), _T_669) @[Cat.scala 29:58] - node _T_677 = cat(_T_667, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_678 = cat(_T_677, _T_668) @[Cat.scala 29:58] - node _T_679 = cat(_T_678, _T_676) @[Cat.scala 29:58] - node _T_680 = cat(_T_679, _T_675) @[Cat.scala 29:58] - node _T_681 = bits(io.dcsr, 15, 4) @[dec_tlu_ctl.scala 2051:211] - node _T_682 = bits(io.dcsr, 2, 2) @[dec_tlu_ctl.scala 2051:245] + node _T_676 = bits(wr_dcsr_r, 0, 0) @[dec_tlu_ctl.scala 2049:18] + node _T_677 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 2049:49] + node _T_678 = bits(io.dec_csr_wrdata_r, 11, 10) @[dec_tlu_ctl.scala 2049:84] + node _T_679 = bits(io.dcsr, 8, 6) @[dec_tlu_ctl.scala 2049:110] + node _T_680 = bits(io.dcsr, 3, 3) @[dec_tlu_ctl.scala 2049:154] + node _T_681 = or(nmi_in_debug_mode, _T_680) @[dec_tlu_ctl.scala 2049:145] + node _T_682 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2049:178] node _T_683 = cat(_T_682, UInt<2>("h03")) @[Cat.scala 29:58] - node _T_684 = cat(_T_681, nmi_in_debug_mode) @[Cat.scala 29:58] + node _T_684 = cat(UInt<2>("h00"), _T_681) @[Cat.scala 29:58] node _T_685 = cat(_T_684, _T_683) @[Cat.scala 29:58] - node _T_686 = mux(_T_666, _T_680, _T_685) @[dec_tlu_ctl.scala 2051:7] - node dcsr_ns = mux(_T_660, _T_665, _T_686) @[dec_tlu_ctl.scala 2050:19] - node _T_687 = or(enter_debug_halt_req_le, wr_dcsr_r) @[dec_tlu_ctl.scala 2053:54] - node _T_688 = or(_T_687, io.internal_dbg_halt_mode) @[dec_tlu_ctl.scala 2053:66] - node _T_689 = or(_T_688, io.take_nmi) @[dec_tlu_ctl.scala 2053:94] - node _T_690 = bits(_T_689, 0, 0) @[dec_tlu_ctl.scala 2053:109] + node _T_686 = cat(UInt<1>("h00"), _T_679) @[Cat.scala 29:58] + node _T_687 = cat(_T_677, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_688 = cat(_T_687, _T_678) @[Cat.scala 29:58] + node _T_689 = cat(_T_688, _T_686) @[Cat.scala 29:58] + node _T_690 = cat(_T_689, _T_685) @[Cat.scala 29:58] + node _T_691 = bits(io.dcsr, 15, 4) @[dec_tlu_ctl.scala 2049:211] + node _T_692 = bits(io.dcsr, 2, 2) @[dec_tlu_ctl.scala 2049:245] + node _T_693 = cat(_T_692, UInt<2>("h03")) @[Cat.scala 29:58] + node _T_694 = cat(_T_691, nmi_in_debug_mode) @[Cat.scala 29:58] + node _T_695 = cat(_T_694, _T_693) @[Cat.scala 29:58] + node _T_696 = mux(_T_676, _T_690, _T_695) @[dec_tlu_ctl.scala 2049:7] + node dcsr_ns = mux(_T_670, _T_675, _T_696) @[dec_tlu_ctl.scala 2048:19] + node _T_697 = or(enter_debug_halt_req_le, wr_dcsr_r) @[dec_tlu_ctl.scala 2051:54] + node _T_698 = or(_T_697, io.internal_dbg_halt_mode) @[dec_tlu_ctl.scala 2051:66] + node _T_699 = or(_T_698, io.take_nmi) @[dec_tlu_ctl.scala 2051:94] + node _T_700 = bits(_T_699, 0, 0) @[dec_tlu_ctl.scala 2051:109] inst rvclkhdr_17 of rvclkhdr_737 @[lib.scala 368:23] rvclkhdr_17.clock <= clock rvclkhdr_17.reset <= reset rvclkhdr_17.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_17.io.en <= _T_690 @[lib.scala 371:17] + rvclkhdr_17.io.en <= _T_700 @[lib.scala 371:17] rvclkhdr_17.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_691 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_691 <= dcsr_ns @[lib.scala 374:16] - io.dcsr <= _T_691 @[dec_tlu_ctl.scala 2053:10] - node _T_692 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2061:45] - node _T_693 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2061:90] - node _T_694 = eq(_T_693, UInt<12>("h07b1")) @[dec_tlu_ctl.scala 2061:97] - node wr_dpc_r = and(_T_692, _T_694) @[dec_tlu_ctl.scala 2061:68] - node _T_695 = not(io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2062:44] - node _T_696 = and(io.dbg_tlu_halted, _T_695) @[dec_tlu_ctl.scala 2062:42] - node _T_697 = not(io.request_debug_mode_done) @[dec_tlu_ctl.scala 2062:67] - node dpc_capture_npc = and(_T_696, _T_697) @[dec_tlu_ctl.scala 2062:65] - node _T_698 = not(io.request_debug_mode_r) @[dec_tlu_ctl.scala 2066:21] - node _T_699 = not(dpc_capture_npc) @[dec_tlu_ctl.scala 2066:39] - node _T_700 = and(_T_698, _T_699) @[dec_tlu_ctl.scala 2066:37] - node _T_701 = and(_T_700, wr_dpc_r) @[dec_tlu_ctl.scala 2066:56] - node _T_702 = bits(_T_701, 0, 0) @[dec_tlu_ctl.scala 2066:68] - node _T_703 = bits(io.dec_csr_wrdata_r, 31, 1) @[dec_tlu_ctl.scala 2066:97] - node _T_704 = bits(io.request_debug_mode_r, 0, 0) @[dec_tlu_ctl.scala 2067:68] - node _T_705 = not(io.request_debug_mode_r) @[dec_tlu_ctl.scala 2068:33] - node _T_706 = and(_T_705, dpc_capture_npc) @[dec_tlu_ctl.scala 2068:49] - node _T_707 = bits(_T_706, 0, 0) @[dec_tlu_ctl.scala 2068:68] - node _T_708 = mux(_T_702, _T_703, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_709 = mux(_T_704, pc_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_710 = mux(_T_707, io.npc_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_711 = or(_T_708, _T_709) @[Mux.scala 27:72] - node _T_712 = or(_T_711, _T_710) @[Mux.scala 27:72] + reg _T_701 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_701 <= dcsr_ns @[lib.scala 374:16] + io.dcsr <= _T_701 @[dec_tlu_ctl.scala 2051:10] + node _T_702 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2059:45] + node _T_703 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2059:90] + node _T_704 = eq(_T_703, UInt<12>("h07b1")) @[dec_tlu_ctl.scala 2059:97] + node wr_dpc_r = and(_T_702, _T_704) @[dec_tlu_ctl.scala 2059:68] + node _T_705 = not(io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2060:44] + node _T_706 = and(io.dbg_tlu_halted, _T_705) @[dec_tlu_ctl.scala 2060:42] + node _T_707 = not(io.request_debug_mode_done) @[dec_tlu_ctl.scala 2060:67] + node dpc_capture_npc = and(_T_706, _T_707) @[dec_tlu_ctl.scala 2060:65] + node _T_708 = not(io.request_debug_mode_r) @[dec_tlu_ctl.scala 2064:21] + node _T_709 = not(dpc_capture_npc) @[dec_tlu_ctl.scala 2064:39] + node _T_710 = and(_T_708, _T_709) @[dec_tlu_ctl.scala 2064:37] + node _T_711 = and(_T_710, wr_dpc_r) @[dec_tlu_ctl.scala 2064:56] + node _T_712 = bits(_T_711, 0, 0) @[dec_tlu_ctl.scala 2064:68] + node _T_713 = bits(io.dec_csr_wrdata_r, 31, 1) @[dec_tlu_ctl.scala 2064:97] + node _T_714 = bits(io.request_debug_mode_r, 0, 0) @[dec_tlu_ctl.scala 2065:68] + node _T_715 = not(io.request_debug_mode_r) @[dec_tlu_ctl.scala 2066:33] + node _T_716 = and(_T_715, dpc_capture_npc) @[dec_tlu_ctl.scala 2066:49] + node _T_717 = bits(_T_716, 0, 0) @[dec_tlu_ctl.scala 2066:68] + node _T_718 = mux(_T_712, _T_713, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_719 = mux(_T_714, pc_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_720 = mux(_T_717, io.npc_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_721 = or(_T_718, _T_719) @[Mux.scala 27:72] + node _T_722 = or(_T_721, _T_720) @[Mux.scala 27:72] wire dpc_ns : UInt<31> @[Mux.scala 27:72] - dpc_ns <= _T_712 @[Mux.scala 27:72] - node _T_713 = or(wr_dpc_r, io.request_debug_mode_r) @[dec_tlu_ctl.scala 2070:36] - node _T_714 = or(_T_713, dpc_capture_npc) @[dec_tlu_ctl.scala 2070:53] - node _T_715 = bits(_T_714, 0, 0) @[dec_tlu_ctl.scala 2070:72] + dpc_ns <= _T_722 @[Mux.scala 27:72] + node _T_723 = or(wr_dpc_r, io.request_debug_mode_r) @[dec_tlu_ctl.scala 2068:36] + node _T_724 = or(_T_723, dpc_capture_npc) @[dec_tlu_ctl.scala 2068:53] + node _T_725 = bits(_T_724, 0, 0) @[dec_tlu_ctl.scala 2068:72] inst rvclkhdr_18 of rvclkhdr_738 @[lib.scala 368:23] rvclkhdr_18.clock <= clock rvclkhdr_18.reset <= reset rvclkhdr_18.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_18.io.en <= _T_715 @[lib.scala 371:17] + rvclkhdr_18.io.en <= _T_725 @[lib.scala 371:17] rvclkhdr_18.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_716 : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_716 <= dpc_ns @[lib.scala 374:16] - io.dpc <= _T_716 @[dec_tlu_ctl.scala 2070:9] - node _T_717 = bits(io.dec_csr_wrdata_r, 24, 24) @[dec_tlu_ctl.scala 2084:43] - node _T_718 = bits(io.dec_csr_wrdata_r, 21, 20) @[dec_tlu_ctl.scala 2084:68] - node _T_719 = bits(io.dec_csr_wrdata_r, 16, 3) @[dec_tlu_ctl.scala 2084:96] - node _T_720 = cat(_T_717, _T_718) @[Cat.scala 29:58] - node dicawics_ns = cat(_T_720, _T_719) @[Cat.scala 29:58] - node _T_721 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2085:50] - node _T_722 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2085:95] - node _T_723 = eq(_T_722, UInt<12>("h07c8")) @[dec_tlu_ctl.scala 2085:102] - node wr_dicawics_r = and(_T_721, _T_723) @[dec_tlu_ctl.scala 2085:73] - node _T_724 = bits(wr_dicawics_r, 0, 0) @[dec_tlu_ctl.scala 2087:50] + reg _T_726 : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_726 <= dpc_ns @[lib.scala 374:16] + io.dpc <= _T_726 @[dec_tlu_ctl.scala 2068:9] + node _T_727 = bits(io.dec_csr_wrdata_r, 24, 24) @[dec_tlu_ctl.scala 2082:43] + node _T_728 = bits(io.dec_csr_wrdata_r, 21, 20) @[dec_tlu_ctl.scala 2082:68] + node _T_729 = bits(io.dec_csr_wrdata_r, 16, 3) @[dec_tlu_ctl.scala 2082:96] + node _T_730 = cat(_T_727, _T_728) @[Cat.scala 29:58] + node dicawics_ns = cat(_T_730, _T_729) @[Cat.scala 29:58] + node _T_731 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2083:50] + node _T_732 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2083:95] + node _T_733 = eq(_T_732, UInt<12>("h07c8")) @[dec_tlu_ctl.scala 2083:102] + node wr_dicawics_r = and(_T_731, _T_733) @[dec_tlu_ctl.scala 2083:73] + node _T_734 = bits(wr_dicawics_r, 0, 0) @[dec_tlu_ctl.scala 2085:50] inst rvclkhdr_19 of rvclkhdr_739 @[lib.scala 368:23] rvclkhdr_19.clock <= clock rvclkhdr_19.reset <= reset rvclkhdr_19.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_19.io.en <= _T_724 @[lib.scala 371:17] + rvclkhdr_19.io.en <= _T_734 @[lib.scala 371:17] rvclkhdr_19.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg dicawics : UInt, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] dicawics <= dicawics_ns @[lib.scala 374:16] - node _T_725 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2103:48] - node _T_726 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2103:93] - node _T_727 = eq(_T_726, UInt<12>("h07c9")) @[dec_tlu_ctl.scala 2103:100] - node wr_dicad0_r = and(_T_725, _T_727) @[dec_tlu_ctl.scala 2103:71] - node _T_728 = bits(wr_dicad0_r, 0, 0) @[dec_tlu_ctl.scala 2104:34] - node dicad0_ns = mux(_T_728, io.dec_csr_wrdata_r, io.ifu_ic_debug_rd_data) @[dec_tlu_ctl.scala 2104:21] - node _T_729 = or(wr_dicad0_r, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2106:46] - node _T_730 = bits(_T_729, 0, 0) @[dec_tlu_ctl.scala 2106:79] + node _T_735 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2101:48] + node _T_736 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2101:93] + node _T_737 = eq(_T_736, UInt<12>("h07c9")) @[dec_tlu_ctl.scala 2101:100] + node wr_dicad0_r = and(_T_735, _T_737) @[dec_tlu_ctl.scala 2101:71] + node _T_738 = bits(wr_dicad0_r, 0, 0) @[dec_tlu_ctl.scala 2102:34] + node dicad0_ns = mux(_T_738, io.dec_csr_wrdata_r, io.ifu_ic_debug_rd_data) @[dec_tlu_ctl.scala 2102:21] + node _T_739 = or(wr_dicad0_r, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2104:46] + node _T_740 = bits(_T_739, 0, 0) @[dec_tlu_ctl.scala 2104:79] inst rvclkhdr_20 of rvclkhdr_740 @[lib.scala 368:23] rvclkhdr_20.clock <= clock rvclkhdr_20.reset <= reset rvclkhdr_20.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_20.io.en <= _T_730 @[lib.scala 371:17] + rvclkhdr_20.io.en <= _T_740 @[lib.scala 371:17] rvclkhdr_20.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg dicad0 : UInt, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] dicad0 <= dicad0_ns @[lib.scala 374:16] - node _T_731 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2116:49] - node _T_732 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2116:94] - node _T_733 = eq(_T_732, UInt<12>("h07cc")) @[dec_tlu_ctl.scala 2116:101] - node wr_dicad0h_r = and(_T_731, _T_733) @[dec_tlu_ctl.scala 2116:72] - node _T_734 = bits(wr_dicad0h_r, 0, 0) @[dec_tlu_ctl.scala 2118:36] - node _T_735 = bits(io.ifu_ic_debug_rd_data, 63, 32) @[dec_tlu_ctl.scala 2118:88] - node dicad0h_ns = mux(_T_734, io.dec_csr_wrdata_r, _T_735) @[dec_tlu_ctl.scala 2118:22] - node _T_736 = or(wr_dicad0h_r, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2120:48] - node _T_737 = bits(_T_736, 0, 0) @[dec_tlu_ctl.scala 2120:81] + node _T_741 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2114:49] + node _T_742 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2114:94] + node _T_743 = eq(_T_742, UInt<12>("h07cc")) @[dec_tlu_ctl.scala 2114:101] + node wr_dicad0h_r = and(_T_741, _T_743) @[dec_tlu_ctl.scala 2114:72] + node _T_744 = bits(wr_dicad0h_r, 0, 0) @[dec_tlu_ctl.scala 2116:36] + node _T_745 = bits(io.ifu_ic_debug_rd_data, 63, 32) @[dec_tlu_ctl.scala 2116:88] + node dicad0h_ns = mux(_T_744, io.dec_csr_wrdata_r, _T_745) @[dec_tlu_ctl.scala 2116:22] + node _T_746 = or(wr_dicad0h_r, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2118:48] + node _T_747 = bits(_T_746, 0, 0) @[dec_tlu_ctl.scala 2118:81] inst rvclkhdr_21 of rvclkhdr_741 @[lib.scala 368:23] rvclkhdr_21.clock <= clock rvclkhdr_21.reset <= reset rvclkhdr_21.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_21.io.en <= _T_737 @[lib.scala 371:17] + rvclkhdr_21.io.en <= _T_747 @[lib.scala 371:17] rvclkhdr_21.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg dicad0h : UInt, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] dicad0h <= dicad0h_ns @[lib.scala 374:16] - wire _T_738 : UInt<7> - _T_738 <= UInt<1>("h00") - node _T_739 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2128:48] - node _T_740 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2128:93] - node _T_741 = eq(_T_740, UInt<12>("h07ca")) @[dec_tlu_ctl.scala 2128:100] - node _T_742 = and(_T_739, _T_741) @[dec_tlu_ctl.scala 2128:71] - node _T_743 = bits(_T_742, 0, 0) @[dec_tlu_ctl.scala 2130:34] - node _T_744 = bits(io.dec_csr_wrdata_r, 6, 0) @[dec_tlu_ctl.scala 2130:61] - node _T_745 = bits(io.ifu_ic_debug_rd_data, 70, 64) @[dec_tlu_ctl.scala 2130:91] - node _T_746 = mux(_T_743, _T_744, _T_745) @[dec_tlu_ctl.scala 2130:21] - node _T_747 = or(_T_742, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2132:78] - node _T_748 = bits(_T_747, 0, 0) @[dec_tlu_ctl.scala 2132:111] - reg _T_749 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_748 : @[Reg.scala 28:19] - _T_749 <= _T_746 @[Reg.scala 28:23] + wire _T_748 : UInt<7> + _T_748 <= UInt<1>("h00") + node _T_749 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2126:48] + node _T_750 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2126:93] + node _T_751 = eq(_T_750, UInt<12>("h07ca")) @[dec_tlu_ctl.scala 2126:100] + node _T_752 = and(_T_749, _T_751) @[dec_tlu_ctl.scala 2126:71] + node _T_753 = bits(_T_752, 0, 0) @[dec_tlu_ctl.scala 2128:34] + node _T_754 = bits(io.dec_csr_wrdata_r, 6, 0) @[dec_tlu_ctl.scala 2128:61] + node _T_755 = bits(io.ifu_ic_debug_rd_data, 70, 64) @[dec_tlu_ctl.scala 2128:91] + node _T_756 = mux(_T_753, _T_754, _T_755) @[dec_tlu_ctl.scala 2128:21] + node _T_757 = or(_T_752, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2130:78] + node _T_758 = bits(_T_757, 0, 0) @[dec_tlu_ctl.scala 2130:111] + reg _T_759 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_758 : @[Reg.scala 28:19] + _T_759 <= _T_756 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - _T_738 <= _T_749 @[dec_tlu_ctl.scala 2132:13] - node _T_750 = cat(UInt<25>("h00"), _T_738) @[Cat.scala 29:58] - dicad1 <= _T_750 @[dec_tlu_ctl.scala 2133:9] - node _T_751 = bits(dicad1, 6, 0) @[dec_tlu_ctl.scala 2155:69] - node _T_752 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2155:83] - node _T_753 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2155:97] - node _T_754 = cat(_T_751, _T_752) @[Cat.scala 29:58] - node _T_755 = cat(_T_754, _T_753) @[Cat.scala 29:58] - io.dec_tlu_ic_diag_pkt.icache_wrdata <= _T_755 @[dec_tlu_ctl.scala 2155:56] - io.dec_tlu_ic_diag_pkt.icache_dicawics <= dicawics @[dec_tlu_ctl.scala 2158:41] - node _T_756 = and(io.allow_dbg_halt_csr_write, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 2160:52] - node _T_757 = and(_T_756, io.dec_i0_decode_d) @[dec_tlu_ctl.scala 2160:75] - node _T_758 = not(io.dec_csr_wen_unq_d) @[dec_tlu_ctl.scala 2160:98] - node _T_759 = and(_T_757, _T_758) @[dec_tlu_ctl.scala 2160:96] - node _T_760 = bits(io.dec_csr_rdaddr_d, 11, 0) @[dec_tlu_ctl.scala 2160:142] - node _T_761 = eq(_T_760, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2160:149] - node icache_rd_valid = and(_T_759, _T_761) @[dec_tlu_ctl.scala 2160:120] - node _T_762 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2161:52] - node _T_763 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2161:97] - node _T_764 = eq(_T_763, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2161:104] - node icache_wr_valid = and(_T_762, _T_764) @[dec_tlu_ctl.scala 2161:75] - reg icache_rd_valid_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2163:58] - icache_rd_valid_f <= icache_rd_valid @[dec_tlu_ctl.scala 2163:58] - reg icache_wr_valid_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2164:58] - icache_wr_valid_f <= icache_wr_valid @[dec_tlu_ctl.scala 2164:58] - io.dec_tlu_ic_diag_pkt.icache_rd_valid <= icache_rd_valid_f @[dec_tlu_ctl.scala 2166:41] - io.dec_tlu_ic_diag_pkt.icache_wr_valid <= icache_wr_valid_f @[dec_tlu_ctl.scala 2167:41] - node _T_765 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2175:62] - node _T_766 = eq(_T_765, UInt<12>("h07a0")) @[dec_tlu_ctl.scala 2175:69] - node wr_mtsel_r = and(io.dec_csr_wen_r_mod, _T_766) @[dec_tlu_ctl.scala 2175:40] - node _T_767 = bits(wr_mtsel_r, 0, 0) @[dec_tlu_ctl.scala 2176:32] - node _T_768 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 2176:59] - node mtsel_ns = mux(_T_767, _T_768, mtsel) @[dec_tlu_ctl.scala 2176:20] - reg _T_769 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2178:43] - _T_769 <= mtsel_ns @[dec_tlu_ctl.scala 2178:43] - mtsel <= _T_769 @[dec_tlu_ctl.scala 2178:8] - node _T_770 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2213:38] - node _T_771 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2213:64] - node _T_772 = not(_T_771) @[dec_tlu_ctl.scala 2213:44] - node tdata_load = and(_T_770, _T_772) @[dec_tlu_ctl.scala 2213:42] - node _T_773 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2215:40] - node _T_774 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2215:66] - node _T_775 = not(_T_774) @[dec_tlu_ctl.scala 2215:46] - node tdata_opcode = and(_T_773, _T_775) @[dec_tlu_ctl.scala 2215:44] - node _T_776 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2217:41] - node _T_777 = and(_T_776, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2217:46] - node _T_778 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 2217:90] - node tdata_action = and(_T_777, _T_778) @[dec_tlu_ctl.scala 2217:69] - node _T_779 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2219:47] - node _T_780 = and(_T_779, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2219:52] - node _T_781 = bits(io.dec_csr_wrdata_r, 20, 19) @[dec_tlu_ctl.scala 2219:94] - node _T_782 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 2219:136] - node _T_783 = bits(io.dec_csr_wrdata_r, 7, 6) @[dec_tlu_ctl.scala 2220:43] - node _T_784 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 2220:83] - node _T_785 = cat(_T_784, tdata_load) @[Cat.scala 29:58] - node _T_786 = cat(_T_783, tdata_opcode) @[Cat.scala 29:58] - node _T_787 = cat(_T_786, _T_785) @[Cat.scala 29:58] - node _T_788 = cat(tdata_action, _T_782) @[Cat.scala 29:58] - node _T_789 = cat(_T_780, _T_781) @[Cat.scala 29:58] - node _T_790 = cat(_T_789, _T_788) @[Cat.scala 29:58] - node tdata_wrdata_r = cat(_T_790, _T_787) @[Cat.scala 29:58] - node _T_791 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2223:92] - node _T_792 = eq(_T_791, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2223:99] - node _T_793 = and(io.dec_csr_wen_r_mod, _T_792) @[dec_tlu_ctl.scala 2223:70] - node _T_794 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2223:121] - node _T_795 = and(_T_793, _T_794) @[dec_tlu_ctl.scala 2223:112] - node _T_796 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2223:154] - node _T_797 = not(_T_796) @[dec_tlu_ctl.scala 2223:138] - node _T_798 = or(_T_797, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2223:170] - node _T_799 = and(_T_795, _T_798) @[dec_tlu_ctl.scala 2223:135] - node _T_800 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2223:92] - node _T_801 = eq(_T_800, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2223:99] - node _T_802 = and(io.dec_csr_wen_r_mod, _T_801) @[dec_tlu_ctl.scala 2223:70] - node _T_803 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2223:121] - node _T_804 = and(_T_802, _T_803) @[dec_tlu_ctl.scala 2223:112] - node _T_805 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2223:154] - node _T_806 = not(_T_805) @[dec_tlu_ctl.scala 2223:138] - node _T_807 = or(_T_806, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2223:170] - node _T_808 = and(_T_804, _T_807) @[dec_tlu_ctl.scala 2223:135] - node _T_809 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2223:92] - node _T_810 = eq(_T_809, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2223:99] - node _T_811 = and(io.dec_csr_wen_r_mod, _T_810) @[dec_tlu_ctl.scala 2223:70] - node _T_812 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2223:121] - node _T_813 = and(_T_811, _T_812) @[dec_tlu_ctl.scala 2223:112] - node _T_814 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2223:154] - node _T_815 = not(_T_814) @[dec_tlu_ctl.scala 2223:138] - node _T_816 = or(_T_815, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2223:170] - node _T_817 = and(_T_813, _T_816) @[dec_tlu_ctl.scala 2223:135] - node _T_818 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2223:92] - node _T_819 = eq(_T_818, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2223:99] - node _T_820 = and(io.dec_csr_wen_r_mod, _T_819) @[dec_tlu_ctl.scala 2223:70] - node _T_821 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2223:121] - node _T_822 = and(_T_820, _T_821) @[dec_tlu_ctl.scala 2223:112] - node _T_823 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2223:154] - node _T_824 = not(_T_823) @[dec_tlu_ctl.scala 2223:138] - node _T_825 = or(_T_824, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2223:170] - node _T_826 = and(_T_822, _T_825) @[dec_tlu_ctl.scala 2223:135] - wire wr_mtdata1_t_r : UInt<1>[4] @[dec_tlu_ctl.scala 2223:42] - wr_mtdata1_t_r[0] <= _T_799 @[dec_tlu_ctl.scala 2223:42] - wr_mtdata1_t_r[1] <= _T_808 @[dec_tlu_ctl.scala 2223:42] - wr_mtdata1_t_r[2] <= _T_817 @[dec_tlu_ctl.scala 2223:42] - wr_mtdata1_t_r[3] <= _T_826 @[dec_tlu_ctl.scala 2223:42] - node _T_827 = bits(wr_mtdata1_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2224:68] - node _T_828 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2224:111] - node _T_829 = bits(io.update_hit_bit_r, 0, 0) @[dec_tlu_ctl.scala 2224:135] - node _T_830 = bits(io.mtdata1_t[0], 8, 8) @[dec_tlu_ctl.scala 2224:156] - node _T_831 = or(_T_829, _T_830) @[dec_tlu_ctl.scala 2224:139] - node _T_832 = bits(io.mtdata1_t[0], 7, 0) @[dec_tlu_ctl.scala 2224:176] - node _T_833 = cat(_T_828, _T_831) @[Cat.scala 29:58] - node _T_834 = cat(_T_833, _T_832) @[Cat.scala 29:58] - node _T_835 = mux(_T_827, tdata_wrdata_r, _T_834) @[dec_tlu_ctl.scala 2224:49] - node _T_836 = bits(wr_mtdata1_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2224:68] - node _T_837 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2224:111] - node _T_838 = bits(io.update_hit_bit_r, 1, 1) @[dec_tlu_ctl.scala 2224:135] - node _T_839 = bits(io.mtdata1_t[1], 8, 8) @[dec_tlu_ctl.scala 2224:156] - node _T_840 = or(_T_838, _T_839) @[dec_tlu_ctl.scala 2224:139] - node _T_841 = bits(io.mtdata1_t[1], 7, 0) @[dec_tlu_ctl.scala 2224:176] - node _T_842 = cat(_T_837, _T_840) @[Cat.scala 29:58] - node _T_843 = cat(_T_842, _T_841) @[Cat.scala 29:58] - node _T_844 = mux(_T_836, tdata_wrdata_r, _T_843) @[dec_tlu_ctl.scala 2224:49] - node _T_845 = bits(wr_mtdata1_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2224:68] - node _T_846 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2224:111] - node _T_847 = bits(io.update_hit_bit_r, 2, 2) @[dec_tlu_ctl.scala 2224:135] - node _T_848 = bits(io.mtdata1_t[2], 8, 8) @[dec_tlu_ctl.scala 2224:156] - node _T_849 = or(_T_847, _T_848) @[dec_tlu_ctl.scala 2224:139] - node _T_850 = bits(io.mtdata1_t[2], 7, 0) @[dec_tlu_ctl.scala 2224:176] - node _T_851 = cat(_T_846, _T_849) @[Cat.scala 29:58] - node _T_852 = cat(_T_851, _T_850) @[Cat.scala 29:58] - node _T_853 = mux(_T_845, tdata_wrdata_r, _T_852) @[dec_tlu_ctl.scala 2224:49] - node _T_854 = bits(wr_mtdata1_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2224:68] - node _T_855 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2224:111] - node _T_856 = bits(io.update_hit_bit_r, 3, 3) @[dec_tlu_ctl.scala 2224:135] - node _T_857 = bits(io.mtdata1_t[3], 8, 8) @[dec_tlu_ctl.scala 2224:156] - node _T_858 = or(_T_856, _T_857) @[dec_tlu_ctl.scala 2224:139] - node _T_859 = bits(io.mtdata1_t[3], 7, 0) @[dec_tlu_ctl.scala 2224:176] - node _T_860 = cat(_T_855, _T_858) @[Cat.scala 29:58] - node _T_861 = cat(_T_860, _T_859) @[Cat.scala 29:58] - node _T_862 = mux(_T_854, tdata_wrdata_r, _T_861) @[dec_tlu_ctl.scala 2224:49] - wire mtdata1_t_ns : UInt<10>[4] @[dec_tlu_ctl.scala 2224:40] - mtdata1_t_ns[0] <= _T_835 @[dec_tlu_ctl.scala 2224:40] - mtdata1_t_ns[1] <= _T_844 @[dec_tlu_ctl.scala 2224:40] - mtdata1_t_ns[2] <= _T_853 @[dec_tlu_ctl.scala 2224:40] - mtdata1_t_ns[3] <= _T_862 @[dec_tlu_ctl.scala 2224:40] - reg _T_863 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2226:74] - _T_863 <= mtdata1_t_ns[0] @[dec_tlu_ctl.scala 2226:74] - io.mtdata1_t[0] <= _T_863 @[dec_tlu_ctl.scala 2226:39] - reg _T_864 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2226:74] - _T_864 <= mtdata1_t_ns[1] @[dec_tlu_ctl.scala 2226:74] - io.mtdata1_t[1] <= _T_864 @[dec_tlu_ctl.scala 2226:39] - reg _T_865 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2226:74] - _T_865 <= mtdata1_t_ns[2] @[dec_tlu_ctl.scala 2226:74] - io.mtdata1_t[2] <= _T_865 @[dec_tlu_ctl.scala 2226:39] - reg _T_866 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2226:74] - _T_866 <= mtdata1_t_ns[3] @[dec_tlu_ctl.scala 2226:74] - io.mtdata1_t[3] <= _T_866 @[dec_tlu_ctl.scala 2226:39] - node _T_867 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2229:58] - node _T_868 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2229:104] - node _T_869 = bits(io.mtdata1_t[0], 8, 7) @[dec_tlu_ctl.scala 2229:142] - node _T_870 = bits(io.mtdata1_t[0], 6, 5) @[dec_tlu_ctl.scala 2229:174] - node _T_871 = bits(io.mtdata1_t[0], 4, 3) @[dec_tlu_ctl.scala 2229:206] - node _T_872 = bits(io.mtdata1_t[0], 2, 0) @[dec_tlu_ctl.scala 2229:238] - node _T_873 = cat(UInt<3>("h00"), _T_872) @[Cat.scala 29:58] - node _T_874 = cat(_T_870, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_875 = cat(_T_874, _T_871) @[Cat.scala 29:58] - node _T_876 = cat(_T_875, _T_873) @[Cat.scala 29:58] - node _T_877 = cat(_T_869, UInt<6>("h00")) @[Cat.scala 29:58] - node _T_878 = cat(UInt<4>("h02"), _T_868) @[Cat.scala 29:58] - node _T_879 = cat(_T_878, UInt<6>("h01f")) @[Cat.scala 29:58] - node _T_880 = cat(_T_879, _T_877) @[Cat.scala 29:58] - node _T_881 = cat(_T_880, _T_876) @[Cat.scala 29:58] - node _T_882 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2229:58] - node _T_883 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2229:104] - node _T_884 = bits(io.mtdata1_t[1], 8, 7) @[dec_tlu_ctl.scala 2229:142] - node _T_885 = bits(io.mtdata1_t[1], 6, 5) @[dec_tlu_ctl.scala 2229:174] - node _T_886 = bits(io.mtdata1_t[1], 4, 3) @[dec_tlu_ctl.scala 2229:206] - node _T_887 = bits(io.mtdata1_t[1], 2, 0) @[dec_tlu_ctl.scala 2229:238] - node _T_888 = cat(UInt<3>("h00"), _T_887) @[Cat.scala 29:58] - node _T_889 = cat(_T_885, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_890 = cat(_T_889, _T_886) @[Cat.scala 29:58] - node _T_891 = cat(_T_890, _T_888) @[Cat.scala 29:58] - node _T_892 = cat(_T_884, UInt<6>("h00")) @[Cat.scala 29:58] - node _T_893 = cat(UInt<4>("h02"), _T_883) @[Cat.scala 29:58] - node _T_894 = cat(_T_893, UInt<6>("h01f")) @[Cat.scala 29:58] - node _T_895 = cat(_T_894, _T_892) @[Cat.scala 29:58] - node _T_896 = cat(_T_895, _T_891) @[Cat.scala 29:58] - node _T_897 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2229:58] - node _T_898 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2229:104] - node _T_899 = bits(io.mtdata1_t[2], 8, 7) @[dec_tlu_ctl.scala 2229:142] - node _T_900 = bits(io.mtdata1_t[2], 6, 5) @[dec_tlu_ctl.scala 2229:174] - node _T_901 = bits(io.mtdata1_t[2], 4, 3) @[dec_tlu_ctl.scala 2229:206] - node _T_902 = bits(io.mtdata1_t[2], 2, 0) @[dec_tlu_ctl.scala 2229:238] - node _T_903 = cat(UInt<3>("h00"), _T_902) @[Cat.scala 29:58] - node _T_904 = cat(_T_900, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_905 = cat(_T_904, _T_901) @[Cat.scala 29:58] - node _T_906 = cat(_T_905, _T_903) @[Cat.scala 29:58] - node _T_907 = cat(_T_899, UInt<6>("h00")) @[Cat.scala 29:58] - node _T_908 = cat(UInt<4>("h02"), _T_898) @[Cat.scala 29:58] - node _T_909 = cat(_T_908, UInt<6>("h01f")) @[Cat.scala 29:58] - node _T_910 = cat(_T_909, _T_907) @[Cat.scala 29:58] - node _T_911 = cat(_T_910, _T_906) @[Cat.scala 29:58] - node _T_912 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2229:58] - node _T_913 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2229:104] - node _T_914 = bits(io.mtdata1_t[3], 8, 7) @[dec_tlu_ctl.scala 2229:142] - node _T_915 = bits(io.mtdata1_t[3], 6, 5) @[dec_tlu_ctl.scala 2229:174] - node _T_916 = bits(io.mtdata1_t[3], 4, 3) @[dec_tlu_ctl.scala 2229:206] - node _T_917 = bits(io.mtdata1_t[3], 2, 0) @[dec_tlu_ctl.scala 2229:238] - node _T_918 = cat(UInt<3>("h00"), _T_917) @[Cat.scala 29:58] - node _T_919 = cat(_T_915, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_920 = cat(_T_919, _T_916) @[Cat.scala 29:58] - node _T_921 = cat(_T_920, _T_918) @[Cat.scala 29:58] - node _T_922 = cat(_T_914, UInt<6>("h00")) @[Cat.scala 29:58] - node _T_923 = cat(UInt<4>("h02"), _T_913) @[Cat.scala 29:58] - node _T_924 = cat(_T_923, UInt<6>("h01f")) @[Cat.scala 29:58] - node _T_925 = cat(_T_924, _T_922) @[Cat.scala 29:58] - node _T_926 = cat(_T_925, _T_921) @[Cat.scala 29:58] - node _T_927 = mux(_T_867, _T_881, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_928 = mux(_T_882, _T_896, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_929 = mux(_T_897, _T_911, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_930 = mux(_T_912, _T_926, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_931 = or(_T_927, _T_928) @[Mux.scala 27:72] - node _T_932 = or(_T_931, _T_929) @[Mux.scala 27:72] - node _T_933 = or(_T_932, _T_930) @[Mux.scala 27:72] + _T_748 <= _T_759 @[dec_tlu_ctl.scala 2130:13] + node _T_760 = cat(UInt<25>("h00"), _T_748) @[Cat.scala 29:58] + dicad1 <= _T_760 @[dec_tlu_ctl.scala 2131:9] + node _T_761 = bits(dicad1, 6, 0) @[dec_tlu_ctl.scala 2153:69] + node _T_762 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2153:83] + node _T_763 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2153:97] + node _T_764 = cat(_T_761, _T_762) @[Cat.scala 29:58] + node _T_765 = cat(_T_764, _T_763) @[Cat.scala 29:58] + io.dec_tlu_ic_diag_pkt.icache_wrdata <= _T_765 @[dec_tlu_ctl.scala 2153:56] + io.dec_tlu_ic_diag_pkt.icache_dicawics <= dicawics @[dec_tlu_ctl.scala 2156:41] + node _T_766 = and(io.allow_dbg_halt_csr_write, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 2158:52] + node _T_767 = and(_T_766, io.dec_i0_decode_d) @[dec_tlu_ctl.scala 2158:75] + node _T_768 = not(io.dec_csr_wen_unq_d) @[dec_tlu_ctl.scala 2158:98] + node _T_769 = and(_T_767, _T_768) @[dec_tlu_ctl.scala 2158:96] + node _T_770 = bits(io.dec_csr_rdaddr_d, 11, 0) @[dec_tlu_ctl.scala 2158:142] + node _T_771 = eq(_T_770, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2158:149] + node icache_rd_valid = and(_T_769, _T_771) @[dec_tlu_ctl.scala 2158:120] + node _T_772 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2159:52] + node _T_773 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2159:97] + node _T_774 = eq(_T_773, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2159:104] + node icache_wr_valid = and(_T_772, _T_774) @[dec_tlu_ctl.scala 2159:75] + reg icache_rd_valid_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2161:58] + icache_rd_valid_f <= icache_rd_valid @[dec_tlu_ctl.scala 2161:58] + reg icache_wr_valid_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2162:58] + icache_wr_valid_f <= icache_wr_valid @[dec_tlu_ctl.scala 2162:58] + io.dec_tlu_ic_diag_pkt.icache_rd_valid <= icache_rd_valid_f @[dec_tlu_ctl.scala 2164:41] + io.dec_tlu_ic_diag_pkt.icache_wr_valid <= icache_wr_valid_f @[dec_tlu_ctl.scala 2165:41] + node _T_775 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2173:62] + node _T_776 = eq(_T_775, UInt<12>("h07a0")) @[dec_tlu_ctl.scala 2173:69] + node wr_mtsel_r = and(io.dec_csr_wen_r_mod, _T_776) @[dec_tlu_ctl.scala 2173:40] + node _T_777 = bits(wr_mtsel_r, 0, 0) @[dec_tlu_ctl.scala 2174:32] + node _T_778 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 2174:59] + node mtsel_ns = mux(_T_777, _T_778, mtsel) @[dec_tlu_ctl.scala 2174:20] + reg _T_779 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2176:43] + _T_779 <= mtsel_ns @[dec_tlu_ctl.scala 2176:43] + mtsel <= _T_779 @[dec_tlu_ctl.scala 2176:8] + node _T_780 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2211:38] + node _T_781 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2211:64] + node _T_782 = not(_T_781) @[dec_tlu_ctl.scala 2211:44] + node tdata_load = and(_T_780, _T_782) @[dec_tlu_ctl.scala 2211:42] + node _T_783 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2213:40] + node _T_784 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2213:66] + node _T_785 = not(_T_784) @[dec_tlu_ctl.scala 2213:46] + node tdata_opcode = and(_T_783, _T_785) @[dec_tlu_ctl.scala 2213:44] + node _T_786 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2215:41] + node _T_787 = and(_T_786, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2215:46] + node _T_788 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 2215:90] + node tdata_action = and(_T_787, _T_788) @[dec_tlu_ctl.scala 2215:69] + node _T_789 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2217:47] + node _T_790 = and(_T_789, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2217:52] + node _T_791 = bits(io.dec_csr_wrdata_r, 20, 19) @[dec_tlu_ctl.scala 2217:94] + node _T_792 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 2217:136] + node _T_793 = bits(io.dec_csr_wrdata_r, 7, 6) @[dec_tlu_ctl.scala 2218:43] + node _T_794 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 2218:83] + node _T_795 = cat(_T_794, tdata_load) @[Cat.scala 29:58] + node _T_796 = cat(_T_793, tdata_opcode) @[Cat.scala 29:58] + node _T_797 = cat(_T_796, _T_795) @[Cat.scala 29:58] + node _T_798 = cat(tdata_action, _T_792) @[Cat.scala 29:58] + node _T_799 = cat(_T_790, _T_791) @[Cat.scala 29:58] + node _T_800 = cat(_T_799, _T_798) @[Cat.scala 29:58] + node tdata_wrdata_r = cat(_T_800, _T_797) @[Cat.scala 29:58] + node _T_801 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2221:92] + node _T_802 = eq(_T_801, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2221:99] + node _T_803 = and(io.dec_csr_wen_r_mod, _T_802) @[dec_tlu_ctl.scala 2221:70] + node _T_804 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2221:121] + node _T_805 = and(_T_803, _T_804) @[dec_tlu_ctl.scala 2221:112] + node _T_806 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2221:154] + node _T_807 = not(_T_806) @[dec_tlu_ctl.scala 2221:138] + node _T_808 = or(_T_807, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2221:170] + node _T_809 = and(_T_805, _T_808) @[dec_tlu_ctl.scala 2221:135] + node _T_810 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2221:92] + node _T_811 = eq(_T_810, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2221:99] + node _T_812 = and(io.dec_csr_wen_r_mod, _T_811) @[dec_tlu_ctl.scala 2221:70] + node _T_813 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2221:121] + node _T_814 = and(_T_812, _T_813) @[dec_tlu_ctl.scala 2221:112] + node _T_815 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2221:154] + node _T_816 = not(_T_815) @[dec_tlu_ctl.scala 2221:138] + node _T_817 = or(_T_816, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2221:170] + node _T_818 = and(_T_814, _T_817) @[dec_tlu_ctl.scala 2221:135] + node _T_819 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2221:92] + node _T_820 = eq(_T_819, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2221:99] + node _T_821 = and(io.dec_csr_wen_r_mod, _T_820) @[dec_tlu_ctl.scala 2221:70] + node _T_822 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2221:121] + node _T_823 = and(_T_821, _T_822) @[dec_tlu_ctl.scala 2221:112] + node _T_824 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2221:154] + node _T_825 = not(_T_824) @[dec_tlu_ctl.scala 2221:138] + node _T_826 = or(_T_825, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2221:170] + node _T_827 = and(_T_823, _T_826) @[dec_tlu_ctl.scala 2221:135] + node _T_828 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2221:92] + node _T_829 = eq(_T_828, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2221:99] + node _T_830 = and(io.dec_csr_wen_r_mod, _T_829) @[dec_tlu_ctl.scala 2221:70] + node _T_831 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2221:121] + node _T_832 = and(_T_830, _T_831) @[dec_tlu_ctl.scala 2221:112] + node _T_833 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2221:154] + node _T_834 = not(_T_833) @[dec_tlu_ctl.scala 2221:138] + node _T_835 = or(_T_834, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2221:170] + node _T_836 = and(_T_832, _T_835) @[dec_tlu_ctl.scala 2221:135] + wire wr_mtdata1_t_r : UInt<1>[4] @[dec_tlu_ctl.scala 2221:42] + wr_mtdata1_t_r[0] <= _T_809 @[dec_tlu_ctl.scala 2221:42] + wr_mtdata1_t_r[1] <= _T_818 @[dec_tlu_ctl.scala 2221:42] + wr_mtdata1_t_r[2] <= _T_827 @[dec_tlu_ctl.scala 2221:42] + wr_mtdata1_t_r[3] <= _T_836 @[dec_tlu_ctl.scala 2221:42] + node _T_837 = bits(wr_mtdata1_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2222:68] + node _T_838 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2222:111] + node _T_839 = bits(io.update_hit_bit_r, 0, 0) @[dec_tlu_ctl.scala 2222:135] + node _T_840 = bits(io.mtdata1_t[0], 8, 8) @[dec_tlu_ctl.scala 2222:156] + node _T_841 = or(_T_839, _T_840) @[dec_tlu_ctl.scala 2222:139] + node _T_842 = bits(io.mtdata1_t[0], 7, 0) @[dec_tlu_ctl.scala 2222:176] + node _T_843 = cat(_T_838, _T_841) @[Cat.scala 29:58] + node _T_844 = cat(_T_843, _T_842) @[Cat.scala 29:58] + node _T_845 = mux(_T_837, tdata_wrdata_r, _T_844) @[dec_tlu_ctl.scala 2222:49] + node _T_846 = bits(wr_mtdata1_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2222:68] + node _T_847 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2222:111] + node _T_848 = bits(io.update_hit_bit_r, 1, 1) @[dec_tlu_ctl.scala 2222:135] + node _T_849 = bits(io.mtdata1_t[1], 8, 8) @[dec_tlu_ctl.scala 2222:156] + node _T_850 = or(_T_848, _T_849) @[dec_tlu_ctl.scala 2222:139] + node _T_851 = bits(io.mtdata1_t[1], 7, 0) @[dec_tlu_ctl.scala 2222:176] + node _T_852 = cat(_T_847, _T_850) @[Cat.scala 29:58] + node _T_853 = cat(_T_852, _T_851) @[Cat.scala 29:58] + node _T_854 = mux(_T_846, tdata_wrdata_r, _T_853) @[dec_tlu_ctl.scala 2222:49] + node _T_855 = bits(wr_mtdata1_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2222:68] + node _T_856 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2222:111] + node _T_857 = bits(io.update_hit_bit_r, 2, 2) @[dec_tlu_ctl.scala 2222:135] + node _T_858 = bits(io.mtdata1_t[2], 8, 8) @[dec_tlu_ctl.scala 2222:156] + node _T_859 = or(_T_857, _T_858) @[dec_tlu_ctl.scala 2222:139] + node _T_860 = bits(io.mtdata1_t[2], 7, 0) @[dec_tlu_ctl.scala 2222:176] + node _T_861 = cat(_T_856, _T_859) @[Cat.scala 29:58] + node _T_862 = cat(_T_861, _T_860) @[Cat.scala 29:58] + node _T_863 = mux(_T_855, tdata_wrdata_r, _T_862) @[dec_tlu_ctl.scala 2222:49] + node _T_864 = bits(wr_mtdata1_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2222:68] + node _T_865 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2222:111] + node _T_866 = bits(io.update_hit_bit_r, 3, 3) @[dec_tlu_ctl.scala 2222:135] + node _T_867 = bits(io.mtdata1_t[3], 8, 8) @[dec_tlu_ctl.scala 2222:156] + node _T_868 = or(_T_866, _T_867) @[dec_tlu_ctl.scala 2222:139] + node _T_869 = bits(io.mtdata1_t[3], 7, 0) @[dec_tlu_ctl.scala 2222:176] + node _T_870 = cat(_T_865, _T_868) @[Cat.scala 29:58] + node _T_871 = cat(_T_870, _T_869) @[Cat.scala 29:58] + node _T_872 = mux(_T_864, tdata_wrdata_r, _T_871) @[dec_tlu_ctl.scala 2222:49] + wire mtdata1_t_ns : UInt<10>[4] @[dec_tlu_ctl.scala 2222:40] + mtdata1_t_ns[0] <= _T_845 @[dec_tlu_ctl.scala 2222:40] + mtdata1_t_ns[1] <= _T_854 @[dec_tlu_ctl.scala 2222:40] + mtdata1_t_ns[2] <= _T_863 @[dec_tlu_ctl.scala 2222:40] + mtdata1_t_ns[3] <= _T_872 @[dec_tlu_ctl.scala 2222:40] + reg _T_873 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2224:74] + _T_873 <= mtdata1_t_ns[0] @[dec_tlu_ctl.scala 2224:74] + io.mtdata1_t[0] <= _T_873 @[dec_tlu_ctl.scala 2224:39] + reg _T_874 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2224:74] + _T_874 <= mtdata1_t_ns[1] @[dec_tlu_ctl.scala 2224:74] + io.mtdata1_t[1] <= _T_874 @[dec_tlu_ctl.scala 2224:39] + reg _T_875 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2224:74] + _T_875 <= mtdata1_t_ns[2] @[dec_tlu_ctl.scala 2224:74] + io.mtdata1_t[2] <= _T_875 @[dec_tlu_ctl.scala 2224:39] + reg _T_876 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2224:74] + _T_876 <= mtdata1_t_ns[3] @[dec_tlu_ctl.scala 2224:74] + io.mtdata1_t[3] <= _T_876 @[dec_tlu_ctl.scala 2224:39] + node _T_877 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2227:58] + node _T_878 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2227:104] + node _T_879 = bits(io.mtdata1_t[0], 8, 7) @[dec_tlu_ctl.scala 2227:142] + node _T_880 = bits(io.mtdata1_t[0], 6, 5) @[dec_tlu_ctl.scala 2227:174] + node _T_881 = bits(io.mtdata1_t[0], 4, 3) @[dec_tlu_ctl.scala 2227:206] + node _T_882 = bits(io.mtdata1_t[0], 2, 0) @[dec_tlu_ctl.scala 2227:238] + node _T_883 = cat(UInt<3>("h00"), _T_882) @[Cat.scala 29:58] + node _T_884 = cat(_T_880, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_885 = cat(_T_884, _T_881) @[Cat.scala 29:58] + node _T_886 = cat(_T_885, _T_883) @[Cat.scala 29:58] + node _T_887 = cat(_T_879, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_888 = cat(UInt<4>("h02"), _T_878) @[Cat.scala 29:58] + node _T_889 = cat(_T_888, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_890 = cat(_T_889, _T_887) @[Cat.scala 29:58] + node _T_891 = cat(_T_890, _T_886) @[Cat.scala 29:58] + node _T_892 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2227:58] + node _T_893 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2227:104] + node _T_894 = bits(io.mtdata1_t[1], 8, 7) @[dec_tlu_ctl.scala 2227:142] + node _T_895 = bits(io.mtdata1_t[1], 6, 5) @[dec_tlu_ctl.scala 2227:174] + node _T_896 = bits(io.mtdata1_t[1], 4, 3) @[dec_tlu_ctl.scala 2227:206] + node _T_897 = bits(io.mtdata1_t[1], 2, 0) @[dec_tlu_ctl.scala 2227:238] + node _T_898 = cat(UInt<3>("h00"), _T_897) @[Cat.scala 29:58] + node _T_899 = cat(_T_895, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_900 = cat(_T_899, _T_896) @[Cat.scala 29:58] + node _T_901 = cat(_T_900, _T_898) @[Cat.scala 29:58] + node _T_902 = cat(_T_894, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_903 = cat(UInt<4>("h02"), _T_893) @[Cat.scala 29:58] + node _T_904 = cat(_T_903, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_905 = cat(_T_904, _T_902) @[Cat.scala 29:58] + node _T_906 = cat(_T_905, _T_901) @[Cat.scala 29:58] + node _T_907 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2227:58] + node _T_908 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2227:104] + node _T_909 = bits(io.mtdata1_t[2], 8, 7) @[dec_tlu_ctl.scala 2227:142] + node _T_910 = bits(io.mtdata1_t[2], 6, 5) @[dec_tlu_ctl.scala 2227:174] + node _T_911 = bits(io.mtdata1_t[2], 4, 3) @[dec_tlu_ctl.scala 2227:206] + node _T_912 = bits(io.mtdata1_t[2], 2, 0) @[dec_tlu_ctl.scala 2227:238] + node _T_913 = cat(UInt<3>("h00"), _T_912) @[Cat.scala 29:58] + node _T_914 = cat(_T_910, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_915 = cat(_T_914, _T_911) @[Cat.scala 29:58] + node _T_916 = cat(_T_915, _T_913) @[Cat.scala 29:58] + node _T_917 = cat(_T_909, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_918 = cat(UInt<4>("h02"), _T_908) @[Cat.scala 29:58] + node _T_919 = cat(_T_918, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_920 = cat(_T_919, _T_917) @[Cat.scala 29:58] + node _T_921 = cat(_T_920, _T_916) @[Cat.scala 29:58] + node _T_922 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2227:58] + node _T_923 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2227:104] + node _T_924 = bits(io.mtdata1_t[3], 8, 7) @[dec_tlu_ctl.scala 2227:142] + node _T_925 = bits(io.mtdata1_t[3], 6, 5) @[dec_tlu_ctl.scala 2227:174] + node _T_926 = bits(io.mtdata1_t[3], 4, 3) @[dec_tlu_ctl.scala 2227:206] + node _T_927 = bits(io.mtdata1_t[3], 2, 0) @[dec_tlu_ctl.scala 2227:238] + node _T_928 = cat(UInt<3>("h00"), _T_927) @[Cat.scala 29:58] + node _T_929 = cat(_T_925, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_930 = cat(_T_929, _T_926) @[Cat.scala 29:58] + node _T_931 = cat(_T_930, _T_928) @[Cat.scala 29:58] + node _T_932 = cat(_T_924, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_933 = cat(UInt<4>("h02"), _T_923) @[Cat.scala 29:58] + node _T_934 = cat(_T_933, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_935 = cat(_T_934, _T_932) @[Cat.scala 29:58] + node _T_936 = cat(_T_935, _T_931) @[Cat.scala 29:58] + node _T_937 = mux(_T_877, _T_891, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_938 = mux(_T_892, _T_906, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_939 = mux(_T_907, _T_921, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_940 = mux(_T_922, _T_936, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_941 = or(_T_937, _T_938) @[Mux.scala 27:72] + node _T_942 = or(_T_941, _T_939) @[Mux.scala 27:72] + node _T_943 = or(_T_942, _T_940) @[Mux.scala 27:72] wire mtdata1_tsel_out : UInt<32> @[Mux.scala 27:72] - mtdata1_tsel_out <= _T_933 @[Mux.scala 27:72] - node _T_934 = bits(io.mtdata1_t[0], 7, 7) @[dec_tlu_ctl.scala 2231:58] - io.trigger_pkt_any[0].select <= _T_934 @[dec_tlu_ctl.scala 2231:40] - node _T_935 = bits(io.mtdata1_t[0], 4, 4) @[dec_tlu_ctl.scala 2232:61] - io.trigger_pkt_any[0].match_pkt <= _T_935 @[dec_tlu_ctl.scala 2232:43] - node _T_936 = bits(io.mtdata1_t[0], 1, 1) @[dec_tlu_ctl.scala 2233:58] - io.trigger_pkt_any[0].store <= _T_936 @[dec_tlu_ctl.scala 2233:40] - node _T_937 = bits(io.mtdata1_t[0], 0, 0) @[dec_tlu_ctl.scala 2234:58] - io.trigger_pkt_any[0].load <= _T_937 @[dec_tlu_ctl.scala 2234:40] - node _T_938 = bits(io.mtdata1_t[0], 2, 2) @[dec_tlu_ctl.scala 2235:58] - io.trigger_pkt_any[0].execute <= _T_938 @[dec_tlu_ctl.scala 2235:40] - node _T_939 = bits(io.mtdata1_t[0], 3, 3) @[dec_tlu_ctl.scala 2236:58] - io.trigger_pkt_any[0].m <= _T_939 @[dec_tlu_ctl.scala 2236:40] - node _T_940 = bits(io.mtdata1_t[1], 7, 7) @[dec_tlu_ctl.scala 2231:58] - io.trigger_pkt_any[1].select <= _T_940 @[dec_tlu_ctl.scala 2231:40] - node _T_941 = bits(io.mtdata1_t[1], 4, 4) @[dec_tlu_ctl.scala 2232:61] - io.trigger_pkt_any[1].match_pkt <= _T_941 @[dec_tlu_ctl.scala 2232:43] - node _T_942 = bits(io.mtdata1_t[1], 1, 1) @[dec_tlu_ctl.scala 2233:58] - io.trigger_pkt_any[1].store <= _T_942 @[dec_tlu_ctl.scala 2233:40] - node _T_943 = bits(io.mtdata1_t[1], 0, 0) @[dec_tlu_ctl.scala 2234:58] - io.trigger_pkt_any[1].load <= _T_943 @[dec_tlu_ctl.scala 2234:40] - node _T_944 = bits(io.mtdata1_t[1], 2, 2) @[dec_tlu_ctl.scala 2235:58] - io.trigger_pkt_any[1].execute <= _T_944 @[dec_tlu_ctl.scala 2235:40] - node _T_945 = bits(io.mtdata1_t[1], 3, 3) @[dec_tlu_ctl.scala 2236:58] - io.trigger_pkt_any[1].m <= _T_945 @[dec_tlu_ctl.scala 2236:40] - node _T_946 = bits(io.mtdata1_t[2], 7, 7) @[dec_tlu_ctl.scala 2231:58] - io.trigger_pkt_any[2].select <= _T_946 @[dec_tlu_ctl.scala 2231:40] - node _T_947 = bits(io.mtdata1_t[2], 4, 4) @[dec_tlu_ctl.scala 2232:61] - io.trigger_pkt_any[2].match_pkt <= _T_947 @[dec_tlu_ctl.scala 2232:43] - node _T_948 = bits(io.mtdata1_t[2], 1, 1) @[dec_tlu_ctl.scala 2233:58] - io.trigger_pkt_any[2].store <= _T_948 @[dec_tlu_ctl.scala 2233:40] - node _T_949 = bits(io.mtdata1_t[2], 0, 0) @[dec_tlu_ctl.scala 2234:58] - io.trigger_pkt_any[2].load <= _T_949 @[dec_tlu_ctl.scala 2234:40] - node _T_950 = bits(io.mtdata1_t[2], 2, 2) @[dec_tlu_ctl.scala 2235:58] - io.trigger_pkt_any[2].execute <= _T_950 @[dec_tlu_ctl.scala 2235:40] - node _T_951 = bits(io.mtdata1_t[2], 3, 3) @[dec_tlu_ctl.scala 2236:58] - io.trigger_pkt_any[2].m <= _T_951 @[dec_tlu_ctl.scala 2236:40] - node _T_952 = bits(io.mtdata1_t[3], 7, 7) @[dec_tlu_ctl.scala 2231:58] - io.trigger_pkt_any[3].select <= _T_952 @[dec_tlu_ctl.scala 2231:40] - node _T_953 = bits(io.mtdata1_t[3], 4, 4) @[dec_tlu_ctl.scala 2232:61] - io.trigger_pkt_any[3].match_pkt <= _T_953 @[dec_tlu_ctl.scala 2232:43] - node _T_954 = bits(io.mtdata1_t[3], 1, 1) @[dec_tlu_ctl.scala 2233:58] - io.trigger_pkt_any[3].store <= _T_954 @[dec_tlu_ctl.scala 2233:40] - node _T_955 = bits(io.mtdata1_t[3], 0, 0) @[dec_tlu_ctl.scala 2234:58] - io.trigger_pkt_any[3].load <= _T_955 @[dec_tlu_ctl.scala 2234:40] - node _T_956 = bits(io.mtdata1_t[3], 2, 2) @[dec_tlu_ctl.scala 2235:58] - io.trigger_pkt_any[3].execute <= _T_956 @[dec_tlu_ctl.scala 2235:40] - node _T_957 = bits(io.mtdata1_t[3], 3, 3) @[dec_tlu_ctl.scala 2236:58] - io.trigger_pkt_any[3].m <= _T_957 @[dec_tlu_ctl.scala 2236:40] - node _T_958 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2243:91] - node _T_959 = eq(_T_958, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2243:98] - node _T_960 = and(io.dec_csr_wen_r_mod, _T_959) @[dec_tlu_ctl.scala 2243:69] - node _T_961 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2243:120] - node _T_962 = and(_T_960, _T_961) @[dec_tlu_ctl.scala 2243:111] - node _T_963 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2243:153] - node _T_964 = not(_T_963) @[dec_tlu_ctl.scala 2243:137] - node _T_965 = or(_T_964, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2243:169] - node _T_966 = and(_T_962, _T_965) @[dec_tlu_ctl.scala 2243:134] - node _T_967 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2243:91] - node _T_968 = eq(_T_967, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2243:98] - node _T_969 = and(io.dec_csr_wen_r_mod, _T_968) @[dec_tlu_ctl.scala 2243:69] - node _T_970 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2243:120] - node _T_971 = and(_T_969, _T_970) @[dec_tlu_ctl.scala 2243:111] - node _T_972 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2243:153] - node _T_973 = not(_T_972) @[dec_tlu_ctl.scala 2243:137] - node _T_974 = or(_T_973, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2243:169] - node _T_975 = and(_T_971, _T_974) @[dec_tlu_ctl.scala 2243:134] - node _T_976 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2243:91] - node _T_977 = eq(_T_976, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2243:98] - node _T_978 = and(io.dec_csr_wen_r_mod, _T_977) @[dec_tlu_ctl.scala 2243:69] - node _T_979 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2243:120] - node _T_980 = and(_T_978, _T_979) @[dec_tlu_ctl.scala 2243:111] - node _T_981 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2243:153] - node _T_982 = not(_T_981) @[dec_tlu_ctl.scala 2243:137] - node _T_983 = or(_T_982, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2243:169] - node _T_984 = and(_T_980, _T_983) @[dec_tlu_ctl.scala 2243:134] - node _T_985 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2243:91] - node _T_986 = eq(_T_985, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2243:98] - node _T_987 = and(io.dec_csr_wen_r_mod, _T_986) @[dec_tlu_ctl.scala 2243:69] - node _T_988 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2243:120] - node _T_989 = and(_T_987, _T_988) @[dec_tlu_ctl.scala 2243:111] - node _T_990 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2243:153] - node _T_991 = not(_T_990) @[dec_tlu_ctl.scala 2243:137] - node _T_992 = or(_T_991, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2243:169] - node _T_993 = and(_T_989, _T_992) @[dec_tlu_ctl.scala 2243:134] - wire wr_mtdata2_t_r : UInt<1>[4] @[dec_tlu_ctl.scala 2243:42] - wr_mtdata2_t_r[0] <= _T_966 @[dec_tlu_ctl.scala 2243:42] - wr_mtdata2_t_r[1] <= _T_975 @[dec_tlu_ctl.scala 2243:42] - wr_mtdata2_t_r[2] <= _T_984 @[dec_tlu_ctl.scala 2243:42] - wr_mtdata2_t_r[3] <= _T_993 @[dec_tlu_ctl.scala 2243:42] - node _T_994 = bits(wr_mtdata2_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2244:84] + mtdata1_tsel_out <= _T_943 @[Mux.scala 27:72] + node _T_944 = bits(io.mtdata1_t[0], 7, 7) @[dec_tlu_ctl.scala 2229:58] + io.trigger_pkt_any[0].select <= _T_944 @[dec_tlu_ctl.scala 2229:40] + node _T_945 = bits(io.mtdata1_t[0], 4, 4) @[dec_tlu_ctl.scala 2230:61] + io.trigger_pkt_any[0].match_pkt <= _T_945 @[dec_tlu_ctl.scala 2230:43] + node _T_946 = bits(io.mtdata1_t[0], 1, 1) @[dec_tlu_ctl.scala 2231:58] + io.trigger_pkt_any[0].store <= _T_946 @[dec_tlu_ctl.scala 2231:40] + node _T_947 = bits(io.mtdata1_t[0], 0, 0) @[dec_tlu_ctl.scala 2232:58] + io.trigger_pkt_any[0].load <= _T_947 @[dec_tlu_ctl.scala 2232:40] + node _T_948 = bits(io.mtdata1_t[0], 2, 2) @[dec_tlu_ctl.scala 2233:58] + io.trigger_pkt_any[0].execute <= _T_948 @[dec_tlu_ctl.scala 2233:40] + node _T_949 = bits(io.mtdata1_t[0], 3, 3) @[dec_tlu_ctl.scala 2234:58] + io.trigger_pkt_any[0].m <= _T_949 @[dec_tlu_ctl.scala 2234:40] + node _T_950 = bits(io.mtdata1_t[1], 7, 7) @[dec_tlu_ctl.scala 2229:58] + io.trigger_pkt_any[1].select <= _T_950 @[dec_tlu_ctl.scala 2229:40] + node _T_951 = bits(io.mtdata1_t[1], 4, 4) @[dec_tlu_ctl.scala 2230:61] + io.trigger_pkt_any[1].match_pkt <= _T_951 @[dec_tlu_ctl.scala 2230:43] + node _T_952 = bits(io.mtdata1_t[1], 1, 1) @[dec_tlu_ctl.scala 2231:58] + io.trigger_pkt_any[1].store <= _T_952 @[dec_tlu_ctl.scala 2231:40] + node _T_953 = bits(io.mtdata1_t[1], 0, 0) @[dec_tlu_ctl.scala 2232:58] + io.trigger_pkt_any[1].load <= _T_953 @[dec_tlu_ctl.scala 2232:40] + node _T_954 = bits(io.mtdata1_t[1], 2, 2) @[dec_tlu_ctl.scala 2233:58] + io.trigger_pkt_any[1].execute <= _T_954 @[dec_tlu_ctl.scala 2233:40] + node _T_955 = bits(io.mtdata1_t[1], 3, 3) @[dec_tlu_ctl.scala 2234:58] + io.trigger_pkt_any[1].m <= _T_955 @[dec_tlu_ctl.scala 2234:40] + node _T_956 = bits(io.mtdata1_t[2], 7, 7) @[dec_tlu_ctl.scala 2229:58] + io.trigger_pkt_any[2].select <= _T_956 @[dec_tlu_ctl.scala 2229:40] + node _T_957 = bits(io.mtdata1_t[2], 4, 4) @[dec_tlu_ctl.scala 2230:61] + io.trigger_pkt_any[2].match_pkt <= _T_957 @[dec_tlu_ctl.scala 2230:43] + node _T_958 = bits(io.mtdata1_t[2], 1, 1) @[dec_tlu_ctl.scala 2231:58] + io.trigger_pkt_any[2].store <= _T_958 @[dec_tlu_ctl.scala 2231:40] + node _T_959 = bits(io.mtdata1_t[2], 0, 0) @[dec_tlu_ctl.scala 2232:58] + io.trigger_pkt_any[2].load <= _T_959 @[dec_tlu_ctl.scala 2232:40] + node _T_960 = bits(io.mtdata1_t[2], 2, 2) @[dec_tlu_ctl.scala 2233:58] + io.trigger_pkt_any[2].execute <= _T_960 @[dec_tlu_ctl.scala 2233:40] + node _T_961 = bits(io.mtdata1_t[2], 3, 3) @[dec_tlu_ctl.scala 2234:58] + io.trigger_pkt_any[2].m <= _T_961 @[dec_tlu_ctl.scala 2234:40] + node _T_962 = bits(io.mtdata1_t[3], 7, 7) @[dec_tlu_ctl.scala 2229:58] + io.trigger_pkt_any[3].select <= _T_962 @[dec_tlu_ctl.scala 2229:40] + node _T_963 = bits(io.mtdata1_t[3], 4, 4) @[dec_tlu_ctl.scala 2230:61] + io.trigger_pkt_any[3].match_pkt <= _T_963 @[dec_tlu_ctl.scala 2230:43] + node _T_964 = bits(io.mtdata1_t[3], 1, 1) @[dec_tlu_ctl.scala 2231:58] + io.trigger_pkt_any[3].store <= _T_964 @[dec_tlu_ctl.scala 2231:40] + node _T_965 = bits(io.mtdata1_t[3], 0, 0) @[dec_tlu_ctl.scala 2232:58] + io.trigger_pkt_any[3].load <= _T_965 @[dec_tlu_ctl.scala 2232:40] + node _T_966 = bits(io.mtdata1_t[3], 2, 2) @[dec_tlu_ctl.scala 2233:58] + io.trigger_pkt_any[3].execute <= _T_966 @[dec_tlu_ctl.scala 2233:40] + node _T_967 = bits(io.mtdata1_t[3], 3, 3) @[dec_tlu_ctl.scala 2234:58] + io.trigger_pkt_any[3].m <= _T_967 @[dec_tlu_ctl.scala 2234:40] + node _T_968 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2241:91] + node _T_969 = eq(_T_968, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2241:98] + node _T_970 = and(io.dec_csr_wen_r_mod, _T_969) @[dec_tlu_ctl.scala 2241:69] + node _T_971 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2241:120] + node _T_972 = and(_T_970, _T_971) @[dec_tlu_ctl.scala 2241:111] + node _T_973 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2241:153] + node _T_974 = not(_T_973) @[dec_tlu_ctl.scala 2241:137] + node _T_975 = or(_T_974, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2241:169] + node _T_976 = and(_T_972, _T_975) @[dec_tlu_ctl.scala 2241:134] + node _T_977 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2241:91] + node _T_978 = eq(_T_977, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2241:98] + node _T_979 = and(io.dec_csr_wen_r_mod, _T_978) @[dec_tlu_ctl.scala 2241:69] + node _T_980 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2241:120] + node _T_981 = and(_T_979, _T_980) @[dec_tlu_ctl.scala 2241:111] + node _T_982 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2241:153] + node _T_983 = not(_T_982) @[dec_tlu_ctl.scala 2241:137] + node _T_984 = or(_T_983, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2241:169] + node _T_985 = and(_T_981, _T_984) @[dec_tlu_ctl.scala 2241:134] + node _T_986 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2241:91] + node _T_987 = eq(_T_986, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2241:98] + node _T_988 = and(io.dec_csr_wen_r_mod, _T_987) @[dec_tlu_ctl.scala 2241:69] + node _T_989 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2241:120] + node _T_990 = and(_T_988, _T_989) @[dec_tlu_ctl.scala 2241:111] + node _T_991 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2241:153] + node _T_992 = not(_T_991) @[dec_tlu_ctl.scala 2241:137] + node _T_993 = or(_T_992, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2241:169] + node _T_994 = and(_T_990, _T_993) @[dec_tlu_ctl.scala 2241:134] + node _T_995 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2241:91] + node _T_996 = eq(_T_995, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2241:98] + node _T_997 = and(io.dec_csr_wen_r_mod, _T_996) @[dec_tlu_ctl.scala 2241:69] + node _T_998 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2241:120] + node _T_999 = and(_T_997, _T_998) @[dec_tlu_ctl.scala 2241:111] + node _T_1000 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2241:153] + node _T_1001 = not(_T_1000) @[dec_tlu_ctl.scala 2241:137] + node _T_1002 = or(_T_1001, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2241:169] + node _T_1003 = and(_T_999, _T_1002) @[dec_tlu_ctl.scala 2241:134] + wire wr_mtdata2_t_r : UInt<1>[4] @[dec_tlu_ctl.scala 2241:42] + wr_mtdata2_t_r[0] <= _T_976 @[dec_tlu_ctl.scala 2241:42] + wr_mtdata2_t_r[1] <= _T_985 @[dec_tlu_ctl.scala 2241:42] + wr_mtdata2_t_r[2] <= _T_994 @[dec_tlu_ctl.scala 2241:42] + wr_mtdata2_t_r[3] <= _T_1003 @[dec_tlu_ctl.scala 2241:42] + node _T_1004 = bits(wr_mtdata2_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2242:84] inst rvclkhdr_22 of rvclkhdr_742 @[lib.scala 368:23] rvclkhdr_22.clock <= clock rvclkhdr_22.reset <= reset rvclkhdr_22.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_22.io.en <= _T_994 @[lib.scala 371:17] + rvclkhdr_22.io.en <= _T_1004 @[lib.scala 371:17] rvclkhdr_22.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_995 : UInt, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_995 <= io.dec_csr_wrdata_r @[lib.scala 374:16] - mtdata2_t[0] <= _T_995 @[dec_tlu_ctl.scala 2244:36] - node _T_996 = bits(wr_mtdata2_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2244:84] + reg _T_1005 : UInt, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_1005 <= io.dec_csr_wrdata_r @[lib.scala 374:16] + mtdata2_t[0] <= _T_1005 @[dec_tlu_ctl.scala 2242:36] + node _T_1006 = bits(wr_mtdata2_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2242:84] inst rvclkhdr_23 of rvclkhdr_743 @[lib.scala 368:23] rvclkhdr_23.clock <= clock rvclkhdr_23.reset <= reset rvclkhdr_23.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_23.io.en <= _T_996 @[lib.scala 371:17] + rvclkhdr_23.io.en <= _T_1006 @[lib.scala 371:17] rvclkhdr_23.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_997 : UInt, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_997 <= io.dec_csr_wrdata_r @[lib.scala 374:16] - mtdata2_t[1] <= _T_997 @[dec_tlu_ctl.scala 2244:36] - node _T_998 = bits(wr_mtdata2_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2244:84] + reg _T_1007 : UInt, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_1007 <= io.dec_csr_wrdata_r @[lib.scala 374:16] + mtdata2_t[1] <= _T_1007 @[dec_tlu_ctl.scala 2242:36] + node _T_1008 = bits(wr_mtdata2_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2242:84] inst rvclkhdr_24 of rvclkhdr_744 @[lib.scala 368:23] rvclkhdr_24.clock <= clock rvclkhdr_24.reset <= reset rvclkhdr_24.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_24.io.en <= _T_998 @[lib.scala 371:17] + rvclkhdr_24.io.en <= _T_1008 @[lib.scala 371:17] rvclkhdr_24.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_999 : UInt, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_999 <= io.dec_csr_wrdata_r @[lib.scala 374:16] - mtdata2_t[2] <= _T_999 @[dec_tlu_ctl.scala 2244:36] - node _T_1000 = bits(wr_mtdata2_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2244:84] + reg _T_1009 : UInt, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_1009 <= io.dec_csr_wrdata_r @[lib.scala 374:16] + mtdata2_t[2] <= _T_1009 @[dec_tlu_ctl.scala 2242:36] + node _T_1010 = bits(wr_mtdata2_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2242:84] inst rvclkhdr_25 of rvclkhdr_745 @[lib.scala 368:23] rvclkhdr_25.clock <= clock rvclkhdr_25.reset <= reset rvclkhdr_25.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_25.io.en <= _T_1000 @[lib.scala 371:17] + rvclkhdr_25.io.en <= _T_1010 @[lib.scala 371:17] rvclkhdr_25.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_1001 : UInt, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_1001 <= io.dec_csr_wrdata_r @[lib.scala 374:16] - mtdata2_t[3] <= _T_1001 @[dec_tlu_ctl.scala 2244:36] - node _T_1002 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2248:57] - node _T_1003 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2248:57] - node _T_1004 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2248:57] - node _T_1005 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2248:57] - node _T_1006 = mux(_T_1002, mtdata2_t[0], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1007 = mux(_T_1003, mtdata2_t[1], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1008 = mux(_T_1004, mtdata2_t[2], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1009 = mux(_T_1005, mtdata2_t[3], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1010 = or(_T_1006, _T_1007) @[Mux.scala 27:72] - node _T_1011 = or(_T_1010, _T_1008) @[Mux.scala 27:72] - node _T_1012 = or(_T_1011, _T_1009) @[Mux.scala 27:72] + reg _T_1011 : UInt, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_1011 <= io.dec_csr_wrdata_r @[lib.scala 374:16] + mtdata2_t[3] <= _T_1011 @[dec_tlu_ctl.scala 2242:36] + node _T_1012 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2246:57] + node _T_1013 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2246:57] + node _T_1014 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2246:57] + node _T_1015 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2246:57] + node _T_1016 = mux(_T_1012, mtdata2_t[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1017 = mux(_T_1013, mtdata2_t[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1018 = mux(_T_1014, mtdata2_t[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1019 = mux(_T_1015, mtdata2_t[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1020 = or(_T_1016, _T_1017) @[Mux.scala 27:72] + node _T_1021 = or(_T_1020, _T_1018) @[Mux.scala 27:72] + node _T_1022 = or(_T_1021, _T_1019) @[Mux.scala 27:72] wire mtdata2_tsel_out : UInt<32> @[Mux.scala 27:72] - mtdata2_tsel_out <= _T_1012 @[Mux.scala 27:72] - io.trigger_pkt_any[0].tdata2 <= mtdata2_t[0] @[dec_tlu_ctl.scala 2249:51] - io.trigger_pkt_any[1].tdata2 <= mtdata2_t[1] @[dec_tlu_ctl.scala 2249:51] - io.trigger_pkt_any[2].tdata2 <= mtdata2_t[2] @[dec_tlu_ctl.scala 2249:51] - io.trigger_pkt_any[3].tdata2 <= mtdata2_t[3] @[dec_tlu_ctl.scala 2249:51] - mhpme_vec[0] <= mhpme3 @[dec_tlu_ctl.scala 2259:15] - mhpme_vec[1] <= mhpme4 @[dec_tlu_ctl.scala 2260:15] - mhpme_vec[2] <= mhpme5 @[dec_tlu_ctl.scala 2261:15] - mhpme_vec[3] <= mhpme6 @[dec_tlu_ctl.scala 2262:15] - node _T_1013 = bits(io.tlu_i0_commit_cmt, 0, 0) @[Bitwise.scala 72:15] - node _T_1014 = mux(_T_1013, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node pmu_i0_itype_qual = and(io.dec_tlu_packet_r.pmu_i0_itype, _T_1014) @[dec_tlu_ctl.scala 2268:59] - wire mhpmc_inc_r : UInt<1>[4] @[dec_tlu_ctl.scala 2269:24] - wire mhpmc_inc_r_d1 : UInt<1>[4] @[dec_tlu_ctl.scala 2270:27] - node _T_1015 = bits(mcountinhibit, 3, 3) @[dec_tlu_ctl.scala 2274:38] - node _T_1016 = not(_T_1015) @[dec_tlu_ctl.scala 2274:24] - node _T_1017 = eq(mhpme_vec[0], UInt<1>("h01")) @[dec_tlu_ctl.scala 2275:34] - node _T_1018 = bits(_T_1017, 0, 0) @[dec_tlu_ctl.scala 2275:62] - node _T_1019 = eq(mhpme_vec[0], UInt<2>("h02")) @[dec_tlu_ctl.scala 2276:34] - node _T_1020 = bits(_T_1019, 0, 0) @[dec_tlu_ctl.scala 2276:62] - node _T_1021 = eq(mhpme_vec[0], UInt<2>("h03")) @[dec_tlu_ctl.scala 2277:34] - node _T_1022 = bits(_T_1021, 0, 0) @[dec_tlu_ctl.scala 2277:62] - node _T_1023 = eq(mhpme_vec[0], UInt<3>("h04")) @[dec_tlu_ctl.scala 2278:34] - node _T_1024 = bits(_T_1023, 0, 0) @[dec_tlu_ctl.scala 2278:62] - node _T_1025 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:96] - node _T_1026 = and(io.tlu_i0_commit_cmt, _T_1025) @[dec_tlu_ctl.scala 2278:94] - node _T_1027 = eq(mhpme_vec[0], UInt<3>("h05")) @[dec_tlu_ctl.scala 2279:34] - node _T_1028 = bits(_T_1027, 0, 0) @[dec_tlu_ctl.scala 2279:62] - node _T_1029 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:96] - node _T_1030 = and(io.tlu_i0_commit_cmt, _T_1029) @[dec_tlu_ctl.scala 2279:94] - node _T_1031 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] - node _T_1032 = and(_T_1030, _T_1031) @[dec_tlu_ctl.scala 2279:115] - node _T_1033 = eq(mhpme_vec[0], UInt<3>("h06")) @[dec_tlu_ctl.scala 2280:34] - node _T_1034 = bits(_T_1033, 0, 0) @[dec_tlu_ctl.scala 2280:62] - node _T_1035 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2280:94] - node _T_1036 = not(io.illegal_r) @[dec_tlu_ctl.scala 2280:117] - node _T_1037 = and(_T_1035, _T_1036) @[dec_tlu_ctl.scala 2280:115] - node _T_1038 = eq(mhpme_vec[0], UInt<3>("h07")) @[dec_tlu_ctl.scala 2281:34] - node _T_1039 = bits(_T_1038, 0, 0) @[dec_tlu_ctl.scala 2281:62] - node _T_1040 = eq(mhpme_vec[0], UInt<4>("h08")) @[dec_tlu_ctl.scala 2282:34] - node _T_1041 = bits(_T_1040, 0, 0) @[dec_tlu_ctl.scala 2282:62] - node _T_1042 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2283:34] - node _T_1043 = bits(_T_1042, 0, 0) @[dec_tlu_ctl.scala 2283:62] - node _T_1044 = eq(mhpme_vec[0], UInt<4>("h09")) @[dec_tlu_ctl.scala 2284:34] - node _T_1045 = bits(_T_1044, 0, 0) @[dec_tlu_ctl.scala 2284:62] - node _T_1046 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2284:91] - node _T_1047 = eq(mhpme_vec[0], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2285:34] - node _T_1048 = bits(_T_1047, 0, 0) @[dec_tlu_ctl.scala 2285:62] - node _T_1049 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2285:105] - node _T_1050 = eq(mhpme_vec[0], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2286:34] - node _T_1051 = bits(_T_1050, 0, 0) @[dec_tlu_ctl.scala 2286:62] - node _T_1052 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2286:91] - node _T_1053 = eq(mhpme_vec[0], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2287:34] - node _T_1054 = bits(_T_1053, 0, 0) @[dec_tlu_ctl.scala 2287:62] - node _T_1055 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2287:91] - node _T_1056 = eq(mhpme_vec[0], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2288:34] - node _T_1057 = bits(_T_1056, 0, 0) @[dec_tlu_ctl.scala 2288:62] - node _T_1058 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2288:91] - node _T_1059 = and(_T_1058, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2288:100] - node _T_1060 = eq(mhpme_vec[0], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2289:34] - node _T_1061 = bits(_T_1060, 0, 0) @[dec_tlu_ctl.scala 2289:62] - node _T_1062 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2289:91] - node _T_1063 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2289:142] - node _T_1064 = and(_T_1062, _T_1063) @[dec_tlu_ctl.scala 2289:101] - node _T_1065 = eq(mhpme_vec[0], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2290:34] - node _T_1066 = bits(_T_1065, 0, 0) @[dec_tlu_ctl.scala 2290:59] - node _T_1067 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2290:89] - node _T_1068 = eq(mhpme_vec[0], UInt<5>("h010")) @[dec_tlu_ctl.scala 2291:34] - node _T_1069 = bits(_T_1068, 0, 0) @[dec_tlu_ctl.scala 2291:59] - node _T_1070 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2291:89] - node _T_1071 = eq(mhpme_vec[0], UInt<5>("h012")) @[dec_tlu_ctl.scala 2292:34] - node _T_1072 = bits(_T_1071, 0, 0) @[dec_tlu_ctl.scala 2292:59] - node _T_1073 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2292:89] - node _T_1074 = eq(mhpme_vec[0], UInt<5>("h011")) @[dec_tlu_ctl.scala 2293:34] - node _T_1075 = bits(_T_1074, 0, 0) @[dec_tlu_ctl.scala 2293:59] - node _T_1076 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2293:89] - node _T_1077 = eq(mhpme_vec[0], UInt<5>("h013")) @[dec_tlu_ctl.scala 2294:34] - node _T_1078 = bits(_T_1077, 0, 0) @[dec_tlu_ctl.scala 2294:59] - node _T_1079 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2294:89] - node _T_1080 = eq(mhpme_vec[0], UInt<5>("h014")) @[dec_tlu_ctl.scala 2295:34] - node _T_1081 = bits(_T_1080, 0, 0) @[dec_tlu_ctl.scala 2295:59] - node _T_1082 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2295:89] - node _T_1083 = eq(mhpme_vec[0], UInt<5>("h015")) @[dec_tlu_ctl.scala 2296:34] - node _T_1084 = bits(_T_1083, 0, 0) @[dec_tlu_ctl.scala 2296:59] - node _T_1085 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2296:89] - node _T_1086 = eq(mhpme_vec[0], UInt<5>("h016")) @[dec_tlu_ctl.scala 2297:34] - node _T_1087 = bits(_T_1086, 0, 0) @[dec_tlu_ctl.scala 2297:59] - node _T_1088 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2297:89] - node _T_1089 = eq(mhpme_vec[0], UInt<5>("h017")) @[dec_tlu_ctl.scala 2298:34] - node _T_1090 = bits(_T_1089, 0, 0) @[dec_tlu_ctl.scala 2298:59] - node _T_1091 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2298:89] - node _T_1092 = eq(mhpme_vec[0], UInt<5>("h018")) @[dec_tlu_ctl.scala 2299:34] - node _T_1093 = bits(_T_1092, 0, 0) @[dec_tlu_ctl.scala 2299:59] - node _T_1094 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2299:89] - node _T_1095 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2299:122] - node _T_1096 = or(_T_1094, _T_1095) @[dec_tlu_ctl.scala 2299:101] - node _T_1097 = eq(mhpme_vec[0], UInt<5>("h019")) @[dec_tlu_ctl.scala 2300:34] - node _T_1098 = bits(_T_1097, 0, 0) @[dec_tlu_ctl.scala 2300:62] - node _T_1099 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:95] - node _T_1100 = eq(mhpme_vec[0], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2301:34] - node _T_1101 = bits(_T_1100, 0, 0) @[dec_tlu_ctl.scala 2301:62] - node _T_1102 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:97] - node _T_1103 = eq(mhpme_vec[0], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2302:34] - node _T_1104 = bits(_T_1103, 0, 0) @[dec_tlu_ctl.scala 2302:62] - node _T_1105 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2302:110] - node _T_1106 = eq(mhpme_vec[0], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2303:34] - node _T_1107 = bits(_T_1106, 0, 0) @[dec_tlu_ctl.scala 2303:62] - node _T_1108 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2304:34] - node _T_1109 = bits(_T_1108, 0, 0) @[dec_tlu_ctl.scala 2304:62] - node _T_1110 = eq(mhpme_vec[0], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2305:34] - node _T_1111 = bits(_T_1110, 0, 0) @[dec_tlu_ctl.scala 2305:62] - node _T_1112 = eq(mhpme_vec[0], UInt<6>("h020")) @[dec_tlu_ctl.scala 2306:34] - node _T_1113 = bits(_T_1112, 0, 0) @[dec_tlu_ctl.scala 2306:62] - node _T_1114 = eq(mhpme_vec[0], UInt<6>("h022")) @[dec_tlu_ctl.scala 2307:34] - node _T_1115 = bits(_T_1114, 0, 0) @[dec_tlu_ctl.scala 2307:62] - node _T_1116 = eq(mhpme_vec[0], UInt<6>("h023")) @[dec_tlu_ctl.scala 2308:34] - node _T_1117 = bits(_T_1116, 0, 0) @[dec_tlu_ctl.scala 2308:62] - node _T_1118 = eq(mhpme_vec[0], UInt<6>("h024")) @[dec_tlu_ctl.scala 2309:34] - node _T_1119 = bits(_T_1118, 0, 0) @[dec_tlu_ctl.scala 2309:62] - node _T_1120 = eq(mhpme_vec[0], UInt<6>("h025")) @[dec_tlu_ctl.scala 2310:34] - node _T_1121 = bits(_T_1120, 0, 0) @[dec_tlu_ctl.scala 2310:62] - node _T_1122 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2310:98] - node _T_1123 = or(_T_1122, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2310:120] - node _T_1124 = eq(mhpme_vec[0], UInt<6>("h026")) @[dec_tlu_ctl.scala 2311:34] - node _T_1125 = bits(_T_1124, 0, 0) @[dec_tlu_ctl.scala 2311:62] - node _T_1126 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2311:92] - node _T_1127 = or(_T_1126, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2311:117] - node _T_1128 = eq(mhpme_vec[0], UInt<6>("h027")) @[dec_tlu_ctl.scala 2312:34] - node _T_1129 = bits(_T_1128, 0, 0) @[dec_tlu_ctl.scala 2312:62] - node _T_1130 = eq(mhpme_vec[0], UInt<6>("h028")) @[dec_tlu_ctl.scala 2313:34] - node _T_1131 = bits(_T_1130, 0, 0) @[dec_tlu_ctl.scala 2313:62] - node _T_1132 = eq(mhpme_vec[0], UInt<6>("h029")) @[dec_tlu_ctl.scala 2314:34] - node _T_1133 = bits(_T_1132, 0, 0) @[dec_tlu_ctl.scala 2314:62] - node _T_1134 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2314:97] - node _T_1135 = and(_T_1134, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2314:129] - node _T_1136 = eq(mhpme_vec[0], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2315:34] - node _T_1137 = bits(_T_1136, 0, 0) @[dec_tlu_ctl.scala 2315:62] - node _T_1138 = eq(mhpme_vec[0], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2316:34] - node _T_1139 = bits(_T_1138, 0, 0) @[dec_tlu_ctl.scala 2316:62] - node _T_1140 = eq(mhpme_vec[0], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2317:34] - node _T_1141 = bits(_T_1140, 0, 0) @[dec_tlu_ctl.scala 2317:62] - node _T_1142 = eq(mhpme_vec[0], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2318:34] - node _T_1143 = bits(_T_1142, 0, 0) @[dec_tlu_ctl.scala 2318:62] - node _T_1144 = eq(mhpme_vec[0], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2319:34] - node _T_1145 = bits(_T_1144, 0, 0) @[dec_tlu_ctl.scala 2319:62] - node _T_1146 = eq(mhpme_vec[0], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2320:34] - node _T_1147 = bits(_T_1146, 0, 0) @[dec_tlu_ctl.scala 2320:62] - node _T_1148 = eq(mhpme_vec[0], UInt<6>("h030")) @[dec_tlu_ctl.scala 2321:34] - node _T_1149 = bits(_T_1148, 0, 0) @[dec_tlu_ctl.scala 2321:62] - node _T_1150 = eq(mhpme_vec[0], UInt<6>("h031")) @[dec_tlu_ctl.scala 2322:34] - node _T_1151 = bits(_T_1150, 0, 0) @[dec_tlu_ctl.scala 2322:62] - node _T_1152 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] - node _T_1153 = bits(_T_1152, 0, 0) @[dec_tlu_ctl.scala 2322:84] - node _T_1154 = not(_T_1153) @[dec_tlu_ctl.scala 2322:73] - node _T_1155 = eq(mhpme_vec[0], UInt<6>("h032")) @[dec_tlu_ctl.scala 2323:34] - node _T_1156 = bits(_T_1155, 0, 0) @[dec_tlu_ctl.scala 2323:62] - node _T_1157 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2323:84] - node _T_1158 = bits(_T_1157, 0, 0) @[dec_tlu_ctl.scala 2323:84] - node _T_1159 = not(_T_1158) @[dec_tlu_ctl.scala 2323:73] - node _T_1160 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2323:107] - node _T_1161 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2323:118] - node _T_1162 = and(_T_1160, _T_1161) @[dec_tlu_ctl.scala 2323:113] - node _T_1163 = orr(_T_1162) @[dec_tlu_ctl.scala 2323:125] - node _T_1164 = and(_T_1159, _T_1163) @[dec_tlu_ctl.scala 2323:98] - node _T_1165 = eq(mhpme_vec[0], UInt<6>("h036")) @[dec_tlu_ctl.scala 2324:34] - node _T_1166 = bits(_T_1165, 0, 0) @[dec_tlu_ctl.scala 2324:62] - node _T_1167 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2324:91] - node _T_1168 = eq(mhpme_vec[0], UInt<6>("h037")) @[dec_tlu_ctl.scala 2325:34] - node _T_1169 = bits(_T_1168, 0, 0) @[dec_tlu_ctl.scala 2325:62] - node _T_1170 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2325:94] - node _T_1171 = eq(mhpme_vec[0], UInt<6>("h038")) @[dec_tlu_ctl.scala 2326:34] - node _T_1172 = bits(_T_1171, 0, 0) @[dec_tlu_ctl.scala 2326:62] - node _T_1173 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2326:94] - node _T_1174 = eq(mhpme_vec[0], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2328:34] - node _T_1175 = bits(_T_1174, 0, 0) @[dec_tlu_ctl.scala 2328:62] - node _T_1176 = eq(mhpme_vec[0], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2329:34] - node _T_1177 = bits(_T_1176, 0, 0) @[dec_tlu_ctl.scala 2329:62] - node _T_1178 = eq(mhpme_vec[0], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2330:34] - node _T_1179 = bits(_T_1178, 0, 0) @[dec_tlu_ctl.scala 2330:62] - node _T_1180 = eq(mhpme_vec[0], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2331:34] - node _T_1181 = bits(_T_1180, 0, 0) @[dec_tlu_ctl.scala 2331:62] - node _T_1182 = eq(mhpme_vec[0], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2332:34] - node _T_1183 = bits(_T_1182, 0, 0) @[dec_tlu_ctl.scala 2332:62] - node _T_1184 = mux(_T_1018, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1185 = mux(_T_1020, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1186 = mux(_T_1022, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1187 = mux(_T_1024, _T_1026, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1188 = mux(_T_1028, _T_1032, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1189 = mux(_T_1034, _T_1037, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1190 = mux(_T_1039, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1191 = mux(_T_1041, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1192 = mux(_T_1043, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1193 = mux(_T_1045, _T_1046, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1194 = mux(_T_1048, _T_1049, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1195 = mux(_T_1051, _T_1052, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1196 = mux(_T_1054, _T_1055, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1197 = mux(_T_1057, _T_1059, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1198 = mux(_T_1061, _T_1064, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1199 = mux(_T_1066, _T_1067, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1200 = mux(_T_1069, _T_1070, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1201 = mux(_T_1072, _T_1073, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1202 = mux(_T_1075, _T_1076, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1203 = mux(_T_1078, _T_1079, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1204 = mux(_T_1081, _T_1082, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1205 = mux(_T_1084, _T_1085, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1206 = mux(_T_1087, _T_1088, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1207 = mux(_T_1090, _T_1091, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1208 = mux(_T_1093, _T_1096, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1209 = mux(_T_1098, _T_1099, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1210 = mux(_T_1101, _T_1102, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1211 = mux(_T_1104, _T_1105, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1212 = mux(_T_1107, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1213 = mux(_T_1109, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1214 = mux(_T_1111, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1215 = mux(_T_1113, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1216 = mux(_T_1115, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1217 = mux(_T_1117, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1218 = mux(_T_1119, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1219 = mux(_T_1121, _T_1123, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1220 = mux(_T_1125, _T_1127, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1221 = mux(_T_1129, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1222 = mux(_T_1131, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1223 = mux(_T_1133, _T_1135, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1224 = mux(_T_1137, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1225 = mux(_T_1139, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1226 = mux(_T_1141, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1227 = mux(_T_1143, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1228 = mux(_T_1145, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1229 = mux(_T_1147, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1230 = mux(_T_1149, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1231 = mux(_T_1151, _T_1154, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1232 = mux(_T_1156, _T_1164, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1233 = mux(_T_1166, _T_1167, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1234 = mux(_T_1169, _T_1170, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1235 = mux(_T_1172, _T_1173, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1236 = mux(_T_1175, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1237 = mux(_T_1177, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1238 = mux(_T_1179, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1239 = mux(_T_1181, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1240 = mux(_T_1183, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1241 = or(_T_1184, _T_1185) @[Mux.scala 27:72] - node _T_1242 = or(_T_1241, _T_1186) @[Mux.scala 27:72] - node _T_1243 = or(_T_1242, _T_1187) @[Mux.scala 27:72] - node _T_1244 = or(_T_1243, _T_1188) @[Mux.scala 27:72] - node _T_1245 = or(_T_1244, _T_1189) @[Mux.scala 27:72] - node _T_1246 = or(_T_1245, _T_1190) @[Mux.scala 27:72] - node _T_1247 = or(_T_1246, _T_1191) @[Mux.scala 27:72] - node _T_1248 = or(_T_1247, _T_1192) @[Mux.scala 27:72] - node _T_1249 = or(_T_1248, _T_1193) @[Mux.scala 27:72] - node _T_1250 = or(_T_1249, _T_1194) @[Mux.scala 27:72] - node _T_1251 = or(_T_1250, _T_1195) @[Mux.scala 27:72] + mtdata2_tsel_out <= _T_1022 @[Mux.scala 27:72] + io.trigger_pkt_any[0].tdata2 <= mtdata2_t[0] @[dec_tlu_ctl.scala 2247:51] + io.trigger_pkt_any[1].tdata2 <= mtdata2_t[1] @[dec_tlu_ctl.scala 2247:51] + io.trigger_pkt_any[2].tdata2 <= mtdata2_t[2] @[dec_tlu_ctl.scala 2247:51] + io.trigger_pkt_any[3].tdata2 <= mtdata2_t[3] @[dec_tlu_ctl.scala 2247:51] + mhpme_vec[0] <= mhpme3 @[dec_tlu_ctl.scala 2257:15] + mhpme_vec[1] <= mhpme4 @[dec_tlu_ctl.scala 2258:15] + mhpme_vec[2] <= mhpme5 @[dec_tlu_ctl.scala 2259:15] + mhpme_vec[3] <= mhpme6 @[dec_tlu_ctl.scala 2260:15] + node _T_1023 = bits(io.tlu_i0_commit_cmt, 0, 0) @[Bitwise.scala 72:15] + node _T_1024 = mux(_T_1023, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node pmu_i0_itype_qual = and(io.dec_tlu_packet_r.pmu_i0_itype, _T_1024) @[dec_tlu_ctl.scala 2266:59] + wire mhpmc_inc_r : UInt<1>[4] @[dec_tlu_ctl.scala 2267:24] + wire mhpmc_inc_r_d1 : UInt<1>[4] @[dec_tlu_ctl.scala 2268:27] + node _T_1025 = bits(mcountinhibit, 3, 3) @[dec_tlu_ctl.scala 2272:38] + node _T_1026 = not(_T_1025) @[dec_tlu_ctl.scala 2272:24] + node _T_1027 = eq(mhpme_vec[0], UInt<1>("h01")) @[dec_tlu_ctl.scala 2273:34] + node _T_1028 = bits(_T_1027, 0, 0) @[dec_tlu_ctl.scala 2273:62] + node _T_1029 = eq(mhpme_vec[0], UInt<2>("h02")) @[dec_tlu_ctl.scala 2274:34] + node _T_1030 = bits(_T_1029, 0, 0) @[dec_tlu_ctl.scala 2274:62] + node _T_1031 = eq(mhpme_vec[0], UInt<2>("h03")) @[dec_tlu_ctl.scala 2275:34] + node _T_1032 = bits(_T_1031, 0, 0) @[dec_tlu_ctl.scala 2275:62] + node _T_1033 = eq(mhpme_vec[0], UInt<3>("h04")) @[dec_tlu_ctl.scala 2276:34] + node _T_1034 = bits(_T_1033, 0, 0) @[dec_tlu_ctl.scala 2276:62] + node _T_1035 = not(io.illegal_r) @[dec_tlu_ctl.scala 2276:96] + node _T_1036 = and(io.tlu_i0_commit_cmt, _T_1035) @[dec_tlu_ctl.scala 2276:94] + node _T_1037 = eq(mhpme_vec[0], UInt<3>("h05")) @[dec_tlu_ctl.scala 2277:34] + node _T_1038 = bits(_T_1037, 0, 0) @[dec_tlu_ctl.scala 2277:62] + node _T_1039 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2277:96] + node _T_1040 = and(io.tlu_i0_commit_cmt, _T_1039) @[dec_tlu_ctl.scala 2277:94] + node _T_1041 = not(io.illegal_r) @[dec_tlu_ctl.scala 2277:117] + node _T_1042 = and(_T_1040, _T_1041) @[dec_tlu_ctl.scala 2277:115] + node _T_1043 = eq(mhpme_vec[0], UInt<3>("h06")) @[dec_tlu_ctl.scala 2278:34] + node _T_1044 = bits(_T_1043, 0, 0) @[dec_tlu_ctl.scala 2278:62] + node _T_1045 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2278:94] + node _T_1046 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:117] + node _T_1047 = and(_T_1045, _T_1046) @[dec_tlu_ctl.scala 2278:115] + node _T_1048 = eq(mhpme_vec[0], UInt<3>("h07")) @[dec_tlu_ctl.scala 2279:34] + node _T_1049 = bits(_T_1048, 0, 0) @[dec_tlu_ctl.scala 2279:62] + node _T_1050 = eq(mhpme_vec[0], UInt<4>("h08")) @[dec_tlu_ctl.scala 2280:34] + node _T_1051 = bits(_T_1050, 0, 0) @[dec_tlu_ctl.scala 2280:62] + node _T_1052 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2281:34] + node _T_1053 = bits(_T_1052, 0, 0) @[dec_tlu_ctl.scala 2281:62] + node _T_1054 = eq(mhpme_vec[0], UInt<4>("h09")) @[dec_tlu_ctl.scala 2282:34] + node _T_1055 = bits(_T_1054, 0, 0) @[dec_tlu_ctl.scala 2282:62] + node _T_1056 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2282:91] + node _T_1057 = eq(mhpme_vec[0], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2283:34] + node _T_1058 = bits(_T_1057, 0, 0) @[dec_tlu_ctl.scala 2283:62] + node _T_1059 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2283:105] + node _T_1060 = eq(mhpme_vec[0], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2284:34] + node _T_1061 = bits(_T_1060, 0, 0) @[dec_tlu_ctl.scala 2284:62] + node _T_1062 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2284:91] + node _T_1063 = eq(mhpme_vec[0], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2285:34] + node _T_1064 = bits(_T_1063, 0, 0) @[dec_tlu_ctl.scala 2285:62] + node _T_1065 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2285:91] + node _T_1066 = eq(mhpme_vec[0], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2286:34] + node _T_1067 = bits(_T_1066, 0, 0) @[dec_tlu_ctl.scala 2286:62] + node _T_1068 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2286:91] + node _T_1069 = and(_T_1068, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2286:100] + node _T_1070 = eq(mhpme_vec[0], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2287:34] + node _T_1071 = bits(_T_1070, 0, 0) @[dec_tlu_ctl.scala 2287:62] + node _T_1072 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2287:91] + node _T_1073 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2287:142] + node _T_1074 = and(_T_1072, _T_1073) @[dec_tlu_ctl.scala 2287:101] + node _T_1075 = eq(mhpme_vec[0], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2288:34] + node _T_1076 = bits(_T_1075, 0, 0) @[dec_tlu_ctl.scala 2288:59] + node _T_1077 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2288:89] + node _T_1078 = eq(mhpme_vec[0], UInt<5>("h010")) @[dec_tlu_ctl.scala 2289:34] + node _T_1079 = bits(_T_1078, 0, 0) @[dec_tlu_ctl.scala 2289:59] + node _T_1080 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2289:89] + node _T_1081 = eq(mhpme_vec[0], UInt<5>("h012")) @[dec_tlu_ctl.scala 2290:34] + node _T_1082 = bits(_T_1081, 0, 0) @[dec_tlu_ctl.scala 2290:59] + node _T_1083 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2290:89] + node _T_1084 = eq(mhpme_vec[0], UInt<5>("h011")) @[dec_tlu_ctl.scala 2291:34] + node _T_1085 = bits(_T_1084, 0, 0) @[dec_tlu_ctl.scala 2291:59] + node _T_1086 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2291:89] + node _T_1087 = eq(mhpme_vec[0], UInt<5>("h013")) @[dec_tlu_ctl.scala 2292:34] + node _T_1088 = bits(_T_1087, 0, 0) @[dec_tlu_ctl.scala 2292:59] + node _T_1089 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2292:89] + node _T_1090 = eq(mhpme_vec[0], UInt<5>("h014")) @[dec_tlu_ctl.scala 2293:34] + node _T_1091 = bits(_T_1090, 0, 0) @[dec_tlu_ctl.scala 2293:59] + node _T_1092 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2293:89] + node _T_1093 = eq(mhpme_vec[0], UInt<5>("h015")) @[dec_tlu_ctl.scala 2294:34] + node _T_1094 = bits(_T_1093, 0, 0) @[dec_tlu_ctl.scala 2294:59] + node _T_1095 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2294:89] + node _T_1096 = eq(mhpme_vec[0], UInt<5>("h016")) @[dec_tlu_ctl.scala 2295:34] + node _T_1097 = bits(_T_1096, 0, 0) @[dec_tlu_ctl.scala 2295:59] + node _T_1098 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2295:89] + node _T_1099 = eq(mhpme_vec[0], UInt<5>("h017")) @[dec_tlu_ctl.scala 2296:34] + node _T_1100 = bits(_T_1099, 0, 0) @[dec_tlu_ctl.scala 2296:59] + node _T_1101 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2296:89] + node _T_1102 = eq(mhpme_vec[0], UInt<5>("h018")) @[dec_tlu_ctl.scala 2297:34] + node _T_1103 = bits(_T_1102, 0, 0) @[dec_tlu_ctl.scala 2297:59] + node _T_1104 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2297:89] + node _T_1105 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2297:122] + node _T_1106 = or(_T_1104, _T_1105) @[dec_tlu_ctl.scala 2297:101] + node _T_1107 = eq(mhpme_vec[0], UInt<5>("h019")) @[dec_tlu_ctl.scala 2298:34] + node _T_1108 = bits(_T_1107, 0, 0) @[dec_tlu_ctl.scala 2298:62] + node _T_1109 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2298:95] + node _T_1110 = eq(mhpme_vec[0], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2299:34] + node _T_1111 = bits(_T_1110, 0, 0) @[dec_tlu_ctl.scala 2299:62] + node _T_1112 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2299:97] + node _T_1113 = eq(mhpme_vec[0], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2300:34] + node _T_1114 = bits(_T_1113, 0, 0) @[dec_tlu_ctl.scala 2300:62] + node _T_1115 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:110] + node _T_1116 = eq(mhpme_vec[0], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2301:34] + node _T_1117 = bits(_T_1116, 0, 0) @[dec_tlu_ctl.scala 2301:62] + node _T_1118 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2302:34] + node _T_1119 = bits(_T_1118, 0, 0) @[dec_tlu_ctl.scala 2302:62] + node _T_1120 = eq(mhpme_vec[0], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2303:34] + node _T_1121 = bits(_T_1120, 0, 0) @[dec_tlu_ctl.scala 2303:62] + node _T_1122 = eq(mhpme_vec[0], UInt<6>("h020")) @[dec_tlu_ctl.scala 2304:34] + node _T_1123 = bits(_T_1122, 0, 0) @[dec_tlu_ctl.scala 2304:62] + node _T_1124 = eq(mhpme_vec[0], UInt<6>("h022")) @[dec_tlu_ctl.scala 2305:34] + node _T_1125 = bits(_T_1124, 0, 0) @[dec_tlu_ctl.scala 2305:62] + node _T_1126 = eq(mhpme_vec[0], UInt<6>("h023")) @[dec_tlu_ctl.scala 2306:34] + node _T_1127 = bits(_T_1126, 0, 0) @[dec_tlu_ctl.scala 2306:62] + node _T_1128 = eq(mhpme_vec[0], UInt<6>("h024")) @[dec_tlu_ctl.scala 2307:34] + node _T_1129 = bits(_T_1128, 0, 0) @[dec_tlu_ctl.scala 2307:62] + node _T_1130 = eq(mhpme_vec[0], UInt<6>("h025")) @[dec_tlu_ctl.scala 2308:34] + node _T_1131 = bits(_T_1130, 0, 0) @[dec_tlu_ctl.scala 2308:62] + node _T_1132 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2308:98] + node _T_1133 = or(_T_1132, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2308:120] + node _T_1134 = eq(mhpme_vec[0], UInt<6>("h026")) @[dec_tlu_ctl.scala 2309:34] + node _T_1135 = bits(_T_1134, 0, 0) @[dec_tlu_ctl.scala 2309:62] + node _T_1136 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2309:92] + node _T_1137 = or(_T_1136, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2309:117] + node _T_1138 = eq(mhpme_vec[0], UInt<6>("h027")) @[dec_tlu_ctl.scala 2310:34] + node _T_1139 = bits(_T_1138, 0, 0) @[dec_tlu_ctl.scala 2310:62] + node _T_1140 = eq(mhpme_vec[0], UInt<6>("h028")) @[dec_tlu_ctl.scala 2311:34] + node _T_1141 = bits(_T_1140, 0, 0) @[dec_tlu_ctl.scala 2311:62] + node _T_1142 = eq(mhpme_vec[0], UInt<6>("h029")) @[dec_tlu_ctl.scala 2312:34] + node _T_1143 = bits(_T_1142, 0, 0) @[dec_tlu_ctl.scala 2312:62] + node _T_1144 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2312:97] + node _T_1145 = and(_T_1144, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2312:129] + node _T_1146 = eq(mhpme_vec[0], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2313:34] + node _T_1147 = bits(_T_1146, 0, 0) @[dec_tlu_ctl.scala 2313:62] + node _T_1148 = eq(mhpme_vec[0], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2314:34] + node _T_1149 = bits(_T_1148, 0, 0) @[dec_tlu_ctl.scala 2314:62] + node _T_1150 = eq(mhpme_vec[0], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2315:34] + node _T_1151 = bits(_T_1150, 0, 0) @[dec_tlu_ctl.scala 2315:62] + node _T_1152 = eq(mhpme_vec[0], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2316:34] + node _T_1153 = bits(_T_1152, 0, 0) @[dec_tlu_ctl.scala 2316:62] + node _T_1154 = eq(mhpme_vec[0], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2317:34] + node _T_1155 = bits(_T_1154, 0, 0) @[dec_tlu_ctl.scala 2317:62] + node _T_1156 = eq(mhpme_vec[0], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2318:34] + node _T_1157 = bits(_T_1156, 0, 0) @[dec_tlu_ctl.scala 2318:62] + node _T_1158 = eq(mhpme_vec[0], UInt<6>("h030")) @[dec_tlu_ctl.scala 2319:34] + node _T_1159 = bits(_T_1158, 0, 0) @[dec_tlu_ctl.scala 2319:62] + node _T_1160 = eq(mhpme_vec[0], UInt<6>("h031")) @[dec_tlu_ctl.scala 2320:34] + node _T_1161 = bits(_T_1160, 0, 0) @[dec_tlu_ctl.scala 2320:62] + node _T_1162 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2320:84] + node _T_1163 = bits(_T_1162, 0, 0) @[dec_tlu_ctl.scala 2320:84] + node _T_1164 = not(_T_1163) @[dec_tlu_ctl.scala 2320:73] + node _T_1165 = eq(mhpme_vec[0], UInt<6>("h032")) @[dec_tlu_ctl.scala 2321:34] + node _T_1166 = bits(_T_1165, 0, 0) @[dec_tlu_ctl.scala 2321:62] + node _T_1167 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2321:84] + node _T_1168 = bits(_T_1167, 0, 0) @[dec_tlu_ctl.scala 2321:84] + node _T_1169 = not(_T_1168) @[dec_tlu_ctl.scala 2321:73] + node _T_1170 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2321:107] + node _T_1171 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2321:118] + node _T_1172 = and(_T_1170, _T_1171) @[dec_tlu_ctl.scala 2321:113] + node _T_1173 = orr(_T_1172) @[dec_tlu_ctl.scala 2321:125] + node _T_1174 = and(_T_1169, _T_1173) @[dec_tlu_ctl.scala 2321:98] + node _T_1175 = eq(mhpme_vec[0], UInt<6>("h036")) @[dec_tlu_ctl.scala 2322:34] + node _T_1176 = bits(_T_1175, 0, 0) @[dec_tlu_ctl.scala 2322:62] + node _T_1177 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2322:91] + node _T_1178 = eq(mhpme_vec[0], UInt<6>("h037")) @[dec_tlu_ctl.scala 2323:34] + node _T_1179 = bits(_T_1178, 0, 0) @[dec_tlu_ctl.scala 2323:62] + node _T_1180 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2323:94] + node _T_1181 = eq(mhpme_vec[0], UInt<6>("h038")) @[dec_tlu_ctl.scala 2324:34] + node _T_1182 = bits(_T_1181, 0, 0) @[dec_tlu_ctl.scala 2324:62] + node _T_1183 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2324:94] + node _T_1184 = eq(mhpme_vec[0], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2326:34] + node _T_1185 = bits(_T_1184, 0, 0) @[dec_tlu_ctl.scala 2326:62] + node _T_1186 = eq(mhpme_vec[0], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2327:34] + node _T_1187 = bits(_T_1186, 0, 0) @[dec_tlu_ctl.scala 2327:62] + node _T_1188 = eq(mhpme_vec[0], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2328:34] + node _T_1189 = bits(_T_1188, 0, 0) @[dec_tlu_ctl.scala 2328:62] + node _T_1190 = eq(mhpme_vec[0], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2329:34] + node _T_1191 = bits(_T_1190, 0, 0) @[dec_tlu_ctl.scala 2329:62] + node _T_1192 = eq(mhpme_vec[0], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2330:34] + node _T_1193 = bits(_T_1192, 0, 0) @[dec_tlu_ctl.scala 2330:62] + node _T_1194 = mux(_T_1028, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1195 = mux(_T_1030, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1196 = mux(_T_1032, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1197 = mux(_T_1034, _T_1036, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1198 = mux(_T_1038, _T_1042, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1199 = mux(_T_1044, _T_1047, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1200 = mux(_T_1049, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1201 = mux(_T_1051, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1202 = mux(_T_1053, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1203 = mux(_T_1055, _T_1056, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1204 = mux(_T_1058, _T_1059, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1205 = mux(_T_1061, _T_1062, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1206 = mux(_T_1064, _T_1065, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1207 = mux(_T_1067, _T_1069, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1208 = mux(_T_1071, _T_1074, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1209 = mux(_T_1076, _T_1077, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1210 = mux(_T_1079, _T_1080, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1211 = mux(_T_1082, _T_1083, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1212 = mux(_T_1085, _T_1086, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1213 = mux(_T_1088, _T_1089, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1214 = mux(_T_1091, _T_1092, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1215 = mux(_T_1094, _T_1095, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1216 = mux(_T_1097, _T_1098, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1217 = mux(_T_1100, _T_1101, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1218 = mux(_T_1103, _T_1106, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1219 = mux(_T_1108, _T_1109, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1220 = mux(_T_1111, _T_1112, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1221 = mux(_T_1114, _T_1115, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1222 = mux(_T_1117, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1223 = mux(_T_1119, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1224 = mux(_T_1121, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1225 = mux(_T_1123, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1226 = mux(_T_1125, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1227 = mux(_T_1127, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1228 = mux(_T_1129, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1229 = mux(_T_1131, _T_1133, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1230 = mux(_T_1135, _T_1137, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1231 = mux(_T_1139, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1232 = mux(_T_1141, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1233 = mux(_T_1143, _T_1145, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1234 = mux(_T_1147, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1235 = mux(_T_1149, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1236 = mux(_T_1151, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1237 = mux(_T_1153, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1238 = mux(_T_1155, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1239 = mux(_T_1157, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1240 = mux(_T_1159, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1241 = mux(_T_1161, _T_1164, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1242 = mux(_T_1166, _T_1174, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1243 = mux(_T_1176, _T_1177, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1244 = mux(_T_1179, _T_1180, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1245 = mux(_T_1182, _T_1183, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1246 = mux(_T_1185, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1247 = mux(_T_1187, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1248 = mux(_T_1189, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1249 = mux(_T_1191, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1250 = mux(_T_1193, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1251 = or(_T_1194, _T_1195) @[Mux.scala 27:72] node _T_1252 = or(_T_1251, _T_1196) @[Mux.scala 27:72] node _T_1253 = or(_T_1252, _T_1197) @[Mux.scala 27:72] node _T_1254 = or(_T_1253, _T_1198) @[Mux.scala 27:72] @@ -74686,247 +74686,247 @@ circuit quasar_wrapper : node _T_1294 = or(_T_1293, _T_1238) @[Mux.scala 27:72] node _T_1295 = or(_T_1294, _T_1239) @[Mux.scala 27:72] node _T_1296 = or(_T_1295, _T_1240) @[Mux.scala 27:72] - wire _T_1297 : UInt<1> @[Mux.scala 27:72] - _T_1297 <= _T_1296 @[Mux.scala 27:72] - node _T_1298 = and(_T_1016, _T_1297) @[dec_tlu_ctl.scala 2274:44] - mhpmc_inc_r[0] <= _T_1298 @[dec_tlu_ctl.scala 2274:19] - node _T_1299 = bits(mcountinhibit, 4, 4) @[dec_tlu_ctl.scala 2274:38] - node _T_1300 = not(_T_1299) @[dec_tlu_ctl.scala 2274:24] - node _T_1301 = eq(mhpme_vec[1], UInt<1>("h01")) @[dec_tlu_ctl.scala 2275:34] - node _T_1302 = bits(_T_1301, 0, 0) @[dec_tlu_ctl.scala 2275:62] - node _T_1303 = eq(mhpme_vec[1], UInt<2>("h02")) @[dec_tlu_ctl.scala 2276:34] - node _T_1304 = bits(_T_1303, 0, 0) @[dec_tlu_ctl.scala 2276:62] - node _T_1305 = eq(mhpme_vec[1], UInt<2>("h03")) @[dec_tlu_ctl.scala 2277:34] - node _T_1306 = bits(_T_1305, 0, 0) @[dec_tlu_ctl.scala 2277:62] - node _T_1307 = eq(mhpme_vec[1], UInt<3>("h04")) @[dec_tlu_ctl.scala 2278:34] - node _T_1308 = bits(_T_1307, 0, 0) @[dec_tlu_ctl.scala 2278:62] - node _T_1309 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:96] - node _T_1310 = and(io.tlu_i0_commit_cmt, _T_1309) @[dec_tlu_ctl.scala 2278:94] - node _T_1311 = eq(mhpme_vec[1], UInt<3>("h05")) @[dec_tlu_ctl.scala 2279:34] - node _T_1312 = bits(_T_1311, 0, 0) @[dec_tlu_ctl.scala 2279:62] - node _T_1313 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:96] - node _T_1314 = and(io.tlu_i0_commit_cmt, _T_1313) @[dec_tlu_ctl.scala 2279:94] - node _T_1315 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] - node _T_1316 = and(_T_1314, _T_1315) @[dec_tlu_ctl.scala 2279:115] - node _T_1317 = eq(mhpme_vec[1], UInt<3>("h06")) @[dec_tlu_ctl.scala 2280:34] - node _T_1318 = bits(_T_1317, 0, 0) @[dec_tlu_ctl.scala 2280:62] - node _T_1319 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2280:94] - node _T_1320 = not(io.illegal_r) @[dec_tlu_ctl.scala 2280:117] - node _T_1321 = and(_T_1319, _T_1320) @[dec_tlu_ctl.scala 2280:115] - node _T_1322 = eq(mhpme_vec[1], UInt<3>("h07")) @[dec_tlu_ctl.scala 2281:34] - node _T_1323 = bits(_T_1322, 0, 0) @[dec_tlu_ctl.scala 2281:62] - node _T_1324 = eq(mhpme_vec[1], UInt<4>("h08")) @[dec_tlu_ctl.scala 2282:34] - node _T_1325 = bits(_T_1324, 0, 0) @[dec_tlu_ctl.scala 2282:62] - node _T_1326 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2283:34] - node _T_1327 = bits(_T_1326, 0, 0) @[dec_tlu_ctl.scala 2283:62] - node _T_1328 = eq(mhpme_vec[1], UInt<4>("h09")) @[dec_tlu_ctl.scala 2284:34] - node _T_1329 = bits(_T_1328, 0, 0) @[dec_tlu_ctl.scala 2284:62] - node _T_1330 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2284:91] - node _T_1331 = eq(mhpme_vec[1], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2285:34] - node _T_1332 = bits(_T_1331, 0, 0) @[dec_tlu_ctl.scala 2285:62] - node _T_1333 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2285:105] - node _T_1334 = eq(mhpme_vec[1], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2286:34] - node _T_1335 = bits(_T_1334, 0, 0) @[dec_tlu_ctl.scala 2286:62] - node _T_1336 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2286:91] - node _T_1337 = eq(mhpme_vec[1], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2287:34] - node _T_1338 = bits(_T_1337, 0, 0) @[dec_tlu_ctl.scala 2287:62] - node _T_1339 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2287:91] - node _T_1340 = eq(mhpme_vec[1], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2288:34] - node _T_1341 = bits(_T_1340, 0, 0) @[dec_tlu_ctl.scala 2288:62] - node _T_1342 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2288:91] - node _T_1343 = and(_T_1342, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2288:100] - node _T_1344 = eq(mhpme_vec[1], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2289:34] - node _T_1345 = bits(_T_1344, 0, 0) @[dec_tlu_ctl.scala 2289:62] - node _T_1346 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2289:91] - node _T_1347 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2289:142] - node _T_1348 = and(_T_1346, _T_1347) @[dec_tlu_ctl.scala 2289:101] - node _T_1349 = eq(mhpme_vec[1], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2290:34] - node _T_1350 = bits(_T_1349, 0, 0) @[dec_tlu_ctl.scala 2290:59] - node _T_1351 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2290:89] - node _T_1352 = eq(mhpme_vec[1], UInt<5>("h010")) @[dec_tlu_ctl.scala 2291:34] - node _T_1353 = bits(_T_1352, 0, 0) @[dec_tlu_ctl.scala 2291:59] - node _T_1354 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2291:89] - node _T_1355 = eq(mhpme_vec[1], UInt<5>("h012")) @[dec_tlu_ctl.scala 2292:34] - node _T_1356 = bits(_T_1355, 0, 0) @[dec_tlu_ctl.scala 2292:59] - node _T_1357 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2292:89] - node _T_1358 = eq(mhpme_vec[1], UInt<5>("h011")) @[dec_tlu_ctl.scala 2293:34] - node _T_1359 = bits(_T_1358, 0, 0) @[dec_tlu_ctl.scala 2293:59] - node _T_1360 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2293:89] - node _T_1361 = eq(mhpme_vec[1], UInt<5>("h013")) @[dec_tlu_ctl.scala 2294:34] - node _T_1362 = bits(_T_1361, 0, 0) @[dec_tlu_ctl.scala 2294:59] - node _T_1363 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2294:89] - node _T_1364 = eq(mhpme_vec[1], UInt<5>("h014")) @[dec_tlu_ctl.scala 2295:34] - node _T_1365 = bits(_T_1364, 0, 0) @[dec_tlu_ctl.scala 2295:59] - node _T_1366 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2295:89] - node _T_1367 = eq(mhpme_vec[1], UInt<5>("h015")) @[dec_tlu_ctl.scala 2296:34] - node _T_1368 = bits(_T_1367, 0, 0) @[dec_tlu_ctl.scala 2296:59] - node _T_1369 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2296:89] - node _T_1370 = eq(mhpme_vec[1], UInt<5>("h016")) @[dec_tlu_ctl.scala 2297:34] - node _T_1371 = bits(_T_1370, 0, 0) @[dec_tlu_ctl.scala 2297:59] - node _T_1372 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2297:89] - node _T_1373 = eq(mhpme_vec[1], UInt<5>("h017")) @[dec_tlu_ctl.scala 2298:34] - node _T_1374 = bits(_T_1373, 0, 0) @[dec_tlu_ctl.scala 2298:59] - node _T_1375 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2298:89] - node _T_1376 = eq(mhpme_vec[1], UInt<5>("h018")) @[dec_tlu_ctl.scala 2299:34] - node _T_1377 = bits(_T_1376, 0, 0) @[dec_tlu_ctl.scala 2299:59] - node _T_1378 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2299:89] - node _T_1379 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2299:122] - node _T_1380 = or(_T_1378, _T_1379) @[dec_tlu_ctl.scala 2299:101] - node _T_1381 = eq(mhpme_vec[1], UInt<5>("h019")) @[dec_tlu_ctl.scala 2300:34] - node _T_1382 = bits(_T_1381, 0, 0) @[dec_tlu_ctl.scala 2300:62] - node _T_1383 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:95] - node _T_1384 = eq(mhpme_vec[1], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2301:34] - node _T_1385 = bits(_T_1384, 0, 0) @[dec_tlu_ctl.scala 2301:62] - node _T_1386 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:97] - node _T_1387 = eq(mhpme_vec[1], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2302:34] - node _T_1388 = bits(_T_1387, 0, 0) @[dec_tlu_ctl.scala 2302:62] - node _T_1389 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2302:110] - node _T_1390 = eq(mhpme_vec[1], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2303:34] - node _T_1391 = bits(_T_1390, 0, 0) @[dec_tlu_ctl.scala 2303:62] - node _T_1392 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2304:34] - node _T_1393 = bits(_T_1392, 0, 0) @[dec_tlu_ctl.scala 2304:62] - node _T_1394 = eq(mhpme_vec[1], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2305:34] - node _T_1395 = bits(_T_1394, 0, 0) @[dec_tlu_ctl.scala 2305:62] - node _T_1396 = eq(mhpme_vec[1], UInt<6>("h020")) @[dec_tlu_ctl.scala 2306:34] - node _T_1397 = bits(_T_1396, 0, 0) @[dec_tlu_ctl.scala 2306:62] - node _T_1398 = eq(mhpme_vec[1], UInt<6>("h022")) @[dec_tlu_ctl.scala 2307:34] - node _T_1399 = bits(_T_1398, 0, 0) @[dec_tlu_ctl.scala 2307:62] - node _T_1400 = eq(mhpme_vec[1], UInt<6>("h023")) @[dec_tlu_ctl.scala 2308:34] - node _T_1401 = bits(_T_1400, 0, 0) @[dec_tlu_ctl.scala 2308:62] - node _T_1402 = eq(mhpme_vec[1], UInt<6>("h024")) @[dec_tlu_ctl.scala 2309:34] - node _T_1403 = bits(_T_1402, 0, 0) @[dec_tlu_ctl.scala 2309:62] - node _T_1404 = eq(mhpme_vec[1], UInt<6>("h025")) @[dec_tlu_ctl.scala 2310:34] - node _T_1405 = bits(_T_1404, 0, 0) @[dec_tlu_ctl.scala 2310:62] - node _T_1406 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2310:98] - node _T_1407 = or(_T_1406, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2310:120] - node _T_1408 = eq(mhpme_vec[1], UInt<6>("h026")) @[dec_tlu_ctl.scala 2311:34] - node _T_1409 = bits(_T_1408, 0, 0) @[dec_tlu_ctl.scala 2311:62] - node _T_1410 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2311:92] - node _T_1411 = or(_T_1410, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2311:117] - node _T_1412 = eq(mhpme_vec[1], UInt<6>("h027")) @[dec_tlu_ctl.scala 2312:34] - node _T_1413 = bits(_T_1412, 0, 0) @[dec_tlu_ctl.scala 2312:62] - node _T_1414 = eq(mhpme_vec[1], UInt<6>("h028")) @[dec_tlu_ctl.scala 2313:34] - node _T_1415 = bits(_T_1414, 0, 0) @[dec_tlu_ctl.scala 2313:62] - node _T_1416 = eq(mhpme_vec[1], UInt<6>("h029")) @[dec_tlu_ctl.scala 2314:34] - node _T_1417 = bits(_T_1416, 0, 0) @[dec_tlu_ctl.scala 2314:62] - node _T_1418 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2314:97] - node _T_1419 = and(_T_1418, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2314:129] - node _T_1420 = eq(mhpme_vec[1], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2315:34] - node _T_1421 = bits(_T_1420, 0, 0) @[dec_tlu_ctl.scala 2315:62] - node _T_1422 = eq(mhpme_vec[1], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2316:34] - node _T_1423 = bits(_T_1422, 0, 0) @[dec_tlu_ctl.scala 2316:62] - node _T_1424 = eq(mhpme_vec[1], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2317:34] - node _T_1425 = bits(_T_1424, 0, 0) @[dec_tlu_ctl.scala 2317:62] - node _T_1426 = eq(mhpme_vec[1], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2318:34] - node _T_1427 = bits(_T_1426, 0, 0) @[dec_tlu_ctl.scala 2318:62] - node _T_1428 = eq(mhpme_vec[1], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2319:34] - node _T_1429 = bits(_T_1428, 0, 0) @[dec_tlu_ctl.scala 2319:62] - node _T_1430 = eq(mhpme_vec[1], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2320:34] - node _T_1431 = bits(_T_1430, 0, 0) @[dec_tlu_ctl.scala 2320:62] - node _T_1432 = eq(mhpme_vec[1], UInt<6>("h030")) @[dec_tlu_ctl.scala 2321:34] - node _T_1433 = bits(_T_1432, 0, 0) @[dec_tlu_ctl.scala 2321:62] - node _T_1434 = eq(mhpme_vec[1], UInt<6>("h031")) @[dec_tlu_ctl.scala 2322:34] - node _T_1435 = bits(_T_1434, 0, 0) @[dec_tlu_ctl.scala 2322:62] - node _T_1436 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] - node _T_1437 = bits(_T_1436, 0, 0) @[dec_tlu_ctl.scala 2322:84] - node _T_1438 = not(_T_1437) @[dec_tlu_ctl.scala 2322:73] - node _T_1439 = eq(mhpme_vec[1], UInt<6>("h032")) @[dec_tlu_ctl.scala 2323:34] - node _T_1440 = bits(_T_1439, 0, 0) @[dec_tlu_ctl.scala 2323:62] - node _T_1441 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2323:84] - node _T_1442 = bits(_T_1441, 0, 0) @[dec_tlu_ctl.scala 2323:84] - node _T_1443 = not(_T_1442) @[dec_tlu_ctl.scala 2323:73] - node _T_1444 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2323:107] - node _T_1445 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2323:118] - node _T_1446 = and(_T_1444, _T_1445) @[dec_tlu_ctl.scala 2323:113] - node _T_1447 = orr(_T_1446) @[dec_tlu_ctl.scala 2323:125] - node _T_1448 = and(_T_1443, _T_1447) @[dec_tlu_ctl.scala 2323:98] - node _T_1449 = eq(mhpme_vec[1], UInt<6>("h036")) @[dec_tlu_ctl.scala 2324:34] - node _T_1450 = bits(_T_1449, 0, 0) @[dec_tlu_ctl.scala 2324:62] - node _T_1451 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2324:91] - node _T_1452 = eq(mhpme_vec[1], UInt<6>("h037")) @[dec_tlu_ctl.scala 2325:34] - node _T_1453 = bits(_T_1452, 0, 0) @[dec_tlu_ctl.scala 2325:62] - node _T_1454 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2325:94] - node _T_1455 = eq(mhpme_vec[1], UInt<6>("h038")) @[dec_tlu_ctl.scala 2326:34] - node _T_1456 = bits(_T_1455, 0, 0) @[dec_tlu_ctl.scala 2326:62] - node _T_1457 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2326:94] - node _T_1458 = eq(mhpme_vec[1], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2328:34] - node _T_1459 = bits(_T_1458, 0, 0) @[dec_tlu_ctl.scala 2328:62] - node _T_1460 = eq(mhpme_vec[1], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2329:34] - node _T_1461 = bits(_T_1460, 0, 0) @[dec_tlu_ctl.scala 2329:62] - node _T_1462 = eq(mhpme_vec[1], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2330:34] - node _T_1463 = bits(_T_1462, 0, 0) @[dec_tlu_ctl.scala 2330:62] - node _T_1464 = eq(mhpme_vec[1], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2331:34] - node _T_1465 = bits(_T_1464, 0, 0) @[dec_tlu_ctl.scala 2331:62] - node _T_1466 = eq(mhpme_vec[1], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2332:34] - node _T_1467 = bits(_T_1466, 0, 0) @[dec_tlu_ctl.scala 2332:62] - node _T_1468 = mux(_T_1302, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1469 = mux(_T_1304, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1470 = mux(_T_1306, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1471 = mux(_T_1308, _T_1310, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1472 = mux(_T_1312, _T_1316, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1473 = mux(_T_1318, _T_1321, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1474 = mux(_T_1323, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1475 = mux(_T_1325, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1476 = mux(_T_1327, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1477 = mux(_T_1329, _T_1330, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1478 = mux(_T_1332, _T_1333, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1479 = mux(_T_1335, _T_1336, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1480 = mux(_T_1338, _T_1339, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1481 = mux(_T_1341, _T_1343, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1482 = mux(_T_1345, _T_1348, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1483 = mux(_T_1350, _T_1351, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1484 = mux(_T_1353, _T_1354, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1485 = mux(_T_1356, _T_1357, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1486 = mux(_T_1359, _T_1360, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1487 = mux(_T_1362, _T_1363, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1488 = mux(_T_1365, _T_1366, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1489 = mux(_T_1368, _T_1369, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1490 = mux(_T_1371, _T_1372, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1491 = mux(_T_1374, _T_1375, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1492 = mux(_T_1377, _T_1380, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1493 = mux(_T_1382, _T_1383, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1494 = mux(_T_1385, _T_1386, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1495 = mux(_T_1388, _T_1389, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1496 = mux(_T_1391, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1497 = mux(_T_1393, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1498 = mux(_T_1395, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1499 = mux(_T_1397, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1500 = mux(_T_1399, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1501 = mux(_T_1401, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1502 = mux(_T_1403, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1503 = mux(_T_1405, _T_1407, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1504 = mux(_T_1409, _T_1411, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1505 = mux(_T_1413, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1506 = mux(_T_1415, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1507 = mux(_T_1417, _T_1419, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1508 = mux(_T_1421, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1509 = mux(_T_1423, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1510 = mux(_T_1425, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1511 = mux(_T_1427, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1512 = mux(_T_1429, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1513 = mux(_T_1431, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1514 = mux(_T_1433, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1515 = mux(_T_1435, _T_1438, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1516 = mux(_T_1440, _T_1448, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1517 = mux(_T_1450, _T_1451, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1518 = mux(_T_1453, _T_1454, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1519 = mux(_T_1456, _T_1457, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1520 = mux(_T_1459, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1521 = mux(_T_1461, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1522 = mux(_T_1463, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1523 = mux(_T_1465, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1524 = mux(_T_1467, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1525 = or(_T_1468, _T_1469) @[Mux.scala 27:72] - node _T_1526 = or(_T_1525, _T_1470) @[Mux.scala 27:72] - node _T_1527 = or(_T_1526, _T_1471) @[Mux.scala 27:72] - node _T_1528 = or(_T_1527, _T_1472) @[Mux.scala 27:72] - node _T_1529 = or(_T_1528, _T_1473) @[Mux.scala 27:72] - node _T_1530 = or(_T_1529, _T_1474) @[Mux.scala 27:72] - node _T_1531 = or(_T_1530, _T_1475) @[Mux.scala 27:72] - node _T_1532 = or(_T_1531, _T_1476) @[Mux.scala 27:72] - node _T_1533 = or(_T_1532, _T_1477) @[Mux.scala 27:72] - node _T_1534 = or(_T_1533, _T_1478) @[Mux.scala 27:72] - node _T_1535 = or(_T_1534, _T_1479) @[Mux.scala 27:72] + node _T_1297 = or(_T_1296, _T_1241) @[Mux.scala 27:72] + node _T_1298 = or(_T_1297, _T_1242) @[Mux.scala 27:72] + node _T_1299 = or(_T_1298, _T_1243) @[Mux.scala 27:72] + node _T_1300 = or(_T_1299, _T_1244) @[Mux.scala 27:72] + node _T_1301 = or(_T_1300, _T_1245) @[Mux.scala 27:72] + node _T_1302 = or(_T_1301, _T_1246) @[Mux.scala 27:72] + node _T_1303 = or(_T_1302, _T_1247) @[Mux.scala 27:72] + node _T_1304 = or(_T_1303, _T_1248) @[Mux.scala 27:72] + node _T_1305 = or(_T_1304, _T_1249) @[Mux.scala 27:72] + node _T_1306 = or(_T_1305, _T_1250) @[Mux.scala 27:72] + wire _T_1307 : UInt<1> @[Mux.scala 27:72] + _T_1307 <= _T_1306 @[Mux.scala 27:72] + node _T_1308 = and(_T_1026, _T_1307) @[dec_tlu_ctl.scala 2272:44] + mhpmc_inc_r[0] <= _T_1308 @[dec_tlu_ctl.scala 2272:19] + node _T_1309 = bits(mcountinhibit, 4, 4) @[dec_tlu_ctl.scala 2272:38] + node _T_1310 = not(_T_1309) @[dec_tlu_ctl.scala 2272:24] + node _T_1311 = eq(mhpme_vec[1], UInt<1>("h01")) @[dec_tlu_ctl.scala 2273:34] + node _T_1312 = bits(_T_1311, 0, 0) @[dec_tlu_ctl.scala 2273:62] + node _T_1313 = eq(mhpme_vec[1], UInt<2>("h02")) @[dec_tlu_ctl.scala 2274:34] + node _T_1314 = bits(_T_1313, 0, 0) @[dec_tlu_ctl.scala 2274:62] + node _T_1315 = eq(mhpme_vec[1], UInt<2>("h03")) @[dec_tlu_ctl.scala 2275:34] + node _T_1316 = bits(_T_1315, 0, 0) @[dec_tlu_ctl.scala 2275:62] + node _T_1317 = eq(mhpme_vec[1], UInt<3>("h04")) @[dec_tlu_ctl.scala 2276:34] + node _T_1318 = bits(_T_1317, 0, 0) @[dec_tlu_ctl.scala 2276:62] + node _T_1319 = not(io.illegal_r) @[dec_tlu_ctl.scala 2276:96] + node _T_1320 = and(io.tlu_i0_commit_cmt, _T_1319) @[dec_tlu_ctl.scala 2276:94] + node _T_1321 = eq(mhpme_vec[1], UInt<3>("h05")) @[dec_tlu_ctl.scala 2277:34] + node _T_1322 = bits(_T_1321, 0, 0) @[dec_tlu_ctl.scala 2277:62] + node _T_1323 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2277:96] + node _T_1324 = and(io.tlu_i0_commit_cmt, _T_1323) @[dec_tlu_ctl.scala 2277:94] + node _T_1325 = not(io.illegal_r) @[dec_tlu_ctl.scala 2277:117] + node _T_1326 = and(_T_1324, _T_1325) @[dec_tlu_ctl.scala 2277:115] + node _T_1327 = eq(mhpme_vec[1], UInt<3>("h06")) @[dec_tlu_ctl.scala 2278:34] + node _T_1328 = bits(_T_1327, 0, 0) @[dec_tlu_ctl.scala 2278:62] + node _T_1329 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2278:94] + node _T_1330 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:117] + node _T_1331 = and(_T_1329, _T_1330) @[dec_tlu_ctl.scala 2278:115] + node _T_1332 = eq(mhpme_vec[1], UInt<3>("h07")) @[dec_tlu_ctl.scala 2279:34] + node _T_1333 = bits(_T_1332, 0, 0) @[dec_tlu_ctl.scala 2279:62] + node _T_1334 = eq(mhpme_vec[1], UInt<4>("h08")) @[dec_tlu_ctl.scala 2280:34] + node _T_1335 = bits(_T_1334, 0, 0) @[dec_tlu_ctl.scala 2280:62] + node _T_1336 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2281:34] + node _T_1337 = bits(_T_1336, 0, 0) @[dec_tlu_ctl.scala 2281:62] + node _T_1338 = eq(mhpme_vec[1], UInt<4>("h09")) @[dec_tlu_ctl.scala 2282:34] + node _T_1339 = bits(_T_1338, 0, 0) @[dec_tlu_ctl.scala 2282:62] + node _T_1340 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2282:91] + node _T_1341 = eq(mhpme_vec[1], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2283:34] + node _T_1342 = bits(_T_1341, 0, 0) @[dec_tlu_ctl.scala 2283:62] + node _T_1343 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2283:105] + node _T_1344 = eq(mhpme_vec[1], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2284:34] + node _T_1345 = bits(_T_1344, 0, 0) @[dec_tlu_ctl.scala 2284:62] + node _T_1346 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2284:91] + node _T_1347 = eq(mhpme_vec[1], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2285:34] + node _T_1348 = bits(_T_1347, 0, 0) @[dec_tlu_ctl.scala 2285:62] + node _T_1349 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2285:91] + node _T_1350 = eq(mhpme_vec[1], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2286:34] + node _T_1351 = bits(_T_1350, 0, 0) @[dec_tlu_ctl.scala 2286:62] + node _T_1352 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2286:91] + node _T_1353 = and(_T_1352, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2286:100] + node _T_1354 = eq(mhpme_vec[1], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2287:34] + node _T_1355 = bits(_T_1354, 0, 0) @[dec_tlu_ctl.scala 2287:62] + node _T_1356 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2287:91] + node _T_1357 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2287:142] + node _T_1358 = and(_T_1356, _T_1357) @[dec_tlu_ctl.scala 2287:101] + node _T_1359 = eq(mhpme_vec[1], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2288:34] + node _T_1360 = bits(_T_1359, 0, 0) @[dec_tlu_ctl.scala 2288:59] + node _T_1361 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2288:89] + node _T_1362 = eq(mhpme_vec[1], UInt<5>("h010")) @[dec_tlu_ctl.scala 2289:34] + node _T_1363 = bits(_T_1362, 0, 0) @[dec_tlu_ctl.scala 2289:59] + node _T_1364 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2289:89] + node _T_1365 = eq(mhpme_vec[1], UInt<5>("h012")) @[dec_tlu_ctl.scala 2290:34] + node _T_1366 = bits(_T_1365, 0, 0) @[dec_tlu_ctl.scala 2290:59] + node _T_1367 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2290:89] + node _T_1368 = eq(mhpme_vec[1], UInt<5>("h011")) @[dec_tlu_ctl.scala 2291:34] + node _T_1369 = bits(_T_1368, 0, 0) @[dec_tlu_ctl.scala 2291:59] + node _T_1370 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2291:89] + node _T_1371 = eq(mhpme_vec[1], UInt<5>("h013")) @[dec_tlu_ctl.scala 2292:34] + node _T_1372 = bits(_T_1371, 0, 0) @[dec_tlu_ctl.scala 2292:59] + node _T_1373 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2292:89] + node _T_1374 = eq(mhpme_vec[1], UInt<5>("h014")) @[dec_tlu_ctl.scala 2293:34] + node _T_1375 = bits(_T_1374, 0, 0) @[dec_tlu_ctl.scala 2293:59] + node _T_1376 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2293:89] + node _T_1377 = eq(mhpme_vec[1], UInt<5>("h015")) @[dec_tlu_ctl.scala 2294:34] + node _T_1378 = bits(_T_1377, 0, 0) @[dec_tlu_ctl.scala 2294:59] + node _T_1379 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2294:89] + node _T_1380 = eq(mhpme_vec[1], UInt<5>("h016")) @[dec_tlu_ctl.scala 2295:34] + node _T_1381 = bits(_T_1380, 0, 0) @[dec_tlu_ctl.scala 2295:59] + node _T_1382 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2295:89] + node _T_1383 = eq(mhpme_vec[1], UInt<5>("h017")) @[dec_tlu_ctl.scala 2296:34] + node _T_1384 = bits(_T_1383, 0, 0) @[dec_tlu_ctl.scala 2296:59] + node _T_1385 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2296:89] + node _T_1386 = eq(mhpme_vec[1], UInt<5>("h018")) @[dec_tlu_ctl.scala 2297:34] + node _T_1387 = bits(_T_1386, 0, 0) @[dec_tlu_ctl.scala 2297:59] + node _T_1388 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2297:89] + node _T_1389 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2297:122] + node _T_1390 = or(_T_1388, _T_1389) @[dec_tlu_ctl.scala 2297:101] + node _T_1391 = eq(mhpme_vec[1], UInt<5>("h019")) @[dec_tlu_ctl.scala 2298:34] + node _T_1392 = bits(_T_1391, 0, 0) @[dec_tlu_ctl.scala 2298:62] + node _T_1393 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2298:95] + node _T_1394 = eq(mhpme_vec[1], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2299:34] + node _T_1395 = bits(_T_1394, 0, 0) @[dec_tlu_ctl.scala 2299:62] + node _T_1396 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2299:97] + node _T_1397 = eq(mhpme_vec[1], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2300:34] + node _T_1398 = bits(_T_1397, 0, 0) @[dec_tlu_ctl.scala 2300:62] + node _T_1399 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:110] + node _T_1400 = eq(mhpme_vec[1], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2301:34] + node _T_1401 = bits(_T_1400, 0, 0) @[dec_tlu_ctl.scala 2301:62] + node _T_1402 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2302:34] + node _T_1403 = bits(_T_1402, 0, 0) @[dec_tlu_ctl.scala 2302:62] + node _T_1404 = eq(mhpme_vec[1], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2303:34] + node _T_1405 = bits(_T_1404, 0, 0) @[dec_tlu_ctl.scala 2303:62] + node _T_1406 = eq(mhpme_vec[1], UInt<6>("h020")) @[dec_tlu_ctl.scala 2304:34] + node _T_1407 = bits(_T_1406, 0, 0) @[dec_tlu_ctl.scala 2304:62] + node _T_1408 = eq(mhpme_vec[1], UInt<6>("h022")) @[dec_tlu_ctl.scala 2305:34] + node _T_1409 = bits(_T_1408, 0, 0) @[dec_tlu_ctl.scala 2305:62] + node _T_1410 = eq(mhpme_vec[1], UInt<6>("h023")) @[dec_tlu_ctl.scala 2306:34] + node _T_1411 = bits(_T_1410, 0, 0) @[dec_tlu_ctl.scala 2306:62] + node _T_1412 = eq(mhpme_vec[1], UInt<6>("h024")) @[dec_tlu_ctl.scala 2307:34] + node _T_1413 = bits(_T_1412, 0, 0) @[dec_tlu_ctl.scala 2307:62] + node _T_1414 = eq(mhpme_vec[1], UInt<6>("h025")) @[dec_tlu_ctl.scala 2308:34] + node _T_1415 = bits(_T_1414, 0, 0) @[dec_tlu_ctl.scala 2308:62] + node _T_1416 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2308:98] + node _T_1417 = or(_T_1416, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2308:120] + node _T_1418 = eq(mhpme_vec[1], UInt<6>("h026")) @[dec_tlu_ctl.scala 2309:34] + node _T_1419 = bits(_T_1418, 0, 0) @[dec_tlu_ctl.scala 2309:62] + node _T_1420 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2309:92] + node _T_1421 = or(_T_1420, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2309:117] + node _T_1422 = eq(mhpme_vec[1], UInt<6>("h027")) @[dec_tlu_ctl.scala 2310:34] + node _T_1423 = bits(_T_1422, 0, 0) @[dec_tlu_ctl.scala 2310:62] + node _T_1424 = eq(mhpme_vec[1], UInt<6>("h028")) @[dec_tlu_ctl.scala 2311:34] + node _T_1425 = bits(_T_1424, 0, 0) @[dec_tlu_ctl.scala 2311:62] + node _T_1426 = eq(mhpme_vec[1], UInt<6>("h029")) @[dec_tlu_ctl.scala 2312:34] + node _T_1427 = bits(_T_1426, 0, 0) @[dec_tlu_ctl.scala 2312:62] + node _T_1428 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2312:97] + node _T_1429 = and(_T_1428, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2312:129] + node _T_1430 = eq(mhpme_vec[1], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2313:34] + node _T_1431 = bits(_T_1430, 0, 0) @[dec_tlu_ctl.scala 2313:62] + node _T_1432 = eq(mhpme_vec[1], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2314:34] + node _T_1433 = bits(_T_1432, 0, 0) @[dec_tlu_ctl.scala 2314:62] + node _T_1434 = eq(mhpme_vec[1], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2315:34] + node _T_1435 = bits(_T_1434, 0, 0) @[dec_tlu_ctl.scala 2315:62] + node _T_1436 = eq(mhpme_vec[1], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2316:34] + node _T_1437 = bits(_T_1436, 0, 0) @[dec_tlu_ctl.scala 2316:62] + node _T_1438 = eq(mhpme_vec[1], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2317:34] + node _T_1439 = bits(_T_1438, 0, 0) @[dec_tlu_ctl.scala 2317:62] + node _T_1440 = eq(mhpme_vec[1], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2318:34] + node _T_1441 = bits(_T_1440, 0, 0) @[dec_tlu_ctl.scala 2318:62] + node _T_1442 = eq(mhpme_vec[1], UInt<6>("h030")) @[dec_tlu_ctl.scala 2319:34] + node _T_1443 = bits(_T_1442, 0, 0) @[dec_tlu_ctl.scala 2319:62] + node _T_1444 = eq(mhpme_vec[1], UInt<6>("h031")) @[dec_tlu_ctl.scala 2320:34] + node _T_1445 = bits(_T_1444, 0, 0) @[dec_tlu_ctl.scala 2320:62] + node _T_1446 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2320:84] + node _T_1447 = bits(_T_1446, 0, 0) @[dec_tlu_ctl.scala 2320:84] + node _T_1448 = not(_T_1447) @[dec_tlu_ctl.scala 2320:73] + node _T_1449 = eq(mhpme_vec[1], UInt<6>("h032")) @[dec_tlu_ctl.scala 2321:34] + node _T_1450 = bits(_T_1449, 0, 0) @[dec_tlu_ctl.scala 2321:62] + node _T_1451 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2321:84] + node _T_1452 = bits(_T_1451, 0, 0) @[dec_tlu_ctl.scala 2321:84] + node _T_1453 = not(_T_1452) @[dec_tlu_ctl.scala 2321:73] + node _T_1454 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2321:107] + node _T_1455 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2321:118] + node _T_1456 = and(_T_1454, _T_1455) @[dec_tlu_ctl.scala 2321:113] + node _T_1457 = orr(_T_1456) @[dec_tlu_ctl.scala 2321:125] + node _T_1458 = and(_T_1453, _T_1457) @[dec_tlu_ctl.scala 2321:98] + node _T_1459 = eq(mhpme_vec[1], UInt<6>("h036")) @[dec_tlu_ctl.scala 2322:34] + node _T_1460 = bits(_T_1459, 0, 0) @[dec_tlu_ctl.scala 2322:62] + node _T_1461 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2322:91] + node _T_1462 = eq(mhpme_vec[1], UInt<6>("h037")) @[dec_tlu_ctl.scala 2323:34] + node _T_1463 = bits(_T_1462, 0, 0) @[dec_tlu_ctl.scala 2323:62] + node _T_1464 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2323:94] + node _T_1465 = eq(mhpme_vec[1], UInt<6>("h038")) @[dec_tlu_ctl.scala 2324:34] + node _T_1466 = bits(_T_1465, 0, 0) @[dec_tlu_ctl.scala 2324:62] + node _T_1467 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2324:94] + node _T_1468 = eq(mhpme_vec[1], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2326:34] + node _T_1469 = bits(_T_1468, 0, 0) @[dec_tlu_ctl.scala 2326:62] + node _T_1470 = eq(mhpme_vec[1], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2327:34] + node _T_1471 = bits(_T_1470, 0, 0) @[dec_tlu_ctl.scala 2327:62] + node _T_1472 = eq(mhpme_vec[1], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2328:34] + node _T_1473 = bits(_T_1472, 0, 0) @[dec_tlu_ctl.scala 2328:62] + node _T_1474 = eq(mhpme_vec[1], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2329:34] + node _T_1475 = bits(_T_1474, 0, 0) @[dec_tlu_ctl.scala 2329:62] + node _T_1476 = eq(mhpme_vec[1], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2330:34] + node _T_1477 = bits(_T_1476, 0, 0) @[dec_tlu_ctl.scala 2330:62] + node _T_1478 = mux(_T_1312, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1479 = mux(_T_1314, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1480 = mux(_T_1316, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1481 = mux(_T_1318, _T_1320, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1482 = mux(_T_1322, _T_1326, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1483 = mux(_T_1328, _T_1331, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1484 = mux(_T_1333, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1485 = mux(_T_1335, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1486 = mux(_T_1337, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1487 = mux(_T_1339, _T_1340, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1488 = mux(_T_1342, _T_1343, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1489 = mux(_T_1345, _T_1346, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1490 = mux(_T_1348, _T_1349, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1491 = mux(_T_1351, _T_1353, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1492 = mux(_T_1355, _T_1358, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1493 = mux(_T_1360, _T_1361, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1494 = mux(_T_1363, _T_1364, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1495 = mux(_T_1366, _T_1367, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1496 = mux(_T_1369, _T_1370, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1497 = mux(_T_1372, _T_1373, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1498 = mux(_T_1375, _T_1376, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1499 = mux(_T_1378, _T_1379, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1500 = mux(_T_1381, _T_1382, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1501 = mux(_T_1384, _T_1385, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1502 = mux(_T_1387, _T_1390, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1503 = mux(_T_1392, _T_1393, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1504 = mux(_T_1395, _T_1396, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1505 = mux(_T_1398, _T_1399, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1506 = mux(_T_1401, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1507 = mux(_T_1403, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1508 = mux(_T_1405, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1509 = mux(_T_1407, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1510 = mux(_T_1409, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1511 = mux(_T_1411, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1512 = mux(_T_1413, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1513 = mux(_T_1415, _T_1417, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1514 = mux(_T_1419, _T_1421, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1515 = mux(_T_1423, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1516 = mux(_T_1425, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1517 = mux(_T_1427, _T_1429, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1518 = mux(_T_1431, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1519 = mux(_T_1433, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1520 = mux(_T_1435, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1521 = mux(_T_1437, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1522 = mux(_T_1439, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1523 = mux(_T_1441, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1524 = mux(_T_1443, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1525 = mux(_T_1445, _T_1448, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1526 = mux(_T_1450, _T_1458, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1527 = mux(_T_1460, _T_1461, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1528 = mux(_T_1463, _T_1464, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1529 = mux(_T_1466, _T_1467, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1530 = mux(_T_1469, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1531 = mux(_T_1471, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1532 = mux(_T_1473, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1533 = mux(_T_1475, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1534 = mux(_T_1477, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1535 = or(_T_1478, _T_1479) @[Mux.scala 27:72] node _T_1536 = or(_T_1535, _T_1480) @[Mux.scala 27:72] node _T_1537 = or(_T_1536, _T_1481) @[Mux.scala 27:72] node _T_1538 = or(_T_1537, _T_1482) @[Mux.scala 27:72] @@ -74972,247 +74972,247 @@ circuit quasar_wrapper : node _T_1578 = or(_T_1577, _T_1522) @[Mux.scala 27:72] node _T_1579 = or(_T_1578, _T_1523) @[Mux.scala 27:72] node _T_1580 = or(_T_1579, _T_1524) @[Mux.scala 27:72] - wire _T_1581 : UInt<1> @[Mux.scala 27:72] - _T_1581 <= _T_1580 @[Mux.scala 27:72] - node _T_1582 = and(_T_1300, _T_1581) @[dec_tlu_ctl.scala 2274:44] - mhpmc_inc_r[1] <= _T_1582 @[dec_tlu_ctl.scala 2274:19] - node _T_1583 = bits(mcountinhibit, 5, 5) @[dec_tlu_ctl.scala 2274:38] - node _T_1584 = not(_T_1583) @[dec_tlu_ctl.scala 2274:24] - node _T_1585 = eq(mhpme_vec[2], UInt<1>("h01")) @[dec_tlu_ctl.scala 2275:34] - node _T_1586 = bits(_T_1585, 0, 0) @[dec_tlu_ctl.scala 2275:62] - node _T_1587 = eq(mhpme_vec[2], UInt<2>("h02")) @[dec_tlu_ctl.scala 2276:34] - node _T_1588 = bits(_T_1587, 0, 0) @[dec_tlu_ctl.scala 2276:62] - node _T_1589 = eq(mhpme_vec[2], UInt<2>("h03")) @[dec_tlu_ctl.scala 2277:34] - node _T_1590 = bits(_T_1589, 0, 0) @[dec_tlu_ctl.scala 2277:62] - node _T_1591 = eq(mhpme_vec[2], UInt<3>("h04")) @[dec_tlu_ctl.scala 2278:34] - node _T_1592 = bits(_T_1591, 0, 0) @[dec_tlu_ctl.scala 2278:62] - node _T_1593 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:96] - node _T_1594 = and(io.tlu_i0_commit_cmt, _T_1593) @[dec_tlu_ctl.scala 2278:94] - node _T_1595 = eq(mhpme_vec[2], UInt<3>("h05")) @[dec_tlu_ctl.scala 2279:34] - node _T_1596 = bits(_T_1595, 0, 0) @[dec_tlu_ctl.scala 2279:62] - node _T_1597 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:96] - node _T_1598 = and(io.tlu_i0_commit_cmt, _T_1597) @[dec_tlu_ctl.scala 2279:94] - node _T_1599 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] - node _T_1600 = and(_T_1598, _T_1599) @[dec_tlu_ctl.scala 2279:115] - node _T_1601 = eq(mhpme_vec[2], UInt<3>("h06")) @[dec_tlu_ctl.scala 2280:34] - node _T_1602 = bits(_T_1601, 0, 0) @[dec_tlu_ctl.scala 2280:62] - node _T_1603 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2280:94] - node _T_1604 = not(io.illegal_r) @[dec_tlu_ctl.scala 2280:117] - node _T_1605 = and(_T_1603, _T_1604) @[dec_tlu_ctl.scala 2280:115] - node _T_1606 = eq(mhpme_vec[2], UInt<3>("h07")) @[dec_tlu_ctl.scala 2281:34] - node _T_1607 = bits(_T_1606, 0, 0) @[dec_tlu_ctl.scala 2281:62] - node _T_1608 = eq(mhpme_vec[2], UInt<4>("h08")) @[dec_tlu_ctl.scala 2282:34] - node _T_1609 = bits(_T_1608, 0, 0) @[dec_tlu_ctl.scala 2282:62] - node _T_1610 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2283:34] - node _T_1611 = bits(_T_1610, 0, 0) @[dec_tlu_ctl.scala 2283:62] - node _T_1612 = eq(mhpme_vec[2], UInt<4>("h09")) @[dec_tlu_ctl.scala 2284:34] - node _T_1613 = bits(_T_1612, 0, 0) @[dec_tlu_ctl.scala 2284:62] - node _T_1614 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2284:91] - node _T_1615 = eq(mhpme_vec[2], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2285:34] - node _T_1616 = bits(_T_1615, 0, 0) @[dec_tlu_ctl.scala 2285:62] - node _T_1617 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2285:105] - node _T_1618 = eq(mhpme_vec[2], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2286:34] - node _T_1619 = bits(_T_1618, 0, 0) @[dec_tlu_ctl.scala 2286:62] - node _T_1620 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2286:91] - node _T_1621 = eq(mhpme_vec[2], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2287:34] - node _T_1622 = bits(_T_1621, 0, 0) @[dec_tlu_ctl.scala 2287:62] - node _T_1623 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2287:91] - node _T_1624 = eq(mhpme_vec[2], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2288:34] - node _T_1625 = bits(_T_1624, 0, 0) @[dec_tlu_ctl.scala 2288:62] - node _T_1626 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2288:91] - node _T_1627 = and(_T_1626, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2288:100] - node _T_1628 = eq(mhpme_vec[2], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2289:34] - node _T_1629 = bits(_T_1628, 0, 0) @[dec_tlu_ctl.scala 2289:62] - node _T_1630 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2289:91] - node _T_1631 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2289:142] - node _T_1632 = and(_T_1630, _T_1631) @[dec_tlu_ctl.scala 2289:101] - node _T_1633 = eq(mhpme_vec[2], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2290:34] - node _T_1634 = bits(_T_1633, 0, 0) @[dec_tlu_ctl.scala 2290:59] - node _T_1635 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2290:89] - node _T_1636 = eq(mhpme_vec[2], UInt<5>("h010")) @[dec_tlu_ctl.scala 2291:34] - node _T_1637 = bits(_T_1636, 0, 0) @[dec_tlu_ctl.scala 2291:59] - node _T_1638 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2291:89] - node _T_1639 = eq(mhpme_vec[2], UInt<5>("h012")) @[dec_tlu_ctl.scala 2292:34] - node _T_1640 = bits(_T_1639, 0, 0) @[dec_tlu_ctl.scala 2292:59] - node _T_1641 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2292:89] - node _T_1642 = eq(mhpme_vec[2], UInt<5>("h011")) @[dec_tlu_ctl.scala 2293:34] - node _T_1643 = bits(_T_1642, 0, 0) @[dec_tlu_ctl.scala 2293:59] - node _T_1644 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2293:89] - node _T_1645 = eq(mhpme_vec[2], UInt<5>("h013")) @[dec_tlu_ctl.scala 2294:34] - node _T_1646 = bits(_T_1645, 0, 0) @[dec_tlu_ctl.scala 2294:59] - node _T_1647 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2294:89] - node _T_1648 = eq(mhpme_vec[2], UInt<5>("h014")) @[dec_tlu_ctl.scala 2295:34] - node _T_1649 = bits(_T_1648, 0, 0) @[dec_tlu_ctl.scala 2295:59] - node _T_1650 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2295:89] - node _T_1651 = eq(mhpme_vec[2], UInt<5>("h015")) @[dec_tlu_ctl.scala 2296:34] - node _T_1652 = bits(_T_1651, 0, 0) @[dec_tlu_ctl.scala 2296:59] - node _T_1653 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2296:89] - node _T_1654 = eq(mhpme_vec[2], UInt<5>("h016")) @[dec_tlu_ctl.scala 2297:34] - node _T_1655 = bits(_T_1654, 0, 0) @[dec_tlu_ctl.scala 2297:59] - node _T_1656 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2297:89] - node _T_1657 = eq(mhpme_vec[2], UInt<5>("h017")) @[dec_tlu_ctl.scala 2298:34] - node _T_1658 = bits(_T_1657, 0, 0) @[dec_tlu_ctl.scala 2298:59] - node _T_1659 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2298:89] - node _T_1660 = eq(mhpme_vec[2], UInt<5>("h018")) @[dec_tlu_ctl.scala 2299:34] - node _T_1661 = bits(_T_1660, 0, 0) @[dec_tlu_ctl.scala 2299:59] - node _T_1662 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2299:89] - node _T_1663 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2299:122] - node _T_1664 = or(_T_1662, _T_1663) @[dec_tlu_ctl.scala 2299:101] - node _T_1665 = eq(mhpme_vec[2], UInt<5>("h019")) @[dec_tlu_ctl.scala 2300:34] - node _T_1666 = bits(_T_1665, 0, 0) @[dec_tlu_ctl.scala 2300:62] - node _T_1667 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:95] - node _T_1668 = eq(mhpme_vec[2], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2301:34] - node _T_1669 = bits(_T_1668, 0, 0) @[dec_tlu_ctl.scala 2301:62] - node _T_1670 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:97] - node _T_1671 = eq(mhpme_vec[2], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2302:34] - node _T_1672 = bits(_T_1671, 0, 0) @[dec_tlu_ctl.scala 2302:62] - node _T_1673 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2302:110] - node _T_1674 = eq(mhpme_vec[2], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2303:34] - node _T_1675 = bits(_T_1674, 0, 0) @[dec_tlu_ctl.scala 2303:62] - node _T_1676 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2304:34] - node _T_1677 = bits(_T_1676, 0, 0) @[dec_tlu_ctl.scala 2304:62] - node _T_1678 = eq(mhpme_vec[2], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2305:34] - node _T_1679 = bits(_T_1678, 0, 0) @[dec_tlu_ctl.scala 2305:62] - node _T_1680 = eq(mhpme_vec[2], UInt<6>("h020")) @[dec_tlu_ctl.scala 2306:34] - node _T_1681 = bits(_T_1680, 0, 0) @[dec_tlu_ctl.scala 2306:62] - node _T_1682 = eq(mhpme_vec[2], UInt<6>("h022")) @[dec_tlu_ctl.scala 2307:34] - node _T_1683 = bits(_T_1682, 0, 0) @[dec_tlu_ctl.scala 2307:62] - node _T_1684 = eq(mhpme_vec[2], UInt<6>("h023")) @[dec_tlu_ctl.scala 2308:34] - node _T_1685 = bits(_T_1684, 0, 0) @[dec_tlu_ctl.scala 2308:62] - node _T_1686 = eq(mhpme_vec[2], UInt<6>("h024")) @[dec_tlu_ctl.scala 2309:34] - node _T_1687 = bits(_T_1686, 0, 0) @[dec_tlu_ctl.scala 2309:62] - node _T_1688 = eq(mhpme_vec[2], UInt<6>("h025")) @[dec_tlu_ctl.scala 2310:34] - node _T_1689 = bits(_T_1688, 0, 0) @[dec_tlu_ctl.scala 2310:62] - node _T_1690 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2310:98] - node _T_1691 = or(_T_1690, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2310:120] - node _T_1692 = eq(mhpme_vec[2], UInt<6>("h026")) @[dec_tlu_ctl.scala 2311:34] - node _T_1693 = bits(_T_1692, 0, 0) @[dec_tlu_ctl.scala 2311:62] - node _T_1694 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2311:92] - node _T_1695 = or(_T_1694, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2311:117] - node _T_1696 = eq(mhpme_vec[2], UInt<6>("h027")) @[dec_tlu_ctl.scala 2312:34] - node _T_1697 = bits(_T_1696, 0, 0) @[dec_tlu_ctl.scala 2312:62] - node _T_1698 = eq(mhpme_vec[2], UInt<6>("h028")) @[dec_tlu_ctl.scala 2313:34] - node _T_1699 = bits(_T_1698, 0, 0) @[dec_tlu_ctl.scala 2313:62] - node _T_1700 = eq(mhpme_vec[2], UInt<6>("h029")) @[dec_tlu_ctl.scala 2314:34] - node _T_1701 = bits(_T_1700, 0, 0) @[dec_tlu_ctl.scala 2314:62] - node _T_1702 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2314:97] - node _T_1703 = and(_T_1702, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2314:129] - node _T_1704 = eq(mhpme_vec[2], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2315:34] - node _T_1705 = bits(_T_1704, 0, 0) @[dec_tlu_ctl.scala 2315:62] - node _T_1706 = eq(mhpme_vec[2], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2316:34] - node _T_1707 = bits(_T_1706, 0, 0) @[dec_tlu_ctl.scala 2316:62] - node _T_1708 = eq(mhpme_vec[2], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2317:34] - node _T_1709 = bits(_T_1708, 0, 0) @[dec_tlu_ctl.scala 2317:62] - node _T_1710 = eq(mhpme_vec[2], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2318:34] - node _T_1711 = bits(_T_1710, 0, 0) @[dec_tlu_ctl.scala 2318:62] - node _T_1712 = eq(mhpme_vec[2], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2319:34] - node _T_1713 = bits(_T_1712, 0, 0) @[dec_tlu_ctl.scala 2319:62] - node _T_1714 = eq(mhpme_vec[2], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2320:34] - node _T_1715 = bits(_T_1714, 0, 0) @[dec_tlu_ctl.scala 2320:62] - node _T_1716 = eq(mhpme_vec[2], UInt<6>("h030")) @[dec_tlu_ctl.scala 2321:34] - node _T_1717 = bits(_T_1716, 0, 0) @[dec_tlu_ctl.scala 2321:62] - node _T_1718 = eq(mhpme_vec[2], UInt<6>("h031")) @[dec_tlu_ctl.scala 2322:34] - node _T_1719 = bits(_T_1718, 0, 0) @[dec_tlu_ctl.scala 2322:62] - node _T_1720 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] - node _T_1721 = bits(_T_1720, 0, 0) @[dec_tlu_ctl.scala 2322:84] - node _T_1722 = not(_T_1721) @[dec_tlu_ctl.scala 2322:73] - node _T_1723 = eq(mhpme_vec[2], UInt<6>("h032")) @[dec_tlu_ctl.scala 2323:34] - node _T_1724 = bits(_T_1723, 0, 0) @[dec_tlu_ctl.scala 2323:62] - node _T_1725 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2323:84] - node _T_1726 = bits(_T_1725, 0, 0) @[dec_tlu_ctl.scala 2323:84] - node _T_1727 = not(_T_1726) @[dec_tlu_ctl.scala 2323:73] - node _T_1728 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2323:107] - node _T_1729 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2323:118] - node _T_1730 = and(_T_1728, _T_1729) @[dec_tlu_ctl.scala 2323:113] - node _T_1731 = orr(_T_1730) @[dec_tlu_ctl.scala 2323:125] - node _T_1732 = and(_T_1727, _T_1731) @[dec_tlu_ctl.scala 2323:98] - node _T_1733 = eq(mhpme_vec[2], UInt<6>("h036")) @[dec_tlu_ctl.scala 2324:34] - node _T_1734 = bits(_T_1733, 0, 0) @[dec_tlu_ctl.scala 2324:62] - node _T_1735 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2324:91] - node _T_1736 = eq(mhpme_vec[2], UInt<6>("h037")) @[dec_tlu_ctl.scala 2325:34] - node _T_1737 = bits(_T_1736, 0, 0) @[dec_tlu_ctl.scala 2325:62] - node _T_1738 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2325:94] - node _T_1739 = eq(mhpme_vec[2], UInt<6>("h038")) @[dec_tlu_ctl.scala 2326:34] - node _T_1740 = bits(_T_1739, 0, 0) @[dec_tlu_ctl.scala 2326:62] - node _T_1741 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2326:94] - node _T_1742 = eq(mhpme_vec[2], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2328:34] - node _T_1743 = bits(_T_1742, 0, 0) @[dec_tlu_ctl.scala 2328:62] - node _T_1744 = eq(mhpme_vec[2], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2329:34] - node _T_1745 = bits(_T_1744, 0, 0) @[dec_tlu_ctl.scala 2329:62] - node _T_1746 = eq(mhpme_vec[2], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2330:34] - node _T_1747 = bits(_T_1746, 0, 0) @[dec_tlu_ctl.scala 2330:62] - node _T_1748 = eq(mhpme_vec[2], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2331:34] - node _T_1749 = bits(_T_1748, 0, 0) @[dec_tlu_ctl.scala 2331:62] - node _T_1750 = eq(mhpme_vec[2], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2332:34] - node _T_1751 = bits(_T_1750, 0, 0) @[dec_tlu_ctl.scala 2332:62] - node _T_1752 = mux(_T_1586, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1753 = mux(_T_1588, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1754 = mux(_T_1590, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1755 = mux(_T_1592, _T_1594, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1756 = mux(_T_1596, _T_1600, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1757 = mux(_T_1602, _T_1605, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1758 = mux(_T_1607, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1759 = mux(_T_1609, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1760 = mux(_T_1611, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1761 = mux(_T_1613, _T_1614, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1762 = mux(_T_1616, _T_1617, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1763 = mux(_T_1619, _T_1620, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1764 = mux(_T_1622, _T_1623, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1765 = mux(_T_1625, _T_1627, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1766 = mux(_T_1629, _T_1632, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1767 = mux(_T_1634, _T_1635, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1768 = mux(_T_1637, _T_1638, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1769 = mux(_T_1640, _T_1641, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1770 = mux(_T_1643, _T_1644, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1771 = mux(_T_1646, _T_1647, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1772 = mux(_T_1649, _T_1650, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1773 = mux(_T_1652, _T_1653, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1774 = mux(_T_1655, _T_1656, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1775 = mux(_T_1658, _T_1659, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1776 = mux(_T_1661, _T_1664, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1777 = mux(_T_1666, _T_1667, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1778 = mux(_T_1669, _T_1670, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1779 = mux(_T_1672, _T_1673, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1780 = mux(_T_1675, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1781 = mux(_T_1677, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1782 = mux(_T_1679, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1783 = mux(_T_1681, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1784 = mux(_T_1683, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1785 = mux(_T_1685, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1786 = mux(_T_1687, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1787 = mux(_T_1689, _T_1691, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1788 = mux(_T_1693, _T_1695, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1789 = mux(_T_1697, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1790 = mux(_T_1699, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1791 = mux(_T_1701, _T_1703, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1792 = mux(_T_1705, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1793 = mux(_T_1707, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1794 = mux(_T_1709, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1795 = mux(_T_1711, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1796 = mux(_T_1713, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1797 = mux(_T_1715, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1798 = mux(_T_1717, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1799 = mux(_T_1719, _T_1722, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1800 = mux(_T_1724, _T_1732, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1801 = mux(_T_1734, _T_1735, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1802 = mux(_T_1737, _T_1738, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1803 = mux(_T_1740, _T_1741, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1804 = mux(_T_1743, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1805 = mux(_T_1745, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1806 = mux(_T_1747, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1807 = mux(_T_1749, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1808 = mux(_T_1751, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1809 = or(_T_1752, _T_1753) @[Mux.scala 27:72] - node _T_1810 = or(_T_1809, _T_1754) @[Mux.scala 27:72] - node _T_1811 = or(_T_1810, _T_1755) @[Mux.scala 27:72] - node _T_1812 = or(_T_1811, _T_1756) @[Mux.scala 27:72] - node _T_1813 = or(_T_1812, _T_1757) @[Mux.scala 27:72] - node _T_1814 = or(_T_1813, _T_1758) @[Mux.scala 27:72] - node _T_1815 = or(_T_1814, _T_1759) @[Mux.scala 27:72] - node _T_1816 = or(_T_1815, _T_1760) @[Mux.scala 27:72] - node _T_1817 = or(_T_1816, _T_1761) @[Mux.scala 27:72] - node _T_1818 = or(_T_1817, _T_1762) @[Mux.scala 27:72] - node _T_1819 = or(_T_1818, _T_1763) @[Mux.scala 27:72] + node _T_1581 = or(_T_1580, _T_1525) @[Mux.scala 27:72] + node _T_1582 = or(_T_1581, _T_1526) @[Mux.scala 27:72] + node _T_1583 = or(_T_1582, _T_1527) @[Mux.scala 27:72] + node _T_1584 = or(_T_1583, _T_1528) @[Mux.scala 27:72] + node _T_1585 = or(_T_1584, _T_1529) @[Mux.scala 27:72] + node _T_1586 = or(_T_1585, _T_1530) @[Mux.scala 27:72] + node _T_1587 = or(_T_1586, _T_1531) @[Mux.scala 27:72] + node _T_1588 = or(_T_1587, _T_1532) @[Mux.scala 27:72] + node _T_1589 = or(_T_1588, _T_1533) @[Mux.scala 27:72] + node _T_1590 = or(_T_1589, _T_1534) @[Mux.scala 27:72] + wire _T_1591 : UInt<1> @[Mux.scala 27:72] + _T_1591 <= _T_1590 @[Mux.scala 27:72] + node _T_1592 = and(_T_1310, _T_1591) @[dec_tlu_ctl.scala 2272:44] + mhpmc_inc_r[1] <= _T_1592 @[dec_tlu_ctl.scala 2272:19] + node _T_1593 = bits(mcountinhibit, 5, 5) @[dec_tlu_ctl.scala 2272:38] + node _T_1594 = not(_T_1593) @[dec_tlu_ctl.scala 2272:24] + node _T_1595 = eq(mhpme_vec[2], UInt<1>("h01")) @[dec_tlu_ctl.scala 2273:34] + node _T_1596 = bits(_T_1595, 0, 0) @[dec_tlu_ctl.scala 2273:62] + node _T_1597 = eq(mhpme_vec[2], UInt<2>("h02")) @[dec_tlu_ctl.scala 2274:34] + node _T_1598 = bits(_T_1597, 0, 0) @[dec_tlu_ctl.scala 2274:62] + node _T_1599 = eq(mhpme_vec[2], UInt<2>("h03")) @[dec_tlu_ctl.scala 2275:34] + node _T_1600 = bits(_T_1599, 0, 0) @[dec_tlu_ctl.scala 2275:62] + node _T_1601 = eq(mhpme_vec[2], UInt<3>("h04")) @[dec_tlu_ctl.scala 2276:34] + node _T_1602 = bits(_T_1601, 0, 0) @[dec_tlu_ctl.scala 2276:62] + node _T_1603 = not(io.illegal_r) @[dec_tlu_ctl.scala 2276:96] + node _T_1604 = and(io.tlu_i0_commit_cmt, _T_1603) @[dec_tlu_ctl.scala 2276:94] + node _T_1605 = eq(mhpme_vec[2], UInt<3>("h05")) @[dec_tlu_ctl.scala 2277:34] + node _T_1606 = bits(_T_1605, 0, 0) @[dec_tlu_ctl.scala 2277:62] + node _T_1607 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2277:96] + node _T_1608 = and(io.tlu_i0_commit_cmt, _T_1607) @[dec_tlu_ctl.scala 2277:94] + node _T_1609 = not(io.illegal_r) @[dec_tlu_ctl.scala 2277:117] + node _T_1610 = and(_T_1608, _T_1609) @[dec_tlu_ctl.scala 2277:115] + node _T_1611 = eq(mhpme_vec[2], UInt<3>("h06")) @[dec_tlu_ctl.scala 2278:34] + node _T_1612 = bits(_T_1611, 0, 0) @[dec_tlu_ctl.scala 2278:62] + node _T_1613 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2278:94] + node _T_1614 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:117] + node _T_1615 = and(_T_1613, _T_1614) @[dec_tlu_ctl.scala 2278:115] + node _T_1616 = eq(mhpme_vec[2], UInt<3>("h07")) @[dec_tlu_ctl.scala 2279:34] + node _T_1617 = bits(_T_1616, 0, 0) @[dec_tlu_ctl.scala 2279:62] + node _T_1618 = eq(mhpme_vec[2], UInt<4>("h08")) @[dec_tlu_ctl.scala 2280:34] + node _T_1619 = bits(_T_1618, 0, 0) @[dec_tlu_ctl.scala 2280:62] + node _T_1620 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2281:34] + node _T_1621 = bits(_T_1620, 0, 0) @[dec_tlu_ctl.scala 2281:62] + node _T_1622 = eq(mhpme_vec[2], UInt<4>("h09")) @[dec_tlu_ctl.scala 2282:34] + node _T_1623 = bits(_T_1622, 0, 0) @[dec_tlu_ctl.scala 2282:62] + node _T_1624 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2282:91] + node _T_1625 = eq(mhpme_vec[2], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2283:34] + node _T_1626 = bits(_T_1625, 0, 0) @[dec_tlu_ctl.scala 2283:62] + node _T_1627 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2283:105] + node _T_1628 = eq(mhpme_vec[2], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2284:34] + node _T_1629 = bits(_T_1628, 0, 0) @[dec_tlu_ctl.scala 2284:62] + node _T_1630 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2284:91] + node _T_1631 = eq(mhpme_vec[2], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2285:34] + node _T_1632 = bits(_T_1631, 0, 0) @[dec_tlu_ctl.scala 2285:62] + node _T_1633 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2285:91] + node _T_1634 = eq(mhpme_vec[2], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2286:34] + node _T_1635 = bits(_T_1634, 0, 0) @[dec_tlu_ctl.scala 2286:62] + node _T_1636 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2286:91] + node _T_1637 = and(_T_1636, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2286:100] + node _T_1638 = eq(mhpme_vec[2], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2287:34] + node _T_1639 = bits(_T_1638, 0, 0) @[dec_tlu_ctl.scala 2287:62] + node _T_1640 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2287:91] + node _T_1641 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2287:142] + node _T_1642 = and(_T_1640, _T_1641) @[dec_tlu_ctl.scala 2287:101] + node _T_1643 = eq(mhpme_vec[2], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2288:34] + node _T_1644 = bits(_T_1643, 0, 0) @[dec_tlu_ctl.scala 2288:59] + node _T_1645 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2288:89] + node _T_1646 = eq(mhpme_vec[2], UInt<5>("h010")) @[dec_tlu_ctl.scala 2289:34] + node _T_1647 = bits(_T_1646, 0, 0) @[dec_tlu_ctl.scala 2289:59] + node _T_1648 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2289:89] + node _T_1649 = eq(mhpme_vec[2], UInt<5>("h012")) @[dec_tlu_ctl.scala 2290:34] + node _T_1650 = bits(_T_1649, 0, 0) @[dec_tlu_ctl.scala 2290:59] + node _T_1651 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2290:89] + node _T_1652 = eq(mhpme_vec[2], UInt<5>("h011")) @[dec_tlu_ctl.scala 2291:34] + node _T_1653 = bits(_T_1652, 0, 0) @[dec_tlu_ctl.scala 2291:59] + node _T_1654 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2291:89] + node _T_1655 = eq(mhpme_vec[2], UInt<5>("h013")) @[dec_tlu_ctl.scala 2292:34] + node _T_1656 = bits(_T_1655, 0, 0) @[dec_tlu_ctl.scala 2292:59] + node _T_1657 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2292:89] + node _T_1658 = eq(mhpme_vec[2], UInt<5>("h014")) @[dec_tlu_ctl.scala 2293:34] + node _T_1659 = bits(_T_1658, 0, 0) @[dec_tlu_ctl.scala 2293:59] + node _T_1660 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2293:89] + node _T_1661 = eq(mhpme_vec[2], UInt<5>("h015")) @[dec_tlu_ctl.scala 2294:34] + node _T_1662 = bits(_T_1661, 0, 0) @[dec_tlu_ctl.scala 2294:59] + node _T_1663 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2294:89] + node _T_1664 = eq(mhpme_vec[2], UInt<5>("h016")) @[dec_tlu_ctl.scala 2295:34] + node _T_1665 = bits(_T_1664, 0, 0) @[dec_tlu_ctl.scala 2295:59] + node _T_1666 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2295:89] + node _T_1667 = eq(mhpme_vec[2], UInt<5>("h017")) @[dec_tlu_ctl.scala 2296:34] + node _T_1668 = bits(_T_1667, 0, 0) @[dec_tlu_ctl.scala 2296:59] + node _T_1669 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2296:89] + node _T_1670 = eq(mhpme_vec[2], UInt<5>("h018")) @[dec_tlu_ctl.scala 2297:34] + node _T_1671 = bits(_T_1670, 0, 0) @[dec_tlu_ctl.scala 2297:59] + node _T_1672 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2297:89] + node _T_1673 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2297:122] + node _T_1674 = or(_T_1672, _T_1673) @[dec_tlu_ctl.scala 2297:101] + node _T_1675 = eq(mhpme_vec[2], UInt<5>("h019")) @[dec_tlu_ctl.scala 2298:34] + node _T_1676 = bits(_T_1675, 0, 0) @[dec_tlu_ctl.scala 2298:62] + node _T_1677 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2298:95] + node _T_1678 = eq(mhpme_vec[2], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2299:34] + node _T_1679 = bits(_T_1678, 0, 0) @[dec_tlu_ctl.scala 2299:62] + node _T_1680 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2299:97] + node _T_1681 = eq(mhpme_vec[2], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2300:34] + node _T_1682 = bits(_T_1681, 0, 0) @[dec_tlu_ctl.scala 2300:62] + node _T_1683 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:110] + node _T_1684 = eq(mhpme_vec[2], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2301:34] + node _T_1685 = bits(_T_1684, 0, 0) @[dec_tlu_ctl.scala 2301:62] + node _T_1686 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2302:34] + node _T_1687 = bits(_T_1686, 0, 0) @[dec_tlu_ctl.scala 2302:62] + node _T_1688 = eq(mhpme_vec[2], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2303:34] + node _T_1689 = bits(_T_1688, 0, 0) @[dec_tlu_ctl.scala 2303:62] + node _T_1690 = eq(mhpme_vec[2], UInt<6>("h020")) @[dec_tlu_ctl.scala 2304:34] + node _T_1691 = bits(_T_1690, 0, 0) @[dec_tlu_ctl.scala 2304:62] + node _T_1692 = eq(mhpme_vec[2], UInt<6>("h022")) @[dec_tlu_ctl.scala 2305:34] + node _T_1693 = bits(_T_1692, 0, 0) @[dec_tlu_ctl.scala 2305:62] + node _T_1694 = eq(mhpme_vec[2], UInt<6>("h023")) @[dec_tlu_ctl.scala 2306:34] + node _T_1695 = bits(_T_1694, 0, 0) @[dec_tlu_ctl.scala 2306:62] + node _T_1696 = eq(mhpme_vec[2], UInt<6>("h024")) @[dec_tlu_ctl.scala 2307:34] + node _T_1697 = bits(_T_1696, 0, 0) @[dec_tlu_ctl.scala 2307:62] + node _T_1698 = eq(mhpme_vec[2], UInt<6>("h025")) @[dec_tlu_ctl.scala 2308:34] + node _T_1699 = bits(_T_1698, 0, 0) @[dec_tlu_ctl.scala 2308:62] + node _T_1700 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2308:98] + node _T_1701 = or(_T_1700, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2308:120] + node _T_1702 = eq(mhpme_vec[2], UInt<6>("h026")) @[dec_tlu_ctl.scala 2309:34] + node _T_1703 = bits(_T_1702, 0, 0) @[dec_tlu_ctl.scala 2309:62] + node _T_1704 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2309:92] + node _T_1705 = or(_T_1704, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2309:117] + node _T_1706 = eq(mhpme_vec[2], UInt<6>("h027")) @[dec_tlu_ctl.scala 2310:34] + node _T_1707 = bits(_T_1706, 0, 0) @[dec_tlu_ctl.scala 2310:62] + node _T_1708 = eq(mhpme_vec[2], UInt<6>("h028")) @[dec_tlu_ctl.scala 2311:34] + node _T_1709 = bits(_T_1708, 0, 0) @[dec_tlu_ctl.scala 2311:62] + node _T_1710 = eq(mhpme_vec[2], UInt<6>("h029")) @[dec_tlu_ctl.scala 2312:34] + node _T_1711 = bits(_T_1710, 0, 0) @[dec_tlu_ctl.scala 2312:62] + node _T_1712 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2312:97] + node _T_1713 = and(_T_1712, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2312:129] + node _T_1714 = eq(mhpme_vec[2], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2313:34] + node _T_1715 = bits(_T_1714, 0, 0) @[dec_tlu_ctl.scala 2313:62] + node _T_1716 = eq(mhpme_vec[2], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2314:34] + node _T_1717 = bits(_T_1716, 0, 0) @[dec_tlu_ctl.scala 2314:62] + node _T_1718 = eq(mhpme_vec[2], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2315:34] + node _T_1719 = bits(_T_1718, 0, 0) @[dec_tlu_ctl.scala 2315:62] + node _T_1720 = eq(mhpme_vec[2], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2316:34] + node _T_1721 = bits(_T_1720, 0, 0) @[dec_tlu_ctl.scala 2316:62] + node _T_1722 = eq(mhpme_vec[2], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2317:34] + node _T_1723 = bits(_T_1722, 0, 0) @[dec_tlu_ctl.scala 2317:62] + node _T_1724 = eq(mhpme_vec[2], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2318:34] + node _T_1725 = bits(_T_1724, 0, 0) @[dec_tlu_ctl.scala 2318:62] + node _T_1726 = eq(mhpme_vec[2], UInt<6>("h030")) @[dec_tlu_ctl.scala 2319:34] + node _T_1727 = bits(_T_1726, 0, 0) @[dec_tlu_ctl.scala 2319:62] + node _T_1728 = eq(mhpme_vec[2], UInt<6>("h031")) @[dec_tlu_ctl.scala 2320:34] + node _T_1729 = bits(_T_1728, 0, 0) @[dec_tlu_ctl.scala 2320:62] + node _T_1730 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2320:84] + node _T_1731 = bits(_T_1730, 0, 0) @[dec_tlu_ctl.scala 2320:84] + node _T_1732 = not(_T_1731) @[dec_tlu_ctl.scala 2320:73] + node _T_1733 = eq(mhpme_vec[2], UInt<6>("h032")) @[dec_tlu_ctl.scala 2321:34] + node _T_1734 = bits(_T_1733, 0, 0) @[dec_tlu_ctl.scala 2321:62] + node _T_1735 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2321:84] + node _T_1736 = bits(_T_1735, 0, 0) @[dec_tlu_ctl.scala 2321:84] + node _T_1737 = not(_T_1736) @[dec_tlu_ctl.scala 2321:73] + node _T_1738 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2321:107] + node _T_1739 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2321:118] + node _T_1740 = and(_T_1738, _T_1739) @[dec_tlu_ctl.scala 2321:113] + node _T_1741 = orr(_T_1740) @[dec_tlu_ctl.scala 2321:125] + node _T_1742 = and(_T_1737, _T_1741) @[dec_tlu_ctl.scala 2321:98] + node _T_1743 = eq(mhpme_vec[2], UInt<6>("h036")) @[dec_tlu_ctl.scala 2322:34] + node _T_1744 = bits(_T_1743, 0, 0) @[dec_tlu_ctl.scala 2322:62] + node _T_1745 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2322:91] + node _T_1746 = eq(mhpme_vec[2], UInt<6>("h037")) @[dec_tlu_ctl.scala 2323:34] + node _T_1747 = bits(_T_1746, 0, 0) @[dec_tlu_ctl.scala 2323:62] + node _T_1748 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2323:94] + node _T_1749 = eq(mhpme_vec[2], UInt<6>("h038")) @[dec_tlu_ctl.scala 2324:34] + node _T_1750 = bits(_T_1749, 0, 0) @[dec_tlu_ctl.scala 2324:62] + node _T_1751 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2324:94] + node _T_1752 = eq(mhpme_vec[2], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2326:34] + node _T_1753 = bits(_T_1752, 0, 0) @[dec_tlu_ctl.scala 2326:62] + node _T_1754 = eq(mhpme_vec[2], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2327:34] + node _T_1755 = bits(_T_1754, 0, 0) @[dec_tlu_ctl.scala 2327:62] + node _T_1756 = eq(mhpme_vec[2], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2328:34] + node _T_1757 = bits(_T_1756, 0, 0) @[dec_tlu_ctl.scala 2328:62] + node _T_1758 = eq(mhpme_vec[2], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2329:34] + node _T_1759 = bits(_T_1758, 0, 0) @[dec_tlu_ctl.scala 2329:62] + node _T_1760 = eq(mhpme_vec[2], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2330:34] + node _T_1761 = bits(_T_1760, 0, 0) @[dec_tlu_ctl.scala 2330:62] + node _T_1762 = mux(_T_1596, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1763 = mux(_T_1598, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1764 = mux(_T_1600, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1765 = mux(_T_1602, _T_1604, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1766 = mux(_T_1606, _T_1610, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1767 = mux(_T_1612, _T_1615, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1768 = mux(_T_1617, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1769 = mux(_T_1619, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1770 = mux(_T_1621, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1771 = mux(_T_1623, _T_1624, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1772 = mux(_T_1626, _T_1627, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1773 = mux(_T_1629, _T_1630, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1774 = mux(_T_1632, _T_1633, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1775 = mux(_T_1635, _T_1637, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1776 = mux(_T_1639, _T_1642, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1777 = mux(_T_1644, _T_1645, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1778 = mux(_T_1647, _T_1648, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1779 = mux(_T_1650, _T_1651, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1780 = mux(_T_1653, _T_1654, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1781 = mux(_T_1656, _T_1657, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1782 = mux(_T_1659, _T_1660, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1783 = mux(_T_1662, _T_1663, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1784 = mux(_T_1665, _T_1666, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1785 = mux(_T_1668, _T_1669, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1786 = mux(_T_1671, _T_1674, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1787 = mux(_T_1676, _T_1677, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1788 = mux(_T_1679, _T_1680, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1789 = mux(_T_1682, _T_1683, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1790 = mux(_T_1685, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1791 = mux(_T_1687, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1792 = mux(_T_1689, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1793 = mux(_T_1691, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1794 = mux(_T_1693, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1795 = mux(_T_1695, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1796 = mux(_T_1697, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1797 = mux(_T_1699, _T_1701, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1798 = mux(_T_1703, _T_1705, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1799 = mux(_T_1707, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1800 = mux(_T_1709, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1801 = mux(_T_1711, _T_1713, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1802 = mux(_T_1715, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1803 = mux(_T_1717, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1804 = mux(_T_1719, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1805 = mux(_T_1721, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1806 = mux(_T_1723, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1807 = mux(_T_1725, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1808 = mux(_T_1727, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1809 = mux(_T_1729, _T_1732, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1810 = mux(_T_1734, _T_1742, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1811 = mux(_T_1744, _T_1745, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1812 = mux(_T_1747, _T_1748, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1813 = mux(_T_1750, _T_1751, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1814 = mux(_T_1753, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1815 = mux(_T_1755, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1816 = mux(_T_1757, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1817 = mux(_T_1759, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1818 = mux(_T_1761, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1819 = or(_T_1762, _T_1763) @[Mux.scala 27:72] node _T_1820 = or(_T_1819, _T_1764) @[Mux.scala 27:72] node _T_1821 = or(_T_1820, _T_1765) @[Mux.scala 27:72] node _T_1822 = or(_T_1821, _T_1766) @[Mux.scala 27:72] @@ -75258,247 +75258,247 @@ circuit quasar_wrapper : node _T_1862 = or(_T_1861, _T_1806) @[Mux.scala 27:72] node _T_1863 = or(_T_1862, _T_1807) @[Mux.scala 27:72] node _T_1864 = or(_T_1863, _T_1808) @[Mux.scala 27:72] - wire _T_1865 : UInt<1> @[Mux.scala 27:72] - _T_1865 <= _T_1864 @[Mux.scala 27:72] - node _T_1866 = and(_T_1584, _T_1865) @[dec_tlu_ctl.scala 2274:44] - mhpmc_inc_r[2] <= _T_1866 @[dec_tlu_ctl.scala 2274:19] - node _T_1867 = bits(mcountinhibit, 6, 6) @[dec_tlu_ctl.scala 2274:38] - node _T_1868 = not(_T_1867) @[dec_tlu_ctl.scala 2274:24] - node _T_1869 = eq(mhpme_vec[3], UInt<1>("h01")) @[dec_tlu_ctl.scala 2275:34] - node _T_1870 = bits(_T_1869, 0, 0) @[dec_tlu_ctl.scala 2275:62] - node _T_1871 = eq(mhpme_vec[3], UInt<2>("h02")) @[dec_tlu_ctl.scala 2276:34] - node _T_1872 = bits(_T_1871, 0, 0) @[dec_tlu_ctl.scala 2276:62] - node _T_1873 = eq(mhpme_vec[3], UInt<2>("h03")) @[dec_tlu_ctl.scala 2277:34] - node _T_1874 = bits(_T_1873, 0, 0) @[dec_tlu_ctl.scala 2277:62] - node _T_1875 = eq(mhpme_vec[3], UInt<3>("h04")) @[dec_tlu_ctl.scala 2278:34] - node _T_1876 = bits(_T_1875, 0, 0) @[dec_tlu_ctl.scala 2278:62] - node _T_1877 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:96] - node _T_1878 = and(io.tlu_i0_commit_cmt, _T_1877) @[dec_tlu_ctl.scala 2278:94] - node _T_1879 = eq(mhpme_vec[3], UInt<3>("h05")) @[dec_tlu_ctl.scala 2279:34] - node _T_1880 = bits(_T_1879, 0, 0) @[dec_tlu_ctl.scala 2279:62] - node _T_1881 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:96] - node _T_1882 = and(io.tlu_i0_commit_cmt, _T_1881) @[dec_tlu_ctl.scala 2279:94] - node _T_1883 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] - node _T_1884 = and(_T_1882, _T_1883) @[dec_tlu_ctl.scala 2279:115] - node _T_1885 = eq(mhpme_vec[3], UInt<3>("h06")) @[dec_tlu_ctl.scala 2280:34] - node _T_1886 = bits(_T_1885, 0, 0) @[dec_tlu_ctl.scala 2280:62] - node _T_1887 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2280:94] - node _T_1888 = not(io.illegal_r) @[dec_tlu_ctl.scala 2280:117] - node _T_1889 = and(_T_1887, _T_1888) @[dec_tlu_ctl.scala 2280:115] - node _T_1890 = eq(mhpme_vec[3], UInt<3>("h07")) @[dec_tlu_ctl.scala 2281:34] - node _T_1891 = bits(_T_1890, 0, 0) @[dec_tlu_ctl.scala 2281:62] - node _T_1892 = eq(mhpme_vec[3], UInt<4>("h08")) @[dec_tlu_ctl.scala 2282:34] - node _T_1893 = bits(_T_1892, 0, 0) @[dec_tlu_ctl.scala 2282:62] - node _T_1894 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2283:34] - node _T_1895 = bits(_T_1894, 0, 0) @[dec_tlu_ctl.scala 2283:62] - node _T_1896 = eq(mhpme_vec[3], UInt<4>("h09")) @[dec_tlu_ctl.scala 2284:34] - node _T_1897 = bits(_T_1896, 0, 0) @[dec_tlu_ctl.scala 2284:62] - node _T_1898 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2284:91] - node _T_1899 = eq(mhpme_vec[3], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2285:34] - node _T_1900 = bits(_T_1899, 0, 0) @[dec_tlu_ctl.scala 2285:62] - node _T_1901 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2285:105] - node _T_1902 = eq(mhpme_vec[3], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2286:34] - node _T_1903 = bits(_T_1902, 0, 0) @[dec_tlu_ctl.scala 2286:62] - node _T_1904 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2286:91] - node _T_1905 = eq(mhpme_vec[3], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2287:34] - node _T_1906 = bits(_T_1905, 0, 0) @[dec_tlu_ctl.scala 2287:62] - node _T_1907 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2287:91] - node _T_1908 = eq(mhpme_vec[3], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2288:34] - node _T_1909 = bits(_T_1908, 0, 0) @[dec_tlu_ctl.scala 2288:62] - node _T_1910 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2288:91] - node _T_1911 = and(_T_1910, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2288:100] - node _T_1912 = eq(mhpme_vec[3], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2289:34] - node _T_1913 = bits(_T_1912, 0, 0) @[dec_tlu_ctl.scala 2289:62] - node _T_1914 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2289:91] - node _T_1915 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2289:142] - node _T_1916 = and(_T_1914, _T_1915) @[dec_tlu_ctl.scala 2289:101] - node _T_1917 = eq(mhpme_vec[3], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2290:34] - node _T_1918 = bits(_T_1917, 0, 0) @[dec_tlu_ctl.scala 2290:59] - node _T_1919 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2290:89] - node _T_1920 = eq(mhpme_vec[3], UInt<5>("h010")) @[dec_tlu_ctl.scala 2291:34] - node _T_1921 = bits(_T_1920, 0, 0) @[dec_tlu_ctl.scala 2291:59] - node _T_1922 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2291:89] - node _T_1923 = eq(mhpme_vec[3], UInt<5>("h012")) @[dec_tlu_ctl.scala 2292:34] - node _T_1924 = bits(_T_1923, 0, 0) @[dec_tlu_ctl.scala 2292:59] - node _T_1925 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2292:89] - node _T_1926 = eq(mhpme_vec[3], UInt<5>("h011")) @[dec_tlu_ctl.scala 2293:34] - node _T_1927 = bits(_T_1926, 0, 0) @[dec_tlu_ctl.scala 2293:59] - node _T_1928 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2293:89] - node _T_1929 = eq(mhpme_vec[3], UInt<5>("h013")) @[dec_tlu_ctl.scala 2294:34] - node _T_1930 = bits(_T_1929, 0, 0) @[dec_tlu_ctl.scala 2294:59] - node _T_1931 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2294:89] - node _T_1932 = eq(mhpme_vec[3], UInt<5>("h014")) @[dec_tlu_ctl.scala 2295:34] - node _T_1933 = bits(_T_1932, 0, 0) @[dec_tlu_ctl.scala 2295:59] - node _T_1934 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2295:89] - node _T_1935 = eq(mhpme_vec[3], UInt<5>("h015")) @[dec_tlu_ctl.scala 2296:34] - node _T_1936 = bits(_T_1935, 0, 0) @[dec_tlu_ctl.scala 2296:59] - node _T_1937 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2296:89] - node _T_1938 = eq(mhpme_vec[3], UInt<5>("h016")) @[dec_tlu_ctl.scala 2297:34] - node _T_1939 = bits(_T_1938, 0, 0) @[dec_tlu_ctl.scala 2297:59] - node _T_1940 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2297:89] - node _T_1941 = eq(mhpme_vec[3], UInt<5>("h017")) @[dec_tlu_ctl.scala 2298:34] - node _T_1942 = bits(_T_1941, 0, 0) @[dec_tlu_ctl.scala 2298:59] - node _T_1943 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2298:89] - node _T_1944 = eq(mhpme_vec[3], UInt<5>("h018")) @[dec_tlu_ctl.scala 2299:34] - node _T_1945 = bits(_T_1944, 0, 0) @[dec_tlu_ctl.scala 2299:59] - node _T_1946 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2299:89] - node _T_1947 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2299:122] - node _T_1948 = or(_T_1946, _T_1947) @[dec_tlu_ctl.scala 2299:101] - node _T_1949 = eq(mhpme_vec[3], UInt<5>("h019")) @[dec_tlu_ctl.scala 2300:34] - node _T_1950 = bits(_T_1949, 0, 0) @[dec_tlu_ctl.scala 2300:62] - node _T_1951 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:95] - node _T_1952 = eq(mhpme_vec[3], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2301:34] - node _T_1953 = bits(_T_1952, 0, 0) @[dec_tlu_ctl.scala 2301:62] - node _T_1954 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:97] - node _T_1955 = eq(mhpme_vec[3], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2302:34] - node _T_1956 = bits(_T_1955, 0, 0) @[dec_tlu_ctl.scala 2302:62] - node _T_1957 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2302:110] - node _T_1958 = eq(mhpme_vec[3], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2303:34] - node _T_1959 = bits(_T_1958, 0, 0) @[dec_tlu_ctl.scala 2303:62] - node _T_1960 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2304:34] - node _T_1961 = bits(_T_1960, 0, 0) @[dec_tlu_ctl.scala 2304:62] - node _T_1962 = eq(mhpme_vec[3], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2305:34] - node _T_1963 = bits(_T_1962, 0, 0) @[dec_tlu_ctl.scala 2305:62] - node _T_1964 = eq(mhpme_vec[3], UInt<6>("h020")) @[dec_tlu_ctl.scala 2306:34] - node _T_1965 = bits(_T_1964, 0, 0) @[dec_tlu_ctl.scala 2306:62] - node _T_1966 = eq(mhpme_vec[3], UInt<6>("h022")) @[dec_tlu_ctl.scala 2307:34] - node _T_1967 = bits(_T_1966, 0, 0) @[dec_tlu_ctl.scala 2307:62] - node _T_1968 = eq(mhpme_vec[3], UInt<6>("h023")) @[dec_tlu_ctl.scala 2308:34] - node _T_1969 = bits(_T_1968, 0, 0) @[dec_tlu_ctl.scala 2308:62] - node _T_1970 = eq(mhpme_vec[3], UInt<6>("h024")) @[dec_tlu_ctl.scala 2309:34] - node _T_1971 = bits(_T_1970, 0, 0) @[dec_tlu_ctl.scala 2309:62] - node _T_1972 = eq(mhpme_vec[3], UInt<6>("h025")) @[dec_tlu_ctl.scala 2310:34] - node _T_1973 = bits(_T_1972, 0, 0) @[dec_tlu_ctl.scala 2310:62] - node _T_1974 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2310:98] - node _T_1975 = or(_T_1974, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2310:120] - node _T_1976 = eq(mhpme_vec[3], UInt<6>("h026")) @[dec_tlu_ctl.scala 2311:34] - node _T_1977 = bits(_T_1976, 0, 0) @[dec_tlu_ctl.scala 2311:62] - node _T_1978 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2311:92] - node _T_1979 = or(_T_1978, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2311:117] - node _T_1980 = eq(mhpme_vec[3], UInt<6>("h027")) @[dec_tlu_ctl.scala 2312:34] - node _T_1981 = bits(_T_1980, 0, 0) @[dec_tlu_ctl.scala 2312:62] - node _T_1982 = eq(mhpme_vec[3], UInt<6>("h028")) @[dec_tlu_ctl.scala 2313:34] - node _T_1983 = bits(_T_1982, 0, 0) @[dec_tlu_ctl.scala 2313:62] - node _T_1984 = eq(mhpme_vec[3], UInt<6>("h029")) @[dec_tlu_ctl.scala 2314:34] - node _T_1985 = bits(_T_1984, 0, 0) @[dec_tlu_ctl.scala 2314:62] - node _T_1986 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2314:97] - node _T_1987 = and(_T_1986, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2314:129] - node _T_1988 = eq(mhpme_vec[3], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2315:34] - node _T_1989 = bits(_T_1988, 0, 0) @[dec_tlu_ctl.scala 2315:62] - node _T_1990 = eq(mhpme_vec[3], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2316:34] - node _T_1991 = bits(_T_1990, 0, 0) @[dec_tlu_ctl.scala 2316:62] - node _T_1992 = eq(mhpme_vec[3], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2317:34] - node _T_1993 = bits(_T_1992, 0, 0) @[dec_tlu_ctl.scala 2317:62] - node _T_1994 = eq(mhpme_vec[3], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2318:34] - node _T_1995 = bits(_T_1994, 0, 0) @[dec_tlu_ctl.scala 2318:62] - node _T_1996 = eq(mhpme_vec[3], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2319:34] - node _T_1997 = bits(_T_1996, 0, 0) @[dec_tlu_ctl.scala 2319:62] - node _T_1998 = eq(mhpme_vec[3], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2320:34] - node _T_1999 = bits(_T_1998, 0, 0) @[dec_tlu_ctl.scala 2320:62] - node _T_2000 = eq(mhpme_vec[3], UInt<6>("h030")) @[dec_tlu_ctl.scala 2321:34] - node _T_2001 = bits(_T_2000, 0, 0) @[dec_tlu_ctl.scala 2321:62] - node _T_2002 = eq(mhpme_vec[3], UInt<6>("h031")) @[dec_tlu_ctl.scala 2322:34] - node _T_2003 = bits(_T_2002, 0, 0) @[dec_tlu_ctl.scala 2322:62] - node _T_2004 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] - node _T_2005 = bits(_T_2004, 0, 0) @[dec_tlu_ctl.scala 2322:84] - node _T_2006 = not(_T_2005) @[dec_tlu_ctl.scala 2322:73] - node _T_2007 = eq(mhpme_vec[3], UInt<6>("h032")) @[dec_tlu_ctl.scala 2323:34] - node _T_2008 = bits(_T_2007, 0, 0) @[dec_tlu_ctl.scala 2323:62] - node _T_2009 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2323:84] - node _T_2010 = bits(_T_2009, 0, 0) @[dec_tlu_ctl.scala 2323:84] - node _T_2011 = not(_T_2010) @[dec_tlu_ctl.scala 2323:73] - node _T_2012 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2323:107] - node _T_2013 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2323:118] - node _T_2014 = and(_T_2012, _T_2013) @[dec_tlu_ctl.scala 2323:113] - node _T_2015 = orr(_T_2014) @[dec_tlu_ctl.scala 2323:125] - node _T_2016 = and(_T_2011, _T_2015) @[dec_tlu_ctl.scala 2323:98] - node _T_2017 = eq(mhpme_vec[3], UInt<6>("h036")) @[dec_tlu_ctl.scala 2324:34] - node _T_2018 = bits(_T_2017, 0, 0) @[dec_tlu_ctl.scala 2324:62] - node _T_2019 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2324:91] - node _T_2020 = eq(mhpme_vec[3], UInt<6>("h037")) @[dec_tlu_ctl.scala 2325:34] - node _T_2021 = bits(_T_2020, 0, 0) @[dec_tlu_ctl.scala 2325:62] - node _T_2022 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2325:94] - node _T_2023 = eq(mhpme_vec[3], UInt<6>("h038")) @[dec_tlu_ctl.scala 2326:34] - node _T_2024 = bits(_T_2023, 0, 0) @[dec_tlu_ctl.scala 2326:62] - node _T_2025 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2326:94] - node _T_2026 = eq(mhpme_vec[3], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2328:34] - node _T_2027 = bits(_T_2026, 0, 0) @[dec_tlu_ctl.scala 2328:62] - node _T_2028 = eq(mhpme_vec[3], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2329:34] - node _T_2029 = bits(_T_2028, 0, 0) @[dec_tlu_ctl.scala 2329:62] - node _T_2030 = eq(mhpme_vec[3], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2330:34] - node _T_2031 = bits(_T_2030, 0, 0) @[dec_tlu_ctl.scala 2330:62] - node _T_2032 = eq(mhpme_vec[3], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2331:34] - node _T_2033 = bits(_T_2032, 0, 0) @[dec_tlu_ctl.scala 2331:62] - node _T_2034 = eq(mhpme_vec[3], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2332:34] - node _T_2035 = bits(_T_2034, 0, 0) @[dec_tlu_ctl.scala 2332:62] - node _T_2036 = mux(_T_1870, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2037 = mux(_T_1872, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2038 = mux(_T_1874, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2039 = mux(_T_1876, _T_1878, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2040 = mux(_T_1880, _T_1884, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2041 = mux(_T_1886, _T_1889, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2042 = mux(_T_1891, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2043 = mux(_T_1893, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2044 = mux(_T_1895, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2045 = mux(_T_1897, _T_1898, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2046 = mux(_T_1900, _T_1901, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2047 = mux(_T_1903, _T_1904, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2048 = mux(_T_1906, _T_1907, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2049 = mux(_T_1909, _T_1911, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2050 = mux(_T_1913, _T_1916, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2051 = mux(_T_1918, _T_1919, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2052 = mux(_T_1921, _T_1922, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2053 = mux(_T_1924, _T_1925, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2054 = mux(_T_1927, _T_1928, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2055 = mux(_T_1930, _T_1931, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2056 = mux(_T_1933, _T_1934, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2057 = mux(_T_1936, _T_1937, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2058 = mux(_T_1939, _T_1940, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2059 = mux(_T_1942, _T_1943, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2060 = mux(_T_1945, _T_1948, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2061 = mux(_T_1950, _T_1951, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2062 = mux(_T_1953, _T_1954, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2063 = mux(_T_1956, _T_1957, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2064 = mux(_T_1959, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2065 = mux(_T_1961, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2066 = mux(_T_1963, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2067 = mux(_T_1965, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2068 = mux(_T_1967, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2069 = mux(_T_1969, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2070 = mux(_T_1971, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2071 = mux(_T_1973, _T_1975, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2072 = mux(_T_1977, _T_1979, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2073 = mux(_T_1981, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2074 = mux(_T_1983, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2075 = mux(_T_1985, _T_1987, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2076 = mux(_T_1989, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2077 = mux(_T_1991, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2078 = mux(_T_1993, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2079 = mux(_T_1995, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2080 = mux(_T_1997, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2081 = mux(_T_1999, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2082 = mux(_T_2001, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2083 = mux(_T_2003, _T_2006, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2084 = mux(_T_2008, _T_2016, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2085 = mux(_T_2018, _T_2019, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2086 = mux(_T_2021, _T_2022, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2087 = mux(_T_2024, _T_2025, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2088 = mux(_T_2027, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2089 = mux(_T_2029, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2090 = mux(_T_2031, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2091 = mux(_T_2033, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2092 = mux(_T_2035, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2093 = or(_T_2036, _T_2037) @[Mux.scala 27:72] - node _T_2094 = or(_T_2093, _T_2038) @[Mux.scala 27:72] - node _T_2095 = or(_T_2094, _T_2039) @[Mux.scala 27:72] - node _T_2096 = or(_T_2095, _T_2040) @[Mux.scala 27:72] - node _T_2097 = or(_T_2096, _T_2041) @[Mux.scala 27:72] - node _T_2098 = or(_T_2097, _T_2042) @[Mux.scala 27:72] - node _T_2099 = or(_T_2098, _T_2043) @[Mux.scala 27:72] - node _T_2100 = or(_T_2099, _T_2044) @[Mux.scala 27:72] - node _T_2101 = or(_T_2100, _T_2045) @[Mux.scala 27:72] - node _T_2102 = or(_T_2101, _T_2046) @[Mux.scala 27:72] - node _T_2103 = or(_T_2102, _T_2047) @[Mux.scala 27:72] + node _T_1865 = or(_T_1864, _T_1809) @[Mux.scala 27:72] + node _T_1866 = or(_T_1865, _T_1810) @[Mux.scala 27:72] + node _T_1867 = or(_T_1866, _T_1811) @[Mux.scala 27:72] + node _T_1868 = or(_T_1867, _T_1812) @[Mux.scala 27:72] + node _T_1869 = or(_T_1868, _T_1813) @[Mux.scala 27:72] + node _T_1870 = or(_T_1869, _T_1814) @[Mux.scala 27:72] + node _T_1871 = or(_T_1870, _T_1815) @[Mux.scala 27:72] + node _T_1872 = or(_T_1871, _T_1816) @[Mux.scala 27:72] + node _T_1873 = or(_T_1872, _T_1817) @[Mux.scala 27:72] + node _T_1874 = or(_T_1873, _T_1818) @[Mux.scala 27:72] + wire _T_1875 : UInt<1> @[Mux.scala 27:72] + _T_1875 <= _T_1874 @[Mux.scala 27:72] + node _T_1876 = and(_T_1594, _T_1875) @[dec_tlu_ctl.scala 2272:44] + mhpmc_inc_r[2] <= _T_1876 @[dec_tlu_ctl.scala 2272:19] + node _T_1877 = bits(mcountinhibit, 6, 6) @[dec_tlu_ctl.scala 2272:38] + node _T_1878 = not(_T_1877) @[dec_tlu_ctl.scala 2272:24] + node _T_1879 = eq(mhpme_vec[3], UInt<1>("h01")) @[dec_tlu_ctl.scala 2273:34] + node _T_1880 = bits(_T_1879, 0, 0) @[dec_tlu_ctl.scala 2273:62] + node _T_1881 = eq(mhpme_vec[3], UInt<2>("h02")) @[dec_tlu_ctl.scala 2274:34] + node _T_1882 = bits(_T_1881, 0, 0) @[dec_tlu_ctl.scala 2274:62] + node _T_1883 = eq(mhpme_vec[3], UInt<2>("h03")) @[dec_tlu_ctl.scala 2275:34] + node _T_1884 = bits(_T_1883, 0, 0) @[dec_tlu_ctl.scala 2275:62] + node _T_1885 = eq(mhpme_vec[3], UInt<3>("h04")) @[dec_tlu_ctl.scala 2276:34] + node _T_1886 = bits(_T_1885, 0, 0) @[dec_tlu_ctl.scala 2276:62] + node _T_1887 = not(io.illegal_r) @[dec_tlu_ctl.scala 2276:96] + node _T_1888 = and(io.tlu_i0_commit_cmt, _T_1887) @[dec_tlu_ctl.scala 2276:94] + node _T_1889 = eq(mhpme_vec[3], UInt<3>("h05")) @[dec_tlu_ctl.scala 2277:34] + node _T_1890 = bits(_T_1889, 0, 0) @[dec_tlu_ctl.scala 2277:62] + node _T_1891 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2277:96] + node _T_1892 = and(io.tlu_i0_commit_cmt, _T_1891) @[dec_tlu_ctl.scala 2277:94] + node _T_1893 = not(io.illegal_r) @[dec_tlu_ctl.scala 2277:117] + node _T_1894 = and(_T_1892, _T_1893) @[dec_tlu_ctl.scala 2277:115] + node _T_1895 = eq(mhpme_vec[3], UInt<3>("h06")) @[dec_tlu_ctl.scala 2278:34] + node _T_1896 = bits(_T_1895, 0, 0) @[dec_tlu_ctl.scala 2278:62] + node _T_1897 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2278:94] + node _T_1898 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:117] + node _T_1899 = and(_T_1897, _T_1898) @[dec_tlu_ctl.scala 2278:115] + node _T_1900 = eq(mhpme_vec[3], UInt<3>("h07")) @[dec_tlu_ctl.scala 2279:34] + node _T_1901 = bits(_T_1900, 0, 0) @[dec_tlu_ctl.scala 2279:62] + node _T_1902 = eq(mhpme_vec[3], UInt<4>("h08")) @[dec_tlu_ctl.scala 2280:34] + node _T_1903 = bits(_T_1902, 0, 0) @[dec_tlu_ctl.scala 2280:62] + node _T_1904 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2281:34] + node _T_1905 = bits(_T_1904, 0, 0) @[dec_tlu_ctl.scala 2281:62] + node _T_1906 = eq(mhpme_vec[3], UInt<4>("h09")) @[dec_tlu_ctl.scala 2282:34] + node _T_1907 = bits(_T_1906, 0, 0) @[dec_tlu_ctl.scala 2282:62] + node _T_1908 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2282:91] + node _T_1909 = eq(mhpme_vec[3], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2283:34] + node _T_1910 = bits(_T_1909, 0, 0) @[dec_tlu_ctl.scala 2283:62] + node _T_1911 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2283:105] + node _T_1912 = eq(mhpme_vec[3], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2284:34] + node _T_1913 = bits(_T_1912, 0, 0) @[dec_tlu_ctl.scala 2284:62] + node _T_1914 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2284:91] + node _T_1915 = eq(mhpme_vec[3], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2285:34] + node _T_1916 = bits(_T_1915, 0, 0) @[dec_tlu_ctl.scala 2285:62] + node _T_1917 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2285:91] + node _T_1918 = eq(mhpme_vec[3], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2286:34] + node _T_1919 = bits(_T_1918, 0, 0) @[dec_tlu_ctl.scala 2286:62] + node _T_1920 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2286:91] + node _T_1921 = and(_T_1920, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2286:100] + node _T_1922 = eq(mhpme_vec[3], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2287:34] + node _T_1923 = bits(_T_1922, 0, 0) @[dec_tlu_ctl.scala 2287:62] + node _T_1924 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2287:91] + node _T_1925 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2287:142] + node _T_1926 = and(_T_1924, _T_1925) @[dec_tlu_ctl.scala 2287:101] + node _T_1927 = eq(mhpme_vec[3], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2288:34] + node _T_1928 = bits(_T_1927, 0, 0) @[dec_tlu_ctl.scala 2288:59] + node _T_1929 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2288:89] + node _T_1930 = eq(mhpme_vec[3], UInt<5>("h010")) @[dec_tlu_ctl.scala 2289:34] + node _T_1931 = bits(_T_1930, 0, 0) @[dec_tlu_ctl.scala 2289:59] + node _T_1932 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2289:89] + node _T_1933 = eq(mhpme_vec[3], UInt<5>("h012")) @[dec_tlu_ctl.scala 2290:34] + node _T_1934 = bits(_T_1933, 0, 0) @[dec_tlu_ctl.scala 2290:59] + node _T_1935 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2290:89] + node _T_1936 = eq(mhpme_vec[3], UInt<5>("h011")) @[dec_tlu_ctl.scala 2291:34] + node _T_1937 = bits(_T_1936, 0, 0) @[dec_tlu_ctl.scala 2291:59] + node _T_1938 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2291:89] + node _T_1939 = eq(mhpme_vec[3], UInt<5>("h013")) @[dec_tlu_ctl.scala 2292:34] + node _T_1940 = bits(_T_1939, 0, 0) @[dec_tlu_ctl.scala 2292:59] + node _T_1941 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2292:89] + node _T_1942 = eq(mhpme_vec[3], UInt<5>("h014")) @[dec_tlu_ctl.scala 2293:34] + node _T_1943 = bits(_T_1942, 0, 0) @[dec_tlu_ctl.scala 2293:59] + node _T_1944 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2293:89] + node _T_1945 = eq(mhpme_vec[3], UInt<5>("h015")) @[dec_tlu_ctl.scala 2294:34] + node _T_1946 = bits(_T_1945, 0, 0) @[dec_tlu_ctl.scala 2294:59] + node _T_1947 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2294:89] + node _T_1948 = eq(mhpme_vec[3], UInt<5>("h016")) @[dec_tlu_ctl.scala 2295:34] + node _T_1949 = bits(_T_1948, 0, 0) @[dec_tlu_ctl.scala 2295:59] + node _T_1950 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2295:89] + node _T_1951 = eq(mhpme_vec[3], UInt<5>("h017")) @[dec_tlu_ctl.scala 2296:34] + node _T_1952 = bits(_T_1951, 0, 0) @[dec_tlu_ctl.scala 2296:59] + node _T_1953 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2296:89] + node _T_1954 = eq(mhpme_vec[3], UInt<5>("h018")) @[dec_tlu_ctl.scala 2297:34] + node _T_1955 = bits(_T_1954, 0, 0) @[dec_tlu_ctl.scala 2297:59] + node _T_1956 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2297:89] + node _T_1957 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2297:122] + node _T_1958 = or(_T_1956, _T_1957) @[dec_tlu_ctl.scala 2297:101] + node _T_1959 = eq(mhpme_vec[3], UInt<5>("h019")) @[dec_tlu_ctl.scala 2298:34] + node _T_1960 = bits(_T_1959, 0, 0) @[dec_tlu_ctl.scala 2298:62] + node _T_1961 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2298:95] + node _T_1962 = eq(mhpme_vec[3], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2299:34] + node _T_1963 = bits(_T_1962, 0, 0) @[dec_tlu_ctl.scala 2299:62] + node _T_1964 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2299:97] + node _T_1965 = eq(mhpme_vec[3], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2300:34] + node _T_1966 = bits(_T_1965, 0, 0) @[dec_tlu_ctl.scala 2300:62] + node _T_1967 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:110] + node _T_1968 = eq(mhpme_vec[3], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2301:34] + node _T_1969 = bits(_T_1968, 0, 0) @[dec_tlu_ctl.scala 2301:62] + node _T_1970 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2302:34] + node _T_1971 = bits(_T_1970, 0, 0) @[dec_tlu_ctl.scala 2302:62] + node _T_1972 = eq(mhpme_vec[3], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2303:34] + node _T_1973 = bits(_T_1972, 0, 0) @[dec_tlu_ctl.scala 2303:62] + node _T_1974 = eq(mhpme_vec[3], UInt<6>("h020")) @[dec_tlu_ctl.scala 2304:34] + node _T_1975 = bits(_T_1974, 0, 0) @[dec_tlu_ctl.scala 2304:62] + node _T_1976 = eq(mhpme_vec[3], UInt<6>("h022")) @[dec_tlu_ctl.scala 2305:34] + node _T_1977 = bits(_T_1976, 0, 0) @[dec_tlu_ctl.scala 2305:62] + node _T_1978 = eq(mhpme_vec[3], UInt<6>("h023")) @[dec_tlu_ctl.scala 2306:34] + node _T_1979 = bits(_T_1978, 0, 0) @[dec_tlu_ctl.scala 2306:62] + node _T_1980 = eq(mhpme_vec[3], UInt<6>("h024")) @[dec_tlu_ctl.scala 2307:34] + node _T_1981 = bits(_T_1980, 0, 0) @[dec_tlu_ctl.scala 2307:62] + node _T_1982 = eq(mhpme_vec[3], UInt<6>("h025")) @[dec_tlu_ctl.scala 2308:34] + node _T_1983 = bits(_T_1982, 0, 0) @[dec_tlu_ctl.scala 2308:62] + node _T_1984 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2308:98] + node _T_1985 = or(_T_1984, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2308:120] + node _T_1986 = eq(mhpme_vec[3], UInt<6>("h026")) @[dec_tlu_ctl.scala 2309:34] + node _T_1987 = bits(_T_1986, 0, 0) @[dec_tlu_ctl.scala 2309:62] + node _T_1988 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2309:92] + node _T_1989 = or(_T_1988, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2309:117] + node _T_1990 = eq(mhpme_vec[3], UInt<6>("h027")) @[dec_tlu_ctl.scala 2310:34] + node _T_1991 = bits(_T_1990, 0, 0) @[dec_tlu_ctl.scala 2310:62] + node _T_1992 = eq(mhpme_vec[3], UInt<6>("h028")) @[dec_tlu_ctl.scala 2311:34] + node _T_1993 = bits(_T_1992, 0, 0) @[dec_tlu_ctl.scala 2311:62] + node _T_1994 = eq(mhpme_vec[3], UInt<6>("h029")) @[dec_tlu_ctl.scala 2312:34] + node _T_1995 = bits(_T_1994, 0, 0) @[dec_tlu_ctl.scala 2312:62] + node _T_1996 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2312:97] + node _T_1997 = and(_T_1996, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2312:129] + node _T_1998 = eq(mhpme_vec[3], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2313:34] + node _T_1999 = bits(_T_1998, 0, 0) @[dec_tlu_ctl.scala 2313:62] + node _T_2000 = eq(mhpme_vec[3], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2314:34] + node _T_2001 = bits(_T_2000, 0, 0) @[dec_tlu_ctl.scala 2314:62] + node _T_2002 = eq(mhpme_vec[3], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2315:34] + node _T_2003 = bits(_T_2002, 0, 0) @[dec_tlu_ctl.scala 2315:62] + node _T_2004 = eq(mhpme_vec[3], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2316:34] + node _T_2005 = bits(_T_2004, 0, 0) @[dec_tlu_ctl.scala 2316:62] + node _T_2006 = eq(mhpme_vec[3], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2317:34] + node _T_2007 = bits(_T_2006, 0, 0) @[dec_tlu_ctl.scala 2317:62] + node _T_2008 = eq(mhpme_vec[3], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2318:34] + node _T_2009 = bits(_T_2008, 0, 0) @[dec_tlu_ctl.scala 2318:62] + node _T_2010 = eq(mhpme_vec[3], UInt<6>("h030")) @[dec_tlu_ctl.scala 2319:34] + node _T_2011 = bits(_T_2010, 0, 0) @[dec_tlu_ctl.scala 2319:62] + node _T_2012 = eq(mhpme_vec[3], UInt<6>("h031")) @[dec_tlu_ctl.scala 2320:34] + node _T_2013 = bits(_T_2012, 0, 0) @[dec_tlu_ctl.scala 2320:62] + node _T_2014 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2320:84] + node _T_2015 = bits(_T_2014, 0, 0) @[dec_tlu_ctl.scala 2320:84] + node _T_2016 = not(_T_2015) @[dec_tlu_ctl.scala 2320:73] + node _T_2017 = eq(mhpme_vec[3], UInt<6>("h032")) @[dec_tlu_ctl.scala 2321:34] + node _T_2018 = bits(_T_2017, 0, 0) @[dec_tlu_ctl.scala 2321:62] + node _T_2019 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2321:84] + node _T_2020 = bits(_T_2019, 0, 0) @[dec_tlu_ctl.scala 2321:84] + node _T_2021 = not(_T_2020) @[dec_tlu_ctl.scala 2321:73] + node _T_2022 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2321:107] + node _T_2023 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2321:118] + node _T_2024 = and(_T_2022, _T_2023) @[dec_tlu_ctl.scala 2321:113] + node _T_2025 = orr(_T_2024) @[dec_tlu_ctl.scala 2321:125] + node _T_2026 = and(_T_2021, _T_2025) @[dec_tlu_ctl.scala 2321:98] + node _T_2027 = eq(mhpme_vec[3], UInt<6>("h036")) @[dec_tlu_ctl.scala 2322:34] + node _T_2028 = bits(_T_2027, 0, 0) @[dec_tlu_ctl.scala 2322:62] + node _T_2029 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2322:91] + node _T_2030 = eq(mhpme_vec[3], UInt<6>("h037")) @[dec_tlu_ctl.scala 2323:34] + node _T_2031 = bits(_T_2030, 0, 0) @[dec_tlu_ctl.scala 2323:62] + node _T_2032 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2323:94] + node _T_2033 = eq(mhpme_vec[3], UInt<6>("h038")) @[dec_tlu_ctl.scala 2324:34] + node _T_2034 = bits(_T_2033, 0, 0) @[dec_tlu_ctl.scala 2324:62] + node _T_2035 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2324:94] + node _T_2036 = eq(mhpme_vec[3], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2326:34] + node _T_2037 = bits(_T_2036, 0, 0) @[dec_tlu_ctl.scala 2326:62] + node _T_2038 = eq(mhpme_vec[3], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2327:34] + node _T_2039 = bits(_T_2038, 0, 0) @[dec_tlu_ctl.scala 2327:62] + node _T_2040 = eq(mhpme_vec[3], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2328:34] + node _T_2041 = bits(_T_2040, 0, 0) @[dec_tlu_ctl.scala 2328:62] + node _T_2042 = eq(mhpme_vec[3], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2329:34] + node _T_2043 = bits(_T_2042, 0, 0) @[dec_tlu_ctl.scala 2329:62] + node _T_2044 = eq(mhpme_vec[3], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2330:34] + node _T_2045 = bits(_T_2044, 0, 0) @[dec_tlu_ctl.scala 2330:62] + node _T_2046 = mux(_T_1880, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2047 = mux(_T_1882, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2048 = mux(_T_1884, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2049 = mux(_T_1886, _T_1888, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2050 = mux(_T_1890, _T_1894, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2051 = mux(_T_1896, _T_1899, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2052 = mux(_T_1901, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2053 = mux(_T_1903, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2054 = mux(_T_1905, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2055 = mux(_T_1907, _T_1908, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2056 = mux(_T_1910, _T_1911, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2057 = mux(_T_1913, _T_1914, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2058 = mux(_T_1916, _T_1917, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2059 = mux(_T_1919, _T_1921, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2060 = mux(_T_1923, _T_1926, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2061 = mux(_T_1928, _T_1929, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2062 = mux(_T_1931, _T_1932, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2063 = mux(_T_1934, _T_1935, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2064 = mux(_T_1937, _T_1938, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2065 = mux(_T_1940, _T_1941, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2066 = mux(_T_1943, _T_1944, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2067 = mux(_T_1946, _T_1947, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2068 = mux(_T_1949, _T_1950, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2069 = mux(_T_1952, _T_1953, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2070 = mux(_T_1955, _T_1958, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2071 = mux(_T_1960, _T_1961, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2072 = mux(_T_1963, _T_1964, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2073 = mux(_T_1966, _T_1967, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2074 = mux(_T_1969, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2075 = mux(_T_1971, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2076 = mux(_T_1973, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2077 = mux(_T_1975, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2078 = mux(_T_1977, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2079 = mux(_T_1979, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2080 = mux(_T_1981, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2081 = mux(_T_1983, _T_1985, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2082 = mux(_T_1987, _T_1989, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2083 = mux(_T_1991, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2084 = mux(_T_1993, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2085 = mux(_T_1995, _T_1997, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2086 = mux(_T_1999, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2087 = mux(_T_2001, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2088 = mux(_T_2003, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2089 = mux(_T_2005, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2090 = mux(_T_2007, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2091 = mux(_T_2009, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2092 = mux(_T_2011, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2093 = mux(_T_2013, _T_2016, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2094 = mux(_T_2018, _T_2026, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2095 = mux(_T_2028, _T_2029, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2096 = mux(_T_2031, _T_2032, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2097 = mux(_T_2034, _T_2035, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2098 = mux(_T_2037, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2099 = mux(_T_2039, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2100 = mux(_T_2041, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2101 = mux(_T_2043, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2102 = mux(_T_2045, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2103 = or(_T_2046, _T_2047) @[Mux.scala 27:72] node _T_2104 = or(_T_2103, _T_2048) @[Mux.scala 27:72] node _T_2105 = or(_T_2104, _T_2049) @[Mux.scala 27:72] node _T_2106 = or(_T_2105, _T_2050) @[Mux.scala 27:72] @@ -75544,585 +75544,585 @@ circuit quasar_wrapper : node _T_2146 = or(_T_2145, _T_2090) @[Mux.scala 27:72] node _T_2147 = or(_T_2146, _T_2091) @[Mux.scala 27:72] node _T_2148 = or(_T_2147, _T_2092) @[Mux.scala 27:72] - wire _T_2149 : UInt<1> @[Mux.scala 27:72] - _T_2149 <= _T_2148 @[Mux.scala 27:72] - node _T_2150 = and(_T_1868, _T_2149) @[dec_tlu_ctl.scala 2274:44] - mhpmc_inc_r[3] <= _T_2150 @[dec_tlu_ctl.scala 2274:19] - reg _T_2151 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2335:53] - _T_2151 <= mhpmc_inc_r[0] @[dec_tlu_ctl.scala 2335:53] - mhpmc_inc_r_d1[0] <= _T_2151 @[dec_tlu_ctl.scala 2335:20] - reg _T_2152 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2336:53] - _T_2152 <= mhpmc_inc_r[1] @[dec_tlu_ctl.scala 2336:53] - mhpmc_inc_r_d1[1] <= _T_2152 @[dec_tlu_ctl.scala 2336:20] - reg _T_2153 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2337:53] - _T_2153 <= mhpmc_inc_r[2] @[dec_tlu_ctl.scala 2337:53] - mhpmc_inc_r_d1[2] <= _T_2153 @[dec_tlu_ctl.scala 2337:20] - reg _T_2154 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2338:53] - _T_2154 <= mhpmc_inc_r[3] @[dec_tlu_ctl.scala 2338:53] - mhpmc_inc_r_d1[3] <= _T_2154 @[dec_tlu_ctl.scala 2338:20] - reg perfcnt_halted_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2339:56] - perfcnt_halted_d1 <= perfcnt_halted @[dec_tlu_ctl.scala 2339:56] - node _T_2155 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2342:53] - node _T_2156 = and(io.dec_tlu_dbg_halted, _T_2155) @[dec_tlu_ctl.scala 2342:44] - node _T_2157 = or(_T_2156, io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2342:67] - perfcnt_halted <= _T_2157 @[dec_tlu_ctl.scala 2342:17] - node _T_2158 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2343:70] - node _T_2159 = and(io.dec_tlu_dbg_halted, _T_2158) @[dec_tlu_ctl.scala 2343:61] - node _T_2160 = not(_T_2159) @[dec_tlu_ctl.scala 2343:37] - node _T_2161 = bits(_T_2160, 0, 0) @[Bitwise.scala 72:15] - node _T_2162 = mux(_T_2161, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_2163 = bits(mhpme_vec[3], 9, 9) @[dec_tlu_ctl.scala 2343:104] - node _T_2164 = bits(mhpme_vec[2], 9, 9) @[dec_tlu_ctl.scala 2343:120] - node _T_2165 = bits(mhpme_vec[1], 9, 9) @[dec_tlu_ctl.scala 2343:136] - node _T_2166 = bits(mhpme_vec[0], 9, 9) @[dec_tlu_ctl.scala 2343:152] - node _T_2167 = cat(_T_2165, _T_2166) @[Cat.scala 29:58] - node _T_2168 = cat(_T_2163, _T_2164) @[Cat.scala 29:58] - node _T_2169 = cat(_T_2168, _T_2167) @[Cat.scala 29:58] - node perfcnt_during_sleep = and(_T_2162, _T_2169) @[dec_tlu_ctl.scala 2343:86] - node _T_2170 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2345:88] - node _T_2171 = not(_T_2170) @[dec_tlu_ctl.scala 2345:67] - node _T_2172 = and(perfcnt_halted_d1, _T_2171) @[dec_tlu_ctl.scala 2345:65] - node _T_2173 = not(_T_2172) @[dec_tlu_ctl.scala 2345:45] - node _T_2174 = and(mhpmc_inc_r_d1[0], _T_2173) @[dec_tlu_ctl.scala 2345:43] - io.dec_tlu_perfcnt0 <= _T_2174 @[dec_tlu_ctl.scala 2345:22] - node _T_2175 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2346:88] - node _T_2176 = not(_T_2175) @[dec_tlu_ctl.scala 2346:67] - node _T_2177 = and(perfcnt_halted_d1, _T_2176) @[dec_tlu_ctl.scala 2346:65] - node _T_2178 = not(_T_2177) @[dec_tlu_ctl.scala 2346:45] - node _T_2179 = and(mhpmc_inc_r_d1[1], _T_2178) @[dec_tlu_ctl.scala 2346:43] - io.dec_tlu_perfcnt1 <= _T_2179 @[dec_tlu_ctl.scala 2346:22] - node _T_2180 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2347:88] - node _T_2181 = not(_T_2180) @[dec_tlu_ctl.scala 2347:67] - node _T_2182 = and(perfcnt_halted_d1, _T_2181) @[dec_tlu_ctl.scala 2347:65] - node _T_2183 = not(_T_2182) @[dec_tlu_ctl.scala 2347:45] - node _T_2184 = and(mhpmc_inc_r_d1[2], _T_2183) @[dec_tlu_ctl.scala 2347:43] - io.dec_tlu_perfcnt2 <= _T_2184 @[dec_tlu_ctl.scala 2347:22] - node _T_2185 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2348:88] - node _T_2186 = not(_T_2185) @[dec_tlu_ctl.scala 2348:67] - node _T_2187 = and(perfcnt_halted_d1, _T_2186) @[dec_tlu_ctl.scala 2348:65] - node _T_2188 = not(_T_2187) @[dec_tlu_ctl.scala 2348:45] - node _T_2189 = and(mhpmc_inc_r_d1[3], _T_2188) @[dec_tlu_ctl.scala 2348:43] - io.dec_tlu_perfcnt3 <= _T_2189 @[dec_tlu_ctl.scala 2348:22] - node _T_2190 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2354:65] - node _T_2191 = eq(_T_2190, UInt<12>("h0b03")) @[dec_tlu_ctl.scala 2354:72] - node mhpmc3_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2191) @[dec_tlu_ctl.scala 2354:43] - node _T_2192 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2355:23] - node _T_2193 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2355:61] - node _T_2194 = or(_T_2192, _T_2193) @[dec_tlu_ctl.scala 2355:39] - node _T_2195 = orr(mhpmc_inc_r[0]) @[dec_tlu_ctl.scala 2355:86] - node mhpmc3_wr_en1 = and(_T_2194, _T_2195) @[dec_tlu_ctl.scala 2355:66] - node mhpmc3_wr_en = or(mhpmc3_wr_en0, mhpmc3_wr_en1) @[dec_tlu_ctl.scala 2356:36] - node _T_2196 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2359:28] - node _T_2197 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2359:41] - node _T_2198 = cat(_T_2196, _T_2197) @[Cat.scala 29:58] - node _T_2199 = cat(UInt<63>("h00"), mhpmc_inc_r[0]) @[Cat.scala 29:58] - node _T_2200 = add(_T_2198, _T_2199) @[dec_tlu_ctl.scala 2359:49] - node _T_2201 = tail(_T_2200, 1) @[dec_tlu_ctl.scala 2359:49] - mhpmc3_incr <= _T_2201 @[dec_tlu_ctl.scala 2359:14] - node _T_2202 = bits(mhpmc3_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2360:36] - node _T_2203 = bits(mhpmc3_incr, 31, 0) @[dec_tlu_ctl.scala 2360:76] - node mhpmc3_ns = mux(_T_2202, io.dec_csr_wrdata_r, _T_2203) @[dec_tlu_ctl.scala 2360:21] - node _T_2204 = bits(mhpmc3_wr_en, 0, 0) @[dec_tlu_ctl.scala 2362:42] + node _T_2149 = or(_T_2148, _T_2093) @[Mux.scala 27:72] + node _T_2150 = or(_T_2149, _T_2094) @[Mux.scala 27:72] + node _T_2151 = or(_T_2150, _T_2095) @[Mux.scala 27:72] + node _T_2152 = or(_T_2151, _T_2096) @[Mux.scala 27:72] + node _T_2153 = or(_T_2152, _T_2097) @[Mux.scala 27:72] + node _T_2154 = or(_T_2153, _T_2098) @[Mux.scala 27:72] + node _T_2155 = or(_T_2154, _T_2099) @[Mux.scala 27:72] + node _T_2156 = or(_T_2155, _T_2100) @[Mux.scala 27:72] + node _T_2157 = or(_T_2156, _T_2101) @[Mux.scala 27:72] + node _T_2158 = or(_T_2157, _T_2102) @[Mux.scala 27:72] + wire _T_2159 : UInt<1> @[Mux.scala 27:72] + _T_2159 <= _T_2158 @[Mux.scala 27:72] + node _T_2160 = and(_T_1878, _T_2159) @[dec_tlu_ctl.scala 2272:44] + mhpmc_inc_r[3] <= _T_2160 @[dec_tlu_ctl.scala 2272:19] + reg _T_2161 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2333:53] + _T_2161 <= mhpmc_inc_r[0] @[dec_tlu_ctl.scala 2333:53] + mhpmc_inc_r_d1[0] <= _T_2161 @[dec_tlu_ctl.scala 2333:20] + reg _T_2162 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2334:53] + _T_2162 <= mhpmc_inc_r[1] @[dec_tlu_ctl.scala 2334:53] + mhpmc_inc_r_d1[1] <= _T_2162 @[dec_tlu_ctl.scala 2334:20] + reg _T_2163 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2335:53] + _T_2163 <= mhpmc_inc_r[2] @[dec_tlu_ctl.scala 2335:53] + mhpmc_inc_r_d1[2] <= _T_2163 @[dec_tlu_ctl.scala 2335:20] + reg _T_2164 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2336:53] + _T_2164 <= mhpmc_inc_r[3] @[dec_tlu_ctl.scala 2336:53] + mhpmc_inc_r_d1[3] <= _T_2164 @[dec_tlu_ctl.scala 2336:20] + reg perfcnt_halted_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2337:56] + perfcnt_halted_d1 <= perfcnt_halted @[dec_tlu_ctl.scala 2337:56] + node _T_2165 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2340:53] + node _T_2166 = and(io.dec_tlu_dbg_halted, _T_2165) @[dec_tlu_ctl.scala 2340:44] + node _T_2167 = or(_T_2166, io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2340:67] + perfcnt_halted <= _T_2167 @[dec_tlu_ctl.scala 2340:17] + node _T_2168 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2341:70] + node _T_2169 = and(io.dec_tlu_dbg_halted, _T_2168) @[dec_tlu_ctl.scala 2341:61] + node _T_2170 = not(_T_2169) @[dec_tlu_ctl.scala 2341:37] + node _T_2171 = bits(_T_2170, 0, 0) @[Bitwise.scala 72:15] + node _T_2172 = mux(_T_2171, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_2173 = bits(mhpme_vec[3], 9, 9) @[dec_tlu_ctl.scala 2341:104] + node _T_2174 = bits(mhpme_vec[2], 9, 9) @[dec_tlu_ctl.scala 2341:120] + node _T_2175 = bits(mhpme_vec[1], 9, 9) @[dec_tlu_ctl.scala 2341:136] + node _T_2176 = bits(mhpme_vec[0], 9, 9) @[dec_tlu_ctl.scala 2341:152] + node _T_2177 = cat(_T_2175, _T_2176) @[Cat.scala 29:58] + node _T_2178 = cat(_T_2173, _T_2174) @[Cat.scala 29:58] + node _T_2179 = cat(_T_2178, _T_2177) @[Cat.scala 29:58] + node perfcnt_during_sleep = and(_T_2172, _T_2179) @[dec_tlu_ctl.scala 2341:86] + node _T_2180 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2343:88] + node _T_2181 = not(_T_2180) @[dec_tlu_ctl.scala 2343:67] + node _T_2182 = and(perfcnt_halted_d1, _T_2181) @[dec_tlu_ctl.scala 2343:65] + node _T_2183 = not(_T_2182) @[dec_tlu_ctl.scala 2343:45] + node _T_2184 = and(mhpmc_inc_r_d1[0], _T_2183) @[dec_tlu_ctl.scala 2343:43] + io.dec_tlu_perfcnt0 <= _T_2184 @[dec_tlu_ctl.scala 2343:22] + node _T_2185 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2344:88] + node _T_2186 = not(_T_2185) @[dec_tlu_ctl.scala 2344:67] + node _T_2187 = and(perfcnt_halted_d1, _T_2186) @[dec_tlu_ctl.scala 2344:65] + node _T_2188 = not(_T_2187) @[dec_tlu_ctl.scala 2344:45] + node _T_2189 = and(mhpmc_inc_r_d1[1], _T_2188) @[dec_tlu_ctl.scala 2344:43] + io.dec_tlu_perfcnt1 <= _T_2189 @[dec_tlu_ctl.scala 2344:22] + node _T_2190 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2345:88] + node _T_2191 = not(_T_2190) @[dec_tlu_ctl.scala 2345:67] + node _T_2192 = and(perfcnt_halted_d1, _T_2191) @[dec_tlu_ctl.scala 2345:65] + node _T_2193 = not(_T_2192) @[dec_tlu_ctl.scala 2345:45] + node _T_2194 = and(mhpmc_inc_r_d1[2], _T_2193) @[dec_tlu_ctl.scala 2345:43] + io.dec_tlu_perfcnt2 <= _T_2194 @[dec_tlu_ctl.scala 2345:22] + node _T_2195 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2346:88] + node _T_2196 = not(_T_2195) @[dec_tlu_ctl.scala 2346:67] + node _T_2197 = and(perfcnt_halted_d1, _T_2196) @[dec_tlu_ctl.scala 2346:65] + node _T_2198 = not(_T_2197) @[dec_tlu_ctl.scala 2346:45] + node _T_2199 = and(mhpmc_inc_r_d1[3], _T_2198) @[dec_tlu_ctl.scala 2346:43] + io.dec_tlu_perfcnt3 <= _T_2199 @[dec_tlu_ctl.scala 2346:22] + node _T_2200 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2352:65] + node _T_2201 = eq(_T_2200, UInt<12>("h0b03")) @[dec_tlu_ctl.scala 2352:72] + node mhpmc3_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2201) @[dec_tlu_ctl.scala 2352:43] + node _T_2202 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2353:23] + node _T_2203 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2353:61] + node _T_2204 = or(_T_2202, _T_2203) @[dec_tlu_ctl.scala 2353:39] + node _T_2205 = orr(mhpmc_inc_r[0]) @[dec_tlu_ctl.scala 2353:86] + node mhpmc3_wr_en1 = and(_T_2204, _T_2205) @[dec_tlu_ctl.scala 2353:66] + node mhpmc3_wr_en = or(mhpmc3_wr_en0, mhpmc3_wr_en1) @[dec_tlu_ctl.scala 2354:36] + node _T_2206 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2357:28] + node _T_2207 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2357:41] + node _T_2208 = cat(_T_2206, _T_2207) @[Cat.scala 29:58] + node _T_2209 = cat(UInt<63>("h00"), mhpmc_inc_r[0]) @[Cat.scala 29:58] + node _T_2210 = add(_T_2208, _T_2209) @[dec_tlu_ctl.scala 2357:49] + node _T_2211 = tail(_T_2210, 1) @[dec_tlu_ctl.scala 2357:49] + mhpmc3_incr <= _T_2211 @[dec_tlu_ctl.scala 2357:14] + node _T_2212 = bits(mhpmc3_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2358:36] + node _T_2213 = bits(mhpmc3_incr, 31, 0) @[dec_tlu_ctl.scala 2358:76] + node mhpmc3_ns = mux(_T_2212, io.dec_csr_wrdata_r, _T_2213) @[dec_tlu_ctl.scala 2358:21] + node _T_2214 = bits(mhpmc3_wr_en, 0, 0) @[dec_tlu_ctl.scala 2360:42] inst rvclkhdr_26 of rvclkhdr_746 @[lib.scala 368:23] rvclkhdr_26.clock <= clock rvclkhdr_26.reset <= reset rvclkhdr_26.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_26.io.en <= _T_2204 @[lib.scala 371:17] + rvclkhdr_26.io.en <= _T_2214 @[lib.scala 371:17] rvclkhdr_26.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2205 : UInt, rvclkhdr_26.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2205 <= mhpmc3_ns @[lib.scala 374:16] - mhpmc3 <= _T_2205 @[dec_tlu_ctl.scala 2362:9] - node _T_2206 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2364:66] - node _T_2207 = eq(_T_2206, UInt<12>("h0b83")) @[dec_tlu_ctl.scala 2364:73] - node mhpmc3h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2207) @[dec_tlu_ctl.scala 2364:44] - node mhpmc3h_wr_en = or(mhpmc3h_wr_en0, mhpmc3_wr_en1) @[dec_tlu_ctl.scala 2365:38] - node _T_2208 = bits(mhpmc3h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2366:38] - node _T_2209 = bits(mhpmc3_incr, 63, 32) @[dec_tlu_ctl.scala 2366:78] - node mhpmc3h_ns = mux(_T_2208, io.dec_csr_wrdata_r, _T_2209) @[dec_tlu_ctl.scala 2366:22] - node _T_2210 = bits(mhpmc3h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2368:46] + reg _T_2215 : UInt, rvclkhdr_26.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2215 <= mhpmc3_ns @[lib.scala 374:16] + mhpmc3 <= _T_2215 @[dec_tlu_ctl.scala 2360:9] + node _T_2216 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2362:66] + node _T_2217 = eq(_T_2216, UInt<12>("h0b83")) @[dec_tlu_ctl.scala 2362:73] + node mhpmc3h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2217) @[dec_tlu_ctl.scala 2362:44] + node mhpmc3h_wr_en = or(mhpmc3h_wr_en0, mhpmc3_wr_en1) @[dec_tlu_ctl.scala 2363:38] + node _T_2218 = bits(mhpmc3h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2364:38] + node _T_2219 = bits(mhpmc3_incr, 63, 32) @[dec_tlu_ctl.scala 2364:78] + node mhpmc3h_ns = mux(_T_2218, io.dec_csr_wrdata_r, _T_2219) @[dec_tlu_ctl.scala 2364:22] + node _T_2220 = bits(mhpmc3h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2366:46] inst rvclkhdr_27 of rvclkhdr_747 @[lib.scala 368:23] rvclkhdr_27.clock <= clock rvclkhdr_27.reset <= reset rvclkhdr_27.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_27.io.en <= _T_2210 @[lib.scala 371:17] + rvclkhdr_27.io.en <= _T_2220 @[lib.scala 371:17] rvclkhdr_27.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2211 : UInt, rvclkhdr_27.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2211 <= mhpmc3h_ns @[lib.scala 374:16] - mhpmc3h <= _T_2211 @[dec_tlu_ctl.scala 2368:10] - node _T_2212 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2373:65] - node _T_2213 = eq(_T_2212, UInt<12>("h0b04")) @[dec_tlu_ctl.scala 2373:72] - node mhpmc4_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2213) @[dec_tlu_ctl.scala 2373:43] - node _T_2214 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2374:23] - node _T_2215 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2374:61] - node _T_2216 = or(_T_2214, _T_2215) @[dec_tlu_ctl.scala 2374:39] - node _T_2217 = orr(mhpmc_inc_r[1]) @[dec_tlu_ctl.scala 2374:86] - node mhpmc4_wr_en1 = and(_T_2216, _T_2217) @[dec_tlu_ctl.scala 2374:66] - node mhpmc4_wr_en = or(mhpmc4_wr_en0, mhpmc4_wr_en1) @[dec_tlu_ctl.scala 2375:36] - node _T_2218 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2379:28] - node _T_2219 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2379:41] - node _T_2220 = cat(_T_2218, _T_2219) @[Cat.scala 29:58] - node _T_2221 = cat(UInt<63>("h00"), mhpmc_inc_r[1]) @[Cat.scala 29:58] - node _T_2222 = add(_T_2220, _T_2221) @[dec_tlu_ctl.scala 2379:49] - node _T_2223 = tail(_T_2222, 1) @[dec_tlu_ctl.scala 2379:49] - mhpmc4_incr <= _T_2223 @[dec_tlu_ctl.scala 2379:14] - node _T_2224 = bits(mhpmc4_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2380:36] - node _T_2225 = bits(io.dec_csr_wrdata_r, 31, 0) @[dec_tlu_ctl.scala 2380:63] - node _T_2226 = bits(mhpmc4_incr, 31, 0) @[dec_tlu_ctl.scala 2380:82] - node mhpmc4_ns = mux(_T_2224, _T_2225, _T_2226) @[dec_tlu_ctl.scala 2380:21] - node _T_2227 = bits(mhpmc4_wr_en, 0, 0) @[dec_tlu_ctl.scala 2381:43] + reg _T_2221 : UInt, rvclkhdr_27.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2221 <= mhpmc3h_ns @[lib.scala 374:16] + mhpmc3h <= _T_2221 @[dec_tlu_ctl.scala 2366:10] + node _T_2222 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2371:65] + node _T_2223 = eq(_T_2222, UInt<12>("h0b04")) @[dec_tlu_ctl.scala 2371:72] + node mhpmc4_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2223) @[dec_tlu_ctl.scala 2371:43] + node _T_2224 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2372:23] + node _T_2225 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2372:61] + node _T_2226 = or(_T_2224, _T_2225) @[dec_tlu_ctl.scala 2372:39] + node _T_2227 = orr(mhpmc_inc_r[1]) @[dec_tlu_ctl.scala 2372:86] + node mhpmc4_wr_en1 = and(_T_2226, _T_2227) @[dec_tlu_ctl.scala 2372:66] + node mhpmc4_wr_en = or(mhpmc4_wr_en0, mhpmc4_wr_en1) @[dec_tlu_ctl.scala 2373:36] + node _T_2228 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2377:28] + node _T_2229 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2377:41] + node _T_2230 = cat(_T_2228, _T_2229) @[Cat.scala 29:58] + node _T_2231 = cat(UInt<63>("h00"), mhpmc_inc_r[1]) @[Cat.scala 29:58] + node _T_2232 = add(_T_2230, _T_2231) @[dec_tlu_ctl.scala 2377:49] + node _T_2233 = tail(_T_2232, 1) @[dec_tlu_ctl.scala 2377:49] + mhpmc4_incr <= _T_2233 @[dec_tlu_ctl.scala 2377:14] + node _T_2234 = bits(mhpmc4_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2378:36] + node _T_2235 = bits(io.dec_csr_wrdata_r, 31, 0) @[dec_tlu_ctl.scala 2378:63] + node _T_2236 = bits(mhpmc4_incr, 31, 0) @[dec_tlu_ctl.scala 2378:82] + node mhpmc4_ns = mux(_T_2234, _T_2235, _T_2236) @[dec_tlu_ctl.scala 2378:21] + node _T_2237 = bits(mhpmc4_wr_en, 0, 0) @[dec_tlu_ctl.scala 2379:43] inst rvclkhdr_28 of rvclkhdr_748 @[lib.scala 368:23] rvclkhdr_28.clock <= clock rvclkhdr_28.reset <= reset rvclkhdr_28.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_28.io.en <= _T_2227 @[lib.scala 371:17] + rvclkhdr_28.io.en <= _T_2237 @[lib.scala 371:17] rvclkhdr_28.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2228 : UInt, rvclkhdr_28.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2228 <= mhpmc4_ns @[lib.scala 374:16] - mhpmc4 <= _T_2228 @[dec_tlu_ctl.scala 2381:9] - node _T_2229 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2383:66] - node _T_2230 = eq(_T_2229, UInt<12>("h0b84")) @[dec_tlu_ctl.scala 2383:73] - node mhpmc4h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2230) @[dec_tlu_ctl.scala 2383:44] - node mhpmc4h_wr_en = or(mhpmc4h_wr_en0, mhpmc4_wr_en1) @[dec_tlu_ctl.scala 2384:38] - node _T_2231 = bits(mhpmc4h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2385:38] - node _T_2232 = bits(mhpmc4_incr, 63, 32) @[dec_tlu_ctl.scala 2385:78] - node mhpmc4h_ns = mux(_T_2231, io.dec_csr_wrdata_r, _T_2232) @[dec_tlu_ctl.scala 2385:22] - node _T_2233 = bits(mhpmc4h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2386:46] + reg _T_2238 : UInt, rvclkhdr_28.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2238 <= mhpmc4_ns @[lib.scala 374:16] + mhpmc4 <= _T_2238 @[dec_tlu_ctl.scala 2379:9] + node _T_2239 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2381:66] + node _T_2240 = eq(_T_2239, UInt<12>("h0b84")) @[dec_tlu_ctl.scala 2381:73] + node mhpmc4h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2240) @[dec_tlu_ctl.scala 2381:44] + node mhpmc4h_wr_en = or(mhpmc4h_wr_en0, mhpmc4_wr_en1) @[dec_tlu_ctl.scala 2382:38] + node _T_2241 = bits(mhpmc4h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2383:38] + node _T_2242 = bits(mhpmc4_incr, 63, 32) @[dec_tlu_ctl.scala 2383:78] + node mhpmc4h_ns = mux(_T_2241, io.dec_csr_wrdata_r, _T_2242) @[dec_tlu_ctl.scala 2383:22] + node _T_2243 = bits(mhpmc4h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2384:46] inst rvclkhdr_29 of rvclkhdr_749 @[lib.scala 368:23] rvclkhdr_29.clock <= clock rvclkhdr_29.reset <= reset rvclkhdr_29.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_29.io.en <= _T_2233 @[lib.scala 371:17] + rvclkhdr_29.io.en <= _T_2243 @[lib.scala 371:17] rvclkhdr_29.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2234 : UInt, rvclkhdr_29.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2234 <= mhpmc4h_ns @[lib.scala 374:16] - mhpmc4h <= _T_2234 @[dec_tlu_ctl.scala 2386:10] - node _T_2235 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2392:65] - node _T_2236 = eq(_T_2235, UInt<12>("h0b05")) @[dec_tlu_ctl.scala 2392:72] - node mhpmc5_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2236) @[dec_tlu_ctl.scala 2392:43] - node _T_2237 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2393:23] - node _T_2238 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2393:61] - node _T_2239 = or(_T_2237, _T_2238) @[dec_tlu_ctl.scala 2393:39] - node _T_2240 = orr(mhpmc_inc_r[2]) @[dec_tlu_ctl.scala 2393:86] - node mhpmc5_wr_en1 = and(_T_2239, _T_2240) @[dec_tlu_ctl.scala 2393:66] - node mhpmc5_wr_en = or(mhpmc5_wr_en0, mhpmc5_wr_en1) @[dec_tlu_ctl.scala 2394:36] - node _T_2241 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2396:28] - node _T_2242 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2396:41] - node _T_2243 = cat(_T_2241, _T_2242) @[Cat.scala 29:58] - node _T_2244 = cat(UInt<63>("h00"), mhpmc_inc_r[2]) @[Cat.scala 29:58] - node _T_2245 = add(_T_2243, _T_2244) @[dec_tlu_ctl.scala 2396:49] - node _T_2246 = tail(_T_2245, 1) @[dec_tlu_ctl.scala 2396:49] - mhpmc5_incr <= _T_2246 @[dec_tlu_ctl.scala 2396:14] - node _T_2247 = bits(mhpmc5_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2397:36] - node _T_2248 = bits(mhpmc5_incr, 31, 0) @[dec_tlu_ctl.scala 2397:76] - node mhpmc5_ns = mux(_T_2247, io.dec_csr_wrdata_r, _T_2248) @[dec_tlu_ctl.scala 2397:21] - node _T_2249 = bits(mhpmc5_wr_en, 0, 0) @[dec_tlu_ctl.scala 2399:43] + reg _T_2244 : UInt, rvclkhdr_29.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2244 <= mhpmc4h_ns @[lib.scala 374:16] + mhpmc4h <= _T_2244 @[dec_tlu_ctl.scala 2384:10] + node _T_2245 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2390:65] + node _T_2246 = eq(_T_2245, UInt<12>("h0b05")) @[dec_tlu_ctl.scala 2390:72] + node mhpmc5_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2246) @[dec_tlu_ctl.scala 2390:43] + node _T_2247 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2391:23] + node _T_2248 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2391:61] + node _T_2249 = or(_T_2247, _T_2248) @[dec_tlu_ctl.scala 2391:39] + node _T_2250 = orr(mhpmc_inc_r[2]) @[dec_tlu_ctl.scala 2391:86] + node mhpmc5_wr_en1 = and(_T_2249, _T_2250) @[dec_tlu_ctl.scala 2391:66] + node mhpmc5_wr_en = or(mhpmc5_wr_en0, mhpmc5_wr_en1) @[dec_tlu_ctl.scala 2392:36] + node _T_2251 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2394:28] + node _T_2252 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2394:41] + node _T_2253 = cat(_T_2251, _T_2252) @[Cat.scala 29:58] + node _T_2254 = cat(UInt<63>("h00"), mhpmc_inc_r[2]) @[Cat.scala 29:58] + node _T_2255 = add(_T_2253, _T_2254) @[dec_tlu_ctl.scala 2394:49] + node _T_2256 = tail(_T_2255, 1) @[dec_tlu_ctl.scala 2394:49] + mhpmc5_incr <= _T_2256 @[dec_tlu_ctl.scala 2394:14] + node _T_2257 = bits(mhpmc5_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2395:36] + node _T_2258 = bits(mhpmc5_incr, 31, 0) @[dec_tlu_ctl.scala 2395:76] + node mhpmc5_ns = mux(_T_2257, io.dec_csr_wrdata_r, _T_2258) @[dec_tlu_ctl.scala 2395:21] + node _T_2259 = bits(mhpmc5_wr_en, 0, 0) @[dec_tlu_ctl.scala 2397:43] inst rvclkhdr_30 of rvclkhdr_750 @[lib.scala 368:23] rvclkhdr_30.clock <= clock rvclkhdr_30.reset <= reset rvclkhdr_30.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_30.io.en <= _T_2249 @[lib.scala 371:17] + rvclkhdr_30.io.en <= _T_2259 @[lib.scala 371:17] rvclkhdr_30.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2250 : UInt, rvclkhdr_30.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2250 <= mhpmc5_ns @[lib.scala 374:16] - mhpmc5 <= _T_2250 @[dec_tlu_ctl.scala 2399:9] - node _T_2251 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2401:66] - node _T_2252 = eq(_T_2251, UInt<12>("h0b85")) @[dec_tlu_ctl.scala 2401:73] - node mhpmc5h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2252) @[dec_tlu_ctl.scala 2401:44] - node mhpmc5h_wr_en = or(mhpmc5h_wr_en0, mhpmc5_wr_en1) @[dec_tlu_ctl.scala 2402:38] - node _T_2253 = bits(mhpmc5h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2403:38] - node _T_2254 = bits(mhpmc5_incr, 63, 32) @[dec_tlu_ctl.scala 2403:78] - node mhpmc5h_ns = mux(_T_2253, io.dec_csr_wrdata_r, _T_2254) @[dec_tlu_ctl.scala 2403:22] - node _T_2255 = bits(mhpmc5h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2405:46] + reg _T_2260 : UInt, rvclkhdr_30.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2260 <= mhpmc5_ns @[lib.scala 374:16] + mhpmc5 <= _T_2260 @[dec_tlu_ctl.scala 2397:9] + node _T_2261 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2399:66] + node _T_2262 = eq(_T_2261, UInt<12>("h0b85")) @[dec_tlu_ctl.scala 2399:73] + node mhpmc5h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2262) @[dec_tlu_ctl.scala 2399:44] + node mhpmc5h_wr_en = or(mhpmc5h_wr_en0, mhpmc5_wr_en1) @[dec_tlu_ctl.scala 2400:38] + node _T_2263 = bits(mhpmc5h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2401:38] + node _T_2264 = bits(mhpmc5_incr, 63, 32) @[dec_tlu_ctl.scala 2401:78] + node mhpmc5h_ns = mux(_T_2263, io.dec_csr_wrdata_r, _T_2264) @[dec_tlu_ctl.scala 2401:22] + node _T_2265 = bits(mhpmc5h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2403:46] inst rvclkhdr_31 of rvclkhdr_751 @[lib.scala 368:23] rvclkhdr_31.clock <= clock rvclkhdr_31.reset <= reset rvclkhdr_31.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_31.io.en <= _T_2255 @[lib.scala 371:17] + rvclkhdr_31.io.en <= _T_2265 @[lib.scala 371:17] rvclkhdr_31.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2256 : UInt, rvclkhdr_31.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2256 <= mhpmc5h_ns @[lib.scala 374:16] - mhpmc5h <= _T_2256 @[dec_tlu_ctl.scala 2405:10] - node _T_2257 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2410:65] - node _T_2258 = eq(_T_2257, UInt<12>("h0b06")) @[dec_tlu_ctl.scala 2410:72] - node mhpmc6_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2258) @[dec_tlu_ctl.scala 2410:43] - node _T_2259 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2411:23] - node _T_2260 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2411:61] - node _T_2261 = or(_T_2259, _T_2260) @[dec_tlu_ctl.scala 2411:39] - node _T_2262 = orr(mhpmc_inc_r[3]) @[dec_tlu_ctl.scala 2411:86] - node mhpmc6_wr_en1 = and(_T_2261, _T_2262) @[dec_tlu_ctl.scala 2411:66] - node mhpmc6_wr_en = or(mhpmc6_wr_en0, mhpmc6_wr_en1) @[dec_tlu_ctl.scala 2412:36] - node _T_2263 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2414:28] - node _T_2264 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2414:41] - node _T_2265 = cat(_T_2263, _T_2264) @[Cat.scala 29:58] - node _T_2266 = cat(UInt<63>("h00"), mhpmc_inc_r[3]) @[Cat.scala 29:58] - node _T_2267 = add(_T_2265, _T_2266) @[dec_tlu_ctl.scala 2414:49] - node _T_2268 = tail(_T_2267, 1) @[dec_tlu_ctl.scala 2414:49] - mhpmc6_incr <= _T_2268 @[dec_tlu_ctl.scala 2414:14] - node _T_2269 = bits(mhpmc6_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2415:36] - node _T_2270 = bits(mhpmc6_incr, 31, 0) @[dec_tlu_ctl.scala 2415:76] - node mhpmc6_ns = mux(_T_2269, io.dec_csr_wrdata_r, _T_2270) @[dec_tlu_ctl.scala 2415:21] - node _T_2271 = bits(mhpmc6_wr_en, 0, 0) @[dec_tlu_ctl.scala 2417:43] + reg _T_2266 : UInt, rvclkhdr_31.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2266 <= mhpmc5h_ns @[lib.scala 374:16] + mhpmc5h <= _T_2266 @[dec_tlu_ctl.scala 2403:10] + node _T_2267 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2408:65] + node _T_2268 = eq(_T_2267, UInt<12>("h0b06")) @[dec_tlu_ctl.scala 2408:72] + node mhpmc6_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2268) @[dec_tlu_ctl.scala 2408:43] + node _T_2269 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2409:23] + node _T_2270 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2409:61] + node _T_2271 = or(_T_2269, _T_2270) @[dec_tlu_ctl.scala 2409:39] + node _T_2272 = orr(mhpmc_inc_r[3]) @[dec_tlu_ctl.scala 2409:86] + node mhpmc6_wr_en1 = and(_T_2271, _T_2272) @[dec_tlu_ctl.scala 2409:66] + node mhpmc6_wr_en = or(mhpmc6_wr_en0, mhpmc6_wr_en1) @[dec_tlu_ctl.scala 2410:36] + node _T_2273 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2412:28] + node _T_2274 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2412:41] + node _T_2275 = cat(_T_2273, _T_2274) @[Cat.scala 29:58] + node _T_2276 = cat(UInt<63>("h00"), mhpmc_inc_r[3]) @[Cat.scala 29:58] + node _T_2277 = add(_T_2275, _T_2276) @[dec_tlu_ctl.scala 2412:49] + node _T_2278 = tail(_T_2277, 1) @[dec_tlu_ctl.scala 2412:49] + mhpmc6_incr <= _T_2278 @[dec_tlu_ctl.scala 2412:14] + node _T_2279 = bits(mhpmc6_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2413:36] + node _T_2280 = bits(mhpmc6_incr, 31, 0) @[dec_tlu_ctl.scala 2413:76] + node mhpmc6_ns = mux(_T_2279, io.dec_csr_wrdata_r, _T_2280) @[dec_tlu_ctl.scala 2413:21] + node _T_2281 = bits(mhpmc6_wr_en, 0, 0) @[dec_tlu_ctl.scala 2415:43] inst rvclkhdr_32 of rvclkhdr_752 @[lib.scala 368:23] rvclkhdr_32.clock <= clock rvclkhdr_32.reset <= reset rvclkhdr_32.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_32.io.en <= _T_2271 @[lib.scala 371:17] + rvclkhdr_32.io.en <= _T_2281 @[lib.scala 371:17] rvclkhdr_32.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2272 : UInt, rvclkhdr_32.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2272 <= mhpmc6_ns @[lib.scala 374:16] - mhpmc6 <= _T_2272 @[dec_tlu_ctl.scala 2417:9] - node _T_2273 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2419:66] - node _T_2274 = eq(_T_2273, UInt<12>("h0b86")) @[dec_tlu_ctl.scala 2419:73] - node mhpmc6h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2274) @[dec_tlu_ctl.scala 2419:44] - node mhpmc6h_wr_en = or(mhpmc6h_wr_en0, mhpmc6_wr_en1) @[dec_tlu_ctl.scala 2420:38] - node _T_2275 = bits(mhpmc6h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2421:38] - node _T_2276 = bits(mhpmc6_incr, 63, 32) @[dec_tlu_ctl.scala 2421:78] - node mhpmc6h_ns = mux(_T_2275, io.dec_csr_wrdata_r, _T_2276) @[dec_tlu_ctl.scala 2421:22] - node _T_2277 = bits(mhpmc6h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2423:46] + reg _T_2282 : UInt, rvclkhdr_32.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2282 <= mhpmc6_ns @[lib.scala 374:16] + mhpmc6 <= _T_2282 @[dec_tlu_ctl.scala 2415:9] + node _T_2283 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2417:66] + node _T_2284 = eq(_T_2283, UInt<12>("h0b86")) @[dec_tlu_ctl.scala 2417:73] + node mhpmc6h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2284) @[dec_tlu_ctl.scala 2417:44] + node mhpmc6h_wr_en = or(mhpmc6h_wr_en0, mhpmc6_wr_en1) @[dec_tlu_ctl.scala 2418:38] + node _T_2285 = bits(mhpmc6h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2419:38] + node _T_2286 = bits(mhpmc6_incr, 63, 32) @[dec_tlu_ctl.scala 2419:78] + node mhpmc6h_ns = mux(_T_2285, io.dec_csr_wrdata_r, _T_2286) @[dec_tlu_ctl.scala 2419:22] + node _T_2287 = bits(mhpmc6h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2421:46] inst rvclkhdr_33 of rvclkhdr_753 @[lib.scala 368:23] rvclkhdr_33.clock <= clock rvclkhdr_33.reset <= reset rvclkhdr_33.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_33.io.en <= _T_2277 @[lib.scala 371:17] + rvclkhdr_33.io.en <= _T_2287 @[lib.scala 371:17] rvclkhdr_33.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2278 : UInt, rvclkhdr_33.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2278 <= mhpmc6h_ns @[lib.scala 374:16] - mhpmc6h <= _T_2278 @[dec_tlu_ctl.scala 2423:10] - node _T_2279 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2430:50] - node _T_2280 = gt(_T_2279, UInt<10>("h0204")) @[dec_tlu_ctl.scala 2430:56] - node _T_2281 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 2430:93] - node _T_2282 = orr(_T_2281) @[dec_tlu_ctl.scala 2430:102] - node _T_2283 = or(_T_2280, _T_2282) @[dec_tlu_ctl.scala 2430:71] - node _T_2284 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2430:141] - node event_saturate_r = mux(_T_2283, UInt<10>("h0204"), _T_2284) @[dec_tlu_ctl.scala 2430:28] - node _T_2285 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2432:63] - node _T_2286 = eq(_T_2285, UInt<12>("h0323")) @[dec_tlu_ctl.scala 2432:70] - node wr_mhpme3_r = and(io.dec_csr_wen_r_mod, _T_2286) @[dec_tlu_ctl.scala 2432:41] - node _T_2287 = bits(wr_mhpme3_r, 0, 0) @[dec_tlu_ctl.scala 2434:80] - reg _T_2288 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2287 : @[Reg.scala 28:19] - _T_2288 <= event_saturate_r @[Reg.scala 28:23] + reg _T_2288 : UInt, rvclkhdr_33.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2288 <= mhpmc6h_ns @[lib.scala 374:16] + mhpmc6h <= _T_2288 @[dec_tlu_ctl.scala 2421:10] + node _T_2289 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2428:50] + node _T_2290 = gt(_T_2289, UInt<10>("h0204")) @[dec_tlu_ctl.scala 2428:56] + node _T_2291 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 2428:93] + node _T_2292 = orr(_T_2291) @[dec_tlu_ctl.scala 2428:102] + node _T_2293 = or(_T_2290, _T_2292) @[dec_tlu_ctl.scala 2428:71] + node _T_2294 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2428:141] + node event_saturate_r = mux(_T_2293, UInt<10>("h0204"), _T_2294) @[dec_tlu_ctl.scala 2428:28] + node _T_2295 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2430:63] + node _T_2296 = eq(_T_2295, UInt<12>("h0323")) @[dec_tlu_ctl.scala 2430:70] + node wr_mhpme3_r = and(io.dec_csr_wen_r_mod, _T_2296) @[dec_tlu_ctl.scala 2430:41] + node _T_2297 = bits(wr_mhpme3_r, 0, 0) @[dec_tlu_ctl.scala 2432:80] + reg _T_2298 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2297 : @[Reg.scala 28:19] + _T_2298 <= event_saturate_r @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mhpme3 <= _T_2288 @[dec_tlu_ctl.scala 2434:9] - node _T_2289 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2439:63] - node _T_2290 = eq(_T_2289, UInt<12>("h0324")) @[dec_tlu_ctl.scala 2439:70] - node wr_mhpme4_r = and(io.dec_csr_wen_r_mod, _T_2290) @[dec_tlu_ctl.scala 2439:41] - node _T_2291 = bits(wr_mhpme4_r, 0, 0) @[dec_tlu_ctl.scala 2440:80] - reg _T_2292 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2291 : @[Reg.scala 28:19] - _T_2292 <= event_saturate_r @[Reg.scala 28:23] + mhpme3 <= _T_2298 @[dec_tlu_ctl.scala 2432:9] + node _T_2299 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2437:63] + node _T_2300 = eq(_T_2299, UInt<12>("h0324")) @[dec_tlu_ctl.scala 2437:70] + node wr_mhpme4_r = and(io.dec_csr_wen_r_mod, _T_2300) @[dec_tlu_ctl.scala 2437:41] + node _T_2301 = bits(wr_mhpme4_r, 0, 0) @[dec_tlu_ctl.scala 2438:80] + reg _T_2302 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2301 : @[Reg.scala 28:19] + _T_2302 <= event_saturate_r @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mhpme4 <= _T_2292 @[dec_tlu_ctl.scala 2440:9] - node _T_2293 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2446:63] - node _T_2294 = eq(_T_2293, UInt<12>("h0325")) @[dec_tlu_ctl.scala 2446:70] - node wr_mhpme5_r = and(io.dec_csr_wen_r_mod, _T_2294) @[dec_tlu_ctl.scala 2446:41] - node _T_2295 = bits(wr_mhpme5_r, 0, 0) @[dec_tlu_ctl.scala 2447:80] - reg _T_2296 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2295 : @[Reg.scala 28:19] - _T_2296 <= event_saturate_r @[Reg.scala 28:23] + mhpme4 <= _T_2302 @[dec_tlu_ctl.scala 2438:9] + node _T_2303 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2444:63] + node _T_2304 = eq(_T_2303, UInt<12>("h0325")) @[dec_tlu_ctl.scala 2444:70] + node wr_mhpme5_r = and(io.dec_csr_wen_r_mod, _T_2304) @[dec_tlu_ctl.scala 2444:41] + node _T_2305 = bits(wr_mhpme5_r, 0, 0) @[dec_tlu_ctl.scala 2445:80] + reg _T_2306 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2305 : @[Reg.scala 28:19] + _T_2306 <= event_saturate_r @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mhpme5 <= _T_2296 @[dec_tlu_ctl.scala 2447:9] - node _T_2297 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2453:63] - node _T_2298 = eq(_T_2297, UInt<12>("h0326")) @[dec_tlu_ctl.scala 2453:70] - node wr_mhpme6_r = and(io.dec_csr_wen_r_mod, _T_2298) @[dec_tlu_ctl.scala 2453:41] - node _T_2299 = bits(wr_mhpme6_r, 0, 0) @[dec_tlu_ctl.scala 2454:80] - reg _T_2300 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2299 : @[Reg.scala 28:19] - _T_2300 <= event_saturate_r @[Reg.scala 28:23] + mhpme5 <= _T_2306 @[dec_tlu_ctl.scala 2445:9] + node _T_2307 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2451:63] + node _T_2308 = eq(_T_2307, UInt<12>("h0326")) @[dec_tlu_ctl.scala 2451:70] + node wr_mhpme6_r = and(io.dec_csr_wen_r_mod, _T_2308) @[dec_tlu_ctl.scala 2451:41] + node _T_2309 = bits(wr_mhpme6_r, 0, 0) @[dec_tlu_ctl.scala 2452:80] + reg _T_2310 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2309 : @[Reg.scala 28:19] + _T_2310 <= event_saturate_r @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mhpme6 <= _T_2300 @[dec_tlu_ctl.scala 2454:9] - node _T_2301 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2470:70] - node _T_2302 = eq(_T_2301, UInt<12>("h0320")) @[dec_tlu_ctl.scala 2470:77] - node wr_mcountinhibit_r = and(io.dec_csr_wen_r_mod, _T_2302) @[dec_tlu_ctl.scala 2470:48] - node _T_2303 = bits(mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2472:54] + mhpme6 <= _T_2310 @[dec_tlu_ctl.scala 2452:9] + node _T_2311 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2468:70] + node _T_2312 = eq(_T_2311, UInt<12>("h0320")) @[dec_tlu_ctl.scala 2468:77] + node wr_mcountinhibit_r = and(io.dec_csr_wen_r_mod, _T_2312) @[dec_tlu_ctl.scala 2468:48] + node _T_2313 = bits(mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2470:54] wire temp_ncount0 : UInt<1> - temp_ncount0 <= _T_2303 - node _T_2304 = bits(mcountinhibit, 1, 1) @[dec_tlu_ctl.scala 2473:54] + temp_ncount0 <= _T_2313 + node _T_2314 = bits(mcountinhibit, 1, 1) @[dec_tlu_ctl.scala 2471:54] wire temp_ncount1 : UInt<1> - temp_ncount1 <= _T_2304 - node _T_2305 = bits(mcountinhibit, 6, 2) @[dec_tlu_ctl.scala 2474:55] + temp_ncount1 <= _T_2314 + node _T_2315 = bits(mcountinhibit, 6, 2) @[dec_tlu_ctl.scala 2472:55] wire temp_ncount6_2 : UInt<5> - temp_ncount6_2 <= _T_2305 - node _T_2306 = bits(io.dec_csr_wrdata_r, 6, 2) @[dec_tlu_ctl.scala 2475:74] - node _T_2307 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2475:103] - reg _T_2308 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2307 : @[Reg.scala 28:19] - _T_2308 <= _T_2306 @[Reg.scala 28:23] + temp_ncount6_2 <= _T_2315 + node _T_2316 = bits(io.dec_csr_wrdata_r, 6, 2) @[dec_tlu_ctl.scala 2473:74] + node _T_2317 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2473:103] + reg _T_2318 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2317 : @[Reg.scala 28:19] + _T_2318 <= _T_2316 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - temp_ncount6_2 <= _T_2308 @[dec_tlu_ctl.scala 2475:17] - node _T_2309 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2477:72] - node _T_2310 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2477:99] - reg _T_2311 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2310 : @[Reg.scala 28:19] - _T_2311 <= _T_2309 @[Reg.scala 28:23] + temp_ncount6_2 <= _T_2318 @[dec_tlu_ctl.scala 2473:17] + node _T_2319 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2475:72] + node _T_2320 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2475:99] + reg _T_2321 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2320 : @[Reg.scala 28:19] + _T_2321 <= _T_2319 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - temp_ncount0 <= _T_2311 @[dec_tlu_ctl.scala 2477:15] - node _T_2312 = cat(temp_ncount6_2, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2313 = cat(_T_2312, temp_ncount0) @[Cat.scala 29:58] - mcountinhibit <= _T_2313 @[dec_tlu_ctl.scala 2478:16] - node _T_2314 = or(io.i0_valid_wb, io.exc_or_int_valid_r_d1) @[dec_tlu_ctl.scala 2485:51] - node _T_2315 = or(_T_2314, io.interrupt_valid_r_d1) @[dec_tlu_ctl.scala 2485:78] - node _T_2316 = or(_T_2315, io.dec_tlu_i0_valid_wb1) @[dec_tlu_ctl.scala 2485:104] - node _T_2317 = or(_T_2316, io.dec_tlu_i0_exc_valid_wb1) @[dec_tlu_ctl.scala 2485:130] - node _T_2318 = or(_T_2317, io.dec_tlu_int_valid_wb1) @[dec_tlu_ctl.scala 2486:32] - node _T_2319 = or(_T_2318, io.clk_override) @[dec_tlu_ctl.scala 2486:59] - node _T_2320 = bits(_T_2319, 0, 0) @[dec_tlu_ctl.scala 2486:78] + temp_ncount0 <= _T_2321 @[dec_tlu_ctl.scala 2475:15] + node _T_2322 = cat(temp_ncount6_2, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2323 = cat(_T_2322, temp_ncount0) @[Cat.scala 29:58] + mcountinhibit <= _T_2323 @[dec_tlu_ctl.scala 2476:16] + node _T_2324 = or(io.i0_valid_wb, io.exc_or_int_valid_r_d1) @[dec_tlu_ctl.scala 2483:51] + node _T_2325 = or(_T_2324, io.interrupt_valid_r_d1) @[dec_tlu_ctl.scala 2483:78] + node _T_2326 = or(_T_2325, io.dec_tlu_i0_valid_wb1) @[dec_tlu_ctl.scala 2483:104] + node _T_2327 = or(_T_2326, io.dec_tlu_i0_exc_valid_wb1) @[dec_tlu_ctl.scala 2483:130] + node _T_2328 = or(_T_2327, io.dec_tlu_int_valid_wb1) @[dec_tlu_ctl.scala 2484:32] + node _T_2329 = or(_T_2328, io.clk_override) @[dec_tlu_ctl.scala 2484:59] + node _T_2330 = bits(_T_2329, 0, 0) @[dec_tlu_ctl.scala 2484:78] inst rvclkhdr_34 of rvclkhdr_754 @[lib.scala 343:22] rvclkhdr_34.clock <= clock rvclkhdr_34.reset <= reset rvclkhdr_34.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_34.io.en <= _T_2320 @[lib.scala 345:16] + rvclkhdr_34.io.en <= _T_2330 @[lib.scala 345:16] rvclkhdr_34.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - reg _T_2321 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2488:62] - _T_2321 <= io.i0_valid_wb @[dec_tlu_ctl.scala 2488:62] - io.dec_tlu_i0_valid_wb1 <= _T_2321 @[dec_tlu_ctl.scala 2488:30] - node _T_2322 = or(io.i0_exception_valid_r_d1, io.lsu_i0_exc_r_d1) @[dec_tlu_ctl.scala 2489:91] - node _T_2323 = not(io.trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 2489:137] - node _T_2324 = and(io.trigger_hit_r_d1, _T_2323) @[dec_tlu_ctl.scala 2489:135] - node _T_2325 = or(_T_2322, _T_2324) @[dec_tlu_ctl.scala 2489:112] - reg _T_2326 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2489:62] - _T_2326 <= _T_2325 @[dec_tlu_ctl.scala 2489:62] - io.dec_tlu_i0_exc_valid_wb1 <= _T_2326 @[dec_tlu_ctl.scala 2489:30] - reg _T_2327 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2490:62] - _T_2327 <= io.exc_cause_wb @[dec_tlu_ctl.scala 2490:62] - io.dec_tlu_exc_cause_wb1 <= _T_2327 @[dec_tlu_ctl.scala 2490:30] - reg _T_2328 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2491:62] - _T_2328 <= io.interrupt_valid_r_d1 @[dec_tlu_ctl.scala 2491:62] - io.dec_tlu_int_valid_wb1 <= _T_2328 @[dec_tlu_ctl.scala 2491:30] - io.dec_tlu_mtval_wb1 <= mtval @[dec_tlu_ctl.scala 2493:24] - node _T_2329 = bits(io.csr_pkt.csr_misa, 0, 0) @[dec_tlu_ctl.scala 2499:61] - node _T_2330 = bits(io.csr_pkt.csr_mvendorid, 0, 0) @[dec_tlu_ctl.scala 2500:42] - node _T_2331 = bits(io.csr_pkt.csr_marchid, 0, 0) @[dec_tlu_ctl.scala 2501:40] - node _T_2332 = bits(io.csr_pkt.csr_mimpid, 0, 0) @[dec_tlu_ctl.scala 2502:39] - node _T_2333 = bits(io.csr_pkt.csr_mhartid, 0, 0) @[dec_tlu_ctl.scala 2503:40] - node _T_2334 = cat(io.core_id, UInt<4>("h00")) @[Cat.scala 29:58] - node _T_2335 = bits(io.csr_pkt.csr_mstatus, 0, 0) @[dec_tlu_ctl.scala 2504:40] - node _T_2336 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 2504:103] - node _T_2337 = bits(io.mstatus, 0, 0) @[dec_tlu_ctl.scala 2504:128] - node _T_2338 = cat(UInt<3>("h00"), _T_2337) @[Cat.scala 29:58] - node _T_2339 = cat(_T_2338, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2340 = cat(UInt<3>("h00"), _T_2336) @[Cat.scala 29:58] - node _T_2341 = cat(UInt<19>("h00"), UInt<2>("h03")) @[Cat.scala 29:58] - node _T_2342 = cat(_T_2341, _T_2340) @[Cat.scala 29:58] - node _T_2343 = cat(_T_2342, _T_2339) @[Cat.scala 29:58] - node _T_2344 = bits(io.csr_pkt.csr_mtvec, 0, 0) @[dec_tlu_ctl.scala 2505:38] - node _T_2345 = bits(io.mtvec, 30, 1) @[dec_tlu_ctl.scala 2505:70] - node _T_2346 = bits(io.mtvec, 0, 0) @[dec_tlu_ctl.scala 2505:96] - node _T_2347 = cat(_T_2345, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2348 = cat(_T_2347, _T_2346) @[Cat.scala 29:58] - node _T_2349 = bits(io.csr_pkt.csr_mip, 0, 0) @[dec_tlu_ctl.scala 2506:36] - node _T_2350 = bits(io.mip, 5, 3) @[dec_tlu_ctl.scala 2506:78] - node _T_2351 = bits(io.mip, 2, 2) @[dec_tlu_ctl.scala 2506:102] - node _T_2352 = bits(io.mip, 1, 1) @[dec_tlu_ctl.scala 2506:123] - node _T_2353 = bits(io.mip, 0, 0) @[dec_tlu_ctl.scala 2506:144] - node _T_2354 = cat(_T_2353, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2355 = cat(_T_2352, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2356 = cat(_T_2355, _T_2354) @[Cat.scala 29:58] - node _T_2357 = cat(_T_2351, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2358 = cat(UInt<1>("h00"), _T_2350) @[Cat.scala 29:58] - node _T_2359 = cat(_T_2358, UInt<16>("h00")) @[Cat.scala 29:58] - node _T_2360 = cat(_T_2359, _T_2357) @[Cat.scala 29:58] - node _T_2361 = cat(_T_2360, _T_2356) @[Cat.scala 29:58] - node _T_2362 = bits(io.csr_pkt.csr_mie, 0, 0) @[dec_tlu_ctl.scala 2507:36] - node _T_2363 = bits(mie, 5, 3) @[dec_tlu_ctl.scala 2507:75] - node _T_2364 = bits(mie, 2, 2) @[dec_tlu_ctl.scala 2507:96] - node _T_2365 = bits(mie, 1, 1) @[dec_tlu_ctl.scala 2507:114] - node _T_2366 = bits(mie, 0, 0) @[dec_tlu_ctl.scala 2507:132] - node _T_2367 = cat(_T_2366, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2368 = cat(_T_2365, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2369 = cat(_T_2368, _T_2367) @[Cat.scala 29:58] - node _T_2370 = cat(_T_2364, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2371 = cat(UInt<1>("h00"), _T_2363) @[Cat.scala 29:58] - node _T_2372 = cat(_T_2371, UInt<16>("h00")) @[Cat.scala 29:58] - node _T_2373 = cat(_T_2372, _T_2370) @[Cat.scala 29:58] - node _T_2374 = cat(_T_2373, _T_2369) @[Cat.scala 29:58] - node _T_2375 = bits(io.csr_pkt.csr_mcyclel, 0, 0) @[dec_tlu_ctl.scala 2508:40] - node _T_2376 = bits(mcyclel, 31, 0) @[dec_tlu_ctl.scala 2508:65] - node _T_2377 = bits(io.csr_pkt.csr_mcycleh, 0, 0) @[dec_tlu_ctl.scala 2509:40] - node _T_2378 = bits(mcycleh_inc, 31, 0) @[dec_tlu_ctl.scala 2509:69] - node _T_2379 = bits(io.csr_pkt.csr_minstretl, 0, 0) @[dec_tlu_ctl.scala 2510:42] - node _T_2380 = bits(minstretl, 31, 0) @[dec_tlu_ctl.scala 2510:72] - node _T_2381 = bits(io.csr_pkt.csr_minstreth, 0, 0) @[dec_tlu_ctl.scala 2511:42] - node _T_2382 = bits(minstreth_inc, 31, 0) @[dec_tlu_ctl.scala 2511:72] - node _T_2383 = bits(io.csr_pkt.csr_mscratch, 0, 0) @[dec_tlu_ctl.scala 2512:41] - node _T_2384 = bits(mscratch, 31, 0) @[dec_tlu_ctl.scala 2512:66] - node _T_2385 = bits(io.csr_pkt.csr_mepc, 0, 0) @[dec_tlu_ctl.scala 2513:37] - node _T_2386 = cat(io.mepc, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2387 = bits(io.csr_pkt.csr_mcause, 0, 0) @[dec_tlu_ctl.scala 2514:39] - node _T_2388 = bits(mcause, 31, 0) @[dec_tlu_ctl.scala 2514:64] - node _T_2389 = bits(io.csr_pkt.csr_mscause, 0, 0) @[dec_tlu_ctl.scala 2515:40] - node _T_2390 = bits(mscause, 3, 0) @[dec_tlu_ctl.scala 2515:80] - node _T_2391 = cat(UInt<28>("h00"), _T_2390) @[Cat.scala 29:58] - node _T_2392 = bits(io.csr_pkt.csr_mtval, 0, 0) @[dec_tlu_ctl.scala 2516:38] - node _T_2393 = bits(mtval, 31, 0) @[dec_tlu_ctl.scala 2516:63] - node _T_2394 = bits(io.csr_pkt.csr_mrac, 0, 0) @[dec_tlu_ctl.scala 2517:37] - node _T_2395 = bits(mrac, 31, 0) @[dec_tlu_ctl.scala 2517:62] - node _T_2396 = bits(io.csr_pkt.csr_mdseac, 0, 0) @[dec_tlu_ctl.scala 2518:39] - node _T_2397 = bits(mdseac, 31, 0) @[dec_tlu_ctl.scala 2518:64] - node _T_2398 = bits(io.csr_pkt.csr_meivt, 0, 0) @[dec_tlu_ctl.scala 2519:38] - node _T_2399 = cat(meivt, UInt<10>("h00")) @[Cat.scala 29:58] - node _T_2400 = bits(io.csr_pkt.csr_meihap, 0, 0) @[dec_tlu_ctl.scala 2520:39] - node _T_2401 = cat(meivt, meihap) @[Cat.scala 29:58] - node _T_2402 = cat(_T_2401, UInt<2>("h00")) @[Cat.scala 29:58] - node _T_2403 = bits(io.csr_pkt.csr_meicurpl, 0, 0) @[dec_tlu_ctl.scala 2521:41] - node _T_2404 = bits(meicurpl, 3, 0) @[dec_tlu_ctl.scala 2521:81] - node _T_2405 = cat(UInt<28>("h00"), _T_2404) @[Cat.scala 29:58] - node _T_2406 = bits(io.csr_pkt.csr_meicidpl, 0, 0) @[dec_tlu_ctl.scala 2522:41] - node _T_2407 = bits(meicidpl, 3, 0) @[dec_tlu_ctl.scala 2522:81] - node _T_2408 = cat(UInt<28>("h00"), _T_2407) @[Cat.scala 29:58] - node _T_2409 = bits(io.csr_pkt.csr_meipt, 0, 0) @[dec_tlu_ctl.scala 2523:38] - node _T_2410 = bits(meipt, 3, 0) @[dec_tlu_ctl.scala 2523:78] - node _T_2411 = cat(UInt<28>("h00"), _T_2410) @[Cat.scala 29:58] - node _T_2412 = bits(io.csr_pkt.csr_mcgc, 0, 0) @[dec_tlu_ctl.scala 2524:37] - node _T_2413 = bits(mcgc, 8, 0) @[dec_tlu_ctl.scala 2524:77] - node _T_2414 = cat(UInt<23>("h00"), _T_2413) @[Cat.scala 29:58] - node _T_2415 = bits(io.csr_pkt.csr_mfdc, 0, 0) @[dec_tlu_ctl.scala 2525:37] - node _T_2416 = bits(mfdc, 18, 0) @[dec_tlu_ctl.scala 2525:77] - node _T_2417 = cat(UInt<13>("h00"), _T_2416) @[Cat.scala 29:58] - node _T_2418 = bits(io.csr_pkt.csr_dcsr, 0, 0) @[dec_tlu_ctl.scala 2526:37] - node _T_2419 = bits(io.dcsr, 15, 2) @[dec_tlu_ctl.scala 2526:85] - node _T_2420 = cat(UInt<16>("h04000"), _T_2419) @[Cat.scala 29:58] - node _T_2421 = cat(_T_2420, UInt<2>("h03")) @[Cat.scala 29:58] - node _T_2422 = bits(io.csr_pkt.csr_dpc, 0, 0) @[dec_tlu_ctl.scala 2527:36] - node _T_2423 = cat(io.dpc, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2424 = bits(io.csr_pkt.csr_dicad0, 0, 0) @[dec_tlu_ctl.scala 2528:39] - node _T_2425 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2528:64] - node _T_2426 = bits(io.csr_pkt.csr_dicad0h, 0, 0) @[dec_tlu_ctl.scala 2529:40] - node _T_2427 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2529:65] - node _T_2428 = bits(io.csr_pkt.csr_dicad1, 0, 0) @[dec_tlu_ctl.scala 2530:39] - node _T_2429 = bits(dicad1, 31, 0) @[dec_tlu_ctl.scala 2530:64] - node _T_2430 = bits(io.csr_pkt.csr_dicawics, 0, 0) @[dec_tlu_ctl.scala 2531:41] - node _T_2431 = bits(dicawics, 16, 16) @[dec_tlu_ctl.scala 2531:80] - node _T_2432 = bits(dicawics, 15, 14) @[dec_tlu_ctl.scala 2531:104] - node _T_2433 = bits(dicawics, 13, 0) @[dec_tlu_ctl.scala 2531:131] - node _T_2434 = cat(UInt<3>("h00"), _T_2433) @[Cat.scala 29:58] - node _T_2435 = cat(_T_2434, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2436 = cat(UInt<2>("h00"), _T_2432) @[Cat.scala 29:58] - node _T_2437 = cat(UInt<7>("h00"), _T_2431) @[Cat.scala 29:58] - node _T_2438 = cat(_T_2437, _T_2436) @[Cat.scala 29:58] - node _T_2439 = cat(_T_2438, _T_2435) @[Cat.scala 29:58] - node _T_2440 = bits(io.csr_pkt.csr_mtsel, 0, 0) @[dec_tlu_ctl.scala 2532:38] - node _T_2441 = bits(mtsel, 1, 0) @[dec_tlu_ctl.scala 2532:78] - node _T_2442 = cat(UInt<30>("h00"), _T_2441) @[Cat.scala 29:58] - node _T_2443 = bits(io.csr_pkt.csr_mtdata1, 0, 0) @[dec_tlu_ctl.scala 2533:40] - node _T_2444 = bits(mtdata1_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2533:74] - node _T_2445 = bits(io.csr_pkt.csr_mtdata2, 0, 0) @[dec_tlu_ctl.scala 2534:40] - node _T_2446 = bits(mtdata2_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2534:74] - node _T_2447 = bits(io.csr_pkt.csr_micect, 0, 0) @[dec_tlu_ctl.scala 2535:39] - node _T_2448 = bits(micect, 31, 0) @[dec_tlu_ctl.scala 2535:64] - node _T_2449 = bits(io.csr_pkt.csr_miccmect, 0, 0) @[dec_tlu_ctl.scala 2536:41] - node _T_2450 = bits(miccmect, 31, 0) @[dec_tlu_ctl.scala 2536:66] - node _T_2451 = bits(io.csr_pkt.csr_mdccmect, 0, 0) @[dec_tlu_ctl.scala 2537:41] - node _T_2452 = bits(mdccmect, 31, 0) @[dec_tlu_ctl.scala 2537:66] - node _T_2453 = bits(io.csr_pkt.csr_mhpmc3, 0, 0) @[dec_tlu_ctl.scala 2538:39] - node _T_2454 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2538:64] - node _T_2455 = bits(io.csr_pkt.csr_mhpmc4, 0, 0) @[dec_tlu_ctl.scala 2539:39] - node _T_2456 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2539:64] - node _T_2457 = bits(io.csr_pkt.csr_mhpmc5, 0, 0) @[dec_tlu_ctl.scala 2540:39] - node _T_2458 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2540:64] - node _T_2459 = bits(io.csr_pkt.csr_mhpmc6, 0, 0) @[dec_tlu_ctl.scala 2541:39] - node _T_2460 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2541:64] - node _T_2461 = bits(io.csr_pkt.csr_mhpmc3h, 0, 0) @[dec_tlu_ctl.scala 2542:40] - node _T_2462 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2542:65] - node _T_2463 = bits(io.csr_pkt.csr_mhpmc4h, 0, 0) @[dec_tlu_ctl.scala 2543:40] - node _T_2464 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2543:65] - node _T_2465 = bits(io.csr_pkt.csr_mhpmc5h, 0, 0) @[dec_tlu_ctl.scala 2544:40] - node _T_2466 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2544:65] - node _T_2467 = bits(io.csr_pkt.csr_mhpmc6h, 0, 0) @[dec_tlu_ctl.scala 2545:40] - node _T_2468 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2545:65] - node _T_2469 = bits(io.csr_pkt.csr_mfdht, 0, 0) @[dec_tlu_ctl.scala 2546:38] - node _T_2470 = bits(mfdht, 5, 0) @[dec_tlu_ctl.scala 2546:78] - node _T_2471 = cat(UInt<26>("h00"), _T_2470) @[Cat.scala 29:58] - node _T_2472 = bits(io.csr_pkt.csr_mfdhs, 0, 0) @[dec_tlu_ctl.scala 2547:38] - node _T_2473 = bits(mfdhs, 1, 0) @[dec_tlu_ctl.scala 2547:78] - node _T_2474 = cat(UInt<30>("h00"), _T_2473) @[Cat.scala 29:58] - node _T_2475 = bits(io.csr_pkt.csr_mhpme3, 0, 0) @[dec_tlu_ctl.scala 2548:39] - node _T_2476 = bits(mhpme3, 9, 0) @[dec_tlu_ctl.scala 2548:79] - node _T_2477 = cat(UInt<22>("h00"), _T_2476) @[Cat.scala 29:58] - node _T_2478 = bits(io.csr_pkt.csr_mhpme4, 0, 0) @[dec_tlu_ctl.scala 2549:39] - node _T_2479 = bits(mhpme4, 9, 0) @[dec_tlu_ctl.scala 2549:79] - node _T_2480 = cat(UInt<22>("h00"), _T_2479) @[Cat.scala 29:58] - node _T_2481 = bits(io.csr_pkt.csr_mhpme5, 0, 0) @[dec_tlu_ctl.scala 2550:39] - node _T_2482 = bits(mhpme5, 9, 0) @[dec_tlu_ctl.scala 2550:78] - node _T_2483 = cat(UInt<22>("h00"), _T_2482) @[Cat.scala 29:58] - node _T_2484 = bits(io.csr_pkt.csr_mhpme6, 0, 0) @[dec_tlu_ctl.scala 2551:39] - node _T_2485 = bits(mhpme6, 9, 0) @[dec_tlu_ctl.scala 2551:78] - node _T_2486 = cat(UInt<22>("h00"), _T_2485) @[Cat.scala 29:58] - node _T_2487 = bits(io.csr_pkt.csr_mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2552:46] - node _T_2488 = bits(mcountinhibit, 6, 0) @[dec_tlu_ctl.scala 2552:86] - node _T_2489 = cat(UInt<25>("h00"), _T_2488) @[Cat.scala 29:58] - node _T_2490 = bits(io.csr_pkt.csr_mpmc, 0, 0) @[dec_tlu_ctl.scala 2553:37] - node _T_2491 = cat(UInt<30>("h00"), mpmc) @[Cat.scala 29:58] - node _T_2492 = cat(_T_2491, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2493 = bits(io.dec_timer_read_d, 0, 0) @[dec_tlu_ctl.scala 2554:37] - node _T_2494 = bits(io.dec_timer_rddata_d, 31, 0) @[dec_tlu_ctl.scala 2554:76] - node _T_2495 = mux(_T_2329, UInt<32>("h040001104"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2496 = mux(_T_2330, UInt<32>("h045"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2497 = mux(_T_2331, UInt<32>("h010"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2498 = mux(_T_2332, UInt<32>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2499 = mux(_T_2333, _T_2334, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2500 = mux(_T_2335, _T_2343, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2501 = mux(_T_2344, _T_2348, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2502 = mux(_T_2349, _T_2361, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2503 = mux(_T_2362, _T_2374, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2504 = mux(_T_2375, _T_2376, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2505 = mux(_T_2377, _T_2378, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2506 = mux(_T_2379, _T_2380, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2507 = mux(_T_2381, _T_2382, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2508 = mux(_T_2383, _T_2384, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2509 = mux(_T_2385, _T_2386, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2510 = mux(_T_2387, _T_2388, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2511 = mux(_T_2389, _T_2391, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2512 = mux(_T_2392, _T_2393, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2513 = mux(_T_2394, _T_2395, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2514 = mux(_T_2396, _T_2397, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2515 = mux(_T_2398, _T_2399, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2516 = mux(_T_2400, _T_2402, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2517 = mux(_T_2403, _T_2405, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2518 = mux(_T_2406, _T_2408, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2519 = mux(_T_2409, _T_2411, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2520 = mux(_T_2412, _T_2414, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2521 = mux(_T_2415, _T_2417, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2522 = mux(_T_2418, _T_2421, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2523 = mux(_T_2422, _T_2423, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2524 = mux(_T_2424, _T_2425, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2525 = mux(_T_2426, _T_2427, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2526 = mux(_T_2428, _T_2429, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2527 = mux(_T_2430, _T_2439, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2528 = mux(_T_2440, _T_2442, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2529 = mux(_T_2443, _T_2444, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2530 = mux(_T_2445, _T_2446, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2531 = mux(_T_2447, _T_2448, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2532 = mux(_T_2449, _T_2450, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2533 = mux(_T_2451, _T_2452, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2534 = mux(_T_2453, _T_2454, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2535 = mux(_T_2455, _T_2456, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2536 = mux(_T_2457, _T_2458, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2537 = mux(_T_2459, _T_2460, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2538 = mux(_T_2461, _T_2462, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2539 = mux(_T_2463, _T_2464, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2540 = mux(_T_2465, _T_2466, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2541 = mux(_T_2467, _T_2468, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2542 = mux(_T_2469, _T_2471, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2543 = mux(_T_2472, _T_2474, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2544 = mux(_T_2475, _T_2477, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2545 = mux(_T_2478, _T_2480, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2546 = mux(_T_2481, _T_2483, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2547 = mux(_T_2484, _T_2486, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2548 = mux(_T_2487, _T_2489, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2549 = mux(_T_2490, _T_2492, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2550 = mux(_T_2493, _T_2494, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2551 = or(_T_2495, _T_2496) @[Mux.scala 27:72] - node _T_2552 = or(_T_2551, _T_2497) @[Mux.scala 27:72] - node _T_2553 = or(_T_2552, _T_2498) @[Mux.scala 27:72] - node _T_2554 = or(_T_2553, _T_2499) @[Mux.scala 27:72] - node _T_2555 = or(_T_2554, _T_2500) @[Mux.scala 27:72] - node _T_2556 = or(_T_2555, _T_2501) @[Mux.scala 27:72] - node _T_2557 = or(_T_2556, _T_2502) @[Mux.scala 27:72] - node _T_2558 = or(_T_2557, _T_2503) @[Mux.scala 27:72] - node _T_2559 = or(_T_2558, _T_2504) @[Mux.scala 27:72] - node _T_2560 = or(_T_2559, _T_2505) @[Mux.scala 27:72] - node _T_2561 = or(_T_2560, _T_2506) @[Mux.scala 27:72] + reg _T_2331 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2486:62] + _T_2331 <= io.i0_valid_wb @[dec_tlu_ctl.scala 2486:62] + io.dec_tlu_i0_valid_wb1 <= _T_2331 @[dec_tlu_ctl.scala 2486:30] + node _T_2332 = or(io.i0_exception_valid_r_d1, io.lsu_i0_exc_r_d1) @[dec_tlu_ctl.scala 2487:91] + node _T_2333 = not(io.trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 2487:137] + node _T_2334 = and(io.trigger_hit_r_d1, _T_2333) @[dec_tlu_ctl.scala 2487:135] + node _T_2335 = or(_T_2332, _T_2334) @[dec_tlu_ctl.scala 2487:112] + reg _T_2336 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2487:62] + _T_2336 <= _T_2335 @[dec_tlu_ctl.scala 2487:62] + io.dec_tlu_i0_exc_valid_wb1 <= _T_2336 @[dec_tlu_ctl.scala 2487:30] + reg _T_2337 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2488:62] + _T_2337 <= io.exc_cause_wb @[dec_tlu_ctl.scala 2488:62] + io.dec_tlu_exc_cause_wb1 <= _T_2337 @[dec_tlu_ctl.scala 2488:30] + reg _T_2338 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2489:62] + _T_2338 <= io.interrupt_valid_r_d1 @[dec_tlu_ctl.scala 2489:62] + io.dec_tlu_int_valid_wb1 <= _T_2338 @[dec_tlu_ctl.scala 2489:30] + io.dec_tlu_mtval_wb1 <= mtval @[dec_tlu_ctl.scala 2491:24] + node _T_2339 = bits(io.csr_pkt.csr_misa, 0, 0) @[dec_tlu_ctl.scala 2497:61] + node _T_2340 = bits(io.csr_pkt.csr_mvendorid, 0, 0) @[dec_tlu_ctl.scala 2498:42] + node _T_2341 = bits(io.csr_pkt.csr_marchid, 0, 0) @[dec_tlu_ctl.scala 2499:40] + node _T_2342 = bits(io.csr_pkt.csr_mimpid, 0, 0) @[dec_tlu_ctl.scala 2500:39] + node _T_2343 = bits(io.csr_pkt.csr_mhartid, 0, 0) @[dec_tlu_ctl.scala 2501:40] + node _T_2344 = cat(io.core_id, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_2345 = bits(io.csr_pkt.csr_mstatus, 0, 0) @[dec_tlu_ctl.scala 2502:40] + node _T_2346 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 2502:103] + node _T_2347 = bits(io.mstatus, 0, 0) @[dec_tlu_ctl.scala 2502:128] + node _T_2348 = cat(UInt<3>("h00"), _T_2347) @[Cat.scala 29:58] + node _T_2349 = cat(_T_2348, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2350 = cat(UInt<3>("h00"), _T_2346) @[Cat.scala 29:58] + node _T_2351 = cat(UInt<19>("h00"), UInt<2>("h03")) @[Cat.scala 29:58] + node _T_2352 = cat(_T_2351, _T_2350) @[Cat.scala 29:58] + node _T_2353 = cat(_T_2352, _T_2349) @[Cat.scala 29:58] + node _T_2354 = bits(io.csr_pkt.csr_mtvec, 0, 0) @[dec_tlu_ctl.scala 2503:38] + node _T_2355 = bits(io.mtvec, 30, 1) @[dec_tlu_ctl.scala 2503:70] + node _T_2356 = bits(io.mtvec, 0, 0) @[dec_tlu_ctl.scala 2503:96] + node _T_2357 = cat(_T_2355, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2358 = cat(_T_2357, _T_2356) @[Cat.scala 29:58] + node _T_2359 = bits(io.csr_pkt.csr_mip, 0, 0) @[dec_tlu_ctl.scala 2504:36] + node _T_2360 = bits(io.mip, 5, 3) @[dec_tlu_ctl.scala 2504:78] + node _T_2361 = bits(io.mip, 2, 2) @[dec_tlu_ctl.scala 2504:102] + node _T_2362 = bits(io.mip, 1, 1) @[dec_tlu_ctl.scala 2504:123] + node _T_2363 = bits(io.mip, 0, 0) @[dec_tlu_ctl.scala 2504:144] + node _T_2364 = cat(_T_2363, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2365 = cat(_T_2362, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2366 = cat(_T_2365, _T_2364) @[Cat.scala 29:58] + node _T_2367 = cat(_T_2361, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2368 = cat(UInt<1>("h00"), _T_2360) @[Cat.scala 29:58] + node _T_2369 = cat(_T_2368, UInt<16>("h00")) @[Cat.scala 29:58] + node _T_2370 = cat(_T_2369, _T_2367) @[Cat.scala 29:58] + node _T_2371 = cat(_T_2370, _T_2366) @[Cat.scala 29:58] + node _T_2372 = bits(io.csr_pkt.csr_mie, 0, 0) @[dec_tlu_ctl.scala 2505:36] + node _T_2373 = bits(mie, 5, 3) @[dec_tlu_ctl.scala 2505:75] + node _T_2374 = bits(mie, 2, 2) @[dec_tlu_ctl.scala 2505:96] + node _T_2375 = bits(mie, 1, 1) @[dec_tlu_ctl.scala 2505:114] + node _T_2376 = bits(mie, 0, 0) @[dec_tlu_ctl.scala 2505:132] + node _T_2377 = cat(_T_2376, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2378 = cat(_T_2375, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2379 = cat(_T_2378, _T_2377) @[Cat.scala 29:58] + node _T_2380 = cat(_T_2374, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2381 = cat(UInt<1>("h00"), _T_2373) @[Cat.scala 29:58] + node _T_2382 = cat(_T_2381, UInt<16>("h00")) @[Cat.scala 29:58] + node _T_2383 = cat(_T_2382, _T_2380) @[Cat.scala 29:58] + node _T_2384 = cat(_T_2383, _T_2379) @[Cat.scala 29:58] + node _T_2385 = bits(io.csr_pkt.csr_mcyclel, 0, 0) @[dec_tlu_ctl.scala 2506:40] + node _T_2386 = bits(mcyclel, 31, 0) @[dec_tlu_ctl.scala 2506:65] + node _T_2387 = bits(io.csr_pkt.csr_mcycleh, 0, 0) @[dec_tlu_ctl.scala 2507:40] + node _T_2388 = bits(mcycleh_inc, 31, 0) @[dec_tlu_ctl.scala 2507:69] + node _T_2389 = bits(io.csr_pkt.csr_minstretl, 0, 0) @[dec_tlu_ctl.scala 2508:42] + node _T_2390 = bits(minstretl, 31, 0) @[dec_tlu_ctl.scala 2508:72] + node _T_2391 = bits(io.csr_pkt.csr_minstreth, 0, 0) @[dec_tlu_ctl.scala 2509:42] + node _T_2392 = bits(minstreth_inc, 31, 0) @[dec_tlu_ctl.scala 2509:72] + node _T_2393 = bits(io.csr_pkt.csr_mscratch, 0, 0) @[dec_tlu_ctl.scala 2510:41] + node _T_2394 = bits(mscratch, 31, 0) @[dec_tlu_ctl.scala 2510:66] + node _T_2395 = bits(io.csr_pkt.csr_mepc, 0, 0) @[dec_tlu_ctl.scala 2511:37] + node _T_2396 = cat(io.mepc, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2397 = bits(io.csr_pkt.csr_mcause, 0, 0) @[dec_tlu_ctl.scala 2512:39] + node _T_2398 = bits(mcause, 31, 0) @[dec_tlu_ctl.scala 2512:64] + node _T_2399 = bits(io.csr_pkt.csr_mscause, 0, 0) @[dec_tlu_ctl.scala 2513:40] + node _T_2400 = bits(mscause, 3, 0) @[dec_tlu_ctl.scala 2513:80] + node _T_2401 = cat(UInt<28>("h00"), _T_2400) @[Cat.scala 29:58] + node _T_2402 = bits(io.csr_pkt.csr_mtval, 0, 0) @[dec_tlu_ctl.scala 2514:38] + node _T_2403 = bits(mtval, 31, 0) @[dec_tlu_ctl.scala 2514:63] + node _T_2404 = bits(io.csr_pkt.csr_mrac, 0, 0) @[dec_tlu_ctl.scala 2515:37] + node _T_2405 = bits(mrac, 31, 0) @[dec_tlu_ctl.scala 2515:62] + node _T_2406 = bits(io.csr_pkt.csr_mdseac, 0, 0) @[dec_tlu_ctl.scala 2516:39] + node _T_2407 = bits(mdseac, 31, 0) @[dec_tlu_ctl.scala 2516:64] + node _T_2408 = bits(io.csr_pkt.csr_meivt, 0, 0) @[dec_tlu_ctl.scala 2517:38] + node _T_2409 = cat(meivt, UInt<10>("h00")) @[Cat.scala 29:58] + node _T_2410 = bits(io.csr_pkt.csr_meihap, 0, 0) @[dec_tlu_ctl.scala 2518:39] + node _T_2411 = cat(meivt, meihap) @[Cat.scala 29:58] + node _T_2412 = cat(_T_2411, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_2413 = bits(io.csr_pkt.csr_meicurpl, 0, 0) @[dec_tlu_ctl.scala 2519:41] + node _T_2414 = bits(meicurpl, 3, 0) @[dec_tlu_ctl.scala 2519:81] + node _T_2415 = cat(UInt<28>("h00"), _T_2414) @[Cat.scala 29:58] + node _T_2416 = bits(io.csr_pkt.csr_meicidpl, 0, 0) @[dec_tlu_ctl.scala 2520:41] + node _T_2417 = bits(meicidpl, 3, 0) @[dec_tlu_ctl.scala 2520:81] + node _T_2418 = cat(UInt<28>("h00"), _T_2417) @[Cat.scala 29:58] + node _T_2419 = bits(io.csr_pkt.csr_meipt, 0, 0) @[dec_tlu_ctl.scala 2521:38] + node _T_2420 = bits(meipt, 3, 0) @[dec_tlu_ctl.scala 2521:78] + node _T_2421 = cat(UInt<28>("h00"), _T_2420) @[Cat.scala 29:58] + node _T_2422 = bits(io.csr_pkt.csr_mcgc, 0, 0) @[dec_tlu_ctl.scala 2522:37] + node _T_2423 = bits(mcgc, 8, 0) @[dec_tlu_ctl.scala 2522:77] + node _T_2424 = cat(UInt<23>("h00"), _T_2423) @[Cat.scala 29:58] + node _T_2425 = bits(io.csr_pkt.csr_mfdc, 0, 0) @[dec_tlu_ctl.scala 2523:37] + node _T_2426 = bits(mfdc, 18, 0) @[dec_tlu_ctl.scala 2523:77] + node _T_2427 = cat(UInt<13>("h00"), _T_2426) @[Cat.scala 29:58] + node _T_2428 = bits(io.csr_pkt.csr_dcsr, 0, 0) @[dec_tlu_ctl.scala 2524:37] + node _T_2429 = bits(io.dcsr, 15, 2) @[dec_tlu_ctl.scala 2524:85] + node _T_2430 = cat(UInt<16>("h04000"), _T_2429) @[Cat.scala 29:58] + node _T_2431 = cat(_T_2430, UInt<2>("h03")) @[Cat.scala 29:58] + node _T_2432 = bits(io.csr_pkt.csr_dpc, 0, 0) @[dec_tlu_ctl.scala 2525:36] + node _T_2433 = cat(io.dpc, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2434 = bits(io.csr_pkt.csr_dicad0, 0, 0) @[dec_tlu_ctl.scala 2526:39] + node _T_2435 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2526:64] + node _T_2436 = bits(io.csr_pkt.csr_dicad0h, 0, 0) @[dec_tlu_ctl.scala 2527:40] + node _T_2437 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2527:65] + node _T_2438 = bits(io.csr_pkt.csr_dicad1, 0, 0) @[dec_tlu_ctl.scala 2528:39] + node _T_2439 = bits(dicad1, 31, 0) @[dec_tlu_ctl.scala 2528:64] + node _T_2440 = bits(io.csr_pkt.csr_dicawics, 0, 0) @[dec_tlu_ctl.scala 2529:41] + node _T_2441 = bits(dicawics, 16, 16) @[dec_tlu_ctl.scala 2529:80] + node _T_2442 = bits(dicawics, 15, 14) @[dec_tlu_ctl.scala 2529:104] + node _T_2443 = bits(dicawics, 13, 0) @[dec_tlu_ctl.scala 2529:131] + node _T_2444 = cat(UInt<3>("h00"), _T_2443) @[Cat.scala 29:58] + node _T_2445 = cat(_T_2444, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2446 = cat(UInt<2>("h00"), _T_2442) @[Cat.scala 29:58] + node _T_2447 = cat(UInt<7>("h00"), _T_2441) @[Cat.scala 29:58] + node _T_2448 = cat(_T_2447, _T_2446) @[Cat.scala 29:58] + node _T_2449 = cat(_T_2448, _T_2445) @[Cat.scala 29:58] + node _T_2450 = bits(io.csr_pkt.csr_mtsel, 0, 0) @[dec_tlu_ctl.scala 2530:38] + node _T_2451 = bits(mtsel, 1, 0) @[dec_tlu_ctl.scala 2530:78] + node _T_2452 = cat(UInt<30>("h00"), _T_2451) @[Cat.scala 29:58] + node _T_2453 = bits(io.csr_pkt.csr_mtdata1, 0, 0) @[dec_tlu_ctl.scala 2531:40] + node _T_2454 = bits(mtdata1_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2531:74] + node _T_2455 = bits(io.csr_pkt.csr_mtdata2, 0, 0) @[dec_tlu_ctl.scala 2532:40] + node _T_2456 = bits(mtdata2_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2532:74] + node _T_2457 = bits(io.csr_pkt.csr_micect, 0, 0) @[dec_tlu_ctl.scala 2533:39] + node _T_2458 = bits(micect, 31, 0) @[dec_tlu_ctl.scala 2533:64] + node _T_2459 = bits(io.csr_pkt.csr_miccmect, 0, 0) @[dec_tlu_ctl.scala 2534:41] + node _T_2460 = bits(miccmect, 31, 0) @[dec_tlu_ctl.scala 2534:66] + node _T_2461 = bits(io.csr_pkt.csr_mdccmect, 0, 0) @[dec_tlu_ctl.scala 2535:41] + node _T_2462 = bits(mdccmect, 31, 0) @[dec_tlu_ctl.scala 2535:66] + node _T_2463 = bits(io.csr_pkt.csr_mhpmc3, 0, 0) @[dec_tlu_ctl.scala 2536:39] + node _T_2464 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2536:64] + node _T_2465 = bits(io.csr_pkt.csr_mhpmc4, 0, 0) @[dec_tlu_ctl.scala 2537:39] + node _T_2466 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2537:64] + node _T_2467 = bits(io.csr_pkt.csr_mhpmc5, 0, 0) @[dec_tlu_ctl.scala 2538:39] + node _T_2468 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2538:64] + node _T_2469 = bits(io.csr_pkt.csr_mhpmc6, 0, 0) @[dec_tlu_ctl.scala 2539:39] + node _T_2470 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2539:64] + node _T_2471 = bits(io.csr_pkt.csr_mhpmc3h, 0, 0) @[dec_tlu_ctl.scala 2540:40] + node _T_2472 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2540:65] + node _T_2473 = bits(io.csr_pkt.csr_mhpmc4h, 0, 0) @[dec_tlu_ctl.scala 2541:40] + node _T_2474 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2541:65] + node _T_2475 = bits(io.csr_pkt.csr_mhpmc5h, 0, 0) @[dec_tlu_ctl.scala 2542:40] + node _T_2476 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2542:65] + node _T_2477 = bits(io.csr_pkt.csr_mhpmc6h, 0, 0) @[dec_tlu_ctl.scala 2543:40] + node _T_2478 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2543:65] + node _T_2479 = bits(io.csr_pkt.csr_mfdht, 0, 0) @[dec_tlu_ctl.scala 2544:38] + node _T_2480 = bits(mfdht, 5, 0) @[dec_tlu_ctl.scala 2544:78] + node _T_2481 = cat(UInt<26>("h00"), _T_2480) @[Cat.scala 29:58] + node _T_2482 = bits(io.csr_pkt.csr_mfdhs, 0, 0) @[dec_tlu_ctl.scala 2545:38] + node _T_2483 = bits(mfdhs, 1, 0) @[dec_tlu_ctl.scala 2545:78] + node _T_2484 = cat(UInt<30>("h00"), _T_2483) @[Cat.scala 29:58] + node _T_2485 = bits(io.csr_pkt.csr_mhpme3, 0, 0) @[dec_tlu_ctl.scala 2546:39] + node _T_2486 = bits(mhpme3, 9, 0) @[dec_tlu_ctl.scala 2546:79] + node _T_2487 = cat(UInt<22>("h00"), _T_2486) @[Cat.scala 29:58] + node _T_2488 = bits(io.csr_pkt.csr_mhpme4, 0, 0) @[dec_tlu_ctl.scala 2547:39] + node _T_2489 = bits(mhpme4, 9, 0) @[dec_tlu_ctl.scala 2547:79] + node _T_2490 = cat(UInt<22>("h00"), _T_2489) @[Cat.scala 29:58] + node _T_2491 = bits(io.csr_pkt.csr_mhpme5, 0, 0) @[dec_tlu_ctl.scala 2548:39] + node _T_2492 = bits(mhpme5, 9, 0) @[dec_tlu_ctl.scala 2548:78] + node _T_2493 = cat(UInt<22>("h00"), _T_2492) @[Cat.scala 29:58] + node _T_2494 = bits(io.csr_pkt.csr_mhpme6, 0, 0) @[dec_tlu_ctl.scala 2549:39] + node _T_2495 = bits(mhpme6, 9, 0) @[dec_tlu_ctl.scala 2549:78] + node _T_2496 = cat(UInt<22>("h00"), _T_2495) @[Cat.scala 29:58] + node _T_2497 = bits(io.csr_pkt.csr_mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2550:46] + node _T_2498 = bits(mcountinhibit, 6, 0) @[dec_tlu_ctl.scala 2550:86] + node _T_2499 = cat(UInt<25>("h00"), _T_2498) @[Cat.scala 29:58] + node _T_2500 = bits(io.csr_pkt.csr_mpmc, 0, 0) @[dec_tlu_ctl.scala 2551:37] + node _T_2501 = cat(UInt<30>("h00"), mpmc) @[Cat.scala 29:58] + node _T_2502 = cat(_T_2501, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2503 = bits(io.dec_timer_read_d, 0, 0) @[dec_tlu_ctl.scala 2552:37] + node _T_2504 = bits(io.dec_timer_rddata_d, 31, 0) @[dec_tlu_ctl.scala 2552:76] + node _T_2505 = mux(_T_2339, UInt<32>("h040001104"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2506 = mux(_T_2340, UInt<32>("h045"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2507 = mux(_T_2341, UInt<32>("h010"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2508 = mux(_T_2342, UInt<32>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2509 = mux(_T_2343, _T_2344, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2510 = mux(_T_2345, _T_2353, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2511 = mux(_T_2354, _T_2358, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2512 = mux(_T_2359, _T_2371, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2513 = mux(_T_2372, _T_2384, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2514 = mux(_T_2385, _T_2386, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2515 = mux(_T_2387, _T_2388, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2516 = mux(_T_2389, _T_2390, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2517 = mux(_T_2391, _T_2392, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2518 = mux(_T_2393, _T_2394, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2519 = mux(_T_2395, _T_2396, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2520 = mux(_T_2397, _T_2398, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2521 = mux(_T_2399, _T_2401, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2522 = mux(_T_2402, _T_2403, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2523 = mux(_T_2404, _T_2405, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2524 = mux(_T_2406, _T_2407, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2525 = mux(_T_2408, _T_2409, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2526 = mux(_T_2410, _T_2412, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2527 = mux(_T_2413, _T_2415, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2528 = mux(_T_2416, _T_2418, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2529 = mux(_T_2419, _T_2421, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2530 = mux(_T_2422, _T_2424, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2531 = mux(_T_2425, _T_2427, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2532 = mux(_T_2428, _T_2431, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2533 = mux(_T_2432, _T_2433, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2534 = mux(_T_2434, _T_2435, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2535 = mux(_T_2436, _T_2437, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2536 = mux(_T_2438, _T_2439, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2537 = mux(_T_2440, _T_2449, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2538 = mux(_T_2450, _T_2452, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2539 = mux(_T_2453, _T_2454, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2540 = mux(_T_2455, _T_2456, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2541 = mux(_T_2457, _T_2458, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2542 = mux(_T_2459, _T_2460, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2543 = mux(_T_2461, _T_2462, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2544 = mux(_T_2463, _T_2464, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2545 = mux(_T_2465, _T_2466, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2546 = mux(_T_2467, _T_2468, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2547 = mux(_T_2469, _T_2470, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2548 = mux(_T_2471, _T_2472, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2549 = mux(_T_2473, _T_2474, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2550 = mux(_T_2475, _T_2476, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2551 = mux(_T_2477, _T_2478, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2552 = mux(_T_2479, _T_2481, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2553 = mux(_T_2482, _T_2484, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2554 = mux(_T_2485, _T_2487, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2555 = mux(_T_2488, _T_2490, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2556 = mux(_T_2491, _T_2493, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2557 = mux(_T_2494, _T_2496, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2558 = mux(_T_2497, _T_2499, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2559 = mux(_T_2500, _T_2502, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2560 = mux(_T_2503, _T_2504, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2561 = or(_T_2505, _T_2506) @[Mux.scala 27:72] node _T_2562 = or(_T_2561, _T_2507) @[Mux.scala 27:72] node _T_2563 = or(_T_2562, _T_2508) @[Mux.scala 27:72] node _T_2564 = or(_T_2563, _T_2509) @[Mux.scala 27:72] @@ -76167,1690 +76167,1700 @@ circuit quasar_wrapper : node _T_2603 = or(_T_2602, _T_2548) @[Mux.scala 27:72] node _T_2604 = or(_T_2603, _T_2549) @[Mux.scala 27:72] node _T_2605 = or(_T_2604, _T_2550) @[Mux.scala 27:72] - wire _T_2606 : UInt @[Mux.scala 27:72] - _T_2606 <= _T_2605 @[Mux.scala 27:72] - io.dec_csr_rddata_d <= _T_2606 @[dec_tlu_ctl.scala 2498:21] + node _T_2606 = or(_T_2605, _T_2551) @[Mux.scala 27:72] + node _T_2607 = or(_T_2606, _T_2552) @[Mux.scala 27:72] + node _T_2608 = or(_T_2607, _T_2553) @[Mux.scala 27:72] + node _T_2609 = or(_T_2608, _T_2554) @[Mux.scala 27:72] + node _T_2610 = or(_T_2609, _T_2555) @[Mux.scala 27:72] + node _T_2611 = or(_T_2610, _T_2556) @[Mux.scala 27:72] + node _T_2612 = or(_T_2611, _T_2557) @[Mux.scala 27:72] + node _T_2613 = or(_T_2612, _T_2558) @[Mux.scala 27:72] + node _T_2614 = or(_T_2613, _T_2559) @[Mux.scala 27:72] + node _T_2615 = or(_T_2614, _T_2560) @[Mux.scala 27:72] + wire _T_2616 : UInt @[Mux.scala 27:72] + _T_2616 <= _T_2615 @[Mux.scala 27:72] + io.dec_csr_rddata_d <= _T_2616 @[dec_tlu_ctl.scala 2496:21] module dec_decode_csr_read : input clock : Clock input reset : AsyncReset output io : {flip dec_csr_rdaddr_d : UInt<12>, csr_pkt : {csr_misa : UInt<1>, csr_mvendorid : UInt<1>, csr_marchid : UInt<1>, csr_mimpid : UInt<1>, csr_mhartid : UInt<1>, csr_mstatus : UInt<1>, csr_mtvec : UInt<1>, csr_mip : UInt<1>, csr_mie : UInt<1>, csr_mcyclel : UInt<1>, csr_mcycleh : UInt<1>, csr_minstretl : UInt<1>, csr_minstreth : UInt<1>, csr_mscratch : UInt<1>, csr_mepc : UInt<1>, csr_mcause : UInt<1>, csr_mscause : UInt<1>, csr_mtval : UInt<1>, csr_mrac : UInt<1>, csr_dmst : UInt<1>, csr_mdseac : UInt<1>, csr_meihap : UInt<1>, csr_meivt : UInt<1>, csr_meipt : UInt<1>, csr_meicurpl : UInt<1>, csr_meicidpl : UInt<1>, csr_dcsr : UInt<1>, csr_mcgc : UInt<1>, csr_mfdc : UInt<1>, csr_dpc : UInt<1>, csr_mtsel : UInt<1>, csr_mtdata1 : UInt<1>, csr_mtdata2 : UInt<1>, csr_mhpmc3 : UInt<1>, csr_mhpmc4 : UInt<1>, csr_mhpmc5 : UInt<1>, csr_mhpmc6 : UInt<1>, csr_mhpmc3h : UInt<1>, csr_mhpmc4h : UInt<1>, csr_mhpmc5h : UInt<1>, csr_mhpmc6h : UInt<1>, csr_mhpme3 : UInt<1>, csr_mhpme4 : UInt<1>, csr_mhpme5 : UInt<1>, csr_mhpme6 : UInt<1>, csr_mcountinhibit : UInt<1>, csr_mitctl0 : UInt<1>, csr_mitctl1 : UInt<1>, csr_mitb0 : UInt<1>, csr_mitb1 : UInt<1>, csr_mitcnt0 : UInt<1>, csr_mitcnt1 : UInt<1>, csr_mpmc : UInt<1>, csr_mcpc : UInt<1>, csr_meicpct : UInt<1>, csr_mdeau : UInt<1>, csr_micect : UInt<1>, csr_miccmect : UInt<1>, csr_mdccmect : UInt<1>, csr_mfdht : UInt<1>, csr_mfdhs : UInt<1>, csr_dicawics : UInt<1>, csr_dicad0h : UInt<1>, csr_dicad0 : UInt<1>, csr_dicad1 : UInt<1>, csr_dicago : UInt<1>, presync : UInt<1>, postsync : UInt<1>, legal : UInt<1>}} - node _T = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:149] - node _T_1 = eq(_T, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_2 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] - node _T_3 = eq(_T_2, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_4 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] - node _T_5 = eq(_T_4, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_6 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] - node _T_7 = eq(_T_6, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_8 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] - node _T_9 = and(_T_1, _T_3) @[dec_tlu_ctl.scala 2570:198] - node _T_10 = and(_T_9, _T_5) @[dec_tlu_ctl.scala 2570:198] - node _T_11 = and(_T_10, _T_7) @[dec_tlu_ctl.scala 2570:198] - node _T_12 = and(_T_11, _T_8) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_misa <= _T_12 @[dec_tlu_ctl.scala 2572:57] - node _T_13 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] - node _T_14 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] - node _T_15 = eq(_T_14, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_16 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] - node _T_17 = eq(_T_16, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_18 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] - node _T_19 = and(_T_13, _T_15) @[dec_tlu_ctl.scala 2570:198] - node _T_20 = and(_T_19, _T_17) @[dec_tlu_ctl.scala 2570:198] - node _T_21 = and(_T_20, _T_18) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_mvendorid <= _T_21 @[dec_tlu_ctl.scala 2573:57] - node _T_22 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] - node _T_23 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] - node _T_24 = eq(_T_23, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_25 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] - node _T_26 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] - node _T_27 = eq(_T_26, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] - node _T_28 = and(_T_22, _T_24) @[dec_tlu_ctl.scala 2570:198] - node _T_29 = and(_T_28, _T_25) @[dec_tlu_ctl.scala 2570:198] - node _T_30 = and(_T_29, _T_27) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_marchid <= _T_30 @[dec_tlu_ctl.scala 2574:57] - node _T_31 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] - node _T_32 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] - node _T_33 = eq(_T_32, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_34 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] - node _T_35 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] - node _T_36 = and(_T_31, _T_33) @[dec_tlu_ctl.scala 2570:198] - node _T_37 = and(_T_36, _T_34) @[dec_tlu_ctl.scala 2570:198] - node _T_38 = and(_T_37, _T_35) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_mimpid <= _T_38 @[dec_tlu_ctl.scala 2575:57] - node _T_39 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] - node _T_40 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] - node _T_41 = eq(_T_40, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_42 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] - node _T_43 = and(_T_39, _T_41) @[dec_tlu_ctl.scala 2570:198] - node _T_44 = and(_T_43, _T_42) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_mhartid <= _T_44 @[dec_tlu_ctl.scala 2576:57] - node _T_45 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:149] - node _T_46 = eq(_T_45, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_47 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] - node _T_48 = eq(_T_47, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_49 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] - node _T_50 = eq(_T_49, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_51 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] - node _T_52 = eq(_T_51, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_53 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] - node _T_54 = eq(_T_53, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] - node _T_55 = and(_T_46, _T_48) @[dec_tlu_ctl.scala 2570:198] - node _T_56 = and(_T_55, _T_50) @[dec_tlu_ctl.scala 2570:198] - node _T_57 = and(_T_56, _T_52) @[dec_tlu_ctl.scala 2570:198] - node _T_58 = and(_T_57, _T_54) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_mstatus <= _T_58 @[dec_tlu_ctl.scala 2577:57] - node _T_59 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:149] - node _T_60 = eq(_T_59, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_61 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] - node _T_62 = eq(_T_61, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_63 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] - node _T_64 = eq(_T_63, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_65 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] - node _T_66 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] - node _T_67 = and(_T_60, _T_62) @[dec_tlu_ctl.scala 2570:198] - node _T_68 = and(_T_67, _T_64) @[dec_tlu_ctl.scala 2570:198] - node _T_69 = and(_T_68, _T_65) @[dec_tlu_ctl.scala 2570:198] - node _T_70 = and(_T_69, _T_66) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_mtvec <= _T_70 @[dec_tlu_ctl.scala 2578:57] - node _T_71 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] - node _T_72 = eq(_T_71, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_73 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] - node _T_74 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] - node _T_75 = and(_T_72, _T_73) @[dec_tlu_ctl.scala 2570:198] - node _T_76 = and(_T_75, _T_74) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_mip <= _T_76 @[dec_tlu_ctl.scala 2579:65] - node _T_77 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:149] - node _T_78 = eq(_T_77, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_79 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] - node _T_80 = eq(_T_79, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_81 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] - node _T_82 = eq(_T_81, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_83 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] - node _T_84 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] - node _T_85 = eq(_T_84, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] - node _T_86 = and(_T_78, _T_80) @[dec_tlu_ctl.scala 2570:198] - node _T_87 = and(_T_86, _T_82) @[dec_tlu_ctl.scala 2570:198] - node _T_88 = and(_T_87, _T_83) @[dec_tlu_ctl.scala 2570:198] - node _T_89 = and(_T_88, _T_85) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_mie <= _T_89 @[dec_tlu_ctl.scala 2580:65] - node _T_90 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:106] - node _T_91 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] - node _T_92 = eq(_T_91, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_93 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] - node _T_94 = eq(_T_93, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_95 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] - node _T_96 = eq(_T_95, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_97 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] - node _T_98 = eq(_T_97, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_99 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] - node _T_100 = eq(_T_99, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_101 = and(_T_90, _T_92) @[dec_tlu_ctl.scala 2570:198] - node _T_102 = and(_T_101, _T_94) @[dec_tlu_ctl.scala 2570:198] - node _T_103 = and(_T_102, _T_96) @[dec_tlu_ctl.scala 2570:198] - node _T_104 = and(_T_103, _T_98) @[dec_tlu_ctl.scala 2570:198] - node _T_105 = and(_T_104, _T_100) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_mcyclel <= _T_105 @[dec_tlu_ctl.scala 2581:57] - node _T_106 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:106] - node _T_107 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] - node _T_108 = eq(_T_107, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_109 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] - node _T_110 = eq(_T_109, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_111 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] - node _T_112 = eq(_T_111, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_113 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] - node _T_114 = eq(_T_113, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_115 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] - node _T_116 = eq(_T_115, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_117 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] - node _T_118 = eq(_T_117, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_119 = and(_T_106, _T_108) @[dec_tlu_ctl.scala 2570:198] - node _T_120 = and(_T_119, _T_110) @[dec_tlu_ctl.scala 2570:198] - node _T_121 = and(_T_120, _T_112) @[dec_tlu_ctl.scala 2570:198] - node _T_122 = and(_T_121, _T_114) @[dec_tlu_ctl.scala 2570:198] - node _T_123 = and(_T_122, _T_116) @[dec_tlu_ctl.scala 2570:198] - node _T_124 = and(_T_123, _T_118) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_mcycleh <= _T_124 @[dec_tlu_ctl.scala 2582:57] - node _T_125 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] - node _T_126 = eq(_T_125, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_127 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] - node _T_128 = eq(_T_127, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_129 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] - node _T_130 = eq(_T_129, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_131 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] - node _T_132 = eq(_T_131, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_133 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] - node _T_134 = eq(_T_133, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_135 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] - node _T_136 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] - node _T_137 = eq(_T_136, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] - node _T_138 = and(_T_126, _T_128) @[dec_tlu_ctl.scala 2570:198] - node _T_139 = and(_T_138, _T_130) @[dec_tlu_ctl.scala 2570:198] - node _T_140 = and(_T_139, _T_132) @[dec_tlu_ctl.scala 2570:198] - node _T_141 = and(_T_140, _T_134) @[dec_tlu_ctl.scala 2570:198] - node _T_142 = and(_T_141, _T_135) @[dec_tlu_ctl.scala 2570:198] - node _T_143 = and(_T_142, _T_137) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_minstretl <= _T_143 @[dec_tlu_ctl.scala 2583:57] - node _T_144 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:149] - node _T_145 = eq(_T_144, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_146 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:106] - node _T_147 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] - node _T_148 = eq(_T_147, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_149 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] - node _T_150 = eq(_T_149, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_151 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] - node _T_152 = eq(_T_151, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_153 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] - node _T_154 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] - node _T_155 = eq(_T_154, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] - node _T_156 = and(_T_145, _T_146) @[dec_tlu_ctl.scala 2570:198] - node _T_157 = and(_T_156, _T_148) @[dec_tlu_ctl.scala 2570:198] - node _T_158 = and(_T_157, _T_150) @[dec_tlu_ctl.scala 2570:198] - node _T_159 = and(_T_158, _T_152) @[dec_tlu_ctl.scala 2570:198] - node _T_160 = and(_T_159, _T_153) @[dec_tlu_ctl.scala 2570:198] - node _T_161 = and(_T_160, _T_155) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_minstreth <= _T_161 @[dec_tlu_ctl.scala 2584:57] - node _T_162 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] - node _T_163 = eq(_T_162, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_164 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] - node _T_165 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] - node _T_166 = eq(_T_165, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_167 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] - node _T_168 = eq(_T_167, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_169 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] - node _T_170 = eq(_T_169, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] - node _T_171 = and(_T_163, _T_164) @[dec_tlu_ctl.scala 2570:198] - node _T_172 = and(_T_171, _T_166) @[dec_tlu_ctl.scala 2570:198] - node _T_173 = and(_T_172, _T_168) @[dec_tlu_ctl.scala 2570:198] - node _T_174 = and(_T_173, _T_170) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_mscratch <= _T_174 @[dec_tlu_ctl.scala 2585:57] - node _T_175 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] - node _T_176 = eq(_T_175, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_177 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] - node _T_178 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] - node _T_179 = eq(_T_178, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_180 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] - node _T_181 = and(_T_176, _T_177) @[dec_tlu_ctl.scala 2570:198] - node _T_182 = and(_T_181, _T_179) @[dec_tlu_ctl.scala 2570:198] - node _T_183 = and(_T_182, _T_180) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_mepc <= _T_183 @[dec_tlu_ctl.scala 2586:57] - node _T_184 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] - node _T_185 = eq(_T_184, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_186 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] - node _T_187 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] - node _T_188 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] - node _T_189 = eq(_T_188, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] - node _T_190 = and(_T_185, _T_186) @[dec_tlu_ctl.scala 2570:198] - node _T_191 = and(_T_190, _T_187) @[dec_tlu_ctl.scala 2570:198] - node _T_192 = and(_T_191, _T_189) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_mcause <= _T_192 @[dec_tlu_ctl.scala 2587:57] - node _T_193 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] - node _T_194 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:106] - node _T_195 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] - node _T_196 = and(_T_193, _T_194) @[dec_tlu_ctl.scala 2570:198] - node _T_197 = and(_T_196, _T_195) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_mscause <= _T_197 @[dec_tlu_ctl.scala 2588:57] - node _T_198 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] - node _T_199 = eq(_T_198, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_200 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] - node _T_201 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] - node _T_202 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] - node _T_203 = and(_T_199, _T_200) @[dec_tlu_ctl.scala 2570:198] - node _T_204 = and(_T_203, _T_201) @[dec_tlu_ctl.scala 2570:198] - node _T_205 = and(_T_204, _T_202) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_mtval <= _T_205 @[dec_tlu_ctl.scala 2589:57] - node _T_206 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:149] - node _T_207 = eq(_T_206, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_208 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:106] - node _T_209 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] - node _T_210 = eq(_T_209, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_211 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] - node _T_212 = eq(_T_211, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_213 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] - node _T_214 = eq(_T_213, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_215 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] - node _T_216 = eq(_T_215, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_217 = and(_T_207, _T_208) @[dec_tlu_ctl.scala 2570:198] - node _T_218 = and(_T_217, _T_210) @[dec_tlu_ctl.scala 2570:198] - node _T_219 = and(_T_218, _T_212) @[dec_tlu_ctl.scala 2570:198] - node _T_220 = and(_T_219, _T_214) @[dec_tlu_ctl.scala 2570:198] - node _T_221 = and(_T_220, _T_216) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_mrac <= _T_221 @[dec_tlu_ctl.scala 2590:57] - node _T_222 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] - node _T_223 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] - node _T_224 = eq(_T_223, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_225 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] - node _T_226 = eq(_T_225, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_227 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] - node _T_228 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] - node _T_229 = eq(_T_228, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_230 = and(_T_222, _T_224) @[dec_tlu_ctl.scala 2570:198] - node _T_231 = and(_T_230, _T_226) @[dec_tlu_ctl.scala 2570:198] - node _T_232 = and(_T_231, _T_227) @[dec_tlu_ctl.scala 2570:198] - node _T_233 = and(_T_232, _T_229) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_dmst <= _T_233 @[dec_tlu_ctl.scala 2591:57] - node _T_234 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:106] - node _T_235 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] - node _T_236 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] - node _T_237 = eq(_T_236, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_238 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] - node _T_239 = eq(_T_238, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_240 = and(_T_234, _T_235) @[dec_tlu_ctl.scala 2570:198] - node _T_241 = and(_T_240, _T_237) @[dec_tlu_ctl.scala 2570:198] - node _T_242 = and(_T_241, _T_239) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_mdseac <= _T_242 @[dec_tlu_ctl.scala 2592:57] - node _T_243 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:106] - node _T_244 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] - node _T_245 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:106] - node _T_246 = and(_T_243, _T_244) @[dec_tlu_ctl.scala 2570:198] - node _T_247 = and(_T_246, _T_245) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_meihap <= _T_247 @[dec_tlu_ctl.scala 2593:57] - node _T_248 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:149] - node _T_249 = eq(_T_248, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_250 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] - node _T_251 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:106] - node _T_252 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] - node _T_253 = eq(_T_252, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_254 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] - node _T_255 = eq(_T_254, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_256 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] - node _T_257 = eq(_T_256, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] - node _T_258 = and(_T_249, _T_250) @[dec_tlu_ctl.scala 2570:198] - node _T_259 = and(_T_258, _T_251) @[dec_tlu_ctl.scala 2570:198] - node _T_260 = and(_T_259, _T_253) @[dec_tlu_ctl.scala 2570:198] - node _T_261 = and(_T_260, _T_255) @[dec_tlu_ctl.scala 2570:198] - node _T_262 = and(_T_261, _T_257) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_meivt <= _T_262 @[dec_tlu_ctl.scala 2594:57] - node _T_263 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:106] - node _T_264 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] - node _T_265 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] - node _T_266 = eq(_T_265, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_267 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] - node _T_268 = and(_T_263, _T_264) @[dec_tlu_ctl.scala 2570:198] - node _T_269 = and(_T_268, _T_266) @[dec_tlu_ctl.scala 2570:198] - node _T_270 = and(_T_269, _T_267) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_meipt <= _T_270 @[dec_tlu_ctl.scala 2595:57] - node _T_271 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:106] - node _T_272 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] - node _T_273 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] - node _T_274 = and(_T_271, _T_272) @[dec_tlu_ctl.scala 2570:198] - node _T_275 = and(_T_274, _T_273) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_meicurpl <= _T_275 @[dec_tlu_ctl.scala 2596:57] - node _T_276 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:106] - node _T_277 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] - node _T_278 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] - node _T_279 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] - node _T_280 = and(_T_276, _T_277) @[dec_tlu_ctl.scala 2570:198] - node _T_281 = and(_T_280, _T_278) @[dec_tlu_ctl.scala 2570:198] - node _T_282 = and(_T_281, _T_279) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_meicidpl <= _T_282 @[dec_tlu_ctl.scala 2597:57] - node _T_283 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] - node _T_284 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] - node _T_285 = eq(_T_284, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_286 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:106] - node _T_287 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:106] - node _T_288 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] - node _T_289 = eq(_T_288, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] - node _T_290 = and(_T_283, _T_285) @[dec_tlu_ctl.scala 2570:198] - node _T_291 = and(_T_290, _T_286) @[dec_tlu_ctl.scala 2570:198] - node _T_292 = and(_T_291, _T_287) @[dec_tlu_ctl.scala 2570:198] - node _T_293 = and(_T_292, _T_289) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_dcsr <= _T_293 @[dec_tlu_ctl.scala 2598:57] - node _T_294 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] - node _T_295 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:106] - node _T_296 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:106] - node _T_297 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] - node _T_298 = eq(_T_297, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] - node _T_299 = and(_T_294, _T_295) @[dec_tlu_ctl.scala 2570:198] - node _T_300 = and(_T_299, _T_296) @[dec_tlu_ctl.scala 2570:198] - node _T_301 = and(_T_300, _T_298) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_mcgc <= _T_301 @[dec_tlu_ctl.scala 2599:57] - node _T_302 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] - node _T_303 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:106] - node _T_304 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:106] - node _T_305 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] - node _T_306 = eq(_T_305, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_307 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] - node _T_308 = and(_T_302, _T_303) @[dec_tlu_ctl.scala 2570:198] - node _T_309 = and(_T_308, _T_304) @[dec_tlu_ctl.scala 2570:198] - node _T_310 = and(_T_309, _T_306) @[dec_tlu_ctl.scala 2570:198] - node _T_311 = and(_T_310, _T_307) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_mfdc <= _T_311 @[dec_tlu_ctl.scala 2600:57] - node _T_312 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] - node _T_313 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] - node _T_314 = eq(_T_313, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_315 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:106] - node _T_316 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:106] - node _T_317 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] - node _T_318 = and(_T_312, _T_314) @[dec_tlu_ctl.scala 2570:198] - node _T_319 = and(_T_318, _T_315) @[dec_tlu_ctl.scala 2570:198] - node _T_320 = and(_T_319, _T_316) @[dec_tlu_ctl.scala 2570:198] - node _T_321 = and(_T_320, _T_317) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_dpc <= _T_321 @[dec_tlu_ctl.scala 2601:65] - node _T_322 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] - node _T_323 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:106] - node _T_324 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] - node _T_325 = eq(_T_324, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_326 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] - node _T_327 = eq(_T_326, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_328 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] - node _T_329 = eq(_T_328, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] - node _T_330 = and(_T_322, _T_323) @[dec_tlu_ctl.scala 2570:198] - node _T_331 = and(_T_330, _T_325) @[dec_tlu_ctl.scala 2570:198] - node _T_332 = and(_T_331, _T_327) @[dec_tlu_ctl.scala 2570:198] - node _T_333 = and(_T_332, _T_329) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_mtsel <= _T_333 @[dec_tlu_ctl.scala 2602:57] - node _T_334 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] - node _T_335 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] - node _T_336 = eq(_T_335, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_337 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] - node _T_338 = eq(_T_337, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_339 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] - node _T_340 = and(_T_334, _T_336) @[dec_tlu_ctl.scala 2570:198] - node _T_341 = and(_T_340, _T_338) @[dec_tlu_ctl.scala 2570:198] - node _T_342 = and(_T_341, _T_339) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_mtdata1 <= _T_342 @[dec_tlu_ctl.scala 2603:57] - node _T_343 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] - node _T_344 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:106] - node _T_345 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] - node _T_346 = eq(_T_345, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_347 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] - node _T_348 = and(_T_343, _T_344) @[dec_tlu_ctl.scala 2570:198] - node _T_349 = and(_T_348, _T_346) @[dec_tlu_ctl.scala 2570:198] - node _T_350 = and(_T_349, _T_347) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_mtdata2 <= _T_350 @[dec_tlu_ctl.scala 2604:57] - node _T_351 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:106] - node _T_352 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] - node _T_353 = eq(_T_352, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_354 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] - node _T_355 = eq(_T_354, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_356 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] - node _T_357 = eq(_T_356, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_358 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] - node _T_359 = eq(_T_358, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_360 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] - node _T_361 = and(_T_351, _T_353) @[dec_tlu_ctl.scala 2570:198] - node _T_362 = and(_T_361, _T_355) @[dec_tlu_ctl.scala 2570:198] - node _T_363 = and(_T_362, _T_357) @[dec_tlu_ctl.scala 2570:198] - node _T_364 = and(_T_363, _T_359) @[dec_tlu_ctl.scala 2570:198] - node _T_365 = and(_T_364, _T_360) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_mhpmc3 <= _T_365 @[dec_tlu_ctl.scala 2605:57] - node _T_366 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:106] - node _T_367 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] - node _T_368 = eq(_T_367, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_369 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] - node _T_370 = eq(_T_369, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_371 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] - node _T_372 = eq(_T_371, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_373 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] - node _T_374 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] - node _T_375 = eq(_T_374, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_376 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] - node _T_377 = eq(_T_376, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] - node _T_378 = and(_T_366, _T_368) @[dec_tlu_ctl.scala 2570:198] - node _T_379 = and(_T_378, _T_370) @[dec_tlu_ctl.scala 2570:198] - node _T_380 = and(_T_379, _T_372) @[dec_tlu_ctl.scala 2570:198] - node _T_381 = and(_T_380, _T_373) @[dec_tlu_ctl.scala 2570:198] - node _T_382 = and(_T_381, _T_375) @[dec_tlu_ctl.scala 2570:198] - node _T_383 = and(_T_382, _T_377) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_mhpmc4 <= _T_383 @[dec_tlu_ctl.scala 2606:57] - node _T_384 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:106] - node _T_385 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] - node _T_386 = eq(_T_385, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_387 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] - node _T_388 = eq(_T_387, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_389 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] - node _T_390 = eq(_T_389, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_391 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] - node _T_392 = eq(_T_391, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_393 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] - node _T_394 = and(_T_384, _T_386) @[dec_tlu_ctl.scala 2570:198] - node _T_395 = and(_T_394, _T_388) @[dec_tlu_ctl.scala 2570:198] - node _T_396 = and(_T_395, _T_390) @[dec_tlu_ctl.scala 2570:198] - node _T_397 = and(_T_396, _T_392) @[dec_tlu_ctl.scala 2570:198] - node _T_398 = and(_T_397, _T_393) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_mhpmc5 <= _T_398 @[dec_tlu_ctl.scala 2607:57] - node _T_399 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] - node _T_400 = eq(_T_399, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_401 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] - node _T_402 = eq(_T_401, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_403 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] - node _T_404 = eq(_T_403, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_405 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] - node _T_406 = eq(_T_405, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_407 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] - node _T_408 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] - node _T_409 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] - node _T_410 = eq(_T_409, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] - node _T_411 = and(_T_400, _T_402) @[dec_tlu_ctl.scala 2570:198] - node _T_412 = and(_T_411, _T_404) @[dec_tlu_ctl.scala 2570:198] - node _T_413 = and(_T_412, _T_406) @[dec_tlu_ctl.scala 2570:198] - node _T_414 = and(_T_413, _T_407) @[dec_tlu_ctl.scala 2570:198] - node _T_415 = and(_T_414, _T_408) @[dec_tlu_ctl.scala 2570:198] - node _T_416 = and(_T_415, _T_410) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_mhpmc6 <= _T_416 @[dec_tlu_ctl.scala 2608:57] - node _T_417 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:106] - node _T_418 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] - node _T_419 = eq(_T_418, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_420 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] - node _T_421 = eq(_T_420, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_422 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] - node _T_423 = eq(_T_422, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_424 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] - node _T_425 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] - node _T_426 = and(_T_417, _T_419) @[dec_tlu_ctl.scala 2570:198] - node _T_427 = and(_T_426, _T_421) @[dec_tlu_ctl.scala 2570:198] - node _T_428 = and(_T_427, _T_423) @[dec_tlu_ctl.scala 2570:198] - node _T_429 = and(_T_428, _T_424) @[dec_tlu_ctl.scala 2570:198] - node _T_430 = and(_T_429, _T_425) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_mhpmc3h <= _T_430 @[dec_tlu_ctl.scala 2609:57] - node _T_431 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:106] - node _T_432 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] - node _T_433 = eq(_T_432, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_434 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] - node _T_435 = eq(_T_434, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_436 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] - node _T_437 = eq(_T_436, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_438 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] - node _T_439 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] - node _T_440 = eq(_T_439, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_441 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] - node _T_442 = eq(_T_441, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] - node _T_443 = and(_T_431, _T_433) @[dec_tlu_ctl.scala 2570:198] - node _T_444 = and(_T_443, _T_435) @[dec_tlu_ctl.scala 2570:198] - node _T_445 = and(_T_444, _T_437) @[dec_tlu_ctl.scala 2570:198] - node _T_446 = and(_T_445, _T_438) @[dec_tlu_ctl.scala 2570:198] - node _T_447 = and(_T_446, _T_440) @[dec_tlu_ctl.scala 2570:198] - node _T_448 = and(_T_447, _T_442) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_mhpmc4h <= _T_448 @[dec_tlu_ctl.scala 2610:57] - node _T_449 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:106] - node _T_450 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] - node _T_451 = eq(_T_450, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_452 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] - node _T_453 = eq(_T_452, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_454 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] - node _T_455 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] - node _T_456 = eq(_T_455, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_457 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] - node _T_458 = and(_T_449, _T_451) @[dec_tlu_ctl.scala 2570:198] - node _T_459 = and(_T_458, _T_453) @[dec_tlu_ctl.scala 2570:198] - node _T_460 = and(_T_459, _T_454) @[dec_tlu_ctl.scala 2570:198] - node _T_461 = and(_T_460, _T_456) @[dec_tlu_ctl.scala 2570:198] - node _T_462 = and(_T_461, _T_457) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_mhpmc5h <= _T_462 @[dec_tlu_ctl.scala 2611:57] - node _T_463 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:106] - node _T_464 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] - node _T_465 = eq(_T_464, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_466 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] - node _T_467 = eq(_T_466, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_468 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] - node _T_469 = eq(_T_468, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_470 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] - node _T_471 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] - node _T_472 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] - node _T_473 = eq(_T_472, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] - node _T_474 = and(_T_463, _T_465) @[dec_tlu_ctl.scala 2570:198] - node _T_475 = and(_T_474, _T_467) @[dec_tlu_ctl.scala 2570:198] - node _T_476 = and(_T_475, _T_469) @[dec_tlu_ctl.scala 2570:198] - node _T_477 = and(_T_476, _T_470) @[dec_tlu_ctl.scala 2570:198] - node _T_478 = and(_T_477, _T_471) @[dec_tlu_ctl.scala 2570:198] - node _T_479 = and(_T_478, _T_473) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_mhpmc6h <= _T_479 @[dec_tlu_ctl.scala 2612:57] - node _T_480 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] - node _T_481 = eq(_T_480, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_482 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:106] - node _T_483 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] - node _T_484 = eq(_T_483, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_485 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] - node _T_486 = eq(_T_485, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_487 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] - node _T_488 = eq(_T_487, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_489 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] - node _T_490 = and(_T_481, _T_482) @[dec_tlu_ctl.scala 2570:198] - node _T_491 = and(_T_490, _T_484) @[dec_tlu_ctl.scala 2570:198] - node _T_492 = and(_T_491, _T_486) @[dec_tlu_ctl.scala 2570:198] - node _T_493 = and(_T_492, _T_488) @[dec_tlu_ctl.scala 2570:198] - node _T_494 = and(_T_493, _T_489) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_mhpme3 <= _T_494 @[dec_tlu_ctl.scala 2613:57] - node _T_495 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:106] - node _T_496 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] - node _T_497 = eq(_T_496, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_498 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] - node _T_499 = eq(_T_498, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_500 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] - node _T_501 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] - node _T_502 = eq(_T_501, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_503 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] - node _T_504 = eq(_T_503, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] - node _T_505 = and(_T_495, _T_497) @[dec_tlu_ctl.scala 2570:198] - node _T_506 = and(_T_505, _T_499) @[dec_tlu_ctl.scala 2570:198] - node _T_507 = and(_T_506, _T_500) @[dec_tlu_ctl.scala 2570:198] - node _T_508 = and(_T_507, _T_502) @[dec_tlu_ctl.scala 2570:198] - node _T_509 = and(_T_508, _T_504) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_mhpme4 <= _T_509 @[dec_tlu_ctl.scala 2614:57] - node _T_510 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:106] - node _T_511 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] - node _T_512 = eq(_T_511, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_513 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] - node _T_514 = eq(_T_513, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_515 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] - node _T_516 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] - node _T_517 = eq(_T_516, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_518 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] - node _T_519 = and(_T_510, _T_512) @[dec_tlu_ctl.scala 2570:198] - node _T_520 = and(_T_519, _T_514) @[dec_tlu_ctl.scala 2570:198] - node _T_521 = and(_T_520, _T_515) @[dec_tlu_ctl.scala 2570:198] - node _T_522 = and(_T_521, _T_517) @[dec_tlu_ctl.scala 2570:198] - node _T_523 = and(_T_522, _T_518) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_mhpme5 <= _T_523 @[dec_tlu_ctl.scala 2615:57] - node _T_524 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:106] - node _T_525 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] - node _T_526 = eq(_T_525, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_527 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] - node _T_528 = eq(_T_527, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_529 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] - node _T_530 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] - node _T_531 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] - node _T_532 = eq(_T_531, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] - node _T_533 = and(_T_524, _T_526) @[dec_tlu_ctl.scala 2570:198] - node _T_534 = and(_T_533, _T_528) @[dec_tlu_ctl.scala 2570:198] - node _T_535 = and(_T_534, _T_529) @[dec_tlu_ctl.scala 2570:198] - node _T_536 = and(_T_535, _T_530) @[dec_tlu_ctl.scala 2570:198] - node _T_537 = and(_T_536, _T_532) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_mhpme6 <= _T_537 @[dec_tlu_ctl.scala 2616:57] - node _T_538 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] - node _T_539 = eq(_T_538, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_540 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:106] - node _T_541 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] - node _T_542 = eq(_T_541, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_543 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] - node _T_544 = eq(_T_543, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_545 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] - node _T_546 = eq(_T_545, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_547 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] - node _T_548 = eq(_T_547, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] - node _T_549 = and(_T_539, _T_540) @[dec_tlu_ctl.scala 2570:198] - node _T_550 = and(_T_549, _T_542) @[dec_tlu_ctl.scala 2570:198] - node _T_551 = and(_T_550, _T_544) @[dec_tlu_ctl.scala 2570:198] - node _T_552 = and(_T_551, _T_546) @[dec_tlu_ctl.scala 2570:198] - node _T_553 = and(_T_552, _T_548) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_mcountinhibit <= _T_553 @[dec_tlu_ctl.scala 2617:49] - node _T_554 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] - node _T_555 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] - node _T_556 = eq(_T_555, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_557 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:106] - node _T_558 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] - node _T_559 = eq(_T_558, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_560 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] - node _T_561 = eq(_T_560, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] - node _T_562 = and(_T_554, _T_556) @[dec_tlu_ctl.scala 2570:198] - node _T_563 = and(_T_562, _T_557) @[dec_tlu_ctl.scala 2570:198] - node _T_564 = and(_T_563, _T_559) @[dec_tlu_ctl.scala 2570:198] - node _T_565 = and(_T_564, _T_561) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_mitctl0 <= _T_565 @[dec_tlu_ctl.scala 2618:57] - node _T_566 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] - node _T_567 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] - node _T_568 = eq(_T_567, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_569 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] - node _T_570 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] - node _T_571 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] - node _T_572 = and(_T_566, _T_568) @[dec_tlu_ctl.scala 2570:198] - node _T_573 = and(_T_572, _T_569) @[dec_tlu_ctl.scala 2570:198] - node _T_574 = and(_T_573, _T_570) @[dec_tlu_ctl.scala 2570:198] - node _T_575 = and(_T_574, _T_571) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_mitctl1 <= _T_575 @[dec_tlu_ctl.scala 2619:57] - node _T_576 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] - node _T_577 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] - node _T_578 = eq(_T_577, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_579 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:106] - node _T_580 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] - node _T_581 = eq(_T_580, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_582 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] - node _T_583 = and(_T_576, _T_578) @[dec_tlu_ctl.scala 2570:198] - node _T_584 = and(_T_583, _T_579) @[dec_tlu_ctl.scala 2570:198] - node _T_585 = and(_T_584, _T_581) @[dec_tlu_ctl.scala 2570:198] - node _T_586 = and(_T_585, _T_582) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_mitb0 <= _T_586 @[dec_tlu_ctl.scala 2620:57] - node _T_587 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] - node _T_588 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:106] - node _T_589 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] - node _T_590 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] - node _T_591 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] - node _T_592 = eq(_T_591, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] - node _T_593 = and(_T_587, _T_588) @[dec_tlu_ctl.scala 2570:198] - node _T_594 = and(_T_593, _T_589) @[dec_tlu_ctl.scala 2570:198] - node _T_595 = and(_T_594, _T_590) @[dec_tlu_ctl.scala 2570:198] - node _T_596 = and(_T_595, _T_592) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_mitb1 <= _T_596 @[dec_tlu_ctl.scala 2621:57] - node _T_597 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] - node _T_598 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] - node _T_599 = eq(_T_598, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_600 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:106] - node _T_601 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] - node _T_602 = eq(_T_601, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_603 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] - node _T_604 = eq(_T_603, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] - node _T_605 = and(_T_597, _T_599) @[dec_tlu_ctl.scala 2570:198] - node _T_606 = and(_T_605, _T_600) @[dec_tlu_ctl.scala 2570:198] - node _T_607 = and(_T_606, _T_602) @[dec_tlu_ctl.scala 2570:198] - node _T_608 = and(_T_607, _T_604) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_mitcnt0 <= _T_608 @[dec_tlu_ctl.scala 2622:57] - node _T_609 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] - node _T_610 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] - node _T_611 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] - node _T_612 = eq(_T_611, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_613 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] - node _T_614 = and(_T_609, _T_610) @[dec_tlu_ctl.scala 2570:198] - node _T_615 = and(_T_614, _T_612) @[dec_tlu_ctl.scala 2570:198] - node _T_616 = and(_T_615, _T_613) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_mitcnt1 <= _T_616 @[dec_tlu_ctl.scala 2623:57] - node _T_617 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] - node _T_618 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] - node _T_619 = eq(_T_618, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_620 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] - node _T_621 = eq(_T_620, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_622 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] - node _T_623 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] - node _T_624 = and(_T_617, _T_619) @[dec_tlu_ctl.scala 2570:198] - node _T_625 = and(_T_624, _T_621) @[dec_tlu_ctl.scala 2570:198] - node _T_626 = and(_T_625, _T_622) @[dec_tlu_ctl.scala 2570:198] - node _T_627 = and(_T_626, _T_623) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_mpmc <= _T_627 @[dec_tlu_ctl.scala 2624:57] - node _T_628 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] - node _T_629 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] - node _T_630 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] - node _T_631 = eq(_T_630, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_632 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] - node _T_633 = eq(_T_632, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_634 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] - node _T_635 = eq(_T_634, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_636 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] - node _T_637 = and(_T_628, _T_629) @[dec_tlu_ctl.scala 2570:198] - node _T_638 = and(_T_637, _T_631) @[dec_tlu_ctl.scala 2570:198] - node _T_639 = and(_T_638, _T_633) @[dec_tlu_ctl.scala 2570:198] - node _T_640 = and(_T_639, _T_635) @[dec_tlu_ctl.scala 2570:198] - node _T_641 = and(_T_640, _T_636) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_mcpc <= _T_641 @[dec_tlu_ctl.scala 2625:57] - node _T_642 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:106] - node _T_643 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] - node _T_644 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] - node _T_645 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] - node _T_646 = eq(_T_645, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] - node _T_647 = and(_T_642, _T_643) @[dec_tlu_ctl.scala 2570:198] - node _T_648 = and(_T_647, _T_644) @[dec_tlu_ctl.scala 2570:198] - node _T_649 = and(_T_648, _T_646) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_meicpct <= _T_649 @[dec_tlu_ctl.scala 2626:57] - node _T_650 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:149] - node _T_651 = eq(_T_650, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_652 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:106] - node _T_653 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] - node _T_654 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] - node _T_655 = eq(_T_654, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_656 = and(_T_651, _T_652) @[dec_tlu_ctl.scala 2570:198] - node _T_657 = and(_T_656, _T_653) @[dec_tlu_ctl.scala 2570:198] - node _T_658 = and(_T_657, _T_655) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_mdeau <= _T_658 @[dec_tlu_ctl.scala 2627:57] - node _T_659 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] - node _T_660 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:106] - node _T_661 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] - node _T_662 = eq(_T_661, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_663 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] - node _T_664 = eq(_T_663, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_665 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] - node _T_666 = eq(_T_665, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] - node _T_667 = and(_T_659, _T_660) @[dec_tlu_ctl.scala 2570:198] - node _T_668 = and(_T_667, _T_662) @[dec_tlu_ctl.scala 2570:198] - node _T_669 = and(_T_668, _T_664) @[dec_tlu_ctl.scala 2570:198] - node _T_670 = and(_T_669, _T_666) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_micect <= _T_670 @[dec_tlu_ctl.scala 2628:57] - node _T_671 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] - node _T_672 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:106] - node _T_673 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] - node _T_674 = eq(_T_673, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_675 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] - node _T_676 = and(_T_671, _T_672) @[dec_tlu_ctl.scala 2570:198] - node _T_677 = and(_T_676, _T_674) @[dec_tlu_ctl.scala 2570:198] - node _T_678 = and(_T_677, _T_675) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_miccmect <= _T_678 @[dec_tlu_ctl.scala 2629:57] - node _T_679 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] - node _T_680 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:106] - node _T_681 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] - node _T_682 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] - node _T_683 = eq(_T_682, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] - node _T_684 = and(_T_679, _T_680) @[dec_tlu_ctl.scala 2570:198] - node _T_685 = and(_T_684, _T_681) @[dec_tlu_ctl.scala 2570:198] - node _T_686 = and(_T_685, _T_683) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_mdccmect <= _T_686 @[dec_tlu_ctl.scala 2630:57] - node _T_687 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] - node _T_688 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:106] - node _T_689 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] - node _T_690 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] - node _T_691 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] - node _T_692 = eq(_T_691, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] - node _T_693 = and(_T_687, _T_688) @[dec_tlu_ctl.scala 2570:198] - node _T_694 = and(_T_693, _T_689) @[dec_tlu_ctl.scala 2570:198] - node _T_695 = and(_T_694, _T_690) @[dec_tlu_ctl.scala 2570:198] - node _T_696 = and(_T_695, _T_692) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_mfdht <= _T_696 @[dec_tlu_ctl.scala 2631:57] - node _T_697 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] - node _T_698 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] - node _T_699 = eq(_T_698, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_700 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] - node _T_701 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] - node _T_702 = and(_T_697, _T_699) @[dec_tlu_ctl.scala 2570:198] - node _T_703 = and(_T_702, _T_700) @[dec_tlu_ctl.scala 2570:198] - node _T_704 = and(_T_703, _T_701) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_mfdhs <= _T_704 @[dec_tlu_ctl.scala 2632:57] - node _T_705 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:149] - node _T_706 = eq(_T_705, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_707 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] - node _T_708 = eq(_T_707, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_709 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:106] - node _T_710 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] - node _T_711 = eq(_T_710, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_712 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] - node _T_713 = eq(_T_712, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_714 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] - node _T_715 = eq(_T_714, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] - node _T_716 = and(_T_706, _T_708) @[dec_tlu_ctl.scala 2570:198] - node _T_717 = and(_T_716, _T_709) @[dec_tlu_ctl.scala 2570:198] - node _T_718 = and(_T_717, _T_711) @[dec_tlu_ctl.scala 2570:198] - node _T_719 = and(_T_718, _T_713) @[dec_tlu_ctl.scala 2570:198] - node _T_720 = and(_T_719, _T_715) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_dicawics <= _T_720 @[dec_tlu_ctl.scala 2633:57] - node _T_721 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] - node _T_722 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:106] - node _T_723 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] - node _T_724 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] - node _T_725 = eq(_T_724, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_726 = and(_T_721, _T_722) @[dec_tlu_ctl.scala 2570:198] - node _T_727 = and(_T_726, _T_723) @[dec_tlu_ctl.scala 2570:198] - node _T_728 = and(_T_727, _T_725) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_dicad0h <= _T_728 @[dec_tlu_ctl.scala 2634:57] - node _T_729 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] - node _T_730 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] - node _T_731 = eq(_T_730, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_732 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:106] - node _T_733 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] - node _T_734 = eq(_T_733, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_735 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] - node _T_736 = and(_T_729, _T_731) @[dec_tlu_ctl.scala 2570:198] - node _T_737 = and(_T_736, _T_732) @[dec_tlu_ctl.scala 2570:198] - node _T_738 = and(_T_737, _T_734) @[dec_tlu_ctl.scala 2570:198] - node _T_739 = and(_T_738, _T_735) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_dicad0 <= _T_739 @[dec_tlu_ctl.scala 2635:57] - node _T_740 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] - node _T_741 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:106] - node _T_742 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] - node _T_743 = eq(_T_742, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_744 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] - node _T_745 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] - node _T_746 = eq(_T_745, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] - node _T_747 = and(_T_740, _T_741) @[dec_tlu_ctl.scala 2570:198] - node _T_748 = and(_T_747, _T_743) @[dec_tlu_ctl.scala 2570:198] - node _T_749 = and(_T_748, _T_744) @[dec_tlu_ctl.scala 2570:198] - node _T_750 = and(_T_749, _T_746) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_dicad1 <= _T_750 @[dec_tlu_ctl.scala 2636:57] - node _T_751 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] - node _T_752 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:106] - node _T_753 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] - node _T_754 = eq(_T_753, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_755 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] - node _T_756 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] - node _T_757 = and(_T_751, _T_752) @[dec_tlu_ctl.scala 2570:198] - node _T_758 = and(_T_757, _T_754) @[dec_tlu_ctl.scala 2570:198] - node _T_759 = and(_T_758, _T_755) @[dec_tlu_ctl.scala 2570:198] - node _T_760 = and(_T_759, _T_756) @[dec_tlu_ctl.scala 2570:198] - io.csr_pkt.csr_dicago <= _T_760 @[dec_tlu_ctl.scala 2637:57] - node _T_761 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] - node _T_762 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:106] - node _T_763 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:106] - node _T_764 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] - node _T_765 = eq(_T_764, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_766 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] - node _T_767 = and(_T_761, _T_762) @[dec_tlu_ctl.scala 2570:198] - node _T_768 = and(_T_767, _T_763) @[dec_tlu_ctl.scala 2570:198] - node _T_769 = and(_T_768, _T_765) @[dec_tlu_ctl.scala 2570:198] - node _T_770 = and(_T_769, _T_766) @[dec_tlu_ctl.scala 2570:198] - node _T_771 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] - node _T_772 = eq(_T_771, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_773 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:106] - node _T_774 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] - node _T_775 = eq(_T_774, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_776 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] - node _T_777 = eq(_T_776, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_778 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] - node _T_779 = eq(_T_778, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_780 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] - node _T_781 = eq(_T_780, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] - node _T_782 = and(_T_772, _T_773) @[dec_tlu_ctl.scala 2570:198] - node _T_783 = and(_T_782, _T_775) @[dec_tlu_ctl.scala 2570:198] - node _T_784 = and(_T_783, _T_777) @[dec_tlu_ctl.scala 2570:198] - node _T_785 = and(_T_784, _T_779) @[dec_tlu_ctl.scala 2570:198] - node _T_786 = and(_T_785, _T_781) @[dec_tlu_ctl.scala 2570:198] - node _T_787 = or(_T_770, _T_786) @[dec_tlu_ctl.scala 2638:81] - node _T_788 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] - node _T_789 = eq(_T_788, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_790 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] - node _T_791 = eq(_T_790, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_792 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] - node _T_793 = eq(_T_792, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_794 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] - node _T_795 = eq(_T_794, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_796 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] - node _T_797 = eq(_T_796, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_798 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] - node _T_799 = and(_T_789, _T_791) @[dec_tlu_ctl.scala 2570:198] - node _T_800 = and(_T_799, _T_793) @[dec_tlu_ctl.scala 2570:198] - node _T_801 = and(_T_800, _T_795) @[dec_tlu_ctl.scala 2570:198] - node _T_802 = and(_T_801, _T_797) @[dec_tlu_ctl.scala 2570:198] - node _T_803 = and(_T_802, _T_798) @[dec_tlu_ctl.scala 2570:198] - node _T_804 = or(_T_787, _T_803) @[dec_tlu_ctl.scala 2638:121] - node _T_805 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:106] - node _T_806 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] - node _T_807 = eq(_T_806, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_808 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] - node _T_809 = eq(_T_808, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_810 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] - node _T_811 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] - node _T_812 = eq(_T_811, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_813 = and(_T_805, _T_807) @[dec_tlu_ctl.scala 2570:198] - node _T_814 = and(_T_813, _T_809) @[dec_tlu_ctl.scala 2570:198] - node _T_815 = and(_T_814, _T_810) @[dec_tlu_ctl.scala 2570:198] - node _T_816 = and(_T_815, _T_812) @[dec_tlu_ctl.scala 2570:198] - node _T_817 = or(_T_804, _T_816) @[dec_tlu_ctl.scala 2638:155] - node _T_818 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:106] - node _T_819 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] - node _T_820 = eq(_T_819, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_821 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] - node _T_822 = eq(_T_821, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_823 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] - node _T_824 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] - node _T_825 = eq(_T_824, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] - node _T_826 = and(_T_818, _T_820) @[dec_tlu_ctl.scala 2570:198] - node _T_827 = and(_T_826, _T_822) @[dec_tlu_ctl.scala 2570:198] - node _T_828 = and(_T_827, _T_823) @[dec_tlu_ctl.scala 2570:198] - node _T_829 = and(_T_828, _T_825) @[dec_tlu_ctl.scala 2570:198] - node _T_830 = or(_T_817, _T_829) @[dec_tlu_ctl.scala 2639:97] - node _T_831 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:106] - node _T_832 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] - node _T_833 = eq(_T_832, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_834 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] - node _T_835 = eq(_T_834, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_836 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] - node _T_837 = eq(_T_836, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_838 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] - node _T_839 = eq(_T_838, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_840 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] - node _T_841 = and(_T_831, _T_833) @[dec_tlu_ctl.scala 2570:198] - node _T_842 = and(_T_841, _T_835) @[dec_tlu_ctl.scala 2570:198] - node _T_843 = and(_T_842, _T_837) @[dec_tlu_ctl.scala 2570:198] - node _T_844 = and(_T_843, _T_839) @[dec_tlu_ctl.scala 2570:198] - node _T_845 = and(_T_844, _T_840) @[dec_tlu_ctl.scala 2570:198] - node _T_846 = or(_T_830, _T_845) @[dec_tlu_ctl.scala 2639:137] - io.csr_pkt.presync <= _T_846 @[dec_tlu_ctl.scala 2638:34] - node _T_847 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] - node _T_848 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:106] - node _T_849 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:106] - node _T_850 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] - node _T_851 = eq(_T_850, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_852 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] - node _T_853 = and(_T_847, _T_848) @[dec_tlu_ctl.scala 2570:198] - node _T_854 = and(_T_853, _T_849) @[dec_tlu_ctl.scala 2570:198] - node _T_855 = and(_T_854, _T_851) @[dec_tlu_ctl.scala 2570:198] - node _T_856 = and(_T_855, _T_852) @[dec_tlu_ctl.scala 2570:198] - node _T_857 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:149] - node _T_858 = eq(_T_857, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_859 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] - node _T_860 = eq(_T_859, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_861 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] - node _T_862 = eq(_T_861, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_863 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] - node _T_864 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] - node _T_865 = and(_T_858, _T_860) @[dec_tlu_ctl.scala 2570:198] - node _T_866 = and(_T_865, _T_862) @[dec_tlu_ctl.scala 2570:198] - node _T_867 = and(_T_866, _T_863) @[dec_tlu_ctl.scala 2570:198] - node _T_868 = and(_T_867, _T_864) @[dec_tlu_ctl.scala 2570:198] - node _T_869 = or(_T_856, _T_868) @[dec_tlu_ctl.scala 2640:81] - node _T_870 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] - node _T_871 = eq(_T_870, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_872 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] - node _T_873 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] - node _T_874 = eq(_T_873, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_875 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] - node _T_876 = and(_T_871, _T_872) @[dec_tlu_ctl.scala 2570:198] - node _T_877 = and(_T_876, _T_874) @[dec_tlu_ctl.scala 2570:198] - node _T_878 = and(_T_877, _T_875) @[dec_tlu_ctl.scala 2570:198] - node _T_879 = or(_T_869, _T_878) @[dec_tlu_ctl.scala 2640:121] - node _T_880 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] - node _T_881 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] - node _T_882 = eq(_T_881, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_883 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] - node _T_884 = eq(_T_883, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_885 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] - node _T_886 = and(_T_880, _T_882) @[dec_tlu_ctl.scala 2570:198] - node _T_887 = and(_T_886, _T_884) @[dec_tlu_ctl.scala 2570:198] - node _T_888 = and(_T_887, _T_885) @[dec_tlu_ctl.scala 2570:198] - node _T_889 = or(_T_879, _T_888) @[dec_tlu_ctl.scala 2640:162] - node _T_890 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:149] - node _T_891 = eq(_T_890, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_892 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] - node _T_893 = eq(_T_892, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_894 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] - node _T_895 = eq(_T_894, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_896 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] - node _T_897 = eq(_T_896, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_898 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] - node _T_899 = eq(_T_898, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_900 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] - node _T_901 = eq(_T_900, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_902 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] - node _T_903 = eq(_T_902, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] - node _T_904 = and(_T_891, _T_893) @[dec_tlu_ctl.scala 2570:198] - node _T_905 = and(_T_904, _T_895) @[dec_tlu_ctl.scala 2570:198] - node _T_906 = and(_T_905, _T_897) @[dec_tlu_ctl.scala 2570:198] - node _T_907 = and(_T_906, _T_899) @[dec_tlu_ctl.scala 2570:198] - node _T_908 = and(_T_907, _T_901) @[dec_tlu_ctl.scala 2570:198] - node _T_909 = and(_T_908, _T_903) @[dec_tlu_ctl.scala 2570:198] - node _T_910 = or(_T_889, _T_909) @[dec_tlu_ctl.scala 2641:105] - node _T_911 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:149] - node _T_912 = eq(_T_911, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_913 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:106] - node _T_914 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] - node _T_915 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] - node _T_916 = eq(_T_915, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_917 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] - node _T_918 = eq(_T_917, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_919 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] - node _T_920 = eq(_T_919, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_921 = and(_T_912, _T_913) @[dec_tlu_ctl.scala 2570:198] - node _T_922 = and(_T_921, _T_914) @[dec_tlu_ctl.scala 2570:198] - node _T_923 = and(_T_922, _T_916) @[dec_tlu_ctl.scala 2570:198] - node _T_924 = and(_T_923, _T_918) @[dec_tlu_ctl.scala 2570:198] - node _T_925 = and(_T_924, _T_920) @[dec_tlu_ctl.scala 2570:198] - node _T_926 = or(_T_910, _T_925) @[dec_tlu_ctl.scala 2641:145] - node _T_927 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] - node _T_928 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] - node _T_929 = eq(_T_928, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_930 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] - node _T_931 = eq(_T_930, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_932 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] - node _T_933 = eq(_T_932, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_934 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] - node _T_935 = and(_T_927, _T_929) @[dec_tlu_ctl.scala 2570:198] - node _T_936 = and(_T_935, _T_931) @[dec_tlu_ctl.scala 2570:198] - node _T_937 = and(_T_936, _T_933) @[dec_tlu_ctl.scala 2570:198] - node _T_938 = and(_T_937, _T_934) @[dec_tlu_ctl.scala 2570:198] - node _T_939 = or(_T_926, _T_938) @[dec_tlu_ctl.scala 2641:178] - io.csr_pkt.postsync <= _T_939 @[dec_tlu_ctl.scala 2640:30] - node _T_940 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:149] - node _T_941 = eq(_T_940, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_942 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] - node _T_943 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] - node _T_944 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] - node _T_945 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:106] - node _T_946 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] - node _T_947 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:106] - node _T_948 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] - node _T_949 = eq(_T_948, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_950 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] - node _T_951 = eq(_T_950, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_952 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] - node _T_953 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] - node _T_954 = eq(_T_953, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] - node _T_955 = and(_T_941, _T_942) @[dec_tlu_ctl.scala 2570:198] - node _T_956 = and(_T_955, _T_943) @[dec_tlu_ctl.scala 2570:198] - node _T_957 = and(_T_956, _T_944) @[dec_tlu_ctl.scala 2570:198] - node _T_958 = and(_T_957, _T_945) @[dec_tlu_ctl.scala 2570:198] - node _T_959 = and(_T_958, _T_946) @[dec_tlu_ctl.scala 2570:198] - node _T_960 = and(_T_959, _T_947) @[dec_tlu_ctl.scala 2570:198] - node _T_961 = and(_T_960, _T_949) @[dec_tlu_ctl.scala 2570:198] - node _T_962 = and(_T_961, _T_951) @[dec_tlu_ctl.scala 2570:198] - node _T_963 = and(_T_962, _T_952) @[dec_tlu_ctl.scala 2570:198] - node _T_964 = and(_T_963, _T_954) @[dec_tlu_ctl.scala 2570:198] - node _T_965 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:149] - node _T_966 = eq(_T_965, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_967 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:149] - node _T_968 = eq(_T_967, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_969 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] - node _T_970 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] - node _T_971 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] - node _T_972 = eq(_T_971, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_973 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] - node _T_974 = eq(_T_973, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_975 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] - node _T_976 = eq(_T_975, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_977 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] - node _T_978 = eq(_T_977, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_979 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] - node _T_980 = eq(_T_979, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_981 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] - node _T_982 = eq(_T_981, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_983 = and(_T_966, _T_968) @[dec_tlu_ctl.scala 2570:198] - node _T_984 = and(_T_983, _T_969) @[dec_tlu_ctl.scala 2570:198] - node _T_985 = and(_T_984, _T_970) @[dec_tlu_ctl.scala 2570:198] - node _T_986 = and(_T_985, _T_972) @[dec_tlu_ctl.scala 2570:198] - node _T_987 = and(_T_986, _T_974) @[dec_tlu_ctl.scala 2570:198] - node _T_988 = and(_T_987, _T_976) @[dec_tlu_ctl.scala 2570:198] - node _T_989 = and(_T_988, _T_978) @[dec_tlu_ctl.scala 2570:198] - node _T_990 = and(_T_989, _T_980) @[dec_tlu_ctl.scala 2570:198] - node _T_991 = and(_T_990, _T_982) @[dec_tlu_ctl.scala 2570:198] - node _T_992 = or(_T_964, _T_991) @[dec_tlu_ctl.scala 2643:81] - node _T_993 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:149] - node _T_994 = eq(_T_993, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_995 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:149] - node _T_996 = eq(_T_995, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_997 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] - node _T_998 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] - node _T_999 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] - node _T_1000 = eq(_T_999, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1001 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] - node _T_1002 = eq(_T_1001, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1003 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:106] - node _T_1004 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] - node _T_1005 = eq(_T_1004, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1006 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] - node _T_1007 = eq(_T_1006, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] - node _T_1008 = and(_T_994, _T_996) @[dec_tlu_ctl.scala 2570:198] - node _T_1009 = and(_T_1008, _T_997) @[dec_tlu_ctl.scala 2570:198] - node _T_1010 = and(_T_1009, _T_998) @[dec_tlu_ctl.scala 2570:198] - node _T_1011 = and(_T_1010, _T_1000) @[dec_tlu_ctl.scala 2570:198] - node _T_1012 = and(_T_1011, _T_1002) @[dec_tlu_ctl.scala 2570:198] - node _T_1013 = and(_T_1012, _T_1003) @[dec_tlu_ctl.scala 2570:198] - node _T_1014 = and(_T_1013, _T_1005) @[dec_tlu_ctl.scala 2570:198] - node _T_1015 = and(_T_1014, _T_1007) @[dec_tlu_ctl.scala 2570:198] - node _T_1016 = or(_T_992, _T_1015) @[dec_tlu_ctl.scala 2643:129] - node _T_1017 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:106] - node _T_1018 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] - node _T_1019 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] - node _T_1020 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:106] - node _T_1021 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] - node _T_1022 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] - node _T_1023 = eq(_T_1022, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1024 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] - node _T_1025 = eq(_T_1024, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1026 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] - node _T_1027 = eq(_T_1026, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1028 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] - node _T_1029 = eq(_T_1028, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1030 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] - node _T_1031 = eq(_T_1030, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] - node _T_1032 = and(_T_1017, _T_1018) @[dec_tlu_ctl.scala 2570:198] - node _T_1033 = and(_T_1032, _T_1019) @[dec_tlu_ctl.scala 2570:198] - node _T_1034 = and(_T_1033, _T_1020) @[dec_tlu_ctl.scala 2570:198] - node _T_1035 = and(_T_1034, _T_1021) @[dec_tlu_ctl.scala 2570:198] - node _T_1036 = and(_T_1035, _T_1023) @[dec_tlu_ctl.scala 2570:198] - node _T_1037 = and(_T_1036, _T_1025) @[dec_tlu_ctl.scala 2570:198] - node _T_1038 = and(_T_1037, _T_1027) @[dec_tlu_ctl.scala 2570:198] - node _T_1039 = and(_T_1038, _T_1029) @[dec_tlu_ctl.scala 2570:198] - node _T_1040 = and(_T_1039, _T_1031) @[dec_tlu_ctl.scala 2570:198] - node _T_1041 = or(_T_1016, _T_1040) @[dec_tlu_ctl.scala 2644:105] - node _T_1042 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:106] - node _T_1043 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:149] - node _T_1044 = eq(_T_1043, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1045 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] - node _T_1046 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] - node _T_1047 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] - node _T_1048 = eq(_T_1047, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1049 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] - node _T_1050 = eq(_T_1049, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1051 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] - node _T_1052 = eq(_T_1051, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] - node _T_1053 = and(_T_1042, _T_1044) @[dec_tlu_ctl.scala 2570:198] - node _T_1054 = and(_T_1053, _T_1045) @[dec_tlu_ctl.scala 2570:198] - node _T_1055 = and(_T_1054, _T_1046) @[dec_tlu_ctl.scala 2570:198] - node _T_1056 = and(_T_1055, _T_1048) @[dec_tlu_ctl.scala 2570:198] - node _T_1057 = and(_T_1056, _T_1050) @[dec_tlu_ctl.scala 2570:198] - node _T_1058 = and(_T_1057, _T_1052) @[dec_tlu_ctl.scala 2570:198] - node _T_1059 = or(_T_1041, _T_1058) @[dec_tlu_ctl.scala 2644:153] - node _T_1060 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:149] - node _T_1061 = eq(_T_1060, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1062 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] - node _T_1063 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] - node _T_1064 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] - node _T_1065 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:106] - node _T_1066 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] - node _T_1067 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:106] - node _T_1068 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:106] - node _T_1069 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:106] - node _T_1070 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] - node _T_1071 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] - node _T_1072 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] - node _T_1073 = and(_T_1061, _T_1062) @[dec_tlu_ctl.scala 2570:198] - node _T_1074 = and(_T_1073, _T_1063) @[dec_tlu_ctl.scala 2570:198] - node _T_1075 = and(_T_1074, _T_1064) @[dec_tlu_ctl.scala 2570:198] - node _T_1076 = and(_T_1075, _T_1065) @[dec_tlu_ctl.scala 2570:198] - node _T_1077 = and(_T_1076, _T_1066) @[dec_tlu_ctl.scala 2570:198] - node _T_1078 = and(_T_1077, _T_1067) @[dec_tlu_ctl.scala 2570:198] - node _T_1079 = and(_T_1078, _T_1068) @[dec_tlu_ctl.scala 2570:198] - node _T_1080 = and(_T_1079, _T_1069) @[dec_tlu_ctl.scala 2570:198] - node _T_1081 = and(_T_1080, _T_1070) @[dec_tlu_ctl.scala 2570:198] - node _T_1082 = and(_T_1081, _T_1071) @[dec_tlu_ctl.scala 2570:198] - node _T_1083 = and(_T_1082, _T_1072) @[dec_tlu_ctl.scala 2570:198] - node _T_1084 = or(_T_1059, _T_1083) @[dec_tlu_ctl.scala 2645:105] - node _T_1085 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:149] - node _T_1086 = eq(_T_1085, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1087 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] - node _T_1088 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] - node _T_1089 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] - node _T_1090 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:106] - node _T_1091 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] - node _T_1092 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:106] - node _T_1093 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:106] - node _T_1094 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] - node _T_1095 = eq(_T_1094, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1096 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] - node _T_1097 = eq(_T_1096, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1098 = and(_T_1086, _T_1087) @[dec_tlu_ctl.scala 2570:198] - node _T_1099 = and(_T_1098, _T_1088) @[dec_tlu_ctl.scala 2570:198] - node _T_1100 = and(_T_1099, _T_1089) @[dec_tlu_ctl.scala 2570:198] - node _T_1101 = and(_T_1100, _T_1090) @[dec_tlu_ctl.scala 2570:198] - node _T_1102 = and(_T_1101, _T_1091) @[dec_tlu_ctl.scala 2570:198] - node _T_1103 = and(_T_1102, _T_1092) @[dec_tlu_ctl.scala 2570:198] - node _T_1104 = and(_T_1103, _T_1093) @[dec_tlu_ctl.scala 2570:198] - node _T_1105 = and(_T_1104, _T_1095) @[dec_tlu_ctl.scala 2570:198] - node _T_1106 = and(_T_1105, _T_1097) @[dec_tlu_ctl.scala 2570:198] - node _T_1107 = or(_T_1084, _T_1106) @[dec_tlu_ctl.scala 2645:153] - node _T_1108 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:106] - node _T_1109 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] - node _T_1110 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] - node _T_1111 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] - node _T_1112 = eq(_T_1111, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1113 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] - node _T_1114 = eq(_T_1113, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1115 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] - node _T_1116 = eq(_T_1115, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1117 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:106] - node _T_1118 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] - node _T_1119 = eq(_T_1118, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1120 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] - node _T_1121 = eq(_T_1120, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1122 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] - node _T_1123 = and(_T_1108, _T_1109) @[dec_tlu_ctl.scala 2570:198] - node _T_1124 = and(_T_1123, _T_1110) @[dec_tlu_ctl.scala 2570:198] - node _T_1125 = and(_T_1124, _T_1112) @[dec_tlu_ctl.scala 2570:198] - node _T_1126 = and(_T_1125, _T_1114) @[dec_tlu_ctl.scala 2570:198] - node _T_1127 = and(_T_1126, _T_1116) @[dec_tlu_ctl.scala 2570:198] - node _T_1128 = and(_T_1127, _T_1117) @[dec_tlu_ctl.scala 2570:198] - node _T_1129 = and(_T_1128, _T_1119) @[dec_tlu_ctl.scala 2570:198] - node _T_1130 = and(_T_1129, _T_1121) @[dec_tlu_ctl.scala 2570:198] - node _T_1131 = and(_T_1130, _T_1122) @[dec_tlu_ctl.scala 2570:198] - node _T_1132 = or(_T_1107, _T_1131) @[dec_tlu_ctl.scala 2646:105] - node _T_1133 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:149] - node _T_1134 = eq(_T_1133, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1135 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] - node _T_1136 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] - node _T_1137 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] - node _T_1138 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:106] - node _T_1139 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] - node _T_1140 = eq(_T_1139, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1141 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:106] - node _T_1142 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] - node _T_1143 = eq(_T_1142, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1144 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] - node _T_1145 = eq(_T_1144, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1146 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] - node _T_1147 = eq(_T_1146, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1148 = and(_T_1134, _T_1135) @[dec_tlu_ctl.scala 2570:198] - node _T_1149 = and(_T_1148, _T_1136) @[dec_tlu_ctl.scala 2570:198] - node _T_1150 = and(_T_1149, _T_1137) @[dec_tlu_ctl.scala 2570:198] - node _T_1151 = and(_T_1150, _T_1138) @[dec_tlu_ctl.scala 2570:198] - node _T_1152 = and(_T_1151, _T_1140) @[dec_tlu_ctl.scala 2570:198] - node _T_1153 = and(_T_1152, _T_1141) @[dec_tlu_ctl.scala 2570:198] - node _T_1154 = and(_T_1153, _T_1143) @[dec_tlu_ctl.scala 2570:198] - node _T_1155 = and(_T_1154, _T_1145) @[dec_tlu_ctl.scala 2570:198] - node _T_1156 = and(_T_1155, _T_1147) @[dec_tlu_ctl.scala 2570:198] - node _T_1157 = or(_T_1132, _T_1156) @[dec_tlu_ctl.scala 2646:161] - node _T_1158 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:149] - node _T_1159 = eq(_T_1158, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1160 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:149] - node _T_1161 = eq(_T_1160, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1162 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] - node _T_1163 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] - node _T_1164 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] - node _T_1165 = eq(_T_1164, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1166 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] - node _T_1167 = eq(_T_1166, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1168 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:106] - node _T_1169 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] - node _T_1170 = and(_T_1159, _T_1161) @[dec_tlu_ctl.scala 2570:198] - node _T_1171 = and(_T_1170, _T_1162) @[dec_tlu_ctl.scala 2570:198] - node _T_1172 = and(_T_1171, _T_1163) @[dec_tlu_ctl.scala 2570:198] - node _T_1173 = and(_T_1172, _T_1165) @[dec_tlu_ctl.scala 2570:198] - node _T_1174 = and(_T_1173, _T_1167) @[dec_tlu_ctl.scala 2570:198] - node _T_1175 = and(_T_1174, _T_1168) @[dec_tlu_ctl.scala 2570:198] - node _T_1176 = and(_T_1175, _T_1169) @[dec_tlu_ctl.scala 2570:198] - node _T_1177 = or(_T_1157, _T_1176) @[dec_tlu_ctl.scala 2647:105] - node _T_1178 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:106] - node _T_1179 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] - node _T_1180 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] - node _T_1181 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] - node _T_1182 = eq(_T_1181, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1183 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] - node _T_1184 = eq(_T_1183, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1185 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] - node _T_1186 = eq(_T_1185, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1187 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:106] - node _T_1188 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] - node _T_1189 = eq(_T_1188, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1190 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] - node _T_1191 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] - node _T_1192 = eq(_T_1191, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1193 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] - node _T_1194 = eq(_T_1193, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] - node _T_1195 = and(_T_1178, _T_1179) @[dec_tlu_ctl.scala 2570:198] - node _T_1196 = and(_T_1195, _T_1180) @[dec_tlu_ctl.scala 2570:198] - node _T_1197 = and(_T_1196, _T_1182) @[dec_tlu_ctl.scala 2570:198] - node _T_1198 = and(_T_1197, _T_1184) @[dec_tlu_ctl.scala 2570:198] - node _T_1199 = and(_T_1198, _T_1186) @[dec_tlu_ctl.scala 2570:198] - node _T_1200 = and(_T_1199, _T_1187) @[dec_tlu_ctl.scala 2570:198] - node _T_1201 = and(_T_1200, _T_1189) @[dec_tlu_ctl.scala 2570:198] - node _T_1202 = and(_T_1201, _T_1190) @[dec_tlu_ctl.scala 2570:198] - node _T_1203 = and(_T_1202, _T_1192) @[dec_tlu_ctl.scala 2570:198] - node _T_1204 = and(_T_1203, _T_1194) @[dec_tlu_ctl.scala 2570:198] - node _T_1205 = or(_T_1177, _T_1204) @[dec_tlu_ctl.scala 2647:161] - node _T_1206 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:149] - node _T_1207 = eq(_T_1206, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1208 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] - node _T_1209 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] - node _T_1210 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] - node _T_1211 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:106] - node _T_1212 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] - node _T_1213 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] - node _T_1214 = eq(_T_1213, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1215 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] - node _T_1216 = eq(_T_1215, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1217 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:106] - node _T_1218 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] - node _T_1219 = and(_T_1207, _T_1208) @[dec_tlu_ctl.scala 2570:198] - node _T_1220 = and(_T_1219, _T_1209) @[dec_tlu_ctl.scala 2570:198] - node _T_1221 = and(_T_1220, _T_1210) @[dec_tlu_ctl.scala 2570:198] - node _T_1222 = and(_T_1221, _T_1211) @[dec_tlu_ctl.scala 2570:198] - node _T_1223 = and(_T_1222, _T_1212) @[dec_tlu_ctl.scala 2570:198] - node _T_1224 = and(_T_1223, _T_1214) @[dec_tlu_ctl.scala 2570:198] - node _T_1225 = and(_T_1224, _T_1216) @[dec_tlu_ctl.scala 2570:198] - node _T_1226 = and(_T_1225, _T_1217) @[dec_tlu_ctl.scala 2570:198] - node _T_1227 = and(_T_1226, _T_1218) @[dec_tlu_ctl.scala 2570:198] - node _T_1228 = or(_T_1205, _T_1227) @[dec_tlu_ctl.scala 2648:97] - node _T_1229 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:149] - node _T_1230 = eq(_T_1229, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1231 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] - node _T_1232 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] - node _T_1233 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] - node _T_1234 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:106] - node _T_1235 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] - node _T_1236 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] - node _T_1237 = eq(_T_1236, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1238 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:106] - node _T_1239 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] - node _T_1240 = eq(_T_1239, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1241 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] - node _T_1242 = and(_T_1230, _T_1231) @[dec_tlu_ctl.scala 2570:198] - node _T_1243 = and(_T_1242, _T_1232) @[dec_tlu_ctl.scala 2570:198] - node _T_1244 = and(_T_1243, _T_1233) @[dec_tlu_ctl.scala 2570:198] - node _T_1245 = and(_T_1244, _T_1234) @[dec_tlu_ctl.scala 2570:198] - node _T_1246 = and(_T_1245, _T_1235) @[dec_tlu_ctl.scala 2570:198] - node _T_1247 = and(_T_1246, _T_1237) @[dec_tlu_ctl.scala 2570:198] - node _T_1248 = and(_T_1247, _T_1238) @[dec_tlu_ctl.scala 2570:198] - node _T_1249 = and(_T_1248, _T_1240) @[dec_tlu_ctl.scala 2570:198] - node _T_1250 = and(_T_1249, _T_1241) @[dec_tlu_ctl.scala 2570:198] - node _T_1251 = or(_T_1228, _T_1250) @[dec_tlu_ctl.scala 2648:153] - node _T_1252 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:106] - node _T_1253 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] - node _T_1254 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] - node _T_1255 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] - node _T_1256 = eq(_T_1255, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1257 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] - node _T_1258 = eq(_T_1257, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1259 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] - node _T_1260 = eq(_T_1259, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1261 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:106] - node _T_1262 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] - node _T_1263 = eq(_T_1262, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1264 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] - node _T_1265 = eq(_T_1264, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1266 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] - node _T_1267 = and(_T_1252, _T_1253) @[dec_tlu_ctl.scala 2570:198] - node _T_1268 = and(_T_1267, _T_1254) @[dec_tlu_ctl.scala 2570:198] - node _T_1269 = and(_T_1268, _T_1256) @[dec_tlu_ctl.scala 2570:198] - node _T_1270 = and(_T_1269, _T_1258) @[dec_tlu_ctl.scala 2570:198] - node _T_1271 = and(_T_1270, _T_1260) @[dec_tlu_ctl.scala 2570:198] - node _T_1272 = and(_T_1271, _T_1261) @[dec_tlu_ctl.scala 2570:198] - node _T_1273 = and(_T_1272, _T_1263) @[dec_tlu_ctl.scala 2570:198] - node _T_1274 = and(_T_1273, _T_1265) @[dec_tlu_ctl.scala 2570:198] - node _T_1275 = and(_T_1274, _T_1266) @[dec_tlu_ctl.scala 2570:198] - node _T_1276 = or(_T_1251, _T_1275) @[dec_tlu_ctl.scala 2649:105] - node _T_1277 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:149] - node _T_1278 = eq(_T_1277, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1279 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:149] - node _T_1280 = eq(_T_1279, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1281 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] - node _T_1282 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] - node _T_1283 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] - node _T_1284 = eq(_T_1283, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1285 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] - node _T_1286 = eq(_T_1285, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1287 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:106] - node _T_1288 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] - node _T_1289 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] - node _T_1290 = and(_T_1278, _T_1280) @[dec_tlu_ctl.scala 2570:198] - node _T_1291 = and(_T_1290, _T_1281) @[dec_tlu_ctl.scala 2570:198] - node _T_1292 = and(_T_1291, _T_1282) @[dec_tlu_ctl.scala 2570:198] - node _T_1293 = and(_T_1292, _T_1284) @[dec_tlu_ctl.scala 2570:198] - node _T_1294 = and(_T_1293, _T_1286) @[dec_tlu_ctl.scala 2570:198] - node _T_1295 = and(_T_1294, _T_1287) @[dec_tlu_ctl.scala 2570:198] - node _T_1296 = and(_T_1295, _T_1288) @[dec_tlu_ctl.scala 2570:198] - node _T_1297 = and(_T_1296, _T_1289) @[dec_tlu_ctl.scala 2570:198] - node _T_1298 = or(_T_1276, _T_1297) @[dec_tlu_ctl.scala 2649:161] - node _T_1299 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:106] - node _T_1300 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:149] - node _T_1301 = eq(_T_1300, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1302 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] - node _T_1303 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] - node _T_1304 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:106] - node _T_1305 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] - node _T_1306 = eq(_T_1305, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1307 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] - node _T_1308 = eq(_T_1307, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1309 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:106] - node _T_1310 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] - node _T_1311 = eq(_T_1310, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1312 = and(_T_1299, _T_1301) @[dec_tlu_ctl.scala 2570:198] - node _T_1313 = and(_T_1312, _T_1302) @[dec_tlu_ctl.scala 2570:198] - node _T_1314 = and(_T_1313, _T_1303) @[dec_tlu_ctl.scala 2570:198] - node _T_1315 = and(_T_1314, _T_1304) @[dec_tlu_ctl.scala 2570:198] - node _T_1316 = and(_T_1315, _T_1306) @[dec_tlu_ctl.scala 2570:198] - node _T_1317 = and(_T_1316, _T_1308) @[dec_tlu_ctl.scala 2570:198] - node _T_1318 = and(_T_1317, _T_1309) @[dec_tlu_ctl.scala 2570:198] - node _T_1319 = and(_T_1318, _T_1311) @[dec_tlu_ctl.scala 2570:198] - node _T_1320 = or(_T_1298, _T_1319) @[dec_tlu_ctl.scala 2650:105] - node _T_1321 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:106] - node _T_1322 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:149] - node _T_1323 = eq(_T_1322, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1324 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] - node _T_1325 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] - node _T_1326 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:106] - node _T_1327 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] - node _T_1328 = eq(_T_1327, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1329 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] - node _T_1330 = eq(_T_1329, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1331 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:106] - node _T_1332 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] - node _T_1333 = eq(_T_1332, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1334 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] - node _T_1335 = eq(_T_1334, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] - node _T_1336 = and(_T_1321, _T_1323) @[dec_tlu_ctl.scala 2570:198] - node _T_1337 = and(_T_1336, _T_1324) @[dec_tlu_ctl.scala 2570:198] - node _T_1338 = and(_T_1337, _T_1325) @[dec_tlu_ctl.scala 2570:198] - node _T_1339 = and(_T_1338, _T_1326) @[dec_tlu_ctl.scala 2570:198] - node _T_1340 = and(_T_1339, _T_1328) @[dec_tlu_ctl.scala 2570:198] - node _T_1341 = and(_T_1340, _T_1330) @[dec_tlu_ctl.scala 2570:198] - node _T_1342 = and(_T_1341, _T_1331) @[dec_tlu_ctl.scala 2570:198] - node _T_1343 = and(_T_1342, _T_1333) @[dec_tlu_ctl.scala 2570:198] - node _T_1344 = and(_T_1343, _T_1335) @[dec_tlu_ctl.scala 2570:198] - node _T_1345 = or(_T_1320, _T_1344) @[dec_tlu_ctl.scala 2650:161] - node _T_1346 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:106] - node _T_1347 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:149] - node _T_1348 = eq(_T_1347, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1349 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] - node _T_1350 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] - node _T_1351 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] - node _T_1352 = eq(_T_1351, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1353 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] - node _T_1354 = eq(_T_1353, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1355 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] - node _T_1356 = and(_T_1346, _T_1348) @[dec_tlu_ctl.scala 2570:198] - node _T_1357 = and(_T_1356, _T_1349) @[dec_tlu_ctl.scala 2570:198] - node _T_1358 = and(_T_1357, _T_1350) @[dec_tlu_ctl.scala 2570:198] - node _T_1359 = and(_T_1358, _T_1352) @[dec_tlu_ctl.scala 2570:198] - node _T_1360 = and(_T_1359, _T_1354) @[dec_tlu_ctl.scala 2570:198] - node _T_1361 = and(_T_1360, _T_1355) @[dec_tlu_ctl.scala 2570:198] - node _T_1362 = or(_T_1345, _T_1361) @[dec_tlu_ctl.scala 2651:105] - node _T_1363 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:149] - node _T_1364 = eq(_T_1363, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1365 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] - node _T_1366 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] - node _T_1367 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] - node _T_1368 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:106] - node _T_1369 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] - node _T_1370 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] - node _T_1371 = eq(_T_1370, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1372 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:106] - node _T_1373 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] - node _T_1374 = eq(_T_1373, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1375 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] - node _T_1376 = and(_T_1364, _T_1365) @[dec_tlu_ctl.scala 2570:198] - node _T_1377 = and(_T_1376, _T_1366) @[dec_tlu_ctl.scala 2570:198] - node _T_1378 = and(_T_1377, _T_1367) @[dec_tlu_ctl.scala 2570:198] - node _T_1379 = and(_T_1378, _T_1368) @[dec_tlu_ctl.scala 2570:198] - node _T_1380 = and(_T_1379, _T_1369) @[dec_tlu_ctl.scala 2570:198] - node _T_1381 = and(_T_1380, _T_1371) @[dec_tlu_ctl.scala 2570:198] - node _T_1382 = and(_T_1381, _T_1372) @[dec_tlu_ctl.scala 2570:198] - node _T_1383 = and(_T_1382, _T_1374) @[dec_tlu_ctl.scala 2570:198] - node _T_1384 = and(_T_1383, _T_1375) @[dec_tlu_ctl.scala 2570:198] - node _T_1385 = or(_T_1362, _T_1384) @[dec_tlu_ctl.scala 2651:161] - node _T_1386 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:149] - node _T_1387 = eq(_T_1386, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1388 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] - node _T_1389 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] - node _T_1390 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] - node _T_1391 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:106] - node _T_1392 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] - node _T_1393 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] - node _T_1394 = eq(_T_1393, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1395 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] - node _T_1396 = eq(_T_1395, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1397 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] - node _T_1398 = eq(_T_1397, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] - node _T_1399 = and(_T_1387, _T_1388) @[dec_tlu_ctl.scala 2570:198] - node _T_1400 = and(_T_1399, _T_1389) @[dec_tlu_ctl.scala 2570:198] - node _T_1401 = and(_T_1400, _T_1390) @[dec_tlu_ctl.scala 2570:198] - node _T_1402 = and(_T_1401, _T_1391) @[dec_tlu_ctl.scala 2570:198] - node _T_1403 = and(_T_1402, _T_1392) @[dec_tlu_ctl.scala 2570:198] - node _T_1404 = and(_T_1403, _T_1394) @[dec_tlu_ctl.scala 2570:198] - node _T_1405 = and(_T_1404, _T_1396) @[dec_tlu_ctl.scala 2570:198] - node _T_1406 = and(_T_1405, _T_1398) @[dec_tlu_ctl.scala 2570:198] - node _T_1407 = or(_T_1385, _T_1406) @[dec_tlu_ctl.scala 2652:105] - node _T_1408 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:149] - node _T_1409 = eq(_T_1408, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1410 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] - node _T_1411 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] - node _T_1412 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] - node _T_1413 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:106] - node _T_1414 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] - node _T_1415 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] - node _T_1416 = eq(_T_1415, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1417 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] - node _T_1418 = eq(_T_1417, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1419 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:106] - node _T_1420 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] - node _T_1421 = eq(_T_1420, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1422 = and(_T_1409, _T_1410) @[dec_tlu_ctl.scala 2570:198] - node _T_1423 = and(_T_1422, _T_1411) @[dec_tlu_ctl.scala 2570:198] - node _T_1424 = and(_T_1423, _T_1412) @[dec_tlu_ctl.scala 2570:198] - node _T_1425 = and(_T_1424, _T_1413) @[dec_tlu_ctl.scala 2570:198] - node _T_1426 = and(_T_1425, _T_1414) @[dec_tlu_ctl.scala 2570:198] - node _T_1427 = and(_T_1426, _T_1416) @[dec_tlu_ctl.scala 2570:198] - node _T_1428 = and(_T_1427, _T_1418) @[dec_tlu_ctl.scala 2570:198] - node _T_1429 = and(_T_1428, _T_1419) @[dec_tlu_ctl.scala 2570:198] - node _T_1430 = and(_T_1429, _T_1421) @[dec_tlu_ctl.scala 2570:198] - node _T_1431 = or(_T_1407, _T_1430) @[dec_tlu_ctl.scala 2652:161] - node _T_1432 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:149] - node _T_1433 = eq(_T_1432, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1434 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] - node _T_1435 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] - node _T_1436 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] - node _T_1437 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:106] - node _T_1438 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] - node _T_1439 = eq(_T_1438, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1440 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:106] - node _T_1441 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] - node _T_1442 = eq(_T_1441, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1443 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] - node _T_1444 = eq(_T_1443, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1445 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] - node _T_1446 = eq(_T_1445, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1447 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] - node _T_1448 = eq(_T_1447, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] - node _T_1449 = and(_T_1433, _T_1434) @[dec_tlu_ctl.scala 2570:198] - node _T_1450 = and(_T_1449, _T_1435) @[dec_tlu_ctl.scala 2570:198] - node _T_1451 = and(_T_1450, _T_1436) @[dec_tlu_ctl.scala 2570:198] - node _T_1452 = and(_T_1451, _T_1437) @[dec_tlu_ctl.scala 2570:198] - node _T_1453 = and(_T_1452, _T_1439) @[dec_tlu_ctl.scala 2570:198] - node _T_1454 = and(_T_1453, _T_1440) @[dec_tlu_ctl.scala 2570:198] - node _T_1455 = and(_T_1454, _T_1442) @[dec_tlu_ctl.scala 2570:198] - node _T_1456 = and(_T_1455, _T_1444) @[dec_tlu_ctl.scala 2570:198] - node _T_1457 = and(_T_1456, _T_1446) @[dec_tlu_ctl.scala 2570:198] - node _T_1458 = and(_T_1457, _T_1448) @[dec_tlu_ctl.scala 2570:198] - node _T_1459 = or(_T_1431, _T_1458) @[dec_tlu_ctl.scala 2653:105] - node _T_1460 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:106] - node _T_1461 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:149] - node _T_1462 = eq(_T_1461, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1463 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] - node _T_1464 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] - node _T_1465 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] - node _T_1466 = eq(_T_1465, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1467 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] - node _T_1468 = eq(_T_1467, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1469 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] - node _T_1470 = and(_T_1460, _T_1462) @[dec_tlu_ctl.scala 2570:198] - node _T_1471 = and(_T_1470, _T_1463) @[dec_tlu_ctl.scala 2570:198] - node _T_1472 = and(_T_1471, _T_1464) @[dec_tlu_ctl.scala 2570:198] - node _T_1473 = and(_T_1472, _T_1466) @[dec_tlu_ctl.scala 2570:198] - node _T_1474 = and(_T_1473, _T_1468) @[dec_tlu_ctl.scala 2570:198] - node _T_1475 = and(_T_1474, _T_1469) @[dec_tlu_ctl.scala 2570:198] - node _T_1476 = or(_T_1459, _T_1475) @[dec_tlu_ctl.scala 2653:153] - node _T_1477 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:149] - node _T_1478 = eq(_T_1477, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1479 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:149] - node _T_1480 = eq(_T_1479, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1481 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] - node _T_1482 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] - node _T_1483 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] - node _T_1484 = eq(_T_1483, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1485 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] - node _T_1486 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] - node _T_1487 = eq(_T_1486, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1488 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] - node _T_1489 = eq(_T_1488, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1490 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] - node _T_1491 = eq(_T_1490, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1492 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] - node _T_1493 = eq(_T_1492, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1494 = and(_T_1478, _T_1480) @[dec_tlu_ctl.scala 2570:198] - node _T_1495 = and(_T_1494, _T_1481) @[dec_tlu_ctl.scala 2570:198] - node _T_1496 = and(_T_1495, _T_1482) @[dec_tlu_ctl.scala 2570:198] - node _T_1497 = and(_T_1496, _T_1484) @[dec_tlu_ctl.scala 2570:198] - node _T_1498 = and(_T_1497, _T_1485) @[dec_tlu_ctl.scala 2570:198] - node _T_1499 = and(_T_1498, _T_1487) @[dec_tlu_ctl.scala 2570:198] - node _T_1500 = and(_T_1499, _T_1489) @[dec_tlu_ctl.scala 2570:198] - node _T_1501 = and(_T_1500, _T_1491) @[dec_tlu_ctl.scala 2570:198] - node _T_1502 = and(_T_1501, _T_1493) @[dec_tlu_ctl.scala 2570:198] - node _T_1503 = or(_T_1476, _T_1502) @[dec_tlu_ctl.scala 2654:113] - node _T_1504 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:149] - node _T_1505 = eq(_T_1504, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1506 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:149] - node _T_1507 = eq(_T_1506, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1508 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] - node _T_1509 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] - node _T_1510 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] - node _T_1511 = eq(_T_1510, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1512 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] - node _T_1513 = eq(_T_1512, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1514 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] - node _T_1515 = eq(_T_1514, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1516 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] - node _T_1517 = eq(_T_1516, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1518 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] - node _T_1519 = eq(_T_1518, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1520 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] - node _T_1521 = eq(_T_1520, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] - node _T_1522 = and(_T_1505, _T_1507) @[dec_tlu_ctl.scala 2570:198] - node _T_1523 = and(_T_1522, _T_1508) @[dec_tlu_ctl.scala 2570:198] - node _T_1524 = and(_T_1523, _T_1509) @[dec_tlu_ctl.scala 2570:198] - node _T_1525 = and(_T_1524, _T_1511) @[dec_tlu_ctl.scala 2570:198] - node _T_1526 = and(_T_1525, _T_1513) @[dec_tlu_ctl.scala 2570:198] - node _T_1527 = and(_T_1526, _T_1515) @[dec_tlu_ctl.scala 2570:198] - node _T_1528 = and(_T_1527, _T_1517) @[dec_tlu_ctl.scala 2570:198] - node _T_1529 = and(_T_1528, _T_1519) @[dec_tlu_ctl.scala 2570:198] - node _T_1530 = and(_T_1529, _T_1521) @[dec_tlu_ctl.scala 2570:198] - node _T_1531 = or(_T_1503, _T_1530) @[dec_tlu_ctl.scala 2654:161] - node _T_1532 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:149] - node _T_1533 = eq(_T_1532, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1534 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:149] - node _T_1535 = eq(_T_1534, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1536 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] - node _T_1537 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] - node _T_1538 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] - node _T_1539 = eq(_T_1538, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1540 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] - node _T_1541 = eq(_T_1540, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1542 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:106] - node _T_1543 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:106] - node _T_1544 = and(_T_1533, _T_1535) @[dec_tlu_ctl.scala 2570:198] - node _T_1545 = and(_T_1544, _T_1536) @[dec_tlu_ctl.scala 2570:198] - node _T_1546 = and(_T_1545, _T_1537) @[dec_tlu_ctl.scala 2570:198] - node _T_1547 = and(_T_1546, _T_1539) @[dec_tlu_ctl.scala 2570:198] - node _T_1548 = and(_T_1547, _T_1541) @[dec_tlu_ctl.scala 2570:198] - node _T_1549 = and(_T_1548, _T_1542) @[dec_tlu_ctl.scala 2570:198] - node _T_1550 = and(_T_1549, _T_1543) @[dec_tlu_ctl.scala 2570:198] - node _T_1551 = or(_T_1531, _T_1550) @[dec_tlu_ctl.scala 2655:97] - node _T_1552 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:106] - node _T_1553 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:149] - node _T_1554 = eq(_T_1553, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1555 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] - node _T_1556 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] - node _T_1557 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] - node _T_1558 = eq(_T_1557, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1559 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] - node _T_1560 = eq(_T_1559, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1561 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:106] - node _T_1562 = and(_T_1552, _T_1554) @[dec_tlu_ctl.scala 2570:198] - node _T_1563 = and(_T_1562, _T_1555) @[dec_tlu_ctl.scala 2570:198] - node _T_1564 = and(_T_1563, _T_1556) @[dec_tlu_ctl.scala 2570:198] - node _T_1565 = and(_T_1564, _T_1558) @[dec_tlu_ctl.scala 2570:198] - node _T_1566 = and(_T_1565, _T_1560) @[dec_tlu_ctl.scala 2570:198] - node _T_1567 = and(_T_1566, _T_1561) @[dec_tlu_ctl.scala 2570:198] - node _T_1568 = or(_T_1551, _T_1567) @[dec_tlu_ctl.scala 2655:153] - node _T_1569 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:149] - node _T_1570 = eq(_T_1569, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1571 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:149] - node _T_1572 = eq(_T_1571, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1573 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] - node _T_1574 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] - node _T_1575 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] - node _T_1576 = eq(_T_1575, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1577 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] - node _T_1578 = eq(_T_1577, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1579 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:106] - node _T_1580 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:106] - node _T_1581 = and(_T_1570, _T_1572) @[dec_tlu_ctl.scala 2570:198] - node _T_1582 = and(_T_1581, _T_1573) @[dec_tlu_ctl.scala 2570:198] - node _T_1583 = and(_T_1582, _T_1574) @[dec_tlu_ctl.scala 2570:198] - node _T_1584 = and(_T_1583, _T_1576) @[dec_tlu_ctl.scala 2570:198] - node _T_1585 = and(_T_1584, _T_1578) @[dec_tlu_ctl.scala 2570:198] - node _T_1586 = and(_T_1585, _T_1579) @[dec_tlu_ctl.scala 2570:198] - node _T_1587 = and(_T_1586, _T_1580) @[dec_tlu_ctl.scala 2570:198] - node _T_1588 = or(_T_1568, _T_1587) @[dec_tlu_ctl.scala 2656:113] - node _T_1589 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:106] - node _T_1590 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:149] - node _T_1591 = eq(_T_1590, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1592 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] - node _T_1593 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] - node _T_1594 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] - node _T_1595 = eq(_T_1594, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1596 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] - node _T_1597 = eq(_T_1596, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] - node _T_1598 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:106] - node _T_1599 = and(_T_1589, _T_1591) @[dec_tlu_ctl.scala 2570:198] - node _T_1600 = and(_T_1599, _T_1592) @[dec_tlu_ctl.scala 2570:198] - node _T_1601 = and(_T_1600, _T_1593) @[dec_tlu_ctl.scala 2570:198] - node _T_1602 = and(_T_1601, _T_1595) @[dec_tlu_ctl.scala 2570:198] - node _T_1603 = and(_T_1602, _T_1597) @[dec_tlu_ctl.scala 2570:198] - node _T_1604 = and(_T_1603, _T_1598) @[dec_tlu_ctl.scala 2570:198] - node _T_1605 = or(_T_1588, _T_1604) @[dec_tlu_ctl.scala 2656:169] - io.csr_pkt.legal <= _T_1605 @[dec_tlu_ctl.scala 2643:26] + node _T = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] + node _T_1 = eq(_T, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_2 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] + node _T_3 = eq(_T_2, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_4 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] + node _T_5 = eq(_T_4, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_6 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] + node _T_7 = eq(_T_6, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_8 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] + node _T_9 = and(_T_1, _T_3) @[dec_tlu_ctl.scala 2568:198] + node _T_10 = and(_T_9, _T_5) @[dec_tlu_ctl.scala 2568:198] + node _T_11 = and(_T_10, _T_7) @[dec_tlu_ctl.scala 2568:198] + node _T_12 = and(_T_11, _T_8) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_misa <= _T_12 @[dec_tlu_ctl.scala 2570:57] + node _T_13 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] + node _T_14 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] + node _T_15 = eq(_T_14, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_16 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] + node _T_17 = eq(_T_16, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_18 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] + node _T_19 = and(_T_13, _T_15) @[dec_tlu_ctl.scala 2568:198] + node _T_20 = and(_T_19, _T_17) @[dec_tlu_ctl.scala 2568:198] + node _T_21 = and(_T_20, _T_18) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_mvendorid <= _T_21 @[dec_tlu_ctl.scala 2571:57] + node _T_22 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] + node _T_23 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] + node _T_24 = eq(_T_23, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_25 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] + node _T_26 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] + node _T_27 = eq(_T_26, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] + node _T_28 = and(_T_22, _T_24) @[dec_tlu_ctl.scala 2568:198] + node _T_29 = and(_T_28, _T_25) @[dec_tlu_ctl.scala 2568:198] + node _T_30 = and(_T_29, _T_27) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_marchid <= _T_30 @[dec_tlu_ctl.scala 2572:57] + node _T_31 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] + node _T_32 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] + node _T_33 = eq(_T_32, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_34 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] + node _T_35 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] + node _T_36 = and(_T_31, _T_33) @[dec_tlu_ctl.scala 2568:198] + node _T_37 = and(_T_36, _T_34) @[dec_tlu_ctl.scala 2568:198] + node _T_38 = and(_T_37, _T_35) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_mimpid <= _T_38 @[dec_tlu_ctl.scala 2573:57] + node _T_39 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] + node _T_40 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] + node _T_41 = eq(_T_40, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_42 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] + node _T_43 = and(_T_39, _T_41) @[dec_tlu_ctl.scala 2568:198] + node _T_44 = and(_T_43, _T_42) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_mhartid <= _T_44 @[dec_tlu_ctl.scala 2574:57] + node _T_45 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] + node _T_46 = eq(_T_45, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_47 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] + node _T_48 = eq(_T_47, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_49 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] + node _T_50 = eq(_T_49, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_51 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] + node _T_52 = eq(_T_51, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_53 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] + node _T_54 = eq(_T_53, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] + node _T_55 = and(_T_46, _T_48) @[dec_tlu_ctl.scala 2568:198] + node _T_56 = and(_T_55, _T_50) @[dec_tlu_ctl.scala 2568:198] + node _T_57 = and(_T_56, _T_52) @[dec_tlu_ctl.scala 2568:198] + node _T_58 = and(_T_57, _T_54) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_mstatus <= _T_58 @[dec_tlu_ctl.scala 2575:57] + node _T_59 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] + node _T_60 = eq(_T_59, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_61 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] + node _T_62 = eq(_T_61, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_63 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] + node _T_64 = eq(_T_63, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_65 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] + node _T_66 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] + node _T_67 = and(_T_60, _T_62) @[dec_tlu_ctl.scala 2568:198] + node _T_68 = and(_T_67, _T_64) @[dec_tlu_ctl.scala 2568:198] + node _T_69 = and(_T_68, _T_65) @[dec_tlu_ctl.scala 2568:198] + node _T_70 = and(_T_69, _T_66) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_mtvec <= _T_70 @[dec_tlu_ctl.scala 2576:57] + node _T_71 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] + node _T_72 = eq(_T_71, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_73 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] + node _T_74 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] + node _T_75 = and(_T_72, _T_73) @[dec_tlu_ctl.scala 2568:198] + node _T_76 = and(_T_75, _T_74) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_mip <= _T_76 @[dec_tlu_ctl.scala 2577:65] + node _T_77 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] + node _T_78 = eq(_T_77, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_79 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] + node _T_80 = eq(_T_79, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_81 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] + node _T_82 = eq(_T_81, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_83 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] + node _T_84 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] + node _T_85 = eq(_T_84, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] + node _T_86 = and(_T_78, _T_80) @[dec_tlu_ctl.scala 2568:198] + node _T_87 = and(_T_86, _T_82) @[dec_tlu_ctl.scala 2568:198] + node _T_88 = and(_T_87, _T_83) @[dec_tlu_ctl.scala 2568:198] + node _T_89 = and(_T_88, _T_85) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_mie <= _T_89 @[dec_tlu_ctl.scala 2578:65] + node _T_90 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] + node _T_91 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] + node _T_92 = eq(_T_91, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_93 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] + node _T_94 = eq(_T_93, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_95 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] + node _T_96 = eq(_T_95, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_97 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] + node _T_98 = eq(_T_97, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_99 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] + node _T_100 = eq(_T_99, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_101 = and(_T_90, _T_92) @[dec_tlu_ctl.scala 2568:198] + node _T_102 = and(_T_101, _T_94) @[dec_tlu_ctl.scala 2568:198] + node _T_103 = and(_T_102, _T_96) @[dec_tlu_ctl.scala 2568:198] + node _T_104 = and(_T_103, _T_98) @[dec_tlu_ctl.scala 2568:198] + node _T_105 = and(_T_104, _T_100) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_mcyclel <= _T_105 @[dec_tlu_ctl.scala 2579:57] + node _T_106 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] + node _T_107 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] + node _T_108 = eq(_T_107, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_109 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] + node _T_110 = eq(_T_109, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_111 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] + node _T_112 = eq(_T_111, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_113 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] + node _T_114 = eq(_T_113, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_115 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] + node _T_116 = eq(_T_115, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_117 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] + node _T_118 = eq(_T_117, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_119 = and(_T_106, _T_108) @[dec_tlu_ctl.scala 2568:198] + node _T_120 = and(_T_119, _T_110) @[dec_tlu_ctl.scala 2568:198] + node _T_121 = and(_T_120, _T_112) @[dec_tlu_ctl.scala 2568:198] + node _T_122 = and(_T_121, _T_114) @[dec_tlu_ctl.scala 2568:198] + node _T_123 = and(_T_122, _T_116) @[dec_tlu_ctl.scala 2568:198] + node _T_124 = and(_T_123, _T_118) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_mcycleh <= _T_124 @[dec_tlu_ctl.scala 2580:57] + node _T_125 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] + node _T_126 = eq(_T_125, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_127 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] + node _T_128 = eq(_T_127, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_129 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] + node _T_130 = eq(_T_129, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_131 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] + node _T_132 = eq(_T_131, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_133 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] + node _T_134 = eq(_T_133, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_135 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] + node _T_136 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] + node _T_137 = eq(_T_136, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] + node _T_138 = and(_T_126, _T_128) @[dec_tlu_ctl.scala 2568:198] + node _T_139 = and(_T_138, _T_130) @[dec_tlu_ctl.scala 2568:198] + node _T_140 = and(_T_139, _T_132) @[dec_tlu_ctl.scala 2568:198] + node _T_141 = and(_T_140, _T_134) @[dec_tlu_ctl.scala 2568:198] + node _T_142 = and(_T_141, _T_135) @[dec_tlu_ctl.scala 2568:198] + node _T_143 = and(_T_142, _T_137) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_minstretl <= _T_143 @[dec_tlu_ctl.scala 2581:57] + node _T_144 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149] + node _T_145 = eq(_T_144, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_146 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] + node _T_147 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] + node _T_148 = eq(_T_147, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_149 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] + node _T_150 = eq(_T_149, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_151 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] + node _T_152 = eq(_T_151, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_153 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] + node _T_154 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] + node _T_155 = eq(_T_154, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] + node _T_156 = and(_T_145, _T_146) @[dec_tlu_ctl.scala 2568:198] + node _T_157 = and(_T_156, _T_148) @[dec_tlu_ctl.scala 2568:198] + node _T_158 = and(_T_157, _T_150) @[dec_tlu_ctl.scala 2568:198] + node _T_159 = and(_T_158, _T_152) @[dec_tlu_ctl.scala 2568:198] + node _T_160 = and(_T_159, _T_153) @[dec_tlu_ctl.scala 2568:198] + node _T_161 = and(_T_160, _T_155) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_minstreth <= _T_161 @[dec_tlu_ctl.scala 2582:57] + node _T_162 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] + node _T_163 = eq(_T_162, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_164 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] + node _T_165 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] + node _T_166 = eq(_T_165, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_167 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] + node _T_168 = eq(_T_167, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_169 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] + node _T_170 = eq(_T_169, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] + node _T_171 = and(_T_163, _T_164) @[dec_tlu_ctl.scala 2568:198] + node _T_172 = and(_T_171, _T_166) @[dec_tlu_ctl.scala 2568:198] + node _T_173 = and(_T_172, _T_168) @[dec_tlu_ctl.scala 2568:198] + node _T_174 = and(_T_173, _T_170) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_mscratch <= _T_174 @[dec_tlu_ctl.scala 2583:57] + node _T_175 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] + node _T_176 = eq(_T_175, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_177 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] + node _T_178 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] + node _T_179 = eq(_T_178, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_180 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] + node _T_181 = and(_T_176, _T_177) @[dec_tlu_ctl.scala 2568:198] + node _T_182 = and(_T_181, _T_179) @[dec_tlu_ctl.scala 2568:198] + node _T_183 = and(_T_182, _T_180) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_mepc <= _T_183 @[dec_tlu_ctl.scala 2584:57] + node _T_184 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] + node _T_185 = eq(_T_184, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_186 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] + node _T_187 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] + node _T_188 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] + node _T_189 = eq(_T_188, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] + node _T_190 = and(_T_185, _T_186) @[dec_tlu_ctl.scala 2568:198] + node _T_191 = and(_T_190, _T_187) @[dec_tlu_ctl.scala 2568:198] + node _T_192 = and(_T_191, _T_189) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_mcause <= _T_192 @[dec_tlu_ctl.scala 2585:57] + node _T_193 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] + node _T_194 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] + node _T_195 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] + node _T_196 = and(_T_193, _T_194) @[dec_tlu_ctl.scala 2568:198] + node _T_197 = and(_T_196, _T_195) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_mscause <= _T_197 @[dec_tlu_ctl.scala 2586:57] + node _T_198 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] + node _T_199 = eq(_T_198, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_200 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] + node _T_201 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] + node _T_202 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] + node _T_203 = and(_T_199, _T_200) @[dec_tlu_ctl.scala 2568:198] + node _T_204 = and(_T_203, _T_201) @[dec_tlu_ctl.scala 2568:198] + node _T_205 = and(_T_204, _T_202) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_mtval <= _T_205 @[dec_tlu_ctl.scala 2587:57] + node _T_206 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] + node _T_207 = eq(_T_206, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_208 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] + node _T_209 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] + node _T_210 = eq(_T_209, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_211 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] + node _T_212 = eq(_T_211, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_213 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] + node _T_214 = eq(_T_213, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_215 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] + node _T_216 = eq(_T_215, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_217 = and(_T_207, _T_208) @[dec_tlu_ctl.scala 2568:198] + node _T_218 = and(_T_217, _T_210) @[dec_tlu_ctl.scala 2568:198] + node _T_219 = and(_T_218, _T_212) @[dec_tlu_ctl.scala 2568:198] + node _T_220 = and(_T_219, _T_214) @[dec_tlu_ctl.scala 2568:198] + node _T_221 = and(_T_220, _T_216) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_mrac <= _T_221 @[dec_tlu_ctl.scala 2588:57] + node _T_222 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] + node _T_223 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] + node _T_224 = eq(_T_223, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_225 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] + node _T_226 = eq(_T_225, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_227 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] + node _T_228 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] + node _T_229 = eq(_T_228, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_230 = and(_T_222, _T_224) @[dec_tlu_ctl.scala 2568:198] + node _T_231 = and(_T_230, _T_226) @[dec_tlu_ctl.scala 2568:198] + node _T_232 = and(_T_231, _T_227) @[dec_tlu_ctl.scala 2568:198] + node _T_233 = and(_T_232, _T_229) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_dmst <= _T_233 @[dec_tlu_ctl.scala 2589:57] + node _T_234 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] + node _T_235 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] + node _T_236 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] + node _T_237 = eq(_T_236, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_238 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] + node _T_239 = eq(_T_238, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_240 = and(_T_234, _T_235) @[dec_tlu_ctl.scala 2568:198] + node _T_241 = and(_T_240, _T_237) @[dec_tlu_ctl.scala 2568:198] + node _T_242 = and(_T_241, _T_239) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_mdseac <= _T_242 @[dec_tlu_ctl.scala 2590:57] + node _T_243 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] + node _T_244 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] + node _T_245 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] + node _T_246 = and(_T_243, _T_244) @[dec_tlu_ctl.scala 2568:198] + node _T_247 = and(_T_246, _T_245) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_meihap <= _T_247 @[dec_tlu_ctl.scala 2591:57] + node _T_248 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149] + node _T_249 = eq(_T_248, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_250 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] + node _T_251 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] + node _T_252 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] + node _T_253 = eq(_T_252, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_254 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] + node _T_255 = eq(_T_254, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_256 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] + node _T_257 = eq(_T_256, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] + node _T_258 = and(_T_249, _T_250) @[dec_tlu_ctl.scala 2568:198] + node _T_259 = and(_T_258, _T_251) @[dec_tlu_ctl.scala 2568:198] + node _T_260 = and(_T_259, _T_253) @[dec_tlu_ctl.scala 2568:198] + node _T_261 = and(_T_260, _T_255) @[dec_tlu_ctl.scala 2568:198] + node _T_262 = and(_T_261, _T_257) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_meivt <= _T_262 @[dec_tlu_ctl.scala 2592:57] + node _T_263 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] + node _T_264 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] + node _T_265 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] + node _T_266 = eq(_T_265, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_267 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] + node _T_268 = and(_T_263, _T_264) @[dec_tlu_ctl.scala 2568:198] + node _T_269 = and(_T_268, _T_266) @[dec_tlu_ctl.scala 2568:198] + node _T_270 = and(_T_269, _T_267) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_meipt <= _T_270 @[dec_tlu_ctl.scala 2593:57] + node _T_271 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] + node _T_272 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] + node _T_273 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] + node _T_274 = and(_T_271, _T_272) @[dec_tlu_ctl.scala 2568:198] + node _T_275 = and(_T_274, _T_273) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_meicurpl <= _T_275 @[dec_tlu_ctl.scala 2594:57] + node _T_276 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] + node _T_277 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] + node _T_278 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] + node _T_279 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] + node _T_280 = and(_T_276, _T_277) @[dec_tlu_ctl.scala 2568:198] + node _T_281 = and(_T_280, _T_278) @[dec_tlu_ctl.scala 2568:198] + node _T_282 = and(_T_281, _T_279) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_meicidpl <= _T_282 @[dec_tlu_ctl.scala 2595:57] + node _T_283 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] + node _T_284 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] + node _T_285 = eq(_T_284, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_286 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] + node _T_287 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] + node _T_288 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] + node _T_289 = eq(_T_288, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] + node _T_290 = and(_T_283, _T_285) @[dec_tlu_ctl.scala 2568:198] + node _T_291 = and(_T_290, _T_286) @[dec_tlu_ctl.scala 2568:198] + node _T_292 = and(_T_291, _T_287) @[dec_tlu_ctl.scala 2568:198] + node _T_293 = and(_T_292, _T_289) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_dcsr <= _T_293 @[dec_tlu_ctl.scala 2596:57] + node _T_294 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] + node _T_295 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] + node _T_296 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] + node _T_297 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] + node _T_298 = eq(_T_297, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] + node _T_299 = and(_T_294, _T_295) @[dec_tlu_ctl.scala 2568:198] + node _T_300 = and(_T_299, _T_296) @[dec_tlu_ctl.scala 2568:198] + node _T_301 = and(_T_300, _T_298) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_mcgc <= _T_301 @[dec_tlu_ctl.scala 2597:57] + node _T_302 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] + node _T_303 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] + node _T_304 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] + node _T_305 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] + node _T_306 = eq(_T_305, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_307 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] + node _T_308 = and(_T_302, _T_303) @[dec_tlu_ctl.scala 2568:198] + node _T_309 = and(_T_308, _T_304) @[dec_tlu_ctl.scala 2568:198] + node _T_310 = and(_T_309, _T_306) @[dec_tlu_ctl.scala 2568:198] + node _T_311 = and(_T_310, _T_307) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_mfdc <= _T_311 @[dec_tlu_ctl.scala 2598:57] + node _T_312 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] + node _T_313 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] + node _T_314 = eq(_T_313, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_315 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] + node _T_316 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] + node _T_317 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] + node _T_318 = and(_T_312, _T_314) @[dec_tlu_ctl.scala 2568:198] + node _T_319 = and(_T_318, _T_315) @[dec_tlu_ctl.scala 2568:198] + node _T_320 = and(_T_319, _T_316) @[dec_tlu_ctl.scala 2568:198] + node _T_321 = and(_T_320, _T_317) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_dpc <= _T_321 @[dec_tlu_ctl.scala 2599:65] + node _T_322 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] + node _T_323 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] + node _T_324 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] + node _T_325 = eq(_T_324, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_326 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] + node _T_327 = eq(_T_326, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_328 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] + node _T_329 = eq(_T_328, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] + node _T_330 = and(_T_322, _T_323) @[dec_tlu_ctl.scala 2568:198] + node _T_331 = and(_T_330, _T_325) @[dec_tlu_ctl.scala 2568:198] + node _T_332 = and(_T_331, _T_327) @[dec_tlu_ctl.scala 2568:198] + node _T_333 = and(_T_332, _T_329) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_mtsel <= _T_333 @[dec_tlu_ctl.scala 2600:57] + node _T_334 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] + node _T_335 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] + node _T_336 = eq(_T_335, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_337 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] + node _T_338 = eq(_T_337, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_339 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] + node _T_340 = and(_T_334, _T_336) @[dec_tlu_ctl.scala 2568:198] + node _T_341 = and(_T_340, _T_338) @[dec_tlu_ctl.scala 2568:198] + node _T_342 = and(_T_341, _T_339) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_mtdata1 <= _T_342 @[dec_tlu_ctl.scala 2601:57] + node _T_343 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] + node _T_344 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] + node _T_345 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] + node _T_346 = eq(_T_345, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_347 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] + node _T_348 = and(_T_343, _T_344) @[dec_tlu_ctl.scala 2568:198] + node _T_349 = and(_T_348, _T_346) @[dec_tlu_ctl.scala 2568:198] + node _T_350 = and(_T_349, _T_347) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_mtdata2 <= _T_350 @[dec_tlu_ctl.scala 2602:57] + node _T_351 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] + node _T_352 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] + node _T_353 = eq(_T_352, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_354 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] + node _T_355 = eq(_T_354, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_356 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] + node _T_357 = eq(_T_356, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_358 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] + node _T_359 = eq(_T_358, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_360 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] + node _T_361 = and(_T_351, _T_353) @[dec_tlu_ctl.scala 2568:198] + node _T_362 = and(_T_361, _T_355) @[dec_tlu_ctl.scala 2568:198] + node _T_363 = and(_T_362, _T_357) @[dec_tlu_ctl.scala 2568:198] + node _T_364 = and(_T_363, _T_359) @[dec_tlu_ctl.scala 2568:198] + node _T_365 = and(_T_364, _T_360) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_mhpmc3 <= _T_365 @[dec_tlu_ctl.scala 2603:57] + node _T_366 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] + node _T_367 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] + node _T_368 = eq(_T_367, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_369 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] + node _T_370 = eq(_T_369, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_371 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] + node _T_372 = eq(_T_371, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_373 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] + node _T_374 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] + node _T_375 = eq(_T_374, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_376 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] + node _T_377 = eq(_T_376, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] + node _T_378 = and(_T_366, _T_368) @[dec_tlu_ctl.scala 2568:198] + node _T_379 = and(_T_378, _T_370) @[dec_tlu_ctl.scala 2568:198] + node _T_380 = and(_T_379, _T_372) @[dec_tlu_ctl.scala 2568:198] + node _T_381 = and(_T_380, _T_373) @[dec_tlu_ctl.scala 2568:198] + node _T_382 = and(_T_381, _T_375) @[dec_tlu_ctl.scala 2568:198] + node _T_383 = and(_T_382, _T_377) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_mhpmc4 <= _T_383 @[dec_tlu_ctl.scala 2604:57] + node _T_384 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] + node _T_385 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] + node _T_386 = eq(_T_385, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_387 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] + node _T_388 = eq(_T_387, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_389 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] + node _T_390 = eq(_T_389, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_391 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] + node _T_392 = eq(_T_391, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_393 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] + node _T_394 = and(_T_384, _T_386) @[dec_tlu_ctl.scala 2568:198] + node _T_395 = and(_T_394, _T_388) @[dec_tlu_ctl.scala 2568:198] + node _T_396 = and(_T_395, _T_390) @[dec_tlu_ctl.scala 2568:198] + node _T_397 = and(_T_396, _T_392) @[dec_tlu_ctl.scala 2568:198] + node _T_398 = and(_T_397, _T_393) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_mhpmc5 <= _T_398 @[dec_tlu_ctl.scala 2605:57] + node _T_399 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] + node _T_400 = eq(_T_399, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_401 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] + node _T_402 = eq(_T_401, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_403 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] + node _T_404 = eq(_T_403, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_405 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] + node _T_406 = eq(_T_405, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_407 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] + node _T_408 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] + node _T_409 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] + node _T_410 = eq(_T_409, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] + node _T_411 = and(_T_400, _T_402) @[dec_tlu_ctl.scala 2568:198] + node _T_412 = and(_T_411, _T_404) @[dec_tlu_ctl.scala 2568:198] + node _T_413 = and(_T_412, _T_406) @[dec_tlu_ctl.scala 2568:198] + node _T_414 = and(_T_413, _T_407) @[dec_tlu_ctl.scala 2568:198] + node _T_415 = and(_T_414, _T_408) @[dec_tlu_ctl.scala 2568:198] + node _T_416 = and(_T_415, _T_410) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_mhpmc6 <= _T_416 @[dec_tlu_ctl.scala 2606:57] + node _T_417 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] + node _T_418 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] + node _T_419 = eq(_T_418, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_420 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] + node _T_421 = eq(_T_420, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_422 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] + node _T_423 = eq(_T_422, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_424 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] + node _T_425 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] + node _T_426 = and(_T_417, _T_419) @[dec_tlu_ctl.scala 2568:198] + node _T_427 = and(_T_426, _T_421) @[dec_tlu_ctl.scala 2568:198] + node _T_428 = and(_T_427, _T_423) @[dec_tlu_ctl.scala 2568:198] + node _T_429 = and(_T_428, _T_424) @[dec_tlu_ctl.scala 2568:198] + node _T_430 = and(_T_429, _T_425) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_mhpmc3h <= _T_430 @[dec_tlu_ctl.scala 2607:57] + node _T_431 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] + node _T_432 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] + node _T_433 = eq(_T_432, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_434 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] + node _T_435 = eq(_T_434, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_436 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] + node _T_437 = eq(_T_436, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_438 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] + node _T_439 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] + node _T_440 = eq(_T_439, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_441 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] + node _T_442 = eq(_T_441, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] + node _T_443 = and(_T_431, _T_433) @[dec_tlu_ctl.scala 2568:198] + node _T_444 = and(_T_443, _T_435) @[dec_tlu_ctl.scala 2568:198] + node _T_445 = and(_T_444, _T_437) @[dec_tlu_ctl.scala 2568:198] + node _T_446 = and(_T_445, _T_438) @[dec_tlu_ctl.scala 2568:198] + node _T_447 = and(_T_446, _T_440) @[dec_tlu_ctl.scala 2568:198] + node _T_448 = and(_T_447, _T_442) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_mhpmc4h <= _T_448 @[dec_tlu_ctl.scala 2608:57] + node _T_449 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] + node _T_450 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] + node _T_451 = eq(_T_450, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_452 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] + node _T_453 = eq(_T_452, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_454 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] + node _T_455 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] + node _T_456 = eq(_T_455, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_457 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] + node _T_458 = and(_T_449, _T_451) @[dec_tlu_ctl.scala 2568:198] + node _T_459 = and(_T_458, _T_453) @[dec_tlu_ctl.scala 2568:198] + node _T_460 = and(_T_459, _T_454) @[dec_tlu_ctl.scala 2568:198] + node _T_461 = and(_T_460, _T_456) @[dec_tlu_ctl.scala 2568:198] + node _T_462 = and(_T_461, _T_457) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_mhpmc5h <= _T_462 @[dec_tlu_ctl.scala 2609:57] + node _T_463 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] + node _T_464 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] + node _T_465 = eq(_T_464, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_466 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] + node _T_467 = eq(_T_466, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_468 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] + node _T_469 = eq(_T_468, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_470 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] + node _T_471 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] + node _T_472 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] + node _T_473 = eq(_T_472, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] + node _T_474 = and(_T_463, _T_465) @[dec_tlu_ctl.scala 2568:198] + node _T_475 = and(_T_474, _T_467) @[dec_tlu_ctl.scala 2568:198] + node _T_476 = and(_T_475, _T_469) @[dec_tlu_ctl.scala 2568:198] + node _T_477 = and(_T_476, _T_470) @[dec_tlu_ctl.scala 2568:198] + node _T_478 = and(_T_477, _T_471) @[dec_tlu_ctl.scala 2568:198] + node _T_479 = and(_T_478, _T_473) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_mhpmc6h <= _T_479 @[dec_tlu_ctl.scala 2610:57] + node _T_480 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] + node _T_481 = eq(_T_480, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_482 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] + node _T_483 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] + node _T_484 = eq(_T_483, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_485 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] + node _T_486 = eq(_T_485, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_487 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] + node _T_488 = eq(_T_487, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_489 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] + node _T_490 = and(_T_481, _T_482) @[dec_tlu_ctl.scala 2568:198] + node _T_491 = and(_T_490, _T_484) @[dec_tlu_ctl.scala 2568:198] + node _T_492 = and(_T_491, _T_486) @[dec_tlu_ctl.scala 2568:198] + node _T_493 = and(_T_492, _T_488) @[dec_tlu_ctl.scala 2568:198] + node _T_494 = and(_T_493, _T_489) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_mhpme3 <= _T_494 @[dec_tlu_ctl.scala 2611:57] + node _T_495 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] + node _T_496 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] + node _T_497 = eq(_T_496, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_498 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] + node _T_499 = eq(_T_498, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_500 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] + node _T_501 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] + node _T_502 = eq(_T_501, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_503 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] + node _T_504 = eq(_T_503, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] + node _T_505 = and(_T_495, _T_497) @[dec_tlu_ctl.scala 2568:198] + node _T_506 = and(_T_505, _T_499) @[dec_tlu_ctl.scala 2568:198] + node _T_507 = and(_T_506, _T_500) @[dec_tlu_ctl.scala 2568:198] + node _T_508 = and(_T_507, _T_502) @[dec_tlu_ctl.scala 2568:198] + node _T_509 = and(_T_508, _T_504) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_mhpme4 <= _T_509 @[dec_tlu_ctl.scala 2612:57] + node _T_510 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] + node _T_511 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] + node _T_512 = eq(_T_511, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_513 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] + node _T_514 = eq(_T_513, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_515 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] + node _T_516 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] + node _T_517 = eq(_T_516, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_518 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] + node _T_519 = and(_T_510, _T_512) @[dec_tlu_ctl.scala 2568:198] + node _T_520 = and(_T_519, _T_514) @[dec_tlu_ctl.scala 2568:198] + node _T_521 = and(_T_520, _T_515) @[dec_tlu_ctl.scala 2568:198] + node _T_522 = and(_T_521, _T_517) @[dec_tlu_ctl.scala 2568:198] + node _T_523 = and(_T_522, _T_518) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_mhpme5 <= _T_523 @[dec_tlu_ctl.scala 2613:57] + node _T_524 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] + node _T_525 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] + node _T_526 = eq(_T_525, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_527 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] + node _T_528 = eq(_T_527, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_529 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] + node _T_530 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] + node _T_531 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] + node _T_532 = eq(_T_531, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] + node _T_533 = and(_T_524, _T_526) @[dec_tlu_ctl.scala 2568:198] + node _T_534 = and(_T_533, _T_528) @[dec_tlu_ctl.scala 2568:198] + node _T_535 = and(_T_534, _T_529) @[dec_tlu_ctl.scala 2568:198] + node _T_536 = and(_T_535, _T_530) @[dec_tlu_ctl.scala 2568:198] + node _T_537 = and(_T_536, _T_532) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_mhpme6 <= _T_537 @[dec_tlu_ctl.scala 2614:57] + node _T_538 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] + node _T_539 = eq(_T_538, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_540 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] + node _T_541 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] + node _T_542 = eq(_T_541, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_543 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] + node _T_544 = eq(_T_543, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_545 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] + node _T_546 = eq(_T_545, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_547 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] + node _T_548 = eq(_T_547, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] + node _T_549 = and(_T_539, _T_540) @[dec_tlu_ctl.scala 2568:198] + node _T_550 = and(_T_549, _T_542) @[dec_tlu_ctl.scala 2568:198] + node _T_551 = and(_T_550, _T_544) @[dec_tlu_ctl.scala 2568:198] + node _T_552 = and(_T_551, _T_546) @[dec_tlu_ctl.scala 2568:198] + node _T_553 = and(_T_552, _T_548) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_mcountinhibit <= _T_553 @[dec_tlu_ctl.scala 2615:49] + node _T_554 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] + node _T_555 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] + node _T_556 = eq(_T_555, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_557 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] + node _T_558 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] + node _T_559 = eq(_T_558, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_560 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] + node _T_561 = eq(_T_560, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] + node _T_562 = and(_T_554, _T_556) @[dec_tlu_ctl.scala 2568:198] + node _T_563 = and(_T_562, _T_557) @[dec_tlu_ctl.scala 2568:198] + node _T_564 = and(_T_563, _T_559) @[dec_tlu_ctl.scala 2568:198] + node _T_565 = and(_T_564, _T_561) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_mitctl0 <= _T_565 @[dec_tlu_ctl.scala 2616:57] + node _T_566 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] + node _T_567 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] + node _T_568 = eq(_T_567, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_569 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] + node _T_570 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] + node _T_571 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] + node _T_572 = and(_T_566, _T_568) @[dec_tlu_ctl.scala 2568:198] + node _T_573 = and(_T_572, _T_569) @[dec_tlu_ctl.scala 2568:198] + node _T_574 = and(_T_573, _T_570) @[dec_tlu_ctl.scala 2568:198] + node _T_575 = and(_T_574, _T_571) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_mitctl1 <= _T_575 @[dec_tlu_ctl.scala 2617:57] + node _T_576 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] + node _T_577 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] + node _T_578 = eq(_T_577, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_579 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] + node _T_580 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] + node _T_581 = eq(_T_580, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_582 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] + node _T_583 = and(_T_576, _T_578) @[dec_tlu_ctl.scala 2568:198] + node _T_584 = and(_T_583, _T_579) @[dec_tlu_ctl.scala 2568:198] + node _T_585 = and(_T_584, _T_581) @[dec_tlu_ctl.scala 2568:198] + node _T_586 = and(_T_585, _T_582) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_mitb0 <= _T_586 @[dec_tlu_ctl.scala 2618:57] + node _T_587 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] + node _T_588 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] + node _T_589 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] + node _T_590 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] + node _T_591 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] + node _T_592 = eq(_T_591, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] + node _T_593 = and(_T_587, _T_588) @[dec_tlu_ctl.scala 2568:198] + node _T_594 = and(_T_593, _T_589) @[dec_tlu_ctl.scala 2568:198] + node _T_595 = and(_T_594, _T_590) @[dec_tlu_ctl.scala 2568:198] + node _T_596 = and(_T_595, _T_592) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_mitb1 <= _T_596 @[dec_tlu_ctl.scala 2619:57] + node _T_597 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] + node _T_598 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] + node _T_599 = eq(_T_598, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_600 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] + node _T_601 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] + node _T_602 = eq(_T_601, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_603 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] + node _T_604 = eq(_T_603, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] + node _T_605 = and(_T_597, _T_599) @[dec_tlu_ctl.scala 2568:198] + node _T_606 = and(_T_605, _T_600) @[dec_tlu_ctl.scala 2568:198] + node _T_607 = and(_T_606, _T_602) @[dec_tlu_ctl.scala 2568:198] + node _T_608 = and(_T_607, _T_604) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_mitcnt0 <= _T_608 @[dec_tlu_ctl.scala 2620:57] + node _T_609 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] + node _T_610 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] + node _T_611 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] + node _T_612 = eq(_T_611, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_613 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] + node _T_614 = and(_T_609, _T_610) @[dec_tlu_ctl.scala 2568:198] + node _T_615 = and(_T_614, _T_612) @[dec_tlu_ctl.scala 2568:198] + node _T_616 = and(_T_615, _T_613) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_mitcnt1 <= _T_616 @[dec_tlu_ctl.scala 2621:57] + node _T_617 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] + node _T_618 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] + node _T_619 = eq(_T_618, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_620 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] + node _T_621 = eq(_T_620, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_622 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] + node _T_623 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] + node _T_624 = and(_T_617, _T_619) @[dec_tlu_ctl.scala 2568:198] + node _T_625 = and(_T_624, _T_621) @[dec_tlu_ctl.scala 2568:198] + node _T_626 = and(_T_625, _T_622) @[dec_tlu_ctl.scala 2568:198] + node _T_627 = and(_T_626, _T_623) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_mpmc <= _T_627 @[dec_tlu_ctl.scala 2622:57] + node _T_628 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] + node _T_629 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] + node _T_630 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] + node _T_631 = eq(_T_630, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_632 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] + node _T_633 = eq(_T_632, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_634 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] + node _T_635 = eq(_T_634, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_636 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] + node _T_637 = and(_T_628, _T_629) @[dec_tlu_ctl.scala 2568:198] + node _T_638 = and(_T_637, _T_631) @[dec_tlu_ctl.scala 2568:198] + node _T_639 = and(_T_638, _T_633) @[dec_tlu_ctl.scala 2568:198] + node _T_640 = and(_T_639, _T_635) @[dec_tlu_ctl.scala 2568:198] + node _T_641 = and(_T_640, _T_636) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_mcpc <= _T_641 @[dec_tlu_ctl.scala 2623:57] + node _T_642 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] + node _T_643 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] + node _T_644 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] + node _T_645 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] + node _T_646 = eq(_T_645, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] + node _T_647 = and(_T_642, _T_643) @[dec_tlu_ctl.scala 2568:198] + node _T_648 = and(_T_647, _T_644) @[dec_tlu_ctl.scala 2568:198] + node _T_649 = and(_T_648, _T_646) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_meicpct <= _T_649 @[dec_tlu_ctl.scala 2624:57] + node _T_650 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149] + node _T_651 = eq(_T_650, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_652 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] + node _T_653 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] + node _T_654 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] + node _T_655 = eq(_T_654, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_656 = and(_T_651, _T_652) @[dec_tlu_ctl.scala 2568:198] + node _T_657 = and(_T_656, _T_653) @[dec_tlu_ctl.scala 2568:198] + node _T_658 = and(_T_657, _T_655) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_mdeau <= _T_658 @[dec_tlu_ctl.scala 2625:57] + node _T_659 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] + node _T_660 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] + node _T_661 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] + node _T_662 = eq(_T_661, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_663 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] + node _T_664 = eq(_T_663, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_665 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] + node _T_666 = eq(_T_665, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] + node _T_667 = and(_T_659, _T_660) @[dec_tlu_ctl.scala 2568:198] + node _T_668 = and(_T_667, _T_662) @[dec_tlu_ctl.scala 2568:198] + node _T_669 = and(_T_668, _T_664) @[dec_tlu_ctl.scala 2568:198] + node _T_670 = and(_T_669, _T_666) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_micect <= _T_670 @[dec_tlu_ctl.scala 2626:57] + node _T_671 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] + node _T_672 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] + node _T_673 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] + node _T_674 = eq(_T_673, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_675 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] + node _T_676 = and(_T_671, _T_672) @[dec_tlu_ctl.scala 2568:198] + node _T_677 = and(_T_676, _T_674) @[dec_tlu_ctl.scala 2568:198] + node _T_678 = and(_T_677, _T_675) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_miccmect <= _T_678 @[dec_tlu_ctl.scala 2627:57] + node _T_679 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] + node _T_680 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] + node _T_681 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] + node _T_682 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] + node _T_683 = eq(_T_682, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] + node _T_684 = and(_T_679, _T_680) @[dec_tlu_ctl.scala 2568:198] + node _T_685 = and(_T_684, _T_681) @[dec_tlu_ctl.scala 2568:198] + node _T_686 = and(_T_685, _T_683) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_mdccmect <= _T_686 @[dec_tlu_ctl.scala 2628:57] + node _T_687 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] + node _T_688 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] + node _T_689 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] + node _T_690 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] + node _T_691 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] + node _T_692 = eq(_T_691, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] + node _T_693 = and(_T_687, _T_688) @[dec_tlu_ctl.scala 2568:198] + node _T_694 = and(_T_693, _T_689) @[dec_tlu_ctl.scala 2568:198] + node _T_695 = and(_T_694, _T_690) @[dec_tlu_ctl.scala 2568:198] + node _T_696 = and(_T_695, _T_692) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_mfdht <= _T_696 @[dec_tlu_ctl.scala 2629:57] + node _T_697 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] + node _T_698 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] + node _T_699 = eq(_T_698, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_700 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] + node _T_701 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] + node _T_702 = and(_T_697, _T_699) @[dec_tlu_ctl.scala 2568:198] + node _T_703 = and(_T_702, _T_700) @[dec_tlu_ctl.scala 2568:198] + node _T_704 = and(_T_703, _T_701) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_mfdhs <= _T_704 @[dec_tlu_ctl.scala 2630:57] + node _T_705 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] + node _T_706 = eq(_T_705, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_707 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] + node _T_708 = eq(_T_707, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_709 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] + node _T_710 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] + node _T_711 = eq(_T_710, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_712 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] + node _T_713 = eq(_T_712, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_714 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] + node _T_715 = eq(_T_714, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] + node _T_716 = and(_T_706, _T_708) @[dec_tlu_ctl.scala 2568:198] + node _T_717 = and(_T_716, _T_709) @[dec_tlu_ctl.scala 2568:198] + node _T_718 = and(_T_717, _T_711) @[dec_tlu_ctl.scala 2568:198] + node _T_719 = and(_T_718, _T_713) @[dec_tlu_ctl.scala 2568:198] + node _T_720 = and(_T_719, _T_715) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_dicawics <= _T_720 @[dec_tlu_ctl.scala 2631:57] + node _T_721 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] + node _T_722 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] + node _T_723 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] + node _T_724 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] + node _T_725 = eq(_T_724, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_726 = and(_T_721, _T_722) @[dec_tlu_ctl.scala 2568:198] + node _T_727 = and(_T_726, _T_723) @[dec_tlu_ctl.scala 2568:198] + node _T_728 = and(_T_727, _T_725) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_dicad0h <= _T_728 @[dec_tlu_ctl.scala 2632:57] + node _T_729 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] + node _T_730 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] + node _T_731 = eq(_T_730, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_732 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] + node _T_733 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] + node _T_734 = eq(_T_733, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_735 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] + node _T_736 = and(_T_729, _T_731) @[dec_tlu_ctl.scala 2568:198] + node _T_737 = and(_T_736, _T_732) @[dec_tlu_ctl.scala 2568:198] + node _T_738 = and(_T_737, _T_734) @[dec_tlu_ctl.scala 2568:198] + node _T_739 = and(_T_738, _T_735) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_dicad0 <= _T_739 @[dec_tlu_ctl.scala 2633:57] + node _T_740 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] + node _T_741 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] + node _T_742 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] + node _T_743 = eq(_T_742, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_744 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] + node _T_745 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] + node _T_746 = eq(_T_745, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] + node _T_747 = and(_T_740, _T_741) @[dec_tlu_ctl.scala 2568:198] + node _T_748 = and(_T_747, _T_743) @[dec_tlu_ctl.scala 2568:198] + node _T_749 = and(_T_748, _T_744) @[dec_tlu_ctl.scala 2568:198] + node _T_750 = and(_T_749, _T_746) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_dicad1 <= _T_750 @[dec_tlu_ctl.scala 2634:57] + node _T_751 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] + node _T_752 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] + node _T_753 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] + node _T_754 = eq(_T_753, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_755 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] + node _T_756 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] + node _T_757 = and(_T_751, _T_752) @[dec_tlu_ctl.scala 2568:198] + node _T_758 = and(_T_757, _T_754) @[dec_tlu_ctl.scala 2568:198] + node _T_759 = and(_T_758, _T_755) @[dec_tlu_ctl.scala 2568:198] + node _T_760 = and(_T_759, _T_756) @[dec_tlu_ctl.scala 2568:198] + io.csr_pkt.csr_dicago <= _T_760 @[dec_tlu_ctl.scala 2635:57] + node _T_761 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] + node _T_762 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] + node _T_763 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] + node _T_764 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] + node _T_765 = eq(_T_764, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_766 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] + node _T_767 = and(_T_761, _T_762) @[dec_tlu_ctl.scala 2568:198] + node _T_768 = and(_T_767, _T_763) @[dec_tlu_ctl.scala 2568:198] + node _T_769 = and(_T_768, _T_765) @[dec_tlu_ctl.scala 2568:198] + node _T_770 = and(_T_769, _T_766) @[dec_tlu_ctl.scala 2568:198] + node _T_771 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] + node _T_772 = eq(_T_771, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_773 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] + node _T_774 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] + node _T_775 = eq(_T_774, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_776 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] + node _T_777 = eq(_T_776, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_778 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] + node _T_779 = eq(_T_778, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_780 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] + node _T_781 = eq(_T_780, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] + node _T_782 = and(_T_772, _T_773) @[dec_tlu_ctl.scala 2568:198] + node _T_783 = and(_T_782, _T_775) @[dec_tlu_ctl.scala 2568:198] + node _T_784 = and(_T_783, _T_777) @[dec_tlu_ctl.scala 2568:198] + node _T_785 = and(_T_784, _T_779) @[dec_tlu_ctl.scala 2568:198] + node _T_786 = and(_T_785, _T_781) @[dec_tlu_ctl.scala 2568:198] + node _T_787 = or(_T_770, _T_786) @[dec_tlu_ctl.scala 2636:81] + node _T_788 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] + node _T_789 = eq(_T_788, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_790 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] + node _T_791 = eq(_T_790, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_792 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] + node _T_793 = eq(_T_792, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_794 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] + node _T_795 = eq(_T_794, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_796 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] + node _T_797 = eq(_T_796, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_798 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] + node _T_799 = and(_T_789, _T_791) @[dec_tlu_ctl.scala 2568:198] + node _T_800 = and(_T_799, _T_793) @[dec_tlu_ctl.scala 2568:198] + node _T_801 = and(_T_800, _T_795) @[dec_tlu_ctl.scala 2568:198] + node _T_802 = and(_T_801, _T_797) @[dec_tlu_ctl.scala 2568:198] + node _T_803 = and(_T_802, _T_798) @[dec_tlu_ctl.scala 2568:198] + node _T_804 = or(_T_787, _T_803) @[dec_tlu_ctl.scala 2636:121] + node _T_805 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] + node _T_806 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] + node _T_807 = eq(_T_806, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_808 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] + node _T_809 = eq(_T_808, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_810 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] + node _T_811 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] + node _T_812 = eq(_T_811, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_813 = and(_T_805, _T_807) @[dec_tlu_ctl.scala 2568:198] + node _T_814 = and(_T_813, _T_809) @[dec_tlu_ctl.scala 2568:198] + node _T_815 = and(_T_814, _T_810) @[dec_tlu_ctl.scala 2568:198] + node _T_816 = and(_T_815, _T_812) @[dec_tlu_ctl.scala 2568:198] + node _T_817 = or(_T_804, _T_816) @[dec_tlu_ctl.scala 2636:155] + node _T_818 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] + node _T_819 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] + node _T_820 = eq(_T_819, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_821 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] + node _T_822 = eq(_T_821, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_823 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] + node _T_824 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] + node _T_825 = eq(_T_824, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] + node _T_826 = and(_T_818, _T_820) @[dec_tlu_ctl.scala 2568:198] + node _T_827 = and(_T_826, _T_822) @[dec_tlu_ctl.scala 2568:198] + node _T_828 = and(_T_827, _T_823) @[dec_tlu_ctl.scala 2568:198] + node _T_829 = and(_T_828, _T_825) @[dec_tlu_ctl.scala 2568:198] + node _T_830 = or(_T_817, _T_829) @[dec_tlu_ctl.scala 2637:97] + node _T_831 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] + node _T_832 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] + node _T_833 = eq(_T_832, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_834 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] + node _T_835 = eq(_T_834, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_836 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] + node _T_837 = eq(_T_836, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_838 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] + node _T_839 = eq(_T_838, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_840 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] + node _T_841 = and(_T_831, _T_833) @[dec_tlu_ctl.scala 2568:198] + node _T_842 = and(_T_841, _T_835) @[dec_tlu_ctl.scala 2568:198] + node _T_843 = and(_T_842, _T_837) @[dec_tlu_ctl.scala 2568:198] + node _T_844 = and(_T_843, _T_839) @[dec_tlu_ctl.scala 2568:198] + node _T_845 = and(_T_844, _T_840) @[dec_tlu_ctl.scala 2568:198] + node _T_846 = or(_T_830, _T_845) @[dec_tlu_ctl.scala 2637:137] + io.csr_pkt.presync <= _T_846 @[dec_tlu_ctl.scala 2636:34] + node _T_847 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] + node _T_848 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] + node _T_849 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] + node _T_850 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] + node _T_851 = eq(_T_850, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_852 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] + node _T_853 = and(_T_847, _T_848) @[dec_tlu_ctl.scala 2568:198] + node _T_854 = and(_T_853, _T_849) @[dec_tlu_ctl.scala 2568:198] + node _T_855 = and(_T_854, _T_851) @[dec_tlu_ctl.scala 2568:198] + node _T_856 = and(_T_855, _T_852) @[dec_tlu_ctl.scala 2568:198] + node _T_857 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] + node _T_858 = eq(_T_857, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_859 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] + node _T_860 = eq(_T_859, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_861 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] + node _T_862 = eq(_T_861, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_863 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] + node _T_864 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] + node _T_865 = and(_T_858, _T_860) @[dec_tlu_ctl.scala 2568:198] + node _T_866 = and(_T_865, _T_862) @[dec_tlu_ctl.scala 2568:198] + node _T_867 = and(_T_866, _T_863) @[dec_tlu_ctl.scala 2568:198] + node _T_868 = and(_T_867, _T_864) @[dec_tlu_ctl.scala 2568:198] + node _T_869 = or(_T_856, _T_868) @[dec_tlu_ctl.scala 2638:81] + node _T_870 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] + node _T_871 = eq(_T_870, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_872 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] + node _T_873 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] + node _T_874 = eq(_T_873, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_875 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] + node _T_876 = and(_T_871, _T_872) @[dec_tlu_ctl.scala 2568:198] + node _T_877 = and(_T_876, _T_874) @[dec_tlu_ctl.scala 2568:198] + node _T_878 = and(_T_877, _T_875) @[dec_tlu_ctl.scala 2568:198] + node _T_879 = or(_T_869, _T_878) @[dec_tlu_ctl.scala 2638:121] + node _T_880 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] + node _T_881 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] + node _T_882 = eq(_T_881, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_883 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] + node _T_884 = eq(_T_883, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_885 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] + node _T_886 = and(_T_880, _T_882) @[dec_tlu_ctl.scala 2568:198] + node _T_887 = and(_T_886, _T_884) @[dec_tlu_ctl.scala 2568:198] + node _T_888 = and(_T_887, _T_885) @[dec_tlu_ctl.scala 2568:198] + node _T_889 = or(_T_879, _T_888) @[dec_tlu_ctl.scala 2638:162] + node _T_890 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] + node _T_891 = eq(_T_890, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_892 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] + node _T_893 = eq(_T_892, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_894 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] + node _T_895 = eq(_T_894, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_896 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] + node _T_897 = eq(_T_896, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_898 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] + node _T_899 = eq(_T_898, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_900 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] + node _T_901 = eq(_T_900, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_902 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] + node _T_903 = eq(_T_902, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] + node _T_904 = and(_T_891, _T_893) @[dec_tlu_ctl.scala 2568:198] + node _T_905 = and(_T_904, _T_895) @[dec_tlu_ctl.scala 2568:198] + node _T_906 = and(_T_905, _T_897) @[dec_tlu_ctl.scala 2568:198] + node _T_907 = and(_T_906, _T_899) @[dec_tlu_ctl.scala 2568:198] + node _T_908 = and(_T_907, _T_901) @[dec_tlu_ctl.scala 2568:198] + node _T_909 = and(_T_908, _T_903) @[dec_tlu_ctl.scala 2568:198] + node _T_910 = or(_T_889, _T_909) @[dec_tlu_ctl.scala 2639:105] + node _T_911 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] + node _T_912 = eq(_T_911, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_913 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] + node _T_914 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] + node _T_915 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] + node _T_916 = eq(_T_915, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_917 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] + node _T_918 = eq(_T_917, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_919 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] + node _T_920 = eq(_T_919, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_921 = and(_T_912, _T_913) @[dec_tlu_ctl.scala 2568:198] + node _T_922 = and(_T_921, _T_914) @[dec_tlu_ctl.scala 2568:198] + node _T_923 = and(_T_922, _T_916) @[dec_tlu_ctl.scala 2568:198] + node _T_924 = and(_T_923, _T_918) @[dec_tlu_ctl.scala 2568:198] + node _T_925 = and(_T_924, _T_920) @[dec_tlu_ctl.scala 2568:198] + node _T_926 = or(_T_910, _T_925) @[dec_tlu_ctl.scala 2639:145] + node _T_927 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] + node _T_928 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] + node _T_929 = eq(_T_928, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_930 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] + node _T_931 = eq(_T_930, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_932 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] + node _T_933 = eq(_T_932, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_934 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] + node _T_935 = and(_T_927, _T_929) @[dec_tlu_ctl.scala 2568:198] + node _T_936 = and(_T_935, _T_931) @[dec_tlu_ctl.scala 2568:198] + node _T_937 = and(_T_936, _T_933) @[dec_tlu_ctl.scala 2568:198] + node _T_938 = and(_T_937, _T_934) @[dec_tlu_ctl.scala 2568:198] + node _T_939 = or(_T_926, _T_938) @[dec_tlu_ctl.scala 2639:178] + io.csr_pkt.postsync <= _T_939 @[dec_tlu_ctl.scala 2638:30] + node _T_940 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] + node _T_941 = eq(_T_940, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_942 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] + node _T_943 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] + node _T_944 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] + node _T_945 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] + node _T_946 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] + node _T_947 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] + node _T_948 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] + node _T_949 = eq(_T_948, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_950 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] + node _T_951 = eq(_T_950, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_952 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] + node _T_953 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] + node _T_954 = eq(_T_953, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] + node _T_955 = and(_T_941, _T_942) @[dec_tlu_ctl.scala 2568:198] + node _T_956 = and(_T_955, _T_943) @[dec_tlu_ctl.scala 2568:198] + node _T_957 = and(_T_956, _T_944) @[dec_tlu_ctl.scala 2568:198] + node _T_958 = and(_T_957, _T_945) @[dec_tlu_ctl.scala 2568:198] + node _T_959 = and(_T_958, _T_946) @[dec_tlu_ctl.scala 2568:198] + node _T_960 = and(_T_959, _T_947) @[dec_tlu_ctl.scala 2568:198] + node _T_961 = and(_T_960, _T_949) @[dec_tlu_ctl.scala 2568:198] + node _T_962 = and(_T_961, _T_951) @[dec_tlu_ctl.scala 2568:198] + node _T_963 = and(_T_962, _T_952) @[dec_tlu_ctl.scala 2568:198] + node _T_964 = and(_T_963, _T_954) @[dec_tlu_ctl.scala 2568:198] + node _T_965 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] + node _T_966 = eq(_T_965, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_967 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149] + node _T_968 = eq(_T_967, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_969 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] + node _T_970 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] + node _T_971 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] + node _T_972 = eq(_T_971, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_973 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] + node _T_974 = eq(_T_973, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_975 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] + node _T_976 = eq(_T_975, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_977 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] + node _T_978 = eq(_T_977, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_979 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] + node _T_980 = eq(_T_979, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_981 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] + node _T_982 = eq(_T_981, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_983 = and(_T_966, _T_968) @[dec_tlu_ctl.scala 2568:198] + node _T_984 = and(_T_983, _T_969) @[dec_tlu_ctl.scala 2568:198] + node _T_985 = and(_T_984, _T_970) @[dec_tlu_ctl.scala 2568:198] + node _T_986 = and(_T_985, _T_972) @[dec_tlu_ctl.scala 2568:198] + node _T_987 = and(_T_986, _T_974) @[dec_tlu_ctl.scala 2568:198] + node _T_988 = and(_T_987, _T_976) @[dec_tlu_ctl.scala 2568:198] + node _T_989 = and(_T_988, _T_978) @[dec_tlu_ctl.scala 2568:198] + node _T_990 = and(_T_989, _T_980) @[dec_tlu_ctl.scala 2568:198] + node _T_991 = and(_T_990, _T_982) @[dec_tlu_ctl.scala 2568:198] + node _T_992 = or(_T_964, _T_991) @[dec_tlu_ctl.scala 2641:81] + node _T_993 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] + node _T_994 = eq(_T_993, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_995 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149] + node _T_996 = eq(_T_995, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_997 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] + node _T_998 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] + node _T_999 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] + node _T_1000 = eq(_T_999, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1001 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] + node _T_1002 = eq(_T_1001, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1003 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] + node _T_1004 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] + node _T_1005 = eq(_T_1004, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1006 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] + node _T_1007 = eq(_T_1006, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] + node _T_1008 = and(_T_994, _T_996) @[dec_tlu_ctl.scala 2568:198] + node _T_1009 = and(_T_1008, _T_997) @[dec_tlu_ctl.scala 2568:198] + node _T_1010 = and(_T_1009, _T_998) @[dec_tlu_ctl.scala 2568:198] + node _T_1011 = and(_T_1010, _T_1000) @[dec_tlu_ctl.scala 2568:198] + node _T_1012 = and(_T_1011, _T_1002) @[dec_tlu_ctl.scala 2568:198] + node _T_1013 = and(_T_1012, _T_1003) @[dec_tlu_ctl.scala 2568:198] + node _T_1014 = and(_T_1013, _T_1005) @[dec_tlu_ctl.scala 2568:198] + node _T_1015 = and(_T_1014, _T_1007) @[dec_tlu_ctl.scala 2568:198] + node _T_1016 = or(_T_992, _T_1015) @[dec_tlu_ctl.scala 2641:129] + node _T_1017 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] + node _T_1018 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] + node _T_1019 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] + node _T_1020 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] + node _T_1021 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] + node _T_1022 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] + node _T_1023 = eq(_T_1022, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1024 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] + node _T_1025 = eq(_T_1024, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1026 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] + node _T_1027 = eq(_T_1026, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1028 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] + node _T_1029 = eq(_T_1028, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1030 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] + node _T_1031 = eq(_T_1030, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] + node _T_1032 = and(_T_1017, _T_1018) @[dec_tlu_ctl.scala 2568:198] + node _T_1033 = and(_T_1032, _T_1019) @[dec_tlu_ctl.scala 2568:198] + node _T_1034 = and(_T_1033, _T_1020) @[dec_tlu_ctl.scala 2568:198] + node _T_1035 = and(_T_1034, _T_1021) @[dec_tlu_ctl.scala 2568:198] + node _T_1036 = and(_T_1035, _T_1023) @[dec_tlu_ctl.scala 2568:198] + node _T_1037 = and(_T_1036, _T_1025) @[dec_tlu_ctl.scala 2568:198] + node _T_1038 = and(_T_1037, _T_1027) @[dec_tlu_ctl.scala 2568:198] + node _T_1039 = and(_T_1038, _T_1029) @[dec_tlu_ctl.scala 2568:198] + node _T_1040 = and(_T_1039, _T_1031) @[dec_tlu_ctl.scala 2568:198] + node _T_1041 = or(_T_1016, _T_1040) @[dec_tlu_ctl.scala 2642:105] + node _T_1042 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] + node _T_1043 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149] + node _T_1044 = eq(_T_1043, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1045 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] + node _T_1046 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] + node _T_1047 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] + node _T_1048 = eq(_T_1047, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1049 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] + node _T_1050 = eq(_T_1049, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1051 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] + node _T_1052 = eq(_T_1051, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] + node _T_1053 = and(_T_1042, _T_1044) @[dec_tlu_ctl.scala 2568:198] + node _T_1054 = and(_T_1053, _T_1045) @[dec_tlu_ctl.scala 2568:198] + node _T_1055 = and(_T_1054, _T_1046) @[dec_tlu_ctl.scala 2568:198] + node _T_1056 = and(_T_1055, _T_1048) @[dec_tlu_ctl.scala 2568:198] + node _T_1057 = and(_T_1056, _T_1050) @[dec_tlu_ctl.scala 2568:198] + node _T_1058 = and(_T_1057, _T_1052) @[dec_tlu_ctl.scala 2568:198] + node _T_1059 = or(_T_1041, _T_1058) @[dec_tlu_ctl.scala 2642:153] + node _T_1060 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] + node _T_1061 = eq(_T_1060, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1062 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] + node _T_1063 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] + node _T_1064 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] + node _T_1065 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] + node _T_1066 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] + node _T_1067 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] + node _T_1068 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] + node _T_1069 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] + node _T_1070 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] + node _T_1071 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] + node _T_1072 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] + node _T_1073 = and(_T_1061, _T_1062) @[dec_tlu_ctl.scala 2568:198] + node _T_1074 = and(_T_1073, _T_1063) @[dec_tlu_ctl.scala 2568:198] + node _T_1075 = and(_T_1074, _T_1064) @[dec_tlu_ctl.scala 2568:198] + node _T_1076 = and(_T_1075, _T_1065) @[dec_tlu_ctl.scala 2568:198] + node _T_1077 = and(_T_1076, _T_1066) @[dec_tlu_ctl.scala 2568:198] + node _T_1078 = and(_T_1077, _T_1067) @[dec_tlu_ctl.scala 2568:198] + node _T_1079 = and(_T_1078, _T_1068) @[dec_tlu_ctl.scala 2568:198] + node _T_1080 = and(_T_1079, _T_1069) @[dec_tlu_ctl.scala 2568:198] + node _T_1081 = and(_T_1080, _T_1070) @[dec_tlu_ctl.scala 2568:198] + node _T_1082 = and(_T_1081, _T_1071) @[dec_tlu_ctl.scala 2568:198] + node _T_1083 = and(_T_1082, _T_1072) @[dec_tlu_ctl.scala 2568:198] + node _T_1084 = or(_T_1059, _T_1083) @[dec_tlu_ctl.scala 2643:105] + node _T_1085 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] + node _T_1086 = eq(_T_1085, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1087 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] + node _T_1088 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] + node _T_1089 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] + node _T_1090 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] + node _T_1091 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] + node _T_1092 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] + node _T_1093 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] + node _T_1094 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] + node _T_1095 = eq(_T_1094, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1096 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] + node _T_1097 = eq(_T_1096, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1098 = and(_T_1086, _T_1087) @[dec_tlu_ctl.scala 2568:198] + node _T_1099 = and(_T_1098, _T_1088) @[dec_tlu_ctl.scala 2568:198] + node _T_1100 = and(_T_1099, _T_1089) @[dec_tlu_ctl.scala 2568:198] + node _T_1101 = and(_T_1100, _T_1090) @[dec_tlu_ctl.scala 2568:198] + node _T_1102 = and(_T_1101, _T_1091) @[dec_tlu_ctl.scala 2568:198] + node _T_1103 = and(_T_1102, _T_1092) @[dec_tlu_ctl.scala 2568:198] + node _T_1104 = and(_T_1103, _T_1093) @[dec_tlu_ctl.scala 2568:198] + node _T_1105 = and(_T_1104, _T_1095) @[dec_tlu_ctl.scala 2568:198] + node _T_1106 = and(_T_1105, _T_1097) @[dec_tlu_ctl.scala 2568:198] + node _T_1107 = or(_T_1084, _T_1106) @[dec_tlu_ctl.scala 2643:153] + node _T_1108 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] + node _T_1109 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] + node _T_1110 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] + node _T_1111 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] + node _T_1112 = eq(_T_1111, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1113 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] + node _T_1114 = eq(_T_1113, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1115 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] + node _T_1116 = eq(_T_1115, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1117 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] + node _T_1118 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] + node _T_1119 = eq(_T_1118, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1120 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] + node _T_1121 = eq(_T_1120, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1122 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] + node _T_1123 = and(_T_1108, _T_1109) @[dec_tlu_ctl.scala 2568:198] + node _T_1124 = and(_T_1123, _T_1110) @[dec_tlu_ctl.scala 2568:198] + node _T_1125 = and(_T_1124, _T_1112) @[dec_tlu_ctl.scala 2568:198] + node _T_1126 = and(_T_1125, _T_1114) @[dec_tlu_ctl.scala 2568:198] + node _T_1127 = and(_T_1126, _T_1116) @[dec_tlu_ctl.scala 2568:198] + node _T_1128 = and(_T_1127, _T_1117) @[dec_tlu_ctl.scala 2568:198] + node _T_1129 = and(_T_1128, _T_1119) @[dec_tlu_ctl.scala 2568:198] + node _T_1130 = and(_T_1129, _T_1121) @[dec_tlu_ctl.scala 2568:198] + node _T_1131 = and(_T_1130, _T_1122) @[dec_tlu_ctl.scala 2568:198] + node _T_1132 = or(_T_1107, _T_1131) @[dec_tlu_ctl.scala 2644:105] + node _T_1133 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] + node _T_1134 = eq(_T_1133, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1135 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] + node _T_1136 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] + node _T_1137 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] + node _T_1138 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] + node _T_1139 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] + node _T_1140 = eq(_T_1139, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1141 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] + node _T_1142 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] + node _T_1143 = eq(_T_1142, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1144 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] + node _T_1145 = eq(_T_1144, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1146 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] + node _T_1147 = eq(_T_1146, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1148 = and(_T_1134, _T_1135) @[dec_tlu_ctl.scala 2568:198] + node _T_1149 = and(_T_1148, _T_1136) @[dec_tlu_ctl.scala 2568:198] + node _T_1150 = and(_T_1149, _T_1137) @[dec_tlu_ctl.scala 2568:198] + node _T_1151 = and(_T_1150, _T_1138) @[dec_tlu_ctl.scala 2568:198] + node _T_1152 = and(_T_1151, _T_1140) @[dec_tlu_ctl.scala 2568:198] + node _T_1153 = and(_T_1152, _T_1141) @[dec_tlu_ctl.scala 2568:198] + node _T_1154 = and(_T_1153, _T_1143) @[dec_tlu_ctl.scala 2568:198] + node _T_1155 = and(_T_1154, _T_1145) @[dec_tlu_ctl.scala 2568:198] + node _T_1156 = and(_T_1155, _T_1147) @[dec_tlu_ctl.scala 2568:198] + node _T_1157 = or(_T_1132, _T_1156) @[dec_tlu_ctl.scala 2644:161] + node _T_1158 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] + node _T_1159 = eq(_T_1158, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1160 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149] + node _T_1161 = eq(_T_1160, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1162 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] + node _T_1163 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] + node _T_1164 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] + node _T_1165 = eq(_T_1164, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1166 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] + node _T_1167 = eq(_T_1166, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1168 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] + node _T_1169 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] + node _T_1170 = and(_T_1159, _T_1161) @[dec_tlu_ctl.scala 2568:198] + node _T_1171 = and(_T_1170, _T_1162) @[dec_tlu_ctl.scala 2568:198] + node _T_1172 = and(_T_1171, _T_1163) @[dec_tlu_ctl.scala 2568:198] + node _T_1173 = and(_T_1172, _T_1165) @[dec_tlu_ctl.scala 2568:198] + node _T_1174 = and(_T_1173, _T_1167) @[dec_tlu_ctl.scala 2568:198] + node _T_1175 = and(_T_1174, _T_1168) @[dec_tlu_ctl.scala 2568:198] + node _T_1176 = and(_T_1175, _T_1169) @[dec_tlu_ctl.scala 2568:198] + node _T_1177 = or(_T_1157, _T_1176) @[dec_tlu_ctl.scala 2645:105] + node _T_1178 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] + node _T_1179 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] + node _T_1180 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] + node _T_1181 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] + node _T_1182 = eq(_T_1181, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1183 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] + node _T_1184 = eq(_T_1183, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1185 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] + node _T_1186 = eq(_T_1185, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1187 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] + node _T_1188 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] + node _T_1189 = eq(_T_1188, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1190 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] + node _T_1191 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] + node _T_1192 = eq(_T_1191, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1193 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] + node _T_1194 = eq(_T_1193, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] + node _T_1195 = and(_T_1178, _T_1179) @[dec_tlu_ctl.scala 2568:198] + node _T_1196 = and(_T_1195, _T_1180) @[dec_tlu_ctl.scala 2568:198] + node _T_1197 = and(_T_1196, _T_1182) @[dec_tlu_ctl.scala 2568:198] + node _T_1198 = and(_T_1197, _T_1184) @[dec_tlu_ctl.scala 2568:198] + node _T_1199 = and(_T_1198, _T_1186) @[dec_tlu_ctl.scala 2568:198] + node _T_1200 = and(_T_1199, _T_1187) @[dec_tlu_ctl.scala 2568:198] + node _T_1201 = and(_T_1200, _T_1189) @[dec_tlu_ctl.scala 2568:198] + node _T_1202 = and(_T_1201, _T_1190) @[dec_tlu_ctl.scala 2568:198] + node _T_1203 = and(_T_1202, _T_1192) @[dec_tlu_ctl.scala 2568:198] + node _T_1204 = and(_T_1203, _T_1194) @[dec_tlu_ctl.scala 2568:198] + node _T_1205 = or(_T_1177, _T_1204) @[dec_tlu_ctl.scala 2645:161] + node _T_1206 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] + node _T_1207 = eq(_T_1206, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1208 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] + node _T_1209 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] + node _T_1210 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] + node _T_1211 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] + node _T_1212 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] + node _T_1213 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] + node _T_1214 = eq(_T_1213, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1215 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] + node _T_1216 = eq(_T_1215, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1217 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] + node _T_1218 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] + node _T_1219 = and(_T_1207, _T_1208) @[dec_tlu_ctl.scala 2568:198] + node _T_1220 = and(_T_1219, _T_1209) @[dec_tlu_ctl.scala 2568:198] + node _T_1221 = and(_T_1220, _T_1210) @[dec_tlu_ctl.scala 2568:198] + node _T_1222 = and(_T_1221, _T_1211) @[dec_tlu_ctl.scala 2568:198] + node _T_1223 = and(_T_1222, _T_1212) @[dec_tlu_ctl.scala 2568:198] + node _T_1224 = and(_T_1223, _T_1214) @[dec_tlu_ctl.scala 2568:198] + node _T_1225 = and(_T_1224, _T_1216) @[dec_tlu_ctl.scala 2568:198] + node _T_1226 = and(_T_1225, _T_1217) @[dec_tlu_ctl.scala 2568:198] + node _T_1227 = and(_T_1226, _T_1218) @[dec_tlu_ctl.scala 2568:198] + node _T_1228 = or(_T_1205, _T_1227) @[dec_tlu_ctl.scala 2646:97] + node _T_1229 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] + node _T_1230 = eq(_T_1229, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1231 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] + node _T_1232 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] + node _T_1233 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] + node _T_1234 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] + node _T_1235 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] + node _T_1236 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] + node _T_1237 = eq(_T_1236, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1238 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] + node _T_1239 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] + node _T_1240 = eq(_T_1239, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1241 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] + node _T_1242 = and(_T_1230, _T_1231) @[dec_tlu_ctl.scala 2568:198] + node _T_1243 = and(_T_1242, _T_1232) @[dec_tlu_ctl.scala 2568:198] + node _T_1244 = and(_T_1243, _T_1233) @[dec_tlu_ctl.scala 2568:198] + node _T_1245 = and(_T_1244, _T_1234) @[dec_tlu_ctl.scala 2568:198] + node _T_1246 = and(_T_1245, _T_1235) @[dec_tlu_ctl.scala 2568:198] + node _T_1247 = and(_T_1246, _T_1237) @[dec_tlu_ctl.scala 2568:198] + node _T_1248 = and(_T_1247, _T_1238) @[dec_tlu_ctl.scala 2568:198] + node _T_1249 = and(_T_1248, _T_1240) @[dec_tlu_ctl.scala 2568:198] + node _T_1250 = and(_T_1249, _T_1241) @[dec_tlu_ctl.scala 2568:198] + node _T_1251 = or(_T_1228, _T_1250) @[dec_tlu_ctl.scala 2646:153] + node _T_1252 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] + node _T_1253 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] + node _T_1254 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] + node _T_1255 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] + node _T_1256 = eq(_T_1255, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1257 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] + node _T_1258 = eq(_T_1257, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1259 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] + node _T_1260 = eq(_T_1259, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1261 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] + node _T_1262 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] + node _T_1263 = eq(_T_1262, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1264 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] + node _T_1265 = eq(_T_1264, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1266 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] + node _T_1267 = and(_T_1252, _T_1253) @[dec_tlu_ctl.scala 2568:198] + node _T_1268 = and(_T_1267, _T_1254) @[dec_tlu_ctl.scala 2568:198] + node _T_1269 = and(_T_1268, _T_1256) @[dec_tlu_ctl.scala 2568:198] + node _T_1270 = and(_T_1269, _T_1258) @[dec_tlu_ctl.scala 2568:198] + node _T_1271 = and(_T_1270, _T_1260) @[dec_tlu_ctl.scala 2568:198] + node _T_1272 = and(_T_1271, _T_1261) @[dec_tlu_ctl.scala 2568:198] + node _T_1273 = and(_T_1272, _T_1263) @[dec_tlu_ctl.scala 2568:198] + node _T_1274 = and(_T_1273, _T_1265) @[dec_tlu_ctl.scala 2568:198] + node _T_1275 = and(_T_1274, _T_1266) @[dec_tlu_ctl.scala 2568:198] + node _T_1276 = or(_T_1251, _T_1275) @[dec_tlu_ctl.scala 2647:105] + node _T_1277 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] + node _T_1278 = eq(_T_1277, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1279 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149] + node _T_1280 = eq(_T_1279, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1281 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] + node _T_1282 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] + node _T_1283 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] + node _T_1284 = eq(_T_1283, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1285 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] + node _T_1286 = eq(_T_1285, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1287 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] + node _T_1288 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] + node _T_1289 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] + node _T_1290 = and(_T_1278, _T_1280) @[dec_tlu_ctl.scala 2568:198] + node _T_1291 = and(_T_1290, _T_1281) @[dec_tlu_ctl.scala 2568:198] + node _T_1292 = and(_T_1291, _T_1282) @[dec_tlu_ctl.scala 2568:198] + node _T_1293 = and(_T_1292, _T_1284) @[dec_tlu_ctl.scala 2568:198] + node _T_1294 = and(_T_1293, _T_1286) @[dec_tlu_ctl.scala 2568:198] + node _T_1295 = and(_T_1294, _T_1287) @[dec_tlu_ctl.scala 2568:198] + node _T_1296 = and(_T_1295, _T_1288) @[dec_tlu_ctl.scala 2568:198] + node _T_1297 = and(_T_1296, _T_1289) @[dec_tlu_ctl.scala 2568:198] + node _T_1298 = or(_T_1276, _T_1297) @[dec_tlu_ctl.scala 2647:161] + node _T_1299 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] + node _T_1300 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149] + node _T_1301 = eq(_T_1300, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1302 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] + node _T_1303 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] + node _T_1304 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] + node _T_1305 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] + node _T_1306 = eq(_T_1305, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1307 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] + node _T_1308 = eq(_T_1307, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1309 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] + node _T_1310 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] + node _T_1311 = eq(_T_1310, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1312 = and(_T_1299, _T_1301) @[dec_tlu_ctl.scala 2568:198] + node _T_1313 = and(_T_1312, _T_1302) @[dec_tlu_ctl.scala 2568:198] + node _T_1314 = and(_T_1313, _T_1303) @[dec_tlu_ctl.scala 2568:198] + node _T_1315 = and(_T_1314, _T_1304) @[dec_tlu_ctl.scala 2568:198] + node _T_1316 = and(_T_1315, _T_1306) @[dec_tlu_ctl.scala 2568:198] + node _T_1317 = and(_T_1316, _T_1308) @[dec_tlu_ctl.scala 2568:198] + node _T_1318 = and(_T_1317, _T_1309) @[dec_tlu_ctl.scala 2568:198] + node _T_1319 = and(_T_1318, _T_1311) @[dec_tlu_ctl.scala 2568:198] + node _T_1320 = or(_T_1298, _T_1319) @[dec_tlu_ctl.scala 2648:105] + node _T_1321 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] + node _T_1322 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149] + node _T_1323 = eq(_T_1322, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1324 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] + node _T_1325 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] + node _T_1326 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] + node _T_1327 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] + node _T_1328 = eq(_T_1327, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1329 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] + node _T_1330 = eq(_T_1329, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1331 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] + node _T_1332 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] + node _T_1333 = eq(_T_1332, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1334 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] + node _T_1335 = eq(_T_1334, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] + node _T_1336 = and(_T_1321, _T_1323) @[dec_tlu_ctl.scala 2568:198] + node _T_1337 = and(_T_1336, _T_1324) @[dec_tlu_ctl.scala 2568:198] + node _T_1338 = and(_T_1337, _T_1325) @[dec_tlu_ctl.scala 2568:198] + node _T_1339 = and(_T_1338, _T_1326) @[dec_tlu_ctl.scala 2568:198] + node _T_1340 = and(_T_1339, _T_1328) @[dec_tlu_ctl.scala 2568:198] + node _T_1341 = and(_T_1340, _T_1330) @[dec_tlu_ctl.scala 2568:198] + node _T_1342 = and(_T_1341, _T_1331) @[dec_tlu_ctl.scala 2568:198] + node _T_1343 = and(_T_1342, _T_1333) @[dec_tlu_ctl.scala 2568:198] + node _T_1344 = and(_T_1343, _T_1335) @[dec_tlu_ctl.scala 2568:198] + node _T_1345 = or(_T_1320, _T_1344) @[dec_tlu_ctl.scala 2648:161] + node _T_1346 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] + node _T_1347 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149] + node _T_1348 = eq(_T_1347, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1349 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] + node _T_1350 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] + node _T_1351 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] + node _T_1352 = eq(_T_1351, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1353 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] + node _T_1354 = eq(_T_1353, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1355 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] + node _T_1356 = and(_T_1346, _T_1348) @[dec_tlu_ctl.scala 2568:198] + node _T_1357 = and(_T_1356, _T_1349) @[dec_tlu_ctl.scala 2568:198] + node _T_1358 = and(_T_1357, _T_1350) @[dec_tlu_ctl.scala 2568:198] + node _T_1359 = and(_T_1358, _T_1352) @[dec_tlu_ctl.scala 2568:198] + node _T_1360 = and(_T_1359, _T_1354) @[dec_tlu_ctl.scala 2568:198] + node _T_1361 = and(_T_1360, _T_1355) @[dec_tlu_ctl.scala 2568:198] + node _T_1362 = or(_T_1345, _T_1361) @[dec_tlu_ctl.scala 2649:105] + node _T_1363 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] + node _T_1364 = eq(_T_1363, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1365 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] + node _T_1366 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] + node _T_1367 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] + node _T_1368 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] + node _T_1369 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] + node _T_1370 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] + node _T_1371 = eq(_T_1370, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1372 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] + node _T_1373 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] + node _T_1374 = eq(_T_1373, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1375 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] + node _T_1376 = and(_T_1364, _T_1365) @[dec_tlu_ctl.scala 2568:198] + node _T_1377 = and(_T_1376, _T_1366) @[dec_tlu_ctl.scala 2568:198] + node _T_1378 = and(_T_1377, _T_1367) @[dec_tlu_ctl.scala 2568:198] + node _T_1379 = and(_T_1378, _T_1368) @[dec_tlu_ctl.scala 2568:198] + node _T_1380 = and(_T_1379, _T_1369) @[dec_tlu_ctl.scala 2568:198] + node _T_1381 = and(_T_1380, _T_1371) @[dec_tlu_ctl.scala 2568:198] + node _T_1382 = and(_T_1381, _T_1372) @[dec_tlu_ctl.scala 2568:198] + node _T_1383 = and(_T_1382, _T_1374) @[dec_tlu_ctl.scala 2568:198] + node _T_1384 = and(_T_1383, _T_1375) @[dec_tlu_ctl.scala 2568:198] + node _T_1385 = or(_T_1362, _T_1384) @[dec_tlu_ctl.scala 2649:161] + node _T_1386 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] + node _T_1387 = eq(_T_1386, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1388 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] + node _T_1389 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] + node _T_1390 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] + node _T_1391 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] + node _T_1392 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] + node _T_1393 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] + node _T_1394 = eq(_T_1393, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1395 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] + node _T_1396 = eq(_T_1395, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1397 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] + node _T_1398 = eq(_T_1397, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] + node _T_1399 = and(_T_1387, _T_1388) @[dec_tlu_ctl.scala 2568:198] + node _T_1400 = and(_T_1399, _T_1389) @[dec_tlu_ctl.scala 2568:198] + node _T_1401 = and(_T_1400, _T_1390) @[dec_tlu_ctl.scala 2568:198] + node _T_1402 = and(_T_1401, _T_1391) @[dec_tlu_ctl.scala 2568:198] + node _T_1403 = and(_T_1402, _T_1392) @[dec_tlu_ctl.scala 2568:198] + node _T_1404 = and(_T_1403, _T_1394) @[dec_tlu_ctl.scala 2568:198] + node _T_1405 = and(_T_1404, _T_1396) @[dec_tlu_ctl.scala 2568:198] + node _T_1406 = and(_T_1405, _T_1398) @[dec_tlu_ctl.scala 2568:198] + node _T_1407 = or(_T_1385, _T_1406) @[dec_tlu_ctl.scala 2650:105] + node _T_1408 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] + node _T_1409 = eq(_T_1408, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1410 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] + node _T_1411 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] + node _T_1412 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] + node _T_1413 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] + node _T_1414 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] + node _T_1415 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] + node _T_1416 = eq(_T_1415, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1417 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] + node _T_1418 = eq(_T_1417, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1419 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] + node _T_1420 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] + node _T_1421 = eq(_T_1420, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1422 = and(_T_1409, _T_1410) @[dec_tlu_ctl.scala 2568:198] + node _T_1423 = and(_T_1422, _T_1411) @[dec_tlu_ctl.scala 2568:198] + node _T_1424 = and(_T_1423, _T_1412) @[dec_tlu_ctl.scala 2568:198] + node _T_1425 = and(_T_1424, _T_1413) @[dec_tlu_ctl.scala 2568:198] + node _T_1426 = and(_T_1425, _T_1414) @[dec_tlu_ctl.scala 2568:198] + node _T_1427 = and(_T_1426, _T_1416) @[dec_tlu_ctl.scala 2568:198] + node _T_1428 = and(_T_1427, _T_1418) @[dec_tlu_ctl.scala 2568:198] + node _T_1429 = and(_T_1428, _T_1419) @[dec_tlu_ctl.scala 2568:198] + node _T_1430 = and(_T_1429, _T_1421) @[dec_tlu_ctl.scala 2568:198] + node _T_1431 = or(_T_1407, _T_1430) @[dec_tlu_ctl.scala 2650:161] + node _T_1432 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] + node _T_1433 = eq(_T_1432, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1434 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] + node _T_1435 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] + node _T_1436 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] + node _T_1437 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] + node _T_1438 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] + node _T_1439 = eq(_T_1438, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1440 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] + node _T_1441 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] + node _T_1442 = eq(_T_1441, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1443 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] + node _T_1444 = eq(_T_1443, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1445 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] + node _T_1446 = eq(_T_1445, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1447 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] + node _T_1448 = eq(_T_1447, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] + node _T_1449 = and(_T_1433, _T_1434) @[dec_tlu_ctl.scala 2568:198] + node _T_1450 = and(_T_1449, _T_1435) @[dec_tlu_ctl.scala 2568:198] + node _T_1451 = and(_T_1450, _T_1436) @[dec_tlu_ctl.scala 2568:198] + node _T_1452 = and(_T_1451, _T_1437) @[dec_tlu_ctl.scala 2568:198] + node _T_1453 = and(_T_1452, _T_1439) @[dec_tlu_ctl.scala 2568:198] + node _T_1454 = and(_T_1453, _T_1440) @[dec_tlu_ctl.scala 2568:198] + node _T_1455 = and(_T_1454, _T_1442) @[dec_tlu_ctl.scala 2568:198] + node _T_1456 = and(_T_1455, _T_1444) @[dec_tlu_ctl.scala 2568:198] + node _T_1457 = and(_T_1456, _T_1446) @[dec_tlu_ctl.scala 2568:198] + node _T_1458 = and(_T_1457, _T_1448) @[dec_tlu_ctl.scala 2568:198] + node _T_1459 = or(_T_1431, _T_1458) @[dec_tlu_ctl.scala 2651:105] + node _T_1460 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] + node _T_1461 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149] + node _T_1462 = eq(_T_1461, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1463 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] + node _T_1464 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] + node _T_1465 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] + node _T_1466 = eq(_T_1465, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1467 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] + node _T_1468 = eq(_T_1467, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1469 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] + node _T_1470 = and(_T_1460, _T_1462) @[dec_tlu_ctl.scala 2568:198] + node _T_1471 = and(_T_1470, _T_1463) @[dec_tlu_ctl.scala 2568:198] + node _T_1472 = and(_T_1471, _T_1464) @[dec_tlu_ctl.scala 2568:198] + node _T_1473 = and(_T_1472, _T_1466) @[dec_tlu_ctl.scala 2568:198] + node _T_1474 = and(_T_1473, _T_1468) @[dec_tlu_ctl.scala 2568:198] + node _T_1475 = and(_T_1474, _T_1469) @[dec_tlu_ctl.scala 2568:198] + node _T_1476 = or(_T_1459, _T_1475) @[dec_tlu_ctl.scala 2651:153] + node _T_1477 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] + node _T_1478 = eq(_T_1477, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1479 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149] + node _T_1480 = eq(_T_1479, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1481 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] + node _T_1482 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] + node _T_1483 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] + node _T_1484 = eq(_T_1483, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1485 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] + node _T_1486 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] + node _T_1487 = eq(_T_1486, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1488 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] + node _T_1489 = eq(_T_1488, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1490 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] + node _T_1491 = eq(_T_1490, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1492 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] + node _T_1493 = eq(_T_1492, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1494 = and(_T_1478, _T_1480) @[dec_tlu_ctl.scala 2568:198] + node _T_1495 = and(_T_1494, _T_1481) @[dec_tlu_ctl.scala 2568:198] + node _T_1496 = and(_T_1495, _T_1482) @[dec_tlu_ctl.scala 2568:198] + node _T_1497 = and(_T_1496, _T_1484) @[dec_tlu_ctl.scala 2568:198] + node _T_1498 = and(_T_1497, _T_1485) @[dec_tlu_ctl.scala 2568:198] + node _T_1499 = and(_T_1498, _T_1487) @[dec_tlu_ctl.scala 2568:198] + node _T_1500 = and(_T_1499, _T_1489) @[dec_tlu_ctl.scala 2568:198] + node _T_1501 = and(_T_1500, _T_1491) @[dec_tlu_ctl.scala 2568:198] + node _T_1502 = and(_T_1501, _T_1493) @[dec_tlu_ctl.scala 2568:198] + node _T_1503 = or(_T_1476, _T_1502) @[dec_tlu_ctl.scala 2652:113] + node _T_1504 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] + node _T_1505 = eq(_T_1504, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1506 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149] + node _T_1507 = eq(_T_1506, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1508 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] + node _T_1509 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] + node _T_1510 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] + node _T_1511 = eq(_T_1510, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1512 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] + node _T_1513 = eq(_T_1512, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1514 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] + node _T_1515 = eq(_T_1514, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1516 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] + node _T_1517 = eq(_T_1516, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1518 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] + node _T_1519 = eq(_T_1518, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1520 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] + node _T_1521 = eq(_T_1520, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] + node _T_1522 = and(_T_1505, _T_1507) @[dec_tlu_ctl.scala 2568:198] + node _T_1523 = and(_T_1522, _T_1508) @[dec_tlu_ctl.scala 2568:198] + node _T_1524 = and(_T_1523, _T_1509) @[dec_tlu_ctl.scala 2568:198] + node _T_1525 = and(_T_1524, _T_1511) @[dec_tlu_ctl.scala 2568:198] + node _T_1526 = and(_T_1525, _T_1513) @[dec_tlu_ctl.scala 2568:198] + node _T_1527 = and(_T_1526, _T_1515) @[dec_tlu_ctl.scala 2568:198] + node _T_1528 = and(_T_1527, _T_1517) @[dec_tlu_ctl.scala 2568:198] + node _T_1529 = and(_T_1528, _T_1519) @[dec_tlu_ctl.scala 2568:198] + node _T_1530 = and(_T_1529, _T_1521) @[dec_tlu_ctl.scala 2568:198] + node _T_1531 = or(_T_1503, _T_1530) @[dec_tlu_ctl.scala 2652:161] + node _T_1532 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] + node _T_1533 = eq(_T_1532, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1534 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149] + node _T_1535 = eq(_T_1534, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1536 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] + node _T_1537 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] + node _T_1538 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] + node _T_1539 = eq(_T_1538, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1540 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] + node _T_1541 = eq(_T_1540, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1542 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] + node _T_1543 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] + node _T_1544 = and(_T_1533, _T_1535) @[dec_tlu_ctl.scala 2568:198] + node _T_1545 = and(_T_1544, _T_1536) @[dec_tlu_ctl.scala 2568:198] + node _T_1546 = and(_T_1545, _T_1537) @[dec_tlu_ctl.scala 2568:198] + node _T_1547 = and(_T_1546, _T_1539) @[dec_tlu_ctl.scala 2568:198] + node _T_1548 = and(_T_1547, _T_1541) @[dec_tlu_ctl.scala 2568:198] + node _T_1549 = and(_T_1548, _T_1542) @[dec_tlu_ctl.scala 2568:198] + node _T_1550 = and(_T_1549, _T_1543) @[dec_tlu_ctl.scala 2568:198] + node _T_1551 = or(_T_1531, _T_1550) @[dec_tlu_ctl.scala 2653:97] + node _T_1552 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] + node _T_1553 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149] + node _T_1554 = eq(_T_1553, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1555 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] + node _T_1556 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] + node _T_1557 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] + node _T_1558 = eq(_T_1557, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1559 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] + node _T_1560 = eq(_T_1559, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1561 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] + node _T_1562 = and(_T_1552, _T_1554) @[dec_tlu_ctl.scala 2568:198] + node _T_1563 = and(_T_1562, _T_1555) @[dec_tlu_ctl.scala 2568:198] + node _T_1564 = and(_T_1563, _T_1556) @[dec_tlu_ctl.scala 2568:198] + node _T_1565 = and(_T_1564, _T_1558) @[dec_tlu_ctl.scala 2568:198] + node _T_1566 = and(_T_1565, _T_1560) @[dec_tlu_ctl.scala 2568:198] + node _T_1567 = and(_T_1566, _T_1561) @[dec_tlu_ctl.scala 2568:198] + node _T_1568 = or(_T_1551, _T_1567) @[dec_tlu_ctl.scala 2653:153] + node _T_1569 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] + node _T_1570 = eq(_T_1569, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1571 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149] + node _T_1572 = eq(_T_1571, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1573 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] + node _T_1574 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] + node _T_1575 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] + node _T_1576 = eq(_T_1575, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1577 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] + node _T_1578 = eq(_T_1577, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1579 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] + node _T_1580 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] + node _T_1581 = and(_T_1570, _T_1572) @[dec_tlu_ctl.scala 2568:198] + node _T_1582 = and(_T_1581, _T_1573) @[dec_tlu_ctl.scala 2568:198] + node _T_1583 = and(_T_1582, _T_1574) @[dec_tlu_ctl.scala 2568:198] + node _T_1584 = and(_T_1583, _T_1576) @[dec_tlu_ctl.scala 2568:198] + node _T_1585 = and(_T_1584, _T_1578) @[dec_tlu_ctl.scala 2568:198] + node _T_1586 = and(_T_1585, _T_1579) @[dec_tlu_ctl.scala 2568:198] + node _T_1587 = and(_T_1586, _T_1580) @[dec_tlu_ctl.scala 2568:198] + node _T_1588 = or(_T_1568, _T_1587) @[dec_tlu_ctl.scala 2654:113] + node _T_1589 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] + node _T_1590 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149] + node _T_1591 = eq(_T_1590, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1592 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] + node _T_1593 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] + node _T_1594 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] + node _T_1595 = eq(_T_1594, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1596 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] + node _T_1597 = eq(_T_1596, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] + node _T_1598 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] + node _T_1599 = and(_T_1589, _T_1591) @[dec_tlu_ctl.scala 2568:198] + node _T_1600 = and(_T_1599, _T_1592) @[dec_tlu_ctl.scala 2568:198] + node _T_1601 = and(_T_1600, _T_1593) @[dec_tlu_ctl.scala 2568:198] + node _T_1602 = and(_T_1601, _T_1595) @[dec_tlu_ctl.scala 2568:198] + node _T_1603 = and(_T_1602, _T_1597) @[dec_tlu_ctl.scala 2568:198] + node _T_1604 = and(_T_1603, _T_1598) @[dec_tlu_ctl.scala 2568:198] + node _T_1605 = or(_T_1588, _T_1604) @[dec_tlu_ctl.scala 2654:169] + io.csr_pkt.legal <= _T_1605 @[dec_tlu_ctl.scala 2641:26] module dec_tlu_ctl : input clock : Clock @@ -78198,761 +78208,761 @@ circuit quasar_wrapper : reg _T_33 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 331:89] _T_33 <= force_halt @[dec_tlu_ctl.scala 331:89] io.tlu_mem.dec_tlu_force_halt <= _T_33 @[dec_tlu_ctl.scala 331:57] - io.dec_tlu_i0_kill_writeb_r <= tlu_i0_kill_writeb_r @[dec_tlu_ctl.scala 335:41] - reg reset_detect : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 336:88] - reset_detect <= UInt<1>("h01") @[dec_tlu_ctl.scala 336:88] - reg reset_detected : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 337:88] - reset_detected <= reset_detect @[dec_tlu_ctl.scala 337:88] - node _T_34 = xor(reset_detect, reset_detected) @[dec_tlu_ctl.scala 338:64] - reset_delayed <= _T_34 @[dec_tlu_ctl.scala 338:49] - reg nmi_int_delayed : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 340:72] - nmi_int_delayed <= nmi_int_sync @[dec_tlu_ctl.scala 340:72] - reg nmi_int_detected_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 341:72] - nmi_int_detected_f <= nmi_int_detected @[dec_tlu_ctl.scala 341:72] - reg nmi_lsu_load_type_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 342:72] - nmi_lsu_load_type_f <= nmi_lsu_load_type @[dec_tlu_ctl.scala 342:72] - reg nmi_lsu_store_type_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 343:72] - nmi_lsu_store_type_f <= nmi_lsu_store_type @[dec_tlu_ctl.scala 343:72] - node _T_35 = not(mdseac_locked_f) @[dec_tlu_ctl.scala 347:32] - node _T_36 = or(io.tlu_busbuff.lsu_imprecise_error_load_any, io.tlu_busbuff.lsu_imprecise_error_store_any) @[dec_tlu_ctl.scala 347:96] - node nmi_lsu_detected = and(_T_35, _T_36) @[dec_tlu_ctl.scala 347:49] - node _T_37 = not(nmi_int_delayed) @[dec_tlu_ctl.scala 349:45] - node _T_38 = and(nmi_int_sync, _T_37) @[dec_tlu_ctl.scala 349:43] - node _T_39 = or(_T_38, nmi_lsu_detected) @[dec_tlu_ctl.scala 349:63] - node _T_40 = not(take_nmi_r_d1) @[dec_tlu_ctl.scala 349:106] - node _T_41 = and(nmi_int_detected_f, _T_40) @[dec_tlu_ctl.scala 349:104] - node _T_42 = or(_T_39, _T_41) @[dec_tlu_ctl.scala 349:82] - node _T_43 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 349:165] - node _T_44 = and(take_ext_int_start_d3, _T_43) @[dec_tlu_ctl.scala 349:146] - node _T_45 = or(_T_42, _T_44) @[dec_tlu_ctl.scala 349:122] - nmi_int_detected <= _T_45 @[dec_tlu_ctl.scala 349:26] - node _T_46 = and(nmi_lsu_detected, io.tlu_busbuff.lsu_imprecise_error_load_any) @[dec_tlu_ctl.scala 351:48] - node _T_47 = not(take_nmi_r_d1) @[dec_tlu_ctl.scala 351:119] - node _T_48 = and(nmi_int_detected_f, _T_47) @[dec_tlu_ctl.scala 351:117] - node _T_49 = not(_T_48) @[dec_tlu_ctl.scala 351:96] - node _T_50 = and(_T_46, _T_49) @[dec_tlu_ctl.scala 351:94] - node _T_51 = not(take_nmi_r_d1) @[dec_tlu_ctl.scala 351:161] - node _T_52 = and(nmi_lsu_load_type_f, _T_51) @[dec_tlu_ctl.scala 351:159] - node _T_53 = or(_T_50, _T_52) @[dec_tlu_ctl.scala 351:136] - nmi_lsu_load_type <= _T_53 @[dec_tlu_ctl.scala 351:27] - node _T_54 = and(nmi_lsu_detected, io.tlu_busbuff.lsu_imprecise_error_store_any) @[dec_tlu_ctl.scala 352:49] - node _T_55 = not(take_nmi_r_d1) @[dec_tlu_ctl.scala 352:121] - node _T_56 = and(nmi_int_detected_f, _T_55) @[dec_tlu_ctl.scala 352:119] - node _T_57 = not(_T_56) @[dec_tlu_ctl.scala 352:98] - node _T_58 = and(_T_54, _T_57) @[dec_tlu_ctl.scala 352:96] - node _T_59 = not(take_nmi_r_d1) @[dec_tlu_ctl.scala 352:164] - node _T_60 = and(nmi_lsu_store_type_f, _T_59) @[dec_tlu_ctl.scala 352:162] - node _T_61 = or(_T_58, _T_60) @[dec_tlu_ctl.scala 352:138] - nmi_lsu_store_type <= _T_61 @[dec_tlu_ctl.scala 352:28] - node _T_62 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 359:69] - node mpc_debug_halt_req_sync = and(mpc_debug_halt_req_sync_raw, _T_62) @[dec_tlu_ctl.scala 359:67] - reg mpc_debug_halt_req_sync_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 360:72] - mpc_debug_halt_req_sync_f <= mpc_debug_halt_req_sync @[dec_tlu_ctl.scala 360:72] - reg mpc_debug_run_req_sync_f : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 361:72] - mpc_debug_run_req_sync_f <= mpc_debug_run_req_sync @[dec_tlu_ctl.scala 361:72] - reg _T_63 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 362:89] - _T_63 <= mpc_halt_state_ns @[dec_tlu_ctl.scala 362:89] - mpc_halt_state_f <= _T_63 @[dec_tlu_ctl.scala 362:57] - reg mpc_run_state_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 363:88] - mpc_run_state_f <= mpc_run_state_ns @[dec_tlu_ctl.scala 363:88] - reg debug_brkpt_status_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 364:80] - debug_brkpt_status_f <= debug_brkpt_status_ns @[dec_tlu_ctl.scala 364:80] - reg mpc_debug_halt_ack_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 365:80] - mpc_debug_halt_ack_f <= mpc_debug_halt_ack_ns @[dec_tlu_ctl.scala 365:80] - reg mpc_debug_run_ack_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 366:80] - mpc_debug_run_ack_f <= mpc_debug_run_ack_ns @[dec_tlu_ctl.scala 366:80] - reg _T_64 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 367:89] - _T_64 <= dbg_halt_state_ns @[dec_tlu_ctl.scala 367:89] - dbg_halt_state_f <= _T_64 @[dec_tlu_ctl.scala 367:57] - reg dbg_run_state_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 368:88] - dbg_run_state_f <= dbg_run_state_ns @[dec_tlu_ctl.scala 368:88] - reg _T_65 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 369:81] - _T_65 <= dec_tlu_mpc_halted_only_ns @[dec_tlu_ctl.scala 369:81] - io.dec_tlu_mpc_halted_only <= _T_65 @[dec_tlu_ctl.scala 369:49] - node _T_66 = not(mpc_debug_halt_req_sync_f) @[dec_tlu_ctl.scala 373:71] - node mpc_debug_halt_req_sync_pulse = and(mpc_debug_halt_req_sync, _T_66) @[dec_tlu_ctl.scala 373:69] - node _T_67 = not(mpc_debug_run_req_sync_f) @[dec_tlu_ctl.scala 374:70] - node mpc_debug_run_req_sync_pulse = and(mpc_debug_run_req_sync, _T_67) @[dec_tlu_ctl.scala 374:68] - node _T_68 = or(mpc_halt_state_f, mpc_debug_halt_req_sync_pulse) @[dec_tlu_ctl.scala 376:48] - node _T_69 = not(io.mpc_reset_run_req) @[dec_tlu_ctl.scala 376:99] - node _T_70 = and(reset_delayed, _T_69) @[dec_tlu_ctl.scala 376:97] - node _T_71 = or(_T_68, _T_70) @[dec_tlu_ctl.scala 376:80] - node _T_72 = not(mpc_debug_run_req_sync) @[dec_tlu_ctl.scala 376:125] - node _T_73 = and(_T_71, _T_72) @[dec_tlu_ctl.scala 376:123] - mpc_halt_state_ns <= _T_73 @[dec_tlu_ctl.scala 376:27] - node _T_74 = not(mpc_debug_run_ack_f) @[dec_tlu_ctl.scala 377:80] - node _T_75 = and(mpc_debug_run_req_sync_pulse, _T_74) @[dec_tlu_ctl.scala 377:78] - node _T_76 = or(mpc_run_state_f, _T_75) @[dec_tlu_ctl.scala 377:46] - node _T_77 = not(dcsr_single_step_running_f) @[dec_tlu_ctl.scala 377:133] - node _T_78 = and(debug_mode_status, _T_77) @[dec_tlu_ctl.scala 377:131] - node _T_79 = and(_T_76, _T_78) @[dec_tlu_ctl.scala 377:103] - mpc_run_state_ns <= _T_79 @[dec_tlu_ctl.scala 377:26] - node _T_80 = or(dbg_halt_req_final, dcsr_single_step_done_f) @[dec_tlu_ctl.scala 379:70] - node _T_81 = or(_T_80, trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 379:96] - node _T_82 = or(_T_81, ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 379:121] - node _T_83 = or(dbg_halt_state_f, _T_82) @[dec_tlu_ctl.scala 379:48] - node _T_84 = not(io.dbg_resume_req) @[dec_tlu_ctl.scala 379:153] - node _T_85 = and(_T_83, _T_84) @[dec_tlu_ctl.scala 379:151] - dbg_halt_state_ns <= _T_85 @[dec_tlu_ctl.scala 379:27] - node _T_86 = or(dbg_run_state_f, io.dbg_resume_req) @[dec_tlu_ctl.scala 380:46] - node _T_87 = not(dcsr_single_step_running_f) @[dec_tlu_ctl.scala 380:97] - node _T_88 = and(debug_mode_status, _T_87) @[dec_tlu_ctl.scala 380:95] - node _T_89 = and(_T_86, _T_88) @[dec_tlu_ctl.scala 380:67] - dbg_run_state_ns <= _T_89 @[dec_tlu_ctl.scala 380:26] - node _T_90 = not(dbg_halt_state_f) @[dec_tlu_ctl.scala 383:39] - node _T_91 = and(_T_90, mpc_halt_state_f) @[dec_tlu_ctl.scala 383:57] - dec_tlu_mpc_halted_only_ns <= _T_91 @[dec_tlu_ctl.scala 383:36] - node debug_brkpt_valid = or(ebreak_to_debug_mode_r_d1, trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 386:59] - node _T_92 = or(debug_brkpt_valid, debug_brkpt_status_f) @[dec_tlu_ctl.scala 387:53] - node _T_93 = not(dcsr_single_step_running_f) @[dec_tlu_ctl.scala 387:105] - node _T_94 = and(internal_dbg_halt_mode, _T_93) @[dec_tlu_ctl.scala 387:103] - node _T_95 = and(_T_92, _T_94) @[dec_tlu_ctl.scala 387:77] - debug_brkpt_status_ns <= _T_95 @[dec_tlu_ctl.scala 387:31] - node _T_96 = and(mpc_halt_state_f, debug_mode_status) @[dec_tlu_ctl.scala 390:51] - node _T_97 = and(_T_96, mpc_debug_halt_req_sync) @[dec_tlu_ctl.scala 390:78] - node _T_98 = and(_T_97, core_empty) @[dec_tlu_ctl.scala 390:104] - mpc_debug_halt_ack_ns <= _T_98 @[dec_tlu_ctl.scala 390:31] - node _T_99 = not(dbg_halt_state_ns) @[dec_tlu_ctl.scala 391:59] - node _T_100 = and(mpc_debug_run_req_sync, _T_99) @[dec_tlu_ctl.scala 391:57] - node _T_101 = not(mpc_debug_halt_req_sync) @[dec_tlu_ctl.scala 391:80] - node _T_102 = and(_T_100, _T_101) @[dec_tlu_ctl.scala 391:78] - node _T_103 = and(mpc_debug_run_ack_f, mpc_debug_run_req_sync) @[dec_tlu_ctl.scala 391:129] - node _T_104 = or(_T_102, _T_103) @[dec_tlu_ctl.scala 391:106] - mpc_debug_run_ack_ns <= _T_104 @[dec_tlu_ctl.scala 391:30] - io.mpc_debug_halt_ack <= mpc_debug_halt_ack_f @[dec_tlu_ctl.scala 394:31] - io.mpc_debug_run_ack <= mpc_debug_run_ack_f @[dec_tlu_ctl.scala 395:31] - io.debug_brkpt_status <= debug_brkpt_status_f @[dec_tlu_ctl.scala 396:31] - node _T_105 = or(io.dbg_halt_req, dbg_halt_req_held) @[dec_tlu_ctl.scala 399:53] - node dbg_halt_req_held_ns = and(_T_105, ext_int_freeze_d1) @[dec_tlu_ctl.scala 399:74] - node _T_106 = or(io.dbg_halt_req, dbg_halt_req_held) @[dec_tlu_ctl.scala 400:48] - node _T_107 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 400:71] - node _T_108 = and(_T_106, _T_107) @[dec_tlu_ctl.scala 400:69] - dbg_halt_req_final <= _T_108 @[dec_tlu_ctl.scala 400:28] - node _T_109 = or(dbg_halt_req_final, mpc_debug_halt_req_sync) @[dec_tlu_ctl.scala 403:50] - node _T_110 = not(io.mpc_reset_run_req) @[dec_tlu_ctl.scala 403:95] - node _T_111 = and(reset_delayed, _T_110) @[dec_tlu_ctl.scala 403:93] - node _T_112 = or(_T_109, _T_111) @[dec_tlu_ctl.scala 403:76] - node _T_113 = not(debug_mode_status) @[dec_tlu_ctl.scala 403:121] - node _T_114 = and(_T_112, _T_113) @[dec_tlu_ctl.scala 403:119] - node _T_115 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 403:149] - node debug_halt_req = and(_T_114, _T_115) @[dec_tlu_ctl.scala 403:147] - node _T_116 = not(debug_resume_req_f) @[dec_tlu_ctl.scala 405:32] - node _T_117 = not(dbg_halt_state_ns) @[dec_tlu_ctl.scala 405:75] - node _T_118 = and(mpc_run_state_ns, _T_117) @[dec_tlu_ctl.scala 405:73] - node _T_119 = not(mpc_halt_state_ns) @[dec_tlu_ctl.scala 405:117] - node _T_120 = and(dbg_run_state_ns, _T_119) @[dec_tlu_ctl.scala 405:115] - node _T_121 = or(_T_118, _T_120) @[dec_tlu_ctl.scala 405:95] - node debug_resume_req = and(_T_116, _T_121) @[dec_tlu_ctl.scala 405:52] - node _T_122 = or(debug_halt_req_f, pmu_fw_halt_req_f) @[dec_tlu_ctl.scala 410:43] - node _T_123 = not(synchronous_flush_r) @[dec_tlu_ctl.scala 410:66] - node _T_124 = and(_T_122, _T_123) @[dec_tlu_ctl.scala 410:64] - node _T_125 = not(mret_r) @[dec_tlu_ctl.scala 410:89] - node _T_126 = and(_T_124, _T_125) @[dec_tlu_ctl.scala 410:87] - node _T_127 = not(halt_taken_f) @[dec_tlu_ctl.scala 410:99] - node _T_128 = and(_T_126, _T_127) @[dec_tlu_ctl.scala 410:97] - node _T_129 = not(dec_tlu_flush_noredir_r_d1) @[dec_tlu_ctl.scala 410:115] - node _T_130 = and(_T_128, _T_129) @[dec_tlu_ctl.scala 410:113] - node _T_131 = not(take_reset) @[dec_tlu_ctl.scala 410:145] - node take_halt = and(_T_130, _T_131) @[dec_tlu_ctl.scala 410:143] - node _T_132 = not(dec_tlu_flush_pause_r_d1) @[dec_tlu_ctl.scala 413:56] - node _T_133 = and(dec_tlu_flush_noredir_r_d1, _T_132) @[dec_tlu_ctl.scala 413:54] - node _T_134 = not(take_ext_int_start_d1) @[dec_tlu_ctl.scala 413:84] - node _T_135 = and(_T_133, _T_134) @[dec_tlu_ctl.scala 413:82] - node _T_136 = not(dbg_tlu_halted_f) @[dec_tlu_ctl.scala 413:126] - node _T_137 = and(halt_taken_f, _T_136) @[dec_tlu_ctl.scala 413:124] - node _T_138 = not(pmu_fw_tlu_halted_f) @[dec_tlu_ctl.scala 413:146] - node _T_139 = and(_T_137, _T_138) @[dec_tlu_ctl.scala 413:144] - node _T_140 = not(interrupt_valid_r_d1) @[dec_tlu_ctl.scala 413:169] - node _T_141 = and(_T_139, _T_140) @[dec_tlu_ctl.scala 413:167] - node halt_taken = or(_T_135, _T_141) @[dec_tlu_ctl.scala 413:108] - node _T_142 = and(io.lsu_idle_any, lsu_idle_any_f) @[dec_tlu_ctl.scala 417:53] - node _T_143 = and(_T_142, io.tlu_mem.ifu_miss_state_idle) @[dec_tlu_ctl.scala 417:70] - node _T_144 = and(_T_143, ifu_miss_state_idle_f) @[dec_tlu_ctl.scala 417:103] - node _T_145 = not(debug_halt_req) @[dec_tlu_ctl.scala 417:129] - node _T_146 = and(_T_144, _T_145) @[dec_tlu_ctl.scala 417:127] - node _T_147 = not(debug_halt_req_d1) @[dec_tlu_ctl.scala 417:147] - node _T_148 = and(_T_146, _T_147) @[dec_tlu_ctl.scala 417:145] - node _T_149 = not(io.dec_div_active) @[dec_tlu_ctl.scala 417:168] - node _T_150 = and(_T_148, _T_149) @[dec_tlu_ctl.scala 417:166] - node _T_151 = or(force_halt, _T_150) @[dec_tlu_ctl.scala 417:34] - core_empty <= _T_151 @[dec_tlu_ctl.scala 417:20] - node _T_152 = not(debug_mode_status) @[dec_tlu_ctl.scala 423:37] - node _T_153 = and(_T_152, debug_halt_req) @[dec_tlu_ctl.scala 423:63] - node _T_154 = or(_T_153, dcsr_single_step_done_f) @[dec_tlu_ctl.scala 423:81] - node _T_155 = or(_T_154, trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 423:107] - node enter_debug_halt_req = or(_T_155, ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 423:132] - node _T_156 = bits(dcsr, 2, 2) @[dec_tlu_ctl.scala 426:111] - node _T_157 = not(_T_156) @[dec_tlu_ctl.scala 426:106] - node _T_158 = and(debug_resume_req_f, _T_157) @[dec_tlu_ctl.scala 426:104] - node _T_159 = not(_T_158) @[dec_tlu_ctl.scala 426:83] - node _T_160 = and(debug_mode_status, _T_159) @[dec_tlu_ctl.scala 426:81] - node _T_161 = or(debug_halt_req_ns, _T_160) @[dec_tlu_ctl.scala 426:53] - internal_dbg_halt_mode <= _T_161 @[dec_tlu_ctl.scala 426:32] - node _T_162 = not(dcsr_single_step_running_f) @[dec_tlu_ctl.scala 428:67] - node allow_dbg_halt_csr_write = and(debug_mode_status, _T_162) @[dec_tlu_ctl.scala 428:65] - node _T_163 = and(debug_halt_req_f, core_empty) @[dec_tlu_ctl.scala 433:48] - node _T_164 = and(_T_163, halt_taken) @[dec_tlu_ctl.scala 433:61] - node _T_165 = not(debug_resume_req_f) @[dec_tlu_ctl.scala 433:97] - node _T_166 = and(dbg_tlu_halted_f, _T_165) @[dec_tlu_ctl.scala 433:95] - node dbg_tlu_halted = or(_T_164, _T_166) @[dec_tlu_ctl.scala 433:75] - node _T_167 = not(dbg_tlu_halted) @[dec_tlu_ctl.scala 434:73] - node _T_168 = and(debug_halt_req_f, _T_167) @[dec_tlu_ctl.scala 434:71] - node _T_169 = or(enter_debug_halt_req, _T_168) @[dec_tlu_ctl.scala 434:51] - debug_halt_req_ns <= _T_169 @[dec_tlu_ctl.scala 434:27] - node _T_170 = and(debug_resume_req_f, dbg_tlu_halted_f) @[dec_tlu_ctl.scala 435:49] - node resume_ack_ns = and(_T_170, dbg_run_state_ns) @[dec_tlu_ctl.scala 435:68] - node _T_171 = not(io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 437:61] - node _T_172 = and(io.dec_tlu_i0_valid_r, _T_171) @[dec_tlu_ctl.scala 437:59] - node _T_173 = bits(dcsr, 2, 2) @[dec_tlu_ctl.scala 437:90] - node _T_174 = and(_T_172, _T_173) @[dec_tlu_ctl.scala 437:84] - node _T_175 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 437:104] - node dcsr_single_step_done = and(_T_174, _T_175) @[dec_tlu_ctl.scala 437:102] - node _T_176 = bits(dcsr, 2, 2) @[dec_tlu_ctl.scala 439:66] - node _T_177 = and(debug_resume_req_f, _T_176) @[dec_tlu_ctl.scala 439:60] - node _T_178 = not(dcsr_single_step_done_f) @[dec_tlu_ctl.scala 439:111] - node _T_179 = and(dcsr_single_step_running_f, _T_178) @[dec_tlu_ctl.scala 439:109] - node dcsr_single_step_running = or(_T_177, _T_179) @[dec_tlu_ctl.scala 439:79] - node dbg_cmd_done_ns = and(io.dec_tlu_i0_valid_r, io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 441:53] - node _T_180 = or(trigger_hit_dmode_r, ebreak_to_debug_mode_r) @[dec_tlu_ctl.scala 444:57] - node _T_181 = not(io.dec_tlu_flush_lower_wb) @[dec_tlu_ctl.scala 444:112] - node _T_182 = and(request_debug_mode_r_d1, _T_181) @[dec_tlu_ctl.scala 444:110] - node request_debug_mode_r = or(_T_180, _T_182) @[dec_tlu_ctl.scala 444:83] - node _T_183 = or(request_debug_mode_r_d1, request_debug_mode_done_f) @[dec_tlu_ctl.scala 446:64] - node _T_184 = not(dbg_tlu_halted_f) @[dec_tlu_ctl.scala 446:95] - node request_debug_mode_done = and(_T_183, _T_184) @[dec_tlu_ctl.scala 446:93] - reg _T_185 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 449:81] - _T_185 <= io.tlu_ifc.dec_tlu_flush_noredir_wb @[dec_tlu_ctl.scala 449:81] - dec_tlu_flush_noredir_r_d1 <= _T_185 @[dec_tlu_ctl.scala 449:49] - reg _T_186 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 450:89] - _T_186 <= halt_taken @[dec_tlu_ctl.scala 450:89] - halt_taken_f <= _T_186 @[dec_tlu_ctl.scala 450:57] - reg _T_187 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 451:89] - _T_187 <= io.lsu_idle_any @[dec_tlu_ctl.scala 451:89] - lsu_idle_any_f <= _T_187 @[dec_tlu_ctl.scala 451:57] - reg _T_188 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 452:81] - _T_188 <= io.tlu_mem.ifu_miss_state_idle @[dec_tlu_ctl.scala 452:81] - ifu_miss_state_idle_f <= _T_188 @[dec_tlu_ctl.scala 452:49] - reg _T_189 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 453:89] - _T_189 <= dbg_tlu_halted @[dec_tlu_ctl.scala 453:89] - dbg_tlu_halted_f <= _T_189 @[dec_tlu_ctl.scala 453:57] - reg _T_190 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 454:81] - _T_190 <= resume_ack_ns @[dec_tlu_ctl.scala 454:81] - io.dec_tlu_resume_ack <= _T_190 @[dec_tlu_ctl.scala 454:49] - reg _T_191 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 455:89] - _T_191 <= debug_halt_req_ns @[dec_tlu_ctl.scala 455:89] - debug_halt_req_f <= _T_191 @[dec_tlu_ctl.scala 455:57] - reg _T_192 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 456:89] - _T_192 <= debug_resume_req @[dec_tlu_ctl.scala 456:89] - debug_resume_req_f <= _T_192 @[dec_tlu_ctl.scala 456:57] - reg _T_193 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 457:81] - _T_193 <= trigger_hit_dmode_r @[dec_tlu_ctl.scala 457:81] - trigger_hit_dmode_r_d1 <= _T_193 @[dec_tlu_ctl.scala 457:49] - reg _T_194 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 458:81] - _T_194 <= dcsr_single_step_done @[dec_tlu_ctl.scala 458:81] - dcsr_single_step_done_f <= _T_194 @[dec_tlu_ctl.scala 458:49] - reg _T_195 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 459:89] - _T_195 <= debug_halt_req @[dec_tlu_ctl.scala 459:89] - debug_halt_req_d1 <= _T_195 @[dec_tlu_ctl.scala 459:57] - reg dec_tlu_wr_pause_r_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 460:81] - dec_tlu_wr_pause_r_d1 <= io.dec_tlu_wr_pause_r @[dec_tlu_ctl.scala 460:81] - reg dec_pause_state_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 461:81] - dec_pause_state_f <= io.dec_pause_state @[dec_tlu_ctl.scala 461:81] - reg _T_196 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 462:81] - _T_196 <= request_debug_mode_r @[dec_tlu_ctl.scala 462:81] - request_debug_mode_r_d1 <= _T_196 @[dec_tlu_ctl.scala 462:49] - reg _T_197 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 463:73] - _T_197 <= request_debug_mode_done @[dec_tlu_ctl.scala 463:73] - request_debug_mode_done_f <= _T_197 @[dec_tlu_ctl.scala 463:41] - reg _T_198 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 464:73] - _T_198 <= dcsr_single_step_running @[dec_tlu_ctl.scala 464:73] - dcsr_single_step_running_f <= _T_198 @[dec_tlu_ctl.scala 464:41] - reg _T_199 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 465:73] - _T_199 <= io.dec_tlu_flush_pause_r @[dec_tlu_ctl.scala 465:73] - dec_tlu_flush_pause_r_d1 <= _T_199 @[dec_tlu_ctl.scala 465:41] - reg _T_200 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 466:81] - _T_200 <= dbg_halt_req_held_ns @[dec_tlu_ctl.scala 466:81] - dbg_halt_req_held <= _T_200 @[dec_tlu_ctl.scala 466:49] - io.dec_tlu_debug_stall <= debug_halt_req_f @[dec_tlu_ctl.scala 469:41] - io.dec_tlu_dbg_halted <= dbg_tlu_halted_f @[dec_tlu_ctl.scala 470:41] - io.dec_tlu_debug_mode <= debug_mode_status @[dec_tlu_ctl.scala 471:41] - dec_tlu_pmu_fw_halted <= pmu_fw_tlu_halted_f @[dec_tlu_ctl.scala 472:41] - node _T_201 = and(fence_i_r, internal_dbg_halt_mode) @[dec_tlu_ctl.scala 475:71] - node _T_202 = or(take_halt, _T_201) @[dec_tlu_ctl.scala 475:58] - node _T_203 = or(_T_202, io.dec_tlu_flush_pause_r) @[dec_tlu_ctl.scala 475:97] - node _T_204 = and(i0_trigger_hit_r, trigger_hit_dmode_r) @[dec_tlu_ctl.scala 475:144] - node _T_205 = or(_T_203, _T_204) @[dec_tlu_ctl.scala 475:124] - node _T_206 = or(_T_205, take_ext_int_start) @[dec_tlu_ctl.scala 475:167] - io.tlu_ifc.dec_tlu_flush_noredir_wb <= _T_206 @[dec_tlu_ctl.scala 475:45] - io.dec_tlu_flush_extint <= take_ext_int_start @[dec_tlu_ctl.scala 477:33] - node _T_207 = not(interrupt_valid_r) @[dec_tlu_ctl.scala 480:61] - node _T_208 = and(dec_tlu_wr_pause_r_d1, _T_207) @[dec_tlu_ctl.scala 480:59] - node _T_209 = not(take_ext_int_start) @[dec_tlu_ctl.scala 480:82] - node _T_210 = and(_T_208, _T_209) @[dec_tlu_ctl.scala 480:80] - io.dec_tlu_flush_pause_r <= _T_210 @[dec_tlu_ctl.scala 480:34] - node _T_211 = not(io.dec_pause_state) @[dec_tlu_ctl.scala 482:28] - node _T_212 = and(_T_211, dec_pause_state_f) @[dec_tlu_ctl.scala 482:48] - node _T_213 = or(ext_int_ready, ce_int_ready) @[dec_tlu_ctl.scala 482:86] - node _T_214 = or(_T_213, timer_int_ready) @[dec_tlu_ctl.scala 482:101] - node _T_215 = or(_T_214, soft_int_ready) @[dec_tlu_ctl.scala 482:119] - node _T_216 = or(_T_215, int_timer0_int_hold_f) @[dec_tlu_ctl.scala 482:136] - node _T_217 = or(_T_216, int_timer1_int_hold_f) @[dec_tlu_ctl.scala 482:160] - node _T_218 = or(_T_217, nmi_int_detected) @[dec_tlu_ctl.scala 482:184] - node _T_219 = or(_T_218, ext_int_freeze_d1) @[dec_tlu_ctl.scala 482:203] - node _T_220 = not(_T_219) @[dec_tlu_ctl.scala 482:70] - node _T_221 = and(_T_212, _T_220) @[dec_tlu_ctl.scala 482:68] - node _T_222 = not(interrupt_valid_r_d1) @[dec_tlu_ctl.scala 482:226] - node _T_223 = and(_T_221, _T_222) @[dec_tlu_ctl.scala 482:224] - node _T_224 = not(debug_halt_req_f) @[dec_tlu_ctl.scala 482:250] - node _T_225 = and(_T_223, _T_224) @[dec_tlu_ctl.scala 482:248] - node _T_226 = not(pmu_fw_halt_req_f) @[dec_tlu_ctl.scala 482:270] - node _T_227 = and(_T_225, _T_226) @[dec_tlu_ctl.scala 482:268] - node _T_228 = not(halt_taken_f) @[dec_tlu_ctl.scala 482:291] - node _T_229 = and(_T_227, _T_228) @[dec_tlu_ctl.scala 482:289] - pause_expired_r <= _T_229 @[dec_tlu_ctl.scala 482:25] - node _T_230 = bits(dcsr, 2, 2) @[dec_tlu_ctl.scala 484:88] - node _T_231 = and(io.tlu_exu.dec_tlu_flush_lower_r, _T_230) @[dec_tlu_ctl.scala 484:82] - node _T_232 = or(io.dec_tlu_resume_ack, dcsr_single_step_running) @[dec_tlu_ctl.scala 484:125] - node _T_233 = and(_T_231, _T_232) @[dec_tlu_ctl.scala 484:100] - node _T_234 = not(io.tlu_ifc.dec_tlu_flush_noredir_wb) @[dec_tlu_ctl.scala 484:155] - node _T_235 = and(_T_233, _T_234) @[dec_tlu_ctl.scala 484:153] - io.tlu_bp.dec_tlu_flush_leak_one_wb <= _T_235 @[dec_tlu_ctl.scala 484:45] - node _T_236 = or(ic_perr_r_d1, iccm_sbecc_r_d1) @[dec_tlu_ctl.scala 485:93] - node _T_237 = and(io.tlu_exu.dec_tlu_flush_lower_r, _T_236) @[dec_tlu_ctl.scala 485:77] - io.tlu_mem.dec_tlu_flush_err_wb <= _T_237 @[dec_tlu_ctl.scala 485:41] - io.dec_dbg_cmd_done <= dbg_cmd_done_ns @[dec_tlu_ctl.scala 488:29] - node _T_238 = and(illegal_r, io.dec_dbg_cmd_done) @[dec_tlu_ctl.scala 489:42] - io.dec_dbg_cmd_fail <= _T_238 @[dec_tlu_ctl.scala 489:29] - node _T_239 = bits(mtdata1_t[3], 2, 2) @[dec_tlu_ctl.scala 502:48] - node _T_240 = bits(mtdata1_t[2], 2, 2) @[dec_tlu_ctl.scala 502:75] - node _T_241 = bits(mtdata1_t[1], 2, 2) @[dec_tlu_ctl.scala 502:102] - node _T_242 = bits(mtdata1_t[0], 2, 2) @[dec_tlu_ctl.scala 502:129] + io.dec_tlu_i0_kill_writeb_r <= tlu_i0_kill_writeb_r @[dec_tlu_ctl.scala 333:41] + reg reset_detect : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 334:88] + reset_detect <= UInt<1>("h01") @[dec_tlu_ctl.scala 334:88] + reg reset_detected : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 335:88] + reset_detected <= reset_detect @[dec_tlu_ctl.scala 335:88] + node _T_34 = xor(reset_detect, reset_detected) @[dec_tlu_ctl.scala 336:64] + reset_delayed <= _T_34 @[dec_tlu_ctl.scala 336:49] + reg nmi_int_delayed : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 338:72] + nmi_int_delayed <= nmi_int_sync @[dec_tlu_ctl.scala 338:72] + reg nmi_int_detected_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 339:72] + nmi_int_detected_f <= nmi_int_detected @[dec_tlu_ctl.scala 339:72] + reg nmi_lsu_load_type_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 340:72] + nmi_lsu_load_type_f <= nmi_lsu_load_type @[dec_tlu_ctl.scala 340:72] + reg nmi_lsu_store_type_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 341:72] + nmi_lsu_store_type_f <= nmi_lsu_store_type @[dec_tlu_ctl.scala 341:72] + node _T_35 = not(mdseac_locked_f) @[dec_tlu_ctl.scala 345:32] + node _T_36 = or(io.tlu_busbuff.lsu_imprecise_error_load_any, io.tlu_busbuff.lsu_imprecise_error_store_any) @[dec_tlu_ctl.scala 345:96] + node nmi_lsu_detected = and(_T_35, _T_36) @[dec_tlu_ctl.scala 345:49] + node _T_37 = not(nmi_int_delayed) @[dec_tlu_ctl.scala 347:45] + node _T_38 = and(nmi_int_sync, _T_37) @[dec_tlu_ctl.scala 347:43] + node _T_39 = or(_T_38, nmi_lsu_detected) @[dec_tlu_ctl.scala 347:63] + node _T_40 = not(take_nmi_r_d1) @[dec_tlu_ctl.scala 347:106] + node _T_41 = and(nmi_int_detected_f, _T_40) @[dec_tlu_ctl.scala 347:104] + node _T_42 = or(_T_39, _T_41) @[dec_tlu_ctl.scala 347:82] + node _T_43 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 347:165] + node _T_44 = and(take_ext_int_start_d3, _T_43) @[dec_tlu_ctl.scala 347:146] + node _T_45 = or(_T_42, _T_44) @[dec_tlu_ctl.scala 347:122] + nmi_int_detected <= _T_45 @[dec_tlu_ctl.scala 347:26] + node _T_46 = and(nmi_lsu_detected, io.tlu_busbuff.lsu_imprecise_error_load_any) @[dec_tlu_ctl.scala 349:48] + node _T_47 = not(take_nmi_r_d1) @[dec_tlu_ctl.scala 349:119] + node _T_48 = and(nmi_int_detected_f, _T_47) @[dec_tlu_ctl.scala 349:117] + node _T_49 = not(_T_48) @[dec_tlu_ctl.scala 349:96] + node _T_50 = and(_T_46, _T_49) @[dec_tlu_ctl.scala 349:94] + node _T_51 = not(take_nmi_r_d1) @[dec_tlu_ctl.scala 349:161] + node _T_52 = and(nmi_lsu_load_type_f, _T_51) @[dec_tlu_ctl.scala 349:159] + node _T_53 = or(_T_50, _T_52) @[dec_tlu_ctl.scala 349:136] + nmi_lsu_load_type <= _T_53 @[dec_tlu_ctl.scala 349:27] + node _T_54 = and(nmi_lsu_detected, io.tlu_busbuff.lsu_imprecise_error_store_any) @[dec_tlu_ctl.scala 350:49] + node _T_55 = not(take_nmi_r_d1) @[dec_tlu_ctl.scala 350:121] + node _T_56 = and(nmi_int_detected_f, _T_55) @[dec_tlu_ctl.scala 350:119] + node _T_57 = not(_T_56) @[dec_tlu_ctl.scala 350:98] + node _T_58 = and(_T_54, _T_57) @[dec_tlu_ctl.scala 350:96] + node _T_59 = not(take_nmi_r_d1) @[dec_tlu_ctl.scala 350:164] + node _T_60 = and(nmi_lsu_store_type_f, _T_59) @[dec_tlu_ctl.scala 350:162] + node _T_61 = or(_T_58, _T_60) @[dec_tlu_ctl.scala 350:138] + nmi_lsu_store_type <= _T_61 @[dec_tlu_ctl.scala 350:28] + node _T_62 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 357:69] + node mpc_debug_halt_req_sync = and(mpc_debug_halt_req_sync_raw, _T_62) @[dec_tlu_ctl.scala 357:67] + reg mpc_debug_halt_req_sync_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 358:72] + mpc_debug_halt_req_sync_f <= mpc_debug_halt_req_sync @[dec_tlu_ctl.scala 358:72] + reg mpc_debug_run_req_sync_f : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 359:72] + mpc_debug_run_req_sync_f <= mpc_debug_run_req_sync @[dec_tlu_ctl.scala 359:72] + reg _T_63 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 360:89] + _T_63 <= mpc_halt_state_ns @[dec_tlu_ctl.scala 360:89] + mpc_halt_state_f <= _T_63 @[dec_tlu_ctl.scala 360:57] + reg mpc_run_state_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 361:88] + mpc_run_state_f <= mpc_run_state_ns @[dec_tlu_ctl.scala 361:88] + reg debug_brkpt_status_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 362:80] + debug_brkpt_status_f <= debug_brkpt_status_ns @[dec_tlu_ctl.scala 362:80] + reg mpc_debug_halt_ack_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 363:80] + mpc_debug_halt_ack_f <= mpc_debug_halt_ack_ns @[dec_tlu_ctl.scala 363:80] + reg mpc_debug_run_ack_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 364:80] + mpc_debug_run_ack_f <= mpc_debug_run_ack_ns @[dec_tlu_ctl.scala 364:80] + reg _T_64 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 365:89] + _T_64 <= dbg_halt_state_ns @[dec_tlu_ctl.scala 365:89] + dbg_halt_state_f <= _T_64 @[dec_tlu_ctl.scala 365:57] + reg dbg_run_state_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 366:88] + dbg_run_state_f <= dbg_run_state_ns @[dec_tlu_ctl.scala 366:88] + reg _T_65 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 367:81] + _T_65 <= dec_tlu_mpc_halted_only_ns @[dec_tlu_ctl.scala 367:81] + io.dec_tlu_mpc_halted_only <= _T_65 @[dec_tlu_ctl.scala 367:49] + node _T_66 = not(mpc_debug_halt_req_sync_f) @[dec_tlu_ctl.scala 371:71] + node mpc_debug_halt_req_sync_pulse = and(mpc_debug_halt_req_sync, _T_66) @[dec_tlu_ctl.scala 371:69] + node _T_67 = not(mpc_debug_run_req_sync_f) @[dec_tlu_ctl.scala 372:70] + node mpc_debug_run_req_sync_pulse = and(mpc_debug_run_req_sync, _T_67) @[dec_tlu_ctl.scala 372:68] + node _T_68 = or(mpc_halt_state_f, mpc_debug_halt_req_sync_pulse) @[dec_tlu_ctl.scala 374:48] + node _T_69 = not(io.mpc_reset_run_req) @[dec_tlu_ctl.scala 374:99] + node _T_70 = and(reset_delayed, _T_69) @[dec_tlu_ctl.scala 374:97] + node _T_71 = or(_T_68, _T_70) @[dec_tlu_ctl.scala 374:80] + node _T_72 = not(mpc_debug_run_req_sync) @[dec_tlu_ctl.scala 374:125] + node _T_73 = and(_T_71, _T_72) @[dec_tlu_ctl.scala 374:123] + mpc_halt_state_ns <= _T_73 @[dec_tlu_ctl.scala 374:27] + node _T_74 = not(mpc_debug_run_ack_f) @[dec_tlu_ctl.scala 375:80] + node _T_75 = and(mpc_debug_run_req_sync_pulse, _T_74) @[dec_tlu_ctl.scala 375:78] + node _T_76 = or(mpc_run_state_f, _T_75) @[dec_tlu_ctl.scala 375:46] + node _T_77 = not(dcsr_single_step_running_f) @[dec_tlu_ctl.scala 375:133] + node _T_78 = and(debug_mode_status, _T_77) @[dec_tlu_ctl.scala 375:131] + node _T_79 = and(_T_76, _T_78) @[dec_tlu_ctl.scala 375:103] + mpc_run_state_ns <= _T_79 @[dec_tlu_ctl.scala 375:26] + node _T_80 = or(dbg_halt_req_final, dcsr_single_step_done_f) @[dec_tlu_ctl.scala 377:70] + node _T_81 = or(_T_80, trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 377:96] + node _T_82 = or(_T_81, ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 377:121] + node _T_83 = or(dbg_halt_state_f, _T_82) @[dec_tlu_ctl.scala 377:48] + node _T_84 = not(io.dbg_resume_req) @[dec_tlu_ctl.scala 377:153] + node _T_85 = and(_T_83, _T_84) @[dec_tlu_ctl.scala 377:151] + dbg_halt_state_ns <= _T_85 @[dec_tlu_ctl.scala 377:27] + node _T_86 = or(dbg_run_state_f, io.dbg_resume_req) @[dec_tlu_ctl.scala 378:46] + node _T_87 = not(dcsr_single_step_running_f) @[dec_tlu_ctl.scala 378:97] + node _T_88 = and(debug_mode_status, _T_87) @[dec_tlu_ctl.scala 378:95] + node _T_89 = and(_T_86, _T_88) @[dec_tlu_ctl.scala 378:67] + dbg_run_state_ns <= _T_89 @[dec_tlu_ctl.scala 378:26] + node _T_90 = not(dbg_halt_state_f) @[dec_tlu_ctl.scala 381:39] + node _T_91 = and(_T_90, mpc_halt_state_f) @[dec_tlu_ctl.scala 381:57] + dec_tlu_mpc_halted_only_ns <= _T_91 @[dec_tlu_ctl.scala 381:36] + node debug_brkpt_valid = or(ebreak_to_debug_mode_r_d1, trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 384:59] + node _T_92 = or(debug_brkpt_valid, debug_brkpt_status_f) @[dec_tlu_ctl.scala 385:53] + node _T_93 = not(dcsr_single_step_running_f) @[dec_tlu_ctl.scala 385:105] + node _T_94 = and(internal_dbg_halt_mode, _T_93) @[dec_tlu_ctl.scala 385:103] + node _T_95 = and(_T_92, _T_94) @[dec_tlu_ctl.scala 385:77] + debug_brkpt_status_ns <= _T_95 @[dec_tlu_ctl.scala 385:31] + node _T_96 = and(mpc_halt_state_f, debug_mode_status) @[dec_tlu_ctl.scala 388:51] + node _T_97 = and(_T_96, mpc_debug_halt_req_sync) @[dec_tlu_ctl.scala 388:78] + node _T_98 = and(_T_97, core_empty) @[dec_tlu_ctl.scala 388:104] + mpc_debug_halt_ack_ns <= _T_98 @[dec_tlu_ctl.scala 388:31] + node _T_99 = not(dbg_halt_state_ns) @[dec_tlu_ctl.scala 389:59] + node _T_100 = and(mpc_debug_run_req_sync, _T_99) @[dec_tlu_ctl.scala 389:57] + node _T_101 = not(mpc_debug_halt_req_sync) @[dec_tlu_ctl.scala 389:80] + node _T_102 = and(_T_100, _T_101) @[dec_tlu_ctl.scala 389:78] + node _T_103 = and(mpc_debug_run_ack_f, mpc_debug_run_req_sync) @[dec_tlu_ctl.scala 389:129] + node _T_104 = or(_T_102, _T_103) @[dec_tlu_ctl.scala 389:106] + mpc_debug_run_ack_ns <= _T_104 @[dec_tlu_ctl.scala 389:30] + io.mpc_debug_halt_ack <= mpc_debug_halt_ack_f @[dec_tlu_ctl.scala 392:31] + io.mpc_debug_run_ack <= mpc_debug_run_ack_f @[dec_tlu_ctl.scala 393:31] + io.debug_brkpt_status <= debug_brkpt_status_f @[dec_tlu_ctl.scala 394:31] + node _T_105 = or(io.dbg_halt_req, dbg_halt_req_held) @[dec_tlu_ctl.scala 397:53] + node dbg_halt_req_held_ns = and(_T_105, ext_int_freeze_d1) @[dec_tlu_ctl.scala 397:74] + node _T_106 = or(io.dbg_halt_req, dbg_halt_req_held) @[dec_tlu_ctl.scala 398:48] + node _T_107 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 398:71] + node _T_108 = and(_T_106, _T_107) @[dec_tlu_ctl.scala 398:69] + dbg_halt_req_final <= _T_108 @[dec_tlu_ctl.scala 398:28] + node _T_109 = or(dbg_halt_req_final, mpc_debug_halt_req_sync) @[dec_tlu_ctl.scala 401:50] + node _T_110 = not(io.mpc_reset_run_req) @[dec_tlu_ctl.scala 401:95] + node _T_111 = and(reset_delayed, _T_110) @[dec_tlu_ctl.scala 401:93] + node _T_112 = or(_T_109, _T_111) @[dec_tlu_ctl.scala 401:76] + node _T_113 = not(debug_mode_status) @[dec_tlu_ctl.scala 401:121] + node _T_114 = and(_T_112, _T_113) @[dec_tlu_ctl.scala 401:119] + node _T_115 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 401:149] + node debug_halt_req = and(_T_114, _T_115) @[dec_tlu_ctl.scala 401:147] + node _T_116 = not(debug_resume_req_f) @[dec_tlu_ctl.scala 403:32] + node _T_117 = not(dbg_halt_state_ns) @[dec_tlu_ctl.scala 403:75] + node _T_118 = and(mpc_run_state_ns, _T_117) @[dec_tlu_ctl.scala 403:73] + node _T_119 = not(mpc_halt_state_ns) @[dec_tlu_ctl.scala 403:117] + node _T_120 = and(dbg_run_state_ns, _T_119) @[dec_tlu_ctl.scala 403:115] + node _T_121 = or(_T_118, _T_120) @[dec_tlu_ctl.scala 403:95] + node debug_resume_req = and(_T_116, _T_121) @[dec_tlu_ctl.scala 403:52] + node _T_122 = or(debug_halt_req_f, pmu_fw_halt_req_f) @[dec_tlu_ctl.scala 408:43] + node _T_123 = not(synchronous_flush_r) @[dec_tlu_ctl.scala 408:66] + node _T_124 = and(_T_122, _T_123) @[dec_tlu_ctl.scala 408:64] + node _T_125 = not(mret_r) @[dec_tlu_ctl.scala 408:89] + node _T_126 = and(_T_124, _T_125) @[dec_tlu_ctl.scala 408:87] + node _T_127 = not(halt_taken_f) @[dec_tlu_ctl.scala 408:99] + node _T_128 = and(_T_126, _T_127) @[dec_tlu_ctl.scala 408:97] + node _T_129 = not(dec_tlu_flush_noredir_r_d1) @[dec_tlu_ctl.scala 408:115] + node _T_130 = and(_T_128, _T_129) @[dec_tlu_ctl.scala 408:113] + node _T_131 = not(take_reset) @[dec_tlu_ctl.scala 408:145] + node take_halt = and(_T_130, _T_131) @[dec_tlu_ctl.scala 408:143] + node _T_132 = not(dec_tlu_flush_pause_r_d1) @[dec_tlu_ctl.scala 411:56] + node _T_133 = and(dec_tlu_flush_noredir_r_d1, _T_132) @[dec_tlu_ctl.scala 411:54] + node _T_134 = not(take_ext_int_start_d1) @[dec_tlu_ctl.scala 411:84] + node _T_135 = and(_T_133, _T_134) @[dec_tlu_ctl.scala 411:82] + node _T_136 = not(dbg_tlu_halted_f) @[dec_tlu_ctl.scala 411:126] + node _T_137 = and(halt_taken_f, _T_136) @[dec_tlu_ctl.scala 411:124] + node _T_138 = not(pmu_fw_tlu_halted_f) @[dec_tlu_ctl.scala 411:146] + node _T_139 = and(_T_137, _T_138) @[dec_tlu_ctl.scala 411:144] + node _T_140 = not(interrupt_valid_r_d1) @[dec_tlu_ctl.scala 411:169] + node _T_141 = and(_T_139, _T_140) @[dec_tlu_ctl.scala 411:167] + node halt_taken = or(_T_135, _T_141) @[dec_tlu_ctl.scala 411:108] + node _T_142 = and(io.lsu_idle_any, lsu_idle_any_f) @[dec_tlu_ctl.scala 415:53] + node _T_143 = and(_T_142, io.tlu_mem.ifu_miss_state_idle) @[dec_tlu_ctl.scala 415:70] + node _T_144 = and(_T_143, ifu_miss_state_idle_f) @[dec_tlu_ctl.scala 415:103] + node _T_145 = not(debug_halt_req) @[dec_tlu_ctl.scala 415:129] + node _T_146 = and(_T_144, _T_145) @[dec_tlu_ctl.scala 415:127] + node _T_147 = not(debug_halt_req_d1) @[dec_tlu_ctl.scala 415:147] + node _T_148 = and(_T_146, _T_147) @[dec_tlu_ctl.scala 415:145] + node _T_149 = not(io.dec_div_active) @[dec_tlu_ctl.scala 415:168] + node _T_150 = and(_T_148, _T_149) @[dec_tlu_ctl.scala 415:166] + node _T_151 = or(force_halt, _T_150) @[dec_tlu_ctl.scala 415:34] + core_empty <= _T_151 @[dec_tlu_ctl.scala 415:20] + node _T_152 = not(debug_mode_status) @[dec_tlu_ctl.scala 421:37] + node _T_153 = and(_T_152, debug_halt_req) @[dec_tlu_ctl.scala 421:63] + node _T_154 = or(_T_153, dcsr_single_step_done_f) @[dec_tlu_ctl.scala 421:81] + node _T_155 = or(_T_154, trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 421:107] + node enter_debug_halt_req = or(_T_155, ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 421:132] + node _T_156 = bits(dcsr, 2, 2) @[dec_tlu_ctl.scala 424:111] + node _T_157 = not(_T_156) @[dec_tlu_ctl.scala 424:106] + node _T_158 = and(debug_resume_req_f, _T_157) @[dec_tlu_ctl.scala 424:104] + node _T_159 = not(_T_158) @[dec_tlu_ctl.scala 424:83] + node _T_160 = and(debug_mode_status, _T_159) @[dec_tlu_ctl.scala 424:81] + node _T_161 = or(debug_halt_req_ns, _T_160) @[dec_tlu_ctl.scala 424:53] + internal_dbg_halt_mode <= _T_161 @[dec_tlu_ctl.scala 424:32] + node _T_162 = not(dcsr_single_step_running_f) @[dec_tlu_ctl.scala 426:67] + node allow_dbg_halt_csr_write = and(debug_mode_status, _T_162) @[dec_tlu_ctl.scala 426:65] + node _T_163 = and(debug_halt_req_f, core_empty) @[dec_tlu_ctl.scala 431:48] + node _T_164 = and(_T_163, halt_taken) @[dec_tlu_ctl.scala 431:61] + node _T_165 = not(debug_resume_req_f) @[dec_tlu_ctl.scala 431:97] + node _T_166 = and(dbg_tlu_halted_f, _T_165) @[dec_tlu_ctl.scala 431:95] + node dbg_tlu_halted = or(_T_164, _T_166) @[dec_tlu_ctl.scala 431:75] + node _T_167 = not(dbg_tlu_halted) @[dec_tlu_ctl.scala 432:73] + node _T_168 = and(debug_halt_req_f, _T_167) @[dec_tlu_ctl.scala 432:71] + node _T_169 = or(enter_debug_halt_req, _T_168) @[dec_tlu_ctl.scala 432:51] + debug_halt_req_ns <= _T_169 @[dec_tlu_ctl.scala 432:27] + node _T_170 = and(debug_resume_req_f, dbg_tlu_halted_f) @[dec_tlu_ctl.scala 433:49] + node resume_ack_ns = and(_T_170, dbg_run_state_ns) @[dec_tlu_ctl.scala 433:68] + node _T_171 = not(io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 435:61] + node _T_172 = and(io.dec_tlu_i0_valid_r, _T_171) @[dec_tlu_ctl.scala 435:59] + node _T_173 = bits(dcsr, 2, 2) @[dec_tlu_ctl.scala 435:90] + node _T_174 = and(_T_172, _T_173) @[dec_tlu_ctl.scala 435:84] + node _T_175 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 435:104] + node dcsr_single_step_done = and(_T_174, _T_175) @[dec_tlu_ctl.scala 435:102] + node _T_176 = bits(dcsr, 2, 2) @[dec_tlu_ctl.scala 437:66] + node _T_177 = and(debug_resume_req_f, _T_176) @[dec_tlu_ctl.scala 437:60] + node _T_178 = not(dcsr_single_step_done_f) @[dec_tlu_ctl.scala 437:111] + node _T_179 = and(dcsr_single_step_running_f, _T_178) @[dec_tlu_ctl.scala 437:109] + node dcsr_single_step_running = or(_T_177, _T_179) @[dec_tlu_ctl.scala 437:79] + node dbg_cmd_done_ns = and(io.dec_tlu_i0_valid_r, io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 439:53] + node _T_180 = or(trigger_hit_dmode_r, ebreak_to_debug_mode_r) @[dec_tlu_ctl.scala 442:57] + node _T_181 = not(io.dec_tlu_flush_lower_wb) @[dec_tlu_ctl.scala 442:112] + node _T_182 = and(request_debug_mode_r_d1, _T_181) @[dec_tlu_ctl.scala 442:110] + node request_debug_mode_r = or(_T_180, _T_182) @[dec_tlu_ctl.scala 442:83] + node _T_183 = or(request_debug_mode_r_d1, request_debug_mode_done_f) @[dec_tlu_ctl.scala 444:64] + node _T_184 = not(dbg_tlu_halted_f) @[dec_tlu_ctl.scala 444:95] + node request_debug_mode_done = and(_T_183, _T_184) @[dec_tlu_ctl.scala 444:93] + reg _T_185 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 447:81] + _T_185 <= io.tlu_ifc.dec_tlu_flush_noredir_wb @[dec_tlu_ctl.scala 447:81] + dec_tlu_flush_noredir_r_d1 <= _T_185 @[dec_tlu_ctl.scala 447:49] + reg _T_186 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 448:89] + _T_186 <= halt_taken @[dec_tlu_ctl.scala 448:89] + halt_taken_f <= _T_186 @[dec_tlu_ctl.scala 448:57] + reg _T_187 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 449:89] + _T_187 <= io.lsu_idle_any @[dec_tlu_ctl.scala 449:89] + lsu_idle_any_f <= _T_187 @[dec_tlu_ctl.scala 449:57] + reg _T_188 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 450:81] + _T_188 <= io.tlu_mem.ifu_miss_state_idle @[dec_tlu_ctl.scala 450:81] + ifu_miss_state_idle_f <= _T_188 @[dec_tlu_ctl.scala 450:49] + reg _T_189 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 451:89] + _T_189 <= dbg_tlu_halted @[dec_tlu_ctl.scala 451:89] + dbg_tlu_halted_f <= _T_189 @[dec_tlu_ctl.scala 451:57] + reg _T_190 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 452:81] + _T_190 <= resume_ack_ns @[dec_tlu_ctl.scala 452:81] + io.dec_tlu_resume_ack <= _T_190 @[dec_tlu_ctl.scala 452:49] + reg _T_191 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 453:89] + _T_191 <= debug_halt_req_ns @[dec_tlu_ctl.scala 453:89] + debug_halt_req_f <= _T_191 @[dec_tlu_ctl.scala 453:57] + reg _T_192 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 454:89] + _T_192 <= debug_resume_req @[dec_tlu_ctl.scala 454:89] + debug_resume_req_f <= _T_192 @[dec_tlu_ctl.scala 454:57] + reg _T_193 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 455:81] + _T_193 <= trigger_hit_dmode_r @[dec_tlu_ctl.scala 455:81] + trigger_hit_dmode_r_d1 <= _T_193 @[dec_tlu_ctl.scala 455:49] + reg _T_194 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 456:81] + _T_194 <= dcsr_single_step_done @[dec_tlu_ctl.scala 456:81] + dcsr_single_step_done_f <= _T_194 @[dec_tlu_ctl.scala 456:49] + reg _T_195 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 457:89] + _T_195 <= debug_halt_req @[dec_tlu_ctl.scala 457:89] + debug_halt_req_d1 <= _T_195 @[dec_tlu_ctl.scala 457:57] + reg dec_tlu_wr_pause_r_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 458:81] + dec_tlu_wr_pause_r_d1 <= io.dec_tlu_wr_pause_r @[dec_tlu_ctl.scala 458:81] + reg dec_pause_state_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 459:81] + dec_pause_state_f <= io.dec_pause_state @[dec_tlu_ctl.scala 459:81] + reg _T_196 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 460:81] + _T_196 <= request_debug_mode_r @[dec_tlu_ctl.scala 460:81] + request_debug_mode_r_d1 <= _T_196 @[dec_tlu_ctl.scala 460:49] + reg _T_197 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 461:73] + _T_197 <= request_debug_mode_done @[dec_tlu_ctl.scala 461:73] + request_debug_mode_done_f <= _T_197 @[dec_tlu_ctl.scala 461:41] + reg _T_198 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 462:73] + _T_198 <= dcsr_single_step_running @[dec_tlu_ctl.scala 462:73] + dcsr_single_step_running_f <= _T_198 @[dec_tlu_ctl.scala 462:41] + reg _T_199 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 463:73] + _T_199 <= io.dec_tlu_flush_pause_r @[dec_tlu_ctl.scala 463:73] + dec_tlu_flush_pause_r_d1 <= _T_199 @[dec_tlu_ctl.scala 463:41] + reg _T_200 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 464:81] + _T_200 <= dbg_halt_req_held_ns @[dec_tlu_ctl.scala 464:81] + dbg_halt_req_held <= _T_200 @[dec_tlu_ctl.scala 464:49] + io.dec_tlu_debug_stall <= debug_halt_req_f @[dec_tlu_ctl.scala 467:41] + io.dec_tlu_dbg_halted <= dbg_tlu_halted_f @[dec_tlu_ctl.scala 468:41] + io.dec_tlu_debug_mode <= debug_mode_status @[dec_tlu_ctl.scala 469:41] + dec_tlu_pmu_fw_halted <= pmu_fw_tlu_halted_f @[dec_tlu_ctl.scala 470:41] + node _T_201 = and(fence_i_r, internal_dbg_halt_mode) @[dec_tlu_ctl.scala 473:71] + node _T_202 = or(take_halt, _T_201) @[dec_tlu_ctl.scala 473:58] + node _T_203 = or(_T_202, io.dec_tlu_flush_pause_r) @[dec_tlu_ctl.scala 473:97] + node _T_204 = and(i0_trigger_hit_r, trigger_hit_dmode_r) @[dec_tlu_ctl.scala 473:144] + node _T_205 = or(_T_203, _T_204) @[dec_tlu_ctl.scala 473:124] + node _T_206 = or(_T_205, take_ext_int_start) @[dec_tlu_ctl.scala 473:167] + io.tlu_ifc.dec_tlu_flush_noredir_wb <= _T_206 @[dec_tlu_ctl.scala 473:45] + io.dec_tlu_flush_extint <= take_ext_int_start @[dec_tlu_ctl.scala 475:33] + node _T_207 = not(interrupt_valid_r) @[dec_tlu_ctl.scala 478:61] + node _T_208 = and(dec_tlu_wr_pause_r_d1, _T_207) @[dec_tlu_ctl.scala 478:59] + node _T_209 = not(take_ext_int_start) @[dec_tlu_ctl.scala 478:82] + node _T_210 = and(_T_208, _T_209) @[dec_tlu_ctl.scala 478:80] + io.dec_tlu_flush_pause_r <= _T_210 @[dec_tlu_ctl.scala 478:34] + node _T_211 = not(io.dec_pause_state) @[dec_tlu_ctl.scala 480:28] + node _T_212 = and(_T_211, dec_pause_state_f) @[dec_tlu_ctl.scala 480:48] + node _T_213 = or(ext_int_ready, ce_int_ready) @[dec_tlu_ctl.scala 480:86] + node _T_214 = or(_T_213, timer_int_ready) @[dec_tlu_ctl.scala 480:101] + node _T_215 = or(_T_214, soft_int_ready) @[dec_tlu_ctl.scala 480:119] + node _T_216 = or(_T_215, int_timer0_int_hold_f) @[dec_tlu_ctl.scala 480:136] + node _T_217 = or(_T_216, int_timer1_int_hold_f) @[dec_tlu_ctl.scala 480:160] + node _T_218 = or(_T_217, nmi_int_detected) @[dec_tlu_ctl.scala 480:184] + node _T_219 = or(_T_218, ext_int_freeze_d1) @[dec_tlu_ctl.scala 480:203] + node _T_220 = not(_T_219) @[dec_tlu_ctl.scala 480:70] + node _T_221 = and(_T_212, _T_220) @[dec_tlu_ctl.scala 480:68] + node _T_222 = not(interrupt_valid_r_d1) @[dec_tlu_ctl.scala 480:226] + node _T_223 = and(_T_221, _T_222) @[dec_tlu_ctl.scala 480:224] + node _T_224 = not(debug_halt_req_f) @[dec_tlu_ctl.scala 480:250] + node _T_225 = and(_T_223, _T_224) @[dec_tlu_ctl.scala 480:248] + node _T_226 = not(pmu_fw_halt_req_f) @[dec_tlu_ctl.scala 480:270] + node _T_227 = and(_T_225, _T_226) @[dec_tlu_ctl.scala 480:268] + node _T_228 = not(halt_taken_f) @[dec_tlu_ctl.scala 480:291] + node _T_229 = and(_T_227, _T_228) @[dec_tlu_ctl.scala 480:289] + pause_expired_r <= _T_229 @[dec_tlu_ctl.scala 480:25] + node _T_230 = bits(dcsr, 2, 2) @[dec_tlu_ctl.scala 482:88] + node _T_231 = and(io.tlu_exu.dec_tlu_flush_lower_r, _T_230) @[dec_tlu_ctl.scala 482:82] + node _T_232 = or(io.dec_tlu_resume_ack, dcsr_single_step_running) @[dec_tlu_ctl.scala 482:125] + node _T_233 = and(_T_231, _T_232) @[dec_tlu_ctl.scala 482:100] + node _T_234 = not(io.tlu_ifc.dec_tlu_flush_noredir_wb) @[dec_tlu_ctl.scala 482:155] + node _T_235 = and(_T_233, _T_234) @[dec_tlu_ctl.scala 482:153] + io.tlu_bp.dec_tlu_flush_leak_one_wb <= _T_235 @[dec_tlu_ctl.scala 482:45] + node _T_236 = or(ic_perr_r_d1, iccm_sbecc_r_d1) @[dec_tlu_ctl.scala 483:93] + node _T_237 = and(io.tlu_exu.dec_tlu_flush_lower_r, _T_236) @[dec_tlu_ctl.scala 483:77] + io.tlu_mem.dec_tlu_flush_err_wb <= _T_237 @[dec_tlu_ctl.scala 483:41] + io.dec_dbg_cmd_done <= dbg_cmd_done_ns @[dec_tlu_ctl.scala 486:29] + node _T_238 = and(illegal_r, io.dec_dbg_cmd_done) @[dec_tlu_ctl.scala 487:42] + io.dec_dbg_cmd_fail <= _T_238 @[dec_tlu_ctl.scala 487:29] + node _T_239 = bits(mtdata1_t[3], 2, 2) @[dec_tlu_ctl.scala 500:48] + node _T_240 = bits(mtdata1_t[2], 2, 2) @[dec_tlu_ctl.scala 500:75] + node _T_241 = bits(mtdata1_t[1], 2, 2) @[dec_tlu_ctl.scala 500:102] + node _T_242 = bits(mtdata1_t[0], 2, 2) @[dec_tlu_ctl.scala 500:129] node _T_243 = cat(_T_241, _T_242) @[Cat.scala 29:58] node _T_244 = cat(_T_239, _T_240) @[Cat.scala 29:58] node trigger_execute = cat(_T_244, _T_243) @[Cat.scala 29:58] - node _T_245 = bits(mtdata1_t[3], 7, 7) @[dec_tlu_ctl.scala 503:52] - node _T_246 = bits(mtdata1_t[2], 7, 7) @[dec_tlu_ctl.scala 503:79] - node _T_247 = bits(mtdata1_t[1], 7, 7) @[dec_tlu_ctl.scala 503:106] - node _T_248 = bits(mtdata1_t[0], 7, 7) @[dec_tlu_ctl.scala 503:133] + node _T_245 = bits(mtdata1_t[3], 7, 7) @[dec_tlu_ctl.scala 501:52] + node _T_246 = bits(mtdata1_t[2], 7, 7) @[dec_tlu_ctl.scala 501:79] + node _T_247 = bits(mtdata1_t[1], 7, 7) @[dec_tlu_ctl.scala 501:106] + node _T_248 = bits(mtdata1_t[0], 7, 7) @[dec_tlu_ctl.scala 501:133] node _T_249 = cat(_T_247, _T_248) @[Cat.scala 29:58] node _T_250 = cat(_T_245, _T_246) @[Cat.scala 29:58] node trigger_data = cat(_T_250, _T_249) @[Cat.scala 29:58] - node _T_251 = bits(mtdata1_t[3], 1, 1) @[dec_tlu_ctl.scala 504:52] - node _T_252 = bits(mtdata1_t[2], 1, 1) @[dec_tlu_ctl.scala 504:79] - node _T_253 = bits(mtdata1_t[1], 1, 1) @[dec_tlu_ctl.scala 504:106] - node _T_254 = bits(mtdata1_t[0], 1, 1) @[dec_tlu_ctl.scala 504:133] + node _T_251 = bits(mtdata1_t[3], 1, 1) @[dec_tlu_ctl.scala 502:52] + node _T_252 = bits(mtdata1_t[2], 1, 1) @[dec_tlu_ctl.scala 502:79] + node _T_253 = bits(mtdata1_t[1], 1, 1) @[dec_tlu_ctl.scala 502:106] + node _T_254 = bits(mtdata1_t[0], 1, 1) @[dec_tlu_ctl.scala 502:133] node _T_255 = cat(_T_253, _T_254) @[Cat.scala 29:58] node _T_256 = cat(_T_251, _T_252) @[Cat.scala 29:58] node trigger_store = cat(_T_256, _T_255) @[Cat.scala 29:58] - node _T_257 = bits(mtdata1_t[3], 6, 6) @[dec_tlu_ctl.scala 507:45] - node _T_258 = bits(mstatus, 0, 0) @[dec_tlu_ctl.scala 507:71] - node _T_259 = or(_T_257, _T_258) @[dec_tlu_ctl.scala 507:62] - node _T_260 = bits(mtdata1_t[3], 3, 3) @[dec_tlu_ctl.scala 507:100] - node _T_261 = and(_T_259, _T_260) @[dec_tlu_ctl.scala 507:86] - node _T_262 = bits(mtdata1_t[2], 6, 6) @[dec_tlu_ctl.scala 507:133] - node _T_263 = bits(mstatus, 0, 0) @[dec_tlu_ctl.scala 507:159] - node _T_264 = or(_T_262, _T_263) @[dec_tlu_ctl.scala 507:150] - node _T_265 = bits(mtdata1_t[2], 3, 3) @[dec_tlu_ctl.scala 507:188] - node _T_266 = and(_T_264, _T_265) @[dec_tlu_ctl.scala 507:174] - node _T_267 = bits(mtdata1_t[1], 6, 6) @[dec_tlu_ctl.scala 507:222] - node _T_268 = bits(mstatus, 0, 0) @[dec_tlu_ctl.scala 507:248] - node _T_269 = or(_T_267, _T_268) @[dec_tlu_ctl.scala 507:239] - node _T_270 = bits(mtdata1_t[1], 3, 3) @[dec_tlu_ctl.scala 507:277] - node _T_271 = and(_T_269, _T_270) @[dec_tlu_ctl.scala 507:263] - node _T_272 = bits(mtdata1_t[0], 6, 6) @[dec_tlu_ctl.scala 507:311] - node _T_273 = bits(mstatus, 0, 0) @[dec_tlu_ctl.scala 507:337] - node _T_274 = or(_T_272, _T_273) @[dec_tlu_ctl.scala 507:328] - node _T_275 = bits(mtdata1_t[0], 3, 3) @[dec_tlu_ctl.scala 507:366] - node _T_276 = and(_T_274, _T_275) @[dec_tlu_ctl.scala 507:352] + node _T_257 = bits(mtdata1_t[3], 6, 6) @[dec_tlu_ctl.scala 505:45] + node _T_258 = bits(mstatus, 0, 0) @[dec_tlu_ctl.scala 505:71] + node _T_259 = or(_T_257, _T_258) @[dec_tlu_ctl.scala 505:62] + node _T_260 = bits(mtdata1_t[3], 3, 3) @[dec_tlu_ctl.scala 505:100] + node _T_261 = and(_T_259, _T_260) @[dec_tlu_ctl.scala 505:86] + node _T_262 = bits(mtdata1_t[2], 6, 6) @[dec_tlu_ctl.scala 505:133] + node _T_263 = bits(mstatus, 0, 0) @[dec_tlu_ctl.scala 505:159] + node _T_264 = or(_T_262, _T_263) @[dec_tlu_ctl.scala 505:150] + node _T_265 = bits(mtdata1_t[2], 3, 3) @[dec_tlu_ctl.scala 505:188] + node _T_266 = and(_T_264, _T_265) @[dec_tlu_ctl.scala 505:174] + node _T_267 = bits(mtdata1_t[1], 6, 6) @[dec_tlu_ctl.scala 505:222] + node _T_268 = bits(mstatus, 0, 0) @[dec_tlu_ctl.scala 505:248] + node _T_269 = or(_T_267, _T_268) @[dec_tlu_ctl.scala 505:239] + node _T_270 = bits(mtdata1_t[1], 3, 3) @[dec_tlu_ctl.scala 505:277] + node _T_271 = and(_T_269, _T_270) @[dec_tlu_ctl.scala 505:263] + node _T_272 = bits(mtdata1_t[0], 6, 6) @[dec_tlu_ctl.scala 505:311] + node _T_273 = bits(mstatus, 0, 0) @[dec_tlu_ctl.scala 505:337] + node _T_274 = or(_T_272, _T_273) @[dec_tlu_ctl.scala 505:328] + node _T_275 = bits(mtdata1_t[0], 3, 3) @[dec_tlu_ctl.scala 505:366] + node _T_276 = and(_T_274, _T_275) @[dec_tlu_ctl.scala 505:352] node _T_277 = cat(_T_271, _T_276) @[Cat.scala 29:58] node _T_278 = cat(_T_261, _T_266) @[Cat.scala 29:58] node trigger_enabled = cat(_T_278, _T_277) @[Cat.scala 29:58] - node _T_279 = and(trigger_execute, trigger_data) @[dec_tlu_ctl.scala 510:57] + node _T_279 = and(trigger_execute, trigger_data) @[dec_tlu_ctl.scala 508:57] node _T_280 = bits(inst_acc_r_raw, 0, 0) @[Bitwise.scala 72:15] node _T_281 = mux(_T_280, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_282 = and(_T_279, _T_281) @[dec_tlu_ctl.scala 510:72] - node _T_283 = or(io.tlu_exu.exu_i0_br_error_r, io.tlu_exu.exu_i0_br_start_error_r) @[dec_tlu_ctl.scala 510:137] + node _T_282 = and(_T_279, _T_281) @[dec_tlu_ctl.scala 508:72] + node _T_283 = or(io.tlu_exu.exu_i0_br_error_r, io.tlu_exu.exu_i0_br_start_error_r) @[dec_tlu_ctl.scala 508:137] node _T_284 = bits(_T_283, 0, 0) @[Bitwise.scala 72:15] node _T_285 = mux(_T_284, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_286 = or(_T_282, _T_285) @[dec_tlu_ctl.scala 510:98] - node i0_iside_trigger_has_pri_r = not(_T_286) @[dec_tlu_ctl.scala 510:38] - node _T_287 = and(trigger_store, trigger_data) @[dec_tlu_ctl.scala 513:51] + node _T_286 = or(_T_282, _T_285) @[dec_tlu_ctl.scala 508:98] + node i0_iside_trigger_has_pri_r = not(_T_286) @[dec_tlu_ctl.scala 508:38] + node _T_287 = and(trigger_store, trigger_data) @[dec_tlu_ctl.scala 511:51] node _T_288 = bits(lsu_i0_exc_r_raw, 0, 0) @[Bitwise.scala 72:15] node _T_289 = mux(_T_288, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_290 = and(_T_287, _T_289) @[dec_tlu_ctl.scala 513:66] - node i0_lsu_trigger_has_pri_r = not(_T_290) @[dec_tlu_ctl.scala 513:35] + node _T_290 = and(_T_287, _T_289) @[dec_tlu_ctl.scala 511:66] + node i0_lsu_trigger_has_pri_r = not(_T_290) @[dec_tlu_ctl.scala 511:35] node _T_291 = bits(io.dec_tlu_i0_valid_r, 0, 0) @[Bitwise.scala 72:15] node _T_292 = mux(_T_291, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_293 = bits(io.dec_tlu_packet_r.i0trigger, 3, 0) @[dec_tlu_ctl.scala 518:84] - node _T_294 = and(_T_292, _T_293) @[dec_tlu_ctl.scala 518:53] - node _T_295 = and(_T_294, i0_iside_trigger_has_pri_r) @[dec_tlu_ctl.scala 518:90] - node _T_296 = and(_T_295, i0_lsu_trigger_has_pri_r) @[dec_tlu_ctl.scala 518:119] - node i0trigger_qual_r = and(_T_296, trigger_enabled) @[dec_tlu_ctl.scala 518:146] - node _T_297 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 520:58] + node _T_293 = bits(io.dec_tlu_packet_r.i0trigger, 3, 0) @[dec_tlu_ctl.scala 516:84] + node _T_294 = and(_T_292, _T_293) @[dec_tlu_ctl.scala 516:53] + node _T_295 = and(_T_294, i0_iside_trigger_has_pri_r) @[dec_tlu_ctl.scala 516:90] + node _T_296 = and(_T_295, i0_lsu_trigger_has_pri_r) @[dec_tlu_ctl.scala 516:119] + node i0trigger_qual_r = and(_T_296, trigger_enabled) @[dec_tlu_ctl.scala 516:146] + node _T_297 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 518:58] node _T_298 = bits(_T_297, 0, 0) @[Bitwise.scala 72:15] node _T_299 = mux(_T_298, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_300 = not(_T_299) @[dec_tlu_ctl.scala 520:23] - node i0_trigger_r = and(_T_300, i0trigger_qual_r) @[dec_tlu_ctl.scala 520:84] - node _T_301 = bits(i0_trigger_r, 3, 3) @[dec_tlu_ctl.scala 523:53] - node _T_302 = bits(mtdata1_t[2], 5, 5) @[dec_tlu_ctl.scala 523:73] - node _T_303 = not(_T_302) @[dec_tlu_ctl.scala 523:60] - node _T_304 = bits(i0_trigger_r, 2, 2) @[dec_tlu_ctl.scala 523:103] - node _T_305 = or(_T_303, _T_304) @[dec_tlu_ctl.scala 523:89] - node _T_306 = and(_T_301, _T_305) @[dec_tlu_ctl.scala 523:57] - node _T_307 = bits(i0_trigger_r, 2, 2) @[dec_tlu_ctl.scala 523:121] - node _T_308 = bits(mtdata1_t[2], 5, 5) @[dec_tlu_ctl.scala 523:141] - node _T_309 = not(_T_308) @[dec_tlu_ctl.scala 523:128] - node _T_310 = bits(i0_trigger_r, 3, 3) @[dec_tlu_ctl.scala 523:171] - node _T_311 = or(_T_309, _T_310) @[dec_tlu_ctl.scala 523:157] - node _T_312 = and(_T_307, _T_311) @[dec_tlu_ctl.scala 523:125] - node _T_313 = bits(i0_trigger_r, 1, 1) @[dec_tlu_ctl.scala 523:189] - node _T_314 = bits(mtdata1_t[0], 5, 5) @[dec_tlu_ctl.scala 523:209] - node _T_315 = not(_T_314) @[dec_tlu_ctl.scala 523:196] - node _T_316 = bits(i0_trigger_r, 0, 0) @[dec_tlu_ctl.scala 523:239] - node _T_317 = or(_T_315, _T_316) @[dec_tlu_ctl.scala 523:225] - node _T_318 = and(_T_313, _T_317) @[dec_tlu_ctl.scala 523:193] - node _T_319 = bits(i0_trigger_r, 0, 0) @[dec_tlu_ctl.scala 523:257] - node _T_320 = bits(mtdata1_t[0], 5, 5) @[dec_tlu_ctl.scala 523:277] - node _T_321 = not(_T_320) @[dec_tlu_ctl.scala 523:264] - node _T_322 = bits(i0_trigger_r, 1, 1) @[dec_tlu_ctl.scala 523:307] - node _T_323 = or(_T_321, _T_322) @[dec_tlu_ctl.scala 523:293] - node _T_324 = and(_T_319, _T_323) @[dec_tlu_ctl.scala 523:261] + node _T_300 = not(_T_299) @[dec_tlu_ctl.scala 518:23] + node i0_trigger_r = and(_T_300, i0trigger_qual_r) @[dec_tlu_ctl.scala 518:84] + node _T_301 = bits(i0_trigger_r, 3, 3) @[dec_tlu_ctl.scala 521:53] + node _T_302 = bits(mtdata1_t[2], 5, 5) @[dec_tlu_ctl.scala 521:73] + node _T_303 = not(_T_302) @[dec_tlu_ctl.scala 521:60] + node _T_304 = bits(i0_trigger_r, 2, 2) @[dec_tlu_ctl.scala 521:103] + node _T_305 = or(_T_303, _T_304) @[dec_tlu_ctl.scala 521:89] + node _T_306 = and(_T_301, _T_305) @[dec_tlu_ctl.scala 521:57] + node _T_307 = bits(i0_trigger_r, 2, 2) @[dec_tlu_ctl.scala 521:121] + node _T_308 = bits(mtdata1_t[2], 5, 5) @[dec_tlu_ctl.scala 521:141] + node _T_309 = not(_T_308) @[dec_tlu_ctl.scala 521:128] + node _T_310 = bits(i0_trigger_r, 3, 3) @[dec_tlu_ctl.scala 521:171] + node _T_311 = or(_T_309, _T_310) @[dec_tlu_ctl.scala 521:157] + node _T_312 = and(_T_307, _T_311) @[dec_tlu_ctl.scala 521:125] + node _T_313 = bits(i0_trigger_r, 1, 1) @[dec_tlu_ctl.scala 521:189] + node _T_314 = bits(mtdata1_t[0], 5, 5) @[dec_tlu_ctl.scala 521:209] + node _T_315 = not(_T_314) @[dec_tlu_ctl.scala 521:196] + node _T_316 = bits(i0_trigger_r, 0, 0) @[dec_tlu_ctl.scala 521:239] + node _T_317 = or(_T_315, _T_316) @[dec_tlu_ctl.scala 521:225] + node _T_318 = and(_T_313, _T_317) @[dec_tlu_ctl.scala 521:193] + node _T_319 = bits(i0_trigger_r, 0, 0) @[dec_tlu_ctl.scala 521:257] + node _T_320 = bits(mtdata1_t[0], 5, 5) @[dec_tlu_ctl.scala 521:277] + node _T_321 = not(_T_320) @[dec_tlu_ctl.scala 521:264] + node _T_322 = bits(i0_trigger_r, 1, 1) @[dec_tlu_ctl.scala 521:307] + node _T_323 = or(_T_321, _T_322) @[dec_tlu_ctl.scala 521:293] + node _T_324 = and(_T_319, _T_323) @[dec_tlu_ctl.scala 521:261] node _T_325 = cat(_T_318, _T_324) @[Cat.scala 29:58] node _T_326 = cat(_T_306, _T_312) @[Cat.scala 29:58] node i0_trigger_chain_masked_r = cat(_T_326, _T_325) @[Cat.scala 29:58] - node i0_trigger_hit_raw_r = orr(i0_trigger_chain_masked_r) @[dec_tlu_ctl.scala 526:57] - i0_trigger_hit_r <= i0_trigger_hit_raw_r @[dec_tlu_ctl.scala 528:25] - node _T_327 = bits(mtdata1_t[3], 6, 6) @[dec_tlu_ctl.scala 532:44] - node _T_328 = bits(mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 532:75] - node _T_329 = and(_T_327, _T_328) @[dec_tlu_ctl.scala 532:61] - node _T_330 = bits(mtdata1_t[2], 6, 6) @[dec_tlu_ctl.scala 532:104] - node _T_331 = bits(mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 532:135] - node _T_332 = and(_T_330, _T_331) @[dec_tlu_ctl.scala 532:121] - node _T_333 = bits(mtdata1_t[1], 6, 6) @[dec_tlu_ctl.scala 532:164] - node _T_334 = bits(mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 532:195] - node _T_335 = and(_T_333, _T_334) @[dec_tlu_ctl.scala 532:181] - node _T_336 = bits(mtdata1_t[0], 6, 6) @[dec_tlu_ctl.scala 532:224] - node _T_337 = bits(mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 532:255] - node _T_338 = and(_T_336, _T_337) @[dec_tlu_ctl.scala 532:241] + node i0_trigger_hit_raw_r = orr(i0_trigger_chain_masked_r) @[dec_tlu_ctl.scala 524:57] + i0_trigger_hit_r <= i0_trigger_hit_raw_r @[dec_tlu_ctl.scala 526:25] + node _T_327 = bits(mtdata1_t[3], 6, 6) @[dec_tlu_ctl.scala 530:44] + node _T_328 = bits(mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 530:75] + node _T_329 = and(_T_327, _T_328) @[dec_tlu_ctl.scala 530:61] + node _T_330 = bits(mtdata1_t[2], 6, 6) @[dec_tlu_ctl.scala 530:104] + node _T_331 = bits(mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 530:135] + node _T_332 = and(_T_330, _T_331) @[dec_tlu_ctl.scala 530:121] + node _T_333 = bits(mtdata1_t[1], 6, 6) @[dec_tlu_ctl.scala 530:164] + node _T_334 = bits(mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 530:195] + node _T_335 = and(_T_333, _T_334) @[dec_tlu_ctl.scala 530:181] + node _T_336 = bits(mtdata1_t[0], 6, 6) @[dec_tlu_ctl.scala 530:224] + node _T_337 = bits(mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 530:255] + node _T_338 = and(_T_336, _T_337) @[dec_tlu_ctl.scala 530:241] node _T_339 = cat(_T_335, _T_338) @[Cat.scala 29:58] node _T_340 = cat(_T_329, _T_332) @[Cat.scala 29:58] node trigger_action = cat(_T_340, _T_339) @[Cat.scala 29:58] node _T_341 = bits(i0_trigger_hit_r, 0, 0) @[Bitwise.scala 72:15] node _T_342 = mux(_T_341, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node update_hit_bit_r = and(_T_342, i0_trigger_chain_masked_r) @[dec_tlu_ctl.scala 535:56] - node _T_343 = and(i0_trigger_chain_masked_r, trigger_action) @[dec_tlu_ctl.scala 538:57] - node i0_trigger_action_r = orr(_T_343) @[dec_tlu_ctl.scala 538:75] - node _T_344 = and(i0_trigger_hit_r, i0_trigger_action_r) @[dec_tlu_ctl.scala 540:45] - trigger_hit_dmode_r <= _T_344 @[dec_tlu_ctl.scala 540:24] - node _T_345 = not(trigger_hit_dmode_r) @[dec_tlu_ctl.scala 542:55] - node mepc_trigger_hit_sel_pc_r = and(i0_trigger_hit_r, _T_345) @[dec_tlu_ctl.scala 542:53] - node _T_346 = not(io.dec_tlu_debug_mode) @[dec_tlu_ctl.scala 569:62] - node _T_347 = and(i_cpu_halt_req_sync, _T_346) @[dec_tlu_ctl.scala 569:60] - node _T_348 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 569:87] - node i_cpu_halt_req_sync_qual = and(_T_347, _T_348) @[dec_tlu_ctl.scala 569:85] - node _T_349 = not(io.dec_tlu_debug_mode) @[dec_tlu_ctl.scala 570:60] - node _T_350 = and(i_cpu_run_req_sync, _T_349) @[dec_tlu_ctl.scala 570:58] - node _T_351 = and(_T_350, pmu_fw_tlu_halted_f) @[dec_tlu_ctl.scala 570:83] - node _T_352 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 570:107] - node i_cpu_run_req_sync_qual = and(_T_351, _T_352) @[dec_tlu_ctl.scala 570:105] - reg i_cpu_halt_req_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 572:80] - i_cpu_halt_req_d1 <= i_cpu_halt_req_sync_qual @[dec_tlu_ctl.scala 572:80] - reg i_cpu_run_req_d1_raw : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 573:80] - i_cpu_run_req_d1_raw <= i_cpu_run_req_sync_qual @[dec_tlu_ctl.scala 573:80] - reg _T_353 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 574:81] - _T_353 <= cpu_halt_status @[dec_tlu_ctl.scala 574:81] - io.o_cpu_halt_status <= _T_353 @[dec_tlu_ctl.scala 574:49] - reg _T_354 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 575:81] - _T_354 <= cpu_halt_ack @[dec_tlu_ctl.scala 575:81] - io.o_cpu_halt_ack <= _T_354 @[dec_tlu_ctl.scala 575:49] - reg _T_355 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 576:81] - _T_355 <= cpu_run_ack @[dec_tlu_ctl.scala 576:81] - io.o_cpu_run_ack <= _T_355 @[dec_tlu_ctl.scala 576:49] - reg internal_pmu_fw_halt_mode_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 577:68] - internal_pmu_fw_halt_mode_f <= internal_pmu_fw_halt_mode @[dec_tlu_ctl.scala 577:68] - reg _T_356 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 578:73] - _T_356 <= pmu_fw_halt_req_ns @[dec_tlu_ctl.scala 578:73] - pmu_fw_halt_req_f <= _T_356 @[dec_tlu_ctl.scala 578:41] - reg _T_357 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 579:73] - _T_357 <= pmu_fw_tlu_halted @[dec_tlu_ctl.scala 579:73] - pmu_fw_tlu_halted_f <= _T_357 @[dec_tlu_ctl.scala 579:41] - reg _T_358 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 580:73] - _T_358 <= int_timer0_int_hold @[dec_tlu_ctl.scala 580:73] - int_timer0_int_hold_f <= _T_358 @[dec_tlu_ctl.scala 580:41] - reg _T_359 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 581:73] - _T_359 <= int_timer1_int_hold @[dec_tlu_ctl.scala 581:73] - int_timer1_int_hold_f <= _T_359 @[dec_tlu_ctl.scala 581:41] - node _T_360 = not(i_cpu_halt_req_d1) @[dec_tlu_ctl.scala 585:52] - node ext_halt_pulse = and(i_cpu_halt_req_sync_qual, _T_360) @[dec_tlu_ctl.scala 585:50] - node enter_pmu_fw_halt_req = or(ext_halt_pulse, fw_halt_req) @[dec_tlu_ctl.scala 586:48] - node _T_361 = not(pmu_fw_tlu_halted) @[dec_tlu_ctl.scala 587:72] - node _T_362 = and(pmu_fw_halt_req_f, _T_361) @[dec_tlu_ctl.scala 587:70] - node _T_363 = or(enter_pmu_fw_halt_req, _T_362) @[dec_tlu_ctl.scala 587:49] - node _T_364 = not(debug_halt_req_f) @[dec_tlu_ctl.scala 587:95] - node _T_365 = and(_T_363, _T_364) @[dec_tlu_ctl.scala 587:93] - pmu_fw_halt_req_ns <= _T_365 @[dec_tlu_ctl.scala 587:23] - node _T_366 = not(i_cpu_run_req_d1) @[dec_tlu_ctl.scala 588:85] - node _T_367 = and(internal_pmu_fw_halt_mode_f, _T_366) @[dec_tlu_ctl.scala 588:83] - node _T_368 = not(debug_halt_req_f) @[dec_tlu_ctl.scala 588:105] - node _T_369 = and(_T_367, _T_368) @[dec_tlu_ctl.scala 588:103] - node _T_370 = or(pmu_fw_halt_req_ns, _T_369) @[dec_tlu_ctl.scala 588:52] - internal_pmu_fw_halt_mode <= _T_370 @[dec_tlu_ctl.scala 588:30] - node _T_371 = and(pmu_fw_halt_req_f, core_empty) @[dec_tlu_ctl.scala 591:45] - node _T_372 = and(_T_371, halt_taken) @[dec_tlu_ctl.scala 591:58] - node _T_373 = not(enter_debug_halt_req) @[dec_tlu_ctl.scala 591:73] - node _T_374 = and(_T_372, _T_373) @[dec_tlu_ctl.scala 591:71] - node _T_375 = not(i_cpu_run_req_d1) @[dec_tlu_ctl.scala 591:121] - node _T_376 = and(pmu_fw_tlu_halted_f, _T_375) @[dec_tlu_ctl.scala 591:119] - node _T_377 = or(_T_374, _T_376) @[dec_tlu_ctl.scala 591:96] - node _T_378 = not(debug_halt_req_f) @[dec_tlu_ctl.scala 591:143] - node _T_379 = and(_T_377, _T_378) @[dec_tlu_ctl.scala 591:141] - pmu_fw_tlu_halted <= _T_379 @[dec_tlu_ctl.scala 591:22] - node _T_380 = and(i_cpu_halt_req_d1, pmu_fw_tlu_halted_f) @[dec_tlu_ctl.scala 593:38] - cpu_halt_ack <= _T_380 @[dec_tlu_ctl.scala 593:17] - node _T_381 = not(i_cpu_run_req_d1) @[dec_tlu_ctl.scala 594:46] - node _T_382 = and(pmu_fw_tlu_halted_f, _T_381) @[dec_tlu_ctl.scala 594:44] - node _T_383 = not(i_cpu_run_req_d1) @[dec_tlu_ctl.scala 594:91] - node _T_384 = and(io.o_cpu_halt_status, _T_383) @[dec_tlu_ctl.scala 594:89] - node _T_385 = not(debug_mode_status) @[dec_tlu_ctl.scala 594:111] - node _T_386 = and(_T_384, _T_385) @[dec_tlu_ctl.scala 594:109] - node _T_387 = or(_T_382, _T_386) @[dec_tlu_ctl.scala 594:65] - cpu_halt_status <= _T_387 @[dec_tlu_ctl.scala 594:20] - node _T_388 = and(io.o_cpu_halt_status, i_cpu_run_req_sync_qual) @[dec_tlu_ctl.scala 595:41] - node _T_389 = and(io.o_cpu_run_ack, i_cpu_run_req_sync_qual) @[dec_tlu_ctl.scala 595:88] - node _T_390 = or(_T_388, _T_389) @[dec_tlu_ctl.scala 595:68] - cpu_run_ack <= _T_390 @[dec_tlu_ctl.scala 595:16] - io.o_debug_mode_status <= debug_mode_status @[dec_tlu_ctl.scala 597:27] - node _T_391 = or(nmi_int_detected, timer_int_ready) @[dec_tlu_ctl.scala 600:66] - node _T_392 = or(_T_391, soft_int_ready) @[dec_tlu_ctl.scala 600:84] - node _T_393 = or(_T_392, int_timer0_int_hold_f) @[dec_tlu_ctl.scala 600:101] - node _T_394 = or(_T_393, int_timer1_int_hold_f) @[dec_tlu_ctl.scala 600:125] - node _T_395 = and(io.dec_pic.mhwakeup, mhwakeup_ready) @[dec_tlu_ctl.scala 600:172] - node _T_396 = or(_T_394, _T_395) @[dec_tlu_ctl.scala 600:149] - node _T_397 = and(_T_396, io.o_cpu_halt_status) @[dec_tlu_ctl.scala 600:191] - node _T_398 = not(i_cpu_halt_req_d1) @[dec_tlu_ctl.scala 600:216] - node _T_399 = and(_T_397, _T_398) @[dec_tlu_ctl.scala 600:214] - node _T_400 = or(i_cpu_run_req_d1_raw, _T_399) @[dec_tlu_ctl.scala 600:45] - i_cpu_run_req_d1 <= _T_400 @[dec_tlu_ctl.scala 600:21] - reg _T_401 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 606:89] - _T_401 <= mdseac_locked_ns @[dec_tlu_ctl.scala 606:89] - mdseac_locked_f <= _T_401 @[dec_tlu_ctl.scala 606:57] - reg lsu_single_ecc_error_r_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 607:72] - lsu_single_ecc_error_r_d1 <= io.lsu_single_ecc_error_incr @[dec_tlu_ctl.scala 607:72] - node _T_402 = not(io.dec_tlu_flush_lower_wb) @[dec_tlu_ctl.scala 609:57] - node lsu_exc_valid_r_raw = and(io.lsu_error_pkt_r.valid, _T_402) @[dec_tlu_ctl.scala 609:55] - lsu_i0_exc_r_raw <= io.lsu_error_pkt_r.valid @[dec_tlu_ctl.scala 610:21] - node _T_403 = and(lsu_i0_exc_r_raw, lsu_exc_valid_r_raw) @[dec_tlu_ctl.scala 611:40] - node _T_404 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 611:64] - node _T_405 = and(_T_403, _T_404) @[dec_tlu_ctl.scala 611:62] - node _T_406 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 611:84] - node lsu_exc_valid_r = and(_T_405, _T_406) @[dec_tlu_ctl.scala 611:82] - reg _T_407 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 613:74] - _T_407 <= lsu_exc_valid_r @[dec_tlu_ctl.scala 613:74] - lsu_exc_valid_r_d1 <= _T_407 @[dec_tlu_ctl.scala 613:41] - reg lsu_i0_exc_r_d1 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 614:73] - lsu_i0_exc_r_d1 <= lsu_exc_valid_r @[dec_tlu_ctl.scala 614:73] - node _T_408 = not(io.lsu_error_pkt_r.bits.exc_type) @[dec_tlu_ctl.scala 615:40] - node lsu_exc_ma_r = and(lsu_exc_valid_r, _T_408) @[dec_tlu_ctl.scala 615:38] - node lsu_exc_acc_r = and(lsu_exc_valid_r, io.lsu_error_pkt_r.bits.exc_type) @[dec_tlu_ctl.scala 616:38] - node lsu_exc_st_r = and(lsu_exc_valid_r, io.lsu_error_pkt_r.bits.inst_type) @[dec_tlu_ctl.scala 617:38] - node _T_409 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 621:49] - node _T_410 = and(io.dec_tlu_i0_valid_r, _T_409) @[dec_tlu_ctl.scala 621:47] - node _T_411 = not(io.lsu_error_pkt_r.bits.inst_type) @[dec_tlu_ctl.scala 621:70] - node _T_412 = and(_T_411, io.lsu_error_pkt_r.bits.single_ecc_error) @[dec_tlu_ctl.scala 621:105] - node lsu_i0_rfnpc_r = and(_T_410, _T_412) @[dec_tlu_ctl.scala 621:67] - node _T_413 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 624:52] - node _T_414 = and(io.dec_tlu_i0_valid_r, _T_413) @[dec_tlu_ctl.scala 624:50] - node _T_415 = not(lsu_exc_valid_r) @[dec_tlu_ctl.scala 624:65] - node _T_416 = and(_T_414, _T_415) @[dec_tlu_ctl.scala 624:63] - node _T_417 = not(inst_acc_r) @[dec_tlu_ctl.scala 624:82] - node _T_418 = and(_T_416, _T_417) @[dec_tlu_ctl.scala 624:79] - node _T_419 = not(io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 624:96] - node _T_420 = and(_T_418, _T_419) @[dec_tlu_ctl.scala 624:94] - node _T_421 = not(request_debug_mode_r_d1) @[dec_tlu_ctl.scala 624:121] - node _T_422 = and(_T_420, _T_421) @[dec_tlu_ctl.scala 624:119] - node _T_423 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 624:148] - node tlu_i0_commit_cmt = and(_T_422, _T_423) @[dec_tlu_ctl.scala 624:146] - node _T_424 = or(rfpc_i0_r, lsu_exc_valid_r) @[dec_tlu_ctl.scala 627:38] - node _T_425 = or(_T_424, inst_acc_r) @[dec_tlu_ctl.scala 627:53] - node _T_426 = and(illegal_r, io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 627:79] - node _T_427 = or(_T_425, _T_426) @[dec_tlu_ctl.scala 627:66] - node _T_428 = or(_T_427, i0_trigger_hit_r) @[dec_tlu_ctl.scala 627:104] - tlu_i0_kill_writeb_r <= _T_428 @[dec_tlu_ctl.scala 627:25] - io.tlu_mem.dec_tlu_i0_commit_cmt <= tlu_i0_commit_cmt @[dec_tlu_ctl.scala 628:37] - node _T_429 = not(tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 633:44] - node _T_430 = and(io.dec_tlu_i0_valid_r, _T_429) @[dec_tlu_ctl.scala 633:42] - node _T_431 = or(io.tlu_exu.exu_i0_br_error_r, io.tlu_exu.exu_i0_br_start_error_r) @[dec_tlu_ctl.scala 633:98] - node _T_432 = and(_T_430, _T_431) @[dec_tlu_ctl.scala 633:66] - node _T_433 = or(ic_perr_r_d1, iccm_sbecc_r_d1) @[dec_tlu_ctl.scala 633:154] - node _T_434 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 633:175] - node _T_435 = and(_T_433, _T_434) @[dec_tlu_ctl.scala 633:173] - node _T_436 = or(_T_432, _T_435) @[dec_tlu_ctl.scala 633:137] - node _T_437 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 633:199] - node _T_438 = and(_T_436, _T_437) @[dec_tlu_ctl.scala 633:196] - node _T_439 = not(lsu_i0_rfnpc_r) @[dec_tlu_ctl.scala 633:220] - node _T_440 = and(_T_438, _T_439) @[dec_tlu_ctl.scala 633:217] - rfpc_i0_r <= _T_440 @[dec_tlu_ctl.scala 633:14] - node _T_441 = not(io.tlu_exu.dec_tlu_flush_lower_r) @[dec_tlu_ctl.scala 636:70] - node _T_442 = and(iccm_repair_state_d1, _T_441) @[dec_tlu_ctl.scala 636:68] - node _T_443 = or(iccm_sbecc_r_d1, _T_442) @[dec_tlu_ctl.scala 636:44] - iccm_repair_state_ns <= _T_443 @[dec_tlu_ctl.scala 636:25] - node _T_444 = and(tlu_i0_commit_cmt, iccm_repair_state_d1) @[dec_tlu_ctl.scala 642:52] - node _T_445 = or(ebreak_r, ecall_r) @[dec_tlu_ctl.scala 642:88] - node _T_446 = or(_T_445, mret_r) @[dec_tlu_ctl.scala 642:98] - node _T_447 = or(_T_446, take_reset) @[dec_tlu_ctl.scala 642:107] - node _T_448 = or(_T_447, illegal_r) @[dec_tlu_ctl.scala 642:120] - node _T_449 = eq(io.dec_csr_wraddr_r, UInt<12>("h07c2")) @[dec_tlu_ctl.scala 642:176] - node _T_450 = and(dec_csr_wen_r_mod, _T_449) @[dec_tlu_ctl.scala 642:153] - node _T_451 = or(_T_448, _T_450) @[dec_tlu_ctl.scala 642:132] - node _T_452 = not(_T_451) @[dec_tlu_ctl.scala 642:77] - node iccm_repair_state_rfnpc = and(_T_444, _T_452) @[dec_tlu_ctl.scala 642:75] - node _T_453 = and(io.tlu_exu.exu_i0_br_error_r, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 645:59] - node _T_454 = not(tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 645:85] - node dec_tlu_br0_error_r = and(_T_453, _T_454) @[dec_tlu_ctl.scala 645:83] - node _T_455 = and(io.tlu_exu.exu_i0_br_start_error_r, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 646:71] - node _T_456 = not(tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 646:97] - node dec_tlu_br0_start_error_r = and(_T_455, _T_456) @[dec_tlu_ctl.scala 646:95] - node _T_457 = and(io.tlu_exu.exu_i0_br_valid_r, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 647:55] - node _T_458 = not(tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 647:81] - node _T_459 = and(_T_457, _T_458) @[dec_tlu_ctl.scala 647:79] - node _T_460 = not(io.tlu_exu.exu_i0_br_mp_r) @[dec_tlu_ctl.scala 647:106] - node _T_461 = not(io.tlu_exu.exu_pmu_i0_br_ataken) @[dec_tlu_ctl.scala 647:135] - node _T_462 = or(_T_460, _T_461) @[dec_tlu_ctl.scala 647:133] - node dec_tlu_br0_v_r = and(_T_459, _T_462) @[dec_tlu_ctl.scala 647:103] - io.tlu_bp.dec_tlu_br0_r_pkt.bits.hist <= io.tlu_exu.exu_i0_br_hist_r @[dec_tlu_ctl.scala 650:65] - io.tlu_bp.dec_tlu_br0_r_pkt.bits.br_error <= dec_tlu_br0_error_r @[dec_tlu_ctl.scala 651:57] - io.tlu_bp.dec_tlu_br0_r_pkt.bits.br_start_error <= dec_tlu_br0_start_error_r @[dec_tlu_ctl.scala 652:57] - io.tlu_bp.dec_tlu_br0_r_pkt.valid <= dec_tlu_br0_v_r @[dec_tlu_ctl.scala 653:57] - io.tlu_bp.dec_tlu_br0_r_pkt.bits.way <= io.exu_i0_br_way_r @[dec_tlu_ctl.scala 654:65] - io.tlu_bp.dec_tlu_br0_r_pkt.bits.middle <= io.tlu_exu.exu_i0_br_middle_r @[dec_tlu_ctl.scala 655:65] - node _T_463 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h08")) @[dec_tlu_ctl.scala 658:51] - node _T_464 = and(_T_463, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 658:64] - node _T_465 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 658:90] - node _T_466 = and(_T_464, _T_465) @[dec_tlu_ctl.scala 658:88] - node _T_467 = bits(dcsr, 15, 15) @[dec_tlu_ctl.scala 658:115] - node _T_468 = not(_T_467) @[dec_tlu_ctl.scala 658:110] - node _T_469 = and(_T_466, _T_468) @[dec_tlu_ctl.scala 658:108] - node _T_470 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 658:132] - node _T_471 = and(_T_469, _T_470) @[dec_tlu_ctl.scala 658:130] - ebreak_r <= _T_471 @[dec_tlu_ctl.scala 658:13] - node _T_472 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h09")) @[dec_tlu_ctl.scala 659:51] - node _T_473 = and(_T_472, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 659:64] - node _T_474 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 659:90] - node _T_475 = and(_T_473, _T_474) @[dec_tlu_ctl.scala 659:88] - node _T_476 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 659:110] - node _T_477 = and(_T_475, _T_476) @[dec_tlu_ctl.scala 659:108] - ecall_r <= _T_477 @[dec_tlu_ctl.scala 659:13] - node _T_478 = not(io.dec_tlu_packet_r.legal) @[dec_tlu_ctl.scala 660:17] - node _T_479 = and(_T_478, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 660:46] - node _T_480 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 660:72] - node _T_481 = and(_T_479, _T_480) @[dec_tlu_ctl.scala 660:70] - node _T_482 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 660:92] - node _T_483 = and(_T_481, _T_482) @[dec_tlu_ctl.scala 660:90] - illegal_r <= _T_483 @[dec_tlu_ctl.scala 660:13] - node _T_484 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h0c")) @[dec_tlu_ctl.scala 661:51] - node _T_485 = and(_T_484, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 661:64] - node _T_486 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 661:90] - node _T_487 = and(_T_485, _T_486) @[dec_tlu_ctl.scala 661:88] - node _T_488 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 661:110] - node _T_489 = and(_T_487, _T_488) @[dec_tlu_ctl.scala 661:108] - mret_r <= _T_489 @[dec_tlu_ctl.scala 661:13] - node _T_490 = and(io.dec_tlu_packet_r.fence_i, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 663:50] - node _T_491 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 663:76] - node _T_492 = and(_T_490, _T_491) @[dec_tlu_ctl.scala 663:74] - node _T_493 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 663:97] - node _T_494 = and(_T_492, _T_493) @[dec_tlu_ctl.scala 663:95] - fence_i_r <= _T_494 @[dec_tlu_ctl.scala 663:17] - node _T_495 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 664:53] - node _T_496 = and(io.tlu_mem.ifu_ic_error_start, _T_495) @[dec_tlu_ctl.scala 664:51] - node _T_497 = not(debug_mode_status) @[dec_tlu_ctl.scala 664:75] - node _T_498 = or(_T_497, dcsr_single_step_running) @[dec_tlu_ctl.scala 664:101] - node _T_499 = and(_T_496, _T_498) @[dec_tlu_ctl.scala 664:72] - node _T_500 = not(internal_pmu_fw_halt_mode_f) @[dec_tlu_ctl.scala 664:131] - node _T_501 = and(_T_499, _T_500) @[dec_tlu_ctl.scala 664:129] - ic_perr_r <= _T_501 @[dec_tlu_ctl.scala 664:17] - node _T_502 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 665:61] - node _T_503 = and(io.tlu_mem.ifu_iccm_rd_ecc_single_err, _T_502) @[dec_tlu_ctl.scala 665:59] - node _T_504 = not(debug_mode_status) @[dec_tlu_ctl.scala 665:83] - node _T_505 = or(_T_504, dcsr_single_step_running) @[dec_tlu_ctl.scala 665:109] - node _T_506 = and(_T_503, _T_505) @[dec_tlu_ctl.scala 665:80] - node _T_507 = not(internal_pmu_fw_halt_mode_f) @[dec_tlu_ctl.scala 665:139] - node _T_508 = and(_T_506, _T_507) @[dec_tlu_ctl.scala 665:137] - iccm_sbecc_r <= _T_508 @[dec_tlu_ctl.scala 665:17] - node _T_509 = and(io.dec_tlu_packet_r.icaf, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 666:49] - inst_acc_r_raw <= _T_509 @[dec_tlu_ctl.scala 666:20] - node _T_510 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 667:35] - node _T_511 = and(inst_acc_r_raw, _T_510) @[dec_tlu_ctl.scala 667:33] - node _T_512 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 667:48] - node _T_513 = and(_T_511, _T_512) @[dec_tlu_ctl.scala 667:46] - inst_acc_r <= _T_513 @[dec_tlu_ctl.scala 667:15] - node _T_514 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h08")) @[dec_tlu_ctl.scala 670:64] - node _T_515 = and(_T_514, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 670:77] - node _T_516 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 670:103] - node _T_517 = and(_T_515, _T_516) @[dec_tlu_ctl.scala 670:101] - node _T_518 = bits(dcsr, 15, 15) @[dec_tlu_ctl.scala 670:127] - node _T_519 = and(_T_517, _T_518) @[dec_tlu_ctl.scala 670:121] - node _T_520 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 670:144] - node _T_521 = and(_T_519, _T_520) @[dec_tlu_ctl.scala 670:142] - ebreak_to_debug_mode_r <= _T_521 @[dec_tlu_ctl.scala 670:27] - reg _T_522 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 672:64] - _T_522 <= ebreak_to_debug_mode_r @[dec_tlu_ctl.scala 672:64] - ebreak_to_debug_mode_r_d1 <= _T_522 @[dec_tlu_ctl.scala 672:34] - io.tlu_mem.dec_tlu_fence_i_wb <= fence_i_r @[dec_tlu_ctl.scala 673:39] - node _T_523 = or(ebreak_r, ecall_r) @[dec_tlu_ctl.scala 686:41] - node _T_524 = or(_T_523, illegal_r) @[dec_tlu_ctl.scala 686:51] - node _T_525 = or(_T_524, inst_acc_r) @[dec_tlu_ctl.scala 686:63] - node _T_526 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 686:79] - node _T_527 = and(_T_525, _T_526) @[dec_tlu_ctl.scala 686:77] - node _T_528 = not(io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 686:92] - node i0_exception_valid_r = and(_T_527, _T_528) @[dec_tlu_ctl.scala 686:90] - node _T_529 = not(take_nmi) @[dec_tlu_ctl.scala 695:33] - node _T_530 = and(take_ext_int, _T_529) @[dec_tlu_ctl.scala 695:31] - node _T_531 = bits(_T_530, 0, 0) @[dec_tlu_ctl.scala 695:44] - node _T_532 = not(take_nmi) @[dec_tlu_ctl.scala 696:27] - node _T_533 = and(take_timer_int, _T_532) @[dec_tlu_ctl.scala 696:25] - node _T_534 = bits(_T_533, 0, 0) @[dec_tlu_ctl.scala 696:38] - node _T_535 = not(take_nmi) @[dec_tlu_ctl.scala 697:26] - node _T_536 = and(take_soft_int, _T_535) @[dec_tlu_ctl.scala 697:24] - node _T_537 = bits(_T_536, 0, 0) @[dec_tlu_ctl.scala 697:37] - node _T_538 = not(take_nmi) @[dec_tlu_ctl.scala 698:32] - node _T_539 = and(take_int_timer0_int, _T_538) @[dec_tlu_ctl.scala 698:30] - node _T_540 = bits(_T_539, 0, 0) @[dec_tlu_ctl.scala 698:43] - node _T_541 = not(take_nmi) @[dec_tlu_ctl.scala 699:32] - node _T_542 = and(take_int_timer1_int, _T_541) @[dec_tlu_ctl.scala 699:30] - node _T_543 = bits(_T_542, 0, 0) @[dec_tlu_ctl.scala 699:43] - node _T_544 = not(take_nmi) @[dec_tlu_ctl.scala 700:24] - node _T_545 = and(take_ce_int, _T_544) @[dec_tlu_ctl.scala 700:22] - node _T_546 = bits(_T_545, 0, 0) @[dec_tlu_ctl.scala 700:35] - node _T_547 = not(take_nmi) @[dec_tlu_ctl.scala 701:22] - node _T_548 = and(illegal_r, _T_547) @[dec_tlu_ctl.scala 701:20] - node _T_549 = bits(_T_548, 0, 0) @[dec_tlu_ctl.scala 701:33] - node _T_550 = not(take_nmi) @[dec_tlu_ctl.scala 702:21] - node _T_551 = and(ecall_r, _T_550) @[dec_tlu_ctl.scala 702:19] - node _T_552 = bits(_T_551, 0, 0) @[dec_tlu_ctl.scala 702:32] - node _T_553 = not(take_nmi) @[dec_tlu_ctl.scala 703:24] - node _T_554 = and(inst_acc_r, _T_553) @[dec_tlu_ctl.scala 703:22] - node _T_555 = bits(_T_554, 0, 0) @[dec_tlu_ctl.scala 703:35] - node _T_556 = or(ebreak_r, i0_trigger_hit_r) @[dec_tlu_ctl.scala 704:20] - node _T_557 = not(take_nmi) @[dec_tlu_ctl.scala 704:42] - node _T_558 = and(_T_556, _T_557) @[dec_tlu_ctl.scala 704:40] - node _T_559 = bits(_T_558, 0, 0) @[dec_tlu_ctl.scala 704:53] - node _T_560 = not(lsu_exc_st_r) @[dec_tlu_ctl.scala 705:25] - node _T_561 = and(lsu_exc_ma_r, _T_560) @[dec_tlu_ctl.scala 705:23] - node _T_562 = not(take_nmi) @[dec_tlu_ctl.scala 705:41] - node _T_563 = and(_T_561, _T_562) @[dec_tlu_ctl.scala 705:39] - node _T_564 = bits(_T_563, 0, 0) @[dec_tlu_ctl.scala 705:52] - node _T_565 = not(lsu_exc_st_r) @[dec_tlu_ctl.scala 706:26] - node _T_566 = and(lsu_exc_acc_r, _T_565) @[dec_tlu_ctl.scala 706:24] - node _T_567 = not(take_nmi) @[dec_tlu_ctl.scala 706:42] - node _T_568 = and(_T_566, _T_567) @[dec_tlu_ctl.scala 706:40] - node _T_569 = bits(_T_568, 0, 0) @[dec_tlu_ctl.scala 706:53] - node _T_570 = and(lsu_exc_ma_r, lsu_exc_st_r) @[dec_tlu_ctl.scala 707:23] - node _T_571 = not(take_nmi) @[dec_tlu_ctl.scala 707:40] - node _T_572 = and(_T_570, _T_571) @[dec_tlu_ctl.scala 707:38] - node _T_573 = bits(_T_572, 0, 0) @[dec_tlu_ctl.scala 707:51] - node _T_574 = and(lsu_exc_acc_r, lsu_exc_st_r) @[dec_tlu_ctl.scala 708:24] - node _T_575 = not(take_nmi) @[dec_tlu_ctl.scala 708:41] - node _T_576 = and(_T_574, _T_575) @[dec_tlu_ctl.scala 708:39] - node _T_577 = bits(_T_576, 0, 0) @[dec_tlu_ctl.scala 708:52] + node update_hit_bit_r = and(_T_342, i0_trigger_chain_masked_r) @[dec_tlu_ctl.scala 533:56] + node _T_343 = and(i0_trigger_chain_masked_r, trigger_action) @[dec_tlu_ctl.scala 536:57] + node i0_trigger_action_r = orr(_T_343) @[dec_tlu_ctl.scala 536:75] + node _T_344 = and(i0_trigger_hit_r, i0_trigger_action_r) @[dec_tlu_ctl.scala 538:45] + trigger_hit_dmode_r <= _T_344 @[dec_tlu_ctl.scala 538:24] + node _T_345 = not(trigger_hit_dmode_r) @[dec_tlu_ctl.scala 540:55] + node mepc_trigger_hit_sel_pc_r = and(i0_trigger_hit_r, _T_345) @[dec_tlu_ctl.scala 540:53] + node _T_346 = not(io.dec_tlu_debug_mode) @[dec_tlu_ctl.scala 567:62] + node _T_347 = and(i_cpu_halt_req_sync, _T_346) @[dec_tlu_ctl.scala 567:60] + node _T_348 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 567:87] + node i_cpu_halt_req_sync_qual = and(_T_347, _T_348) @[dec_tlu_ctl.scala 567:85] + node _T_349 = not(io.dec_tlu_debug_mode) @[dec_tlu_ctl.scala 568:60] + node _T_350 = and(i_cpu_run_req_sync, _T_349) @[dec_tlu_ctl.scala 568:58] + node _T_351 = and(_T_350, pmu_fw_tlu_halted_f) @[dec_tlu_ctl.scala 568:83] + node _T_352 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 568:107] + node i_cpu_run_req_sync_qual = and(_T_351, _T_352) @[dec_tlu_ctl.scala 568:105] + reg i_cpu_halt_req_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 570:80] + i_cpu_halt_req_d1 <= i_cpu_halt_req_sync_qual @[dec_tlu_ctl.scala 570:80] + reg i_cpu_run_req_d1_raw : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 571:80] + i_cpu_run_req_d1_raw <= i_cpu_run_req_sync_qual @[dec_tlu_ctl.scala 571:80] + reg _T_353 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 572:81] + _T_353 <= cpu_halt_status @[dec_tlu_ctl.scala 572:81] + io.o_cpu_halt_status <= _T_353 @[dec_tlu_ctl.scala 572:49] + reg _T_354 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 573:81] + _T_354 <= cpu_halt_ack @[dec_tlu_ctl.scala 573:81] + io.o_cpu_halt_ack <= _T_354 @[dec_tlu_ctl.scala 573:49] + reg _T_355 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 574:81] + _T_355 <= cpu_run_ack @[dec_tlu_ctl.scala 574:81] + io.o_cpu_run_ack <= _T_355 @[dec_tlu_ctl.scala 574:49] + reg internal_pmu_fw_halt_mode_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 575:68] + internal_pmu_fw_halt_mode_f <= internal_pmu_fw_halt_mode @[dec_tlu_ctl.scala 575:68] + reg _T_356 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 576:73] + _T_356 <= pmu_fw_halt_req_ns @[dec_tlu_ctl.scala 576:73] + pmu_fw_halt_req_f <= _T_356 @[dec_tlu_ctl.scala 576:41] + reg _T_357 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 577:73] + _T_357 <= pmu_fw_tlu_halted @[dec_tlu_ctl.scala 577:73] + pmu_fw_tlu_halted_f <= _T_357 @[dec_tlu_ctl.scala 577:41] + reg _T_358 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 578:73] + _T_358 <= int_timer0_int_hold @[dec_tlu_ctl.scala 578:73] + int_timer0_int_hold_f <= _T_358 @[dec_tlu_ctl.scala 578:41] + reg _T_359 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 579:73] + _T_359 <= int_timer1_int_hold @[dec_tlu_ctl.scala 579:73] + int_timer1_int_hold_f <= _T_359 @[dec_tlu_ctl.scala 579:41] + node _T_360 = not(i_cpu_halt_req_d1) @[dec_tlu_ctl.scala 583:52] + node ext_halt_pulse = and(i_cpu_halt_req_sync_qual, _T_360) @[dec_tlu_ctl.scala 583:50] + node enter_pmu_fw_halt_req = or(ext_halt_pulse, fw_halt_req) @[dec_tlu_ctl.scala 584:48] + node _T_361 = not(pmu_fw_tlu_halted) @[dec_tlu_ctl.scala 585:72] + node _T_362 = and(pmu_fw_halt_req_f, _T_361) @[dec_tlu_ctl.scala 585:70] + node _T_363 = or(enter_pmu_fw_halt_req, _T_362) @[dec_tlu_ctl.scala 585:49] + node _T_364 = not(debug_halt_req_f) @[dec_tlu_ctl.scala 585:95] + node _T_365 = and(_T_363, _T_364) @[dec_tlu_ctl.scala 585:93] + pmu_fw_halt_req_ns <= _T_365 @[dec_tlu_ctl.scala 585:23] + node _T_366 = not(i_cpu_run_req_d1) @[dec_tlu_ctl.scala 586:85] + node _T_367 = and(internal_pmu_fw_halt_mode_f, _T_366) @[dec_tlu_ctl.scala 586:83] + node _T_368 = not(debug_halt_req_f) @[dec_tlu_ctl.scala 586:105] + node _T_369 = and(_T_367, _T_368) @[dec_tlu_ctl.scala 586:103] + node _T_370 = or(pmu_fw_halt_req_ns, _T_369) @[dec_tlu_ctl.scala 586:52] + internal_pmu_fw_halt_mode <= _T_370 @[dec_tlu_ctl.scala 586:30] + node _T_371 = and(pmu_fw_halt_req_f, core_empty) @[dec_tlu_ctl.scala 589:45] + node _T_372 = and(_T_371, halt_taken) @[dec_tlu_ctl.scala 589:58] + node _T_373 = not(enter_debug_halt_req) @[dec_tlu_ctl.scala 589:73] + node _T_374 = and(_T_372, _T_373) @[dec_tlu_ctl.scala 589:71] + node _T_375 = not(i_cpu_run_req_d1) @[dec_tlu_ctl.scala 589:121] + node _T_376 = and(pmu_fw_tlu_halted_f, _T_375) @[dec_tlu_ctl.scala 589:119] + node _T_377 = or(_T_374, _T_376) @[dec_tlu_ctl.scala 589:96] + node _T_378 = not(debug_halt_req_f) @[dec_tlu_ctl.scala 589:143] + node _T_379 = and(_T_377, _T_378) @[dec_tlu_ctl.scala 589:141] + pmu_fw_tlu_halted <= _T_379 @[dec_tlu_ctl.scala 589:22] + node _T_380 = and(i_cpu_halt_req_d1, pmu_fw_tlu_halted_f) @[dec_tlu_ctl.scala 591:38] + cpu_halt_ack <= _T_380 @[dec_tlu_ctl.scala 591:17] + node _T_381 = not(i_cpu_run_req_d1) @[dec_tlu_ctl.scala 592:46] + node _T_382 = and(pmu_fw_tlu_halted_f, _T_381) @[dec_tlu_ctl.scala 592:44] + node _T_383 = not(i_cpu_run_req_d1) @[dec_tlu_ctl.scala 592:91] + node _T_384 = and(io.o_cpu_halt_status, _T_383) @[dec_tlu_ctl.scala 592:89] + node _T_385 = not(debug_mode_status) @[dec_tlu_ctl.scala 592:111] + node _T_386 = and(_T_384, _T_385) @[dec_tlu_ctl.scala 592:109] + node _T_387 = or(_T_382, _T_386) @[dec_tlu_ctl.scala 592:65] + cpu_halt_status <= _T_387 @[dec_tlu_ctl.scala 592:20] + node _T_388 = and(io.o_cpu_halt_status, i_cpu_run_req_sync_qual) @[dec_tlu_ctl.scala 593:41] + node _T_389 = and(io.o_cpu_run_ack, i_cpu_run_req_sync_qual) @[dec_tlu_ctl.scala 593:88] + node _T_390 = or(_T_388, _T_389) @[dec_tlu_ctl.scala 593:68] + cpu_run_ack <= _T_390 @[dec_tlu_ctl.scala 593:16] + io.o_debug_mode_status <= debug_mode_status @[dec_tlu_ctl.scala 595:27] + node _T_391 = or(nmi_int_detected, timer_int_ready) @[dec_tlu_ctl.scala 598:66] + node _T_392 = or(_T_391, soft_int_ready) @[dec_tlu_ctl.scala 598:84] + node _T_393 = or(_T_392, int_timer0_int_hold_f) @[dec_tlu_ctl.scala 598:101] + node _T_394 = or(_T_393, int_timer1_int_hold_f) @[dec_tlu_ctl.scala 598:125] + node _T_395 = and(io.dec_pic.mhwakeup, mhwakeup_ready) @[dec_tlu_ctl.scala 598:172] + node _T_396 = or(_T_394, _T_395) @[dec_tlu_ctl.scala 598:149] + node _T_397 = and(_T_396, io.o_cpu_halt_status) @[dec_tlu_ctl.scala 598:191] + node _T_398 = not(i_cpu_halt_req_d1) @[dec_tlu_ctl.scala 598:216] + node _T_399 = and(_T_397, _T_398) @[dec_tlu_ctl.scala 598:214] + node _T_400 = or(i_cpu_run_req_d1_raw, _T_399) @[dec_tlu_ctl.scala 598:45] + i_cpu_run_req_d1 <= _T_400 @[dec_tlu_ctl.scala 598:21] + reg _T_401 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 604:89] + _T_401 <= mdseac_locked_ns @[dec_tlu_ctl.scala 604:89] + mdseac_locked_f <= _T_401 @[dec_tlu_ctl.scala 604:57] + reg lsu_single_ecc_error_r_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 605:72] + lsu_single_ecc_error_r_d1 <= io.lsu_single_ecc_error_incr @[dec_tlu_ctl.scala 605:72] + node _T_402 = not(io.dec_tlu_flush_lower_wb) @[dec_tlu_ctl.scala 607:57] + node lsu_exc_valid_r_raw = and(io.lsu_error_pkt_r.valid, _T_402) @[dec_tlu_ctl.scala 607:55] + lsu_i0_exc_r_raw <= io.lsu_error_pkt_r.valid @[dec_tlu_ctl.scala 608:21] + node _T_403 = and(lsu_i0_exc_r_raw, lsu_exc_valid_r_raw) @[dec_tlu_ctl.scala 609:40] + node _T_404 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 609:64] + node _T_405 = and(_T_403, _T_404) @[dec_tlu_ctl.scala 609:62] + node _T_406 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 609:84] + node lsu_exc_valid_r = and(_T_405, _T_406) @[dec_tlu_ctl.scala 609:82] + reg _T_407 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 611:74] + _T_407 <= lsu_exc_valid_r @[dec_tlu_ctl.scala 611:74] + lsu_exc_valid_r_d1 <= _T_407 @[dec_tlu_ctl.scala 611:41] + reg lsu_i0_exc_r_d1 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 612:73] + lsu_i0_exc_r_d1 <= lsu_exc_valid_r @[dec_tlu_ctl.scala 612:73] + node _T_408 = not(io.lsu_error_pkt_r.bits.exc_type) @[dec_tlu_ctl.scala 613:40] + node lsu_exc_ma_r = and(lsu_exc_valid_r, _T_408) @[dec_tlu_ctl.scala 613:38] + node lsu_exc_acc_r = and(lsu_exc_valid_r, io.lsu_error_pkt_r.bits.exc_type) @[dec_tlu_ctl.scala 614:38] + node lsu_exc_st_r = and(lsu_exc_valid_r, io.lsu_error_pkt_r.bits.inst_type) @[dec_tlu_ctl.scala 615:38] + node _T_409 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 619:49] + node _T_410 = and(io.dec_tlu_i0_valid_r, _T_409) @[dec_tlu_ctl.scala 619:47] + node _T_411 = not(io.lsu_error_pkt_r.bits.inst_type) @[dec_tlu_ctl.scala 619:70] + node _T_412 = and(_T_411, io.lsu_error_pkt_r.bits.single_ecc_error) @[dec_tlu_ctl.scala 619:105] + node lsu_i0_rfnpc_r = and(_T_410, _T_412) @[dec_tlu_ctl.scala 619:67] + node _T_413 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 622:52] + node _T_414 = and(io.dec_tlu_i0_valid_r, _T_413) @[dec_tlu_ctl.scala 622:50] + node _T_415 = not(lsu_exc_valid_r) @[dec_tlu_ctl.scala 622:65] + node _T_416 = and(_T_414, _T_415) @[dec_tlu_ctl.scala 622:63] + node _T_417 = not(inst_acc_r) @[dec_tlu_ctl.scala 622:82] + node _T_418 = and(_T_416, _T_417) @[dec_tlu_ctl.scala 622:79] + node _T_419 = not(io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 622:96] + node _T_420 = and(_T_418, _T_419) @[dec_tlu_ctl.scala 622:94] + node _T_421 = not(request_debug_mode_r_d1) @[dec_tlu_ctl.scala 622:121] + node _T_422 = and(_T_420, _T_421) @[dec_tlu_ctl.scala 622:119] + node _T_423 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 622:148] + node tlu_i0_commit_cmt = and(_T_422, _T_423) @[dec_tlu_ctl.scala 622:146] + node _T_424 = or(rfpc_i0_r, lsu_exc_valid_r) @[dec_tlu_ctl.scala 625:38] + node _T_425 = or(_T_424, inst_acc_r) @[dec_tlu_ctl.scala 625:53] + node _T_426 = and(illegal_r, io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 625:79] + node _T_427 = or(_T_425, _T_426) @[dec_tlu_ctl.scala 625:66] + node _T_428 = or(_T_427, i0_trigger_hit_r) @[dec_tlu_ctl.scala 625:104] + tlu_i0_kill_writeb_r <= _T_428 @[dec_tlu_ctl.scala 625:25] + io.tlu_mem.dec_tlu_i0_commit_cmt <= tlu_i0_commit_cmt @[dec_tlu_ctl.scala 626:37] + node _T_429 = not(tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 631:44] + node _T_430 = and(io.dec_tlu_i0_valid_r, _T_429) @[dec_tlu_ctl.scala 631:42] + node _T_431 = or(io.tlu_exu.exu_i0_br_error_r, io.tlu_exu.exu_i0_br_start_error_r) @[dec_tlu_ctl.scala 631:98] + node _T_432 = and(_T_430, _T_431) @[dec_tlu_ctl.scala 631:66] + node _T_433 = or(ic_perr_r_d1, iccm_sbecc_r_d1) @[dec_tlu_ctl.scala 631:154] + node _T_434 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 631:175] + node _T_435 = and(_T_433, _T_434) @[dec_tlu_ctl.scala 631:173] + node _T_436 = or(_T_432, _T_435) @[dec_tlu_ctl.scala 631:137] + node _T_437 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 631:199] + node _T_438 = and(_T_436, _T_437) @[dec_tlu_ctl.scala 631:196] + node _T_439 = not(lsu_i0_rfnpc_r) @[dec_tlu_ctl.scala 631:220] + node _T_440 = and(_T_438, _T_439) @[dec_tlu_ctl.scala 631:217] + rfpc_i0_r <= _T_440 @[dec_tlu_ctl.scala 631:14] + node _T_441 = not(io.tlu_exu.dec_tlu_flush_lower_r) @[dec_tlu_ctl.scala 634:70] + node _T_442 = and(iccm_repair_state_d1, _T_441) @[dec_tlu_ctl.scala 634:68] + node _T_443 = or(iccm_sbecc_r_d1, _T_442) @[dec_tlu_ctl.scala 634:44] + iccm_repair_state_ns <= _T_443 @[dec_tlu_ctl.scala 634:25] + node _T_444 = and(tlu_i0_commit_cmt, iccm_repair_state_d1) @[dec_tlu_ctl.scala 640:52] + node _T_445 = or(ebreak_r, ecall_r) @[dec_tlu_ctl.scala 640:88] + node _T_446 = or(_T_445, mret_r) @[dec_tlu_ctl.scala 640:98] + node _T_447 = or(_T_446, take_reset) @[dec_tlu_ctl.scala 640:107] + node _T_448 = or(_T_447, illegal_r) @[dec_tlu_ctl.scala 640:120] + node _T_449 = eq(io.dec_csr_wraddr_r, UInt<12>("h07c2")) @[dec_tlu_ctl.scala 640:176] + node _T_450 = and(dec_csr_wen_r_mod, _T_449) @[dec_tlu_ctl.scala 640:153] + node _T_451 = or(_T_448, _T_450) @[dec_tlu_ctl.scala 640:132] + node _T_452 = not(_T_451) @[dec_tlu_ctl.scala 640:77] + node iccm_repair_state_rfnpc = and(_T_444, _T_452) @[dec_tlu_ctl.scala 640:75] + node _T_453 = and(io.tlu_exu.exu_i0_br_error_r, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 643:59] + node _T_454 = not(tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 643:85] + node dec_tlu_br0_error_r = and(_T_453, _T_454) @[dec_tlu_ctl.scala 643:83] + node _T_455 = and(io.tlu_exu.exu_i0_br_start_error_r, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 644:71] + node _T_456 = not(tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 644:97] + node dec_tlu_br0_start_error_r = and(_T_455, _T_456) @[dec_tlu_ctl.scala 644:95] + node _T_457 = and(io.tlu_exu.exu_i0_br_valid_r, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 645:55] + node _T_458 = not(tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 645:81] + node _T_459 = and(_T_457, _T_458) @[dec_tlu_ctl.scala 645:79] + node _T_460 = not(io.tlu_exu.exu_i0_br_mp_r) @[dec_tlu_ctl.scala 645:106] + node _T_461 = not(io.tlu_exu.exu_pmu_i0_br_ataken) @[dec_tlu_ctl.scala 645:135] + node _T_462 = or(_T_460, _T_461) @[dec_tlu_ctl.scala 645:133] + node dec_tlu_br0_v_r = and(_T_459, _T_462) @[dec_tlu_ctl.scala 645:103] + io.tlu_bp.dec_tlu_br0_r_pkt.bits.hist <= io.tlu_exu.exu_i0_br_hist_r @[dec_tlu_ctl.scala 648:65] + io.tlu_bp.dec_tlu_br0_r_pkt.bits.br_error <= dec_tlu_br0_error_r @[dec_tlu_ctl.scala 649:57] + io.tlu_bp.dec_tlu_br0_r_pkt.bits.br_start_error <= dec_tlu_br0_start_error_r @[dec_tlu_ctl.scala 650:57] + io.tlu_bp.dec_tlu_br0_r_pkt.valid <= dec_tlu_br0_v_r @[dec_tlu_ctl.scala 651:57] + io.tlu_bp.dec_tlu_br0_r_pkt.bits.way <= io.exu_i0_br_way_r @[dec_tlu_ctl.scala 652:65] + io.tlu_bp.dec_tlu_br0_r_pkt.bits.middle <= io.tlu_exu.exu_i0_br_middle_r @[dec_tlu_ctl.scala 653:65] + node _T_463 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h08")) @[dec_tlu_ctl.scala 656:51] + node _T_464 = and(_T_463, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 656:64] + node _T_465 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 656:90] + node _T_466 = and(_T_464, _T_465) @[dec_tlu_ctl.scala 656:88] + node _T_467 = bits(dcsr, 15, 15) @[dec_tlu_ctl.scala 656:115] + node _T_468 = not(_T_467) @[dec_tlu_ctl.scala 656:110] + node _T_469 = and(_T_466, _T_468) @[dec_tlu_ctl.scala 656:108] + node _T_470 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 656:132] + node _T_471 = and(_T_469, _T_470) @[dec_tlu_ctl.scala 656:130] + ebreak_r <= _T_471 @[dec_tlu_ctl.scala 656:13] + node _T_472 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h09")) @[dec_tlu_ctl.scala 657:51] + node _T_473 = and(_T_472, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 657:64] + node _T_474 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 657:90] + node _T_475 = and(_T_473, _T_474) @[dec_tlu_ctl.scala 657:88] + node _T_476 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 657:110] + node _T_477 = and(_T_475, _T_476) @[dec_tlu_ctl.scala 657:108] + ecall_r <= _T_477 @[dec_tlu_ctl.scala 657:13] + node _T_478 = not(io.dec_tlu_packet_r.legal) @[dec_tlu_ctl.scala 658:17] + node _T_479 = and(_T_478, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 658:46] + node _T_480 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 658:72] + node _T_481 = and(_T_479, _T_480) @[dec_tlu_ctl.scala 658:70] + node _T_482 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 658:92] + node _T_483 = and(_T_481, _T_482) @[dec_tlu_ctl.scala 658:90] + illegal_r <= _T_483 @[dec_tlu_ctl.scala 658:13] + node _T_484 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h0c")) @[dec_tlu_ctl.scala 659:51] + node _T_485 = and(_T_484, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 659:64] + node _T_486 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 659:90] + node _T_487 = and(_T_485, _T_486) @[dec_tlu_ctl.scala 659:88] + node _T_488 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 659:110] + node _T_489 = and(_T_487, _T_488) @[dec_tlu_ctl.scala 659:108] + mret_r <= _T_489 @[dec_tlu_ctl.scala 659:13] + node _T_490 = and(io.dec_tlu_packet_r.fence_i, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 661:50] + node _T_491 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 661:76] + node _T_492 = and(_T_490, _T_491) @[dec_tlu_ctl.scala 661:74] + node _T_493 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 661:97] + node _T_494 = and(_T_492, _T_493) @[dec_tlu_ctl.scala 661:95] + fence_i_r <= _T_494 @[dec_tlu_ctl.scala 661:17] + node _T_495 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 662:53] + node _T_496 = and(io.tlu_mem.ifu_ic_error_start, _T_495) @[dec_tlu_ctl.scala 662:51] + node _T_497 = not(debug_mode_status) @[dec_tlu_ctl.scala 662:75] + node _T_498 = or(_T_497, dcsr_single_step_running) @[dec_tlu_ctl.scala 662:101] + node _T_499 = and(_T_496, _T_498) @[dec_tlu_ctl.scala 662:72] + node _T_500 = not(internal_pmu_fw_halt_mode_f) @[dec_tlu_ctl.scala 662:131] + node _T_501 = and(_T_499, _T_500) @[dec_tlu_ctl.scala 662:129] + ic_perr_r <= _T_501 @[dec_tlu_ctl.scala 662:17] + node _T_502 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 663:61] + node _T_503 = and(io.tlu_mem.ifu_iccm_rd_ecc_single_err, _T_502) @[dec_tlu_ctl.scala 663:59] + node _T_504 = not(debug_mode_status) @[dec_tlu_ctl.scala 663:83] + node _T_505 = or(_T_504, dcsr_single_step_running) @[dec_tlu_ctl.scala 663:109] + node _T_506 = and(_T_503, _T_505) @[dec_tlu_ctl.scala 663:80] + node _T_507 = not(internal_pmu_fw_halt_mode_f) @[dec_tlu_ctl.scala 663:139] + node _T_508 = and(_T_506, _T_507) @[dec_tlu_ctl.scala 663:137] + iccm_sbecc_r <= _T_508 @[dec_tlu_ctl.scala 663:17] + node _T_509 = and(io.dec_tlu_packet_r.icaf, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 664:49] + inst_acc_r_raw <= _T_509 @[dec_tlu_ctl.scala 664:20] + node _T_510 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 665:35] + node _T_511 = and(inst_acc_r_raw, _T_510) @[dec_tlu_ctl.scala 665:33] + node _T_512 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 665:48] + node _T_513 = and(_T_511, _T_512) @[dec_tlu_ctl.scala 665:46] + inst_acc_r <= _T_513 @[dec_tlu_ctl.scala 665:15] + node _T_514 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h08")) @[dec_tlu_ctl.scala 668:64] + node _T_515 = and(_T_514, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 668:77] + node _T_516 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 668:103] + node _T_517 = and(_T_515, _T_516) @[dec_tlu_ctl.scala 668:101] + node _T_518 = bits(dcsr, 15, 15) @[dec_tlu_ctl.scala 668:127] + node _T_519 = and(_T_517, _T_518) @[dec_tlu_ctl.scala 668:121] + node _T_520 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 668:144] + node _T_521 = and(_T_519, _T_520) @[dec_tlu_ctl.scala 668:142] + ebreak_to_debug_mode_r <= _T_521 @[dec_tlu_ctl.scala 668:27] + reg _T_522 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 670:64] + _T_522 <= ebreak_to_debug_mode_r @[dec_tlu_ctl.scala 670:64] + ebreak_to_debug_mode_r_d1 <= _T_522 @[dec_tlu_ctl.scala 670:34] + io.tlu_mem.dec_tlu_fence_i_wb <= fence_i_r @[dec_tlu_ctl.scala 671:39] + node _T_523 = or(ebreak_r, ecall_r) @[dec_tlu_ctl.scala 684:41] + node _T_524 = or(_T_523, illegal_r) @[dec_tlu_ctl.scala 684:51] + node _T_525 = or(_T_524, inst_acc_r) @[dec_tlu_ctl.scala 684:63] + node _T_526 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 684:79] + node _T_527 = and(_T_525, _T_526) @[dec_tlu_ctl.scala 684:77] + node _T_528 = not(io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 684:92] + node i0_exception_valid_r = and(_T_527, _T_528) @[dec_tlu_ctl.scala 684:90] + node _T_529 = not(take_nmi) @[dec_tlu_ctl.scala 693:33] + node _T_530 = and(take_ext_int, _T_529) @[dec_tlu_ctl.scala 693:31] + node _T_531 = bits(_T_530, 0, 0) @[dec_tlu_ctl.scala 693:44] + node _T_532 = not(take_nmi) @[dec_tlu_ctl.scala 694:27] + node _T_533 = and(take_timer_int, _T_532) @[dec_tlu_ctl.scala 694:25] + node _T_534 = bits(_T_533, 0, 0) @[dec_tlu_ctl.scala 694:38] + node _T_535 = not(take_nmi) @[dec_tlu_ctl.scala 695:26] + node _T_536 = and(take_soft_int, _T_535) @[dec_tlu_ctl.scala 695:24] + node _T_537 = bits(_T_536, 0, 0) @[dec_tlu_ctl.scala 695:37] + node _T_538 = not(take_nmi) @[dec_tlu_ctl.scala 696:32] + node _T_539 = and(take_int_timer0_int, _T_538) @[dec_tlu_ctl.scala 696:30] + node _T_540 = bits(_T_539, 0, 0) @[dec_tlu_ctl.scala 696:43] + node _T_541 = not(take_nmi) @[dec_tlu_ctl.scala 697:32] + node _T_542 = and(take_int_timer1_int, _T_541) @[dec_tlu_ctl.scala 697:30] + node _T_543 = bits(_T_542, 0, 0) @[dec_tlu_ctl.scala 697:43] + node _T_544 = not(take_nmi) @[dec_tlu_ctl.scala 698:24] + node _T_545 = and(take_ce_int, _T_544) @[dec_tlu_ctl.scala 698:22] + node _T_546 = bits(_T_545, 0, 0) @[dec_tlu_ctl.scala 698:35] + node _T_547 = not(take_nmi) @[dec_tlu_ctl.scala 699:22] + node _T_548 = and(illegal_r, _T_547) @[dec_tlu_ctl.scala 699:20] + node _T_549 = bits(_T_548, 0, 0) @[dec_tlu_ctl.scala 699:33] + node _T_550 = not(take_nmi) @[dec_tlu_ctl.scala 700:21] + node _T_551 = and(ecall_r, _T_550) @[dec_tlu_ctl.scala 700:19] + node _T_552 = bits(_T_551, 0, 0) @[dec_tlu_ctl.scala 700:32] + node _T_553 = not(take_nmi) @[dec_tlu_ctl.scala 701:24] + node _T_554 = and(inst_acc_r, _T_553) @[dec_tlu_ctl.scala 701:22] + node _T_555 = bits(_T_554, 0, 0) @[dec_tlu_ctl.scala 701:35] + node _T_556 = or(ebreak_r, i0_trigger_hit_r) @[dec_tlu_ctl.scala 702:20] + node _T_557 = not(take_nmi) @[dec_tlu_ctl.scala 702:42] + node _T_558 = and(_T_556, _T_557) @[dec_tlu_ctl.scala 702:40] + node _T_559 = bits(_T_558, 0, 0) @[dec_tlu_ctl.scala 702:53] + node _T_560 = not(lsu_exc_st_r) @[dec_tlu_ctl.scala 703:25] + node _T_561 = and(lsu_exc_ma_r, _T_560) @[dec_tlu_ctl.scala 703:23] + node _T_562 = not(take_nmi) @[dec_tlu_ctl.scala 703:41] + node _T_563 = and(_T_561, _T_562) @[dec_tlu_ctl.scala 703:39] + node _T_564 = bits(_T_563, 0, 0) @[dec_tlu_ctl.scala 703:52] + node _T_565 = not(lsu_exc_st_r) @[dec_tlu_ctl.scala 704:26] + node _T_566 = and(lsu_exc_acc_r, _T_565) @[dec_tlu_ctl.scala 704:24] + node _T_567 = not(take_nmi) @[dec_tlu_ctl.scala 704:42] + node _T_568 = and(_T_566, _T_567) @[dec_tlu_ctl.scala 704:40] + node _T_569 = bits(_T_568, 0, 0) @[dec_tlu_ctl.scala 704:53] + node _T_570 = and(lsu_exc_ma_r, lsu_exc_st_r) @[dec_tlu_ctl.scala 705:23] + node _T_571 = not(take_nmi) @[dec_tlu_ctl.scala 705:40] + node _T_572 = and(_T_570, _T_571) @[dec_tlu_ctl.scala 705:38] + node _T_573 = bits(_T_572, 0, 0) @[dec_tlu_ctl.scala 705:51] + node _T_574 = and(lsu_exc_acc_r, lsu_exc_st_r) @[dec_tlu_ctl.scala 706:24] + node _T_575 = not(take_nmi) @[dec_tlu_ctl.scala 706:41] + node _T_576 = and(_T_574, _T_575) @[dec_tlu_ctl.scala 706:39] + node _T_577 = bits(_T_576, 0, 0) @[dec_tlu_ctl.scala 706:52] node _T_578 = mux(_T_531, UInt<5>("h0b"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_579 = mux(_T_534, UInt<5>("h07"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_580 = mux(_T_537, UInt<5>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] @@ -78982,281 +78992,281 @@ circuit quasar_wrapper : node _T_604 = or(_T_603, _T_591) @[Mux.scala 27:72] wire exc_cause_r : UInt<5> @[Mux.scala 27:72] exc_cause_r <= _T_604 @[Mux.scala 27:72] - node _T_605 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 719:24] - node _T_606 = and(_T_605, mstatus_mie_ns) @[dec_tlu_ctl.scala 719:49] - node _T_607 = bits(mip, 2, 2) @[dec_tlu_ctl.scala 719:71] - node _T_608 = and(_T_606, _T_607) @[dec_tlu_ctl.scala 719:66] - node _T_609 = bits(mie_ns, 2, 2) @[dec_tlu_ctl.scala 719:92] - node _T_610 = and(_T_608, _T_609) @[dec_tlu_ctl.scala 719:84] - mhwakeup_ready <= _T_610 @[dec_tlu_ctl.scala 719:20] - node _T_611 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 720:23] - node _T_612 = and(_T_611, mstatus_mie_ns) @[dec_tlu_ctl.scala 720:48] - node _T_613 = bits(mip, 2, 2) @[dec_tlu_ctl.scala 720:70] - node _T_614 = and(_T_612, _T_613) @[dec_tlu_ctl.scala 720:65] - node _T_615 = bits(mie_ns, 2, 2) @[dec_tlu_ctl.scala 720:91] - node _T_616 = and(_T_614, _T_615) @[dec_tlu_ctl.scala 720:83] - node _T_617 = not(ignore_ext_int_due_to_lsu_stall) @[dec_tlu_ctl.scala 720:104] - node _T_618 = and(_T_616, _T_617) @[dec_tlu_ctl.scala 720:102] - ext_int_ready <= _T_618 @[dec_tlu_ctl.scala 720:20] - node _T_619 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 721:23] - node _T_620 = and(_T_619, mstatus_mie_ns) @[dec_tlu_ctl.scala 721:48] - node _T_621 = bits(mip, 5, 5) @[dec_tlu_ctl.scala 721:70] - node _T_622 = and(_T_620, _T_621) @[dec_tlu_ctl.scala 721:65] - node _T_623 = bits(mie_ns, 5, 5) @[dec_tlu_ctl.scala 721:91] - node _T_624 = and(_T_622, _T_623) @[dec_tlu_ctl.scala 721:83] - ce_int_ready <= _T_624 @[dec_tlu_ctl.scala 721:20] - node _T_625 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 722:23] - node _T_626 = and(_T_625, mstatus_mie_ns) @[dec_tlu_ctl.scala 722:48] - node _T_627 = bits(mip, 0, 0) @[dec_tlu_ctl.scala 722:70] - node _T_628 = and(_T_626, _T_627) @[dec_tlu_ctl.scala 722:65] - node _T_629 = bits(mie_ns, 0, 0) @[dec_tlu_ctl.scala 722:91] - node _T_630 = and(_T_628, _T_629) @[dec_tlu_ctl.scala 722:83] - soft_int_ready <= _T_630 @[dec_tlu_ctl.scala 722:20] - node _T_631 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 723:23] - node _T_632 = and(_T_631, mstatus_mie_ns) @[dec_tlu_ctl.scala 723:48] - node _T_633 = bits(mip, 1, 1) @[dec_tlu_ctl.scala 723:70] - node _T_634 = and(_T_632, _T_633) @[dec_tlu_ctl.scala 723:65] - node _T_635 = bits(mie_ns, 1, 1) @[dec_tlu_ctl.scala 723:91] - node _T_636 = and(_T_634, _T_635) @[dec_tlu_ctl.scala 723:83] - timer_int_ready <= _T_636 @[dec_tlu_ctl.scala 723:20] - node _T_637 = bits(mie_ns, 4, 4) @[dec_tlu_ctl.scala 726:57] - node int_timer0_int_possible = and(mstatus_mie_ns, _T_637) @[dec_tlu_ctl.scala 726:49] - node _T_638 = bits(mip, 4, 4) @[dec_tlu_ctl.scala 727:34] - node int_timer0_int_ready = and(_T_638, int_timer0_int_possible) @[dec_tlu_ctl.scala 727:47] - node _T_639 = bits(mie_ns, 3, 3) @[dec_tlu_ctl.scala 728:57] - node int_timer1_int_possible = and(mstatus_mie_ns, _T_639) @[dec_tlu_ctl.scala 728:49] - node _T_640 = bits(mip, 3, 3) @[dec_tlu_ctl.scala 729:34] - node int_timer1_int_ready = and(_T_640, int_timer1_int_possible) @[dec_tlu_ctl.scala 729:47] - node _T_641 = or(io.dec_csr_stall_int_ff, synchronous_flush_r) @[dec_tlu_ctl.scala 733:52] - node _T_642 = or(_T_641, exc_or_int_valid_r_d1) @[dec_tlu_ctl.scala 733:74] - node int_timer_stalled = or(_T_642, mret_r) @[dec_tlu_ctl.scala 733:98] - node _T_643 = or(pmu_fw_tlu_halted_f, int_timer_stalled) @[dec_tlu_ctl.scala 735:72] - node _T_644 = and(int_timer0_int_ready, _T_643) @[dec_tlu_ctl.scala 735:49] - node _T_645 = and(int_timer0_int_possible, int_timer0_int_hold_f) @[dec_tlu_ctl.scala 735:121] - node _T_646 = not(interrupt_valid_r) @[dec_tlu_ctl.scala 735:147] - node _T_647 = and(_T_645, _T_646) @[dec_tlu_ctl.scala 735:145] - node _T_648 = not(take_ext_int_start) @[dec_tlu_ctl.scala 735:168] - node _T_649 = and(_T_647, _T_648) @[dec_tlu_ctl.scala 735:166] - node _T_650 = not(debug_mode_status) @[dec_tlu_ctl.scala 735:190] - node _T_651 = and(_T_649, _T_650) @[dec_tlu_ctl.scala 735:188] - node _T_652 = or(_T_644, _T_651) @[dec_tlu_ctl.scala 735:94] - int_timer0_int_hold <= _T_652 @[dec_tlu_ctl.scala 735:24] - node _T_653 = or(pmu_fw_tlu_halted_f, int_timer_stalled) @[dec_tlu_ctl.scala 736:72] - node _T_654 = and(int_timer1_int_ready, _T_653) @[dec_tlu_ctl.scala 736:49] - node _T_655 = and(int_timer1_int_possible, int_timer1_int_hold_f) @[dec_tlu_ctl.scala 736:121] - node _T_656 = not(interrupt_valid_r) @[dec_tlu_ctl.scala 736:147] - node _T_657 = and(_T_655, _T_656) @[dec_tlu_ctl.scala 736:145] - node _T_658 = not(take_ext_int_start) @[dec_tlu_ctl.scala 736:168] - node _T_659 = and(_T_657, _T_658) @[dec_tlu_ctl.scala 736:166] - node _T_660 = not(debug_mode_status) @[dec_tlu_ctl.scala 736:190] - node _T_661 = and(_T_659, _T_660) @[dec_tlu_ctl.scala 736:188] - node _T_662 = or(_T_654, _T_661) @[dec_tlu_ctl.scala 736:94] - int_timer1_int_hold <= _T_662 @[dec_tlu_ctl.scala 736:24] - node _T_663 = not(dcsr_single_step_running) @[dec_tlu_ctl.scala 738:59] - node _T_664 = and(debug_mode_status, _T_663) @[dec_tlu_ctl.scala 738:57] - internal_dbg_halt_timers <= _T_664 @[dec_tlu_ctl.scala 738:29] - node _T_665 = not(dcsr_single_step_running) @[dec_tlu_ctl.scala 740:55] - node _T_666 = or(_T_665, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 740:81] - node _T_667 = and(internal_dbg_halt_mode, _T_666) @[dec_tlu_ctl.scala 740:52] - node _T_668 = or(_T_667, internal_pmu_fw_halt_mode) @[dec_tlu_ctl.scala 740:107] - node _T_669 = or(_T_668, i_cpu_halt_req_d1) @[dec_tlu_ctl.scala 740:135] - node _T_670 = or(_T_669, take_nmi) @[dec_tlu_ctl.scala 740:155] - node _T_671 = or(_T_670, ebreak_to_debug_mode_r) @[dec_tlu_ctl.scala 740:166] - node _T_672 = or(_T_671, synchronous_flush_r) @[dec_tlu_ctl.scala 740:191] - node _T_673 = or(_T_672, exc_or_int_valid_r_d1) @[dec_tlu_ctl.scala 740:214] - node _T_674 = or(_T_673, mret_r) @[dec_tlu_ctl.scala 740:238] - node block_interrupts = or(_T_674, ext_int_freeze_d1) @[dec_tlu_ctl.scala 740:247] - reg _T_675 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 744:62] - _T_675 <= take_ext_int_start @[dec_tlu_ctl.scala 744:62] - take_ext_int_start_d1 <= _T_675 @[dec_tlu_ctl.scala 744:30] - reg _T_676 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 745:62] - _T_676 <= take_ext_int_start_d1 @[dec_tlu_ctl.scala 745:62] - take_ext_int_start_d2 <= _T_676 @[dec_tlu_ctl.scala 745:30] - reg _T_677 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 746:62] - _T_677 <= take_ext_int_start_d2 @[dec_tlu_ctl.scala 746:62] - take_ext_int_start_d3 <= _T_677 @[dec_tlu_ctl.scala 746:30] - reg _T_678 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 747:66] - _T_678 <= ext_int_freeze @[dec_tlu_ctl.scala 747:66] - ext_int_freeze_d1 <= _T_678 @[dec_tlu_ctl.scala 747:34] - node _T_679 = not(block_interrupts) @[dec_tlu_ctl.scala 748:47] - node _T_680 = and(ext_int_ready, _T_679) @[dec_tlu_ctl.scala 748:45] - take_ext_int_start <= _T_680 @[dec_tlu_ctl.scala 748:28] - node _T_681 = or(take_ext_int_start, take_ext_int_start_d1) @[dec_tlu_ctl.scala 750:46] - node _T_682 = or(_T_681, take_ext_int_start_d2) @[dec_tlu_ctl.scala 750:70] - node _T_683 = or(_T_682, take_ext_int_start_d3) @[dec_tlu_ctl.scala 750:94] - ext_int_freeze <= _T_683 @[dec_tlu_ctl.scala 750:24] - node _T_684 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 751:67] - node _T_685 = not(_T_684) @[dec_tlu_ctl.scala 751:49] - node _T_686 = and(take_ext_int_start_d3, _T_685) @[dec_tlu_ctl.scala 751:47] - take_ext_int <= _T_686 @[dec_tlu_ctl.scala 751:22] - node _T_687 = and(csr_pkt.csr_meicpct, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 752:49] - fast_int_meicpct <= _T_687 @[dec_tlu_ctl.scala 752:26] - ignore_ext_int_due_to_lsu_stall <= io.lsu_fastint_stall_any @[dec_tlu_ctl.scala 753:41] - node _T_688 = not(ext_int_ready) @[dec_tlu_ctl.scala 766:35] - node _T_689 = and(ce_int_ready, _T_688) @[dec_tlu_ctl.scala 766:33] - node _T_690 = not(block_interrupts) @[dec_tlu_ctl.scala 766:52] - node _T_691 = and(_T_689, _T_690) @[dec_tlu_ctl.scala 766:50] - take_ce_int <= _T_691 @[dec_tlu_ctl.scala 766:17] - node _T_692 = not(ext_int_ready) @[dec_tlu_ctl.scala 767:38] - node _T_693 = and(soft_int_ready, _T_692) @[dec_tlu_ctl.scala 767:36] - node _T_694 = not(ce_int_ready) @[dec_tlu_ctl.scala 767:55] - node _T_695 = and(_T_693, _T_694) @[dec_tlu_ctl.scala 767:53] - node _T_696 = not(block_interrupts) @[dec_tlu_ctl.scala 767:71] - node _T_697 = and(_T_695, _T_696) @[dec_tlu_ctl.scala 767:69] - take_soft_int <= _T_697 @[dec_tlu_ctl.scala 767:18] - node _T_698 = not(soft_int_ready) @[dec_tlu_ctl.scala 768:40] - node _T_699 = and(timer_int_ready, _T_698) @[dec_tlu_ctl.scala 768:38] - node _T_700 = not(ext_int_ready) @[dec_tlu_ctl.scala 768:58] - node _T_701 = and(_T_699, _T_700) @[dec_tlu_ctl.scala 768:56] - node _T_702 = not(ce_int_ready) @[dec_tlu_ctl.scala 768:75] - node _T_703 = and(_T_701, _T_702) @[dec_tlu_ctl.scala 768:73] - node _T_704 = not(block_interrupts) @[dec_tlu_ctl.scala 768:91] - node _T_705 = and(_T_703, _T_704) @[dec_tlu_ctl.scala 768:89] - take_timer_int <= _T_705 @[dec_tlu_ctl.scala 768:19] - node _T_706 = or(int_timer0_int_ready, int_timer0_int_hold_f) @[dec_tlu_ctl.scala 769:49] - node _T_707 = and(_T_706, int_timer0_int_possible) @[dec_tlu_ctl.scala 769:74] - node _T_708 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 769:102] - node _T_709 = and(_T_707, _T_708) @[dec_tlu_ctl.scala 769:100] - node _T_710 = not(timer_int_ready) @[dec_tlu_ctl.scala 769:129] - node _T_711 = and(_T_709, _T_710) @[dec_tlu_ctl.scala 769:127] - node _T_712 = not(soft_int_ready) @[dec_tlu_ctl.scala 769:148] - node _T_713 = and(_T_711, _T_712) @[dec_tlu_ctl.scala 769:146] - node _T_714 = not(ext_int_ready) @[dec_tlu_ctl.scala 769:166] - node _T_715 = and(_T_713, _T_714) @[dec_tlu_ctl.scala 769:164] - node _T_716 = not(ce_int_ready) @[dec_tlu_ctl.scala 769:183] - node _T_717 = and(_T_715, _T_716) @[dec_tlu_ctl.scala 769:181] - node _T_718 = not(block_interrupts) @[dec_tlu_ctl.scala 769:199] - node _T_719 = and(_T_717, _T_718) @[dec_tlu_ctl.scala 769:197] - take_int_timer0_int <= _T_719 @[dec_tlu_ctl.scala 769:24] - node _T_720 = or(int_timer1_int_ready, int_timer1_int_hold_f) @[dec_tlu_ctl.scala 770:49] - node _T_721 = and(_T_720, int_timer1_int_possible) @[dec_tlu_ctl.scala 770:74] - node _T_722 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 770:102] - node _T_723 = and(_T_721, _T_722) @[dec_tlu_ctl.scala 770:100] - node _T_724 = or(int_timer0_int_ready, int_timer0_int_hold_f) @[dec_tlu_ctl.scala 770:152] - node _T_725 = not(_T_724) @[dec_tlu_ctl.scala 770:129] - node _T_726 = and(_T_723, _T_725) @[dec_tlu_ctl.scala 770:127] - node _T_727 = not(timer_int_ready) @[dec_tlu_ctl.scala 770:179] - node _T_728 = and(_T_726, _T_727) @[dec_tlu_ctl.scala 770:177] - node _T_729 = not(soft_int_ready) @[dec_tlu_ctl.scala 770:198] - node _T_730 = and(_T_728, _T_729) @[dec_tlu_ctl.scala 770:196] - node _T_731 = not(ext_int_ready) @[dec_tlu_ctl.scala 770:216] - node _T_732 = and(_T_730, _T_731) @[dec_tlu_ctl.scala 770:214] - node _T_733 = not(ce_int_ready) @[dec_tlu_ctl.scala 770:233] - node _T_734 = and(_T_732, _T_733) @[dec_tlu_ctl.scala 770:231] - node _T_735 = not(block_interrupts) @[dec_tlu_ctl.scala 770:249] - node _T_736 = and(_T_734, _T_735) @[dec_tlu_ctl.scala 770:247] - take_int_timer1_int <= _T_736 @[dec_tlu_ctl.scala 770:24] - node _T_737 = and(reset_delayed, io.mpc_reset_run_req) @[dec_tlu_ctl.scala 771:32] - take_reset <= _T_737 @[dec_tlu_ctl.scala 771:15] - node _T_738 = not(internal_pmu_fw_halt_mode) @[dec_tlu_ctl.scala 772:35] - node _T_739 = and(nmi_int_detected, _T_738) @[dec_tlu_ctl.scala 772:33] - node _T_740 = not(internal_dbg_halt_mode) @[dec_tlu_ctl.scala 772:65] - node _T_741 = bits(dcsr, 11, 11) @[dec_tlu_ctl.scala 772:125] - node _T_742 = and(dcsr_single_step_running_f, _T_741) @[dec_tlu_ctl.scala 772:119] - node _T_743 = not(io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 772:141] - node _T_744 = and(_T_742, _T_743) @[dec_tlu_ctl.scala 772:139] - node _T_745 = not(dcsr_single_step_done_f) @[dec_tlu_ctl.scala 772:166] - node _T_746 = and(_T_744, _T_745) @[dec_tlu_ctl.scala 772:164] - node _T_747 = or(_T_740, _T_746) @[dec_tlu_ctl.scala 772:89] - node _T_748 = and(_T_739, _T_747) @[dec_tlu_ctl.scala 772:62] - node _T_749 = not(synchronous_flush_r) @[dec_tlu_ctl.scala 772:195] - node _T_750 = and(_T_748, _T_749) @[dec_tlu_ctl.scala 772:193] - node _T_751 = not(mret_r) @[dec_tlu_ctl.scala 772:218] - node _T_752 = and(_T_750, _T_751) @[dec_tlu_ctl.scala 772:216] - node _T_753 = not(take_reset) @[dec_tlu_ctl.scala 772:228] - node _T_754 = and(_T_752, _T_753) @[dec_tlu_ctl.scala 772:226] - node _T_755 = not(ebreak_to_debug_mode_r) @[dec_tlu_ctl.scala 772:242] - node _T_756 = and(_T_754, _T_755) @[dec_tlu_ctl.scala 772:240] - node _T_757 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 772:269] - node _T_758 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 772:332] - node _T_759 = and(take_ext_int_start_d3, _T_758) @[dec_tlu_ctl.scala 772:313] - node _T_760 = or(_T_757, _T_759) @[dec_tlu_ctl.scala 772:288] - node _T_761 = and(_T_756, _T_760) @[dec_tlu_ctl.scala 772:266] - take_nmi <= _T_761 @[dec_tlu_ctl.scala 772:13] - node _T_762 = or(take_ext_int, take_timer_int) @[dec_tlu_ctl.scala 775:38] - node _T_763 = or(_T_762, take_soft_int) @[dec_tlu_ctl.scala 775:55] - node _T_764 = or(_T_763, take_nmi) @[dec_tlu_ctl.scala 775:71] - node _T_765 = or(_T_764, take_ce_int) @[dec_tlu_ctl.scala 775:82] - node _T_766 = or(_T_765, take_int_timer0_int) @[dec_tlu_ctl.scala 775:96] - node _T_767 = or(_T_766, take_int_timer1_int) @[dec_tlu_ctl.scala 775:118] - interrupt_valid_r <= _T_767 @[dec_tlu_ctl.scala 775:22] - node _T_768 = bits(mtvec, 30, 1) @[dec_tlu_ctl.scala 780:34] + node _T_605 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 717:24] + node _T_606 = and(_T_605, mstatus_mie_ns) @[dec_tlu_ctl.scala 717:49] + node _T_607 = bits(mip, 2, 2) @[dec_tlu_ctl.scala 717:71] + node _T_608 = and(_T_606, _T_607) @[dec_tlu_ctl.scala 717:66] + node _T_609 = bits(mie_ns, 2, 2) @[dec_tlu_ctl.scala 717:92] + node _T_610 = and(_T_608, _T_609) @[dec_tlu_ctl.scala 717:84] + mhwakeup_ready <= _T_610 @[dec_tlu_ctl.scala 717:20] + node _T_611 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 718:23] + node _T_612 = and(_T_611, mstatus_mie_ns) @[dec_tlu_ctl.scala 718:48] + node _T_613 = bits(mip, 2, 2) @[dec_tlu_ctl.scala 718:70] + node _T_614 = and(_T_612, _T_613) @[dec_tlu_ctl.scala 718:65] + node _T_615 = bits(mie_ns, 2, 2) @[dec_tlu_ctl.scala 718:91] + node _T_616 = and(_T_614, _T_615) @[dec_tlu_ctl.scala 718:83] + node _T_617 = not(ignore_ext_int_due_to_lsu_stall) @[dec_tlu_ctl.scala 718:104] + node _T_618 = and(_T_616, _T_617) @[dec_tlu_ctl.scala 718:102] + ext_int_ready <= _T_618 @[dec_tlu_ctl.scala 718:20] + node _T_619 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 719:23] + node _T_620 = and(_T_619, mstatus_mie_ns) @[dec_tlu_ctl.scala 719:48] + node _T_621 = bits(mip, 5, 5) @[dec_tlu_ctl.scala 719:70] + node _T_622 = and(_T_620, _T_621) @[dec_tlu_ctl.scala 719:65] + node _T_623 = bits(mie_ns, 5, 5) @[dec_tlu_ctl.scala 719:91] + node _T_624 = and(_T_622, _T_623) @[dec_tlu_ctl.scala 719:83] + ce_int_ready <= _T_624 @[dec_tlu_ctl.scala 719:20] + node _T_625 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 720:23] + node _T_626 = and(_T_625, mstatus_mie_ns) @[dec_tlu_ctl.scala 720:48] + node _T_627 = bits(mip, 0, 0) @[dec_tlu_ctl.scala 720:70] + node _T_628 = and(_T_626, _T_627) @[dec_tlu_ctl.scala 720:65] + node _T_629 = bits(mie_ns, 0, 0) @[dec_tlu_ctl.scala 720:91] + node _T_630 = and(_T_628, _T_629) @[dec_tlu_ctl.scala 720:83] + soft_int_ready <= _T_630 @[dec_tlu_ctl.scala 720:20] + node _T_631 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 721:23] + node _T_632 = and(_T_631, mstatus_mie_ns) @[dec_tlu_ctl.scala 721:48] + node _T_633 = bits(mip, 1, 1) @[dec_tlu_ctl.scala 721:70] + node _T_634 = and(_T_632, _T_633) @[dec_tlu_ctl.scala 721:65] + node _T_635 = bits(mie_ns, 1, 1) @[dec_tlu_ctl.scala 721:91] + node _T_636 = and(_T_634, _T_635) @[dec_tlu_ctl.scala 721:83] + timer_int_ready <= _T_636 @[dec_tlu_ctl.scala 721:20] + node _T_637 = bits(mie_ns, 4, 4) @[dec_tlu_ctl.scala 724:57] + node int_timer0_int_possible = and(mstatus_mie_ns, _T_637) @[dec_tlu_ctl.scala 724:49] + node _T_638 = bits(mip, 4, 4) @[dec_tlu_ctl.scala 725:34] + node int_timer0_int_ready = and(_T_638, int_timer0_int_possible) @[dec_tlu_ctl.scala 725:47] + node _T_639 = bits(mie_ns, 3, 3) @[dec_tlu_ctl.scala 726:57] + node int_timer1_int_possible = and(mstatus_mie_ns, _T_639) @[dec_tlu_ctl.scala 726:49] + node _T_640 = bits(mip, 3, 3) @[dec_tlu_ctl.scala 727:34] + node int_timer1_int_ready = and(_T_640, int_timer1_int_possible) @[dec_tlu_ctl.scala 727:47] + node _T_641 = or(io.dec_csr_stall_int_ff, synchronous_flush_r) @[dec_tlu_ctl.scala 731:52] + node _T_642 = or(_T_641, exc_or_int_valid_r_d1) @[dec_tlu_ctl.scala 731:74] + node int_timer_stalled = or(_T_642, mret_r) @[dec_tlu_ctl.scala 731:98] + node _T_643 = or(pmu_fw_tlu_halted_f, int_timer_stalled) @[dec_tlu_ctl.scala 733:72] + node _T_644 = and(int_timer0_int_ready, _T_643) @[dec_tlu_ctl.scala 733:49] + node _T_645 = and(int_timer0_int_possible, int_timer0_int_hold_f) @[dec_tlu_ctl.scala 733:121] + node _T_646 = not(interrupt_valid_r) @[dec_tlu_ctl.scala 733:147] + node _T_647 = and(_T_645, _T_646) @[dec_tlu_ctl.scala 733:145] + node _T_648 = not(take_ext_int_start) @[dec_tlu_ctl.scala 733:168] + node _T_649 = and(_T_647, _T_648) @[dec_tlu_ctl.scala 733:166] + node _T_650 = not(debug_mode_status) @[dec_tlu_ctl.scala 733:190] + node _T_651 = and(_T_649, _T_650) @[dec_tlu_ctl.scala 733:188] + node _T_652 = or(_T_644, _T_651) @[dec_tlu_ctl.scala 733:94] + int_timer0_int_hold <= _T_652 @[dec_tlu_ctl.scala 733:24] + node _T_653 = or(pmu_fw_tlu_halted_f, int_timer_stalled) @[dec_tlu_ctl.scala 734:72] + node _T_654 = and(int_timer1_int_ready, _T_653) @[dec_tlu_ctl.scala 734:49] + node _T_655 = and(int_timer1_int_possible, int_timer1_int_hold_f) @[dec_tlu_ctl.scala 734:121] + node _T_656 = not(interrupt_valid_r) @[dec_tlu_ctl.scala 734:147] + node _T_657 = and(_T_655, _T_656) @[dec_tlu_ctl.scala 734:145] + node _T_658 = not(take_ext_int_start) @[dec_tlu_ctl.scala 734:168] + node _T_659 = and(_T_657, _T_658) @[dec_tlu_ctl.scala 734:166] + node _T_660 = not(debug_mode_status) @[dec_tlu_ctl.scala 734:190] + node _T_661 = and(_T_659, _T_660) @[dec_tlu_ctl.scala 734:188] + node _T_662 = or(_T_654, _T_661) @[dec_tlu_ctl.scala 734:94] + int_timer1_int_hold <= _T_662 @[dec_tlu_ctl.scala 734:24] + node _T_663 = not(dcsr_single_step_running) @[dec_tlu_ctl.scala 736:59] + node _T_664 = and(debug_mode_status, _T_663) @[dec_tlu_ctl.scala 736:57] + internal_dbg_halt_timers <= _T_664 @[dec_tlu_ctl.scala 736:29] + node _T_665 = not(dcsr_single_step_running) @[dec_tlu_ctl.scala 738:55] + node _T_666 = or(_T_665, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 738:81] + node _T_667 = and(internal_dbg_halt_mode, _T_666) @[dec_tlu_ctl.scala 738:52] + node _T_668 = or(_T_667, internal_pmu_fw_halt_mode) @[dec_tlu_ctl.scala 738:107] + node _T_669 = or(_T_668, i_cpu_halt_req_d1) @[dec_tlu_ctl.scala 738:135] + node _T_670 = or(_T_669, take_nmi) @[dec_tlu_ctl.scala 738:155] + node _T_671 = or(_T_670, ebreak_to_debug_mode_r) @[dec_tlu_ctl.scala 738:166] + node _T_672 = or(_T_671, synchronous_flush_r) @[dec_tlu_ctl.scala 738:191] + node _T_673 = or(_T_672, exc_or_int_valid_r_d1) @[dec_tlu_ctl.scala 738:214] + node _T_674 = or(_T_673, mret_r) @[dec_tlu_ctl.scala 738:238] + node block_interrupts = or(_T_674, ext_int_freeze_d1) @[dec_tlu_ctl.scala 738:247] + reg _T_675 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 742:62] + _T_675 <= take_ext_int_start @[dec_tlu_ctl.scala 742:62] + take_ext_int_start_d1 <= _T_675 @[dec_tlu_ctl.scala 742:30] + reg _T_676 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 743:62] + _T_676 <= take_ext_int_start_d1 @[dec_tlu_ctl.scala 743:62] + take_ext_int_start_d2 <= _T_676 @[dec_tlu_ctl.scala 743:30] + reg _T_677 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 744:62] + _T_677 <= take_ext_int_start_d2 @[dec_tlu_ctl.scala 744:62] + take_ext_int_start_d3 <= _T_677 @[dec_tlu_ctl.scala 744:30] + reg _T_678 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 745:66] + _T_678 <= ext_int_freeze @[dec_tlu_ctl.scala 745:66] + ext_int_freeze_d1 <= _T_678 @[dec_tlu_ctl.scala 745:34] + node _T_679 = not(block_interrupts) @[dec_tlu_ctl.scala 746:47] + node _T_680 = and(ext_int_ready, _T_679) @[dec_tlu_ctl.scala 746:45] + take_ext_int_start <= _T_680 @[dec_tlu_ctl.scala 746:28] + node _T_681 = or(take_ext_int_start, take_ext_int_start_d1) @[dec_tlu_ctl.scala 748:46] + node _T_682 = or(_T_681, take_ext_int_start_d2) @[dec_tlu_ctl.scala 748:70] + node _T_683 = or(_T_682, take_ext_int_start_d3) @[dec_tlu_ctl.scala 748:94] + ext_int_freeze <= _T_683 @[dec_tlu_ctl.scala 748:24] + node _T_684 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 749:67] + node _T_685 = not(_T_684) @[dec_tlu_ctl.scala 749:49] + node _T_686 = and(take_ext_int_start_d3, _T_685) @[dec_tlu_ctl.scala 749:47] + take_ext_int <= _T_686 @[dec_tlu_ctl.scala 749:22] + node _T_687 = and(csr_pkt.csr_meicpct, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 750:49] + fast_int_meicpct <= _T_687 @[dec_tlu_ctl.scala 750:26] + ignore_ext_int_due_to_lsu_stall <= io.lsu_fastint_stall_any @[dec_tlu_ctl.scala 751:41] + node _T_688 = not(ext_int_ready) @[dec_tlu_ctl.scala 764:35] + node _T_689 = and(ce_int_ready, _T_688) @[dec_tlu_ctl.scala 764:33] + node _T_690 = not(block_interrupts) @[dec_tlu_ctl.scala 764:52] + node _T_691 = and(_T_689, _T_690) @[dec_tlu_ctl.scala 764:50] + take_ce_int <= _T_691 @[dec_tlu_ctl.scala 764:17] + node _T_692 = not(ext_int_ready) @[dec_tlu_ctl.scala 765:38] + node _T_693 = and(soft_int_ready, _T_692) @[dec_tlu_ctl.scala 765:36] + node _T_694 = not(ce_int_ready) @[dec_tlu_ctl.scala 765:55] + node _T_695 = and(_T_693, _T_694) @[dec_tlu_ctl.scala 765:53] + node _T_696 = not(block_interrupts) @[dec_tlu_ctl.scala 765:71] + node _T_697 = and(_T_695, _T_696) @[dec_tlu_ctl.scala 765:69] + take_soft_int <= _T_697 @[dec_tlu_ctl.scala 765:18] + node _T_698 = not(soft_int_ready) @[dec_tlu_ctl.scala 766:40] + node _T_699 = and(timer_int_ready, _T_698) @[dec_tlu_ctl.scala 766:38] + node _T_700 = not(ext_int_ready) @[dec_tlu_ctl.scala 766:58] + node _T_701 = and(_T_699, _T_700) @[dec_tlu_ctl.scala 766:56] + node _T_702 = not(ce_int_ready) @[dec_tlu_ctl.scala 766:75] + node _T_703 = and(_T_701, _T_702) @[dec_tlu_ctl.scala 766:73] + node _T_704 = not(block_interrupts) @[dec_tlu_ctl.scala 766:91] + node _T_705 = and(_T_703, _T_704) @[dec_tlu_ctl.scala 766:89] + take_timer_int <= _T_705 @[dec_tlu_ctl.scala 766:19] + node _T_706 = or(int_timer0_int_ready, int_timer0_int_hold_f) @[dec_tlu_ctl.scala 767:49] + node _T_707 = and(_T_706, int_timer0_int_possible) @[dec_tlu_ctl.scala 767:74] + node _T_708 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 767:102] + node _T_709 = and(_T_707, _T_708) @[dec_tlu_ctl.scala 767:100] + node _T_710 = not(timer_int_ready) @[dec_tlu_ctl.scala 767:129] + node _T_711 = and(_T_709, _T_710) @[dec_tlu_ctl.scala 767:127] + node _T_712 = not(soft_int_ready) @[dec_tlu_ctl.scala 767:148] + node _T_713 = and(_T_711, _T_712) @[dec_tlu_ctl.scala 767:146] + node _T_714 = not(ext_int_ready) @[dec_tlu_ctl.scala 767:166] + node _T_715 = and(_T_713, _T_714) @[dec_tlu_ctl.scala 767:164] + node _T_716 = not(ce_int_ready) @[dec_tlu_ctl.scala 767:183] + node _T_717 = and(_T_715, _T_716) @[dec_tlu_ctl.scala 767:181] + node _T_718 = not(block_interrupts) @[dec_tlu_ctl.scala 767:199] + node _T_719 = and(_T_717, _T_718) @[dec_tlu_ctl.scala 767:197] + take_int_timer0_int <= _T_719 @[dec_tlu_ctl.scala 767:24] + node _T_720 = or(int_timer1_int_ready, int_timer1_int_hold_f) @[dec_tlu_ctl.scala 768:49] + node _T_721 = and(_T_720, int_timer1_int_possible) @[dec_tlu_ctl.scala 768:74] + node _T_722 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 768:102] + node _T_723 = and(_T_721, _T_722) @[dec_tlu_ctl.scala 768:100] + node _T_724 = or(int_timer0_int_ready, int_timer0_int_hold_f) @[dec_tlu_ctl.scala 768:152] + node _T_725 = not(_T_724) @[dec_tlu_ctl.scala 768:129] + node _T_726 = and(_T_723, _T_725) @[dec_tlu_ctl.scala 768:127] + node _T_727 = not(timer_int_ready) @[dec_tlu_ctl.scala 768:179] + node _T_728 = and(_T_726, _T_727) @[dec_tlu_ctl.scala 768:177] + node _T_729 = not(soft_int_ready) @[dec_tlu_ctl.scala 768:198] + node _T_730 = and(_T_728, _T_729) @[dec_tlu_ctl.scala 768:196] + node _T_731 = not(ext_int_ready) @[dec_tlu_ctl.scala 768:216] + node _T_732 = and(_T_730, _T_731) @[dec_tlu_ctl.scala 768:214] + node _T_733 = not(ce_int_ready) @[dec_tlu_ctl.scala 768:233] + node _T_734 = and(_T_732, _T_733) @[dec_tlu_ctl.scala 768:231] + node _T_735 = not(block_interrupts) @[dec_tlu_ctl.scala 768:249] + node _T_736 = and(_T_734, _T_735) @[dec_tlu_ctl.scala 768:247] + take_int_timer1_int <= _T_736 @[dec_tlu_ctl.scala 768:24] + node _T_737 = and(reset_delayed, io.mpc_reset_run_req) @[dec_tlu_ctl.scala 769:32] + take_reset <= _T_737 @[dec_tlu_ctl.scala 769:15] + node _T_738 = not(internal_pmu_fw_halt_mode) @[dec_tlu_ctl.scala 770:35] + node _T_739 = and(nmi_int_detected, _T_738) @[dec_tlu_ctl.scala 770:33] + node _T_740 = not(internal_dbg_halt_mode) @[dec_tlu_ctl.scala 770:65] + node _T_741 = bits(dcsr, 11, 11) @[dec_tlu_ctl.scala 770:125] + node _T_742 = and(dcsr_single_step_running_f, _T_741) @[dec_tlu_ctl.scala 770:119] + node _T_743 = not(io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 770:141] + node _T_744 = and(_T_742, _T_743) @[dec_tlu_ctl.scala 770:139] + node _T_745 = not(dcsr_single_step_done_f) @[dec_tlu_ctl.scala 770:166] + node _T_746 = and(_T_744, _T_745) @[dec_tlu_ctl.scala 770:164] + node _T_747 = or(_T_740, _T_746) @[dec_tlu_ctl.scala 770:89] + node _T_748 = and(_T_739, _T_747) @[dec_tlu_ctl.scala 770:62] + node _T_749 = not(synchronous_flush_r) @[dec_tlu_ctl.scala 770:195] + node _T_750 = and(_T_748, _T_749) @[dec_tlu_ctl.scala 770:193] + node _T_751 = not(mret_r) @[dec_tlu_ctl.scala 770:218] + node _T_752 = and(_T_750, _T_751) @[dec_tlu_ctl.scala 770:216] + node _T_753 = not(take_reset) @[dec_tlu_ctl.scala 770:228] + node _T_754 = and(_T_752, _T_753) @[dec_tlu_ctl.scala 770:226] + node _T_755 = not(ebreak_to_debug_mode_r) @[dec_tlu_ctl.scala 770:242] + node _T_756 = and(_T_754, _T_755) @[dec_tlu_ctl.scala 770:240] + node _T_757 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 770:269] + node _T_758 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 770:332] + node _T_759 = and(take_ext_int_start_d3, _T_758) @[dec_tlu_ctl.scala 770:313] + node _T_760 = or(_T_757, _T_759) @[dec_tlu_ctl.scala 770:288] + node _T_761 = and(_T_756, _T_760) @[dec_tlu_ctl.scala 770:266] + take_nmi <= _T_761 @[dec_tlu_ctl.scala 770:13] + node _T_762 = or(take_ext_int, take_timer_int) @[dec_tlu_ctl.scala 773:38] + node _T_763 = or(_T_762, take_soft_int) @[dec_tlu_ctl.scala 773:55] + node _T_764 = or(_T_763, take_nmi) @[dec_tlu_ctl.scala 773:71] + node _T_765 = or(_T_764, take_ce_int) @[dec_tlu_ctl.scala 773:82] + node _T_766 = or(_T_765, take_int_timer0_int) @[dec_tlu_ctl.scala 773:96] + node _T_767 = or(_T_766, take_int_timer1_int) @[dec_tlu_ctl.scala 773:118] + interrupt_valid_r <= _T_767 @[dec_tlu_ctl.scala 773:22] + node _T_768 = bits(mtvec, 30, 1) @[dec_tlu_ctl.scala 778:34] node _T_769 = cat(_T_768, UInt<1>("h00")) @[Cat.scala 29:58] node _T_770 = cat(UInt<25>("h00"), exc_cause_r) @[Cat.scala 29:58] node _T_771 = cat(_T_770, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_772 = add(_T_769, _T_771) @[dec_tlu_ctl.scala 780:51] - node vectored_path = tail(_T_772, 1) @[dec_tlu_ctl.scala 780:51] - node _T_773 = bits(take_nmi, 0, 0) @[dec_tlu_ctl.scala 781:38] - node _T_774 = bits(mtvec, 0, 0) @[dec_tlu_ctl.scala 781:67] - node _T_775 = eq(_T_774, UInt<1>("h01")) @[dec_tlu_ctl.scala 781:71] - node _T_776 = bits(mtvec, 30, 1) @[dec_tlu_ctl.scala 781:104] + node _T_772 = add(_T_769, _T_771) @[dec_tlu_ctl.scala 778:51] + node vectored_path = tail(_T_772, 1) @[dec_tlu_ctl.scala 778:51] + node _T_773 = bits(take_nmi, 0, 0) @[dec_tlu_ctl.scala 779:38] + node _T_774 = bits(mtvec, 0, 0) @[dec_tlu_ctl.scala 779:67] + node _T_775 = eq(_T_774, UInt<1>("h01")) @[dec_tlu_ctl.scala 779:71] + node _T_776 = bits(mtvec, 30, 1) @[dec_tlu_ctl.scala 779:104] node _T_777 = cat(_T_776, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_778 = mux(_T_775, vectored_path, _T_777) @[dec_tlu_ctl.scala 781:61] - node interrupt_path = mux(_T_773, io.nmi_vec, _T_778) @[dec_tlu_ctl.scala 781:28] - node _T_779 = or(lsu_i0_rfnpc_r, fence_i_r) @[dec_tlu_ctl.scala 782:36] - node _T_780 = or(_T_779, iccm_repair_state_rfnpc) @[dec_tlu_ctl.scala 782:48] - node _T_781 = not(interrupt_valid_r) @[dec_tlu_ctl.scala 782:96] - node _T_782 = and(i_cpu_run_req_d1, _T_781) @[dec_tlu_ctl.scala 782:94] - node _T_783 = or(_T_780, _T_782) @[dec_tlu_ctl.scala 782:74] - node _T_784 = not(io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 782:131] - node _T_785 = and(rfpc_i0_r, _T_784) @[dec_tlu_ctl.scala 782:129] - node sel_npc_r = or(_T_783, _T_785) @[dec_tlu_ctl.scala 782:116] - node _T_786 = and(i_cpu_run_req_d1, pmu_fw_tlu_halted_f) @[dec_tlu_ctl.scala 783:43] - node sel_npc_resume = or(_T_786, pause_expired_r) @[dec_tlu_ctl.scala 783:66] - node _T_787 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 784:65] - node _T_788 = not(_T_787) @[dec_tlu_ctl.scala 784:47] - node sel_fir_addr = and(take_ext_int_start_d3, _T_788) @[dec_tlu_ctl.scala 784:45] - node _T_789 = or(i0_exception_valid_r, rfpc_i0_r) @[dec_tlu_ctl.scala 785:49] - node _T_790 = or(_T_789, lsu_exc_valid_r) @[dec_tlu_ctl.scala 785:61] - node _T_791 = or(_T_790, fence_i_r) @[dec_tlu_ctl.scala 785:79] - node _T_792 = or(_T_791, lsu_i0_rfnpc_r) @[dec_tlu_ctl.scala 785:91] - node _T_793 = or(_T_792, iccm_repair_state_rfnpc) @[dec_tlu_ctl.scala 785:108] - node _T_794 = or(_T_793, debug_resume_req_f) @[dec_tlu_ctl.scala 785:135] - node _T_795 = or(_T_794, sel_npc_resume) @[dec_tlu_ctl.scala 785:157] - node _T_796 = or(_T_795, dec_tlu_wr_pause_r_d1) @[dec_tlu_ctl.scala 785:175] - node _T_797 = or(_T_796, i0_trigger_hit_r) @[dec_tlu_ctl.scala 785:201] - synchronous_flush_r <= _T_797 @[dec_tlu_ctl.scala 785:25] - node _T_798 = or(interrupt_valid_r, mret_r) @[dec_tlu_ctl.scala 786:43] - node _T_799 = or(_T_798, synchronous_flush_r) @[dec_tlu_ctl.scala 786:52] - node _T_800 = or(_T_799, take_halt) @[dec_tlu_ctl.scala 786:74] - node _T_801 = or(_T_800, take_reset) @[dec_tlu_ctl.scala 786:86] - node _T_802 = or(_T_801, take_ext_int_start) @[dec_tlu_ctl.scala 786:99] - tlu_flush_lower_r <= _T_802 @[dec_tlu_ctl.scala 786:22] - node _T_803 = bits(take_reset, 0, 0) @[dec_tlu_ctl.scala 788:42] - node _T_804 = bits(sel_fir_addr, 0, 0) @[dec_tlu_ctl.scala 789:72] - node _T_805 = eq(take_nmi, UInt<1>("h00")) @[dec_tlu_ctl.scala 790:66] - node _T_806 = eq(sel_npc_r, UInt<1>("h01")) @[dec_tlu_ctl.scala 790:84] - node _T_807 = and(_T_805, _T_806) @[dec_tlu_ctl.scala 790:73] - node _T_808 = eq(take_nmi, UInt<1>("h00")) @[dec_tlu_ctl.scala 791:66] - node _T_809 = eq(rfpc_i0_r, UInt<1>("h01")) @[dec_tlu_ctl.scala 791:84] - node _T_810 = and(_T_808, _T_809) @[dec_tlu_ctl.scala 791:73] - node _T_811 = eq(io.dec_tlu_i0_valid_r, UInt<1>("h01")) @[dec_tlu_ctl.scala 791:114] - node _T_812 = and(_T_810, _T_811) @[dec_tlu_ctl.scala 791:91] - node _T_813 = eq(sel_npc_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 791:132] - node _T_814 = and(_T_812, _T_813) @[dec_tlu_ctl.scala 791:121] - node _T_815 = eq(interrupt_valid_r, UInt<1>("h01")) @[dec_tlu_ctl.scala 792:75] - node _T_816 = eq(sel_fir_addr, UInt<1>("h00")) @[dec_tlu_ctl.scala 792:96] - node _T_817 = and(_T_815, _T_816) @[dec_tlu_ctl.scala 792:82] - node _T_818 = or(i0_exception_valid_r, lsu_exc_valid_r) @[dec_tlu_ctl.scala 793:80] - node _T_819 = not(trigger_hit_dmode_r) @[dec_tlu_ctl.scala 793:120] - node _T_820 = and(i0_trigger_hit_r, _T_819) @[dec_tlu_ctl.scala 793:118] - node _T_821 = or(_T_818, _T_820) @[dec_tlu_ctl.scala 793:98] - node _T_822 = not(interrupt_valid_r) @[dec_tlu_ctl.scala 793:145] - node _T_823 = and(_T_821, _T_822) @[dec_tlu_ctl.scala 793:143] - node _T_824 = not(sel_fir_addr) @[dec_tlu_ctl.scala 793:166] - node _T_825 = and(_T_823, _T_824) @[dec_tlu_ctl.scala 793:164] - node _T_826 = bits(_T_825, 0, 0) @[dec_tlu_ctl.scala 793:181] - node _T_827 = bits(mtvec, 30, 1) @[dec_tlu_ctl.scala 793:205] + node _T_778 = mux(_T_775, vectored_path, _T_777) @[dec_tlu_ctl.scala 779:61] + node interrupt_path = mux(_T_773, io.nmi_vec, _T_778) @[dec_tlu_ctl.scala 779:28] + node _T_779 = or(lsu_i0_rfnpc_r, fence_i_r) @[dec_tlu_ctl.scala 780:36] + node _T_780 = or(_T_779, iccm_repair_state_rfnpc) @[dec_tlu_ctl.scala 780:48] + node _T_781 = not(interrupt_valid_r) @[dec_tlu_ctl.scala 780:96] + node _T_782 = and(i_cpu_run_req_d1, _T_781) @[dec_tlu_ctl.scala 780:94] + node _T_783 = or(_T_780, _T_782) @[dec_tlu_ctl.scala 780:74] + node _T_784 = not(io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 780:131] + node _T_785 = and(rfpc_i0_r, _T_784) @[dec_tlu_ctl.scala 780:129] + node sel_npc_r = or(_T_783, _T_785) @[dec_tlu_ctl.scala 780:116] + node _T_786 = and(i_cpu_run_req_d1, pmu_fw_tlu_halted_f) @[dec_tlu_ctl.scala 781:43] + node sel_npc_resume = or(_T_786, pause_expired_r) @[dec_tlu_ctl.scala 781:66] + node _T_787 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 782:65] + node _T_788 = not(_T_787) @[dec_tlu_ctl.scala 782:47] + node sel_fir_addr = and(take_ext_int_start_d3, _T_788) @[dec_tlu_ctl.scala 782:45] + node _T_789 = or(i0_exception_valid_r, rfpc_i0_r) @[dec_tlu_ctl.scala 783:49] + node _T_790 = or(_T_789, lsu_exc_valid_r) @[dec_tlu_ctl.scala 783:61] + node _T_791 = or(_T_790, fence_i_r) @[dec_tlu_ctl.scala 783:79] + node _T_792 = or(_T_791, lsu_i0_rfnpc_r) @[dec_tlu_ctl.scala 783:91] + node _T_793 = or(_T_792, iccm_repair_state_rfnpc) @[dec_tlu_ctl.scala 783:108] + node _T_794 = or(_T_793, debug_resume_req_f) @[dec_tlu_ctl.scala 783:135] + node _T_795 = or(_T_794, sel_npc_resume) @[dec_tlu_ctl.scala 783:157] + node _T_796 = or(_T_795, dec_tlu_wr_pause_r_d1) @[dec_tlu_ctl.scala 783:175] + node _T_797 = or(_T_796, i0_trigger_hit_r) @[dec_tlu_ctl.scala 783:201] + synchronous_flush_r <= _T_797 @[dec_tlu_ctl.scala 783:25] + node _T_798 = or(interrupt_valid_r, mret_r) @[dec_tlu_ctl.scala 784:43] + node _T_799 = or(_T_798, synchronous_flush_r) @[dec_tlu_ctl.scala 784:52] + node _T_800 = or(_T_799, take_halt) @[dec_tlu_ctl.scala 784:74] + node _T_801 = or(_T_800, take_reset) @[dec_tlu_ctl.scala 784:86] + node _T_802 = or(_T_801, take_ext_int_start) @[dec_tlu_ctl.scala 784:99] + tlu_flush_lower_r <= _T_802 @[dec_tlu_ctl.scala 784:22] + node _T_803 = bits(take_reset, 0, 0) @[dec_tlu_ctl.scala 786:42] + node _T_804 = bits(sel_fir_addr, 0, 0) @[dec_tlu_ctl.scala 787:72] + node _T_805 = eq(take_nmi, UInt<1>("h00")) @[dec_tlu_ctl.scala 788:66] + node _T_806 = eq(sel_npc_r, UInt<1>("h01")) @[dec_tlu_ctl.scala 788:84] + node _T_807 = and(_T_805, _T_806) @[dec_tlu_ctl.scala 788:73] + node _T_808 = eq(take_nmi, UInt<1>("h00")) @[dec_tlu_ctl.scala 789:66] + node _T_809 = eq(rfpc_i0_r, UInt<1>("h01")) @[dec_tlu_ctl.scala 789:84] + node _T_810 = and(_T_808, _T_809) @[dec_tlu_ctl.scala 789:73] + node _T_811 = eq(io.dec_tlu_i0_valid_r, UInt<1>("h01")) @[dec_tlu_ctl.scala 789:114] + node _T_812 = and(_T_810, _T_811) @[dec_tlu_ctl.scala 789:91] + node _T_813 = eq(sel_npc_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 789:132] + node _T_814 = and(_T_812, _T_813) @[dec_tlu_ctl.scala 789:121] + node _T_815 = eq(interrupt_valid_r, UInt<1>("h01")) @[dec_tlu_ctl.scala 790:75] + node _T_816 = eq(sel_fir_addr, UInt<1>("h00")) @[dec_tlu_ctl.scala 790:96] + node _T_817 = and(_T_815, _T_816) @[dec_tlu_ctl.scala 790:82] + node _T_818 = or(i0_exception_valid_r, lsu_exc_valid_r) @[dec_tlu_ctl.scala 791:80] + node _T_819 = not(trigger_hit_dmode_r) @[dec_tlu_ctl.scala 791:120] + node _T_820 = and(i0_trigger_hit_r, _T_819) @[dec_tlu_ctl.scala 791:118] + node _T_821 = or(_T_818, _T_820) @[dec_tlu_ctl.scala 791:98] + node _T_822 = not(interrupt_valid_r) @[dec_tlu_ctl.scala 791:145] + node _T_823 = and(_T_821, _T_822) @[dec_tlu_ctl.scala 791:143] + node _T_824 = not(sel_fir_addr) @[dec_tlu_ctl.scala 791:166] + node _T_825 = and(_T_823, _T_824) @[dec_tlu_ctl.scala 791:164] + node _T_826 = bits(_T_825, 0, 0) @[dec_tlu_ctl.scala 791:181] + node _T_827 = bits(mtvec, 30, 1) @[dec_tlu_ctl.scala 791:205] node _T_828 = cat(_T_827, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_829 = not(take_nmi) @[dec_tlu_ctl.scala 794:58] - node _T_830 = and(_T_829, mret_r) @[dec_tlu_ctl.scala 794:68] - node _T_831 = bits(_T_830, 0, 0) @[dec_tlu_ctl.scala 794:78] - node _T_832 = not(take_nmi) @[dec_tlu_ctl.scala 795:58] - node _T_833 = and(_T_832, debug_resume_req_f) @[dec_tlu_ctl.scala 795:68] - node _T_834 = bits(_T_833, 0, 0) @[dec_tlu_ctl.scala 795:90] - node _T_835 = not(take_nmi) @[dec_tlu_ctl.scala 796:58] - node _T_836 = and(_T_835, sel_npc_resume) @[dec_tlu_ctl.scala 796:68] - node _T_837 = bits(_T_836, 0, 0) @[dec_tlu_ctl.scala 796:86] + node _T_829 = not(take_nmi) @[dec_tlu_ctl.scala 792:58] + node _T_830 = and(_T_829, mret_r) @[dec_tlu_ctl.scala 792:68] + node _T_831 = bits(_T_830, 0, 0) @[dec_tlu_ctl.scala 792:78] + node _T_832 = not(take_nmi) @[dec_tlu_ctl.scala 793:58] + node _T_833 = and(_T_832, debug_resume_req_f) @[dec_tlu_ctl.scala 793:68] + node _T_834 = bits(_T_833, 0, 0) @[dec_tlu_ctl.scala 793:90] + node _T_835 = not(take_nmi) @[dec_tlu_ctl.scala 794:58] + node _T_836 = and(_T_835, sel_npc_resume) @[dec_tlu_ctl.scala 794:68] + node _T_837 = bits(_T_836, 0, 0) @[dec_tlu_ctl.scala 794:86] node _T_838 = mux(_T_804, io.lsu_fir_addr, UInt<1>("h00")) @[Mux.scala 27:72] node _T_839 = mux(_T_807, npc_r, UInt<1>("h00")) @[Mux.scala 27:72] node _T_840 = mux(_T_814, io.dec_tlu_i0_pc_r, UInt<1>("h00")) @[Mux.scala 27:72] @@ -79274,461 +79284,461 @@ circuit quasar_wrapper : node _T_852 = or(_T_851, _T_845) @[Mux.scala 27:72] wire _T_853 : UInt<31> @[Mux.scala 27:72] _T_853 <= _T_852 @[Mux.scala 27:72] - node tlu_flush_path_r = mux(_T_803, io.rst_vec, _T_853) @[dec_tlu_ctl.scala 788:30] - reg tlu_flush_path_r_d1 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 799:64] - tlu_flush_path_r_d1 <= tlu_flush_path_r @[dec_tlu_ctl.scala 799:64] - io.dec_tlu_flush_lower_wb <= tlu_flush_lower_r_d1 @[dec_tlu_ctl.scala 801:41] - io.tlu_exu.dec_tlu_flush_lower_r <= tlu_flush_lower_r @[dec_tlu_ctl.scala 803:49] - io.tlu_exu.dec_tlu_flush_path_r <= tlu_flush_path_r @[dec_tlu_ctl.scala 804:49] - node _T_854 = or(lsu_exc_valid_r, i0_exception_valid_r) @[dec_tlu_ctl.scala 807:45] - node _T_855 = or(_T_854, interrupt_valid_r) @[dec_tlu_ctl.scala 807:68] - node _T_856 = not(trigger_hit_dmode_r) @[dec_tlu_ctl.scala 807:110] - node _T_857 = and(i0_trigger_hit_r, _T_856) @[dec_tlu_ctl.scala 807:108] - node exc_or_int_valid_r = or(_T_855, _T_857) @[dec_tlu_ctl.scala 807:88] - reg _T_858 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 809:90] - _T_858 <= interrupt_valid_r @[dec_tlu_ctl.scala 809:90] - interrupt_valid_r_d1 <= _T_858 @[dec_tlu_ctl.scala 809:57] - reg i0_exception_valid_r_d1 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 810:89] - i0_exception_valid_r_d1 <= i0_exception_valid_r @[dec_tlu_ctl.scala 810:89] - reg _T_859 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 811:90] - _T_859 <= exc_or_int_valid_r @[dec_tlu_ctl.scala 811:90] - exc_or_int_valid_r_d1 <= _T_859 @[dec_tlu_ctl.scala 811:57] - reg exc_cause_wb : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 812:89] - exc_cause_wb <= exc_cause_r @[dec_tlu_ctl.scala 812:89] - node _T_860 = not(illegal_r) @[dec_tlu_ctl.scala 813:119] - node _T_861 = and(tlu_i0_commit_cmt, _T_860) @[dec_tlu_ctl.scala 813:117] - reg i0_valid_wb : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 813:97] - i0_valid_wb <= _T_861 @[dec_tlu_ctl.scala 813:97] - reg trigger_hit_r_d1 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 814:89] - trigger_hit_r_d1 <= i0_trigger_hit_r @[dec_tlu_ctl.scala 814:89] - reg _T_862 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 815:98] - _T_862 <= take_nmi @[dec_tlu_ctl.scala 815:98] - take_nmi_r_d1 <= _T_862 @[dec_tlu_ctl.scala 815:65] - reg _T_863 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 816:90] - _T_863 <= pause_expired_r @[dec_tlu_ctl.scala 816:90] - pause_expired_wb <= _T_863 @[dec_tlu_ctl.scala 816:57] - inst csr of csr_tlu @[dec_tlu_ctl.scala 818:15] + node tlu_flush_path_r = mux(_T_803, io.rst_vec, _T_853) @[dec_tlu_ctl.scala 786:30] + reg tlu_flush_path_r_d1 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 797:64] + tlu_flush_path_r_d1 <= tlu_flush_path_r @[dec_tlu_ctl.scala 797:64] + io.dec_tlu_flush_lower_wb <= tlu_flush_lower_r_d1 @[dec_tlu_ctl.scala 799:41] + io.tlu_exu.dec_tlu_flush_lower_r <= tlu_flush_lower_r @[dec_tlu_ctl.scala 801:49] + io.tlu_exu.dec_tlu_flush_path_r <= tlu_flush_path_r @[dec_tlu_ctl.scala 802:49] + node _T_854 = or(lsu_exc_valid_r, i0_exception_valid_r) @[dec_tlu_ctl.scala 805:45] + node _T_855 = or(_T_854, interrupt_valid_r) @[dec_tlu_ctl.scala 805:68] + node _T_856 = not(trigger_hit_dmode_r) @[dec_tlu_ctl.scala 805:110] + node _T_857 = and(i0_trigger_hit_r, _T_856) @[dec_tlu_ctl.scala 805:108] + node exc_or_int_valid_r = or(_T_855, _T_857) @[dec_tlu_ctl.scala 805:88] + reg _T_858 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 807:90] + _T_858 <= interrupt_valid_r @[dec_tlu_ctl.scala 807:90] + interrupt_valid_r_d1 <= _T_858 @[dec_tlu_ctl.scala 807:57] + reg i0_exception_valid_r_d1 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 808:89] + i0_exception_valid_r_d1 <= i0_exception_valid_r @[dec_tlu_ctl.scala 808:89] + reg _T_859 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 809:90] + _T_859 <= exc_or_int_valid_r @[dec_tlu_ctl.scala 809:90] + exc_or_int_valid_r_d1 <= _T_859 @[dec_tlu_ctl.scala 809:57] + reg exc_cause_wb : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 810:89] + exc_cause_wb <= exc_cause_r @[dec_tlu_ctl.scala 810:89] + node _T_860 = not(illegal_r) @[dec_tlu_ctl.scala 811:119] + node _T_861 = and(tlu_i0_commit_cmt, _T_860) @[dec_tlu_ctl.scala 811:117] + reg i0_valid_wb : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 811:97] + i0_valid_wb <= _T_861 @[dec_tlu_ctl.scala 811:97] + reg trigger_hit_r_d1 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 812:89] + trigger_hit_r_d1 <= i0_trigger_hit_r @[dec_tlu_ctl.scala 812:89] + reg _T_862 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 813:98] + _T_862 <= take_nmi @[dec_tlu_ctl.scala 813:98] + take_nmi_r_d1 <= _T_862 @[dec_tlu_ctl.scala 813:65] + reg _T_863 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 814:90] + _T_863 <= pause_expired_r @[dec_tlu_ctl.scala 814:90] + pause_expired_wb <= _T_863 @[dec_tlu_ctl.scala 814:57] + inst csr of csr_tlu @[dec_tlu_ctl.scala 816:15] csr.clock <= clock csr.reset <= reset - csr.io.free_clk <= io.free_clk @[dec_tlu_ctl.scala 819:44] - csr.io.active_clk <= io.active_clk @[dec_tlu_ctl.scala 820:44] - csr.io.scan_mode <= io.scan_mode @[dec_tlu_ctl.scala 821:44] - csr.io.dec_csr_wrdata_r <= io.dec_csr_wrdata_r @[dec_tlu_ctl.scala 822:44] - csr.io.dec_csr_wraddr_r <= io.dec_csr_wraddr_r @[dec_tlu_ctl.scala 823:44] - csr.io.dec_csr_rdaddr_d <= io.dec_csr_rdaddr_d @[dec_tlu_ctl.scala 824:44] - csr.io.dec_csr_wen_unq_d <= io.dec_csr_wen_unq_d @[dec_tlu_ctl.scala 825:44] - csr.io.dec_i0_decode_d <= io.dec_i0_decode_d @[dec_tlu_ctl.scala 826:44] - csr.io.ifu_ic_debug_rd_data_valid <= io.tlu_mem.ifu_ic_debug_rd_data_valid @[dec_tlu_ctl.scala 827:44] - csr.io.ifu_pmu_bus_trxn <= io.tlu_mem.ifu_pmu_bus_trxn @[dec_tlu_ctl.scala 828:44] - csr.io.dma_iccm_stall_any <= io.tlu_dma.dma_iccm_stall_any @[dec_tlu_ctl.scala 829:44] - csr.io.dma_dccm_stall_any <= io.tlu_dma.dma_dccm_stall_any @[dec_tlu_ctl.scala 830:44] - csr.io.lsu_store_stall_any <= io.lsu_store_stall_any @[dec_tlu_ctl.scala 831:44] - csr.io.dec_pmu_presync_stall <= io.dec_pmu_presync_stall @[dec_tlu_ctl.scala 832:44] - csr.io.dec_pmu_postsync_stall <= io.dec_pmu_postsync_stall @[dec_tlu_ctl.scala 833:44] - csr.io.dec_pmu_decode_stall <= io.dec_pmu_decode_stall @[dec_tlu_ctl.scala 834:44] - csr.io.ifu_pmu_fetch_stall <= io.tlu_ifc.ifu_pmu_fetch_stall @[dec_tlu_ctl.scala 835:44] - csr.io.dec_tlu_packet_r.pmu_lsu_misaligned <= io.dec_tlu_packet_r.pmu_lsu_misaligned @[dec_tlu_ctl.scala 836:44] - csr.io.dec_tlu_packet_r.pmu_divide <= io.dec_tlu_packet_r.pmu_divide @[dec_tlu_ctl.scala 836:44] - csr.io.dec_tlu_packet_r.pmu_i0_br_unpred <= io.dec_tlu_packet_r.pmu_i0_br_unpred @[dec_tlu_ctl.scala 836:44] - csr.io.dec_tlu_packet_r.pmu_i0_itype <= io.dec_tlu_packet_r.pmu_i0_itype @[dec_tlu_ctl.scala 836:44] - csr.io.dec_tlu_packet_r.i0trigger <= io.dec_tlu_packet_r.i0trigger @[dec_tlu_ctl.scala 836:44] - csr.io.dec_tlu_packet_r.fence_i <= io.dec_tlu_packet_r.fence_i @[dec_tlu_ctl.scala 836:44] - csr.io.dec_tlu_packet_r.icaf_type <= io.dec_tlu_packet_r.icaf_type @[dec_tlu_ctl.scala 836:44] - csr.io.dec_tlu_packet_r.icaf_f1 <= io.dec_tlu_packet_r.icaf_f1 @[dec_tlu_ctl.scala 836:44] - csr.io.dec_tlu_packet_r.icaf <= io.dec_tlu_packet_r.icaf @[dec_tlu_ctl.scala 836:44] - csr.io.dec_tlu_packet_r.legal <= io.dec_tlu_packet_r.legal @[dec_tlu_ctl.scala 836:44] - csr.io.exu_pmu_i0_br_ataken <= io.tlu_exu.exu_pmu_i0_br_ataken @[dec_tlu_ctl.scala 837:44] - csr.io.exu_pmu_i0_br_misp <= io.tlu_exu.exu_pmu_i0_br_misp @[dec_tlu_ctl.scala 838:44] - csr.io.dec_pmu_instr_decoded <= io.dec_pmu_instr_decoded @[dec_tlu_ctl.scala 839:44] - csr.io.ifu_pmu_instr_aligned <= io.ifu_pmu_instr_aligned @[dec_tlu_ctl.scala 840:44] - csr.io.exu_pmu_i0_pc4 <= io.tlu_exu.exu_pmu_i0_pc4 @[dec_tlu_ctl.scala 841:44] - csr.io.ifu_pmu_ic_miss <= io.tlu_mem.ifu_pmu_ic_miss @[dec_tlu_ctl.scala 842:44] - csr.io.ifu_pmu_ic_hit <= io.tlu_mem.ifu_pmu_ic_hit @[dec_tlu_ctl.scala 843:44] - csr.io.dec_csr_wen_r <= io.dec_csr_wen_r @[dec_tlu_ctl.scala 844:44] - csr.io.dec_tlu_dbg_halted <= io.dec_tlu_dbg_halted @[dec_tlu_ctl.scala 845:44] - csr.io.dma_pmu_dccm_write <= io.tlu_dma.dma_pmu_dccm_write @[dec_tlu_ctl.scala 846:44] - csr.io.dma_pmu_dccm_read <= io.tlu_dma.dma_pmu_dccm_read @[dec_tlu_ctl.scala 847:44] - csr.io.dma_pmu_any_write <= io.tlu_dma.dma_pmu_any_write @[dec_tlu_ctl.scala 848:44] - csr.io.dma_pmu_any_read <= io.tlu_dma.dma_pmu_any_read @[dec_tlu_ctl.scala 849:44] - csr.io.lsu_pmu_bus_busy <= io.tlu_busbuff.lsu_pmu_bus_busy @[dec_tlu_ctl.scala 850:44] - csr.io.dec_tlu_i0_pc_r <= io.dec_tlu_i0_pc_r @[dec_tlu_ctl.scala 851:44] - csr.io.dec_tlu_i0_valid_r <= io.dec_tlu_i0_valid_r @[dec_tlu_ctl.scala 852:44] - csr.io.dec_csr_stall_int_ff <= io.dec_csr_stall_int_ff @[dec_tlu_ctl.scala 853:44] - csr.io.dec_csr_any_unq_d <= io.dec_csr_any_unq_d @[dec_tlu_ctl.scala 854:44] - csr.io.ifu_pmu_bus_busy <= io.tlu_mem.ifu_pmu_bus_busy @[dec_tlu_ctl.scala 855:44] - csr.io.lsu_pmu_bus_error <= io.tlu_busbuff.lsu_pmu_bus_error @[dec_tlu_ctl.scala 856:44] - csr.io.ifu_pmu_bus_error <= io.tlu_mem.ifu_pmu_bus_error @[dec_tlu_ctl.scala 857:44] - csr.io.lsu_pmu_bus_misaligned <= io.tlu_busbuff.lsu_pmu_bus_misaligned @[dec_tlu_ctl.scala 858:44] - csr.io.lsu_pmu_bus_trxn <= io.tlu_busbuff.lsu_pmu_bus_trxn @[dec_tlu_ctl.scala 859:44] - csr.io.ifu_ic_debug_rd_data <= io.tlu_mem.ifu_ic_debug_rd_data @[dec_tlu_ctl.scala 860:44] - csr.io.pic_pl <= io.dec_pic.pic_pl @[dec_tlu_ctl.scala 861:44] - csr.io.pic_claimid <= io.dec_pic.pic_claimid @[dec_tlu_ctl.scala 862:44] - csr.io.iccm_dma_sb_error <= io.iccm_dma_sb_error @[dec_tlu_ctl.scala 863:44] - csr.io.lsu_imprecise_error_addr_any <= io.tlu_busbuff.lsu_imprecise_error_addr_any @[dec_tlu_ctl.scala 864:44] - csr.io.lsu_imprecise_error_load_any <= io.tlu_busbuff.lsu_imprecise_error_load_any @[dec_tlu_ctl.scala 865:44] - csr.io.lsu_imprecise_error_store_any <= io.tlu_busbuff.lsu_imprecise_error_store_any @[dec_tlu_ctl.scala 866:44] - csr.io.dec_illegal_inst <= io.dec_illegal_inst @[dec_tlu_ctl.scala 867:44] - csr.io.lsu_error_pkt_r.bits.addr <= io.lsu_error_pkt_r.bits.addr @[dec_tlu_ctl.scala 868:44] - csr.io.lsu_error_pkt_r.bits.mscause <= io.lsu_error_pkt_r.bits.mscause @[dec_tlu_ctl.scala 868:44] - csr.io.lsu_error_pkt_r.bits.exc_type <= io.lsu_error_pkt_r.bits.exc_type @[dec_tlu_ctl.scala 868:44] - csr.io.lsu_error_pkt_r.bits.inst_type <= io.lsu_error_pkt_r.bits.inst_type @[dec_tlu_ctl.scala 868:44] - csr.io.lsu_error_pkt_r.bits.single_ecc_error <= io.lsu_error_pkt_r.bits.single_ecc_error @[dec_tlu_ctl.scala 868:44] - csr.io.lsu_error_pkt_r.valid <= io.lsu_error_pkt_r.valid @[dec_tlu_ctl.scala 868:44] - csr.io.mexintpend <= io.dec_pic.mexintpend @[dec_tlu_ctl.scala 869:44] - csr.io.exu_npc_r <= io.tlu_exu.exu_npc_r @[dec_tlu_ctl.scala 870:44] - csr.io.mpc_reset_run_req <= io.mpc_reset_run_req @[dec_tlu_ctl.scala 871:44] - csr.io.rst_vec <= io.rst_vec @[dec_tlu_ctl.scala 872:44] - csr.io.core_id <= io.core_id @[dec_tlu_ctl.scala 873:44] - csr.io.dec_timer_rddata_d <= int_timers.io.dec_timer_rddata_d @[dec_tlu_ctl.scala 874:44] - csr.io.dec_timer_read_d <= int_timers.io.dec_timer_read_d @[dec_tlu_ctl.scala 875:44] - io.dec_pic.dec_tlu_meicurpl <= csr.io.dec_tlu_meicurpl @[dec_tlu_ctl.scala 876:52] - io.tlu_exu.dec_tlu_meihap <= csr.io.dec_tlu_meihap @[dec_tlu_ctl.scala 877:52] - io.dec_pic.dec_tlu_meipt <= csr.io.dec_tlu_meipt @[dec_tlu_ctl.scala 878:52] - io.dec_tlu_int_valid_wb1 <= csr.io.dec_tlu_int_valid_wb1 @[dec_tlu_ctl.scala 879:44] - io.dec_tlu_i0_exc_valid_wb1 <= csr.io.dec_tlu_i0_exc_valid_wb1 @[dec_tlu_ctl.scala 880:44] - io.dec_tlu_i0_valid_wb1 <= csr.io.dec_tlu_i0_valid_wb1 @[dec_tlu_ctl.scala 881:44] - io.tlu_mem.dec_tlu_ic_diag_pkt.icache_wr_valid <= csr.io.dec_tlu_ic_diag_pkt.icache_wr_valid @[dec_tlu_ctl.scala 882:52] - io.tlu_mem.dec_tlu_ic_diag_pkt.icache_rd_valid <= csr.io.dec_tlu_ic_diag_pkt.icache_rd_valid @[dec_tlu_ctl.scala 882:52] - io.tlu_mem.dec_tlu_ic_diag_pkt.icache_dicawics <= csr.io.dec_tlu_ic_diag_pkt.icache_dicawics @[dec_tlu_ctl.scala 882:52] - io.tlu_mem.dec_tlu_ic_diag_pkt.icache_wrdata <= csr.io.dec_tlu_ic_diag_pkt.icache_wrdata @[dec_tlu_ctl.scala 882:52] - io.trigger_pkt_any[0].tdata2 <= csr.io.trigger_pkt_any[0].tdata2 @[dec_tlu_ctl.scala 883:40] - io.trigger_pkt_any[0].m <= csr.io.trigger_pkt_any[0].m @[dec_tlu_ctl.scala 883:40] - io.trigger_pkt_any[0].execute <= csr.io.trigger_pkt_any[0].execute @[dec_tlu_ctl.scala 883:40] - io.trigger_pkt_any[0].load <= csr.io.trigger_pkt_any[0].load @[dec_tlu_ctl.scala 883:40] - io.trigger_pkt_any[0].store <= csr.io.trigger_pkt_any[0].store @[dec_tlu_ctl.scala 883:40] - io.trigger_pkt_any[0].match_pkt <= csr.io.trigger_pkt_any[0].match_pkt @[dec_tlu_ctl.scala 883:40] - io.trigger_pkt_any[0].select <= csr.io.trigger_pkt_any[0].select @[dec_tlu_ctl.scala 883:40] - io.trigger_pkt_any[1].tdata2 <= csr.io.trigger_pkt_any[1].tdata2 @[dec_tlu_ctl.scala 883:40] - io.trigger_pkt_any[1].m <= csr.io.trigger_pkt_any[1].m @[dec_tlu_ctl.scala 883:40] - io.trigger_pkt_any[1].execute <= csr.io.trigger_pkt_any[1].execute @[dec_tlu_ctl.scala 883:40] - io.trigger_pkt_any[1].load <= csr.io.trigger_pkt_any[1].load @[dec_tlu_ctl.scala 883:40] - io.trigger_pkt_any[1].store <= csr.io.trigger_pkt_any[1].store @[dec_tlu_ctl.scala 883:40] - io.trigger_pkt_any[1].match_pkt <= csr.io.trigger_pkt_any[1].match_pkt @[dec_tlu_ctl.scala 883:40] - io.trigger_pkt_any[1].select <= csr.io.trigger_pkt_any[1].select @[dec_tlu_ctl.scala 883:40] - io.trigger_pkt_any[2].tdata2 <= csr.io.trigger_pkt_any[2].tdata2 @[dec_tlu_ctl.scala 883:40] - io.trigger_pkt_any[2].m <= csr.io.trigger_pkt_any[2].m @[dec_tlu_ctl.scala 883:40] - io.trigger_pkt_any[2].execute <= csr.io.trigger_pkt_any[2].execute @[dec_tlu_ctl.scala 883:40] - io.trigger_pkt_any[2].load <= csr.io.trigger_pkt_any[2].load @[dec_tlu_ctl.scala 883:40] - io.trigger_pkt_any[2].store <= csr.io.trigger_pkt_any[2].store @[dec_tlu_ctl.scala 883:40] - io.trigger_pkt_any[2].match_pkt <= csr.io.trigger_pkt_any[2].match_pkt @[dec_tlu_ctl.scala 883:40] - io.trigger_pkt_any[2].select <= csr.io.trigger_pkt_any[2].select @[dec_tlu_ctl.scala 883:40] - io.trigger_pkt_any[3].tdata2 <= csr.io.trigger_pkt_any[3].tdata2 @[dec_tlu_ctl.scala 883:40] - io.trigger_pkt_any[3].m <= csr.io.trigger_pkt_any[3].m @[dec_tlu_ctl.scala 883:40] - io.trigger_pkt_any[3].execute <= csr.io.trigger_pkt_any[3].execute @[dec_tlu_ctl.scala 883:40] - io.trigger_pkt_any[3].load <= csr.io.trigger_pkt_any[3].load @[dec_tlu_ctl.scala 883:40] - io.trigger_pkt_any[3].store <= csr.io.trigger_pkt_any[3].store @[dec_tlu_ctl.scala 883:40] - io.trigger_pkt_any[3].match_pkt <= csr.io.trigger_pkt_any[3].match_pkt @[dec_tlu_ctl.scala 883:40] - io.trigger_pkt_any[3].select <= csr.io.trigger_pkt_any[3].select @[dec_tlu_ctl.scala 883:40] - io.dec_tlu_mtval_wb1 <= csr.io.dec_tlu_mtval_wb1 @[dec_tlu_ctl.scala 884:40] - io.dec_tlu_exc_cause_wb1 <= csr.io.dec_tlu_exc_cause_wb1 @[dec_tlu_ctl.scala 885:40] - io.dec_tlu_perfcnt0 <= csr.io.dec_tlu_perfcnt0 @[dec_tlu_ctl.scala 886:40] - io.dec_tlu_perfcnt1 <= csr.io.dec_tlu_perfcnt1 @[dec_tlu_ctl.scala 887:40] - io.dec_tlu_perfcnt2 <= csr.io.dec_tlu_perfcnt2 @[dec_tlu_ctl.scala 888:40] - io.dec_tlu_perfcnt3 <= csr.io.dec_tlu_perfcnt3 @[dec_tlu_ctl.scala 889:40] - io.dec_tlu_misc_clk_override <= csr.io.dec_tlu_misc_clk_override @[dec_tlu_ctl.scala 890:40] - io.dec_tlu_dec_clk_override <= csr.io.dec_tlu_dec_clk_override @[dec_tlu_ctl.scala 891:40] - io.dec_tlu_ifu_clk_override <= csr.io.dec_tlu_ifu_clk_override @[dec_tlu_ctl.scala 892:40] - io.dec_tlu_lsu_clk_override <= csr.io.dec_tlu_lsu_clk_override @[dec_tlu_ctl.scala 893:40] - io.dec_tlu_bus_clk_override <= csr.io.dec_tlu_bus_clk_override @[dec_tlu_ctl.scala 894:40] - io.dec_tlu_pic_clk_override <= csr.io.dec_tlu_pic_clk_override @[dec_tlu_ctl.scala 895:40] - io.dec_tlu_dccm_clk_override <= csr.io.dec_tlu_dccm_clk_override @[dec_tlu_ctl.scala 896:40] - io.dec_tlu_icm_clk_override <= csr.io.dec_tlu_icm_clk_override @[dec_tlu_ctl.scala 897:40] - io.dec_csr_rddata_d <= csr.io.dec_csr_rddata_d @[dec_tlu_ctl.scala 898:40] - io.dec_tlu_pipelining_disable <= csr.io.dec_tlu_pipelining_disable @[dec_tlu_ctl.scala 899:40] - io.dec_tlu_wr_pause_r <= csr.io.dec_tlu_wr_pause_r @[dec_tlu_ctl.scala 900:40] - io.tlu_ifc.dec_tlu_mrac_ff <= csr.io.dec_tlu_mrac_ff @[dec_tlu_ctl.scala 901:48] - io.tlu_busbuff.dec_tlu_wb_coalescing_disable <= csr.io.dec_tlu_wb_coalescing_disable @[dec_tlu_ctl.scala 902:52] - io.tlu_bp.dec_tlu_bpred_disable <= csr.io.dec_tlu_bpred_disable @[dec_tlu_ctl.scala 903:47] - io.tlu_busbuff.dec_tlu_sideeffect_posted_disable <= csr.io.dec_tlu_sideeffect_posted_disable @[dec_tlu_ctl.scala 904:52] - io.tlu_mem.dec_tlu_core_ecc_disable <= csr.io.dec_tlu_core_ecc_disable @[dec_tlu_ctl.scala 905:48] - io.tlu_busbuff.dec_tlu_external_ldfwd_disable <= csr.io.dec_tlu_external_ldfwd_disable @[dec_tlu_ctl.scala 906:52] - io.tlu_dma.dec_tlu_dma_qos_prty <= csr.io.dec_tlu_dma_qos_prty @[dec_tlu_ctl.scala 907:48] - csr.io.dec_illegal_inst <= io.dec_illegal_inst @[dec_tlu_ctl.scala 908:44] - csr.io.lsu_error_pkt_r.bits.addr <= io.lsu_error_pkt_r.bits.addr @[dec_tlu_ctl.scala 909:44] - csr.io.lsu_error_pkt_r.bits.mscause <= io.lsu_error_pkt_r.bits.mscause @[dec_tlu_ctl.scala 909:44] - csr.io.lsu_error_pkt_r.bits.exc_type <= io.lsu_error_pkt_r.bits.exc_type @[dec_tlu_ctl.scala 909:44] - csr.io.lsu_error_pkt_r.bits.inst_type <= io.lsu_error_pkt_r.bits.inst_type @[dec_tlu_ctl.scala 909:44] - csr.io.lsu_error_pkt_r.bits.single_ecc_error <= io.lsu_error_pkt_r.bits.single_ecc_error @[dec_tlu_ctl.scala 909:44] - csr.io.lsu_error_pkt_r.valid <= io.lsu_error_pkt_r.valid @[dec_tlu_ctl.scala 909:44] - csr.io.mexintpend <= io.dec_pic.mexintpend @[dec_tlu_ctl.scala 910:44] - csr.io.exu_npc_r <= io.tlu_exu.exu_npc_r @[dec_tlu_ctl.scala 911:44] - csr.io.mpc_reset_run_req <= io.mpc_reset_run_req @[dec_tlu_ctl.scala 912:44] - csr.io.rst_vec <= io.rst_vec @[dec_tlu_ctl.scala 913:44] - csr.io.core_id <= io.core_id @[dec_tlu_ctl.scala 914:44] - csr.io.dec_timer_rddata_d <= int_timers.io.dec_timer_rddata_d @[dec_tlu_ctl.scala 915:44] - csr.io.dec_timer_read_d <= int_timers.io.dec_timer_read_d @[dec_tlu_ctl.scala 916:44] - csr.io.rfpc_i0_r <= rfpc_i0_r @[dec_tlu_ctl.scala 919:39] - csr.io.i0_trigger_hit_r <= i0_trigger_hit_r @[dec_tlu_ctl.scala 920:39] - csr.io.exc_or_int_valid_r <= exc_or_int_valid_r @[dec_tlu_ctl.scala 921:39] - csr.io.mret_r <= mret_r @[dec_tlu_ctl.scala 922:39] - csr.io.dcsr_single_step_running_f <= dcsr_single_step_running_f @[dec_tlu_ctl.scala 923:39] - csr.io.dec_timer_t0_pulse <= int_timers.io.dec_timer_t0_pulse @[dec_tlu_ctl.scala 924:39] - csr.io.dec_timer_t1_pulse <= int_timers.io.dec_timer_t1_pulse @[dec_tlu_ctl.scala 925:39] - csr.io.timer_int_sync <= timer_int_sync @[dec_tlu_ctl.scala 926:39] - csr.io.soft_int_sync <= soft_int_sync @[dec_tlu_ctl.scala 927:39] - csr.io.csr_wr_clk <= rvclkhdr.io.l1clk @[dec_tlu_ctl.scala 928:39] - csr.io.ebreak_to_debug_mode_r <= ebreak_to_debug_mode_r @[dec_tlu_ctl.scala 929:39] - csr.io.dec_tlu_pmu_fw_halted <= dec_tlu_pmu_fw_halted @[dec_tlu_ctl.scala 930:39] - csr.io.lsu_fir_error <= io.lsu_fir_error @[dec_tlu_ctl.scala 931:39] - csr.io.tlu_flush_lower_r_d1 <= tlu_flush_lower_r_d1 @[dec_tlu_ctl.scala 932:39] - csr.io.dec_tlu_flush_noredir_r_d1 <= dec_tlu_flush_noredir_r_d1 @[dec_tlu_ctl.scala 933:39] - csr.io.tlu_flush_path_r_d1 <= tlu_flush_path_r_d1 @[dec_tlu_ctl.scala 934:39] - csr.io.reset_delayed <= reset_delayed @[dec_tlu_ctl.scala 935:39] - csr.io.interrupt_valid_r <= interrupt_valid_r @[dec_tlu_ctl.scala 936:39] - csr.io.i0_exception_valid_r <= i0_exception_valid_r @[dec_tlu_ctl.scala 937:39] - csr.io.lsu_exc_valid_r <= lsu_exc_valid_r @[dec_tlu_ctl.scala 938:39] - csr.io.mepc_trigger_hit_sel_pc_r <= mepc_trigger_hit_sel_pc_r @[dec_tlu_ctl.scala 939:39] - csr.io.e4e5_int_clk <= rvclkhdr_3.io.l1clk @[dec_tlu_ctl.scala 940:39] - csr.io.lsu_i0_exc_r <= lsu_exc_valid_r @[dec_tlu_ctl.scala 941:39] - csr.io.inst_acc_r <= inst_acc_r @[dec_tlu_ctl.scala 942:39] - csr.io.inst_acc_second_r <= io.dec_tlu_packet_r.icaf_f1 @[dec_tlu_ctl.scala 943:39] - csr.io.take_nmi <= take_nmi @[dec_tlu_ctl.scala 944:39] - csr.io.lsu_error_pkt_addr_r <= io.lsu_error_pkt_r.bits.addr @[dec_tlu_ctl.scala 945:39] - csr.io.exc_cause_r <= exc_cause_r @[dec_tlu_ctl.scala 946:39] - csr.io.i0_valid_wb <= i0_valid_wb @[dec_tlu_ctl.scala 947:39] - csr.io.exc_or_int_valid_r_d1 <= exc_or_int_valid_r_d1 @[dec_tlu_ctl.scala 948:39] - csr.io.interrupt_valid_r_d1 <= interrupt_valid_r_d1 @[dec_tlu_ctl.scala 949:39] - csr.io.clk_override <= io.dec_tlu_dec_clk_override @[dec_tlu_ctl.scala 950:39] - csr.io.i0_exception_valid_r_d1 <= i0_exception_valid_r_d1 @[dec_tlu_ctl.scala 951:39] - csr.io.lsu_i0_exc_r_d1 <= lsu_i0_exc_r_d1 @[dec_tlu_ctl.scala 952:39] - csr.io.exc_cause_wb <= exc_cause_wb @[dec_tlu_ctl.scala 953:39] - csr.io.nmi_lsu_store_type <= nmi_lsu_store_type @[dec_tlu_ctl.scala 954:39] - csr.io.nmi_lsu_load_type <= nmi_lsu_load_type @[dec_tlu_ctl.scala 955:39] - csr.io.tlu_i0_commit_cmt <= tlu_i0_commit_cmt @[dec_tlu_ctl.scala 956:39] - csr.io.ebreak_r <= ebreak_r @[dec_tlu_ctl.scala 957:39] - csr.io.ecall_r <= ecall_r @[dec_tlu_ctl.scala 958:39] - csr.io.illegal_r <= illegal_r @[dec_tlu_ctl.scala 959:39] - csr.io.mdseac_locked_f <= mdseac_locked_f @[dec_tlu_ctl.scala 960:39] - csr.io.nmi_int_detected_f <= nmi_int_detected_f @[dec_tlu_ctl.scala 961:39] - csr.io.internal_dbg_halt_mode_f2 <= internal_dbg_halt_mode_f2 @[dec_tlu_ctl.scala 962:39] - csr.io.ext_int_freeze_d1 <= ext_int_freeze_d1 @[dec_tlu_ctl.scala 963:39] - csr.io.ic_perr_r_d1 <= ic_perr_r_d1 @[dec_tlu_ctl.scala 964:39] - csr.io.iccm_sbecc_r_d1 <= iccm_sbecc_r_d1 @[dec_tlu_ctl.scala 965:39] - csr.io.lsu_single_ecc_error_r_d1 <= lsu_single_ecc_error_r_d1 @[dec_tlu_ctl.scala 966:39] - csr.io.ifu_miss_state_idle_f <= ifu_miss_state_idle_f @[dec_tlu_ctl.scala 967:39] - csr.io.lsu_idle_any_f <= lsu_idle_any_f @[dec_tlu_ctl.scala 968:39] - csr.io.dbg_tlu_halted_f <= dbg_tlu_halted_f @[dec_tlu_ctl.scala 969:39] - csr.io.dbg_tlu_halted <= dbg_tlu_halted @[dec_tlu_ctl.scala 970:39] - csr.io.debug_halt_req_f <= debug_halt_req_f @[dec_tlu_ctl.scala 971:51] - csr.io.take_ext_int_start <= take_ext_int_start @[dec_tlu_ctl.scala 972:47] - csr.io.trigger_hit_dmode_r_d1 <= trigger_hit_dmode_r_d1 @[dec_tlu_ctl.scala 973:43] - csr.io.trigger_hit_r_d1 <= trigger_hit_r_d1 @[dec_tlu_ctl.scala 974:43] - csr.io.dcsr_single_step_done_f <= dcsr_single_step_done_f @[dec_tlu_ctl.scala 975:43] - csr.io.ebreak_to_debug_mode_r_d1 <= ebreak_to_debug_mode_r_d1 @[dec_tlu_ctl.scala 976:39] - csr.io.debug_halt_req <= debug_halt_req @[dec_tlu_ctl.scala 977:51] - csr.io.allow_dbg_halt_csr_write <= allow_dbg_halt_csr_write @[dec_tlu_ctl.scala 978:39] - csr.io.internal_dbg_halt_mode_f <= debug_mode_status @[dec_tlu_ctl.scala 979:39] - csr.io.enter_debug_halt_req <= enter_debug_halt_req @[dec_tlu_ctl.scala 980:39] - csr.io.internal_dbg_halt_mode <= internal_dbg_halt_mode @[dec_tlu_ctl.scala 981:39] - csr.io.request_debug_mode_done <= request_debug_mode_done @[dec_tlu_ctl.scala 982:39] - csr.io.request_debug_mode_r <= request_debug_mode_r @[dec_tlu_ctl.scala 983:39] - csr.io.update_hit_bit_r <= update_hit_bit_r @[dec_tlu_ctl.scala 984:39] - csr.io.take_timer_int <= take_timer_int @[dec_tlu_ctl.scala 985:39] - csr.io.take_int_timer0_int <= take_int_timer0_int @[dec_tlu_ctl.scala 986:39] - csr.io.take_int_timer1_int <= take_int_timer1_int @[dec_tlu_ctl.scala 987:39] - csr.io.take_ext_int <= take_ext_int @[dec_tlu_ctl.scala 988:39] - csr.io.tlu_flush_lower_r <= tlu_flush_lower_r @[dec_tlu_ctl.scala 989:39] - csr.io.dec_tlu_br0_error_r <= dec_tlu_br0_error_r @[dec_tlu_ctl.scala 990:39] - csr.io.dec_tlu_br0_start_error_r <= dec_tlu_br0_start_error_r @[dec_tlu_ctl.scala 991:39] - csr.io.lsu_pmu_load_external_r <= lsu_pmu_load_external_r @[dec_tlu_ctl.scala 992:39] - csr.io.lsu_pmu_store_external_r <= lsu_pmu_store_external_r @[dec_tlu_ctl.scala 993:39] - csr.io.csr_pkt.legal <= csr_pkt.legal @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.postsync <= csr_pkt.postsync @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.presync <= csr_pkt.presync @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_dicago <= csr_pkt.csr_dicago @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_dicad1 <= csr_pkt.csr_dicad1 @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_dicad0 <= csr_pkt.csr_dicad0 @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_dicad0h <= csr_pkt.csr_dicad0h @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_dicawics <= csr_pkt.csr_dicawics @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_mfdhs <= csr_pkt.csr_mfdhs @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_mfdht <= csr_pkt.csr_mfdht @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_mdccmect <= csr_pkt.csr_mdccmect @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_miccmect <= csr_pkt.csr_miccmect @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_micect <= csr_pkt.csr_micect @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_mdeau <= csr_pkt.csr_mdeau @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_meicpct <= csr_pkt.csr_meicpct @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_mcpc <= csr_pkt.csr_mcpc @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_mpmc <= csr_pkt.csr_mpmc @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_mitcnt1 <= csr_pkt.csr_mitcnt1 @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_mitcnt0 <= csr_pkt.csr_mitcnt0 @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_mitb1 <= csr_pkt.csr_mitb1 @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_mitb0 <= csr_pkt.csr_mitb0 @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_mitctl1 <= csr_pkt.csr_mitctl1 @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_mitctl0 <= csr_pkt.csr_mitctl0 @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_mcountinhibit <= csr_pkt.csr_mcountinhibit @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_mhpme6 <= csr_pkt.csr_mhpme6 @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_mhpme5 <= csr_pkt.csr_mhpme5 @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_mhpme4 <= csr_pkt.csr_mhpme4 @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_mhpme3 <= csr_pkt.csr_mhpme3 @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_mhpmc6h <= csr_pkt.csr_mhpmc6h @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_mhpmc5h <= csr_pkt.csr_mhpmc5h @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_mhpmc4h <= csr_pkt.csr_mhpmc4h @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_mhpmc3h <= csr_pkt.csr_mhpmc3h @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_mhpmc6 <= csr_pkt.csr_mhpmc6 @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_mhpmc5 <= csr_pkt.csr_mhpmc5 @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_mhpmc4 <= csr_pkt.csr_mhpmc4 @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_mhpmc3 <= csr_pkt.csr_mhpmc3 @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_mtdata2 <= csr_pkt.csr_mtdata2 @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_mtdata1 <= csr_pkt.csr_mtdata1 @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_mtsel <= csr_pkt.csr_mtsel @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_dpc <= csr_pkt.csr_dpc @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_mfdc <= csr_pkt.csr_mfdc @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_mcgc <= csr_pkt.csr_mcgc @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_dcsr <= csr_pkt.csr_dcsr @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_meicidpl <= csr_pkt.csr_meicidpl @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_meicurpl <= csr_pkt.csr_meicurpl @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_meipt <= csr_pkt.csr_meipt @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_meivt <= csr_pkt.csr_meivt @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_meihap <= csr_pkt.csr_meihap @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_mdseac <= csr_pkt.csr_mdseac @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_dmst <= csr_pkt.csr_dmst @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_mrac <= csr_pkt.csr_mrac @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_mtval <= csr_pkt.csr_mtval @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_mscause <= csr_pkt.csr_mscause @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_mcause <= csr_pkt.csr_mcause @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_mepc <= csr_pkt.csr_mepc @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_mscratch <= csr_pkt.csr_mscratch @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_minstreth <= csr_pkt.csr_minstreth @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_minstretl <= csr_pkt.csr_minstretl @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_mcycleh <= csr_pkt.csr_mcycleh @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_mcyclel <= csr_pkt.csr_mcyclel @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_mie <= csr_pkt.csr_mie @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_mip <= csr_pkt.csr_mip @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_mtvec <= csr_pkt.csr_mtvec @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_mstatus <= csr_pkt.csr_mstatus @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_mhartid <= csr_pkt.csr_mhartid @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_mimpid <= csr_pkt.csr_mimpid @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_marchid <= csr_pkt.csr_marchid @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_mvendorid <= csr_pkt.csr_mvendorid @[dec_tlu_ctl.scala 994:39] - csr.io.csr_pkt.csr_misa <= csr_pkt.csr_misa @[dec_tlu_ctl.scala 994:39] - npc_r <= csr.io.npc_r @[dec_tlu_ctl.scala 996:31] - npc_r_d1 <= csr.io.npc_r_d1 @[dec_tlu_ctl.scala 997:31] - mie_ns <= csr.io.mie_ns @[dec_tlu_ctl.scala 998:31] - mepc <= csr.io.mepc @[dec_tlu_ctl.scala 999:31] - mdseac_locked_ns <= csr.io.mdseac_locked_ns @[dec_tlu_ctl.scala 1000:31] - force_halt <= csr.io.force_halt @[dec_tlu_ctl.scala 1001:31] - dpc <= csr.io.dpc @[dec_tlu_ctl.scala 1002:31] - mstatus_mie_ns <= csr.io.mstatus_mie_ns @[dec_tlu_ctl.scala 1003:31] - dec_csr_wen_r_mod <= csr.io.dec_csr_wen_r_mod @[dec_tlu_ctl.scala 1004:31] - fw_halt_req <= csr.io.fw_halt_req @[dec_tlu_ctl.scala 1005:31] - mstatus <= csr.io.mstatus @[dec_tlu_ctl.scala 1006:31] - dcsr <= csr.io.dcsr @[dec_tlu_ctl.scala 1007:31] - mtvec <= csr.io.mtvec @[dec_tlu_ctl.scala 1008:31] - mip <= csr.io.mip @[dec_tlu_ctl.scala 1009:31] - mtdata1_t[0] <= csr.io.mtdata1_t[0] @[dec_tlu_ctl.scala 1010:33] - mtdata1_t[1] <= csr.io.mtdata1_t[1] @[dec_tlu_ctl.scala 1010:33] - mtdata1_t[2] <= csr.io.mtdata1_t[2] @[dec_tlu_ctl.scala 1010:33] - mtdata1_t[3] <= csr.io.mtdata1_t[3] @[dec_tlu_ctl.scala 1010:33] - inst csr_read of dec_decode_csr_read @[dec_tlu_ctl.scala 1011:22] + csr.io.free_clk <= io.free_clk @[dec_tlu_ctl.scala 817:44] + csr.io.active_clk <= io.active_clk @[dec_tlu_ctl.scala 818:44] + csr.io.scan_mode <= io.scan_mode @[dec_tlu_ctl.scala 819:44] + csr.io.dec_csr_wrdata_r <= io.dec_csr_wrdata_r @[dec_tlu_ctl.scala 820:44] + csr.io.dec_csr_wraddr_r <= io.dec_csr_wraddr_r @[dec_tlu_ctl.scala 821:44] + csr.io.dec_csr_rdaddr_d <= io.dec_csr_rdaddr_d @[dec_tlu_ctl.scala 822:44] + csr.io.dec_csr_wen_unq_d <= io.dec_csr_wen_unq_d @[dec_tlu_ctl.scala 823:44] + csr.io.dec_i0_decode_d <= io.dec_i0_decode_d @[dec_tlu_ctl.scala 824:44] + csr.io.ifu_ic_debug_rd_data_valid <= io.tlu_mem.ifu_ic_debug_rd_data_valid @[dec_tlu_ctl.scala 825:44] + csr.io.ifu_pmu_bus_trxn <= io.tlu_mem.ifu_pmu_bus_trxn @[dec_tlu_ctl.scala 826:44] + csr.io.dma_iccm_stall_any <= io.tlu_dma.dma_iccm_stall_any @[dec_tlu_ctl.scala 827:44] + csr.io.dma_dccm_stall_any <= io.tlu_dma.dma_dccm_stall_any @[dec_tlu_ctl.scala 828:44] + csr.io.lsu_store_stall_any <= io.lsu_store_stall_any @[dec_tlu_ctl.scala 829:44] + csr.io.dec_pmu_presync_stall <= io.dec_pmu_presync_stall @[dec_tlu_ctl.scala 830:44] + csr.io.dec_pmu_postsync_stall <= io.dec_pmu_postsync_stall @[dec_tlu_ctl.scala 831:44] + csr.io.dec_pmu_decode_stall <= io.dec_pmu_decode_stall @[dec_tlu_ctl.scala 832:44] + csr.io.ifu_pmu_fetch_stall <= io.tlu_ifc.ifu_pmu_fetch_stall @[dec_tlu_ctl.scala 833:44] + csr.io.dec_tlu_packet_r.pmu_lsu_misaligned <= io.dec_tlu_packet_r.pmu_lsu_misaligned @[dec_tlu_ctl.scala 834:44] + csr.io.dec_tlu_packet_r.pmu_divide <= io.dec_tlu_packet_r.pmu_divide @[dec_tlu_ctl.scala 834:44] + csr.io.dec_tlu_packet_r.pmu_i0_br_unpred <= io.dec_tlu_packet_r.pmu_i0_br_unpred @[dec_tlu_ctl.scala 834:44] + csr.io.dec_tlu_packet_r.pmu_i0_itype <= io.dec_tlu_packet_r.pmu_i0_itype @[dec_tlu_ctl.scala 834:44] + csr.io.dec_tlu_packet_r.i0trigger <= io.dec_tlu_packet_r.i0trigger @[dec_tlu_ctl.scala 834:44] + csr.io.dec_tlu_packet_r.fence_i <= io.dec_tlu_packet_r.fence_i @[dec_tlu_ctl.scala 834:44] + csr.io.dec_tlu_packet_r.icaf_type <= io.dec_tlu_packet_r.icaf_type @[dec_tlu_ctl.scala 834:44] + csr.io.dec_tlu_packet_r.icaf_f1 <= io.dec_tlu_packet_r.icaf_f1 @[dec_tlu_ctl.scala 834:44] + csr.io.dec_tlu_packet_r.icaf <= io.dec_tlu_packet_r.icaf @[dec_tlu_ctl.scala 834:44] + csr.io.dec_tlu_packet_r.legal <= io.dec_tlu_packet_r.legal @[dec_tlu_ctl.scala 834:44] + csr.io.exu_pmu_i0_br_ataken <= io.tlu_exu.exu_pmu_i0_br_ataken @[dec_tlu_ctl.scala 835:44] + csr.io.exu_pmu_i0_br_misp <= io.tlu_exu.exu_pmu_i0_br_misp @[dec_tlu_ctl.scala 836:44] + csr.io.dec_pmu_instr_decoded <= io.dec_pmu_instr_decoded @[dec_tlu_ctl.scala 837:44] + csr.io.ifu_pmu_instr_aligned <= io.ifu_pmu_instr_aligned @[dec_tlu_ctl.scala 838:44] + csr.io.exu_pmu_i0_pc4 <= io.tlu_exu.exu_pmu_i0_pc4 @[dec_tlu_ctl.scala 839:44] + csr.io.ifu_pmu_ic_miss <= io.tlu_mem.ifu_pmu_ic_miss @[dec_tlu_ctl.scala 840:44] + csr.io.ifu_pmu_ic_hit <= io.tlu_mem.ifu_pmu_ic_hit @[dec_tlu_ctl.scala 841:44] + csr.io.dec_csr_wen_r <= io.dec_csr_wen_r @[dec_tlu_ctl.scala 842:44] + csr.io.dec_tlu_dbg_halted <= io.dec_tlu_dbg_halted @[dec_tlu_ctl.scala 843:44] + csr.io.dma_pmu_dccm_write <= io.tlu_dma.dma_pmu_dccm_write @[dec_tlu_ctl.scala 844:44] + csr.io.dma_pmu_dccm_read <= io.tlu_dma.dma_pmu_dccm_read @[dec_tlu_ctl.scala 845:44] + csr.io.dma_pmu_any_write <= io.tlu_dma.dma_pmu_any_write @[dec_tlu_ctl.scala 846:44] + csr.io.dma_pmu_any_read <= io.tlu_dma.dma_pmu_any_read @[dec_tlu_ctl.scala 847:44] + csr.io.lsu_pmu_bus_busy <= io.tlu_busbuff.lsu_pmu_bus_busy @[dec_tlu_ctl.scala 848:44] + csr.io.dec_tlu_i0_pc_r <= io.dec_tlu_i0_pc_r @[dec_tlu_ctl.scala 849:44] + csr.io.dec_tlu_i0_valid_r <= io.dec_tlu_i0_valid_r @[dec_tlu_ctl.scala 850:44] + csr.io.dec_csr_stall_int_ff <= io.dec_csr_stall_int_ff @[dec_tlu_ctl.scala 851:44] + csr.io.dec_csr_any_unq_d <= io.dec_csr_any_unq_d @[dec_tlu_ctl.scala 852:44] + csr.io.ifu_pmu_bus_busy <= io.tlu_mem.ifu_pmu_bus_busy @[dec_tlu_ctl.scala 853:44] + csr.io.lsu_pmu_bus_error <= io.tlu_busbuff.lsu_pmu_bus_error @[dec_tlu_ctl.scala 854:44] + csr.io.ifu_pmu_bus_error <= io.tlu_mem.ifu_pmu_bus_error @[dec_tlu_ctl.scala 855:44] + csr.io.lsu_pmu_bus_misaligned <= io.tlu_busbuff.lsu_pmu_bus_misaligned @[dec_tlu_ctl.scala 856:44] + csr.io.lsu_pmu_bus_trxn <= io.tlu_busbuff.lsu_pmu_bus_trxn @[dec_tlu_ctl.scala 857:44] + csr.io.ifu_ic_debug_rd_data <= io.tlu_mem.ifu_ic_debug_rd_data @[dec_tlu_ctl.scala 858:44] + csr.io.pic_pl <= io.dec_pic.pic_pl @[dec_tlu_ctl.scala 859:44] + csr.io.pic_claimid <= io.dec_pic.pic_claimid @[dec_tlu_ctl.scala 860:44] + csr.io.iccm_dma_sb_error <= io.iccm_dma_sb_error @[dec_tlu_ctl.scala 861:44] + csr.io.lsu_imprecise_error_addr_any <= io.tlu_busbuff.lsu_imprecise_error_addr_any @[dec_tlu_ctl.scala 862:44] + csr.io.lsu_imprecise_error_load_any <= io.tlu_busbuff.lsu_imprecise_error_load_any @[dec_tlu_ctl.scala 863:44] + csr.io.lsu_imprecise_error_store_any <= io.tlu_busbuff.lsu_imprecise_error_store_any @[dec_tlu_ctl.scala 864:44] + csr.io.dec_illegal_inst <= io.dec_illegal_inst @[dec_tlu_ctl.scala 865:44] + csr.io.lsu_error_pkt_r.bits.addr <= io.lsu_error_pkt_r.bits.addr @[dec_tlu_ctl.scala 866:44] + csr.io.lsu_error_pkt_r.bits.mscause <= io.lsu_error_pkt_r.bits.mscause @[dec_tlu_ctl.scala 866:44] + csr.io.lsu_error_pkt_r.bits.exc_type <= io.lsu_error_pkt_r.bits.exc_type @[dec_tlu_ctl.scala 866:44] + csr.io.lsu_error_pkt_r.bits.inst_type <= io.lsu_error_pkt_r.bits.inst_type @[dec_tlu_ctl.scala 866:44] + csr.io.lsu_error_pkt_r.bits.single_ecc_error <= io.lsu_error_pkt_r.bits.single_ecc_error @[dec_tlu_ctl.scala 866:44] + csr.io.lsu_error_pkt_r.valid <= io.lsu_error_pkt_r.valid @[dec_tlu_ctl.scala 866:44] + csr.io.mexintpend <= io.dec_pic.mexintpend @[dec_tlu_ctl.scala 867:44] + csr.io.exu_npc_r <= io.tlu_exu.exu_npc_r @[dec_tlu_ctl.scala 868:44] + csr.io.mpc_reset_run_req <= io.mpc_reset_run_req @[dec_tlu_ctl.scala 869:44] + csr.io.rst_vec <= io.rst_vec @[dec_tlu_ctl.scala 870:44] + csr.io.core_id <= io.core_id @[dec_tlu_ctl.scala 871:44] + csr.io.dec_timer_rddata_d <= int_timers.io.dec_timer_rddata_d @[dec_tlu_ctl.scala 872:44] + csr.io.dec_timer_read_d <= int_timers.io.dec_timer_read_d @[dec_tlu_ctl.scala 873:44] + io.dec_pic.dec_tlu_meicurpl <= csr.io.dec_tlu_meicurpl @[dec_tlu_ctl.scala 874:52] + io.tlu_exu.dec_tlu_meihap <= csr.io.dec_tlu_meihap @[dec_tlu_ctl.scala 875:52] + io.dec_pic.dec_tlu_meipt <= csr.io.dec_tlu_meipt @[dec_tlu_ctl.scala 876:52] + io.dec_tlu_int_valid_wb1 <= csr.io.dec_tlu_int_valid_wb1 @[dec_tlu_ctl.scala 877:44] + io.dec_tlu_i0_exc_valid_wb1 <= csr.io.dec_tlu_i0_exc_valid_wb1 @[dec_tlu_ctl.scala 878:44] + io.dec_tlu_i0_valid_wb1 <= csr.io.dec_tlu_i0_valid_wb1 @[dec_tlu_ctl.scala 879:44] + io.tlu_mem.dec_tlu_ic_diag_pkt.icache_wr_valid <= csr.io.dec_tlu_ic_diag_pkt.icache_wr_valid @[dec_tlu_ctl.scala 880:52] + io.tlu_mem.dec_tlu_ic_diag_pkt.icache_rd_valid <= csr.io.dec_tlu_ic_diag_pkt.icache_rd_valid @[dec_tlu_ctl.scala 880:52] + io.tlu_mem.dec_tlu_ic_diag_pkt.icache_dicawics <= csr.io.dec_tlu_ic_diag_pkt.icache_dicawics @[dec_tlu_ctl.scala 880:52] + io.tlu_mem.dec_tlu_ic_diag_pkt.icache_wrdata <= csr.io.dec_tlu_ic_diag_pkt.icache_wrdata @[dec_tlu_ctl.scala 880:52] + io.trigger_pkt_any[0].tdata2 <= csr.io.trigger_pkt_any[0].tdata2 @[dec_tlu_ctl.scala 881:40] + io.trigger_pkt_any[0].m <= csr.io.trigger_pkt_any[0].m @[dec_tlu_ctl.scala 881:40] + io.trigger_pkt_any[0].execute <= csr.io.trigger_pkt_any[0].execute @[dec_tlu_ctl.scala 881:40] + io.trigger_pkt_any[0].load <= csr.io.trigger_pkt_any[0].load @[dec_tlu_ctl.scala 881:40] + io.trigger_pkt_any[0].store <= csr.io.trigger_pkt_any[0].store @[dec_tlu_ctl.scala 881:40] + io.trigger_pkt_any[0].match_pkt <= csr.io.trigger_pkt_any[0].match_pkt @[dec_tlu_ctl.scala 881:40] + io.trigger_pkt_any[0].select <= csr.io.trigger_pkt_any[0].select @[dec_tlu_ctl.scala 881:40] + io.trigger_pkt_any[1].tdata2 <= csr.io.trigger_pkt_any[1].tdata2 @[dec_tlu_ctl.scala 881:40] + io.trigger_pkt_any[1].m <= csr.io.trigger_pkt_any[1].m @[dec_tlu_ctl.scala 881:40] + io.trigger_pkt_any[1].execute <= csr.io.trigger_pkt_any[1].execute @[dec_tlu_ctl.scala 881:40] + io.trigger_pkt_any[1].load <= csr.io.trigger_pkt_any[1].load @[dec_tlu_ctl.scala 881:40] + io.trigger_pkt_any[1].store <= csr.io.trigger_pkt_any[1].store @[dec_tlu_ctl.scala 881:40] + io.trigger_pkt_any[1].match_pkt <= csr.io.trigger_pkt_any[1].match_pkt @[dec_tlu_ctl.scala 881:40] + io.trigger_pkt_any[1].select <= csr.io.trigger_pkt_any[1].select @[dec_tlu_ctl.scala 881:40] + io.trigger_pkt_any[2].tdata2 <= csr.io.trigger_pkt_any[2].tdata2 @[dec_tlu_ctl.scala 881:40] + io.trigger_pkt_any[2].m <= csr.io.trigger_pkt_any[2].m @[dec_tlu_ctl.scala 881:40] + io.trigger_pkt_any[2].execute <= csr.io.trigger_pkt_any[2].execute @[dec_tlu_ctl.scala 881:40] + io.trigger_pkt_any[2].load <= csr.io.trigger_pkt_any[2].load @[dec_tlu_ctl.scala 881:40] + io.trigger_pkt_any[2].store <= csr.io.trigger_pkt_any[2].store @[dec_tlu_ctl.scala 881:40] + io.trigger_pkt_any[2].match_pkt <= csr.io.trigger_pkt_any[2].match_pkt @[dec_tlu_ctl.scala 881:40] + io.trigger_pkt_any[2].select <= csr.io.trigger_pkt_any[2].select @[dec_tlu_ctl.scala 881:40] + io.trigger_pkt_any[3].tdata2 <= csr.io.trigger_pkt_any[3].tdata2 @[dec_tlu_ctl.scala 881:40] + io.trigger_pkt_any[3].m <= csr.io.trigger_pkt_any[3].m @[dec_tlu_ctl.scala 881:40] + io.trigger_pkt_any[3].execute <= csr.io.trigger_pkt_any[3].execute @[dec_tlu_ctl.scala 881:40] + io.trigger_pkt_any[3].load <= csr.io.trigger_pkt_any[3].load @[dec_tlu_ctl.scala 881:40] + io.trigger_pkt_any[3].store <= csr.io.trigger_pkt_any[3].store @[dec_tlu_ctl.scala 881:40] + io.trigger_pkt_any[3].match_pkt <= csr.io.trigger_pkt_any[3].match_pkt @[dec_tlu_ctl.scala 881:40] + io.trigger_pkt_any[3].select <= csr.io.trigger_pkt_any[3].select @[dec_tlu_ctl.scala 881:40] + io.dec_tlu_mtval_wb1 <= csr.io.dec_tlu_mtval_wb1 @[dec_tlu_ctl.scala 882:40] + io.dec_tlu_exc_cause_wb1 <= csr.io.dec_tlu_exc_cause_wb1 @[dec_tlu_ctl.scala 883:40] + io.dec_tlu_perfcnt0 <= csr.io.dec_tlu_perfcnt0 @[dec_tlu_ctl.scala 884:40] + io.dec_tlu_perfcnt1 <= csr.io.dec_tlu_perfcnt1 @[dec_tlu_ctl.scala 885:40] + io.dec_tlu_perfcnt2 <= csr.io.dec_tlu_perfcnt2 @[dec_tlu_ctl.scala 886:40] + io.dec_tlu_perfcnt3 <= csr.io.dec_tlu_perfcnt3 @[dec_tlu_ctl.scala 887:40] + io.dec_tlu_misc_clk_override <= csr.io.dec_tlu_misc_clk_override @[dec_tlu_ctl.scala 888:40] + io.dec_tlu_dec_clk_override <= csr.io.dec_tlu_dec_clk_override @[dec_tlu_ctl.scala 889:40] + io.dec_tlu_ifu_clk_override <= csr.io.dec_tlu_ifu_clk_override @[dec_tlu_ctl.scala 890:40] + io.dec_tlu_lsu_clk_override <= csr.io.dec_tlu_lsu_clk_override @[dec_tlu_ctl.scala 891:40] + io.dec_tlu_bus_clk_override <= csr.io.dec_tlu_bus_clk_override @[dec_tlu_ctl.scala 892:40] + io.dec_tlu_pic_clk_override <= csr.io.dec_tlu_pic_clk_override @[dec_tlu_ctl.scala 893:40] + io.dec_tlu_dccm_clk_override <= csr.io.dec_tlu_dccm_clk_override @[dec_tlu_ctl.scala 894:40] + io.dec_tlu_icm_clk_override <= csr.io.dec_tlu_icm_clk_override @[dec_tlu_ctl.scala 895:40] + io.dec_csr_rddata_d <= csr.io.dec_csr_rddata_d @[dec_tlu_ctl.scala 896:40] + io.dec_tlu_pipelining_disable <= csr.io.dec_tlu_pipelining_disable @[dec_tlu_ctl.scala 897:40] + io.dec_tlu_wr_pause_r <= csr.io.dec_tlu_wr_pause_r @[dec_tlu_ctl.scala 898:40] + io.tlu_ifc.dec_tlu_mrac_ff <= csr.io.dec_tlu_mrac_ff @[dec_tlu_ctl.scala 899:48] + io.tlu_busbuff.dec_tlu_wb_coalescing_disable <= csr.io.dec_tlu_wb_coalescing_disable @[dec_tlu_ctl.scala 900:52] + io.tlu_bp.dec_tlu_bpred_disable <= csr.io.dec_tlu_bpred_disable @[dec_tlu_ctl.scala 901:47] + io.tlu_busbuff.dec_tlu_sideeffect_posted_disable <= csr.io.dec_tlu_sideeffect_posted_disable @[dec_tlu_ctl.scala 902:52] + io.tlu_mem.dec_tlu_core_ecc_disable <= csr.io.dec_tlu_core_ecc_disable @[dec_tlu_ctl.scala 903:48] + io.tlu_busbuff.dec_tlu_external_ldfwd_disable <= csr.io.dec_tlu_external_ldfwd_disable @[dec_tlu_ctl.scala 904:52] + io.tlu_dma.dec_tlu_dma_qos_prty <= csr.io.dec_tlu_dma_qos_prty @[dec_tlu_ctl.scala 905:48] + csr.io.dec_illegal_inst <= io.dec_illegal_inst @[dec_tlu_ctl.scala 906:44] + csr.io.lsu_error_pkt_r.bits.addr <= io.lsu_error_pkt_r.bits.addr @[dec_tlu_ctl.scala 907:44] + csr.io.lsu_error_pkt_r.bits.mscause <= io.lsu_error_pkt_r.bits.mscause @[dec_tlu_ctl.scala 907:44] + csr.io.lsu_error_pkt_r.bits.exc_type <= io.lsu_error_pkt_r.bits.exc_type @[dec_tlu_ctl.scala 907:44] + csr.io.lsu_error_pkt_r.bits.inst_type <= io.lsu_error_pkt_r.bits.inst_type @[dec_tlu_ctl.scala 907:44] + csr.io.lsu_error_pkt_r.bits.single_ecc_error <= io.lsu_error_pkt_r.bits.single_ecc_error @[dec_tlu_ctl.scala 907:44] + csr.io.lsu_error_pkt_r.valid <= io.lsu_error_pkt_r.valid @[dec_tlu_ctl.scala 907:44] + csr.io.mexintpend <= io.dec_pic.mexintpend @[dec_tlu_ctl.scala 908:44] + csr.io.exu_npc_r <= io.tlu_exu.exu_npc_r @[dec_tlu_ctl.scala 909:44] + csr.io.mpc_reset_run_req <= io.mpc_reset_run_req @[dec_tlu_ctl.scala 910:44] + csr.io.rst_vec <= io.rst_vec @[dec_tlu_ctl.scala 911:44] + csr.io.core_id <= io.core_id @[dec_tlu_ctl.scala 912:44] + csr.io.dec_timer_rddata_d <= int_timers.io.dec_timer_rddata_d @[dec_tlu_ctl.scala 913:44] + csr.io.dec_timer_read_d <= int_timers.io.dec_timer_read_d @[dec_tlu_ctl.scala 914:44] + csr.io.rfpc_i0_r <= rfpc_i0_r @[dec_tlu_ctl.scala 917:39] + csr.io.i0_trigger_hit_r <= i0_trigger_hit_r @[dec_tlu_ctl.scala 918:39] + csr.io.exc_or_int_valid_r <= exc_or_int_valid_r @[dec_tlu_ctl.scala 919:39] + csr.io.mret_r <= mret_r @[dec_tlu_ctl.scala 920:39] + csr.io.dcsr_single_step_running_f <= dcsr_single_step_running_f @[dec_tlu_ctl.scala 921:39] + csr.io.dec_timer_t0_pulse <= int_timers.io.dec_timer_t0_pulse @[dec_tlu_ctl.scala 922:39] + csr.io.dec_timer_t1_pulse <= int_timers.io.dec_timer_t1_pulse @[dec_tlu_ctl.scala 923:39] + csr.io.timer_int_sync <= timer_int_sync @[dec_tlu_ctl.scala 924:39] + csr.io.soft_int_sync <= soft_int_sync @[dec_tlu_ctl.scala 925:39] + csr.io.csr_wr_clk <= rvclkhdr.io.l1clk @[dec_tlu_ctl.scala 926:39] + csr.io.ebreak_to_debug_mode_r <= ebreak_to_debug_mode_r @[dec_tlu_ctl.scala 927:39] + csr.io.dec_tlu_pmu_fw_halted <= dec_tlu_pmu_fw_halted @[dec_tlu_ctl.scala 928:39] + csr.io.lsu_fir_error <= io.lsu_fir_error @[dec_tlu_ctl.scala 929:39] + csr.io.tlu_flush_lower_r_d1 <= tlu_flush_lower_r_d1 @[dec_tlu_ctl.scala 930:39] + csr.io.dec_tlu_flush_noredir_r_d1 <= dec_tlu_flush_noredir_r_d1 @[dec_tlu_ctl.scala 931:39] + csr.io.tlu_flush_path_r_d1 <= tlu_flush_path_r_d1 @[dec_tlu_ctl.scala 932:39] + csr.io.reset_delayed <= reset_delayed @[dec_tlu_ctl.scala 933:39] + csr.io.interrupt_valid_r <= interrupt_valid_r @[dec_tlu_ctl.scala 934:39] + csr.io.i0_exception_valid_r <= i0_exception_valid_r @[dec_tlu_ctl.scala 935:39] + csr.io.lsu_exc_valid_r <= lsu_exc_valid_r @[dec_tlu_ctl.scala 936:39] + csr.io.mepc_trigger_hit_sel_pc_r <= mepc_trigger_hit_sel_pc_r @[dec_tlu_ctl.scala 937:39] + csr.io.e4e5_int_clk <= rvclkhdr_3.io.l1clk @[dec_tlu_ctl.scala 938:39] + csr.io.lsu_i0_exc_r <= lsu_exc_valid_r @[dec_tlu_ctl.scala 939:39] + csr.io.inst_acc_r <= inst_acc_r @[dec_tlu_ctl.scala 940:39] + csr.io.inst_acc_second_r <= io.dec_tlu_packet_r.icaf_f1 @[dec_tlu_ctl.scala 941:39] + csr.io.take_nmi <= take_nmi @[dec_tlu_ctl.scala 942:39] + csr.io.lsu_error_pkt_addr_r <= io.lsu_error_pkt_r.bits.addr @[dec_tlu_ctl.scala 943:39] + csr.io.exc_cause_r <= exc_cause_r @[dec_tlu_ctl.scala 944:39] + csr.io.i0_valid_wb <= i0_valid_wb @[dec_tlu_ctl.scala 945:39] + csr.io.exc_or_int_valid_r_d1 <= exc_or_int_valid_r_d1 @[dec_tlu_ctl.scala 946:39] + csr.io.interrupt_valid_r_d1 <= interrupt_valid_r_d1 @[dec_tlu_ctl.scala 947:39] + csr.io.clk_override <= io.dec_tlu_dec_clk_override @[dec_tlu_ctl.scala 948:39] + csr.io.i0_exception_valid_r_d1 <= i0_exception_valid_r_d1 @[dec_tlu_ctl.scala 949:39] + csr.io.lsu_i0_exc_r_d1 <= lsu_i0_exc_r_d1 @[dec_tlu_ctl.scala 950:39] + csr.io.exc_cause_wb <= exc_cause_wb @[dec_tlu_ctl.scala 951:39] + csr.io.nmi_lsu_store_type <= nmi_lsu_store_type @[dec_tlu_ctl.scala 952:39] + csr.io.nmi_lsu_load_type <= nmi_lsu_load_type @[dec_tlu_ctl.scala 953:39] + csr.io.tlu_i0_commit_cmt <= tlu_i0_commit_cmt @[dec_tlu_ctl.scala 954:39] + csr.io.ebreak_r <= ebreak_r @[dec_tlu_ctl.scala 955:39] + csr.io.ecall_r <= ecall_r @[dec_tlu_ctl.scala 956:39] + csr.io.illegal_r <= illegal_r @[dec_tlu_ctl.scala 957:39] + csr.io.mdseac_locked_f <= mdseac_locked_f @[dec_tlu_ctl.scala 958:39] + csr.io.nmi_int_detected_f <= nmi_int_detected_f @[dec_tlu_ctl.scala 959:39] + csr.io.internal_dbg_halt_mode_f2 <= internal_dbg_halt_mode_f2 @[dec_tlu_ctl.scala 960:39] + csr.io.ext_int_freeze_d1 <= ext_int_freeze_d1 @[dec_tlu_ctl.scala 961:39] + csr.io.ic_perr_r_d1 <= ic_perr_r_d1 @[dec_tlu_ctl.scala 962:39] + csr.io.iccm_sbecc_r_d1 <= iccm_sbecc_r_d1 @[dec_tlu_ctl.scala 963:39] + csr.io.lsu_single_ecc_error_r_d1 <= lsu_single_ecc_error_r_d1 @[dec_tlu_ctl.scala 964:39] + csr.io.ifu_miss_state_idle_f <= ifu_miss_state_idle_f @[dec_tlu_ctl.scala 965:39] + csr.io.lsu_idle_any_f <= lsu_idle_any_f @[dec_tlu_ctl.scala 966:39] + csr.io.dbg_tlu_halted_f <= dbg_tlu_halted_f @[dec_tlu_ctl.scala 967:39] + csr.io.dbg_tlu_halted <= dbg_tlu_halted @[dec_tlu_ctl.scala 968:39] + csr.io.debug_halt_req_f <= debug_halt_req_f @[dec_tlu_ctl.scala 969:51] + csr.io.take_ext_int_start <= take_ext_int_start @[dec_tlu_ctl.scala 970:47] + csr.io.trigger_hit_dmode_r_d1 <= trigger_hit_dmode_r_d1 @[dec_tlu_ctl.scala 971:43] + csr.io.trigger_hit_r_d1 <= trigger_hit_r_d1 @[dec_tlu_ctl.scala 972:43] + csr.io.dcsr_single_step_done_f <= dcsr_single_step_done_f @[dec_tlu_ctl.scala 973:43] + csr.io.ebreak_to_debug_mode_r_d1 <= ebreak_to_debug_mode_r_d1 @[dec_tlu_ctl.scala 974:39] + csr.io.debug_halt_req <= debug_halt_req @[dec_tlu_ctl.scala 975:51] + csr.io.allow_dbg_halt_csr_write <= allow_dbg_halt_csr_write @[dec_tlu_ctl.scala 976:39] + csr.io.internal_dbg_halt_mode_f <= debug_mode_status @[dec_tlu_ctl.scala 977:39] + csr.io.enter_debug_halt_req <= enter_debug_halt_req @[dec_tlu_ctl.scala 978:39] + csr.io.internal_dbg_halt_mode <= internal_dbg_halt_mode @[dec_tlu_ctl.scala 979:39] + csr.io.request_debug_mode_done <= request_debug_mode_done @[dec_tlu_ctl.scala 980:39] + csr.io.request_debug_mode_r <= request_debug_mode_r @[dec_tlu_ctl.scala 981:39] + csr.io.update_hit_bit_r <= update_hit_bit_r @[dec_tlu_ctl.scala 982:39] + csr.io.take_timer_int <= take_timer_int @[dec_tlu_ctl.scala 983:39] + csr.io.take_int_timer0_int <= take_int_timer0_int @[dec_tlu_ctl.scala 984:39] + csr.io.take_int_timer1_int <= take_int_timer1_int @[dec_tlu_ctl.scala 985:39] + csr.io.take_ext_int <= take_ext_int @[dec_tlu_ctl.scala 986:39] + csr.io.tlu_flush_lower_r <= tlu_flush_lower_r @[dec_tlu_ctl.scala 987:39] + csr.io.dec_tlu_br0_error_r <= dec_tlu_br0_error_r @[dec_tlu_ctl.scala 988:39] + csr.io.dec_tlu_br0_start_error_r <= dec_tlu_br0_start_error_r @[dec_tlu_ctl.scala 989:39] + csr.io.lsu_pmu_load_external_r <= lsu_pmu_load_external_r @[dec_tlu_ctl.scala 990:39] + csr.io.lsu_pmu_store_external_r <= lsu_pmu_store_external_r @[dec_tlu_ctl.scala 991:39] + csr.io.csr_pkt.legal <= csr_pkt.legal @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.postsync <= csr_pkt.postsync @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.presync <= csr_pkt.presync @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_dicago <= csr_pkt.csr_dicago @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_dicad1 <= csr_pkt.csr_dicad1 @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_dicad0 <= csr_pkt.csr_dicad0 @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_dicad0h <= csr_pkt.csr_dicad0h @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_dicawics <= csr_pkt.csr_dicawics @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_mfdhs <= csr_pkt.csr_mfdhs @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_mfdht <= csr_pkt.csr_mfdht @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_mdccmect <= csr_pkt.csr_mdccmect @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_miccmect <= csr_pkt.csr_miccmect @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_micect <= csr_pkt.csr_micect @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_mdeau <= csr_pkt.csr_mdeau @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_meicpct <= csr_pkt.csr_meicpct @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_mcpc <= csr_pkt.csr_mcpc @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_mpmc <= csr_pkt.csr_mpmc @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_mitcnt1 <= csr_pkt.csr_mitcnt1 @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_mitcnt0 <= csr_pkt.csr_mitcnt0 @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_mitb1 <= csr_pkt.csr_mitb1 @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_mitb0 <= csr_pkt.csr_mitb0 @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_mitctl1 <= csr_pkt.csr_mitctl1 @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_mitctl0 <= csr_pkt.csr_mitctl0 @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_mcountinhibit <= csr_pkt.csr_mcountinhibit @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_mhpme6 <= csr_pkt.csr_mhpme6 @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_mhpme5 <= csr_pkt.csr_mhpme5 @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_mhpme4 <= csr_pkt.csr_mhpme4 @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_mhpme3 <= csr_pkt.csr_mhpme3 @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_mhpmc6h <= csr_pkt.csr_mhpmc6h @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_mhpmc5h <= csr_pkt.csr_mhpmc5h @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_mhpmc4h <= csr_pkt.csr_mhpmc4h @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_mhpmc3h <= csr_pkt.csr_mhpmc3h @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_mhpmc6 <= csr_pkt.csr_mhpmc6 @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_mhpmc5 <= csr_pkt.csr_mhpmc5 @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_mhpmc4 <= csr_pkt.csr_mhpmc4 @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_mhpmc3 <= csr_pkt.csr_mhpmc3 @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_mtdata2 <= csr_pkt.csr_mtdata2 @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_mtdata1 <= csr_pkt.csr_mtdata1 @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_mtsel <= csr_pkt.csr_mtsel @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_dpc <= csr_pkt.csr_dpc @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_mfdc <= csr_pkt.csr_mfdc @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_mcgc <= csr_pkt.csr_mcgc @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_dcsr <= csr_pkt.csr_dcsr @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_meicidpl <= csr_pkt.csr_meicidpl @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_meicurpl <= csr_pkt.csr_meicurpl @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_meipt <= csr_pkt.csr_meipt @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_meivt <= csr_pkt.csr_meivt @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_meihap <= csr_pkt.csr_meihap @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_mdseac <= csr_pkt.csr_mdseac @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_dmst <= csr_pkt.csr_dmst @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_mrac <= csr_pkt.csr_mrac @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_mtval <= csr_pkt.csr_mtval @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_mscause <= csr_pkt.csr_mscause @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_mcause <= csr_pkt.csr_mcause @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_mepc <= csr_pkt.csr_mepc @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_mscratch <= csr_pkt.csr_mscratch @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_minstreth <= csr_pkt.csr_minstreth @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_minstretl <= csr_pkt.csr_minstretl @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_mcycleh <= csr_pkt.csr_mcycleh @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_mcyclel <= csr_pkt.csr_mcyclel @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_mie <= csr_pkt.csr_mie @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_mip <= csr_pkt.csr_mip @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_mtvec <= csr_pkt.csr_mtvec @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_mstatus <= csr_pkt.csr_mstatus @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_mhartid <= csr_pkt.csr_mhartid @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_mimpid <= csr_pkt.csr_mimpid @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_marchid <= csr_pkt.csr_marchid @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_mvendorid <= csr_pkt.csr_mvendorid @[dec_tlu_ctl.scala 992:39] + csr.io.csr_pkt.csr_misa <= csr_pkt.csr_misa @[dec_tlu_ctl.scala 992:39] + npc_r <= csr.io.npc_r @[dec_tlu_ctl.scala 994:31] + npc_r_d1 <= csr.io.npc_r_d1 @[dec_tlu_ctl.scala 995:31] + mie_ns <= csr.io.mie_ns @[dec_tlu_ctl.scala 996:31] + mepc <= csr.io.mepc @[dec_tlu_ctl.scala 997:31] + mdseac_locked_ns <= csr.io.mdseac_locked_ns @[dec_tlu_ctl.scala 998:31] + force_halt <= csr.io.force_halt @[dec_tlu_ctl.scala 999:31] + dpc <= csr.io.dpc @[dec_tlu_ctl.scala 1000:31] + mstatus_mie_ns <= csr.io.mstatus_mie_ns @[dec_tlu_ctl.scala 1001:31] + dec_csr_wen_r_mod <= csr.io.dec_csr_wen_r_mod @[dec_tlu_ctl.scala 1002:31] + fw_halt_req <= csr.io.fw_halt_req @[dec_tlu_ctl.scala 1003:31] + mstatus <= csr.io.mstatus @[dec_tlu_ctl.scala 1004:31] + dcsr <= csr.io.dcsr @[dec_tlu_ctl.scala 1005:31] + mtvec <= csr.io.mtvec @[dec_tlu_ctl.scala 1006:31] + mip <= csr.io.mip @[dec_tlu_ctl.scala 1007:31] + mtdata1_t[0] <= csr.io.mtdata1_t[0] @[dec_tlu_ctl.scala 1008:33] + mtdata1_t[1] <= csr.io.mtdata1_t[1] @[dec_tlu_ctl.scala 1008:33] + mtdata1_t[2] <= csr.io.mtdata1_t[2] @[dec_tlu_ctl.scala 1008:33] + mtdata1_t[3] <= csr.io.mtdata1_t[3] @[dec_tlu_ctl.scala 1008:33] + inst csr_read of dec_decode_csr_read @[dec_tlu_ctl.scala 1009:22] csr_read.clock <= clock csr_read.reset <= reset - csr_read.io.dec_csr_rdaddr_d <= io.dec_csr_rdaddr_d @[dec_tlu_ctl.scala 1012:37] - csr_pkt.legal <= csr_read.io.csr_pkt.legal @[dec_tlu_ctl.scala 1013:16] - csr_pkt.postsync <= csr_read.io.csr_pkt.postsync @[dec_tlu_ctl.scala 1013:16] - csr_pkt.presync <= csr_read.io.csr_pkt.presync @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_dicago <= csr_read.io.csr_pkt.csr_dicago @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_dicad1 <= csr_read.io.csr_pkt.csr_dicad1 @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_dicad0 <= csr_read.io.csr_pkt.csr_dicad0 @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_dicad0h <= csr_read.io.csr_pkt.csr_dicad0h @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_dicawics <= csr_read.io.csr_pkt.csr_dicawics @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_mfdhs <= csr_read.io.csr_pkt.csr_mfdhs @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_mfdht <= csr_read.io.csr_pkt.csr_mfdht @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_mdccmect <= csr_read.io.csr_pkt.csr_mdccmect @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_miccmect <= csr_read.io.csr_pkt.csr_miccmect @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_micect <= csr_read.io.csr_pkt.csr_micect @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_mdeau <= csr_read.io.csr_pkt.csr_mdeau @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_meicpct <= csr_read.io.csr_pkt.csr_meicpct @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_mcpc <= csr_read.io.csr_pkt.csr_mcpc @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_mpmc <= csr_read.io.csr_pkt.csr_mpmc @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_mitcnt1 <= csr_read.io.csr_pkt.csr_mitcnt1 @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_mitcnt0 <= csr_read.io.csr_pkt.csr_mitcnt0 @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_mitb1 <= csr_read.io.csr_pkt.csr_mitb1 @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_mitb0 <= csr_read.io.csr_pkt.csr_mitb0 @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_mitctl1 <= csr_read.io.csr_pkt.csr_mitctl1 @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_mitctl0 <= csr_read.io.csr_pkt.csr_mitctl0 @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_mcountinhibit <= csr_read.io.csr_pkt.csr_mcountinhibit @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_mhpme6 <= csr_read.io.csr_pkt.csr_mhpme6 @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_mhpme5 <= csr_read.io.csr_pkt.csr_mhpme5 @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_mhpme4 <= csr_read.io.csr_pkt.csr_mhpme4 @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_mhpme3 <= csr_read.io.csr_pkt.csr_mhpme3 @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_mhpmc6h <= csr_read.io.csr_pkt.csr_mhpmc6h @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_mhpmc5h <= csr_read.io.csr_pkt.csr_mhpmc5h @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_mhpmc4h <= csr_read.io.csr_pkt.csr_mhpmc4h @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_mhpmc3h <= csr_read.io.csr_pkt.csr_mhpmc3h @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_mhpmc6 <= csr_read.io.csr_pkt.csr_mhpmc6 @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_mhpmc5 <= csr_read.io.csr_pkt.csr_mhpmc5 @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_mhpmc4 <= csr_read.io.csr_pkt.csr_mhpmc4 @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_mhpmc3 <= csr_read.io.csr_pkt.csr_mhpmc3 @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_mtdata2 <= csr_read.io.csr_pkt.csr_mtdata2 @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_mtdata1 <= csr_read.io.csr_pkt.csr_mtdata1 @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_mtsel <= csr_read.io.csr_pkt.csr_mtsel @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_dpc <= csr_read.io.csr_pkt.csr_dpc @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_mfdc <= csr_read.io.csr_pkt.csr_mfdc @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_mcgc <= csr_read.io.csr_pkt.csr_mcgc @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_dcsr <= csr_read.io.csr_pkt.csr_dcsr @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_meicidpl <= csr_read.io.csr_pkt.csr_meicidpl @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_meicurpl <= csr_read.io.csr_pkt.csr_meicurpl @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_meipt <= csr_read.io.csr_pkt.csr_meipt @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_meivt <= csr_read.io.csr_pkt.csr_meivt @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_meihap <= csr_read.io.csr_pkt.csr_meihap @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_mdseac <= csr_read.io.csr_pkt.csr_mdseac @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_dmst <= csr_read.io.csr_pkt.csr_dmst @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_mrac <= csr_read.io.csr_pkt.csr_mrac @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_mtval <= csr_read.io.csr_pkt.csr_mtval @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_mscause <= csr_read.io.csr_pkt.csr_mscause @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_mcause <= csr_read.io.csr_pkt.csr_mcause @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_mepc <= csr_read.io.csr_pkt.csr_mepc @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_mscratch <= csr_read.io.csr_pkt.csr_mscratch @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_minstreth <= csr_read.io.csr_pkt.csr_minstreth @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_minstretl <= csr_read.io.csr_pkt.csr_minstretl @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_mcycleh <= csr_read.io.csr_pkt.csr_mcycleh @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_mcyclel <= csr_read.io.csr_pkt.csr_mcyclel @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_mie <= csr_read.io.csr_pkt.csr_mie @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_mip <= csr_read.io.csr_pkt.csr_mip @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_mtvec <= csr_read.io.csr_pkt.csr_mtvec @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_mstatus <= csr_read.io.csr_pkt.csr_mstatus @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_mhartid <= csr_read.io.csr_pkt.csr_mhartid @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_mimpid <= csr_read.io.csr_pkt.csr_mimpid @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_marchid <= csr_read.io.csr_pkt.csr_marchid @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_mvendorid <= csr_read.io.csr_pkt.csr_mvendorid @[dec_tlu_ctl.scala 1013:16] - csr_pkt.csr_misa <= csr_read.io.csr_pkt.csr_misa @[dec_tlu_ctl.scala 1013:16] - node _T_864 = and(csr_pkt.presync, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 1015:42] - node _T_865 = not(io.dec_csr_wen_unq_d) @[dec_tlu_ctl.scala 1015:67] - node _T_866 = and(_T_864, _T_865) @[dec_tlu_ctl.scala 1015:65] - io.dec_tlu_presync_d <= _T_866 @[dec_tlu_ctl.scala 1015:23] - node _T_867 = and(csr_pkt.postsync, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 1016:43] - io.dec_tlu_postsync_d <= _T_867 @[dec_tlu_ctl.scala 1016:23] - node _T_868 = or(csr_pkt.csr_mitcnt0, csr_pkt.csr_mitcnt1) @[dec_tlu_ctl.scala 1019:50] - node _T_869 = or(_T_868, csr_pkt.csr_mitb0) @[dec_tlu_ctl.scala 1019:72] - node _T_870 = or(_T_869, csr_pkt.csr_mitb1) @[dec_tlu_ctl.scala 1019:92] - node _T_871 = or(_T_870, csr_pkt.csr_mitctl0) @[dec_tlu_ctl.scala 1019:112] - node _T_872 = or(_T_871, csr_pkt.csr_mitctl1) @[dec_tlu_ctl.scala 1019:134] - node _T_873 = not(UInt<1>("h01")) @[dec_tlu_ctl.scala 1019:159] - node conditionally_illegal = and(_T_872, _T_873) @[dec_tlu_ctl.scala 1019:157] - node _T_874 = or(csr_pkt.csr_dcsr, csr_pkt.csr_dpc) @[dec_tlu_ctl.scala 1020:55] - node _T_875 = or(_T_874, csr_pkt.csr_dmst) @[dec_tlu_ctl.scala 1020:73] - node _T_876 = or(_T_875, csr_pkt.csr_dicawics) @[dec_tlu_ctl.scala 1020:92] - node _T_877 = or(_T_876, csr_pkt.csr_dicad0) @[dec_tlu_ctl.scala 1020:115] - node _T_878 = or(_T_877, csr_pkt.csr_dicad0h) @[dec_tlu_ctl.scala 1020:136] - node _T_879 = or(_T_878, csr_pkt.csr_dicad1) @[dec_tlu_ctl.scala 1020:158] - node _T_880 = or(_T_879, csr_pkt.csr_dicago) @[dec_tlu_ctl.scala 1020:179] - node _T_881 = not(_T_880) @[dec_tlu_ctl.scala 1020:36] - node _T_882 = or(_T_881, dbg_tlu_halted_f) @[dec_tlu_ctl.scala 1020:201] - node _T_883 = and(csr_pkt.legal, _T_882) @[dec_tlu_ctl.scala 1020:33] - node _T_884 = not(fast_int_meicpct) @[dec_tlu_ctl.scala 1020:223] - node _T_885 = and(_T_883, _T_884) @[dec_tlu_ctl.scala 1020:221] - node _T_886 = not(conditionally_illegal) @[dec_tlu_ctl.scala 1020:243] - node valid_csr = and(_T_885, _T_886) @[dec_tlu_ctl.scala 1020:241] - node _T_887 = and(io.dec_csr_any_unq_d, valid_csr) @[dec_tlu_ctl.scala 1022:46] - node _T_888 = or(csr_pkt.csr_mvendorid, csr_pkt.csr_marchid) @[dec_tlu_ctl.scala 1022:107] - node _T_889 = or(_T_888, csr_pkt.csr_mimpid) @[dec_tlu_ctl.scala 1022:129] - node _T_890 = or(_T_889, csr_pkt.csr_mhartid) @[dec_tlu_ctl.scala 1022:150] - node _T_891 = or(_T_890, csr_pkt.csr_mdseac) @[dec_tlu_ctl.scala 1022:172] - node _T_892 = or(_T_891, csr_pkt.csr_meihap) @[dec_tlu_ctl.scala 1022:193] - node _T_893 = and(io.dec_csr_wen_unq_d, _T_892) @[dec_tlu_ctl.scala 1022:82] - node _T_894 = not(_T_893) @[dec_tlu_ctl.scala 1022:59] - node _T_895 = and(_T_887, _T_894) @[dec_tlu_ctl.scala 1022:57] - io.dec_csr_legal_d <= _T_895 @[dec_tlu_ctl.scala 1022:20] + csr_read.io.dec_csr_rdaddr_d <= io.dec_csr_rdaddr_d @[dec_tlu_ctl.scala 1010:37] + csr_pkt.legal <= csr_read.io.csr_pkt.legal @[dec_tlu_ctl.scala 1011:16] + csr_pkt.postsync <= csr_read.io.csr_pkt.postsync @[dec_tlu_ctl.scala 1011:16] + csr_pkt.presync <= csr_read.io.csr_pkt.presync @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_dicago <= csr_read.io.csr_pkt.csr_dicago @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_dicad1 <= csr_read.io.csr_pkt.csr_dicad1 @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_dicad0 <= csr_read.io.csr_pkt.csr_dicad0 @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_dicad0h <= csr_read.io.csr_pkt.csr_dicad0h @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_dicawics <= csr_read.io.csr_pkt.csr_dicawics @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_mfdhs <= csr_read.io.csr_pkt.csr_mfdhs @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_mfdht <= csr_read.io.csr_pkt.csr_mfdht @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_mdccmect <= csr_read.io.csr_pkt.csr_mdccmect @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_miccmect <= csr_read.io.csr_pkt.csr_miccmect @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_micect <= csr_read.io.csr_pkt.csr_micect @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_mdeau <= csr_read.io.csr_pkt.csr_mdeau @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_meicpct <= csr_read.io.csr_pkt.csr_meicpct @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_mcpc <= csr_read.io.csr_pkt.csr_mcpc @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_mpmc <= csr_read.io.csr_pkt.csr_mpmc @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_mitcnt1 <= csr_read.io.csr_pkt.csr_mitcnt1 @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_mitcnt0 <= csr_read.io.csr_pkt.csr_mitcnt0 @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_mitb1 <= csr_read.io.csr_pkt.csr_mitb1 @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_mitb0 <= csr_read.io.csr_pkt.csr_mitb0 @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_mitctl1 <= csr_read.io.csr_pkt.csr_mitctl1 @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_mitctl0 <= csr_read.io.csr_pkt.csr_mitctl0 @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_mcountinhibit <= csr_read.io.csr_pkt.csr_mcountinhibit @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_mhpme6 <= csr_read.io.csr_pkt.csr_mhpme6 @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_mhpme5 <= csr_read.io.csr_pkt.csr_mhpme5 @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_mhpme4 <= csr_read.io.csr_pkt.csr_mhpme4 @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_mhpme3 <= csr_read.io.csr_pkt.csr_mhpme3 @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_mhpmc6h <= csr_read.io.csr_pkt.csr_mhpmc6h @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_mhpmc5h <= csr_read.io.csr_pkt.csr_mhpmc5h @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_mhpmc4h <= csr_read.io.csr_pkt.csr_mhpmc4h @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_mhpmc3h <= csr_read.io.csr_pkt.csr_mhpmc3h @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_mhpmc6 <= csr_read.io.csr_pkt.csr_mhpmc6 @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_mhpmc5 <= csr_read.io.csr_pkt.csr_mhpmc5 @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_mhpmc4 <= csr_read.io.csr_pkt.csr_mhpmc4 @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_mhpmc3 <= csr_read.io.csr_pkt.csr_mhpmc3 @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_mtdata2 <= csr_read.io.csr_pkt.csr_mtdata2 @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_mtdata1 <= csr_read.io.csr_pkt.csr_mtdata1 @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_mtsel <= csr_read.io.csr_pkt.csr_mtsel @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_dpc <= csr_read.io.csr_pkt.csr_dpc @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_mfdc <= csr_read.io.csr_pkt.csr_mfdc @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_mcgc <= csr_read.io.csr_pkt.csr_mcgc @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_dcsr <= csr_read.io.csr_pkt.csr_dcsr @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_meicidpl <= csr_read.io.csr_pkt.csr_meicidpl @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_meicurpl <= csr_read.io.csr_pkt.csr_meicurpl @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_meipt <= csr_read.io.csr_pkt.csr_meipt @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_meivt <= csr_read.io.csr_pkt.csr_meivt @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_meihap <= csr_read.io.csr_pkt.csr_meihap @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_mdseac <= csr_read.io.csr_pkt.csr_mdseac @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_dmst <= csr_read.io.csr_pkt.csr_dmst @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_mrac <= csr_read.io.csr_pkt.csr_mrac @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_mtval <= csr_read.io.csr_pkt.csr_mtval @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_mscause <= csr_read.io.csr_pkt.csr_mscause @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_mcause <= csr_read.io.csr_pkt.csr_mcause @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_mepc <= csr_read.io.csr_pkt.csr_mepc @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_mscratch <= csr_read.io.csr_pkt.csr_mscratch @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_minstreth <= csr_read.io.csr_pkt.csr_minstreth @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_minstretl <= csr_read.io.csr_pkt.csr_minstretl @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_mcycleh <= csr_read.io.csr_pkt.csr_mcycleh @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_mcyclel <= csr_read.io.csr_pkt.csr_mcyclel @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_mie <= csr_read.io.csr_pkt.csr_mie @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_mip <= csr_read.io.csr_pkt.csr_mip @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_mtvec <= csr_read.io.csr_pkt.csr_mtvec @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_mstatus <= csr_read.io.csr_pkt.csr_mstatus @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_mhartid <= csr_read.io.csr_pkt.csr_mhartid @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_mimpid <= csr_read.io.csr_pkt.csr_mimpid @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_marchid <= csr_read.io.csr_pkt.csr_marchid @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_mvendorid <= csr_read.io.csr_pkt.csr_mvendorid @[dec_tlu_ctl.scala 1011:16] + csr_pkt.csr_misa <= csr_read.io.csr_pkt.csr_misa @[dec_tlu_ctl.scala 1011:16] + node _T_864 = and(csr_pkt.presync, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 1013:42] + node _T_865 = not(io.dec_csr_wen_unq_d) @[dec_tlu_ctl.scala 1013:67] + node _T_866 = and(_T_864, _T_865) @[dec_tlu_ctl.scala 1013:65] + io.dec_tlu_presync_d <= _T_866 @[dec_tlu_ctl.scala 1013:23] + node _T_867 = and(csr_pkt.postsync, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 1014:43] + io.dec_tlu_postsync_d <= _T_867 @[dec_tlu_ctl.scala 1014:23] + node _T_868 = or(csr_pkt.csr_mitcnt0, csr_pkt.csr_mitcnt1) @[dec_tlu_ctl.scala 1017:50] + node _T_869 = or(_T_868, csr_pkt.csr_mitb0) @[dec_tlu_ctl.scala 1017:72] + node _T_870 = or(_T_869, csr_pkt.csr_mitb1) @[dec_tlu_ctl.scala 1017:92] + node _T_871 = or(_T_870, csr_pkt.csr_mitctl0) @[dec_tlu_ctl.scala 1017:112] + node _T_872 = or(_T_871, csr_pkt.csr_mitctl1) @[dec_tlu_ctl.scala 1017:134] + node _T_873 = not(UInt<1>("h01")) @[dec_tlu_ctl.scala 1017:159] + node conditionally_illegal = and(_T_872, _T_873) @[dec_tlu_ctl.scala 1017:157] + node _T_874 = or(csr_pkt.csr_dcsr, csr_pkt.csr_dpc) @[dec_tlu_ctl.scala 1018:55] + node _T_875 = or(_T_874, csr_pkt.csr_dmst) @[dec_tlu_ctl.scala 1018:73] + node _T_876 = or(_T_875, csr_pkt.csr_dicawics) @[dec_tlu_ctl.scala 1018:92] + node _T_877 = or(_T_876, csr_pkt.csr_dicad0) @[dec_tlu_ctl.scala 1018:115] + node _T_878 = or(_T_877, csr_pkt.csr_dicad0h) @[dec_tlu_ctl.scala 1018:136] + node _T_879 = or(_T_878, csr_pkt.csr_dicad1) @[dec_tlu_ctl.scala 1018:158] + node _T_880 = or(_T_879, csr_pkt.csr_dicago) @[dec_tlu_ctl.scala 1018:179] + node _T_881 = not(_T_880) @[dec_tlu_ctl.scala 1018:36] + node _T_882 = or(_T_881, dbg_tlu_halted_f) @[dec_tlu_ctl.scala 1018:201] + node _T_883 = and(csr_pkt.legal, _T_882) @[dec_tlu_ctl.scala 1018:33] + node _T_884 = not(fast_int_meicpct) @[dec_tlu_ctl.scala 1018:223] + node _T_885 = and(_T_883, _T_884) @[dec_tlu_ctl.scala 1018:221] + node _T_886 = not(conditionally_illegal) @[dec_tlu_ctl.scala 1018:243] + node valid_csr = and(_T_885, _T_886) @[dec_tlu_ctl.scala 1018:241] + node _T_887 = and(io.dec_csr_any_unq_d, valid_csr) @[dec_tlu_ctl.scala 1020:46] + node _T_888 = or(csr_pkt.csr_mvendorid, csr_pkt.csr_marchid) @[dec_tlu_ctl.scala 1020:107] + node _T_889 = or(_T_888, csr_pkt.csr_mimpid) @[dec_tlu_ctl.scala 1020:129] + node _T_890 = or(_T_889, csr_pkt.csr_mhartid) @[dec_tlu_ctl.scala 1020:150] + node _T_891 = or(_T_890, csr_pkt.csr_mdseac) @[dec_tlu_ctl.scala 1020:172] + node _T_892 = or(_T_891, csr_pkt.csr_meihap) @[dec_tlu_ctl.scala 1020:193] + node _T_893 = and(io.dec_csr_wen_unq_d, _T_892) @[dec_tlu_ctl.scala 1020:82] + node _T_894 = not(_T_893) @[dec_tlu_ctl.scala 1020:59] + node _T_895 = and(_T_887, _T_894) @[dec_tlu_ctl.scala 1020:57] + io.dec_csr_legal_d <= _T_895 @[dec_tlu_ctl.scala 1020:20] module dec_trigger : input clock : Clock @@ -81932,32 +81942,29 @@ circuit quasar_wrapper : node _T_12 = asUInt(reset) @[dbg.scala 102:55] node _T_13 = and(_T_11, _T_12) @[dbg.scala 102:41] node rst_temp = asAsyncReset(_T_13) @[dbg.scala 102:71] - node _T_14 = asUInt(dbg_dm_rst_l) @[dbg.scala 104:32] - node _T_15 = eq(_T_14, UInt<1>("h00")) @[dbg.scala 104:18] - node rst_not = asAsyncReset(_T_15) @[dbg.scala 104:52] - node _T_16 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 107:39] - node _T_17 = eq(_T_16, UInt<1>("h00")) @[dbg.scala 107:25] - node _T_18 = bits(_T_17, 0, 0) @[dbg.scala 107:50] - io.dbg_core_rst_l <= _T_18 @[dbg.scala 107:21] - node _T_19 = eq(io.dmi_reg_addr, UInt<6>("h038")) @[dbg.scala 108:36] - node _T_20 = and(_T_19, io.dmi_reg_en) @[dbg.scala 108:49] - node _T_21 = and(_T_20, io.dmi_reg_wr_en) @[dbg.scala 108:65] - node _T_22 = eq(sb_state, UInt<4>("h00")) @[dbg.scala 108:96] - node sbcs_wren = and(_T_21, _T_22) @[dbg.scala 108:84] - node _T_23 = bits(io.dmi_reg_wdata, 22, 22) @[dbg.scala 109:60] - node _T_24 = and(sbcs_wren, _T_23) @[dbg.scala 109:42] - node _T_25 = neq(sb_state, UInt<4>("h00")) @[dbg.scala 109:79] - node _T_26 = and(_T_25, io.dmi_reg_en) @[dbg.scala 109:102] - node _T_27 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[dbg.scala 110:23] - node _T_28 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 110:55] - node _T_29 = or(_T_27, _T_28) @[dbg.scala 110:36] - node _T_30 = eq(io.dmi_reg_addr, UInt<6>("h03d")) @[dbg.scala 110:87] - node _T_31 = or(_T_29, _T_30) @[dbg.scala 110:68] - node _T_32 = and(_T_26, _T_31) @[dbg.scala 109:118] - node sbcs_sbbusyerror_wren = or(_T_24, _T_32) @[dbg.scala 109:66] - node _T_33 = bits(io.dmi_reg_wdata, 22, 22) @[dbg.scala 112:61] - node _T_34 = and(sbcs_wren, _T_33) @[dbg.scala 112:43] - node sbcs_sbbusyerror_din = not(_T_34) @[dbg.scala 112:31] + node _T_14 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 105:39] + node _T_15 = eq(_T_14, UInt<1>("h00")) @[dbg.scala 105:25] + node _T_16 = bits(_T_15, 0, 0) @[dbg.scala 105:50] + io.dbg_core_rst_l <= _T_16 @[dbg.scala 105:21] + node _T_17 = eq(io.dmi_reg_addr, UInt<6>("h038")) @[dbg.scala 106:36] + node _T_18 = and(_T_17, io.dmi_reg_en) @[dbg.scala 106:49] + node _T_19 = and(_T_18, io.dmi_reg_wr_en) @[dbg.scala 106:65] + node _T_20 = eq(sb_state, UInt<4>("h00")) @[dbg.scala 106:96] + node sbcs_wren = and(_T_19, _T_20) @[dbg.scala 106:84] + node _T_21 = bits(io.dmi_reg_wdata, 22, 22) @[dbg.scala 107:60] + node _T_22 = and(sbcs_wren, _T_21) @[dbg.scala 107:42] + node _T_23 = neq(sb_state, UInt<4>("h00")) @[dbg.scala 107:79] + node _T_24 = and(_T_23, io.dmi_reg_en) @[dbg.scala 107:102] + node _T_25 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[dbg.scala 108:23] + node _T_26 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 108:55] + node _T_27 = or(_T_25, _T_26) @[dbg.scala 108:36] + node _T_28 = eq(io.dmi_reg_addr, UInt<6>("h03d")) @[dbg.scala 108:87] + node _T_29 = or(_T_27, _T_28) @[dbg.scala 108:68] + node _T_30 = and(_T_24, _T_29) @[dbg.scala 107:118] + node sbcs_sbbusyerror_wren = or(_T_22, _T_30) @[dbg.scala 107:66] + node _T_31 = bits(io.dmi_reg_wdata, 22, 22) @[dbg.scala 110:61] + node _T_32 = and(sbcs_wren, _T_31) @[dbg.scala 110:43] + node sbcs_sbbusyerror_din = not(_T_32) @[dbg.scala 110:31] reg temp_sbcs_22 : UInt, rvclkhdr_1.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] when sbcs_sbbusyerror_wren : @[Reg.scala 28:19] temp_sbcs_22 <= sbcs_sbbusyerror_din @[Reg.scala 28:23] @@ -81966,102 +81973,102 @@ circuit quasar_wrapper : when sbcs_sbbusy_wren : @[Reg.scala 28:19] temp_sbcs_21 <= sbcs_sbbusy_din @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_35 = bits(io.dmi_reg_wdata, 20, 20) @[dbg.scala 122:31] + node _T_33 = bits(io.dmi_reg_wdata, 20, 20) @[dbg.scala 120:31] reg temp_sbcs_20 : UInt, rvclkhdr_1.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] when sbcs_wren : @[Reg.scala 28:19] - temp_sbcs_20 <= _T_35 @[Reg.scala 28:23] + temp_sbcs_20 <= _T_33 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_36 = bits(io.dmi_reg_wdata, 19, 15) @[dbg.scala 126:31] + node _T_34 = bits(io.dmi_reg_wdata, 19, 15) @[dbg.scala 124:31] reg temp_sbcs_19_15 : UInt, rvclkhdr_1.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] when sbcs_wren : @[Reg.scala 28:19] - temp_sbcs_19_15 <= _T_36 @[Reg.scala 28:23] + temp_sbcs_19_15 <= _T_34 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_37 = bits(sbcs_sberror_din, 2, 0) @[dbg.scala 130:31] - reg temp_sbcs_14_12 : UInt, rvclkhdr_1.io.l1clk with : (reset => (rst_not, UInt<1>("h00"))) @[Reg.scala 27:20] + node _T_35 = bits(sbcs_sberror_din, 2, 0) @[dbg.scala 128:31] + reg temp_sbcs_14_12 : UInt, rvclkhdr_1.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] when sbcs_sberror_wren : @[Reg.scala 28:19] - temp_sbcs_14_12 <= _T_37 @[Reg.scala 28:23] + temp_sbcs_14_12 <= _T_35 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_38 = cat(UInt<7>("h020"), UInt<5>("h0f")) @[Cat.scala 29:58] - node _T_39 = cat(temp_sbcs_19_15, temp_sbcs_14_12) @[Cat.scala 29:58] - node _T_40 = cat(_T_39, _T_38) @[Cat.scala 29:58] - node _T_41 = cat(temp_sbcs_21, temp_sbcs_20) @[Cat.scala 29:58] - node _T_42 = cat(UInt<3>("h01"), UInt<6>("h00")) @[Cat.scala 29:58] - node _T_43 = cat(_T_42, temp_sbcs_22) @[Cat.scala 29:58] - node _T_44 = cat(_T_43, _T_41) @[Cat.scala 29:58] - node _T_45 = cat(_T_44, _T_40) @[Cat.scala 29:58] - sbcs_reg <= _T_45 @[dbg.scala 132:12] - node _T_46 = bits(sbcs_reg, 19, 17) @[dbg.scala 134:33] - node _T_47 = eq(_T_46, UInt<3>("h01")) @[dbg.scala 134:42] - node _T_48 = bits(sbaddress0_reg, 0, 0) @[dbg.scala 134:77] - node _T_49 = and(_T_47, _T_48) @[dbg.scala 134:61] - node _T_50 = bits(sbcs_reg, 19, 17) @[dbg.scala 135:14] - node _T_51 = eq(_T_50, UInt<3>("h02")) @[dbg.scala 135:23] - node _T_52 = bits(sbaddress0_reg, 1, 0) @[dbg.scala 135:58] - node _T_53 = orr(_T_52) @[dbg.scala 135:65] - node _T_54 = and(_T_51, _T_53) @[dbg.scala 135:42] - node _T_55 = or(_T_49, _T_54) @[dbg.scala 134:81] - node _T_56 = bits(sbcs_reg, 19, 17) @[dbg.scala 136:14] - node _T_57 = eq(_T_56, UInt<3>("h03")) @[dbg.scala 136:23] - node _T_58 = bits(sbaddress0_reg, 2, 0) @[dbg.scala 136:58] - node _T_59 = orr(_T_58) @[dbg.scala 136:65] - node _T_60 = and(_T_57, _T_59) @[dbg.scala 136:42] - node sbcs_unaligned = or(_T_55, _T_60) @[dbg.scala 135:69] - node sbcs_illegal_size = bits(sbcs_reg, 19, 19) @[dbg.scala 138:35] - node _T_61 = bits(sbcs_reg, 19, 17) @[dbg.scala 139:42] - node _T_62 = eq(_T_61, UInt<1>("h00")) @[dbg.scala 139:51] - node _T_63 = bits(_T_62, 0, 0) @[Bitwise.scala 72:15] - node _T_64 = mux(_T_63, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_65 = and(_T_64, UInt<4>("h01")) @[dbg.scala 139:64] - node _T_66 = bits(sbcs_reg, 19, 17) @[dbg.scala 139:100] - node _T_67 = eq(_T_66, UInt<1>("h01")) @[dbg.scala 139:109] - node _T_68 = bits(_T_67, 0, 0) @[Bitwise.scala 72:15] - node _T_69 = mux(_T_68, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_70 = and(_T_69, UInt<4>("h02")) @[dbg.scala 139:122] - node _T_71 = or(_T_65, _T_70) @[dbg.scala 139:81] - node _T_72 = bits(sbcs_reg, 19, 17) @[dbg.scala 140:22] - node _T_73 = eq(_T_72, UInt<2>("h02")) @[dbg.scala 140:31] - node _T_74 = bits(_T_73, 0, 0) @[Bitwise.scala 72:15] - node _T_75 = mux(_T_74, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_76 = and(_T_75, UInt<4>("h04")) @[dbg.scala 140:44] - node _T_77 = or(_T_71, _T_76) @[dbg.scala 139:139] - node _T_78 = bits(sbcs_reg, 19, 17) @[dbg.scala 140:80] - node _T_79 = eq(_T_78, UInt<2>("h03")) @[dbg.scala 140:89] - node _T_80 = bits(_T_79, 0, 0) @[Bitwise.scala 72:15] - node _T_81 = mux(_T_80, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_82 = and(_T_81, UInt<4>("h08")) @[dbg.scala 140:102] - node sbaddress0_incr = or(_T_77, _T_82) @[dbg.scala 140:61] - node _T_83 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 142:41] - node _T_84 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 142:79] - node sbdata0_reg_wren0 = and(_T_83, _T_84) @[dbg.scala 142:60] - node _T_85 = eq(sb_state, UInt<4>("h07")) @[dbg.scala 143:37] - node _T_86 = and(_T_85, sb_state_en) @[dbg.scala 143:60] - node _T_87 = eq(sbcs_sberror_wren, UInt<1>("h00")) @[dbg.scala 143:76] - node sbdata0_reg_wren1 = and(_T_86, _T_87) @[dbg.scala 143:74] - node sbdata0_reg_wren = or(sbdata0_reg_wren0, sbdata0_reg_wren1) @[dbg.scala 144:44] - node _T_88 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 145:41] - node _T_89 = eq(io.dmi_reg_addr, UInt<6>("h03d")) @[dbg.scala 145:79] - node sbdata1_reg_wren0 = and(_T_88, _T_89) @[dbg.scala 145:60] - node _T_90 = eq(sb_state, UInt<4>("h07")) @[dbg.scala 146:37] - node _T_91 = and(_T_90, sb_state_en) @[dbg.scala 146:60] - node _T_92 = eq(sbcs_sberror_wren, UInt<1>("h00")) @[dbg.scala 146:76] - node sbdata1_reg_wren1 = and(_T_91, _T_92) @[dbg.scala 146:74] - node sbdata1_reg_wren = or(sbdata1_reg_wren0, sbdata1_reg_wren1) @[dbg.scala 147:44] - node _T_93 = bits(sbdata0_reg_wren0, 0, 0) @[Bitwise.scala 72:15] - node _T_94 = mux(_T_93, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_95 = and(_T_94, io.dmi_reg_wdata) @[dbg.scala 148:49] - node _T_96 = bits(sbdata0_reg_wren1, 0, 0) @[Bitwise.scala 72:15] - node _T_97 = mux(_T_96, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_98 = bits(sb_bus_rdata, 31, 0) @[dbg.scala 149:47] - node _T_99 = and(_T_97, _T_98) @[dbg.scala 149:33] - node sbdata0_din = or(_T_95, _T_99) @[dbg.scala 148:68] - node _T_100 = bits(sbdata1_reg_wren0, 0, 0) @[Bitwise.scala 72:15] - node _T_101 = mux(_T_100, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_102 = and(_T_101, io.dmi_reg_wdata) @[dbg.scala 151:49] - node _T_103 = bits(sbdata1_reg_wren1, 0, 0) @[Bitwise.scala 72:15] - node _T_104 = mux(_T_103, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_105 = bits(sb_bus_rdata, 63, 32) @[dbg.scala 152:47] - node _T_106 = and(_T_104, _T_105) @[dbg.scala 152:33] - node sbdata1_din = or(_T_102, _T_106) @[dbg.scala 151:68] + node _T_36 = cat(UInt<7>("h020"), UInt<5>("h0f")) @[Cat.scala 29:58] + node _T_37 = cat(temp_sbcs_19_15, temp_sbcs_14_12) @[Cat.scala 29:58] + node _T_38 = cat(_T_37, _T_36) @[Cat.scala 29:58] + node _T_39 = cat(temp_sbcs_21, temp_sbcs_20) @[Cat.scala 29:58] + node _T_40 = cat(UInt<3>("h01"), UInt<6>("h00")) @[Cat.scala 29:58] + node _T_41 = cat(_T_40, temp_sbcs_22) @[Cat.scala 29:58] + node _T_42 = cat(_T_41, _T_39) @[Cat.scala 29:58] + node _T_43 = cat(_T_42, _T_38) @[Cat.scala 29:58] + sbcs_reg <= _T_43 @[dbg.scala 130:12] + node _T_44 = bits(sbcs_reg, 19, 17) @[dbg.scala 132:33] + node _T_45 = eq(_T_44, UInt<3>("h01")) @[dbg.scala 132:42] + node _T_46 = bits(sbaddress0_reg, 0, 0) @[dbg.scala 132:77] + node _T_47 = and(_T_45, _T_46) @[dbg.scala 132:61] + node _T_48 = bits(sbcs_reg, 19, 17) @[dbg.scala 133:14] + node _T_49 = eq(_T_48, UInt<3>("h02")) @[dbg.scala 133:23] + node _T_50 = bits(sbaddress0_reg, 1, 0) @[dbg.scala 133:58] + node _T_51 = orr(_T_50) @[dbg.scala 133:65] + node _T_52 = and(_T_49, _T_51) @[dbg.scala 133:42] + node _T_53 = or(_T_47, _T_52) @[dbg.scala 132:81] + node _T_54 = bits(sbcs_reg, 19, 17) @[dbg.scala 134:14] + node _T_55 = eq(_T_54, UInt<3>("h03")) @[dbg.scala 134:23] + node _T_56 = bits(sbaddress0_reg, 2, 0) @[dbg.scala 134:58] + node _T_57 = orr(_T_56) @[dbg.scala 134:65] + node _T_58 = and(_T_55, _T_57) @[dbg.scala 134:42] + node sbcs_unaligned = or(_T_53, _T_58) @[dbg.scala 133:69] + node sbcs_illegal_size = bits(sbcs_reg, 19, 19) @[dbg.scala 136:35] + node _T_59 = bits(sbcs_reg, 19, 17) @[dbg.scala 137:42] + node _T_60 = eq(_T_59, UInt<1>("h00")) @[dbg.scala 137:51] + node _T_61 = bits(_T_60, 0, 0) @[Bitwise.scala 72:15] + node _T_62 = mux(_T_61, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_63 = and(_T_62, UInt<4>("h01")) @[dbg.scala 137:64] + node _T_64 = bits(sbcs_reg, 19, 17) @[dbg.scala 137:100] + node _T_65 = eq(_T_64, UInt<1>("h01")) @[dbg.scala 137:109] + node _T_66 = bits(_T_65, 0, 0) @[Bitwise.scala 72:15] + node _T_67 = mux(_T_66, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_68 = and(_T_67, UInt<4>("h02")) @[dbg.scala 137:122] + node _T_69 = or(_T_63, _T_68) @[dbg.scala 137:81] + node _T_70 = bits(sbcs_reg, 19, 17) @[dbg.scala 138:22] + node _T_71 = eq(_T_70, UInt<2>("h02")) @[dbg.scala 138:31] + node _T_72 = bits(_T_71, 0, 0) @[Bitwise.scala 72:15] + node _T_73 = mux(_T_72, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_74 = and(_T_73, UInt<4>("h04")) @[dbg.scala 138:44] + node _T_75 = or(_T_69, _T_74) @[dbg.scala 137:139] + node _T_76 = bits(sbcs_reg, 19, 17) @[dbg.scala 138:80] + node _T_77 = eq(_T_76, UInt<2>("h03")) @[dbg.scala 138:89] + node _T_78 = bits(_T_77, 0, 0) @[Bitwise.scala 72:15] + node _T_79 = mux(_T_78, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_80 = and(_T_79, UInt<4>("h08")) @[dbg.scala 138:102] + node sbaddress0_incr = or(_T_75, _T_80) @[dbg.scala 138:61] + node _T_81 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 140:41] + node _T_82 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 140:79] + node sbdata0_reg_wren0 = and(_T_81, _T_82) @[dbg.scala 140:60] + node _T_83 = eq(sb_state, UInt<4>("h07")) @[dbg.scala 141:37] + node _T_84 = and(_T_83, sb_state_en) @[dbg.scala 141:60] + node _T_85 = eq(sbcs_sberror_wren, UInt<1>("h00")) @[dbg.scala 141:76] + node sbdata0_reg_wren1 = and(_T_84, _T_85) @[dbg.scala 141:74] + node sbdata0_reg_wren = or(sbdata0_reg_wren0, sbdata0_reg_wren1) @[dbg.scala 142:44] + node _T_86 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 143:41] + node _T_87 = eq(io.dmi_reg_addr, UInt<6>("h03d")) @[dbg.scala 143:79] + node sbdata1_reg_wren0 = and(_T_86, _T_87) @[dbg.scala 143:60] + node _T_88 = eq(sb_state, UInt<4>("h07")) @[dbg.scala 144:37] + node _T_89 = and(_T_88, sb_state_en) @[dbg.scala 144:60] + node _T_90 = eq(sbcs_sberror_wren, UInt<1>("h00")) @[dbg.scala 144:76] + node sbdata1_reg_wren1 = and(_T_89, _T_90) @[dbg.scala 144:74] + node sbdata1_reg_wren = or(sbdata1_reg_wren0, sbdata1_reg_wren1) @[dbg.scala 145:44] + node _T_91 = bits(sbdata0_reg_wren0, 0, 0) @[Bitwise.scala 72:15] + node _T_92 = mux(_T_91, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_93 = and(_T_92, io.dmi_reg_wdata) @[dbg.scala 146:49] + node _T_94 = bits(sbdata0_reg_wren1, 0, 0) @[Bitwise.scala 72:15] + node _T_95 = mux(_T_94, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_96 = bits(sb_bus_rdata, 31, 0) @[dbg.scala 147:47] + node _T_97 = and(_T_95, _T_96) @[dbg.scala 147:33] + node sbdata0_din = or(_T_93, _T_97) @[dbg.scala 146:68] + node _T_98 = bits(sbdata1_reg_wren0, 0, 0) @[Bitwise.scala 72:15] + node _T_99 = mux(_T_98, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_100 = and(_T_99, io.dmi_reg_wdata) @[dbg.scala 149:49] + node _T_101 = bits(sbdata1_reg_wren1, 0, 0) @[Bitwise.scala 72:15] + node _T_102 = mux(_T_101, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_103 = bits(sb_bus_rdata, 63, 32) @[dbg.scala 150:47] + node _T_104 = and(_T_102, _T_103) @[dbg.scala 150:33] + node sbdata1_din = or(_T_100, _T_104) @[dbg.scala 149:68] inst rvclkhdr_2 of rvclkhdr_757 @[lib.scala 368:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= dbg_dm_rst_l @@ -82078,241 +82085,241 @@ circuit quasar_wrapper : rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg sbdata1_reg : UInt, rvclkhdr_3.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[lib.scala 374:16] sbdata1_reg <= sbdata1_din @[lib.scala 374:16] - node _T_107 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 162:44] - node _T_108 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[dbg.scala 162:82] - node sbaddress0_reg_wren0 = and(_T_107, _T_108) @[dbg.scala 162:63] - node sbaddress0_reg_wren = or(sbaddress0_reg_wren0, sbaddress0_reg_wren1) @[dbg.scala 163:50] - node _T_109 = bits(sbaddress0_reg_wren0, 0, 0) @[Bitwise.scala 72:15] - node _T_110 = mux(_T_109, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_111 = and(_T_110, io.dmi_reg_wdata) @[dbg.scala 164:59] - node _T_112 = bits(sbaddress0_reg_wren1, 0, 0) @[Bitwise.scala 72:15] - node _T_113 = mux(_T_112, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_114 = cat(UInt<28>("h00"), sbaddress0_incr) @[Cat.scala 29:58] - node _T_115 = add(sbaddress0_reg, _T_114) @[dbg.scala 165:54] - node _T_116 = tail(_T_115, 1) @[dbg.scala 165:54] - node _T_117 = and(_T_113, _T_116) @[dbg.scala 165:36] - node sbaddress0_reg_din = or(_T_111, _T_117) @[dbg.scala 164:78] + node _T_105 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 160:44] + node _T_106 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[dbg.scala 160:82] + node sbaddress0_reg_wren0 = and(_T_105, _T_106) @[dbg.scala 160:63] + node sbaddress0_reg_wren = or(sbaddress0_reg_wren0, sbaddress0_reg_wren1) @[dbg.scala 161:50] + node _T_107 = bits(sbaddress0_reg_wren0, 0, 0) @[Bitwise.scala 72:15] + node _T_108 = mux(_T_107, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_109 = and(_T_108, io.dmi_reg_wdata) @[dbg.scala 162:59] + node _T_110 = bits(sbaddress0_reg_wren1, 0, 0) @[Bitwise.scala 72:15] + node _T_111 = mux(_T_110, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_112 = cat(UInt<28>("h00"), sbaddress0_incr) @[Cat.scala 29:58] + node _T_113 = add(sbaddress0_reg, _T_112) @[dbg.scala 163:54] + node _T_114 = tail(_T_113, 1) @[dbg.scala 163:54] + node _T_115 = and(_T_111, _T_114) @[dbg.scala 163:36] + node sbaddress0_reg_din = or(_T_109, _T_115) @[dbg.scala 162:78] inst rvclkhdr_4 of rvclkhdr_759 @[lib.scala 368:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= dbg_dm_rst_l rvclkhdr_4.io.clk <= clock @[lib.scala 370:18] rvclkhdr_4.io.en <= sbaddress0_reg_wren @[lib.scala 371:17] rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_118 : UInt, rvclkhdr_4.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[lib.scala 374:16] - _T_118 <= sbaddress0_reg_din @[lib.scala 374:16] - sbaddress0_reg <= _T_118 @[dbg.scala 166:18] - node _T_119 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 170:43] - node _T_120 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[dbg.scala 170:81] - node _T_121 = and(_T_119, _T_120) @[dbg.scala 170:62] - node _T_122 = bits(sbcs_reg, 20, 20) @[dbg.scala 170:104] - node sbreadonaddr_access = and(_T_121, _T_122) @[dbg.scala 170:94] - node _T_123 = eq(io.dmi_reg_wr_en, UInt<1>("h00")) @[dbg.scala 171:45] - node _T_124 = and(io.dmi_reg_en, _T_123) @[dbg.scala 171:43] - node _T_125 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 171:82] - node _T_126 = and(_T_124, _T_125) @[dbg.scala 171:63] - node _T_127 = bits(sbcs_reg, 15, 15) @[dbg.scala 171:105] - node sbreadondata_access = and(_T_126, _T_127) @[dbg.scala 171:95] - node _T_128 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 172:40] - node _T_129 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 172:78] - node sbdata0wr_access = and(_T_128, _T_129) @[dbg.scala 172:59] - node _T_130 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[dbg.scala 173:41] - node _T_131 = and(_T_130, io.dmi_reg_en) @[dbg.scala 173:54] - node dmcontrol_wren = and(_T_131, io.dmi_reg_wr_en) @[dbg.scala 173:70] - node _T_132 = bits(io.dmi_reg_wdata, 31, 30) @[dbg.scala 176:27] - node _T_133 = bits(io.dmi_reg_wdata, 28, 28) @[dbg.scala 176:53] - node _T_134 = bits(io.dmi_reg_wdata, 1, 1) @[dbg.scala 176:75] - node _T_135 = cat(_T_132, _T_133) @[Cat.scala 29:58] - node _T_136 = cat(_T_135, _T_134) @[Cat.scala 29:58] + reg _T_116 : UInt, rvclkhdr_4.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[lib.scala 374:16] + _T_116 <= sbaddress0_reg_din @[lib.scala 374:16] + sbaddress0_reg <= _T_116 @[dbg.scala 164:18] + node _T_117 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 168:43] + node _T_118 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[dbg.scala 168:81] + node _T_119 = and(_T_117, _T_118) @[dbg.scala 168:62] + node _T_120 = bits(sbcs_reg, 20, 20) @[dbg.scala 168:104] + node sbreadonaddr_access = and(_T_119, _T_120) @[dbg.scala 168:94] + node _T_121 = eq(io.dmi_reg_wr_en, UInt<1>("h00")) @[dbg.scala 169:45] + node _T_122 = and(io.dmi_reg_en, _T_121) @[dbg.scala 169:43] + node _T_123 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 169:82] + node _T_124 = and(_T_122, _T_123) @[dbg.scala 169:63] + node _T_125 = bits(sbcs_reg, 15, 15) @[dbg.scala 169:105] + node sbreadondata_access = and(_T_124, _T_125) @[dbg.scala 169:95] + node _T_126 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 170:40] + node _T_127 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 170:78] + node sbdata0wr_access = and(_T_126, _T_127) @[dbg.scala 170:59] + node _T_128 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[dbg.scala 171:41] + node _T_129 = and(_T_128, io.dmi_reg_en) @[dbg.scala 171:54] + node dmcontrol_wren = and(_T_129, io.dmi_reg_wr_en) @[dbg.scala 171:70] + node _T_130 = bits(io.dmi_reg_wdata, 31, 30) @[dbg.scala 174:27] + node _T_131 = bits(io.dmi_reg_wdata, 28, 28) @[dbg.scala 174:53] + node _T_132 = bits(io.dmi_reg_wdata, 1, 1) @[dbg.scala 174:75] + node _T_133 = cat(_T_130, _T_131) @[Cat.scala 29:58] + node _T_134 = cat(_T_133, _T_132) @[Cat.scala 29:58] reg dm_temp : UInt, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] when dmcontrol_wren : @[Reg.scala 28:19] - dm_temp <= _T_136 @[Reg.scala 28:23] + dm_temp <= _T_134 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_137 = asAsyncReset(io.dbg_rst_l) @[dbg.scala 180:76] - node _T_138 = bits(io.dmi_reg_wdata, 0, 0) @[dbg.scala 181:31] - reg dm_temp_0 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_137, UInt<1>("h00"))) @[Reg.scala 27:20] + node _T_135 = asAsyncReset(io.dbg_rst_l) @[dbg.scala 178:76] + node _T_136 = bits(io.dmi_reg_wdata, 0, 0) @[dbg.scala 179:31] + reg dm_temp_0 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_135, UInt<1>("h00"))) @[Reg.scala 27:20] when dmcontrol_wren : @[Reg.scala 28:19] - dm_temp_0 <= _T_138 @[Reg.scala 28:23] + dm_temp_0 <= _T_136 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_139 = bits(dm_temp, 3, 2) @[dbg.scala 184:25] - node _T_140 = bits(dm_temp, 1, 1) @[dbg.scala 184:45] - node _T_141 = bits(dm_temp, 0, 0) @[dbg.scala 184:68] - node _T_142 = cat(UInt<26>("h00"), _T_141) @[Cat.scala 29:58] - node _T_143 = cat(_T_142, dm_temp_0) @[Cat.scala 29:58] - node _T_144 = cat(_T_139, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_145 = cat(_T_144, _T_140) @[Cat.scala 29:58] - node temp = cat(_T_145, _T_143) @[Cat.scala 29:58] - dmcontrol_reg <= temp @[dbg.scala 185:17] - reg dmcontrol_wren_Q : UInt<1>, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[dbg.scala 188:12] - dmcontrol_wren_Q <= dmcontrol_wren @[dbg.scala 188:12] - node _T_146 = bits(dmstatus_havereset, 0, 0) @[Bitwise.scala 72:15] + node _T_137 = bits(dm_temp, 3, 2) @[dbg.scala 182:25] + node _T_138 = bits(dm_temp, 1, 1) @[dbg.scala 182:45] + node _T_139 = bits(dm_temp, 0, 0) @[dbg.scala 182:68] + node _T_140 = cat(UInt<26>("h00"), _T_139) @[Cat.scala 29:58] + node _T_141 = cat(_T_140, dm_temp_0) @[Cat.scala 29:58] + node _T_142 = cat(_T_137, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_143 = cat(_T_142, _T_138) @[Cat.scala 29:58] + node temp = cat(_T_143, _T_141) @[Cat.scala 29:58] + dmcontrol_reg <= temp @[dbg.scala 183:17] + reg dmcontrol_wren_Q : UInt<1>, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[dbg.scala 186:12] + dmcontrol_wren_Q <= dmcontrol_wren @[dbg.scala 186:12] + node _T_144 = bits(dmstatus_havereset, 0, 0) @[Bitwise.scala 72:15] + node _T_145 = mux(_T_144, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_146 = bits(dmstatus_resumeack, 0, 0) @[Bitwise.scala 72:15] node _T_147 = mux(_T_146, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_148 = bits(dmstatus_resumeack, 0, 0) @[Bitwise.scala 72:15] + node _T_148 = bits(dmstatus_unavail, 0, 0) @[Bitwise.scala 72:15] node _T_149 = mux(_T_148, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_150 = bits(dmstatus_unavail, 0, 0) @[Bitwise.scala 72:15] + node _T_150 = bits(dmstatus_running, 0, 0) @[Bitwise.scala 72:15] node _T_151 = mux(_T_150, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_152 = bits(dmstatus_running, 0, 0) @[Bitwise.scala 72:15] + node _T_152 = bits(dmstatus_halted, 0, 0) @[Bitwise.scala 72:15] node _T_153 = mux(_T_152, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_154 = bits(dmstatus_halted, 0, 0) @[Bitwise.scala 72:15] - node _T_155 = mux(_T_154, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_156 = cat(UInt<3>("h00"), UInt<4>("h02")) @[Cat.scala 29:58] - node _T_157 = cat(_T_153, _T_155) @[Cat.scala 29:58] - node _T_158 = cat(_T_157, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_159 = cat(_T_158, _T_156) @[Cat.scala 29:58] - node _T_160 = cat(UInt<2>("h00"), _T_151) @[Cat.scala 29:58] - node _T_161 = cat(UInt<12>("h00"), _T_147) @[Cat.scala 29:58] - node _T_162 = cat(_T_161, _T_149) @[Cat.scala 29:58] - node _T_163 = cat(_T_162, _T_160) @[Cat.scala 29:58] - node _T_164 = cat(_T_163, _T_159) @[Cat.scala 29:58] - dmstatus_reg <= _T_164 @[dbg.scala 191:16] - node _T_165 = eq(dbg_state, UInt<3>("h06")) @[dbg.scala 193:44] - node _T_166 = and(_T_165, io.dec_tlu_resume_ack) @[dbg.scala 193:66] - node _T_167 = bits(dmcontrol_reg, 30, 30) @[dbg.scala 193:127] - node _T_168 = eq(_T_167, UInt<1>("h00")) @[dbg.scala 193:113] - node _T_169 = and(dmstatus_resumeack, _T_168) @[dbg.scala 193:111] - node dmstatus_resumeack_wren = or(_T_166, _T_169) @[dbg.scala 193:90] - node _T_170 = eq(dbg_state, UInt<3>("h06")) @[dbg.scala 194:43] - node dmstatus_resumeack_din = and(_T_170, io.dec_tlu_resume_ack) @[dbg.scala 194:65] - node _T_171 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[dbg.scala 195:50] - node _T_172 = bits(io.dmi_reg_wdata, 1, 1) @[dbg.scala 195:81] - node _T_173 = and(_T_171, _T_172) @[dbg.scala 195:63] - node _T_174 = and(_T_173, io.dmi_reg_en) @[dbg.scala 195:85] - node dmstatus_havereset_wren = and(_T_174, io.dmi_reg_wr_en) @[dbg.scala 195:101] - node _T_175 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[dbg.scala 196:49] - node _T_176 = bits(io.dmi_reg_wdata, 28, 28) @[dbg.scala 196:80] - node _T_177 = and(_T_175, _T_176) @[dbg.scala 196:62] - node _T_178 = and(_T_177, io.dmi_reg_en) @[dbg.scala 196:85] - node dmstatus_havereset_rst = and(_T_178, io.dmi_reg_wr_en) @[dbg.scala 196:101] - node temp_rst = asUInt(reset) @[dbg.scala 197:30] - node _T_179 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 198:37] - node _T_180 = eq(temp_rst, UInt<1>("h00")) @[dbg.scala 198:43] - node _T_181 = or(_T_179, _T_180) @[dbg.scala 198:41] - node _T_182 = bits(_T_181, 0, 0) @[dbg.scala 198:62] - dmstatus_unavail <= _T_182 @[dbg.scala 198:20] - node _T_183 = or(dmstatus_unavail, dmstatus_halted) @[dbg.scala 199:42] - node _T_184 = not(_T_183) @[dbg.scala 199:23] - dmstatus_running <= _T_184 @[dbg.scala 199:20] - reg _T_185 : UInt, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] + node _T_154 = cat(UInt<3>("h00"), UInt<4>("h02")) @[Cat.scala 29:58] + node _T_155 = cat(_T_151, _T_153) @[Cat.scala 29:58] + node _T_156 = cat(_T_155, UInt<1>("h01")) @[Cat.scala 29:58] + node _T_157 = cat(_T_156, _T_154) @[Cat.scala 29:58] + node _T_158 = cat(UInt<2>("h00"), _T_149) @[Cat.scala 29:58] + node _T_159 = cat(UInt<12>("h00"), _T_145) @[Cat.scala 29:58] + node _T_160 = cat(_T_159, _T_147) @[Cat.scala 29:58] + node _T_161 = cat(_T_160, _T_158) @[Cat.scala 29:58] + node _T_162 = cat(_T_161, _T_157) @[Cat.scala 29:58] + dmstatus_reg <= _T_162 @[dbg.scala 189:16] + node _T_163 = eq(dbg_state, UInt<3>("h06")) @[dbg.scala 191:44] + node _T_164 = and(_T_163, io.dec_tlu_resume_ack) @[dbg.scala 191:66] + node _T_165 = bits(dmcontrol_reg, 30, 30) @[dbg.scala 191:127] + node _T_166 = eq(_T_165, UInt<1>("h00")) @[dbg.scala 191:113] + node _T_167 = and(dmstatus_resumeack, _T_166) @[dbg.scala 191:111] + node dmstatus_resumeack_wren = or(_T_164, _T_167) @[dbg.scala 191:90] + node _T_168 = eq(dbg_state, UInt<3>("h06")) @[dbg.scala 192:43] + node dmstatus_resumeack_din = and(_T_168, io.dec_tlu_resume_ack) @[dbg.scala 192:65] + node _T_169 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[dbg.scala 193:50] + node _T_170 = bits(io.dmi_reg_wdata, 1, 1) @[dbg.scala 193:81] + node _T_171 = and(_T_169, _T_170) @[dbg.scala 193:63] + node _T_172 = and(_T_171, io.dmi_reg_en) @[dbg.scala 193:85] + node dmstatus_havereset_wren = and(_T_172, io.dmi_reg_wr_en) @[dbg.scala 193:101] + node _T_173 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[dbg.scala 194:49] + node _T_174 = bits(io.dmi_reg_wdata, 28, 28) @[dbg.scala 194:80] + node _T_175 = and(_T_173, _T_174) @[dbg.scala 194:62] + node _T_176 = and(_T_175, io.dmi_reg_en) @[dbg.scala 194:85] + node dmstatus_havereset_rst = and(_T_176, io.dmi_reg_wr_en) @[dbg.scala 194:101] + node temp_rst = asUInt(reset) @[dbg.scala 195:30] + node _T_177 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 196:37] + node _T_178 = eq(temp_rst, UInt<1>("h00")) @[dbg.scala 196:43] + node _T_179 = or(_T_177, _T_178) @[dbg.scala 196:41] + node _T_180 = bits(_T_179, 0, 0) @[dbg.scala 196:62] + dmstatus_unavail <= _T_180 @[dbg.scala 196:20] + node _T_181 = or(dmstatus_unavail, dmstatus_halted) @[dbg.scala 197:42] + node _T_182 = not(_T_181) @[dbg.scala 197:23] + dmstatus_running <= _T_182 @[dbg.scala 197:20] + reg _T_183 : UInt, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] when dmstatus_resumeack_wren : @[Reg.scala 28:19] - _T_185 <= dmstatus_resumeack_din @[Reg.scala 28:23] + _T_183 <= dmstatus_resumeack_din @[Reg.scala 28:23] skip @[Reg.scala 28:19] - dmstatus_resumeack <= _T_185 @[dbg.scala 200:22] - node _T_186 = eq(io.dec_tlu_mpc_halted_only, UInt<1>("h00")) @[dbg.scala 205:37] - node _T_187 = and(io.dec_tlu_dbg_halted, _T_186) @[dbg.scala 205:35] - reg _T_188 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[dbg.scala 205:12] - _T_188 <= _T_187 @[dbg.scala 205:12] - dmstatus_halted <= _T_188 @[dbg.scala 204:19] - node _T_189 = mux(dmstatus_havereset_wren, UInt<1>("h01"), dmstatus_havereset) @[dbg.scala 209:16] - node _T_190 = eq(dmstatus_havereset_rst, UInt<1>("h00")) @[dbg.scala 209:72] - node _T_191 = and(_T_189, _T_190) @[dbg.scala 209:70] - reg _T_192 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[dbg.scala 209:12] - _T_192 <= _T_191 @[dbg.scala 209:12] - dmstatus_havereset <= _T_192 @[dbg.scala 208:22] + dmstatus_resumeack <= _T_183 @[dbg.scala 198:22] + node _T_184 = eq(io.dec_tlu_mpc_halted_only, UInt<1>("h00")) @[dbg.scala 203:37] + node _T_185 = and(io.dec_tlu_dbg_halted, _T_184) @[dbg.scala 203:35] + reg _T_186 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[dbg.scala 203:12] + _T_186 <= _T_185 @[dbg.scala 203:12] + dmstatus_halted <= _T_186 @[dbg.scala 202:19] + node _T_187 = mux(dmstatus_havereset_wren, UInt<1>("h01"), dmstatus_havereset) @[dbg.scala 207:16] + node _T_188 = eq(dmstatus_havereset_rst, UInt<1>("h00")) @[dbg.scala 207:72] + node _T_189 = and(_T_187, _T_188) @[dbg.scala 207:70] + reg _T_190 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[dbg.scala 207:12] + _T_190 <= _T_189 @[dbg.scala 207:12] + dmstatus_havereset <= _T_190 @[dbg.scala 206:22] node haltsum0_reg = cat(UInt<31>("h00"), dmstatus_halted) @[Cat.scala 29:58] wire abstractcs_reg : UInt<32> abstractcs_reg <= UInt<32>("h02") - node _T_193 = bits(abstractcs_reg, 12, 12) @[dbg.scala 215:45] - node _T_194 = and(_T_193, io.dmi_reg_en) @[dbg.scala 215:50] - node _T_195 = eq(io.dmi_reg_addr, UInt<5>("h016")) @[dbg.scala 215:106] - node _T_196 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 215:138] - node _T_197 = or(_T_195, _T_196) @[dbg.scala 215:119] - node _T_198 = and(io.dmi_reg_wr_en, _T_197) @[dbg.scala 215:86] - node _T_199 = eq(io.dmi_reg_addr, UInt<3>("h04")) @[dbg.scala 215:171] - node _T_200 = or(_T_198, _T_199) @[dbg.scala 215:152] - node abstractcs_error_sel0 = and(_T_194, _T_200) @[dbg.scala 215:66] - node _T_201 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 216:45] - node _T_202 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 216:83] - node _T_203 = and(_T_201, _T_202) @[dbg.scala 216:64] - node _T_204 = bits(io.dmi_reg_wdata, 31, 24) @[dbg.scala 216:117] - node _T_205 = eq(_T_204, UInt<1>("h00")) @[dbg.scala 216:126] - node _T_206 = bits(io.dmi_reg_wdata, 31, 24) @[dbg.scala 216:154] - node _T_207 = eq(_T_206, UInt<2>("h02")) @[dbg.scala 216:163] - node _T_208 = or(_T_205, _T_207) @[dbg.scala 216:135] - node _T_209 = eq(_T_208, UInt<1>("h00")) @[dbg.scala 216:98] - node abstractcs_error_sel1 = and(_T_203, _T_209) @[dbg.scala 216:96] - node abstractcs_error_sel2 = and(io.core_dbg_cmd_done, io.core_dbg_cmd_fail) @[dbg.scala 217:52] - node _T_210 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 218:45] - node _T_211 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 218:83] - node _T_212 = and(_T_210, _T_211) @[dbg.scala 218:64] - node _T_213 = bits(dmstatus_reg, 9, 9) @[dbg.scala 218:111] - node _T_214 = eq(_T_213, UInt<1>("h00")) @[dbg.scala 218:98] - node abstractcs_error_sel3 = and(_T_212, _T_214) @[dbg.scala 218:96] - node _T_215 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 219:48] - node _T_216 = and(_T_215, io.dmi_reg_en) @[dbg.scala 219:61] - node _T_217 = and(_T_216, io.dmi_reg_wr_en) @[dbg.scala 219:77] - node _T_218 = bits(io.dmi_reg_wdata, 22, 20) @[dbg.scala 220:23] - node _T_219 = neq(_T_218, UInt<3>("h02")) @[dbg.scala 220:32] - node _T_220 = bits(io.dmi_reg_wdata, 31, 24) @[dbg.scala 220:71] - node _T_221 = eq(_T_220, UInt<2>("h02")) @[dbg.scala 220:80] - node _T_222 = bits(data1_reg, 1, 0) @[dbg.scala 220:104] - node _T_223 = orr(_T_222) @[dbg.scala 220:111] - node _T_224 = and(_T_221, _T_223) @[dbg.scala 220:92] - node _T_225 = or(_T_219, _T_224) @[dbg.scala 220:51] - node abstractcs_error_sel4 = and(_T_217, _T_225) @[dbg.scala 219:96] - node _T_226 = eq(io.dmi_reg_addr, UInt<5>("h016")) @[dbg.scala 222:48] - node _T_227 = and(_T_226, io.dmi_reg_en) @[dbg.scala 222:61] - node abstractcs_error_sel5 = and(_T_227, io.dmi_reg_wr_en) @[dbg.scala 222:77] - node _T_228 = or(abstractcs_error_sel0, abstractcs_error_sel1) @[dbg.scala 223:54] - node _T_229 = or(_T_228, abstractcs_error_sel2) @[dbg.scala 223:78] - node _T_230 = or(_T_229, abstractcs_error_sel3) @[dbg.scala 223:102] - node _T_231 = or(_T_230, abstractcs_error_sel4) @[dbg.scala 223:126] - node abstractcs_error_selor = or(_T_231, abstractcs_error_sel5) @[dbg.scala 223:150] - node _T_232 = bits(abstractcs_error_sel0, 0, 0) @[Bitwise.scala 72:15] - node _T_233 = mux(_T_232, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_234 = and(_T_233, UInt<3>("h01")) @[dbg.scala 224:62] - node _T_235 = bits(abstractcs_error_sel1, 0, 0) @[Bitwise.scala 72:15] - node _T_236 = mux(_T_235, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_237 = and(_T_236, UInt<3>("h02")) @[dbg.scala 225:37] - node _T_238 = or(_T_234, _T_237) @[dbg.scala 224:79] - node _T_239 = bits(abstractcs_error_sel2, 0, 0) @[Bitwise.scala 72:15] - node _T_240 = mux(_T_239, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_241 = and(_T_240, UInt<3>("h03")) @[dbg.scala 226:37] - node _T_242 = or(_T_238, _T_241) @[dbg.scala 225:54] - node _T_243 = bits(abstractcs_error_sel3, 0, 0) @[Bitwise.scala 72:15] - node _T_244 = mux(_T_243, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_245 = and(_T_244, UInt<3>("h04")) @[dbg.scala 227:37] - node _T_246 = or(_T_242, _T_245) @[dbg.scala 226:54] - node _T_247 = bits(abstractcs_error_sel4, 0, 0) @[Bitwise.scala 72:15] - node _T_248 = mux(_T_247, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_249 = and(_T_248, UInt<3>("h07")) @[dbg.scala 228:37] - node _T_250 = or(_T_246, _T_249) @[dbg.scala 227:54] - node _T_251 = bits(abstractcs_error_sel5, 0, 0) @[Bitwise.scala 72:15] - node _T_252 = mux(_T_251, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_253 = bits(io.dmi_reg_wdata, 10, 8) @[dbg.scala 229:57] - node _T_254 = not(_T_253) @[dbg.scala 229:40] - node _T_255 = and(_T_252, _T_254) @[dbg.scala 229:37] - node _T_256 = bits(abstractcs_reg, 10, 8) @[dbg.scala 229:91] - node _T_257 = and(_T_255, _T_256) @[dbg.scala 229:75] - node _T_258 = or(_T_250, _T_257) @[dbg.scala 228:54] - node _T_259 = not(abstractcs_error_selor) @[dbg.scala 230:15] - node _T_260 = bits(_T_259, 0, 0) @[Bitwise.scala 72:15] - node _T_261 = mux(_T_260, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_262 = bits(abstractcs_reg, 10, 8) @[dbg.scala 230:66] - node _T_263 = and(_T_261, _T_262) @[dbg.scala 230:50] - node abstractcs_error_din = or(_T_258, _T_263) @[dbg.scala 229:100] + node _T_191 = bits(abstractcs_reg, 12, 12) @[dbg.scala 213:45] + node _T_192 = and(_T_191, io.dmi_reg_en) @[dbg.scala 213:50] + node _T_193 = eq(io.dmi_reg_addr, UInt<5>("h016")) @[dbg.scala 213:106] + node _T_194 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 213:138] + node _T_195 = or(_T_193, _T_194) @[dbg.scala 213:119] + node _T_196 = and(io.dmi_reg_wr_en, _T_195) @[dbg.scala 213:86] + node _T_197 = eq(io.dmi_reg_addr, UInt<3>("h04")) @[dbg.scala 213:171] + node _T_198 = or(_T_196, _T_197) @[dbg.scala 213:152] + node abstractcs_error_sel0 = and(_T_192, _T_198) @[dbg.scala 213:66] + node _T_199 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 214:45] + node _T_200 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 214:83] + node _T_201 = and(_T_199, _T_200) @[dbg.scala 214:64] + node _T_202 = bits(io.dmi_reg_wdata, 31, 24) @[dbg.scala 214:117] + node _T_203 = eq(_T_202, UInt<1>("h00")) @[dbg.scala 214:126] + node _T_204 = bits(io.dmi_reg_wdata, 31, 24) @[dbg.scala 214:154] + node _T_205 = eq(_T_204, UInt<2>("h02")) @[dbg.scala 214:163] + node _T_206 = or(_T_203, _T_205) @[dbg.scala 214:135] + node _T_207 = eq(_T_206, UInt<1>("h00")) @[dbg.scala 214:98] + node abstractcs_error_sel1 = and(_T_201, _T_207) @[dbg.scala 214:96] + node abstractcs_error_sel2 = and(io.core_dbg_cmd_done, io.core_dbg_cmd_fail) @[dbg.scala 215:52] + node _T_208 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 216:45] + node _T_209 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 216:83] + node _T_210 = and(_T_208, _T_209) @[dbg.scala 216:64] + node _T_211 = bits(dmstatus_reg, 9, 9) @[dbg.scala 216:111] + node _T_212 = eq(_T_211, UInt<1>("h00")) @[dbg.scala 216:98] + node abstractcs_error_sel3 = and(_T_210, _T_212) @[dbg.scala 216:96] + node _T_213 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 217:48] + node _T_214 = and(_T_213, io.dmi_reg_en) @[dbg.scala 217:61] + node _T_215 = and(_T_214, io.dmi_reg_wr_en) @[dbg.scala 217:77] + node _T_216 = bits(io.dmi_reg_wdata, 22, 20) @[dbg.scala 218:23] + node _T_217 = neq(_T_216, UInt<3>("h02")) @[dbg.scala 218:32] + node _T_218 = bits(io.dmi_reg_wdata, 31, 24) @[dbg.scala 218:71] + node _T_219 = eq(_T_218, UInt<2>("h02")) @[dbg.scala 218:80] + node _T_220 = bits(data1_reg, 1, 0) @[dbg.scala 218:104] + node _T_221 = orr(_T_220) @[dbg.scala 218:111] + node _T_222 = and(_T_219, _T_221) @[dbg.scala 218:92] + node _T_223 = or(_T_217, _T_222) @[dbg.scala 218:51] + node abstractcs_error_sel4 = and(_T_215, _T_223) @[dbg.scala 217:96] + node _T_224 = eq(io.dmi_reg_addr, UInt<5>("h016")) @[dbg.scala 220:48] + node _T_225 = and(_T_224, io.dmi_reg_en) @[dbg.scala 220:61] + node abstractcs_error_sel5 = and(_T_225, io.dmi_reg_wr_en) @[dbg.scala 220:77] + node _T_226 = or(abstractcs_error_sel0, abstractcs_error_sel1) @[dbg.scala 221:54] + node _T_227 = or(_T_226, abstractcs_error_sel2) @[dbg.scala 221:78] + node _T_228 = or(_T_227, abstractcs_error_sel3) @[dbg.scala 221:102] + node _T_229 = or(_T_228, abstractcs_error_sel4) @[dbg.scala 221:126] + node abstractcs_error_selor = or(_T_229, abstractcs_error_sel5) @[dbg.scala 221:150] + node _T_230 = bits(abstractcs_error_sel0, 0, 0) @[Bitwise.scala 72:15] + node _T_231 = mux(_T_230, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_232 = and(_T_231, UInt<3>("h01")) @[dbg.scala 222:62] + node _T_233 = bits(abstractcs_error_sel1, 0, 0) @[Bitwise.scala 72:15] + node _T_234 = mux(_T_233, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_235 = and(_T_234, UInt<3>("h02")) @[dbg.scala 223:37] + node _T_236 = or(_T_232, _T_235) @[dbg.scala 222:79] + node _T_237 = bits(abstractcs_error_sel2, 0, 0) @[Bitwise.scala 72:15] + node _T_238 = mux(_T_237, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_239 = and(_T_238, UInt<3>("h03")) @[dbg.scala 224:37] + node _T_240 = or(_T_236, _T_239) @[dbg.scala 223:54] + node _T_241 = bits(abstractcs_error_sel3, 0, 0) @[Bitwise.scala 72:15] + node _T_242 = mux(_T_241, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_243 = and(_T_242, UInt<3>("h04")) @[dbg.scala 225:37] + node _T_244 = or(_T_240, _T_243) @[dbg.scala 224:54] + node _T_245 = bits(abstractcs_error_sel4, 0, 0) @[Bitwise.scala 72:15] + node _T_246 = mux(_T_245, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_247 = and(_T_246, UInt<3>("h07")) @[dbg.scala 226:37] + node _T_248 = or(_T_244, _T_247) @[dbg.scala 225:54] + node _T_249 = bits(abstractcs_error_sel5, 0, 0) @[Bitwise.scala 72:15] + node _T_250 = mux(_T_249, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_251 = bits(io.dmi_reg_wdata, 10, 8) @[dbg.scala 227:57] + node _T_252 = not(_T_251) @[dbg.scala 227:40] + node _T_253 = and(_T_250, _T_252) @[dbg.scala 227:37] + node _T_254 = bits(abstractcs_reg, 10, 8) @[dbg.scala 227:91] + node _T_255 = and(_T_253, _T_254) @[dbg.scala 227:75] + node _T_256 = or(_T_248, _T_255) @[dbg.scala 226:54] + node _T_257 = not(abstractcs_error_selor) @[dbg.scala 228:15] + node _T_258 = bits(_T_257, 0, 0) @[Bitwise.scala 72:15] + node _T_259 = mux(_T_258, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_260 = bits(abstractcs_reg, 10, 8) @[dbg.scala 228:66] + node _T_261 = and(_T_259, _T_260) @[dbg.scala 228:50] + node abstractcs_error_din = or(_T_256, _T_261) @[dbg.scala 227:100] reg abs_temp_12 : UInt, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] when abstractcs_busy_wren : @[Reg.scala 28:19] abs_temp_12 <= abstractcs_busy_din @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_264 = bits(abstractcs_error_din, 2, 0) @[dbg.scala 237:33] - reg abs_temp_10_8 : UInt, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[dbg.scala 237:12] - abs_temp_10_8 <= _T_264 @[dbg.scala 237:12] - node _T_265 = cat(abs_temp_10_8, UInt<8>("h02")) @[Cat.scala 29:58] - node _T_266 = cat(UInt<19>("h00"), abs_temp_12) @[Cat.scala 29:58] - node _T_267 = cat(_T_266, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_268 = cat(_T_267, _T_265) @[Cat.scala 29:58] - abstractcs_reg <= _T_268 @[dbg.scala 240:18] - node _T_269 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 242:39] - node _T_270 = and(_T_269, io.dmi_reg_en) @[dbg.scala 242:52] - node _T_271 = and(_T_270, io.dmi_reg_wr_en) @[dbg.scala 242:68] - node _T_272 = eq(dbg_state, UInt<3>("h02")) @[dbg.scala 242:100] - node command_wren = and(_T_271, _T_272) @[dbg.scala 242:87] - node _T_273 = bits(io.dmi_reg_wdata, 31, 24) @[dbg.scala 243:41] - node _T_274 = bits(io.dmi_reg_wdata, 22, 20) @[dbg.scala 243:77] - node _T_275 = bits(io.dmi_reg_wdata, 16, 0) @[dbg.scala 243:113] - node _T_276 = cat(UInt<3>("h00"), _T_275) @[Cat.scala 29:58] - node _T_277 = cat(_T_273, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_278 = cat(_T_277, _T_274) @[Cat.scala 29:58] - node command_din = cat(_T_278, _T_276) @[Cat.scala 29:58] + node _T_262 = bits(abstractcs_error_din, 2, 0) @[dbg.scala 235:33] + reg abs_temp_10_8 : UInt, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[dbg.scala 235:12] + abs_temp_10_8 <= _T_262 @[dbg.scala 235:12] + node _T_263 = cat(abs_temp_10_8, UInt<8>("h02")) @[Cat.scala 29:58] + node _T_264 = cat(UInt<19>("h00"), abs_temp_12) @[Cat.scala 29:58] + node _T_265 = cat(_T_264, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_266 = cat(_T_265, _T_263) @[Cat.scala 29:58] + abstractcs_reg <= _T_266 @[dbg.scala 238:18] + node _T_267 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 240:39] + node _T_268 = and(_T_267, io.dmi_reg_en) @[dbg.scala 240:52] + node _T_269 = and(_T_268, io.dmi_reg_wr_en) @[dbg.scala 240:68] + node _T_270 = eq(dbg_state, UInt<3>("h02")) @[dbg.scala 240:100] + node command_wren = and(_T_269, _T_270) @[dbg.scala 240:87] + node _T_271 = bits(io.dmi_reg_wdata, 31, 24) @[dbg.scala 241:41] + node _T_272 = bits(io.dmi_reg_wdata, 22, 20) @[dbg.scala 241:77] + node _T_273 = bits(io.dmi_reg_wdata, 16, 0) @[dbg.scala 241:113] + node _T_274 = cat(UInt<3>("h00"), _T_273) @[Cat.scala 29:58] + node _T_275 = cat(_T_271, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_276 = cat(_T_275, _T_272) @[Cat.scala 29:58] + node command_din = cat(_T_276, _T_274) @[Cat.scala 29:58] inst rvclkhdr_5 of rvclkhdr_760 @[lib.scala 368:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= dbg_dm_rst_l @@ -82321,24 +82328,24 @@ circuit quasar_wrapper : rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg command_reg : UInt, rvclkhdr_5.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[lib.scala 374:16] command_reg <= command_din @[lib.scala 374:16] - node _T_279 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 248:39] - node _T_280 = eq(io.dmi_reg_addr, UInt<3>("h04")) @[dbg.scala 248:77] - node _T_281 = and(_T_279, _T_280) @[dbg.scala 248:58] - node _T_282 = eq(dbg_state, UInt<3>("h02")) @[dbg.scala 248:102] - node data0_reg_wren0 = and(_T_281, _T_282) @[dbg.scala 248:89] - node _T_283 = eq(dbg_state, UInt<3>("h04")) @[dbg.scala 249:59] - node _T_284 = and(io.core_dbg_cmd_done, _T_283) @[dbg.scala 249:46] - node _T_285 = bits(command_reg, 16, 16) @[dbg.scala 249:95] - node _T_286 = eq(_T_285, UInt<1>("h00")) @[dbg.scala 249:83] - node data0_reg_wren1 = and(_T_284, _T_286) @[dbg.scala 249:81] - node data0_reg_wren = or(data0_reg_wren0, data0_reg_wren1) @[dbg.scala 251:40] - node _T_287 = bits(data0_reg_wren0, 0, 0) @[Bitwise.scala 72:15] - node _T_288 = mux(_T_287, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_289 = and(_T_288, io.dmi_reg_wdata) @[dbg.scala 252:45] - node _T_290 = bits(data0_reg_wren1, 0, 0) @[Bitwise.scala 72:15] - node _T_291 = mux(_T_290, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_292 = and(_T_291, io.core_dbg_rddata) @[dbg.scala 252:92] - node data0_din = or(_T_289, _T_292) @[dbg.scala 252:64] + node _T_277 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 246:39] + node _T_278 = eq(io.dmi_reg_addr, UInt<3>("h04")) @[dbg.scala 246:77] + node _T_279 = and(_T_277, _T_278) @[dbg.scala 246:58] + node _T_280 = eq(dbg_state, UInt<3>("h02")) @[dbg.scala 246:102] + node data0_reg_wren0 = and(_T_279, _T_280) @[dbg.scala 246:89] + node _T_281 = eq(dbg_state, UInt<3>("h04")) @[dbg.scala 247:59] + node _T_282 = and(io.core_dbg_cmd_done, _T_281) @[dbg.scala 247:46] + node _T_283 = bits(command_reg, 16, 16) @[dbg.scala 247:95] + node _T_284 = eq(_T_283, UInt<1>("h00")) @[dbg.scala 247:83] + node data0_reg_wren1 = and(_T_282, _T_284) @[dbg.scala 247:81] + node data0_reg_wren = or(data0_reg_wren0, data0_reg_wren1) @[dbg.scala 249:40] + node _T_285 = bits(data0_reg_wren0, 0, 0) @[Bitwise.scala 72:15] + node _T_286 = mux(_T_285, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_287 = and(_T_286, io.dmi_reg_wdata) @[dbg.scala 250:45] + node _T_288 = bits(data0_reg_wren1, 0, 0) @[Bitwise.scala 72:15] + node _T_289 = mux(_T_288, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_290 = and(_T_289, io.core_dbg_rddata) @[dbg.scala 250:92] + node data0_din = or(_T_287, _T_290) @[dbg.scala 250:64] inst rvclkhdr_6 of rvclkhdr_761 @[lib.scala 368:23] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= dbg_dm_rst_l @@ -82347,588 +82354,588 @@ circuit quasar_wrapper : rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg data0_reg : UInt, rvclkhdr_6.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[lib.scala 374:16] data0_reg <= data0_din @[lib.scala 374:16] - node _T_293 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 257:39] - node _T_294 = eq(io.dmi_reg_addr, UInt<3>("h05")) @[dbg.scala 257:77] - node _T_295 = and(_T_293, _T_294) @[dbg.scala 257:58] - node _T_296 = eq(dbg_state, UInt<3>("h02")) @[dbg.scala 257:102] - node data1_reg_wren = and(_T_295, _T_296) @[dbg.scala 257:89] - node _T_297 = bits(data1_reg_wren, 0, 0) @[Bitwise.scala 72:15] - node _T_298 = mux(_T_297, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node data1_din = and(_T_298, io.dmi_reg_wdata) @[dbg.scala 258:44] + node _T_291 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 255:39] + node _T_292 = eq(io.dmi_reg_addr, UInt<3>("h05")) @[dbg.scala 255:77] + node _T_293 = and(_T_291, _T_292) @[dbg.scala 255:58] + node _T_294 = eq(dbg_state, UInt<3>("h02")) @[dbg.scala 255:102] + node data1_reg_wren = and(_T_293, _T_294) @[dbg.scala 255:89] + node _T_295 = bits(data1_reg_wren, 0, 0) @[Bitwise.scala 72:15] + node _T_296 = mux(_T_295, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node data1_din = and(_T_296, io.dmi_reg_wdata) @[dbg.scala 256:44] inst rvclkhdr_7 of rvclkhdr_762 @[lib.scala 368:23] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= dbg_dm_rst_l rvclkhdr_7.io.clk <= clock @[lib.scala 370:18] rvclkhdr_7.io.en <= data1_reg_wren @[lib.scala 371:17] rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_299 : UInt, rvclkhdr_7.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[lib.scala 374:16] - _T_299 <= data1_din @[lib.scala 374:16] - data1_reg <= _T_299 @[dbg.scala 259:13] + reg _T_297 : UInt, rvclkhdr_7.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[lib.scala 374:16] + _T_297 <= data1_din @[lib.scala 374:16] + data1_reg <= _T_297 @[dbg.scala 257:13] wire dbg_nxtstate : UInt<3> dbg_nxtstate <= UInt<3>("h00") - dbg_nxtstate <= UInt<3>("h00") @[dbg.scala 264:16] - dbg_state_en <= UInt<1>("h00") @[dbg.scala 265:16] - abstractcs_busy_wren <= UInt<1>("h00") @[dbg.scala 266:24] - abstractcs_busy_din <= UInt<1>("h00") @[dbg.scala 267:23] - io.dbg_halt_req <= UInt<1>("h00") @[dbg.scala 268:19] - io.dbg_resume_req <= UInt<1>("h00") @[dbg.scala 269:21] - node _T_300 = eq(UInt<3>("h00"), dbg_state) @[Conditional.scala 37:30] - when _T_300 : @[Conditional.scala 40:58] - node _T_301 = bits(dmstatus_reg, 9, 9) @[dbg.scala 272:39] - node _T_302 = or(_T_301, io.dec_tlu_mpc_halted_only) @[dbg.scala 272:43] - node _T_303 = mux(_T_302, UInt<3>("h02"), UInt<3>("h01")) @[dbg.scala 272:26] - dbg_nxtstate <= _T_303 @[dbg.scala 272:20] - node _T_304 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 273:38] - node _T_305 = eq(io.dec_tlu_debug_mode, UInt<1>("h00")) @[dbg.scala 273:45] - node _T_306 = and(_T_304, _T_305) @[dbg.scala 273:43] - node _T_307 = bits(dmstatus_reg, 9, 9) @[dbg.scala 273:83] - node _T_308 = or(_T_306, _T_307) @[dbg.scala 273:69] - node _T_309 = or(_T_308, io.dec_tlu_mpc_halted_only) @[dbg.scala 273:87] - node _T_310 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 273:133] - node _T_311 = eq(_T_310, UInt<1>("h00")) @[dbg.scala 273:119] - node _T_312 = and(_T_309, _T_311) @[dbg.scala 273:117] - dbg_state_en <= _T_312 @[dbg.scala 273:20] - node _T_313 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 274:40] - node _T_314 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 274:61] - node _T_315 = eq(_T_314, UInt<1>("h00")) @[dbg.scala 274:47] - node _T_316 = and(_T_313, _T_315) @[dbg.scala 274:45] - node _T_317 = bits(_T_316, 0, 0) @[dbg.scala 274:72] - io.dbg_halt_req <= _T_317 @[dbg.scala 274:23] + dbg_nxtstate <= UInt<3>("h00") @[dbg.scala 262:16] + dbg_state_en <= UInt<1>("h00") @[dbg.scala 263:16] + abstractcs_busy_wren <= UInt<1>("h00") @[dbg.scala 264:24] + abstractcs_busy_din <= UInt<1>("h00") @[dbg.scala 265:23] + io.dbg_halt_req <= UInt<1>("h00") @[dbg.scala 266:19] + io.dbg_resume_req <= UInt<1>("h00") @[dbg.scala 267:21] + node _T_298 = eq(UInt<3>("h00"), dbg_state) @[Conditional.scala 37:30] + when _T_298 : @[Conditional.scala 40:58] + node _T_299 = bits(dmstatus_reg, 9, 9) @[dbg.scala 270:39] + node _T_300 = or(_T_299, io.dec_tlu_mpc_halted_only) @[dbg.scala 270:43] + node _T_301 = mux(_T_300, UInt<3>("h02"), UInt<3>("h01")) @[dbg.scala 270:26] + dbg_nxtstate <= _T_301 @[dbg.scala 270:20] + node _T_302 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 271:38] + node _T_303 = eq(io.dec_tlu_debug_mode, UInt<1>("h00")) @[dbg.scala 271:45] + node _T_304 = and(_T_302, _T_303) @[dbg.scala 271:43] + node _T_305 = bits(dmstatus_reg, 9, 9) @[dbg.scala 271:83] + node _T_306 = or(_T_304, _T_305) @[dbg.scala 271:69] + node _T_307 = or(_T_306, io.dec_tlu_mpc_halted_only) @[dbg.scala 271:87] + node _T_308 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 271:133] + node _T_309 = eq(_T_308, UInt<1>("h00")) @[dbg.scala 271:119] + node _T_310 = and(_T_307, _T_309) @[dbg.scala 271:117] + dbg_state_en <= _T_310 @[dbg.scala 271:20] + node _T_311 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 272:40] + node _T_312 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 272:61] + node _T_313 = eq(_T_312, UInt<1>("h00")) @[dbg.scala 272:47] + node _T_314 = and(_T_311, _T_313) @[dbg.scala 272:45] + node _T_315 = bits(_T_314, 0, 0) @[dbg.scala 272:72] + io.dbg_halt_req <= _T_315 @[dbg.scala 272:23] skip @[Conditional.scala 40:58] else : @[Conditional.scala 39:67] - node _T_318 = eq(UInt<3>("h01"), dbg_state) @[Conditional.scala 37:30] - when _T_318 : @[Conditional.scala 39:67] - node _T_319 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 277:40] - node _T_320 = mux(_T_319, UInt<3>("h00"), UInt<3>("h02")) @[dbg.scala 277:26] - dbg_nxtstate <= _T_320 @[dbg.scala 277:20] - node _T_321 = bits(dmstatus_reg, 9, 9) @[dbg.scala 278:35] - node _T_322 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 278:54] - node _T_323 = or(_T_321, _T_322) @[dbg.scala 278:39] - dbg_state_en <= _T_323 @[dbg.scala 278:20] - node _T_324 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 279:59] - node _T_325 = and(dmcontrol_wren_Q, _T_324) @[dbg.scala 279:44] - node _T_326 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 279:81] - node _T_327 = not(_T_326) @[dbg.scala 279:67] - node _T_328 = and(_T_325, _T_327) @[dbg.scala 279:64] - node _T_329 = bits(_T_328, 0, 0) @[dbg.scala 279:102] - io.dbg_halt_req <= _T_329 @[dbg.scala 279:23] + node _T_316 = eq(UInt<3>("h01"), dbg_state) @[Conditional.scala 37:30] + when _T_316 : @[Conditional.scala 39:67] + node _T_317 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 275:40] + node _T_318 = mux(_T_317, UInt<3>("h00"), UInt<3>("h02")) @[dbg.scala 275:26] + dbg_nxtstate <= _T_318 @[dbg.scala 275:20] + node _T_319 = bits(dmstatus_reg, 9, 9) @[dbg.scala 276:35] + node _T_320 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 276:54] + node _T_321 = or(_T_319, _T_320) @[dbg.scala 276:39] + dbg_state_en <= _T_321 @[dbg.scala 276:20] + node _T_322 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 277:59] + node _T_323 = and(dmcontrol_wren_Q, _T_322) @[dbg.scala 277:44] + node _T_324 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 277:81] + node _T_325 = not(_T_324) @[dbg.scala 277:67] + node _T_326 = and(_T_323, _T_325) @[dbg.scala 277:64] + node _T_327 = bits(_T_326, 0, 0) @[dbg.scala 277:102] + io.dbg_halt_req <= _T_327 @[dbg.scala 277:23] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_330 = eq(UInt<3>("h02"), dbg_state) @[Conditional.scala 37:30] - when _T_330 : @[Conditional.scala 39:67] - node _T_331 = bits(dmstatus_reg, 9, 9) @[dbg.scala 282:39] - node _T_332 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 282:59] - node _T_333 = eq(_T_332, UInt<1>("h00")) @[dbg.scala 282:45] - node _T_334 = and(_T_331, _T_333) @[dbg.scala 282:43] - node _T_335 = bits(dmcontrol_reg, 30, 30) @[dbg.scala 283:26] - node _T_336 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 283:47] - node _T_337 = eq(_T_336, UInt<1>("h00")) @[dbg.scala 283:33] - node _T_338 = and(_T_335, _T_337) @[dbg.scala 283:31] - node _T_339 = mux(_T_338, UInt<3>("h06"), UInt<3>("h03")) @[dbg.scala 283:12] - node _T_340 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 284:26] - node _T_341 = mux(_T_340, UInt<3>("h01"), UInt<3>("h00")) @[dbg.scala 284:12] - node _T_342 = mux(_T_334, _T_339, _T_341) @[dbg.scala 282:26] - dbg_nxtstate <= _T_342 @[dbg.scala 282:20] - node _T_343 = bits(dmstatus_reg, 9, 9) @[dbg.scala 285:35] - node _T_344 = bits(dmcontrol_reg, 30, 30) @[dbg.scala 285:54] - node _T_345 = and(_T_343, _T_344) @[dbg.scala 285:39] - node _T_346 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 285:75] - node _T_347 = eq(_T_346, UInt<1>("h00")) @[dbg.scala 285:61] - node _T_348 = and(_T_345, _T_347) @[dbg.scala 285:59] - node _T_349 = and(_T_348, dmcontrol_wren_Q) @[dbg.scala 285:80] - node _T_350 = or(_T_349, command_wren) @[dbg.scala 285:99] - node _T_351 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 286:22] - node _T_352 = or(_T_350, _T_351) @[dbg.scala 285:114] - node _T_353 = bits(dmstatus_reg, 9, 9) @[dbg.scala 286:42] - node _T_354 = or(_T_353, io.dec_tlu_mpc_halted_only) @[dbg.scala 286:46] - node _T_355 = eq(_T_354, UInt<1>("h00")) @[dbg.scala 286:28] - node _T_356 = or(_T_352, _T_355) @[dbg.scala 286:26] - dbg_state_en <= _T_356 @[dbg.scala 285:20] - node _T_357 = eq(dbg_nxtstate, UInt<3>("h03")) @[dbg.scala 287:60] - node _T_358 = and(dbg_state_en, _T_357) @[dbg.scala 287:44] - abstractcs_busy_wren <= _T_358 @[dbg.scala 287:28] - abstractcs_busy_din <= UInt<1>("h01") @[dbg.scala 288:27] - node _T_359 = eq(dbg_nxtstate, UInt<3>("h06")) @[dbg.scala 289:58] - node _T_360 = and(dbg_state_en, _T_359) @[dbg.scala 289:42] - node _T_361 = bits(_T_360, 0, 0) @[dbg.scala 289:87] - io.dbg_resume_req <= _T_361 @[dbg.scala 289:25] - node _T_362 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 290:59] - node _T_363 = and(dmcontrol_wren_Q, _T_362) @[dbg.scala 290:44] - node _T_364 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 290:81] - node _T_365 = not(_T_364) @[dbg.scala 290:67] - node _T_366 = and(_T_363, _T_365) @[dbg.scala 290:64] - node _T_367 = bits(_T_366, 0, 0) @[dbg.scala 290:102] - io.dbg_halt_req <= _T_367 @[dbg.scala 290:23] + node _T_328 = eq(UInt<3>("h02"), dbg_state) @[Conditional.scala 37:30] + when _T_328 : @[Conditional.scala 39:67] + node _T_329 = bits(dmstatus_reg, 9, 9) @[dbg.scala 280:39] + node _T_330 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 280:59] + node _T_331 = eq(_T_330, UInt<1>("h00")) @[dbg.scala 280:45] + node _T_332 = and(_T_329, _T_331) @[dbg.scala 280:43] + node _T_333 = bits(dmcontrol_reg, 30, 30) @[dbg.scala 281:26] + node _T_334 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 281:47] + node _T_335 = eq(_T_334, UInt<1>("h00")) @[dbg.scala 281:33] + node _T_336 = and(_T_333, _T_335) @[dbg.scala 281:31] + node _T_337 = mux(_T_336, UInt<3>("h06"), UInt<3>("h03")) @[dbg.scala 281:12] + node _T_338 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 282:26] + node _T_339 = mux(_T_338, UInt<3>("h01"), UInt<3>("h00")) @[dbg.scala 282:12] + node _T_340 = mux(_T_332, _T_337, _T_339) @[dbg.scala 280:26] + dbg_nxtstate <= _T_340 @[dbg.scala 280:20] + node _T_341 = bits(dmstatus_reg, 9, 9) @[dbg.scala 283:35] + node _T_342 = bits(dmcontrol_reg, 30, 30) @[dbg.scala 283:54] + node _T_343 = and(_T_341, _T_342) @[dbg.scala 283:39] + node _T_344 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 283:75] + node _T_345 = eq(_T_344, UInt<1>("h00")) @[dbg.scala 283:61] + node _T_346 = and(_T_343, _T_345) @[dbg.scala 283:59] + node _T_347 = and(_T_346, dmcontrol_wren_Q) @[dbg.scala 283:80] + node _T_348 = or(_T_347, command_wren) @[dbg.scala 283:99] + node _T_349 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 284:22] + node _T_350 = or(_T_348, _T_349) @[dbg.scala 283:114] + node _T_351 = bits(dmstatus_reg, 9, 9) @[dbg.scala 284:42] + node _T_352 = or(_T_351, io.dec_tlu_mpc_halted_only) @[dbg.scala 284:46] + node _T_353 = eq(_T_352, UInt<1>("h00")) @[dbg.scala 284:28] + node _T_354 = or(_T_350, _T_353) @[dbg.scala 284:26] + dbg_state_en <= _T_354 @[dbg.scala 283:20] + node _T_355 = eq(dbg_nxtstate, UInt<3>("h03")) @[dbg.scala 285:60] + node _T_356 = and(dbg_state_en, _T_355) @[dbg.scala 285:44] + abstractcs_busy_wren <= _T_356 @[dbg.scala 285:28] + abstractcs_busy_din <= UInt<1>("h01") @[dbg.scala 286:27] + node _T_357 = eq(dbg_nxtstate, UInt<3>("h06")) @[dbg.scala 287:58] + node _T_358 = and(dbg_state_en, _T_357) @[dbg.scala 287:42] + node _T_359 = bits(_T_358, 0, 0) @[dbg.scala 287:87] + io.dbg_resume_req <= _T_359 @[dbg.scala 287:25] + node _T_360 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 288:59] + node _T_361 = and(dmcontrol_wren_Q, _T_360) @[dbg.scala 288:44] + node _T_362 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 288:81] + node _T_363 = not(_T_362) @[dbg.scala 288:67] + node _T_364 = and(_T_361, _T_363) @[dbg.scala 288:64] + node _T_365 = bits(_T_364, 0, 0) @[dbg.scala 288:102] + io.dbg_halt_req <= _T_365 @[dbg.scala 288:23] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_368 = eq(UInt<3>("h03"), dbg_state) @[Conditional.scala 37:30] - when _T_368 : @[Conditional.scala 39:67] - node _T_369 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 293:40] - node _T_370 = bits(abstractcs_reg, 10, 8) @[dbg.scala 293:77] - node _T_371 = orr(_T_370) @[dbg.scala 293:85] - node _T_372 = mux(_T_371, UInt<3>("h05"), UInt<3>("h04")) @[dbg.scala 293:62] - node _T_373 = mux(_T_369, UInt<3>("h00"), _T_372) @[dbg.scala 293:26] - dbg_nxtstate <= _T_373 @[dbg.scala 293:20] - node _T_374 = bits(abstractcs_reg, 10, 8) @[dbg.scala 294:71] - node _T_375 = orr(_T_374) @[dbg.scala 294:79] - node _T_376 = or(io.dbg_dec.dbg_ib.dbg_cmd_valid, _T_375) @[dbg.scala 294:55] - node _T_377 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 294:98] - node _T_378 = or(_T_376, _T_377) @[dbg.scala 294:83] - dbg_state_en <= _T_378 @[dbg.scala 294:20] - node _T_379 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 295:59] - node _T_380 = and(dmcontrol_wren_Q, _T_379) @[dbg.scala 295:44] - node _T_381 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 295:81] - node _T_382 = not(_T_381) @[dbg.scala 295:67] - node _T_383 = and(_T_380, _T_382) @[dbg.scala 295:64] - node _T_384 = bits(_T_383, 0, 0) @[dbg.scala 295:102] - io.dbg_halt_req <= _T_384 @[dbg.scala 295:23] + node _T_366 = eq(UInt<3>("h03"), dbg_state) @[Conditional.scala 37:30] + when _T_366 : @[Conditional.scala 39:67] + node _T_367 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 291:40] + node _T_368 = bits(abstractcs_reg, 10, 8) @[dbg.scala 291:77] + node _T_369 = orr(_T_368) @[dbg.scala 291:85] + node _T_370 = mux(_T_369, UInt<3>("h05"), UInt<3>("h04")) @[dbg.scala 291:62] + node _T_371 = mux(_T_367, UInt<3>("h00"), _T_370) @[dbg.scala 291:26] + dbg_nxtstate <= _T_371 @[dbg.scala 291:20] + node _T_372 = bits(abstractcs_reg, 10, 8) @[dbg.scala 292:71] + node _T_373 = orr(_T_372) @[dbg.scala 292:79] + node _T_374 = or(io.dbg_dec.dbg_ib.dbg_cmd_valid, _T_373) @[dbg.scala 292:55] + node _T_375 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 292:98] + node _T_376 = or(_T_374, _T_375) @[dbg.scala 292:83] + dbg_state_en <= _T_376 @[dbg.scala 292:20] + node _T_377 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 293:59] + node _T_378 = and(dmcontrol_wren_Q, _T_377) @[dbg.scala 293:44] + node _T_379 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 293:81] + node _T_380 = not(_T_379) @[dbg.scala 293:67] + node _T_381 = and(_T_378, _T_380) @[dbg.scala 293:64] + node _T_382 = bits(_T_381, 0, 0) @[dbg.scala 293:102] + io.dbg_halt_req <= _T_382 @[dbg.scala 293:23] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_385 = eq(UInt<3>("h04"), dbg_state) @[Conditional.scala 37:30] - when _T_385 : @[Conditional.scala 39:67] - node _T_386 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 298:40] - node _T_387 = mux(_T_386, UInt<3>("h00"), UInt<3>("h05")) @[dbg.scala 298:26] - dbg_nxtstate <= _T_387 @[dbg.scala 298:20] - node _T_388 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 299:59] - node _T_389 = or(io.core_dbg_cmd_done, _T_388) @[dbg.scala 299:44] - dbg_state_en <= _T_389 @[dbg.scala 299:20] - node _T_390 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 300:59] - node _T_391 = and(dmcontrol_wren_Q, _T_390) @[dbg.scala 300:44] - node _T_392 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 300:81] - node _T_393 = not(_T_392) @[dbg.scala 300:67] - node _T_394 = and(_T_391, _T_393) @[dbg.scala 300:64] - node _T_395 = bits(_T_394, 0, 0) @[dbg.scala 300:102] - io.dbg_halt_req <= _T_395 @[dbg.scala 300:23] + node _T_383 = eq(UInt<3>("h04"), dbg_state) @[Conditional.scala 37:30] + when _T_383 : @[Conditional.scala 39:67] + node _T_384 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 296:40] + node _T_385 = mux(_T_384, UInt<3>("h00"), UInt<3>("h05")) @[dbg.scala 296:26] + dbg_nxtstate <= _T_385 @[dbg.scala 296:20] + node _T_386 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 297:59] + node _T_387 = or(io.core_dbg_cmd_done, _T_386) @[dbg.scala 297:44] + dbg_state_en <= _T_387 @[dbg.scala 297:20] + node _T_388 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 298:59] + node _T_389 = and(dmcontrol_wren_Q, _T_388) @[dbg.scala 298:44] + node _T_390 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 298:81] + node _T_391 = not(_T_390) @[dbg.scala 298:67] + node _T_392 = and(_T_389, _T_391) @[dbg.scala 298:64] + node _T_393 = bits(_T_392, 0, 0) @[dbg.scala 298:102] + io.dbg_halt_req <= _T_393 @[dbg.scala 298:23] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_396 = eq(UInt<3>("h05"), dbg_state) @[Conditional.scala 37:30] - when _T_396 : @[Conditional.scala 39:67] - node _T_397 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 303:40] - node _T_398 = mux(_T_397, UInt<3>("h00"), UInt<3>("h02")) @[dbg.scala 303:26] - dbg_nxtstate <= _T_398 @[dbg.scala 303:20] - dbg_state_en <= UInt<1>("h01") @[dbg.scala 304:20] - abstractcs_busy_wren <= dbg_state_en @[dbg.scala 305:28] - abstractcs_busy_din <= UInt<1>("h00") @[dbg.scala 306:27] - node _T_399 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 307:59] - node _T_400 = and(dmcontrol_wren_Q, _T_399) @[dbg.scala 307:44] - node _T_401 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 307:81] - node _T_402 = not(_T_401) @[dbg.scala 307:67] - node _T_403 = and(_T_400, _T_402) @[dbg.scala 307:64] - node _T_404 = bits(_T_403, 0, 0) @[dbg.scala 307:102] - io.dbg_halt_req <= _T_404 @[dbg.scala 307:23] + node _T_394 = eq(UInt<3>("h05"), dbg_state) @[Conditional.scala 37:30] + when _T_394 : @[Conditional.scala 39:67] + node _T_395 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 301:40] + node _T_396 = mux(_T_395, UInt<3>("h00"), UInt<3>("h02")) @[dbg.scala 301:26] + dbg_nxtstate <= _T_396 @[dbg.scala 301:20] + dbg_state_en <= UInt<1>("h01") @[dbg.scala 302:20] + abstractcs_busy_wren <= dbg_state_en @[dbg.scala 303:28] + abstractcs_busy_din <= UInt<1>("h00") @[dbg.scala 304:27] + node _T_397 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 305:59] + node _T_398 = and(dmcontrol_wren_Q, _T_397) @[dbg.scala 305:44] + node _T_399 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 305:81] + node _T_400 = not(_T_399) @[dbg.scala 305:67] + node _T_401 = and(_T_398, _T_400) @[dbg.scala 305:64] + node _T_402 = bits(_T_401, 0, 0) @[dbg.scala 305:102] + io.dbg_halt_req <= _T_402 @[dbg.scala 305:23] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_405 = eq(UInt<3>("h06"), dbg_state) @[Conditional.scala 37:30] - when _T_405 : @[Conditional.scala 39:67] - dbg_nxtstate <= UInt<3>("h00") @[dbg.scala 310:20] - node _T_406 = bits(dmstatus_reg, 17, 17) @[dbg.scala 311:35] - node _T_407 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 311:55] - node _T_408 = or(_T_406, _T_407) @[dbg.scala 311:40] - dbg_state_en <= _T_408 @[dbg.scala 311:20] - node _T_409 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 312:59] - node _T_410 = and(dmcontrol_wren_Q, _T_409) @[dbg.scala 312:44] - node _T_411 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 312:81] - node _T_412 = not(_T_411) @[dbg.scala 312:67] - node _T_413 = and(_T_410, _T_412) @[dbg.scala 312:64] - node _T_414 = bits(_T_413, 0, 0) @[dbg.scala 312:102] - io.dbg_halt_req <= _T_414 @[dbg.scala 312:23] + node _T_403 = eq(UInt<3>("h06"), dbg_state) @[Conditional.scala 37:30] + when _T_403 : @[Conditional.scala 39:67] + dbg_nxtstate <= UInt<3>("h00") @[dbg.scala 308:20] + node _T_404 = bits(dmstatus_reg, 17, 17) @[dbg.scala 309:35] + node _T_405 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 309:55] + node _T_406 = or(_T_404, _T_405) @[dbg.scala 309:40] + dbg_state_en <= _T_406 @[dbg.scala 309:20] + node _T_407 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 310:59] + node _T_408 = and(dmcontrol_wren_Q, _T_407) @[dbg.scala 310:44] + node _T_409 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 310:81] + node _T_410 = not(_T_409) @[dbg.scala 310:67] + node _T_411 = and(_T_408, _T_410) @[dbg.scala 310:64] + node _T_412 = bits(_T_411, 0, 0) @[dbg.scala 310:102] + io.dbg_halt_req <= _T_412 @[dbg.scala 310:23] skip @[Conditional.scala 39:67] - node _T_415 = eq(io.dmi_reg_addr, UInt<3>("h04")) @[dbg.scala 315:52] - node _T_416 = bits(_T_415, 0, 0) @[Bitwise.scala 72:15] - node _T_417 = mux(_T_416, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_418 = and(_T_417, data0_reg) @[dbg.scala 315:71] - node _T_419 = eq(io.dmi_reg_addr, UInt<3>("h05")) @[dbg.scala 315:110] - node _T_420 = bits(_T_419, 0, 0) @[Bitwise.scala 72:15] - node _T_421 = mux(_T_420, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_422 = and(_T_421, data1_reg) @[dbg.scala 315:122] - node _T_423 = or(_T_418, _T_422) @[dbg.scala 315:83] - node _T_424 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[dbg.scala 316:30] - node _T_425 = bits(_T_424, 0, 0) @[Bitwise.scala 72:15] - node _T_426 = mux(_T_425, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_427 = and(_T_426, dmcontrol_reg) @[dbg.scala 316:43] - node _T_428 = or(_T_423, _T_427) @[dbg.scala 315:134] - node _T_429 = eq(io.dmi_reg_addr, UInt<5>("h011")) @[dbg.scala 316:86] - node _T_430 = bits(_T_429, 0, 0) @[Bitwise.scala 72:15] - node _T_431 = mux(_T_430, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_432 = and(_T_431, dmstatus_reg) @[dbg.scala 316:99] - node _T_433 = or(_T_428, _T_432) @[dbg.scala 316:59] - node _T_434 = eq(io.dmi_reg_addr, UInt<5>("h016")) @[dbg.scala 317:30] - node _T_435 = bits(_T_434, 0, 0) @[Bitwise.scala 72:15] - node _T_436 = mux(_T_435, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_437 = and(_T_436, abstractcs_reg) @[dbg.scala 317:43] - node _T_438 = or(_T_433, _T_437) @[dbg.scala 316:114] - node _T_439 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 317:87] - node _T_440 = bits(_T_439, 0, 0) @[Bitwise.scala 72:15] - node _T_441 = mux(_T_440, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_442 = and(_T_441, command_reg) @[dbg.scala 317:100] - node _T_443 = or(_T_438, _T_442) @[dbg.scala 317:60] - node _T_444 = eq(io.dmi_reg_addr, UInt<7>("h040")) @[dbg.scala 318:30] - node _T_445 = bits(_T_444, 0, 0) @[Bitwise.scala 72:15] - node _T_446 = mux(_T_445, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_447 = and(_T_446, haltsum0_reg) @[dbg.scala 318:43] - node _T_448 = or(_T_443, _T_447) @[dbg.scala 317:114] - node _T_449 = eq(io.dmi_reg_addr, UInt<6>("h038")) @[dbg.scala 318:85] - node _T_450 = bits(_T_449, 0, 0) @[Bitwise.scala 72:15] - node _T_451 = mux(_T_450, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_452 = and(_T_451, sbcs_reg) @[dbg.scala 318:98] - node _T_453 = or(_T_448, _T_452) @[dbg.scala 318:58] - node _T_454 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[dbg.scala 319:30] - node _T_455 = bits(_T_454, 0, 0) @[Bitwise.scala 72:15] - node _T_456 = mux(_T_455, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_457 = and(_T_456, sbaddress0_reg) @[dbg.scala 319:43] - node _T_458 = or(_T_453, _T_457) @[dbg.scala 318:109] - node _T_459 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 319:87] - node _T_460 = bits(_T_459, 0, 0) @[Bitwise.scala 72:15] - node _T_461 = mux(_T_460, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_462 = and(_T_461, sbdata0_reg) @[dbg.scala 319:100] - node _T_463 = or(_T_458, _T_462) @[dbg.scala 319:60] - node _T_464 = eq(io.dmi_reg_addr, UInt<6>("h03d")) @[dbg.scala 320:30] - node _T_465 = bits(_T_464, 0, 0) @[Bitwise.scala 72:15] - node _T_466 = mux(_T_465, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_467 = and(_T_466, sbdata1_reg) @[dbg.scala 320:43] - node dmi_reg_rdata_din = or(_T_463, _T_467) @[dbg.scala 319:114] - reg _T_468 : UInt, rvclkhdr.io.l1clk with : (reset => (rst_temp, UInt<1>("h00"))) @[Reg.scala 27:20] + node _T_413 = eq(io.dmi_reg_addr, UInt<3>("h04")) @[dbg.scala 313:52] + node _T_414 = bits(_T_413, 0, 0) @[Bitwise.scala 72:15] + node _T_415 = mux(_T_414, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_416 = and(_T_415, data0_reg) @[dbg.scala 313:71] + node _T_417 = eq(io.dmi_reg_addr, UInt<3>("h05")) @[dbg.scala 313:110] + node _T_418 = bits(_T_417, 0, 0) @[Bitwise.scala 72:15] + node _T_419 = mux(_T_418, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_420 = and(_T_419, data1_reg) @[dbg.scala 313:122] + node _T_421 = or(_T_416, _T_420) @[dbg.scala 313:83] + node _T_422 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[dbg.scala 314:30] + node _T_423 = bits(_T_422, 0, 0) @[Bitwise.scala 72:15] + node _T_424 = mux(_T_423, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_425 = and(_T_424, dmcontrol_reg) @[dbg.scala 314:43] + node _T_426 = or(_T_421, _T_425) @[dbg.scala 313:134] + node _T_427 = eq(io.dmi_reg_addr, UInt<5>("h011")) @[dbg.scala 314:86] + node _T_428 = bits(_T_427, 0, 0) @[Bitwise.scala 72:15] + node _T_429 = mux(_T_428, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_430 = and(_T_429, dmstatus_reg) @[dbg.scala 314:99] + node _T_431 = or(_T_426, _T_430) @[dbg.scala 314:59] + node _T_432 = eq(io.dmi_reg_addr, UInt<5>("h016")) @[dbg.scala 315:30] + node _T_433 = bits(_T_432, 0, 0) @[Bitwise.scala 72:15] + node _T_434 = mux(_T_433, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_435 = and(_T_434, abstractcs_reg) @[dbg.scala 315:43] + node _T_436 = or(_T_431, _T_435) @[dbg.scala 314:114] + node _T_437 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 315:87] + node _T_438 = bits(_T_437, 0, 0) @[Bitwise.scala 72:15] + node _T_439 = mux(_T_438, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_440 = and(_T_439, command_reg) @[dbg.scala 315:100] + node _T_441 = or(_T_436, _T_440) @[dbg.scala 315:60] + node _T_442 = eq(io.dmi_reg_addr, UInt<7>("h040")) @[dbg.scala 316:30] + node _T_443 = bits(_T_442, 0, 0) @[Bitwise.scala 72:15] + node _T_444 = mux(_T_443, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_445 = and(_T_444, haltsum0_reg) @[dbg.scala 316:43] + node _T_446 = or(_T_441, _T_445) @[dbg.scala 315:114] + node _T_447 = eq(io.dmi_reg_addr, UInt<6>("h038")) @[dbg.scala 316:85] + node _T_448 = bits(_T_447, 0, 0) @[Bitwise.scala 72:15] + node _T_449 = mux(_T_448, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_450 = and(_T_449, sbcs_reg) @[dbg.scala 316:98] + node _T_451 = or(_T_446, _T_450) @[dbg.scala 316:58] + node _T_452 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[dbg.scala 317:30] + node _T_453 = bits(_T_452, 0, 0) @[Bitwise.scala 72:15] + node _T_454 = mux(_T_453, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_455 = and(_T_454, sbaddress0_reg) @[dbg.scala 317:43] + node _T_456 = or(_T_451, _T_455) @[dbg.scala 316:109] + node _T_457 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 317:87] + node _T_458 = bits(_T_457, 0, 0) @[Bitwise.scala 72:15] + node _T_459 = mux(_T_458, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_460 = and(_T_459, sbdata0_reg) @[dbg.scala 317:100] + node _T_461 = or(_T_456, _T_460) @[dbg.scala 317:60] + node _T_462 = eq(io.dmi_reg_addr, UInt<6>("h03d")) @[dbg.scala 318:30] + node _T_463 = bits(_T_462, 0, 0) @[Bitwise.scala 72:15] + node _T_464 = mux(_T_463, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_465 = and(_T_464, sbdata1_reg) @[dbg.scala 318:43] + node dmi_reg_rdata_din = or(_T_461, _T_465) @[dbg.scala 317:114] + reg _T_466 : UInt, rvclkhdr.io.l1clk with : (reset => (rst_temp, UInt<1>("h00"))) @[Reg.scala 27:20] when dbg_state_en : @[Reg.scala 28:19] - _T_468 <= dbg_nxtstate @[Reg.scala 28:23] + _T_466 <= dbg_nxtstate @[Reg.scala 28:23] skip @[Reg.scala 28:19] - dbg_state <= _T_468 @[dbg.scala 322:13] - reg _T_469 : UInt, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] + dbg_state <= _T_466 @[dbg.scala 320:13] + reg _T_467 : UInt, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] when io.dmi_reg_en : @[Reg.scala 28:19] - _T_469 <= dmi_reg_rdata_din @[Reg.scala 28:23] + _T_467 <= dmi_reg_rdata_din @[Reg.scala 28:23] skip @[Reg.scala 28:19] - io.dmi_reg_rdata <= _T_469 @[dbg.scala 327:20] - node _T_470 = bits(command_reg, 31, 24) @[dbg.scala 331:53] - node _T_471 = eq(_T_470, UInt<2>("h02")) @[dbg.scala 331:62] - node _T_472 = bits(data1_reg, 31, 2) @[dbg.scala 331:88] - node _T_473 = cat(_T_472, UInt<2>("h00")) @[Cat.scala 29:58] - node _T_474 = bits(command_reg, 11, 0) @[dbg.scala 331:138] - node _T_475 = cat(UInt<20>("h00"), _T_474) @[Cat.scala 29:58] - node _T_476 = mux(_T_471, _T_473, _T_475) @[dbg.scala 331:40] - io.dbg_dec.dbg_ib.dbg_cmd_addr <= _T_476 @[dbg.scala 331:34] - node _T_477 = bits(data0_reg, 31, 0) @[dbg.scala 332:50] - io.dbg_dec.dbg_dctl.dbg_cmd_wrdata <= _T_477 @[dbg.scala 332:38] - node _T_478 = eq(dbg_state, UInt<3>("h03")) @[dbg.scala 333:50] - node _T_479 = bits(abstractcs_reg, 10, 8) @[dbg.scala 333:91] - node _T_480 = orr(_T_479) @[dbg.scala 333:99] - node _T_481 = eq(_T_480, UInt<1>("h00")) @[dbg.scala 333:75] - node _T_482 = and(_T_478, _T_481) @[dbg.scala 333:73] - node _T_483 = and(_T_482, io.dbg_dma_io.dma_dbg_ready) @[dbg.scala 333:104] - node _T_484 = bits(_T_483, 0, 0) @[dbg.scala 333:141] - io.dbg_dec.dbg_ib.dbg_cmd_valid <= _T_484 @[dbg.scala 333:35] - node _T_485 = bits(command_reg, 16, 16) @[dbg.scala 334:49] - node _T_486 = bits(_T_485, 0, 0) @[dbg.scala 334:60] - io.dbg_dec.dbg_ib.dbg_cmd_write <= _T_486 @[dbg.scala 334:35] - node _T_487 = bits(command_reg, 31, 24) @[dbg.scala 335:53] - node _T_488 = eq(_T_487, UInt<2>("h02")) @[dbg.scala 335:62] - node _T_489 = bits(command_reg, 15, 12) @[dbg.scala 335:113] - node _T_490 = eq(_T_489, UInt<1>("h00")) @[dbg.scala 335:122] - node _T_491 = cat(UInt<1>("h00"), _T_490) @[Cat.scala 29:58] - node _T_492 = mux(_T_488, UInt<2>("h02"), _T_491) @[dbg.scala 335:40] - io.dbg_dec.dbg_ib.dbg_cmd_type <= _T_492 @[dbg.scala 335:34] - node _T_493 = bits(command_reg, 21, 20) @[dbg.scala 336:33] - io.dbg_cmd_size <= _T_493 @[dbg.scala 336:19] - node _T_494 = eq(dbg_state, UInt<3>("h03")) @[dbg.scala 337:47] - node _T_495 = bits(abstractcs_reg, 10, 8) @[dbg.scala 337:88] - node _T_496 = orr(_T_495) @[dbg.scala 337:96] - node _T_497 = eq(_T_496, UInt<1>("h00")) @[dbg.scala 337:72] - node _T_498 = and(_T_494, _T_497) @[dbg.scala 337:70] - node _T_499 = eq(dbg_state, UInt<3>("h04")) @[dbg.scala 337:114] - node _T_500 = or(_T_498, _T_499) @[dbg.scala 337:101] - node _T_501 = bits(_T_500, 0, 0) @[dbg.scala 337:143] - io.dbg_dma_io.dbg_dma_bubble <= _T_501 @[dbg.scala 337:32] + io.dmi_reg_rdata <= _T_467 @[dbg.scala 325:20] + node _T_468 = bits(command_reg, 31, 24) @[dbg.scala 329:53] + node _T_469 = eq(_T_468, UInt<2>("h02")) @[dbg.scala 329:62] + node _T_470 = bits(data1_reg, 31, 2) @[dbg.scala 329:88] + node _T_471 = cat(_T_470, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_472 = bits(command_reg, 11, 0) @[dbg.scala 329:138] + node _T_473 = cat(UInt<20>("h00"), _T_472) @[Cat.scala 29:58] + node _T_474 = mux(_T_469, _T_471, _T_473) @[dbg.scala 329:40] + io.dbg_dec.dbg_ib.dbg_cmd_addr <= _T_474 @[dbg.scala 329:34] + node _T_475 = bits(data0_reg, 31, 0) @[dbg.scala 330:50] + io.dbg_dec.dbg_dctl.dbg_cmd_wrdata <= _T_475 @[dbg.scala 330:38] + node _T_476 = eq(dbg_state, UInt<3>("h03")) @[dbg.scala 331:50] + node _T_477 = bits(abstractcs_reg, 10, 8) @[dbg.scala 331:91] + node _T_478 = orr(_T_477) @[dbg.scala 331:99] + node _T_479 = eq(_T_478, UInt<1>("h00")) @[dbg.scala 331:75] + node _T_480 = and(_T_476, _T_479) @[dbg.scala 331:73] + node _T_481 = and(_T_480, io.dbg_dma_io.dma_dbg_ready) @[dbg.scala 331:104] + node _T_482 = bits(_T_481, 0, 0) @[dbg.scala 331:141] + io.dbg_dec.dbg_ib.dbg_cmd_valid <= _T_482 @[dbg.scala 331:35] + node _T_483 = bits(command_reg, 16, 16) @[dbg.scala 332:49] + node _T_484 = bits(_T_483, 0, 0) @[dbg.scala 332:60] + io.dbg_dec.dbg_ib.dbg_cmd_write <= _T_484 @[dbg.scala 332:35] + node _T_485 = bits(command_reg, 31, 24) @[dbg.scala 333:53] + node _T_486 = eq(_T_485, UInt<2>("h02")) @[dbg.scala 333:62] + node _T_487 = bits(command_reg, 15, 12) @[dbg.scala 333:113] + node _T_488 = eq(_T_487, UInt<1>("h00")) @[dbg.scala 333:122] + node _T_489 = cat(UInt<1>("h00"), _T_488) @[Cat.scala 29:58] + node _T_490 = mux(_T_486, UInt<2>("h02"), _T_489) @[dbg.scala 333:40] + io.dbg_dec.dbg_ib.dbg_cmd_type <= _T_490 @[dbg.scala 333:34] + node _T_491 = bits(command_reg, 21, 20) @[dbg.scala 334:33] + io.dbg_cmd_size <= _T_491 @[dbg.scala 334:19] + node _T_492 = eq(dbg_state, UInt<3>("h03")) @[dbg.scala 335:47] + node _T_493 = bits(abstractcs_reg, 10, 8) @[dbg.scala 335:88] + node _T_494 = orr(_T_493) @[dbg.scala 335:96] + node _T_495 = eq(_T_494, UInt<1>("h00")) @[dbg.scala 335:72] + node _T_496 = and(_T_492, _T_495) @[dbg.scala 335:70] + node _T_497 = eq(dbg_state, UInt<3>("h04")) @[dbg.scala 335:114] + node _T_498 = or(_T_496, _T_497) @[dbg.scala 335:101] + node _T_499 = bits(_T_498, 0, 0) @[dbg.scala 335:143] + io.dbg_dma_io.dbg_dma_bubble <= _T_499 @[dbg.scala 335:32] wire sb_nxtstate : UInt<4> sb_nxtstate <= UInt<4>("h00") - sb_nxtstate <= UInt<4>("h00") @[dbg.scala 340:15] - sbcs_sbbusy_wren <= UInt<1>("h00") @[dbg.scala 342:20] - sbcs_sbbusy_din <= UInt<1>("h00") @[dbg.scala 343:19] - sbcs_sberror_wren <= UInt<1>("h00") @[dbg.scala 344:21] - sbcs_sberror_din <= UInt<3>("h00") @[dbg.scala 345:20] - sbaddress0_reg_wren1 <= UInt<1>("h00") @[dbg.scala 346:24] - node _T_502 = eq(UInt<4>("h00"), sb_state) @[Conditional.scala 37:30] - when _T_502 : @[Conditional.scala 40:58] - node _T_503 = mux(sbdata0wr_access, UInt<4>("h02"), UInt<4>("h01")) @[dbg.scala 349:25] - sb_nxtstate <= _T_503 @[dbg.scala 349:19] - node _T_504 = or(sbdata0wr_access, sbreadondata_access) @[dbg.scala 350:39] - node _T_505 = or(_T_504, sbreadonaddr_access) @[dbg.scala 350:61] - sb_state_en <= _T_505 @[dbg.scala 350:19] - sbcs_sbbusy_wren <= sb_state_en @[dbg.scala 351:24] - sbcs_sbbusy_din <= UInt<1>("h01") @[dbg.scala 352:23] - node _T_506 = bits(io.dmi_reg_wdata, 14, 12) @[dbg.scala 353:56] - node _T_507 = orr(_T_506) @[dbg.scala 353:65] - node _T_508 = and(sbcs_wren, _T_507) @[dbg.scala 353:38] - sbcs_sberror_wren <= _T_508 @[dbg.scala 353:25] - node _T_509 = bits(io.dmi_reg_wdata, 14, 12) @[dbg.scala 354:44] - node _T_510 = not(_T_509) @[dbg.scala 354:27] - node _T_511 = bits(sbcs_reg, 14, 12) @[dbg.scala 354:63] - node _T_512 = and(_T_510, _T_511) @[dbg.scala 354:53] - sbcs_sberror_din <= _T_512 @[dbg.scala 354:24] + sb_nxtstate <= UInt<4>("h00") @[dbg.scala 338:15] + sbcs_sbbusy_wren <= UInt<1>("h00") @[dbg.scala 340:20] + sbcs_sbbusy_din <= UInt<1>("h00") @[dbg.scala 341:19] + sbcs_sberror_wren <= UInt<1>("h00") @[dbg.scala 342:21] + sbcs_sberror_din <= UInt<3>("h00") @[dbg.scala 343:20] + sbaddress0_reg_wren1 <= UInt<1>("h00") @[dbg.scala 344:24] + node _T_500 = eq(UInt<4>("h00"), sb_state) @[Conditional.scala 37:30] + when _T_500 : @[Conditional.scala 40:58] + node _T_501 = mux(sbdata0wr_access, UInt<4>("h02"), UInt<4>("h01")) @[dbg.scala 347:25] + sb_nxtstate <= _T_501 @[dbg.scala 347:19] + node _T_502 = or(sbdata0wr_access, sbreadondata_access) @[dbg.scala 348:39] + node _T_503 = or(_T_502, sbreadonaddr_access) @[dbg.scala 348:61] + sb_state_en <= _T_503 @[dbg.scala 348:19] + sbcs_sbbusy_wren <= sb_state_en @[dbg.scala 349:24] + sbcs_sbbusy_din <= UInt<1>("h01") @[dbg.scala 350:23] + node _T_504 = bits(io.dmi_reg_wdata, 14, 12) @[dbg.scala 351:56] + node _T_505 = orr(_T_504) @[dbg.scala 351:65] + node _T_506 = and(sbcs_wren, _T_505) @[dbg.scala 351:38] + sbcs_sberror_wren <= _T_506 @[dbg.scala 351:25] + node _T_507 = bits(io.dmi_reg_wdata, 14, 12) @[dbg.scala 352:44] + node _T_508 = not(_T_507) @[dbg.scala 352:27] + node _T_509 = bits(sbcs_reg, 14, 12) @[dbg.scala 352:63] + node _T_510 = and(_T_508, _T_509) @[dbg.scala 352:53] + sbcs_sberror_din <= _T_510 @[dbg.scala 352:24] skip @[Conditional.scala 40:58] else : @[Conditional.scala 39:67] - node _T_513 = eq(UInt<4>("h01"), sb_state) @[Conditional.scala 37:30] - when _T_513 : @[Conditional.scala 39:67] - node _T_514 = or(sbcs_unaligned, sbcs_illegal_size) @[dbg.scala 357:41] - node _T_515 = mux(_T_514, UInt<4>("h09"), UInt<4>("h03")) @[dbg.scala 357:25] - sb_nxtstate <= _T_515 @[dbg.scala 357:19] - node _T_516 = or(io.dbg_bus_clk_en, sbcs_unaligned) @[dbg.scala 358:40] - node _T_517 = or(_T_516, sbcs_illegal_size) @[dbg.scala 358:57] - sb_state_en <= _T_517 @[dbg.scala 358:19] - node _T_518 = or(sbcs_unaligned, sbcs_illegal_size) @[dbg.scala 359:43] - sbcs_sberror_wren <= _T_518 @[dbg.scala 359:25] - node _T_519 = mux(sbcs_unaligned, UInt<3>("h03"), UInt<3>("h04")) @[dbg.scala 360:30] - sbcs_sberror_din <= _T_519 @[dbg.scala 360:24] + node _T_511 = eq(UInt<4>("h01"), sb_state) @[Conditional.scala 37:30] + when _T_511 : @[Conditional.scala 39:67] + node _T_512 = or(sbcs_unaligned, sbcs_illegal_size) @[dbg.scala 355:41] + node _T_513 = mux(_T_512, UInt<4>("h09"), UInt<4>("h03")) @[dbg.scala 355:25] + sb_nxtstate <= _T_513 @[dbg.scala 355:19] + node _T_514 = or(io.dbg_bus_clk_en, sbcs_unaligned) @[dbg.scala 356:40] + node _T_515 = or(_T_514, sbcs_illegal_size) @[dbg.scala 356:57] + sb_state_en <= _T_515 @[dbg.scala 356:19] + node _T_516 = or(sbcs_unaligned, sbcs_illegal_size) @[dbg.scala 357:43] + sbcs_sberror_wren <= _T_516 @[dbg.scala 357:25] + node _T_517 = mux(sbcs_unaligned, UInt<3>("h03"), UInt<3>("h04")) @[dbg.scala 358:30] + sbcs_sberror_din <= _T_517 @[dbg.scala 358:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_520 = eq(UInt<4>("h02"), sb_state) @[Conditional.scala 37:30] - when _T_520 : @[Conditional.scala 39:67] - node _T_521 = or(sbcs_unaligned, sbcs_illegal_size) @[dbg.scala 363:41] - node _T_522 = mux(_T_521, UInt<4>("h09"), UInt<4>("h04")) @[dbg.scala 363:25] - sb_nxtstate <= _T_522 @[dbg.scala 363:19] - node _T_523 = or(io.dbg_bus_clk_en, sbcs_unaligned) @[dbg.scala 364:40] - node _T_524 = or(_T_523, sbcs_illegal_size) @[dbg.scala 364:57] - sb_state_en <= _T_524 @[dbg.scala 364:19] - node _T_525 = or(sbcs_unaligned, sbcs_illegal_size) @[dbg.scala 365:43] - sbcs_sberror_wren <= _T_525 @[dbg.scala 365:25] - node _T_526 = mux(sbcs_unaligned, UInt<3>("h03"), UInt<3>("h04")) @[dbg.scala 366:30] - sbcs_sberror_din <= _T_526 @[dbg.scala 366:24] + node _T_518 = eq(UInt<4>("h02"), sb_state) @[Conditional.scala 37:30] + when _T_518 : @[Conditional.scala 39:67] + node _T_519 = or(sbcs_unaligned, sbcs_illegal_size) @[dbg.scala 361:41] + node _T_520 = mux(_T_519, UInt<4>("h09"), UInt<4>("h04")) @[dbg.scala 361:25] + sb_nxtstate <= _T_520 @[dbg.scala 361:19] + node _T_521 = or(io.dbg_bus_clk_en, sbcs_unaligned) @[dbg.scala 362:40] + node _T_522 = or(_T_521, sbcs_illegal_size) @[dbg.scala 362:57] + sb_state_en <= _T_522 @[dbg.scala 362:19] + node _T_523 = or(sbcs_unaligned, sbcs_illegal_size) @[dbg.scala 363:43] + sbcs_sberror_wren <= _T_523 @[dbg.scala 363:25] + node _T_524 = mux(sbcs_unaligned, UInt<3>("h03"), UInt<3>("h04")) @[dbg.scala 364:30] + sbcs_sberror_din <= _T_524 @[dbg.scala 364:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_527 = eq(UInt<4>("h03"), sb_state) @[Conditional.scala 37:30] - when _T_527 : @[Conditional.scala 39:67] - sb_nxtstate <= UInt<4>("h07") @[dbg.scala 369:19] - node _T_528 = and(sb_bus_cmd_read, io.dbg_bus_clk_en) @[dbg.scala 370:38] - sb_state_en <= _T_528 @[dbg.scala 370:19] + node _T_525 = eq(UInt<4>("h03"), sb_state) @[Conditional.scala 37:30] + when _T_525 : @[Conditional.scala 39:67] + sb_nxtstate <= UInt<4>("h07") @[dbg.scala 367:19] + node _T_526 = and(sb_bus_cmd_read, io.dbg_bus_clk_en) @[dbg.scala 368:38] + sb_state_en <= _T_526 @[dbg.scala 368:19] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_529 = eq(UInt<4>("h04"), sb_state) @[Conditional.scala 37:30] - when _T_529 : @[Conditional.scala 39:67] - node _T_530 = and(sb_bus_cmd_write_addr, sb_bus_cmd_write_data) @[dbg.scala 373:48] - node _T_531 = mux(sb_bus_cmd_write_data, UInt<4>("h05"), UInt<4>("h06")) @[dbg.scala 373:95] - node _T_532 = mux(_T_530, UInt<4>("h08"), _T_531) @[dbg.scala 373:25] - sb_nxtstate <= _T_532 @[dbg.scala 373:19] - node _T_533 = or(sb_bus_cmd_write_addr, sb_bus_cmd_write_data) @[dbg.scala 374:45] - node _T_534 = and(_T_533, io.dbg_bus_clk_en) @[dbg.scala 374:70] - sb_state_en <= _T_534 @[dbg.scala 374:19] + node _T_527 = eq(UInt<4>("h04"), sb_state) @[Conditional.scala 37:30] + when _T_527 : @[Conditional.scala 39:67] + node _T_528 = and(sb_bus_cmd_write_addr, sb_bus_cmd_write_data) @[dbg.scala 371:48] + node _T_529 = mux(sb_bus_cmd_write_data, UInt<4>("h05"), UInt<4>("h06")) @[dbg.scala 371:95] + node _T_530 = mux(_T_528, UInt<4>("h08"), _T_529) @[dbg.scala 371:25] + sb_nxtstate <= _T_530 @[dbg.scala 371:19] + node _T_531 = or(sb_bus_cmd_write_addr, sb_bus_cmd_write_data) @[dbg.scala 372:45] + node _T_532 = and(_T_531, io.dbg_bus_clk_en) @[dbg.scala 372:70] + sb_state_en <= _T_532 @[dbg.scala 372:19] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_535 = eq(UInt<4>("h05"), sb_state) @[Conditional.scala 37:30] - when _T_535 : @[Conditional.scala 39:67] - sb_nxtstate <= UInt<4>("h08") @[dbg.scala 377:19] - node _T_536 = and(sb_bus_cmd_write_addr, io.dbg_bus_clk_en) @[dbg.scala 378:44] - sb_state_en <= _T_536 @[dbg.scala 378:19] + node _T_533 = eq(UInt<4>("h05"), sb_state) @[Conditional.scala 37:30] + when _T_533 : @[Conditional.scala 39:67] + sb_nxtstate <= UInt<4>("h08") @[dbg.scala 375:19] + node _T_534 = and(sb_bus_cmd_write_addr, io.dbg_bus_clk_en) @[dbg.scala 376:44] + sb_state_en <= _T_534 @[dbg.scala 376:19] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_537 = eq(UInt<4>("h06"), sb_state) @[Conditional.scala 37:30] - when _T_537 : @[Conditional.scala 39:67] - sb_nxtstate <= UInt<4>("h08") @[dbg.scala 381:19] - node _T_538 = and(sb_bus_cmd_write_data, io.dbg_bus_clk_en) @[dbg.scala 382:44] - sb_state_en <= _T_538 @[dbg.scala 382:19] + node _T_535 = eq(UInt<4>("h06"), sb_state) @[Conditional.scala 37:30] + when _T_535 : @[Conditional.scala 39:67] + sb_nxtstate <= UInt<4>("h08") @[dbg.scala 379:19] + node _T_536 = and(sb_bus_cmd_write_data, io.dbg_bus_clk_en) @[dbg.scala 380:44] + sb_state_en <= _T_536 @[dbg.scala 380:19] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_539 = eq(UInt<4>("h07"), sb_state) @[Conditional.scala 37:30] - when _T_539 : @[Conditional.scala 39:67] - sb_nxtstate <= UInt<4>("h09") @[dbg.scala 385:19] - node _T_540 = and(sb_bus_rsp_read, io.dbg_bus_clk_en) @[dbg.scala 386:38] - sb_state_en <= _T_540 @[dbg.scala 386:19] - node _T_541 = and(sb_state_en, sb_bus_rsp_error) @[dbg.scala 387:40] - sbcs_sberror_wren <= _T_541 @[dbg.scala 387:25] - sbcs_sberror_din <= UInt<3>("h02") @[dbg.scala 388:24] + node _T_537 = eq(UInt<4>("h07"), sb_state) @[Conditional.scala 37:30] + when _T_537 : @[Conditional.scala 39:67] + sb_nxtstate <= UInt<4>("h09") @[dbg.scala 383:19] + node _T_538 = and(sb_bus_rsp_read, io.dbg_bus_clk_en) @[dbg.scala 384:38] + sb_state_en <= _T_538 @[dbg.scala 384:19] + node _T_539 = and(sb_state_en, sb_bus_rsp_error) @[dbg.scala 385:40] + sbcs_sberror_wren <= _T_539 @[dbg.scala 385:25] + sbcs_sberror_din <= UInt<3>("h02") @[dbg.scala 386:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_542 = eq(UInt<4>("h08"), sb_state) @[Conditional.scala 37:30] - when _T_542 : @[Conditional.scala 39:67] - sb_nxtstate <= UInt<4>("h09") @[dbg.scala 391:19] - node _T_543 = and(sb_bus_rsp_write, io.dbg_bus_clk_en) @[dbg.scala 392:39] - sb_state_en <= _T_543 @[dbg.scala 392:19] - node _T_544 = and(sb_state_en, sb_bus_rsp_error) @[dbg.scala 393:40] - sbcs_sberror_wren <= _T_544 @[dbg.scala 393:25] - sbcs_sberror_din <= UInt<3>("h02") @[dbg.scala 394:24] + node _T_540 = eq(UInt<4>("h08"), sb_state) @[Conditional.scala 37:30] + when _T_540 : @[Conditional.scala 39:67] + sb_nxtstate <= UInt<4>("h09") @[dbg.scala 389:19] + node _T_541 = and(sb_bus_rsp_write, io.dbg_bus_clk_en) @[dbg.scala 390:39] + sb_state_en <= _T_541 @[dbg.scala 390:19] + node _T_542 = and(sb_state_en, sb_bus_rsp_error) @[dbg.scala 391:40] + sbcs_sberror_wren <= _T_542 @[dbg.scala 391:25] + sbcs_sberror_din <= UInt<3>("h02") @[dbg.scala 392:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_545 = eq(UInt<4>("h09"), sb_state) @[Conditional.scala 37:30] - when _T_545 : @[Conditional.scala 39:67] - sb_nxtstate <= UInt<4>("h00") @[dbg.scala 397:19] - sb_state_en <= UInt<1>("h01") @[dbg.scala 398:19] - sbcs_sbbusy_wren <= UInt<1>("h01") @[dbg.scala 399:24] - sbcs_sbbusy_din <= UInt<1>("h00") @[dbg.scala 400:23] - node _T_546 = bits(sbcs_reg, 16, 16) @[dbg.scala 401:39] - sbaddress0_reg_wren1 <= _T_546 @[dbg.scala 401:28] + node _T_543 = eq(UInt<4>("h09"), sb_state) @[Conditional.scala 37:30] + when _T_543 : @[Conditional.scala 39:67] + sb_nxtstate <= UInt<4>("h00") @[dbg.scala 395:19] + sb_state_en <= UInt<1>("h01") @[dbg.scala 396:19] + sbcs_sbbusy_wren <= UInt<1>("h01") @[dbg.scala 397:24] + sbcs_sbbusy_din <= UInt<1>("h00") @[dbg.scala 398:23] + node _T_544 = bits(sbcs_reg, 16, 16) @[dbg.scala 399:39] + sbaddress0_reg_wren1 <= _T_544 @[dbg.scala 399:28] skip @[Conditional.scala 39:67] - reg _T_547 : UInt, rvclkhdr_1.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] + reg _T_545 : UInt, rvclkhdr_1.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] when sb_state_en : @[Reg.scala 28:19] - _T_547 <= sb_nxtstate @[Reg.scala 28:23] + _T_545 <= sb_nxtstate @[Reg.scala 28:23] skip @[Reg.scala 28:19] - sb_state <= _T_547 @[dbg.scala 404:12] - node _T_548 = and(io.sb_axi.ar.valid, io.sb_axi.ar.ready) @[dbg.scala 408:41] - sb_bus_cmd_read <= _T_548 @[dbg.scala 408:19] - node _T_549 = and(io.sb_axi.aw.valid, io.sb_axi.aw.ready) @[dbg.scala 409:47] - sb_bus_cmd_write_addr <= _T_549 @[dbg.scala 409:25] - node _T_550 = and(io.sb_axi.w.valid, io.sb_axi.w.ready) @[dbg.scala 410:46] - sb_bus_cmd_write_data <= _T_550 @[dbg.scala 410:25] - node _T_551 = and(io.sb_axi.r.valid, io.sb_axi.r.ready) @[dbg.scala 411:40] - sb_bus_rsp_read <= _T_551 @[dbg.scala 411:19] - node _T_552 = and(io.sb_axi.b.valid, io.sb_axi.b.ready) @[dbg.scala 412:41] - sb_bus_rsp_write <= _T_552 @[dbg.scala 412:20] - node _T_553 = bits(io.sb_axi.r.bits.resp, 1, 0) @[dbg.scala 413:62] - node _T_554 = orr(_T_553) @[dbg.scala 413:69] - node _T_555 = and(sb_bus_rsp_read, _T_554) @[dbg.scala 413:39] - node _T_556 = bits(io.sb_axi.b.bits.resp, 1, 0) @[dbg.scala 413:115] - node _T_557 = orr(_T_556) @[dbg.scala 413:122] - node _T_558 = and(sb_bus_rsp_write, _T_557) @[dbg.scala 413:92] - node _T_559 = or(_T_555, _T_558) @[dbg.scala 413:73] - sb_bus_rsp_error <= _T_559 @[dbg.scala 413:20] - node _T_560 = eq(sb_state, UInt<4>("h04")) @[dbg.scala 414:36] - node _T_561 = eq(sb_state, UInt<4>("h05")) @[dbg.scala 414:71] - node _T_562 = or(_T_560, _T_561) @[dbg.scala 414:59] - node _T_563 = bits(_T_562, 0, 0) @[dbg.scala 414:106] - io.sb_axi.aw.valid <= _T_563 @[dbg.scala 414:22] - io.sb_axi.aw.bits.addr <= sbaddress0_reg @[dbg.scala 415:26] - io.sb_axi.aw.bits.id <= UInt<1>("h00") @[dbg.scala 416:24] - node _T_564 = bits(sbcs_reg, 19, 17) @[dbg.scala 417:37] - io.sb_axi.aw.bits.size <= _T_564 @[dbg.scala 417:26] - io.sb_axi.aw.bits.prot <= UInt<1>("h00") @[dbg.scala 418:26] - io.sb_axi.aw.bits.cache <= UInt<4>("h0f") @[dbg.scala 419:27] - node _T_565 = bits(sbaddress0_reg, 31, 28) @[dbg.scala 420:45] - io.sb_axi.aw.bits.region <= _T_565 @[dbg.scala 420:28] - io.sb_axi.aw.bits.len <= UInt<1>("h00") @[dbg.scala 421:25] - io.sb_axi.aw.bits.burst <= UInt<2>("h01") @[dbg.scala 422:27] - io.sb_axi.aw.bits.qos <= UInt<1>("h00") @[dbg.scala 423:25] - io.sb_axi.aw.bits.lock <= UInt<1>("h00") @[dbg.scala 424:26] - node _T_566 = eq(sb_state, UInt<4>("h04")) @[dbg.scala 425:35] - node _T_567 = eq(sb_state, UInt<4>("h06")) @[dbg.scala 425:70] - node _T_568 = or(_T_566, _T_567) @[dbg.scala 425:58] - node _T_569 = bits(_T_568, 0, 0) @[dbg.scala 425:105] - io.sb_axi.w.valid <= _T_569 @[dbg.scala 425:21] - node _T_570 = bits(sbcs_reg, 19, 17) @[dbg.scala 426:46] - node _T_571 = eq(_T_570, UInt<1>("h00")) @[dbg.scala 426:55] - node _T_572 = bits(_T_571, 0, 0) @[Bitwise.scala 72:15] - node _T_573 = mux(_T_572, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] - node _T_574 = bits(sbdata0_reg, 7, 0) @[dbg.scala 426:87] + sb_state <= _T_545 @[dbg.scala 402:12] + node _T_546 = and(io.sb_axi.ar.valid, io.sb_axi.ar.ready) @[dbg.scala 406:41] + sb_bus_cmd_read <= _T_546 @[dbg.scala 406:19] + node _T_547 = and(io.sb_axi.aw.valid, io.sb_axi.aw.ready) @[dbg.scala 407:47] + sb_bus_cmd_write_addr <= _T_547 @[dbg.scala 407:25] + node _T_548 = and(io.sb_axi.w.valid, io.sb_axi.w.ready) @[dbg.scala 408:46] + sb_bus_cmd_write_data <= _T_548 @[dbg.scala 408:25] + node _T_549 = and(io.sb_axi.r.valid, io.sb_axi.r.ready) @[dbg.scala 409:40] + sb_bus_rsp_read <= _T_549 @[dbg.scala 409:19] + node _T_550 = and(io.sb_axi.b.valid, io.sb_axi.b.ready) @[dbg.scala 410:41] + sb_bus_rsp_write <= _T_550 @[dbg.scala 410:20] + node _T_551 = bits(io.sb_axi.r.bits.resp, 1, 0) @[dbg.scala 411:62] + node _T_552 = orr(_T_551) @[dbg.scala 411:69] + node _T_553 = and(sb_bus_rsp_read, _T_552) @[dbg.scala 411:39] + node _T_554 = bits(io.sb_axi.b.bits.resp, 1, 0) @[dbg.scala 411:115] + node _T_555 = orr(_T_554) @[dbg.scala 411:122] + node _T_556 = and(sb_bus_rsp_write, _T_555) @[dbg.scala 411:92] + node _T_557 = or(_T_553, _T_556) @[dbg.scala 411:73] + sb_bus_rsp_error <= _T_557 @[dbg.scala 411:20] + node _T_558 = eq(sb_state, UInt<4>("h04")) @[dbg.scala 412:36] + node _T_559 = eq(sb_state, UInt<4>("h05")) @[dbg.scala 412:71] + node _T_560 = or(_T_558, _T_559) @[dbg.scala 412:59] + node _T_561 = bits(_T_560, 0, 0) @[dbg.scala 412:106] + io.sb_axi.aw.valid <= _T_561 @[dbg.scala 412:22] + io.sb_axi.aw.bits.addr <= sbaddress0_reg @[dbg.scala 413:26] + io.sb_axi.aw.bits.id <= UInt<1>("h00") @[dbg.scala 414:24] + node _T_562 = bits(sbcs_reg, 19, 17) @[dbg.scala 415:37] + io.sb_axi.aw.bits.size <= _T_562 @[dbg.scala 415:26] + io.sb_axi.aw.bits.prot <= UInt<1>("h00") @[dbg.scala 416:26] + io.sb_axi.aw.bits.cache <= UInt<4>("h0f") @[dbg.scala 417:27] + node _T_563 = bits(sbaddress0_reg, 31, 28) @[dbg.scala 418:45] + io.sb_axi.aw.bits.region <= _T_563 @[dbg.scala 418:28] + io.sb_axi.aw.bits.len <= UInt<1>("h00") @[dbg.scala 419:25] + io.sb_axi.aw.bits.burst <= UInt<2>("h01") @[dbg.scala 420:27] + io.sb_axi.aw.bits.qos <= UInt<1>("h00") @[dbg.scala 421:25] + io.sb_axi.aw.bits.lock <= UInt<1>("h00") @[dbg.scala 422:26] + node _T_564 = eq(sb_state, UInt<4>("h04")) @[dbg.scala 423:35] + node _T_565 = eq(sb_state, UInt<4>("h06")) @[dbg.scala 423:70] + node _T_566 = or(_T_564, _T_565) @[dbg.scala 423:58] + node _T_567 = bits(_T_566, 0, 0) @[dbg.scala 423:105] + io.sb_axi.w.valid <= _T_567 @[dbg.scala 423:21] + node _T_568 = bits(sbcs_reg, 19, 17) @[dbg.scala 424:46] + node _T_569 = eq(_T_568, UInt<1>("h00")) @[dbg.scala 424:55] + node _T_570 = bits(_T_569, 0, 0) @[Bitwise.scala 72:15] + node _T_571 = mux(_T_570, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] + node _T_572 = bits(sbdata0_reg, 7, 0) @[dbg.scala 424:87] + node _T_573 = cat(_T_572, _T_572) @[Cat.scala 29:58] + node _T_574 = cat(_T_573, _T_573) @[Cat.scala 29:58] node _T_575 = cat(_T_574, _T_574) @[Cat.scala 29:58] - node _T_576 = cat(_T_575, _T_575) @[Cat.scala 29:58] - node _T_577 = cat(_T_576, _T_576) @[Cat.scala 29:58] - node _T_578 = and(_T_573, _T_577) @[dbg.scala 426:65] - node _T_579 = bits(sbcs_reg, 19, 17) @[dbg.scala 426:116] - node _T_580 = eq(_T_579, UInt<1>("h01")) @[dbg.scala 426:125] - node _T_581 = bits(_T_580, 0, 0) @[Bitwise.scala 72:15] - node _T_582 = mux(_T_581, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] - node _T_583 = bits(sbdata0_reg, 15, 0) @[dbg.scala 426:159] - node _T_584 = cat(_T_583, _T_583) @[Cat.scala 29:58] - node _T_585 = cat(_T_584, _T_584) @[Cat.scala 29:58] - node _T_586 = and(_T_582, _T_585) @[dbg.scala 426:138] - node _T_587 = or(_T_578, _T_586) @[dbg.scala 426:96] - node _T_588 = bits(sbcs_reg, 19, 17) @[dbg.scala 427:23] - node _T_589 = eq(_T_588, UInt<2>("h02")) @[dbg.scala 427:32] - node _T_590 = bits(_T_589, 0, 0) @[Bitwise.scala 72:15] - node _T_591 = mux(_T_590, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] - node _T_592 = bits(sbdata0_reg, 31, 0) @[dbg.scala 427:67] - node _T_593 = cat(_T_592, _T_592) @[Cat.scala 29:58] - node _T_594 = and(_T_591, _T_593) @[dbg.scala 427:45] - node _T_595 = or(_T_587, _T_594) @[dbg.scala 426:168] - node _T_596 = bits(sbcs_reg, 19, 17) @[dbg.scala 427:97] - node _T_597 = eq(_T_596, UInt<2>("h03")) @[dbg.scala 427:106] - node _T_598 = bits(_T_597, 0, 0) @[Bitwise.scala 72:15] - node _T_599 = mux(_T_598, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] - node _T_600 = bits(sbdata1_reg, 31, 0) @[dbg.scala 427:136] - node _T_601 = bits(sbdata0_reg, 31, 0) @[dbg.scala 427:156] - node _T_602 = cat(_T_600, _T_601) @[Cat.scala 29:58] - node _T_603 = and(_T_599, _T_602) @[dbg.scala 427:119] - node _T_604 = or(_T_595, _T_603) @[dbg.scala 427:77] - io.sb_axi.w.bits.data <= _T_604 @[dbg.scala 426:25] - node _T_605 = bits(sbcs_reg, 19, 17) @[dbg.scala 429:45] - node _T_606 = eq(_T_605, UInt<1>("h00")) @[dbg.scala 429:54] - node _T_607 = bits(_T_606, 0, 0) @[Bitwise.scala 72:15] - node _T_608 = mux(_T_607, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_609 = bits(sbaddress0_reg, 2, 0) @[dbg.scala 429:99] - node _T_610 = dshl(UInt<8>("h01"), _T_609) @[dbg.scala 429:82] - node _T_611 = and(_T_608, _T_610) @[dbg.scala 429:67] - node _T_612 = bits(sbcs_reg, 19, 17) @[dbg.scala 430:22] - node _T_613 = eq(_T_612, UInt<1>("h01")) @[dbg.scala 430:31] - node _T_614 = bits(_T_613, 0, 0) @[Bitwise.scala 72:15] - node _T_615 = mux(_T_614, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_616 = bits(sbaddress0_reg, 2, 1) @[dbg.scala 430:80] - node _T_617 = cat(_T_616, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_618 = dshl(UInt<8>("h03"), _T_617) @[dbg.scala 430:59] - node _T_619 = and(_T_615, _T_618) @[dbg.scala 430:44] - node _T_620 = or(_T_611, _T_619) @[dbg.scala 429:107] - node _T_621 = bits(sbcs_reg, 19, 17) @[dbg.scala 431:22] - node _T_622 = eq(_T_621, UInt<2>("h02")) @[dbg.scala 431:31] - node _T_623 = bits(_T_622, 0, 0) @[Bitwise.scala 72:15] - node _T_624 = mux(_T_623, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_625 = bits(sbaddress0_reg, 2, 2) @[dbg.scala 431:80] - node _T_626 = cat(_T_625, UInt<2>("h00")) @[Cat.scala 29:58] - node _T_627 = dshl(UInt<8>("h0f"), _T_626) @[dbg.scala 431:59] - node _T_628 = and(_T_624, _T_627) @[dbg.scala 431:44] - node _T_629 = or(_T_620, _T_628) @[dbg.scala 430:97] - node _T_630 = bits(sbcs_reg, 19, 17) @[dbg.scala 432:22] - node _T_631 = eq(_T_630, UInt<2>("h03")) @[dbg.scala 432:31] - node _T_632 = bits(_T_631, 0, 0) @[Bitwise.scala 72:15] - node _T_633 = mux(_T_632, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_634 = and(_T_633, UInt<8>("h0ff")) @[dbg.scala 432:44] - node _T_635 = or(_T_629, _T_634) @[dbg.scala 431:100] - io.sb_axi.w.bits.strb <= _T_635 @[dbg.scala 429:25] - io.sb_axi.w.bits.last <= UInt<1>("h01") @[dbg.scala 434:25] - node _T_636 = eq(sb_state, UInt<4>("h03")) @[dbg.scala 435:35] - node _T_637 = bits(_T_636, 0, 0) @[dbg.scala 435:64] - io.sb_axi.ar.valid <= _T_637 @[dbg.scala 435:22] - io.sb_axi.ar.bits.addr <= sbaddress0_reg @[dbg.scala 436:26] - io.sb_axi.ar.bits.id <= UInt<1>("h00") @[dbg.scala 437:24] - node _T_638 = bits(sbcs_reg, 19, 17) @[dbg.scala 438:37] - io.sb_axi.ar.bits.size <= _T_638 @[dbg.scala 438:26] - io.sb_axi.ar.bits.prot <= UInt<1>("h00") @[dbg.scala 439:26] - io.sb_axi.ar.bits.cache <= UInt<1>("h00") @[dbg.scala 440:27] - node _T_639 = bits(sbaddress0_reg, 31, 28) @[dbg.scala 441:45] - io.sb_axi.ar.bits.region <= _T_639 @[dbg.scala 441:28] - io.sb_axi.ar.bits.len <= UInt<1>("h00") @[dbg.scala 442:25] - io.sb_axi.ar.bits.burst <= UInt<2>("h01") @[dbg.scala 443:27] - io.sb_axi.ar.bits.qos <= UInt<1>("h00") @[dbg.scala 444:25] - io.sb_axi.ar.bits.lock <= UInt<1>("h00") @[dbg.scala 445:26] - io.sb_axi.b.ready <= UInt<1>("h01") @[dbg.scala 446:21] - io.sb_axi.r.ready <= UInt<1>("h01") @[dbg.scala 447:21] - node _T_640 = bits(sbcs_reg, 19, 17) @[dbg.scala 448:37] - node _T_641 = eq(_T_640, UInt<1>("h00")) @[dbg.scala 448:46] - node _T_642 = bits(_T_641, 0, 0) @[Bitwise.scala 72:15] - node _T_643 = mux(_T_642, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] - node _T_644 = bits(io.sb_axi.r.bits.data, 63, 0) @[dbg.scala 448:84] - node _T_645 = bits(sbaddress0_reg, 2, 0) @[dbg.scala 448:115] - node _T_646 = mul(UInt<4>("h08"), _T_645) @[dbg.scala 448:99] - node _T_647 = dshr(_T_644, _T_646) @[dbg.scala 448:92] - node _T_648 = and(_T_647, UInt<64>("h0ff")) @[dbg.scala 448:123] - node _T_649 = and(_T_643, _T_648) @[dbg.scala 448:59] - node _T_650 = bits(sbcs_reg, 19, 17) @[dbg.scala 449:23] - node _T_651 = eq(_T_650, UInt<1>("h01")) @[dbg.scala 449:32] - node _T_652 = bits(_T_651, 0, 0) @[Bitwise.scala 72:15] - node _T_653 = mux(_T_652, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] - node _T_654 = bits(io.sb_axi.r.bits.data, 63, 0) @[dbg.scala 449:70] - node _T_655 = bits(sbaddress0_reg, 2, 1) @[dbg.scala 449:102] - node _T_656 = mul(UInt<5>("h010"), _T_655) @[dbg.scala 449:86] - node _T_657 = dshr(_T_654, _T_656) @[dbg.scala 449:78] - node _T_658 = and(_T_657, UInt<64>("h0ffff")) @[dbg.scala 449:110] - node _T_659 = and(_T_653, _T_658) @[dbg.scala 449:45] - node _T_660 = or(_T_649, _T_659) @[dbg.scala 448:140] - node _T_661 = bits(sbcs_reg, 19, 17) @[dbg.scala 450:23] - node _T_662 = eq(_T_661, UInt<2>("h02")) @[dbg.scala 450:32] - node _T_663 = bits(_T_662, 0, 0) @[Bitwise.scala 72:15] - node _T_664 = mux(_T_663, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] - node _T_665 = bits(io.sb_axi.r.bits.data, 63, 0) @[dbg.scala 450:70] - node _T_666 = bits(sbaddress0_reg, 2, 2) @[dbg.scala 450:102] - node _T_667 = mul(UInt<6>("h020"), _T_666) @[dbg.scala 450:86] - node _T_668 = dshr(_T_665, _T_667) @[dbg.scala 450:78] - node _T_669 = and(_T_668, UInt<64>("h0ffffffff")) @[dbg.scala 450:107] - node _T_670 = and(_T_664, _T_669) @[dbg.scala 450:45] - node _T_671 = or(_T_660, _T_670) @[dbg.scala 449:129] - node _T_672 = bits(sbcs_reg, 19, 17) @[dbg.scala 451:23] - node _T_673 = eq(_T_672, UInt<2>("h03")) @[dbg.scala 451:32] - node _T_674 = bits(_T_673, 0, 0) @[Bitwise.scala 72:15] - node _T_675 = mux(_T_674, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] - node _T_676 = bits(io.sb_axi.r.bits.data, 63, 0) @[dbg.scala 451:68] - node _T_677 = and(_T_675, _T_676) @[dbg.scala 451:45] - node _T_678 = or(_T_671, _T_677) @[dbg.scala 450:131] - sb_bus_rdata <= _T_678 @[dbg.scala 448:16] - io.dbg_dma.dbg_ib.dbg_cmd_addr <= io.dbg_dec.dbg_ib.dbg_cmd_addr @[dbg.scala 454:39] - io.dbg_dma.dbg_dctl.dbg_cmd_wrdata <= io.dbg_dec.dbg_dctl.dbg_cmd_wrdata @[dbg.scala 455:39] - io.dbg_dma.dbg_ib.dbg_cmd_valid <= io.dbg_dec.dbg_ib.dbg_cmd_valid @[dbg.scala 456:39] - io.dbg_dma.dbg_ib.dbg_cmd_write <= io.dbg_dec.dbg_ib.dbg_cmd_write @[dbg.scala 457:39] - io.dbg_dma.dbg_ib.dbg_cmd_type <= io.dbg_dec.dbg_ib.dbg_cmd_type @[dbg.scala 458:39] + node _T_576 = and(_T_571, _T_575) @[dbg.scala 424:65] + node _T_577 = bits(sbcs_reg, 19, 17) @[dbg.scala 424:116] + node _T_578 = eq(_T_577, UInt<1>("h01")) @[dbg.scala 424:125] + node _T_579 = bits(_T_578, 0, 0) @[Bitwise.scala 72:15] + node _T_580 = mux(_T_579, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] + node _T_581 = bits(sbdata0_reg, 15, 0) @[dbg.scala 424:159] + node _T_582 = cat(_T_581, _T_581) @[Cat.scala 29:58] + node _T_583 = cat(_T_582, _T_582) @[Cat.scala 29:58] + node _T_584 = and(_T_580, _T_583) @[dbg.scala 424:138] + node _T_585 = or(_T_576, _T_584) @[dbg.scala 424:96] + node _T_586 = bits(sbcs_reg, 19, 17) @[dbg.scala 425:23] + node _T_587 = eq(_T_586, UInt<2>("h02")) @[dbg.scala 425:32] + node _T_588 = bits(_T_587, 0, 0) @[Bitwise.scala 72:15] + node _T_589 = mux(_T_588, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] + node _T_590 = bits(sbdata0_reg, 31, 0) @[dbg.scala 425:67] + node _T_591 = cat(_T_590, _T_590) @[Cat.scala 29:58] + node _T_592 = and(_T_589, _T_591) @[dbg.scala 425:45] + node _T_593 = or(_T_585, _T_592) @[dbg.scala 424:168] + node _T_594 = bits(sbcs_reg, 19, 17) @[dbg.scala 425:97] + node _T_595 = eq(_T_594, UInt<2>("h03")) @[dbg.scala 425:106] + node _T_596 = bits(_T_595, 0, 0) @[Bitwise.scala 72:15] + node _T_597 = mux(_T_596, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] + node _T_598 = bits(sbdata1_reg, 31, 0) @[dbg.scala 425:136] + node _T_599 = bits(sbdata0_reg, 31, 0) @[dbg.scala 425:156] + node _T_600 = cat(_T_598, _T_599) @[Cat.scala 29:58] + node _T_601 = and(_T_597, _T_600) @[dbg.scala 425:119] + node _T_602 = or(_T_593, _T_601) @[dbg.scala 425:77] + io.sb_axi.w.bits.data <= _T_602 @[dbg.scala 424:25] + node _T_603 = bits(sbcs_reg, 19, 17) @[dbg.scala 427:45] + node _T_604 = eq(_T_603, UInt<1>("h00")) @[dbg.scala 427:54] + node _T_605 = bits(_T_604, 0, 0) @[Bitwise.scala 72:15] + node _T_606 = mux(_T_605, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_607 = bits(sbaddress0_reg, 2, 0) @[dbg.scala 427:99] + node _T_608 = dshl(UInt<8>("h01"), _T_607) @[dbg.scala 427:82] + node _T_609 = and(_T_606, _T_608) @[dbg.scala 427:67] + node _T_610 = bits(sbcs_reg, 19, 17) @[dbg.scala 428:22] + node _T_611 = eq(_T_610, UInt<1>("h01")) @[dbg.scala 428:31] + node _T_612 = bits(_T_611, 0, 0) @[Bitwise.scala 72:15] + node _T_613 = mux(_T_612, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_614 = bits(sbaddress0_reg, 2, 1) @[dbg.scala 428:80] + node _T_615 = cat(_T_614, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_616 = dshl(UInt<8>("h03"), _T_615) @[dbg.scala 428:59] + node _T_617 = and(_T_613, _T_616) @[dbg.scala 428:44] + node _T_618 = or(_T_609, _T_617) @[dbg.scala 427:107] + node _T_619 = bits(sbcs_reg, 19, 17) @[dbg.scala 429:22] + node _T_620 = eq(_T_619, UInt<2>("h02")) @[dbg.scala 429:31] + node _T_621 = bits(_T_620, 0, 0) @[Bitwise.scala 72:15] + node _T_622 = mux(_T_621, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_623 = bits(sbaddress0_reg, 2, 2) @[dbg.scala 429:80] + node _T_624 = cat(_T_623, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_625 = dshl(UInt<8>("h0f"), _T_624) @[dbg.scala 429:59] + node _T_626 = and(_T_622, _T_625) @[dbg.scala 429:44] + node _T_627 = or(_T_618, _T_626) @[dbg.scala 428:97] + node _T_628 = bits(sbcs_reg, 19, 17) @[dbg.scala 430:22] + node _T_629 = eq(_T_628, UInt<2>("h03")) @[dbg.scala 430:31] + node _T_630 = bits(_T_629, 0, 0) @[Bitwise.scala 72:15] + node _T_631 = mux(_T_630, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_632 = and(_T_631, UInt<8>("h0ff")) @[dbg.scala 430:44] + node _T_633 = or(_T_627, _T_632) @[dbg.scala 429:100] + io.sb_axi.w.bits.strb <= _T_633 @[dbg.scala 427:25] + io.sb_axi.w.bits.last <= UInt<1>("h01") @[dbg.scala 432:25] + node _T_634 = eq(sb_state, UInt<4>("h03")) @[dbg.scala 433:35] + node _T_635 = bits(_T_634, 0, 0) @[dbg.scala 433:64] + io.sb_axi.ar.valid <= _T_635 @[dbg.scala 433:22] + io.sb_axi.ar.bits.addr <= sbaddress0_reg @[dbg.scala 434:26] + io.sb_axi.ar.bits.id <= UInt<1>("h00") @[dbg.scala 435:24] + node _T_636 = bits(sbcs_reg, 19, 17) @[dbg.scala 436:37] + io.sb_axi.ar.bits.size <= _T_636 @[dbg.scala 436:26] + io.sb_axi.ar.bits.prot <= UInt<1>("h00") @[dbg.scala 437:26] + io.sb_axi.ar.bits.cache <= UInt<1>("h00") @[dbg.scala 438:27] + node _T_637 = bits(sbaddress0_reg, 31, 28) @[dbg.scala 439:45] + io.sb_axi.ar.bits.region <= _T_637 @[dbg.scala 439:28] + io.sb_axi.ar.bits.len <= UInt<1>("h00") @[dbg.scala 440:25] + io.sb_axi.ar.bits.burst <= UInt<2>("h01") @[dbg.scala 441:27] + io.sb_axi.ar.bits.qos <= UInt<1>("h00") @[dbg.scala 442:25] + io.sb_axi.ar.bits.lock <= UInt<1>("h00") @[dbg.scala 443:26] + io.sb_axi.b.ready <= UInt<1>("h01") @[dbg.scala 444:21] + io.sb_axi.r.ready <= UInt<1>("h01") @[dbg.scala 445:21] + node _T_638 = bits(sbcs_reg, 19, 17) @[dbg.scala 446:37] + node _T_639 = eq(_T_638, UInt<1>("h00")) @[dbg.scala 446:46] + node _T_640 = bits(_T_639, 0, 0) @[Bitwise.scala 72:15] + node _T_641 = mux(_T_640, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] + node _T_642 = bits(io.sb_axi.r.bits.data, 63, 0) @[dbg.scala 446:84] + node _T_643 = bits(sbaddress0_reg, 2, 0) @[dbg.scala 446:115] + node _T_644 = mul(UInt<4>("h08"), _T_643) @[dbg.scala 446:99] + node _T_645 = dshr(_T_642, _T_644) @[dbg.scala 446:92] + node _T_646 = and(_T_645, UInt<64>("h0ff")) @[dbg.scala 446:123] + node _T_647 = and(_T_641, _T_646) @[dbg.scala 446:59] + node _T_648 = bits(sbcs_reg, 19, 17) @[dbg.scala 447:23] + node _T_649 = eq(_T_648, UInt<1>("h01")) @[dbg.scala 447:32] + node _T_650 = bits(_T_649, 0, 0) @[Bitwise.scala 72:15] + node _T_651 = mux(_T_650, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] + node _T_652 = bits(io.sb_axi.r.bits.data, 63, 0) @[dbg.scala 447:70] + node _T_653 = bits(sbaddress0_reg, 2, 1) @[dbg.scala 447:102] + node _T_654 = mul(UInt<5>("h010"), _T_653) @[dbg.scala 447:86] + node _T_655 = dshr(_T_652, _T_654) @[dbg.scala 447:78] + node _T_656 = and(_T_655, UInt<64>("h0ffff")) @[dbg.scala 447:110] + node _T_657 = and(_T_651, _T_656) @[dbg.scala 447:45] + node _T_658 = or(_T_647, _T_657) @[dbg.scala 446:140] + node _T_659 = bits(sbcs_reg, 19, 17) @[dbg.scala 448:23] + node _T_660 = eq(_T_659, UInt<2>("h02")) @[dbg.scala 448:32] + node _T_661 = bits(_T_660, 0, 0) @[Bitwise.scala 72:15] + node _T_662 = mux(_T_661, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] + node _T_663 = bits(io.sb_axi.r.bits.data, 63, 0) @[dbg.scala 448:70] + node _T_664 = bits(sbaddress0_reg, 2, 2) @[dbg.scala 448:102] + node _T_665 = mul(UInt<6>("h020"), _T_664) @[dbg.scala 448:86] + node _T_666 = dshr(_T_663, _T_665) @[dbg.scala 448:78] + node _T_667 = and(_T_666, UInt<64>("h0ffffffff")) @[dbg.scala 448:107] + node _T_668 = and(_T_662, _T_667) @[dbg.scala 448:45] + node _T_669 = or(_T_658, _T_668) @[dbg.scala 447:129] + node _T_670 = bits(sbcs_reg, 19, 17) @[dbg.scala 449:23] + node _T_671 = eq(_T_670, UInt<2>("h03")) @[dbg.scala 449:32] + node _T_672 = bits(_T_671, 0, 0) @[Bitwise.scala 72:15] + node _T_673 = mux(_T_672, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] + node _T_674 = bits(io.sb_axi.r.bits.data, 63, 0) @[dbg.scala 449:68] + node _T_675 = and(_T_673, _T_674) @[dbg.scala 449:45] + node _T_676 = or(_T_669, _T_675) @[dbg.scala 448:131] + sb_bus_rdata <= _T_676 @[dbg.scala 446:16] + io.dbg_dma.dbg_ib.dbg_cmd_addr <= io.dbg_dec.dbg_ib.dbg_cmd_addr @[dbg.scala 452:39] + io.dbg_dma.dbg_dctl.dbg_cmd_wrdata <= io.dbg_dec.dbg_dctl.dbg_cmd_wrdata @[dbg.scala 453:39] + io.dbg_dma.dbg_ib.dbg_cmd_valid <= io.dbg_dec.dbg_ib.dbg_cmd_valid @[dbg.scala 454:39] + io.dbg_dma.dbg_ib.dbg_cmd_write <= io.dbg_dec.dbg_ib.dbg_cmd_write @[dbg.scala 455:39] + io.dbg_dma.dbg_ib.dbg_cmd_type <= io.dbg_dec.dbg_ib.dbg_cmd_type @[dbg.scala 456:39] extmodule gated_latch_763 : output Q : Clock @@ -94944,180 +94951,180 @@ circuit quasar_wrapper : input reset : AsyncReset output io : {flip scan_mode : UInt<1>, tlu_busbuff : {lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>}, dctl_busbuff : {lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>}, flip dec_tlu_force_halt : UInt<1>, flip lsu_c2_r_clk : Clock, flip lsu_bus_ibuf_c1_clk : Clock, flip lsu_bus_obuf_c1_clk : Clock, flip lsu_bus_buf_c1_clk : Clock, flip lsu_free_c2_clk : Clock, flip lsu_busm_clk : Clock, flip dec_lsu_valid_raw_d : UInt<1>, flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_addr_m : UInt<32>, flip end_addr_m : UInt<32>, flip lsu_addr_r : UInt<32>, flip end_addr_r : UInt<32>, flip store_data_r : UInt<32>, flip no_word_merge_r : UInt<1>, flip no_dword_merge_r : UInt<1>, flip lsu_busreq_m : UInt<1>, flip ld_full_hit_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, flip lsu_commit_r : UInt<1>, flip is_sideeffects_r : UInt<1>, flip ldst_dual_d : UInt<1>, flip ldst_dual_m : UInt<1>, flip ldst_dual_r : UInt<1>, flip ldst_byteen_ext_m : UInt<8>, lsu_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip lsu_bus_clk_en : UInt<1>, flip lsu_bus_clk_en_q : UInt<1>, lsu_busreq_r : UInt<1>, lsu_bus_buffer_pend_any : UInt<1>, lsu_bus_buffer_full_any : UInt<1>, lsu_bus_buffer_empty_any : UInt<1>, lsu_bus_idle_any : UInt<1>, ld_byte_hit_buf_lo : UInt<4>, ld_byte_hit_buf_hi : UInt<4>, ld_fwddata_buf_lo : UInt<32>, ld_fwddata_buf_hi : UInt<32>} - wire buf_addr : UInt<32>[4] @[lsu_bus_buffer.scala 66:22] - wire buf_state : UInt<3>[4] @[lsu_bus_buffer.scala 67:23] + wire buf_addr : UInt<32>[4] @[lsu_bus_buffer.scala 67:22] + wire buf_state : UInt<3>[4] @[lsu_bus_buffer.scala 68:23] wire buf_write : UInt<4> buf_write <= UInt<1>("h00") wire CmdPtr0 : UInt<2> CmdPtr0 <= UInt<1>("h00") - node ldst_byteen_hi_m = bits(io.ldst_byteen_ext_m, 7, 4) @[lsu_bus_buffer.scala 72:46] - node ldst_byteen_lo_m = bits(io.ldst_byteen_ext_m, 3, 0) @[lsu_bus_buffer.scala 73:46] - node _T = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 75:66] - node _T_1 = bits(buf_addr[0], 31, 2) @[lsu_bus_buffer.scala 75:89] - node _T_2 = eq(_T, _T_1) @[lsu_bus_buffer.scala 75:74] - node _T_3 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 75:109] - node _T_4 = and(_T_2, _T_3) @[lsu_bus_buffer.scala 75:98] - node _T_5 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 75:129] - node _T_6 = and(_T_4, _T_5) @[lsu_bus_buffer.scala 75:113] - node ld_addr_hitvec_lo_0 = and(_T_6, io.lsu_busreq_m) @[lsu_bus_buffer.scala 75:141] - node _T_7 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 75:66] - node _T_8 = bits(buf_addr[1], 31, 2) @[lsu_bus_buffer.scala 75:89] - node _T_9 = eq(_T_7, _T_8) @[lsu_bus_buffer.scala 75:74] - node _T_10 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 75:109] - node _T_11 = and(_T_9, _T_10) @[lsu_bus_buffer.scala 75:98] - node _T_12 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 75:129] - node _T_13 = and(_T_11, _T_12) @[lsu_bus_buffer.scala 75:113] - node ld_addr_hitvec_lo_1 = and(_T_13, io.lsu_busreq_m) @[lsu_bus_buffer.scala 75:141] - node _T_14 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 75:66] - node _T_15 = bits(buf_addr[2], 31, 2) @[lsu_bus_buffer.scala 75:89] - node _T_16 = eq(_T_14, _T_15) @[lsu_bus_buffer.scala 75:74] - node _T_17 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 75:109] - node _T_18 = and(_T_16, _T_17) @[lsu_bus_buffer.scala 75:98] - node _T_19 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 75:129] - node _T_20 = and(_T_18, _T_19) @[lsu_bus_buffer.scala 75:113] - node ld_addr_hitvec_lo_2 = and(_T_20, io.lsu_busreq_m) @[lsu_bus_buffer.scala 75:141] - node _T_21 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 75:66] - node _T_22 = bits(buf_addr[3], 31, 2) @[lsu_bus_buffer.scala 75:89] - node _T_23 = eq(_T_21, _T_22) @[lsu_bus_buffer.scala 75:74] - node _T_24 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 75:109] - node _T_25 = and(_T_23, _T_24) @[lsu_bus_buffer.scala 75:98] - node _T_26 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 75:129] - node _T_27 = and(_T_25, _T_26) @[lsu_bus_buffer.scala 75:113] - node ld_addr_hitvec_lo_3 = and(_T_27, io.lsu_busreq_m) @[lsu_bus_buffer.scala 75:141] - node _T_28 = bits(io.end_addr_m, 31, 2) @[lsu_bus_buffer.scala 76:66] - node _T_29 = bits(buf_addr[0], 31, 2) @[lsu_bus_buffer.scala 76:89] - node _T_30 = eq(_T_28, _T_29) @[lsu_bus_buffer.scala 76:74] - node _T_31 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 76:109] - node _T_32 = and(_T_30, _T_31) @[lsu_bus_buffer.scala 76:98] - node _T_33 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 76:129] - node _T_34 = and(_T_32, _T_33) @[lsu_bus_buffer.scala 76:113] - node ld_addr_hitvec_hi_0 = and(_T_34, io.lsu_busreq_m) @[lsu_bus_buffer.scala 76:141] - node _T_35 = bits(io.end_addr_m, 31, 2) @[lsu_bus_buffer.scala 76:66] - node _T_36 = bits(buf_addr[1], 31, 2) @[lsu_bus_buffer.scala 76:89] - node _T_37 = eq(_T_35, _T_36) @[lsu_bus_buffer.scala 76:74] - node _T_38 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 76:109] - node _T_39 = and(_T_37, _T_38) @[lsu_bus_buffer.scala 76:98] - node _T_40 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 76:129] - node _T_41 = and(_T_39, _T_40) @[lsu_bus_buffer.scala 76:113] - node ld_addr_hitvec_hi_1 = and(_T_41, io.lsu_busreq_m) @[lsu_bus_buffer.scala 76:141] - node _T_42 = bits(io.end_addr_m, 31, 2) @[lsu_bus_buffer.scala 76:66] - node _T_43 = bits(buf_addr[2], 31, 2) @[lsu_bus_buffer.scala 76:89] - node _T_44 = eq(_T_42, _T_43) @[lsu_bus_buffer.scala 76:74] - node _T_45 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 76:109] - node _T_46 = and(_T_44, _T_45) @[lsu_bus_buffer.scala 76:98] - node _T_47 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 76:129] - node _T_48 = and(_T_46, _T_47) @[lsu_bus_buffer.scala 76:113] - node ld_addr_hitvec_hi_2 = and(_T_48, io.lsu_busreq_m) @[lsu_bus_buffer.scala 76:141] - node _T_49 = bits(io.end_addr_m, 31, 2) @[lsu_bus_buffer.scala 76:66] - node _T_50 = bits(buf_addr[3], 31, 2) @[lsu_bus_buffer.scala 76:89] - node _T_51 = eq(_T_49, _T_50) @[lsu_bus_buffer.scala 76:74] - node _T_52 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 76:109] - node _T_53 = and(_T_51, _T_52) @[lsu_bus_buffer.scala 76:98] - node _T_54 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 76:129] - node _T_55 = and(_T_53, _T_54) @[lsu_bus_buffer.scala 76:113] - node ld_addr_hitvec_hi_3 = and(_T_55, io.lsu_busreq_m) @[lsu_bus_buffer.scala 76:141] - wire ld_byte_hitvecfn_lo : UInt<4>[4] @[lsu_bus_buffer.scala 77:33] + node ldst_byteen_hi_m = bits(io.ldst_byteen_ext_m, 7, 4) @[lsu_bus_buffer.scala 73:46] + node ldst_byteen_lo_m = bits(io.ldst_byteen_ext_m, 3, 0) @[lsu_bus_buffer.scala 74:46] + node _T = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 76:66] + node _T_1 = bits(buf_addr[0], 31, 2) @[lsu_bus_buffer.scala 76:89] + node _T_2 = eq(_T, _T_1) @[lsu_bus_buffer.scala 76:74] + node _T_3 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 76:109] + node _T_4 = and(_T_2, _T_3) @[lsu_bus_buffer.scala 76:98] + node _T_5 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 76:129] + node _T_6 = and(_T_4, _T_5) @[lsu_bus_buffer.scala 76:113] + node ld_addr_hitvec_lo_0 = and(_T_6, io.lsu_busreq_m) @[lsu_bus_buffer.scala 76:141] + node _T_7 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 76:66] + node _T_8 = bits(buf_addr[1], 31, 2) @[lsu_bus_buffer.scala 76:89] + node _T_9 = eq(_T_7, _T_8) @[lsu_bus_buffer.scala 76:74] + node _T_10 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 76:109] + node _T_11 = and(_T_9, _T_10) @[lsu_bus_buffer.scala 76:98] + node _T_12 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 76:129] + node _T_13 = and(_T_11, _T_12) @[lsu_bus_buffer.scala 76:113] + node ld_addr_hitvec_lo_1 = and(_T_13, io.lsu_busreq_m) @[lsu_bus_buffer.scala 76:141] + node _T_14 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 76:66] + node _T_15 = bits(buf_addr[2], 31, 2) @[lsu_bus_buffer.scala 76:89] + node _T_16 = eq(_T_14, _T_15) @[lsu_bus_buffer.scala 76:74] + node _T_17 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 76:109] + node _T_18 = and(_T_16, _T_17) @[lsu_bus_buffer.scala 76:98] + node _T_19 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 76:129] + node _T_20 = and(_T_18, _T_19) @[lsu_bus_buffer.scala 76:113] + node ld_addr_hitvec_lo_2 = and(_T_20, io.lsu_busreq_m) @[lsu_bus_buffer.scala 76:141] + node _T_21 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 76:66] + node _T_22 = bits(buf_addr[3], 31, 2) @[lsu_bus_buffer.scala 76:89] + node _T_23 = eq(_T_21, _T_22) @[lsu_bus_buffer.scala 76:74] + node _T_24 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 76:109] + node _T_25 = and(_T_23, _T_24) @[lsu_bus_buffer.scala 76:98] + node _T_26 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 76:129] + node _T_27 = and(_T_25, _T_26) @[lsu_bus_buffer.scala 76:113] + node ld_addr_hitvec_lo_3 = and(_T_27, io.lsu_busreq_m) @[lsu_bus_buffer.scala 76:141] + node _T_28 = bits(io.end_addr_m, 31, 2) @[lsu_bus_buffer.scala 77:66] + node _T_29 = bits(buf_addr[0], 31, 2) @[lsu_bus_buffer.scala 77:89] + node _T_30 = eq(_T_28, _T_29) @[lsu_bus_buffer.scala 77:74] + node _T_31 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 77:109] + node _T_32 = and(_T_30, _T_31) @[lsu_bus_buffer.scala 77:98] + node _T_33 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 77:129] + node _T_34 = and(_T_32, _T_33) @[lsu_bus_buffer.scala 77:113] + node ld_addr_hitvec_hi_0 = and(_T_34, io.lsu_busreq_m) @[lsu_bus_buffer.scala 77:141] + node _T_35 = bits(io.end_addr_m, 31, 2) @[lsu_bus_buffer.scala 77:66] + node _T_36 = bits(buf_addr[1], 31, 2) @[lsu_bus_buffer.scala 77:89] + node _T_37 = eq(_T_35, _T_36) @[lsu_bus_buffer.scala 77:74] + node _T_38 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 77:109] + node _T_39 = and(_T_37, _T_38) @[lsu_bus_buffer.scala 77:98] + node _T_40 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 77:129] + node _T_41 = and(_T_39, _T_40) @[lsu_bus_buffer.scala 77:113] + node ld_addr_hitvec_hi_1 = and(_T_41, io.lsu_busreq_m) @[lsu_bus_buffer.scala 77:141] + node _T_42 = bits(io.end_addr_m, 31, 2) @[lsu_bus_buffer.scala 77:66] + node _T_43 = bits(buf_addr[2], 31, 2) @[lsu_bus_buffer.scala 77:89] + node _T_44 = eq(_T_42, _T_43) @[lsu_bus_buffer.scala 77:74] + node _T_45 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 77:109] + node _T_46 = and(_T_44, _T_45) @[lsu_bus_buffer.scala 77:98] + node _T_47 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 77:129] + node _T_48 = and(_T_46, _T_47) @[lsu_bus_buffer.scala 77:113] + node ld_addr_hitvec_hi_2 = and(_T_48, io.lsu_busreq_m) @[lsu_bus_buffer.scala 77:141] + node _T_49 = bits(io.end_addr_m, 31, 2) @[lsu_bus_buffer.scala 77:66] + node _T_50 = bits(buf_addr[3], 31, 2) @[lsu_bus_buffer.scala 77:89] + node _T_51 = eq(_T_49, _T_50) @[lsu_bus_buffer.scala 77:74] + node _T_52 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 77:109] + node _T_53 = and(_T_51, _T_52) @[lsu_bus_buffer.scala 77:98] + node _T_54 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 77:129] + node _T_55 = and(_T_53, _T_54) @[lsu_bus_buffer.scala 77:113] + node ld_addr_hitvec_hi_3 = and(_T_55, io.lsu_busreq_m) @[lsu_bus_buffer.scala 77:141] + wire ld_byte_hitvecfn_lo : UInt<4>[4] @[lsu_bus_buffer.scala 78:33] wire ld_byte_ibuf_hit_lo : UInt<4> ld_byte_ibuf_hit_lo <= UInt<1>("h00") - wire ld_byte_hitvecfn_hi : UInt<4>[4] @[lsu_bus_buffer.scala 79:33] + wire ld_byte_hitvecfn_hi : UInt<4>[4] @[lsu_bus_buffer.scala 80:33] wire ld_byte_ibuf_hit_hi : UInt<4> ld_byte_ibuf_hit_hi <= UInt<1>("h00") - wire buf_byteen : UInt<4>[4] @[lsu_bus_buffer.scala 81:24] - buf_byteen[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 82:14] - buf_byteen[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 82:14] - buf_byteen[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 82:14] - buf_byteen[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 82:14] - wire buf_nxtstate : UInt<3>[4] @[lsu_bus_buffer.scala 83:26] - buf_nxtstate[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 84:16] - buf_nxtstate[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 84:16] - buf_nxtstate[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 84:16] - buf_nxtstate[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 84:16] - wire buf_wr_en : UInt<1>[4] @[lsu_bus_buffer.scala 85:23] - buf_wr_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 86:13] - buf_wr_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 86:13] - buf_wr_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 86:13] - buf_wr_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 86:13] - wire buf_data_en : UInt<1>[4] @[lsu_bus_buffer.scala 87:25] - buf_data_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 88:15] - buf_data_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 88:15] - buf_data_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 88:15] - buf_data_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 88:15] - wire buf_state_bus_en : UInt<1>[4] @[lsu_bus_buffer.scala 89:30] - buf_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 90:20] - buf_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 90:20] - buf_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 90:20] - buf_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 90:20] - wire buf_ldfwd_in : UInt<1>[4] @[lsu_bus_buffer.scala 91:26] - buf_ldfwd_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 92:16] - buf_ldfwd_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 92:16] - buf_ldfwd_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 92:16] - buf_ldfwd_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 92:16] - wire buf_ldfwd_en : UInt<1>[4] @[lsu_bus_buffer.scala 93:26] - buf_ldfwd_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 94:16] - buf_ldfwd_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 94:16] - buf_ldfwd_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 94:16] - buf_ldfwd_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 94:16] - wire buf_data_in : UInt<32>[4] @[lsu_bus_buffer.scala 95:25] - buf_data_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 96:15] - buf_data_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 96:15] - buf_data_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 96:15] - buf_data_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 96:15] - wire buf_ldfwdtag_in : UInt<2>[4] @[lsu_bus_buffer.scala 97:29] - buf_ldfwdtag_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 98:19] - buf_ldfwdtag_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 98:19] - buf_ldfwdtag_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 98:19] - buf_ldfwdtag_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 98:19] - wire buf_error_en : UInt<1>[4] @[lsu_bus_buffer.scala 99:26] - buf_error_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 100:16] - buf_error_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 100:16] - buf_error_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 100:16] - buf_error_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 100:16] + wire buf_byteen : UInt<4>[4] @[lsu_bus_buffer.scala 82:24] + buf_byteen[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 83:14] + buf_byteen[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 83:14] + buf_byteen[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 83:14] + buf_byteen[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 83:14] + wire buf_nxtstate : UInt<3>[4] @[lsu_bus_buffer.scala 84:26] + buf_nxtstate[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 85:16] + buf_nxtstate[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 85:16] + buf_nxtstate[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 85:16] + buf_nxtstate[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 85:16] + wire buf_wr_en : UInt<1>[4] @[lsu_bus_buffer.scala 86:23] + buf_wr_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 87:13] + buf_wr_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 87:13] + buf_wr_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 87:13] + buf_wr_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 87:13] + wire buf_data_en : UInt<1>[4] @[lsu_bus_buffer.scala 88:25] + buf_data_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 89:15] + buf_data_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 89:15] + buf_data_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 89:15] + buf_data_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 89:15] + wire buf_state_bus_en : UInt<1>[4] @[lsu_bus_buffer.scala 90:30] + buf_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 91:20] + buf_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 91:20] + buf_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 91:20] + buf_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 91:20] + wire buf_ldfwd_in : UInt<1>[4] @[lsu_bus_buffer.scala 92:26] + buf_ldfwd_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 93:16] + buf_ldfwd_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 93:16] + buf_ldfwd_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 93:16] + buf_ldfwd_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 93:16] + wire buf_ldfwd_en : UInt<1>[4] @[lsu_bus_buffer.scala 94:26] + buf_ldfwd_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 95:16] + buf_ldfwd_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 95:16] + buf_ldfwd_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 95:16] + buf_ldfwd_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 95:16] + wire buf_data_in : UInt<32>[4] @[lsu_bus_buffer.scala 96:25] + buf_data_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 97:15] + buf_data_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 97:15] + buf_data_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 97:15] + buf_data_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 97:15] + wire buf_ldfwdtag_in : UInt<2>[4] @[lsu_bus_buffer.scala 98:29] + buf_ldfwdtag_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 99:19] + buf_ldfwdtag_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 99:19] + buf_ldfwdtag_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 99:19] + buf_ldfwdtag_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 99:19] + wire buf_error_en : UInt<1>[4] @[lsu_bus_buffer.scala 100:26] + buf_error_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 101:16] + buf_error_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 101:16] + buf_error_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 101:16] + buf_error_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 101:16] wire bus_rsp_read_error : UInt<1> bus_rsp_read_error <= UInt<1>("h00") wire bus_rsp_rdata : UInt<64> bus_rsp_rdata <= UInt<1>("h00") wire bus_rsp_write_error : UInt<1> bus_rsp_write_error <= UInt<1>("h00") - wire buf_dualtag : UInt<2>[4] @[lsu_bus_buffer.scala 104:25] - buf_dualtag[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 105:15] - buf_dualtag[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 105:15] - buf_dualtag[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 105:15] - buf_dualtag[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 105:15] + wire buf_dualtag : UInt<2>[4] @[lsu_bus_buffer.scala 105:25] + buf_dualtag[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 106:15] + buf_dualtag[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 106:15] + buf_dualtag[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 106:15] + buf_dualtag[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 106:15] wire buf_ldfwd : UInt<4> buf_ldfwd <= UInt<1>("h00") - wire buf_resp_state_bus_en : UInt<1>[4] @[lsu_bus_buffer.scala 107:35] - buf_resp_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 108:25] - buf_resp_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 108:25] - buf_resp_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 108:25] - buf_resp_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 108:25] + wire buf_resp_state_bus_en : UInt<1>[4] @[lsu_bus_buffer.scala 108:35] + buf_resp_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 109:25] + buf_resp_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 109:25] + buf_resp_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 109:25] + buf_resp_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 109:25] wire any_done_wait_state : UInt<1> any_done_wait_state <= UInt<1>("h00") wire bus_rsp_write : UInt<1> bus_rsp_write <= UInt<1>("h00") wire bus_rsp_write_tag : UInt<3> bus_rsp_write_tag <= UInt<1>("h00") - wire buf_ldfwdtag : UInt<2>[4] @[lsu_bus_buffer.scala 112:26] - buf_ldfwdtag[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 113:16] - buf_ldfwdtag[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 113:16] - buf_ldfwdtag[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 113:16] - buf_ldfwdtag[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 113:16] - wire buf_rst : UInt<1>[4] @[lsu_bus_buffer.scala 114:21] - buf_rst[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 115:11] - buf_rst[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 115:11] - buf_rst[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 115:11] - buf_rst[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 115:11] + wire buf_ldfwdtag : UInt<2>[4] @[lsu_bus_buffer.scala 113:26] + buf_ldfwdtag[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 114:16] + buf_ldfwdtag[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 114:16] + buf_ldfwdtag[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 114:16] + buf_ldfwdtag[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 114:16] + wire buf_rst : UInt<1>[4] @[lsu_bus_buffer.scala 115:21] + buf_rst[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 116:11] + buf_rst[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 116:11] + buf_rst[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 116:11] + buf_rst[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 116:11] wire ibuf_drainvec_vld : UInt<4> ibuf_drainvec_vld <= UInt<1>("h00") - wire buf_byteen_in : UInt<4>[4] @[lsu_bus_buffer.scala 117:27] - buf_byteen_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 118:17] - buf_byteen_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 118:17] - buf_byteen_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 118:17] - buf_byteen_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 118:17] - wire buf_addr_in : UInt<32>[4] @[lsu_bus_buffer.scala 119:25] - buf_addr_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 120:15] - buf_addr_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 120:15] - buf_addr_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 120:15] - buf_addr_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 120:15] + wire buf_byteen_in : UInt<4>[4] @[lsu_bus_buffer.scala 118:27] + buf_byteen_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 119:17] + buf_byteen_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 119:17] + buf_byteen_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 119:17] + buf_byteen_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 119:17] + wire buf_addr_in : UInt<32>[4] @[lsu_bus_buffer.scala 120:25] + buf_addr_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 121:15] + buf_addr_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 121:15] + buf_addr_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 121:15] + buf_addr_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 121:15] wire buf_dual_in : UInt<4> buf_dual_in <= UInt<1>("h00") wire buf_samedw_in : UInt<4> @@ -95126,20 +95133,20 @@ circuit quasar_wrapper : buf_nomerge_in <= UInt<1>("h00") wire buf_dualhi_in : UInt<4> buf_dualhi_in <= UInt<1>("h00") - wire buf_dualtag_in : UInt<2>[4] @[lsu_bus_buffer.scala 125:28] - buf_dualtag_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 126:18] - buf_dualtag_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 126:18] - buf_dualtag_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 126:18] - buf_dualtag_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 126:18] + wire buf_dualtag_in : UInt<2>[4] @[lsu_bus_buffer.scala 126:28] + buf_dualtag_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 127:18] + buf_dualtag_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 127:18] + buf_dualtag_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 127:18] + buf_dualtag_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 127:18] wire buf_sideeffect_in : UInt<4> buf_sideeffect_in <= UInt<1>("h00") wire buf_unsign_in : UInt<4> buf_unsign_in <= UInt<1>("h00") - wire buf_sz_in : UInt<2>[4] @[lsu_bus_buffer.scala 129:23] - buf_sz_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 130:13] - buf_sz_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 130:13] - buf_sz_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 130:13] - buf_sz_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 130:13] + wire buf_sz_in : UInt<2>[4] @[lsu_bus_buffer.scala 130:23] + buf_sz_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 131:13] + buf_sz_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 131:13] + buf_sz_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 131:13] + buf_sz_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 131:13] wire buf_write_in : UInt<4> buf_write_in <= UInt<1>("h00") wire buf_unsign : UInt<4> @@ -95150,747 +95157,747 @@ circuit quasar_wrapper : CmdPtr1 <= UInt<1>("h00") wire ibuf_data : UInt<32> ibuf_data <= UInt<1>("h00") - node _T_56 = orr(ld_byte_hitvecfn_lo[0]) @[lsu_bus_buffer.scala 137:73] - node _T_57 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[lsu_bus_buffer.scala 137:98] - node _T_58 = or(_T_56, _T_57) @[lsu_bus_buffer.scala 137:77] - node _T_59 = orr(ld_byte_hitvecfn_lo[1]) @[lsu_bus_buffer.scala 137:73] - node _T_60 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[lsu_bus_buffer.scala 137:98] - node _T_61 = or(_T_59, _T_60) @[lsu_bus_buffer.scala 137:77] - node _T_62 = orr(ld_byte_hitvecfn_lo[2]) @[lsu_bus_buffer.scala 137:73] - node _T_63 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[lsu_bus_buffer.scala 137:98] - node _T_64 = or(_T_62, _T_63) @[lsu_bus_buffer.scala 137:77] - node _T_65 = orr(ld_byte_hitvecfn_lo[3]) @[lsu_bus_buffer.scala 137:73] - node _T_66 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[lsu_bus_buffer.scala 137:98] - node _T_67 = or(_T_65, _T_66) @[lsu_bus_buffer.scala 137:77] + node _T_56 = orr(ld_byte_hitvecfn_lo[0]) @[lsu_bus_buffer.scala 138:73] + node _T_57 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[lsu_bus_buffer.scala 138:98] + node _T_58 = or(_T_56, _T_57) @[lsu_bus_buffer.scala 138:77] + node _T_59 = orr(ld_byte_hitvecfn_lo[1]) @[lsu_bus_buffer.scala 138:73] + node _T_60 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[lsu_bus_buffer.scala 138:98] + node _T_61 = or(_T_59, _T_60) @[lsu_bus_buffer.scala 138:77] + node _T_62 = orr(ld_byte_hitvecfn_lo[2]) @[lsu_bus_buffer.scala 138:73] + node _T_63 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[lsu_bus_buffer.scala 138:98] + node _T_64 = or(_T_62, _T_63) @[lsu_bus_buffer.scala 138:77] + node _T_65 = orr(ld_byte_hitvecfn_lo[3]) @[lsu_bus_buffer.scala 138:73] + node _T_66 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[lsu_bus_buffer.scala 138:98] + node _T_67 = or(_T_65, _T_66) @[lsu_bus_buffer.scala 138:77] node _T_68 = cat(_T_67, _T_64) @[Cat.scala 29:58] node _T_69 = cat(_T_68, _T_61) @[Cat.scala 29:58] node _T_70 = cat(_T_69, _T_58) @[Cat.scala 29:58] - io.ld_byte_hit_buf_lo <= _T_70 @[lsu_bus_buffer.scala 137:25] - node _T_71 = orr(ld_byte_hitvecfn_hi[0]) @[lsu_bus_buffer.scala 138:73] - node _T_72 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[lsu_bus_buffer.scala 138:98] - node _T_73 = or(_T_71, _T_72) @[lsu_bus_buffer.scala 138:77] - node _T_74 = orr(ld_byte_hitvecfn_hi[1]) @[lsu_bus_buffer.scala 138:73] - node _T_75 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[lsu_bus_buffer.scala 138:98] - node _T_76 = or(_T_74, _T_75) @[lsu_bus_buffer.scala 138:77] - node _T_77 = orr(ld_byte_hitvecfn_hi[2]) @[lsu_bus_buffer.scala 138:73] - node _T_78 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[lsu_bus_buffer.scala 138:98] - node _T_79 = or(_T_77, _T_78) @[lsu_bus_buffer.scala 138:77] - node _T_80 = orr(ld_byte_hitvecfn_hi[3]) @[lsu_bus_buffer.scala 138:73] - node _T_81 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[lsu_bus_buffer.scala 138:98] - node _T_82 = or(_T_80, _T_81) @[lsu_bus_buffer.scala 138:77] + io.ld_byte_hit_buf_lo <= _T_70 @[lsu_bus_buffer.scala 138:25] + node _T_71 = orr(ld_byte_hitvecfn_hi[0]) @[lsu_bus_buffer.scala 139:73] + node _T_72 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[lsu_bus_buffer.scala 139:98] + node _T_73 = or(_T_71, _T_72) @[lsu_bus_buffer.scala 139:77] + node _T_74 = orr(ld_byte_hitvecfn_hi[1]) @[lsu_bus_buffer.scala 139:73] + node _T_75 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[lsu_bus_buffer.scala 139:98] + node _T_76 = or(_T_74, _T_75) @[lsu_bus_buffer.scala 139:77] + node _T_77 = orr(ld_byte_hitvecfn_hi[2]) @[lsu_bus_buffer.scala 139:73] + node _T_78 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[lsu_bus_buffer.scala 139:98] + node _T_79 = or(_T_77, _T_78) @[lsu_bus_buffer.scala 139:77] + node _T_80 = orr(ld_byte_hitvecfn_hi[3]) @[lsu_bus_buffer.scala 139:73] + node _T_81 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[lsu_bus_buffer.scala 139:98] + node _T_82 = or(_T_80, _T_81) @[lsu_bus_buffer.scala 139:77] node _T_83 = cat(_T_82, _T_79) @[Cat.scala 29:58] node _T_84 = cat(_T_83, _T_76) @[Cat.scala 29:58] node _T_85 = cat(_T_84, _T_73) @[Cat.scala 29:58] - io.ld_byte_hit_buf_hi <= _T_85 @[lsu_bus_buffer.scala 138:25] - node _T_86 = bits(buf_byteen[0], 0, 0) @[lsu_bus_buffer.scala 140:110] - node _T_87 = and(ld_addr_hitvec_lo_0, _T_86) @[lsu_bus_buffer.scala 140:95] - node _T_88 = bits(ldst_byteen_lo_m, 0, 0) @[lsu_bus_buffer.scala 140:132] - node _T_89 = and(_T_87, _T_88) @[lsu_bus_buffer.scala 140:114] - node _T_90 = bits(buf_byteen[1], 0, 0) @[lsu_bus_buffer.scala 140:110] - node _T_91 = and(ld_addr_hitvec_lo_1, _T_90) @[lsu_bus_buffer.scala 140:95] - node _T_92 = bits(ldst_byteen_lo_m, 0, 0) @[lsu_bus_buffer.scala 140:132] - node _T_93 = and(_T_91, _T_92) @[lsu_bus_buffer.scala 140:114] - node _T_94 = bits(buf_byteen[2], 0, 0) @[lsu_bus_buffer.scala 140:110] - node _T_95 = and(ld_addr_hitvec_lo_2, _T_94) @[lsu_bus_buffer.scala 140:95] - node _T_96 = bits(ldst_byteen_lo_m, 0, 0) @[lsu_bus_buffer.scala 140:132] - node _T_97 = and(_T_95, _T_96) @[lsu_bus_buffer.scala 140:114] - node _T_98 = bits(buf_byteen[3], 0, 0) @[lsu_bus_buffer.scala 140:110] - node _T_99 = and(ld_addr_hitvec_lo_3, _T_98) @[lsu_bus_buffer.scala 140:95] - node _T_100 = bits(ldst_byteen_lo_m, 0, 0) @[lsu_bus_buffer.scala 140:132] - node _T_101 = and(_T_99, _T_100) @[lsu_bus_buffer.scala 140:114] + io.ld_byte_hit_buf_hi <= _T_85 @[lsu_bus_buffer.scala 139:25] + node _T_86 = bits(buf_byteen[0], 0, 0) @[lsu_bus_buffer.scala 141:110] + node _T_87 = and(ld_addr_hitvec_lo_0, _T_86) @[lsu_bus_buffer.scala 141:95] + node _T_88 = bits(ldst_byteen_lo_m, 0, 0) @[lsu_bus_buffer.scala 141:132] + node _T_89 = and(_T_87, _T_88) @[lsu_bus_buffer.scala 141:114] + node _T_90 = bits(buf_byteen[1], 0, 0) @[lsu_bus_buffer.scala 141:110] + node _T_91 = and(ld_addr_hitvec_lo_1, _T_90) @[lsu_bus_buffer.scala 141:95] + node _T_92 = bits(ldst_byteen_lo_m, 0, 0) @[lsu_bus_buffer.scala 141:132] + node _T_93 = and(_T_91, _T_92) @[lsu_bus_buffer.scala 141:114] + node _T_94 = bits(buf_byteen[2], 0, 0) @[lsu_bus_buffer.scala 141:110] + node _T_95 = and(ld_addr_hitvec_lo_2, _T_94) @[lsu_bus_buffer.scala 141:95] + node _T_96 = bits(ldst_byteen_lo_m, 0, 0) @[lsu_bus_buffer.scala 141:132] + node _T_97 = and(_T_95, _T_96) @[lsu_bus_buffer.scala 141:114] + node _T_98 = bits(buf_byteen[3], 0, 0) @[lsu_bus_buffer.scala 141:110] + node _T_99 = and(ld_addr_hitvec_lo_3, _T_98) @[lsu_bus_buffer.scala 141:95] + node _T_100 = bits(ldst_byteen_lo_m, 0, 0) @[lsu_bus_buffer.scala 141:132] + node _T_101 = and(_T_99, _T_100) @[lsu_bus_buffer.scala 141:114] node _T_102 = cat(_T_101, _T_97) @[Cat.scala 29:58] node _T_103 = cat(_T_102, _T_93) @[Cat.scala 29:58] node ld_byte_hitvec_lo_0 = cat(_T_103, _T_89) @[Cat.scala 29:58] - node _T_104 = bits(buf_byteen[0], 1, 1) @[lsu_bus_buffer.scala 140:110] - node _T_105 = and(ld_addr_hitvec_lo_0, _T_104) @[lsu_bus_buffer.scala 140:95] - node _T_106 = bits(ldst_byteen_lo_m, 1, 1) @[lsu_bus_buffer.scala 140:132] - node _T_107 = and(_T_105, _T_106) @[lsu_bus_buffer.scala 140:114] - node _T_108 = bits(buf_byteen[1], 1, 1) @[lsu_bus_buffer.scala 140:110] - node _T_109 = and(ld_addr_hitvec_lo_1, _T_108) @[lsu_bus_buffer.scala 140:95] - node _T_110 = bits(ldst_byteen_lo_m, 1, 1) @[lsu_bus_buffer.scala 140:132] - node _T_111 = and(_T_109, _T_110) @[lsu_bus_buffer.scala 140:114] - node _T_112 = bits(buf_byteen[2], 1, 1) @[lsu_bus_buffer.scala 140:110] - node _T_113 = and(ld_addr_hitvec_lo_2, _T_112) @[lsu_bus_buffer.scala 140:95] - node _T_114 = bits(ldst_byteen_lo_m, 1, 1) @[lsu_bus_buffer.scala 140:132] - node _T_115 = and(_T_113, _T_114) @[lsu_bus_buffer.scala 140:114] - node _T_116 = bits(buf_byteen[3], 1, 1) @[lsu_bus_buffer.scala 140:110] - node _T_117 = and(ld_addr_hitvec_lo_3, _T_116) @[lsu_bus_buffer.scala 140:95] - node _T_118 = bits(ldst_byteen_lo_m, 1, 1) @[lsu_bus_buffer.scala 140:132] - node _T_119 = and(_T_117, _T_118) @[lsu_bus_buffer.scala 140:114] + node _T_104 = bits(buf_byteen[0], 1, 1) @[lsu_bus_buffer.scala 141:110] + node _T_105 = and(ld_addr_hitvec_lo_0, _T_104) @[lsu_bus_buffer.scala 141:95] + node _T_106 = bits(ldst_byteen_lo_m, 1, 1) @[lsu_bus_buffer.scala 141:132] + node _T_107 = and(_T_105, _T_106) @[lsu_bus_buffer.scala 141:114] + node _T_108 = bits(buf_byteen[1], 1, 1) @[lsu_bus_buffer.scala 141:110] + node _T_109 = and(ld_addr_hitvec_lo_1, _T_108) @[lsu_bus_buffer.scala 141:95] + node _T_110 = bits(ldst_byteen_lo_m, 1, 1) @[lsu_bus_buffer.scala 141:132] + node _T_111 = and(_T_109, _T_110) @[lsu_bus_buffer.scala 141:114] + node _T_112 = bits(buf_byteen[2], 1, 1) @[lsu_bus_buffer.scala 141:110] + node _T_113 = and(ld_addr_hitvec_lo_2, _T_112) @[lsu_bus_buffer.scala 141:95] + node _T_114 = bits(ldst_byteen_lo_m, 1, 1) @[lsu_bus_buffer.scala 141:132] + node _T_115 = and(_T_113, _T_114) @[lsu_bus_buffer.scala 141:114] + node _T_116 = bits(buf_byteen[3], 1, 1) @[lsu_bus_buffer.scala 141:110] + node _T_117 = and(ld_addr_hitvec_lo_3, _T_116) @[lsu_bus_buffer.scala 141:95] + node _T_118 = bits(ldst_byteen_lo_m, 1, 1) @[lsu_bus_buffer.scala 141:132] + node _T_119 = and(_T_117, _T_118) @[lsu_bus_buffer.scala 141:114] node _T_120 = cat(_T_119, _T_115) @[Cat.scala 29:58] node _T_121 = cat(_T_120, _T_111) @[Cat.scala 29:58] node ld_byte_hitvec_lo_1 = cat(_T_121, _T_107) @[Cat.scala 29:58] - node _T_122 = bits(buf_byteen[0], 2, 2) @[lsu_bus_buffer.scala 140:110] - node _T_123 = and(ld_addr_hitvec_lo_0, _T_122) @[lsu_bus_buffer.scala 140:95] - node _T_124 = bits(ldst_byteen_lo_m, 2, 2) @[lsu_bus_buffer.scala 140:132] - node _T_125 = and(_T_123, _T_124) @[lsu_bus_buffer.scala 140:114] - node _T_126 = bits(buf_byteen[1], 2, 2) @[lsu_bus_buffer.scala 140:110] - node _T_127 = and(ld_addr_hitvec_lo_1, _T_126) @[lsu_bus_buffer.scala 140:95] - node _T_128 = bits(ldst_byteen_lo_m, 2, 2) @[lsu_bus_buffer.scala 140:132] - node _T_129 = and(_T_127, _T_128) @[lsu_bus_buffer.scala 140:114] - node _T_130 = bits(buf_byteen[2], 2, 2) @[lsu_bus_buffer.scala 140:110] - node _T_131 = and(ld_addr_hitvec_lo_2, _T_130) @[lsu_bus_buffer.scala 140:95] - node _T_132 = bits(ldst_byteen_lo_m, 2, 2) @[lsu_bus_buffer.scala 140:132] - node _T_133 = and(_T_131, _T_132) @[lsu_bus_buffer.scala 140:114] - node _T_134 = bits(buf_byteen[3], 2, 2) @[lsu_bus_buffer.scala 140:110] - node _T_135 = and(ld_addr_hitvec_lo_3, _T_134) @[lsu_bus_buffer.scala 140:95] - node _T_136 = bits(ldst_byteen_lo_m, 2, 2) @[lsu_bus_buffer.scala 140:132] - node _T_137 = and(_T_135, _T_136) @[lsu_bus_buffer.scala 140:114] + node _T_122 = bits(buf_byteen[0], 2, 2) @[lsu_bus_buffer.scala 141:110] + node _T_123 = and(ld_addr_hitvec_lo_0, _T_122) @[lsu_bus_buffer.scala 141:95] + node _T_124 = bits(ldst_byteen_lo_m, 2, 2) @[lsu_bus_buffer.scala 141:132] + node _T_125 = and(_T_123, _T_124) @[lsu_bus_buffer.scala 141:114] + node _T_126 = bits(buf_byteen[1], 2, 2) @[lsu_bus_buffer.scala 141:110] + node _T_127 = and(ld_addr_hitvec_lo_1, _T_126) @[lsu_bus_buffer.scala 141:95] + node _T_128 = bits(ldst_byteen_lo_m, 2, 2) @[lsu_bus_buffer.scala 141:132] + node _T_129 = and(_T_127, _T_128) @[lsu_bus_buffer.scala 141:114] + node _T_130 = bits(buf_byteen[2], 2, 2) @[lsu_bus_buffer.scala 141:110] + node _T_131 = and(ld_addr_hitvec_lo_2, _T_130) @[lsu_bus_buffer.scala 141:95] + node _T_132 = bits(ldst_byteen_lo_m, 2, 2) @[lsu_bus_buffer.scala 141:132] + node _T_133 = and(_T_131, _T_132) @[lsu_bus_buffer.scala 141:114] + node _T_134 = bits(buf_byteen[3], 2, 2) @[lsu_bus_buffer.scala 141:110] + node _T_135 = and(ld_addr_hitvec_lo_3, _T_134) @[lsu_bus_buffer.scala 141:95] + node _T_136 = bits(ldst_byteen_lo_m, 2, 2) @[lsu_bus_buffer.scala 141:132] + node _T_137 = and(_T_135, _T_136) @[lsu_bus_buffer.scala 141:114] node _T_138 = cat(_T_137, _T_133) @[Cat.scala 29:58] node _T_139 = cat(_T_138, _T_129) @[Cat.scala 29:58] node ld_byte_hitvec_lo_2 = cat(_T_139, _T_125) @[Cat.scala 29:58] - node _T_140 = bits(buf_byteen[0], 3, 3) @[lsu_bus_buffer.scala 140:110] - node _T_141 = and(ld_addr_hitvec_lo_0, _T_140) @[lsu_bus_buffer.scala 140:95] - node _T_142 = bits(ldst_byteen_lo_m, 3, 3) @[lsu_bus_buffer.scala 140:132] - node _T_143 = and(_T_141, _T_142) @[lsu_bus_buffer.scala 140:114] - node _T_144 = bits(buf_byteen[1], 3, 3) @[lsu_bus_buffer.scala 140:110] - node _T_145 = and(ld_addr_hitvec_lo_1, _T_144) @[lsu_bus_buffer.scala 140:95] - node _T_146 = bits(ldst_byteen_lo_m, 3, 3) @[lsu_bus_buffer.scala 140:132] - node _T_147 = and(_T_145, _T_146) @[lsu_bus_buffer.scala 140:114] - node _T_148 = bits(buf_byteen[2], 3, 3) @[lsu_bus_buffer.scala 140:110] - node _T_149 = and(ld_addr_hitvec_lo_2, _T_148) @[lsu_bus_buffer.scala 140:95] - node _T_150 = bits(ldst_byteen_lo_m, 3, 3) @[lsu_bus_buffer.scala 140:132] - node _T_151 = and(_T_149, _T_150) @[lsu_bus_buffer.scala 140:114] - node _T_152 = bits(buf_byteen[3], 3, 3) @[lsu_bus_buffer.scala 140:110] - node _T_153 = and(ld_addr_hitvec_lo_3, _T_152) @[lsu_bus_buffer.scala 140:95] - node _T_154 = bits(ldst_byteen_lo_m, 3, 3) @[lsu_bus_buffer.scala 140:132] - node _T_155 = and(_T_153, _T_154) @[lsu_bus_buffer.scala 140:114] + node _T_140 = bits(buf_byteen[0], 3, 3) @[lsu_bus_buffer.scala 141:110] + node _T_141 = and(ld_addr_hitvec_lo_0, _T_140) @[lsu_bus_buffer.scala 141:95] + node _T_142 = bits(ldst_byteen_lo_m, 3, 3) @[lsu_bus_buffer.scala 141:132] + node _T_143 = and(_T_141, _T_142) @[lsu_bus_buffer.scala 141:114] + node _T_144 = bits(buf_byteen[1], 3, 3) @[lsu_bus_buffer.scala 141:110] + node _T_145 = and(ld_addr_hitvec_lo_1, _T_144) @[lsu_bus_buffer.scala 141:95] + node _T_146 = bits(ldst_byteen_lo_m, 3, 3) @[lsu_bus_buffer.scala 141:132] + node _T_147 = and(_T_145, _T_146) @[lsu_bus_buffer.scala 141:114] + node _T_148 = bits(buf_byteen[2], 3, 3) @[lsu_bus_buffer.scala 141:110] + node _T_149 = and(ld_addr_hitvec_lo_2, _T_148) @[lsu_bus_buffer.scala 141:95] + node _T_150 = bits(ldst_byteen_lo_m, 3, 3) @[lsu_bus_buffer.scala 141:132] + node _T_151 = and(_T_149, _T_150) @[lsu_bus_buffer.scala 141:114] + node _T_152 = bits(buf_byteen[3], 3, 3) @[lsu_bus_buffer.scala 141:110] + node _T_153 = and(ld_addr_hitvec_lo_3, _T_152) @[lsu_bus_buffer.scala 141:95] + node _T_154 = bits(ldst_byteen_lo_m, 3, 3) @[lsu_bus_buffer.scala 141:132] + node _T_155 = and(_T_153, _T_154) @[lsu_bus_buffer.scala 141:114] node _T_156 = cat(_T_155, _T_151) @[Cat.scala 29:58] node _T_157 = cat(_T_156, _T_147) @[Cat.scala 29:58] node ld_byte_hitvec_lo_3 = cat(_T_157, _T_143) @[Cat.scala 29:58] - node _T_158 = bits(buf_byteen[0], 0, 0) @[lsu_bus_buffer.scala 141:110] - node _T_159 = and(ld_addr_hitvec_hi_0, _T_158) @[lsu_bus_buffer.scala 141:95] - node _T_160 = bits(ldst_byteen_hi_m, 0, 0) @[lsu_bus_buffer.scala 141:132] - node _T_161 = and(_T_159, _T_160) @[lsu_bus_buffer.scala 141:114] - node _T_162 = bits(buf_byteen[1], 0, 0) @[lsu_bus_buffer.scala 141:110] - node _T_163 = and(ld_addr_hitvec_hi_1, _T_162) @[lsu_bus_buffer.scala 141:95] - node _T_164 = bits(ldst_byteen_hi_m, 0, 0) @[lsu_bus_buffer.scala 141:132] - node _T_165 = and(_T_163, _T_164) @[lsu_bus_buffer.scala 141:114] - node _T_166 = bits(buf_byteen[2], 0, 0) @[lsu_bus_buffer.scala 141:110] - node _T_167 = and(ld_addr_hitvec_hi_2, _T_166) @[lsu_bus_buffer.scala 141:95] - node _T_168 = bits(ldst_byteen_hi_m, 0, 0) @[lsu_bus_buffer.scala 141:132] - node _T_169 = and(_T_167, _T_168) @[lsu_bus_buffer.scala 141:114] - node _T_170 = bits(buf_byteen[3], 0, 0) @[lsu_bus_buffer.scala 141:110] - node _T_171 = and(ld_addr_hitvec_hi_3, _T_170) @[lsu_bus_buffer.scala 141:95] - node _T_172 = bits(ldst_byteen_hi_m, 0, 0) @[lsu_bus_buffer.scala 141:132] - node _T_173 = and(_T_171, _T_172) @[lsu_bus_buffer.scala 141:114] + node _T_158 = bits(buf_byteen[0], 0, 0) @[lsu_bus_buffer.scala 142:110] + node _T_159 = and(ld_addr_hitvec_hi_0, _T_158) @[lsu_bus_buffer.scala 142:95] + node _T_160 = bits(ldst_byteen_hi_m, 0, 0) @[lsu_bus_buffer.scala 142:132] + node _T_161 = and(_T_159, _T_160) @[lsu_bus_buffer.scala 142:114] + node _T_162 = bits(buf_byteen[1], 0, 0) @[lsu_bus_buffer.scala 142:110] + node _T_163 = and(ld_addr_hitvec_hi_1, _T_162) @[lsu_bus_buffer.scala 142:95] + node _T_164 = bits(ldst_byteen_hi_m, 0, 0) @[lsu_bus_buffer.scala 142:132] + node _T_165 = and(_T_163, _T_164) @[lsu_bus_buffer.scala 142:114] + node _T_166 = bits(buf_byteen[2], 0, 0) @[lsu_bus_buffer.scala 142:110] + node _T_167 = and(ld_addr_hitvec_hi_2, _T_166) @[lsu_bus_buffer.scala 142:95] + node _T_168 = bits(ldst_byteen_hi_m, 0, 0) @[lsu_bus_buffer.scala 142:132] + node _T_169 = and(_T_167, _T_168) @[lsu_bus_buffer.scala 142:114] + node _T_170 = bits(buf_byteen[3], 0, 0) @[lsu_bus_buffer.scala 142:110] + node _T_171 = and(ld_addr_hitvec_hi_3, _T_170) @[lsu_bus_buffer.scala 142:95] + node _T_172 = bits(ldst_byteen_hi_m, 0, 0) @[lsu_bus_buffer.scala 142:132] + node _T_173 = and(_T_171, _T_172) @[lsu_bus_buffer.scala 142:114] node _T_174 = cat(_T_173, _T_169) @[Cat.scala 29:58] node _T_175 = cat(_T_174, _T_165) @[Cat.scala 29:58] node ld_byte_hitvec_hi_0 = cat(_T_175, _T_161) @[Cat.scala 29:58] - node _T_176 = bits(buf_byteen[0], 1, 1) @[lsu_bus_buffer.scala 141:110] - node _T_177 = and(ld_addr_hitvec_hi_0, _T_176) @[lsu_bus_buffer.scala 141:95] - node _T_178 = bits(ldst_byteen_hi_m, 1, 1) @[lsu_bus_buffer.scala 141:132] - node _T_179 = and(_T_177, _T_178) @[lsu_bus_buffer.scala 141:114] - node _T_180 = bits(buf_byteen[1], 1, 1) @[lsu_bus_buffer.scala 141:110] - node _T_181 = and(ld_addr_hitvec_hi_1, _T_180) @[lsu_bus_buffer.scala 141:95] - node _T_182 = bits(ldst_byteen_hi_m, 1, 1) @[lsu_bus_buffer.scala 141:132] - node _T_183 = and(_T_181, _T_182) @[lsu_bus_buffer.scala 141:114] - node _T_184 = bits(buf_byteen[2], 1, 1) @[lsu_bus_buffer.scala 141:110] - node _T_185 = and(ld_addr_hitvec_hi_2, _T_184) @[lsu_bus_buffer.scala 141:95] - node _T_186 = bits(ldst_byteen_hi_m, 1, 1) @[lsu_bus_buffer.scala 141:132] - node _T_187 = and(_T_185, _T_186) @[lsu_bus_buffer.scala 141:114] - node _T_188 = bits(buf_byteen[3], 1, 1) @[lsu_bus_buffer.scala 141:110] - node _T_189 = and(ld_addr_hitvec_hi_3, _T_188) @[lsu_bus_buffer.scala 141:95] - node _T_190 = bits(ldst_byteen_hi_m, 1, 1) @[lsu_bus_buffer.scala 141:132] - node _T_191 = and(_T_189, _T_190) @[lsu_bus_buffer.scala 141:114] + node _T_176 = bits(buf_byteen[0], 1, 1) @[lsu_bus_buffer.scala 142:110] + node _T_177 = and(ld_addr_hitvec_hi_0, _T_176) @[lsu_bus_buffer.scala 142:95] + node _T_178 = bits(ldst_byteen_hi_m, 1, 1) @[lsu_bus_buffer.scala 142:132] + node _T_179 = and(_T_177, _T_178) @[lsu_bus_buffer.scala 142:114] + node _T_180 = bits(buf_byteen[1], 1, 1) @[lsu_bus_buffer.scala 142:110] + node _T_181 = and(ld_addr_hitvec_hi_1, _T_180) @[lsu_bus_buffer.scala 142:95] + node _T_182 = bits(ldst_byteen_hi_m, 1, 1) @[lsu_bus_buffer.scala 142:132] + node _T_183 = and(_T_181, _T_182) @[lsu_bus_buffer.scala 142:114] + node _T_184 = bits(buf_byteen[2], 1, 1) @[lsu_bus_buffer.scala 142:110] + node _T_185 = and(ld_addr_hitvec_hi_2, _T_184) @[lsu_bus_buffer.scala 142:95] + node _T_186 = bits(ldst_byteen_hi_m, 1, 1) @[lsu_bus_buffer.scala 142:132] + node _T_187 = and(_T_185, _T_186) @[lsu_bus_buffer.scala 142:114] + node _T_188 = bits(buf_byteen[3], 1, 1) @[lsu_bus_buffer.scala 142:110] + node _T_189 = and(ld_addr_hitvec_hi_3, _T_188) @[lsu_bus_buffer.scala 142:95] + node _T_190 = bits(ldst_byteen_hi_m, 1, 1) @[lsu_bus_buffer.scala 142:132] + node _T_191 = and(_T_189, _T_190) @[lsu_bus_buffer.scala 142:114] node _T_192 = cat(_T_191, _T_187) @[Cat.scala 29:58] node _T_193 = cat(_T_192, _T_183) @[Cat.scala 29:58] node ld_byte_hitvec_hi_1 = cat(_T_193, _T_179) @[Cat.scala 29:58] - node _T_194 = bits(buf_byteen[0], 2, 2) @[lsu_bus_buffer.scala 141:110] - node _T_195 = and(ld_addr_hitvec_hi_0, _T_194) @[lsu_bus_buffer.scala 141:95] - node _T_196 = bits(ldst_byteen_hi_m, 2, 2) @[lsu_bus_buffer.scala 141:132] - node _T_197 = and(_T_195, _T_196) @[lsu_bus_buffer.scala 141:114] - node _T_198 = bits(buf_byteen[1], 2, 2) @[lsu_bus_buffer.scala 141:110] - node _T_199 = and(ld_addr_hitvec_hi_1, _T_198) @[lsu_bus_buffer.scala 141:95] - node _T_200 = bits(ldst_byteen_hi_m, 2, 2) @[lsu_bus_buffer.scala 141:132] - node _T_201 = and(_T_199, _T_200) @[lsu_bus_buffer.scala 141:114] - node _T_202 = bits(buf_byteen[2], 2, 2) @[lsu_bus_buffer.scala 141:110] - node _T_203 = and(ld_addr_hitvec_hi_2, _T_202) @[lsu_bus_buffer.scala 141:95] - node _T_204 = bits(ldst_byteen_hi_m, 2, 2) @[lsu_bus_buffer.scala 141:132] - node _T_205 = and(_T_203, _T_204) @[lsu_bus_buffer.scala 141:114] - node _T_206 = bits(buf_byteen[3], 2, 2) @[lsu_bus_buffer.scala 141:110] - node _T_207 = and(ld_addr_hitvec_hi_3, _T_206) @[lsu_bus_buffer.scala 141:95] - node _T_208 = bits(ldst_byteen_hi_m, 2, 2) @[lsu_bus_buffer.scala 141:132] - node _T_209 = and(_T_207, _T_208) @[lsu_bus_buffer.scala 141:114] + node _T_194 = bits(buf_byteen[0], 2, 2) @[lsu_bus_buffer.scala 142:110] + node _T_195 = and(ld_addr_hitvec_hi_0, _T_194) @[lsu_bus_buffer.scala 142:95] + node _T_196 = bits(ldst_byteen_hi_m, 2, 2) @[lsu_bus_buffer.scala 142:132] + node _T_197 = and(_T_195, _T_196) @[lsu_bus_buffer.scala 142:114] + node _T_198 = bits(buf_byteen[1], 2, 2) @[lsu_bus_buffer.scala 142:110] + node _T_199 = and(ld_addr_hitvec_hi_1, _T_198) @[lsu_bus_buffer.scala 142:95] + node _T_200 = bits(ldst_byteen_hi_m, 2, 2) @[lsu_bus_buffer.scala 142:132] + node _T_201 = and(_T_199, _T_200) @[lsu_bus_buffer.scala 142:114] + node _T_202 = bits(buf_byteen[2], 2, 2) @[lsu_bus_buffer.scala 142:110] + node _T_203 = and(ld_addr_hitvec_hi_2, _T_202) @[lsu_bus_buffer.scala 142:95] + node _T_204 = bits(ldst_byteen_hi_m, 2, 2) @[lsu_bus_buffer.scala 142:132] + node _T_205 = and(_T_203, _T_204) @[lsu_bus_buffer.scala 142:114] + node _T_206 = bits(buf_byteen[3], 2, 2) @[lsu_bus_buffer.scala 142:110] + node _T_207 = and(ld_addr_hitvec_hi_3, _T_206) @[lsu_bus_buffer.scala 142:95] + node _T_208 = bits(ldst_byteen_hi_m, 2, 2) @[lsu_bus_buffer.scala 142:132] + node _T_209 = and(_T_207, _T_208) @[lsu_bus_buffer.scala 142:114] node _T_210 = cat(_T_209, _T_205) @[Cat.scala 29:58] node _T_211 = cat(_T_210, _T_201) @[Cat.scala 29:58] node ld_byte_hitvec_hi_2 = cat(_T_211, _T_197) @[Cat.scala 29:58] - node _T_212 = bits(buf_byteen[0], 3, 3) @[lsu_bus_buffer.scala 141:110] - node _T_213 = and(ld_addr_hitvec_hi_0, _T_212) @[lsu_bus_buffer.scala 141:95] - node _T_214 = bits(ldst_byteen_hi_m, 3, 3) @[lsu_bus_buffer.scala 141:132] - node _T_215 = and(_T_213, _T_214) @[lsu_bus_buffer.scala 141:114] - node _T_216 = bits(buf_byteen[1], 3, 3) @[lsu_bus_buffer.scala 141:110] - node _T_217 = and(ld_addr_hitvec_hi_1, _T_216) @[lsu_bus_buffer.scala 141:95] - node _T_218 = bits(ldst_byteen_hi_m, 3, 3) @[lsu_bus_buffer.scala 141:132] - node _T_219 = and(_T_217, _T_218) @[lsu_bus_buffer.scala 141:114] - node _T_220 = bits(buf_byteen[2], 3, 3) @[lsu_bus_buffer.scala 141:110] - node _T_221 = and(ld_addr_hitvec_hi_2, _T_220) @[lsu_bus_buffer.scala 141:95] - node _T_222 = bits(ldst_byteen_hi_m, 3, 3) @[lsu_bus_buffer.scala 141:132] - node _T_223 = and(_T_221, _T_222) @[lsu_bus_buffer.scala 141:114] - node _T_224 = bits(buf_byteen[3], 3, 3) @[lsu_bus_buffer.scala 141:110] - node _T_225 = and(ld_addr_hitvec_hi_3, _T_224) @[lsu_bus_buffer.scala 141:95] - node _T_226 = bits(ldst_byteen_hi_m, 3, 3) @[lsu_bus_buffer.scala 141:132] - node _T_227 = and(_T_225, _T_226) @[lsu_bus_buffer.scala 141:114] + node _T_212 = bits(buf_byteen[0], 3, 3) @[lsu_bus_buffer.scala 142:110] + node _T_213 = and(ld_addr_hitvec_hi_0, _T_212) @[lsu_bus_buffer.scala 142:95] + node _T_214 = bits(ldst_byteen_hi_m, 3, 3) @[lsu_bus_buffer.scala 142:132] + node _T_215 = and(_T_213, _T_214) @[lsu_bus_buffer.scala 142:114] + node _T_216 = bits(buf_byteen[1], 3, 3) @[lsu_bus_buffer.scala 142:110] + node _T_217 = and(ld_addr_hitvec_hi_1, _T_216) @[lsu_bus_buffer.scala 142:95] + node _T_218 = bits(ldst_byteen_hi_m, 3, 3) @[lsu_bus_buffer.scala 142:132] + node _T_219 = and(_T_217, _T_218) @[lsu_bus_buffer.scala 142:114] + node _T_220 = bits(buf_byteen[2], 3, 3) @[lsu_bus_buffer.scala 142:110] + node _T_221 = and(ld_addr_hitvec_hi_2, _T_220) @[lsu_bus_buffer.scala 142:95] + node _T_222 = bits(ldst_byteen_hi_m, 3, 3) @[lsu_bus_buffer.scala 142:132] + node _T_223 = and(_T_221, _T_222) @[lsu_bus_buffer.scala 142:114] + node _T_224 = bits(buf_byteen[3], 3, 3) @[lsu_bus_buffer.scala 142:110] + node _T_225 = and(ld_addr_hitvec_hi_3, _T_224) @[lsu_bus_buffer.scala 142:95] + node _T_226 = bits(ldst_byteen_hi_m, 3, 3) @[lsu_bus_buffer.scala 142:132] + node _T_227 = and(_T_225, _T_226) @[lsu_bus_buffer.scala 142:114] node _T_228 = cat(_T_227, _T_223) @[Cat.scala 29:58] node _T_229 = cat(_T_228, _T_219) @[Cat.scala 29:58] node ld_byte_hitvec_hi_3 = cat(_T_229, _T_215) @[Cat.scala 29:58] - wire buf_age_younger : UInt<4>[4] @[lsu_bus_buffer.scala 143:29] - buf_age_younger[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 144:19] - buf_age_younger[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 144:19] - buf_age_younger[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 144:19] - buf_age_younger[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 144:19] - node _T_230 = bits(ld_byte_hitvec_lo_0, 0, 0) @[lsu_bus_buffer.scala 145:93] - node _T_231 = and(ld_byte_hitvec_lo_0, buf_age_younger[0]) @[lsu_bus_buffer.scala 145:122] - node _T_232 = orr(_T_231) @[lsu_bus_buffer.scala 145:144] - node _T_233 = eq(_T_232, UInt<1>("h00")) @[lsu_bus_buffer.scala 145:99] - node _T_234 = and(_T_230, _T_233) @[lsu_bus_buffer.scala 145:97] - node _T_235 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[lsu_bus_buffer.scala 145:170] - node _T_236 = eq(_T_235, UInt<1>("h00")) @[lsu_bus_buffer.scala 145:150] - node _T_237 = and(_T_234, _T_236) @[lsu_bus_buffer.scala 145:148] - node _T_238 = bits(ld_byte_hitvec_lo_0, 1, 1) @[lsu_bus_buffer.scala 145:93] - node _T_239 = and(ld_byte_hitvec_lo_0, buf_age_younger[1]) @[lsu_bus_buffer.scala 145:122] - node _T_240 = orr(_T_239) @[lsu_bus_buffer.scala 145:144] - node _T_241 = eq(_T_240, UInt<1>("h00")) @[lsu_bus_buffer.scala 145:99] - node _T_242 = and(_T_238, _T_241) @[lsu_bus_buffer.scala 145:97] - node _T_243 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[lsu_bus_buffer.scala 145:170] - node _T_244 = eq(_T_243, UInt<1>("h00")) @[lsu_bus_buffer.scala 145:150] - node _T_245 = and(_T_242, _T_244) @[lsu_bus_buffer.scala 145:148] - node _T_246 = bits(ld_byte_hitvec_lo_0, 2, 2) @[lsu_bus_buffer.scala 145:93] - node _T_247 = and(ld_byte_hitvec_lo_0, buf_age_younger[2]) @[lsu_bus_buffer.scala 145:122] - node _T_248 = orr(_T_247) @[lsu_bus_buffer.scala 145:144] - node _T_249 = eq(_T_248, UInt<1>("h00")) @[lsu_bus_buffer.scala 145:99] - node _T_250 = and(_T_246, _T_249) @[lsu_bus_buffer.scala 145:97] - node _T_251 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[lsu_bus_buffer.scala 145:170] - node _T_252 = eq(_T_251, UInt<1>("h00")) @[lsu_bus_buffer.scala 145:150] - node _T_253 = and(_T_250, _T_252) @[lsu_bus_buffer.scala 145:148] - node _T_254 = bits(ld_byte_hitvec_lo_0, 3, 3) @[lsu_bus_buffer.scala 145:93] - node _T_255 = and(ld_byte_hitvec_lo_0, buf_age_younger[3]) @[lsu_bus_buffer.scala 145:122] - node _T_256 = orr(_T_255) @[lsu_bus_buffer.scala 145:144] - node _T_257 = eq(_T_256, UInt<1>("h00")) @[lsu_bus_buffer.scala 145:99] - node _T_258 = and(_T_254, _T_257) @[lsu_bus_buffer.scala 145:97] - node _T_259 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[lsu_bus_buffer.scala 145:170] - node _T_260 = eq(_T_259, UInt<1>("h00")) @[lsu_bus_buffer.scala 145:150] - node _T_261 = and(_T_258, _T_260) @[lsu_bus_buffer.scala 145:148] + wire buf_age_younger : UInt<4>[4] @[lsu_bus_buffer.scala 144:29] + buf_age_younger[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 145:19] + buf_age_younger[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 145:19] + buf_age_younger[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 145:19] + buf_age_younger[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 145:19] + node _T_230 = bits(ld_byte_hitvec_lo_0, 0, 0) @[lsu_bus_buffer.scala 146:93] + node _T_231 = and(ld_byte_hitvec_lo_0, buf_age_younger[0]) @[lsu_bus_buffer.scala 146:122] + node _T_232 = orr(_T_231) @[lsu_bus_buffer.scala 146:144] + node _T_233 = eq(_T_232, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] + node _T_234 = and(_T_230, _T_233) @[lsu_bus_buffer.scala 146:97] + node _T_235 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[lsu_bus_buffer.scala 146:170] + node _T_236 = eq(_T_235, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] + node _T_237 = and(_T_234, _T_236) @[lsu_bus_buffer.scala 146:148] + node _T_238 = bits(ld_byte_hitvec_lo_0, 1, 1) @[lsu_bus_buffer.scala 146:93] + node _T_239 = and(ld_byte_hitvec_lo_0, buf_age_younger[1]) @[lsu_bus_buffer.scala 146:122] + node _T_240 = orr(_T_239) @[lsu_bus_buffer.scala 146:144] + node _T_241 = eq(_T_240, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] + node _T_242 = and(_T_238, _T_241) @[lsu_bus_buffer.scala 146:97] + node _T_243 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[lsu_bus_buffer.scala 146:170] + node _T_244 = eq(_T_243, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] + node _T_245 = and(_T_242, _T_244) @[lsu_bus_buffer.scala 146:148] + node _T_246 = bits(ld_byte_hitvec_lo_0, 2, 2) @[lsu_bus_buffer.scala 146:93] + node _T_247 = and(ld_byte_hitvec_lo_0, buf_age_younger[2]) @[lsu_bus_buffer.scala 146:122] + node _T_248 = orr(_T_247) @[lsu_bus_buffer.scala 146:144] + node _T_249 = eq(_T_248, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] + node _T_250 = and(_T_246, _T_249) @[lsu_bus_buffer.scala 146:97] + node _T_251 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[lsu_bus_buffer.scala 146:170] + node _T_252 = eq(_T_251, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] + node _T_253 = and(_T_250, _T_252) @[lsu_bus_buffer.scala 146:148] + node _T_254 = bits(ld_byte_hitvec_lo_0, 3, 3) @[lsu_bus_buffer.scala 146:93] + node _T_255 = and(ld_byte_hitvec_lo_0, buf_age_younger[3]) @[lsu_bus_buffer.scala 146:122] + node _T_256 = orr(_T_255) @[lsu_bus_buffer.scala 146:144] + node _T_257 = eq(_T_256, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] + node _T_258 = and(_T_254, _T_257) @[lsu_bus_buffer.scala 146:97] + node _T_259 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[lsu_bus_buffer.scala 146:170] + node _T_260 = eq(_T_259, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] + node _T_261 = and(_T_258, _T_260) @[lsu_bus_buffer.scala 146:148] node _T_262 = cat(_T_261, _T_253) @[Cat.scala 29:58] node _T_263 = cat(_T_262, _T_245) @[Cat.scala 29:58] node _T_264 = cat(_T_263, _T_237) @[Cat.scala 29:58] - node _T_265 = bits(ld_byte_hitvec_lo_1, 0, 0) @[lsu_bus_buffer.scala 145:93] - node _T_266 = and(ld_byte_hitvec_lo_1, buf_age_younger[0]) @[lsu_bus_buffer.scala 145:122] - node _T_267 = orr(_T_266) @[lsu_bus_buffer.scala 145:144] - node _T_268 = eq(_T_267, UInt<1>("h00")) @[lsu_bus_buffer.scala 145:99] - node _T_269 = and(_T_265, _T_268) @[lsu_bus_buffer.scala 145:97] - node _T_270 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[lsu_bus_buffer.scala 145:170] - node _T_271 = eq(_T_270, UInt<1>("h00")) @[lsu_bus_buffer.scala 145:150] - node _T_272 = and(_T_269, _T_271) @[lsu_bus_buffer.scala 145:148] - node _T_273 = bits(ld_byte_hitvec_lo_1, 1, 1) @[lsu_bus_buffer.scala 145:93] - node _T_274 = and(ld_byte_hitvec_lo_1, buf_age_younger[1]) @[lsu_bus_buffer.scala 145:122] - node _T_275 = orr(_T_274) @[lsu_bus_buffer.scala 145:144] - node _T_276 = eq(_T_275, UInt<1>("h00")) @[lsu_bus_buffer.scala 145:99] - node _T_277 = and(_T_273, _T_276) @[lsu_bus_buffer.scala 145:97] - node _T_278 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[lsu_bus_buffer.scala 145:170] - node _T_279 = eq(_T_278, UInt<1>("h00")) @[lsu_bus_buffer.scala 145:150] - node _T_280 = and(_T_277, _T_279) @[lsu_bus_buffer.scala 145:148] - node _T_281 = bits(ld_byte_hitvec_lo_1, 2, 2) @[lsu_bus_buffer.scala 145:93] - node _T_282 = and(ld_byte_hitvec_lo_1, buf_age_younger[2]) @[lsu_bus_buffer.scala 145:122] - node _T_283 = orr(_T_282) @[lsu_bus_buffer.scala 145:144] - node _T_284 = eq(_T_283, UInt<1>("h00")) @[lsu_bus_buffer.scala 145:99] - node _T_285 = and(_T_281, _T_284) @[lsu_bus_buffer.scala 145:97] - node _T_286 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[lsu_bus_buffer.scala 145:170] - node _T_287 = eq(_T_286, UInt<1>("h00")) @[lsu_bus_buffer.scala 145:150] - node _T_288 = and(_T_285, _T_287) @[lsu_bus_buffer.scala 145:148] - node _T_289 = bits(ld_byte_hitvec_lo_1, 3, 3) @[lsu_bus_buffer.scala 145:93] - node _T_290 = and(ld_byte_hitvec_lo_1, buf_age_younger[3]) @[lsu_bus_buffer.scala 145:122] - node _T_291 = orr(_T_290) @[lsu_bus_buffer.scala 145:144] - node _T_292 = eq(_T_291, UInt<1>("h00")) @[lsu_bus_buffer.scala 145:99] - node _T_293 = and(_T_289, _T_292) @[lsu_bus_buffer.scala 145:97] - node _T_294 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[lsu_bus_buffer.scala 145:170] - node _T_295 = eq(_T_294, UInt<1>("h00")) @[lsu_bus_buffer.scala 145:150] - node _T_296 = and(_T_293, _T_295) @[lsu_bus_buffer.scala 145:148] + node _T_265 = bits(ld_byte_hitvec_lo_1, 0, 0) @[lsu_bus_buffer.scala 146:93] + node _T_266 = and(ld_byte_hitvec_lo_1, buf_age_younger[0]) @[lsu_bus_buffer.scala 146:122] + node _T_267 = orr(_T_266) @[lsu_bus_buffer.scala 146:144] + node _T_268 = eq(_T_267, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] + node _T_269 = and(_T_265, _T_268) @[lsu_bus_buffer.scala 146:97] + node _T_270 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[lsu_bus_buffer.scala 146:170] + node _T_271 = eq(_T_270, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] + node _T_272 = and(_T_269, _T_271) @[lsu_bus_buffer.scala 146:148] + node _T_273 = bits(ld_byte_hitvec_lo_1, 1, 1) @[lsu_bus_buffer.scala 146:93] + node _T_274 = and(ld_byte_hitvec_lo_1, buf_age_younger[1]) @[lsu_bus_buffer.scala 146:122] + node _T_275 = orr(_T_274) @[lsu_bus_buffer.scala 146:144] + node _T_276 = eq(_T_275, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] + node _T_277 = and(_T_273, _T_276) @[lsu_bus_buffer.scala 146:97] + node _T_278 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[lsu_bus_buffer.scala 146:170] + node _T_279 = eq(_T_278, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] + node _T_280 = and(_T_277, _T_279) @[lsu_bus_buffer.scala 146:148] + node _T_281 = bits(ld_byte_hitvec_lo_1, 2, 2) @[lsu_bus_buffer.scala 146:93] + node _T_282 = and(ld_byte_hitvec_lo_1, buf_age_younger[2]) @[lsu_bus_buffer.scala 146:122] + node _T_283 = orr(_T_282) @[lsu_bus_buffer.scala 146:144] + node _T_284 = eq(_T_283, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] + node _T_285 = and(_T_281, _T_284) @[lsu_bus_buffer.scala 146:97] + node _T_286 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[lsu_bus_buffer.scala 146:170] + node _T_287 = eq(_T_286, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] + node _T_288 = and(_T_285, _T_287) @[lsu_bus_buffer.scala 146:148] + node _T_289 = bits(ld_byte_hitvec_lo_1, 3, 3) @[lsu_bus_buffer.scala 146:93] + node _T_290 = and(ld_byte_hitvec_lo_1, buf_age_younger[3]) @[lsu_bus_buffer.scala 146:122] + node _T_291 = orr(_T_290) @[lsu_bus_buffer.scala 146:144] + node _T_292 = eq(_T_291, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] + node _T_293 = and(_T_289, _T_292) @[lsu_bus_buffer.scala 146:97] + node _T_294 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[lsu_bus_buffer.scala 146:170] + node _T_295 = eq(_T_294, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] + node _T_296 = and(_T_293, _T_295) @[lsu_bus_buffer.scala 146:148] node _T_297 = cat(_T_296, _T_288) @[Cat.scala 29:58] node _T_298 = cat(_T_297, _T_280) @[Cat.scala 29:58] node _T_299 = cat(_T_298, _T_272) @[Cat.scala 29:58] - node _T_300 = bits(ld_byte_hitvec_lo_2, 0, 0) @[lsu_bus_buffer.scala 145:93] - node _T_301 = and(ld_byte_hitvec_lo_2, buf_age_younger[0]) @[lsu_bus_buffer.scala 145:122] - node _T_302 = orr(_T_301) @[lsu_bus_buffer.scala 145:144] - node _T_303 = eq(_T_302, UInt<1>("h00")) @[lsu_bus_buffer.scala 145:99] - node _T_304 = and(_T_300, _T_303) @[lsu_bus_buffer.scala 145:97] - node _T_305 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[lsu_bus_buffer.scala 145:170] - node _T_306 = eq(_T_305, UInt<1>("h00")) @[lsu_bus_buffer.scala 145:150] - node _T_307 = and(_T_304, _T_306) @[lsu_bus_buffer.scala 145:148] - node _T_308 = bits(ld_byte_hitvec_lo_2, 1, 1) @[lsu_bus_buffer.scala 145:93] - node _T_309 = and(ld_byte_hitvec_lo_2, buf_age_younger[1]) @[lsu_bus_buffer.scala 145:122] - node _T_310 = orr(_T_309) @[lsu_bus_buffer.scala 145:144] - node _T_311 = eq(_T_310, UInt<1>("h00")) @[lsu_bus_buffer.scala 145:99] - node _T_312 = and(_T_308, _T_311) @[lsu_bus_buffer.scala 145:97] - node _T_313 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[lsu_bus_buffer.scala 145:170] - node _T_314 = eq(_T_313, UInt<1>("h00")) @[lsu_bus_buffer.scala 145:150] - node _T_315 = and(_T_312, _T_314) @[lsu_bus_buffer.scala 145:148] - node _T_316 = bits(ld_byte_hitvec_lo_2, 2, 2) @[lsu_bus_buffer.scala 145:93] - node _T_317 = and(ld_byte_hitvec_lo_2, buf_age_younger[2]) @[lsu_bus_buffer.scala 145:122] - node _T_318 = orr(_T_317) @[lsu_bus_buffer.scala 145:144] - node _T_319 = eq(_T_318, UInt<1>("h00")) @[lsu_bus_buffer.scala 145:99] - node _T_320 = and(_T_316, _T_319) @[lsu_bus_buffer.scala 145:97] - node _T_321 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[lsu_bus_buffer.scala 145:170] - node _T_322 = eq(_T_321, UInt<1>("h00")) @[lsu_bus_buffer.scala 145:150] - node _T_323 = and(_T_320, _T_322) @[lsu_bus_buffer.scala 145:148] - node _T_324 = bits(ld_byte_hitvec_lo_2, 3, 3) @[lsu_bus_buffer.scala 145:93] - node _T_325 = and(ld_byte_hitvec_lo_2, buf_age_younger[3]) @[lsu_bus_buffer.scala 145:122] - node _T_326 = orr(_T_325) @[lsu_bus_buffer.scala 145:144] - node _T_327 = eq(_T_326, UInt<1>("h00")) @[lsu_bus_buffer.scala 145:99] - node _T_328 = and(_T_324, _T_327) @[lsu_bus_buffer.scala 145:97] - node _T_329 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[lsu_bus_buffer.scala 145:170] - node _T_330 = eq(_T_329, UInt<1>("h00")) @[lsu_bus_buffer.scala 145:150] - node _T_331 = and(_T_328, _T_330) @[lsu_bus_buffer.scala 145:148] + node _T_300 = bits(ld_byte_hitvec_lo_2, 0, 0) @[lsu_bus_buffer.scala 146:93] + node _T_301 = and(ld_byte_hitvec_lo_2, buf_age_younger[0]) @[lsu_bus_buffer.scala 146:122] + node _T_302 = orr(_T_301) @[lsu_bus_buffer.scala 146:144] + node _T_303 = eq(_T_302, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] + node _T_304 = and(_T_300, _T_303) @[lsu_bus_buffer.scala 146:97] + node _T_305 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[lsu_bus_buffer.scala 146:170] + node _T_306 = eq(_T_305, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] + node _T_307 = and(_T_304, _T_306) @[lsu_bus_buffer.scala 146:148] + node _T_308 = bits(ld_byte_hitvec_lo_2, 1, 1) @[lsu_bus_buffer.scala 146:93] + node _T_309 = and(ld_byte_hitvec_lo_2, buf_age_younger[1]) @[lsu_bus_buffer.scala 146:122] + node _T_310 = orr(_T_309) @[lsu_bus_buffer.scala 146:144] + node _T_311 = eq(_T_310, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] + node _T_312 = and(_T_308, _T_311) @[lsu_bus_buffer.scala 146:97] + node _T_313 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[lsu_bus_buffer.scala 146:170] + node _T_314 = eq(_T_313, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] + node _T_315 = and(_T_312, _T_314) @[lsu_bus_buffer.scala 146:148] + node _T_316 = bits(ld_byte_hitvec_lo_2, 2, 2) @[lsu_bus_buffer.scala 146:93] + node _T_317 = and(ld_byte_hitvec_lo_2, buf_age_younger[2]) @[lsu_bus_buffer.scala 146:122] + node _T_318 = orr(_T_317) @[lsu_bus_buffer.scala 146:144] + node _T_319 = eq(_T_318, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] + node _T_320 = and(_T_316, _T_319) @[lsu_bus_buffer.scala 146:97] + node _T_321 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[lsu_bus_buffer.scala 146:170] + node _T_322 = eq(_T_321, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] + node _T_323 = and(_T_320, _T_322) @[lsu_bus_buffer.scala 146:148] + node _T_324 = bits(ld_byte_hitvec_lo_2, 3, 3) @[lsu_bus_buffer.scala 146:93] + node _T_325 = and(ld_byte_hitvec_lo_2, buf_age_younger[3]) @[lsu_bus_buffer.scala 146:122] + node _T_326 = orr(_T_325) @[lsu_bus_buffer.scala 146:144] + node _T_327 = eq(_T_326, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] + node _T_328 = and(_T_324, _T_327) @[lsu_bus_buffer.scala 146:97] + node _T_329 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[lsu_bus_buffer.scala 146:170] + node _T_330 = eq(_T_329, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] + node _T_331 = and(_T_328, _T_330) @[lsu_bus_buffer.scala 146:148] node _T_332 = cat(_T_331, _T_323) @[Cat.scala 29:58] node _T_333 = cat(_T_332, _T_315) @[Cat.scala 29:58] node _T_334 = cat(_T_333, _T_307) @[Cat.scala 29:58] - node _T_335 = bits(ld_byte_hitvec_lo_3, 0, 0) @[lsu_bus_buffer.scala 145:93] - node _T_336 = and(ld_byte_hitvec_lo_3, buf_age_younger[0]) @[lsu_bus_buffer.scala 145:122] - node _T_337 = orr(_T_336) @[lsu_bus_buffer.scala 145:144] - node _T_338 = eq(_T_337, UInt<1>("h00")) @[lsu_bus_buffer.scala 145:99] - node _T_339 = and(_T_335, _T_338) @[lsu_bus_buffer.scala 145:97] - node _T_340 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[lsu_bus_buffer.scala 145:170] - node _T_341 = eq(_T_340, UInt<1>("h00")) @[lsu_bus_buffer.scala 145:150] - node _T_342 = and(_T_339, _T_341) @[lsu_bus_buffer.scala 145:148] - node _T_343 = bits(ld_byte_hitvec_lo_3, 1, 1) @[lsu_bus_buffer.scala 145:93] - node _T_344 = and(ld_byte_hitvec_lo_3, buf_age_younger[1]) @[lsu_bus_buffer.scala 145:122] - node _T_345 = orr(_T_344) @[lsu_bus_buffer.scala 145:144] - node _T_346 = eq(_T_345, UInt<1>("h00")) @[lsu_bus_buffer.scala 145:99] - node _T_347 = and(_T_343, _T_346) @[lsu_bus_buffer.scala 145:97] - node _T_348 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[lsu_bus_buffer.scala 145:170] - node _T_349 = eq(_T_348, UInt<1>("h00")) @[lsu_bus_buffer.scala 145:150] - node _T_350 = and(_T_347, _T_349) @[lsu_bus_buffer.scala 145:148] - node _T_351 = bits(ld_byte_hitvec_lo_3, 2, 2) @[lsu_bus_buffer.scala 145:93] - node _T_352 = and(ld_byte_hitvec_lo_3, buf_age_younger[2]) @[lsu_bus_buffer.scala 145:122] - node _T_353 = orr(_T_352) @[lsu_bus_buffer.scala 145:144] - node _T_354 = eq(_T_353, UInt<1>("h00")) @[lsu_bus_buffer.scala 145:99] - node _T_355 = and(_T_351, _T_354) @[lsu_bus_buffer.scala 145:97] - node _T_356 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[lsu_bus_buffer.scala 145:170] - node _T_357 = eq(_T_356, UInt<1>("h00")) @[lsu_bus_buffer.scala 145:150] - node _T_358 = and(_T_355, _T_357) @[lsu_bus_buffer.scala 145:148] - node _T_359 = bits(ld_byte_hitvec_lo_3, 3, 3) @[lsu_bus_buffer.scala 145:93] - node _T_360 = and(ld_byte_hitvec_lo_3, buf_age_younger[3]) @[lsu_bus_buffer.scala 145:122] - node _T_361 = orr(_T_360) @[lsu_bus_buffer.scala 145:144] - node _T_362 = eq(_T_361, UInt<1>("h00")) @[lsu_bus_buffer.scala 145:99] - node _T_363 = and(_T_359, _T_362) @[lsu_bus_buffer.scala 145:97] - node _T_364 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[lsu_bus_buffer.scala 145:170] - node _T_365 = eq(_T_364, UInt<1>("h00")) @[lsu_bus_buffer.scala 145:150] - node _T_366 = and(_T_363, _T_365) @[lsu_bus_buffer.scala 145:148] + node _T_335 = bits(ld_byte_hitvec_lo_3, 0, 0) @[lsu_bus_buffer.scala 146:93] + node _T_336 = and(ld_byte_hitvec_lo_3, buf_age_younger[0]) @[lsu_bus_buffer.scala 146:122] + node _T_337 = orr(_T_336) @[lsu_bus_buffer.scala 146:144] + node _T_338 = eq(_T_337, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] + node _T_339 = and(_T_335, _T_338) @[lsu_bus_buffer.scala 146:97] + node _T_340 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[lsu_bus_buffer.scala 146:170] + node _T_341 = eq(_T_340, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] + node _T_342 = and(_T_339, _T_341) @[lsu_bus_buffer.scala 146:148] + node _T_343 = bits(ld_byte_hitvec_lo_3, 1, 1) @[lsu_bus_buffer.scala 146:93] + node _T_344 = and(ld_byte_hitvec_lo_3, buf_age_younger[1]) @[lsu_bus_buffer.scala 146:122] + node _T_345 = orr(_T_344) @[lsu_bus_buffer.scala 146:144] + node _T_346 = eq(_T_345, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] + node _T_347 = and(_T_343, _T_346) @[lsu_bus_buffer.scala 146:97] + node _T_348 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[lsu_bus_buffer.scala 146:170] + node _T_349 = eq(_T_348, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] + node _T_350 = and(_T_347, _T_349) @[lsu_bus_buffer.scala 146:148] + node _T_351 = bits(ld_byte_hitvec_lo_3, 2, 2) @[lsu_bus_buffer.scala 146:93] + node _T_352 = and(ld_byte_hitvec_lo_3, buf_age_younger[2]) @[lsu_bus_buffer.scala 146:122] + node _T_353 = orr(_T_352) @[lsu_bus_buffer.scala 146:144] + node _T_354 = eq(_T_353, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] + node _T_355 = and(_T_351, _T_354) @[lsu_bus_buffer.scala 146:97] + node _T_356 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[lsu_bus_buffer.scala 146:170] + node _T_357 = eq(_T_356, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] + node _T_358 = and(_T_355, _T_357) @[lsu_bus_buffer.scala 146:148] + node _T_359 = bits(ld_byte_hitvec_lo_3, 3, 3) @[lsu_bus_buffer.scala 146:93] + node _T_360 = and(ld_byte_hitvec_lo_3, buf_age_younger[3]) @[lsu_bus_buffer.scala 146:122] + node _T_361 = orr(_T_360) @[lsu_bus_buffer.scala 146:144] + node _T_362 = eq(_T_361, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] + node _T_363 = and(_T_359, _T_362) @[lsu_bus_buffer.scala 146:97] + node _T_364 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[lsu_bus_buffer.scala 146:170] + node _T_365 = eq(_T_364, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] + node _T_366 = and(_T_363, _T_365) @[lsu_bus_buffer.scala 146:148] node _T_367 = cat(_T_366, _T_358) @[Cat.scala 29:58] node _T_368 = cat(_T_367, _T_350) @[Cat.scala 29:58] node _T_369 = cat(_T_368, _T_342) @[Cat.scala 29:58] - ld_byte_hitvecfn_lo[0] <= _T_264 @[lsu_bus_buffer.scala 145:23] - ld_byte_hitvecfn_lo[1] <= _T_299 @[lsu_bus_buffer.scala 145:23] - ld_byte_hitvecfn_lo[2] <= _T_334 @[lsu_bus_buffer.scala 145:23] - ld_byte_hitvecfn_lo[3] <= _T_369 @[lsu_bus_buffer.scala 145:23] - node _T_370 = bits(ld_byte_hitvec_hi_0, 0, 0) @[lsu_bus_buffer.scala 146:93] - node _T_371 = and(ld_byte_hitvec_hi_0, buf_age_younger[0]) @[lsu_bus_buffer.scala 146:122] - node _T_372 = orr(_T_371) @[lsu_bus_buffer.scala 146:144] - node _T_373 = eq(_T_372, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] - node _T_374 = and(_T_370, _T_373) @[lsu_bus_buffer.scala 146:97] - node _T_375 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[lsu_bus_buffer.scala 146:170] - node _T_376 = eq(_T_375, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] - node _T_377 = and(_T_374, _T_376) @[lsu_bus_buffer.scala 146:148] - node _T_378 = bits(ld_byte_hitvec_hi_0, 1, 1) @[lsu_bus_buffer.scala 146:93] - node _T_379 = and(ld_byte_hitvec_hi_0, buf_age_younger[1]) @[lsu_bus_buffer.scala 146:122] - node _T_380 = orr(_T_379) @[lsu_bus_buffer.scala 146:144] - node _T_381 = eq(_T_380, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] - node _T_382 = and(_T_378, _T_381) @[lsu_bus_buffer.scala 146:97] - node _T_383 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[lsu_bus_buffer.scala 146:170] - node _T_384 = eq(_T_383, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] - node _T_385 = and(_T_382, _T_384) @[lsu_bus_buffer.scala 146:148] - node _T_386 = bits(ld_byte_hitvec_hi_0, 2, 2) @[lsu_bus_buffer.scala 146:93] - node _T_387 = and(ld_byte_hitvec_hi_0, buf_age_younger[2]) @[lsu_bus_buffer.scala 146:122] - node _T_388 = orr(_T_387) @[lsu_bus_buffer.scala 146:144] - node _T_389 = eq(_T_388, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] - node _T_390 = and(_T_386, _T_389) @[lsu_bus_buffer.scala 146:97] - node _T_391 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[lsu_bus_buffer.scala 146:170] - node _T_392 = eq(_T_391, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] - node _T_393 = and(_T_390, _T_392) @[lsu_bus_buffer.scala 146:148] - node _T_394 = bits(ld_byte_hitvec_hi_0, 3, 3) @[lsu_bus_buffer.scala 146:93] - node _T_395 = and(ld_byte_hitvec_hi_0, buf_age_younger[3]) @[lsu_bus_buffer.scala 146:122] - node _T_396 = orr(_T_395) @[lsu_bus_buffer.scala 146:144] - node _T_397 = eq(_T_396, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] - node _T_398 = and(_T_394, _T_397) @[lsu_bus_buffer.scala 146:97] - node _T_399 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[lsu_bus_buffer.scala 146:170] - node _T_400 = eq(_T_399, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] - node _T_401 = and(_T_398, _T_400) @[lsu_bus_buffer.scala 146:148] + ld_byte_hitvecfn_lo[0] <= _T_264 @[lsu_bus_buffer.scala 146:23] + ld_byte_hitvecfn_lo[1] <= _T_299 @[lsu_bus_buffer.scala 146:23] + ld_byte_hitvecfn_lo[2] <= _T_334 @[lsu_bus_buffer.scala 146:23] + ld_byte_hitvecfn_lo[3] <= _T_369 @[lsu_bus_buffer.scala 146:23] + node _T_370 = bits(ld_byte_hitvec_hi_0, 0, 0) @[lsu_bus_buffer.scala 147:93] + node _T_371 = and(ld_byte_hitvec_hi_0, buf_age_younger[0]) @[lsu_bus_buffer.scala 147:122] + node _T_372 = orr(_T_371) @[lsu_bus_buffer.scala 147:144] + node _T_373 = eq(_T_372, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:99] + node _T_374 = and(_T_370, _T_373) @[lsu_bus_buffer.scala 147:97] + node _T_375 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[lsu_bus_buffer.scala 147:170] + node _T_376 = eq(_T_375, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:150] + node _T_377 = and(_T_374, _T_376) @[lsu_bus_buffer.scala 147:148] + node _T_378 = bits(ld_byte_hitvec_hi_0, 1, 1) @[lsu_bus_buffer.scala 147:93] + node _T_379 = and(ld_byte_hitvec_hi_0, buf_age_younger[1]) @[lsu_bus_buffer.scala 147:122] + node _T_380 = orr(_T_379) @[lsu_bus_buffer.scala 147:144] + node _T_381 = eq(_T_380, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:99] + node _T_382 = and(_T_378, _T_381) @[lsu_bus_buffer.scala 147:97] + node _T_383 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[lsu_bus_buffer.scala 147:170] + node _T_384 = eq(_T_383, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:150] + node _T_385 = and(_T_382, _T_384) @[lsu_bus_buffer.scala 147:148] + node _T_386 = bits(ld_byte_hitvec_hi_0, 2, 2) @[lsu_bus_buffer.scala 147:93] + node _T_387 = and(ld_byte_hitvec_hi_0, buf_age_younger[2]) @[lsu_bus_buffer.scala 147:122] + node _T_388 = orr(_T_387) @[lsu_bus_buffer.scala 147:144] + node _T_389 = eq(_T_388, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:99] + node _T_390 = and(_T_386, _T_389) @[lsu_bus_buffer.scala 147:97] + node _T_391 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[lsu_bus_buffer.scala 147:170] + node _T_392 = eq(_T_391, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:150] + node _T_393 = and(_T_390, _T_392) @[lsu_bus_buffer.scala 147:148] + node _T_394 = bits(ld_byte_hitvec_hi_0, 3, 3) @[lsu_bus_buffer.scala 147:93] + node _T_395 = and(ld_byte_hitvec_hi_0, buf_age_younger[3]) @[lsu_bus_buffer.scala 147:122] + node _T_396 = orr(_T_395) @[lsu_bus_buffer.scala 147:144] + node _T_397 = eq(_T_396, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:99] + node _T_398 = and(_T_394, _T_397) @[lsu_bus_buffer.scala 147:97] + node _T_399 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[lsu_bus_buffer.scala 147:170] + node _T_400 = eq(_T_399, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:150] + node _T_401 = and(_T_398, _T_400) @[lsu_bus_buffer.scala 147:148] node _T_402 = cat(_T_401, _T_393) @[Cat.scala 29:58] node _T_403 = cat(_T_402, _T_385) @[Cat.scala 29:58] node _T_404 = cat(_T_403, _T_377) @[Cat.scala 29:58] - node _T_405 = bits(ld_byte_hitvec_hi_1, 0, 0) @[lsu_bus_buffer.scala 146:93] - node _T_406 = and(ld_byte_hitvec_hi_1, buf_age_younger[0]) @[lsu_bus_buffer.scala 146:122] - node _T_407 = orr(_T_406) @[lsu_bus_buffer.scala 146:144] - node _T_408 = eq(_T_407, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] - node _T_409 = and(_T_405, _T_408) @[lsu_bus_buffer.scala 146:97] - node _T_410 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[lsu_bus_buffer.scala 146:170] - node _T_411 = eq(_T_410, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] - node _T_412 = and(_T_409, _T_411) @[lsu_bus_buffer.scala 146:148] - node _T_413 = bits(ld_byte_hitvec_hi_1, 1, 1) @[lsu_bus_buffer.scala 146:93] - node _T_414 = and(ld_byte_hitvec_hi_1, buf_age_younger[1]) @[lsu_bus_buffer.scala 146:122] - node _T_415 = orr(_T_414) @[lsu_bus_buffer.scala 146:144] - node _T_416 = eq(_T_415, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] - node _T_417 = and(_T_413, _T_416) @[lsu_bus_buffer.scala 146:97] - node _T_418 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[lsu_bus_buffer.scala 146:170] - node _T_419 = eq(_T_418, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] - node _T_420 = and(_T_417, _T_419) @[lsu_bus_buffer.scala 146:148] - node _T_421 = bits(ld_byte_hitvec_hi_1, 2, 2) @[lsu_bus_buffer.scala 146:93] - node _T_422 = and(ld_byte_hitvec_hi_1, buf_age_younger[2]) @[lsu_bus_buffer.scala 146:122] - node _T_423 = orr(_T_422) @[lsu_bus_buffer.scala 146:144] - node _T_424 = eq(_T_423, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] - node _T_425 = and(_T_421, _T_424) @[lsu_bus_buffer.scala 146:97] - node _T_426 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[lsu_bus_buffer.scala 146:170] - node _T_427 = eq(_T_426, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] - node _T_428 = and(_T_425, _T_427) @[lsu_bus_buffer.scala 146:148] - node _T_429 = bits(ld_byte_hitvec_hi_1, 3, 3) @[lsu_bus_buffer.scala 146:93] - node _T_430 = and(ld_byte_hitvec_hi_1, buf_age_younger[3]) @[lsu_bus_buffer.scala 146:122] - node _T_431 = orr(_T_430) @[lsu_bus_buffer.scala 146:144] - node _T_432 = eq(_T_431, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] - node _T_433 = and(_T_429, _T_432) @[lsu_bus_buffer.scala 146:97] - node _T_434 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[lsu_bus_buffer.scala 146:170] - node _T_435 = eq(_T_434, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] - node _T_436 = and(_T_433, _T_435) @[lsu_bus_buffer.scala 146:148] + node _T_405 = bits(ld_byte_hitvec_hi_1, 0, 0) @[lsu_bus_buffer.scala 147:93] + node _T_406 = and(ld_byte_hitvec_hi_1, buf_age_younger[0]) @[lsu_bus_buffer.scala 147:122] + node _T_407 = orr(_T_406) @[lsu_bus_buffer.scala 147:144] + node _T_408 = eq(_T_407, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:99] + node _T_409 = and(_T_405, _T_408) @[lsu_bus_buffer.scala 147:97] + node _T_410 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[lsu_bus_buffer.scala 147:170] + node _T_411 = eq(_T_410, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:150] + node _T_412 = and(_T_409, _T_411) @[lsu_bus_buffer.scala 147:148] + node _T_413 = bits(ld_byte_hitvec_hi_1, 1, 1) @[lsu_bus_buffer.scala 147:93] + node _T_414 = and(ld_byte_hitvec_hi_1, buf_age_younger[1]) @[lsu_bus_buffer.scala 147:122] + node _T_415 = orr(_T_414) @[lsu_bus_buffer.scala 147:144] + node _T_416 = eq(_T_415, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:99] + node _T_417 = and(_T_413, _T_416) @[lsu_bus_buffer.scala 147:97] + node _T_418 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[lsu_bus_buffer.scala 147:170] + node _T_419 = eq(_T_418, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:150] + node _T_420 = and(_T_417, _T_419) @[lsu_bus_buffer.scala 147:148] + node _T_421 = bits(ld_byte_hitvec_hi_1, 2, 2) @[lsu_bus_buffer.scala 147:93] + node _T_422 = and(ld_byte_hitvec_hi_1, buf_age_younger[2]) @[lsu_bus_buffer.scala 147:122] + node _T_423 = orr(_T_422) @[lsu_bus_buffer.scala 147:144] + node _T_424 = eq(_T_423, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:99] + node _T_425 = and(_T_421, _T_424) @[lsu_bus_buffer.scala 147:97] + node _T_426 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[lsu_bus_buffer.scala 147:170] + node _T_427 = eq(_T_426, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:150] + node _T_428 = and(_T_425, _T_427) @[lsu_bus_buffer.scala 147:148] + node _T_429 = bits(ld_byte_hitvec_hi_1, 3, 3) @[lsu_bus_buffer.scala 147:93] + node _T_430 = and(ld_byte_hitvec_hi_1, buf_age_younger[3]) @[lsu_bus_buffer.scala 147:122] + node _T_431 = orr(_T_430) @[lsu_bus_buffer.scala 147:144] + node _T_432 = eq(_T_431, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:99] + node _T_433 = and(_T_429, _T_432) @[lsu_bus_buffer.scala 147:97] + node _T_434 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[lsu_bus_buffer.scala 147:170] + node _T_435 = eq(_T_434, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:150] + node _T_436 = and(_T_433, _T_435) @[lsu_bus_buffer.scala 147:148] node _T_437 = cat(_T_436, _T_428) @[Cat.scala 29:58] node _T_438 = cat(_T_437, _T_420) @[Cat.scala 29:58] node _T_439 = cat(_T_438, _T_412) @[Cat.scala 29:58] - node _T_440 = bits(ld_byte_hitvec_hi_2, 0, 0) @[lsu_bus_buffer.scala 146:93] - node _T_441 = and(ld_byte_hitvec_hi_2, buf_age_younger[0]) @[lsu_bus_buffer.scala 146:122] - node _T_442 = orr(_T_441) @[lsu_bus_buffer.scala 146:144] - node _T_443 = eq(_T_442, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] - node _T_444 = and(_T_440, _T_443) @[lsu_bus_buffer.scala 146:97] - node _T_445 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[lsu_bus_buffer.scala 146:170] - node _T_446 = eq(_T_445, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] - node _T_447 = and(_T_444, _T_446) @[lsu_bus_buffer.scala 146:148] - node _T_448 = bits(ld_byte_hitvec_hi_2, 1, 1) @[lsu_bus_buffer.scala 146:93] - node _T_449 = and(ld_byte_hitvec_hi_2, buf_age_younger[1]) @[lsu_bus_buffer.scala 146:122] - node _T_450 = orr(_T_449) @[lsu_bus_buffer.scala 146:144] - node _T_451 = eq(_T_450, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] - node _T_452 = and(_T_448, _T_451) @[lsu_bus_buffer.scala 146:97] - node _T_453 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[lsu_bus_buffer.scala 146:170] - node _T_454 = eq(_T_453, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] - node _T_455 = and(_T_452, _T_454) @[lsu_bus_buffer.scala 146:148] - node _T_456 = bits(ld_byte_hitvec_hi_2, 2, 2) @[lsu_bus_buffer.scala 146:93] - node _T_457 = and(ld_byte_hitvec_hi_2, buf_age_younger[2]) @[lsu_bus_buffer.scala 146:122] - node _T_458 = orr(_T_457) @[lsu_bus_buffer.scala 146:144] - node _T_459 = eq(_T_458, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] - node _T_460 = and(_T_456, _T_459) @[lsu_bus_buffer.scala 146:97] - node _T_461 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[lsu_bus_buffer.scala 146:170] - node _T_462 = eq(_T_461, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] - node _T_463 = and(_T_460, _T_462) @[lsu_bus_buffer.scala 146:148] - node _T_464 = bits(ld_byte_hitvec_hi_2, 3, 3) @[lsu_bus_buffer.scala 146:93] - node _T_465 = and(ld_byte_hitvec_hi_2, buf_age_younger[3]) @[lsu_bus_buffer.scala 146:122] - node _T_466 = orr(_T_465) @[lsu_bus_buffer.scala 146:144] - node _T_467 = eq(_T_466, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] - node _T_468 = and(_T_464, _T_467) @[lsu_bus_buffer.scala 146:97] - node _T_469 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[lsu_bus_buffer.scala 146:170] - node _T_470 = eq(_T_469, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] - node _T_471 = and(_T_468, _T_470) @[lsu_bus_buffer.scala 146:148] + node _T_440 = bits(ld_byte_hitvec_hi_2, 0, 0) @[lsu_bus_buffer.scala 147:93] + node _T_441 = and(ld_byte_hitvec_hi_2, buf_age_younger[0]) @[lsu_bus_buffer.scala 147:122] + node _T_442 = orr(_T_441) @[lsu_bus_buffer.scala 147:144] + node _T_443 = eq(_T_442, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:99] + node _T_444 = and(_T_440, _T_443) @[lsu_bus_buffer.scala 147:97] + node _T_445 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[lsu_bus_buffer.scala 147:170] + node _T_446 = eq(_T_445, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:150] + node _T_447 = and(_T_444, _T_446) @[lsu_bus_buffer.scala 147:148] + node _T_448 = bits(ld_byte_hitvec_hi_2, 1, 1) @[lsu_bus_buffer.scala 147:93] + node _T_449 = and(ld_byte_hitvec_hi_2, buf_age_younger[1]) @[lsu_bus_buffer.scala 147:122] + node _T_450 = orr(_T_449) @[lsu_bus_buffer.scala 147:144] + node _T_451 = eq(_T_450, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:99] + node _T_452 = and(_T_448, _T_451) @[lsu_bus_buffer.scala 147:97] + node _T_453 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[lsu_bus_buffer.scala 147:170] + node _T_454 = eq(_T_453, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:150] + node _T_455 = and(_T_452, _T_454) @[lsu_bus_buffer.scala 147:148] + node _T_456 = bits(ld_byte_hitvec_hi_2, 2, 2) @[lsu_bus_buffer.scala 147:93] + node _T_457 = and(ld_byte_hitvec_hi_2, buf_age_younger[2]) @[lsu_bus_buffer.scala 147:122] + node _T_458 = orr(_T_457) @[lsu_bus_buffer.scala 147:144] + node _T_459 = eq(_T_458, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:99] + node _T_460 = and(_T_456, _T_459) @[lsu_bus_buffer.scala 147:97] + node _T_461 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[lsu_bus_buffer.scala 147:170] + node _T_462 = eq(_T_461, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:150] + node _T_463 = and(_T_460, _T_462) @[lsu_bus_buffer.scala 147:148] + node _T_464 = bits(ld_byte_hitvec_hi_2, 3, 3) @[lsu_bus_buffer.scala 147:93] + node _T_465 = and(ld_byte_hitvec_hi_2, buf_age_younger[3]) @[lsu_bus_buffer.scala 147:122] + node _T_466 = orr(_T_465) @[lsu_bus_buffer.scala 147:144] + node _T_467 = eq(_T_466, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:99] + node _T_468 = and(_T_464, _T_467) @[lsu_bus_buffer.scala 147:97] + node _T_469 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[lsu_bus_buffer.scala 147:170] + node _T_470 = eq(_T_469, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:150] + node _T_471 = and(_T_468, _T_470) @[lsu_bus_buffer.scala 147:148] node _T_472 = cat(_T_471, _T_463) @[Cat.scala 29:58] node _T_473 = cat(_T_472, _T_455) @[Cat.scala 29:58] node _T_474 = cat(_T_473, _T_447) @[Cat.scala 29:58] - node _T_475 = bits(ld_byte_hitvec_hi_3, 0, 0) @[lsu_bus_buffer.scala 146:93] - node _T_476 = and(ld_byte_hitvec_hi_3, buf_age_younger[0]) @[lsu_bus_buffer.scala 146:122] - node _T_477 = orr(_T_476) @[lsu_bus_buffer.scala 146:144] - node _T_478 = eq(_T_477, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] - node _T_479 = and(_T_475, _T_478) @[lsu_bus_buffer.scala 146:97] - node _T_480 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[lsu_bus_buffer.scala 146:170] - node _T_481 = eq(_T_480, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] - node _T_482 = and(_T_479, _T_481) @[lsu_bus_buffer.scala 146:148] - node _T_483 = bits(ld_byte_hitvec_hi_3, 1, 1) @[lsu_bus_buffer.scala 146:93] - node _T_484 = and(ld_byte_hitvec_hi_3, buf_age_younger[1]) @[lsu_bus_buffer.scala 146:122] - node _T_485 = orr(_T_484) @[lsu_bus_buffer.scala 146:144] - node _T_486 = eq(_T_485, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] - node _T_487 = and(_T_483, _T_486) @[lsu_bus_buffer.scala 146:97] - node _T_488 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[lsu_bus_buffer.scala 146:170] - node _T_489 = eq(_T_488, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] - node _T_490 = and(_T_487, _T_489) @[lsu_bus_buffer.scala 146:148] - node _T_491 = bits(ld_byte_hitvec_hi_3, 2, 2) @[lsu_bus_buffer.scala 146:93] - node _T_492 = and(ld_byte_hitvec_hi_3, buf_age_younger[2]) @[lsu_bus_buffer.scala 146:122] - node _T_493 = orr(_T_492) @[lsu_bus_buffer.scala 146:144] - node _T_494 = eq(_T_493, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] - node _T_495 = and(_T_491, _T_494) @[lsu_bus_buffer.scala 146:97] - node _T_496 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[lsu_bus_buffer.scala 146:170] - node _T_497 = eq(_T_496, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] - node _T_498 = and(_T_495, _T_497) @[lsu_bus_buffer.scala 146:148] - node _T_499 = bits(ld_byte_hitvec_hi_3, 3, 3) @[lsu_bus_buffer.scala 146:93] - node _T_500 = and(ld_byte_hitvec_hi_3, buf_age_younger[3]) @[lsu_bus_buffer.scala 146:122] - node _T_501 = orr(_T_500) @[lsu_bus_buffer.scala 146:144] - node _T_502 = eq(_T_501, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:99] - node _T_503 = and(_T_499, _T_502) @[lsu_bus_buffer.scala 146:97] - node _T_504 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[lsu_bus_buffer.scala 146:170] - node _T_505 = eq(_T_504, UInt<1>("h00")) @[lsu_bus_buffer.scala 146:150] - node _T_506 = and(_T_503, _T_505) @[lsu_bus_buffer.scala 146:148] + node _T_475 = bits(ld_byte_hitvec_hi_3, 0, 0) @[lsu_bus_buffer.scala 147:93] + node _T_476 = and(ld_byte_hitvec_hi_3, buf_age_younger[0]) @[lsu_bus_buffer.scala 147:122] + node _T_477 = orr(_T_476) @[lsu_bus_buffer.scala 147:144] + node _T_478 = eq(_T_477, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:99] + node _T_479 = and(_T_475, _T_478) @[lsu_bus_buffer.scala 147:97] + node _T_480 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[lsu_bus_buffer.scala 147:170] + node _T_481 = eq(_T_480, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:150] + node _T_482 = and(_T_479, _T_481) @[lsu_bus_buffer.scala 147:148] + node _T_483 = bits(ld_byte_hitvec_hi_3, 1, 1) @[lsu_bus_buffer.scala 147:93] + node _T_484 = and(ld_byte_hitvec_hi_3, buf_age_younger[1]) @[lsu_bus_buffer.scala 147:122] + node _T_485 = orr(_T_484) @[lsu_bus_buffer.scala 147:144] + node _T_486 = eq(_T_485, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:99] + node _T_487 = and(_T_483, _T_486) @[lsu_bus_buffer.scala 147:97] + node _T_488 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[lsu_bus_buffer.scala 147:170] + node _T_489 = eq(_T_488, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:150] + node _T_490 = and(_T_487, _T_489) @[lsu_bus_buffer.scala 147:148] + node _T_491 = bits(ld_byte_hitvec_hi_3, 2, 2) @[lsu_bus_buffer.scala 147:93] + node _T_492 = and(ld_byte_hitvec_hi_3, buf_age_younger[2]) @[lsu_bus_buffer.scala 147:122] + node _T_493 = orr(_T_492) @[lsu_bus_buffer.scala 147:144] + node _T_494 = eq(_T_493, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:99] + node _T_495 = and(_T_491, _T_494) @[lsu_bus_buffer.scala 147:97] + node _T_496 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[lsu_bus_buffer.scala 147:170] + node _T_497 = eq(_T_496, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:150] + node _T_498 = and(_T_495, _T_497) @[lsu_bus_buffer.scala 147:148] + node _T_499 = bits(ld_byte_hitvec_hi_3, 3, 3) @[lsu_bus_buffer.scala 147:93] + node _T_500 = and(ld_byte_hitvec_hi_3, buf_age_younger[3]) @[lsu_bus_buffer.scala 147:122] + node _T_501 = orr(_T_500) @[lsu_bus_buffer.scala 147:144] + node _T_502 = eq(_T_501, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:99] + node _T_503 = and(_T_499, _T_502) @[lsu_bus_buffer.scala 147:97] + node _T_504 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[lsu_bus_buffer.scala 147:170] + node _T_505 = eq(_T_504, UInt<1>("h00")) @[lsu_bus_buffer.scala 147:150] + node _T_506 = and(_T_503, _T_505) @[lsu_bus_buffer.scala 147:148] node _T_507 = cat(_T_506, _T_498) @[Cat.scala 29:58] node _T_508 = cat(_T_507, _T_490) @[Cat.scala 29:58] node _T_509 = cat(_T_508, _T_482) @[Cat.scala 29:58] - ld_byte_hitvecfn_hi[0] <= _T_404 @[lsu_bus_buffer.scala 146:23] - ld_byte_hitvecfn_hi[1] <= _T_439 @[lsu_bus_buffer.scala 146:23] - ld_byte_hitvecfn_hi[2] <= _T_474 @[lsu_bus_buffer.scala 146:23] - ld_byte_hitvecfn_hi[3] <= _T_509 @[lsu_bus_buffer.scala 146:23] + ld_byte_hitvecfn_hi[0] <= _T_404 @[lsu_bus_buffer.scala 147:23] + ld_byte_hitvecfn_hi[1] <= _T_439 @[lsu_bus_buffer.scala 147:23] + ld_byte_hitvecfn_hi[2] <= _T_474 @[lsu_bus_buffer.scala 147:23] + ld_byte_hitvecfn_hi[3] <= _T_509 @[lsu_bus_buffer.scala 147:23] wire ibuf_addr : UInt<32> ibuf_addr <= UInt<1>("h00") wire ibuf_write : UInt<1> ibuf_write <= UInt<1>("h00") wire ibuf_valid : UInt<1> ibuf_valid <= UInt<1>("h00") - node _T_510 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 151:43] - node _T_511 = bits(ibuf_addr, 31, 2) @[lsu_bus_buffer.scala 151:64] - node _T_512 = eq(_T_510, _T_511) @[lsu_bus_buffer.scala 151:51] - node _T_513 = and(_T_512, ibuf_write) @[lsu_bus_buffer.scala 151:73] - node _T_514 = and(_T_513, ibuf_valid) @[lsu_bus_buffer.scala 151:86] - node ld_addr_ibuf_hit_lo = and(_T_514, io.lsu_busreq_m) @[lsu_bus_buffer.scala 151:99] - node _T_515 = bits(io.end_addr_m, 31, 2) @[lsu_bus_buffer.scala 152:43] - node _T_516 = bits(ibuf_addr, 31, 2) @[lsu_bus_buffer.scala 152:64] - node _T_517 = eq(_T_515, _T_516) @[lsu_bus_buffer.scala 152:51] - node _T_518 = and(_T_517, ibuf_write) @[lsu_bus_buffer.scala 152:73] - node _T_519 = and(_T_518, ibuf_valid) @[lsu_bus_buffer.scala 152:86] - node ld_addr_ibuf_hit_hi = and(_T_519, io.lsu_busreq_m) @[lsu_bus_buffer.scala 152:99] + node _T_510 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 152:43] + node _T_511 = bits(ibuf_addr, 31, 2) @[lsu_bus_buffer.scala 152:64] + node _T_512 = eq(_T_510, _T_511) @[lsu_bus_buffer.scala 152:51] + node _T_513 = and(_T_512, ibuf_write) @[lsu_bus_buffer.scala 152:73] + node _T_514 = and(_T_513, ibuf_valid) @[lsu_bus_buffer.scala 152:86] + node ld_addr_ibuf_hit_lo = and(_T_514, io.lsu_busreq_m) @[lsu_bus_buffer.scala 152:99] + node _T_515 = bits(io.end_addr_m, 31, 2) @[lsu_bus_buffer.scala 153:43] + node _T_516 = bits(ibuf_addr, 31, 2) @[lsu_bus_buffer.scala 153:64] + node _T_517 = eq(_T_515, _T_516) @[lsu_bus_buffer.scala 153:51] + node _T_518 = and(_T_517, ibuf_write) @[lsu_bus_buffer.scala 153:73] + node _T_519 = and(_T_518, ibuf_valid) @[lsu_bus_buffer.scala 153:86] + node ld_addr_ibuf_hit_hi = and(_T_519, io.lsu_busreq_m) @[lsu_bus_buffer.scala 153:99] wire ibuf_byteen : UInt<4> ibuf_byteen <= UInt<1>("h00") node _T_520 = bits(ld_addr_ibuf_hit_lo, 0, 0) @[Bitwise.scala 72:15] node _T_521 = mux(_T_520, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_522 = and(_T_521, ibuf_byteen) @[lsu_bus_buffer.scala 156:55] - node _T_523 = and(_T_522, ldst_byteen_lo_m) @[lsu_bus_buffer.scala 156:69] - ld_byte_ibuf_hit_lo <= _T_523 @[lsu_bus_buffer.scala 156:23] + node _T_522 = and(_T_521, ibuf_byteen) @[lsu_bus_buffer.scala 157:55] + node _T_523 = and(_T_522, ldst_byteen_lo_m) @[lsu_bus_buffer.scala 157:69] + ld_byte_ibuf_hit_lo <= _T_523 @[lsu_bus_buffer.scala 157:23] node _T_524 = bits(ld_addr_ibuf_hit_hi, 0, 0) @[Bitwise.scala 72:15] node _T_525 = mux(_T_524, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_526 = and(_T_525, ibuf_byteen) @[lsu_bus_buffer.scala 157:55] - node _T_527 = and(_T_526, ldst_byteen_hi_m) @[lsu_bus_buffer.scala 157:69] - ld_byte_ibuf_hit_hi <= _T_527 @[lsu_bus_buffer.scala 157:23] - wire buf_data : UInt<32>[4] @[lsu_bus_buffer.scala 159:22] - buf_data[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 160:12] - buf_data[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 160:12] - buf_data[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 160:12] - buf_data[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 160:12] + node _T_526 = and(_T_525, ibuf_byteen) @[lsu_bus_buffer.scala 158:55] + node _T_527 = and(_T_526, ldst_byteen_hi_m) @[lsu_bus_buffer.scala 158:69] + ld_byte_ibuf_hit_hi <= _T_527 @[lsu_bus_buffer.scala 158:23] + wire buf_data : UInt<32>[4] @[lsu_bus_buffer.scala 160:22] + buf_data[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 161:12] + buf_data[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 161:12] + buf_data[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 161:12] + buf_data[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 161:12] wire fwd_data : UInt<32> fwd_data <= UInt<1>("h00") - node _T_528 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[lsu_bus_buffer.scala 162:81] + node _T_528 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[lsu_bus_buffer.scala 163:81] node _T_529 = bits(_T_528, 0, 0) @[Bitwise.scala 72:15] node _T_530 = mux(_T_529, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_531 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[lsu_bus_buffer.scala 162:81] + node _T_531 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[lsu_bus_buffer.scala 163:81] node _T_532 = bits(_T_531, 0, 0) @[Bitwise.scala 72:15] node _T_533 = mux(_T_532, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_534 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[lsu_bus_buffer.scala 162:81] + node _T_534 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[lsu_bus_buffer.scala 163:81] node _T_535 = bits(_T_534, 0, 0) @[Bitwise.scala 72:15] node _T_536 = mux(_T_535, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_537 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[lsu_bus_buffer.scala 162:81] + node _T_537 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[lsu_bus_buffer.scala 163:81] node _T_538 = bits(_T_537, 0, 0) @[Bitwise.scala 72:15] node _T_539 = mux(_T_538, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] node _T_540 = cat(_T_539, _T_536) @[Cat.scala 29:58] node _T_541 = cat(_T_540, _T_533) @[Cat.scala 29:58] node ld_fwddata_buf_lo_initial = cat(_T_541, _T_530) @[Cat.scala 29:58] - node _T_542 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[lsu_bus_buffer.scala 163:81] + node _T_542 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[lsu_bus_buffer.scala 164:81] node _T_543 = bits(_T_542, 0, 0) @[Bitwise.scala 72:15] node _T_544 = mux(_T_543, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_545 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[lsu_bus_buffer.scala 163:81] + node _T_545 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[lsu_bus_buffer.scala 164:81] node _T_546 = bits(_T_545, 0, 0) @[Bitwise.scala 72:15] node _T_547 = mux(_T_546, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_548 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[lsu_bus_buffer.scala 163:81] + node _T_548 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[lsu_bus_buffer.scala 164:81] node _T_549 = bits(_T_548, 0, 0) @[Bitwise.scala 72:15] node _T_550 = mux(_T_549, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_551 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[lsu_bus_buffer.scala 163:81] + node _T_551 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[lsu_bus_buffer.scala 164:81] node _T_552 = bits(_T_551, 0, 0) @[Bitwise.scala 72:15] node _T_553 = mux(_T_552, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] node _T_554 = cat(_T_553, _T_550) @[Cat.scala 29:58] node _T_555 = cat(_T_554, _T_547) @[Cat.scala 29:58] node ld_fwddata_buf_hi_initial = cat(_T_555, _T_544) @[Cat.scala 29:58] - node _T_556 = bits(ld_byte_hitvecfn_lo[3], 0, 0) @[lsu_bus_buffer.scala 164:86] + node _T_556 = bits(ld_byte_hitvecfn_lo[3], 0, 0) @[lsu_bus_buffer.scala 165:86] node _T_557 = bits(_T_556, 0, 0) @[Bitwise.scala 72:15] node _T_558 = mux(_T_557, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_559 = bits(buf_data[0], 31, 24) @[lsu_bus_buffer.scala 164:104] - node _T_560 = and(_T_558, _T_559) @[lsu_bus_buffer.scala 164:91] - node _T_561 = bits(ld_byte_hitvecfn_lo[3], 1, 1) @[lsu_bus_buffer.scala 164:86] + node _T_559 = bits(buf_data[0], 31, 24) @[lsu_bus_buffer.scala 165:104] + node _T_560 = and(_T_558, _T_559) @[lsu_bus_buffer.scala 165:91] + node _T_561 = bits(ld_byte_hitvecfn_lo[3], 1, 1) @[lsu_bus_buffer.scala 165:86] node _T_562 = bits(_T_561, 0, 0) @[Bitwise.scala 72:15] node _T_563 = mux(_T_562, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_564 = bits(buf_data[1], 31, 24) @[lsu_bus_buffer.scala 164:104] - node _T_565 = and(_T_563, _T_564) @[lsu_bus_buffer.scala 164:91] - node _T_566 = bits(ld_byte_hitvecfn_lo[3], 2, 2) @[lsu_bus_buffer.scala 164:86] + node _T_564 = bits(buf_data[1], 31, 24) @[lsu_bus_buffer.scala 165:104] + node _T_565 = and(_T_563, _T_564) @[lsu_bus_buffer.scala 165:91] + node _T_566 = bits(ld_byte_hitvecfn_lo[3], 2, 2) @[lsu_bus_buffer.scala 165:86] node _T_567 = bits(_T_566, 0, 0) @[Bitwise.scala 72:15] node _T_568 = mux(_T_567, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_569 = bits(buf_data[2], 31, 24) @[lsu_bus_buffer.scala 164:104] - node _T_570 = and(_T_568, _T_569) @[lsu_bus_buffer.scala 164:91] - node _T_571 = bits(ld_byte_hitvecfn_lo[3], 3, 3) @[lsu_bus_buffer.scala 164:86] + node _T_569 = bits(buf_data[2], 31, 24) @[lsu_bus_buffer.scala 165:104] + node _T_570 = and(_T_568, _T_569) @[lsu_bus_buffer.scala 165:91] + node _T_571 = bits(ld_byte_hitvecfn_lo[3], 3, 3) @[lsu_bus_buffer.scala 165:86] node _T_572 = bits(_T_571, 0, 0) @[Bitwise.scala 72:15] node _T_573 = mux(_T_572, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_574 = bits(buf_data[3], 31, 24) @[lsu_bus_buffer.scala 164:104] - node _T_575 = and(_T_573, _T_574) @[lsu_bus_buffer.scala 164:91] - node _T_576 = or(_T_560, _T_565) @[lsu_bus_buffer.scala 164:123] - node _T_577 = or(_T_576, _T_570) @[lsu_bus_buffer.scala 164:123] - node _T_578 = or(_T_577, _T_575) @[lsu_bus_buffer.scala 164:123] - node _T_579 = bits(ld_byte_hitvecfn_lo[2], 0, 0) @[lsu_bus_buffer.scala 165:60] + node _T_574 = bits(buf_data[3], 31, 24) @[lsu_bus_buffer.scala 165:104] + node _T_575 = and(_T_573, _T_574) @[lsu_bus_buffer.scala 165:91] + node _T_576 = or(_T_560, _T_565) @[lsu_bus_buffer.scala 165:123] + node _T_577 = or(_T_576, _T_570) @[lsu_bus_buffer.scala 165:123] + node _T_578 = or(_T_577, _T_575) @[lsu_bus_buffer.scala 165:123] + node _T_579 = bits(ld_byte_hitvecfn_lo[2], 0, 0) @[lsu_bus_buffer.scala 166:60] node _T_580 = bits(_T_579, 0, 0) @[Bitwise.scala 72:15] node _T_581 = mux(_T_580, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_582 = bits(buf_data[0], 23, 16) @[lsu_bus_buffer.scala 165:78] - node _T_583 = and(_T_581, _T_582) @[lsu_bus_buffer.scala 165:65] - node _T_584 = bits(ld_byte_hitvecfn_lo[2], 1, 1) @[lsu_bus_buffer.scala 165:60] + node _T_582 = bits(buf_data[0], 23, 16) @[lsu_bus_buffer.scala 166:78] + node _T_583 = and(_T_581, _T_582) @[lsu_bus_buffer.scala 166:65] + node _T_584 = bits(ld_byte_hitvecfn_lo[2], 1, 1) @[lsu_bus_buffer.scala 166:60] node _T_585 = bits(_T_584, 0, 0) @[Bitwise.scala 72:15] node _T_586 = mux(_T_585, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_587 = bits(buf_data[1], 23, 16) @[lsu_bus_buffer.scala 165:78] - node _T_588 = and(_T_586, _T_587) @[lsu_bus_buffer.scala 165:65] - node _T_589 = bits(ld_byte_hitvecfn_lo[2], 2, 2) @[lsu_bus_buffer.scala 165:60] + node _T_587 = bits(buf_data[1], 23, 16) @[lsu_bus_buffer.scala 166:78] + node _T_588 = and(_T_586, _T_587) @[lsu_bus_buffer.scala 166:65] + node _T_589 = bits(ld_byte_hitvecfn_lo[2], 2, 2) @[lsu_bus_buffer.scala 166:60] node _T_590 = bits(_T_589, 0, 0) @[Bitwise.scala 72:15] node _T_591 = mux(_T_590, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_592 = bits(buf_data[2], 23, 16) @[lsu_bus_buffer.scala 165:78] - node _T_593 = and(_T_591, _T_592) @[lsu_bus_buffer.scala 165:65] - node _T_594 = bits(ld_byte_hitvecfn_lo[2], 3, 3) @[lsu_bus_buffer.scala 165:60] + node _T_592 = bits(buf_data[2], 23, 16) @[lsu_bus_buffer.scala 166:78] + node _T_593 = and(_T_591, _T_592) @[lsu_bus_buffer.scala 166:65] + node _T_594 = bits(ld_byte_hitvecfn_lo[2], 3, 3) @[lsu_bus_buffer.scala 166:60] node _T_595 = bits(_T_594, 0, 0) @[Bitwise.scala 72:15] node _T_596 = mux(_T_595, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_597 = bits(buf_data[3], 23, 16) @[lsu_bus_buffer.scala 165:78] - node _T_598 = and(_T_596, _T_597) @[lsu_bus_buffer.scala 165:65] - node _T_599 = or(_T_583, _T_588) @[lsu_bus_buffer.scala 165:97] - node _T_600 = or(_T_599, _T_593) @[lsu_bus_buffer.scala 165:97] - node _T_601 = or(_T_600, _T_598) @[lsu_bus_buffer.scala 165:97] - node _T_602 = bits(ld_byte_hitvecfn_lo[1], 0, 0) @[lsu_bus_buffer.scala 166:60] + node _T_597 = bits(buf_data[3], 23, 16) @[lsu_bus_buffer.scala 166:78] + node _T_598 = and(_T_596, _T_597) @[lsu_bus_buffer.scala 166:65] + node _T_599 = or(_T_583, _T_588) @[lsu_bus_buffer.scala 166:97] + node _T_600 = or(_T_599, _T_593) @[lsu_bus_buffer.scala 166:97] + node _T_601 = or(_T_600, _T_598) @[lsu_bus_buffer.scala 166:97] + node _T_602 = bits(ld_byte_hitvecfn_lo[1], 0, 0) @[lsu_bus_buffer.scala 167:60] node _T_603 = bits(_T_602, 0, 0) @[Bitwise.scala 72:15] node _T_604 = mux(_T_603, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_605 = bits(buf_data[0], 15, 8) @[lsu_bus_buffer.scala 166:78] - node _T_606 = and(_T_604, _T_605) @[lsu_bus_buffer.scala 166:65] - node _T_607 = bits(ld_byte_hitvecfn_lo[1], 1, 1) @[lsu_bus_buffer.scala 166:60] + node _T_605 = bits(buf_data[0], 15, 8) @[lsu_bus_buffer.scala 167:78] + node _T_606 = and(_T_604, _T_605) @[lsu_bus_buffer.scala 167:65] + node _T_607 = bits(ld_byte_hitvecfn_lo[1], 1, 1) @[lsu_bus_buffer.scala 167:60] node _T_608 = bits(_T_607, 0, 0) @[Bitwise.scala 72:15] node _T_609 = mux(_T_608, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_610 = bits(buf_data[1], 15, 8) @[lsu_bus_buffer.scala 166:78] - node _T_611 = and(_T_609, _T_610) @[lsu_bus_buffer.scala 166:65] - node _T_612 = bits(ld_byte_hitvecfn_lo[1], 2, 2) @[lsu_bus_buffer.scala 166:60] + node _T_610 = bits(buf_data[1], 15, 8) @[lsu_bus_buffer.scala 167:78] + node _T_611 = and(_T_609, _T_610) @[lsu_bus_buffer.scala 167:65] + node _T_612 = bits(ld_byte_hitvecfn_lo[1], 2, 2) @[lsu_bus_buffer.scala 167:60] node _T_613 = bits(_T_612, 0, 0) @[Bitwise.scala 72:15] node _T_614 = mux(_T_613, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_615 = bits(buf_data[2], 15, 8) @[lsu_bus_buffer.scala 166:78] - node _T_616 = and(_T_614, _T_615) @[lsu_bus_buffer.scala 166:65] - node _T_617 = bits(ld_byte_hitvecfn_lo[1], 3, 3) @[lsu_bus_buffer.scala 166:60] + node _T_615 = bits(buf_data[2], 15, 8) @[lsu_bus_buffer.scala 167:78] + node _T_616 = and(_T_614, _T_615) @[lsu_bus_buffer.scala 167:65] + node _T_617 = bits(ld_byte_hitvecfn_lo[1], 3, 3) @[lsu_bus_buffer.scala 167:60] node _T_618 = bits(_T_617, 0, 0) @[Bitwise.scala 72:15] node _T_619 = mux(_T_618, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_620 = bits(buf_data[3], 15, 8) @[lsu_bus_buffer.scala 166:78] - node _T_621 = and(_T_619, _T_620) @[lsu_bus_buffer.scala 166:65] - node _T_622 = or(_T_606, _T_611) @[lsu_bus_buffer.scala 166:97] - node _T_623 = or(_T_622, _T_616) @[lsu_bus_buffer.scala 166:97] - node _T_624 = or(_T_623, _T_621) @[lsu_bus_buffer.scala 166:97] - node _T_625 = bits(ld_byte_hitvecfn_lo[0], 0, 0) @[lsu_bus_buffer.scala 167:60] + node _T_620 = bits(buf_data[3], 15, 8) @[lsu_bus_buffer.scala 167:78] + node _T_621 = and(_T_619, _T_620) @[lsu_bus_buffer.scala 167:65] + node _T_622 = or(_T_606, _T_611) @[lsu_bus_buffer.scala 167:97] + node _T_623 = or(_T_622, _T_616) @[lsu_bus_buffer.scala 167:97] + node _T_624 = or(_T_623, _T_621) @[lsu_bus_buffer.scala 167:97] + node _T_625 = bits(ld_byte_hitvecfn_lo[0], 0, 0) @[lsu_bus_buffer.scala 168:60] node _T_626 = bits(_T_625, 0, 0) @[Bitwise.scala 72:15] node _T_627 = mux(_T_626, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_628 = bits(buf_data[0], 7, 0) @[lsu_bus_buffer.scala 167:78] - node _T_629 = and(_T_627, _T_628) @[lsu_bus_buffer.scala 167:65] - node _T_630 = bits(ld_byte_hitvecfn_lo[0], 1, 1) @[lsu_bus_buffer.scala 167:60] + node _T_628 = bits(buf_data[0], 7, 0) @[lsu_bus_buffer.scala 168:78] + node _T_629 = and(_T_627, _T_628) @[lsu_bus_buffer.scala 168:65] + node _T_630 = bits(ld_byte_hitvecfn_lo[0], 1, 1) @[lsu_bus_buffer.scala 168:60] node _T_631 = bits(_T_630, 0, 0) @[Bitwise.scala 72:15] node _T_632 = mux(_T_631, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_633 = bits(buf_data[1], 7, 0) @[lsu_bus_buffer.scala 167:78] - node _T_634 = and(_T_632, _T_633) @[lsu_bus_buffer.scala 167:65] - node _T_635 = bits(ld_byte_hitvecfn_lo[0], 2, 2) @[lsu_bus_buffer.scala 167:60] + node _T_633 = bits(buf_data[1], 7, 0) @[lsu_bus_buffer.scala 168:78] + node _T_634 = and(_T_632, _T_633) @[lsu_bus_buffer.scala 168:65] + node _T_635 = bits(ld_byte_hitvecfn_lo[0], 2, 2) @[lsu_bus_buffer.scala 168:60] node _T_636 = bits(_T_635, 0, 0) @[Bitwise.scala 72:15] node _T_637 = mux(_T_636, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_638 = bits(buf_data[2], 7, 0) @[lsu_bus_buffer.scala 167:78] - node _T_639 = and(_T_637, _T_638) @[lsu_bus_buffer.scala 167:65] - node _T_640 = bits(ld_byte_hitvecfn_lo[0], 3, 3) @[lsu_bus_buffer.scala 167:60] + node _T_638 = bits(buf_data[2], 7, 0) @[lsu_bus_buffer.scala 168:78] + node _T_639 = and(_T_637, _T_638) @[lsu_bus_buffer.scala 168:65] + node _T_640 = bits(ld_byte_hitvecfn_lo[0], 3, 3) @[lsu_bus_buffer.scala 168:60] node _T_641 = bits(_T_640, 0, 0) @[Bitwise.scala 72:15] node _T_642 = mux(_T_641, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_643 = bits(buf_data[3], 7, 0) @[lsu_bus_buffer.scala 167:78] - node _T_644 = and(_T_642, _T_643) @[lsu_bus_buffer.scala 167:65] - node _T_645 = or(_T_629, _T_634) @[lsu_bus_buffer.scala 167:97] - node _T_646 = or(_T_645, _T_639) @[lsu_bus_buffer.scala 167:97] - node _T_647 = or(_T_646, _T_644) @[lsu_bus_buffer.scala 167:97] + node _T_643 = bits(buf_data[3], 7, 0) @[lsu_bus_buffer.scala 168:78] + node _T_644 = and(_T_642, _T_643) @[lsu_bus_buffer.scala 168:65] + node _T_645 = or(_T_629, _T_634) @[lsu_bus_buffer.scala 168:97] + node _T_646 = or(_T_645, _T_639) @[lsu_bus_buffer.scala 168:97] + node _T_647 = or(_T_646, _T_644) @[lsu_bus_buffer.scala 168:97] node _T_648 = cat(_T_624, _T_647) @[Cat.scala 29:58] node _T_649 = cat(_T_578, _T_601) @[Cat.scala 29:58] node _T_650 = cat(_T_649, _T_648) @[Cat.scala 29:58] - node _T_651 = and(ld_fwddata_buf_lo_initial, ibuf_data) @[lsu_bus_buffer.scala 168:32] - node _T_652 = or(_T_650, _T_651) @[lsu_bus_buffer.scala 167:103] - io.ld_fwddata_buf_lo <= _T_652 @[lsu_bus_buffer.scala 164:24] - node _T_653 = bits(ld_byte_hitvecfn_hi[3], 0, 0) @[lsu_bus_buffer.scala 170:86] + node _T_651 = and(ld_fwddata_buf_lo_initial, ibuf_data) @[lsu_bus_buffer.scala 169:32] + node _T_652 = or(_T_650, _T_651) @[lsu_bus_buffer.scala 168:103] + io.ld_fwddata_buf_lo <= _T_652 @[lsu_bus_buffer.scala 165:24] + node _T_653 = bits(ld_byte_hitvecfn_hi[3], 0, 0) @[lsu_bus_buffer.scala 171:86] node _T_654 = bits(_T_653, 0, 0) @[Bitwise.scala 72:15] node _T_655 = mux(_T_654, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_656 = bits(buf_data[0], 31, 24) @[lsu_bus_buffer.scala 170:104] - node _T_657 = and(_T_655, _T_656) @[lsu_bus_buffer.scala 170:91] - node _T_658 = bits(ld_byte_hitvecfn_hi[3], 1, 1) @[lsu_bus_buffer.scala 170:86] + node _T_656 = bits(buf_data[0], 31, 24) @[lsu_bus_buffer.scala 171:104] + node _T_657 = and(_T_655, _T_656) @[lsu_bus_buffer.scala 171:91] + node _T_658 = bits(ld_byte_hitvecfn_hi[3], 1, 1) @[lsu_bus_buffer.scala 171:86] node _T_659 = bits(_T_658, 0, 0) @[Bitwise.scala 72:15] node _T_660 = mux(_T_659, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_661 = bits(buf_data[1], 31, 24) @[lsu_bus_buffer.scala 170:104] - node _T_662 = and(_T_660, _T_661) @[lsu_bus_buffer.scala 170:91] - node _T_663 = bits(ld_byte_hitvecfn_hi[3], 2, 2) @[lsu_bus_buffer.scala 170:86] + node _T_661 = bits(buf_data[1], 31, 24) @[lsu_bus_buffer.scala 171:104] + node _T_662 = and(_T_660, _T_661) @[lsu_bus_buffer.scala 171:91] + node _T_663 = bits(ld_byte_hitvecfn_hi[3], 2, 2) @[lsu_bus_buffer.scala 171:86] node _T_664 = bits(_T_663, 0, 0) @[Bitwise.scala 72:15] node _T_665 = mux(_T_664, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_666 = bits(buf_data[2], 31, 24) @[lsu_bus_buffer.scala 170:104] - node _T_667 = and(_T_665, _T_666) @[lsu_bus_buffer.scala 170:91] - node _T_668 = bits(ld_byte_hitvecfn_hi[3], 3, 3) @[lsu_bus_buffer.scala 170:86] + node _T_666 = bits(buf_data[2], 31, 24) @[lsu_bus_buffer.scala 171:104] + node _T_667 = and(_T_665, _T_666) @[lsu_bus_buffer.scala 171:91] + node _T_668 = bits(ld_byte_hitvecfn_hi[3], 3, 3) @[lsu_bus_buffer.scala 171:86] node _T_669 = bits(_T_668, 0, 0) @[Bitwise.scala 72:15] node _T_670 = mux(_T_669, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_671 = bits(buf_data[3], 31, 24) @[lsu_bus_buffer.scala 170:104] - node _T_672 = and(_T_670, _T_671) @[lsu_bus_buffer.scala 170:91] - node _T_673 = or(_T_657, _T_662) @[lsu_bus_buffer.scala 170:123] - node _T_674 = or(_T_673, _T_667) @[lsu_bus_buffer.scala 170:123] - node _T_675 = or(_T_674, _T_672) @[lsu_bus_buffer.scala 170:123] - node _T_676 = bits(ld_byte_hitvecfn_hi[2], 0, 0) @[lsu_bus_buffer.scala 171:60] + node _T_671 = bits(buf_data[3], 31, 24) @[lsu_bus_buffer.scala 171:104] + node _T_672 = and(_T_670, _T_671) @[lsu_bus_buffer.scala 171:91] + node _T_673 = or(_T_657, _T_662) @[lsu_bus_buffer.scala 171:123] + node _T_674 = or(_T_673, _T_667) @[lsu_bus_buffer.scala 171:123] + node _T_675 = or(_T_674, _T_672) @[lsu_bus_buffer.scala 171:123] + node _T_676 = bits(ld_byte_hitvecfn_hi[2], 0, 0) @[lsu_bus_buffer.scala 172:60] node _T_677 = bits(_T_676, 0, 0) @[Bitwise.scala 72:15] node _T_678 = mux(_T_677, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_679 = bits(buf_data[0], 23, 16) @[lsu_bus_buffer.scala 171:78] - node _T_680 = and(_T_678, _T_679) @[lsu_bus_buffer.scala 171:65] - node _T_681 = bits(ld_byte_hitvecfn_hi[2], 1, 1) @[lsu_bus_buffer.scala 171:60] + node _T_679 = bits(buf_data[0], 23, 16) @[lsu_bus_buffer.scala 172:78] + node _T_680 = and(_T_678, _T_679) @[lsu_bus_buffer.scala 172:65] + node _T_681 = bits(ld_byte_hitvecfn_hi[2], 1, 1) @[lsu_bus_buffer.scala 172:60] node _T_682 = bits(_T_681, 0, 0) @[Bitwise.scala 72:15] node _T_683 = mux(_T_682, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_684 = bits(buf_data[1], 23, 16) @[lsu_bus_buffer.scala 171:78] - node _T_685 = and(_T_683, _T_684) @[lsu_bus_buffer.scala 171:65] - node _T_686 = bits(ld_byte_hitvecfn_hi[2], 2, 2) @[lsu_bus_buffer.scala 171:60] + node _T_684 = bits(buf_data[1], 23, 16) @[lsu_bus_buffer.scala 172:78] + node _T_685 = and(_T_683, _T_684) @[lsu_bus_buffer.scala 172:65] + node _T_686 = bits(ld_byte_hitvecfn_hi[2], 2, 2) @[lsu_bus_buffer.scala 172:60] node _T_687 = bits(_T_686, 0, 0) @[Bitwise.scala 72:15] node _T_688 = mux(_T_687, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_689 = bits(buf_data[2], 23, 16) @[lsu_bus_buffer.scala 171:78] - node _T_690 = and(_T_688, _T_689) @[lsu_bus_buffer.scala 171:65] - node _T_691 = bits(ld_byte_hitvecfn_hi[2], 3, 3) @[lsu_bus_buffer.scala 171:60] + node _T_689 = bits(buf_data[2], 23, 16) @[lsu_bus_buffer.scala 172:78] + node _T_690 = and(_T_688, _T_689) @[lsu_bus_buffer.scala 172:65] + node _T_691 = bits(ld_byte_hitvecfn_hi[2], 3, 3) @[lsu_bus_buffer.scala 172:60] node _T_692 = bits(_T_691, 0, 0) @[Bitwise.scala 72:15] node _T_693 = mux(_T_692, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_694 = bits(buf_data[3], 23, 16) @[lsu_bus_buffer.scala 171:78] - node _T_695 = and(_T_693, _T_694) @[lsu_bus_buffer.scala 171:65] - node _T_696 = or(_T_680, _T_685) @[lsu_bus_buffer.scala 171:97] - node _T_697 = or(_T_696, _T_690) @[lsu_bus_buffer.scala 171:97] - node _T_698 = or(_T_697, _T_695) @[lsu_bus_buffer.scala 171:97] - node _T_699 = bits(ld_byte_hitvecfn_hi[1], 0, 0) @[lsu_bus_buffer.scala 172:60] + node _T_694 = bits(buf_data[3], 23, 16) @[lsu_bus_buffer.scala 172:78] + node _T_695 = and(_T_693, _T_694) @[lsu_bus_buffer.scala 172:65] + node _T_696 = or(_T_680, _T_685) @[lsu_bus_buffer.scala 172:97] + node _T_697 = or(_T_696, _T_690) @[lsu_bus_buffer.scala 172:97] + node _T_698 = or(_T_697, _T_695) @[lsu_bus_buffer.scala 172:97] + node _T_699 = bits(ld_byte_hitvecfn_hi[1], 0, 0) @[lsu_bus_buffer.scala 173:60] node _T_700 = bits(_T_699, 0, 0) @[Bitwise.scala 72:15] node _T_701 = mux(_T_700, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_702 = bits(buf_data[0], 15, 8) @[lsu_bus_buffer.scala 172:78] - node _T_703 = and(_T_701, _T_702) @[lsu_bus_buffer.scala 172:65] - node _T_704 = bits(ld_byte_hitvecfn_hi[1], 1, 1) @[lsu_bus_buffer.scala 172:60] + node _T_702 = bits(buf_data[0], 15, 8) @[lsu_bus_buffer.scala 173:78] + node _T_703 = and(_T_701, _T_702) @[lsu_bus_buffer.scala 173:65] + node _T_704 = bits(ld_byte_hitvecfn_hi[1], 1, 1) @[lsu_bus_buffer.scala 173:60] node _T_705 = bits(_T_704, 0, 0) @[Bitwise.scala 72:15] node _T_706 = mux(_T_705, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_707 = bits(buf_data[1], 15, 8) @[lsu_bus_buffer.scala 172:78] - node _T_708 = and(_T_706, _T_707) @[lsu_bus_buffer.scala 172:65] - node _T_709 = bits(ld_byte_hitvecfn_hi[1], 2, 2) @[lsu_bus_buffer.scala 172:60] + node _T_707 = bits(buf_data[1], 15, 8) @[lsu_bus_buffer.scala 173:78] + node _T_708 = and(_T_706, _T_707) @[lsu_bus_buffer.scala 173:65] + node _T_709 = bits(ld_byte_hitvecfn_hi[1], 2, 2) @[lsu_bus_buffer.scala 173:60] node _T_710 = bits(_T_709, 0, 0) @[Bitwise.scala 72:15] node _T_711 = mux(_T_710, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_712 = bits(buf_data[2], 15, 8) @[lsu_bus_buffer.scala 172:78] - node _T_713 = and(_T_711, _T_712) @[lsu_bus_buffer.scala 172:65] - node _T_714 = bits(ld_byte_hitvecfn_hi[1], 3, 3) @[lsu_bus_buffer.scala 172:60] + node _T_712 = bits(buf_data[2], 15, 8) @[lsu_bus_buffer.scala 173:78] + node _T_713 = and(_T_711, _T_712) @[lsu_bus_buffer.scala 173:65] + node _T_714 = bits(ld_byte_hitvecfn_hi[1], 3, 3) @[lsu_bus_buffer.scala 173:60] node _T_715 = bits(_T_714, 0, 0) @[Bitwise.scala 72:15] node _T_716 = mux(_T_715, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_717 = bits(buf_data[3], 15, 8) @[lsu_bus_buffer.scala 172:78] - node _T_718 = and(_T_716, _T_717) @[lsu_bus_buffer.scala 172:65] - node _T_719 = or(_T_703, _T_708) @[lsu_bus_buffer.scala 172:97] - node _T_720 = or(_T_719, _T_713) @[lsu_bus_buffer.scala 172:97] - node _T_721 = or(_T_720, _T_718) @[lsu_bus_buffer.scala 172:97] - node _T_722 = bits(ld_byte_hitvecfn_hi[0], 0, 0) @[lsu_bus_buffer.scala 173:60] + node _T_717 = bits(buf_data[3], 15, 8) @[lsu_bus_buffer.scala 173:78] + node _T_718 = and(_T_716, _T_717) @[lsu_bus_buffer.scala 173:65] + node _T_719 = or(_T_703, _T_708) @[lsu_bus_buffer.scala 173:97] + node _T_720 = or(_T_719, _T_713) @[lsu_bus_buffer.scala 173:97] + node _T_721 = or(_T_720, _T_718) @[lsu_bus_buffer.scala 173:97] + node _T_722 = bits(ld_byte_hitvecfn_hi[0], 0, 0) @[lsu_bus_buffer.scala 174:60] node _T_723 = bits(_T_722, 0, 0) @[Bitwise.scala 72:15] node _T_724 = mux(_T_723, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_725 = bits(buf_data[0], 7, 0) @[lsu_bus_buffer.scala 173:78] - node _T_726 = and(_T_724, _T_725) @[lsu_bus_buffer.scala 173:65] - node _T_727 = bits(ld_byte_hitvecfn_hi[0], 1, 1) @[lsu_bus_buffer.scala 173:60] + node _T_725 = bits(buf_data[0], 7, 0) @[lsu_bus_buffer.scala 174:78] + node _T_726 = and(_T_724, _T_725) @[lsu_bus_buffer.scala 174:65] + node _T_727 = bits(ld_byte_hitvecfn_hi[0], 1, 1) @[lsu_bus_buffer.scala 174:60] node _T_728 = bits(_T_727, 0, 0) @[Bitwise.scala 72:15] node _T_729 = mux(_T_728, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_730 = bits(buf_data[1], 7, 0) @[lsu_bus_buffer.scala 173:78] - node _T_731 = and(_T_729, _T_730) @[lsu_bus_buffer.scala 173:65] - node _T_732 = bits(ld_byte_hitvecfn_hi[0], 2, 2) @[lsu_bus_buffer.scala 173:60] + node _T_730 = bits(buf_data[1], 7, 0) @[lsu_bus_buffer.scala 174:78] + node _T_731 = and(_T_729, _T_730) @[lsu_bus_buffer.scala 174:65] + node _T_732 = bits(ld_byte_hitvecfn_hi[0], 2, 2) @[lsu_bus_buffer.scala 174:60] node _T_733 = bits(_T_732, 0, 0) @[Bitwise.scala 72:15] node _T_734 = mux(_T_733, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_735 = bits(buf_data[2], 7, 0) @[lsu_bus_buffer.scala 173:78] - node _T_736 = and(_T_734, _T_735) @[lsu_bus_buffer.scala 173:65] - node _T_737 = bits(ld_byte_hitvecfn_hi[0], 3, 3) @[lsu_bus_buffer.scala 173:60] + node _T_735 = bits(buf_data[2], 7, 0) @[lsu_bus_buffer.scala 174:78] + node _T_736 = and(_T_734, _T_735) @[lsu_bus_buffer.scala 174:65] + node _T_737 = bits(ld_byte_hitvecfn_hi[0], 3, 3) @[lsu_bus_buffer.scala 174:60] node _T_738 = bits(_T_737, 0, 0) @[Bitwise.scala 72:15] node _T_739 = mux(_T_738, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_740 = bits(buf_data[3], 7, 0) @[lsu_bus_buffer.scala 173:78] - node _T_741 = and(_T_739, _T_740) @[lsu_bus_buffer.scala 173:65] - node _T_742 = or(_T_726, _T_731) @[lsu_bus_buffer.scala 173:97] - node _T_743 = or(_T_742, _T_736) @[lsu_bus_buffer.scala 173:97] - node _T_744 = or(_T_743, _T_741) @[lsu_bus_buffer.scala 173:97] + node _T_740 = bits(buf_data[3], 7, 0) @[lsu_bus_buffer.scala 174:78] + node _T_741 = and(_T_739, _T_740) @[lsu_bus_buffer.scala 174:65] + node _T_742 = or(_T_726, _T_731) @[lsu_bus_buffer.scala 174:97] + node _T_743 = or(_T_742, _T_736) @[lsu_bus_buffer.scala 174:97] + node _T_744 = or(_T_743, _T_741) @[lsu_bus_buffer.scala 174:97] node _T_745 = cat(_T_721, _T_744) @[Cat.scala 29:58] node _T_746 = cat(_T_675, _T_698) @[Cat.scala 29:58] node _T_747 = cat(_T_746, _T_745) @[Cat.scala 29:58] - node _T_748 = and(ld_fwddata_buf_hi_initial, ibuf_data) @[lsu_bus_buffer.scala 174:32] - node _T_749 = or(_T_747, _T_748) @[lsu_bus_buffer.scala 173:103] - io.ld_fwddata_buf_hi <= _T_749 @[lsu_bus_buffer.scala 170:24] - node bus_coalescing_disable = or(io.tlu_busbuff.dec_tlu_wb_coalescing_disable, UInt<1>("h01")) @[lsu_bus_buffer.scala 176:77] + node _T_748 = and(ld_fwddata_buf_hi_initial, ibuf_data) @[lsu_bus_buffer.scala 175:32] + node _T_749 = or(_T_747, _T_748) @[lsu_bus_buffer.scala 174:103] + io.ld_fwddata_buf_hi <= _T_749 @[lsu_bus_buffer.scala 171:24] + node bus_coalescing_disable = or(io.tlu_busbuff.dec_tlu_wb_coalescing_disable, UInt<1>("h00")) @[lsu_bus_buffer.scala 177:77] node _T_750 = mux(io.lsu_pkt_r.bits.by, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_751 = mux(io.lsu_pkt_r.bits.half, UInt<4>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_752 = mux(io.lsu_pkt_r.bits.word, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72] @@ -95898,19 +95905,19 @@ circuit quasar_wrapper : node _T_754 = or(_T_753, _T_752) @[Mux.scala 27:72] wire ldst_byteen_r : UInt<4> @[Mux.scala 27:72] ldst_byteen_r <= _T_754 @[Mux.scala 27:72] - node _T_755 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 181:50] - node _T_756 = eq(_T_755, UInt<1>("h00")) @[lsu_bus_buffer.scala 181:55] - node _T_757 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 182:19] - node _T_758 = eq(_T_757, UInt<1>("h01")) @[lsu_bus_buffer.scala 182:24] - node _T_759 = bits(ldst_byteen_r, 3, 3) @[lsu_bus_buffer.scala 182:60] + node _T_755 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 182:50] + node _T_756 = eq(_T_755, UInt<1>("h00")) @[lsu_bus_buffer.scala 182:55] + node _T_757 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 183:19] + node _T_758 = eq(_T_757, UInt<1>("h01")) @[lsu_bus_buffer.scala 183:24] + node _T_759 = bits(ldst_byteen_r, 3, 3) @[lsu_bus_buffer.scala 183:60] node _T_760 = cat(UInt<3>("h00"), _T_759) @[Cat.scala 29:58] - node _T_761 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 183:19] - node _T_762 = eq(_T_761, UInt<2>("h02")) @[lsu_bus_buffer.scala 183:24] - node _T_763 = bits(ldst_byteen_r, 3, 2) @[lsu_bus_buffer.scala 183:60] + node _T_761 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 184:19] + node _T_762 = eq(_T_761, UInt<2>("h02")) @[lsu_bus_buffer.scala 184:24] + node _T_763 = bits(ldst_byteen_r, 3, 2) @[lsu_bus_buffer.scala 184:60] node _T_764 = cat(UInt<2>("h00"), _T_763) @[Cat.scala 29:58] - node _T_765 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 184:19] - node _T_766 = eq(_T_765, UInt<2>("h03")) @[lsu_bus_buffer.scala 184:24] - node _T_767 = bits(ldst_byteen_r, 3, 1) @[lsu_bus_buffer.scala 184:60] + node _T_765 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 185:19] + node _T_766 = eq(_T_765, UInt<2>("h03")) @[lsu_bus_buffer.scala 185:24] + node _T_767 = bits(ldst_byteen_r, 3, 1) @[lsu_bus_buffer.scala 185:60] node _T_768 = cat(UInt<1>("h00"), _T_767) @[Cat.scala 29:58] node _T_769 = mux(_T_756, UInt<4>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_770 = mux(_T_758, _T_760, UInt<1>("h00")) @[Mux.scala 27:72] @@ -95921,19 +95928,19 @@ circuit quasar_wrapper : node _T_775 = or(_T_774, _T_772) @[Mux.scala 27:72] wire ldst_byteen_hi_r : UInt<4> @[Mux.scala 27:72] ldst_byteen_hi_r <= _T_775 @[Mux.scala 27:72] - node _T_776 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 185:50] - node _T_777 = eq(_T_776, UInt<1>("h00")) @[lsu_bus_buffer.scala 185:55] - node _T_778 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 186:19] - node _T_779 = eq(_T_778, UInt<1>("h01")) @[lsu_bus_buffer.scala 186:24] - node _T_780 = bits(ldst_byteen_r, 2, 0) @[lsu_bus_buffer.scala 186:50] + node _T_776 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 186:50] + node _T_777 = eq(_T_776, UInt<1>("h00")) @[lsu_bus_buffer.scala 186:55] + node _T_778 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 187:19] + node _T_779 = eq(_T_778, UInt<1>("h01")) @[lsu_bus_buffer.scala 187:24] + node _T_780 = bits(ldst_byteen_r, 2, 0) @[lsu_bus_buffer.scala 187:50] node _T_781 = cat(_T_780, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_782 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 187:19] - node _T_783 = eq(_T_782, UInt<2>("h02")) @[lsu_bus_buffer.scala 187:24] - node _T_784 = bits(ldst_byteen_r, 1, 0) @[lsu_bus_buffer.scala 187:50] + node _T_782 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 188:19] + node _T_783 = eq(_T_782, UInt<2>("h02")) @[lsu_bus_buffer.scala 188:24] + node _T_784 = bits(ldst_byteen_r, 1, 0) @[lsu_bus_buffer.scala 188:50] node _T_785 = cat(_T_784, UInt<2>("h00")) @[Cat.scala 29:58] - node _T_786 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 188:19] - node _T_787 = eq(_T_786, UInt<2>("h03")) @[lsu_bus_buffer.scala 188:24] - node _T_788 = bits(ldst_byteen_r, 0, 0) @[lsu_bus_buffer.scala 188:50] + node _T_786 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 189:19] + node _T_787 = eq(_T_786, UInt<2>("h03")) @[lsu_bus_buffer.scala 189:24] + node _T_788 = bits(ldst_byteen_r, 0, 0) @[lsu_bus_buffer.scala 189:50] node _T_789 = cat(_T_788, UInt<3>("h00")) @[Cat.scala 29:58] node _T_790 = mux(_T_777, ldst_byteen_r, UInt<1>("h00")) @[Mux.scala 27:72] node _T_791 = mux(_T_779, _T_781, UInt<1>("h00")) @[Mux.scala 27:72] @@ -95944,19 +95951,19 @@ circuit quasar_wrapper : node _T_796 = or(_T_795, _T_793) @[Mux.scala 27:72] wire ldst_byteen_lo_r : UInt<4> @[Mux.scala 27:72] ldst_byteen_lo_r <= _T_796 @[Mux.scala 27:72] - node _T_797 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 190:49] - node _T_798 = eq(_T_797, UInt<1>("h00")) @[lsu_bus_buffer.scala 190:54] - node _T_799 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 191:19] - node _T_800 = eq(_T_799, UInt<1>("h01")) @[lsu_bus_buffer.scala 191:24] - node _T_801 = bits(io.store_data_r, 31, 24) @[lsu_bus_buffer.scala 191:64] + node _T_797 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 191:49] + node _T_798 = eq(_T_797, UInt<1>("h00")) @[lsu_bus_buffer.scala 191:54] + node _T_799 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 192:19] + node _T_800 = eq(_T_799, UInt<1>("h01")) @[lsu_bus_buffer.scala 192:24] + node _T_801 = bits(io.store_data_r, 31, 24) @[lsu_bus_buffer.scala 192:64] node _T_802 = cat(UInt<24>("h00"), _T_801) @[Cat.scala 29:58] - node _T_803 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 192:19] - node _T_804 = eq(_T_803, UInt<2>("h02")) @[lsu_bus_buffer.scala 192:24] - node _T_805 = bits(io.store_data_r, 31, 16) @[lsu_bus_buffer.scala 192:63] + node _T_803 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 193:19] + node _T_804 = eq(_T_803, UInt<2>("h02")) @[lsu_bus_buffer.scala 193:24] + node _T_805 = bits(io.store_data_r, 31, 16) @[lsu_bus_buffer.scala 193:63] node _T_806 = cat(UInt<16>("h00"), _T_805) @[Cat.scala 29:58] - node _T_807 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 193:19] - node _T_808 = eq(_T_807, UInt<2>("h03")) @[lsu_bus_buffer.scala 193:24] - node _T_809 = bits(io.store_data_r, 31, 8) @[lsu_bus_buffer.scala 193:62] + node _T_807 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 194:19] + node _T_808 = eq(_T_807, UInt<2>("h03")) @[lsu_bus_buffer.scala 194:24] + node _T_809 = bits(io.store_data_r, 31, 8) @[lsu_bus_buffer.scala 194:62] node _T_810 = cat(UInt<8>("h00"), _T_809) @[Cat.scala 29:58] node _T_811 = mux(_T_798, UInt<32>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_812 = mux(_T_800, _T_802, UInt<1>("h00")) @[Mux.scala 27:72] @@ -95967,19 +95974,19 @@ circuit quasar_wrapper : node _T_817 = or(_T_816, _T_814) @[Mux.scala 27:72] wire store_data_hi_r : UInt<32> @[Mux.scala 27:72] store_data_hi_r <= _T_817 @[Mux.scala 27:72] - node _T_818 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 195:49] - node _T_819 = eq(_T_818, UInt<1>("h00")) @[lsu_bus_buffer.scala 195:54] - node _T_820 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 196:19] - node _T_821 = eq(_T_820, UInt<1>("h01")) @[lsu_bus_buffer.scala 196:24] - node _T_822 = bits(io.store_data_r, 23, 0) @[lsu_bus_buffer.scala 196:52] + node _T_818 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 196:49] + node _T_819 = eq(_T_818, UInt<1>("h00")) @[lsu_bus_buffer.scala 196:54] + node _T_820 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 197:19] + node _T_821 = eq(_T_820, UInt<1>("h01")) @[lsu_bus_buffer.scala 197:24] + node _T_822 = bits(io.store_data_r, 23, 0) @[lsu_bus_buffer.scala 197:52] node _T_823 = cat(_T_822, UInt<8>("h00")) @[Cat.scala 29:58] - node _T_824 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 197:19] - node _T_825 = eq(_T_824, UInt<2>("h02")) @[lsu_bus_buffer.scala 197:24] - node _T_826 = bits(io.store_data_r, 15, 0) @[lsu_bus_buffer.scala 197:52] + node _T_824 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 198:19] + node _T_825 = eq(_T_824, UInt<2>("h02")) @[lsu_bus_buffer.scala 198:24] + node _T_826 = bits(io.store_data_r, 15, 0) @[lsu_bus_buffer.scala 198:52] node _T_827 = cat(_T_826, UInt<16>("h00")) @[Cat.scala 29:58] - node _T_828 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 198:19] - node _T_829 = eq(_T_828, UInt<2>("h03")) @[lsu_bus_buffer.scala 198:24] - node _T_830 = bits(io.store_data_r, 7, 0) @[lsu_bus_buffer.scala 198:52] + node _T_828 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 199:19] + node _T_829 = eq(_T_828, UInt<2>("h03")) @[lsu_bus_buffer.scala 199:24] + node _T_830 = bits(io.store_data_r, 7, 0) @[lsu_bus_buffer.scala 199:52] node _T_831 = cat(_T_830, UInt<24>("h00")) @[Cat.scala 29:58] node _T_832 = mux(_T_819, io.store_data_r, UInt<1>("h00")) @[Mux.scala 27:72] node _T_833 = mux(_T_821, _T_823, UInt<1>("h00")) @[Mux.scala 27:72] @@ -95990,13 +95997,13 @@ circuit quasar_wrapper : node _T_838 = or(_T_837, _T_835) @[Mux.scala 27:72] wire store_data_lo_r : UInt<32> @[Mux.scala 27:72] store_data_lo_r <= _T_838 @[Mux.scala 27:72] - node _T_839 = bits(io.lsu_addr_r, 3, 3) @[lsu_bus_buffer.scala 201:36] - node _T_840 = bits(io.end_addr_r, 3, 3) @[lsu_bus_buffer.scala 201:57] - node ldst_samedw_r = eq(_T_839, _T_840) @[lsu_bus_buffer.scala 201:40] - node _T_841 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 202:72] - node _T_842 = eq(_T_841, UInt<1>("h00")) @[lsu_bus_buffer.scala 202:79] - node _T_843 = bits(io.lsu_addr_r, 0, 0) @[lsu_bus_buffer.scala 203:45] - node _T_844 = eq(_T_843, UInt<1>("h00")) @[lsu_bus_buffer.scala 203:31] + node _T_839 = bits(io.lsu_addr_r, 3, 3) @[lsu_bus_buffer.scala 202:36] + node _T_840 = bits(io.end_addr_r, 3, 3) @[lsu_bus_buffer.scala 202:57] + node ldst_samedw_r = eq(_T_839, _T_840) @[lsu_bus_buffer.scala 202:40] + node _T_841 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_buffer.scala 203:72] + node _T_842 = eq(_T_841, UInt<1>("h00")) @[lsu_bus_buffer.scala 203:79] + node _T_843 = bits(io.lsu_addr_r, 0, 0) @[lsu_bus_buffer.scala 204:45] + node _T_844 = eq(_T_843, UInt<1>("h00")) @[lsu_bus_buffer.scala 204:31] node _T_845 = mux(io.lsu_pkt_r.bits.word, _T_842, UInt<1>("h00")) @[Mux.scala 27:72] node _T_846 = mux(io.lsu_pkt_r.bits.half, _T_844, UInt<1>("h00")) @[Mux.scala 27:72] node _T_847 = mux(io.lsu_pkt_r.bits.by, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] @@ -96004,26 +96011,26 @@ circuit quasar_wrapper : node _T_849 = or(_T_848, _T_847) @[Mux.scala 27:72] wire is_aligned_r : UInt<1> @[Mux.scala 27:72] is_aligned_r <= _T_849 @[Mux.scala 27:72] - node _T_850 = or(io.lsu_pkt_r.bits.load, io.no_word_merge_r) @[lsu_bus_buffer.scala 205:60] - node _T_851 = and(io.lsu_busreq_r, _T_850) @[lsu_bus_buffer.scala 205:34] - node _T_852 = eq(ibuf_valid, UInt<1>("h00")) @[lsu_bus_buffer.scala 205:84] - node ibuf_byp = and(_T_851, _T_852) @[lsu_bus_buffer.scala 205:82] - node _T_853 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 206:36] - node _T_854 = eq(ibuf_byp, UInt<1>("h00")) @[lsu_bus_buffer.scala 206:56] - node ibuf_wr_en = and(_T_853, _T_854) @[lsu_bus_buffer.scala 206:54] + node _T_850 = or(io.lsu_pkt_r.bits.load, io.no_word_merge_r) @[lsu_bus_buffer.scala 206:60] + node _T_851 = and(io.lsu_busreq_r, _T_850) @[lsu_bus_buffer.scala 206:34] + node _T_852 = eq(ibuf_valid, UInt<1>("h00")) @[lsu_bus_buffer.scala 206:84] + node ibuf_byp = and(_T_851, _T_852) @[lsu_bus_buffer.scala 206:82] + node _T_853 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 207:36] + node _T_854 = eq(ibuf_byp, UInt<1>("h00")) @[lsu_bus_buffer.scala 207:56] + node ibuf_wr_en = and(_T_853, _T_854) @[lsu_bus_buffer.scala 207:54] wire ibuf_drain_vld : UInt<1> ibuf_drain_vld <= UInt<1>("h00") - node _T_855 = eq(ibuf_wr_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 208:36] - node _T_856 = and(ibuf_drain_vld, _T_855) @[lsu_bus_buffer.scala 208:34] - node ibuf_rst = or(_T_856, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 208:49] - node _T_857 = eq(io.lsu_busreq_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 209:44] - node _T_858 = and(io.lsu_busreq_m, _T_857) @[lsu_bus_buffer.scala 209:42] - node _T_859 = and(_T_858, ibuf_valid) @[lsu_bus_buffer.scala 209:61] - node _T_860 = bits(ibuf_addr, 31, 2) @[lsu_bus_buffer.scala 209:112] - node _T_861 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 209:137] - node _T_862 = neq(_T_860, _T_861) @[lsu_bus_buffer.scala 209:120] - node _T_863 = or(io.lsu_pkt_m.bits.load, _T_862) @[lsu_bus_buffer.scala 209:100] - node ibuf_force_drain = and(_T_859, _T_863) @[lsu_bus_buffer.scala 209:74] + node _T_855 = eq(ibuf_wr_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 209:36] + node _T_856 = and(ibuf_drain_vld, _T_855) @[lsu_bus_buffer.scala 209:34] + node ibuf_rst = or(_T_856, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 209:49] + node _T_857 = eq(io.lsu_busreq_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 210:44] + node _T_858 = and(io.lsu_busreq_m, _T_857) @[lsu_bus_buffer.scala 210:42] + node _T_859 = and(_T_858, ibuf_valid) @[lsu_bus_buffer.scala 210:61] + node _T_860 = bits(ibuf_addr, 31, 2) @[lsu_bus_buffer.scala 210:112] + node _T_861 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 210:137] + node _T_862 = neq(_T_860, _T_861) @[lsu_bus_buffer.scala 210:120] + node _T_863 = or(io.lsu_pkt_m.bits.load, _T_862) @[lsu_bus_buffer.scala 210:100] + node ibuf_force_drain = and(_T_859, _T_863) @[lsu_bus_buffer.scala 210:74] wire ibuf_sideeffect : UInt<1> ibuf_sideeffect <= UInt<1>("h00") wire ibuf_timer : UInt<3> @@ -96032,175 +96039,175 @@ circuit quasar_wrapper : ibuf_merge_en <= UInt<1>("h00") wire ibuf_merge_in : UInt<1> ibuf_merge_in <= UInt<1>("h00") - node _T_864 = eq(ibuf_timer, UInt<3>("h07")) @[lsu_bus_buffer.scala 214:62] - node _T_865 = or(ibuf_wr_en, _T_864) @[lsu_bus_buffer.scala 214:48] - node _T_866 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 214:98] - node _T_867 = eq(_T_866, UInt<1>("h00")) @[lsu_bus_buffer.scala 214:82] - node _T_868 = and(_T_865, _T_867) @[lsu_bus_buffer.scala 214:80] - node _T_869 = or(_T_868, ibuf_byp) @[lsu_bus_buffer.scala 215:5] - node _T_870 = or(_T_869, ibuf_force_drain) @[lsu_bus_buffer.scala 215:16] - node _T_871 = or(_T_870, ibuf_sideeffect) @[lsu_bus_buffer.scala 215:35] - node _T_872 = eq(ibuf_write, UInt<1>("h00")) @[lsu_bus_buffer.scala 215:55] - node _T_873 = or(_T_871, _T_872) @[lsu_bus_buffer.scala 215:53] - node _T_874 = or(_T_873, bus_coalescing_disable) @[lsu_bus_buffer.scala 215:67] - node _T_875 = and(ibuf_valid, _T_874) @[lsu_bus_buffer.scala 214:32] - ibuf_drain_vld <= _T_875 @[lsu_bus_buffer.scala 214:18] + node _T_864 = eq(ibuf_timer, UInt<3>("h07")) @[lsu_bus_buffer.scala 215:62] + node _T_865 = or(ibuf_wr_en, _T_864) @[lsu_bus_buffer.scala 215:48] + node _T_866 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 215:98] + node _T_867 = eq(_T_866, UInt<1>("h00")) @[lsu_bus_buffer.scala 215:82] + node _T_868 = and(_T_865, _T_867) @[lsu_bus_buffer.scala 215:80] + node _T_869 = or(_T_868, ibuf_byp) @[lsu_bus_buffer.scala 216:5] + node _T_870 = or(_T_869, ibuf_force_drain) @[lsu_bus_buffer.scala 216:16] + node _T_871 = or(_T_870, ibuf_sideeffect) @[lsu_bus_buffer.scala 216:35] + node _T_872 = eq(ibuf_write, UInt<1>("h00")) @[lsu_bus_buffer.scala 216:55] + node _T_873 = or(_T_871, _T_872) @[lsu_bus_buffer.scala 216:53] + node _T_874 = or(_T_873, bus_coalescing_disable) @[lsu_bus_buffer.scala 216:67] + node _T_875 = and(ibuf_valid, _T_874) @[lsu_bus_buffer.scala 215:32] + ibuf_drain_vld <= _T_875 @[lsu_bus_buffer.scala 215:18] wire ibuf_tag : UInt<2> ibuf_tag <= UInt<1>("h00") wire WrPtr1_r : UInt<2> WrPtr1_r <= UInt<1>("h00") wire WrPtr0_r : UInt<2> WrPtr0_r <= UInt<1>("h00") - node _T_876 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 220:39] - node _T_877 = mux(io.ldst_dual_r, WrPtr1_r, WrPtr0_r) @[lsu_bus_buffer.scala 220:69] - node ibuf_tag_in = mux(_T_876, ibuf_tag, _T_877) @[lsu_bus_buffer.scala 220:24] + node _T_876 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 221:39] + node _T_877 = mux(io.ldst_dual_r, WrPtr1_r, WrPtr0_r) @[lsu_bus_buffer.scala 221:69] + node ibuf_tag_in = mux(_T_876, ibuf_tag, _T_877) @[lsu_bus_buffer.scala 221:24] node ibuf_sz_in = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58] - node ibuf_addr_in = mux(io.ldst_dual_r, io.end_addr_r, io.lsu_addr_r) @[lsu_bus_buffer.scala 223:25] - node _T_878 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 224:42] - node _T_879 = bits(ibuf_byteen, 3, 0) @[lsu_bus_buffer.scala 224:70] - node _T_880 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 224:95] - node _T_881 = or(_T_879, _T_880) @[lsu_bus_buffer.scala 224:77] - node _T_882 = bits(ldst_byteen_hi_r, 3, 0) @[lsu_bus_buffer.scala 225:41] - node _T_883 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 225:65] - node _T_884 = mux(io.ldst_dual_r, _T_882, _T_883) @[lsu_bus_buffer.scala 225:8] - node ibuf_byteen_in = mux(_T_878, _T_881, _T_884) @[lsu_bus_buffer.scala 224:27] - node _T_885 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 228:61] - node _T_886 = bits(ldst_byteen_lo_r, 0, 0) @[lsu_bus_buffer.scala 229:25] - node _T_887 = bits(store_data_lo_r, 7, 0) @[lsu_bus_buffer.scala 229:45] - node _T_888 = bits(ibuf_data, 7, 0) @[lsu_bus_buffer.scala 229:76] - node _T_889 = mux(_T_886, _T_887, _T_888) @[lsu_bus_buffer.scala 229:8] - node _T_890 = bits(store_data_hi_r, 7, 0) @[lsu_bus_buffer.scala 230:40] - node _T_891 = bits(store_data_lo_r, 7, 0) @[lsu_bus_buffer.scala 230:77] - node _T_892 = mux(io.ldst_dual_r, _T_890, _T_891) @[lsu_bus_buffer.scala 230:8] - node _T_893 = mux(_T_885, _T_889, _T_892) @[lsu_bus_buffer.scala 228:46] - node _T_894 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 228:61] - node _T_895 = bits(ldst_byteen_lo_r, 1, 1) @[lsu_bus_buffer.scala 229:25] - node _T_896 = bits(store_data_lo_r, 15, 8) @[lsu_bus_buffer.scala 229:45] - node _T_897 = bits(ibuf_data, 15, 8) @[lsu_bus_buffer.scala 229:76] - node _T_898 = mux(_T_895, _T_896, _T_897) @[lsu_bus_buffer.scala 229:8] - node _T_899 = bits(store_data_hi_r, 15, 8) @[lsu_bus_buffer.scala 230:40] - node _T_900 = bits(store_data_lo_r, 15, 8) @[lsu_bus_buffer.scala 230:77] - node _T_901 = mux(io.ldst_dual_r, _T_899, _T_900) @[lsu_bus_buffer.scala 230:8] - node _T_902 = mux(_T_894, _T_898, _T_901) @[lsu_bus_buffer.scala 228:46] - node _T_903 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 228:61] - node _T_904 = bits(ldst_byteen_lo_r, 2, 2) @[lsu_bus_buffer.scala 229:25] - node _T_905 = bits(store_data_lo_r, 23, 16) @[lsu_bus_buffer.scala 229:45] - node _T_906 = bits(ibuf_data, 23, 16) @[lsu_bus_buffer.scala 229:76] - node _T_907 = mux(_T_904, _T_905, _T_906) @[lsu_bus_buffer.scala 229:8] - node _T_908 = bits(store_data_hi_r, 23, 16) @[lsu_bus_buffer.scala 230:40] - node _T_909 = bits(store_data_lo_r, 23, 16) @[lsu_bus_buffer.scala 230:77] - node _T_910 = mux(io.ldst_dual_r, _T_908, _T_909) @[lsu_bus_buffer.scala 230:8] - node _T_911 = mux(_T_903, _T_907, _T_910) @[lsu_bus_buffer.scala 228:46] - node _T_912 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 228:61] - node _T_913 = bits(ldst_byteen_lo_r, 3, 3) @[lsu_bus_buffer.scala 229:25] - node _T_914 = bits(store_data_lo_r, 31, 24) @[lsu_bus_buffer.scala 229:45] - node _T_915 = bits(ibuf_data, 31, 24) @[lsu_bus_buffer.scala 229:76] - node _T_916 = mux(_T_913, _T_914, _T_915) @[lsu_bus_buffer.scala 229:8] - node _T_917 = bits(store_data_hi_r, 31, 24) @[lsu_bus_buffer.scala 230:40] - node _T_918 = bits(store_data_lo_r, 31, 24) @[lsu_bus_buffer.scala 230:77] - node _T_919 = mux(io.ldst_dual_r, _T_917, _T_918) @[lsu_bus_buffer.scala 230:8] - node _T_920 = mux(_T_912, _T_916, _T_919) @[lsu_bus_buffer.scala 228:46] + node ibuf_addr_in = mux(io.ldst_dual_r, io.end_addr_r, io.lsu_addr_r) @[lsu_bus_buffer.scala 224:25] + node _T_878 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 225:42] + node _T_879 = bits(ibuf_byteen, 3, 0) @[lsu_bus_buffer.scala 225:70] + node _T_880 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 225:95] + node _T_881 = or(_T_879, _T_880) @[lsu_bus_buffer.scala 225:77] + node _T_882 = bits(ldst_byteen_hi_r, 3, 0) @[lsu_bus_buffer.scala 226:41] + node _T_883 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 226:65] + node _T_884 = mux(io.ldst_dual_r, _T_882, _T_883) @[lsu_bus_buffer.scala 226:8] + node ibuf_byteen_in = mux(_T_878, _T_881, _T_884) @[lsu_bus_buffer.scala 225:27] + node _T_885 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 229:61] + node _T_886 = bits(ldst_byteen_lo_r, 0, 0) @[lsu_bus_buffer.scala 230:25] + node _T_887 = bits(store_data_lo_r, 7, 0) @[lsu_bus_buffer.scala 230:45] + node _T_888 = bits(ibuf_data, 7, 0) @[lsu_bus_buffer.scala 230:76] + node _T_889 = mux(_T_886, _T_887, _T_888) @[lsu_bus_buffer.scala 230:8] + node _T_890 = bits(store_data_hi_r, 7, 0) @[lsu_bus_buffer.scala 231:40] + node _T_891 = bits(store_data_lo_r, 7, 0) @[lsu_bus_buffer.scala 231:77] + node _T_892 = mux(io.ldst_dual_r, _T_890, _T_891) @[lsu_bus_buffer.scala 231:8] + node _T_893 = mux(_T_885, _T_889, _T_892) @[lsu_bus_buffer.scala 229:46] + node _T_894 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 229:61] + node _T_895 = bits(ldst_byteen_lo_r, 1, 1) @[lsu_bus_buffer.scala 230:25] + node _T_896 = bits(store_data_lo_r, 15, 8) @[lsu_bus_buffer.scala 230:45] + node _T_897 = bits(ibuf_data, 15, 8) @[lsu_bus_buffer.scala 230:76] + node _T_898 = mux(_T_895, _T_896, _T_897) @[lsu_bus_buffer.scala 230:8] + node _T_899 = bits(store_data_hi_r, 15, 8) @[lsu_bus_buffer.scala 231:40] + node _T_900 = bits(store_data_lo_r, 15, 8) @[lsu_bus_buffer.scala 231:77] + node _T_901 = mux(io.ldst_dual_r, _T_899, _T_900) @[lsu_bus_buffer.scala 231:8] + node _T_902 = mux(_T_894, _T_898, _T_901) @[lsu_bus_buffer.scala 229:46] + node _T_903 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 229:61] + node _T_904 = bits(ldst_byteen_lo_r, 2, 2) @[lsu_bus_buffer.scala 230:25] + node _T_905 = bits(store_data_lo_r, 23, 16) @[lsu_bus_buffer.scala 230:45] + node _T_906 = bits(ibuf_data, 23, 16) @[lsu_bus_buffer.scala 230:76] + node _T_907 = mux(_T_904, _T_905, _T_906) @[lsu_bus_buffer.scala 230:8] + node _T_908 = bits(store_data_hi_r, 23, 16) @[lsu_bus_buffer.scala 231:40] + node _T_909 = bits(store_data_lo_r, 23, 16) @[lsu_bus_buffer.scala 231:77] + node _T_910 = mux(io.ldst_dual_r, _T_908, _T_909) @[lsu_bus_buffer.scala 231:8] + node _T_911 = mux(_T_903, _T_907, _T_910) @[lsu_bus_buffer.scala 229:46] + node _T_912 = and(ibuf_merge_en, ibuf_merge_in) @[lsu_bus_buffer.scala 229:61] + node _T_913 = bits(ldst_byteen_lo_r, 3, 3) @[lsu_bus_buffer.scala 230:25] + node _T_914 = bits(store_data_lo_r, 31, 24) @[lsu_bus_buffer.scala 230:45] + node _T_915 = bits(ibuf_data, 31, 24) @[lsu_bus_buffer.scala 230:76] + node _T_916 = mux(_T_913, _T_914, _T_915) @[lsu_bus_buffer.scala 230:8] + node _T_917 = bits(store_data_hi_r, 31, 24) @[lsu_bus_buffer.scala 231:40] + node _T_918 = bits(store_data_lo_r, 31, 24) @[lsu_bus_buffer.scala 231:77] + node _T_919 = mux(io.ldst_dual_r, _T_917, _T_918) @[lsu_bus_buffer.scala 231:8] + node _T_920 = mux(_T_912, _T_916, _T_919) @[lsu_bus_buffer.scala 229:46] node _T_921 = cat(_T_920, _T_911) @[Cat.scala 29:58] node _T_922 = cat(_T_921, _T_902) @[Cat.scala 29:58] node ibuf_data_in = cat(_T_922, _T_893) @[Cat.scala 29:58] - node _T_923 = lt(ibuf_timer, UInt<3>("h07")) @[lsu_bus_buffer.scala 231:59] - node _T_924 = bits(_T_923, 0, 0) @[lsu_bus_buffer.scala 231:79] - node _T_925 = add(ibuf_timer, UInt<1>("h01")) @[lsu_bus_buffer.scala 231:93] - node _T_926 = tail(_T_925, 1) @[lsu_bus_buffer.scala 231:93] - node _T_927 = mux(_T_924, _T_926, ibuf_timer) @[lsu_bus_buffer.scala 231:47] - node ibuf_timer_in = mux(ibuf_wr_en, UInt<1>("h00"), _T_927) @[lsu_bus_buffer.scala 231:26] - node _T_928 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 233:36] - node _T_929 = and(_T_928, io.lsu_pkt_r.bits.store) @[lsu_bus_buffer.scala 233:54] - node _T_930 = and(_T_929, ibuf_valid) @[lsu_bus_buffer.scala 233:80] - node _T_931 = and(_T_930, ibuf_write) @[lsu_bus_buffer.scala 233:93] - node _T_932 = bits(io.lsu_addr_r, 31, 2) @[lsu_bus_buffer.scala 233:122] - node _T_933 = bits(ibuf_addr, 31, 2) @[lsu_bus_buffer.scala 233:142] - node _T_934 = eq(_T_932, _T_933) @[lsu_bus_buffer.scala 233:129] - node _T_935 = and(_T_931, _T_934) @[lsu_bus_buffer.scala 233:106] - node _T_936 = eq(io.is_sideeffects_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 233:152] - node _T_937 = and(_T_935, _T_936) @[lsu_bus_buffer.scala 233:150] - node _T_938 = eq(bus_coalescing_disable, UInt<1>("h00")) @[lsu_bus_buffer.scala 233:175] - node _T_939 = and(_T_937, _T_938) @[lsu_bus_buffer.scala 233:173] - ibuf_merge_en <= _T_939 @[lsu_bus_buffer.scala 233:17] - node _T_940 = eq(io.ldst_dual_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 234:20] - ibuf_merge_in <= _T_940 @[lsu_bus_buffer.scala 234:17] - node _T_941 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 235:65] - node _T_942 = and(ibuf_merge_en, _T_941) @[lsu_bus_buffer.scala 235:63] - node _T_943 = bits(ibuf_byteen, 0, 0) @[lsu_bus_buffer.scala 235:92] - node _T_944 = bits(ldst_byteen_lo_r, 0, 0) @[lsu_bus_buffer.scala 235:114] - node _T_945 = or(_T_943, _T_944) @[lsu_bus_buffer.scala 235:96] - node _T_946 = bits(ibuf_byteen, 0, 0) @[lsu_bus_buffer.scala 235:130] - node _T_947 = mux(_T_942, _T_945, _T_946) @[lsu_bus_buffer.scala 235:48] - node _T_948 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 235:65] - node _T_949 = and(ibuf_merge_en, _T_948) @[lsu_bus_buffer.scala 235:63] - node _T_950 = bits(ibuf_byteen, 1, 1) @[lsu_bus_buffer.scala 235:92] - node _T_951 = bits(ldst_byteen_lo_r, 1, 1) @[lsu_bus_buffer.scala 235:114] - node _T_952 = or(_T_950, _T_951) @[lsu_bus_buffer.scala 235:96] - node _T_953 = bits(ibuf_byteen, 1, 1) @[lsu_bus_buffer.scala 235:130] - node _T_954 = mux(_T_949, _T_952, _T_953) @[lsu_bus_buffer.scala 235:48] - node _T_955 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 235:65] - node _T_956 = and(ibuf_merge_en, _T_955) @[lsu_bus_buffer.scala 235:63] - node _T_957 = bits(ibuf_byteen, 2, 2) @[lsu_bus_buffer.scala 235:92] - node _T_958 = bits(ldst_byteen_lo_r, 2, 2) @[lsu_bus_buffer.scala 235:114] - node _T_959 = or(_T_957, _T_958) @[lsu_bus_buffer.scala 235:96] - node _T_960 = bits(ibuf_byteen, 2, 2) @[lsu_bus_buffer.scala 235:130] - node _T_961 = mux(_T_956, _T_959, _T_960) @[lsu_bus_buffer.scala 235:48] - node _T_962 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 235:65] - node _T_963 = and(ibuf_merge_en, _T_962) @[lsu_bus_buffer.scala 235:63] - node _T_964 = bits(ibuf_byteen, 3, 3) @[lsu_bus_buffer.scala 235:92] - node _T_965 = bits(ldst_byteen_lo_r, 3, 3) @[lsu_bus_buffer.scala 235:114] - node _T_966 = or(_T_964, _T_965) @[lsu_bus_buffer.scala 235:96] - node _T_967 = bits(ibuf_byteen, 3, 3) @[lsu_bus_buffer.scala 235:130] - node _T_968 = mux(_T_963, _T_966, _T_967) @[lsu_bus_buffer.scala 235:48] + node _T_923 = lt(ibuf_timer, UInt<3>("h07")) @[lsu_bus_buffer.scala 232:59] + node _T_924 = bits(_T_923, 0, 0) @[lsu_bus_buffer.scala 232:79] + node _T_925 = add(ibuf_timer, UInt<1>("h01")) @[lsu_bus_buffer.scala 232:93] + node _T_926 = tail(_T_925, 1) @[lsu_bus_buffer.scala 232:93] + node _T_927 = mux(_T_924, _T_926, ibuf_timer) @[lsu_bus_buffer.scala 232:47] + node ibuf_timer_in = mux(ibuf_wr_en, UInt<1>("h00"), _T_927) @[lsu_bus_buffer.scala 232:26] + node _T_928 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 234:36] + node _T_929 = and(_T_928, io.lsu_pkt_r.bits.store) @[lsu_bus_buffer.scala 234:54] + node _T_930 = and(_T_929, ibuf_valid) @[lsu_bus_buffer.scala 234:80] + node _T_931 = and(_T_930, ibuf_write) @[lsu_bus_buffer.scala 234:93] + node _T_932 = bits(io.lsu_addr_r, 31, 2) @[lsu_bus_buffer.scala 234:122] + node _T_933 = bits(ibuf_addr, 31, 2) @[lsu_bus_buffer.scala 234:142] + node _T_934 = eq(_T_932, _T_933) @[lsu_bus_buffer.scala 234:129] + node _T_935 = and(_T_931, _T_934) @[lsu_bus_buffer.scala 234:106] + node _T_936 = eq(io.is_sideeffects_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 234:152] + node _T_937 = and(_T_935, _T_936) @[lsu_bus_buffer.scala 234:150] + node _T_938 = eq(bus_coalescing_disable, UInt<1>("h00")) @[lsu_bus_buffer.scala 234:175] + node _T_939 = and(_T_937, _T_938) @[lsu_bus_buffer.scala 234:173] + ibuf_merge_en <= _T_939 @[lsu_bus_buffer.scala 234:17] + node _T_940 = eq(io.ldst_dual_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 235:20] + ibuf_merge_in <= _T_940 @[lsu_bus_buffer.scala 235:17] + node _T_941 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 236:65] + node _T_942 = and(ibuf_merge_en, _T_941) @[lsu_bus_buffer.scala 236:63] + node _T_943 = bits(ibuf_byteen, 0, 0) @[lsu_bus_buffer.scala 236:92] + node _T_944 = bits(ldst_byteen_lo_r, 0, 0) @[lsu_bus_buffer.scala 236:114] + node _T_945 = or(_T_943, _T_944) @[lsu_bus_buffer.scala 236:96] + node _T_946 = bits(ibuf_byteen, 0, 0) @[lsu_bus_buffer.scala 236:130] + node _T_947 = mux(_T_942, _T_945, _T_946) @[lsu_bus_buffer.scala 236:48] + node _T_948 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 236:65] + node _T_949 = and(ibuf_merge_en, _T_948) @[lsu_bus_buffer.scala 236:63] + node _T_950 = bits(ibuf_byteen, 1, 1) @[lsu_bus_buffer.scala 236:92] + node _T_951 = bits(ldst_byteen_lo_r, 1, 1) @[lsu_bus_buffer.scala 236:114] + node _T_952 = or(_T_950, _T_951) @[lsu_bus_buffer.scala 236:96] + node _T_953 = bits(ibuf_byteen, 1, 1) @[lsu_bus_buffer.scala 236:130] + node _T_954 = mux(_T_949, _T_952, _T_953) @[lsu_bus_buffer.scala 236:48] + node _T_955 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 236:65] + node _T_956 = and(ibuf_merge_en, _T_955) @[lsu_bus_buffer.scala 236:63] + node _T_957 = bits(ibuf_byteen, 2, 2) @[lsu_bus_buffer.scala 236:92] + node _T_958 = bits(ldst_byteen_lo_r, 2, 2) @[lsu_bus_buffer.scala 236:114] + node _T_959 = or(_T_957, _T_958) @[lsu_bus_buffer.scala 236:96] + node _T_960 = bits(ibuf_byteen, 2, 2) @[lsu_bus_buffer.scala 236:130] + node _T_961 = mux(_T_956, _T_959, _T_960) @[lsu_bus_buffer.scala 236:48] + node _T_962 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 236:65] + node _T_963 = and(ibuf_merge_en, _T_962) @[lsu_bus_buffer.scala 236:63] + node _T_964 = bits(ibuf_byteen, 3, 3) @[lsu_bus_buffer.scala 236:92] + node _T_965 = bits(ldst_byteen_lo_r, 3, 3) @[lsu_bus_buffer.scala 236:114] + node _T_966 = or(_T_964, _T_965) @[lsu_bus_buffer.scala 236:96] + node _T_967 = bits(ibuf_byteen, 3, 3) @[lsu_bus_buffer.scala 236:130] + node _T_968 = mux(_T_963, _T_966, _T_967) @[lsu_bus_buffer.scala 236:48] node _T_969 = cat(_T_968, _T_961) @[Cat.scala 29:58] node _T_970 = cat(_T_969, _T_954) @[Cat.scala 29:58] node ibuf_byteen_out = cat(_T_970, _T_947) @[Cat.scala 29:58] - node _T_971 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 236:62] - node _T_972 = and(ibuf_merge_en, _T_971) @[lsu_bus_buffer.scala 236:60] - node _T_973 = bits(ldst_byteen_lo_r, 0, 0) @[lsu_bus_buffer.scala 236:98] - node _T_974 = bits(store_data_lo_r, 7, 0) @[lsu_bus_buffer.scala 236:118] - node _T_975 = bits(ibuf_data, 7, 0) @[lsu_bus_buffer.scala 236:143] - node _T_976 = mux(_T_973, _T_974, _T_975) @[lsu_bus_buffer.scala 236:81] - node _T_977 = bits(ibuf_data, 7, 0) @[lsu_bus_buffer.scala 236:169] - node _T_978 = mux(_T_972, _T_976, _T_977) @[lsu_bus_buffer.scala 236:45] - node _T_979 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 236:62] - node _T_980 = and(ibuf_merge_en, _T_979) @[lsu_bus_buffer.scala 236:60] - node _T_981 = bits(ldst_byteen_lo_r, 1, 1) @[lsu_bus_buffer.scala 236:98] - node _T_982 = bits(store_data_lo_r, 15, 8) @[lsu_bus_buffer.scala 236:118] - node _T_983 = bits(ibuf_data, 15, 8) @[lsu_bus_buffer.scala 236:143] - node _T_984 = mux(_T_981, _T_982, _T_983) @[lsu_bus_buffer.scala 236:81] - node _T_985 = bits(ibuf_data, 15, 8) @[lsu_bus_buffer.scala 236:169] - node _T_986 = mux(_T_980, _T_984, _T_985) @[lsu_bus_buffer.scala 236:45] - node _T_987 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 236:62] - node _T_988 = and(ibuf_merge_en, _T_987) @[lsu_bus_buffer.scala 236:60] - node _T_989 = bits(ldst_byteen_lo_r, 2, 2) @[lsu_bus_buffer.scala 236:98] - node _T_990 = bits(store_data_lo_r, 23, 16) @[lsu_bus_buffer.scala 236:118] - node _T_991 = bits(ibuf_data, 23, 16) @[lsu_bus_buffer.scala 236:143] - node _T_992 = mux(_T_989, _T_990, _T_991) @[lsu_bus_buffer.scala 236:81] - node _T_993 = bits(ibuf_data, 23, 16) @[lsu_bus_buffer.scala 236:169] - node _T_994 = mux(_T_988, _T_992, _T_993) @[lsu_bus_buffer.scala 236:45] - node _T_995 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 236:62] - node _T_996 = and(ibuf_merge_en, _T_995) @[lsu_bus_buffer.scala 236:60] - node _T_997 = bits(ldst_byteen_lo_r, 3, 3) @[lsu_bus_buffer.scala 236:98] - node _T_998 = bits(store_data_lo_r, 31, 24) @[lsu_bus_buffer.scala 236:118] - node _T_999 = bits(ibuf_data, 31, 24) @[lsu_bus_buffer.scala 236:143] - node _T_1000 = mux(_T_997, _T_998, _T_999) @[lsu_bus_buffer.scala 236:81] - node _T_1001 = bits(ibuf_data, 31, 24) @[lsu_bus_buffer.scala 236:169] - node _T_1002 = mux(_T_996, _T_1000, _T_1001) @[lsu_bus_buffer.scala 236:45] + node _T_971 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 237:62] + node _T_972 = and(ibuf_merge_en, _T_971) @[lsu_bus_buffer.scala 237:60] + node _T_973 = bits(ldst_byteen_lo_r, 0, 0) @[lsu_bus_buffer.scala 237:98] + node _T_974 = bits(store_data_lo_r, 7, 0) @[lsu_bus_buffer.scala 237:118] + node _T_975 = bits(ibuf_data, 7, 0) @[lsu_bus_buffer.scala 237:143] + node _T_976 = mux(_T_973, _T_974, _T_975) @[lsu_bus_buffer.scala 237:81] + node _T_977 = bits(ibuf_data, 7, 0) @[lsu_bus_buffer.scala 237:169] + node _T_978 = mux(_T_972, _T_976, _T_977) @[lsu_bus_buffer.scala 237:45] + node _T_979 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 237:62] + node _T_980 = and(ibuf_merge_en, _T_979) @[lsu_bus_buffer.scala 237:60] + node _T_981 = bits(ldst_byteen_lo_r, 1, 1) @[lsu_bus_buffer.scala 237:98] + node _T_982 = bits(store_data_lo_r, 15, 8) @[lsu_bus_buffer.scala 237:118] + node _T_983 = bits(ibuf_data, 15, 8) @[lsu_bus_buffer.scala 237:143] + node _T_984 = mux(_T_981, _T_982, _T_983) @[lsu_bus_buffer.scala 237:81] + node _T_985 = bits(ibuf_data, 15, 8) @[lsu_bus_buffer.scala 237:169] + node _T_986 = mux(_T_980, _T_984, _T_985) @[lsu_bus_buffer.scala 237:45] + node _T_987 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 237:62] + node _T_988 = and(ibuf_merge_en, _T_987) @[lsu_bus_buffer.scala 237:60] + node _T_989 = bits(ldst_byteen_lo_r, 2, 2) @[lsu_bus_buffer.scala 237:98] + node _T_990 = bits(store_data_lo_r, 23, 16) @[lsu_bus_buffer.scala 237:118] + node _T_991 = bits(ibuf_data, 23, 16) @[lsu_bus_buffer.scala 237:143] + node _T_992 = mux(_T_989, _T_990, _T_991) @[lsu_bus_buffer.scala 237:81] + node _T_993 = bits(ibuf_data, 23, 16) @[lsu_bus_buffer.scala 237:169] + node _T_994 = mux(_T_988, _T_992, _T_993) @[lsu_bus_buffer.scala 237:45] + node _T_995 = eq(ibuf_merge_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 237:62] + node _T_996 = and(ibuf_merge_en, _T_995) @[lsu_bus_buffer.scala 237:60] + node _T_997 = bits(ldst_byteen_lo_r, 3, 3) @[lsu_bus_buffer.scala 237:98] + node _T_998 = bits(store_data_lo_r, 31, 24) @[lsu_bus_buffer.scala 237:118] + node _T_999 = bits(ibuf_data, 31, 24) @[lsu_bus_buffer.scala 237:143] + node _T_1000 = mux(_T_997, _T_998, _T_999) @[lsu_bus_buffer.scala 237:81] + node _T_1001 = bits(ibuf_data, 31, 24) @[lsu_bus_buffer.scala 237:169] + node _T_1002 = mux(_T_996, _T_1000, _T_1001) @[lsu_bus_buffer.scala 237:45] node _T_1003 = cat(_T_1002, _T_994) @[Cat.scala 29:58] node _T_1004 = cat(_T_1003, _T_986) @[Cat.scala 29:58] node ibuf_data_out = cat(_T_1004, _T_978) @[Cat.scala 29:58] - node _T_1005 = mux(ibuf_wr_en, UInt<1>("h01"), ibuf_valid) @[lsu_bus_buffer.scala 238:58] - node _T_1006 = eq(ibuf_rst, UInt<1>("h00")) @[lsu_bus_buffer.scala 238:93] - node _T_1007 = and(_T_1005, _T_1006) @[lsu_bus_buffer.scala 238:91] - reg _T_1008 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 238:54] - _T_1008 <= _T_1007 @[lsu_bus_buffer.scala 238:54] - ibuf_valid <= _T_1008 @[lsu_bus_buffer.scala 238:14] + node _T_1005 = mux(ibuf_wr_en, UInt<1>("h01"), ibuf_valid) @[lsu_bus_buffer.scala 239:58] + node _T_1006 = eq(ibuf_rst, UInt<1>("h00")) @[lsu_bus_buffer.scala 239:93] + node _T_1007 = and(_T_1005, _T_1006) @[lsu_bus_buffer.scala 239:91] + reg _T_1008 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 239:54] + _T_1008 <= _T_1007 @[lsu_bus_buffer.scala 239:54] + ibuf_valid <= _T_1008 @[lsu_bus_buffer.scala 239:14] reg _T_1009 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when ibuf_wr_en : @[Reg.scala 28:19] _T_1009 <= ibuf_tag_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ibuf_tag <= _T_1009 @[lsu_bus_buffer.scala 239:12] + ibuf_tag <= _T_1009 @[lsu_bus_buffer.scala 240:12] reg ibuf_dualtag : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when ibuf_wr_en : @[Reg.scala 28:19] ibuf_dualtag <= WrPtr0_r @[Reg.scala 28:23] @@ -96221,7 +96228,7 @@ circuit quasar_wrapper : when ibuf_wr_en : @[Reg.scala 28:19] _T_1010 <= io.is_sideeffects_r @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ibuf_sideeffect <= _T_1010 @[lsu_bus_buffer.scala 244:19] + ibuf_sideeffect <= _T_1010 @[lsu_bus_buffer.scala 245:19] reg ibuf_unsign : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when ibuf_wr_en : @[Reg.scala 28:19] ibuf_unsign <= io.lsu_pkt_r.bits.unsign @[Reg.scala 28:23] @@ -96230,7 +96237,7 @@ circuit quasar_wrapper : when ibuf_wr_en : @[Reg.scala 28:19] _T_1011 <= io.lsu_pkt_r.bits.store @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ibuf_write <= _T_1011 @[lsu_bus_buffer.scala 246:14] + ibuf_write <= _T_1011 @[lsu_bus_buffer.scala 247:14] reg ibuf_sz : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when ibuf_wr_en : @[Reg.scala 28:19] ibuf_sz <= ibuf_sz_in @[Reg.scala 28:23] @@ -96243,12 +96250,12 @@ circuit quasar_wrapper : rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_1012 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_1012 <= ibuf_addr_in @[lib.scala 374:16] - ibuf_addr <= _T_1012 @[lsu_bus_buffer.scala 248:13] + ibuf_addr <= _T_1012 @[lsu_bus_buffer.scala 249:13] reg _T_1013 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when ibuf_wr_en : @[Reg.scala 28:19] _T_1013 <= ibuf_byteen_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ibuf_byteen <= _T_1013 @[lsu_bus_buffer.scala 249:15] + ibuf_byteen <= _T_1013 @[lsu_bus_buffer.scala 250:15] inst rvclkhdr_1 of rvclkhdr_815 @[lib.scala 368:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset @@ -96257,38 +96264,38 @@ circuit quasar_wrapper : rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_1014 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_1014 <= ibuf_data_in @[lib.scala 374:16] - ibuf_data <= _T_1014 @[lsu_bus_buffer.scala 250:13] - reg _T_1015 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 251:55] - _T_1015 <= ibuf_timer_in @[lsu_bus_buffer.scala 251:55] - ibuf_timer <= _T_1015 @[lsu_bus_buffer.scala 251:14] + ibuf_data <= _T_1014 @[lsu_bus_buffer.scala 251:13] + reg _T_1015 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 252:55] + _T_1015 <= ibuf_timer_in @[lsu_bus_buffer.scala 252:55] + ibuf_timer <= _T_1015 @[lsu_bus_buffer.scala 252:14] wire buf_numvld_wrcmd_any : UInt<4> buf_numvld_wrcmd_any <= UInt<1>("h00") wire buf_numvld_cmd_any : UInt<4> buf_numvld_cmd_any <= UInt<1>("h00") wire obuf_wr_timer : UInt<3> obuf_wr_timer <= UInt<1>("h00") - wire buf_nomerge : UInt<1>[4] @[lsu_bus_buffer.scala 255:25] - buf_nomerge[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 256:15] - buf_nomerge[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 256:15] - buf_nomerge[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 256:15] - buf_nomerge[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 256:15] + wire buf_nomerge : UInt<1>[4] @[lsu_bus_buffer.scala 256:25] + buf_nomerge[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 257:15] + buf_nomerge[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 257:15] + buf_nomerge[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 257:15] + buf_nomerge[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 257:15] wire buf_sideeffect : UInt<4> buf_sideeffect <= UInt<1>("h00") wire obuf_force_wr_en : UInt<1> obuf_force_wr_en <= UInt<1>("h00") wire obuf_wr_en : UInt<1> obuf_wr_en <= UInt<1>("h00") - node _T_1016 = eq(buf_numvld_wrcmd_any, UInt<1>("h01")) @[lsu_bus_buffer.scala 261:43] - node _T_1017 = eq(buf_numvld_cmd_any, UInt<1>("h01")) @[lsu_bus_buffer.scala 261:72] - node _T_1018 = and(_T_1016, _T_1017) @[lsu_bus_buffer.scala 261:51] - node _T_1019 = neq(obuf_wr_timer, UInt<3>("h07")) @[lsu_bus_buffer.scala 261:97] - node _T_1020 = and(_T_1018, _T_1019) @[lsu_bus_buffer.scala 261:80] - node _T_1021 = eq(bus_coalescing_disable, UInt<1>("h00")) @[lsu_bus_buffer.scala 262:5] - node _T_1022 = and(_T_1020, _T_1021) @[lsu_bus_buffer.scala 261:114] - node _T_1023 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 262:114] - node _T_1024 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 262:114] - node _T_1025 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 262:114] - node _T_1026 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 262:114] + node _T_1016 = eq(buf_numvld_wrcmd_any, UInt<1>("h01")) @[lsu_bus_buffer.scala 262:43] + node _T_1017 = eq(buf_numvld_cmd_any, UInt<1>("h01")) @[lsu_bus_buffer.scala 262:72] + node _T_1018 = and(_T_1016, _T_1017) @[lsu_bus_buffer.scala 262:51] + node _T_1019 = neq(obuf_wr_timer, UInt<3>("h07")) @[lsu_bus_buffer.scala 262:97] + node _T_1020 = and(_T_1018, _T_1019) @[lsu_bus_buffer.scala 262:80] + node _T_1021 = eq(bus_coalescing_disable, UInt<1>("h00")) @[lsu_bus_buffer.scala 263:5] + node _T_1022 = and(_T_1020, _T_1021) @[lsu_bus_buffer.scala 262:114] + node _T_1023 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 263:114] + node _T_1024 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 263:114] + node _T_1025 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 263:114] + node _T_1026 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 263:114] node _T_1027 = mux(_T_1023, buf_nomerge[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1028 = mux(_T_1024, buf_nomerge[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1029 = mux(_T_1025, buf_nomerge[2], UInt<1>("h00")) @[Mux.scala 27:72] @@ -96298,16 +96305,16 @@ circuit quasar_wrapper : node _T_1033 = or(_T_1032, _T_1030) @[Mux.scala 27:72] wire _T_1034 : UInt<1> @[Mux.scala 27:72] _T_1034 <= _T_1033 @[Mux.scala 27:72] - node _T_1035 = eq(_T_1034, UInt<1>("h00")) @[lsu_bus_buffer.scala 262:31] - node _T_1036 = and(_T_1022, _T_1035) @[lsu_bus_buffer.scala 262:29] - node _T_1037 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 263:88] - node _T_1038 = bits(buf_sideeffect, 0, 0) @[lsu_bus_buffer.scala 263:111] - node _T_1039 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 263:88] - node _T_1040 = bits(buf_sideeffect, 1, 1) @[lsu_bus_buffer.scala 263:111] - node _T_1041 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 263:88] - node _T_1042 = bits(buf_sideeffect, 2, 2) @[lsu_bus_buffer.scala 263:111] - node _T_1043 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 263:88] - node _T_1044 = bits(buf_sideeffect, 3, 3) @[lsu_bus_buffer.scala 263:111] + node _T_1035 = eq(_T_1034, UInt<1>("h00")) @[lsu_bus_buffer.scala 263:31] + node _T_1036 = and(_T_1022, _T_1035) @[lsu_bus_buffer.scala 263:29] + node _T_1037 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 264:88] + node _T_1038 = bits(buf_sideeffect, 0, 0) @[lsu_bus_buffer.scala 264:111] + node _T_1039 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 264:88] + node _T_1040 = bits(buf_sideeffect, 1, 1) @[lsu_bus_buffer.scala 264:111] + node _T_1041 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 264:88] + node _T_1042 = bits(buf_sideeffect, 2, 2) @[lsu_bus_buffer.scala 264:111] + node _T_1043 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 264:88] + node _T_1044 = bits(buf_sideeffect, 3, 3) @[lsu_bus_buffer.scala 264:111] node _T_1045 = mux(_T_1037, _T_1038, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1046 = mux(_T_1039, _T_1040, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1047 = mux(_T_1041, _T_1042, UInt<1>("h00")) @[Mux.scala 27:72] @@ -96317,32 +96324,32 @@ circuit quasar_wrapper : node _T_1051 = or(_T_1050, _T_1048) @[Mux.scala 27:72] wire _T_1052 : UInt<1> @[Mux.scala 27:72] _T_1052 <= _T_1051 @[Mux.scala 27:72] - node _T_1053 = eq(_T_1052, UInt<1>("h00")) @[lsu_bus_buffer.scala 263:5] - node _T_1054 = and(_T_1036, _T_1053) @[lsu_bus_buffer.scala 262:140] - node _T_1055 = eq(obuf_force_wr_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 263:119] - node obuf_wr_wait = and(_T_1054, _T_1055) @[lsu_bus_buffer.scala 263:117] - node _T_1056 = orr(buf_numvld_cmd_any) @[lsu_bus_buffer.scala 264:75] - node _T_1057 = lt(obuf_wr_timer, UInt<3>("h07")) @[lsu_bus_buffer.scala 264:95] - node _T_1058 = and(_T_1056, _T_1057) @[lsu_bus_buffer.scala 264:79] - node _T_1059 = add(obuf_wr_timer, UInt<1>("h01")) @[lsu_bus_buffer.scala 264:123] - node _T_1060 = tail(_T_1059, 1) @[lsu_bus_buffer.scala 264:123] - node _T_1061 = mux(_T_1058, _T_1060, obuf_wr_timer) @[lsu_bus_buffer.scala 264:55] - node obuf_wr_timer_in = mux(obuf_wr_en, UInt<3>("h00"), _T_1061) @[lsu_bus_buffer.scala 264:29] - node _T_1062 = eq(io.lsu_busreq_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 265:41] - node _T_1063 = and(io.lsu_busreq_m, _T_1062) @[lsu_bus_buffer.scala 265:39] - node _T_1064 = eq(ibuf_valid, UInt<1>("h00")) @[lsu_bus_buffer.scala 265:60] - node _T_1065 = and(_T_1063, _T_1064) @[lsu_bus_buffer.scala 265:58] - node _T_1066 = eq(buf_numvld_cmd_any, UInt<1>("h01")) @[lsu_bus_buffer.scala 265:93] - node _T_1067 = and(_T_1065, _T_1066) @[lsu_bus_buffer.scala 265:72] - node _T_1068 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 265:117] - node _T_1069 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 265:208] - node _T_1070 = bits(buf_addr[0], 31, 2) @[lsu_bus_buffer.scala 265:228] - node _T_1071 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 265:208] - node _T_1072 = bits(buf_addr[1], 31, 2) @[lsu_bus_buffer.scala 265:228] - node _T_1073 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 265:208] - node _T_1074 = bits(buf_addr[2], 31, 2) @[lsu_bus_buffer.scala 265:228] - node _T_1075 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 265:208] - node _T_1076 = bits(buf_addr[3], 31, 2) @[lsu_bus_buffer.scala 265:228] + node _T_1053 = eq(_T_1052, UInt<1>("h00")) @[lsu_bus_buffer.scala 264:5] + node _T_1054 = and(_T_1036, _T_1053) @[lsu_bus_buffer.scala 263:140] + node _T_1055 = eq(obuf_force_wr_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 264:119] + node obuf_wr_wait = and(_T_1054, _T_1055) @[lsu_bus_buffer.scala 264:117] + node _T_1056 = orr(buf_numvld_cmd_any) @[lsu_bus_buffer.scala 265:75] + node _T_1057 = lt(obuf_wr_timer, UInt<3>("h07")) @[lsu_bus_buffer.scala 265:95] + node _T_1058 = and(_T_1056, _T_1057) @[lsu_bus_buffer.scala 265:79] + node _T_1059 = add(obuf_wr_timer, UInt<1>("h01")) @[lsu_bus_buffer.scala 265:123] + node _T_1060 = tail(_T_1059, 1) @[lsu_bus_buffer.scala 265:123] + node _T_1061 = mux(_T_1058, _T_1060, obuf_wr_timer) @[lsu_bus_buffer.scala 265:55] + node obuf_wr_timer_in = mux(obuf_wr_en, UInt<3>("h00"), _T_1061) @[lsu_bus_buffer.scala 265:29] + node _T_1062 = eq(io.lsu_busreq_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 266:41] + node _T_1063 = and(io.lsu_busreq_m, _T_1062) @[lsu_bus_buffer.scala 266:39] + node _T_1064 = eq(ibuf_valid, UInt<1>("h00")) @[lsu_bus_buffer.scala 266:60] + node _T_1065 = and(_T_1063, _T_1064) @[lsu_bus_buffer.scala 266:58] + node _T_1066 = eq(buf_numvld_cmd_any, UInt<1>("h01")) @[lsu_bus_buffer.scala 266:93] + node _T_1067 = and(_T_1065, _T_1066) @[lsu_bus_buffer.scala 266:72] + node _T_1068 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_buffer.scala 266:117] + node _T_1069 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 266:208] + node _T_1070 = bits(buf_addr[0], 31, 2) @[lsu_bus_buffer.scala 266:228] + node _T_1071 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 266:208] + node _T_1072 = bits(buf_addr[1], 31, 2) @[lsu_bus_buffer.scala 266:228] + node _T_1073 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 266:208] + node _T_1074 = bits(buf_addr[2], 31, 2) @[lsu_bus_buffer.scala 266:228] + node _T_1075 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 266:208] + node _T_1076 = bits(buf_addr[3], 31, 2) @[lsu_bus_buffer.scala 266:228] node _T_1077 = mux(_T_1069, _T_1070, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1078 = mux(_T_1071, _T_1072, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1079 = mux(_T_1073, _T_1074, UInt<1>("h00")) @[Mux.scala 27:72] @@ -96352,35 +96359,35 @@ circuit quasar_wrapper : node _T_1083 = or(_T_1082, _T_1080) @[Mux.scala 27:72] wire _T_1084 : UInt<30> @[Mux.scala 27:72] _T_1084 <= _T_1083 @[Mux.scala 27:72] - node _T_1085 = neq(_T_1068, _T_1084) @[lsu_bus_buffer.scala 265:123] - node _T_1086 = and(_T_1067, _T_1085) @[lsu_bus_buffer.scala 265:101] - obuf_force_wr_en <= _T_1086 @[lsu_bus_buffer.scala 265:20] + node _T_1085 = neq(_T_1068, _T_1084) @[lsu_bus_buffer.scala 266:123] + node _T_1086 = and(_T_1067, _T_1085) @[lsu_bus_buffer.scala 266:101] + obuf_force_wr_en <= _T_1086 @[lsu_bus_buffer.scala 266:20] wire buf_numvld_pend_any : UInt<4> buf_numvld_pend_any <= UInt<1>("h00") - node _T_1087 = eq(buf_numvld_pend_any, UInt<1>("h00")) @[lsu_bus_buffer.scala 267:53] - node _T_1088 = and(ibuf_byp, _T_1087) @[lsu_bus_buffer.scala 267:31] - node _T_1089 = eq(io.lsu_pkt_r.bits.store, UInt<1>("h00")) @[lsu_bus_buffer.scala 267:64] - node _T_1090 = or(_T_1089, io.no_dword_merge_r) @[lsu_bus_buffer.scala 267:89] - node ibuf_buf_byp = and(_T_1088, _T_1090) @[lsu_bus_buffer.scala 267:61] + node _T_1087 = eq(buf_numvld_pend_any, UInt<1>("h00")) @[lsu_bus_buffer.scala 268:53] + node _T_1088 = and(ibuf_byp, _T_1087) @[lsu_bus_buffer.scala 268:31] + node _T_1089 = eq(io.lsu_pkt_r.bits.store, UInt<1>("h00")) @[lsu_bus_buffer.scala 268:64] + node _T_1090 = or(_T_1089, io.no_dword_merge_r) @[lsu_bus_buffer.scala 268:89] + node ibuf_buf_byp = and(_T_1088, _T_1090) @[lsu_bus_buffer.scala 268:61] wire bus_sideeffect_pend : UInt<1> bus_sideeffect_pend <= UInt<1>("h00") wire found_cmdptr0 : UInt<1> found_cmdptr0 <= UInt<1>("h00") - wire buf_cmd_state_bus_en : UInt<1>[4] @[lsu_bus_buffer.scala 270:34] - buf_cmd_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 271:24] - buf_cmd_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 271:24] - buf_cmd_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 271:24] - buf_cmd_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 271:24] - wire buf_dual : UInt<1>[4] @[lsu_bus_buffer.scala 272:22] - buf_dual[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 273:12] - buf_dual[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 273:12] - buf_dual[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 273:12] - buf_dual[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 273:12] - wire buf_samedw : UInt<1>[4] @[lsu_bus_buffer.scala 274:24] - buf_samedw[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 275:14] - buf_samedw[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 275:14] - buf_samedw[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 275:14] - buf_samedw[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 275:14] + wire buf_cmd_state_bus_en : UInt<1>[4] @[lsu_bus_buffer.scala 271:34] + buf_cmd_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 272:24] + buf_cmd_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 272:24] + buf_cmd_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 272:24] + buf_cmd_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 272:24] + wire buf_dual : UInt<1>[4] @[lsu_bus_buffer.scala 273:22] + buf_dual[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 274:12] + buf_dual[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 274:12] + buf_dual[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 274:12] + buf_dual[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 274:12] + wire buf_samedw : UInt<1>[4] @[lsu_bus_buffer.scala 275:24] + buf_samedw[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 276:14] + buf_samedw[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 276:14] + buf_samedw[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 276:14] + buf_samedw[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 276:14] wire found_cmdptr1 : UInt<1> found_cmdptr1 <= UInt<1>("h00") wire bus_cmd_ready : UInt<1> @@ -96393,14 +96400,14 @@ circuit quasar_wrapper : lsu_bus_cntr_overflow <= UInt<1>("h00") wire bus_addr_match_pending : UInt<1> bus_addr_match_pending <= UInt<1>("h00") - node _T_1091 = and(ibuf_buf_byp, io.lsu_commit_r) @[lsu_bus_buffer.scala 282:32] - node _T_1092 = and(io.is_sideeffects_r, bus_sideeffect_pend) @[lsu_bus_buffer.scala 282:74] - node _T_1093 = eq(_T_1092, UInt<1>("h00")) @[lsu_bus_buffer.scala 282:52] - node _T_1094 = and(_T_1091, _T_1093) @[lsu_bus_buffer.scala 282:50] - node _T_1095 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:123] - node _T_1096 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:123] - node _T_1097 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:123] - node _T_1098 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:123] + node _T_1091 = and(ibuf_buf_byp, io.lsu_commit_r) @[lsu_bus_buffer.scala 283:32] + node _T_1092 = and(io.is_sideeffects_r, bus_sideeffect_pend) @[lsu_bus_buffer.scala 283:74] + node _T_1093 = eq(_T_1092, UInt<1>("h00")) @[lsu_bus_buffer.scala 283:52] + node _T_1094 = and(_T_1091, _T_1093) @[lsu_bus_buffer.scala 283:50] + node _T_1095 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1096 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1097 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1098 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] node _T_1099 = mux(_T_1095, buf_state[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1100 = mux(_T_1096, buf_state[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1101 = mux(_T_1097, buf_state[2], UInt<1>("h00")) @[Mux.scala 27:72] @@ -96410,19 +96417,19 @@ circuit quasar_wrapper : node _T_1105 = or(_T_1104, _T_1102) @[Mux.scala 27:72] wire _T_1106 : UInt<3> @[Mux.scala 27:72] _T_1106 <= _T_1105 @[Mux.scala 27:72] - node _T_1107 = eq(_T_1106, UInt<3>("h02")) @[lsu_bus_buffer.scala 283:36] - node _T_1108 = and(_T_1107, found_cmdptr0) @[lsu_bus_buffer.scala 283:47] + node _T_1107 = eq(_T_1106, UInt<3>("h02")) @[lsu_bus_buffer.scala 284:36] + node _T_1108 = and(_T_1107, found_cmdptr0) @[lsu_bus_buffer.scala 284:47] node _T_1109 = cat(buf_cmd_state_bus_en[3], buf_cmd_state_bus_en[2]) @[Cat.scala 29:58] node _T_1110 = cat(_T_1109, buf_cmd_state_bus_en[1]) @[Cat.scala 29:58] node _T_1111 = cat(_T_1110, buf_cmd_state_bus_en[0]) @[Cat.scala 29:58] - node _T_1112 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 56:118] - node _T_1113 = bits(_T_1111, 0, 0) @[lsu_bus_buffer.scala 56:129] - node _T_1114 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 56:118] - node _T_1115 = bits(_T_1111, 1, 1) @[lsu_bus_buffer.scala 56:129] - node _T_1116 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 56:118] - node _T_1117 = bits(_T_1111, 2, 2) @[lsu_bus_buffer.scala 56:129] - node _T_1118 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 56:118] - node _T_1119 = bits(_T_1111, 3, 3) @[lsu_bus_buffer.scala 56:129] + node _T_1112 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_1113 = bits(_T_1111, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_1114 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_1115 = bits(_T_1111, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_1116 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_1117 = bits(_T_1111, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_1118 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_1119 = bits(_T_1111, 3, 3) @[lsu_bus_buffer.scala 57:129] node _T_1120 = mux(_T_1112, _T_1113, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1121 = mux(_T_1114, _T_1115, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1122 = mux(_T_1116, _T_1117, UInt<1>("h00")) @[Mux.scala 27:72] @@ -96432,16 +96439,16 @@ circuit quasar_wrapper : node _T_1126 = or(_T_1125, _T_1123) @[Mux.scala 27:72] wire _T_1127 : UInt<1> @[Mux.scala 27:72] _T_1127 <= _T_1126 @[Mux.scala 27:72] - node _T_1128 = eq(_T_1127, UInt<1>("h00")) @[lsu_bus_buffer.scala 284:23] - node _T_1129 = and(_T_1108, _T_1128) @[lsu_bus_buffer.scala 284:21] - node _T_1130 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 56:118] - node _T_1131 = bits(buf_sideeffect, 0, 0) @[lsu_bus_buffer.scala 56:129] - node _T_1132 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 56:118] - node _T_1133 = bits(buf_sideeffect, 1, 1) @[lsu_bus_buffer.scala 56:129] - node _T_1134 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 56:118] - node _T_1135 = bits(buf_sideeffect, 2, 2) @[lsu_bus_buffer.scala 56:129] - node _T_1136 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 56:118] - node _T_1137 = bits(buf_sideeffect, 3, 3) @[lsu_bus_buffer.scala 56:129] + node _T_1128 = eq(_T_1127, UInt<1>("h00")) @[lsu_bus_buffer.scala 285:23] + node _T_1129 = and(_T_1108, _T_1128) @[lsu_bus_buffer.scala 285:21] + node _T_1130 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_1131 = bits(buf_sideeffect, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_1132 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_1133 = bits(buf_sideeffect, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_1134 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_1135 = bits(buf_sideeffect, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_1136 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_1137 = bits(buf_sideeffect, 3, 3) @[lsu_bus_buffer.scala 57:129] node _T_1138 = mux(_T_1130, _T_1131, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1139 = mux(_T_1132, _T_1133, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1140 = mux(_T_1134, _T_1135, UInt<1>("h00")) @[Mux.scala 27:72] @@ -96451,20 +96458,20 @@ circuit quasar_wrapper : node _T_1144 = or(_T_1143, _T_1141) @[Mux.scala 27:72] wire _T_1145 : UInt<1> @[Mux.scala 27:72] _T_1145 <= _T_1144 @[Mux.scala 27:72] - node _T_1146 = and(_T_1145, bus_sideeffect_pend) @[lsu_bus_buffer.scala 284:141] - node _T_1147 = eq(_T_1146, UInt<1>("h00")) @[lsu_bus_buffer.scala 284:105] - node _T_1148 = and(_T_1129, _T_1147) @[lsu_bus_buffer.scala 284:103] + node _T_1146 = and(_T_1145, bus_sideeffect_pend) @[lsu_bus_buffer.scala 285:141] + node _T_1147 = eq(_T_1146, UInt<1>("h00")) @[lsu_bus_buffer.scala 285:105] + node _T_1148 = and(_T_1129, _T_1147) @[lsu_bus_buffer.scala 285:103] node _T_1149 = cat(buf_dual[3], buf_dual[2]) @[Cat.scala 29:58] node _T_1150 = cat(_T_1149, buf_dual[1]) @[Cat.scala 29:58] node _T_1151 = cat(_T_1150, buf_dual[0]) @[Cat.scala 29:58] - node _T_1152 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 56:118] - node _T_1153 = bits(_T_1151, 0, 0) @[lsu_bus_buffer.scala 56:129] - node _T_1154 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 56:118] - node _T_1155 = bits(_T_1151, 1, 1) @[lsu_bus_buffer.scala 56:129] - node _T_1156 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 56:118] - node _T_1157 = bits(_T_1151, 2, 2) @[lsu_bus_buffer.scala 56:129] - node _T_1158 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 56:118] - node _T_1159 = bits(_T_1151, 3, 3) @[lsu_bus_buffer.scala 56:129] + node _T_1152 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_1153 = bits(_T_1151, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_1154 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_1155 = bits(_T_1151, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_1156 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_1157 = bits(_T_1151, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_1158 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_1159 = bits(_T_1151, 3, 3) @[lsu_bus_buffer.scala 57:129] node _T_1160 = mux(_T_1152, _T_1153, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1161 = mux(_T_1154, _T_1155, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1162 = mux(_T_1156, _T_1157, UInt<1>("h00")) @[Mux.scala 27:72] @@ -96477,14 +96484,14 @@ circuit quasar_wrapper : node _T_1168 = cat(buf_samedw[3], buf_samedw[2]) @[Cat.scala 29:58] node _T_1169 = cat(_T_1168, buf_samedw[1]) @[Cat.scala 29:58] node _T_1170 = cat(_T_1169, buf_samedw[0]) @[Cat.scala 29:58] - node _T_1171 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 56:118] - node _T_1172 = bits(_T_1170, 0, 0) @[lsu_bus_buffer.scala 56:129] - node _T_1173 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 56:118] - node _T_1174 = bits(_T_1170, 1, 1) @[lsu_bus_buffer.scala 56:129] - node _T_1175 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 56:118] - node _T_1176 = bits(_T_1170, 2, 2) @[lsu_bus_buffer.scala 56:129] - node _T_1177 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 56:118] - node _T_1178 = bits(_T_1170, 3, 3) @[lsu_bus_buffer.scala 56:129] + node _T_1171 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_1172 = bits(_T_1170, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_1173 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_1174 = bits(_T_1170, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_1175 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_1176 = bits(_T_1170, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_1177 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_1178 = bits(_T_1170, 3, 3) @[lsu_bus_buffer.scala 57:129] node _T_1179 = mux(_T_1171, _T_1172, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1180 = mux(_T_1173, _T_1174, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1181 = mux(_T_1175, _T_1176, UInt<1>("h00")) @[Mux.scala 27:72] @@ -96494,15 +96501,15 @@ circuit quasar_wrapper : node _T_1185 = or(_T_1184, _T_1182) @[Mux.scala 27:72] wire _T_1186 : UInt<1> @[Mux.scala 27:72] _T_1186 <= _T_1185 @[Mux.scala 27:72] - node _T_1187 = and(_T_1167, _T_1186) @[lsu_bus_buffer.scala 285:77] - node _T_1188 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 56:118] - node _T_1189 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 56:129] - node _T_1190 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 56:118] - node _T_1191 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 56:129] - node _T_1192 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 56:118] - node _T_1193 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 56:129] - node _T_1194 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 56:118] - node _T_1195 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 56:129] + node _T_1187 = and(_T_1167, _T_1186) @[lsu_bus_buffer.scala 286:77] + node _T_1188 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_1189 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_1190 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_1191 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_1192 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_1193 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_1194 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_1195 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 57:129] node _T_1196 = mux(_T_1188, _T_1189, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1197 = mux(_T_1190, _T_1191, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1198 = mux(_T_1192, _T_1193, UInt<1>("h00")) @[Mux.scala 27:72] @@ -96512,21 +96519,21 @@ circuit quasar_wrapper : node _T_1202 = or(_T_1201, _T_1199) @[Mux.scala 27:72] wire _T_1203 : UInt<1> @[Mux.scala 27:72] _T_1203 <= _T_1202 @[Mux.scala 27:72] - node _T_1204 = eq(_T_1203, UInt<1>("h00")) @[lsu_bus_buffer.scala 285:150] - node _T_1205 = and(_T_1187, _T_1204) @[lsu_bus_buffer.scala 285:148] - node _T_1206 = eq(_T_1205, UInt<1>("h00")) @[lsu_bus_buffer.scala 285:8] - node _T_1207 = or(_T_1206, found_cmdptr1) @[lsu_bus_buffer.scala 285:181] + node _T_1204 = eq(_T_1203, UInt<1>("h00")) @[lsu_bus_buffer.scala 286:150] + node _T_1205 = and(_T_1187, _T_1204) @[lsu_bus_buffer.scala 286:148] + node _T_1206 = eq(_T_1205, UInt<1>("h00")) @[lsu_bus_buffer.scala 286:8] + node _T_1207 = or(_T_1206, found_cmdptr1) @[lsu_bus_buffer.scala 286:181] node _T_1208 = cat(buf_nomerge[3], buf_nomerge[2]) @[Cat.scala 29:58] node _T_1209 = cat(_T_1208, buf_nomerge[1]) @[Cat.scala 29:58] node _T_1210 = cat(_T_1209, buf_nomerge[0]) @[Cat.scala 29:58] - node _T_1211 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 56:118] - node _T_1212 = bits(_T_1210, 0, 0) @[lsu_bus_buffer.scala 56:129] - node _T_1213 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 56:118] - node _T_1214 = bits(_T_1210, 1, 1) @[lsu_bus_buffer.scala 56:129] - node _T_1215 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 56:118] - node _T_1216 = bits(_T_1210, 2, 2) @[lsu_bus_buffer.scala 56:129] - node _T_1217 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 56:118] - node _T_1218 = bits(_T_1210, 3, 3) @[lsu_bus_buffer.scala 56:129] + node _T_1211 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_1212 = bits(_T_1210, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_1213 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_1214 = bits(_T_1210, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_1215 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_1216 = bits(_T_1210, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_1217 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_1218 = bits(_T_1210, 3, 3) @[lsu_bus_buffer.scala 57:129] node _T_1219 = mux(_T_1211, _T_1212, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1220 = mux(_T_1213, _T_1214, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1221 = mux(_T_1215, _T_1216, UInt<1>("h00")) @[Mux.scala 27:72] @@ -96536,38 +96543,38 @@ circuit quasar_wrapper : node _T_1225 = or(_T_1224, _T_1222) @[Mux.scala 27:72] wire _T_1226 : UInt<1> @[Mux.scala 27:72] _T_1226 <= _T_1225 @[Mux.scala 27:72] - node _T_1227 = or(_T_1207, _T_1226) @[lsu_bus_buffer.scala 285:197] - node _T_1228 = or(_T_1227, obuf_force_wr_en) @[lsu_bus_buffer.scala 285:269] - node _T_1229 = and(_T_1148, _T_1228) @[lsu_bus_buffer.scala 284:164] - node _T_1230 = or(_T_1094, _T_1229) @[lsu_bus_buffer.scala 282:98] - node _T_1231 = eq(obuf_valid, UInt<1>("h00")) @[lsu_bus_buffer.scala 286:48] - node _T_1232 = or(bus_cmd_ready, _T_1231) @[lsu_bus_buffer.scala 286:46] - node _T_1233 = or(_T_1232, obuf_nosend) @[lsu_bus_buffer.scala 286:60] - node _T_1234 = and(_T_1230, _T_1233) @[lsu_bus_buffer.scala 286:29] - node _T_1235 = eq(obuf_wr_wait, UInt<1>("h00")) @[lsu_bus_buffer.scala 286:77] - node _T_1236 = and(_T_1234, _T_1235) @[lsu_bus_buffer.scala 286:75] - node _T_1237 = eq(lsu_bus_cntr_overflow, UInt<1>("h00")) @[lsu_bus_buffer.scala 286:93] - node _T_1238 = and(_T_1236, _T_1237) @[lsu_bus_buffer.scala 286:91] - node _T_1239 = eq(bus_addr_match_pending, UInt<1>("h00")) @[lsu_bus_buffer.scala 286:118] - node _T_1240 = and(_T_1238, _T_1239) @[lsu_bus_buffer.scala 286:116] - node _T_1241 = and(_T_1240, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 286:142] - obuf_wr_en <= _T_1241 @[lsu_bus_buffer.scala 282:14] + node _T_1227 = or(_T_1207, _T_1226) @[lsu_bus_buffer.scala 286:197] + node _T_1228 = or(_T_1227, obuf_force_wr_en) @[lsu_bus_buffer.scala 286:269] + node _T_1229 = and(_T_1148, _T_1228) @[lsu_bus_buffer.scala 285:164] + node _T_1230 = or(_T_1094, _T_1229) @[lsu_bus_buffer.scala 283:98] + node _T_1231 = eq(obuf_valid, UInt<1>("h00")) @[lsu_bus_buffer.scala 287:48] + node _T_1232 = or(bus_cmd_ready, _T_1231) @[lsu_bus_buffer.scala 287:46] + node _T_1233 = or(_T_1232, obuf_nosend) @[lsu_bus_buffer.scala 287:60] + node _T_1234 = and(_T_1230, _T_1233) @[lsu_bus_buffer.scala 287:29] + node _T_1235 = eq(obuf_wr_wait, UInt<1>("h00")) @[lsu_bus_buffer.scala 287:77] + node _T_1236 = and(_T_1234, _T_1235) @[lsu_bus_buffer.scala 287:75] + node _T_1237 = eq(lsu_bus_cntr_overflow, UInt<1>("h00")) @[lsu_bus_buffer.scala 287:93] + node _T_1238 = and(_T_1236, _T_1237) @[lsu_bus_buffer.scala 287:91] + node _T_1239 = eq(bus_addr_match_pending, UInt<1>("h00")) @[lsu_bus_buffer.scala 287:118] + node _T_1240 = and(_T_1238, _T_1239) @[lsu_bus_buffer.scala 287:116] + node _T_1241 = and(_T_1240, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 287:142] + obuf_wr_en <= _T_1241 @[lsu_bus_buffer.scala 283:14] wire bus_cmd_sent : UInt<1> bus_cmd_sent <= UInt<1>("h00") - node _T_1242 = and(obuf_valid, obuf_nosend) @[lsu_bus_buffer.scala 288:47] - node _T_1243 = or(bus_cmd_sent, _T_1242) @[lsu_bus_buffer.scala 288:33] - node _T_1244 = eq(obuf_wr_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 288:65] - node _T_1245 = and(_T_1243, _T_1244) @[lsu_bus_buffer.scala 288:63] - node _T_1246 = and(_T_1245, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 288:77] - node obuf_rst = or(_T_1246, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 288:98] - node _T_1247 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 56:118] - node _T_1248 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 56:129] - node _T_1249 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 56:118] - node _T_1250 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 56:129] - node _T_1251 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 56:118] - node _T_1252 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 56:129] - node _T_1253 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 56:118] - node _T_1254 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 56:129] + node _T_1242 = and(obuf_valid, obuf_nosend) @[lsu_bus_buffer.scala 289:47] + node _T_1243 = or(bus_cmd_sent, _T_1242) @[lsu_bus_buffer.scala 289:33] + node _T_1244 = eq(obuf_wr_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 289:65] + node _T_1245 = and(_T_1243, _T_1244) @[lsu_bus_buffer.scala 289:63] + node _T_1246 = and(_T_1245, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 289:77] + node obuf_rst = or(_T_1246, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 289:98] + node _T_1247 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_1248 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_1249 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_1250 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_1251 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_1252 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_1253 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_1254 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 57:129] node _T_1255 = mux(_T_1247, _T_1248, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1256 = mux(_T_1249, _T_1250, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1257 = mux(_T_1251, _T_1252, UInt<1>("h00")) @[Mux.scala 27:72] @@ -96577,15 +96584,15 @@ circuit quasar_wrapper : node _T_1261 = or(_T_1260, _T_1258) @[Mux.scala 27:72] wire _T_1262 : UInt<1> @[Mux.scala 27:72] _T_1262 <= _T_1261 @[Mux.scala 27:72] - node obuf_write_in = mux(ibuf_buf_byp, io.lsu_pkt_r.bits.store, _T_1262) @[lsu_bus_buffer.scala 289:26] - node _T_1263 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 56:118] - node _T_1264 = bits(buf_sideeffect, 0, 0) @[lsu_bus_buffer.scala 56:129] - node _T_1265 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 56:118] - node _T_1266 = bits(buf_sideeffect, 1, 1) @[lsu_bus_buffer.scala 56:129] - node _T_1267 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 56:118] - node _T_1268 = bits(buf_sideeffect, 2, 2) @[lsu_bus_buffer.scala 56:129] - node _T_1269 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 56:118] - node _T_1270 = bits(buf_sideeffect, 3, 3) @[lsu_bus_buffer.scala 56:129] + node obuf_write_in = mux(ibuf_buf_byp, io.lsu_pkt_r.bits.store, _T_1262) @[lsu_bus_buffer.scala 290:26] + node _T_1263 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_1264 = bits(buf_sideeffect, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_1265 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_1266 = bits(buf_sideeffect, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_1267 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_1268 = bits(buf_sideeffect, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_1269 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_1270 = bits(buf_sideeffect, 3, 3) @[lsu_bus_buffer.scala 57:129] node _T_1271 = mux(_T_1263, _T_1264, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1272 = mux(_T_1265, _T_1266, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1273 = mux(_T_1267, _T_1268, UInt<1>("h00")) @[Mux.scala 27:72] @@ -96595,11 +96602,11 @@ circuit quasar_wrapper : node _T_1277 = or(_T_1276, _T_1274) @[Mux.scala 27:72] wire _T_1278 : UInt<1> @[Mux.scala 27:72] _T_1278 <= _T_1277 @[Mux.scala 27:72] - node obuf_sideeffect_in = mux(ibuf_buf_byp, io.is_sideeffects_r, _T_1278) @[lsu_bus_buffer.scala 290:31] - node _T_1279 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:123] - node _T_1280 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:123] - node _T_1281 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:123] - node _T_1282 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:123] + node obuf_sideeffect_in = mux(ibuf_buf_byp, io.is_sideeffects_r, _T_1278) @[lsu_bus_buffer.scala 291:31] + node _T_1279 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1280 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1281 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1282 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] node _T_1283 = mux(_T_1279, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1284 = mux(_T_1280, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1285 = mux(_T_1281, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] @@ -96609,17 +96616,17 @@ circuit quasar_wrapper : node _T_1289 = or(_T_1288, _T_1286) @[Mux.scala 27:72] wire _T_1290 : UInt<32> @[Mux.scala 27:72] _T_1290 <= _T_1289 @[Mux.scala 27:72] - node obuf_addr_in = mux(ibuf_buf_byp, io.lsu_addr_r, _T_1290) @[lsu_bus_buffer.scala 291:25] - wire buf_sz : UInt<2>[4] @[lsu_bus_buffer.scala 292:20] - buf_sz[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 293:10] - buf_sz[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 293:10] - buf_sz[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 293:10] - buf_sz[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 293:10] + node obuf_addr_in = mux(ibuf_buf_byp, io.lsu_addr_r, _T_1290) @[lsu_bus_buffer.scala 292:25] + wire buf_sz : UInt<2>[4] @[lsu_bus_buffer.scala 293:20] + buf_sz[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 294:10] + buf_sz[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 294:10] + buf_sz[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 294:10] + buf_sz[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 294:10] node _T_1291 = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58] - node _T_1292 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:123] - node _T_1293 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:123] - node _T_1294 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:123] - node _T_1295 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:123] + node _T_1292 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1293 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1294 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1295 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] node _T_1296 = mux(_T_1292, buf_sz[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1297 = mux(_T_1293, buf_sz[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1298 = mux(_T_1294, buf_sz[2], UInt<1>("h00")) @[Mux.scala 27:72] @@ -96629,10 +96636,10 @@ circuit quasar_wrapper : node _T_1302 = or(_T_1301, _T_1299) @[Mux.scala 27:72] wire _T_1303 : UInt<2> @[Mux.scala 27:72] _T_1303 <= _T_1302 @[Mux.scala 27:72] - node obuf_sz_in = mux(ibuf_buf_byp, _T_1291, _T_1303) @[lsu_bus_buffer.scala 294:23] + node obuf_sz_in = mux(ibuf_buf_byp, _T_1291, _T_1303) @[lsu_bus_buffer.scala 295:23] wire obuf_merge_en : UInt<1> obuf_merge_en <= UInt<1>("h00") - node obuf_tag0_in = mux(ibuf_buf_byp, WrPtr0_r, CmdPtr0) @[lsu_bus_buffer.scala 297:25] + node obuf_tag0_in = mux(ibuf_buf_byp, WrPtr0_r, CmdPtr0) @[lsu_bus_buffer.scala 298:25] node obuf_tag1_in = mux(ibuf_buf_byp, WrPtr1_r, CmdPtr1) @[lsu_bus_buffer.scala 300:25] wire obuf_cmd_done : UInt<1> obuf_cmd_done <= UInt<1>("h00") @@ -96723,10 +96730,10 @@ circuit quasar_wrapper : node _T_1358 = cat(ldst_byteen_lo_r, UInt<4>("h00")) @[Cat.scala 29:58] node _T_1359 = cat(UInt<4>("h00"), ldst_byteen_lo_r) @[Cat.scala 29:58] node _T_1360 = mux(_T_1357, _T_1358, _T_1359) @[lsu_bus_buffer.scala 323:46] - node _T_1361 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:123] - node _T_1362 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:123] - node _T_1363 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:123] - node _T_1364 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:123] + node _T_1361 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1362 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1363 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1364 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] node _T_1365 = mux(_T_1361, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1366 = mux(_T_1362, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1367 = mux(_T_1363, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] @@ -96738,10 +96745,10 @@ circuit quasar_wrapper : _T_1372 <= _T_1371 @[Mux.scala 27:72] node _T_1373 = bits(_T_1372, 2, 2) @[lsu_bus_buffer.scala 324:36] node _T_1374 = bits(_T_1373, 0, 0) @[lsu_bus_buffer.scala 324:46] - node _T_1375 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:123] - node _T_1376 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:123] - node _T_1377 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:123] - node _T_1378 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:123] + node _T_1375 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1376 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1377 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1378 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] node _T_1379 = mux(_T_1375, buf_byteen[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1380 = mux(_T_1376, buf_byteen[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1381 = mux(_T_1377, buf_byteen[2], UInt<1>("h00")) @[Mux.scala 27:72] @@ -96752,10 +96759,10 @@ circuit quasar_wrapper : wire _T_1386 : UInt<4> @[Mux.scala 27:72] _T_1386 <= _T_1385 @[Mux.scala 27:72] node _T_1387 = cat(_T_1386, UInt<4>("h00")) @[Cat.scala 29:58] - node _T_1388 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:123] - node _T_1389 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:123] - node _T_1390 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:123] - node _T_1391 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:123] + node _T_1388 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1389 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1390 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1391 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] node _T_1392 = mux(_T_1388, buf_byteen[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1393 = mux(_T_1389, buf_byteen[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1394 = mux(_T_1390, buf_byteen[2], UInt<1>("h00")) @[Mux.scala 27:72] @@ -96772,10 +96779,10 @@ circuit quasar_wrapper : node _T_1403 = cat(ldst_byteen_hi_r, UInt<4>("h00")) @[Cat.scala 29:58] node _T_1404 = cat(UInt<4>("h00"), ldst_byteen_hi_r) @[Cat.scala 29:58] node _T_1405 = mux(_T_1402, _T_1403, _T_1404) @[lsu_bus_buffer.scala 325:46] - node _T_1406 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:123] - node _T_1407 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:123] - node _T_1408 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:123] - node _T_1409 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:123] + node _T_1406 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1407 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1408 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1409 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] node _T_1410 = mux(_T_1406, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1411 = mux(_T_1407, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1412 = mux(_T_1408, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] @@ -96787,10 +96794,10 @@ circuit quasar_wrapper : _T_1417 <= _T_1416 @[Mux.scala 27:72] node _T_1418 = bits(_T_1417, 2, 2) @[lsu_bus_buffer.scala 326:36] node _T_1419 = bits(_T_1418, 0, 0) @[lsu_bus_buffer.scala 326:46] - node _T_1420 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:123] - node _T_1421 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:123] - node _T_1422 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:123] - node _T_1423 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:123] + node _T_1420 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1421 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1422 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1423 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] node _T_1424 = mux(_T_1420, buf_byteen[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1425 = mux(_T_1421, buf_byteen[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1426 = mux(_T_1422, buf_byteen[2], UInt<1>("h00")) @[Mux.scala 27:72] @@ -96801,10 +96808,10 @@ circuit quasar_wrapper : wire _T_1431 : UInt<4> @[Mux.scala 27:72] _T_1431 <= _T_1430 @[Mux.scala 27:72] node _T_1432 = cat(_T_1431, UInt<4>("h00")) @[Cat.scala 29:58] - node _T_1433 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:123] - node _T_1434 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:123] - node _T_1435 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:123] - node _T_1436 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:123] + node _T_1433 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1434 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1435 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1436 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] node _T_1437 = mux(_T_1433, buf_byteen[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1438 = mux(_T_1434, buf_byteen[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1439 = mux(_T_1435, buf_byteen[2], UInt<1>("h00")) @[Mux.scala 27:72] @@ -96821,10 +96828,10 @@ circuit quasar_wrapper : node _T_1448 = cat(store_data_lo_r, UInt<32>("h00")) @[Cat.scala 29:58] node _T_1449 = cat(UInt<32>("h00"), store_data_lo_r) @[Cat.scala 29:58] node _T_1450 = mux(_T_1447, _T_1448, _T_1449) @[lsu_bus_buffer.scala 328:44] - node _T_1451 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:123] - node _T_1452 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:123] - node _T_1453 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:123] - node _T_1454 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:123] + node _T_1451 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1452 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1453 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1454 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] node _T_1455 = mux(_T_1451, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1456 = mux(_T_1452, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1457 = mux(_T_1453, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] @@ -96836,10 +96843,10 @@ circuit quasar_wrapper : _T_1462 <= _T_1461 @[Mux.scala 27:72] node _T_1463 = bits(_T_1462, 2, 2) @[lsu_bus_buffer.scala 329:36] node _T_1464 = bits(_T_1463, 0, 0) @[lsu_bus_buffer.scala 329:46] - node _T_1465 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:123] - node _T_1466 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:123] - node _T_1467 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:123] - node _T_1468 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:123] + node _T_1465 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1466 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1467 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1468 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] node _T_1469 = mux(_T_1465, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1470 = mux(_T_1466, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1471 = mux(_T_1467, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] @@ -96850,10 +96857,10 @@ circuit quasar_wrapper : wire _T_1476 : UInt<32> @[Mux.scala 27:72] _T_1476 <= _T_1475 @[Mux.scala 27:72] node _T_1477 = cat(_T_1476, UInt<32>("h00")) @[Cat.scala 29:58] - node _T_1478 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:123] - node _T_1479 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:123] - node _T_1480 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:123] - node _T_1481 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:123] + node _T_1478 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1479 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1480 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1481 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] node _T_1482 = mux(_T_1478, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1483 = mux(_T_1479, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1484 = mux(_T_1480, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] @@ -96870,10 +96877,10 @@ circuit quasar_wrapper : node _T_1493 = cat(store_data_hi_r, UInt<32>("h00")) @[Cat.scala 29:58] node _T_1494 = cat(UInt<32>("h00"), store_data_hi_r) @[Cat.scala 29:58] node _T_1495 = mux(_T_1492, _T_1493, _T_1494) @[lsu_bus_buffer.scala 330:44] - node _T_1496 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:123] - node _T_1497 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:123] - node _T_1498 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:123] - node _T_1499 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:123] + node _T_1496 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1497 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1498 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1499 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] node _T_1500 = mux(_T_1496, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1501 = mux(_T_1497, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1502 = mux(_T_1498, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] @@ -96885,10 +96892,10 @@ circuit quasar_wrapper : _T_1507 <= _T_1506 @[Mux.scala 27:72] node _T_1508 = bits(_T_1507, 2, 2) @[lsu_bus_buffer.scala 331:36] node _T_1509 = bits(_T_1508, 0, 0) @[lsu_bus_buffer.scala 331:46] - node _T_1510 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:123] - node _T_1511 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:123] - node _T_1512 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:123] - node _T_1513 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:123] + node _T_1510 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1511 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1512 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1513 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] node _T_1514 = mux(_T_1510, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1515 = mux(_T_1511, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1516 = mux(_T_1512, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] @@ -96899,10 +96906,10 @@ circuit quasar_wrapper : wire _T_1521 : UInt<32> @[Mux.scala 27:72] _T_1521 <= _T_1520 @[Mux.scala 27:72] node _T_1522 = cat(_T_1521, UInt<32>("h00")) @[Cat.scala 29:58] - node _T_1523 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:123] - node _T_1524 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:123] - node _T_1525 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:123] - node _T_1526 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:123] + node _T_1523 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1524 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1525 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1526 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] node _T_1527 = mux(_T_1523, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1528 = mux(_T_1524, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1529 = mux(_T_1525, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] @@ -97009,10 +97016,10 @@ circuit quasar_wrapper : node _T_1621 = neq(CmdPtr0, CmdPtr1) @[lsu_bus_buffer.scala 337:30] node _T_1622 = and(_T_1621, found_cmdptr0) @[lsu_bus_buffer.scala 337:43] node _T_1623 = and(_T_1622, found_cmdptr1) @[lsu_bus_buffer.scala 337:59] - node _T_1624 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:123] - node _T_1625 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:123] - node _T_1626 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:123] - node _T_1627 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:123] + node _T_1624 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1625 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1626 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1627 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] node _T_1628 = mux(_T_1624, buf_state[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1629 = mux(_T_1625, buf_state[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1630 = mux(_T_1626, buf_state[2], UInt<1>("h00")) @[Mux.scala 27:72] @@ -97024,10 +97031,10 @@ circuit quasar_wrapper : _T_1635 <= _T_1634 @[Mux.scala 27:72] node _T_1636 = eq(_T_1635, UInt<3>("h02")) @[lsu_bus_buffer.scala 337:107] node _T_1637 = and(_T_1623, _T_1636) @[lsu_bus_buffer.scala 337:75] - node _T_1638 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:123] - node _T_1639 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:123] - node _T_1640 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:123] - node _T_1641 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:123] + node _T_1638 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1639 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1640 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1641 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] node _T_1642 = mux(_T_1638, buf_state[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1643 = mux(_T_1639, buf_state[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1644 = mux(_T_1640, buf_state[2], UInt<1>("h00")) @[Mux.scala 27:72] @@ -97042,14 +97049,14 @@ circuit quasar_wrapper : node _T_1652 = cat(buf_cmd_state_bus_en[3], buf_cmd_state_bus_en[2]) @[Cat.scala 29:58] node _T_1653 = cat(_T_1652, buf_cmd_state_bus_en[1]) @[Cat.scala 29:58] node _T_1654 = cat(_T_1653, buf_cmd_state_bus_en[0]) @[Cat.scala 29:58] - node _T_1655 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 56:118] - node _T_1656 = bits(_T_1654, 0, 0) @[lsu_bus_buffer.scala 56:129] - node _T_1657 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 56:118] - node _T_1658 = bits(_T_1654, 1, 1) @[lsu_bus_buffer.scala 56:129] - node _T_1659 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 56:118] - node _T_1660 = bits(_T_1654, 2, 2) @[lsu_bus_buffer.scala 56:129] - node _T_1661 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 56:118] - node _T_1662 = bits(_T_1654, 3, 3) @[lsu_bus_buffer.scala 56:129] + node _T_1655 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_1656 = bits(_T_1654, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_1657 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_1658 = bits(_T_1654, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_1659 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_1660 = bits(_T_1654, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_1661 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_1662 = bits(_T_1654, 3, 3) @[lsu_bus_buffer.scala 57:129] node _T_1663 = mux(_T_1655, _T_1656, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1664 = mux(_T_1657, _T_1658, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1665 = mux(_T_1659, _T_1660, UInt<1>("h00")) @[Mux.scala 27:72] @@ -97061,14 +97068,14 @@ circuit quasar_wrapper : _T_1670 <= _T_1669 @[Mux.scala 27:72] node _T_1671 = eq(_T_1670, UInt<1>("h00")) @[lsu_bus_buffer.scala 338:5] node _T_1672 = and(_T_1651, _T_1671) @[lsu_bus_buffer.scala 337:161] - node _T_1673 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 56:118] - node _T_1674 = bits(buf_sideeffect, 0, 0) @[lsu_bus_buffer.scala 56:129] - node _T_1675 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 56:118] - node _T_1676 = bits(buf_sideeffect, 1, 1) @[lsu_bus_buffer.scala 56:129] - node _T_1677 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 56:118] - node _T_1678 = bits(buf_sideeffect, 2, 2) @[lsu_bus_buffer.scala 56:129] - node _T_1679 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 56:118] - node _T_1680 = bits(buf_sideeffect, 3, 3) @[lsu_bus_buffer.scala 56:129] + node _T_1673 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_1674 = bits(buf_sideeffect, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_1675 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_1676 = bits(buf_sideeffect, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_1677 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_1678 = bits(buf_sideeffect, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_1679 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_1680 = bits(buf_sideeffect, 3, 3) @[lsu_bus_buffer.scala 57:129] node _T_1681 = mux(_T_1673, _T_1674, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1682 = mux(_T_1675, _T_1676, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1683 = mux(_T_1677, _T_1678, UInt<1>("h00")) @[Mux.scala 27:72] @@ -97080,14 +97087,14 @@ circuit quasar_wrapper : _T_1688 <= _T_1687 @[Mux.scala 27:72] node _T_1689 = eq(_T_1688, UInt<1>("h00")) @[lsu_bus_buffer.scala 338:87] node _T_1690 = and(_T_1672, _T_1689) @[lsu_bus_buffer.scala 338:85] - node _T_1691 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 56:118] - node _T_1692 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 56:129] - node _T_1693 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 56:118] - node _T_1694 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 56:129] - node _T_1695 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 56:118] - node _T_1696 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 56:129] - node _T_1697 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 56:118] - node _T_1698 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 56:129] + node _T_1691 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_1692 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_1693 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_1694 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_1695 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_1696 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_1697 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_1698 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 57:129] node _T_1699 = mux(_T_1691, _T_1692, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1700 = mux(_T_1693, _T_1694, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1701 = mux(_T_1695, _T_1696, UInt<1>("h00")) @[Mux.scala 27:72] @@ -97097,14 +97104,14 @@ circuit quasar_wrapper : node _T_1705 = or(_T_1704, _T_1702) @[Mux.scala 27:72] wire _T_1706 : UInt<1> @[Mux.scala 27:72] _T_1706 <= _T_1705 @[Mux.scala 27:72] - node _T_1707 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 56:118] - node _T_1708 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 56:129] - node _T_1709 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 56:118] - node _T_1710 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 56:129] - node _T_1711 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 56:118] - node _T_1712 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 56:129] - node _T_1713 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 56:118] - node _T_1714 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 56:129] + node _T_1707 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_1708 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_1709 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_1710 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_1711 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_1712 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_1713 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_1714 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 57:129] node _T_1715 = mux(_T_1707, _T_1708, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1716 = mux(_T_1709, _T_1710, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1717 = mux(_T_1711, _T_1712, UInt<1>("h00")) @[Mux.scala 27:72] @@ -97115,10 +97122,10 @@ circuit quasar_wrapper : wire _T_1722 : UInt<1> @[Mux.scala 27:72] _T_1722 <= _T_1721 @[Mux.scala 27:72] node _T_1723 = and(_T_1706, _T_1722) @[lsu_bus_buffer.scala 339:36] - node _T_1724 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:123] - node _T_1725 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:123] - node _T_1726 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:123] - node _T_1727 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:123] + node _T_1724 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1725 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1726 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1727 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] node _T_1728 = mux(_T_1724, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1729 = mux(_T_1725, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1730 = mux(_T_1726, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] @@ -97129,10 +97136,10 @@ circuit quasar_wrapper : wire _T_1735 : UInt<32> @[Mux.scala 27:72] _T_1735 <= _T_1734 @[Mux.scala 27:72] node _T_1736 = bits(_T_1735, 31, 3) @[lsu_bus_buffer.scala 340:35] - node _T_1737 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:123] - node _T_1738 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:123] - node _T_1739 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:123] - node _T_1740 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:123] + node _T_1737 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_1738 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_1739 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_1740 = eq(CmdPtr1, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] node _T_1741 = mux(_T_1737, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1742 = mux(_T_1738, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1743 = mux(_T_1739, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] @@ -97149,14 +97156,14 @@ circuit quasar_wrapper : node _T_1753 = and(_T_1751, _T_1752) @[lsu_bus_buffer.scala 340:79] node _T_1754 = eq(UInt<1>("h00"), UInt<1>("h00")) @[lsu_bus_buffer.scala 340:107] node _T_1755 = and(_T_1753, _T_1754) @[lsu_bus_buffer.scala 340:105] - node _T_1756 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 56:118] - node _T_1757 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 56:129] - node _T_1758 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 56:118] - node _T_1759 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 56:129] - node _T_1760 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 56:118] - node _T_1761 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 56:129] - node _T_1762 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 56:118] - node _T_1763 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 56:129] + node _T_1756 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_1757 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_1758 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_1759 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_1760 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_1761 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_1762 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_1763 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 57:129] node _T_1764 = mux(_T_1756, _T_1757, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1765 = mux(_T_1758, _T_1759, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1766 = mux(_T_1760, _T_1761, UInt<1>("h00")) @[Mux.scala 27:72] @@ -97170,14 +97177,14 @@ circuit quasar_wrapper : node _T_1773 = cat(buf_dual[3], buf_dual[2]) @[Cat.scala 29:58] node _T_1774 = cat(_T_1773, buf_dual[1]) @[Cat.scala 29:58] node _T_1775 = cat(_T_1774, buf_dual[0]) @[Cat.scala 29:58] - node _T_1776 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 56:118] - node _T_1777 = bits(_T_1775, 0, 0) @[lsu_bus_buffer.scala 56:129] - node _T_1778 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 56:118] - node _T_1779 = bits(_T_1775, 1, 1) @[lsu_bus_buffer.scala 56:129] - node _T_1780 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 56:118] - node _T_1781 = bits(_T_1775, 2, 2) @[lsu_bus_buffer.scala 56:129] - node _T_1782 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 56:118] - node _T_1783 = bits(_T_1775, 3, 3) @[lsu_bus_buffer.scala 56:129] + node _T_1776 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_1777 = bits(_T_1775, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_1778 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_1779 = bits(_T_1775, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_1780 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_1781 = bits(_T_1775, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_1782 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_1783 = bits(_T_1775, 3, 3) @[lsu_bus_buffer.scala 57:129] node _T_1784 = mux(_T_1776, _T_1777, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1785 = mux(_T_1778, _T_1779, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1786 = mux(_T_1780, _T_1781, UInt<1>("h00")) @[Mux.scala 27:72] @@ -97191,14 +97198,14 @@ circuit quasar_wrapper : node _T_1793 = cat(buf_dualhi[3], buf_dualhi[2]) @[Cat.scala 29:58] node _T_1794 = cat(_T_1793, buf_dualhi[1]) @[Cat.scala 29:58] node _T_1795 = cat(_T_1794, buf_dualhi[0]) @[Cat.scala 29:58] - node _T_1796 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 56:118] - node _T_1797 = bits(_T_1795, 0, 0) @[lsu_bus_buffer.scala 56:129] - node _T_1798 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 56:118] - node _T_1799 = bits(_T_1795, 1, 1) @[lsu_bus_buffer.scala 56:129] - node _T_1800 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 56:118] - node _T_1801 = bits(_T_1795, 2, 2) @[lsu_bus_buffer.scala 56:129] - node _T_1802 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 56:118] - node _T_1803 = bits(_T_1795, 3, 3) @[lsu_bus_buffer.scala 56:129] + node _T_1796 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_1797 = bits(_T_1795, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_1798 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_1799 = bits(_T_1795, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_1800 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_1801 = bits(_T_1795, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_1802 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_1803 = bits(_T_1795, 3, 3) @[lsu_bus_buffer.scala 57:129] node _T_1804 = mux(_T_1796, _T_1797, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1805 = mux(_T_1798, _T_1799, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1806 = mux(_T_1800, _T_1801, UInt<1>("h00")) @[Mux.scala 27:72] @@ -97213,14 +97220,14 @@ circuit quasar_wrapper : node _T_1814 = cat(buf_samedw[3], buf_samedw[2]) @[Cat.scala 29:58] node _T_1815 = cat(_T_1814, buf_samedw[1]) @[Cat.scala 29:58] node _T_1816 = cat(_T_1815, buf_samedw[0]) @[Cat.scala 29:58] - node _T_1817 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 56:118] - node _T_1818 = bits(_T_1816, 0, 0) @[lsu_bus_buffer.scala 56:129] - node _T_1819 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 56:118] - node _T_1820 = bits(_T_1816, 1, 1) @[lsu_bus_buffer.scala 56:129] - node _T_1821 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 56:118] - node _T_1822 = bits(_T_1816, 2, 2) @[lsu_bus_buffer.scala 56:129] - node _T_1823 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 56:118] - node _T_1824 = bits(_T_1816, 3, 3) @[lsu_bus_buffer.scala 56:129] + node _T_1817 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_1818 = bits(_T_1816, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_1819 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_1820 = bits(_T_1816, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_1821 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_1822 = bits(_T_1816, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_1823 = eq(CmdPtr0, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_1824 = bits(_T_1816, 3, 3) @[lsu_bus_buffer.scala 57:129] node _T_1825 = mux(_T_1817, _T_1818, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1826 = mux(_T_1819, _T_1820, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1827 = mux(_T_1821, _T_1822, UInt<1>("h00")) @[Mux.scala 27:72] @@ -99205,14 +99212,14 @@ circuit quasar_wrapper : node _T_3607 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 467:97] node _T_3608 = eq(_T_3607, UInt<1>("h00")) @[lsu_bus_buffer.scala 467:87] node _T_3609 = and(_T_3606, _T_3608) @[lsu_bus_buffer.scala 467:85] - node _T_3610 = eq(buf_dualtag[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 56:118] - node _T_3611 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 56:129] - node _T_3612 = eq(buf_dualtag[0], UInt<1>("h01")) @[lsu_bus_buffer.scala 56:118] - node _T_3613 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 56:129] - node _T_3614 = eq(buf_dualtag[0], UInt<2>("h02")) @[lsu_bus_buffer.scala 56:118] - node _T_3615 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 56:129] - node _T_3616 = eq(buf_dualtag[0], UInt<2>("h03")) @[lsu_bus_buffer.scala 56:118] - node _T_3617 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 56:129] + node _T_3610 = eq(buf_dualtag[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_3611 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_3612 = eq(buf_dualtag[0], UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_3613 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_3614 = eq(buf_dualtag[0], UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_3615 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_3616 = eq(buf_dualtag[0], UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_3617 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 57:129] node _T_3618 = mux(_T_3610, _T_3611, UInt<1>("h00")) @[Mux.scala 27:72] node _T_3619 = mux(_T_3612, _T_3613, UInt<1>("h00")) @[Mux.scala 27:72] node _T_3620 = mux(_T_3614, _T_3615, UInt<1>("h00")) @[Mux.scala 27:72] @@ -99481,14 +99488,14 @@ circuit quasar_wrapper : node _T_3800 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 467:97] node _T_3801 = eq(_T_3800, UInt<1>("h00")) @[lsu_bus_buffer.scala 467:87] node _T_3802 = and(_T_3799, _T_3801) @[lsu_bus_buffer.scala 467:85] - node _T_3803 = eq(buf_dualtag[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 56:118] - node _T_3804 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 56:129] - node _T_3805 = eq(buf_dualtag[1], UInt<1>("h01")) @[lsu_bus_buffer.scala 56:118] - node _T_3806 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 56:129] - node _T_3807 = eq(buf_dualtag[1], UInt<2>("h02")) @[lsu_bus_buffer.scala 56:118] - node _T_3808 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 56:129] - node _T_3809 = eq(buf_dualtag[1], UInt<2>("h03")) @[lsu_bus_buffer.scala 56:118] - node _T_3810 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 56:129] + node _T_3803 = eq(buf_dualtag[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_3804 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_3805 = eq(buf_dualtag[1], UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_3806 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_3807 = eq(buf_dualtag[1], UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_3808 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_3809 = eq(buf_dualtag[1], UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_3810 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 57:129] node _T_3811 = mux(_T_3803, _T_3804, UInt<1>("h00")) @[Mux.scala 27:72] node _T_3812 = mux(_T_3805, _T_3806, UInt<1>("h00")) @[Mux.scala 27:72] node _T_3813 = mux(_T_3807, _T_3808, UInt<1>("h00")) @[Mux.scala 27:72] @@ -99757,14 +99764,14 @@ circuit quasar_wrapper : node _T_3993 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 467:97] node _T_3994 = eq(_T_3993, UInt<1>("h00")) @[lsu_bus_buffer.scala 467:87] node _T_3995 = and(_T_3992, _T_3994) @[lsu_bus_buffer.scala 467:85] - node _T_3996 = eq(buf_dualtag[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 56:118] - node _T_3997 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 56:129] - node _T_3998 = eq(buf_dualtag[2], UInt<1>("h01")) @[lsu_bus_buffer.scala 56:118] - node _T_3999 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 56:129] - node _T_4000 = eq(buf_dualtag[2], UInt<2>("h02")) @[lsu_bus_buffer.scala 56:118] - node _T_4001 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 56:129] - node _T_4002 = eq(buf_dualtag[2], UInt<2>("h03")) @[lsu_bus_buffer.scala 56:118] - node _T_4003 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 56:129] + node _T_3996 = eq(buf_dualtag[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_3997 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_3998 = eq(buf_dualtag[2], UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_3999 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_4000 = eq(buf_dualtag[2], UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_4001 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_4002 = eq(buf_dualtag[2], UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_4003 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 57:129] node _T_4004 = mux(_T_3996, _T_3997, UInt<1>("h00")) @[Mux.scala 27:72] node _T_4005 = mux(_T_3998, _T_3999, UInt<1>("h00")) @[Mux.scala 27:72] node _T_4006 = mux(_T_4000, _T_4001, UInt<1>("h00")) @[Mux.scala 27:72] @@ -100033,14 +100040,14 @@ circuit quasar_wrapper : node _T_4186 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 467:97] node _T_4187 = eq(_T_4186, UInt<1>("h00")) @[lsu_bus_buffer.scala 467:87] node _T_4188 = and(_T_4185, _T_4187) @[lsu_bus_buffer.scala 467:85] - node _T_4189 = eq(buf_dualtag[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 56:118] - node _T_4190 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 56:129] - node _T_4191 = eq(buf_dualtag[3], UInt<1>("h01")) @[lsu_bus_buffer.scala 56:118] - node _T_4192 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 56:129] - node _T_4193 = eq(buf_dualtag[3], UInt<2>("h02")) @[lsu_bus_buffer.scala 56:118] - node _T_4194 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 56:129] - node _T_4195 = eq(buf_dualtag[3], UInt<2>("h03")) @[lsu_bus_buffer.scala 56:118] - node _T_4196 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 56:129] + node _T_4189 = eq(buf_dualtag[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_4190 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_4191 = eq(buf_dualtag[3], UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_4192 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_4193 = eq(buf_dualtag[3], UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_4194 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_4195 = eq(buf_dualtag[3], UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_4196 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 57:129] node _T_4197 = mux(_T_4189, _T_4190, UInt<1>("h00")) @[Mux.scala 27:72] node _T_4198 = mux(_T_4191, _T_4192, UInt<1>("h00")) @[Mux.scala 27:72] node _T_4199 = mux(_T_4193, _T_4194, UInt<1>("h00")) @[Mux.scala 27:72] @@ -100776,10 +100783,10 @@ circuit quasar_wrapper : node _T_4682 = or(_T_4681, _T_4679) @[Mux.scala 27:72] wire lsu_nonblock_load_data_hi : UInt<32> @[Mux.scala 27:72] lsu_nonblock_load_data_hi <= _T_4682 @[Mux.scala 27:72] - node _T_4683 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:123] - node _T_4684 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:123] - node _T_4685 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:123] - node _T_4686 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:123] + node _T_4683 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_4684 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_4685 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_4686 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] node _T_4687 = mux(_T_4683, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_4688 = mux(_T_4684, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_4689 = mux(_T_4685, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] @@ -100790,10 +100797,10 @@ circuit quasar_wrapper : wire _T_4694 : UInt<32> @[Mux.scala 27:72] _T_4694 <= _T_4693 @[Mux.scala 27:72] node lsu_nonblock_addr_offset = bits(_T_4694, 1, 0) @[lsu_bus_buffer.scala 539:96] - node _T_4695 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:123] - node _T_4696 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:123] - node _T_4697 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:123] - node _T_4698 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:123] + node _T_4695 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] + node _T_4696 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] + node _T_4697 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] + node _T_4698 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 58:123] node _T_4699 = mux(_T_4695, buf_sz[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_4700 = mux(_T_4696, buf_sz[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_4701 = mux(_T_4697, buf_sz[2], UInt<1>("h00")) @[Mux.scala 27:72] @@ -100803,14 +100810,14 @@ circuit quasar_wrapper : node _T_4705 = or(_T_4704, _T_4702) @[Mux.scala 27:72] wire lsu_nonblock_sz : UInt<2> @[Mux.scala 27:72] lsu_nonblock_sz <= _T_4705 @[Mux.scala 27:72] - node _T_4706 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 56:118] - node _T_4707 = bits(buf_unsign, 0, 0) @[lsu_bus_buffer.scala 56:129] - node _T_4708 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 56:118] - node _T_4709 = bits(buf_unsign, 1, 1) @[lsu_bus_buffer.scala 56:129] - node _T_4710 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 56:118] - node _T_4711 = bits(buf_unsign, 2, 2) @[lsu_bus_buffer.scala 56:129] - node _T_4712 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 56:118] - node _T_4713 = bits(buf_unsign, 3, 3) @[lsu_bus_buffer.scala 56:129] + node _T_4706 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_4707 = bits(buf_unsign, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_4708 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_4709 = bits(buf_unsign, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_4710 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_4711 = bits(buf_unsign, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_4712 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_4713 = bits(buf_unsign, 3, 3) @[lsu_bus_buffer.scala 57:129] node _T_4714 = mux(_T_4706, _T_4707, UInt<1>("h00")) @[Mux.scala 27:72] node _T_4715 = mux(_T_4708, _T_4709, UInt<1>("h00")) @[Mux.scala 27:72] node _T_4716 = mux(_T_4710, _T_4711, UInt<1>("h00")) @[Mux.scala 27:72] @@ -100823,14 +100830,14 @@ circuit quasar_wrapper : node _T_4721 = cat(buf_dual[3], buf_dual[2]) @[Cat.scala 29:58] node _T_4722 = cat(_T_4721, buf_dual[1]) @[Cat.scala 29:58] node _T_4723 = cat(_T_4722, buf_dual[0]) @[Cat.scala 29:58] - node _T_4724 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 56:118] - node _T_4725 = bits(_T_4723, 0, 0) @[lsu_bus_buffer.scala 56:129] - node _T_4726 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 56:118] - node _T_4727 = bits(_T_4723, 1, 1) @[lsu_bus_buffer.scala 56:129] - node _T_4728 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 56:118] - node _T_4729 = bits(_T_4723, 2, 2) @[lsu_bus_buffer.scala 56:129] - node _T_4730 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 56:118] - node _T_4731 = bits(_T_4723, 3, 3) @[lsu_bus_buffer.scala 56:129] + node _T_4724 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] + node _T_4725 = bits(_T_4723, 0, 0) @[lsu_bus_buffer.scala 57:129] + node _T_4726 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] + node _T_4727 = bits(_T_4723, 1, 1) @[lsu_bus_buffer.scala 57:129] + node _T_4728 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 57:118] + node _T_4729 = bits(_T_4723, 2, 2) @[lsu_bus_buffer.scala 57:129] + node _T_4730 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 57:118] + node _T_4731 = bits(_T_4723, 3, 3) @[lsu_bus_buffer.scala 57:129] node _T_4732 = mux(_T_4724, _T_4725, UInt<1>("h00")) @[Mux.scala 27:72] node _T_4733 = mux(_T_4726, _T_4727, UInt<1>("h00")) @[Mux.scala 27:72] node _T_4734 = mux(_T_4728, _T_4729, UInt<1>("h00")) @[Mux.scala 27:72] @@ -101250,132 +101257,132 @@ circuit quasar_wrapper : ld_full_hit_lo_m <= UInt<1>("h01") wire ld_full_hit_m : UInt<1> ld_full_hit_m <= UInt<1>("h00") - inst bus_buffer of lsu_bus_buffer @[lsu_bus_intf.scala 101:39] + inst bus_buffer of lsu_bus_buffer @[lsu_bus_intf.scala 100:39] bus_buffer.clock <= clock bus_buffer.reset <= reset - bus_buffer.io.scan_mode <= io.scan_mode @[lsu_bus_intf.scala 103:29] - io.tlu_busbuff.lsu_imprecise_error_addr_any <= bus_buffer.io.tlu_busbuff.lsu_imprecise_error_addr_any @[lsu_bus_intf.scala 104:18] - io.tlu_busbuff.lsu_imprecise_error_store_any <= bus_buffer.io.tlu_busbuff.lsu_imprecise_error_store_any @[lsu_bus_intf.scala 104:18] - io.tlu_busbuff.lsu_imprecise_error_load_any <= bus_buffer.io.tlu_busbuff.lsu_imprecise_error_load_any @[lsu_bus_intf.scala 104:18] - bus_buffer.io.tlu_busbuff.dec_tlu_sideeffect_posted_disable <= io.tlu_busbuff.dec_tlu_sideeffect_posted_disable @[lsu_bus_intf.scala 104:18] - bus_buffer.io.tlu_busbuff.dec_tlu_wb_coalescing_disable <= io.tlu_busbuff.dec_tlu_wb_coalescing_disable @[lsu_bus_intf.scala 104:18] - bus_buffer.io.tlu_busbuff.dec_tlu_external_ldfwd_disable <= io.tlu_busbuff.dec_tlu_external_ldfwd_disable @[lsu_bus_intf.scala 104:18] - io.tlu_busbuff.lsu_pmu_bus_busy <= bus_buffer.io.tlu_busbuff.lsu_pmu_bus_busy @[lsu_bus_intf.scala 104:18] - io.tlu_busbuff.lsu_pmu_bus_error <= bus_buffer.io.tlu_busbuff.lsu_pmu_bus_error @[lsu_bus_intf.scala 104:18] - io.tlu_busbuff.lsu_pmu_bus_misaligned <= bus_buffer.io.tlu_busbuff.lsu_pmu_bus_misaligned @[lsu_bus_intf.scala 104:18] - io.tlu_busbuff.lsu_pmu_bus_trxn <= bus_buffer.io.tlu_busbuff.lsu_pmu_bus_trxn @[lsu_bus_intf.scala 104:18] - bus_buffer.io.dec_tlu_force_halt <= io.dec_tlu_force_halt @[lsu_bus_intf.scala 106:51] - bus_buffer.io.lsu_c2_r_clk <= io.lsu_c2_r_clk @[lsu_bus_intf.scala 107:51] - bus_buffer.io.lsu_bus_ibuf_c1_clk <= io.lsu_bus_ibuf_c1_clk @[lsu_bus_intf.scala 108:51] - bus_buffer.io.lsu_bus_obuf_c1_clk <= io.lsu_bus_obuf_c1_clk @[lsu_bus_intf.scala 109:51] - bus_buffer.io.lsu_bus_buf_c1_clk <= io.lsu_bus_buf_c1_clk @[lsu_bus_intf.scala 110:51] - bus_buffer.io.lsu_free_c2_clk <= io.lsu_free_c2_clk @[lsu_bus_intf.scala 111:51] - bus_buffer.io.lsu_busm_clk <= io.lsu_busm_clk @[lsu_bus_intf.scala 112:51] - bus_buffer.io.dec_lsu_valid_raw_d <= io.dec_lsu_valid_raw_d @[lsu_bus_intf.scala 113:51] - bus_buffer.io.lsu_pkt_m.bits.store_data_bypass_m <= io.lsu_pkt_m.bits.store_data_bypass_m @[lsu_bus_intf.scala 116:27] - bus_buffer.io.lsu_pkt_m.bits.load_ldst_bypass_d <= io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu_bus_intf.scala 116:27] - bus_buffer.io.lsu_pkt_m.bits.store_data_bypass_d <= io.lsu_pkt_m.bits.store_data_bypass_d @[lsu_bus_intf.scala 116:27] - bus_buffer.io.lsu_pkt_m.bits.dma <= io.lsu_pkt_m.bits.dma @[lsu_bus_intf.scala 116:27] - bus_buffer.io.lsu_pkt_m.bits.unsign <= io.lsu_pkt_m.bits.unsign @[lsu_bus_intf.scala 116:27] - bus_buffer.io.lsu_pkt_m.bits.store <= io.lsu_pkt_m.bits.store @[lsu_bus_intf.scala 116:27] - bus_buffer.io.lsu_pkt_m.bits.load <= io.lsu_pkt_m.bits.load @[lsu_bus_intf.scala 116:27] - bus_buffer.io.lsu_pkt_m.bits.dword <= io.lsu_pkt_m.bits.dword @[lsu_bus_intf.scala 116:27] - bus_buffer.io.lsu_pkt_m.bits.word <= io.lsu_pkt_m.bits.word @[lsu_bus_intf.scala 116:27] - bus_buffer.io.lsu_pkt_m.bits.half <= io.lsu_pkt_m.bits.half @[lsu_bus_intf.scala 116:27] - bus_buffer.io.lsu_pkt_m.bits.by <= io.lsu_pkt_m.bits.by @[lsu_bus_intf.scala 116:27] - bus_buffer.io.lsu_pkt_m.bits.fast_int <= io.lsu_pkt_m.bits.fast_int @[lsu_bus_intf.scala 116:27] - bus_buffer.io.lsu_pkt_m.valid <= io.lsu_pkt_m.valid @[lsu_bus_intf.scala 116:27] - bus_buffer.io.lsu_pkt_r.bits.store_data_bypass_m <= io.lsu_pkt_r.bits.store_data_bypass_m @[lsu_bus_intf.scala 117:27] - bus_buffer.io.lsu_pkt_r.bits.load_ldst_bypass_d <= io.lsu_pkt_r.bits.load_ldst_bypass_d @[lsu_bus_intf.scala 117:27] - bus_buffer.io.lsu_pkt_r.bits.store_data_bypass_d <= io.lsu_pkt_r.bits.store_data_bypass_d @[lsu_bus_intf.scala 117:27] - bus_buffer.io.lsu_pkt_r.bits.dma <= io.lsu_pkt_r.bits.dma @[lsu_bus_intf.scala 117:27] - bus_buffer.io.lsu_pkt_r.bits.unsign <= io.lsu_pkt_r.bits.unsign @[lsu_bus_intf.scala 117:27] - bus_buffer.io.lsu_pkt_r.bits.store <= io.lsu_pkt_r.bits.store @[lsu_bus_intf.scala 117:27] - bus_buffer.io.lsu_pkt_r.bits.load <= io.lsu_pkt_r.bits.load @[lsu_bus_intf.scala 117:27] - bus_buffer.io.lsu_pkt_r.bits.dword <= io.lsu_pkt_r.bits.dword @[lsu_bus_intf.scala 117:27] - bus_buffer.io.lsu_pkt_r.bits.word <= io.lsu_pkt_r.bits.word @[lsu_bus_intf.scala 117:27] - bus_buffer.io.lsu_pkt_r.bits.half <= io.lsu_pkt_r.bits.half @[lsu_bus_intf.scala 117:27] - bus_buffer.io.lsu_pkt_r.bits.by <= io.lsu_pkt_r.bits.by @[lsu_bus_intf.scala 117:27] - bus_buffer.io.lsu_pkt_r.bits.fast_int <= io.lsu_pkt_r.bits.fast_int @[lsu_bus_intf.scala 117:27] - bus_buffer.io.lsu_pkt_r.valid <= io.lsu_pkt_r.valid @[lsu_bus_intf.scala 117:27] - bus_buffer.io.lsu_addr_m <= io.lsu_addr_m @[lsu_bus_intf.scala 120:51] - bus_buffer.io.end_addr_m <= io.end_addr_m @[lsu_bus_intf.scala 121:51] - bus_buffer.io.lsu_addr_r <= io.lsu_addr_r @[lsu_bus_intf.scala 122:51] - bus_buffer.io.end_addr_r <= io.end_addr_r @[lsu_bus_intf.scala 123:51] - bus_buffer.io.store_data_r <= io.store_data_r @[lsu_bus_intf.scala 124:51] - bus_buffer.io.lsu_busreq_m <= io.lsu_busreq_m @[lsu_bus_intf.scala 126:51] - bus_buffer.io.flush_m_up <= io.flush_m_up @[lsu_bus_intf.scala 127:51] - bus_buffer.io.flush_r <= io.flush_r @[lsu_bus_intf.scala 128:51] - bus_buffer.io.lsu_commit_r <= io.lsu_commit_r @[lsu_bus_intf.scala 129:51] - bus_buffer.io.lsu_axi.r.bits.last <= io.axi.r.bits.last @[lsu_bus_intf.scala 130:43] - bus_buffer.io.lsu_axi.r.bits.resp <= io.axi.r.bits.resp @[lsu_bus_intf.scala 130:43] - bus_buffer.io.lsu_axi.r.bits.data <= io.axi.r.bits.data @[lsu_bus_intf.scala 130:43] - bus_buffer.io.lsu_axi.r.bits.id <= io.axi.r.bits.id @[lsu_bus_intf.scala 130:43] - bus_buffer.io.lsu_axi.r.valid <= io.axi.r.valid @[lsu_bus_intf.scala 130:43] - io.axi.r.ready <= bus_buffer.io.lsu_axi.r.ready @[lsu_bus_intf.scala 130:43] - io.axi.ar.bits.qos <= bus_buffer.io.lsu_axi.ar.bits.qos @[lsu_bus_intf.scala 130:43] - io.axi.ar.bits.prot <= bus_buffer.io.lsu_axi.ar.bits.prot @[lsu_bus_intf.scala 130:43] - io.axi.ar.bits.cache <= bus_buffer.io.lsu_axi.ar.bits.cache @[lsu_bus_intf.scala 130:43] - io.axi.ar.bits.lock <= bus_buffer.io.lsu_axi.ar.bits.lock @[lsu_bus_intf.scala 130:43] - io.axi.ar.bits.burst <= bus_buffer.io.lsu_axi.ar.bits.burst @[lsu_bus_intf.scala 130:43] - io.axi.ar.bits.size <= bus_buffer.io.lsu_axi.ar.bits.size @[lsu_bus_intf.scala 130:43] - io.axi.ar.bits.len <= bus_buffer.io.lsu_axi.ar.bits.len @[lsu_bus_intf.scala 130:43] - io.axi.ar.bits.region <= bus_buffer.io.lsu_axi.ar.bits.region @[lsu_bus_intf.scala 130:43] - io.axi.ar.bits.addr <= bus_buffer.io.lsu_axi.ar.bits.addr @[lsu_bus_intf.scala 130:43] - io.axi.ar.bits.id <= bus_buffer.io.lsu_axi.ar.bits.id @[lsu_bus_intf.scala 130:43] - io.axi.ar.valid <= bus_buffer.io.lsu_axi.ar.valid @[lsu_bus_intf.scala 130:43] - bus_buffer.io.lsu_axi.ar.ready <= io.axi.ar.ready @[lsu_bus_intf.scala 130:43] - bus_buffer.io.lsu_axi.b.bits.id <= io.axi.b.bits.id @[lsu_bus_intf.scala 130:43] - bus_buffer.io.lsu_axi.b.bits.resp <= io.axi.b.bits.resp @[lsu_bus_intf.scala 130:43] - bus_buffer.io.lsu_axi.b.valid <= io.axi.b.valid @[lsu_bus_intf.scala 130:43] - io.axi.b.ready <= bus_buffer.io.lsu_axi.b.ready @[lsu_bus_intf.scala 130:43] - io.axi.w.bits.last <= bus_buffer.io.lsu_axi.w.bits.last @[lsu_bus_intf.scala 130:43] - io.axi.w.bits.strb <= bus_buffer.io.lsu_axi.w.bits.strb @[lsu_bus_intf.scala 130:43] - io.axi.w.bits.data <= bus_buffer.io.lsu_axi.w.bits.data @[lsu_bus_intf.scala 130:43] - io.axi.w.valid <= bus_buffer.io.lsu_axi.w.valid @[lsu_bus_intf.scala 130:43] - bus_buffer.io.lsu_axi.w.ready <= io.axi.w.ready @[lsu_bus_intf.scala 130:43] - io.axi.aw.bits.qos <= bus_buffer.io.lsu_axi.aw.bits.qos @[lsu_bus_intf.scala 130:43] - io.axi.aw.bits.prot <= bus_buffer.io.lsu_axi.aw.bits.prot @[lsu_bus_intf.scala 130:43] - io.axi.aw.bits.cache <= bus_buffer.io.lsu_axi.aw.bits.cache @[lsu_bus_intf.scala 130:43] - io.axi.aw.bits.lock <= bus_buffer.io.lsu_axi.aw.bits.lock @[lsu_bus_intf.scala 130:43] - io.axi.aw.bits.burst <= bus_buffer.io.lsu_axi.aw.bits.burst @[lsu_bus_intf.scala 130:43] - io.axi.aw.bits.size <= bus_buffer.io.lsu_axi.aw.bits.size @[lsu_bus_intf.scala 130:43] - io.axi.aw.bits.len <= bus_buffer.io.lsu_axi.aw.bits.len @[lsu_bus_intf.scala 130:43] - io.axi.aw.bits.region <= bus_buffer.io.lsu_axi.aw.bits.region @[lsu_bus_intf.scala 130:43] - io.axi.aw.bits.addr <= bus_buffer.io.lsu_axi.aw.bits.addr @[lsu_bus_intf.scala 130:43] - io.axi.aw.bits.id <= bus_buffer.io.lsu_axi.aw.bits.id @[lsu_bus_intf.scala 130:43] - io.axi.aw.valid <= bus_buffer.io.lsu_axi.aw.valid @[lsu_bus_intf.scala 130:43] - bus_buffer.io.lsu_axi.aw.ready <= io.axi.aw.ready @[lsu_bus_intf.scala 130:43] - bus_buffer.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[lsu_bus_intf.scala 131:51] - io.lsu_busreq_r <= bus_buffer.io.lsu_busreq_r @[lsu_bus_intf.scala 133:38] - io.lsu_bus_buffer_pend_any <= bus_buffer.io.lsu_bus_buffer_pend_any @[lsu_bus_intf.scala 134:38] - io.lsu_bus_buffer_full_any <= bus_buffer.io.lsu_bus_buffer_full_any @[lsu_bus_intf.scala 135:38] - io.lsu_bus_buffer_empty_any <= bus_buffer.io.lsu_bus_buffer_empty_any @[lsu_bus_intf.scala 136:38] - io.lsu_bus_idle_any <= bus_buffer.io.lsu_bus_idle_any @[lsu_bus_intf.scala 137:38] - ld_byte_hit_buf_lo <= bus_buffer.io.ld_byte_hit_buf_lo @[lsu_bus_intf.scala 138:38] - ld_byte_hit_buf_hi <= bus_buffer.io.ld_byte_hit_buf_hi @[lsu_bus_intf.scala 139:38] - ld_fwddata_buf_lo <= bus_buffer.io.ld_fwddata_buf_lo @[lsu_bus_intf.scala 140:38] - ld_fwddata_buf_hi <= bus_buffer.io.ld_fwddata_buf_hi @[lsu_bus_intf.scala 141:38] - io.dctl_busbuff.lsu_nonblock_load_data <= bus_buffer.io.dctl_busbuff.lsu_nonblock_load_data @[lsu_bus_intf.scala 142:19] - io.dctl_busbuff.lsu_nonblock_load_data_tag <= bus_buffer.io.dctl_busbuff.lsu_nonblock_load_data_tag @[lsu_bus_intf.scala 142:19] - io.dctl_busbuff.lsu_nonblock_load_data_error <= bus_buffer.io.dctl_busbuff.lsu_nonblock_load_data_error @[lsu_bus_intf.scala 142:19] - io.dctl_busbuff.lsu_nonblock_load_data_valid <= bus_buffer.io.dctl_busbuff.lsu_nonblock_load_data_valid @[lsu_bus_intf.scala 142:19] - io.dctl_busbuff.lsu_nonblock_load_inv_tag_r <= bus_buffer.io.dctl_busbuff.lsu_nonblock_load_inv_tag_r @[lsu_bus_intf.scala 142:19] - io.dctl_busbuff.lsu_nonblock_load_inv_r <= bus_buffer.io.dctl_busbuff.lsu_nonblock_load_inv_r @[lsu_bus_intf.scala 142:19] - io.dctl_busbuff.lsu_nonblock_load_tag_m <= bus_buffer.io.dctl_busbuff.lsu_nonblock_load_tag_m @[lsu_bus_intf.scala 142:19] - io.dctl_busbuff.lsu_nonblock_load_valid_m <= bus_buffer.io.dctl_busbuff.lsu_nonblock_load_valid_m @[lsu_bus_intf.scala 142:19] - bus_buffer.io.no_word_merge_r <= no_word_merge_r @[lsu_bus_intf.scala 143:51] - bus_buffer.io.no_dword_merge_r <= no_dword_merge_r @[lsu_bus_intf.scala 144:51] - bus_buffer.io.is_sideeffects_r <= is_sideeffects_r @[lsu_bus_intf.scala 145:51] - bus_buffer.io.ldst_dual_d <= ldst_dual_d @[lsu_bus_intf.scala 146:51] - bus_buffer.io.ldst_dual_m <= ldst_dual_m @[lsu_bus_intf.scala 147:51] - bus_buffer.io.ldst_dual_r <= ldst_dual_r @[lsu_bus_intf.scala 148:51] - bus_buffer.io.ldst_byteen_ext_m <= ldst_byteen_ext_m @[lsu_bus_intf.scala 149:51] - bus_buffer.io.ld_full_hit_m <= ld_full_hit_m @[lsu_bus_intf.scala 150:51] - bus_buffer.io.lsu_bus_clk_en_q <= lsu_bus_clk_en_q @[lsu_bus_intf.scala 151:51] - node _T = bits(io.lsu_pkt_m.bits.word, 0, 0) @[lsu_bus_intf.scala 153:63] - node _T_1 = bits(io.lsu_pkt_m.bits.half, 0, 0) @[lsu_bus_intf.scala 153:107] - node _T_2 = bits(io.lsu_pkt_m.bits.by, 0, 0) @[lsu_bus_intf.scala 153:148] + bus_buffer.io.scan_mode <= io.scan_mode @[lsu_bus_intf.scala 102:29] + io.tlu_busbuff.lsu_imprecise_error_addr_any <= bus_buffer.io.tlu_busbuff.lsu_imprecise_error_addr_any @[lsu_bus_intf.scala 103:18] + io.tlu_busbuff.lsu_imprecise_error_store_any <= bus_buffer.io.tlu_busbuff.lsu_imprecise_error_store_any @[lsu_bus_intf.scala 103:18] + io.tlu_busbuff.lsu_imprecise_error_load_any <= bus_buffer.io.tlu_busbuff.lsu_imprecise_error_load_any @[lsu_bus_intf.scala 103:18] + bus_buffer.io.tlu_busbuff.dec_tlu_sideeffect_posted_disable <= io.tlu_busbuff.dec_tlu_sideeffect_posted_disable @[lsu_bus_intf.scala 103:18] + bus_buffer.io.tlu_busbuff.dec_tlu_wb_coalescing_disable <= io.tlu_busbuff.dec_tlu_wb_coalescing_disable @[lsu_bus_intf.scala 103:18] + bus_buffer.io.tlu_busbuff.dec_tlu_external_ldfwd_disable <= io.tlu_busbuff.dec_tlu_external_ldfwd_disable @[lsu_bus_intf.scala 103:18] + io.tlu_busbuff.lsu_pmu_bus_busy <= bus_buffer.io.tlu_busbuff.lsu_pmu_bus_busy @[lsu_bus_intf.scala 103:18] + io.tlu_busbuff.lsu_pmu_bus_error <= bus_buffer.io.tlu_busbuff.lsu_pmu_bus_error @[lsu_bus_intf.scala 103:18] + io.tlu_busbuff.lsu_pmu_bus_misaligned <= bus_buffer.io.tlu_busbuff.lsu_pmu_bus_misaligned @[lsu_bus_intf.scala 103:18] + io.tlu_busbuff.lsu_pmu_bus_trxn <= bus_buffer.io.tlu_busbuff.lsu_pmu_bus_trxn @[lsu_bus_intf.scala 103:18] + bus_buffer.io.dec_tlu_force_halt <= io.dec_tlu_force_halt @[lsu_bus_intf.scala 105:51] + bus_buffer.io.lsu_c2_r_clk <= io.lsu_c2_r_clk @[lsu_bus_intf.scala 106:51] + bus_buffer.io.lsu_bus_ibuf_c1_clk <= io.lsu_bus_ibuf_c1_clk @[lsu_bus_intf.scala 107:51] + bus_buffer.io.lsu_bus_obuf_c1_clk <= io.lsu_bus_obuf_c1_clk @[lsu_bus_intf.scala 108:51] + bus_buffer.io.lsu_bus_buf_c1_clk <= io.lsu_bus_buf_c1_clk @[lsu_bus_intf.scala 109:51] + bus_buffer.io.lsu_free_c2_clk <= io.lsu_free_c2_clk @[lsu_bus_intf.scala 110:51] + bus_buffer.io.lsu_busm_clk <= io.lsu_busm_clk @[lsu_bus_intf.scala 111:51] + bus_buffer.io.dec_lsu_valid_raw_d <= io.dec_lsu_valid_raw_d @[lsu_bus_intf.scala 112:51] + bus_buffer.io.lsu_pkt_m.bits.store_data_bypass_m <= io.lsu_pkt_m.bits.store_data_bypass_m @[lsu_bus_intf.scala 115:27] + bus_buffer.io.lsu_pkt_m.bits.load_ldst_bypass_d <= io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu_bus_intf.scala 115:27] + bus_buffer.io.lsu_pkt_m.bits.store_data_bypass_d <= io.lsu_pkt_m.bits.store_data_bypass_d @[lsu_bus_intf.scala 115:27] + bus_buffer.io.lsu_pkt_m.bits.dma <= io.lsu_pkt_m.bits.dma @[lsu_bus_intf.scala 115:27] + bus_buffer.io.lsu_pkt_m.bits.unsign <= io.lsu_pkt_m.bits.unsign @[lsu_bus_intf.scala 115:27] + bus_buffer.io.lsu_pkt_m.bits.store <= io.lsu_pkt_m.bits.store @[lsu_bus_intf.scala 115:27] + bus_buffer.io.lsu_pkt_m.bits.load <= io.lsu_pkt_m.bits.load @[lsu_bus_intf.scala 115:27] + bus_buffer.io.lsu_pkt_m.bits.dword <= io.lsu_pkt_m.bits.dword @[lsu_bus_intf.scala 115:27] + bus_buffer.io.lsu_pkt_m.bits.word <= io.lsu_pkt_m.bits.word @[lsu_bus_intf.scala 115:27] + bus_buffer.io.lsu_pkt_m.bits.half <= io.lsu_pkt_m.bits.half @[lsu_bus_intf.scala 115:27] + bus_buffer.io.lsu_pkt_m.bits.by <= io.lsu_pkt_m.bits.by @[lsu_bus_intf.scala 115:27] + bus_buffer.io.lsu_pkt_m.bits.fast_int <= io.lsu_pkt_m.bits.fast_int @[lsu_bus_intf.scala 115:27] + bus_buffer.io.lsu_pkt_m.valid <= io.lsu_pkt_m.valid @[lsu_bus_intf.scala 115:27] + bus_buffer.io.lsu_pkt_r.bits.store_data_bypass_m <= io.lsu_pkt_r.bits.store_data_bypass_m @[lsu_bus_intf.scala 116:27] + bus_buffer.io.lsu_pkt_r.bits.load_ldst_bypass_d <= io.lsu_pkt_r.bits.load_ldst_bypass_d @[lsu_bus_intf.scala 116:27] + bus_buffer.io.lsu_pkt_r.bits.store_data_bypass_d <= io.lsu_pkt_r.bits.store_data_bypass_d @[lsu_bus_intf.scala 116:27] + bus_buffer.io.lsu_pkt_r.bits.dma <= io.lsu_pkt_r.bits.dma @[lsu_bus_intf.scala 116:27] + bus_buffer.io.lsu_pkt_r.bits.unsign <= io.lsu_pkt_r.bits.unsign @[lsu_bus_intf.scala 116:27] + bus_buffer.io.lsu_pkt_r.bits.store <= io.lsu_pkt_r.bits.store @[lsu_bus_intf.scala 116:27] + bus_buffer.io.lsu_pkt_r.bits.load <= io.lsu_pkt_r.bits.load @[lsu_bus_intf.scala 116:27] + bus_buffer.io.lsu_pkt_r.bits.dword <= io.lsu_pkt_r.bits.dword @[lsu_bus_intf.scala 116:27] + bus_buffer.io.lsu_pkt_r.bits.word <= io.lsu_pkt_r.bits.word @[lsu_bus_intf.scala 116:27] + bus_buffer.io.lsu_pkt_r.bits.half <= io.lsu_pkt_r.bits.half @[lsu_bus_intf.scala 116:27] + bus_buffer.io.lsu_pkt_r.bits.by <= io.lsu_pkt_r.bits.by @[lsu_bus_intf.scala 116:27] + bus_buffer.io.lsu_pkt_r.bits.fast_int <= io.lsu_pkt_r.bits.fast_int @[lsu_bus_intf.scala 116:27] + bus_buffer.io.lsu_pkt_r.valid <= io.lsu_pkt_r.valid @[lsu_bus_intf.scala 116:27] + bus_buffer.io.lsu_addr_m <= io.lsu_addr_m @[lsu_bus_intf.scala 119:51] + bus_buffer.io.end_addr_m <= io.end_addr_m @[lsu_bus_intf.scala 120:51] + bus_buffer.io.lsu_addr_r <= io.lsu_addr_r @[lsu_bus_intf.scala 121:51] + bus_buffer.io.end_addr_r <= io.end_addr_r @[lsu_bus_intf.scala 122:51] + bus_buffer.io.store_data_r <= io.store_data_r @[lsu_bus_intf.scala 123:51] + bus_buffer.io.lsu_busreq_m <= io.lsu_busreq_m @[lsu_bus_intf.scala 125:51] + bus_buffer.io.flush_m_up <= io.flush_m_up @[lsu_bus_intf.scala 126:51] + bus_buffer.io.flush_r <= io.flush_r @[lsu_bus_intf.scala 127:51] + bus_buffer.io.lsu_commit_r <= io.lsu_commit_r @[lsu_bus_intf.scala 128:51] + bus_buffer.io.lsu_axi.r.bits.last <= io.axi.r.bits.last @[lsu_bus_intf.scala 129:43] + bus_buffer.io.lsu_axi.r.bits.resp <= io.axi.r.bits.resp @[lsu_bus_intf.scala 129:43] + bus_buffer.io.lsu_axi.r.bits.data <= io.axi.r.bits.data @[lsu_bus_intf.scala 129:43] + bus_buffer.io.lsu_axi.r.bits.id <= io.axi.r.bits.id @[lsu_bus_intf.scala 129:43] + bus_buffer.io.lsu_axi.r.valid <= io.axi.r.valid @[lsu_bus_intf.scala 129:43] + io.axi.r.ready <= bus_buffer.io.lsu_axi.r.ready @[lsu_bus_intf.scala 129:43] + io.axi.ar.bits.qos <= bus_buffer.io.lsu_axi.ar.bits.qos @[lsu_bus_intf.scala 129:43] + io.axi.ar.bits.prot <= bus_buffer.io.lsu_axi.ar.bits.prot @[lsu_bus_intf.scala 129:43] + io.axi.ar.bits.cache <= bus_buffer.io.lsu_axi.ar.bits.cache @[lsu_bus_intf.scala 129:43] + io.axi.ar.bits.lock <= bus_buffer.io.lsu_axi.ar.bits.lock @[lsu_bus_intf.scala 129:43] + io.axi.ar.bits.burst <= bus_buffer.io.lsu_axi.ar.bits.burst @[lsu_bus_intf.scala 129:43] + io.axi.ar.bits.size <= bus_buffer.io.lsu_axi.ar.bits.size @[lsu_bus_intf.scala 129:43] + io.axi.ar.bits.len <= bus_buffer.io.lsu_axi.ar.bits.len @[lsu_bus_intf.scala 129:43] + io.axi.ar.bits.region <= bus_buffer.io.lsu_axi.ar.bits.region @[lsu_bus_intf.scala 129:43] + io.axi.ar.bits.addr <= bus_buffer.io.lsu_axi.ar.bits.addr @[lsu_bus_intf.scala 129:43] + io.axi.ar.bits.id <= bus_buffer.io.lsu_axi.ar.bits.id @[lsu_bus_intf.scala 129:43] + io.axi.ar.valid <= bus_buffer.io.lsu_axi.ar.valid @[lsu_bus_intf.scala 129:43] + bus_buffer.io.lsu_axi.ar.ready <= io.axi.ar.ready @[lsu_bus_intf.scala 129:43] + bus_buffer.io.lsu_axi.b.bits.id <= io.axi.b.bits.id @[lsu_bus_intf.scala 129:43] + bus_buffer.io.lsu_axi.b.bits.resp <= io.axi.b.bits.resp @[lsu_bus_intf.scala 129:43] + bus_buffer.io.lsu_axi.b.valid <= io.axi.b.valid @[lsu_bus_intf.scala 129:43] + io.axi.b.ready <= bus_buffer.io.lsu_axi.b.ready @[lsu_bus_intf.scala 129:43] + io.axi.w.bits.last <= bus_buffer.io.lsu_axi.w.bits.last @[lsu_bus_intf.scala 129:43] + io.axi.w.bits.strb <= bus_buffer.io.lsu_axi.w.bits.strb @[lsu_bus_intf.scala 129:43] + io.axi.w.bits.data <= bus_buffer.io.lsu_axi.w.bits.data @[lsu_bus_intf.scala 129:43] + io.axi.w.valid <= bus_buffer.io.lsu_axi.w.valid @[lsu_bus_intf.scala 129:43] + bus_buffer.io.lsu_axi.w.ready <= io.axi.w.ready @[lsu_bus_intf.scala 129:43] + io.axi.aw.bits.qos <= bus_buffer.io.lsu_axi.aw.bits.qos @[lsu_bus_intf.scala 129:43] + io.axi.aw.bits.prot <= bus_buffer.io.lsu_axi.aw.bits.prot @[lsu_bus_intf.scala 129:43] + io.axi.aw.bits.cache <= bus_buffer.io.lsu_axi.aw.bits.cache @[lsu_bus_intf.scala 129:43] + io.axi.aw.bits.lock <= bus_buffer.io.lsu_axi.aw.bits.lock @[lsu_bus_intf.scala 129:43] + io.axi.aw.bits.burst <= bus_buffer.io.lsu_axi.aw.bits.burst @[lsu_bus_intf.scala 129:43] + io.axi.aw.bits.size <= bus_buffer.io.lsu_axi.aw.bits.size @[lsu_bus_intf.scala 129:43] + io.axi.aw.bits.len <= bus_buffer.io.lsu_axi.aw.bits.len @[lsu_bus_intf.scala 129:43] + io.axi.aw.bits.region <= bus_buffer.io.lsu_axi.aw.bits.region @[lsu_bus_intf.scala 129:43] + io.axi.aw.bits.addr <= bus_buffer.io.lsu_axi.aw.bits.addr @[lsu_bus_intf.scala 129:43] + io.axi.aw.bits.id <= bus_buffer.io.lsu_axi.aw.bits.id @[lsu_bus_intf.scala 129:43] + io.axi.aw.valid <= bus_buffer.io.lsu_axi.aw.valid @[lsu_bus_intf.scala 129:43] + bus_buffer.io.lsu_axi.aw.ready <= io.axi.aw.ready @[lsu_bus_intf.scala 129:43] + bus_buffer.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[lsu_bus_intf.scala 130:51] + io.lsu_busreq_r <= bus_buffer.io.lsu_busreq_r @[lsu_bus_intf.scala 132:38] + io.lsu_bus_buffer_pend_any <= bus_buffer.io.lsu_bus_buffer_pend_any @[lsu_bus_intf.scala 133:38] + io.lsu_bus_buffer_full_any <= bus_buffer.io.lsu_bus_buffer_full_any @[lsu_bus_intf.scala 134:38] + io.lsu_bus_buffer_empty_any <= bus_buffer.io.lsu_bus_buffer_empty_any @[lsu_bus_intf.scala 135:38] + io.lsu_bus_idle_any <= bus_buffer.io.lsu_bus_idle_any @[lsu_bus_intf.scala 136:38] + ld_byte_hit_buf_lo <= bus_buffer.io.ld_byte_hit_buf_lo @[lsu_bus_intf.scala 137:38] + ld_byte_hit_buf_hi <= bus_buffer.io.ld_byte_hit_buf_hi @[lsu_bus_intf.scala 138:38] + ld_fwddata_buf_lo <= bus_buffer.io.ld_fwddata_buf_lo @[lsu_bus_intf.scala 139:38] + ld_fwddata_buf_hi <= bus_buffer.io.ld_fwddata_buf_hi @[lsu_bus_intf.scala 140:38] + io.dctl_busbuff.lsu_nonblock_load_data <= bus_buffer.io.dctl_busbuff.lsu_nonblock_load_data @[lsu_bus_intf.scala 141:19] + io.dctl_busbuff.lsu_nonblock_load_data_tag <= bus_buffer.io.dctl_busbuff.lsu_nonblock_load_data_tag @[lsu_bus_intf.scala 141:19] + io.dctl_busbuff.lsu_nonblock_load_data_error <= bus_buffer.io.dctl_busbuff.lsu_nonblock_load_data_error @[lsu_bus_intf.scala 141:19] + io.dctl_busbuff.lsu_nonblock_load_data_valid <= bus_buffer.io.dctl_busbuff.lsu_nonblock_load_data_valid @[lsu_bus_intf.scala 141:19] + io.dctl_busbuff.lsu_nonblock_load_inv_tag_r <= bus_buffer.io.dctl_busbuff.lsu_nonblock_load_inv_tag_r @[lsu_bus_intf.scala 141:19] + io.dctl_busbuff.lsu_nonblock_load_inv_r <= bus_buffer.io.dctl_busbuff.lsu_nonblock_load_inv_r @[lsu_bus_intf.scala 141:19] + io.dctl_busbuff.lsu_nonblock_load_tag_m <= bus_buffer.io.dctl_busbuff.lsu_nonblock_load_tag_m @[lsu_bus_intf.scala 141:19] + io.dctl_busbuff.lsu_nonblock_load_valid_m <= bus_buffer.io.dctl_busbuff.lsu_nonblock_load_valid_m @[lsu_bus_intf.scala 141:19] + bus_buffer.io.no_word_merge_r <= no_word_merge_r @[lsu_bus_intf.scala 142:51] + bus_buffer.io.no_dword_merge_r <= no_dword_merge_r @[lsu_bus_intf.scala 143:51] + bus_buffer.io.is_sideeffects_r <= is_sideeffects_r @[lsu_bus_intf.scala 144:51] + bus_buffer.io.ldst_dual_d <= ldst_dual_d @[lsu_bus_intf.scala 145:51] + bus_buffer.io.ldst_dual_m <= ldst_dual_m @[lsu_bus_intf.scala 146:51] + bus_buffer.io.ldst_dual_r <= ldst_dual_r @[lsu_bus_intf.scala 147:51] + bus_buffer.io.ldst_byteen_ext_m <= ldst_byteen_ext_m @[lsu_bus_intf.scala 148:51] + bus_buffer.io.ld_full_hit_m <= ld_full_hit_m @[lsu_bus_intf.scala 149:51] + bus_buffer.io.lsu_bus_clk_en_q <= lsu_bus_clk_en_q @[lsu_bus_intf.scala 150:51] + node _T = bits(io.lsu_pkt_m.bits.word, 0, 0) @[lsu_bus_intf.scala 152:63] + node _T_1 = bits(io.lsu_pkt_m.bits.half, 0, 0) @[lsu_bus_intf.scala 152:107] + node _T_2 = bits(io.lsu_pkt_m.bits.by, 0, 0) @[lsu_bus_intf.scala 152:148] node _T_3 = mux(_T, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_4 = mux(_T_1, UInt<4>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_5 = mux(_T_2, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] @@ -101383,279 +101390,279 @@ circuit quasar_wrapper : node _T_7 = or(_T_6, _T_5) @[Mux.scala 27:72] wire _T_8 : UInt<4> @[Mux.scala 27:72] _T_8 <= _T_7 @[Mux.scala 27:72] - ldst_byteen_m <= _T_8 @[lsu_bus_intf.scala 153:27] - node _T_9 = bits(io.lsu_addr_d, 2, 2) @[lsu_bus_intf.scala 154:43] - node _T_10 = bits(io.end_addr_d, 2, 2) @[lsu_bus_intf.scala 154:64] - node _T_11 = neq(_T_9, _T_10) @[lsu_bus_intf.scala 154:47] - ldst_dual_d <= _T_11 @[lsu_bus_intf.scala 154:27] - node _T_12 = bits(io.lsu_addr_r, 31, 3) @[lsu_bus_intf.scala 155:44] - node _T_13 = bits(io.lsu_addr_m, 31, 3) @[lsu_bus_intf.scala 155:68] - node _T_14 = eq(_T_12, _T_13) @[lsu_bus_intf.scala 155:51] - addr_match_dw_lo_r_m <= _T_14 @[lsu_bus_intf.scala 155:27] - node _T_15 = bits(io.lsu_addr_r, 2, 2) @[lsu_bus_intf.scala 156:68] - node _T_16 = bits(io.lsu_addr_m, 2, 2) @[lsu_bus_intf.scala 156:85] - node _T_17 = xor(_T_15, _T_16) @[lsu_bus_intf.scala 156:71] - node _T_18 = eq(_T_17, UInt<1>("h00")) @[lsu_bus_intf.scala 156:53] - node _T_19 = and(addr_match_dw_lo_r_m, _T_18) @[lsu_bus_intf.scala 156:51] - addr_match_word_lo_r_m <= _T_19 @[lsu_bus_intf.scala 156:27] - node _T_20 = eq(ldst_dual_r, UInt<1>("h00")) @[lsu_bus_intf.scala 157:48] - node _T_21 = and(io.lsu_busreq_r, _T_20) @[lsu_bus_intf.scala 157:46] - node _T_22 = and(_T_21, io.lsu_busreq_m) @[lsu_bus_intf.scala 157:61] - node _T_23 = eq(addr_match_word_lo_r_m, UInt<1>("h00")) @[lsu_bus_intf.scala 157:107] - node _T_24 = or(io.lsu_pkt_m.bits.load, _T_23) @[lsu_bus_intf.scala 157:105] - node _T_25 = and(_T_22, _T_24) @[lsu_bus_intf.scala 157:79] - no_word_merge_r <= _T_25 @[lsu_bus_intf.scala 157:27] - node _T_26 = eq(ldst_dual_r, UInt<1>("h00")) @[lsu_bus_intf.scala 158:48] - node _T_27 = and(io.lsu_busreq_r, _T_26) @[lsu_bus_intf.scala 158:46] - node _T_28 = and(_T_27, io.lsu_busreq_m) @[lsu_bus_intf.scala 158:61] - node _T_29 = eq(addr_match_dw_lo_r_m, UInt<1>("h00")) @[lsu_bus_intf.scala 158:107] - node _T_30 = or(io.lsu_pkt_m.bits.load, _T_29) @[lsu_bus_intf.scala 158:105] - node _T_31 = and(_T_28, _T_30) @[lsu_bus_intf.scala 158:79] - no_dword_merge_r <= _T_31 @[lsu_bus_intf.scala 158:27] - node _T_32 = bits(ldst_byteen_m, 3, 0) @[lsu_bus_intf.scala 160:43] - node _T_33 = bits(io.lsu_addr_m, 1, 0) @[lsu_bus_intf.scala 160:65] - node _T_34 = dshl(_T_32, _T_33) @[lsu_bus_intf.scala 160:49] - ldst_byteen_ext_m <= _T_34 @[lsu_bus_intf.scala 160:27] - node _T_35 = bits(ldst_byteen_r, 3, 0) @[lsu_bus_intf.scala 161:43] - node _T_36 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_intf.scala 161:65] - node _T_37 = dshl(_T_35, _T_36) @[lsu_bus_intf.scala 161:49] - ldst_byteen_ext_r <= _T_37 @[lsu_bus_intf.scala 161:27] - node _T_38 = bits(io.store_data_r, 31, 0) @[lsu_bus_intf.scala 162:45] - node _T_39 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_intf.scala 162:72] + ldst_byteen_m <= _T_8 @[lsu_bus_intf.scala 152:27] + node _T_9 = bits(io.lsu_addr_d, 2, 2) @[lsu_bus_intf.scala 153:43] + node _T_10 = bits(io.end_addr_d, 2, 2) @[lsu_bus_intf.scala 153:64] + node _T_11 = neq(_T_9, _T_10) @[lsu_bus_intf.scala 153:47] + ldst_dual_d <= _T_11 @[lsu_bus_intf.scala 153:27] + node _T_12 = bits(io.lsu_addr_r, 31, 3) @[lsu_bus_intf.scala 154:44] + node _T_13 = bits(io.lsu_addr_m, 31, 3) @[lsu_bus_intf.scala 154:68] + node _T_14 = eq(_T_12, _T_13) @[lsu_bus_intf.scala 154:51] + addr_match_dw_lo_r_m <= _T_14 @[lsu_bus_intf.scala 154:27] + node _T_15 = bits(io.lsu_addr_r, 2, 2) @[lsu_bus_intf.scala 155:68] + node _T_16 = bits(io.lsu_addr_m, 2, 2) @[lsu_bus_intf.scala 155:85] + node _T_17 = xor(_T_15, _T_16) @[lsu_bus_intf.scala 155:71] + node _T_18 = eq(_T_17, UInt<1>("h00")) @[lsu_bus_intf.scala 155:53] + node _T_19 = and(addr_match_dw_lo_r_m, _T_18) @[lsu_bus_intf.scala 155:51] + addr_match_word_lo_r_m <= _T_19 @[lsu_bus_intf.scala 155:27] + node _T_20 = eq(ldst_dual_r, UInt<1>("h00")) @[lsu_bus_intf.scala 156:48] + node _T_21 = and(io.lsu_busreq_r, _T_20) @[lsu_bus_intf.scala 156:46] + node _T_22 = and(_T_21, io.lsu_busreq_m) @[lsu_bus_intf.scala 156:61] + node _T_23 = eq(addr_match_word_lo_r_m, UInt<1>("h00")) @[lsu_bus_intf.scala 156:107] + node _T_24 = or(io.lsu_pkt_m.bits.load, _T_23) @[lsu_bus_intf.scala 156:105] + node _T_25 = and(_T_22, _T_24) @[lsu_bus_intf.scala 156:79] + no_word_merge_r <= _T_25 @[lsu_bus_intf.scala 156:27] + node _T_26 = eq(ldst_dual_r, UInt<1>("h00")) @[lsu_bus_intf.scala 157:48] + node _T_27 = and(io.lsu_busreq_r, _T_26) @[lsu_bus_intf.scala 157:46] + node _T_28 = and(_T_27, io.lsu_busreq_m) @[lsu_bus_intf.scala 157:61] + node _T_29 = eq(addr_match_dw_lo_r_m, UInt<1>("h00")) @[lsu_bus_intf.scala 157:107] + node _T_30 = or(io.lsu_pkt_m.bits.load, _T_29) @[lsu_bus_intf.scala 157:105] + node _T_31 = and(_T_28, _T_30) @[lsu_bus_intf.scala 157:79] + no_dword_merge_r <= _T_31 @[lsu_bus_intf.scala 157:27] + node _T_32 = bits(ldst_byteen_m, 3, 0) @[lsu_bus_intf.scala 159:43] + node _T_33 = bits(io.lsu_addr_m, 1, 0) @[lsu_bus_intf.scala 159:65] + node _T_34 = dshl(_T_32, _T_33) @[lsu_bus_intf.scala 159:49] + ldst_byteen_ext_m <= _T_34 @[lsu_bus_intf.scala 159:27] + node _T_35 = bits(ldst_byteen_r, 3, 0) @[lsu_bus_intf.scala 160:43] + node _T_36 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_intf.scala 160:65] + node _T_37 = dshl(_T_35, _T_36) @[lsu_bus_intf.scala 160:49] + ldst_byteen_ext_r <= _T_37 @[lsu_bus_intf.scala 160:27] + node _T_38 = bits(io.store_data_r, 31, 0) @[lsu_bus_intf.scala 161:45] + node _T_39 = bits(io.lsu_addr_r, 1, 0) @[lsu_bus_intf.scala 161:72] node _T_40 = cat(_T_39, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_41 = dshl(_T_38, _T_40) @[lsu_bus_intf.scala 162:52] - store_data_ext_r <= _T_41 @[lsu_bus_intf.scala 162:27] - node _T_42 = bits(ldst_byteen_ext_m, 7, 4) @[lsu_bus_intf.scala 163:47] - ldst_byteen_hi_m <= _T_42 @[lsu_bus_intf.scala 163:27] - node _T_43 = bits(ldst_byteen_ext_m, 3, 0) @[lsu_bus_intf.scala 164:47] - ldst_byteen_lo_m <= _T_43 @[lsu_bus_intf.scala 164:27] - node _T_44 = bits(ldst_byteen_ext_r, 7, 4) @[lsu_bus_intf.scala 165:47] - ldst_byteen_hi_r <= _T_44 @[lsu_bus_intf.scala 165:27] - node _T_45 = bits(ldst_byteen_ext_r, 3, 0) @[lsu_bus_intf.scala 166:47] - ldst_byteen_lo_r <= _T_45 @[lsu_bus_intf.scala 166:27] - node _T_46 = bits(store_data_ext_r, 63, 32) @[lsu_bus_intf.scala 168:46] - store_data_hi_r <= _T_46 @[lsu_bus_intf.scala 168:27] - node _T_47 = bits(store_data_ext_r, 31, 0) @[lsu_bus_intf.scala 169:46] - store_data_lo_r <= _T_47 @[lsu_bus_intf.scala 169:27] - node _T_48 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_intf.scala 170:44] - node _T_49 = bits(io.lsu_addr_r, 31, 2) @[lsu_bus_intf.scala 170:68] - node _T_50 = eq(_T_48, _T_49) @[lsu_bus_intf.scala 170:51] - node _T_51 = and(_T_50, io.lsu_pkt_r.valid) @[lsu_bus_intf.scala 170:76] - node _T_52 = and(_T_51, io.lsu_pkt_r.bits.store) @[lsu_bus_intf.scala 170:97] - node _T_53 = and(_T_52, io.lsu_busreq_m) @[lsu_bus_intf.scala 170:123] - ld_addr_rhit_lo_lo <= _T_53 @[lsu_bus_intf.scala 170:27] - node _T_54 = bits(io.end_addr_m, 31, 2) @[lsu_bus_intf.scala 171:44] - node _T_55 = bits(io.lsu_addr_r, 31, 2) @[lsu_bus_intf.scala 171:68] - node _T_56 = eq(_T_54, _T_55) @[lsu_bus_intf.scala 171:51] - node _T_57 = and(_T_56, io.lsu_pkt_r.valid) @[lsu_bus_intf.scala 171:76] - node _T_58 = and(_T_57, io.lsu_pkt_r.bits.store) @[lsu_bus_intf.scala 171:97] - node _T_59 = and(_T_58, io.lsu_busreq_m) @[lsu_bus_intf.scala 171:123] - ld_addr_rhit_lo_hi <= _T_59 @[lsu_bus_intf.scala 171:27] - node _T_60 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_intf.scala 172:44] - node _T_61 = bits(io.end_addr_r, 31, 2) @[lsu_bus_intf.scala 172:68] - node _T_62 = eq(_T_60, _T_61) @[lsu_bus_intf.scala 172:51] - node _T_63 = and(_T_62, io.lsu_pkt_r.valid) @[lsu_bus_intf.scala 172:76] - node _T_64 = and(_T_63, io.lsu_pkt_r.bits.store) @[lsu_bus_intf.scala 172:97] - node _T_65 = and(_T_64, io.lsu_busreq_m) @[lsu_bus_intf.scala 172:123] - ld_addr_rhit_hi_lo <= _T_65 @[lsu_bus_intf.scala 172:27] - node _T_66 = bits(io.end_addr_m, 31, 2) @[lsu_bus_intf.scala 173:44] - node _T_67 = bits(io.end_addr_r, 31, 2) @[lsu_bus_intf.scala 173:68] - node _T_68 = eq(_T_66, _T_67) @[lsu_bus_intf.scala 173:51] - node _T_69 = and(_T_68, io.lsu_pkt_r.valid) @[lsu_bus_intf.scala 173:76] - node _T_70 = and(_T_69, io.lsu_pkt_r.bits.store) @[lsu_bus_intf.scala 173:97] - node _T_71 = and(_T_70, io.lsu_busreq_m) @[lsu_bus_intf.scala 173:123] - ld_addr_rhit_hi_hi <= _T_71 @[lsu_bus_intf.scala 173:27] - node _T_72 = bits(ldst_byteen_lo_r, 0, 0) @[lsu_bus_intf.scala 175:88] - node _T_73 = and(ld_addr_rhit_lo_lo, _T_72) @[lsu_bus_intf.scala 175:70] - node _T_74 = bits(ldst_byteen_lo_m, 0, 0) @[lsu_bus_intf.scala 175:110] - node _T_75 = and(_T_73, _T_74) @[lsu_bus_intf.scala 175:92] - node _T_76 = bits(ldst_byteen_lo_r, 1, 1) @[lsu_bus_intf.scala 175:88] - node _T_77 = and(ld_addr_rhit_lo_lo, _T_76) @[lsu_bus_intf.scala 175:70] - node _T_78 = bits(ldst_byteen_lo_m, 1, 1) @[lsu_bus_intf.scala 175:110] - node _T_79 = and(_T_77, _T_78) @[lsu_bus_intf.scala 175:92] - node _T_80 = bits(ldst_byteen_lo_r, 2, 2) @[lsu_bus_intf.scala 175:88] - node _T_81 = and(ld_addr_rhit_lo_lo, _T_80) @[lsu_bus_intf.scala 175:70] - node _T_82 = bits(ldst_byteen_lo_m, 2, 2) @[lsu_bus_intf.scala 175:110] - node _T_83 = and(_T_81, _T_82) @[lsu_bus_intf.scala 175:92] - node _T_84 = bits(ldst_byteen_lo_r, 3, 3) @[lsu_bus_intf.scala 175:88] - node _T_85 = and(ld_addr_rhit_lo_lo, _T_84) @[lsu_bus_intf.scala 175:70] - node _T_86 = bits(ldst_byteen_lo_m, 3, 3) @[lsu_bus_intf.scala 175:110] - node _T_87 = and(_T_85, _T_86) @[lsu_bus_intf.scala 175:92] + node _T_41 = dshl(_T_38, _T_40) @[lsu_bus_intf.scala 161:52] + store_data_ext_r <= _T_41 @[lsu_bus_intf.scala 161:27] + node _T_42 = bits(ldst_byteen_ext_m, 7, 4) @[lsu_bus_intf.scala 162:47] + ldst_byteen_hi_m <= _T_42 @[lsu_bus_intf.scala 162:27] + node _T_43 = bits(ldst_byteen_ext_m, 3, 0) @[lsu_bus_intf.scala 163:47] + ldst_byteen_lo_m <= _T_43 @[lsu_bus_intf.scala 163:27] + node _T_44 = bits(ldst_byteen_ext_r, 7, 4) @[lsu_bus_intf.scala 164:47] + ldst_byteen_hi_r <= _T_44 @[lsu_bus_intf.scala 164:27] + node _T_45 = bits(ldst_byteen_ext_r, 3, 0) @[lsu_bus_intf.scala 165:47] + ldst_byteen_lo_r <= _T_45 @[lsu_bus_intf.scala 165:27] + node _T_46 = bits(store_data_ext_r, 63, 32) @[lsu_bus_intf.scala 167:46] + store_data_hi_r <= _T_46 @[lsu_bus_intf.scala 167:27] + node _T_47 = bits(store_data_ext_r, 31, 0) @[lsu_bus_intf.scala 168:46] + store_data_lo_r <= _T_47 @[lsu_bus_intf.scala 168:27] + node _T_48 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_intf.scala 169:44] + node _T_49 = bits(io.lsu_addr_r, 31, 2) @[lsu_bus_intf.scala 169:68] + node _T_50 = eq(_T_48, _T_49) @[lsu_bus_intf.scala 169:51] + node _T_51 = and(_T_50, io.lsu_pkt_r.valid) @[lsu_bus_intf.scala 169:76] + node _T_52 = and(_T_51, io.lsu_pkt_r.bits.store) @[lsu_bus_intf.scala 169:97] + node _T_53 = and(_T_52, io.lsu_busreq_m) @[lsu_bus_intf.scala 169:123] + ld_addr_rhit_lo_lo <= _T_53 @[lsu_bus_intf.scala 169:27] + node _T_54 = bits(io.end_addr_m, 31, 2) @[lsu_bus_intf.scala 170:44] + node _T_55 = bits(io.lsu_addr_r, 31, 2) @[lsu_bus_intf.scala 170:68] + node _T_56 = eq(_T_54, _T_55) @[lsu_bus_intf.scala 170:51] + node _T_57 = and(_T_56, io.lsu_pkt_r.valid) @[lsu_bus_intf.scala 170:76] + node _T_58 = and(_T_57, io.lsu_pkt_r.bits.store) @[lsu_bus_intf.scala 170:97] + node _T_59 = and(_T_58, io.lsu_busreq_m) @[lsu_bus_intf.scala 170:123] + ld_addr_rhit_lo_hi <= _T_59 @[lsu_bus_intf.scala 170:27] + node _T_60 = bits(io.lsu_addr_m, 31, 2) @[lsu_bus_intf.scala 171:44] + node _T_61 = bits(io.end_addr_r, 31, 2) @[lsu_bus_intf.scala 171:68] + node _T_62 = eq(_T_60, _T_61) @[lsu_bus_intf.scala 171:51] + node _T_63 = and(_T_62, io.lsu_pkt_r.valid) @[lsu_bus_intf.scala 171:76] + node _T_64 = and(_T_63, io.lsu_pkt_r.bits.store) @[lsu_bus_intf.scala 171:97] + node _T_65 = and(_T_64, io.lsu_busreq_m) @[lsu_bus_intf.scala 171:123] + ld_addr_rhit_hi_lo <= _T_65 @[lsu_bus_intf.scala 171:27] + node _T_66 = bits(io.end_addr_m, 31, 2) @[lsu_bus_intf.scala 172:44] + node _T_67 = bits(io.end_addr_r, 31, 2) @[lsu_bus_intf.scala 172:68] + node _T_68 = eq(_T_66, _T_67) @[lsu_bus_intf.scala 172:51] + node _T_69 = and(_T_68, io.lsu_pkt_r.valid) @[lsu_bus_intf.scala 172:76] + node _T_70 = and(_T_69, io.lsu_pkt_r.bits.store) @[lsu_bus_intf.scala 172:97] + node _T_71 = and(_T_70, io.lsu_busreq_m) @[lsu_bus_intf.scala 172:123] + ld_addr_rhit_hi_hi <= _T_71 @[lsu_bus_intf.scala 172:27] + node _T_72 = bits(ldst_byteen_lo_r, 0, 0) @[lsu_bus_intf.scala 174:88] + node _T_73 = and(ld_addr_rhit_lo_lo, _T_72) @[lsu_bus_intf.scala 174:70] + node _T_74 = bits(ldst_byteen_lo_m, 0, 0) @[lsu_bus_intf.scala 174:110] + node _T_75 = and(_T_73, _T_74) @[lsu_bus_intf.scala 174:92] + node _T_76 = bits(ldst_byteen_lo_r, 1, 1) @[lsu_bus_intf.scala 174:88] + node _T_77 = and(ld_addr_rhit_lo_lo, _T_76) @[lsu_bus_intf.scala 174:70] + node _T_78 = bits(ldst_byteen_lo_m, 1, 1) @[lsu_bus_intf.scala 174:110] + node _T_79 = and(_T_77, _T_78) @[lsu_bus_intf.scala 174:92] + node _T_80 = bits(ldst_byteen_lo_r, 2, 2) @[lsu_bus_intf.scala 174:88] + node _T_81 = and(ld_addr_rhit_lo_lo, _T_80) @[lsu_bus_intf.scala 174:70] + node _T_82 = bits(ldst_byteen_lo_m, 2, 2) @[lsu_bus_intf.scala 174:110] + node _T_83 = and(_T_81, _T_82) @[lsu_bus_intf.scala 174:92] + node _T_84 = bits(ldst_byteen_lo_r, 3, 3) @[lsu_bus_intf.scala 174:88] + node _T_85 = and(ld_addr_rhit_lo_lo, _T_84) @[lsu_bus_intf.scala 174:70] + node _T_86 = bits(ldst_byteen_lo_m, 3, 3) @[lsu_bus_intf.scala 174:110] + node _T_87 = and(_T_85, _T_86) @[lsu_bus_intf.scala 174:92] node _T_88 = cat(_T_87, _T_83) @[Cat.scala 29:58] node _T_89 = cat(_T_88, _T_79) @[Cat.scala 29:58] node _T_90 = cat(_T_89, _T_75) @[Cat.scala 29:58] - ld_byte_rhit_lo_lo <= _T_90 @[lsu_bus_intf.scala 175:27] - node _T_91 = bits(ldst_byteen_lo_r, 0, 0) @[lsu_bus_intf.scala 176:88] - node _T_92 = and(ld_addr_rhit_lo_hi, _T_91) @[lsu_bus_intf.scala 176:70] - node _T_93 = bits(ldst_byteen_hi_m, 0, 0) @[lsu_bus_intf.scala 176:110] - node _T_94 = and(_T_92, _T_93) @[lsu_bus_intf.scala 176:92] - node _T_95 = bits(ldst_byteen_lo_r, 1, 1) @[lsu_bus_intf.scala 176:88] - node _T_96 = and(ld_addr_rhit_lo_hi, _T_95) @[lsu_bus_intf.scala 176:70] - node _T_97 = bits(ldst_byteen_hi_m, 1, 1) @[lsu_bus_intf.scala 176:110] - node _T_98 = and(_T_96, _T_97) @[lsu_bus_intf.scala 176:92] - node _T_99 = bits(ldst_byteen_lo_r, 2, 2) @[lsu_bus_intf.scala 176:88] - node _T_100 = and(ld_addr_rhit_lo_hi, _T_99) @[lsu_bus_intf.scala 176:70] - node _T_101 = bits(ldst_byteen_hi_m, 2, 2) @[lsu_bus_intf.scala 176:110] - node _T_102 = and(_T_100, _T_101) @[lsu_bus_intf.scala 176:92] - node _T_103 = bits(ldst_byteen_lo_r, 3, 3) @[lsu_bus_intf.scala 176:88] - node _T_104 = and(ld_addr_rhit_lo_hi, _T_103) @[lsu_bus_intf.scala 176:70] - node _T_105 = bits(ldst_byteen_hi_m, 3, 3) @[lsu_bus_intf.scala 176:110] - node _T_106 = and(_T_104, _T_105) @[lsu_bus_intf.scala 176:92] + ld_byte_rhit_lo_lo <= _T_90 @[lsu_bus_intf.scala 174:27] + node _T_91 = bits(ldst_byteen_lo_r, 0, 0) @[lsu_bus_intf.scala 175:88] + node _T_92 = and(ld_addr_rhit_lo_hi, _T_91) @[lsu_bus_intf.scala 175:70] + node _T_93 = bits(ldst_byteen_hi_m, 0, 0) @[lsu_bus_intf.scala 175:110] + node _T_94 = and(_T_92, _T_93) @[lsu_bus_intf.scala 175:92] + node _T_95 = bits(ldst_byteen_lo_r, 1, 1) @[lsu_bus_intf.scala 175:88] + node _T_96 = and(ld_addr_rhit_lo_hi, _T_95) @[lsu_bus_intf.scala 175:70] + node _T_97 = bits(ldst_byteen_hi_m, 1, 1) @[lsu_bus_intf.scala 175:110] + node _T_98 = and(_T_96, _T_97) @[lsu_bus_intf.scala 175:92] + node _T_99 = bits(ldst_byteen_lo_r, 2, 2) @[lsu_bus_intf.scala 175:88] + node _T_100 = and(ld_addr_rhit_lo_hi, _T_99) @[lsu_bus_intf.scala 175:70] + node _T_101 = bits(ldst_byteen_hi_m, 2, 2) @[lsu_bus_intf.scala 175:110] + node _T_102 = and(_T_100, _T_101) @[lsu_bus_intf.scala 175:92] + node _T_103 = bits(ldst_byteen_lo_r, 3, 3) @[lsu_bus_intf.scala 175:88] + node _T_104 = and(ld_addr_rhit_lo_hi, _T_103) @[lsu_bus_intf.scala 175:70] + node _T_105 = bits(ldst_byteen_hi_m, 3, 3) @[lsu_bus_intf.scala 175:110] + node _T_106 = and(_T_104, _T_105) @[lsu_bus_intf.scala 175:92] node _T_107 = cat(_T_106, _T_102) @[Cat.scala 29:58] node _T_108 = cat(_T_107, _T_98) @[Cat.scala 29:58] node _T_109 = cat(_T_108, _T_94) @[Cat.scala 29:58] - ld_byte_rhit_lo_hi <= _T_109 @[lsu_bus_intf.scala 176:27] - node _T_110 = bits(ldst_byteen_hi_r, 0, 0) @[lsu_bus_intf.scala 177:88] - node _T_111 = and(ld_addr_rhit_hi_lo, _T_110) @[lsu_bus_intf.scala 177:70] - node _T_112 = bits(ldst_byteen_lo_m, 0, 0) @[lsu_bus_intf.scala 177:110] - node _T_113 = and(_T_111, _T_112) @[lsu_bus_intf.scala 177:92] - node _T_114 = bits(ldst_byteen_hi_r, 1, 1) @[lsu_bus_intf.scala 177:88] - node _T_115 = and(ld_addr_rhit_hi_lo, _T_114) @[lsu_bus_intf.scala 177:70] - node _T_116 = bits(ldst_byteen_lo_m, 1, 1) @[lsu_bus_intf.scala 177:110] - node _T_117 = and(_T_115, _T_116) @[lsu_bus_intf.scala 177:92] - node _T_118 = bits(ldst_byteen_hi_r, 2, 2) @[lsu_bus_intf.scala 177:88] - node _T_119 = and(ld_addr_rhit_hi_lo, _T_118) @[lsu_bus_intf.scala 177:70] - node _T_120 = bits(ldst_byteen_lo_m, 2, 2) @[lsu_bus_intf.scala 177:110] - node _T_121 = and(_T_119, _T_120) @[lsu_bus_intf.scala 177:92] - node _T_122 = bits(ldst_byteen_hi_r, 3, 3) @[lsu_bus_intf.scala 177:88] - node _T_123 = and(ld_addr_rhit_hi_lo, _T_122) @[lsu_bus_intf.scala 177:70] - node _T_124 = bits(ldst_byteen_lo_m, 3, 3) @[lsu_bus_intf.scala 177:110] - node _T_125 = and(_T_123, _T_124) @[lsu_bus_intf.scala 177:92] + ld_byte_rhit_lo_hi <= _T_109 @[lsu_bus_intf.scala 175:27] + node _T_110 = bits(ldst_byteen_hi_r, 0, 0) @[lsu_bus_intf.scala 176:88] + node _T_111 = and(ld_addr_rhit_hi_lo, _T_110) @[lsu_bus_intf.scala 176:70] + node _T_112 = bits(ldst_byteen_lo_m, 0, 0) @[lsu_bus_intf.scala 176:110] + node _T_113 = and(_T_111, _T_112) @[lsu_bus_intf.scala 176:92] + node _T_114 = bits(ldst_byteen_hi_r, 1, 1) @[lsu_bus_intf.scala 176:88] + node _T_115 = and(ld_addr_rhit_hi_lo, _T_114) @[lsu_bus_intf.scala 176:70] + node _T_116 = bits(ldst_byteen_lo_m, 1, 1) @[lsu_bus_intf.scala 176:110] + node _T_117 = and(_T_115, _T_116) @[lsu_bus_intf.scala 176:92] + node _T_118 = bits(ldst_byteen_hi_r, 2, 2) @[lsu_bus_intf.scala 176:88] + node _T_119 = and(ld_addr_rhit_hi_lo, _T_118) @[lsu_bus_intf.scala 176:70] + node _T_120 = bits(ldst_byteen_lo_m, 2, 2) @[lsu_bus_intf.scala 176:110] + node _T_121 = and(_T_119, _T_120) @[lsu_bus_intf.scala 176:92] + node _T_122 = bits(ldst_byteen_hi_r, 3, 3) @[lsu_bus_intf.scala 176:88] + node _T_123 = and(ld_addr_rhit_hi_lo, _T_122) @[lsu_bus_intf.scala 176:70] + node _T_124 = bits(ldst_byteen_lo_m, 3, 3) @[lsu_bus_intf.scala 176:110] + node _T_125 = and(_T_123, _T_124) @[lsu_bus_intf.scala 176:92] node _T_126 = cat(_T_125, _T_121) @[Cat.scala 29:58] node _T_127 = cat(_T_126, _T_117) @[Cat.scala 29:58] node _T_128 = cat(_T_127, _T_113) @[Cat.scala 29:58] - ld_byte_rhit_hi_lo <= _T_128 @[lsu_bus_intf.scala 177:27] - node _T_129 = bits(ldst_byteen_hi_r, 0, 0) @[lsu_bus_intf.scala 178:88] - node _T_130 = and(ld_addr_rhit_hi_hi, _T_129) @[lsu_bus_intf.scala 178:70] - node _T_131 = bits(ldst_byteen_hi_m, 0, 0) @[lsu_bus_intf.scala 178:110] - node _T_132 = and(_T_130, _T_131) @[lsu_bus_intf.scala 178:92] - node _T_133 = bits(ldst_byteen_hi_r, 1, 1) @[lsu_bus_intf.scala 178:88] - node _T_134 = and(ld_addr_rhit_hi_hi, _T_133) @[lsu_bus_intf.scala 178:70] - node _T_135 = bits(ldst_byteen_hi_m, 1, 1) @[lsu_bus_intf.scala 178:110] - node _T_136 = and(_T_134, _T_135) @[lsu_bus_intf.scala 178:92] - node _T_137 = bits(ldst_byteen_hi_r, 2, 2) @[lsu_bus_intf.scala 178:88] - node _T_138 = and(ld_addr_rhit_hi_hi, _T_137) @[lsu_bus_intf.scala 178:70] - node _T_139 = bits(ldst_byteen_hi_m, 2, 2) @[lsu_bus_intf.scala 178:110] - node _T_140 = and(_T_138, _T_139) @[lsu_bus_intf.scala 178:92] - node _T_141 = bits(ldst_byteen_hi_r, 3, 3) @[lsu_bus_intf.scala 178:88] - node _T_142 = and(ld_addr_rhit_hi_hi, _T_141) @[lsu_bus_intf.scala 178:70] - node _T_143 = bits(ldst_byteen_hi_m, 3, 3) @[lsu_bus_intf.scala 178:110] - node _T_144 = and(_T_142, _T_143) @[lsu_bus_intf.scala 178:92] + ld_byte_rhit_hi_lo <= _T_128 @[lsu_bus_intf.scala 176:27] + node _T_129 = bits(ldst_byteen_hi_r, 0, 0) @[lsu_bus_intf.scala 177:88] + node _T_130 = and(ld_addr_rhit_hi_hi, _T_129) @[lsu_bus_intf.scala 177:70] + node _T_131 = bits(ldst_byteen_hi_m, 0, 0) @[lsu_bus_intf.scala 177:110] + node _T_132 = and(_T_130, _T_131) @[lsu_bus_intf.scala 177:92] + node _T_133 = bits(ldst_byteen_hi_r, 1, 1) @[lsu_bus_intf.scala 177:88] + node _T_134 = and(ld_addr_rhit_hi_hi, _T_133) @[lsu_bus_intf.scala 177:70] + node _T_135 = bits(ldst_byteen_hi_m, 1, 1) @[lsu_bus_intf.scala 177:110] + node _T_136 = and(_T_134, _T_135) @[lsu_bus_intf.scala 177:92] + node _T_137 = bits(ldst_byteen_hi_r, 2, 2) @[lsu_bus_intf.scala 177:88] + node _T_138 = and(ld_addr_rhit_hi_hi, _T_137) @[lsu_bus_intf.scala 177:70] + node _T_139 = bits(ldst_byteen_hi_m, 2, 2) @[lsu_bus_intf.scala 177:110] + node _T_140 = and(_T_138, _T_139) @[lsu_bus_intf.scala 177:92] + node _T_141 = bits(ldst_byteen_hi_r, 3, 3) @[lsu_bus_intf.scala 177:88] + node _T_142 = and(ld_addr_rhit_hi_hi, _T_141) @[lsu_bus_intf.scala 177:70] + node _T_143 = bits(ldst_byteen_hi_m, 3, 3) @[lsu_bus_intf.scala 177:110] + node _T_144 = and(_T_142, _T_143) @[lsu_bus_intf.scala 177:92] node _T_145 = cat(_T_144, _T_140) @[Cat.scala 29:58] node _T_146 = cat(_T_145, _T_136) @[Cat.scala 29:58] node _T_147 = cat(_T_146, _T_132) @[Cat.scala 29:58] - ld_byte_rhit_hi_hi <= _T_147 @[lsu_bus_intf.scala 178:27] - node _T_148 = bits(ld_byte_rhit_lo_lo, 0, 0) @[lsu_bus_intf.scala 180:69] - node _T_149 = bits(ld_byte_rhit_hi_lo, 0, 0) @[lsu_bus_intf.scala 180:93] - node _T_150 = or(_T_148, _T_149) @[lsu_bus_intf.scala 180:73] - node _T_151 = bits(ld_byte_hit_buf_lo, 0, 0) @[lsu_bus_intf.scala 180:117] - node _T_152 = or(_T_150, _T_151) @[lsu_bus_intf.scala 180:97] - node _T_153 = bits(ld_byte_rhit_lo_lo, 1, 1) @[lsu_bus_intf.scala 180:69] - node _T_154 = bits(ld_byte_rhit_hi_lo, 1, 1) @[lsu_bus_intf.scala 180:93] - node _T_155 = or(_T_153, _T_154) @[lsu_bus_intf.scala 180:73] - node _T_156 = bits(ld_byte_hit_buf_lo, 1, 1) @[lsu_bus_intf.scala 180:117] - node _T_157 = or(_T_155, _T_156) @[lsu_bus_intf.scala 180:97] - node _T_158 = bits(ld_byte_rhit_lo_lo, 2, 2) @[lsu_bus_intf.scala 180:69] - node _T_159 = bits(ld_byte_rhit_hi_lo, 2, 2) @[lsu_bus_intf.scala 180:93] - node _T_160 = or(_T_158, _T_159) @[lsu_bus_intf.scala 180:73] - node _T_161 = bits(ld_byte_hit_buf_lo, 2, 2) @[lsu_bus_intf.scala 180:117] - node _T_162 = or(_T_160, _T_161) @[lsu_bus_intf.scala 180:97] - node _T_163 = bits(ld_byte_rhit_lo_lo, 3, 3) @[lsu_bus_intf.scala 180:69] - node _T_164 = bits(ld_byte_rhit_hi_lo, 3, 3) @[lsu_bus_intf.scala 180:93] - node _T_165 = or(_T_163, _T_164) @[lsu_bus_intf.scala 180:73] - node _T_166 = bits(ld_byte_hit_buf_lo, 3, 3) @[lsu_bus_intf.scala 180:117] - node _T_167 = or(_T_165, _T_166) @[lsu_bus_intf.scala 180:97] + ld_byte_rhit_hi_hi <= _T_147 @[lsu_bus_intf.scala 177:27] + node _T_148 = bits(ld_byte_rhit_lo_lo, 0, 0) @[lsu_bus_intf.scala 179:69] + node _T_149 = bits(ld_byte_rhit_hi_lo, 0, 0) @[lsu_bus_intf.scala 179:93] + node _T_150 = or(_T_148, _T_149) @[lsu_bus_intf.scala 179:73] + node _T_151 = bits(ld_byte_hit_buf_lo, 0, 0) @[lsu_bus_intf.scala 179:117] + node _T_152 = or(_T_150, _T_151) @[lsu_bus_intf.scala 179:97] + node _T_153 = bits(ld_byte_rhit_lo_lo, 1, 1) @[lsu_bus_intf.scala 179:69] + node _T_154 = bits(ld_byte_rhit_hi_lo, 1, 1) @[lsu_bus_intf.scala 179:93] + node _T_155 = or(_T_153, _T_154) @[lsu_bus_intf.scala 179:73] + node _T_156 = bits(ld_byte_hit_buf_lo, 1, 1) @[lsu_bus_intf.scala 179:117] + node _T_157 = or(_T_155, _T_156) @[lsu_bus_intf.scala 179:97] + node _T_158 = bits(ld_byte_rhit_lo_lo, 2, 2) @[lsu_bus_intf.scala 179:69] + node _T_159 = bits(ld_byte_rhit_hi_lo, 2, 2) @[lsu_bus_intf.scala 179:93] + node _T_160 = or(_T_158, _T_159) @[lsu_bus_intf.scala 179:73] + node _T_161 = bits(ld_byte_hit_buf_lo, 2, 2) @[lsu_bus_intf.scala 179:117] + node _T_162 = or(_T_160, _T_161) @[lsu_bus_intf.scala 179:97] + node _T_163 = bits(ld_byte_rhit_lo_lo, 3, 3) @[lsu_bus_intf.scala 179:69] + node _T_164 = bits(ld_byte_rhit_hi_lo, 3, 3) @[lsu_bus_intf.scala 179:93] + node _T_165 = or(_T_163, _T_164) @[lsu_bus_intf.scala 179:73] + node _T_166 = bits(ld_byte_hit_buf_lo, 3, 3) @[lsu_bus_intf.scala 179:117] + node _T_167 = or(_T_165, _T_166) @[lsu_bus_intf.scala 179:97] node _T_168 = cat(_T_167, _T_162) @[Cat.scala 29:58] node _T_169 = cat(_T_168, _T_157) @[Cat.scala 29:58] node _T_170 = cat(_T_169, _T_152) @[Cat.scala 29:58] - ld_byte_hit_lo <= _T_170 @[lsu_bus_intf.scala 180:27] - node _T_171 = bits(ld_byte_rhit_lo_hi, 0, 0) @[lsu_bus_intf.scala 181:69] - node _T_172 = bits(ld_byte_rhit_hi_hi, 0, 0) @[lsu_bus_intf.scala 181:93] - node _T_173 = or(_T_171, _T_172) @[lsu_bus_intf.scala 181:73] - node _T_174 = bits(ld_byte_hit_buf_hi, 0, 0) @[lsu_bus_intf.scala 181:117] - node _T_175 = or(_T_173, _T_174) @[lsu_bus_intf.scala 181:97] - node _T_176 = bits(ld_byte_rhit_lo_hi, 1, 1) @[lsu_bus_intf.scala 181:69] - node _T_177 = bits(ld_byte_rhit_hi_hi, 1, 1) @[lsu_bus_intf.scala 181:93] - node _T_178 = or(_T_176, _T_177) @[lsu_bus_intf.scala 181:73] - node _T_179 = bits(ld_byte_hit_buf_hi, 1, 1) @[lsu_bus_intf.scala 181:117] - node _T_180 = or(_T_178, _T_179) @[lsu_bus_intf.scala 181:97] - node _T_181 = bits(ld_byte_rhit_lo_hi, 2, 2) @[lsu_bus_intf.scala 181:69] - node _T_182 = bits(ld_byte_rhit_hi_hi, 2, 2) @[lsu_bus_intf.scala 181:93] - node _T_183 = or(_T_181, _T_182) @[lsu_bus_intf.scala 181:73] - node _T_184 = bits(ld_byte_hit_buf_hi, 2, 2) @[lsu_bus_intf.scala 181:117] - node _T_185 = or(_T_183, _T_184) @[lsu_bus_intf.scala 181:97] - node _T_186 = bits(ld_byte_rhit_lo_hi, 3, 3) @[lsu_bus_intf.scala 181:69] - node _T_187 = bits(ld_byte_rhit_hi_hi, 3, 3) @[lsu_bus_intf.scala 181:93] - node _T_188 = or(_T_186, _T_187) @[lsu_bus_intf.scala 181:73] - node _T_189 = bits(ld_byte_hit_buf_hi, 3, 3) @[lsu_bus_intf.scala 181:117] - node _T_190 = or(_T_188, _T_189) @[lsu_bus_intf.scala 181:97] + ld_byte_hit_lo <= _T_170 @[lsu_bus_intf.scala 179:27] + node _T_171 = bits(ld_byte_rhit_lo_hi, 0, 0) @[lsu_bus_intf.scala 180:69] + node _T_172 = bits(ld_byte_rhit_hi_hi, 0, 0) @[lsu_bus_intf.scala 180:93] + node _T_173 = or(_T_171, _T_172) @[lsu_bus_intf.scala 180:73] + node _T_174 = bits(ld_byte_hit_buf_hi, 0, 0) @[lsu_bus_intf.scala 180:117] + node _T_175 = or(_T_173, _T_174) @[lsu_bus_intf.scala 180:97] + node _T_176 = bits(ld_byte_rhit_lo_hi, 1, 1) @[lsu_bus_intf.scala 180:69] + node _T_177 = bits(ld_byte_rhit_hi_hi, 1, 1) @[lsu_bus_intf.scala 180:93] + node _T_178 = or(_T_176, _T_177) @[lsu_bus_intf.scala 180:73] + node _T_179 = bits(ld_byte_hit_buf_hi, 1, 1) @[lsu_bus_intf.scala 180:117] + node _T_180 = or(_T_178, _T_179) @[lsu_bus_intf.scala 180:97] + node _T_181 = bits(ld_byte_rhit_lo_hi, 2, 2) @[lsu_bus_intf.scala 180:69] + node _T_182 = bits(ld_byte_rhit_hi_hi, 2, 2) @[lsu_bus_intf.scala 180:93] + node _T_183 = or(_T_181, _T_182) @[lsu_bus_intf.scala 180:73] + node _T_184 = bits(ld_byte_hit_buf_hi, 2, 2) @[lsu_bus_intf.scala 180:117] + node _T_185 = or(_T_183, _T_184) @[lsu_bus_intf.scala 180:97] + node _T_186 = bits(ld_byte_rhit_lo_hi, 3, 3) @[lsu_bus_intf.scala 180:69] + node _T_187 = bits(ld_byte_rhit_hi_hi, 3, 3) @[lsu_bus_intf.scala 180:93] + node _T_188 = or(_T_186, _T_187) @[lsu_bus_intf.scala 180:73] + node _T_189 = bits(ld_byte_hit_buf_hi, 3, 3) @[lsu_bus_intf.scala 180:117] + node _T_190 = or(_T_188, _T_189) @[lsu_bus_intf.scala 180:97] node _T_191 = cat(_T_190, _T_185) @[Cat.scala 29:58] node _T_192 = cat(_T_191, _T_180) @[Cat.scala 29:58] node _T_193 = cat(_T_192, _T_175) @[Cat.scala 29:58] - ld_byte_hit_hi <= _T_193 @[lsu_bus_intf.scala 181:27] - node _T_194 = bits(ld_byte_rhit_lo_lo, 0, 0) @[lsu_bus_intf.scala 182:69] - node _T_195 = bits(ld_byte_rhit_hi_lo, 0, 0) @[lsu_bus_intf.scala 182:93] - node _T_196 = or(_T_194, _T_195) @[lsu_bus_intf.scala 182:73] - node _T_197 = bits(ld_byte_rhit_lo_lo, 1, 1) @[lsu_bus_intf.scala 182:69] - node _T_198 = bits(ld_byte_rhit_hi_lo, 1, 1) @[lsu_bus_intf.scala 182:93] - node _T_199 = or(_T_197, _T_198) @[lsu_bus_intf.scala 182:73] - node _T_200 = bits(ld_byte_rhit_lo_lo, 2, 2) @[lsu_bus_intf.scala 182:69] - node _T_201 = bits(ld_byte_rhit_hi_lo, 2, 2) @[lsu_bus_intf.scala 182:93] - node _T_202 = or(_T_200, _T_201) @[lsu_bus_intf.scala 182:73] - node _T_203 = bits(ld_byte_rhit_lo_lo, 3, 3) @[lsu_bus_intf.scala 182:69] - node _T_204 = bits(ld_byte_rhit_hi_lo, 3, 3) @[lsu_bus_intf.scala 182:93] - node _T_205 = or(_T_203, _T_204) @[lsu_bus_intf.scala 182:73] + ld_byte_hit_hi <= _T_193 @[lsu_bus_intf.scala 180:27] + node _T_194 = bits(ld_byte_rhit_lo_lo, 0, 0) @[lsu_bus_intf.scala 181:69] + node _T_195 = bits(ld_byte_rhit_hi_lo, 0, 0) @[lsu_bus_intf.scala 181:93] + node _T_196 = or(_T_194, _T_195) @[lsu_bus_intf.scala 181:73] + node _T_197 = bits(ld_byte_rhit_lo_lo, 1, 1) @[lsu_bus_intf.scala 181:69] + node _T_198 = bits(ld_byte_rhit_hi_lo, 1, 1) @[lsu_bus_intf.scala 181:93] + node _T_199 = or(_T_197, _T_198) @[lsu_bus_intf.scala 181:73] + node _T_200 = bits(ld_byte_rhit_lo_lo, 2, 2) @[lsu_bus_intf.scala 181:69] + node _T_201 = bits(ld_byte_rhit_hi_lo, 2, 2) @[lsu_bus_intf.scala 181:93] + node _T_202 = or(_T_200, _T_201) @[lsu_bus_intf.scala 181:73] + node _T_203 = bits(ld_byte_rhit_lo_lo, 3, 3) @[lsu_bus_intf.scala 181:69] + node _T_204 = bits(ld_byte_rhit_hi_lo, 3, 3) @[lsu_bus_intf.scala 181:93] + node _T_205 = or(_T_203, _T_204) @[lsu_bus_intf.scala 181:73] node _T_206 = cat(_T_205, _T_202) @[Cat.scala 29:58] node _T_207 = cat(_T_206, _T_199) @[Cat.scala 29:58] node _T_208 = cat(_T_207, _T_196) @[Cat.scala 29:58] - ld_byte_rhit_lo <= _T_208 @[lsu_bus_intf.scala 182:27] - node _T_209 = bits(ld_byte_rhit_lo_hi, 0, 0) @[lsu_bus_intf.scala 183:69] - node _T_210 = bits(ld_byte_rhit_hi_hi, 0, 0) @[lsu_bus_intf.scala 183:93] - node _T_211 = or(_T_209, _T_210) @[lsu_bus_intf.scala 183:73] - node _T_212 = bits(ld_byte_rhit_lo_hi, 1, 1) @[lsu_bus_intf.scala 183:69] - node _T_213 = bits(ld_byte_rhit_hi_hi, 1, 1) @[lsu_bus_intf.scala 183:93] - node _T_214 = or(_T_212, _T_213) @[lsu_bus_intf.scala 183:73] - node _T_215 = bits(ld_byte_rhit_lo_hi, 2, 2) @[lsu_bus_intf.scala 183:69] - node _T_216 = bits(ld_byte_rhit_hi_hi, 2, 2) @[lsu_bus_intf.scala 183:93] - node _T_217 = or(_T_215, _T_216) @[lsu_bus_intf.scala 183:73] - node _T_218 = bits(ld_byte_rhit_lo_hi, 3, 3) @[lsu_bus_intf.scala 183:69] - node _T_219 = bits(ld_byte_rhit_hi_hi, 3, 3) @[lsu_bus_intf.scala 183:93] - node _T_220 = or(_T_218, _T_219) @[lsu_bus_intf.scala 183:73] + ld_byte_rhit_lo <= _T_208 @[lsu_bus_intf.scala 181:27] + node _T_209 = bits(ld_byte_rhit_lo_hi, 0, 0) @[lsu_bus_intf.scala 182:69] + node _T_210 = bits(ld_byte_rhit_hi_hi, 0, 0) @[lsu_bus_intf.scala 182:93] + node _T_211 = or(_T_209, _T_210) @[lsu_bus_intf.scala 182:73] + node _T_212 = bits(ld_byte_rhit_lo_hi, 1, 1) @[lsu_bus_intf.scala 182:69] + node _T_213 = bits(ld_byte_rhit_hi_hi, 1, 1) @[lsu_bus_intf.scala 182:93] + node _T_214 = or(_T_212, _T_213) @[lsu_bus_intf.scala 182:73] + node _T_215 = bits(ld_byte_rhit_lo_hi, 2, 2) @[lsu_bus_intf.scala 182:69] + node _T_216 = bits(ld_byte_rhit_hi_hi, 2, 2) @[lsu_bus_intf.scala 182:93] + node _T_217 = or(_T_215, _T_216) @[lsu_bus_intf.scala 182:73] + node _T_218 = bits(ld_byte_rhit_lo_hi, 3, 3) @[lsu_bus_intf.scala 182:69] + node _T_219 = bits(ld_byte_rhit_hi_hi, 3, 3) @[lsu_bus_intf.scala 182:93] + node _T_220 = or(_T_218, _T_219) @[lsu_bus_intf.scala 182:73] node _T_221 = cat(_T_220, _T_217) @[Cat.scala 29:58] node _T_222 = cat(_T_221, _T_214) @[Cat.scala 29:58] node _T_223 = cat(_T_222, _T_211) @[Cat.scala 29:58] - ld_byte_rhit_hi <= _T_223 @[lsu_bus_intf.scala 183:27] - node _T_224 = bits(ld_byte_rhit_lo_lo, 0, 0) @[lsu_bus_intf.scala 184:79] - node _T_225 = bits(store_data_lo_r, 7, 0) @[lsu_bus_intf.scala 184:101] - node _T_226 = bits(ld_byte_rhit_hi_lo, 0, 0) @[lsu_bus_intf.scala 184:136] - node _T_227 = bits(store_data_hi_r, 7, 0) @[lsu_bus_intf.scala 184:158] + ld_byte_rhit_hi <= _T_223 @[lsu_bus_intf.scala 182:27] + node _T_224 = bits(ld_byte_rhit_lo_lo, 0, 0) @[lsu_bus_intf.scala 183:79] + node _T_225 = bits(store_data_lo_r, 7, 0) @[lsu_bus_intf.scala 183:101] + node _T_226 = bits(ld_byte_rhit_hi_lo, 0, 0) @[lsu_bus_intf.scala 183:136] + node _T_227 = bits(store_data_hi_r, 7, 0) @[lsu_bus_intf.scala 183:158] node _T_228 = mux(_T_224, _T_225, UInt<1>("h00")) @[Mux.scala 27:72] node _T_229 = mux(_T_226, _T_227, UInt<1>("h00")) @[Mux.scala 27:72] node _T_230 = or(_T_228, _T_229) @[Mux.scala 27:72] wire _T_231 : UInt<8> @[Mux.scala 27:72] _T_231 <= _T_230 @[Mux.scala 27:72] - node _T_232 = bits(ld_byte_rhit_lo_lo, 1, 1) @[lsu_bus_intf.scala 184:79] - node _T_233 = bits(store_data_lo_r, 15, 8) @[lsu_bus_intf.scala 184:101] - node _T_234 = bits(ld_byte_rhit_hi_lo, 1, 1) @[lsu_bus_intf.scala 184:136] - node _T_235 = bits(store_data_hi_r, 15, 8) @[lsu_bus_intf.scala 184:158] + node _T_232 = bits(ld_byte_rhit_lo_lo, 1, 1) @[lsu_bus_intf.scala 183:79] + node _T_233 = bits(store_data_lo_r, 15, 8) @[lsu_bus_intf.scala 183:101] + node _T_234 = bits(ld_byte_rhit_hi_lo, 1, 1) @[lsu_bus_intf.scala 183:136] + node _T_235 = bits(store_data_hi_r, 15, 8) @[lsu_bus_intf.scala 183:158] node _T_236 = mux(_T_232, _T_233, UInt<1>("h00")) @[Mux.scala 27:72] node _T_237 = mux(_T_234, _T_235, UInt<1>("h00")) @[Mux.scala 27:72] node _T_238 = or(_T_236, _T_237) @[Mux.scala 27:72] wire _T_239 : UInt<8> @[Mux.scala 27:72] _T_239 <= _T_238 @[Mux.scala 27:72] - node _T_240 = bits(ld_byte_rhit_lo_lo, 2, 2) @[lsu_bus_intf.scala 184:79] - node _T_241 = bits(store_data_lo_r, 23, 16) @[lsu_bus_intf.scala 184:101] - node _T_242 = bits(ld_byte_rhit_hi_lo, 2, 2) @[lsu_bus_intf.scala 184:136] - node _T_243 = bits(store_data_hi_r, 23, 16) @[lsu_bus_intf.scala 184:158] + node _T_240 = bits(ld_byte_rhit_lo_lo, 2, 2) @[lsu_bus_intf.scala 183:79] + node _T_241 = bits(store_data_lo_r, 23, 16) @[lsu_bus_intf.scala 183:101] + node _T_242 = bits(ld_byte_rhit_hi_lo, 2, 2) @[lsu_bus_intf.scala 183:136] + node _T_243 = bits(store_data_hi_r, 23, 16) @[lsu_bus_intf.scala 183:158] node _T_244 = mux(_T_240, _T_241, UInt<1>("h00")) @[Mux.scala 27:72] node _T_245 = mux(_T_242, _T_243, UInt<1>("h00")) @[Mux.scala 27:72] node _T_246 = or(_T_244, _T_245) @[Mux.scala 27:72] wire _T_247 : UInt<8> @[Mux.scala 27:72] _T_247 <= _T_246 @[Mux.scala 27:72] - node _T_248 = bits(ld_byte_rhit_lo_lo, 3, 3) @[lsu_bus_intf.scala 184:79] - node _T_249 = bits(store_data_lo_r, 31, 24) @[lsu_bus_intf.scala 184:101] - node _T_250 = bits(ld_byte_rhit_hi_lo, 3, 3) @[lsu_bus_intf.scala 184:136] - node _T_251 = bits(store_data_hi_r, 31, 24) @[lsu_bus_intf.scala 184:158] + node _T_248 = bits(ld_byte_rhit_lo_lo, 3, 3) @[lsu_bus_intf.scala 183:79] + node _T_249 = bits(store_data_lo_r, 31, 24) @[lsu_bus_intf.scala 183:101] + node _T_250 = bits(ld_byte_rhit_hi_lo, 3, 3) @[lsu_bus_intf.scala 183:136] + node _T_251 = bits(store_data_hi_r, 31, 24) @[lsu_bus_intf.scala 183:158] node _T_252 = mux(_T_248, _T_249, UInt<1>("h00")) @[Mux.scala 27:72] node _T_253 = mux(_T_250, _T_251, UInt<1>("h00")) @[Mux.scala 27:72] node _T_254 = or(_T_252, _T_253) @[Mux.scala 27:72] @@ -101664,38 +101671,38 @@ circuit quasar_wrapper : node _T_256 = cat(_T_255, _T_247) @[Cat.scala 29:58] node _T_257 = cat(_T_256, _T_239) @[Cat.scala 29:58] node _T_258 = cat(_T_257, _T_231) @[Cat.scala 29:58] - ld_fwddata_rpipe_lo <= _T_258 @[lsu_bus_intf.scala 184:27] - node _T_259 = bits(ld_byte_rhit_lo_hi, 0, 0) @[lsu_bus_intf.scala 185:79] - node _T_260 = bits(store_data_lo_r, 7, 0) @[lsu_bus_intf.scala 185:101] - node _T_261 = bits(ld_byte_rhit_hi_hi, 0, 0) @[lsu_bus_intf.scala 185:136] - node _T_262 = bits(store_data_hi_r, 7, 0) @[lsu_bus_intf.scala 185:158] + ld_fwddata_rpipe_lo <= _T_258 @[lsu_bus_intf.scala 183:27] + node _T_259 = bits(ld_byte_rhit_lo_hi, 0, 0) @[lsu_bus_intf.scala 184:79] + node _T_260 = bits(store_data_lo_r, 7, 0) @[lsu_bus_intf.scala 184:101] + node _T_261 = bits(ld_byte_rhit_hi_hi, 0, 0) @[lsu_bus_intf.scala 184:136] + node _T_262 = bits(store_data_hi_r, 7, 0) @[lsu_bus_intf.scala 184:158] node _T_263 = mux(_T_259, _T_260, UInt<1>("h00")) @[Mux.scala 27:72] node _T_264 = mux(_T_261, _T_262, UInt<1>("h00")) @[Mux.scala 27:72] node _T_265 = or(_T_263, _T_264) @[Mux.scala 27:72] wire _T_266 : UInt<8> @[Mux.scala 27:72] _T_266 <= _T_265 @[Mux.scala 27:72] - node _T_267 = bits(ld_byte_rhit_lo_hi, 1, 1) @[lsu_bus_intf.scala 185:79] - node _T_268 = bits(store_data_lo_r, 15, 8) @[lsu_bus_intf.scala 185:101] - node _T_269 = bits(ld_byte_rhit_hi_hi, 1, 1) @[lsu_bus_intf.scala 185:136] - node _T_270 = bits(store_data_hi_r, 15, 8) @[lsu_bus_intf.scala 185:158] + node _T_267 = bits(ld_byte_rhit_lo_hi, 1, 1) @[lsu_bus_intf.scala 184:79] + node _T_268 = bits(store_data_lo_r, 15, 8) @[lsu_bus_intf.scala 184:101] + node _T_269 = bits(ld_byte_rhit_hi_hi, 1, 1) @[lsu_bus_intf.scala 184:136] + node _T_270 = bits(store_data_hi_r, 15, 8) @[lsu_bus_intf.scala 184:158] node _T_271 = mux(_T_267, _T_268, UInt<1>("h00")) @[Mux.scala 27:72] node _T_272 = mux(_T_269, _T_270, UInt<1>("h00")) @[Mux.scala 27:72] node _T_273 = or(_T_271, _T_272) @[Mux.scala 27:72] wire _T_274 : UInt<8> @[Mux.scala 27:72] _T_274 <= _T_273 @[Mux.scala 27:72] - node _T_275 = bits(ld_byte_rhit_lo_hi, 2, 2) @[lsu_bus_intf.scala 185:79] - node _T_276 = bits(store_data_lo_r, 23, 16) @[lsu_bus_intf.scala 185:101] - node _T_277 = bits(ld_byte_rhit_hi_hi, 2, 2) @[lsu_bus_intf.scala 185:136] - node _T_278 = bits(store_data_hi_r, 23, 16) @[lsu_bus_intf.scala 185:158] + node _T_275 = bits(ld_byte_rhit_lo_hi, 2, 2) @[lsu_bus_intf.scala 184:79] + node _T_276 = bits(store_data_lo_r, 23, 16) @[lsu_bus_intf.scala 184:101] + node _T_277 = bits(ld_byte_rhit_hi_hi, 2, 2) @[lsu_bus_intf.scala 184:136] + node _T_278 = bits(store_data_hi_r, 23, 16) @[lsu_bus_intf.scala 184:158] node _T_279 = mux(_T_275, _T_276, UInt<1>("h00")) @[Mux.scala 27:72] node _T_280 = mux(_T_277, _T_278, UInt<1>("h00")) @[Mux.scala 27:72] node _T_281 = or(_T_279, _T_280) @[Mux.scala 27:72] wire _T_282 : UInt<8> @[Mux.scala 27:72] _T_282 <= _T_281 @[Mux.scala 27:72] - node _T_283 = bits(ld_byte_rhit_lo_hi, 3, 3) @[lsu_bus_intf.scala 185:79] - node _T_284 = bits(store_data_lo_r, 31, 24) @[lsu_bus_intf.scala 185:101] - node _T_285 = bits(ld_byte_rhit_hi_hi, 3, 3) @[lsu_bus_intf.scala 185:136] - node _T_286 = bits(store_data_hi_r, 31, 24) @[lsu_bus_intf.scala 185:158] + node _T_283 = bits(ld_byte_rhit_lo_hi, 3, 3) @[lsu_bus_intf.scala 184:79] + node _T_284 = bits(store_data_lo_r, 31, 24) @[lsu_bus_intf.scala 184:101] + node _T_285 = bits(ld_byte_rhit_hi_hi, 3, 3) @[lsu_bus_intf.scala 184:136] + node _T_286 = bits(store_data_hi_r, 31, 24) @[lsu_bus_intf.scala 184:158] node _T_287 = mux(_T_283, _T_284, UInt<1>("h00")) @[Mux.scala 27:72] node _T_288 = mux(_T_285, _T_286, UInt<1>("h00")) @[Mux.scala 27:72] node _T_289 = or(_T_287, _T_288) @[Mux.scala 27:72] @@ -101704,117 +101711,117 @@ circuit quasar_wrapper : node _T_291 = cat(_T_290, _T_282) @[Cat.scala 29:58] node _T_292 = cat(_T_291, _T_274) @[Cat.scala 29:58] node _T_293 = cat(_T_292, _T_266) @[Cat.scala 29:58] - ld_fwddata_rpipe_hi <= _T_293 @[lsu_bus_intf.scala 185:27] - node _T_294 = bits(ld_byte_rhit_lo, 0, 0) @[lsu_bus_intf.scala 186:70] - node _T_295 = bits(ld_fwddata_rpipe_lo, 7, 0) @[lsu_bus_intf.scala 186:94] - node _T_296 = bits(ld_fwddata_buf_lo, 7, 0) @[lsu_bus_intf.scala 186:128] - node _T_297 = mux(_T_294, _T_295, _T_296) @[lsu_bus_intf.scala 186:54] - node _T_298 = bits(ld_byte_rhit_lo, 1, 1) @[lsu_bus_intf.scala 186:70] - node _T_299 = bits(ld_fwddata_rpipe_lo, 15, 8) @[lsu_bus_intf.scala 186:94] - node _T_300 = bits(ld_fwddata_buf_lo, 15, 8) @[lsu_bus_intf.scala 186:128] - node _T_301 = mux(_T_298, _T_299, _T_300) @[lsu_bus_intf.scala 186:54] - node _T_302 = bits(ld_byte_rhit_lo, 2, 2) @[lsu_bus_intf.scala 186:70] - node _T_303 = bits(ld_fwddata_rpipe_lo, 23, 16) @[lsu_bus_intf.scala 186:94] - node _T_304 = bits(ld_fwddata_buf_lo, 23, 16) @[lsu_bus_intf.scala 186:128] - node _T_305 = mux(_T_302, _T_303, _T_304) @[lsu_bus_intf.scala 186:54] - node _T_306 = bits(ld_byte_rhit_lo, 3, 3) @[lsu_bus_intf.scala 186:70] - node _T_307 = bits(ld_fwddata_rpipe_lo, 31, 24) @[lsu_bus_intf.scala 186:94] - node _T_308 = bits(ld_fwddata_buf_lo, 31, 24) @[lsu_bus_intf.scala 186:128] - node _T_309 = mux(_T_306, _T_307, _T_308) @[lsu_bus_intf.scala 186:54] + ld_fwddata_rpipe_hi <= _T_293 @[lsu_bus_intf.scala 184:27] + node _T_294 = bits(ld_byte_rhit_lo, 0, 0) @[lsu_bus_intf.scala 185:70] + node _T_295 = bits(ld_fwddata_rpipe_lo, 7, 0) @[lsu_bus_intf.scala 185:94] + node _T_296 = bits(ld_fwddata_buf_lo, 7, 0) @[lsu_bus_intf.scala 185:128] + node _T_297 = mux(_T_294, _T_295, _T_296) @[lsu_bus_intf.scala 185:54] + node _T_298 = bits(ld_byte_rhit_lo, 1, 1) @[lsu_bus_intf.scala 185:70] + node _T_299 = bits(ld_fwddata_rpipe_lo, 15, 8) @[lsu_bus_intf.scala 185:94] + node _T_300 = bits(ld_fwddata_buf_lo, 15, 8) @[lsu_bus_intf.scala 185:128] + node _T_301 = mux(_T_298, _T_299, _T_300) @[lsu_bus_intf.scala 185:54] + node _T_302 = bits(ld_byte_rhit_lo, 2, 2) @[lsu_bus_intf.scala 185:70] + node _T_303 = bits(ld_fwddata_rpipe_lo, 23, 16) @[lsu_bus_intf.scala 185:94] + node _T_304 = bits(ld_fwddata_buf_lo, 23, 16) @[lsu_bus_intf.scala 185:128] + node _T_305 = mux(_T_302, _T_303, _T_304) @[lsu_bus_intf.scala 185:54] + node _T_306 = bits(ld_byte_rhit_lo, 3, 3) @[lsu_bus_intf.scala 185:70] + node _T_307 = bits(ld_fwddata_rpipe_lo, 31, 24) @[lsu_bus_intf.scala 185:94] + node _T_308 = bits(ld_fwddata_buf_lo, 31, 24) @[lsu_bus_intf.scala 185:128] + node _T_309 = mux(_T_306, _T_307, _T_308) @[lsu_bus_intf.scala 185:54] node _T_310 = cat(_T_309, _T_305) @[Cat.scala 29:58] node _T_311 = cat(_T_310, _T_301) @[Cat.scala 29:58] node _T_312 = cat(_T_311, _T_297) @[Cat.scala 29:58] - ld_fwddata_lo <= _T_312 @[lsu_bus_intf.scala 186:27] - node _T_313 = bits(ld_byte_rhit_hi, 0, 0) @[lsu_bus_intf.scala 187:70] - node _T_314 = bits(ld_fwddata_rpipe_hi, 7, 0) @[lsu_bus_intf.scala 187:94] - node _T_315 = bits(ld_fwddata_buf_hi, 7, 0) @[lsu_bus_intf.scala 187:128] - node _T_316 = mux(_T_313, _T_314, _T_315) @[lsu_bus_intf.scala 187:54] - node _T_317 = bits(ld_byte_rhit_hi, 1, 1) @[lsu_bus_intf.scala 187:70] - node _T_318 = bits(ld_fwddata_rpipe_hi, 15, 8) @[lsu_bus_intf.scala 187:94] - node _T_319 = bits(ld_fwddata_buf_hi, 15, 8) @[lsu_bus_intf.scala 187:128] - node _T_320 = mux(_T_317, _T_318, _T_319) @[lsu_bus_intf.scala 187:54] - node _T_321 = bits(ld_byte_rhit_hi, 2, 2) @[lsu_bus_intf.scala 187:70] - node _T_322 = bits(ld_fwddata_rpipe_hi, 23, 16) @[lsu_bus_intf.scala 187:94] - node _T_323 = bits(ld_fwddata_buf_hi, 23, 16) @[lsu_bus_intf.scala 187:128] - node _T_324 = mux(_T_321, _T_322, _T_323) @[lsu_bus_intf.scala 187:54] - node _T_325 = bits(ld_byte_rhit_hi, 3, 3) @[lsu_bus_intf.scala 187:70] - node _T_326 = bits(ld_fwddata_rpipe_hi, 31, 24) @[lsu_bus_intf.scala 187:94] - node _T_327 = bits(ld_fwddata_buf_hi, 31, 24) @[lsu_bus_intf.scala 187:128] - node _T_328 = mux(_T_325, _T_326, _T_327) @[lsu_bus_intf.scala 187:54] + ld_fwddata_lo <= _T_312 @[lsu_bus_intf.scala 185:27] + node _T_313 = bits(ld_byte_rhit_hi, 0, 0) @[lsu_bus_intf.scala 186:70] + node _T_314 = bits(ld_fwddata_rpipe_hi, 7, 0) @[lsu_bus_intf.scala 186:94] + node _T_315 = bits(ld_fwddata_buf_hi, 7, 0) @[lsu_bus_intf.scala 186:128] + node _T_316 = mux(_T_313, _T_314, _T_315) @[lsu_bus_intf.scala 186:54] + node _T_317 = bits(ld_byte_rhit_hi, 1, 1) @[lsu_bus_intf.scala 186:70] + node _T_318 = bits(ld_fwddata_rpipe_hi, 15, 8) @[lsu_bus_intf.scala 186:94] + node _T_319 = bits(ld_fwddata_buf_hi, 15, 8) @[lsu_bus_intf.scala 186:128] + node _T_320 = mux(_T_317, _T_318, _T_319) @[lsu_bus_intf.scala 186:54] + node _T_321 = bits(ld_byte_rhit_hi, 2, 2) @[lsu_bus_intf.scala 186:70] + node _T_322 = bits(ld_fwddata_rpipe_hi, 23, 16) @[lsu_bus_intf.scala 186:94] + node _T_323 = bits(ld_fwddata_buf_hi, 23, 16) @[lsu_bus_intf.scala 186:128] + node _T_324 = mux(_T_321, _T_322, _T_323) @[lsu_bus_intf.scala 186:54] + node _T_325 = bits(ld_byte_rhit_hi, 3, 3) @[lsu_bus_intf.scala 186:70] + node _T_326 = bits(ld_fwddata_rpipe_hi, 31, 24) @[lsu_bus_intf.scala 186:94] + node _T_327 = bits(ld_fwddata_buf_hi, 31, 24) @[lsu_bus_intf.scala 186:128] + node _T_328 = mux(_T_325, _T_326, _T_327) @[lsu_bus_intf.scala 186:54] node _T_329 = cat(_T_328, _T_324) @[Cat.scala 29:58] node _T_330 = cat(_T_329, _T_320) @[Cat.scala 29:58] node _T_331 = cat(_T_330, _T_316) @[Cat.scala 29:58] - ld_fwddata_hi <= _T_331 @[lsu_bus_intf.scala 187:27] - node _T_332 = bits(ld_byte_hit_lo, 0, 0) @[lsu_bus_intf.scala 188:66] - node _T_333 = bits(ldst_byteen_lo_m, 0, 0) @[lsu_bus_intf.scala 188:89] - node _T_334 = eq(_T_333, UInt<1>("h00")) @[lsu_bus_intf.scala 188:72] - node _T_335 = or(_T_332, _T_334) @[lsu_bus_intf.scala 188:70] - node _T_336 = bits(ld_byte_hit_lo, 1, 1) @[lsu_bus_intf.scala 188:66] - node _T_337 = bits(ldst_byteen_lo_m, 1, 1) @[lsu_bus_intf.scala 188:89] - node _T_338 = eq(_T_337, UInt<1>("h00")) @[lsu_bus_intf.scala 188:72] - node _T_339 = or(_T_336, _T_338) @[lsu_bus_intf.scala 188:70] - node _T_340 = bits(ld_byte_hit_lo, 2, 2) @[lsu_bus_intf.scala 188:66] - node _T_341 = bits(ldst_byteen_lo_m, 2, 2) @[lsu_bus_intf.scala 188:89] - node _T_342 = eq(_T_341, UInt<1>("h00")) @[lsu_bus_intf.scala 188:72] - node _T_343 = or(_T_340, _T_342) @[lsu_bus_intf.scala 188:70] - node _T_344 = bits(ld_byte_hit_lo, 3, 3) @[lsu_bus_intf.scala 188:66] - node _T_345 = bits(ldst_byteen_lo_m, 3, 3) @[lsu_bus_intf.scala 188:89] - node _T_346 = eq(_T_345, UInt<1>("h00")) @[lsu_bus_intf.scala 188:72] - node _T_347 = or(_T_344, _T_346) @[lsu_bus_intf.scala 188:70] - node _T_348 = and(_T_335, _T_339) @[lsu_bus_intf.scala 188:111] - node _T_349 = and(_T_348, _T_343) @[lsu_bus_intf.scala 188:111] - node _T_350 = and(_T_349, _T_347) @[lsu_bus_intf.scala 188:111] - ld_full_hit_lo_m <= _T_350 @[lsu_bus_intf.scala 188:27] - node _T_351 = bits(ld_byte_hit_hi, 0, 0) @[lsu_bus_intf.scala 189:66] - node _T_352 = bits(ldst_byteen_hi_m, 0, 0) @[lsu_bus_intf.scala 189:89] - node _T_353 = eq(_T_352, UInt<1>("h00")) @[lsu_bus_intf.scala 189:72] - node _T_354 = or(_T_351, _T_353) @[lsu_bus_intf.scala 189:70] - node _T_355 = bits(ld_byte_hit_hi, 1, 1) @[lsu_bus_intf.scala 189:66] - node _T_356 = bits(ldst_byteen_hi_m, 1, 1) @[lsu_bus_intf.scala 189:89] - node _T_357 = eq(_T_356, UInt<1>("h00")) @[lsu_bus_intf.scala 189:72] - node _T_358 = or(_T_355, _T_357) @[lsu_bus_intf.scala 189:70] - node _T_359 = bits(ld_byte_hit_hi, 2, 2) @[lsu_bus_intf.scala 189:66] - node _T_360 = bits(ldst_byteen_hi_m, 2, 2) @[lsu_bus_intf.scala 189:89] - node _T_361 = eq(_T_360, UInt<1>("h00")) @[lsu_bus_intf.scala 189:72] - node _T_362 = or(_T_359, _T_361) @[lsu_bus_intf.scala 189:70] - node _T_363 = bits(ld_byte_hit_hi, 3, 3) @[lsu_bus_intf.scala 189:66] - node _T_364 = bits(ldst_byteen_hi_m, 3, 3) @[lsu_bus_intf.scala 189:89] - node _T_365 = eq(_T_364, UInt<1>("h00")) @[lsu_bus_intf.scala 189:72] - node _T_366 = or(_T_363, _T_365) @[lsu_bus_intf.scala 189:70] - node _T_367 = and(_T_354, _T_358) @[lsu_bus_intf.scala 189:111] - node _T_368 = and(_T_367, _T_362) @[lsu_bus_intf.scala 189:111] - node _T_369 = and(_T_368, _T_366) @[lsu_bus_intf.scala 189:111] - ld_full_hit_hi_m <= _T_369 @[lsu_bus_intf.scala 189:27] - node _T_370 = and(ld_full_hit_lo_m, ld_full_hit_hi_m) @[lsu_bus_intf.scala 190:47] - node _T_371 = and(_T_370, io.lsu_busreq_m) @[lsu_bus_intf.scala 190:66] - node _T_372 = and(_T_371, io.lsu_pkt_m.bits.load) @[lsu_bus_intf.scala 190:84] - node _T_373 = eq(io.is_sideeffects_m, UInt<1>("h00")) @[lsu_bus_intf.scala 190:111] - node _T_374 = and(_T_372, _T_373) @[lsu_bus_intf.scala 190:109] - ld_full_hit_m <= _T_374 @[lsu_bus_intf.scala 190:27] - node _T_375 = bits(ld_fwddata_hi, 31, 0) @[lsu_bus_intf.scala 191:47] - node _T_376 = bits(ld_fwddata_lo, 31, 0) @[lsu_bus_intf.scala 191:68] + ld_fwddata_hi <= _T_331 @[lsu_bus_intf.scala 186:27] + node _T_332 = bits(ld_byte_hit_lo, 0, 0) @[lsu_bus_intf.scala 187:66] + node _T_333 = bits(ldst_byteen_lo_m, 0, 0) @[lsu_bus_intf.scala 187:89] + node _T_334 = eq(_T_333, UInt<1>("h00")) @[lsu_bus_intf.scala 187:72] + node _T_335 = or(_T_332, _T_334) @[lsu_bus_intf.scala 187:70] + node _T_336 = bits(ld_byte_hit_lo, 1, 1) @[lsu_bus_intf.scala 187:66] + node _T_337 = bits(ldst_byteen_lo_m, 1, 1) @[lsu_bus_intf.scala 187:89] + node _T_338 = eq(_T_337, UInt<1>("h00")) @[lsu_bus_intf.scala 187:72] + node _T_339 = or(_T_336, _T_338) @[lsu_bus_intf.scala 187:70] + node _T_340 = bits(ld_byte_hit_lo, 2, 2) @[lsu_bus_intf.scala 187:66] + node _T_341 = bits(ldst_byteen_lo_m, 2, 2) @[lsu_bus_intf.scala 187:89] + node _T_342 = eq(_T_341, UInt<1>("h00")) @[lsu_bus_intf.scala 187:72] + node _T_343 = or(_T_340, _T_342) @[lsu_bus_intf.scala 187:70] + node _T_344 = bits(ld_byte_hit_lo, 3, 3) @[lsu_bus_intf.scala 187:66] + node _T_345 = bits(ldst_byteen_lo_m, 3, 3) @[lsu_bus_intf.scala 187:89] + node _T_346 = eq(_T_345, UInt<1>("h00")) @[lsu_bus_intf.scala 187:72] + node _T_347 = or(_T_344, _T_346) @[lsu_bus_intf.scala 187:70] + node _T_348 = and(_T_335, _T_339) @[lsu_bus_intf.scala 187:111] + node _T_349 = and(_T_348, _T_343) @[lsu_bus_intf.scala 187:111] + node _T_350 = and(_T_349, _T_347) @[lsu_bus_intf.scala 187:111] + ld_full_hit_lo_m <= _T_350 @[lsu_bus_intf.scala 187:27] + node _T_351 = bits(ld_byte_hit_hi, 0, 0) @[lsu_bus_intf.scala 188:66] + node _T_352 = bits(ldst_byteen_hi_m, 0, 0) @[lsu_bus_intf.scala 188:89] + node _T_353 = eq(_T_352, UInt<1>("h00")) @[lsu_bus_intf.scala 188:72] + node _T_354 = or(_T_351, _T_353) @[lsu_bus_intf.scala 188:70] + node _T_355 = bits(ld_byte_hit_hi, 1, 1) @[lsu_bus_intf.scala 188:66] + node _T_356 = bits(ldst_byteen_hi_m, 1, 1) @[lsu_bus_intf.scala 188:89] + node _T_357 = eq(_T_356, UInt<1>("h00")) @[lsu_bus_intf.scala 188:72] + node _T_358 = or(_T_355, _T_357) @[lsu_bus_intf.scala 188:70] + node _T_359 = bits(ld_byte_hit_hi, 2, 2) @[lsu_bus_intf.scala 188:66] + node _T_360 = bits(ldst_byteen_hi_m, 2, 2) @[lsu_bus_intf.scala 188:89] + node _T_361 = eq(_T_360, UInt<1>("h00")) @[lsu_bus_intf.scala 188:72] + node _T_362 = or(_T_359, _T_361) @[lsu_bus_intf.scala 188:70] + node _T_363 = bits(ld_byte_hit_hi, 3, 3) @[lsu_bus_intf.scala 188:66] + node _T_364 = bits(ldst_byteen_hi_m, 3, 3) @[lsu_bus_intf.scala 188:89] + node _T_365 = eq(_T_364, UInt<1>("h00")) @[lsu_bus_intf.scala 188:72] + node _T_366 = or(_T_363, _T_365) @[lsu_bus_intf.scala 188:70] + node _T_367 = and(_T_354, _T_358) @[lsu_bus_intf.scala 188:111] + node _T_368 = and(_T_367, _T_362) @[lsu_bus_intf.scala 188:111] + node _T_369 = and(_T_368, _T_366) @[lsu_bus_intf.scala 188:111] + ld_full_hit_hi_m <= _T_369 @[lsu_bus_intf.scala 188:27] + node _T_370 = and(ld_full_hit_lo_m, ld_full_hit_hi_m) @[lsu_bus_intf.scala 189:47] + node _T_371 = and(_T_370, io.lsu_busreq_m) @[lsu_bus_intf.scala 189:66] + node _T_372 = and(_T_371, io.lsu_pkt_m.bits.load) @[lsu_bus_intf.scala 189:84] + node _T_373 = eq(io.is_sideeffects_m, UInt<1>("h00")) @[lsu_bus_intf.scala 189:111] + node _T_374 = and(_T_372, _T_373) @[lsu_bus_intf.scala 189:109] + ld_full_hit_m <= _T_374 @[lsu_bus_intf.scala 189:27] + node _T_375 = bits(ld_fwddata_hi, 31, 0) @[lsu_bus_intf.scala 190:47] + node _T_376 = bits(ld_fwddata_lo, 31, 0) @[lsu_bus_intf.scala 190:68] node _T_377 = cat(_T_375, _T_376) @[Cat.scala 29:58] - node _T_378 = bits(io.lsu_addr_m, 1, 0) @[lsu_bus_intf.scala 191:97] - node _T_379 = mul(UInt<4>("h08"), _T_378) @[lsu_bus_intf.scala 191:83] - node _T_380 = dshr(_T_377, _T_379) @[lsu_bus_intf.scala 191:76] - ld_fwddata_m <= _T_380 @[lsu_bus_intf.scala 191:27] - node _T_381 = bits(ld_fwddata_m, 31, 0) @[lsu_bus_intf.scala 192:42] - io.bus_read_data_m <= _T_381 @[lsu_bus_intf.scala 192:27] - reg _T_382 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_intf.scala 195:32] - _T_382 <= io.lsu_bus_clk_en @[lsu_bus_intf.scala 195:32] - lsu_bus_clk_en_q <= _T_382 @[lsu_bus_intf.scala 195:22] - reg _T_383 : UInt<1>, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_intf.scala 198:27] - _T_383 <= ldst_dual_d @[lsu_bus_intf.scala 198:27] - ldst_dual_m <= _T_383 @[lsu_bus_intf.scala 198:17] - reg _T_384 : UInt<1>, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_intf.scala 201:33] - _T_384 <= ldst_dual_m @[lsu_bus_intf.scala 201:33] - ldst_dual_r <= _T_384 @[lsu_bus_intf.scala 201:23] - reg _T_385 : UInt<1>, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_intf.scala 202:33] - _T_385 <= io.is_sideeffects_m @[lsu_bus_intf.scala 202:33] - is_sideeffects_r <= _T_385 @[lsu_bus_intf.scala 202:23] - reg _T_386 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<4>("h00"))) @[lsu_bus_intf.scala 203:33] - _T_386 <= ldst_byteen_m @[lsu_bus_intf.scala 203:33] - ldst_byteen_r <= _T_386 @[lsu_bus_intf.scala 203:23] + node _T_378 = bits(io.lsu_addr_m, 1, 0) @[lsu_bus_intf.scala 190:97] + node _T_379 = mul(UInt<4>("h08"), _T_378) @[lsu_bus_intf.scala 190:83] + node _T_380 = dshr(_T_377, _T_379) @[lsu_bus_intf.scala 190:76] + ld_fwddata_m <= _T_380 @[lsu_bus_intf.scala 190:27] + node _T_381 = bits(ld_fwddata_m, 31, 0) @[lsu_bus_intf.scala 191:42] + io.bus_read_data_m <= _T_381 @[lsu_bus_intf.scala 191:27] + reg _T_382 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_intf.scala 194:32] + _T_382 <= io.lsu_bus_clk_en @[lsu_bus_intf.scala 194:32] + lsu_bus_clk_en_q <= _T_382 @[lsu_bus_intf.scala 194:22] + reg _T_383 : UInt<1>, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_intf.scala 197:27] + _T_383 <= ldst_dual_d @[lsu_bus_intf.scala 197:27] + ldst_dual_m <= _T_383 @[lsu_bus_intf.scala 197:17] + reg _T_384 : UInt<1>, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_intf.scala 200:33] + _T_384 <= ldst_dual_m @[lsu_bus_intf.scala 200:33] + ldst_dual_r <= _T_384 @[lsu_bus_intf.scala 200:23] + reg _T_385 : UInt<1>, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_intf.scala 201:33] + _T_385 <= io.is_sideeffects_m @[lsu_bus_intf.scala 201:33] + is_sideeffects_r <= _T_385 @[lsu_bus_intf.scala 201:23] + reg _T_386 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<4>("h00"))) @[lsu_bus_intf.scala 202:33] + _T_386 <= ldst_byteen_m @[lsu_bus_intf.scala 202:33] + ldst_byteen_r <= _T_386 @[lsu_bus_intf.scala 202:23] module lsu : input clock : Clock @@ -109048,4831 +109055,6 @@ circuit quasar_wrapper : clkhdr.EN <= io.en @[lib.scala 337:18] clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - extmodule gated_latch_849 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_849 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_849 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_850 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_850 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_850 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_851 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_851 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_851 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_852 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_852 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_852 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_853 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_853 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_853 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_854 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_854 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_854 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_855 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_855 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_855 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_856 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_856 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_856 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_857 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_857 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_857 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_858 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_858 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_858 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - module axi4_to_ahb : - input clock : Clock - input reset : AsyncReset - output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ahb : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}} - - wire buf_rst : UInt<1> - buf_rst <= UInt<1>("h00") - buf_rst <= UInt<1>("h00") @[axi4_to_ahb.scala 21:11] - io.ahb.out.htrans <= UInt<1>("h00") @[axi4_to_ahb.scala 22:21] - wire buf_state_en : UInt<1> - buf_state_en <= UInt<1>("h00") - wire ahbm_clk : Clock @[axi4_to_ahb.scala 24:22] - wire ahbm_addr_clk : Clock @[axi4_to_ahb.scala 25:27] - wire ahbm_data_clk : Clock @[axi4_to_ahb.scala 26:27] - wire buf_state : UInt<3> - buf_state <= UInt<3>("h00") - wire buf_nxtstate : UInt<3> - buf_nxtstate <= UInt<3>("h00") - node _T = bits(buf_state_en, 0, 0) @[axi4_to_ahb.scala 30:70] - node _T_1 = mux(_T, buf_nxtstate, buf_state) @[axi4_to_ahb.scala 30:50] - node _T_2 = eq(buf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 30:108] - node _T_3 = bits(_T_2, 0, 0) @[Bitwise.scala 72:15] - node _T_4 = mux(_T_3, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_5 = and(_T_1, _T_4) @[axi4_to_ahb.scala 30:98] - reg _T_6 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 30:45] - _T_6 <= _T_5 @[axi4_to_ahb.scala 30:45] - buf_state <= _T_6 @[axi4_to_ahb.scala 30:13] - wire slave_valid : UInt<1> - slave_valid <= UInt<1>("h00") - wire slave_ready : UInt<1> - slave_ready <= UInt<1>("h00") - wire slave_tag : UInt<1> - slave_tag <= UInt<1>("h00") - wire slave_rdata : UInt<64> - slave_rdata <= UInt<64>("h00") - wire slave_opc : UInt<4> - slave_opc <= UInt<4>("h00") - wire wrbuf_en : UInt<1> - wrbuf_en <= UInt<1>("h00") - wire wrbuf_data_en : UInt<1> - wrbuf_data_en <= UInt<1>("h00") - wire wrbuf_cmd_sent : UInt<1> - wrbuf_cmd_sent <= UInt<1>("h00") - wire wrbuf_rst : UInt<1> - wrbuf_rst <= UInt<1>("h00") - wire wrbuf_vld : UInt<1> - wrbuf_vld <= UInt<1>("h00") - wire wrbuf_data_vld : UInt<1> - wrbuf_data_vld <= UInt<1>("h00") - wire wrbuf_tag : UInt<1> - wrbuf_tag <= UInt<1>("h00") - wire wrbuf_size : UInt<3> - wrbuf_size <= UInt<3>("h00") - wire wrbuf_addr : UInt<32> - wrbuf_addr <= UInt<32>("h00") - wire wrbuf_data : UInt<64> - wrbuf_data <= UInt<64>("h00") - wire wrbuf_byteen : UInt<8> - wrbuf_byteen <= UInt<8>("h00") - wire bus_write_clk_en : UInt<1> - bus_write_clk_en <= UInt<1>("h00") - wire bus_clk : Clock @[axi4_to_ahb.scala 50:21] - wire bus_write_clk : Clock @[axi4_to_ahb.scala 51:27] - wire master_valid : UInt<1> - master_valid <= UInt<1>("h00") - wire master_ready : UInt<1> - master_ready <= UInt<1>("h00") - wire master_tag : UInt<1> - master_tag <= UInt<1>("h00") - wire master_addr : UInt<32> - master_addr <= UInt<32>("h00") - wire master_wdata : UInt<64> - master_wdata <= UInt<64>("h00") - wire master_size : UInt<3> - master_size <= UInt<3>("h00") - wire master_opc : UInt<3> - master_opc <= UInt<3>("h00") - wire master_byteen : UInt<8> - master_byteen <= UInt<8>("h00") - wire buf_addr : UInt<32> - buf_addr <= UInt<32>("h00") - wire buf_size : UInt<2> - buf_size <= UInt<2>("h00") - wire buf_write : UInt<1> - buf_write <= UInt<1>("h00") - wire buf_byteen : UInt<8> - buf_byteen <= UInt<8>("h00") - wire buf_aligned : UInt<1> - buf_aligned <= UInt<1>("h00") - wire buf_data : UInt<64> - buf_data <= UInt<64>("h00") - wire buf_tag : UInt<1> - buf_tag <= UInt<1>("h00") - wire buf_tag_in : UInt<1> - buf_tag_in <= UInt<1>("h00") - wire buf_addr_in : UInt<32> - buf_addr_in <= UInt<32>("h00") - wire buf_byteen_in : UInt<8> - buf_byteen_in <= UInt<8>("h00") - wire buf_data_in : UInt<64> - buf_data_in <= UInt<64>("h00") - wire buf_write_in : UInt<1> - buf_write_in <= UInt<1>("h00") - wire buf_aligned_in : UInt<1> - buf_aligned_in <= UInt<1>("h00") - wire buf_size_in : UInt<3> - buf_size_in <= UInt<3>("h00") - wire buf_wr_en : UInt<1> - buf_wr_en <= UInt<1>("h00") - wire buf_data_wr_en : UInt<1> - buf_data_wr_en <= UInt<1>("h00") - wire slvbuf_error_en : UInt<1> - slvbuf_error_en <= UInt<1>("h00") - wire wr_cmd_vld : UInt<1> - wr_cmd_vld <= UInt<1>("h00") - wire cmd_done_rst : UInt<1> - cmd_done_rst <= UInt<1>("h00") - wire cmd_done : UInt<1> - cmd_done <= UInt<1>("h00") - wire cmd_doneQ : UInt<1> - cmd_doneQ <= UInt<1>("h00") - wire trxn_done : UInt<1> - trxn_done <= UInt<1>("h00") - wire buf_cmd_byte_ptr : UInt<3> - buf_cmd_byte_ptr <= UInt<3>("h00") - wire buf_cmd_byte_ptrQ : UInt<3> - buf_cmd_byte_ptrQ <= UInt<3>("h00") - wire buf_cmd_nxtbyte_ptr : UInt<3> - buf_cmd_nxtbyte_ptr <= UInt<3>("h00") - wire buf_cmd_byte_ptr_en : UInt<1> - buf_cmd_byte_ptr_en <= UInt<1>("h00") - wire found : UInt<1> - found <= UInt<1>("h00") - wire slave_valid_pre : UInt<1> - slave_valid_pre <= UInt<1>("h00") - wire ahb_hready_q : UInt<1> - ahb_hready_q <= UInt<1>("h00") - wire ahb_hresp_q : UInt<1> - ahb_hresp_q <= UInt<1>("h00") - wire ahb_htrans_q : UInt<2> - ahb_htrans_q <= UInt<2>("h00") - wire ahb_hwrite_q : UInt<1> - ahb_hwrite_q <= UInt<1>("h00") - wire ahb_hrdata_q : UInt<64> - ahb_hrdata_q <= UInt<64>("h00") - wire slvbuf_write : UInt<1> - slvbuf_write <= UInt<1>("h00") - wire slvbuf_error : UInt<1> - slvbuf_error <= UInt<1>("h00") - wire slvbuf_tag : UInt<1> - slvbuf_tag <= UInt<1>("h00") - wire slvbuf_error_in : UInt<1> - slvbuf_error_in <= UInt<1>("h00") - wire slvbuf_wr_en : UInt<1> - slvbuf_wr_en <= UInt<1>("h00") - wire bypass_en : UInt<1> - bypass_en <= UInt<1>("h00") - wire rd_bypass_idle : UInt<1> - rd_bypass_idle <= UInt<1>("h00") - wire last_addr_en : UInt<1> - last_addr_en <= UInt<1>("h00") - wire last_bus_addr : UInt<32> - last_bus_addr <= UInt<32>("h00") - wire buf_clken : UInt<1> - buf_clken <= UInt<1>("h00") - wire slvbuf_clken : UInt<1> - slvbuf_clken <= UInt<1>("h00") - wire ahbm_addr_clken : UInt<1> - ahbm_addr_clken <= UInt<1>("h00") - wire ahbm_data_clken : UInt<1> - ahbm_data_clken <= UInt<1>("h00") - wire buf_clk : Clock @[axi4_to_ahb.scala 118:21] - node _T_7 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 139:27] - wr_cmd_vld <= _T_7 @[axi4_to_ahb.scala 139:14] - node _T_8 = or(wr_cmd_vld, io.axi.ar.valid) @[axi4_to_ahb.scala 140:30] - master_valid <= _T_8 @[axi4_to_ahb.scala 140:16] - node _T_9 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 141:38] - node _T_10 = bits(wrbuf_tag, 0, 0) @[axi4_to_ahb.scala 141:51] - node _T_11 = bits(io.axi.ar.bits.id, 0, 0) @[axi4_to_ahb.scala 141:82] - node _T_12 = mux(_T_9, _T_10, _T_11) @[axi4_to_ahb.scala 141:20] - master_tag <= _T_12 @[axi4_to_ahb.scala 141:14] - node _T_13 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 142:38] - node _T_14 = mux(_T_13, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 142:20] - master_opc <= _T_14 @[axi4_to_ahb.scala 142:14] - node _T_15 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 143:39] - node _T_16 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 143:53] - node _T_17 = bits(io.axi.ar.bits.addr, 31, 0) @[axi4_to_ahb.scala 143:81] - node _T_18 = mux(_T_15, _T_16, _T_17) @[axi4_to_ahb.scala 143:21] - master_addr <= _T_18 @[axi4_to_ahb.scala 143:15] - node _T_19 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 144:39] - node _T_20 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 144:53] - node _T_21 = bits(io.axi.ar.bits.size, 2, 0) @[axi4_to_ahb.scala 144:80] - node _T_22 = mux(_T_19, _T_20, _T_21) @[axi4_to_ahb.scala 144:21] - master_size <= _T_22 @[axi4_to_ahb.scala 144:15] - node _T_23 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 145:32] - master_byteen <= _T_23 @[axi4_to_ahb.scala 145:17] - node _T_24 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 146:29] - master_wdata <= _T_24 @[axi4_to_ahb.scala 146:16] - node _T_25 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 149:33] - node _T_26 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 149:58] - node _T_27 = and(_T_25, _T_26) @[axi4_to_ahb.scala 149:47] - io.axi.b.valid <= _T_27 @[axi4_to_ahb.scala 149:18] - node _T_28 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 150:38] - node _T_29 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 150:65] - node _T_30 = mux(_T_29, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 150:55] - node _T_31 = mux(_T_28, UInt<2>("h02"), _T_30) @[axi4_to_ahb.scala 150:28] - io.axi.b.bits.resp <= _T_31 @[axi4_to_ahb.scala 150:22] - node _T_32 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 151:32] - io.axi.b.bits.id <= _T_32 @[axi4_to_ahb.scala 151:20] - node _T_33 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 153:33] - node _T_34 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 153:59] - node _T_35 = eq(_T_34, UInt<1>("h00")) @[axi4_to_ahb.scala 153:66] - node _T_36 = and(_T_33, _T_35) @[axi4_to_ahb.scala 153:47] - io.axi.r.valid <= _T_36 @[axi4_to_ahb.scala 153:18] - node _T_37 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 154:38] - node _T_38 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 154:65] - node _T_39 = mux(_T_38, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 154:55] - node _T_40 = mux(_T_37, UInt<2>("h02"), _T_39) @[axi4_to_ahb.scala 154:28] - io.axi.r.bits.resp <= _T_40 @[axi4_to_ahb.scala 154:22] - node _T_41 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 155:32] - io.axi.r.bits.id <= _T_41 @[axi4_to_ahb.scala 155:20] - node _T_42 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 156:36] - io.axi.r.bits.data <= _T_42 @[axi4_to_ahb.scala 156:22] - node _T_43 = and(io.axi.b.ready, io.axi.r.ready) @[axi4_to_ahb.scala 157:33] - slave_ready <= _T_43 @[axi4_to_ahb.scala 157:15] - node _T_44 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 160:57] - node _T_45 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 160:94] - node _T_46 = or(_T_44, _T_45) @[axi4_to_ahb.scala 160:76] - node _T_47 = and(io.bus_clk_en, _T_46) @[axi4_to_ahb.scala 160:37] - bus_write_clk_en <= _T_47 @[axi4_to_ahb.scala 160:20] - inst rvclkhdr of rvclkhdr_849 @[lib.scala 343:22] - rvclkhdr.clock <= clock - rvclkhdr.reset <= reset - rvclkhdr.io.clk <= clock @[lib.scala 344:17] - rvclkhdr.io.en <= io.bus_clk_en @[lib.scala 345:16] - rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - bus_clk <= rvclkhdr.io.l1clk @[axi4_to_ahb.scala 162:11] - node _T_48 = bits(bus_write_clk_en, 0, 0) @[axi4_to_ahb.scala 163:59] - inst rvclkhdr_1 of rvclkhdr_850 @[lib.scala 343:22] - rvclkhdr_1.clock <= clock - rvclkhdr_1.reset <= reset - rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_1.io.en <= _T_48 @[lib.scala 345:16] - rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - bus_write_clk <= rvclkhdr_1.io.l1clk @[axi4_to_ahb.scala 163:17] - node _T_49 = eq(UInt<3>("h00"), buf_state) @[Conditional.scala 37:30] - when _T_49 : @[Conditional.scala 40:58] - master_ready <= UInt<1>("h01") @[axi4_to_ahb.scala 167:20] - node _T_50 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 168:34] - node _T_51 = eq(_T_50, UInt<1>("h01")) @[axi4_to_ahb.scala 168:41] - buf_write_in <= _T_51 @[axi4_to_ahb.scala 168:20] - node _T_52 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 169:46] - node _T_53 = mux(_T_52, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 169:26] - buf_nxtstate <= _T_53 @[axi4_to_ahb.scala 169:20] - node _T_54 = and(master_valid, UInt<1>("h01")) @[axi4_to_ahb.scala 170:36] - buf_state_en <= _T_54 @[axi4_to_ahb.scala 170:20] - buf_wr_en <= buf_state_en @[axi4_to_ahb.scala 171:17] - node _T_55 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 172:54] - node _T_56 = and(buf_state_en, _T_55) @[axi4_to_ahb.scala 172:38] - buf_data_wr_en <= _T_56 @[axi4_to_ahb.scala 172:22] - buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 173:27] - node _T_57 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 175:50] - node _T_58 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 175:94] - node _T_59 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_60 = tail(_T_59, 1) @[axi4_to_ahb.scala 135:52] - node _T_61 = mux(UInt<1>("h00"), _T_60, UInt<3>("h00")) @[axi4_to_ahb.scala 135:24] - node _T_62 = bits(_T_58, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_63 = geq(UInt<1>("h00"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_64 = and(_T_62, _T_63) @[axi4_to_ahb.scala 136:48] - node _T_65 = bits(_T_58, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_66 = geq(UInt<1>("h01"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_67 = and(_T_65, _T_66) @[axi4_to_ahb.scala 136:48] - node _T_68 = bits(_T_58, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_69 = geq(UInt<2>("h02"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_70 = and(_T_68, _T_69) @[axi4_to_ahb.scala 136:48] - node _T_71 = bits(_T_58, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_72 = geq(UInt<2>("h03"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_73 = and(_T_71, _T_72) @[axi4_to_ahb.scala 136:48] - node _T_74 = bits(_T_58, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_75 = geq(UInt<3>("h04"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_76 = and(_T_74, _T_75) @[axi4_to_ahb.scala 136:48] - node _T_77 = bits(_T_58, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_78 = geq(UInt<3>("h05"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_79 = and(_T_77, _T_78) @[axi4_to_ahb.scala 136:48] - node _T_80 = bits(_T_58, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_81 = geq(UInt<3>("h06"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_82 = and(_T_80, _T_81) @[axi4_to_ahb.scala 136:48] - node _T_83 = bits(_T_58, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_84 = geq(UInt<3>("h07"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_85 = and(_T_83, _T_84) @[axi4_to_ahb.scala 136:48] - node _T_86 = mux(_T_85, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_87 = mux(_T_82, UInt<3>("h06"), _T_86) @[Mux.scala 98:16] - node _T_88 = mux(_T_79, UInt<3>("h05"), _T_87) @[Mux.scala 98:16] - node _T_89 = mux(_T_76, UInt<3>("h04"), _T_88) @[Mux.scala 98:16] - node _T_90 = mux(_T_73, UInt<2>("h03"), _T_89) @[Mux.scala 98:16] - node _T_91 = mux(_T_70, UInt<2>("h02"), _T_90) @[Mux.scala 98:16] - node _T_92 = mux(_T_67, UInt<1>("h01"), _T_91) @[Mux.scala 98:16] - node _T_93 = mux(_T_64, UInt<1>("h00"), _T_92) @[Mux.scala 98:16] - node _T_94 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 175:124] - node _T_95 = mux(_T_57, _T_93, _T_94) @[axi4_to_ahb.scala 175:30] - buf_cmd_byte_ptr <= _T_95 @[axi4_to_ahb.scala 175:24] - bypass_en <= buf_state_en @[axi4_to_ahb.scala 176:17] - node _T_96 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 177:51] - node _T_97 = and(bypass_en, _T_96) @[axi4_to_ahb.scala 177:35] - rd_bypass_idle <= _T_97 @[axi4_to_ahb.scala 177:22] - node _T_98 = bits(bypass_en, 0, 0) @[Bitwise.scala 72:15] - node _T_99 = mux(_T_98, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_100 = and(_T_99, UInt<2>("h02")) @[axi4_to_ahb.scala 178:49] - io.ahb.out.htrans <= _T_100 @[axi4_to_ahb.scala 178:25] - skip @[Conditional.scala 40:58] - else : @[Conditional.scala 39:67] - node _T_101 = eq(UInt<3>("h01"), buf_state) @[Conditional.scala 37:30] - when _T_101 : @[Conditional.scala 39:67] - node _T_102 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 182:54] - node _T_103 = eq(_T_102, UInt<1>("h00")) @[axi4_to_ahb.scala 182:61] - node _T_104 = and(master_valid, _T_103) @[axi4_to_ahb.scala 182:41] - node _T_105 = bits(_T_104, 0, 0) @[axi4_to_ahb.scala 182:82] - node _T_106 = mux(_T_105, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 182:26] - buf_nxtstate <= _T_106 @[axi4_to_ahb.scala 182:20] - node _T_107 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 183:51] - node _T_108 = neq(_T_107, UInt<1>("h00")) @[axi4_to_ahb.scala 183:58] - node _T_109 = and(ahb_hready_q, _T_108) @[axi4_to_ahb.scala 183:36] - node _T_110 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 183:72] - node _T_111 = and(_T_109, _T_110) @[axi4_to_ahb.scala 183:70] - buf_state_en <= _T_111 @[axi4_to_ahb.scala 183:20] - node _T_112 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 184:34] - node _T_113 = and(buf_state_en, _T_112) @[axi4_to_ahb.scala 184:32] - cmd_done <= _T_113 @[axi4_to_ahb.scala 184:16] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 185:20] - node _T_114 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 186:52] - node _T_115 = neq(_T_114, UInt<1>("h00")) @[axi4_to_ahb.scala 186:59] - node _T_116 = and(ahb_hready_q, _T_115) @[axi4_to_ahb.scala 186:37] - node _T_117 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 186:73] - node _T_118 = and(_T_116, _T_117) @[axi4_to_ahb.scala 186:71] - node _T_119 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 186:122] - node _T_120 = eq(_T_119, UInt<1>("h00")) @[axi4_to_ahb.scala 186:129] - node _T_121 = and(master_valid, _T_120) @[axi4_to_ahb.scala 186:109] - node _T_122 = bits(_T_121, 0, 0) @[axi4_to_ahb.scala 186:150] - node _T_123 = mux(_T_122, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 186:94] - node _T_124 = eq(_T_123, UInt<3>("h06")) @[axi4_to_ahb.scala 186:174] - node _T_125 = and(_T_118, _T_124) @[axi4_to_ahb.scala 186:88] - master_ready <= _T_125 @[axi4_to_ahb.scala 186:20] - buf_wr_en <= master_ready @[axi4_to_ahb.scala 187:17] - node _T_126 = and(master_ready, master_valid) @[axi4_to_ahb.scala 188:33] - bypass_en <= _T_126 @[axi4_to_ahb.scala 188:17] - node _T_127 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 189:47] - node _T_128 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 189:62] - node _T_129 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 189:78] - node _T_130 = mux(_T_127, _T_128, _T_129) @[axi4_to_ahb.scala 189:30] - buf_cmd_byte_ptr <= _T_130 @[axi4_to_ahb.scala 189:24] - node _T_131 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 190:48] - node _T_132 = or(_T_131, bypass_en) @[axi4_to_ahb.scala 190:62] - node _T_133 = bits(_T_132, 0, 0) @[Bitwise.scala 72:15] - node _T_134 = mux(_T_133, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_135 = and(UInt<2>("h02"), _T_134) @[axi4_to_ahb.scala 190:36] - io.ahb.out.htrans <= _T_135 @[axi4_to_ahb.scala 190:25] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_136 = eq(UInt<3>("h06"), buf_state) @[Conditional.scala 37:30] - when _T_136 : @[Conditional.scala 39:67] - node _T_137 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 194:39] - node _T_138 = and(ahb_hready_q, _T_137) @[axi4_to_ahb.scala 194:37] - node _T_139 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 194:82] - node _T_140 = eq(_T_139, UInt<1>("h01")) @[axi4_to_ahb.scala 194:89] - node _T_141 = and(master_valid, _T_140) @[axi4_to_ahb.scala 194:70] - node _T_142 = not(_T_141) @[axi4_to_ahb.scala 194:55] - node _T_143 = and(_T_138, _T_142) @[axi4_to_ahb.scala 194:53] - master_ready <= _T_143 @[axi4_to_ahb.scala 194:20] - node _T_144 = and(master_valid, master_ready) @[axi4_to_ahb.scala 195:34] - node _T_145 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 195:62] - node _T_146 = eq(_T_145, UInt<1>("h00")) @[axi4_to_ahb.scala 195:69] - node _T_147 = and(_T_144, _T_146) @[axi4_to_ahb.scala 195:49] - buf_wr_en <= _T_147 @[axi4_to_ahb.scala 195:17] - node _T_148 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 196:45] - node _T_149 = and(master_valid, master_ready) @[axi4_to_ahb.scala 196:82] - node _T_150 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 196:110] - node _T_151 = eq(_T_150, UInt<1>("h00")) @[axi4_to_ahb.scala 196:117] - node _T_152 = and(_T_149, _T_151) @[axi4_to_ahb.scala 196:97] - node _T_153 = bits(_T_152, 0, 0) @[axi4_to_ahb.scala 196:138] - node _T_154 = mux(_T_153, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 196:67] - node _T_155 = mux(_T_148, UInt<3>("h07"), _T_154) @[axi4_to_ahb.scala 196:26] - buf_nxtstate <= _T_155 @[axi4_to_ahb.scala 196:20] - node _T_156 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 197:37] - buf_state_en <= _T_156 @[axi4_to_ahb.scala 197:20] - buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 198:22] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 199:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 200:23] - node _T_157 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 201:41] - node _T_158 = and(buf_state_en, _T_157) @[axi4_to_ahb.scala 201:39] - slave_valid_pre <= _T_158 @[axi4_to_ahb.scala 201:23] - node _T_159 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 202:34] - node _T_160 = and(buf_state_en, _T_159) @[axi4_to_ahb.scala 202:32] - cmd_done <= _T_160 @[axi4_to_ahb.scala 202:16] - node _T_161 = and(master_ready, master_valid) @[axi4_to_ahb.scala 203:33] - node _T_162 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 203:64] - node _T_163 = and(_T_161, _T_162) @[axi4_to_ahb.scala 203:48] - node _T_164 = and(_T_163, buf_state_en) @[axi4_to_ahb.scala 203:79] - bypass_en <= _T_164 @[axi4_to_ahb.scala 203:17] - node _T_165 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 204:47] - node _T_166 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 204:62] - node _T_167 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 204:78] - node _T_168 = mux(_T_165, _T_166, _T_167) @[axi4_to_ahb.scala 204:30] - buf_cmd_byte_ptr <= _T_168 @[axi4_to_ahb.scala 204:24] - node _T_169 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 205:63] - node _T_170 = and(_T_169, buf_state_en) @[axi4_to_ahb.scala 205:78] - node _T_171 = eq(_T_170, UInt<1>("h00")) @[axi4_to_ahb.scala 205:47] - node _T_172 = bits(_T_171, 0, 0) @[Bitwise.scala 72:15] - node _T_173 = mux(_T_172, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_174 = and(UInt<2>("h02"), _T_173) @[axi4_to_ahb.scala 205:36] - io.ahb.out.htrans <= _T_174 @[axi4_to_ahb.scala 205:25] - slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 206:20] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_175 = eq(UInt<3>("h07"), buf_state) @[Conditional.scala 37:30] - when _T_175 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 210:20] - node _T_176 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 211:51] - node _T_177 = neq(_T_176, UInt<1>("h00")) @[axi4_to_ahb.scala 211:58] - node _T_178 = and(ahb_hready_q, _T_177) @[axi4_to_ahb.scala 211:36] - node _T_179 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 211:72] - node _T_180 = and(_T_178, _T_179) @[axi4_to_ahb.scala 211:70] - buf_state_en <= _T_180 @[axi4_to_ahb.scala 211:20] - slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 212:23] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 213:20] - node _T_181 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 214:35] - buf_cmd_byte_ptr <= _T_181 @[axi4_to_ahb.scala 214:24] - node _T_182 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 215:51] - node _T_183 = bits(_T_182, 0, 0) @[Bitwise.scala 72:15] - node _T_184 = mux(_T_183, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_185 = and(UInt<2>("h02"), _T_184) @[axi4_to_ahb.scala 215:41] - io.ahb.out.htrans <= _T_185 @[axi4_to_ahb.scala 215:25] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_186 = eq(UInt<3>("h03"), buf_state) @[Conditional.scala 37:30] - when _T_186 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 219:20] - node _T_187 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 220:37] - buf_state_en <= _T_187 @[axi4_to_ahb.scala 220:20] - buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 221:22] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 222:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 223:23] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 224:20] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_188 = eq(UInt<3>("h02"), buf_state) @[Conditional.scala 37:30] - when _T_188 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 228:20] - node _T_189 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 229:33] - node _T_190 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 229:63] - node _T_191 = neq(_T_190, UInt<1>("h00")) @[axi4_to_ahb.scala 229:70] - node _T_192 = and(_T_189, _T_191) @[axi4_to_ahb.scala 229:48] - trxn_done <= _T_192 @[axi4_to_ahb.scala 229:17] - buf_state_en <= trxn_done @[axi4_to_ahb.scala 230:20] - buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 231:27] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 232:20] - node _T_193 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 233:47] - node _T_194 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 233:85] - node _T_195 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 233:103] - node _T_196 = add(_T_194, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_197 = tail(_T_196, 1) @[axi4_to_ahb.scala 135:52] - node _T_198 = mux(UInt<1>("h01"), _T_197, _T_194) @[axi4_to_ahb.scala 135:24] - node _T_199 = bits(_T_195, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_200 = geq(UInt<1>("h00"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_201 = and(_T_199, _T_200) @[axi4_to_ahb.scala 136:48] - node _T_202 = bits(_T_195, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_203 = geq(UInt<1>("h01"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_204 = and(_T_202, _T_203) @[axi4_to_ahb.scala 136:48] - node _T_205 = bits(_T_195, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_206 = geq(UInt<2>("h02"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_207 = and(_T_205, _T_206) @[axi4_to_ahb.scala 136:48] - node _T_208 = bits(_T_195, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_209 = geq(UInt<2>("h03"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_210 = and(_T_208, _T_209) @[axi4_to_ahb.scala 136:48] - node _T_211 = bits(_T_195, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_212 = geq(UInt<3>("h04"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_213 = and(_T_211, _T_212) @[axi4_to_ahb.scala 136:48] - node _T_214 = bits(_T_195, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_215 = geq(UInt<3>("h05"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_216 = and(_T_214, _T_215) @[axi4_to_ahb.scala 136:48] - node _T_217 = bits(_T_195, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_218 = geq(UInt<3>("h06"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_219 = and(_T_217, _T_218) @[axi4_to_ahb.scala 136:48] - node _T_220 = bits(_T_195, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_221 = geq(UInt<3>("h07"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_222 = and(_T_220, _T_221) @[axi4_to_ahb.scala 136:48] - node _T_223 = mux(_T_222, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_224 = mux(_T_219, UInt<3>("h06"), _T_223) @[Mux.scala 98:16] - node _T_225 = mux(_T_216, UInt<3>("h05"), _T_224) @[Mux.scala 98:16] - node _T_226 = mux(_T_213, UInt<3>("h04"), _T_225) @[Mux.scala 98:16] - node _T_227 = mux(_T_210, UInt<2>("h03"), _T_226) @[Mux.scala 98:16] - node _T_228 = mux(_T_207, UInt<2>("h02"), _T_227) @[Mux.scala 98:16] - node _T_229 = mux(_T_204, UInt<1>("h01"), _T_228) @[Mux.scala 98:16] - node _T_230 = mux(_T_201, UInt<1>("h00"), _T_229) @[Mux.scala 98:16] - node _T_231 = mux(_T_193, _T_230, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 233:30] - buf_cmd_byte_ptr <= _T_231 @[axi4_to_ahb.scala 233:24] - node _T_232 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 234:65] - node _T_233 = or(buf_aligned, _T_232) @[axi4_to_ahb.scala 234:44] - node _T_234 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 234:127] - node _T_235 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 234:145] - node _T_236 = add(_T_234, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_237 = tail(_T_236, 1) @[axi4_to_ahb.scala 135:52] - node _T_238 = mux(UInt<1>("h01"), _T_237, _T_234) @[axi4_to_ahb.scala 135:24] - node _T_239 = bits(_T_235, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_240 = geq(UInt<1>("h00"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_241 = and(_T_239, _T_240) @[axi4_to_ahb.scala 136:48] - node _T_242 = bits(_T_235, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_243 = geq(UInt<1>("h01"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_244 = and(_T_242, _T_243) @[axi4_to_ahb.scala 136:48] - node _T_245 = bits(_T_235, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_246 = geq(UInt<2>("h02"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_247 = and(_T_245, _T_246) @[axi4_to_ahb.scala 136:48] - node _T_248 = bits(_T_235, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_249 = geq(UInt<2>("h03"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_250 = and(_T_248, _T_249) @[axi4_to_ahb.scala 136:48] - node _T_251 = bits(_T_235, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_252 = geq(UInt<3>("h04"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_253 = and(_T_251, _T_252) @[axi4_to_ahb.scala 136:48] - node _T_254 = bits(_T_235, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_255 = geq(UInt<3>("h05"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_256 = and(_T_254, _T_255) @[axi4_to_ahb.scala 136:48] - node _T_257 = bits(_T_235, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_258 = geq(UInt<3>("h06"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_259 = and(_T_257, _T_258) @[axi4_to_ahb.scala 136:48] - node _T_260 = bits(_T_235, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_261 = geq(UInt<3>("h07"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_262 = and(_T_260, _T_261) @[axi4_to_ahb.scala 136:48] - node _T_263 = mux(_T_262, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_264 = mux(_T_259, UInt<3>("h06"), _T_263) @[Mux.scala 98:16] - node _T_265 = mux(_T_256, UInt<3>("h05"), _T_264) @[Mux.scala 98:16] - node _T_266 = mux(_T_253, UInt<3>("h04"), _T_265) @[Mux.scala 98:16] - node _T_267 = mux(_T_250, UInt<2>("h03"), _T_266) @[Mux.scala 98:16] - node _T_268 = mux(_T_247, UInt<2>("h02"), _T_267) @[Mux.scala 98:16] - node _T_269 = mux(_T_244, UInt<1>("h01"), _T_268) @[Mux.scala 98:16] - node _T_270 = mux(_T_241, UInt<1>("h00"), _T_269) @[Mux.scala 98:16] - node _T_271 = dshr(buf_byteen, _T_270) @[axi4_to_ahb.scala 234:92] - node _T_272 = bits(_T_271, 0, 0) @[axi4_to_ahb.scala 234:92] - node _T_273 = eq(_T_272, UInt<1>("h00")) @[axi4_to_ahb.scala 234:163] - node _T_274 = or(_T_233, _T_273) @[axi4_to_ahb.scala 234:79] - node _T_275 = and(trxn_done, _T_274) @[axi4_to_ahb.scala 234:29] - cmd_done <= _T_275 @[axi4_to_ahb.scala 234:16] - node _T_276 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 235:47] - node _T_277 = eq(_T_276, UInt<1>("h00")) @[axi4_to_ahb.scala 235:36] - node _T_278 = bits(_T_277, 0, 0) @[Bitwise.scala 72:15] - node _T_279 = mux(_T_278, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_280 = and(_T_279, UInt<2>("h02")) @[axi4_to_ahb.scala 235:61] - io.ahb.out.htrans <= _T_280 @[axi4_to_ahb.scala 235:25] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_281 = eq(UInt<3>("h04"), buf_state) @[Conditional.scala 37:30] - when _T_281 : @[Conditional.scala 39:67] - node _T_282 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 239:34] - node _T_283 = or(_T_282, ahb_hresp_q) @[axi4_to_ahb.scala 239:50] - buf_state_en <= _T_283 @[axi4_to_ahb.scala 239:20] - node _T_284 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 240:38] - node _T_285 = and(buf_state_en, _T_284) @[axi4_to_ahb.scala 240:36] - node _T_286 = and(_T_285, slave_ready) @[axi4_to_ahb.scala 240:51] - master_ready <= _T_286 @[axi4_to_ahb.scala 240:20] - node _T_287 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 241:42] - node _T_288 = or(ahb_hresp_q, _T_287) @[axi4_to_ahb.scala 241:40] - node _T_289 = and(master_valid, master_valid) @[axi4_to_ahb.scala 241:80] - node _T_290 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 241:111] - node _T_291 = eq(_T_290, UInt<1>("h01")) @[axi4_to_ahb.scala 241:117] - node _T_292 = bits(_T_291, 0, 0) @[axi4_to_ahb.scala 241:132] - node _T_293 = mux(_T_292, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 241:99] - node _T_294 = mux(_T_289, _T_293, UInt<3>("h00")) @[axi4_to_ahb.scala 241:65] - node _T_295 = mux(_T_288, UInt<3>("h05"), _T_294) @[axi4_to_ahb.scala 241:26] - buf_nxtstate <= _T_295 @[axi4_to_ahb.scala 241:20] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 242:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 243:23] - node _T_296 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 244:33] - node _T_297 = eq(_T_296, UInt<1>("h01")) @[axi4_to_ahb.scala 244:39] - buf_write_in <= _T_297 @[axi4_to_ahb.scala 244:20] - node _T_298 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 245:50] - node _T_299 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 245:78] - node _T_300 = or(_T_298, _T_299) @[axi4_to_ahb.scala 245:62] - node _T_301 = and(buf_state_en, _T_300) @[axi4_to_ahb.scala 245:33] - buf_wr_en <= _T_301 @[axi4_to_ahb.scala 245:17] - buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 246:22] - node _T_302 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 247:65] - node _T_303 = neq(_T_302, UInt<1>("h00")) @[axi4_to_ahb.scala 247:71] - node _T_304 = and(ahb_hready_q, _T_303) @[axi4_to_ahb.scala 247:50] - node _T_305 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 248:29] - node _T_306 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 248:85] - node _T_307 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 248:101] - node _T_308 = add(_T_306, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_309 = tail(_T_308, 1) @[axi4_to_ahb.scala 135:52] - node _T_310 = mux(UInt<1>("h01"), _T_309, _T_306) @[axi4_to_ahb.scala 135:24] - node _T_311 = bits(_T_307, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_312 = geq(UInt<1>("h00"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_313 = and(_T_311, _T_312) @[axi4_to_ahb.scala 136:48] - node _T_314 = bits(_T_307, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_315 = geq(UInt<1>("h01"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_316 = and(_T_314, _T_315) @[axi4_to_ahb.scala 136:48] - node _T_317 = bits(_T_307, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_318 = geq(UInt<2>("h02"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_319 = and(_T_317, _T_318) @[axi4_to_ahb.scala 136:48] - node _T_320 = bits(_T_307, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_321 = geq(UInt<2>("h03"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_322 = and(_T_320, _T_321) @[axi4_to_ahb.scala 136:48] - node _T_323 = bits(_T_307, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_324 = geq(UInt<3>("h04"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_325 = and(_T_323, _T_324) @[axi4_to_ahb.scala 136:48] - node _T_326 = bits(_T_307, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_327 = geq(UInt<3>("h05"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_328 = and(_T_326, _T_327) @[axi4_to_ahb.scala 136:48] - node _T_329 = bits(_T_307, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_330 = geq(UInt<3>("h06"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_331 = and(_T_329, _T_330) @[axi4_to_ahb.scala 136:48] - node _T_332 = bits(_T_307, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_333 = geq(UInt<3>("h07"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_334 = and(_T_332, _T_333) @[axi4_to_ahb.scala 136:48] - node _T_335 = mux(_T_334, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_336 = mux(_T_331, UInt<3>("h06"), _T_335) @[Mux.scala 98:16] - node _T_337 = mux(_T_328, UInt<3>("h05"), _T_336) @[Mux.scala 98:16] - node _T_338 = mux(_T_325, UInt<3>("h04"), _T_337) @[Mux.scala 98:16] - node _T_339 = mux(_T_322, UInt<2>("h03"), _T_338) @[Mux.scala 98:16] - node _T_340 = mux(_T_319, UInt<2>("h02"), _T_339) @[Mux.scala 98:16] - node _T_341 = mux(_T_316, UInt<1>("h01"), _T_340) @[Mux.scala 98:16] - node _T_342 = mux(_T_313, UInt<1>("h00"), _T_341) @[Mux.scala 98:16] - node _T_343 = dshr(buf_byteen, _T_342) @[axi4_to_ahb.scala 248:51] - node _T_344 = bits(_T_343, 0, 0) @[axi4_to_ahb.scala 248:51] - node _T_345 = eq(_T_344, UInt<1>("h00")) @[axi4_to_ahb.scala 248:116] - node _T_346 = or(_T_305, _T_345) @[axi4_to_ahb.scala 248:38] - node _T_347 = and(_T_304, _T_346) @[axi4_to_ahb.scala 247:80] - node _T_348 = or(ahb_hresp_q, _T_347) @[axi4_to_ahb.scala 247:34] - cmd_done <= _T_348 @[axi4_to_ahb.scala 247:16] - node _T_349 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 249:33] - node _T_350 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 249:64] - node _T_351 = and(_T_349, _T_350) @[axi4_to_ahb.scala 249:48] - bypass_en <= _T_351 @[axi4_to_ahb.scala 249:17] - node _T_352 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 250:48] - node _T_353 = eq(_T_352, UInt<1>("h00")) @[axi4_to_ahb.scala 250:37] - node _T_354 = or(_T_353, bypass_en) @[axi4_to_ahb.scala 250:61] - node _T_355 = bits(_T_354, 0, 0) @[Bitwise.scala 72:15] - node _T_356 = mux(_T_355, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_357 = and(_T_356, UInt<2>("h02")) @[axi4_to_ahb.scala 250:75] - io.ahb.out.htrans <= _T_357 @[axi4_to_ahb.scala 250:25] - node _T_358 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 251:55] - node _T_359 = and(buf_state_en, _T_358) @[axi4_to_ahb.scala 251:39] - slave_valid_pre <= _T_359 @[axi4_to_ahb.scala 251:23] - node _T_360 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 252:33] - node _T_361 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 252:63] - node _T_362 = neq(_T_361, UInt<1>("h00")) @[axi4_to_ahb.scala 252:69] - node _T_363 = and(_T_360, _T_362) @[axi4_to_ahb.scala 252:48] - trxn_done <= _T_363 @[axi4_to_ahb.scala 252:17] - node _T_364 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 253:40] - buf_cmd_byte_ptr_en <= _T_364 @[axi4_to_ahb.scala 253:27] - node _T_365 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 254:79] - node _T_366 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_367 = tail(_T_366, 1) @[axi4_to_ahb.scala 135:52] - node _T_368 = mux(UInt<1>("h00"), _T_367, UInt<3>("h00")) @[axi4_to_ahb.scala 135:24] - node _T_369 = bits(_T_365, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_370 = geq(UInt<1>("h00"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_371 = and(_T_369, _T_370) @[axi4_to_ahb.scala 136:48] - node _T_372 = bits(_T_365, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_373 = geq(UInt<1>("h01"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_374 = and(_T_372, _T_373) @[axi4_to_ahb.scala 136:48] - node _T_375 = bits(_T_365, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_376 = geq(UInt<2>("h02"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_377 = and(_T_375, _T_376) @[axi4_to_ahb.scala 136:48] - node _T_378 = bits(_T_365, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_379 = geq(UInt<2>("h03"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_380 = and(_T_378, _T_379) @[axi4_to_ahb.scala 136:48] - node _T_381 = bits(_T_365, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_382 = geq(UInt<3>("h04"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_383 = and(_T_381, _T_382) @[axi4_to_ahb.scala 136:48] - node _T_384 = bits(_T_365, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_385 = geq(UInt<3>("h05"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_386 = and(_T_384, _T_385) @[axi4_to_ahb.scala 136:48] - node _T_387 = bits(_T_365, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_388 = geq(UInt<3>("h06"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_389 = and(_T_387, _T_388) @[axi4_to_ahb.scala 136:48] - node _T_390 = bits(_T_365, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_391 = geq(UInt<3>("h07"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_392 = and(_T_390, _T_391) @[axi4_to_ahb.scala 136:48] - node _T_393 = mux(_T_392, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_394 = mux(_T_389, UInt<3>("h06"), _T_393) @[Mux.scala 98:16] - node _T_395 = mux(_T_386, UInt<3>("h05"), _T_394) @[Mux.scala 98:16] - node _T_396 = mux(_T_383, UInt<3>("h04"), _T_395) @[Mux.scala 98:16] - node _T_397 = mux(_T_380, UInt<2>("h03"), _T_396) @[Mux.scala 98:16] - node _T_398 = mux(_T_377, UInt<2>("h02"), _T_397) @[Mux.scala 98:16] - node _T_399 = mux(_T_374, UInt<1>("h01"), _T_398) @[Mux.scala 98:16] - node _T_400 = mux(_T_371, UInt<1>("h00"), _T_399) @[Mux.scala 98:16] - node _T_401 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 254:141] - node _T_402 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 254:157] - node _T_403 = add(_T_401, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_404 = tail(_T_403, 1) @[axi4_to_ahb.scala 135:52] - node _T_405 = mux(UInt<1>("h01"), _T_404, _T_401) @[axi4_to_ahb.scala 135:24] - node _T_406 = bits(_T_402, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_407 = geq(UInt<1>("h00"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_408 = and(_T_406, _T_407) @[axi4_to_ahb.scala 136:48] - node _T_409 = bits(_T_402, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_410 = geq(UInt<1>("h01"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_411 = and(_T_409, _T_410) @[axi4_to_ahb.scala 136:48] - node _T_412 = bits(_T_402, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_413 = geq(UInt<2>("h02"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_414 = and(_T_412, _T_413) @[axi4_to_ahb.scala 136:48] - node _T_415 = bits(_T_402, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_416 = geq(UInt<2>("h03"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_417 = and(_T_415, _T_416) @[axi4_to_ahb.scala 136:48] - node _T_418 = bits(_T_402, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_419 = geq(UInt<3>("h04"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_420 = and(_T_418, _T_419) @[axi4_to_ahb.scala 136:48] - node _T_421 = bits(_T_402, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_422 = geq(UInt<3>("h05"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_423 = and(_T_421, _T_422) @[axi4_to_ahb.scala 136:48] - node _T_424 = bits(_T_402, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_425 = geq(UInt<3>("h06"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_426 = and(_T_424, _T_425) @[axi4_to_ahb.scala 136:48] - node _T_427 = bits(_T_402, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_428 = geq(UInt<3>("h07"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_429 = and(_T_427, _T_428) @[axi4_to_ahb.scala 136:48] - node _T_430 = mux(_T_429, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_431 = mux(_T_426, UInt<3>("h06"), _T_430) @[Mux.scala 98:16] - node _T_432 = mux(_T_423, UInt<3>("h05"), _T_431) @[Mux.scala 98:16] - node _T_433 = mux(_T_420, UInt<3>("h04"), _T_432) @[Mux.scala 98:16] - node _T_434 = mux(_T_417, UInt<2>("h03"), _T_433) @[Mux.scala 98:16] - node _T_435 = mux(_T_414, UInt<2>("h02"), _T_434) @[Mux.scala 98:16] - node _T_436 = mux(_T_411, UInt<1>("h01"), _T_435) @[Mux.scala 98:16] - node _T_437 = mux(_T_408, UInt<1>("h00"), _T_436) @[Mux.scala 98:16] - node _T_438 = mux(trxn_done, _T_437, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 254:97] - node _T_439 = mux(bypass_en, _T_400, _T_438) @[axi4_to_ahb.scala 254:30] - buf_cmd_byte_ptr <= _T_439 @[axi4_to_ahb.scala 254:24] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_440 = eq(UInt<3>("h05"), buf_state) @[Conditional.scala 37:30] - when _T_440 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 257:20] - buf_state_en <= slave_ready @[axi4_to_ahb.scala 258:20] - slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 259:23] - slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 260:23] - skip @[Conditional.scala 39:67] - cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 264:16] - node _T_441 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 265:33] - node _T_442 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 265:73] - node _T_443 = eq(_T_442, UInt<1>("h01")) @[axi4_to_ahb.scala 265:80] - node _T_444 = and(buf_aligned_in, _T_443) @[axi4_to_ahb.scala 265:60] - node _T_445 = bits(_T_444, 0, 0) @[axi4_to_ahb.scala 265:100] - node _T_446 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 265:132] - node _T_447 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:50] - node _T_448 = eq(_T_447, UInt<8>("h0ff")) @[axi4_to_ahb.scala 127:57] - node _T_449 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:81] - node _T_450 = eq(_T_449, UInt<8>("h0f")) @[axi4_to_ahb.scala 127:88] - node _T_451 = or(_T_448, _T_450) @[axi4_to_ahb.scala 127:70] - node _T_452 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:117] - node _T_453 = eq(_T_452, UInt<8>("h03")) @[axi4_to_ahb.scala 127:124] - node _T_454 = or(_T_451, _T_453) @[axi4_to_ahb.scala 127:106] - node _T_455 = bits(_T_454, 0, 0) @[Bitwise.scala 72:15] - node _T_456 = mux(_T_455, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_457 = and(UInt<3>("h00"), _T_456) @[axi4_to_ahb.scala 127:29] - node _T_458 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 128:35] - node _T_459 = eq(_T_458, UInt<8>("h0c")) @[axi4_to_ahb.scala 128:42] - node _T_460 = bits(_T_459, 0, 0) @[Bitwise.scala 72:15] - node _T_461 = mux(_T_460, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_462 = and(UInt<2>("h02"), _T_461) @[axi4_to_ahb.scala 128:15] - node _T_463 = or(_T_457, _T_462) @[axi4_to_ahb.scala 127:146] - node _T_464 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 129:36] - node _T_465 = eq(_T_464, UInt<8>("h0f0")) @[axi4_to_ahb.scala 129:43] - node _T_466 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 129:67] - node _T_467 = eq(_T_466, UInt<8>("h03")) @[axi4_to_ahb.scala 129:74] - node _T_468 = or(_T_465, _T_467) @[axi4_to_ahb.scala 129:56] - node _T_469 = bits(_T_468, 0, 0) @[Bitwise.scala 72:15] - node _T_470 = mux(_T_469, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_471 = and(UInt<3>("h04"), _T_470) @[axi4_to_ahb.scala 129:15] - node _T_472 = or(_T_463, _T_471) @[axi4_to_ahb.scala 128:63] - node _T_473 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 130:35] - node _T_474 = eq(_T_473, UInt<8>("h0c0")) @[axi4_to_ahb.scala 130:42] - node _T_475 = bits(_T_474, 0, 0) @[Bitwise.scala 72:15] - node _T_476 = mux(_T_475, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_477 = and(UInt<3>("h06"), _T_476) @[axi4_to_ahb.scala 130:15] - node _T_478 = or(_T_472, _T_477) @[axi4_to_ahb.scala 129:96] - node _T_479 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 131:33] - node _T_480 = eq(_T_479, UInt<8>("h0c0")) @[axi4_to_ahb.scala 131:40] - node _T_481 = bits(_T_480, 0, 0) @[Bitwise.scala 72:15] - node _T_482 = mux(_T_481, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_483 = and(UInt<3>("h06"), _T_482) @[axi4_to_ahb.scala 131:13] - node _T_484 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 265:152] - node _T_485 = mux(_T_445, _T_478, _T_484) @[axi4_to_ahb.scala 265:43] - node _T_486 = cat(_T_441, _T_485) @[Cat.scala 29:58] - buf_addr_in <= _T_486 @[axi4_to_ahb.scala 265:15] - node _T_487 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 266:27] - buf_tag_in <= _T_487 @[axi4_to_ahb.scala 266:14] - node _T_488 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 267:32] - buf_byteen_in <= _T_488 @[axi4_to_ahb.scala 267:17] - node _T_489 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 268:33] - node _T_490 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 268:59] - node _T_491 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 268:80] - node _T_492 = mux(_T_489, _T_490, _T_491) @[axi4_to_ahb.scala 268:21] - buf_data_in <= _T_492 @[axi4_to_ahb.scala 268:15] - node _T_493 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 269:52] - node _T_494 = eq(_T_493, UInt<2>("h03")) @[axi4_to_ahb.scala 269:58] - node _T_495 = and(buf_aligned_in, _T_494) @[axi4_to_ahb.scala 269:38] - node _T_496 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 269:84] - node _T_497 = eq(_T_496, UInt<1>("h01")) @[axi4_to_ahb.scala 269:91] - node _T_498 = and(_T_495, _T_497) @[axi4_to_ahb.scala 269:71] - node _T_499 = bits(_T_498, 0, 0) @[axi4_to_ahb.scala 269:111] - node _T_500 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 269:142] - node _T_501 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 121:42] - node _T_502 = eq(_T_501, UInt<8>("h0ff")) @[axi4_to_ahb.scala 121:49] - node _T_503 = bits(_T_502, 0, 0) @[Bitwise.scala 72:15] - node _T_504 = mux(_T_503, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_505 = and(UInt<2>("h03"), _T_504) @[axi4_to_ahb.scala 121:25] - node _T_506 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 122:35] - node _T_507 = eq(_T_506, UInt<8>("h0f0")) @[axi4_to_ahb.scala 122:42] - node _T_508 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 122:64] - node _T_509 = eq(_T_508, UInt<8>("h0f")) @[axi4_to_ahb.scala 122:71] - node _T_510 = or(_T_507, _T_509) @[axi4_to_ahb.scala 122:55] - node _T_511 = bits(_T_510, 0, 0) @[Bitwise.scala 72:15] - node _T_512 = mux(_T_511, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_513 = and(UInt<2>("h02"), _T_512) @[axi4_to_ahb.scala 122:16] - node _T_514 = or(_T_505, _T_513) @[axi4_to_ahb.scala 121:64] - node _T_515 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:40] - node _T_516 = eq(_T_515, UInt<8>("h0c0")) @[axi4_to_ahb.scala 123:47] - node _T_517 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:69] - node _T_518 = eq(_T_517, UInt<6>("h030")) @[axi4_to_ahb.scala 123:76] - node _T_519 = or(_T_516, _T_518) @[axi4_to_ahb.scala 123:60] - node _T_520 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:98] - node _T_521 = eq(_T_520, UInt<8>("h0c")) @[axi4_to_ahb.scala 123:105] - node _T_522 = or(_T_519, _T_521) @[axi4_to_ahb.scala 123:89] - node _T_523 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:132] - node _T_524 = eq(_T_523, UInt<8>("h03")) @[axi4_to_ahb.scala 123:139] - node _T_525 = or(_T_522, _T_524) @[axi4_to_ahb.scala 123:123] - node _T_526 = bits(_T_525, 0, 0) @[Bitwise.scala 72:15] - node _T_527 = mux(_T_526, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_528 = and(UInt<2>("h01"), _T_527) @[axi4_to_ahb.scala 123:21] - node _T_529 = or(_T_514, _T_528) @[axi4_to_ahb.scala 122:93] - node _T_530 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 269:161] - node _T_531 = mux(_T_499, _T_529, _T_530) @[axi4_to_ahb.scala 269:21] - buf_size_in <= _T_531 @[axi4_to_ahb.scala 269:15] - node _T_532 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 270:32] - node _T_533 = eq(_T_532, UInt<1>("h00")) @[axi4_to_ahb.scala 270:39] - node _T_534 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 271:17] - node _T_535 = eq(_T_534, UInt<1>("h00")) @[axi4_to_ahb.scala 271:24] - node _T_536 = or(_T_533, _T_535) @[axi4_to_ahb.scala 270:48] - node _T_537 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 271:47] - node _T_538 = eq(_T_537, UInt<2>("h01")) @[axi4_to_ahb.scala 271:54] - node _T_539 = or(_T_536, _T_538) @[axi4_to_ahb.scala 271:33] - node _T_540 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 271:86] - node _T_541 = eq(_T_540, UInt<2>("h02")) @[axi4_to_ahb.scala 271:93] - node _T_542 = or(_T_539, _T_541) @[axi4_to_ahb.scala 271:72] - node _T_543 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 272:18] - node _T_544 = eq(_T_543, UInt<2>("h03")) @[axi4_to_ahb.scala 272:25] - node _T_545 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:55] - node _T_546 = eq(_T_545, UInt<2>("h03")) @[axi4_to_ahb.scala 272:62] - node _T_547 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:90] - node _T_548 = eq(_T_547, UInt<4>("h0c")) @[axi4_to_ahb.scala 272:97] - node _T_549 = or(_T_546, _T_548) @[axi4_to_ahb.scala 272:74] - node _T_550 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:125] - node _T_551 = eq(_T_550, UInt<6>("h030")) @[axi4_to_ahb.scala 272:132] - node _T_552 = or(_T_549, _T_551) @[axi4_to_ahb.scala 272:109] - node _T_553 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:161] - node _T_554 = eq(_T_553, UInt<8>("h0c0")) @[axi4_to_ahb.scala 272:168] - node _T_555 = or(_T_552, _T_554) @[axi4_to_ahb.scala 272:145] - node _T_556 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 273:21] - node _T_557 = eq(_T_556, UInt<4>("h0f")) @[axi4_to_ahb.scala 273:28] - node _T_558 = or(_T_555, _T_557) @[axi4_to_ahb.scala 272:181] - node _T_559 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 273:56] - node _T_560 = eq(_T_559, UInt<8>("h0f0")) @[axi4_to_ahb.scala 273:63] - node _T_561 = or(_T_558, _T_560) @[axi4_to_ahb.scala 273:40] - node _T_562 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 273:92] - node _T_563 = eq(_T_562, UInt<8>("h0ff")) @[axi4_to_ahb.scala 273:99] - node _T_564 = or(_T_561, _T_563) @[axi4_to_ahb.scala 273:76] - node _T_565 = and(_T_544, _T_564) @[axi4_to_ahb.scala 272:38] - node _T_566 = or(_T_542, _T_565) @[axi4_to_ahb.scala 271:106] - buf_aligned_in <= _T_566 @[axi4_to_ahb.scala 270:18] - node _T_567 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 275:43] - node _T_568 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 275:62] - node _T_569 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 275:87] - node _T_570 = cat(_T_568, _T_569) @[Cat.scala 29:58] - node _T_571 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 275:108] - node _T_572 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 275:133] - node _T_573 = cat(_T_571, _T_572) @[Cat.scala 29:58] - node _T_574 = mux(_T_567, _T_570, _T_573) @[axi4_to_ahb.scala 275:26] - io.ahb.out.haddr <= _T_574 @[axi4_to_ahb.scala 275:20] - node _T_575 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 276:43] - node _T_576 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15] - node _T_577 = mux(_T_576, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_578 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 276:94] - node _T_579 = and(_T_577, _T_578) @[axi4_to_ahb.scala 276:81] - node _T_580 = cat(UInt<1>("h00"), _T_579) @[Cat.scala 29:58] - node _T_581 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15] - node _T_582 = mux(_T_581, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_583 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 276:148] - node _T_584 = and(_T_582, _T_583) @[axi4_to_ahb.scala 276:138] - node _T_585 = cat(UInt<1>("h00"), _T_584) @[Cat.scala 29:58] - node _T_586 = mux(_T_575, _T_580, _T_585) @[axi4_to_ahb.scala 276:26] - io.ahb.out.hsize <= _T_586 @[axi4_to_ahb.scala 276:20] - io.ahb.out.hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 278:21] - io.ahb.out.hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 279:24] - node _T_587 = bits(io.axi.ar.bits.prot, 2, 2) @[axi4_to_ahb.scala 280:57] - node _T_588 = eq(_T_587, UInt<1>("h00")) @[axi4_to_ahb.scala 280:37] - node _T_589 = cat(UInt<1>("h01"), _T_588) @[Cat.scala 29:58] - io.ahb.out.hprot <= _T_589 @[axi4_to_ahb.scala 280:20] - node _T_590 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 281:44] - node _T_591 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 281:59] - node _T_592 = eq(_T_591, UInt<1>("h01")) @[axi4_to_ahb.scala 281:66] - node _T_593 = mux(_T_590, _T_592, buf_write) @[axi4_to_ahb.scala 281:27] - io.ahb.out.hwrite <= _T_593 @[axi4_to_ahb.scala 281:21] - node _T_594 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 282:32] - io.ahb.out.hwdata <= _T_594 @[axi4_to_ahb.scala 282:21] - slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 284:15] - node _T_595 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 285:43] - node _T_596 = mux(_T_595, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 285:23] - node _T_597 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15] - node _T_598 = mux(_T_597, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_599 = and(_T_598, UInt<2>("h02")) @[axi4_to_ahb.scala 285:88] - node _T_600 = cat(_T_596, _T_599) @[Cat.scala 29:58] - slave_opc <= _T_600 @[axi4_to_ahb.scala 285:13] - node _T_601 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 286:41] - node _T_602 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 286:66] - node _T_603 = cat(_T_602, _T_602) @[Cat.scala 29:58] - node _T_604 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 286:91] - node _T_605 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 286:110] - node _T_606 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 286:131] - node _T_607 = mux(_T_604, _T_605, _T_606) @[axi4_to_ahb.scala 286:79] - node _T_608 = mux(_T_601, _T_603, _T_607) @[axi4_to_ahb.scala 286:21] - slave_rdata <= _T_608 @[axi4_to_ahb.scala 286:15] - node _T_609 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 287:26] - slave_tag <= _T_609 @[axi4_to_ahb.scala 287:13] - node _T_610 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 289:37] - node _T_611 = neq(_T_610, UInt<1>("h00")) @[axi4_to_ahb.scala 289:44] - node _T_612 = and(_T_611, io.ahb.in.hready) @[axi4_to_ahb.scala 289:56] - node _T_613 = and(_T_612, io.ahb.out.hwrite) @[axi4_to_ahb.scala 289:75] - last_addr_en <= _T_613 @[axi4_to_ahb.scala 289:16] - node _T_614 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 291:31] - node _T_615 = and(_T_614, master_ready) @[axi4_to_ahb.scala 291:49] - wrbuf_en <= _T_615 @[axi4_to_ahb.scala 291:12] - node _T_616 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 292:35] - node _T_617 = and(_T_616, master_ready) @[axi4_to_ahb.scala 292:52] - wrbuf_data_en <= _T_617 @[axi4_to_ahb.scala 292:17] - node _T_618 = and(master_valid, master_ready) @[axi4_to_ahb.scala 293:34] - node _T_619 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 293:62] - node _T_620 = eq(_T_619, UInt<1>("h01")) @[axi4_to_ahb.scala 293:69] - node _T_621 = and(_T_618, _T_620) @[axi4_to_ahb.scala 293:49] - wrbuf_cmd_sent <= _T_621 @[axi4_to_ahb.scala 293:18] - node _T_622 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 294:33] - node _T_623 = and(wrbuf_cmd_sent, _T_622) @[axi4_to_ahb.scala 294:31] - wrbuf_rst <= _T_623 @[axi4_to_ahb.scala 294:13] - node _T_624 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 296:36] - node _T_625 = and(wrbuf_vld, _T_624) @[axi4_to_ahb.scala 296:34] - node _T_626 = eq(_T_625, UInt<1>("h00")) @[axi4_to_ahb.scala 296:22] - node _T_627 = and(_T_626, master_ready) @[axi4_to_ahb.scala 296:53] - io.axi.aw.ready <= _T_627 @[axi4_to_ahb.scala 296:19] - node _T_628 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 297:40] - node _T_629 = and(wrbuf_data_vld, _T_628) @[axi4_to_ahb.scala 297:38] - node _T_630 = eq(_T_629, UInt<1>("h00")) @[axi4_to_ahb.scala 297:21] - node _T_631 = and(_T_630, master_ready) @[axi4_to_ahb.scala 297:57] - io.axi.w.ready <= _T_631 @[axi4_to_ahb.scala 297:18] - node _T_632 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 298:34] - node _T_633 = eq(_T_632, UInt<1>("h00")) @[axi4_to_ahb.scala 298:22] - node _T_634 = and(_T_633, master_ready) @[axi4_to_ahb.scala 298:52] - io.axi.ar.ready <= _T_634 @[axi4_to_ahb.scala 298:19] - io.axi.r.bits.last <= UInt<1>("h01") @[axi4_to_ahb.scala 299:22] - node _T_635 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 301:71] - node _T_636 = mux(_T_635, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 301:55] - node _T_637 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 301:91] - node _T_638 = and(_T_636, _T_637) @[axi4_to_ahb.scala 301:89] - reg _T_639 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 301:51] - _T_639 <= _T_638 @[axi4_to_ahb.scala 301:51] - wrbuf_vld <= _T_639 @[axi4_to_ahb.scala 301:21] - node _T_640 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 302:76] - node _T_641 = mux(_T_640, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 302:55] - node _T_642 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 302:102] - node _T_643 = and(_T_641, _T_642) @[axi4_to_ahb.scala 302:100] - reg _T_644 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 302:51] - _T_644 <= _T_643 @[axi4_to_ahb.scala 302:51] - wrbuf_data_vld <= _T_644 @[axi4_to_ahb.scala 302:21] - node _T_645 = bits(io.axi.aw.bits.id, 0, 0) @[axi4_to_ahb.scala 303:71] - node _T_646 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 303:105] - reg _T_647 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_646 : @[Reg.scala 28:19] - _T_647 <= _T_645 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - wrbuf_tag <= _T_647 @[axi4_to_ahb.scala 303:21] - node _T_648 = bits(io.axi.aw.bits.size, 2, 0) @[axi4_to_ahb.scala 304:73] - node _T_649 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 304:101] - reg _T_650 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_649 : @[Reg.scala 28:19] - _T_650 <= _T_648 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - wrbuf_size <= _T_650 @[axi4_to_ahb.scala 304:21] - node _T_651 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 305:61] - inst rvclkhdr_2 of rvclkhdr_851 @[lib.scala 368:23] - rvclkhdr_2.clock <= clock - rvclkhdr_2.reset <= reset - rvclkhdr_2.io.clk <= bus_clk @[lib.scala 370:18] - rvclkhdr_2.io.en <= _T_651 @[lib.scala 371:17] - rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_652 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_652 <= io.axi.aw.bits.addr @[lib.scala 374:16] - wrbuf_addr <= _T_652 @[axi4_to_ahb.scala 305:21] - node _T_653 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 306:65] - inst rvclkhdr_3 of rvclkhdr_852 @[lib.scala 368:23] - rvclkhdr_3.clock <= clock - rvclkhdr_3.reset <= reset - rvclkhdr_3.io.clk <= bus_clk @[lib.scala 370:18] - rvclkhdr_3.io.en <= _T_653 @[lib.scala 371:17] - rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_654 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_654 <= io.axi.w.bits.data @[lib.scala 374:16] - wrbuf_data <= _T_654 @[axi4_to_ahb.scala 306:21] - node _T_655 = bits(io.axi.w.bits.strb, 7, 0) @[axi4_to_ahb.scala 307:72] - node _T_656 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 307:105] - reg _T_657 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_656 : @[Reg.scala 28:19] - _T_657 <= _T_655 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - wrbuf_byteen <= _T_657 @[axi4_to_ahb.scala 307:21] - node _T_658 = bits(io.ahb.out.haddr, 31, 0) @[axi4_to_ahb.scala 308:71] - node _T_659 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 308:104] - reg _T_660 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_659 : @[Reg.scala 28:19] - _T_660 <= _T_658 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - last_bus_addr <= _T_660 @[axi4_to_ahb.scala 308:21] - node _T_661 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 309:89] - reg _T_662 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_661 : @[Reg.scala 28:19] - _T_662 <= buf_write_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_write <= _T_662 @[axi4_to_ahb.scala 309:21] - node _T_663 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 310:64] - node _T_664 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 310:99] - reg _T_665 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_664 : @[Reg.scala 28:19] - _T_665 <= _T_663 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_tag <= _T_665 @[axi4_to_ahb.scala 310:21] - node _T_666 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 311:42] - node _T_667 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 311:61] - node _T_668 = bits(_T_667, 0, 0) @[axi4_to_ahb.scala 311:78] - inst rvclkhdr_4 of rvclkhdr_853 @[lib.scala 368:23] - rvclkhdr_4.clock <= clock - rvclkhdr_4.reset <= reset - rvclkhdr_4.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_4.io.en <= _T_668 @[lib.scala 371:17] - rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_669 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_669 <= _T_666 @[lib.scala 374:16] - buf_addr <= _T_669 @[axi4_to_ahb.scala 311:21] - node _T_670 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 312:65] - node _T_671 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 312:94] - reg _T_672 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_671 : @[Reg.scala 28:19] - _T_672 <= _T_670 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_size <= _T_672 @[axi4_to_ahb.scala 312:21] - node _T_673 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 313:91] - reg _T_674 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_673 : @[Reg.scala 28:19] - _T_674 <= buf_aligned_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_aligned <= _T_674 @[axi4_to_ahb.scala 313:21] - node _T_675 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 314:67] - node _T_676 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 314:96] - reg _T_677 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_676 : @[Reg.scala 28:19] - _T_677 <= _T_675 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_byteen <= _T_677 @[axi4_to_ahb.scala 314:21] - node _T_678 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 315:42] - node _T_679 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 315:66] - node _T_680 = bits(_T_679, 0, 0) @[axi4_to_ahb.scala 315:89] - inst rvclkhdr_5 of rvclkhdr_854 @[lib.scala 368:23] - rvclkhdr_5.clock <= clock - rvclkhdr_5.reset <= reset - rvclkhdr_5.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_5.io.en <= _T_680 @[lib.scala 371:17] - rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_681 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_681 <= _T_678 @[lib.scala 374:16] - buf_data <= _T_681 @[axi4_to_ahb.scala 315:21] - node _T_682 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 316:89] - reg _T_683 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_682 : @[Reg.scala 28:19] - _T_683 <= buf_write @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - slvbuf_write <= _T_683 @[axi4_to_ahb.scala 316:21] - node _T_684 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 317:61] - node _T_685 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 317:99] - reg _T_686 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_685 : @[Reg.scala 28:19] - _T_686 <= _T_684 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - slvbuf_tag <= _T_686 @[axi4_to_ahb.scala 317:21] - node _T_687 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 318:99] - reg _T_688 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_687 : @[Reg.scala 28:19] - _T_688 <= slvbuf_error_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - slvbuf_error <= _T_688 @[axi4_to_ahb.scala 318:21] - node _T_689 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 319:72] - node _T_690 = mux(_T_689, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 319:56] - node _T_691 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 319:92] - node _T_692 = and(_T_690, _T_691) @[axi4_to_ahb.scala 319:90] - reg _T_693 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 319:52] - _T_693 <= _T_692 @[axi4_to_ahb.scala 319:52] - cmd_doneQ <= _T_693 @[axi4_to_ahb.scala 319:21] - node _T_694 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 320:71] - node _T_695 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 320:110] - reg _T_696 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_695 : @[Reg.scala 28:19] - _T_696 <= _T_694 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_cmd_byte_ptrQ <= _T_696 @[axi4_to_ahb.scala 320:21] - reg _T_697 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 321:52] - _T_697 <= io.ahb.in.hready @[axi4_to_ahb.scala 321:52] - ahb_hready_q <= _T_697 @[axi4_to_ahb.scala 321:21] - node _T_698 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 322:70] - reg _T_699 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 322:52] - _T_699 <= _T_698 @[axi4_to_ahb.scala 322:52] - ahb_htrans_q <= _T_699 @[axi4_to_ahb.scala 322:21] - reg _T_700 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 323:57] - _T_700 <= io.ahb.out.hwrite @[axi4_to_ahb.scala 323:57] - ahb_hwrite_q <= _T_700 @[axi4_to_ahb.scala 323:21] - reg _T_701 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 324:52] - _T_701 <= io.ahb.in.hresp @[axi4_to_ahb.scala 324:52] - ahb_hresp_q <= _T_701 @[axi4_to_ahb.scala 324:21] - node _T_702 = bits(io.ahb.in.hrdata, 63, 0) @[axi4_to_ahb.scala 325:74] - reg _T_703 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 325:57] - _T_703 <= _T_702 @[axi4_to_ahb.scala 325:57] - ahb_hrdata_q <= _T_703 @[axi4_to_ahb.scala 325:21] - node _T_704 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 327:43] - node _T_705 = or(_T_704, io.clk_override) @[axi4_to_ahb.scala 327:58] - node _T_706 = and(io.bus_clk_en, _T_705) @[axi4_to_ahb.scala 327:30] - buf_clken <= _T_706 @[axi4_to_ahb.scala 327:13] - node _T_707 = bits(io.ahb.out.htrans, 1, 1) @[axi4_to_ahb.scala 328:76] - node _T_708 = and(io.ahb.in.hready, _T_707) @[axi4_to_ahb.scala 328:57] - node _T_709 = or(_T_708, io.clk_override) @[axi4_to_ahb.scala 328:81] - node _T_710 = and(io.bus_clk_en, _T_709) @[axi4_to_ahb.scala 328:36] - ahbm_addr_clken <= _T_710 @[axi4_to_ahb.scala 328:19] - node _T_711 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 329:50] - node _T_712 = or(_T_711, io.clk_override) @[axi4_to_ahb.scala 329:60] - node _T_713 = and(io.bus_clk_en, _T_712) @[axi4_to_ahb.scala 329:36] - ahbm_data_clken <= _T_713 @[axi4_to_ahb.scala 329:19] - inst rvclkhdr_6 of rvclkhdr_855 @[lib.scala 343:22] - rvclkhdr_6.clock <= clock - rvclkhdr_6.reset <= reset - rvclkhdr_6.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_6.io.en <= buf_clken @[lib.scala 345:16] - rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 332:12] - inst rvclkhdr_7 of rvclkhdr_856 @[lib.scala 343:22] - rvclkhdr_7.clock <= clock - rvclkhdr_7.reset <= reset - rvclkhdr_7.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_7.io.en <= io.bus_clk_en @[lib.scala 345:16] - rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 333:12] - inst rvclkhdr_8 of rvclkhdr_857 @[lib.scala 343:22] - rvclkhdr_8.clock <= clock - rvclkhdr_8.reset <= reset - rvclkhdr_8.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_8.io.en <= ahbm_addr_clken @[lib.scala 345:16] - rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 334:17] - inst rvclkhdr_9 of rvclkhdr_858 @[lib.scala 343:22] - rvclkhdr_9.clock <= clock - rvclkhdr_9.reset <= reset - rvclkhdr_9.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_9.io.en <= ahbm_data_clken @[lib.scala 345:16] - rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 335:17] - - extmodule gated_latch_859 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_859 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_859 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_860 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_860 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_860 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_861 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_861 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_861 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_862 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_862 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_862 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_863 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_863 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_863 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_864 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_864 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_864 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_865 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_865 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_865 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_866 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_866 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_866 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_867 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_867 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_867 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_868 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_868 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_868 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - module axi4_to_ahb_1 : - input clock : Clock - input reset : AsyncReset - output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ahb : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}} - - wire buf_rst : UInt<1> - buf_rst <= UInt<1>("h00") - buf_rst <= UInt<1>("h00") @[axi4_to_ahb.scala 21:11] - io.ahb.out.htrans <= UInt<1>("h00") @[axi4_to_ahb.scala 22:21] - wire buf_state_en : UInt<1> - buf_state_en <= UInt<1>("h00") - wire ahbm_clk : Clock @[axi4_to_ahb.scala 24:22] - wire ahbm_addr_clk : Clock @[axi4_to_ahb.scala 25:27] - wire ahbm_data_clk : Clock @[axi4_to_ahb.scala 26:27] - wire buf_state : UInt<3> - buf_state <= UInt<3>("h00") - wire buf_nxtstate : UInt<3> - buf_nxtstate <= UInt<3>("h00") - node _T = bits(buf_state_en, 0, 0) @[axi4_to_ahb.scala 30:70] - node _T_1 = mux(_T, buf_nxtstate, buf_state) @[axi4_to_ahb.scala 30:50] - node _T_2 = eq(buf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 30:108] - node _T_3 = bits(_T_2, 0, 0) @[Bitwise.scala 72:15] - node _T_4 = mux(_T_3, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_5 = and(_T_1, _T_4) @[axi4_to_ahb.scala 30:98] - reg _T_6 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 30:45] - _T_6 <= _T_5 @[axi4_to_ahb.scala 30:45] - buf_state <= _T_6 @[axi4_to_ahb.scala 30:13] - wire slave_valid : UInt<1> - slave_valid <= UInt<1>("h00") - wire slave_ready : UInt<1> - slave_ready <= UInt<1>("h00") - wire slave_tag : UInt<3> - slave_tag <= UInt<3>("h00") - wire slave_rdata : UInt<64> - slave_rdata <= UInt<64>("h00") - wire slave_opc : UInt<4> - slave_opc <= UInt<4>("h00") - wire wrbuf_en : UInt<1> - wrbuf_en <= UInt<1>("h00") - wire wrbuf_data_en : UInt<1> - wrbuf_data_en <= UInt<1>("h00") - wire wrbuf_cmd_sent : UInt<1> - wrbuf_cmd_sent <= UInt<1>("h00") - wire wrbuf_rst : UInt<1> - wrbuf_rst <= UInt<1>("h00") - wire wrbuf_vld : UInt<1> - wrbuf_vld <= UInt<1>("h00") - wire wrbuf_data_vld : UInt<1> - wrbuf_data_vld <= UInt<1>("h00") - wire wrbuf_tag : UInt<3> - wrbuf_tag <= UInt<3>("h00") - wire wrbuf_size : UInt<3> - wrbuf_size <= UInt<3>("h00") - wire wrbuf_addr : UInt<32> - wrbuf_addr <= UInt<32>("h00") - wire wrbuf_data : UInt<64> - wrbuf_data <= UInt<64>("h00") - wire wrbuf_byteen : UInt<8> - wrbuf_byteen <= UInt<8>("h00") - wire bus_write_clk_en : UInt<1> - bus_write_clk_en <= UInt<1>("h00") - wire bus_clk : Clock @[axi4_to_ahb.scala 50:21] - wire bus_write_clk : Clock @[axi4_to_ahb.scala 51:27] - wire master_valid : UInt<1> - master_valid <= UInt<1>("h00") - wire master_ready : UInt<1> - master_ready <= UInt<1>("h00") - wire master_tag : UInt<3> - master_tag <= UInt<3>("h00") - wire master_addr : UInt<32> - master_addr <= UInt<32>("h00") - wire master_wdata : UInt<64> - master_wdata <= UInt<64>("h00") - wire master_size : UInt<3> - master_size <= UInt<3>("h00") - wire master_opc : UInt<3> - master_opc <= UInt<3>("h00") - wire master_byteen : UInt<8> - master_byteen <= UInt<8>("h00") - wire buf_addr : UInt<32> - buf_addr <= UInt<32>("h00") - wire buf_size : UInt<2> - buf_size <= UInt<2>("h00") - wire buf_write : UInt<1> - buf_write <= UInt<1>("h00") - wire buf_byteen : UInt<8> - buf_byteen <= UInt<8>("h00") - wire buf_aligned : UInt<1> - buf_aligned <= UInt<1>("h00") - wire buf_data : UInt<64> - buf_data <= UInt<64>("h00") - wire buf_tag : UInt<3> - buf_tag <= UInt<3>("h00") - wire buf_tag_in : UInt<3> - buf_tag_in <= UInt<3>("h00") - wire buf_addr_in : UInt<32> - buf_addr_in <= UInt<32>("h00") - wire buf_byteen_in : UInt<8> - buf_byteen_in <= UInt<8>("h00") - wire buf_data_in : UInt<64> - buf_data_in <= UInt<64>("h00") - wire buf_write_in : UInt<1> - buf_write_in <= UInt<1>("h00") - wire buf_aligned_in : UInt<1> - buf_aligned_in <= UInt<1>("h00") - wire buf_size_in : UInt<3> - buf_size_in <= UInt<3>("h00") - wire buf_wr_en : UInt<1> - buf_wr_en <= UInt<1>("h00") - wire buf_data_wr_en : UInt<1> - buf_data_wr_en <= UInt<1>("h00") - wire slvbuf_error_en : UInt<1> - slvbuf_error_en <= UInt<1>("h00") - wire wr_cmd_vld : UInt<1> - wr_cmd_vld <= UInt<1>("h00") - wire cmd_done_rst : UInt<1> - cmd_done_rst <= UInt<1>("h00") - wire cmd_done : UInt<1> - cmd_done <= UInt<1>("h00") - wire cmd_doneQ : UInt<1> - cmd_doneQ <= UInt<1>("h00") - wire trxn_done : UInt<1> - trxn_done <= UInt<1>("h00") - wire buf_cmd_byte_ptr : UInt<3> - buf_cmd_byte_ptr <= UInt<3>("h00") - wire buf_cmd_byte_ptrQ : UInt<3> - buf_cmd_byte_ptrQ <= UInt<3>("h00") - wire buf_cmd_nxtbyte_ptr : UInt<3> - buf_cmd_nxtbyte_ptr <= UInt<3>("h00") - wire buf_cmd_byte_ptr_en : UInt<1> - buf_cmd_byte_ptr_en <= UInt<1>("h00") - wire found : UInt<1> - found <= UInt<1>("h00") - wire slave_valid_pre : UInt<1> - slave_valid_pre <= UInt<1>("h00") - wire ahb_hready_q : UInt<1> - ahb_hready_q <= UInt<1>("h00") - wire ahb_hresp_q : UInt<1> - ahb_hresp_q <= UInt<1>("h00") - wire ahb_htrans_q : UInt<2> - ahb_htrans_q <= UInt<2>("h00") - wire ahb_hwrite_q : UInt<1> - ahb_hwrite_q <= UInt<1>("h00") - wire ahb_hrdata_q : UInt<64> - ahb_hrdata_q <= UInt<64>("h00") - wire slvbuf_write : UInt<1> - slvbuf_write <= UInt<1>("h00") - wire slvbuf_error : UInt<1> - slvbuf_error <= UInt<1>("h00") - wire slvbuf_tag : UInt<3> - slvbuf_tag <= UInt<3>("h00") - wire slvbuf_error_in : UInt<1> - slvbuf_error_in <= UInt<1>("h00") - wire slvbuf_wr_en : UInt<1> - slvbuf_wr_en <= UInt<1>("h00") - wire bypass_en : UInt<1> - bypass_en <= UInt<1>("h00") - wire rd_bypass_idle : UInt<1> - rd_bypass_idle <= UInt<1>("h00") - wire last_addr_en : UInt<1> - last_addr_en <= UInt<1>("h00") - wire last_bus_addr : UInt<32> - last_bus_addr <= UInt<32>("h00") - wire buf_clken : UInt<1> - buf_clken <= UInt<1>("h00") - wire slvbuf_clken : UInt<1> - slvbuf_clken <= UInt<1>("h00") - wire ahbm_addr_clken : UInt<1> - ahbm_addr_clken <= UInt<1>("h00") - wire ahbm_data_clken : UInt<1> - ahbm_data_clken <= UInt<1>("h00") - wire buf_clk : Clock @[axi4_to_ahb.scala 118:21] - node _T_7 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 139:27] - wr_cmd_vld <= _T_7 @[axi4_to_ahb.scala 139:14] - node _T_8 = or(wr_cmd_vld, io.axi.ar.valid) @[axi4_to_ahb.scala 140:30] - master_valid <= _T_8 @[axi4_to_ahb.scala 140:16] - node _T_9 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 141:38] - node _T_10 = bits(wrbuf_tag, 2, 0) @[axi4_to_ahb.scala 141:51] - node _T_11 = bits(io.axi.ar.bits.id, 2, 0) @[axi4_to_ahb.scala 141:82] - node _T_12 = mux(_T_9, _T_10, _T_11) @[axi4_to_ahb.scala 141:20] - master_tag <= _T_12 @[axi4_to_ahb.scala 141:14] - node _T_13 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 142:38] - node _T_14 = mux(_T_13, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 142:20] - master_opc <= _T_14 @[axi4_to_ahb.scala 142:14] - node _T_15 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 143:39] - node _T_16 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 143:53] - node _T_17 = bits(io.axi.ar.bits.addr, 31, 0) @[axi4_to_ahb.scala 143:81] - node _T_18 = mux(_T_15, _T_16, _T_17) @[axi4_to_ahb.scala 143:21] - master_addr <= _T_18 @[axi4_to_ahb.scala 143:15] - node _T_19 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 144:39] - node _T_20 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 144:53] - node _T_21 = bits(io.axi.ar.bits.size, 2, 0) @[axi4_to_ahb.scala 144:80] - node _T_22 = mux(_T_19, _T_20, _T_21) @[axi4_to_ahb.scala 144:21] - master_size <= _T_22 @[axi4_to_ahb.scala 144:15] - node _T_23 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 145:32] - master_byteen <= _T_23 @[axi4_to_ahb.scala 145:17] - node _T_24 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 146:29] - master_wdata <= _T_24 @[axi4_to_ahb.scala 146:16] - node _T_25 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 149:33] - node _T_26 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 149:58] - node _T_27 = and(_T_25, _T_26) @[axi4_to_ahb.scala 149:47] - io.axi.b.valid <= _T_27 @[axi4_to_ahb.scala 149:18] - node _T_28 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 150:38] - node _T_29 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 150:65] - node _T_30 = mux(_T_29, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 150:55] - node _T_31 = mux(_T_28, UInt<2>("h02"), _T_30) @[axi4_to_ahb.scala 150:28] - io.axi.b.bits.resp <= _T_31 @[axi4_to_ahb.scala 150:22] - node _T_32 = bits(slave_tag, 2, 0) @[axi4_to_ahb.scala 151:32] - io.axi.b.bits.id <= _T_32 @[axi4_to_ahb.scala 151:20] - node _T_33 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 153:33] - node _T_34 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 153:59] - node _T_35 = eq(_T_34, UInt<1>("h00")) @[axi4_to_ahb.scala 153:66] - node _T_36 = and(_T_33, _T_35) @[axi4_to_ahb.scala 153:47] - io.axi.r.valid <= _T_36 @[axi4_to_ahb.scala 153:18] - node _T_37 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 154:38] - node _T_38 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 154:65] - node _T_39 = mux(_T_38, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 154:55] - node _T_40 = mux(_T_37, UInt<2>("h02"), _T_39) @[axi4_to_ahb.scala 154:28] - io.axi.r.bits.resp <= _T_40 @[axi4_to_ahb.scala 154:22] - node _T_41 = bits(slave_tag, 2, 0) @[axi4_to_ahb.scala 155:32] - io.axi.r.bits.id <= _T_41 @[axi4_to_ahb.scala 155:20] - node _T_42 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 156:36] - io.axi.r.bits.data <= _T_42 @[axi4_to_ahb.scala 156:22] - node _T_43 = and(io.axi.b.ready, io.axi.r.ready) @[axi4_to_ahb.scala 157:33] - slave_ready <= _T_43 @[axi4_to_ahb.scala 157:15] - node _T_44 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 160:57] - node _T_45 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 160:94] - node _T_46 = or(_T_44, _T_45) @[axi4_to_ahb.scala 160:76] - node _T_47 = and(io.bus_clk_en, _T_46) @[axi4_to_ahb.scala 160:37] - bus_write_clk_en <= _T_47 @[axi4_to_ahb.scala 160:20] - inst rvclkhdr of rvclkhdr_859 @[lib.scala 343:22] - rvclkhdr.clock <= clock - rvclkhdr.reset <= reset - rvclkhdr.io.clk <= clock @[lib.scala 344:17] - rvclkhdr.io.en <= io.bus_clk_en @[lib.scala 345:16] - rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - bus_clk <= rvclkhdr.io.l1clk @[axi4_to_ahb.scala 162:11] - node _T_48 = bits(bus_write_clk_en, 0, 0) @[axi4_to_ahb.scala 163:59] - inst rvclkhdr_1 of rvclkhdr_860 @[lib.scala 343:22] - rvclkhdr_1.clock <= clock - rvclkhdr_1.reset <= reset - rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_1.io.en <= _T_48 @[lib.scala 345:16] - rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - bus_write_clk <= rvclkhdr_1.io.l1clk @[axi4_to_ahb.scala 163:17] - node _T_49 = eq(UInt<3>("h00"), buf_state) @[Conditional.scala 37:30] - when _T_49 : @[Conditional.scala 40:58] - master_ready <= UInt<1>("h01") @[axi4_to_ahb.scala 167:20] - node _T_50 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 168:34] - node _T_51 = eq(_T_50, UInt<1>("h01")) @[axi4_to_ahb.scala 168:41] - buf_write_in <= _T_51 @[axi4_to_ahb.scala 168:20] - node _T_52 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 169:46] - node _T_53 = mux(_T_52, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 169:26] - buf_nxtstate <= _T_53 @[axi4_to_ahb.scala 169:20] - node _T_54 = and(master_valid, UInt<1>("h01")) @[axi4_to_ahb.scala 170:36] - buf_state_en <= _T_54 @[axi4_to_ahb.scala 170:20] - buf_wr_en <= buf_state_en @[axi4_to_ahb.scala 171:17] - node _T_55 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 172:54] - node _T_56 = and(buf_state_en, _T_55) @[axi4_to_ahb.scala 172:38] - buf_data_wr_en <= _T_56 @[axi4_to_ahb.scala 172:22] - buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 173:27] - node _T_57 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 175:50] - node _T_58 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 175:94] - node _T_59 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_60 = tail(_T_59, 1) @[axi4_to_ahb.scala 135:52] - node _T_61 = mux(UInt<1>("h00"), _T_60, UInt<3>("h00")) @[axi4_to_ahb.scala 135:24] - node _T_62 = bits(_T_58, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_63 = geq(UInt<1>("h00"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_64 = and(_T_62, _T_63) @[axi4_to_ahb.scala 136:48] - node _T_65 = bits(_T_58, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_66 = geq(UInt<1>("h01"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_67 = and(_T_65, _T_66) @[axi4_to_ahb.scala 136:48] - node _T_68 = bits(_T_58, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_69 = geq(UInt<2>("h02"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_70 = and(_T_68, _T_69) @[axi4_to_ahb.scala 136:48] - node _T_71 = bits(_T_58, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_72 = geq(UInt<2>("h03"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_73 = and(_T_71, _T_72) @[axi4_to_ahb.scala 136:48] - node _T_74 = bits(_T_58, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_75 = geq(UInt<3>("h04"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_76 = and(_T_74, _T_75) @[axi4_to_ahb.scala 136:48] - node _T_77 = bits(_T_58, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_78 = geq(UInt<3>("h05"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_79 = and(_T_77, _T_78) @[axi4_to_ahb.scala 136:48] - node _T_80 = bits(_T_58, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_81 = geq(UInt<3>("h06"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_82 = and(_T_80, _T_81) @[axi4_to_ahb.scala 136:48] - node _T_83 = bits(_T_58, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_84 = geq(UInt<3>("h07"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_85 = and(_T_83, _T_84) @[axi4_to_ahb.scala 136:48] - node _T_86 = mux(_T_85, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_87 = mux(_T_82, UInt<3>("h06"), _T_86) @[Mux.scala 98:16] - node _T_88 = mux(_T_79, UInt<3>("h05"), _T_87) @[Mux.scala 98:16] - node _T_89 = mux(_T_76, UInt<3>("h04"), _T_88) @[Mux.scala 98:16] - node _T_90 = mux(_T_73, UInt<2>("h03"), _T_89) @[Mux.scala 98:16] - node _T_91 = mux(_T_70, UInt<2>("h02"), _T_90) @[Mux.scala 98:16] - node _T_92 = mux(_T_67, UInt<1>("h01"), _T_91) @[Mux.scala 98:16] - node _T_93 = mux(_T_64, UInt<1>("h00"), _T_92) @[Mux.scala 98:16] - node _T_94 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 175:124] - node _T_95 = mux(_T_57, _T_93, _T_94) @[axi4_to_ahb.scala 175:30] - buf_cmd_byte_ptr <= _T_95 @[axi4_to_ahb.scala 175:24] - bypass_en <= buf_state_en @[axi4_to_ahb.scala 176:17] - node _T_96 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 177:51] - node _T_97 = and(bypass_en, _T_96) @[axi4_to_ahb.scala 177:35] - rd_bypass_idle <= _T_97 @[axi4_to_ahb.scala 177:22] - node _T_98 = bits(bypass_en, 0, 0) @[Bitwise.scala 72:15] - node _T_99 = mux(_T_98, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_100 = and(_T_99, UInt<2>("h02")) @[axi4_to_ahb.scala 178:49] - io.ahb.out.htrans <= _T_100 @[axi4_to_ahb.scala 178:25] - skip @[Conditional.scala 40:58] - else : @[Conditional.scala 39:67] - node _T_101 = eq(UInt<3>("h01"), buf_state) @[Conditional.scala 37:30] - when _T_101 : @[Conditional.scala 39:67] - node _T_102 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 182:54] - node _T_103 = eq(_T_102, UInt<1>("h00")) @[axi4_to_ahb.scala 182:61] - node _T_104 = and(master_valid, _T_103) @[axi4_to_ahb.scala 182:41] - node _T_105 = bits(_T_104, 0, 0) @[axi4_to_ahb.scala 182:82] - node _T_106 = mux(_T_105, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 182:26] - buf_nxtstate <= _T_106 @[axi4_to_ahb.scala 182:20] - node _T_107 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 183:51] - node _T_108 = neq(_T_107, UInt<1>("h00")) @[axi4_to_ahb.scala 183:58] - node _T_109 = and(ahb_hready_q, _T_108) @[axi4_to_ahb.scala 183:36] - node _T_110 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 183:72] - node _T_111 = and(_T_109, _T_110) @[axi4_to_ahb.scala 183:70] - buf_state_en <= _T_111 @[axi4_to_ahb.scala 183:20] - node _T_112 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 184:34] - node _T_113 = and(buf_state_en, _T_112) @[axi4_to_ahb.scala 184:32] - cmd_done <= _T_113 @[axi4_to_ahb.scala 184:16] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 185:20] - node _T_114 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 186:52] - node _T_115 = neq(_T_114, UInt<1>("h00")) @[axi4_to_ahb.scala 186:59] - node _T_116 = and(ahb_hready_q, _T_115) @[axi4_to_ahb.scala 186:37] - node _T_117 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 186:73] - node _T_118 = and(_T_116, _T_117) @[axi4_to_ahb.scala 186:71] - node _T_119 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 186:122] - node _T_120 = eq(_T_119, UInt<1>("h00")) @[axi4_to_ahb.scala 186:129] - node _T_121 = and(master_valid, _T_120) @[axi4_to_ahb.scala 186:109] - node _T_122 = bits(_T_121, 0, 0) @[axi4_to_ahb.scala 186:150] - node _T_123 = mux(_T_122, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 186:94] - node _T_124 = eq(_T_123, UInt<3>("h06")) @[axi4_to_ahb.scala 186:174] - node _T_125 = and(_T_118, _T_124) @[axi4_to_ahb.scala 186:88] - master_ready <= _T_125 @[axi4_to_ahb.scala 186:20] - buf_wr_en <= master_ready @[axi4_to_ahb.scala 187:17] - node _T_126 = and(master_ready, master_valid) @[axi4_to_ahb.scala 188:33] - bypass_en <= _T_126 @[axi4_to_ahb.scala 188:17] - node _T_127 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 189:47] - node _T_128 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 189:62] - node _T_129 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 189:78] - node _T_130 = mux(_T_127, _T_128, _T_129) @[axi4_to_ahb.scala 189:30] - buf_cmd_byte_ptr <= _T_130 @[axi4_to_ahb.scala 189:24] - node _T_131 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 190:48] - node _T_132 = or(_T_131, bypass_en) @[axi4_to_ahb.scala 190:62] - node _T_133 = bits(_T_132, 0, 0) @[Bitwise.scala 72:15] - node _T_134 = mux(_T_133, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_135 = and(UInt<2>("h02"), _T_134) @[axi4_to_ahb.scala 190:36] - io.ahb.out.htrans <= _T_135 @[axi4_to_ahb.scala 190:25] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_136 = eq(UInt<3>("h06"), buf_state) @[Conditional.scala 37:30] - when _T_136 : @[Conditional.scala 39:67] - node _T_137 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 194:39] - node _T_138 = and(ahb_hready_q, _T_137) @[axi4_to_ahb.scala 194:37] - node _T_139 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 194:82] - node _T_140 = eq(_T_139, UInt<1>("h01")) @[axi4_to_ahb.scala 194:89] - node _T_141 = and(master_valid, _T_140) @[axi4_to_ahb.scala 194:70] - node _T_142 = not(_T_141) @[axi4_to_ahb.scala 194:55] - node _T_143 = and(_T_138, _T_142) @[axi4_to_ahb.scala 194:53] - master_ready <= _T_143 @[axi4_to_ahb.scala 194:20] - node _T_144 = and(master_valid, master_ready) @[axi4_to_ahb.scala 195:34] - node _T_145 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 195:62] - node _T_146 = eq(_T_145, UInt<1>("h00")) @[axi4_to_ahb.scala 195:69] - node _T_147 = and(_T_144, _T_146) @[axi4_to_ahb.scala 195:49] - buf_wr_en <= _T_147 @[axi4_to_ahb.scala 195:17] - node _T_148 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 196:45] - node _T_149 = and(master_valid, master_ready) @[axi4_to_ahb.scala 196:82] - node _T_150 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 196:110] - node _T_151 = eq(_T_150, UInt<1>("h00")) @[axi4_to_ahb.scala 196:117] - node _T_152 = and(_T_149, _T_151) @[axi4_to_ahb.scala 196:97] - node _T_153 = bits(_T_152, 0, 0) @[axi4_to_ahb.scala 196:138] - node _T_154 = mux(_T_153, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 196:67] - node _T_155 = mux(_T_148, UInt<3>("h07"), _T_154) @[axi4_to_ahb.scala 196:26] - buf_nxtstate <= _T_155 @[axi4_to_ahb.scala 196:20] - node _T_156 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 197:37] - buf_state_en <= _T_156 @[axi4_to_ahb.scala 197:20] - buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 198:22] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 199:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 200:23] - node _T_157 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 201:41] - node _T_158 = and(buf_state_en, _T_157) @[axi4_to_ahb.scala 201:39] - slave_valid_pre <= _T_158 @[axi4_to_ahb.scala 201:23] - node _T_159 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 202:34] - node _T_160 = and(buf_state_en, _T_159) @[axi4_to_ahb.scala 202:32] - cmd_done <= _T_160 @[axi4_to_ahb.scala 202:16] - node _T_161 = and(master_ready, master_valid) @[axi4_to_ahb.scala 203:33] - node _T_162 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 203:64] - node _T_163 = and(_T_161, _T_162) @[axi4_to_ahb.scala 203:48] - node _T_164 = and(_T_163, buf_state_en) @[axi4_to_ahb.scala 203:79] - bypass_en <= _T_164 @[axi4_to_ahb.scala 203:17] - node _T_165 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 204:47] - node _T_166 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 204:62] - node _T_167 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 204:78] - node _T_168 = mux(_T_165, _T_166, _T_167) @[axi4_to_ahb.scala 204:30] - buf_cmd_byte_ptr <= _T_168 @[axi4_to_ahb.scala 204:24] - node _T_169 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 205:63] - node _T_170 = and(_T_169, buf_state_en) @[axi4_to_ahb.scala 205:78] - node _T_171 = eq(_T_170, UInt<1>("h00")) @[axi4_to_ahb.scala 205:47] - node _T_172 = bits(_T_171, 0, 0) @[Bitwise.scala 72:15] - node _T_173 = mux(_T_172, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_174 = and(UInt<2>("h02"), _T_173) @[axi4_to_ahb.scala 205:36] - io.ahb.out.htrans <= _T_174 @[axi4_to_ahb.scala 205:25] - slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 206:20] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_175 = eq(UInt<3>("h07"), buf_state) @[Conditional.scala 37:30] - when _T_175 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 210:20] - node _T_176 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 211:51] - node _T_177 = neq(_T_176, UInt<1>("h00")) @[axi4_to_ahb.scala 211:58] - node _T_178 = and(ahb_hready_q, _T_177) @[axi4_to_ahb.scala 211:36] - node _T_179 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 211:72] - node _T_180 = and(_T_178, _T_179) @[axi4_to_ahb.scala 211:70] - buf_state_en <= _T_180 @[axi4_to_ahb.scala 211:20] - slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 212:23] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 213:20] - node _T_181 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 214:35] - buf_cmd_byte_ptr <= _T_181 @[axi4_to_ahb.scala 214:24] - node _T_182 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 215:51] - node _T_183 = bits(_T_182, 0, 0) @[Bitwise.scala 72:15] - node _T_184 = mux(_T_183, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_185 = and(UInt<2>("h02"), _T_184) @[axi4_to_ahb.scala 215:41] - io.ahb.out.htrans <= _T_185 @[axi4_to_ahb.scala 215:25] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_186 = eq(UInt<3>("h03"), buf_state) @[Conditional.scala 37:30] - when _T_186 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 219:20] - node _T_187 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 220:37] - buf_state_en <= _T_187 @[axi4_to_ahb.scala 220:20] - buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 221:22] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 222:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 223:23] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 224:20] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_188 = eq(UInt<3>("h02"), buf_state) @[Conditional.scala 37:30] - when _T_188 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 228:20] - node _T_189 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 229:33] - node _T_190 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 229:63] - node _T_191 = neq(_T_190, UInt<1>("h00")) @[axi4_to_ahb.scala 229:70] - node _T_192 = and(_T_189, _T_191) @[axi4_to_ahb.scala 229:48] - trxn_done <= _T_192 @[axi4_to_ahb.scala 229:17] - buf_state_en <= trxn_done @[axi4_to_ahb.scala 230:20] - buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 231:27] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 232:20] - node _T_193 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 233:47] - node _T_194 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 233:85] - node _T_195 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 233:103] - node _T_196 = add(_T_194, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_197 = tail(_T_196, 1) @[axi4_to_ahb.scala 135:52] - node _T_198 = mux(UInt<1>("h01"), _T_197, _T_194) @[axi4_to_ahb.scala 135:24] - node _T_199 = bits(_T_195, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_200 = geq(UInt<1>("h00"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_201 = and(_T_199, _T_200) @[axi4_to_ahb.scala 136:48] - node _T_202 = bits(_T_195, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_203 = geq(UInt<1>("h01"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_204 = and(_T_202, _T_203) @[axi4_to_ahb.scala 136:48] - node _T_205 = bits(_T_195, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_206 = geq(UInt<2>("h02"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_207 = and(_T_205, _T_206) @[axi4_to_ahb.scala 136:48] - node _T_208 = bits(_T_195, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_209 = geq(UInt<2>("h03"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_210 = and(_T_208, _T_209) @[axi4_to_ahb.scala 136:48] - node _T_211 = bits(_T_195, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_212 = geq(UInt<3>("h04"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_213 = and(_T_211, _T_212) @[axi4_to_ahb.scala 136:48] - node _T_214 = bits(_T_195, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_215 = geq(UInt<3>("h05"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_216 = and(_T_214, _T_215) @[axi4_to_ahb.scala 136:48] - node _T_217 = bits(_T_195, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_218 = geq(UInt<3>("h06"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_219 = and(_T_217, _T_218) @[axi4_to_ahb.scala 136:48] - node _T_220 = bits(_T_195, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_221 = geq(UInt<3>("h07"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_222 = and(_T_220, _T_221) @[axi4_to_ahb.scala 136:48] - node _T_223 = mux(_T_222, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_224 = mux(_T_219, UInt<3>("h06"), _T_223) @[Mux.scala 98:16] - node _T_225 = mux(_T_216, UInt<3>("h05"), _T_224) @[Mux.scala 98:16] - node _T_226 = mux(_T_213, UInt<3>("h04"), _T_225) @[Mux.scala 98:16] - node _T_227 = mux(_T_210, UInt<2>("h03"), _T_226) @[Mux.scala 98:16] - node _T_228 = mux(_T_207, UInt<2>("h02"), _T_227) @[Mux.scala 98:16] - node _T_229 = mux(_T_204, UInt<1>("h01"), _T_228) @[Mux.scala 98:16] - node _T_230 = mux(_T_201, UInt<1>("h00"), _T_229) @[Mux.scala 98:16] - node _T_231 = mux(_T_193, _T_230, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 233:30] - buf_cmd_byte_ptr <= _T_231 @[axi4_to_ahb.scala 233:24] - node _T_232 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 234:65] - node _T_233 = or(buf_aligned, _T_232) @[axi4_to_ahb.scala 234:44] - node _T_234 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 234:127] - node _T_235 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 234:145] - node _T_236 = add(_T_234, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_237 = tail(_T_236, 1) @[axi4_to_ahb.scala 135:52] - node _T_238 = mux(UInt<1>("h01"), _T_237, _T_234) @[axi4_to_ahb.scala 135:24] - node _T_239 = bits(_T_235, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_240 = geq(UInt<1>("h00"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_241 = and(_T_239, _T_240) @[axi4_to_ahb.scala 136:48] - node _T_242 = bits(_T_235, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_243 = geq(UInt<1>("h01"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_244 = and(_T_242, _T_243) @[axi4_to_ahb.scala 136:48] - node _T_245 = bits(_T_235, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_246 = geq(UInt<2>("h02"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_247 = and(_T_245, _T_246) @[axi4_to_ahb.scala 136:48] - node _T_248 = bits(_T_235, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_249 = geq(UInt<2>("h03"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_250 = and(_T_248, _T_249) @[axi4_to_ahb.scala 136:48] - node _T_251 = bits(_T_235, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_252 = geq(UInt<3>("h04"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_253 = and(_T_251, _T_252) @[axi4_to_ahb.scala 136:48] - node _T_254 = bits(_T_235, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_255 = geq(UInt<3>("h05"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_256 = and(_T_254, _T_255) @[axi4_to_ahb.scala 136:48] - node _T_257 = bits(_T_235, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_258 = geq(UInt<3>("h06"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_259 = and(_T_257, _T_258) @[axi4_to_ahb.scala 136:48] - node _T_260 = bits(_T_235, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_261 = geq(UInt<3>("h07"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_262 = and(_T_260, _T_261) @[axi4_to_ahb.scala 136:48] - node _T_263 = mux(_T_262, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_264 = mux(_T_259, UInt<3>("h06"), _T_263) @[Mux.scala 98:16] - node _T_265 = mux(_T_256, UInt<3>("h05"), _T_264) @[Mux.scala 98:16] - node _T_266 = mux(_T_253, UInt<3>("h04"), _T_265) @[Mux.scala 98:16] - node _T_267 = mux(_T_250, UInt<2>("h03"), _T_266) @[Mux.scala 98:16] - node _T_268 = mux(_T_247, UInt<2>("h02"), _T_267) @[Mux.scala 98:16] - node _T_269 = mux(_T_244, UInt<1>("h01"), _T_268) @[Mux.scala 98:16] - node _T_270 = mux(_T_241, UInt<1>("h00"), _T_269) @[Mux.scala 98:16] - node _T_271 = dshr(buf_byteen, _T_270) @[axi4_to_ahb.scala 234:92] - node _T_272 = bits(_T_271, 0, 0) @[axi4_to_ahb.scala 234:92] - node _T_273 = eq(_T_272, UInt<1>("h00")) @[axi4_to_ahb.scala 234:163] - node _T_274 = or(_T_233, _T_273) @[axi4_to_ahb.scala 234:79] - node _T_275 = and(trxn_done, _T_274) @[axi4_to_ahb.scala 234:29] - cmd_done <= _T_275 @[axi4_to_ahb.scala 234:16] - node _T_276 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 235:47] - node _T_277 = eq(_T_276, UInt<1>("h00")) @[axi4_to_ahb.scala 235:36] - node _T_278 = bits(_T_277, 0, 0) @[Bitwise.scala 72:15] - node _T_279 = mux(_T_278, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_280 = and(_T_279, UInt<2>("h02")) @[axi4_to_ahb.scala 235:61] - io.ahb.out.htrans <= _T_280 @[axi4_to_ahb.scala 235:25] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_281 = eq(UInt<3>("h04"), buf_state) @[Conditional.scala 37:30] - when _T_281 : @[Conditional.scala 39:67] - node _T_282 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 239:34] - node _T_283 = or(_T_282, ahb_hresp_q) @[axi4_to_ahb.scala 239:50] - buf_state_en <= _T_283 @[axi4_to_ahb.scala 239:20] - node _T_284 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 240:38] - node _T_285 = and(buf_state_en, _T_284) @[axi4_to_ahb.scala 240:36] - node _T_286 = and(_T_285, slave_ready) @[axi4_to_ahb.scala 240:51] - master_ready <= _T_286 @[axi4_to_ahb.scala 240:20] - node _T_287 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 241:42] - node _T_288 = or(ahb_hresp_q, _T_287) @[axi4_to_ahb.scala 241:40] - node _T_289 = and(master_valid, master_valid) @[axi4_to_ahb.scala 241:80] - node _T_290 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 241:111] - node _T_291 = eq(_T_290, UInt<1>("h01")) @[axi4_to_ahb.scala 241:117] - node _T_292 = bits(_T_291, 0, 0) @[axi4_to_ahb.scala 241:132] - node _T_293 = mux(_T_292, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 241:99] - node _T_294 = mux(_T_289, _T_293, UInt<3>("h00")) @[axi4_to_ahb.scala 241:65] - node _T_295 = mux(_T_288, UInt<3>("h05"), _T_294) @[axi4_to_ahb.scala 241:26] - buf_nxtstate <= _T_295 @[axi4_to_ahb.scala 241:20] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 242:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 243:23] - node _T_296 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 244:33] - node _T_297 = eq(_T_296, UInt<1>("h01")) @[axi4_to_ahb.scala 244:39] - buf_write_in <= _T_297 @[axi4_to_ahb.scala 244:20] - node _T_298 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 245:50] - node _T_299 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 245:78] - node _T_300 = or(_T_298, _T_299) @[axi4_to_ahb.scala 245:62] - node _T_301 = and(buf_state_en, _T_300) @[axi4_to_ahb.scala 245:33] - buf_wr_en <= _T_301 @[axi4_to_ahb.scala 245:17] - buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 246:22] - node _T_302 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 247:65] - node _T_303 = neq(_T_302, UInt<1>("h00")) @[axi4_to_ahb.scala 247:71] - node _T_304 = and(ahb_hready_q, _T_303) @[axi4_to_ahb.scala 247:50] - node _T_305 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 248:29] - node _T_306 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 248:85] - node _T_307 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 248:101] - node _T_308 = add(_T_306, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_309 = tail(_T_308, 1) @[axi4_to_ahb.scala 135:52] - node _T_310 = mux(UInt<1>("h01"), _T_309, _T_306) @[axi4_to_ahb.scala 135:24] - node _T_311 = bits(_T_307, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_312 = geq(UInt<1>("h00"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_313 = and(_T_311, _T_312) @[axi4_to_ahb.scala 136:48] - node _T_314 = bits(_T_307, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_315 = geq(UInt<1>("h01"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_316 = and(_T_314, _T_315) @[axi4_to_ahb.scala 136:48] - node _T_317 = bits(_T_307, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_318 = geq(UInt<2>("h02"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_319 = and(_T_317, _T_318) @[axi4_to_ahb.scala 136:48] - node _T_320 = bits(_T_307, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_321 = geq(UInt<2>("h03"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_322 = and(_T_320, _T_321) @[axi4_to_ahb.scala 136:48] - node _T_323 = bits(_T_307, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_324 = geq(UInt<3>("h04"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_325 = and(_T_323, _T_324) @[axi4_to_ahb.scala 136:48] - node _T_326 = bits(_T_307, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_327 = geq(UInt<3>("h05"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_328 = and(_T_326, _T_327) @[axi4_to_ahb.scala 136:48] - node _T_329 = bits(_T_307, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_330 = geq(UInt<3>("h06"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_331 = and(_T_329, _T_330) @[axi4_to_ahb.scala 136:48] - node _T_332 = bits(_T_307, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_333 = geq(UInt<3>("h07"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_334 = and(_T_332, _T_333) @[axi4_to_ahb.scala 136:48] - node _T_335 = mux(_T_334, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_336 = mux(_T_331, UInt<3>("h06"), _T_335) @[Mux.scala 98:16] - node _T_337 = mux(_T_328, UInt<3>("h05"), _T_336) @[Mux.scala 98:16] - node _T_338 = mux(_T_325, UInt<3>("h04"), _T_337) @[Mux.scala 98:16] - node _T_339 = mux(_T_322, UInt<2>("h03"), _T_338) @[Mux.scala 98:16] - node _T_340 = mux(_T_319, UInt<2>("h02"), _T_339) @[Mux.scala 98:16] - node _T_341 = mux(_T_316, UInt<1>("h01"), _T_340) @[Mux.scala 98:16] - node _T_342 = mux(_T_313, UInt<1>("h00"), _T_341) @[Mux.scala 98:16] - node _T_343 = dshr(buf_byteen, _T_342) @[axi4_to_ahb.scala 248:51] - node _T_344 = bits(_T_343, 0, 0) @[axi4_to_ahb.scala 248:51] - node _T_345 = eq(_T_344, UInt<1>("h00")) @[axi4_to_ahb.scala 248:116] - node _T_346 = or(_T_305, _T_345) @[axi4_to_ahb.scala 248:38] - node _T_347 = and(_T_304, _T_346) @[axi4_to_ahb.scala 247:80] - node _T_348 = or(ahb_hresp_q, _T_347) @[axi4_to_ahb.scala 247:34] - cmd_done <= _T_348 @[axi4_to_ahb.scala 247:16] - node _T_349 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 249:33] - node _T_350 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 249:64] - node _T_351 = and(_T_349, _T_350) @[axi4_to_ahb.scala 249:48] - bypass_en <= _T_351 @[axi4_to_ahb.scala 249:17] - node _T_352 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 250:48] - node _T_353 = eq(_T_352, UInt<1>("h00")) @[axi4_to_ahb.scala 250:37] - node _T_354 = or(_T_353, bypass_en) @[axi4_to_ahb.scala 250:61] - node _T_355 = bits(_T_354, 0, 0) @[Bitwise.scala 72:15] - node _T_356 = mux(_T_355, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_357 = and(_T_356, UInt<2>("h02")) @[axi4_to_ahb.scala 250:75] - io.ahb.out.htrans <= _T_357 @[axi4_to_ahb.scala 250:25] - node _T_358 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 251:55] - node _T_359 = and(buf_state_en, _T_358) @[axi4_to_ahb.scala 251:39] - slave_valid_pre <= _T_359 @[axi4_to_ahb.scala 251:23] - node _T_360 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 252:33] - node _T_361 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 252:63] - node _T_362 = neq(_T_361, UInt<1>("h00")) @[axi4_to_ahb.scala 252:69] - node _T_363 = and(_T_360, _T_362) @[axi4_to_ahb.scala 252:48] - trxn_done <= _T_363 @[axi4_to_ahb.scala 252:17] - node _T_364 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 253:40] - buf_cmd_byte_ptr_en <= _T_364 @[axi4_to_ahb.scala 253:27] - node _T_365 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 254:79] - node _T_366 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_367 = tail(_T_366, 1) @[axi4_to_ahb.scala 135:52] - node _T_368 = mux(UInt<1>("h00"), _T_367, UInt<3>("h00")) @[axi4_to_ahb.scala 135:24] - node _T_369 = bits(_T_365, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_370 = geq(UInt<1>("h00"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_371 = and(_T_369, _T_370) @[axi4_to_ahb.scala 136:48] - node _T_372 = bits(_T_365, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_373 = geq(UInt<1>("h01"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_374 = and(_T_372, _T_373) @[axi4_to_ahb.scala 136:48] - node _T_375 = bits(_T_365, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_376 = geq(UInt<2>("h02"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_377 = and(_T_375, _T_376) @[axi4_to_ahb.scala 136:48] - node _T_378 = bits(_T_365, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_379 = geq(UInt<2>("h03"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_380 = and(_T_378, _T_379) @[axi4_to_ahb.scala 136:48] - node _T_381 = bits(_T_365, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_382 = geq(UInt<3>("h04"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_383 = and(_T_381, _T_382) @[axi4_to_ahb.scala 136:48] - node _T_384 = bits(_T_365, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_385 = geq(UInt<3>("h05"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_386 = and(_T_384, _T_385) @[axi4_to_ahb.scala 136:48] - node _T_387 = bits(_T_365, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_388 = geq(UInt<3>("h06"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_389 = and(_T_387, _T_388) @[axi4_to_ahb.scala 136:48] - node _T_390 = bits(_T_365, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_391 = geq(UInt<3>("h07"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_392 = and(_T_390, _T_391) @[axi4_to_ahb.scala 136:48] - node _T_393 = mux(_T_392, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_394 = mux(_T_389, UInt<3>("h06"), _T_393) @[Mux.scala 98:16] - node _T_395 = mux(_T_386, UInt<3>("h05"), _T_394) @[Mux.scala 98:16] - node _T_396 = mux(_T_383, UInt<3>("h04"), _T_395) @[Mux.scala 98:16] - node _T_397 = mux(_T_380, UInt<2>("h03"), _T_396) @[Mux.scala 98:16] - node _T_398 = mux(_T_377, UInt<2>("h02"), _T_397) @[Mux.scala 98:16] - node _T_399 = mux(_T_374, UInt<1>("h01"), _T_398) @[Mux.scala 98:16] - node _T_400 = mux(_T_371, UInt<1>("h00"), _T_399) @[Mux.scala 98:16] - node _T_401 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 254:141] - node _T_402 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 254:157] - node _T_403 = add(_T_401, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_404 = tail(_T_403, 1) @[axi4_to_ahb.scala 135:52] - node _T_405 = mux(UInt<1>("h01"), _T_404, _T_401) @[axi4_to_ahb.scala 135:24] - node _T_406 = bits(_T_402, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_407 = geq(UInt<1>("h00"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_408 = and(_T_406, _T_407) @[axi4_to_ahb.scala 136:48] - node _T_409 = bits(_T_402, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_410 = geq(UInt<1>("h01"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_411 = and(_T_409, _T_410) @[axi4_to_ahb.scala 136:48] - node _T_412 = bits(_T_402, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_413 = geq(UInt<2>("h02"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_414 = and(_T_412, _T_413) @[axi4_to_ahb.scala 136:48] - node _T_415 = bits(_T_402, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_416 = geq(UInt<2>("h03"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_417 = and(_T_415, _T_416) @[axi4_to_ahb.scala 136:48] - node _T_418 = bits(_T_402, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_419 = geq(UInt<3>("h04"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_420 = and(_T_418, _T_419) @[axi4_to_ahb.scala 136:48] - node _T_421 = bits(_T_402, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_422 = geq(UInt<3>("h05"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_423 = and(_T_421, _T_422) @[axi4_to_ahb.scala 136:48] - node _T_424 = bits(_T_402, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_425 = geq(UInt<3>("h06"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_426 = and(_T_424, _T_425) @[axi4_to_ahb.scala 136:48] - node _T_427 = bits(_T_402, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_428 = geq(UInt<3>("h07"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_429 = and(_T_427, _T_428) @[axi4_to_ahb.scala 136:48] - node _T_430 = mux(_T_429, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_431 = mux(_T_426, UInt<3>("h06"), _T_430) @[Mux.scala 98:16] - node _T_432 = mux(_T_423, UInt<3>("h05"), _T_431) @[Mux.scala 98:16] - node _T_433 = mux(_T_420, UInt<3>("h04"), _T_432) @[Mux.scala 98:16] - node _T_434 = mux(_T_417, UInt<2>("h03"), _T_433) @[Mux.scala 98:16] - node _T_435 = mux(_T_414, UInt<2>("h02"), _T_434) @[Mux.scala 98:16] - node _T_436 = mux(_T_411, UInt<1>("h01"), _T_435) @[Mux.scala 98:16] - node _T_437 = mux(_T_408, UInt<1>("h00"), _T_436) @[Mux.scala 98:16] - node _T_438 = mux(trxn_done, _T_437, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 254:97] - node _T_439 = mux(bypass_en, _T_400, _T_438) @[axi4_to_ahb.scala 254:30] - buf_cmd_byte_ptr <= _T_439 @[axi4_to_ahb.scala 254:24] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_440 = eq(UInt<3>("h05"), buf_state) @[Conditional.scala 37:30] - when _T_440 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 257:20] - buf_state_en <= slave_ready @[axi4_to_ahb.scala 258:20] - slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 259:23] - slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 260:23] - skip @[Conditional.scala 39:67] - cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 264:16] - node _T_441 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 265:33] - node _T_442 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 265:73] - node _T_443 = eq(_T_442, UInt<1>("h01")) @[axi4_to_ahb.scala 265:80] - node _T_444 = and(buf_aligned_in, _T_443) @[axi4_to_ahb.scala 265:60] - node _T_445 = bits(_T_444, 0, 0) @[axi4_to_ahb.scala 265:100] - node _T_446 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 265:132] - node _T_447 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:50] - node _T_448 = eq(_T_447, UInt<8>("h0ff")) @[axi4_to_ahb.scala 127:57] - node _T_449 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:81] - node _T_450 = eq(_T_449, UInt<8>("h0f")) @[axi4_to_ahb.scala 127:88] - node _T_451 = or(_T_448, _T_450) @[axi4_to_ahb.scala 127:70] - node _T_452 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:117] - node _T_453 = eq(_T_452, UInt<8>("h03")) @[axi4_to_ahb.scala 127:124] - node _T_454 = or(_T_451, _T_453) @[axi4_to_ahb.scala 127:106] - node _T_455 = bits(_T_454, 0, 0) @[Bitwise.scala 72:15] - node _T_456 = mux(_T_455, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_457 = and(UInt<3>("h00"), _T_456) @[axi4_to_ahb.scala 127:29] - node _T_458 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 128:35] - node _T_459 = eq(_T_458, UInt<8>("h0c")) @[axi4_to_ahb.scala 128:42] - node _T_460 = bits(_T_459, 0, 0) @[Bitwise.scala 72:15] - node _T_461 = mux(_T_460, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_462 = and(UInt<2>("h02"), _T_461) @[axi4_to_ahb.scala 128:15] - node _T_463 = or(_T_457, _T_462) @[axi4_to_ahb.scala 127:146] - node _T_464 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 129:36] - node _T_465 = eq(_T_464, UInt<8>("h0f0")) @[axi4_to_ahb.scala 129:43] - node _T_466 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 129:67] - node _T_467 = eq(_T_466, UInt<8>("h03")) @[axi4_to_ahb.scala 129:74] - node _T_468 = or(_T_465, _T_467) @[axi4_to_ahb.scala 129:56] - node _T_469 = bits(_T_468, 0, 0) @[Bitwise.scala 72:15] - node _T_470 = mux(_T_469, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_471 = and(UInt<3>("h04"), _T_470) @[axi4_to_ahb.scala 129:15] - node _T_472 = or(_T_463, _T_471) @[axi4_to_ahb.scala 128:63] - node _T_473 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 130:35] - node _T_474 = eq(_T_473, UInt<8>("h0c0")) @[axi4_to_ahb.scala 130:42] - node _T_475 = bits(_T_474, 0, 0) @[Bitwise.scala 72:15] - node _T_476 = mux(_T_475, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_477 = and(UInt<3>("h06"), _T_476) @[axi4_to_ahb.scala 130:15] - node _T_478 = or(_T_472, _T_477) @[axi4_to_ahb.scala 129:96] - node _T_479 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 131:33] - node _T_480 = eq(_T_479, UInt<8>("h0c0")) @[axi4_to_ahb.scala 131:40] - node _T_481 = bits(_T_480, 0, 0) @[Bitwise.scala 72:15] - node _T_482 = mux(_T_481, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_483 = and(UInt<3>("h06"), _T_482) @[axi4_to_ahb.scala 131:13] - node _T_484 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 265:152] - node _T_485 = mux(_T_445, _T_478, _T_484) @[axi4_to_ahb.scala 265:43] - node _T_486 = cat(_T_441, _T_485) @[Cat.scala 29:58] - buf_addr_in <= _T_486 @[axi4_to_ahb.scala 265:15] - node _T_487 = bits(master_tag, 2, 0) @[axi4_to_ahb.scala 266:27] - buf_tag_in <= _T_487 @[axi4_to_ahb.scala 266:14] - node _T_488 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 267:32] - buf_byteen_in <= _T_488 @[axi4_to_ahb.scala 267:17] - node _T_489 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 268:33] - node _T_490 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 268:59] - node _T_491 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 268:80] - node _T_492 = mux(_T_489, _T_490, _T_491) @[axi4_to_ahb.scala 268:21] - buf_data_in <= _T_492 @[axi4_to_ahb.scala 268:15] - node _T_493 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 269:52] - node _T_494 = eq(_T_493, UInt<2>("h03")) @[axi4_to_ahb.scala 269:58] - node _T_495 = and(buf_aligned_in, _T_494) @[axi4_to_ahb.scala 269:38] - node _T_496 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 269:84] - node _T_497 = eq(_T_496, UInt<1>("h01")) @[axi4_to_ahb.scala 269:91] - node _T_498 = and(_T_495, _T_497) @[axi4_to_ahb.scala 269:71] - node _T_499 = bits(_T_498, 0, 0) @[axi4_to_ahb.scala 269:111] - node _T_500 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 269:142] - node _T_501 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 121:42] - node _T_502 = eq(_T_501, UInt<8>("h0ff")) @[axi4_to_ahb.scala 121:49] - node _T_503 = bits(_T_502, 0, 0) @[Bitwise.scala 72:15] - node _T_504 = mux(_T_503, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_505 = and(UInt<2>("h03"), _T_504) @[axi4_to_ahb.scala 121:25] - node _T_506 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 122:35] - node _T_507 = eq(_T_506, UInt<8>("h0f0")) @[axi4_to_ahb.scala 122:42] - node _T_508 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 122:64] - node _T_509 = eq(_T_508, UInt<8>("h0f")) @[axi4_to_ahb.scala 122:71] - node _T_510 = or(_T_507, _T_509) @[axi4_to_ahb.scala 122:55] - node _T_511 = bits(_T_510, 0, 0) @[Bitwise.scala 72:15] - node _T_512 = mux(_T_511, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_513 = and(UInt<2>("h02"), _T_512) @[axi4_to_ahb.scala 122:16] - node _T_514 = or(_T_505, _T_513) @[axi4_to_ahb.scala 121:64] - node _T_515 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:40] - node _T_516 = eq(_T_515, UInt<8>("h0c0")) @[axi4_to_ahb.scala 123:47] - node _T_517 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:69] - node _T_518 = eq(_T_517, UInt<6>("h030")) @[axi4_to_ahb.scala 123:76] - node _T_519 = or(_T_516, _T_518) @[axi4_to_ahb.scala 123:60] - node _T_520 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:98] - node _T_521 = eq(_T_520, UInt<8>("h0c")) @[axi4_to_ahb.scala 123:105] - node _T_522 = or(_T_519, _T_521) @[axi4_to_ahb.scala 123:89] - node _T_523 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:132] - node _T_524 = eq(_T_523, UInt<8>("h03")) @[axi4_to_ahb.scala 123:139] - node _T_525 = or(_T_522, _T_524) @[axi4_to_ahb.scala 123:123] - node _T_526 = bits(_T_525, 0, 0) @[Bitwise.scala 72:15] - node _T_527 = mux(_T_526, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_528 = and(UInt<2>("h01"), _T_527) @[axi4_to_ahb.scala 123:21] - node _T_529 = or(_T_514, _T_528) @[axi4_to_ahb.scala 122:93] - node _T_530 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 269:161] - node _T_531 = mux(_T_499, _T_529, _T_530) @[axi4_to_ahb.scala 269:21] - buf_size_in <= _T_531 @[axi4_to_ahb.scala 269:15] - node _T_532 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 270:32] - node _T_533 = eq(_T_532, UInt<1>("h00")) @[axi4_to_ahb.scala 270:39] - node _T_534 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 271:17] - node _T_535 = eq(_T_534, UInt<1>("h00")) @[axi4_to_ahb.scala 271:24] - node _T_536 = or(_T_533, _T_535) @[axi4_to_ahb.scala 270:48] - node _T_537 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 271:47] - node _T_538 = eq(_T_537, UInt<2>("h01")) @[axi4_to_ahb.scala 271:54] - node _T_539 = or(_T_536, _T_538) @[axi4_to_ahb.scala 271:33] - node _T_540 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 271:86] - node _T_541 = eq(_T_540, UInt<2>("h02")) @[axi4_to_ahb.scala 271:93] - node _T_542 = or(_T_539, _T_541) @[axi4_to_ahb.scala 271:72] - node _T_543 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 272:18] - node _T_544 = eq(_T_543, UInt<2>("h03")) @[axi4_to_ahb.scala 272:25] - node _T_545 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:55] - node _T_546 = eq(_T_545, UInt<2>("h03")) @[axi4_to_ahb.scala 272:62] - node _T_547 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:90] - node _T_548 = eq(_T_547, UInt<4>("h0c")) @[axi4_to_ahb.scala 272:97] - node _T_549 = or(_T_546, _T_548) @[axi4_to_ahb.scala 272:74] - node _T_550 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:125] - node _T_551 = eq(_T_550, UInt<6>("h030")) @[axi4_to_ahb.scala 272:132] - node _T_552 = or(_T_549, _T_551) @[axi4_to_ahb.scala 272:109] - node _T_553 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:161] - node _T_554 = eq(_T_553, UInt<8>("h0c0")) @[axi4_to_ahb.scala 272:168] - node _T_555 = or(_T_552, _T_554) @[axi4_to_ahb.scala 272:145] - node _T_556 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 273:21] - node _T_557 = eq(_T_556, UInt<4>("h0f")) @[axi4_to_ahb.scala 273:28] - node _T_558 = or(_T_555, _T_557) @[axi4_to_ahb.scala 272:181] - node _T_559 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 273:56] - node _T_560 = eq(_T_559, UInt<8>("h0f0")) @[axi4_to_ahb.scala 273:63] - node _T_561 = or(_T_558, _T_560) @[axi4_to_ahb.scala 273:40] - node _T_562 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 273:92] - node _T_563 = eq(_T_562, UInt<8>("h0ff")) @[axi4_to_ahb.scala 273:99] - node _T_564 = or(_T_561, _T_563) @[axi4_to_ahb.scala 273:76] - node _T_565 = and(_T_544, _T_564) @[axi4_to_ahb.scala 272:38] - node _T_566 = or(_T_542, _T_565) @[axi4_to_ahb.scala 271:106] - buf_aligned_in <= _T_566 @[axi4_to_ahb.scala 270:18] - node _T_567 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 275:43] - node _T_568 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 275:62] - node _T_569 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 275:87] - node _T_570 = cat(_T_568, _T_569) @[Cat.scala 29:58] - node _T_571 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 275:108] - node _T_572 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 275:133] - node _T_573 = cat(_T_571, _T_572) @[Cat.scala 29:58] - node _T_574 = mux(_T_567, _T_570, _T_573) @[axi4_to_ahb.scala 275:26] - io.ahb.out.haddr <= _T_574 @[axi4_to_ahb.scala 275:20] - node _T_575 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 276:43] - node _T_576 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15] - node _T_577 = mux(_T_576, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_578 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 276:94] - node _T_579 = and(_T_577, _T_578) @[axi4_to_ahb.scala 276:81] - node _T_580 = cat(UInt<1>("h00"), _T_579) @[Cat.scala 29:58] - node _T_581 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15] - node _T_582 = mux(_T_581, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_583 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 276:148] - node _T_584 = and(_T_582, _T_583) @[axi4_to_ahb.scala 276:138] - node _T_585 = cat(UInt<1>("h00"), _T_584) @[Cat.scala 29:58] - node _T_586 = mux(_T_575, _T_580, _T_585) @[axi4_to_ahb.scala 276:26] - io.ahb.out.hsize <= _T_586 @[axi4_to_ahb.scala 276:20] - io.ahb.out.hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 278:21] - io.ahb.out.hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 279:24] - node _T_587 = bits(io.axi.ar.bits.prot, 2, 2) @[axi4_to_ahb.scala 280:57] - node _T_588 = eq(_T_587, UInt<1>("h00")) @[axi4_to_ahb.scala 280:37] - node _T_589 = cat(UInt<1>("h01"), _T_588) @[Cat.scala 29:58] - io.ahb.out.hprot <= _T_589 @[axi4_to_ahb.scala 280:20] - node _T_590 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 281:44] - node _T_591 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 281:59] - node _T_592 = eq(_T_591, UInt<1>("h01")) @[axi4_to_ahb.scala 281:66] - node _T_593 = mux(_T_590, _T_592, buf_write) @[axi4_to_ahb.scala 281:27] - io.ahb.out.hwrite <= _T_593 @[axi4_to_ahb.scala 281:21] - node _T_594 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 282:32] - io.ahb.out.hwdata <= _T_594 @[axi4_to_ahb.scala 282:21] - slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 284:15] - node _T_595 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 285:43] - node _T_596 = mux(_T_595, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 285:23] - node _T_597 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15] - node _T_598 = mux(_T_597, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_599 = and(_T_598, UInt<2>("h02")) @[axi4_to_ahb.scala 285:88] - node _T_600 = cat(_T_596, _T_599) @[Cat.scala 29:58] - slave_opc <= _T_600 @[axi4_to_ahb.scala 285:13] - node _T_601 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 286:41] - node _T_602 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 286:66] - node _T_603 = cat(_T_602, _T_602) @[Cat.scala 29:58] - node _T_604 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 286:91] - node _T_605 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 286:110] - node _T_606 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 286:131] - node _T_607 = mux(_T_604, _T_605, _T_606) @[axi4_to_ahb.scala 286:79] - node _T_608 = mux(_T_601, _T_603, _T_607) @[axi4_to_ahb.scala 286:21] - slave_rdata <= _T_608 @[axi4_to_ahb.scala 286:15] - node _T_609 = bits(slvbuf_tag, 2, 0) @[axi4_to_ahb.scala 287:26] - slave_tag <= _T_609 @[axi4_to_ahb.scala 287:13] - node _T_610 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 289:37] - node _T_611 = neq(_T_610, UInt<1>("h00")) @[axi4_to_ahb.scala 289:44] - node _T_612 = and(_T_611, io.ahb.in.hready) @[axi4_to_ahb.scala 289:56] - node _T_613 = and(_T_612, io.ahb.out.hwrite) @[axi4_to_ahb.scala 289:75] - last_addr_en <= _T_613 @[axi4_to_ahb.scala 289:16] - node _T_614 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 291:31] - node _T_615 = and(_T_614, master_ready) @[axi4_to_ahb.scala 291:49] - wrbuf_en <= _T_615 @[axi4_to_ahb.scala 291:12] - node _T_616 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 292:35] - node _T_617 = and(_T_616, master_ready) @[axi4_to_ahb.scala 292:52] - wrbuf_data_en <= _T_617 @[axi4_to_ahb.scala 292:17] - node _T_618 = and(master_valid, master_ready) @[axi4_to_ahb.scala 293:34] - node _T_619 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 293:62] - node _T_620 = eq(_T_619, UInt<1>("h01")) @[axi4_to_ahb.scala 293:69] - node _T_621 = and(_T_618, _T_620) @[axi4_to_ahb.scala 293:49] - wrbuf_cmd_sent <= _T_621 @[axi4_to_ahb.scala 293:18] - node _T_622 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 294:33] - node _T_623 = and(wrbuf_cmd_sent, _T_622) @[axi4_to_ahb.scala 294:31] - wrbuf_rst <= _T_623 @[axi4_to_ahb.scala 294:13] - node _T_624 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 296:36] - node _T_625 = and(wrbuf_vld, _T_624) @[axi4_to_ahb.scala 296:34] - node _T_626 = eq(_T_625, UInt<1>("h00")) @[axi4_to_ahb.scala 296:22] - node _T_627 = and(_T_626, master_ready) @[axi4_to_ahb.scala 296:53] - io.axi.aw.ready <= _T_627 @[axi4_to_ahb.scala 296:19] - node _T_628 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 297:40] - node _T_629 = and(wrbuf_data_vld, _T_628) @[axi4_to_ahb.scala 297:38] - node _T_630 = eq(_T_629, UInt<1>("h00")) @[axi4_to_ahb.scala 297:21] - node _T_631 = and(_T_630, master_ready) @[axi4_to_ahb.scala 297:57] - io.axi.w.ready <= _T_631 @[axi4_to_ahb.scala 297:18] - node _T_632 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 298:34] - node _T_633 = eq(_T_632, UInt<1>("h00")) @[axi4_to_ahb.scala 298:22] - node _T_634 = and(_T_633, master_ready) @[axi4_to_ahb.scala 298:52] - io.axi.ar.ready <= _T_634 @[axi4_to_ahb.scala 298:19] - io.axi.r.bits.last <= UInt<1>("h01") @[axi4_to_ahb.scala 299:22] - node _T_635 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 301:71] - node _T_636 = mux(_T_635, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 301:55] - node _T_637 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 301:91] - node _T_638 = and(_T_636, _T_637) @[axi4_to_ahb.scala 301:89] - reg _T_639 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 301:51] - _T_639 <= _T_638 @[axi4_to_ahb.scala 301:51] - wrbuf_vld <= _T_639 @[axi4_to_ahb.scala 301:21] - node _T_640 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 302:76] - node _T_641 = mux(_T_640, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 302:55] - node _T_642 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 302:102] - node _T_643 = and(_T_641, _T_642) @[axi4_to_ahb.scala 302:100] - reg _T_644 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 302:51] - _T_644 <= _T_643 @[axi4_to_ahb.scala 302:51] - wrbuf_data_vld <= _T_644 @[axi4_to_ahb.scala 302:21] - node _T_645 = bits(io.axi.aw.bits.id, 2, 0) @[axi4_to_ahb.scala 303:71] - node _T_646 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 303:105] - reg _T_647 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_646 : @[Reg.scala 28:19] - _T_647 <= _T_645 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - wrbuf_tag <= _T_647 @[axi4_to_ahb.scala 303:21] - node _T_648 = bits(io.axi.aw.bits.size, 2, 0) @[axi4_to_ahb.scala 304:73] - node _T_649 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 304:101] - reg _T_650 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_649 : @[Reg.scala 28:19] - _T_650 <= _T_648 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - wrbuf_size <= _T_650 @[axi4_to_ahb.scala 304:21] - node _T_651 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 305:61] - inst rvclkhdr_2 of rvclkhdr_861 @[lib.scala 368:23] - rvclkhdr_2.clock <= clock - rvclkhdr_2.reset <= reset - rvclkhdr_2.io.clk <= bus_clk @[lib.scala 370:18] - rvclkhdr_2.io.en <= _T_651 @[lib.scala 371:17] - rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_652 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_652 <= io.axi.aw.bits.addr @[lib.scala 374:16] - wrbuf_addr <= _T_652 @[axi4_to_ahb.scala 305:21] - node _T_653 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 306:65] - inst rvclkhdr_3 of rvclkhdr_862 @[lib.scala 368:23] - rvclkhdr_3.clock <= clock - rvclkhdr_3.reset <= reset - rvclkhdr_3.io.clk <= bus_clk @[lib.scala 370:18] - rvclkhdr_3.io.en <= _T_653 @[lib.scala 371:17] - rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_654 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_654 <= io.axi.w.bits.data @[lib.scala 374:16] - wrbuf_data <= _T_654 @[axi4_to_ahb.scala 306:21] - node _T_655 = bits(io.axi.w.bits.strb, 7, 0) @[axi4_to_ahb.scala 307:72] - node _T_656 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 307:105] - reg _T_657 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_656 : @[Reg.scala 28:19] - _T_657 <= _T_655 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - wrbuf_byteen <= _T_657 @[axi4_to_ahb.scala 307:21] - node _T_658 = bits(io.ahb.out.haddr, 31, 0) @[axi4_to_ahb.scala 308:71] - node _T_659 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 308:104] - reg _T_660 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_659 : @[Reg.scala 28:19] - _T_660 <= _T_658 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - last_bus_addr <= _T_660 @[axi4_to_ahb.scala 308:21] - node _T_661 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 309:89] - reg _T_662 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_661 : @[Reg.scala 28:19] - _T_662 <= buf_write_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_write <= _T_662 @[axi4_to_ahb.scala 309:21] - node _T_663 = bits(buf_tag_in, 2, 0) @[axi4_to_ahb.scala 310:64] - node _T_664 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 310:99] - reg _T_665 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_664 : @[Reg.scala 28:19] - _T_665 <= _T_663 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_tag <= _T_665 @[axi4_to_ahb.scala 310:21] - node _T_666 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 311:42] - node _T_667 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 311:61] - node _T_668 = bits(_T_667, 0, 0) @[axi4_to_ahb.scala 311:78] - inst rvclkhdr_4 of rvclkhdr_863 @[lib.scala 368:23] - rvclkhdr_4.clock <= clock - rvclkhdr_4.reset <= reset - rvclkhdr_4.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_4.io.en <= _T_668 @[lib.scala 371:17] - rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_669 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_669 <= _T_666 @[lib.scala 374:16] - buf_addr <= _T_669 @[axi4_to_ahb.scala 311:21] - node _T_670 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 312:65] - node _T_671 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 312:94] - reg _T_672 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_671 : @[Reg.scala 28:19] - _T_672 <= _T_670 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_size <= _T_672 @[axi4_to_ahb.scala 312:21] - node _T_673 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 313:91] - reg _T_674 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_673 : @[Reg.scala 28:19] - _T_674 <= buf_aligned_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_aligned <= _T_674 @[axi4_to_ahb.scala 313:21] - node _T_675 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 314:67] - node _T_676 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 314:96] - reg _T_677 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_676 : @[Reg.scala 28:19] - _T_677 <= _T_675 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_byteen <= _T_677 @[axi4_to_ahb.scala 314:21] - node _T_678 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 315:42] - node _T_679 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 315:66] - node _T_680 = bits(_T_679, 0, 0) @[axi4_to_ahb.scala 315:89] - inst rvclkhdr_5 of rvclkhdr_864 @[lib.scala 368:23] - rvclkhdr_5.clock <= clock - rvclkhdr_5.reset <= reset - rvclkhdr_5.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_5.io.en <= _T_680 @[lib.scala 371:17] - rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_681 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_681 <= _T_678 @[lib.scala 374:16] - buf_data <= _T_681 @[axi4_to_ahb.scala 315:21] - node _T_682 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 316:89] - reg _T_683 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_682 : @[Reg.scala 28:19] - _T_683 <= buf_write @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - slvbuf_write <= _T_683 @[axi4_to_ahb.scala 316:21] - node _T_684 = bits(buf_tag, 2, 0) @[axi4_to_ahb.scala 317:61] - node _T_685 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 317:99] - reg _T_686 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_685 : @[Reg.scala 28:19] - _T_686 <= _T_684 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - slvbuf_tag <= _T_686 @[axi4_to_ahb.scala 317:21] - node _T_687 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 318:99] - reg _T_688 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_687 : @[Reg.scala 28:19] - _T_688 <= slvbuf_error_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - slvbuf_error <= _T_688 @[axi4_to_ahb.scala 318:21] - node _T_689 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 319:72] - node _T_690 = mux(_T_689, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 319:56] - node _T_691 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 319:92] - node _T_692 = and(_T_690, _T_691) @[axi4_to_ahb.scala 319:90] - reg _T_693 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 319:52] - _T_693 <= _T_692 @[axi4_to_ahb.scala 319:52] - cmd_doneQ <= _T_693 @[axi4_to_ahb.scala 319:21] - node _T_694 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 320:71] - node _T_695 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 320:110] - reg _T_696 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_695 : @[Reg.scala 28:19] - _T_696 <= _T_694 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_cmd_byte_ptrQ <= _T_696 @[axi4_to_ahb.scala 320:21] - reg _T_697 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 321:52] - _T_697 <= io.ahb.in.hready @[axi4_to_ahb.scala 321:52] - ahb_hready_q <= _T_697 @[axi4_to_ahb.scala 321:21] - node _T_698 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 322:70] - reg _T_699 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 322:52] - _T_699 <= _T_698 @[axi4_to_ahb.scala 322:52] - ahb_htrans_q <= _T_699 @[axi4_to_ahb.scala 322:21] - reg _T_700 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 323:57] - _T_700 <= io.ahb.out.hwrite @[axi4_to_ahb.scala 323:57] - ahb_hwrite_q <= _T_700 @[axi4_to_ahb.scala 323:21] - reg _T_701 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 324:52] - _T_701 <= io.ahb.in.hresp @[axi4_to_ahb.scala 324:52] - ahb_hresp_q <= _T_701 @[axi4_to_ahb.scala 324:21] - node _T_702 = bits(io.ahb.in.hrdata, 63, 0) @[axi4_to_ahb.scala 325:74] - reg _T_703 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 325:57] - _T_703 <= _T_702 @[axi4_to_ahb.scala 325:57] - ahb_hrdata_q <= _T_703 @[axi4_to_ahb.scala 325:21] - node _T_704 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 327:43] - node _T_705 = or(_T_704, io.clk_override) @[axi4_to_ahb.scala 327:58] - node _T_706 = and(io.bus_clk_en, _T_705) @[axi4_to_ahb.scala 327:30] - buf_clken <= _T_706 @[axi4_to_ahb.scala 327:13] - node _T_707 = bits(io.ahb.out.htrans, 1, 1) @[axi4_to_ahb.scala 328:76] - node _T_708 = and(io.ahb.in.hready, _T_707) @[axi4_to_ahb.scala 328:57] - node _T_709 = or(_T_708, io.clk_override) @[axi4_to_ahb.scala 328:81] - node _T_710 = and(io.bus_clk_en, _T_709) @[axi4_to_ahb.scala 328:36] - ahbm_addr_clken <= _T_710 @[axi4_to_ahb.scala 328:19] - node _T_711 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 329:50] - node _T_712 = or(_T_711, io.clk_override) @[axi4_to_ahb.scala 329:60] - node _T_713 = and(io.bus_clk_en, _T_712) @[axi4_to_ahb.scala 329:36] - ahbm_data_clken <= _T_713 @[axi4_to_ahb.scala 329:19] - inst rvclkhdr_6 of rvclkhdr_865 @[lib.scala 343:22] - rvclkhdr_6.clock <= clock - rvclkhdr_6.reset <= reset - rvclkhdr_6.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_6.io.en <= buf_clken @[lib.scala 345:16] - rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 332:12] - inst rvclkhdr_7 of rvclkhdr_866 @[lib.scala 343:22] - rvclkhdr_7.clock <= clock - rvclkhdr_7.reset <= reset - rvclkhdr_7.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_7.io.en <= io.bus_clk_en @[lib.scala 345:16] - rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 333:12] - inst rvclkhdr_8 of rvclkhdr_867 @[lib.scala 343:22] - rvclkhdr_8.clock <= clock - rvclkhdr_8.reset <= reset - rvclkhdr_8.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_8.io.en <= ahbm_addr_clken @[lib.scala 345:16] - rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 334:17] - inst rvclkhdr_9 of rvclkhdr_868 @[lib.scala 343:22] - rvclkhdr_9.clock <= clock - rvclkhdr_9.reset <= reset - rvclkhdr_9.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_9.io.en <= ahbm_data_clken @[lib.scala 345:16] - rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 335:17] - - extmodule gated_latch_869 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_869 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_869 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_870 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_870 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_870 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_871 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_871 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_871 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_872 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_872 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_872 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_873 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_873 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_873 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_874 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_874 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_874 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_875 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_875 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_875 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_876 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_876 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_876 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_877 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_877 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_877 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_878 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_878 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_878 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - module axi4_to_ahb_2 : - input clock : Clock - input reset : AsyncReset - output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ahb : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}} - - wire buf_rst : UInt<1> - buf_rst <= UInt<1>("h00") - buf_rst <= UInt<1>("h00") @[axi4_to_ahb.scala 21:11] - io.ahb.out.htrans <= UInt<1>("h00") @[axi4_to_ahb.scala 22:21] - wire buf_state_en : UInt<1> - buf_state_en <= UInt<1>("h00") - wire ahbm_clk : Clock @[axi4_to_ahb.scala 24:22] - wire ahbm_addr_clk : Clock @[axi4_to_ahb.scala 25:27] - wire ahbm_data_clk : Clock @[axi4_to_ahb.scala 26:27] - wire buf_state : UInt<3> - buf_state <= UInt<3>("h00") - wire buf_nxtstate : UInt<3> - buf_nxtstate <= UInt<3>("h00") - node _T = bits(buf_state_en, 0, 0) @[axi4_to_ahb.scala 30:70] - node _T_1 = mux(_T, buf_nxtstate, buf_state) @[axi4_to_ahb.scala 30:50] - node _T_2 = eq(buf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 30:108] - node _T_3 = bits(_T_2, 0, 0) @[Bitwise.scala 72:15] - node _T_4 = mux(_T_3, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_5 = and(_T_1, _T_4) @[axi4_to_ahb.scala 30:98] - reg _T_6 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 30:45] - _T_6 <= _T_5 @[axi4_to_ahb.scala 30:45] - buf_state <= _T_6 @[axi4_to_ahb.scala 30:13] - wire slave_valid : UInt<1> - slave_valid <= UInt<1>("h00") - wire slave_ready : UInt<1> - slave_ready <= UInt<1>("h00") - wire slave_tag : UInt<3> - slave_tag <= UInt<3>("h00") - wire slave_rdata : UInt<64> - slave_rdata <= UInt<64>("h00") - wire slave_opc : UInt<4> - slave_opc <= UInt<4>("h00") - wire wrbuf_en : UInt<1> - wrbuf_en <= UInt<1>("h00") - wire wrbuf_data_en : UInt<1> - wrbuf_data_en <= UInt<1>("h00") - wire wrbuf_cmd_sent : UInt<1> - wrbuf_cmd_sent <= UInt<1>("h00") - wire wrbuf_rst : UInt<1> - wrbuf_rst <= UInt<1>("h00") - wire wrbuf_vld : UInt<1> - wrbuf_vld <= UInt<1>("h00") - wire wrbuf_data_vld : UInt<1> - wrbuf_data_vld <= UInt<1>("h00") - wire wrbuf_tag : UInt<3> - wrbuf_tag <= UInt<3>("h00") - wire wrbuf_size : UInt<3> - wrbuf_size <= UInt<3>("h00") - wire wrbuf_addr : UInt<32> - wrbuf_addr <= UInt<32>("h00") - wire wrbuf_data : UInt<64> - wrbuf_data <= UInt<64>("h00") - wire wrbuf_byteen : UInt<8> - wrbuf_byteen <= UInt<8>("h00") - wire bus_write_clk_en : UInt<1> - bus_write_clk_en <= UInt<1>("h00") - wire bus_clk : Clock @[axi4_to_ahb.scala 50:21] - wire bus_write_clk : Clock @[axi4_to_ahb.scala 51:27] - wire master_valid : UInt<1> - master_valid <= UInt<1>("h00") - wire master_ready : UInt<1> - master_ready <= UInt<1>("h00") - wire master_tag : UInt<3> - master_tag <= UInt<3>("h00") - wire master_addr : UInt<32> - master_addr <= UInt<32>("h00") - wire master_wdata : UInt<64> - master_wdata <= UInt<64>("h00") - wire master_size : UInt<3> - master_size <= UInt<3>("h00") - wire master_opc : UInt<3> - master_opc <= UInt<3>("h00") - wire master_byteen : UInt<8> - master_byteen <= UInt<8>("h00") - wire buf_addr : UInt<32> - buf_addr <= UInt<32>("h00") - wire buf_size : UInt<2> - buf_size <= UInt<2>("h00") - wire buf_write : UInt<1> - buf_write <= UInt<1>("h00") - wire buf_byteen : UInt<8> - buf_byteen <= UInt<8>("h00") - wire buf_aligned : UInt<1> - buf_aligned <= UInt<1>("h00") - wire buf_data : UInt<64> - buf_data <= UInt<64>("h00") - wire buf_tag : UInt<3> - buf_tag <= UInt<3>("h00") - wire buf_tag_in : UInt<3> - buf_tag_in <= UInt<3>("h00") - wire buf_addr_in : UInt<32> - buf_addr_in <= UInt<32>("h00") - wire buf_byteen_in : UInt<8> - buf_byteen_in <= UInt<8>("h00") - wire buf_data_in : UInt<64> - buf_data_in <= UInt<64>("h00") - wire buf_write_in : UInt<1> - buf_write_in <= UInt<1>("h00") - wire buf_aligned_in : UInt<1> - buf_aligned_in <= UInt<1>("h00") - wire buf_size_in : UInt<3> - buf_size_in <= UInt<3>("h00") - wire buf_wr_en : UInt<1> - buf_wr_en <= UInt<1>("h00") - wire buf_data_wr_en : UInt<1> - buf_data_wr_en <= UInt<1>("h00") - wire slvbuf_error_en : UInt<1> - slvbuf_error_en <= UInt<1>("h00") - wire wr_cmd_vld : UInt<1> - wr_cmd_vld <= UInt<1>("h00") - wire cmd_done_rst : UInt<1> - cmd_done_rst <= UInt<1>("h00") - wire cmd_done : UInt<1> - cmd_done <= UInt<1>("h00") - wire cmd_doneQ : UInt<1> - cmd_doneQ <= UInt<1>("h00") - wire trxn_done : UInt<1> - trxn_done <= UInt<1>("h00") - wire buf_cmd_byte_ptr : UInt<3> - buf_cmd_byte_ptr <= UInt<3>("h00") - wire buf_cmd_byte_ptrQ : UInt<3> - buf_cmd_byte_ptrQ <= UInt<3>("h00") - wire buf_cmd_nxtbyte_ptr : UInt<3> - buf_cmd_nxtbyte_ptr <= UInt<3>("h00") - wire buf_cmd_byte_ptr_en : UInt<1> - buf_cmd_byte_ptr_en <= UInt<1>("h00") - wire found : UInt<1> - found <= UInt<1>("h00") - wire slave_valid_pre : UInt<1> - slave_valid_pre <= UInt<1>("h00") - wire ahb_hready_q : UInt<1> - ahb_hready_q <= UInt<1>("h00") - wire ahb_hresp_q : UInt<1> - ahb_hresp_q <= UInt<1>("h00") - wire ahb_htrans_q : UInt<2> - ahb_htrans_q <= UInt<2>("h00") - wire ahb_hwrite_q : UInt<1> - ahb_hwrite_q <= UInt<1>("h00") - wire ahb_hrdata_q : UInt<64> - ahb_hrdata_q <= UInt<64>("h00") - wire slvbuf_write : UInt<1> - slvbuf_write <= UInt<1>("h00") - wire slvbuf_error : UInt<1> - slvbuf_error <= UInt<1>("h00") - wire slvbuf_tag : UInt<3> - slvbuf_tag <= UInt<3>("h00") - wire slvbuf_error_in : UInt<1> - slvbuf_error_in <= UInt<1>("h00") - wire slvbuf_wr_en : UInt<1> - slvbuf_wr_en <= UInt<1>("h00") - wire bypass_en : UInt<1> - bypass_en <= UInt<1>("h00") - wire rd_bypass_idle : UInt<1> - rd_bypass_idle <= UInt<1>("h00") - wire last_addr_en : UInt<1> - last_addr_en <= UInt<1>("h00") - wire last_bus_addr : UInt<32> - last_bus_addr <= UInt<32>("h00") - wire buf_clken : UInt<1> - buf_clken <= UInt<1>("h00") - wire slvbuf_clken : UInt<1> - slvbuf_clken <= UInt<1>("h00") - wire ahbm_addr_clken : UInt<1> - ahbm_addr_clken <= UInt<1>("h00") - wire ahbm_data_clken : UInt<1> - ahbm_data_clken <= UInt<1>("h00") - wire buf_clk : Clock @[axi4_to_ahb.scala 118:21] - node _T_7 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 139:27] - wr_cmd_vld <= _T_7 @[axi4_to_ahb.scala 139:14] - node _T_8 = or(wr_cmd_vld, io.axi.ar.valid) @[axi4_to_ahb.scala 140:30] - master_valid <= _T_8 @[axi4_to_ahb.scala 140:16] - node _T_9 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 141:38] - node _T_10 = bits(wrbuf_tag, 2, 0) @[axi4_to_ahb.scala 141:51] - node _T_11 = bits(io.axi.ar.bits.id, 2, 0) @[axi4_to_ahb.scala 141:82] - node _T_12 = mux(_T_9, _T_10, _T_11) @[axi4_to_ahb.scala 141:20] - master_tag <= _T_12 @[axi4_to_ahb.scala 141:14] - node _T_13 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 142:38] - node _T_14 = mux(_T_13, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 142:20] - master_opc <= _T_14 @[axi4_to_ahb.scala 142:14] - node _T_15 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 143:39] - node _T_16 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 143:53] - node _T_17 = bits(io.axi.ar.bits.addr, 31, 0) @[axi4_to_ahb.scala 143:81] - node _T_18 = mux(_T_15, _T_16, _T_17) @[axi4_to_ahb.scala 143:21] - master_addr <= _T_18 @[axi4_to_ahb.scala 143:15] - node _T_19 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 144:39] - node _T_20 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 144:53] - node _T_21 = bits(io.axi.ar.bits.size, 2, 0) @[axi4_to_ahb.scala 144:80] - node _T_22 = mux(_T_19, _T_20, _T_21) @[axi4_to_ahb.scala 144:21] - master_size <= _T_22 @[axi4_to_ahb.scala 144:15] - node _T_23 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 145:32] - master_byteen <= _T_23 @[axi4_to_ahb.scala 145:17] - node _T_24 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 146:29] - master_wdata <= _T_24 @[axi4_to_ahb.scala 146:16] - node _T_25 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 149:33] - node _T_26 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 149:58] - node _T_27 = and(_T_25, _T_26) @[axi4_to_ahb.scala 149:47] - io.axi.b.valid <= _T_27 @[axi4_to_ahb.scala 149:18] - node _T_28 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 150:38] - node _T_29 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 150:65] - node _T_30 = mux(_T_29, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 150:55] - node _T_31 = mux(_T_28, UInt<2>("h02"), _T_30) @[axi4_to_ahb.scala 150:28] - io.axi.b.bits.resp <= _T_31 @[axi4_to_ahb.scala 150:22] - node _T_32 = bits(slave_tag, 2, 0) @[axi4_to_ahb.scala 151:32] - io.axi.b.bits.id <= _T_32 @[axi4_to_ahb.scala 151:20] - node _T_33 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 153:33] - node _T_34 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 153:59] - node _T_35 = eq(_T_34, UInt<1>("h00")) @[axi4_to_ahb.scala 153:66] - node _T_36 = and(_T_33, _T_35) @[axi4_to_ahb.scala 153:47] - io.axi.r.valid <= _T_36 @[axi4_to_ahb.scala 153:18] - node _T_37 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 154:38] - node _T_38 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 154:65] - node _T_39 = mux(_T_38, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 154:55] - node _T_40 = mux(_T_37, UInt<2>("h02"), _T_39) @[axi4_to_ahb.scala 154:28] - io.axi.r.bits.resp <= _T_40 @[axi4_to_ahb.scala 154:22] - node _T_41 = bits(slave_tag, 2, 0) @[axi4_to_ahb.scala 155:32] - io.axi.r.bits.id <= _T_41 @[axi4_to_ahb.scala 155:20] - node _T_42 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 156:36] - io.axi.r.bits.data <= _T_42 @[axi4_to_ahb.scala 156:22] - node _T_43 = and(io.axi.b.ready, io.axi.r.ready) @[axi4_to_ahb.scala 157:33] - slave_ready <= _T_43 @[axi4_to_ahb.scala 157:15] - node _T_44 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 160:57] - node _T_45 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 160:94] - node _T_46 = or(_T_44, _T_45) @[axi4_to_ahb.scala 160:76] - node _T_47 = and(io.bus_clk_en, _T_46) @[axi4_to_ahb.scala 160:37] - bus_write_clk_en <= _T_47 @[axi4_to_ahb.scala 160:20] - inst rvclkhdr of rvclkhdr_869 @[lib.scala 343:22] - rvclkhdr.clock <= clock - rvclkhdr.reset <= reset - rvclkhdr.io.clk <= clock @[lib.scala 344:17] - rvclkhdr.io.en <= io.bus_clk_en @[lib.scala 345:16] - rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - bus_clk <= rvclkhdr.io.l1clk @[axi4_to_ahb.scala 162:11] - node _T_48 = bits(bus_write_clk_en, 0, 0) @[axi4_to_ahb.scala 163:59] - inst rvclkhdr_1 of rvclkhdr_870 @[lib.scala 343:22] - rvclkhdr_1.clock <= clock - rvclkhdr_1.reset <= reset - rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_1.io.en <= _T_48 @[lib.scala 345:16] - rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - bus_write_clk <= rvclkhdr_1.io.l1clk @[axi4_to_ahb.scala 163:17] - node _T_49 = eq(UInt<3>("h00"), buf_state) @[Conditional.scala 37:30] - when _T_49 : @[Conditional.scala 40:58] - master_ready <= UInt<1>("h01") @[axi4_to_ahb.scala 167:20] - node _T_50 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 168:34] - node _T_51 = eq(_T_50, UInt<1>("h01")) @[axi4_to_ahb.scala 168:41] - buf_write_in <= _T_51 @[axi4_to_ahb.scala 168:20] - node _T_52 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 169:46] - node _T_53 = mux(_T_52, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 169:26] - buf_nxtstate <= _T_53 @[axi4_to_ahb.scala 169:20] - node _T_54 = and(master_valid, UInt<1>("h01")) @[axi4_to_ahb.scala 170:36] - buf_state_en <= _T_54 @[axi4_to_ahb.scala 170:20] - buf_wr_en <= buf_state_en @[axi4_to_ahb.scala 171:17] - node _T_55 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 172:54] - node _T_56 = and(buf_state_en, _T_55) @[axi4_to_ahb.scala 172:38] - buf_data_wr_en <= _T_56 @[axi4_to_ahb.scala 172:22] - buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 173:27] - node _T_57 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 175:50] - node _T_58 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 175:94] - node _T_59 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_60 = tail(_T_59, 1) @[axi4_to_ahb.scala 135:52] - node _T_61 = mux(UInt<1>("h00"), _T_60, UInt<3>("h00")) @[axi4_to_ahb.scala 135:24] - node _T_62 = bits(_T_58, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_63 = geq(UInt<1>("h00"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_64 = and(_T_62, _T_63) @[axi4_to_ahb.scala 136:48] - node _T_65 = bits(_T_58, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_66 = geq(UInt<1>("h01"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_67 = and(_T_65, _T_66) @[axi4_to_ahb.scala 136:48] - node _T_68 = bits(_T_58, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_69 = geq(UInt<2>("h02"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_70 = and(_T_68, _T_69) @[axi4_to_ahb.scala 136:48] - node _T_71 = bits(_T_58, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_72 = geq(UInt<2>("h03"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_73 = and(_T_71, _T_72) @[axi4_to_ahb.scala 136:48] - node _T_74 = bits(_T_58, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_75 = geq(UInt<3>("h04"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_76 = and(_T_74, _T_75) @[axi4_to_ahb.scala 136:48] - node _T_77 = bits(_T_58, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_78 = geq(UInt<3>("h05"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_79 = and(_T_77, _T_78) @[axi4_to_ahb.scala 136:48] - node _T_80 = bits(_T_58, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_81 = geq(UInt<3>("h06"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_82 = and(_T_80, _T_81) @[axi4_to_ahb.scala 136:48] - node _T_83 = bits(_T_58, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_84 = geq(UInt<3>("h07"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_85 = and(_T_83, _T_84) @[axi4_to_ahb.scala 136:48] - node _T_86 = mux(_T_85, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_87 = mux(_T_82, UInt<3>("h06"), _T_86) @[Mux.scala 98:16] - node _T_88 = mux(_T_79, UInt<3>("h05"), _T_87) @[Mux.scala 98:16] - node _T_89 = mux(_T_76, UInt<3>("h04"), _T_88) @[Mux.scala 98:16] - node _T_90 = mux(_T_73, UInt<2>("h03"), _T_89) @[Mux.scala 98:16] - node _T_91 = mux(_T_70, UInt<2>("h02"), _T_90) @[Mux.scala 98:16] - node _T_92 = mux(_T_67, UInt<1>("h01"), _T_91) @[Mux.scala 98:16] - node _T_93 = mux(_T_64, UInt<1>("h00"), _T_92) @[Mux.scala 98:16] - node _T_94 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 175:124] - node _T_95 = mux(_T_57, _T_93, _T_94) @[axi4_to_ahb.scala 175:30] - buf_cmd_byte_ptr <= _T_95 @[axi4_to_ahb.scala 175:24] - bypass_en <= buf_state_en @[axi4_to_ahb.scala 176:17] - node _T_96 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 177:51] - node _T_97 = and(bypass_en, _T_96) @[axi4_to_ahb.scala 177:35] - rd_bypass_idle <= _T_97 @[axi4_to_ahb.scala 177:22] - node _T_98 = bits(bypass_en, 0, 0) @[Bitwise.scala 72:15] - node _T_99 = mux(_T_98, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_100 = and(_T_99, UInt<2>("h02")) @[axi4_to_ahb.scala 178:49] - io.ahb.out.htrans <= _T_100 @[axi4_to_ahb.scala 178:25] - skip @[Conditional.scala 40:58] - else : @[Conditional.scala 39:67] - node _T_101 = eq(UInt<3>("h01"), buf_state) @[Conditional.scala 37:30] - when _T_101 : @[Conditional.scala 39:67] - node _T_102 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 182:54] - node _T_103 = eq(_T_102, UInt<1>("h00")) @[axi4_to_ahb.scala 182:61] - node _T_104 = and(master_valid, _T_103) @[axi4_to_ahb.scala 182:41] - node _T_105 = bits(_T_104, 0, 0) @[axi4_to_ahb.scala 182:82] - node _T_106 = mux(_T_105, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 182:26] - buf_nxtstate <= _T_106 @[axi4_to_ahb.scala 182:20] - node _T_107 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 183:51] - node _T_108 = neq(_T_107, UInt<1>("h00")) @[axi4_to_ahb.scala 183:58] - node _T_109 = and(ahb_hready_q, _T_108) @[axi4_to_ahb.scala 183:36] - node _T_110 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 183:72] - node _T_111 = and(_T_109, _T_110) @[axi4_to_ahb.scala 183:70] - buf_state_en <= _T_111 @[axi4_to_ahb.scala 183:20] - node _T_112 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 184:34] - node _T_113 = and(buf_state_en, _T_112) @[axi4_to_ahb.scala 184:32] - cmd_done <= _T_113 @[axi4_to_ahb.scala 184:16] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 185:20] - node _T_114 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 186:52] - node _T_115 = neq(_T_114, UInt<1>("h00")) @[axi4_to_ahb.scala 186:59] - node _T_116 = and(ahb_hready_q, _T_115) @[axi4_to_ahb.scala 186:37] - node _T_117 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 186:73] - node _T_118 = and(_T_116, _T_117) @[axi4_to_ahb.scala 186:71] - node _T_119 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 186:122] - node _T_120 = eq(_T_119, UInt<1>("h00")) @[axi4_to_ahb.scala 186:129] - node _T_121 = and(master_valid, _T_120) @[axi4_to_ahb.scala 186:109] - node _T_122 = bits(_T_121, 0, 0) @[axi4_to_ahb.scala 186:150] - node _T_123 = mux(_T_122, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 186:94] - node _T_124 = eq(_T_123, UInt<3>("h06")) @[axi4_to_ahb.scala 186:174] - node _T_125 = and(_T_118, _T_124) @[axi4_to_ahb.scala 186:88] - master_ready <= _T_125 @[axi4_to_ahb.scala 186:20] - buf_wr_en <= master_ready @[axi4_to_ahb.scala 187:17] - node _T_126 = and(master_ready, master_valid) @[axi4_to_ahb.scala 188:33] - bypass_en <= _T_126 @[axi4_to_ahb.scala 188:17] - node _T_127 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 189:47] - node _T_128 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 189:62] - node _T_129 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 189:78] - node _T_130 = mux(_T_127, _T_128, _T_129) @[axi4_to_ahb.scala 189:30] - buf_cmd_byte_ptr <= _T_130 @[axi4_to_ahb.scala 189:24] - node _T_131 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 190:48] - node _T_132 = or(_T_131, bypass_en) @[axi4_to_ahb.scala 190:62] - node _T_133 = bits(_T_132, 0, 0) @[Bitwise.scala 72:15] - node _T_134 = mux(_T_133, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_135 = and(UInt<2>("h02"), _T_134) @[axi4_to_ahb.scala 190:36] - io.ahb.out.htrans <= _T_135 @[axi4_to_ahb.scala 190:25] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_136 = eq(UInt<3>("h06"), buf_state) @[Conditional.scala 37:30] - when _T_136 : @[Conditional.scala 39:67] - node _T_137 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 194:39] - node _T_138 = and(ahb_hready_q, _T_137) @[axi4_to_ahb.scala 194:37] - node _T_139 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 194:82] - node _T_140 = eq(_T_139, UInt<1>("h01")) @[axi4_to_ahb.scala 194:89] - node _T_141 = and(master_valid, _T_140) @[axi4_to_ahb.scala 194:70] - node _T_142 = not(_T_141) @[axi4_to_ahb.scala 194:55] - node _T_143 = and(_T_138, _T_142) @[axi4_to_ahb.scala 194:53] - master_ready <= _T_143 @[axi4_to_ahb.scala 194:20] - node _T_144 = and(master_valid, master_ready) @[axi4_to_ahb.scala 195:34] - node _T_145 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 195:62] - node _T_146 = eq(_T_145, UInt<1>("h00")) @[axi4_to_ahb.scala 195:69] - node _T_147 = and(_T_144, _T_146) @[axi4_to_ahb.scala 195:49] - buf_wr_en <= _T_147 @[axi4_to_ahb.scala 195:17] - node _T_148 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 196:45] - node _T_149 = and(master_valid, master_ready) @[axi4_to_ahb.scala 196:82] - node _T_150 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 196:110] - node _T_151 = eq(_T_150, UInt<1>("h00")) @[axi4_to_ahb.scala 196:117] - node _T_152 = and(_T_149, _T_151) @[axi4_to_ahb.scala 196:97] - node _T_153 = bits(_T_152, 0, 0) @[axi4_to_ahb.scala 196:138] - node _T_154 = mux(_T_153, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 196:67] - node _T_155 = mux(_T_148, UInt<3>("h07"), _T_154) @[axi4_to_ahb.scala 196:26] - buf_nxtstate <= _T_155 @[axi4_to_ahb.scala 196:20] - node _T_156 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 197:37] - buf_state_en <= _T_156 @[axi4_to_ahb.scala 197:20] - buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 198:22] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 199:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 200:23] - node _T_157 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 201:41] - node _T_158 = and(buf_state_en, _T_157) @[axi4_to_ahb.scala 201:39] - slave_valid_pre <= _T_158 @[axi4_to_ahb.scala 201:23] - node _T_159 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 202:34] - node _T_160 = and(buf_state_en, _T_159) @[axi4_to_ahb.scala 202:32] - cmd_done <= _T_160 @[axi4_to_ahb.scala 202:16] - node _T_161 = and(master_ready, master_valid) @[axi4_to_ahb.scala 203:33] - node _T_162 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 203:64] - node _T_163 = and(_T_161, _T_162) @[axi4_to_ahb.scala 203:48] - node _T_164 = and(_T_163, buf_state_en) @[axi4_to_ahb.scala 203:79] - bypass_en <= _T_164 @[axi4_to_ahb.scala 203:17] - node _T_165 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 204:47] - node _T_166 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 204:62] - node _T_167 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 204:78] - node _T_168 = mux(_T_165, _T_166, _T_167) @[axi4_to_ahb.scala 204:30] - buf_cmd_byte_ptr <= _T_168 @[axi4_to_ahb.scala 204:24] - node _T_169 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 205:63] - node _T_170 = and(_T_169, buf_state_en) @[axi4_to_ahb.scala 205:78] - node _T_171 = eq(_T_170, UInt<1>("h00")) @[axi4_to_ahb.scala 205:47] - node _T_172 = bits(_T_171, 0, 0) @[Bitwise.scala 72:15] - node _T_173 = mux(_T_172, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_174 = and(UInt<2>("h02"), _T_173) @[axi4_to_ahb.scala 205:36] - io.ahb.out.htrans <= _T_174 @[axi4_to_ahb.scala 205:25] - slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 206:20] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_175 = eq(UInt<3>("h07"), buf_state) @[Conditional.scala 37:30] - when _T_175 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 210:20] - node _T_176 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 211:51] - node _T_177 = neq(_T_176, UInt<1>("h00")) @[axi4_to_ahb.scala 211:58] - node _T_178 = and(ahb_hready_q, _T_177) @[axi4_to_ahb.scala 211:36] - node _T_179 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 211:72] - node _T_180 = and(_T_178, _T_179) @[axi4_to_ahb.scala 211:70] - buf_state_en <= _T_180 @[axi4_to_ahb.scala 211:20] - slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 212:23] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 213:20] - node _T_181 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 214:35] - buf_cmd_byte_ptr <= _T_181 @[axi4_to_ahb.scala 214:24] - node _T_182 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 215:51] - node _T_183 = bits(_T_182, 0, 0) @[Bitwise.scala 72:15] - node _T_184 = mux(_T_183, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_185 = and(UInt<2>("h02"), _T_184) @[axi4_to_ahb.scala 215:41] - io.ahb.out.htrans <= _T_185 @[axi4_to_ahb.scala 215:25] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_186 = eq(UInt<3>("h03"), buf_state) @[Conditional.scala 37:30] - when _T_186 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 219:20] - node _T_187 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 220:37] - buf_state_en <= _T_187 @[axi4_to_ahb.scala 220:20] - buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 221:22] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 222:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 223:23] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 224:20] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_188 = eq(UInt<3>("h02"), buf_state) @[Conditional.scala 37:30] - when _T_188 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 228:20] - node _T_189 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 229:33] - node _T_190 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 229:63] - node _T_191 = neq(_T_190, UInt<1>("h00")) @[axi4_to_ahb.scala 229:70] - node _T_192 = and(_T_189, _T_191) @[axi4_to_ahb.scala 229:48] - trxn_done <= _T_192 @[axi4_to_ahb.scala 229:17] - buf_state_en <= trxn_done @[axi4_to_ahb.scala 230:20] - buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 231:27] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 232:20] - node _T_193 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 233:47] - node _T_194 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 233:85] - node _T_195 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 233:103] - node _T_196 = add(_T_194, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_197 = tail(_T_196, 1) @[axi4_to_ahb.scala 135:52] - node _T_198 = mux(UInt<1>("h01"), _T_197, _T_194) @[axi4_to_ahb.scala 135:24] - node _T_199 = bits(_T_195, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_200 = geq(UInt<1>("h00"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_201 = and(_T_199, _T_200) @[axi4_to_ahb.scala 136:48] - node _T_202 = bits(_T_195, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_203 = geq(UInt<1>("h01"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_204 = and(_T_202, _T_203) @[axi4_to_ahb.scala 136:48] - node _T_205 = bits(_T_195, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_206 = geq(UInt<2>("h02"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_207 = and(_T_205, _T_206) @[axi4_to_ahb.scala 136:48] - node _T_208 = bits(_T_195, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_209 = geq(UInt<2>("h03"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_210 = and(_T_208, _T_209) @[axi4_to_ahb.scala 136:48] - node _T_211 = bits(_T_195, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_212 = geq(UInt<3>("h04"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_213 = and(_T_211, _T_212) @[axi4_to_ahb.scala 136:48] - node _T_214 = bits(_T_195, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_215 = geq(UInt<3>("h05"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_216 = and(_T_214, _T_215) @[axi4_to_ahb.scala 136:48] - node _T_217 = bits(_T_195, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_218 = geq(UInt<3>("h06"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_219 = and(_T_217, _T_218) @[axi4_to_ahb.scala 136:48] - node _T_220 = bits(_T_195, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_221 = geq(UInt<3>("h07"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_222 = and(_T_220, _T_221) @[axi4_to_ahb.scala 136:48] - node _T_223 = mux(_T_222, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_224 = mux(_T_219, UInt<3>("h06"), _T_223) @[Mux.scala 98:16] - node _T_225 = mux(_T_216, UInt<3>("h05"), _T_224) @[Mux.scala 98:16] - node _T_226 = mux(_T_213, UInt<3>("h04"), _T_225) @[Mux.scala 98:16] - node _T_227 = mux(_T_210, UInt<2>("h03"), _T_226) @[Mux.scala 98:16] - node _T_228 = mux(_T_207, UInt<2>("h02"), _T_227) @[Mux.scala 98:16] - node _T_229 = mux(_T_204, UInt<1>("h01"), _T_228) @[Mux.scala 98:16] - node _T_230 = mux(_T_201, UInt<1>("h00"), _T_229) @[Mux.scala 98:16] - node _T_231 = mux(_T_193, _T_230, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 233:30] - buf_cmd_byte_ptr <= _T_231 @[axi4_to_ahb.scala 233:24] - node _T_232 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 234:65] - node _T_233 = or(buf_aligned, _T_232) @[axi4_to_ahb.scala 234:44] - node _T_234 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 234:127] - node _T_235 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 234:145] - node _T_236 = add(_T_234, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_237 = tail(_T_236, 1) @[axi4_to_ahb.scala 135:52] - node _T_238 = mux(UInt<1>("h01"), _T_237, _T_234) @[axi4_to_ahb.scala 135:24] - node _T_239 = bits(_T_235, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_240 = geq(UInt<1>("h00"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_241 = and(_T_239, _T_240) @[axi4_to_ahb.scala 136:48] - node _T_242 = bits(_T_235, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_243 = geq(UInt<1>("h01"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_244 = and(_T_242, _T_243) @[axi4_to_ahb.scala 136:48] - node _T_245 = bits(_T_235, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_246 = geq(UInt<2>("h02"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_247 = and(_T_245, _T_246) @[axi4_to_ahb.scala 136:48] - node _T_248 = bits(_T_235, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_249 = geq(UInt<2>("h03"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_250 = and(_T_248, _T_249) @[axi4_to_ahb.scala 136:48] - node _T_251 = bits(_T_235, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_252 = geq(UInt<3>("h04"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_253 = and(_T_251, _T_252) @[axi4_to_ahb.scala 136:48] - node _T_254 = bits(_T_235, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_255 = geq(UInt<3>("h05"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_256 = and(_T_254, _T_255) @[axi4_to_ahb.scala 136:48] - node _T_257 = bits(_T_235, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_258 = geq(UInt<3>("h06"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_259 = and(_T_257, _T_258) @[axi4_to_ahb.scala 136:48] - node _T_260 = bits(_T_235, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_261 = geq(UInt<3>("h07"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_262 = and(_T_260, _T_261) @[axi4_to_ahb.scala 136:48] - node _T_263 = mux(_T_262, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_264 = mux(_T_259, UInt<3>("h06"), _T_263) @[Mux.scala 98:16] - node _T_265 = mux(_T_256, UInt<3>("h05"), _T_264) @[Mux.scala 98:16] - node _T_266 = mux(_T_253, UInt<3>("h04"), _T_265) @[Mux.scala 98:16] - node _T_267 = mux(_T_250, UInt<2>("h03"), _T_266) @[Mux.scala 98:16] - node _T_268 = mux(_T_247, UInt<2>("h02"), _T_267) @[Mux.scala 98:16] - node _T_269 = mux(_T_244, UInt<1>("h01"), _T_268) @[Mux.scala 98:16] - node _T_270 = mux(_T_241, UInt<1>("h00"), _T_269) @[Mux.scala 98:16] - node _T_271 = dshr(buf_byteen, _T_270) @[axi4_to_ahb.scala 234:92] - node _T_272 = bits(_T_271, 0, 0) @[axi4_to_ahb.scala 234:92] - node _T_273 = eq(_T_272, UInt<1>("h00")) @[axi4_to_ahb.scala 234:163] - node _T_274 = or(_T_233, _T_273) @[axi4_to_ahb.scala 234:79] - node _T_275 = and(trxn_done, _T_274) @[axi4_to_ahb.scala 234:29] - cmd_done <= _T_275 @[axi4_to_ahb.scala 234:16] - node _T_276 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 235:47] - node _T_277 = eq(_T_276, UInt<1>("h00")) @[axi4_to_ahb.scala 235:36] - node _T_278 = bits(_T_277, 0, 0) @[Bitwise.scala 72:15] - node _T_279 = mux(_T_278, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_280 = and(_T_279, UInt<2>("h02")) @[axi4_to_ahb.scala 235:61] - io.ahb.out.htrans <= _T_280 @[axi4_to_ahb.scala 235:25] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_281 = eq(UInt<3>("h04"), buf_state) @[Conditional.scala 37:30] - when _T_281 : @[Conditional.scala 39:67] - node _T_282 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 239:34] - node _T_283 = or(_T_282, ahb_hresp_q) @[axi4_to_ahb.scala 239:50] - buf_state_en <= _T_283 @[axi4_to_ahb.scala 239:20] - node _T_284 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 240:38] - node _T_285 = and(buf_state_en, _T_284) @[axi4_to_ahb.scala 240:36] - node _T_286 = and(_T_285, slave_ready) @[axi4_to_ahb.scala 240:51] - master_ready <= _T_286 @[axi4_to_ahb.scala 240:20] - node _T_287 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 241:42] - node _T_288 = or(ahb_hresp_q, _T_287) @[axi4_to_ahb.scala 241:40] - node _T_289 = and(master_valid, master_valid) @[axi4_to_ahb.scala 241:80] - node _T_290 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 241:111] - node _T_291 = eq(_T_290, UInt<1>("h01")) @[axi4_to_ahb.scala 241:117] - node _T_292 = bits(_T_291, 0, 0) @[axi4_to_ahb.scala 241:132] - node _T_293 = mux(_T_292, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 241:99] - node _T_294 = mux(_T_289, _T_293, UInt<3>("h00")) @[axi4_to_ahb.scala 241:65] - node _T_295 = mux(_T_288, UInt<3>("h05"), _T_294) @[axi4_to_ahb.scala 241:26] - buf_nxtstate <= _T_295 @[axi4_to_ahb.scala 241:20] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 242:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 243:23] - node _T_296 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 244:33] - node _T_297 = eq(_T_296, UInt<1>("h01")) @[axi4_to_ahb.scala 244:39] - buf_write_in <= _T_297 @[axi4_to_ahb.scala 244:20] - node _T_298 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 245:50] - node _T_299 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 245:78] - node _T_300 = or(_T_298, _T_299) @[axi4_to_ahb.scala 245:62] - node _T_301 = and(buf_state_en, _T_300) @[axi4_to_ahb.scala 245:33] - buf_wr_en <= _T_301 @[axi4_to_ahb.scala 245:17] - buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 246:22] - node _T_302 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 247:65] - node _T_303 = neq(_T_302, UInt<1>("h00")) @[axi4_to_ahb.scala 247:71] - node _T_304 = and(ahb_hready_q, _T_303) @[axi4_to_ahb.scala 247:50] - node _T_305 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 248:29] - node _T_306 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 248:85] - node _T_307 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 248:101] - node _T_308 = add(_T_306, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_309 = tail(_T_308, 1) @[axi4_to_ahb.scala 135:52] - node _T_310 = mux(UInt<1>("h01"), _T_309, _T_306) @[axi4_to_ahb.scala 135:24] - node _T_311 = bits(_T_307, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_312 = geq(UInt<1>("h00"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_313 = and(_T_311, _T_312) @[axi4_to_ahb.scala 136:48] - node _T_314 = bits(_T_307, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_315 = geq(UInt<1>("h01"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_316 = and(_T_314, _T_315) @[axi4_to_ahb.scala 136:48] - node _T_317 = bits(_T_307, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_318 = geq(UInt<2>("h02"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_319 = and(_T_317, _T_318) @[axi4_to_ahb.scala 136:48] - node _T_320 = bits(_T_307, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_321 = geq(UInt<2>("h03"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_322 = and(_T_320, _T_321) @[axi4_to_ahb.scala 136:48] - node _T_323 = bits(_T_307, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_324 = geq(UInt<3>("h04"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_325 = and(_T_323, _T_324) @[axi4_to_ahb.scala 136:48] - node _T_326 = bits(_T_307, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_327 = geq(UInt<3>("h05"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_328 = and(_T_326, _T_327) @[axi4_to_ahb.scala 136:48] - node _T_329 = bits(_T_307, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_330 = geq(UInt<3>("h06"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_331 = and(_T_329, _T_330) @[axi4_to_ahb.scala 136:48] - node _T_332 = bits(_T_307, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_333 = geq(UInt<3>("h07"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_334 = and(_T_332, _T_333) @[axi4_to_ahb.scala 136:48] - node _T_335 = mux(_T_334, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_336 = mux(_T_331, UInt<3>("h06"), _T_335) @[Mux.scala 98:16] - node _T_337 = mux(_T_328, UInt<3>("h05"), _T_336) @[Mux.scala 98:16] - node _T_338 = mux(_T_325, UInt<3>("h04"), _T_337) @[Mux.scala 98:16] - node _T_339 = mux(_T_322, UInt<2>("h03"), _T_338) @[Mux.scala 98:16] - node _T_340 = mux(_T_319, UInt<2>("h02"), _T_339) @[Mux.scala 98:16] - node _T_341 = mux(_T_316, UInt<1>("h01"), _T_340) @[Mux.scala 98:16] - node _T_342 = mux(_T_313, UInt<1>("h00"), _T_341) @[Mux.scala 98:16] - node _T_343 = dshr(buf_byteen, _T_342) @[axi4_to_ahb.scala 248:51] - node _T_344 = bits(_T_343, 0, 0) @[axi4_to_ahb.scala 248:51] - node _T_345 = eq(_T_344, UInt<1>("h00")) @[axi4_to_ahb.scala 248:116] - node _T_346 = or(_T_305, _T_345) @[axi4_to_ahb.scala 248:38] - node _T_347 = and(_T_304, _T_346) @[axi4_to_ahb.scala 247:80] - node _T_348 = or(ahb_hresp_q, _T_347) @[axi4_to_ahb.scala 247:34] - cmd_done <= _T_348 @[axi4_to_ahb.scala 247:16] - node _T_349 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 249:33] - node _T_350 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 249:64] - node _T_351 = and(_T_349, _T_350) @[axi4_to_ahb.scala 249:48] - bypass_en <= _T_351 @[axi4_to_ahb.scala 249:17] - node _T_352 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 250:48] - node _T_353 = eq(_T_352, UInt<1>("h00")) @[axi4_to_ahb.scala 250:37] - node _T_354 = or(_T_353, bypass_en) @[axi4_to_ahb.scala 250:61] - node _T_355 = bits(_T_354, 0, 0) @[Bitwise.scala 72:15] - node _T_356 = mux(_T_355, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_357 = and(_T_356, UInt<2>("h02")) @[axi4_to_ahb.scala 250:75] - io.ahb.out.htrans <= _T_357 @[axi4_to_ahb.scala 250:25] - node _T_358 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 251:55] - node _T_359 = and(buf_state_en, _T_358) @[axi4_to_ahb.scala 251:39] - slave_valid_pre <= _T_359 @[axi4_to_ahb.scala 251:23] - node _T_360 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 252:33] - node _T_361 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 252:63] - node _T_362 = neq(_T_361, UInt<1>("h00")) @[axi4_to_ahb.scala 252:69] - node _T_363 = and(_T_360, _T_362) @[axi4_to_ahb.scala 252:48] - trxn_done <= _T_363 @[axi4_to_ahb.scala 252:17] - node _T_364 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 253:40] - buf_cmd_byte_ptr_en <= _T_364 @[axi4_to_ahb.scala 253:27] - node _T_365 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 254:79] - node _T_366 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_367 = tail(_T_366, 1) @[axi4_to_ahb.scala 135:52] - node _T_368 = mux(UInt<1>("h00"), _T_367, UInt<3>("h00")) @[axi4_to_ahb.scala 135:24] - node _T_369 = bits(_T_365, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_370 = geq(UInt<1>("h00"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_371 = and(_T_369, _T_370) @[axi4_to_ahb.scala 136:48] - node _T_372 = bits(_T_365, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_373 = geq(UInt<1>("h01"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_374 = and(_T_372, _T_373) @[axi4_to_ahb.scala 136:48] - node _T_375 = bits(_T_365, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_376 = geq(UInt<2>("h02"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_377 = and(_T_375, _T_376) @[axi4_to_ahb.scala 136:48] - node _T_378 = bits(_T_365, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_379 = geq(UInt<2>("h03"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_380 = and(_T_378, _T_379) @[axi4_to_ahb.scala 136:48] - node _T_381 = bits(_T_365, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_382 = geq(UInt<3>("h04"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_383 = and(_T_381, _T_382) @[axi4_to_ahb.scala 136:48] - node _T_384 = bits(_T_365, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_385 = geq(UInt<3>("h05"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_386 = and(_T_384, _T_385) @[axi4_to_ahb.scala 136:48] - node _T_387 = bits(_T_365, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_388 = geq(UInt<3>("h06"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_389 = and(_T_387, _T_388) @[axi4_to_ahb.scala 136:48] - node _T_390 = bits(_T_365, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_391 = geq(UInt<3>("h07"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_392 = and(_T_390, _T_391) @[axi4_to_ahb.scala 136:48] - node _T_393 = mux(_T_392, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_394 = mux(_T_389, UInt<3>("h06"), _T_393) @[Mux.scala 98:16] - node _T_395 = mux(_T_386, UInt<3>("h05"), _T_394) @[Mux.scala 98:16] - node _T_396 = mux(_T_383, UInt<3>("h04"), _T_395) @[Mux.scala 98:16] - node _T_397 = mux(_T_380, UInt<2>("h03"), _T_396) @[Mux.scala 98:16] - node _T_398 = mux(_T_377, UInt<2>("h02"), _T_397) @[Mux.scala 98:16] - node _T_399 = mux(_T_374, UInt<1>("h01"), _T_398) @[Mux.scala 98:16] - node _T_400 = mux(_T_371, UInt<1>("h00"), _T_399) @[Mux.scala 98:16] - node _T_401 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 254:141] - node _T_402 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 254:157] - node _T_403 = add(_T_401, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_404 = tail(_T_403, 1) @[axi4_to_ahb.scala 135:52] - node _T_405 = mux(UInt<1>("h01"), _T_404, _T_401) @[axi4_to_ahb.scala 135:24] - node _T_406 = bits(_T_402, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_407 = geq(UInt<1>("h00"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_408 = and(_T_406, _T_407) @[axi4_to_ahb.scala 136:48] - node _T_409 = bits(_T_402, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_410 = geq(UInt<1>("h01"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_411 = and(_T_409, _T_410) @[axi4_to_ahb.scala 136:48] - node _T_412 = bits(_T_402, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_413 = geq(UInt<2>("h02"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_414 = and(_T_412, _T_413) @[axi4_to_ahb.scala 136:48] - node _T_415 = bits(_T_402, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_416 = geq(UInt<2>("h03"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_417 = and(_T_415, _T_416) @[axi4_to_ahb.scala 136:48] - node _T_418 = bits(_T_402, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_419 = geq(UInt<3>("h04"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_420 = and(_T_418, _T_419) @[axi4_to_ahb.scala 136:48] - node _T_421 = bits(_T_402, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_422 = geq(UInt<3>("h05"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_423 = and(_T_421, _T_422) @[axi4_to_ahb.scala 136:48] - node _T_424 = bits(_T_402, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_425 = geq(UInt<3>("h06"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_426 = and(_T_424, _T_425) @[axi4_to_ahb.scala 136:48] - node _T_427 = bits(_T_402, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_428 = geq(UInt<3>("h07"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_429 = and(_T_427, _T_428) @[axi4_to_ahb.scala 136:48] - node _T_430 = mux(_T_429, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_431 = mux(_T_426, UInt<3>("h06"), _T_430) @[Mux.scala 98:16] - node _T_432 = mux(_T_423, UInt<3>("h05"), _T_431) @[Mux.scala 98:16] - node _T_433 = mux(_T_420, UInt<3>("h04"), _T_432) @[Mux.scala 98:16] - node _T_434 = mux(_T_417, UInt<2>("h03"), _T_433) @[Mux.scala 98:16] - node _T_435 = mux(_T_414, UInt<2>("h02"), _T_434) @[Mux.scala 98:16] - node _T_436 = mux(_T_411, UInt<1>("h01"), _T_435) @[Mux.scala 98:16] - node _T_437 = mux(_T_408, UInt<1>("h00"), _T_436) @[Mux.scala 98:16] - node _T_438 = mux(trxn_done, _T_437, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 254:97] - node _T_439 = mux(bypass_en, _T_400, _T_438) @[axi4_to_ahb.scala 254:30] - buf_cmd_byte_ptr <= _T_439 @[axi4_to_ahb.scala 254:24] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_440 = eq(UInt<3>("h05"), buf_state) @[Conditional.scala 37:30] - when _T_440 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 257:20] - buf_state_en <= slave_ready @[axi4_to_ahb.scala 258:20] - slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 259:23] - slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 260:23] - skip @[Conditional.scala 39:67] - cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 264:16] - node _T_441 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 265:33] - node _T_442 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 265:73] - node _T_443 = eq(_T_442, UInt<1>("h01")) @[axi4_to_ahb.scala 265:80] - node _T_444 = and(buf_aligned_in, _T_443) @[axi4_to_ahb.scala 265:60] - node _T_445 = bits(_T_444, 0, 0) @[axi4_to_ahb.scala 265:100] - node _T_446 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 265:132] - node _T_447 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:50] - node _T_448 = eq(_T_447, UInt<8>("h0ff")) @[axi4_to_ahb.scala 127:57] - node _T_449 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:81] - node _T_450 = eq(_T_449, UInt<8>("h0f")) @[axi4_to_ahb.scala 127:88] - node _T_451 = or(_T_448, _T_450) @[axi4_to_ahb.scala 127:70] - node _T_452 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:117] - node _T_453 = eq(_T_452, UInt<8>("h03")) @[axi4_to_ahb.scala 127:124] - node _T_454 = or(_T_451, _T_453) @[axi4_to_ahb.scala 127:106] - node _T_455 = bits(_T_454, 0, 0) @[Bitwise.scala 72:15] - node _T_456 = mux(_T_455, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_457 = and(UInt<3>("h00"), _T_456) @[axi4_to_ahb.scala 127:29] - node _T_458 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 128:35] - node _T_459 = eq(_T_458, UInt<8>("h0c")) @[axi4_to_ahb.scala 128:42] - node _T_460 = bits(_T_459, 0, 0) @[Bitwise.scala 72:15] - node _T_461 = mux(_T_460, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_462 = and(UInt<2>("h02"), _T_461) @[axi4_to_ahb.scala 128:15] - node _T_463 = or(_T_457, _T_462) @[axi4_to_ahb.scala 127:146] - node _T_464 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 129:36] - node _T_465 = eq(_T_464, UInt<8>("h0f0")) @[axi4_to_ahb.scala 129:43] - node _T_466 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 129:67] - node _T_467 = eq(_T_466, UInt<8>("h03")) @[axi4_to_ahb.scala 129:74] - node _T_468 = or(_T_465, _T_467) @[axi4_to_ahb.scala 129:56] - node _T_469 = bits(_T_468, 0, 0) @[Bitwise.scala 72:15] - node _T_470 = mux(_T_469, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_471 = and(UInt<3>("h04"), _T_470) @[axi4_to_ahb.scala 129:15] - node _T_472 = or(_T_463, _T_471) @[axi4_to_ahb.scala 128:63] - node _T_473 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 130:35] - node _T_474 = eq(_T_473, UInt<8>("h0c0")) @[axi4_to_ahb.scala 130:42] - node _T_475 = bits(_T_474, 0, 0) @[Bitwise.scala 72:15] - node _T_476 = mux(_T_475, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_477 = and(UInt<3>("h06"), _T_476) @[axi4_to_ahb.scala 130:15] - node _T_478 = or(_T_472, _T_477) @[axi4_to_ahb.scala 129:96] - node _T_479 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 131:33] - node _T_480 = eq(_T_479, UInt<8>("h0c0")) @[axi4_to_ahb.scala 131:40] - node _T_481 = bits(_T_480, 0, 0) @[Bitwise.scala 72:15] - node _T_482 = mux(_T_481, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_483 = and(UInt<3>("h06"), _T_482) @[axi4_to_ahb.scala 131:13] - node _T_484 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 265:152] - node _T_485 = mux(_T_445, _T_478, _T_484) @[axi4_to_ahb.scala 265:43] - node _T_486 = cat(_T_441, _T_485) @[Cat.scala 29:58] - buf_addr_in <= _T_486 @[axi4_to_ahb.scala 265:15] - node _T_487 = bits(master_tag, 2, 0) @[axi4_to_ahb.scala 266:27] - buf_tag_in <= _T_487 @[axi4_to_ahb.scala 266:14] - node _T_488 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 267:32] - buf_byteen_in <= _T_488 @[axi4_to_ahb.scala 267:17] - node _T_489 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 268:33] - node _T_490 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 268:59] - node _T_491 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 268:80] - node _T_492 = mux(_T_489, _T_490, _T_491) @[axi4_to_ahb.scala 268:21] - buf_data_in <= _T_492 @[axi4_to_ahb.scala 268:15] - node _T_493 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 269:52] - node _T_494 = eq(_T_493, UInt<2>("h03")) @[axi4_to_ahb.scala 269:58] - node _T_495 = and(buf_aligned_in, _T_494) @[axi4_to_ahb.scala 269:38] - node _T_496 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 269:84] - node _T_497 = eq(_T_496, UInt<1>("h01")) @[axi4_to_ahb.scala 269:91] - node _T_498 = and(_T_495, _T_497) @[axi4_to_ahb.scala 269:71] - node _T_499 = bits(_T_498, 0, 0) @[axi4_to_ahb.scala 269:111] - node _T_500 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 269:142] - node _T_501 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 121:42] - node _T_502 = eq(_T_501, UInt<8>("h0ff")) @[axi4_to_ahb.scala 121:49] - node _T_503 = bits(_T_502, 0, 0) @[Bitwise.scala 72:15] - node _T_504 = mux(_T_503, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_505 = and(UInt<2>("h03"), _T_504) @[axi4_to_ahb.scala 121:25] - node _T_506 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 122:35] - node _T_507 = eq(_T_506, UInt<8>("h0f0")) @[axi4_to_ahb.scala 122:42] - node _T_508 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 122:64] - node _T_509 = eq(_T_508, UInt<8>("h0f")) @[axi4_to_ahb.scala 122:71] - node _T_510 = or(_T_507, _T_509) @[axi4_to_ahb.scala 122:55] - node _T_511 = bits(_T_510, 0, 0) @[Bitwise.scala 72:15] - node _T_512 = mux(_T_511, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_513 = and(UInt<2>("h02"), _T_512) @[axi4_to_ahb.scala 122:16] - node _T_514 = or(_T_505, _T_513) @[axi4_to_ahb.scala 121:64] - node _T_515 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:40] - node _T_516 = eq(_T_515, UInt<8>("h0c0")) @[axi4_to_ahb.scala 123:47] - node _T_517 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:69] - node _T_518 = eq(_T_517, UInt<6>("h030")) @[axi4_to_ahb.scala 123:76] - node _T_519 = or(_T_516, _T_518) @[axi4_to_ahb.scala 123:60] - node _T_520 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:98] - node _T_521 = eq(_T_520, UInt<8>("h0c")) @[axi4_to_ahb.scala 123:105] - node _T_522 = or(_T_519, _T_521) @[axi4_to_ahb.scala 123:89] - node _T_523 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:132] - node _T_524 = eq(_T_523, UInt<8>("h03")) @[axi4_to_ahb.scala 123:139] - node _T_525 = or(_T_522, _T_524) @[axi4_to_ahb.scala 123:123] - node _T_526 = bits(_T_525, 0, 0) @[Bitwise.scala 72:15] - node _T_527 = mux(_T_526, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_528 = and(UInt<2>("h01"), _T_527) @[axi4_to_ahb.scala 123:21] - node _T_529 = or(_T_514, _T_528) @[axi4_to_ahb.scala 122:93] - node _T_530 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 269:161] - node _T_531 = mux(_T_499, _T_529, _T_530) @[axi4_to_ahb.scala 269:21] - buf_size_in <= _T_531 @[axi4_to_ahb.scala 269:15] - node _T_532 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 270:32] - node _T_533 = eq(_T_532, UInt<1>("h00")) @[axi4_to_ahb.scala 270:39] - node _T_534 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 271:17] - node _T_535 = eq(_T_534, UInt<1>("h00")) @[axi4_to_ahb.scala 271:24] - node _T_536 = or(_T_533, _T_535) @[axi4_to_ahb.scala 270:48] - node _T_537 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 271:47] - node _T_538 = eq(_T_537, UInt<2>("h01")) @[axi4_to_ahb.scala 271:54] - node _T_539 = or(_T_536, _T_538) @[axi4_to_ahb.scala 271:33] - node _T_540 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 271:86] - node _T_541 = eq(_T_540, UInt<2>("h02")) @[axi4_to_ahb.scala 271:93] - node _T_542 = or(_T_539, _T_541) @[axi4_to_ahb.scala 271:72] - node _T_543 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 272:18] - node _T_544 = eq(_T_543, UInt<2>("h03")) @[axi4_to_ahb.scala 272:25] - node _T_545 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:55] - node _T_546 = eq(_T_545, UInt<2>("h03")) @[axi4_to_ahb.scala 272:62] - node _T_547 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:90] - node _T_548 = eq(_T_547, UInt<4>("h0c")) @[axi4_to_ahb.scala 272:97] - node _T_549 = or(_T_546, _T_548) @[axi4_to_ahb.scala 272:74] - node _T_550 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:125] - node _T_551 = eq(_T_550, UInt<6>("h030")) @[axi4_to_ahb.scala 272:132] - node _T_552 = or(_T_549, _T_551) @[axi4_to_ahb.scala 272:109] - node _T_553 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:161] - node _T_554 = eq(_T_553, UInt<8>("h0c0")) @[axi4_to_ahb.scala 272:168] - node _T_555 = or(_T_552, _T_554) @[axi4_to_ahb.scala 272:145] - node _T_556 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 273:21] - node _T_557 = eq(_T_556, UInt<4>("h0f")) @[axi4_to_ahb.scala 273:28] - node _T_558 = or(_T_555, _T_557) @[axi4_to_ahb.scala 272:181] - node _T_559 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 273:56] - node _T_560 = eq(_T_559, UInt<8>("h0f0")) @[axi4_to_ahb.scala 273:63] - node _T_561 = or(_T_558, _T_560) @[axi4_to_ahb.scala 273:40] - node _T_562 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 273:92] - node _T_563 = eq(_T_562, UInt<8>("h0ff")) @[axi4_to_ahb.scala 273:99] - node _T_564 = or(_T_561, _T_563) @[axi4_to_ahb.scala 273:76] - node _T_565 = and(_T_544, _T_564) @[axi4_to_ahb.scala 272:38] - node _T_566 = or(_T_542, _T_565) @[axi4_to_ahb.scala 271:106] - buf_aligned_in <= _T_566 @[axi4_to_ahb.scala 270:18] - node _T_567 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 275:43] - node _T_568 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 275:62] - node _T_569 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 275:87] - node _T_570 = cat(_T_568, _T_569) @[Cat.scala 29:58] - node _T_571 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 275:108] - node _T_572 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 275:133] - node _T_573 = cat(_T_571, _T_572) @[Cat.scala 29:58] - node _T_574 = mux(_T_567, _T_570, _T_573) @[axi4_to_ahb.scala 275:26] - io.ahb.out.haddr <= _T_574 @[axi4_to_ahb.scala 275:20] - node _T_575 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 276:43] - node _T_576 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15] - node _T_577 = mux(_T_576, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_578 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 276:94] - node _T_579 = and(_T_577, _T_578) @[axi4_to_ahb.scala 276:81] - node _T_580 = cat(UInt<1>("h00"), _T_579) @[Cat.scala 29:58] - node _T_581 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15] - node _T_582 = mux(_T_581, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_583 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 276:148] - node _T_584 = and(_T_582, _T_583) @[axi4_to_ahb.scala 276:138] - node _T_585 = cat(UInt<1>("h00"), _T_584) @[Cat.scala 29:58] - node _T_586 = mux(_T_575, _T_580, _T_585) @[axi4_to_ahb.scala 276:26] - io.ahb.out.hsize <= _T_586 @[axi4_to_ahb.scala 276:20] - io.ahb.out.hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 278:21] - io.ahb.out.hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 279:24] - node _T_587 = bits(io.axi.ar.bits.prot, 2, 2) @[axi4_to_ahb.scala 280:57] - node _T_588 = eq(_T_587, UInt<1>("h00")) @[axi4_to_ahb.scala 280:37] - node _T_589 = cat(UInt<1>("h01"), _T_588) @[Cat.scala 29:58] - io.ahb.out.hprot <= _T_589 @[axi4_to_ahb.scala 280:20] - node _T_590 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 281:44] - node _T_591 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 281:59] - node _T_592 = eq(_T_591, UInt<1>("h01")) @[axi4_to_ahb.scala 281:66] - node _T_593 = mux(_T_590, _T_592, buf_write) @[axi4_to_ahb.scala 281:27] - io.ahb.out.hwrite <= _T_593 @[axi4_to_ahb.scala 281:21] - node _T_594 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 282:32] - io.ahb.out.hwdata <= _T_594 @[axi4_to_ahb.scala 282:21] - slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 284:15] - node _T_595 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 285:43] - node _T_596 = mux(_T_595, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 285:23] - node _T_597 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15] - node _T_598 = mux(_T_597, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_599 = and(_T_598, UInt<2>("h02")) @[axi4_to_ahb.scala 285:88] - node _T_600 = cat(_T_596, _T_599) @[Cat.scala 29:58] - slave_opc <= _T_600 @[axi4_to_ahb.scala 285:13] - node _T_601 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 286:41] - node _T_602 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 286:66] - node _T_603 = cat(_T_602, _T_602) @[Cat.scala 29:58] - node _T_604 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 286:91] - node _T_605 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 286:110] - node _T_606 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 286:131] - node _T_607 = mux(_T_604, _T_605, _T_606) @[axi4_to_ahb.scala 286:79] - node _T_608 = mux(_T_601, _T_603, _T_607) @[axi4_to_ahb.scala 286:21] - slave_rdata <= _T_608 @[axi4_to_ahb.scala 286:15] - node _T_609 = bits(slvbuf_tag, 2, 0) @[axi4_to_ahb.scala 287:26] - slave_tag <= _T_609 @[axi4_to_ahb.scala 287:13] - node _T_610 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 289:37] - node _T_611 = neq(_T_610, UInt<1>("h00")) @[axi4_to_ahb.scala 289:44] - node _T_612 = and(_T_611, io.ahb.in.hready) @[axi4_to_ahb.scala 289:56] - node _T_613 = and(_T_612, io.ahb.out.hwrite) @[axi4_to_ahb.scala 289:75] - last_addr_en <= _T_613 @[axi4_to_ahb.scala 289:16] - node _T_614 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 291:31] - node _T_615 = and(_T_614, master_ready) @[axi4_to_ahb.scala 291:49] - wrbuf_en <= _T_615 @[axi4_to_ahb.scala 291:12] - node _T_616 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 292:35] - node _T_617 = and(_T_616, master_ready) @[axi4_to_ahb.scala 292:52] - wrbuf_data_en <= _T_617 @[axi4_to_ahb.scala 292:17] - node _T_618 = and(master_valid, master_ready) @[axi4_to_ahb.scala 293:34] - node _T_619 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 293:62] - node _T_620 = eq(_T_619, UInt<1>("h01")) @[axi4_to_ahb.scala 293:69] - node _T_621 = and(_T_618, _T_620) @[axi4_to_ahb.scala 293:49] - wrbuf_cmd_sent <= _T_621 @[axi4_to_ahb.scala 293:18] - node _T_622 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 294:33] - node _T_623 = and(wrbuf_cmd_sent, _T_622) @[axi4_to_ahb.scala 294:31] - wrbuf_rst <= _T_623 @[axi4_to_ahb.scala 294:13] - node _T_624 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 296:36] - node _T_625 = and(wrbuf_vld, _T_624) @[axi4_to_ahb.scala 296:34] - node _T_626 = eq(_T_625, UInt<1>("h00")) @[axi4_to_ahb.scala 296:22] - node _T_627 = and(_T_626, master_ready) @[axi4_to_ahb.scala 296:53] - io.axi.aw.ready <= _T_627 @[axi4_to_ahb.scala 296:19] - node _T_628 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 297:40] - node _T_629 = and(wrbuf_data_vld, _T_628) @[axi4_to_ahb.scala 297:38] - node _T_630 = eq(_T_629, UInt<1>("h00")) @[axi4_to_ahb.scala 297:21] - node _T_631 = and(_T_630, master_ready) @[axi4_to_ahb.scala 297:57] - io.axi.w.ready <= _T_631 @[axi4_to_ahb.scala 297:18] - node _T_632 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 298:34] - node _T_633 = eq(_T_632, UInt<1>("h00")) @[axi4_to_ahb.scala 298:22] - node _T_634 = and(_T_633, master_ready) @[axi4_to_ahb.scala 298:52] - io.axi.ar.ready <= _T_634 @[axi4_to_ahb.scala 298:19] - io.axi.r.bits.last <= UInt<1>("h01") @[axi4_to_ahb.scala 299:22] - node _T_635 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 301:71] - node _T_636 = mux(_T_635, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 301:55] - node _T_637 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 301:91] - node _T_638 = and(_T_636, _T_637) @[axi4_to_ahb.scala 301:89] - reg _T_639 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 301:51] - _T_639 <= _T_638 @[axi4_to_ahb.scala 301:51] - wrbuf_vld <= _T_639 @[axi4_to_ahb.scala 301:21] - node _T_640 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 302:76] - node _T_641 = mux(_T_640, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 302:55] - node _T_642 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 302:102] - node _T_643 = and(_T_641, _T_642) @[axi4_to_ahb.scala 302:100] - reg _T_644 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 302:51] - _T_644 <= _T_643 @[axi4_to_ahb.scala 302:51] - wrbuf_data_vld <= _T_644 @[axi4_to_ahb.scala 302:21] - node _T_645 = bits(io.axi.aw.bits.id, 2, 0) @[axi4_to_ahb.scala 303:71] - node _T_646 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 303:105] - reg _T_647 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_646 : @[Reg.scala 28:19] - _T_647 <= _T_645 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - wrbuf_tag <= _T_647 @[axi4_to_ahb.scala 303:21] - node _T_648 = bits(io.axi.aw.bits.size, 2, 0) @[axi4_to_ahb.scala 304:73] - node _T_649 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 304:101] - reg _T_650 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_649 : @[Reg.scala 28:19] - _T_650 <= _T_648 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - wrbuf_size <= _T_650 @[axi4_to_ahb.scala 304:21] - node _T_651 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 305:61] - inst rvclkhdr_2 of rvclkhdr_871 @[lib.scala 368:23] - rvclkhdr_2.clock <= clock - rvclkhdr_2.reset <= reset - rvclkhdr_2.io.clk <= bus_clk @[lib.scala 370:18] - rvclkhdr_2.io.en <= _T_651 @[lib.scala 371:17] - rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_652 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_652 <= io.axi.aw.bits.addr @[lib.scala 374:16] - wrbuf_addr <= _T_652 @[axi4_to_ahb.scala 305:21] - node _T_653 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 306:65] - inst rvclkhdr_3 of rvclkhdr_872 @[lib.scala 368:23] - rvclkhdr_3.clock <= clock - rvclkhdr_3.reset <= reset - rvclkhdr_3.io.clk <= bus_clk @[lib.scala 370:18] - rvclkhdr_3.io.en <= _T_653 @[lib.scala 371:17] - rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_654 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_654 <= io.axi.w.bits.data @[lib.scala 374:16] - wrbuf_data <= _T_654 @[axi4_to_ahb.scala 306:21] - node _T_655 = bits(io.axi.w.bits.strb, 7, 0) @[axi4_to_ahb.scala 307:72] - node _T_656 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 307:105] - reg _T_657 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_656 : @[Reg.scala 28:19] - _T_657 <= _T_655 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - wrbuf_byteen <= _T_657 @[axi4_to_ahb.scala 307:21] - node _T_658 = bits(io.ahb.out.haddr, 31, 0) @[axi4_to_ahb.scala 308:71] - node _T_659 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 308:104] - reg _T_660 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_659 : @[Reg.scala 28:19] - _T_660 <= _T_658 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - last_bus_addr <= _T_660 @[axi4_to_ahb.scala 308:21] - node _T_661 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 309:89] - reg _T_662 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_661 : @[Reg.scala 28:19] - _T_662 <= buf_write_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_write <= _T_662 @[axi4_to_ahb.scala 309:21] - node _T_663 = bits(buf_tag_in, 2, 0) @[axi4_to_ahb.scala 310:64] - node _T_664 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 310:99] - reg _T_665 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_664 : @[Reg.scala 28:19] - _T_665 <= _T_663 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_tag <= _T_665 @[axi4_to_ahb.scala 310:21] - node _T_666 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 311:42] - node _T_667 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 311:61] - node _T_668 = bits(_T_667, 0, 0) @[axi4_to_ahb.scala 311:78] - inst rvclkhdr_4 of rvclkhdr_873 @[lib.scala 368:23] - rvclkhdr_4.clock <= clock - rvclkhdr_4.reset <= reset - rvclkhdr_4.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_4.io.en <= _T_668 @[lib.scala 371:17] - rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_669 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_669 <= _T_666 @[lib.scala 374:16] - buf_addr <= _T_669 @[axi4_to_ahb.scala 311:21] - node _T_670 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 312:65] - node _T_671 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 312:94] - reg _T_672 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_671 : @[Reg.scala 28:19] - _T_672 <= _T_670 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_size <= _T_672 @[axi4_to_ahb.scala 312:21] - node _T_673 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 313:91] - reg _T_674 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_673 : @[Reg.scala 28:19] - _T_674 <= buf_aligned_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_aligned <= _T_674 @[axi4_to_ahb.scala 313:21] - node _T_675 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 314:67] - node _T_676 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 314:96] - reg _T_677 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_676 : @[Reg.scala 28:19] - _T_677 <= _T_675 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_byteen <= _T_677 @[axi4_to_ahb.scala 314:21] - node _T_678 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 315:42] - node _T_679 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 315:66] - node _T_680 = bits(_T_679, 0, 0) @[axi4_to_ahb.scala 315:89] - inst rvclkhdr_5 of rvclkhdr_874 @[lib.scala 368:23] - rvclkhdr_5.clock <= clock - rvclkhdr_5.reset <= reset - rvclkhdr_5.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_5.io.en <= _T_680 @[lib.scala 371:17] - rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_681 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_681 <= _T_678 @[lib.scala 374:16] - buf_data <= _T_681 @[axi4_to_ahb.scala 315:21] - node _T_682 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 316:89] - reg _T_683 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_682 : @[Reg.scala 28:19] - _T_683 <= buf_write @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - slvbuf_write <= _T_683 @[axi4_to_ahb.scala 316:21] - node _T_684 = bits(buf_tag, 2, 0) @[axi4_to_ahb.scala 317:61] - node _T_685 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 317:99] - reg _T_686 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_685 : @[Reg.scala 28:19] - _T_686 <= _T_684 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - slvbuf_tag <= _T_686 @[axi4_to_ahb.scala 317:21] - node _T_687 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 318:99] - reg _T_688 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_687 : @[Reg.scala 28:19] - _T_688 <= slvbuf_error_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - slvbuf_error <= _T_688 @[axi4_to_ahb.scala 318:21] - node _T_689 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 319:72] - node _T_690 = mux(_T_689, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 319:56] - node _T_691 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 319:92] - node _T_692 = and(_T_690, _T_691) @[axi4_to_ahb.scala 319:90] - reg _T_693 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 319:52] - _T_693 <= _T_692 @[axi4_to_ahb.scala 319:52] - cmd_doneQ <= _T_693 @[axi4_to_ahb.scala 319:21] - node _T_694 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 320:71] - node _T_695 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 320:110] - reg _T_696 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_695 : @[Reg.scala 28:19] - _T_696 <= _T_694 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_cmd_byte_ptrQ <= _T_696 @[axi4_to_ahb.scala 320:21] - reg _T_697 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 321:52] - _T_697 <= io.ahb.in.hready @[axi4_to_ahb.scala 321:52] - ahb_hready_q <= _T_697 @[axi4_to_ahb.scala 321:21] - node _T_698 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 322:70] - reg _T_699 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 322:52] - _T_699 <= _T_698 @[axi4_to_ahb.scala 322:52] - ahb_htrans_q <= _T_699 @[axi4_to_ahb.scala 322:21] - reg _T_700 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 323:57] - _T_700 <= io.ahb.out.hwrite @[axi4_to_ahb.scala 323:57] - ahb_hwrite_q <= _T_700 @[axi4_to_ahb.scala 323:21] - reg _T_701 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 324:52] - _T_701 <= io.ahb.in.hresp @[axi4_to_ahb.scala 324:52] - ahb_hresp_q <= _T_701 @[axi4_to_ahb.scala 324:21] - node _T_702 = bits(io.ahb.in.hrdata, 63, 0) @[axi4_to_ahb.scala 325:74] - reg _T_703 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 325:57] - _T_703 <= _T_702 @[axi4_to_ahb.scala 325:57] - ahb_hrdata_q <= _T_703 @[axi4_to_ahb.scala 325:21] - node _T_704 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 327:43] - node _T_705 = or(_T_704, io.clk_override) @[axi4_to_ahb.scala 327:58] - node _T_706 = and(io.bus_clk_en, _T_705) @[axi4_to_ahb.scala 327:30] - buf_clken <= _T_706 @[axi4_to_ahb.scala 327:13] - node _T_707 = bits(io.ahb.out.htrans, 1, 1) @[axi4_to_ahb.scala 328:76] - node _T_708 = and(io.ahb.in.hready, _T_707) @[axi4_to_ahb.scala 328:57] - node _T_709 = or(_T_708, io.clk_override) @[axi4_to_ahb.scala 328:81] - node _T_710 = and(io.bus_clk_en, _T_709) @[axi4_to_ahb.scala 328:36] - ahbm_addr_clken <= _T_710 @[axi4_to_ahb.scala 328:19] - node _T_711 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 329:50] - node _T_712 = or(_T_711, io.clk_override) @[axi4_to_ahb.scala 329:60] - node _T_713 = and(io.bus_clk_en, _T_712) @[axi4_to_ahb.scala 329:36] - ahbm_data_clken <= _T_713 @[axi4_to_ahb.scala 329:19] - inst rvclkhdr_6 of rvclkhdr_875 @[lib.scala 343:22] - rvclkhdr_6.clock <= clock - rvclkhdr_6.reset <= reset - rvclkhdr_6.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_6.io.en <= buf_clken @[lib.scala 345:16] - rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 332:12] - inst rvclkhdr_7 of rvclkhdr_876 @[lib.scala 343:22] - rvclkhdr_7.clock <= clock - rvclkhdr_7.reset <= reset - rvclkhdr_7.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_7.io.en <= io.bus_clk_en @[lib.scala 345:16] - rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 333:12] - inst rvclkhdr_8 of rvclkhdr_877 @[lib.scala 343:22] - rvclkhdr_8.clock <= clock - rvclkhdr_8.reset <= reset - rvclkhdr_8.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_8.io.en <= ahbm_addr_clken @[lib.scala 345:16] - rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 334:17] - inst rvclkhdr_9 of rvclkhdr_878 @[lib.scala 343:22] - rvclkhdr_9.clock <= clock - rvclkhdr_9.reset <= reset - rvclkhdr_9.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_9.io.en <= ahbm_data_clken @[lib.scala 345:16] - rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 335:17] - - extmodule gated_latch_879 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_879 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_879 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_880 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_880 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_880 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_881 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_881 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_881 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_882 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_882 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_882 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_883 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_883 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_883 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_884 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_884 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_884 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - module ahb_to_axi4 : - input clock : Clock - input reset : AsyncReset - output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ahb : {flip sig : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, flip hsel : UInt<1>, flip hreadyin : UInt<1>}} - - wire _T : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[ahb_to_axi4.scala 20:25] - _T.r.bits.last <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.r.bits.resp <= UInt<2>("h00") @[ahb_to_axi4.scala 20:25] - _T.r.bits.data <= UInt<64>("h00") @[ahb_to_axi4.scala 20:25] - _T.r.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.r.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.r.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.ar.bits.qos <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25] - _T.ar.bits.prot <= UInt<3>("h00") @[ahb_to_axi4.scala 20:25] - _T.ar.bits.cache <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25] - _T.ar.bits.lock <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.ar.bits.burst <= UInt<2>("h00") @[ahb_to_axi4.scala 20:25] - _T.ar.bits.size <= UInt<3>("h00") @[ahb_to_axi4.scala 20:25] - _T.ar.bits.len <= UInt<8>("h00") @[ahb_to_axi4.scala 20:25] - _T.ar.bits.region <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25] - _T.ar.bits.addr <= UInt<32>("h00") @[ahb_to_axi4.scala 20:25] - _T.ar.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.ar.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.ar.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.b.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.b.bits.resp <= UInt<2>("h00") @[ahb_to_axi4.scala 20:25] - _T.b.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.b.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.w.bits.last <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.w.bits.strb <= UInt<8>("h00") @[ahb_to_axi4.scala 20:25] - _T.w.bits.data <= UInt<64>("h00") @[ahb_to_axi4.scala 20:25] - _T.w.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.w.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.aw.bits.qos <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25] - _T.aw.bits.prot <= UInt<3>("h00") @[ahb_to_axi4.scala 20:25] - _T.aw.bits.cache <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25] - _T.aw.bits.lock <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.aw.bits.burst <= UInt<2>("h00") @[ahb_to_axi4.scala 20:25] - _T.aw.bits.size <= UInt<3>("h00") @[ahb_to_axi4.scala 20:25] - _T.aw.bits.len <= UInt<8>("h00") @[ahb_to_axi4.scala 20:25] - _T.aw.bits.region <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25] - _T.aw.bits.addr <= UInt<32>("h00") @[ahb_to_axi4.scala 20:25] - _T.aw.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.aw.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.aw.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.r.bits.last <= io.axi.r.bits.last @[ahb_to_axi4.scala 20:10] - _T.r.bits.resp <= io.axi.r.bits.resp @[ahb_to_axi4.scala 20:10] - _T.r.bits.data <= io.axi.r.bits.data @[ahb_to_axi4.scala 20:10] - _T.r.bits.id <= io.axi.r.bits.id @[ahb_to_axi4.scala 20:10] - _T.r.valid <= io.axi.r.valid @[ahb_to_axi4.scala 20:10] - io.axi.r.ready <= _T.r.ready @[ahb_to_axi4.scala 20:10] - io.axi.ar.bits.qos <= _T.ar.bits.qos @[ahb_to_axi4.scala 20:10] - io.axi.ar.bits.prot <= _T.ar.bits.prot @[ahb_to_axi4.scala 20:10] - io.axi.ar.bits.cache <= _T.ar.bits.cache @[ahb_to_axi4.scala 20:10] - io.axi.ar.bits.lock <= _T.ar.bits.lock @[ahb_to_axi4.scala 20:10] - io.axi.ar.bits.burst <= _T.ar.bits.burst @[ahb_to_axi4.scala 20:10] - io.axi.ar.bits.size <= _T.ar.bits.size @[ahb_to_axi4.scala 20:10] - io.axi.ar.bits.len <= _T.ar.bits.len @[ahb_to_axi4.scala 20:10] - io.axi.ar.bits.region <= _T.ar.bits.region @[ahb_to_axi4.scala 20:10] - io.axi.ar.bits.addr <= _T.ar.bits.addr @[ahb_to_axi4.scala 20:10] - io.axi.ar.bits.id <= _T.ar.bits.id @[ahb_to_axi4.scala 20:10] - io.axi.ar.valid <= _T.ar.valid @[ahb_to_axi4.scala 20:10] - _T.ar.ready <= io.axi.ar.ready @[ahb_to_axi4.scala 20:10] - _T.b.bits.id <= io.axi.b.bits.id @[ahb_to_axi4.scala 20:10] - _T.b.bits.resp <= io.axi.b.bits.resp @[ahb_to_axi4.scala 20:10] - _T.b.valid <= io.axi.b.valid @[ahb_to_axi4.scala 20:10] - io.axi.b.ready <= _T.b.ready @[ahb_to_axi4.scala 20:10] - io.axi.w.bits.last <= _T.w.bits.last @[ahb_to_axi4.scala 20:10] - io.axi.w.bits.strb <= _T.w.bits.strb @[ahb_to_axi4.scala 20:10] - io.axi.w.bits.data <= _T.w.bits.data @[ahb_to_axi4.scala 20:10] - io.axi.w.valid <= _T.w.valid @[ahb_to_axi4.scala 20:10] - _T.w.ready <= io.axi.w.ready @[ahb_to_axi4.scala 20:10] - io.axi.aw.bits.qos <= _T.aw.bits.qos @[ahb_to_axi4.scala 20:10] - io.axi.aw.bits.prot <= _T.aw.bits.prot @[ahb_to_axi4.scala 20:10] - io.axi.aw.bits.cache <= _T.aw.bits.cache @[ahb_to_axi4.scala 20:10] - io.axi.aw.bits.lock <= _T.aw.bits.lock @[ahb_to_axi4.scala 20:10] - io.axi.aw.bits.burst <= _T.aw.bits.burst @[ahb_to_axi4.scala 20:10] - io.axi.aw.bits.size <= _T.aw.bits.size @[ahb_to_axi4.scala 20:10] - io.axi.aw.bits.len <= _T.aw.bits.len @[ahb_to_axi4.scala 20:10] - io.axi.aw.bits.region <= _T.aw.bits.region @[ahb_to_axi4.scala 20:10] - io.axi.aw.bits.addr <= _T.aw.bits.addr @[ahb_to_axi4.scala 20:10] - io.axi.aw.bits.id <= _T.aw.bits.id @[ahb_to_axi4.scala 20:10] - io.axi.aw.valid <= _T.aw.valid @[ahb_to_axi4.scala 20:10] - _T.aw.ready <= io.axi.aw.ready @[ahb_to_axi4.scala 20:10] - wire master_wstrb : UInt<8> - master_wstrb <= UInt<8>("h00") - wire buf_state_en : UInt<1> - buf_state_en <= UInt<1>("h00") - wire buf_read_error_in : UInt<1> - buf_read_error_in <= UInt<1>("h00") - wire buf_read_error : UInt<1> - buf_read_error <= UInt<1>("h00") - wire buf_rdata : UInt<64> - buf_rdata <= UInt<64>("h00") - wire ahb_hready : UInt<1> - ahb_hready <= UInt<1>("h00") - wire ahb_hready_q : UInt<1> - ahb_hready_q <= UInt<1>("h00") - wire ahb_htrans_in : UInt<2> - ahb_htrans_in <= UInt<2>("h00") - wire ahb_htrans_q : UInt<2> - ahb_htrans_q <= UInt<2>("h00") - wire ahb_hsize_q : UInt<3> - ahb_hsize_q <= UInt<3>("h00") - wire ahb_hwrite_q : UInt<1> - ahb_hwrite_q <= UInt<1>("h00") - wire ahb_haddr_q : UInt<32> - ahb_haddr_q <= UInt<32>("h00") - wire ahb_hwdata_q : UInt<64> - ahb_hwdata_q <= UInt<64>("h00") - wire ahb_hresp_q : UInt<1> - ahb_hresp_q <= UInt<1>("h00") - wire buf_rdata_en : UInt<1> - buf_rdata_en <= UInt<1>("h00") - wire ahb_bus_addr_clk_en : UInt<1> - ahb_bus_addr_clk_en <= UInt<1>("h00") - wire buf_rdata_clk_en : UInt<1> - buf_rdata_clk_en <= UInt<1>("h00") - wire ahb_clk : Clock @[ahb_to_axi4.scala 43:33] - wire ahb_addr_clk : Clock @[ahb_to_axi4.scala 44:33] - wire buf_rdata_clk : Clock @[ahb_to_axi4.scala 45:33] - wire cmdbuf_wr_en : UInt<1> - cmdbuf_wr_en <= UInt<1>("h00") - wire cmdbuf_rst : UInt<1> - cmdbuf_rst <= UInt<1>("h00") - wire cmdbuf_full : UInt<1> - cmdbuf_full <= UInt<1>("h00") - wire cmdbuf_vld : UInt<1> - cmdbuf_vld <= UInt<1>("h00") - wire cmdbuf_write : UInt<1> - cmdbuf_write <= UInt<1>("h00") - wire cmdbuf_size : UInt<2> - cmdbuf_size <= UInt<2>("h00") - wire cmdbuf_wstrb : UInt<8> - cmdbuf_wstrb <= UInt<8>("h00") - wire cmdbuf_addr : UInt<32> - cmdbuf_addr <= UInt<32>("h00") - wire cmdbuf_wdata : UInt<64> - cmdbuf_wdata <= UInt<64>("h00") - wire bus_clk : Clock @[ahb_to_axi4.scala 57:33] - node _T_1 = bits(ahb_haddr_q, 31, 28) @[lib.scala 84:25] - node ahb_addr_in_dccm_region_nc = eq(_T_1, UInt<4>("h0f")) @[lib.scala 84:47] - node _T_2 = bits(ahb_haddr_q, 31, 16) @[lib.scala 87:14] - node ahb_addr_in_dccm = eq(_T_2, UInt<16>("h0f004")) @[lib.scala 87:29] - node _T_3 = bits(ahb_haddr_q, 31, 28) @[lib.scala 84:25] - node ahb_addr_in_iccm_region_nc = eq(_T_3, UInt<4>("h0e")) @[lib.scala 84:47] - node _T_4 = bits(ahb_haddr_q, 31, 16) @[lib.scala 87:14] - node ahb_addr_in_iccm = eq(_T_4, UInt<16>("h0ee00")) @[lib.scala 87:29] - node _T_5 = bits(ahb_haddr_q, 31, 28) @[lib.scala 84:25] - node ahb_addr_in_pic_region_nc = eq(_T_5, UInt<4>("h0f")) @[lib.scala 84:47] - node _T_6 = bits(ahb_haddr_q, 31, 15) @[lib.scala 87:14] - node ahb_addr_in_pic = eq(_T_6, UInt<17>("h01e018")) @[lib.scala 87:29] - wire buf_state : UInt<2> - buf_state <= UInt<2>("h00") - wire buf_nxtstate : UInt<2> - buf_nxtstate <= UInt<2>("h00") - buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 67:31] - buf_state_en <= UInt<1>("h00") @[ahb_to_axi4.scala 68:31] - buf_rdata_en <= UInt<1>("h00") @[ahb_to_axi4.scala 69:31] - buf_read_error_in <= UInt<1>("h00") @[ahb_to_axi4.scala 70:31] - cmdbuf_wr_en <= UInt<1>("h00") @[ahb_to_axi4.scala 71:31] - node _T_7 = eq(UInt<2>("h00"), buf_state) @[Conditional.scala 37:30] - when _T_7 : @[Conditional.scala 40:58] - node _T_8 = mux(io.ahb.sig.out.hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 75:26] - buf_nxtstate <= _T_8 @[ahb_to_axi4.scala 75:20] - node _T_9 = bits(io.ahb.sig.out.htrans, 1, 1) @[ahb_to_axi4.scala 76:57] - node _T_10 = and(ahb_hready, _T_9) @[ahb_to_axi4.scala 76:34] - node _T_11 = and(_T_10, io.ahb.hsel) @[ahb_to_axi4.scala 76:61] - buf_state_en <= _T_11 @[ahb_to_axi4.scala 76:20] - skip @[Conditional.scala 40:58] - else : @[Conditional.scala 39:67] - node _T_12 = eq(UInt<2>("h01"), buf_state) @[Conditional.scala 37:30] - when _T_12 : @[Conditional.scala 39:67] - node _T_13 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 79:72] - node _T_14 = eq(_T_13, UInt<1>("h00")) @[ahb_to_axi4.scala 79:79] - node _T_15 = or(io.ahb.sig.in.hresp, _T_14) @[ahb_to_axi4.scala 79:48] - node _T_16 = eq(io.ahb.hsel, UInt<1>("h00")) @[ahb_to_axi4.scala 79:93] - node _T_17 = or(_T_15, _T_16) @[ahb_to_axi4.scala 79:91] - node _T_18 = bits(_T_17, 0, 0) @[ahb_to_axi4.scala 79:107] - node _T_19 = mux(io.ahb.sig.out.hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 79:124] - node _T_20 = mux(_T_18, UInt<2>("h00"), _T_19) @[ahb_to_axi4.scala 79:26] - buf_nxtstate <= _T_20 @[ahb_to_axi4.scala 79:20] - node _T_21 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 80:24] - node _T_22 = or(_T_21, io.ahb.sig.in.hresp) @[ahb_to_axi4.scala 80:37] - buf_state_en <= _T_22 @[ahb_to_axi4.scala 80:20] - node _T_23 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 81:23] - node _T_24 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 81:85] - node _T_25 = eq(_T_24, UInt<2>("h01")) @[ahb_to_axi4.scala 81:92] - node _T_26 = and(_T_25, io.ahb.hsel) @[ahb_to_axi4.scala 81:110] - node _T_27 = or(io.ahb.sig.in.hresp, _T_26) @[ahb_to_axi4.scala 81:60] - node _T_28 = eq(_T_27, UInt<1>("h00")) @[ahb_to_axi4.scala 81:38] - node _T_29 = and(_T_23, _T_28) @[ahb_to_axi4.scala 81:36] - cmdbuf_wr_en <= _T_29 @[ahb_to_axi4.scala 81:20] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_30 = eq(UInt<2>("h02"), buf_state) @[Conditional.scala 37:30] - when _T_30 : @[Conditional.scala 39:67] - node _T_31 = mux(io.ahb.sig.in.hresp, UInt<2>("h00"), UInt<2>("h03")) @[ahb_to_axi4.scala 84:26] - buf_nxtstate <= _T_31 @[ahb_to_axi4.scala 84:20] - node _T_32 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 85:24] - node _T_33 = or(_T_32, io.ahb.sig.in.hresp) @[ahb_to_axi4.scala 85:37] - buf_state_en <= _T_33 @[ahb_to_axi4.scala 85:20] - node _T_34 = eq(io.ahb.sig.in.hresp, UInt<1>("h00")) @[ahb_to_axi4.scala 86:23] - node _T_35 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 86:46] - node _T_36 = and(_T_34, _T_35) @[ahb_to_axi4.scala 86:44] - cmdbuf_wr_en <= _T_36 @[ahb_to_axi4.scala 86:20] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_37 = eq(UInt<2>("h03"), buf_state) @[Conditional.scala 37:30] - when _T_37 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 89:20] - node _T_38 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 90:40] - node _T_39 = and(io.axi.r.valid, _T_38) @[ahb_to_axi4.scala 90:38] - buf_state_en <= _T_39 @[ahb_to_axi4.scala 90:20] - buf_rdata_en <= buf_state_en @[ahb_to_axi4.scala 91:20] - node _T_40 = bits(io.axi.r.bits.resp, 1, 0) @[ahb_to_axi4.scala 92:61] - node _T_41 = orr(_T_40) @[ahb_to_axi4.scala 92:68] - node _T_42 = and(buf_state_en, _T_41) @[ahb_to_axi4.scala 92:41] - buf_read_error_in <= _T_42 @[ahb_to_axi4.scala 92:25] - skip @[Conditional.scala 39:67] - node _T_43 = bits(buf_state_en, 0, 0) @[ahb_to_axi4.scala 95:99] - reg _T_44 : UInt, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_43 : @[Reg.scala 28:19] - _T_44 <= buf_nxtstate @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_state <= _T_44 @[ahb_to_axi4.scala 95:31] - node _T_45 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 97:54] - node _T_46 = eq(_T_45, UInt<1>("h00")) @[ahb_to_axi4.scala 97:60] - node _T_47 = bits(_T_46, 0, 0) @[Bitwise.scala 72:15] - node _T_48 = mux(_T_47, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_49 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 97:92] - node _T_50 = dshl(UInt<1>("h01"), _T_49) @[ahb_to_axi4.scala 97:78] - node _T_51 = and(_T_48, _T_50) @[ahb_to_axi4.scala 97:70] - node _T_52 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 98:24] - node _T_53 = eq(_T_52, UInt<1>("h01")) @[ahb_to_axi4.scala 98:30] - node _T_54 = bits(_T_53, 0, 0) @[Bitwise.scala 72:15] - node _T_55 = mux(_T_54, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_56 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 98:62] - node _T_57 = dshl(UInt<2>("h03"), _T_56) @[ahb_to_axi4.scala 98:48] - node _T_58 = and(_T_55, _T_57) @[ahb_to_axi4.scala 98:40] - node _T_59 = or(_T_51, _T_58) @[ahb_to_axi4.scala 97:109] - node _T_60 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 99:24] - node _T_61 = eq(_T_60, UInt<2>("h02")) @[ahb_to_axi4.scala 99:30] - node _T_62 = bits(_T_61, 0, 0) @[Bitwise.scala 72:15] - node _T_63 = mux(_T_62, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_64 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 99:62] - node _T_65 = dshl(UInt<4>("h0f"), _T_64) @[ahb_to_axi4.scala 99:48] - node _T_66 = and(_T_63, _T_65) @[ahb_to_axi4.scala 99:40] - node _T_67 = or(_T_59, _T_66) @[ahb_to_axi4.scala 98:79] - node _T_68 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 100:24] - node _T_69 = eq(_T_68, UInt<2>("h03")) @[ahb_to_axi4.scala 100:30] - node _T_70 = bits(_T_69, 0, 0) @[Bitwise.scala 72:15] - node _T_71 = mux(_T_70, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_72 = and(_T_71, UInt<8>("h0ff")) @[ahb_to_axi4.scala 100:40] - node _T_73 = or(_T_67, _T_72) @[ahb_to_axi4.scala 99:79] - master_wstrb <= _T_73 @[ahb_to_axi4.scala 97:31] - node _T_74 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 103:80] - node _T_75 = and(ahb_hresp_q, _T_74) @[ahb_to_axi4.scala 103:78] - node _T_76 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 103:98] - node _T_77 = eq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 103:124] - node _T_78 = or(_T_76, _T_77) @[ahb_to_axi4.scala 103:111] - node _T_79 = eq(buf_state, UInt<2>("h02")) @[ahb_to_axi4.scala 103:149] - node _T_80 = eq(buf_state, UInt<2>("h03")) @[ahb_to_axi4.scala 103:168] - node _T_81 = or(_T_79, _T_80) @[ahb_to_axi4.scala 103:156] - node _T_82 = eq(_T_81, UInt<1>("h00")) @[ahb_to_axi4.scala 103:137] - node _T_83 = and(_T_78, _T_82) @[ahb_to_axi4.scala 103:135] - node _T_84 = eq(buf_read_error, UInt<1>("h00")) @[ahb_to_axi4.scala 103:181] - node _T_85 = and(_T_83, _T_84) @[ahb_to_axi4.scala 103:179] - node _T_86 = mux(io.ahb.sig.in.hresp, _T_75, _T_85) @[ahb_to_axi4.scala 103:44] - io.ahb.sig.in.hready <= _T_86 @[ahb_to_axi4.scala 103:38] - node _T_87 = and(io.ahb.sig.in.hready, io.ahb.hreadyin) @[ahb_to_axi4.scala 104:55] - ahb_hready <= _T_87 @[ahb_to_axi4.scala 104:31] - node _T_88 = bits(io.ahb.hsel, 0, 0) @[Bitwise.scala 72:15] - node _T_89 = mux(_T_88, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_90 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 105:77] - node _T_91 = and(_T_89, _T_90) @[ahb_to_axi4.scala 105:54] - ahb_htrans_in <= _T_91 @[ahb_to_axi4.scala 105:31] - node _T_92 = bits(buf_rdata, 63, 0) @[ahb_to_axi4.scala 106:50] - io.ahb.sig.in.hrdata <= _T_92 @[ahb_to_axi4.scala 106:38] - node _T_93 = bits(ahb_htrans_q, 1, 0) @[ahb_to_axi4.scala 107:55] - node _T_94 = neq(_T_93, UInt<1>("h00")) @[ahb_to_axi4.scala 107:61] - node _T_95 = neq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 107:83] - node _T_96 = and(_T_94, _T_95) @[ahb_to_axi4.scala 107:70] - node _T_97 = or(ahb_addr_in_dccm, ahb_addr_in_iccm) @[ahb_to_axi4.scala 108:26] - node _T_98 = eq(_T_97, UInt<1>("h00")) @[ahb_to_axi4.scala 108:7] - node _T_99 = and(ahb_addr_in_dccm, ahb_hwrite_q) @[ahb_to_axi4.scala 109:46] - node _T_100 = or(ahb_addr_in_iccm, _T_99) @[ahb_to_axi4.scala 109:26] - node _T_101 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 109:80] - node _T_102 = eq(_T_101, UInt<2>("h02")) @[ahb_to_axi4.scala 109:86] - node _T_103 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 109:109] - node _T_104 = eq(_T_103, UInt<2>("h03")) @[ahb_to_axi4.scala 109:115] - node _T_105 = or(_T_102, _T_104) @[ahb_to_axi4.scala 109:95] - node _T_106 = eq(_T_105, UInt<1>("h00")) @[ahb_to_axi4.scala 109:66] - node _T_107 = and(_T_100, _T_106) @[ahb_to_axi4.scala 109:64] - node _T_108 = or(_T_98, _T_107) @[ahb_to_axi4.scala 108:47] - node _T_109 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 110:20] - node _T_110 = eq(_T_109, UInt<1>("h01")) @[ahb_to_axi4.scala 110:26] - node _T_111 = bits(ahb_haddr_q, 0, 0) @[ahb_to_axi4.scala 110:48] - node _T_112 = and(_T_110, _T_111) @[ahb_to_axi4.scala 110:35] - node _T_113 = or(_T_108, _T_112) @[ahb_to_axi4.scala 109:126] - node _T_114 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 111:20] - node _T_115 = eq(_T_114, UInt<2>("h02")) @[ahb_to_axi4.scala 111:26] - node _T_116 = bits(ahb_haddr_q, 1, 0) @[ahb_to_axi4.scala 111:49] - node _T_117 = orr(_T_116) @[ahb_to_axi4.scala 111:56] - node _T_118 = and(_T_115, _T_117) @[ahb_to_axi4.scala 111:35] - node _T_119 = or(_T_113, _T_118) @[ahb_to_axi4.scala 110:55] - node _T_120 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 112:20] - node _T_121 = eq(_T_120, UInt<2>("h03")) @[ahb_to_axi4.scala 112:26] - node _T_122 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 112:49] - node _T_123 = orr(_T_122) @[ahb_to_axi4.scala 112:56] - node _T_124 = and(_T_121, _T_123) @[ahb_to_axi4.scala 112:35] - node _T_125 = or(_T_119, _T_124) @[ahb_to_axi4.scala 111:61] - node _T_126 = and(_T_96, _T_125) @[ahb_to_axi4.scala 107:94] - node _T_127 = or(_T_126, buf_read_error) @[ahb_to_axi4.scala 112:63] - node _T_128 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 114:20] - node _T_129 = and(ahb_hresp_q, _T_128) @[ahb_to_axi4.scala 114:18] - node _T_130 = or(_T_127, _T_129) @[ahb_to_axi4.scala 113:20] - io.ahb.sig.in.hresp <= _T_130 @[ahb_to_axi4.scala 107:38] - reg _T_131 : UInt, buf_rdata_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 117:66] - _T_131 <= io.axi.r.bits.data @[ahb_to_axi4.scala 117:66] - buf_rdata <= _T_131 @[ahb_to_axi4.scala 117:31] - reg _T_132 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 118:60] - _T_132 <= buf_read_error_in @[ahb_to_axi4.scala 118:60] - buf_read_error <= _T_132 @[ahb_to_axi4.scala 118:31] - reg _T_133 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 121:60] - _T_133 <= io.ahb.sig.in.hresp @[ahb_to_axi4.scala 121:60] - ahb_hresp_q <= _T_133 @[ahb_to_axi4.scala 121:31] - reg _T_134 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 122:60] - _T_134 <= ahb_hready @[ahb_to_axi4.scala 122:60] - ahb_hready_q <= _T_134 @[ahb_to_axi4.scala 122:31] - reg _T_135 : UInt, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 123:60] - _T_135 <= ahb_htrans_in @[ahb_to_axi4.scala 123:60] - ahb_htrans_q <= _T_135 @[ahb_to_axi4.scala 123:31] - reg _T_136 : UInt, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 124:65] - _T_136 <= io.ahb.sig.out.hsize @[ahb_to_axi4.scala 124:65] - ahb_hsize_q <= _T_136 @[ahb_to_axi4.scala 124:31] - reg _T_137 : UInt<1>, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 125:65] - _T_137 <= io.ahb.sig.out.hwrite @[ahb_to_axi4.scala 125:65] - ahb_hwrite_q <= _T_137 @[ahb_to_axi4.scala 125:31] - reg _T_138 : UInt, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 126:65] - _T_138 <= io.ahb.sig.out.haddr @[ahb_to_axi4.scala 126:65] - ahb_haddr_q <= _T_138 @[ahb_to_axi4.scala 126:31] - node _T_139 = bits(io.ahb.sig.out.htrans, 1, 1) @[ahb_to_axi4.scala 129:85] - node _T_140 = and(ahb_hready, _T_139) @[ahb_to_axi4.scala 129:62] - node _T_141 = and(io.bus_clk_en, _T_140) @[ahb_to_axi4.scala 129:48] - ahb_bus_addr_clk_en <= _T_141 @[ahb_to_axi4.scala 129:31] - node _T_142 = and(io.bus_clk_en, buf_rdata_en) @[ahb_to_axi4.scala 130:48] - buf_rdata_clk_en <= _T_142 @[ahb_to_axi4.scala 130:31] - inst rvclkhdr of rvclkhdr_879 @[lib.scala 343:22] - rvclkhdr.clock <= clock - rvclkhdr.reset <= reset - rvclkhdr.io.clk <= clock @[lib.scala 344:17] - rvclkhdr.io.en <= io.bus_clk_en @[lib.scala 345:16] - rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahb_clk <= rvclkhdr.io.l1clk @[ahb_to_axi4.scala 132:31] - inst rvclkhdr_1 of rvclkhdr_880 @[lib.scala 343:22] - rvclkhdr_1.clock <= clock - rvclkhdr_1.reset <= reset - rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_1.io.en <= ahb_bus_addr_clk_en @[lib.scala 345:16] - rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahb_addr_clk <= rvclkhdr_1.io.l1clk @[ahb_to_axi4.scala 133:31] - inst rvclkhdr_2 of rvclkhdr_881 @[lib.scala 343:22] - rvclkhdr_2.clock <= clock - rvclkhdr_2.reset <= reset - rvclkhdr_2.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_2.io.en <= buf_rdata_clk_en @[lib.scala 345:16] - rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - buf_rdata_clk <= rvclkhdr_2.io.l1clk @[ahb_to_axi4.scala 134:31] - node _T_143 = and(io.axi.aw.valid, io.axi.aw.ready) @[ahb_to_axi4.scala 136:53] - node _T_144 = and(io.axi.ar.valid, io.axi.ar.ready) @[ahb_to_axi4.scala 136:91] - node _T_145 = or(_T_143, _T_144) @[ahb_to_axi4.scala 136:72] - node _T_146 = eq(cmdbuf_wr_en, UInt<1>("h00")) @[ahb_to_axi4.scala 136:113] - node _T_147 = and(_T_145, _T_146) @[ahb_to_axi4.scala 136:111] - node _T_148 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 136:153] - node _T_149 = and(io.ahb.sig.in.hresp, _T_148) @[ahb_to_axi4.scala 136:151] - node _T_150 = or(_T_147, _T_149) @[ahb_to_axi4.scala 136:128] - cmdbuf_rst <= _T_150 @[ahb_to_axi4.scala 136:31] - node _T_151 = and(io.axi.aw.valid, io.axi.aw.ready) @[ahb_to_axi4.scala 137:67] - node _T_152 = and(io.axi.ar.valid, io.axi.ar.ready) @[ahb_to_axi4.scala 137:105] - node _T_153 = or(_T_151, _T_152) @[ahb_to_axi4.scala 137:86] - node _T_154 = eq(_T_153, UInt<1>("h00")) @[ahb_to_axi4.scala 137:48] - node _T_155 = and(cmdbuf_vld, _T_154) @[ahb_to_axi4.scala 137:46] - cmdbuf_full <= _T_155 @[ahb_to_axi4.scala 137:31] - node _T_156 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 139:86] - node _T_157 = mux(_T_156, UInt<1>("h01"), cmdbuf_vld) @[ahb_to_axi4.scala 139:66] - node _T_158 = eq(cmdbuf_rst, UInt<1>("h00")) @[ahb_to_axi4.scala 139:110] - node _T_159 = and(_T_157, _T_158) @[ahb_to_axi4.scala 139:108] - reg _T_160 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 139:61] - _T_160 <= _T_159 @[ahb_to_axi4.scala 139:61] - cmdbuf_vld <= _T_160 @[ahb_to_axi4.scala 139:31] - node _T_161 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 143:53] - reg _T_162 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_161 : @[Reg.scala 28:19] - _T_162 <= ahb_hwrite_q @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - cmdbuf_write <= _T_162 @[ahb_to_axi4.scala 142:31] - node _T_163 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 146:52] - reg _T_164 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_163 : @[Reg.scala 28:19] - _T_164 <= ahb_hsize_q @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - cmdbuf_size <= _T_164 @[ahb_to_axi4.scala 145:31] - node _T_165 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 149:53] - reg _T_166 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_165 : @[Reg.scala 28:19] - _T_166 <= master_wstrb @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - cmdbuf_wstrb <= _T_166 @[ahb_to_axi4.scala 148:31] - node _T_167 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 152:57] - inst rvclkhdr_3 of rvclkhdr_882 @[lib.scala 368:23] - rvclkhdr_3.clock <= clock - rvclkhdr_3.reset <= reset - rvclkhdr_3.io.clk <= bus_clk @[lib.scala 370:18] - rvclkhdr_3.io.en <= _T_167 @[lib.scala 371:17] - rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_168 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_168 <= ahb_haddr_q @[lib.scala 374:16] - cmdbuf_addr <= _T_168 @[ahb_to_axi4.scala 152:15] - node _T_169 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 153:68] - inst rvclkhdr_4 of rvclkhdr_883 @[lib.scala 368:23] - rvclkhdr_4.clock <= clock - rvclkhdr_4.reset <= reset - rvclkhdr_4.io.clk <= bus_clk @[lib.scala 370:18] - rvclkhdr_4.io.en <= _T_169 @[lib.scala 371:17] - rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_170 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_170 <= io.ahb.sig.out.hwdata @[lib.scala 374:16] - cmdbuf_wdata <= _T_170 @[ahb_to_axi4.scala 153:16] - node _T_171 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 156:42] - io.axi.aw.valid <= _T_171 @[ahb_to_axi4.scala 156:28] - io.axi.aw.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 157:33] - io.axi.aw.bits.addr <= cmdbuf_addr @[ahb_to_axi4.scala 158:33] - node _T_172 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 159:59] - node _T_173 = cat(UInt<1>("h00"), _T_172) @[Cat.scala 29:58] - io.axi.aw.bits.size <= _T_173 @[ahb_to_axi4.scala 159:33] - node _T_174 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - io.axi.aw.bits.prot <= _T_174 @[ahb_to_axi4.scala 160:33] - node _T_175 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - io.axi.aw.bits.len <= _T_175 @[ahb_to_axi4.scala 161:33] - io.axi.aw.bits.burst <= UInt<1>("h01") @[ahb_to_axi4.scala 162:33] - node _T_176 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 164:42] - io.axi.w.valid <= _T_176 @[ahb_to_axi4.scala 164:28] - io.axi.w.bits.data <= cmdbuf_wdata @[ahb_to_axi4.scala 165:33] - io.axi.w.bits.strb <= cmdbuf_wstrb @[ahb_to_axi4.scala 166:33] - io.axi.w.bits.last <= UInt<1>("h01") @[ahb_to_axi4.scala 167:33] - io.axi.b.ready <= UInt<1>("h01") @[ahb_to_axi4.scala 169:28] - node _T_177 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 171:44] - node _T_178 = and(cmdbuf_vld, _T_177) @[ahb_to_axi4.scala 171:42] - io.axi.ar.valid <= _T_178 @[ahb_to_axi4.scala 171:28] - io.axi.ar.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 172:33] - io.axi.ar.bits.addr <= cmdbuf_addr @[ahb_to_axi4.scala 173:33] - node _T_179 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 174:59] - node _T_180 = cat(UInt<1>("h00"), _T_179) @[Cat.scala 29:58] - io.axi.ar.bits.size <= _T_180 @[ahb_to_axi4.scala 174:33] - node _T_181 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - io.axi.ar.bits.prot <= _T_181 @[ahb_to_axi4.scala 175:33] - node _T_182 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - io.axi.ar.bits.len <= _T_182 @[ahb_to_axi4.scala 176:33] - io.axi.ar.bits.burst <= UInt<1>("h01") @[ahb_to_axi4.scala 177:33] - io.axi.r.ready <= UInt<1>("h01") @[ahb_to_axi4.scala 179:28] - inst rvclkhdr_5 of rvclkhdr_884 @[lib.scala 343:22] - rvclkhdr_5.clock <= clock - rvclkhdr_5.reset <= reset - rvclkhdr_5.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_5.io.en <= io.bus_clk_en @[lib.scala 345:16] - rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - bus_clk <= rvclkhdr_5.io.l1clk @[ahb_to_axi4.scala 180:27] - module quasar : input clock : Clock input reset : AsyncReset @@ -113921,1009 +109103,715 @@ circuit quasar_wrapper : rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] rvclkhdr_1.io.en <= _T_7 @[lib.scala 345:16] rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - node core_dbg_cmd_done = or(dma_ctrl.io.dma_dbg_cmd_done, dec.io.dec_dbg_cmd_done) @[quasar.scala 86:56] - node core_dbg_cmd_fail = or(dma_ctrl.io.dma_dbg_cmd_fail, dec.io.dec_dbg_cmd_fail) @[quasar.scala 87:56] - node core_dbg_rddata = mux(dma_ctrl.io.dma_dbg_cmd_done, dma_ctrl.io.dma_dbg_rddata, dec.io.dec_dbg_rddata) @[quasar.scala 88:28] - ifu.io.ifu_dec.dec_bp.dec_tlu_bpred_disable <= dec.io.ifu_dec.dec_bp.dec_tlu_bpred_disable @[quasar.scala 91:18] - ifu.io.ifu_dec.dec_bp.dec_tlu_flush_leak_one_wb <= dec.io.ifu_dec.dec_bp.dec_tlu_flush_leak_one_wb @[quasar.scala 91:18] - ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.middle <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.middle @[quasar.scala 91:18] - ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.way <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.way @[quasar.scala 91:18] - ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_start_error <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_start_error @[quasar.scala 91:18] - ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_error <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_error @[quasar.scala 91:18] - ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.hist <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.hist @[quasar.scala 91:18] - ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.valid <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.valid @[quasar.scala 91:18] - dec.io.ifu_dec.dec_ifc.ifu_pmu_fetch_stall <= ifu.io.ifu_dec.dec_ifc.ifu_pmu_fetch_stall @[quasar.scala 91:18] - ifu.io.ifu_dec.dec_ifc.dec_tlu_mrac_ff <= dec.io.ifu_dec.dec_ifc.dec_tlu_mrac_ff @[quasar.scala 91:18] - ifu.io.ifu_dec.dec_ifc.dec_tlu_flush_noredir_wb <= dec.io.ifu_dec.dec_ifc.dec_tlu_flush_noredir_wb @[quasar.scala 91:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_miss_state_idle <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_miss_state_idle @[quasar.scala 91:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data_valid <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data_valid @[quasar.scala 91:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data @[quasar.scala 91:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err @[quasar.scala 91:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_ic_error_start <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_ic_error_start @[quasar.scala 91:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_trxn <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_trxn @[quasar.scala 91:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_busy <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_busy @[quasar.scala 91:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_error <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_error @[quasar.scala 91:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_hit <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_hit @[quasar.scala 91:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_miss <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_miss @[quasar.scala 91:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable @[quasar.scala 91:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid @[quasar.scala 91:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid @[quasar.scala 91:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics @[quasar.scala 91:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata @[quasar.scala 91:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_fence_i_wb <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_fence_i_wb @[quasar.scala 91:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt @[quasar.scala 91:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_i0_commit_cmt <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_i0_commit_cmt @[quasar.scala 91:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_flush_err_wb <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_flush_err_wb @[quasar.scala 91:18] - dec.io.ifu_dec.dec_aln.ifu_pmu_instr_aligned <= ifu.io.ifu_dec.dec_aln.ifu_pmu_instr_aligned @[quasar.scala 91:18] - dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.ret <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.ret @[quasar.scala 91:18] - dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.way <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.way @[quasar.scala 91:18] - dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.prett <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.prett @[quasar.scala 91:18] - dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.bank <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.bank @[quasar.scala 91:18] - dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_start_error <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_start_error @[quasar.scala 91:18] - dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_error <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_error @[quasar.scala 91:18] - dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.hist <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.hist @[quasar.scala 91:18] - dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.toffset <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.toffset @[quasar.scala 91:18] - dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.valid <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.valid @[quasar.scala 91:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc4 <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc4 @[quasar.scala 91:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc @[quasar.scala 91:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_instr <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_instr @[quasar.scala 91:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_valid <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_valid @[quasar.scala 91:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_btag <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_btag @[quasar.scala 91:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_fghr <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_fghr @[quasar.scala 91:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_index <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_index @[quasar.scala 91:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_dbecc <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_dbecc @[quasar.scala 91:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_f1 <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_f1 @[quasar.scala 91:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_type <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_type @[quasar.scala 91:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf @[quasar.scala 91:18] - dec.io.ifu_dec.dec_aln.aln_dec.ifu_i0_cinst <= ifu.io.ifu_dec.dec_aln.aln_dec.ifu_i0_cinst @[quasar.scala 91:18] - ifu.io.ifu_dec.dec_aln.aln_dec.dec_i0_decode_d <= dec.io.ifu_dec.dec_aln.aln_dec.dec_i0_decode_d @[quasar.scala 91:18] - ifu.reset <= io.core_rst_l @[quasar.scala 93:13] - ifu.io.scan_mode <= io.scan_mode @[quasar.scala 94:20] - ifu.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 95:19] - ifu.io.active_clk <= rvclkhdr_1.io.l1clk @[quasar.scala 96:21] - ifu.io.exu_flush_final <= dec.io.exu_flush_final @[quasar.scala 98:26] - ifu.io.exu_flush_path_final <= exu.io.exu_flush_path_final @[quasar.scala 99:31] - ifu.io.ifu_bus_clk_en <= io.ifu_bus_clk_en @[quasar.scala 101:25] - ifu.io.ifu_dma.dma_mem_ctl.dma_mem_tag <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_tag @[quasar.scala 102:18] - ifu.io.ifu_dma.dma_mem_ctl.dma_mem_wdata <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_wdata @[quasar.scala 102:18] - ifu.io.ifu_dma.dma_mem_ctl.dma_mem_write <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_write @[quasar.scala 102:18] - ifu.io.ifu_dma.dma_mem_ctl.dma_mem_sz <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_sz @[quasar.scala 102:18] - ifu.io.ifu_dma.dma_mem_ctl.dma_mem_addr <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_addr @[quasar.scala 102:18] - ifu.io.ifu_dma.dma_mem_ctl.dma_iccm_req <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_iccm_req @[quasar.scala 102:18] - ifu.io.ifu_dma.dma_ifc.dma_iccm_stall_any <= dma_ctrl.io.ifu_dma.dma_ifc.dma_iccm_stall_any @[quasar.scala 102:18] - io.ic.sel_premux_data <= ifu.io.ic.sel_premux_data @[quasar.scala 103:13] - io.ic.premux_data <= ifu.io.ic.premux_data @[quasar.scala 103:13] - io.ic.debug_way <= ifu.io.ic.debug_way @[quasar.scala 103:13] - io.ic.debug_tag_array <= ifu.io.ic.debug_tag_array @[quasar.scala 103:13] - io.ic.debug_wr_en <= ifu.io.ic.debug_wr_en @[quasar.scala 103:13] - io.ic.debug_rd_en <= ifu.io.ic.debug_rd_en @[quasar.scala 103:13] - ifu.io.ic.tag_perr <= io.ic.tag_perr @[quasar.scala 103:13] - ifu.io.ic.rd_hit <= io.ic.rd_hit @[quasar.scala 103:13] - ifu.io.ic.parerr <= io.ic.parerr @[quasar.scala 103:13] - ifu.io.ic.eccerr <= io.ic.eccerr @[quasar.scala 103:13] - ifu.io.ic.tag_debug_rd_data <= io.ic.tag_debug_rd_data @[quasar.scala 103:13] - ifu.io.ic.debug_rd_data <= io.ic.debug_rd_data @[quasar.scala 103:13] - ifu.io.ic.rd_data <= io.ic.rd_data @[quasar.scala 103:13] - io.ic.debug_addr <= ifu.io.ic.debug_addr @[quasar.scala 103:13] - io.ic.debug_wr_data <= ifu.io.ic.debug_wr_data @[quasar.scala 103:13] - io.ic.wr_data[0] <= ifu.io.ic.wr_data[0] @[quasar.scala 103:13] - io.ic.wr_data[1] <= ifu.io.ic.wr_data[1] @[quasar.scala 103:13] - io.ic.rd_en <= ifu.io.ic.rd_en @[quasar.scala 103:13] - io.ic.wr_en <= ifu.io.ic.wr_en @[quasar.scala 103:13] - io.ic.tag_valid <= ifu.io.ic.tag_valid @[quasar.scala 103:13] - io.ic.rw_addr <= ifu.io.ic.rw_addr @[quasar.scala 103:13] - ifu.io.iccm.rd_data_ecc <= io.iccm.rd_data_ecc @[quasar.scala 104:15] - ifu.io.iccm.rd_data <= io.iccm.rd_data @[quasar.scala 104:15] - io.iccm.wr_data <= ifu.io.iccm.wr_data @[quasar.scala 104:15] - io.iccm.wr_size <= ifu.io.iccm.wr_size @[quasar.scala 104:15] - io.iccm.rden <= ifu.io.iccm.rden @[quasar.scala 104:15] - io.iccm.wren <= ifu.io.iccm.wren @[quasar.scala 104:15] - io.iccm.correction_state <= ifu.io.iccm.correction_state @[quasar.scala 104:15] - io.iccm.buf_correct_ecc <= ifu.io.iccm.buf_correct_ecc @[quasar.scala 104:15] - io.iccm.rw_addr <= ifu.io.iccm.rw_addr @[quasar.scala 104:15] - ifu.io.exu_ifu.exu_bp.exu_mp_btag <= exu.io.exu_bp.exu_mp_btag @[quasar.scala 105:25] - ifu.io.exu_ifu.exu_bp.exu_mp_index <= exu.io.exu_bp.exu_mp_index @[quasar.scala 105:25] - ifu.io.exu_ifu.exu_bp.exu_mp_fghr <= exu.io.exu_bp.exu_mp_fghr @[quasar.scala 105:25] - ifu.io.exu_ifu.exu_bp.exu_mp_eghr <= exu.io.exu_bp.exu_mp_eghr @[quasar.scala 105:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.way <= exu.io.exu_bp.exu_mp_pkt.bits.way @[quasar.scala 105:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pja <= exu.io.exu_bp.exu_mp_pkt.bits.pja @[quasar.scala 105:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pret <= exu.io.exu_bp.exu_mp_pkt.bits.pret @[quasar.scala 105:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pcall <= exu.io.exu_bp.exu_mp_pkt.bits.pcall @[quasar.scala 105:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.prett <= exu.io.exu_bp.exu_mp_pkt.bits.prett @[quasar.scala 105:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.br_start_error <= exu.io.exu_bp.exu_mp_pkt.bits.br_start_error @[quasar.scala 105:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.br_error <= exu.io.exu_bp.exu_mp_pkt.bits.br_error @[quasar.scala 105:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.toffset <= exu.io.exu_bp.exu_mp_pkt.bits.toffset @[quasar.scala 105:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.hist <= exu.io.exu_bp.exu_mp_pkt.bits.hist @[quasar.scala 105:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pc4 <= exu.io.exu_bp.exu_mp_pkt.bits.pc4 @[quasar.scala 105:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.boffset <= exu.io.exu_bp.exu_mp_pkt.bits.boffset @[quasar.scala 105:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.ataken <= exu.io.exu_bp.exu_mp_pkt.bits.ataken @[quasar.scala 105:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.misp <= exu.io.exu_bp.exu_mp_pkt.bits.misp @[quasar.scala 105:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.valid <= exu.io.exu_bp.exu_mp_pkt.valid @[quasar.scala 105:25] - ifu.io.exu_ifu.exu_bp.exu_i0_br_way_r <= exu.io.exu_bp.exu_i0_br_way_r @[quasar.scala 105:25] - ifu.io.exu_ifu.exu_bp.exu_i0_br_fghr_r <= exu.io.exu_bp.exu_i0_br_fghr_r @[quasar.scala 105:25] - ifu.io.exu_ifu.exu_bp.exu_i0_br_index_r <= exu.io.exu_bp.exu_i0_br_index_r @[quasar.scala 105:25] - ifu.io.exu_ifu.exu_bp.exu_i0_br_fghr_r <= exu.io.exu_bp.exu_i0_br_fghr_r @[quasar.scala 106:42] - ifu.io.exu_ifu.exu_bp.exu_i0_br_index_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_index_r @[quasar.scala 107:43] - ifu.io.dec_tlu_flush_lower_wb <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[quasar.scala 108:33] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid @[quasar.scala 109:51] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid @[quasar.scala 109:51] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics @[quasar.scala 109:51] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata @[quasar.scala 109:51] - dec.reset <= io.core_rst_l @[quasar.scala 112:13] - dec.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 113:19] - dec.io.active_clk <= rvclkhdr_1.io.l1clk @[quasar.scala 114:21] - dec.io.lsu_fastint_stall_any <= lsu.io.lsu_fastint_stall_any @[quasar.scala 115:32] - dec.io.rst_vec <= io.rst_vec @[quasar.scala 116:18] - dec.io.nmi_int <= io.nmi_int @[quasar.scala 117:18] - dec.io.nmi_vec <= io.nmi_vec @[quasar.scala 118:18] - dec.io.i_cpu_halt_req <= io.i_cpu_halt_req @[quasar.scala 119:25] - dec.io.i_cpu_run_req <= io.i_cpu_run_req @[quasar.scala 120:24] - dec.io.core_id <= io.core_id @[quasar.scala 121:18] - dec.io.mpc_debug_halt_req <= io.mpc_debug_halt_req @[quasar.scala 122:29] - dec.io.mpc_debug_run_req <= io.mpc_debug_run_req @[quasar.scala 123:28] - dec.io.mpc_reset_run_req <= io.mpc_reset_run_req @[quasar.scala 124:28] - dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data @[quasar.scala 125:18] - dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_tag <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_tag @[quasar.scala 125:18] - dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_error <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_error @[quasar.scala 125:18] - dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_valid <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_valid @[quasar.scala 125:18] - dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_tag_r <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_tag_r @[quasar.scala 125:18] - dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_r <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_r @[quasar.scala 125:18] - dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_tag_m <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_tag_m @[quasar.scala 125:18] - dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_valid_m <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_valid_m @[quasar.scala 125:18] - dec.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_addr_any <= lsu.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_addr_any @[quasar.scala 125:18] - dec.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_store_any <= lsu.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_store_any @[quasar.scala 125:18] - dec.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_load_any <= lsu.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_load_any @[quasar.scala 125:18] - lsu.io.lsu_dec.tlu_busbuff.dec_tlu_sideeffect_posted_disable <= dec.io.lsu_dec.tlu_busbuff.dec_tlu_sideeffect_posted_disable @[quasar.scala 125:18] - lsu.io.lsu_dec.tlu_busbuff.dec_tlu_wb_coalescing_disable <= dec.io.lsu_dec.tlu_busbuff.dec_tlu_wb_coalescing_disable @[quasar.scala 125:18] - lsu.io.lsu_dec.tlu_busbuff.dec_tlu_external_ldfwd_disable <= dec.io.lsu_dec.tlu_busbuff.dec_tlu_external_ldfwd_disable @[quasar.scala 125:18] - dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_busy <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_busy @[quasar.scala 125:18] - dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_error <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_error @[quasar.scala 125:18] - dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_misaligned <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_misaligned @[quasar.scala 125:18] - dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_trxn <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_trxn @[quasar.scala 125:18] - dec.io.lsu_tlu.lsu_pmu_store_external_m <= lsu.io.lsu_tlu.lsu_pmu_store_external_m @[quasar.scala 126:18] - dec.io.lsu_tlu.lsu_pmu_load_external_m <= lsu.io.lsu_tlu.lsu_pmu_load_external_m @[quasar.scala 126:18] - dec.io.lsu_pmu_misaligned_m <= lsu.io.lsu_pmu_misaligned_m @[quasar.scala 127:31] - dec.io.dec_dma.tlu_dma.dma_iccm_stall_any <= dma_ctrl.io.dec_dma.tlu_dma.dma_iccm_stall_any @[quasar.scala 128:18] - dec.io.dec_dma.tlu_dma.dma_dccm_stall_any <= dma_ctrl.io.dec_dma.tlu_dma.dma_dccm_stall_any @[quasar.scala 128:18] - dma_ctrl.io.dec_dma.tlu_dma.dec_tlu_dma_qos_prty <= dec.io.dec_dma.tlu_dma.dec_tlu_dma_qos_prty @[quasar.scala 128:18] - dec.io.dec_dma.tlu_dma.dma_pmu_any_write <= dma_ctrl.io.dec_dma.tlu_dma.dma_pmu_any_write @[quasar.scala 128:18] - dec.io.dec_dma.tlu_dma.dma_pmu_any_read <= dma_ctrl.io.dec_dma.tlu_dma.dma_pmu_any_read @[quasar.scala 128:18] - dec.io.dec_dma.tlu_dma.dma_pmu_dccm_write <= dma_ctrl.io.dec_dma.tlu_dma.dma_pmu_dccm_write @[quasar.scala 128:18] - dec.io.dec_dma.tlu_dma.dma_pmu_dccm_read <= dma_ctrl.io.dec_dma.tlu_dma.dma_pmu_dccm_read @[quasar.scala 128:18] - dec.io.dec_dma.dctl_dma.dma_dccm_stall_any <= dma_ctrl.io.dec_dma.dctl_dma.dma_dccm_stall_any @[quasar.scala 128:18] - dec.io.lsu_fir_addr <= lsu.io.lsu_fir_addr @[quasar.scala 130:23] - dec.io.lsu_fir_error <= lsu.io.lsu_fir_error @[quasar.scala 131:24] - dec.io.lsu_trigger_match_m <= lsu.io.lsu_trigger_match_m @[quasar.scala 132:30] - dec.io.dec_dbg.dbg_dctl.dbg_cmd_wrdata <= dbg.io.dbg_dec.dbg_dctl.dbg_cmd_wrdata @[quasar.scala 133:18] - dec.io.dec_dbg.dbg_ib.dbg_cmd_addr <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_addr @[quasar.scala 133:18] - dec.io.dec_dbg.dbg_ib.dbg_cmd_type <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_type @[quasar.scala 133:18] - dec.io.dec_dbg.dbg_ib.dbg_cmd_write <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_write @[quasar.scala 133:18] - dec.io.dec_dbg.dbg_ib.dbg_cmd_valid <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_valid @[quasar.scala 133:18] - dec.io.lsu_idle_any <= lsu.io.lsu_idle_any @[quasar.scala 134:23] - dec.io.lsu_error_pkt_r.bits.addr <= lsu.io.lsu_error_pkt_r.bits.addr @[quasar.scala 135:26] - dec.io.lsu_error_pkt_r.bits.mscause <= lsu.io.lsu_error_pkt_r.bits.mscause @[quasar.scala 135:26] - dec.io.lsu_error_pkt_r.bits.exc_type <= lsu.io.lsu_error_pkt_r.bits.exc_type @[quasar.scala 135:26] - dec.io.lsu_error_pkt_r.bits.inst_type <= lsu.io.lsu_error_pkt_r.bits.inst_type @[quasar.scala 135:26] - dec.io.lsu_error_pkt_r.bits.single_ecc_error <= lsu.io.lsu_error_pkt_r.bits.single_ecc_error @[quasar.scala 135:26] - dec.io.lsu_error_pkt_r.valid <= lsu.io.lsu_error_pkt_r.valid @[quasar.scala 135:26] - dec.io.lsu_single_ecc_error_incr <= lsu.io.lsu_single_ecc_error_incr @[quasar.scala 136:36] - dec.io.exu_div_result <= exu.io.exu_div_result @[quasar.scala 137:25] - dec.io.exu_div_wren <= exu.io.exu_div_wren @[quasar.scala 138:23] - dec.io.lsu_result_m <= lsu.io.lsu_result_m @[quasar.scala 139:23] - dec.io.lsu_result_corr_r <= lsu.io.lsu_result_corr_r @[quasar.scala 140:28] - dec.io.lsu_load_stall_any <= lsu.io.lsu_load_stall_any @[quasar.scala 141:29] - dec.io.lsu_store_stall_any <= lsu.io.lsu_store_stall_any @[quasar.scala 142:30] - dec.io.iccm_dma_sb_error <= ifu.io.iccm_dma_sb_error @[quasar.scala 143:28] - dec.io.exu_flush_final <= exu.io.exu_flush_final @[quasar.scala 144:26] - dec.io.soft_int <= io.soft_int @[quasar.scala 146:19] - dec.io.dbg_halt_req <= dbg.io.dbg_halt_req @[quasar.scala 147:23] - dec.io.dbg_resume_req <= dbg.io.dbg_resume_req @[quasar.scala 148:25] - dec.io.exu_i0_br_way_r <= exu.io.exu_bp.exu_i0_br_way_r @[quasar.scala 149:26] - dec.io.timer_int <= io.timer_int @[quasar.scala 150:20] - dec.io.scan_mode <= io.scan_mode @[quasar.scala 151:20] - exu.io.dec_exu.gpr_exu.gpr_i0_rs2_d <= dec.io.dec_exu.gpr_exu.gpr_i0_rs2_d @[quasar.scala 154:18] - exu.io.dec_exu.gpr_exu.gpr_i0_rs1_d <= dec.io.dec_exu.gpr_exu.gpr_i0_rs1_d @[quasar.scala 154:18] - exu.io.dec_exu.ib_exu.dec_debug_wdata_rs1_d <= dec.io.dec_exu.ib_exu.dec_debug_wdata_rs1_d @[quasar.scala 154:18] - exu.io.dec_exu.ib_exu.dec_i0_pc_d <= dec.io.dec_exu.ib_exu.dec_i0_pc_d @[quasar.scala 154:18] - dec.io.dec_exu.tlu_exu.exu_npc_r <= exu.io.dec_exu.tlu_exu.exu_npc_r @[quasar.scala 154:18] - dec.io.dec_exu.tlu_exu.exu_pmu_i0_pc4 <= exu.io.dec_exu.tlu_exu.exu_pmu_i0_pc4 @[quasar.scala 154:18] - dec.io.dec_exu.tlu_exu.exu_pmu_i0_br_ataken <= exu.io.dec_exu.tlu_exu.exu_pmu_i0_br_ataken @[quasar.scala 154:18] - dec.io.dec_exu.tlu_exu.exu_pmu_i0_br_misp <= exu.io.dec_exu.tlu_exu.exu_pmu_i0_br_misp @[quasar.scala 154:18] - dec.io.dec_exu.tlu_exu.exu_i0_br_middle_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_middle_r @[quasar.scala 154:18] - dec.io.dec_exu.tlu_exu.exu_i0_br_mp_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_mp_r @[quasar.scala 154:18] - dec.io.dec_exu.tlu_exu.exu_i0_br_valid_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_valid_r @[quasar.scala 154:18] - dec.io.dec_exu.tlu_exu.exu_i0_br_index_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_index_r @[quasar.scala 154:18] - dec.io.dec_exu.tlu_exu.exu_i0_br_start_error_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_start_error_r @[quasar.scala 154:18] - dec.io.dec_exu.tlu_exu.exu_i0_br_error_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_error_r @[quasar.scala 154:18] - dec.io.dec_exu.tlu_exu.exu_i0_br_hist_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_hist_r @[quasar.scala 154:18] - exu.io.dec_exu.tlu_exu.dec_tlu_flush_path_r <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_path_r @[quasar.scala 154:18] - exu.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[quasar.scala 154:18] - exu.io.dec_exu.tlu_exu.dec_tlu_meihap <= dec.io.dec_exu.tlu_exu.dec_tlu_meihap @[quasar.scala 154:18] - dec.io.dec_exu.decode_exu.exu_csr_rs1_x <= exu.io.dec_exu.decode_exu.exu_csr_rs1_x @[quasar.scala 154:18] - dec.io.dec_exu.decode_exu.exu_i0_result_x <= exu.io.dec_exu.decode_exu.exu_i0_result_x @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.dec_extint_stall <= dec.io.dec_exu.decode_exu.dec_extint_stall @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.pred_correct_npc_x <= dec.io.dec_exu.decode_exu.pred_correct_npc_x @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.mul_p.bits.bfp <= dec.io.dec_exu.decode_exu.mul_p.bits.bfp @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.mul_p.bits.crc32c_w <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32c_w @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.mul_p.bits.crc32c_h <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32c_h @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.mul_p.bits.crc32c_b <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32c_b @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.mul_p.bits.crc32_w <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32_w @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.mul_p.bits.crc32_h <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32_h @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.mul_p.bits.crc32_b <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32_b @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.mul_p.bits.unshfl <= dec.io.dec_exu.decode_exu.mul_p.bits.unshfl @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.mul_p.bits.shfl <= dec.io.dec_exu.decode_exu.mul_p.bits.shfl @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.mul_p.bits.grev <= dec.io.dec_exu.decode_exu.mul_p.bits.grev @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.mul_p.bits.clmulr <= dec.io.dec_exu.decode_exu.mul_p.bits.clmulr @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.mul_p.bits.clmulh <= dec.io.dec_exu.decode_exu.mul_p.bits.clmulh @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.mul_p.bits.clmul <= dec.io.dec_exu.decode_exu.mul_p.bits.clmul @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.mul_p.bits.bdep <= dec.io.dec_exu.decode_exu.mul_p.bits.bdep @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.mul_p.bits.bext <= dec.io.dec_exu.decode_exu.mul_p.bits.bext @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.mul_p.bits.low <= dec.io.dec_exu.decode_exu.mul_p.bits.low @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.mul_p.bits.rs2_sign <= dec.io.dec_exu.decode_exu.mul_p.bits.rs2_sign @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.mul_p.bits.rs1_sign <= dec.io.dec_exu.decode_exu.mul_p.bits.rs1_sign @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.mul_p.valid <= dec.io.dec_exu.decode_exu.mul_p.valid @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.dec_i0_select_pc_d <= dec.io.dec_exu.decode_exu.dec_i0_select_pc_d @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.dec_i0_rs2_bypass_data_d <= dec.io.dec_exu.decode_exu.dec_i0_rs2_bypass_data_d @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.dec_i0_rs1_bypass_data_d <= dec.io.dec_exu.decode_exu.dec_i0_rs1_bypass_data_d @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.dec_i0_immed_d <= dec.io.dec_exu.decode_exu.dec_i0_immed_d @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.dec_i0_rs2_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs2_en_d @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.dec_i0_rs1_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs1_en_d @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.i0_predict_btag_d <= dec.io.dec_exu.decode_exu.i0_predict_btag_d @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.i0_predict_index_d <= dec.io.dec_exu.decode_exu.i0_predict_index_d @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.i0_predict_fghr_d <= dec.io.dec_exu.decode_exu.i0_predict_fghr_d @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.way <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.way @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pja <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pja @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pret <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pret @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pcall <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pcall @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.prett <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.prett @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_start_error <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_start_error @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_error <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_error @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.toffset <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.toffset @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.hist <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.hist @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pc4 <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pc4 @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.boffset <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.boffset @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.ataken <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.ataken @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.misp <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.misp @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.valid <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.valid @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.i0_ap.csr_imm <= dec.io.dec_exu.decode_exu.i0_ap.csr_imm @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.i0_ap.csr_write <= dec.io.dec_exu.decode_exu.i0_ap.csr_write @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.i0_ap.predict_nt <= dec.io.dec_exu.decode_exu.i0_ap.predict_nt @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.i0_ap.predict_t <= dec.io.dec_exu.decode_exu.i0_ap.predict_t @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.i0_ap.jal <= dec.io.dec_exu.decode_exu.i0_ap.jal @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.i0_ap.unsign <= dec.io.dec_exu.decode_exu.i0_ap.unsign @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.i0_ap.slt <= dec.io.dec_exu.decode_exu.i0_ap.slt @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.i0_ap.sub <= dec.io.dec_exu.decode_exu.i0_ap.sub @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.i0_ap.add <= dec.io.dec_exu.decode_exu.i0_ap.add @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.i0_ap.bge <= dec.io.dec_exu.decode_exu.i0_ap.bge @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.i0_ap.blt <= dec.io.dec_exu.decode_exu.i0_ap.blt @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.i0_ap.bne <= dec.io.dec_exu.decode_exu.i0_ap.bne @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.i0_ap.beq <= dec.io.dec_exu.decode_exu.i0_ap.beq @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.i0_ap.sra <= dec.io.dec_exu.decode_exu.i0_ap.sra @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.i0_ap.srl <= dec.io.dec_exu.decode_exu.i0_ap.srl @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.i0_ap.sll <= dec.io.dec_exu.decode_exu.i0_ap.sll @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.i0_ap.lxor <= dec.io.dec_exu.decode_exu.i0_ap.lxor @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.i0_ap.lor <= dec.io.dec_exu.decode_exu.i0_ap.lor @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.i0_ap.land <= dec.io.dec_exu.decode_exu.i0_ap.land @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.dec_ctl_en <= dec.io.dec_exu.decode_exu.dec_ctl_en @[quasar.scala 154:18] - exu.io.dec_exu.decode_exu.dec_data_en <= dec.io.dec_exu.decode_exu.dec_data_en @[quasar.scala 154:18] - exu.io.dec_exu.dec_div.dec_div_cancel <= dec.io.dec_exu.dec_div.dec_div_cancel @[quasar.scala 154:18] - exu.io.dec_exu.dec_div.div_p.bits.rem <= dec.io.dec_exu.dec_div.div_p.bits.rem @[quasar.scala 154:18] - exu.io.dec_exu.dec_div.div_p.bits.unsign <= dec.io.dec_exu.dec_div.div_p.bits.unsign @[quasar.scala 154:18] - exu.io.dec_exu.dec_div.div_p.valid <= dec.io.dec_exu.dec_div.div_p.valid @[quasar.scala 154:18] - dec.io.dec_exu.dec_alu.exu_i0_pc_x <= exu.io.dec_exu.dec_alu.exu_i0_pc_x @[quasar.scala 154:18] - exu.io.dec_exu.dec_alu.dec_i0_br_immed_d <= dec.io.dec_exu.dec_alu.dec_i0_br_immed_d @[quasar.scala 154:18] - exu.io.dec_exu.dec_alu.dec_csr_ren_d <= dec.io.dec_exu.dec_alu.dec_csr_ren_d @[quasar.scala 154:18] - exu.io.dec_exu.dec_alu.dec_i0_alu_decode_d <= dec.io.dec_exu.dec_alu.dec_i0_alu_decode_d @[quasar.scala 154:18] - exu.reset <= io.core_rst_l @[quasar.scala 155:13] - exu.io.scan_mode <= io.scan_mode @[quasar.scala 156:20] - exu.io.dbg_cmd_wrdata <= dbg.io.dbg_dec.dbg_dctl.dbg_cmd_wrdata @[quasar.scala 157:25] - lsu.reset <= io.core_rst_l @[quasar.scala 160:13] - lsu.io.clk_override <= dec.io.dec_tlu_lsu_clk_override @[quasar.scala 161:23] - lsu.io.dec_tlu_flush_lower_r <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[quasar.scala 162:32] - lsu.io.dec_tlu_i0_kill_writeb_r <= dec.io.dec_tlu_i0_kill_writeb_r @[quasar.scala 163:35] - lsu.io.dec_tlu_force_halt <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt @[quasar.scala 164:29] - lsu.io.dec_tlu_core_ecc_disable <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable @[quasar.scala 165:35] - lsu.io.lsu_exu.exu_lsu_rs2_d <= exu.io.lsu_exu.exu_lsu_rs2_d @[quasar.scala 166:18] - lsu.io.lsu_exu.exu_lsu_rs1_d <= exu.io.lsu_exu.exu_lsu_rs1_d @[quasar.scala 166:18] - lsu.io.dec_lsu_offset_d <= dec.io.dec_lsu_offset_d @[quasar.scala 167:27] - lsu.io.lsu_p.bits.store_data_bypass_m <= dec.io.lsu_p.bits.store_data_bypass_m @[quasar.scala 168:16] - lsu.io.lsu_p.bits.load_ldst_bypass_d <= dec.io.lsu_p.bits.load_ldst_bypass_d @[quasar.scala 168:16] - lsu.io.lsu_p.bits.store_data_bypass_d <= dec.io.lsu_p.bits.store_data_bypass_d @[quasar.scala 168:16] - lsu.io.lsu_p.bits.dma <= dec.io.lsu_p.bits.dma @[quasar.scala 168:16] - lsu.io.lsu_p.bits.unsign <= dec.io.lsu_p.bits.unsign @[quasar.scala 168:16] - lsu.io.lsu_p.bits.store <= dec.io.lsu_p.bits.store @[quasar.scala 168:16] - lsu.io.lsu_p.bits.load <= dec.io.lsu_p.bits.load @[quasar.scala 168:16] - lsu.io.lsu_p.bits.dword <= dec.io.lsu_p.bits.dword @[quasar.scala 168:16] - lsu.io.lsu_p.bits.word <= dec.io.lsu_p.bits.word @[quasar.scala 168:16] - lsu.io.lsu_p.bits.half <= dec.io.lsu_p.bits.half @[quasar.scala 168:16] - lsu.io.lsu_p.bits.by <= dec.io.lsu_p.bits.by @[quasar.scala 168:16] - lsu.io.lsu_p.bits.fast_int <= dec.io.lsu_p.bits.fast_int @[quasar.scala 168:16] - lsu.io.lsu_p.valid <= dec.io.lsu_p.valid @[quasar.scala 168:16] - lsu.io.dec_lsu_valid_raw_d <= dec.io.dec_lsu_valid_raw_d @[quasar.scala 169:30] - lsu.io.dec_tlu_mrac_ff <= dec.io.ifu_dec.dec_ifc.dec_tlu_mrac_ff @[quasar.scala 170:26] - lsu.io.trigger_pkt_any[0].tdata2 <= dec.io.trigger_pkt_any[0].tdata2 @[quasar.scala 171:26] - lsu.io.trigger_pkt_any[0].m <= dec.io.trigger_pkt_any[0].m @[quasar.scala 171:26] - lsu.io.trigger_pkt_any[0].execute <= dec.io.trigger_pkt_any[0].execute @[quasar.scala 171:26] - lsu.io.trigger_pkt_any[0].load <= dec.io.trigger_pkt_any[0].load @[quasar.scala 171:26] - lsu.io.trigger_pkt_any[0].store <= dec.io.trigger_pkt_any[0].store @[quasar.scala 171:26] - lsu.io.trigger_pkt_any[0].match_pkt <= dec.io.trigger_pkt_any[0].match_pkt @[quasar.scala 171:26] - lsu.io.trigger_pkt_any[0].select <= dec.io.trigger_pkt_any[0].select @[quasar.scala 171:26] - lsu.io.trigger_pkt_any[1].tdata2 <= dec.io.trigger_pkt_any[1].tdata2 @[quasar.scala 171:26] - lsu.io.trigger_pkt_any[1].m <= dec.io.trigger_pkt_any[1].m @[quasar.scala 171:26] - lsu.io.trigger_pkt_any[1].execute <= dec.io.trigger_pkt_any[1].execute @[quasar.scala 171:26] - lsu.io.trigger_pkt_any[1].load <= dec.io.trigger_pkt_any[1].load @[quasar.scala 171:26] - lsu.io.trigger_pkt_any[1].store <= dec.io.trigger_pkt_any[1].store @[quasar.scala 171:26] - lsu.io.trigger_pkt_any[1].match_pkt <= dec.io.trigger_pkt_any[1].match_pkt @[quasar.scala 171:26] - lsu.io.trigger_pkt_any[1].select <= dec.io.trigger_pkt_any[1].select @[quasar.scala 171:26] - lsu.io.trigger_pkt_any[2].tdata2 <= dec.io.trigger_pkt_any[2].tdata2 @[quasar.scala 171:26] - lsu.io.trigger_pkt_any[2].m <= dec.io.trigger_pkt_any[2].m @[quasar.scala 171:26] - lsu.io.trigger_pkt_any[2].execute <= dec.io.trigger_pkt_any[2].execute @[quasar.scala 171:26] - lsu.io.trigger_pkt_any[2].load <= dec.io.trigger_pkt_any[2].load @[quasar.scala 171:26] - lsu.io.trigger_pkt_any[2].store <= dec.io.trigger_pkt_any[2].store @[quasar.scala 171:26] - lsu.io.trigger_pkt_any[2].match_pkt <= dec.io.trigger_pkt_any[2].match_pkt @[quasar.scala 171:26] - lsu.io.trigger_pkt_any[2].select <= dec.io.trigger_pkt_any[2].select @[quasar.scala 171:26] - lsu.io.trigger_pkt_any[3].tdata2 <= dec.io.trigger_pkt_any[3].tdata2 @[quasar.scala 171:26] - lsu.io.trigger_pkt_any[3].m <= dec.io.trigger_pkt_any[3].m @[quasar.scala 171:26] - lsu.io.trigger_pkt_any[3].execute <= dec.io.trigger_pkt_any[3].execute @[quasar.scala 171:26] - lsu.io.trigger_pkt_any[3].load <= dec.io.trigger_pkt_any[3].load @[quasar.scala 171:26] - lsu.io.trigger_pkt_any[3].store <= dec.io.trigger_pkt_any[3].store @[quasar.scala 171:26] - lsu.io.trigger_pkt_any[3].match_pkt <= dec.io.trigger_pkt_any[3].match_pkt @[quasar.scala 171:26] - lsu.io.trigger_pkt_any[3].select <= dec.io.trigger_pkt_any[3].select @[quasar.scala 171:26] - lsu.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[quasar.scala 173:25] - lsu.io.lsu_dma.dma_mem_tag <= dma_ctrl.io.lsu_dma.dma_mem_tag @[quasar.scala 174:18] - dma_ctrl.io.lsu_dma.dccm_ready <= lsu.io.lsu_dma.dccm_ready @[quasar.scala 174:18] - dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_rdata <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_rdata @[quasar.scala 174:18] - dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag @[quasar.scala 174:18] - dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error @[quasar.scala 174:18] - dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid @[quasar.scala 174:18] - lsu.io.lsu_dma.dma_dccm_ctl.dma_mem_wdata <= dma_ctrl.io.lsu_dma.dma_dccm_ctl.dma_mem_wdata @[quasar.scala 174:18] - lsu.io.lsu_dma.dma_dccm_ctl.dma_mem_addr <= dma_ctrl.io.lsu_dma.dma_dccm_ctl.dma_mem_addr @[quasar.scala 174:18] - lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_wdata <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_wdata @[quasar.scala 174:18] - lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_write <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_write @[quasar.scala 174:18] - lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_sz <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_sz @[quasar.scala 174:18] - lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_addr <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_addr @[quasar.scala 174:18] - lsu.io.lsu_dma.dma_lsc_ctl.dma_dccm_req <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_dccm_req @[quasar.scala 174:18] - lsu.io.scan_mode <= io.scan_mode @[quasar.scala 175:20] - lsu.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 176:19] - dbg.reset <= io.core_rst_l @[quasar.scala 179:13] - node _T_8 = mux(dma_ctrl.io.dma_dbg_cmd_done, dma_ctrl.io.dma_dbg_rddata, dec.io.dec_dbg_rddata) @[quasar.scala 180:32] - dbg.io.core_dbg_rddata <= _T_8 @[quasar.scala 180:26] - node _T_9 = or(dma_ctrl.io.dma_dbg_cmd_done, dec.io.dec_dbg_cmd_done) @[quasar.scala 181:60] - dbg.io.core_dbg_cmd_done <= _T_9 @[quasar.scala 181:28] - node _T_10 = or(dma_ctrl.io.dma_dbg_cmd_fail, dec.io.dec_dbg_cmd_fail) @[quasar.scala 182:60] - dbg.io.core_dbg_cmd_fail <= _T_10 @[quasar.scala 182:28] - dbg.io.dec_tlu_debug_mode <= dec.io.dec_tlu_debug_mode @[quasar.scala 183:29] - dbg.io.dec_tlu_dbg_halted <= dec.io.dec_tlu_dbg_halted @[quasar.scala 184:29] - dbg.io.dec_tlu_mpc_halted_only <= dec.io.dec_tlu_mpc_halted_only @[quasar.scala 185:34] - dbg.io.dec_tlu_resume_ack <= dec.io.dec_tlu_resume_ack @[quasar.scala 186:29] - dbg.io.dmi_reg_en <= io.dmi_reg_en @[quasar.scala 187:21] - dbg.io.dmi_reg_addr <= io.dmi_reg_addr @[quasar.scala 188:23] - dbg.io.dmi_reg_wr_en <= io.dmi_reg_wr_en @[quasar.scala 189:24] - dbg.io.dmi_reg_wdata <= io.dmi_reg_wdata @[quasar.scala 190:24] - dbg.io.dbg_bus_clk_en <= io.dbg_bus_clk_en @[quasar.scala 191:25] - node _T_11 = asUInt(io.dbg_rst_l) @[quasar.scala 192:42] - dbg.io.dbg_rst_l <= _T_11 @[quasar.scala 192:20] - dbg.io.clk_override <= dec.io.dec_tlu_misc_clk_override @[quasar.scala 193:23] - dbg.io.scan_mode <= io.scan_mode @[quasar.scala 194:20] - dma_ctrl.reset <= io.core_rst_l @[quasar.scala 198:18] - dma_ctrl.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 199:24] - dma_ctrl.io.dma_bus_clk_en <= io.dma_bus_clk_en @[quasar.scala 200:30] - dma_ctrl.io.clk_override <= dec.io.dec_tlu_misc_clk_override @[quasar.scala 201:28] - dma_ctrl.io.scan_mode <= io.scan_mode @[quasar.scala 202:25] - dma_ctrl.io.dbg_dma.dbg_dctl.dbg_cmd_wrdata <= dbg.io.dbg_dma.dbg_dctl.dbg_cmd_wrdata @[quasar.scala 203:23] - dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_addr <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_addr @[quasar.scala 203:23] - dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_type <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_type @[quasar.scala 203:23] - dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_write <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_write @[quasar.scala 203:23] - dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_valid <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_valid @[quasar.scala 203:23] - dbg.io.dbg_dma_io.dma_dbg_ready <= dma_ctrl.io.dbg_dma_io.dma_dbg_ready @[quasar.scala 204:26] - dma_ctrl.io.dbg_dma_io.dbg_dma_bubble <= dbg.io.dbg_dma_io.dbg_dma_bubble @[quasar.scala 204:26] - dma_ctrl.io.dbg_cmd_size <= dbg.io.dbg_cmd_size @[quasar.scala 205:28] - dma_ctrl.io.iccm_dma_rvalid <= ifu.io.iccm_dma_rvalid @[quasar.scala 206:31] - dma_ctrl.io.iccm_dma_rtag <= ifu.io.iccm_dma_rtag @[quasar.scala 207:29] - dma_ctrl.io.iccm_dma_rdata <= ifu.io.iccm_dma_rdata @[quasar.scala 208:30] - dma_ctrl.io.iccm_ready <= ifu.io.iccm_ready @[quasar.scala 209:26] - dma_ctrl.io.iccm_dma_ecc_error <= ifu.io.iccm_dma_ecc_error @[quasar.scala 210:34] - pic_ctrl_inst.io.scan_mode <= io.scan_mode @[quasar.scala 213:30] - pic_ctrl_inst.reset <= io.core_rst_l @[quasar.scala 214:23] - pic_ctrl_inst.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 215:29] - pic_ctrl_inst.io.active_clk <= rvclkhdr_1.io.l1clk @[quasar.scala 216:31] - pic_ctrl_inst.io.clk_override <= dec.io.dec_tlu_pic_clk_override @[quasar.scala 217:33] - pic_ctrl_inst.io.extintsrc_req <= io.extintsrc_req @[quasar.scala 218:34] - lsu.io.lsu_pic.picm_rd_data <= pic_ctrl_inst.io.lsu_pic.picm_rd_data @[quasar.scala 219:28] - pic_ctrl_inst.io.lsu_pic.picm_wr_data <= lsu.io.lsu_pic.picm_wr_data @[quasar.scala 219:28] - pic_ctrl_inst.io.lsu_pic.picm_wraddr <= lsu.io.lsu_pic.picm_wraddr @[quasar.scala 219:28] - pic_ctrl_inst.io.lsu_pic.picm_rdaddr <= lsu.io.lsu_pic.picm_rdaddr @[quasar.scala 219:28] - pic_ctrl_inst.io.lsu_pic.picm_mken <= lsu.io.lsu_pic.picm_mken @[quasar.scala 219:28] - pic_ctrl_inst.io.lsu_pic.picm_rden <= lsu.io.lsu_pic.picm_rden @[quasar.scala 219:28] - pic_ctrl_inst.io.lsu_pic.picm_wren <= lsu.io.lsu_pic.picm_wren @[quasar.scala 219:28] - dec.io.dec_pic.mexintpend <= pic_ctrl_inst.io.dec_pic.mexintpend @[quasar.scala 220:28] - pic_ctrl_inst.io.dec_pic.dec_tlu_meipt <= dec.io.dec_pic.dec_tlu_meipt @[quasar.scala 220:28] - pic_ctrl_inst.io.dec_pic.dec_tlu_meicurpl <= dec.io.dec_pic.dec_tlu_meicurpl @[quasar.scala 220:28] - dec.io.dec_pic.mhwakeup <= pic_ctrl_inst.io.dec_pic.mhwakeup @[quasar.scala 220:28] - dec.io.dec_pic.pic_pl <= pic_ctrl_inst.io.dec_pic.pic_pl @[quasar.scala 220:28] - dec.io.dec_pic.pic_claimid <= pic_ctrl_inst.io.dec_pic.pic_claimid @[quasar.scala 220:28] - io.rv_trace_pkt.rv_i_tval_ip <= dec.io.rv_trace_pkt.rv_i_tval_ip @[quasar.scala 222:19] - io.rv_trace_pkt.rv_i_interrupt_ip <= dec.io.rv_trace_pkt.rv_i_interrupt_ip @[quasar.scala 222:19] - io.rv_trace_pkt.rv_i_ecause_ip <= dec.io.rv_trace_pkt.rv_i_ecause_ip @[quasar.scala 222:19] - io.rv_trace_pkt.rv_i_exception_ip <= dec.io.rv_trace_pkt.rv_i_exception_ip @[quasar.scala 222:19] - io.rv_trace_pkt.rv_i_address_ip <= dec.io.rv_trace_pkt.rv_i_address_ip @[quasar.scala 222:19] - io.rv_trace_pkt.rv_i_insn_ip <= dec.io.rv_trace_pkt.rv_i_insn_ip @[quasar.scala 222:19] - io.rv_trace_pkt.rv_i_valid_ip <= dec.io.rv_trace_pkt.rv_i_valid_ip @[quasar.scala 222:19] - io.dccm_clk_override <= dec.io.dec_tlu_dccm_clk_override @[quasar.scala 225:24] - io.icm_clk_override <= dec.io.dec_tlu_icm_clk_override @[quasar.scala 226:23] - io.dec_tlu_core_ecc_disable <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable @[quasar.scala 227:31] - io.o_cpu_halt_ack <= dec.io.o_cpu_halt_ack @[quasar.scala 228:21] - io.o_cpu_halt_status <= dec.io.o_cpu_halt_status @[quasar.scala 229:24] - io.o_cpu_run_ack <= dec.io.o_cpu_run_ack @[quasar.scala 230:20] - io.o_debug_mode_status <= dec.io.o_debug_mode_status @[quasar.scala 231:26] - io.mpc_debug_halt_ack <= dec.io.mpc_debug_halt_ack @[quasar.scala 232:25] - io.mpc_debug_run_ack <= dec.io.mpc_debug_run_ack @[quasar.scala 233:24] - io.debug_brkpt_status <= dec.io.debug_brkpt_status @[quasar.scala 234:25] - io.dec_tlu_perfcnt0 <= dec.io.dec_tlu_perfcnt0 @[quasar.scala 235:23] - io.dec_tlu_perfcnt1 <= dec.io.dec_tlu_perfcnt1 @[quasar.scala 236:23] - io.dec_tlu_perfcnt2 <= dec.io.dec_tlu_perfcnt2 @[quasar.scala 237:23] - io.dec_tlu_perfcnt3 <= dec.io.dec_tlu_perfcnt3 @[quasar.scala 238:23] - io.dmi_reg_rdata <= dbg.io.dmi_reg_rdata @[quasar.scala 239:20] - lsu.io.dccm.rd_data_hi <= io.dccm.rd_data_hi @[quasar.scala 242:11] - lsu.io.dccm.rd_data_lo <= io.dccm.rd_data_lo @[quasar.scala 242:11] - io.dccm.wr_data_hi <= lsu.io.dccm.wr_data_hi @[quasar.scala 242:11] - io.dccm.wr_data_lo <= lsu.io.dccm.wr_data_lo @[quasar.scala 242:11] - io.dccm.rd_addr_hi <= lsu.io.dccm.rd_addr_hi @[quasar.scala 242:11] - io.dccm.rd_addr_lo <= lsu.io.dccm.rd_addr_lo @[quasar.scala 242:11] - io.dccm.wr_addr_hi <= lsu.io.dccm.wr_addr_hi @[quasar.scala 242:11] - io.dccm.wr_addr_lo <= lsu.io.dccm.wr_addr_lo @[quasar.scala 242:11] - io.dccm.rden <= lsu.io.dccm.rden @[quasar.scala 242:11] - io.dccm.wren <= lsu.io.dccm.wren @[quasar.scala 242:11] - inst axi4_to_ahb of axi4_to_ahb @[quasar.scala 245:32] - axi4_to_ahb.clock <= clock - axi4_to_ahb.reset <= reset - inst axi4_to_ahb_1 of axi4_to_ahb_1 @[quasar.scala 246:33] - axi4_to_ahb_1.clock <= clock - axi4_to_ahb_1.reset <= reset - inst axi4_to_ahb_2 of axi4_to_ahb_2 @[quasar.scala 247:33] - axi4_to_ahb_2.clock <= clock - axi4_to_ahb_2.reset <= reset - inst ahb_to_axi4 of ahb_to_axi4 @[quasar.scala 248:33] - ahb_to_axi4.clock <= clock - ahb_to_axi4.reset <= reset - axi4_to_ahb_2.io.scan_mode <= io.scan_mode @[quasar.scala 250:34] - axi4_to_ahb_2.io.bus_clk_en <= io.lsu_bus_clk_en @[quasar.scala 251:35] - axi4_to_ahb_2.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 252:37] - lsu.io.axi.r.bits.last <= axi4_to_ahb_2.io.axi.r.bits.last @[quasar.scala 253:28] - lsu.io.axi.r.bits.resp <= axi4_to_ahb_2.io.axi.r.bits.resp @[quasar.scala 253:28] - lsu.io.axi.r.bits.data <= axi4_to_ahb_2.io.axi.r.bits.data @[quasar.scala 253:28] - lsu.io.axi.r.bits.id <= axi4_to_ahb_2.io.axi.r.bits.id @[quasar.scala 253:28] - lsu.io.axi.r.valid <= axi4_to_ahb_2.io.axi.r.valid @[quasar.scala 253:28] - axi4_to_ahb_2.io.axi.r.ready <= lsu.io.axi.r.ready @[quasar.scala 253:28] - axi4_to_ahb_2.io.axi.ar.bits.qos <= lsu.io.axi.ar.bits.qos @[quasar.scala 253:28] - axi4_to_ahb_2.io.axi.ar.bits.prot <= lsu.io.axi.ar.bits.prot @[quasar.scala 253:28] - axi4_to_ahb_2.io.axi.ar.bits.cache <= lsu.io.axi.ar.bits.cache @[quasar.scala 253:28] - axi4_to_ahb_2.io.axi.ar.bits.lock <= lsu.io.axi.ar.bits.lock @[quasar.scala 253:28] - axi4_to_ahb_2.io.axi.ar.bits.burst <= lsu.io.axi.ar.bits.burst @[quasar.scala 253:28] - axi4_to_ahb_2.io.axi.ar.bits.size <= lsu.io.axi.ar.bits.size @[quasar.scala 253:28] - axi4_to_ahb_2.io.axi.ar.bits.len <= lsu.io.axi.ar.bits.len @[quasar.scala 253:28] - axi4_to_ahb_2.io.axi.ar.bits.region <= lsu.io.axi.ar.bits.region @[quasar.scala 253:28] - axi4_to_ahb_2.io.axi.ar.bits.addr <= lsu.io.axi.ar.bits.addr @[quasar.scala 253:28] - axi4_to_ahb_2.io.axi.ar.bits.id <= lsu.io.axi.ar.bits.id @[quasar.scala 253:28] - axi4_to_ahb_2.io.axi.ar.valid <= lsu.io.axi.ar.valid @[quasar.scala 253:28] - lsu.io.axi.ar.ready <= axi4_to_ahb_2.io.axi.ar.ready @[quasar.scala 253:28] - lsu.io.axi.b.bits.id <= axi4_to_ahb_2.io.axi.b.bits.id @[quasar.scala 253:28] - lsu.io.axi.b.bits.resp <= axi4_to_ahb_2.io.axi.b.bits.resp @[quasar.scala 253:28] - lsu.io.axi.b.valid <= axi4_to_ahb_2.io.axi.b.valid @[quasar.scala 253:28] - axi4_to_ahb_2.io.axi.b.ready <= lsu.io.axi.b.ready @[quasar.scala 253:28] - axi4_to_ahb_2.io.axi.w.bits.last <= lsu.io.axi.w.bits.last @[quasar.scala 253:28] - axi4_to_ahb_2.io.axi.w.bits.strb <= lsu.io.axi.w.bits.strb @[quasar.scala 253:28] - axi4_to_ahb_2.io.axi.w.bits.data <= lsu.io.axi.w.bits.data @[quasar.scala 253:28] - axi4_to_ahb_2.io.axi.w.valid <= lsu.io.axi.w.valid @[quasar.scala 253:28] - lsu.io.axi.w.ready <= axi4_to_ahb_2.io.axi.w.ready @[quasar.scala 253:28] - axi4_to_ahb_2.io.axi.aw.bits.qos <= lsu.io.axi.aw.bits.qos @[quasar.scala 253:28] - axi4_to_ahb_2.io.axi.aw.bits.prot <= lsu.io.axi.aw.bits.prot @[quasar.scala 253:28] - axi4_to_ahb_2.io.axi.aw.bits.cache <= lsu.io.axi.aw.bits.cache @[quasar.scala 253:28] - axi4_to_ahb_2.io.axi.aw.bits.lock <= lsu.io.axi.aw.bits.lock @[quasar.scala 253:28] - axi4_to_ahb_2.io.axi.aw.bits.burst <= lsu.io.axi.aw.bits.burst @[quasar.scala 253:28] - axi4_to_ahb_2.io.axi.aw.bits.size <= lsu.io.axi.aw.bits.size @[quasar.scala 253:28] - axi4_to_ahb_2.io.axi.aw.bits.len <= lsu.io.axi.aw.bits.len @[quasar.scala 253:28] - axi4_to_ahb_2.io.axi.aw.bits.region <= lsu.io.axi.aw.bits.region @[quasar.scala 253:28] - axi4_to_ahb_2.io.axi.aw.bits.addr <= lsu.io.axi.aw.bits.addr @[quasar.scala 253:28] - axi4_to_ahb_2.io.axi.aw.bits.id <= lsu.io.axi.aw.bits.id @[quasar.scala 253:28] - axi4_to_ahb_2.io.axi.aw.valid <= lsu.io.axi.aw.valid @[quasar.scala 253:28] - lsu.io.axi.aw.ready <= axi4_to_ahb_2.io.axi.aw.ready @[quasar.scala 253:28] - io.lsu_ahb.out.hwdata <= axi4_to_ahb_2.io.ahb.out.hwdata @[quasar.scala 254:28] - io.lsu_ahb.out.hwrite <= axi4_to_ahb_2.io.ahb.out.hwrite @[quasar.scala 254:28] - io.lsu_ahb.out.htrans <= axi4_to_ahb_2.io.ahb.out.htrans @[quasar.scala 254:28] - io.lsu_ahb.out.hsize <= axi4_to_ahb_2.io.ahb.out.hsize @[quasar.scala 254:28] - io.lsu_ahb.out.hprot <= axi4_to_ahb_2.io.ahb.out.hprot @[quasar.scala 254:28] - io.lsu_ahb.out.hmastlock <= axi4_to_ahb_2.io.ahb.out.hmastlock @[quasar.scala 254:28] - io.lsu_ahb.out.hburst <= axi4_to_ahb_2.io.ahb.out.hburst @[quasar.scala 254:28] - io.lsu_ahb.out.haddr <= axi4_to_ahb_2.io.ahb.out.haddr @[quasar.scala 254:28] - axi4_to_ahb_2.io.ahb.in.hresp <= io.lsu_ahb.in.hresp @[quasar.scala 254:28] - axi4_to_ahb_2.io.ahb.in.hready <= io.lsu_ahb.in.hready @[quasar.scala 254:28] - axi4_to_ahb_2.io.ahb.in.hrdata <= io.lsu_ahb.in.hrdata @[quasar.scala 254:28] - axi4_to_ahb_1.io.scan_mode <= io.scan_mode @[quasar.scala 256:34] - axi4_to_ahb_1.io.bus_clk_en <= io.ifu_bus_clk_en @[quasar.scala 257:35] - axi4_to_ahb_1.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 258:37] - ifu.io.ifu.r.bits.last <= axi4_to_ahb_1.io.axi.r.bits.last @[quasar.scala 259:28] - ifu.io.ifu.r.bits.resp <= axi4_to_ahb_1.io.axi.r.bits.resp @[quasar.scala 259:28] - ifu.io.ifu.r.bits.data <= axi4_to_ahb_1.io.axi.r.bits.data @[quasar.scala 259:28] - ifu.io.ifu.r.bits.id <= axi4_to_ahb_1.io.axi.r.bits.id @[quasar.scala 259:28] - ifu.io.ifu.r.valid <= axi4_to_ahb_1.io.axi.r.valid @[quasar.scala 259:28] - axi4_to_ahb_1.io.axi.r.ready <= ifu.io.ifu.r.ready @[quasar.scala 259:28] - axi4_to_ahb_1.io.axi.ar.bits.qos <= ifu.io.ifu.ar.bits.qos @[quasar.scala 259:28] - axi4_to_ahb_1.io.axi.ar.bits.prot <= ifu.io.ifu.ar.bits.prot @[quasar.scala 259:28] - axi4_to_ahb_1.io.axi.ar.bits.cache <= ifu.io.ifu.ar.bits.cache @[quasar.scala 259:28] - axi4_to_ahb_1.io.axi.ar.bits.lock <= ifu.io.ifu.ar.bits.lock @[quasar.scala 259:28] - axi4_to_ahb_1.io.axi.ar.bits.burst <= ifu.io.ifu.ar.bits.burst @[quasar.scala 259:28] - axi4_to_ahb_1.io.axi.ar.bits.size <= ifu.io.ifu.ar.bits.size @[quasar.scala 259:28] - axi4_to_ahb_1.io.axi.ar.bits.len <= ifu.io.ifu.ar.bits.len @[quasar.scala 259:28] - axi4_to_ahb_1.io.axi.ar.bits.region <= ifu.io.ifu.ar.bits.region @[quasar.scala 259:28] - axi4_to_ahb_1.io.axi.ar.bits.addr <= ifu.io.ifu.ar.bits.addr @[quasar.scala 259:28] - axi4_to_ahb_1.io.axi.ar.bits.id <= ifu.io.ifu.ar.bits.id @[quasar.scala 259:28] - axi4_to_ahb_1.io.axi.ar.valid <= ifu.io.ifu.ar.valid @[quasar.scala 259:28] - ifu.io.ifu.ar.ready <= axi4_to_ahb_1.io.axi.ar.ready @[quasar.scala 259:28] - ifu.io.ifu.b.bits.id <= axi4_to_ahb_1.io.axi.b.bits.id @[quasar.scala 259:28] - ifu.io.ifu.b.bits.resp <= axi4_to_ahb_1.io.axi.b.bits.resp @[quasar.scala 259:28] - ifu.io.ifu.b.valid <= axi4_to_ahb_1.io.axi.b.valid @[quasar.scala 259:28] - axi4_to_ahb_1.io.axi.b.ready <= ifu.io.ifu.b.ready @[quasar.scala 259:28] - axi4_to_ahb_1.io.axi.w.bits.last <= ifu.io.ifu.w.bits.last @[quasar.scala 259:28] - axi4_to_ahb_1.io.axi.w.bits.strb <= ifu.io.ifu.w.bits.strb @[quasar.scala 259:28] - axi4_to_ahb_1.io.axi.w.bits.data <= ifu.io.ifu.w.bits.data @[quasar.scala 259:28] - axi4_to_ahb_1.io.axi.w.valid <= ifu.io.ifu.w.valid @[quasar.scala 259:28] - ifu.io.ifu.w.ready <= axi4_to_ahb_1.io.axi.w.ready @[quasar.scala 259:28] - axi4_to_ahb_1.io.axi.aw.bits.qos <= ifu.io.ifu.aw.bits.qos @[quasar.scala 259:28] - axi4_to_ahb_1.io.axi.aw.bits.prot <= ifu.io.ifu.aw.bits.prot @[quasar.scala 259:28] - axi4_to_ahb_1.io.axi.aw.bits.cache <= ifu.io.ifu.aw.bits.cache @[quasar.scala 259:28] - axi4_to_ahb_1.io.axi.aw.bits.lock <= ifu.io.ifu.aw.bits.lock @[quasar.scala 259:28] - axi4_to_ahb_1.io.axi.aw.bits.burst <= ifu.io.ifu.aw.bits.burst @[quasar.scala 259:28] - axi4_to_ahb_1.io.axi.aw.bits.size <= ifu.io.ifu.aw.bits.size @[quasar.scala 259:28] - axi4_to_ahb_1.io.axi.aw.bits.len <= ifu.io.ifu.aw.bits.len @[quasar.scala 259:28] - axi4_to_ahb_1.io.axi.aw.bits.region <= ifu.io.ifu.aw.bits.region @[quasar.scala 259:28] - axi4_to_ahb_1.io.axi.aw.bits.addr <= ifu.io.ifu.aw.bits.addr @[quasar.scala 259:28] - axi4_to_ahb_1.io.axi.aw.bits.id <= ifu.io.ifu.aw.bits.id @[quasar.scala 259:28] - axi4_to_ahb_1.io.axi.aw.valid <= ifu.io.ifu.aw.valid @[quasar.scala 259:28] - ifu.io.ifu.aw.ready <= axi4_to_ahb_1.io.axi.aw.ready @[quasar.scala 259:28] - io.ifu_ahb.out.hwdata <= axi4_to_ahb_1.io.ahb.out.hwdata @[quasar.scala 260:28] - io.ifu_ahb.out.hwrite <= axi4_to_ahb_1.io.ahb.out.hwrite @[quasar.scala 260:28] - io.ifu_ahb.out.htrans <= axi4_to_ahb_1.io.ahb.out.htrans @[quasar.scala 260:28] - io.ifu_ahb.out.hsize <= axi4_to_ahb_1.io.ahb.out.hsize @[quasar.scala 260:28] - io.ifu_ahb.out.hprot <= axi4_to_ahb_1.io.ahb.out.hprot @[quasar.scala 260:28] - io.ifu_ahb.out.hmastlock <= axi4_to_ahb_1.io.ahb.out.hmastlock @[quasar.scala 260:28] - io.ifu_ahb.out.hburst <= axi4_to_ahb_1.io.ahb.out.hburst @[quasar.scala 260:28] - io.ifu_ahb.out.haddr <= axi4_to_ahb_1.io.ahb.out.haddr @[quasar.scala 260:28] - axi4_to_ahb_1.io.ahb.in.hresp <= io.ifu_ahb.in.hresp @[quasar.scala 260:28] - axi4_to_ahb_1.io.ahb.in.hready <= io.ifu_ahb.in.hready @[quasar.scala 260:28] - axi4_to_ahb_1.io.ahb.in.hrdata <= io.ifu_ahb.in.hrdata @[quasar.scala 260:28] - axi4_to_ahb_1.io.axi.b.ready <= UInt<1>("h01") @[quasar.scala 261:36] - axi4_to_ahb.io.scan_mode <= io.scan_mode @[quasar.scala 263:33] - axi4_to_ahb.io.bus_clk_en <= io.dbg_bus_clk_en @[quasar.scala 264:34] - axi4_to_ahb.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 265:36] - dbg.io.sb_axi.r.bits.last <= axi4_to_ahb.io.axi.r.bits.last @[quasar.scala 266:27] - dbg.io.sb_axi.r.bits.resp <= axi4_to_ahb.io.axi.r.bits.resp @[quasar.scala 266:27] - dbg.io.sb_axi.r.bits.data <= axi4_to_ahb.io.axi.r.bits.data @[quasar.scala 266:27] - dbg.io.sb_axi.r.bits.id <= axi4_to_ahb.io.axi.r.bits.id @[quasar.scala 266:27] - dbg.io.sb_axi.r.valid <= axi4_to_ahb.io.axi.r.valid @[quasar.scala 266:27] - axi4_to_ahb.io.axi.r.ready <= dbg.io.sb_axi.r.ready @[quasar.scala 266:27] - axi4_to_ahb.io.axi.ar.bits.qos <= dbg.io.sb_axi.ar.bits.qos @[quasar.scala 266:27] - axi4_to_ahb.io.axi.ar.bits.prot <= dbg.io.sb_axi.ar.bits.prot @[quasar.scala 266:27] - axi4_to_ahb.io.axi.ar.bits.cache <= dbg.io.sb_axi.ar.bits.cache @[quasar.scala 266:27] - axi4_to_ahb.io.axi.ar.bits.lock <= dbg.io.sb_axi.ar.bits.lock @[quasar.scala 266:27] - axi4_to_ahb.io.axi.ar.bits.burst <= dbg.io.sb_axi.ar.bits.burst @[quasar.scala 266:27] - axi4_to_ahb.io.axi.ar.bits.size <= dbg.io.sb_axi.ar.bits.size @[quasar.scala 266:27] - axi4_to_ahb.io.axi.ar.bits.len <= dbg.io.sb_axi.ar.bits.len @[quasar.scala 266:27] - axi4_to_ahb.io.axi.ar.bits.region <= dbg.io.sb_axi.ar.bits.region @[quasar.scala 266:27] - axi4_to_ahb.io.axi.ar.bits.addr <= dbg.io.sb_axi.ar.bits.addr @[quasar.scala 266:27] - axi4_to_ahb.io.axi.ar.bits.id <= dbg.io.sb_axi.ar.bits.id @[quasar.scala 266:27] - axi4_to_ahb.io.axi.ar.valid <= dbg.io.sb_axi.ar.valid @[quasar.scala 266:27] - dbg.io.sb_axi.ar.ready <= axi4_to_ahb.io.axi.ar.ready @[quasar.scala 266:27] - dbg.io.sb_axi.b.bits.id <= axi4_to_ahb.io.axi.b.bits.id @[quasar.scala 266:27] - dbg.io.sb_axi.b.bits.resp <= axi4_to_ahb.io.axi.b.bits.resp @[quasar.scala 266:27] - dbg.io.sb_axi.b.valid <= axi4_to_ahb.io.axi.b.valid @[quasar.scala 266:27] - axi4_to_ahb.io.axi.b.ready <= dbg.io.sb_axi.b.ready @[quasar.scala 266:27] - axi4_to_ahb.io.axi.w.bits.last <= dbg.io.sb_axi.w.bits.last @[quasar.scala 266:27] - axi4_to_ahb.io.axi.w.bits.strb <= dbg.io.sb_axi.w.bits.strb @[quasar.scala 266:27] - axi4_to_ahb.io.axi.w.bits.data <= dbg.io.sb_axi.w.bits.data @[quasar.scala 266:27] - axi4_to_ahb.io.axi.w.valid <= dbg.io.sb_axi.w.valid @[quasar.scala 266:27] - dbg.io.sb_axi.w.ready <= axi4_to_ahb.io.axi.w.ready @[quasar.scala 266:27] - axi4_to_ahb.io.axi.aw.bits.qos <= dbg.io.sb_axi.aw.bits.qos @[quasar.scala 266:27] - axi4_to_ahb.io.axi.aw.bits.prot <= dbg.io.sb_axi.aw.bits.prot @[quasar.scala 266:27] - axi4_to_ahb.io.axi.aw.bits.cache <= dbg.io.sb_axi.aw.bits.cache @[quasar.scala 266:27] - axi4_to_ahb.io.axi.aw.bits.lock <= dbg.io.sb_axi.aw.bits.lock @[quasar.scala 266:27] - axi4_to_ahb.io.axi.aw.bits.burst <= dbg.io.sb_axi.aw.bits.burst @[quasar.scala 266:27] - axi4_to_ahb.io.axi.aw.bits.size <= dbg.io.sb_axi.aw.bits.size @[quasar.scala 266:27] - axi4_to_ahb.io.axi.aw.bits.len <= dbg.io.sb_axi.aw.bits.len @[quasar.scala 266:27] - axi4_to_ahb.io.axi.aw.bits.region <= dbg.io.sb_axi.aw.bits.region @[quasar.scala 266:27] - axi4_to_ahb.io.axi.aw.bits.addr <= dbg.io.sb_axi.aw.bits.addr @[quasar.scala 266:27] - axi4_to_ahb.io.axi.aw.bits.id <= dbg.io.sb_axi.aw.bits.id @[quasar.scala 266:27] - axi4_to_ahb.io.axi.aw.valid <= dbg.io.sb_axi.aw.valid @[quasar.scala 266:27] - dbg.io.sb_axi.aw.ready <= axi4_to_ahb.io.axi.aw.ready @[quasar.scala 266:27] - io.sb_ahb.out.hwdata <= axi4_to_ahb.io.ahb.out.hwdata @[quasar.scala 267:27] - io.sb_ahb.out.hwrite <= axi4_to_ahb.io.ahb.out.hwrite @[quasar.scala 267:27] - io.sb_ahb.out.htrans <= axi4_to_ahb.io.ahb.out.htrans @[quasar.scala 267:27] - io.sb_ahb.out.hsize <= axi4_to_ahb.io.ahb.out.hsize @[quasar.scala 267:27] - io.sb_ahb.out.hprot <= axi4_to_ahb.io.ahb.out.hprot @[quasar.scala 267:27] - io.sb_ahb.out.hmastlock <= axi4_to_ahb.io.ahb.out.hmastlock @[quasar.scala 267:27] - io.sb_ahb.out.hburst <= axi4_to_ahb.io.ahb.out.hburst @[quasar.scala 267:27] - io.sb_ahb.out.haddr <= axi4_to_ahb.io.ahb.out.haddr @[quasar.scala 267:27] - axi4_to_ahb.io.ahb.in.hresp <= io.sb_ahb.in.hresp @[quasar.scala 267:27] - axi4_to_ahb.io.ahb.in.hready <= io.sb_ahb.in.hready @[quasar.scala 267:27] - axi4_to_ahb.io.ahb.in.hrdata <= io.sb_ahb.in.hrdata @[quasar.scala 267:27] - ahb_to_axi4.io.scan_mode <= io.scan_mode @[quasar.scala 269:34] - ahb_to_axi4.io.bus_clk_en <= io.dma_bus_clk_en @[quasar.scala 270:35] - ahb_to_axi4.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 271:37] - ahb_to_axi4.io.axi.r.bits.last <= dma_ctrl.io.dma_axi.r.bits.last @[quasar.scala 272:28] - ahb_to_axi4.io.axi.r.bits.resp <= dma_ctrl.io.dma_axi.r.bits.resp @[quasar.scala 272:28] - ahb_to_axi4.io.axi.r.bits.data <= dma_ctrl.io.dma_axi.r.bits.data @[quasar.scala 272:28] - ahb_to_axi4.io.axi.r.bits.id <= dma_ctrl.io.dma_axi.r.bits.id @[quasar.scala 272:28] - ahb_to_axi4.io.axi.r.valid <= dma_ctrl.io.dma_axi.r.valid @[quasar.scala 272:28] - dma_ctrl.io.dma_axi.r.ready <= ahb_to_axi4.io.axi.r.ready @[quasar.scala 272:28] - dma_ctrl.io.dma_axi.ar.bits.qos <= ahb_to_axi4.io.axi.ar.bits.qos @[quasar.scala 272:28] - dma_ctrl.io.dma_axi.ar.bits.prot <= ahb_to_axi4.io.axi.ar.bits.prot @[quasar.scala 272:28] - dma_ctrl.io.dma_axi.ar.bits.cache <= ahb_to_axi4.io.axi.ar.bits.cache @[quasar.scala 272:28] - dma_ctrl.io.dma_axi.ar.bits.lock <= ahb_to_axi4.io.axi.ar.bits.lock @[quasar.scala 272:28] - dma_ctrl.io.dma_axi.ar.bits.burst <= ahb_to_axi4.io.axi.ar.bits.burst @[quasar.scala 272:28] - dma_ctrl.io.dma_axi.ar.bits.size <= ahb_to_axi4.io.axi.ar.bits.size @[quasar.scala 272:28] - dma_ctrl.io.dma_axi.ar.bits.len <= ahb_to_axi4.io.axi.ar.bits.len @[quasar.scala 272:28] - dma_ctrl.io.dma_axi.ar.bits.region <= ahb_to_axi4.io.axi.ar.bits.region @[quasar.scala 272:28] - dma_ctrl.io.dma_axi.ar.bits.addr <= ahb_to_axi4.io.axi.ar.bits.addr @[quasar.scala 272:28] - dma_ctrl.io.dma_axi.ar.bits.id <= ahb_to_axi4.io.axi.ar.bits.id @[quasar.scala 272:28] - dma_ctrl.io.dma_axi.ar.valid <= ahb_to_axi4.io.axi.ar.valid @[quasar.scala 272:28] - ahb_to_axi4.io.axi.ar.ready <= dma_ctrl.io.dma_axi.ar.ready @[quasar.scala 272:28] - ahb_to_axi4.io.axi.b.bits.id <= dma_ctrl.io.dma_axi.b.bits.id @[quasar.scala 272:28] - ahb_to_axi4.io.axi.b.bits.resp <= dma_ctrl.io.dma_axi.b.bits.resp @[quasar.scala 272:28] - ahb_to_axi4.io.axi.b.valid <= dma_ctrl.io.dma_axi.b.valid @[quasar.scala 272:28] - dma_ctrl.io.dma_axi.b.ready <= ahb_to_axi4.io.axi.b.ready @[quasar.scala 272:28] - dma_ctrl.io.dma_axi.w.bits.last <= ahb_to_axi4.io.axi.w.bits.last @[quasar.scala 272:28] - dma_ctrl.io.dma_axi.w.bits.strb <= ahb_to_axi4.io.axi.w.bits.strb @[quasar.scala 272:28] - dma_ctrl.io.dma_axi.w.bits.data <= ahb_to_axi4.io.axi.w.bits.data @[quasar.scala 272:28] - dma_ctrl.io.dma_axi.w.valid <= ahb_to_axi4.io.axi.w.valid @[quasar.scala 272:28] - ahb_to_axi4.io.axi.w.ready <= dma_ctrl.io.dma_axi.w.ready @[quasar.scala 272:28] - dma_ctrl.io.dma_axi.aw.bits.qos <= ahb_to_axi4.io.axi.aw.bits.qos @[quasar.scala 272:28] - dma_ctrl.io.dma_axi.aw.bits.prot <= ahb_to_axi4.io.axi.aw.bits.prot @[quasar.scala 272:28] - dma_ctrl.io.dma_axi.aw.bits.cache <= ahb_to_axi4.io.axi.aw.bits.cache @[quasar.scala 272:28] - dma_ctrl.io.dma_axi.aw.bits.lock <= ahb_to_axi4.io.axi.aw.bits.lock @[quasar.scala 272:28] - dma_ctrl.io.dma_axi.aw.bits.burst <= ahb_to_axi4.io.axi.aw.bits.burst @[quasar.scala 272:28] - dma_ctrl.io.dma_axi.aw.bits.size <= ahb_to_axi4.io.axi.aw.bits.size @[quasar.scala 272:28] - dma_ctrl.io.dma_axi.aw.bits.len <= ahb_to_axi4.io.axi.aw.bits.len @[quasar.scala 272:28] - dma_ctrl.io.dma_axi.aw.bits.region <= ahb_to_axi4.io.axi.aw.bits.region @[quasar.scala 272:28] - dma_ctrl.io.dma_axi.aw.bits.addr <= ahb_to_axi4.io.axi.aw.bits.addr @[quasar.scala 272:28] - dma_ctrl.io.dma_axi.aw.bits.id <= ahb_to_axi4.io.axi.aw.bits.id @[quasar.scala 272:28] - dma_ctrl.io.dma_axi.aw.valid <= ahb_to_axi4.io.axi.aw.valid @[quasar.scala 272:28] - ahb_to_axi4.io.axi.aw.ready <= dma_ctrl.io.dma_axi.aw.ready @[quasar.scala 272:28] - ahb_to_axi4.io.ahb.hreadyin <= io.dma_ahb.hreadyin @[quasar.scala 273:28] - ahb_to_axi4.io.ahb.hsel <= io.dma_ahb.hsel @[quasar.scala 273:28] - ahb_to_axi4.io.ahb.sig.out.hwdata <= io.dma_ahb.sig.out.hwdata @[quasar.scala 273:28] - ahb_to_axi4.io.ahb.sig.out.hwrite <= io.dma_ahb.sig.out.hwrite @[quasar.scala 273:28] - ahb_to_axi4.io.ahb.sig.out.htrans <= io.dma_ahb.sig.out.htrans @[quasar.scala 273:28] - ahb_to_axi4.io.ahb.sig.out.hsize <= io.dma_ahb.sig.out.hsize @[quasar.scala 273:28] - ahb_to_axi4.io.ahb.sig.out.hprot <= io.dma_ahb.sig.out.hprot @[quasar.scala 273:28] - ahb_to_axi4.io.ahb.sig.out.hmastlock <= io.dma_ahb.sig.out.hmastlock @[quasar.scala 273:28] - ahb_to_axi4.io.ahb.sig.out.hburst <= io.dma_ahb.sig.out.hburst @[quasar.scala 273:28] - ahb_to_axi4.io.ahb.sig.out.haddr <= io.dma_ahb.sig.out.haddr @[quasar.scala 273:28] - io.dma_ahb.sig.in.hresp <= ahb_to_axi4.io.ahb.sig.in.hresp @[quasar.scala 273:28] - io.dma_ahb.sig.in.hready <= ahb_to_axi4.io.ahb.sig.in.hready @[quasar.scala 273:28] - io.dma_ahb.sig.in.hrdata <= ahb_to_axi4.io.ahb.sig.in.hrdata @[quasar.scala 273:28] - wire _T_12 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar.scala 275:36] - _T_12.r.bits.last <= UInt<1>("h00") @[quasar.scala 275:36] - _T_12.r.bits.resp <= UInt<2>("h00") @[quasar.scala 275:36] - _T_12.r.bits.data <= UInt<64>("h00") @[quasar.scala 275:36] - _T_12.r.bits.id <= UInt<1>("h00") @[quasar.scala 275:36] - _T_12.r.valid <= UInt<1>("h00") @[quasar.scala 275:36] - _T_12.r.ready <= UInt<1>("h00") @[quasar.scala 275:36] - _T_12.ar.bits.qos <= UInt<4>("h00") @[quasar.scala 275:36] - _T_12.ar.bits.prot <= UInt<3>("h00") @[quasar.scala 275:36] - _T_12.ar.bits.cache <= UInt<4>("h00") @[quasar.scala 275:36] - _T_12.ar.bits.lock <= UInt<1>("h00") @[quasar.scala 275:36] - _T_12.ar.bits.burst <= UInt<2>("h00") @[quasar.scala 275:36] - _T_12.ar.bits.size <= UInt<3>("h00") @[quasar.scala 275:36] - _T_12.ar.bits.len <= UInt<8>("h00") @[quasar.scala 275:36] - _T_12.ar.bits.region <= UInt<4>("h00") @[quasar.scala 275:36] - _T_12.ar.bits.addr <= UInt<32>("h00") @[quasar.scala 275:36] - _T_12.ar.bits.id <= UInt<1>("h00") @[quasar.scala 275:36] - _T_12.ar.valid <= UInt<1>("h00") @[quasar.scala 275:36] - _T_12.ar.ready <= UInt<1>("h00") @[quasar.scala 275:36] - _T_12.b.bits.id <= UInt<1>("h00") @[quasar.scala 275:36] - _T_12.b.bits.resp <= UInt<2>("h00") @[quasar.scala 275:36] - _T_12.b.valid <= UInt<1>("h00") @[quasar.scala 275:36] - _T_12.b.ready <= UInt<1>("h00") @[quasar.scala 275:36] - _T_12.w.bits.last <= UInt<1>("h00") @[quasar.scala 275:36] - _T_12.w.bits.strb <= UInt<8>("h00") @[quasar.scala 275:36] - _T_12.w.bits.data <= UInt<64>("h00") @[quasar.scala 275:36] - _T_12.w.valid <= UInt<1>("h00") @[quasar.scala 275:36] - _T_12.w.ready <= UInt<1>("h00") @[quasar.scala 275:36] - _T_12.aw.bits.qos <= UInt<4>("h00") @[quasar.scala 275:36] - _T_12.aw.bits.prot <= UInt<3>("h00") @[quasar.scala 275:36] - _T_12.aw.bits.cache <= UInt<4>("h00") @[quasar.scala 275:36] - _T_12.aw.bits.lock <= UInt<1>("h00") @[quasar.scala 275:36] - _T_12.aw.bits.burst <= UInt<2>("h00") @[quasar.scala 275:36] - _T_12.aw.bits.size <= UInt<3>("h00") @[quasar.scala 275:36] - _T_12.aw.bits.len <= UInt<8>("h00") @[quasar.scala 275:36] - _T_12.aw.bits.region <= UInt<4>("h00") @[quasar.scala 275:36] - _T_12.aw.bits.addr <= UInt<32>("h00") @[quasar.scala 275:36] - _T_12.aw.bits.id <= UInt<1>("h00") @[quasar.scala 275:36] - _T_12.aw.valid <= UInt<1>("h00") @[quasar.scala 275:36] - _T_12.aw.ready <= UInt<1>("h00") @[quasar.scala 275:36] - io.dma_axi.r.bits.last <= _T_12.r.bits.last @[quasar.scala 275:21] - io.dma_axi.r.bits.resp <= _T_12.r.bits.resp @[quasar.scala 275:21] - io.dma_axi.r.bits.data <= _T_12.r.bits.data @[quasar.scala 275:21] - io.dma_axi.r.bits.id <= _T_12.r.bits.id @[quasar.scala 275:21] - io.dma_axi.r.valid <= _T_12.r.valid @[quasar.scala 275:21] - _T_12.r.ready <= io.dma_axi.r.ready @[quasar.scala 275:21] - _T_12.ar.bits.qos <= io.dma_axi.ar.bits.qos @[quasar.scala 275:21] - _T_12.ar.bits.prot <= io.dma_axi.ar.bits.prot @[quasar.scala 275:21] - _T_12.ar.bits.cache <= io.dma_axi.ar.bits.cache @[quasar.scala 275:21] - _T_12.ar.bits.lock <= io.dma_axi.ar.bits.lock @[quasar.scala 275:21] - _T_12.ar.bits.burst <= io.dma_axi.ar.bits.burst @[quasar.scala 275:21] - _T_12.ar.bits.size <= io.dma_axi.ar.bits.size @[quasar.scala 275:21] - _T_12.ar.bits.len <= io.dma_axi.ar.bits.len @[quasar.scala 275:21] - _T_12.ar.bits.region <= io.dma_axi.ar.bits.region @[quasar.scala 275:21] - _T_12.ar.bits.addr <= io.dma_axi.ar.bits.addr @[quasar.scala 275:21] - _T_12.ar.bits.id <= io.dma_axi.ar.bits.id @[quasar.scala 275:21] - _T_12.ar.valid <= io.dma_axi.ar.valid @[quasar.scala 275:21] - io.dma_axi.ar.ready <= _T_12.ar.ready @[quasar.scala 275:21] - io.dma_axi.b.bits.id <= _T_12.b.bits.id @[quasar.scala 275:21] - io.dma_axi.b.bits.resp <= _T_12.b.bits.resp @[quasar.scala 275:21] - io.dma_axi.b.valid <= _T_12.b.valid @[quasar.scala 275:21] - _T_12.b.ready <= io.dma_axi.b.ready @[quasar.scala 275:21] - _T_12.w.bits.last <= io.dma_axi.w.bits.last @[quasar.scala 275:21] - _T_12.w.bits.strb <= io.dma_axi.w.bits.strb @[quasar.scala 275:21] - _T_12.w.bits.data <= io.dma_axi.w.bits.data @[quasar.scala 275:21] - _T_12.w.valid <= io.dma_axi.w.valid @[quasar.scala 275:21] - io.dma_axi.w.ready <= _T_12.w.ready @[quasar.scala 275:21] - _T_12.aw.bits.qos <= io.dma_axi.aw.bits.qos @[quasar.scala 275:21] - _T_12.aw.bits.prot <= io.dma_axi.aw.bits.prot @[quasar.scala 275:21] - _T_12.aw.bits.cache <= io.dma_axi.aw.bits.cache @[quasar.scala 275:21] - _T_12.aw.bits.lock <= io.dma_axi.aw.bits.lock @[quasar.scala 275:21] - _T_12.aw.bits.burst <= io.dma_axi.aw.bits.burst @[quasar.scala 275:21] - _T_12.aw.bits.size <= io.dma_axi.aw.bits.size @[quasar.scala 275:21] - _T_12.aw.bits.len <= io.dma_axi.aw.bits.len @[quasar.scala 275:21] - _T_12.aw.bits.region <= io.dma_axi.aw.bits.region @[quasar.scala 275:21] - _T_12.aw.bits.addr <= io.dma_axi.aw.bits.addr @[quasar.scala 275:21] - _T_12.aw.bits.id <= io.dma_axi.aw.bits.id @[quasar.scala 275:21] - _T_12.aw.valid <= io.dma_axi.aw.valid @[quasar.scala 275:21] - io.dma_axi.aw.ready <= _T_12.aw.ready @[quasar.scala 275:21] - wire _T_13 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar.scala 276:36] - _T_13.r.bits.last <= UInt<1>("h00") @[quasar.scala 276:36] - _T_13.r.bits.resp <= UInt<2>("h00") @[quasar.scala 276:36] - _T_13.r.bits.data <= UInt<64>("h00") @[quasar.scala 276:36] - _T_13.r.bits.id <= UInt<1>("h00") @[quasar.scala 276:36] - _T_13.r.valid <= UInt<1>("h00") @[quasar.scala 276:36] - _T_13.r.ready <= UInt<1>("h00") @[quasar.scala 276:36] - _T_13.ar.bits.qos <= UInt<4>("h00") @[quasar.scala 276:36] - _T_13.ar.bits.prot <= UInt<3>("h00") @[quasar.scala 276:36] - _T_13.ar.bits.cache <= UInt<4>("h00") @[quasar.scala 276:36] - _T_13.ar.bits.lock <= UInt<1>("h00") @[quasar.scala 276:36] - _T_13.ar.bits.burst <= UInt<2>("h00") @[quasar.scala 276:36] - _T_13.ar.bits.size <= UInt<3>("h00") @[quasar.scala 276:36] - _T_13.ar.bits.len <= UInt<8>("h00") @[quasar.scala 276:36] - _T_13.ar.bits.region <= UInt<4>("h00") @[quasar.scala 276:36] - _T_13.ar.bits.addr <= UInt<32>("h00") @[quasar.scala 276:36] - _T_13.ar.bits.id <= UInt<1>("h00") @[quasar.scala 276:36] - _T_13.ar.valid <= UInt<1>("h00") @[quasar.scala 276:36] - _T_13.ar.ready <= UInt<1>("h00") @[quasar.scala 276:36] - _T_13.b.bits.id <= UInt<1>("h00") @[quasar.scala 276:36] - _T_13.b.bits.resp <= UInt<2>("h00") @[quasar.scala 276:36] - _T_13.b.valid <= UInt<1>("h00") @[quasar.scala 276:36] - _T_13.b.ready <= UInt<1>("h00") @[quasar.scala 276:36] - _T_13.w.bits.last <= UInt<1>("h00") @[quasar.scala 276:36] - _T_13.w.bits.strb <= UInt<8>("h00") @[quasar.scala 276:36] - _T_13.w.bits.data <= UInt<64>("h00") @[quasar.scala 276:36] - _T_13.w.valid <= UInt<1>("h00") @[quasar.scala 276:36] - _T_13.w.ready <= UInt<1>("h00") @[quasar.scala 276:36] - _T_13.aw.bits.qos <= UInt<4>("h00") @[quasar.scala 276:36] - _T_13.aw.bits.prot <= UInt<3>("h00") @[quasar.scala 276:36] - _T_13.aw.bits.cache <= UInt<4>("h00") @[quasar.scala 276:36] - _T_13.aw.bits.lock <= UInt<1>("h00") @[quasar.scala 276:36] - _T_13.aw.bits.burst <= UInt<2>("h00") @[quasar.scala 276:36] - _T_13.aw.bits.size <= UInt<3>("h00") @[quasar.scala 276:36] - _T_13.aw.bits.len <= UInt<8>("h00") @[quasar.scala 276:36] - _T_13.aw.bits.region <= UInt<4>("h00") @[quasar.scala 276:36] - _T_13.aw.bits.addr <= UInt<32>("h00") @[quasar.scala 276:36] - _T_13.aw.bits.id <= UInt<1>("h00") @[quasar.scala 276:36] - _T_13.aw.valid <= UInt<1>("h00") @[quasar.scala 276:36] - _T_13.aw.ready <= UInt<1>("h00") @[quasar.scala 276:36] - _T_13.r.bits.last <= io.sb_axi.r.bits.last @[quasar.scala 276:21] - _T_13.r.bits.resp <= io.sb_axi.r.bits.resp @[quasar.scala 276:21] - _T_13.r.bits.data <= io.sb_axi.r.bits.data @[quasar.scala 276:21] - _T_13.r.bits.id <= io.sb_axi.r.bits.id @[quasar.scala 276:21] - _T_13.r.valid <= io.sb_axi.r.valid @[quasar.scala 276:21] - io.sb_axi.r.ready <= _T_13.r.ready @[quasar.scala 276:21] - io.sb_axi.ar.bits.qos <= _T_13.ar.bits.qos @[quasar.scala 276:21] - io.sb_axi.ar.bits.prot <= _T_13.ar.bits.prot @[quasar.scala 276:21] - io.sb_axi.ar.bits.cache <= _T_13.ar.bits.cache @[quasar.scala 276:21] - io.sb_axi.ar.bits.lock <= _T_13.ar.bits.lock @[quasar.scala 276:21] - io.sb_axi.ar.bits.burst <= _T_13.ar.bits.burst @[quasar.scala 276:21] - io.sb_axi.ar.bits.size <= _T_13.ar.bits.size @[quasar.scala 276:21] - io.sb_axi.ar.bits.len <= _T_13.ar.bits.len @[quasar.scala 276:21] - io.sb_axi.ar.bits.region <= _T_13.ar.bits.region @[quasar.scala 276:21] - io.sb_axi.ar.bits.addr <= _T_13.ar.bits.addr @[quasar.scala 276:21] - io.sb_axi.ar.bits.id <= _T_13.ar.bits.id @[quasar.scala 276:21] - io.sb_axi.ar.valid <= _T_13.ar.valid @[quasar.scala 276:21] - _T_13.ar.ready <= io.sb_axi.ar.ready @[quasar.scala 276:21] - _T_13.b.bits.id <= io.sb_axi.b.bits.id @[quasar.scala 276:21] - _T_13.b.bits.resp <= io.sb_axi.b.bits.resp @[quasar.scala 276:21] - _T_13.b.valid <= io.sb_axi.b.valid @[quasar.scala 276:21] - io.sb_axi.b.ready <= _T_13.b.ready @[quasar.scala 276:21] - io.sb_axi.w.bits.last <= _T_13.w.bits.last @[quasar.scala 276:21] - io.sb_axi.w.bits.strb <= _T_13.w.bits.strb @[quasar.scala 276:21] - io.sb_axi.w.bits.data <= _T_13.w.bits.data @[quasar.scala 276:21] - io.sb_axi.w.valid <= _T_13.w.valid @[quasar.scala 276:21] - _T_13.w.ready <= io.sb_axi.w.ready @[quasar.scala 276:21] - io.sb_axi.aw.bits.qos <= _T_13.aw.bits.qos @[quasar.scala 276:21] - io.sb_axi.aw.bits.prot <= _T_13.aw.bits.prot @[quasar.scala 276:21] - io.sb_axi.aw.bits.cache <= _T_13.aw.bits.cache @[quasar.scala 276:21] - io.sb_axi.aw.bits.lock <= _T_13.aw.bits.lock @[quasar.scala 276:21] - io.sb_axi.aw.bits.burst <= _T_13.aw.bits.burst @[quasar.scala 276:21] - io.sb_axi.aw.bits.size <= _T_13.aw.bits.size @[quasar.scala 276:21] - io.sb_axi.aw.bits.len <= _T_13.aw.bits.len @[quasar.scala 276:21] - io.sb_axi.aw.bits.region <= _T_13.aw.bits.region @[quasar.scala 276:21] - io.sb_axi.aw.bits.addr <= _T_13.aw.bits.addr @[quasar.scala 276:21] - io.sb_axi.aw.bits.id <= _T_13.aw.bits.id @[quasar.scala 276:21] - io.sb_axi.aw.valid <= _T_13.aw.valid @[quasar.scala 276:21] - _T_13.aw.ready <= io.sb_axi.aw.ready @[quasar.scala 276:21] - wire _T_14 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar.scala 277:36] - _T_14.r.bits.last <= UInt<1>("h00") @[quasar.scala 277:36] - _T_14.r.bits.resp <= UInt<2>("h00") @[quasar.scala 277:36] - _T_14.r.bits.data <= UInt<64>("h00") @[quasar.scala 277:36] - _T_14.r.bits.id <= UInt<3>("h00") @[quasar.scala 277:36] - _T_14.r.valid <= UInt<1>("h00") @[quasar.scala 277:36] - _T_14.r.ready <= UInt<1>("h00") @[quasar.scala 277:36] - _T_14.ar.bits.qos <= UInt<4>("h00") @[quasar.scala 277:36] - _T_14.ar.bits.prot <= UInt<3>("h00") @[quasar.scala 277:36] - _T_14.ar.bits.cache <= UInt<4>("h00") @[quasar.scala 277:36] - _T_14.ar.bits.lock <= UInt<1>("h00") @[quasar.scala 277:36] - _T_14.ar.bits.burst <= UInt<2>("h00") @[quasar.scala 277:36] - _T_14.ar.bits.size <= UInt<3>("h00") @[quasar.scala 277:36] - _T_14.ar.bits.len <= UInt<8>("h00") @[quasar.scala 277:36] - _T_14.ar.bits.region <= UInt<4>("h00") @[quasar.scala 277:36] - _T_14.ar.bits.addr <= UInt<32>("h00") @[quasar.scala 277:36] - _T_14.ar.bits.id <= UInt<3>("h00") @[quasar.scala 277:36] - _T_14.ar.valid <= UInt<1>("h00") @[quasar.scala 277:36] - _T_14.ar.ready <= UInt<1>("h00") @[quasar.scala 277:36] - _T_14.b.bits.id <= UInt<3>("h00") @[quasar.scala 277:36] - _T_14.b.bits.resp <= UInt<2>("h00") @[quasar.scala 277:36] - _T_14.b.valid <= UInt<1>("h00") @[quasar.scala 277:36] - _T_14.b.ready <= UInt<1>("h00") @[quasar.scala 277:36] - _T_14.w.bits.last <= UInt<1>("h00") @[quasar.scala 277:36] - _T_14.w.bits.strb <= UInt<8>("h00") @[quasar.scala 277:36] - _T_14.w.bits.data <= UInt<64>("h00") @[quasar.scala 277:36] - _T_14.w.valid <= UInt<1>("h00") @[quasar.scala 277:36] - _T_14.w.ready <= UInt<1>("h00") @[quasar.scala 277:36] - _T_14.aw.bits.qos <= UInt<4>("h00") @[quasar.scala 277:36] - _T_14.aw.bits.prot <= UInt<3>("h00") @[quasar.scala 277:36] - _T_14.aw.bits.cache <= UInt<4>("h00") @[quasar.scala 277:36] - _T_14.aw.bits.lock <= UInt<1>("h00") @[quasar.scala 277:36] - _T_14.aw.bits.burst <= UInt<2>("h00") @[quasar.scala 277:36] - _T_14.aw.bits.size <= UInt<3>("h00") @[quasar.scala 277:36] - _T_14.aw.bits.len <= UInt<8>("h00") @[quasar.scala 277:36] - _T_14.aw.bits.region <= UInt<4>("h00") @[quasar.scala 277:36] - _T_14.aw.bits.addr <= UInt<32>("h00") @[quasar.scala 277:36] - _T_14.aw.bits.id <= UInt<3>("h00") @[quasar.scala 277:36] - _T_14.aw.valid <= UInt<1>("h00") @[quasar.scala 277:36] - _T_14.aw.ready <= UInt<1>("h00") @[quasar.scala 277:36] - _T_14.r.bits.last <= io.ifu_axi.r.bits.last @[quasar.scala 277:21] - _T_14.r.bits.resp <= io.ifu_axi.r.bits.resp @[quasar.scala 277:21] - _T_14.r.bits.data <= io.ifu_axi.r.bits.data @[quasar.scala 277:21] - _T_14.r.bits.id <= io.ifu_axi.r.bits.id @[quasar.scala 277:21] - _T_14.r.valid <= io.ifu_axi.r.valid @[quasar.scala 277:21] - io.ifu_axi.r.ready <= _T_14.r.ready @[quasar.scala 277:21] - io.ifu_axi.ar.bits.qos <= _T_14.ar.bits.qos @[quasar.scala 277:21] - io.ifu_axi.ar.bits.prot <= _T_14.ar.bits.prot @[quasar.scala 277:21] - io.ifu_axi.ar.bits.cache <= _T_14.ar.bits.cache @[quasar.scala 277:21] - io.ifu_axi.ar.bits.lock <= _T_14.ar.bits.lock @[quasar.scala 277:21] - io.ifu_axi.ar.bits.burst <= _T_14.ar.bits.burst @[quasar.scala 277:21] - io.ifu_axi.ar.bits.size <= _T_14.ar.bits.size @[quasar.scala 277:21] - io.ifu_axi.ar.bits.len <= _T_14.ar.bits.len @[quasar.scala 277:21] - io.ifu_axi.ar.bits.region <= _T_14.ar.bits.region @[quasar.scala 277:21] - io.ifu_axi.ar.bits.addr <= _T_14.ar.bits.addr @[quasar.scala 277:21] - io.ifu_axi.ar.bits.id <= _T_14.ar.bits.id @[quasar.scala 277:21] - io.ifu_axi.ar.valid <= _T_14.ar.valid @[quasar.scala 277:21] - _T_14.ar.ready <= io.ifu_axi.ar.ready @[quasar.scala 277:21] - _T_14.b.bits.id <= io.ifu_axi.b.bits.id @[quasar.scala 277:21] - _T_14.b.bits.resp <= io.ifu_axi.b.bits.resp @[quasar.scala 277:21] - _T_14.b.valid <= io.ifu_axi.b.valid @[quasar.scala 277:21] - io.ifu_axi.b.ready <= _T_14.b.ready @[quasar.scala 277:21] - io.ifu_axi.w.bits.last <= _T_14.w.bits.last @[quasar.scala 277:21] - io.ifu_axi.w.bits.strb <= _T_14.w.bits.strb @[quasar.scala 277:21] - io.ifu_axi.w.bits.data <= _T_14.w.bits.data @[quasar.scala 277:21] - io.ifu_axi.w.valid <= _T_14.w.valid @[quasar.scala 277:21] - _T_14.w.ready <= io.ifu_axi.w.ready @[quasar.scala 277:21] - io.ifu_axi.aw.bits.qos <= _T_14.aw.bits.qos @[quasar.scala 277:21] - io.ifu_axi.aw.bits.prot <= _T_14.aw.bits.prot @[quasar.scala 277:21] - io.ifu_axi.aw.bits.cache <= _T_14.aw.bits.cache @[quasar.scala 277:21] - io.ifu_axi.aw.bits.lock <= _T_14.aw.bits.lock @[quasar.scala 277:21] - io.ifu_axi.aw.bits.burst <= _T_14.aw.bits.burst @[quasar.scala 277:21] - io.ifu_axi.aw.bits.size <= _T_14.aw.bits.size @[quasar.scala 277:21] - io.ifu_axi.aw.bits.len <= _T_14.aw.bits.len @[quasar.scala 277:21] - io.ifu_axi.aw.bits.region <= _T_14.aw.bits.region @[quasar.scala 277:21] - io.ifu_axi.aw.bits.addr <= _T_14.aw.bits.addr @[quasar.scala 277:21] - io.ifu_axi.aw.bits.id <= _T_14.aw.bits.id @[quasar.scala 277:21] - io.ifu_axi.aw.valid <= _T_14.aw.valid @[quasar.scala 277:21] - _T_14.aw.ready <= io.ifu_axi.aw.ready @[quasar.scala 277:21] - wire _T_15 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar.scala 278:36] - _T_15.r.bits.last <= UInt<1>("h00") @[quasar.scala 278:36] - _T_15.r.bits.resp <= UInt<2>("h00") @[quasar.scala 278:36] - _T_15.r.bits.data <= UInt<64>("h00") @[quasar.scala 278:36] - _T_15.r.bits.id <= UInt<3>("h00") @[quasar.scala 278:36] - _T_15.r.valid <= UInt<1>("h00") @[quasar.scala 278:36] - _T_15.r.ready <= UInt<1>("h00") @[quasar.scala 278:36] - _T_15.ar.bits.qos <= UInt<4>("h00") @[quasar.scala 278:36] - _T_15.ar.bits.prot <= UInt<3>("h00") @[quasar.scala 278:36] - _T_15.ar.bits.cache <= UInt<4>("h00") @[quasar.scala 278:36] - _T_15.ar.bits.lock <= UInt<1>("h00") @[quasar.scala 278:36] - _T_15.ar.bits.burst <= UInt<2>("h00") @[quasar.scala 278:36] - _T_15.ar.bits.size <= UInt<3>("h00") @[quasar.scala 278:36] - _T_15.ar.bits.len <= UInt<8>("h00") @[quasar.scala 278:36] - _T_15.ar.bits.region <= UInt<4>("h00") @[quasar.scala 278:36] - _T_15.ar.bits.addr <= UInt<32>("h00") @[quasar.scala 278:36] - _T_15.ar.bits.id <= UInt<3>("h00") @[quasar.scala 278:36] - _T_15.ar.valid <= UInt<1>("h00") @[quasar.scala 278:36] - _T_15.ar.ready <= UInt<1>("h00") @[quasar.scala 278:36] - _T_15.b.bits.id <= UInt<3>("h00") @[quasar.scala 278:36] - _T_15.b.bits.resp <= UInt<2>("h00") @[quasar.scala 278:36] - _T_15.b.valid <= UInt<1>("h00") @[quasar.scala 278:36] - _T_15.b.ready <= UInt<1>("h00") @[quasar.scala 278:36] - _T_15.w.bits.last <= UInt<1>("h00") @[quasar.scala 278:36] - _T_15.w.bits.strb <= UInt<8>("h00") @[quasar.scala 278:36] - _T_15.w.bits.data <= UInt<64>("h00") @[quasar.scala 278:36] - _T_15.w.valid <= UInt<1>("h00") @[quasar.scala 278:36] - _T_15.w.ready <= UInt<1>("h00") @[quasar.scala 278:36] - _T_15.aw.bits.qos <= UInt<4>("h00") @[quasar.scala 278:36] - _T_15.aw.bits.prot <= UInt<3>("h00") @[quasar.scala 278:36] - _T_15.aw.bits.cache <= UInt<4>("h00") @[quasar.scala 278:36] - _T_15.aw.bits.lock <= UInt<1>("h00") @[quasar.scala 278:36] - _T_15.aw.bits.burst <= UInt<2>("h00") @[quasar.scala 278:36] - _T_15.aw.bits.size <= UInt<3>("h00") @[quasar.scala 278:36] - _T_15.aw.bits.len <= UInt<8>("h00") @[quasar.scala 278:36] - _T_15.aw.bits.region <= UInt<4>("h00") @[quasar.scala 278:36] - _T_15.aw.bits.addr <= UInt<32>("h00") @[quasar.scala 278:36] - _T_15.aw.bits.id <= UInt<3>("h00") @[quasar.scala 278:36] - _T_15.aw.valid <= UInt<1>("h00") @[quasar.scala 278:36] - _T_15.aw.ready <= UInt<1>("h00") @[quasar.scala 278:36] - _T_15.r.bits.last <= io.lsu_axi.r.bits.last @[quasar.scala 278:21] - _T_15.r.bits.resp <= io.lsu_axi.r.bits.resp @[quasar.scala 278:21] - _T_15.r.bits.data <= io.lsu_axi.r.bits.data @[quasar.scala 278:21] - _T_15.r.bits.id <= io.lsu_axi.r.bits.id @[quasar.scala 278:21] - _T_15.r.valid <= io.lsu_axi.r.valid @[quasar.scala 278:21] - io.lsu_axi.r.ready <= _T_15.r.ready @[quasar.scala 278:21] - io.lsu_axi.ar.bits.qos <= _T_15.ar.bits.qos @[quasar.scala 278:21] - io.lsu_axi.ar.bits.prot <= _T_15.ar.bits.prot @[quasar.scala 278:21] - io.lsu_axi.ar.bits.cache <= _T_15.ar.bits.cache @[quasar.scala 278:21] - io.lsu_axi.ar.bits.lock <= _T_15.ar.bits.lock @[quasar.scala 278:21] - io.lsu_axi.ar.bits.burst <= _T_15.ar.bits.burst @[quasar.scala 278:21] - io.lsu_axi.ar.bits.size <= _T_15.ar.bits.size @[quasar.scala 278:21] - io.lsu_axi.ar.bits.len <= _T_15.ar.bits.len @[quasar.scala 278:21] - io.lsu_axi.ar.bits.region <= _T_15.ar.bits.region @[quasar.scala 278:21] - io.lsu_axi.ar.bits.addr <= _T_15.ar.bits.addr @[quasar.scala 278:21] - io.lsu_axi.ar.bits.id <= _T_15.ar.bits.id @[quasar.scala 278:21] - io.lsu_axi.ar.valid <= _T_15.ar.valid @[quasar.scala 278:21] - _T_15.ar.ready <= io.lsu_axi.ar.ready @[quasar.scala 278:21] - _T_15.b.bits.id <= io.lsu_axi.b.bits.id @[quasar.scala 278:21] - _T_15.b.bits.resp <= io.lsu_axi.b.bits.resp @[quasar.scala 278:21] - _T_15.b.valid <= io.lsu_axi.b.valid @[quasar.scala 278:21] - io.lsu_axi.b.ready <= _T_15.b.ready @[quasar.scala 278:21] - io.lsu_axi.w.bits.last <= _T_15.w.bits.last @[quasar.scala 278:21] - io.lsu_axi.w.bits.strb <= _T_15.w.bits.strb @[quasar.scala 278:21] - io.lsu_axi.w.bits.data <= _T_15.w.bits.data @[quasar.scala 278:21] - io.lsu_axi.w.valid <= _T_15.w.valid @[quasar.scala 278:21] - _T_15.w.ready <= io.lsu_axi.w.ready @[quasar.scala 278:21] - io.lsu_axi.aw.bits.qos <= _T_15.aw.bits.qos @[quasar.scala 278:21] - io.lsu_axi.aw.bits.prot <= _T_15.aw.bits.prot @[quasar.scala 278:21] - io.lsu_axi.aw.bits.cache <= _T_15.aw.bits.cache @[quasar.scala 278:21] - io.lsu_axi.aw.bits.lock <= _T_15.aw.bits.lock @[quasar.scala 278:21] - io.lsu_axi.aw.bits.burst <= _T_15.aw.bits.burst @[quasar.scala 278:21] - io.lsu_axi.aw.bits.size <= _T_15.aw.bits.size @[quasar.scala 278:21] - io.lsu_axi.aw.bits.len <= _T_15.aw.bits.len @[quasar.scala 278:21] - io.lsu_axi.aw.bits.region <= _T_15.aw.bits.region @[quasar.scala 278:21] - io.lsu_axi.aw.bits.addr <= _T_15.aw.bits.addr @[quasar.scala 278:21] - io.lsu_axi.aw.bits.id <= _T_15.aw.bits.id @[quasar.scala 278:21] - io.lsu_axi.aw.valid <= _T_15.aw.valid @[quasar.scala 278:21] - _T_15.aw.ready <= io.lsu_axi.aw.ready @[quasar.scala 278:21] + ifu.io.ifu_dec.dec_bp.dec_tlu_bpred_disable <= dec.io.ifu_dec.dec_bp.dec_tlu_bpred_disable @[quasar.scala 88:18] + ifu.io.ifu_dec.dec_bp.dec_tlu_flush_leak_one_wb <= dec.io.ifu_dec.dec_bp.dec_tlu_flush_leak_one_wb @[quasar.scala 88:18] + ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.middle <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.middle @[quasar.scala 88:18] + ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.way <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.way @[quasar.scala 88:18] + ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_start_error <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_start_error @[quasar.scala 88:18] + ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_error <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_error @[quasar.scala 88:18] + ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.hist <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.hist @[quasar.scala 88:18] + ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.valid <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.valid @[quasar.scala 88:18] + dec.io.ifu_dec.dec_ifc.ifu_pmu_fetch_stall <= ifu.io.ifu_dec.dec_ifc.ifu_pmu_fetch_stall @[quasar.scala 88:18] + ifu.io.ifu_dec.dec_ifc.dec_tlu_mrac_ff <= dec.io.ifu_dec.dec_ifc.dec_tlu_mrac_ff @[quasar.scala 88:18] + ifu.io.ifu_dec.dec_ifc.dec_tlu_flush_noredir_wb <= dec.io.ifu_dec.dec_ifc.dec_tlu_flush_noredir_wb @[quasar.scala 88:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_miss_state_idle <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_miss_state_idle @[quasar.scala 88:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data_valid <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data_valid @[quasar.scala 88:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data @[quasar.scala 88:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err @[quasar.scala 88:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_ic_error_start <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_ic_error_start @[quasar.scala 88:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_trxn <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_trxn @[quasar.scala 88:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_busy <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_busy @[quasar.scala 88:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_error <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_error @[quasar.scala 88:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_hit <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_hit @[quasar.scala 88:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_miss <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_miss @[quasar.scala 88:18] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable @[quasar.scala 88:18] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid @[quasar.scala 88:18] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid @[quasar.scala 88:18] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics @[quasar.scala 88:18] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata @[quasar.scala 88:18] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_fence_i_wb <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_fence_i_wb @[quasar.scala 88:18] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt @[quasar.scala 88:18] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_i0_commit_cmt <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_i0_commit_cmt @[quasar.scala 88:18] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_flush_err_wb <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_flush_err_wb @[quasar.scala 88:18] + dec.io.ifu_dec.dec_aln.ifu_pmu_instr_aligned <= ifu.io.ifu_dec.dec_aln.ifu_pmu_instr_aligned @[quasar.scala 88:18] + dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.ret <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.ret @[quasar.scala 88:18] + dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.way <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.way @[quasar.scala 88:18] + dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.prett <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.prett @[quasar.scala 88:18] + dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.bank <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.bank @[quasar.scala 88:18] + dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_start_error <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_start_error @[quasar.scala 88:18] + dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_error <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_error @[quasar.scala 88:18] + dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.hist <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.hist @[quasar.scala 88:18] + dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.toffset <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.toffset @[quasar.scala 88:18] + dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.valid <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.valid @[quasar.scala 88:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc4 <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc4 @[quasar.scala 88:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc @[quasar.scala 88:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_instr <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_instr @[quasar.scala 88:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_valid <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_valid @[quasar.scala 88:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_btag <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_btag @[quasar.scala 88:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_fghr <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_fghr @[quasar.scala 88:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_index <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_index @[quasar.scala 88:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_dbecc <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_dbecc @[quasar.scala 88:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_f1 <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_f1 @[quasar.scala 88:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_type <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_type @[quasar.scala 88:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf @[quasar.scala 88:18] + dec.io.ifu_dec.dec_aln.aln_dec.ifu_i0_cinst <= ifu.io.ifu_dec.dec_aln.aln_dec.ifu_i0_cinst @[quasar.scala 88:18] + ifu.io.ifu_dec.dec_aln.aln_dec.dec_i0_decode_d <= dec.io.ifu_dec.dec_aln.aln_dec.dec_i0_decode_d @[quasar.scala 88:18] + ifu.reset <= io.core_rst_l @[quasar.scala 90:13] + ifu.io.scan_mode <= io.scan_mode @[quasar.scala 91:20] + ifu.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 92:19] + ifu.io.active_clk <= rvclkhdr_1.io.l1clk @[quasar.scala 93:21] + ifu.io.exu_flush_final <= dec.io.exu_flush_final @[quasar.scala 95:26] + ifu.io.exu_flush_path_final <= exu.io.exu_flush_path_final @[quasar.scala 96:31] + ifu.io.ifu_bus_clk_en <= io.ifu_bus_clk_en @[quasar.scala 98:25] + ifu.io.ifu_dma.dma_mem_ctl.dma_mem_tag <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_tag @[quasar.scala 99:18] + ifu.io.ifu_dma.dma_mem_ctl.dma_mem_wdata <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_wdata @[quasar.scala 99:18] + ifu.io.ifu_dma.dma_mem_ctl.dma_mem_write <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_write @[quasar.scala 99:18] + ifu.io.ifu_dma.dma_mem_ctl.dma_mem_sz <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_sz @[quasar.scala 99:18] + ifu.io.ifu_dma.dma_mem_ctl.dma_mem_addr <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_addr @[quasar.scala 99:18] + ifu.io.ifu_dma.dma_mem_ctl.dma_iccm_req <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_iccm_req @[quasar.scala 99:18] + ifu.io.ifu_dma.dma_ifc.dma_iccm_stall_any <= dma_ctrl.io.ifu_dma.dma_ifc.dma_iccm_stall_any @[quasar.scala 99:18] + io.ic.sel_premux_data <= ifu.io.ic.sel_premux_data @[quasar.scala 100:13] + io.ic.premux_data <= ifu.io.ic.premux_data @[quasar.scala 100:13] + io.ic.debug_way <= ifu.io.ic.debug_way @[quasar.scala 100:13] + io.ic.debug_tag_array <= ifu.io.ic.debug_tag_array @[quasar.scala 100:13] + io.ic.debug_wr_en <= ifu.io.ic.debug_wr_en @[quasar.scala 100:13] + io.ic.debug_rd_en <= ifu.io.ic.debug_rd_en @[quasar.scala 100:13] + ifu.io.ic.tag_perr <= io.ic.tag_perr @[quasar.scala 100:13] + ifu.io.ic.rd_hit <= io.ic.rd_hit @[quasar.scala 100:13] + ifu.io.ic.parerr <= io.ic.parerr @[quasar.scala 100:13] + ifu.io.ic.eccerr <= io.ic.eccerr @[quasar.scala 100:13] + ifu.io.ic.tag_debug_rd_data <= io.ic.tag_debug_rd_data @[quasar.scala 100:13] + ifu.io.ic.debug_rd_data <= io.ic.debug_rd_data @[quasar.scala 100:13] + ifu.io.ic.rd_data <= io.ic.rd_data @[quasar.scala 100:13] + io.ic.debug_addr <= ifu.io.ic.debug_addr @[quasar.scala 100:13] + io.ic.debug_wr_data <= ifu.io.ic.debug_wr_data @[quasar.scala 100:13] + io.ic.wr_data[0] <= ifu.io.ic.wr_data[0] @[quasar.scala 100:13] + io.ic.wr_data[1] <= ifu.io.ic.wr_data[1] @[quasar.scala 100:13] + io.ic.rd_en <= ifu.io.ic.rd_en @[quasar.scala 100:13] + io.ic.wr_en <= ifu.io.ic.wr_en @[quasar.scala 100:13] + io.ic.tag_valid <= ifu.io.ic.tag_valid @[quasar.scala 100:13] + io.ic.rw_addr <= ifu.io.ic.rw_addr @[quasar.scala 100:13] + ifu.io.iccm.rd_data_ecc <= io.iccm.rd_data_ecc @[quasar.scala 101:15] + ifu.io.iccm.rd_data <= io.iccm.rd_data @[quasar.scala 101:15] + io.iccm.wr_data <= ifu.io.iccm.wr_data @[quasar.scala 101:15] + io.iccm.wr_size <= ifu.io.iccm.wr_size @[quasar.scala 101:15] + io.iccm.rden <= ifu.io.iccm.rden @[quasar.scala 101:15] + io.iccm.wren <= ifu.io.iccm.wren @[quasar.scala 101:15] + io.iccm.correction_state <= ifu.io.iccm.correction_state @[quasar.scala 101:15] + io.iccm.buf_correct_ecc <= ifu.io.iccm.buf_correct_ecc @[quasar.scala 101:15] + io.iccm.rw_addr <= ifu.io.iccm.rw_addr @[quasar.scala 101:15] + ifu.io.exu_ifu.exu_bp.exu_mp_btag <= exu.io.exu_bp.exu_mp_btag @[quasar.scala 102:25] + ifu.io.exu_ifu.exu_bp.exu_mp_index <= exu.io.exu_bp.exu_mp_index @[quasar.scala 102:25] + ifu.io.exu_ifu.exu_bp.exu_mp_fghr <= exu.io.exu_bp.exu_mp_fghr @[quasar.scala 102:25] + ifu.io.exu_ifu.exu_bp.exu_mp_eghr <= exu.io.exu_bp.exu_mp_eghr @[quasar.scala 102:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.way <= exu.io.exu_bp.exu_mp_pkt.bits.way @[quasar.scala 102:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pja <= exu.io.exu_bp.exu_mp_pkt.bits.pja @[quasar.scala 102:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pret <= exu.io.exu_bp.exu_mp_pkt.bits.pret @[quasar.scala 102:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pcall <= exu.io.exu_bp.exu_mp_pkt.bits.pcall @[quasar.scala 102:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.prett <= exu.io.exu_bp.exu_mp_pkt.bits.prett @[quasar.scala 102:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.br_start_error <= exu.io.exu_bp.exu_mp_pkt.bits.br_start_error @[quasar.scala 102:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.br_error <= exu.io.exu_bp.exu_mp_pkt.bits.br_error @[quasar.scala 102:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.toffset <= exu.io.exu_bp.exu_mp_pkt.bits.toffset @[quasar.scala 102:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.hist <= exu.io.exu_bp.exu_mp_pkt.bits.hist @[quasar.scala 102:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pc4 <= exu.io.exu_bp.exu_mp_pkt.bits.pc4 @[quasar.scala 102:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.boffset <= exu.io.exu_bp.exu_mp_pkt.bits.boffset @[quasar.scala 102:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.ataken <= exu.io.exu_bp.exu_mp_pkt.bits.ataken @[quasar.scala 102:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.misp <= exu.io.exu_bp.exu_mp_pkt.bits.misp @[quasar.scala 102:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.valid <= exu.io.exu_bp.exu_mp_pkt.valid @[quasar.scala 102:25] + ifu.io.exu_ifu.exu_bp.exu_i0_br_way_r <= exu.io.exu_bp.exu_i0_br_way_r @[quasar.scala 102:25] + ifu.io.exu_ifu.exu_bp.exu_i0_br_fghr_r <= exu.io.exu_bp.exu_i0_br_fghr_r @[quasar.scala 102:25] + ifu.io.exu_ifu.exu_bp.exu_i0_br_index_r <= exu.io.exu_bp.exu_i0_br_index_r @[quasar.scala 102:25] + ifu.io.exu_ifu.exu_bp.exu_i0_br_fghr_r <= exu.io.exu_bp.exu_i0_br_fghr_r @[quasar.scala 103:42] + ifu.io.exu_ifu.exu_bp.exu_i0_br_index_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_index_r @[quasar.scala 104:43] + ifu.io.dec_tlu_flush_lower_wb <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[quasar.scala 105:33] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid @[quasar.scala 106:51] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid @[quasar.scala 106:51] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics @[quasar.scala 106:51] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata @[quasar.scala 106:51] + dec.reset <= io.core_rst_l @[quasar.scala 109:13] + dec.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 110:19] + dec.io.active_clk <= rvclkhdr_1.io.l1clk @[quasar.scala 111:21] + dec.io.lsu_fastint_stall_any <= lsu.io.lsu_fastint_stall_any @[quasar.scala 112:32] + dec.io.rst_vec <= io.rst_vec @[quasar.scala 113:18] + dec.io.nmi_int <= io.nmi_int @[quasar.scala 114:18] + dec.io.nmi_vec <= io.nmi_vec @[quasar.scala 115:18] + dec.io.i_cpu_halt_req <= io.i_cpu_halt_req @[quasar.scala 116:25] + dec.io.i_cpu_run_req <= io.i_cpu_run_req @[quasar.scala 117:24] + dec.io.core_id <= io.core_id @[quasar.scala 118:18] + dec.io.mpc_debug_halt_req <= io.mpc_debug_halt_req @[quasar.scala 119:29] + dec.io.mpc_debug_run_req <= io.mpc_debug_run_req @[quasar.scala 120:28] + dec.io.mpc_reset_run_req <= io.mpc_reset_run_req @[quasar.scala 121:28] + dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data @[quasar.scala 122:18] + dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_tag <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_tag @[quasar.scala 122:18] + dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_error <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_error @[quasar.scala 122:18] + dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_valid <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_valid @[quasar.scala 122:18] + dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_tag_r <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_tag_r @[quasar.scala 122:18] + dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_r <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_r @[quasar.scala 122:18] + dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_tag_m <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_tag_m @[quasar.scala 122:18] + dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_valid_m <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_valid_m @[quasar.scala 122:18] + dec.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_addr_any <= lsu.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_addr_any @[quasar.scala 122:18] + dec.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_store_any <= lsu.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_store_any @[quasar.scala 122:18] + dec.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_load_any <= lsu.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_load_any @[quasar.scala 122:18] + lsu.io.lsu_dec.tlu_busbuff.dec_tlu_sideeffect_posted_disable <= dec.io.lsu_dec.tlu_busbuff.dec_tlu_sideeffect_posted_disable @[quasar.scala 122:18] + lsu.io.lsu_dec.tlu_busbuff.dec_tlu_wb_coalescing_disable <= dec.io.lsu_dec.tlu_busbuff.dec_tlu_wb_coalescing_disable @[quasar.scala 122:18] + lsu.io.lsu_dec.tlu_busbuff.dec_tlu_external_ldfwd_disable <= dec.io.lsu_dec.tlu_busbuff.dec_tlu_external_ldfwd_disable @[quasar.scala 122:18] + dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_busy <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_busy @[quasar.scala 122:18] + dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_error <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_error @[quasar.scala 122:18] + dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_misaligned <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_misaligned @[quasar.scala 122:18] + dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_trxn <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_trxn @[quasar.scala 122:18] + dec.io.lsu_tlu.lsu_pmu_store_external_m <= lsu.io.lsu_tlu.lsu_pmu_store_external_m @[quasar.scala 123:18] + dec.io.lsu_tlu.lsu_pmu_load_external_m <= lsu.io.lsu_tlu.lsu_pmu_load_external_m @[quasar.scala 123:18] + dec.io.lsu_pmu_misaligned_m <= lsu.io.lsu_pmu_misaligned_m @[quasar.scala 124:31] + dec.io.dec_dma.tlu_dma.dma_iccm_stall_any <= dma_ctrl.io.dec_dma.tlu_dma.dma_iccm_stall_any @[quasar.scala 125:18] + dec.io.dec_dma.tlu_dma.dma_dccm_stall_any <= dma_ctrl.io.dec_dma.tlu_dma.dma_dccm_stall_any @[quasar.scala 125:18] + dma_ctrl.io.dec_dma.tlu_dma.dec_tlu_dma_qos_prty <= dec.io.dec_dma.tlu_dma.dec_tlu_dma_qos_prty @[quasar.scala 125:18] + dec.io.dec_dma.tlu_dma.dma_pmu_any_write <= dma_ctrl.io.dec_dma.tlu_dma.dma_pmu_any_write @[quasar.scala 125:18] + dec.io.dec_dma.tlu_dma.dma_pmu_any_read <= dma_ctrl.io.dec_dma.tlu_dma.dma_pmu_any_read @[quasar.scala 125:18] + dec.io.dec_dma.tlu_dma.dma_pmu_dccm_write <= dma_ctrl.io.dec_dma.tlu_dma.dma_pmu_dccm_write @[quasar.scala 125:18] + dec.io.dec_dma.tlu_dma.dma_pmu_dccm_read <= dma_ctrl.io.dec_dma.tlu_dma.dma_pmu_dccm_read @[quasar.scala 125:18] + dec.io.dec_dma.dctl_dma.dma_dccm_stall_any <= dma_ctrl.io.dec_dma.dctl_dma.dma_dccm_stall_any @[quasar.scala 125:18] + dec.io.lsu_fir_addr <= lsu.io.lsu_fir_addr @[quasar.scala 127:23] + dec.io.lsu_fir_error <= lsu.io.lsu_fir_error @[quasar.scala 128:24] + dec.io.lsu_trigger_match_m <= lsu.io.lsu_trigger_match_m @[quasar.scala 129:30] + dec.io.dec_dbg.dbg_dctl.dbg_cmd_wrdata <= dbg.io.dbg_dec.dbg_dctl.dbg_cmd_wrdata @[quasar.scala 130:18] + dec.io.dec_dbg.dbg_ib.dbg_cmd_addr <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_addr @[quasar.scala 130:18] + dec.io.dec_dbg.dbg_ib.dbg_cmd_type <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_type @[quasar.scala 130:18] + dec.io.dec_dbg.dbg_ib.dbg_cmd_write <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_write @[quasar.scala 130:18] + dec.io.dec_dbg.dbg_ib.dbg_cmd_valid <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_valid @[quasar.scala 130:18] + dec.io.lsu_idle_any <= lsu.io.lsu_idle_any @[quasar.scala 131:23] + dec.io.lsu_error_pkt_r.bits.addr <= lsu.io.lsu_error_pkt_r.bits.addr @[quasar.scala 132:26] + dec.io.lsu_error_pkt_r.bits.mscause <= lsu.io.lsu_error_pkt_r.bits.mscause @[quasar.scala 132:26] + dec.io.lsu_error_pkt_r.bits.exc_type <= lsu.io.lsu_error_pkt_r.bits.exc_type @[quasar.scala 132:26] + dec.io.lsu_error_pkt_r.bits.inst_type <= lsu.io.lsu_error_pkt_r.bits.inst_type @[quasar.scala 132:26] + dec.io.lsu_error_pkt_r.bits.single_ecc_error <= lsu.io.lsu_error_pkt_r.bits.single_ecc_error @[quasar.scala 132:26] + dec.io.lsu_error_pkt_r.valid <= lsu.io.lsu_error_pkt_r.valid @[quasar.scala 132:26] + dec.io.lsu_single_ecc_error_incr <= lsu.io.lsu_single_ecc_error_incr @[quasar.scala 133:36] + dec.io.exu_div_result <= exu.io.exu_div_result @[quasar.scala 134:25] + dec.io.exu_div_wren <= exu.io.exu_div_wren @[quasar.scala 135:23] + dec.io.lsu_result_m <= lsu.io.lsu_result_m @[quasar.scala 136:23] + dec.io.lsu_result_corr_r <= lsu.io.lsu_result_corr_r @[quasar.scala 137:28] + dec.io.lsu_load_stall_any <= lsu.io.lsu_load_stall_any @[quasar.scala 138:29] + dec.io.lsu_store_stall_any <= lsu.io.lsu_store_stall_any @[quasar.scala 139:30] + dec.io.iccm_dma_sb_error <= ifu.io.iccm_dma_sb_error @[quasar.scala 140:28] + dec.io.exu_flush_final <= exu.io.exu_flush_final @[quasar.scala 141:26] + dec.io.soft_int <= io.soft_int @[quasar.scala 143:19] + dec.io.dbg_halt_req <= dbg.io.dbg_halt_req @[quasar.scala 144:23] + dec.io.dbg_resume_req <= dbg.io.dbg_resume_req @[quasar.scala 145:25] + dec.io.exu_i0_br_way_r <= exu.io.exu_bp.exu_i0_br_way_r @[quasar.scala 146:26] + dec.io.timer_int <= io.timer_int @[quasar.scala 147:20] + dec.io.scan_mode <= io.scan_mode @[quasar.scala 148:20] + exu.io.dec_exu.gpr_exu.gpr_i0_rs2_d <= dec.io.dec_exu.gpr_exu.gpr_i0_rs2_d @[quasar.scala 151:18] + exu.io.dec_exu.gpr_exu.gpr_i0_rs1_d <= dec.io.dec_exu.gpr_exu.gpr_i0_rs1_d @[quasar.scala 151:18] + exu.io.dec_exu.ib_exu.dec_debug_wdata_rs1_d <= dec.io.dec_exu.ib_exu.dec_debug_wdata_rs1_d @[quasar.scala 151:18] + exu.io.dec_exu.ib_exu.dec_i0_pc_d <= dec.io.dec_exu.ib_exu.dec_i0_pc_d @[quasar.scala 151:18] + dec.io.dec_exu.tlu_exu.exu_npc_r <= exu.io.dec_exu.tlu_exu.exu_npc_r @[quasar.scala 151:18] + dec.io.dec_exu.tlu_exu.exu_pmu_i0_pc4 <= exu.io.dec_exu.tlu_exu.exu_pmu_i0_pc4 @[quasar.scala 151:18] + dec.io.dec_exu.tlu_exu.exu_pmu_i0_br_ataken <= exu.io.dec_exu.tlu_exu.exu_pmu_i0_br_ataken @[quasar.scala 151:18] + dec.io.dec_exu.tlu_exu.exu_pmu_i0_br_misp <= exu.io.dec_exu.tlu_exu.exu_pmu_i0_br_misp @[quasar.scala 151:18] + dec.io.dec_exu.tlu_exu.exu_i0_br_middle_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_middle_r @[quasar.scala 151:18] + dec.io.dec_exu.tlu_exu.exu_i0_br_mp_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_mp_r @[quasar.scala 151:18] + dec.io.dec_exu.tlu_exu.exu_i0_br_valid_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_valid_r @[quasar.scala 151:18] + dec.io.dec_exu.tlu_exu.exu_i0_br_index_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_index_r @[quasar.scala 151:18] + dec.io.dec_exu.tlu_exu.exu_i0_br_start_error_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_start_error_r @[quasar.scala 151:18] + dec.io.dec_exu.tlu_exu.exu_i0_br_error_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_error_r @[quasar.scala 151:18] + dec.io.dec_exu.tlu_exu.exu_i0_br_hist_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_hist_r @[quasar.scala 151:18] + exu.io.dec_exu.tlu_exu.dec_tlu_flush_path_r <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_path_r @[quasar.scala 151:18] + exu.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[quasar.scala 151:18] + exu.io.dec_exu.tlu_exu.dec_tlu_meihap <= dec.io.dec_exu.tlu_exu.dec_tlu_meihap @[quasar.scala 151:18] + dec.io.dec_exu.decode_exu.exu_csr_rs1_x <= exu.io.dec_exu.decode_exu.exu_csr_rs1_x @[quasar.scala 151:18] + dec.io.dec_exu.decode_exu.exu_i0_result_x <= exu.io.dec_exu.decode_exu.exu_i0_result_x @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.dec_extint_stall <= dec.io.dec_exu.decode_exu.dec_extint_stall @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.pred_correct_npc_x <= dec.io.dec_exu.decode_exu.pred_correct_npc_x @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.mul_p.bits.bfp <= dec.io.dec_exu.decode_exu.mul_p.bits.bfp @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.mul_p.bits.crc32c_w <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32c_w @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.mul_p.bits.crc32c_h <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32c_h @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.mul_p.bits.crc32c_b <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32c_b @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.mul_p.bits.crc32_w <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32_w @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.mul_p.bits.crc32_h <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32_h @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.mul_p.bits.crc32_b <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32_b @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.mul_p.bits.unshfl <= dec.io.dec_exu.decode_exu.mul_p.bits.unshfl @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.mul_p.bits.shfl <= dec.io.dec_exu.decode_exu.mul_p.bits.shfl @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.mul_p.bits.grev <= dec.io.dec_exu.decode_exu.mul_p.bits.grev @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.mul_p.bits.clmulr <= dec.io.dec_exu.decode_exu.mul_p.bits.clmulr @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.mul_p.bits.clmulh <= dec.io.dec_exu.decode_exu.mul_p.bits.clmulh @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.mul_p.bits.clmul <= dec.io.dec_exu.decode_exu.mul_p.bits.clmul @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.mul_p.bits.bdep <= dec.io.dec_exu.decode_exu.mul_p.bits.bdep @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.mul_p.bits.bext <= dec.io.dec_exu.decode_exu.mul_p.bits.bext @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.mul_p.bits.low <= dec.io.dec_exu.decode_exu.mul_p.bits.low @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.mul_p.bits.rs2_sign <= dec.io.dec_exu.decode_exu.mul_p.bits.rs2_sign @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.mul_p.bits.rs1_sign <= dec.io.dec_exu.decode_exu.mul_p.bits.rs1_sign @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.mul_p.valid <= dec.io.dec_exu.decode_exu.mul_p.valid @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.dec_i0_select_pc_d <= dec.io.dec_exu.decode_exu.dec_i0_select_pc_d @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.dec_i0_rs2_bypass_data_d <= dec.io.dec_exu.decode_exu.dec_i0_rs2_bypass_data_d @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.dec_i0_rs1_bypass_data_d <= dec.io.dec_exu.decode_exu.dec_i0_rs1_bypass_data_d @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.dec_i0_immed_d <= dec.io.dec_exu.decode_exu.dec_i0_immed_d @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.dec_i0_rs2_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs2_en_d @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.dec_i0_rs1_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs1_en_d @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.i0_predict_btag_d <= dec.io.dec_exu.decode_exu.i0_predict_btag_d @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.i0_predict_index_d <= dec.io.dec_exu.decode_exu.i0_predict_index_d @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.i0_predict_fghr_d <= dec.io.dec_exu.decode_exu.i0_predict_fghr_d @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.way <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.way @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pja <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pja @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pret <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pret @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pcall <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pcall @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.prett <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.prett @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_start_error <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_start_error @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_error <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_error @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.toffset <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.toffset @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.hist <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.hist @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pc4 <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pc4 @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.boffset <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.boffset @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.ataken <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.ataken @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.misp <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.misp @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.valid <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.valid @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.i0_ap.csr_imm <= dec.io.dec_exu.decode_exu.i0_ap.csr_imm @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.i0_ap.csr_write <= dec.io.dec_exu.decode_exu.i0_ap.csr_write @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.i0_ap.predict_nt <= dec.io.dec_exu.decode_exu.i0_ap.predict_nt @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.i0_ap.predict_t <= dec.io.dec_exu.decode_exu.i0_ap.predict_t @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.i0_ap.jal <= dec.io.dec_exu.decode_exu.i0_ap.jal @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.i0_ap.unsign <= dec.io.dec_exu.decode_exu.i0_ap.unsign @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.i0_ap.slt <= dec.io.dec_exu.decode_exu.i0_ap.slt @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.i0_ap.sub <= dec.io.dec_exu.decode_exu.i0_ap.sub @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.i0_ap.add <= dec.io.dec_exu.decode_exu.i0_ap.add @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.i0_ap.bge <= dec.io.dec_exu.decode_exu.i0_ap.bge @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.i0_ap.blt <= dec.io.dec_exu.decode_exu.i0_ap.blt @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.i0_ap.bne <= dec.io.dec_exu.decode_exu.i0_ap.bne @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.i0_ap.beq <= dec.io.dec_exu.decode_exu.i0_ap.beq @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.i0_ap.sra <= dec.io.dec_exu.decode_exu.i0_ap.sra @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.i0_ap.srl <= dec.io.dec_exu.decode_exu.i0_ap.srl @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.i0_ap.sll <= dec.io.dec_exu.decode_exu.i0_ap.sll @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.i0_ap.lxor <= dec.io.dec_exu.decode_exu.i0_ap.lxor @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.i0_ap.lor <= dec.io.dec_exu.decode_exu.i0_ap.lor @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.i0_ap.land <= dec.io.dec_exu.decode_exu.i0_ap.land @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.dec_ctl_en <= dec.io.dec_exu.decode_exu.dec_ctl_en @[quasar.scala 151:18] + exu.io.dec_exu.decode_exu.dec_data_en <= dec.io.dec_exu.decode_exu.dec_data_en @[quasar.scala 151:18] + exu.io.dec_exu.dec_div.dec_div_cancel <= dec.io.dec_exu.dec_div.dec_div_cancel @[quasar.scala 151:18] + exu.io.dec_exu.dec_div.div_p.bits.rem <= dec.io.dec_exu.dec_div.div_p.bits.rem @[quasar.scala 151:18] + exu.io.dec_exu.dec_div.div_p.bits.unsign <= dec.io.dec_exu.dec_div.div_p.bits.unsign @[quasar.scala 151:18] + exu.io.dec_exu.dec_div.div_p.valid <= dec.io.dec_exu.dec_div.div_p.valid @[quasar.scala 151:18] + dec.io.dec_exu.dec_alu.exu_i0_pc_x <= exu.io.dec_exu.dec_alu.exu_i0_pc_x @[quasar.scala 151:18] + exu.io.dec_exu.dec_alu.dec_i0_br_immed_d <= dec.io.dec_exu.dec_alu.dec_i0_br_immed_d @[quasar.scala 151:18] + exu.io.dec_exu.dec_alu.dec_csr_ren_d <= dec.io.dec_exu.dec_alu.dec_csr_ren_d @[quasar.scala 151:18] + exu.io.dec_exu.dec_alu.dec_i0_alu_decode_d <= dec.io.dec_exu.dec_alu.dec_i0_alu_decode_d @[quasar.scala 151:18] + exu.reset <= io.core_rst_l @[quasar.scala 152:13] + exu.io.scan_mode <= io.scan_mode @[quasar.scala 153:20] + exu.io.dbg_cmd_wrdata <= dbg.io.dbg_dec.dbg_dctl.dbg_cmd_wrdata @[quasar.scala 154:25] + lsu.reset <= io.core_rst_l @[quasar.scala 157:13] + lsu.io.clk_override <= dec.io.dec_tlu_lsu_clk_override @[quasar.scala 158:23] + lsu.io.dec_tlu_flush_lower_r <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[quasar.scala 159:32] + lsu.io.dec_tlu_i0_kill_writeb_r <= dec.io.dec_tlu_i0_kill_writeb_r @[quasar.scala 160:35] + lsu.io.dec_tlu_force_halt <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt @[quasar.scala 161:29] + lsu.io.dec_tlu_core_ecc_disable <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable @[quasar.scala 162:35] + lsu.io.lsu_exu.exu_lsu_rs2_d <= exu.io.lsu_exu.exu_lsu_rs2_d @[quasar.scala 163:18] + lsu.io.lsu_exu.exu_lsu_rs1_d <= exu.io.lsu_exu.exu_lsu_rs1_d @[quasar.scala 163:18] + lsu.io.dec_lsu_offset_d <= dec.io.dec_lsu_offset_d @[quasar.scala 164:27] + lsu.io.lsu_p.bits.store_data_bypass_m <= dec.io.lsu_p.bits.store_data_bypass_m @[quasar.scala 165:16] + lsu.io.lsu_p.bits.load_ldst_bypass_d <= dec.io.lsu_p.bits.load_ldst_bypass_d @[quasar.scala 165:16] + lsu.io.lsu_p.bits.store_data_bypass_d <= dec.io.lsu_p.bits.store_data_bypass_d @[quasar.scala 165:16] + lsu.io.lsu_p.bits.dma <= dec.io.lsu_p.bits.dma @[quasar.scala 165:16] + lsu.io.lsu_p.bits.unsign <= dec.io.lsu_p.bits.unsign @[quasar.scala 165:16] + lsu.io.lsu_p.bits.store <= dec.io.lsu_p.bits.store @[quasar.scala 165:16] + lsu.io.lsu_p.bits.load <= dec.io.lsu_p.bits.load @[quasar.scala 165:16] + lsu.io.lsu_p.bits.dword <= dec.io.lsu_p.bits.dword @[quasar.scala 165:16] + lsu.io.lsu_p.bits.word <= dec.io.lsu_p.bits.word @[quasar.scala 165:16] + lsu.io.lsu_p.bits.half <= dec.io.lsu_p.bits.half @[quasar.scala 165:16] + lsu.io.lsu_p.bits.by <= dec.io.lsu_p.bits.by @[quasar.scala 165:16] + lsu.io.lsu_p.bits.fast_int <= dec.io.lsu_p.bits.fast_int @[quasar.scala 165:16] + lsu.io.lsu_p.valid <= dec.io.lsu_p.valid @[quasar.scala 165:16] + lsu.io.dec_lsu_valid_raw_d <= dec.io.dec_lsu_valid_raw_d @[quasar.scala 166:30] + lsu.io.dec_tlu_mrac_ff <= dec.io.ifu_dec.dec_ifc.dec_tlu_mrac_ff @[quasar.scala 167:26] + lsu.io.trigger_pkt_any[0].tdata2 <= dec.io.trigger_pkt_any[0].tdata2 @[quasar.scala 168:26] + lsu.io.trigger_pkt_any[0].m <= dec.io.trigger_pkt_any[0].m @[quasar.scala 168:26] + lsu.io.trigger_pkt_any[0].execute <= dec.io.trigger_pkt_any[0].execute @[quasar.scala 168:26] + lsu.io.trigger_pkt_any[0].load <= dec.io.trigger_pkt_any[0].load @[quasar.scala 168:26] + lsu.io.trigger_pkt_any[0].store <= dec.io.trigger_pkt_any[0].store @[quasar.scala 168:26] + lsu.io.trigger_pkt_any[0].match_pkt <= dec.io.trigger_pkt_any[0].match_pkt @[quasar.scala 168:26] + lsu.io.trigger_pkt_any[0].select <= dec.io.trigger_pkt_any[0].select @[quasar.scala 168:26] + lsu.io.trigger_pkt_any[1].tdata2 <= dec.io.trigger_pkt_any[1].tdata2 @[quasar.scala 168:26] + lsu.io.trigger_pkt_any[1].m <= dec.io.trigger_pkt_any[1].m @[quasar.scala 168:26] + lsu.io.trigger_pkt_any[1].execute <= dec.io.trigger_pkt_any[1].execute @[quasar.scala 168:26] + lsu.io.trigger_pkt_any[1].load <= dec.io.trigger_pkt_any[1].load @[quasar.scala 168:26] + lsu.io.trigger_pkt_any[1].store <= dec.io.trigger_pkt_any[1].store @[quasar.scala 168:26] + lsu.io.trigger_pkt_any[1].match_pkt <= dec.io.trigger_pkt_any[1].match_pkt @[quasar.scala 168:26] + lsu.io.trigger_pkt_any[1].select <= dec.io.trigger_pkt_any[1].select @[quasar.scala 168:26] + lsu.io.trigger_pkt_any[2].tdata2 <= dec.io.trigger_pkt_any[2].tdata2 @[quasar.scala 168:26] + lsu.io.trigger_pkt_any[2].m <= dec.io.trigger_pkt_any[2].m @[quasar.scala 168:26] + lsu.io.trigger_pkt_any[2].execute <= dec.io.trigger_pkt_any[2].execute @[quasar.scala 168:26] + lsu.io.trigger_pkt_any[2].load <= dec.io.trigger_pkt_any[2].load @[quasar.scala 168:26] + lsu.io.trigger_pkt_any[2].store <= dec.io.trigger_pkt_any[2].store @[quasar.scala 168:26] + lsu.io.trigger_pkt_any[2].match_pkt <= dec.io.trigger_pkt_any[2].match_pkt @[quasar.scala 168:26] + lsu.io.trigger_pkt_any[2].select <= dec.io.trigger_pkt_any[2].select @[quasar.scala 168:26] + lsu.io.trigger_pkt_any[3].tdata2 <= dec.io.trigger_pkt_any[3].tdata2 @[quasar.scala 168:26] + lsu.io.trigger_pkt_any[3].m <= dec.io.trigger_pkt_any[3].m @[quasar.scala 168:26] + lsu.io.trigger_pkt_any[3].execute <= dec.io.trigger_pkt_any[3].execute @[quasar.scala 168:26] + lsu.io.trigger_pkt_any[3].load <= dec.io.trigger_pkt_any[3].load @[quasar.scala 168:26] + lsu.io.trigger_pkt_any[3].store <= dec.io.trigger_pkt_any[3].store @[quasar.scala 168:26] + lsu.io.trigger_pkt_any[3].match_pkt <= dec.io.trigger_pkt_any[3].match_pkt @[quasar.scala 168:26] + lsu.io.trigger_pkt_any[3].select <= dec.io.trigger_pkt_any[3].select @[quasar.scala 168:26] + lsu.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[quasar.scala 170:25] + lsu.io.lsu_dma.dma_mem_tag <= dma_ctrl.io.lsu_dma.dma_mem_tag @[quasar.scala 171:18] + dma_ctrl.io.lsu_dma.dccm_ready <= lsu.io.lsu_dma.dccm_ready @[quasar.scala 171:18] + dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_rdata <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_rdata @[quasar.scala 171:18] + dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag @[quasar.scala 171:18] + dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error @[quasar.scala 171:18] + dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid @[quasar.scala 171:18] + lsu.io.lsu_dma.dma_dccm_ctl.dma_mem_wdata <= dma_ctrl.io.lsu_dma.dma_dccm_ctl.dma_mem_wdata @[quasar.scala 171:18] + lsu.io.lsu_dma.dma_dccm_ctl.dma_mem_addr <= dma_ctrl.io.lsu_dma.dma_dccm_ctl.dma_mem_addr @[quasar.scala 171:18] + lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_wdata <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_wdata @[quasar.scala 171:18] + lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_write <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_write @[quasar.scala 171:18] + lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_sz <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_sz @[quasar.scala 171:18] + lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_addr <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_addr @[quasar.scala 171:18] + lsu.io.lsu_dma.dma_lsc_ctl.dma_dccm_req <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_dccm_req @[quasar.scala 171:18] + lsu.io.scan_mode <= io.scan_mode @[quasar.scala 172:20] + lsu.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 173:19] + dbg.reset <= io.core_rst_l @[quasar.scala 176:13] + node _T_8 = mux(dma_ctrl.io.dma_dbg_cmd_done, dma_ctrl.io.dma_dbg_rddata, dec.io.dec_dbg_rddata) @[quasar.scala 177:32] + dbg.io.core_dbg_rddata <= _T_8 @[quasar.scala 177:26] + node _T_9 = or(dma_ctrl.io.dma_dbg_cmd_done, dec.io.dec_dbg_cmd_done) @[quasar.scala 178:60] + dbg.io.core_dbg_cmd_done <= _T_9 @[quasar.scala 178:28] + node _T_10 = or(dma_ctrl.io.dma_dbg_cmd_fail, dec.io.dec_dbg_cmd_fail) @[quasar.scala 179:60] + dbg.io.core_dbg_cmd_fail <= _T_10 @[quasar.scala 179:28] + dbg.io.dec_tlu_debug_mode <= dec.io.dec_tlu_debug_mode @[quasar.scala 180:29] + dbg.io.dec_tlu_dbg_halted <= dec.io.dec_tlu_dbg_halted @[quasar.scala 181:29] + dbg.io.dec_tlu_mpc_halted_only <= dec.io.dec_tlu_mpc_halted_only @[quasar.scala 182:34] + dbg.io.dec_tlu_resume_ack <= dec.io.dec_tlu_resume_ack @[quasar.scala 183:29] + dbg.io.dmi_reg_en <= io.dmi_reg_en @[quasar.scala 184:21] + dbg.io.dmi_reg_addr <= io.dmi_reg_addr @[quasar.scala 185:23] + dbg.io.dmi_reg_wr_en <= io.dmi_reg_wr_en @[quasar.scala 186:24] + dbg.io.dmi_reg_wdata <= io.dmi_reg_wdata @[quasar.scala 187:24] + dbg.io.dbg_bus_clk_en <= io.dbg_bus_clk_en @[quasar.scala 188:25] + node _T_11 = asUInt(io.dbg_rst_l) @[quasar.scala 189:42] + dbg.io.dbg_rst_l <= _T_11 @[quasar.scala 189:20] + dbg.io.clk_override <= dec.io.dec_tlu_misc_clk_override @[quasar.scala 190:23] + dbg.io.scan_mode <= io.scan_mode @[quasar.scala 191:20] + dma_ctrl.reset <= io.core_rst_l @[quasar.scala 195:18] + dma_ctrl.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 196:24] + dma_ctrl.io.dma_bus_clk_en <= io.dma_bus_clk_en @[quasar.scala 197:30] + dma_ctrl.io.clk_override <= dec.io.dec_tlu_misc_clk_override @[quasar.scala 198:28] + dma_ctrl.io.scan_mode <= io.scan_mode @[quasar.scala 199:25] + dma_ctrl.io.dbg_dma.dbg_dctl.dbg_cmd_wrdata <= dbg.io.dbg_dma.dbg_dctl.dbg_cmd_wrdata @[quasar.scala 200:23] + dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_addr <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_addr @[quasar.scala 200:23] + dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_type <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_type @[quasar.scala 200:23] + dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_write <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_write @[quasar.scala 200:23] + dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_valid <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_valid @[quasar.scala 200:23] + dbg.io.dbg_dma_io.dma_dbg_ready <= dma_ctrl.io.dbg_dma_io.dma_dbg_ready @[quasar.scala 201:26] + dma_ctrl.io.dbg_dma_io.dbg_dma_bubble <= dbg.io.dbg_dma_io.dbg_dma_bubble @[quasar.scala 201:26] + dma_ctrl.io.dbg_cmd_size <= dbg.io.dbg_cmd_size @[quasar.scala 202:28] + dma_ctrl.io.iccm_dma_rvalid <= ifu.io.iccm_dma_rvalid @[quasar.scala 203:31] + dma_ctrl.io.iccm_dma_rtag <= ifu.io.iccm_dma_rtag @[quasar.scala 204:29] + dma_ctrl.io.iccm_dma_rdata <= ifu.io.iccm_dma_rdata @[quasar.scala 205:30] + dma_ctrl.io.iccm_ready <= ifu.io.iccm_ready @[quasar.scala 206:26] + dma_ctrl.io.iccm_dma_ecc_error <= ifu.io.iccm_dma_ecc_error @[quasar.scala 207:34] + pic_ctrl_inst.io.scan_mode <= io.scan_mode @[quasar.scala 210:30] + pic_ctrl_inst.reset <= io.core_rst_l @[quasar.scala 211:23] + pic_ctrl_inst.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 212:29] + pic_ctrl_inst.io.active_clk <= rvclkhdr_1.io.l1clk @[quasar.scala 213:31] + pic_ctrl_inst.io.clk_override <= dec.io.dec_tlu_pic_clk_override @[quasar.scala 214:33] + pic_ctrl_inst.io.extintsrc_req <= io.extintsrc_req @[quasar.scala 215:34] + lsu.io.lsu_pic.picm_rd_data <= pic_ctrl_inst.io.lsu_pic.picm_rd_data @[quasar.scala 216:28] + pic_ctrl_inst.io.lsu_pic.picm_wr_data <= lsu.io.lsu_pic.picm_wr_data @[quasar.scala 216:28] + pic_ctrl_inst.io.lsu_pic.picm_wraddr <= lsu.io.lsu_pic.picm_wraddr @[quasar.scala 216:28] + pic_ctrl_inst.io.lsu_pic.picm_rdaddr <= lsu.io.lsu_pic.picm_rdaddr @[quasar.scala 216:28] + pic_ctrl_inst.io.lsu_pic.picm_mken <= lsu.io.lsu_pic.picm_mken @[quasar.scala 216:28] + pic_ctrl_inst.io.lsu_pic.picm_rden <= lsu.io.lsu_pic.picm_rden @[quasar.scala 216:28] + pic_ctrl_inst.io.lsu_pic.picm_wren <= lsu.io.lsu_pic.picm_wren @[quasar.scala 216:28] + dec.io.dec_pic.mexintpend <= pic_ctrl_inst.io.dec_pic.mexintpend @[quasar.scala 217:28] + pic_ctrl_inst.io.dec_pic.dec_tlu_meipt <= dec.io.dec_pic.dec_tlu_meipt @[quasar.scala 217:28] + pic_ctrl_inst.io.dec_pic.dec_tlu_meicurpl <= dec.io.dec_pic.dec_tlu_meicurpl @[quasar.scala 217:28] + dec.io.dec_pic.mhwakeup <= pic_ctrl_inst.io.dec_pic.mhwakeup @[quasar.scala 217:28] + dec.io.dec_pic.pic_pl <= pic_ctrl_inst.io.dec_pic.pic_pl @[quasar.scala 217:28] + dec.io.dec_pic.pic_claimid <= pic_ctrl_inst.io.dec_pic.pic_claimid @[quasar.scala 217:28] + io.rv_trace_pkt.rv_i_tval_ip <= dec.io.rv_trace_pkt.rv_i_tval_ip @[quasar.scala 219:19] + io.rv_trace_pkt.rv_i_interrupt_ip <= dec.io.rv_trace_pkt.rv_i_interrupt_ip @[quasar.scala 219:19] + io.rv_trace_pkt.rv_i_ecause_ip <= dec.io.rv_trace_pkt.rv_i_ecause_ip @[quasar.scala 219:19] + io.rv_trace_pkt.rv_i_exception_ip <= dec.io.rv_trace_pkt.rv_i_exception_ip @[quasar.scala 219:19] + io.rv_trace_pkt.rv_i_address_ip <= dec.io.rv_trace_pkt.rv_i_address_ip @[quasar.scala 219:19] + io.rv_trace_pkt.rv_i_insn_ip <= dec.io.rv_trace_pkt.rv_i_insn_ip @[quasar.scala 219:19] + io.rv_trace_pkt.rv_i_valid_ip <= dec.io.rv_trace_pkt.rv_i_valid_ip @[quasar.scala 219:19] + io.dccm_clk_override <= dec.io.dec_tlu_dccm_clk_override @[quasar.scala 222:24] + io.icm_clk_override <= dec.io.dec_tlu_icm_clk_override @[quasar.scala 223:23] + io.dec_tlu_core_ecc_disable <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable @[quasar.scala 224:31] + io.o_cpu_halt_ack <= dec.io.o_cpu_halt_ack @[quasar.scala 225:21] + io.o_cpu_halt_status <= dec.io.o_cpu_halt_status @[quasar.scala 226:24] + io.o_cpu_run_ack <= dec.io.o_cpu_run_ack @[quasar.scala 227:20] + io.o_debug_mode_status <= dec.io.o_debug_mode_status @[quasar.scala 228:26] + io.mpc_debug_halt_ack <= dec.io.mpc_debug_halt_ack @[quasar.scala 229:25] + io.mpc_debug_run_ack <= dec.io.mpc_debug_run_ack @[quasar.scala 230:24] + io.debug_brkpt_status <= dec.io.debug_brkpt_status @[quasar.scala 231:25] + io.dec_tlu_perfcnt0 <= dec.io.dec_tlu_perfcnt0 @[quasar.scala 232:23] + io.dec_tlu_perfcnt1 <= dec.io.dec_tlu_perfcnt1 @[quasar.scala 233:23] + io.dec_tlu_perfcnt2 <= dec.io.dec_tlu_perfcnt2 @[quasar.scala 234:23] + io.dec_tlu_perfcnt3 <= dec.io.dec_tlu_perfcnt3 @[quasar.scala 235:23] + io.dmi_reg_rdata <= dbg.io.dmi_reg_rdata @[quasar.scala 236:20] + lsu.io.dccm.rd_data_hi <= io.dccm.rd_data_hi @[quasar.scala 239:11] + lsu.io.dccm.rd_data_lo <= io.dccm.rd_data_lo @[quasar.scala 239:11] + io.dccm.wr_data_hi <= lsu.io.dccm.wr_data_hi @[quasar.scala 239:11] + io.dccm.wr_data_lo <= lsu.io.dccm.wr_data_lo @[quasar.scala 239:11] + io.dccm.rd_addr_hi <= lsu.io.dccm.rd_addr_hi @[quasar.scala 239:11] + io.dccm.rd_addr_lo <= lsu.io.dccm.rd_addr_lo @[quasar.scala 239:11] + io.dccm.wr_addr_hi <= lsu.io.dccm.wr_addr_hi @[quasar.scala 239:11] + io.dccm.wr_addr_lo <= lsu.io.dccm.wr_addr_lo @[quasar.scala 239:11] + io.dccm.rden <= lsu.io.dccm.rden @[quasar.scala 239:11] + io.dccm.wren <= lsu.io.dccm.wren @[quasar.scala 239:11] + wire _T_12 : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}} @[quasar.scala 278:42] + _T_12.out.hwdata <= UInt<64>("h00") @[quasar.scala 278:42] + _T_12.out.hwrite <= UInt<1>("h00") @[quasar.scala 278:42] + _T_12.out.htrans <= UInt<2>("h00") @[quasar.scala 278:42] + _T_12.out.hsize <= UInt<3>("h00") @[quasar.scala 278:42] + _T_12.out.hprot <= UInt<4>("h00") @[quasar.scala 278:42] + _T_12.out.hmastlock <= UInt<1>("h00") @[quasar.scala 278:42] + _T_12.out.hburst <= UInt<3>("h00") @[quasar.scala 278:42] + _T_12.out.haddr <= UInt<32>("h00") @[quasar.scala 278:42] + _T_12.in.hresp <= UInt<1>("h00") @[quasar.scala 278:42] + _T_12.in.hready <= UInt<1>("h00") @[quasar.scala 278:42] + _T_12.in.hrdata <= UInt<64>("h00") @[quasar.scala 278:42] + io.lsu_ahb.out.hwdata <= _T_12.out.hwdata @[quasar.scala 278:27] + io.lsu_ahb.out.hwrite <= _T_12.out.hwrite @[quasar.scala 278:27] + io.lsu_ahb.out.htrans <= _T_12.out.htrans @[quasar.scala 278:27] + io.lsu_ahb.out.hsize <= _T_12.out.hsize @[quasar.scala 278:27] + io.lsu_ahb.out.hprot <= _T_12.out.hprot @[quasar.scala 278:27] + io.lsu_ahb.out.hmastlock <= _T_12.out.hmastlock @[quasar.scala 278:27] + io.lsu_ahb.out.hburst <= _T_12.out.hburst @[quasar.scala 278:27] + io.lsu_ahb.out.haddr <= _T_12.out.haddr @[quasar.scala 278:27] + _T_12.in.hresp <= io.lsu_ahb.in.hresp @[quasar.scala 278:27] + _T_12.in.hready <= io.lsu_ahb.in.hready @[quasar.scala 278:27] + _T_12.in.hrdata <= io.lsu_ahb.in.hrdata @[quasar.scala 278:27] + wire _T_13 : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}} @[quasar.scala 279:42] + _T_13.out.hwdata <= UInt<64>("h00") @[quasar.scala 279:42] + _T_13.out.hwrite <= UInt<1>("h00") @[quasar.scala 279:42] + _T_13.out.htrans <= UInt<2>("h00") @[quasar.scala 279:42] + _T_13.out.hsize <= UInt<3>("h00") @[quasar.scala 279:42] + _T_13.out.hprot <= UInt<4>("h00") @[quasar.scala 279:42] + _T_13.out.hmastlock <= UInt<1>("h00") @[quasar.scala 279:42] + _T_13.out.hburst <= UInt<3>("h00") @[quasar.scala 279:42] + _T_13.out.haddr <= UInt<32>("h00") @[quasar.scala 279:42] + _T_13.in.hresp <= UInt<1>("h00") @[quasar.scala 279:42] + _T_13.in.hready <= UInt<1>("h00") @[quasar.scala 279:42] + _T_13.in.hrdata <= UInt<64>("h00") @[quasar.scala 279:42] + io.ifu_ahb.out.hwdata <= _T_13.out.hwdata @[quasar.scala 279:27] + io.ifu_ahb.out.hwrite <= _T_13.out.hwrite @[quasar.scala 279:27] + io.ifu_ahb.out.htrans <= _T_13.out.htrans @[quasar.scala 279:27] + io.ifu_ahb.out.hsize <= _T_13.out.hsize @[quasar.scala 279:27] + io.ifu_ahb.out.hprot <= _T_13.out.hprot @[quasar.scala 279:27] + io.ifu_ahb.out.hmastlock <= _T_13.out.hmastlock @[quasar.scala 279:27] + io.ifu_ahb.out.hburst <= _T_13.out.hburst @[quasar.scala 279:27] + io.ifu_ahb.out.haddr <= _T_13.out.haddr @[quasar.scala 279:27] + _T_13.in.hresp <= io.ifu_ahb.in.hresp @[quasar.scala 279:27] + _T_13.in.hready <= io.ifu_ahb.in.hready @[quasar.scala 279:27] + _T_13.in.hrdata <= io.ifu_ahb.in.hrdata @[quasar.scala 279:27] + wire _T_14 : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}} @[quasar.scala 280:42] + _T_14.out.hwdata <= UInt<64>("h00") @[quasar.scala 280:42] + _T_14.out.hwrite <= UInt<1>("h00") @[quasar.scala 280:42] + _T_14.out.htrans <= UInt<2>("h00") @[quasar.scala 280:42] + _T_14.out.hsize <= UInt<3>("h00") @[quasar.scala 280:42] + _T_14.out.hprot <= UInt<4>("h00") @[quasar.scala 280:42] + _T_14.out.hmastlock <= UInt<1>("h00") @[quasar.scala 280:42] + _T_14.out.hburst <= UInt<3>("h00") @[quasar.scala 280:42] + _T_14.out.haddr <= UInt<32>("h00") @[quasar.scala 280:42] + _T_14.in.hresp <= UInt<1>("h00") @[quasar.scala 280:42] + _T_14.in.hready <= UInt<1>("h00") @[quasar.scala 280:42] + _T_14.in.hrdata <= UInt<64>("h00") @[quasar.scala 280:42] + io.sb_ahb.out.hwdata <= _T_14.out.hwdata @[quasar.scala 280:27] + io.sb_ahb.out.hwrite <= _T_14.out.hwrite @[quasar.scala 280:27] + io.sb_ahb.out.htrans <= _T_14.out.htrans @[quasar.scala 280:27] + io.sb_ahb.out.hsize <= _T_14.out.hsize @[quasar.scala 280:27] + io.sb_ahb.out.hprot <= _T_14.out.hprot @[quasar.scala 280:27] + io.sb_ahb.out.hmastlock <= _T_14.out.hmastlock @[quasar.scala 280:27] + io.sb_ahb.out.hburst <= _T_14.out.hburst @[quasar.scala 280:27] + io.sb_ahb.out.haddr <= _T_14.out.haddr @[quasar.scala 280:27] + _T_14.in.hresp <= io.sb_ahb.in.hresp @[quasar.scala 280:27] + _T_14.in.hready <= io.sb_ahb.in.hready @[quasar.scala 280:27] + _T_14.in.hrdata <= io.sb_ahb.in.hrdata @[quasar.scala 280:27] + wire _T_15 : {flip sig : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, flip hsel : UInt<1>, flip hreadyin : UInt<1>} @[quasar.scala 281:42] + _T_15.hreadyin <= UInt<1>("h00") @[quasar.scala 281:42] + _T_15.hsel <= UInt<1>("h00") @[quasar.scala 281:42] + _T_15.sig.out.hwdata <= UInt<64>("h00") @[quasar.scala 281:42] + _T_15.sig.out.hwrite <= UInt<1>("h00") @[quasar.scala 281:42] + _T_15.sig.out.htrans <= UInt<2>("h00") @[quasar.scala 281:42] + _T_15.sig.out.hsize <= UInt<3>("h00") @[quasar.scala 281:42] + _T_15.sig.out.hprot <= UInt<4>("h00") @[quasar.scala 281:42] + _T_15.sig.out.hmastlock <= UInt<1>("h00") @[quasar.scala 281:42] + _T_15.sig.out.hburst <= UInt<3>("h00") @[quasar.scala 281:42] + _T_15.sig.out.haddr <= UInt<32>("h00") @[quasar.scala 281:42] + _T_15.sig.in.hresp <= UInt<1>("h00") @[quasar.scala 281:42] + _T_15.sig.in.hready <= UInt<1>("h00") @[quasar.scala 281:42] + _T_15.sig.in.hrdata <= UInt<64>("h00") @[quasar.scala 281:42] + _T_15.hreadyin <= io.dma_ahb.hreadyin @[quasar.scala 281:27] + _T_15.hsel <= io.dma_ahb.hsel @[quasar.scala 281:27] + _T_15.sig.out.hwdata <= io.dma_ahb.sig.out.hwdata @[quasar.scala 281:27] + _T_15.sig.out.hwrite <= io.dma_ahb.sig.out.hwrite @[quasar.scala 281:27] + _T_15.sig.out.htrans <= io.dma_ahb.sig.out.htrans @[quasar.scala 281:27] + _T_15.sig.out.hsize <= io.dma_ahb.sig.out.hsize @[quasar.scala 281:27] + _T_15.sig.out.hprot <= io.dma_ahb.sig.out.hprot @[quasar.scala 281:27] + _T_15.sig.out.hmastlock <= io.dma_ahb.sig.out.hmastlock @[quasar.scala 281:27] + _T_15.sig.out.hburst <= io.dma_ahb.sig.out.hburst @[quasar.scala 281:27] + _T_15.sig.out.haddr <= io.dma_ahb.sig.out.haddr @[quasar.scala 281:27] + io.dma_ahb.sig.in.hresp <= _T_15.sig.in.hresp @[quasar.scala 281:27] + io.dma_ahb.sig.in.hready <= _T_15.sig.in.hready @[quasar.scala 281:27] + io.dma_ahb.sig.in.hrdata <= _T_15.sig.in.hrdata @[quasar.scala 281:27] + io.dma_axi.r.bits.last <= dma_ctrl.io.dma_axi.r.bits.last @[quasar.scala 282:27] + io.dma_axi.r.bits.resp <= dma_ctrl.io.dma_axi.r.bits.resp @[quasar.scala 282:27] + io.dma_axi.r.bits.data <= dma_ctrl.io.dma_axi.r.bits.data @[quasar.scala 282:27] + io.dma_axi.r.bits.id <= dma_ctrl.io.dma_axi.r.bits.id @[quasar.scala 282:27] + io.dma_axi.r.valid <= dma_ctrl.io.dma_axi.r.valid @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.r.ready <= io.dma_axi.r.ready @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.ar.bits.qos <= io.dma_axi.ar.bits.qos @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.ar.bits.prot <= io.dma_axi.ar.bits.prot @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.ar.bits.cache <= io.dma_axi.ar.bits.cache @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.ar.bits.lock <= io.dma_axi.ar.bits.lock @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.ar.bits.burst <= io.dma_axi.ar.bits.burst @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.ar.bits.size <= io.dma_axi.ar.bits.size @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.ar.bits.len <= io.dma_axi.ar.bits.len @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.ar.bits.region <= io.dma_axi.ar.bits.region @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.ar.bits.addr <= io.dma_axi.ar.bits.addr @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.ar.bits.id <= io.dma_axi.ar.bits.id @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.ar.valid <= io.dma_axi.ar.valid @[quasar.scala 282:27] + io.dma_axi.ar.ready <= dma_ctrl.io.dma_axi.ar.ready @[quasar.scala 282:27] + io.dma_axi.b.bits.id <= dma_ctrl.io.dma_axi.b.bits.id @[quasar.scala 282:27] + io.dma_axi.b.bits.resp <= dma_ctrl.io.dma_axi.b.bits.resp @[quasar.scala 282:27] + io.dma_axi.b.valid <= dma_ctrl.io.dma_axi.b.valid @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.b.ready <= io.dma_axi.b.ready @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.w.bits.last <= io.dma_axi.w.bits.last @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.w.bits.strb <= io.dma_axi.w.bits.strb @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.w.bits.data <= io.dma_axi.w.bits.data @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.w.valid <= io.dma_axi.w.valid @[quasar.scala 282:27] + io.dma_axi.w.ready <= dma_ctrl.io.dma_axi.w.ready @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.aw.bits.qos <= io.dma_axi.aw.bits.qos @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.aw.bits.prot <= io.dma_axi.aw.bits.prot @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.aw.bits.cache <= io.dma_axi.aw.bits.cache @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.aw.bits.lock <= io.dma_axi.aw.bits.lock @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.aw.bits.burst <= io.dma_axi.aw.bits.burst @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.aw.bits.size <= io.dma_axi.aw.bits.size @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.aw.bits.len <= io.dma_axi.aw.bits.len @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.aw.bits.region <= io.dma_axi.aw.bits.region @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.aw.bits.addr <= io.dma_axi.aw.bits.addr @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.aw.bits.id <= io.dma_axi.aw.bits.id @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.aw.valid <= io.dma_axi.aw.valid @[quasar.scala 282:27] + io.dma_axi.aw.ready <= dma_ctrl.io.dma_axi.aw.ready @[quasar.scala 282:27] + dbg.io.sb_axi.r.bits.last <= io.sb_axi.r.bits.last @[quasar.scala 283:27] + dbg.io.sb_axi.r.bits.resp <= io.sb_axi.r.bits.resp @[quasar.scala 283:27] + dbg.io.sb_axi.r.bits.data <= io.sb_axi.r.bits.data @[quasar.scala 283:27] + dbg.io.sb_axi.r.bits.id <= io.sb_axi.r.bits.id @[quasar.scala 283:27] + dbg.io.sb_axi.r.valid <= io.sb_axi.r.valid @[quasar.scala 283:27] + io.sb_axi.r.ready <= dbg.io.sb_axi.r.ready @[quasar.scala 283:27] + io.sb_axi.ar.bits.qos <= dbg.io.sb_axi.ar.bits.qos @[quasar.scala 283:27] + io.sb_axi.ar.bits.prot <= dbg.io.sb_axi.ar.bits.prot @[quasar.scala 283:27] + io.sb_axi.ar.bits.cache <= dbg.io.sb_axi.ar.bits.cache @[quasar.scala 283:27] + io.sb_axi.ar.bits.lock <= dbg.io.sb_axi.ar.bits.lock @[quasar.scala 283:27] + io.sb_axi.ar.bits.burst <= dbg.io.sb_axi.ar.bits.burst @[quasar.scala 283:27] + io.sb_axi.ar.bits.size <= dbg.io.sb_axi.ar.bits.size @[quasar.scala 283:27] + io.sb_axi.ar.bits.len <= dbg.io.sb_axi.ar.bits.len @[quasar.scala 283:27] + io.sb_axi.ar.bits.region <= dbg.io.sb_axi.ar.bits.region @[quasar.scala 283:27] + io.sb_axi.ar.bits.addr <= dbg.io.sb_axi.ar.bits.addr @[quasar.scala 283:27] + io.sb_axi.ar.bits.id <= dbg.io.sb_axi.ar.bits.id @[quasar.scala 283:27] + io.sb_axi.ar.valid <= dbg.io.sb_axi.ar.valid @[quasar.scala 283:27] + dbg.io.sb_axi.ar.ready <= io.sb_axi.ar.ready @[quasar.scala 283:27] + dbg.io.sb_axi.b.bits.id <= io.sb_axi.b.bits.id @[quasar.scala 283:27] + dbg.io.sb_axi.b.bits.resp <= io.sb_axi.b.bits.resp @[quasar.scala 283:27] + dbg.io.sb_axi.b.valid <= io.sb_axi.b.valid @[quasar.scala 283:27] + io.sb_axi.b.ready <= dbg.io.sb_axi.b.ready @[quasar.scala 283:27] + io.sb_axi.w.bits.last <= dbg.io.sb_axi.w.bits.last @[quasar.scala 283:27] + io.sb_axi.w.bits.strb <= dbg.io.sb_axi.w.bits.strb @[quasar.scala 283:27] + io.sb_axi.w.bits.data <= dbg.io.sb_axi.w.bits.data @[quasar.scala 283:27] + io.sb_axi.w.valid <= dbg.io.sb_axi.w.valid @[quasar.scala 283:27] + dbg.io.sb_axi.w.ready <= io.sb_axi.w.ready @[quasar.scala 283:27] + io.sb_axi.aw.bits.qos <= dbg.io.sb_axi.aw.bits.qos @[quasar.scala 283:27] + io.sb_axi.aw.bits.prot <= dbg.io.sb_axi.aw.bits.prot @[quasar.scala 283:27] + io.sb_axi.aw.bits.cache <= dbg.io.sb_axi.aw.bits.cache @[quasar.scala 283:27] + io.sb_axi.aw.bits.lock <= dbg.io.sb_axi.aw.bits.lock @[quasar.scala 283:27] + io.sb_axi.aw.bits.burst <= dbg.io.sb_axi.aw.bits.burst @[quasar.scala 283:27] + io.sb_axi.aw.bits.size <= dbg.io.sb_axi.aw.bits.size @[quasar.scala 283:27] + io.sb_axi.aw.bits.len <= dbg.io.sb_axi.aw.bits.len @[quasar.scala 283:27] + io.sb_axi.aw.bits.region <= dbg.io.sb_axi.aw.bits.region @[quasar.scala 283:27] + io.sb_axi.aw.bits.addr <= dbg.io.sb_axi.aw.bits.addr @[quasar.scala 283:27] + io.sb_axi.aw.bits.id <= dbg.io.sb_axi.aw.bits.id @[quasar.scala 283:27] + io.sb_axi.aw.valid <= dbg.io.sb_axi.aw.valid @[quasar.scala 283:27] + dbg.io.sb_axi.aw.ready <= io.sb_axi.aw.ready @[quasar.scala 283:27] + ifu.io.ifu.r.bits.last <= io.ifu_axi.r.bits.last @[quasar.scala 284:27] + ifu.io.ifu.r.bits.resp <= io.ifu_axi.r.bits.resp @[quasar.scala 284:27] + ifu.io.ifu.r.bits.data <= io.ifu_axi.r.bits.data @[quasar.scala 284:27] + ifu.io.ifu.r.bits.id <= io.ifu_axi.r.bits.id @[quasar.scala 284:27] + ifu.io.ifu.r.valid <= io.ifu_axi.r.valid @[quasar.scala 284:27] + io.ifu_axi.r.ready <= ifu.io.ifu.r.ready @[quasar.scala 284:27] + io.ifu_axi.ar.bits.qos <= ifu.io.ifu.ar.bits.qos @[quasar.scala 284:27] + io.ifu_axi.ar.bits.prot <= ifu.io.ifu.ar.bits.prot @[quasar.scala 284:27] + io.ifu_axi.ar.bits.cache <= ifu.io.ifu.ar.bits.cache @[quasar.scala 284:27] + io.ifu_axi.ar.bits.lock <= ifu.io.ifu.ar.bits.lock @[quasar.scala 284:27] + io.ifu_axi.ar.bits.burst <= ifu.io.ifu.ar.bits.burst @[quasar.scala 284:27] + io.ifu_axi.ar.bits.size <= ifu.io.ifu.ar.bits.size @[quasar.scala 284:27] + io.ifu_axi.ar.bits.len <= ifu.io.ifu.ar.bits.len @[quasar.scala 284:27] + io.ifu_axi.ar.bits.region <= ifu.io.ifu.ar.bits.region @[quasar.scala 284:27] + io.ifu_axi.ar.bits.addr <= ifu.io.ifu.ar.bits.addr @[quasar.scala 284:27] + io.ifu_axi.ar.bits.id <= ifu.io.ifu.ar.bits.id @[quasar.scala 284:27] + io.ifu_axi.ar.valid <= ifu.io.ifu.ar.valid @[quasar.scala 284:27] + ifu.io.ifu.ar.ready <= io.ifu_axi.ar.ready @[quasar.scala 284:27] + ifu.io.ifu.b.bits.id <= io.ifu_axi.b.bits.id @[quasar.scala 284:27] + ifu.io.ifu.b.bits.resp <= io.ifu_axi.b.bits.resp @[quasar.scala 284:27] + ifu.io.ifu.b.valid <= io.ifu_axi.b.valid @[quasar.scala 284:27] + io.ifu_axi.b.ready <= ifu.io.ifu.b.ready @[quasar.scala 284:27] + io.ifu_axi.w.bits.last <= ifu.io.ifu.w.bits.last @[quasar.scala 284:27] + io.ifu_axi.w.bits.strb <= ifu.io.ifu.w.bits.strb @[quasar.scala 284:27] + io.ifu_axi.w.bits.data <= ifu.io.ifu.w.bits.data @[quasar.scala 284:27] + io.ifu_axi.w.valid <= ifu.io.ifu.w.valid @[quasar.scala 284:27] + ifu.io.ifu.w.ready <= io.ifu_axi.w.ready @[quasar.scala 284:27] + io.ifu_axi.aw.bits.qos <= ifu.io.ifu.aw.bits.qos @[quasar.scala 284:27] + io.ifu_axi.aw.bits.prot <= ifu.io.ifu.aw.bits.prot @[quasar.scala 284:27] + io.ifu_axi.aw.bits.cache <= ifu.io.ifu.aw.bits.cache @[quasar.scala 284:27] + io.ifu_axi.aw.bits.lock <= ifu.io.ifu.aw.bits.lock @[quasar.scala 284:27] + io.ifu_axi.aw.bits.burst <= ifu.io.ifu.aw.bits.burst @[quasar.scala 284:27] + io.ifu_axi.aw.bits.size <= ifu.io.ifu.aw.bits.size @[quasar.scala 284:27] + io.ifu_axi.aw.bits.len <= ifu.io.ifu.aw.bits.len @[quasar.scala 284:27] + io.ifu_axi.aw.bits.region <= ifu.io.ifu.aw.bits.region @[quasar.scala 284:27] + io.ifu_axi.aw.bits.addr <= ifu.io.ifu.aw.bits.addr @[quasar.scala 284:27] + io.ifu_axi.aw.bits.id <= ifu.io.ifu.aw.bits.id @[quasar.scala 284:27] + io.ifu_axi.aw.valid <= ifu.io.ifu.aw.valid @[quasar.scala 284:27] + ifu.io.ifu.aw.ready <= io.ifu_axi.aw.ready @[quasar.scala 284:27] + lsu.io.axi.r.bits.last <= io.lsu_axi.r.bits.last @[quasar.scala 285:27] + lsu.io.axi.r.bits.resp <= io.lsu_axi.r.bits.resp @[quasar.scala 285:27] + lsu.io.axi.r.bits.data <= io.lsu_axi.r.bits.data @[quasar.scala 285:27] + lsu.io.axi.r.bits.id <= io.lsu_axi.r.bits.id @[quasar.scala 285:27] + lsu.io.axi.r.valid <= io.lsu_axi.r.valid @[quasar.scala 285:27] + io.lsu_axi.r.ready <= lsu.io.axi.r.ready @[quasar.scala 285:27] + io.lsu_axi.ar.bits.qos <= lsu.io.axi.ar.bits.qos @[quasar.scala 285:27] + io.lsu_axi.ar.bits.prot <= lsu.io.axi.ar.bits.prot @[quasar.scala 285:27] + io.lsu_axi.ar.bits.cache <= lsu.io.axi.ar.bits.cache @[quasar.scala 285:27] + io.lsu_axi.ar.bits.lock <= lsu.io.axi.ar.bits.lock @[quasar.scala 285:27] + io.lsu_axi.ar.bits.burst <= lsu.io.axi.ar.bits.burst @[quasar.scala 285:27] + io.lsu_axi.ar.bits.size <= lsu.io.axi.ar.bits.size @[quasar.scala 285:27] + io.lsu_axi.ar.bits.len <= lsu.io.axi.ar.bits.len @[quasar.scala 285:27] + io.lsu_axi.ar.bits.region <= lsu.io.axi.ar.bits.region @[quasar.scala 285:27] + io.lsu_axi.ar.bits.addr <= lsu.io.axi.ar.bits.addr @[quasar.scala 285:27] + io.lsu_axi.ar.bits.id <= lsu.io.axi.ar.bits.id @[quasar.scala 285:27] + io.lsu_axi.ar.valid <= lsu.io.axi.ar.valid @[quasar.scala 285:27] + lsu.io.axi.ar.ready <= io.lsu_axi.ar.ready @[quasar.scala 285:27] + lsu.io.axi.b.bits.id <= io.lsu_axi.b.bits.id @[quasar.scala 285:27] + lsu.io.axi.b.bits.resp <= io.lsu_axi.b.bits.resp @[quasar.scala 285:27] + lsu.io.axi.b.valid <= io.lsu_axi.b.valid @[quasar.scala 285:27] + io.lsu_axi.b.ready <= lsu.io.axi.b.ready @[quasar.scala 285:27] + io.lsu_axi.w.bits.last <= lsu.io.axi.w.bits.last @[quasar.scala 285:27] + io.lsu_axi.w.bits.strb <= lsu.io.axi.w.bits.strb @[quasar.scala 285:27] + io.lsu_axi.w.bits.data <= lsu.io.axi.w.bits.data @[quasar.scala 285:27] + io.lsu_axi.w.valid <= lsu.io.axi.w.valid @[quasar.scala 285:27] + lsu.io.axi.w.ready <= io.lsu_axi.w.ready @[quasar.scala 285:27] + io.lsu_axi.aw.bits.qos <= lsu.io.axi.aw.bits.qos @[quasar.scala 285:27] + io.lsu_axi.aw.bits.prot <= lsu.io.axi.aw.bits.prot @[quasar.scala 285:27] + io.lsu_axi.aw.bits.cache <= lsu.io.axi.aw.bits.cache @[quasar.scala 285:27] + io.lsu_axi.aw.bits.lock <= lsu.io.axi.aw.bits.lock @[quasar.scala 285:27] + io.lsu_axi.aw.bits.burst <= lsu.io.axi.aw.bits.burst @[quasar.scala 285:27] + io.lsu_axi.aw.bits.size <= lsu.io.axi.aw.bits.size @[quasar.scala 285:27] + io.lsu_axi.aw.bits.len <= lsu.io.axi.aw.bits.len @[quasar.scala 285:27] + io.lsu_axi.aw.bits.region <= lsu.io.axi.aw.bits.region @[quasar.scala 285:27] + io.lsu_axi.aw.bits.addr <= lsu.io.axi.aw.bits.addr @[quasar.scala 285:27] + io.lsu_axi.aw.bits.id <= lsu.io.axi.aw.bits.id @[quasar.scala 285:27] + io.lsu_axi.aw.valid <= lsu.io.axi.aw.valid @[quasar.scala 285:27] + lsu.io.axi.aw.ready <= io.lsu_axi.aw.ready @[quasar.scala 285:27] module quasar_wrapper : input clock : Clock input reset : AsyncReset - output io : {flip dbg_rst_l : AsyncReset, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip jtag_id : UInt<31>, lsu_brg : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, ifu_brg : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, sb_brg : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, dma_brg : {flip sig : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, flip hsel : UInt<1>, flip hreadyin : UInt<1>}, flip lsu_bus_clk_en : UInt<1>, flip ifu_bus_clk_en : UInt<1>, flip dbg_bus_clk_en : UInt<1>, flip dma_bus_clk_en : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip extintsrc_req : UInt<31>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, flip jtag_tck : Clock, flip jtag_tms : UInt<1>, flip jtag_tdi : UInt<1>, flip jtag_trst_n : UInt<1>, jtag_tdo : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_halt_status : UInt<1>, o_debug_mode_status : UInt<1>, o_cpu_run_ack : UInt<1>, flip mbist_mode : UInt<1>, rv_trace_pkt : {rv_i_valid_ip : UInt<2>, rv_i_insn_ip : UInt<32>, rv_i_address_ip : UInt<32>, rv_i_exception_ip : UInt<2>, rv_i_ecause_ip : UInt<5>, rv_i_interrupt_ip : UInt<2>, rv_i_tval_ip : UInt<32>}, flip scan_mode : UInt<1>} + output io : {flip dbg_rst_l : AsyncReset, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip jtag_id : UInt<31>, lsu_brg : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ifu_brg : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, sb_brg : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dma_brg : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip lsu_bus_clk_en : UInt<1>, flip ifu_bus_clk_en : UInt<1>, flip dbg_bus_clk_en : UInt<1>, flip dma_bus_clk_en : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip extintsrc_req : UInt<31>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, flip jtag_tck : Clock, flip jtag_tms : UInt<1>, flip jtag_tdi : UInt<1>, flip jtag_trst_n : UInt<1>, jtag_tdo : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_halt_status : UInt<1>, o_debug_mode_status : UInt<1>, o_cpu_run_ack : UInt<1>, flip mbist_mode : UInt<1>, rv_trace_pkt : {rv_i_valid_ip : UInt<2>, rv_i_insn_ip : UInt<32>, rv_i_address_ip : UInt<32>, rv_i_exception_ip : UInt<2>, rv_i_ecause_ip : UInt<5>, rv_i_interrupt_ip : UInt<2>, rv_i_tval_ip : UInt<32>}, flip scan_mode : UInt<1>} inst mem of mem @[quasar_wrapper.scala 63:19] mem.scan_mode is invalid @@ -115016,368 +109904,258 @@ circuit quasar_wrapper : mem.iccm.correction_state <= core.io.iccm.correction_state @[quasar_wrapper.scala 95:16] mem.iccm.buf_correct_ecc <= core.io.iccm.buf_correct_ecc @[quasar_wrapper.scala 95:16] mem.iccm.rw_addr <= core.io.iccm.rw_addr @[quasar_wrapper.scala 95:16] - io.ifu_brg.out.hwdata <= core.io.ifu_ahb.out.hwdata @[quasar_wrapper.scala 110:21] - io.ifu_brg.out.hwrite <= core.io.ifu_ahb.out.hwrite @[quasar_wrapper.scala 110:21] - io.ifu_brg.out.htrans <= core.io.ifu_ahb.out.htrans @[quasar_wrapper.scala 110:21] - io.ifu_brg.out.hsize <= core.io.ifu_ahb.out.hsize @[quasar_wrapper.scala 110:21] - io.ifu_brg.out.hprot <= core.io.ifu_ahb.out.hprot @[quasar_wrapper.scala 110:21] - io.ifu_brg.out.hmastlock <= core.io.ifu_ahb.out.hmastlock @[quasar_wrapper.scala 110:21] - io.ifu_brg.out.hburst <= core.io.ifu_ahb.out.hburst @[quasar_wrapper.scala 110:21] - io.ifu_brg.out.haddr <= core.io.ifu_ahb.out.haddr @[quasar_wrapper.scala 110:21] - core.io.ifu_ahb.in.hresp <= io.ifu_brg.in.hresp @[quasar_wrapper.scala 110:21] - core.io.ifu_ahb.in.hready <= io.ifu_brg.in.hready @[quasar_wrapper.scala 110:21] - core.io.ifu_ahb.in.hrdata <= io.ifu_brg.in.hrdata @[quasar_wrapper.scala 110:21] - io.lsu_brg.out.hwdata <= core.io.lsu_ahb.out.hwdata @[quasar_wrapper.scala 111:21] - io.lsu_brg.out.hwrite <= core.io.lsu_ahb.out.hwrite @[quasar_wrapper.scala 111:21] - io.lsu_brg.out.htrans <= core.io.lsu_ahb.out.htrans @[quasar_wrapper.scala 111:21] - io.lsu_brg.out.hsize <= core.io.lsu_ahb.out.hsize @[quasar_wrapper.scala 111:21] - io.lsu_brg.out.hprot <= core.io.lsu_ahb.out.hprot @[quasar_wrapper.scala 111:21] - io.lsu_brg.out.hmastlock <= core.io.lsu_ahb.out.hmastlock @[quasar_wrapper.scala 111:21] - io.lsu_brg.out.hburst <= core.io.lsu_ahb.out.hburst @[quasar_wrapper.scala 111:21] - io.lsu_brg.out.haddr <= core.io.lsu_ahb.out.haddr @[quasar_wrapper.scala 111:21] - core.io.lsu_ahb.in.hresp <= io.lsu_brg.in.hresp @[quasar_wrapper.scala 111:21] - core.io.lsu_ahb.in.hready <= io.lsu_brg.in.hready @[quasar_wrapper.scala 111:21] - core.io.lsu_ahb.in.hrdata <= io.lsu_brg.in.hrdata @[quasar_wrapper.scala 111:21] - io.sb_brg.out.hwdata <= core.io.sb_ahb.out.hwdata @[quasar_wrapper.scala 112:20] - io.sb_brg.out.hwrite <= core.io.sb_ahb.out.hwrite @[quasar_wrapper.scala 112:20] - io.sb_brg.out.htrans <= core.io.sb_ahb.out.htrans @[quasar_wrapper.scala 112:20] - io.sb_brg.out.hsize <= core.io.sb_ahb.out.hsize @[quasar_wrapper.scala 112:20] - io.sb_brg.out.hprot <= core.io.sb_ahb.out.hprot @[quasar_wrapper.scala 112:20] - io.sb_brg.out.hmastlock <= core.io.sb_ahb.out.hmastlock @[quasar_wrapper.scala 112:20] - io.sb_brg.out.hburst <= core.io.sb_ahb.out.hburst @[quasar_wrapper.scala 112:20] - io.sb_brg.out.haddr <= core.io.sb_ahb.out.haddr @[quasar_wrapper.scala 112:20] - core.io.sb_ahb.in.hresp <= io.sb_brg.in.hresp @[quasar_wrapper.scala 112:20] - core.io.sb_ahb.in.hready <= io.sb_brg.in.hready @[quasar_wrapper.scala 112:20] - core.io.sb_ahb.in.hrdata <= io.sb_brg.in.hrdata @[quasar_wrapper.scala 112:20] - core.io.dma_ahb.hreadyin <= io.dma_brg.hreadyin @[quasar_wrapper.scala 113:21] - core.io.dma_ahb.hsel <= io.dma_brg.hsel @[quasar_wrapper.scala 113:21] - core.io.dma_ahb.sig.out.hwdata <= io.dma_brg.sig.out.hwdata @[quasar_wrapper.scala 113:21] - core.io.dma_ahb.sig.out.hwrite <= io.dma_brg.sig.out.hwrite @[quasar_wrapper.scala 113:21] - core.io.dma_ahb.sig.out.htrans <= io.dma_brg.sig.out.htrans @[quasar_wrapper.scala 113:21] - core.io.dma_ahb.sig.out.hsize <= io.dma_brg.sig.out.hsize @[quasar_wrapper.scala 113:21] - core.io.dma_ahb.sig.out.hprot <= io.dma_brg.sig.out.hprot @[quasar_wrapper.scala 113:21] - core.io.dma_ahb.sig.out.hmastlock <= io.dma_brg.sig.out.hmastlock @[quasar_wrapper.scala 113:21] - core.io.dma_ahb.sig.out.hburst <= io.dma_brg.sig.out.hburst @[quasar_wrapper.scala 113:21] - core.io.dma_ahb.sig.out.haddr <= io.dma_brg.sig.out.haddr @[quasar_wrapper.scala 113:21] - io.dma_brg.sig.in.hresp <= core.io.dma_ahb.sig.in.hresp @[quasar_wrapper.scala 113:21] - io.dma_brg.sig.in.hready <= core.io.dma_ahb.sig.in.hready @[quasar_wrapper.scala 113:21] - io.dma_brg.sig.in.hrdata <= core.io.dma_ahb.sig.in.hrdata @[quasar_wrapper.scala 113:21] - wire _T : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar_wrapper.scala 115:36] - _T.r.bits.last <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] - _T.r.bits.resp <= UInt<2>("h00") @[quasar_wrapper.scala 115:36] - _T.r.bits.data <= UInt<64>("h00") @[quasar_wrapper.scala 115:36] - _T.r.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 115:36] - _T.r.valid <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] - _T.r.ready <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] - _T.ar.bits.qos <= UInt<4>("h00") @[quasar_wrapper.scala 115:36] - _T.ar.bits.prot <= UInt<3>("h00") @[quasar_wrapper.scala 115:36] - _T.ar.bits.cache <= UInt<4>("h00") @[quasar_wrapper.scala 115:36] - _T.ar.bits.lock <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] - _T.ar.bits.burst <= UInt<2>("h00") @[quasar_wrapper.scala 115:36] - _T.ar.bits.size <= UInt<3>("h00") @[quasar_wrapper.scala 115:36] - _T.ar.bits.len <= UInt<8>("h00") @[quasar_wrapper.scala 115:36] - _T.ar.bits.region <= UInt<4>("h00") @[quasar_wrapper.scala 115:36] - _T.ar.bits.addr <= UInt<32>("h00") @[quasar_wrapper.scala 115:36] - _T.ar.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 115:36] - _T.ar.valid <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] - _T.ar.ready <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] - _T.b.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 115:36] - _T.b.bits.resp <= UInt<2>("h00") @[quasar_wrapper.scala 115:36] - _T.b.valid <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] - _T.b.ready <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] - _T.w.bits.last <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] - _T.w.bits.strb <= UInt<8>("h00") @[quasar_wrapper.scala 115:36] - _T.w.bits.data <= UInt<64>("h00") @[quasar_wrapper.scala 115:36] - _T.w.valid <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] - _T.w.ready <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] - _T.aw.bits.qos <= UInt<4>("h00") @[quasar_wrapper.scala 115:36] - _T.aw.bits.prot <= UInt<3>("h00") @[quasar_wrapper.scala 115:36] - _T.aw.bits.cache <= UInt<4>("h00") @[quasar_wrapper.scala 115:36] - _T.aw.bits.lock <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] - _T.aw.bits.burst <= UInt<2>("h00") @[quasar_wrapper.scala 115:36] - _T.aw.bits.size <= UInt<3>("h00") @[quasar_wrapper.scala 115:36] - _T.aw.bits.len <= UInt<8>("h00") @[quasar_wrapper.scala 115:36] - _T.aw.bits.region <= UInt<4>("h00") @[quasar_wrapper.scala 115:36] - _T.aw.bits.addr <= UInt<32>("h00") @[quasar_wrapper.scala 115:36] - _T.aw.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 115:36] - _T.aw.valid <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] - _T.aw.ready <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] - core.io.lsu_axi.r.bits.last <= _T.r.bits.last @[quasar_wrapper.scala 115:21] - core.io.lsu_axi.r.bits.resp <= _T.r.bits.resp @[quasar_wrapper.scala 115:21] - core.io.lsu_axi.r.bits.data <= _T.r.bits.data @[quasar_wrapper.scala 115:21] - core.io.lsu_axi.r.bits.id <= _T.r.bits.id @[quasar_wrapper.scala 115:21] - core.io.lsu_axi.r.valid <= _T.r.valid @[quasar_wrapper.scala 115:21] - _T.r.ready <= core.io.lsu_axi.r.ready @[quasar_wrapper.scala 115:21] - _T.ar.bits.qos <= core.io.lsu_axi.ar.bits.qos @[quasar_wrapper.scala 115:21] - _T.ar.bits.prot <= core.io.lsu_axi.ar.bits.prot @[quasar_wrapper.scala 115:21] - _T.ar.bits.cache <= core.io.lsu_axi.ar.bits.cache @[quasar_wrapper.scala 115:21] - _T.ar.bits.lock <= core.io.lsu_axi.ar.bits.lock @[quasar_wrapper.scala 115:21] - _T.ar.bits.burst <= core.io.lsu_axi.ar.bits.burst @[quasar_wrapper.scala 115:21] - _T.ar.bits.size <= core.io.lsu_axi.ar.bits.size @[quasar_wrapper.scala 115:21] - _T.ar.bits.len <= core.io.lsu_axi.ar.bits.len @[quasar_wrapper.scala 115:21] - _T.ar.bits.region <= core.io.lsu_axi.ar.bits.region @[quasar_wrapper.scala 115:21] - _T.ar.bits.addr <= core.io.lsu_axi.ar.bits.addr @[quasar_wrapper.scala 115:21] - _T.ar.bits.id <= core.io.lsu_axi.ar.bits.id @[quasar_wrapper.scala 115:21] - _T.ar.valid <= core.io.lsu_axi.ar.valid @[quasar_wrapper.scala 115:21] - core.io.lsu_axi.ar.ready <= _T.ar.ready @[quasar_wrapper.scala 115:21] - core.io.lsu_axi.b.bits.id <= _T.b.bits.id @[quasar_wrapper.scala 115:21] - core.io.lsu_axi.b.bits.resp <= _T.b.bits.resp @[quasar_wrapper.scala 115:21] - core.io.lsu_axi.b.valid <= _T.b.valid @[quasar_wrapper.scala 115:21] - _T.b.ready <= core.io.lsu_axi.b.ready @[quasar_wrapper.scala 115:21] - _T.w.bits.last <= core.io.lsu_axi.w.bits.last @[quasar_wrapper.scala 115:21] - _T.w.bits.strb <= core.io.lsu_axi.w.bits.strb @[quasar_wrapper.scala 115:21] - _T.w.bits.data <= core.io.lsu_axi.w.bits.data @[quasar_wrapper.scala 115:21] - _T.w.valid <= core.io.lsu_axi.w.valid @[quasar_wrapper.scala 115:21] - core.io.lsu_axi.w.ready <= _T.w.ready @[quasar_wrapper.scala 115:21] - _T.aw.bits.qos <= core.io.lsu_axi.aw.bits.qos @[quasar_wrapper.scala 115:21] - _T.aw.bits.prot <= core.io.lsu_axi.aw.bits.prot @[quasar_wrapper.scala 115:21] - _T.aw.bits.cache <= core.io.lsu_axi.aw.bits.cache @[quasar_wrapper.scala 115:21] - _T.aw.bits.lock <= core.io.lsu_axi.aw.bits.lock @[quasar_wrapper.scala 115:21] - _T.aw.bits.burst <= core.io.lsu_axi.aw.bits.burst @[quasar_wrapper.scala 115:21] - _T.aw.bits.size <= core.io.lsu_axi.aw.bits.size @[quasar_wrapper.scala 115:21] - _T.aw.bits.len <= core.io.lsu_axi.aw.bits.len @[quasar_wrapper.scala 115:21] - _T.aw.bits.region <= core.io.lsu_axi.aw.bits.region @[quasar_wrapper.scala 115:21] - _T.aw.bits.addr <= core.io.lsu_axi.aw.bits.addr @[quasar_wrapper.scala 115:21] - _T.aw.bits.id <= core.io.lsu_axi.aw.bits.id @[quasar_wrapper.scala 115:21] - _T.aw.valid <= core.io.lsu_axi.aw.valid @[quasar_wrapper.scala 115:21] - core.io.lsu_axi.aw.ready <= _T.aw.ready @[quasar_wrapper.scala 115:21] - wire _T_1 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar_wrapper.scala 116:36] - _T_1.r.bits.last <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] - _T_1.r.bits.resp <= UInt<2>("h00") @[quasar_wrapper.scala 116:36] - _T_1.r.bits.data <= UInt<64>("h00") @[quasar_wrapper.scala 116:36] - _T_1.r.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 116:36] - _T_1.r.valid <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] - _T_1.r.ready <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] - _T_1.ar.bits.qos <= UInt<4>("h00") @[quasar_wrapper.scala 116:36] - _T_1.ar.bits.prot <= UInt<3>("h00") @[quasar_wrapper.scala 116:36] - _T_1.ar.bits.cache <= UInt<4>("h00") @[quasar_wrapper.scala 116:36] - _T_1.ar.bits.lock <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] - _T_1.ar.bits.burst <= UInt<2>("h00") @[quasar_wrapper.scala 116:36] - _T_1.ar.bits.size <= UInt<3>("h00") @[quasar_wrapper.scala 116:36] - _T_1.ar.bits.len <= UInt<8>("h00") @[quasar_wrapper.scala 116:36] - _T_1.ar.bits.region <= UInt<4>("h00") @[quasar_wrapper.scala 116:36] - _T_1.ar.bits.addr <= UInt<32>("h00") @[quasar_wrapper.scala 116:36] - _T_1.ar.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 116:36] - _T_1.ar.valid <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] - _T_1.ar.ready <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] - _T_1.b.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 116:36] - _T_1.b.bits.resp <= UInt<2>("h00") @[quasar_wrapper.scala 116:36] - _T_1.b.valid <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] - _T_1.b.ready <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] - _T_1.w.bits.last <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] - _T_1.w.bits.strb <= UInt<8>("h00") @[quasar_wrapper.scala 116:36] - _T_1.w.bits.data <= UInt<64>("h00") @[quasar_wrapper.scala 116:36] - _T_1.w.valid <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] - _T_1.w.ready <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] - _T_1.aw.bits.qos <= UInt<4>("h00") @[quasar_wrapper.scala 116:36] - _T_1.aw.bits.prot <= UInt<3>("h00") @[quasar_wrapper.scala 116:36] - _T_1.aw.bits.cache <= UInt<4>("h00") @[quasar_wrapper.scala 116:36] - _T_1.aw.bits.lock <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] - _T_1.aw.bits.burst <= UInt<2>("h00") @[quasar_wrapper.scala 116:36] - _T_1.aw.bits.size <= UInt<3>("h00") @[quasar_wrapper.scala 116:36] - _T_1.aw.bits.len <= UInt<8>("h00") @[quasar_wrapper.scala 116:36] - _T_1.aw.bits.region <= UInt<4>("h00") @[quasar_wrapper.scala 116:36] - _T_1.aw.bits.addr <= UInt<32>("h00") @[quasar_wrapper.scala 116:36] - _T_1.aw.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 116:36] - _T_1.aw.valid <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] - _T_1.aw.ready <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] - core.io.ifu_axi.r.bits.last <= _T_1.r.bits.last @[quasar_wrapper.scala 116:21] - core.io.ifu_axi.r.bits.resp <= _T_1.r.bits.resp @[quasar_wrapper.scala 116:21] - core.io.ifu_axi.r.bits.data <= _T_1.r.bits.data @[quasar_wrapper.scala 116:21] - core.io.ifu_axi.r.bits.id <= _T_1.r.bits.id @[quasar_wrapper.scala 116:21] - core.io.ifu_axi.r.valid <= _T_1.r.valid @[quasar_wrapper.scala 116:21] - _T_1.r.ready <= core.io.ifu_axi.r.ready @[quasar_wrapper.scala 116:21] - _T_1.ar.bits.qos <= core.io.ifu_axi.ar.bits.qos @[quasar_wrapper.scala 116:21] - _T_1.ar.bits.prot <= core.io.ifu_axi.ar.bits.prot @[quasar_wrapper.scala 116:21] - _T_1.ar.bits.cache <= core.io.ifu_axi.ar.bits.cache @[quasar_wrapper.scala 116:21] - _T_1.ar.bits.lock <= core.io.ifu_axi.ar.bits.lock @[quasar_wrapper.scala 116:21] - _T_1.ar.bits.burst <= core.io.ifu_axi.ar.bits.burst @[quasar_wrapper.scala 116:21] - _T_1.ar.bits.size <= core.io.ifu_axi.ar.bits.size @[quasar_wrapper.scala 116:21] - _T_1.ar.bits.len <= core.io.ifu_axi.ar.bits.len @[quasar_wrapper.scala 116:21] - _T_1.ar.bits.region <= core.io.ifu_axi.ar.bits.region @[quasar_wrapper.scala 116:21] - _T_1.ar.bits.addr <= core.io.ifu_axi.ar.bits.addr @[quasar_wrapper.scala 116:21] - _T_1.ar.bits.id <= core.io.ifu_axi.ar.bits.id @[quasar_wrapper.scala 116:21] - _T_1.ar.valid <= core.io.ifu_axi.ar.valid @[quasar_wrapper.scala 116:21] - core.io.ifu_axi.ar.ready <= _T_1.ar.ready @[quasar_wrapper.scala 116:21] - core.io.ifu_axi.b.bits.id <= _T_1.b.bits.id @[quasar_wrapper.scala 116:21] - core.io.ifu_axi.b.bits.resp <= _T_1.b.bits.resp @[quasar_wrapper.scala 116:21] - core.io.ifu_axi.b.valid <= _T_1.b.valid @[quasar_wrapper.scala 116:21] - _T_1.b.ready <= core.io.ifu_axi.b.ready @[quasar_wrapper.scala 116:21] - _T_1.w.bits.last <= core.io.ifu_axi.w.bits.last @[quasar_wrapper.scala 116:21] - _T_1.w.bits.strb <= core.io.ifu_axi.w.bits.strb @[quasar_wrapper.scala 116:21] - _T_1.w.bits.data <= core.io.ifu_axi.w.bits.data @[quasar_wrapper.scala 116:21] - _T_1.w.valid <= core.io.ifu_axi.w.valid @[quasar_wrapper.scala 116:21] - core.io.ifu_axi.w.ready <= _T_1.w.ready @[quasar_wrapper.scala 116:21] - _T_1.aw.bits.qos <= core.io.ifu_axi.aw.bits.qos @[quasar_wrapper.scala 116:21] - _T_1.aw.bits.prot <= core.io.ifu_axi.aw.bits.prot @[quasar_wrapper.scala 116:21] - _T_1.aw.bits.cache <= core.io.ifu_axi.aw.bits.cache @[quasar_wrapper.scala 116:21] - _T_1.aw.bits.lock <= core.io.ifu_axi.aw.bits.lock @[quasar_wrapper.scala 116:21] - _T_1.aw.bits.burst <= core.io.ifu_axi.aw.bits.burst @[quasar_wrapper.scala 116:21] - _T_1.aw.bits.size <= core.io.ifu_axi.aw.bits.size @[quasar_wrapper.scala 116:21] - _T_1.aw.bits.len <= core.io.ifu_axi.aw.bits.len @[quasar_wrapper.scala 116:21] - _T_1.aw.bits.region <= core.io.ifu_axi.aw.bits.region @[quasar_wrapper.scala 116:21] - _T_1.aw.bits.addr <= core.io.ifu_axi.aw.bits.addr @[quasar_wrapper.scala 116:21] - _T_1.aw.bits.id <= core.io.ifu_axi.aw.bits.id @[quasar_wrapper.scala 116:21] - _T_1.aw.valid <= core.io.ifu_axi.aw.valid @[quasar_wrapper.scala 116:21] - core.io.ifu_axi.aw.ready <= _T_1.aw.ready @[quasar_wrapper.scala 116:21] - wire _T_2 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar_wrapper.scala 117:36] - _T_2.r.bits.last <= UInt<1>("h00") @[quasar_wrapper.scala 117:36] - _T_2.r.bits.resp <= UInt<2>("h00") @[quasar_wrapper.scala 117:36] - _T_2.r.bits.data <= UInt<64>("h00") @[quasar_wrapper.scala 117:36] - _T_2.r.bits.id <= UInt<1>("h00") @[quasar_wrapper.scala 117:36] - _T_2.r.valid <= UInt<1>("h00") @[quasar_wrapper.scala 117:36] - _T_2.r.ready <= UInt<1>("h00") @[quasar_wrapper.scala 117:36] - _T_2.ar.bits.qos <= UInt<4>("h00") @[quasar_wrapper.scala 117:36] - _T_2.ar.bits.prot <= UInt<3>("h00") @[quasar_wrapper.scala 117:36] - _T_2.ar.bits.cache <= UInt<4>("h00") @[quasar_wrapper.scala 117:36] - _T_2.ar.bits.lock <= UInt<1>("h00") @[quasar_wrapper.scala 117:36] - _T_2.ar.bits.burst <= UInt<2>("h00") @[quasar_wrapper.scala 117:36] - _T_2.ar.bits.size <= UInt<3>("h00") @[quasar_wrapper.scala 117:36] - _T_2.ar.bits.len <= UInt<8>("h00") @[quasar_wrapper.scala 117:36] - _T_2.ar.bits.region <= UInt<4>("h00") @[quasar_wrapper.scala 117:36] - _T_2.ar.bits.addr <= UInt<32>("h00") @[quasar_wrapper.scala 117:36] - _T_2.ar.bits.id <= UInt<1>("h00") @[quasar_wrapper.scala 117:36] - _T_2.ar.valid <= UInt<1>("h00") @[quasar_wrapper.scala 117:36] - _T_2.ar.ready <= UInt<1>("h00") @[quasar_wrapper.scala 117:36] - _T_2.b.bits.id <= UInt<1>("h00") @[quasar_wrapper.scala 117:36] - _T_2.b.bits.resp <= UInt<2>("h00") @[quasar_wrapper.scala 117:36] - _T_2.b.valid <= UInt<1>("h00") @[quasar_wrapper.scala 117:36] - _T_2.b.ready <= UInt<1>("h00") @[quasar_wrapper.scala 117:36] - _T_2.w.bits.last <= UInt<1>("h00") @[quasar_wrapper.scala 117:36] - _T_2.w.bits.strb <= UInt<8>("h00") @[quasar_wrapper.scala 117:36] - _T_2.w.bits.data <= UInt<64>("h00") @[quasar_wrapper.scala 117:36] - _T_2.w.valid <= UInt<1>("h00") @[quasar_wrapper.scala 117:36] - _T_2.w.ready <= UInt<1>("h00") @[quasar_wrapper.scala 117:36] - _T_2.aw.bits.qos <= UInt<4>("h00") @[quasar_wrapper.scala 117:36] - _T_2.aw.bits.prot <= UInt<3>("h00") @[quasar_wrapper.scala 117:36] - _T_2.aw.bits.cache <= UInt<4>("h00") @[quasar_wrapper.scala 117:36] - _T_2.aw.bits.lock <= UInt<1>("h00") @[quasar_wrapper.scala 117:36] - _T_2.aw.bits.burst <= UInt<2>("h00") @[quasar_wrapper.scala 117:36] - _T_2.aw.bits.size <= UInt<3>("h00") @[quasar_wrapper.scala 117:36] - _T_2.aw.bits.len <= UInt<8>("h00") @[quasar_wrapper.scala 117:36] - _T_2.aw.bits.region <= UInt<4>("h00") @[quasar_wrapper.scala 117:36] - _T_2.aw.bits.addr <= UInt<32>("h00") @[quasar_wrapper.scala 117:36] - _T_2.aw.bits.id <= UInt<1>("h00") @[quasar_wrapper.scala 117:36] - _T_2.aw.valid <= UInt<1>("h00") @[quasar_wrapper.scala 117:36] - _T_2.aw.ready <= UInt<1>("h00") @[quasar_wrapper.scala 117:36] - core.io.sb_axi.r.bits.last <= _T_2.r.bits.last @[quasar_wrapper.scala 117:21] - core.io.sb_axi.r.bits.resp <= _T_2.r.bits.resp @[quasar_wrapper.scala 117:21] - core.io.sb_axi.r.bits.data <= _T_2.r.bits.data @[quasar_wrapper.scala 117:21] - core.io.sb_axi.r.bits.id <= _T_2.r.bits.id @[quasar_wrapper.scala 117:21] - core.io.sb_axi.r.valid <= _T_2.r.valid @[quasar_wrapper.scala 117:21] - _T_2.r.ready <= core.io.sb_axi.r.ready @[quasar_wrapper.scala 117:21] - _T_2.ar.bits.qos <= core.io.sb_axi.ar.bits.qos @[quasar_wrapper.scala 117:21] - _T_2.ar.bits.prot <= core.io.sb_axi.ar.bits.prot @[quasar_wrapper.scala 117:21] - _T_2.ar.bits.cache <= core.io.sb_axi.ar.bits.cache @[quasar_wrapper.scala 117:21] - _T_2.ar.bits.lock <= core.io.sb_axi.ar.bits.lock @[quasar_wrapper.scala 117:21] - _T_2.ar.bits.burst <= core.io.sb_axi.ar.bits.burst @[quasar_wrapper.scala 117:21] - _T_2.ar.bits.size <= core.io.sb_axi.ar.bits.size @[quasar_wrapper.scala 117:21] - _T_2.ar.bits.len <= core.io.sb_axi.ar.bits.len @[quasar_wrapper.scala 117:21] - _T_2.ar.bits.region <= core.io.sb_axi.ar.bits.region @[quasar_wrapper.scala 117:21] - _T_2.ar.bits.addr <= core.io.sb_axi.ar.bits.addr @[quasar_wrapper.scala 117:21] - _T_2.ar.bits.id <= core.io.sb_axi.ar.bits.id @[quasar_wrapper.scala 117:21] - _T_2.ar.valid <= core.io.sb_axi.ar.valid @[quasar_wrapper.scala 117:21] - core.io.sb_axi.ar.ready <= _T_2.ar.ready @[quasar_wrapper.scala 117:21] - core.io.sb_axi.b.bits.id <= _T_2.b.bits.id @[quasar_wrapper.scala 117:21] - core.io.sb_axi.b.bits.resp <= _T_2.b.bits.resp @[quasar_wrapper.scala 117:21] - core.io.sb_axi.b.valid <= _T_2.b.valid @[quasar_wrapper.scala 117:21] - _T_2.b.ready <= core.io.sb_axi.b.ready @[quasar_wrapper.scala 117:21] - _T_2.w.bits.last <= core.io.sb_axi.w.bits.last @[quasar_wrapper.scala 117:21] - _T_2.w.bits.strb <= core.io.sb_axi.w.bits.strb @[quasar_wrapper.scala 117:21] - _T_2.w.bits.data <= core.io.sb_axi.w.bits.data @[quasar_wrapper.scala 117:21] - _T_2.w.valid <= core.io.sb_axi.w.valid @[quasar_wrapper.scala 117:21] - core.io.sb_axi.w.ready <= _T_2.w.ready @[quasar_wrapper.scala 117:21] - _T_2.aw.bits.qos <= core.io.sb_axi.aw.bits.qos @[quasar_wrapper.scala 117:21] - _T_2.aw.bits.prot <= core.io.sb_axi.aw.bits.prot @[quasar_wrapper.scala 117:21] - _T_2.aw.bits.cache <= core.io.sb_axi.aw.bits.cache @[quasar_wrapper.scala 117:21] - _T_2.aw.bits.lock <= core.io.sb_axi.aw.bits.lock @[quasar_wrapper.scala 117:21] - _T_2.aw.bits.burst <= core.io.sb_axi.aw.bits.burst @[quasar_wrapper.scala 117:21] - _T_2.aw.bits.size <= core.io.sb_axi.aw.bits.size @[quasar_wrapper.scala 117:21] - _T_2.aw.bits.len <= core.io.sb_axi.aw.bits.len @[quasar_wrapper.scala 117:21] - _T_2.aw.bits.region <= core.io.sb_axi.aw.bits.region @[quasar_wrapper.scala 117:21] - _T_2.aw.bits.addr <= core.io.sb_axi.aw.bits.addr @[quasar_wrapper.scala 117:21] - _T_2.aw.bits.id <= core.io.sb_axi.aw.bits.id @[quasar_wrapper.scala 117:21] - _T_2.aw.valid <= core.io.sb_axi.aw.valid @[quasar_wrapper.scala 117:21] - core.io.sb_axi.aw.ready <= _T_2.aw.ready @[quasar_wrapper.scala 117:21] - wire _T_3 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar_wrapper.scala 118:36] - _T_3.r.bits.last <= UInt<1>("h00") @[quasar_wrapper.scala 118:36] - _T_3.r.bits.resp <= UInt<2>("h00") @[quasar_wrapper.scala 118:36] - _T_3.r.bits.data <= UInt<64>("h00") @[quasar_wrapper.scala 118:36] - _T_3.r.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 118:36] - _T_3.r.valid <= UInt<1>("h00") @[quasar_wrapper.scala 118:36] - _T_3.r.ready <= UInt<1>("h00") @[quasar_wrapper.scala 118:36] - _T_3.ar.bits.qos <= UInt<4>("h00") @[quasar_wrapper.scala 118:36] - _T_3.ar.bits.prot <= UInt<3>("h00") @[quasar_wrapper.scala 118:36] - _T_3.ar.bits.cache <= UInt<4>("h00") @[quasar_wrapper.scala 118:36] - _T_3.ar.bits.lock <= UInt<1>("h00") @[quasar_wrapper.scala 118:36] - _T_3.ar.bits.burst <= UInt<2>("h00") @[quasar_wrapper.scala 118:36] - _T_3.ar.bits.size <= UInt<3>("h00") @[quasar_wrapper.scala 118:36] - _T_3.ar.bits.len <= UInt<8>("h00") @[quasar_wrapper.scala 118:36] - _T_3.ar.bits.region <= UInt<4>("h00") @[quasar_wrapper.scala 118:36] - _T_3.ar.bits.addr <= UInt<32>("h00") @[quasar_wrapper.scala 118:36] - _T_3.ar.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 118:36] - _T_3.ar.valid <= UInt<1>("h00") @[quasar_wrapper.scala 118:36] - _T_3.ar.ready <= UInt<1>("h00") @[quasar_wrapper.scala 118:36] - _T_3.b.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 118:36] - _T_3.b.bits.resp <= UInt<2>("h00") @[quasar_wrapper.scala 118:36] - _T_3.b.valid <= UInt<1>("h00") @[quasar_wrapper.scala 118:36] - _T_3.b.ready <= UInt<1>("h00") @[quasar_wrapper.scala 118:36] - _T_3.w.bits.last <= UInt<1>("h00") @[quasar_wrapper.scala 118:36] - _T_3.w.bits.strb <= UInt<8>("h00") @[quasar_wrapper.scala 118:36] - _T_3.w.bits.data <= UInt<64>("h00") @[quasar_wrapper.scala 118:36] - _T_3.w.valid <= UInt<1>("h00") @[quasar_wrapper.scala 118:36] - _T_3.w.ready <= UInt<1>("h00") @[quasar_wrapper.scala 118:36] - _T_3.aw.bits.qos <= UInt<4>("h00") @[quasar_wrapper.scala 118:36] - _T_3.aw.bits.prot <= UInt<3>("h00") @[quasar_wrapper.scala 118:36] - _T_3.aw.bits.cache <= UInt<4>("h00") @[quasar_wrapper.scala 118:36] - _T_3.aw.bits.lock <= UInt<1>("h00") @[quasar_wrapper.scala 118:36] - _T_3.aw.bits.burst <= UInt<2>("h00") @[quasar_wrapper.scala 118:36] - _T_3.aw.bits.size <= UInt<3>("h00") @[quasar_wrapper.scala 118:36] - _T_3.aw.bits.len <= UInt<8>("h00") @[quasar_wrapper.scala 118:36] - _T_3.aw.bits.region <= UInt<4>("h00") @[quasar_wrapper.scala 118:36] - _T_3.aw.bits.addr <= UInt<32>("h00") @[quasar_wrapper.scala 118:36] - _T_3.aw.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 118:36] - _T_3.aw.valid <= UInt<1>("h00") @[quasar_wrapper.scala 118:36] - _T_3.aw.ready <= UInt<1>("h00") @[quasar_wrapper.scala 118:36] - _T_3.r.bits.last <= core.io.dma_axi.r.bits.last @[quasar_wrapper.scala 118:21] - _T_3.r.bits.resp <= core.io.dma_axi.r.bits.resp @[quasar_wrapper.scala 118:21] - _T_3.r.bits.data <= core.io.dma_axi.r.bits.data @[quasar_wrapper.scala 118:21] - _T_3.r.bits.id <= core.io.dma_axi.r.bits.id @[quasar_wrapper.scala 118:21] - _T_3.r.valid <= core.io.dma_axi.r.valid @[quasar_wrapper.scala 118:21] - core.io.dma_axi.r.ready <= _T_3.r.ready @[quasar_wrapper.scala 118:21] - core.io.dma_axi.ar.bits.qos <= _T_3.ar.bits.qos @[quasar_wrapper.scala 118:21] - core.io.dma_axi.ar.bits.prot <= _T_3.ar.bits.prot @[quasar_wrapper.scala 118:21] - core.io.dma_axi.ar.bits.cache <= _T_3.ar.bits.cache @[quasar_wrapper.scala 118:21] - core.io.dma_axi.ar.bits.lock <= _T_3.ar.bits.lock @[quasar_wrapper.scala 118:21] - core.io.dma_axi.ar.bits.burst <= _T_3.ar.bits.burst @[quasar_wrapper.scala 118:21] - core.io.dma_axi.ar.bits.size <= _T_3.ar.bits.size @[quasar_wrapper.scala 118:21] - core.io.dma_axi.ar.bits.len <= _T_3.ar.bits.len @[quasar_wrapper.scala 118:21] - core.io.dma_axi.ar.bits.region <= _T_3.ar.bits.region @[quasar_wrapper.scala 118:21] - core.io.dma_axi.ar.bits.addr <= _T_3.ar.bits.addr @[quasar_wrapper.scala 118:21] - core.io.dma_axi.ar.bits.id <= _T_3.ar.bits.id @[quasar_wrapper.scala 118:21] - core.io.dma_axi.ar.valid <= _T_3.ar.valid @[quasar_wrapper.scala 118:21] - _T_3.ar.ready <= core.io.dma_axi.ar.ready @[quasar_wrapper.scala 118:21] - _T_3.b.bits.id <= core.io.dma_axi.b.bits.id @[quasar_wrapper.scala 118:21] - _T_3.b.bits.resp <= core.io.dma_axi.b.bits.resp @[quasar_wrapper.scala 118:21] - _T_3.b.valid <= core.io.dma_axi.b.valid @[quasar_wrapper.scala 118:21] - core.io.dma_axi.b.ready <= _T_3.b.ready @[quasar_wrapper.scala 118:21] - core.io.dma_axi.w.bits.last <= _T_3.w.bits.last @[quasar_wrapper.scala 118:21] - core.io.dma_axi.w.bits.strb <= _T_3.w.bits.strb @[quasar_wrapper.scala 118:21] - core.io.dma_axi.w.bits.data <= _T_3.w.bits.data @[quasar_wrapper.scala 118:21] - core.io.dma_axi.w.valid <= _T_3.w.valid @[quasar_wrapper.scala 118:21] - _T_3.w.ready <= core.io.dma_axi.w.ready @[quasar_wrapper.scala 118:21] - core.io.dma_axi.aw.bits.qos <= _T_3.aw.bits.qos @[quasar_wrapper.scala 118:21] - core.io.dma_axi.aw.bits.prot <= _T_3.aw.bits.prot @[quasar_wrapper.scala 118:21] - core.io.dma_axi.aw.bits.cache <= _T_3.aw.bits.cache @[quasar_wrapper.scala 118:21] - core.io.dma_axi.aw.bits.lock <= _T_3.aw.bits.lock @[quasar_wrapper.scala 118:21] - core.io.dma_axi.aw.bits.burst <= _T_3.aw.bits.burst @[quasar_wrapper.scala 118:21] - core.io.dma_axi.aw.bits.size <= _T_3.aw.bits.size @[quasar_wrapper.scala 118:21] - core.io.dma_axi.aw.bits.len <= _T_3.aw.bits.len @[quasar_wrapper.scala 118:21] - core.io.dma_axi.aw.bits.region <= _T_3.aw.bits.region @[quasar_wrapper.scala 118:21] - core.io.dma_axi.aw.bits.addr <= _T_3.aw.bits.addr @[quasar_wrapper.scala 118:21] - core.io.dma_axi.aw.bits.id <= _T_3.aw.bits.id @[quasar_wrapper.scala 118:21] - core.io.dma_axi.aw.valid <= _T_3.aw.valid @[quasar_wrapper.scala 118:21] - _T_3.aw.ready <= core.io.dma_axi.aw.ready @[quasar_wrapper.scala 118:21] + wire _T : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}} @[quasar_wrapper.scala 99:36] + _T.out.hwdata <= UInt<64>("h00") @[quasar_wrapper.scala 99:36] + _T.out.hwrite <= UInt<1>("h00") @[quasar_wrapper.scala 99:36] + _T.out.htrans <= UInt<2>("h00") @[quasar_wrapper.scala 99:36] + _T.out.hsize <= UInt<3>("h00") @[quasar_wrapper.scala 99:36] + _T.out.hprot <= UInt<4>("h00") @[quasar_wrapper.scala 99:36] + _T.out.hmastlock <= UInt<1>("h00") @[quasar_wrapper.scala 99:36] + _T.out.hburst <= UInt<3>("h00") @[quasar_wrapper.scala 99:36] + _T.out.haddr <= UInt<32>("h00") @[quasar_wrapper.scala 99:36] + _T.in.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 99:36] + _T.in.hready <= UInt<1>("h00") @[quasar_wrapper.scala 99:36] + _T.in.hrdata <= UInt<64>("h00") @[quasar_wrapper.scala 99:36] + _T.out.hwdata <= core.io.ifu_ahb.out.hwdata @[quasar_wrapper.scala 99:21] + _T.out.hwrite <= core.io.ifu_ahb.out.hwrite @[quasar_wrapper.scala 99:21] + _T.out.htrans <= core.io.ifu_ahb.out.htrans @[quasar_wrapper.scala 99:21] + _T.out.hsize <= core.io.ifu_ahb.out.hsize @[quasar_wrapper.scala 99:21] + _T.out.hprot <= core.io.ifu_ahb.out.hprot @[quasar_wrapper.scala 99:21] + _T.out.hmastlock <= core.io.ifu_ahb.out.hmastlock @[quasar_wrapper.scala 99:21] + _T.out.hburst <= core.io.ifu_ahb.out.hburst @[quasar_wrapper.scala 99:21] + _T.out.haddr <= core.io.ifu_ahb.out.haddr @[quasar_wrapper.scala 99:21] + core.io.ifu_ahb.in.hresp <= _T.in.hresp @[quasar_wrapper.scala 99:21] + core.io.ifu_ahb.in.hready <= _T.in.hready @[quasar_wrapper.scala 99:21] + core.io.ifu_ahb.in.hrdata <= _T.in.hrdata @[quasar_wrapper.scala 99:21] + wire _T_1 : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}} @[quasar_wrapper.scala 100:36] + _T_1.out.hwdata <= UInt<64>("h00") @[quasar_wrapper.scala 100:36] + _T_1.out.hwrite <= UInt<1>("h00") @[quasar_wrapper.scala 100:36] + _T_1.out.htrans <= UInt<2>("h00") @[quasar_wrapper.scala 100:36] + _T_1.out.hsize <= UInt<3>("h00") @[quasar_wrapper.scala 100:36] + _T_1.out.hprot <= UInt<4>("h00") @[quasar_wrapper.scala 100:36] + _T_1.out.hmastlock <= UInt<1>("h00") @[quasar_wrapper.scala 100:36] + _T_1.out.hburst <= UInt<3>("h00") @[quasar_wrapper.scala 100:36] + _T_1.out.haddr <= UInt<32>("h00") @[quasar_wrapper.scala 100:36] + _T_1.in.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 100:36] + _T_1.in.hready <= UInt<1>("h00") @[quasar_wrapper.scala 100:36] + _T_1.in.hrdata <= UInt<64>("h00") @[quasar_wrapper.scala 100:36] + _T_1.out.hwdata <= core.io.lsu_ahb.out.hwdata @[quasar_wrapper.scala 100:21] + _T_1.out.hwrite <= core.io.lsu_ahb.out.hwrite @[quasar_wrapper.scala 100:21] + _T_1.out.htrans <= core.io.lsu_ahb.out.htrans @[quasar_wrapper.scala 100:21] + _T_1.out.hsize <= core.io.lsu_ahb.out.hsize @[quasar_wrapper.scala 100:21] + _T_1.out.hprot <= core.io.lsu_ahb.out.hprot @[quasar_wrapper.scala 100:21] + _T_1.out.hmastlock <= core.io.lsu_ahb.out.hmastlock @[quasar_wrapper.scala 100:21] + _T_1.out.hburst <= core.io.lsu_ahb.out.hburst @[quasar_wrapper.scala 100:21] + _T_1.out.haddr <= core.io.lsu_ahb.out.haddr @[quasar_wrapper.scala 100:21] + core.io.lsu_ahb.in.hresp <= _T_1.in.hresp @[quasar_wrapper.scala 100:21] + core.io.lsu_ahb.in.hready <= _T_1.in.hready @[quasar_wrapper.scala 100:21] + core.io.lsu_ahb.in.hrdata <= _T_1.in.hrdata @[quasar_wrapper.scala 100:21] + wire _T_2 : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}} @[quasar_wrapper.scala 101:36] + _T_2.out.hwdata <= UInt<64>("h00") @[quasar_wrapper.scala 101:36] + _T_2.out.hwrite <= UInt<1>("h00") @[quasar_wrapper.scala 101:36] + _T_2.out.htrans <= UInt<2>("h00") @[quasar_wrapper.scala 101:36] + _T_2.out.hsize <= UInt<3>("h00") @[quasar_wrapper.scala 101:36] + _T_2.out.hprot <= UInt<4>("h00") @[quasar_wrapper.scala 101:36] + _T_2.out.hmastlock <= UInt<1>("h00") @[quasar_wrapper.scala 101:36] + _T_2.out.hburst <= UInt<3>("h00") @[quasar_wrapper.scala 101:36] + _T_2.out.haddr <= UInt<32>("h00") @[quasar_wrapper.scala 101:36] + _T_2.in.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 101:36] + _T_2.in.hready <= UInt<1>("h00") @[quasar_wrapper.scala 101:36] + _T_2.in.hrdata <= UInt<64>("h00") @[quasar_wrapper.scala 101:36] + _T_2.out.hwdata <= core.io.sb_ahb.out.hwdata @[quasar_wrapper.scala 101:21] + _T_2.out.hwrite <= core.io.sb_ahb.out.hwrite @[quasar_wrapper.scala 101:21] + _T_2.out.htrans <= core.io.sb_ahb.out.htrans @[quasar_wrapper.scala 101:21] + _T_2.out.hsize <= core.io.sb_ahb.out.hsize @[quasar_wrapper.scala 101:21] + _T_2.out.hprot <= core.io.sb_ahb.out.hprot @[quasar_wrapper.scala 101:21] + _T_2.out.hmastlock <= core.io.sb_ahb.out.hmastlock @[quasar_wrapper.scala 101:21] + _T_2.out.hburst <= core.io.sb_ahb.out.hburst @[quasar_wrapper.scala 101:21] + _T_2.out.haddr <= core.io.sb_ahb.out.haddr @[quasar_wrapper.scala 101:21] + core.io.sb_ahb.in.hresp <= _T_2.in.hresp @[quasar_wrapper.scala 101:21] + core.io.sb_ahb.in.hready <= _T_2.in.hready @[quasar_wrapper.scala 101:21] + core.io.sb_ahb.in.hrdata <= _T_2.in.hrdata @[quasar_wrapper.scala 101:21] + wire _T_3 : {flip sig : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, flip hsel : UInt<1>, flip hreadyin : UInt<1>} @[quasar_wrapper.scala 102:36] + _T_3.hreadyin <= UInt<1>("h00") @[quasar_wrapper.scala 102:36] + _T_3.hsel <= UInt<1>("h00") @[quasar_wrapper.scala 102:36] + _T_3.sig.out.hwdata <= UInt<64>("h00") @[quasar_wrapper.scala 102:36] + _T_3.sig.out.hwrite <= UInt<1>("h00") @[quasar_wrapper.scala 102:36] + _T_3.sig.out.htrans <= UInt<2>("h00") @[quasar_wrapper.scala 102:36] + _T_3.sig.out.hsize <= UInt<3>("h00") @[quasar_wrapper.scala 102:36] + _T_3.sig.out.hprot <= UInt<4>("h00") @[quasar_wrapper.scala 102:36] + _T_3.sig.out.hmastlock <= UInt<1>("h00") @[quasar_wrapper.scala 102:36] + _T_3.sig.out.hburst <= UInt<3>("h00") @[quasar_wrapper.scala 102:36] + _T_3.sig.out.haddr <= UInt<32>("h00") @[quasar_wrapper.scala 102:36] + _T_3.sig.in.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 102:36] + _T_3.sig.in.hready <= UInt<1>("h00") @[quasar_wrapper.scala 102:36] + _T_3.sig.in.hrdata <= UInt<64>("h00") @[quasar_wrapper.scala 102:36] + core.io.dma_ahb.hreadyin <= _T_3.hreadyin @[quasar_wrapper.scala 102:21] + core.io.dma_ahb.hsel <= _T_3.hsel @[quasar_wrapper.scala 102:21] + core.io.dma_ahb.sig.out.hwdata <= _T_3.sig.out.hwdata @[quasar_wrapper.scala 102:21] + core.io.dma_ahb.sig.out.hwrite <= _T_3.sig.out.hwrite @[quasar_wrapper.scala 102:21] + core.io.dma_ahb.sig.out.htrans <= _T_3.sig.out.htrans @[quasar_wrapper.scala 102:21] + core.io.dma_ahb.sig.out.hsize <= _T_3.sig.out.hsize @[quasar_wrapper.scala 102:21] + core.io.dma_ahb.sig.out.hprot <= _T_3.sig.out.hprot @[quasar_wrapper.scala 102:21] + core.io.dma_ahb.sig.out.hmastlock <= _T_3.sig.out.hmastlock @[quasar_wrapper.scala 102:21] + core.io.dma_ahb.sig.out.hburst <= _T_3.sig.out.hburst @[quasar_wrapper.scala 102:21] + core.io.dma_ahb.sig.out.haddr <= _T_3.sig.out.haddr @[quasar_wrapper.scala 102:21] + _T_3.sig.in.hresp <= core.io.dma_ahb.sig.in.hresp @[quasar_wrapper.scala 102:21] + _T_3.sig.in.hready <= core.io.dma_ahb.sig.in.hready @[quasar_wrapper.scala 102:21] + _T_3.sig.in.hrdata <= core.io.dma_ahb.sig.in.hrdata @[quasar_wrapper.scala 102:21] + core.io.lsu_axi.r.bits.last <= io.lsu_brg.r.bits.last @[quasar_wrapper.scala 104:21] + core.io.lsu_axi.r.bits.resp <= io.lsu_brg.r.bits.resp @[quasar_wrapper.scala 104:21] + core.io.lsu_axi.r.bits.data <= io.lsu_brg.r.bits.data @[quasar_wrapper.scala 104:21] + core.io.lsu_axi.r.bits.id <= io.lsu_brg.r.bits.id @[quasar_wrapper.scala 104:21] + core.io.lsu_axi.r.valid <= io.lsu_brg.r.valid @[quasar_wrapper.scala 104:21] + io.lsu_brg.r.ready <= core.io.lsu_axi.r.ready @[quasar_wrapper.scala 104:21] + io.lsu_brg.ar.bits.qos <= core.io.lsu_axi.ar.bits.qos @[quasar_wrapper.scala 104:21] + io.lsu_brg.ar.bits.prot <= core.io.lsu_axi.ar.bits.prot @[quasar_wrapper.scala 104:21] + io.lsu_brg.ar.bits.cache <= core.io.lsu_axi.ar.bits.cache @[quasar_wrapper.scala 104:21] + io.lsu_brg.ar.bits.lock <= core.io.lsu_axi.ar.bits.lock @[quasar_wrapper.scala 104:21] + io.lsu_brg.ar.bits.burst <= core.io.lsu_axi.ar.bits.burst @[quasar_wrapper.scala 104:21] + io.lsu_brg.ar.bits.size <= core.io.lsu_axi.ar.bits.size @[quasar_wrapper.scala 104:21] + io.lsu_brg.ar.bits.len <= core.io.lsu_axi.ar.bits.len @[quasar_wrapper.scala 104:21] + io.lsu_brg.ar.bits.region <= core.io.lsu_axi.ar.bits.region @[quasar_wrapper.scala 104:21] + io.lsu_brg.ar.bits.addr <= core.io.lsu_axi.ar.bits.addr @[quasar_wrapper.scala 104:21] + io.lsu_brg.ar.bits.id <= core.io.lsu_axi.ar.bits.id @[quasar_wrapper.scala 104:21] + io.lsu_brg.ar.valid <= core.io.lsu_axi.ar.valid @[quasar_wrapper.scala 104:21] + core.io.lsu_axi.ar.ready <= io.lsu_brg.ar.ready @[quasar_wrapper.scala 104:21] + core.io.lsu_axi.b.bits.id <= io.lsu_brg.b.bits.id @[quasar_wrapper.scala 104:21] + core.io.lsu_axi.b.bits.resp <= io.lsu_brg.b.bits.resp @[quasar_wrapper.scala 104:21] + core.io.lsu_axi.b.valid <= io.lsu_brg.b.valid @[quasar_wrapper.scala 104:21] + io.lsu_brg.b.ready <= core.io.lsu_axi.b.ready @[quasar_wrapper.scala 104:21] + io.lsu_brg.w.bits.last <= core.io.lsu_axi.w.bits.last @[quasar_wrapper.scala 104:21] + io.lsu_brg.w.bits.strb <= core.io.lsu_axi.w.bits.strb @[quasar_wrapper.scala 104:21] + io.lsu_brg.w.bits.data <= core.io.lsu_axi.w.bits.data @[quasar_wrapper.scala 104:21] + io.lsu_brg.w.valid <= core.io.lsu_axi.w.valid @[quasar_wrapper.scala 104:21] + core.io.lsu_axi.w.ready <= io.lsu_brg.w.ready @[quasar_wrapper.scala 104:21] + io.lsu_brg.aw.bits.qos <= core.io.lsu_axi.aw.bits.qos @[quasar_wrapper.scala 104:21] + io.lsu_brg.aw.bits.prot <= core.io.lsu_axi.aw.bits.prot @[quasar_wrapper.scala 104:21] + io.lsu_brg.aw.bits.cache <= core.io.lsu_axi.aw.bits.cache @[quasar_wrapper.scala 104:21] + io.lsu_brg.aw.bits.lock <= core.io.lsu_axi.aw.bits.lock @[quasar_wrapper.scala 104:21] + io.lsu_brg.aw.bits.burst <= core.io.lsu_axi.aw.bits.burst @[quasar_wrapper.scala 104:21] + io.lsu_brg.aw.bits.size <= core.io.lsu_axi.aw.bits.size @[quasar_wrapper.scala 104:21] + io.lsu_brg.aw.bits.len <= core.io.lsu_axi.aw.bits.len @[quasar_wrapper.scala 104:21] + io.lsu_brg.aw.bits.region <= core.io.lsu_axi.aw.bits.region @[quasar_wrapper.scala 104:21] + io.lsu_brg.aw.bits.addr <= core.io.lsu_axi.aw.bits.addr @[quasar_wrapper.scala 104:21] + io.lsu_brg.aw.bits.id <= core.io.lsu_axi.aw.bits.id @[quasar_wrapper.scala 104:21] + io.lsu_brg.aw.valid <= core.io.lsu_axi.aw.valid @[quasar_wrapper.scala 104:21] + core.io.lsu_axi.aw.ready <= io.lsu_brg.aw.ready @[quasar_wrapper.scala 104:21] + core.io.ifu_axi.r.bits.last <= io.ifu_brg.r.bits.last @[quasar_wrapper.scala 105:21] + core.io.ifu_axi.r.bits.resp <= io.ifu_brg.r.bits.resp @[quasar_wrapper.scala 105:21] + core.io.ifu_axi.r.bits.data <= io.ifu_brg.r.bits.data @[quasar_wrapper.scala 105:21] + core.io.ifu_axi.r.bits.id <= io.ifu_brg.r.bits.id @[quasar_wrapper.scala 105:21] + core.io.ifu_axi.r.valid <= io.ifu_brg.r.valid @[quasar_wrapper.scala 105:21] + io.ifu_brg.r.ready <= core.io.ifu_axi.r.ready @[quasar_wrapper.scala 105:21] + io.ifu_brg.ar.bits.qos <= core.io.ifu_axi.ar.bits.qos @[quasar_wrapper.scala 105:21] + io.ifu_brg.ar.bits.prot <= core.io.ifu_axi.ar.bits.prot @[quasar_wrapper.scala 105:21] + io.ifu_brg.ar.bits.cache <= core.io.ifu_axi.ar.bits.cache @[quasar_wrapper.scala 105:21] + io.ifu_brg.ar.bits.lock <= core.io.ifu_axi.ar.bits.lock @[quasar_wrapper.scala 105:21] + io.ifu_brg.ar.bits.burst <= core.io.ifu_axi.ar.bits.burst @[quasar_wrapper.scala 105:21] + io.ifu_brg.ar.bits.size <= core.io.ifu_axi.ar.bits.size @[quasar_wrapper.scala 105:21] + io.ifu_brg.ar.bits.len <= core.io.ifu_axi.ar.bits.len @[quasar_wrapper.scala 105:21] + io.ifu_brg.ar.bits.region <= core.io.ifu_axi.ar.bits.region @[quasar_wrapper.scala 105:21] + io.ifu_brg.ar.bits.addr <= core.io.ifu_axi.ar.bits.addr @[quasar_wrapper.scala 105:21] + io.ifu_brg.ar.bits.id <= core.io.ifu_axi.ar.bits.id @[quasar_wrapper.scala 105:21] + io.ifu_brg.ar.valid <= core.io.ifu_axi.ar.valid @[quasar_wrapper.scala 105:21] + core.io.ifu_axi.ar.ready <= io.ifu_brg.ar.ready @[quasar_wrapper.scala 105:21] + core.io.ifu_axi.b.bits.id <= io.ifu_brg.b.bits.id @[quasar_wrapper.scala 105:21] + core.io.ifu_axi.b.bits.resp <= io.ifu_brg.b.bits.resp @[quasar_wrapper.scala 105:21] + core.io.ifu_axi.b.valid <= io.ifu_brg.b.valid @[quasar_wrapper.scala 105:21] + io.ifu_brg.b.ready <= core.io.ifu_axi.b.ready @[quasar_wrapper.scala 105:21] + io.ifu_brg.w.bits.last <= core.io.ifu_axi.w.bits.last @[quasar_wrapper.scala 105:21] + io.ifu_brg.w.bits.strb <= core.io.ifu_axi.w.bits.strb @[quasar_wrapper.scala 105:21] + io.ifu_brg.w.bits.data <= core.io.ifu_axi.w.bits.data @[quasar_wrapper.scala 105:21] + io.ifu_brg.w.valid <= core.io.ifu_axi.w.valid @[quasar_wrapper.scala 105:21] + core.io.ifu_axi.w.ready <= io.ifu_brg.w.ready @[quasar_wrapper.scala 105:21] + io.ifu_brg.aw.bits.qos <= core.io.ifu_axi.aw.bits.qos @[quasar_wrapper.scala 105:21] + io.ifu_brg.aw.bits.prot <= core.io.ifu_axi.aw.bits.prot @[quasar_wrapper.scala 105:21] + io.ifu_brg.aw.bits.cache <= core.io.ifu_axi.aw.bits.cache @[quasar_wrapper.scala 105:21] + io.ifu_brg.aw.bits.lock <= core.io.ifu_axi.aw.bits.lock @[quasar_wrapper.scala 105:21] + io.ifu_brg.aw.bits.burst <= core.io.ifu_axi.aw.bits.burst @[quasar_wrapper.scala 105:21] + io.ifu_brg.aw.bits.size <= core.io.ifu_axi.aw.bits.size @[quasar_wrapper.scala 105:21] + io.ifu_brg.aw.bits.len <= core.io.ifu_axi.aw.bits.len @[quasar_wrapper.scala 105:21] + io.ifu_brg.aw.bits.region <= core.io.ifu_axi.aw.bits.region @[quasar_wrapper.scala 105:21] + io.ifu_brg.aw.bits.addr <= core.io.ifu_axi.aw.bits.addr @[quasar_wrapper.scala 105:21] + io.ifu_brg.aw.bits.id <= core.io.ifu_axi.aw.bits.id @[quasar_wrapper.scala 105:21] + io.ifu_brg.aw.valid <= core.io.ifu_axi.aw.valid @[quasar_wrapper.scala 105:21] + core.io.ifu_axi.aw.ready <= io.ifu_brg.aw.ready @[quasar_wrapper.scala 105:21] + core.io.sb_axi.r.bits.last <= io.sb_brg.r.bits.last @[quasar_wrapper.scala 106:21] + core.io.sb_axi.r.bits.resp <= io.sb_brg.r.bits.resp @[quasar_wrapper.scala 106:21] + core.io.sb_axi.r.bits.data <= io.sb_brg.r.bits.data @[quasar_wrapper.scala 106:21] + core.io.sb_axi.r.bits.id <= io.sb_brg.r.bits.id @[quasar_wrapper.scala 106:21] + core.io.sb_axi.r.valid <= io.sb_brg.r.valid @[quasar_wrapper.scala 106:21] + io.sb_brg.r.ready <= core.io.sb_axi.r.ready @[quasar_wrapper.scala 106:21] + io.sb_brg.ar.bits.qos <= core.io.sb_axi.ar.bits.qos @[quasar_wrapper.scala 106:21] + io.sb_brg.ar.bits.prot <= core.io.sb_axi.ar.bits.prot @[quasar_wrapper.scala 106:21] + io.sb_brg.ar.bits.cache <= core.io.sb_axi.ar.bits.cache @[quasar_wrapper.scala 106:21] + io.sb_brg.ar.bits.lock <= core.io.sb_axi.ar.bits.lock @[quasar_wrapper.scala 106:21] + io.sb_brg.ar.bits.burst <= core.io.sb_axi.ar.bits.burst @[quasar_wrapper.scala 106:21] + io.sb_brg.ar.bits.size <= core.io.sb_axi.ar.bits.size @[quasar_wrapper.scala 106:21] + io.sb_brg.ar.bits.len <= core.io.sb_axi.ar.bits.len @[quasar_wrapper.scala 106:21] + io.sb_brg.ar.bits.region <= core.io.sb_axi.ar.bits.region @[quasar_wrapper.scala 106:21] + io.sb_brg.ar.bits.addr <= core.io.sb_axi.ar.bits.addr @[quasar_wrapper.scala 106:21] + io.sb_brg.ar.bits.id <= core.io.sb_axi.ar.bits.id @[quasar_wrapper.scala 106:21] + io.sb_brg.ar.valid <= core.io.sb_axi.ar.valid @[quasar_wrapper.scala 106:21] + core.io.sb_axi.ar.ready <= io.sb_brg.ar.ready @[quasar_wrapper.scala 106:21] + core.io.sb_axi.b.bits.id <= io.sb_brg.b.bits.id @[quasar_wrapper.scala 106:21] + core.io.sb_axi.b.bits.resp <= io.sb_brg.b.bits.resp @[quasar_wrapper.scala 106:21] + core.io.sb_axi.b.valid <= io.sb_brg.b.valid @[quasar_wrapper.scala 106:21] + io.sb_brg.b.ready <= core.io.sb_axi.b.ready @[quasar_wrapper.scala 106:21] + io.sb_brg.w.bits.last <= core.io.sb_axi.w.bits.last @[quasar_wrapper.scala 106:21] + io.sb_brg.w.bits.strb <= core.io.sb_axi.w.bits.strb @[quasar_wrapper.scala 106:21] + io.sb_brg.w.bits.data <= core.io.sb_axi.w.bits.data @[quasar_wrapper.scala 106:21] + io.sb_brg.w.valid <= core.io.sb_axi.w.valid @[quasar_wrapper.scala 106:21] + core.io.sb_axi.w.ready <= io.sb_brg.w.ready @[quasar_wrapper.scala 106:21] + io.sb_brg.aw.bits.qos <= core.io.sb_axi.aw.bits.qos @[quasar_wrapper.scala 106:21] + io.sb_brg.aw.bits.prot <= core.io.sb_axi.aw.bits.prot @[quasar_wrapper.scala 106:21] + io.sb_brg.aw.bits.cache <= core.io.sb_axi.aw.bits.cache @[quasar_wrapper.scala 106:21] + io.sb_brg.aw.bits.lock <= core.io.sb_axi.aw.bits.lock @[quasar_wrapper.scala 106:21] + io.sb_brg.aw.bits.burst <= core.io.sb_axi.aw.bits.burst @[quasar_wrapper.scala 106:21] + io.sb_brg.aw.bits.size <= core.io.sb_axi.aw.bits.size @[quasar_wrapper.scala 106:21] + io.sb_brg.aw.bits.len <= core.io.sb_axi.aw.bits.len @[quasar_wrapper.scala 106:21] + io.sb_brg.aw.bits.region <= core.io.sb_axi.aw.bits.region @[quasar_wrapper.scala 106:21] + io.sb_brg.aw.bits.addr <= core.io.sb_axi.aw.bits.addr @[quasar_wrapper.scala 106:21] + io.sb_brg.aw.bits.id <= core.io.sb_axi.aw.bits.id @[quasar_wrapper.scala 106:21] + io.sb_brg.aw.valid <= core.io.sb_axi.aw.valid @[quasar_wrapper.scala 106:21] + core.io.sb_axi.aw.ready <= io.sb_brg.aw.ready @[quasar_wrapper.scala 106:21] + io.dma_brg.r.bits.last <= core.io.dma_axi.r.bits.last @[quasar_wrapper.scala 107:21] + io.dma_brg.r.bits.resp <= core.io.dma_axi.r.bits.resp @[quasar_wrapper.scala 107:21] + io.dma_brg.r.bits.data <= core.io.dma_axi.r.bits.data @[quasar_wrapper.scala 107:21] + io.dma_brg.r.bits.id <= core.io.dma_axi.r.bits.id @[quasar_wrapper.scala 107:21] + io.dma_brg.r.valid <= core.io.dma_axi.r.valid @[quasar_wrapper.scala 107:21] + core.io.dma_axi.r.ready <= io.dma_brg.r.ready @[quasar_wrapper.scala 107:21] + core.io.dma_axi.ar.bits.qos <= io.dma_brg.ar.bits.qos @[quasar_wrapper.scala 107:21] + core.io.dma_axi.ar.bits.prot <= io.dma_brg.ar.bits.prot @[quasar_wrapper.scala 107:21] + core.io.dma_axi.ar.bits.cache <= io.dma_brg.ar.bits.cache @[quasar_wrapper.scala 107:21] + core.io.dma_axi.ar.bits.lock <= io.dma_brg.ar.bits.lock @[quasar_wrapper.scala 107:21] + core.io.dma_axi.ar.bits.burst <= io.dma_brg.ar.bits.burst @[quasar_wrapper.scala 107:21] + core.io.dma_axi.ar.bits.size <= io.dma_brg.ar.bits.size @[quasar_wrapper.scala 107:21] + core.io.dma_axi.ar.bits.len <= io.dma_brg.ar.bits.len @[quasar_wrapper.scala 107:21] + core.io.dma_axi.ar.bits.region <= io.dma_brg.ar.bits.region @[quasar_wrapper.scala 107:21] + core.io.dma_axi.ar.bits.addr <= io.dma_brg.ar.bits.addr @[quasar_wrapper.scala 107:21] + core.io.dma_axi.ar.bits.id <= io.dma_brg.ar.bits.id @[quasar_wrapper.scala 107:21] + core.io.dma_axi.ar.valid <= io.dma_brg.ar.valid @[quasar_wrapper.scala 107:21] + io.dma_brg.ar.ready <= core.io.dma_axi.ar.ready @[quasar_wrapper.scala 107:21] + io.dma_brg.b.bits.id <= core.io.dma_axi.b.bits.id @[quasar_wrapper.scala 107:21] + io.dma_brg.b.bits.resp <= core.io.dma_axi.b.bits.resp @[quasar_wrapper.scala 107:21] + io.dma_brg.b.valid <= core.io.dma_axi.b.valid @[quasar_wrapper.scala 107:21] + core.io.dma_axi.b.ready <= io.dma_brg.b.ready @[quasar_wrapper.scala 107:21] + core.io.dma_axi.w.bits.last <= io.dma_brg.w.bits.last @[quasar_wrapper.scala 107:21] + core.io.dma_axi.w.bits.strb <= io.dma_brg.w.bits.strb @[quasar_wrapper.scala 107:21] + core.io.dma_axi.w.bits.data <= io.dma_brg.w.bits.data @[quasar_wrapper.scala 107:21] + core.io.dma_axi.w.valid <= io.dma_brg.w.valid @[quasar_wrapper.scala 107:21] + io.dma_brg.w.ready <= core.io.dma_axi.w.ready @[quasar_wrapper.scala 107:21] + core.io.dma_axi.aw.bits.qos <= io.dma_brg.aw.bits.qos @[quasar_wrapper.scala 107:21] + core.io.dma_axi.aw.bits.prot <= io.dma_brg.aw.bits.prot @[quasar_wrapper.scala 107:21] + core.io.dma_axi.aw.bits.cache <= io.dma_brg.aw.bits.cache @[quasar_wrapper.scala 107:21] + core.io.dma_axi.aw.bits.lock <= io.dma_brg.aw.bits.lock @[quasar_wrapper.scala 107:21] + core.io.dma_axi.aw.bits.burst <= io.dma_brg.aw.bits.burst @[quasar_wrapper.scala 107:21] + core.io.dma_axi.aw.bits.size <= io.dma_brg.aw.bits.size @[quasar_wrapper.scala 107:21] + core.io.dma_axi.aw.bits.len <= io.dma_brg.aw.bits.len @[quasar_wrapper.scala 107:21] + core.io.dma_axi.aw.bits.region <= io.dma_brg.aw.bits.region @[quasar_wrapper.scala 107:21] + core.io.dma_axi.aw.bits.addr <= io.dma_brg.aw.bits.addr @[quasar_wrapper.scala 107:21] + core.io.dma_axi.aw.bits.id <= io.dma_brg.aw.bits.id @[quasar_wrapper.scala 107:21] + core.io.dma_axi.aw.valid <= io.dma_brg.aw.valid @[quasar_wrapper.scala 107:21] + io.dma_brg.aw.ready <= core.io.dma_axi.aw.ready @[quasar_wrapper.scala 107:21] core.io.dbg_rst_l <= io.dbg_rst_l @[quasar_wrapper.scala 121:21] core.io.rst_vec <= io.rst_vec @[quasar_wrapper.scala 122:19] core.io.nmi_int <= io.nmi_int @[quasar_wrapper.scala 123:19] diff --git a/quasar_wrapper.v b/quasar_wrapper.v index 6eb457d5..627e99fb 100644 --- a/quasar_wrapper.v +++ b/quasar_wrapper.v @@ -57,6 +57,7 @@ module ifu_mem_ctl( output io_ifu_axi_ar_valid, output [2:0] io_ifu_axi_ar_bits_id, output [31:0] io_ifu_axi_ar_bits_addr, + output [3:0] io_ifu_axi_ar_bits_region, output io_ifu_axi_r_ready, input io_ifu_axi_r_valid, input [2:0] io_ifu_axi_r_bits_id, @@ -1928,6 +1929,7 @@ module ifu_mem_ctl( wire _T_318 = ~stream_miss_f; // @[ifu_mem_ctl.scala 226:106] reg ifc_region_acc_fault_f; // @[ifu_mem_ctl.scala 232:68] reg [2:0] bus_rd_addr_count; // @[ifu_mem_ctl.scala 540:55] + wire [28:0] ifu_ic_req_addr_f = {miss_addr,bus_rd_addr_count}; // @[Cat.scala 29:58] wire _T_325 = _T_239 | _T_2268; // @[ifu_mem_ctl.scala 234:55] wire _T_328 = _T_325 & _T_56; // @[ifu_mem_ctl.scala 234:82] wire _T_2289 = ~ifu_bus_rid_ff[0]; // @[ifu_mem_ctl.scala 378:55] @@ -5660,6 +5662,7 @@ module ifu_mem_ctl( assign io_ifu_axi_ar_valid = ifu_bus_cmd_valid; // @[ifu_mem_ctl.scala 497:23] assign io_ifu_axi_ar_bits_id = bus_rd_addr_count & _T_2608; // @[ifu_mem_ctl.scala 498:25] assign io_ifu_axi_ar_bits_addr = _T_2610 & _T_2612; // @[ifu_mem_ctl.scala 499:27] + assign io_ifu_axi_ar_bits_region = ifu_ic_req_addr_f[28:25]; // @[ifu_mem_ctl.scala 502:29] assign io_ifu_axi_r_ready = 1'h1; // @[ifu_mem_ctl.scala 504:22] assign io_iccm_rw_addr = _T_3110 ? io_dma_mem_ctl_dma_mem_addr[15:1] : _T_3117; // @[ifu_mem_ctl.scala 599:19] assign io_iccm_buf_correct_ecc = iccm_correct_ecc & _T_2497; // @[ifu_mem_ctl.scala 395:27] @@ -44530,6 +44533,7 @@ module ifu( output io_ifu_ar_valid, output [2:0] io_ifu_ar_bits_id, output [31:0] io_ifu_ar_bits_addr, + output [3:0] io_ifu_ar_bits_region, input io_ifu_r_valid, input [2:0] io_ifu_r_bits_id, input [63:0] io_ifu_r_bits_data, @@ -44588,6 +44592,7 @@ module ifu( wire mem_ctl_io_ifu_axi_ar_valid; // @[ifu.scala 34:23] wire [2:0] mem_ctl_io_ifu_axi_ar_bits_id; // @[ifu.scala 34:23] wire [31:0] mem_ctl_io_ifu_axi_ar_bits_addr; // @[ifu.scala 34:23] + wire [3:0] mem_ctl_io_ifu_axi_ar_bits_region; // @[ifu.scala 34:23] wire mem_ctl_io_ifu_axi_r_ready; // @[ifu.scala 34:23] wire mem_ctl_io_ifu_axi_r_valid; // @[ifu.scala 34:23] wire [2:0] mem_ctl_io_ifu_axi_r_bits_id; // @[ifu.scala 34:23] @@ -44803,6 +44808,7 @@ module ifu( .io_ifu_axi_ar_valid(mem_ctl_io_ifu_axi_ar_valid), .io_ifu_axi_ar_bits_id(mem_ctl_io_ifu_axi_ar_bits_id), .io_ifu_axi_ar_bits_addr(mem_ctl_io_ifu_axi_ar_bits_addr), + .io_ifu_axi_ar_bits_region(mem_ctl_io_ifu_axi_ar_bits_region), .io_ifu_axi_r_ready(mem_ctl_io_ifu_axi_r_ready), .io_ifu_axi_r_valid(mem_ctl_io_ifu_axi_r_valid), .io_ifu_axi_r_bits_id(mem_ctl_io_ifu_axi_r_bits_id), @@ -45043,6 +45049,7 @@ module ifu( assign io_ifu_ar_valid = mem_ctl_io_ifu_axi_ar_valid; // @[ifu.scala 103:22] assign io_ifu_ar_bits_id = mem_ctl_io_ifu_axi_ar_bits_id; // @[ifu.scala 103:22] assign io_ifu_ar_bits_addr = mem_ctl_io_ifu_axi_ar_bits_addr; // @[ifu.scala 103:22] + assign io_ifu_ar_bits_region = mem_ctl_io_ifu_axi_ar_bits_region; // @[ifu.scala 103:22] assign io_iccm_dma_ecc_error = mem_ctl_io_iccm_dma_ecc_error; // @[ifu.scala 113:25] assign io_iccm_dma_rvalid = mem_ctl_io_iccm_dma_rvalid; // @[ifu.scala 114:22] assign io_iccm_dma_rdata = mem_ctl_io_iccm_dma_rdata; // @[ifu.scala 115:21] @@ -50182,56 +50189,56 @@ module dec_timer_ctl( wire rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23] reg [31:0] mitcnt0; // @[lib.scala 374:16] reg [31:0] mitb0_b; // @[lib.scala 374:16] - wire [31:0] mitb0 = ~mitb0_b; // @[dec_tlu_ctl.scala 2713:22] - wire mit0_match_ns = mitcnt0 >= mitb0; // @[dec_tlu_ctl.scala 2674:36] + wire [31:0] mitb0 = ~mitb0_b; // @[dec_tlu_ctl.scala 2711:22] + wire mit0_match_ns = mitcnt0 >= mitb0; // @[dec_tlu_ctl.scala 2672:36] reg [31:0] mitcnt1; // @[lib.scala 374:16] reg [31:0] mitb1_b; // @[lib.scala 374:16] - wire [31:0] mitb1 = ~mitb1_b; // @[dec_tlu_ctl.scala 2722:18] - wire mit1_match_ns = mitcnt1 >= mitb1; // @[dec_tlu_ctl.scala 2675:36] - wire _T = io_dec_csr_wraddr_r == 12'h7d2; // @[dec_tlu_ctl.scala 2685:72] - wire wr_mitcnt0_r = io_dec_csr_wen_r_mod & _T; // @[dec_tlu_ctl.scala 2685:49] - reg [1:0] _T_57; // @[dec_tlu_ctl.scala 2738:67] - reg mitctl0_0_b; // @[dec_tlu_ctl.scala 2737:60] - wire _T_58 = ~mitctl0_0_b; // @[dec_tlu_ctl.scala 2738:90] + wire [31:0] mitb1 = ~mitb1_b; // @[dec_tlu_ctl.scala 2720:18] + wire mit1_match_ns = mitcnt1 >= mitb1; // @[dec_tlu_ctl.scala 2673:36] + wire _T = io_dec_csr_wraddr_r == 12'h7d2; // @[dec_tlu_ctl.scala 2683:72] + wire wr_mitcnt0_r = io_dec_csr_wen_r_mod & _T; // @[dec_tlu_ctl.scala 2683:49] + reg [1:0] _T_57; // @[dec_tlu_ctl.scala 2736:67] + reg mitctl0_0_b; // @[dec_tlu_ctl.scala 2735:60] + wire _T_58 = ~mitctl0_0_b; // @[dec_tlu_ctl.scala 2736:90] wire [2:0] mitctl0 = {_T_57,_T_58}; // @[Cat.scala 29:58] - wire _T_2 = ~io_dec_pause_state; // @[dec_tlu_ctl.scala 2687:56] - wire _T_4 = _T_2 | mitctl0[2]; // @[dec_tlu_ctl.scala 2687:76] - wire _T_5 = mitctl0[0] & _T_4; // @[dec_tlu_ctl.scala 2687:53] - wire _T_6 = ~io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 2687:112] - wire _T_8 = _T_6 | mitctl0[1]; // @[dec_tlu_ctl.scala 2687:138] - wire _T_9 = _T_5 & _T_8; // @[dec_tlu_ctl.scala 2687:109] - wire _T_10 = ~io_internal_dbg_halt_timers; // @[dec_tlu_ctl.scala 2687:173] - wire mitcnt0_inc_ok = _T_9 & _T_10; // @[dec_tlu_ctl.scala 2687:171] - wire [31:0] mitcnt0_inc = mitcnt0 + 32'h1; // @[dec_tlu_ctl.scala 2688:35] - wire _T_15 = wr_mitcnt0_r | mitcnt0_inc_ok; // @[dec_tlu_ctl.scala 2690:59] - wire _T_19 = io_dec_csr_wraddr_r == 12'h7d5; // @[dec_tlu_ctl.scala 2697:72] - wire wr_mitcnt1_r = io_dec_csr_wen_r_mod & _T_19; // @[dec_tlu_ctl.scala 2697:49] - reg [2:0] _T_66; // @[dec_tlu_ctl.scala 2752:52] - reg mitctl1_0_b; // @[dec_tlu_ctl.scala 2751:55] - wire _T_67 = ~mitctl1_0_b; // @[dec_tlu_ctl.scala 2752:75] + wire _T_2 = ~io_dec_pause_state; // @[dec_tlu_ctl.scala 2685:56] + wire _T_4 = _T_2 | mitctl0[2]; // @[dec_tlu_ctl.scala 2685:76] + wire _T_5 = mitctl0[0] & _T_4; // @[dec_tlu_ctl.scala 2685:53] + wire _T_6 = ~io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 2685:112] + wire _T_8 = _T_6 | mitctl0[1]; // @[dec_tlu_ctl.scala 2685:138] + wire _T_9 = _T_5 & _T_8; // @[dec_tlu_ctl.scala 2685:109] + wire _T_10 = ~io_internal_dbg_halt_timers; // @[dec_tlu_ctl.scala 2685:173] + wire mitcnt0_inc_ok = _T_9 & _T_10; // @[dec_tlu_ctl.scala 2685:171] + wire [31:0] mitcnt0_inc = mitcnt0 + 32'h1; // @[dec_tlu_ctl.scala 2686:35] + wire _T_15 = wr_mitcnt0_r | mitcnt0_inc_ok; // @[dec_tlu_ctl.scala 2688:59] + wire _T_19 = io_dec_csr_wraddr_r == 12'h7d5; // @[dec_tlu_ctl.scala 2695:72] + wire wr_mitcnt1_r = io_dec_csr_wen_r_mod & _T_19; // @[dec_tlu_ctl.scala 2695:49] + reg [2:0] _T_66; // @[dec_tlu_ctl.scala 2750:52] + reg mitctl1_0_b; // @[dec_tlu_ctl.scala 2749:55] + wire _T_67 = ~mitctl1_0_b; // @[dec_tlu_ctl.scala 2750:75] wire [3:0] mitctl1 = {_T_66,_T_67}; // @[Cat.scala 29:58] - wire _T_23 = _T_2 | mitctl1[2]; // @[dec_tlu_ctl.scala 2699:76] - wire _T_24 = mitctl1[0] & _T_23; // @[dec_tlu_ctl.scala 2699:53] - wire _T_27 = _T_6 | mitctl1[1]; // @[dec_tlu_ctl.scala 2699:138] - wire _T_28 = _T_24 & _T_27; // @[dec_tlu_ctl.scala 2699:109] - wire mitcnt1_inc_ok = _T_28 & _T_10; // @[dec_tlu_ctl.scala 2699:171] - wire _T_32 = ~mitctl1[3]; // @[dec_tlu_ctl.scala 2702:60] - wire _T_33 = _T_32 | mit0_match_ns; // @[dec_tlu_ctl.scala 2702:72] + wire _T_23 = _T_2 | mitctl1[2]; // @[dec_tlu_ctl.scala 2697:76] + wire _T_24 = mitctl1[0] & _T_23; // @[dec_tlu_ctl.scala 2697:53] + wire _T_27 = _T_6 | mitctl1[1]; // @[dec_tlu_ctl.scala 2697:138] + wire _T_28 = _T_24 & _T_27; // @[dec_tlu_ctl.scala 2697:109] + wire mitcnt1_inc_ok = _T_28 & _T_10; // @[dec_tlu_ctl.scala 2697:171] + wire _T_32 = ~mitctl1[3]; // @[dec_tlu_ctl.scala 2700:60] + wire _T_33 = _T_32 | mit0_match_ns; // @[dec_tlu_ctl.scala 2700:72] wire [31:0] _T_34 = {31'h0,_T_33}; // @[Cat.scala 29:58] - wire [31:0] mitcnt1_inc = mitcnt1 + _T_34; // @[dec_tlu_ctl.scala 2702:35] - wire _T_39 = wr_mitcnt1_r | mitcnt1_inc_ok; // @[dec_tlu_ctl.scala 2704:60] - wire _T_43 = io_dec_csr_wraddr_r == 12'h7d3; // @[dec_tlu_ctl.scala 2711:70] - wire _T_47 = io_dec_csr_wraddr_r == 12'h7d6; // @[dec_tlu_ctl.scala 2720:69] - wire _T_51 = io_dec_csr_wraddr_r == 12'h7d4; // @[dec_tlu_ctl.scala 2733:72] - wire wr_mitctl0_r = io_dec_csr_wen_r_mod & _T_51; // @[dec_tlu_ctl.scala 2733:49] - wire [2:0] mitctl0_ns = wr_mitctl0_r ? io_dec_csr_wrdata_r[2:0] : mitctl0; // @[dec_tlu_ctl.scala 2734:31] - wire _T_60 = io_dec_csr_wraddr_r == 12'h7d7; // @[dec_tlu_ctl.scala 2748:71] - wire wr_mitctl1_r = io_dec_csr_wen_r_mod & _T_60; // @[dec_tlu_ctl.scala 2748:49] - wire [3:0] mitctl1_ns = wr_mitctl1_r ? io_dec_csr_wrdata_r[3:0] : mitctl1; // @[dec_tlu_ctl.scala 2749:31] - wire _T_69 = io_csr_mitcnt1 | io_csr_mitcnt0; // @[dec_tlu_ctl.scala 2754:51] - wire _T_70 = _T_69 | io_csr_mitb1; // @[dec_tlu_ctl.scala 2754:68] - wire _T_71 = _T_70 | io_csr_mitb0; // @[dec_tlu_ctl.scala 2754:83] - wire _T_72 = _T_71 | io_csr_mitctl0; // @[dec_tlu_ctl.scala 2754:98] + wire [31:0] mitcnt1_inc = mitcnt1 + _T_34; // @[dec_tlu_ctl.scala 2700:35] + wire _T_39 = wr_mitcnt1_r | mitcnt1_inc_ok; // @[dec_tlu_ctl.scala 2702:60] + wire _T_43 = io_dec_csr_wraddr_r == 12'h7d3; // @[dec_tlu_ctl.scala 2709:70] + wire _T_47 = io_dec_csr_wraddr_r == 12'h7d6; // @[dec_tlu_ctl.scala 2718:69] + wire _T_51 = io_dec_csr_wraddr_r == 12'h7d4; // @[dec_tlu_ctl.scala 2731:72] + wire wr_mitctl0_r = io_dec_csr_wen_r_mod & _T_51; // @[dec_tlu_ctl.scala 2731:49] + wire [2:0] mitctl0_ns = wr_mitctl0_r ? io_dec_csr_wrdata_r[2:0] : mitctl0; // @[dec_tlu_ctl.scala 2732:31] + wire _T_60 = io_dec_csr_wraddr_r == 12'h7d7; // @[dec_tlu_ctl.scala 2746:71] + wire wr_mitctl1_r = io_dec_csr_wen_r_mod & _T_60; // @[dec_tlu_ctl.scala 2746:49] + wire [3:0] mitctl1_ns = wr_mitctl1_r ? io_dec_csr_wrdata_r[3:0] : mitctl1; // @[dec_tlu_ctl.scala 2747:31] + wire _T_69 = io_csr_mitcnt1 | io_csr_mitcnt0; // @[dec_tlu_ctl.scala 2752:51] + wire _T_70 = _T_69 | io_csr_mitb1; // @[dec_tlu_ctl.scala 2752:68] + wire _T_71 = _T_70 | io_csr_mitb0; // @[dec_tlu_ctl.scala 2752:83] + wire _T_72 = _T_71 | io_csr_mitctl0; // @[dec_tlu_ctl.scala 2752:98] wire [31:0] _T_81 = {29'h0,_T_57,_T_58}; // @[Cat.scala 29:58] wire [31:0] _T_84 = {28'h0,_T_66,_T_67}; // @[Cat.scala 29:58] wire [31:0] _T_85 = io_csr_mitcnt0 ? mitcnt0 : 32'h0; // @[Mux.scala 27:72] @@ -50268,10 +50275,10 @@ module dec_timer_ctl( .io_en(rvclkhdr_3_io_en), .io_scan_mode(rvclkhdr_3_io_scan_mode) ); - assign io_dec_timer_rddata_d = _T_94 | _T_90; // @[dec_tlu_ctl.scala 2755:33] - assign io_dec_timer_read_d = _T_72 | io_csr_mitctl1; // @[dec_tlu_ctl.scala 2754:33] - assign io_dec_timer_t0_pulse = mitcnt0 >= mitb0; // @[dec_tlu_ctl.scala 2677:31] - assign io_dec_timer_t1_pulse = mitcnt1 >= mitb1; // @[dec_tlu_ctl.scala 2678:31] + assign io_dec_timer_rddata_d = _T_94 | _T_90; // @[dec_tlu_ctl.scala 2753:33] + assign io_dec_timer_read_d = _T_72 | io_csr_mitctl1; // @[dec_tlu_ctl.scala 2752:33] + assign io_dec_timer_t0_pulse = mitcnt0 >= mitb0; // @[dec_tlu_ctl.scala 2675:31] + assign io_dec_timer_t1_pulse = mitcnt1 >= mitb1; // @[dec_tlu_ctl.scala 2676:31] assign rvclkhdr_io_clk = clock; // @[lib.scala 370:18] assign rvclkhdr_io_en = _T_15 | mit0_match_ns; // @[lib.scala 371:17] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] @@ -50517,7 +50524,6 @@ module csr_tlu( output io_dec_tlu_misc_clk_override, output io_dec_tlu_dec_clk_override, output io_dec_tlu_lsu_clk_override, - output io_dec_tlu_bus_clk_override, output io_dec_tlu_pic_clk_override, output io_dec_tlu_dccm_clk_override, output io_dec_tlu_icm_clk_override, @@ -50540,6 +50546,7 @@ module csr_tlu( input io_lsu_imprecise_error_load_any, input io_lsu_imprecise_error_store_any, output [31:0] io_dec_tlu_mrac_ff, + output io_dec_tlu_wb_coalescing_disable, output io_dec_tlu_bpred_disable, output io_dec_tlu_sideeffect_posted_disable, output io_dec_tlu_core_ecc_disable, @@ -50919,36 +50926,36 @@ module csr_tlu( wire rvclkhdr_34_io_clk; // @[lib.scala 343:22] wire rvclkhdr_34_io_en; // @[lib.scala 343:22] wire rvclkhdr_34_io_scan_mode; // @[lib.scala 343:22] - wire _T = ~io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 1451:45] - wire _T_1 = io_dec_csr_wen_r & _T; // @[dec_tlu_ctl.scala 1451:43] - wire _T_2 = ~io_rfpc_i0_r; // @[dec_tlu_ctl.scala 1451:68] - wire _T_5 = io_dec_csr_wraddr_r == 12'h300; // @[dec_tlu_ctl.scala 1452:71] - wire wr_mstatus_r = io_dec_csr_wen_r_mod & _T_5; // @[dec_tlu_ctl.scala 1452:42] - wire _T_488 = io_dec_csr_wraddr_r == 12'h7c6; // @[dec_tlu_ctl.scala 1838:68] - wire wr_mpmc_r = io_dec_csr_wen_r_mod & _T_488; // @[dec_tlu_ctl.scala 1838:39] - wire _T_500 = ~io_dec_csr_wrdata_r[1]; // @[dec_tlu_ctl.scala 1846:37] - reg mpmc_b; // @[dec_tlu_ctl.scala 1848:44] - wire mpmc = ~mpmc_b; // @[dec_tlu_ctl.scala 1851:10] - wire _T_501 = ~mpmc; // @[dec_tlu_ctl.scala 1846:62] - wire mpmc_b_ns = wr_mpmc_r ? _T_500 : _T_501; // @[dec_tlu_ctl.scala 1846:18] - wire _T_6 = ~mpmc_b_ns; // @[dec_tlu_ctl.scala 1455:28] - wire set_mie_pmu_fw_halt = _T_6 & io_fw_halt_req; // @[dec_tlu_ctl.scala 1455:39] - wire _T_7 = ~wr_mstatus_r; // @[dec_tlu_ctl.scala 1458:5] - wire _T_8 = _T_7 & io_exc_or_int_valid_r; // @[dec_tlu_ctl.scala 1458:19] + wire _T = ~io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 1449:45] + wire _T_1 = io_dec_csr_wen_r & _T; // @[dec_tlu_ctl.scala 1449:43] + wire _T_2 = ~io_rfpc_i0_r; // @[dec_tlu_ctl.scala 1449:68] + wire _T_5 = io_dec_csr_wraddr_r == 12'h300; // @[dec_tlu_ctl.scala 1450:71] + wire wr_mstatus_r = io_dec_csr_wen_r_mod & _T_5; // @[dec_tlu_ctl.scala 1450:42] + wire _T_498 = io_dec_csr_wraddr_r == 12'h7c6; // @[dec_tlu_ctl.scala 1836:68] + wire wr_mpmc_r = io_dec_csr_wen_r_mod & _T_498; // @[dec_tlu_ctl.scala 1836:39] + wire _T_510 = ~io_dec_csr_wrdata_r[1]; // @[dec_tlu_ctl.scala 1844:37] + reg mpmc_b; // @[dec_tlu_ctl.scala 1846:44] + wire mpmc = ~mpmc_b; // @[dec_tlu_ctl.scala 1849:10] + wire _T_511 = ~mpmc; // @[dec_tlu_ctl.scala 1844:62] + wire mpmc_b_ns = wr_mpmc_r ? _T_510 : _T_511; // @[dec_tlu_ctl.scala 1844:18] + wire _T_6 = ~mpmc_b_ns; // @[dec_tlu_ctl.scala 1453:28] + wire set_mie_pmu_fw_halt = _T_6 & io_fw_halt_req; // @[dec_tlu_ctl.scala 1453:39] + wire _T_7 = ~wr_mstatus_r; // @[dec_tlu_ctl.scala 1456:5] + wire _T_8 = _T_7 & io_exc_or_int_valid_r; // @[dec_tlu_ctl.scala 1456:19] wire [1:0] _T_12 = {io_mstatus[0],1'h0}; // @[Cat.scala 29:58] - wire _T_13 = wr_mstatus_r & io_exc_or_int_valid_r; // @[dec_tlu_ctl.scala 1459:18] + wire _T_13 = wr_mstatus_r & io_exc_or_int_valid_r; // @[dec_tlu_ctl.scala 1457:18] wire [1:0] _T_16 = {io_dec_csr_wrdata_r[3],1'h0}; // @[Cat.scala 29:58] - wire _T_17 = ~io_exc_or_int_valid_r; // @[dec_tlu_ctl.scala 1460:17] - wire _T_18 = io_mret_r & _T_17; // @[dec_tlu_ctl.scala 1460:15] + wire _T_17 = ~io_exc_or_int_valid_r; // @[dec_tlu_ctl.scala 1458:17] + wire _T_18 = io_mret_r & _T_17; // @[dec_tlu_ctl.scala 1458:15] wire [1:0] _T_21 = {1'h1,io_mstatus[1]}; // @[Cat.scala 29:58] wire [1:0] _T_24 = {io_mstatus[1],1'h1}; // @[Cat.scala 29:58] - wire _T_26 = wr_mstatus_r & _T_17; // @[dec_tlu_ctl.scala 1462:18] + wire _T_26 = wr_mstatus_r & _T_17; // @[dec_tlu_ctl.scala 1460:18] wire [1:0] _T_30 = {io_dec_csr_wrdata_r[7],io_dec_csr_wrdata_r[3]}; // @[Cat.scala 29:58] - wire _T_33 = _T_7 & _T_17; // @[dec_tlu_ctl.scala 1463:19] - wire _T_34 = ~io_mret_r; // @[dec_tlu_ctl.scala 1463:46] - wire _T_35 = _T_33 & _T_34; // @[dec_tlu_ctl.scala 1463:44] - wire _T_36 = ~set_mie_pmu_fw_halt; // @[dec_tlu_ctl.scala 1463:59] - wire _T_37 = _T_35 & _T_36; // @[dec_tlu_ctl.scala 1463:57] + wire _T_33 = _T_7 & _T_17; // @[dec_tlu_ctl.scala 1461:19] + wire _T_34 = ~io_mret_r; // @[dec_tlu_ctl.scala 1461:46] + wire _T_35 = _T_33 & _T_34; // @[dec_tlu_ctl.scala 1461:44] + wire _T_36 = ~set_mie_pmu_fw_halt; // @[dec_tlu_ctl.scala 1461:59] + wire _T_37 = _T_35 & _T_36; // @[dec_tlu_ctl.scala 1461:57] wire [1:0] _T_39 = _T_8 ? _T_12 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_40 = _T_13 ? _T_16 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_41 = _T_18 ? _T_21 : 2'h0; // @[Mux.scala 27:72] @@ -50959,155 +50966,155 @@ module csr_tlu( wire [1:0] _T_46 = _T_45 | _T_41; // @[Mux.scala 27:72] wire [1:0] _T_47 = _T_46 | _T_42; // @[Mux.scala 27:72] wire [1:0] _T_48 = _T_47 | _T_43; // @[Mux.scala 27:72] - wire _T_52 = ~io_dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 1466:50] - wire _T_54 = _T_52 | io_dcsr[11]; // @[dec_tlu_ctl.scala 1466:81] - reg [1:0] _T_56; // @[dec_tlu_ctl.scala 1468:11] - wire _T_58 = io_dec_csr_wraddr_r == 12'h305; // @[dec_tlu_ctl.scala 1477:69] + wire _T_52 = ~io_dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 1464:50] + wire _T_54 = _T_52 | io_dcsr[11]; // @[dec_tlu_ctl.scala 1464:81] + reg [1:0] _T_56; // @[dec_tlu_ctl.scala 1466:11] + wire _T_58 = io_dec_csr_wraddr_r == 12'h305; // @[dec_tlu_ctl.scala 1475:69] reg [30:0] _T_62; // @[lib.scala 374:16] reg [31:0] mdccmect; // @[lib.scala 374:16] - wire [62:0] _T_564 = 63'hffffffff << mdccmect[31:27]; // @[dec_tlu_ctl.scala 1898:41] - wire [31:0] _T_566 = {5'h0,mdccmect[26:0]}; // @[Cat.scala 29:58] - wire [62:0] _GEN_9 = {{31'd0}, _T_566}; // @[dec_tlu_ctl.scala 1898:61] - wire [62:0] _T_567 = _T_564 & _GEN_9; // @[dec_tlu_ctl.scala 1898:61] - wire mdccme_ce_req = |_T_567; // @[dec_tlu_ctl.scala 1898:94] + wire [62:0] _T_574 = 63'hffffffff << mdccmect[31:27]; // @[dec_tlu_ctl.scala 1896:41] + wire [31:0] _T_576 = {5'h0,mdccmect[26:0]}; // @[Cat.scala 29:58] + wire [62:0] _GEN_9 = {{31'd0}, _T_576}; // @[dec_tlu_ctl.scala 1896:61] + wire [62:0] _T_577 = _T_574 & _GEN_9; // @[dec_tlu_ctl.scala 1896:61] + wire mdccme_ce_req = |_T_577; // @[dec_tlu_ctl.scala 1896:94] reg [31:0] miccmect; // @[lib.scala 374:16] - wire [62:0] _T_544 = 63'hffffffff << miccmect[31:27]; // @[dec_tlu_ctl.scala 1883:40] - wire [31:0] _T_546 = {5'h0,miccmect[26:0]}; // @[Cat.scala 29:58] - wire [62:0] _GEN_10 = {{31'd0}, _T_546}; // @[dec_tlu_ctl.scala 1883:60] - wire [62:0] _T_547 = _T_544 & _GEN_10; // @[dec_tlu_ctl.scala 1883:60] - wire miccme_ce_req = |_T_547; // @[dec_tlu_ctl.scala 1883:93] - wire _T_63 = mdccme_ce_req | miccme_ce_req; // @[dec_tlu_ctl.scala 1491:30] + wire [62:0] _T_554 = 63'hffffffff << miccmect[31:27]; // @[dec_tlu_ctl.scala 1881:40] + wire [31:0] _T_556 = {5'h0,miccmect[26:0]}; // @[Cat.scala 29:58] + wire [62:0] _GEN_10 = {{31'd0}, _T_556}; // @[dec_tlu_ctl.scala 1881:60] + wire [62:0] _T_557 = _T_554 & _GEN_10; // @[dec_tlu_ctl.scala 1881:60] + wire miccme_ce_req = |_T_557; // @[dec_tlu_ctl.scala 1881:93] + wire _T_63 = mdccme_ce_req | miccme_ce_req; // @[dec_tlu_ctl.scala 1489:30] reg [31:0] micect; // @[lib.scala 374:16] - wire [62:0] _T_522 = 63'hffffffff << micect[31:27]; // @[dec_tlu_ctl.scala 1868:39] - wire [31:0] _T_524 = {5'h0,micect[26:0]}; // @[Cat.scala 29:58] - wire [62:0] _GEN_11 = {{31'd0}, _T_524}; // @[dec_tlu_ctl.scala 1868:57] - wire [62:0] _T_525 = _T_522 & _GEN_11; // @[dec_tlu_ctl.scala 1868:57] - wire mice_ce_req = |_T_525; // @[dec_tlu_ctl.scala 1868:88] - wire ce_int = _T_63 | mice_ce_req; // @[dec_tlu_ctl.scala 1491:46] + wire [62:0] _T_532 = 63'hffffffff << micect[31:27]; // @[dec_tlu_ctl.scala 1866:39] + wire [31:0] _T_534 = {5'h0,micect[26:0]}; // @[Cat.scala 29:58] + wire [62:0] _GEN_11 = {{31'd0}, _T_534}; // @[dec_tlu_ctl.scala 1866:57] + wire [62:0] _T_535 = _T_532 & _GEN_11; // @[dec_tlu_ctl.scala 1866:57] + wire mice_ce_req = |_T_535; // @[dec_tlu_ctl.scala 1866:88] + wire ce_int = _T_63 | mice_ce_req; // @[dec_tlu_ctl.scala 1489:46] wire [2:0] _T_65 = {io_mexintpend,io_timer_int_sync,io_soft_int_sync}; // @[Cat.scala 29:58] wire [2:0] _T_67 = {ce_int,io_dec_timer_t0_pulse,io_dec_timer_t1_pulse}; // @[Cat.scala 29:58] - reg [5:0] _T_68; // @[dec_tlu_ctl.scala 1495:11] - wire _T_70 = io_dec_csr_wraddr_r == 12'h304; // @[dec_tlu_ctl.scala 1507:67] - wire wr_mie_r = io_dec_csr_wen_r_mod & _T_70; // @[dec_tlu_ctl.scala 1507:38] + reg [5:0] _T_68; // @[dec_tlu_ctl.scala 1493:11] + wire _T_70 = io_dec_csr_wraddr_r == 12'h304; // @[dec_tlu_ctl.scala 1505:67] + wire wr_mie_r = io_dec_csr_wen_r_mod & _T_70; // @[dec_tlu_ctl.scala 1505:38] wire [5:0] _T_78 = {io_dec_csr_wrdata_r[30:28],io_dec_csr_wrdata_r[11],io_dec_csr_wrdata_r[7],io_dec_csr_wrdata_r[3]}; // @[Cat.scala 29:58] - reg [5:0] mie; // @[dec_tlu_ctl.scala 1510:11] - wire kill_ebreak_count_r = io_ebreak_to_debug_mode_r & io_dcsr[10]; // @[dec_tlu_ctl.scala 1517:54] - wire _T_83 = io_dec_csr_wraddr_r == 12'hb00; // @[dec_tlu_ctl.scala 1519:71] - wire wr_mcyclel_r = io_dec_csr_wen_r_mod & _T_83; // @[dec_tlu_ctl.scala 1519:42] - wire _T_85 = io_dec_tlu_dbg_halted & io_dcsr[10]; // @[dec_tlu_ctl.scala 1521:71] - wire _T_86 = kill_ebreak_count_r | _T_85; // @[dec_tlu_ctl.scala 1521:46] - wire _T_87 = _T_86 | io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 1521:94] + reg [5:0] mie; // @[dec_tlu_ctl.scala 1508:11] + wire kill_ebreak_count_r = io_ebreak_to_debug_mode_r & io_dcsr[10]; // @[dec_tlu_ctl.scala 1515:54] + wire _T_83 = io_dec_csr_wraddr_r == 12'hb00; // @[dec_tlu_ctl.scala 1517:71] + wire wr_mcyclel_r = io_dec_csr_wen_r_mod & _T_83; // @[dec_tlu_ctl.scala 1517:42] + wire _T_85 = io_dec_tlu_dbg_halted & io_dcsr[10]; // @[dec_tlu_ctl.scala 1519:71] + wire _T_86 = kill_ebreak_count_r | _T_85; // @[dec_tlu_ctl.scala 1519:46] + wire _T_87 = _T_86 | io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 1519:94] reg [4:0] temp_ncount6_2; // @[Reg.scala 27:20] reg temp_ncount0; // @[Reg.scala 27:20] wire [6:0] mcountinhibit = {temp_ncount6_2,1'h0,temp_ncount0}; // @[Cat.scala 29:58] - wire _T_89 = _T_87 | mcountinhibit[0]; // @[dec_tlu_ctl.scala 1521:121] - wire mcyclel_cout_in = ~_T_89; // @[dec_tlu_ctl.scala 1521:24] + wire _T_89 = _T_87 | mcountinhibit[0]; // @[dec_tlu_ctl.scala 1519:121] + wire mcyclel_cout_in = ~_T_89; // @[dec_tlu_ctl.scala 1519:24] wire [31:0] _T_90 = {31'h0,mcyclel_cout_in}; // @[Cat.scala 29:58] reg [31:0] mcyclel; // @[lib.scala 374:16] - wire [32:0] mcyclel_inc = mcyclel + _T_90; // @[dec_tlu_ctl.scala 1525:25] - wire mcyclel_cout = mcyclel_inc[32]; // @[dec_tlu_ctl.scala 1527:32] - wire _T_101 = io_dec_csr_wraddr_r == 12'hb80; // @[dec_tlu_ctl.scala 1535:68] - wire wr_mcycleh_r = io_dec_csr_wen_r_mod & _T_101; // @[dec_tlu_ctl.scala 1535:39] - wire _T_98 = ~wr_mcycleh_r; // @[dec_tlu_ctl.scala 1529:71] - reg mcyclel_cout_f; // @[dec_tlu_ctl.scala 1529:54] + wire [32:0] mcyclel_inc = mcyclel + _T_90; // @[dec_tlu_ctl.scala 1523:25] + wire mcyclel_cout = mcyclel_inc[32]; // @[dec_tlu_ctl.scala 1525:32] + wire _T_101 = io_dec_csr_wraddr_r == 12'hb80; // @[dec_tlu_ctl.scala 1533:68] + wire wr_mcycleh_r = io_dec_csr_wen_r_mod & _T_101; // @[dec_tlu_ctl.scala 1533:39] + wire _T_98 = ~wr_mcycleh_r; // @[dec_tlu_ctl.scala 1527:71] + reg mcyclel_cout_f; // @[dec_tlu_ctl.scala 1527:54] wire [31:0] _T_103 = {31'h0,mcyclel_cout_f}; // @[Cat.scala 29:58] reg [31:0] mcycleh; // @[lib.scala 374:16] - wire [31:0] mcycleh_inc = mcycleh + _T_103; // @[dec_tlu_ctl.scala 1537:28] - wire _T_109 = io_ebreak_r | io_ecall_r; // @[dec_tlu_ctl.scala 1554:72] - wire _T_110 = _T_109 | io_ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 1554:85] - wire _T_111 = _T_110 | io_illegal_r; // @[dec_tlu_ctl.scala 1554:113] - wire _T_113 = _T_111 | mcountinhibit[2]; // @[dec_tlu_ctl.scala 1554:128] - wire _T_115 = ~_T_113; // @[dec_tlu_ctl.scala 1554:58] - wire i0_valid_no_ebreak_ecall_r = io_tlu_i0_commit_cmt & _T_115; // @[dec_tlu_ctl.scala 1554:56] - wire _T_117 = io_dec_csr_wraddr_r == 12'hb02; // @[dec_tlu_ctl.scala 1556:73] - wire wr_minstretl_r = io_dec_csr_wen_r_mod & _T_117; // @[dec_tlu_ctl.scala 1556:44] + wire [31:0] mcycleh_inc = mcycleh + _T_103; // @[dec_tlu_ctl.scala 1535:28] + wire _T_109 = io_ebreak_r | io_ecall_r; // @[dec_tlu_ctl.scala 1552:72] + wire _T_110 = _T_109 | io_ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 1552:85] + wire _T_111 = _T_110 | io_illegal_r; // @[dec_tlu_ctl.scala 1552:113] + wire _T_113 = _T_111 | mcountinhibit[2]; // @[dec_tlu_ctl.scala 1552:128] + wire _T_115 = ~_T_113; // @[dec_tlu_ctl.scala 1552:58] + wire i0_valid_no_ebreak_ecall_r = io_tlu_i0_commit_cmt & _T_115; // @[dec_tlu_ctl.scala 1552:56] + wire _T_117 = io_dec_csr_wraddr_r == 12'hb02; // @[dec_tlu_ctl.scala 1554:73] + wire wr_minstretl_r = io_dec_csr_wen_r_mod & _T_117; // @[dec_tlu_ctl.scala 1554:44] wire [31:0] _T_118 = {31'h0,i0_valid_no_ebreak_ecall_r}; // @[Cat.scala 29:58] reg [31:0] minstretl; // @[lib.scala 374:16] - wire [32:0] minstretl_inc = minstretl + _T_118; // @[dec_tlu_ctl.scala 1558:29] - wire minstretl_cout = minstretl_inc[32]; // @[dec_tlu_ctl.scala 1559:36] - reg minstret_enable_f; // @[dec_tlu_ctl.scala 1564:56] - wire _T_128 = io_dec_csr_wraddr_r == 12'hb82; // @[dec_tlu_ctl.scala 1573:71] - wire wr_minstreth_r = io_dec_csr_wen_r_mod & _T_128; // @[dec_tlu_ctl.scala 1573:42] - wire _T_125 = ~wr_minstreth_r; // @[dec_tlu_ctl.scala 1565:75] - reg minstretl_cout_f; // @[dec_tlu_ctl.scala 1565:56] + wire [32:0] minstretl_inc = minstretl + _T_118; // @[dec_tlu_ctl.scala 1556:29] + wire minstretl_cout = minstretl_inc[32]; // @[dec_tlu_ctl.scala 1557:36] + reg minstret_enable_f; // @[dec_tlu_ctl.scala 1562:56] + wire _T_128 = io_dec_csr_wraddr_r == 12'hb82; // @[dec_tlu_ctl.scala 1571:71] + wire wr_minstreth_r = io_dec_csr_wen_r_mod & _T_128; // @[dec_tlu_ctl.scala 1571:42] + wire _T_125 = ~wr_minstreth_r; // @[dec_tlu_ctl.scala 1563:75] + reg minstretl_cout_f; // @[dec_tlu_ctl.scala 1563:56] wire [31:0] _T_131 = {31'h0,minstretl_cout_f}; // @[Cat.scala 29:58] reg [31:0] minstreth; // @[lib.scala 374:16] - wire [31:0] minstreth_inc = minstreth + _T_131; // @[dec_tlu_ctl.scala 1576:29] - wire _T_139 = io_dec_csr_wraddr_r == 12'h340; // @[dec_tlu_ctl.scala 1587:72] + wire [31:0] minstreth_inc = minstreth + _T_131; // @[dec_tlu_ctl.scala 1574:29] + wire _T_139 = io_dec_csr_wraddr_r == 12'h340; // @[dec_tlu_ctl.scala 1585:72] reg [31:0] mscratch; // @[lib.scala 374:16] - wire _T_142 = ~io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 1598:22] - wire _T_143 = ~io_tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 1598:47] - wire _T_144 = _T_142 & _T_143; // @[dec_tlu_ctl.scala 1598:45] - wire sel_exu_npc_r = _T_144 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 1598:72] - wire _T_146 = _T_142 & io_tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 1599:47] - wire _T_147 = ~io_dec_tlu_flush_noredir_r_d1; // @[dec_tlu_ctl.scala 1599:75] - wire sel_flush_npc_r = _T_146 & _T_147; // @[dec_tlu_ctl.scala 1599:73] - wire _T_148 = ~sel_exu_npc_r; // @[dec_tlu_ctl.scala 1600:23] - wire _T_149 = ~sel_flush_npc_r; // @[dec_tlu_ctl.scala 1600:40] - wire sel_hold_npc_r = _T_148 & _T_149; // @[dec_tlu_ctl.scala 1600:38] - wire _T_151 = ~io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 1604:13] - wire _T_152 = _T_151 & io_reset_delayed; // @[dec_tlu_ctl.scala 1604:35] + wire _T_142 = ~io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 1596:22] + wire _T_143 = ~io_tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 1596:47] + wire _T_144 = _T_142 & _T_143; // @[dec_tlu_ctl.scala 1596:45] + wire sel_exu_npc_r = _T_144 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 1596:72] + wire _T_146 = _T_142 & io_tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 1597:47] + wire _T_147 = ~io_dec_tlu_flush_noredir_r_d1; // @[dec_tlu_ctl.scala 1597:75] + wire sel_flush_npc_r = _T_146 & _T_147; // @[dec_tlu_ctl.scala 1597:73] + wire _T_148 = ~sel_exu_npc_r; // @[dec_tlu_ctl.scala 1598:23] + wire _T_149 = ~sel_flush_npc_r; // @[dec_tlu_ctl.scala 1598:40] + wire sel_hold_npc_r = _T_148 & _T_149; // @[dec_tlu_ctl.scala 1598:38] + wire _T_151 = ~io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 1602:13] + wire _T_152 = _T_151 & io_reset_delayed; // @[dec_tlu_ctl.scala 1602:35] wire [30:0] _T_156 = sel_exu_npc_r ? io_exu_npc_r : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_157 = _T_152 ? io_rst_vec : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_158 = sel_flush_npc_r ? io_tlu_flush_path_r_d1 : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_159 = sel_hold_npc_r ? io_npc_r_d1 : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_160 = _T_156 | _T_157; // @[Mux.scala 27:72] wire [30:0] _T_161 = _T_160 | _T_158; // @[Mux.scala 27:72] - wire _T_164 = sel_exu_npc_r | sel_flush_npc_r; // @[dec_tlu_ctl.scala 1608:48] + wire _T_164 = sel_exu_npc_r | sel_flush_npc_r; // @[dec_tlu_ctl.scala 1606:48] reg [30:0] _T_167; // @[lib.scala 374:16] - wire pc0_valid_r = _T_142 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 1611:44] - wire _T_170 = ~pc0_valid_r; // @[dec_tlu_ctl.scala 1615:22] + wire pc0_valid_r = _T_142 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 1609:44] + wire _T_170 = ~pc0_valid_r; // @[dec_tlu_ctl.scala 1613:22] wire [30:0] _T_171 = pc0_valid_r ? io_dec_tlu_i0_pc_r : 31'h0; // @[Mux.scala 27:72] reg [30:0] pc_r_d1; // @[lib.scala 374:16] wire [30:0] _T_172 = _T_170 ? pc_r_d1 : 31'h0; // @[Mux.scala 27:72] wire [30:0] pc_r = _T_171 | _T_172; // @[Mux.scala 27:72] - wire _T_176 = io_dec_csr_wraddr_r == 12'h341; // @[dec_tlu_ctl.scala 1619:68] - wire wr_mepc_r = io_dec_csr_wen_r_mod & _T_176; // @[dec_tlu_ctl.scala 1619:39] - wire _T_177 = io_i0_exception_valid_r | io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 1622:27] - wire _T_178 = _T_177 | io_mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 1622:48] - wire _T_182 = wr_mepc_r & _T_17; // @[dec_tlu_ctl.scala 1624:13] - wire _T_185 = ~wr_mepc_r; // @[dec_tlu_ctl.scala 1625:3] - wire _T_187 = _T_185 & _T_17; // @[dec_tlu_ctl.scala 1625:14] + wire _T_176 = io_dec_csr_wraddr_r == 12'h341; // @[dec_tlu_ctl.scala 1617:68] + wire wr_mepc_r = io_dec_csr_wen_r_mod & _T_176; // @[dec_tlu_ctl.scala 1617:39] + wire _T_177 = io_i0_exception_valid_r | io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 1620:27] + wire _T_178 = _T_177 | io_mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 1620:48] + wire _T_182 = wr_mepc_r & _T_17; // @[dec_tlu_ctl.scala 1622:13] + wire _T_185 = ~wr_mepc_r; // @[dec_tlu_ctl.scala 1623:3] + wire _T_187 = _T_185 & _T_17; // @[dec_tlu_ctl.scala 1623:14] wire [30:0] _T_189 = _T_178 ? pc_r : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_190 = io_interrupt_valid_r ? io_npc_r : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_191 = _T_182 ? io_dec_csr_wrdata_r[31:1] : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_192 = _T_187 ? io_mepc : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_193 = _T_189 | _T_190; // @[Mux.scala 27:72] wire [30:0] _T_194 = _T_193 | _T_191; // @[Mux.scala 27:72] - reg [30:0] _T_196; // @[dec_tlu_ctl.scala 1627:47] - wire _T_198 = io_dec_csr_wraddr_r == 12'h342; // @[dec_tlu_ctl.scala 1634:72] - wire wr_mcause_r = io_dec_csr_wen_r_mod & _T_198; // @[dec_tlu_ctl.scala 1634:43] - wire _T_199 = io_exc_or_int_valid_r & io_take_nmi; // @[dec_tlu_ctl.scala 1635:53] - wire mcause_sel_nmi_store = _T_199 & io_nmi_lsu_store_type; // @[dec_tlu_ctl.scala 1635:67] - wire mcause_sel_nmi_load = _T_199 & io_nmi_lsu_load_type; // @[dec_tlu_ctl.scala 1636:66] - wire _T_202 = |io_lsu_fir_error; // @[dec_tlu_ctl.scala 1637:84] - wire mcause_sel_nmi_ext = _T_199 & _T_202; // @[dec_tlu_ctl.scala 1637:65] - wire _T_203 = &io_lsu_fir_error; // @[dec_tlu_ctl.scala 1643:53] - wire _T_206 = ~io_lsu_fir_error[0]; // @[dec_tlu_ctl.scala 1643:82] - wire _T_207 = io_lsu_fir_error[1] & _T_206; // @[dec_tlu_ctl.scala 1643:80] + reg [30:0] _T_196; // @[dec_tlu_ctl.scala 1625:47] + wire _T_198 = io_dec_csr_wraddr_r == 12'h342; // @[dec_tlu_ctl.scala 1632:72] + wire wr_mcause_r = io_dec_csr_wen_r_mod & _T_198; // @[dec_tlu_ctl.scala 1632:43] + wire _T_199 = io_exc_or_int_valid_r & io_take_nmi; // @[dec_tlu_ctl.scala 1633:53] + wire mcause_sel_nmi_store = _T_199 & io_nmi_lsu_store_type; // @[dec_tlu_ctl.scala 1633:67] + wire mcause_sel_nmi_load = _T_199 & io_nmi_lsu_load_type; // @[dec_tlu_ctl.scala 1634:66] + wire _T_202 = |io_lsu_fir_error; // @[dec_tlu_ctl.scala 1635:84] + wire mcause_sel_nmi_ext = _T_199 & _T_202; // @[dec_tlu_ctl.scala 1635:65] + wire _T_203 = &io_lsu_fir_error; // @[dec_tlu_ctl.scala 1641:53] + wire _T_206 = ~io_lsu_fir_error[0]; // @[dec_tlu_ctl.scala 1641:82] + wire _T_207 = io_lsu_fir_error[1] & _T_206; // @[dec_tlu_ctl.scala 1641:80] wire [31:0] _T_212 = {30'h3c000400,_T_203,_T_207}; // @[Cat.scala 29:58] - wire _T_213 = ~io_take_nmi; // @[dec_tlu_ctl.scala 1649:56] - wire _T_214 = io_exc_or_int_valid_r & _T_213; // @[dec_tlu_ctl.scala 1649:54] + wire _T_213 = ~io_take_nmi; // @[dec_tlu_ctl.scala 1647:56] + wire _T_214 = io_exc_or_int_valid_r & _T_213; // @[dec_tlu_ctl.scala 1647:54] wire [31:0] _T_217 = {io_interrupt_valid_r,26'h0,io_exc_cause_r}; // @[Cat.scala 29:58] - wire _T_219 = wr_mcause_r & _T_17; // @[dec_tlu_ctl.scala 1650:44] - wire _T_221 = ~wr_mcause_r; // @[dec_tlu_ctl.scala 1651:32] - wire _T_223 = _T_221 & _T_17; // @[dec_tlu_ctl.scala 1651:45] + wire _T_219 = wr_mcause_r & _T_17; // @[dec_tlu_ctl.scala 1648:44] + wire _T_221 = ~wr_mcause_r; // @[dec_tlu_ctl.scala 1649:32] + wire _T_223 = _T_221 & _T_17; // @[dec_tlu_ctl.scala 1649:45] wire [31:0] _T_225 = mcause_sel_nmi_store ? 32'hf0000000 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_226 = mcause_sel_nmi_load ? 32'hf0000001 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_227 = mcause_sel_nmi_ext ? _T_212 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_228 = _T_214 ? _T_217 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_229 = _T_219 ? io_dec_csr_wrdata_r : 32'h0; // @[Mux.scala 27:72] - reg [31:0] mcause; // @[dec_tlu_ctl.scala 1653:49] + reg [31:0] mcause; // @[dec_tlu_ctl.scala 1651:49] wire [31:0] _T_230 = _T_223 ? mcause : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_231 = _T_225 | _T_226; // @[Mux.scala 27:72] wire [31:0] _T_232 = _T_231 | _T_227; // @[Mux.scala 27:72] wire [31:0] _T_233 = _T_232 | _T_228; // @[Mux.scala 27:72] wire [31:0] _T_234 = _T_233 | _T_229; // @[Mux.scala 27:72] - wire _T_238 = io_dec_csr_wraddr_r == 12'h7ff; // @[dec_tlu_ctl.scala 1660:71] - wire wr_mscause_r = io_dec_csr_wen_r_mod & _T_238; // @[dec_tlu_ctl.scala 1660:42] - wire _T_239 = io_dec_tlu_packet_r_icaf_type == 2'h0; // @[dec_tlu_ctl.scala 1662:56] + wire _T_238 = io_dec_csr_wraddr_r == 12'h7ff; // @[dec_tlu_ctl.scala 1658:71] + wire wr_mscause_r = io_dec_csr_wen_r_mod & _T_238; // @[dec_tlu_ctl.scala 1658:42] + wire _T_239 = io_dec_tlu_packet_r_icaf_type == 2'h0; // @[dec_tlu_ctl.scala 1660:56] wire [3:0] _T_240 = {2'h0,io_dec_tlu_packet_r_icaf_type}; // @[Cat.scala 29:58] - wire [3:0] ifu_mscause = _T_239 ? 4'h9 : _T_240; // @[dec_tlu_ctl.scala 1662:24] + wire [3:0] ifu_mscause = _T_239 ? 4'h9 : _T_240; // @[dec_tlu_ctl.scala 1660:24] wire [3:0] _T_245 = io_lsu_i0_exc_r ? io_lsu_error_pkt_r_bits_mscause : 4'h0; // @[Mux.scala 27:72] wire [1:0] _T_247 = io_ebreak_r ? 2'h2 : 2'h0; // @[Mux.scala 27:72] wire [3:0] _T_248 = io_inst_acc_r ? ifu_mscause : 4'h0; // @[Mux.scala 27:72] @@ -51116,487 +51123,481 @@ module csr_tlu( wire [3:0] _GEN_13 = {{2'd0}, _T_247}; // @[Mux.scala 27:72] wire [3:0] _T_250 = _T_249 | _GEN_13; // @[Mux.scala 27:72] wire [3:0] mscause_type = _T_250 | _T_248; // @[Mux.scala 27:72] - wire _T_254 = wr_mscause_r & _T_17; // @[dec_tlu_ctl.scala 1673:38] - wire _T_257 = ~wr_mscause_r; // @[dec_tlu_ctl.scala 1674:25] - wire _T_259 = _T_257 & _T_17; // @[dec_tlu_ctl.scala 1674:39] + wire _T_254 = wr_mscause_r & _T_17; // @[dec_tlu_ctl.scala 1671:38] + wire _T_257 = ~wr_mscause_r; // @[dec_tlu_ctl.scala 1672:25] + wire _T_259 = _T_257 & _T_17; // @[dec_tlu_ctl.scala 1672:39] wire [3:0] _T_261 = io_exc_or_int_valid_r ? mscause_type : 4'h0; // @[Mux.scala 27:72] wire [3:0] _T_262 = _T_254 ? io_dec_csr_wrdata_r[3:0] : 4'h0; // @[Mux.scala 27:72] - reg [3:0] mscause; // @[dec_tlu_ctl.scala 1676:47] + reg [3:0] mscause; // @[dec_tlu_ctl.scala 1674:47] wire [3:0] _T_263 = _T_259 ? mscause : 4'h0; // @[Mux.scala 27:72] wire [3:0] _T_264 = _T_261 | _T_262; // @[Mux.scala 27:72] - wire _T_268 = io_dec_csr_wraddr_r == 12'h343; // @[dec_tlu_ctl.scala 1683:69] - wire wr_mtval_r = io_dec_csr_wen_r_mod & _T_268; // @[dec_tlu_ctl.scala 1683:40] - wire _T_269 = ~io_inst_acc_second_r; // @[dec_tlu_ctl.scala 1684:83] - wire _T_270 = io_inst_acc_r & _T_269; // @[dec_tlu_ctl.scala 1684:81] - wire _T_271 = io_ebreak_r | _T_270; // @[dec_tlu_ctl.scala 1684:64] - wire _T_272 = _T_271 | io_mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 1684:106] - wire _T_273 = io_exc_or_int_valid_r & _T_272; // @[dec_tlu_ctl.scala 1684:49] - wire mtval_capture_pc_r = _T_273 & _T_213; // @[dec_tlu_ctl.scala 1684:138] - wire _T_275 = io_inst_acc_r & io_inst_acc_second_r; // @[dec_tlu_ctl.scala 1685:72] - wire _T_276 = io_exc_or_int_valid_r & _T_275; // @[dec_tlu_ctl.scala 1685:55] - wire mtval_capture_pc_plus2_r = _T_276 & _T_213; // @[dec_tlu_ctl.scala 1685:96] - wire _T_278 = io_exc_or_int_valid_r & io_illegal_r; // @[dec_tlu_ctl.scala 1686:51] - wire mtval_capture_inst_r = _T_278 & _T_213; // @[dec_tlu_ctl.scala 1686:66] - wire _T_280 = io_exc_or_int_valid_r & io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 1687:50] - wire mtval_capture_lsu_r = _T_280 & _T_213; // @[dec_tlu_ctl.scala 1687:71] - wire _T_282 = ~mtval_capture_pc_r; // @[dec_tlu_ctl.scala 1688:46] - wire _T_283 = io_exc_or_int_valid_r & _T_282; // @[dec_tlu_ctl.scala 1688:44] - wire _T_284 = ~mtval_capture_inst_r; // @[dec_tlu_ctl.scala 1688:68] - wire _T_285 = _T_283 & _T_284; // @[dec_tlu_ctl.scala 1688:66] - wire _T_286 = ~mtval_capture_lsu_r; // @[dec_tlu_ctl.scala 1688:92] - wire _T_287 = _T_285 & _T_286; // @[dec_tlu_ctl.scala 1688:90] - wire _T_288 = ~io_mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 1688:115] - wire mtval_clear_r = _T_287 & _T_288; // @[dec_tlu_ctl.scala 1688:113] + wire _T_268 = io_dec_csr_wraddr_r == 12'h343; // @[dec_tlu_ctl.scala 1681:69] + wire wr_mtval_r = io_dec_csr_wen_r_mod & _T_268; // @[dec_tlu_ctl.scala 1681:40] + wire _T_269 = ~io_inst_acc_second_r; // @[dec_tlu_ctl.scala 1682:83] + wire _T_270 = io_inst_acc_r & _T_269; // @[dec_tlu_ctl.scala 1682:81] + wire _T_271 = io_ebreak_r | _T_270; // @[dec_tlu_ctl.scala 1682:64] + wire _T_272 = _T_271 | io_mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 1682:106] + wire _T_273 = io_exc_or_int_valid_r & _T_272; // @[dec_tlu_ctl.scala 1682:49] + wire mtval_capture_pc_r = _T_273 & _T_213; // @[dec_tlu_ctl.scala 1682:138] + wire _T_275 = io_inst_acc_r & io_inst_acc_second_r; // @[dec_tlu_ctl.scala 1683:72] + wire _T_276 = io_exc_or_int_valid_r & _T_275; // @[dec_tlu_ctl.scala 1683:55] + wire mtval_capture_pc_plus2_r = _T_276 & _T_213; // @[dec_tlu_ctl.scala 1683:96] + wire _T_278 = io_exc_or_int_valid_r & io_illegal_r; // @[dec_tlu_ctl.scala 1684:51] + wire mtval_capture_inst_r = _T_278 & _T_213; // @[dec_tlu_ctl.scala 1684:66] + wire _T_280 = io_exc_or_int_valid_r & io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 1685:50] + wire mtval_capture_lsu_r = _T_280 & _T_213; // @[dec_tlu_ctl.scala 1685:71] + wire _T_282 = ~mtval_capture_pc_r; // @[dec_tlu_ctl.scala 1686:46] + wire _T_283 = io_exc_or_int_valid_r & _T_282; // @[dec_tlu_ctl.scala 1686:44] + wire _T_284 = ~mtval_capture_inst_r; // @[dec_tlu_ctl.scala 1686:68] + wire _T_285 = _T_283 & _T_284; // @[dec_tlu_ctl.scala 1686:66] + wire _T_286 = ~mtval_capture_lsu_r; // @[dec_tlu_ctl.scala 1686:92] + wire _T_287 = _T_285 & _T_286; // @[dec_tlu_ctl.scala 1686:90] + wire _T_288 = ~io_mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 1686:115] + wire mtval_clear_r = _T_287 & _T_288; // @[dec_tlu_ctl.scala 1686:113] wire [31:0] _T_290 = {pc_r,1'h0}; // @[Cat.scala 29:58] - wire [30:0] _T_293 = pc_r + 31'h1; // @[dec_tlu_ctl.scala 1693:83] + wire [30:0] _T_293 = pc_r + 31'h1; // @[dec_tlu_ctl.scala 1691:83] wire [31:0] _T_294 = {_T_293,1'h0}; // @[Cat.scala 29:58] - wire _T_297 = ~io_interrupt_valid_r; // @[dec_tlu_ctl.scala 1696:18] - wire _T_298 = wr_mtval_r & _T_297; // @[dec_tlu_ctl.scala 1696:16] - wire _T_301 = ~wr_mtval_r; // @[dec_tlu_ctl.scala 1697:20] - wire _T_302 = _T_213 & _T_301; // @[dec_tlu_ctl.scala 1697:18] - wire _T_304 = _T_302 & _T_282; // @[dec_tlu_ctl.scala 1697:32] - wire _T_306 = _T_304 & _T_284; // @[dec_tlu_ctl.scala 1697:54] - wire _T_307 = ~mtval_clear_r; // @[dec_tlu_ctl.scala 1697:80] - wire _T_308 = _T_306 & _T_307; // @[dec_tlu_ctl.scala 1697:78] - wire _T_310 = _T_308 & _T_286; // @[dec_tlu_ctl.scala 1697:95] + wire _T_297 = ~io_interrupt_valid_r; // @[dec_tlu_ctl.scala 1694:18] + wire _T_298 = wr_mtval_r & _T_297; // @[dec_tlu_ctl.scala 1694:16] + wire _T_301 = ~wr_mtval_r; // @[dec_tlu_ctl.scala 1695:20] + wire _T_302 = _T_213 & _T_301; // @[dec_tlu_ctl.scala 1695:18] + wire _T_304 = _T_302 & _T_282; // @[dec_tlu_ctl.scala 1695:32] + wire _T_306 = _T_304 & _T_284; // @[dec_tlu_ctl.scala 1695:54] + wire _T_307 = ~mtval_clear_r; // @[dec_tlu_ctl.scala 1695:80] + wire _T_308 = _T_306 & _T_307; // @[dec_tlu_ctl.scala 1695:78] + wire _T_310 = _T_308 & _T_286; // @[dec_tlu_ctl.scala 1695:95] wire [31:0] _T_312 = mtval_capture_pc_r ? _T_290 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_313 = mtval_capture_pc_plus2_r ? _T_294 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_314 = mtval_capture_inst_r ? io_dec_illegal_inst : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_315 = mtval_capture_lsu_r ? io_lsu_error_pkt_addr_r : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_316 = _T_298 ? io_dec_csr_wrdata_r : 32'h0; // @[Mux.scala 27:72] - reg [31:0] mtval; // @[dec_tlu_ctl.scala 1699:46] + reg [31:0] mtval; // @[dec_tlu_ctl.scala 1697:46] wire [31:0] _T_317 = _T_310 ? mtval : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_318 = _T_312 | _T_313; // @[Mux.scala 27:72] wire [31:0] _T_319 = _T_318 | _T_314; // @[Mux.scala 27:72] wire [31:0] _T_320 = _T_319 | _T_315; // @[Mux.scala 27:72] wire [31:0] _T_321 = _T_320 | _T_316; // @[Mux.scala 27:72] - wire _T_325 = io_dec_csr_wraddr_r == 12'h7f8; // @[dec_tlu_ctl.scala 1714:68] + wire _T_325 = io_dec_csr_wraddr_r == 12'h7f8; // @[dec_tlu_ctl.scala 1712:68] reg [8:0] mcgc; // @[lib.scala 374:16] - wire _T_337 = io_dec_csr_wraddr_r == 12'h7f9; // @[dec_tlu_ctl.scala 1744:68] + wire _T_337 = io_dec_csr_wraddr_r == 12'h7f9; // @[dec_tlu_ctl.scala 1742:68] reg [14:0] mfdc_int; // @[lib.scala 374:16] - wire [2:0] _T_341 = ~io_dec_csr_wrdata_r[18:16]; // @[dec_tlu_ctl.scala 1757:19] - wire [2:0] _T_345 = ~mfdc_int[14:12]; // @[dec_tlu_ctl.scala 1758:19] - wire [18:0] mfdc = {_T_345,4'h0,mfdc_int[11:0]}; // @[Cat.scala 29:58] - wire _T_357 = io_dec_csr_wraddr_r == 12'h7c2; // @[dec_tlu_ctl.scala 1777:77] - wire _T_358 = io_dec_csr_wen_r_mod & _T_357; // @[dec_tlu_ctl.scala 1777:48] - wire _T_360 = _T_358 & _T_297; // @[dec_tlu_ctl.scala 1777:87] - wire _T_361 = ~io_take_ext_int_start; // @[dec_tlu_ctl.scala 1777:113] - wire _T_364 = io_dec_csr_wraddr_r == 12'h7c0; // @[dec_tlu_ctl.scala 1784:68] - wire _T_368 = ~io_dec_csr_wrdata_r[31]; // @[dec_tlu_ctl.scala 1787:71] - wire _T_369 = io_dec_csr_wrdata_r[30] & _T_368; // @[dec_tlu_ctl.scala 1787:69] - wire _T_373 = ~io_dec_csr_wrdata_r[29]; // @[dec_tlu_ctl.scala 1788:73] - wire _T_374 = io_dec_csr_wrdata_r[28] & _T_373; // @[dec_tlu_ctl.scala 1788:71] - wire _T_378 = ~io_dec_csr_wrdata_r[27]; // @[dec_tlu_ctl.scala 1789:73] - wire _T_379 = io_dec_csr_wrdata_r[26] & _T_378; // @[dec_tlu_ctl.scala 1789:71] - wire _T_383 = ~io_dec_csr_wrdata_r[25]; // @[dec_tlu_ctl.scala 1790:73] - wire _T_384 = io_dec_csr_wrdata_r[24] & _T_383; // @[dec_tlu_ctl.scala 1790:71] - wire _T_388 = ~io_dec_csr_wrdata_r[23]; // @[dec_tlu_ctl.scala 1791:73] - wire _T_389 = io_dec_csr_wrdata_r[22] & _T_388; // @[dec_tlu_ctl.scala 1791:71] - wire _T_393 = ~io_dec_csr_wrdata_r[21]; // @[dec_tlu_ctl.scala 1792:73] - wire _T_394 = io_dec_csr_wrdata_r[20] & _T_393; // @[dec_tlu_ctl.scala 1792:71] - wire _T_398 = ~io_dec_csr_wrdata_r[19]; // @[dec_tlu_ctl.scala 1793:73] - wire _T_399 = io_dec_csr_wrdata_r[18] & _T_398; // @[dec_tlu_ctl.scala 1793:71] - wire _T_403 = ~io_dec_csr_wrdata_r[17]; // @[dec_tlu_ctl.scala 1794:73] - wire _T_404 = io_dec_csr_wrdata_r[16] & _T_403; // @[dec_tlu_ctl.scala 1794:71] - wire _T_408 = ~io_dec_csr_wrdata_r[15]; // @[dec_tlu_ctl.scala 1795:73] - wire _T_409 = io_dec_csr_wrdata_r[14] & _T_408; // @[dec_tlu_ctl.scala 1795:71] - wire _T_413 = ~io_dec_csr_wrdata_r[13]; // @[dec_tlu_ctl.scala 1796:73] - wire _T_414 = io_dec_csr_wrdata_r[12] & _T_413; // @[dec_tlu_ctl.scala 1796:71] - wire _T_418 = ~io_dec_csr_wrdata_r[11]; // @[dec_tlu_ctl.scala 1797:73] - wire _T_419 = io_dec_csr_wrdata_r[10] & _T_418; // @[dec_tlu_ctl.scala 1797:71] - wire _T_423 = ~io_dec_csr_wrdata_r[9]; // @[dec_tlu_ctl.scala 1798:73] - wire _T_424 = io_dec_csr_wrdata_r[8] & _T_423; // @[dec_tlu_ctl.scala 1798:70] - wire _T_428 = ~io_dec_csr_wrdata_r[7]; // @[dec_tlu_ctl.scala 1799:73] - wire _T_429 = io_dec_csr_wrdata_r[6] & _T_428; // @[dec_tlu_ctl.scala 1799:70] - wire _T_433 = ~io_dec_csr_wrdata_r[5]; // @[dec_tlu_ctl.scala 1800:73] - wire _T_434 = io_dec_csr_wrdata_r[4] & _T_433; // @[dec_tlu_ctl.scala 1800:70] - wire _T_438 = ~io_dec_csr_wrdata_r[3]; // @[dec_tlu_ctl.scala 1801:73] - wire _T_439 = io_dec_csr_wrdata_r[2] & _T_438; // @[dec_tlu_ctl.scala 1801:70] - wire _T_444 = io_dec_csr_wrdata_r[0] & _T_500; // @[dec_tlu_ctl.scala 1802:70] - wire [7:0] _T_451 = {io_dec_csr_wrdata_r[7],_T_429,io_dec_csr_wrdata_r[5],_T_434,io_dec_csr_wrdata_r[3],_T_439,io_dec_csr_wrdata_r[1],_T_444}; // @[Cat.scala 29:58] - wire [15:0] _T_459 = {io_dec_csr_wrdata_r[15],_T_409,io_dec_csr_wrdata_r[13],_T_414,io_dec_csr_wrdata_r[11],_T_419,io_dec_csr_wrdata_r[9],_T_424,_T_451}; // @[Cat.scala 29:58] - wire [7:0] _T_466 = {io_dec_csr_wrdata_r[23],_T_389,io_dec_csr_wrdata_r[21],_T_394,io_dec_csr_wrdata_r[19],_T_399,io_dec_csr_wrdata_r[17],_T_404}; // @[Cat.scala 29:58] - wire [15:0] _T_474 = {io_dec_csr_wrdata_r[31],_T_369,io_dec_csr_wrdata_r[29],_T_374,io_dec_csr_wrdata_r[27],_T_379,io_dec_csr_wrdata_r[25],_T_384,_T_466}; // @[Cat.scala 29:58] + wire [2:0] _T_341 = ~io_dec_csr_wrdata_r[18:16]; // @[dec_tlu_ctl.scala 1751:20] + wire _T_344 = ~io_dec_csr_wrdata_r[6]; // @[dec_tlu_ctl.scala 1751:75] + wire [6:0] _T_346 = {_T_344,io_dec_csr_wrdata_r[5:0]}; // @[Cat.scala 29:58] + wire [7:0] _T_347 = {_T_341,io_dec_csr_wrdata_r[11:7]}; // @[Cat.scala 29:58] + wire [2:0] _T_350 = ~mfdc_int[14:12]; // @[dec_tlu_ctl.scala 1752:20] + wire _T_353 = ~mfdc_int[6]; // @[dec_tlu_ctl.scala 1752:63] + wire [18:0] mfdc = {_T_350,4'h0,mfdc_int[11:7],_T_353,mfdc_int[5:0]}; // @[Cat.scala 29:58] + wire _T_367 = io_dec_csr_wraddr_r == 12'h7c2; // @[dec_tlu_ctl.scala 1775:77] + wire _T_368 = io_dec_csr_wen_r_mod & _T_367; // @[dec_tlu_ctl.scala 1775:48] + wire _T_370 = _T_368 & _T_297; // @[dec_tlu_ctl.scala 1775:87] + wire _T_371 = ~io_take_ext_int_start; // @[dec_tlu_ctl.scala 1775:113] + wire _T_374 = io_dec_csr_wraddr_r == 12'h7c0; // @[dec_tlu_ctl.scala 1782:68] + wire _T_378 = ~io_dec_csr_wrdata_r[31]; // @[dec_tlu_ctl.scala 1785:71] + wire _T_379 = io_dec_csr_wrdata_r[30] & _T_378; // @[dec_tlu_ctl.scala 1785:69] + wire _T_383 = ~io_dec_csr_wrdata_r[29]; // @[dec_tlu_ctl.scala 1786:73] + wire _T_384 = io_dec_csr_wrdata_r[28] & _T_383; // @[dec_tlu_ctl.scala 1786:71] + wire _T_388 = ~io_dec_csr_wrdata_r[27]; // @[dec_tlu_ctl.scala 1787:73] + wire _T_389 = io_dec_csr_wrdata_r[26] & _T_388; // @[dec_tlu_ctl.scala 1787:71] + wire _T_393 = ~io_dec_csr_wrdata_r[25]; // @[dec_tlu_ctl.scala 1788:73] + wire _T_394 = io_dec_csr_wrdata_r[24] & _T_393; // @[dec_tlu_ctl.scala 1788:71] + wire _T_398 = ~io_dec_csr_wrdata_r[23]; // @[dec_tlu_ctl.scala 1789:73] + wire _T_399 = io_dec_csr_wrdata_r[22] & _T_398; // @[dec_tlu_ctl.scala 1789:71] + wire _T_403 = ~io_dec_csr_wrdata_r[21]; // @[dec_tlu_ctl.scala 1790:73] + wire _T_404 = io_dec_csr_wrdata_r[20] & _T_403; // @[dec_tlu_ctl.scala 1790:71] + wire _T_408 = ~io_dec_csr_wrdata_r[19]; // @[dec_tlu_ctl.scala 1791:73] + wire _T_409 = io_dec_csr_wrdata_r[18] & _T_408; // @[dec_tlu_ctl.scala 1791:71] + wire _T_413 = ~io_dec_csr_wrdata_r[17]; // @[dec_tlu_ctl.scala 1792:73] + wire _T_414 = io_dec_csr_wrdata_r[16] & _T_413; // @[dec_tlu_ctl.scala 1792:71] + wire _T_418 = ~io_dec_csr_wrdata_r[15]; // @[dec_tlu_ctl.scala 1793:73] + wire _T_419 = io_dec_csr_wrdata_r[14] & _T_418; // @[dec_tlu_ctl.scala 1793:71] + wire _T_423 = ~io_dec_csr_wrdata_r[13]; // @[dec_tlu_ctl.scala 1794:73] + wire _T_424 = io_dec_csr_wrdata_r[12] & _T_423; // @[dec_tlu_ctl.scala 1794:71] + wire _T_428 = ~io_dec_csr_wrdata_r[11]; // @[dec_tlu_ctl.scala 1795:73] + wire _T_429 = io_dec_csr_wrdata_r[10] & _T_428; // @[dec_tlu_ctl.scala 1795:71] + wire _T_433 = ~io_dec_csr_wrdata_r[9]; // @[dec_tlu_ctl.scala 1796:73] + wire _T_434 = io_dec_csr_wrdata_r[8] & _T_433; // @[dec_tlu_ctl.scala 1796:70] + wire _T_438 = ~io_dec_csr_wrdata_r[7]; // @[dec_tlu_ctl.scala 1797:73] + wire _T_439 = io_dec_csr_wrdata_r[6] & _T_438; // @[dec_tlu_ctl.scala 1797:70] + wire _T_443 = ~io_dec_csr_wrdata_r[5]; // @[dec_tlu_ctl.scala 1798:73] + wire _T_444 = io_dec_csr_wrdata_r[4] & _T_443; // @[dec_tlu_ctl.scala 1798:70] + wire _T_448 = ~io_dec_csr_wrdata_r[3]; // @[dec_tlu_ctl.scala 1799:73] + wire _T_449 = io_dec_csr_wrdata_r[2] & _T_448; // @[dec_tlu_ctl.scala 1799:70] + wire _T_454 = io_dec_csr_wrdata_r[0] & _T_510; // @[dec_tlu_ctl.scala 1800:70] + wire [7:0] _T_461 = {io_dec_csr_wrdata_r[7],_T_439,io_dec_csr_wrdata_r[5],_T_444,io_dec_csr_wrdata_r[3],_T_449,io_dec_csr_wrdata_r[1],_T_454}; // @[Cat.scala 29:58] + wire [15:0] _T_469 = {io_dec_csr_wrdata_r[15],_T_419,io_dec_csr_wrdata_r[13],_T_424,io_dec_csr_wrdata_r[11],_T_429,io_dec_csr_wrdata_r[9],_T_434,_T_461}; // @[Cat.scala 29:58] + wire [7:0] _T_476 = {io_dec_csr_wrdata_r[23],_T_399,io_dec_csr_wrdata_r[21],_T_404,io_dec_csr_wrdata_r[19],_T_409,io_dec_csr_wrdata_r[17],_T_414}; // @[Cat.scala 29:58] + wire [15:0] _T_484 = {io_dec_csr_wrdata_r[31],_T_379,io_dec_csr_wrdata_r[29],_T_384,io_dec_csr_wrdata_r[27],_T_389,io_dec_csr_wrdata_r[25],_T_394,_T_476}; // @[Cat.scala 29:58] reg [31:0] mrac; // @[lib.scala 374:16] - wire _T_477 = io_dec_csr_wraddr_r == 12'hbc0; // @[dec_tlu_ctl.scala 1815:69] - wire wr_mdeau_r = io_dec_csr_wen_r_mod & _T_477; // @[dec_tlu_ctl.scala 1815:40] - wire _T_478 = ~wr_mdeau_r; // @[dec_tlu_ctl.scala 1825:59] - wire _T_479 = io_mdseac_locked_f & _T_478; // @[dec_tlu_ctl.scala 1825:57] - wire _T_481 = io_lsu_imprecise_error_store_any | io_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 1827:49] - wire _T_482 = ~io_nmi_int_detected_f; // @[dec_tlu_ctl.scala 1827:86] - wire _T_483 = _T_481 & _T_482; // @[dec_tlu_ctl.scala 1827:84] - wire _T_484 = ~io_mdseac_locked_f; // @[dec_tlu_ctl.scala 1827:111] - wire mdseac_en = _T_483 & _T_484; // @[dec_tlu_ctl.scala 1827:109] + wire _T_487 = io_dec_csr_wraddr_r == 12'hbc0; // @[dec_tlu_ctl.scala 1813:69] + wire wr_mdeau_r = io_dec_csr_wen_r_mod & _T_487; // @[dec_tlu_ctl.scala 1813:40] + wire _T_488 = ~wr_mdeau_r; // @[dec_tlu_ctl.scala 1823:59] + wire _T_489 = io_mdseac_locked_f & _T_488; // @[dec_tlu_ctl.scala 1823:57] + wire _T_491 = io_lsu_imprecise_error_store_any | io_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 1825:49] + wire _T_492 = ~io_nmi_int_detected_f; // @[dec_tlu_ctl.scala 1825:86] + wire _T_493 = _T_491 & _T_492; // @[dec_tlu_ctl.scala 1825:84] + wire _T_494 = ~io_mdseac_locked_f; // @[dec_tlu_ctl.scala 1825:111] + wire mdseac_en = _T_493 & _T_494; // @[dec_tlu_ctl.scala 1825:109] reg [31:0] mdseac; // @[lib.scala 374:16] - wire _T_490 = wr_mpmc_r & io_dec_csr_wrdata_r[0]; // @[dec_tlu_ctl.scala 1842:30] - wire _T_491 = ~io_internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 1842:57] - wire _T_492 = _T_490 & _T_491; // @[dec_tlu_ctl.scala 1842:55] - wire _T_493 = ~io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 1842:89] - wire _T_506 = io_dec_csr_wrdata_r[31:27] > 5'h1a; // @[dec_tlu_ctl.scala 1860:48] - wire [4:0] csr_sat = _T_506 ? 5'h1a : io_dec_csr_wrdata_r[31:27]; // @[dec_tlu_ctl.scala 1860:19] - wire _T_509 = io_dec_csr_wraddr_r == 12'h7f0; // @[dec_tlu_ctl.scala 1862:70] - wire wr_micect_r = io_dec_csr_wen_r_mod & _T_509; // @[dec_tlu_ctl.scala 1862:41] - wire [26:0] _T_510 = {26'h0,io_ic_perr_r_d1}; // @[Cat.scala 29:58] - wire [31:0] _GEN_14 = {{5'd0}, _T_510}; // @[dec_tlu_ctl.scala 1863:23] - wire [31:0] _T_512 = micect + _GEN_14; // @[dec_tlu_ctl.scala 1863:23] - wire [31:0] _T_515 = {csr_sat,io_dec_csr_wrdata_r[26:0]}; // @[Cat.scala 29:58] - wire [26:0] micect_inc = _T_512[26:0]; // @[dec_tlu_ctl.scala 1863:13] - wire [31:0] _T_517 = {micect[31:27],micect_inc}; // @[Cat.scala 29:58] - wire _T_528 = io_dec_csr_wraddr_r == 12'h7f1; // @[dec_tlu_ctl.scala 1877:76] - wire wr_miccmect_r = io_dec_csr_wen_r_mod & _T_528; // @[dec_tlu_ctl.scala 1877:47] - wire _T_530 = io_iccm_sbecc_r_d1 | io_iccm_dma_sb_error; // @[dec_tlu_ctl.scala 1878:70] - wire [26:0] _T_531 = {26'h0,_T_530}; // @[Cat.scala 29:58] - wire [26:0] miccmect_inc = miccmect[26:0] + _T_531; // @[dec_tlu_ctl.scala 1878:33] - wire [31:0] _T_538 = {miccmect[31:27],miccmect_inc}; // @[Cat.scala 29:58] - wire _T_539 = wr_miccmect_r | io_iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 1881:48] - wire _T_550 = io_dec_csr_wraddr_r == 12'h7f2; // @[dec_tlu_ctl.scala 1892:76] - wire wr_mdccmect_r = io_dec_csr_wen_r_mod & _T_550; // @[dec_tlu_ctl.scala 1892:47] - wire [26:0] _T_552 = {26'h0,io_lsu_single_ecc_error_r_d1}; // @[Cat.scala 29:58] - wire [26:0] mdccmect_inc = mdccmect[26:0] + _T_552; // @[dec_tlu_ctl.scala 1893:33] - wire [31:0] _T_559 = {mdccmect[31:27],mdccmect_inc}; // @[Cat.scala 29:58] - wire _T_570 = io_dec_csr_wraddr_r == 12'h7ce; // @[dec_tlu_ctl.scala 1908:69] - wire wr_mfdht_r = io_dec_csr_wen_r_mod & _T_570; // @[dec_tlu_ctl.scala 1908:40] - reg [5:0] mfdht; // @[dec_tlu_ctl.scala 1912:43] - wire _T_575 = io_dec_csr_wraddr_r == 12'h7cf; // @[dec_tlu_ctl.scala 1921:69] - wire wr_mfdhs_r = io_dec_csr_wen_r_mod & _T_575; // @[dec_tlu_ctl.scala 1921:40] - wire _T_578 = ~io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 1924:43] - wire _T_579 = io_dbg_tlu_halted & _T_578; // @[dec_tlu_ctl.scala 1924:41] - wire _T_581 = ~io_lsu_idle_any_f; // @[dec_tlu_ctl.scala 1924:78] - wire _T_582 = ~io_ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 1924:98] - wire [1:0] _T_583 = {_T_581,_T_582}; // @[Cat.scala 29:58] + wire _T_500 = wr_mpmc_r & io_dec_csr_wrdata_r[0]; // @[dec_tlu_ctl.scala 1840:30] + wire _T_501 = ~io_internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 1840:57] + wire _T_502 = _T_500 & _T_501; // @[dec_tlu_ctl.scala 1840:55] + wire _T_503 = ~io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 1840:89] + wire _T_516 = io_dec_csr_wrdata_r[31:27] > 5'h1a; // @[dec_tlu_ctl.scala 1858:48] + wire [4:0] csr_sat = _T_516 ? 5'h1a : io_dec_csr_wrdata_r[31:27]; // @[dec_tlu_ctl.scala 1858:19] + wire _T_519 = io_dec_csr_wraddr_r == 12'h7f0; // @[dec_tlu_ctl.scala 1860:70] + wire wr_micect_r = io_dec_csr_wen_r_mod & _T_519; // @[dec_tlu_ctl.scala 1860:41] + wire [26:0] _T_520 = {26'h0,io_ic_perr_r_d1}; // @[Cat.scala 29:58] + wire [31:0] _GEN_14 = {{5'd0}, _T_520}; // @[dec_tlu_ctl.scala 1861:23] + wire [31:0] _T_522 = micect + _GEN_14; // @[dec_tlu_ctl.scala 1861:23] + wire [31:0] _T_525 = {csr_sat,io_dec_csr_wrdata_r[26:0]}; // @[Cat.scala 29:58] + wire [26:0] micect_inc = _T_522[26:0]; // @[dec_tlu_ctl.scala 1861:13] + wire [31:0] _T_527 = {micect[31:27],micect_inc}; // @[Cat.scala 29:58] + wire _T_538 = io_dec_csr_wraddr_r == 12'h7f1; // @[dec_tlu_ctl.scala 1875:76] + wire wr_miccmect_r = io_dec_csr_wen_r_mod & _T_538; // @[dec_tlu_ctl.scala 1875:47] + wire _T_540 = io_iccm_sbecc_r_d1 | io_iccm_dma_sb_error; // @[dec_tlu_ctl.scala 1876:70] + wire [26:0] _T_541 = {26'h0,_T_540}; // @[Cat.scala 29:58] + wire [26:0] miccmect_inc = miccmect[26:0] + _T_541; // @[dec_tlu_ctl.scala 1876:33] + wire [31:0] _T_548 = {miccmect[31:27],miccmect_inc}; // @[Cat.scala 29:58] + wire _T_549 = wr_miccmect_r | io_iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 1879:48] + wire _T_560 = io_dec_csr_wraddr_r == 12'h7f2; // @[dec_tlu_ctl.scala 1890:76] + wire wr_mdccmect_r = io_dec_csr_wen_r_mod & _T_560; // @[dec_tlu_ctl.scala 1890:47] + wire [26:0] _T_562 = {26'h0,io_lsu_single_ecc_error_r_d1}; // @[Cat.scala 29:58] + wire [26:0] mdccmect_inc = mdccmect[26:0] + _T_562; // @[dec_tlu_ctl.scala 1891:33] + wire [31:0] _T_569 = {mdccmect[31:27],mdccmect_inc}; // @[Cat.scala 29:58] + wire _T_580 = io_dec_csr_wraddr_r == 12'h7ce; // @[dec_tlu_ctl.scala 1906:69] + wire wr_mfdht_r = io_dec_csr_wen_r_mod & _T_580; // @[dec_tlu_ctl.scala 1906:40] + reg [5:0] mfdht; // @[dec_tlu_ctl.scala 1910:43] + wire _T_585 = io_dec_csr_wraddr_r == 12'h7cf; // @[dec_tlu_ctl.scala 1919:69] + wire wr_mfdhs_r = io_dec_csr_wen_r_mod & _T_585; // @[dec_tlu_ctl.scala 1919:40] + wire _T_588 = ~io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 1922:43] + wire _T_589 = io_dbg_tlu_halted & _T_588; // @[dec_tlu_ctl.scala 1922:41] + wire _T_591 = ~io_lsu_idle_any_f; // @[dec_tlu_ctl.scala 1922:78] + wire _T_592 = ~io_ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 1922:98] + wire [1:0] _T_593 = {_T_591,_T_592}; // @[Cat.scala 29:58] reg [1:0] mfdhs; // @[Reg.scala 27:20] - wire _T_585 = wr_mfdhs_r | io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 1926:71] + wire _T_595 = wr_mfdhs_r | io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 1924:71] reg [31:0] force_halt_ctr_f; // @[Reg.scala 27:20] - wire [31:0] _T_590 = force_halt_ctr_f + 32'h1; // @[dec_tlu_ctl.scala 1928:74] - wire [62:0] _T_597 = 63'hffffffff << mfdht[5:1]; // @[dec_tlu_ctl.scala 1933:71] - wire [62:0] _GEN_15 = {{31'd0}, force_halt_ctr_f}; // @[dec_tlu_ctl.scala 1933:48] - wire [62:0] _T_598 = _GEN_15 & _T_597; // @[dec_tlu_ctl.scala 1933:48] - wire _T_599 = |_T_598; // @[dec_tlu_ctl.scala 1933:87] - wire _T_602 = io_dec_csr_wraddr_r == 12'hbc8; // @[dec_tlu_ctl.scala 1941:69] + wire [31:0] _T_600 = force_halt_ctr_f + 32'h1; // @[dec_tlu_ctl.scala 1926:74] + wire [62:0] _T_607 = 63'hffffffff << mfdht[5:1]; // @[dec_tlu_ctl.scala 1931:71] + wire [62:0] _GEN_15 = {{31'd0}, force_halt_ctr_f}; // @[dec_tlu_ctl.scala 1931:48] + wire [62:0] _T_608 = _GEN_15 & _T_607; // @[dec_tlu_ctl.scala 1931:48] + wire _T_609 = |_T_608; // @[dec_tlu_ctl.scala 1931:87] + wire _T_612 = io_dec_csr_wraddr_r == 12'hbc8; // @[dec_tlu_ctl.scala 1939:69] reg [21:0] meivt; // @[lib.scala 374:16] - wire _T_621 = io_dec_csr_wraddr_r == 12'hbca; // @[dec_tlu_ctl.scala 1992:69] - wire _T_622 = io_dec_csr_wen_r_mod & _T_621; // @[dec_tlu_ctl.scala 1992:40] - wire wr_meicpct_r = _T_622 | io_take_ext_int_start; // @[dec_tlu_ctl.scala 1992:83] + wire _T_631 = io_dec_csr_wraddr_r == 12'hbca; // @[dec_tlu_ctl.scala 1990:69] + wire _T_632 = io_dec_csr_wen_r_mod & _T_631; // @[dec_tlu_ctl.scala 1990:40] + wire wr_meicpct_r = _T_632 | io_take_ext_int_start; // @[dec_tlu_ctl.scala 1990:83] reg [7:0] meihap; // @[lib.scala 374:16] - wire _T_608 = io_dec_csr_wraddr_r == 12'hbcc; // @[dec_tlu_ctl.scala 1965:72] - wire wr_meicurpl_r = io_dec_csr_wen_r_mod & _T_608; // @[dec_tlu_ctl.scala 1965:43] - reg [3:0] meicurpl; // @[dec_tlu_ctl.scala 1968:46] - wire _T_613 = io_dec_csr_wraddr_r == 12'hbcb; // @[dec_tlu_ctl.scala 1980:73] - wire _T_614 = io_dec_csr_wen_r_mod & _T_613; // @[dec_tlu_ctl.scala 1980:44] - wire wr_meicidpl_r = _T_614 | io_take_ext_int_start; // @[dec_tlu_ctl.scala 1980:88] - reg [3:0] meicidpl; // @[dec_tlu_ctl.scala 1985:44] - wire _T_625 = io_dec_csr_wraddr_r == 12'hbc9; // @[dec_tlu_ctl.scala 2001:69] - wire wr_meipt_r = io_dec_csr_wen_r_mod & _T_625; // @[dec_tlu_ctl.scala 2001:40] - reg [3:0] meipt; // @[dec_tlu_ctl.scala 2004:43] - wire _T_629 = io_trigger_hit_r_d1 & io_dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 2032:89] - wire trigger_hit_for_dscr_cause_r_d1 = io_trigger_hit_dmode_r_d1 | _T_629; // @[dec_tlu_ctl.scala 2032:66] - wire _T_630 = ~io_ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 2035:31] - wire _T_631 = io_dcsr_single_step_done_f & _T_630; // @[dec_tlu_ctl.scala 2035:29] - wire _T_632 = ~trigger_hit_for_dscr_cause_r_d1; // @[dec_tlu_ctl.scala 2035:63] - wire _T_633 = _T_631 & _T_632; // @[dec_tlu_ctl.scala 2035:61] - wire _T_634 = ~io_debug_halt_req; // @[dec_tlu_ctl.scala 2035:98] - wire _T_635 = _T_633 & _T_634; // @[dec_tlu_ctl.scala 2035:96] - wire _T_638 = io_debug_halt_req & _T_630; // @[dec_tlu_ctl.scala 2036:46] - wire _T_640 = _T_638 & _T_632; // @[dec_tlu_ctl.scala 2036:78] - wire _T_643 = io_ebreak_to_debug_mode_r_d1 & _T_632; // @[dec_tlu_ctl.scala 2037:75] - wire [2:0] _T_646 = _T_635 ? 3'h4 : 3'h0; // @[Mux.scala 27:72] - wire [2:0] _T_647 = _T_640 ? 3'h3 : 3'h0; // @[Mux.scala 27:72] - wire [2:0] _T_648 = _T_643 ? 3'h1 : 3'h0; // @[Mux.scala 27:72] - wire [2:0] _T_649 = trigger_hit_for_dscr_cause_r_d1 ? 3'h2 : 3'h0; // @[Mux.scala 27:72] - wire [2:0] _T_650 = _T_646 | _T_647; // @[Mux.scala 27:72] - wire [2:0] _T_651 = _T_650 | _T_648; // @[Mux.scala 27:72] - wire [2:0] dcsr_cause = _T_651 | _T_649; // @[Mux.scala 27:72] - wire _T_653 = io_allow_dbg_halt_csr_write & io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 2040:46] - wire _T_655 = io_dec_csr_wraddr_r == 12'h7b0; // @[dec_tlu_ctl.scala 2040:98] - wire wr_dcsr_r = _T_653 & _T_655; // @[dec_tlu_ctl.scala 2040:69] - wire _T_657 = io_dcsr[8:6] == 3'h3; // @[dec_tlu_ctl.scala 2046:75] - wire dcsr_cause_upgradeable = io_internal_dbg_halt_mode_f & _T_657; // @[dec_tlu_ctl.scala 2046:59] - wire _T_658 = ~io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 2047:59] - wire _T_659 = _T_658 | dcsr_cause_upgradeable; // @[dec_tlu_ctl.scala 2047:78] - wire enter_debug_halt_req_le = io_enter_debug_halt_req & _T_659; // @[dec_tlu_ctl.scala 2047:56] - wire nmi_in_debug_mode = io_nmi_int_detected_f & io_internal_dbg_halt_mode_f; // @[dec_tlu_ctl.scala 2049:48] - wire [15:0] _T_665 = {io_dcsr[15:9],dcsr_cause,io_dcsr[5:2],2'h3}; // @[Cat.scala 29:58] - wire _T_671 = nmi_in_debug_mode | io_dcsr[3]; // @[dec_tlu_ctl.scala 2051:145] - wire [15:0] _T_680 = {io_dec_csr_wrdata_r[15],3'h0,io_dec_csr_wrdata_r[11:10],1'h0,io_dcsr[8:6],2'h0,_T_671,io_dec_csr_wrdata_r[2],2'h3}; // @[Cat.scala 29:58] - wire [15:0] _T_685 = {io_dcsr[15:4],nmi_in_debug_mode,io_dcsr[2],2'h3}; // @[Cat.scala 29:58] - wire _T_687 = enter_debug_halt_req_le | wr_dcsr_r; // @[dec_tlu_ctl.scala 2053:54] - wire _T_688 = _T_687 | io_internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 2053:66] - reg [15:0] _T_691; // @[lib.scala 374:16] - wire _T_694 = io_dec_csr_wraddr_r == 12'h7b1; // @[dec_tlu_ctl.scala 2061:97] - wire wr_dpc_r = _T_653 & _T_694; // @[dec_tlu_ctl.scala 2061:68] - wire _T_697 = ~io_request_debug_mode_done; // @[dec_tlu_ctl.scala 2062:67] - wire dpc_capture_npc = _T_579 & _T_697; // @[dec_tlu_ctl.scala 2062:65] - wire _T_698 = ~io_request_debug_mode_r; // @[dec_tlu_ctl.scala 2066:21] - wire _T_699 = ~dpc_capture_npc; // @[dec_tlu_ctl.scala 2066:39] - wire _T_700 = _T_698 & _T_699; // @[dec_tlu_ctl.scala 2066:37] - wire _T_701 = _T_700 & wr_dpc_r; // @[dec_tlu_ctl.scala 2066:56] - wire _T_706 = _T_698 & dpc_capture_npc; // @[dec_tlu_ctl.scala 2068:49] - wire [30:0] _T_708 = _T_701 ? io_dec_csr_wrdata_r[31:1] : 31'h0; // @[Mux.scala 27:72] - wire [30:0] _T_709 = io_request_debug_mode_r ? pc_r : 31'h0; // @[Mux.scala 27:72] - wire [30:0] _T_710 = _T_706 ? io_npc_r : 31'h0; // @[Mux.scala 27:72] - wire [30:0] _T_711 = _T_708 | _T_709; // @[Mux.scala 27:72] - wire _T_713 = wr_dpc_r | io_request_debug_mode_r; // @[dec_tlu_ctl.scala 2070:36] - reg [30:0] _T_716; // @[lib.scala 374:16] - wire [2:0] _T_720 = {io_dec_csr_wrdata_r[24],io_dec_csr_wrdata_r[21:20]}; // @[Cat.scala 29:58] - wire _T_723 = io_dec_csr_wraddr_r == 12'h7c8; // @[dec_tlu_ctl.scala 2085:102] + wire _T_618 = io_dec_csr_wraddr_r == 12'hbcc; // @[dec_tlu_ctl.scala 1963:72] + wire wr_meicurpl_r = io_dec_csr_wen_r_mod & _T_618; // @[dec_tlu_ctl.scala 1963:43] + reg [3:0] meicurpl; // @[dec_tlu_ctl.scala 1966:46] + wire _T_623 = io_dec_csr_wraddr_r == 12'hbcb; // @[dec_tlu_ctl.scala 1978:73] + wire _T_624 = io_dec_csr_wen_r_mod & _T_623; // @[dec_tlu_ctl.scala 1978:44] + wire wr_meicidpl_r = _T_624 | io_take_ext_int_start; // @[dec_tlu_ctl.scala 1978:88] + reg [3:0] meicidpl; // @[dec_tlu_ctl.scala 1983:44] + wire _T_635 = io_dec_csr_wraddr_r == 12'hbc9; // @[dec_tlu_ctl.scala 1999:69] + wire wr_meipt_r = io_dec_csr_wen_r_mod & _T_635; // @[dec_tlu_ctl.scala 1999:40] + reg [3:0] meipt; // @[dec_tlu_ctl.scala 2002:43] + wire _T_639 = io_trigger_hit_r_d1 & io_dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 2030:89] + wire trigger_hit_for_dscr_cause_r_d1 = io_trigger_hit_dmode_r_d1 | _T_639; // @[dec_tlu_ctl.scala 2030:66] + wire _T_640 = ~io_ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 2033:31] + wire _T_641 = io_dcsr_single_step_done_f & _T_640; // @[dec_tlu_ctl.scala 2033:29] + wire _T_642 = ~trigger_hit_for_dscr_cause_r_d1; // @[dec_tlu_ctl.scala 2033:63] + wire _T_643 = _T_641 & _T_642; // @[dec_tlu_ctl.scala 2033:61] + wire _T_644 = ~io_debug_halt_req; // @[dec_tlu_ctl.scala 2033:98] + wire _T_645 = _T_643 & _T_644; // @[dec_tlu_ctl.scala 2033:96] + wire _T_648 = io_debug_halt_req & _T_640; // @[dec_tlu_ctl.scala 2034:46] + wire _T_650 = _T_648 & _T_642; // @[dec_tlu_ctl.scala 2034:78] + wire _T_653 = io_ebreak_to_debug_mode_r_d1 & _T_642; // @[dec_tlu_ctl.scala 2035:75] + wire [2:0] _T_656 = _T_645 ? 3'h4 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_657 = _T_650 ? 3'h3 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_658 = _T_653 ? 3'h1 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_659 = trigger_hit_for_dscr_cause_r_d1 ? 3'h2 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_660 = _T_656 | _T_657; // @[Mux.scala 27:72] + wire [2:0] _T_661 = _T_660 | _T_658; // @[Mux.scala 27:72] + wire [2:0] dcsr_cause = _T_661 | _T_659; // @[Mux.scala 27:72] + wire _T_663 = io_allow_dbg_halt_csr_write & io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 2038:46] + wire _T_665 = io_dec_csr_wraddr_r == 12'h7b0; // @[dec_tlu_ctl.scala 2038:98] + wire wr_dcsr_r = _T_663 & _T_665; // @[dec_tlu_ctl.scala 2038:69] + wire _T_667 = io_dcsr[8:6] == 3'h3; // @[dec_tlu_ctl.scala 2044:75] + wire dcsr_cause_upgradeable = io_internal_dbg_halt_mode_f & _T_667; // @[dec_tlu_ctl.scala 2044:59] + wire _T_668 = ~io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 2045:59] + wire _T_669 = _T_668 | dcsr_cause_upgradeable; // @[dec_tlu_ctl.scala 2045:78] + wire enter_debug_halt_req_le = io_enter_debug_halt_req & _T_669; // @[dec_tlu_ctl.scala 2045:56] + wire nmi_in_debug_mode = io_nmi_int_detected_f & io_internal_dbg_halt_mode_f; // @[dec_tlu_ctl.scala 2047:48] + wire [15:0] _T_675 = {io_dcsr[15:9],dcsr_cause,io_dcsr[5:2],2'h3}; // @[Cat.scala 29:58] + wire _T_681 = nmi_in_debug_mode | io_dcsr[3]; // @[dec_tlu_ctl.scala 2049:145] + wire [15:0] _T_690 = {io_dec_csr_wrdata_r[15],3'h0,io_dec_csr_wrdata_r[11:10],1'h0,io_dcsr[8:6],2'h0,_T_681,io_dec_csr_wrdata_r[2],2'h3}; // @[Cat.scala 29:58] + wire [15:0] _T_695 = {io_dcsr[15:4],nmi_in_debug_mode,io_dcsr[2],2'h3}; // @[Cat.scala 29:58] + wire _T_697 = enter_debug_halt_req_le | wr_dcsr_r; // @[dec_tlu_ctl.scala 2051:54] + wire _T_698 = _T_697 | io_internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 2051:66] + reg [15:0] _T_701; // @[lib.scala 374:16] + wire _T_704 = io_dec_csr_wraddr_r == 12'h7b1; // @[dec_tlu_ctl.scala 2059:97] + wire wr_dpc_r = _T_663 & _T_704; // @[dec_tlu_ctl.scala 2059:68] + wire _T_707 = ~io_request_debug_mode_done; // @[dec_tlu_ctl.scala 2060:67] + wire dpc_capture_npc = _T_589 & _T_707; // @[dec_tlu_ctl.scala 2060:65] + wire _T_708 = ~io_request_debug_mode_r; // @[dec_tlu_ctl.scala 2064:21] + wire _T_709 = ~dpc_capture_npc; // @[dec_tlu_ctl.scala 2064:39] + wire _T_710 = _T_708 & _T_709; // @[dec_tlu_ctl.scala 2064:37] + wire _T_711 = _T_710 & wr_dpc_r; // @[dec_tlu_ctl.scala 2064:56] + wire _T_716 = _T_708 & dpc_capture_npc; // @[dec_tlu_ctl.scala 2066:49] + wire [30:0] _T_718 = _T_711 ? io_dec_csr_wrdata_r[31:1] : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_719 = io_request_debug_mode_r ? pc_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_720 = _T_716 ? io_npc_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_721 = _T_718 | _T_719; // @[Mux.scala 27:72] + wire _T_723 = wr_dpc_r | io_request_debug_mode_r; // @[dec_tlu_ctl.scala 2068:36] + reg [30:0] _T_726; // @[lib.scala 374:16] + wire [2:0] _T_730 = {io_dec_csr_wrdata_r[24],io_dec_csr_wrdata_r[21:20]}; // @[Cat.scala 29:58] + wire _T_733 = io_dec_csr_wraddr_r == 12'h7c8; // @[dec_tlu_ctl.scala 2083:102] reg [16:0] dicawics; // @[lib.scala 374:16] - wire _T_727 = io_dec_csr_wraddr_r == 12'h7c9; // @[dec_tlu_ctl.scala 2103:100] - wire wr_dicad0_r = _T_653 & _T_727; // @[dec_tlu_ctl.scala 2103:71] + wire _T_737 = io_dec_csr_wraddr_r == 12'h7c9; // @[dec_tlu_ctl.scala 2101:100] + wire wr_dicad0_r = _T_663 & _T_737; // @[dec_tlu_ctl.scala 2101:71] reg [70:0] dicad0; // @[lib.scala 374:16] - wire _T_733 = io_dec_csr_wraddr_r == 12'h7cc; // @[dec_tlu_ctl.scala 2116:101] - wire wr_dicad0h_r = _T_653 & _T_733; // @[dec_tlu_ctl.scala 2116:72] + wire _T_743 = io_dec_csr_wraddr_r == 12'h7cc; // @[dec_tlu_ctl.scala 2114:101] + wire wr_dicad0h_r = _T_663 & _T_743; // @[dec_tlu_ctl.scala 2114:72] reg [31:0] dicad0h; // @[lib.scala 374:16] - wire _T_741 = io_dec_csr_wraddr_r == 12'h7ca; // @[dec_tlu_ctl.scala 2128:100] - wire _T_742 = _T_653 & _T_741; // @[dec_tlu_ctl.scala 2128:71] - wire _T_747 = _T_742 | io_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 2132:78] - reg [6:0] _T_749; // @[Reg.scala 27:20] - wire [31:0] dicad1 = {25'h0,_T_749}; // @[Cat.scala 29:58] - wire [38:0] _T_754 = {dicad1[6:0],dicad0h}; // @[Cat.scala 29:58] - wire _T_756 = io_allow_dbg_halt_csr_write & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 2160:52] - wire _T_757 = _T_756 & io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 2160:75] - wire _T_758 = ~io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 2160:98] - wire _T_759 = _T_757 & _T_758; // @[dec_tlu_ctl.scala 2160:96] - wire _T_761 = io_dec_csr_rdaddr_d == 12'h7cb; // @[dec_tlu_ctl.scala 2160:149] - wire _T_764 = io_dec_csr_wraddr_r == 12'h7cb; // @[dec_tlu_ctl.scala 2161:104] - reg icache_rd_valid_f; // @[dec_tlu_ctl.scala 2163:58] - reg icache_wr_valid_f; // @[dec_tlu_ctl.scala 2164:58] - wire _T_766 = io_dec_csr_wraddr_r == 12'h7a0; // @[dec_tlu_ctl.scala 2175:69] - wire wr_mtsel_r = io_dec_csr_wen_r_mod & _T_766; // @[dec_tlu_ctl.scala 2175:40] - reg [1:0] mtsel; // @[dec_tlu_ctl.scala 2178:43] - wire tdata_load = io_dec_csr_wrdata_r[0] & _T_398; // @[dec_tlu_ctl.scala 2213:42] - wire tdata_opcode = io_dec_csr_wrdata_r[2] & _T_398; // @[dec_tlu_ctl.scala 2215:44] - wire _T_777 = io_dec_csr_wrdata_r[27] & io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2217:46] - wire tdata_action = _T_777 & io_dec_csr_wrdata_r[12]; // @[dec_tlu_ctl.scala 2217:69] - wire [9:0] tdata_wrdata_r = {_T_777,io_dec_csr_wrdata_r[20:19],tdata_action,io_dec_csr_wrdata_r[11],io_dec_csr_wrdata_r[7:6],tdata_opcode,io_dec_csr_wrdata_r[1],tdata_load}; // @[Cat.scala 29:58] - wire _T_792 = io_dec_csr_wraddr_r == 12'h7a1; // @[dec_tlu_ctl.scala 2223:99] - wire _T_793 = io_dec_csr_wen_r_mod & _T_792; // @[dec_tlu_ctl.scala 2223:70] - wire _T_794 = mtsel == 2'h0; // @[dec_tlu_ctl.scala 2223:121] - wire _T_795 = _T_793 & _T_794; // @[dec_tlu_ctl.scala 2223:112] - wire _T_797 = ~io_mtdata1_t_0[9]; // @[dec_tlu_ctl.scala 2223:138] - wire _T_798 = _T_797 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2223:170] - wire wr_mtdata1_t_r_0 = _T_795 & _T_798; // @[dec_tlu_ctl.scala 2223:135] - wire _T_803 = mtsel == 2'h1; // @[dec_tlu_ctl.scala 2223:121] - wire _T_804 = _T_793 & _T_803; // @[dec_tlu_ctl.scala 2223:112] - wire _T_806 = ~io_mtdata1_t_1[9]; // @[dec_tlu_ctl.scala 2223:138] - wire _T_807 = _T_806 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2223:170] - wire wr_mtdata1_t_r_1 = _T_804 & _T_807; // @[dec_tlu_ctl.scala 2223:135] - wire _T_812 = mtsel == 2'h2; // @[dec_tlu_ctl.scala 2223:121] - wire _T_813 = _T_793 & _T_812; // @[dec_tlu_ctl.scala 2223:112] - wire _T_815 = ~io_mtdata1_t_2[9]; // @[dec_tlu_ctl.scala 2223:138] - wire _T_816 = _T_815 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2223:170] - wire wr_mtdata1_t_r_2 = _T_813 & _T_816; // @[dec_tlu_ctl.scala 2223:135] - wire _T_821 = mtsel == 2'h3; // @[dec_tlu_ctl.scala 2223:121] - wire _T_822 = _T_793 & _T_821; // @[dec_tlu_ctl.scala 2223:112] - wire _T_824 = ~io_mtdata1_t_3[9]; // @[dec_tlu_ctl.scala 2223:138] - wire _T_825 = _T_824 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2223:170] - wire wr_mtdata1_t_r_3 = _T_822 & _T_825; // @[dec_tlu_ctl.scala 2223:135] - wire _T_831 = io_update_hit_bit_r[0] | io_mtdata1_t_0[8]; // @[dec_tlu_ctl.scala 2224:139] - wire [9:0] _T_834 = {io_mtdata1_t_0[9],_T_831,io_mtdata1_t_0[7:0]}; // @[Cat.scala 29:58] - wire _T_840 = io_update_hit_bit_r[1] | io_mtdata1_t_1[8]; // @[dec_tlu_ctl.scala 2224:139] - wire [9:0] _T_843 = {io_mtdata1_t_1[9],_T_840,io_mtdata1_t_1[7:0]}; // @[Cat.scala 29:58] - wire _T_849 = io_update_hit_bit_r[2] | io_mtdata1_t_2[8]; // @[dec_tlu_ctl.scala 2224:139] - wire [9:0] _T_852 = {io_mtdata1_t_2[9],_T_849,io_mtdata1_t_2[7:0]}; // @[Cat.scala 29:58] - wire _T_858 = io_update_hit_bit_r[3] | io_mtdata1_t_3[8]; // @[dec_tlu_ctl.scala 2224:139] - wire [9:0] _T_861 = {io_mtdata1_t_3[9],_T_858,io_mtdata1_t_3[7:0]}; // @[Cat.scala 29:58] - reg [9:0] _T_863; // @[dec_tlu_ctl.scala 2226:74] - reg [9:0] _T_864; // @[dec_tlu_ctl.scala 2226:74] - reg [9:0] _T_865; // @[dec_tlu_ctl.scala 2226:74] - reg [9:0] _T_866; // @[dec_tlu_ctl.scala 2226:74] - wire [31:0] _T_881 = {4'h2,io_mtdata1_t_0[9],6'h1f,io_mtdata1_t_0[8:7],6'h0,io_mtdata1_t_0[6:5],3'h0,io_mtdata1_t_0[4:3],3'h0,io_mtdata1_t_0[2:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_896 = {4'h2,io_mtdata1_t_1[9],6'h1f,io_mtdata1_t_1[8:7],6'h0,io_mtdata1_t_1[6:5],3'h0,io_mtdata1_t_1[4:3],3'h0,io_mtdata1_t_1[2:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_911 = {4'h2,io_mtdata1_t_2[9],6'h1f,io_mtdata1_t_2[8:7],6'h0,io_mtdata1_t_2[6:5],3'h0,io_mtdata1_t_2[4:3],3'h0,io_mtdata1_t_2[2:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_926 = {4'h2,io_mtdata1_t_3[9],6'h1f,io_mtdata1_t_3[8:7],6'h0,io_mtdata1_t_3[6:5],3'h0,io_mtdata1_t_3[4:3],3'h0,io_mtdata1_t_3[2:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_927 = _T_794 ? _T_881 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_928 = _T_803 ? _T_896 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_929 = _T_812 ? _T_911 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_930 = _T_821 ? _T_926 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_931 = _T_927 | _T_928; // @[Mux.scala 27:72] - wire [31:0] _T_932 = _T_931 | _T_929; // @[Mux.scala 27:72] - wire [31:0] mtdata1_tsel_out = _T_932 | _T_930; // @[Mux.scala 27:72] - wire _T_959 = io_dec_csr_wraddr_r == 12'h7a2; // @[dec_tlu_ctl.scala 2243:98] - wire _T_960 = io_dec_csr_wen_r_mod & _T_959; // @[dec_tlu_ctl.scala 2243:69] - wire _T_962 = _T_960 & _T_794; // @[dec_tlu_ctl.scala 2243:111] - wire _T_971 = _T_960 & _T_803; // @[dec_tlu_ctl.scala 2243:111] - wire _T_980 = _T_960 & _T_812; // @[dec_tlu_ctl.scala 2243:111] - wire _T_989 = _T_960 & _T_821; // @[dec_tlu_ctl.scala 2243:111] + wire _T_751 = io_dec_csr_wraddr_r == 12'h7ca; // @[dec_tlu_ctl.scala 2126:100] + wire _T_752 = _T_663 & _T_751; // @[dec_tlu_ctl.scala 2126:71] + wire _T_757 = _T_752 | io_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 2130:78] + reg [6:0] _T_759; // @[Reg.scala 27:20] + wire [31:0] dicad1 = {25'h0,_T_759}; // @[Cat.scala 29:58] + wire [38:0] _T_764 = {dicad1[6:0],dicad0h}; // @[Cat.scala 29:58] + wire _T_766 = io_allow_dbg_halt_csr_write & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 2158:52] + wire _T_767 = _T_766 & io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 2158:75] + wire _T_768 = ~io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 2158:98] + wire _T_769 = _T_767 & _T_768; // @[dec_tlu_ctl.scala 2158:96] + wire _T_771 = io_dec_csr_rdaddr_d == 12'h7cb; // @[dec_tlu_ctl.scala 2158:149] + wire _T_774 = io_dec_csr_wraddr_r == 12'h7cb; // @[dec_tlu_ctl.scala 2159:104] + reg icache_rd_valid_f; // @[dec_tlu_ctl.scala 2161:58] + reg icache_wr_valid_f; // @[dec_tlu_ctl.scala 2162:58] + wire _T_776 = io_dec_csr_wraddr_r == 12'h7a0; // @[dec_tlu_ctl.scala 2173:69] + wire wr_mtsel_r = io_dec_csr_wen_r_mod & _T_776; // @[dec_tlu_ctl.scala 2173:40] + reg [1:0] mtsel; // @[dec_tlu_ctl.scala 2176:43] + wire tdata_load = io_dec_csr_wrdata_r[0] & _T_408; // @[dec_tlu_ctl.scala 2211:42] + wire tdata_opcode = io_dec_csr_wrdata_r[2] & _T_408; // @[dec_tlu_ctl.scala 2213:44] + wire _T_787 = io_dec_csr_wrdata_r[27] & io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2215:46] + wire tdata_action = _T_787 & io_dec_csr_wrdata_r[12]; // @[dec_tlu_ctl.scala 2215:69] + wire [9:0] tdata_wrdata_r = {_T_787,io_dec_csr_wrdata_r[20:19],tdata_action,io_dec_csr_wrdata_r[11],io_dec_csr_wrdata_r[7:6],tdata_opcode,io_dec_csr_wrdata_r[1],tdata_load}; // @[Cat.scala 29:58] + wire _T_802 = io_dec_csr_wraddr_r == 12'h7a1; // @[dec_tlu_ctl.scala 2221:99] + wire _T_803 = io_dec_csr_wen_r_mod & _T_802; // @[dec_tlu_ctl.scala 2221:70] + wire _T_804 = mtsel == 2'h0; // @[dec_tlu_ctl.scala 2221:121] + wire _T_805 = _T_803 & _T_804; // @[dec_tlu_ctl.scala 2221:112] + wire _T_807 = ~io_mtdata1_t_0[9]; // @[dec_tlu_ctl.scala 2221:138] + wire _T_808 = _T_807 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2221:170] + wire wr_mtdata1_t_r_0 = _T_805 & _T_808; // @[dec_tlu_ctl.scala 2221:135] + wire _T_813 = mtsel == 2'h1; // @[dec_tlu_ctl.scala 2221:121] + wire _T_814 = _T_803 & _T_813; // @[dec_tlu_ctl.scala 2221:112] + wire _T_816 = ~io_mtdata1_t_1[9]; // @[dec_tlu_ctl.scala 2221:138] + wire _T_817 = _T_816 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2221:170] + wire wr_mtdata1_t_r_1 = _T_814 & _T_817; // @[dec_tlu_ctl.scala 2221:135] + wire _T_822 = mtsel == 2'h2; // @[dec_tlu_ctl.scala 2221:121] + wire _T_823 = _T_803 & _T_822; // @[dec_tlu_ctl.scala 2221:112] + wire _T_825 = ~io_mtdata1_t_2[9]; // @[dec_tlu_ctl.scala 2221:138] + wire _T_826 = _T_825 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2221:170] + wire wr_mtdata1_t_r_2 = _T_823 & _T_826; // @[dec_tlu_ctl.scala 2221:135] + wire _T_831 = mtsel == 2'h3; // @[dec_tlu_ctl.scala 2221:121] + wire _T_832 = _T_803 & _T_831; // @[dec_tlu_ctl.scala 2221:112] + wire _T_834 = ~io_mtdata1_t_3[9]; // @[dec_tlu_ctl.scala 2221:138] + wire _T_835 = _T_834 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2221:170] + wire wr_mtdata1_t_r_3 = _T_832 & _T_835; // @[dec_tlu_ctl.scala 2221:135] + wire _T_841 = io_update_hit_bit_r[0] | io_mtdata1_t_0[8]; // @[dec_tlu_ctl.scala 2222:139] + wire [9:0] _T_844 = {io_mtdata1_t_0[9],_T_841,io_mtdata1_t_0[7:0]}; // @[Cat.scala 29:58] + wire _T_850 = io_update_hit_bit_r[1] | io_mtdata1_t_1[8]; // @[dec_tlu_ctl.scala 2222:139] + wire [9:0] _T_853 = {io_mtdata1_t_1[9],_T_850,io_mtdata1_t_1[7:0]}; // @[Cat.scala 29:58] + wire _T_859 = io_update_hit_bit_r[2] | io_mtdata1_t_2[8]; // @[dec_tlu_ctl.scala 2222:139] + wire [9:0] _T_862 = {io_mtdata1_t_2[9],_T_859,io_mtdata1_t_2[7:0]}; // @[Cat.scala 29:58] + wire _T_868 = io_update_hit_bit_r[3] | io_mtdata1_t_3[8]; // @[dec_tlu_ctl.scala 2222:139] + wire [9:0] _T_871 = {io_mtdata1_t_3[9],_T_868,io_mtdata1_t_3[7:0]}; // @[Cat.scala 29:58] + reg [9:0] _T_873; // @[dec_tlu_ctl.scala 2224:74] + reg [9:0] _T_874; // @[dec_tlu_ctl.scala 2224:74] + reg [9:0] _T_875; // @[dec_tlu_ctl.scala 2224:74] + reg [9:0] _T_876; // @[dec_tlu_ctl.scala 2224:74] + wire [31:0] _T_891 = {4'h2,io_mtdata1_t_0[9],6'h1f,io_mtdata1_t_0[8:7],6'h0,io_mtdata1_t_0[6:5],3'h0,io_mtdata1_t_0[4:3],3'h0,io_mtdata1_t_0[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_906 = {4'h2,io_mtdata1_t_1[9],6'h1f,io_mtdata1_t_1[8:7],6'h0,io_mtdata1_t_1[6:5],3'h0,io_mtdata1_t_1[4:3],3'h0,io_mtdata1_t_1[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_921 = {4'h2,io_mtdata1_t_2[9],6'h1f,io_mtdata1_t_2[8:7],6'h0,io_mtdata1_t_2[6:5],3'h0,io_mtdata1_t_2[4:3],3'h0,io_mtdata1_t_2[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_936 = {4'h2,io_mtdata1_t_3[9],6'h1f,io_mtdata1_t_3[8:7],6'h0,io_mtdata1_t_3[6:5],3'h0,io_mtdata1_t_3[4:3],3'h0,io_mtdata1_t_3[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_937 = _T_804 ? _T_891 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_938 = _T_813 ? _T_906 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_939 = _T_822 ? _T_921 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_940 = _T_831 ? _T_936 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_941 = _T_937 | _T_938; // @[Mux.scala 27:72] + wire [31:0] _T_942 = _T_941 | _T_939; // @[Mux.scala 27:72] + wire [31:0] mtdata1_tsel_out = _T_942 | _T_940; // @[Mux.scala 27:72] + wire _T_969 = io_dec_csr_wraddr_r == 12'h7a2; // @[dec_tlu_ctl.scala 2241:98] + wire _T_970 = io_dec_csr_wen_r_mod & _T_969; // @[dec_tlu_ctl.scala 2241:69] + wire _T_972 = _T_970 & _T_804; // @[dec_tlu_ctl.scala 2241:111] + wire _T_981 = _T_970 & _T_813; // @[dec_tlu_ctl.scala 2241:111] + wire _T_990 = _T_970 & _T_822; // @[dec_tlu_ctl.scala 2241:111] + wire _T_999 = _T_970 & _T_831; // @[dec_tlu_ctl.scala 2241:111] reg [31:0] mtdata2_t_0; // @[lib.scala 374:16] reg [31:0] mtdata2_t_1; // @[lib.scala 374:16] reg [31:0] mtdata2_t_2; // @[lib.scala 374:16] reg [31:0] mtdata2_t_3; // @[lib.scala 374:16] - wire [31:0] _T_1006 = _T_794 ? mtdata2_t_0 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_1007 = _T_803 ? mtdata2_t_1 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_1008 = _T_812 ? mtdata2_t_2 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_1009 = _T_821 ? mtdata2_t_3 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_1010 = _T_1006 | _T_1007; // @[Mux.scala 27:72] - wire [31:0] _T_1011 = _T_1010 | _T_1008; // @[Mux.scala 27:72] - wire [31:0] mtdata2_tsel_out = _T_1011 | _T_1009; // @[Mux.scala 27:72] - wire [3:0] _T_1014 = io_tlu_i0_commit_cmt ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] pmu_i0_itype_qual = io_dec_tlu_packet_r_pmu_i0_itype & _T_1014; // @[dec_tlu_ctl.scala 2268:59] - wire _T_1016 = ~mcountinhibit[3]; // @[dec_tlu_ctl.scala 2274:24] + wire [31:0] _T_1016 = _T_804 ? mtdata2_t_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1017 = _T_813 ? mtdata2_t_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1018 = _T_822 ? mtdata2_t_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1019 = _T_831 ? mtdata2_t_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1020 = _T_1016 | _T_1017; // @[Mux.scala 27:72] + wire [31:0] _T_1021 = _T_1020 | _T_1018; // @[Mux.scala 27:72] + wire [31:0] mtdata2_tsel_out = _T_1021 | _T_1019; // @[Mux.scala 27:72] + wire [3:0] _T_1024 = io_tlu_i0_commit_cmt ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] pmu_i0_itype_qual = io_dec_tlu_packet_r_pmu_i0_itype & _T_1024; // @[dec_tlu_ctl.scala 2266:59] + wire _T_1026 = ~mcountinhibit[3]; // @[dec_tlu_ctl.scala 2272:24] reg [9:0] mhpme3; // @[Reg.scala 27:20] - wire _T_1017 = mhpme3 == 10'h1; // @[dec_tlu_ctl.scala 2275:34] - wire _T_1019 = mhpme3 == 10'h2; // @[dec_tlu_ctl.scala 2276:34] - wire _T_1021 = mhpme3 == 10'h3; // @[dec_tlu_ctl.scala 2277:34] - wire _T_1023 = mhpme3 == 10'h4; // @[dec_tlu_ctl.scala 2278:34] - wire _T_1025 = ~io_illegal_r; // @[dec_tlu_ctl.scala 2278:96] - wire _T_1026 = io_tlu_i0_commit_cmt & _T_1025; // @[dec_tlu_ctl.scala 2278:94] - wire _T_1027 = mhpme3 == 10'h5; // @[dec_tlu_ctl.scala 2279:34] - wire _T_1029 = ~io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2279:96] - wire _T_1030 = io_tlu_i0_commit_cmt & _T_1029; // @[dec_tlu_ctl.scala 2279:94] - wire _T_1032 = _T_1030 & _T_1025; // @[dec_tlu_ctl.scala 2279:115] - wire _T_1033 = mhpme3 == 10'h6; // @[dec_tlu_ctl.scala 2280:34] - wire _T_1035 = io_tlu_i0_commit_cmt & io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2280:94] - wire _T_1037 = _T_1035 & _T_1025; // @[dec_tlu_ctl.scala 2280:115] - wire _T_1038 = mhpme3 == 10'h7; // @[dec_tlu_ctl.scala 2281:34] - wire _T_1040 = mhpme3 == 10'h8; // @[dec_tlu_ctl.scala 2282:34] - wire _T_1042 = mhpme3 == 10'h1e; // @[dec_tlu_ctl.scala 2283:34] - wire _T_1044 = mhpme3 == 10'h9; // @[dec_tlu_ctl.scala 2284:34] - wire _T_1046 = pmu_i0_itype_qual == 4'h1; // @[dec_tlu_ctl.scala 2284:91] - wire _T_1047 = mhpme3 == 10'ha; // @[dec_tlu_ctl.scala 2285:34] - wire _T_1049 = io_dec_tlu_packet_r_pmu_divide & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2285:105] - wire _T_1050 = mhpme3 == 10'hb; // @[dec_tlu_ctl.scala 2286:34] - wire _T_1052 = pmu_i0_itype_qual == 4'h2; // @[dec_tlu_ctl.scala 2286:91] - wire _T_1053 = mhpme3 == 10'hc; // @[dec_tlu_ctl.scala 2287:34] - wire _T_1055 = pmu_i0_itype_qual == 4'h3; // @[dec_tlu_ctl.scala 2287:91] - wire _T_1056 = mhpme3 == 10'hd; // @[dec_tlu_ctl.scala 2288:34] - wire _T_1059 = _T_1052 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2288:100] - wire _T_1060 = mhpme3 == 10'he; // @[dec_tlu_ctl.scala 2289:34] - wire _T_1064 = _T_1055 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2289:101] - wire _T_1065 = mhpme3 == 10'hf; // @[dec_tlu_ctl.scala 2290:34] - wire _T_1067 = pmu_i0_itype_qual == 4'h4; // @[dec_tlu_ctl.scala 2290:89] - wire _T_1068 = mhpme3 == 10'h10; // @[dec_tlu_ctl.scala 2291:34] - wire _T_1070 = pmu_i0_itype_qual == 4'h5; // @[dec_tlu_ctl.scala 2291:89] - wire _T_1071 = mhpme3 == 10'h12; // @[dec_tlu_ctl.scala 2292:34] - wire _T_1073 = pmu_i0_itype_qual == 4'h6; // @[dec_tlu_ctl.scala 2292:89] - wire _T_1074 = mhpme3 == 10'h11; // @[dec_tlu_ctl.scala 2293:34] - wire _T_1076 = pmu_i0_itype_qual == 4'h7; // @[dec_tlu_ctl.scala 2293:89] - wire _T_1077 = mhpme3 == 10'h13; // @[dec_tlu_ctl.scala 2294:34] - wire _T_1079 = pmu_i0_itype_qual == 4'h8; // @[dec_tlu_ctl.scala 2294:89] - wire _T_1080 = mhpme3 == 10'h14; // @[dec_tlu_ctl.scala 2295:34] - wire _T_1082 = pmu_i0_itype_qual == 4'h9; // @[dec_tlu_ctl.scala 2295:89] - wire _T_1083 = mhpme3 == 10'h15; // @[dec_tlu_ctl.scala 2296:34] - wire _T_1085 = pmu_i0_itype_qual == 4'ha; // @[dec_tlu_ctl.scala 2296:89] - wire _T_1086 = mhpme3 == 10'h16; // @[dec_tlu_ctl.scala 2297:34] - wire _T_1088 = pmu_i0_itype_qual == 4'hb; // @[dec_tlu_ctl.scala 2297:89] - wire _T_1089 = mhpme3 == 10'h17; // @[dec_tlu_ctl.scala 2298:34] - wire _T_1091 = pmu_i0_itype_qual == 4'hc; // @[dec_tlu_ctl.scala 2298:89] - wire _T_1092 = mhpme3 == 10'h18; // @[dec_tlu_ctl.scala 2299:34] - wire _T_1094 = pmu_i0_itype_qual == 4'hd; // @[dec_tlu_ctl.scala 2299:89] - wire _T_1095 = pmu_i0_itype_qual == 4'he; // @[dec_tlu_ctl.scala 2299:122] - wire _T_1096 = _T_1094 | _T_1095; // @[dec_tlu_ctl.scala 2299:101] - wire _T_1097 = mhpme3 == 10'h19; // @[dec_tlu_ctl.scala 2300:34] - wire _T_1099 = io_exu_pmu_i0_br_misp & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2300:95] - wire _T_1100 = mhpme3 == 10'h1a; // @[dec_tlu_ctl.scala 2301:34] - wire _T_1102 = io_exu_pmu_i0_br_ataken & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2301:97] - wire _T_1103 = mhpme3 == 10'h1b; // @[dec_tlu_ctl.scala 2302:34] - wire _T_1105 = io_dec_tlu_packet_r_pmu_i0_br_unpred & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2302:110] - wire _T_1106 = mhpme3 == 10'h1c; // @[dec_tlu_ctl.scala 2303:34] - wire _T_1110 = mhpme3 == 10'h1f; // @[dec_tlu_ctl.scala 2305:34] - wire _T_1112 = mhpme3 == 10'h20; // @[dec_tlu_ctl.scala 2306:34] - wire _T_1114 = mhpme3 == 10'h22; // @[dec_tlu_ctl.scala 2307:34] - wire _T_1116 = mhpme3 == 10'h23; // @[dec_tlu_ctl.scala 2308:34] - wire _T_1118 = mhpme3 == 10'h24; // @[dec_tlu_ctl.scala 2309:34] - wire _T_1120 = mhpme3 == 10'h25; // @[dec_tlu_ctl.scala 2310:34] - wire _T_1122 = io_i0_exception_valid_r | io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 2310:98] - wire _T_1123 = _T_1122 | io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 2310:120] - wire _T_1124 = mhpme3 == 10'h26; // @[dec_tlu_ctl.scala 2311:34] - wire _T_1126 = io_take_timer_int | io_take_int_timer0_int; // @[dec_tlu_ctl.scala 2311:92] - wire _T_1127 = _T_1126 | io_take_int_timer1_int; // @[dec_tlu_ctl.scala 2311:117] - wire _T_1128 = mhpme3 == 10'h27; // @[dec_tlu_ctl.scala 2312:34] - wire _T_1130 = mhpme3 == 10'h28; // @[dec_tlu_ctl.scala 2313:34] - wire _T_1132 = mhpme3 == 10'h29; // @[dec_tlu_ctl.scala 2314:34] - wire _T_1134 = io_dec_tlu_br0_error_r | io_dec_tlu_br0_start_error_r; // @[dec_tlu_ctl.scala 2314:97] - wire _T_1135 = _T_1134 & io_rfpc_i0_r; // @[dec_tlu_ctl.scala 2314:129] - wire _T_1136 = mhpme3 == 10'h2a; // @[dec_tlu_ctl.scala 2315:34] - wire _T_1138 = mhpme3 == 10'h2b; // @[dec_tlu_ctl.scala 2316:34] - wire _T_1140 = mhpme3 == 10'h2c; // @[dec_tlu_ctl.scala 2317:34] - wire _T_1142 = mhpme3 == 10'h2d; // @[dec_tlu_ctl.scala 2318:34] - wire _T_1144 = mhpme3 == 10'h2e; // @[dec_tlu_ctl.scala 2319:34] - wire _T_1146 = mhpme3 == 10'h2f; // @[dec_tlu_ctl.scala 2320:34] - wire _T_1148 = mhpme3 == 10'h30; // @[dec_tlu_ctl.scala 2321:34] - wire _T_1150 = mhpme3 == 10'h31; // @[dec_tlu_ctl.scala 2322:34] - wire _T_1154 = ~io_mstatus[0]; // @[dec_tlu_ctl.scala 2322:73] - wire _T_1155 = mhpme3 == 10'h32; // @[dec_tlu_ctl.scala 2323:34] - wire [5:0] _T_1162 = io_mip & mie; // @[dec_tlu_ctl.scala 2323:113] - wire _T_1163 = |_T_1162; // @[dec_tlu_ctl.scala 2323:125] - wire _T_1164 = _T_1154 & _T_1163; // @[dec_tlu_ctl.scala 2323:98] - wire _T_1165 = mhpme3 == 10'h36; // @[dec_tlu_ctl.scala 2324:34] - wire _T_1167 = pmu_i0_itype_qual == 4'hf; // @[dec_tlu_ctl.scala 2324:91] - wire _T_1168 = mhpme3 == 10'h37; // @[dec_tlu_ctl.scala 2325:34] - wire _T_1170 = io_tlu_i0_commit_cmt & io_lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 2325:94] - wire _T_1171 = mhpme3 == 10'h38; // @[dec_tlu_ctl.scala 2326:34] - wire _T_1173 = io_tlu_i0_commit_cmt & io_lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 2326:94] - wire _T_1174 = mhpme3 == 10'h200; // @[dec_tlu_ctl.scala 2328:34] - wire _T_1176 = mhpme3 == 10'h201; // @[dec_tlu_ctl.scala 2329:34] - wire _T_1178 = mhpme3 == 10'h202; // @[dec_tlu_ctl.scala 2330:34] - wire _T_1180 = mhpme3 == 10'h203; // @[dec_tlu_ctl.scala 2331:34] - wire _T_1182 = mhpme3 == 10'h204; // @[dec_tlu_ctl.scala 2332:34] - wire _T_1185 = _T_1019 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] - wire _T_1186 = _T_1021 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] - wire _T_1187 = _T_1023 & _T_1026; // @[Mux.scala 27:72] - wire _T_1188 = _T_1027 & _T_1032; // @[Mux.scala 27:72] - wire _T_1189 = _T_1033 & _T_1037; // @[Mux.scala 27:72] - wire _T_1190 = _T_1038 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] - wire _T_1191 = _T_1040 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] - wire _T_1192 = _T_1042 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] - wire _T_1193 = _T_1044 & _T_1046; // @[Mux.scala 27:72] - wire _T_1194 = _T_1047 & _T_1049; // @[Mux.scala 27:72] - wire _T_1195 = _T_1050 & _T_1052; // @[Mux.scala 27:72] - wire _T_1196 = _T_1053 & _T_1055; // @[Mux.scala 27:72] - wire _T_1197 = _T_1056 & _T_1059; // @[Mux.scala 27:72] - wire _T_1198 = _T_1060 & _T_1064; // @[Mux.scala 27:72] - wire _T_1199 = _T_1065 & _T_1067; // @[Mux.scala 27:72] - wire _T_1200 = _T_1068 & _T_1070; // @[Mux.scala 27:72] - wire _T_1201 = _T_1071 & _T_1073; // @[Mux.scala 27:72] - wire _T_1202 = _T_1074 & _T_1076; // @[Mux.scala 27:72] - wire _T_1203 = _T_1077 & _T_1079; // @[Mux.scala 27:72] - wire _T_1204 = _T_1080 & _T_1082; // @[Mux.scala 27:72] - wire _T_1205 = _T_1083 & _T_1085; // @[Mux.scala 27:72] - wire _T_1206 = _T_1086 & _T_1088; // @[Mux.scala 27:72] - wire _T_1207 = _T_1089 & _T_1091; // @[Mux.scala 27:72] - wire _T_1208 = _T_1092 & _T_1096; // @[Mux.scala 27:72] - wire _T_1209 = _T_1097 & _T_1099; // @[Mux.scala 27:72] - wire _T_1210 = _T_1100 & _T_1102; // @[Mux.scala 27:72] - wire _T_1211 = _T_1103 & _T_1105; // @[Mux.scala 27:72] - wire _T_1212 = _T_1106 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] - wire _T_1214 = _T_1110 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] - wire _T_1215 = _T_1112 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] - wire _T_1216 = _T_1114 & io_lsu_store_stall_any; // @[Mux.scala 27:72] - wire _T_1217 = _T_1116 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] - wire _T_1218 = _T_1118 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] - wire _T_1219 = _T_1120 & _T_1123; // @[Mux.scala 27:72] - wire _T_1220 = _T_1124 & _T_1127; // @[Mux.scala 27:72] - wire _T_1221 = _T_1128 & io_take_ext_int; // @[Mux.scala 27:72] - wire _T_1222 = _T_1130 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] - wire _T_1223 = _T_1132 & _T_1135; // @[Mux.scala 27:72] - wire _T_1224 = _T_1136 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1225 = _T_1138 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1226 = _T_1140 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] - wire _T_1227 = _T_1142 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1228 = _T_1144 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1229 = _T_1146 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1230 = _T_1148 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1231 = _T_1150 & _T_1154; // @[Mux.scala 27:72] - wire _T_1232 = _T_1155 & _T_1164; // @[Mux.scala 27:72] - wire _T_1233 = _T_1165 & _T_1167; // @[Mux.scala 27:72] - wire _T_1234 = _T_1168 & _T_1170; // @[Mux.scala 27:72] - wire _T_1235 = _T_1171 & _T_1173; // @[Mux.scala 27:72] - wire _T_1236 = _T_1174 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] - wire _T_1237 = _T_1176 & io_dma_pmu_any_read; // @[Mux.scala 27:72] - wire _T_1238 = _T_1178 & io_dma_pmu_any_write; // @[Mux.scala 27:72] - wire _T_1239 = _T_1180 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] - wire _T_1240 = _T_1182 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] - wire _T_1241 = _T_1017 | _T_1185; // @[Mux.scala 27:72] - wire _T_1242 = _T_1241 | _T_1186; // @[Mux.scala 27:72] - wire _T_1243 = _T_1242 | _T_1187; // @[Mux.scala 27:72] - wire _T_1244 = _T_1243 | _T_1188; // @[Mux.scala 27:72] - wire _T_1245 = _T_1244 | _T_1189; // @[Mux.scala 27:72] - wire _T_1246 = _T_1245 | _T_1190; // @[Mux.scala 27:72] - wire _T_1247 = _T_1246 | _T_1191; // @[Mux.scala 27:72] - wire _T_1248 = _T_1247 | _T_1192; // @[Mux.scala 27:72] - wire _T_1249 = _T_1248 | _T_1193; // @[Mux.scala 27:72] - wire _T_1250 = _T_1249 | _T_1194; // @[Mux.scala 27:72] - wire _T_1251 = _T_1250 | _T_1195; // @[Mux.scala 27:72] + wire _T_1027 = mhpme3 == 10'h1; // @[dec_tlu_ctl.scala 2273:34] + wire _T_1029 = mhpme3 == 10'h2; // @[dec_tlu_ctl.scala 2274:34] + wire _T_1031 = mhpme3 == 10'h3; // @[dec_tlu_ctl.scala 2275:34] + wire _T_1033 = mhpme3 == 10'h4; // @[dec_tlu_ctl.scala 2276:34] + wire _T_1035 = ~io_illegal_r; // @[dec_tlu_ctl.scala 2276:96] + wire _T_1036 = io_tlu_i0_commit_cmt & _T_1035; // @[dec_tlu_ctl.scala 2276:94] + wire _T_1037 = mhpme3 == 10'h5; // @[dec_tlu_ctl.scala 2277:34] + wire _T_1039 = ~io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2277:96] + wire _T_1040 = io_tlu_i0_commit_cmt & _T_1039; // @[dec_tlu_ctl.scala 2277:94] + wire _T_1042 = _T_1040 & _T_1035; // @[dec_tlu_ctl.scala 2277:115] + wire _T_1043 = mhpme3 == 10'h6; // @[dec_tlu_ctl.scala 2278:34] + wire _T_1045 = io_tlu_i0_commit_cmt & io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2278:94] + wire _T_1047 = _T_1045 & _T_1035; // @[dec_tlu_ctl.scala 2278:115] + wire _T_1048 = mhpme3 == 10'h7; // @[dec_tlu_ctl.scala 2279:34] + wire _T_1050 = mhpme3 == 10'h8; // @[dec_tlu_ctl.scala 2280:34] + wire _T_1052 = mhpme3 == 10'h1e; // @[dec_tlu_ctl.scala 2281:34] + wire _T_1054 = mhpme3 == 10'h9; // @[dec_tlu_ctl.scala 2282:34] + wire _T_1056 = pmu_i0_itype_qual == 4'h1; // @[dec_tlu_ctl.scala 2282:91] + wire _T_1057 = mhpme3 == 10'ha; // @[dec_tlu_ctl.scala 2283:34] + wire _T_1059 = io_dec_tlu_packet_r_pmu_divide & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2283:105] + wire _T_1060 = mhpme3 == 10'hb; // @[dec_tlu_ctl.scala 2284:34] + wire _T_1062 = pmu_i0_itype_qual == 4'h2; // @[dec_tlu_ctl.scala 2284:91] + wire _T_1063 = mhpme3 == 10'hc; // @[dec_tlu_ctl.scala 2285:34] + wire _T_1065 = pmu_i0_itype_qual == 4'h3; // @[dec_tlu_ctl.scala 2285:91] + wire _T_1066 = mhpme3 == 10'hd; // @[dec_tlu_ctl.scala 2286:34] + wire _T_1069 = _T_1062 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2286:100] + wire _T_1070 = mhpme3 == 10'he; // @[dec_tlu_ctl.scala 2287:34] + wire _T_1074 = _T_1065 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2287:101] + wire _T_1075 = mhpme3 == 10'hf; // @[dec_tlu_ctl.scala 2288:34] + wire _T_1077 = pmu_i0_itype_qual == 4'h4; // @[dec_tlu_ctl.scala 2288:89] + wire _T_1078 = mhpme3 == 10'h10; // @[dec_tlu_ctl.scala 2289:34] + wire _T_1080 = pmu_i0_itype_qual == 4'h5; // @[dec_tlu_ctl.scala 2289:89] + wire _T_1081 = mhpme3 == 10'h12; // @[dec_tlu_ctl.scala 2290:34] + wire _T_1083 = pmu_i0_itype_qual == 4'h6; // @[dec_tlu_ctl.scala 2290:89] + wire _T_1084 = mhpme3 == 10'h11; // @[dec_tlu_ctl.scala 2291:34] + wire _T_1086 = pmu_i0_itype_qual == 4'h7; // @[dec_tlu_ctl.scala 2291:89] + wire _T_1087 = mhpme3 == 10'h13; // @[dec_tlu_ctl.scala 2292:34] + wire _T_1089 = pmu_i0_itype_qual == 4'h8; // @[dec_tlu_ctl.scala 2292:89] + wire _T_1090 = mhpme3 == 10'h14; // @[dec_tlu_ctl.scala 2293:34] + wire _T_1092 = pmu_i0_itype_qual == 4'h9; // @[dec_tlu_ctl.scala 2293:89] + wire _T_1093 = mhpme3 == 10'h15; // @[dec_tlu_ctl.scala 2294:34] + wire _T_1095 = pmu_i0_itype_qual == 4'ha; // @[dec_tlu_ctl.scala 2294:89] + wire _T_1096 = mhpme3 == 10'h16; // @[dec_tlu_ctl.scala 2295:34] + wire _T_1098 = pmu_i0_itype_qual == 4'hb; // @[dec_tlu_ctl.scala 2295:89] + wire _T_1099 = mhpme3 == 10'h17; // @[dec_tlu_ctl.scala 2296:34] + wire _T_1101 = pmu_i0_itype_qual == 4'hc; // @[dec_tlu_ctl.scala 2296:89] + wire _T_1102 = mhpme3 == 10'h18; // @[dec_tlu_ctl.scala 2297:34] + wire _T_1104 = pmu_i0_itype_qual == 4'hd; // @[dec_tlu_ctl.scala 2297:89] + wire _T_1105 = pmu_i0_itype_qual == 4'he; // @[dec_tlu_ctl.scala 2297:122] + wire _T_1106 = _T_1104 | _T_1105; // @[dec_tlu_ctl.scala 2297:101] + wire _T_1107 = mhpme3 == 10'h19; // @[dec_tlu_ctl.scala 2298:34] + wire _T_1109 = io_exu_pmu_i0_br_misp & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2298:95] + wire _T_1110 = mhpme3 == 10'h1a; // @[dec_tlu_ctl.scala 2299:34] + wire _T_1112 = io_exu_pmu_i0_br_ataken & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2299:97] + wire _T_1113 = mhpme3 == 10'h1b; // @[dec_tlu_ctl.scala 2300:34] + wire _T_1115 = io_dec_tlu_packet_r_pmu_i0_br_unpred & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2300:110] + wire _T_1116 = mhpme3 == 10'h1c; // @[dec_tlu_ctl.scala 2301:34] + wire _T_1120 = mhpme3 == 10'h1f; // @[dec_tlu_ctl.scala 2303:34] + wire _T_1122 = mhpme3 == 10'h20; // @[dec_tlu_ctl.scala 2304:34] + wire _T_1124 = mhpme3 == 10'h22; // @[dec_tlu_ctl.scala 2305:34] + wire _T_1126 = mhpme3 == 10'h23; // @[dec_tlu_ctl.scala 2306:34] + wire _T_1128 = mhpme3 == 10'h24; // @[dec_tlu_ctl.scala 2307:34] + wire _T_1130 = mhpme3 == 10'h25; // @[dec_tlu_ctl.scala 2308:34] + wire _T_1132 = io_i0_exception_valid_r | io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 2308:98] + wire _T_1133 = _T_1132 | io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 2308:120] + wire _T_1134 = mhpme3 == 10'h26; // @[dec_tlu_ctl.scala 2309:34] + wire _T_1136 = io_take_timer_int | io_take_int_timer0_int; // @[dec_tlu_ctl.scala 2309:92] + wire _T_1137 = _T_1136 | io_take_int_timer1_int; // @[dec_tlu_ctl.scala 2309:117] + wire _T_1138 = mhpme3 == 10'h27; // @[dec_tlu_ctl.scala 2310:34] + wire _T_1140 = mhpme3 == 10'h28; // @[dec_tlu_ctl.scala 2311:34] + wire _T_1142 = mhpme3 == 10'h29; // @[dec_tlu_ctl.scala 2312:34] + wire _T_1144 = io_dec_tlu_br0_error_r | io_dec_tlu_br0_start_error_r; // @[dec_tlu_ctl.scala 2312:97] + wire _T_1145 = _T_1144 & io_rfpc_i0_r; // @[dec_tlu_ctl.scala 2312:129] + wire _T_1146 = mhpme3 == 10'h2a; // @[dec_tlu_ctl.scala 2313:34] + wire _T_1148 = mhpme3 == 10'h2b; // @[dec_tlu_ctl.scala 2314:34] + wire _T_1150 = mhpme3 == 10'h2c; // @[dec_tlu_ctl.scala 2315:34] + wire _T_1152 = mhpme3 == 10'h2d; // @[dec_tlu_ctl.scala 2316:34] + wire _T_1154 = mhpme3 == 10'h2e; // @[dec_tlu_ctl.scala 2317:34] + wire _T_1156 = mhpme3 == 10'h2f; // @[dec_tlu_ctl.scala 2318:34] + wire _T_1158 = mhpme3 == 10'h30; // @[dec_tlu_ctl.scala 2319:34] + wire _T_1160 = mhpme3 == 10'h31; // @[dec_tlu_ctl.scala 2320:34] + wire _T_1164 = ~io_mstatus[0]; // @[dec_tlu_ctl.scala 2320:73] + wire _T_1165 = mhpme3 == 10'h32; // @[dec_tlu_ctl.scala 2321:34] + wire [5:0] _T_1172 = io_mip & mie; // @[dec_tlu_ctl.scala 2321:113] + wire _T_1173 = |_T_1172; // @[dec_tlu_ctl.scala 2321:125] + wire _T_1174 = _T_1164 & _T_1173; // @[dec_tlu_ctl.scala 2321:98] + wire _T_1175 = mhpme3 == 10'h36; // @[dec_tlu_ctl.scala 2322:34] + wire _T_1177 = pmu_i0_itype_qual == 4'hf; // @[dec_tlu_ctl.scala 2322:91] + wire _T_1178 = mhpme3 == 10'h37; // @[dec_tlu_ctl.scala 2323:34] + wire _T_1180 = io_tlu_i0_commit_cmt & io_lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 2323:94] + wire _T_1181 = mhpme3 == 10'h38; // @[dec_tlu_ctl.scala 2324:34] + wire _T_1183 = io_tlu_i0_commit_cmt & io_lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 2324:94] + wire _T_1184 = mhpme3 == 10'h200; // @[dec_tlu_ctl.scala 2326:34] + wire _T_1186 = mhpme3 == 10'h201; // @[dec_tlu_ctl.scala 2327:34] + wire _T_1188 = mhpme3 == 10'h202; // @[dec_tlu_ctl.scala 2328:34] + wire _T_1190 = mhpme3 == 10'h203; // @[dec_tlu_ctl.scala 2329:34] + wire _T_1192 = mhpme3 == 10'h204; // @[dec_tlu_ctl.scala 2330:34] + wire _T_1195 = _T_1029 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_1196 = _T_1031 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_1197 = _T_1033 & _T_1036; // @[Mux.scala 27:72] + wire _T_1198 = _T_1037 & _T_1042; // @[Mux.scala 27:72] + wire _T_1199 = _T_1043 & _T_1047; // @[Mux.scala 27:72] + wire _T_1200 = _T_1048 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_1201 = _T_1050 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_1202 = _T_1052 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_1203 = _T_1054 & _T_1056; // @[Mux.scala 27:72] + wire _T_1204 = _T_1057 & _T_1059; // @[Mux.scala 27:72] + wire _T_1205 = _T_1060 & _T_1062; // @[Mux.scala 27:72] + wire _T_1206 = _T_1063 & _T_1065; // @[Mux.scala 27:72] + wire _T_1207 = _T_1066 & _T_1069; // @[Mux.scala 27:72] + wire _T_1208 = _T_1070 & _T_1074; // @[Mux.scala 27:72] + wire _T_1209 = _T_1075 & _T_1077; // @[Mux.scala 27:72] + wire _T_1210 = _T_1078 & _T_1080; // @[Mux.scala 27:72] + wire _T_1211 = _T_1081 & _T_1083; // @[Mux.scala 27:72] + wire _T_1212 = _T_1084 & _T_1086; // @[Mux.scala 27:72] + wire _T_1213 = _T_1087 & _T_1089; // @[Mux.scala 27:72] + wire _T_1214 = _T_1090 & _T_1092; // @[Mux.scala 27:72] + wire _T_1215 = _T_1093 & _T_1095; // @[Mux.scala 27:72] + wire _T_1216 = _T_1096 & _T_1098; // @[Mux.scala 27:72] + wire _T_1217 = _T_1099 & _T_1101; // @[Mux.scala 27:72] + wire _T_1218 = _T_1102 & _T_1106; // @[Mux.scala 27:72] + wire _T_1219 = _T_1107 & _T_1109; // @[Mux.scala 27:72] + wire _T_1220 = _T_1110 & _T_1112; // @[Mux.scala 27:72] + wire _T_1221 = _T_1113 & _T_1115; // @[Mux.scala 27:72] + wire _T_1222 = _T_1116 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_1224 = _T_1120 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_1225 = _T_1122 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_1226 = _T_1124 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_1227 = _T_1126 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_1228 = _T_1128 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_1229 = _T_1130 & _T_1133; // @[Mux.scala 27:72] + wire _T_1230 = _T_1134 & _T_1137; // @[Mux.scala 27:72] + wire _T_1231 = _T_1138 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_1232 = _T_1140 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_1233 = _T_1142 & _T_1145; // @[Mux.scala 27:72] + wire _T_1234 = _T_1146 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1235 = _T_1148 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1236 = _T_1150 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_1237 = _T_1152 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1238 = _T_1154 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1239 = _T_1156 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1240 = _T_1158 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1241 = _T_1160 & _T_1164; // @[Mux.scala 27:72] + wire _T_1242 = _T_1165 & _T_1174; // @[Mux.scala 27:72] + wire _T_1243 = _T_1175 & _T_1177; // @[Mux.scala 27:72] + wire _T_1244 = _T_1178 & _T_1180; // @[Mux.scala 27:72] + wire _T_1245 = _T_1181 & _T_1183; // @[Mux.scala 27:72] + wire _T_1246 = _T_1184 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_1247 = _T_1186 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_1248 = _T_1188 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_1249 = _T_1190 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_1250 = _T_1192 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_1251 = _T_1027 | _T_1195; // @[Mux.scala 27:72] wire _T_1252 = _T_1251 | _T_1196; // @[Mux.scala 27:72] wire _T_1253 = _T_1252 | _T_1197; // @[Mux.scala 27:72] wire _T_1254 = _T_1253 | _T_1198; // @[Mux.scala 27:72] @@ -51614,7 +51615,7 @@ module csr_tlu( wire _T_1266 = _T_1265 | _T_1210; // @[Mux.scala 27:72] wire _T_1267 = _T_1266 | _T_1211; // @[Mux.scala 27:72] wire _T_1268 = _T_1267 | _T_1212; // @[Mux.scala 27:72] - wire _T_1269 = _T_1268 | _T_1192; // @[Mux.scala 27:72] + wire _T_1269 = _T_1268 | _T_1213; // @[Mux.scala 27:72] wire _T_1270 = _T_1269 | _T_1214; // @[Mux.scala 27:72] wire _T_1271 = _T_1270 | _T_1215; // @[Mux.scala 27:72] wire _T_1272 = _T_1271 | _T_1216; // @[Mux.scala 27:72] @@ -51624,7 +51625,7 @@ module csr_tlu( wire _T_1276 = _T_1275 | _T_1220; // @[Mux.scala 27:72] wire _T_1277 = _T_1276 | _T_1221; // @[Mux.scala 27:72] wire _T_1278 = _T_1277 | _T_1222; // @[Mux.scala 27:72] - wire _T_1279 = _T_1278 | _T_1223; // @[Mux.scala 27:72] + wire _T_1279 = _T_1278 | _T_1202; // @[Mux.scala 27:72] wire _T_1280 = _T_1279 | _T_1224; // @[Mux.scala 27:72] wire _T_1281 = _T_1280 | _T_1225; // @[Mux.scala 27:72] wire _T_1282 = _T_1281 | _T_1226; // @[Mux.scala 27:72] @@ -51642,131 +51643,131 @@ module csr_tlu( wire _T_1294 = _T_1293 | _T_1238; // @[Mux.scala 27:72] wire _T_1295 = _T_1294 | _T_1239; // @[Mux.scala 27:72] wire _T_1296 = _T_1295 | _T_1240; // @[Mux.scala 27:72] - wire mhpmc_inc_r_0 = _T_1016 & _T_1296; // @[dec_tlu_ctl.scala 2274:44] - wire _T_1300 = ~mcountinhibit[4]; // @[dec_tlu_ctl.scala 2274:24] + wire _T_1297 = _T_1296 | _T_1241; // @[Mux.scala 27:72] + wire _T_1298 = _T_1297 | _T_1242; // @[Mux.scala 27:72] + wire _T_1299 = _T_1298 | _T_1243; // @[Mux.scala 27:72] + wire _T_1300 = _T_1299 | _T_1244; // @[Mux.scala 27:72] + wire _T_1301 = _T_1300 | _T_1245; // @[Mux.scala 27:72] + wire _T_1302 = _T_1301 | _T_1246; // @[Mux.scala 27:72] + wire _T_1303 = _T_1302 | _T_1247; // @[Mux.scala 27:72] + wire _T_1304 = _T_1303 | _T_1248; // @[Mux.scala 27:72] + wire _T_1305 = _T_1304 | _T_1249; // @[Mux.scala 27:72] + wire _T_1306 = _T_1305 | _T_1250; // @[Mux.scala 27:72] + wire mhpmc_inc_r_0 = _T_1026 & _T_1306; // @[dec_tlu_ctl.scala 2272:44] + wire _T_1310 = ~mcountinhibit[4]; // @[dec_tlu_ctl.scala 2272:24] reg [9:0] mhpme4; // @[Reg.scala 27:20] - wire _T_1301 = mhpme4 == 10'h1; // @[dec_tlu_ctl.scala 2275:34] - wire _T_1303 = mhpme4 == 10'h2; // @[dec_tlu_ctl.scala 2276:34] - wire _T_1305 = mhpme4 == 10'h3; // @[dec_tlu_ctl.scala 2277:34] - wire _T_1307 = mhpme4 == 10'h4; // @[dec_tlu_ctl.scala 2278:34] - wire _T_1311 = mhpme4 == 10'h5; // @[dec_tlu_ctl.scala 2279:34] - wire _T_1317 = mhpme4 == 10'h6; // @[dec_tlu_ctl.scala 2280:34] - wire _T_1322 = mhpme4 == 10'h7; // @[dec_tlu_ctl.scala 2281:34] - wire _T_1324 = mhpme4 == 10'h8; // @[dec_tlu_ctl.scala 2282:34] - wire _T_1326 = mhpme4 == 10'h1e; // @[dec_tlu_ctl.scala 2283:34] - wire _T_1328 = mhpme4 == 10'h9; // @[dec_tlu_ctl.scala 2284:34] - wire _T_1331 = mhpme4 == 10'ha; // @[dec_tlu_ctl.scala 2285:34] - wire _T_1334 = mhpme4 == 10'hb; // @[dec_tlu_ctl.scala 2286:34] - wire _T_1337 = mhpme4 == 10'hc; // @[dec_tlu_ctl.scala 2287:34] - wire _T_1340 = mhpme4 == 10'hd; // @[dec_tlu_ctl.scala 2288:34] - wire _T_1344 = mhpme4 == 10'he; // @[dec_tlu_ctl.scala 2289:34] - wire _T_1349 = mhpme4 == 10'hf; // @[dec_tlu_ctl.scala 2290:34] - wire _T_1352 = mhpme4 == 10'h10; // @[dec_tlu_ctl.scala 2291:34] - wire _T_1355 = mhpme4 == 10'h12; // @[dec_tlu_ctl.scala 2292:34] - wire _T_1358 = mhpme4 == 10'h11; // @[dec_tlu_ctl.scala 2293:34] - wire _T_1361 = mhpme4 == 10'h13; // @[dec_tlu_ctl.scala 2294:34] - wire _T_1364 = mhpme4 == 10'h14; // @[dec_tlu_ctl.scala 2295:34] - wire _T_1367 = mhpme4 == 10'h15; // @[dec_tlu_ctl.scala 2296:34] - wire _T_1370 = mhpme4 == 10'h16; // @[dec_tlu_ctl.scala 2297:34] - wire _T_1373 = mhpme4 == 10'h17; // @[dec_tlu_ctl.scala 2298:34] - wire _T_1376 = mhpme4 == 10'h18; // @[dec_tlu_ctl.scala 2299:34] - wire _T_1381 = mhpme4 == 10'h19; // @[dec_tlu_ctl.scala 2300:34] - wire _T_1384 = mhpme4 == 10'h1a; // @[dec_tlu_ctl.scala 2301:34] - wire _T_1387 = mhpme4 == 10'h1b; // @[dec_tlu_ctl.scala 2302:34] - wire _T_1390 = mhpme4 == 10'h1c; // @[dec_tlu_ctl.scala 2303:34] - wire _T_1394 = mhpme4 == 10'h1f; // @[dec_tlu_ctl.scala 2305:34] - wire _T_1396 = mhpme4 == 10'h20; // @[dec_tlu_ctl.scala 2306:34] - wire _T_1398 = mhpme4 == 10'h22; // @[dec_tlu_ctl.scala 2307:34] - wire _T_1400 = mhpme4 == 10'h23; // @[dec_tlu_ctl.scala 2308:34] - wire _T_1402 = mhpme4 == 10'h24; // @[dec_tlu_ctl.scala 2309:34] - wire _T_1404 = mhpme4 == 10'h25; // @[dec_tlu_ctl.scala 2310:34] - wire _T_1408 = mhpme4 == 10'h26; // @[dec_tlu_ctl.scala 2311:34] - wire _T_1412 = mhpme4 == 10'h27; // @[dec_tlu_ctl.scala 2312:34] - wire _T_1414 = mhpme4 == 10'h28; // @[dec_tlu_ctl.scala 2313:34] - wire _T_1416 = mhpme4 == 10'h29; // @[dec_tlu_ctl.scala 2314:34] - wire _T_1420 = mhpme4 == 10'h2a; // @[dec_tlu_ctl.scala 2315:34] - wire _T_1422 = mhpme4 == 10'h2b; // @[dec_tlu_ctl.scala 2316:34] - wire _T_1424 = mhpme4 == 10'h2c; // @[dec_tlu_ctl.scala 2317:34] - wire _T_1426 = mhpme4 == 10'h2d; // @[dec_tlu_ctl.scala 2318:34] - wire _T_1428 = mhpme4 == 10'h2e; // @[dec_tlu_ctl.scala 2319:34] - wire _T_1430 = mhpme4 == 10'h2f; // @[dec_tlu_ctl.scala 2320:34] - wire _T_1432 = mhpme4 == 10'h30; // @[dec_tlu_ctl.scala 2321:34] - wire _T_1434 = mhpme4 == 10'h31; // @[dec_tlu_ctl.scala 2322:34] - wire _T_1439 = mhpme4 == 10'h32; // @[dec_tlu_ctl.scala 2323:34] - wire _T_1449 = mhpme4 == 10'h36; // @[dec_tlu_ctl.scala 2324:34] - wire _T_1452 = mhpme4 == 10'h37; // @[dec_tlu_ctl.scala 2325:34] - wire _T_1455 = mhpme4 == 10'h38; // @[dec_tlu_ctl.scala 2326:34] - wire _T_1458 = mhpme4 == 10'h200; // @[dec_tlu_ctl.scala 2328:34] - wire _T_1460 = mhpme4 == 10'h201; // @[dec_tlu_ctl.scala 2329:34] - wire _T_1462 = mhpme4 == 10'h202; // @[dec_tlu_ctl.scala 2330:34] - wire _T_1464 = mhpme4 == 10'h203; // @[dec_tlu_ctl.scala 2331:34] - wire _T_1466 = mhpme4 == 10'h204; // @[dec_tlu_ctl.scala 2332:34] - wire _T_1469 = _T_1303 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] - wire _T_1470 = _T_1305 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] - wire _T_1471 = _T_1307 & _T_1026; // @[Mux.scala 27:72] - wire _T_1472 = _T_1311 & _T_1032; // @[Mux.scala 27:72] - wire _T_1473 = _T_1317 & _T_1037; // @[Mux.scala 27:72] - wire _T_1474 = _T_1322 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] - wire _T_1475 = _T_1324 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] - wire _T_1476 = _T_1326 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] - wire _T_1477 = _T_1328 & _T_1046; // @[Mux.scala 27:72] - wire _T_1478 = _T_1331 & _T_1049; // @[Mux.scala 27:72] - wire _T_1479 = _T_1334 & _T_1052; // @[Mux.scala 27:72] - wire _T_1480 = _T_1337 & _T_1055; // @[Mux.scala 27:72] - wire _T_1481 = _T_1340 & _T_1059; // @[Mux.scala 27:72] - wire _T_1482 = _T_1344 & _T_1064; // @[Mux.scala 27:72] - wire _T_1483 = _T_1349 & _T_1067; // @[Mux.scala 27:72] - wire _T_1484 = _T_1352 & _T_1070; // @[Mux.scala 27:72] - wire _T_1485 = _T_1355 & _T_1073; // @[Mux.scala 27:72] - wire _T_1486 = _T_1358 & _T_1076; // @[Mux.scala 27:72] - wire _T_1487 = _T_1361 & _T_1079; // @[Mux.scala 27:72] - wire _T_1488 = _T_1364 & _T_1082; // @[Mux.scala 27:72] - wire _T_1489 = _T_1367 & _T_1085; // @[Mux.scala 27:72] - wire _T_1490 = _T_1370 & _T_1088; // @[Mux.scala 27:72] - wire _T_1491 = _T_1373 & _T_1091; // @[Mux.scala 27:72] - wire _T_1492 = _T_1376 & _T_1096; // @[Mux.scala 27:72] - wire _T_1493 = _T_1381 & _T_1099; // @[Mux.scala 27:72] - wire _T_1494 = _T_1384 & _T_1102; // @[Mux.scala 27:72] - wire _T_1495 = _T_1387 & _T_1105; // @[Mux.scala 27:72] - wire _T_1496 = _T_1390 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] - wire _T_1498 = _T_1394 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] - wire _T_1499 = _T_1396 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] - wire _T_1500 = _T_1398 & io_lsu_store_stall_any; // @[Mux.scala 27:72] - wire _T_1501 = _T_1400 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] - wire _T_1502 = _T_1402 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] - wire _T_1503 = _T_1404 & _T_1123; // @[Mux.scala 27:72] - wire _T_1504 = _T_1408 & _T_1127; // @[Mux.scala 27:72] - wire _T_1505 = _T_1412 & io_take_ext_int; // @[Mux.scala 27:72] - wire _T_1506 = _T_1414 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] - wire _T_1507 = _T_1416 & _T_1135; // @[Mux.scala 27:72] - wire _T_1508 = _T_1420 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1509 = _T_1422 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1510 = _T_1424 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] - wire _T_1511 = _T_1426 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1512 = _T_1428 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1513 = _T_1430 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1514 = _T_1432 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1515 = _T_1434 & _T_1154; // @[Mux.scala 27:72] - wire _T_1516 = _T_1439 & _T_1164; // @[Mux.scala 27:72] - wire _T_1517 = _T_1449 & _T_1167; // @[Mux.scala 27:72] - wire _T_1518 = _T_1452 & _T_1170; // @[Mux.scala 27:72] - wire _T_1519 = _T_1455 & _T_1173; // @[Mux.scala 27:72] - wire _T_1520 = _T_1458 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] - wire _T_1521 = _T_1460 & io_dma_pmu_any_read; // @[Mux.scala 27:72] - wire _T_1522 = _T_1462 & io_dma_pmu_any_write; // @[Mux.scala 27:72] - wire _T_1523 = _T_1464 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] - wire _T_1524 = _T_1466 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] - wire _T_1525 = _T_1301 | _T_1469; // @[Mux.scala 27:72] - wire _T_1526 = _T_1525 | _T_1470; // @[Mux.scala 27:72] - wire _T_1527 = _T_1526 | _T_1471; // @[Mux.scala 27:72] - wire _T_1528 = _T_1527 | _T_1472; // @[Mux.scala 27:72] - wire _T_1529 = _T_1528 | _T_1473; // @[Mux.scala 27:72] - wire _T_1530 = _T_1529 | _T_1474; // @[Mux.scala 27:72] - wire _T_1531 = _T_1530 | _T_1475; // @[Mux.scala 27:72] - wire _T_1532 = _T_1531 | _T_1476; // @[Mux.scala 27:72] - wire _T_1533 = _T_1532 | _T_1477; // @[Mux.scala 27:72] - wire _T_1534 = _T_1533 | _T_1478; // @[Mux.scala 27:72] - wire _T_1535 = _T_1534 | _T_1479; // @[Mux.scala 27:72] + wire _T_1311 = mhpme4 == 10'h1; // @[dec_tlu_ctl.scala 2273:34] + wire _T_1313 = mhpme4 == 10'h2; // @[dec_tlu_ctl.scala 2274:34] + wire _T_1315 = mhpme4 == 10'h3; // @[dec_tlu_ctl.scala 2275:34] + wire _T_1317 = mhpme4 == 10'h4; // @[dec_tlu_ctl.scala 2276:34] + wire _T_1321 = mhpme4 == 10'h5; // @[dec_tlu_ctl.scala 2277:34] + wire _T_1327 = mhpme4 == 10'h6; // @[dec_tlu_ctl.scala 2278:34] + wire _T_1332 = mhpme4 == 10'h7; // @[dec_tlu_ctl.scala 2279:34] + wire _T_1334 = mhpme4 == 10'h8; // @[dec_tlu_ctl.scala 2280:34] + wire _T_1336 = mhpme4 == 10'h1e; // @[dec_tlu_ctl.scala 2281:34] + wire _T_1338 = mhpme4 == 10'h9; // @[dec_tlu_ctl.scala 2282:34] + wire _T_1341 = mhpme4 == 10'ha; // @[dec_tlu_ctl.scala 2283:34] + wire _T_1344 = mhpme4 == 10'hb; // @[dec_tlu_ctl.scala 2284:34] + wire _T_1347 = mhpme4 == 10'hc; // @[dec_tlu_ctl.scala 2285:34] + wire _T_1350 = mhpme4 == 10'hd; // @[dec_tlu_ctl.scala 2286:34] + wire _T_1354 = mhpme4 == 10'he; // @[dec_tlu_ctl.scala 2287:34] + wire _T_1359 = mhpme4 == 10'hf; // @[dec_tlu_ctl.scala 2288:34] + wire _T_1362 = mhpme4 == 10'h10; // @[dec_tlu_ctl.scala 2289:34] + wire _T_1365 = mhpme4 == 10'h12; // @[dec_tlu_ctl.scala 2290:34] + wire _T_1368 = mhpme4 == 10'h11; // @[dec_tlu_ctl.scala 2291:34] + wire _T_1371 = mhpme4 == 10'h13; // @[dec_tlu_ctl.scala 2292:34] + wire _T_1374 = mhpme4 == 10'h14; // @[dec_tlu_ctl.scala 2293:34] + wire _T_1377 = mhpme4 == 10'h15; // @[dec_tlu_ctl.scala 2294:34] + wire _T_1380 = mhpme4 == 10'h16; // @[dec_tlu_ctl.scala 2295:34] + wire _T_1383 = mhpme4 == 10'h17; // @[dec_tlu_ctl.scala 2296:34] + wire _T_1386 = mhpme4 == 10'h18; // @[dec_tlu_ctl.scala 2297:34] + wire _T_1391 = mhpme4 == 10'h19; // @[dec_tlu_ctl.scala 2298:34] + wire _T_1394 = mhpme4 == 10'h1a; // @[dec_tlu_ctl.scala 2299:34] + wire _T_1397 = mhpme4 == 10'h1b; // @[dec_tlu_ctl.scala 2300:34] + wire _T_1400 = mhpme4 == 10'h1c; // @[dec_tlu_ctl.scala 2301:34] + wire _T_1404 = mhpme4 == 10'h1f; // @[dec_tlu_ctl.scala 2303:34] + wire _T_1406 = mhpme4 == 10'h20; // @[dec_tlu_ctl.scala 2304:34] + wire _T_1408 = mhpme4 == 10'h22; // @[dec_tlu_ctl.scala 2305:34] + wire _T_1410 = mhpme4 == 10'h23; // @[dec_tlu_ctl.scala 2306:34] + wire _T_1412 = mhpme4 == 10'h24; // @[dec_tlu_ctl.scala 2307:34] + wire _T_1414 = mhpme4 == 10'h25; // @[dec_tlu_ctl.scala 2308:34] + wire _T_1418 = mhpme4 == 10'h26; // @[dec_tlu_ctl.scala 2309:34] + wire _T_1422 = mhpme4 == 10'h27; // @[dec_tlu_ctl.scala 2310:34] + wire _T_1424 = mhpme4 == 10'h28; // @[dec_tlu_ctl.scala 2311:34] + wire _T_1426 = mhpme4 == 10'h29; // @[dec_tlu_ctl.scala 2312:34] + wire _T_1430 = mhpme4 == 10'h2a; // @[dec_tlu_ctl.scala 2313:34] + wire _T_1432 = mhpme4 == 10'h2b; // @[dec_tlu_ctl.scala 2314:34] + wire _T_1434 = mhpme4 == 10'h2c; // @[dec_tlu_ctl.scala 2315:34] + wire _T_1436 = mhpme4 == 10'h2d; // @[dec_tlu_ctl.scala 2316:34] + wire _T_1438 = mhpme4 == 10'h2e; // @[dec_tlu_ctl.scala 2317:34] + wire _T_1440 = mhpme4 == 10'h2f; // @[dec_tlu_ctl.scala 2318:34] + wire _T_1442 = mhpme4 == 10'h30; // @[dec_tlu_ctl.scala 2319:34] + wire _T_1444 = mhpme4 == 10'h31; // @[dec_tlu_ctl.scala 2320:34] + wire _T_1449 = mhpme4 == 10'h32; // @[dec_tlu_ctl.scala 2321:34] + wire _T_1459 = mhpme4 == 10'h36; // @[dec_tlu_ctl.scala 2322:34] + wire _T_1462 = mhpme4 == 10'h37; // @[dec_tlu_ctl.scala 2323:34] + wire _T_1465 = mhpme4 == 10'h38; // @[dec_tlu_ctl.scala 2324:34] + wire _T_1468 = mhpme4 == 10'h200; // @[dec_tlu_ctl.scala 2326:34] + wire _T_1470 = mhpme4 == 10'h201; // @[dec_tlu_ctl.scala 2327:34] + wire _T_1472 = mhpme4 == 10'h202; // @[dec_tlu_ctl.scala 2328:34] + wire _T_1474 = mhpme4 == 10'h203; // @[dec_tlu_ctl.scala 2329:34] + wire _T_1476 = mhpme4 == 10'h204; // @[dec_tlu_ctl.scala 2330:34] + wire _T_1479 = _T_1313 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_1480 = _T_1315 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_1481 = _T_1317 & _T_1036; // @[Mux.scala 27:72] + wire _T_1482 = _T_1321 & _T_1042; // @[Mux.scala 27:72] + wire _T_1483 = _T_1327 & _T_1047; // @[Mux.scala 27:72] + wire _T_1484 = _T_1332 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_1485 = _T_1334 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_1486 = _T_1336 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_1487 = _T_1338 & _T_1056; // @[Mux.scala 27:72] + wire _T_1488 = _T_1341 & _T_1059; // @[Mux.scala 27:72] + wire _T_1489 = _T_1344 & _T_1062; // @[Mux.scala 27:72] + wire _T_1490 = _T_1347 & _T_1065; // @[Mux.scala 27:72] + wire _T_1491 = _T_1350 & _T_1069; // @[Mux.scala 27:72] + wire _T_1492 = _T_1354 & _T_1074; // @[Mux.scala 27:72] + wire _T_1493 = _T_1359 & _T_1077; // @[Mux.scala 27:72] + wire _T_1494 = _T_1362 & _T_1080; // @[Mux.scala 27:72] + wire _T_1495 = _T_1365 & _T_1083; // @[Mux.scala 27:72] + wire _T_1496 = _T_1368 & _T_1086; // @[Mux.scala 27:72] + wire _T_1497 = _T_1371 & _T_1089; // @[Mux.scala 27:72] + wire _T_1498 = _T_1374 & _T_1092; // @[Mux.scala 27:72] + wire _T_1499 = _T_1377 & _T_1095; // @[Mux.scala 27:72] + wire _T_1500 = _T_1380 & _T_1098; // @[Mux.scala 27:72] + wire _T_1501 = _T_1383 & _T_1101; // @[Mux.scala 27:72] + wire _T_1502 = _T_1386 & _T_1106; // @[Mux.scala 27:72] + wire _T_1503 = _T_1391 & _T_1109; // @[Mux.scala 27:72] + wire _T_1504 = _T_1394 & _T_1112; // @[Mux.scala 27:72] + wire _T_1505 = _T_1397 & _T_1115; // @[Mux.scala 27:72] + wire _T_1506 = _T_1400 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_1508 = _T_1404 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_1509 = _T_1406 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_1510 = _T_1408 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_1511 = _T_1410 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_1512 = _T_1412 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_1513 = _T_1414 & _T_1133; // @[Mux.scala 27:72] + wire _T_1514 = _T_1418 & _T_1137; // @[Mux.scala 27:72] + wire _T_1515 = _T_1422 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_1516 = _T_1424 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_1517 = _T_1426 & _T_1145; // @[Mux.scala 27:72] + wire _T_1518 = _T_1430 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1519 = _T_1432 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1520 = _T_1434 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_1521 = _T_1436 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1522 = _T_1438 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1523 = _T_1440 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1524 = _T_1442 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1525 = _T_1444 & _T_1164; // @[Mux.scala 27:72] + wire _T_1526 = _T_1449 & _T_1174; // @[Mux.scala 27:72] + wire _T_1527 = _T_1459 & _T_1177; // @[Mux.scala 27:72] + wire _T_1528 = _T_1462 & _T_1180; // @[Mux.scala 27:72] + wire _T_1529 = _T_1465 & _T_1183; // @[Mux.scala 27:72] + wire _T_1530 = _T_1468 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_1531 = _T_1470 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_1532 = _T_1472 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_1533 = _T_1474 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_1534 = _T_1476 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_1535 = _T_1311 | _T_1479; // @[Mux.scala 27:72] wire _T_1536 = _T_1535 | _T_1480; // @[Mux.scala 27:72] wire _T_1537 = _T_1536 | _T_1481; // @[Mux.scala 27:72] wire _T_1538 = _T_1537 | _T_1482; // @[Mux.scala 27:72] @@ -51784,7 +51785,7 @@ module csr_tlu( wire _T_1550 = _T_1549 | _T_1494; // @[Mux.scala 27:72] wire _T_1551 = _T_1550 | _T_1495; // @[Mux.scala 27:72] wire _T_1552 = _T_1551 | _T_1496; // @[Mux.scala 27:72] - wire _T_1553 = _T_1552 | _T_1476; // @[Mux.scala 27:72] + wire _T_1553 = _T_1552 | _T_1497; // @[Mux.scala 27:72] wire _T_1554 = _T_1553 | _T_1498; // @[Mux.scala 27:72] wire _T_1555 = _T_1554 | _T_1499; // @[Mux.scala 27:72] wire _T_1556 = _T_1555 | _T_1500; // @[Mux.scala 27:72] @@ -51794,7 +51795,7 @@ module csr_tlu( wire _T_1560 = _T_1559 | _T_1504; // @[Mux.scala 27:72] wire _T_1561 = _T_1560 | _T_1505; // @[Mux.scala 27:72] wire _T_1562 = _T_1561 | _T_1506; // @[Mux.scala 27:72] - wire _T_1563 = _T_1562 | _T_1507; // @[Mux.scala 27:72] + wire _T_1563 = _T_1562 | _T_1486; // @[Mux.scala 27:72] wire _T_1564 = _T_1563 | _T_1508; // @[Mux.scala 27:72] wire _T_1565 = _T_1564 | _T_1509; // @[Mux.scala 27:72] wire _T_1566 = _T_1565 | _T_1510; // @[Mux.scala 27:72] @@ -51812,131 +51813,131 @@ module csr_tlu( wire _T_1578 = _T_1577 | _T_1522; // @[Mux.scala 27:72] wire _T_1579 = _T_1578 | _T_1523; // @[Mux.scala 27:72] wire _T_1580 = _T_1579 | _T_1524; // @[Mux.scala 27:72] - wire mhpmc_inc_r_1 = _T_1300 & _T_1580; // @[dec_tlu_ctl.scala 2274:44] - wire _T_1584 = ~mcountinhibit[5]; // @[dec_tlu_ctl.scala 2274:24] + wire _T_1581 = _T_1580 | _T_1525; // @[Mux.scala 27:72] + wire _T_1582 = _T_1581 | _T_1526; // @[Mux.scala 27:72] + wire _T_1583 = _T_1582 | _T_1527; // @[Mux.scala 27:72] + wire _T_1584 = _T_1583 | _T_1528; // @[Mux.scala 27:72] + wire _T_1585 = _T_1584 | _T_1529; // @[Mux.scala 27:72] + wire _T_1586 = _T_1585 | _T_1530; // @[Mux.scala 27:72] + wire _T_1587 = _T_1586 | _T_1531; // @[Mux.scala 27:72] + wire _T_1588 = _T_1587 | _T_1532; // @[Mux.scala 27:72] + wire _T_1589 = _T_1588 | _T_1533; // @[Mux.scala 27:72] + wire _T_1590 = _T_1589 | _T_1534; // @[Mux.scala 27:72] + wire mhpmc_inc_r_1 = _T_1310 & _T_1590; // @[dec_tlu_ctl.scala 2272:44] + wire _T_1594 = ~mcountinhibit[5]; // @[dec_tlu_ctl.scala 2272:24] reg [9:0] mhpme5; // @[Reg.scala 27:20] - wire _T_1585 = mhpme5 == 10'h1; // @[dec_tlu_ctl.scala 2275:34] - wire _T_1587 = mhpme5 == 10'h2; // @[dec_tlu_ctl.scala 2276:34] - wire _T_1589 = mhpme5 == 10'h3; // @[dec_tlu_ctl.scala 2277:34] - wire _T_1591 = mhpme5 == 10'h4; // @[dec_tlu_ctl.scala 2278:34] - wire _T_1595 = mhpme5 == 10'h5; // @[dec_tlu_ctl.scala 2279:34] - wire _T_1601 = mhpme5 == 10'h6; // @[dec_tlu_ctl.scala 2280:34] - wire _T_1606 = mhpme5 == 10'h7; // @[dec_tlu_ctl.scala 2281:34] - wire _T_1608 = mhpme5 == 10'h8; // @[dec_tlu_ctl.scala 2282:34] - wire _T_1610 = mhpme5 == 10'h1e; // @[dec_tlu_ctl.scala 2283:34] - wire _T_1612 = mhpme5 == 10'h9; // @[dec_tlu_ctl.scala 2284:34] - wire _T_1615 = mhpme5 == 10'ha; // @[dec_tlu_ctl.scala 2285:34] - wire _T_1618 = mhpme5 == 10'hb; // @[dec_tlu_ctl.scala 2286:34] - wire _T_1621 = mhpme5 == 10'hc; // @[dec_tlu_ctl.scala 2287:34] - wire _T_1624 = mhpme5 == 10'hd; // @[dec_tlu_ctl.scala 2288:34] - wire _T_1628 = mhpme5 == 10'he; // @[dec_tlu_ctl.scala 2289:34] - wire _T_1633 = mhpme5 == 10'hf; // @[dec_tlu_ctl.scala 2290:34] - wire _T_1636 = mhpme5 == 10'h10; // @[dec_tlu_ctl.scala 2291:34] - wire _T_1639 = mhpme5 == 10'h12; // @[dec_tlu_ctl.scala 2292:34] - wire _T_1642 = mhpme5 == 10'h11; // @[dec_tlu_ctl.scala 2293:34] - wire _T_1645 = mhpme5 == 10'h13; // @[dec_tlu_ctl.scala 2294:34] - wire _T_1648 = mhpme5 == 10'h14; // @[dec_tlu_ctl.scala 2295:34] - wire _T_1651 = mhpme5 == 10'h15; // @[dec_tlu_ctl.scala 2296:34] - wire _T_1654 = mhpme5 == 10'h16; // @[dec_tlu_ctl.scala 2297:34] - wire _T_1657 = mhpme5 == 10'h17; // @[dec_tlu_ctl.scala 2298:34] - wire _T_1660 = mhpme5 == 10'h18; // @[dec_tlu_ctl.scala 2299:34] - wire _T_1665 = mhpme5 == 10'h19; // @[dec_tlu_ctl.scala 2300:34] - wire _T_1668 = mhpme5 == 10'h1a; // @[dec_tlu_ctl.scala 2301:34] - wire _T_1671 = mhpme5 == 10'h1b; // @[dec_tlu_ctl.scala 2302:34] - wire _T_1674 = mhpme5 == 10'h1c; // @[dec_tlu_ctl.scala 2303:34] - wire _T_1678 = mhpme5 == 10'h1f; // @[dec_tlu_ctl.scala 2305:34] - wire _T_1680 = mhpme5 == 10'h20; // @[dec_tlu_ctl.scala 2306:34] - wire _T_1682 = mhpme5 == 10'h22; // @[dec_tlu_ctl.scala 2307:34] - wire _T_1684 = mhpme5 == 10'h23; // @[dec_tlu_ctl.scala 2308:34] - wire _T_1686 = mhpme5 == 10'h24; // @[dec_tlu_ctl.scala 2309:34] - wire _T_1688 = mhpme5 == 10'h25; // @[dec_tlu_ctl.scala 2310:34] - wire _T_1692 = mhpme5 == 10'h26; // @[dec_tlu_ctl.scala 2311:34] - wire _T_1696 = mhpme5 == 10'h27; // @[dec_tlu_ctl.scala 2312:34] - wire _T_1698 = mhpme5 == 10'h28; // @[dec_tlu_ctl.scala 2313:34] - wire _T_1700 = mhpme5 == 10'h29; // @[dec_tlu_ctl.scala 2314:34] - wire _T_1704 = mhpme5 == 10'h2a; // @[dec_tlu_ctl.scala 2315:34] - wire _T_1706 = mhpme5 == 10'h2b; // @[dec_tlu_ctl.scala 2316:34] - wire _T_1708 = mhpme5 == 10'h2c; // @[dec_tlu_ctl.scala 2317:34] - wire _T_1710 = mhpme5 == 10'h2d; // @[dec_tlu_ctl.scala 2318:34] - wire _T_1712 = mhpme5 == 10'h2e; // @[dec_tlu_ctl.scala 2319:34] - wire _T_1714 = mhpme5 == 10'h2f; // @[dec_tlu_ctl.scala 2320:34] - wire _T_1716 = mhpme5 == 10'h30; // @[dec_tlu_ctl.scala 2321:34] - wire _T_1718 = mhpme5 == 10'h31; // @[dec_tlu_ctl.scala 2322:34] - wire _T_1723 = mhpme5 == 10'h32; // @[dec_tlu_ctl.scala 2323:34] - wire _T_1733 = mhpme5 == 10'h36; // @[dec_tlu_ctl.scala 2324:34] - wire _T_1736 = mhpme5 == 10'h37; // @[dec_tlu_ctl.scala 2325:34] - wire _T_1739 = mhpme5 == 10'h38; // @[dec_tlu_ctl.scala 2326:34] - wire _T_1742 = mhpme5 == 10'h200; // @[dec_tlu_ctl.scala 2328:34] - wire _T_1744 = mhpme5 == 10'h201; // @[dec_tlu_ctl.scala 2329:34] - wire _T_1746 = mhpme5 == 10'h202; // @[dec_tlu_ctl.scala 2330:34] - wire _T_1748 = mhpme5 == 10'h203; // @[dec_tlu_ctl.scala 2331:34] - wire _T_1750 = mhpme5 == 10'h204; // @[dec_tlu_ctl.scala 2332:34] - wire _T_1753 = _T_1587 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] - wire _T_1754 = _T_1589 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] - wire _T_1755 = _T_1591 & _T_1026; // @[Mux.scala 27:72] - wire _T_1756 = _T_1595 & _T_1032; // @[Mux.scala 27:72] - wire _T_1757 = _T_1601 & _T_1037; // @[Mux.scala 27:72] - wire _T_1758 = _T_1606 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] - wire _T_1759 = _T_1608 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] - wire _T_1760 = _T_1610 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] - wire _T_1761 = _T_1612 & _T_1046; // @[Mux.scala 27:72] - wire _T_1762 = _T_1615 & _T_1049; // @[Mux.scala 27:72] - wire _T_1763 = _T_1618 & _T_1052; // @[Mux.scala 27:72] - wire _T_1764 = _T_1621 & _T_1055; // @[Mux.scala 27:72] - wire _T_1765 = _T_1624 & _T_1059; // @[Mux.scala 27:72] - wire _T_1766 = _T_1628 & _T_1064; // @[Mux.scala 27:72] - wire _T_1767 = _T_1633 & _T_1067; // @[Mux.scala 27:72] - wire _T_1768 = _T_1636 & _T_1070; // @[Mux.scala 27:72] - wire _T_1769 = _T_1639 & _T_1073; // @[Mux.scala 27:72] - wire _T_1770 = _T_1642 & _T_1076; // @[Mux.scala 27:72] - wire _T_1771 = _T_1645 & _T_1079; // @[Mux.scala 27:72] - wire _T_1772 = _T_1648 & _T_1082; // @[Mux.scala 27:72] - wire _T_1773 = _T_1651 & _T_1085; // @[Mux.scala 27:72] - wire _T_1774 = _T_1654 & _T_1088; // @[Mux.scala 27:72] - wire _T_1775 = _T_1657 & _T_1091; // @[Mux.scala 27:72] - wire _T_1776 = _T_1660 & _T_1096; // @[Mux.scala 27:72] - wire _T_1777 = _T_1665 & _T_1099; // @[Mux.scala 27:72] - wire _T_1778 = _T_1668 & _T_1102; // @[Mux.scala 27:72] - wire _T_1779 = _T_1671 & _T_1105; // @[Mux.scala 27:72] - wire _T_1780 = _T_1674 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] - wire _T_1782 = _T_1678 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] - wire _T_1783 = _T_1680 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] - wire _T_1784 = _T_1682 & io_lsu_store_stall_any; // @[Mux.scala 27:72] - wire _T_1785 = _T_1684 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] - wire _T_1786 = _T_1686 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] - wire _T_1787 = _T_1688 & _T_1123; // @[Mux.scala 27:72] - wire _T_1788 = _T_1692 & _T_1127; // @[Mux.scala 27:72] - wire _T_1789 = _T_1696 & io_take_ext_int; // @[Mux.scala 27:72] - wire _T_1790 = _T_1698 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] - wire _T_1791 = _T_1700 & _T_1135; // @[Mux.scala 27:72] - wire _T_1792 = _T_1704 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1793 = _T_1706 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1794 = _T_1708 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] - wire _T_1795 = _T_1710 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1796 = _T_1712 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1797 = _T_1714 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1798 = _T_1716 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1799 = _T_1718 & _T_1154; // @[Mux.scala 27:72] - wire _T_1800 = _T_1723 & _T_1164; // @[Mux.scala 27:72] - wire _T_1801 = _T_1733 & _T_1167; // @[Mux.scala 27:72] - wire _T_1802 = _T_1736 & _T_1170; // @[Mux.scala 27:72] - wire _T_1803 = _T_1739 & _T_1173; // @[Mux.scala 27:72] - wire _T_1804 = _T_1742 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] - wire _T_1805 = _T_1744 & io_dma_pmu_any_read; // @[Mux.scala 27:72] - wire _T_1806 = _T_1746 & io_dma_pmu_any_write; // @[Mux.scala 27:72] - wire _T_1807 = _T_1748 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] - wire _T_1808 = _T_1750 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] - wire _T_1809 = _T_1585 | _T_1753; // @[Mux.scala 27:72] - wire _T_1810 = _T_1809 | _T_1754; // @[Mux.scala 27:72] - wire _T_1811 = _T_1810 | _T_1755; // @[Mux.scala 27:72] - wire _T_1812 = _T_1811 | _T_1756; // @[Mux.scala 27:72] - wire _T_1813 = _T_1812 | _T_1757; // @[Mux.scala 27:72] - wire _T_1814 = _T_1813 | _T_1758; // @[Mux.scala 27:72] - wire _T_1815 = _T_1814 | _T_1759; // @[Mux.scala 27:72] - wire _T_1816 = _T_1815 | _T_1760; // @[Mux.scala 27:72] - wire _T_1817 = _T_1816 | _T_1761; // @[Mux.scala 27:72] - wire _T_1818 = _T_1817 | _T_1762; // @[Mux.scala 27:72] - wire _T_1819 = _T_1818 | _T_1763; // @[Mux.scala 27:72] + wire _T_1595 = mhpme5 == 10'h1; // @[dec_tlu_ctl.scala 2273:34] + wire _T_1597 = mhpme5 == 10'h2; // @[dec_tlu_ctl.scala 2274:34] + wire _T_1599 = mhpme5 == 10'h3; // @[dec_tlu_ctl.scala 2275:34] + wire _T_1601 = mhpme5 == 10'h4; // @[dec_tlu_ctl.scala 2276:34] + wire _T_1605 = mhpme5 == 10'h5; // @[dec_tlu_ctl.scala 2277:34] + wire _T_1611 = mhpme5 == 10'h6; // @[dec_tlu_ctl.scala 2278:34] + wire _T_1616 = mhpme5 == 10'h7; // @[dec_tlu_ctl.scala 2279:34] + wire _T_1618 = mhpme5 == 10'h8; // @[dec_tlu_ctl.scala 2280:34] + wire _T_1620 = mhpme5 == 10'h1e; // @[dec_tlu_ctl.scala 2281:34] + wire _T_1622 = mhpme5 == 10'h9; // @[dec_tlu_ctl.scala 2282:34] + wire _T_1625 = mhpme5 == 10'ha; // @[dec_tlu_ctl.scala 2283:34] + wire _T_1628 = mhpme5 == 10'hb; // @[dec_tlu_ctl.scala 2284:34] + wire _T_1631 = mhpme5 == 10'hc; // @[dec_tlu_ctl.scala 2285:34] + wire _T_1634 = mhpme5 == 10'hd; // @[dec_tlu_ctl.scala 2286:34] + wire _T_1638 = mhpme5 == 10'he; // @[dec_tlu_ctl.scala 2287:34] + wire _T_1643 = mhpme5 == 10'hf; // @[dec_tlu_ctl.scala 2288:34] + wire _T_1646 = mhpme5 == 10'h10; // @[dec_tlu_ctl.scala 2289:34] + wire _T_1649 = mhpme5 == 10'h12; // @[dec_tlu_ctl.scala 2290:34] + wire _T_1652 = mhpme5 == 10'h11; // @[dec_tlu_ctl.scala 2291:34] + wire _T_1655 = mhpme5 == 10'h13; // @[dec_tlu_ctl.scala 2292:34] + wire _T_1658 = mhpme5 == 10'h14; // @[dec_tlu_ctl.scala 2293:34] + wire _T_1661 = mhpme5 == 10'h15; // @[dec_tlu_ctl.scala 2294:34] + wire _T_1664 = mhpme5 == 10'h16; // @[dec_tlu_ctl.scala 2295:34] + wire _T_1667 = mhpme5 == 10'h17; // @[dec_tlu_ctl.scala 2296:34] + wire _T_1670 = mhpme5 == 10'h18; // @[dec_tlu_ctl.scala 2297:34] + wire _T_1675 = mhpme5 == 10'h19; // @[dec_tlu_ctl.scala 2298:34] + wire _T_1678 = mhpme5 == 10'h1a; // @[dec_tlu_ctl.scala 2299:34] + wire _T_1681 = mhpme5 == 10'h1b; // @[dec_tlu_ctl.scala 2300:34] + wire _T_1684 = mhpme5 == 10'h1c; // @[dec_tlu_ctl.scala 2301:34] + wire _T_1688 = mhpme5 == 10'h1f; // @[dec_tlu_ctl.scala 2303:34] + wire _T_1690 = mhpme5 == 10'h20; // @[dec_tlu_ctl.scala 2304:34] + wire _T_1692 = mhpme5 == 10'h22; // @[dec_tlu_ctl.scala 2305:34] + wire _T_1694 = mhpme5 == 10'h23; // @[dec_tlu_ctl.scala 2306:34] + wire _T_1696 = mhpme5 == 10'h24; // @[dec_tlu_ctl.scala 2307:34] + wire _T_1698 = mhpme5 == 10'h25; // @[dec_tlu_ctl.scala 2308:34] + wire _T_1702 = mhpme5 == 10'h26; // @[dec_tlu_ctl.scala 2309:34] + wire _T_1706 = mhpme5 == 10'h27; // @[dec_tlu_ctl.scala 2310:34] + wire _T_1708 = mhpme5 == 10'h28; // @[dec_tlu_ctl.scala 2311:34] + wire _T_1710 = mhpme5 == 10'h29; // @[dec_tlu_ctl.scala 2312:34] + wire _T_1714 = mhpme5 == 10'h2a; // @[dec_tlu_ctl.scala 2313:34] + wire _T_1716 = mhpme5 == 10'h2b; // @[dec_tlu_ctl.scala 2314:34] + wire _T_1718 = mhpme5 == 10'h2c; // @[dec_tlu_ctl.scala 2315:34] + wire _T_1720 = mhpme5 == 10'h2d; // @[dec_tlu_ctl.scala 2316:34] + wire _T_1722 = mhpme5 == 10'h2e; // @[dec_tlu_ctl.scala 2317:34] + wire _T_1724 = mhpme5 == 10'h2f; // @[dec_tlu_ctl.scala 2318:34] + wire _T_1726 = mhpme5 == 10'h30; // @[dec_tlu_ctl.scala 2319:34] + wire _T_1728 = mhpme5 == 10'h31; // @[dec_tlu_ctl.scala 2320:34] + wire _T_1733 = mhpme5 == 10'h32; // @[dec_tlu_ctl.scala 2321:34] + wire _T_1743 = mhpme5 == 10'h36; // @[dec_tlu_ctl.scala 2322:34] + wire _T_1746 = mhpme5 == 10'h37; // @[dec_tlu_ctl.scala 2323:34] + wire _T_1749 = mhpme5 == 10'h38; // @[dec_tlu_ctl.scala 2324:34] + wire _T_1752 = mhpme5 == 10'h200; // @[dec_tlu_ctl.scala 2326:34] + wire _T_1754 = mhpme5 == 10'h201; // @[dec_tlu_ctl.scala 2327:34] + wire _T_1756 = mhpme5 == 10'h202; // @[dec_tlu_ctl.scala 2328:34] + wire _T_1758 = mhpme5 == 10'h203; // @[dec_tlu_ctl.scala 2329:34] + wire _T_1760 = mhpme5 == 10'h204; // @[dec_tlu_ctl.scala 2330:34] + wire _T_1763 = _T_1597 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_1764 = _T_1599 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_1765 = _T_1601 & _T_1036; // @[Mux.scala 27:72] + wire _T_1766 = _T_1605 & _T_1042; // @[Mux.scala 27:72] + wire _T_1767 = _T_1611 & _T_1047; // @[Mux.scala 27:72] + wire _T_1768 = _T_1616 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_1769 = _T_1618 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_1770 = _T_1620 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_1771 = _T_1622 & _T_1056; // @[Mux.scala 27:72] + wire _T_1772 = _T_1625 & _T_1059; // @[Mux.scala 27:72] + wire _T_1773 = _T_1628 & _T_1062; // @[Mux.scala 27:72] + wire _T_1774 = _T_1631 & _T_1065; // @[Mux.scala 27:72] + wire _T_1775 = _T_1634 & _T_1069; // @[Mux.scala 27:72] + wire _T_1776 = _T_1638 & _T_1074; // @[Mux.scala 27:72] + wire _T_1777 = _T_1643 & _T_1077; // @[Mux.scala 27:72] + wire _T_1778 = _T_1646 & _T_1080; // @[Mux.scala 27:72] + wire _T_1779 = _T_1649 & _T_1083; // @[Mux.scala 27:72] + wire _T_1780 = _T_1652 & _T_1086; // @[Mux.scala 27:72] + wire _T_1781 = _T_1655 & _T_1089; // @[Mux.scala 27:72] + wire _T_1782 = _T_1658 & _T_1092; // @[Mux.scala 27:72] + wire _T_1783 = _T_1661 & _T_1095; // @[Mux.scala 27:72] + wire _T_1784 = _T_1664 & _T_1098; // @[Mux.scala 27:72] + wire _T_1785 = _T_1667 & _T_1101; // @[Mux.scala 27:72] + wire _T_1786 = _T_1670 & _T_1106; // @[Mux.scala 27:72] + wire _T_1787 = _T_1675 & _T_1109; // @[Mux.scala 27:72] + wire _T_1788 = _T_1678 & _T_1112; // @[Mux.scala 27:72] + wire _T_1789 = _T_1681 & _T_1115; // @[Mux.scala 27:72] + wire _T_1790 = _T_1684 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_1792 = _T_1688 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_1793 = _T_1690 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_1794 = _T_1692 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_1795 = _T_1694 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_1796 = _T_1696 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_1797 = _T_1698 & _T_1133; // @[Mux.scala 27:72] + wire _T_1798 = _T_1702 & _T_1137; // @[Mux.scala 27:72] + wire _T_1799 = _T_1706 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_1800 = _T_1708 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_1801 = _T_1710 & _T_1145; // @[Mux.scala 27:72] + wire _T_1802 = _T_1714 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1803 = _T_1716 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1804 = _T_1718 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_1805 = _T_1720 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1806 = _T_1722 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1807 = _T_1724 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1808 = _T_1726 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1809 = _T_1728 & _T_1164; // @[Mux.scala 27:72] + wire _T_1810 = _T_1733 & _T_1174; // @[Mux.scala 27:72] + wire _T_1811 = _T_1743 & _T_1177; // @[Mux.scala 27:72] + wire _T_1812 = _T_1746 & _T_1180; // @[Mux.scala 27:72] + wire _T_1813 = _T_1749 & _T_1183; // @[Mux.scala 27:72] + wire _T_1814 = _T_1752 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_1815 = _T_1754 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_1816 = _T_1756 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_1817 = _T_1758 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_1818 = _T_1760 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_1819 = _T_1595 | _T_1763; // @[Mux.scala 27:72] wire _T_1820 = _T_1819 | _T_1764; // @[Mux.scala 27:72] wire _T_1821 = _T_1820 | _T_1765; // @[Mux.scala 27:72] wire _T_1822 = _T_1821 | _T_1766; // @[Mux.scala 27:72] @@ -51954,7 +51955,7 @@ module csr_tlu( wire _T_1834 = _T_1833 | _T_1778; // @[Mux.scala 27:72] wire _T_1835 = _T_1834 | _T_1779; // @[Mux.scala 27:72] wire _T_1836 = _T_1835 | _T_1780; // @[Mux.scala 27:72] - wire _T_1837 = _T_1836 | _T_1760; // @[Mux.scala 27:72] + wire _T_1837 = _T_1836 | _T_1781; // @[Mux.scala 27:72] wire _T_1838 = _T_1837 | _T_1782; // @[Mux.scala 27:72] wire _T_1839 = _T_1838 | _T_1783; // @[Mux.scala 27:72] wire _T_1840 = _T_1839 | _T_1784; // @[Mux.scala 27:72] @@ -51964,7 +51965,7 @@ module csr_tlu( wire _T_1844 = _T_1843 | _T_1788; // @[Mux.scala 27:72] wire _T_1845 = _T_1844 | _T_1789; // @[Mux.scala 27:72] wire _T_1846 = _T_1845 | _T_1790; // @[Mux.scala 27:72] - wire _T_1847 = _T_1846 | _T_1791; // @[Mux.scala 27:72] + wire _T_1847 = _T_1846 | _T_1770; // @[Mux.scala 27:72] wire _T_1848 = _T_1847 | _T_1792; // @[Mux.scala 27:72] wire _T_1849 = _T_1848 | _T_1793; // @[Mux.scala 27:72] wire _T_1850 = _T_1849 | _T_1794; // @[Mux.scala 27:72] @@ -51982,131 +51983,131 @@ module csr_tlu( wire _T_1862 = _T_1861 | _T_1806; // @[Mux.scala 27:72] wire _T_1863 = _T_1862 | _T_1807; // @[Mux.scala 27:72] wire _T_1864 = _T_1863 | _T_1808; // @[Mux.scala 27:72] - wire mhpmc_inc_r_2 = _T_1584 & _T_1864; // @[dec_tlu_ctl.scala 2274:44] - wire _T_1868 = ~mcountinhibit[6]; // @[dec_tlu_ctl.scala 2274:24] + wire _T_1865 = _T_1864 | _T_1809; // @[Mux.scala 27:72] + wire _T_1866 = _T_1865 | _T_1810; // @[Mux.scala 27:72] + wire _T_1867 = _T_1866 | _T_1811; // @[Mux.scala 27:72] + wire _T_1868 = _T_1867 | _T_1812; // @[Mux.scala 27:72] + wire _T_1869 = _T_1868 | _T_1813; // @[Mux.scala 27:72] + wire _T_1870 = _T_1869 | _T_1814; // @[Mux.scala 27:72] + wire _T_1871 = _T_1870 | _T_1815; // @[Mux.scala 27:72] + wire _T_1872 = _T_1871 | _T_1816; // @[Mux.scala 27:72] + wire _T_1873 = _T_1872 | _T_1817; // @[Mux.scala 27:72] + wire _T_1874 = _T_1873 | _T_1818; // @[Mux.scala 27:72] + wire mhpmc_inc_r_2 = _T_1594 & _T_1874; // @[dec_tlu_ctl.scala 2272:44] + wire _T_1878 = ~mcountinhibit[6]; // @[dec_tlu_ctl.scala 2272:24] reg [9:0] mhpme6; // @[Reg.scala 27:20] - wire _T_1869 = mhpme6 == 10'h1; // @[dec_tlu_ctl.scala 2275:34] - wire _T_1871 = mhpme6 == 10'h2; // @[dec_tlu_ctl.scala 2276:34] - wire _T_1873 = mhpme6 == 10'h3; // @[dec_tlu_ctl.scala 2277:34] - wire _T_1875 = mhpme6 == 10'h4; // @[dec_tlu_ctl.scala 2278:34] - wire _T_1879 = mhpme6 == 10'h5; // @[dec_tlu_ctl.scala 2279:34] - wire _T_1885 = mhpme6 == 10'h6; // @[dec_tlu_ctl.scala 2280:34] - wire _T_1890 = mhpme6 == 10'h7; // @[dec_tlu_ctl.scala 2281:34] - wire _T_1892 = mhpme6 == 10'h8; // @[dec_tlu_ctl.scala 2282:34] - wire _T_1894 = mhpme6 == 10'h1e; // @[dec_tlu_ctl.scala 2283:34] - wire _T_1896 = mhpme6 == 10'h9; // @[dec_tlu_ctl.scala 2284:34] - wire _T_1899 = mhpme6 == 10'ha; // @[dec_tlu_ctl.scala 2285:34] - wire _T_1902 = mhpme6 == 10'hb; // @[dec_tlu_ctl.scala 2286:34] - wire _T_1905 = mhpme6 == 10'hc; // @[dec_tlu_ctl.scala 2287:34] - wire _T_1908 = mhpme6 == 10'hd; // @[dec_tlu_ctl.scala 2288:34] - wire _T_1912 = mhpme6 == 10'he; // @[dec_tlu_ctl.scala 2289:34] - wire _T_1917 = mhpme6 == 10'hf; // @[dec_tlu_ctl.scala 2290:34] - wire _T_1920 = mhpme6 == 10'h10; // @[dec_tlu_ctl.scala 2291:34] - wire _T_1923 = mhpme6 == 10'h12; // @[dec_tlu_ctl.scala 2292:34] - wire _T_1926 = mhpme6 == 10'h11; // @[dec_tlu_ctl.scala 2293:34] - wire _T_1929 = mhpme6 == 10'h13; // @[dec_tlu_ctl.scala 2294:34] - wire _T_1932 = mhpme6 == 10'h14; // @[dec_tlu_ctl.scala 2295:34] - wire _T_1935 = mhpme6 == 10'h15; // @[dec_tlu_ctl.scala 2296:34] - wire _T_1938 = mhpme6 == 10'h16; // @[dec_tlu_ctl.scala 2297:34] - wire _T_1941 = mhpme6 == 10'h17; // @[dec_tlu_ctl.scala 2298:34] - wire _T_1944 = mhpme6 == 10'h18; // @[dec_tlu_ctl.scala 2299:34] - wire _T_1949 = mhpme6 == 10'h19; // @[dec_tlu_ctl.scala 2300:34] - wire _T_1952 = mhpme6 == 10'h1a; // @[dec_tlu_ctl.scala 2301:34] - wire _T_1955 = mhpme6 == 10'h1b; // @[dec_tlu_ctl.scala 2302:34] - wire _T_1958 = mhpme6 == 10'h1c; // @[dec_tlu_ctl.scala 2303:34] - wire _T_1962 = mhpme6 == 10'h1f; // @[dec_tlu_ctl.scala 2305:34] - wire _T_1964 = mhpme6 == 10'h20; // @[dec_tlu_ctl.scala 2306:34] - wire _T_1966 = mhpme6 == 10'h22; // @[dec_tlu_ctl.scala 2307:34] - wire _T_1968 = mhpme6 == 10'h23; // @[dec_tlu_ctl.scala 2308:34] - wire _T_1970 = mhpme6 == 10'h24; // @[dec_tlu_ctl.scala 2309:34] - wire _T_1972 = mhpme6 == 10'h25; // @[dec_tlu_ctl.scala 2310:34] - wire _T_1976 = mhpme6 == 10'h26; // @[dec_tlu_ctl.scala 2311:34] - wire _T_1980 = mhpme6 == 10'h27; // @[dec_tlu_ctl.scala 2312:34] - wire _T_1982 = mhpme6 == 10'h28; // @[dec_tlu_ctl.scala 2313:34] - wire _T_1984 = mhpme6 == 10'h29; // @[dec_tlu_ctl.scala 2314:34] - wire _T_1988 = mhpme6 == 10'h2a; // @[dec_tlu_ctl.scala 2315:34] - wire _T_1990 = mhpme6 == 10'h2b; // @[dec_tlu_ctl.scala 2316:34] - wire _T_1992 = mhpme6 == 10'h2c; // @[dec_tlu_ctl.scala 2317:34] - wire _T_1994 = mhpme6 == 10'h2d; // @[dec_tlu_ctl.scala 2318:34] - wire _T_1996 = mhpme6 == 10'h2e; // @[dec_tlu_ctl.scala 2319:34] - wire _T_1998 = mhpme6 == 10'h2f; // @[dec_tlu_ctl.scala 2320:34] - wire _T_2000 = mhpme6 == 10'h30; // @[dec_tlu_ctl.scala 2321:34] - wire _T_2002 = mhpme6 == 10'h31; // @[dec_tlu_ctl.scala 2322:34] - wire _T_2007 = mhpme6 == 10'h32; // @[dec_tlu_ctl.scala 2323:34] - wire _T_2017 = mhpme6 == 10'h36; // @[dec_tlu_ctl.scala 2324:34] - wire _T_2020 = mhpme6 == 10'h37; // @[dec_tlu_ctl.scala 2325:34] - wire _T_2023 = mhpme6 == 10'h38; // @[dec_tlu_ctl.scala 2326:34] - wire _T_2026 = mhpme6 == 10'h200; // @[dec_tlu_ctl.scala 2328:34] - wire _T_2028 = mhpme6 == 10'h201; // @[dec_tlu_ctl.scala 2329:34] - wire _T_2030 = mhpme6 == 10'h202; // @[dec_tlu_ctl.scala 2330:34] - wire _T_2032 = mhpme6 == 10'h203; // @[dec_tlu_ctl.scala 2331:34] - wire _T_2034 = mhpme6 == 10'h204; // @[dec_tlu_ctl.scala 2332:34] - wire _T_2037 = _T_1871 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] - wire _T_2038 = _T_1873 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] - wire _T_2039 = _T_1875 & _T_1026; // @[Mux.scala 27:72] - wire _T_2040 = _T_1879 & _T_1032; // @[Mux.scala 27:72] - wire _T_2041 = _T_1885 & _T_1037; // @[Mux.scala 27:72] - wire _T_2042 = _T_1890 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] - wire _T_2043 = _T_1892 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] - wire _T_2044 = _T_1894 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] - wire _T_2045 = _T_1896 & _T_1046; // @[Mux.scala 27:72] - wire _T_2046 = _T_1899 & _T_1049; // @[Mux.scala 27:72] - wire _T_2047 = _T_1902 & _T_1052; // @[Mux.scala 27:72] - wire _T_2048 = _T_1905 & _T_1055; // @[Mux.scala 27:72] - wire _T_2049 = _T_1908 & _T_1059; // @[Mux.scala 27:72] - wire _T_2050 = _T_1912 & _T_1064; // @[Mux.scala 27:72] - wire _T_2051 = _T_1917 & _T_1067; // @[Mux.scala 27:72] - wire _T_2052 = _T_1920 & _T_1070; // @[Mux.scala 27:72] - wire _T_2053 = _T_1923 & _T_1073; // @[Mux.scala 27:72] - wire _T_2054 = _T_1926 & _T_1076; // @[Mux.scala 27:72] - wire _T_2055 = _T_1929 & _T_1079; // @[Mux.scala 27:72] - wire _T_2056 = _T_1932 & _T_1082; // @[Mux.scala 27:72] - wire _T_2057 = _T_1935 & _T_1085; // @[Mux.scala 27:72] - wire _T_2058 = _T_1938 & _T_1088; // @[Mux.scala 27:72] - wire _T_2059 = _T_1941 & _T_1091; // @[Mux.scala 27:72] - wire _T_2060 = _T_1944 & _T_1096; // @[Mux.scala 27:72] - wire _T_2061 = _T_1949 & _T_1099; // @[Mux.scala 27:72] - wire _T_2062 = _T_1952 & _T_1102; // @[Mux.scala 27:72] - wire _T_2063 = _T_1955 & _T_1105; // @[Mux.scala 27:72] - wire _T_2064 = _T_1958 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] - wire _T_2066 = _T_1962 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] - wire _T_2067 = _T_1964 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] - wire _T_2068 = _T_1966 & io_lsu_store_stall_any; // @[Mux.scala 27:72] - wire _T_2069 = _T_1968 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] - wire _T_2070 = _T_1970 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] - wire _T_2071 = _T_1972 & _T_1123; // @[Mux.scala 27:72] - wire _T_2072 = _T_1976 & _T_1127; // @[Mux.scala 27:72] - wire _T_2073 = _T_1980 & io_take_ext_int; // @[Mux.scala 27:72] - wire _T_2074 = _T_1982 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] - wire _T_2075 = _T_1984 & _T_1135; // @[Mux.scala 27:72] - wire _T_2076 = _T_1988 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_2077 = _T_1990 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_2078 = _T_1992 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] - wire _T_2079 = _T_1994 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_2080 = _T_1996 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_2081 = _T_1998 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_2082 = _T_2000 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_2083 = _T_2002 & _T_1154; // @[Mux.scala 27:72] - wire _T_2084 = _T_2007 & _T_1164; // @[Mux.scala 27:72] - wire _T_2085 = _T_2017 & _T_1167; // @[Mux.scala 27:72] - wire _T_2086 = _T_2020 & _T_1170; // @[Mux.scala 27:72] - wire _T_2087 = _T_2023 & _T_1173; // @[Mux.scala 27:72] - wire _T_2088 = _T_2026 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] - wire _T_2089 = _T_2028 & io_dma_pmu_any_read; // @[Mux.scala 27:72] - wire _T_2090 = _T_2030 & io_dma_pmu_any_write; // @[Mux.scala 27:72] - wire _T_2091 = _T_2032 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] - wire _T_2092 = _T_2034 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] - wire _T_2093 = _T_1869 | _T_2037; // @[Mux.scala 27:72] - wire _T_2094 = _T_2093 | _T_2038; // @[Mux.scala 27:72] - wire _T_2095 = _T_2094 | _T_2039; // @[Mux.scala 27:72] - wire _T_2096 = _T_2095 | _T_2040; // @[Mux.scala 27:72] - wire _T_2097 = _T_2096 | _T_2041; // @[Mux.scala 27:72] - wire _T_2098 = _T_2097 | _T_2042; // @[Mux.scala 27:72] - wire _T_2099 = _T_2098 | _T_2043; // @[Mux.scala 27:72] - wire _T_2100 = _T_2099 | _T_2044; // @[Mux.scala 27:72] - wire _T_2101 = _T_2100 | _T_2045; // @[Mux.scala 27:72] - wire _T_2102 = _T_2101 | _T_2046; // @[Mux.scala 27:72] - wire _T_2103 = _T_2102 | _T_2047; // @[Mux.scala 27:72] + wire _T_1879 = mhpme6 == 10'h1; // @[dec_tlu_ctl.scala 2273:34] + wire _T_1881 = mhpme6 == 10'h2; // @[dec_tlu_ctl.scala 2274:34] + wire _T_1883 = mhpme6 == 10'h3; // @[dec_tlu_ctl.scala 2275:34] + wire _T_1885 = mhpme6 == 10'h4; // @[dec_tlu_ctl.scala 2276:34] + wire _T_1889 = mhpme6 == 10'h5; // @[dec_tlu_ctl.scala 2277:34] + wire _T_1895 = mhpme6 == 10'h6; // @[dec_tlu_ctl.scala 2278:34] + wire _T_1900 = mhpme6 == 10'h7; // @[dec_tlu_ctl.scala 2279:34] + wire _T_1902 = mhpme6 == 10'h8; // @[dec_tlu_ctl.scala 2280:34] + wire _T_1904 = mhpme6 == 10'h1e; // @[dec_tlu_ctl.scala 2281:34] + wire _T_1906 = mhpme6 == 10'h9; // @[dec_tlu_ctl.scala 2282:34] + wire _T_1909 = mhpme6 == 10'ha; // @[dec_tlu_ctl.scala 2283:34] + wire _T_1912 = mhpme6 == 10'hb; // @[dec_tlu_ctl.scala 2284:34] + wire _T_1915 = mhpme6 == 10'hc; // @[dec_tlu_ctl.scala 2285:34] + wire _T_1918 = mhpme6 == 10'hd; // @[dec_tlu_ctl.scala 2286:34] + wire _T_1922 = mhpme6 == 10'he; // @[dec_tlu_ctl.scala 2287:34] + wire _T_1927 = mhpme6 == 10'hf; // @[dec_tlu_ctl.scala 2288:34] + wire _T_1930 = mhpme6 == 10'h10; // @[dec_tlu_ctl.scala 2289:34] + wire _T_1933 = mhpme6 == 10'h12; // @[dec_tlu_ctl.scala 2290:34] + wire _T_1936 = mhpme6 == 10'h11; // @[dec_tlu_ctl.scala 2291:34] + wire _T_1939 = mhpme6 == 10'h13; // @[dec_tlu_ctl.scala 2292:34] + wire _T_1942 = mhpme6 == 10'h14; // @[dec_tlu_ctl.scala 2293:34] + wire _T_1945 = mhpme6 == 10'h15; // @[dec_tlu_ctl.scala 2294:34] + wire _T_1948 = mhpme6 == 10'h16; // @[dec_tlu_ctl.scala 2295:34] + wire _T_1951 = mhpme6 == 10'h17; // @[dec_tlu_ctl.scala 2296:34] + wire _T_1954 = mhpme6 == 10'h18; // @[dec_tlu_ctl.scala 2297:34] + wire _T_1959 = mhpme6 == 10'h19; // @[dec_tlu_ctl.scala 2298:34] + wire _T_1962 = mhpme6 == 10'h1a; // @[dec_tlu_ctl.scala 2299:34] + wire _T_1965 = mhpme6 == 10'h1b; // @[dec_tlu_ctl.scala 2300:34] + wire _T_1968 = mhpme6 == 10'h1c; // @[dec_tlu_ctl.scala 2301:34] + wire _T_1972 = mhpme6 == 10'h1f; // @[dec_tlu_ctl.scala 2303:34] + wire _T_1974 = mhpme6 == 10'h20; // @[dec_tlu_ctl.scala 2304:34] + wire _T_1976 = mhpme6 == 10'h22; // @[dec_tlu_ctl.scala 2305:34] + wire _T_1978 = mhpme6 == 10'h23; // @[dec_tlu_ctl.scala 2306:34] + wire _T_1980 = mhpme6 == 10'h24; // @[dec_tlu_ctl.scala 2307:34] + wire _T_1982 = mhpme6 == 10'h25; // @[dec_tlu_ctl.scala 2308:34] + wire _T_1986 = mhpme6 == 10'h26; // @[dec_tlu_ctl.scala 2309:34] + wire _T_1990 = mhpme6 == 10'h27; // @[dec_tlu_ctl.scala 2310:34] + wire _T_1992 = mhpme6 == 10'h28; // @[dec_tlu_ctl.scala 2311:34] + wire _T_1994 = mhpme6 == 10'h29; // @[dec_tlu_ctl.scala 2312:34] + wire _T_1998 = mhpme6 == 10'h2a; // @[dec_tlu_ctl.scala 2313:34] + wire _T_2000 = mhpme6 == 10'h2b; // @[dec_tlu_ctl.scala 2314:34] + wire _T_2002 = mhpme6 == 10'h2c; // @[dec_tlu_ctl.scala 2315:34] + wire _T_2004 = mhpme6 == 10'h2d; // @[dec_tlu_ctl.scala 2316:34] + wire _T_2006 = mhpme6 == 10'h2e; // @[dec_tlu_ctl.scala 2317:34] + wire _T_2008 = mhpme6 == 10'h2f; // @[dec_tlu_ctl.scala 2318:34] + wire _T_2010 = mhpme6 == 10'h30; // @[dec_tlu_ctl.scala 2319:34] + wire _T_2012 = mhpme6 == 10'h31; // @[dec_tlu_ctl.scala 2320:34] + wire _T_2017 = mhpme6 == 10'h32; // @[dec_tlu_ctl.scala 2321:34] + wire _T_2027 = mhpme6 == 10'h36; // @[dec_tlu_ctl.scala 2322:34] + wire _T_2030 = mhpme6 == 10'h37; // @[dec_tlu_ctl.scala 2323:34] + wire _T_2033 = mhpme6 == 10'h38; // @[dec_tlu_ctl.scala 2324:34] + wire _T_2036 = mhpme6 == 10'h200; // @[dec_tlu_ctl.scala 2326:34] + wire _T_2038 = mhpme6 == 10'h201; // @[dec_tlu_ctl.scala 2327:34] + wire _T_2040 = mhpme6 == 10'h202; // @[dec_tlu_ctl.scala 2328:34] + wire _T_2042 = mhpme6 == 10'h203; // @[dec_tlu_ctl.scala 2329:34] + wire _T_2044 = mhpme6 == 10'h204; // @[dec_tlu_ctl.scala 2330:34] + wire _T_2047 = _T_1881 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_2048 = _T_1883 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_2049 = _T_1885 & _T_1036; // @[Mux.scala 27:72] + wire _T_2050 = _T_1889 & _T_1042; // @[Mux.scala 27:72] + wire _T_2051 = _T_1895 & _T_1047; // @[Mux.scala 27:72] + wire _T_2052 = _T_1900 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_2053 = _T_1902 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_2054 = _T_1904 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_2055 = _T_1906 & _T_1056; // @[Mux.scala 27:72] + wire _T_2056 = _T_1909 & _T_1059; // @[Mux.scala 27:72] + wire _T_2057 = _T_1912 & _T_1062; // @[Mux.scala 27:72] + wire _T_2058 = _T_1915 & _T_1065; // @[Mux.scala 27:72] + wire _T_2059 = _T_1918 & _T_1069; // @[Mux.scala 27:72] + wire _T_2060 = _T_1922 & _T_1074; // @[Mux.scala 27:72] + wire _T_2061 = _T_1927 & _T_1077; // @[Mux.scala 27:72] + wire _T_2062 = _T_1930 & _T_1080; // @[Mux.scala 27:72] + wire _T_2063 = _T_1933 & _T_1083; // @[Mux.scala 27:72] + wire _T_2064 = _T_1936 & _T_1086; // @[Mux.scala 27:72] + wire _T_2065 = _T_1939 & _T_1089; // @[Mux.scala 27:72] + wire _T_2066 = _T_1942 & _T_1092; // @[Mux.scala 27:72] + wire _T_2067 = _T_1945 & _T_1095; // @[Mux.scala 27:72] + wire _T_2068 = _T_1948 & _T_1098; // @[Mux.scala 27:72] + wire _T_2069 = _T_1951 & _T_1101; // @[Mux.scala 27:72] + wire _T_2070 = _T_1954 & _T_1106; // @[Mux.scala 27:72] + wire _T_2071 = _T_1959 & _T_1109; // @[Mux.scala 27:72] + wire _T_2072 = _T_1962 & _T_1112; // @[Mux.scala 27:72] + wire _T_2073 = _T_1965 & _T_1115; // @[Mux.scala 27:72] + wire _T_2074 = _T_1968 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_2076 = _T_1972 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_2077 = _T_1974 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_2078 = _T_1976 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_2079 = _T_1978 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_2080 = _T_1980 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_2081 = _T_1982 & _T_1133; // @[Mux.scala 27:72] + wire _T_2082 = _T_1986 & _T_1137; // @[Mux.scala 27:72] + wire _T_2083 = _T_1990 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_2084 = _T_1992 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_2085 = _T_1994 & _T_1145; // @[Mux.scala 27:72] + wire _T_2086 = _T_1998 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_2087 = _T_2000 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_2088 = _T_2002 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_2089 = _T_2004 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_2090 = _T_2006 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_2091 = _T_2008 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_2092 = _T_2010 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_2093 = _T_2012 & _T_1164; // @[Mux.scala 27:72] + wire _T_2094 = _T_2017 & _T_1174; // @[Mux.scala 27:72] + wire _T_2095 = _T_2027 & _T_1177; // @[Mux.scala 27:72] + wire _T_2096 = _T_2030 & _T_1180; // @[Mux.scala 27:72] + wire _T_2097 = _T_2033 & _T_1183; // @[Mux.scala 27:72] + wire _T_2098 = _T_2036 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_2099 = _T_2038 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_2100 = _T_2040 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_2101 = _T_2042 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_2102 = _T_2044 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_2103 = _T_1879 | _T_2047; // @[Mux.scala 27:72] wire _T_2104 = _T_2103 | _T_2048; // @[Mux.scala 27:72] wire _T_2105 = _T_2104 | _T_2049; // @[Mux.scala 27:72] wire _T_2106 = _T_2105 | _T_2050; // @[Mux.scala 27:72] @@ -52124,7 +52125,7 @@ module csr_tlu( wire _T_2118 = _T_2117 | _T_2062; // @[Mux.scala 27:72] wire _T_2119 = _T_2118 | _T_2063; // @[Mux.scala 27:72] wire _T_2120 = _T_2119 | _T_2064; // @[Mux.scala 27:72] - wire _T_2121 = _T_2120 | _T_2044; // @[Mux.scala 27:72] + wire _T_2121 = _T_2120 | _T_2065; // @[Mux.scala 27:72] wire _T_2122 = _T_2121 | _T_2066; // @[Mux.scala 27:72] wire _T_2123 = _T_2122 | _T_2067; // @[Mux.scala 27:72] wire _T_2124 = _T_2123 | _T_2068; // @[Mux.scala 27:72] @@ -52134,7 +52135,7 @@ module csr_tlu( wire _T_2128 = _T_2127 | _T_2072; // @[Mux.scala 27:72] wire _T_2129 = _T_2128 | _T_2073; // @[Mux.scala 27:72] wire _T_2130 = _T_2129 | _T_2074; // @[Mux.scala 27:72] - wire _T_2131 = _T_2130 | _T_2075; // @[Mux.scala 27:72] + wire _T_2131 = _T_2130 | _T_2054; // @[Mux.scala 27:72] wire _T_2132 = _T_2131 | _T_2076; // @[Mux.scala 27:72] wire _T_2133 = _T_2132 | _T_2077; // @[Mux.scala 27:72] wire _T_2134 = _T_2133 | _T_2078; // @[Mux.scala 27:72] @@ -52152,196 +52153,196 @@ module csr_tlu( wire _T_2146 = _T_2145 | _T_2090; // @[Mux.scala 27:72] wire _T_2147 = _T_2146 | _T_2091; // @[Mux.scala 27:72] wire _T_2148 = _T_2147 | _T_2092; // @[Mux.scala 27:72] - wire mhpmc_inc_r_3 = _T_1868 & _T_2148; // @[dec_tlu_ctl.scala 2274:44] - reg mhpmc_inc_r_d1_0; // @[dec_tlu_ctl.scala 2335:53] - reg mhpmc_inc_r_d1_1; // @[dec_tlu_ctl.scala 2336:53] - reg mhpmc_inc_r_d1_2; // @[dec_tlu_ctl.scala 2337:53] - reg mhpmc_inc_r_d1_3; // @[dec_tlu_ctl.scala 2338:53] - reg perfcnt_halted_d1; // @[dec_tlu_ctl.scala 2339:56] - wire perfcnt_halted = _T_85 | io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 2342:67] - wire _T_2160 = ~_T_85; // @[dec_tlu_ctl.scala 2343:37] - wire [3:0] _T_2162 = _T_2160 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_2169 = {mhpme6[9],mhpme5[9],mhpme4[9],mhpme3[9]}; // @[Cat.scala 29:58] - wire [3:0] perfcnt_during_sleep = _T_2162 & _T_2169; // @[dec_tlu_ctl.scala 2343:86] - wire _T_2171 = ~perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2345:67] - wire _T_2172 = perfcnt_halted_d1 & _T_2171; // @[dec_tlu_ctl.scala 2345:65] - wire _T_2173 = ~_T_2172; // @[dec_tlu_ctl.scala 2345:45] - wire _T_2176 = ~perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2346:67] - wire _T_2177 = perfcnt_halted_d1 & _T_2176; // @[dec_tlu_ctl.scala 2346:65] - wire _T_2178 = ~_T_2177; // @[dec_tlu_ctl.scala 2346:45] - wire _T_2181 = ~perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2347:67] - wire _T_2182 = perfcnt_halted_d1 & _T_2181; // @[dec_tlu_ctl.scala 2347:65] - wire _T_2183 = ~_T_2182; // @[dec_tlu_ctl.scala 2347:45] - wire _T_2186 = ~perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2348:67] - wire _T_2187 = perfcnt_halted_d1 & _T_2186; // @[dec_tlu_ctl.scala 2348:65] - wire _T_2188 = ~_T_2187; // @[dec_tlu_ctl.scala 2348:45] - wire _T_2191 = io_dec_csr_wraddr_r == 12'hb03; // @[dec_tlu_ctl.scala 2354:72] - wire mhpmc3_wr_en0 = io_dec_csr_wen_r_mod & _T_2191; // @[dec_tlu_ctl.scala 2354:43] - wire _T_2192 = ~perfcnt_halted; // @[dec_tlu_ctl.scala 2355:23] - wire _T_2194 = _T_2192 | perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2355:39] - wire _T_2195 = |mhpmc_inc_r_0; // @[dec_tlu_ctl.scala 2355:86] - wire mhpmc3_wr_en1 = _T_2194 & _T_2195; // @[dec_tlu_ctl.scala 2355:66] + wire _T_2149 = _T_2148 | _T_2093; // @[Mux.scala 27:72] + wire _T_2150 = _T_2149 | _T_2094; // @[Mux.scala 27:72] + wire _T_2151 = _T_2150 | _T_2095; // @[Mux.scala 27:72] + wire _T_2152 = _T_2151 | _T_2096; // @[Mux.scala 27:72] + wire _T_2153 = _T_2152 | _T_2097; // @[Mux.scala 27:72] + wire _T_2154 = _T_2153 | _T_2098; // @[Mux.scala 27:72] + wire _T_2155 = _T_2154 | _T_2099; // @[Mux.scala 27:72] + wire _T_2156 = _T_2155 | _T_2100; // @[Mux.scala 27:72] + wire _T_2157 = _T_2156 | _T_2101; // @[Mux.scala 27:72] + wire _T_2158 = _T_2157 | _T_2102; // @[Mux.scala 27:72] + wire mhpmc_inc_r_3 = _T_1878 & _T_2158; // @[dec_tlu_ctl.scala 2272:44] + reg mhpmc_inc_r_d1_0; // @[dec_tlu_ctl.scala 2333:53] + reg mhpmc_inc_r_d1_1; // @[dec_tlu_ctl.scala 2334:53] + reg mhpmc_inc_r_d1_2; // @[dec_tlu_ctl.scala 2335:53] + reg mhpmc_inc_r_d1_3; // @[dec_tlu_ctl.scala 2336:53] + reg perfcnt_halted_d1; // @[dec_tlu_ctl.scala 2337:56] + wire perfcnt_halted = _T_85 | io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 2340:67] + wire _T_2170 = ~_T_85; // @[dec_tlu_ctl.scala 2341:37] + wire [3:0] _T_2172 = _T_2170 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_2179 = {mhpme6[9],mhpme5[9],mhpme4[9],mhpme3[9]}; // @[Cat.scala 29:58] + wire [3:0] perfcnt_during_sleep = _T_2172 & _T_2179; // @[dec_tlu_ctl.scala 2341:86] + wire _T_2181 = ~perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2343:67] + wire _T_2182 = perfcnt_halted_d1 & _T_2181; // @[dec_tlu_ctl.scala 2343:65] + wire _T_2183 = ~_T_2182; // @[dec_tlu_ctl.scala 2343:45] + wire _T_2186 = ~perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2344:67] + wire _T_2187 = perfcnt_halted_d1 & _T_2186; // @[dec_tlu_ctl.scala 2344:65] + wire _T_2188 = ~_T_2187; // @[dec_tlu_ctl.scala 2344:45] + wire _T_2191 = ~perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2345:67] + wire _T_2192 = perfcnt_halted_d1 & _T_2191; // @[dec_tlu_ctl.scala 2345:65] + wire _T_2193 = ~_T_2192; // @[dec_tlu_ctl.scala 2345:45] + wire _T_2196 = ~perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2346:67] + wire _T_2197 = perfcnt_halted_d1 & _T_2196; // @[dec_tlu_ctl.scala 2346:65] + wire _T_2198 = ~_T_2197; // @[dec_tlu_ctl.scala 2346:45] + wire _T_2201 = io_dec_csr_wraddr_r == 12'hb03; // @[dec_tlu_ctl.scala 2352:72] + wire mhpmc3_wr_en0 = io_dec_csr_wen_r_mod & _T_2201; // @[dec_tlu_ctl.scala 2352:43] + wire _T_2202 = ~perfcnt_halted; // @[dec_tlu_ctl.scala 2353:23] + wire _T_2204 = _T_2202 | perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2353:39] + wire _T_2205 = |mhpmc_inc_r_0; // @[dec_tlu_ctl.scala 2353:86] + wire mhpmc3_wr_en1 = _T_2204 & _T_2205; // @[dec_tlu_ctl.scala 2353:66] reg [31:0] mhpmc3h; // @[lib.scala 374:16] reg [31:0] mhpmc3; // @[lib.scala 374:16] - wire [63:0] _T_2198 = {mhpmc3h,mhpmc3}; // @[Cat.scala 29:58] - wire [63:0] _T_2199 = {63'h0,mhpmc_inc_r_0}; // @[Cat.scala 29:58] - wire [63:0] mhpmc3_incr = _T_2198 + _T_2199; // @[dec_tlu_ctl.scala 2359:49] - wire _T_2207 = io_dec_csr_wraddr_r == 12'hb83; // @[dec_tlu_ctl.scala 2364:73] - wire mhpmc3h_wr_en0 = io_dec_csr_wen_r_mod & _T_2207; // @[dec_tlu_ctl.scala 2364:44] - wire _T_2213 = io_dec_csr_wraddr_r == 12'hb04; // @[dec_tlu_ctl.scala 2373:72] - wire mhpmc4_wr_en0 = io_dec_csr_wen_r_mod & _T_2213; // @[dec_tlu_ctl.scala 2373:43] - wire _T_2216 = _T_2192 | perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2374:39] - wire _T_2217 = |mhpmc_inc_r_1; // @[dec_tlu_ctl.scala 2374:86] - wire mhpmc4_wr_en1 = _T_2216 & _T_2217; // @[dec_tlu_ctl.scala 2374:66] + wire [63:0] _T_2208 = {mhpmc3h,mhpmc3}; // @[Cat.scala 29:58] + wire [63:0] _T_2209 = {63'h0,mhpmc_inc_r_0}; // @[Cat.scala 29:58] + wire [63:0] mhpmc3_incr = _T_2208 + _T_2209; // @[dec_tlu_ctl.scala 2357:49] + wire _T_2217 = io_dec_csr_wraddr_r == 12'hb83; // @[dec_tlu_ctl.scala 2362:73] + wire mhpmc3h_wr_en0 = io_dec_csr_wen_r_mod & _T_2217; // @[dec_tlu_ctl.scala 2362:44] + wire _T_2223 = io_dec_csr_wraddr_r == 12'hb04; // @[dec_tlu_ctl.scala 2371:72] + wire mhpmc4_wr_en0 = io_dec_csr_wen_r_mod & _T_2223; // @[dec_tlu_ctl.scala 2371:43] + wire _T_2226 = _T_2202 | perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2372:39] + wire _T_2227 = |mhpmc_inc_r_1; // @[dec_tlu_ctl.scala 2372:86] + wire mhpmc4_wr_en1 = _T_2226 & _T_2227; // @[dec_tlu_ctl.scala 2372:66] reg [31:0] mhpmc4h; // @[lib.scala 374:16] reg [31:0] mhpmc4; // @[lib.scala 374:16] - wire [63:0] _T_2220 = {mhpmc4h,mhpmc4}; // @[Cat.scala 29:58] - wire [63:0] _T_2221 = {63'h0,mhpmc_inc_r_1}; // @[Cat.scala 29:58] - wire [63:0] mhpmc4_incr = _T_2220 + _T_2221; // @[dec_tlu_ctl.scala 2379:49] - wire _T_2230 = io_dec_csr_wraddr_r == 12'hb84; // @[dec_tlu_ctl.scala 2383:73] - wire mhpmc4h_wr_en0 = io_dec_csr_wen_r_mod & _T_2230; // @[dec_tlu_ctl.scala 2383:44] - wire _T_2236 = io_dec_csr_wraddr_r == 12'hb05; // @[dec_tlu_ctl.scala 2392:72] - wire mhpmc5_wr_en0 = io_dec_csr_wen_r_mod & _T_2236; // @[dec_tlu_ctl.scala 2392:43] - wire _T_2239 = _T_2192 | perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2393:39] - wire _T_2240 = |mhpmc_inc_r_2; // @[dec_tlu_ctl.scala 2393:86] - wire mhpmc5_wr_en1 = _T_2239 & _T_2240; // @[dec_tlu_ctl.scala 2393:66] + wire [63:0] _T_2230 = {mhpmc4h,mhpmc4}; // @[Cat.scala 29:58] + wire [63:0] _T_2231 = {63'h0,mhpmc_inc_r_1}; // @[Cat.scala 29:58] + wire [63:0] mhpmc4_incr = _T_2230 + _T_2231; // @[dec_tlu_ctl.scala 2377:49] + wire _T_2240 = io_dec_csr_wraddr_r == 12'hb84; // @[dec_tlu_ctl.scala 2381:73] + wire mhpmc4h_wr_en0 = io_dec_csr_wen_r_mod & _T_2240; // @[dec_tlu_ctl.scala 2381:44] + wire _T_2246 = io_dec_csr_wraddr_r == 12'hb05; // @[dec_tlu_ctl.scala 2390:72] + wire mhpmc5_wr_en0 = io_dec_csr_wen_r_mod & _T_2246; // @[dec_tlu_ctl.scala 2390:43] + wire _T_2249 = _T_2202 | perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2391:39] + wire _T_2250 = |mhpmc_inc_r_2; // @[dec_tlu_ctl.scala 2391:86] + wire mhpmc5_wr_en1 = _T_2249 & _T_2250; // @[dec_tlu_ctl.scala 2391:66] reg [31:0] mhpmc5h; // @[lib.scala 374:16] reg [31:0] mhpmc5; // @[lib.scala 374:16] - wire [63:0] _T_2243 = {mhpmc5h,mhpmc5}; // @[Cat.scala 29:58] - wire [63:0] _T_2244 = {63'h0,mhpmc_inc_r_2}; // @[Cat.scala 29:58] - wire [63:0] mhpmc5_incr = _T_2243 + _T_2244; // @[dec_tlu_ctl.scala 2396:49] - wire _T_2252 = io_dec_csr_wraddr_r == 12'hb85; // @[dec_tlu_ctl.scala 2401:73] - wire mhpmc5h_wr_en0 = io_dec_csr_wen_r_mod & _T_2252; // @[dec_tlu_ctl.scala 2401:44] - wire _T_2258 = io_dec_csr_wraddr_r == 12'hb06; // @[dec_tlu_ctl.scala 2410:72] - wire mhpmc6_wr_en0 = io_dec_csr_wen_r_mod & _T_2258; // @[dec_tlu_ctl.scala 2410:43] - wire _T_2261 = _T_2192 | perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2411:39] - wire _T_2262 = |mhpmc_inc_r_3; // @[dec_tlu_ctl.scala 2411:86] - wire mhpmc6_wr_en1 = _T_2261 & _T_2262; // @[dec_tlu_ctl.scala 2411:66] + wire [63:0] _T_2253 = {mhpmc5h,mhpmc5}; // @[Cat.scala 29:58] + wire [63:0] _T_2254 = {63'h0,mhpmc_inc_r_2}; // @[Cat.scala 29:58] + wire [63:0] mhpmc5_incr = _T_2253 + _T_2254; // @[dec_tlu_ctl.scala 2394:49] + wire _T_2262 = io_dec_csr_wraddr_r == 12'hb85; // @[dec_tlu_ctl.scala 2399:73] + wire mhpmc5h_wr_en0 = io_dec_csr_wen_r_mod & _T_2262; // @[dec_tlu_ctl.scala 2399:44] + wire _T_2268 = io_dec_csr_wraddr_r == 12'hb06; // @[dec_tlu_ctl.scala 2408:72] + wire mhpmc6_wr_en0 = io_dec_csr_wen_r_mod & _T_2268; // @[dec_tlu_ctl.scala 2408:43] + wire _T_2271 = _T_2202 | perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2409:39] + wire _T_2272 = |mhpmc_inc_r_3; // @[dec_tlu_ctl.scala 2409:86] + wire mhpmc6_wr_en1 = _T_2271 & _T_2272; // @[dec_tlu_ctl.scala 2409:66] reg [31:0] mhpmc6h; // @[lib.scala 374:16] reg [31:0] mhpmc6; // @[lib.scala 374:16] - wire [63:0] _T_2265 = {mhpmc6h,mhpmc6}; // @[Cat.scala 29:58] - wire [63:0] _T_2266 = {63'h0,mhpmc_inc_r_3}; // @[Cat.scala 29:58] - wire [63:0] mhpmc6_incr = _T_2265 + _T_2266; // @[dec_tlu_ctl.scala 2414:49] - wire _T_2274 = io_dec_csr_wraddr_r == 12'hb86; // @[dec_tlu_ctl.scala 2419:73] - wire mhpmc6h_wr_en0 = io_dec_csr_wen_r_mod & _T_2274; // @[dec_tlu_ctl.scala 2419:44] - wire _T_2280 = io_dec_csr_wrdata_r[9:0] > 10'h204; // @[dec_tlu_ctl.scala 2430:56] - wire _T_2282 = |io_dec_csr_wrdata_r[31:10]; // @[dec_tlu_ctl.scala 2430:102] - wire _T_2283 = _T_2280 | _T_2282; // @[dec_tlu_ctl.scala 2430:71] - wire _T_2286 = io_dec_csr_wraddr_r == 12'h323; // @[dec_tlu_ctl.scala 2432:70] - wire wr_mhpme3_r = io_dec_csr_wen_r_mod & _T_2286; // @[dec_tlu_ctl.scala 2432:41] - wire _T_2290 = io_dec_csr_wraddr_r == 12'h324; // @[dec_tlu_ctl.scala 2439:70] - wire wr_mhpme4_r = io_dec_csr_wen_r_mod & _T_2290; // @[dec_tlu_ctl.scala 2439:41] - wire _T_2294 = io_dec_csr_wraddr_r == 12'h325; // @[dec_tlu_ctl.scala 2446:70] - wire wr_mhpme5_r = io_dec_csr_wen_r_mod & _T_2294; // @[dec_tlu_ctl.scala 2446:41] - wire _T_2298 = io_dec_csr_wraddr_r == 12'h326; // @[dec_tlu_ctl.scala 2453:70] - wire wr_mhpme6_r = io_dec_csr_wen_r_mod & _T_2298; // @[dec_tlu_ctl.scala 2453:41] - wire _T_2302 = io_dec_csr_wraddr_r == 12'h320; // @[dec_tlu_ctl.scala 2470:77] - wire wr_mcountinhibit_r = io_dec_csr_wen_r_mod & _T_2302; // @[dec_tlu_ctl.scala 2470:48] - wire _T_2314 = io_i0_valid_wb | io_exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 2485:51] - wire _T_2315 = _T_2314 | io_interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 2485:78] - wire _T_2316 = _T_2315 | io_dec_tlu_i0_valid_wb1; // @[dec_tlu_ctl.scala 2485:104] - wire _T_2317 = _T_2316 | io_dec_tlu_i0_exc_valid_wb1; // @[dec_tlu_ctl.scala 2485:130] - wire _T_2318 = _T_2317 | io_dec_tlu_int_valid_wb1; // @[dec_tlu_ctl.scala 2486:32] - reg _T_2321; // @[dec_tlu_ctl.scala 2488:62] - wire _T_2322 = io_i0_exception_valid_r_d1 | io_lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 2489:91] - wire _T_2323 = ~io_trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 2489:137] - wire _T_2324 = io_trigger_hit_r_d1 & _T_2323; // @[dec_tlu_ctl.scala 2489:135] - reg _T_2326; // @[dec_tlu_ctl.scala 2489:62] - reg [4:0] _T_2327; // @[dec_tlu_ctl.scala 2490:62] - reg _T_2328; // @[dec_tlu_ctl.scala 2491:62] - wire [31:0] _T_2334 = {io_core_id,4'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2343 = {21'h3,3'h0,io_mstatus[1],3'h0,io_mstatus[0],3'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2348 = {io_mtvec[30:1],1'h0,io_mtvec[0]}; // @[Cat.scala 29:58] - wire [31:0] _T_2361 = {1'h0,io_mip[5:3],16'h0,io_mip[2],3'h0,io_mip[1],3'h0,io_mip[0],3'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2374 = {1'h0,mie[5:3],16'h0,mie[2],3'h0,mie[1],3'h0,mie[0],3'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2386 = {io_mepc,1'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2391 = {28'h0,mscause}; // @[Cat.scala 29:58] - wire [31:0] _T_2399 = {meivt,10'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2402 = {meivt,meihap,2'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2405 = {28'h0,meicurpl}; // @[Cat.scala 29:58] - wire [31:0] _T_2408 = {28'h0,meicidpl}; // @[Cat.scala 29:58] - wire [31:0] _T_2411 = {28'h0,meipt}; // @[Cat.scala 29:58] - wire [31:0] _T_2414 = {23'h0,mcgc}; // @[Cat.scala 29:58] - wire [31:0] _T_2417 = {13'h0,_T_345,4'h0,mfdc_int[11:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_2421 = {16'h4000,io_dcsr[15:2],2'h3}; // @[Cat.scala 29:58] - wire [31:0] _T_2423 = {io_dpc,1'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2439 = {7'h0,dicawics[16],2'h0,dicawics[15:14],3'h0,dicawics[13:0],3'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2442 = {30'h0,mtsel}; // @[Cat.scala 29:58] - wire [31:0] _T_2471 = {26'h0,mfdht}; // @[Cat.scala 29:58] - wire [31:0] _T_2474 = {30'h0,mfdhs}; // @[Cat.scala 29:58] - wire [31:0] _T_2477 = {22'h0,mhpme3}; // @[Cat.scala 29:58] - wire [31:0] _T_2480 = {22'h0,mhpme4}; // @[Cat.scala 29:58] - wire [31:0] _T_2483 = {22'h0,mhpme5}; // @[Cat.scala 29:58] - wire [31:0] _T_2486 = {22'h0,mhpme6}; // @[Cat.scala 29:58] - wire [31:0] _T_2489 = {25'h0,temp_ncount6_2,1'h0,temp_ncount0}; // @[Cat.scala 29:58] - wire [31:0] _T_2492 = {30'h0,mpmc,1'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2495 = io_csr_pkt_csr_misa ? 32'h40001104 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2496 = io_csr_pkt_csr_mvendorid ? 32'h45 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2497 = io_csr_pkt_csr_marchid ? 32'h10 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2498 = io_csr_pkt_csr_mimpid ? 32'h1 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2499 = io_csr_pkt_csr_mhartid ? _T_2334 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2500 = io_csr_pkt_csr_mstatus ? _T_2343 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2501 = io_csr_pkt_csr_mtvec ? _T_2348 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2502 = io_csr_pkt_csr_mip ? _T_2361 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2503 = io_csr_pkt_csr_mie ? _T_2374 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2504 = io_csr_pkt_csr_mcyclel ? mcyclel : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2505 = io_csr_pkt_csr_mcycleh ? mcycleh_inc : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2506 = io_csr_pkt_csr_minstretl ? minstretl : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2507 = io_csr_pkt_csr_minstreth ? minstreth_inc : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2508 = io_csr_pkt_csr_mscratch ? mscratch : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2509 = io_csr_pkt_csr_mepc ? _T_2386 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2510 = io_csr_pkt_csr_mcause ? mcause : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2511 = io_csr_pkt_csr_mscause ? _T_2391 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2512 = io_csr_pkt_csr_mtval ? mtval : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2513 = io_csr_pkt_csr_mrac ? mrac : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2514 = io_csr_pkt_csr_mdseac ? mdseac : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2515 = io_csr_pkt_csr_meivt ? _T_2399 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2516 = io_csr_pkt_csr_meihap ? _T_2402 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2517 = io_csr_pkt_csr_meicurpl ? _T_2405 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2518 = io_csr_pkt_csr_meicidpl ? _T_2408 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2519 = io_csr_pkt_csr_meipt ? _T_2411 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2520 = io_csr_pkt_csr_mcgc ? _T_2414 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2521 = io_csr_pkt_csr_mfdc ? _T_2417 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2522 = io_csr_pkt_csr_dcsr ? _T_2421 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2523 = io_csr_pkt_csr_dpc ? _T_2423 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2524 = io_csr_pkt_csr_dicad0 ? dicad0[31:0] : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2525 = io_csr_pkt_csr_dicad0h ? dicad0h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2526 = io_csr_pkt_csr_dicad1 ? dicad1 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2527 = io_csr_pkt_csr_dicawics ? _T_2439 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2528 = io_csr_pkt_csr_mtsel ? _T_2442 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2529 = io_csr_pkt_csr_mtdata1 ? mtdata1_tsel_out : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2530 = io_csr_pkt_csr_mtdata2 ? mtdata2_tsel_out : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2531 = io_csr_pkt_csr_micect ? micect : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2532 = io_csr_pkt_csr_miccmect ? miccmect : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2533 = io_csr_pkt_csr_mdccmect ? mdccmect : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2534 = io_csr_pkt_csr_mhpmc3 ? mhpmc3 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2535 = io_csr_pkt_csr_mhpmc4 ? mhpmc4 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2536 = io_csr_pkt_csr_mhpmc5 ? mhpmc5 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2537 = io_csr_pkt_csr_mhpmc6 ? mhpmc6 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2538 = io_csr_pkt_csr_mhpmc3h ? mhpmc3h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2539 = io_csr_pkt_csr_mhpmc4h ? mhpmc4h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2540 = io_csr_pkt_csr_mhpmc5h ? mhpmc5h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2541 = io_csr_pkt_csr_mhpmc6h ? mhpmc6h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2542 = io_csr_pkt_csr_mfdht ? _T_2471 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2543 = io_csr_pkt_csr_mfdhs ? _T_2474 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2544 = io_csr_pkt_csr_mhpme3 ? _T_2477 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2545 = io_csr_pkt_csr_mhpme4 ? _T_2480 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2546 = io_csr_pkt_csr_mhpme5 ? _T_2483 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2547 = io_csr_pkt_csr_mhpme6 ? _T_2486 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2548 = io_csr_pkt_csr_mcountinhibit ? _T_2489 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2549 = io_csr_pkt_csr_mpmc ? _T_2492 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2550 = io_dec_timer_read_d ? io_dec_timer_rddata_d : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2551 = _T_2495 | _T_2496; // @[Mux.scala 27:72] - wire [31:0] _T_2552 = _T_2551 | _T_2497; // @[Mux.scala 27:72] - wire [31:0] _T_2553 = _T_2552 | _T_2498; // @[Mux.scala 27:72] - wire [31:0] _T_2554 = _T_2553 | _T_2499; // @[Mux.scala 27:72] - wire [31:0] _T_2555 = _T_2554 | _T_2500; // @[Mux.scala 27:72] - wire [31:0] _T_2556 = _T_2555 | _T_2501; // @[Mux.scala 27:72] - wire [31:0] _T_2557 = _T_2556 | _T_2502; // @[Mux.scala 27:72] - wire [31:0] _T_2558 = _T_2557 | _T_2503; // @[Mux.scala 27:72] - wire [31:0] _T_2559 = _T_2558 | _T_2504; // @[Mux.scala 27:72] - wire [31:0] _T_2560 = _T_2559 | _T_2505; // @[Mux.scala 27:72] - wire [31:0] _T_2561 = _T_2560 | _T_2506; // @[Mux.scala 27:72] + wire [63:0] _T_2275 = {mhpmc6h,mhpmc6}; // @[Cat.scala 29:58] + wire [63:0] _T_2276 = {63'h0,mhpmc_inc_r_3}; // @[Cat.scala 29:58] + wire [63:0] mhpmc6_incr = _T_2275 + _T_2276; // @[dec_tlu_ctl.scala 2412:49] + wire _T_2284 = io_dec_csr_wraddr_r == 12'hb86; // @[dec_tlu_ctl.scala 2417:73] + wire mhpmc6h_wr_en0 = io_dec_csr_wen_r_mod & _T_2284; // @[dec_tlu_ctl.scala 2417:44] + wire _T_2290 = io_dec_csr_wrdata_r[9:0] > 10'h204; // @[dec_tlu_ctl.scala 2428:56] + wire _T_2292 = |io_dec_csr_wrdata_r[31:10]; // @[dec_tlu_ctl.scala 2428:102] + wire _T_2293 = _T_2290 | _T_2292; // @[dec_tlu_ctl.scala 2428:71] + wire _T_2296 = io_dec_csr_wraddr_r == 12'h323; // @[dec_tlu_ctl.scala 2430:70] + wire wr_mhpme3_r = io_dec_csr_wen_r_mod & _T_2296; // @[dec_tlu_ctl.scala 2430:41] + wire _T_2300 = io_dec_csr_wraddr_r == 12'h324; // @[dec_tlu_ctl.scala 2437:70] + wire wr_mhpme4_r = io_dec_csr_wen_r_mod & _T_2300; // @[dec_tlu_ctl.scala 2437:41] + wire _T_2304 = io_dec_csr_wraddr_r == 12'h325; // @[dec_tlu_ctl.scala 2444:70] + wire wr_mhpme5_r = io_dec_csr_wen_r_mod & _T_2304; // @[dec_tlu_ctl.scala 2444:41] + wire _T_2308 = io_dec_csr_wraddr_r == 12'h326; // @[dec_tlu_ctl.scala 2451:70] + wire wr_mhpme6_r = io_dec_csr_wen_r_mod & _T_2308; // @[dec_tlu_ctl.scala 2451:41] + wire _T_2312 = io_dec_csr_wraddr_r == 12'h320; // @[dec_tlu_ctl.scala 2468:77] + wire wr_mcountinhibit_r = io_dec_csr_wen_r_mod & _T_2312; // @[dec_tlu_ctl.scala 2468:48] + wire _T_2324 = io_i0_valid_wb | io_exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 2483:51] + wire _T_2325 = _T_2324 | io_interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 2483:78] + wire _T_2326 = _T_2325 | io_dec_tlu_i0_valid_wb1; // @[dec_tlu_ctl.scala 2483:104] + wire _T_2327 = _T_2326 | io_dec_tlu_i0_exc_valid_wb1; // @[dec_tlu_ctl.scala 2483:130] + wire _T_2328 = _T_2327 | io_dec_tlu_int_valid_wb1; // @[dec_tlu_ctl.scala 2484:32] + reg _T_2331; // @[dec_tlu_ctl.scala 2486:62] + wire _T_2332 = io_i0_exception_valid_r_d1 | io_lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 2487:91] + wire _T_2333 = ~io_trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 2487:137] + wire _T_2334 = io_trigger_hit_r_d1 & _T_2333; // @[dec_tlu_ctl.scala 2487:135] + reg _T_2336; // @[dec_tlu_ctl.scala 2487:62] + reg [4:0] _T_2337; // @[dec_tlu_ctl.scala 2488:62] + reg _T_2338; // @[dec_tlu_ctl.scala 2489:62] + wire [31:0] _T_2344 = {io_core_id,4'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2353 = {21'h3,3'h0,io_mstatus[1],3'h0,io_mstatus[0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2358 = {io_mtvec[30:1],1'h0,io_mtvec[0]}; // @[Cat.scala 29:58] + wire [31:0] _T_2371 = {1'h0,io_mip[5:3],16'h0,io_mip[2],3'h0,io_mip[1],3'h0,io_mip[0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2384 = {1'h0,mie[5:3],16'h0,mie[2],3'h0,mie[1],3'h0,mie[0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2396 = {io_mepc,1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2401 = {28'h0,mscause}; // @[Cat.scala 29:58] + wire [31:0] _T_2409 = {meivt,10'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2412 = {meivt,meihap,2'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2415 = {28'h0,meicurpl}; // @[Cat.scala 29:58] + wire [31:0] _T_2418 = {28'h0,meicidpl}; // @[Cat.scala 29:58] + wire [31:0] _T_2421 = {28'h0,meipt}; // @[Cat.scala 29:58] + wire [31:0] _T_2424 = {23'h0,mcgc}; // @[Cat.scala 29:58] + wire [31:0] _T_2427 = {13'h0,_T_350,4'h0,mfdc_int[11:7],_T_353,mfdc_int[5:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_2431 = {16'h4000,io_dcsr[15:2],2'h3}; // @[Cat.scala 29:58] + wire [31:0] _T_2433 = {io_dpc,1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2449 = {7'h0,dicawics[16],2'h0,dicawics[15:14],3'h0,dicawics[13:0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2452 = {30'h0,mtsel}; // @[Cat.scala 29:58] + wire [31:0] _T_2481 = {26'h0,mfdht}; // @[Cat.scala 29:58] + wire [31:0] _T_2484 = {30'h0,mfdhs}; // @[Cat.scala 29:58] + wire [31:0] _T_2487 = {22'h0,mhpme3}; // @[Cat.scala 29:58] + wire [31:0] _T_2490 = {22'h0,mhpme4}; // @[Cat.scala 29:58] + wire [31:0] _T_2493 = {22'h0,mhpme5}; // @[Cat.scala 29:58] + wire [31:0] _T_2496 = {22'h0,mhpme6}; // @[Cat.scala 29:58] + wire [31:0] _T_2499 = {25'h0,temp_ncount6_2,1'h0,temp_ncount0}; // @[Cat.scala 29:58] + wire [31:0] _T_2502 = {30'h0,mpmc,1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2505 = io_csr_pkt_csr_misa ? 32'h40001104 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2506 = io_csr_pkt_csr_mvendorid ? 32'h45 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2507 = io_csr_pkt_csr_marchid ? 32'h10 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2508 = io_csr_pkt_csr_mimpid ? 32'h1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2509 = io_csr_pkt_csr_mhartid ? _T_2344 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2510 = io_csr_pkt_csr_mstatus ? _T_2353 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2511 = io_csr_pkt_csr_mtvec ? _T_2358 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2512 = io_csr_pkt_csr_mip ? _T_2371 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2513 = io_csr_pkt_csr_mie ? _T_2384 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2514 = io_csr_pkt_csr_mcyclel ? mcyclel : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2515 = io_csr_pkt_csr_mcycleh ? mcycleh_inc : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2516 = io_csr_pkt_csr_minstretl ? minstretl : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2517 = io_csr_pkt_csr_minstreth ? minstreth_inc : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2518 = io_csr_pkt_csr_mscratch ? mscratch : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2519 = io_csr_pkt_csr_mepc ? _T_2396 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2520 = io_csr_pkt_csr_mcause ? mcause : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2521 = io_csr_pkt_csr_mscause ? _T_2401 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2522 = io_csr_pkt_csr_mtval ? mtval : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2523 = io_csr_pkt_csr_mrac ? mrac : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2524 = io_csr_pkt_csr_mdseac ? mdseac : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2525 = io_csr_pkt_csr_meivt ? _T_2409 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2526 = io_csr_pkt_csr_meihap ? _T_2412 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2527 = io_csr_pkt_csr_meicurpl ? _T_2415 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2528 = io_csr_pkt_csr_meicidpl ? _T_2418 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2529 = io_csr_pkt_csr_meipt ? _T_2421 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2530 = io_csr_pkt_csr_mcgc ? _T_2424 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2531 = io_csr_pkt_csr_mfdc ? _T_2427 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2532 = io_csr_pkt_csr_dcsr ? _T_2431 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2533 = io_csr_pkt_csr_dpc ? _T_2433 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2534 = io_csr_pkt_csr_dicad0 ? dicad0[31:0] : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2535 = io_csr_pkt_csr_dicad0h ? dicad0h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2536 = io_csr_pkt_csr_dicad1 ? dicad1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2537 = io_csr_pkt_csr_dicawics ? _T_2449 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2538 = io_csr_pkt_csr_mtsel ? _T_2452 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2539 = io_csr_pkt_csr_mtdata1 ? mtdata1_tsel_out : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2540 = io_csr_pkt_csr_mtdata2 ? mtdata2_tsel_out : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2541 = io_csr_pkt_csr_micect ? micect : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2542 = io_csr_pkt_csr_miccmect ? miccmect : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2543 = io_csr_pkt_csr_mdccmect ? mdccmect : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2544 = io_csr_pkt_csr_mhpmc3 ? mhpmc3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2545 = io_csr_pkt_csr_mhpmc4 ? mhpmc4 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2546 = io_csr_pkt_csr_mhpmc5 ? mhpmc5 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2547 = io_csr_pkt_csr_mhpmc6 ? mhpmc6 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2548 = io_csr_pkt_csr_mhpmc3h ? mhpmc3h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2549 = io_csr_pkt_csr_mhpmc4h ? mhpmc4h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2550 = io_csr_pkt_csr_mhpmc5h ? mhpmc5h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2551 = io_csr_pkt_csr_mhpmc6h ? mhpmc6h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2552 = io_csr_pkt_csr_mfdht ? _T_2481 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2553 = io_csr_pkt_csr_mfdhs ? _T_2484 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2554 = io_csr_pkt_csr_mhpme3 ? _T_2487 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2555 = io_csr_pkt_csr_mhpme4 ? _T_2490 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2556 = io_csr_pkt_csr_mhpme5 ? _T_2493 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2557 = io_csr_pkt_csr_mhpme6 ? _T_2496 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2558 = io_csr_pkt_csr_mcountinhibit ? _T_2499 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2559 = io_csr_pkt_csr_mpmc ? _T_2502 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2560 = io_dec_timer_read_d ? io_dec_timer_rddata_d : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2561 = _T_2505 | _T_2506; // @[Mux.scala 27:72] wire [31:0] _T_2562 = _T_2561 | _T_2507; // @[Mux.scala 27:72] wire [31:0] _T_2563 = _T_2562 | _T_2508; // @[Mux.scala 27:72] wire [31:0] _T_2564 = _T_2563 | _T_2509; // @[Mux.scala 27:72] @@ -52385,6 +52386,16 @@ module csr_tlu( wire [31:0] _T_2602 = _T_2601 | _T_2547; // @[Mux.scala 27:72] wire [31:0] _T_2603 = _T_2602 | _T_2548; // @[Mux.scala 27:72] wire [31:0] _T_2604 = _T_2603 | _T_2549; // @[Mux.scala 27:72] + wire [31:0] _T_2605 = _T_2604 | _T_2550; // @[Mux.scala 27:72] + wire [31:0] _T_2606 = _T_2605 | _T_2551; // @[Mux.scala 27:72] + wire [31:0] _T_2607 = _T_2606 | _T_2552; // @[Mux.scala 27:72] + wire [31:0] _T_2608 = _T_2607 | _T_2553; // @[Mux.scala 27:72] + wire [31:0] _T_2609 = _T_2608 | _T_2554; // @[Mux.scala 27:72] + wire [31:0] _T_2610 = _T_2609 | _T_2555; // @[Mux.scala 27:72] + wire [31:0] _T_2611 = _T_2610 | _T_2556; // @[Mux.scala 27:72] + wire [31:0] _T_2612 = _T_2611 | _T_2557; // @[Mux.scala 27:72] + wire [31:0] _T_2613 = _T_2612 | _T_2558; // @[Mux.scala 27:72] + wire [31:0] _T_2614 = _T_2613 | _T_2559; // @[Mux.scala 27:72] rvclkhdr rvclkhdr ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), @@ -52595,84 +52606,84 @@ module csr_tlu( .io_en(rvclkhdr_34_io_en), .io_scan_mode(rvclkhdr_34_io_scan_mode) ); - assign io_dec_tlu_ic_diag_pkt_icache_wrdata = {_T_754,dicad0[31:0]}; // @[dec_tlu_ctl.scala 2155:56] - assign io_dec_tlu_ic_diag_pkt_icache_dicawics = dicawics; // @[dec_tlu_ctl.scala 2158:41] - assign io_dec_tlu_ic_diag_pkt_icache_rd_valid = icache_rd_valid_f; // @[dec_tlu_ctl.scala 2166:41] - assign io_dec_tlu_ic_diag_pkt_icache_wr_valid = icache_wr_valid_f; // @[dec_tlu_ctl.scala 2167:41] - assign io_trigger_pkt_any_0_select = io_mtdata1_t_0[7]; // @[dec_tlu_ctl.scala 2231:40] - assign io_trigger_pkt_any_0_match_pkt = io_mtdata1_t_0[4]; // @[dec_tlu_ctl.scala 2232:43] - assign io_trigger_pkt_any_0_store = io_mtdata1_t_0[1]; // @[dec_tlu_ctl.scala 2233:40] - assign io_trigger_pkt_any_0_load = io_mtdata1_t_0[0]; // @[dec_tlu_ctl.scala 2234:40] - assign io_trigger_pkt_any_0_execute = io_mtdata1_t_0[2]; // @[dec_tlu_ctl.scala 2235:40] - assign io_trigger_pkt_any_0_m = io_mtdata1_t_0[3]; // @[dec_tlu_ctl.scala 2236:40] - assign io_trigger_pkt_any_0_tdata2 = mtdata2_t_0; // @[dec_tlu_ctl.scala 2249:51] - assign io_trigger_pkt_any_1_select = io_mtdata1_t_1[7]; // @[dec_tlu_ctl.scala 2231:40] - assign io_trigger_pkt_any_1_match_pkt = io_mtdata1_t_1[4]; // @[dec_tlu_ctl.scala 2232:43] - assign io_trigger_pkt_any_1_store = io_mtdata1_t_1[1]; // @[dec_tlu_ctl.scala 2233:40] - assign io_trigger_pkt_any_1_load = io_mtdata1_t_1[0]; // @[dec_tlu_ctl.scala 2234:40] - assign io_trigger_pkt_any_1_execute = io_mtdata1_t_1[2]; // @[dec_tlu_ctl.scala 2235:40] - assign io_trigger_pkt_any_1_m = io_mtdata1_t_1[3]; // @[dec_tlu_ctl.scala 2236:40] - assign io_trigger_pkt_any_1_tdata2 = mtdata2_t_1; // @[dec_tlu_ctl.scala 2249:51] - assign io_trigger_pkt_any_2_select = io_mtdata1_t_2[7]; // @[dec_tlu_ctl.scala 2231:40] - assign io_trigger_pkt_any_2_match_pkt = io_mtdata1_t_2[4]; // @[dec_tlu_ctl.scala 2232:43] - assign io_trigger_pkt_any_2_store = io_mtdata1_t_2[1]; // @[dec_tlu_ctl.scala 2233:40] - assign io_trigger_pkt_any_2_load = io_mtdata1_t_2[0]; // @[dec_tlu_ctl.scala 2234:40] - assign io_trigger_pkt_any_2_execute = io_mtdata1_t_2[2]; // @[dec_tlu_ctl.scala 2235:40] - assign io_trigger_pkt_any_2_m = io_mtdata1_t_2[3]; // @[dec_tlu_ctl.scala 2236:40] - assign io_trigger_pkt_any_2_tdata2 = mtdata2_t_2; // @[dec_tlu_ctl.scala 2249:51] - assign io_trigger_pkt_any_3_select = io_mtdata1_t_3[7]; // @[dec_tlu_ctl.scala 2231:40] - assign io_trigger_pkt_any_3_match_pkt = io_mtdata1_t_3[4]; // @[dec_tlu_ctl.scala 2232:43] - assign io_trigger_pkt_any_3_store = io_mtdata1_t_3[1]; // @[dec_tlu_ctl.scala 2233:40] - assign io_trigger_pkt_any_3_load = io_mtdata1_t_3[0]; // @[dec_tlu_ctl.scala 2234:40] - assign io_trigger_pkt_any_3_execute = io_mtdata1_t_3[2]; // @[dec_tlu_ctl.scala 2235:40] - assign io_trigger_pkt_any_3_m = io_mtdata1_t_3[3]; // @[dec_tlu_ctl.scala 2236:40] - assign io_trigger_pkt_any_3_tdata2 = mtdata2_t_3; // @[dec_tlu_ctl.scala 2249:51] - assign io_dec_tlu_int_valid_wb1 = _T_2328; // @[dec_tlu_ctl.scala 2491:30] - assign io_dec_tlu_i0_exc_valid_wb1 = _T_2326; // @[dec_tlu_ctl.scala 2489:30] - assign io_dec_tlu_i0_valid_wb1 = _T_2321; // @[dec_tlu_ctl.scala 2488:30] - assign io_dec_tlu_mtval_wb1 = mtval; // @[dec_tlu_ctl.scala 2493:24] - assign io_dec_tlu_exc_cause_wb1 = _T_2327; // @[dec_tlu_ctl.scala 2490:30] - assign io_dec_tlu_perfcnt0 = mhpmc_inc_r_d1_0 & _T_2173; // @[dec_tlu_ctl.scala 2345:22] - assign io_dec_tlu_perfcnt1 = mhpmc_inc_r_d1_1 & _T_2178; // @[dec_tlu_ctl.scala 2346:22] - assign io_dec_tlu_perfcnt2 = mhpmc_inc_r_d1_2 & _T_2183; // @[dec_tlu_ctl.scala 2347:22] - assign io_dec_tlu_perfcnt3 = mhpmc_inc_r_d1_3 & _T_2188; // @[dec_tlu_ctl.scala 2348:22] - assign io_dec_tlu_misc_clk_override = mcgc[8]; // @[dec_tlu_ctl.scala 1718:31] - assign io_dec_tlu_dec_clk_override = mcgc[7]; // @[dec_tlu_ctl.scala 1719:31] - assign io_dec_tlu_lsu_clk_override = mcgc[4]; // @[dec_tlu_ctl.scala 1721:31] - assign io_dec_tlu_bus_clk_override = mcgc[3]; // @[dec_tlu_ctl.scala 1722:31] - assign io_dec_tlu_pic_clk_override = mcgc[2]; // @[dec_tlu_ctl.scala 1723:31] - assign io_dec_tlu_dccm_clk_override = mcgc[1]; // @[dec_tlu_ctl.scala 1724:31] - assign io_dec_tlu_icm_clk_override = mcgc[0]; // @[dec_tlu_ctl.scala 1725:31] - assign io_dec_csr_rddata_d = _T_2604 | _T_2550; // @[dec_tlu_ctl.scala 2498:21] - assign io_dec_tlu_pipelining_disable = mfdc[0]; // @[dec_tlu_ctl.scala 1768:39] - assign io_dec_tlu_wr_pause_r = _T_360 & _T_361; // @[dec_tlu_ctl.scala 1777:24] - assign io_dec_tlu_meipt = meipt; // @[dec_tlu_ctl.scala 2006:19] - assign io_dec_tlu_meicurpl = meicurpl; // @[dec_tlu_ctl.scala 1970:22] - assign io_dec_tlu_meihap = {meivt,meihap}; // @[dec_tlu_ctl.scala 1956:20] - assign io_dec_tlu_mrac_ff = mrac; // @[dec_tlu_ctl.scala 1807:21] - assign io_dec_tlu_bpred_disable = mfdc[3]; // @[dec_tlu_ctl.scala 1766:39] - assign io_dec_tlu_sideeffect_posted_disable = mfdc[6]; // @[dec_tlu_ctl.scala 1765:39] - assign io_dec_tlu_core_ecc_disable = mfdc[8]; // @[dec_tlu_ctl.scala 1764:39] - assign io_dec_tlu_external_ldfwd_disable = mfdc[11]; // @[dec_tlu_ctl.scala 1763:39] - assign io_dec_tlu_dma_qos_prty = mfdc[18:16]; // @[dec_tlu_ctl.scala 1762:39] - assign io_dec_csr_wen_r_mod = _T_1 & _T_2; // @[dec_tlu_ctl.scala 1451:23] - assign io_fw_halt_req = _T_492 & _T_493; // @[dec_tlu_ctl.scala 1842:17] - assign io_mstatus = _T_56; // @[dec_tlu_ctl.scala 1467:13] - assign io_mstatus_mie_ns = io_mstatus[0] & _T_54; // @[dec_tlu_ctl.scala 1466:20] - assign io_dcsr = _T_691; // @[dec_tlu_ctl.scala 2053:10] - assign io_mtvec = _T_62; // @[dec_tlu_ctl.scala 1479:11] - assign io_mip = _T_68; // @[dec_tlu_ctl.scala 1494:9] - assign io_mie_ns = wr_mie_r ? _T_78 : mie; // @[dec_tlu_ctl.scala 1508:12] - assign io_npc_r = _T_161 | _T_159; // @[dec_tlu_ctl.scala 1602:11] - assign io_npc_r_d1 = _T_167; // @[dec_tlu_ctl.scala 1608:14] - assign io_mepc = _T_196; // @[dec_tlu_ctl.scala 1627:10] - assign io_mdseac_locked_ns = mdseac_en | _T_479; // @[dec_tlu_ctl.scala 1825:22] - assign io_force_halt = mfdht[0] & _T_599; // @[dec_tlu_ctl.scala 1933:16] - assign io_dpc = _T_716; // @[dec_tlu_ctl.scala 2070:9] - assign io_mtdata1_t_0 = _T_863; // @[dec_tlu_ctl.scala 2226:39] - assign io_mtdata1_t_1 = _T_864; // @[dec_tlu_ctl.scala 2226:39] - assign io_mtdata1_t_2 = _T_865; // @[dec_tlu_ctl.scala 2226:39] - assign io_mtdata1_t_3 = _T_866; // @[dec_tlu_ctl.scala 2226:39] + assign io_dec_tlu_ic_diag_pkt_icache_wrdata = {_T_764,dicad0[31:0]}; // @[dec_tlu_ctl.scala 2153:56] + assign io_dec_tlu_ic_diag_pkt_icache_dicawics = dicawics; // @[dec_tlu_ctl.scala 2156:41] + assign io_dec_tlu_ic_diag_pkt_icache_rd_valid = icache_rd_valid_f; // @[dec_tlu_ctl.scala 2164:41] + assign io_dec_tlu_ic_diag_pkt_icache_wr_valid = icache_wr_valid_f; // @[dec_tlu_ctl.scala 2165:41] + assign io_trigger_pkt_any_0_select = io_mtdata1_t_0[7]; // @[dec_tlu_ctl.scala 2229:40] + assign io_trigger_pkt_any_0_match_pkt = io_mtdata1_t_0[4]; // @[dec_tlu_ctl.scala 2230:43] + assign io_trigger_pkt_any_0_store = io_mtdata1_t_0[1]; // @[dec_tlu_ctl.scala 2231:40] + assign io_trigger_pkt_any_0_load = io_mtdata1_t_0[0]; // @[dec_tlu_ctl.scala 2232:40] + assign io_trigger_pkt_any_0_execute = io_mtdata1_t_0[2]; // @[dec_tlu_ctl.scala 2233:40] + assign io_trigger_pkt_any_0_m = io_mtdata1_t_0[3]; // @[dec_tlu_ctl.scala 2234:40] + assign io_trigger_pkt_any_0_tdata2 = mtdata2_t_0; // @[dec_tlu_ctl.scala 2247:51] + assign io_trigger_pkt_any_1_select = io_mtdata1_t_1[7]; // @[dec_tlu_ctl.scala 2229:40] + assign io_trigger_pkt_any_1_match_pkt = io_mtdata1_t_1[4]; // @[dec_tlu_ctl.scala 2230:43] + assign io_trigger_pkt_any_1_store = io_mtdata1_t_1[1]; // @[dec_tlu_ctl.scala 2231:40] + assign io_trigger_pkt_any_1_load = io_mtdata1_t_1[0]; // @[dec_tlu_ctl.scala 2232:40] + assign io_trigger_pkt_any_1_execute = io_mtdata1_t_1[2]; // @[dec_tlu_ctl.scala 2233:40] + assign io_trigger_pkt_any_1_m = io_mtdata1_t_1[3]; // @[dec_tlu_ctl.scala 2234:40] + assign io_trigger_pkt_any_1_tdata2 = mtdata2_t_1; // @[dec_tlu_ctl.scala 2247:51] + assign io_trigger_pkt_any_2_select = io_mtdata1_t_2[7]; // @[dec_tlu_ctl.scala 2229:40] + assign io_trigger_pkt_any_2_match_pkt = io_mtdata1_t_2[4]; // @[dec_tlu_ctl.scala 2230:43] + assign io_trigger_pkt_any_2_store = io_mtdata1_t_2[1]; // @[dec_tlu_ctl.scala 2231:40] + assign io_trigger_pkt_any_2_load = io_mtdata1_t_2[0]; // @[dec_tlu_ctl.scala 2232:40] + assign io_trigger_pkt_any_2_execute = io_mtdata1_t_2[2]; // @[dec_tlu_ctl.scala 2233:40] + assign io_trigger_pkt_any_2_m = io_mtdata1_t_2[3]; // @[dec_tlu_ctl.scala 2234:40] + assign io_trigger_pkt_any_2_tdata2 = mtdata2_t_2; // @[dec_tlu_ctl.scala 2247:51] + assign io_trigger_pkt_any_3_select = io_mtdata1_t_3[7]; // @[dec_tlu_ctl.scala 2229:40] + assign io_trigger_pkt_any_3_match_pkt = io_mtdata1_t_3[4]; // @[dec_tlu_ctl.scala 2230:43] + assign io_trigger_pkt_any_3_store = io_mtdata1_t_3[1]; // @[dec_tlu_ctl.scala 2231:40] + assign io_trigger_pkt_any_3_load = io_mtdata1_t_3[0]; // @[dec_tlu_ctl.scala 2232:40] + assign io_trigger_pkt_any_3_execute = io_mtdata1_t_3[2]; // @[dec_tlu_ctl.scala 2233:40] + assign io_trigger_pkt_any_3_m = io_mtdata1_t_3[3]; // @[dec_tlu_ctl.scala 2234:40] + assign io_trigger_pkt_any_3_tdata2 = mtdata2_t_3; // @[dec_tlu_ctl.scala 2247:51] + assign io_dec_tlu_int_valid_wb1 = _T_2338; // @[dec_tlu_ctl.scala 2489:30] + assign io_dec_tlu_i0_exc_valid_wb1 = _T_2336; // @[dec_tlu_ctl.scala 2487:30] + assign io_dec_tlu_i0_valid_wb1 = _T_2331; // @[dec_tlu_ctl.scala 2486:30] + assign io_dec_tlu_mtval_wb1 = mtval; // @[dec_tlu_ctl.scala 2491:24] + assign io_dec_tlu_exc_cause_wb1 = _T_2337; // @[dec_tlu_ctl.scala 2488:30] + assign io_dec_tlu_perfcnt0 = mhpmc_inc_r_d1_0 & _T_2183; // @[dec_tlu_ctl.scala 2343:22] + assign io_dec_tlu_perfcnt1 = mhpmc_inc_r_d1_1 & _T_2188; // @[dec_tlu_ctl.scala 2344:22] + assign io_dec_tlu_perfcnt2 = mhpmc_inc_r_d1_2 & _T_2193; // @[dec_tlu_ctl.scala 2345:22] + assign io_dec_tlu_perfcnt3 = mhpmc_inc_r_d1_3 & _T_2198; // @[dec_tlu_ctl.scala 2346:22] + assign io_dec_tlu_misc_clk_override = mcgc[8]; // @[dec_tlu_ctl.scala 1716:31] + assign io_dec_tlu_dec_clk_override = mcgc[7]; // @[dec_tlu_ctl.scala 1717:31] + assign io_dec_tlu_lsu_clk_override = mcgc[4]; // @[dec_tlu_ctl.scala 1719:31] + assign io_dec_tlu_pic_clk_override = mcgc[2]; // @[dec_tlu_ctl.scala 1721:31] + assign io_dec_tlu_dccm_clk_override = mcgc[1]; // @[dec_tlu_ctl.scala 1722:31] + assign io_dec_tlu_icm_clk_override = mcgc[0]; // @[dec_tlu_ctl.scala 1723:31] + assign io_dec_csr_rddata_d = _T_2614 | _T_2560; // @[dec_tlu_ctl.scala 2496:21] + assign io_dec_tlu_pipelining_disable = mfdc[0]; // @[dec_tlu_ctl.scala 1766:39] + assign io_dec_tlu_wr_pause_r = _T_370 & _T_371; // @[dec_tlu_ctl.scala 1775:24] + assign io_dec_tlu_meipt = meipt; // @[dec_tlu_ctl.scala 2004:19] + assign io_dec_tlu_meicurpl = meicurpl; // @[dec_tlu_ctl.scala 1968:22] + assign io_dec_tlu_meihap = {meivt,meihap}; // @[dec_tlu_ctl.scala 1954:20] + assign io_dec_tlu_mrac_ff = mrac; // @[dec_tlu_ctl.scala 1805:21] + assign io_dec_tlu_wb_coalescing_disable = mfdc[2]; // @[dec_tlu_ctl.scala 1765:39] + assign io_dec_tlu_bpred_disable = mfdc[3]; // @[dec_tlu_ctl.scala 1764:39] + assign io_dec_tlu_sideeffect_posted_disable = mfdc[6]; // @[dec_tlu_ctl.scala 1763:39] + assign io_dec_tlu_core_ecc_disable = mfdc[8]; // @[dec_tlu_ctl.scala 1762:39] + assign io_dec_tlu_external_ldfwd_disable = mfdc[11]; // @[dec_tlu_ctl.scala 1761:39] + assign io_dec_tlu_dma_qos_prty = mfdc[18:16]; // @[dec_tlu_ctl.scala 1760:39] + assign io_dec_csr_wen_r_mod = _T_1 & _T_2; // @[dec_tlu_ctl.scala 1449:23] + assign io_fw_halt_req = _T_502 & _T_503; // @[dec_tlu_ctl.scala 1840:17] + assign io_mstatus = _T_56; // @[dec_tlu_ctl.scala 1465:13] + assign io_mstatus_mie_ns = io_mstatus[0] & _T_54; // @[dec_tlu_ctl.scala 1464:20] + assign io_dcsr = _T_701; // @[dec_tlu_ctl.scala 2051:10] + assign io_mtvec = _T_62; // @[dec_tlu_ctl.scala 1477:11] + assign io_mip = _T_68; // @[dec_tlu_ctl.scala 1492:9] + assign io_mie_ns = wr_mie_r ? _T_78 : mie; // @[dec_tlu_ctl.scala 1506:12] + assign io_npc_r = _T_161 | _T_159; // @[dec_tlu_ctl.scala 1600:11] + assign io_npc_r_d1 = _T_167; // @[dec_tlu_ctl.scala 1606:14] + assign io_mepc = _T_196; // @[dec_tlu_ctl.scala 1625:10] + assign io_mdseac_locked_ns = mdseac_en | _T_489; // @[dec_tlu_ctl.scala 1823:22] + assign io_force_halt = mfdht[0] & _T_609; // @[dec_tlu_ctl.scala 1931:16] + assign io_dpc = _T_726; // @[dec_tlu_ctl.scala 2068:9] + assign io_mtdata1_t_0 = _T_873; // @[dec_tlu_ctl.scala 2224:39] + assign io_mtdata1_t_1 = _T_874; // @[dec_tlu_ctl.scala 2224:39] + assign io_mtdata1_t_2 = _T_875; // @[dec_tlu_ctl.scala 2224:39] + assign io_mtdata1_t_3 = _T_876; // @[dec_tlu_ctl.scala 2224:39] assign rvclkhdr_io_clk = clock; // @[lib.scala 370:18] assign rvclkhdr_io_en = io_dec_csr_wen_r_mod & _T_58; // @[lib.scala 371:17] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] @@ -52704,34 +52715,34 @@ module csr_tlu( assign rvclkhdr_9_io_en = io_dec_csr_wen_r_mod & _T_337; // @[lib.scala 371:17] assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_10_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_10_io_en = io_dec_csr_wen_r_mod & _T_364; // @[lib.scala 371:17] + assign rvclkhdr_10_io_en = io_dec_csr_wen_r_mod & _T_374; // @[lib.scala 371:17] assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_11_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_11_io_en = _T_483 & _T_484; // @[lib.scala 371:17] + assign rvclkhdr_11_io_en = _T_493 & _T_494; // @[lib.scala 371:17] assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_12_io_clk = clock; // @[lib.scala 370:18] assign rvclkhdr_12_io_en = wr_micect_r | io_ic_perr_r_d1; // @[lib.scala 371:17] assign rvclkhdr_12_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_13_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_13_io_en = _T_539 | io_iccm_dma_sb_error; // @[lib.scala 371:17] + assign rvclkhdr_13_io_en = _T_549 | io_iccm_dma_sb_error; // @[lib.scala 371:17] assign rvclkhdr_13_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_14_io_clk = clock; // @[lib.scala 370:18] assign rvclkhdr_14_io_en = wr_mdccmect_r | io_lsu_single_ecc_error_r_d1; // @[lib.scala 371:17] assign rvclkhdr_14_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_15_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_15_io_en = io_dec_csr_wen_r_mod & _T_602; // @[lib.scala 371:17] + assign rvclkhdr_15_io_en = io_dec_csr_wen_r_mod & _T_612; // @[lib.scala 371:17] assign rvclkhdr_15_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_16_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_16_io_en = _T_622 | io_take_ext_int_start; // @[lib.scala 371:17] + assign rvclkhdr_16_io_en = _T_632 | io_take_ext_int_start; // @[lib.scala 371:17] assign rvclkhdr_16_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_17_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_17_io_en = _T_688 | io_take_nmi; // @[lib.scala 371:17] + assign rvclkhdr_17_io_en = _T_698 | io_take_nmi; // @[lib.scala 371:17] assign rvclkhdr_17_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_18_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_18_io_en = _T_713 | dpc_capture_npc; // @[lib.scala 371:17] + assign rvclkhdr_18_io_en = _T_723 | dpc_capture_npc; // @[lib.scala 371:17] assign rvclkhdr_18_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_19_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_19_io_en = _T_653 & _T_723; // @[lib.scala 371:17] + assign rvclkhdr_19_io_en = _T_663 & _T_733; // @[lib.scala 371:17] assign rvclkhdr_19_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_20_io_clk = clock; // @[lib.scala 370:18] assign rvclkhdr_20_io_en = wr_dicad0_r | io_ifu_ic_debug_rd_data_valid; // @[lib.scala 371:17] @@ -52740,16 +52751,16 @@ module csr_tlu( assign rvclkhdr_21_io_en = wr_dicad0h_r | io_ifu_ic_debug_rd_data_valid; // @[lib.scala 371:17] assign rvclkhdr_21_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_22_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_22_io_en = _T_962 & _T_798; // @[lib.scala 371:17] + assign rvclkhdr_22_io_en = _T_972 & _T_808; // @[lib.scala 371:17] assign rvclkhdr_22_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_23_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_23_io_en = _T_971 & _T_807; // @[lib.scala 371:17] + assign rvclkhdr_23_io_en = _T_981 & _T_817; // @[lib.scala 371:17] assign rvclkhdr_23_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_24_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_24_io_en = _T_980 & _T_816; // @[lib.scala 371:17] + assign rvclkhdr_24_io_en = _T_990 & _T_826; // @[lib.scala 371:17] assign rvclkhdr_24_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_25_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_25_io_en = _T_989 & _T_825; // @[lib.scala 371:17] + assign rvclkhdr_25_io_en = _T_999 & _T_835; // @[lib.scala 371:17] assign rvclkhdr_25_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_26_io_clk = clock; // @[lib.scala 370:18] assign rvclkhdr_26_io_en = mhpmc3_wr_en0 | mhpmc3_wr_en1; // @[lib.scala 371:17] @@ -52776,7 +52787,7 @@ module csr_tlu( assign rvclkhdr_33_io_en = mhpmc6h_wr_en0 | mhpmc6_wr_en1; // @[lib.scala 371:17] assign rvclkhdr_33_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_34_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_34_io_en = _T_2318 | io_clk_override; // @[lib.scala 345:16] + assign rvclkhdr_34_io_en = _T_2328 | io_clk_override; // @[lib.scala 345:16] assign rvclkhdr_34_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE @@ -52886,9 +52897,9 @@ initial begin _RAND_35 = {1{`RANDOM}}; meipt = _RAND_35[3:0]; _RAND_36 = {1{`RANDOM}}; - _T_691 = _RAND_36[15:0]; + _T_701 = _RAND_36[15:0]; _RAND_37 = {1{`RANDOM}}; - _T_716 = _RAND_37[30:0]; + _T_726 = _RAND_37[30:0]; _RAND_38 = {1{`RANDOM}}; dicawics = _RAND_38[16:0]; _RAND_39 = {3{`RANDOM}}; @@ -52896,7 +52907,7 @@ initial begin _RAND_40 = {1{`RANDOM}}; dicad0h = _RAND_40[31:0]; _RAND_41 = {1{`RANDOM}}; - _T_749 = _RAND_41[6:0]; + _T_759 = _RAND_41[6:0]; _RAND_42 = {1{`RANDOM}}; icache_rd_valid_f = _RAND_42[0:0]; _RAND_43 = {1{`RANDOM}}; @@ -52904,13 +52915,13 @@ initial begin _RAND_44 = {1{`RANDOM}}; mtsel = _RAND_44[1:0]; _RAND_45 = {1{`RANDOM}}; - _T_863 = _RAND_45[9:0]; + _T_873 = _RAND_45[9:0]; _RAND_46 = {1{`RANDOM}}; - _T_864 = _RAND_46[9:0]; + _T_874 = _RAND_46[9:0]; _RAND_47 = {1{`RANDOM}}; - _T_865 = _RAND_47[9:0]; + _T_875 = _RAND_47[9:0]; _RAND_48 = {1{`RANDOM}}; - _T_866 = _RAND_48[9:0]; + _T_876 = _RAND_48[9:0]; _RAND_49 = {1{`RANDOM}}; mtdata2_t_0 = _RAND_49[31:0]; _RAND_50 = {1{`RANDOM}}; @@ -52954,13 +52965,13 @@ initial begin _RAND_69 = {1{`RANDOM}}; mhpmc6 = _RAND_69[31:0]; _RAND_70 = {1{`RANDOM}}; - _T_2321 = _RAND_70[0:0]; + _T_2331 = _RAND_70[0:0]; _RAND_71 = {1{`RANDOM}}; - _T_2326 = _RAND_71[0:0]; + _T_2336 = _RAND_71[0:0]; _RAND_72 = {1{`RANDOM}}; - _T_2327 = _RAND_72[4:0]; + _T_2337 = _RAND_72[4:0]; _RAND_73 = {1{`RANDOM}}; - _T_2328 = _RAND_73[0:0]; + _T_2338 = _RAND_73[0:0]; `endif // RANDOMIZE_REG_INIT if (reset) begin mpmc_b = 1'h0; @@ -53071,10 +53082,10 @@ initial begin meipt = 4'h0; end if (reset) begin - _T_691 = 16'h0; + _T_701 = 16'h0; end if (reset) begin - _T_716 = 31'h0; + _T_726 = 31'h0; end if (reset) begin dicawics = 17'h0; @@ -53086,7 +53097,7 @@ initial begin dicad0h = 32'h0; end if (reset) begin - _T_749 = 7'h0; + _T_759 = 7'h0; end if (reset) begin icache_rd_valid_f = 1'h0; @@ -53098,16 +53109,16 @@ initial begin mtsel = 2'h0; end if (reset) begin - _T_863 = 10'h0; + _T_873 = 10'h0; end if (reset) begin - _T_864 = 10'h0; + _T_874 = 10'h0; end if (reset) begin - _T_865 = 10'h0; + _T_875 = 10'h0; end if (reset) begin - _T_866 = 10'h0; + _T_876 = 10'h0; end if (reset) begin mtdata2_t_0 = 32'h0; @@ -53173,16 +53184,16 @@ initial begin mhpmc6 = 32'h0; end if (reset) begin - _T_2321 = 1'h0; + _T_2331 = 1'h0; end if (reset) begin - _T_2326 = 1'h0; + _T_2336 = 1'h0; end if (reset) begin - _T_2327 = 5'h0; + _T_2337 = 5'h0; end if (reset) begin - _T_2328 = 1'h0; + _T_2338 = 1'h0; end `endif // RANDOMIZE end // initial @@ -53194,9 +53205,9 @@ end // initial if (reset) begin mpmc_b <= 1'h0; end else if (wr_mpmc_r) begin - mpmc_b <= _T_500; + mpmc_b <= _T_510; end else begin - mpmc_b <= _T_501; + mpmc_b <= _T_511; end end always @(posedge io_free_clk or posedge reset) begin @@ -53217,27 +53228,27 @@ end // initial if (reset) begin mdccmect <= 32'h0; end else if (wr_mdccmect_r) begin - mdccmect <= _T_515; + mdccmect <= _T_525; end else begin - mdccmect <= _T_559; + mdccmect <= _T_569; end end always @(posedge rvclkhdr_13_io_l1clk or posedge reset) begin if (reset) begin miccmect <= 32'h0; end else if (wr_miccmect_r) begin - miccmect <= _T_515; + miccmect <= _T_525; end else begin - miccmect <= _T_538; + miccmect <= _T_548; end end always @(posedge rvclkhdr_12_io_l1clk or posedge reset) begin if (reset) begin micect <= 32'h0; end else if (wr_micect_r) begin - micect <= _T_515; + micect <= _T_525; end else begin - micect <= _T_517; + micect <= _T_527; end end always @(posedge io_free_clk or posedge reset) begin @@ -53385,14 +53396,14 @@ end // initial if (reset) begin mfdc_int <= 15'h0; end else begin - mfdc_int <= {_T_341,io_dec_csr_wrdata_r[11:0]}; + mfdc_int <= {_T_347,_T_346}; end end always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin if (reset) begin mrac <= 32'h0; end else begin - mrac <= {_T_474,_T_459}; + mrac <= {_T_484,_T_469}; end end always @(posedge rvclkhdr_11_io_l1clk or posedge reset) begin @@ -53412,11 +53423,11 @@ end // initial always @(posedge io_active_clk or posedge reset) begin if (reset) begin mfdhs <= 2'h0; - end else if (_T_585) begin + end else if (_T_595) begin if (wr_mfdhs_r) begin mfdhs <= io_dec_csr_wrdata_r[1:0]; - end else if (_T_579) begin - mfdhs <= _T_583; + end else if (_T_589) begin + mfdhs <= _T_593; end end end @@ -53425,7 +53436,7 @@ end // initial force_halt_ctr_f <= 32'h0; end else if (mfdht[0]) begin if (io_debug_halt_req_f) begin - force_halt_ctr_f <= _T_590; + force_halt_ctr_f <= _T_600; end else if (io_dbg_tlu_halted_f) begin force_halt_ctr_f <= 32'h0; end @@ -53470,27 +53481,27 @@ end // initial end always @(posedge rvclkhdr_17_io_l1clk or posedge reset) begin if (reset) begin - _T_691 <= 16'h0; + _T_701 <= 16'h0; end else if (enter_debug_halt_req_le) begin - _T_691 <= _T_665; + _T_701 <= _T_675; end else if (wr_dcsr_r) begin - _T_691 <= _T_680; + _T_701 <= _T_690; end else begin - _T_691 <= _T_685; + _T_701 <= _T_695; end end always @(posedge rvclkhdr_18_io_l1clk or posedge reset) begin if (reset) begin - _T_716 <= 31'h0; + _T_726 <= 31'h0; end else begin - _T_716 <= _T_711 | _T_710; + _T_726 <= _T_721 | _T_720; end end always @(posedge rvclkhdr_19_io_l1clk or posedge reset) begin if (reset) begin dicawics <= 17'h0; end else begin - dicawics <= {_T_720,io_dec_csr_wrdata_r[16:3]}; + dicawics <= {_T_730,io_dec_csr_wrdata_r[16:3]}; end end always @(posedge rvclkhdr_20_io_l1clk or posedge reset) begin @@ -53513,12 +53524,12 @@ end // initial end always @(posedge io_active_clk or posedge reset) begin if (reset) begin - _T_749 <= 7'h0; - end else if (_T_747) begin - if (_T_742) begin - _T_749 <= io_dec_csr_wrdata_r[6:0]; + _T_759 <= 7'h0; + end else if (_T_757) begin + if (_T_752) begin + _T_759 <= io_dec_csr_wrdata_r[6:0]; end else begin - _T_749 <= io_ifu_ic_debug_rd_data[70:64]; + _T_759 <= io_ifu_ic_debug_rd_data[70:64]; end end end @@ -53526,14 +53537,14 @@ end // initial if (reset) begin icache_rd_valid_f <= 1'h0; end else begin - icache_rd_valid_f <= _T_759 & _T_761; + icache_rd_valid_f <= _T_769 & _T_771; end end always @(posedge io_active_clk or posedge reset) begin if (reset) begin icache_wr_valid_f <= 1'h0; end else begin - icache_wr_valid_f <= _T_653 & _T_764; + icache_wr_valid_f <= _T_663 & _T_774; end end always @(posedge io_csr_wr_clk or posedge reset) begin @@ -53545,38 +53556,38 @@ end // initial end always @(posedge io_active_clk or posedge reset) begin if (reset) begin - _T_863 <= 10'h0; + _T_873 <= 10'h0; end else if (wr_mtdata1_t_r_0) begin - _T_863 <= tdata_wrdata_r; + _T_873 <= tdata_wrdata_r; end else begin - _T_863 <= _T_834; + _T_873 <= _T_844; end end always @(posedge io_active_clk or posedge reset) begin if (reset) begin - _T_864 <= 10'h0; + _T_874 <= 10'h0; end else if (wr_mtdata1_t_r_1) begin - _T_864 <= tdata_wrdata_r; + _T_874 <= tdata_wrdata_r; end else begin - _T_864 <= _T_843; + _T_874 <= _T_853; end end always @(posedge io_active_clk or posedge reset) begin if (reset) begin - _T_865 <= 10'h0; + _T_875 <= 10'h0; end else if (wr_mtdata1_t_r_2) begin - _T_865 <= tdata_wrdata_r; + _T_875 <= tdata_wrdata_r; end else begin - _T_865 <= _T_852; + _T_875 <= _T_862; end end always @(posedge io_active_clk or posedge reset) begin if (reset) begin - _T_866 <= 10'h0; + _T_876 <= 10'h0; end else if (wr_mtdata1_t_r_3) begin - _T_866 <= tdata_wrdata_r; + _T_876 <= tdata_wrdata_r; end else begin - _T_866 <= _T_861; + _T_876 <= _T_871; end end always @(posedge rvclkhdr_22_io_l1clk or posedge reset) begin @@ -53611,7 +53622,7 @@ end // initial if (reset) begin mhpme3 <= 10'h0; end else if (wr_mhpme3_r) begin - if (_T_2283) begin + if (_T_2293) begin mhpme3 <= 10'h204; end else begin mhpme3 <= io_dec_csr_wrdata_r[9:0]; @@ -53622,7 +53633,7 @@ end // initial if (reset) begin mhpme4 <= 10'h0; end else if (wr_mhpme4_r) begin - if (_T_2283) begin + if (_T_2293) begin mhpme4 <= 10'h204; end else begin mhpme4 <= io_dec_csr_wrdata_r[9:0]; @@ -53633,7 +53644,7 @@ end // initial if (reset) begin mhpme5 <= 10'h0; end else if (wr_mhpme5_r) begin - if (_T_2283) begin + if (_T_2293) begin mhpme5 <= 10'h204; end else begin mhpme5 <= io_dec_csr_wrdata_r[9:0]; @@ -53644,7 +53655,7 @@ end // initial if (reset) begin mhpme6 <= 10'h0; end else if (wr_mhpme6_r) begin - if (_T_2283) begin + if (_T_2293) begin mhpme6 <= 10'h204; end else begin mhpme6 <= io_dec_csr_wrdata_r[9:0]; @@ -53655,28 +53666,28 @@ end // initial if (reset) begin mhpmc_inc_r_d1_0 <= 1'h0; end else begin - mhpmc_inc_r_d1_0 <= _T_1016 & _T_1296; + mhpmc_inc_r_d1_0 <= _T_1026 & _T_1306; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin mhpmc_inc_r_d1_1 <= 1'h0; end else begin - mhpmc_inc_r_d1_1 <= _T_1300 & _T_1580; + mhpmc_inc_r_d1_1 <= _T_1310 & _T_1590; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin mhpmc_inc_r_d1_2 <= 1'h0; end else begin - mhpmc_inc_r_d1_2 <= _T_1584 & _T_1864; + mhpmc_inc_r_d1_2 <= _T_1594 & _T_1874; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin mhpmc_inc_r_d1_3 <= 1'h0; end else begin - mhpmc_inc_r_d1_3 <= _T_1868 & _T_2148; + mhpmc_inc_r_d1_3 <= _T_1878 & _T_2158; end end always @(posedge io_free_clk or posedge reset) begin @@ -53760,30 +53771,30 @@ end // initial end always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin if (reset) begin - _T_2321 <= 1'h0; + _T_2331 <= 1'h0; end else begin - _T_2321 <= io_i0_valid_wb; + _T_2331 <= io_i0_valid_wb; end end always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin if (reset) begin - _T_2326 <= 1'h0; + _T_2336 <= 1'h0; end else begin - _T_2326 <= _T_2322 | _T_2324; + _T_2336 <= _T_2332 | _T_2334; end end always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin if (reset) begin - _T_2327 <= 5'h0; + _T_2337 <= 5'h0; end else begin - _T_2327 <= io_exc_cause_wb; + _T_2337 <= io_exc_cause_wb; end end always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin if (reset) begin - _T_2328 <= 1'h0; + _T_2338 <= 1'h0; end else begin - _T_2328 <= io_interrupt_valid_r_d1; + _T_2338 <= io_interrupt_valid_r_d1; end end endmodule @@ -53857,371 +53868,371 @@ module dec_decode_csr_read( output io_csr_pkt_postsync, output io_csr_pkt_legal ); - wire _T_1 = ~io_dec_csr_rdaddr_d[11]; // @[dec_tlu_ctl.scala 2570:129] - wire _T_3 = ~io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2570:129] - wire _T_5 = ~io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2570:129] - wire _T_7 = ~io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2570:129] - wire _T_9 = _T_1 & _T_3; // @[dec_tlu_ctl.scala 2570:198] - wire _T_10 = _T_9 & _T_5; // @[dec_tlu_ctl.scala 2570:198] - wire _T_11 = _T_10 & _T_7; // @[dec_tlu_ctl.scala 2570:198] - wire _T_15 = ~io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2570:129] - wire _T_17 = ~io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2570:129] - wire _T_19 = io_dec_csr_rdaddr_d[10] & _T_15; // @[dec_tlu_ctl.scala 2570:198] - wire _T_20 = _T_19 & _T_17; // @[dec_tlu_ctl.scala 2570:198] - wire _T_27 = ~io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2570:165] - wire _T_29 = _T_19 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_36 = io_dec_csr_rdaddr_d[10] & _T_3; // @[dec_tlu_ctl.scala 2570:198] - wire _T_37 = _T_36 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_69 = _T_10 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_70 = _T_69 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_75 = _T_15 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_94 = ~io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2570:129] - wire _T_96 = ~io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2570:129] - wire _T_101 = io_dec_csr_rdaddr_d[11] & _T_15; // @[dec_tlu_ctl.scala 2570:198] - wire _T_102 = _T_101 & _T_94; // @[dec_tlu_ctl.scala 2570:198] - wire _T_103 = _T_102 & _T_96; // @[dec_tlu_ctl.scala 2570:198] - wire _T_104 = _T_103 & _T_7; // @[dec_tlu_ctl.scala 2570:198] - wire _T_119 = io_dec_csr_rdaddr_d[7] & _T_3; // @[dec_tlu_ctl.scala 2570:198] - wire _T_120 = _T_119 & _T_5; // @[dec_tlu_ctl.scala 2570:198] - wire _T_121 = _T_120 & _T_94; // @[dec_tlu_ctl.scala 2570:198] - wire _T_122 = _T_121 & _T_96; // @[dec_tlu_ctl.scala 2570:198] - wire _T_123 = _T_122 & _T_7; // @[dec_tlu_ctl.scala 2570:198] - wire _T_138 = _T_15 & _T_3; // @[dec_tlu_ctl.scala 2570:198] - wire _T_139 = _T_138 & _T_94; // @[dec_tlu_ctl.scala 2570:198] - wire _T_140 = _T_139 & _T_96; // @[dec_tlu_ctl.scala 2570:198] - wire _T_141 = _T_140 & _T_7; // @[dec_tlu_ctl.scala 2570:198] - wire _T_142 = _T_141 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_145 = ~io_dec_csr_rdaddr_d[10]; // @[dec_tlu_ctl.scala 2570:129] - wire _T_156 = _T_145 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_157 = _T_156 & _T_94; // @[dec_tlu_ctl.scala 2570:198] - wire _T_158 = _T_157 & _T_96; // @[dec_tlu_ctl.scala 2570:198] - wire _T_159 = _T_158 & _T_7; // @[dec_tlu_ctl.scala 2570:198] - wire _T_160 = _T_159 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_172 = _T_75 & _T_7; // @[dec_tlu_ctl.scala 2570:198] - wire _T_173 = _T_172 & _T_17; // @[dec_tlu_ctl.scala 2570:198] - wire _T_182 = _T_75 & _T_17; // @[dec_tlu_ctl.scala 2570:198] - wire _T_183 = _T_182 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_191 = _T_75 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_196 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_217 = _T_1 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_218 = _T_217 & _T_5; // @[dec_tlu_ctl.scala 2570:198] - wire _T_219 = _T_218 & _T_96; // @[dec_tlu_ctl.scala 2570:198] - wire _T_220 = _T_219 & _T_7; // @[dec_tlu_ctl.scala 2570:198] - wire _T_230 = io_dec_csr_rdaddr_d[10] & _T_94; // @[dec_tlu_ctl.scala 2570:198] - wire _T_231 = _T_230 & _T_96; // @[dec_tlu_ctl.scala 2570:198] - wire _T_232 = _T_231 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_240 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[10]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_241 = _T_240 & _T_94; // @[dec_tlu_ctl.scala 2570:198] - wire _T_258 = _T_145 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_259 = _T_258 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_260 = _T_259 & _T_7; // @[dec_tlu_ctl.scala 2570:198] - wire _T_261 = _T_260 & _T_17; // @[dec_tlu_ctl.scala 2570:198] - wire _T_268 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_269 = _T_268 & _T_17; // @[dec_tlu_ctl.scala 2570:198] - wire _T_281 = _T_268 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_291 = _T_36 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_292 = _T_291 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_299 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_300 = _T_299 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_310 = _T_300 & _T_17; // @[dec_tlu_ctl.scala 2570:198] - wire _T_311 = _T_310 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_330 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_331 = _T_330 & _T_94; // @[dec_tlu_ctl.scala 2570:198] - wire _T_332 = _T_331 & _T_17; // @[dec_tlu_ctl.scala 2570:198] - wire _T_342 = _T_231 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_381 = _T_103 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_382 = _T_381 & _T_17; // @[dec_tlu_ctl.scala 2570:198] - wire _T_397 = _T_103 & _T_17; // @[dec_tlu_ctl.scala 2570:198] - wire _T_411 = _T_15 & _T_5; // @[dec_tlu_ctl.scala 2570:198] - wire _T_412 = _T_411 & _T_94; // @[dec_tlu_ctl.scala 2570:198] - wire _T_413 = _T_412 & _T_96; // @[dec_tlu_ctl.scala 2570:198] - wire _T_414 = _T_413 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_415 = _T_414 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_426 = io_dec_csr_rdaddr_d[7] & _T_94; // @[dec_tlu_ctl.scala 2570:198] - wire _T_427 = _T_426 & _T_96; // @[dec_tlu_ctl.scala 2570:198] - wire _T_428 = _T_427 & _T_7; // @[dec_tlu_ctl.scala 2570:198] - wire _T_429 = _T_428 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_444 = _T_119 & _T_94; // @[dec_tlu_ctl.scala 2570:198] - wire _T_445 = _T_444 & _T_96; // @[dec_tlu_ctl.scala 2570:198] - wire _T_446 = _T_445 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_447 = _T_446 & _T_17; // @[dec_tlu_ctl.scala 2570:198] - wire _T_460 = _T_427 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_461 = _T_460 & _T_17; // @[dec_tlu_ctl.scala 2570:198] - wire _T_478 = _T_446 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_490 = _T_15 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_491 = _T_490 & _T_94; // @[dec_tlu_ctl.scala 2570:198] - wire _T_492 = _T_491 & _T_96; // @[dec_tlu_ctl.scala 2570:198] - wire _T_493 = _T_492 & _T_7; // @[dec_tlu_ctl.scala 2570:198] - wire _T_505 = io_dec_csr_rdaddr_d[5] & _T_94; // @[dec_tlu_ctl.scala 2570:198] - wire _T_506 = _T_505 & _T_96; // @[dec_tlu_ctl.scala 2570:198] - wire _T_507 = _T_506 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_508 = _T_507 & _T_17; // @[dec_tlu_ctl.scala 2570:198] - wire _T_536 = _T_507 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_553 = _T_493 & _T_27; // @[dec_tlu_ctl.scala 2570:198] - wire _T_562 = io_dec_csr_rdaddr_d[6] & _T_5; // @[dec_tlu_ctl.scala 2570:198] - wire _T_563 = _T_562 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_564 = _T_563 & _T_17; // @[dec_tlu_ctl.scala 2570:198] - wire _T_572 = io_dec_csr_rdaddr_d[6] & _T_96; // @[dec_tlu_ctl.scala 2570:198] - wire _T_573 = _T_572 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_574 = _T_573 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_585 = _T_563 & _T_7; // @[dec_tlu_ctl.scala 2570:198] - wire _T_593 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_594 = _T_593 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_595 = _T_594 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_614 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_615 = _T_614 & _T_17; // @[dec_tlu_ctl.scala 2570:198] - wire _T_624 = io_dec_csr_rdaddr_d[6] & _T_94; // @[dec_tlu_ctl.scala 2570:198] - wire _T_625 = _T_624 & _T_96; // @[dec_tlu_ctl.scala 2570:198] - wire _T_626 = _T_625 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_668 = _T_196 & _T_96; // @[dec_tlu_ctl.scala 2570:198] - wire _T_669 = _T_668 & _T_17; // @[dec_tlu_ctl.scala 2570:198] - wire _T_685 = _T_196 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_693 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_694 = _T_693 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_695 = _T_694 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_703 = _T_624 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_716 = _T_1 & _T_5; // @[dec_tlu_ctl.scala 2570:198] - wire _T_717 = _T_716 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_718 = _T_717 & _T_7; // @[dec_tlu_ctl.scala 2570:198] - wire _T_719 = _T_718 & _T_17; // @[dec_tlu_ctl.scala 2570:198] - wire _T_726 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_727 = _T_726 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_737 = _T_230 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_738 = _T_737 & _T_17; // @[dec_tlu_ctl.scala 2570:198] - wire _T_748 = _T_726 & _T_7; // @[dec_tlu_ctl.scala 2570:198] - wire _T_749 = _T_748 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_787 = _T_311 | _T_553; // @[dec_tlu_ctl.scala 2638:81] - wire _T_799 = _T_3 & _T_5; // @[dec_tlu_ctl.scala 2570:198] - wire _T_800 = _T_799 & _T_94; // @[dec_tlu_ctl.scala 2570:198] - wire _T_801 = _T_800 & _T_96; // @[dec_tlu_ctl.scala 2570:198] - wire _T_802 = _T_801 & _T_7; // @[dec_tlu_ctl.scala 2570:198] - wire _T_803 = _T_802 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_804 = _T_787 | _T_803; // @[dec_tlu_ctl.scala 2638:121] - wire _T_813 = io_dec_csr_rdaddr_d[11] & _T_94; // @[dec_tlu_ctl.scala 2570:198] - wire _T_814 = _T_813 & _T_96; // @[dec_tlu_ctl.scala 2570:198] - wire _T_815 = _T_814 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_816 = _T_815 & _T_17; // @[dec_tlu_ctl.scala 2570:198] - wire _T_817 = _T_804 | _T_816; // @[dec_tlu_ctl.scala 2638:155] - wire _T_828 = _T_814 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_829 = _T_828 & _T_27; // @[dec_tlu_ctl.scala 2570:198] - wire _T_830 = _T_817 | _T_829; // @[dec_tlu_ctl.scala 2639:97] - wire _T_841 = io_dec_csr_rdaddr_d[7] & _T_5; // @[dec_tlu_ctl.scala 2570:198] - wire _T_842 = _T_841 & _T_94; // @[dec_tlu_ctl.scala 2570:198] - wire _T_843 = _T_842 & _T_96; // @[dec_tlu_ctl.scala 2570:198] - wire _T_844 = _T_843 & _T_7; // @[dec_tlu_ctl.scala 2570:198] - wire _T_845 = _T_844 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_869 = _T_311 | _T_70; // @[dec_tlu_ctl.scala 2640:81] - wire _T_879 = _T_869 | _T_183; // @[dec_tlu_ctl.scala 2640:121] - wire _T_889 = _T_879 | _T_342; // @[dec_tlu_ctl.scala 2640:162] - wire _T_904 = _T_1 & _T_15; // @[dec_tlu_ctl.scala 2570:198] - wire _T_905 = _T_904 & _T_3; // @[dec_tlu_ctl.scala 2570:198] - wire _T_906 = _T_905 & _T_94; // @[dec_tlu_ctl.scala 2570:198] - wire _T_907 = _T_906 & _T_96; // @[dec_tlu_ctl.scala 2570:198] - wire _T_908 = _T_907 & _T_7; // @[dec_tlu_ctl.scala 2570:198] - wire _T_909 = _T_908 & _T_27; // @[dec_tlu_ctl.scala 2570:198] - wire _T_910 = _T_889 | _T_909; // @[dec_tlu_ctl.scala 2641:105] - wire _T_922 = _T_217 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_923 = _T_922 & _T_94; // @[dec_tlu_ctl.scala 2570:198] - wire _T_924 = _T_923 & _T_96; // @[dec_tlu_ctl.scala 2570:198] - wire _T_925 = _T_924 & _T_17; // @[dec_tlu_ctl.scala 2570:198] - wire _T_926 = _T_910 | _T_925; // @[dec_tlu_ctl.scala 2641:145] - wire _T_937 = _T_231 & _T_7; // @[dec_tlu_ctl.scala 2570:198] - wire _T_938 = _T_937 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_955 = _T_1 & io_dec_csr_rdaddr_d[10]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_956 = _T_955 & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_957 = _T_956 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_958 = _T_957 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_959 = _T_958 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_960 = _T_959 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_961 = _T_960 & _T_96; // @[dec_tlu_ctl.scala 2570:198] - wire _T_962 = _T_961 & _T_7; // @[dec_tlu_ctl.scala 2570:198] - wire _T_963 = _T_962 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_964 = _T_963 & _T_27; // @[dec_tlu_ctl.scala 2570:198] - wire _T_983 = _T_1 & _T_145; // @[dec_tlu_ctl.scala 2570:198] - wire _T_984 = _T_983 & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_985 = _T_984 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_986 = _T_985 & _T_15; // @[dec_tlu_ctl.scala 2570:198] - wire _T_987 = _T_986 & _T_3; // @[dec_tlu_ctl.scala 2570:198] - wire _T_988 = _T_987 & _T_5; // @[dec_tlu_ctl.scala 2570:198] - wire _T_989 = _T_988 & _T_94; // @[dec_tlu_ctl.scala 2570:198] - wire _T_990 = _T_989 & _T_96; // @[dec_tlu_ctl.scala 2570:198] - wire _T_991 = _T_990 & _T_17; // @[dec_tlu_ctl.scala 2570:198] - wire _T_992 = _T_964 | _T_991; // @[dec_tlu_ctl.scala 2643:81] - wire _T_1013 = _T_987 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1014 = _T_1013 & _T_17; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1015 = _T_1014 & _T_27; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1016 = _T_992 | _T_1015; // @[dec_tlu_ctl.scala 2643:129] - wire _T_1032 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1033 = _T_1032 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1034 = _T_1033 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1035 = _T_1034 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1036 = _T_1035 & _T_5; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1037 = _T_1036 & _T_94; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1038 = _T_1037 & _T_7; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1039 = _T_1038 & _T_17; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1040 = _T_1039 & _T_27; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1041 = _T_1016 | _T_1040; // @[dec_tlu_ctl.scala 2644:105] - wire _T_1053 = io_dec_csr_rdaddr_d[11] & _T_145; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1054 = _T_1053 & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1055 = _T_1054 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1056 = _T_1055 & _T_3; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1057 = _T_1056 & _T_5; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1058 = _T_1057 & _T_27; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1059 = _T_1041 | _T_1058; // @[dec_tlu_ctl.scala 2644:153] - wire _T_1078 = _T_959 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1079 = _T_1078 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1080 = _T_1079 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1081 = _T_1080 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1082 = _T_1081 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1083 = _T_1082 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1084 = _T_1059 | _T_1083; // @[dec_tlu_ctl.scala 2645:105] - wire _T_1105 = _T_1079 & _T_7; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1106 = _T_1105 & _T_17; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1107 = _T_1084 | _T_1106; // @[dec_tlu_ctl.scala 2645:153] - wire _T_1125 = _T_1033 & _T_15; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1126 = _T_1125 & _T_3; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1127 = _T_1126 & _T_5; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1128 = _T_1127 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1129 = _T_1128 & _T_96; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1130 = _T_1129 & _T_7; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1131 = _T_1130 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1132 = _T_1107 | _T_1131; // @[dec_tlu_ctl.scala 2646:105] - wire _T_1152 = _T_958 & _T_3; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1153 = _T_1152 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1154 = _T_1153 & _T_96; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1155 = _T_1154 & _T_7; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1156 = _T_1155 & _T_17; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1157 = _T_1132 | _T_1156; // @[dec_tlu_ctl.scala 2646:161] - wire _T_1176 = _T_1013 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1177 = _T_1157 | _T_1176; // @[dec_tlu_ctl.scala 2647:105] - wire _T_1202 = _T_1129 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1203 = _T_1202 & _T_17; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1204 = _T_1203 & _T_27; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1205 = _T_1177 | _T_1204; // @[dec_tlu_ctl.scala 2647:161] - wire _T_1224 = _T_959 & _T_5; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1225 = _T_1224 & _T_94; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1226 = _T_1225 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1227 = _T_1226 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1228 = _T_1205 | _T_1227; // @[dec_tlu_ctl.scala 2648:97] - wire _T_1248 = _T_1224 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1249 = _T_1248 & _T_96; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1250 = _T_1249 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1251 = _T_1228 | _T_1250; // @[dec_tlu_ctl.scala 2648:153] - wire _T_1275 = _T_1130 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1276 = _T_1251 | _T_1275; // @[dec_tlu_ctl.scala 2649:105] - wire _T_1296 = _T_1013 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1297 = _T_1296 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1298 = _T_1276 | _T_1297; // @[dec_tlu_ctl.scala 2649:161] - wire _T_1315 = _T_1055 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1316 = _T_1315 & _T_5; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1317 = _T_1316 & _T_94; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1318 = _T_1317 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1319 = _T_1318 & _T_7; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1320 = _T_1298 | _T_1319; // @[dec_tlu_ctl.scala 2650:105] - wire _T_1343 = _T_1318 & _T_17; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1344 = _T_1343 & _T_27; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1345 = _T_1320 | _T_1344; // @[dec_tlu_ctl.scala 2650:161] - wire _T_1361 = _T_1057 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1362 = _T_1345 | _T_1361; // @[dec_tlu_ctl.scala 2651:105] - wire _T_1384 = _T_1249 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1385 = _T_1362 | _T_1384; // @[dec_tlu_ctl.scala 2651:161] - wire _T_1406 = _T_1225 & _T_27; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1407 = _T_1385 | _T_1406; // @[dec_tlu_ctl.scala 2652:105] - wire _T_1430 = _T_1226 & _T_7; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1431 = _T_1407 | _T_1430; // @[dec_tlu_ctl.scala 2652:161] - wire _T_1455 = _T_1153 & _T_94; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1456 = _T_1455 & _T_96; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1457 = _T_1456 & _T_7; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1458 = _T_1457 & _T_27; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1459 = _T_1431 | _T_1458; // @[dec_tlu_ctl.scala 2653:105] - wire _T_1475 = _T_1057 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1476 = _T_1459 | _T_1475; // @[dec_tlu_ctl.scala 2653:153] - wire _T_1498 = _T_986 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1499 = _T_1498 & _T_5; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1500 = _T_1499 & _T_94; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1501 = _T_1500 & _T_96; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1502 = _T_1501 & _T_7; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1503 = _T_1476 | _T_1502; // @[dec_tlu_ctl.scala 2654:113] - wire _T_1526 = _T_986 & _T_5; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1527 = _T_1526 & _T_94; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1528 = _T_1527 & _T_96; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1529 = _T_1528 & _T_17; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1530 = _T_1529 & _T_27; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1531 = _T_1503 | _T_1530; // @[dec_tlu_ctl.scala 2654:161] - wire _T_1550 = _T_1013 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1551 = _T_1531 | _T_1550; // @[dec_tlu_ctl.scala 2655:97] - wire _T_1567 = _T_1057 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1568 = _T_1551 | _T_1567; // @[dec_tlu_ctl.scala 2655:153] - wire _T_1587 = _T_1013 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2570:198] - wire _T_1588 = _T_1568 | _T_1587; // @[dec_tlu_ctl.scala 2656:113] - wire _T_1604 = _T_1057 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2570:198] - assign io_csr_pkt_csr_misa = _T_11 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2572:57] - assign io_csr_pkt_csr_mvendorid = _T_20 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2573:57] - assign io_csr_pkt_csr_marchid = _T_29 & _T_27; // @[dec_tlu_ctl.scala 2574:57] - assign io_csr_pkt_csr_mimpid = _T_37 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2575:57] - assign io_csr_pkt_csr_mhartid = _T_19 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2576:57] - assign io_csr_pkt_csr_mstatus = _T_11 & _T_27; // @[dec_tlu_ctl.scala 2577:57] - assign io_csr_pkt_csr_mtvec = _T_69 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2578:57] - assign io_csr_pkt_csr_mip = _T_75 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2579:65] - assign io_csr_pkt_csr_mie = _T_69 & _T_27; // @[dec_tlu_ctl.scala 2580:65] - assign io_csr_pkt_csr_mcyclel = _T_104 & _T_17; // @[dec_tlu_ctl.scala 2581:57] - assign io_csr_pkt_csr_mcycleh = _T_123 & _T_17; // @[dec_tlu_ctl.scala 2582:57] - assign io_csr_pkt_csr_minstretl = _T_142 & _T_27; // @[dec_tlu_ctl.scala 2583:57] - assign io_csr_pkt_csr_minstreth = _T_160 & _T_27; // @[dec_tlu_ctl.scala 2584:57] - assign io_csr_pkt_csr_mscratch = _T_173 & _T_27; // @[dec_tlu_ctl.scala 2585:57] - assign io_csr_pkt_csr_mepc = _T_182 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2586:57] - assign io_csr_pkt_csr_mcause = _T_191 & _T_27; // @[dec_tlu_ctl.scala 2587:57] - assign io_csr_pkt_csr_mscause = _T_196 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2588:57] - assign io_csr_pkt_csr_mtval = _T_191 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2589:57] - assign io_csr_pkt_csr_mrac = _T_220 & _T_17; // @[dec_tlu_ctl.scala 2590:57] - assign io_csr_pkt_csr_dmst = _T_232 & _T_17; // @[dec_tlu_ctl.scala 2591:57] - assign io_csr_pkt_csr_mdseac = _T_241 & _T_96; // @[dec_tlu_ctl.scala 2592:57] - assign io_csr_pkt_csr_meihap = _T_240 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2593:57] - assign io_csr_pkt_csr_meivt = _T_261 & _T_27; // @[dec_tlu_ctl.scala 2594:57] - assign io_csr_pkt_csr_meipt = _T_269 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2595:57] - assign io_csr_pkt_csr_meicurpl = _T_268 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2596:57] - assign io_csr_pkt_csr_meicidpl = _T_281 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2597:57] - assign io_csr_pkt_csr_dcsr = _T_292 & _T_27; // @[dec_tlu_ctl.scala 2598:57] - assign io_csr_pkt_csr_mcgc = _T_300 & _T_27; // @[dec_tlu_ctl.scala 2599:57] - assign io_csr_pkt_csr_mfdc = _T_310 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2600:57] - assign io_csr_pkt_csr_dpc = _T_292 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2601:65] - assign io_csr_pkt_csr_mtsel = _T_332 & _T_27; // @[dec_tlu_ctl.scala 2602:57] - assign io_csr_pkt_csr_mtdata1 = _T_231 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2603:57] - assign io_csr_pkt_csr_mtdata2 = _T_331 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2604:57] - assign io_csr_pkt_csr_mhpmc3 = _T_104 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2605:57] - assign io_csr_pkt_csr_mhpmc4 = _T_382 & _T_27; // @[dec_tlu_ctl.scala 2606:57] - assign io_csr_pkt_csr_mhpmc5 = _T_397 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2607:57] - assign io_csr_pkt_csr_mhpmc6 = _T_415 & _T_27; // @[dec_tlu_ctl.scala 2608:57] - assign io_csr_pkt_csr_mhpmc3h = _T_429 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2609:57] - assign io_csr_pkt_csr_mhpmc4h = _T_447 & _T_27; // @[dec_tlu_ctl.scala 2610:57] - assign io_csr_pkt_csr_mhpmc5h = _T_461 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2611:57] - assign io_csr_pkt_csr_mhpmc6h = _T_478 & _T_27; // @[dec_tlu_ctl.scala 2612:57] - assign io_csr_pkt_csr_mhpme3 = _T_493 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2613:57] - assign io_csr_pkt_csr_mhpme4 = _T_508 & _T_27; // @[dec_tlu_ctl.scala 2614:57] - assign io_csr_pkt_csr_mhpme5 = _T_508 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2615:57] - assign io_csr_pkt_csr_mhpme6 = _T_536 & _T_27; // @[dec_tlu_ctl.scala 2616:57] - assign io_csr_pkt_csr_mcountinhibit = _T_493 & _T_27; // @[dec_tlu_ctl.scala 2617:49] - assign io_csr_pkt_csr_mitctl0 = _T_564 & _T_27; // @[dec_tlu_ctl.scala 2618:57] - assign io_csr_pkt_csr_mitctl1 = _T_574 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2619:57] - assign io_csr_pkt_csr_mitb0 = _T_585 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2620:57] - assign io_csr_pkt_csr_mitb1 = _T_595 & _T_27; // @[dec_tlu_ctl.scala 2621:57] - assign io_csr_pkt_csr_mitcnt0 = _T_585 & _T_27; // @[dec_tlu_ctl.scala 2622:57] - assign io_csr_pkt_csr_mitcnt1 = _T_615 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2623:57] - assign io_csr_pkt_csr_mpmc = _T_626 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2624:57] - assign io_csr_pkt_csr_meicpct = _T_281 & _T_27; // @[dec_tlu_ctl.scala 2626:57] - assign io_csr_pkt_csr_micect = _T_669 & _T_27; // @[dec_tlu_ctl.scala 2628:57] - assign io_csr_pkt_csr_miccmect = _T_668 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2629:57] - assign io_csr_pkt_csr_mdccmect = _T_685 & _T_27; // @[dec_tlu_ctl.scala 2630:57] - assign io_csr_pkt_csr_mfdht = _T_695 & _T_27; // @[dec_tlu_ctl.scala 2631:57] - assign io_csr_pkt_csr_mfdhs = _T_703 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2632:57] - assign io_csr_pkt_csr_dicawics = _T_719 & _T_27; // @[dec_tlu_ctl.scala 2633:57] - assign io_csr_pkt_csr_dicad0h = _T_727 & _T_17; // @[dec_tlu_ctl.scala 2634:57] - assign io_csr_pkt_csr_dicad0 = _T_738 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2635:57] - assign io_csr_pkt_csr_dicad1 = _T_749 & _T_27; // @[dec_tlu_ctl.scala 2636:57] - assign io_csr_pkt_csr_dicago = _T_749 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2637:57] - assign io_csr_pkt_presync = _T_830 | _T_845; // @[dec_tlu_ctl.scala 2638:34] - assign io_csr_pkt_postsync = _T_926 | _T_938; // @[dec_tlu_ctl.scala 2640:30] - assign io_csr_pkt_legal = _T_1588 | _T_1604; // @[dec_tlu_ctl.scala 2643:26] + wire _T_1 = ~io_dec_csr_rdaddr_d[11]; // @[dec_tlu_ctl.scala 2568:129] + wire _T_3 = ~io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2568:129] + wire _T_5 = ~io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2568:129] + wire _T_7 = ~io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:129] + wire _T_9 = _T_1 & _T_3; // @[dec_tlu_ctl.scala 2568:198] + wire _T_10 = _T_9 & _T_5; // @[dec_tlu_ctl.scala 2568:198] + wire _T_11 = _T_10 & _T_7; // @[dec_tlu_ctl.scala 2568:198] + wire _T_15 = ~io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2568:129] + wire _T_17 = ~io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:129] + wire _T_19 = io_dec_csr_rdaddr_d[10] & _T_15; // @[dec_tlu_ctl.scala 2568:198] + wire _T_20 = _T_19 & _T_17; // @[dec_tlu_ctl.scala 2568:198] + wire _T_27 = ~io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2568:165] + wire _T_29 = _T_19 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_36 = io_dec_csr_rdaddr_d[10] & _T_3; // @[dec_tlu_ctl.scala 2568:198] + wire _T_37 = _T_36 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_69 = _T_10 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_70 = _T_69 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_75 = _T_15 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_94 = ~io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2568:129] + wire _T_96 = ~io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2568:129] + wire _T_101 = io_dec_csr_rdaddr_d[11] & _T_15; // @[dec_tlu_ctl.scala 2568:198] + wire _T_102 = _T_101 & _T_94; // @[dec_tlu_ctl.scala 2568:198] + wire _T_103 = _T_102 & _T_96; // @[dec_tlu_ctl.scala 2568:198] + wire _T_104 = _T_103 & _T_7; // @[dec_tlu_ctl.scala 2568:198] + wire _T_119 = io_dec_csr_rdaddr_d[7] & _T_3; // @[dec_tlu_ctl.scala 2568:198] + wire _T_120 = _T_119 & _T_5; // @[dec_tlu_ctl.scala 2568:198] + wire _T_121 = _T_120 & _T_94; // @[dec_tlu_ctl.scala 2568:198] + wire _T_122 = _T_121 & _T_96; // @[dec_tlu_ctl.scala 2568:198] + wire _T_123 = _T_122 & _T_7; // @[dec_tlu_ctl.scala 2568:198] + wire _T_138 = _T_15 & _T_3; // @[dec_tlu_ctl.scala 2568:198] + wire _T_139 = _T_138 & _T_94; // @[dec_tlu_ctl.scala 2568:198] + wire _T_140 = _T_139 & _T_96; // @[dec_tlu_ctl.scala 2568:198] + wire _T_141 = _T_140 & _T_7; // @[dec_tlu_ctl.scala 2568:198] + wire _T_142 = _T_141 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_145 = ~io_dec_csr_rdaddr_d[10]; // @[dec_tlu_ctl.scala 2568:129] + wire _T_156 = _T_145 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_157 = _T_156 & _T_94; // @[dec_tlu_ctl.scala 2568:198] + wire _T_158 = _T_157 & _T_96; // @[dec_tlu_ctl.scala 2568:198] + wire _T_159 = _T_158 & _T_7; // @[dec_tlu_ctl.scala 2568:198] + wire _T_160 = _T_159 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_172 = _T_75 & _T_7; // @[dec_tlu_ctl.scala 2568:198] + wire _T_173 = _T_172 & _T_17; // @[dec_tlu_ctl.scala 2568:198] + wire _T_182 = _T_75 & _T_17; // @[dec_tlu_ctl.scala 2568:198] + wire _T_183 = _T_182 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_191 = _T_75 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_196 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_217 = _T_1 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_218 = _T_217 & _T_5; // @[dec_tlu_ctl.scala 2568:198] + wire _T_219 = _T_218 & _T_96; // @[dec_tlu_ctl.scala 2568:198] + wire _T_220 = _T_219 & _T_7; // @[dec_tlu_ctl.scala 2568:198] + wire _T_230 = io_dec_csr_rdaddr_d[10] & _T_94; // @[dec_tlu_ctl.scala 2568:198] + wire _T_231 = _T_230 & _T_96; // @[dec_tlu_ctl.scala 2568:198] + wire _T_232 = _T_231 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_240 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[10]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_241 = _T_240 & _T_94; // @[dec_tlu_ctl.scala 2568:198] + wire _T_258 = _T_145 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_259 = _T_258 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_260 = _T_259 & _T_7; // @[dec_tlu_ctl.scala 2568:198] + wire _T_261 = _T_260 & _T_17; // @[dec_tlu_ctl.scala 2568:198] + wire _T_268 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_269 = _T_268 & _T_17; // @[dec_tlu_ctl.scala 2568:198] + wire _T_281 = _T_268 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_291 = _T_36 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_292 = _T_291 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_299 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_300 = _T_299 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_310 = _T_300 & _T_17; // @[dec_tlu_ctl.scala 2568:198] + wire _T_311 = _T_310 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_330 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_331 = _T_330 & _T_94; // @[dec_tlu_ctl.scala 2568:198] + wire _T_332 = _T_331 & _T_17; // @[dec_tlu_ctl.scala 2568:198] + wire _T_342 = _T_231 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_381 = _T_103 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_382 = _T_381 & _T_17; // @[dec_tlu_ctl.scala 2568:198] + wire _T_397 = _T_103 & _T_17; // @[dec_tlu_ctl.scala 2568:198] + wire _T_411 = _T_15 & _T_5; // @[dec_tlu_ctl.scala 2568:198] + wire _T_412 = _T_411 & _T_94; // @[dec_tlu_ctl.scala 2568:198] + wire _T_413 = _T_412 & _T_96; // @[dec_tlu_ctl.scala 2568:198] + wire _T_414 = _T_413 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_415 = _T_414 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_426 = io_dec_csr_rdaddr_d[7] & _T_94; // @[dec_tlu_ctl.scala 2568:198] + wire _T_427 = _T_426 & _T_96; // @[dec_tlu_ctl.scala 2568:198] + wire _T_428 = _T_427 & _T_7; // @[dec_tlu_ctl.scala 2568:198] + wire _T_429 = _T_428 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_444 = _T_119 & _T_94; // @[dec_tlu_ctl.scala 2568:198] + wire _T_445 = _T_444 & _T_96; // @[dec_tlu_ctl.scala 2568:198] + wire _T_446 = _T_445 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_447 = _T_446 & _T_17; // @[dec_tlu_ctl.scala 2568:198] + wire _T_460 = _T_427 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_461 = _T_460 & _T_17; // @[dec_tlu_ctl.scala 2568:198] + wire _T_478 = _T_446 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_490 = _T_15 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_491 = _T_490 & _T_94; // @[dec_tlu_ctl.scala 2568:198] + wire _T_492 = _T_491 & _T_96; // @[dec_tlu_ctl.scala 2568:198] + wire _T_493 = _T_492 & _T_7; // @[dec_tlu_ctl.scala 2568:198] + wire _T_505 = io_dec_csr_rdaddr_d[5] & _T_94; // @[dec_tlu_ctl.scala 2568:198] + wire _T_506 = _T_505 & _T_96; // @[dec_tlu_ctl.scala 2568:198] + wire _T_507 = _T_506 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_508 = _T_507 & _T_17; // @[dec_tlu_ctl.scala 2568:198] + wire _T_536 = _T_507 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_553 = _T_493 & _T_27; // @[dec_tlu_ctl.scala 2568:198] + wire _T_562 = io_dec_csr_rdaddr_d[6] & _T_5; // @[dec_tlu_ctl.scala 2568:198] + wire _T_563 = _T_562 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_564 = _T_563 & _T_17; // @[dec_tlu_ctl.scala 2568:198] + wire _T_572 = io_dec_csr_rdaddr_d[6] & _T_96; // @[dec_tlu_ctl.scala 2568:198] + wire _T_573 = _T_572 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_574 = _T_573 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_585 = _T_563 & _T_7; // @[dec_tlu_ctl.scala 2568:198] + wire _T_593 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_594 = _T_593 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_595 = _T_594 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_614 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_615 = _T_614 & _T_17; // @[dec_tlu_ctl.scala 2568:198] + wire _T_624 = io_dec_csr_rdaddr_d[6] & _T_94; // @[dec_tlu_ctl.scala 2568:198] + wire _T_625 = _T_624 & _T_96; // @[dec_tlu_ctl.scala 2568:198] + wire _T_626 = _T_625 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_668 = _T_196 & _T_96; // @[dec_tlu_ctl.scala 2568:198] + wire _T_669 = _T_668 & _T_17; // @[dec_tlu_ctl.scala 2568:198] + wire _T_685 = _T_196 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_693 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_694 = _T_693 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_695 = _T_694 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_703 = _T_624 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_716 = _T_1 & _T_5; // @[dec_tlu_ctl.scala 2568:198] + wire _T_717 = _T_716 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_718 = _T_717 & _T_7; // @[dec_tlu_ctl.scala 2568:198] + wire _T_719 = _T_718 & _T_17; // @[dec_tlu_ctl.scala 2568:198] + wire _T_726 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_727 = _T_726 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_737 = _T_230 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_738 = _T_737 & _T_17; // @[dec_tlu_ctl.scala 2568:198] + wire _T_748 = _T_726 & _T_7; // @[dec_tlu_ctl.scala 2568:198] + wire _T_749 = _T_748 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_787 = _T_311 | _T_553; // @[dec_tlu_ctl.scala 2636:81] + wire _T_799 = _T_3 & _T_5; // @[dec_tlu_ctl.scala 2568:198] + wire _T_800 = _T_799 & _T_94; // @[dec_tlu_ctl.scala 2568:198] + wire _T_801 = _T_800 & _T_96; // @[dec_tlu_ctl.scala 2568:198] + wire _T_802 = _T_801 & _T_7; // @[dec_tlu_ctl.scala 2568:198] + wire _T_803 = _T_802 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_804 = _T_787 | _T_803; // @[dec_tlu_ctl.scala 2636:121] + wire _T_813 = io_dec_csr_rdaddr_d[11] & _T_94; // @[dec_tlu_ctl.scala 2568:198] + wire _T_814 = _T_813 & _T_96; // @[dec_tlu_ctl.scala 2568:198] + wire _T_815 = _T_814 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_816 = _T_815 & _T_17; // @[dec_tlu_ctl.scala 2568:198] + wire _T_817 = _T_804 | _T_816; // @[dec_tlu_ctl.scala 2636:155] + wire _T_828 = _T_814 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_829 = _T_828 & _T_27; // @[dec_tlu_ctl.scala 2568:198] + wire _T_830 = _T_817 | _T_829; // @[dec_tlu_ctl.scala 2637:97] + wire _T_841 = io_dec_csr_rdaddr_d[7] & _T_5; // @[dec_tlu_ctl.scala 2568:198] + wire _T_842 = _T_841 & _T_94; // @[dec_tlu_ctl.scala 2568:198] + wire _T_843 = _T_842 & _T_96; // @[dec_tlu_ctl.scala 2568:198] + wire _T_844 = _T_843 & _T_7; // @[dec_tlu_ctl.scala 2568:198] + wire _T_845 = _T_844 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_869 = _T_311 | _T_70; // @[dec_tlu_ctl.scala 2638:81] + wire _T_879 = _T_869 | _T_183; // @[dec_tlu_ctl.scala 2638:121] + wire _T_889 = _T_879 | _T_342; // @[dec_tlu_ctl.scala 2638:162] + wire _T_904 = _T_1 & _T_15; // @[dec_tlu_ctl.scala 2568:198] + wire _T_905 = _T_904 & _T_3; // @[dec_tlu_ctl.scala 2568:198] + wire _T_906 = _T_905 & _T_94; // @[dec_tlu_ctl.scala 2568:198] + wire _T_907 = _T_906 & _T_96; // @[dec_tlu_ctl.scala 2568:198] + wire _T_908 = _T_907 & _T_7; // @[dec_tlu_ctl.scala 2568:198] + wire _T_909 = _T_908 & _T_27; // @[dec_tlu_ctl.scala 2568:198] + wire _T_910 = _T_889 | _T_909; // @[dec_tlu_ctl.scala 2639:105] + wire _T_922 = _T_217 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_923 = _T_922 & _T_94; // @[dec_tlu_ctl.scala 2568:198] + wire _T_924 = _T_923 & _T_96; // @[dec_tlu_ctl.scala 2568:198] + wire _T_925 = _T_924 & _T_17; // @[dec_tlu_ctl.scala 2568:198] + wire _T_926 = _T_910 | _T_925; // @[dec_tlu_ctl.scala 2639:145] + wire _T_937 = _T_231 & _T_7; // @[dec_tlu_ctl.scala 2568:198] + wire _T_938 = _T_937 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_955 = _T_1 & io_dec_csr_rdaddr_d[10]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_956 = _T_955 & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_957 = _T_956 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_958 = _T_957 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_959 = _T_958 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_960 = _T_959 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_961 = _T_960 & _T_96; // @[dec_tlu_ctl.scala 2568:198] + wire _T_962 = _T_961 & _T_7; // @[dec_tlu_ctl.scala 2568:198] + wire _T_963 = _T_962 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_964 = _T_963 & _T_27; // @[dec_tlu_ctl.scala 2568:198] + wire _T_983 = _T_1 & _T_145; // @[dec_tlu_ctl.scala 2568:198] + wire _T_984 = _T_983 & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_985 = _T_984 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_986 = _T_985 & _T_15; // @[dec_tlu_ctl.scala 2568:198] + wire _T_987 = _T_986 & _T_3; // @[dec_tlu_ctl.scala 2568:198] + wire _T_988 = _T_987 & _T_5; // @[dec_tlu_ctl.scala 2568:198] + wire _T_989 = _T_988 & _T_94; // @[dec_tlu_ctl.scala 2568:198] + wire _T_990 = _T_989 & _T_96; // @[dec_tlu_ctl.scala 2568:198] + wire _T_991 = _T_990 & _T_17; // @[dec_tlu_ctl.scala 2568:198] + wire _T_992 = _T_964 | _T_991; // @[dec_tlu_ctl.scala 2641:81] + wire _T_1013 = _T_987 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1014 = _T_1013 & _T_17; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1015 = _T_1014 & _T_27; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1016 = _T_992 | _T_1015; // @[dec_tlu_ctl.scala 2641:129] + wire _T_1032 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1033 = _T_1032 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1034 = _T_1033 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1035 = _T_1034 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1036 = _T_1035 & _T_5; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1037 = _T_1036 & _T_94; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1038 = _T_1037 & _T_7; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1039 = _T_1038 & _T_17; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1040 = _T_1039 & _T_27; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1041 = _T_1016 | _T_1040; // @[dec_tlu_ctl.scala 2642:105] + wire _T_1053 = io_dec_csr_rdaddr_d[11] & _T_145; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1054 = _T_1053 & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1055 = _T_1054 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1056 = _T_1055 & _T_3; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1057 = _T_1056 & _T_5; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1058 = _T_1057 & _T_27; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1059 = _T_1041 | _T_1058; // @[dec_tlu_ctl.scala 2642:153] + wire _T_1078 = _T_959 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1079 = _T_1078 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1080 = _T_1079 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1081 = _T_1080 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1082 = _T_1081 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1083 = _T_1082 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1084 = _T_1059 | _T_1083; // @[dec_tlu_ctl.scala 2643:105] + wire _T_1105 = _T_1079 & _T_7; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1106 = _T_1105 & _T_17; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1107 = _T_1084 | _T_1106; // @[dec_tlu_ctl.scala 2643:153] + wire _T_1125 = _T_1033 & _T_15; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1126 = _T_1125 & _T_3; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1127 = _T_1126 & _T_5; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1128 = _T_1127 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1129 = _T_1128 & _T_96; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1130 = _T_1129 & _T_7; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1131 = _T_1130 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1132 = _T_1107 | _T_1131; // @[dec_tlu_ctl.scala 2644:105] + wire _T_1152 = _T_958 & _T_3; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1153 = _T_1152 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1154 = _T_1153 & _T_96; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1155 = _T_1154 & _T_7; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1156 = _T_1155 & _T_17; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1157 = _T_1132 | _T_1156; // @[dec_tlu_ctl.scala 2644:161] + wire _T_1176 = _T_1013 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1177 = _T_1157 | _T_1176; // @[dec_tlu_ctl.scala 2645:105] + wire _T_1202 = _T_1129 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1203 = _T_1202 & _T_17; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1204 = _T_1203 & _T_27; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1205 = _T_1177 | _T_1204; // @[dec_tlu_ctl.scala 2645:161] + wire _T_1224 = _T_959 & _T_5; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1225 = _T_1224 & _T_94; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1226 = _T_1225 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1227 = _T_1226 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1228 = _T_1205 | _T_1227; // @[dec_tlu_ctl.scala 2646:97] + wire _T_1248 = _T_1224 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1249 = _T_1248 & _T_96; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1250 = _T_1249 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1251 = _T_1228 | _T_1250; // @[dec_tlu_ctl.scala 2646:153] + wire _T_1275 = _T_1130 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1276 = _T_1251 | _T_1275; // @[dec_tlu_ctl.scala 2647:105] + wire _T_1296 = _T_1013 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1297 = _T_1296 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1298 = _T_1276 | _T_1297; // @[dec_tlu_ctl.scala 2647:161] + wire _T_1315 = _T_1055 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1316 = _T_1315 & _T_5; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1317 = _T_1316 & _T_94; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1318 = _T_1317 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1319 = _T_1318 & _T_7; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1320 = _T_1298 | _T_1319; // @[dec_tlu_ctl.scala 2648:105] + wire _T_1343 = _T_1318 & _T_17; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1344 = _T_1343 & _T_27; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1345 = _T_1320 | _T_1344; // @[dec_tlu_ctl.scala 2648:161] + wire _T_1361 = _T_1057 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1362 = _T_1345 | _T_1361; // @[dec_tlu_ctl.scala 2649:105] + wire _T_1384 = _T_1249 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1385 = _T_1362 | _T_1384; // @[dec_tlu_ctl.scala 2649:161] + wire _T_1406 = _T_1225 & _T_27; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1407 = _T_1385 | _T_1406; // @[dec_tlu_ctl.scala 2650:105] + wire _T_1430 = _T_1226 & _T_7; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1431 = _T_1407 | _T_1430; // @[dec_tlu_ctl.scala 2650:161] + wire _T_1455 = _T_1153 & _T_94; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1456 = _T_1455 & _T_96; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1457 = _T_1456 & _T_7; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1458 = _T_1457 & _T_27; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1459 = _T_1431 | _T_1458; // @[dec_tlu_ctl.scala 2651:105] + wire _T_1475 = _T_1057 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1476 = _T_1459 | _T_1475; // @[dec_tlu_ctl.scala 2651:153] + wire _T_1498 = _T_986 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1499 = _T_1498 & _T_5; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1500 = _T_1499 & _T_94; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1501 = _T_1500 & _T_96; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1502 = _T_1501 & _T_7; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1503 = _T_1476 | _T_1502; // @[dec_tlu_ctl.scala 2652:113] + wire _T_1526 = _T_986 & _T_5; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1527 = _T_1526 & _T_94; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1528 = _T_1527 & _T_96; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1529 = _T_1528 & _T_17; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1530 = _T_1529 & _T_27; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1531 = _T_1503 | _T_1530; // @[dec_tlu_ctl.scala 2652:161] + wire _T_1550 = _T_1013 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1551 = _T_1531 | _T_1550; // @[dec_tlu_ctl.scala 2653:97] + wire _T_1567 = _T_1057 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1568 = _T_1551 | _T_1567; // @[dec_tlu_ctl.scala 2653:153] + wire _T_1587 = _T_1013 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2568:198] + wire _T_1588 = _T_1568 | _T_1587; // @[dec_tlu_ctl.scala 2654:113] + wire _T_1604 = _T_1057 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2568:198] + assign io_csr_pkt_csr_misa = _T_11 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2570:57] + assign io_csr_pkt_csr_mvendorid = _T_20 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2571:57] + assign io_csr_pkt_csr_marchid = _T_29 & _T_27; // @[dec_tlu_ctl.scala 2572:57] + assign io_csr_pkt_csr_mimpid = _T_37 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2573:57] + assign io_csr_pkt_csr_mhartid = _T_19 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2574:57] + assign io_csr_pkt_csr_mstatus = _T_11 & _T_27; // @[dec_tlu_ctl.scala 2575:57] + assign io_csr_pkt_csr_mtvec = _T_69 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2576:57] + assign io_csr_pkt_csr_mip = _T_75 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2577:65] + assign io_csr_pkt_csr_mie = _T_69 & _T_27; // @[dec_tlu_ctl.scala 2578:65] + assign io_csr_pkt_csr_mcyclel = _T_104 & _T_17; // @[dec_tlu_ctl.scala 2579:57] + assign io_csr_pkt_csr_mcycleh = _T_123 & _T_17; // @[dec_tlu_ctl.scala 2580:57] + assign io_csr_pkt_csr_minstretl = _T_142 & _T_27; // @[dec_tlu_ctl.scala 2581:57] + assign io_csr_pkt_csr_minstreth = _T_160 & _T_27; // @[dec_tlu_ctl.scala 2582:57] + assign io_csr_pkt_csr_mscratch = _T_173 & _T_27; // @[dec_tlu_ctl.scala 2583:57] + assign io_csr_pkt_csr_mepc = _T_182 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2584:57] + assign io_csr_pkt_csr_mcause = _T_191 & _T_27; // @[dec_tlu_ctl.scala 2585:57] + assign io_csr_pkt_csr_mscause = _T_196 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2586:57] + assign io_csr_pkt_csr_mtval = _T_191 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2587:57] + assign io_csr_pkt_csr_mrac = _T_220 & _T_17; // @[dec_tlu_ctl.scala 2588:57] + assign io_csr_pkt_csr_dmst = _T_232 & _T_17; // @[dec_tlu_ctl.scala 2589:57] + assign io_csr_pkt_csr_mdseac = _T_241 & _T_96; // @[dec_tlu_ctl.scala 2590:57] + assign io_csr_pkt_csr_meihap = _T_240 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2591:57] + assign io_csr_pkt_csr_meivt = _T_261 & _T_27; // @[dec_tlu_ctl.scala 2592:57] + assign io_csr_pkt_csr_meipt = _T_269 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2593:57] + assign io_csr_pkt_csr_meicurpl = _T_268 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2594:57] + assign io_csr_pkt_csr_meicidpl = _T_281 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2595:57] + assign io_csr_pkt_csr_dcsr = _T_292 & _T_27; // @[dec_tlu_ctl.scala 2596:57] + assign io_csr_pkt_csr_mcgc = _T_300 & _T_27; // @[dec_tlu_ctl.scala 2597:57] + assign io_csr_pkt_csr_mfdc = _T_310 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2598:57] + assign io_csr_pkt_csr_dpc = _T_292 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2599:65] + assign io_csr_pkt_csr_mtsel = _T_332 & _T_27; // @[dec_tlu_ctl.scala 2600:57] + assign io_csr_pkt_csr_mtdata1 = _T_231 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2601:57] + assign io_csr_pkt_csr_mtdata2 = _T_331 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2602:57] + assign io_csr_pkt_csr_mhpmc3 = _T_104 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2603:57] + assign io_csr_pkt_csr_mhpmc4 = _T_382 & _T_27; // @[dec_tlu_ctl.scala 2604:57] + assign io_csr_pkt_csr_mhpmc5 = _T_397 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2605:57] + assign io_csr_pkt_csr_mhpmc6 = _T_415 & _T_27; // @[dec_tlu_ctl.scala 2606:57] + assign io_csr_pkt_csr_mhpmc3h = _T_429 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2607:57] + assign io_csr_pkt_csr_mhpmc4h = _T_447 & _T_27; // @[dec_tlu_ctl.scala 2608:57] + assign io_csr_pkt_csr_mhpmc5h = _T_461 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2609:57] + assign io_csr_pkt_csr_mhpmc6h = _T_478 & _T_27; // @[dec_tlu_ctl.scala 2610:57] + assign io_csr_pkt_csr_mhpme3 = _T_493 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2611:57] + assign io_csr_pkt_csr_mhpme4 = _T_508 & _T_27; // @[dec_tlu_ctl.scala 2612:57] + assign io_csr_pkt_csr_mhpme5 = _T_508 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2613:57] + assign io_csr_pkt_csr_mhpme6 = _T_536 & _T_27; // @[dec_tlu_ctl.scala 2614:57] + assign io_csr_pkt_csr_mcountinhibit = _T_493 & _T_27; // @[dec_tlu_ctl.scala 2615:49] + assign io_csr_pkt_csr_mitctl0 = _T_564 & _T_27; // @[dec_tlu_ctl.scala 2616:57] + assign io_csr_pkt_csr_mitctl1 = _T_574 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2617:57] + assign io_csr_pkt_csr_mitb0 = _T_585 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2618:57] + assign io_csr_pkt_csr_mitb1 = _T_595 & _T_27; // @[dec_tlu_ctl.scala 2619:57] + assign io_csr_pkt_csr_mitcnt0 = _T_585 & _T_27; // @[dec_tlu_ctl.scala 2620:57] + assign io_csr_pkt_csr_mitcnt1 = _T_615 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2621:57] + assign io_csr_pkt_csr_mpmc = _T_626 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2622:57] + assign io_csr_pkt_csr_meicpct = _T_281 & _T_27; // @[dec_tlu_ctl.scala 2624:57] + assign io_csr_pkt_csr_micect = _T_669 & _T_27; // @[dec_tlu_ctl.scala 2626:57] + assign io_csr_pkt_csr_miccmect = _T_668 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2627:57] + assign io_csr_pkt_csr_mdccmect = _T_685 & _T_27; // @[dec_tlu_ctl.scala 2628:57] + assign io_csr_pkt_csr_mfdht = _T_695 & _T_27; // @[dec_tlu_ctl.scala 2629:57] + assign io_csr_pkt_csr_mfdhs = _T_703 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2630:57] + assign io_csr_pkt_csr_dicawics = _T_719 & _T_27; // @[dec_tlu_ctl.scala 2631:57] + assign io_csr_pkt_csr_dicad0h = _T_727 & _T_17; // @[dec_tlu_ctl.scala 2632:57] + assign io_csr_pkt_csr_dicad0 = _T_738 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2633:57] + assign io_csr_pkt_csr_dicad1 = _T_749 & _T_27; // @[dec_tlu_ctl.scala 2634:57] + assign io_csr_pkt_csr_dicago = _T_749 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2635:57] + assign io_csr_pkt_presync = _T_830 | _T_845; // @[dec_tlu_ctl.scala 2636:34] + assign io_csr_pkt_postsync = _T_926 | _T_938; // @[dec_tlu_ctl.scala 2638:30] + assign io_csr_pkt_legal = _T_1588 | _T_1604; // @[dec_tlu_ctl.scala 2641:26] endmodule module dec_tlu_ctl( input clock, @@ -54367,7 +54378,6 @@ module dec_tlu_ctl( output io_dec_tlu_misc_clk_override, output io_dec_tlu_dec_clk_override, output io_dec_tlu_lsu_clk_override, - output io_dec_tlu_bus_clk_override, output io_dec_tlu_pic_clk_override, output io_dec_tlu_dccm_clk_override, output io_dec_tlu_icm_clk_override, @@ -54408,6 +54418,7 @@ module dec_tlu_ctl( input io_tlu_busbuff_lsu_pmu_bus_error, input io_tlu_busbuff_lsu_pmu_bus_busy, output io_tlu_busbuff_dec_tlu_external_ldfwd_disable, + output io_tlu_busbuff_dec_tlu_wb_coalescing_disable, output io_tlu_busbuff_dec_tlu_sideeffect_posted_disable, input io_tlu_busbuff_lsu_imprecise_error_load_any, input io_tlu_busbuff_lsu_imprecise_error_store_any, @@ -54534,347 +54545,347 @@ module dec_tlu_ctl( wire rvclkhdr_3_io_clk; // @[lib.scala 343:22] wire rvclkhdr_3_io_en; // @[lib.scala 343:22] wire rvclkhdr_3_io_scan_mode; // @[lib.scala 343:22] - wire csr_clock; // @[dec_tlu_ctl.scala 818:15] - wire csr_reset; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_free_clk; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_active_clk; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_scan_mode; // @[dec_tlu_ctl.scala 818:15] - wire [31:0] csr_io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 818:15] - wire [11:0] csr_io_dec_csr_wraddr_r; // @[dec_tlu_ctl.scala 818:15] - wire [11:0] csr_io_dec_csr_rdaddr_d; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 818:15] - wire [70:0] csr_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[dec_tlu_ctl.scala 818:15] - wire [16:0] csr_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_trigger_pkt_any_0_select; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_trigger_pkt_any_0_match_pkt; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_trigger_pkt_any_0_store; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_trigger_pkt_any_0_load; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_trigger_pkt_any_0_execute; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_trigger_pkt_any_0_m; // @[dec_tlu_ctl.scala 818:15] - wire [31:0] csr_io_trigger_pkt_any_0_tdata2; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_trigger_pkt_any_1_select; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_trigger_pkt_any_1_match_pkt; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_trigger_pkt_any_1_store; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_trigger_pkt_any_1_load; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_trigger_pkt_any_1_execute; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_trigger_pkt_any_1_m; // @[dec_tlu_ctl.scala 818:15] - wire [31:0] csr_io_trigger_pkt_any_1_tdata2; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_trigger_pkt_any_2_select; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_trigger_pkt_any_2_match_pkt; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_trigger_pkt_any_2_store; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_trigger_pkt_any_2_load; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_trigger_pkt_any_2_execute; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_trigger_pkt_any_2_m; // @[dec_tlu_ctl.scala 818:15] - wire [31:0] csr_io_trigger_pkt_any_2_tdata2; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_trigger_pkt_any_3_select; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_trigger_pkt_any_3_match_pkt; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_trigger_pkt_any_3_store; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_trigger_pkt_any_3_load; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_trigger_pkt_any_3_execute; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_trigger_pkt_any_3_m; // @[dec_tlu_ctl.scala 818:15] - wire [31:0] csr_io_trigger_pkt_any_3_tdata2; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_ifu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dma_iccm_stall_any; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dma_dccm_stall_any; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_lsu_store_stall_any; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dec_pmu_presync_stall; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dec_pmu_postsync_stall; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dec_pmu_decode_stall; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_ifu_pmu_fetch_stall; // @[dec_tlu_ctl.scala 818:15] - wire [1:0] csr_io_dec_tlu_packet_r_icaf_type; // @[dec_tlu_ctl.scala 818:15] - wire [3:0] csr_io_dec_tlu_packet_r_pmu_i0_itype; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dec_tlu_packet_r_pmu_divide; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_exu_pmu_i0_br_ataken; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_exu_pmu_i0_br_misp; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dec_pmu_instr_decoded; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_ifu_pmu_instr_aligned; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_ifu_pmu_ic_miss; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_ifu_pmu_ic_hit; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dec_tlu_int_valid_wb1; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dec_tlu_i0_exc_valid_wb1; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dec_tlu_i0_valid_wb1; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dec_csr_wen_r; // @[dec_tlu_ctl.scala 818:15] - wire [31:0] csr_io_dec_tlu_mtval_wb1; // @[dec_tlu_ctl.scala 818:15] - wire [4:0] csr_io_dec_tlu_exc_cause_wb1; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dec_tlu_perfcnt0; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dec_tlu_perfcnt1; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dec_tlu_perfcnt2; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dec_tlu_perfcnt3; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dma_pmu_dccm_write; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dma_pmu_dccm_read; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dma_pmu_any_write; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dma_pmu_any_read; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_lsu_pmu_bus_busy; // @[dec_tlu_ctl.scala 818:15] - wire [30:0] csr_io_dec_tlu_i0_pc_r; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dec_tlu_misc_clk_override; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dec_tlu_dec_clk_override; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dec_tlu_lsu_clk_override; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dec_tlu_bus_clk_override; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dec_tlu_pic_clk_override; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dec_tlu_dccm_clk_override; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dec_tlu_icm_clk_override; // @[dec_tlu_ctl.scala 818:15] - wire [31:0] csr_io_dec_csr_rddata_d; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dec_tlu_pipelining_disable; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dec_tlu_wr_pause_r; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_ifu_pmu_bus_busy; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_lsu_pmu_bus_error; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_ifu_pmu_bus_error; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_lsu_pmu_bus_misaligned; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_lsu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 818:15] - wire [70:0] csr_io_ifu_ic_debug_rd_data; // @[dec_tlu_ctl.scala 818:15] - wire [3:0] csr_io_dec_tlu_meipt; // @[dec_tlu_ctl.scala 818:15] - wire [3:0] csr_io_pic_pl; // @[dec_tlu_ctl.scala 818:15] - wire [3:0] csr_io_dec_tlu_meicurpl; // @[dec_tlu_ctl.scala 818:15] - wire [29:0] csr_io_dec_tlu_meihap; // @[dec_tlu_ctl.scala 818:15] - wire [7:0] csr_io_pic_claimid; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_iccm_dma_sb_error; // @[dec_tlu_ctl.scala 818:15] - wire [31:0] csr_io_lsu_imprecise_error_addr_any; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_lsu_imprecise_error_store_any; // @[dec_tlu_ctl.scala 818:15] - wire [31:0] csr_io_dec_tlu_mrac_ff; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dec_tlu_bpred_disable; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dec_tlu_sideeffect_posted_disable; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dec_tlu_core_ecc_disable; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dec_tlu_external_ldfwd_disable; // @[dec_tlu_ctl.scala 818:15] - wire [2:0] csr_io_dec_tlu_dma_qos_prty; // @[dec_tlu_ctl.scala 818:15] - wire [31:0] csr_io_dec_illegal_inst; // @[dec_tlu_ctl.scala 818:15] - wire [3:0] csr_io_lsu_error_pkt_r_bits_mscause; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_mexintpend; // @[dec_tlu_ctl.scala 818:15] - wire [30:0] csr_io_exu_npc_r; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 818:15] - wire [30:0] csr_io_rst_vec; // @[dec_tlu_ctl.scala 818:15] - wire [27:0] csr_io_core_id; // @[dec_tlu_ctl.scala 818:15] - wire [31:0] csr_io_dec_timer_rddata_d; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dec_timer_read_d; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_rfpc_i0_r; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_fw_halt_req; // @[dec_tlu_ctl.scala 818:15] - wire [1:0] csr_io_mstatus; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_exc_or_int_valid_r; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_mret_r; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_mstatus_mie_ns; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 818:15] - wire [15:0] csr_io_dcsr; // @[dec_tlu_ctl.scala 818:15] - wire [30:0] csr_io_mtvec; // @[dec_tlu_ctl.scala 818:15] - wire [5:0] csr_io_mip; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dec_timer_t0_pulse; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dec_timer_t1_pulse; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_timer_int_sync; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_soft_int_sync; // @[dec_tlu_ctl.scala 818:15] - wire [5:0] csr_io_mie_ns; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_wr_clk; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 818:15] - wire [1:0] csr_io_lsu_fir_error; // @[dec_tlu_ctl.scala 818:15] - wire [30:0] csr_io_npc_r; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dec_tlu_flush_noredir_r_d1; // @[dec_tlu_ctl.scala 818:15] - wire [30:0] csr_io_tlu_flush_path_r_d1; // @[dec_tlu_ctl.scala 818:15] - wire [30:0] csr_io_npc_r_d1; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_reset_delayed; // @[dec_tlu_ctl.scala 818:15] - wire [30:0] csr_io_mepc; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_interrupt_valid_r; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_i0_exception_valid_r; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_e4e5_int_clk; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_lsu_i0_exc_r; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_inst_acc_r; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_inst_acc_second_r; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_take_nmi; // @[dec_tlu_ctl.scala 818:15] - wire [31:0] csr_io_lsu_error_pkt_addr_r; // @[dec_tlu_ctl.scala 818:15] - wire [4:0] csr_io_exc_cause_r; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_i0_valid_wb; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_clk_override; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_i0_exception_valid_r_d1; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 818:15] - wire [4:0] csr_io_exc_cause_wb; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_nmi_lsu_store_type; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_nmi_lsu_load_type; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_ebreak_r; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_ecall_r; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_illegal_r; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_mdseac_locked_ns; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_mdseac_locked_f; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_nmi_int_detected_f; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_ic_perr_r_d1; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_lsu_single_ecc_error_r_d1; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_lsu_idle_any_f; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_debug_halt_req_f; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_force_halt; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_take_ext_int_start; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_trigger_hit_r_d1; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_debug_halt_req; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_allow_dbg_halt_csr_write; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_internal_dbg_halt_mode_f; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_enter_debug_halt_req; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_request_debug_mode_done; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_request_debug_mode_r; // @[dec_tlu_ctl.scala 818:15] - wire [30:0] csr_io_dpc; // @[dec_tlu_ctl.scala 818:15] - wire [3:0] csr_io_update_hit_bit_r; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_take_timer_int; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_take_int_timer0_int; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_take_int_timer1_int; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_take_ext_int; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_tlu_flush_lower_r; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dec_tlu_br0_error_r; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dec_tlu_br0_start_error_r; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_misa; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_mvendorid; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_mstatus; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_mtvec; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_mip; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_mie; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_mcyclel; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_mcycleh; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_minstretl; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_minstreth; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_mscratch; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_mepc; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_mcause; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_mscause; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_mtval; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_mrac; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_meivt; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_meipt; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_meicurpl; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_meicidpl; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_dcsr; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_mcgc; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_mfdc; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_mtsel; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_mtdata1; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_mtdata2; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_mhpmc3; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_mhpmc4; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_mhpmc5; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_mhpmc6; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_mhpmc3h; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_mhpmc4h; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_mhpmc5h; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_mhpmc6h; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_mhpme3; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_mhpme4; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_mhpme5; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_mhpme6; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_mcountinhibit; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_mpmc; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_micect; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_miccmect; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_mdccmect; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_mfdht; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_mfdhs; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 818:15] - wire [9:0] csr_io_mtdata1_t_0; // @[dec_tlu_ctl.scala 818:15] - wire [9:0] csr_io_mtdata1_t_1; // @[dec_tlu_ctl.scala 818:15] - wire [9:0] csr_io_mtdata1_t_2; // @[dec_tlu_ctl.scala 818:15] - wire [9:0] csr_io_mtdata1_t_3; // @[dec_tlu_ctl.scala 818:15] - wire [11:0] csr_read_io_dec_csr_rdaddr_d; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_misa; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_mvendorid; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_mstatus; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_mtvec; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_mip; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_mie; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_mcyclel; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_mcycleh; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_minstretl; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_minstreth; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_mscratch; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_mepc; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_mcause; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_mscause; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_mtval; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_mrac; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_dmst; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_meivt; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_meipt; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_meicurpl; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_meicidpl; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_dcsr; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_mcgc; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_mfdc; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_mtsel; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_mtdata1; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_mtdata2; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_mhpmc3; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_mhpmc4; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_mhpmc5; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_mhpmc6; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_mhpmc3h; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_mhpmc4h; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_mhpmc5h; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_mhpmc6h; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_mhpme3; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_mhpme4; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_mhpme5; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_mhpme6; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_mcountinhibit; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_mitctl0; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_mitctl1; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_mitb0; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_mitb1; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_mitcnt0; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_mitcnt1; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_mpmc; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_meicpct; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_micect; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_miccmect; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_mdccmect; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_mfdht; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_mfdhs; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_csr_dicago; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_presync; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_postsync; // @[dec_tlu_ctl.scala 1011:22] - wire csr_read_io_csr_pkt_legal; // @[dec_tlu_ctl.scala 1011:22] - reg dbg_halt_state_f; // @[dec_tlu_ctl.scala 367:89] + wire csr_clock; // @[dec_tlu_ctl.scala 816:15] + wire csr_reset; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_free_clk; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_active_clk; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_scan_mode; // @[dec_tlu_ctl.scala 816:15] + wire [31:0] csr_io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 816:15] + wire [11:0] csr_io_dec_csr_wraddr_r; // @[dec_tlu_ctl.scala 816:15] + wire [11:0] csr_io_dec_csr_rdaddr_d; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 816:15] + wire [70:0] csr_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[dec_tlu_ctl.scala 816:15] + wire [16:0] csr_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_trigger_pkt_any_0_select; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_trigger_pkt_any_0_match_pkt; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_trigger_pkt_any_0_store; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_trigger_pkt_any_0_load; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_trigger_pkt_any_0_execute; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_trigger_pkt_any_0_m; // @[dec_tlu_ctl.scala 816:15] + wire [31:0] csr_io_trigger_pkt_any_0_tdata2; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_trigger_pkt_any_1_select; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_trigger_pkt_any_1_match_pkt; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_trigger_pkt_any_1_store; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_trigger_pkt_any_1_load; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_trigger_pkt_any_1_execute; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_trigger_pkt_any_1_m; // @[dec_tlu_ctl.scala 816:15] + wire [31:0] csr_io_trigger_pkt_any_1_tdata2; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_trigger_pkt_any_2_select; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_trigger_pkt_any_2_match_pkt; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_trigger_pkt_any_2_store; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_trigger_pkt_any_2_load; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_trigger_pkt_any_2_execute; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_trigger_pkt_any_2_m; // @[dec_tlu_ctl.scala 816:15] + wire [31:0] csr_io_trigger_pkt_any_2_tdata2; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_trigger_pkt_any_3_select; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_trigger_pkt_any_3_match_pkt; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_trigger_pkt_any_3_store; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_trigger_pkt_any_3_load; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_trigger_pkt_any_3_execute; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_trigger_pkt_any_3_m; // @[dec_tlu_ctl.scala 816:15] + wire [31:0] csr_io_trigger_pkt_any_3_tdata2; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_ifu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_dma_iccm_stall_any; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_dma_dccm_stall_any; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_lsu_store_stall_any; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_dec_pmu_presync_stall; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_dec_pmu_postsync_stall; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_dec_pmu_decode_stall; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_ifu_pmu_fetch_stall; // @[dec_tlu_ctl.scala 816:15] + wire [1:0] csr_io_dec_tlu_packet_r_icaf_type; // @[dec_tlu_ctl.scala 816:15] + wire [3:0] csr_io_dec_tlu_packet_r_pmu_i0_itype; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_dec_tlu_packet_r_pmu_divide; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_exu_pmu_i0_br_ataken; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_exu_pmu_i0_br_misp; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_dec_pmu_instr_decoded; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_ifu_pmu_instr_aligned; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_ifu_pmu_ic_miss; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_ifu_pmu_ic_hit; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_dec_tlu_int_valid_wb1; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_dec_tlu_i0_exc_valid_wb1; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_dec_tlu_i0_valid_wb1; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_dec_csr_wen_r; // @[dec_tlu_ctl.scala 816:15] + wire [31:0] csr_io_dec_tlu_mtval_wb1; // @[dec_tlu_ctl.scala 816:15] + wire [4:0] csr_io_dec_tlu_exc_cause_wb1; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_dec_tlu_perfcnt0; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_dec_tlu_perfcnt1; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_dec_tlu_perfcnt2; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_dec_tlu_perfcnt3; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_dma_pmu_dccm_write; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_dma_pmu_dccm_read; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_dma_pmu_any_write; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_dma_pmu_any_read; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_lsu_pmu_bus_busy; // @[dec_tlu_ctl.scala 816:15] + wire [30:0] csr_io_dec_tlu_i0_pc_r; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_dec_tlu_misc_clk_override; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_dec_tlu_dec_clk_override; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_dec_tlu_lsu_clk_override; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_dec_tlu_pic_clk_override; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_dec_tlu_dccm_clk_override; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_dec_tlu_icm_clk_override; // @[dec_tlu_ctl.scala 816:15] + wire [31:0] csr_io_dec_csr_rddata_d; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_dec_tlu_pipelining_disable; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_dec_tlu_wr_pause_r; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_ifu_pmu_bus_busy; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_lsu_pmu_bus_error; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_ifu_pmu_bus_error; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_lsu_pmu_bus_misaligned; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_lsu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 816:15] + wire [70:0] csr_io_ifu_ic_debug_rd_data; // @[dec_tlu_ctl.scala 816:15] + wire [3:0] csr_io_dec_tlu_meipt; // @[dec_tlu_ctl.scala 816:15] + wire [3:0] csr_io_pic_pl; // @[dec_tlu_ctl.scala 816:15] + wire [3:0] csr_io_dec_tlu_meicurpl; // @[dec_tlu_ctl.scala 816:15] + wire [29:0] csr_io_dec_tlu_meihap; // @[dec_tlu_ctl.scala 816:15] + wire [7:0] csr_io_pic_claimid; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_iccm_dma_sb_error; // @[dec_tlu_ctl.scala 816:15] + wire [31:0] csr_io_lsu_imprecise_error_addr_any; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_lsu_imprecise_error_store_any; // @[dec_tlu_ctl.scala 816:15] + wire [31:0] csr_io_dec_tlu_mrac_ff; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_dec_tlu_wb_coalescing_disable; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_dec_tlu_bpred_disable; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_dec_tlu_sideeffect_posted_disable; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_dec_tlu_core_ecc_disable; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_dec_tlu_external_ldfwd_disable; // @[dec_tlu_ctl.scala 816:15] + wire [2:0] csr_io_dec_tlu_dma_qos_prty; // @[dec_tlu_ctl.scala 816:15] + wire [31:0] csr_io_dec_illegal_inst; // @[dec_tlu_ctl.scala 816:15] + wire [3:0] csr_io_lsu_error_pkt_r_bits_mscause; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_mexintpend; // @[dec_tlu_ctl.scala 816:15] + wire [30:0] csr_io_exu_npc_r; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 816:15] + wire [30:0] csr_io_rst_vec; // @[dec_tlu_ctl.scala 816:15] + wire [27:0] csr_io_core_id; // @[dec_tlu_ctl.scala 816:15] + wire [31:0] csr_io_dec_timer_rddata_d; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_dec_timer_read_d; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_rfpc_i0_r; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_fw_halt_req; // @[dec_tlu_ctl.scala 816:15] + wire [1:0] csr_io_mstatus; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_exc_or_int_valid_r; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_mret_r; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_mstatus_mie_ns; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 816:15] + wire [15:0] csr_io_dcsr; // @[dec_tlu_ctl.scala 816:15] + wire [30:0] csr_io_mtvec; // @[dec_tlu_ctl.scala 816:15] + wire [5:0] csr_io_mip; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_dec_timer_t0_pulse; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_dec_timer_t1_pulse; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_timer_int_sync; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_soft_int_sync; // @[dec_tlu_ctl.scala 816:15] + wire [5:0] csr_io_mie_ns; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_wr_clk; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 816:15] + wire [1:0] csr_io_lsu_fir_error; // @[dec_tlu_ctl.scala 816:15] + wire [30:0] csr_io_npc_r; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_dec_tlu_flush_noredir_r_d1; // @[dec_tlu_ctl.scala 816:15] + wire [30:0] csr_io_tlu_flush_path_r_d1; // @[dec_tlu_ctl.scala 816:15] + wire [30:0] csr_io_npc_r_d1; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_reset_delayed; // @[dec_tlu_ctl.scala 816:15] + wire [30:0] csr_io_mepc; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_interrupt_valid_r; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_i0_exception_valid_r; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_e4e5_int_clk; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_lsu_i0_exc_r; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_inst_acc_r; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_inst_acc_second_r; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_take_nmi; // @[dec_tlu_ctl.scala 816:15] + wire [31:0] csr_io_lsu_error_pkt_addr_r; // @[dec_tlu_ctl.scala 816:15] + wire [4:0] csr_io_exc_cause_r; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_i0_valid_wb; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_clk_override; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_i0_exception_valid_r_d1; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 816:15] + wire [4:0] csr_io_exc_cause_wb; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_nmi_lsu_store_type; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_nmi_lsu_load_type; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_ebreak_r; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_ecall_r; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_illegal_r; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_mdseac_locked_ns; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_mdseac_locked_f; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_nmi_int_detected_f; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_ic_perr_r_d1; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_lsu_single_ecc_error_r_d1; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_lsu_idle_any_f; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_debug_halt_req_f; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_force_halt; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_take_ext_int_start; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_trigger_hit_r_d1; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_debug_halt_req; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_allow_dbg_halt_csr_write; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_internal_dbg_halt_mode_f; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_enter_debug_halt_req; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_request_debug_mode_done; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_request_debug_mode_r; // @[dec_tlu_ctl.scala 816:15] + wire [30:0] csr_io_dpc; // @[dec_tlu_ctl.scala 816:15] + wire [3:0] csr_io_update_hit_bit_r; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_take_timer_int; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_take_int_timer0_int; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_take_int_timer1_int; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_take_ext_int; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_tlu_flush_lower_r; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_dec_tlu_br0_error_r; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_dec_tlu_br0_start_error_r; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_misa; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_mvendorid; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_mstatus; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_mtvec; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_mip; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_mie; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_mcyclel; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_mcycleh; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_minstretl; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_minstreth; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_mscratch; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_mepc; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_mcause; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_mscause; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_mtval; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_mrac; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_meivt; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_meipt; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_meicurpl; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_meicidpl; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_dcsr; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_mcgc; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_mfdc; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_mtsel; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_mtdata1; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_mtdata2; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_mhpmc3; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_mhpmc4; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_mhpmc5; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_mhpmc6; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_mhpmc3h; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_mhpmc4h; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_mhpmc5h; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_mhpmc6h; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_mhpme3; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_mhpme4; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_mhpme5; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_mhpme6; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_mcountinhibit; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_mpmc; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_micect; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_miccmect; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_mdccmect; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_mfdht; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_mfdhs; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 816:15] + wire csr_io_csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 816:15] + wire [9:0] csr_io_mtdata1_t_0; // @[dec_tlu_ctl.scala 816:15] + wire [9:0] csr_io_mtdata1_t_1; // @[dec_tlu_ctl.scala 816:15] + wire [9:0] csr_io_mtdata1_t_2; // @[dec_tlu_ctl.scala 816:15] + wire [9:0] csr_io_mtdata1_t_3; // @[dec_tlu_ctl.scala 816:15] + wire [11:0] csr_read_io_dec_csr_rdaddr_d; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_misa; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_mvendorid; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_mstatus; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_mtvec; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_mip; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_mie; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_mcyclel; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_mcycleh; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_minstretl; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_minstreth; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_mscratch; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_mepc; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_mcause; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_mscause; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_mtval; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_mrac; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_dmst; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_meivt; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_meipt; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_meicurpl; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_meicidpl; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_dcsr; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_mcgc; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_mfdc; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_mtsel; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_mtdata1; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_mtdata2; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_mhpmc3; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_mhpmc4; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_mhpmc5; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_mhpmc6; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_mhpmc3h; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_mhpmc4h; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_mhpmc5h; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_mhpmc6h; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_mhpme3; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_mhpme4; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_mhpme5; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_mhpme6; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_mcountinhibit; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_mitctl0; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_mitctl1; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_mitb0; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_mitb1; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_mitcnt0; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_mitcnt1; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_mpmc; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_meicpct; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_micect; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_miccmect; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_mdccmect; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_mfdht; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_mfdhs; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_csr_dicago; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_presync; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_postsync; // @[dec_tlu_ctl.scala 1009:22] + wire csr_read_io_csr_pkt_legal; // @[dec_tlu_ctl.scala 1009:22] + reg dbg_halt_state_f; // @[dec_tlu_ctl.scala 365:89] wire _T = ~dbg_halt_state_f; // @[dec_tlu_ctl.scala 274:39] - reg mpc_halt_state_f; // @[dec_tlu_ctl.scala 362:89] + reg mpc_halt_state_f; // @[dec_tlu_ctl.scala 360:89] wire [2:0] _T_3 = {io_i_cpu_run_req,io_mpc_debug_halt_req,io_mpc_debug_run_req}; // @[Cat.scala 29:58] wire [3:0] _T_6 = {io_nmi_int,io_timer_int,io_soft_int,io_i_cpu_halt_req}; // @[Cat.scala 29:58] reg [6:0] _T_8; // @[lib.scala 37:81] @@ -54884,405 +54895,405 @@ module dec_tlu_ctl( wire i_cpu_run_req_sync = syncro_ff[2]; // @[dec_tlu_ctl.scala 306:59] wire mpc_debug_halt_req_sync_raw = syncro_ff[1]; // @[dec_tlu_ctl.scala 307:51] wire mpc_debug_run_req_sync = syncro_ff[0]; // @[dec_tlu_ctl.scala 308:51] - wire dec_csr_wen_r_mod = csr_io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 1004:31] - reg lsu_exc_valid_r_d1; // @[dec_tlu_ctl.scala 613:74] + wire dec_csr_wen_r_mod = csr_io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 1002:31] + reg lsu_exc_valid_r_d1; // @[dec_tlu_ctl.scala 611:74] wire _T_11 = io_lsu_error_pkt_r_valid | lsu_exc_valid_r_d1; // @[dec_tlu_ctl.scala 312:67] reg e5_valid; // @[dec_tlu_ctl.scala 324:97] wire e4e5_valid = io_dec_tlu_i0_valid_r | e5_valid; // @[dec_tlu_ctl.scala 315:30] reg debug_mode_status; // @[dec_tlu_ctl.scala 325:81] - reg i_cpu_run_req_d1_raw; // @[dec_tlu_ctl.scala 573:80] - reg nmi_int_delayed; // @[dec_tlu_ctl.scala 340:72] - wire _T_37 = ~nmi_int_delayed; // @[dec_tlu_ctl.scala 349:45] - wire _T_38 = nmi_int_sync & _T_37; // @[dec_tlu_ctl.scala 349:43] - reg mdseac_locked_f; // @[dec_tlu_ctl.scala 606:89] - wire _T_35 = ~mdseac_locked_f; // @[dec_tlu_ctl.scala 347:32] - wire _T_36 = io_tlu_busbuff_lsu_imprecise_error_load_any | io_tlu_busbuff_lsu_imprecise_error_store_any; // @[dec_tlu_ctl.scala 347:96] - wire nmi_lsu_detected = _T_35 & _T_36; // @[dec_tlu_ctl.scala 347:49] - wire _T_39 = _T_38 | nmi_lsu_detected; // @[dec_tlu_ctl.scala 349:63] - reg nmi_int_detected_f; // @[dec_tlu_ctl.scala 341:72] - reg take_nmi_r_d1; // @[dec_tlu_ctl.scala 815:98] - wire _T_40 = ~take_nmi_r_d1; // @[dec_tlu_ctl.scala 349:106] - wire _T_41 = nmi_int_detected_f & _T_40; // @[dec_tlu_ctl.scala 349:104] - wire _T_42 = _T_39 | _T_41; // @[dec_tlu_ctl.scala 349:82] - reg take_ext_int_start_d3; // @[dec_tlu_ctl.scala 746:62] - wire _T_43 = |io_lsu_fir_error; // @[dec_tlu_ctl.scala 349:165] - wire _T_44 = take_ext_int_start_d3 & _T_43; // @[dec_tlu_ctl.scala 349:146] - wire nmi_int_detected = _T_42 | _T_44; // @[dec_tlu_ctl.scala 349:122] - wire _T_631 = ~io_dec_csr_stall_int_ff; // @[dec_tlu_ctl.scala 723:23] - wire mstatus_mie_ns = csr_io_mstatus_mie_ns; // @[dec_tlu_ctl.scala 1003:31] - wire _T_632 = _T_631 & mstatus_mie_ns; // @[dec_tlu_ctl.scala 723:48] - wire [5:0] mip = csr_io_mip; // @[dec_tlu_ctl.scala 1009:31] - wire _T_634 = _T_632 & mip[1]; // @[dec_tlu_ctl.scala 723:65] - wire [5:0] mie_ns = csr_io_mie_ns; // @[dec_tlu_ctl.scala 998:31] - wire timer_int_ready = _T_634 & mie_ns[1]; // @[dec_tlu_ctl.scala 723:83] - wire _T_391 = nmi_int_detected | timer_int_ready; // @[dec_tlu_ctl.scala 600:66] - wire _T_628 = _T_632 & mip[0]; // @[dec_tlu_ctl.scala 722:65] - wire soft_int_ready = _T_628 & mie_ns[0]; // @[dec_tlu_ctl.scala 722:83] - wire _T_392 = _T_391 | soft_int_ready; // @[dec_tlu_ctl.scala 600:84] - reg int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 580:73] - wire _T_393 = _T_392 | int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 600:101] - reg int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 581:73] - wire _T_394 = _T_393 | int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 600:125] - wire _T_608 = _T_632 & mip[2]; // @[dec_tlu_ctl.scala 719:66] - wire mhwakeup_ready = _T_608 & mie_ns[2]; // @[dec_tlu_ctl.scala 719:84] - wire _T_395 = io_dec_pic_mhwakeup & mhwakeup_ready; // @[dec_tlu_ctl.scala 600:172] - wire _T_396 = _T_394 | _T_395; // @[dec_tlu_ctl.scala 600:149] - wire _T_397 = _T_396 & io_o_cpu_halt_status; // @[dec_tlu_ctl.scala 600:191] - reg i_cpu_halt_req_d1; // @[dec_tlu_ctl.scala 572:80] - wire _T_398 = ~i_cpu_halt_req_d1; // @[dec_tlu_ctl.scala 600:216] - wire _T_399 = _T_397 & _T_398; // @[dec_tlu_ctl.scala 600:214] - wire i_cpu_run_req_d1 = i_cpu_run_req_d1_raw | _T_399; // @[dec_tlu_ctl.scala 600:45] + reg i_cpu_run_req_d1_raw; // @[dec_tlu_ctl.scala 571:80] + reg nmi_int_delayed; // @[dec_tlu_ctl.scala 338:72] + wire _T_37 = ~nmi_int_delayed; // @[dec_tlu_ctl.scala 347:45] + wire _T_38 = nmi_int_sync & _T_37; // @[dec_tlu_ctl.scala 347:43] + reg mdseac_locked_f; // @[dec_tlu_ctl.scala 604:89] + wire _T_35 = ~mdseac_locked_f; // @[dec_tlu_ctl.scala 345:32] + wire _T_36 = io_tlu_busbuff_lsu_imprecise_error_load_any | io_tlu_busbuff_lsu_imprecise_error_store_any; // @[dec_tlu_ctl.scala 345:96] + wire nmi_lsu_detected = _T_35 & _T_36; // @[dec_tlu_ctl.scala 345:49] + wire _T_39 = _T_38 | nmi_lsu_detected; // @[dec_tlu_ctl.scala 347:63] + reg nmi_int_detected_f; // @[dec_tlu_ctl.scala 339:72] + reg take_nmi_r_d1; // @[dec_tlu_ctl.scala 813:98] + wire _T_40 = ~take_nmi_r_d1; // @[dec_tlu_ctl.scala 347:106] + wire _T_41 = nmi_int_detected_f & _T_40; // @[dec_tlu_ctl.scala 347:104] + wire _T_42 = _T_39 | _T_41; // @[dec_tlu_ctl.scala 347:82] + reg take_ext_int_start_d3; // @[dec_tlu_ctl.scala 744:62] + wire _T_43 = |io_lsu_fir_error; // @[dec_tlu_ctl.scala 347:165] + wire _T_44 = take_ext_int_start_d3 & _T_43; // @[dec_tlu_ctl.scala 347:146] + wire nmi_int_detected = _T_42 | _T_44; // @[dec_tlu_ctl.scala 347:122] + wire _T_631 = ~io_dec_csr_stall_int_ff; // @[dec_tlu_ctl.scala 721:23] + wire mstatus_mie_ns = csr_io_mstatus_mie_ns; // @[dec_tlu_ctl.scala 1001:31] + wire _T_632 = _T_631 & mstatus_mie_ns; // @[dec_tlu_ctl.scala 721:48] + wire [5:0] mip = csr_io_mip; // @[dec_tlu_ctl.scala 1007:31] + wire _T_634 = _T_632 & mip[1]; // @[dec_tlu_ctl.scala 721:65] + wire [5:0] mie_ns = csr_io_mie_ns; // @[dec_tlu_ctl.scala 996:31] + wire timer_int_ready = _T_634 & mie_ns[1]; // @[dec_tlu_ctl.scala 721:83] + wire _T_391 = nmi_int_detected | timer_int_ready; // @[dec_tlu_ctl.scala 598:66] + wire _T_628 = _T_632 & mip[0]; // @[dec_tlu_ctl.scala 720:65] + wire soft_int_ready = _T_628 & mie_ns[0]; // @[dec_tlu_ctl.scala 720:83] + wire _T_392 = _T_391 | soft_int_ready; // @[dec_tlu_ctl.scala 598:84] + reg int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 578:73] + wire _T_393 = _T_392 | int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 598:101] + reg int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 579:73] + wire _T_394 = _T_393 | int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 598:125] + wire _T_608 = _T_632 & mip[2]; // @[dec_tlu_ctl.scala 717:66] + wire mhwakeup_ready = _T_608 & mie_ns[2]; // @[dec_tlu_ctl.scala 717:84] + wire _T_395 = io_dec_pic_mhwakeup & mhwakeup_ready; // @[dec_tlu_ctl.scala 598:172] + wire _T_396 = _T_394 | _T_395; // @[dec_tlu_ctl.scala 598:149] + wire _T_397 = _T_396 & io_o_cpu_halt_status; // @[dec_tlu_ctl.scala 598:191] + reg i_cpu_halt_req_d1; // @[dec_tlu_ctl.scala 570:80] + wire _T_398 = ~i_cpu_halt_req_d1; // @[dec_tlu_ctl.scala 598:216] + wire _T_399 = _T_397 & _T_398; // @[dec_tlu_ctl.scala 598:214] + wire i_cpu_run_req_d1 = i_cpu_run_req_d1_raw | _T_399; // @[dec_tlu_ctl.scala 598:45] wire _T_14 = debug_mode_status | i_cpu_run_req_d1; // @[dec_tlu_ctl.scala 316:50] - wire _T_685 = ~_T_43; // @[dec_tlu_ctl.scala 751:49] - wire take_ext_int = take_ext_int_start_d3 & _T_685; // @[dec_tlu_ctl.scala 751:47] - wire _T_698 = ~soft_int_ready; // @[dec_tlu_ctl.scala 768:40] - wire _T_699 = timer_int_ready & _T_698; // @[dec_tlu_ctl.scala 768:38] - wire _T_617 = ~io_lsu_fastint_stall_any; // @[dec_tlu_ctl.scala 720:104] - wire ext_int_ready = mhwakeup_ready & _T_617; // @[dec_tlu_ctl.scala 720:102] - wire _T_700 = ~ext_int_ready; // @[dec_tlu_ctl.scala 768:58] - wire _T_701 = _T_699 & _T_700; // @[dec_tlu_ctl.scala 768:56] - wire _T_622 = _T_632 & mip[5]; // @[dec_tlu_ctl.scala 721:65] - wire ce_int_ready = _T_622 & mie_ns[5]; // @[dec_tlu_ctl.scala 721:83] - wire _T_702 = ~ce_int_ready; // @[dec_tlu_ctl.scala 768:75] - wire _T_703 = _T_701 & _T_702; // @[dec_tlu_ctl.scala 768:73] - wire _T_152 = ~debug_mode_status; // @[dec_tlu_ctl.scala 423:37] - reg dbg_halt_req_held; // @[dec_tlu_ctl.scala 466:81] - wire _T_106 = io_dbg_halt_req | dbg_halt_req_held; // @[dec_tlu_ctl.scala 400:48] - reg ext_int_freeze_d1; // @[dec_tlu_ctl.scala 747:66] - wire _T_107 = ~ext_int_freeze_d1; // @[dec_tlu_ctl.scala 400:71] - wire dbg_halt_req_final = _T_106 & _T_107; // @[dec_tlu_ctl.scala 400:69] - wire mpc_debug_halt_req_sync = mpc_debug_halt_req_sync_raw & _T_107; // @[dec_tlu_ctl.scala 359:67] - wire _T_109 = dbg_halt_req_final | mpc_debug_halt_req_sync; // @[dec_tlu_ctl.scala 403:50] - reg reset_detect; // @[dec_tlu_ctl.scala 336:88] - reg reset_detected; // @[dec_tlu_ctl.scala 337:88] - wire reset_delayed = reset_detect ^ reset_detected; // @[dec_tlu_ctl.scala 338:64] - wire _T_110 = ~io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 403:95] - wire _T_111 = reset_delayed & _T_110; // @[dec_tlu_ctl.scala 403:93] - wire _T_112 = _T_109 | _T_111; // @[dec_tlu_ctl.scala 403:76] - wire _T_114 = _T_112 & _T_152; // @[dec_tlu_ctl.scala 403:119] - wire debug_halt_req = _T_114 & _T_107; // @[dec_tlu_ctl.scala 403:147] - wire _T_153 = _T_152 & debug_halt_req; // @[dec_tlu_ctl.scala 423:63] - reg dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 458:81] - wire _T_154 = _T_153 | dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 423:81] - reg trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 457:81] - wire _T_155 = _T_154 | trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 423:107] - reg ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 672:64] - wire enter_debug_halt_req = _T_155 | ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 423:132] - reg debug_halt_req_f; // @[dec_tlu_ctl.scala 455:89] - wire force_halt = csr_io_force_halt; // @[dec_tlu_ctl.scala 1001:31] - reg lsu_idle_any_f; // @[dec_tlu_ctl.scala 451:89] - wire _T_142 = io_lsu_idle_any & lsu_idle_any_f; // @[dec_tlu_ctl.scala 417:53] - wire _T_143 = _T_142 & io_tlu_mem_ifu_miss_state_idle; // @[dec_tlu_ctl.scala 417:70] - reg ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 452:81] - wire _T_144 = _T_143 & ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 417:103] - wire _T_145 = ~debug_halt_req; // @[dec_tlu_ctl.scala 417:129] - wire _T_146 = _T_144 & _T_145; // @[dec_tlu_ctl.scala 417:127] - reg debug_halt_req_d1; // @[dec_tlu_ctl.scala 459:89] - wire _T_147 = ~debug_halt_req_d1; // @[dec_tlu_ctl.scala 417:147] - wire _T_148 = _T_146 & _T_147; // @[dec_tlu_ctl.scala 417:145] - wire _T_149 = ~io_dec_div_active; // @[dec_tlu_ctl.scala 417:168] - wire _T_150 = _T_148 & _T_149; // @[dec_tlu_ctl.scala 417:166] - wire core_empty = force_halt | _T_150; // @[dec_tlu_ctl.scala 417:34] - wire _T_163 = debug_halt_req_f & core_empty; // @[dec_tlu_ctl.scala 433:48] - reg dec_tlu_flush_noredir_r_d1; // @[dec_tlu_ctl.scala 449:81] - reg dec_tlu_flush_pause_r_d1; // @[dec_tlu_ctl.scala 465:73] - wire _T_132 = ~dec_tlu_flush_pause_r_d1; // @[dec_tlu_ctl.scala 413:56] - wire _T_133 = dec_tlu_flush_noredir_r_d1 & _T_132; // @[dec_tlu_ctl.scala 413:54] - reg take_ext_int_start_d1; // @[dec_tlu_ctl.scala 744:62] - wire _T_134 = ~take_ext_int_start_d1; // @[dec_tlu_ctl.scala 413:84] - wire _T_135 = _T_133 & _T_134; // @[dec_tlu_ctl.scala 413:82] - reg halt_taken_f; // @[dec_tlu_ctl.scala 450:89] - reg dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 453:89] - wire _T_136 = ~dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 413:126] - wire _T_137 = halt_taken_f & _T_136; // @[dec_tlu_ctl.scala 413:124] - reg pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 579:73] - wire _T_138 = ~pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 413:146] - wire _T_139 = _T_137 & _T_138; // @[dec_tlu_ctl.scala 413:144] - reg interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 809:90] - wire _T_140 = ~interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 413:169] - wire _T_141 = _T_139 & _T_140; // @[dec_tlu_ctl.scala 413:167] - wire halt_taken = _T_135 | _T_141; // @[dec_tlu_ctl.scala 413:108] - wire _T_164 = _T_163 & halt_taken; // @[dec_tlu_ctl.scala 433:61] - reg debug_resume_req_f; // @[dec_tlu_ctl.scala 456:89] - wire _T_165 = ~debug_resume_req_f; // @[dec_tlu_ctl.scala 433:97] - wire _T_166 = dbg_tlu_halted_f & _T_165; // @[dec_tlu_ctl.scala 433:95] - wire dbg_tlu_halted = _T_164 | _T_166; // @[dec_tlu_ctl.scala 433:75] - wire _T_167 = ~dbg_tlu_halted; // @[dec_tlu_ctl.scala 434:73] - wire _T_168 = debug_halt_req_f & _T_167; // @[dec_tlu_ctl.scala 434:71] - wire debug_halt_req_ns = enter_debug_halt_req | _T_168; // @[dec_tlu_ctl.scala 434:51] - wire [15:0] dcsr = csr_io_dcsr; // @[dec_tlu_ctl.scala 1007:31] - wire _T_157 = ~dcsr[2]; // @[dec_tlu_ctl.scala 426:106] - wire _T_158 = debug_resume_req_f & _T_157; // @[dec_tlu_ctl.scala 426:104] - wire _T_159 = ~_T_158; // @[dec_tlu_ctl.scala 426:83] - wire _T_160 = debug_mode_status & _T_159; // @[dec_tlu_ctl.scala 426:81] - wire internal_dbg_halt_mode = debug_halt_req_ns | _T_160; // @[dec_tlu_ctl.scala 426:53] - wire _T_177 = debug_resume_req_f & dcsr[2]; // @[dec_tlu_ctl.scala 439:60] - reg dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 464:73] - wire _T_178 = ~dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 439:111] - wire _T_179 = dcsr_single_step_running_f & _T_178; // @[dec_tlu_ctl.scala 439:109] - wire dcsr_single_step_running = _T_177 | _T_179; // @[dec_tlu_ctl.scala 439:79] - wire _T_665 = ~dcsr_single_step_running; // @[dec_tlu_ctl.scala 740:55] - wire _T_666 = _T_665 | io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 740:81] - wire _T_667 = internal_dbg_halt_mode & _T_666; // @[dec_tlu_ctl.scala 740:52] - wire _T_346 = ~io_dec_tlu_debug_mode; // @[dec_tlu_ctl.scala 569:62] - wire _T_347 = i_cpu_halt_req_sync & _T_346; // @[dec_tlu_ctl.scala 569:60] - wire i_cpu_halt_req_sync_qual = _T_347 & _T_107; // @[dec_tlu_ctl.scala 569:85] - wire ext_halt_pulse = i_cpu_halt_req_sync_qual & _T_398; // @[dec_tlu_ctl.scala 585:50] - wire fw_halt_req = csr_io_fw_halt_req; // @[dec_tlu_ctl.scala 1005:31] - wire enter_pmu_fw_halt_req = ext_halt_pulse | fw_halt_req; // @[dec_tlu_ctl.scala 586:48] - reg pmu_fw_halt_req_f; // @[dec_tlu_ctl.scala 578:73] - wire _T_371 = pmu_fw_halt_req_f & core_empty; // @[dec_tlu_ctl.scala 591:45] - wire _T_372 = _T_371 & halt_taken; // @[dec_tlu_ctl.scala 591:58] - wire _T_373 = ~enter_debug_halt_req; // @[dec_tlu_ctl.scala 591:73] - wire _T_374 = _T_372 & _T_373; // @[dec_tlu_ctl.scala 591:71] - wire _T_375 = ~i_cpu_run_req_d1; // @[dec_tlu_ctl.scala 591:121] - wire _T_376 = pmu_fw_tlu_halted_f & _T_375; // @[dec_tlu_ctl.scala 591:119] - wire _T_377 = _T_374 | _T_376; // @[dec_tlu_ctl.scala 591:96] - wire _T_378 = ~debug_halt_req_f; // @[dec_tlu_ctl.scala 591:143] - wire pmu_fw_tlu_halted = _T_377 & _T_378; // @[dec_tlu_ctl.scala 591:141] - wire _T_361 = ~pmu_fw_tlu_halted; // @[dec_tlu_ctl.scala 587:72] - wire _T_362 = pmu_fw_halt_req_f & _T_361; // @[dec_tlu_ctl.scala 587:70] - wire _T_363 = enter_pmu_fw_halt_req | _T_362; // @[dec_tlu_ctl.scala 587:49] - wire pmu_fw_halt_req_ns = _T_363 & _T_378; // @[dec_tlu_ctl.scala 587:93] - reg internal_pmu_fw_halt_mode_f; // @[dec_tlu_ctl.scala 577:68] - wire _T_367 = internal_pmu_fw_halt_mode_f & _T_375; // @[dec_tlu_ctl.scala 588:83] - wire _T_369 = _T_367 & _T_378; // @[dec_tlu_ctl.scala 588:103] - wire internal_pmu_fw_halt_mode = pmu_fw_halt_req_ns | _T_369; // @[dec_tlu_ctl.scala 588:52] - wire _T_668 = _T_667 | internal_pmu_fw_halt_mode; // @[dec_tlu_ctl.scala 740:107] - wire _T_669 = _T_668 | i_cpu_halt_req_d1; // @[dec_tlu_ctl.scala 740:135] - wire _T_738 = ~internal_pmu_fw_halt_mode; // @[dec_tlu_ctl.scala 772:35] - wire _T_739 = nmi_int_detected & _T_738; // @[dec_tlu_ctl.scala 772:33] - wire _T_740 = ~internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 772:65] - wire _T_742 = dcsr_single_step_running_f & dcsr[11]; // @[dec_tlu_ctl.scala 772:119] - wire _T_743 = ~io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 772:141] - wire _T_744 = _T_742 & _T_743; // @[dec_tlu_ctl.scala 772:139] - wire _T_746 = _T_744 & _T_178; // @[dec_tlu_ctl.scala 772:164] - wire _T_747 = _T_740 | _T_746; // @[dec_tlu_ctl.scala 772:89] - wire _T_748 = _T_739 & _T_747; // @[dec_tlu_ctl.scala 772:62] - wire _T_463 = io_dec_tlu_packet_r_pmu_i0_itype == 4'h8; // @[dec_tlu_ctl.scala 658:51] - wire _T_464 = _T_463 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 658:64] - wire _T_297 = io_dec_tlu_flush_lower_wb | io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 520:58] + wire _T_685 = ~_T_43; // @[dec_tlu_ctl.scala 749:49] + wire take_ext_int = take_ext_int_start_d3 & _T_685; // @[dec_tlu_ctl.scala 749:47] + wire _T_698 = ~soft_int_ready; // @[dec_tlu_ctl.scala 766:40] + wire _T_699 = timer_int_ready & _T_698; // @[dec_tlu_ctl.scala 766:38] + wire _T_617 = ~io_lsu_fastint_stall_any; // @[dec_tlu_ctl.scala 718:104] + wire ext_int_ready = mhwakeup_ready & _T_617; // @[dec_tlu_ctl.scala 718:102] + wire _T_700 = ~ext_int_ready; // @[dec_tlu_ctl.scala 766:58] + wire _T_701 = _T_699 & _T_700; // @[dec_tlu_ctl.scala 766:56] + wire _T_622 = _T_632 & mip[5]; // @[dec_tlu_ctl.scala 719:65] + wire ce_int_ready = _T_622 & mie_ns[5]; // @[dec_tlu_ctl.scala 719:83] + wire _T_702 = ~ce_int_ready; // @[dec_tlu_ctl.scala 766:75] + wire _T_703 = _T_701 & _T_702; // @[dec_tlu_ctl.scala 766:73] + wire _T_152 = ~debug_mode_status; // @[dec_tlu_ctl.scala 421:37] + reg dbg_halt_req_held; // @[dec_tlu_ctl.scala 464:81] + wire _T_106 = io_dbg_halt_req | dbg_halt_req_held; // @[dec_tlu_ctl.scala 398:48] + reg ext_int_freeze_d1; // @[dec_tlu_ctl.scala 745:66] + wire _T_107 = ~ext_int_freeze_d1; // @[dec_tlu_ctl.scala 398:71] + wire dbg_halt_req_final = _T_106 & _T_107; // @[dec_tlu_ctl.scala 398:69] + wire mpc_debug_halt_req_sync = mpc_debug_halt_req_sync_raw & _T_107; // @[dec_tlu_ctl.scala 357:67] + wire _T_109 = dbg_halt_req_final | mpc_debug_halt_req_sync; // @[dec_tlu_ctl.scala 401:50] + reg reset_detect; // @[dec_tlu_ctl.scala 334:88] + reg reset_detected; // @[dec_tlu_ctl.scala 335:88] + wire reset_delayed = reset_detect ^ reset_detected; // @[dec_tlu_ctl.scala 336:64] + wire _T_110 = ~io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 401:95] + wire _T_111 = reset_delayed & _T_110; // @[dec_tlu_ctl.scala 401:93] + wire _T_112 = _T_109 | _T_111; // @[dec_tlu_ctl.scala 401:76] + wire _T_114 = _T_112 & _T_152; // @[dec_tlu_ctl.scala 401:119] + wire debug_halt_req = _T_114 & _T_107; // @[dec_tlu_ctl.scala 401:147] + wire _T_153 = _T_152 & debug_halt_req; // @[dec_tlu_ctl.scala 421:63] + reg dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 456:81] + wire _T_154 = _T_153 | dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 421:81] + reg trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 455:81] + wire _T_155 = _T_154 | trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 421:107] + reg ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 670:64] + wire enter_debug_halt_req = _T_155 | ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 421:132] + reg debug_halt_req_f; // @[dec_tlu_ctl.scala 453:89] + wire force_halt = csr_io_force_halt; // @[dec_tlu_ctl.scala 999:31] + reg lsu_idle_any_f; // @[dec_tlu_ctl.scala 449:89] + wire _T_142 = io_lsu_idle_any & lsu_idle_any_f; // @[dec_tlu_ctl.scala 415:53] + wire _T_143 = _T_142 & io_tlu_mem_ifu_miss_state_idle; // @[dec_tlu_ctl.scala 415:70] + reg ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 450:81] + wire _T_144 = _T_143 & ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 415:103] + wire _T_145 = ~debug_halt_req; // @[dec_tlu_ctl.scala 415:129] + wire _T_146 = _T_144 & _T_145; // @[dec_tlu_ctl.scala 415:127] + reg debug_halt_req_d1; // @[dec_tlu_ctl.scala 457:89] + wire _T_147 = ~debug_halt_req_d1; // @[dec_tlu_ctl.scala 415:147] + wire _T_148 = _T_146 & _T_147; // @[dec_tlu_ctl.scala 415:145] + wire _T_149 = ~io_dec_div_active; // @[dec_tlu_ctl.scala 415:168] + wire _T_150 = _T_148 & _T_149; // @[dec_tlu_ctl.scala 415:166] + wire core_empty = force_halt | _T_150; // @[dec_tlu_ctl.scala 415:34] + wire _T_163 = debug_halt_req_f & core_empty; // @[dec_tlu_ctl.scala 431:48] + reg dec_tlu_flush_noredir_r_d1; // @[dec_tlu_ctl.scala 447:81] + reg dec_tlu_flush_pause_r_d1; // @[dec_tlu_ctl.scala 463:73] + wire _T_132 = ~dec_tlu_flush_pause_r_d1; // @[dec_tlu_ctl.scala 411:56] + wire _T_133 = dec_tlu_flush_noredir_r_d1 & _T_132; // @[dec_tlu_ctl.scala 411:54] + reg take_ext_int_start_d1; // @[dec_tlu_ctl.scala 742:62] + wire _T_134 = ~take_ext_int_start_d1; // @[dec_tlu_ctl.scala 411:84] + wire _T_135 = _T_133 & _T_134; // @[dec_tlu_ctl.scala 411:82] + reg halt_taken_f; // @[dec_tlu_ctl.scala 448:89] + reg dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 451:89] + wire _T_136 = ~dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 411:126] + wire _T_137 = halt_taken_f & _T_136; // @[dec_tlu_ctl.scala 411:124] + reg pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 577:73] + wire _T_138 = ~pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 411:146] + wire _T_139 = _T_137 & _T_138; // @[dec_tlu_ctl.scala 411:144] + reg interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 807:90] + wire _T_140 = ~interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 411:169] + wire _T_141 = _T_139 & _T_140; // @[dec_tlu_ctl.scala 411:167] + wire halt_taken = _T_135 | _T_141; // @[dec_tlu_ctl.scala 411:108] + wire _T_164 = _T_163 & halt_taken; // @[dec_tlu_ctl.scala 431:61] + reg debug_resume_req_f; // @[dec_tlu_ctl.scala 454:89] + wire _T_165 = ~debug_resume_req_f; // @[dec_tlu_ctl.scala 431:97] + wire _T_166 = dbg_tlu_halted_f & _T_165; // @[dec_tlu_ctl.scala 431:95] + wire dbg_tlu_halted = _T_164 | _T_166; // @[dec_tlu_ctl.scala 431:75] + wire _T_167 = ~dbg_tlu_halted; // @[dec_tlu_ctl.scala 432:73] + wire _T_168 = debug_halt_req_f & _T_167; // @[dec_tlu_ctl.scala 432:71] + wire debug_halt_req_ns = enter_debug_halt_req | _T_168; // @[dec_tlu_ctl.scala 432:51] + wire [15:0] dcsr = csr_io_dcsr; // @[dec_tlu_ctl.scala 1005:31] + wire _T_157 = ~dcsr[2]; // @[dec_tlu_ctl.scala 424:106] + wire _T_158 = debug_resume_req_f & _T_157; // @[dec_tlu_ctl.scala 424:104] + wire _T_159 = ~_T_158; // @[dec_tlu_ctl.scala 424:83] + wire _T_160 = debug_mode_status & _T_159; // @[dec_tlu_ctl.scala 424:81] + wire internal_dbg_halt_mode = debug_halt_req_ns | _T_160; // @[dec_tlu_ctl.scala 424:53] + wire _T_177 = debug_resume_req_f & dcsr[2]; // @[dec_tlu_ctl.scala 437:60] + reg dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 462:73] + wire _T_178 = ~dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 437:111] + wire _T_179 = dcsr_single_step_running_f & _T_178; // @[dec_tlu_ctl.scala 437:109] + wire dcsr_single_step_running = _T_177 | _T_179; // @[dec_tlu_ctl.scala 437:79] + wire _T_665 = ~dcsr_single_step_running; // @[dec_tlu_ctl.scala 738:55] + wire _T_666 = _T_665 | io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 738:81] + wire _T_667 = internal_dbg_halt_mode & _T_666; // @[dec_tlu_ctl.scala 738:52] + wire _T_346 = ~io_dec_tlu_debug_mode; // @[dec_tlu_ctl.scala 567:62] + wire _T_347 = i_cpu_halt_req_sync & _T_346; // @[dec_tlu_ctl.scala 567:60] + wire i_cpu_halt_req_sync_qual = _T_347 & _T_107; // @[dec_tlu_ctl.scala 567:85] + wire ext_halt_pulse = i_cpu_halt_req_sync_qual & _T_398; // @[dec_tlu_ctl.scala 583:50] + wire fw_halt_req = csr_io_fw_halt_req; // @[dec_tlu_ctl.scala 1003:31] + wire enter_pmu_fw_halt_req = ext_halt_pulse | fw_halt_req; // @[dec_tlu_ctl.scala 584:48] + reg pmu_fw_halt_req_f; // @[dec_tlu_ctl.scala 576:73] + wire _T_371 = pmu_fw_halt_req_f & core_empty; // @[dec_tlu_ctl.scala 589:45] + wire _T_372 = _T_371 & halt_taken; // @[dec_tlu_ctl.scala 589:58] + wire _T_373 = ~enter_debug_halt_req; // @[dec_tlu_ctl.scala 589:73] + wire _T_374 = _T_372 & _T_373; // @[dec_tlu_ctl.scala 589:71] + wire _T_375 = ~i_cpu_run_req_d1; // @[dec_tlu_ctl.scala 589:121] + wire _T_376 = pmu_fw_tlu_halted_f & _T_375; // @[dec_tlu_ctl.scala 589:119] + wire _T_377 = _T_374 | _T_376; // @[dec_tlu_ctl.scala 589:96] + wire _T_378 = ~debug_halt_req_f; // @[dec_tlu_ctl.scala 589:143] + wire pmu_fw_tlu_halted = _T_377 & _T_378; // @[dec_tlu_ctl.scala 589:141] + wire _T_361 = ~pmu_fw_tlu_halted; // @[dec_tlu_ctl.scala 585:72] + wire _T_362 = pmu_fw_halt_req_f & _T_361; // @[dec_tlu_ctl.scala 585:70] + wire _T_363 = enter_pmu_fw_halt_req | _T_362; // @[dec_tlu_ctl.scala 585:49] + wire pmu_fw_halt_req_ns = _T_363 & _T_378; // @[dec_tlu_ctl.scala 585:93] + reg internal_pmu_fw_halt_mode_f; // @[dec_tlu_ctl.scala 575:68] + wire _T_367 = internal_pmu_fw_halt_mode_f & _T_375; // @[dec_tlu_ctl.scala 586:83] + wire _T_369 = _T_367 & _T_378; // @[dec_tlu_ctl.scala 586:103] + wire internal_pmu_fw_halt_mode = pmu_fw_halt_req_ns | _T_369; // @[dec_tlu_ctl.scala 586:52] + wire _T_668 = _T_667 | internal_pmu_fw_halt_mode; // @[dec_tlu_ctl.scala 738:107] + wire _T_669 = _T_668 | i_cpu_halt_req_d1; // @[dec_tlu_ctl.scala 738:135] + wire _T_738 = ~internal_pmu_fw_halt_mode; // @[dec_tlu_ctl.scala 770:35] + wire _T_739 = nmi_int_detected & _T_738; // @[dec_tlu_ctl.scala 770:33] + wire _T_740 = ~internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 770:65] + wire _T_742 = dcsr_single_step_running_f & dcsr[11]; // @[dec_tlu_ctl.scala 770:119] + wire _T_743 = ~io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 770:141] + wire _T_744 = _T_742 & _T_743; // @[dec_tlu_ctl.scala 770:139] + wire _T_746 = _T_744 & _T_178; // @[dec_tlu_ctl.scala 770:164] + wire _T_747 = _T_740 | _T_746; // @[dec_tlu_ctl.scala 770:89] + wire _T_748 = _T_739 & _T_747; // @[dec_tlu_ctl.scala 770:62] + wire _T_463 = io_dec_tlu_packet_r_pmu_i0_itype == 4'h8; // @[dec_tlu_ctl.scala 656:51] + wire _T_464 = _T_463 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 656:64] + wire _T_297 = io_dec_tlu_flush_lower_wb | io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 518:58] wire [3:0] _T_299 = _T_297 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_300 = ~_T_299; // @[dec_tlu_ctl.scala 520:23] + wire [3:0] _T_300 = ~_T_299; // @[dec_tlu_ctl.scala 518:23] wire [3:0] _T_292 = io_dec_tlu_i0_valid_r ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_294 = _T_292 & io_dec_tlu_packet_r_i0trigger; // @[dec_tlu_ctl.scala 518:53] - wire [9:0] mtdata1_t_3 = csr_io_mtdata1_t_3; // @[dec_tlu_ctl.scala 156:67 dec_tlu_ctl.scala 1010:33] - wire [9:0] mtdata1_t_2 = csr_io_mtdata1_t_2; // @[dec_tlu_ctl.scala 156:67 dec_tlu_ctl.scala 1010:33] - wire [9:0] mtdata1_t_1 = csr_io_mtdata1_t_1; // @[dec_tlu_ctl.scala 156:67 dec_tlu_ctl.scala 1010:33] - wire [9:0] mtdata1_t_0 = csr_io_mtdata1_t_0; // @[dec_tlu_ctl.scala 156:67 dec_tlu_ctl.scala 1010:33] + wire [3:0] _T_294 = _T_292 & io_dec_tlu_packet_r_i0trigger; // @[dec_tlu_ctl.scala 516:53] + wire [9:0] mtdata1_t_3 = csr_io_mtdata1_t_3; // @[dec_tlu_ctl.scala 156:67 dec_tlu_ctl.scala 1008:33] + wire [9:0] mtdata1_t_2 = csr_io_mtdata1_t_2; // @[dec_tlu_ctl.scala 156:67 dec_tlu_ctl.scala 1008:33] + wire [9:0] mtdata1_t_1 = csr_io_mtdata1_t_1; // @[dec_tlu_ctl.scala 156:67 dec_tlu_ctl.scala 1008:33] + wire [9:0] mtdata1_t_0 = csr_io_mtdata1_t_0; // @[dec_tlu_ctl.scala 156:67 dec_tlu_ctl.scala 1008:33] wire [3:0] trigger_execute = {mtdata1_t_3[2],mtdata1_t_2[2],mtdata1_t_1[2],mtdata1_t_0[2]}; // @[Cat.scala 29:58] wire [3:0] trigger_data = {mtdata1_t_3[7],mtdata1_t_2[7],mtdata1_t_1[7],mtdata1_t_0[7]}; // @[Cat.scala 29:58] - wire [3:0] _T_279 = trigger_execute & trigger_data; // @[dec_tlu_ctl.scala 510:57] - wire inst_acc_r_raw = io_dec_tlu_packet_r_icaf & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 666:49] + wire [3:0] _T_279 = trigger_execute & trigger_data; // @[dec_tlu_ctl.scala 508:57] + wire inst_acc_r_raw = io_dec_tlu_packet_r_icaf & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 664:49] wire [3:0] _T_281 = inst_acc_r_raw ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_282 = _T_279 & _T_281; // @[dec_tlu_ctl.scala 510:72] - wire _T_283 = io_tlu_exu_exu_i0_br_error_r | io_tlu_exu_exu_i0_br_start_error_r; // @[dec_tlu_ctl.scala 510:137] + wire [3:0] _T_282 = _T_279 & _T_281; // @[dec_tlu_ctl.scala 508:72] + wire _T_283 = io_tlu_exu_exu_i0_br_error_r | io_tlu_exu_exu_i0_br_start_error_r; // @[dec_tlu_ctl.scala 508:137] wire [3:0] _T_285 = _T_283 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_286 = _T_282 | _T_285; // @[dec_tlu_ctl.scala 510:98] - wire [3:0] i0_iside_trigger_has_pri_r = ~_T_286; // @[dec_tlu_ctl.scala 510:38] - wire [3:0] _T_295 = _T_294 & i0_iside_trigger_has_pri_r; // @[dec_tlu_ctl.scala 518:90] + wire [3:0] _T_286 = _T_282 | _T_285; // @[dec_tlu_ctl.scala 508:98] + wire [3:0] i0_iside_trigger_has_pri_r = ~_T_286; // @[dec_tlu_ctl.scala 508:38] + wire [3:0] _T_295 = _T_294 & i0_iside_trigger_has_pri_r; // @[dec_tlu_ctl.scala 516:90] wire [3:0] trigger_store = {mtdata1_t_3[1],mtdata1_t_2[1],mtdata1_t_1[1],mtdata1_t_0[1]}; // @[Cat.scala 29:58] - wire [3:0] _T_287 = trigger_store & trigger_data; // @[dec_tlu_ctl.scala 513:51] + wire [3:0] _T_287 = trigger_store & trigger_data; // @[dec_tlu_ctl.scala 511:51] wire [3:0] _T_289 = io_lsu_error_pkt_r_valid ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_290 = _T_287 & _T_289; // @[dec_tlu_ctl.scala 513:66] - wire [3:0] i0_lsu_trigger_has_pri_r = ~_T_290; // @[dec_tlu_ctl.scala 513:35] - wire [3:0] _T_296 = _T_295 & i0_lsu_trigger_has_pri_r; // @[dec_tlu_ctl.scala 518:119] - wire [1:0] mstatus = csr_io_mstatus; // @[dec_tlu_ctl.scala 1006:31] - wire _T_259 = mtdata1_t_3[6] | mstatus[0]; // @[dec_tlu_ctl.scala 507:62] - wire _T_261 = _T_259 & mtdata1_t_3[3]; // @[dec_tlu_ctl.scala 507:86] - wire _T_264 = mtdata1_t_2[6] | mstatus[0]; // @[dec_tlu_ctl.scala 507:150] - wire _T_266 = _T_264 & mtdata1_t_2[3]; // @[dec_tlu_ctl.scala 507:174] - wire _T_269 = mtdata1_t_1[6] | mstatus[0]; // @[dec_tlu_ctl.scala 507:239] - wire _T_271 = _T_269 & mtdata1_t_1[3]; // @[dec_tlu_ctl.scala 507:263] - wire _T_274 = mtdata1_t_0[6] | mstatus[0]; // @[dec_tlu_ctl.scala 507:328] - wire _T_276 = _T_274 & mtdata1_t_0[3]; // @[dec_tlu_ctl.scala 507:352] + wire [3:0] _T_290 = _T_287 & _T_289; // @[dec_tlu_ctl.scala 511:66] + wire [3:0] i0_lsu_trigger_has_pri_r = ~_T_290; // @[dec_tlu_ctl.scala 511:35] + wire [3:0] _T_296 = _T_295 & i0_lsu_trigger_has_pri_r; // @[dec_tlu_ctl.scala 516:119] + wire [1:0] mstatus = csr_io_mstatus; // @[dec_tlu_ctl.scala 1004:31] + wire _T_259 = mtdata1_t_3[6] | mstatus[0]; // @[dec_tlu_ctl.scala 505:62] + wire _T_261 = _T_259 & mtdata1_t_3[3]; // @[dec_tlu_ctl.scala 505:86] + wire _T_264 = mtdata1_t_2[6] | mstatus[0]; // @[dec_tlu_ctl.scala 505:150] + wire _T_266 = _T_264 & mtdata1_t_2[3]; // @[dec_tlu_ctl.scala 505:174] + wire _T_269 = mtdata1_t_1[6] | mstatus[0]; // @[dec_tlu_ctl.scala 505:239] + wire _T_271 = _T_269 & mtdata1_t_1[3]; // @[dec_tlu_ctl.scala 505:263] + wire _T_274 = mtdata1_t_0[6] | mstatus[0]; // @[dec_tlu_ctl.scala 505:328] + wire _T_276 = _T_274 & mtdata1_t_0[3]; // @[dec_tlu_ctl.scala 505:352] wire [3:0] trigger_enabled = {_T_261,_T_266,_T_271,_T_276}; // @[Cat.scala 29:58] - wire [3:0] i0trigger_qual_r = _T_296 & trigger_enabled; // @[dec_tlu_ctl.scala 518:146] - wire [3:0] i0_trigger_r = _T_300 & i0trigger_qual_r; // @[dec_tlu_ctl.scala 520:84] - wire _T_303 = ~mtdata1_t_2[5]; // @[dec_tlu_ctl.scala 523:60] - wire _T_305 = _T_303 | i0_trigger_r[2]; // @[dec_tlu_ctl.scala 523:89] - wire _T_306 = i0_trigger_r[3] & _T_305; // @[dec_tlu_ctl.scala 523:57] - wire _T_311 = _T_303 | i0_trigger_r[3]; // @[dec_tlu_ctl.scala 523:157] - wire _T_312 = i0_trigger_r[2] & _T_311; // @[dec_tlu_ctl.scala 523:125] - wire _T_315 = ~mtdata1_t_0[5]; // @[dec_tlu_ctl.scala 523:196] - wire _T_317 = _T_315 | i0_trigger_r[0]; // @[dec_tlu_ctl.scala 523:225] - wire _T_318 = i0_trigger_r[1] & _T_317; // @[dec_tlu_ctl.scala 523:193] - wire _T_323 = _T_315 | i0_trigger_r[1]; // @[dec_tlu_ctl.scala 523:293] - wire _T_324 = i0_trigger_r[0] & _T_323; // @[dec_tlu_ctl.scala 523:261] + wire [3:0] i0trigger_qual_r = _T_296 & trigger_enabled; // @[dec_tlu_ctl.scala 516:146] + wire [3:0] i0_trigger_r = _T_300 & i0trigger_qual_r; // @[dec_tlu_ctl.scala 518:84] + wire _T_303 = ~mtdata1_t_2[5]; // @[dec_tlu_ctl.scala 521:60] + wire _T_305 = _T_303 | i0_trigger_r[2]; // @[dec_tlu_ctl.scala 521:89] + wire _T_306 = i0_trigger_r[3] & _T_305; // @[dec_tlu_ctl.scala 521:57] + wire _T_311 = _T_303 | i0_trigger_r[3]; // @[dec_tlu_ctl.scala 521:157] + wire _T_312 = i0_trigger_r[2] & _T_311; // @[dec_tlu_ctl.scala 521:125] + wire _T_315 = ~mtdata1_t_0[5]; // @[dec_tlu_ctl.scala 521:196] + wire _T_317 = _T_315 | i0_trigger_r[0]; // @[dec_tlu_ctl.scala 521:225] + wire _T_318 = i0_trigger_r[1] & _T_317; // @[dec_tlu_ctl.scala 521:193] + wire _T_323 = _T_315 | i0_trigger_r[1]; // @[dec_tlu_ctl.scala 521:293] + wire _T_324 = i0_trigger_r[0] & _T_323; // @[dec_tlu_ctl.scala 521:261] wire [3:0] i0_trigger_chain_masked_r = {_T_306,_T_312,_T_318,_T_324}; // @[Cat.scala 29:58] - wire i0_trigger_hit_raw_r = |i0_trigger_chain_masked_r; // @[dec_tlu_ctl.scala 526:57] - wire _T_465 = ~i0_trigger_hit_raw_r; // @[dec_tlu_ctl.scala 658:90] - wire _T_466 = _T_464 & _T_465; // @[dec_tlu_ctl.scala 658:88] - wire _T_468 = ~dcsr[15]; // @[dec_tlu_ctl.scala 658:110] - wire _T_469 = _T_466 & _T_468; // @[dec_tlu_ctl.scala 658:108] + wire i0_trigger_hit_raw_r = |i0_trigger_chain_masked_r; // @[dec_tlu_ctl.scala 524:57] + wire _T_465 = ~i0_trigger_hit_raw_r; // @[dec_tlu_ctl.scala 656:90] + wire _T_466 = _T_464 & _T_465; // @[dec_tlu_ctl.scala 656:88] + wire _T_468 = ~dcsr[15]; // @[dec_tlu_ctl.scala 656:110] + wire _T_469 = _T_466 & _T_468; // @[dec_tlu_ctl.scala 656:108] reg tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 328:80] - wire _T_429 = ~tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 633:44] - wire _T_430 = io_dec_tlu_i0_valid_r & _T_429; // @[dec_tlu_ctl.scala 633:42] - wire _T_432 = _T_430 & _T_283; // @[dec_tlu_ctl.scala 633:66] + wire _T_429 = ~tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 631:44] + wire _T_430 = io_dec_tlu_i0_valid_r & _T_429; // @[dec_tlu_ctl.scala 631:42] + wire _T_432 = _T_430 & _T_283; // @[dec_tlu_ctl.scala 631:66] reg ic_perr_r_d1; // @[dec_tlu_ctl.scala 322:89] reg iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 323:89] - wire _T_433 = ic_perr_r_d1 | iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 633:154] - wire _T_435 = _T_433 & _T_107; // @[dec_tlu_ctl.scala 633:173] - wire _T_436 = _T_432 | _T_435; // @[dec_tlu_ctl.scala 633:137] - wire _T_438 = _T_436 & _T_465; // @[dec_tlu_ctl.scala 633:196] - wire _T_410 = io_dec_tlu_i0_valid_r & _T_465; // @[dec_tlu_ctl.scala 621:47] - wire _T_411 = ~io_lsu_error_pkt_r_bits_inst_type; // @[dec_tlu_ctl.scala 621:70] - wire _T_412 = _T_411 & io_lsu_error_pkt_r_bits_single_ecc_error; // @[dec_tlu_ctl.scala 621:105] - wire lsu_i0_rfnpc_r = _T_410 & _T_412; // @[dec_tlu_ctl.scala 621:67] - wire _T_439 = ~lsu_i0_rfnpc_r; // @[dec_tlu_ctl.scala 633:220] - wire rfpc_i0_r = _T_438 & _T_439; // @[dec_tlu_ctl.scala 633:217] - wire _T_470 = ~rfpc_i0_r; // @[dec_tlu_ctl.scala 658:132] - wire ebreak_r = _T_469 & _T_470; // @[dec_tlu_ctl.scala 658:130] - wire _T_472 = io_dec_tlu_packet_r_pmu_i0_itype == 4'h9; // @[dec_tlu_ctl.scala 659:51] - wire _T_473 = _T_472 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 659:64] - wire _T_475 = _T_473 & _T_465; // @[dec_tlu_ctl.scala 659:88] - wire ecall_r = _T_475 & _T_470; // @[dec_tlu_ctl.scala 659:108] - wire _T_523 = ebreak_r | ecall_r; // @[dec_tlu_ctl.scala 686:41] - wire _T_478 = ~io_dec_tlu_packet_r_legal; // @[dec_tlu_ctl.scala 660:17] - wire _T_479 = _T_478 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 660:46] - wire _T_481 = _T_479 & _T_465; // @[dec_tlu_ctl.scala 660:70] - wire illegal_r = _T_481 & _T_470; // @[dec_tlu_ctl.scala 660:90] - wire _T_524 = _T_523 | illegal_r; // @[dec_tlu_ctl.scala 686:51] - wire _T_511 = inst_acc_r_raw & _T_470; // @[dec_tlu_ctl.scala 667:33] - wire inst_acc_r = _T_511 & _T_465; // @[dec_tlu_ctl.scala 667:46] - wire _T_525 = _T_524 | inst_acc_r; // @[dec_tlu_ctl.scala 686:63] - wire _T_527 = _T_525 & _T_470; // @[dec_tlu_ctl.scala 686:77] - wire _T_528 = ~io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 686:92] - wire i0_exception_valid_r = _T_527 & _T_528; // @[dec_tlu_ctl.scala 686:90] - wire _T_789 = i0_exception_valid_r | rfpc_i0_r; // @[dec_tlu_ctl.scala 785:49] - wire _T_402 = ~io_dec_tlu_flush_lower_wb; // @[dec_tlu_ctl.scala 609:57] - wire lsu_exc_valid_r_raw = io_lsu_error_pkt_r_valid & _T_402; // @[dec_tlu_ctl.scala 609:55] - wire _T_403 = io_lsu_error_pkt_r_valid & lsu_exc_valid_r_raw; // @[dec_tlu_ctl.scala 611:40] - wire _T_405 = _T_403 & _T_465; // @[dec_tlu_ctl.scala 611:62] - wire lsu_exc_valid_r = _T_405 & _T_470; // @[dec_tlu_ctl.scala 611:82] - wire _T_790 = _T_789 | lsu_exc_valid_r; // @[dec_tlu_ctl.scala 785:61] - wire _T_490 = io_dec_tlu_packet_r_fence_i & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 663:50] - wire _T_492 = _T_490 & _T_465; // @[dec_tlu_ctl.scala 663:74] - wire fence_i_r = _T_492 & _T_470; // @[dec_tlu_ctl.scala 663:95] - wire _T_791 = _T_790 | fence_i_r; // @[dec_tlu_ctl.scala 785:79] - wire _T_792 = _T_791 | lsu_i0_rfnpc_r; // @[dec_tlu_ctl.scala 785:91] - wire _T_414 = io_dec_tlu_i0_valid_r & _T_470; // @[dec_tlu_ctl.scala 624:50] - wire _T_415 = ~lsu_exc_valid_r; // @[dec_tlu_ctl.scala 624:65] - wire _T_416 = _T_414 & _T_415; // @[dec_tlu_ctl.scala 624:63] - wire _T_417 = ~inst_acc_r; // @[dec_tlu_ctl.scala 624:82] - wire _T_418 = _T_416 & _T_417; // @[dec_tlu_ctl.scala 624:79] - wire _T_420 = _T_418 & _T_528; // @[dec_tlu_ctl.scala 624:94] - reg request_debug_mode_r_d1; // @[dec_tlu_ctl.scala 462:81] - wire _T_421 = ~request_debug_mode_r_d1; // @[dec_tlu_ctl.scala 624:121] - wire _T_422 = _T_420 & _T_421; // @[dec_tlu_ctl.scala 624:119] - wire tlu_i0_commit_cmt = _T_422 & _T_465; // @[dec_tlu_ctl.scala 624:146] + wire _T_433 = ic_perr_r_d1 | iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 631:154] + wire _T_435 = _T_433 & _T_107; // @[dec_tlu_ctl.scala 631:173] + wire _T_436 = _T_432 | _T_435; // @[dec_tlu_ctl.scala 631:137] + wire _T_438 = _T_436 & _T_465; // @[dec_tlu_ctl.scala 631:196] + wire _T_410 = io_dec_tlu_i0_valid_r & _T_465; // @[dec_tlu_ctl.scala 619:47] + wire _T_411 = ~io_lsu_error_pkt_r_bits_inst_type; // @[dec_tlu_ctl.scala 619:70] + wire _T_412 = _T_411 & io_lsu_error_pkt_r_bits_single_ecc_error; // @[dec_tlu_ctl.scala 619:105] + wire lsu_i0_rfnpc_r = _T_410 & _T_412; // @[dec_tlu_ctl.scala 619:67] + wire _T_439 = ~lsu_i0_rfnpc_r; // @[dec_tlu_ctl.scala 631:220] + wire rfpc_i0_r = _T_438 & _T_439; // @[dec_tlu_ctl.scala 631:217] + wire _T_470 = ~rfpc_i0_r; // @[dec_tlu_ctl.scala 656:132] + wire ebreak_r = _T_469 & _T_470; // @[dec_tlu_ctl.scala 656:130] + wire _T_472 = io_dec_tlu_packet_r_pmu_i0_itype == 4'h9; // @[dec_tlu_ctl.scala 657:51] + wire _T_473 = _T_472 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 657:64] + wire _T_475 = _T_473 & _T_465; // @[dec_tlu_ctl.scala 657:88] + wire ecall_r = _T_475 & _T_470; // @[dec_tlu_ctl.scala 657:108] + wire _T_523 = ebreak_r | ecall_r; // @[dec_tlu_ctl.scala 684:41] + wire _T_478 = ~io_dec_tlu_packet_r_legal; // @[dec_tlu_ctl.scala 658:17] + wire _T_479 = _T_478 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 658:46] + wire _T_481 = _T_479 & _T_465; // @[dec_tlu_ctl.scala 658:70] + wire illegal_r = _T_481 & _T_470; // @[dec_tlu_ctl.scala 658:90] + wire _T_524 = _T_523 | illegal_r; // @[dec_tlu_ctl.scala 684:51] + wire _T_511 = inst_acc_r_raw & _T_470; // @[dec_tlu_ctl.scala 665:33] + wire inst_acc_r = _T_511 & _T_465; // @[dec_tlu_ctl.scala 665:46] + wire _T_525 = _T_524 | inst_acc_r; // @[dec_tlu_ctl.scala 684:63] + wire _T_527 = _T_525 & _T_470; // @[dec_tlu_ctl.scala 684:77] + wire _T_528 = ~io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 684:92] + wire i0_exception_valid_r = _T_527 & _T_528; // @[dec_tlu_ctl.scala 684:90] + wire _T_789 = i0_exception_valid_r | rfpc_i0_r; // @[dec_tlu_ctl.scala 783:49] + wire _T_402 = ~io_dec_tlu_flush_lower_wb; // @[dec_tlu_ctl.scala 607:57] + wire lsu_exc_valid_r_raw = io_lsu_error_pkt_r_valid & _T_402; // @[dec_tlu_ctl.scala 607:55] + wire _T_403 = io_lsu_error_pkt_r_valid & lsu_exc_valid_r_raw; // @[dec_tlu_ctl.scala 609:40] + wire _T_405 = _T_403 & _T_465; // @[dec_tlu_ctl.scala 609:62] + wire lsu_exc_valid_r = _T_405 & _T_470; // @[dec_tlu_ctl.scala 609:82] + wire _T_790 = _T_789 | lsu_exc_valid_r; // @[dec_tlu_ctl.scala 783:61] + wire _T_490 = io_dec_tlu_packet_r_fence_i & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 661:50] + wire _T_492 = _T_490 & _T_465; // @[dec_tlu_ctl.scala 661:74] + wire fence_i_r = _T_492 & _T_470; // @[dec_tlu_ctl.scala 661:95] + wire _T_791 = _T_790 | fence_i_r; // @[dec_tlu_ctl.scala 783:79] + wire _T_792 = _T_791 | lsu_i0_rfnpc_r; // @[dec_tlu_ctl.scala 783:91] + wire _T_414 = io_dec_tlu_i0_valid_r & _T_470; // @[dec_tlu_ctl.scala 622:50] + wire _T_415 = ~lsu_exc_valid_r; // @[dec_tlu_ctl.scala 622:65] + wire _T_416 = _T_414 & _T_415; // @[dec_tlu_ctl.scala 622:63] + wire _T_417 = ~inst_acc_r; // @[dec_tlu_ctl.scala 622:82] + wire _T_418 = _T_416 & _T_417; // @[dec_tlu_ctl.scala 622:79] + wire _T_420 = _T_418 & _T_528; // @[dec_tlu_ctl.scala 622:94] + reg request_debug_mode_r_d1; // @[dec_tlu_ctl.scala 460:81] + wire _T_421 = ~request_debug_mode_r_d1; // @[dec_tlu_ctl.scala 622:121] + wire _T_422 = _T_420 & _T_421; // @[dec_tlu_ctl.scala 622:119] + wire tlu_i0_commit_cmt = _T_422 & _T_465; // @[dec_tlu_ctl.scala 622:146] reg iccm_repair_state_d1; // @[dec_tlu_ctl.scala 321:80] - wire _T_444 = tlu_i0_commit_cmt & iccm_repair_state_d1; // @[dec_tlu_ctl.scala 642:52] - wire _T_484 = io_dec_tlu_packet_r_pmu_i0_itype == 4'hc; // @[dec_tlu_ctl.scala 661:51] - wire _T_485 = _T_484 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 661:64] - wire _T_487 = _T_485 & _T_465; // @[dec_tlu_ctl.scala 661:88] - wire mret_r = _T_487 & _T_470; // @[dec_tlu_ctl.scala 661:108] - wire _T_446 = _T_523 | mret_r; // @[dec_tlu_ctl.scala 642:98] - wire take_reset = reset_delayed & io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 771:32] - wire _T_447 = _T_446 | take_reset; // @[dec_tlu_ctl.scala 642:107] - wire _T_448 = _T_447 | illegal_r; // @[dec_tlu_ctl.scala 642:120] - wire _T_449 = io_dec_csr_wraddr_r == 12'h7c2; // @[dec_tlu_ctl.scala 642:176] - wire _T_450 = dec_csr_wen_r_mod & _T_449; // @[dec_tlu_ctl.scala 642:153] - wire _T_451 = _T_448 | _T_450; // @[dec_tlu_ctl.scala 642:132] - wire _T_452 = ~_T_451; // @[dec_tlu_ctl.scala 642:77] - wire iccm_repair_state_rfnpc = _T_444 & _T_452; // @[dec_tlu_ctl.scala 642:75] - wire _T_793 = _T_792 | iccm_repair_state_rfnpc; // @[dec_tlu_ctl.scala 785:108] - wire _T_794 = _T_793 | debug_resume_req_f; // @[dec_tlu_ctl.scala 785:135] - wire _T_786 = i_cpu_run_req_d1 & pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 783:43] - wire _T_211 = ~io_dec_pause_state; // @[dec_tlu_ctl.scala 482:28] - reg dec_pause_state_f; // @[dec_tlu_ctl.scala 461:81] - wire _T_212 = _T_211 & dec_pause_state_f; // @[dec_tlu_ctl.scala 482:48] - wire _T_213 = ext_int_ready | ce_int_ready; // @[dec_tlu_ctl.scala 482:86] - wire _T_214 = _T_213 | timer_int_ready; // @[dec_tlu_ctl.scala 482:101] - wire _T_215 = _T_214 | soft_int_ready; // @[dec_tlu_ctl.scala 482:119] - wire _T_216 = _T_215 | int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 482:136] - wire _T_217 = _T_216 | int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 482:160] - wire _T_218 = _T_217 | nmi_int_detected; // @[dec_tlu_ctl.scala 482:184] - wire _T_219 = _T_218 | ext_int_freeze_d1; // @[dec_tlu_ctl.scala 482:203] - wire _T_220 = ~_T_219; // @[dec_tlu_ctl.scala 482:70] - wire _T_221 = _T_212 & _T_220; // @[dec_tlu_ctl.scala 482:68] - wire _T_223 = _T_221 & _T_140; // @[dec_tlu_ctl.scala 482:224] - wire _T_225 = _T_223 & _T_378; // @[dec_tlu_ctl.scala 482:248] - wire _T_226 = ~pmu_fw_halt_req_f; // @[dec_tlu_ctl.scala 482:270] - wire _T_227 = _T_225 & _T_226; // @[dec_tlu_ctl.scala 482:268] - wire _T_228 = ~halt_taken_f; // @[dec_tlu_ctl.scala 482:291] - wire pause_expired_r = _T_227 & _T_228; // @[dec_tlu_ctl.scala 482:289] - wire sel_npc_resume = _T_786 | pause_expired_r; // @[dec_tlu_ctl.scala 783:66] - wire _T_795 = _T_794 | sel_npc_resume; // @[dec_tlu_ctl.scala 785:157] - reg dec_tlu_wr_pause_r_d1; // @[dec_tlu_ctl.scala 460:81] - wire _T_796 = _T_795 | dec_tlu_wr_pause_r_d1; // @[dec_tlu_ctl.scala 785:175] - wire synchronous_flush_r = _T_796 | i0_trigger_hit_raw_r; // @[dec_tlu_ctl.scala 785:201] - wire _T_749 = ~synchronous_flush_r; // @[dec_tlu_ctl.scala 772:195] - wire _T_750 = _T_748 & _T_749; // @[dec_tlu_ctl.scala 772:193] - wire _T_751 = ~mret_r; // @[dec_tlu_ctl.scala 772:218] - wire _T_752 = _T_750 & _T_751; // @[dec_tlu_ctl.scala 772:216] - wire _T_753 = ~take_reset; // @[dec_tlu_ctl.scala 772:228] - wire _T_754 = _T_752 & _T_753; // @[dec_tlu_ctl.scala 772:226] - wire _T_519 = _T_466 & dcsr[15]; // @[dec_tlu_ctl.scala 670:121] - wire ebreak_to_debug_mode_r = _T_519 & _T_470; // @[dec_tlu_ctl.scala 670:142] - wire _T_755 = ~ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 772:242] - wire _T_756 = _T_754 & _T_755; // @[dec_tlu_ctl.scala 772:240] - wire _T_760 = _T_107 | _T_44; // @[dec_tlu_ctl.scala 772:288] - wire take_nmi = _T_756 & _T_760; // @[dec_tlu_ctl.scala 772:266] - wire _T_670 = _T_669 | take_nmi; // @[dec_tlu_ctl.scala 740:155] - wire _T_671 = _T_670 | ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 740:166] - wire _T_672 = _T_671 | synchronous_flush_r; // @[dec_tlu_ctl.scala 740:191] - reg exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 811:90] - wire _T_673 = _T_672 | exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 740:214] - wire _T_674 = _T_673 | mret_r; // @[dec_tlu_ctl.scala 740:238] - wire block_interrupts = _T_674 | ext_int_freeze_d1; // @[dec_tlu_ctl.scala 740:247] - wire _T_704 = ~block_interrupts; // @[dec_tlu_ctl.scala 768:91] - wire take_timer_int = _T_703 & _T_704; // @[dec_tlu_ctl.scala 768:89] - wire _T_762 = take_ext_int | take_timer_int; // @[dec_tlu_ctl.scala 775:38] - wire _T_693 = soft_int_ready & _T_700; // @[dec_tlu_ctl.scala 767:36] - wire _T_695 = _T_693 & _T_702; // @[dec_tlu_ctl.scala 767:53] - wire take_soft_int = _T_695 & _T_704; // @[dec_tlu_ctl.scala 767:69] - wire _T_763 = _T_762 | take_soft_int; // @[dec_tlu_ctl.scala 775:55] - wire _T_764 = _T_763 | take_nmi; // @[dec_tlu_ctl.scala 775:71] - wire _T_689 = ce_int_ready & _T_700; // @[dec_tlu_ctl.scala 766:33] - wire take_ce_int = _T_689 & _T_704; // @[dec_tlu_ctl.scala 766:50] - wire _T_765 = _T_764 | take_ce_int; // @[dec_tlu_ctl.scala 775:82] - wire int_timer0_int_possible = mstatus_mie_ns & mie_ns[4]; // @[dec_tlu_ctl.scala 726:49] - wire int_timer0_int_ready = mip[4] & int_timer0_int_possible; // @[dec_tlu_ctl.scala 727:47] - wire _T_706 = int_timer0_int_ready | int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 769:49] - wire _T_707 = _T_706 & int_timer0_int_possible; // @[dec_tlu_ctl.scala 769:74] - wire _T_709 = _T_707 & _T_631; // @[dec_tlu_ctl.scala 769:100] - wire _T_710 = ~timer_int_ready; // @[dec_tlu_ctl.scala 769:129] - wire _T_711 = _T_709 & _T_710; // @[dec_tlu_ctl.scala 769:127] - wire _T_713 = _T_711 & _T_698; // @[dec_tlu_ctl.scala 769:146] - wire _T_715 = _T_713 & _T_700; // @[dec_tlu_ctl.scala 769:164] - wire _T_717 = _T_715 & _T_702; // @[dec_tlu_ctl.scala 769:181] - wire take_int_timer0_int = _T_717 & _T_704; // @[dec_tlu_ctl.scala 769:197] - wire _T_766 = _T_765 | take_int_timer0_int; // @[dec_tlu_ctl.scala 775:96] - wire int_timer1_int_possible = mstatus_mie_ns & mie_ns[3]; // @[dec_tlu_ctl.scala 728:49] - wire int_timer1_int_ready = mip[3] & int_timer1_int_possible; // @[dec_tlu_ctl.scala 729:47] - wire _T_720 = int_timer1_int_ready | int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 770:49] - wire _T_721 = _T_720 & int_timer1_int_possible; // @[dec_tlu_ctl.scala 770:74] - wire _T_723 = _T_721 & _T_631; // @[dec_tlu_ctl.scala 770:100] - wire _T_725 = ~_T_706; // @[dec_tlu_ctl.scala 770:129] - wire _T_726 = _T_723 & _T_725; // @[dec_tlu_ctl.scala 770:127] - wire _T_728 = _T_726 & _T_710; // @[dec_tlu_ctl.scala 770:177] - wire _T_730 = _T_728 & _T_698; // @[dec_tlu_ctl.scala 770:196] - wire _T_732 = _T_730 & _T_700; // @[dec_tlu_ctl.scala 770:214] - wire _T_734 = _T_732 & _T_702; // @[dec_tlu_ctl.scala 770:231] - wire take_int_timer1_int = _T_734 & _T_704; // @[dec_tlu_ctl.scala 770:247] - wire interrupt_valid_r = _T_766 | take_int_timer1_int; // @[dec_tlu_ctl.scala 775:118] + wire _T_444 = tlu_i0_commit_cmt & iccm_repair_state_d1; // @[dec_tlu_ctl.scala 640:52] + wire _T_484 = io_dec_tlu_packet_r_pmu_i0_itype == 4'hc; // @[dec_tlu_ctl.scala 659:51] + wire _T_485 = _T_484 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 659:64] + wire _T_487 = _T_485 & _T_465; // @[dec_tlu_ctl.scala 659:88] + wire mret_r = _T_487 & _T_470; // @[dec_tlu_ctl.scala 659:108] + wire _T_446 = _T_523 | mret_r; // @[dec_tlu_ctl.scala 640:98] + wire take_reset = reset_delayed & io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 769:32] + wire _T_447 = _T_446 | take_reset; // @[dec_tlu_ctl.scala 640:107] + wire _T_448 = _T_447 | illegal_r; // @[dec_tlu_ctl.scala 640:120] + wire _T_449 = io_dec_csr_wraddr_r == 12'h7c2; // @[dec_tlu_ctl.scala 640:176] + wire _T_450 = dec_csr_wen_r_mod & _T_449; // @[dec_tlu_ctl.scala 640:153] + wire _T_451 = _T_448 | _T_450; // @[dec_tlu_ctl.scala 640:132] + wire _T_452 = ~_T_451; // @[dec_tlu_ctl.scala 640:77] + wire iccm_repair_state_rfnpc = _T_444 & _T_452; // @[dec_tlu_ctl.scala 640:75] + wire _T_793 = _T_792 | iccm_repair_state_rfnpc; // @[dec_tlu_ctl.scala 783:108] + wire _T_794 = _T_793 | debug_resume_req_f; // @[dec_tlu_ctl.scala 783:135] + wire _T_786 = i_cpu_run_req_d1 & pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 781:43] + wire _T_211 = ~io_dec_pause_state; // @[dec_tlu_ctl.scala 480:28] + reg dec_pause_state_f; // @[dec_tlu_ctl.scala 459:81] + wire _T_212 = _T_211 & dec_pause_state_f; // @[dec_tlu_ctl.scala 480:48] + wire _T_213 = ext_int_ready | ce_int_ready; // @[dec_tlu_ctl.scala 480:86] + wire _T_214 = _T_213 | timer_int_ready; // @[dec_tlu_ctl.scala 480:101] + wire _T_215 = _T_214 | soft_int_ready; // @[dec_tlu_ctl.scala 480:119] + wire _T_216 = _T_215 | int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 480:136] + wire _T_217 = _T_216 | int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 480:160] + wire _T_218 = _T_217 | nmi_int_detected; // @[dec_tlu_ctl.scala 480:184] + wire _T_219 = _T_218 | ext_int_freeze_d1; // @[dec_tlu_ctl.scala 480:203] + wire _T_220 = ~_T_219; // @[dec_tlu_ctl.scala 480:70] + wire _T_221 = _T_212 & _T_220; // @[dec_tlu_ctl.scala 480:68] + wire _T_223 = _T_221 & _T_140; // @[dec_tlu_ctl.scala 480:224] + wire _T_225 = _T_223 & _T_378; // @[dec_tlu_ctl.scala 480:248] + wire _T_226 = ~pmu_fw_halt_req_f; // @[dec_tlu_ctl.scala 480:270] + wire _T_227 = _T_225 & _T_226; // @[dec_tlu_ctl.scala 480:268] + wire _T_228 = ~halt_taken_f; // @[dec_tlu_ctl.scala 480:291] + wire pause_expired_r = _T_227 & _T_228; // @[dec_tlu_ctl.scala 480:289] + wire sel_npc_resume = _T_786 | pause_expired_r; // @[dec_tlu_ctl.scala 781:66] + wire _T_795 = _T_794 | sel_npc_resume; // @[dec_tlu_ctl.scala 783:157] + reg dec_tlu_wr_pause_r_d1; // @[dec_tlu_ctl.scala 458:81] + wire _T_796 = _T_795 | dec_tlu_wr_pause_r_d1; // @[dec_tlu_ctl.scala 783:175] + wire synchronous_flush_r = _T_796 | i0_trigger_hit_raw_r; // @[dec_tlu_ctl.scala 783:201] + wire _T_749 = ~synchronous_flush_r; // @[dec_tlu_ctl.scala 770:195] + wire _T_750 = _T_748 & _T_749; // @[dec_tlu_ctl.scala 770:193] + wire _T_751 = ~mret_r; // @[dec_tlu_ctl.scala 770:218] + wire _T_752 = _T_750 & _T_751; // @[dec_tlu_ctl.scala 770:216] + wire _T_753 = ~take_reset; // @[dec_tlu_ctl.scala 770:228] + wire _T_754 = _T_752 & _T_753; // @[dec_tlu_ctl.scala 770:226] + wire _T_519 = _T_466 & dcsr[15]; // @[dec_tlu_ctl.scala 668:121] + wire ebreak_to_debug_mode_r = _T_519 & _T_470; // @[dec_tlu_ctl.scala 668:142] + wire _T_755 = ~ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 770:242] + wire _T_756 = _T_754 & _T_755; // @[dec_tlu_ctl.scala 770:240] + wire _T_760 = _T_107 | _T_44; // @[dec_tlu_ctl.scala 770:288] + wire take_nmi = _T_756 & _T_760; // @[dec_tlu_ctl.scala 770:266] + wire _T_670 = _T_669 | take_nmi; // @[dec_tlu_ctl.scala 738:155] + wire _T_671 = _T_670 | ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 738:166] + wire _T_672 = _T_671 | synchronous_flush_r; // @[dec_tlu_ctl.scala 738:191] + reg exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 809:90] + wire _T_673 = _T_672 | exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 738:214] + wire _T_674 = _T_673 | mret_r; // @[dec_tlu_ctl.scala 738:238] + wire block_interrupts = _T_674 | ext_int_freeze_d1; // @[dec_tlu_ctl.scala 738:247] + wire _T_704 = ~block_interrupts; // @[dec_tlu_ctl.scala 766:91] + wire take_timer_int = _T_703 & _T_704; // @[dec_tlu_ctl.scala 766:89] + wire _T_762 = take_ext_int | take_timer_int; // @[dec_tlu_ctl.scala 773:38] + wire _T_693 = soft_int_ready & _T_700; // @[dec_tlu_ctl.scala 765:36] + wire _T_695 = _T_693 & _T_702; // @[dec_tlu_ctl.scala 765:53] + wire take_soft_int = _T_695 & _T_704; // @[dec_tlu_ctl.scala 765:69] + wire _T_763 = _T_762 | take_soft_int; // @[dec_tlu_ctl.scala 773:55] + wire _T_764 = _T_763 | take_nmi; // @[dec_tlu_ctl.scala 773:71] + wire _T_689 = ce_int_ready & _T_700; // @[dec_tlu_ctl.scala 764:33] + wire take_ce_int = _T_689 & _T_704; // @[dec_tlu_ctl.scala 764:50] + wire _T_765 = _T_764 | take_ce_int; // @[dec_tlu_ctl.scala 773:82] + wire int_timer0_int_possible = mstatus_mie_ns & mie_ns[4]; // @[dec_tlu_ctl.scala 724:49] + wire int_timer0_int_ready = mip[4] & int_timer0_int_possible; // @[dec_tlu_ctl.scala 725:47] + wire _T_706 = int_timer0_int_ready | int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 767:49] + wire _T_707 = _T_706 & int_timer0_int_possible; // @[dec_tlu_ctl.scala 767:74] + wire _T_709 = _T_707 & _T_631; // @[dec_tlu_ctl.scala 767:100] + wire _T_710 = ~timer_int_ready; // @[dec_tlu_ctl.scala 767:129] + wire _T_711 = _T_709 & _T_710; // @[dec_tlu_ctl.scala 767:127] + wire _T_713 = _T_711 & _T_698; // @[dec_tlu_ctl.scala 767:146] + wire _T_715 = _T_713 & _T_700; // @[dec_tlu_ctl.scala 767:164] + wire _T_717 = _T_715 & _T_702; // @[dec_tlu_ctl.scala 767:181] + wire take_int_timer0_int = _T_717 & _T_704; // @[dec_tlu_ctl.scala 767:197] + wire _T_766 = _T_765 | take_int_timer0_int; // @[dec_tlu_ctl.scala 773:96] + wire int_timer1_int_possible = mstatus_mie_ns & mie_ns[3]; // @[dec_tlu_ctl.scala 726:49] + wire int_timer1_int_ready = mip[3] & int_timer1_int_possible; // @[dec_tlu_ctl.scala 727:47] + wire _T_720 = int_timer1_int_ready | int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 768:49] + wire _T_721 = _T_720 & int_timer1_int_possible; // @[dec_tlu_ctl.scala 768:74] + wire _T_723 = _T_721 & _T_631; // @[dec_tlu_ctl.scala 768:100] + wire _T_725 = ~_T_706; // @[dec_tlu_ctl.scala 768:129] + wire _T_726 = _T_723 & _T_725; // @[dec_tlu_ctl.scala 768:127] + wire _T_728 = _T_726 & _T_710; // @[dec_tlu_ctl.scala 768:177] + wire _T_730 = _T_728 & _T_698; // @[dec_tlu_ctl.scala 768:196] + wire _T_732 = _T_730 & _T_700; // @[dec_tlu_ctl.scala 768:214] + wire _T_734 = _T_732 & _T_702; // @[dec_tlu_ctl.scala 768:231] + wire take_int_timer1_int = _T_734 & _T_704; // @[dec_tlu_ctl.scala 768:247] + wire interrupt_valid_r = _T_766 | take_int_timer1_int; // @[dec_tlu_ctl.scala 773:118] wire _T_15 = _T_14 | interrupt_valid_r; // @[dec_tlu_ctl.scala 316:69] wire _T_16 = _T_15 | interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 316:89] wire _T_17 = _T_16 | reset_delayed; // @[dec_tlu_ctl.scala 316:112] wire _T_18 = _T_17 | pause_expired_r; // @[dec_tlu_ctl.scala 316:128] - reg pause_expired_wb; // @[dec_tlu_ctl.scala 816:90] + reg pause_expired_wb; // @[dec_tlu_ctl.scala 814:90] wire _T_19 = _T_18 | pause_expired_wb; // @[dec_tlu_ctl.scala 316:146] - wire _T_496 = io_tlu_mem_ifu_ic_error_start & _T_107; // @[dec_tlu_ctl.scala 664:51] - wire _T_498 = _T_152 | dcsr_single_step_running; // @[dec_tlu_ctl.scala 664:101] - wire _T_499 = _T_496 & _T_498; // @[dec_tlu_ctl.scala 664:72] - wire _T_500 = ~internal_pmu_fw_halt_mode_f; // @[dec_tlu_ctl.scala 664:131] - wire ic_perr_r = _T_499 & _T_500; // @[dec_tlu_ctl.scala 664:129] + wire _T_496 = io_tlu_mem_ifu_ic_error_start & _T_107; // @[dec_tlu_ctl.scala 662:51] + wire _T_498 = _T_152 | dcsr_single_step_running; // @[dec_tlu_ctl.scala 662:101] + wire _T_499 = _T_496 & _T_498; // @[dec_tlu_ctl.scala 662:72] + wire _T_500 = ~internal_pmu_fw_halt_mode_f; // @[dec_tlu_ctl.scala 662:131] + wire ic_perr_r = _T_499 & _T_500; // @[dec_tlu_ctl.scala 662:129] wire _T_20 = _T_19 | ic_perr_r; // @[dec_tlu_ctl.scala 316:165] wire _T_21 = _T_20 | ic_perr_r_d1; // @[dec_tlu_ctl.scala 316:177] - wire _T_503 = io_tlu_mem_ifu_iccm_rd_ecc_single_err & _T_107; // @[dec_tlu_ctl.scala 665:59] - wire _T_506 = _T_503 & _T_498; // @[dec_tlu_ctl.scala 665:80] - wire iccm_sbecc_r = _T_506 & _T_500; // @[dec_tlu_ctl.scala 665:137] + wire _T_503 = io_tlu_mem_ifu_iccm_rd_ecc_single_err & _T_107; // @[dec_tlu_ctl.scala 663:59] + wire _T_506 = _T_503 & _T_498; // @[dec_tlu_ctl.scala 663:80] + wire iccm_sbecc_r = _T_506 & _T_500; // @[dec_tlu_ctl.scala 663:137] wire _T_22 = _T_21 | iccm_sbecc_r; // @[dec_tlu_ctl.scala 316:192] wire _T_23 = _T_22 | iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 316:207] wire flush_clkvalid = _T_23 | io_dec_tlu_dec_clk_override; // @[dec_tlu_ctl.scala 316:225] @@ -55291,148 +55302,148 @@ module dec_tlu_ctl( reg _T_32; // @[dec_tlu_ctl.scala 329:73] reg internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 330:72] reg _T_33; // @[dec_tlu_ctl.scala 331:89] - reg nmi_lsu_load_type_f; // @[dec_tlu_ctl.scala 342:72] - reg nmi_lsu_store_type_f; // @[dec_tlu_ctl.scala 343:72] - wire _T_46 = nmi_lsu_detected & io_tlu_busbuff_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 351:48] - wire _T_49 = ~_T_41; // @[dec_tlu_ctl.scala 351:96] - wire _T_50 = _T_46 & _T_49; // @[dec_tlu_ctl.scala 351:94] - wire _T_52 = nmi_lsu_load_type_f & _T_40; // @[dec_tlu_ctl.scala 351:159] - wire _T_54 = nmi_lsu_detected & io_tlu_busbuff_lsu_imprecise_error_store_any; // @[dec_tlu_ctl.scala 352:49] - wire _T_58 = _T_54 & _T_49; // @[dec_tlu_ctl.scala 352:96] - wire _T_60 = nmi_lsu_store_type_f & _T_40; // @[dec_tlu_ctl.scala 352:162] - reg mpc_debug_halt_req_sync_f; // @[dec_tlu_ctl.scala 360:72] - reg mpc_debug_run_req_sync_f; // @[dec_tlu_ctl.scala 361:72] - reg mpc_run_state_f; // @[dec_tlu_ctl.scala 363:88] - reg debug_brkpt_status_f; // @[dec_tlu_ctl.scala 364:80] - reg mpc_debug_halt_ack_f; // @[dec_tlu_ctl.scala 365:80] - reg mpc_debug_run_ack_f; // @[dec_tlu_ctl.scala 366:80] - reg dbg_run_state_f; // @[dec_tlu_ctl.scala 368:88] - reg _T_65; // @[dec_tlu_ctl.scala 369:81] - wire _T_66 = ~mpc_debug_halt_req_sync_f; // @[dec_tlu_ctl.scala 373:71] - wire mpc_debug_halt_req_sync_pulse = mpc_debug_halt_req_sync & _T_66; // @[dec_tlu_ctl.scala 373:69] - wire _T_67 = ~mpc_debug_run_req_sync_f; // @[dec_tlu_ctl.scala 374:70] - wire mpc_debug_run_req_sync_pulse = mpc_debug_run_req_sync & _T_67; // @[dec_tlu_ctl.scala 374:68] - wire _T_68 = mpc_halt_state_f | mpc_debug_halt_req_sync_pulse; // @[dec_tlu_ctl.scala 376:48] - wire _T_71 = _T_68 | _T_111; // @[dec_tlu_ctl.scala 376:80] - wire _T_72 = ~mpc_debug_run_req_sync; // @[dec_tlu_ctl.scala 376:125] - wire mpc_halt_state_ns = _T_71 & _T_72; // @[dec_tlu_ctl.scala 376:123] - wire _T_74 = ~mpc_debug_run_ack_f; // @[dec_tlu_ctl.scala 377:80] - wire _T_75 = mpc_debug_run_req_sync_pulse & _T_74; // @[dec_tlu_ctl.scala 377:78] - wire _T_76 = mpc_run_state_f | _T_75; // @[dec_tlu_ctl.scala 377:46] - wire _T_77 = ~dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 377:133] - wire _T_78 = debug_mode_status & _T_77; // @[dec_tlu_ctl.scala 377:131] - wire mpc_run_state_ns = _T_76 & _T_78; // @[dec_tlu_ctl.scala 377:103] - wire _T_80 = dbg_halt_req_final | dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 379:70] - wire _T_81 = _T_80 | trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 379:96] - wire _T_82 = _T_81 | ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 379:121] - wire _T_83 = dbg_halt_state_f | _T_82; // @[dec_tlu_ctl.scala 379:48] - wire _T_84 = ~io_dbg_resume_req; // @[dec_tlu_ctl.scala 379:153] - wire dbg_halt_state_ns = _T_83 & _T_84; // @[dec_tlu_ctl.scala 379:151] - wire _T_86 = dbg_run_state_f | io_dbg_resume_req; // @[dec_tlu_ctl.scala 380:46] - wire dbg_run_state_ns = _T_86 & _T_78; // @[dec_tlu_ctl.scala 380:67] - wire debug_brkpt_valid = ebreak_to_debug_mode_r_d1 | trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 386:59] - wire _T_92 = debug_brkpt_valid | debug_brkpt_status_f; // @[dec_tlu_ctl.scala 387:53] - wire _T_94 = internal_dbg_halt_mode & _T_77; // @[dec_tlu_ctl.scala 387:103] - wire _T_96 = mpc_halt_state_f & debug_mode_status; // @[dec_tlu_ctl.scala 390:51] - wire _T_97 = _T_96 & mpc_debug_halt_req_sync; // @[dec_tlu_ctl.scala 390:78] - wire _T_99 = ~dbg_halt_state_ns; // @[dec_tlu_ctl.scala 391:59] - wire _T_100 = mpc_debug_run_req_sync & _T_99; // @[dec_tlu_ctl.scala 391:57] - wire _T_101 = ~mpc_debug_halt_req_sync; // @[dec_tlu_ctl.scala 391:80] - wire _T_102 = _T_100 & _T_101; // @[dec_tlu_ctl.scala 391:78] - wire _T_103 = mpc_debug_run_ack_f & mpc_debug_run_req_sync; // @[dec_tlu_ctl.scala 391:129] - wire _T_118 = mpc_run_state_ns & _T_99; // @[dec_tlu_ctl.scala 405:73] - wire _T_119 = ~mpc_halt_state_ns; // @[dec_tlu_ctl.scala 405:117] - wire _T_120 = dbg_run_state_ns & _T_119; // @[dec_tlu_ctl.scala 405:115] - wire _T_121 = _T_118 | _T_120; // @[dec_tlu_ctl.scala 405:95] - wire _T_122 = debug_halt_req_f | pmu_fw_halt_req_f; // @[dec_tlu_ctl.scala 410:43] - wire _T_124 = _T_122 & _T_749; // @[dec_tlu_ctl.scala 410:64] - wire _T_126 = _T_124 & _T_751; // @[dec_tlu_ctl.scala 410:87] - wire _T_128 = _T_126 & _T_228; // @[dec_tlu_ctl.scala 410:97] - wire _T_129 = ~dec_tlu_flush_noredir_r_d1; // @[dec_tlu_ctl.scala 410:115] - wire _T_130 = _T_128 & _T_129; // @[dec_tlu_ctl.scala 410:113] - wire take_halt = _T_130 & _T_753; // @[dec_tlu_ctl.scala 410:143] - wire _T_170 = debug_resume_req_f & dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 435:49] - wire _T_172 = io_dec_tlu_i0_valid_r & _T_528; // @[dec_tlu_ctl.scala 437:59] - wire _T_174 = _T_172 & dcsr[2]; // @[dec_tlu_ctl.scala 437:84] - wire _T_329 = mtdata1_t_3[6] & mtdata1_t_3[9]; // @[dec_tlu_ctl.scala 532:61] - wire _T_332 = mtdata1_t_2[6] & mtdata1_t_2[9]; // @[dec_tlu_ctl.scala 532:121] - wire _T_335 = mtdata1_t_1[6] & mtdata1_t_1[9]; // @[dec_tlu_ctl.scala 532:181] - wire _T_338 = mtdata1_t_0[6] & mtdata1_t_0[9]; // @[dec_tlu_ctl.scala 532:241] + reg nmi_lsu_load_type_f; // @[dec_tlu_ctl.scala 340:72] + reg nmi_lsu_store_type_f; // @[dec_tlu_ctl.scala 341:72] + wire _T_46 = nmi_lsu_detected & io_tlu_busbuff_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 349:48] + wire _T_49 = ~_T_41; // @[dec_tlu_ctl.scala 349:96] + wire _T_50 = _T_46 & _T_49; // @[dec_tlu_ctl.scala 349:94] + wire _T_52 = nmi_lsu_load_type_f & _T_40; // @[dec_tlu_ctl.scala 349:159] + wire _T_54 = nmi_lsu_detected & io_tlu_busbuff_lsu_imprecise_error_store_any; // @[dec_tlu_ctl.scala 350:49] + wire _T_58 = _T_54 & _T_49; // @[dec_tlu_ctl.scala 350:96] + wire _T_60 = nmi_lsu_store_type_f & _T_40; // @[dec_tlu_ctl.scala 350:162] + reg mpc_debug_halt_req_sync_f; // @[dec_tlu_ctl.scala 358:72] + reg mpc_debug_run_req_sync_f; // @[dec_tlu_ctl.scala 359:72] + reg mpc_run_state_f; // @[dec_tlu_ctl.scala 361:88] + reg debug_brkpt_status_f; // @[dec_tlu_ctl.scala 362:80] + reg mpc_debug_halt_ack_f; // @[dec_tlu_ctl.scala 363:80] + reg mpc_debug_run_ack_f; // @[dec_tlu_ctl.scala 364:80] + reg dbg_run_state_f; // @[dec_tlu_ctl.scala 366:88] + reg _T_65; // @[dec_tlu_ctl.scala 367:81] + wire _T_66 = ~mpc_debug_halt_req_sync_f; // @[dec_tlu_ctl.scala 371:71] + wire mpc_debug_halt_req_sync_pulse = mpc_debug_halt_req_sync & _T_66; // @[dec_tlu_ctl.scala 371:69] + wire _T_67 = ~mpc_debug_run_req_sync_f; // @[dec_tlu_ctl.scala 372:70] + wire mpc_debug_run_req_sync_pulse = mpc_debug_run_req_sync & _T_67; // @[dec_tlu_ctl.scala 372:68] + wire _T_68 = mpc_halt_state_f | mpc_debug_halt_req_sync_pulse; // @[dec_tlu_ctl.scala 374:48] + wire _T_71 = _T_68 | _T_111; // @[dec_tlu_ctl.scala 374:80] + wire _T_72 = ~mpc_debug_run_req_sync; // @[dec_tlu_ctl.scala 374:125] + wire mpc_halt_state_ns = _T_71 & _T_72; // @[dec_tlu_ctl.scala 374:123] + wire _T_74 = ~mpc_debug_run_ack_f; // @[dec_tlu_ctl.scala 375:80] + wire _T_75 = mpc_debug_run_req_sync_pulse & _T_74; // @[dec_tlu_ctl.scala 375:78] + wire _T_76 = mpc_run_state_f | _T_75; // @[dec_tlu_ctl.scala 375:46] + wire _T_77 = ~dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 375:133] + wire _T_78 = debug_mode_status & _T_77; // @[dec_tlu_ctl.scala 375:131] + wire mpc_run_state_ns = _T_76 & _T_78; // @[dec_tlu_ctl.scala 375:103] + wire _T_80 = dbg_halt_req_final | dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 377:70] + wire _T_81 = _T_80 | trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 377:96] + wire _T_82 = _T_81 | ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 377:121] + wire _T_83 = dbg_halt_state_f | _T_82; // @[dec_tlu_ctl.scala 377:48] + wire _T_84 = ~io_dbg_resume_req; // @[dec_tlu_ctl.scala 377:153] + wire dbg_halt_state_ns = _T_83 & _T_84; // @[dec_tlu_ctl.scala 377:151] + wire _T_86 = dbg_run_state_f | io_dbg_resume_req; // @[dec_tlu_ctl.scala 378:46] + wire dbg_run_state_ns = _T_86 & _T_78; // @[dec_tlu_ctl.scala 378:67] + wire debug_brkpt_valid = ebreak_to_debug_mode_r_d1 | trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 384:59] + wire _T_92 = debug_brkpt_valid | debug_brkpt_status_f; // @[dec_tlu_ctl.scala 385:53] + wire _T_94 = internal_dbg_halt_mode & _T_77; // @[dec_tlu_ctl.scala 385:103] + wire _T_96 = mpc_halt_state_f & debug_mode_status; // @[dec_tlu_ctl.scala 388:51] + wire _T_97 = _T_96 & mpc_debug_halt_req_sync; // @[dec_tlu_ctl.scala 388:78] + wire _T_99 = ~dbg_halt_state_ns; // @[dec_tlu_ctl.scala 389:59] + wire _T_100 = mpc_debug_run_req_sync & _T_99; // @[dec_tlu_ctl.scala 389:57] + wire _T_101 = ~mpc_debug_halt_req_sync; // @[dec_tlu_ctl.scala 389:80] + wire _T_102 = _T_100 & _T_101; // @[dec_tlu_ctl.scala 389:78] + wire _T_103 = mpc_debug_run_ack_f & mpc_debug_run_req_sync; // @[dec_tlu_ctl.scala 389:129] + wire _T_118 = mpc_run_state_ns & _T_99; // @[dec_tlu_ctl.scala 403:73] + wire _T_119 = ~mpc_halt_state_ns; // @[dec_tlu_ctl.scala 403:117] + wire _T_120 = dbg_run_state_ns & _T_119; // @[dec_tlu_ctl.scala 403:115] + wire _T_121 = _T_118 | _T_120; // @[dec_tlu_ctl.scala 403:95] + wire _T_122 = debug_halt_req_f | pmu_fw_halt_req_f; // @[dec_tlu_ctl.scala 408:43] + wire _T_124 = _T_122 & _T_749; // @[dec_tlu_ctl.scala 408:64] + wire _T_126 = _T_124 & _T_751; // @[dec_tlu_ctl.scala 408:87] + wire _T_128 = _T_126 & _T_228; // @[dec_tlu_ctl.scala 408:97] + wire _T_129 = ~dec_tlu_flush_noredir_r_d1; // @[dec_tlu_ctl.scala 408:115] + wire _T_130 = _T_128 & _T_129; // @[dec_tlu_ctl.scala 408:113] + wire take_halt = _T_130 & _T_753; // @[dec_tlu_ctl.scala 408:143] + wire _T_170 = debug_resume_req_f & dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 433:49] + wire _T_172 = io_dec_tlu_i0_valid_r & _T_528; // @[dec_tlu_ctl.scala 435:59] + wire _T_174 = _T_172 & dcsr[2]; // @[dec_tlu_ctl.scala 435:84] + wire _T_329 = mtdata1_t_3[6] & mtdata1_t_3[9]; // @[dec_tlu_ctl.scala 530:61] + wire _T_332 = mtdata1_t_2[6] & mtdata1_t_2[9]; // @[dec_tlu_ctl.scala 530:121] + wire _T_335 = mtdata1_t_1[6] & mtdata1_t_1[9]; // @[dec_tlu_ctl.scala 530:181] + wire _T_338 = mtdata1_t_0[6] & mtdata1_t_0[9]; // @[dec_tlu_ctl.scala 530:241] wire [3:0] trigger_action = {_T_329,_T_332,_T_335,_T_338}; // @[Cat.scala 29:58] - wire [3:0] _T_343 = i0_trigger_chain_masked_r & trigger_action; // @[dec_tlu_ctl.scala 538:57] - wire i0_trigger_action_r = |_T_343; // @[dec_tlu_ctl.scala 538:75] - wire trigger_hit_dmode_r = i0_trigger_hit_raw_r & i0_trigger_action_r; // @[dec_tlu_ctl.scala 540:45] - wire _T_180 = trigger_hit_dmode_r | ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 444:57] - wire _T_182 = request_debug_mode_r_d1 & _T_402; // @[dec_tlu_ctl.scala 444:110] - reg request_debug_mode_done_f; // @[dec_tlu_ctl.scala 463:73] - wire _T_183 = request_debug_mode_r_d1 | request_debug_mode_done_f; // @[dec_tlu_ctl.scala 446:64] - reg _T_190; // @[dec_tlu_ctl.scala 454:81] - wire _T_201 = fence_i_r & internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 475:71] - wire _T_202 = take_halt | _T_201; // @[dec_tlu_ctl.scala 475:58] - wire _T_203 = _T_202 | io_dec_tlu_flush_pause_r; // @[dec_tlu_ctl.scala 475:97] - wire _T_204 = i0_trigger_hit_raw_r & trigger_hit_dmode_r; // @[dec_tlu_ctl.scala 475:144] - wire _T_205 = _T_203 | _T_204; // @[dec_tlu_ctl.scala 475:124] - wire take_ext_int_start = ext_int_ready & _T_704; // @[dec_tlu_ctl.scala 748:45] - wire _T_207 = ~interrupt_valid_r; // @[dec_tlu_ctl.scala 480:61] - wire _T_208 = dec_tlu_wr_pause_r_d1 & _T_207; // @[dec_tlu_ctl.scala 480:59] - wire _T_209 = ~take_ext_int_start; // @[dec_tlu_ctl.scala 480:82] - wire _T_231 = io_tlu_exu_dec_tlu_flush_lower_r & dcsr[2]; // @[dec_tlu_ctl.scala 484:82] - wire _T_232 = io_dec_tlu_resume_ack | dcsr_single_step_running; // @[dec_tlu_ctl.scala 484:125] - wire _T_233 = _T_231 & _T_232; // @[dec_tlu_ctl.scala 484:100] - wire _T_234 = ~io_tlu_ifc_dec_tlu_flush_noredir_wb; // @[dec_tlu_ctl.scala 484:155] + wire [3:0] _T_343 = i0_trigger_chain_masked_r & trigger_action; // @[dec_tlu_ctl.scala 536:57] + wire i0_trigger_action_r = |_T_343; // @[dec_tlu_ctl.scala 536:75] + wire trigger_hit_dmode_r = i0_trigger_hit_raw_r & i0_trigger_action_r; // @[dec_tlu_ctl.scala 538:45] + wire _T_180 = trigger_hit_dmode_r | ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 442:57] + wire _T_182 = request_debug_mode_r_d1 & _T_402; // @[dec_tlu_ctl.scala 442:110] + reg request_debug_mode_done_f; // @[dec_tlu_ctl.scala 461:73] + wire _T_183 = request_debug_mode_r_d1 | request_debug_mode_done_f; // @[dec_tlu_ctl.scala 444:64] + reg _T_190; // @[dec_tlu_ctl.scala 452:81] + wire _T_201 = fence_i_r & internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 473:71] + wire _T_202 = take_halt | _T_201; // @[dec_tlu_ctl.scala 473:58] + wire _T_203 = _T_202 | io_dec_tlu_flush_pause_r; // @[dec_tlu_ctl.scala 473:97] + wire _T_204 = i0_trigger_hit_raw_r & trigger_hit_dmode_r; // @[dec_tlu_ctl.scala 473:144] + wire _T_205 = _T_203 | _T_204; // @[dec_tlu_ctl.scala 473:124] + wire take_ext_int_start = ext_int_ready & _T_704; // @[dec_tlu_ctl.scala 746:45] + wire _T_207 = ~interrupt_valid_r; // @[dec_tlu_ctl.scala 478:61] + wire _T_208 = dec_tlu_wr_pause_r_d1 & _T_207; // @[dec_tlu_ctl.scala 478:59] + wire _T_209 = ~take_ext_int_start; // @[dec_tlu_ctl.scala 478:82] + wire _T_231 = io_tlu_exu_dec_tlu_flush_lower_r & dcsr[2]; // @[dec_tlu_ctl.scala 482:82] + wire _T_232 = io_dec_tlu_resume_ack | dcsr_single_step_running; // @[dec_tlu_ctl.scala 482:125] + wire _T_233 = _T_231 & _T_232; // @[dec_tlu_ctl.scala 482:100] + wire _T_234 = ~io_tlu_ifc_dec_tlu_flush_noredir_wb; // @[dec_tlu_ctl.scala 482:155] wire [3:0] _T_342 = i0_trigger_hit_raw_r ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire _T_345 = ~trigger_hit_dmode_r; // @[dec_tlu_ctl.scala 542:55] - wire mepc_trigger_hit_sel_pc_r = i0_trigger_hit_raw_r & _T_345; // @[dec_tlu_ctl.scala 542:53] - wire _T_350 = i_cpu_run_req_sync & _T_346; // @[dec_tlu_ctl.scala 570:58] - wire _T_351 = _T_350 & pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 570:83] - wire i_cpu_run_req_sync_qual = _T_351 & _T_107; // @[dec_tlu_ctl.scala 570:105] - reg _T_353; // @[dec_tlu_ctl.scala 574:81] - reg _T_354; // @[dec_tlu_ctl.scala 575:81] - reg _T_355; // @[dec_tlu_ctl.scala 576:81] - wire _T_384 = io_o_cpu_halt_status & _T_375; // @[dec_tlu_ctl.scala 594:89] - wire _T_386 = _T_384 & _T_152; // @[dec_tlu_ctl.scala 594:109] - wire _T_388 = io_o_cpu_halt_status & i_cpu_run_req_sync_qual; // @[dec_tlu_ctl.scala 595:41] - wire _T_389 = io_o_cpu_run_ack & i_cpu_run_req_sync_qual; // @[dec_tlu_ctl.scala 595:88] - reg lsu_single_ecc_error_r_d1; // @[dec_tlu_ctl.scala 607:72] - reg lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 614:73] - wire _T_408 = ~io_lsu_error_pkt_r_bits_exc_type; // @[dec_tlu_ctl.scala 615:40] - wire lsu_exc_ma_r = lsu_exc_valid_r & _T_408; // @[dec_tlu_ctl.scala 615:38] - wire lsu_exc_acc_r = lsu_exc_valid_r & io_lsu_error_pkt_r_bits_exc_type; // @[dec_tlu_ctl.scala 616:38] - wire lsu_exc_st_r = lsu_exc_valid_r & io_lsu_error_pkt_r_bits_inst_type; // @[dec_tlu_ctl.scala 617:38] - wire _T_424 = rfpc_i0_r | lsu_exc_valid_r; // @[dec_tlu_ctl.scala 627:38] - wire _T_425 = _T_424 | inst_acc_r; // @[dec_tlu_ctl.scala 627:53] - wire _T_426 = illegal_r & io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 627:79] - wire _T_427 = _T_425 | _T_426; // @[dec_tlu_ctl.scala 627:66] - wire _T_441 = ~io_tlu_exu_dec_tlu_flush_lower_r; // @[dec_tlu_ctl.scala 636:70] - wire _T_442 = iccm_repair_state_d1 & _T_441; // @[dec_tlu_ctl.scala 636:68] - wire _T_453 = io_tlu_exu_exu_i0_br_error_r & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 645:59] - wire _T_455 = io_tlu_exu_exu_i0_br_start_error_r & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 646:71] - wire _T_457 = io_tlu_exu_exu_i0_br_valid_r & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 647:55] - wire _T_459 = _T_457 & _T_429; // @[dec_tlu_ctl.scala 647:79] - wire _T_460 = ~io_tlu_exu_exu_i0_br_mp_r; // @[dec_tlu_ctl.scala 647:106] - wire _T_461 = ~io_tlu_exu_exu_pmu_i0_br_ataken; // @[dec_tlu_ctl.scala 647:135] - wire _T_462 = _T_460 | _T_461; // @[dec_tlu_ctl.scala 647:133] - wire _T_529 = ~take_nmi; // @[dec_tlu_ctl.scala 695:33] - wire _T_530 = take_ext_int & _T_529; // @[dec_tlu_ctl.scala 695:31] - wire _T_533 = take_timer_int & _T_529; // @[dec_tlu_ctl.scala 696:25] - wire _T_536 = take_soft_int & _T_529; // @[dec_tlu_ctl.scala 697:24] - wire _T_539 = take_int_timer0_int & _T_529; // @[dec_tlu_ctl.scala 698:30] - wire _T_542 = take_int_timer1_int & _T_529; // @[dec_tlu_ctl.scala 699:30] - wire _T_545 = take_ce_int & _T_529; // @[dec_tlu_ctl.scala 700:22] - wire _T_548 = illegal_r & _T_529; // @[dec_tlu_ctl.scala 701:20] - wire _T_551 = ecall_r & _T_529; // @[dec_tlu_ctl.scala 702:19] - wire _T_554 = inst_acc_r & _T_529; // @[dec_tlu_ctl.scala 703:22] - wire _T_556 = ebreak_r | i0_trigger_hit_raw_r; // @[dec_tlu_ctl.scala 704:20] - wire _T_558 = _T_556 & _T_529; // @[dec_tlu_ctl.scala 704:40] - wire _T_560 = ~lsu_exc_st_r; // @[dec_tlu_ctl.scala 705:25] - wire _T_561 = lsu_exc_ma_r & _T_560; // @[dec_tlu_ctl.scala 705:23] - wire _T_563 = _T_561 & _T_529; // @[dec_tlu_ctl.scala 705:39] - wire _T_566 = lsu_exc_acc_r & _T_560; // @[dec_tlu_ctl.scala 706:24] - wire _T_568 = _T_566 & _T_529; // @[dec_tlu_ctl.scala 706:40] - wire _T_570 = lsu_exc_ma_r & lsu_exc_st_r; // @[dec_tlu_ctl.scala 707:23] - wire _T_572 = _T_570 & _T_529; // @[dec_tlu_ctl.scala 707:38] - wire _T_574 = lsu_exc_acc_r & lsu_exc_st_r; // @[dec_tlu_ctl.scala 708:24] - wire _T_576 = _T_574 & _T_529; // @[dec_tlu_ctl.scala 708:39] + wire _T_345 = ~trigger_hit_dmode_r; // @[dec_tlu_ctl.scala 540:55] + wire mepc_trigger_hit_sel_pc_r = i0_trigger_hit_raw_r & _T_345; // @[dec_tlu_ctl.scala 540:53] + wire _T_350 = i_cpu_run_req_sync & _T_346; // @[dec_tlu_ctl.scala 568:58] + wire _T_351 = _T_350 & pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 568:83] + wire i_cpu_run_req_sync_qual = _T_351 & _T_107; // @[dec_tlu_ctl.scala 568:105] + reg _T_353; // @[dec_tlu_ctl.scala 572:81] + reg _T_354; // @[dec_tlu_ctl.scala 573:81] + reg _T_355; // @[dec_tlu_ctl.scala 574:81] + wire _T_384 = io_o_cpu_halt_status & _T_375; // @[dec_tlu_ctl.scala 592:89] + wire _T_386 = _T_384 & _T_152; // @[dec_tlu_ctl.scala 592:109] + wire _T_388 = io_o_cpu_halt_status & i_cpu_run_req_sync_qual; // @[dec_tlu_ctl.scala 593:41] + wire _T_389 = io_o_cpu_run_ack & i_cpu_run_req_sync_qual; // @[dec_tlu_ctl.scala 593:88] + reg lsu_single_ecc_error_r_d1; // @[dec_tlu_ctl.scala 605:72] + reg lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 612:73] + wire _T_408 = ~io_lsu_error_pkt_r_bits_exc_type; // @[dec_tlu_ctl.scala 613:40] + wire lsu_exc_ma_r = lsu_exc_valid_r & _T_408; // @[dec_tlu_ctl.scala 613:38] + wire lsu_exc_acc_r = lsu_exc_valid_r & io_lsu_error_pkt_r_bits_exc_type; // @[dec_tlu_ctl.scala 614:38] + wire lsu_exc_st_r = lsu_exc_valid_r & io_lsu_error_pkt_r_bits_inst_type; // @[dec_tlu_ctl.scala 615:38] + wire _T_424 = rfpc_i0_r | lsu_exc_valid_r; // @[dec_tlu_ctl.scala 625:38] + wire _T_425 = _T_424 | inst_acc_r; // @[dec_tlu_ctl.scala 625:53] + wire _T_426 = illegal_r & io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 625:79] + wire _T_427 = _T_425 | _T_426; // @[dec_tlu_ctl.scala 625:66] + wire _T_441 = ~io_tlu_exu_dec_tlu_flush_lower_r; // @[dec_tlu_ctl.scala 634:70] + wire _T_442 = iccm_repair_state_d1 & _T_441; // @[dec_tlu_ctl.scala 634:68] + wire _T_453 = io_tlu_exu_exu_i0_br_error_r & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 643:59] + wire _T_455 = io_tlu_exu_exu_i0_br_start_error_r & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 644:71] + wire _T_457 = io_tlu_exu_exu_i0_br_valid_r & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 645:55] + wire _T_459 = _T_457 & _T_429; // @[dec_tlu_ctl.scala 645:79] + wire _T_460 = ~io_tlu_exu_exu_i0_br_mp_r; // @[dec_tlu_ctl.scala 645:106] + wire _T_461 = ~io_tlu_exu_exu_pmu_i0_br_ataken; // @[dec_tlu_ctl.scala 645:135] + wire _T_462 = _T_460 | _T_461; // @[dec_tlu_ctl.scala 645:133] + wire _T_529 = ~take_nmi; // @[dec_tlu_ctl.scala 693:33] + wire _T_530 = take_ext_int & _T_529; // @[dec_tlu_ctl.scala 693:31] + wire _T_533 = take_timer_int & _T_529; // @[dec_tlu_ctl.scala 694:25] + wire _T_536 = take_soft_int & _T_529; // @[dec_tlu_ctl.scala 695:24] + wire _T_539 = take_int_timer0_int & _T_529; // @[dec_tlu_ctl.scala 696:30] + wire _T_542 = take_int_timer1_int & _T_529; // @[dec_tlu_ctl.scala 697:30] + wire _T_545 = take_ce_int & _T_529; // @[dec_tlu_ctl.scala 698:22] + wire _T_548 = illegal_r & _T_529; // @[dec_tlu_ctl.scala 699:20] + wire _T_551 = ecall_r & _T_529; // @[dec_tlu_ctl.scala 700:19] + wire _T_554 = inst_acc_r & _T_529; // @[dec_tlu_ctl.scala 701:22] + wire _T_556 = ebreak_r | i0_trigger_hit_raw_r; // @[dec_tlu_ctl.scala 702:20] + wire _T_558 = _T_556 & _T_529; // @[dec_tlu_ctl.scala 702:40] + wire _T_560 = ~lsu_exc_st_r; // @[dec_tlu_ctl.scala 703:25] + wire _T_561 = lsu_exc_ma_r & _T_560; // @[dec_tlu_ctl.scala 703:23] + wire _T_563 = _T_561 & _T_529; // @[dec_tlu_ctl.scala 703:39] + wire _T_566 = lsu_exc_acc_r & _T_560; // @[dec_tlu_ctl.scala 704:24] + wire _T_568 = _T_566 & _T_529; // @[dec_tlu_ctl.scala 704:40] + wire _T_570 = lsu_exc_ma_r & lsu_exc_st_r; // @[dec_tlu_ctl.scala 705:23] + wire _T_572 = _T_570 & _T_529; // @[dec_tlu_ctl.scala 705:38] + wire _T_574 = lsu_exc_acc_r & lsu_exc_st_r; // @[dec_tlu_ctl.scala 706:24] + wire _T_576 = _T_574 & _T_529; // @[dec_tlu_ctl.scala 706:39] wire [4:0] _T_578 = _T_530 ? 5'hb : 5'h0; // @[Mux.scala 27:72] wire [4:0] _T_579 = _T_533 ? 5'h7 : 5'h0; // @[Mux.scala 27:72] wire [4:0] _T_580 = _T_536 ? 5'h3 : 5'h0; // @[Mux.scala 27:72] @@ -55460,66 +55471,66 @@ module dec_tlu_ctl( wire [4:0] _T_602 = _T_601 | _T_589; // @[Mux.scala 27:72] wire [4:0] _T_603 = _T_602 | _T_590; // @[Mux.scala 27:72] wire [4:0] exc_cause_r = _T_603 | _T_591; // @[Mux.scala 27:72] - wire _T_641 = io_dec_csr_stall_int_ff | synchronous_flush_r; // @[dec_tlu_ctl.scala 733:52] - wire _T_642 = _T_641 | exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 733:74] - wire int_timer_stalled = _T_642 | mret_r; // @[dec_tlu_ctl.scala 733:98] - wire _T_643 = pmu_fw_tlu_halted_f | int_timer_stalled; // @[dec_tlu_ctl.scala 735:72] - wire _T_644 = int_timer0_int_ready & _T_643; // @[dec_tlu_ctl.scala 735:49] - wire _T_645 = int_timer0_int_possible & int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 735:121] - wire _T_647 = _T_645 & _T_207; // @[dec_tlu_ctl.scala 735:145] - wire _T_649 = _T_647 & _T_209; // @[dec_tlu_ctl.scala 735:166] - wire _T_651 = _T_649 & _T_152; // @[dec_tlu_ctl.scala 735:188] - wire _T_654 = int_timer1_int_ready & _T_643; // @[dec_tlu_ctl.scala 736:49] - wire _T_655 = int_timer1_int_possible & int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 736:121] - wire _T_657 = _T_655 & _T_207; // @[dec_tlu_ctl.scala 736:145] - wire _T_659 = _T_657 & _T_209; // @[dec_tlu_ctl.scala 736:166] - wire _T_661 = _T_659 & _T_152; // @[dec_tlu_ctl.scala 736:188] - reg take_ext_int_start_d2; // @[dec_tlu_ctl.scala 745:62] - wire _T_681 = take_ext_int_start | take_ext_int_start_d1; // @[dec_tlu_ctl.scala 750:46] - wire _T_682 = _T_681 | take_ext_int_start_d2; // @[dec_tlu_ctl.scala 750:70] - wire csr_pkt_csr_meicpct = csr_read_io_csr_pkt_csr_meicpct; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1013:16] - wire fast_int_meicpct = csr_pkt_csr_meicpct & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 752:49] - wire [30:0] mtvec = csr_io_mtvec; // @[dec_tlu_ctl.scala 1008:31] + wire _T_641 = io_dec_csr_stall_int_ff | synchronous_flush_r; // @[dec_tlu_ctl.scala 731:52] + wire _T_642 = _T_641 | exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 731:74] + wire int_timer_stalled = _T_642 | mret_r; // @[dec_tlu_ctl.scala 731:98] + wire _T_643 = pmu_fw_tlu_halted_f | int_timer_stalled; // @[dec_tlu_ctl.scala 733:72] + wire _T_644 = int_timer0_int_ready & _T_643; // @[dec_tlu_ctl.scala 733:49] + wire _T_645 = int_timer0_int_possible & int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 733:121] + wire _T_647 = _T_645 & _T_207; // @[dec_tlu_ctl.scala 733:145] + wire _T_649 = _T_647 & _T_209; // @[dec_tlu_ctl.scala 733:166] + wire _T_651 = _T_649 & _T_152; // @[dec_tlu_ctl.scala 733:188] + wire _T_654 = int_timer1_int_ready & _T_643; // @[dec_tlu_ctl.scala 734:49] + wire _T_655 = int_timer1_int_possible & int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 734:121] + wire _T_657 = _T_655 & _T_207; // @[dec_tlu_ctl.scala 734:145] + wire _T_659 = _T_657 & _T_209; // @[dec_tlu_ctl.scala 734:166] + wire _T_661 = _T_659 & _T_152; // @[dec_tlu_ctl.scala 734:188] + reg take_ext_int_start_d2; // @[dec_tlu_ctl.scala 743:62] + wire _T_681 = take_ext_int_start | take_ext_int_start_d1; // @[dec_tlu_ctl.scala 748:46] + wire _T_682 = _T_681 | take_ext_int_start_d2; // @[dec_tlu_ctl.scala 748:70] + wire csr_pkt_csr_meicpct = csr_read_io_csr_pkt_csr_meicpct; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1011:16] + wire fast_int_meicpct = csr_pkt_csr_meicpct & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 750:49] + wire [30:0] mtvec = csr_io_mtvec; // @[dec_tlu_ctl.scala 1006:31] wire [30:0] _T_769 = {mtvec[30:1],1'h0}; // @[Cat.scala 29:58] wire [30:0] _T_771 = {25'h0,exc_cause_r,1'h0}; // @[Cat.scala 29:58] - wire [30:0] vectored_path = _T_769 + _T_771; // @[dec_tlu_ctl.scala 780:51] - wire [30:0] _T_778 = mtvec[0] ? vectored_path : _T_769; // @[dec_tlu_ctl.scala 781:61] - wire [30:0] interrupt_path = take_nmi ? io_nmi_vec : _T_778; // @[dec_tlu_ctl.scala 781:28] - wire _T_779 = lsu_i0_rfnpc_r | fence_i_r; // @[dec_tlu_ctl.scala 782:36] - wire _T_780 = _T_779 | iccm_repair_state_rfnpc; // @[dec_tlu_ctl.scala 782:48] - wire _T_782 = i_cpu_run_req_d1 & _T_207; // @[dec_tlu_ctl.scala 782:94] - wire _T_783 = _T_780 | _T_782; // @[dec_tlu_ctl.scala 782:74] - wire _T_785 = rfpc_i0_r & _T_743; // @[dec_tlu_ctl.scala 782:129] - wire sel_npc_r = _T_783 | _T_785; // @[dec_tlu_ctl.scala 782:116] - wire _T_798 = interrupt_valid_r | mret_r; // @[dec_tlu_ctl.scala 786:43] - wire _T_799 = _T_798 | synchronous_flush_r; // @[dec_tlu_ctl.scala 786:52] - wire _T_800 = _T_799 | take_halt; // @[dec_tlu_ctl.scala 786:74] - wire _T_801 = _T_800 | take_reset; // @[dec_tlu_ctl.scala 786:86] - wire _T_807 = _T_529 & sel_npc_r; // @[dec_tlu_ctl.scala 790:73] - wire _T_810 = _T_529 & rfpc_i0_r; // @[dec_tlu_ctl.scala 791:73] - wire _T_812 = _T_810 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 791:91] - wire _T_813 = ~sel_npc_r; // @[dec_tlu_ctl.scala 791:132] - wire _T_814 = _T_812 & _T_813; // @[dec_tlu_ctl.scala 791:121] - wire _T_816 = ~take_ext_int; // @[dec_tlu_ctl.scala 792:96] - wire _T_817 = interrupt_valid_r & _T_816; // @[dec_tlu_ctl.scala 792:82] - wire _T_818 = i0_exception_valid_r | lsu_exc_valid_r; // @[dec_tlu_ctl.scala 793:80] - wire _T_821 = _T_818 | mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 793:98] - wire _T_823 = _T_821 & _T_207; // @[dec_tlu_ctl.scala 793:143] - wire _T_825 = _T_823 & _T_816; // @[dec_tlu_ctl.scala 793:164] - wire _T_830 = _T_529 & mret_r; // @[dec_tlu_ctl.scala 794:68] - wire _T_833 = _T_529 & debug_resume_req_f; // @[dec_tlu_ctl.scala 795:68] - wire _T_836 = _T_529 & sel_npc_resume; // @[dec_tlu_ctl.scala 796:68] + wire [30:0] vectored_path = _T_769 + _T_771; // @[dec_tlu_ctl.scala 778:51] + wire [30:0] _T_778 = mtvec[0] ? vectored_path : _T_769; // @[dec_tlu_ctl.scala 779:61] + wire [30:0] interrupt_path = take_nmi ? io_nmi_vec : _T_778; // @[dec_tlu_ctl.scala 779:28] + wire _T_779 = lsu_i0_rfnpc_r | fence_i_r; // @[dec_tlu_ctl.scala 780:36] + wire _T_780 = _T_779 | iccm_repair_state_rfnpc; // @[dec_tlu_ctl.scala 780:48] + wire _T_782 = i_cpu_run_req_d1 & _T_207; // @[dec_tlu_ctl.scala 780:94] + wire _T_783 = _T_780 | _T_782; // @[dec_tlu_ctl.scala 780:74] + wire _T_785 = rfpc_i0_r & _T_743; // @[dec_tlu_ctl.scala 780:129] + wire sel_npc_r = _T_783 | _T_785; // @[dec_tlu_ctl.scala 780:116] + wire _T_798 = interrupt_valid_r | mret_r; // @[dec_tlu_ctl.scala 784:43] + wire _T_799 = _T_798 | synchronous_flush_r; // @[dec_tlu_ctl.scala 784:52] + wire _T_800 = _T_799 | take_halt; // @[dec_tlu_ctl.scala 784:74] + wire _T_801 = _T_800 | take_reset; // @[dec_tlu_ctl.scala 784:86] + wire _T_807 = _T_529 & sel_npc_r; // @[dec_tlu_ctl.scala 788:73] + wire _T_810 = _T_529 & rfpc_i0_r; // @[dec_tlu_ctl.scala 789:73] + wire _T_812 = _T_810 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 789:91] + wire _T_813 = ~sel_npc_r; // @[dec_tlu_ctl.scala 789:132] + wire _T_814 = _T_812 & _T_813; // @[dec_tlu_ctl.scala 789:121] + wire _T_816 = ~take_ext_int; // @[dec_tlu_ctl.scala 790:96] + wire _T_817 = interrupt_valid_r & _T_816; // @[dec_tlu_ctl.scala 790:82] + wire _T_818 = i0_exception_valid_r | lsu_exc_valid_r; // @[dec_tlu_ctl.scala 791:80] + wire _T_821 = _T_818 | mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 791:98] + wire _T_823 = _T_821 & _T_207; // @[dec_tlu_ctl.scala 791:143] + wire _T_825 = _T_823 & _T_816; // @[dec_tlu_ctl.scala 791:164] + wire _T_830 = _T_529 & mret_r; // @[dec_tlu_ctl.scala 792:68] + wire _T_833 = _T_529 & debug_resume_req_f; // @[dec_tlu_ctl.scala 793:68] + wire _T_836 = _T_529 & sel_npc_resume; // @[dec_tlu_ctl.scala 794:68] wire [30:0] _T_838 = take_ext_int ? io_lsu_fir_addr : 31'h0; // @[Mux.scala 27:72] - wire [30:0] npc_r = csr_io_npc_r; // @[dec_tlu_ctl.scala 996:31] + wire [30:0] npc_r = csr_io_npc_r; // @[dec_tlu_ctl.scala 994:31] wire [30:0] _T_839 = _T_807 ? npc_r : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_840 = _T_814 ? io_dec_tlu_i0_pc_r : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_841 = _T_817 ? interrupt_path : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_842 = _T_825 ? _T_769 : 31'h0; // @[Mux.scala 27:72] - wire [30:0] mepc = csr_io_mepc; // @[dec_tlu_ctl.scala 999:31] + wire [30:0] mepc = csr_io_mepc; // @[dec_tlu_ctl.scala 997:31] wire [30:0] _T_843 = _T_830 ? mepc : 31'h0; // @[Mux.scala 27:72] - wire [30:0] dpc = csr_io_dpc; // @[dec_tlu_ctl.scala 1002:31] + wire [30:0] dpc = csr_io_dpc; // @[dec_tlu_ctl.scala 1000:31] wire [30:0] _T_844 = _T_833 ? dpc : 31'h0; // @[Mux.scala 27:72] - wire [30:0] npc_r_d1 = csr_io_npc_r_d1; // @[dec_tlu_ctl.scala 997:31] + wire [30:0] npc_r_d1 = csr_io_npc_r_d1; // @[dec_tlu_ctl.scala 995:31] wire [30:0] _T_845 = _T_836 ? npc_r_d1 : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_846 = _T_838 | _T_839; // @[Mux.scala 27:72] wire [30:0] _T_847 = _T_846 | _T_840; // @[Mux.scala 27:72] @@ -55528,53 +55539,53 @@ module dec_tlu_ctl( wire [30:0] _T_850 = _T_849 | _T_843; // @[Mux.scala 27:72] wire [30:0] _T_851 = _T_850 | _T_844; // @[Mux.scala 27:72] wire [30:0] _T_852 = _T_851 | _T_845; // @[Mux.scala 27:72] - reg [30:0] tlu_flush_path_r_d1; // @[dec_tlu_ctl.scala 799:64] - wire _T_854 = lsu_exc_valid_r | i0_exception_valid_r; // @[dec_tlu_ctl.scala 807:45] - wire _T_855 = _T_854 | interrupt_valid_r; // @[dec_tlu_ctl.scala 807:68] - reg i0_exception_valid_r_d1; // @[dec_tlu_ctl.scala 810:89] - reg [4:0] exc_cause_wb; // @[dec_tlu_ctl.scala 812:89] - wire _T_860 = ~illegal_r; // @[dec_tlu_ctl.scala 813:119] - reg i0_valid_wb; // @[dec_tlu_ctl.scala 813:97] - reg trigger_hit_r_d1; // @[dec_tlu_ctl.scala 814:89] - wire csr_pkt_presync = csr_read_io_csr_pkt_presync; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1013:16] - wire _T_864 = csr_pkt_presync & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 1015:42] - wire _T_865 = ~io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 1015:67] - wire csr_pkt_postsync = csr_read_io_csr_pkt_postsync; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1013:16] - wire csr_pkt_csr_dcsr = csr_read_io_csr_pkt_csr_dcsr; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1013:16] - wire csr_pkt_csr_dpc = csr_read_io_csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1013:16] - wire _T_874 = csr_pkt_csr_dcsr | csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 1020:55] - wire csr_pkt_csr_dmst = csr_read_io_csr_pkt_csr_dmst; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1013:16] - wire _T_875 = _T_874 | csr_pkt_csr_dmst; // @[dec_tlu_ctl.scala 1020:73] - wire csr_pkt_csr_dicawics = csr_read_io_csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1013:16] - wire _T_876 = _T_875 | csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 1020:92] - wire csr_pkt_csr_dicad0 = csr_read_io_csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1013:16] - wire _T_877 = _T_876 | csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 1020:115] - wire csr_pkt_csr_dicad0h = csr_read_io_csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1013:16] - wire _T_878 = _T_877 | csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 1020:136] - wire csr_pkt_csr_dicad1 = csr_read_io_csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1013:16] - wire _T_879 = _T_878 | csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 1020:158] - wire csr_pkt_csr_dicago = csr_read_io_csr_pkt_csr_dicago; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1013:16] - wire _T_880 = _T_879 | csr_pkt_csr_dicago; // @[dec_tlu_ctl.scala 1020:179] - wire _T_881 = ~_T_880; // @[dec_tlu_ctl.scala 1020:36] - wire _T_882 = _T_881 | dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 1020:201] - wire csr_pkt_legal = csr_read_io_csr_pkt_legal; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1013:16] - wire _T_883 = csr_pkt_legal & _T_882; // @[dec_tlu_ctl.scala 1020:33] - wire _T_884 = ~fast_int_meicpct; // @[dec_tlu_ctl.scala 1020:223] - wire valid_csr = _T_883 & _T_884; // @[dec_tlu_ctl.scala 1020:221] - wire _T_887 = io_dec_csr_any_unq_d & valid_csr; // @[dec_tlu_ctl.scala 1022:46] - wire csr_pkt_csr_mvendorid = csr_read_io_csr_pkt_csr_mvendorid; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1013:16] - wire csr_pkt_csr_marchid = csr_read_io_csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1013:16] - wire _T_888 = csr_pkt_csr_mvendorid | csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 1022:107] - wire csr_pkt_csr_mimpid = csr_read_io_csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1013:16] - wire _T_889 = _T_888 | csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 1022:129] - wire csr_pkt_csr_mhartid = csr_read_io_csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1013:16] - wire _T_890 = _T_889 | csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 1022:150] - wire csr_pkt_csr_mdseac = csr_read_io_csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1013:16] - wire _T_891 = _T_890 | csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 1022:172] - wire csr_pkt_csr_meihap = csr_read_io_csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1013:16] - wire _T_892 = _T_891 | csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 1022:193] - wire _T_893 = io_dec_csr_wen_unq_d & _T_892; // @[dec_tlu_ctl.scala 1022:82] - wire _T_894 = ~_T_893; // @[dec_tlu_ctl.scala 1022:59] + reg [30:0] tlu_flush_path_r_d1; // @[dec_tlu_ctl.scala 797:64] + wire _T_854 = lsu_exc_valid_r | i0_exception_valid_r; // @[dec_tlu_ctl.scala 805:45] + wire _T_855 = _T_854 | interrupt_valid_r; // @[dec_tlu_ctl.scala 805:68] + reg i0_exception_valid_r_d1; // @[dec_tlu_ctl.scala 808:89] + reg [4:0] exc_cause_wb; // @[dec_tlu_ctl.scala 810:89] + wire _T_860 = ~illegal_r; // @[dec_tlu_ctl.scala 811:119] + reg i0_valid_wb; // @[dec_tlu_ctl.scala 811:97] + reg trigger_hit_r_d1; // @[dec_tlu_ctl.scala 812:89] + wire csr_pkt_presync = csr_read_io_csr_pkt_presync; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1011:16] + wire _T_864 = csr_pkt_presync & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 1013:42] + wire _T_865 = ~io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 1013:67] + wire csr_pkt_postsync = csr_read_io_csr_pkt_postsync; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1011:16] + wire csr_pkt_csr_dcsr = csr_read_io_csr_pkt_csr_dcsr; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1011:16] + wire csr_pkt_csr_dpc = csr_read_io_csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1011:16] + wire _T_874 = csr_pkt_csr_dcsr | csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 1018:55] + wire csr_pkt_csr_dmst = csr_read_io_csr_pkt_csr_dmst; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1011:16] + wire _T_875 = _T_874 | csr_pkt_csr_dmst; // @[dec_tlu_ctl.scala 1018:73] + wire csr_pkt_csr_dicawics = csr_read_io_csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1011:16] + wire _T_876 = _T_875 | csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 1018:92] + wire csr_pkt_csr_dicad0 = csr_read_io_csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1011:16] + wire _T_877 = _T_876 | csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 1018:115] + wire csr_pkt_csr_dicad0h = csr_read_io_csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1011:16] + wire _T_878 = _T_877 | csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 1018:136] + wire csr_pkt_csr_dicad1 = csr_read_io_csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1011:16] + wire _T_879 = _T_878 | csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 1018:158] + wire csr_pkt_csr_dicago = csr_read_io_csr_pkt_csr_dicago; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1011:16] + wire _T_880 = _T_879 | csr_pkt_csr_dicago; // @[dec_tlu_ctl.scala 1018:179] + wire _T_881 = ~_T_880; // @[dec_tlu_ctl.scala 1018:36] + wire _T_882 = _T_881 | dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 1018:201] + wire csr_pkt_legal = csr_read_io_csr_pkt_legal; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1011:16] + wire _T_883 = csr_pkt_legal & _T_882; // @[dec_tlu_ctl.scala 1018:33] + wire _T_884 = ~fast_int_meicpct; // @[dec_tlu_ctl.scala 1018:223] + wire valid_csr = _T_883 & _T_884; // @[dec_tlu_ctl.scala 1018:221] + wire _T_887 = io_dec_csr_any_unq_d & valid_csr; // @[dec_tlu_ctl.scala 1020:46] + wire csr_pkt_csr_mvendorid = csr_read_io_csr_pkt_csr_mvendorid; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1011:16] + wire csr_pkt_csr_marchid = csr_read_io_csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1011:16] + wire _T_888 = csr_pkt_csr_mvendorid | csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 1020:107] + wire csr_pkt_csr_mimpid = csr_read_io_csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1011:16] + wire _T_889 = _T_888 | csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 1020:129] + wire csr_pkt_csr_mhartid = csr_read_io_csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1011:16] + wire _T_890 = _T_889 | csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 1020:150] + wire csr_pkt_csr_mdseac = csr_read_io_csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1011:16] + wire _T_891 = _T_890 | csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 1020:172] + wire csr_pkt_csr_meihap = csr_read_io_csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1011:16] + wire _T_892 = _T_891 | csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 1020:193] + wire _T_893 = io_dec_csr_wen_unq_d & _T_892; // @[dec_tlu_ctl.scala 1020:82] + wire _T_894 = ~_T_893; // @[dec_tlu_ctl.scala 1020:59] dec_timer_ctl int_timers ( // @[dec_tlu_ctl.scala 275:30] .clock(int_timers_clock), .reset(int_timers_reset), @@ -55621,7 +55632,7 @@ module dec_tlu_ctl( .io_en(rvclkhdr_3_io_en), .io_scan_mode(rvclkhdr_3_io_scan_mode) ); - csr_tlu csr ( // @[dec_tlu_ctl.scala 818:15] + csr_tlu csr ( // @[dec_tlu_ctl.scala 816:15] .clock(csr_clock), .reset(csr_reset), .io_free_clk(csr_io_free_clk), @@ -55707,7 +55718,6 @@ module dec_tlu_ctl( .io_dec_tlu_misc_clk_override(csr_io_dec_tlu_misc_clk_override), .io_dec_tlu_dec_clk_override(csr_io_dec_tlu_dec_clk_override), .io_dec_tlu_lsu_clk_override(csr_io_dec_tlu_lsu_clk_override), - .io_dec_tlu_bus_clk_override(csr_io_dec_tlu_bus_clk_override), .io_dec_tlu_pic_clk_override(csr_io_dec_tlu_pic_clk_override), .io_dec_tlu_dccm_clk_override(csr_io_dec_tlu_dccm_clk_override), .io_dec_tlu_icm_clk_override(csr_io_dec_tlu_icm_clk_override), @@ -55730,6 +55740,7 @@ module dec_tlu_ctl( .io_lsu_imprecise_error_load_any(csr_io_lsu_imprecise_error_load_any), .io_lsu_imprecise_error_store_any(csr_io_lsu_imprecise_error_store_any), .io_dec_tlu_mrac_ff(csr_io_dec_tlu_mrac_ff), + .io_dec_tlu_wb_coalescing_disable(csr_io_dec_tlu_wb_coalescing_disable), .io_dec_tlu_bpred_disable(csr_io_dec_tlu_bpred_disable), .io_dec_tlu_sideeffect_posted_disable(csr_io_dec_tlu_sideeffect_posted_disable), .io_dec_tlu_core_ecc_disable(csr_io_dec_tlu_core_ecc_disable), @@ -55893,7 +55904,7 @@ module dec_tlu_ctl( .io_mtdata1_t_2(csr_io_mtdata1_t_2), .io_mtdata1_t_3(csr_io_mtdata1_t_3) ); - dec_decode_csr_read csr_read ( // @[dec_tlu_ctl.scala 1011:22] + dec_decode_csr_read csr_read ( // @[dec_tlu_ctl.scala 1009:22] .io_dec_csr_rdaddr_d(csr_read_io_dec_csr_rdaddr_d), .io_csr_pkt_csr_misa(csr_read_io_csr_pkt_csr_misa), .io_csr_pkt_csr_mvendorid(csr_read_io_csr_pkt_csr_mvendorid), @@ -55963,102 +55974,102 @@ module dec_tlu_ctl( .io_csr_pkt_postsync(csr_read_io_csr_pkt_postsync), .io_csr_pkt_legal(csr_read_io_csr_pkt_legal) ); - assign io_tlu_exu_dec_tlu_meihap = csr_io_dec_tlu_meihap; // @[dec_tlu_ctl.scala 877:52] - assign io_tlu_exu_dec_tlu_flush_lower_r = _T_801 | take_ext_int_start; // @[dec_tlu_ctl.scala 803:49] - assign io_tlu_exu_dec_tlu_flush_path_r = take_reset ? io_rst_vec : _T_852; // @[dec_tlu_ctl.scala 804:49] - assign io_tlu_dma_dec_tlu_dma_qos_prty = csr_io_dec_tlu_dma_qos_prty; // @[dec_tlu_ctl.scala 907:48] - assign io_dec_dbg_cmd_done = io_dec_tlu_i0_valid_r & io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 488:29] - assign io_dec_dbg_cmd_fail = illegal_r & io_dec_dbg_cmd_done; // @[dec_tlu_ctl.scala 489:29] - assign io_dec_tlu_dbg_halted = dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 470:41] - assign io_dec_tlu_debug_mode = debug_mode_status; // @[dec_tlu_ctl.scala 471:41] - assign io_dec_tlu_resume_ack = _T_190; // @[dec_tlu_ctl.scala 454:49] - assign io_dec_tlu_debug_stall = debug_halt_req_f; // @[dec_tlu_ctl.scala 469:41] - assign io_dec_tlu_mpc_halted_only = _T_65; // @[dec_tlu_ctl.scala 369:49] - assign io_dec_tlu_flush_extint = ext_int_ready & _T_704; // @[dec_tlu_ctl.scala 477:33] - assign io_trigger_pkt_any_0_select = csr_io_trigger_pkt_any_0_select; // @[dec_tlu_ctl.scala 883:40] - assign io_trigger_pkt_any_0_match_pkt = csr_io_trigger_pkt_any_0_match_pkt; // @[dec_tlu_ctl.scala 883:40] - assign io_trigger_pkt_any_0_store = csr_io_trigger_pkt_any_0_store; // @[dec_tlu_ctl.scala 883:40] - assign io_trigger_pkt_any_0_load = csr_io_trigger_pkt_any_0_load; // @[dec_tlu_ctl.scala 883:40] - assign io_trigger_pkt_any_0_execute = csr_io_trigger_pkt_any_0_execute; // @[dec_tlu_ctl.scala 883:40] - assign io_trigger_pkt_any_0_m = csr_io_trigger_pkt_any_0_m; // @[dec_tlu_ctl.scala 883:40] - assign io_trigger_pkt_any_0_tdata2 = csr_io_trigger_pkt_any_0_tdata2; // @[dec_tlu_ctl.scala 883:40] - assign io_trigger_pkt_any_1_select = csr_io_trigger_pkt_any_1_select; // @[dec_tlu_ctl.scala 883:40] - assign io_trigger_pkt_any_1_match_pkt = csr_io_trigger_pkt_any_1_match_pkt; // @[dec_tlu_ctl.scala 883:40] - assign io_trigger_pkt_any_1_store = csr_io_trigger_pkt_any_1_store; // @[dec_tlu_ctl.scala 883:40] - assign io_trigger_pkt_any_1_load = csr_io_trigger_pkt_any_1_load; // @[dec_tlu_ctl.scala 883:40] - assign io_trigger_pkt_any_1_execute = csr_io_trigger_pkt_any_1_execute; // @[dec_tlu_ctl.scala 883:40] - assign io_trigger_pkt_any_1_m = csr_io_trigger_pkt_any_1_m; // @[dec_tlu_ctl.scala 883:40] - assign io_trigger_pkt_any_1_tdata2 = csr_io_trigger_pkt_any_1_tdata2; // @[dec_tlu_ctl.scala 883:40] - assign io_trigger_pkt_any_2_select = csr_io_trigger_pkt_any_2_select; // @[dec_tlu_ctl.scala 883:40] - assign io_trigger_pkt_any_2_match_pkt = csr_io_trigger_pkt_any_2_match_pkt; // @[dec_tlu_ctl.scala 883:40] - assign io_trigger_pkt_any_2_store = csr_io_trigger_pkt_any_2_store; // @[dec_tlu_ctl.scala 883:40] - assign io_trigger_pkt_any_2_load = csr_io_trigger_pkt_any_2_load; // @[dec_tlu_ctl.scala 883:40] - assign io_trigger_pkt_any_2_execute = csr_io_trigger_pkt_any_2_execute; // @[dec_tlu_ctl.scala 883:40] - assign io_trigger_pkt_any_2_m = csr_io_trigger_pkt_any_2_m; // @[dec_tlu_ctl.scala 883:40] - assign io_trigger_pkt_any_2_tdata2 = csr_io_trigger_pkt_any_2_tdata2; // @[dec_tlu_ctl.scala 883:40] - assign io_trigger_pkt_any_3_select = csr_io_trigger_pkt_any_3_select; // @[dec_tlu_ctl.scala 883:40] - assign io_trigger_pkt_any_3_match_pkt = csr_io_trigger_pkt_any_3_match_pkt; // @[dec_tlu_ctl.scala 883:40] - assign io_trigger_pkt_any_3_store = csr_io_trigger_pkt_any_3_store; // @[dec_tlu_ctl.scala 883:40] - assign io_trigger_pkt_any_3_load = csr_io_trigger_pkt_any_3_load; // @[dec_tlu_ctl.scala 883:40] - assign io_trigger_pkt_any_3_execute = csr_io_trigger_pkt_any_3_execute; // @[dec_tlu_ctl.scala 883:40] - assign io_trigger_pkt_any_3_m = csr_io_trigger_pkt_any_3_m; // @[dec_tlu_ctl.scala 883:40] - assign io_trigger_pkt_any_3_tdata2 = csr_io_trigger_pkt_any_3_tdata2; // @[dec_tlu_ctl.scala 883:40] - assign io_o_cpu_halt_status = _T_353; // @[dec_tlu_ctl.scala 574:49] - assign io_o_cpu_halt_ack = _T_354; // @[dec_tlu_ctl.scala 575:49] - assign io_o_cpu_run_ack = _T_355; // @[dec_tlu_ctl.scala 576:49] - assign io_o_debug_mode_status = debug_mode_status; // @[dec_tlu_ctl.scala 597:27] - assign io_mpc_debug_halt_ack = mpc_debug_halt_ack_f; // @[dec_tlu_ctl.scala 394:31] - assign io_mpc_debug_run_ack = mpc_debug_run_ack_f; // @[dec_tlu_ctl.scala 395:31] - assign io_debug_brkpt_status = debug_brkpt_status_f; // @[dec_tlu_ctl.scala 396:31] - assign io_dec_csr_rddata_d = csr_io_dec_csr_rddata_d; // @[dec_tlu_ctl.scala 898:40] - assign io_dec_csr_legal_d = _T_887 & _T_894; // @[dec_tlu_ctl.scala 1022:20] + assign io_tlu_exu_dec_tlu_meihap = csr_io_dec_tlu_meihap; // @[dec_tlu_ctl.scala 875:52] + assign io_tlu_exu_dec_tlu_flush_lower_r = _T_801 | take_ext_int_start; // @[dec_tlu_ctl.scala 801:49] + assign io_tlu_exu_dec_tlu_flush_path_r = take_reset ? io_rst_vec : _T_852; // @[dec_tlu_ctl.scala 802:49] + assign io_tlu_dma_dec_tlu_dma_qos_prty = csr_io_dec_tlu_dma_qos_prty; // @[dec_tlu_ctl.scala 905:48] + assign io_dec_dbg_cmd_done = io_dec_tlu_i0_valid_r & io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 486:29] + assign io_dec_dbg_cmd_fail = illegal_r & io_dec_dbg_cmd_done; // @[dec_tlu_ctl.scala 487:29] + assign io_dec_tlu_dbg_halted = dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 468:41] + assign io_dec_tlu_debug_mode = debug_mode_status; // @[dec_tlu_ctl.scala 469:41] + assign io_dec_tlu_resume_ack = _T_190; // @[dec_tlu_ctl.scala 452:49] + assign io_dec_tlu_debug_stall = debug_halt_req_f; // @[dec_tlu_ctl.scala 467:41] + assign io_dec_tlu_mpc_halted_only = _T_65; // @[dec_tlu_ctl.scala 367:49] + assign io_dec_tlu_flush_extint = ext_int_ready & _T_704; // @[dec_tlu_ctl.scala 475:33] + assign io_trigger_pkt_any_0_select = csr_io_trigger_pkt_any_0_select; // @[dec_tlu_ctl.scala 881:40] + assign io_trigger_pkt_any_0_match_pkt = csr_io_trigger_pkt_any_0_match_pkt; // @[dec_tlu_ctl.scala 881:40] + assign io_trigger_pkt_any_0_store = csr_io_trigger_pkt_any_0_store; // @[dec_tlu_ctl.scala 881:40] + assign io_trigger_pkt_any_0_load = csr_io_trigger_pkt_any_0_load; // @[dec_tlu_ctl.scala 881:40] + assign io_trigger_pkt_any_0_execute = csr_io_trigger_pkt_any_0_execute; // @[dec_tlu_ctl.scala 881:40] + assign io_trigger_pkt_any_0_m = csr_io_trigger_pkt_any_0_m; // @[dec_tlu_ctl.scala 881:40] + assign io_trigger_pkt_any_0_tdata2 = csr_io_trigger_pkt_any_0_tdata2; // @[dec_tlu_ctl.scala 881:40] + assign io_trigger_pkt_any_1_select = csr_io_trigger_pkt_any_1_select; // @[dec_tlu_ctl.scala 881:40] + assign io_trigger_pkt_any_1_match_pkt = csr_io_trigger_pkt_any_1_match_pkt; // @[dec_tlu_ctl.scala 881:40] + assign io_trigger_pkt_any_1_store = csr_io_trigger_pkt_any_1_store; // @[dec_tlu_ctl.scala 881:40] + assign io_trigger_pkt_any_1_load = csr_io_trigger_pkt_any_1_load; // @[dec_tlu_ctl.scala 881:40] + assign io_trigger_pkt_any_1_execute = csr_io_trigger_pkt_any_1_execute; // @[dec_tlu_ctl.scala 881:40] + assign io_trigger_pkt_any_1_m = csr_io_trigger_pkt_any_1_m; // @[dec_tlu_ctl.scala 881:40] + assign io_trigger_pkt_any_1_tdata2 = csr_io_trigger_pkt_any_1_tdata2; // @[dec_tlu_ctl.scala 881:40] + assign io_trigger_pkt_any_2_select = csr_io_trigger_pkt_any_2_select; // @[dec_tlu_ctl.scala 881:40] + assign io_trigger_pkt_any_2_match_pkt = csr_io_trigger_pkt_any_2_match_pkt; // @[dec_tlu_ctl.scala 881:40] + assign io_trigger_pkt_any_2_store = csr_io_trigger_pkt_any_2_store; // @[dec_tlu_ctl.scala 881:40] + assign io_trigger_pkt_any_2_load = csr_io_trigger_pkt_any_2_load; // @[dec_tlu_ctl.scala 881:40] + assign io_trigger_pkt_any_2_execute = csr_io_trigger_pkt_any_2_execute; // @[dec_tlu_ctl.scala 881:40] + assign io_trigger_pkt_any_2_m = csr_io_trigger_pkt_any_2_m; // @[dec_tlu_ctl.scala 881:40] + assign io_trigger_pkt_any_2_tdata2 = csr_io_trigger_pkt_any_2_tdata2; // @[dec_tlu_ctl.scala 881:40] + assign io_trigger_pkt_any_3_select = csr_io_trigger_pkt_any_3_select; // @[dec_tlu_ctl.scala 881:40] + assign io_trigger_pkt_any_3_match_pkt = csr_io_trigger_pkt_any_3_match_pkt; // @[dec_tlu_ctl.scala 881:40] + assign io_trigger_pkt_any_3_store = csr_io_trigger_pkt_any_3_store; // @[dec_tlu_ctl.scala 881:40] + assign io_trigger_pkt_any_3_load = csr_io_trigger_pkt_any_3_load; // @[dec_tlu_ctl.scala 881:40] + assign io_trigger_pkt_any_3_execute = csr_io_trigger_pkt_any_3_execute; // @[dec_tlu_ctl.scala 881:40] + assign io_trigger_pkt_any_3_m = csr_io_trigger_pkt_any_3_m; // @[dec_tlu_ctl.scala 881:40] + assign io_trigger_pkt_any_3_tdata2 = csr_io_trigger_pkt_any_3_tdata2; // @[dec_tlu_ctl.scala 881:40] + assign io_o_cpu_halt_status = _T_353; // @[dec_tlu_ctl.scala 572:49] + assign io_o_cpu_halt_ack = _T_354; // @[dec_tlu_ctl.scala 573:49] + assign io_o_cpu_run_ack = _T_355; // @[dec_tlu_ctl.scala 574:49] + assign io_o_debug_mode_status = debug_mode_status; // @[dec_tlu_ctl.scala 595:27] + assign io_mpc_debug_halt_ack = mpc_debug_halt_ack_f; // @[dec_tlu_ctl.scala 392:31] + assign io_mpc_debug_run_ack = mpc_debug_run_ack_f; // @[dec_tlu_ctl.scala 393:31] + assign io_debug_brkpt_status = debug_brkpt_status_f; // @[dec_tlu_ctl.scala 394:31] + assign io_dec_csr_rddata_d = csr_io_dec_csr_rddata_d; // @[dec_tlu_ctl.scala 896:40] + assign io_dec_csr_legal_d = _T_887 & _T_894; // @[dec_tlu_ctl.scala 1020:20] assign io_dec_tlu_i0_kill_writeb_wb = _T_32; // @[dec_tlu_ctl.scala 329:41] - assign io_dec_tlu_i0_kill_writeb_r = _T_427 | i0_trigger_hit_raw_r; // @[dec_tlu_ctl.scala 335:41] - assign io_dec_tlu_wr_pause_r = csr_io_dec_tlu_wr_pause_r; // @[dec_tlu_ctl.scala 900:40] - assign io_dec_tlu_flush_pause_r = _T_208 & _T_209; // @[dec_tlu_ctl.scala 480:34] - assign io_dec_tlu_presync_d = _T_864 & _T_865; // @[dec_tlu_ctl.scala 1015:23] - assign io_dec_tlu_postsync_d = csr_pkt_postsync & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 1016:23] - assign io_dec_tlu_perfcnt0 = csr_io_dec_tlu_perfcnt0; // @[dec_tlu_ctl.scala 886:40] - assign io_dec_tlu_perfcnt1 = csr_io_dec_tlu_perfcnt1; // @[dec_tlu_ctl.scala 887:40] - assign io_dec_tlu_perfcnt2 = csr_io_dec_tlu_perfcnt2; // @[dec_tlu_ctl.scala 888:40] - assign io_dec_tlu_perfcnt3 = csr_io_dec_tlu_perfcnt3; // @[dec_tlu_ctl.scala 889:40] - assign io_dec_tlu_i0_exc_valid_wb1 = csr_io_dec_tlu_i0_exc_valid_wb1; // @[dec_tlu_ctl.scala 880:44] - assign io_dec_tlu_i0_valid_wb1 = csr_io_dec_tlu_i0_valid_wb1; // @[dec_tlu_ctl.scala 881:44] - assign io_dec_tlu_int_valid_wb1 = csr_io_dec_tlu_int_valid_wb1; // @[dec_tlu_ctl.scala 879:44] - assign io_dec_tlu_exc_cause_wb1 = csr_io_dec_tlu_exc_cause_wb1; // @[dec_tlu_ctl.scala 885:40] - assign io_dec_tlu_mtval_wb1 = csr_io_dec_tlu_mtval_wb1; // @[dec_tlu_ctl.scala 884:40] - assign io_dec_tlu_pipelining_disable = csr_io_dec_tlu_pipelining_disable; // @[dec_tlu_ctl.scala 899:40] - assign io_dec_tlu_misc_clk_override = csr_io_dec_tlu_misc_clk_override; // @[dec_tlu_ctl.scala 890:40] - assign io_dec_tlu_dec_clk_override = csr_io_dec_tlu_dec_clk_override; // @[dec_tlu_ctl.scala 891:40] - assign io_dec_tlu_lsu_clk_override = csr_io_dec_tlu_lsu_clk_override; // @[dec_tlu_ctl.scala 893:40] - assign io_dec_tlu_bus_clk_override = csr_io_dec_tlu_bus_clk_override; // @[dec_tlu_ctl.scala 894:40] - assign io_dec_tlu_pic_clk_override = csr_io_dec_tlu_pic_clk_override; // @[dec_tlu_ctl.scala 895:40] - assign io_dec_tlu_dccm_clk_override = csr_io_dec_tlu_dccm_clk_override; // @[dec_tlu_ctl.scala 896:40] - assign io_dec_tlu_icm_clk_override = csr_io_dec_tlu_icm_clk_override; // @[dec_tlu_ctl.scala 897:40] - assign io_dec_tlu_flush_lower_wb = tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 801:41] - assign io_tlu_bp_dec_tlu_br0_r_pkt_valid = _T_459 & _T_462; // @[dec_tlu_ctl.scala 653:57] - assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_hist = io_tlu_exu_exu_i0_br_hist_r; // @[dec_tlu_ctl.scala 650:65] - assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_error = _T_453 & _T_429; // @[dec_tlu_ctl.scala 651:57] - assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_start_error = _T_455 & _T_429; // @[dec_tlu_ctl.scala 652:57] - assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_way = io_exu_i0_br_way_r; // @[dec_tlu_ctl.scala 654:65] - assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_middle = io_tlu_exu_exu_i0_br_middle_r; // @[dec_tlu_ctl.scala 655:65] - assign io_tlu_bp_dec_tlu_flush_leak_one_wb = _T_233 & _T_234; // @[dec_tlu_ctl.scala 484:45] - assign io_tlu_bp_dec_tlu_bpred_disable = csr_io_dec_tlu_bpred_disable; // @[dec_tlu_ctl.scala 903:47] - assign io_tlu_ifc_dec_tlu_flush_noredir_wb = _T_205 | take_ext_int_start; // @[dec_tlu_ctl.scala 475:45] - assign io_tlu_ifc_dec_tlu_mrac_ff = csr_io_dec_tlu_mrac_ff; // @[dec_tlu_ctl.scala 901:48] - assign io_tlu_mem_dec_tlu_flush_err_wb = io_tlu_exu_dec_tlu_flush_lower_r & _T_433; // @[dec_tlu_ctl.scala 485:41] - assign io_tlu_mem_dec_tlu_i0_commit_cmt = _T_422 & _T_465; // @[dec_tlu_ctl.scala 628:37] + assign io_dec_tlu_i0_kill_writeb_r = _T_427 | i0_trigger_hit_raw_r; // @[dec_tlu_ctl.scala 333:41] + assign io_dec_tlu_wr_pause_r = csr_io_dec_tlu_wr_pause_r; // @[dec_tlu_ctl.scala 898:40] + assign io_dec_tlu_flush_pause_r = _T_208 & _T_209; // @[dec_tlu_ctl.scala 478:34] + assign io_dec_tlu_presync_d = _T_864 & _T_865; // @[dec_tlu_ctl.scala 1013:23] + assign io_dec_tlu_postsync_d = csr_pkt_postsync & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 1014:23] + assign io_dec_tlu_perfcnt0 = csr_io_dec_tlu_perfcnt0; // @[dec_tlu_ctl.scala 884:40] + assign io_dec_tlu_perfcnt1 = csr_io_dec_tlu_perfcnt1; // @[dec_tlu_ctl.scala 885:40] + assign io_dec_tlu_perfcnt2 = csr_io_dec_tlu_perfcnt2; // @[dec_tlu_ctl.scala 886:40] + assign io_dec_tlu_perfcnt3 = csr_io_dec_tlu_perfcnt3; // @[dec_tlu_ctl.scala 887:40] + assign io_dec_tlu_i0_exc_valid_wb1 = csr_io_dec_tlu_i0_exc_valid_wb1; // @[dec_tlu_ctl.scala 878:44] + assign io_dec_tlu_i0_valid_wb1 = csr_io_dec_tlu_i0_valid_wb1; // @[dec_tlu_ctl.scala 879:44] + assign io_dec_tlu_int_valid_wb1 = csr_io_dec_tlu_int_valid_wb1; // @[dec_tlu_ctl.scala 877:44] + assign io_dec_tlu_exc_cause_wb1 = csr_io_dec_tlu_exc_cause_wb1; // @[dec_tlu_ctl.scala 883:40] + assign io_dec_tlu_mtval_wb1 = csr_io_dec_tlu_mtval_wb1; // @[dec_tlu_ctl.scala 882:40] + assign io_dec_tlu_pipelining_disable = csr_io_dec_tlu_pipelining_disable; // @[dec_tlu_ctl.scala 897:40] + assign io_dec_tlu_misc_clk_override = csr_io_dec_tlu_misc_clk_override; // @[dec_tlu_ctl.scala 888:40] + assign io_dec_tlu_dec_clk_override = csr_io_dec_tlu_dec_clk_override; // @[dec_tlu_ctl.scala 889:40] + assign io_dec_tlu_lsu_clk_override = csr_io_dec_tlu_lsu_clk_override; // @[dec_tlu_ctl.scala 891:40] + assign io_dec_tlu_pic_clk_override = csr_io_dec_tlu_pic_clk_override; // @[dec_tlu_ctl.scala 893:40] + assign io_dec_tlu_dccm_clk_override = csr_io_dec_tlu_dccm_clk_override; // @[dec_tlu_ctl.scala 894:40] + assign io_dec_tlu_icm_clk_override = csr_io_dec_tlu_icm_clk_override; // @[dec_tlu_ctl.scala 895:40] + assign io_dec_tlu_flush_lower_wb = tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 799:41] + assign io_tlu_bp_dec_tlu_br0_r_pkt_valid = _T_459 & _T_462; // @[dec_tlu_ctl.scala 651:57] + assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_hist = io_tlu_exu_exu_i0_br_hist_r; // @[dec_tlu_ctl.scala 648:65] + assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_error = _T_453 & _T_429; // @[dec_tlu_ctl.scala 649:57] + assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_start_error = _T_455 & _T_429; // @[dec_tlu_ctl.scala 650:57] + assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_way = io_exu_i0_br_way_r; // @[dec_tlu_ctl.scala 652:65] + assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_middle = io_tlu_exu_exu_i0_br_middle_r; // @[dec_tlu_ctl.scala 653:65] + assign io_tlu_bp_dec_tlu_flush_leak_one_wb = _T_233 & _T_234; // @[dec_tlu_ctl.scala 482:45] + assign io_tlu_bp_dec_tlu_bpred_disable = csr_io_dec_tlu_bpred_disable; // @[dec_tlu_ctl.scala 901:47] + assign io_tlu_ifc_dec_tlu_flush_noredir_wb = _T_205 | take_ext_int_start; // @[dec_tlu_ctl.scala 473:45] + assign io_tlu_ifc_dec_tlu_mrac_ff = csr_io_dec_tlu_mrac_ff; // @[dec_tlu_ctl.scala 899:48] + assign io_tlu_mem_dec_tlu_flush_err_wb = io_tlu_exu_dec_tlu_flush_lower_r & _T_433; // @[dec_tlu_ctl.scala 483:41] + assign io_tlu_mem_dec_tlu_i0_commit_cmt = _T_422 & _T_465; // @[dec_tlu_ctl.scala 626:37] assign io_tlu_mem_dec_tlu_force_halt = _T_33; // @[dec_tlu_ctl.scala 331:57] - assign io_tlu_mem_dec_tlu_fence_i_wb = _T_492 & _T_470; // @[dec_tlu_ctl.scala 673:39] - assign io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wrdata = csr_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[dec_tlu_ctl.scala 882:52] - assign io_tlu_mem_dec_tlu_ic_diag_pkt_icache_dicawics = csr_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[dec_tlu_ctl.scala 882:52] - assign io_tlu_mem_dec_tlu_ic_diag_pkt_icache_rd_valid = csr_io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[dec_tlu_ctl.scala 882:52] - assign io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wr_valid = csr_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[dec_tlu_ctl.scala 882:52] - assign io_tlu_mem_dec_tlu_core_ecc_disable = csr_io_dec_tlu_core_ecc_disable; // @[dec_tlu_ctl.scala 905:48] - assign io_tlu_busbuff_dec_tlu_external_ldfwd_disable = csr_io_dec_tlu_external_ldfwd_disable; // @[dec_tlu_ctl.scala 906:52] - assign io_tlu_busbuff_dec_tlu_sideeffect_posted_disable = csr_io_dec_tlu_sideeffect_posted_disable; // @[dec_tlu_ctl.scala 904:52] - assign io_dec_pic_dec_tlu_meicurpl = csr_io_dec_tlu_meicurpl; // @[dec_tlu_ctl.scala 876:52] - assign io_dec_pic_dec_tlu_meipt = csr_io_dec_tlu_meipt; // @[dec_tlu_ctl.scala 878:52] + assign io_tlu_mem_dec_tlu_fence_i_wb = _T_492 & _T_470; // @[dec_tlu_ctl.scala 671:39] + assign io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wrdata = csr_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[dec_tlu_ctl.scala 880:52] + assign io_tlu_mem_dec_tlu_ic_diag_pkt_icache_dicawics = csr_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[dec_tlu_ctl.scala 880:52] + assign io_tlu_mem_dec_tlu_ic_diag_pkt_icache_rd_valid = csr_io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[dec_tlu_ctl.scala 880:52] + assign io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wr_valid = csr_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[dec_tlu_ctl.scala 880:52] + assign io_tlu_mem_dec_tlu_core_ecc_disable = csr_io_dec_tlu_core_ecc_disable; // @[dec_tlu_ctl.scala 903:48] + assign io_tlu_busbuff_dec_tlu_external_ldfwd_disable = csr_io_dec_tlu_external_ldfwd_disable; // @[dec_tlu_ctl.scala 904:52] + assign io_tlu_busbuff_dec_tlu_wb_coalescing_disable = csr_io_dec_tlu_wb_coalescing_disable; // @[dec_tlu_ctl.scala 900:52] + assign io_tlu_busbuff_dec_tlu_sideeffect_posted_disable = csr_io_dec_tlu_sideeffect_posted_disable; // @[dec_tlu_ctl.scala 902:52] + assign io_dec_pic_dec_tlu_meicurpl = csr_io_dec_tlu_meicurpl; // @[dec_tlu_ctl.scala 874:52] + assign io_dec_pic_dec_tlu_meipt = csr_io_dec_tlu_meipt; // @[dec_tlu_ctl.scala 876:52] assign int_timers_clock = clock; assign int_timers_reset = reset; assign int_timers_io_free_clk = io_free_clk; // @[dec_tlu_ctl.scala 276:57] @@ -56089,197 +56100,197 @@ module dec_tlu_ctl( assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] assign csr_clock = clock; assign csr_reset = reset; - assign csr_io_free_clk = io_free_clk; // @[dec_tlu_ctl.scala 819:44] - assign csr_io_active_clk = io_active_clk; // @[dec_tlu_ctl.scala 820:44] - assign csr_io_scan_mode = io_scan_mode; // @[dec_tlu_ctl.scala 821:44] - assign csr_io_dec_csr_wrdata_r = io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 822:44] - assign csr_io_dec_csr_wraddr_r = io_dec_csr_wraddr_r; // @[dec_tlu_ctl.scala 823:44] - assign csr_io_dec_csr_rdaddr_d = io_dec_csr_rdaddr_d; // @[dec_tlu_ctl.scala 824:44] - assign csr_io_dec_csr_wen_unq_d = io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 825:44] - assign csr_io_dec_i0_decode_d = io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 826:44] - assign csr_io_ifu_ic_debug_rd_data_valid = io_tlu_mem_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 827:44] - assign csr_io_ifu_pmu_bus_trxn = io_tlu_mem_ifu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 828:44] - assign csr_io_dma_iccm_stall_any = io_tlu_dma_dma_iccm_stall_any; // @[dec_tlu_ctl.scala 829:44] - assign csr_io_dma_dccm_stall_any = io_tlu_dma_dma_dccm_stall_any; // @[dec_tlu_ctl.scala 830:44] - assign csr_io_lsu_store_stall_any = io_lsu_store_stall_any; // @[dec_tlu_ctl.scala 831:44] - assign csr_io_dec_pmu_presync_stall = io_dec_pmu_presync_stall; // @[dec_tlu_ctl.scala 832:44] - assign csr_io_dec_pmu_postsync_stall = io_dec_pmu_postsync_stall; // @[dec_tlu_ctl.scala 833:44] - assign csr_io_dec_pmu_decode_stall = io_dec_pmu_decode_stall; // @[dec_tlu_ctl.scala 834:44] - assign csr_io_ifu_pmu_fetch_stall = io_tlu_ifc_ifu_pmu_fetch_stall; // @[dec_tlu_ctl.scala 835:44] - assign csr_io_dec_tlu_packet_r_icaf_type = io_dec_tlu_packet_r_icaf_type; // @[dec_tlu_ctl.scala 836:44] - assign csr_io_dec_tlu_packet_r_pmu_i0_itype = io_dec_tlu_packet_r_pmu_i0_itype; // @[dec_tlu_ctl.scala 836:44] - assign csr_io_dec_tlu_packet_r_pmu_i0_br_unpred = io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[dec_tlu_ctl.scala 836:44] - assign csr_io_dec_tlu_packet_r_pmu_divide = io_dec_tlu_packet_r_pmu_divide; // @[dec_tlu_ctl.scala 836:44] - assign csr_io_dec_tlu_packet_r_pmu_lsu_misaligned = io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 836:44] - assign csr_io_exu_pmu_i0_br_ataken = io_tlu_exu_exu_pmu_i0_br_ataken; // @[dec_tlu_ctl.scala 837:44] - assign csr_io_exu_pmu_i0_br_misp = io_tlu_exu_exu_pmu_i0_br_misp; // @[dec_tlu_ctl.scala 838:44] - assign csr_io_dec_pmu_instr_decoded = io_dec_pmu_instr_decoded; // @[dec_tlu_ctl.scala 839:44] - assign csr_io_ifu_pmu_instr_aligned = io_ifu_pmu_instr_aligned; // @[dec_tlu_ctl.scala 840:44] - assign csr_io_exu_pmu_i0_pc4 = io_tlu_exu_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 841:44] - assign csr_io_ifu_pmu_ic_miss = io_tlu_mem_ifu_pmu_ic_miss; // @[dec_tlu_ctl.scala 842:44] - assign csr_io_ifu_pmu_ic_hit = io_tlu_mem_ifu_pmu_ic_hit; // @[dec_tlu_ctl.scala 843:44] - assign csr_io_dec_csr_wen_r = io_dec_csr_wen_r; // @[dec_tlu_ctl.scala 844:44] - assign csr_io_dec_tlu_dbg_halted = io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 845:44] - assign csr_io_dma_pmu_dccm_write = io_tlu_dma_dma_pmu_dccm_write; // @[dec_tlu_ctl.scala 846:44] - assign csr_io_dma_pmu_dccm_read = io_tlu_dma_dma_pmu_dccm_read; // @[dec_tlu_ctl.scala 847:44] - assign csr_io_dma_pmu_any_write = io_tlu_dma_dma_pmu_any_write; // @[dec_tlu_ctl.scala 848:44] - assign csr_io_dma_pmu_any_read = io_tlu_dma_dma_pmu_any_read; // @[dec_tlu_ctl.scala 849:44] - assign csr_io_lsu_pmu_bus_busy = io_tlu_busbuff_lsu_pmu_bus_busy; // @[dec_tlu_ctl.scala 850:44] - assign csr_io_dec_tlu_i0_pc_r = io_dec_tlu_i0_pc_r; // @[dec_tlu_ctl.scala 851:44] - assign csr_io_dec_tlu_i0_valid_r = io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 852:44] - assign csr_io_dec_csr_any_unq_d = io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 854:44] - assign csr_io_ifu_pmu_bus_busy = io_tlu_mem_ifu_pmu_bus_busy; // @[dec_tlu_ctl.scala 855:44] - assign csr_io_lsu_pmu_bus_error = io_tlu_busbuff_lsu_pmu_bus_error; // @[dec_tlu_ctl.scala 856:44] - assign csr_io_ifu_pmu_bus_error = io_tlu_mem_ifu_pmu_bus_error; // @[dec_tlu_ctl.scala 857:44] - assign csr_io_lsu_pmu_bus_misaligned = io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[dec_tlu_ctl.scala 858:44] - assign csr_io_lsu_pmu_bus_trxn = io_tlu_busbuff_lsu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 859:44] - assign csr_io_ifu_ic_debug_rd_data = io_tlu_mem_ifu_ic_debug_rd_data; // @[dec_tlu_ctl.scala 860:44] - assign csr_io_pic_pl = io_dec_pic_pic_pl; // @[dec_tlu_ctl.scala 861:44] - assign csr_io_pic_claimid = io_dec_pic_pic_claimid; // @[dec_tlu_ctl.scala 862:44] - assign csr_io_iccm_dma_sb_error = io_iccm_dma_sb_error; // @[dec_tlu_ctl.scala 863:44] - assign csr_io_lsu_imprecise_error_addr_any = io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[dec_tlu_ctl.scala 864:44] - assign csr_io_lsu_imprecise_error_load_any = io_tlu_busbuff_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 865:44] - assign csr_io_lsu_imprecise_error_store_any = io_tlu_busbuff_lsu_imprecise_error_store_any; // @[dec_tlu_ctl.scala 866:44] - assign csr_io_dec_illegal_inst = io_dec_illegal_inst; // @[dec_tlu_ctl.scala 867:44 dec_tlu_ctl.scala 908:44] - assign csr_io_lsu_error_pkt_r_bits_mscause = io_lsu_error_pkt_r_bits_mscause; // @[dec_tlu_ctl.scala 868:44 dec_tlu_ctl.scala 909:44] - assign csr_io_mexintpend = io_dec_pic_mexintpend; // @[dec_tlu_ctl.scala 869:44 dec_tlu_ctl.scala 910:44] - assign csr_io_exu_npc_r = io_tlu_exu_exu_npc_r; // @[dec_tlu_ctl.scala 870:44 dec_tlu_ctl.scala 911:44] - assign csr_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 871:44 dec_tlu_ctl.scala 912:44] - assign csr_io_rst_vec = io_rst_vec; // @[dec_tlu_ctl.scala 872:44 dec_tlu_ctl.scala 913:44] - assign csr_io_core_id = io_core_id; // @[dec_tlu_ctl.scala 873:44 dec_tlu_ctl.scala 914:44] - assign csr_io_dec_timer_rddata_d = int_timers_io_dec_timer_rddata_d; // @[dec_tlu_ctl.scala 874:44 dec_tlu_ctl.scala 915:44] - assign csr_io_dec_timer_read_d = int_timers_io_dec_timer_read_d; // @[dec_tlu_ctl.scala 875:44 dec_tlu_ctl.scala 916:44] - assign csr_io_rfpc_i0_r = _T_438 & _T_439; // @[dec_tlu_ctl.scala 919:39] - assign csr_io_i0_trigger_hit_r = |i0_trigger_chain_masked_r; // @[dec_tlu_ctl.scala 920:39] - assign csr_io_exc_or_int_valid_r = _T_855 | mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 921:39] - assign csr_io_mret_r = _T_487 & _T_470; // @[dec_tlu_ctl.scala 922:39] - assign csr_io_dcsr_single_step_running_f = dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 923:39] - assign csr_io_dec_timer_t0_pulse = int_timers_io_dec_timer_t0_pulse; // @[dec_tlu_ctl.scala 924:39] - assign csr_io_dec_timer_t1_pulse = int_timers_io_dec_timer_t1_pulse; // @[dec_tlu_ctl.scala 925:39] - assign csr_io_timer_int_sync = syncro_ff[5]; // @[dec_tlu_ctl.scala 926:39] - assign csr_io_soft_int_sync = syncro_ff[4]; // @[dec_tlu_ctl.scala 927:39] - assign csr_io_csr_wr_clk = rvclkhdr_io_l1clk; // @[dec_tlu_ctl.scala 928:39] - assign csr_io_ebreak_to_debug_mode_r = _T_519 & _T_470; // @[dec_tlu_ctl.scala 929:39] - assign csr_io_dec_tlu_pmu_fw_halted = pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 930:39] - assign csr_io_lsu_fir_error = io_lsu_fir_error; // @[dec_tlu_ctl.scala 931:39] - assign csr_io_tlu_flush_lower_r_d1 = tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 932:39] - assign csr_io_dec_tlu_flush_noredir_r_d1 = dec_tlu_flush_noredir_r_d1; // @[dec_tlu_ctl.scala 933:39] - assign csr_io_tlu_flush_path_r_d1 = tlu_flush_path_r_d1; // @[dec_tlu_ctl.scala 934:39] - assign csr_io_reset_delayed = reset_detect ^ reset_detected; // @[dec_tlu_ctl.scala 935:39] - assign csr_io_interrupt_valid_r = _T_766 | take_int_timer1_int; // @[dec_tlu_ctl.scala 936:39] - assign csr_io_i0_exception_valid_r = _T_527 & _T_528; // @[dec_tlu_ctl.scala 937:39] - assign csr_io_lsu_exc_valid_r = _T_405 & _T_470; // @[dec_tlu_ctl.scala 938:39] - assign csr_io_mepc_trigger_hit_sel_pc_r = i0_trigger_hit_raw_r & _T_345; // @[dec_tlu_ctl.scala 939:39] - assign csr_io_e4e5_int_clk = rvclkhdr_3_io_l1clk; // @[dec_tlu_ctl.scala 940:39] - assign csr_io_lsu_i0_exc_r = _T_405 & _T_470; // @[dec_tlu_ctl.scala 941:39] - assign csr_io_inst_acc_r = _T_511 & _T_465; // @[dec_tlu_ctl.scala 942:39] - assign csr_io_inst_acc_second_r = io_dec_tlu_packet_r_icaf_f1; // @[dec_tlu_ctl.scala 943:39] - assign csr_io_take_nmi = _T_756 & _T_760; // @[dec_tlu_ctl.scala 944:39] - assign csr_io_lsu_error_pkt_addr_r = io_lsu_error_pkt_r_bits_addr; // @[dec_tlu_ctl.scala 945:39] - assign csr_io_exc_cause_r = _T_603 | _T_591; // @[dec_tlu_ctl.scala 946:39] - assign csr_io_i0_valid_wb = i0_valid_wb; // @[dec_tlu_ctl.scala 947:39] - assign csr_io_exc_or_int_valid_r_d1 = exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 948:39] - assign csr_io_interrupt_valid_r_d1 = interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 949:39] - assign csr_io_clk_override = io_dec_tlu_dec_clk_override; // @[dec_tlu_ctl.scala 950:39] - assign csr_io_i0_exception_valid_r_d1 = i0_exception_valid_r_d1; // @[dec_tlu_ctl.scala 951:39] - assign csr_io_lsu_i0_exc_r_d1 = lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 952:39] - assign csr_io_exc_cause_wb = exc_cause_wb; // @[dec_tlu_ctl.scala 953:39] - assign csr_io_nmi_lsu_store_type = _T_58 | _T_60; // @[dec_tlu_ctl.scala 954:39] - assign csr_io_nmi_lsu_load_type = _T_50 | _T_52; // @[dec_tlu_ctl.scala 955:39] - assign csr_io_tlu_i0_commit_cmt = _T_422 & _T_465; // @[dec_tlu_ctl.scala 956:39] - assign csr_io_ebreak_r = _T_469 & _T_470; // @[dec_tlu_ctl.scala 957:39] - assign csr_io_ecall_r = _T_475 & _T_470; // @[dec_tlu_ctl.scala 958:39] - assign csr_io_illegal_r = _T_481 & _T_470; // @[dec_tlu_ctl.scala 959:39] - assign csr_io_mdseac_locked_f = mdseac_locked_f; // @[dec_tlu_ctl.scala 960:39] - assign csr_io_nmi_int_detected_f = nmi_int_detected_f; // @[dec_tlu_ctl.scala 961:39] - assign csr_io_internal_dbg_halt_mode_f2 = internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 962:39] - assign csr_io_ext_int_freeze_d1 = ext_int_freeze_d1; // @[dec_tlu_ctl.scala 963:39] - assign csr_io_ic_perr_r_d1 = ic_perr_r_d1; // @[dec_tlu_ctl.scala 964:39] - assign csr_io_iccm_sbecc_r_d1 = iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 965:39] - assign csr_io_lsu_single_ecc_error_r_d1 = lsu_single_ecc_error_r_d1; // @[dec_tlu_ctl.scala 966:39] - assign csr_io_ifu_miss_state_idle_f = ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 967:39] - assign csr_io_lsu_idle_any_f = lsu_idle_any_f; // @[dec_tlu_ctl.scala 968:39] - assign csr_io_dbg_tlu_halted_f = dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 969:39] - assign csr_io_dbg_tlu_halted = _T_164 | _T_166; // @[dec_tlu_ctl.scala 970:39] - assign csr_io_debug_halt_req_f = debug_halt_req_f; // @[dec_tlu_ctl.scala 971:51] - assign csr_io_take_ext_int_start = ext_int_ready & _T_704; // @[dec_tlu_ctl.scala 972:47] - assign csr_io_trigger_hit_dmode_r_d1 = trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 973:43] - assign csr_io_trigger_hit_r_d1 = trigger_hit_r_d1; // @[dec_tlu_ctl.scala 974:43] - assign csr_io_dcsr_single_step_done_f = dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 975:43] - assign csr_io_ebreak_to_debug_mode_r_d1 = ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 976:39] - assign csr_io_debug_halt_req = _T_114 & _T_107; // @[dec_tlu_ctl.scala 977:51] - assign csr_io_allow_dbg_halt_csr_write = debug_mode_status & _T_77; // @[dec_tlu_ctl.scala 978:39] - assign csr_io_internal_dbg_halt_mode_f = debug_mode_status; // @[dec_tlu_ctl.scala 979:39] - assign csr_io_enter_debug_halt_req = _T_155 | ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 980:39] - assign csr_io_internal_dbg_halt_mode = debug_halt_req_ns | _T_160; // @[dec_tlu_ctl.scala 981:39] - assign csr_io_request_debug_mode_done = _T_183 & _T_136; // @[dec_tlu_ctl.scala 982:39] - assign csr_io_request_debug_mode_r = _T_180 | _T_182; // @[dec_tlu_ctl.scala 983:39] - assign csr_io_update_hit_bit_r = _T_342 & i0_trigger_chain_masked_r; // @[dec_tlu_ctl.scala 984:39] - assign csr_io_take_timer_int = _T_703 & _T_704; // @[dec_tlu_ctl.scala 985:39] - assign csr_io_take_int_timer0_int = _T_717 & _T_704; // @[dec_tlu_ctl.scala 986:39] - assign csr_io_take_int_timer1_int = _T_734 & _T_704; // @[dec_tlu_ctl.scala 987:39] - assign csr_io_take_ext_int = take_ext_int_start_d3 & _T_685; // @[dec_tlu_ctl.scala 988:39] - assign csr_io_tlu_flush_lower_r = _T_801 | take_ext_int_start; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_dec_tlu_br0_error_r = _T_453 & _T_429; // @[dec_tlu_ctl.scala 990:39] - assign csr_io_dec_tlu_br0_start_error_r = _T_455 & _T_429; // @[dec_tlu_ctl.scala 991:39] - assign csr_io_lsu_pmu_load_external_r = lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_lsu_pmu_store_external_r = lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 993:39] - assign csr_io_csr_pkt_csr_misa = csr_read_io_csr_pkt_csr_misa; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_csr_pkt_csr_mvendorid = csr_read_io_csr_pkt_csr_mvendorid; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_csr_pkt_csr_marchid = csr_read_io_csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_csr_pkt_csr_mimpid = csr_read_io_csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_csr_pkt_csr_mhartid = csr_read_io_csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_csr_pkt_csr_mstatus = csr_read_io_csr_pkt_csr_mstatus; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_csr_pkt_csr_mtvec = csr_read_io_csr_pkt_csr_mtvec; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_csr_pkt_csr_mip = csr_read_io_csr_pkt_csr_mip; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_csr_pkt_csr_mie = csr_read_io_csr_pkt_csr_mie; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_csr_pkt_csr_mcyclel = csr_read_io_csr_pkt_csr_mcyclel; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_csr_pkt_csr_mcycleh = csr_read_io_csr_pkt_csr_mcycleh; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_csr_pkt_csr_minstretl = csr_read_io_csr_pkt_csr_minstretl; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_csr_pkt_csr_minstreth = csr_read_io_csr_pkt_csr_minstreth; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_csr_pkt_csr_mscratch = csr_read_io_csr_pkt_csr_mscratch; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_csr_pkt_csr_mepc = csr_read_io_csr_pkt_csr_mepc; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_csr_pkt_csr_mcause = csr_read_io_csr_pkt_csr_mcause; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_csr_pkt_csr_mscause = csr_read_io_csr_pkt_csr_mscause; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_csr_pkt_csr_mtval = csr_read_io_csr_pkt_csr_mtval; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_csr_pkt_csr_mrac = csr_read_io_csr_pkt_csr_mrac; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_csr_pkt_csr_mdseac = csr_read_io_csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_csr_pkt_csr_meihap = csr_read_io_csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_csr_pkt_csr_meivt = csr_read_io_csr_pkt_csr_meivt; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_csr_pkt_csr_meipt = csr_read_io_csr_pkt_csr_meipt; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_csr_pkt_csr_meicurpl = csr_read_io_csr_pkt_csr_meicurpl; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_csr_pkt_csr_meicidpl = csr_read_io_csr_pkt_csr_meicidpl; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_csr_pkt_csr_dcsr = csr_read_io_csr_pkt_csr_dcsr; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_csr_pkt_csr_mcgc = csr_read_io_csr_pkt_csr_mcgc; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_csr_pkt_csr_mfdc = csr_read_io_csr_pkt_csr_mfdc; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_csr_pkt_csr_dpc = csr_read_io_csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_csr_pkt_csr_mtsel = csr_read_io_csr_pkt_csr_mtsel; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_csr_pkt_csr_mtdata1 = csr_read_io_csr_pkt_csr_mtdata1; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_csr_pkt_csr_mtdata2 = csr_read_io_csr_pkt_csr_mtdata2; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_csr_pkt_csr_mhpmc3 = csr_read_io_csr_pkt_csr_mhpmc3; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_csr_pkt_csr_mhpmc4 = csr_read_io_csr_pkt_csr_mhpmc4; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_csr_pkt_csr_mhpmc5 = csr_read_io_csr_pkt_csr_mhpmc5; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_csr_pkt_csr_mhpmc6 = csr_read_io_csr_pkt_csr_mhpmc6; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_csr_pkt_csr_mhpmc3h = csr_read_io_csr_pkt_csr_mhpmc3h; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_csr_pkt_csr_mhpmc4h = csr_read_io_csr_pkt_csr_mhpmc4h; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_csr_pkt_csr_mhpmc5h = csr_read_io_csr_pkt_csr_mhpmc5h; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_csr_pkt_csr_mhpmc6h = csr_read_io_csr_pkt_csr_mhpmc6h; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_csr_pkt_csr_mhpme3 = csr_read_io_csr_pkt_csr_mhpme3; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_csr_pkt_csr_mhpme4 = csr_read_io_csr_pkt_csr_mhpme4; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_csr_pkt_csr_mhpme5 = csr_read_io_csr_pkt_csr_mhpme5; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_csr_pkt_csr_mhpme6 = csr_read_io_csr_pkt_csr_mhpme6; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_csr_pkt_csr_mcountinhibit = csr_read_io_csr_pkt_csr_mcountinhibit; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_csr_pkt_csr_mpmc = csr_read_io_csr_pkt_csr_mpmc; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_csr_pkt_csr_micect = csr_read_io_csr_pkt_csr_micect; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_csr_pkt_csr_miccmect = csr_read_io_csr_pkt_csr_miccmect; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_csr_pkt_csr_mdccmect = csr_read_io_csr_pkt_csr_mdccmect; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_csr_pkt_csr_mfdht = csr_read_io_csr_pkt_csr_mfdht; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_csr_pkt_csr_mfdhs = csr_read_io_csr_pkt_csr_mfdhs; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_csr_pkt_csr_dicawics = csr_read_io_csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_csr_pkt_csr_dicad0h = csr_read_io_csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_csr_pkt_csr_dicad0 = csr_read_io_csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_csr_pkt_csr_dicad1 = csr_read_io_csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 994:39] - assign csr_read_io_dec_csr_rdaddr_d = io_dec_csr_rdaddr_d; // @[dec_tlu_ctl.scala 1012:37] + assign csr_io_free_clk = io_free_clk; // @[dec_tlu_ctl.scala 817:44] + assign csr_io_active_clk = io_active_clk; // @[dec_tlu_ctl.scala 818:44] + assign csr_io_scan_mode = io_scan_mode; // @[dec_tlu_ctl.scala 819:44] + assign csr_io_dec_csr_wrdata_r = io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 820:44] + assign csr_io_dec_csr_wraddr_r = io_dec_csr_wraddr_r; // @[dec_tlu_ctl.scala 821:44] + assign csr_io_dec_csr_rdaddr_d = io_dec_csr_rdaddr_d; // @[dec_tlu_ctl.scala 822:44] + assign csr_io_dec_csr_wen_unq_d = io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 823:44] + assign csr_io_dec_i0_decode_d = io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 824:44] + assign csr_io_ifu_ic_debug_rd_data_valid = io_tlu_mem_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 825:44] + assign csr_io_ifu_pmu_bus_trxn = io_tlu_mem_ifu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 826:44] + assign csr_io_dma_iccm_stall_any = io_tlu_dma_dma_iccm_stall_any; // @[dec_tlu_ctl.scala 827:44] + assign csr_io_dma_dccm_stall_any = io_tlu_dma_dma_dccm_stall_any; // @[dec_tlu_ctl.scala 828:44] + assign csr_io_lsu_store_stall_any = io_lsu_store_stall_any; // @[dec_tlu_ctl.scala 829:44] + assign csr_io_dec_pmu_presync_stall = io_dec_pmu_presync_stall; // @[dec_tlu_ctl.scala 830:44] + assign csr_io_dec_pmu_postsync_stall = io_dec_pmu_postsync_stall; // @[dec_tlu_ctl.scala 831:44] + assign csr_io_dec_pmu_decode_stall = io_dec_pmu_decode_stall; // @[dec_tlu_ctl.scala 832:44] + assign csr_io_ifu_pmu_fetch_stall = io_tlu_ifc_ifu_pmu_fetch_stall; // @[dec_tlu_ctl.scala 833:44] + assign csr_io_dec_tlu_packet_r_icaf_type = io_dec_tlu_packet_r_icaf_type; // @[dec_tlu_ctl.scala 834:44] + assign csr_io_dec_tlu_packet_r_pmu_i0_itype = io_dec_tlu_packet_r_pmu_i0_itype; // @[dec_tlu_ctl.scala 834:44] + assign csr_io_dec_tlu_packet_r_pmu_i0_br_unpred = io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[dec_tlu_ctl.scala 834:44] + assign csr_io_dec_tlu_packet_r_pmu_divide = io_dec_tlu_packet_r_pmu_divide; // @[dec_tlu_ctl.scala 834:44] + assign csr_io_dec_tlu_packet_r_pmu_lsu_misaligned = io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 834:44] + assign csr_io_exu_pmu_i0_br_ataken = io_tlu_exu_exu_pmu_i0_br_ataken; // @[dec_tlu_ctl.scala 835:44] + assign csr_io_exu_pmu_i0_br_misp = io_tlu_exu_exu_pmu_i0_br_misp; // @[dec_tlu_ctl.scala 836:44] + assign csr_io_dec_pmu_instr_decoded = io_dec_pmu_instr_decoded; // @[dec_tlu_ctl.scala 837:44] + assign csr_io_ifu_pmu_instr_aligned = io_ifu_pmu_instr_aligned; // @[dec_tlu_ctl.scala 838:44] + assign csr_io_exu_pmu_i0_pc4 = io_tlu_exu_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 839:44] + assign csr_io_ifu_pmu_ic_miss = io_tlu_mem_ifu_pmu_ic_miss; // @[dec_tlu_ctl.scala 840:44] + assign csr_io_ifu_pmu_ic_hit = io_tlu_mem_ifu_pmu_ic_hit; // @[dec_tlu_ctl.scala 841:44] + assign csr_io_dec_csr_wen_r = io_dec_csr_wen_r; // @[dec_tlu_ctl.scala 842:44] + assign csr_io_dec_tlu_dbg_halted = io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 843:44] + assign csr_io_dma_pmu_dccm_write = io_tlu_dma_dma_pmu_dccm_write; // @[dec_tlu_ctl.scala 844:44] + assign csr_io_dma_pmu_dccm_read = io_tlu_dma_dma_pmu_dccm_read; // @[dec_tlu_ctl.scala 845:44] + assign csr_io_dma_pmu_any_write = io_tlu_dma_dma_pmu_any_write; // @[dec_tlu_ctl.scala 846:44] + assign csr_io_dma_pmu_any_read = io_tlu_dma_dma_pmu_any_read; // @[dec_tlu_ctl.scala 847:44] + assign csr_io_lsu_pmu_bus_busy = io_tlu_busbuff_lsu_pmu_bus_busy; // @[dec_tlu_ctl.scala 848:44] + assign csr_io_dec_tlu_i0_pc_r = io_dec_tlu_i0_pc_r; // @[dec_tlu_ctl.scala 849:44] + assign csr_io_dec_tlu_i0_valid_r = io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 850:44] + assign csr_io_dec_csr_any_unq_d = io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 852:44] + assign csr_io_ifu_pmu_bus_busy = io_tlu_mem_ifu_pmu_bus_busy; // @[dec_tlu_ctl.scala 853:44] + assign csr_io_lsu_pmu_bus_error = io_tlu_busbuff_lsu_pmu_bus_error; // @[dec_tlu_ctl.scala 854:44] + assign csr_io_ifu_pmu_bus_error = io_tlu_mem_ifu_pmu_bus_error; // @[dec_tlu_ctl.scala 855:44] + assign csr_io_lsu_pmu_bus_misaligned = io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[dec_tlu_ctl.scala 856:44] + assign csr_io_lsu_pmu_bus_trxn = io_tlu_busbuff_lsu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 857:44] + assign csr_io_ifu_ic_debug_rd_data = io_tlu_mem_ifu_ic_debug_rd_data; // @[dec_tlu_ctl.scala 858:44] + assign csr_io_pic_pl = io_dec_pic_pic_pl; // @[dec_tlu_ctl.scala 859:44] + assign csr_io_pic_claimid = io_dec_pic_pic_claimid; // @[dec_tlu_ctl.scala 860:44] + assign csr_io_iccm_dma_sb_error = io_iccm_dma_sb_error; // @[dec_tlu_ctl.scala 861:44] + assign csr_io_lsu_imprecise_error_addr_any = io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[dec_tlu_ctl.scala 862:44] + assign csr_io_lsu_imprecise_error_load_any = io_tlu_busbuff_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 863:44] + assign csr_io_lsu_imprecise_error_store_any = io_tlu_busbuff_lsu_imprecise_error_store_any; // @[dec_tlu_ctl.scala 864:44] + assign csr_io_dec_illegal_inst = io_dec_illegal_inst; // @[dec_tlu_ctl.scala 865:44 dec_tlu_ctl.scala 906:44] + assign csr_io_lsu_error_pkt_r_bits_mscause = io_lsu_error_pkt_r_bits_mscause; // @[dec_tlu_ctl.scala 866:44 dec_tlu_ctl.scala 907:44] + assign csr_io_mexintpend = io_dec_pic_mexintpend; // @[dec_tlu_ctl.scala 867:44 dec_tlu_ctl.scala 908:44] + assign csr_io_exu_npc_r = io_tlu_exu_exu_npc_r; // @[dec_tlu_ctl.scala 868:44 dec_tlu_ctl.scala 909:44] + assign csr_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 869:44 dec_tlu_ctl.scala 910:44] + assign csr_io_rst_vec = io_rst_vec; // @[dec_tlu_ctl.scala 870:44 dec_tlu_ctl.scala 911:44] + assign csr_io_core_id = io_core_id; // @[dec_tlu_ctl.scala 871:44 dec_tlu_ctl.scala 912:44] + assign csr_io_dec_timer_rddata_d = int_timers_io_dec_timer_rddata_d; // @[dec_tlu_ctl.scala 872:44 dec_tlu_ctl.scala 913:44] + assign csr_io_dec_timer_read_d = int_timers_io_dec_timer_read_d; // @[dec_tlu_ctl.scala 873:44 dec_tlu_ctl.scala 914:44] + assign csr_io_rfpc_i0_r = _T_438 & _T_439; // @[dec_tlu_ctl.scala 917:39] + assign csr_io_i0_trigger_hit_r = |i0_trigger_chain_masked_r; // @[dec_tlu_ctl.scala 918:39] + assign csr_io_exc_or_int_valid_r = _T_855 | mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 919:39] + assign csr_io_mret_r = _T_487 & _T_470; // @[dec_tlu_ctl.scala 920:39] + assign csr_io_dcsr_single_step_running_f = dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 921:39] + assign csr_io_dec_timer_t0_pulse = int_timers_io_dec_timer_t0_pulse; // @[dec_tlu_ctl.scala 922:39] + assign csr_io_dec_timer_t1_pulse = int_timers_io_dec_timer_t1_pulse; // @[dec_tlu_ctl.scala 923:39] + assign csr_io_timer_int_sync = syncro_ff[5]; // @[dec_tlu_ctl.scala 924:39] + assign csr_io_soft_int_sync = syncro_ff[4]; // @[dec_tlu_ctl.scala 925:39] + assign csr_io_csr_wr_clk = rvclkhdr_io_l1clk; // @[dec_tlu_ctl.scala 926:39] + assign csr_io_ebreak_to_debug_mode_r = _T_519 & _T_470; // @[dec_tlu_ctl.scala 927:39] + assign csr_io_dec_tlu_pmu_fw_halted = pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 928:39] + assign csr_io_lsu_fir_error = io_lsu_fir_error; // @[dec_tlu_ctl.scala 929:39] + assign csr_io_tlu_flush_lower_r_d1 = tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 930:39] + assign csr_io_dec_tlu_flush_noredir_r_d1 = dec_tlu_flush_noredir_r_d1; // @[dec_tlu_ctl.scala 931:39] + assign csr_io_tlu_flush_path_r_d1 = tlu_flush_path_r_d1; // @[dec_tlu_ctl.scala 932:39] + assign csr_io_reset_delayed = reset_detect ^ reset_detected; // @[dec_tlu_ctl.scala 933:39] + assign csr_io_interrupt_valid_r = _T_766 | take_int_timer1_int; // @[dec_tlu_ctl.scala 934:39] + assign csr_io_i0_exception_valid_r = _T_527 & _T_528; // @[dec_tlu_ctl.scala 935:39] + assign csr_io_lsu_exc_valid_r = _T_405 & _T_470; // @[dec_tlu_ctl.scala 936:39] + assign csr_io_mepc_trigger_hit_sel_pc_r = i0_trigger_hit_raw_r & _T_345; // @[dec_tlu_ctl.scala 937:39] + assign csr_io_e4e5_int_clk = rvclkhdr_3_io_l1clk; // @[dec_tlu_ctl.scala 938:39] + assign csr_io_lsu_i0_exc_r = _T_405 & _T_470; // @[dec_tlu_ctl.scala 939:39] + assign csr_io_inst_acc_r = _T_511 & _T_465; // @[dec_tlu_ctl.scala 940:39] + assign csr_io_inst_acc_second_r = io_dec_tlu_packet_r_icaf_f1; // @[dec_tlu_ctl.scala 941:39] + assign csr_io_take_nmi = _T_756 & _T_760; // @[dec_tlu_ctl.scala 942:39] + assign csr_io_lsu_error_pkt_addr_r = io_lsu_error_pkt_r_bits_addr; // @[dec_tlu_ctl.scala 943:39] + assign csr_io_exc_cause_r = _T_603 | _T_591; // @[dec_tlu_ctl.scala 944:39] + assign csr_io_i0_valid_wb = i0_valid_wb; // @[dec_tlu_ctl.scala 945:39] + assign csr_io_exc_or_int_valid_r_d1 = exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 946:39] + assign csr_io_interrupt_valid_r_d1 = interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 947:39] + assign csr_io_clk_override = io_dec_tlu_dec_clk_override; // @[dec_tlu_ctl.scala 948:39] + assign csr_io_i0_exception_valid_r_d1 = i0_exception_valid_r_d1; // @[dec_tlu_ctl.scala 949:39] + assign csr_io_lsu_i0_exc_r_d1 = lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 950:39] + assign csr_io_exc_cause_wb = exc_cause_wb; // @[dec_tlu_ctl.scala 951:39] + assign csr_io_nmi_lsu_store_type = _T_58 | _T_60; // @[dec_tlu_ctl.scala 952:39] + assign csr_io_nmi_lsu_load_type = _T_50 | _T_52; // @[dec_tlu_ctl.scala 953:39] + assign csr_io_tlu_i0_commit_cmt = _T_422 & _T_465; // @[dec_tlu_ctl.scala 954:39] + assign csr_io_ebreak_r = _T_469 & _T_470; // @[dec_tlu_ctl.scala 955:39] + assign csr_io_ecall_r = _T_475 & _T_470; // @[dec_tlu_ctl.scala 956:39] + assign csr_io_illegal_r = _T_481 & _T_470; // @[dec_tlu_ctl.scala 957:39] + assign csr_io_mdseac_locked_f = mdseac_locked_f; // @[dec_tlu_ctl.scala 958:39] + assign csr_io_nmi_int_detected_f = nmi_int_detected_f; // @[dec_tlu_ctl.scala 959:39] + assign csr_io_internal_dbg_halt_mode_f2 = internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 960:39] + assign csr_io_ext_int_freeze_d1 = ext_int_freeze_d1; // @[dec_tlu_ctl.scala 961:39] + assign csr_io_ic_perr_r_d1 = ic_perr_r_d1; // @[dec_tlu_ctl.scala 962:39] + assign csr_io_iccm_sbecc_r_d1 = iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 963:39] + assign csr_io_lsu_single_ecc_error_r_d1 = lsu_single_ecc_error_r_d1; // @[dec_tlu_ctl.scala 964:39] + assign csr_io_ifu_miss_state_idle_f = ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 965:39] + assign csr_io_lsu_idle_any_f = lsu_idle_any_f; // @[dec_tlu_ctl.scala 966:39] + assign csr_io_dbg_tlu_halted_f = dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 967:39] + assign csr_io_dbg_tlu_halted = _T_164 | _T_166; // @[dec_tlu_ctl.scala 968:39] + assign csr_io_debug_halt_req_f = debug_halt_req_f; // @[dec_tlu_ctl.scala 969:51] + assign csr_io_take_ext_int_start = ext_int_ready & _T_704; // @[dec_tlu_ctl.scala 970:47] + assign csr_io_trigger_hit_dmode_r_d1 = trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 971:43] + assign csr_io_trigger_hit_r_d1 = trigger_hit_r_d1; // @[dec_tlu_ctl.scala 972:43] + assign csr_io_dcsr_single_step_done_f = dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 973:43] + assign csr_io_ebreak_to_debug_mode_r_d1 = ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 974:39] + assign csr_io_debug_halt_req = _T_114 & _T_107; // @[dec_tlu_ctl.scala 975:51] + assign csr_io_allow_dbg_halt_csr_write = debug_mode_status & _T_77; // @[dec_tlu_ctl.scala 976:39] + assign csr_io_internal_dbg_halt_mode_f = debug_mode_status; // @[dec_tlu_ctl.scala 977:39] + assign csr_io_enter_debug_halt_req = _T_155 | ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 978:39] + assign csr_io_internal_dbg_halt_mode = debug_halt_req_ns | _T_160; // @[dec_tlu_ctl.scala 979:39] + assign csr_io_request_debug_mode_done = _T_183 & _T_136; // @[dec_tlu_ctl.scala 980:39] + assign csr_io_request_debug_mode_r = _T_180 | _T_182; // @[dec_tlu_ctl.scala 981:39] + assign csr_io_update_hit_bit_r = _T_342 & i0_trigger_chain_masked_r; // @[dec_tlu_ctl.scala 982:39] + assign csr_io_take_timer_int = _T_703 & _T_704; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_take_int_timer0_int = _T_717 & _T_704; // @[dec_tlu_ctl.scala 984:39] + assign csr_io_take_int_timer1_int = _T_734 & _T_704; // @[dec_tlu_ctl.scala 985:39] + assign csr_io_take_ext_int = take_ext_int_start_d3 & _T_685; // @[dec_tlu_ctl.scala 986:39] + assign csr_io_tlu_flush_lower_r = _T_801 | take_ext_int_start; // @[dec_tlu_ctl.scala 987:39] + assign csr_io_dec_tlu_br0_error_r = _T_453 & _T_429; // @[dec_tlu_ctl.scala 988:39] + assign csr_io_dec_tlu_br0_start_error_r = _T_455 & _T_429; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_lsu_pmu_load_external_r = lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 990:39] + assign csr_io_lsu_pmu_store_external_r = lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 991:39] + assign csr_io_csr_pkt_csr_misa = csr_read_io_csr_pkt_csr_misa; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_csr_pkt_csr_mvendorid = csr_read_io_csr_pkt_csr_mvendorid; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_csr_pkt_csr_marchid = csr_read_io_csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_csr_pkt_csr_mimpid = csr_read_io_csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_csr_pkt_csr_mhartid = csr_read_io_csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_csr_pkt_csr_mstatus = csr_read_io_csr_pkt_csr_mstatus; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_csr_pkt_csr_mtvec = csr_read_io_csr_pkt_csr_mtvec; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_csr_pkt_csr_mip = csr_read_io_csr_pkt_csr_mip; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_csr_pkt_csr_mie = csr_read_io_csr_pkt_csr_mie; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_csr_pkt_csr_mcyclel = csr_read_io_csr_pkt_csr_mcyclel; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_csr_pkt_csr_mcycleh = csr_read_io_csr_pkt_csr_mcycleh; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_csr_pkt_csr_minstretl = csr_read_io_csr_pkt_csr_minstretl; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_csr_pkt_csr_minstreth = csr_read_io_csr_pkt_csr_minstreth; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_csr_pkt_csr_mscratch = csr_read_io_csr_pkt_csr_mscratch; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_csr_pkt_csr_mepc = csr_read_io_csr_pkt_csr_mepc; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_csr_pkt_csr_mcause = csr_read_io_csr_pkt_csr_mcause; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_csr_pkt_csr_mscause = csr_read_io_csr_pkt_csr_mscause; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_csr_pkt_csr_mtval = csr_read_io_csr_pkt_csr_mtval; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_csr_pkt_csr_mrac = csr_read_io_csr_pkt_csr_mrac; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_csr_pkt_csr_mdseac = csr_read_io_csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_csr_pkt_csr_meihap = csr_read_io_csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_csr_pkt_csr_meivt = csr_read_io_csr_pkt_csr_meivt; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_csr_pkt_csr_meipt = csr_read_io_csr_pkt_csr_meipt; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_csr_pkt_csr_meicurpl = csr_read_io_csr_pkt_csr_meicurpl; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_csr_pkt_csr_meicidpl = csr_read_io_csr_pkt_csr_meicidpl; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_csr_pkt_csr_dcsr = csr_read_io_csr_pkt_csr_dcsr; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_csr_pkt_csr_mcgc = csr_read_io_csr_pkt_csr_mcgc; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_csr_pkt_csr_mfdc = csr_read_io_csr_pkt_csr_mfdc; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_csr_pkt_csr_dpc = csr_read_io_csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_csr_pkt_csr_mtsel = csr_read_io_csr_pkt_csr_mtsel; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_csr_pkt_csr_mtdata1 = csr_read_io_csr_pkt_csr_mtdata1; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_csr_pkt_csr_mtdata2 = csr_read_io_csr_pkt_csr_mtdata2; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_csr_pkt_csr_mhpmc3 = csr_read_io_csr_pkt_csr_mhpmc3; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_csr_pkt_csr_mhpmc4 = csr_read_io_csr_pkt_csr_mhpmc4; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_csr_pkt_csr_mhpmc5 = csr_read_io_csr_pkt_csr_mhpmc5; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_csr_pkt_csr_mhpmc6 = csr_read_io_csr_pkt_csr_mhpmc6; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_csr_pkt_csr_mhpmc3h = csr_read_io_csr_pkt_csr_mhpmc3h; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_csr_pkt_csr_mhpmc4h = csr_read_io_csr_pkt_csr_mhpmc4h; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_csr_pkt_csr_mhpmc5h = csr_read_io_csr_pkt_csr_mhpmc5h; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_csr_pkt_csr_mhpmc6h = csr_read_io_csr_pkt_csr_mhpmc6h; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_csr_pkt_csr_mhpme3 = csr_read_io_csr_pkt_csr_mhpme3; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_csr_pkt_csr_mhpme4 = csr_read_io_csr_pkt_csr_mhpme4; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_csr_pkt_csr_mhpme5 = csr_read_io_csr_pkt_csr_mhpme5; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_csr_pkt_csr_mhpme6 = csr_read_io_csr_pkt_csr_mhpme6; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_csr_pkt_csr_mcountinhibit = csr_read_io_csr_pkt_csr_mcountinhibit; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_csr_pkt_csr_mpmc = csr_read_io_csr_pkt_csr_mpmc; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_csr_pkt_csr_micect = csr_read_io_csr_pkt_csr_micect; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_csr_pkt_csr_miccmect = csr_read_io_csr_pkt_csr_miccmect; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_csr_pkt_csr_mdccmect = csr_read_io_csr_pkt_csr_mdccmect; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_csr_pkt_csr_mfdht = csr_read_io_csr_pkt_csr_mfdht; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_csr_pkt_csr_mfdhs = csr_read_io_csr_pkt_csr_mfdhs; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_csr_pkt_csr_dicawics = csr_read_io_csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_csr_pkt_csr_dicad0h = csr_read_io_csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_csr_pkt_csr_dicad0 = csr_read_io_csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_csr_pkt_csr_dicad1 = csr_read_io_csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 992:39] + assign csr_read_io_dec_csr_rdaddr_d = io_dec_csr_rdaddr_d; // @[dec_tlu_ctl.scala 1010:37] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -57929,7 +57940,6 @@ module dec( output [31:0] io_rv_trace_pkt_rv_i_tval_ip, output io_dec_tlu_misc_clk_override, output io_dec_tlu_lsu_clk_override, - output io_dec_tlu_bus_clk_override, output io_dec_tlu_pic_clk_override, output io_dec_tlu_dccm_clk_override, output io_dec_tlu_icm_clk_override, @@ -58067,6 +58077,7 @@ module dec( input io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error, input io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy, output io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable, + output io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable, output io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable, input io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any, input io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any, @@ -58474,7 +58485,6 @@ module dec( wire tlu_io_dec_tlu_misc_clk_override; // @[dec.scala 120:19] wire tlu_io_dec_tlu_dec_clk_override; // @[dec.scala 120:19] wire tlu_io_dec_tlu_lsu_clk_override; // @[dec.scala 120:19] - wire tlu_io_dec_tlu_bus_clk_override; // @[dec.scala 120:19] wire tlu_io_dec_tlu_pic_clk_override; // @[dec.scala 120:19] wire tlu_io_dec_tlu_dccm_clk_override; // @[dec.scala 120:19] wire tlu_io_dec_tlu_icm_clk_override; // @[dec.scala 120:19] @@ -58515,6 +58525,7 @@ module dec( wire tlu_io_tlu_busbuff_lsu_pmu_bus_error; // @[dec.scala 120:19] wire tlu_io_tlu_busbuff_lsu_pmu_bus_busy; // @[dec.scala 120:19] wire tlu_io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[dec.scala 120:19] + wire tlu_io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[dec.scala 120:19] wire tlu_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[dec.scala 120:19] wire tlu_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[dec.scala 120:19] wire tlu_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[dec.scala 120:19] @@ -58930,7 +58941,6 @@ module dec( .io_dec_tlu_misc_clk_override(tlu_io_dec_tlu_misc_clk_override), .io_dec_tlu_dec_clk_override(tlu_io_dec_tlu_dec_clk_override), .io_dec_tlu_lsu_clk_override(tlu_io_dec_tlu_lsu_clk_override), - .io_dec_tlu_bus_clk_override(tlu_io_dec_tlu_bus_clk_override), .io_dec_tlu_pic_clk_override(tlu_io_dec_tlu_pic_clk_override), .io_dec_tlu_dccm_clk_override(tlu_io_dec_tlu_dccm_clk_override), .io_dec_tlu_icm_clk_override(tlu_io_dec_tlu_icm_clk_override), @@ -58971,6 +58981,7 @@ module dec( .io_tlu_busbuff_lsu_pmu_bus_error(tlu_io_tlu_busbuff_lsu_pmu_bus_error), .io_tlu_busbuff_lsu_pmu_bus_busy(tlu_io_tlu_busbuff_lsu_pmu_bus_busy), .io_tlu_busbuff_dec_tlu_external_ldfwd_disable(tlu_io_tlu_busbuff_dec_tlu_external_ldfwd_disable), + .io_tlu_busbuff_dec_tlu_wb_coalescing_disable(tlu_io_tlu_busbuff_dec_tlu_wb_coalescing_disable), .io_tlu_busbuff_dec_tlu_sideeffect_posted_disable(tlu_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable), .io_tlu_busbuff_lsu_imprecise_error_load_any(tlu_io_tlu_busbuff_lsu_imprecise_error_load_any), .io_tlu_busbuff_lsu_imprecise_error_store_any(tlu_io_tlu_busbuff_lsu_imprecise_error_store_any), @@ -59069,7 +59080,6 @@ module dec( assign io_rv_trace_pkt_rv_i_tval_ip = tlu_io_dec_tlu_mtval_wb1; // @[dec.scala 300:32] assign io_dec_tlu_misc_clk_override = tlu_io_dec_tlu_misc_clk_override; // @[dec.scala 284:35] assign io_dec_tlu_lsu_clk_override = tlu_io_dec_tlu_lsu_clk_override; // @[dec.scala 286:36] - assign io_dec_tlu_bus_clk_override = tlu_io_dec_tlu_bus_clk_override; // @[dec.scala 287:36] assign io_dec_tlu_pic_clk_override = tlu_io_dec_tlu_pic_clk_override; // @[dec.scala 288:36] assign io_dec_tlu_dccm_clk_override = tlu_io_dec_tlu_dccm_clk_override; // @[dec.scala 289:36] assign io_dec_tlu_icm_clk_override = tlu_io_dec_tlu_icm_clk_override; // @[dec.scala 290:36] @@ -59157,6 +59167,7 @@ module dec( assign io_dec_exu_gpr_exu_gpr_i0_rs1_d = gpr_io_gpr_exu_gpr_i0_rs1_d; // @[dec.scala 201:22] assign io_dec_exu_gpr_exu_gpr_i0_rs2_d = gpr_io_gpr_exu_gpr_i0_rs2_d; // @[dec.scala 201:22] assign io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable = tlu_io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[dec.scala 222:26] + assign io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable = tlu_io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[dec.scala 222:26] assign io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable = tlu_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[dec.scala 222:26] assign io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty = tlu_io_tlu_dma_dec_tlu_dma_qos_prty; // @[dec.scala 206:18] assign io_dec_pic_dec_tlu_meicurpl = tlu_io_dec_pic_dec_tlu_meicurpl; // @[dec.scala 224:14] @@ -59406,6 +59417,7 @@ module dbg( input io_sb_axi_aw_ready, output io_sb_axi_aw_valid, output [31:0] io_sb_axi_aw_bits_addr, + output [3:0] io_sb_axi_aw_bits_region, output [2:0] io_sb_axi_aw_bits_size, input io_sb_axi_w_ready, output io_sb_axi_w_valid, @@ -59417,6 +59429,7 @@ module dbg( input io_sb_axi_ar_ready, output io_sb_axi_ar_valid, output [31:0] io_sb_axi_ar_bits_addr, + output [3:0] io_sb_axi_ar_bits_region, output [2:0] io_sb_axi_ar_bits_size, output io_sb_axi_r_ready, input io_sb_axi_r_valid, @@ -59508,67 +59521,66 @@ module dbg( wire dbg_dm_rst_l = io_dbg_rst_l & _T_9; // @[dbg.scala 100:94] wire _T_11 = io_dbg_rst_l & _T_9; // @[dbg.scala 102:38] wire rst_temp = _T_11 & reset; // @[dbg.scala 102:71] - wire rst_not = ~_T_11; // @[dbg.scala 104:52] - wire _T_17 = ~dmcontrol_reg[1]; // @[dbg.scala 107:25] - wire _T_19 = io_dmi_reg_addr == 7'h38; // @[dbg.scala 108:36] - wire _T_20 = _T_19 & io_dmi_reg_en; // @[dbg.scala 108:49] - wire _T_21 = _T_20 & io_dmi_reg_wr_en; // @[dbg.scala 108:65] - wire _T_22 = sb_state == 4'h0; // @[dbg.scala 108:96] - wire sbcs_wren = _T_21 & _T_22; // @[dbg.scala 108:84] - wire _T_24 = sbcs_wren & io_dmi_reg_wdata[22]; // @[dbg.scala 109:42] - wire _T_26 = _T_5 & io_dmi_reg_en; // @[dbg.scala 109:102] - wire _T_27 = io_dmi_reg_addr == 7'h39; // @[dbg.scala 110:23] - wire _T_28 = io_dmi_reg_addr == 7'h3c; // @[dbg.scala 110:55] - wire _T_29 = _T_27 | _T_28; // @[dbg.scala 110:36] - wire _T_30 = io_dmi_reg_addr == 7'h3d; // @[dbg.scala 110:87] - wire _T_31 = _T_29 | _T_30; // @[dbg.scala 110:68] - wire _T_32 = _T_26 & _T_31; // @[dbg.scala 109:118] - wire sbcs_sbbusyerror_wren = _T_24 | _T_32; // @[dbg.scala 109:66] - wire sbcs_sbbusyerror_din = ~_T_24; // @[dbg.scala 112:31] + wire _T_15 = ~dmcontrol_reg[1]; // @[dbg.scala 105:25] + wire _T_17 = io_dmi_reg_addr == 7'h38; // @[dbg.scala 106:36] + wire _T_18 = _T_17 & io_dmi_reg_en; // @[dbg.scala 106:49] + wire _T_19 = _T_18 & io_dmi_reg_wr_en; // @[dbg.scala 106:65] + wire _T_20 = sb_state == 4'h0; // @[dbg.scala 106:96] + wire sbcs_wren = _T_19 & _T_20; // @[dbg.scala 106:84] + wire _T_22 = sbcs_wren & io_dmi_reg_wdata[22]; // @[dbg.scala 107:42] + wire _T_24 = _T_5 & io_dmi_reg_en; // @[dbg.scala 107:102] + wire _T_25 = io_dmi_reg_addr == 7'h39; // @[dbg.scala 108:23] + wire _T_26 = io_dmi_reg_addr == 7'h3c; // @[dbg.scala 108:55] + wire _T_27 = _T_25 | _T_26; // @[dbg.scala 108:36] + wire _T_28 = io_dmi_reg_addr == 7'h3d; // @[dbg.scala 108:87] + wire _T_29 = _T_27 | _T_28; // @[dbg.scala 108:68] + wire _T_30 = _T_24 & _T_29; // @[dbg.scala 107:118] + wire sbcs_sbbusyerror_wren = _T_22 | _T_30; // @[dbg.scala 107:66] + wire sbcs_sbbusyerror_din = ~_T_22; // @[dbg.scala 110:31] reg temp_sbcs_22; // @[Reg.scala 27:20] reg temp_sbcs_21; // @[Reg.scala 27:20] reg temp_sbcs_20; // @[Reg.scala 27:20] reg [4:0] temp_sbcs_19_15; // @[Reg.scala 27:20] reg [2:0] temp_sbcs_14_12; // @[Reg.scala 27:20] - wire [19:0] _T_40 = {temp_sbcs_19_15,temp_sbcs_14_12,12'h40f}; // @[Cat.scala 29:58] - wire [11:0] _T_44 = {9'h40,temp_sbcs_22,temp_sbcs_21,temp_sbcs_20}; // @[Cat.scala 29:58] - wire _T_47 = sbcs_reg[19:17] == 3'h1; // @[dbg.scala 134:42] - wire _T_49 = _T_47 & sbaddress0_reg[0]; // @[dbg.scala 134:61] - wire _T_51 = sbcs_reg[19:17] == 3'h2; // @[dbg.scala 135:23] - wire _T_53 = |sbaddress0_reg[1:0]; // @[dbg.scala 135:65] - wire _T_54 = _T_51 & _T_53; // @[dbg.scala 135:42] - wire _T_55 = _T_49 | _T_54; // @[dbg.scala 134:81] - wire _T_57 = sbcs_reg[19:17] == 3'h3; // @[dbg.scala 136:23] - wire _T_59 = |sbaddress0_reg[2:0]; // @[dbg.scala 136:65] - wire _T_60 = _T_57 & _T_59; // @[dbg.scala 136:42] - wire sbcs_unaligned = _T_55 | _T_60; // @[dbg.scala 135:69] - wire sbcs_illegal_size = sbcs_reg[19]; // @[dbg.scala 138:35] - wire _T_62 = sbcs_reg[19:17] == 3'h0; // @[dbg.scala 139:51] - wire [3:0] _T_64 = _T_62 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_65 = _T_64 & 4'h1; // @[dbg.scala 139:64] - wire [3:0] _T_69 = _T_47 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_70 = _T_69 & 4'h2; // @[dbg.scala 139:122] - wire [3:0] _T_71 = _T_65 | _T_70; // @[dbg.scala 139:81] - wire [3:0] _T_75 = _T_51 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_76 = _T_75 & 4'h4; // @[dbg.scala 140:44] - wire [3:0] _T_77 = _T_71 | _T_76; // @[dbg.scala 139:139] - wire [3:0] _T_81 = _T_57 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_82 = _T_81 & 4'h8; // @[dbg.scala 140:102] - wire [3:0] sbaddress0_incr = _T_77 | _T_82; // @[dbg.scala 140:61] - wire _T_83 = io_dmi_reg_en & io_dmi_reg_wr_en; // @[dbg.scala 142:41] - wire sbdata0_reg_wren0 = _T_83 & _T_28; // @[dbg.scala 142:60] - wire _T_85 = sb_state == 4'h7; // @[dbg.scala 143:37] - wire _T_86 = _T_85 & sb_state_en; // @[dbg.scala 143:60] - wire _T_87 = ~sbcs_sberror_wren; // @[dbg.scala 143:76] - wire sbdata0_reg_wren1 = _T_86 & _T_87; // @[dbg.scala 143:74] - wire sbdata1_reg_wren0 = _T_83 & _T_30; // @[dbg.scala 145:60] - wire [31:0] _T_94 = sbdata0_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_95 = _T_94 & io_dmi_reg_wdata; // @[dbg.scala 148:49] - wire [31:0] _T_97 = sbdata0_reg_wren1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_99 = _T_97 & sb_bus_rdata[31:0]; // @[dbg.scala 149:33] - wire [31:0] _T_101 = sbdata1_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_102 = _T_101 & io_dmi_reg_wdata; // @[dbg.scala 151:49] - wire [31:0] _T_106 = _T_97 & sb_bus_rdata[63:32]; // @[dbg.scala 152:33] + wire [19:0] _T_38 = {temp_sbcs_19_15,temp_sbcs_14_12,12'h40f}; // @[Cat.scala 29:58] + wire [11:0] _T_42 = {9'h40,temp_sbcs_22,temp_sbcs_21,temp_sbcs_20}; // @[Cat.scala 29:58] + wire _T_45 = sbcs_reg[19:17] == 3'h1; // @[dbg.scala 132:42] + wire _T_47 = _T_45 & sbaddress0_reg[0]; // @[dbg.scala 132:61] + wire _T_49 = sbcs_reg[19:17] == 3'h2; // @[dbg.scala 133:23] + wire _T_51 = |sbaddress0_reg[1:0]; // @[dbg.scala 133:65] + wire _T_52 = _T_49 & _T_51; // @[dbg.scala 133:42] + wire _T_53 = _T_47 | _T_52; // @[dbg.scala 132:81] + wire _T_55 = sbcs_reg[19:17] == 3'h3; // @[dbg.scala 134:23] + wire _T_57 = |sbaddress0_reg[2:0]; // @[dbg.scala 134:65] + wire _T_58 = _T_55 & _T_57; // @[dbg.scala 134:42] + wire sbcs_unaligned = _T_53 | _T_58; // @[dbg.scala 133:69] + wire sbcs_illegal_size = sbcs_reg[19]; // @[dbg.scala 136:35] + wire _T_60 = sbcs_reg[19:17] == 3'h0; // @[dbg.scala 137:51] + wire [3:0] _T_62 = _T_60 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_63 = _T_62 & 4'h1; // @[dbg.scala 137:64] + wire [3:0] _T_67 = _T_45 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_68 = _T_67 & 4'h2; // @[dbg.scala 137:122] + wire [3:0] _T_69 = _T_63 | _T_68; // @[dbg.scala 137:81] + wire [3:0] _T_73 = _T_49 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_74 = _T_73 & 4'h4; // @[dbg.scala 138:44] + wire [3:0] _T_75 = _T_69 | _T_74; // @[dbg.scala 137:139] + wire [3:0] _T_79 = _T_55 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_80 = _T_79 & 4'h8; // @[dbg.scala 138:102] + wire [3:0] sbaddress0_incr = _T_75 | _T_80; // @[dbg.scala 138:61] + wire _T_81 = io_dmi_reg_en & io_dmi_reg_wr_en; // @[dbg.scala 140:41] + wire sbdata0_reg_wren0 = _T_81 & _T_26; // @[dbg.scala 140:60] + wire _T_83 = sb_state == 4'h7; // @[dbg.scala 141:37] + wire _T_84 = _T_83 & sb_state_en; // @[dbg.scala 141:60] + wire _T_85 = ~sbcs_sberror_wren; // @[dbg.scala 141:76] + wire sbdata0_reg_wren1 = _T_84 & _T_85; // @[dbg.scala 141:74] + wire sbdata1_reg_wren0 = _T_81 & _T_28; // @[dbg.scala 143:60] + wire [31:0] _T_92 = sbdata0_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_93 = _T_92 & io_dmi_reg_wdata; // @[dbg.scala 146:49] + wire [31:0] _T_95 = sbdata0_reg_wren1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_97 = _T_95 & sb_bus_rdata[31:0]; // @[dbg.scala 147:33] + wire [31:0] _T_99 = sbdata1_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_100 = _T_99 & io_dmi_reg_wdata; // @[dbg.scala 149:49] + wire [31:0] _T_104 = _T_95 & sb_bus_rdata[63:32]; // @[dbg.scala 150:33] wire rvclkhdr_2_io_l1clk; // @[lib.scala 368:23] wire rvclkhdr_2_io_clk; // @[lib.scala 368:23] wire rvclkhdr_2_io_en; // @[lib.scala 368:23] @@ -59579,382 +59591,382 @@ module dbg( wire rvclkhdr_3_io_en; // @[lib.scala 368:23] wire rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23] reg [31:0] sbdata1_reg; // @[lib.scala 374:16] - wire sbaddress0_reg_wren0 = _T_83 & _T_27; // @[dbg.scala 162:63] - wire [31:0] _T_110 = sbaddress0_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_111 = _T_110 & io_dmi_reg_wdata; // @[dbg.scala 164:59] - wire [31:0] _T_113 = sbaddress0_reg_wren1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_114 = {28'h0,sbaddress0_incr}; // @[Cat.scala 29:58] - wire [31:0] _T_116 = sbaddress0_reg + _T_114; // @[dbg.scala 165:54] - wire [31:0] _T_117 = _T_113 & _T_116; // @[dbg.scala 165:36] + wire sbaddress0_reg_wren0 = _T_81 & _T_25; // @[dbg.scala 160:63] + wire [31:0] _T_108 = sbaddress0_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_109 = _T_108 & io_dmi_reg_wdata; // @[dbg.scala 162:59] + wire [31:0] _T_111 = sbaddress0_reg_wren1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_112 = {28'h0,sbaddress0_incr}; // @[Cat.scala 29:58] + wire [31:0] _T_114 = sbaddress0_reg + _T_112; // @[dbg.scala 163:54] + wire [31:0] _T_115 = _T_111 & _T_114; // @[dbg.scala 163:36] wire rvclkhdr_4_io_l1clk; // @[lib.scala 368:23] wire rvclkhdr_4_io_clk; // @[lib.scala 368:23] wire rvclkhdr_4_io_en; // @[lib.scala 368:23] wire rvclkhdr_4_io_scan_mode; // @[lib.scala 368:23] - reg [31:0] _T_118; // @[lib.scala 374:16] - wire sbreadonaddr_access = sbaddress0_reg_wren0 & sbcs_reg[20]; // @[dbg.scala 170:94] - wire _T_123 = ~io_dmi_reg_wr_en; // @[dbg.scala 171:45] - wire _T_124 = io_dmi_reg_en & _T_123; // @[dbg.scala 171:43] - wire _T_126 = _T_124 & _T_28; // @[dbg.scala 171:63] - wire sbreadondata_access = _T_126 & sbcs_reg[15]; // @[dbg.scala 171:95] - wire _T_130 = io_dmi_reg_addr == 7'h10; // @[dbg.scala 173:41] - wire _T_131 = _T_130 & io_dmi_reg_en; // @[dbg.scala 173:54] - wire dmcontrol_wren = _T_131 & io_dmi_reg_wr_en; // @[dbg.scala 173:70] - wire [3:0] _T_136 = {io_dmi_reg_wdata[31:30],io_dmi_reg_wdata[28],io_dmi_reg_wdata[1]}; // @[Cat.scala 29:58] + reg [31:0] _T_116; // @[lib.scala 374:16] + wire sbreadonaddr_access = sbaddress0_reg_wren0 & sbcs_reg[20]; // @[dbg.scala 168:94] + wire _T_121 = ~io_dmi_reg_wr_en; // @[dbg.scala 169:45] + wire _T_122 = io_dmi_reg_en & _T_121; // @[dbg.scala 169:43] + wire _T_124 = _T_122 & _T_26; // @[dbg.scala 169:63] + wire sbreadondata_access = _T_124 & sbcs_reg[15]; // @[dbg.scala 169:95] + wire _T_128 = io_dmi_reg_addr == 7'h10; // @[dbg.scala 171:41] + wire _T_129 = _T_128 & io_dmi_reg_en; // @[dbg.scala 171:54] + wire dmcontrol_wren = _T_129 & io_dmi_reg_wr_en; // @[dbg.scala 171:70] + wire [3:0] _T_134 = {io_dmi_reg_wdata[31:30],io_dmi_reg_wdata[28],io_dmi_reg_wdata[1]}; // @[Cat.scala 29:58] reg [3:0] dm_temp; // @[Reg.scala 27:20] reg dm_temp_0; // @[Reg.scala 27:20] - wire [27:0] _T_143 = {26'h0,dm_temp[0],dm_temp_0}; // @[Cat.scala 29:58] - wire [3:0] _T_145 = {dm_temp[3:2],1'h0,dm_temp[1]}; // @[Cat.scala 29:58] - reg dmcontrol_wren_Q; // @[dbg.scala 188:12] - wire [1:0] _T_147 = dmstatus_havereset ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_149 = dmstatus_resumeack ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_151 = dmstatus_unavail ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_153 = dmstatus_running ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_155 = dmstatus_halted ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [11:0] _T_159 = {_T_153,_T_155,1'h1,7'h2}; // @[Cat.scala 29:58] - wire [19:0] _T_163 = {12'h0,_T_147,_T_149,2'h0,_T_151}; // @[Cat.scala 29:58] - wire _T_165 = dbg_state == 3'h6; // @[dbg.scala 193:44] - wire _T_166 = _T_165 & io_dec_tlu_resume_ack; // @[dbg.scala 193:66] - wire _T_168 = ~dmcontrol_reg[30]; // @[dbg.scala 193:113] - wire _T_169 = dmstatus_resumeack & _T_168; // @[dbg.scala 193:111] - wire dmstatus_resumeack_wren = _T_166 | _T_169; // @[dbg.scala 193:90] - wire _T_173 = _T_130 & io_dmi_reg_wdata[1]; // @[dbg.scala 195:63] - wire _T_174 = _T_173 & io_dmi_reg_en; // @[dbg.scala 195:85] - wire dmstatus_havereset_wren = _T_174 & io_dmi_reg_wr_en; // @[dbg.scala 195:101] - wire _T_177 = _T_130 & io_dmi_reg_wdata[28]; // @[dbg.scala 196:62] - wire _T_178 = _T_177 & io_dmi_reg_en; // @[dbg.scala 196:85] - wire dmstatus_havereset_rst = _T_178 & io_dmi_reg_wr_en; // @[dbg.scala 196:101] - wire _T_180 = ~reset; // @[dbg.scala 198:43] - wire _T_183 = dmstatus_unavail | dmstatus_halted; // @[dbg.scala 199:42] - reg _T_185; // @[Reg.scala 27:20] - wire _T_186 = ~io_dec_tlu_mpc_halted_only; // @[dbg.scala 205:37] - reg _T_188; // @[dbg.scala 205:12] - wire _T_189 = dmstatus_havereset_wren | dmstatus_havereset; // @[dbg.scala 209:16] - wire _T_190 = ~dmstatus_havereset_rst; // @[dbg.scala 209:72] - reg _T_192; // @[dbg.scala 209:12] + wire [27:0] _T_141 = {26'h0,dm_temp[0],dm_temp_0}; // @[Cat.scala 29:58] + wire [3:0] _T_143 = {dm_temp[3:2],1'h0,dm_temp[1]}; // @[Cat.scala 29:58] + reg dmcontrol_wren_Q; // @[dbg.scala 186:12] + wire [1:0] _T_145 = dmstatus_havereset ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_147 = dmstatus_resumeack ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_149 = dmstatus_unavail ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_151 = dmstatus_running ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_153 = dmstatus_halted ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [11:0] _T_157 = {_T_151,_T_153,1'h1,7'h2}; // @[Cat.scala 29:58] + wire [19:0] _T_161 = {12'h0,_T_145,_T_147,2'h0,_T_149}; // @[Cat.scala 29:58] + wire _T_163 = dbg_state == 3'h6; // @[dbg.scala 191:44] + wire _T_164 = _T_163 & io_dec_tlu_resume_ack; // @[dbg.scala 191:66] + wire _T_166 = ~dmcontrol_reg[30]; // @[dbg.scala 191:113] + wire _T_167 = dmstatus_resumeack & _T_166; // @[dbg.scala 191:111] + wire dmstatus_resumeack_wren = _T_164 | _T_167; // @[dbg.scala 191:90] + wire _T_171 = _T_128 & io_dmi_reg_wdata[1]; // @[dbg.scala 193:63] + wire _T_172 = _T_171 & io_dmi_reg_en; // @[dbg.scala 193:85] + wire dmstatus_havereset_wren = _T_172 & io_dmi_reg_wr_en; // @[dbg.scala 193:101] + wire _T_175 = _T_128 & io_dmi_reg_wdata[28]; // @[dbg.scala 194:62] + wire _T_176 = _T_175 & io_dmi_reg_en; // @[dbg.scala 194:85] + wire dmstatus_havereset_rst = _T_176 & io_dmi_reg_wr_en; // @[dbg.scala 194:101] + wire _T_178 = ~reset; // @[dbg.scala 196:43] + wire _T_181 = dmstatus_unavail | dmstatus_halted; // @[dbg.scala 197:42] + reg _T_183; // @[Reg.scala 27:20] + wire _T_184 = ~io_dec_tlu_mpc_halted_only; // @[dbg.scala 203:37] + reg _T_186; // @[dbg.scala 203:12] + wire _T_187 = dmstatus_havereset_wren | dmstatus_havereset; // @[dbg.scala 207:16] + wire _T_188 = ~dmstatus_havereset_rst; // @[dbg.scala 207:72] + reg _T_190; // @[dbg.scala 207:12] wire [31:0] haltsum0_reg = {31'h0,dmstatus_halted}; // @[Cat.scala 29:58] wire [31:0] abstractcs_reg; - wire _T_194 = abstractcs_reg[12] & io_dmi_reg_en; // @[dbg.scala 215:50] - wire _T_195 = io_dmi_reg_addr == 7'h16; // @[dbg.scala 215:106] - wire _T_196 = io_dmi_reg_addr == 7'h17; // @[dbg.scala 215:138] - wire _T_197 = _T_195 | _T_196; // @[dbg.scala 215:119] - wire _T_198 = io_dmi_reg_wr_en & _T_197; // @[dbg.scala 215:86] - wire _T_199 = io_dmi_reg_addr == 7'h4; // @[dbg.scala 215:171] - wire _T_200 = _T_198 | _T_199; // @[dbg.scala 215:152] - wire abstractcs_error_sel0 = _T_194 & _T_200; // @[dbg.scala 215:66] - wire _T_203 = _T_83 & _T_196; // @[dbg.scala 216:64] - wire _T_205 = io_dmi_reg_wdata[31:24] == 8'h0; // @[dbg.scala 216:126] - wire _T_207 = io_dmi_reg_wdata[31:24] == 8'h2; // @[dbg.scala 216:163] - wire _T_208 = _T_205 | _T_207; // @[dbg.scala 216:135] - wire _T_209 = ~_T_208; // @[dbg.scala 216:98] - wire abstractcs_error_sel1 = _T_203 & _T_209; // @[dbg.scala 216:96] - wire abstractcs_error_sel2 = io_core_dbg_cmd_done & io_core_dbg_cmd_fail; // @[dbg.scala 217:52] - wire _T_214 = ~dmstatus_reg[9]; // @[dbg.scala 218:98] - wire abstractcs_error_sel3 = _T_203 & _T_214; // @[dbg.scala 218:96] - wire _T_216 = _T_196 & io_dmi_reg_en; // @[dbg.scala 219:61] - wire _T_217 = _T_216 & io_dmi_reg_wr_en; // @[dbg.scala 219:77] - wire _T_219 = io_dmi_reg_wdata[22:20] != 3'h2; // @[dbg.scala 220:32] - wire _T_223 = |data1_reg[1:0]; // @[dbg.scala 220:111] - wire _T_224 = _T_207 & _T_223; // @[dbg.scala 220:92] - wire _T_225 = _T_219 | _T_224; // @[dbg.scala 220:51] - wire abstractcs_error_sel4 = _T_217 & _T_225; // @[dbg.scala 219:96] - wire _T_227 = _T_195 & io_dmi_reg_en; // @[dbg.scala 222:61] - wire abstractcs_error_sel5 = _T_227 & io_dmi_reg_wr_en; // @[dbg.scala 222:77] - wire _T_228 = abstractcs_error_sel0 | abstractcs_error_sel1; // @[dbg.scala 223:54] - wire _T_229 = _T_228 | abstractcs_error_sel2; // @[dbg.scala 223:78] - wire _T_230 = _T_229 | abstractcs_error_sel3; // @[dbg.scala 223:102] - wire _T_231 = _T_230 | abstractcs_error_sel4; // @[dbg.scala 223:126] - wire abstractcs_error_selor = _T_231 | abstractcs_error_sel5; // @[dbg.scala 223:150] - wire [2:0] _T_233 = abstractcs_error_sel0 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_234 = _T_233 & 3'h1; // @[dbg.scala 224:62] - wire [2:0] _T_236 = abstractcs_error_sel1 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_237 = _T_236 & 3'h2; // @[dbg.scala 225:37] - wire [2:0] _T_238 = _T_234 | _T_237; // @[dbg.scala 224:79] - wire [2:0] _T_240 = abstractcs_error_sel2 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_241 = _T_240 & 3'h3; // @[dbg.scala 226:37] - wire [2:0] _T_242 = _T_238 | _T_241; // @[dbg.scala 225:54] - wire [2:0] _T_244 = abstractcs_error_sel3 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_245 = _T_244 & 3'h4; // @[dbg.scala 227:37] - wire [2:0] _T_246 = _T_242 | _T_245; // @[dbg.scala 226:54] - wire [2:0] _T_248 = abstractcs_error_sel4 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_250 = _T_246 | _T_248; // @[dbg.scala 227:54] - wire [2:0] _T_252 = abstractcs_error_sel5 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_254 = ~io_dmi_reg_wdata[10:8]; // @[dbg.scala 229:40] - wire [2:0] _T_255 = _T_252 & _T_254; // @[dbg.scala 229:37] - wire [2:0] _T_257 = _T_255 & abstractcs_reg[10:8]; // @[dbg.scala 229:75] - wire [2:0] _T_258 = _T_250 | _T_257; // @[dbg.scala 228:54] - wire _T_259 = ~abstractcs_error_selor; // @[dbg.scala 230:15] - wire [2:0] _T_261 = _T_259 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_263 = _T_261 & abstractcs_reg[10:8]; // @[dbg.scala 230:50] + wire _T_192 = abstractcs_reg[12] & io_dmi_reg_en; // @[dbg.scala 213:50] + wire _T_193 = io_dmi_reg_addr == 7'h16; // @[dbg.scala 213:106] + wire _T_194 = io_dmi_reg_addr == 7'h17; // @[dbg.scala 213:138] + wire _T_195 = _T_193 | _T_194; // @[dbg.scala 213:119] + wire _T_196 = io_dmi_reg_wr_en & _T_195; // @[dbg.scala 213:86] + wire _T_197 = io_dmi_reg_addr == 7'h4; // @[dbg.scala 213:171] + wire _T_198 = _T_196 | _T_197; // @[dbg.scala 213:152] + wire abstractcs_error_sel0 = _T_192 & _T_198; // @[dbg.scala 213:66] + wire _T_201 = _T_81 & _T_194; // @[dbg.scala 214:64] + wire _T_203 = io_dmi_reg_wdata[31:24] == 8'h0; // @[dbg.scala 214:126] + wire _T_205 = io_dmi_reg_wdata[31:24] == 8'h2; // @[dbg.scala 214:163] + wire _T_206 = _T_203 | _T_205; // @[dbg.scala 214:135] + wire _T_207 = ~_T_206; // @[dbg.scala 214:98] + wire abstractcs_error_sel1 = _T_201 & _T_207; // @[dbg.scala 214:96] + wire abstractcs_error_sel2 = io_core_dbg_cmd_done & io_core_dbg_cmd_fail; // @[dbg.scala 215:52] + wire _T_212 = ~dmstatus_reg[9]; // @[dbg.scala 216:98] + wire abstractcs_error_sel3 = _T_201 & _T_212; // @[dbg.scala 216:96] + wire _T_214 = _T_194 & io_dmi_reg_en; // @[dbg.scala 217:61] + wire _T_215 = _T_214 & io_dmi_reg_wr_en; // @[dbg.scala 217:77] + wire _T_217 = io_dmi_reg_wdata[22:20] != 3'h2; // @[dbg.scala 218:32] + wire _T_221 = |data1_reg[1:0]; // @[dbg.scala 218:111] + wire _T_222 = _T_205 & _T_221; // @[dbg.scala 218:92] + wire _T_223 = _T_217 | _T_222; // @[dbg.scala 218:51] + wire abstractcs_error_sel4 = _T_215 & _T_223; // @[dbg.scala 217:96] + wire _T_225 = _T_193 & io_dmi_reg_en; // @[dbg.scala 220:61] + wire abstractcs_error_sel5 = _T_225 & io_dmi_reg_wr_en; // @[dbg.scala 220:77] + wire _T_226 = abstractcs_error_sel0 | abstractcs_error_sel1; // @[dbg.scala 221:54] + wire _T_227 = _T_226 | abstractcs_error_sel2; // @[dbg.scala 221:78] + wire _T_228 = _T_227 | abstractcs_error_sel3; // @[dbg.scala 221:102] + wire _T_229 = _T_228 | abstractcs_error_sel4; // @[dbg.scala 221:126] + wire abstractcs_error_selor = _T_229 | abstractcs_error_sel5; // @[dbg.scala 221:150] + wire [2:0] _T_231 = abstractcs_error_sel0 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_232 = _T_231 & 3'h1; // @[dbg.scala 222:62] + wire [2:0] _T_234 = abstractcs_error_sel1 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_235 = _T_234 & 3'h2; // @[dbg.scala 223:37] + wire [2:0] _T_236 = _T_232 | _T_235; // @[dbg.scala 222:79] + wire [2:0] _T_238 = abstractcs_error_sel2 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_239 = _T_238 & 3'h3; // @[dbg.scala 224:37] + wire [2:0] _T_240 = _T_236 | _T_239; // @[dbg.scala 223:54] + wire [2:0] _T_242 = abstractcs_error_sel3 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_243 = _T_242 & 3'h4; // @[dbg.scala 225:37] + wire [2:0] _T_244 = _T_240 | _T_243; // @[dbg.scala 224:54] + wire [2:0] _T_246 = abstractcs_error_sel4 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_248 = _T_244 | _T_246; // @[dbg.scala 225:54] + wire [2:0] _T_250 = abstractcs_error_sel5 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_252 = ~io_dmi_reg_wdata[10:8]; // @[dbg.scala 227:40] + wire [2:0] _T_253 = _T_250 & _T_252; // @[dbg.scala 227:37] + wire [2:0] _T_255 = _T_253 & abstractcs_reg[10:8]; // @[dbg.scala 227:75] + wire [2:0] _T_256 = _T_248 | _T_255; // @[dbg.scala 226:54] + wire _T_257 = ~abstractcs_error_selor; // @[dbg.scala 228:15] + wire [2:0] _T_259 = _T_257 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_261 = _T_259 & abstractcs_reg[10:8]; // @[dbg.scala 228:50] reg abs_temp_12; // @[Reg.scala 27:20] - reg [2:0] abs_temp_10_8; // @[dbg.scala 237:12] - wire [10:0] _T_265 = {abs_temp_10_8,8'h2}; // @[Cat.scala 29:58] - wire [20:0] _T_267 = {19'h0,abs_temp_12,1'h0}; // @[Cat.scala 29:58] - wire _T_272 = dbg_state == 3'h2; // @[dbg.scala 242:100] - wire command_wren = _T_217 & _T_272; // @[dbg.scala 242:87] - wire [19:0] _T_276 = {3'h0,io_dmi_reg_wdata[16:0]}; // @[Cat.scala 29:58] - wire [11:0] _T_278 = {io_dmi_reg_wdata[31:24],1'h0,io_dmi_reg_wdata[22:20]}; // @[Cat.scala 29:58] + reg [2:0] abs_temp_10_8; // @[dbg.scala 235:12] + wire [10:0] _T_263 = {abs_temp_10_8,8'h2}; // @[Cat.scala 29:58] + wire [20:0] _T_265 = {19'h0,abs_temp_12,1'h0}; // @[Cat.scala 29:58] + wire _T_270 = dbg_state == 3'h2; // @[dbg.scala 240:100] + wire command_wren = _T_215 & _T_270; // @[dbg.scala 240:87] + wire [19:0] _T_274 = {3'h0,io_dmi_reg_wdata[16:0]}; // @[Cat.scala 29:58] + wire [11:0] _T_276 = {io_dmi_reg_wdata[31:24],1'h0,io_dmi_reg_wdata[22:20]}; // @[Cat.scala 29:58] wire rvclkhdr_5_io_l1clk; // @[lib.scala 368:23] wire rvclkhdr_5_io_clk; // @[lib.scala 368:23] wire rvclkhdr_5_io_en; // @[lib.scala 368:23] wire rvclkhdr_5_io_scan_mode; // @[lib.scala 368:23] reg [31:0] command_reg; // @[lib.scala 374:16] - wire _T_281 = _T_83 & _T_199; // @[dbg.scala 248:58] - wire data0_reg_wren0 = _T_281 & _T_272; // @[dbg.scala 248:89] - wire _T_283 = dbg_state == 3'h4; // @[dbg.scala 249:59] - wire _T_284 = io_core_dbg_cmd_done & _T_283; // @[dbg.scala 249:46] - wire _T_286 = ~command_reg[16]; // @[dbg.scala 249:83] - wire data0_reg_wren1 = _T_284 & _T_286; // @[dbg.scala 249:81] - wire [31:0] _T_288 = data0_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_289 = _T_288 & io_dmi_reg_wdata; // @[dbg.scala 252:45] - wire [31:0] _T_291 = data0_reg_wren1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_292 = _T_291 & io_core_dbg_rddata; // @[dbg.scala 252:92] + wire _T_279 = _T_81 & _T_197; // @[dbg.scala 246:58] + wire data0_reg_wren0 = _T_279 & _T_270; // @[dbg.scala 246:89] + wire _T_281 = dbg_state == 3'h4; // @[dbg.scala 247:59] + wire _T_282 = io_core_dbg_cmd_done & _T_281; // @[dbg.scala 247:46] + wire _T_284 = ~command_reg[16]; // @[dbg.scala 247:83] + wire data0_reg_wren1 = _T_282 & _T_284; // @[dbg.scala 247:81] + wire [31:0] _T_286 = data0_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_287 = _T_286 & io_dmi_reg_wdata; // @[dbg.scala 250:45] + wire [31:0] _T_289 = data0_reg_wren1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_290 = _T_289 & io_core_dbg_rddata; // @[dbg.scala 250:92] wire rvclkhdr_6_io_l1clk; // @[lib.scala 368:23] wire rvclkhdr_6_io_clk; // @[lib.scala 368:23] wire rvclkhdr_6_io_en; // @[lib.scala 368:23] wire rvclkhdr_6_io_scan_mode; // @[lib.scala 368:23] reg [31:0] data0_reg; // @[lib.scala 374:16] - wire _T_294 = io_dmi_reg_addr == 7'h5; // @[dbg.scala 257:77] - wire _T_295 = _T_83 & _T_294; // @[dbg.scala 257:58] - wire data1_reg_wren = _T_295 & _T_272; // @[dbg.scala 257:89] - wire [31:0] _T_298 = data1_reg_wren ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire _T_292 = io_dmi_reg_addr == 7'h5; // @[dbg.scala 255:77] + wire _T_293 = _T_81 & _T_292; // @[dbg.scala 255:58] + wire data1_reg_wren = _T_293 & _T_270; // @[dbg.scala 255:89] + wire [31:0] _T_296 = data1_reg_wren ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] wire rvclkhdr_7_io_l1clk; // @[lib.scala 368:23] wire rvclkhdr_7_io_clk; // @[lib.scala 368:23] wire rvclkhdr_7_io_en; // @[lib.scala 368:23] wire rvclkhdr_7_io_scan_mode; // @[lib.scala 368:23] - reg [31:0] _T_299; // @[lib.scala 374:16] + reg [31:0] _T_297; // @[lib.scala 374:16] wire [2:0] dbg_nxtstate; - wire _T_300 = 3'h0 == dbg_state; // @[Conditional.scala 37:30] - wire _T_302 = dmstatus_reg[9] | io_dec_tlu_mpc_halted_only; // @[dbg.scala 272:43] - wire [2:0] _T_303 = _T_302 ? 3'h2 : 3'h1; // @[dbg.scala 272:26] - wire _T_305 = ~io_dec_tlu_debug_mode; // @[dbg.scala 273:45] - wire _T_306 = dmcontrol_reg[31] & _T_305; // @[dbg.scala 273:43] - wire _T_308 = _T_306 | dmstatus_reg[9]; // @[dbg.scala 273:69] - wire _T_309 = _T_308 | io_dec_tlu_mpc_halted_only; // @[dbg.scala 273:87] - wire _T_312 = _T_309 & _T_17; // @[dbg.scala 273:117] - wire _T_316 = dmcontrol_reg[31] & _T_17; // @[dbg.scala 274:45] - wire _T_318 = 3'h1 == dbg_state; // @[Conditional.scala 37:30] - wire [2:0] _T_320 = dmcontrol_reg[1] ? 3'h0 : 3'h2; // @[dbg.scala 277:26] - wire _T_323 = dmstatus_reg[9] | dmcontrol_reg[1]; // @[dbg.scala 278:39] - wire _T_325 = dmcontrol_wren_Q & dmcontrol_reg[31]; // @[dbg.scala 279:44] - wire _T_328 = _T_325 & _T_17; // @[dbg.scala 279:64] - wire _T_330 = 3'h2 == dbg_state; // @[Conditional.scala 37:30] - wire _T_334 = dmstatus_reg[9] & _T_17; // @[dbg.scala 282:43] - wire _T_337 = ~dmcontrol_reg[31]; // @[dbg.scala 283:33] - wire _T_338 = dmcontrol_reg[30] & _T_337; // @[dbg.scala 283:31] - wire [2:0] _T_339 = _T_338 ? 3'h6 : 3'h3; // @[dbg.scala 283:12] - wire [2:0] _T_341 = dmcontrol_reg[31] ? 3'h1 : 3'h0; // @[dbg.scala 284:12] - wire [2:0] _T_342 = _T_334 ? _T_339 : _T_341; // @[dbg.scala 282:26] - wire _T_345 = dmstatus_reg[9] & dmcontrol_reg[30]; // @[dbg.scala 285:39] - wire _T_348 = _T_345 & _T_337; // @[dbg.scala 285:59] - wire _T_349 = _T_348 & dmcontrol_wren_Q; // @[dbg.scala 285:80] - wire _T_350 = _T_349 | command_wren; // @[dbg.scala 285:99] - wire _T_352 = _T_350 | dmcontrol_reg[1]; // @[dbg.scala 285:114] - wire _T_355 = ~_T_302; // @[dbg.scala 286:28] - wire _T_356 = _T_352 | _T_355; // @[dbg.scala 286:26] - wire _T_357 = dbg_nxtstate == 3'h3; // @[dbg.scala 287:60] - wire _T_358 = dbg_state_en & _T_357; // @[dbg.scala 287:44] - wire _T_359 = dbg_nxtstate == 3'h6; // @[dbg.scala 289:58] - wire _T_360 = dbg_state_en & _T_359; // @[dbg.scala 289:42] - wire _T_368 = 3'h3 == dbg_state; // @[Conditional.scala 37:30] - wire _T_371 = |abstractcs_reg[10:8]; // @[dbg.scala 293:85] - wire [2:0] _T_372 = _T_371 ? 3'h5 : 3'h4; // @[dbg.scala 293:62] - wire [2:0] _T_373 = dmcontrol_reg[1] ? 3'h0 : _T_372; // @[dbg.scala 293:26] - wire _T_376 = io_dbg_dec_dbg_ib_dbg_cmd_valid | _T_371; // @[dbg.scala 294:55] - wire _T_378 = _T_376 | dmcontrol_reg[1]; // @[dbg.scala 294:83] - wire _T_385 = 3'h4 == dbg_state; // @[Conditional.scala 37:30] - wire [2:0] _T_387 = dmcontrol_reg[1] ? 3'h0 : 3'h5; // @[dbg.scala 298:26] - wire _T_389 = io_core_dbg_cmd_done | dmcontrol_reg[1]; // @[dbg.scala 299:44] - wire _T_396 = 3'h5 == dbg_state; // @[Conditional.scala 37:30] - wire _T_405 = 3'h6 == dbg_state; // @[Conditional.scala 37:30] - wire _T_408 = dmstatus_reg[17] | dmcontrol_reg[1]; // @[dbg.scala 311:40] - wire _GEN_10 = _T_405 & _T_408; // @[Conditional.scala 39:67] - wire _GEN_11 = _T_405 & _T_328; // @[Conditional.scala 39:67] - wire [2:0] _GEN_12 = _T_396 ? _T_320 : 3'h0; // @[Conditional.scala 39:67] - wire _GEN_13 = _T_396 | _GEN_10; // @[Conditional.scala 39:67] - wire _GEN_14 = _T_396 & dbg_state_en; // @[Conditional.scala 39:67] - wire _GEN_16 = _T_396 ? _T_328 : _GEN_11; // @[Conditional.scala 39:67] - wire [2:0] _GEN_17 = _T_385 ? _T_387 : _GEN_12; // @[Conditional.scala 39:67] - wire _GEN_18 = _T_385 ? _T_389 : _GEN_13; // @[Conditional.scala 39:67] - wire _GEN_19 = _T_385 ? _T_328 : _GEN_16; // @[Conditional.scala 39:67] - wire _GEN_20 = _T_385 ? 1'h0 : _GEN_14; // @[Conditional.scala 39:67] - wire [2:0] _GEN_22 = _T_368 ? _T_373 : _GEN_17; // @[Conditional.scala 39:67] - wire _GEN_23 = _T_368 ? _T_378 : _GEN_18; // @[Conditional.scala 39:67] - wire _GEN_24 = _T_368 ? _T_328 : _GEN_19; // @[Conditional.scala 39:67] - wire _GEN_25 = _T_368 ? 1'h0 : _GEN_20; // @[Conditional.scala 39:67] - wire [2:0] _GEN_27 = _T_330 ? _T_342 : _GEN_22; // @[Conditional.scala 39:67] - wire _GEN_28 = _T_330 ? _T_356 : _GEN_23; // @[Conditional.scala 39:67] - wire _GEN_29 = _T_330 ? _T_358 : _GEN_25; // @[Conditional.scala 39:67] - wire _GEN_31 = _T_330 & _T_360; // @[Conditional.scala 39:67] - wire _GEN_32 = _T_330 ? _T_328 : _GEN_24; // @[Conditional.scala 39:67] - wire [2:0] _GEN_33 = _T_318 ? _T_320 : _GEN_27; // @[Conditional.scala 39:67] - wire _GEN_34 = _T_318 ? _T_323 : _GEN_28; // @[Conditional.scala 39:67] - wire _GEN_35 = _T_318 ? _T_328 : _GEN_32; // @[Conditional.scala 39:67] - wire _GEN_36 = _T_318 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67] - wire _GEN_38 = _T_318 ? 1'h0 : _GEN_31; // @[Conditional.scala 39:67] - wire [31:0] _T_417 = _T_199 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_418 = _T_417 & data0_reg; // @[dbg.scala 315:71] - wire [31:0] _T_421 = _T_294 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_422 = _T_421 & data1_reg; // @[dbg.scala 315:122] - wire [31:0] _T_423 = _T_418 | _T_422; // @[dbg.scala 315:83] - wire [31:0] _T_426 = _T_130 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_427 = _T_426 & dmcontrol_reg; // @[dbg.scala 316:43] - wire [31:0] _T_428 = _T_423 | _T_427; // @[dbg.scala 315:134] - wire _T_429 = io_dmi_reg_addr == 7'h11; // @[dbg.scala 316:86] - wire [31:0] _T_431 = _T_429 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_432 = _T_431 & dmstatus_reg; // @[dbg.scala 316:99] - wire [31:0] _T_433 = _T_428 | _T_432; // @[dbg.scala 316:59] - wire [31:0] _T_436 = _T_195 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_437 = _T_436 & abstractcs_reg; // @[dbg.scala 317:43] - wire [31:0] _T_438 = _T_433 | _T_437; // @[dbg.scala 316:114] - wire [31:0] _T_441 = _T_196 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_442 = _T_441 & command_reg; // @[dbg.scala 317:100] - wire [31:0] _T_443 = _T_438 | _T_442; // @[dbg.scala 317:60] - wire _T_444 = io_dmi_reg_addr == 7'h40; // @[dbg.scala 318:30] - wire [31:0] _T_446 = _T_444 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_447 = _T_446 & haltsum0_reg; // @[dbg.scala 318:43] - wire [31:0] _T_448 = _T_443 | _T_447; // @[dbg.scala 317:114] - wire [31:0] _T_451 = _T_19 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_452 = _T_451 & sbcs_reg; // @[dbg.scala 318:98] - wire [31:0] _T_453 = _T_448 | _T_452; // @[dbg.scala 318:58] - wire [31:0] _T_456 = _T_27 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_457 = _T_456 & sbaddress0_reg; // @[dbg.scala 319:43] - wire [31:0] _T_458 = _T_453 | _T_457; // @[dbg.scala 318:109] - wire [31:0] _T_461 = _T_28 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_462 = _T_461 & sbdata0_reg; // @[dbg.scala 319:100] - wire [31:0] _T_463 = _T_458 | _T_462; // @[dbg.scala 319:60] - wire [31:0] _T_466 = _T_30 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_467 = _T_466 & sbdata1_reg; // @[dbg.scala 320:43] - wire [31:0] dmi_reg_rdata_din = _T_463 | _T_467; // @[dbg.scala 319:114] - reg [2:0] _T_468; // @[Reg.scala 27:20] - reg [31:0] _T_469; // @[Reg.scala 27:20] - wire _T_471 = command_reg[31:24] == 8'h2; // @[dbg.scala 331:62] - wire [31:0] _T_473 = {data1_reg[31:2],2'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_475 = {20'h0,command_reg[11:0]}; // @[Cat.scala 29:58] - wire _T_478 = dbg_state == 3'h3; // @[dbg.scala 333:50] - wire _T_481 = ~_T_371; // @[dbg.scala 333:75] - wire _T_482 = _T_478 & _T_481; // @[dbg.scala 333:73] - wire _T_490 = command_reg[15:12] == 4'h0; // @[dbg.scala 335:122] - wire [1:0] _T_491 = {1'h0,_T_490}; // @[Cat.scala 29:58] - wire _T_502 = 4'h0 == sb_state; // @[Conditional.scala 37:30] - wire _T_504 = sbdata0_reg_wren0 | sbreadondata_access; // @[dbg.scala 350:39] - wire _T_505 = _T_504 | sbreadonaddr_access; // @[dbg.scala 350:61] - wire _T_507 = |io_dmi_reg_wdata[14:12]; // @[dbg.scala 353:65] - wire _T_508 = sbcs_wren & _T_507; // @[dbg.scala 353:38] - wire [2:0] _T_510 = ~io_dmi_reg_wdata[14:12]; // @[dbg.scala 354:27] - wire [2:0] _T_512 = _T_510 & sbcs_reg[14:12]; // @[dbg.scala 354:53] - wire _T_513 = 4'h1 == sb_state; // @[Conditional.scala 37:30] - wire _T_514 = sbcs_unaligned | sbcs_illegal_size; // @[dbg.scala 357:41] - wire _T_516 = io_dbg_bus_clk_en | sbcs_unaligned; // @[dbg.scala 358:40] - wire _T_517 = _T_516 | sbcs_illegal_size; // @[dbg.scala 358:57] - wire _T_520 = 4'h2 == sb_state; // @[Conditional.scala 37:30] - wire _T_527 = 4'h3 == sb_state; // @[Conditional.scala 37:30] - wire _T_528 = sb_bus_cmd_read & io_dbg_bus_clk_en; // @[dbg.scala 370:38] - wire _T_529 = 4'h4 == sb_state; // @[Conditional.scala 37:30] - wire _T_530 = sb_bus_cmd_write_addr & sb_bus_cmd_write_data; // @[dbg.scala 373:48] - wire _T_533 = sb_bus_cmd_write_addr | sb_bus_cmd_write_data; // @[dbg.scala 374:45] - wire _T_534 = _T_533 & io_dbg_bus_clk_en; // @[dbg.scala 374:70] - wire _T_535 = 4'h5 == sb_state; // @[Conditional.scala 37:30] - wire _T_536 = sb_bus_cmd_write_addr & io_dbg_bus_clk_en; // @[dbg.scala 378:44] - wire _T_537 = 4'h6 == sb_state; // @[Conditional.scala 37:30] - wire _T_538 = sb_bus_cmd_write_data & io_dbg_bus_clk_en; // @[dbg.scala 382:44] - wire _T_539 = 4'h7 == sb_state; // @[Conditional.scala 37:30] - wire _T_540 = sb_bus_rsp_read & io_dbg_bus_clk_en; // @[dbg.scala 386:38] - wire _T_541 = sb_state_en & sb_bus_rsp_error; // @[dbg.scala 387:40] - wire _T_542 = 4'h8 == sb_state; // @[Conditional.scala 37:30] - wire _T_543 = sb_bus_rsp_write & io_dbg_bus_clk_en; // @[dbg.scala 392:39] - wire _T_545 = 4'h9 == sb_state; // @[Conditional.scala 37:30] - wire _GEN_50 = _T_545 & sbcs_reg[16]; // @[Conditional.scala 39:67] - wire _GEN_52 = _T_542 ? _T_543 : _T_545; // @[Conditional.scala 39:67] - wire _GEN_53 = _T_542 & _T_541; // @[Conditional.scala 39:67] - wire _GEN_55 = _T_542 ? 1'h0 : _T_545; // @[Conditional.scala 39:67] - wire _GEN_57 = _T_542 ? 1'h0 : _GEN_50; // @[Conditional.scala 39:67] - wire _GEN_59 = _T_539 ? _T_540 : _GEN_52; // @[Conditional.scala 39:67] - wire _GEN_60 = _T_539 ? _T_541 : _GEN_53; // @[Conditional.scala 39:67] - wire _GEN_62 = _T_539 ? 1'h0 : _GEN_55; // @[Conditional.scala 39:67] - wire _GEN_64 = _T_539 ? 1'h0 : _GEN_57; // @[Conditional.scala 39:67] - wire _GEN_66 = _T_537 ? _T_538 : _GEN_59; // @[Conditional.scala 39:67] - wire _GEN_67 = _T_537 ? 1'h0 : _GEN_60; // @[Conditional.scala 39:67] - wire _GEN_69 = _T_537 ? 1'h0 : _GEN_62; // @[Conditional.scala 39:67] - wire _GEN_71 = _T_537 ? 1'h0 : _GEN_64; // @[Conditional.scala 39:67] - wire _GEN_73 = _T_535 ? _T_536 : _GEN_66; // @[Conditional.scala 39:67] - wire _GEN_74 = _T_535 ? 1'h0 : _GEN_67; // @[Conditional.scala 39:67] - wire _GEN_76 = _T_535 ? 1'h0 : _GEN_69; // @[Conditional.scala 39:67] - wire _GEN_78 = _T_535 ? 1'h0 : _GEN_71; // @[Conditional.scala 39:67] - wire _GEN_80 = _T_529 ? _T_534 : _GEN_73; // @[Conditional.scala 39:67] - wire _GEN_81 = _T_529 ? 1'h0 : _GEN_74; // @[Conditional.scala 39:67] - wire _GEN_83 = _T_529 ? 1'h0 : _GEN_76; // @[Conditional.scala 39:67] - wire _GEN_85 = _T_529 ? 1'h0 : _GEN_78; // @[Conditional.scala 39:67] - wire _GEN_87 = _T_527 ? _T_528 : _GEN_80; // @[Conditional.scala 39:67] - wire _GEN_88 = _T_527 ? 1'h0 : _GEN_81; // @[Conditional.scala 39:67] - wire _GEN_90 = _T_527 ? 1'h0 : _GEN_83; // @[Conditional.scala 39:67] - wire _GEN_92 = _T_527 ? 1'h0 : _GEN_85; // @[Conditional.scala 39:67] - wire _GEN_94 = _T_520 ? _T_517 : _GEN_87; // @[Conditional.scala 39:67] - wire _GEN_95 = _T_520 ? _T_514 : _GEN_88; // @[Conditional.scala 39:67] - wire _GEN_97 = _T_520 ? 1'h0 : _GEN_90; // @[Conditional.scala 39:67] - wire _GEN_99 = _T_520 ? 1'h0 : _GEN_92; // @[Conditional.scala 39:67] - wire _GEN_101 = _T_513 ? _T_517 : _GEN_94; // @[Conditional.scala 39:67] - wire _GEN_102 = _T_513 ? _T_514 : _GEN_95; // @[Conditional.scala 39:67] - wire _GEN_104 = _T_513 ? 1'h0 : _GEN_97; // @[Conditional.scala 39:67] - wire _GEN_106 = _T_513 ? 1'h0 : _GEN_99; // @[Conditional.scala 39:67] - reg [3:0] _T_547; // @[Reg.scala 27:20] - wire _T_554 = |io_sb_axi_r_bits_resp; // @[dbg.scala 413:69] - wire _T_555 = sb_bus_rsp_read & _T_554; // @[dbg.scala 413:39] - wire _T_557 = |io_sb_axi_b_bits_resp; // @[dbg.scala 413:122] - wire _T_558 = sb_bus_rsp_write & _T_557; // @[dbg.scala 413:92] - wire _T_560 = sb_state == 4'h4; // @[dbg.scala 414:36] - wire _T_561 = sb_state == 4'h5; // @[dbg.scala 414:71] - wire _T_567 = sb_state == 4'h6; // @[dbg.scala 425:70] - wire [63:0] _T_573 = _T_62 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12] - wire [63:0] _T_577 = {sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0]}; // @[Cat.scala 29:58] - wire [63:0] _T_578 = _T_573 & _T_577; // @[dbg.scala 426:65] - wire [63:0] _T_582 = _T_47 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12] - wire [63:0] _T_585 = {sbdata0_reg[15:0],sbdata0_reg[15:0],sbdata0_reg[15:0],sbdata0_reg[15:0]}; // @[Cat.scala 29:58] - wire [63:0] _T_586 = _T_582 & _T_585; // @[dbg.scala 426:138] - wire [63:0] _T_587 = _T_578 | _T_586; // @[dbg.scala 426:96] - wire [63:0] _T_591 = _T_51 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12] - wire [63:0] _T_593 = {sbdata0_reg,sbdata0_reg}; // @[Cat.scala 29:58] - wire [63:0] _T_594 = _T_591 & _T_593; // @[dbg.scala 427:45] - wire [63:0] _T_595 = _T_587 | _T_594; // @[dbg.scala 426:168] - wire [63:0] _T_599 = _T_57 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12] - wire [63:0] _T_602 = {sbdata1_reg,sbdata0_reg}; // @[Cat.scala 29:58] - wire [63:0] _T_603 = _T_599 & _T_602; // @[dbg.scala 427:119] - wire [7:0] _T_608 = _T_62 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [14:0] _T_610 = 15'h1 << sbaddress0_reg[2:0]; // @[dbg.scala 429:82] - wire [14:0] _GEN_115 = {{7'd0}, _T_608}; // @[dbg.scala 429:67] - wire [14:0] _T_611 = _GEN_115 & _T_610; // @[dbg.scala 429:67] - wire [7:0] _T_615 = _T_47 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_617 = {sbaddress0_reg[2:1],1'h0}; // @[Cat.scala 29:58] - wire [14:0] _T_618 = 15'h3 << _T_617; // @[dbg.scala 430:59] - wire [14:0] _GEN_116 = {{7'd0}, _T_615}; // @[dbg.scala 430:44] - wire [14:0] _T_619 = _GEN_116 & _T_618; // @[dbg.scala 430:44] - wire [14:0] _T_620 = _T_611 | _T_619; // @[dbg.scala 429:107] - wire [7:0] _T_624 = _T_51 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_626 = {sbaddress0_reg[2],2'h0}; // @[Cat.scala 29:58] - wire [14:0] _T_627 = 15'hf << _T_626; // @[dbg.scala 431:59] - wire [14:0] _GEN_117 = {{7'd0}, _T_624}; // @[dbg.scala 431:44] - wire [14:0] _T_628 = _GEN_117 & _T_627; // @[dbg.scala 431:44] - wire [14:0] _T_629 = _T_620 | _T_628; // @[dbg.scala 430:97] - wire [7:0] _T_633 = _T_57 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [14:0] _GEN_118 = {{7'd0}, _T_633}; // @[dbg.scala 431:100] - wire [14:0] _T_635 = _T_629 | _GEN_118; // @[dbg.scala 431:100] - wire [3:0] _GEN_119 = {{1'd0}, sbaddress0_reg[2:0]}; // @[dbg.scala 448:99] - wire [6:0] _T_646 = 4'h8 * _GEN_119; // @[dbg.scala 448:99] - wire [63:0] _T_647 = io_sb_axi_r_bits_data >> _T_646; // @[dbg.scala 448:92] - wire [63:0] _T_648 = _T_647 & 64'hff; // @[dbg.scala 448:123] - wire [63:0] _T_649 = _T_573 & _T_648; // @[dbg.scala 448:59] - wire [4:0] _GEN_120 = {{3'd0}, sbaddress0_reg[2:1]}; // @[dbg.scala 449:86] - wire [6:0] _T_656 = 5'h10 * _GEN_120; // @[dbg.scala 449:86] - wire [63:0] _T_657 = io_sb_axi_r_bits_data >> _T_656; // @[dbg.scala 449:78] - wire [63:0] _T_658 = _T_657 & 64'hffff; // @[dbg.scala 449:110] - wire [63:0] _T_659 = _T_582 & _T_658; // @[dbg.scala 449:45] - wire [63:0] _T_660 = _T_649 | _T_659; // @[dbg.scala 448:140] - wire [5:0] _GEN_121 = {{5'd0}, sbaddress0_reg[2]}; // @[dbg.scala 450:86] - wire [6:0] _T_667 = 6'h20 * _GEN_121; // @[dbg.scala 450:86] - wire [63:0] _T_668 = io_sb_axi_r_bits_data >> _T_667; // @[dbg.scala 450:78] - wire [63:0] _T_669 = _T_668 & 64'hffffffff; // @[dbg.scala 450:107] - wire [63:0] _T_670 = _T_591 & _T_669; // @[dbg.scala 450:45] - wire [63:0] _T_671 = _T_660 | _T_670; // @[dbg.scala 449:129] - wire [63:0] _T_677 = _T_599 & io_sb_axi_r_bits_data; // @[dbg.scala 451:45] + wire _T_298 = 3'h0 == dbg_state; // @[Conditional.scala 37:30] + wire _T_300 = dmstatus_reg[9] | io_dec_tlu_mpc_halted_only; // @[dbg.scala 270:43] + wire [2:0] _T_301 = _T_300 ? 3'h2 : 3'h1; // @[dbg.scala 270:26] + wire _T_303 = ~io_dec_tlu_debug_mode; // @[dbg.scala 271:45] + wire _T_304 = dmcontrol_reg[31] & _T_303; // @[dbg.scala 271:43] + wire _T_306 = _T_304 | dmstatus_reg[9]; // @[dbg.scala 271:69] + wire _T_307 = _T_306 | io_dec_tlu_mpc_halted_only; // @[dbg.scala 271:87] + wire _T_310 = _T_307 & _T_15; // @[dbg.scala 271:117] + wire _T_314 = dmcontrol_reg[31] & _T_15; // @[dbg.scala 272:45] + wire _T_316 = 3'h1 == dbg_state; // @[Conditional.scala 37:30] + wire [2:0] _T_318 = dmcontrol_reg[1] ? 3'h0 : 3'h2; // @[dbg.scala 275:26] + wire _T_321 = dmstatus_reg[9] | dmcontrol_reg[1]; // @[dbg.scala 276:39] + wire _T_323 = dmcontrol_wren_Q & dmcontrol_reg[31]; // @[dbg.scala 277:44] + wire _T_326 = _T_323 & _T_15; // @[dbg.scala 277:64] + wire _T_328 = 3'h2 == dbg_state; // @[Conditional.scala 37:30] + wire _T_332 = dmstatus_reg[9] & _T_15; // @[dbg.scala 280:43] + wire _T_335 = ~dmcontrol_reg[31]; // @[dbg.scala 281:33] + wire _T_336 = dmcontrol_reg[30] & _T_335; // @[dbg.scala 281:31] + wire [2:0] _T_337 = _T_336 ? 3'h6 : 3'h3; // @[dbg.scala 281:12] + wire [2:0] _T_339 = dmcontrol_reg[31] ? 3'h1 : 3'h0; // @[dbg.scala 282:12] + wire [2:0] _T_340 = _T_332 ? _T_337 : _T_339; // @[dbg.scala 280:26] + wire _T_343 = dmstatus_reg[9] & dmcontrol_reg[30]; // @[dbg.scala 283:39] + wire _T_346 = _T_343 & _T_335; // @[dbg.scala 283:59] + wire _T_347 = _T_346 & dmcontrol_wren_Q; // @[dbg.scala 283:80] + wire _T_348 = _T_347 | command_wren; // @[dbg.scala 283:99] + wire _T_350 = _T_348 | dmcontrol_reg[1]; // @[dbg.scala 283:114] + wire _T_353 = ~_T_300; // @[dbg.scala 284:28] + wire _T_354 = _T_350 | _T_353; // @[dbg.scala 284:26] + wire _T_355 = dbg_nxtstate == 3'h3; // @[dbg.scala 285:60] + wire _T_356 = dbg_state_en & _T_355; // @[dbg.scala 285:44] + wire _T_357 = dbg_nxtstate == 3'h6; // @[dbg.scala 287:58] + wire _T_358 = dbg_state_en & _T_357; // @[dbg.scala 287:42] + wire _T_366 = 3'h3 == dbg_state; // @[Conditional.scala 37:30] + wire _T_369 = |abstractcs_reg[10:8]; // @[dbg.scala 291:85] + wire [2:0] _T_370 = _T_369 ? 3'h5 : 3'h4; // @[dbg.scala 291:62] + wire [2:0] _T_371 = dmcontrol_reg[1] ? 3'h0 : _T_370; // @[dbg.scala 291:26] + wire _T_374 = io_dbg_dec_dbg_ib_dbg_cmd_valid | _T_369; // @[dbg.scala 292:55] + wire _T_376 = _T_374 | dmcontrol_reg[1]; // @[dbg.scala 292:83] + wire _T_383 = 3'h4 == dbg_state; // @[Conditional.scala 37:30] + wire [2:0] _T_385 = dmcontrol_reg[1] ? 3'h0 : 3'h5; // @[dbg.scala 296:26] + wire _T_387 = io_core_dbg_cmd_done | dmcontrol_reg[1]; // @[dbg.scala 297:44] + wire _T_394 = 3'h5 == dbg_state; // @[Conditional.scala 37:30] + wire _T_403 = 3'h6 == dbg_state; // @[Conditional.scala 37:30] + wire _T_406 = dmstatus_reg[17] | dmcontrol_reg[1]; // @[dbg.scala 309:40] + wire _GEN_10 = _T_403 & _T_406; // @[Conditional.scala 39:67] + wire _GEN_11 = _T_403 & _T_326; // @[Conditional.scala 39:67] + wire [2:0] _GEN_12 = _T_394 ? _T_318 : 3'h0; // @[Conditional.scala 39:67] + wire _GEN_13 = _T_394 | _GEN_10; // @[Conditional.scala 39:67] + wire _GEN_14 = _T_394 & dbg_state_en; // @[Conditional.scala 39:67] + wire _GEN_16 = _T_394 ? _T_326 : _GEN_11; // @[Conditional.scala 39:67] + wire [2:0] _GEN_17 = _T_383 ? _T_385 : _GEN_12; // @[Conditional.scala 39:67] + wire _GEN_18 = _T_383 ? _T_387 : _GEN_13; // @[Conditional.scala 39:67] + wire _GEN_19 = _T_383 ? _T_326 : _GEN_16; // @[Conditional.scala 39:67] + wire _GEN_20 = _T_383 ? 1'h0 : _GEN_14; // @[Conditional.scala 39:67] + wire [2:0] _GEN_22 = _T_366 ? _T_371 : _GEN_17; // @[Conditional.scala 39:67] + wire _GEN_23 = _T_366 ? _T_376 : _GEN_18; // @[Conditional.scala 39:67] + wire _GEN_24 = _T_366 ? _T_326 : _GEN_19; // @[Conditional.scala 39:67] + wire _GEN_25 = _T_366 ? 1'h0 : _GEN_20; // @[Conditional.scala 39:67] + wire [2:0] _GEN_27 = _T_328 ? _T_340 : _GEN_22; // @[Conditional.scala 39:67] + wire _GEN_28 = _T_328 ? _T_354 : _GEN_23; // @[Conditional.scala 39:67] + wire _GEN_29 = _T_328 ? _T_356 : _GEN_25; // @[Conditional.scala 39:67] + wire _GEN_31 = _T_328 & _T_358; // @[Conditional.scala 39:67] + wire _GEN_32 = _T_328 ? _T_326 : _GEN_24; // @[Conditional.scala 39:67] + wire [2:0] _GEN_33 = _T_316 ? _T_318 : _GEN_27; // @[Conditional.scala 39:67] + wire _GEN_34 = _T_316 ? _T_321 : _GEN_28; // @[Conditional.scala 39:67] + wire _GEN_35 = _T_316 ? _T_326 : _GEN_32; // @[Conditional.scala 39:67] + wire _GEN_36 = _T_316 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67] + wire _GEN_38 = _T_316 ? 1'h0 : _GEN_31; // @[Conditional.scala 39:67] + wire [31:0] _T_415 = _T_197 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_416 = _T_415 & data0_reg; // @[dbg.scala 313:71] + wire [31:0] _T_419 = _T_292 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_420 = _T_419 & data1_reg; // @[dbg.scala 313:122] + wire [31:0] _T_421 = _T_416 | _T_420; // @[dbg.scala 313:83] + wire [31:0] _T_424 = _T_128 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_425 = _T_424 & dmcontrol_reg; // @[dbg.scala 314:43] + wire [31:0] _T_426 = _T_421 | _T_425; // @[dbg.scala 313:134] + wire _T_427 = io_dmi_reg_addr == 7'h11; // @[dbg.scala 314:86] + wire [31:0] _T_429 = _T_427 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_430 = _T_429 & dmstatus_reg; // @[dbg.scala 314:99] + wire [31:0] _T_431 = _T_426 | _T_430; // @[dbg.scala 314:59] + wire [31:0] _T_434 = _T_193 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_435 = _T_434 & abstractcs_reg; // @[dbg.scala 315:43] + wire [31:0] _T_436 = _T_431 | _T_435; // @[dbg.scala 314:114] + wire [31:0] _T_439 = _T_194 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_440 = _T_439 & command_reg; // @[dbg.scala 315:100] + wire [31:0] _T_441 = _T_436 | _T_440; // @[dbg.scala 315:60] + wire _T_442 = io_dmi_reg_addr == 7'h40; // @[dbg.scala 316:30] + wire [31:0] _T_444 = _T_442 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_445 = _T_444 & haltsum0_reg; // @[dbg.scala 316:43] + wire [31:0] _T_446 = _T_441 | _T_445; // @[dbg.scala 315:114] + wire [31:0] _T_449 = _T_17 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_450 = _T_449 & sbcs_reg; // @[dbg.scala 316:98] + wire [31:0] _T_451 = _T_446 | _T_450; // @[dbg.scala 316:58] + wire [31:0] _T_454 = _T_25 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_455 = _T_454 & sbaddress0_reg; // @[dbg.scala 317:43] + wire [31:0] _T_456 = _T_451 | _T_455; // @[dbg.scala 316:109] + wire [31:0] _T_459 = _T_26 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_460 = _T_459 & sbdata0_reg; // @[dbg.scala 317:100] + wire [31:0] _T_461 = _T_456 | _T_460; // @[dbg.scala 317:60] + wire [31:0] _T_464 = _T_28 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_465 = _T_464 & sbdata1_reg; // @[dbg.scala 318:43] + wire [31:0] dmi_reg_rdata_din = _T_461 | _T_465; // @[dbg.scala 317:114] + reg [2:0] _T_466; // @[Reg.scala 27:20] + reg [31:0] _T_467; // @[Reg.scala 27:20] + wire _T_469 = command_reg[31:24] == 8'h2; // @[dbg.scala 329:62] + wire [31:0] _T_471 = {data1_reg[31:2],2'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_473 = {20'h0,command_reg[11:0]}; // @[Cat.scala 29:58] + wire _T_476 = dbg_state == 3'h3; // @[dbg.scala 331:50] + wire _T_479 = ~_T_369; // @[dbg.scala 331:75] + wire _T_480 = _T_476 & _T_479; // @[dbg.scala 331:73] + wire _T_488 = command_reg[15:12] == 4'h0; // @[dbg.scala 333:122] + wire [1:0] _T_489 = {1'h0,_T_488}; // @[Cat.scala 29:58] + wire _T_500 = 4'h0 == sb_state; // @[Conditional.scala 37:30] + wire _T_502 = sbdata0_reg_wren0 | sbreadondata_access; // @[dbg.scala 348:39] + wire _T_503 = _T_502 | sbreadonaddr_access; // @[dbg.scala 348:61] + wire _T_505 = |io_dmi_reg_wdata[14:12]; // @[dbg.scala 351:65] + wire _T_506 = sbcs_wren & _T_505; // @[dbg.scala 351:38] + wire [2:0] _T_508 = ~io_dmi_reg_wdata[14:12]; // @[dbg.scala 352:27] + wire [2:0] _T_510 = _T_508 & sbcs_reg[14:12]; // @[dbg.scala 352:53] + wire _T_511 = 4'h1 == sb_state; // @[Conditional.scala 37:30] + wire _T_512 = sbcs_unaligned | sbcs_illegal_size; // @[dbg.scala 355:41] + wire _T_514 = io_dbg_bus_clk_en | sbcs_unaligned; // @[dbg.scala 356:40] + wire _T_515 = _T_514 | sbcs_illegal_size; // @[dbg.scala 356:57] + wire _T_518 = 4'h2 == sb_state; // @[Conditional.scala 37:30] + wire _T_525 = 4'h3 == sb_state; // @[Conditional.scala 37:30] + wire _T_526 = sb_bus_cmd_read & io_dbg_bus_clk_en; // @[dbg.scala 368:38] + wire _T_527 = 4'h4 == sb_state; // @[Conditional.scala 37:30] + wire _T_528 = sb_bus_cmd_write_addr & sb_bus_cmd_write_data; // @[dbg.scala 371:48] + wire _T_531 = sb_bus_cmd_write_addr | sb_bus_cmd_write_data; // @[dbg.scala 372:45] + wire _T_532 = _T_531 & io_dbg_bus_clk_en; // @[dbg.scala 372:70] + wire _T_533 = 4'h5 == sb_state; // @[Conditional.scala 37:30] + wire _T_534 = sb_bus_cmd_write_addr & io_dbg_bus_clk_en; // @[dbg.scala 376:44] + wire _T_535 = 4'h6 == sb_state; // @[Conditional.scala 37:30] + wire _T_536 = sb_bus_cmd_write_data & io_dbg_bus_clk_en; // @[dbg.scala 380:44] + wire _T_537 = 4'h7 == sb_state; // @[Conditional.scala 37:30] + wire _T_538 = sb_bus_rsp_read & io_dbg_bus_clk_en; // @[dbg.scala 384:38] + wire _T_539 = sb_state_en & sb_bus_rsp_error; // @[dbg.scala 385:40] + wire _T_540 = 4'h8 == sb_state; // @[Conditional.scala 37:30] + wire _T_541 = sb_bus_rsp_write & io_dbg_bus_clk_en; // @[dbg.scala 390:39] + wire _T_543 = 4'h9 == sb_state; // @[Conditional.scala 37:30] + wire _GEN_50 = _T_543 & sbcs_reg[16]; // @[Conditional.scala 39:67] + wire _GEN_52 = _T_540 ? _T_541 : _T_543; // @[Conditional.scala 39:67] + wire _GEN_53 = _T_540 & _T_539; // @[Conditional.scala 39:67] + wire _GEN_55 = _T_540 ? 1'h0 : _T_543; // @[Conditional.scala 39:67] + wire _GEN_57 = _T_540 ? 1'h0 : _GEN_50; // @[Conditional.scala 39:67] + wire _GEN_59 = _T_537 ? _T_538 : _GEN_52; // @[Conditional.scala 39:67] + wire _GEN_60 = _T_537 ? _T_539 : _GEN_53; // @[Conditional.scala 39:67] + wire _GEN_62 = _T_537 ? 1'h0 : _GEN_55; // @[Conditional.scala 39:67] + wire _GEN_64 = _T_537 ? 1'h0 : _GEN_57; // @[Conditional.scala 39:67] + wire _GEN_66 = _T_535 ? _T_536 : _GEN_59; // @[Conditional.scala 39:67] + wire _GEN_67 = _T_535 ? 1'h0 : _GEN_60; // @[Conditional.scala 39:67] + wire _GEN_69 = _T_535 ? 1'h0 : _GEN_62; // @[Conditional.scala 39:67] + wire _GEN_71 = _T_535 ? 1'h0 : _GEN_64; // @[Conditional.scala 39:67] + wire _GEN_73 = _T_533 ? _T_534 : _GEN_66; // @[Conditional.scala 39:67] + wire _GEN_74 = _T_533 ? 1'h0 : _GEN_67; // @[Conditional.scala 39:67] + wire _GEN_76 = _T_533 ? 1'h0 : _GEN_69; // @[Conditional.scala 39:67] + wire _GEN_78 = _T_533 ? 1'h0 : _GEN_71; // @[Conditional.scala 39:67] + wire _GEN_80 = _T_527 ? _T_532 : _GEN_73; // @[Conditional.scala 39:67] + wire _GEN_81 = _T_527 ? 1'h0 : _GEN_74; // @[Conditional.scala 39:67] + wire _GEN_83 = _T_527 ? 1'h0 : _GEN_76; // @[Conditional.scala 39:67] + wire _GEN_85 = _T_527 ? 1'h0 : _GEN_78; // @[Conditional.scala 39:67] + wire _GEN_87 = _T_525 ? _T_526 : _GEN_80; // @[Conditional.scala 39:67] + wire _GEN_88 = _T_525 ? 1'h0 : _GEN_81; // @[Conditional.scala 39:67] + wire _GEN_90 = _T_525 ? 1'h0 : _GEN_83; // @[Conditional.scala 39:67] + wire _GEN_92 = _T_525 ? 1'h0 : _GEN_85; // @[Conditional.scala 39:67] + wire _GEN_94 = _T_518 ? _T_515 : _GEN_87; // @[Conditional.scala 39:67] + wire _GEN_95 = _T_518 ? _T_512 : _GEN_88; // @[Conditional.scala 39:67] + wire _GEN_97 = _T_518 ? 1'h0 : _GEN_90; // @[Conditional.scala 39:67] + wire _GEN_99 = _T_518 ? 1'h0 : _GEN_92; // @[Conditional.scala 39:67] + wire _GEN_101 = _T_511 ? _T_515 : _GEN_94; // @[Conditional.scala 39:67] + wire _GEN_102 = _T_511 ? _T_512 : _GEN_95; // @[Conditional.scala 39:67] + wire _GEN_104 = _T_511 ? 1'h0 : _GEN_97; // @[Conditional.scala 39:67] + wire _GEN_106 = _T_511 ? 1'h0 : _GEN_99; // @[Conditional.scala 39:67] + reg [3:0] _T_545; // @[Reg.scala 27:20] + wire _T_552 = |io_sb_axi_r_bits_resp; // @[dbg.scala 411:69] + wire _T_553 = sb_bus_rsp_read & _T_552; // @[dbg.scala 411:39] + wire _T_555 = |io_sb_axi_b_bits_resp; // @[dbg.scala 411:122] + wire _T_556 = sb_bus_rsp_write & _T_555; // @[dbg.scala 411:92] + wire _T_558 = sb_state == 4'h4; // @[dbg.scala 412:36] + wire _T_559 = sb_state == 4'h5; // @[dbg.scala 412:71] + wire _T_565 = sb_state == 4'h6; // @[dbg.scala 423:70] + wire [63:0] _T_571 = _T_60 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12] + wire [63:0] _T_575 = {sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0]}; // @[Cat.scala 29:58] + wire [63:0] _T_576 = _T_571 & _T_575; // @[dbg.scala 424:65] + wire [63:0] _T_580 = _T_45 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12] + wire [63:0] _T_583 = {sbdata0_reg[15:0],sbdata0_reg[15:0],sbdata0_reg[15:0],sbdata0_reg[15:0]}; // @[Cat.scala 29:58] + wire [63:0] _T_584 = _T_580 & _T_583; // @[dbg.scala 424:138] + wire [63:0] _T_585 = _T_576 | _T_584; // @[dbg.scala 424:96] + wire [63:0] _T_589 = _T_49 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12] + wire [63:0] _T_591 = {sbdata0_reg,sbdata0_reg}; // @[Cat.scala 29:58] + wire [63:0] _T_592 = _T_589 & _T_591; // @[dbg.scala 425:45] + wire [63:0] _T_593 = _T_585 | _T_592; // @[dbg.scala 424:168] + wire [63:0] _T_597 = _T_55 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12] + wire [63:0] _T_600 = {sbdata1_reg,sbdata0_reg}; // @[Cat.scala 29:58] + wire [63:0] _T_601 = _T_597 & _T_600; // @[dbg.scala 425:119] + wire [7:0] _T_606 = _T_60 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [14:0] _T_608 = 15'h1 << sbaddress0_reg[2:0]; // @[dbg.scala 427:82] + wire [14:0] _GEN_115 = {{7'd0}, _T_606}; // @[dbg.scala 427:67] + wire [14:0] _T_609 = _GEN_115 & _T_608; // @[dbg.scala 427:67] + wire [7:0] _T_613 = _T_45 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_615 = {sbaddress0_reg[2:1],1'h0}; // @[Cat.scala 29:58] + wire [14:0] _T_616 = 15'h3 << _T_615; // @[dbg.scala 428:59] + wire [14:0] _GEN_116 = {{7'd0}, _T_613}; // @[dbg.scala 428:44] + wire [14:0] _T_617 = _GEN_116 & _T_616; // @[dbg.scala 428:44] + wire [14:0] _T_618 = _T_609 | _T_617; // @[dbg.scala 427:107] + wire [7:0] _T_622 = _T_49 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_624 = {sbaddress0_reg[2],2'h0}; // @[Cat.scala 29:58] + wire [14:0] _T_625 = 15'hf << _T_624; // @[dbg.scala 429:59] + wire [14:0] _GEN_117 = {{7'd0}, _T_622}; // @[dbg.scala 429:44] + wire [14:0] _T_626 = _GEN_117 & _T_625; // @[dbg.scala 429:44] + wire [14:0] _T_627 = _T_618 | _T_626; // @[dbg.scala 428:97] + wire [7:0] _T_631 = _T_55 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [14:0] _GEN_118 = {{7'd0}, _T_631}; // @[dbg.scala 429:100] + wire [14:0] _T_633 = _T_627 | _GEN_118; // @[dbg.scala 429:100] + wire [3:0] _GEN_119 = {{1'd0}, sbaddress0_reg[2:0]}; // @[dbg.scala 446:99] + wire [6:0] _T_644 = 4'h8 * _GEN_119; // @[dbg.scala 446:99] + wire [63:0] _T_645 = io_sb_axi_r_bits_data >> _T_644; // @[dbg.scala 446:92] + wire [63:0] _T_646 = _T_645 & 64'hff; // @[dbg.scala 446:123] + wire [63:0] _T_647 = _T_571 & _T_646; // @[dbg.scala 446:59] + wire [4:0] _GEN_120 = {{3'd0}, sbaddress0_reg[2:1]}; // @[dbg.scala 447:86] + wire [6:0] _T_654 = 5'h10 * _GEN_120; // @[dbg.scala 447:86] + wire [63:0] _T_655 = io_sb_axi_r_bits_data >> _T_654; // @[dbg.scala 447:78] + wire [63:0] _T_656 = _T_655 & 64'hffff; // @[dbg.scala 447:110] + wire [63:0] _T_657 = _T_580 & _T_656; // @[dbg.scala 447:45] + wire [63:0] _T_658 = _T_647 | _T_657; // @[dbg.scala 446:140] + wire [5:0] _GEN_121 = {{5'd0}, sbaddress0_reg[2]}; // @[dbg.scala 448:86] + wire [6:0] _T_665 = 6'h20 * _GEN_121; // @[dbg.scala 448:86] + wire [63:0] _T_666 = io_sb_axi_r_bits_data >> _T_665; // @[dbg.scala 448:78] + wire [63:0] _T_667 = _T_666 & 64'hffffffff; // @[dbg.scala 448:107] + wire [63:0] _T_668 = _T_589 & _T_667; // @[dbg.scala 448:45] + wire [63:0] _T_669 = _T_658 | _T_668; // @[dbg.scala 447:129] + wire [63:0] _T_675 = _T_597 & io_sb_axi_r_bits_data; // @[dbg.scala 449:45] rvclkhdr rvclkhdr ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), @@ -60003,59 +60015,61 @@ module dbg( .io_en(rvclkhdr_7_io_en), .io_scan_mode(rvclkhdr_7_io_scan_mode) ); - assign io_dbg_cmd_size = command_reg[21:20]; // @[dbg.scala 336:19] - assign io_dbg_core_rst_l = ~dmcontrol_reg[1]; // @[dbg.scala 107:21] - assign io_dbg_halt_req = _T_300 ? _T_316 : _GEN_35; // @[dbg.scala 268:19 dbg.scala 274:23 dbg.scala 279:23 dbg.scala 290:23 dbg.scala 295:23 dbg.scala 300:23 dbg.scala 307:23 dbg.scala 312:23] - assign io_dbg_resume_req = _T_300 ? 1'h0 : _GEN_38; // @[dbg.scala 269:21 dbg.scala 289:25] - assign io_dmi_reg_rdata = _T_469; // @[dbg.scala 327:20] - assign io_sb_axi_aw_valid = _T_560 | _T_561; // @[dbg.scala 414:22] - assign io_sb_axi_aw_bits_addr = sbaddress0_reg; // @[dbg.scala 415:26] - assign io_sb_axi_aw_bits_size = sbcs_reg[19:17]; // @[dbg.scala 417:26] - assign io_sb_axi_w_valid = _T_560 | _T_567; // @[dbg.scala 425:21] - assign io_sb_axi_w_bits_data = _T_595 | _T_603; // @[dbg.scala 426:25] - assign io_sb_axi_w_bits_strb = _T_635[7:0]; // @[dbg.scala 429:25] - assign io_sb_axi_b_ready = 1'h1; // @[dbg.scala 446:21] - assign io_sb_axi_ar_valid = sb_state == 4'h3; // @[dbg.scala 435:22] - assign io_sb_axi_ar_bits_addr = sbaddress0_reg; // @[dbg.scala 436:26] - assign io_sb_axi_ar_bits_size = sbcs_reg[19:17]; // @[dbg.scala 438:26] - assign io_sb_axi_r_ready = 1'h1; // @[dbg.scala 447:21] - assign io_dbg_dec_dbg_ib_dbg_cmd_valid = _T_482 & io_dbg_dma_io_dma_dbg_ready; // @[dbg.scala 333:35] - assign io_dbg_dec_dbg_ib_dbg_cmd_write = command_reg[16]; // @[dbg.scala 334:35] - assign io_dbg_dec_dbg_ib_dbg_cmd_type = _T_471 ? 2'h2 : _T_491; // @[dbg.scala 335:34] - assign io_dbg_dec_dbg_ib_dbg_cmd_addr = _T_471 ? _T_473 : _T_475; // @[dbg.scala 331:34] - assign io_dbg_dec_dbg_dctl_dbg_cmd_wrdata = data0_reg; // @[dbg.scala 332:38] - assign io_dbg_dma_dbg_ib_dbg_cmd_valid = io_dbg_dec_dbg_ib_dbg_cmd_valid; // @[dbg.scala 456:39] - assign io_dbg_dma_dbg_ib_dbg_cmd_write = io_dbg_dec_dbg_ib_dbg_cmd_write; // @[dbg.scala 457:39] - assign io_dbg_dma_dbg_ib_dbg_cmd_type = io_dbg_dec_dbg_ib_dbg_cmd_type; // @[dbg.scala 458:39] - assign io_dbg_dma_dbg_ib_dbg_cmd_addr = io_dbg_dec_dbg_ib_dbg_cmd_addr; // @[dbg.scala 454:39] - assign io_dbg_dma_dbg_dctl_dbg_cmd_wrdata = io_dbg_dec_dbg_dctl_dbg_cmd_wrdata; // @[dbg.scala 455:39] - assign io_dbg_dma_io_dbg_dma_bubble = _T_482 | _T_283; // @[dbg.scala 337:32] - assign dbg_state = _T_468; // @[dbg.scala 322:13] - assign dbg_state_en = _T_300 ? _T_312 : _GEN_34; // @[dbg.scala 265:16 dbg.scala 273:20 dbg.scala 278:20 dbg.scala 285:20 dbg.scala 294:20 dbg.scala 299:20 dbg.scala 304:20 dbg.scala 311:20] - assign sb_state = _T_547; // @[dbg.scala 404:12] - assign sb_state_en = _T_502 ? _T_505 : _GEN_101; // @[dbg.scala 350:19 dbg.scala 358:19 dbg.scala 364:19 dbg.scala 370:19 dbg.scala 374:19 dbg.scala 378:19 dbg.scala 382:19 dbg.scala 386:19 dbg.scala 392:19 dbg.scala 398:19] - assign dmcontrol_reg = {_T_145,_T_143}; // @[dbg.scala 185:17] - assign sbaddress0_reg = _T_118; // @[dbg.scala 166:18] - assign sbcs_sbbusy_wren = _T_502 ? sb_state_en : _GEN_104; // @[dbg.scala 342:20 dbg.scala 351:24 dbg.scala 399:24] - assign sbcs_sberror_wren = _T_502 ? _T_508 : _GEN_102; // @[dbg.scala 344:21 dbg.scala 353:25 dbg.scala 359:25 dbg.scala 365:25 dbg.scala 387:25 dbg.scala 393:25] - assign sb_bus_rdata = _T_671 | _T_677; // @[dbg.scala 448:16] - assign sbaddress0_reg_wren1 = _T_502 ? 1'h0 : _GEN_106; // @[dbg.scala 346:24 dbg.scala 401:28] - assign dmstatus_reg = {_T_163,_T_159}; // @[dbg.scala 191:16] - assign dmstatus_havereset = _T_192; // @[dbg.scala 208:22] - assign dmstatus_resumeack = _T_185; // @[dbg.scala 200:22] - assign dmstatus_unavail = dmcontrol_reg[1] | _T_180; // @[dbg.scala 198:20] - assign dmstatus_running = ~_T_183; // @[dbg.scala 199:20] - assign dmstatus_halted = _T_188; // @[dbg.scala 204:19] - assign abstractcs_busy_wren = _T_300 ? 1'h0 : _GEN_36; // @[dbg.scala 266:24 dbg.scala 287:28 dbg.scala 305:28] - assign sb_bus_cmd_read = io_sb_axi_ar_valid & io_sb_axi_ar_ready; // @[dbg.scala 408:19] - assign sb_bus_cmd_write_addr = io_sb_axi_aw_valid & io_sb_axi_aw_ready; // @[dbg.scala 409:25] - assign sb_bus_cmd_write_data = io_sb_axi_w_valid & io_sb_axi_w_ready; // @[dbg.scala 410:25] - assign sb_bus_rsp_read = io_sb_axi_r_valid & io_sb_axi_r_ready; // @[dbg.scala 411:19] - assign sb_bus_rsp_error = _T_555 | _T_558; // @[dbg.scala 413:20] - assign sb_bus_rsp_write = io_sb_axi_b_valid & io_sb_axi_b_ready; // @[dbg.scala 412:20] - assign sbcs_sbbusy_din = 4'h0 == sb_state; // @[dbg.scala 343:19 dbg.scala 352:23 dbg.scala 400:23] - assign data1_reg = _T_299; // @[dbg.scala 259:13] - assign sbcs_reg = {_T_44,_T_40}; // @[dbg.scala 132:12] + assign io_dbg_cmd_size = command_reg[21:20]; // @[dbg.scala 334:19] + assign io_dbg_core_rst_l = ~dmcontrol_reg[1]; // @[dbg.scala 105:21] + assign io_dbg_halt_req = _T_298 ? _T_314 : _GEN_35; // @[dbg.scala 266:19 dbg.scala 272:23 dbg.scala 277:23 dbg.scala 288:23 dbg.scala 293:23 dbg.scala 298:23 dbg.scala 305:23 dbg.scala 310:23] + assign io_dbg_resume_req = _T_298 ? 1'h0 : _GEN_38; // @[dbg.scala 267:21 dbg.scala 287:25] + assign io_dmi_reg_rdata = _T_467; // @[dbg.scala 325:20] + assign io_sb_axi_aw_valid = _T_558 | _T_559; // @[dbg.scala 412:22] + assign io_sb_axi_aw_bits_addr = sbaddress0_reg; // @[dbg.scala 413:26] + assign io_sb_axi_aw_bits_region = sbaddress0_reg[31:28]; // @[dbg.scala 418:28] + assign io_sb_axi_aw_bits_size = sbcs_reg[19:17]; // @[dbg.scala 415:26] + assign io_sb_axi_w_valid = _T_558 | _T_565; // @[dbg.scala 423:21] + assign io_sb_axi_w_bits_data = _T_593 | _T_601; // @[dbg.scala 424:25] + assign io_sb_axi_w_bits_strb = _T_633[7:0]; // @[dbg.scala 427:25] + assign io_sb_axi_b_ready = 1'h1; // @[dbg.scala 444:21] + assign io_sb_axi_ar_valid = sb_state == 4'h3; // @[dbg.scala 433:22] + assign io_sb_axi_ar_bits_addr = sbaddress0_reg; // @[dbg.scala 434:26] + assign io_sb_axi_ar_bits_region = sbaddress0_reg[31:28]; // @[dbg.scala 439:28] + assign io_sb_axi_ar_bits_size = sbcs_reg[19:17]; // @[dbg.scala 436:26] + assign io_sb_axi_r_ready = 1'h1; // @[dbg.scala 445:21] + assign io_dbg_dec_dbg_ib_dbg_cmd_valid = _T_480 & io_dbg_dma_io_dma_dbg_ready; // @[dbg.scala 331:35] + assign io_dbg_dec_dbg_ib_dbg_cmd_write = command_reg[16]; // @[dbg.scala 332:35] + assign io_dbg_dec_dbg_ib_dbg_cmd_type = _T_469 ? 2'h2 : _T_489; // @[dbg.scala 333:34] + assign io_dbg_dec_dbg_ib_dbg_cmd_addr = _T_469 ? _T_471 : _T_473; // @[dbg.scala 329:34] + assign io_dbg_dec_dbg_dctl_dbg_cmd_wrdata = data0_reg; // @[dbg.scala 330:38] + assign io_dbg_dma_dbg_ib_dbg_cmd_valid = io_dbg_dec_dbg_ib_dbg_cmd_valid; // @[dbg.scala 454:39] + assign io_dbg_dma_dbg_ib_dbg_cmd_write = io_dbg_dec_dbg_ib_dbg_cmd_write; // @[dbg.scala 455:39] + assign io_dbg_dma_dbg_ib_dbg_cmd_type = io_dbg_dec_dbg_ib_dbg_cmd_type; // @[dbg.scala 456:39] + assign io_dbg_dma_dbg_ib_dbg_cmd_addr = io_dbg_dec_dbg_ib_dbg_cmd_addr; // @[dbg.scala 452:39] + assign io_dbg_dma_dbg_dctl_dbg_cmd_wrdata = io_dbg_dec_dbg_dctl_dbg_cmd_wrdata; // @[dbg.scala 453:39] + assign io_dbg_dma_io_dbg_dma_bubble = _T_480 | _T_281; // @[dbg.scala 335:32] + assign dbg_state = _T_466; // @[dbg.scala 320:13] + assign dbg_state_en = _T_298 ? _T_310 : _GEN_34; // @[dbg.scala 263:16 dbg.scala 271:20 dbg.scala 276:20 dbg.scala 283:20 dbg.scala 292:20 dbg.scala 297:20 dbg.scala 302:20 dbg.scala 309:20] + assign sb_state = _T_545; // @[dbg.scala 402:12] + assign sb_state_en = _T_500 ? _T_503 : _GEN_101; // @[dbg.scala 348:19 dbg.scala 356:19 dbg.scala 362:19 dbg.scala 368:19 dbg.scala 372:19 dbg.scala 376:19 dbg.scala 380:19 dbg.scala 384:19 dbg.scala 390:19 dbg.scala 396:19] + assign dmcontrol_reg = {_T_143,_T_141}; // @[dbg.scala 183:17] + assign sbaddress0_reg = _T_116; // @[dbg.scala 164:18] + assign sbcs_sbbusy_wren = _T_500 ? sb_state_en : _GEN_104; // @[dbg.scala 340:20 dbg.scala 349:24 dbg.scala 397:24] + assign sbcs_sberror_wren = _T_500 ? _T_506 : _GEN_102; // @[dbg.scala 342:21 dbg.scala 351:25 dbg.scala 357:25 dbg.scala 363:25 dbg.scala 385:25 dbg.scala 391:25] + assign sb_bus_rdata = _T_669 | _T_675; // @[dbg.scala 446:16] + assign sbaddress0_reg_wren1 = _T_500 ? 1'h0 : _GEN_106; // @[dbg.scala 344:24 dbg.scala 399:28] + assign dmstatus_reg = {_T_161,_T_157}; // @[dbg.scala 189:16] + assign dmstatus_havereset = _T_190; // @[dbg.scala 206:22] + assign dmstatus_resumeack = _T_183; // @[dbg.scala 198:22] + assign dmstatus_unavail = dmcontrol_reg[1] | _T_178; // @[dbg.scala 196:20] + assign dmstatus_running = ~_T_181; // @[dbg.scala 197:20] + assign dmstatus_halted = _T_186; // @[dbg.scala 202:19] + assign abstractcs_busy_wren = _T_298 ? 1'h0 : _GEN_36; // @[dbg.scala 264:24 dbg.scala 285:28 dbg.scala 303:28] + assign sb_bus_cmd_read = io_sb_axi_ar_valid & io_sb_axi_ar_ready; // @[dbg.scala 406:19] + assign sb_bus_cmd_write_addr = io_sb_axi_aw_valid & io_sb_axi_aw_ready; // @[dbg.scala 407:25] + assign sb_bus_cmd_write_data = io_sb_axi_w_valid & io_sb_axi_w_ready; // @[dbg.scala 408:25] + assign sb_bus_rsp_read = io_sb_axi_r_valid & io_sb_axi_r_ready; // @[dbg.scala 409:19] + assign sb_bus_rsp_error = _T_553 | _T_556; // @[dbg.scala 411:20] + assign sb_bus_rsp_write = io_sb_axi_b_valid & io_sb_axi_b_ready; // @[dbg.scala 410:20] + assign sbcs_sbbusy_din = 4'h0 == sb_state; // @[dbg.scala 341:19 dbg.scala 350:23 dbg.scala 398:23] + assign data1_reg = _T_297; // @[dbg.scala 257:13] + assign sbcs_reg = {_T_42,_T_38}; // @[dbg.scala 130:12] assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17] assign rvclkhdr_io_en = _T_3 | io_clk_override; // @[lib.scala 345:16] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] @@ -60071,17 +60085,17 @@ module dbg( assign rvclkhdr_4_io_clk = clock; // @[lib.scala 370:18] assign rvclkhdr_4_io_en = sbaddress0_reg_wren0 | sbaddress0_reg_wren1; // @[lib.scala 371:17] assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] - assign abstractcs_reg = {_T_267,_T_265}; // @[dbg.scala 240:18] + assign abstractcs_reg = {_T_265,_T_263}; // @[dbg.scala 238:18] assign rvclkhdr_5_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_5_io_en = _T_217 & _T_272; // @[lib.scala 371:17] + assign rvclkhdr_5_io_en = _T_215 & _T_270; // @[lib.scala 371:17] assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_6_io_clk = clock; // @[lib.scala 370:18] assign rvclkhdr_6_io_en = data0_reg_wren0 | data0_reg_wren1; // @[lib.scala 371:17] assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_7_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_7_io_en = _T_295 & _T_272; // @[lib.scala 371:17] + assign rvclkhdr_7_io_en = _T_293 & _T_270; // @[lib.scala 371:17] assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] - assign dbg_nxtstate = _T_300 ? _T_303 : _GEN_33; // @[dbg.scala 264:16 dbg.scala 272:20 dbg.scala 277:20 dbg.scala 282:20 dbg.scala 293:20 dbg.scala 298:20 dbg.scala 303:20 dbg.scala 310:20] + assign dbg_nxtstate = _T_298 ? _T_301 : _GEN_33; // @[dbg.scala 262:16 dbg.scala 270:20 dbg.scala 275:20 dbg.scala 280:20 dbg.scala 291:20 dbg.scala 296:20 dbg.scala 301:20 dbg.scala 308:20] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -60132,7 +60146,7 @@ initial begin _RAND_6 = {1{`RANDOM}}; sbdata1_reg = _RAND_6[31:0]; _RAND_7 = {1{`RANDOM}}; - _T_118 = _RAND_7[31:0]; + _T_116 = _RAND_7[31:0]; _RAND_8 = {1{`RANDOM}}; dm_temp = _RAND_8[3:0]; _RAND_9 = {1{`RANDOM}}; @@ -60140,11 +60154,11 @@ initial begin _RAND_10 = {1{`RANDOM}}; dmcontrol_wren_Q = _RAND_10[0:0]; _RAND_11 = {1{`RANDOM}}; - _T_185 = _RAND_11[0:0]; + _T_183 = _RAND_11[0:0]; _RAND_12 = {1{`RANDOM}}; - _T_188 = _RAND_12[0:0]; + _T_186 = _RAND_12[0:0]; _RAND_13 = {1{`RANDOM}}; - _T_192 = _RAND_13[0:0]; + _T_190 = _RAND_13[0:0]; _RAND_14 = {1{`RANDOM}}; abs_temp_12 = _RAND_14[0:0]; _RAND_15 = {1{`RANDOM}}; @@ -60154,13 +60168,13 @@ initial begin _RAND_17 = {1{`RANDOM}}; data0_reg = _RAND_17[31:0]; _RAND_18 = {1{`RANDOM}}; - _T_299 = _RAND_18[31:0]; + _T_297 = _RAND_18[31:0]; _RAND_19 = {1{`RANDOM}}; - _T_468 = _RAND_19[2:0]; + _T_466 = _RAND_19[2:0]; _RAND_20 = {1{`RANDOM}}; - _T_469 = _RAND_20[31:0]; + _T_467 = _RAND_20[31:0]; _RAND_21 = {1{`RANDOM}}; - _T_547 = _RAND_21[3:0]; + _T_545 = _RAND_21[3:0]; `endif // RANDOMIZE_REG_INIT if (dbg_dm_rst_l) begin temp_sbcs_22 = 1'h0; @@ -60174,7 +60188,7 @@ initial begin if (dbg_dm_rst_l) begin temp_sbcs_19_15 = 5'h0; end - if (rst_not) begin + if (dbg_dm_rst_l) begin temp_sbcs_14_12 = 3'h0; end if (dbg_dm_rst_l) begin @@ -60184,7 +60198,7 @@ initial begin sbdata1_reg = 32'h0; end if (dbg_dm_rst_l) begin - _T_118 = 32'h0; + _T_116 = 32'h0; end if (dbg_dm_rst_l) begin dm_temp = 4'h0; @@ -60196,13 +60210,13 @@ initial begin dmcontrol_wren_Q = 1'h0; end if (dbg_dm_rst_l) begin - _T_185 = 1'h0; + _T_183 = 1'h0; end if (dbg_dm_rst_l) begin - _T_188 = 1'h0; + _T_186 = 1'h0; end if (dbg_dm_rst_l) begin - _T_192 = 1'h0; + _T_190 = 1'h0; end if (dbg_dm_rst_l) begin abs_temp_12 = 1'h0; @@ -60217,16 +60231,16 @@ initial begin data0_reg = 32'h0; end if (dbg_dm_rst_l) begin - _T_299 = 32'h0; + _T_297 = 32'h0; end if (rst_temp) begin - _T_468 = 3'h0; + _T_466 = 3'h0; end if (dbg_dm_rst_l) begin - _T_469 = 32'h0; + _T_467 = 32'h0; end if (dbg_dm_rst_l) begin - _T_547 = 4'h0; + _T_545 = 4'h0; end `endif // RANDOMIZE end // initial @@ -60262,35 +60276,35 @@ end // initial temp_sbcs_19_15 <= io_dmi_reg_wdata[19:15]; end end - always @(posedge rvclkhdr_1_io_l1clk or posedge rst_not) begin - if (rst_not) begin + always @(posedge rvclkhdr_1_io_l1clk or posedge dbg_dm_rst_l) begin + if (dbg_dm_rst_l) begin temp_sbcs_14_12 <= 3'h0; end else if (sbcs_sberror_wren) begin - if (_T_502) begin - temp_sbcs_14_12 <= _T_512; - end else if (_T_513) begin + if (_T_500) begin + temp_sbcs_14_12 <= _T_510; + end else if (_T_511) begin if (sbcs_unaligned) begin temp_sbcs_14_12 <= 3'h3; end else begin temp_sbcs_14_12 <= 3'h4; end - end else if (_T_520) begin + end else if (_T_518) begin if (sbcs_unaligned) begin temp_sbcs_14_12 <= 3'h3; end else begin temp_sbcs_14_12 <= 3'h4; end + end else if (_T_525) begin + temp_sbcs_14_12 <= 3'h0; end else if (_T_527) begin temp_sbcs_14_12 <= 3'h0; - end else if (_T_529) begin + end else if (_T_533) begin temp_sbcs_14_12 <= 3'h0; end else if (_T_535) begin temp_sbcs_14_12 <= 3'h0; end else if (_T_537) begin - temp_sbcs_14_12 <= 3'h0; - end else if (_T_539) begin temp_sbcs_14_12 <= 3'h2; - end else if (_T_542) begin + end else if (_T_540) begin temp_sbcs_14_12 <= 3'h2; end else begin temp_sbcs_14_12 <= 3'h0; @@ -60301,28 +60315,28 @@ end // initial if (dbg_dm_rst_l) begin sbdata0_reg <= 32'h0; end else begin - sbdata0_reg <= _T_95 | _T_99; + sbdata0_reg <= _T_93 | _T_97; end end always @(posedge rvclkhdr_3_io_l1clk or posedge dbg_dm_rst_l) begin if (dbg_dm_rst_l) begin sbdata1_reg <= 32'h0; end else begin - sbdata1_reg <= _T_102 | _T_106; + sbdata1_reg <= _T_100 | _T_104; end end always @(posedge rvclkhdr_4_io_l1clk or posedge dbg_dm_rst_l) begin if (dbg_dm_rst_l) begin - _T_118 <= 32'h0; + _T_116 <= 32'h0; end else begin - _T_118 <= _T_111 | _T_117; + _T_116 <= _T_109 | _T_115; end end always @(posedge rvclkhdr_io_l1clk or posedge dbg_dm_rst_l) begin if (dbg_dm_rst_l) begin dm_temp <= 4'h0; end else if (dmcontrol_wren) begin - dm_temp <= _T_136; + dm_temp <= _T_134; end end always @(posedge rvclkhdr_io_l1clk or posedge io_dbg_rst_l) begin @@ -60336,40 +60350,40 @@ end // initial if (dbg_dm_rst_l) begin dmcontrol_wren_Q <= 1'h0; end else begin - dmcontrol_wren_Q <= _T_131 & io_dmi_reg_wr_en; + dmcontrol_wren_Q <= _T_129 & io_dmi_reg_wr_en; end end always @(posedge rvclkhdr_io_l1clk or posedge dbg_dm_rst_l) begin if (dbg_dm_rst_l) begin - _T_185 <= 1'h0; + _T_183 <= 1'h0; end else if (dmstatus_resumeack_wren) begin - _T_185 <= _T_166; + _T_183 <= _T_164; end end always @(posedge rvclkhdr_io_l1clk or posedge dbg_dm_rst_l) begin if (dbg_dm_rst_l) begin - _T_188 <= 1'h0; + _T_186 <= 1'h0; end else begin - _T_188 <= io_dec_tlu_dbg_halted & _T_186; + _T_186 <= io_dec_tlu_dbg_halted & _T_184; end end always @(posedge rvclkhdr_io_l1clk or posedge dbg_dm_rst_l) begin if (dbg_dm_rst_l) begin - _T_192 <= 1'h0; + _T_190 <= 1'h0; end else begin - _T_192 <= _T_189 & _T_190; + _T_190 <= _T_187 & _T_188; end end always @(posedge rvclkhdr_io_l1clk or posedge dbg_dm_rst_l) begin if (dbg_dm_rst_l) begin abs_temp_12 <= 1'h0; end else if (abstractcs_busy_wren) begin - if (_T_300) begin + if (_T_298) begin abs_temp_12 <= 1'h0; - end else if (_T_318) begin + end else if (_T_316) begin abs_temp_12 <= 1'h0; end else begin - abs_temp_12 <= _T_330; + abs_temp_12 <= _T_328; end end end @@ -60377,132 +60391,132 @@ end // initial if (dbg_dm_rst_l) begin abs_temp_10_8 <= 3'h0; end else begin - abs_temp_10_8 <= _T_258 | _T_263; + abs_temp_10_8 <= _T_256 | _T_261; end end always @(posedge rvclkhdr_5_io_l1clk or posedge dbg_dm_rst_l) begin if (dbg_dm_rst_l) begin command_reg <= 32'h0; end else begin - command_reg <= {_T_278,_T_276}; + command_reg <= {_T_276,_T_274}; end end always @(posedge rvclkhdr_6_io_l1clk or posedge dbg_dm_rst_l) begin if (dbg_dm_rst_l) begin data0_reg <= 32'h0; end else begin - data0_reg <= _T_289 | _T_292; + data0_reg <= _T_287 | _T_290; end end always @(posedge rvclkhdr_7_io_l1clk or posedge dbg_dm_rst_l) begin if (dbg_dm_rst_l) begin - _T_299 <= 32'h0; + _T_297 <= 32'h0; end else begin - _T_299 <= _T_298 & io_dmi_reg_wdata; + _T_297 <= _T_296 & io_dmi_reg_wdata; end end always @(posedge rvclkhdr_io_l1clk or posedge rst_temp) begin if (rst_temp) begin - _T_468 <= 3'h0; + _T_466 <= 3'h0; end else if (dbg_state_en) begin - if (_T_300) begin - if (_T_302) begin - _T_468 <= 3'h2; + if (_T_298) begin + if (_T_300) begin + _T_466 <= 3'h2; end else begin - _T_468 <= 3'h1; + _T_466 <= 3'h1; end - end else if (_T_318) begin + end else if (_T_316) begin if (dmcontrol_reg[1]) begin - _T_468 <= 3'h0; + _T_466 <= 3'h0; end else begin - _T_468 <= 3'h2; + _T_466 <= 3'h2; end - end else if (_T_330) begin - if (_T_334) begin - if (_T_338) begin - _T_468 <= 3'h6; + end else if (_T_328) begin + if (_T_332) begin + if (_T_336) begin + _T_466 <= 3'h6; end else begin - _T_468 <= 3'h3; + _T_466 <= 3'h3; end end else if (dmcontrol_reg[31]) begin - _T_468 <= 3'h1; + _T_466 <= 3'h1; end else begin - _T_468 <= 3'h0; + _T_466 <= 3'h0; end - end else if (_T_368) begin + end else if (_T_366) begin if (dmcontrol_reg[1]) begin - _T_468 <= 3'h0; - end else if (_T_371) begin - _T_468 <= 3'h5; + _T_466 <= 3'h0; + end else if (_T_369) begin + _T_466 <= 3'h5; end else begin - _T_468 <= 3'h4; + _T_466 <= 3'h4; end - end else if (_T_385) begin + end else if (_T_383) begin if (dmcontrol_reg[1]) begin - _T_468 <= 3'h0; + _T_466 <= 3'h0; end else begin - _T_468 <= 3'h5; + _T_466 <= 3'h5; end - end else if (_T_396) begin + end else if (_T_394) begin if (dmcontrol_reg[1]) begin - _T_468 <= 3'h0; + _T_466 <= 3'h0; end else begin - _T_468 <= 3'h2; + _T_466 <= 3'h2; end end else begin - _T_468 <= 3'h0; + _T_466 <= 3'h0; end end end always @(posedge rvclkhdr_io_l1clk or posedge dbg_dm_rst_l) begin if (dbg_dm_rst_l) begin - _T_469 <= 32'h0; + _T_467 <= 32'h0; end else if (io_dmi_reg_en) begin - _T_469 <= dmi_reg_rdata_din; + _T_467 <= dmi_reg_rdata_din; end end always @(posedge rvclkhdr_1_io_l1clk or posedge dbg_dm_rst_l) begin if (dbg_dm_rst_l) begin - _T_547 <= 4'h0; + _T_545 <= 4'h0; end else if (sb_state_en) begin - if (_T_502) begin + if (_T_500) begin if (sbdata0_reg_wren0) begin - _T_547 <= 4'h2; + _T_545 <= 4'h2; end else begin - _T_547 <= 4'h1; + _T_545 <= 4'h1; end - end else if (_T_513) begin - if (_T_514) begin - _T_547 <= 4'h9; + end else if (_T_511) begin + if (_T_512) begin + _T_545 <= 4'h9; end else begin - _T_547 <= 4'h3; + _T_545 <= 4'h3; end - end else if (_T_520) begin - if (_T_514) begin - _T_547 <= 4'h9; + end else if (_T_518) begin + if (_T_512) begin + _T_545 <= 4'h9; end else begin - _T_547 <= 4'h4; + _T_545 <= 4'h4; end + end else if (_T_525) begin + _T_545 <= 4'h7; end else if (_T_527) begin - _T_547 <= 4'h7; - end else if (_T_529) begin - if (_T_530) begin - _T_547 <= 4'h8; + if (_T_528) begin + _T_545 <= 4'h8; end else if (sb_bus_cmd_write_data) begin - _T_547 <= 4'h5; + _T_545 <= 4'h5; end else begin - _T_547 <= 4'h6; + _T_545 <= 4'h6; end + end else if (_T_533) begin + _T_545 <= 4'h8; end else if (_T_535) begin - _T_547 <= 4'h8; + _T_545 <= 4'h8; end else if (_T_537) begin - _T_547 <= 4'h8; - end else if (_T_539) begin - _T_547 <= 4'h9; - end else if (_T_542) begin - _T_547 <= 4'h9; + _T_545 <= 4'h9; + end else if (_T_540) begin + _T_545 <= 4'h9; end else begin - _T_547 <= 4'h0; + _T_545 <= 4'h0; end end end @@ -68176,6 +68190,7 @@ module lsu_bus_buffer( output io_tlu_busbuff_lsu_pmu_bus_error, output io_tlu_busbuff_lsu_pmu_bus_busy, input io_tlu_busbuff_dec_tlu_external_ldfwd_disable, + input io_tlu_busbuff_dec_tlu_wb_coalescing_disable, input io_tlu_busbuff_dec_tlu_sideeffect_posted_disable, output io_tlu_busbuff_lsu_imprecise_error_load_any, output io_tlu_busbuff_lsu_imprecise_error_store_any, @@ -68225,7 +68240,9 @@ module lsu_bus_buffer( output io_lsu_axi_aw_valid, output [2:0] io_lsu_axi_aw_bits_id, output [31:0] io_lsu_axi_aw_bits_addr, + output [3:0] io_lsu_axi_aw_bits_region, output [2:0] io_lsu_axi_aw_bits_size, + output [3:0] io_lsu_axi_aw_bits_cache, input io_lsu_axi_w_ready, output io_lsu_axi_w_valid, output [63:0] io_lsu_axi_w_bits_data, @@ -68237,7 +68254,9 @@ module lsu_bus_buffer( output io_lsu_axi_ar_valid, output [2:0] io_lsu_axi_ar_bits_id, output [31:0] io_lsu_axi_ar_bits_addr, + output [3:0] io_lsu_axi_ar_bits_region, output [2:0] io_lsu_axi_ar_bits_size, + output [3:0] io_lsu_axi_ar_bits_cache, output io_lsu_axi_r_ready, input io_lsu_axi_r_valid, input [2:0] io_lsu_axi_r_bits_id, @@ -68333,9 +68352,9 @@ module lsu_bus_buffer( reg [31:0] _RAND_75; reg [31:0] _RAND_76; reg [31:0] _RAND_77; - reg [63:0] _RAND_78; + reg [31:0] _RAND_78; reg [31:0] _RAND_79; - reg [31:0] _RAND_80; + reg [63:0] _RAND_80; reg [31:0] _RAND_81; reg [31:0] _RAND_82; reg [31:0] _RAND_83; @@ -68360,6 +68379,8 @@ module lsu_bus_buffer( reg [31:0] _RAND_102; reg [31:0] _RAND_103; reg [31:0] _RAND_104; + reg [31:0] _RAND_105; + reg [31:0] _RAND_106; `endif // RANDOMIZE_REG_INIT wire rvclkhdr_io_l1clk; // @[lib.scala 368:23] wire rvclkhdr_io_clk; // @[lib.scala 368:23] @@ -68409,69 +68430,69 @@ module lsu_bus_buffer( wire rvclkhdr_11_io_clk; // @[lib.scala 368:23] wire rvclkhdr_11_io_en; // @[lib.scala 368:23] wire rvclkhdr_11_io_scan_mode; // @[lib.scala 368:23] - wire [3:0] ldst_byteen_hi_m = io_ldst_byteen_ext_m[7:4]; // @[lsu_bus_buffer.scala 72:46] - wire [3:0] ldst_byteen_lo_m = io_ldst_byteen_ext_m[3:0]; // @[lsu_bus_buffer.scala 73:46] + wire [3:0] ldst_byteen_hi_m = io_ldst_byteen_ext_m[7:4]; // @[lsu_bus_buffer.scala 73:46] + wire [3:0] ldst_byteen_lo_m = io_ldst_byteen_ext_m[3:0]; // @[lsu_bus_buffer.scala 74:46] reg [31:0] buf_addr_0; // @[lib.scala 374:16] - wire _T_2 = io_lsu_addr_m[31:2] == buf_addr_0[31:2]; // @[lsu_bus_buffer.scala 75:74] + wire _T_2 = io_lsu_addr_m[31:2] == buf_addr_0[31:2]; // @[lsu_bus_buffer.scala 76:74] reg _T_4360; // @[Reg.scala 27:20] reg _T_4357; // @[Reg.scala 27:20] reg _T_4354; // @[Reg.scala 27:20] reg _T_4351; // @[Reg.scala 27:20] wire [3:0] buf_write = {_T_4360,_T_4357,_T_4354,_T_4351}; // @[Cat.scala 29:58] - wire _T_4 = _T_2 & buf_write[0]; // @[lsu_bus_buffer.scala 75:98] + wire _T_4 = _T_2 & buf_write[0]; // @[lsu_bus_buffer.scala 76:98] reg [2:0] buf_state_0; // @[Reg.scala 27:20] - wire _T_5 = buf_state_0 != 3'h0; // @[lsu_bus_buffer.scala 75:129] - wire _T_6 = _T_4 & _T_5; // @[lsu_bus_buffer.scala 75:113] - wire ld_addr_hitvec_lo_0 = _T_6 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 75:141] + wire _T_5 = buf_state_0 != 3'h0; // @[lsu_bus_buffer.scala 76:129] + wire _T_6 = _T_4 & _T_5; // @[lsu_bus_buffer.scala 76:113] + wire ld_addr_hitvec_lo_0 = _T_6 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 76:141] reg [31:0] buf_addr_1; // @[lib.scala 374:16] - wire _T_9 = io_lsu_addr_m[31:2] == buf_addr_1[31:2]; // @[lsu_bus_buffer.scala 75:74] - wire _T_11 = _T_9 & buf_write[1]; // @[lsu_bus_buffer.scala 75:98] + wire _T_9 = io_lsu_addr_m[31:2] == buf_addr_1[31:2]; // @[lsu_bus_buffer.scala 76:74] + wire _T_11 = _T_9 & buf_write[1]; // @[lsu_bus_buffer.scala 76:98] reg [2:0] buf_state_1; // @[Reg.scala 27:20] - wire _T_12 = buf_state_1 != 3'h0; // @[lsu_bus_buffer.scala 75:129] - wire _T_13 = _T_11 & _T_12; // @[lsu_bus_buffer.scala 75:113] - wire ld_addr_hitvec_lo_1 = _T_13 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 75:141] + wire _T_12 = buf_state_1 != 3'h0; // @[lsu_bus_buffer.scala 76:129] + wire _T_13 = _T_11 & _T_12; // @[lsu_bus_buffer.scala 76:113] + wire ld_addr_hitvec_lo_1 = _T_13 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 76:141] reg [31:0] buf_addr_2; // @[lib.scala 374:16] - wire _T_16 = io_lsu_addr_m[31:2] == buf_addr_2[31:2]; // @[lsu_bus_buffer.scala 75:74] - wire _T_18 = _T_16 & buf_write[2]; // @[lsu_bus_buffer.scala 75:98] + wire _T_16 = io_lsu_addr_m[31:2] == buf_addr_2[31:2]; // @[lsu_bus_buffer.scala 76:74] + wire _T_18 = _T_16 & buf_write[2]; // @[lsu_bus_buffer.scala 76:98] reg [2:0] buf_state_2; // @[Reg.scala 27:20] - wire _T_19 = buf_state_2 != 3'h0; // @[lsu_bus_buffer.scala 75:129] - wire _T_20 = _T_18 & _T_19; // @[lsu_bus_buffer.scala 75:113] - wire ld_addr_hitvec_lo_2 = _T_20 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 75:141] + wire _T_19 = buf_state_2 != 3'h0; // @[lsu_bus_buffer.scala 76:129] + wire _T_20 = _T_18 & _T_19; // @[lsu_bus_buffer.scala 76:113] + wire ld_addr_hitvec_lo_2 = _T_20 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 76:141] reg [31:0] buf_addr_3; // @[lib.scala 374:16] - wire _T_23 = io_lsu_addr_m[31:2] == buf_addr_3[31:2]; // @[lsu_bus_buffer.scala 75:74] - wire _T_25 = _T_23 & buf_write[3]; // @[lsu_bus_buffer.scala 75:98] + wire _T_23 = io_lsu_addr_m[31:2] == buf_addr_3[31:2]; // @[lsu_bus_buffer.scala 76:74] + wire _T_25 = _T_23 & buf_write[3]; // @[lsu_bus_buffer.scala 76:98] reg [2:0] buf_state_3; // @[Reg.scala 27:20] - wire _T_26 = buf_state_3 != 3'h0; // @[lsu_bus_buffer.scala 75:129] - wire _T_27 = _T_25 & _T_26; // @[lsu_bus_buffer.scala 75:113] - wire ld_addr_hitvec_lo_3 = _T_27 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 75:141] - wire _T_30 = io_end_addr_m[31:2] == buf_addr_0[31:2]; // @[lsu_bus_buffer.scala 76:74] - wire _T_32 = _T_30 & buf_write[0]; // @[lsu_bus_buffer.scala 76:98] - wire _T_34 = _T_32 & _T_5; // @[lsu_bus_buffer.scala 76:113] - wire ld_addr_hitvec_hi_0 = _T_34 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 76:141] - wire _T_37 = io_end_addr_m[31:2] == buf_addr_1[31:2]; // @[lsu_bus_buffer.scala 76:74] - wire _T_39 = _T_37 & buf_write[1]; // @[lsu_bus_buffer.scala 76:98] - wire _T_41 = _T_39 & _T_12; // @[lsu_bus_buffer.scala 76:113] - wire ld_addr_hitvec_hi_1 = _T_41 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 76:141] - wire _T_44 = io_end_addr_m[31:2] == buf_addr_2[31:2]; // @[lsu_bus_buffer.scala 76:74] - wire _T_46 = _T_44 & buf_write[2]; // @[lsu_bus_buffer.scala 76:98] - wire _T_48 = _T_46 & _T_19; // @[lsu_bus_buffer.scala 76:113] - wire ld_addr_hitvec_hi_2 = _T_48 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 76:141] - wire _T_51 = io_end_addr_m[31:2] == buf_addr_3[31:2]; // @[lsu_bus_buffer.scala 76:74] - wire _T_53 = _T_51 & buf_write[3]; // @[lsu_bus_buffer.scala 76:98] - wire _T_55 = _T_53 & _T_26; // @[lsu_bus_buffer.scala 76:113] - wire ld_addr_hitvec_hi_3 = _T_55 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 76:141] + wire _T_26 = buf_state_3 != 3'h0; // @[lsu_bus_buffer.scala 76:129] + wire _T_27 = _T_25 & _T_26; // @[lsu_bus_buffer.scala 76:113] + wire ld_addr_hitvec_lo_3 = _T_27 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 76:141] + wire _T_30 = io_end_addr_m[31:2] == buf_addr_0[31:2]; // @[lsu_bus_buffer.scala 77:74] + wire _T_32 = _T_30 & buf_write[0]; // @[lsu_bus_buffer.scala 77:98] + wire _T_34 = _T_32 & _T_5; // @[lsu_bus_buffer.scala 77:113] + wire ld_addr_hitvec_hi_0 = _T_34 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 77:141] + wire _T_37 = io_end_addr_m[31:2] == buf_addr_1[31:2]; // @[lsu_bus_buffer.scala 77:74] + wire _T_39 = _T_37 & buf_write[1]; // @[lsu_bus_buffer.scala 77:98] + wire _T_41 = _T_39 & _T_12; // @[lsu_bus_buffer.scala 77:113] + wire ld_addr_hitvec_hi_1 = _T_41 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 77:141] + wire _T_44 = io_end_addr_m[31:2] == buf_addr_2[31:2]; // @[lsu_bus_buffer.scala 77:74] + wire _T_46 = _T_44 & buf_write[2]; // @[lsu_bus_buffer.scala 77:98] + wire _T_48 = _T_46 & _T_19; // @[lsu_bus_buffer.scala 77:113] + wire ld_addr_hitvec_hi_2 = _T_48 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 77:141] + wire _T_51 = io_end_addr_m[31:2] == buf_addr_3[31:2]; // @[lsu_bus_buffer.scala 77:74] + wire _T_53 = _T_51 & buf_write[3]; // @[lsu_bus_buffer.scala 77:98] + wire _T_55 = _T_53 & _T_26; // @[lsu_bus_buffer.scala 77:113] + wire ld_addr_hitvec_hi_3 = _T_55 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 77:141] reg [3:0] buf_byteen_3; // @[Reg.scala 27:20] - wire _T_99 = ld_addr_hitvec_lo_3 & buf_byteen_3[0]; // @[lsu_bus_buffer.scala 140:95] - wire _T_101 = _T_99 & ldst_byteen_lo_m[0]; // @[lsu_bus_buffer.scala 140:114] + wire _T_99 = ld_addr_hitvec_lo_3 & buf_byteen_3[0]; // @[lsu_bus_buffer.scala 141:95] + wire _T_101 = _T_99 & ldst_byteen_lo_m[0]; // @[lsu_bus_buffer.scala 141:114] reg [3:0] buf_byteen_2; // @[Reg.scala 27:20] - wire _T_95 = ld_addr_hitvec_lo_2 & buf_byteen_2[0]; // @[lsu_bus_buffer.scala 140:95] - wire _T_97 = _T_95 & ldst_byteen_lo_m[0]; // @[lsu_bus_buffer.scala 140:114] + wire _T_95 = ld_addr_hitvec_lo_2 & buf_byteen_2[0]; // @[lsu_bus_buffer.scala 141:95] + wire _T_97 = _T_95 & ldst_byteen_lo_m[0]; // @[lsu_bus_buffer.scala 141:114] reg [3:0] buf_byteen_1; // @[Reg.scala 27:20] - wire _T_91 = ld_addr_hitvec_lo_1 & buf_byteen_1[0]; // @[lsu_bus_buffer.scala 140:95] - wire _T_93 = _T_91 & ldst_byteen_lo_m[0]; // @[lsu_bus_buffer.scala 140:114] + wire _T_91 = ld_addr_hitvec_lo_1 & buf_byteen_1[0]; // @[lsu_bus_buffer.scala 141:95] + wire _T_93 = _T_91 & ldst_byteen_lo_m[0]; // @[lsu_bus_buffer.scala 141:114] reg [3:0] buf_byteen_0; // @[Reg.scala 27:20] - wire _T_87 = ld_addr_hitvec_lo_0 & buf_byteen_0[0]; // @[lsu_bus_buffer.scala 140:95] - wire _T_89 = _T_87 & ldst_byteen_lo_m[0]; // @[lsu_bus_buffer.scala 140:114] + wire _T_87 = ld_addr_hitvec_lo_0 & buf_byteen_0[0]; // @[lsu_bus_buffer.scala 141:95] + wire _T_89 = _T_87 & ldst_byteen_lo_m[0]; // @[lsu_bus_buffer.scala 141:114] wire [3:0] ld_byte_hitvec_lo_0 = {_T_101,_T_97,_T_93,_T_89}; // @[Cat.scala 29:58] reg [3:0] buf_ageQ_3; // @[lsu_bus_buffer.scala 499:60] wire _T_2621 = buf_state_3 == 3'h2; // @[lsu_bus_buffer.scala 411:93] @@ -68553,23 +68574,23 @@ module lsu_bus_buffer( wire _T_2711 = ~buf_age_3[0]; // @[lsu_bus_buffer.scala 412:89] wire _T_2713 = _T_2711 & _T_5; // @[lsu_bus_buffer.scala 412:104] wire [3:0] buf_age_younger_3 = {1'h0,_T_2725,_T_2719,_T_2713}; // @[Cat.scala 29:58] - wire [3:0] _T_255 = ld_byte_hitvec_lo_0 & buf_age_younger_3; // @[lsu_bus_buffer.scala 145:122] - wire _T_256 = |_T_255; // @[lsu_bus_buffer.scala 145:144] - wire _T_257 = ~_T_256; // @[lsu_bus_buffer.scala 145:99] - wire _T_258 = ld_byte_hitvec_lo_0[3] & _T_257; // @[lsu_bus_buffer.scala 145:97] + wire [3:0] _T_255 = ld_byte_hitvec_lo_0 & buf_age_younger_3; // @[lsu_bus_buffer.scala 146:122] + wire _T_256 = |_T_255; // @[lsu_bus_buffer.scala 146:144] + wire _T_257 = ~_T_256; // @[lsu_bus_buffer.scala 146:99] + wire _T_258 = ld_byte_hitvec_lo_0[3] & _T_257; // @[lsu_bus_buffer.scala 146:97] reg [31:0] ibuf_addr; // @[lib.scala 374:16] - wire _T_512 = io_lsu_addr_m[31:2] == ibuf_addr[31:2]; // @[lsu_bus_buffer.scala 151:51] + wire _T_512 = io_lsu_addr_m[31:2] == ibuf_addr[31:2]; // @[lsu_bus_buffer.scala 152:51] reg ibuf_write; // @[Reg.scala 27:20] - wire _T_513 = _T_512 & ibuf_write; // @[lsu_bus_buffer.scala 151:73] - reg ibuf_valid; // @[lsu_bus_buffer.scala 238:54] - wire _T_514 = _T_513 & ibuf_valid; // @[lsu_bus_buffer.scala 151:86] - wire ld_addr_ibuf_hit_lo = _T_514 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 151:99] + wire _T_513 = _T_512 & ibuf_write; // @[lsu_bus_buffer.scala 152:73] + reg ibuf_valid; // @[lsu_bus_buffer.scala 239:54] + wire _T_514 = _T_513 & ibuf_valid; // @[lsu_bus_buffer.scala 152:86] + wire ld_addr_ibuf_hit_lo = _T_514 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 152:99] wire [3:0] _T_521 = ld_addr_ibuf_hit_lo ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] reg [3:0] ibuf_byteen; // @[Reg.scala 27:20] - wire [3:0] _T_522 = _T_521 & ibuf_byteen; // @[lsu_bus_buffer.scala 156:55] - wire [3:0] ld_byte_ibuf_hit_lo = _T_522 & ldst_byteen_lo_m; // @[lsu_bus_buffer.scala 156:69] - wire _T_260 = ~ld_byte_ibuf_hit_lo[0]; // @[lsu_bus_buffer.scala 145:150] - wire _T_261 = _T_258 & _T_260; // @[lsu_bus_buffer.scala 145:148] + wire [3:0] _T_522 = _T_521 & ibuf_byteen; // @[lsu_bus_buffer.scala 157:55] + wire [3:0] ld_byte_ibuf_hit_lo = _T_522 & ldst_byteen_lo_m; // @[lsu_bus_buffer.scala 157:69] + wire _T_260 = ~ld_byte_ibuf_hit_lo[0]; // @[lsu_bus_buffer.scala 146:150] + wire _T_261 = _T_258 & _T_260; // @[lsu_bus_buffer.scala 146:148] reg [3:0] buf_ageQ_2; // @[lsu_bus_buffer.scala 499:60] wire _T_2601 = buf_ageQ_2[3] & _T_2623; // @[lsu_bus_buffer.scala 411:76] wire _T_2596 = buf_ageQ_2[2] & _T_2618; // @[lsu_bus_buffer.scala 411:76] @@ -68583,11 +68604,11 @@ module lsu_bus_buffer( wire _T_2684 = ~buf_age_2[0]; // @[lsu_bus_buffer.scala 412:89] wire _T_2686 = _T_2684 & _T_5; // @[lsu_bus_buffer.scala 412:104] wire [3:0] buf_age_younger_2 = {_T_2704,1'h0,_T_2692,_T_2686}; // @[Cat.scala 29:58] - wire [3:0] _T_247 = ld_byte_hitvec_lo_0 & buf_age_younger_2; // @[lsu_bus_buffer.scala 145:122] - wire _T_248 = |_T_247; // @[lsu_bus_buffer.scala 145:144] - wire _T_249 = ~_T_248; // @[lsu_bus_buffer.scala 145:99] - wire _T_250 = ld_byte_hitvec_lo_0[2] & _T_249; // @[lsu_bus_buffer.scala 145:97] - wire _T_253 = _T_250 & _T_260; // @[lsu_bus_buffer.scala 145:148] + wire [3:0] _T_247 = ld_byte_hitvec_lo_0 & buf_age_younger_2; // @[lsu_bus_buffer.scala 146:122] + wire _T_248 = |_T_247; // @[lsu_bus_buffer.scala 146:144] + wire _T_249 = ~_T_248; // @[lsu_bus_buffer.scala 146:99] + wire _T_250 = ld_byte_hitvec_lo_0[2] & _T_249; // @[lsu_bus_buffer.scala 146:97] + wire _T_253 = _T_250 & _T_260; // @[lsu_bus_buffer.scala 146:148] reg [3:0] buf_ageQ_1; // @[lsu_bus_buffer.scala 499:60] wire _T_2578 = buf_ageQ_1[3] & _T_2623; // @[lsu_bus_buffer.scala 411:76] wire _T_2573 = buf_ageQ_1[2] & _T_2618; // @[lsu_bus_buffer.scala 411:76] @@ -68601,11 +68622,11 @@ module lsu_bus_buffer( wire _T_2657 = ~buf_age_1[0]; // @[lsu_bus_buffer.scala 412:89] wire _T_2659 = _T_2657 & _T_5; // @[lsu_bus_buffer.scala 412:104] wire [3:0] buf_age_younger_1 = {_T_2677,_T_2671,1'h0,_T_2659}; // @[Cat.scala 29:58] - wire [3:0] _T_239 = ld_byte_hitvec_lo_0 & buf_age_younger_1; // @[lsu_bus_buffer.scala 145:122] - wire _T_240 = |_T_239; // @[lsu_bus_buffer.scala 145:144] - wire _T_241 = ~_T_240; // @[lsu_bus_buffer.scala 145:99] - wire _T_242 = ld_byte_hitvec_lo_0[1] & _T_241; // @[lsu_bus_buffer.scala 145:97] - wire _T_245 = _T_242 & _T_260; // @[lsu_bus_buffer.scala 145:148] + wire [3:0] _T_239 = ld_byte_hitvec_lo_0 & buf_age_younger_1; // @[lsu_bus_buffer.scala 146:122] + wire _T_240 = |_T_239; // @[lsu_bus_buffer.scala 146:144] + wire _T_241 = ~_T_240; // @[lsu_bus_buffer.scala 146:99] + wire _T_242 = ld_byte_hitvec_lo_0[1] & _T_241; // @[lsu_bus_buffer.scala 146:97] + wire _T_245 = _T_242 & _T_260; // @[lsu_bus_buffer.scala 146:148] reg [3:0] buf_ageQ_0; // @[lsu_bus_buffer.scala 499:60] wire _T_2555 = buf_ageQ_0[3] & _T_2623; // @[lsu_bus_buffer.scala 411:76] wire _T_2550 = buf_ageQ_0[2] & _T_2618; // @[lsu_bus_buffer.scala 411:76] @@ -68619,253 +68640,253 @@ module lsu_bus_buffer( wire _T_2636 = ~buf_age_0[1]; // @[lsu_bus_buffer.scala 412:89] wire _T_2638 = _T_2636 & _T_12; // @[lsu_bus_buffer.scala 412:104] wire [3:0] buf_age_younger_0 = {_T_2650,_T_2644,_T_2638,1'h0}; // @[Cat.scala 29:58] - wire [3:0] _T_231 = ld_byte_hitvec_lo_0 & buf_age_younger_0; // @[lsu_bus_buffer.scala 145:122] - wire _T_232 = |_T_231; // @[lsu_bus_buffer.scala 145:144] - wire _T_233 = ~_T_232; // @[lsu_bus_buffer.scala 145:99] - wire _T_234 = ld_byte_hitvec_lo_0[0] & _T_233; // @[lsu_bus_buffer.scala 145:97] - wire _T_237 = _T_234 & _T_260; // @[lsu_bus_buffer.scala 145:148] + wire [3:0] _T_231 = ld_byte_hitvec_lo_0 & buf_age_younger_0; // @[lsu_bus_buffer.scala 146:122] + wire _T_232 = |_T_231; // @[lsu_bus_buffer.scala 146:144] + wire _T_233 = ~_T_232; // @[lsu_bus_buffer.scala 146:99] + wire _T_234 = ld_byte_hitvec_lo_0[0] & _T_233; // @[lsu_bus_buffer.scala 146:97] + wire _T_237 = _T_234 & _T_260; // @[lsu_bus_buffer.scala 146:148] wire [3:0] ld_byte_hitvecfn_lo_0 = {_T_261,_T_253,_T_245,_T_237}; // @[Cat.scala 29:58] - wire _T_56 = |ld_byte_hitvecfn_lo_0; // @[lsu_bus_buffer.scala 137:73] - wire _T_58 = _T_56 | ld_byte_ibuf_hit_lo[0]; // @[lsu_bus_buffer.scala 137:77] - wire _T_117 = ld_addr_hitvec_lo_3 & buf_byteen_3[1]; // @[lsu_bus_buffer.scala 140:95] - wire _T_119 = _T_117 & ldst_byteen_lo_m[1]; // @[lsu_bus_buffer.scala 140:114] - wire _T_113 = ld_addr_hitvec_lo_2 & buf_byteen_2[1]; // @[lsu_bus_buffer.scala 140:95] - wire _T_115 = _T_113 & ldst_byteen_lo_m[1]; // @[lsu_bus_buffer.scala 140:114] - wire _T_109 = ld_addr_hitvec_lo_1 & buf_byteen_1[1]; // @[lsu_bus_buffer.scala 140:95] - wire _T_111 = _T_109 & ldst_byteen_lo_m[1]; // @[lsu_bus_buffer.scala 140:114] - wire _T_105 = ld_addr_hitvec_lo_0 & buf_byteen_0[1]; // @[lsu_bus_buffer.scala 140:95] - wire _T_107 = _T_105 & ldst_byteen_lo_m[1]; // @[lsu_bus_buffer.scala 140:114] + wire _T_56 = |ld_byte_hitvecfn_lo_0; // @[lsu_bus_buffer.scala 138:73] + wire _T_58 = _T_56 | ld_byte_ibuf_hit_lo[0]; // @[lsu_bus_buffer.scala 138:77] + wire _T_117 = ld_addr_hitvec_lo_3 & buf_byteen_3[1]; // @[lsu_bus_buffer.scala 141:95] + wire _T_119 = _T_117 & ldst_byteen_lo_m[1]; // @[lsu_bus_buffer.scala 141:114] + wire _T_113 = ld_addr_hitvec_lo_2 & buf_byteen_2[1]; // @[lsu_bus_buffer.scala 141:95] + wire _T_115 = _T_113 & ldst_byteen_lo_m[1]; // @[lsu_bus_buffer.scala 141:114] + wire _T_109 = ld_addr_hitvec_lo_1 & buf_byteen_1[1]; // @[lsu_bus_buffer.scala 141:95] + wire _T_111 = _T_109 & ldst_byteen_lo_m[1]; // @[lsu_bus_buffer.scala 141:114] + wire _T_105 = ld_addr_hitvec_lo_0 & buf_byteen_0[1]; // @[lsu_bus_buffer.scala 141:95] + wire _T_107 = _T_105 & ldst_byteen_lo_m[1]; // @[lsu_bus_buffer.scala 141:114] wire [3:0] ld_byte_hitvec_lo_1 = {_T_119,_T_115,_T_111,_T_107}; // @[Cat.scala 29:58] - wire [3:0] _T_290 = ld_byte_hitvec_lo_1 & buf_age_younger_3; // @[lsu_bus_buffer.scala 145:122] - wire _T_291 = |_T_290; // @[lsu_bus_buffer.scala 145:144] - wire _T_292 = ~_T_291; // @[lsu_bus_buffer.scala 145:99] - wire _T_293 = ld_byte_hitvec_lo_1[3] & _T_292; // @[lsu_bus_buffer.scala 145:97] - wire _T_295 = ~ld_byte_ibuf_hit_lo[1]; // @[lsu_bus_buffer.scala 145:150] - wire _T_296 = _T_293 & _T_295; // @[lsu_bus_buffer.scala 145:148] - wire [3:0] _T_282 = ld_byte_hitvec_lo_1 & buf_age_younger_2; // @[lsu_bus_buffer.scala 145:122] - wire _T_283 = |_T_282; // @[lsu_bus_buffer.scala 145:144] - wire _T_284 = ~_T_283; // @[lsu_bus_buffer.scala 145:99] - wire _T_285 = ld_byte_hitvec_lo_1[2] & _T_284; // @[lsu_bus_buffer.scala 145:97] - wire _T_288 = _T_285 & _T_295; // @[lsu_bus_buffer.scala 145:148] - wire [3:0] _T_274 = ld_byte_hitvec_lo_1 & buf_age_younger_1; // @[lsu_bus_buffer.scala 145:122] - wire _T_275 = |_T_274; // @[lsu_bus_buffer.scala 145:144] - wire _T_276 = ~_T_275; // @[lsu_bus_buffer.scala 145:99] - wire _T_277 = ld_byte_hitvec_lo_1[1] & _T_276; // @[lsu_bus_buffer.scala 145:97] - wire _T_280 = _T_277 & _T_295; // @[lsu_bus_buffer.scala 145:148] - wire [3:0] _T_266 = ld_byte_hitvec_lo_1 & buf_age_younger_0; // @[lsu_bus_buffer.scala 145:122] - wire _T_267 = |_T_266; // @[lsu_bus_buffer.scala 145:144] - wire _T_268 = ~_T_267; // @[lsu_bus_buffer.scala 145:99] - wire _T_269 = ld_byte_hitvec_lo_1[0] & _T_268; // @[lsu_bus_buffer.scala 145:97] - wire _T_272 = _T_269 & _T_295; // @[lsu_bus_buffer.scala 145:148] + wire [3:0] _T_290 = ld_byte_hitvec_lo_1 & buf_age_younger_3; // @[lsu_bus_buffer.scala 146:122] + wire _T_291 = |_T_290; // @[lsu_bus_buffer.scala 146:144] + wire _T_292 = ~_T_291; // @[lsu_bus_buffer.scala 146:99] + wire _T_293 = ld_byte_hitvec_lo_1[3] & _T_292; // @[lsu_bus_buffer.scala 146:97] + wire _T_295 = ~ld_byte_ibuf_hit_lo[1]; // @[lsu_bus_buffer.scala 146:150] + wire _T_296 = _T_293 & _T_295; // @[lsu_bus_buffer.scala 146:148] + wire [3:0] _T_282 = ld_byte_hitvec_lo_1 & buf_age_younger_2; // @[lsu_bus_buffer.scala 146:122] + wire _T_283 = |_T_282; // @[lsu_bus_buffer.scala 146:144] + wire _T_284 = ~_T_283; // @[lsu_bus_buffer.scala 146:99] + wire _T_285 = ld_byte_hitvec_lo_1[2] & _T_284; // @[lsu_bus_buffer.scala 146:97] + wire _T_288 = _T_285 & _T_295; // @[lsu_bus_buffer.scala 146:148] + wire [3:0] _T_274 = ld_byte_hitvec_lo_1 & buf_age_younger_1; // @[lsu_bus_buffer.scala 146:122] + wire _T_275 = |_T_274; // @[lsu_bus_buffer.scala 146:144] + wire _T_276 = ~_T_275; // @[lsu_bus_buffer.scala 146:99] + wire _T_277 = ld_byte_hitvec_lo_1[1] & _T_276; // @[lsu_bus_buffer.scala 146:97] + wire _T_280 = _T_277 & _T_295; // @[lsu_bus_buffer.scala 146:148] + wire [3:0] _T_266 = ld_byte_hitvec_lo_1 & buf_age_younger_0; // @[lsu_bus_buffer.scala 146:122] + wire _T_267 = |_T_266; // @[lsu_bus_buffer.scala 146:144] + wire _T_268 = ~_T_267; // @[lsu_bus_buffer.scala 146:99] + wire _T_269 = ld_byte_hitvec_lo_1[0] & _T_268; // @[lsu_bus_buffer.scala 146:97] + wire _T_272 = _T_269 & _T_295; // @[lsu_bus_buffer.scala 146:148] wire [3:0] ld_byte_hitvecfn_lo_1 = {_T_296,_T_288,_T_280,_T_272}; // @[Cat.scala 29:58] - wire _T_59 = |ld_byte_hitvecfn_lo_1; // @[lsu_bus_buffer.scala 137:73] - wire _T_61 = _T_59 | ld_byte_ibuf_hit_lo[1]; // @[lsu_bus_buffer.scala 137:77] - wire _T_135 = ld_addr_hitvec_lo_3 & buf_byteen_3[2]; // @[lsu_bus_buffer.scala 140:95] - wire _T_137 = _T_135 & ldst_byteen_lo_m[2]; // @[lsu_bus_buffer.scala 140:114] - wire _T_131 = ld_addr_hitvec_lo_2 & buf_byteen_2[2]; // @[lsu_bus_buffer.scala 140:95] - wire _T_133 = _T_131 & ldst_byteen_lo_m[2]; // @[lsu_bus_buffer.scala 140:114] - wire _T_127 = ld_addr_hitvec_lo_1 & buf_byteen_1[2]; // @[lsu_bus_buffer.scala 140:95] - wire _T_129 = _T_127 & ldst_byteen_lo_m[2]; // @[lsu_bus_buffer.scala 140:114] - wire _T_123 = ld_addr_hitvec_lo_0 & buf_byteen_0[2]; // @[lsu_bus_buffer.scala 140:95] - wire _T_125 = _T_123 & ldst_byteen_lo_m[2]; // @[lsu_bus_buffer.scala 140:114] + wire _T_59 = |ld_byte_hitvecfn_lo_1; // @[lsu_bus_buffer.scala 138:73] + wire _T_61 = _T_59 | ld_byte_ibuf_hit_lo[1]; // @[lsu_bus_buffer.scala 138:77] + wire _T_135 = ld_addr_hitvec_lo_3 & buf_byteen_3[2]; // @[lsu_bus_buffer.scala 141:95] + wire _T_137 = _T_135 & ldst_byteen_lo_m[2]; // @[lsu_bus_buffer.scala 141:114] + wire _T_131 = ld_addr_hitvec_lo_2 & buf_byteen_2[2]; // @[lsu_bus_buffer.scala 141:95] + wire _T_133 = _T_131 & ldst_byteen_lo_m[2]; // @[lsu_bus_buffer.scala 141:114] + wire _T_127 = ld_addr_hitvec_lo_1 & buf_byteen_1[2]; // @[lsu_bus_buffer.scala 141:95] + wire _T_129 = _T_127 & ldst_byteen_lo_m[2]; // @[lsu_bus_buffer.scala 141:114] + wire _T_123 = ld_addr_hitvec_lo_0 & buf_byteen_0[2]; // @[lsu_bus_buffer.scala 141:95] + wire _T_125 = _T_123 & ldst_byteen_lo_m[2]; // @[lsu_bus_buffer.scala 141:114] wire [3:0] ld_byte_hitvec_lo_2 = {_T_137,_T_133,_T_129,_T_125}; // @[Cat.scala 29:58] - wire [3:0] _T_325 = ld_byte_hitvec_lo_2 & buf_age_younger_3; // @[lsu_bus_buffer.scala 145:122] - wire _T_326 = |_T_325; // @[lsu_bus_buffer.scala 145:144] - wire _T_327 = ~_T_326; // @[lsu_bus_buffer.scala 145:99] - wire _T_328 = ld_byte_hitvec_lo_2[3] & _T_327; // @[lsu_bus_buffer.scala 145:97] - wire _T_330 = ~ld_byte_ibuf_hit_lo[2]; // @[lsu_bus_buffer.scala 145:150] - wire _T_331 = _T_328 & _T_330; // @[lsu_bus_buffer.scala 145:148] - wire [3:0] _T_317 = ld_byte_hitvec_lo_2 & buf_age_younger_2; // @[lsu_bus_buffer.scala 145:122] - wire _T_318 = |_T_317; // @[lsu_bus_buffer.scala 145:144] - wire _T_319 = ~_T_318; // @[lsu_bus_buffer.scala 145:99] - wire _T_320 = ld_byte_hitvec_lo_2[2] & _T_319; // @[lsu_bus_buffer.scala 145:97] - wire _T_323 = _T_320 & _T_330; // @[lsu_bus_buffer.scala 145:148] - wire [3:0] _T_309 = ld_byte_hitvec_lo_2 & buf_age_younger_1; // @[lsu_bus_buffer.scala 145:122] - wire _T_310 = |_T_309; // @[lsu_bus_buffer.scala 145:144] - wire _T_311 = ~_T_310; // @[lsu_bus_buffer.scala 145:99] - wire _T_312 = ld_byte_hitvec_lo_2[1] & _T_311; // @[lsu_bus_buffer.scala 145:97] - wire _T_315 = _T_312 & _T_330; // @[lsu_bus_buffer.scala 145:148] - wire [3:0] _T_301 = ld_byte_hitvec_lo_2 & buf_age_younger_0; // @[lsu_bus_buffer.scala 145:122] - wire _T_302 = |_T_301; // @[lsu_bus_buffer.scala 145:144] - wire _T_303 = ~_T_302; // @[lsu_bus_buffer.scala 145:99] - wire _T_304 = ld_byte_hitvec_lo_2[0] & _T_303; // @[lsu_bus_buffer.scala 145:97] - wire _T_307 = _T_304 & _T_330; // @[lsu_bus_buffer.scala 145:148] + wire [3:0] _T_325 = ld_byte_hitvec_lo_2 & buf_age_younger_3; // @[lsu_bus_buffer.scala 146:122] + wire _T_326 = |_T_325; // @[lsu_bus_buffer.scala 146:144] + wire _T_327 = ~_T_326; // @[lsu_bus_buffer.scala 146:99] + wire _T_328 = ld_byte_hitvec_lo_2[3] & _T_327; // @[lsu_bus_buffer.scala 146:97] + wire _T_330 = ~ld_byte_ibuf_hit_lo[2]; // @[lsu_bus_buffer.scala 146:150] + wire _T_331 = _T_328 & _T_330; // @[lsu_bus_buffer.scala 146:148] + wire [3:0] _T_317 = ld_byte_hitvec_lo_2 & buf_age_younger_2; // @[lsu_bus_buffer.scala 146:122] + wire _T_318 = |_T_317; // @[lsu_bus_buffer.scala 146:144] + wire _T_319 = ~_T_318; // @[lsu_bus_buffer.scala 146:99] + wire _T_320 = ld_byte_hitvec_lo_2[2] & _T_319; // @[lsu_bus_buffer.scala 146:97] + wire _T_323 = _T_320 & _T_330; // @[lsu_bus_buffer.scala 146:148] + wire [3:0] _T_309 = ld_byte_hitvec_lo_2 & buf_age_younger_1; // @[lsu_bus_buffer.scala 146:122] + wire _T_310 = |_T_309; // @[lsu_bus_buffer.scala 146:144] + wire _T_311 = ~_T_310; // @[lsu_bus_buffer.scala 146:99] + wire _T_312 = ld_byte_hitvec_lo_2[1] & _T_311; // @[lsu_bus_buffer.scala 146:97] + wire _T_315 = _T_312 & _T_330; // @[lsu_bus_buffer.scala 146:148] + wire [3:0] _T_301 = ld_byte_hitvec_lo_2 & buf_age_younger_0; // @[lsu_bus_buffer.scala 146:122] + wire _T_302 = |_T_301; // @[lsu_bus_buffer.scala 146:144] + wire _T_303 = ~_T_302; // @[lsu_bus_buffer.scala 146:99] + wire _T_304 = ld_byte_hitvec_lo_2[0] & _T_303; // @[lsu_bus_buffer.scala 146:97] + wire _T_307 = _T_304 & _T_330; // @[lsu_bus_buffer.scala 146:148] wire [3:0] ld_byte_hitvecfn_lo_2 = {_T_331,_T_323,_T_315,_T_307}; // @[Cat.scala 29:58] - wire _T_62 = |ld_byte_hitvecfn_lo_2; // @[lsu_bus_buffer.scala 137:73] - wire _T_64 = _T_62 | ld_byte_ibuf_hit_lo[2]; // @[lsu_bus_buffer.scala 137:77] - wire _T_153 = ld_addr_hitvec_lo_3 & buf_byteen_3[3]; // @[lsu_bus_buffer.scala 140:95] - wire _T_155 = _T_153 & ldst_byteen_lo_m[3]; // @[lsu_bus_buffer.scala 140:114] - wire _T_149 = ld_addr_hitvec_lo_2 & buf_byteen_2[3]; // @[lsu_bus_buffer.scala 140:95] - wire _T_151 = _T_149 & ldst_byteen_lo_m[3]; // @[lsu_bus_buffer.scala 140:114] - wire _T_145 = ld_addr_hitvec_lo_1 & buf_byteen_1[3]; // @[lsu_bus_buffer.scala 140:95] - wire _T_147 = _T_145 & ldst_byteen_lo_m[3]; // @[lsu_bus_buffer.scala 140:114] - wire _T_141 = ld_addr_hitvec_lo_0 & buf_byteen_0[3]; // @[lsu_bus_buffer.scala 140:95] - wire _T_143 = _T_141 & ldst_byteen_lo_m[3]; // @[lsu_bus_buffer.scala 140:114] + wire _T_62 = |ld_byte_hitvecfn_lo_2; // @[lsu_bus_buffer.scala 138:73] + wire _T_64 = _T_62 | ld_byte_ibuf_hit_lo[2]; // @[lsu_bus_buffer.scala 138:77] + wire _T_153 = ld_addr_hitvec_lo_3 & buf_byteen_3[3]; // @[lsu_bus_buffer.scala 141:95] + wire _T_155 = _T_153 & ldst_byteen_lo_m[3]; // @[lsu_bus_buffer.scala 141:114] + wire _T_149 = ld_addr_hitvec_lo_2 & buf_byteen_2[3]; // @[lsu_bus_buffer.scala 141:95] + wire _T_151 = _T_149 & ldst_byteen_lo_m[3]; // @[lsu_bus_buffer.scala 141:114] + wire _T_145 = ld_addr_hitvec_lo_1 & buf_byteen_1[3]; // @[lsu_bus_buffer.scala 141:95] + wire _T_147 = _T_145 & ldst_byteen_lo_m[3]; // @[lsu_bus_buffer.scala 141:114] + wire _T_141 = ld_addr_hitvec_lo_0 & buf_byteen_0[3]; // @[lsu_bus_buffer.scala 141:95] + wire _T_143 = _T_141 & ldst_byteen_lo_m[3]; // @[lsu_bus_buffer.scala 141:114] wire [3:0] ld_byte_hitvec_lo_3 = {_T_155,_T_151,_T_147,_T_143}; // @[Cat.scala 29:58] - wire [3:0] _T_360 = ld_byte_hitvec_lo_3 & buf_age_younger_3; // @[lsu_bus_buffer.scala 145:122] - wire _T_361 = |_T_360; // @[lsu_bus_buffer.scala 145:144] - wire _T_362 = ~_T_361; // @[lsu_bus_buffer.scala 145:99] - wire _T_363 = ld_byte_hitvec_lo_3[3] & _T_362; // @[lsu_bus_buffer.scala 145:97] - wire _T_365 = ~ld_byte_ibuf_hit_lo[3]; // @[lsu_bus_buffer.scala 145:150] - wire _T_366 = _T_363 & _T_365; // @[lsu_bus_buffer.scala 145:148] - wire [3:0] _T_352 = ld_byte_hitvec_lo_3 & buf_age_younger_2; // @[lsu_bus_buffer.scala 145:122] - wire _T_353 = |_T_352; // @[lsu_bus_buffer.scala 145:144] - wire _T_354 = ~_T_353; // @[lsu_bus_buffer.scala 145:99] - wire _T_355 = ld_byte_hitvec_lo_3[2] & _T_354; // @[lsu_bus_buffer.scala 145:97] - wire _T_358 = _T_355 & _T_365; // @[lsu_bus_buffer.scala 145:148] - wire [3:0] _T_344 = ld_byte_hitvec_lo_3 & buf_age_younger_1; // @[lsu_bus_buffer.scala 145:122] - wire _T_345 = |_T_344; // @[lsu_bus_buffer.scala 145:144] - wire _T_346 = ~_T_345; // @[lsu_bus_buffer.scala 145:99] - wire _T_347 = ld_byte_hitvec_lo_3[1] & _T_346; // @[lsu_bus_buffer.scala 145:97] - wire _T_350 = _T_347 & _T_365; // @[lsu_bus_buffer.scala 145:148] - wire [3:0] _T_336 = ld_byte_hitvec_lo_3 & buf_age_younger_0; // @[lsu_bus_buffer.scala 145:122] - wire _T_337 = |_T_336; // @[lsu_bus_buffer.scala 145:144] - wire _T_338 = ~_T_337; // @[lsu_bus_buffer.scala 145:99] - wire _T_339 = ld_byte_hitvec_lo_3[0] & _T_338; // @[lsu_bus_buffer.scala 145:97] - wire _T_342 = _T_339 & _T_365; // @[lsu_bus_buffer.scala 145:148] + wire [3:0] _T_360 = ld_byte_hitvec_lo_3 & buf_age_younger_3; // @[lsu_bus_buffer.scala 146:122] + wire _T_361 = |_T_360; // @[lsu_bus_buffer.scala 146:144] + wire _T_362 = ~_T_361; // @[lsu_bus_buffer.scala 146:99] + wire _T_363 = ld_byte_hitvec_lo_3[3] & _T_362; // @[lsu_bus_buffer.scala 146:97] + wire _T_365 = ~ld_byte_ibuf_hit_lo[3]; // @[lsu_bus_buffer.scala 146:150] + wire _T_366 = _T_363 & _T_365; // @[lsu_bus_buffer.scala 146:148] + wire [3:0] _T_352 = ld_byte_hitvec_lo_3 & buf_age_younger_2; // @[lsu_bus_buffer.scala 146:122] + wire _T_353 = |_T_352; // @[lsu_bus_buffer.scala 146:144] + wire _T_354 = ~_T_353; // @[lsu_bus_buffer.scala 146:99] + wire _T_355 = ld_byte_hitvec_lo_3[2] & _T_354; // @[lsu_bus_buffer.scala 146:97] + wire _T_358 = _T_355 & _T_365; // @[lsu_bus_buffer.scala 146:148] + wire [3:0] _T_344 = ld_byte_hitvec_lo_3 & buf_age_younger_1; // @[lsu_bus_buffer.scala 146:122] + wire _T_345 = |_T_344; // @[lsu_bus_buffer.scala 146:144] + wire _T_346 = ~_T_345; // @[lsu_bus_buffer.scala 146:99] + wire _T_347 = ld_byte_hitvec_lo_3[1] & _T_346; // @[lsu_bus_buffer.scala 146:97] + wire _T_350 = _T_347 & _T_365; // @[lsu_bus_buffer.scala 146:148] + wire [3:0] _T_336 = ld_byte_hitvec_lo_3 & buf_age_younger_0; // @[lsu_bus_buffer.scala 146:122] + wire _T_337 = |_T_336; // @[lsu_bus_buffer.scala 146:144] + wire _T_338 = ~_T_337; // @[lsu_bus_buffer.scala 146:99] + wire _T_339 = ld_byte_hitvec_lo_3[0] & _T_338; // @[lsu_bus_buffer.scala 146:97] + wire _T_342 = _T_339 & _T_365; // @[lsu_bus_buffer.scala 146:148] wire [3:0] ld_byte_hitvecfn_lo_3 = {_T_366,_T_358,_T_350,_T_342}; // @[Cat.scala 29:58] - wire _T_65 = |ld_byte_hitvecfn_lo_3; // @[lsu_bus_buffer.scala 137:73] - wire _T_67 = _T_65 | ld_byte_ibuf_hit_lo[3]; // @[lsu_bus_buffer.scala 137:77] + wire _T_65 = |ld_byte_hitvecfn_lo_3; // @[lsu_bus_buffer.scala 138:73] + wire _T_67 = _T_65 | ld_byte_ibuf_hit_lo[3]; // @[lsu_bus_buffer.scala 138:77] wire [2:0] _T_69 = {_T_67,_T_64,_T_61}; // @[Cat.scala 29:58] - wire _T_171 = ld_addr_hitvec_hi_3 & buf_byteen_3[0]; // @[lsu_bus_buffer.scala 141:95] - wire _T_173 = _T_171 & ldst_byteen_hi_m[0]; // @[lsu_bus_buffer.scala 141:114] - wire _T_167 = ld_addr_hitvec_hi_2 & buf_byteen_2[0]; // @[lsu_bus_buffer.scala 141:95] - wire _T_169 = _T_167 & ldst_byteen_hi_m[0]; // @[lsu_bus_buffer.scala 141:114] - wire _T_163 = ld_addr_hitvec_hi_1 & buf_byteen_1[0]; // @[lsu_bus_buffer.scala 141:95] - wire _T_165 = _T_163 & ldst_byteen_hi_m[0]; // @[lsu_bus_buffer.scala 141:114] - wire _T_159 = ld_addr_hitvec_hi_0 & buf_byteen_0[0]; // @[lsu_bus_buffer.scala 141:95] - wire _T_161 = _T_159 & ldst_byteen_hi_m[0]; // @[lsu_bus_buffer.scala 141:114] + wire _T_171 = ld_addr_hitvec_hi_3 & buf_byteen_3[0]; // @[lsu_bus_buffer.scala 142:95] + wire _T_173 = _T_171 & ldst_byteen_hi_m[0]; // @[lsu_bus_buffer.scala 142:114] + wire _T_167 = ld_addr_hitvec_hi_2 & buf_byteen_2[0]; // @[lsu_bus_buffer.scala 142:95] + wire _T_169 = _T_167 & ldst_byteen_hi_m[0]; // @[lsu_bus_buffer.scala 142:114] + wire _T_163 = ld_addr_hitvec_hi_1 & buf_byteen_1[0]; // @[lsu_bus_buffer.scala 142:95] + wire _T_165 = _T_163 & ldst_byteen_hi_m[0]; // @[lsu_bus_buffer.scala 142:114] + wire _T_159 = ld_addr_hitvec_hi_0 & buf_byteen_0[0]; // @[lsu_bus_buffer.scala 142:95] + wire _T_161 = _T_159 & ldst_byteen_hi_m[0]; // @[lsu_bus_buffer.scala 142:114] wire [3:0] ld_byte_hitvec_hi_0 = {_T_173,_T_169,_T_165,_T_161}; // @[Cat.scala 29:58] - wire [3:0] _T_395 = ld_byte_hitvec_hi_0 & buf_age_younger_3; // @[lsu_bus_buffer.scala 146:122] - wire _T_396 = |_T_395; // @[lsu_bus_buffer.scala 146:144] - wire _T_397 = ~_T_396; // @[lsu_bus_buffer.scala 146:99] - wire _T_398 = ld_byte_hitvec_hi_0[3] & _T_397; // @[lsu_bus_buffer.scala 146:97] - wire _T_517 = io_end_addr_m[31:2] == ibuf_addr[31:2]; // @[lsu_bus_buffer.scala 152:51] - wire _T_518 = _T_517 & ibuf_write; // @[lsu_bus_buffer.scala 152:73] - wire _T_519 = _T_518 & ibuf_valid; // @[lsu_bus_buffer.scala 152:86] - wire ld_addr_ibuf_hit_hi = _T_519 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 152:99] + wire [3:0] _T_395 = ld_byte_hitvec_hi_0 & buf_age_younger_3; // @[lsu_bus_buffer.scala 147:122] + wire _T_396 = |_T_395; // @[lsu_bus_buffer.scala 147:144] + wire _T_397 = ~_T_396; // @[lsu_bus_buffer.scala 147:99] + wire _T_398 = ld_byte_hitvec_hi_0[3] & _T_397; // @[lsu_bus_buffer.scala 147:97] + wire _T_517 = io_end_addr_m[31:2] == ibuf_addr[31:2]; // @[lsu_bus_buffer.scala 153:51] + wire _T_518 = _T_517 & ibuf_write; // @[lsu_bus_buffer.scala 153:73] + wire _T_519 = _T_518 & ibuf_valid; // @[lsu_bus_buffer.scala 153:86] + wire ld_addr_ibuf_hit_hi = _T_519 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 153:99] wire [3:0] _T_525 = ld_addr_ibuf_hit_hi ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_526 = _T_525 & ibuf_byteen; // @[lsu_bus_buffer.scala 157:55] - wire [3:0] ld_byte_ibuf_hit_hi = _T_526 & ldst_byteen_hi_m; // @[lsu_bus_buffer.scala 157:69] - wire _T_400 = ~ld_byte_ibuf_hit_hi[0]; // @[lsu_bus_buffer.scala 146:150] - wire _T_401 = _T_398 & _T_400; // @[lsu_bus_buffer.scala 146:148] - wire [3:0] _T_387 = ld_byte_hitvec_hi_0 & buf_age_younger_2; // @[lsu_bus_buffer.scala 146:122] - wire _T_388 = |_T_387; // @[lsu_bus_buffer.scala 146:144] - wire _T_389 = ~_T_388; // @[lsu_bus_buffer.scala 146:99] - wire _T_390 = ld_byte_hitvec_hi_0[2] & _T_389; // @[lsu_bus_buffer.scala 146:97] - wire _T_393 = _T_390 & _T_400; // @[lsu_bus_buffer.scala 146:148] - wire [3:0] _T_379 = ld_byte_hitvec_hi_0 & buf_age_younger_1; // @[lsu_bus_buffer.scala 146:122] - wire _T_380 = |_T_379; // @[lsu_bus_buffer.scala 146:144] - wire _T_381 = ~_T_380; // @[lsu_bus_buffer.scala 146:99] - wire _T_382 = ld_byte_hitvec_hi_0[1] & _T_381; // @[lsu_bus_buffer.scala 146:97] - wire _T_385 = _T_382 & _T_400; // @[lsu_bus_buffer.scala 146:148] - wire [3:0] _T_371 = ld_byte_hitvec_hi_0 & buf_age_younger_0; // @[lsu_bus_buffer.scala 146:122] - wire _T_372 = |_T_371; // @[lsu_bus_buffer.scala 146:144] - wire _T_373 = ~_T_372; // @[lsu_bus_buffer.scala 146:99] - wire _T_374 = ld_byte_hitvec_hi_0[0] & _T_373; // @[lsu_bus_buffer.scala 146:97] - wire _T_377 = _T_374 & _T_400; // @[lsu_bus_buffer.scala 146:148] + wire [3:0] _T_526 = _T_525 & ibuf_byteen; // @[lsu_bus_buffer.scala 158:55] + wire [3:0] ld_byte_ibuf_hit_hi = _T_526 & ldst_byteen_hi_m; // @[lsu_bus_buffer.scala 158:69] + wire _T_400 = ~ld_byte_ibuf_hit_hi[0]; // @[lsu_bus_buffer.scala 147:150] + wire _T_401 = _T_398 & _T_400; // @[lsu_bus_buffer.scala 147:148] + wire [3:0] _T_387 = ld_byte_hitvec_hi_0 & buf_age_younger_2; // @[lsu_bus_buffer.scala 147:122] + wire _T_388 = |_T_387; // @[lsu_bus_buffer.scala 147:144] + wire _T_389 = ~_T_388; // @[lsu_bus_buffer.scala 147:99] + wire _T_390 = ld_byte_hitvec_hi_0[2] & _T_389; // @[lsu_bus_buffer.scala 147:97] + wire _T_393 = _T_390 & _T_400; // @[lsu_bus_buffer.scala 147:148] + wire [3:0] _T_379 = ld_byte_hitvec_hi_0 & buf_age_younger_1; // @[lsu_bus_buffer.scala 147:122] + wire _T_380 = |_T_379; // @[lsu_bus_buffer.scala 147:144] + wire _T_381 = ~_T_380; // @[lsu_bus_buffer.scala 147:99] + wire _T_382 = ld_byte_hitvec_hi_0[1] & _T_381; // @[lsu_bus_buffer.scala 147:97] + wire _T_385 = _T_382 & _T_400; // @[lsu_bus_buffer.scala 147:148] + wire [3:0] _T_371 = ld_byte_hitvec_hi_0 & buf_age_younger_0; // @[lsu_bus_buffer.scala 147:122] + wire _T_372 = |_T_371; // @[lsu_bus_buffer.scala 147:144] + wire _T_373 = ~_T_372; // @[lsu_bus_buffer.scala 147:99] + wire _T_374 = ld_byte_hitvec_hi_0[0] & _T_373; // @[lsu_bus_buffer.scala 147:97] + wire _T_377 = _T_374 & _T_400; // @[lsu_bus_buffer.scala 147:148] wire [3:0] ld_byte_hitvecfn_hi_0 = {_T_401,_T_393,_T_385,_T_377}; // @[Cat.scala 29:58] - wire _T_71 = |ld_byte_hitvecfn_hi_0; // @[lsu_bus_buffer.scala 138:73] - wire _T_73 = _T_71 | ld_byte_ibuf_hit_hi[0]; // @[lsu_bus_buffer.scala 138:77] - wire _T_189 = ld_addr_hitvec_hi_3 & buf_byteen_3[1]; // @[lsu_bus_buffer.scala 141:95] - wire _T_191 = _T_189 & ldst_byteen_hi_m[1]; // @[lsu_bus_buffer.scala 141:114] - wire _T_185 = ld_addr_hitvec_hi_2 & buf_byteen_2[1]; // @[lsu_bus_buffer.scala 141:95] - wire _T_187 = _T_185 & ldst_byteen_hi_m[1]; // @[lsu_bus_buffer.scala 141:114] - wire _T_181 = ld_addr_hitvec_hi_1 & buf_byteen_1[1]; // @[lsu_bus_buffer.scala 141:95] - wire _T_183 = _T_181 & ldst_byteen_hi_m[1]; // @[lsu_bus_buffer.scala 141:114] - wire _T_177 = ld_addr_hitvec_hi_0 & buf_byteen_0[1]; // @[lsu_bus_buffer.scala 141:95] - wire _T_179 = _T_177 & ldst_byteen_hi_m[1]; // @[lsu_bus_buffer.scala 141:114] + wire _T_71 = |ld_byte_hitvecfn_hi_0; // @[lsu_bus_buffer.scala 139:73] + wire _T_73 = _T_71 | ld_byte_ibuf_hit_hi[0]; // @[lsu_bus_buffer.scala 139:77] + wire _T_189 = ld_addr_hitvec_hi_3 & buf_byteen_3[1]; // @[lsu_bus_buffer.scala 142:95] + wire _T_191 = _T_189 & ldst_byteen_hi_m[1]; // @[lsu_bus_buffer.scala 142:114] + wire _T_185 = ld_addr_hitvec_hi_2 & buf_byteen_2[1]; // @[lsu_bus_buffer.scala 142:95] + wire _T_187 = _T_185 & ldst_byteen_hi_m[1]; // @[lsu_bus_buffer.scala 142:114] + wire _T_181 = ld_addr_hitvec_hi_1 & buf_byteen_1[1]; // @[lsu_bus_buffer.scala 142:95] + wire _T_183 = _T_181 & ldst_byteen_hi_m[1]; // @[lsu_bus_buffer.scala 142:114] + wire _T_177 = ld_addr_hitvec_hi_0 & buf_byteen_0[1]; // @[lsu_bus_buffer.scala 142:95] + wire _T_179 = _T_177 & ldst_byteen_hi_m[1]; // @[lsu_bus_buffer.scala 142:114] wire [3:0] ld_byte_hitvec_hi_1 = {_T_191,_T_187,_T_183,_T_179}; // @[Cat.scala 29:58] - wire [3:0] _T_430 = ld_byte_hitvec_hi_1 & buf_age_younger_3; // @[lsu_bus_buffer.scala 146:122] - wire _T_431 = |_T_430; // @[lsu_bus_buffer.scala 146:144] - wire _T_432 = ~_T_431; // @[lsu_bus_buffer.scala 146:99] - wire _T_433 = ld_byte_hitvec_hi_1[3] & _T_432; // @[lsu_bus_buffer.scala 146:97] - wire _T_435 = ~ld_byte_ibuf_hit_hi[1]; // @[lsu_bus_buffer.scala 146:150] - wire _T_436 = _T_433 & _T_435; // @[lsu_bus_buffer.scala 146:148] - wire [3:0] _T_422 = ld_byte_hitvec_hi_1 & buf_age_younger_2; // @[lsu_bus_buffer.scala 146:122] - wire _T_423 = |_T_422; // @[lsu_bus_buffer.scala 146:144] - wire _T_424 = ~_T_423; // @[lsu_bus_buffer.scala 146:99] - wire _T_425 = ld_byte_hitvec_hi_1[2] & _T_424; // @[lsu_bus_buffer.scala 146:97] - wire _T_428 = _T_425 & _T_435; // @[lsu_bus_buffer.scala 146:148] - wire [3:0] _T_414 = ld_byte_hitvec_hi_1 & buf_age_younger_1; // @[lsu_bus_buffer.scala 146:122] - wire _T_415 = |_T_414; // @[lsu_bus_buffer.scala 146:144] - wire _T_416 = ~_T_415; // @[lsu_bus_buffer.scala 146:99] - wire _T_417 = ld_byte_hitvec_hi_1[1] & _T_416; // @[lsu_bus_buffer.scala 146:97] - wire _T_420 = _T_417 & _T_435; // @[lsu_bus_buffer.scala 146:148] - wire [3:0] _T_406 = ld_byte_hitvec_hi_1 & buf_age_younger_0; // @[lsu_bus_buffer.scala 146:122] - wire _T_407 = |_T_406; // @[lsu_bus_buffer.scala 146:144] - wire _T_408 = ~_T_407; // @[lsu_bus_buffer.scala 146:99] - wire _T_409 = ld_byte_hitvec_hi_1[0] & _T_408; // @[lsu_bus_buffer.scala 146:97] - wire _T_412 = _T_409 & _T_435; // @[lsu_bus_buffer.scala 146:148] + wire [3:0] _T_430 = ld_byte_hitvec_hi_1 & buf_age_younger_3; // @[lsu_bus_buffer.scala 147:122] + wire _T_431 = |_T_430; // @[lsu_bus_buffer.scala 147:144] + wire _T_432 = ~_T_431; // @[lsu_bus_buffer.scala 147:99] + wire _T_433 = ld_byte_hitvec_hi_1[3] & _T_432; // @[lsu_bus_buffer.scala 147:97] + wire _T_435 = ~ld_byte_ibuf_hit_hi[1]; // @[lsu_bus_buffer.scala 147:150] + wire _T_436 = _T_433 & _T_435; // @[lsu_bus_buffer.scala 147:148] + wire [3:0] _T_422 = ld_byte_hitvec_hi_1 & buf_age_younger_2; // @[lsu_bus_buffer.scala 147:122] + wire _T_423 = |_T_422; // @[lsu_bus_buffer.scala 147:144] + wire _T_424 = ~_T_423; // @[lsu_bus_buffer.scala 147:99] + wire _T_425 = ld_byte_hitvec_hi_1[2] & _T_424; // @[lsu_bus_buffer.scala 147:97] + wire _T_428 = _T_425 & _T_435; // @[lsu_bus_buffer.scala 147:148] + wire [3:0] _T_414 = ld_byte_hitvec_hi_1 & buf_age_younger_1; // @[lsu_bus_buffer.scala 147:122] + wire _T_415 = |_T_414; // @[lsu_bus_buffer.scala 147:144] + wire _T_416 = ~_T_415; // @[lsu_bus_buffer.scala 147:99] + wire _T_417 = ld_byte_hitvec_hi_1[1] & _T_416; // @[lsu_bus_buffer.scala 147:97] + wire _T_420 = _T_417 & _T_435; // @[lsu_bus_buffer.scala 147:148] + wire [3:0] _T_406 = ld_byte_hitvec_hi_1 & buf_age_younger_0; // @[lsu_bus_buffer.scala 147:122] + wire _T_407 = |_T_406; // @[lsu_bus_buffer.scala 147:144] + wire _T_408 = ~_T_407; // @[lsu_bus_buffer.scala 147:99] + wire _T_409 = ld_byte_hitvec_hi_1[0] & _T_408; // @[lsu_bus_buffer.scala 147:97] + wire _T_412 = _T_409 & _T_435; // @[lsu_bus_buffer.scala 147:148] wire [3:0] ld_byte_hitvecfn_hi_1 = {_T_436,_T_428,_T_420,_T_412}; // @[Cat.scala 29:58] - wire _T_74 = |ld_byte_hitvecfn_hi_1; // @[lsu_bus_buffer.scala 138:73] - wire _T_76 = _T_74 | ld_byte_ibuf_hit_hi[1]; // @[lsu_bus_buffer.scala 138:77] - wire _T_207 = ld_addr_hitvec_hi_3 & buf_byteen_3[2]; // @[lsu_bus_buffer.scala 141:95] - wire _T_209 = _T_207 & ldst_byteen_hi_m[2]; // @[lsu_bus_buffer.scala 141:114] - wire _T_203 = ld_addr_hitvec_hi_2 & buf_byteen_2[2]; // @[lsu_bus_buffer.scala 141:95] - wire _T_205 = _T_203 & ldst_byteen_hi_m[2]; // @[lsu_bus_buffer.scala 141:114] - wire _T_199 = ld_addr_hitvec_hi_1 & buf_byteen_1[2]; // @[lsu_bus_buffer.scala 141:95] - wire _T_201 = _T_199 & ldst_byteen_hi_m[2]; // @[lsu_bus_buffer.scala 141:114] - wire _T_195 = ld_addr_hitvec_hi_0 & buf_byteen_0[2]; // @[lsu_bus_buffer.scala 141:95] - wire _T_197 = _T_195 & ldst_byteen_hi_m[2]; // @[lsu_bus_buffer.scala 141:114] + wire _T_74 = |ld_byte_hitvecfn_hi_1; // @[lsu_bus_buffer.scala 139:73] + wire _T_76 = _T_74 | ld_byte_ibuf_hit_hi[1]; // @[lsu_bus_buffer.scala 139:77] + wire _T_207 = ld_addr_hitvec_hi_3 & buf_byteen_3[2]; // @[lsu_bus_buffer.scala 142:95] + wire _T_209 = _T_207 & ldst_byteen_hi_m[2]; // @[lsu_bus_buffer.scala 142:114] + wire _T_203 = ld_addr_hitvec_hi_2 & buf_byteen_2[2]; // @[lsu_bus_buffer.scala 142:95] + wire _T_205 = _T_203 & ldst_byteen_hi_m[2]; // @[lsu_bus_buffer.scala 142:114] + wire _T_199 = ld_addr_hitvec_hi_1 & buf_byteen_1[2]; // @[lsu_bus_buffer.scala 142:95] + wire _T_201 = _T_199 & ldst_byteen_hi_m[2]; // @[lsu_bus_buffer.scala 142:114] + wire _T_195 = ld_addr_hitvec_hi_0 & buf_byteen_0[2]; // @[lsu_bus_buffer.scala 142:95] + wire _T_197 = _T_195 & ldst_byteen_hi_m[2]; // @[lsu_bus_buffer.scala 142:114] wire [3:0] ld_byte_hitvec_hi_2 = {_T_209,_T_205,_T_201,_T_197}; // @[Cat.scala 29:58] - wire [3:0] _T_465 = ld_byte_hitvec_hi_2 & buf_age_younger_3; // @[lsu_bus_buffer.scala 146:122] - wire _T_466 = |_T_465; // @[lsu_bus_buffer.scala 146:144] - wire _T_467 = ~_T_466; // @[lsu_bus_buffer.scala 146:99] - wire _T_468 = ld_byte_hitvec_hi_2[3] & _T_467; // @[lsu_bus_buffer.scala 146:97] - wire _T_470 = ~ld_byte_ibuf_hit_hi[2]; // @[lsu_bus_buffer.scala 146:150] - wire _T_471 = _T_468 & _T_470; // @[lsu_bus_buffer.scala 146:148] - wire [3:0] _T_457 = ld_byte_hitvec_hi_2 & buf_age_younger_2; // @[lsu_bus_buffer.scala 146:122] - wire _T_458 = |_T_457; // @[lsu_bus_buffer.scala 146:144] - wire _T_459 = ~_T_458; // @[lsu_bus_buffer.scala 146:99] - wire _T_460 = ld_byte_hitvec_hi_2[2] & _T_459; // @[lsu_bus_buffer.scala 146:97] - wire _T_463 = _T_460 & _T_470; // @[lsu_bus_buffer.scala 146:148] - wire [3:0] _T_449 = ld_byte_hitvec_hi_2 & buf_age_younger_1; // @[lsu_bus_buffer.scala 146:122] - wire _T_450 = |_T_449; // @[lsu_bus_buffer.scala 146:144] - wire _T_451 = ~_T_450; // @[lsu_bus_buffer.scala 146:99] - wire _T_452 = ld_byte_hitvec_hi_2[1] & _T_451; // @[lsu_bus_buffer.scala 146:97] - wire _T_455 = _T_452 & _T_470; // @[lsu_bus_buffer.scala 146:148] - wire [3:0] _T_441 = ld_byte_hitvec_hi_2 & buf_age_younger_0; // @[lsu_bus_buffer.scala 146:122] - wire _T_442 = |_T_441; // @[lsu_bus_buffer.scala 146:144] - wire _T_443 = ~_T_442; // @[lsu_bus_buffer.scala 146:99] - wire _T_444 = ld_byte_hitvec_hi_2[0] & _T_443; // @[lsu_bus_buffer.scala 146:97] - wire _T_447 = _T_444 & _T_470; // @[lsu_bus_buffer.scala 146:148] + wire [3:0] _T_465 = ld_byte_hitvec_hi_2 & buf_age_younger_3; // @[lsu_bus_buffer.scala 147:122] + wire _T_466 = |_T_465; // @[lsu_bus_buffer.scala 147:144] + wire _T_467 = ~_T_466; // @[lsu_bus_buffer.scala 147:99] + wire _T_468 = ld_byte_hitvec_hi_2[3] & _T_467; // @[lsu_bus_buffer.scala 147:97] + wire _T_470 = ~ld_byte_ibuf_hit_hi[2]; // @[lsu_bus_buffer.scala 147:150] + wire _T_471 = _T_468 & _T_470; // @[lsu_bus_buffer.scala 147:148] + wire [3:0] _T_457 = ld_byte_hitvec_hi_2 & buf_age_younger_2; // @[lsu_bus_buffer.scala 147:122] + wire _T_458 = |_T_457; // @[lsu_bus_buffer.scala 147:144] + wire _T_459 = ~_T_458; // @[lsu_bus_buffer.scala 147:99] + wire _T_460 = ld_byte_hitvec_hi_2[2] & _T_459; // @[lsu_bus_buffer.scala 147:97] + wire _T_463 = _T_460 & _T_470; // @[lsu_bus_buffer.scala 147:148] + wire [3:0] _T_449 = ld_byte_hitvec_hi_2 & buf_age_younger_1; // @[lsu_bus_buffer.scala 147:122] + wire _T_450 = |_T_449; // @[lsu_bus_buffer.scala 147:144] + wire _T_451 = ~_T_450; // @[lsu_bus_buffer.scala 147:99] + wire _T_452 = ld_byte_hitvec_hi_2[1] & _T_451; // @[lsu_bus_buffer.scala 147:97] + wire _T_455 = _T_452 & _T_470; // @[lsu_bus_buffer.scala 147:148] + wire [3:0] _T_441 = ld_byte_hitvec_hi_2 & buf_age_younger_0; // @[lsu_bus_buffer.scala 147:122] + wire _T_442 = |_T_441; // @[lsu_bus_buffer.scala 147:144] + wire _T_443 = ~_T_442; // @[lsu_bus_buffer.scala 147:99] + wire _T_444 = ld_byte_hitvec_hi_2[0] & _T_443; // @[lsu_bus_buffer.scala 147:97] + wire _T_447 = _T_444 & _T_470; // @[lsu_bus_buffer.scala 147:148] wire [3:0] ld_byte_hitvecfn_hi_2 = {_T_471,_T_463,_T_455,_T_447}; // @[Cat.scala 29:58] - wire _T_77 = |ld_byte_hitvecfn_hi_2; // @[lsu_bus_buffer.scala 138:73] - wire _T_79 = _T_77 | ld_byte_ibuf_hit_hi[2]; // @[lsu_bus_buffer.scala 138:77] - wire _T_225 = ld_addr_hitvec_hi_3 & buf_byteen_3[3]; // @[lsu_bus_buffer.scala 141:95] - wire _T_227 = _T_225 & ldst_byteen_hi_m[3]; // @[lsu_bus_buffer.scala 141:114] - wire _T_221 = ld_addr_hitvec_hi_2 & buf_byteen_2[3]; // @[lsu_bus_buffer.scala 141:95] - wire _T_223 = _T_221 & ldst_byteen_hi_m[3]; // @[lsu_bus_buffer.scala 141:114] - wire _T_217 = ld_addr_hitvec_hi_1 & buf_byteen_1[3]; // @[lsu_bus_buffer.scala 141:95] - wire _T_219 = _T_217 & ldst_byteen_hi_m[3]; // @[lsu_bus_buffer.scala 141:114] - wire _T_213 = ld_addr_hitvec_hi_0 & buf_byteen_0[3]; // @[lsu_bus_buffer.scala 141:95] - wire _T_215 = _T_213 & ldst_byteen_hi_m[3]; // @[lsu_bus_buffer.scala 141:114] + wire _T_77 = |ld_byte_hitvecfn_hi_2; // @[lsu_bus_buffer.scala 139:73] + wire _T_79 = _T_77 | ld_byte_ibuf_hit_hi[2]; // @[lsu_bus_buffer.scala 139:77] + wire _T_225 = ld_addr_hitvec_hi_3 & buf_byteen_3[3]; // @[lsu_bus_buffer.scala 142:95] + wire _T_227 = _T_225 & ldst_byteen_hi_m[3]; // @[lsu_bus_buffer.scala 142:114] + wire _T_221 = ld_addr_hitvec_hi_2 & buf_byteen_2[3]; // @[lsu_bus_buffer.scala 142:95] + wire _T_223 = _T_221 & ldst_byteen_hi_m[3]; // @[lsu_bus_buffer.scala 142:114] + wire _T_217 = ld_addr_hitvec_hi_1 & buf_byteen_1[3]; // @[lsu_bus_buffer.scala 142:95] + wire _T_219 = _T_217 & ldst_byteen_hi_m[3]; // @[lsu_bus_buffer.scala 142:114] + wire _T_213 = ld_addr_hitvec_hi_0 & buf_byteen_0[3]; // @[lsu_bus_buffer.scala 142:95] + wire _T_215 = _T_213 & ldst_byteen_hi_m[3]; // @[lsu_bus_buffer.scala 142:114] wire [3:0] ld_byte_hitvec_hi_3 = {_T_227,_T_223,_T_219,_T_215}; // @[Cat.scala 29:58] - wire [3:0] _T_500 = ld_byte_hitvec_hi_3 & buf_age_younger_3; // @[lsu_bus_buffer.scala 146:122] - wire _T_501 = |_T_500; // @[lsu_bus_buffer.scala 146:144] - wire _T_502 = ~_T_501; // @[lsu_bus_buffer.scala 146:99] - wire _T_503 = ld_byte_hitvec_hi_3[3] & _T_502; // @[lsu_bus_buffer.scala 146:97] - wire _T_505 = ~ld_byte_ibuf_hit_hi[3]; // @[lsu_bus_buffer.scala 146:150] - wire _T_506 = _T_503 & _T_505; // @[lsu_bus_buffer.scala 146:148] - wire [3:0] _T_492 = ld_byte_hitvec_hi_3 & buf_age_younger_2; // @[lsu_bus_buffer.scala 146:122] - wire _T_493 = |_T_492; // @[lsu_bus_buffer.scala 146:144] - wire _T_494 = ~_T_493; // @[lsu_bus_buffer.scala 146:99] - wire _T_495 = ld_byte_hitvec_hi_3[2] & _T_494; // @[lsu_bus_buffer.scala 146:97] - wire _T_498 = _T_495 & _T_505; // @[lsu_bus_buffer.scala 146:148] - wire [3:0] _T_484 = ld_byte_hitvec_hi_3 & buf_age_younger_1; // @[lsu_bus_buffer.scala 146:122] - wire _T_485 = |_T_484; // @[lsu_bus_buffer.scala 146:144] - wire _T_486 = ~_T_485; // @[lsu_bus_buffer.scala 146:99] - wire _T_487 = ld_byte_hitvec_hi_3[1] & _T_486; // @[lsu_bus_buffer.scala 146:97] - wire _T_490 = _T_487 & _T_505; // @[lsu_bus_buffer.scala 146:148] - wire [3:0] _T_476 = ld_byte_hitvec_hi_3 & buf_age_younger_0; // @[lsu_bus_buffer.scala 146:122] - wire _T_477 = |_T_476; // @[lsu_bus_buffer.scala 146:144] - wire _T_478 = ~_T_477; // @[lsu_bus_buffer.scala 146:99] - wire _T_479 = ld_byte_hitvec_hi_3[0] & _T_478; // @[lsu_bus_buffer.scala 146:97] - wire _T_482 = _T_479 & _T_505; // @[lsu_bus_buffer.scala 146:148] + wire [3:0] _T_500 = ld_byte_hitvec_hi_3 & buf_age_younger_3; // @[lsu_bus_buffer.scala 147:122] + wire _T_501 = |_T_500; // @[lsu_bus_buffer.scala 147:144] + wire _T_502 = ~_T_501; // @[lsu_bus_buffer.scala 147:99] + wire _T_503 = ld_byte_hitvec_hi_3[3] & _T_502; // @[lsu_bus_buffer.scala 147:97] + wire _T_505 = ~ld_byte_ibuf_hit_hi[3]; // @[lsu_bus_buffer.scala 147:150] + wire _T_506 = _T_503 & _T_505; // @[lsu_bus_buffer.scala 147:148] + wire [3:0] _T_492 = ld_byte_hitvec_hi_3 & buf_age_younger_2; // @[lsu_bus_buffer.scala 147:122] + wire _T_493 = |_T_492; // @[lsu_bus_buffer.scala 147:144] + wire _T_494 = ~_T_493; // @[lsu_bus_buffer.scala 147:99] + wire _T_495 = ld_byte_hitvec_hi_3[2] & _T_494; // @[lsu_bus_buffer.scala 147:97] + wire _T_498 = _T_495 & _T_505; // @[lsu_bus_buffer.scala 147:148] + wire [3:0] _T_484 = ld_byte_hitvec_hi_3 & buf_age_younger_1; // @[lsu_bus_buffer.scala 147:122] + wire _T_485 = |_T_484; // @[lsu_bus_buffer.scala 147:144] + wire _T_486 = ~_T_485; // @[lsu_bus_buffer.scala 147:99] + wire _T_487 = ld_byte_hitvec_hi_3[1] & _T_486; // @[lsu_bus_buffer.scala 147:97] + wire _T_490 = _T_487 & _T_505; // @[lsu_bus_buffer.scala 147:148] + wire [3:0] _T_476 = ld_byte_hitvec_hi_3 & buf_age_younger_0; // @[lsu_bus_buffer.scala 147:122] + wire _T_477 = |_T_476; // @[lsu_bus_buffer.scala 147:144] + wire _T_478 = ~_T_477; // @[lsu_bus_buffer.scala 147:99] + wire _T_479 = ld_byte_hitvec_hi_3[0] & _T_478; // @[lsu_bus_buffer.scala 147:97] + wire _T_482 = _T_479 & _T_505; // @[lsu_bus_buffer.scala 147:148] wire [3:0] ld_byte_hitvecfn_hi_3 = {_T_506,_T_498,_T_490,_T_482}; // @[Cat.scala 29:58] - wire _T_80 = |ld_byte_hitvecfn_hi_3; // @[lsu_bus_buffer.scala 138:73] - wire _T_82 = _T_80 | ld_byte_ibuf_hit_hi[3]; // @[lsu_bus_buffer.scala 138:77] + wire _T_80 = |ld_byte_hitvecfn_hi_3; // @[lsu_bus_buffer.scala 139:73] + wire _T_82 = _T_80 | ld_byte_ibuf_hit_hi[3]; // @[lsu_bus_buffer.scala 139:77] wire [2:0] _T_84 = {_T_82,_T_79,_T_76}; // @[Cat.scala 29:58] wire [7:0] _T_530 = ld_byte_ibuf_hit_lo[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] wire [7:0] _T_533 = ld_byte_ibuf_hit_lo[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] @@ -68879,112 +68900,112 @@ module lsu_bus_buffer( wire [31:0] ld_fwddata_buf_hi_initial = {_T_553,_T_550,_T_547,_T_544}; // @[Cat.scala 29:58] wire [7:0] _T_558 = ld_byte_hitvecfn_lo_3[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] reg [31:0] buf_data_0; // @[lib.scala 374:16] - wire [7:0] _T_560 = _T_558 & buf_data_0[31:24]; // @[lsu_bus_buffer.scala 164:91] + wire [7:0] _T_560 = _T_558 & buf_data_0[31:24]; // @[lsu_bus_buffer.scala 165:91] wire [7:0] _T_563 = ld_byte_hitvecfn_lo_3[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] reg [31:0] buf_data_1; // @[lib.scala 374:16] - wire [7:0] _T_565 = _T_563 & buf_data_1[31:24]; // @[lsu_bus_buffer.scala 164:91] + wire [7:0] _T_565 = _T_563 & buf_data_1[31:24]; // @[lsu_bus_buffer.scala 165:91] wire [7:0] _T_568 = ld_byte_hitvecfn_lo_3[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] reg [31:0] buf_data_2; // @[lib.scala 374:16] - wire [7:0] _T_570 = _T_568 & buf_data_2[31:24]; // @[lsu_bus_buffer.scala 164:91] + wire [7:0] _T_570 = _T_568 & buf_data_2[31:24]; // @[lsu_bus_buffer.scala 165:91] wire [7:0] _T_573 = ld_byte_hitvecfn_lo_3[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] reg [31:0] buf_data_3; // @[lib.scala 374:16] - wire [7:0] _T_575 = _T_573 & buf_data_3[31:24]; // @[lsu_bus_buffer.scala 164:91] - wire [7:0] _T_576 = _T_560 | _T_565; // @[lsu_bus_buffer.scala 164:123] - wire [7:0] _T_577 = _T_576 | _T_570; // @[lsu_bus_buffer.scala 164:123] - wire [7:0] _T_578 = _T_577 | _T_575; // @[lsu_bus_buffer.scala 164:123] + wire [7:0] _T_575 = _T_573 & buf_data_3[31:24]; // @[lsu_bus_buffer.scala 165:91] + wire [7:0] _T_576 = _T_560 | _T_565; // @[lsu_bus_buffer.scala 165:123] + wire [7:0] _T_577 = _T_576 | _T_570; // @[lsu_bus_buffer.scala 165:123] + wire [7:0] _T_578 = _T_577 | _T_575; // @[lsu_bus_buffer.scala 165:123] wire [7:0] _T_581 = ld_byte_hitvecfn_lo_2[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_583 = _T_581 & buf_data_0[23:16]; // @[lsu_bus_buffer.scala 165:65] + wire [7:0] _T_583 = _T_581 & buf_data_0[23:16]; // @[lsu_bus_buffer.scala 166:65] wire [7:0] _T_586 = ld_byte_hitvecfn_lo_2[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_588 = _T_586 & buf_data_1[23:16]; // @[lsu_bus_buffer.scala 165:65] + wire [7:0] _T_588 = _T_586 & buf_data_1[23:16]; // @[lsu_bus_buffer.scala 166:65] wire [7:0] _T_591 = ld_byte_hitvecfn_lo_2[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_593 = _T_591 & buf_data_2[23:16]; // @[lsu_bus_buffer.scala 165:65] + wire [7:0] _T_593 = _T_591 & buf_data_2[23:16]; // @[lsu_bus_buffer.scala 166:65] wire [7:0] _T_596 = ld_byte_hitvecfn_lo_2[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_598 = _T_596 & buf_data_3[23:16]; // @[lsu_bus_buffer.scala 165:65] - wire [7:0] _T_599 = _T_583 | _T_588; // @[lsu_bus_buffer.scala 165:97] - wire [7:0] _T_600 = _T_599 | _T_593; // @[lsu_bus_buffer.scala 165:97] - wire [7:0] _T_601 = _T_600 | _T_598; // @[lsu_bus_buffer.scala 165:97] + wire [7:0] _T_598 = _T_596 & buf_data_3[23:16]; // @[lsu_bus_buffer.scala 166:65] + wire [7:0] _T_599 = _T_583 | _T_588; // @[lsu_bus_buffer.scala 166:97] + wire [7:0] _T_600 = _T_599 | _T_593; // @[lsu_bus_buffer.scala 166:97] + wire [7:0] _T_601 = _T_600 | _T_598; // @[lsu_bus_buffer.scala 166:97] wire [7:0] _T_604 = ld_byte_hitvecfn_lo_1[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_606 = _T_604 & buf_data_0[15:8]; // @[lsu_bus_buffer.scala 166:65] + wire [7:0] _T_606 = _T_604 & buf_data_0[15:8]; // @[lsu_bus_buffer.scala 167:65] wire [7:0] _T_609 = ld_byte_hitvecfn_lo_1[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_611 = _T_609 & buf_data_1[15:8]; // @[lsu_bus_buffer.scala 166:65] + wire [7:0] _T_611 = _T_609 & buf_data_1[15:8]; // @[lsu_bus_buffer.scala 167:65] wire [7:0] _T_614 = ld_byte_hitvecfn_lo_1[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_616 = _T_614 & buf_data_2[15:8]; // @[lsu_bus_buffer.scala 166:65] + wire [7:0] _T_616 = _T_614 & buf_data_2[15:8]; // @[lsu_bus_buffer.scala 167:65] wire [7:0] _T_619 = ld_byte_hitvecfn_lo_1[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_621 = _T_619 & buf_data_3[15:8]; // @[lsu_bus_buffer.scala 166:65] - wire [7:0] _T_622 = _T_606 | _T_611; // @[lsu_bus_buffer.scala 166:97] - wire [7:0] _T_623 = _T_622 | _T_616; // @[lsu_bus_buffer.scala 166:97] - wire [7:0] _T_624 = _T_623 | _T_621; // @[lsu_bus_buffer.scala 166:97] + wire [7:0] _T_621 = _T_619 & buf_data_3[15:8]; // @[lsu_bus_buffer.scala 167:65] + wire [7:0] _T_622 = _T_606 | _T_611; // @[lsu_bus_buffer.scala 167:97] + wire [7:0] _T_623 = _T_622 | _T_616; // @[lsu_bus_buffer.scala 167:97] + wire [7:0] _T_624 = _T_623 | _T_621; // @[lsu_bus_buffer.scala 167:97] wire [7:0] _T_627 = ld_byte_hitvecfn_lo_0[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_629 = _T_627 & buf_data_0[7:0]; // @[lsu_bus_buffer.scala 167:65] + wire [7:0] _T_629 = _T_627 & buf_data_0[7:0]; // @[lsu_bus_buffer.scala 168:65] wire [7:0] _T_632 = ld_byte_hitvecfn_lo_0[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_634 = _T_632 & buf_data_1[7:0]; // @[lsu_bus_buffer.scala 167:65] + wire [7:0] _T_634 = _T_632 & buf_data_1[7:0]; // @[lsu_bus_buffer.scala 168:65] wire [7:0] _T_637 = ld_byte_hitvecfn_lo_0[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_639 = _T_637 & buf_data_2[7:0]; // @[lsu_bus_buffer.scala 167:65] + wire [7:0] _T_639 = _T_637 & buf_data_2[7:0]; // @[lsu_bus_buffer.scala 168:65] wire [7:0] _T_642 = ld_byte_hitvecfn_lo_0[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_644 = _T_642 & buf_data_3[7:0]; // @[lsu_bus_buffer.scala 167:65] - wire [7:0] _T_645 = _T_629 | _T_634; // @[lsu_bus_buffer.scala 167:97] - wire [7:0] _T_646 = _T_645 | _T_639; // @[lsu_bus_buffer.scala 167:97] - wire [7:0] _T_647 = _T_646 | _T_644; // @[lsu_bus_buffer.scala 167:97] + wire [7:0] _T_644 = _T_642 & buf_data_3[7:0]; // @[lsu_bus_buffer.scala 168:65] + wire [7:0] _T_645 = _T_629 | _T_634; // @[lsu_bus_buffer.scala 168:97] + wire [7:0] _T_646 = _T_645 | _T_639; // @[lsu_bus_buffer.scala 168:97] + wire [7:0] _T_647 = _T_646 | _T_644; // @[lsu_bus_buffer.scala 168:97] wire [31:0] _T_650 = {_T_578,_T_601,_T_624,_T_647}; // @[Cat.scala 29:58] reg [31:0] ibuf_data; // @[lib.scala 374:16] - wire [31:0] _T_651 = ld_fwddata_buf_lo_initial & ibuf_data; // @[lsu_bus_buffer.scala 168:32] + wire [31:0] _T_651 = ld_fwddata_buf_lo_initial & ibuf_data; // @[lsu_bus_buffer.scala 169:32] wire [7:0] _T_655 = ld_byte_hitvecfn_hi_3[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_657 = _T_655 & buf_data_0[31:24]; // @[lsu_bus_buffer.scala 170:91] + wire [7:0] _T_657 = _T_655 & buf_data_0[31:24]; // @[lsu_bus_buffer.scala 171:91] wire [7:0] _T_660 = ld_byte_hitvecfn_hi_3[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_662 = _T_660 & buf_data_1[31:24]; // @[lsu_bus_buffer.scala 170:91] + wire [7:0] _T_662 = _T_660 & buf_data_1[31:24]; // @[lsu_bus_buffer.scala 171:91] wire [7:0] _T_665 = ld_byte_hitvecfn_hi_3[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_667 = _T_665 & buf_data_2[31:24]; // @[lsu_bus_buffer.scala 170:91] + wire [7:0] _T_667 = _T_665 & buf_data_2[31:24]; // @[lsu_bus_buffer.scala 171:91] wire [7:0] _T_670 = ld_byte_hitvecfn_hi_3[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_672 = _T_670 & buf_data_3[31:24]; // @[lsu_bus_buffer.scala 170:91] - wire [7:0] _T_673 = _T_657 | _T_662; // @[lsu_bus_buffer.scala 170:123] - wire [7:0] _T_674 = _T_673 | _T_667; // @[lsu_bus_buffer.scala 170:123] - wire [7:0] _T_675 = _T_674 | _T_672; // @[lsu_bus_buffer.scala 170:123] + wire [7:0] _T_672 = _T_670 & buf_data_3[31:24]; // @[lsu_bus_buffer.scala 171:91] + wire [7:0] _T_673 = _T_657 | _T_662; // @[lsu_bus_buffer.scala 171:123] + wire [7:0] _T_674 = _T_673 | _T_667; // @[lsu_bus_buffer.scala 171:123] + wire [7:0] _T_675 = _T_674 | _T_672; // @[lsu_bus_buffer.scala 171:123] wire [7:0] _T_678 = ld_byte_hitvecfn_hi_2[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_680 = _T_678 & buf_data_0[23:16]; // @[lsu_bus_buffer.scala 171:65] + wire [7:0] _T_680 = _T_678 & buf_data_0[23:16]; // @[lsu_bus_buffer.scala 172:65] wire [7:0] _T_683 = ld_byte_hitvecfn_hi_2[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_685 = _T_683 & buf_data_1[23:16]; // @[lsu_bus_buffer.scala 171:65] + wire [7:0] _T_685 = _T_683 & buf_data_1[23:16]; // @[lsu_bus_buffer.scala 172:65] wire [7:0] _T_688 = ld_byte_hitvecfn_hi_2[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_690 = _T_688 & buf_data_2[23:16]; // @[lsu_bus_buffer.scala 171:65] + wire [7:0] _T_690 = _T_688 & buf_data_2[23:16]; // @[lsu_bus_buffer.scala 172:65] wire [7:0] _T_693 = ld_byte_hitvecfn_hi_2[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_695 = _T_693 & buf_data_3[23:16]; // @[lsu_bus_buffer.scala 171:65] - wire [7:0] _T_696 = _T_680 | _T_685; // @[lsu_bus_buffer.scala 171:97] - wire [7:0] _T_697 = _T_696 | _T_690; // @[lsu_bus_buffer.scala 171:97] - wire [7:0] _T_698 = _T_697 | _T_695; // @[lsu_bus_buffer.scala 171:97] + wire [7:0] _T_695 = _T_693 & buf_data_3[23:16]; // @[lsu_bus_buffer.scala 172:65] + wire [7:0] _T_696 = _T_680 | _T_685; // @[lsu_bus_buffer.scala 172:97] + wire [7:0] _T_697 = _T_696 | _T_690; // @[lsu_bus_buffer.scala 172:97] + wire [7:0] _T_698 = _T_697 | _T_695; // @[lsu_bus_buffer.scala 172:97] wire [7:0] _T_701 = ld_byte_hitvecfn_hi_1[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_703 = _T_701 & buf_data_0[15:8]; // @[lsu_bus_buffer.scala 172:65] + wire [7:0] _T_703 = _T_701 & buf_data_0[15:8]; // @[lsu_bus_buffer.scala 173:65] wire [7:0] _T_706 = ld_byte_hitvecfn_hi_1[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_708 = _T_706 & buf_data_1[15:8]; // @[lsu_bus_buffer.scala 172:65] + wire [7:0] _T_708 = _T_706 & buf_data_1[15:8]; // @[lsu_bus_buffer.scala 173:65] wire [7:0] _T_711 = ld_byte_hitvecfn_hi_1[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_713 = _T_711 & buf_data_2[15:8]; // @[lsu_bus_buffer.scala 172:65] + wire [7:0] _T_713 = _T_711 & buf_data_2[15:8]; // @[lsu_bus_buffer.scala 173:65] wire [7:0] _T_716 = ld_byte_hitvecfn_hi_1[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_718 = _T_716 & buf_data_3[15:8]; // @[lsu_bus_buffer.scala 172:65] - wire [7:0] _T_719 = _T_703 | _T_708; // @[lsu_bus_buffer.scala 172:97] - wire [7:0] _T_720 = _T_719 | _T_713; // @[lsu_bus_buffer.scala 172:97] - wire [7:0] _T_721 = _T_720 | _T_718; // @[lsu_bus_buffer.scala 172:97] + wire [7:0] _T_718 = _T_716 & buf_data_3[15:8]; // @[lsu_bus_buffer.scala 173:65] + wire [7:0] _T_719 = _T_703 | _T_708; // @[lsu_bus_buffer.scala 173:97] + wire [7:0] _T_720 = _T_719 | _T_713; // @[lsu_bus_buffer.scala 173:97] + wire [7:0] _T_721 = _T_720 | _T_718; // @[lsu_bus_buffer.scala 173:97] wire [7:0] _T_724 = ld_byte_hitvecfn_hi_0[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_726 = _T_724 & buf_data_0[7:0]; // @[lsu_bus_buffer.scala 173:65] + wire [7:0] _T_726 = _T_724 & buf_data_0[7:0]; // @[lsu_bus_buffer.scala 174:65] wire [7:0] _T_729 = ld_byte_hitvecfn_hi_0[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_731 = _T_729 & buf_data_1[7:0]; // @[lsu_bus_buffer.scala 173:65] + wire [7:0] _T_731 = _T_729 & buf_data_1[7:0]; // @[lsu_bus_buffer.scala 174:65] wire [7:0] _T_734 = ld_byte_hitvecfn_hi_0[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_736 = _T_734 & buf_data_2[7:0]; // @[lsu_bus_buffer.scala 173:65] + wire [7:0] _T_736 = _T_734 & buf_data_2[7:0]; // @[lsu_bus_buffer.scala 174:65] wire [7:0] _T_739 = ld_byte_hitvecfn_hi_0[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_741 = _T_739 & buf_data_3[7:0]; // @[lsu_bus_buffer.scala 173:65] - wire [7:0] _T_742 = _T_726 | _T_731; // @[lsu_bus_buffer.scala 173:97] - wire [7:0] _T_743 = _T_742 | _T_736; // @[lsu_bus_buffer.scala 173:97] - wire [7:0] _T_744 = _T_743 | _T_741; // @[lsu_bus_buffer.scala 173:97] + wire [7:0] _T_741 = _T_739 & buf_data_3[7:0]; // @[lsu_bus_buffer.scala 174:65] + wire [7:0] _T_742 = _T_726 | _T_731; // @[lsu_bus_buffer.scala 174:97] + wire [7:0] _T_743 = _T_742 | _T_736; // @[lsu_bus_buffer.scala 174:97] + wire [7:0] _T_744 = _T_743 | _T_741; // @[lsu_bus_buffer.scala 174:97] wire [31:0] _T_747 = {_T_675,_T_698,_T_721,_T_744}; // @[Cat.scala 29:58] - wire [31:0] _T_748 = ld_fwddata_buf_hi_initial & ibuf_data; // @[lsu_bus_buffer.scala 174:32] + wire [31:0] _T_748 = ld_fwddata_buf_hi_initial & ibuf_data; // @[lsu_bus_buffer.scala 175:32] wire [3:0] _T_750 = io_lsu_pkt_r_bits_by ? 4'h1 : 4'h0; // @[Mux.scala 27:72] wire [3:0] _T_751 = io_lsu_pkt_r_bits_half ? 4'h3 : 4'h0; // @[Mux.scala 27:72] wire [3:0] _T_752 = io_lsu_pkt_r_bits_word ? 4'hf : 4'h0; // @[Mux.scala 27:72] wire [3:0] _T_753 = _T_750 | _T_751; // @[Mux.scala 27:72] wire [3:0] ldst_byteen_r = _T_753 | _T_752; // @[Mux.scala 27:72] - wire _T_756 = io_lsu_addr_r[1:0] == 2'h0; // @[lsu_bus_buffer.scala 181:55] - wire _T_758 = io_lsu_addr_r[1:0] == 2'h1; // @[lsu_bus_buffer.scala 182:24] + wire _T_756 = io_lsu_addr_r[1:0] == 2'h0; // @[lsu_bus_buffer.scala 182:55] + wire _T_758 = io_lsu_addr_r[1:0] == 2'h1; // @[lsu_bus_buffer.scala 183:24] wire [3:0] _T_760 = {3'h0,ldst_byteen_r[3]}; // @[Cat.scala 29:58] - wire _T_762 = io_lsu_addr_r[1:0] == 2'h2; // @[lsu_bus_buffer.scala 183:24] + wire _T_762 = io_lsu_addr_r[1:0] == 2'h2; // @[lsu_bus_buffer.scala 184:24] wire [3:0] _T_764 = {2'h0,ldst_byteen_r[3:2]}; // @[Cat.scala 29:58] - wire _T_766 = io_lsu_addr_r[1:0] == 2'h3; // @[lsu_bus_buffer.scala 184:24] + wire _T_766 = io_lsu_addr_r[1:0] == 2'h3; // @[lsu_bus_buffer.scala 185:24] wire [3:0] _T_768 = {1'h0,ldst_byteen_r[3:1]}; // @[Cat.scala 29:58] wire [3:0] _T_770 = _T_758 ? _T_760 : 4'h0; // @[Mux.scala 27:72] wire [3:0] _T_771 = _T_762 ? _T_764 : 4'h0; // @[Mux.scala 27:72] @@ -69019,52 +69040,114 @@ module lsu_bus_buffer( wire [31:0] _T_836 = _T_832 | _T_833; // @[Mux.scala 27:72] wire [31:0] _T_837 = _T_836 | _T_834; // @[Mux.scala 27:72] wire [31:0] store_data_lo_r = _T_837 | _T_835; // @[Mux.scala 27:72] - wire ldst_samedw_r = io_lsu_addr_r[3] == io_end_addr_r[3]; // @[lsu_bus_buffer.scala 201:40] - wire _T_844 = ~io_lsu_addr_r[0]; // @[lsu_bus_buffer.scala 203:31] + wire ldst_samedw_r = io_lsu_addr_r[3] == io_end_addr_r[3]; // @[lsu_bus_buffer.scala 202:40] + wire _T_844 = ~io_lsu_addr_r[0]; // @[lsu_bus_buffer.scala 204:31] wire _T_845 = io_lsu_pkt_r_bits_word & _T_756; // @[Mux.scala 27:72] wire _T_846 = io_lsu_pkt_r_bits_half & _T_844; // @[Mux.scala 27:72] wire _T_848 = _T_845 | _T_846; // @[Mux.scala 27:72] wire is_aligned_r = _T_848 | io_lsu_pkt_r_bits_by; // @[Mux.scala 27:72] - wire _T_850 = io_lsu_pkt_r_bits_load | io_no_word_merge_r; // @[lsu_bus_buffer.scala 205:60] - wire _T_851 = io_lsu_busreq_r & _T_850; // @[lsu_bus_buffer.scala 205:34] - wire _T_852 = ~ibuf_valid; // @[lsu_bus_buffer.scala 205:84] - wire ibuf_byp = _T_851 & _T_852; // @[lsu_bus_buffer.scala 205:82] - wire _T_853 = io_lsu_busreq_r & io_lsu_commit_r; // @[lsu_bus_buffer.scala 206:36] - wire _T_854 = ~ibuf_byp; // @[lsu_bus_buffer.scala 206:56] - wire ibuf_wr_en = _T_853 & _T_854; // @[lsu_bus_buffer.scala 206:54] - wire _T_855 = ~ibuf_wr_en; // @[lsu_bus_buffer.scala 208:36] - wire _T_857 = ~io_lsu_busreq_r; // @[lsu_bus_buffer.scala 209:44] - wire _T_858 = io_lsu_busreq_m & _T_857; // @[lsu_bus_buffer.scala 209:42] - wire _T_859 = _T_858 & ibuf_valid; // @[lsu_bus_buffer.scala 209:61] - wire _T_862 = ibuf_addr[31:2] != io_lsu_addr_m[31:2]; // @[lsu_bus_buffer.scala 209:120] - wire _T_863 = io_lsu_pkt_m_bits_load | _T_862; // @[lsu_bus_buffer.scala 209:100] - wire ibuf_force_drain = _T_859 & _T_863; // @[lsu_bus_buffer.scala 209:74] + wire _T_850 = io_lsu_pkt_r_bits_load | io_no_word_merge_r; // @[lsu_bus_buffer.scala 206:60] + wire _T_851 = io_lsu_busreq_r & _T_850; // @[lsu_bus_buffer.scala 206:34] + wire _T_852 = ~ibuf_valid; // @[lsu_bus_buffer.scala 206:84] + wire ibuf_byp = _T_851 & _T_852; // @[lsu_bus_buffer.scala 206:82] + wire _T_853 = io_lsu_busreq_r & io_lsu_commit_r; // @[lsu_bus_buffer.scala 207:36] + wire _T_854 = ~ibuf_byp; // @[lsu_bus_buffer.scala 207:56] + wire ibuf_wr_en = _T_853 & _T_854; // @[lsu_bus_buffer.scala 207:54] + wire _T_855 = ~ibuf_wr_en; // @[lsu_bus_buffer.scala 209:36] + reg [2:0] ibuf_timer; // @[lsu_bus_buffer.scala 252:55] + wire _T_864 = ibuf_timer == 3'h7; // @[lsu_bus_buffer.scala 215:62] + wire _T_865 = ibuf_wr_en | _T_864; // @[lsu_bus_buffer.scala 215:48] + wire _T_929 = _T_853 & io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 234:54] + wire _T_930 = _T_929 & ibuf_valid; // @[lsu_bus_buffer.scala 234:80] + wire _T_931 = _T_930 & ibuf_write; // @[lsu_bus_buffer.scala 234:93] + wire _T_934 = io_lsu_addr_r[31:2] == ibuf_addr[31:2]; // @[lsu_bus_buffer.scala 234:129] + wire _T_935 = _T_931 & _T_934; // @[lsu_bus_buffer.scala 234:106] + wire _T_936 = ~io_is_sideeffects_r; // @[lsu_bus_buffer.scala 234:152] + wire _T_937 = _T_935 & _T_936; // @[lsu_bus_buffer.scala 234:150] + wire _T_938 = ~io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_buffer.scala 234:175] + wire ibuf_merge_en = _T_937 & _T_938; // @[lsu_bus_buffer.scala 234:173] + wire ibuf_merge_in = ~io_ldst_dual_r; // @[lsu_bus_buffer.scala 235:20] + wire _T_866 = ibuf_merge_en & ibuf_merge_in; // @[lsu_bus_buffer.scala 215:98] + wire _T_867 = ~_T_866; // @[lsu_bus_buffer.scala 215:82] + wire _T_868 = _T_865 & _T_867; // @[lsu_bus_buffer.scala 215:80] + wire _T_869 = _T_868 | ibuf_byp; // @[lsu_bus_buffer.scala 216:5] + wire _T_857 = ~io_lsu_busreq_r; // @[lsu_bus_buffer.scala 210:44] + wire _T_858 = io_lsu_busreq_m & _T_857; // @[lsu_bus_buffer.scala 210:42] + wire _T_859 = _T_858 & ibuf_valid; // @[lsu_bus_buffer.scala 210:61] + wire _T_862 = ibuf_addr[31:2] != io_lsu_addr_m[31:2]; // @[lsu_bus_buffer.scala 210:120] + wire _T_863 = io_lsu_pkt_m_bits_load | _T_862; // @[lsu_bus_buffer.scala 210:100] + wire ibuf_force_drain = _T_859 & _T_863; // @[lsu_bus_buffer.scala 210:74] + wire _T_870 = _T_869 | ibuf_force_drain; // @[lsu_bus_buffer.scala 216:16] reg ibuf_sideeffect; // @[Reg.scala 27:20] - wire _T_856 = ibuf_valid & _T_855; // @[lsu_bus_buffer.scala 208:34] - wire ibuf_rst = _T_856 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 208:49] + wire _T_871 = _T_870 | ibuf_sideeffect; // @[lsu_bus_buffer.scala 216:35] + wire _T_872 = ~ibuf_write; // @[lsu_bus_buffer.scala 216:55] + wire _T_873 = _T_871 | _T_872; // @[lsu_bus_buffer.scala 216:53] + wire _T_874 = _T_873 | io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_buffer.scala 216:67] + wire ibuf_drain_vld = ibuf_valid & _T_874; // @[lsu_bus_buffer.scala 215:32] + wire _T_856 = ibuf_drain_vld & _T_855; // @[lsu_bus_buffer.scala 209:34] + wire ibuf_rst = _T_856 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 209:49] reg [1:0] WrPtr1_r; // @[lsu_bus_buffer.scala 615:49] reg [1:0] WrPtr0_r; // @[lsu_bus_buffer.scala 614:49] reg [1:0] ibuf_tag; // @[Reg.scala 27:20] wire [1:0] ibuf_sz_in = {io_lsu_pkt_r_bits_word,io_lsu_pkt_r_bits_half}; // @[Cat.scala 29:58] - wire [7:0] _T_892 = io_ldst_dual_r ? store_data_hi_r[7:0] : store_data_lo_r[7:0]; // @[lsu_bus_buffer.scala 230:8] - wire [7:0] _T_901 = io_ldst_dual_r ? store_data_hi_r[15:8] : store_data_lo_r[15:8]; // @[lsu_bus_buffer.scala 230:8] - wire [7:0] _T_910 = io_ldst_dual_r ? store_data_hi_r[23:16] : store_data_lo_r[23:16]; // @[lsu_bus_buffer.scala 230:8] - wire [7:0] _T_919 = io_ldst_dual_r ? store_data_hi_r[31:24] : store_data_lo_r[31:24]; // @[lsu_bus_buffer.scala 230:8] - wire [23:0] _T_922 = {_T_919,_T_910,_T_901}; // @[Cat.scala 29:58] - wire [3:0] ibuf_byteen_out = {ibuf_byteen[3],ibuf_byteen[2],ibuf_byteen[1],ibuf_byteen[0]}; // @[Cat.scala 29:58] - wire [31:0] ibuf_data_out = {ibuf_data[31:24],ibuf_data[23:16],ibuf_data[15:8],ibuf_data[7:0]}; // @[Cat.scala 29:58] - wire _T_1005 = ibuf_wr_en | ibuf_valid; // @[lsu_bus_buffer.scala 238:58] - wire _T_1006 = ~ibuf_rst; // @[lsu_bus_buffer.scala 238:93] + wire [3:0] _T_881 = ibuf_byteen | ldst_byteen_lo_r; // @[lsu_bus_buffer.scala 225:77] + wire [7:0] _T_889 = ldst_byteen_lo_r[0] ? store_data_lo_r[7:0] : ibuf_data[7:0]; // @[lsu_bus_buffer.scala 230:8] + wire [7:0] _T_892 = io_ldst_dual_r ? store_data_hi_r[7:0] : store_data_lo_r[7:0]; // @[lsu_bus_buffer.scala 231:8] + wire [7:0] _T_893 = _T_866 ? _T_889 : _T_892; // @[lsu_bus_buffer.scala 229:46] + wire [7:0] _T_898 = ldst_byteen_lo_r[1] ? store_data_lo_r[15:8] : ibuf_data[15:8]; // @[lsu_bus_buffer.scala 230:8] + wire [7:0] _T_901 = io_ldst_dual_r ? store_data_hi_r[15:8] : store_data_lo_r[15:8]; // @[lsu_bus_buffer.scala 231:8] + wire [7:0] _T_902 = _T_866 ? _T_898 : _T_901; // @[lsu_bus_buffer.scala 229:46] + wire [7:0] _T_907 = ldst_byteen_lo_r[2] ? store_data_lo_r[23:16] : ibuf_data[23:16]; // @[lsu_bus_buffer.scala 230:8] + wire [7:0] _T_910 = io_ldst_dual_r ? store_data_hi_r[23:16] : store_data_lo_r[23:16]; // @[lsu_bus_buffer.scala 231:8] + wire [7:0] _T_911 = _T_866 ? _T_907 : _T_910; // @[lsu_bus_buffer.scala 229:46] + wire [7:0] _T_916 = ldst_byteen_lo_r[3] ? store_data_lo_r[31:24] : ibuf_data[31:24]; // @[lsu_bus_buffer.scala 230:8] + wire [7:0] _T_919 = io_ldst_dual_r ? store_data_hi_r[31:24] : store_data_lo_r[31:24]; // @[lsu_bus_buffer.scala 231:8] + wire [7:0] _T_920 = _T_866 ? _T_916 : _T_919; // @[lsu_bus_buffer.scala 229:46] + wire [23:0] _T_922 = {_T_920,_T_911,_T_902}; // @[Cat.scala 29:58] + wire _T_923 = ibuf_timer < 3'h7; // @[lsu_bus_buffer.scala 232:59] + wire [2:0] _T_926 = ibuf_timer + 3'h1; // @[lsu_bus_buffer.scala 232:93] + wire _T_941 = ~ibuf_merge_in; // @[lsu_bus_buffer.scala 236:65] + wire _T_942 = ibuf_merge_en & _T_941; // @[lsu_bus_buffer.scala 236:63] + wire _T_945 = ibuf_byteen[0] | ldst_byteen_lo_r[0]; // @[lsu_bus_buffer.scala 236:96] + wire _T_947 = _T_942 ? _T_945 : ibuf_byteen[0]; // @[lsu_bus_buffer.scala 236:48] + wire _T_952 = ibuf_byteen[1] | ldst_byteen_lo_r[1]; // @[lsu_bus_buffer.scala 236:96] + wire _T_954 = _T_942 ? _T_952 : ibuf_byteen[1]; // @[lsu_bus_buffer.scala 236:48] + wire _T_959 = ibuf_byteen[2] | ldst_byteen_lo_r[2]; // @[lsu_bus_buffer.scala 236:96] + wire _T_961 = _T_942 ? _T_959 : ibuf_byteen[2]; // @[lsu_bus_buffer.scala 236:48] + wire _T_966 = ibuf_byteen[3] | ldst_byteen_lo_r[3]; // @[lsu_bus_buffer.scala 236:96] + wire _T_968 = _T_942 ? _T_966 : ibuf_byteen[3]; // @[lsu_bus_buffer.scala 236:48] + wire [3:0] ibuf_byteen_out = {_T_968,_T_961,_T_954,_T_947}; // @[Cat.scala 29:58] + wire [7:0] _T_978 = _T_942 ? _T_889 : ibuf_data[7:0]; // @[lsu_bus_buffer.scala 237:45] + wire [7:0] _T_986 = _T_942 ? _T_898 : ibuf_data[15:8]; // @[lsu_bus_buffer.scala 237:45] + wire [7:0] _T_994 = _T_942 ? _T_907 : ibuf_data[23:16]; // @[lsu_bus_buffer.scala 237:45] + wire [7:0] _T_1002 = _T_942 ? _T_916 : ibuf_data[31:24]; // @[lsu_bus_buffer.scala 237:45] + wire [31:0] ibuf_data_out = {_T_1002,_T_994,_T_986,_T_978}; // @[Cat.scala 29:58] + wire _T_1005 = ibuf_wr_en | ibuf_valid; // @[lsu_bus_buffer.scala 239:58] + wire _T_1006 = ~ibuf_rst; // @[lsu_bus_buffer.scala 239:93] reg [1:0] ibuf_dualtag; // @[Reg.scala 27:20] reg ibuf_dual; // @[Reg.scala 27:20] reg ibuf_samedw; // @[Reg.scala 27:20] reg ibuf_nomerge; // @[Reg.scala 27:20] reg ibuf_unsign; // @[Reg.scala 27:20] reg [1:0] ibuf_sz; // @[Reg.scala 27:20] + wire _T_4446 = buf_write[3] & _T_2621; // @[lsu_bus_buffer.scala 521:64] wire _T_4447 = ~buf_cmd_state_bus_en_3; // @[lsu_bus_buffer.scala 521:91] + wire _T_4448 = _T_4446 & _T_4447; // @[lsu_bus_buffer.scala 521:89] + wire _T_4441 = buf_write[2] & _T_2616; // @[lsu_bus_buffer.scala 521:64] wire _T_4442 = ~buf_cmd_state_bus_en_2; // @[lsu_bus_buffer.scala 521:91] + wire _T_4443 = _T_4441 & _T_4442; // @[lsu_bus_buffer.scala 521:89] + wire [1:0] _T_4449 = _T_4448 + _T_4443; // @[lsu_bus_buffer.scala 521:142] + wire _T_4436 = buf_write[1] & _T_2611; // @[lsu_bus_buffer.scala 521:64] wire _T_4437 = ~buf_cmd_state_bus_en_1; // @[lsu_bus_buffer.scala 521:91] + wire _T_4438 = _T_4436 & _T_4437; // @[lsu_bus_buffer.scala 521:89] + wire [1:0] _GEN_362 = {{1'd0}, _T_4438}; // @[lsu_bus_buffer.scala 521:142] + wire [2:0] _T_4450 = _T_4449 + _GEN_362; // @[lsu_bus_buffer.scala 521:142] + wire _T_4431 = buf_write[0] & _T_2606; // @[lsu_bus_buffer.scala 521:64] wire _T_4432 = ~buf_cmd_state_bus_en_0; // @[lsu_bus_buffer.scala 521:91] + wire _T_4433 = _T_4431 & _T_4432; // @[lsu_bus_buffer.scala 521:89] + wire [2:0] _GEN_363 = {{2'd0}, _T_4433}; // @[lsu_bus_buffer.scala 521:142] + wire [3:0] buf_numvld_wrcmd_any = _T_4450 + _GEN_363; // @[lsu_bus_buffer.scala 521:142] + wire _T_1016 = buf_numvld_wrcmd_any == 4'h1; // @[lsu_bus_buffer.scala 262:43] wire _T_4463 = _T_2621 & _T_4447; // @[lsu_bus_buffer.scala 522:73] wire _T_4460 = _T_2616 & _T_4442; // @[lsu_bus_buffer.scala 522:73] wire [1:0] _T_4464 = _T_4463 + _T_4460; // @[lsu_bus_buffer.scala 522:126] @@ -69074,7 +69157,12 @@ module lsu_bus_buffer( wire _T_4454 = _T_2606 & _T_4432; // @[lsu_bus_buffer.scala 522:73] wire [2:0] _GEN_365 = {{2'd0}, _T_4454}; // @[lsu_bus_buffer.scala 522:126] wire [3:0] buf_numvld_cmd_any = _T_4465 + _GEN_365; // @[lsu_bus_buffer.scala 522:126] - wire _T_1017 = buf_numvld_cmd_any == 4'h1; // @[lsu_bus_buffer.scala 261:72] + wire _T_1017 = buf_numvld_cmd_any == 4'h1; // @[lsu_bus_buffer.scala 262:72] + wire _T_1018 = _T_1016 & _T_1017; // @[lsu_bus_buffer.scala 262:51] + reg [2:0] obuf_wr_timer; // @[lsu_bus_buffer.scala 360:54] + wire _T_1019 = obuf_wr_timer != 3'h7; // @[lsu_bus_buffer.scala 262:97] + wire _T_1020 = _T_1018 & _T_1019; // @[lsu_bus_buffer.scala 262:80] + wire _T_1022 = _T_1020 & _T_938; // @[lsu_bus_buffer.scala 262:114] wire _T_1979 = |buf_age_3; // @[lsu_bus_buffer.scala 377:58] wire _T_1980 = ~_T_1979; // @[lsu_bus_buffer.scala 377:45] wire _T_1982 = _T_1980 & _T_2621; // @[lsu_bus_buffer.scala 377:63] @@ -69104,14 +69192,23 @@ module lsu_bus_buffer( wire _T_2075 = _T_2073 | _T_2054[7]; // @[lsu_bus_buffer.scala 385:104] wire [2:0] _T_2077 = {_T_2061,_T_2068,_T_2075}; // @[Cat.scala 29:58] wire [1:0] CmdPtr0 = _T_2077[1:0]; // @[lsu_bus_buffer.scala 390:11] - wire _T_1023 = CmdPtr0 == 2'h0; // @[lsu_bus_buffer.scala 262:114] - wire _T_1024 = CmdPtr0 == 2'h1; // @[lsu_bus_buffer.scala 262:114] - wire _T_1025 = CmdPtr0 == 2'h2; // @[lsu_bus_buffer.scala 262:114] - wire _T_1026 = CmdPtr0 == 2'h3; // @[lsu_bus_buffer.scala 262:114] + wire _T_1023 = CmdPtr0 == 2'h0; // @[lsu_bus_buffer.scala 263:114] + wire _T_1024 = CmdPtr0 == 2'h1; // @[lsu_bus_buffer.scala 263:114] + wire _T_1025 = CmdPtr0 == 2'h2; // @[lsu_bus_buffer.scala 263:114] + wire _T_1026 = CmdPtr0 == 2'h3; // @[lsu_bus_buffer.scala 263:114] reg buf_nomerge_0; // @[Reg.scala 27:20] + wire _T_1027 = _T_1023 & buf_nomerge_0; // @[Mux.scala 27:72] reg buf_nomerge_1; // @[Reg.scala 27:20] + wire _T_1028 = _T_1024 & buf_nomerge_1; // @[Mux.scala 27:72] reg buf_nomerge_2; // @[Reg.scala 27:20] + wire _T_1029 = _T_1025 & buf_nomerge_2; // @[Mux.scala 27:72] reg buf_nomerge_3; // @[Reg.scala 27:20] + wire _T_1030 = _T_1026 & buf_nomerge_3; // @[Mux.scala 27:72] + wire _T_1031 = _T_1027 | _T_1028; // @[Mux.scala 27:72] + wire _T_1032 = _T_1031 | _T_1029; // @[Mux.scala 27:72] + wire _T_1033 = _T_1032 | _T_1030; // @[Mux.scala 27:72] + wire _T_1035 = ~_T_1033; // @[lsu_bus_buffer.scala 263:31] + wire _T_1036 = _T_1022 & _T_1035; // @[lsu_bus_buffer.scala 263:29] reg _T_4330; // @[Reg.scala 27:20] reg _T_4327; // @[Reg.scala 27:20] reg _T_4324; // @[Reg.scala 27:20] @@ -69124,9 +69221,10 @@ module lsu_bus_buffer( wire _T_1049 = _T_1045 | _T_1046; // @[Mux.scala 27:72] wire _T_1050 = _T_1049 | _T_1047; // @[Mux.scala 27:72] wire _T_1051 = _T_1050 | _T_1048; // @[Mux.scala 27:72] - wire _T_1053 = ~_T_1051; // @[lsu_bus_buffer.scala 263:5] - wire _T_1065 = _T_858 & _T_852; // @[lsu_bus_buffer.scala 265:58] - wire _T_1067 = _T_1065 & _T_1017; // @[lsu_bus_buffer.scala 265:72] + wire _T_1053 = ~_T_1051; // @[lsu_bus_buffer.scala 264:5] + wire _T_1054 = _T_1036 & _T_1053; // @[lsu_bus_buffer.scala 263:140] + wire _T_1065 = _T_858 & _T_852; // @[lsu_bus_buffer.scala 266:58] + wire _T_1067 = _T_1065 & _T_1017; // @[lsu_bus_buffer.scala 266:72] wire [29:0] _T_1077 = _T_1023 ? buf_addr_0[31:2] : 30'h0; // @[Mux.scala 27:72] wire [29:0] _T_1078 = _T_1024 ? buf_addr_1[31:2] : 30'h0; // @[Mux.scala 27:72] wire [29:0] _T_1081 = _T_1077 | _T_1078; // @[Mux.scala 27:72] @@ -69134,8 +69232,14 @@ module lsu_bus_buffer( wire [29:0] _T_1082 = _T_1081 | _T_1079; // @[Mux.scala 27:72] wire [29:0] _T_1080 = _T_1026 ? buf_addr_3[31:2] : 30'h0; // @[Mux.scala 27:72] wire [29:0] _T_1083 = _T_1082 | _T_1080; // @[Mux.scala 27:72] - wire _T_1085 = io_lsu_addr_m[31:2] != _T_1083; // @[lsu_bus_buffer.scala 265:123] - wire obuf_force_wr_en = _T_1067 & _T_1085; // @[lsu_bus_buffer.scala 265:101] + wire _T_1085 = io_lsu_addr_m[31:2] != _T_1083; // @[lsu_bus_buffer.scala 266:123] + wire obuf_force_wr_en = _T_1067 & _T_1085; // @[lsu_bus_buffer.scala 266:101] + wire _T_1055 = ~obuf_force_wr_en; // @[lsu_bus_buffer.scala 264:119] + wire obuf_wr_wait = _T_1054 & _T_1055; // @[lsu_bus_buffer.scala 264:117] + wire _T_1056 = |buf_numvld_cmd_any; // @[lsu_bus_buffer.scala 265:75] + wire _T_1057 = obuf_wr_timer < 3'h7; // @[lsu_bus_buffer.scala 265:95] + wire _T_1058 = _T_1056 & _T_1057; // @[lsu_bus_buffer.scala 265:79] + wire [2:0] _T_1060 = obuf_wr_timer + 3'h1; // @[lsu_bus_buffer.scala 265:123] wire _T_4482 = buf_state_3 == 3'h1; // @[lsu_bus_buffer.scala 523:63] wire _T_4486 = _T_4482 | _T_4463; // @[lsu_bus_buffer.scala 523:74] wire _T_4477 = buf_state_2 == 3'h1; // @[lsu_bus_buffer.scala 523:63] @@ -69149,12 +69253,12 @@ module lsu_bus_buffer( wire _T_4471 = _T_4467 | _T_4454; // @[lsu_bus_buffer.scala 523:74] wire [2:0] _GEN_367 = {{2'd0}, _T_4471}; // @[lsu_bus_buffer.scala 523:154] wire [3:0] buf_numvld_pend_any = _T_4488 + _GEN_367; // @[lsu_bus_buffer.scala 523:154] - wire _T_1087 = buf_numvld_pend_any == 4'h0; // @[lsu_bus_buffer.scala 267:53] - wire _T_1088 = ibuf_byp & _T_1087; // @[lsu_bus_buffer.scala 267:31] - wire _T_1089 = ~io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 267:64] - wire _T_1090 = _T_1089 | io_no_dword_merge_r; // @[lsu_bus_buffer.scala 267:89] - wire ibuf_buf_byp = _T_1088 & _T_1090; // @[lsu_bus_buffer.scala 267:61] - wire _T_1091 = ibuf_buf_byp & io_lsu_commit_r; // @[lsu_bus_buffer.scala 282:32] + wire _T_1087 = buf_numvld_pend_any == 4'h0; // @[lsu_bus_buffer.scala 268:53] + wire _T_1088 = ibuf_byp & _T_1087; // @[lsu_bus_buffer.scala 268:31] + wire _T_1089 = ~io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 268:64] + wire _T_1090 = _T_1089 | io_no_dword_merge_r; // @[lsu_bus_buffer.scala 268:89] + wire ibuf_buf_byp = _T_1088 & _T_1090; // @[lsu_bus_buffer.scala 268:61] + wire _T_1091 = ibuf_buf_byp & io_lsu_commit_r; // @[lsu_bus_buffer.scala 283:32] wire _T_4778 = buf_state_0 == 3'h3; // @[lsu_bus_buffer.scala 551:62] wire _T_4780 = _T_4778 & buf_sideeffect[0]; // @[lsu_bus_buffer.scala 551:73] wire _T_4781 = _T_4780 & io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_buffer.scala 551:93] @@ -69174,9 +69278,9 @@ module lsu_bus_buffer( wire _T_4797 = obuf_valid & obuf_sideeffect; // @[lsu_bus_buffer.scala 551:171] wire _T_4798 = _T_4797 & io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_buffer.scala 551:189] wire bus_sideeffect_pend = _T_4796 | _T_4798; // @[lsu_bus_buffer.scala 551:157] - wire _T_1092 = io_is_sideeffects_r & bus_sideeffect_pend; // @[lsu_bus_buffer.scala 282:74] - wire _T_1093 = ~_T_1092; // @[lsu_bus_buffer.scala 282:52] - wire _T_1094 = _T_1091 & _T_1093; // @[lsu_bus_buffer.scala 282:50] + wire _T_1092 = io_is_sideeffects_r & bus_sideeffect_pend; // @[lsu_bus_buffer.scala 283:74] + wire _T_1093 = ~_T_1092; // @[lsu_bus_buffer.scala 283:52] + wire _T_1094 = _T_1091 & _T_1093; // @[lsu_bus_buffer.scala 283:50] wire [2:0] _T_1099 = _T_1023 ? buf_state_0 : 3'h0; // @[Mux.scala 27:72] wire [2:0] _T_1100 = _T_1024 ? buf_state_1 : 3'h0; // @[Mux.scala 27:72] wire [2:0] _T_1103 = _T_1099 | _T_1100; // @[Mux.scala 27:72] @@ -69184,9 +69288,9 @@ module lsu_bus_buffer( wire [2:0] _T_1104 = _T_1103 | _T_1101; // @[Mux.scala 27:72] wire [2:0] _T_1102 = _T_1026 ? buf_state_3 : 3'h0; // @[Mux.scala 27:72] wire [2:0] _T_1105 = _T_1104 | _T_1102; // @[Mux.scala 27:72] - wire _T_1107 = _T_1105 == 3'h2; // @[lsu_bus_buffer.scala 283:36] + wire _T_1107 = _T_1105 == 3'h2; // @[lsu_bus_buffer.scala 284:36] wire found_cmdptr0 = |CmdPtr0Dec; // @[lsu_bus_buffer.scala 382:31] - wire _T_1108 = _T_1107 & found_cmdptr0; // @[lsu_bus_buffer.scala 283:47] + wire _T_1108 = _T_1107 & found_cmdptr0; // @[lsu_bus_buffer.scala 284:47] wire [3:0] _T_1111 = {buf_cmd_state_bus_en_3,buf_cmd_state_bus_en_2,buf_cmd_state_bus_en_1,buf_cmd_state_bus_en_0}; // @[Cat.scala 29:58] wire _T_1120 = _T_1023 & _T_1111[0]; // @[Mux.scala 27:72] wire _T_1121 = _T_1024 & _T_1111[1]; // @[Mux.scala 27:72] @@ -69195,11 +69299,11 @@ module lsu_bus_buffer( wire _T_1125 = _T_1124 | _T_1122; // @[Mux.scala 27:72] wire _T_1123 = _T_1026 & _T_1111[3]; // @[Mux.scala 27:72] wire _T_1126 = _T_1125 | _T_1123; // @[Mux.scala 27:72] - wire _T_1128 = ~_T_1126; // @[lsu_bus_buffer.scala 284:23] - wire _T_1129 = _T_1108 & _T_1128; // @[lsu_bus_buffer.scala 284:21] - wire _T_1146 = _T_1051 & bus_sideeffect_pend; // @[lsu_bus_buffer.scala 284:141] - wire _T_1147 = ~_T_1146; // @[lsu_bus_buffer.scala 284:105] - wire _T_1148 = _T_1129 & _T_1147; // @[lsu_bus_buffer.scala 284:103] + wire _T_1128 = ~_T_1126; // @[lsu_bus_buffer.scala 285:23] + wire _T_1129 = _T_1108 & _T_1128; // @[lsu_bus_buffer.scala 285:21] + wire _T_1146 = _T_1051 & bus_sideeffect_pend; // @[lsu_bus_buffer.scala 285:141] + wire _T_1147 = ~_T_1146; // @[lsu_bus_buffer.scala 285:105] + wire _T_1148 = _T_1129 & _T_1147; // @[lsu_bus_buffer.scala 285:103] reg buf_dual_3; // @[Reg.scala 27:20] reg buf_dual_2; // @[Reg.scala 27:20] reg buf_dual_1; // @[Reg.scala 27:20] @@ -69224,7 +69328,7 @@ module lsu_bus_buffer( wire _T_1184 = _T_1183 | _T_1181; // @[Mux.scala 27:72] wire _T_1182 = _T_1026 & _T_1170[3]; // @[Mux.scala 27:72] wire _T_1185 = _T_1184 | _T_1182; // @[Mux.scala 27:72] - wire _T_1187 = _T_1166 & _T_1185; // @[lsu_bus_buffer.scala 285:77] + wire _T_1187 = _T_1166 & _T_1185; // @[lsu_bus_buffer.scala 286:77] wire _T_1196 = _T_1023 & buf_write[0]; // @[Mux.scala 27:72] wire _T_1197 = _T_1024 & buf_write[1]; // @[Mux.scala 27:72] wire _T_1200 = _T_1196 | _T_1197; // @[Mux.scala 27:72] @@ -69232,9 +69336,9 @@ module lsu_bus_buffer( wire _T_1201 = _T_1200 | _T_1198; // @[Mux.scala 27:72] wire _T_1199 = _T_1026 & buf_write[3]; // @[Mux.scala 27:72] wire _T_1202 = _T_1201 | _T_1199; // @[Mux.scala 27:72] - wire _T_1204 = ~_T_1202; // @[lsu_bus_buffer.scala 285:150] - wire _T_1205 = _T_1187 & _T_1204; // @[lsu_bus_buffer.scala 285:148] - wire _T_1206 = ~_T_1205; // @[lsu_bus_buffer.scala 285:8] + wire _T_1204 = ~_T_1202; // @[lsu_bus_buffer.scala 286:150] + wire _T_1205 = _T_1187 & _T_1204; // @[lsu_bus_buffer.scala 286:148] + wire _T_1206 = ~_T_1205; // @[lsu_bus_buffer.scala 286:8] wire [3:0] _T_2020 = ~CmdPtr0Dec; // @[lsu_bus_buffer.scala 378:62] wire [3:0] _T_2021 = buf_age_3 & _T_2020; // @[lsu_bus_buffer.scala 378:59] wire _T_2022 = |_T_2021; // @[lsu_bus_buffer.scala 378:76] @@ -69266,7 +69370,7 @@ module lsu_bus_buffer( wire _T_1997 = _T_1995 & _T_4432; // @[lsu_bus_buffer.scala 378:123] wire [3:0] CmdPtr1Dec = {_T_2030,_T_2019,_T_2008,_T_1997}; // @[Cat.scala 29:58] wire found_cmdptr1 = |CmdPtr1Dec; // @[lsu_bus_buffer.scala 383:31] - wire _T_1207 = _T_1206 | found_cmdptr1; // @[lsu_bus_buffer.scala 285:181] + wire _T_1207 = _T_1206 | found_cmdptr1; // @[lsu_bus_buffer.scala 286:181] wire [3:0] _T_1210 = {buf_nomerge_3,buf_nomerge_2,buf_nomerge_1,buf_nomerge_0}; // @[Cat.scala 29:58] wire _T_1219 = _T_1023 & _T_1210[0]; // @[Mux.scala 27:72] wire _T_1220 = _T_1024 & _T_1210[1]; // @[Mux.scala 27:72] @@ -69275,10 +69379,10 @@ module lsu_bus_buffer( wire _T_1224 = _T_1223 | _T_1221; // @[Mux.scala 27:72] wire _T_1222 = _T_1026 & _T_1210[3]; // @[Mux.scala 27:72] wire _T_1225 = _T_1224 | _T_1222; // @[Mux.scala 27:72] - wire _T_1227 = _T_1207 | _T_1225; // @[lsu_bus_buffer.scala 285:197] - wire _T_1228 = _T_1227 | obuf_force_wr_en; // @[lsu_bus_buffer.scala 285:269] - wire _T_1229 = _T_1148 & _T_1228; // @[lsu_bus_buffer.scala 284:164] - wire _T_1230 = _T_1094 | _T_1229; // @[lsu_bus_buffer.scala 282:98] + wire _T_1227 = _T_1207 | _T_1225; // @[lsu_bus_buffer.scala 286:197] + wire _T_1228 = _T_1227 | obuf_force_wr_en; // @[lsu_bus_buffer.scala 286:269] + wire _T_1229 = _T_1148 & _T_1228; // @[lsu_bus_buffer.scala 285:164] + wire _T_1230 = _T_1094 | _T_1229; // @[lsu_bus_buffer.scala 283:98] reg obuf_write; // @[Reg.scala 27:20] reg obuf_cmd_done; // @[lsu_bus_buffer.scala 347:54] reg obuf_data_done; // @[lsu_bus_buffer.scala 348:55] @@ -69287,14 +69391,16 @@ module lsu_bus_buffer( wire _T_4858 = io_lsu_axi_aw_ready & io_lsu_axi_w_ready; // @[lsu_bus_buffer.scala 555:153] wire _T_4859 = _T_4856 ? _T_4857 : _T_4858; // @[lsu_bus_buffer.scala 555:39] wire bus_cmd_ready = obuf_write ? _T_4859 : io_lsu_axi_ar_ready; // @[lsu_bus_buffer.scala 555:23] - wire _T_1231 = ~obuf_valid; // @[lsu_bus_buffer.scala 286:48] - wire _T_1232 = bus_cmd_ready | _T_1231; // @[lsu_bus_buffer.scala 286:46] + wire _T_1231 = ~obuf_valid; // @[lsu_bus_buffer.scala 287:48] + wire _T_1232 = bus_cmd_ready | _T_1231; // @[lsu_bus_buffer.scala 287:46] reg obuf_nosend; // @[Reg.scala 27:20] - wire _T_1233 = _T_1232 | obuf_nosend; // @[lsu_bus_buffer.scala 286:60] - wire _T_1234 = _T_1230 & _T_1233; // @[lsu_bus_buffer.scala 286:29] + wire _T_1233 = _T_1232 | obuf_nosend; // @[lsu_bus_buffer.scala 287:60] + wire _T_1234 = _T_1230 & _T_1233; // @[lsu_bus_buffer.scala 287:29] + wire _T_1235 = ~obuf_wr_wait; // @[lsu_bus_buffer.scala 287:77] + wire _T_1236 = _T_1234 & _T_1235; // @[lsu_bus_buffer.scala 287:75] reg [31:0] obuf_addr; // @[lib.scala 374:16] - wire obuf_wr_en = _T_1234 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 286:142] - wire _T_1242 = obuf_valid & obuf_nosend; // @[lsu_bus_buffer.scala 288:47] + wire obuf_wr_en = _T_1236 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 287:142] + wire _T_1242 = obuf_valid & obuf_nosend; // @[lsu_bus_buffer.scala 289:47] wire bus_wcmd_sent = io_lsu_axi_aw_valid & io_lsu_axi_aw_ready; // @[lsu_bus_buffer.scala 556:40] wire _T_4863 = obuf_cmd_done | bus_wcmd_sent; // @[lsu_bus_buffer.scala 558:35] wire bus_wdata_sent = io_lsu_axi_w_valid & io_lsu_axi_w_ready; // @[lsu_bus_buffer.scala 557:40] @@ -69302,12 +69408,12 @@ module lsu_bus_buffer( wire _T_4865 = _T_4863 & _T_4864; // @[lsu_bus_buffer.scala 558:52] wire _T_4866 = io_lsu_axi_ar_valid & io_lsu_axi_ar_ready; // @[lsu_bus_buffer.scala 558:112] wire bus_cmd_sent = _T_4865 | _T_4866; // @[lsu_bus_buffer.scala 558:89] - wire _T_1243 = bus_cmd_sent | _T_1242; // @[lsu_bus_buffer.scala 288:33] - wire _T_1244 = ~obuf_wr_en; // @[lsu_bus_buffer.scala 288:65] - wire _T_1245 = _T_1243 & _T_1244; // @[lsu_bus_buffer.scala 288:63] - wire _T_1246 = _T_1245 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 288:77] - wire obuf_rst = _T_1246 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 288:98] - wire obuf_write_in = ibuf_buf_byp ? io_lsu_pkt_r_bits_store : _T_1202; // @[lsu_bus_buffer.scala 289:26] + wire _T_1243 = bus_cmd_sent | _T_1242; // @[lsu_bus_buffer.scala 289:33] + wire _T_1244 = ~obuf_wr_en; // @[lsu_bus_buffer.scala 289:65] + wire _T_1245 = _T_1243 & _T_1244; // @[lsu_bus_buffer.scala 289:63] + wire _T_1246 = _T_1245 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 289:77] + wire obuf_rst = _T_1246 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 289:98] + wire obuf_write_in = ibuf_buf_byp ? io_lsu_pkt_r_bits_store : _T_1202; // @[lsu_bus_buffer.scala 290:26] wire [31:0] _T_1283 = _T_1023 ? buf_addr_0 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1284 = _T_1024 ? buf_addr_1 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1285 = _T_1025 ? buf_addr_2 : 32'h0; // @[Mux.scala 27:72] @@ -69315,7 +69421,7 @@ module lsu_bus_buffer( wire [31:0] _T_1287 = _T_1283 | _T_1284; // @[Mux.scala 27:72] wire [31:0] _T_1288 = _T_1287 | _T_1285; // @[Mux.scala 27:72] wire [31:0] _T_1289 = _T_1288 | _T_1286; // @[Mux.scala 27:72] - wire [31:0] obuf_addr_in = ibuf_buf_byp ? io_lsu_addr_r : _T_1289; // @[lsu_bus_buffer.scala 291:25] + wire [31:0] obuf_addr_in = ibuf_buf_byp ? io_lsu_addr_r : _T_1289; // @[lsu_bus_buffer.scala 292:25] reg [1:0] buf_sz_0; // @[Reg.scala 27:20] wire [1:0] _T_1296 = _T_1023 ? buf_sz_0 : 2'h0; // @[Mux.scala 27:72] reg [1:0] buf_sz_1; // @[Reg.scala 27:20] @@ -69327,7 +69433,7 @@ module lsu_bus_buffer( wire [1:0] _T_1300 = _T_1296 | _T_1297; // @[Mux.scala 27:72] wire [1:0] _T_1301 = _T_1300 | _T_1298; // @[Mux.scala 27:72] wire [1:0] _T_1302 = _T_1301 | _T_1299; // @[Mux.scala 27:72] - wire [1:0] obuf_sz_in = ibuf_buf_byp ? ibuf_sz_in : _T_1302; // @[lsu_bus_buffer.scala 294:23] + wire [1:0] obuf_sz_in = ibuf_buf_byp ? ibuf_sz_in : _T_1302; // @[lsu_bus_buffer.scala 295:23] wire [7:0] _T_2079 = {4'h0,_T_2030,_T_2019,_T_2008,_T_1997}; // @[Cat.scala 29:58] wire _T_2082 = _T_2079[4] | _T_2079[5]; // @[lsu_bus_buffer.scala 385:42] wire _T_2084 = _T_2082 | _T_2079[6]; // @[lsu_bus_buffer.scala 385:48] @@ -69397,10 +69503,10 @@ module lsu_bus_buffer( wire [7:0] _T_1403 = {ldst_byteen_hi_r,4'h0}; // @[Cat.scala 29:58] wire [7:0] _T_1404 = {4'h0,ldst_byteen_hi_r}; // @[Cat.scala 29:58] wire [7:0] _T_1405 = io_end_addr_r[2] ? _T_1403 : _T_1404; // @[lsu_bus_buffer.scala 325:46] - wire _T_1406 = CmdPtr1 == 2'h0; // @[lsu_bus_buffer.scala 57:123] - wire _T_1407 = CmdPtr1 == 2'h1; // @[lsu_bus_buffer.scala 57:123] - wire _T_1408 = CmdPtr1 == 2'h2; // @[lsu_bus_buffer.scala 57:123] - wire _T_1409 = CmdPtr1 == 2'h3; // @[lsu_bus_buffer.scala 57:123] + wire _T_1406 = CmdPtr1 == 2'h0; // @[lsu_bus_buffer.scala 58:123] + wire _T_1407 = CmdPtr1 == 2'h1; // @[lsu_bus_buffer.scala 58:123] + wire _T_1408 = CmdPtr1 == 2'h2; // @[lsu_bus_buffer.scala 58:123] + wire _T_1409 = CmdPtr1 == 2'h3; // @[lsu_bus_buffer.scala 58:123] wire [31:0] _T_1410 = _T_1406 ? buf_addr_0 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1411 = _T_1407 ? buf_addr_1 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1412 = _T_1408 ? buf_addr_2 : 32'h0; // @[Mux.scala 27:72] @@ -69462,6 +69568,17 @@ module lsu_bus_buffer( wire _T_1651 = _T_1637 & _T_1650; // @[lsu_bus_buffer.scala 337:118] wire _T_1672 = _T_1651 & _T_1128; // @[lsu_bus_buffer.scala 337:161] wire _T_1690 = _T_1672 & _T_1053; // @[lsu_bus_buffer.scala 338:85] + wire _T_1715 = _T_1406 & buf_write[0]; // @[Mux.scala 27:72] + wire _T_1716 = _T_1407 & buf_write[1]; // @[Mux.scala 27:72] + wire _T_1719 = _T_1715 | _T_1716; // @[Mux.scala 27:72] + wire _T_1717 = _T_1408 & buf_write[2]; // @[Mux.scala 27:72] + wire _T_1720 = _T_1719 | _T_1717; // @[Mux.scala 27:72] + wire _T_1718 = _T_1409 & buf_write[3]; // @[Mux.scala 27:72] + wire _T_1721 = _T_1720 | _T_1718; // @[Mux.scala 27:72] + wire _T_1723 = _T_1202 & _T_1721; // @[lsu_bus_buffer.scala 339:36] + wire _T_1750 = _T_1289[31:3] == _T_1416[31:3]; // @[lsu_bus_buffer.scala 340:41] + wire _T_1751 = _T_1723 & _T_1750; // @[lsu_bus_buffer.scala 339:67] + wire _T_1753 = _T_1751 & _T_938; // @[lsu_bus_buffer.scala 340:79] wire _T_1792 = _T_1204 & _T_1166; // @[lsu_bus_buffer.scala 341:38] reg buf_dualhi_3; // @[Reg.scala 27:20] reg buf_dualhi_2; // @[Reg.scala 27:20] @@ -69478,7 +69595,8 @@ module lsu_bus_buffer( wire _T_1812 = ~_T_1810; // @[lsu_bus_buffer.scala 341:109] wire _T_1813 = _T_1792 & _T_1812; // @[lsu_bus_buffer.scala 341:107] wire _T_1833 = _T_1813 & _T_1185; // @[lsu_bus_buffer.scala 341:179] - wire _T_1835 = _T_1690 & _T_1833; // @[lsu_bus_buffer.scala 338:122] + wire _T_1834 = _T_1753 | _T_1833; // @[lsu_bus_buffer.scala 340:128] + wire _T_1835 = _T_1690 & _T_1834; // @[lsu_bus_buffer.scala 338:122] wire _T_1836 = ibuf_buf_byp & ldst_samedw_r; // @[lsu_bus_buffer.scala 342:19] wire _T_1837 = _T_1836 & io_ldst_dual_r; // @[lsu_bus_buffer.scala 342:35] wire obuf_merge_en = _T_1835 | _T_1837; // @[lsu_bus_buffer.scala 341:253] @@ -69548,7 +69666,6 @@ module lsu_bus_buffer( wire _T_1885 = _T_1875 & _T_1884; // @[lsu_bus_buffer.scala 363:76] wire _T_1886 = buf_state_3 == 3'h0; // @[lsu_bus_buffer.scala 363:65] wire _T_1887 = ibuf_tag == 2'h3; // @[lsu_bus_buffer.scala 364:30] - wire _T_1888 = ibuf_valid & _T_1887; // @[lsu_bus_buffer.scala 364:19] wire _T_1889 = WrPtr0_r == 2'h3; // @[lsu_bus_buffer.scala 365:18] wire _T_1890 = WrPtr1_r == 2'h3; // @[lsu_bus_buffer.scala 365:57] wire [1:0] _T_1898 = _T_1885 ? 2'h2 : 2'h3; // @[Mux.scala 98:16] @@ -69624,15 +69741,17 @@ module lsu_bus_buffer( wire _T_2125 = _T_2123 | _T_2104[7]; // @[lsu_bus_buffer.scala 385:104] wire [2:0] _T_2127 = {_T_2111,_T_2118,_T_2125}; // @[Cat.scala 29:58] wire _T_3532 = ibuf_byp | io_ldst_dual_r; // @[lsu_bus_buffer.scala 443:77] + wire _T_3533 = ~ibuf_merge_en; // @[lsu_bus_buffer.scala 443:97] + wire _T_3534 = _T_3532 & _T_3533; // @[lsu_bus_buffer.scala 443:95] wire _T_3535 = 2'h0 == WrPtr0_r; // @[lsu_bus_buffer.scala 443:117] - wire _T_3536 = _T_3532 & _T_3535; // @[lsu_bus_buffer.scala 443:112] + wire _T_3536 = _T_3534 & _T_3535; // @[lsu_bus_buffer.scala 443:112] wire _T_3537 = ibuf_byp & io_ldst_dual_r; // @[lsu_bus_buffer.scala 443:144] wire _T_3538 = 2'h0 == WrPtr1_r; // @[lsu_bus_buffer.scala 443:166] wire _T_3539 = _T_3537 & _T_3538; // @[lsu_bus_buffer.scala 443:161] wire _T_3540 = _T_3536 | _T_3539; // @[lsu_bus_buffer.scala 443:132] wire _T_3541 = _T_853 & _T_3540; // @[lsu_bus_buffer.scala 443:63] wire _T_3542 = 2'h0 == ibuf_tag; // @[lsu_bus_buffer.scala 443:206] - wire _T_3543 = ibuf_valid & _T_3542; // @[lsu_bus_buffer.scala 443:201] + wire _T_3543 = ibuf_drain_vld & _T_3542; // @[lsu_bus_buffer.scala 443:201] wire _T_3544 = _T_3541 | _T_3543; // @[lsu_bus_buffer.scala 443:183] wire _T_3554 = io_lsu_bus_clk_en | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 450:46] wire _T_3589 = 3'h3 == buf_state_0; // @[Conditional.scala 37:30] @@ -69700,7 +69819,7 @@ module lsu_bus_buffer( wire _GEN_64 = _T_3551 ? _T_3554 : _GEN_54; // @[Conditional.scala 39:67] wire buf_state_en_0 = _T_3528 ? _T_3544 : _GEN_64; // @[Conditional.scala 40:58] wire _T_2129 = _T_1853 & buf_state_en_0; // @[lsu_bus_buffer.scala 405:94] - wire _T_2135 = ibuf_valid & io_lsu_busreq_r; // @[lsu_bus_buffer.scala 407:23] + wire _T_2135 = ibuf_drain_vld & io_lsu_busreq_r; // @[lsu_bus_buffer.scala 407:23] wire _T_2137 = _T_2135 & _T_3532; // @[lsu_bus_buffer.scala 407:41] wire _T_2139 = _T_2137 & _T_1856; // @[lsu_bus_buffer.scala 407:71] wire _T_2141 = _T_2139 & _T_1854; // @[lsu_bus_buffer.scala 407:92] @@ -69732,13 +69851,13 @@ module lsu_bus_buffer( wire _T_2227 = _T_2225 | buf_age_0[3]; // @[lsu_bus_buffer.scala 408:97] wire [2:0] _T_2229 = {_T_2227,_T_2202,_T_2177}; // @[Cat.scala 29:58] wire _T_3728 = 2'h1 == WrPtr0_r; // @[lsu_bus_buffer.scala 443:117] - wire _T_3729 = _T_3532 & _T_3728; // @[lsu_bus_buffer.scala 443:112] + wire _T_3729 = _T_3534 & _T_3728; // @[lsu_bus_buffer.scala 443:112] wire _T_3731 = 2'h1 == WrPtr1_r; // @[lsu_bus_buffer.scala 443:166] wire _T_3732 = _T_3537 & _T_3731; // @[lsu_bus_buffer.scala 443:161] wire _T_3733 = _T_3729 | _T_3732; // @[lsu_bus_buffer.scala 443:132] wire _T_3734 = _T_853 & _T_3733; // @[lsu_bus_buffer.scala 443:63] wire _T_3735 = 2'h1 == ibuf_tag; // @[lsu_bus_buffer.scala 443:206] - wire _T_3736 = ibuf_valid & _T_3735; // @[lsu_bus_buffer.scala 443:201] + wire _T_3736 = ibuf_drain_vld & _T_3735; // @[lsu_bus_buffer.scala 443:201] wire _T_3737 = _T_3734 | _T_3736; // @[lsu_bus_buffer.scala 443:183] wire _T_3782 = 3'h3 == buf_state_1; // @[Conditional.scala 37:30] wire _T_3827 = io_lsu_axi_b_bits_id == 3'h1; // @[lsu_bus_buffer.scala 468:73] @@ -69822,13 +69941,13 @@ module lsu_bus_buffer( wire _T_2329 = _T_2327 | buf_age_1[3]; // @[lsu_bus_buffer.scala 408:97] wire [2:0] _T_2331 = {_T_2329,_T_2304,_T_2279}; // @[Cat.scala 29:58] wire _T_3921 = 2'h2 == WrPtr0_r; // @[lsu_bus_buffer.scala 443:117] - wire _T_3922 = _T_3532 & _T_3921; // @[lsu_bus_buffer.scala 443:112] + wire _T_3922 = _T_3534 & _T_3921; // @[lsu_bus_buffer.scala 443:112] wire _T_3924 = 2'h2 == WrPtr1_r; // @[lsu_bus_buffer.scala 443:166] wire _T_3925 = _T_3537 & _T_3924; // @[lsu_bus_buffer.scala 443:161] wire _T_3926 = _T_3922 | _T_3925; // @[lsu_bus_buffer.scala 443:132] wire _T_3927 = _T_853 & _T_3926; // @[lsu_bus_buffer.scala 443:63] wire _T_3928 = 2'h2 == ibuf_tag; // @[lsu_bus_buffer.scala 443:206] - wire _T_3929 = ibuf_valid & _T_3928; // @[lsu_bus_buffer.scala 443:201] + wire _T_3929 = ibuf_drain_vld & _T_3928; // @[lsu_bus_buffer.scala 443:201] wire _T_3930 = _T_3927 | _T_3929; // @[lsu_bus_buffer.scala 443:183] wire _T_3975 = 3'h3 == buf_state_2; // @[Conditional.scala 37:30] wire _T_4020 = io_lsu_axi_b_bits_id == 3'h2; // @[lsu_bus_buffer.scala 468:73] @@ -69912,13 +70031,13 @@ module lsu_bus_buffer( wire _T_2431 = _T_2429 | buf_age_2[3]; // @[lsu_bus_buffer.scala 408:97] wire [2:0] _T_2433 = {_T_2431,_T_2406,_T_2381}; // @[Cat.scala 29:58] wire _T_4114 = 2'h3 == WrPtr0_r; // @[lsu_bus_buffer.scala 443:117] - wire _T_4115 = _T_3532 & _T_4114; // @[lsu_bus_buffer.scala 443:112] + wire _T_4115 = _T_3534 & _T_4114; // @[lsu_bus_buffer.scala 443:112] wire _T_4117 = 2'h3 == WrPtr1_r; // @[lsu_bus_buffer.scala 443:166] wire _T_4118 = _T_3537 & _T_4117; // @[lsu_bus_buffer.scala 443:161] wire _T_4119 = _T_4115 | _T_4118; // @[lsu_bus_buffer.scala 443:132] wire _T_4120 = _T_853 & _T_4119; // @[lsu_bus_buffer.scala 443:63] wire _T_4121 = 2'h3 == ibuf_tag; // @[lsu_bus_buffer.scala 443:206] - wire _T_4122 = ibuf_valid & _T_4121; // @[lsu_bus_buffer.scala 443:201] + wire _T_4122 = ibuf_drain_vld & _T_4121; // @[lsu_bus_buffer.scala 443:201] wire _T_4123 = _T_4120 | _T_4122; // @[lsu_bus_buffer.scala 443:183] wire _T_4168 = 3'h3 == buf_state_3; // @[Conditional.scala 37:30] wire _T_4213 = io_lsu_axi_b_bits_id == 3'h3; // @[lsu_bus_buffer.scala 468:73] @@ -70113,7 +70232,11 @@ module lsu_bus_buffer( wire _T_3213 = buf_rspage_set_3[2] | buf_rspage_3[2]; // @[lsu_bus_buffer.scala 419:88] wire _T_3216 = buf_rspage_set_3[3] | buf_rspage_3[3]; // @[lsu_bus_buffer.scala 419:88] wire [2:0] _T_3218 = {_T_3216,_T_3213,_T_3210}; // @[Cat.scala 29:58] - wire [3:0] ibuf_drainvec_vld = {_T_1888,_T_1877,_T_1866,_T_1855}; // @[Cat.scala 29:58] + wire _T_3329 = ibuf_drain_vld & _T_1854; // @[lsu_bus_buffer.scala 425:63] + wire _T_3331 = ibuf_drain_vld & _T_1865; // @[lsu_bus_buffer.scala 425:63] + wire _T_3333 = ibuf_drain_vld & _T_1876; // @[lsu_bus_buffer.scala 425:63] + wire _T_3335 = ibuf_drain_vld & _T_1887; // @[lsu_bus_buffer.scala 425:63] + wire [3:0] ibuf_drainvec_vld = {_T_3335,_T_3333,_T_3331,_T_3329}; // @[Cat.scala 29:58] wire _T_3343 = _T_3537 & _T_1857; // @[lsu_bus_buffer.scala 427:35] wire _T_3352 = _T_3537 & _T_1868; // @[lsu_bus_buffer.scala 427:35] wire _T_3361 = _T_3537 & _T_1879; // @[lsu_bus_buffer.scala 427:35] @@ -70186,10 +70309,10 @@ module lsu_bus_buffer( wire _T_4495 = _T_4494 | _T_2740; // @[lsu_bus_buffer.scala 524:93] wire any_done_wait_state = _T_4495 | _T_2737; // @[lsu_bus_buffer.scala 524:93] wire _T_3604 = buf_ldfwd[0] | any_done_wait_state; // @[lsu_bus_buffer.scala 467:31] - wire _T_3610 = buf_dualtag_0 == 2'h0; // @[lsu_bus_buffer.scala 56:118] - wire _T_3612 = buf_dualtag_0 == 2'h1; // @[lsu_bus_buffer.scala 56:118] - wire _T_3614 = buf_dualtag_0 == 2'h2; // @[lsu_bus_buffer.scala 56:118] - wire _T_3616 = buf_dualtag_0 == 2'h3; // @[lsu_bus_buffer.scala 56:118] + wire _T_3610 = buf_dualtag_0 == 2'h0; // @[lsu_bus_buffer.scala 57:118] + wire _T_3612 = buf_dualtag_0 == 2'h1; // @[lsu_bus_buffer.scala 57:118] + wire _T_3614 = buf_dualtag_0 == 2'h2; // @[lsu_bus_buffer.scala 57:118] + wire _T_3616 = buf_dualtag_0 == 2'h3; // @[lsu_bus_buffer.scala 57:118] wire _T_3618 = _T_3610 & buf_ldfwd[0]; // @[Mux.scala 27:72] wire _T_3619 = _T_3612 & buf_ldfwd[1]; // @[Mux.scala 27:72] wire _T_3620 = _T_3614 & buf_ldfwd[2]; // @[Mux.scala 27:72] @@ -70250,10 +70373,10 @@ module lsu_bus_buffer( wire _T_3794 = _GEN_97 != 3'h4; // @[lsu_bus_buffer.scala 466:90] wire _T_3795 = _T_3793 & _T_3794; // @[lsu_bus_buffer.scala 466:61] wire _T_3797 = buf_ldfwd[1] | any_done_wait_state; // @[lsu_bus_buffer.scala 467:31] - wire _T_3803 = buf_dualtag_1 == 2'h0; // @[lsu_bus_buffer.scala 56:118] - wire _T_3805 = buf_dualtag_1 == 2'h1; // @[lsu_bus_buffer.scala 56:118] - wire _T_3807 = buf_dualtag_1 == 2'h2; // @[lsu_bus_buffer.scala 56:118] - wire _T_3809 = buf_dualtag_1 == 2'h3; // @[lsu_bus_buffer.scala 56:118] + wire _T_3803 = buf_dualtag_1 == 2'h0; // @[lsu_bus_buffer.scala 57:118] + wire _T_3805 = buf_dualtag_1 == 2'h1; // @[lsu_bus_buffer.scala 57:118] + wire _T_3807 = buf_dualtag_1 == 2'h2; // @[lsu_bus_buffer.scala 57:118] + wire _T_3809 = buf_dualtag_1 == 2'h3; // @[lsu_bus_buffer.scala 57:118] wire _T_3811 = _T_3803 & buf_ldfwd[0]; // @[Mux.scala 27:72] wire _T_3812 = _T_3805 & buf_ldfwd[1]; // @[Mux.scala 27:72] wire _T_3813 = _T_3807 & buf_ldfwd[2]; // @[Mux.scala 27:72] @@ -70314,10 +70437,10 @@ module lsu_bus_buffer( wire _T_3987 = _GEN_173 != 3'h4; // @[lsu_bus_buffer.scala 466:90] wire _T_3988 = _T_3986 & _T_3987; // @[lsu_bus_buffer.scala 466:61] wire _T_3990 = buf_ldfwd[2] | any_done_wait_state; // @[lsu_bus_buffer.scala 467:31] - wire _T_3996 = buf_dualtag_2 == 2'h0; // @[lsu_bus_buffer.scala 56:118] - wire _T_3998 = buf_dualtag_2 == 2'h1; // @[lsu_bus_buffer.scala 56:118] - wire _T_4000 = buf_dualtag_2 == 2'h2; // @[lsu_bus_buffer.scala 56:118] - wire _T_4002 = buf_dualtag_2 == 2'h3; // @[lsu_bus_buffer.scala 56:118] + wire _T_3996 = buf_dualtag_2 == 2'h0; // @[lsu_bus_buffer.scala 57:118] + wire _T_3998 = buf_dualtag_2 == 2'h1; // @[lsu_bus_buffer.scala 57:118] + wire _T_4000 = buf_dualtag_2 == 2'h2; // @[lsu_bus_buffer.scala 57:118] + wire _T_4002 = buf_dualtag_2 == 2'h3; // @[lsu_bus_buffer.scala 57:118] wire _T_4004 = _T_3996 & buf_ldfwd[0]; // @[Mux.scala 27:72] wire _T_4005 = _T_3998 & buf_ldfwd[1]; // @[Mux.scala 27:72] wire _T_4006 = _T_4000 & buf_ldfwd[2]; // @[Mux.scala 27:72] @@ -70378,10 +70501,10 @@ module lsu_bus_buffer( wire _T_4180 = _GEN_249 != 3'h4; // @[lsu_bus_buffer.scala 466:90] wire _T_4181 = _T_4179 & _T_4180; // @[lsu_bus_buffer.scala 466:61] wire _T_4183 = buf_ldfwd[3] | any_done_wait_state; // @[lsu_bus_buffer.scala 467:31] - wire _T_4189 = buf_dualtag_3 == 2'h0; // @[lsu_bus_buffer.scala 56:118] - wire _T_4191 = buf_dualtag_3 == 2'h1; // @[lsu_bus_buffer.scala 56:118] - wire _T_4193 = buf_dualtag_3 == 2'h2; // @[lsu_bus_buffer.scala 56:118] - wire _T_4195 = buf_dualtag_3 == 2'h3; // @[lsu_bus_buffer.scala 56:118] + wire _T_4189 = buf_dualtag_3 == 2'h0; // @[lsu_bus_buffer.scala 57:118] + wire _T_4191 = buf_dualtag_3 == 2'h1; // @[lsu_bus_buffer.scala 57:118] + wire _T_4193 = buf_dualtag_3 == 2'h2; // @[lsu_bus_buffer.scala 57:118] + wire _T_4195 = buf_dualtag_3 == 2'h3; // @[lsu_bus_buffer.scala 57:118] wire _T_4197 = _T_4189 & buf_ldfwd[0]; // @[Mux.scala 27:72] wire _T_4198 = _T_4191 & buf_ldfwd[1]; // @[Mux.scala 27:72] wire _T_4199 = _T_4193 & buf_ldfwd[2]; // @[Mux.scala 27:72] @@ -70522,10 +70645,10 @@ module lsu_bus_buffer( wire [31:0] _T_4680 = _T_4676 | _T_4677; // @[Mux.scala 27:72] wire [31:0] _T_4681 = _T_4680 | _T_4678; // @[Mux.scala 27:72] wire [31:0] lsu_nonblock_load_data_hi = _T_4681 | _T_4679; // @[Mux.scala 27:72] - wire _T_4683 = io_dctl_busbuff_lsu_nonblock_load_data_tag == 2'h0; // @[lsu_bus_buffer.scala 57:123] - wire _T_4684 = io_dctl_busbuff_lsu_nonblock_load_data_tag == 2'h1; // @[lsu_bus_buffer.scala 57:123] - wire _T_4685 = io_dctl_busbuff_lsu_nonblock_load_data_tag == 2'h2; // @[lsu_bus_buffer.scala 57:123] - wire _T_4686 = io_dctl_busbuff_lsu_nonblock_load_data_tag == 2'h3; // @[lsu_bus_buffer.scala 57:123] + wire _T_4683 = io_dctl_busbuff_lsu_nonblock_load_data_tag == 2'h0; // @[lsu_bus_buffer.scala 58:123] + wire _T_4684 = io_dctl_busbuff_lsu_nonblock_load_data_tag == 2'h1; // @[lsu_bus_buffer.scala 58:123] + wire _T_4685 = io_dctl_busbuff_lsu_nonblock_load_data_tag == 2'h2; // @[lsu_bus_buffer.scala 58:123] + wire _T_4686 = io_dctl_busbuff_lsu_nonblock_load_data_tag == 2'h3; // @[lsu_bus_buffer.scala 58:123] wire [31:0] _T_4687 = _T_4683 ? buf_addr_0 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_4688 = _T_4684 ? buf_addr_1 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_4689 = _T_4685 ? buf_addr_2 : 32'h0; // @[Mux.scala 27:72] @@ -70718,7 +70841,9 @@ module lsu_bus_buffer( assign io_lsu_axi_aw_valid = _T_4874 & _T_4875; // @[lsu_bus_buffer.scala 568:23] assign io_lsu_axi_aw_bits_id = {{1'd0}, _T_1848}; // @[lsu_bus_buffer.scala 569:25] assign io_lsu_axi_aw_bits_addr = obuf_sideeffect ? obuf_addr : _T_4880; // @[lsu_bus_buffer.scala 570:27] + assign io_lsu_axi_aw_bits_region = obuf_addr[31:28]; // @[lsu_bus_buffer.scala 574:29] assign io_lsu_axi_aw_bits_size = obuf_sideeffect ? _T_4882 : 3'h3; // @[lsu_bus_buffer.scala 571:27] + assign io_lsu_axi_aw_bits_cache = obuf_sideeffect ? 4'h0 : 4'hf; // @[lsu_bus_buffer.scala 573:28] assign io_lsu_axi_w_valid = _T_4874 & _T_4887; // @[lsu_bus_buffer.scala 580:22] assign io_lsu_axi_w_bits_data = obuf_data; // @[lsu_bus_buffer.scala 582:26] assign io_lsu_axi_w_bits_strb = obuf_byteen & _T_4892; // @[lsu_bus_buffer.scala 581:26] @@ -70726,16 +70851,18 @@ module lsu_bus_buffer( assign io_lsu_axi_ar_valid = _T_4895 & _T_1349; // @[lsu_bus_buffer.scala 585:23] assign io_lsu_axi_ar_bits_id = {{1'd0}, _T_1848}; // @[lsu_bus_buffer.scala 586:25] assign io_lsu_axi_ar_bits_addr = obuf_sideeffect ? obuf_addr : _T_4880; // @[lsu_bus_buffer.scala 587:27] + assign io_lsu_axi_ar_bits_region = obuf_addr[31:28]; // @[lsu_bus_buffer.scala 591:29] assign io_lsu_axi_ar_bits_size = obuf_sideeffect ? _T_4882 : 3'h3; // @[lsu_bus_buffer.scala 588:27] + assign io_lsu_axi_ar_bits_cache = obuf_sideeffect ? 4'h0 : 4'hf; // @[lsu_bus_buffer.scala 590:28] assign io_lsu_axi_r_ready = 1'h1; // @[lsu_bus_buffer.scala 597:22] assign io_lsu_busreq_r = _T_4987; // @[lsu_bus_buffer.scala 616:19] assign io_lsu_bus_buffer_pend_any = |buf_numvld_pend_any; // @[lsu_bus_buffer.scala 525:30] assign io_lsu_bus_buffer_full_any = _T_4498 ? _T_4499 : _T_4500; // @[lsu_bus_buffer.scala 526:30] assign io_lsu_bus_buffer_empty_any = _T_4511 & _T_1231; // @[lsu_bus_buffer.scala 527:31] - assign io_ld_byte_hit_buf_lo = {_T_69,_T_58}; // @[lsu_bus_buffer.scala 137:25] - assign io_ld_byte_hit_buf_hi = {_T_84,_T_73}; // @[lsu_bus_buffer.scala 138:25] - assign io_ld_fwddata_buf_lo = _T_650 | _T_651; // @[lsu_bus_buffer.scala 164:24] - assign io_ld_fwddata_buf_hi = _T_747 | _T_748; // @[lsu_bus_buffer.scala 170:24] + assign io_ld_byte_hit_buf_lo = {_T_69,_T_58}; // @[lsu_bus_buffer.scala 138:25] + assign io_ld_byte_hit_buf_hi = {_T_84,_T_73}; // @[lsu_bus_buffer.scala 139:25] + assign io_ld_fwddata_buf_lo = _T_650 | _T_651; // @[lsu_bus_buffer.scala 165:24] + assign io_ld_fwddata_buf_hi = _T_747 | _T_748; // @[lsu_bus_buffer.scala 171:24] assign rvclkhdr_io_clk = clock; // @[lib.scala 370:18] assign rvclkhdr_io_en = _T_853 & _T_854; // @[lib.scala 371:17] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] @@ -70743,10 +70870,10 @@ module lsu_bus_buffer( assign rvclkhdr_1_io_en = _T_853 & _T_854; // @[lib.scala 371:17] assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_2_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_2_io_en = _T_1234 & io_lsu_bus_clk_en; // @[lib.scala 371:17] + assign rvclkhdr_2_io_en = _T_1236 & io_lsu_bus_clk_en; // @[lib.scala 371:17] assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_3_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_3_io_en = _T_1234 & io_lsu_bus_clk_en; // @[lib.scala 371:17] + assign rvclkhdr_3_io_en = _T_1236 & io_lsu_bus_clk_en; // @[lib.scala 371:17] assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_4_io_clk = clock; // @[lib.scala 370:18] assign rvclkhdr_4_io_en = _T_3528 & buf_state_en_0; // @[lib.scala 371:17] @@ -70876,147 +71003,151 @@ initial begin _RAND_33 = {1{`RANDOM}}; ibuf_data = _RAND_33[31:0]; _RAND_34 = {1{`RANDOM}}; - ibuf_sideeffect = _RAND_34[0:0]; + ibuf_timer = _RAND_34[2:0]; _RAND_35 = {1{`RANDOM}}; - WrPtr1_r = _RAND_35[1:0]; + ibuf_sideeffect = _RAND_35[0:0]; _RAND_36 = {1{`RANDOM}}; - WrPtr0_r = _RAND_36[1:0]; + WrPtr1_r = _RAND_36[1:0]; _RAND_37 = {1{`RANDOM}}; - ibuf_tag = _RAND_37[1:0]; + WrPtr0_r = _RAND_37[1:0]; _RAND_38 = {1{`RANDOM}}; - ibuf_dualtag = _RAND_38[1:0]; + ibuf_tag = _RAND_38[1:0]; _RAND_39 = {1{`RANDOM}}; - ibuf_dual = _RAND_39[0:0]; + ibuf_dualtag = _RAND_39[1:0]; _RAND_40 = {1{`RANDOM}}; - ibuf_samedw = _RAND_40[0:0]; + ibuf_dual = _RAND_40[0:0]; _RAND_41 = {1{`RANDOM}}; - ibuf_nomerge = _RAND_41[0:0]; + ibuf_samedw = _RAND_41[0:0]; _RAND_42 = {1{`RANDOM}}; - ibuf_unsign = _RAND_42[0:0]; + ibuf_nomerge = _RAND_42[0:0]; _RAND_43 = {1{`RANDOM}}; - ibuf_sz = _RAND_43[1:0]; + ibuf_unsign = _RAND_43[0:0]; _RAND_44 = {1{`RANDOM}}; - buf_nomerge_0 = _RAND_44[0:0]; + ibuf_sz = _RAND_44[1:0]; _RAND_45 = {1{`RANDOM}}; - buf_nomerge_1 = _RAND_45[0:0]; + obuf_wr_timer = _RAND_45[2:0]; _RAND_46 = {1{`RANDOM}}; - buf_nomerge_2 = _RAND_46[0:0]; + buf_nomerge_0 = _RAND_46[0:0]; _RAND_47 = {1{`RANDOM}}; - buf_nomerge_3 = _RAND_47[0:0]; + buf_nomerge_1 = _RAND_47[0:0]; _RAND_48 = {1{`RANDOM}}; - _T_4330 = _RAND_48[0:0]; + buf_nomerge_2 = _RAND_48[0:0]; _RAND_49 = {1{`RANDOM}}; - _T_4327 = _RAND_49[0:0]; + buf_nomerge_3 = _RAND_49[0:0]; _RAND_50 = {1{`RANDOM}}; - _T_4324 = _RAND_50[0:0]; + _T_4330 = _RAND_50[0:0]; _RAND_51 = {1{`RANDOM}}; - _T_4321 = _RAND_51[0:0]; + _T_4327 = _RAND_51[0:0]; _RAND_52 = {1{`RANDOM}}; - obuf_sideeffect = _RAND_52[0:0]; + _T_4324 = _RAND_52[0:0]; _RAND_53 = {1{`RANDOM}}; - buf_dual_3 = _RAND_53[0:0]; + _T_4321 = _RAND_53[0:0]; _RAND_54 = {1{`RANDOM}}; - buf_dual_2 = _RAND_54[0:0]; + obuf_sideeffect = _RAND_54[0:0]; _RAND_55 = {1{`RANDOM}}; - buf_dual_1 = _RAND_55[0:0]; + buf_dual_3 = _RAND_55[0:0]; _RAND_56 = {1{`RANDOM}}; - buf_dual_0 = _RAND_56[0:0]; + buf_dual_2 = _RAND_56[0:0]; _RAND_57 = {1{`RANDOM}}; - buf_samedw_3 = _RAND_57[0:0]; + buf_dual_1 = _RAND_57[0:0]; _RAND_58 = {1{`RANDOM}}; - buf_samedw_2 = _RAND_58[0:0]; + buf_dual_0 = _RAND_58[0:0]; _RAND_59 = {1{`RANDOM}}; - buf_samedw_1 = _RAND_59[0:0]; + buf_samedw_3 = _RAND_59[0:0]; _RAND_60 = {1{`RANDOM}}; - buf_samedw_0 = _RAND_60[0:0]; + buf_samedw_2 = _RAND_60[0:0]; _RAND_61 = {1{`RANDOM}}; - obuf_write = _RAND_61[0:0]; + buf_samedw_1 = _RAND_61[0:0]; _RAND_62 = {1{`RANDOM}}; - obuf_cmd_done = _RAND_62[0:0]; + buf_samedw_0 = _RAND_62[0:0]; _RAND_63 = {1{`RANDOM}}; - obuf_data_done = _RAND_63[0:0]; + obuf_write = _RAND_63[0:0]; _RAND_64 = {1{`RANDOM}}; - obuf_nosend = _RAND_64[0:0]; + obuf_cmd_done = _RAND_64[0:0]; _RAND_65 = {1{`RANDOM}}; - obuf_addr = _RAND_65[31:0]; + obuf_data_done = _RAND_65[0:0]; _RAND_66 = {1{`RANDOM}}; - buf_sz_0 = _RAND_66[1:0]; + obuf_nosend = _RAND_66[0:0]; _RAND_67 = {1{`RANDOM}}; - buf_sz_1 = _RAND_67[1:0]; + obuf_addr = _RAND_67[31:0]; _RAND_68 = {1{`RANDOM}}; - buf_sz_2 = _RAND_68[1:0]; + buf_sz_0 = _RAND_68[1:0]; _RAND_69 = {1{`RANDOM}}; - buf_sz_3 = _RAND_69[1:0]; + buf_sz_1 = _RAND_69[1:0]; _RAND_70 = {1{`RANDOM}}; - obuf_rdrsp_pend = _RAND_70[0:0]; + buf_sz_2 = _RAND_70[1:0]; _RAND_71 = {1{`RANDOM}}; - obuf_rdrsp_tag = _RAND_71[2:0]; + buf_sz_3 = _RAND_71[1:0]; _RAND_72 = {1{`RANDOM}}; - buf_dualhi_3 = _RAND_72[0:0]; + obuf_rdrsp_pend = _RAND_72[0:0]; _RAND_73 = {1{`RANDOM}}; - buf_dualhi_2 = _RAND_73[0:0]; + obuf_rdrsp_tag = _RAND_73[2:0]; _RAND_74 = {1{`RANDOM}}; - buf_dualhi_1 = _RAND_74[0:0]; + buf_dualhi_3 = _RAND_74[0:0]; _RAND_75 = {1{`RANDOM}}; - buf_dualhi_0 = _RAND_75[0:0]; + buf_dualhi_2 = _RAND_75[0:0]; _RAND_76 = {1{`RANDOM}}; - obuf_sz = _RAND_76[1:0]; + buf_dualhi_1 = _RAND_76[0:0]; _RAND_77 = {1{`RANDOM}}; - obuf_byteen = _RAND_77[7:0]; - _RAND_78 = {2{`RANDOM}}; - obuf_data = _RAND_78[63:0]; + buf_dualhi_0 = _RAND_77[0:0]; + _RAND_78 = {1{`RANDOM}}; + obuf_sz = _RAND_78[1:0]; _RAND_79 = {1{`RANDOM}}; - buf_rspageQ_0 = _RAND_79[3:0]; - _RAND_80 = {1{`RANDOM}}; - buf_rspageQ_1 = _RAND_80[3:0]; + obuf_byteen = _RAND_79[7:0]; + _RAND_80 = {2{`RANDOM}}; + obuf_data = _RAND_80[63:0]; _RAND_81 = {1{`RANDOM}}; - buf_rspageQ_2 = _RAND_81[3:0]; + buf_rspageQ_0 = _RAND_81[3:0]; _RAND_82 = {1{`RANDOM}}; - buf_rspageQ_3 = _RAND_82[3:0]; + buf_rspageQ_1 = _RAND_82[3:0]; _RAND_83 = {1{`RANDOM}}; - _T_4307 = _RAND_83[0:0]; + buf_rspageQ_2 = _RAND_83[3:0]; _RAND_84 = {1{`RANDOM}}; - _T_4305 = _RAND_84[0:0]; + buf_rspageQ_3 = _RAND_84[3:0]; _RAND_85 = {1{`RANDOM}}; - _T_4303 = _RAND_85[0:0]; + _T_4307 = _RAND_85[0:0]; _RAND_86 = {1{`RANDOM}}; - _T_4301 = _RAND_86[0:0]; + _T_4305 = _RAND_86[0:0]; _RAND_87 = {1{`RANDOM}}; - buf_ldfwdtag_0 = _RAND_87[1:0]; + _T_4303 = _RAND_87[0:0]; _RAND_88 = {1{`RANDOM}}; - buf_dualtag_0 = _RAND_88[1:0]; + _T_4301 = _RAND_88[0:0]; _RAND_89 = {1{`RANDOM}}; - buf_ldfwdtag_3 = _RAND_89[1:0]; + buf_ldfwdtag_0 = _RAND_89[1:0]; _RAND_90 = {1{`RANDOM}}; - buf_ldfwdtag_2 = _RAND_90[1:0]; + buf_dualtag_0 = _RAND_90[1:0]; _RAND_91 = {1{`RANDOM}}; - buf_ldfwdtag_1 = _RAND_91[1:0]; + buf_ldfwdtag_3 = _RAND_91[1:0]; _RAND_92 = {1{`RANDOM}}; - buf_dualtag_1 = _RAND_92[1:0]; + buf_ldfwdtag_2 = _RAND_92[1:0]; _RAND_93 = {1{`RANDOM}}; - buf_dualtag_2 = _RAND_93[1:0]; + buf_ldfwdtag_1 = _RAND_93[1:0]; _RAND_94 = {1{`RANDOM}}; - buf_dualtag_3 = _RAND_94[1:0]; + buf_dualtag_1 = _RAND_94[1:0]; _RAND_95 = {1{`RANDOM}}; - _T_4336 = _RAND_95[0:0]; + buf_dualtag_2 = _RAND_95[1:0]; _RAND_96 = {1{`RANDOM}}; - _T_4339 = _RAND_96[0:0]; + buf_dualtag_3 = _RAND_96[1:0]; _RAND_97 = {1{`RANDOM}}; - _T_4342 = _RAND_97[0:0]; + _T_4336 = _RAND_97[0:0]; _RAND_98 = {1{`RANDOM}}; - _T_4345 = _RAND_98[0:0]; + _T_4339 = _RAND_98[0:0]; _RAND_99 = {1{`RANDOM}}; - _T_4411 = _RAND_99[0:0]; + _T_4342 = _RAND_99[0:0]; _RAND_100 = {1{`RANDOM}}; - _T_4406 = _RAND_100[0:0]; + _T_4345 = _RAND_100[0:0]; _RAND_101 = {1{`RANDOM}}; - _T_4401 = _RAND_101[0:0]; + _T_4411 = _RAND_101[0:0]; _RAND_102 = {1{`RANDOM}}; - _T_4396 = _RAND_102[0:0]; + _T_4406 = _RAND_102[0:0]; _RAND_103 = {1{`RANDOM}}; - lsu_nonblock_load_valid_r = _RAND_103[0:0]; + _T_4401 = _RAND_103[0:0]; _RAND_104 = {1{`RANDOM}}; - _T_4987 = _RAND_104[0:0]; + _T_4396 = _RAND_104[0:0]; + _RAND_105 = {1{`RANDOM}}; + lsu_nonblock_load_valid_r = _RAND_105[0:0]; + _RAND_106 = {1{`RANDOM}}; + _T_4987 = _RAND_106[0:0]; `endif // RANDOMIZE_REG_INIT if (reset) begin buf_addr_0 = 32'h0; @@ -71120,6 +71251,9 @@ initial begin if (reset) begin ibuf_data = 32'h0; end + if (reset) begin + ibuf_timer = 3'h0; + end if (reset) begin ibuf_sideeffect = 1'h0; end @@ -71150,6 +71284,9 @@ initial begin if (reset) begin ibuf_sz = 2'h0; end + if (reset) begin + obuf_wr_timer = 3'h0; + end if (reset) begin buf_nomerge_0 = 1'h0; end @@ -71722,7 +71859,7 @@ end // initial if (reset) begin obuf_wr_enQ <= 1'h0; end else begin - obuf_wr_enQ <= _T_1234 & io_lsu_bus_clk_en; + obuf_wr_enQ <= _T_1236 & io_lsu_bus_clk_en; end end always @(posedge rvclkhdr_io_l1clk or posedge reset) begin @@ -71752,7 +71889,9 @@ end // initial if (reset) begin ibuf_byteen <= 4'h0; end else if (ibuf_wr_en) begin - if (io_ldst_dual_r) begin + if (_T_866) begin + ibuf_byteen <= _T_881; + end else if (io_ldst_dual_r) begin ibuf_byteen <= ldst_byteen_hi_r; end else begin ibuf_byteen <= ldst_byteen_lo_r; @@ -71916,7 +72055,16 @@ end // initial if (reset) begin ibuf_data <= 32'h0; end else begin - ibuf_data <= {_T_922,_T_892}; + ibuf_data <= {_T_922,_T_893}; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + ibuf_timer <= 3'h0; + end else if (ibuf_wr_en) begin + ibuf_timer <= 3'h0; + end else if (_T_923) begin + ibuf_timer <= _T_926; end end always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin @@ -71956,10 +72104,12 @@ end // initial if (reset) begin ibuf_tag <= 2'h0; end else if (ibuf_wr_en) begin - if (io_ldst_dual_r) begin - ibuf_tag <= WrPtr1_r; - end else begin - ibuf_tag <= WrPtr0_r; + if (!(_T_866)) begin + if (io_ldst_dual_r) begin + ibuf_tag <= WrPtr1_r; + end else begin + ibuf_tag <= WrPtr0_r; + end end end end @@ -72005,6 +72155,15 @@ end // initial ibuf_sz <= ibuf_sz_in; end end + always @(posedge io_lsu_busm_clk or posedge reset) begin + if (reset) begin + obuf_wr_timer <= 3'h0; + end else if (obuf_wr_en) begin + obuf_wr_timer <= 3'h0; + end else if (_T_1058) begin + obuf_wr_timer <= _T_1060; + end + end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin buf_nomerge_0 <= 1'h0; @@ -72552,6 +72711,7 @@ module lsu_bus_intf( output io_tlu_busbuff_lsu_pmu_bus_error, output io_tlu_busbuff_lsu_pmu_bus_busy, input io_tlu_busbuff_dec_tlu_external_ldfwd_disable, + input io_tlu_busbuff_dec_tlu_wb_coalescing_disable, input io_tlu_busbuff_dec_tlu_sideeffect_posted_disable, output io_tlu_busbuff_lsu_imprecise_error_load_any, output io_tlu_busbuff_lsu_imprecise_error_store_any, @@ -72569,7 +72729,9 @@ module lsu_bus_intf( output io_axi_aw_valid, output [2:0] io_axi_aw_bits_id, output [31:0] io_axi_aw_bits_addr, + output [3:0] io_axi_aw_bits_region, output [2:0] io_axi_aw_bits_size, + output [3:0] io_axi_aw_bits_cache, input io_axi_w_ready, output io_axi_w_valid, output [63:0] io_axi_w_bits_data, @@ -72580,7 +72742,9 @@ module lsu_bus_intf( output io_axi_ar_valid, output [2:0] io_axi_ar_bits_id, output [31:0] io_axi_ar_bits_addr, + output [3:0] io_axi_ar_bits_region, output [2:0] io_axi_ar_bits_size, + output [3:0] io_axi_ar_bits_cache, input io_axi_r_valid, input [2:0] io_axi_r_bits_id, input [63:0] io_axi_r_bits_data, @@ -72633,196 +72797,201 @@ module lsu_bus_intf( reg [31:0] _RAND_3; reg [31:0] _RAND_4; `endif // RANDOMIZE_REG_INIT - wire bus_buffer_clock; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_reset; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_scan_mode; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_tlu_busbuff_lsu_pmu_bus_trxn; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_tlu_busbuff_lsu_pmu_bus_error; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_tlu_busbuff_lsu_pmu_bus_busy; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_intf.scala 101:39] - wire [31:0] bus_buffer_io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[lsu_bus_intf.scala 101:39] - wire [1:0] bus_buffer_io_dctl_busbuff_lsu_nonblock_load_tag_m; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_dctl_busbuff_lsu_nonblock_load_inv_r; // @[lsu_bus_intf.scala 101:39] - wire [1:0] bus_buffer_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_valid; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_error; // @[lsu_bus_intf.scala 101:39] - wire [1:0] bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_tag; // @[lsu_bus_intf.scala 101:39] - wire [31:0] bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_dec_tlu_force_halt; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_lsu_c2_r_clk; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_lsu_bus_ibuf_c1_clk; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_lsu_bus_obuf_c1_clk; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_lsu_bus_buf_c1_clk; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_lsu_free_c2_clk; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_lsu_busm_clk; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_dec_lsu_valid_raw_d; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_lsu_pkt_m_valid; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_lsu_pkt_m_bits_load; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_lsu_pkt_r_bits_by; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_lsu_pkt_r_bits_half; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_lsu_pkt_r_bits_word; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_lsu_pkt_r_bits_load; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_lsu_pkt_r_bits_unsign; // @[lsu_bus_intf.scala 101:39] - wire [31:0] bus_buffer_io_lsu_addr_m; // @[lsu_bus_intf.scala 101:39] - wire [31:0] bus_buffer_io_end_addr_m; // @[lsu_bus_intf.scala 101:39] - wire [31:0] bus_buffer_io_lsu_addr_r; // @[lsu_bus_intf.scala 101:39] - wire [31:0] bus_buffer_io_end_addr_r; // @[lsu_bus_intf.scala 101:39] - wire [31:0] bus_buffer_io_store_data_r; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_no_word_merge_r; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_no_dword_merge_r; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_lsu_busreq_m; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_ld_full_hit_m; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_flush_m_up; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_flush_r; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_lsu_commit_r; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_is_sideeffects_r; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_ldst_dual_d; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_ldst_dual_m; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_ldst_dual_r; // @[lsu_bus_intf.scala 101:39] - wire [7:0] bus_buffer_io_ldst_byteen_ext_m; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_lsu_axi_aw_ready; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_lsu_axi_aw_valid; // @[lsu_bus_intf.scala 101:39] - wire [2:0] bus_buffer_io_lsu_axi_aw_bits_id; // @[lsu_bus_intf.scala 101:39] - wire [31:0] bus_buffer_io_lsu_axi_aw_bits_addr; // @[lsu_bus_intf.scala 101:39] - wire [2:0] bus_buffer_io_lsu_axi_aw_bits_size; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_lsu_axi_w_ready; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_lsu_axi_w_valid; // @[lsu_bus_intf.scala 101:39] - wire [63:0] bus_buffer_io_lsu_axi_w_bits_data; // @[lsu_bus_intf.scala 101:39] - wire [7:0] bus_buffer_io_lsu_axi_w_bits_strb; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_lsu_axi_b_ready; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_lsu_axi_b_valid; // @[lsu_bus_intf.scala 101:39] - wire [2:0] bus_buffer_io_lsu_axi_b_bits_id; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_lsu_axi_ar_ready; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_lsu_axi_ar_valid; // @[lsu_bus_intf.scala 101:39] - wire [2:0] bus_buffer_io_lsu_axi_ar_bits_id; // @[lsu_bus_intf.scala 101:39] - wire [31:0] bus_buffer_io_lsu_axi_ar_bits_addr; // @[lsu_bus_intf.scala 101:39] - wire [2:0] bus_buffer_io_lsu_axi_ar_bits_size; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_lsu_axi_r_ready; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_lsu_axi_r_valid; // @[lsu_bus_intf.scala 101:39] - wire [2:0] bus_buffer_io_lsu_axi_r_bits_id; // @[lsu_bus_intf.scala 101:39] - wire [63:0] bus_buffer_io_lsu_axi_r_bits_data; // @[lsu_bus_intf.scala 101:39] - wire [1:0] bus_buffer_io_lsu_axi_r_bits_resp; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_lsu_bus_clk_en; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_lsu_bus_clk_en_q; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_lsu_busreq_r; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_lsu_bus_buffer_pend_any; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_lsu_bus_buffer_full_any; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_lsu_bus_buffer_empty_any; // @[lsu_bus_intf.scala 101:39] - wire [3:0] bus_buffer_io_ld_byte_hit_buf_lo; // @[lsu_bus_intf.scala 101:39] - wire [3:0] bus_buffer_io_ld_byte_hit_buf_hi; // @[lsu_bus_intf.scala 101:39] - wire [31:0] bus_buffer_io_ld_fwddata_buf_lo; // @[lsu_bus_intf.scala 101:39] - wire [31:0] bus_buffer_io_ld_fwddata_buf_hi; // @[lsu_bus_intf.scala 101:39] + wire bus_buffer_clock; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_reset; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_scan_mode; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_lsu_pmu_bus_trxn; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_lsu_pmu_bus_error; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_lsu_pmu_bus_busy; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[lsu_bus_intf.scala 100:39] + wire [1:0] bus_buffer_io_dctl_busbuff_lsu_nonblock_load_tag_m; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_dctl_busbuff_lsu_nonblock_load_inv_r; // @[lsu_bus_intf.scala 100:39] + wire [1:0] bus_buffer_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_valid; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_error; // @[lsu_bus_intf.scala 100:39] + wire [1:0] bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_tag; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_dec_tlu_force_halt; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_c2_r_clk; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_bus_ibuf_c1_clk; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_bus_obuf_c1_clk; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_bus_buf_c1_clk; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_free_c2_clk; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_busm_clk; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_dec_lsu_valid_raw_d; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_pkt_m_valid; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_pkt_m_bits_load; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_pkt_r_bits_by; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_pkt_r_bits_half; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_pkt_r_bits_word; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_pkt_r_bits_load; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_pkt_r_bits_unsign; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_lsu_addr_m; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_end_addr_m; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_lsu_addr_r; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_end_addr_r; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_store_data_r; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_no_word_merge_r; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_no_dword_merge_r; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_busreq_m; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_ld_full_hit_m; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_flush_m_up; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_flush_r; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_commit_r; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_is_sideeffects_r; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_ldst_dual_d; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_ldst_dual_m; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_ldst_dual_r; // @[lsu_bus_intf.scala 100:39] + wire [7:0] bus_buffer_io_ldst_byteen_ext_m; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_aw_ready; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_aw_valid; // @[lsu_bus_intf.scala 100:39] + wire [2:0] bus_buffer_io_lsu_axi_aw_bits_id; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_lsu_axi_aw_bits_addr; // @[lsu_bus_intf.scala 100:39] + wire [3:0] bus_buffer_io_lsu_axi_aw_bits_region; // @[lsu_bus_intf.scala 100:39] + wire [2:0] bus_buffer_io_lsu_axi_aw_bits_size; // @[lsu_bus_intf.scala 100:39] + wire [3:0] bus_buffer_io_lsu_axi_aw_bits_cache; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_w_ready; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_w_valid; // @[lsu_bus_intf.scala 100:39] + wire [63:0] bus_buffer_io_lsu_axi_w_bits_data; // @[lsu_bus_intf.scala 100:39] + wire [7:0] bus_buffer_io_lsu_axi_w_bits_strb; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_b_ready; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_b_valid; // @[lsu_bus_intf.scala 100:39] + wire [2:0] bus_buffer_io_lsu_axi_b_bits_id; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_ar_ready; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_ar_valid; // @[lsu_bus_intf.scala 100:39] + wire [2:0] bus_buffer_io_lsu_axi_ar_bits_id; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_lsu_axi_ar_bits_addr; // @[lsu_bus_intf.scala 100:39] + wire [3:0] bus_buffer_io_lsu_axi_ar_bits_region; // @[lsu_bus_intf.scala 100:39] + wire [2:0] bus_buffer_io_lsu_axi_ar_bits_size; // @[lsu_bus_intf.scala 100:39] + wire [3:0] bus_buffer_io_lsu_axi_ar_bits_cache; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_r_ready; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_axi_r_valid; // @[lsu_bus_intf.scala 100:39] + wire [2:0] bus_buffer_io_lsu_axi_r_bits_id; // @[lsu_bus_intf.scala 100:39] + wire [63:0] bus_buffer_io_lsu_axi_r_bits_data; // @[lsu_bus_intf.scala 100:39] + wire [1:0] bus_buffer_io_lsu_axi_r_bits_resp; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_bus_clk_en; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_bus_clk_en_q; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_busreq_r; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_bus_buffer_pend_any; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_bus_buffer_full_any; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_lsu_bus_buffer_empty_any; // @[lsu_bus_intf.scala 100:39] + wire [3:0] bus_buffer_io_ld_byte_hit_buf_lo; // @[lsu_bus_intf.scala 100:39] + wire [3:0] bus_buffer_io_ld_byte_hit_buf_hi; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_ld_fwddata_buf_lo; // @[lsu_bus_intf.scala 100:39] + wire [31:0] bus_buffer_io_ld_fwddata_buf_hi; // @[lsu_bus_intf.scala 100:39] wire [3:0] _T_3 = io_lsu_pkt_m_bits_word ? 4'hf : 4'h0; // @[Mux.scala 27:72] wire [3:0] _T_4 = io_lsu_pkt_m_bits_half ? 4'h3 : 4'h0; // @[Mux.scala 27:72] wire [3:0] _T_5 = io_lsu_pkt_m_bits_by ? 4'h1 : 4'h0; // @[Mux.scala 27:72] wire [3:0] _T_6 = _T_3 | _T_4; // @[Mux.scala 27:72] wire [3:0] ldst_byteen_m = _T_6 | _T_5; // @[Mux.scala 27:72] - wire addr_match_dw_lo_r_m = io_lsu_addr_r[31:3] == io_lsu_addr_m[31:3]; // @[lsu_bus_intf.scala 155:51] - wire _T_17 = io_lsu_addr_r[2] ^ io_lsu_addr_m[2]; // @[lsu_bus_intf.scala 156:71] - wire _T_18 = ~_T_17; // @[lsu_bus_intf.scala 156:53] - wire addr_match_word_lo_r_m = addr_match_dw_lo_r_m & _T_18; // @[lsu_bus_intf.scala 156:51] - reg ldst_dual_r; // @[lsu_bus_intf.scala 201:33] - wire _T_20 = ~ldst_dual_r; // @[lsu_bus_intf.scala 157:48] - wire _T_21 = io_lsu_busreq_r & _T_20; // @[lsu_bus_intf.scala 157:46] - wire _T_22 = _T_21 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 157:61] - wire _T_23 = ~addr_match_word_lo_r_m; // @[lsu_bus_intf.scala 157:107] - wire _T_24 = io_lsu_pkt_m_bits_load | _T_23; // @[lsu_bus_intf.scala 157:105] - wire _T_29 = ~addr_match_dw_lo_r_m; // @[lsu_bus_intf.scala 158:107] - wire _T_30 = io_lsu_pkt_m_bits_load | _T_29; // @[lsu_bus_intf.scala 158:105] - wire [6:0] _GEN_0 = {{3'd0}, ldst_byteen_m}; // @[lsu_bus_intf.scala 160:49] - wire [6:0] _T_34 = _GEN_0 << io_lsu_addr_m[1:0]; // @[lsu_bus_intf.scala 160:49] - reg [3:0] ldst_byteen_r; // @[lsu_bus_intf.scala 203:33] - wire [6:0] _GEN_1 = {{3'd0}, ldst_byteen_r}; // @[lsu_bus_intf.scala 161:49] - wire [6:0] _T_37 = _GEN_1 << io_lsu_addr_r[1:0]; // @[lsu_bus_intf.scala 161:49] + wire addr_match_dw_lo_r_m = io_lsu_addr_r[31:3] == io_lsu_addr_m[31:3]; // @[lsu_bus_intf.scala 154:51] + wire _T_17 = io_lsu_addr_r[2] ^ io_lsu_addr_m[2]; // @[lsu_bus_intf.scala 155:71] + wire _T_18 = ~_T_17; // @[lsu_bus_intf.scala 155:53] + wire addr_match_word_lo_r_m = addr_match_dw_lo_r_m & _T_18; // @[lsu_bus_intf.scala 155:51] + reg ldst_dual_r; // @[lsu_bus_intf.scala 200:33] + wire _T_20 = ~ldst_dual_r; // @[lsu_bus_intf.scala 156:48] + wire _T_21 = io_lsu_busreq_r & _T_20; // @[lsu_bus_intf.scala 156:46] + wire _T_22 = _T_21 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 156:61] + wire _T_23 = ~addr_match_word_lo_r_m; // @[lsu_bus_intf.scala 156:107] + wire _T_24 = io_lsu_pkt_m_bits_load | _T_23; // @[lsu_bus_intf.scala 156:105] + wire _T_29 = ~addr_match_dw_lo_r_m; // @[lsu_bus_intf.scala 157:107] + wire _T_30 = io_lsu_pkt_m_bits_load | _T_29; // @[lsu_bus_intf.scala 157:105] + wire [6:0] _GEN_0 = {{3'd0}, ldst_byteen_m}; // @[lsu_bus_intf.scala 159:49] + wire [6:0] _T_34 = _GEN_0 << io_lsu_addr_m[1:0]; // @[lsu_bus_intf.scala 159:49] + reg [3:0] ldst_byteen_r; // @[lsu_bus_intf.scala 202:33] + wire [6:0] _GEN_1 = {{3'd0}, ldst_byteen_r}; // @[lsu_bus_intf.scala 160:49] + wire [6:0] _T_37 = _GEN_1 << io_lsu_addr_r[1:0]; // @[lsu_bus_intf.scala 160:49] wire [4:0] _T_40 = {io_lsu_addr_r[1:0],3'h0}; // @[Cat.scala 29:58] - wire [62:0] _GEN_2 = {{31'd0}, io_store_data_r}; // @[lsu_bus_intf.scala 162:52] - wire [62:0] _T_41 = _GEN_2 << _T_40; // @[lsu_bus_intf.scala 162:52] - wire [7:0] ldst_byteen_ext_m = {{1'd0}, _T_34}; // @[lsu_bus_intf.scala 160:27] - wire [3:0] ldst_byteen_hi_m = ldst_byteen_ext_m[7:4]; // @[lsu_bus_intf.scala 163:47] - wire [3:0] ldst_byteen_lo_m = ldst_byteen_ext_m[3:0]; // @[lsu_bus_intf.scala 164:47] - wire [7:0] ldst_byteen_ext_r = {{1'd0}, _T_37}; // @[lsu_bus_intf.scala 161:27] - wire [3:0] ldst_byteen_hi_r = ldst_byteen_ext_r[7:4]; // @[lsu_bus_intf.scala 165:47] - wire [3:0] ldst_byteen_lo_r = ldst_byteen_ext_r[3:0]; // @[lsu_bus_intf.scala 166:47] - wire [63:0] store_data_ext_r = {{1'd0}, _T_41}; // @[lsu_bus_intf.scala 162:27] - wire [31:0] store_data_hi_r = store_data_ext_r[63:32]; // @[lsu_bus_intf.scala 168:46] - wire [31:0] store_data_lo_r = store_data_ext_r[31:0]; // @[lsu_bus_intf.scala 169:46] - wire _T_50 = io_lsu_addr_m[31:2] == io_lsu_addr_r[31:2]; // @[lsu_bus_intf.scala 170:51] - wire _T_51 = _T_50 & io_lsu_pkt_r_valid; // @[lsu_bus_intf.scala 170:76] - wire _T_52 = _T_51 & io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 170:97] - wire ld_addr_rhit_lo_lo = _T_52 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 170:123] - wire _T_56 = io_end_addr_m[31:2] == io_lsu_addr_r[31:2]; // @[lsu_bus_intf.scala 171:51] - wire _T_57 = _T_56 & io_lsu_pkt_r_valid; // @[lsu_bus_intf.scala 171:76] - wire _T_58 = _T_57 & io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 171:97] - wire ld_addr_rhit_lo_hi = _T_58 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 171:123] - wire _T_62 = io_lsu_addr_m[31:2] == io_end_addr_r[31:2]; // @[lsu_bus_intf.scala 172:51] - wire _T_63 = _T_62 & io_lsu_pkt_r_valid; // @[lsu_bus_intf.scala 172:76] - wire _T_64 = _T_63 & io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 172:97] - wire ld_addr_rhit_hi_lo = _T_64 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 172:123] - wire _T_68 = io_end_addr_m[31:2] == io_end_addr_r[31:2]; // @[lsu_bus_intf.scala 173:51] - wire _T_69 = _T_68 & io_lsu_pkt_r_valid; // @[lsu_bus_intf.scala 173:76] - wire _T_70 = _T_69 & io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 173:97] - wire ld_addr_rhit_hi_hi = _T_70 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 173:123] - wire _T_73 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[0]; // @[lsu_bus_intf.scala 175:70] - wire _T_75 = _T_73 & ldst_byteen_lo_m[0]; // @[lsu_bus_intf.scala 175:92] - wire _T_77 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[1]; // @[lsu_bus_intf.scala 175:70] - wire _T_79 = _T_77 & ldst_byteen_lo_m[1]; // @[lsu_bus_intf.scala 175:92] - wire _T_81 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[2]; // @[lsu_bus_intf.scala 175:70] - wire _T_83 = _T_81 & ldst_byteen_lo_m[2]; // @[lsu_bus_intf.scala 175:92] - wire _T_85 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[3]; // @[lsu_bus_intf.scala 175:70] - wire _T_87 = _T_85 & ldst_byteen_lo_m[3]; // @[lsu_bus_intf.scala 175:92] + wire [62:0] _GEN_2 = {{31'd0}, io_store_data_r}; // @[lsu_bus_intf.scala 161:52] + wire [62:0] _T_41 = _GEN_2 << _T_40; // @[lsu_bus_intf.scala 161:52] + wire [7:0] ldst_byteen_ext_m = {{1'd0}, _T_34}; // @[lsu_bus_intf.scala 159:27] + wire [3:0] ldst_byteen_hi_m = ldst_byteen_ext_m[7:4]; // @[lsu_bus_intf.scala 162:47] + wire [3:0] ldst_byteen_lo_m = ldst_byteen_ext_m[3:0]; // @[lsu_bus_intf.scala 163:47] + wire [7:0] ldst_byteen_ext_r = {{1'd0}, _T_37}; // @[lsu_bus_intf.scala 160:27] + wire [3:0] ldst_byteen_hi_r = ldst_byteen_ext_r[7:4]; // @[lsu_bus_intf.scala 164:47] + wire [3:0] ldst_byteen_lo_r = ldst_byteen_ext_r[3:0]; // @[lsu_bus_intf.scala 165:47] + wire [63:0] store_data_ext_r = {{1'd0}, _T_41}; // @[lsu_bus_intf.scala 161:27] + wire [31:0] store_data_hi_r = store_data_ext_r[63:32]; // @[lsu_bus_intf.scala 167:46] + wire [31:0] store_data_lo_r = store_data_ext_r[31:0]; // @[lsu_bus_intf.scala 168:46] + wire _T_50 = io_lsu_addr_m[31:2] == io_lsu_addr_r[31:2]; // @[lsu_bus_intf.scala 169:51] + wire _T_51 = _T_50 & io_lsu_pkt_r_valid; // @[lsu_bus_intf.scala 169:76] + wire _T_52 = _T_51 & io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 169:97] + wire ld_addr_rhit_lo_lo = _T_52 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 169:123] + wire _T_56 = io_end_addr_m[31:2] == io_lsu_addr_r[31:2]; // @[lsu_bus_intf.scala 170:51] + wire _T_57 = _T_56 & io_lsu_pkt_r_valid; // @[lsu_bus_intf.scala 170:76] + wire _T_58 = _T_57 & io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 170:97] + wire ld_addr_rhit_lo_hi = _T_58 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 170:123] + wire _T_62 = io_lsu_addr_m[31:2] == io_end_addr_r[31:2]; // @[lsu_bus_intf.scala 171:51] + wire _T_63 = _T_62 & io_lsu_pkt_r_valid; // @[lsu_bus_intf.scala 171:76] + wire _T_64 = _T_63 & io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 171:97] + wire ld_addr_rhit_hi_lo = _T_64 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 171:123] + wire _T_68 = io_end_addr_m[31:2] == io_end_addr_r[31:2]; // @[lsu_bus_intf.scala 172:51] + wire _T_69 = _T_68 & io_lsu_pkt_r_valid; // @[lsu_bus_intf.scala 172:76] + wire _T_70 = _T_69 & io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 172:97] + wire ld_addr_rhit_hi_hi = _T_70 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 172:123] + wire _T_73 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[0]; // @[lsu_bus_intf.scala 174:70] + wire _T_75 = _T_73 & ldst_byteen_lo_m[0]; // @[lsu_bus_intf.scala 174:92] + wire _T_77 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[1]; // @[lsu_bus_intf.scala 174:70] + wire _T_79 = _T_77 & ldst_byteen_lo_m[1]; // @[lsu_bus_intf.scala 174:92] + wire _T_81 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[2]; // @[lsu_bus_intf.scala 174:70] + wire _T_83 = _T_81 & ldst_byteen_lo_m[2]; // @[lsu_bus_intf.scala 174:92] + wire _T_85 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[3]; // @[lsu_bus_intf.scala 174:70] + wire _T_87 = _T_85 & ldst_byteen_lo_m[3]; // @[lsu_bus_intf.scala 174:92] wire [3:0] ld_byte_rhit_lo_lo = {_T_87,_T_83,_T_79,_T_75}; // @[Cat.scala 29:58] - wire _T_92 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[0]; // @[lsu_bus_intf.scala 176:70] - wire _T_94 = _T_92 & ldst_byteen_hi_m[0]; // @[lsu_bus_intf.scala 176:92] - wire _T_96 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[1]; // @[lsu_bus_intf.scala 176:70] - wire _T_98 = _T_96 & ldst_byteen_hi_m[1]; // @[lsu_bus_intf.scala 176:92] - wire _T_100 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[2]; // @[lsu_bus_intf.scala 176:70] - wire _T_102 = _T_100 & ldst_byteen_hi_m[2]; // @[lsu_bus_intf.scala 176:92] - wire _T_104 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[3]; // @[lsu_bus_intf.scala 176:70] - wire _T_106 = _T_104 & ldst_byteen_hi_m[3]; // @[lsu_bus_intf.scala 176:92] + wire _T_92 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[0]; // @[lsu_bus_intf.scala 175:70] + wire _T_94 = _T_92 & ldst_byteen_hi_m[0]; // @[lsu_bus_intf.scala 175:92] + wire _T_96 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[1]; // @[lsu_bus_intf.scala 175:70] + wire _T_98 = _T_96 & ldst_byteen_hi_m[1]; // @[lsu_bus_intf.scala 175:92] + wire _T_100 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[2]; // @[lsu_bus_intf.scala 175:70] + wire _T_102 = _T_100 & ldst_byteen_hi_m[2]; // @[lsu_bus_intf.scala 175:92] + wire _T_104 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[3]; // @[lsu_bus_intf.scala 175:70] + wire _T_106 = _T_104 & ldst_byteen_hi_m[3]; // @[lsu_bus_intf.scala 175:92] wire [3:0] ld_byte_rhit_lo_hi = {_T_106,_T_102,_T_98,_T_94}; // @[Cat.scala 29:58] - wire _T_111 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[0]; // @[lsu_bus_intf.scala 177:70] - wire _T_113 = _T_111 & ldst_byteen_lo_m[0]; // @[lsu_bus_intf.scala 177:92] - wire _T_115 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[1]; // @[lsu_bus_intf.scala 177:70] - wire _T_117 = _T_115 & ldst_byteen_lo_m[1]; // @[lsu_bus_intf.scala 177:92] - wire _T_119 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[2]; // @[lsu_bus_intf.scala 177:70] - wire _T_121 = _T_119 & ldst_byteen_lo_m[2]; // @[lsu_bus_intf.scala 177:92] - wire _T_123 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[3]; // @[lsu_bus_intf.scala 177:70] - wire _T_125 = _T_123 & ldst_byteen_lo_m[3]; // @[lsu_bus_intf.scala 177:92] + wire _T_111 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[0]; // @[lsu_bus_intf.scala 176:70] + wire _T_113 = _T_111 & ldst_byteen_lo_m[0]; // @[lsu_bus_intf.scala 176:92] + wire _T_115 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[1]; // @[lsu_bus_intf.scala 176:70] + wire _T_117 = _T_115 & ldst_byteen_lo_m[1]; // @[lsu_bus_intf.scala 176:92] + wire _T_119 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[2]; // @[lsu_bus_intf.scala 176:70] + wire _T_121 = _T_119 & ldst_byteen_lo_m[2]; // @[lsu_bus_intf.scala 176:92] + wire _T_123 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[3]; // @[lsu_bus_intf.scala 176:70] + wire _T_125 = _T_123 & ldst_byteen_lo_m[3]; // @[lsu_bus_intf.scala 176:92] wire [3:0] ld_byte_rhit_hi_lo = {_T_125,_T_121,_T_117,_T_113}; // @[Cat.scala 29:58] - wire _T_130 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[0]; // @[lsu_bus_intf.scala 178:70] - wire _T_132 = _T_130 & ldst_byteen_hi_m[0]; // @[lsu_bus_intf.scala 178:92] - wire _T_134 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[1]; // @[lsu_bus_intf.scala 178:70] - wire _T_136 = _T_134 & ldst_byteen_hi_m[1]; // @[lsu_bus_intf.scala 178:92] - wire _T_138 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[2]; // @[lsu_bus_intf.scala 178:70] - wire _T_140 = _T_138 & ldst_byteen_hi_m[2]; // @[lsu_bus_intf.scala 178:92] - wire _T_142 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[3]; // @[lsu_bus_intf.scala 178:70] - wire _T_144 = _T_142 & ldst_byteen_hi_m[3]; // @[lsu_bus_intf.scala 178:92] + wire _T_130 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[0]; // @[lsu_bus_intf.scala 177:70] + wire _T_132 = _T_130 & ldst_byteen_hi_m[0]; // @[lsu_bus_intf.scala 177:92] + wire _T_134 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[1]; // @[lsu_bus_intf.scala 177:70] + wire _T_136 = _T_134 & ldst_byteen_hi_m[1]; // @[lsu_bus_intf.scala 177:92] + wire _T_138 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[2]; // @[lsu_bus_intf.scala 177:70] + wire _T_140 = _T_138 & ldst_byteen_hi_m[2]; // @[lsu_bus_intf.scala 177:92] + wire _T_142 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[3]; // @[lsu_bus_intf.scala 177:70] + wire _T_144 = _T_142 & ldst_byteen_hi_m[3]; // @[lsu_bus_intf.scala 177:92] wire [3:0] ld_byte_rhit_hi_hi = {_T_144,_T_140,_T_136,_T_132}; // @[Cat.scala 29:58] - wire _T_150 = ld_byte_rhit_lo_lo[0] | ld_byte_rhit_hi_lo[0]; // @[lsu_bus_intf.scala 180:73] - wire [3:0] ld_byte_hit_buf_lo = bus_buffer_io_ld_byte_hit_buf_lo; // @[lsu_bus_intf.scala 138:38] - wire _T_152 = _T_150 | ld_byte_hit_buf_lo[0]; // @[lsu_bus_intf.scala 180:97] - wire _T_155 = ld_byte_rhit_lo_lo[1] | ld_byte_rhit_hi_lo[1]; // @[lsu_bus_intf.scala 180:73] - wire _T_157 = _T_155 | ld_byte_hit_buf_lo[1]; // @[lsu_bus_intf.scala 180:97] - wire _T_160 = ld_byte_rhit_lo_lo[2] | ld_byte_rhit_hi_lo[2]; // @[lsu_bus_intf.scala 180:73] - wire _T_162 = _T_160 | ld_byte_hit_buf_lo[2]; // @[lsu_bus_intf.scala 180:97] - wire _T_165 = ld_byte_rhit_lo_lo[3] | ld_byte_rhit_hi_lo[3]; // @[lsu_bus_intf.scala 180:73] - wire _T_167 = _T_165 | ld_byte_hit_buf_lo[3]; // @[lsu_bus_intf.scala 180:97] + wire _T_150 = ld_byte_rhit_lo_lo[0] | ld_byte_rhit_hi_lo[0]; // @[lsu_bus_intf.scala 179:73] + wire [3:0] ld_byte_hit_buf_lo = bus_buffer_io_ld_byte_hit_buf_lo; // @[lsu_bus_intf.scala 137:38] + wire _T_152 = _T_150 | ld_byte_hit_buf_lo[0]; // @[lsu_bus_intf.scala 179:97] + wire _T_155 = ld_byte_rhit_lo_lo[1] | ld_byte_rhit_hi_lo[1]; // @[lsu_bus_intf.scala 179:73] + wire _T_157 = _T_155 | ld_byte_hit_buf_lo[1]; // @[lsu_bus_intf.scala 179:97] + wire _T_160 = ld_byte_rhit_lo_lo[2] | ld_byte_rhit_hi_lo[2]; // @[lsu_bus_intf.scala 179:73] + wire _T_162 = _T_160 | ld_byte_hit_buf_lo[2]; // @[lsu_bus_intf.scala 179:97] + wire _T_165 = ld_byte_rhit_lo_lo[3] | ld_byte_rhit_hi_lo[3]; // @[lsu_bus_intf.scala 179:73] + wire _T_167 = _T_165 | ld_byte_hit_buf_lo[3]; // @[lsu_bus_intf.scala 179:97] wire [3:0] ld_byte_hit_lo = {_T_167,_T_162,_T_157,_T_152}; // @[Cat.scala 29:58] - wire _T_173 = ld_byte_rhit_lo_hi[0] | ld_byte_rhit_hi_hi[0]; // @[lsu_bus_intf.scala 181:73] - wire [3:0] ld_byte_hit_buf_hi = bus_buffer_io_ld_byte_hit_buf_hi; // @[lsu_bus_intf.scala 139:38] - wire _T_175 = _T_173 | ld_byte_hit_buf_hi[0]; // @[lsu_bus_intf.scala 181:97] - wire _T_178 = ld_byte_rhit_lo_hi[1] | ld_byte_rhit_hi_hi[1]; // @[lsu_bus_intf.scala 181:73] - wire _T_180 = _T_178 | ld_byte_hit_buf_hi[1]; // @[lsu_bus_intf.scala 181:97] - wire _T_183 = ld_byte_rhit_lo_hi[2] | ld_byte_rhit_hi_hi[2]; // @[lsu_bus_intf.scala 181:73] - wire _T_185 = _T_183 | ld_byte_hit_buf_hi[2]; // @[lsu_bus_intf.scala 181:97] - wire _T_188 = ld_byte_rhit_lo_hi[3] | ld_byte_rhit_hi_hi[3]; // @[lsu_bus_intf.scala 181:73] - wire _T_190 = _T_188 | ld_byte_hit_buf_hi[3]; // @[lsu_bus_intf.scala 181:97] + wire _T_173 = ld_byte_rhit_lo_hi[0] | ld_byte_rhit_hi_hi[0]; // @[lsu_bus_intf.scala 180:73] + wire [3:0] ld_byte_hit_buf_hi = bus_buffer_io_ld_byte_hit_buf_hi; // @[lsu_bus_intf.scala 138:38] + wire _T_175 = _T_173 | ld_byte_hit_buf_hi[0]; // @[lsu_bus_intf.scala 180:97] + wire _T_178 = ld_byte_rhit_lo_hi[1] | ld_byte_rhit_hi_hi[1]; // @[lsu_bus_intf.scala 180:73] + wire _T_180 = _T_178 | ld_byte_hit_buf_hi[1]; // @[lsu_bus_intf.scala 180:97] + wire _T_183 = ld_byte_rhit_lo_hi[2] | ld_byte_rhit_hi_hi[2]; // @[lsu_bus_intf.scala 180:73] + wire _T_185 = _T_183 | ld_byte_hit_buf_hi[2]; // @[lsu_bus_intf.scala 180:97] + wire _T_188 = ld_byte_rhit_lo_hi[3] | ld_byte_rhit_hi_hi[3]; // @[lsu_bus_intf.scala 180:73] + wire _T_190 = _T_188 | ld_byte_hit_buf_hi[3]; // @[lsu_bus_intf.scala 180:97] wire [3:0] ld_byte_hit_hi = {_T_190,_T_185,_T_180,_T_175}; // @[Cat.scala 29:58] wire [3:0] ld_byte_rhit_lo = {_T_165,_T_160,_T_155,_T_150}; // @[Cat.scala 29:58] wire [3:0] ld_byte_rhit_hi = {_T_188,_T_183,_T_178,_T_173}; // @[Cat.scala 29:58] @@ -72852,54 +73021,54 @@ module lsu_bus_intf( wire [7:0] _T_288 = ld_byte_rhit_hi_hi[3] ? store_data_hi_r[31:24] : 8'h0; // @[Mux.scala 27:72] wire [7:0] _T_289 = _T_287 | _T_288; // @[Mux.scala 27:72] wire [31:0] ld_fwddata_rpipe_hi = {_T_289,_T_281,_T_273,_T_265}; // @[Cat.scala 29:58] - wire [31:0] ld_fwddata_buf_lo = bus_buffer_io_ld_fwddata_buf_lo; // @[lsu_bus_intf.scala 140:38] - wire [7:0] _T_297 = ld_byte_rhit_lo[0] ? ld_fwddata_rpipe_lo[7:0] : ld_fwddata_buf_lo[7:0]; // @[lsu_bus_intf.scala 186:54] - wire [7:0] _T_301 = ld_byte_rhit_lo[1] ? ld_fwddata_rpipe_lo[15:8] : ld_fwddata_buf_lo[15:8]; // @[lsu_bus_intf.scala 186:54] - wire [7:0] _T_305 = ld_byte_rhit_lo[2] ? ld_fwddata_rpipe_lo[23:16] : ld_fwddata_buf_lo[23:16]; // @[lsu_bus_intf.scala 186:54] - wire [7:0] _T_309 = ld_byte_rhit_lo[3] ? ld_fwddata_rpipe_lo[31:24] : ld_fwddata_buf_lo[31:24]; // @[lsu_bus_intf.scala 186:54] + wire [31:0] ld_fwddata_buf_lo = bus_buffer_io_ld_fwddata_buf_lo; // @[lsu_bus_intf.scala 139:38] + wire [7:0] _T_297 = ld_byte_rhit_lo[0] ? ld_fwddata_rpipe_lo[7:0] : ld_fwddata_buf_lo[7:0]; // @[lsu_bus_intf.scala 185:54] + wire [7:0] _T_301 = ld_byte_rhit_lo[1] ? ld_fwddata_rpipe_lo[15:8] : ld_fwddata_buf_lo[15:8]; // @[lsu_bus_intf.scala 185:54] + wire [7:0] _T_305 = ld_byte_rhit_lo[2] ? ld_fwddata_rpipe_lo[23:16] : ld_fwddata_buf_lo[23:16]; // @[lsu_bus_intf.scala 185:54] + wire [7:0] _T_309 = ld_byte_rhit_lo[3] ? ld_fwddata_rpipe_lo[31:24] : ld_fwddata_buf_lo[31:24]; // @[lsu_bus_intf.scala 185:54] wire [31:0] _T_312 = {_T_309,_T_305,_T_301,_T_297}; // @[Cat.scala 29:58] - wire [31:0] ld_fwddata_buf_hi = bus_buffer_io_ld_fwddata_buf_hi; // @[lsu_bus_intf.scala 141:38] - wire [7:0] _T_316 = ld_byte_rhit_hi[0] ? ld_fwddata_rpipe_hi[7:0] : ld_fwddata_buf_hi[7:0]; // @[lsu_bus_intf.scala 187:54] - wire [7:0] _T_320 = ld_byte_rhit_hi[1] ? ld_fwddata_rpipe_hi[15:8] : ld_fwddata_buf_hi[15:8]; // @[lsu_bus_intf.scala 187:54] - wire [7:0] _T_324 = ld_byte_rhit_hi[2] ? ld_fwddata_rpipe_hi[23:16] : ld_fwddata_buf_hi[23:16]; // @[lsu_bus_intf.scala 187:54] - wire [7:0] _T_328 = ld_byte_rhit_hi[3] ? ld_fwddata_rpipe_hi[31:24] : ld_fwddata_buf_hi[31:24]; // @[lsu_bus_intf.scala 187:54] + wire [31:0] ld_fwddata_buf_hi = bus_buffer_io_ld_fwddata_buf_hi; // @[lsu_bus_intf.scala 140:38] + wire [7:0] _T_316 = ld_byte_rhit_hi[0] ? ld_fwddata_rpipe_hi[7:0] : ld_fwddata_buf_hi[7:0]; // @[lsu_bus_intf.scala 186:54] + wire [7:0] _T_320 = ld_byte_rhit_hi[1] ? ld_fwddata_rpipe_hi[15:8] : ld_fwddata_buf_hi[15:8]; // @[lsu_bus_intf.scala 186:54] + wire [7:0] _T_324 = ld_byte_rhit_hi[2] ? ld_fwddata_rpipe_hi[23:16] : ld_fwddata_buf_hi[23:16]; // @[lsu_bus_intf.scala 186:54] + wire [7:0] _T_328 = ld_byte_rhit_hi[3] ? ld_fwddata_rpipe_hi[31:24] : ld_fwddata_buf_hi[31:24]; // @[lsu_bus_intf.scala 186:54] wire [31:0] _T_331 = {_T_328,_T_324,_T_320,_T_316}; // @[Cat.scala 29:58] - wire _T_334 = ~ldst_byteen_lo_m[0]; // @[lsu_bus_intf.scala 188:72] - wire _T_335 = ld_byte_hit_lo[0] | _T_334; // @[lsu_bus_intf.scala 188:70] - wire _T_338 = ~ldst_byteen_lo_m[1]; // @[lsu_bus_intf.scala 188:72] - wire _T_339 = ld_byte_hit_lo[1] | _T_338; // @[lsu_bus_intf.scala 188:70] - wire _T_342 = ~ldst_byteen_lo_m[2]; // @[lsu_bus_intf.scala 188:72] - wire _T_343 = ld_byte_hit_lo[2] | _T_342; // @[lsu_bus_intf.scala 188:70] - wire _T_346 = ~ldst_byteen_lo_m[3]; // @[lsu_bus_intf.scala 188:72] - wire _T_347 = ld_byte_hit_lo[3] | _T_346; // @[lsu_bus_intf.scala 188:70] - wire _T_348 = _T_335 & _T_339; // @[lsu_bus_intf.scala 188:111] - wire _T_349 = _T_348 & _T_343; // @[lsu_bus_intf.scala 188:111] - wire ld_full_hit_lo_m = _T_349 & _T_347; // @[lsu_bus_intf.scala 188:111] - wire _T_353 = ~ldst_byteen_hi_m[0]; // @[lsu_bus_intf.scala 189:72] - wire _T_354 = ld_byte_hit_hi[0] | _T_353; // @[lsu_bus_intf.scala 189:70] - wire _T_357 = ~ldst_byteen_hi_m[1]; // @[lsu_bus_intf.scala 189:72] - wire _T_358 = ld_byte_hit_hi[1] | _T_357; // @[lsu_bus_intf.scala 189:70] - wire _T_361 = ~ldst_byteen_hi_m[2]; // @[lsu_bus_intf.scala 189:72] - wire _T_362 = ld_byte_hit_hi[2] | _T_361; // @[lsu_bus_intf.scala 189:70] - wire _T_365 = ~ldst_byteen_hi_m[3]; // @[lsu_bus_intf.scala 189:72] - wire _T_366 = ld_byte_hit_hi[3] | _T_365; // @[lsu_bus_intf.scala 189:70] - wire _T_367 = _T_354 & _T_358; // @[lsu_bus_intf.scala 189:111] - wire _T_368 = _T_367 & _T_362; // @[lsu_bus_intf.scala 189:111] - wire ld_full_hit_hi_m = _T_368 & _T_366; // @[lsu_bus_intf.scala 189:111] - wire _T_370 = ld_full_hit_lo_m & ld_full_hit_hi_m; // @[lsu_bus_intf.scala 190:47] - wire _T_371 = _T_370 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 190:66] - wire _T_372 = _T_371 & io_lsu_pkt_m_bits_load; // @[lsu_bus_intf.scala 190:84] - wire _T_373 = ~io_is_sideeffects_m; // @[lsu_bus_intf.scala 190:111] - wire [63:0] ld_fwddata_hi = {{32'd0}, _T_331}; // @[lsu_bus_intf.scala 187:27] - wire [63:0] ld_fwddata_lo = {{32'd0}, _T_312}; // @[lsu_bus_intf.scala 186:27] + wire _T_334 = ~ldst_byteen_lo_m[0]; // @[lsu_bus_intf.scala 187:72] + wire _T_335 = ld_byte_hit_lo[0] | _T_334; // @[lsu_bus_intf.scala 187:70] + wire _T_338 = ~ldst_byteen_lo_m[1]; // @[lsu_bus_intf.scala 187:72] + wire _T_339 = ld_byte_hit_lo[1] | _T_338; // @[lsu_bus_intf.scala 187:70] + wire _T_342 = ~ldst_byteen_lo_m[2]; // @[lsu_bus_intf.scala 187:72] + wire _T_343 = ld_byte_hit_lo[2] | _T_342; // @[lsu_bus_intf.scala 187:70] + wire _T_346 = ~ldst_byteen_lo_m[3]; // @[lsu_bus_intf.scala 187:72] + wire _T_347 = ld_byte_hit_lo[3] | _T_346; // @[lsu_bus_intf.scala 187:70] + wire _T_348 = _T_335 & _T_339; // @[lsu_bus_intf.scala 187:111] + wire _T_349 = _T_348 & _T_343; // @[lsu_bus_intf.scala 187:111] + wire ld_full_hit_lo_m = _T_349 & _T_347; // @[lsu_bus_intf.scala 187:111] + wire _T_353 = ~ldst_byteen_hi_m[0]; // @[lsu_bus_intf.scala 188:72] + wire _T_354 = ld_byte_hit_hi[0] | _T_353; // @[lsu_bus_intf.scala 188:70] + wire _T_357 = ~ldst_byteen_hi_m[1]; // @[lsu_bus_intf.scala 188:72] + wire _T_358 = ld_byte_hit_hi[1] | _T_357; // @[lsu_bus_intf.scala 188:70] + wire _T_361 = ~ldst_byteen_hi_m[2]; // @[lsu_bus_intf.scala 188:72] + wire _T_362 = ld_byte_hit_hi[2] | _T_361; // @[lsu_bus_intf.scala 188:70] + wire _T_365 = ~ldst_byteen_hi_m[3]; // @[lsu_bus_intf.scala 188:72] + wire _T_366 = ld_byte_hit_hi[3] | _T_365; // @[lsu_bus_intf.scala 188:70] + wire _T_367 = _T_354 & _T_358; // @[lsu_bus_intf.scala 188:111] + wire _T_368 = _T_367 & _T_362; // @[lsu_bus_intf.scala 188:111] + wire ld_full_hit_hi_m = _T_368 & _T_366; // @[lsu_bus_intf.scala 188:111] + wire _T_370 = ld_full_hit_lo_m & ld_full_hit_hi_m; // @[lsu_bus_intf.scala 189:47] + wire _T_371 = _T_370 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 189:66] + wire _T_372 = _T_371 & io_lsu_pkt_m_bits_load; // @[lsu_bus_intf.scala 189:84] + wire _T_373 = ~io_is_sideeffects_m; // @[lsu_bus_intf.scala 189:111] + wire [63:0] ld_fwddata_hi = {{32'd0}, _T_331}; // @[lsu_bus_intf.scala 186:27] + wire [63:0] ld_fwddata_lo = {{32'd0}, _T_312}; // @[lsu_bus_intf.scala 185:27] wire [63:0] _T_377 = {ld_fwddata_hi[31:0],ld_fwddata_lo[31:0]}; // @[Cat.scala 29:58] - wire [3:0] _GEN_3 = {{2'd0}, io_lsu_addr_m[1:0]}; // @[lsu_bus_intf.scala 191:83] - wire [5:0] _T_379 = 4'h8 * _GEN_3; // @[lsu_bus_intf.scala 191:83] - wire [63:0] ld_fwddata_m = _T_377 >> _T_379; // @[lsu_bus_intf.scala 191:76] - reg lsu_bus_clk_en_q; // @[lsu_bus_intf.scala 195:32] - reg ldst_dual_m; // @[lsu_bus_intf.scala 198:27] - reg is_sideeffects_r; // @[lsu_bus_intf.scala 202:33] - lsu_bus_buffer bus_buffer ( // @[lsu_bus_intf.scala 101:39] + wire [3:0] _GEN_3 = {{2'd0}, io_lsu_addr_m[1:0]}; // @[lsu_bus_intf.scala 190:83] + wire [5:0] _T_379 = 4'h8 * _GEN_3; // @[lsu_bus_intf.scala 190:83] + wire [63:0] ld_fwddata_m = _T_377 >> _T_379; // @[lsu_bus_intf.scala 190:76] + reg lsu_bus_clk_en_q; // @[lsu_bus_intf.scala 194:32] + reg ldst_dual_m; // @[lsu_bus_intf.scala 197:27] + reg is_sideeffects_r; // @[lsu_bus_intf.scala 201:33] + lsu_bus_buffer bus_buffer ( // @[lsu_bus_intf.scala 100:39] .clock(bus_buffer_clock), .reset(bus_buffer_reset), .io_scan_mode(bus_buffer_io_scan_mode), @@ -72908,6 +73077,7 @@ module lsu_bus_intf( .io_tlu_busbuff_lsu_pmu_bus_error(bus_buffer_io_tlu_busbuff_lsu_pmu_bus_error), .io_tlu_busbuff_lsu_pmu_bus_busy(bus_buffer_io_tlu_busbuff_lsu_pmu_bus_busy), .io_tlu_busbuff_dec_tlu_external_ldfwd_disable(bus_buffer_io_tlu_busbuff_dec_tlu_external_ldfwd_disable), + .io_tlu_busbuff_dec_tlu_wb_coalescing_disable(bus_buffer_io_tlu_busbuff_dec_tlu_wb_coalescing_disable), .io_tlu_busbuff_dec_tlu_sideeffect_posted_disable(bus_buffer_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable), .io_tlu_busbuff_lsu_imprecise_error_load_any(bus_buffer_io_tlu_busbuff_lsu_imprecise_error_load_any), .io_tlu_busbuff_lsu_imprecise_error_store_any(bus_buffer_io_tlu_busbuff_lsu_imprecise_error_store_any), @@ -72957,7 +73127,9 @@ module lsu_bus_intf( .io_lsu_axi_aw_valid(bus_buffer_io_lsu_axi_aw_valid), .io_lsu_axi_aw_bits_id(bus_buffer_io_lsu_axi_aw_bits_id), .io_lsu_axi_aw_bits_addr(bus_buffer_io_lsu_axi_aw_bits_addr), + .io_lsu_axi_aw_bits_region(bus_buffer_io_lsu_axi_aw_bits_region), .io_lsu_axi_aw_bits_size(bus_buffer_io_lsu_axi_aw_bits_size), + .io_lsu_axi_aw_bits_cache(bus_buffer_io_lsu_axi_aw_bits_cache), .io_lsu_axi_w_ready(bus_buffer_io_lsu_axi_w_ready), .io_lsu_axi_w_valid(bus_buffer_io_lsu_axi_w_valid), .io_lsu_axi_w_bits_data(bus_buffer_io_lsu_axi_w_bits_data), @@ -72969,7 +73141,9 @@ module lsu_bus_intf( .io_lsu_axi_ar_valid(bus_buffer_io_lsu_axi_ar_valid), .io_lsu_axi_ar_bits_id(bus_buffer_io_lsu_axi_ar_bits_id), .io_lsu_axi_ar_bits_addr(bus_buffer_io_lsu_axi_ar_bits_addr), + .io_lsu_axi_ar_bits_region(bus_buffer_io_lsu_axi_ar_bits_region), .io_lsu_axi_ar_bits_size(bus_buffer_io_lsu_axi_ar_bits_size), + .io_lsu_axi_ar_bits_cache(bus_buffer_io_lsu_axi_ar_bits_cache), .io_lsu_axi_r_ready(bus_buffer_io_lsu_axi_r_ready), .io_lsu_axi_r_valid(bus_buffer_io_lsu_axi_r_valid), .io_lsu_axi_r_bits_id(bus_buffer_io_lsu_axi_r_bits_id), @@ -72986,86 +73160,91 @@ module lsu_bus_intf( .io_ld_fwddata_buf_lo(bus_buffer_io_ld_fwddata_buf_lo), .io_ld_fwddata_buf_hi(bus_buffer_io_ld_fwddata_buf_hi) ); - assign io_tlu_busbuff_lsu_pmu_bus_trxn = bus_buffer_io_tlu_busbuff_lsu_pmu_bus_trxn; // @[lsu_bus_intf.scala 104:18] - assign io_tlu_busbuff_lsu_pmu_bus_misaligned = bus_buffer_io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[lsu_bus_intf.scala 104:18] - assign io_tlu_busbuff_lsu_pmu_bus_error = bus_buffer_io_tlu_busbuff_lsu_pmu_bus_error; // @[lsu_bus_intf.scala 104:18] - assign io_tlu_busbuff_lsu_pmu_bus_busy = bus_buffer_io_tlu_busbuff_lsu_pmu_bus_busy; // @[lsu_bus_intf.scala 104:18] - assign io_tlu_busbuff_lsu_imprecise_error_load_any = bus_buffer_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[lsu_bus_intf.scala 104:18] - assign io_tlu_busbuff_lsu_imprecise_error_store_any = bus_buffer_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_intf.scala 104:18] - assign io_tlu_busbuff_lsu_imprecise_error_addr_any = bus_buffer_io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[lsu_bus_intf.scala 104:18] - assign io_axi_aw_valid = bus_buffer_io_lsu_axi_aw_valid; // @[lsu_bus_intf.scala 130:43] - assign io_axi_aw_bits_id = bus_buffer_io_lsu_axi_aw_bits_id; // @[lsu_bus_intf.scala 130:43] - assign io_axi_aw_bits_addr = bus_buffer_io_lsu_axi_aw_bits_addr; // @[lsu_bus_intf.scala 130:43] - assign io_axi_aw_bits_size = bus_buffer_io_lsu_axi_aw_bits_size; // @[lsu_bus_intf.scala 130:43] - assign io_axi_w_valid = bus_buffer_io_lsu_axi_w_valid; // @[lsu_bus_intf.scala 130:43] - assign io_axi_w_bits_data = bus_buffer_io_lsu_axi_w_bits_data; // @[lsu_bus_intf.scala 130:43] - assign io_axi_w_bits_strb = bus_buffer_io_lsu_axi_w_bits_strb; // @[lsu_bus_intf.scala 130:43] - assign io_axi_ar_valid = bus_buffer_io_lsu_axi_ar_valid; // @[lsu_bus_intf.scala 130:43] - assign io_axi_ar_bits_id = bus_buffer_io_lsu_axi_ar_bits_id; // @[lsu_bus_intf.scala 130:43] - assign io_axi_ar_bits_addr = bus_buffer_io_lsu_axi_ar_bits_addr; // @[lsu_bus_intf.scala 130:43] - assign io_axi_ar_bits_size = bus_buffer_io_lsu_axi_ar_bits_size; // @[lsu_bus_intf.scala 130:43] - assign io_lsu_busreq_r = bus_buffer_io_lsu_busreq_r; // @[lsu_bus_intf.scala 133:38] - assign io_lsu_bus_buffer_pend_any = bus_buffer_io_lsu_bus_buffer_pend_any; // @[lsu_bus_intf.scala 134:38] - assign io_lsu_bus_buffer_full_any = bus_buffer_io_lsu_bus_buffer_full_any; // @[lsu_bus_intf.scala 135:38] - assign io_lsu_bus_buffer_empty_any = bus_buffer_io_lsu_bus_buffer_empty_any; // @[lsu_bus_intf.scala 136:38] - assign io_bus_read_data_m = ld_fwddata_m[31:0]; // @[lsu_bus_intf.scala 192:27] - assign io_dctl_busbuff_lsu_nonblock_load_valid_m = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[lsu_bus_intf.scala 142:19] - assign io_dctl_busbuff_lsu_nonblock_load_tag_m = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_tag_m; // @[lsu_bus_intf.scala 142:19] - assign io_dctl_busbuff_lsu_nonblock_load_inv_r = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_inv_r; // @[lsu_bus_intf.scala 142:19] - assign io_dctl_busbuff_lsu_nonblock_load_inv_tag_r = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[lsu_bus_intf.scala 142:19] - assign io_dctl_busbuff_lsu_nonblock_load_data_valid = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_valid; // @[lsu_bus_intf.scala 142:19] - assign io_dctl_busbuff_lsu_nonblock_load_data_error = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_error; // @[lsu_bus_intf.scala 142:19] - assign io_dctl_busbuff_lsu_nonblock_load_data_tag = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_tag; // @[lsu_bus_intf.scala 142:19] - assign io_dctl_busbuff_lsu_nonblock_load_data = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data; // @[lsu_bus_intf.scala 142:19] + assign io_tlu_busbuff_lsu_pmu_bus_trxn = bus_buffer_io_tlu_busbuff_lsu_pmu_bus_trxn; // @[lsu_bus_intf.scala 103:18] + assign io_tlu_busbuff_lsu_pmu_bus_misaligned = bus_buffer_io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[lsu_bus_intf.scala 103:18] + assign io_tlu_busbuff_lsu_pmu_bus_error = bus_buffer_io_tlu_busbuff_lsu_pmu_bus_error; // @[lsu_bus_intf.scala 103:18] + assign io_tlu_busbuff_lsu_pmu_bus_busy = bus_buffer_io_tlu_busbuff_lsu_pmu_bus_busy; // @[lsu_bus_intf.scala 103:18] + assign io_tlu_busbuff_lsu_imprecise_error_load_any = bus_buffer_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[lsu_bus_intf.scala 103:18] + assign io_tlu_busbuff_lsu_imprecise_error_store_any = bus_buffer_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_intf.scala 103:18] + assign io_tlu_busbuff_lsu_imprecise_error_addr_any = bus_buffer_io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[lsu_bus_intf.scala 103:18] + assign io_axi_aw_valid = bus_buffer_io_lsu_axi_aw_valid; // @[lsu_bus_intf.scala 129:43] + assign io_axi_aw_bits_id = bus_buffer_io_lsu_axi_aw_bits_id; // @[lsu_bus_intf.scala 129:43] + assign io_axi_aw_bits_addr = bus_buffer_io_lsu_axi_aw_bits_addr; // @[lsu_bus_intf.scala 129:43] + assign io_axi_aw_bits_region = bus_buffer_io_lsu_axi_aw_bits_region; // @[lsu_bus_intf.scala 129:43] + assign io_axi_aw_bits_size = bus_buffer_io_lsu_axi_aw_bits_size; // @[lsu_bus_intf.scala 129:43] + assign io_axi_aw_bits_cache = bus_buffer_io_lsu_axi_aw_bits_cache; // @[lsu_bus_intf.scala 129:43] + assign io_axi_w_valid = bus_buffer_io_lsu_axi_w_valid; // @[lsu_bus_intf.scala 129:43] + assign io_axi_w_bits_data = bus_buffer_io_lsu_axi_w_bits_data; // @[lsu_bus_intf.scala 129:43] + assign io_axi_w_bits_strb = bus_buffer_io_lsu_axi_w_bits_strb; // @[lsu_bus_intf.scala 129:43] + assign io_axi_ar_valid = bus_buffer_io_lsu_axi_ar_valid; // @[lsu_bus_intf.scala 129:43] + assign io_axi_ar_bits_id = bus_buffer_io_lsu_axi_ar_bits_id; // @[lsu_bus_intf.scala 129:43] + assign io_axi_ar_bits_addr = bus_buffer_io_lsu_axi_ar_bits_addr; // @[lsu_bus_intf.scala 129:43] + assign io_axi_ar_bits_region = bus_buffer_io_lsu_axi_ar_bits_region; // @[lsu_bus_intf.scala 129:43] + assign io_axi_ar_bits_size = bus_buffer_io_lsu_axi_ar_bits_size; // @[lsu_bus_intf.scala 129:43] + assign io_axi_ar_bits_cache = bus_buffer_io_lsu_axi_ar_bits_cache; // @[lsu_bus_intf.scala 129:43] + assign io_lsu_busreq_r = bus_buffer_io_lsu_busreq_r; // @[lsu_bus_intf.scala 132:38] + assign io_lsu_bus_buffer_pend_any = bus_buffer_io_lsu_bus_buffer_pend_any; // @[lsu_bus_intf.scala 133:38] + assign io_lsu_bus_buffer_full_any = bus_buffer_io_lsu_bus_buffer_full_any; // @[lsu_bus_intf.scala 134:38] + assign io_lsu_bus_buffer_empty_any = bus_buffer_io_lsu_bus_buffer_empty_any; // @[lsu_bus_intf.scala 135:38] + assign io_bus_read_data_m = ld_fwddata_m[31:0]; // @[lsu_bus_intf.scala 191:27] + assign io_dctl_busbuff_lsu_nonblock_load_valid_m = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[lsu_bus_intf.scala 141:19] + assign io_dctl_busbuff_lsu_nonblock_load_tag_m = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_tag_m; // @[lsu_bus_intf.scala 141:19] + assign io_dctl_busbuff_lsu_nonblock_load_inv_r = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_inv_r; // @[lsu_bus_intf.scala 141:19] + assign io_dctl_busbuff_lsu_nonblock_load_inv_tag_r = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[lsu_bus_intf.scala 141:19] + assign io_dctl_busbuff_lsu_nonblock_load_data_valid = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_valid; // @[lsu_bus_intf.scala 141:19] + assign io_dctl_busbuff_lsu_nonblock_load_data_error = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_error; // @[lsu_bus_intf.scala 141:19] + assign io_dctl_busbuff_lsu_nonblock_load_data_tag = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_tag; // @[lsu_bus_intf.scala 141:19] + assign io_dctl_busbuff_lsu_nonblock_load_data = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data; // @[lsu_bus_intf.scala 141:19] assign bus_buffer_clock = clock; assign bus_buffer_reset = reset; - assign bus_buffer_io_scan_mode = io_scan_mode; // @[lsu_bus_intf.scala 103:29] - assign bus_buffer_io_tlu_busbuff_dec_tlu_external_ldfwd_disable = io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu_bus_intf.scala 104:18] - assign bus_buffer_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable = io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_intf.scala 104:18] - assign bus_buffer_io_dec_tlu_force_halt = io_dec_tlu_force_halt; // @[lsu_bus_intf.scala 106:51] - assign bus_buffer_io_lsu_c2_r_clk = io_lsu_c2_r_clk; // @[lsu_bus_intf.scala 107:51] - assign bus_buffer_io_lsu_bus_ibuf_c1_clk = io_lsu_bus_ibuf_c1_clk; // @[lsu_bus_intf.scala 108:51] - assign bus_buffer_io_lsu_bus_obuf_c1_clk = io_lsu_bus_obuf_c1_clk; // @[lsu_bus_intf.scala 109:51] - assign bus_buffer_io_lsu_bus_buf_c1_clk = io_lsu_bus_buf_c1_clk; // @[lsu_bus_intf.scala 110:51] - assign bus_buffer_io_lsu_free_c2_clk = io_lsu_free_c2_clk; // @[lsu_bus_intf.scala 111:51] - assign bus_buffer_io_lsu_busm_clk = io_lsu_busm_clk; // @[lsu_bus_intf.scala 112:51] - assign bus_buffer_io_dec_lsu_valid_raw_d = io_dec_lsu_valid_raw_d; // @[lsu_bus_intf.scala 113:51] - assign bus_buffer_io_lsu_pkt_m_valid = io_lsu_pkt_m_valid; // @[lsu_bus_intf.scala 116:27] - assign bus_buffer_io_lsu_pkt_m_bits_load = io_lsu_pkt_m_bits_load; // @[lsu_bus_intf.scala 116:27] - assign bus_buffer_io_lsu_pkt_r_bits_by = io_lsu_pkt_r_bits_by; // @[lsu_bus_intf.scala 117:27] - assign bus_buffer_io_lsu_pkt_r_bits_half = io_lsu_pkt_r_bits_half; // @[lsu_bus_intf.scala 117:27] - assign bus_buffer_io_lsu_pkt_r_bits_word = io_lsu_pkt_r_bits_word; // @[lsu_bus_intf.scala 117:27] - assign bus_buffer_io_lsu_pkt_r_bits_load = io_lsu_pkt_r_bits_load; // @[lsu_bus_intf.scala 117:27] - assign bus_buffer_io_lsu_pkt_r_bits_store = io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 117:27] - assign bus_buffer_io_lsu_pkt_r_bits_unsign = io_lsu_pkt_r_bits_unsign; // @[lsu_bus_intf.scala 117:27] - assign bus_buffer_io_lsu_addr_m = io_lsu_addr_m; // @[lsu_bus_intf.scala 120:51] - assign bus_buffer_io_end_addr_m = io_end_addr_m; // @[lsu_bus_intf.scala 121:51] - assign bus_buffer_io_lsu_addr_r = io_lsu_addr_r; // @[lsu_bus_intf.scala 122:51] - assign bus_buffer_io_end_addr_r = io_end_addr_r; // @[lsu_bus_intf.scala 123:51] - assign bus_buffer_io_store_data_r = io_store_data_r; // @[lsu_bus_intf.scala 124:51] - assign bus_buffer_io_no_word_merge_r = _T_22 & _T_24; // @[lsu_bus_intf.scala 143:51] - assign bus_buffer_io_no_dword_merge_r = _T_22 & _T_30; // @[lsu_bus_intf.scala 144:51] - assign bus_buffer_io_lsu_busreq_m = io_lsu_busreq_m; // @[lsu_bus_intf.scala 126:51] - assign bus_buffer_io_ld_full_hit_m = _T_372 & _T_373; // @[lsu_bus_intf.scala 150:51] - assign bus_buffer_io_flush_m_up = io_flush_m_up; // @[lsu_bus_intf.scala 127:51] - assign bus_buffer_io_flush_r = io_flush_r; // @[lsu_bus_intf.scala 128:51] - assign bus_buffer_io_lsu_commit_r = io_lsu_commit_r; // @[lsu_bus_intf.scala 129:51] - assign bus_buffer_io_is_sideeffects_r = is_sideeffects_r; // @[lsu_bus_intf.scala 145:51] - assign bus_buffer_io_ldst_dual_d = io_lsu_addr_d[2] != io_end_addr_d[2]; // @[lsu_bus_intf.scala 146:51] - assign bus_buffer_io_ldst_dual_m = ldst_dual_m; // @[lsu_bus_intf.scala 147:51] - assign bus_buffer_io_ldst_dual_r = ldst_dual_r; // @[lsu_bus_intf.scala 148:51] - assign bus_buffer_io_ldst_byteen_ext_m = {{1'd0}, _T_34}; // @[lsu_bus_intf.scala 149:51] - assign bus_buffer_io_lsu_axi_aw_ready = io_axi_aw_ready; // @[lsu_bus_intf.scala 130:43] - assign bus_buffer_io_lsu_axi_w_ready = io_axi_w_ready; // @[lsu_bus_intf.scala 130:43] - assign bus_buffer_io_lsu_axi_b_valid = io_axi_b_valid; // @[lsu_bus_intf.scala 130:43] - assign bus_buffer_io_lsu_axi_b_bits_id = io_axi_b_bits_id; // @[lsu_bus_intf.scala 130:43] - assign bus_buffer_io_lsu_axi_ar_ready = io_axi_ar_ready; // @[lsu_bus_intf.scala 130:43] - assign bus_buffer_io_lsu_axi_r_valid = io_axi_r_valid; // @[lsu_bus_intf.scala 130:43] - assign bus_buffer_io_lsu_axi_r_bits_id = io_axi_r_bits_id; // @[lsu_bus_intf.scala 130:43] - assign bus_buffer_io_lsu_axi_r_bits_data = io_axi_r_bits_data; // @[lsu_bus_intf.scala 130:43] - assign bus_buffer_io_lsu_axi_r_bits_resp = io_axi_r_bits_resp; // @[lsu_bus_intf.scala 130:43] - assign bus_buffer_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[lsu_bus_intf.scala 131:51] - assign bus_buffer_io_lsu_bus_clk_en_q = lsu_bus_clk_en_q; // @[lsu_bus_intf.scala 151:51] + assign bus_buffer_io_scan_mode = io_scan_mode; // @[lsu_bus_intf.scala 102:29] + assign bus_buffer_io_tlu_busbuff_dec_tlu_external_ldfwd_disable = io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu_bus_intf.scala 103:18] + assign bus_buffer_io_tlu_busbuff_dec_tlu_wb_coalescing_disable = io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_intf.scala 103:18] + assign bus_buffer_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable = io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_intf.scala 103:18] + assign bus_buffer_io_dec_tlu_force_halt = io_dec_tlu_force_halt; // @[lsu_bus_intf.scala 105:51] + assign bus_buffer_io_lsu_c2_r_clk = io_lsu_c2_r_clk; // @[lsu_bus_intf.scala 106:51] + assign bus_buffer_io_lsu_bus_ibuf_c1_clk = io_lsu_bus_ibuf_c1_clk; // @[lsu_bus_intf.scala 107:51] + assign bus_buffer_io_lsu_bus_obuf_c1_clk = io_lsu_bus_obuf_c1_clk; // @[lsu_bus_intf.scala 108:51] + assign bus_buffer_io_lsu_bus_buf_c1_clk = io_lsu_bus_buf_c1_clk; // @[lsu_bus_intf.scala 109:51] + assign bus_buffer_io_lsu_free_c2_clk = io_lsu_free_c2_clk; // @[lsu_bus_intf.scala 110:51] + assign bus_buffer_io_lsu_busm_clk = io_lsu_busm_clk; // @[lsu_bus_intf.scala 111:51] + assign bus_buffer_io_dec_lsu_valid_raw_d = io_dec_lsu_valid_raw_d; // @[lsu_bus_intf.scala 112:51] + assign bus_buffer_io_lsu_pkt_m_valid = io_lsu_pkt_m_valid; // @[lsu_bus_intf.scala 115:27] + assign bus_buffer_io_lsu_pkt_m_bits_load = io_lsu_pkt_m_bits_load; // @[lsu_bus_intf.scala 115:27] + assign bus_buffer_io_lsu_pkt_r_bits_by = io_lsu_pkt_r_bits_by; // @[lsu_bus_intf.scala 116:27] + assign bus_buffer_io_lsu_pkt_r_bits_half = io_lsu_pkt_r_bits_half; // @[lsu_bus_intf.scala 116:27] + assign bus_buffer_io_lsu_pkt_r_bits_word = io_lsu_pkt_r_bits_word; // @[lsu_bus_intf.scala 116:27] + assign bus_buffer_io_lsu_pkt_r_bits_load = io_lsu_pkt_r_bits_load; // @[lsu_bus_intf.scala 116:27] + assign bus_buffer_io_lsu_pkt_r_bits_store = io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 116:27] + assign bus_buffer_io_lsu_pkt_r_bits_unsign = io_lsu_pkt_r_bits_unsign; // @[lsu_bus_intf.scala 116:27] + assign bus_buffer_io_lsu_addr_m = io_lsu_addr_m; // @[lsu_bus_intf.scala 119:51] + assign bus_buffer_io_end_addr_m = io_end_addr_m; // @[lsu_bus_intf.scala 120:51] + assign bus_buffer_io_lsu_addr_r = io_lsu_addr_r; // @[lsu_bus_intf.scala 121:51] + assign bus_buffer_io_end_addr_r = io_end_addr_r; // @[lsu_bus_intf.scala 122:51] + assign bus_buffer_io_store_data_r = io_store_data_r; // @[lsu_bus_intf.scala 123:51] + assign bus_buffer_io_no_word_merge_r = _T_22 & _T_24; // @[lsu_bus_intf.scala 142:51] + assign bus_buffer_io_no_dword_merge_r = _T_22 & _T_30; // @[lsu_bus_intf.scala 143:51] + assign bus_buffer_io_lsu_busreq_m = io_lsu_busreq_m; // @[lsu_bus_intf.scala 125:51] + assign bus_buffer_io_ld_full_hit_m = _T_372 & _T_373; // @[lsu_bus_intf.scala 149:51] + assign bus_buffer_io_flush_m_up = io_flush_m_up; // @[lsu_bus_intf.scala 126:51] + assign bus_buffer_io_flush_r = io_flush_r; // @[lsu_bus_intf.scala 127:51] + assign bus_buffer_io_lsu_commit_r = io_lsu_commit_r; // @[lsu_bus_intf.scala 128:51] + assign bus_buffer_io_is_sideeffects_r = is_sideeffects_r; // @[lsu_bus_intf.scala 144:51] + assign bus_buffer_io_ldst_dual_d = io_lsu_addr_d[2] != io_end_addr_d[2]; // @[lsu_bus_intf.scala 145:51] + assign bus_buffer_io_ldst_dual_m = ldst_dual_m; // @[lsu_bus_intf.scala 146:51] + assign bus_buffer_io_ldst_dual_r = ldst_dual_r; // @[lsu_bus_intf.scala 147:51] + assign bus_buffer_io_ldst_byteen_ext_m = {{1'd0}, _T_34}; // @[lsu_bus_intf.scala 148:51] + assign bus_buffer_io_lsu_axi_aw_ready = io_axi_aw_ready; // @[lsu_bus_intf.scala 129:43] + assign bus_buffer_io_lsu_axi_w_ready = io_axi_w_ready; // @[lsu_bus_intf.scala 129:43] + assign bus_buffer_io_lsu_axi_b_valid = io_axi_b_valid; // @[lsu_bus_intf.scala 129:43] + assign bus_buffer_io_lsu_axi_b_bits_id = io_axi_b_bits_id; // @[lsu_bus_intf.scala 129:43] + assign bus_buffer_io_lsu_axi_ar_ready = io_axi_ar_ready; // @[lsu_bus_intf.scala 129:43] + assign bus_buffer_io_lsu_axi_r_valid = io_axi_r_valid; // @[lsu_bus_intf.scala 129:43] + assign bus_buffer_io_lsu_axi_r_bits_id = io_axi_r_bits_id; // @[lsu_bus_intf.scala 129:43] + assign bus_buffer_io_lsu_axi_r_bits_data = io_axi_r_bits_data; // @[lsu_bus_intf.scala 129:43] + assign bus_buffer_io_lsu_axi_r_bits_resp = io_axi_r_bits_resp; // @[lsu_bus_intf.scala 129:43] + assign bus_buffer_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[lsu_bus_intf.scala 130:51] + assign bus_buffer_io_lsu_bus_clk_en_q = lsu_bus_clk_en_q; // @[lsu_bus_intf.scala 150:51] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -73200,6 +73379,7 @@ module lsu( output io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error, output io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy, input io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable, + input io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable, input io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable, output io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any, output io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any, @@ -73228,7 +73408,9 @@ module lsu( output io_axi_aw_valid, output [2:0] io_axi_aw_bits_id, output [31:0] io_axi_aw_bits_addr, + output [3:0] io_axi_aw_bits_region, output [2:0] io_axi_aw_bits_size, + output [3:0] io_axi_aw_bits_cache, input io_axi_w_ready, output io_axi_w_valid, output [63:0] io_axi_w_bits_data, @@ -73239,7 +73421,9 @@ module lsu( output io_axi_ar_valid, output [2:0] io_axi_ar_bits_id, output [31:0] io_axi_ar_bits_addr, + output [3:0] io_axi_ar_bits_region, output [2:0] io_axi_ar_bits_size, + output [3:0] io_axi_ar_bits_cache, input io_axi_r_valid, input [2:0] io_axi_r_bits_id, input [63:0] io_axi_r_bits_data, @@ -73664,6 +73848,7 @@ module lsu( wire bus_intf_io_tlu_busbuff_lsu_pmu_bus_error; // @[lsu.scala 68:30] wire bus_intf_io_tlu_busbuff_lsu_pmu_bus_busy; // @[lsu.scala 68:30] wire bus_intf_io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu.scala 68:30] + wire bus_intf_io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu.scala 68:30] wire bus_intf_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu.scala 68:30] wire bus_intf_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[lsu.scala 68:30] wire bus_intf_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu.scala 68:30] @@ -73681,7 +73866,9 @@ module lsu( wire bus_intf_io_axi_aw_valid; // @[lsu.scala 68:30] wire [2:0] bus_intf_io_axi_aw_bits_id; // @[lsu.scala 68:30] wire [31:0] bus_intf_io_axi_aw_bits_addr; // @[lsu.scala 68:30] + wire [3:0] bus_intf_io_axi_aw_bits_region; // @[lsu.scala 68:30] wire [2:0] bus_intf_io_axi_aw_bits_size; // @[lsu.scala 68:30] + wire [3:0] bus_intf_io_axi_aw_bits_cache; // @[lsu.scala 68:30] wire bus_intf_io_axi_w_ready; // @[lsu.scala 68:30] wire bus_intf_io_axi_w_valid; // @[lsu.scala 68:30] wire [63:0] bus_intf_io_axi_w_bits_data; // @[lsu.scala 68:30] @@ -73692,7 +73879,9 @@ module lsu( wire bus_intf_io_axi_ar_valid; // @[lsu.scala 68:30] wire [2:0] bus_intf_io_axi_ar_bits_id; // @[lsu.scala 68:30] wire [31:0] bus_intf_io_axi_ar_bits_addr; // @[lsu.scala 68:30] + wire [3:0] bus_intf_io_axi_ar_bits_region; // @[lsu.scala 68:30] wire [2:0] bus_intf_io_axi_ar_bits_size; // @[lsu.scala 68:30] + wire [3:0] bus_intf_io_axi_ar_bits_cache; // @[lsu.scala 68:30] wire bus_intf_io_axi_r_valid; // @[lsu.scala 68:30] wire [2:0] bus_intf_io_axi_r_bits_id; // @[lsu.scala 68:30] wire [63:0] bus_intf_io_axi_r_bits_data; // @[lsu.scala 68:30] @@ -74143,6 +74332,7 @@ module lsu( .io_tlu_busbuff_lsu_pmu_bus_error(bus_intf_io_tlu_busbuff_lsu_pmu_bus_error), .io_tlu_busbuff_lsu_pmu_bus_busy(bus_intf_io_tlu_busbuff_lsu_pmu_bus_busy), .io_tlu_busbuff_dec_tlu_external_ldfwd_disable(bus_intf_io_tlu_busbuff_dec_tlu_external_ldfwd_disable), + .io_tlu_busbuff_dec_tlu_wb_coalescing_disable(bus_intf_io_tlu_busbuff_dec_tlu_wb_coalescing_disable), .io_tlu_busbuff_dec_tlu_sideeffect_posted_disable(bus_intf_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable), .io_tlu_busbuff_lsu_imprecise_error_load_any(bus_intf_io_tlu_busbuff_lsu_imprecise_error_load_any), .io_tlu_busbuff_lsu_imprecise_error_store_any(bus_intf_io_tlu_busbuff_lsu_imprecise_error_store_any), @@ -74160,7 +74350,9 @@ module lsu( .io_axi_aw_valid(bus_intf_io_axi_aw_valid), .io_axi_aw_bits_id(bus_intf_io_axi_aw_bits_id), .io_axi_aw_bits_addr(bus_intf_io_axi_aw_bits_addr), + .io_axi_aw_bits_region(bus_intf_io_axi_aw_bits_region), .io_axi_aw_bits_size(bus_intf_io_axi_aw_bits_size), + .io_axi_aw_bits_cache(bus_intf_io_axi_aw_bits_cache), .io_axi_w_ready(bus_intf_io_axi_w_ready), .io_axi_w_valid(bus_intf_io_axi_w_valid), .io_axi_w_bits_data(bus_intf_io_axi_w_bits_data), @@ -74171,7 +74363,9 @@ module lsu( .io_axi_ar_valid(bus_intf_io_axi_ar_valid), .io_axi_ar_bits_id(bus_intf_io_axi_ar_bits_id), .io_axi_ar_bits_addr(bus_intf_io_axi_ar_bits_addr), + .io_axi_ar_bits_region(bus_intf_io_axi_ar_bits_region), .io_axi_ar_bits_size(bus_intf_io_axi_ar_bits_size), + .io_axi_ar_bits_cache(bus_intf_io_axi_ar_bits_cache), .io_axi_r_valid(bus_intf_io_axi_r_valid), .io_axi_r_bits_id(bus_intf_io_axi_r_bits_id), .io_axi_r_bits_data(bus_intf_io_axi_r_bits_data), @@ -74256,14 +74450,18 @@ module lsu( assign io_axi_aw_valid = bus_intf_io_axi_aw_valid; // @[lsu.scala 314:49] assign io_axi_aw_bits_id = bus_intf_io_axi_aw_bits_id; // @[lsu.scala 314:49] assign io_axi_aw_bits_addr = bus_intf_io_axi_aw_bits_addr; // @[lsu.scala 314:49] + assign io_axi_aw_bits_region = bus_intf_io_axi_aw_bits_region; // @[lsu.scala 314:49] assign io_axi_aw_bits_size = bus_intf_io_axi_aw_bits_size; // @[lsu.scala 314:49] + assign io_axi_aw_bits_cache = bus_intf_io_axi_aw_bits_cache; // @[lsu.scala 314:49] assign io_axi_w_valid = bus_intf_io_axi_w_valid; // @[lsu.scala 314:49] assign io_axi_w_bits_data = bus_intf_io_axi_w_bits_data; // @[lsu.scala 314:49] assign io_axi_w_bits_strb = bus_intf_io_axi_w_bits_strb; // @[lsu.scala 314:49] assign io_axi_ar_valid = bus_intf_io_axi_ar_valid; // @[lsu.scala 314:49] assign io_axi_ar_bits_id = bus_intf_io_axi_ar_bits_id; // @[lsu.scala 314:49] assign io_axi_ar_bits_addr = bus_intf_io_axi_ar_bits_addr; // @[lsu.scala 314:49] + assign io_axi_ar_bits_region = bus_intf_io_axi_ar_bits_region; // @[lsu.scala 314:49] assign io_axi_ar_bits_size = bus_intf_io_axi_ar_bits_size; // @[lsu.scala 314:49] + assign io_axi_ar_bits_cache = bus_intf_io_axi_ar_bits_cache; // @[lsu.scala 314:49] assign io_lsu_result_m = lsu_lsc_ctl_io_lsu_result_m; // @[lsu.scala 61:19] assign io_lsu_result_corr_r = lsu_lsc_ctl_io_lsu_result_corr_r; // @[lsu.scala 62:24] assign io_lsu_load_stall_any = bus_intf_io_lsu_bus_buffer_full_any | dccm_ctl_io_ld_single_ecc_error_r_ff; // @[lsu.scala 75:25] @@ -74498,6 +74696,7 @@ module lsu( assign bus_intf_reset = reset; assign bus_intf_io_scan_mode = io_scan_mode; // @[lsu.scala 285:49] assign bus_intf_io_tlu_busbuff_dec_tlu_external_ldfwd_disable = io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu.scala 286:26] + assign bus_intf_io_tlu_busbuff_dec_tlu_wb_coalescing_disable = io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu.scala 286:26] assign bus_intf_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable = io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu.scala 286:26] assign bus_intf_io_lsu_c1_m_clk = clkdomain_io_lsu_c1_m_clk; // @[lsu.scala 287:49] assign bus_intf_io_lsu_c1_r_clk = clkdomain_io_lsu_c1_r_clk; // @[lsu.scala 288:49] @@ -78282,18 +78481,25 @@ module dma_ctrl( input io_iccm_ready, output io_dma_axi_aw_ready, input io_dma_axi_aw_valid, + input io_dma_axi_aw_bits_id, input [31:0] io_dma_axi_aw_bits_addr, input [2:0] io_dma_axi_aw_bits_size, output io_dma_axi_w_ready, input io_dma_axi_w_valid, input [63:0] io_dma_axi_w_bits_data, input [7:0] io_dma_axi_w_bits_strb, + input io_dma_axi_b_ready, output io_dma_axi_b_valid, + output [1:0] io_dma_axi_b_bits_resp, + output io_dma_axi_b_bits_id, output io_dma_axi_ar_ready, input io_dma_axi_ar_valid, + input io_dma_axi_ar_bits_id, input [31:0] io_dma_axi_ar_bits_addr, input [2:0] io_dma_axi_ar_bits_size, + input io_dma_axi_r_ready, output io_dma_axi_r_valid, + output io_dma_axi_r_bits_id, output [63:0] io_dma_axi_r_bits_data, output [1:0] io_dma_axi_r_bits_resp, output io_lsu_dma_dma_lsc_ctl_dma_dccm_req, @@ -78390,6 +78596,13 @@ module dma_ctrl( reg [63:0] _RAND_69; reg [31:0] _RAND_70; reg [31:0] _RAND_71; + reg [31:0] _RAND_72; + reg [31:0] _RAND_73; + reg [31:0] _RAND_74; + reg [31:0] _RAND_75; + reg [31:0] _RAND_76; + reg [31:0] _RAND_77; + reg [31:0] _RAND_78; `endif // RANDOMIZE_REG_INIT wire rvclkhdr_io_l1clk; // @[lib.scala 368:23] wire rvclkhdr_io_clk; // @[lib.scala 368:23] @@ -78786,7 +78999,9 @@ module dma_ctrl( wire _T_399 = fifo_done_en[4] | fifo_done[4]; // @[dma_ctrl.scala 218:75] wire _T_400 = _T_399 & io_dma_bus_clk_en; // @[dma_ctrl.scala 218:91] wire [4:0] fifo_done_bus_en = {_T_400,_T_396,_T_392,_T_388,_T_384}; // @[Cat.scala 29:58] - wire bus_rsp_sent = io_dma_axi_b_valid | io_dma_axi_r_valid; // @[dma_ctrl.scala 502:83] + wire _T_1285 = io_dma_axi_b_valid & io_dma_axi_b_ready; // @[dma_ctrl.scala 502:61] + wire _T_1286 = io_dma_axi_r_valid & io_dma_axi_r_ready; // @[dma_ctrl.scala 502:105] + wire bus_rsp_sent = _T_1285 | _T_1286; // @[dma_ctrl.scala 502:83] wire _T_406 = bus_rsp_sent & io_dma_bus_clk_en; // @[dma_ctrl.scala 220:99] wire _T_407 = _T_406 | io_dma_dbg_cmd_done; // @[dma_ctrl.scala 220:120] reg [2:0] RspPtr; // @[Reg.scala 27:20] @@ -78868,6 +79083,14 @@ module dma_ctrl( reg [63:0] fifo_data_2; // @[lib.scala 374:16] reg [63:0] fifo_data_3; // @[lib.scala 374:16] reg [63:0] fifo_data_4; // @[lib.scala 374:16] + reg fifo_tag_0; // @[Reg.scala 27:20] + reg wrbuf_tag; // @[Reg.scala 27:20] + reg rdbuf_tag; // @[Reg.scala 27:20] + wire bus_cmd_tag = axi_mstr_sel ? wrbuf_tag : rdbuf_tag; // @[dma_ctrl.scala 467:43] + reg fifo_tag_1; // @[Reg.scala 27:20] + reg fifo_tag_2; // @[Reg.scala 27:20] + reg fifo_tag_3; // @[Reg.scala 27:20] + reg fifo_tag_4; // @[Reg.scala 27:20] wire _T_931 = WrPtr == 3'h4; // @[dma_ctrl.scala 260:30] wire [2:0] _T_934 = WrPtr + 3'h1; // @[dma_ctrl.scala 260:76] wire _T_936 = RdPtr == 3'h4; // @[dma_ctrl.scala 262:30] @@ -78934,7 +79157,8 @@ module dma_ctrl( reg dma_dbg_cmd_done_q; // @[dma_ctrl.scala 381:12] wire _T_1212 = bus_cmd_valid & io_dma_bus_clk_en; // @[dma_ctrl.scala 386:44] wire _T_1213 = _T_1212 | io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[dma_ctrl.scala 386:65] - wire _T_1214 = bus_cmd_valid | bus_rsp_sent; // @[dma_ctrl.scala 387:44] + wire bus_rsp_valid = io_dma_axi_b_valid | io_dma_axi_r_valid; // @[dma_ctrl.scala 501:60] + wire _T_1214 = bus_cmd_valid | bus_rsp_valid; // @[dma_ctrl.scala 387:44] wire _T_1215 = _T_1214 | io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[dma_ctrl.scala 387:60] wire _T_1216 = _T_1215 | io_dma_dbg_cmd_done; // @[dma_ctrl.scala 387:94] wire _T_1217 = _T_1216 | dma_dbg_cmd_done_q; // @[dma_ctrl.scala 387:116] @@ -78970,6 +79194,9 @@ module dma_ctrl( wire [4:0] _T_1275 = fifo_write >> RspPtr; // @[dma_ctrl.scala 483:39] wire axi_rsp_write = _T_1275[0]; // @[dma_ctrl.scala 483:39] wire [1:0] _T_1278 = _GEN_57[1] ? 2'h3 : 2'h0; // @[dma_ctrl.scala 484:64] + wire _GEN_86 = 3'h1 == RspPtr ? fifo_tag_1 : fifo_tag_0; // @[dma_ctrl.scala 492:33] + wire _GEN_87 = 3'h2 == RspPtr ? fifo_tag_2 : _GEN_86; // @[dma_ctrl.scala 492:33] + wire _GEN_88 = 3'h3 == RspPtr ? fifo_tag_3 : _GEN_87; // @[dma_ctrl.scala 492:33] wire _T_1281 = ~axi_rsp_write; // @[dma_ctrl.scala 494:46] rvclkhdr rvclkhdr ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_io_l1clk), @@ -79081,8 +79308,11 @@ module dma_ctrl( assign io_dma_axi_aw_ready = ~_T_1243; // @[dma_ctrl.scala 453:27] assign io_dma_axi_w_ready = ~_T_1246; // @[dma_ctrl.scala 454:27] assign io_dma_axi_b_valid = axi_rsp_valid & axi_rsp_write; // @[dma_ctrl.scala 490:27] + assign io_dma_axi_b_bits_resp = _GEN_57[0] ? 2'h2 : _T_1278; // @[dma_ctrl.scala 491:41] + assign io_dma_axi_b_bits_id = 3'h4 == RspPtr ? fifo_tag_4 : _GEN_88; // @[dma_ctrl.scala 492:33] assign io_dma_axi_ar_ready = ~_T_1249; // @[dma_ctrl.scala 455:27] assign io_dma_axi_r_valid = axi_rsp_valid & _T_1281; // @[dma_ctrl.scala 494:27] + assign io_dma_axi_r_bits_id = 3'h4 == RspPtr ? fifo_tag_4 : _GEN_88; // @[dma_ctrl.scala 498:37] assign io_dma_axi_r_bits_data = 3'h4 == RspPtr ? fifo_data_4 : _GEN_51; // @[dma_ctrl.scala 496:43] assign io_dma_axi_r_bits_resp = _GEN_57[0] ? 2'h2 : _T_1278; // @[dma_ctrl.scala 495:41] assign io_lsu_dma_dma_lsc_ctl_dma_dccm_req = _T_1137 & io_lsu_dma_dccm_ready; // @[dma_ctrl.scala 352:40] @@ -79324,9 +79554,23 @@ initial begin _RAND_69 = {2{`RANDOM}}; fifo_data_4 = _RAND_69[63:0]; _RAND_70 = {1{`RANDOM}}; - dma_nack_count = _RAND_70[2:0]; + fifo_tag_0 = _RAND_70[0:0]; _RAND_71 = {1{`RANDOM}}; - dma_dbg_cmd_done_q = _RAND_71[0:0]; + wrbuf_tag = _RAND_71[0:0]; + _RAND_72 = {1{`RANDOM}}; + rdbuf_tag = _RAND_72[0:0]; + _RAND_73 = {1{`RANDOM}}; + fifo_tag_1 = _RAND_73[0:0]; + _RAND_74 = {1{`RANDOM}}; + fifo_tag_2 = _RAND_74[0:0]; + _RAND_75 = {1{`RANDOM}}; + fifo_tag_3 = _RAND_75[0:0]; + _RAND_76 = {1{`RANDOM}}; + fifo_tag_4 = _RAND_76[0:0]; + _RAND_77 = {1{`RANDOM}}; + dma_nack_count = _RAND_77[2:0]; + _RAND_78 = {1{`RANDOM}}; + dma_dbg_cmd_done_q = _RAND_78[0:0]; `endif // RANDOMIZE_REG_INIT if (reset) begin RdPtr = 3'h0; @@ -79538,6 +79782,27 @@ initial begin if (reset) begin fifo_data_4 = 64'h0; end + if (reset) begin + fifo_tag_0 = 1'h0; + end + if (reset) begin + wrbuf_tag = 1'h0; + end + if (reset) begin + rdbuf_tag = 1'h0; + end + if (reset) begin + fifo_tag_1 = 1'h0; + end + if (reset) begin + fifo_tag_2 = 1'h0; + end + if (reset) begin + fifo_tag_3 = 1'h0; + end + if (reset) begin + fifo_tag_4 = 1'h0; + end if (reset) begin dma_nack_count = 3'h0; end @@ -80156,6 +80421,71 @@ end // initial fifo_data_4 <= _T_500; end end + always @(posedge dma_buffer_c1_clk or posedge reset) begin + if (reset) begin + fifo_tag_0 <= 1'h0; + end else if (fifo_cmd_en[0]) begin + if (axi_mstr_sel) begin + fifo_tag_0 <= wrbuf_tag; + end else begin + fifo_tag_0 <= rdbuf_tag; + end + end + end + always @(posedge dma_bus_clk or posedge reset) begin + if (reset) begin + wrbuf_tag <= 1'h0; + end else if (wrbuf_en) begin + wrbuf_tag <= io_dma_axi_aw_bits_id; + end + end + always @(posedge dma_bus_clk or posedge reset) begin + if (reset) begin + rdbuf_tag <= 1'h0; + end else if (rdbuf_en) begin + rdbuf_tag <= io_dma_axi_ar_bits_id; + end + end + always @(posedge dma_buffer_c1_clk or posedge reset) begin + if (reset) begin + fifo_tag_1 <= 1'h0; + end else if (fifo_cmd_en[1]) begin + if (axi_mstr_sel) begin + fifo_tag_1 <= wrbuf_tag; + end else begin + fifo_tag_1 <= rdbuf_tag; + end + end + end + always @(posedge dma_buffer_c1_clk or posedge reset) begin + if (reset) begin + fifo_tag_2 <= 1'h0; + end else if (fifo_cmd_en[2]) begin + if (axi_mstr_sel) begin + fifo_tag_2 <= wrbuf_tag; + end else begin + fifo_tag_2 <= rdbuf_tag; + end + end + end + always @(posedge dma_buffer_c1_clk or posedge reset) begin + if (reset) begin + fifo_tag_3 <= 1'h0; + end else if (fifo_cmd_en[3]) begin + if (axi_mstr_sel) begin + fifo_tag_3 <= wrbuf_tag; + end else begin + fifo_tag_3 <= rdbuf_tag; + end + end + end + always @(posedge dma_buffer_c1_clk or posedge reset) begin + if (reset) begin + fifo_tag_4 <= 1'h0; + end else if (fifo_cmd_en[4]) begin + fifo_tag_4 <= bus_cmd_tag; + end + end always @(posedge dma_free_clk or posedge reset) begin if (reset) begin dma_nack_count <= 3'h0; @@ -80177,2674 +80507,84 @@ end // initial end end endmodule -module axi4_to_ahb( - input clock, - input reset, - input io_scan_mode, - input io_bus_clk_en, - input io_clk_override, - output io_axi_aw_ready, - input io_axi_aw_valid, - input [31:0] io_axi_aw_bits_addr, - input [2:0] io_axi_aw_bits_size, - output io_axi_w_ready, - input io_axi_w_valid, - input [63:0] io_axi_w_bits_data, - input [7:0] io_axi_w_bits_strb, - output io_axi_b_valid, - output [1:0] io_axi_b_bits_resp, - output io_axi_ar_ready, - input io_axi_ar_valid, - input [31:0] io_axi_ar_bits_addr, - input [2:0] io_axi_ar_bits_size, - output io_axi_r_valid, - output [63:0] io_axi_r_bits_data, - output [1:0] io_axi_r_bits_resp, - input [63:0] io_ahb_in_hrdata, - input io_ahb_in_hready, - input io_ahb_in_hresp, - output [31:0] io_ahb_out_haddr, - output [2:0] io_ahb_out_hsize, - output [1:0] io_ahb_out_htrans, - output io_ahb_out_hwrite, - output [63:0] io_ahb_out_hwdata -); -`ifdef RANDOMIZE_REG_INIT - reg [31:0] _RAND_0; - reg [31:0] _RAND_1; - reg [31:0] _RAND_2; - reg [31:0] _RAND_3; - reg [31:0] _RAND_4; - reg [31:0] _RAND_5; - reg [31:0] _RAND_6; - reg [31:0] _RAND_7; - reg [31:0] _RAND_8; - reg [31:0] _RAND_9; - reg [31:0] _RAND_10; - reg [63:0] _RAND_11; - reg [31:0] _RAND_12; - reg [31:0] _RAND_13; - reg [31:0] _RAND_14; - reg [63:0] _RAND_15; - reg [63:0] _RAND_16; - reg [31:0] _RAND_17; - reg [31:0] _RAND_18; - reg [31:0] _RAND_19; - reg [31:0] _RAND_20; - reg [31:0] _RAND_21; - reg [31:0] _RAND_22; -`endif // RANDOMIZE_REG_INIT - wire rvclkhdr_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_io_en; // @[lib.scala 343:22] - wire rvclkhdr_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_1_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_1_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_1_io_en; // @[lib.scala 343:22] - wire rvclkhdr_1_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_2_io_l1clk; // @[lib.scala 368:23] - wire rvclkhdr_2_io_clk; // @[lib.scala 368:23] - wire rvclkhdr_2_io_en; // @[lib.scala 368:23] - wire rvclkhdr_2_io_scan_mode; // @[lib.scala 368:23] - wire rvclkhdr_3_io_l1clk; // @[lib.scala 368:23] - wire rvclkhdr_3_io_clk; // @[lib.scala 368:23] - wire rvclkhdr_3_io_en; // @[lib.scala 368:23] - wire rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23] - wire rvclkhdr_4_io_l1clk; // @[lib.scala 368:23] - wire rvclkhdr_4_io_clk; // @[lib.scala 368:23] - wire rvclkhdr_4_io_en; // @[lib.scala 368:23] - wire rvclkhdr_4_io_scan_mode; // @[lib.scala 368:23] - wire rvclkhdr_5_io_l1clk; // @[lib.scala 368:23] - wire rvclkhdr_5_io_clk; // @[lib.scala 368:23] - wire rvclkhdr_5_io_en; // @[lib.scala 368:23] - wire rvclkhdr_5_io_scan_mode; // @[lib.scala 368:23] - wire rvclkhdr_6_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_6_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_6_io_en; // @[lib.scala 343:22] - wire rvclkhdr_6_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_7_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_7_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_7_io_en; // @[lib.scala 343:22] - wire rvclkhdr_7_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_8_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_8_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_8_io_en; // @[lib.scala 343:22] - wire rvclkhdr_8_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_9_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_9_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_9_io_en; // @[lib.scala 343:22] - wire rvclkhdr_9_io_scan_mode; // @[lib.scala 343:22] - wire ahbm_clk = rvclkhdr_7_io_l1clk; // @[axi4_to_ahb.scala 24:22 axi4_to_ahb.scala 333:12] - reg [2:0] buf_state; // @[axi4_to_ahb.scala 30:45] - wire _T_49 = 3'h0 == buf_state; // @[Conditional.scala 37:30] - wire bus_clk = rvclkhdr_io_l1clk; // @[axi4_to_ahb.scala 50:21 axi4_to_ahb.scala 162:11] - reg wrbuf_vld; // @[axi4_to_ahb.scala 301:51] - reg wrbuf_data_vld; // @[axi4_to_ahb.scala 302:51] - wire wr_cmd_vld = wrbuf_vld & wrbuf_data_vld; // @[axi4_to_ahb.scala 139:27] - wire master_valid = wr_cmd_vld | io_axi_ar_valid; // @[axi4_to_ahb.scala 140:30] - wire _T_101 = 3'h1 == buf_state; // @[Conditional.scala 37:30] - reg ahb_hready_q; // @[axi4_to_ahb.scala 321:52] - reg [1:0] ahb_htrans_q; // @[axi4_to_ahb.scala 322:52] - wire _T_108 = ahb_htrans_q != 2'h0; // @[axi4_to_ahb.scala 183:58] - wire _T_109 = ahb_hready_q & _T_108; // @[axi4_to_ahb.scala 183:36] - wire ahbm_addr_clk = rvclkhdr_8_io_l1clk; // @[axi4_to_ahb.scala 25:27 axi4_to_ahb.scala 334:17] - reg ahb_hwrite_q; // @[axi4_to_ahb.scala 323:57] - wire _T_110 = ~ahb_hwrite_q; // @[axi4_to_ahb.scala 183:72] - wire _T_111 = _T_109 & _T_110; // @[axi4_to_ahb.scala 183:70] - wire _T_136 = 3'h6 == buf_state; // @[Conditional.scala 37:30] - reg ahb_hresp_q; // @[axi4_to_ahb.scala 324:52] - wire _T_156 = ahb_hready_q | ahb_hresp_q; // @[axi4_to_ahb.scala 197:37] - wire _T_175 = 3'h7 == buf_state; // @[Conditional.scala 37:30] - wire _T_186 = 3'h3 == buf_state; // @[Conditional.scala 37:30] - wire _T_188 = 3'h2 == buf_state; // @[Conditional.scala 37:30] - wire _T_189 = ahb_hready_q & ahb_hwrite_q; // @[axi4_to_ahb.scala 229:33] - wire _T_192 = _T_189 & _T_108; // @[axi4_to_ahb.scala 229:48] - wire _T_281 = 3'h4 == buf_state; // @[Conditional.scala 37:30] - wire _GEN_15 = _T_281 & _T_192; // @[Conditional.scala 39:67] - wire _GEN_19 = _T_188 ? _T_192 : _GEN_15; // @[Conditional.scala 39:67] - wire _GEN_40 = _T_186 ? 1'h0 : _GEN_19; // @[Conditional.scala 39:67] - wire _GEN_59 = _T_175 ? 1'h0 : _GEN_40; // @[Conditional.scala 39:67] - wire _GEN_79 = _T_136 ? 1'h0 : _GEN_59; // @[Conditional.scala 39:67] - wire _GEN_95 = _T_101 ? 1'h0 : _GEN_79; // @[Conditional.scala 39:67] - wire trxn_done = _T_49 ? 1'h0 : _GEN_95; // @[Conditional.scala 40:58] - reg cmd_doneQ; // @[axi4_to_ahb.scala 319:52] - wire _T_282 = cmd_doneQ & ahb_hready_q; // @[axi4_to_ahb.scala 239:34] - wire _T_283 = _T_282 | ahb_hresp_q; // @[axi4_to_ahb.scala 239:50] - wire _T_440 = 3'h5 == buf_state; // @[Conditional.scala 37:30] - wire _GEN_3 = _T_281 ? _T_283 : _T_440; // @[Conditional.scala 39:67] - wire _GEN_20 = _T_188 ? trxn_done : _GEN_3; // @[Conditional.scala 39:67] - wire _GEN_35 = _T_186 ? _T_156 : _GEN_20; // @[Conditional.scala 39:67] - wire _GEN_51 = _T_175 ? _T_111 : _GEN_35; // @[Conditional.scala 39:67] - wire _GEN_69 = _T_136 ? _T_156 : _GEN_51; // @[Conditional.scala 39:67] - wire _GEN_83 = _T_101 ? _T_111 : _GEN_69; // @[Conditional.scala 39:67] - wire buf_state_en = _T_49 ? master_valid : _GEN_83; // @[Conditional.scala 40:58] - wire [1:0] _T_14 = wr_cmd_vld ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 142:20] - wire [2:0] master_opc = {{1'd0}, _T_14}; // @[axi4_to_ahb.scala 142:14] - wire _T_51 = master_opc[2:1] == 2'h1; // @[axi4_to_ahb.scala 168:41] - wire _GEN_8 = _T_281 & _T_51; // @[Conditional.scala 39:67] - wire _GEN_29 = _T_188 ? 1'h0 : _GEN_8; // @[Conditional.scala 39:67] - wire _GEN_46 = _T_186 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67] - wire _GEN_63 = _T_175 ? 1'h0 : _GEN_46; // @[Conditional.scala 39:67] - wire _GEN_81 = _T_136 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67] - wire _GEN_97 = _T_101 ? 1'h0 : _GEN_81; // @[Conditional.scala 39:67] - wire buf_write_in = _T_49 ? _T_51 : _GEN_97; // @[Conditional.scala 40:58] - wire [2:0] _T_53 = buf_write_in ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 169:26] - wire _T_103 = master_opc == 3'h0; // @[axi4_to_ahb.scala 182:61] - wire _T_104 = master_valid & _T_103; // @[axi4_to_ahb.scala 182:41] - wire [2:0] _T_106 = _T_104 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 182:26] - wire _T_124 = _T_106 == 3'h6; // @[axi4_to_ahb.scala 186:174] - wire _T_125 = _T_111 & _T_124; // @[axi4_to_ahb.scala 186:88] - wire _T_137 = ~ahb_hresp_q; // @[axi4_to_ahb.scala 194:39] - wire _T_138 = ahb_hready_q & _T_137; // @[axi4_to_ahb.scala 194:37] - wire _T_141 = master_valid & _T_51; // @[axi4_to_ahb.scala 194:70] - wire _T_142 = ~_T_141; // @[axi4_to_ahb.scala 194:55] - wire _T_143 = _T_138 & _T_142; // @[axi4_to_ahb.scala 194:53] - wire _T_285 = buf_state_en & _T_137; // @[axi4_to_ahb.scala 240:36] - wire _GEN_4 = _T_281 & _T_285; // @[Conditional.scala 39:67] - wire _GEN_26 = _T_188 ? 1'h0 : _GEN_4; // @[Conditional.scala 39:67] - wire _GEN_45 = _T_186 ? 1'h0 : _GEN_26; // @[Conditional.scala 39:67] - wire _GEN_62 = _T_175 ? 1'h0 : _GEN_45; // @[Conditional.scala 39:67] - wire _GEN_66 = _T_136 ? _T_143 : _GEN_62; // @[Conditional.scala 39:67] - wire _GEN_86 = _T_101 ? _T_125 : _GEN_66; // @[Conditional.scala 39:67] - wire master_ready = _T_49 | _GEN_86; // @[Conditional.scala 40:58] - wire _T_149 = master_valid & master_ready; // @[axi4_to_ahb.scala 196:82] - wire _T_152 = _T_149 & _T_103; // @[axi4_to_ahb.scala 196:97] - wire [2:0] _T_154 = _T_152 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 196:67] - wire [2:0] _T_155 = ahb_hresp_q ? 3'h7 : _T_154; // @[axi4_to_ahb.scala 196:26] - wire [2:0] _T_293 = _T_51 ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 241:99] - wire [2:0] _T_294 = master_valid ? _T_293 : 3'h0; // @[axi4_to_ahb.scala 241:65] - wire [2:0] _T_295 = ahb_hresp_q ? 3'h5 : _T_294; // @[axi4_to_ahb.scala 241:26] - wire [2:0] _GEN_5 = _T_281 ? _T_295 : 3'h0; // @[Conditional.scala 39:67] - wire [2:0] _GEN_18 = _T_188 ? 3'h4 : _GEN_5; // @[Conditional.scala 39:67] - wire [2:0] _GEN_34 = _T_186 ? 3'h5 : _GEN_18; // @[Conditional.scala 39:67] - wire [2:0] _GEN_50 = _T_175 ? 3'h3 : _GEN_34; // @[Conditional.scala 39:67] - wire [2:0] _GEN_68 = _T_136 ? _T_155 : _GEN_50; // @[Conditional.scala 39:67] - wire [2:0] _GEN_82 = _T_101 ? _T_106 : _GEN_68; // @[Conditional.scala 39:67] - wire [2:0] buf_nxtstate = _T_49 ? _T_53 : _GEN_82; // @[Conditional.scala 40:58] - reg [31:0] wrbuf_addr; // @[lib.scala 374:16] - wire [31:0] master_addr = wr_cmd_vld ? wrbuf_addr : io_axi_ar_bits_addr; // @[axi4_to_ahb.scala 143:21] - reg [2:0] wrbuf_size; // @[Reg.scala 27:20] - wire [2:0] master_size = wr_cmd_vld ? wrbuf_size : io_axi_ar_bits_size; // @[axi4_to_ahb.scala 144:21] - reg [7:0] wrbuf_byteen; // @[Reg.scala 27:20] - reg [63:0] wrbuf_data; // @[lib.scala 374:16] - wire _T_358 = buf_nxtstate != 3'h5; // @[axi4_to_ahb.scala 251:55] - wire _T_359 = buf_state_en & _T_358; // @[axi4_to_ahb.scala 251:39] - wire _GEN_14 = _T_281 ? _T_359 : _T_440; // @[Conditional.scala 39:67] - wire _GEN_33 = _T_188 ? 1'h0 : _GEN_14; // @[Conditional.scala 39:67] - wire _GEN_49 = _T_186 ? 1'h0 : _GEN_33; // @[Conditional.scala 39:67] - wire _GEN_52 = _T_175 ? buf_state_en : _GEN_49; // @[Conditional.scala 39:67] - wire _GEN_73 = _T_136 ? _T_285 : _GEN_52; // @[Conditional.scala 39:67] - wire _GEN_94 = _T_101 ? 1'h0 : _GEN_73; // @[Conditional.scala 39:67] - wire slave_valid_pre = _T_49 ? 1'h0 : _GEN_94; // @[Conditional.scala 40:58] - wire buf_clk = rvclkhdr_6_io_l1clk; // @[axi4_to_ahb.scala 118:21 axi4_to_ahb.scala 332:12] - reg slvbuf_write; // @[Reg.scala 27:20] - wire [1:0] _T_596 = slvbuf_write ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 285:23] - reg slvbuf_error; // @[Reg.scala 27:20] - wire [1:0] _T_598 = slvbuf_error ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_599 = _T_598 & 2'h2; // @[axi4_to_ahb.scala 285:88] - wire [3:0] slave_opc = {_T_596,_T_599}; // @[Cat.scala 29:58] - wire [1:0] _T_30 = slave_opc[1] ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 150:55] - wire _T_35 = slave_opc[3:2] == 2'h0; // @[axi4_to_ahb.scala 153:66] - reg [31:0] last_bus_addr; // @[Reg.scala 27:20] - wire [63:0] _T_603 = {last_bus_addr,last_bus_addr}; // @[Cat.scala 29:58] - wire _T_604 = buf_state == 3'h5; // @[axi4_to_ahb.scala 286:91] - reg [63:0] buf_data; // @[lib.scala 374:16] - wire ahbm_data_clk = rvclkhdr_9_io_l1clk; // @[axi4_to_ahb.scala 26:27 axi4_to_ahb.scala 335:17] - reg [63:0] ahb_hrdata_q; // @[axi4_to_ahb.scala 325:57] - wire [63:0] _T_607 = _T_604 ? buf_data : ahb_hrdata_q; // @[axi4_to_ahb.scala 286:79] - wire _T_44 = io_axi_aw_valid & io_axi_aw_ready; // @[axi4_to_ahb.scala 160:57] - wire _T_45 = io_axi_w_valid & io_axi_w_ready; // @[axi4_to_ahb.scala 160:94] - wire _T_46 = _T_44 | _T_45; // @[axi4_to_ahb.scala 160:76] - wire _T_55 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 172:54] - wire _T_56 = buf_state_en & _T_55; // @[axi4_to_ahb.scala 172:38] - wire [2:0] _T_87 = wrbuf_byteen[6] ? 3'h6 : 3'h7; // @[Mux.scala 98:16] - wire [2:0] _T_88 = wrbuf_byteen[5] ? 3'h5 : _T_87; // @[Mux.scala 98:16] - wire [2:0] _T_89 = wrbuf_byteen[4] ? 3'h4 : _T_88; // @[Mux.scala 98:16] - wire [2:0] _T_90 = wrbuf_byteen[3] ? 3'h3 : _T_89; // @[Mux.scala 98:16] - wire [2:0] _T_91 = wrbuf_byteen[2] ? 3'h2 : _T_90; // @[Mux.scala 98:16] - wire [2:0] _T_92 = wrbuf_byteen[1] ? 3'h1 : _T_91; // @[Mux.scala 98:16] - wire [2:0] _T_93 = wrbuf_byteen[0] ? 3'h0 : _T_92; // @[Mux.scala 98:16] - wire [2:0] _T_95 = buf_write_in ? _T_93 : master_addr[2:0]; // @[axi4_to_ahb.scala 175:30] - wire _T_96 = buf_nxtstate == 3'h1; // @[axi4_to_ahb.scala 177:51] - wire _T_126 = master_ready & master_valid; // @[axi4_to_ahb.scala 188:33] - wire _T_162 = buf_nxtstate == 3'h6; // @[axi4_to_ahb.scala 203:64] - wire _T_163 = _T_126 & _T_162; // @[axi4_to_ahb.scala 203:48] - wire _T_164 = _T_163 & buf_state_en; // @[axi4_to_ahb.scala 203:79] - wire _T_349 = buf_state_en & buf_write_in; // @[axi4_to_ahb.scala 249:33] - wire _T_351 = _T_349 & _T_55; // @[axi4_to_ahb.scala 249:48] - wire _GEN_12 = _T_281 & _T_351; // @[Conditional.scala 39:67] - wire _GEN_32 = _T_188 ? 1'h0 : _GEN_12; // @[Conditional.scala 39:67] - wire _GEN_48 = _T_186 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67] - wire _GEN_65 = _T_175 ? 1'h0 : _GEN_48; // @[Conditional.scala 39:67] - wire _GEN_75 = _T_136 ? _T_164 : _GEN_65; // @[Conditional.scala 39:67] - wire _GEN_88 = _T_101 ? _T_126 : _GEN_75; // @[Conditional.scala 39:67] - wire bypass_en = _T_49 ? buf_state_en : _GEN_88; // @[Conditional.scala 40:58] - wire [1:0] _T_99 = bypass_en ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_100 = _T_99 & 2'h2; // @[axi4_to_ahb.scala 178:49] - wire _T_112 = ~master_valid; // @[axi4_to_ahb.scala 184:34] - wire _T_113 = buf_state_en & _T_112; // @[axi4_to_ahb.scala 184:32] - reg [31:0] buf_addr; // @[lib.scala 374:16] - wire [2:0] _T_130 = bypass_en ? master_addr[2:0] : buf_addr[2:0]; // @[axi4_to_ahb.scala 189:30] - wire _T_131 = ~buf_state_en; // @[axi4_to_ahb.scala 190:48] - wire _T_132 = _T_131 | bypass_en; // @[axi4_to_ahb.scala 190:62] - wire [1:0] _T_134 = _T_132 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_135 = 2'h2 & _T_134; // @[axi4_to_ahb.scala 190:36] - wire _T_169 = buf_nxtstate != 3'h6; // @[axi4_to_ahb.scala 205:63] - wire _T_170 = _T_169 & buf_state_en; // @[axi4_to_ahb.scala 205:78] - wire _T_171 = ~_T_170; // @[axi4_to_ahb.scala 205:47] - wire [1:0] _T_173 = _T_171 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_174 = 2'h2 & _T_173; // @[axi4_to_ahb.scala 205:36] - wire [1:0] _T_184 = _T_131 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_185 = 2'h2 & _T_184; // @[axi4_to_ahb.scala 215:41] - reg [2:0] buf_cmd_byte_ptrQ; // @[Reg.scala 27:20] - reg [7:0] buf_byteen; // @[Reg.scala 27:20] - wire [2:0] _T_197 = buf_cmd_byte_ptrQ + 3'h1; // @[axi4_to_ahb.scala 135:52] - wire _T_200 = 3'h0 >= _T_197; // @[axi4_to_ahb.scala 136:62] - wire _T_201 = buf_byteen[0] & _T_200; // @[axi4_to_ahb.scala 136:48] - wire _T_203 = 3'h1 >= _T_197; // @[axi4_to_ahb.scala 136:62] - wire _T_204 = buf_byteen[1] & _T_203; // @[axi4_to_ahb.scala 136:48] - wire _T_206 = 3'h2 >= _T_197; // @[axi4_to_ahb.scala 136:62] - wire _T_207 = buf_byteen[2] & _T_206; // @[axi4_to_ahb.scala 136:48] - wire _T_209 = 3'h3 >= _T_197; // @[axi4_to_ahb.scala 136:62] - wire _T_210 = buf_byteen[3] & _T_209; // @[axi4_to_ahb.scala 136:48] - wire _T_212 = 3'h4 >= _T_197; // @[axi4_to_ahb.scala 136:62] - wire _T_213 = buf_byteen[4] & _T_212; // @[axi4_to_ahb.scala 136:48] - wire _T_215 = 3'h5 >= _T_197; // @[axi4_to_ahb.scala 136:62] - wire _T_216 = buf_byteen[5] & _T_215; // @[axi4_to_ahb.scala 136:48] - wire _T_218 = 3'h6 >= _T_197; // @[axi4_to_ahb.scala 136:62] - wire _T_219 = buf_byteen[6] & _T_218; // @[axi4_to_ahb.scala 136:48] - wire [2:0] _T_224 = _T_219 ? 3'h6 : 3'h7; // @[Mux.scala 98:16] - wire [2:0] _T_225 = _T_216 ? 3'h5 : _T_224; // @[Mux.scala 98:16] - wire [2:0] _T_226 = _T_213 ? 3'h4 : _T_225; // @[Mux.scala 98:16] - wire [2:0] _T_227 = _T_210 ? 3'h3 : _T_226; // @[Mux.scala 98:16] - wire [2:0] _T_228 = _T_207 ? 3'h2 : _T_227; // @[Mux.scala 98:16] - wire [2:0] _T_229 = _T_204 ? 3'h1 : _T_228; // @[Mux.scala 98:16] - wire [2:0] _T_230 = _T_201 ? 3'h0 : _T_229; // @[Mux.scala 98:16] - wire [2:0] _T_231 = trxn_done ? _T_230 : buf_cmd_byte_ptrQ; // @[axi4_to_ahb.scala 233:30] - wire _T_232 = buf_cmd_byte_ptrQ == 3'h7; // @[axi4_to_ahb.scala 234:65] - reg buf_aligned; // @[Reg.scala 27:20] - wire _T_233 = buf_aligned | _T_232; // @[axi4_to_ahb.scala 234:44] - wire [7:0] _T_271 = buf_byteen >> _T_230; // @[axi4_to_ahb.scala 234:92] - wire _T_273 = ~_T_271[0]; // @[axi4_to_ahb.scala 234:163] - wire _T_274 = _T_233 | _T_273; // @[axi4_to_ahb.scala 234:79] - wire _T_275 = trxn_done & _T_274; // @[axi4_to_ahb.scala 234:29] - wire _T_346 = _T_232 | _T_273; // @[axi4_to_ahb.scala 248:38] - wire _T_347 = _T_109 & _T_346; // @[axi4_to_ahb.scala 247:80] - wire _T_348 = ahb_hresp_q | _T_347; // @[axi4_to_ahb.scala 247:34] - wire _GEN_11 = _T_281 & _T_348; // @[Conditional.scala 39:67] - wire _GEN_24 = _T_188 ? _T_275 : _GEN_11; // @[Conditional.scala 39:67] - wire _GEN_43 = _T_186 ? 1'h0 : _GEN_24; // @[Conditional.scala 39:67] - wire _GEN_61 = _T_175 ? 1'h0 : _GEN_43; // @[Conditional.scala 39:67] - wire _GEN_74 = _T_136 ? _T_113 : _GEN_61; // @[Conditional.scala 39:67] - wire _GEN_84 = _T_101 ? _T_113 : _GEN_74; // @[Conditional.scala 39:67] - wire cmd_done = _T_49 ? 1'h0 : _GEN_84; // @[Conditional.scala 40:58] - wire _T_276 = cmd_done | cmd_doneQ; // @[axi4_to_ahb.scala 235:47] - wire _T_277 = ~_T_276; // @[axi4_to_ahb.scala 235:36] - wire [1:0] _T_279 = _T_277 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_280 = _T_279 & 2'h2; // @[axi4_to_ahb.scala 235:61] - wire _T_300 = _T_55 | _T_96; // @[axi4_to_ahb.scala 245:62] - wire _T_301 = buf_state_en & _T_300; // @[axi4_to_ahb.scala 245:33] - wire _T_354 = _T_277 | bypass_en; // @[axi4_to_ahb.scala 250:61] - wire [1:0] _T_356 = _T_354 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_357 = _T_356 & 2'h2; // @[axi4_to_ahb.scala 250:75] - wire _T_364 = trxn_done | bypass_en; // @[axi4_to_ahb.scala 253:40] - wire [2:0] _T_439 = bypass_en ? _T_93 : _T_231; // @[axi4_to_ahb.scala 254:30] - wire _GEN_6 = _T_281 & ahb_hresp_q; // @[Conditional.scala 39:67] - wire _GEN_7 = _T_281 ? buf_state_en : _T_440; // @[Conditional.scala 39:67] - wire _GEN_9 = _T_281 & _T_301; // @[Conditional.scala 39:67] - wire _GEN_30 = _T_188 ? 1'h0 : _GEN_9; // @[Conditional.scala 39:67] - wire _GEN_47 = _T_186 ? 1'h0 : _GEN_30; // @[Conditional.scala 39:67] - wire _GEN_64 = _T_175 ? 1'h0 : _GEN_47; // @[Conditional.scala 39:67] - wire _GEN_67 = _T_136 ? _T_152 : _GEN_64; // @[Conditional.scala 39:67] - wire _GEN_87 = _T_101 ? master_ready : _GEN_67; // @[Conditional.scala 39:67] - wire buf_wr_en = _T_49 ? buf_state_en : _GEN_87; // @[Conditional.scala 40:58] - wire _GEN_10 = _T_281 & buf_wr_en; // @[Conditional.scala 39:67] - wire [1:0] _GEN_13 = _T_281 ? _T_357 : 2'h0; // @[Conditional.scala 39:67] - wire _GEN_16 = _T_281 & _T_364; // @[Conditional.scala 39:67] - wire [2:0] _GEN_17 = _T_281 ? _T_439 : 3'h0; // @[Conditional.scala 39:67] - wire _GEN_21 = _T_188 ? buf_state_en : _GEN_16; // @[Conditional.scala 39:67] - wire _GEN_22 = _T_188 & buf_state_en; // @[Conditional.scala 39:67] - wire [2:0] _GEN_23 = _T_188 ? _T_231 : _GEN_17; // @[Conditional.scala 39:67] - wire [1:0] _GEN_25 = _T_188 ? _T_280 : _GEN_13; // @[Conditional.scala 39:67] - wire _GEN_28 = _T_188 ? 1'h0 : _GEN_7; // @[Conditional.scala 39:67] - wire _GEN_31 = _T_188 ? 1'h0 : _GEN_10; // @[Conditional.scala 39:67] - wire _GEN_36 = _T_186 ? buf_state_en : _GEN_31; // @[Conditional.scala 39:67] - wire _GEN_38 = _T_186 ? buf_state_en : _GEN_28; // @[Conditional.scala 39:67] - wire _GEN_39 = _T_186 ? buf_state_en : _GEN_22; // @[Conditional.scala 39:67] - wire _GEN_41 = _T_186 ? 1'h0 : _GEN_21; // @[Conditional.scala 39:67] - wire [2:0] _GEN_42 = _T_186 ? 3'h0 : _GEN_23; // @[Conditional.scala 39:67] - wire [1:0] _GEN_44 = _T_186 ? 2'h0 : _GEN_25; // @[Conditional.scala 39:67] - wire _GEN_53 = _T_175 ? buf_state_en : _GEN_39; // @[Conditional.scala 39:67] - wire [2:0] _GEN_54 = _T_175 ? buf_addr[2:0] : _GEN_42; // @[Conditional.scala 39:67] - wire [1:0] _GEN_55 = _T_175 ? _T_185 : _GEN_44; // @[Conditional.scala 39:67] - wire _GEN_56 = _T_175 ? 1'h0 : _GEN_36; // @[Conditional.scala 39:67] - wire _GEN_58 = _T_175 ? 1'h0 : _GEN_38; // @[Conditional.scala 39:67] - wire _GEN_60 = _T_175 ? 1'h0 : _GEN_41; // @[Conditional.scala 39:67] - wire _GEN_70 = _T_136 ? buf_state_en : _GEN_56; // @[Conditional.scala 39:67] - wire _GEN_72 = _T_136 ? buf_state_en : _GEN_58; // @[Conditional.scala 39:67] - wire [2:0] _GEN_76 = _T_136 ? _T_130 : _GEN_54; // @[Conditional.scala 39:67] - wire [1:0] _GEN_77 = _T_136 ? _T_174 : _GEN_55; // @[Conditional.scala 39:67] - wire _GEN_78 = _T_136 ? buf_wr_en : _GEN_53; // @[Conditional.scala 39:67] - wire _GEN_80 = _T_136 ? 1'h0 : _GEN_60; // @[Conditional.scala 39:67] - wire _GEN_85 = _T_101 ? buf_state_en : _GEN_78; // @[Conditional.scala 39:67] - wire [2:0] _GEN_89 = _T_101 ? _T_130 : _GEN_76; // @[Conditional.scala 39:67] - wire [1:0] _GEN_90 = _T_101 ? _T_135 : _GEN_77; // @[Conditional.scala 39:67] - wire _GEN_91 = _T_101 ? 1'h0 : _GEN_70; // @[Conditional.scala 39:67] - wire _GEN_93 = _T_101 ? 1'h0 : _GEN_72; // @[Conditional.scala 39:67] - wire _GEN_96 = _T_101 ? 1'h0 : _GEN_80; // @[Conditional.scala 39:67] - wire buf_data_wr_en = _T_49 ? _T_56 : _GEN_91; // @[Conditional.scala 40:58] - wire buf_cmd_byte_ptr_en = _T_49 ? buf_state_en : _GEN_96; // @[Conditional.scala 40:58] - wire [2:0] buf_cmd_byte_ptr = _T_49 ? _T_95 : _GEN_89; // @[Conditional.scala 40:58] - wire slvbuf_wr_en = _T_49 ? 1'h0 : _GEN_85; // @[Conditional.scala 40:58] - wire slvbuf_error_en = _T_49 ? 1'h0 : _GEN_93; // @[Conditional.scala 40:58] - wire _T_535 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 271:24] - wire _T_536 = _T_103 | _T_535; // @[axi4_to_ahb.scala 270:48] - wire _T_538 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 271:54] - wire _T_539 = _T_536 | _T_538; // @[axi4_to_ahb.scala 271:33] - wire _T_541 = master_size[1:0] == 2'h2; // @[axi4_to_ahb.scala 271:93] - wire _T_542 = _T_539 | _T_541; // @[axi4_to_ahb.scala 271:72] - wire _T_544 = master_size[1:0] == 2'h3; // @[axi4_to_ahb.scala 272:25] - wire _T_546 = wrbuf_byteen == 8'h3; // @[axi4_to_ahb.scala 272:62] - wire _T_548 = wrbuf_byteen == 8'hc; // @[axi4_to_ahb.scala 272:97] - wire _T_549 = _T_546 | _T_548; // @[axi4_to_ahb.scala 272:74] - wire _T_551 = wrbuf_byteen == 8'h30; // @[axi4_to_ahb.scala 272:132] - wire _T_552 = _T_549 | _T_551; // @[axi4_to_ahb.scala 272:109] - wire _T_554 = wrbuf_byteen == 8'hc0; // @[axi4_to_ahb.scala 272:168] - wire _T_555 = _T_552 | _T_554; // @[axi4_to_ahb.scala 272:145] - wire _T_557 = wrbuf_byteen == 8'hf; // @[axi4_to_ahb.scala 273:28] - wire _T_558 = _T_555 | _T_557; // @[axi4_to_ahb.scala 272:181] - wire _T_560 = wrbuf_byteen == 8'hf0; // @[axi4_to_ahb.scala 273:63] - wire _T_561 = _T_558 | _T_560; // @[axi4_to_ahb.scala 273:40] - wire _T_563 = wrbuf_byteen == 8'hff; // @[axi4_to_ahb.scala 273:99] - wire _T_564 = _T_561 | _T_563; // @[axi4_to_ahb.scala 273:76] - wire _T_565 = _T_544 & _T_564; // @[axi4_to_ahb.scala 272:38] - wire buf_aligned_in = _T_542 | _T_565; // @[axi4_to_ahb.scala 271:106] - wire _T_444 = buf_aligned_in & _T_51; // @[axi4_to_ahb.scala 265:60] - wire [2:0] _T_461 = _T_548 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_462 = 3'h2 & _T_461; // @[axi4_to_ahb.scala 128:15] - wire _T_468 = _T_560 | _T_546; // @[axi4_to_ahb.scala 129:56] - wire [2:0] _T_470 = _T_468 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_471 = 3'h4 & _T_470; // @[axi4_to_ahb.scala 129:15] - wire [2:0] _T_472 = _T_462 | _T_471; // @[axi4_to_ahb.scala 128:63] - wire [2:0] _T_476 = _T_554 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_477 = 3'h6 & _T_476; // @[axi4_to_ahb.scala 130:15] - wire [2:0] _T_478 = _T_472 | _T_477; // @[axi4_to_ahb.scala 129:96] - wire [2:0] _T_485 = _T_444 ? _T_478 : master_addr[2:0]; // @[axi4_to_ahb.scala 265:43] - wire _T_489 = buf_state == 3'h3; // @[axi4_to_ahb.scala 268:33] - wire _T_495 = buf_aligned_in & _T_544; // @[axi4_to_ahb.scala 269:38] - wire _T_498 = _T_495 & _T_51; // @[axi4_to_ahb.scala 269:71] - wire [1:0] _T_504 = _T_563 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire _T_510 = _T_560 | _T_557; // @[axi4_to_ahb.scala 122:55] - wire [1:0] _T_512 = _T_510 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_513 = 2'h2 & _T_512; // @[axi4_to_ahb.scala 122:16] - wire [1:0] _T_514 = _T_504 | _T_513; // @[axi4_to_ahb.scala 121:64] - wire _T_519 = _T_554 | _T_551; // @[axi4_to_ahb.scala 123:60] - wire _T_522 = _T_519 | _T_548; // @[axi4_to_ahb.scala 123:89] - wire _T_525 = _T_522 | _T_546; // @[axi4_to_ahb.scala 123:123] - wire [1:0] _T_527 = _T_525 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_528 = 2'h1 & _T_527; // @[axi4_to_ahb.scala 123:21] - wire [1:0] _T_529 = _T_514 | _T_528; // @[axi4_to_ahb.scala 122:93] - wire [1:0] _T_531 = _T_498 ? _T_529 : master_size[1:0]; // @[axi4_to_ahb.scala 269:21] - wire [31:0] _T_570 = {master_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] - wire [31:0] _T_573 = {buf_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] - wire [1:0] _T_577 = buf_aligned_in ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [2:0] buf_size_in = {{1'd0}, _T_531}; // @[axi4_to_ahb.scala 269:15] - wire [1:0] _T_579 = _T_577 & buf_size_in[1:0]; // @[axi4_to_ahb.scala 276:81] - wire [2:0] _T_580 = {1'h0,_T_579}; // @[Cat.scala 29:58] - wire [1:0] _T_582 = buf_aligned ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - reg [1:0] buf_size; // @[Reg.scala 27:20] - wire [1:0] _T_584 = _T_582 & buf_size; // @[axi4_to_ahb.scala 276:138] - wire [2:0] _T_585 = {1'h0,_T_584}; // @[Cat.scala 29:58] - reg buf_write; // @[Reg.scala 27:20] - wire _T_611 = io_ahb_out_htrans != 2'h0; // @[axi4_to_ahb.scala 289:44] - wire _T_612 = _T_611 & io_ahb_in_hready; // @[axi4_to_ahb.scala 289:56] - wire last_addr_en = _T_612 & io_ahb_out_hwrite; // @[axi4_to_ahb.scala 289:75] - wire wrbuf_en = _T_44 & master_ready; // @[axi4_to_ahb.scala 291:49] - wire wrbuf_data_en = _T_45 & master_ready; // @[axi4_to_ahb.scala 292:52] - wire wrbuf_cmd_sent = _T_149 & _T_51; // @[axi4_to_ahb.scala 293:49] - wire _T_622 = ~wrbuf_en; // @[axi4_to_ahb.scala 294:33] - wire wrbuf_rst = wrbuf_cmd_sent & _T_622; // @[axi4_to_ahb.scala 294:31] - wire _T_624 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 296:36] - wire _T_625 = wrbuf_vld & _T_624; // @[axi4_to_ahb.scala 296:34] - wire _T_626 = ~_T_625; // @[axi4_to_ahb.scala 296:22] - wire _T_629 = wrbuf_data_vld & _T_624; // @[axi4_to_ahb.scala 297:38] - wire _T_630 = ~_T_629; // @[axi4_to_ahb.scala 297:21] - wire _T_633 = ~wr_cmd_vld; // @[axi4_to_ahb.scala 298:22] - wire _T_636 = wrbuf_en | wrbuf_vld; // @[axi4_to_ahb.scala 301:55] - wire _T_637 = ~wrbuf_rst; // @[axi4_to_ahb.scala 301:91] - wire _T_641 = wrbuf_data_en | wrbuf_data_vld; // @[axi4_to_ahb.scala 302:55] - wire _T_691 = ~slave_valid_pre; // @[axi4_to_ahb.scala 319:92] - wire _T_704 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 327:43] - wire _T_705 = _T_704 | io_clk_override; // @[axi4_to_ahb.scala 327:58] - wire _T_708 = io_ahb_in_hready & io_ahb_out_htrans[1]; // @[axi4_to_ahb.scala 328:57] - wire _T_709 = _T_708 | io_clk_override; // @[axi4_to_ahb.scala 328:81] - wire _T_711 = buf_state != 3'h0; // @[axi4_to_ahb.scala 329:50] - wire _T_712 = _T_711 | io_clk_override; // @[axi4_to_ahb.scala 329:60] - rvclkhdr rvclkhdr ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_io_l1clk), - .io_clk(rvclkhdr_io_clk), - .io_en(rvclkhdr_io_en), - .io_scan_mode(rvclkhdr_io_scan_mode) - ); - rvclkhdr rvclkhdr_1 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_1_io_l1clk), - .io_clk(rvclkhdr_1_io_clk), - .io_en(rvclkhdr_1_io_en), - .io_scan_mode(rvclkhdr_1_io_scan_mode) - ); - rvclkhdr rvclkhdr_2 ( // @[lib.scala 368:23] - .io_l1clk(rvclkhdr_2_io_l1clk), - .io_clk(rvclkhdr_2_io_clk), - .io_en(rvclkhdr_2_io_en), - .io_scan_mode(rvclkhdr_2_io_scan_mode) - ); - rvclkhdr rvclkhdr_3 ( // @[lib.scala 368:23] - .io_l1clk(rvclkhdr_3_io_l1clk), - .io_clk(rvclkhdr_3_io_clk), - .io_en(rvclkhdr_3_io_en), - .io_scan_mode(rvclkhdr_3_io_scan_mode) - ); - rvclkhdr rvclkhdr_4 ( // @[lib.scala 368:23] - .io_l1clk(rvclkhdr_4_io_l1clk), - .io_clk(rvclkhdr_4_io_clk), - .io_en(rvclkhdr_4_io_en), - .io_scan_mode(rvclkhdr_4_io_scan_mode) - ); - rvclkhdr rvclkhdr_5 ( // @[lib.scala 368:23] - .io_l1clk(rvclkhdr_5_io_l1clk), - .io_clk(rvclkhdr_5_io_clk), - .io_en(rvclkhdr_5_io_en), - .io_scan_mode(rvclkhdr_5_io_scan_mode) - ); - rvclkhdr rvclkhdr_6 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_6_io_l1clk), - .io_clk(rvclkhdr_6_io_clk), - .io_en(rvclkhdr_6_io_en), - .io_scan_mode(rvclkhdr_6_io_scan_mode) - ); - rvclkhdr rvclkhdr_7 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_7_io_l1clk), - .io_clk(rvclkhdr_7_io_clk), - .io_en(rvclkhdr_7_io_en), - .io_scan_mode(rvclkhdr_7_io_scan_mode) - ); - rvclkhdr rvclkhdr_8 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_8_io_l1clk), - .io_clk(rvclkhdr_8_io_clk), - .io_en(rvclkhdr_8_io_en), - .io_scan_mode(rvclkhdr_8_io_scan_mode) - ); - rvclkhdr rvclkhdr_9 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_9_io_l1clk), - .io_clk(rvclkhdr_9_io_clk), - .io_en(rvclkhdr_9_io_en), - .io_scan_mode(rvclkhdr_9_io_scan_mode) - ); - assign io_axi_aw_ready = _T_626 & master_ready; // @[axi4_to_ahb.scala 296:19] - assign io_axi_w_ready = _T_630 & master_ready; // @[axi4_to_ahb.scala 297:18] - assign io_axi_b_valid = slave_valid_pre & slave_opc[3]; // @[axi4_to_ahb.scala 149:18] - assign io_axi_b_bits_resp = slave_opc[0] ? 2'h2 : _T_30; // @[axi4_to_ahb.scala 150:22] - assign io_axi_ar_ready = _T_633 & master_ready; // @[axi4_to_ahb.scala 298:19] - assign io_axi_r_valid = slave_valid_pre & _T_35; // @[axi4_to_ahb.scala 153:18] - assign io_axi_r_bits_data = slvbuf_error ? _T_603 : _T_607; // @[axi4_to_ahb.scala 156:22] - assign io_axi_r_bits_resp = slave_opc[0] ? 2'h2 : _T_30; // @[axi4_to_ahb.scala 154:22] - assign io_ahb_out_haddr = bypass_en ? _T_570 : _T_573; // @[axi4_to_ahb.scala 275:20] - assign io_ahb_out_hsize = bypass_en ? _T_580 : _T_585; // @[axi4_to_ahb.scala 276:20] - assign io_ahb_out_htrans = _T_49 ? _T_100 : _GEN_90; // @[axi4_to_ahb.scala 22:21 axi4_to_ahb.scala 178:25 axi4_to_ahb.scala 190:25 axi4_to_ahb.scala 205:25 axi4_to_ahb.scala 215:25 axi4_to_ahb.scala 235:25 axi4_to_ahb.scala 250:25] - assign io_ahb_out_hwrite = bypass_en ? _T_51 : buf_write; // @[axi4_to_ahb.scala 281:21] - assign io_ahb_out_hwdata = buf_data; // @[axi4_to_ahb.scala 282:21] - assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_io_en = io_bus_clk_en; // @[lib.scala 345:16] - assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_1_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_1_io_en = io_bus_clk_en & _T_46; // @[lib.scala 345:16] - assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_2_io_clk = rvclkhdr_io_l1clk; // @[lib.scala 370:18] - assign rvclkhdr_2_io_en = _T_44 & master_ready; // @[lib.scala 371:17] - assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] - assign rvclkhdr_3_io_clk = rvclkhdr_io_l1clk; // @[lib.scala 370:18] - assign rvclkhdr_3_io_en = _T_45 & master_ready; // @[lib.scala 371:17] - assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] - assign rvclkhdr_4_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_4_io_en = buf_wr_en & io_bus_clk_en; // @[lib.scala 371:17] - assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] - assign rvclkhdr_5_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_5_io_en = buf_data_wr_en & io_bus_clk_en; // @[lib.scala 371:17] - assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] - assign rvclkhdr_6_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_6_io_en = io_bus_clk_en & _T_705; // @[lib.scala 345:16] - assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_7_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_7_io_en = io_bus_clk_en; // @[lib.scala 345:16] - assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_8_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_8_io_en = io_bus_clk_en & _T_709; // @[lib.scala 345:16] - assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_9_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_9_io_en = io_bus_clk_en & _T_712; // @[lib.scala 345:16] - assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] -`ifdef RANDOMIZE_GARBAGE_ASSIGN -`define RANDOMIZE -`endif -`ifdef RANDOMIZE_INVALID_ASSIGN -`define RANDOMIZE -`endif -`ifdef RANDOMIZE_REG_INIT -`define RANDOMIZE -`endif -`ifdef RANDOMIZE_MEM_INIT -`define RANDOMIZE -`endif -`ifndef RANDOM -`define RANDOM $random -`endif -`ifdef RANDOMIZE_MEM_INIT - integer initvar; -`endif -`ifndef SYNTHESIS -`ifdef FIRRTL_BEFORE_INITIAL -`FIRRTL_BEFORE_INITIAL -`endif -initial begin - `ifdef RANDOMIZE - `ifdef INIT_RANDOM - `INIT_RANDOM - `endif - `ifndef VERILATOR - `ifdef RANDOMIZE_DELAY - #`RANDOMIZE_DELAY begin end - `else - #0.002 begin end - `endif - `endif -`ifdef RANDOMIZE_REG_INIT - _RAND_0 = {1{`RANDOM}}; - buf_state = _RAND_0[2:0]; - _RAND_1 = {1{`RANDOM}}; - wrbuf_vld = _RAND_1[0:0]; - _RAND_2 = {1{`RANDOM}}; - wrbuf_data_vld = _RAND_2[0:0]; - _RAND_3 = {1{`RANDOM}}; - ahb_hready_q = _RAND_3[0:0]; - _RAND_4 = {1{`RANDOM}}; - ahb_htrans_q = _RAND_4[1:0]; - _RAND_5 = {1{`RANDOM}}; - ahb_hwrite_q = _RAND_5[0:0]; - _RAND_6 = {1{`RANDOM}}; - ahb_hresp_q = _RAND_6[0:0]; - _RAND_7 = {1{`RANDOM}}; - cmd_doneQ = _RAND_7[0:0]; - _RAND_8 = {1{`RANDOM}}; - wrbuf_addr = _RAND_8[31:0]; - _RAND_9 = {1{`RANDOM}}; - wrbuf_size = _RAND_9[2:0]; - _RAND_10 = {1{`RANDOM}}; - wrbuf_byteen = _RAND_10[7:0]; - _RAND_11 = {2{`RANDOM}}; - wrbuf_data = _RAND_11[63:0]; - _RAND_12 = {1{`RANDOM}}; - slvbuf_write = _RAND_12[0:0]; - _RAND_13 = {1{`RANDOM}}; - slvbuf_error = _RAND_13[0:0]; - _RAND_14 = {1{`RANDOM}}; - last_bus_addr = _RAND_14[31:0]; - _RAND_15 = {2{`RANDOM}}; - buf_data = _RAND_15[63:0]; - _RAND_16 = {2{`RANDOM}}; - ahb_hrdata_q = _RAND_16[63:0]; - _RAND_17 = {1{`RANDOM}}; - buf_addr = _RAND_17[31:0]; - _RAND_18 = {1{`RANDOM}}; - buf_cmd_byte_ptrQ = _RAND_18[2:0]; - _RAND_19 = {1{`RANDOM}}; - buf_byteen = _RAND_19[7:0]; - _RAND_20 = {1{`RANDOM}}; - buf_aligned = _RAND_20[0:0]; - _RAND_21 = {1{`RANDOM}}; - buf_size = _RAND_21[1:0]; - _RAND_22 = {1{`RANDOM}}; - buf_write = _RAND_22[0:0]; -`endif // RANDOMIZE_REG_INIT - if (reset) begin - buf_state = 3'h0; - end - if (reset) begin - wrbuf_vld = 1'h0; - end - if (reset) begin - wrbuf_data_vld = 1'h0; - end - if (reset) begin - ahb_hready_q = 1'h0; - end - if (reset) begin - ahb_htrans_q = 2'h0; - end - if (reset) begin - ahb_hwrite_q = 1'h0; - end - if (reset) begin - ahb_hresp_q = 1'h0; - end - if (reset) begin - cmd_doneQ = 1'h0; - end - if (reset) begin - wrbuf_addr = 32'h0; - end - if (reset) begin - wrbuf_size = 3'h0; - end - if (reset) begin - wrbuf_byteen = 8'h0; - end - if (reset) begin - wrbuf_data = 64'h0; - end - if (reset) begin - slvbuf_write = 1'h0; - end - if (reset) begin - slvbuf_error = 1'h0; - end - if (reset) begin - last_bus_addr = 32'h0; - end - if (reset) begin - buf_data = 64'h0; - end - if (reset) begin - ahb_hrdata_q = 64'h0; - end - if (reset) begin - buf_addr = 32'h0; - end - if (reset) begin - buf_cmd_byte_ptrQ = 3'h0; - end - if (reset) begin - buf_byteen = 8'h0; - end - if (reset) begin - buf_aligned = 1'h0; - end - if (reset) begin - buf_size = 2'h0; - end - if (reset) begin - buf_write = 1'h0; - end - `endif // RANDOMIZE -end // initial -`ifdef FIRRTL_AFTER_INITIAL -`FIRRTL_AFTER_INITIAL -`endif -`endif // SYNTHESIS - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - buf_state <= 3'h0; - end else if (buf_state_en) begin - if (_T_49) begin - if (buf_write_in) begin - buf_state <= 3'h2; - end else begin - buf_state <= 3'h1; - end - end else if (_T_101) begin - if (_T_104) begin - buf_state <= 3'h6; - end else begin - buf_state <= 3'h3; - end - end else if (_T_136) begin - if (ahb_hresp_q) begin - buf_state <= 3'h7; - end else if (_T_152) begin - buf_state <= 3'h6; - end else begin - buf_state <= 3'h3; - end - end else if (_T_175) begin - buf_state <= 3'h3; - end else if (_T_186) begin - buf_state <= 3'h5; - end else if (_T_188) begin - buf_state <= 3'h4; - end else if (_T_281) begin - if (ahb_hresp_q) begin - buf_state <= 3'h5; - end else if (master_valid) begin - if (_T_51) begin - buf_state <= 3'h2; - end else begin - buf_state <= 3'h1; - end - end else begin - buf_state <= 3'h0; - end - end else begin - buf_state <= 3'h0; - end - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - wrbuf_vld <= 1'h0; - end else begin - wrbuf_vld <= _T_636 & _T_637; - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - wrbuf_data_vld <= 1'h0; - end else begin - wrbuf_data_vld <= _T_641 & _T_637; - end - end - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - ahb_hready_q <= 1'h0; - end else begin - ahb_hready_q <= io_ahb_in_hready; - end - end - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - ahb_htrans_q <= 2'h0; - end else begin - ahb_htrans_q <= io_ahb_out_htrans; - end - end - always @(posedge ahbm_addr_clk or posedge reset) begin - if (reset) begin - ahb_hwrite_q <= 1'h0; - end else begin - ahb_hwrite_q <= io_ahb_out_hwrite; - end - end - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - ahb_hresp_q <= 1'h0; - end else begin - ahb_hresp_q <= io_ahb_in_hresp; - end - end - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - cmd_doneQ <= 1'h0; - end else begin - cmd_doneQ <= _T_276 & _T_691; - end - end - always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin - if (reset) begin - wrbuf_addr <= 32'h0; - end else begin - wrbuf_addr <= io_axi_aw_bits_addr; - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - wrbuf_size <= 3'h0; - end else if (wrbuf_en) begin - wrbuf_size <= io_axi_aw_bits_size; - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - wrbuf_byteen <= 8'h0; - end else if (wrbuf_data_en) begin - wrbuf_byteen <= io_axi_w_bits_strb; - end - end - always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin - if (reset) begin - wrbuf_data <= 64'h0; - end else begin - wrbuf_data <= io_axi_w_bits_data; - end - end - always @(posedge buf_clk or posedge reset) begin - if (reset) begin - slvbuf_write <= 1'h0; - end else if (slvbuf_wr_en) begin - slvbuf_write <= buf_write; - end - end - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - slvbuf_error <= 1'h0; - end else if (slvbuf_error_en) begin - if (_T_49) begin - slvbuf_error <= 1'h0; - end else if (_T_101) begin - slvbuf_error <= 1'h0; - end else if (_T_136) begin - slvbuf_error <= ahb_hresp_q; - end else if (_T_175) begin - slvbuf_error <= 1'h0; - end else if (_T_186) begin - slvbuf_error <= ahb_hresp_q; - end else if (_T_188) begin - slvbuf_error <= 1'h0; - end else begin - slvbuf_error <= _GEN_6; - end - end - end - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - last_bus_addr <= 32'h0; - end else if (last_addr_en) begin - last_bus_addr <= io_ahb_out_haddr; - end - end - always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin - if (reset) begin - buf_data <= 64'h0; - end else if (_T_489) begin - buf_data <= ahb_hrdata_q; - end else begin - buf_data <= wrbuf_data; - end - end - always @(posedge ahbm_data_clk or posedge reset) begin - if (reset) begin - ahb_hrdata_q <= 64'h0; - end else begin - ahb_hrdata_q <= io_ahb_in_hrdata; - end - end - always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin - if (reset) begin - buf_addr <= 32'h0; - end else begin - buf_addr <= {master_addr[31:3],_T_485}; - end - end - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - buf_cmd_byte_ptrQ <= 3'h0; - end else if (buf_cmd_byte_ptr_en) begin - if (_T_49) begin - if (buf_write_in) begin - if (wrbuf_byteen[0]) begin - buf_cmd_byte_ptrQ <= 3'h0; - end else if (wrbuf_byteen[1]) begin - buf_cmd_byte_ptrQ <= 3'h1; - end else if (wrbuf_byteen[2]) begin - buf_cmd_byte_ptrQ <= 3'h2; - end else if (wrbuf_byteen[3]) begin - buf_cmd_byte_ptrQ <= 3'h3; - end else if (wrbuf_byteen[4]) begin - buf_cmd_byte_ptrQ <= 3'h4; - end else if (wrbuf_byteen[5]) begin - buf_cmd_byte_ptrQ <= 3'h5; - end else if (wrbuf_byteen[6]) begin - buf_cmd_byte_ptrQ <= 3'h6; - end else begin - buf_cmd_byte_ptrQ <= 3'h7; - end - end else begin - buf_cmd_byte_ptrQ <= master_addr[2:0]; - end - end else if (_T_101) begin - if (bypass_en) begin - buf_cmd_byte_ptrQ <= master_addr[2:0]; - end else begin - buf_cmd_byte_ptrQ <= buf_addr[2:0]; - end - end else if (_T_136) begin - if (bypass_en) begin - buf_cmd_byte_ptrQ <= master_addr[2:0]; - end else begin - buf_cmd_byte_ptrQ <= buf_addr[2:0]; - end - end else if (_T_175) begin - buf_cmd_byte_ptrQ <= buf_addr[2:0]; - end else if (_T_186) begin - buf_cmd_byte_ptrQ <= 3'h0; - end else if (_T_188) begin - if (trxn_done) begin - if (_T_201) begin - buf_cmd_byte_ptrQ <= 3'h0; - end else if (_T_204) begin - buf_cmd_byte_ptrQ <= 3'h1; - end else if (_T_207) begin - buf_cmd_byte_ptrQ <= 3'h2; - end else if (_T_210) begin - buf_cmd_byte_ptrQ <= 3'h3; - end else if (_T_213) begin - buf_cmd_byte_ptrQ <= 3'h4; - end else if (_T_216) begin - buf_cmd_byte_ptrQ <= 3'h5; - end else if (_T_219) begin - buf_cmd_byte_ptrQ <= 3'h6; - end else begin - buf_cmd_byte_ptrQ <= 3'h7; - end - end - end else if (_T_281) begin - if (bypass_en) begin - if (wrbuf_byteen[0]) begin - buf_cmd_byte_ptrQ <= 3'h0; - end else if (wrbuf_byteen[1]) begin - buf_cmd_byte_ptrQ <= 3'h1; - end else if (wrbuf_byteen[2]) begin - buf_cmd_byte_ptrQ <= 3'h2; - end else if (wrbuf_byteen[3]) begin - buf_cmd_byte_ptrQ <= 3'h3; - end else if (wrbuf_byteen[4]) begin - buf_cmd_byte_ptrQ <= 3'h4; - end else if (wrbuf_byteen[5]) begin - buf_cmd_byte_ptrQ <= 3'h5; - end else if (wrbuf_byteen[6]) begin - buf_cmd_byte_ptrQ <= 3'h6; - end else begin - buf_cmd_byte_ptrQ <= 3'h7; - end - end else if (trxn_done) begin - if (_T_201) begin - buf_cmd_byte_ptrQ <= 3'h0; - end else if (_T_204) begin - buf_cmd_byte_ptrQ <= 3'h1; - end else if (_T_207) begin - buf_cmd_byte_ptrQ <= 3'h2; - end else if (_T_210) begin - buf_cmd_byte_ptrQ <= 3'h3; - end else if (_T_213) begin - buf_cmd_byte_ptrQ <= 3'h4; - end else if (_T_216) begin - buf_cmd_byte_ptrQ <= 3'h5; - end else if (_T_219) begin - buf_cmd_byte_ptrQ <= 3'h6; - end else begin - buf_cmd_byte_ptrQ <= 3'h7; - end - end - end else begin - buf_cmd_byte_ptrQ <= 3'h0; - end - end - end - always @(posedge buf_clk or posedge reset) begin - if (reset) begin - buf_byteen <= 8'h0; - end else if (buf_wr_en) begin - buf_byteen <= wrbuf_byteen; - end - end - always @(posedge buf_clk or posedge reset) begin - if (reset) begin - buf_aligned <= 1'h0; - end else if (buf_wr_en) begin - buf_aligned <= buf_aligned_in; - end - end - always @(posedge buf_clk or posedge reset) begin - if (reset) begin - buf_size <= 2'h0; - end else if (buf_wr_en) begin - buf_size <= buf_size_in[1:0]; - end - end - always @(posedge buf_clk or posedge reset) begin - if (reset) begin - buf_write <= 1'h0; - end else if (buf_wr_en) begin - if (_T_49) begin - buf_write <= _T_51; - end else if (_T_101) begin - buf_write <= 1'h0; - end else if (_T_136) begin - buf_write <= 1'h0; - end else if (_T_175) begin - buf_write <= 1'h0; - end else if (_T_186) begin - buf_write <= 1'h0; - end else if (_T_188) begin - buf_write <= 1'h0; - end else begin - buf_write <= _GEN_8; - end - end - end -endmodule -module axi4_to_ahb_1( - input clock, - input reset, - input io_scan_mode, - input io_bus_clk_en, - input io_clk_override, - output io_axi_aw_ready, - input io_axi_aw_valid, - input [2:0] io_axi_aw_bits_id, - input [31:0] io_axi_aw_bits_addr, - input [2:0] io_axi_aw_bits_size, - output io_axi_w_ready, - input io_axi_w_valid, - input [63:0] io_axi_w_bits_data, - input [7:0] io_axi_w_bits_strb, - output io_axi_b_valid, - output [2:0] io_axi_b_bits_id, - output io_axi_ar_ready, - input io_axi_ar_valid, - input [2:0] io_axi_ar_bits_id, - input [31:0] io_axi_ar_bits_addr, - input [2:0] io_axi_ar_bits_size, - output io_axi_r_valid, - output [2:0] io_axi_r_bits_id, - output [63:0] io_axi_r_bits_data, - output [1:0] io_axi_r_bits_resp, - input [63:0] io_ahb_in_hrdata, - input io_ahb_in_hready, - input io_ahb_in_hresp, - output [31:0] io_ahb_out_haddr, - output [2:0] io_ahb_out_hsize, - output [1:0] io_ahb_out_htrans, - output io_ahb_out_hwrite, - output [63:0] io_ahb_out_hwdata -); -`ifdef RANDOMIZE_REG_INIT - reg [31:0] _RAND_0; - reg [31:0] _RAND_1; - reg [31:0] _RAND_2; - reg [31:0] _RAND_3; - reg [31:0] _RAND_4; - reg [31:0] _RAND_5; - reg [31:0] _RAND_6; - reg [31:0] _RAND_7; - reg [31:0] _RAND_8; - reg [31:0] _RAND_9; - reg [31:0] _RAND_10; - reg [31:0] _RAND_11; - reg [63:0] _RAND_12; - reg [31:0] _RAND_13; - reg [31:0] _RAND_14; - reg [31:0] _RAND_15; - reg [31:0] _RAND_16; - reg [63:0] _RAND_17; - reg [63:0] _RAND_18; - reg [31:0] _RAND_19; - reg [31:0] _RAND_20; - reg [31:0] _RAND_21; - reg [31:0] _RAND_22; - reg [31:0] _RAND_23; - reg [31:0] _RAND_24; - reg [31:0] _RAND_25; -`endif // RANDOMIZE_REG_INIT - wire rvclkhdr_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_io_en; // @[lib.scala 343:22] - wire rvclkhdr_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_1_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_1_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_1_io_en; // @[lib.scala 343:22] - wire rvclkhdr_1_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_2_io_l1clk; // @[lib.scala 368:23] - wire rvclkhdr_2_io_clk; // @[lib.scala 368:23] - wire rvclkhdr_2_io_en; // @[lib.scala 368:23] - wire rvclkhdr_2_io_scan_mode; // @[lib.scala 368:23] - wire rvclkhdr_3_io_l1clk; // @[lib.scala 368:23] - wire rvclkhdr_3_io_clk; // @[lib.scala 368:23] - wire rvclkhdr_3_io_en; // @[lib.scala 368:23] - wire rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23] - wire rvclkhdr_4_io_l1clk; // @[lib.scala 368:23] - wire rvclkhdr_4_io_clk; // @[lib.scala 368:23] - wire rvclkhdr_4_io_en; // @[lib.scala 368:23] - wire rvclkhdr_4_io_scan_mode; // @[lib.scala 368:23] - wire rvclkhdr_5_io_l1clk; // @[lib.scala 368:23] - wire rvclkhdr_5_io_clk; // @[lib.scala 368:23] - wire rvclkhdr_5_io_en; // @[lib.scala 368:23] - wire rvclkhdr_5_io_scan_mode; // @[lib.scala 368:23] - wire rvclkhdr_6_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_6_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_6_io_en; // @[lib.scala 343:22] - wire rvclkhdr_6_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_7_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_7_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_7_io_en; // @[lib.scala 343:22] - wire rvclkhdr_7_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_8_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_8_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_8_io_en; // @[lib.scala 343:22] - wire rvclkhdr_8_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_9_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_9_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_9_io_en; // @[lib.scala 343:22] - wire rvclkhdr_9_io_scan_mode; // @[lib.scala 343:22] - wire ahbm_clk = rvclkhdr_7_io_l1clk; // @[axi4_to_ahb.scala 24:22 axi4_to_ahb.scala 333:12] - reg [2:0] buf_state; // @[axi4_to_ahb.scala 30:45] - wire _T_49 = 3'h0 == buf_state; // @[Conditional.scala 37:30] - wire bus_clk = rvclkhdr_io_l1clk; // @[axi4_to_ahb.scala 50:21 axi4_to_ahb.scala 162:11] - reg wrbuf_vld; // @[axi4_to_ahb.scala 301:51] - reg wrbuf_data_vld; // @[axi4_to_ahb.scala 302:51] - wire wr_cmd_vld = wrbuf_vld & wrbuf_data_vld; // @[axi4_to_ahb.scala 139:27] - wire master_valid = wr_cmd_vld | io_axi_ar_valid; // @[axi4_to_ahb.scala 140:30] - wire _T_101 = 3'h1 == buf_state; // @[Conditional.scala 37:30] - reg ahb_hready_q; // @[axi4_to_ahb.scala 321:52] - reg [1:0] ahb_htrans_q; // @[axi4_to_ahb.scala 322:52] - wire _T_108 = ahb_htrans_q != 2'h0; // @[axi4_to_ahb.scala 183:58] - wire _T_109 = ahb_hready_q & _T_108; // @[axi4_to_ahb.scala 183:36] - wire ahbm_addr_clk = rvclkhdr_8_io_l1clk; // @[axi4_to_ahb.scala 25:27 axi4_to_ahb.scala 334:17] - reg ahb_hwrite_q; // @[axi4_to_ahb.scala 323:57] - wire _T_110 = ~ahb_hwrite_q; // @[axi4_to_ahb.scala 183:72] - wire _T_111 = _T_109 & _T_110; // @[axi4_to_ahb.scala 183:70] - wire _T_136 = 3'h6 == buf_state; // @[Conditional.scala 37:30] - reg ahb_hresp_q; // @[axi4_to_ahb.scala 324:52] - wire _T_156 = ahb_hready_q | ahb_hresp_q; // @[axi4_to_ahb.scala 197:37] - wire _T_175 = 3'h7 == buf_state; // @[Conditional.scala 37:30] - wire _T_186 = 3'h3 == buf_state; // @[Conditional.scala 37:30] - wire _T_188 = 3'h2 == buf_state; // @[Conditional.scala 37:30] - wire _T_189 = ahb_hready_q & ahb_hwrite_q; // @[axi4_to_ahb.scala 229:33] - wire _T_192 = _T_189 & _T_108; // @[axi4_to_ahb.scala 229:48] - wire _T_281 = 3'h4 == buf_state; // @[Conditional.scala 37:30] - wire _GEN_15 = _T_281 & _T_192; // @[Conditional.scala 39:67] - wire _GEN_19 = _T_188 ? _T_192 : _GEN_15; // @[Conditional.scala 39:67] - wire _GEN_40 = _T_186 ? 1'h0 : _GEN_19; // @[Conditional.scala 39:67] - wire _GEN_59 = _T_175 ? 1'h0 : _GEN_40; // @[Conditional.scala 39:67] - wire _GEN_79 = _T_136 ? 1'h0 : _GEN_59; // @[Conditional.scala 39:67] - wire _GEN_95 = _T_101 ? 1'h0 : _GEN_79; // @[Conditional.scala 39:67] - wire trxn_done = _T_49 ? 1'h0 : _GEN_95; // @[Conditional.scala 40:58] - reg cmd_doneQ; // @[axi4_to_ahb.scala 319:52] - wire _T_282 = cmd_doneQ & ahb_hready_q; // @[axi4_to_ahb.scala 239:34] - wire _T_283 = _T_282 | ahb_hresp_q; // @[axi4_to_ahb.scala 239:50] - wire _T_440 = 3'h5 == buf_state; // @[Conditional.scala 37:30] - wire _GEN_3 = _T_281 ? _T_283 : _T_440; // @[Conditional.scala 39:67] - wire _GEN_20 = _T_188 ? trxn_done : _GEN_3; // @[Conditional.scala 39:67] - wire _GEN_35 = _T_186 ? _T_156 : _GEN_20; // @[Conditional.scala 39:67] - wire _GEN_51 = _T_175 ? _T_111 : _GEN_35; // @[Conditional.scala 39:67] - wire _GEN_69 = _T_136 ? _T_156 : _GEN_51; // @[Conditional.scala 39:67] - wire _GEN_83 = _T_101 ? _T_111 : _GEN_69; // @[Conditional.scala 39:67] - wire buf_state_en = _T_49 ? master_valid : _GEN_83; // @[Conditional.scala 40:58] - wire [1:0] _T_14 = wr_cmd_vld ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 142:20] - wire [2:0] master_opc = {{1'd0}, _T_14}; // @[axi4_to_ahb.scala 142:14] - wire _T_51 = master_opc[2:1] == 2'h1; // @[axi4_to_ahb.scala 168:41] - wire _GEN_8 = _T_281 & _T_51; // @[Conditional.scala 39:67] - wire _GEN_29 = _T_188 ? 1'h0 : _GEN_8; // @[Conditional.scala 39:67] - wire _GEN_46 = _T_186 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67] - wire _GEN_63 = _T_175 ? 1'h0 : _GEN_46; // @[Conditional.scala 39:67] - wire _GEN_81 = _T_136 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67] - wire _GEN_97 = _T_101 ? 1'h0 : _GEN_81; // @[Conditional.scala 39:67] - wire buf_write_in = _T_49 ? _T_51 : _GEN_97; // @[Conditional.scala 40:58] - wire [2:0] _T_53 = buf_write_in ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 169:26] - wire _T_103 = master_opc == 3'h0; // @[axi4_to_ahb.scala 182:61] - wire _T_104 = master_valid & _T_103; // @[axi4_to_ahb.scala 182:41] - wire [2:0] _T_106 = _T_104 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 182:26] - wire _T_124 = _T_106 == 3'h6; // @[axi4_to_ahb.scala 186:174] - wire _T_125 = _T_111 & _T_124; // @[axi4_to_ahb.scala 186:88] - wire _T_137 = ~ahb_hresp_q; // @[axi4_to_ahb.scala 194:39] - wire _T_138 = ahb_hready_q & _T_137; // @[axi4_to_ahb.scala 194:37] - wire _T_141 = master_valid & _T_51; // @[axi4_to_ahb.scala 194:70] - wire _T_142 = ~_T_141; // @[axi4_to_ahb.scala 194:55] - wire _T_143 = _T_138 & _T_142; // @[axi4_to_ahb.scala 194:53] - wire _T_285 = buf_state_en & _T_137; // @[axi4_to_ahb.scala 240:36] - wire _GEN_4 = _T_281 & _T_285; // @[Conditional.scala 39:67] - wire _GEN_26 = _T_188 ? 1'h0 : _GEN_4; // @[Conditional.scala 39:67] - wire _GEN_45 = _T_186 ? 1'h0 : _GEN_26; // @[Conditional.scala 39:67] - wire _GEN_62 = _T_175 ? 1'h0 : _GEN_45; // @[Conditional.scala 39:67] - wire _GEN_66 = _T_136 ? _T_143 : _GEN_62; // @[Conditional.scala 39:67] - wire _GEN_86 = _T_101 ? _T_125 : _GEN_66; // @[Conditional.scala 39:67] - wire master_ready = _T_49 | _GEN_86; // @[Conditional.scala 40:58] - wire _T_149 = master_valid & master_ready; // @[axi4_to_ahb.scala 196:82] - wire _T_152 = _T_149 & _T_103; // @[axi4_to_ahb.scala 196:97] - wire [2:0] _T_154 = _T_152 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 196:67] - wire [2:0] _T_155 = ahb_hresp_q ? 3'h7 : _T_154; // @[axi4_to_ahb.scala 196:26] - wire [2:0] _T_293 = _T_51 ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 241:99] - wire [2:0] _T_294 = master_valid ? _T_293 : 3'h0; // @[axi4_to_ahb.scala 241:65] - wire [2:0] _T_295 = ahb_hresp_q ? 3'h5 : _T_294; // @[axi4_to_ahb.scala 241:26] - wire [2:0] _GEN_5 = _T_281 ? _T_295 : 3'h0; // @[Conditional.scala 39:67] - wire [2:0] _GEN_18 = _T_188 ? 3'h4 : _GEN_5; // @[Conditional.scala 39:67] - wire [2:0] _GEN_34 = _T_186 ? 3'h5 : _GEN_18; // @[Conditional.scala 39:67] - wire [2:0] _GEN_50 = _T_175 ? 3'h3 : _GEN_34; // @[Conditional.scala 39:67] - wire [2:0] _GEN_68 = _T_136 ? _T_155 : _GEN_50; // @[Conditional.scala 39:67] - wire [2:0] _GEN_82 = _T_101 ? _T_106 : _GEN_68; // @[Conditional.scala 39:67] - wire [2:0] buf_nxtstate = _T_49 ? _T_53 : _GEN_82; // @[Conditional.scala 40:58] - reg [2:0] wrbuf_tag; // @[Reg.scala 27:20] - reg [31:0] wrbuf_addr; // @[lib.scala 374:16] - wire [31:0] master_addr = wr_cmd_vld ? wrbuf_addr : io_axi_ar_bits_addr; // @[axi4_to_ahb.scala 143:21] - reg [2:0] wrbuf_size; // @[Reg.scala 27:20] - wire [2:0] master_size = wr_cmd_vld ? wrbuf_size : io_axi_ar_bits_size; // @[axi4_to_ahb.scala 144:21] - reg [7:0] wrbuf_byteen; // @[Reg.scala 27:20] - reg [63:0] wrbuf_data; // @[lib.scala 374:16] - wire _T_358 = buf_nxtstate != 3'h5; // @[axi4_to_ahb.scala 251:55] - wire _T_359 = buf_state_en & _T_358; // @[axi4_to_ahb.scala 251:39] - wire _GEN_14 = _T_281 ? _T_359 : _T_440; // @[Conditional.scala 39:67] - wire _GEN_33 = _T_188 ? 1'h0 : _GEN_14; // @[Conditional.scala 39:67] - wire _GEN_49 = _T_186 ? 1'h0 : _GEN_33; // @[Conditional.scala 39:67] - wire _GEN_52 = _T_175 ? buf_state_en : _GEN_49; // @[Conditional.scala 39:67] - wire _GEN_73 = _T_136 ? _T_285 : _GEN_52; // @[Conditional.scala 39:67] - wire _GEN_94 = _T_101 ? 1'h0 : _GEN_73; // @[Conditional.scala 39:67] - wire slave_valid_pre = _T_49 ? 1'h0 : _GEN_94; // @[Conditional.scala 40:58] - wire buf_clk = rvclkhdr_6_io_l1clk; // @[axi4_to_ahb.scala 118:21 axi4_to_ahb.scala 332:12] - reg slvbuf_write; // @[Reg.scala 27:20] - wire [1:0] _T_596 = slvbuf_write ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 285:23] - reg slvbuf_error; // @[Reg.scala 27:20] - wire [1:0] _T_598 = slvbuf_error ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_599 = _T_598 & 2'h2; // @[axi4_to_ahb.scala 285:88] - wire [3:0] slave_opc = {_T_596,_T_599}; // @[Cat.scala 29:58] - wire [1:0] _T_30 = slave_opc[1] ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 150:55] - reg [2:0] slvbuf_tag; // @[Reg.scala 27:20] - wire _T_35 = slave_opc[3:2] == 2'h0; // @[axi4_to_ahb.scala 153:66] - reg [31:0] last_bus_addr; // @[Reg.scala 27:20] - wire [63:0] _T_603 = {last_bus_addr,last_bus_addr}; // @[Cat.scala 29:58] - wire _T_604 = buf_state == 3'h5; // @[axi4_to_ahb.scala 286:91] - reg [63:0] buf_data; // @[lib.scala 374:16] - wire ahbm_data_clk = rvclkhdr_9_io_l1clk; // @[axi4_to_ahb.scala 26:27 axi4_to_ahb.scala 335:17] - reg [63:0] ahb_hrdata_q; // @[axi4_to_ahb.scala 325:57] - wire [63:0] _T_607 = _T_604 ? buf_data : ahb_hrdata_q; // @[axi4_to_ahb.scala 286:79] - wire _T_44 = io_axi_aw_valid & io_axi_aw_ready; // @[axi4_to_ahb.scala 160:57] - wire _T_45 = io_axi_w_valid & io_axi_w_ready; // @[axi4_to_ahb.scala 160:94] - wire _T_46 = _T_44 | _T_45; // @[axi4_to_ahb.scala 160:76] - wire _T_55 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 172:54] - wire _T_56 = buf_state_en & _T_55; // @[axi4_to_ahb.scala 172:38] - wire [2:0] _T_87 = wrbuf_byteen[6] ? 3'h6 : 3'h7; // @[Mux.scala 98:16] - wire [2:0] _T_88 = wrbuf_byteen[5] ? 3'h5 : _T_87; // @[Mux.scala 98:16] - wire [2:0] _T_89 = wrbuf_byteen[4] ? 3'h4 : _T_88; // @[Mux.scala 98:16] - wire [2:0] _T_90 = wrbuf_byteen[3] ? 3'h3 : _T_89; // @[Mux.scala 98:16] - wire [2:0] _T_91 = wrbuf_byteen[2] ? 3'h2 : _T_90; // @[Mux.scala 98:16] - wire [2:0] _T_92 = wrbuf_byteen[1] ? 3'h1 : _T_91; // @[Mux.scala 98:16] - wire [2:0] _T_93 = wrbuf_byteen[0] ? 3'h0 : _T_92; // @[Mux.scala 98:16] - wire [2:0] _T_95 = buf_write_in ? _T_93 : master_addr[2:0]; // @[axi4_to_ahb.scala 175:30] - wire _T_96 = buf_nxtstate == 3'h1; // @[axi4_to_ahb.scala 177:51] - wire _T_126 = master_ready & master_valid; // @[axi4_to_ahb.scala 188:33] - wire _T_162 = buf_nxtstate == 3'h6; // @[axi4_to_ahb.scala 203:64] - wire _T_163 = _T_126 & _T_162; // @[axi4_to_ahb.scala 203:48] - wire _T_164 = _T_163 & buf_state_en; // @[axi4_to_ahb.scala 203:79] - wire _T_349 = buf_state_en & buf_write_in; // @[axi4_to_ahb.scala 249:33] - wire _T_351 = _T_349 & _T_55; // @[axi4_to_ahb.scala 249:48] - wire _GEN_12 = _T_281 & _T_351; // @[Conditional.scala 39:67] - wire _GEN_32 = _T_188 ? 1'h0 : _GEN_12; // @[Conditional.scala 39:67] - wire _GEN_48 = _T_186 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67] - wire _GEN_65 = _T_175 ? 1'h0 : _GEN_48; // @[Conditional.scala 39:67] - wire _GEN_75 = _T_136 ? _T_164 : _GEN_65; // @[Conditional.scala 39:67] - wire _GEN_88 = _T_101 ? _T_126 : _GEN_75; // @[Conditional.scala 39:67] - wire bypass_en = _T_49 ? buf_state_en : _GEN_88; // @[Conditional.scala 40:58] - wire [1:0] _T_99 = bypass_en ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_100 = _T_99 & 2'h2; // @[axi4_to_ahb.scala 178:49] - wire _T_112 = ~master_valid; // @[axi4_to_ahb.scala 184:34] - wire _T_113 = buf_state_en & _T_112; // @[axi4_to_ahb.scala 184:32] - reg [31:0] buf_addr; // @[lib.scala 374:16] - wire [2:0] _T_130 = bypass_en ? master_addr[2:0] : buf_addr[2:0]; // @[axi4_to_ahb.scala 189:30] - wire _T_131 = ~buf_state_en; // @[axi4_to_ahb.scala 190:48] - wire _T_132 = _T_131 | bypass_en; // @[axi4_to_ahb.scala 190:62] - wire [1:0] _T_134 = _T_132 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_135 = 2'h2 & _T_134; // @[axi4_to_ahb.scala 190:36] - wire _T_169 = buf_nxtstate != 3'h6; // @[axi4_to_ahb.scala 205:63] - wire _T_170 = _T_169 & buf_state_en; // @[axi4_to_ahb.scala 205:78] - wire _T_171 = ~_T_170; // @[axi4_to_ahb.scala 205:47] - wire [1:0] _T_173 = _T_171 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_174 = 2'h2 & _T_173; // @[axi4_to_ahb.scala 205:36] - wire [1:0] _T_184 = _T_131 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_185 = 2'h2 & _T_184; // @[axi4_to_ahb.scala 215:41] - reg [2:0] buf_cmd_byte_ptrQ; // @[Reg.scala 27:20] - reg [7:0] buf_byteen; // @[Reg.scala 27:20] - wire [2:0] _T_197 = buf_cmd_byte_ptrQ + 3'h1; // @[axi4_to_ahb.scala 135:52] - wire _T_200 = 3'h0 >= _T_197; // @[axi4_to_ahb.scala 136:62] - wire _T_201 = buf_byteen[0] & _T_200; // @[axi4_to_ahb.scala 136:48] - wire _T_203 = 3'h1 >= _T_197; // @[axi4_to_ahb.scala 136:62] - wire _T_204 = buf_byteen[1] & _T_203; // @[axi4_to_ahb.scala 136:48] - wire _T_206 = 3'h2 >= _T_197; // @[axi4_to_ahb.scala 136:62] - wire _T_207 = buf_byteen[2] & _T_206; // @[axi4_to_ahb.scala 136:48] - wire _T_209 = 3'h3 >= _T_197; // @[axi4_to_ahb.scala 136:62] - wire _T_210 = buf_byteen[3] & _T_209; // @[axi4_to_ahb.scala 136:48] - wire _T_212 = 3'h4 >= _T_197; // @[axi4_to_ahb.scala 136:62] - wire _T_213 = buf_byteen[4] & _T_212; // @[axi4_to_ahb.scala 136:48] - wire _T_215 = 3'h5 >= _T_197; // @[axi4_to_ahb.scala 136:62] - wire _T_216 = buf_byteen[5] & _T_215; // @[axi4_to_ahb.scala 136:48] - wire _T_218 = 3'h6 >= _T_197; // @[axi4_to_ahb.scala 136:62] - wire _T_219 = buf_byteen[6] & _T_218; // @[axi4_to_ahb.scala 136:48] - wire [2:0] _T_224 = _T_219 ? 3'h6 : 3'h7; // @[Mux.scala 98:16] - wire [2:0] _T_225 = _T_216 ? 3'h5 : _T_224; // @[Mux.scala 98:16] - wire [2:0] _T_226 = _T_213 ? 3'h4 : _T_225; // @[Mux.scala 98:16] - wire [2:0] _T_227 = _T_210 ? 3'h3 : _T_226; // @[Mux.scala 98:16] - wire [2:0] _T_228 = _T_207 ? 3'h2 : _T_227; // @[Mux.scala 98:16] - wire [2:0] _T_229 = _T_204 ? 3'h1 : _T_228; // @[Mux.scala 98:16] - wire [2:0] _T_230 = _T_201 ? 3'h0 : _T_229; // @[Mux.scala 98:16] - wire [2:0] _T_231 = trxn_done ? _T_230 : buf_cmd_byte_ptrQ; // @[axi4_to_ahb.scala 233:30] - wire _T_232 = buf_cmd_byte_ptrQ == 3'h7; // @[axi4_to_ahb.scala 234:65] - reg buf_aligned; // @[Reg.scala 27:20] - wire _T_233 = buf_aligned | _T_232; // @[axi4_to_ahb.scala 234:44] - wire [7:0] _T_271 = buf_byteen >> _T_230; // @[axi4_to_ahb.scala 234:92] - wire _T_273 = ~_T_271[0]; // @[axi4_to_ahb.scala 234:163] - wire _T_274 = _T_233 | _T_273; // @[axi4_to_ahb.scala 234:79] - wire _T_275 = trxn_done & _T_274; // @[axi4_to_ahb.scala 234:29] - wire _T_346 = _T_232 | _T_273; // @[axi4_to_ahb.scala 248:38] - wire _T_347 = _T_109 & _T_346; // @[axi4_to_ahb.scala 247:80] - wire _T_348 = ahb_hresp_q | _T_347; // @[axi4_to_ahb.scala 247:34] - wire _GEN_11 = _T_281 & _T_348; // @[Conditional.scala 39:67] - wire _GEN_24 = _T_188 ? _T_275 : _GEN_11; // @[Conditional.scala 39:67] - wire _GEN_43 = _T_186 ? 1'h0 : _GEN_24; // @[Conditional.scala 39:67] - wire _GEN_61 = _T_175 ? 1'h0 : _GEN_43; // @[Conditional.scala 39:67] - wire _GEN_74 = _T_136 ? _T_113 : _GEN_61; // @[Conditional.scala 39:67] - wire _GEN_84 = _T_101 ? _T_113 : _GEN_74; // @[Conditional.scala 39:67] - wire cmd_done = _T_49 ? 1'h0 : _GEN_84; // @[Conditional.scala 40:58] - wire _T_276 = cmd_done | cmd_doneQ; // @[axi4_to_ahb.scala 235:47] - wire _T_277 = ~_T_276; // @[axi4_to_ahb.scala 235:36] - wire [1:0] _T_279 = _T_277 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_280 = _T_279 & 2'h2; // @[axi4_to_ahb.scala 235:61] - wire _T_300 = _T_55 | _T_96; // @[axi4_to_ahb.scala 245:62] - wire _T_301 = buf_state_en & _T_300; // @[axi4_to_ahb.scala 245:33] - wire _T_354 = _T_277 | bypass_en; // @[axi4_to_ahb.scala 250:61] - wire [1:0] _T_356 = _T_354 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_357 = _T_356 & 2'h2; // @[axi4_to_ahb.scala 250:75] - wire _T_364 = trxn_done | bypass_en; // @[axi4_to_ahb.scala 253:40] - wire [2:0] _T_439 = bypass_en ? _T_93 : _T_231; // @[axi4_to_ahb.scala 254:30] - wire _GEN_6 = _T_281 & ahb_hresp_q; // @[Conditional.scala 39:67] - wire _GEN_7 = _T_281 ? buf_state_en : _T_440; // @[Conditional.scala 39:67] - wire _GEN_9 = _T_281 & _T_301; // @[Conditional.scala 39:67] - wire _GEN_30 = _T_188 ? 1'h0 : _GEN_9; // @[Conditional.scala 39:67] - wire _GEN_47 = _T_186 ? 1'h0 : _GEN_30; // @[Conditional.scala 39:67] - wire _GEN_64 = _T_175 ? 1'h0 : _GEN_47; // @[Conditional.scala 39:67] - wire _GEN_67 = _T_136 ? _T_152 : _GEN_64; // @[Conditional.scala 39:67] - wire _GEN_87 = _T_101 ? master_ready : _GEN_67; // @[Conditional.scala 39:67] - wire buf_wr_en = _T_49 ? buf_state_en : _GEN_87; // @[Conditional.scala 40:58] - wire _GEN_10 = _T_281 & buf_wr_en; // @[Conditional.scala 39:67] - wire [1:0] _GEN_13 = _T_281 ? _T_357 : 2'h0; // @[Conditional.scala 39:67] - wire _GEN_16 = _T_281 & _T_364; // @[Conditional.scala 39:67] - wire [2:0] _GEN_17 = _T_281 ? _T_439 : 3'h0; // @[Conditional.scala 39:67] - wire _GEN_21 = _T_188 ? buf_state_en : _GEN_16; // @[Conditional.scala 39:67] - wire _GEN_22 = _T_188 & buf_state_en; // @[Conditional.scala 39:67] - wire [2:0] _GEN_23 = _T_188 ? _T_231 : _GEN_17; // @[Conditional.scala 39:67] - wire [1:0] _GEN_25 = _T_188 ? _T_280 : _GEN_13; // @[Conditional.scala 39:67] - wire _GEN_28 = _T_188 ? 1'h0 : _GEN_7; // @[Conditional.scala 39:67] - wire _GEN_31 = _T_188 ? 1'h0 : _GEN_10; // @[Conditional.scala 39:67] - wire _GEN_36 = _T_186 ? buf_state_en : _GEN_31; // @[Conditional.scala 39:67] - wire _GEN_38 = _T_186 ? buf_state_en : _GEN_28; // @[Conditional.scala 39:67] - wire _GEN_39 = _T_186 ? buf_state_en : _GEN_22; // @[Conditional.scala 39:67] - wire _GEN_41 = _T_186 ? 1'h0 : _GEN_21; // @[Conditional.scala 39:67] - wire [2:0] _GEN_42 = _T_186 ? 3'h0 : _GEN_23; // @[Conditional.scala 39:67] - wire [1:0] _GEN_44 = _T_186 ? 2'h0 : _GEN_25; // @[Conditional.scala 39:67] - wire _GEN_53 = _T_175 ? buf_state_en : _GEN_39; // @[Conditional.scala 39:67] - wire [2:0] _GEN_54 = _T_175 ? buf_addr[2:0] : _GEN_42; // @[Conditional.scala 39:67] - wire [1:0] _GEN_55 = _T_175 ? _T_185 : _GEN_44; // @[Conditional.scala 39:67] - wire _GEN_56 = _T_175 ? 1'h0 : _GEN_36; // @[Conditional.scala 39:67] - wire _GEN_58 = _T_175 ? 1'h0 : _GEN_38; // @[Conditional.scala 39:67] - wire _GEN_60 = _T_175 ? 1'h0 : _GEN_41; // @[Conditional.scala 39:67] - wire _GEN_70 = _T_136 ? buf_state_en : _GEN_56; // @[Conditional.scala 39:67] - wire _GEN_72 = _T_136 ? buf_state_en : _GEN_58; // @[Conditional.scala 39:67] - wire [2:0] _GEN_76 = _T_136 ? _T_130 : _GEN_54; // @[Conditional.scala 39:67] - wire [1:0] _GEN_77 = _T_136 ? _T_174 : _GEN_55; // @[Conditional.scala 39:67] - wire _GEN_78 = _T_136 ? buf_wr_en : _GEN_53; // @[Conditional.scala 39:67] - wire _GEN_80 = _T_136 ? 1'h0 : _GEN_60; // @[Conditional.scala 39:67] - wire _GEN_85 = _T_101 ? buf_state_en : _GEN_78; // @[Conditional.scala 39:67] - wire [2:0] _GEN_89 = _T_101 ? _T_130 : _GEN_76; // @[Conditional.scala 39:67] - wire [1:0] _GEN_90 = _T_101 ? _T_135 : _GEN_77; // @[Conditional.scala 39:67] - wire _GEN_91 = _T_101 ? 1'h0 : _GEN_70; // @[Conditional.scala 39:67] - wire _GEN_93 = _T_101 ? 1'h0 : _GEN_72; // @[Conditional.scala 39:67] - wire _GEN_96 = _T_101 ? 1'h0 : _GEN_80; // @[Conditional.scala 39:67] - wire buf_data_wr_en = _T_49 ? _T_56 : _GEN_91; // @[Conditional.scala 40:58] - wire buf_cmd_byte_ptr_en = _T_49 ? buf_state_en : _GEN_96; // @[Conditional.scala 40:58] - wire [2:0] buf_cmd_byte_ptr = _T_49 ? _T_95 : _GEN_89; // @[Conditional.scala 40:58] - wire slvbuf_wr_en = _T_49 ? 1'h0 : _GEN_85; // @[Conditional.scala 40:58] - wire slvbuf_error_en = _T_49 ? 1'h0 : _GEN_93; // @[Conditional.scala 40:58] - wire _T_535 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 271:24] - wire _T_536 = _T_103 | _T_535; // @[axi4_to_ahb.scala 270:48] - wire _T_538 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 271:54] - wire _T_539 = _T_536 | _T_538; // @[axi4_to_ahb.scala 271:33] - wire _T_541 = master_size[1:0] == 2'h2; // @[axi4_to_ahb.scala 271:93] - wire _T_542 = _T_539 | _T_541; // @[axi4_to_ahb.scala 271:72] - wire _T_544 = master_size[1:0] == 2'h3; // @[axi4_to_ahb.scala 272:25] - wire _T_546 = wrbuf_byteen == 8'h3; // @[axi4_to_ahb.scala 272:62] - wire _T_548 = wrbuf_byteen == 8'hc; // @[axi4_to_ahb.scala 272:97] - wire _T_549 = _T_546 | _T_548; // @[axi4_to_ahb.scala 272:74] - wire _T_551 = wrbuf_byteen == 8'h30; // @[axi4_to_ahb.scala 272:132] - wire _T_552 = _T_549 | _T_551; // @[axi4_to_ahb.scala 272:109] - wire _T_554 = wrbuf_byteen == 8'hc0; // @[axi4_to_ahb.scala 272:168] - wire _T_555 = _T_552 | _T_554; // @[axi4_to_ahb.scala 272:145] - wire _T_557 = wrbuf_byteen == 8'hf; // @[axi4_to_ahb.scala 273:28] - wire _T_558 = _T_555 | _T_557; // @[axi4_to_ahb.scala 272:181] - wire _T_560 = wrbuf_byteen == 8'hf0; // @[axi4_to_ahb.scala 273:63] - wire _T_561 = _T_558 | _T_560; // @[axi4_to_ahb.scala 273:40] - wire _T_563 = wrbuf_byteen == 8'hff; // @[axi4_to_ahb.scala 273:99] - wire _T_564 = _T_561 | _T_563; // @[axi4_to_ahb.scala 273:76] - wire _T_565 = _T_544 & _T_564; // @[axi4_to_ahb.scala 272:38] - wire buf_aligned_in = _T_542 | _T_565; // @[axi4_to_ahb.scala 271:106] - wire _T_444 = buf_aligned_in & _T_51; // @[axi4_to_ahb.scala 265:60] - wire [2:0] _T_461 = _T_548 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_462 = 3'h2 & _T_461; // @[axi4_to_ahb.scala 128:15] - wire _T_468 = _T_560 | _T_546; // @[axi4_to_ahb.scala 129:56] - wire [2:0] _T_470 = _T_468 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_471 = 3'h4 & _T_470; // @[axi4_to_ahb.scala 129:15] - wire [2:0] _T_472 = _T_462 | _T_471; // @[axi4_to_ahb.scala 128:63] - wire [2:0] _T_476 = _T_554 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_477 = 3'h6 & _T_476; // @[axi4_to_ahb.scala 130:15] - wire [2:0] _T_478 = _T_472 | _T_477; // @[axi4_to_ahb.scala 129:96] - wire [2:0] _T_485 = _T_444 ? _T_478 : master_addr[2:0]; // @[axi4_to_ahb.scala 265:43] - wire _T_489 = buf_state == 3'h3; // @[axi4_to_ahb.scala 268:33] - wire _T_495 = buf_aligned_in & _T_544; // @[axi4_to_ahb.scala 269:38] - wire _T_498 = _T_495 & _T_51; // @[axi4_to_ahb.scala 269:71] - wire [1:0] _T_504 = _T_563 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire _T_510 = _T_560 | _T_557; // @[axi4_to_ahb.scala 122:55] - wire [1:0] _T_512 = _T_510 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_513 = 2'h2 & _T_512; // @[axi4_to_ahb.scala 122:16] - wire [1:0] _T_514 = _T_504 | _T_513; // @[axi4_to_ahb.scala 121:64] - wire _T_519 = _T_554 | _T_551; // @[axi4_to_ahb.scala 123:60] - wire _T_522 = _T_519 | _T_548; // @[axi4_to_ahb.scala 123:89] - wire _T_525 = _T_522 | _T_546; // @[axi4_to_ahb.scala 123:123] - wire [1:0] _T_527 = _T_525 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_528 = 2'h1 & _T_527; // @[axi4_to_ahb.scala 123:21] - wire [1:0] _T_529 = _T_514 | _T_528; // @[axi4_to_ahb.scala 122:93] - wire [1:0] _T_531 = _T_498 ? _T_529 : master_size[1:0]; // @[axi4_to_ahb.scala 269:21] - wire [31:0] _T_570 = {master_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] - wire [31:0] _T_573 = {buf_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] - wire [1:0] _T_577 = buf_aligned_in ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [2:0] buf_size_in = {{1'd0}, _T_531}; // @[axi4_to_ahb.scala 269:15] - wire [1:0] _T_579 = _T_577 & buf_size_in[1:0]; // @[axi4_to_ahb.scala 276:81] - wire [2:0] _T_580 = {1'h0,_T_579}; // @[Cat.scala 29:58] - wire [1:0] _T_582 = buf_aligned ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - reg [1:0] buf_size; // @[Reg.scala 27:20] - wire [1:0] _T_584 = _T_582 & buf_size; // @[axi4_to_ahb.scala 276:138] - wire [2:0] _T_585 = {1'h0,_T_584}; // @[Cat.scala 29:58] - reg buf_write; // @[Reg.scala 27:20] - wire _T_611 = io_ahb_out_htrans != 2'h0; // @[axi4_to_ahb.scala 289:44] - wire _T_612 = _T_611 & io_ahb_in_hready; // @[axi4_to_ahb.scala 289:56] - wire last_addr_en = _T_612 & io_ahb_out_hwrite; // @[axi4_to_ahb.scala 289:75] - wire wrbuf_en = _T_44 & master_ready; // @[axi4_to_ahb.scala 291:49] - wire wrbuf_data_en = _T_45 & master_ready; // @[axi4_to_ahb.scala 292:52] - wire wrbuf_cmd_sent = _T_149 & _T_51; // @[axi4_to_ahb.scala 293:49] - wire _T_622 = ~wrbuf_en; // @[axi4_to_ahb.scala 294:33] - wire wrbuf_rst = wrbuf_cmd_sent & _T_622; // @[axi4_to_ahb.scala 294:31] - wire _T_624 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 296:36] - wire _T_625 = wrbuf_vld & _T_624; // @[axi4_to_ahb.scala 296:34] - wire _T_626 = ~_T_625; // @[axi4_to_ahb.scala 296:22] - wire _T_629 = wrbuf_data_vld & _T_624; // @[axi4_to_ahb.scala 297:38] - wire _T_630 = ~_T_629; // @[axi4_to_ahb.scala 297:21] - wire _T_633 = ~wr_cmd_vld; // @[axi4_to_ahb.scala 298:22] - wire _T_636 = wrbuf_en | wrbuf_vld; // @[axi4_to_ahb.scala 301:55] - wire _T_637 = ~wrbuf_rst; // @[axi4_to_ahb.scala 301:91] - wire _T_641 = wrbuf_data_en | wrbuf_data_vld; // @[axi4_to_ahb.scala 302:55] - reg [2:0] buf_tag; // @[Reg.scala 27:20] - wire _T_691 = ~slave_valid_pre; // @[axi4_to_ahb.scala 319:92] - wire _T_704 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 327:43] - wire _T_705 = _T_704 | io_clk_override; // @[axi4_to_ahb.scala 327:58] - wire _T_708 = io_ahb_in_hready & io_ahb_out_htrans[1]; // @[axi4_to_ahb.scala 328:57] - wire _T_709 = _T_708 | io_clk_override; // @[axi4_to_ahb.scala 328:81] - wire _T_711 = buf_state != 3'h0; // @[axi4_to_ahb.scala 329:50] - wire _T_712 = _T_711 | io_clk_override; // @[axi4_to_ahb.scala 329:60] - rvclkhdr rvclkhdr ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_io_l1clk), - .io_clk(rvclkhdr_io_clk), - .io_en(rvclkhdr_io_en), - .io_scan_mode(rvclkhdr_io_scan_mode) - ); - rvclkhdr rvclkhdr_1 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_1_io_l1clk), - .io_clk(rvclkhdr_1_io_clk), - .io_en(rvclkhdr_1_io_en), - .io_scan_mode(rvclkhdr_1_io_scan_mode) - ); - rvclkhdr rvclkhdr_2 ( // @[lib.scala 368:23] - .io_l1clk(rvclkhdr_2_io_l1clk), - .io_clk(rvclkhdr_2_io_clk), - .io_en(rvclkhdr_2_io_en), - .io_scan_mode(rvclkhdr_2_io_scan_mode) - ); - rvclkhdr rvclkhdr_3 ( // @[lib.scala 368:23] - .io_l1clk(rvclkhdr_3_io_l1clk), - .io_clk(rvclkhdr_3_io_clk), - .io_en(rvclkhdr_3_io_en), - .io_scan_mode(rvclkhdr_3_io_scan_mode) - ); - rvclkhdr rvclkhdr_4 ( // @[lib.scala 368:23] - .io_l1clk(rvclkhdr_4_io_l1clk), - .io_clk(rvclkhdr_4_io_clk), - .io_en(rvclkhdr_4_io_en), - .io_scan_mode(rvclkhdr_4_io_scan_mode) - ); - rvclkhdr rvclkhdr_5 ( // @[lib.scala 368:23] - .io_l1clk(rvclkhdr_5_io_l1clk), - .io_clk(rvclkhdr_5_io_clk), - .io_en(rvclkhdr_5_io_en), - .io_scan_mode(rvclkhdr_5_io_scan_mode) - ); - rvclkhdr rvclkhdr_6 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_6_io_l1clk), - .io_clk(rvclkhdr_6_io_clk), - .io_en(rvclkhdr_6_io_en), - .io_scan_mode(rvclkhdr_6_io_scan_mode) - ); - rvclkhdr rvclkhdr_7 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_7_io_l1clk), - .io_clk(rvclkhdr_7_io_clk), - .io_en(rvclkhdr_7_io_en), - .io_scan_mode(rvclkhdr_7_io_scan_mode) - ); - rvclkhdr rvclkhdr_8 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_8_io_l1clk), - .io_clk(rvclkhdr_8_io_clk), - .io_en(rvclkhdr_8_io_en), - .io_scan_mode(rvclkhdr_8_io_scan_mode) - ); - rvclkhdr rvclkhdr_9 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_9_io_l1clk), - .io_clk(rvclkhdr_9_io_clk), - .io_en(rvclkhdr_9_io_en), - .io_scan_mode(rvclkhdr_9_io_scan_mode) - ); - assign io_axi_aw_ready = _T_626 & master_ready; // @[axi4_to_ahb.scala 296:19] - assign io_axi_w_ready = _T_630 & master_ready; // @[axi4_to_ahb.scala 297:18] - assign io_axi_b_valid = slave_valid_pre & slave_opc[3]; // @[axi4_to_ahb.scala 149:18] - assign io_axi_b_bits_id = slvbuf_tag; // @[axi4_to_ahb.scala 151:20] - assign io_axi_ar_ready = _T_633 & master_ready; // @[axi4_to_ahb.scala 298:19] - assign io_axi_r_valid = slave_valid_pre & _T_35; // @[axi4_to_ahb.scala 153:18] - assign io_axi_r_bits_id = slvbuf_tag; // @[axi4_to_ahb.scala 155:20] - assign io_axi_r_bits_data = slvbuf_error ? _T_603 : _T_607; // @[axi4_to_ahb.scala 156:22] - assign io_axi_r_bits_resp = slave_opc[0] ? 2'h2 : _T_30; // @[axi4_to_ahb.scala 154:22] - assign io_ahb_out_haddr = bypass_en ? _T_570 : _T_573; // @[axi4_to_ahb.scala 275:20] - assign io_ahb_out_hsize = bypass_en ? _T_580 : _T_585; // @[axi4_to_ahb.scala 276:20] - assign io_ahb_out_htrans = _T_49 ? _T_100 : _GEN_90; // @[axi4_to_ahb.scala 22:21 axi4_to_ahb.scala 178:25 axi4_to_ahb.scala 190:25 axi4_to_ahb.scala 205:25 axi4_to_ahb.scala 215:25 axi4_to_ahb.scala 235:25 axi4_to_ahb.scala 250:25] - assign io_ahb_out_hwrite = bypass_en ? _T_51 : buf_write; // @[axi4_to_ahb.scala 281:21] - assign io_ahb_out_hwdata = buf_data; // @[axi4_to_ahb.scala 282:21] - assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_io_en = io_bus_clk_en; // @[lib.scala 345:16] - assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_1_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_1_io_en = io_bus_clk_en & _T_46; // @[lib.scala 345:16] - assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_2_io_clk = rvclkhdr_io_l1clk; // @[lib.scala 370:18] - assign rvclkhdr_2_io_en = _T_44 & master_ready; // @[lib.scala 371:17] - assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] - assign rvclkhdr_3_io_clk = rvclkhdr_io_l1clk; // @[lib.scala 370:18] - assign rvclkhdr_3_io_en = _T_45 & master_ready; // @[lib.scala 371:17] - assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] - assign rvclkhdr_4_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_4_io_en = buf_wr_en & io_bus_clk_en; // @[lib.scala 371:17] - assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] - assign rvclkhdr_5_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_5_io_en = buf_data_wr_en & io_bus_clk_en; // @[lib.scala 371:17] - assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] - assign rvclkhdr_6_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_6_io_en = io_bus_clk_en & _T_705; // @[lib.scala 345:16] - assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_7_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_7_io_en = io_bus_clk_en; // @[lib.scala 345:16] - assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_8_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_8_io_en = io_bus_clk_en & _T_709; // @[lib.scala 345:16] - assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_9_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_9_io_en = io_bus_clk_en & _T_712; // @[lib.scala 345:16] - assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] -`ifdef RANDOMIZE_GARBAGE_ASSIGN -`define RANDOMIZE -`endif -`ifdef RANDOMIZE_INVALID_ASSIGN -`define RANDOMIZE -`endif -`ifdef RANDOMIZE_REG_INIT -`define RANDOMIZE -`endif -`ifdef RANDOMIZE_MEM_INIT -`define RANDOMIZE -`endif -`ifndef RANDOM -`define RANDOM $random -`endif -`ifdef RANDOMIZE_MEM_INIT - integer initvar; -`endif -`ifndef SYNTHESIS -`ifdef FIRRTL_BEFORE_INITIAL -`FIRRTL_BEFORE_INITIAL -`endif -initial begin - `ifdef RANDOMIZE - `ifdef INIT_RANDOM - `INIT_RANDOM - `endif - `ifndef VERILATOR - `ifdef RANDOMIZE_DELAY - #`RANDOMIZE_DELAY begin end - `else - #0.002 begin end - `endif - `endif -`ifdef RANDOMIZE_REG_INIT - _RAND_0 = {1{`RANDOM}}; - buf_state = _RAND_0[2:0]; - _RAND_1 = {1{`RANDOM}}; - wrbuf_vld = _RAND_1[0:0]; - _RAND_2 = {1{`RANDOM}}; - wrbuf_data_vld = _RAND_2[0:0]; - _RAND_3 = {1{`RANDOM}}; - ahb_hready_q = _RAND_3[0:0]; - _RAND_4 = {1{`RANDOM}}; - ahb_htrans_q = _RAND_4[1:0]; - _RAND_5 = {1{`RANDOM}}; - ahb_hwrite_q = _RAND_5[0:0]; - _RAND_6 = {1{`RANDOM}}; - ahb_hresp_q = _RAND_6[0:0]; - _RAND_7 = {1{`RANDOM}}; - cmd_doneQ = _RAND_7[0:0]; - _RAND_8 = {1{`RANDOM}}; - wrbuf_tag = _RAND_8[2:0]; - _RAND_9 = {1{`RANDOM}}; - wrbuf_addr = _RAND_9[31:0]; - _RAND_10 = {1{`RANDOM}}; - wrbuf_size = _RAND_10[2:0]; - _RAND_11 = {1{`RANDOM}}; - wrbuf_byteen = _RAND_11[7:0]; - _RAND_12 = {2{`RANDOM}}; - wrbuf_data = _RAND_12[63:0]; - _RAND_13 = {1{`RANDOM}}; - slvbuf_write = _RAND_13[0:0]; - _RAND_14 = {1{`RANDOM}}; - slvbuf_error = _RAND_14[0:0]; - _RAND_15 = {1{`RANDOM}}; - slvbuf_tag = _RAND_15[2:0]; - _RAND_16 = {1{`RANDOM}}; - last_bus_addr = _RAND_16[31:0]; - _RAND_17 = {2{`RANDOM}}; - buf_data = _RAND_17[63:0]; - _RAND_18 = {2{`RANDOM}}; - ahb_hrdata_q = _RAND_18[63:0]; - _RAND_19 = {1{`RANDOM}}; - buf_addr = _RAND_19[31:0]; - _RAND_20 = {1{`RANDOM}}; - buf_cmd_byte_ptrQ = _RAND_20[2:0]; - _RAND_21 = {1{`RANDOM}}; - buf_byteen = _RAND_21[7:0]; - _RAND_22 = {1{`RANDOM}}; - buf_aligned = _RAND_22[0:0]; - _RAND_23 = {1{`RANDOM}}; - buf_size = _RAND_23[1:0]; - _RAND_24 = {1{`RANDOM}}; - buf_write = _RAND_24[0:0]; - _RAND_25 = {1{`RANDOM}}; - buf_tag = _RAND_25[2:0]; -`endif // RANDOMIZE_REG_INIT - if (reset) begin - buf_state = 3'h0; - end - if (reset) begin - wrbuf_vld = 1'h0; - end - if (reset) begin - wrbuf_data_vld = 1'h0; - end - if (reset) begin - ahb_hready_q = 1'h0; - end - if (reset) begin - ahb_htrans_q = 2'h0; - end - if (reset) begin - ahb_hwrite_q = 1'h0; - end - if (reset) begin - ahb_hresp_q = 1'h0; - end - if (reset) begin - cmd_doneQ = 1'h0; - end - if (reset) begin - wrbuf_tag = 3'h0; - end - if (reset) begin - wrbuf_addr = 32'h0; - end - if (reset) begin - wrbuf_size = 3'h0; - end - if (reset) begin - wrbuf_byteen = 8'h0; - end - if (reset) begin - wrbuf_data = 64'h0; - end - if (reset) begin - slvbuf_write = 1'h0; - end - if (reset) begin - slvbuf_error = 1'h0; - end - if (reset) begin - slvbuf_tag = 3'h0; - end - if (reset) begin - last_bus_addr = 32'h0; - end - if (reset) begin - buf_data = 64'h0; - end - if (reset) begin - ahb_hrdata_q = 64'h0; - end - if (reset) begin - buf_addr = 32'h0; - end - if (reset) begin - buf_cmd_byte_ptrQ = 3'h0; - end - if (reset) begin - buf_byteen = 8'h0; - end - if (reset) begin - buf_aligned = 1'h0; - end - if (reset) begin - buf_size = 2'h0; - end - if (reset) begin - buf_write = 1'h0; - end - if (reset) begin - buf_tag = 3'h0; - end - `endif // RANDOMIZE -end // initial -`ifdef FIRRTL_AFTER_INITIAL -`FIRRTL_AFTER_INITIAL -`endif -`endif // SYNTHESIS - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - buf_state <= 3'h0; - end else if (buf_state_en) begin - if (_T_49) begin - if (buf_write_in) begin - buf_state <= 3'h2; - end else begin - buf_state <= 3'h1; - end - end else if (_T_101) begin - if (_T_104) begin - buf_state <= 3'h6; - end else begin - buf_state <= 3'h3; - end - end else if (_T_136) begin - if (ahb_hresp_q) begin - buf_state <= 3'h7; - end else if (_T_152) begin - buf_state <= 3'h6; - end else begin - buf_state <= 3'h3; - end - end else if (_T_175) begin - buf_state <= 3'h3; - end else if (_T_186) begin - buf_state <= 3'h5; - end else if (_T_188) begin - buf_state <= 3'h4; - end else if (_T_281) begin - if (ahb_hresp_q) begin - buf_state <= 3'h5; - end else if (master_valid) begin - if (_T_51) begin - buf_state <= 3'h2; - end else begin - buf_state <= 3'h1; - end - end else begin - buf_state <= 3'h0; - end - end else begin - buf_state <= 3'h0; - end - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - wrbuf_vld <= 1'h0; - end else begin - wrbuf_vld <= _T_636 & _T_637; - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - wrbuf_data_vld <= 1'h0; - end else begin - wrbuf_data_vld <= _T_641 & _T_637; - end - end - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - ahb_hready_q <= 1'h0; - end else begin - ahb_hready_q <= io_ahb_in_hready; - end - end - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - ahb_htrans_q <= 2'h0; - end else begin - ahb_htrans_q <= io_ahb_out_htrans; - end - end - always @(posedge ahbm_addr_clk or posedge reset) begin - if (reset) begin - ahb_hwrite_q <= 1'h0; - end else begin - ahb_hwrite_q <= io_ahb_out_hwrite; - end - end - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - ahb_hresp_q <= 1'h0; - end else begin - ahb_hresp_q <= io_ahb_in_hresp; - end - end - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - cmd_doneQ <= 1'h0; - end else begin - cmd_doneQ <= _T_276 & _T_691; - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - wrbuf_tag <= 3'h0; - end else if (wrbuf_en) begin - wrbuf_tag <= io_axi_aw_bits_id; - end - end - always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin - if (reset) begin - wrbuf_addr <= 32'h0; - end else begin - wrbuf_addr <= io_axi_aw_bits_addr; - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - wrbuf_size <= 3'h0; - end else if (wrbuf_en) begin - wrbuf_size <= io_axi_aw_bits_size; - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - wrbuf_byteen <= 8'h0; - end else if (wrbuf_data_en) begin - wrbuf_byteen <= io_axi_w_bits_strb; - end - end - always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin - if (reset) begin - wrbuf_data <= 64'h0; - end else begin - wrbuf_data <= io_axi_w_bits_data; - end - end - always @(posedge buf_clk or posedge reset) begin - if (reset) begin - slvbuf_write <= 1'h0; - end else if (slvbuf_wr_en) begin - slvbuf_write <= buf_write; - end - end - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - slvbuf_error <= 1'h0; - end else if (slvbuf_error_en) begin - if (_T_49) begin - slvbuf_error <= 1'h0; - end else if (_T_101) begin - slvbuf_error <= 1'h0; - end else if (_T_136) begin - slvbuf_error <= ahb_hresp_q; - end else if (_T_175) begin - slvbuf_error <= 1'h0; - end else if (_T_186) begin - slvbuf_error <= ahb_hresp_q; - end else if (_T_188) begin - slvbuf_error <= 1'h0; - end else begin - slvbuf_error <= _GEN_6; - end - end - end - always @(posedge buf_clk or posedge reset) begin - if (reset) begin - slvbuf_tag <= 3'h0; - end else if (slvbuf_wr_en) begin - slvbuf_tag <= buf_tag; - end - end - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - last_bus_addr <= 32'h0; - end else if (last_addr_en) begin - last_bus_addr <= io_ahb_out_haddr; - end - end - always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin - if (reset) begin - buf_data <= 64'h0; - end else if (_T_489) begin - buf_data <= ahb_hrdata_q; - end else begin - buf_data <= wrbuf_data; - end - end - always @(posedge ahbm_data_clk or posedge reset) begin - if (reset) begin - ahb_hrdata_q <= 64'h0; - end else begin - ahb_hrdata_q <= io_ahb_in_hrdata; - end - end - always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin - if (reset) begin - buf_addr <= 32'h0; - end else begin - buf_addr <= {master_addr[31:3],_T_485}; - end - end - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - buf_cmd_byte_ptrQ <= 3'h0; - end else if (buf_cmd_byte_ptr_en) begin - if (_T_49) begin - if (buf_write_in) begin - if (wrbuf_byteen[0]) begin - buf_cmd_byte_ptrQ <= 3'h0; - end else if (wrbuf_byteen[1]) begin - buf_cmd_byte_ptrQ <= 3'h1; - end else if (wrbuf_byteen[2]) begin - buf_cmd_byte_ptrQ <= 3'h2; - end else if (wrbuf_byteen[3]) begin - buf_cmd_byte_ptrQ <= 3'h3; - end else if (wrbuf_byteen[4]) begin - buf_cmd_byte_ptrQ <= 3'h4; - end else if (wrbuf_byteen[5]) begin - buf_cmd_byte_ptrQ <= 3'h5; - end else if (wrbuf_byteen[6]) begin - buf_cmd_byte_ptrQ <= 3'h6; - end else begin - buf_cmd_byte_ptrQ <= 3'h7; - end - end else begin - buf_cmd_byte_ptrQ <= master_addr[2:0]; - end - end else if (_T_101) begin - if (bypass_en) begin - buf_cmd_byte_ptrQ <= master_addr[2:0]; - end else begin - buf_cmd_byte_ptrQ <= buf_addr[2:0]; - end - end else if (_T_136) begin - if (bypass_en) begin - buf_cmd_byte_ptrQ <= master_addr[2:0]; - end else begin - buf_cmd_byte_ptrQ <= buf_addr[2:0]; - end - end else if (_T_175) begin - buf_cmd_byte_ptrQ <= buf_addr[2:0]; - end else if (_T_186) begin - buf_cmd_byte_ptrQ <= 3'h0; - end else if (_T_188) begin - if (trxn_done) begin - if (_T_201) begin - buf_cmd_byte_ptrQ <= 3'h0; - end else if (_T_204) begin - buf_cmd_byte_ptrQ <= 3'h1; - end else if (_T_207) begin - buf_cmd_byte_ptrQ <= 3'h2; - end else if (_T_210) begin - buf_cmd_byte_ptrQ <= 3'h3; - end else if (_T_213) begin - buf_cmd_byte_ptrQ <= 3'h4; - end else if (_T_216) begin - buf_cmd_byte_ptrQ <= 3'h5; - end else if (_T_219) begin - buf_cmd_byte_ptrQ <= 3'h6; - end else begin - buf_cmd_byte_ptrQ <= 3'h7; - end - end - end else if (_T_281) begin - if (bypass_en) begin - if (wrbuf_byteen[0]) begin - buf_cmd_byte_ptrQ <= 3'h0; - end else if (wrbuf_byteen[1]) begin - buf_cmd_byte_ptrQ <= 3'h1; - end else if (wrbuf_byteen[2]) begin - buf_cmd_byte_ptrQ <= 3'h2; - end else if (wrbuf_byteen[3]) begin - buf_cmd_byte_ptrQ <= 3'h3; - end else if (wrbuf_byteen[4]) begin - buf_cmd_byte_ptrQ <= 3'h4; - end else if (wrbuf_byteen[5]) begin - buf_cmd_byte_ptrQ <= 3'h5; - end else if (wrbuf_byteen[6]) begin - buf_cmd_byte_ptrQ <= 3'h6; - end else begin - buf_cmd_byte_ptrQ <= 3'h7; - end - end else if (trxn_done) begin - if (_T_201) begin - buf_cmd_byte_ptrQ <= 3'h0; - end else if (_T_204) begin - buf_cmd_byte_ptrQ <= 3'h1; - end else if (_T_207) begin - buf_cmd_byte_ptrQ <= 3'h2; - end else if (_T_210) begin - buf_cmd_byte_ptrQ <= 3'h3; - end else if (_T_213) begin - buf_cmd_byte_ptrQ <= 3'h4; - end else if (_T_216) begin - buf_cmd_byte_ptrQ <= 3'h5; - end else if (_T_219) begin - buf_cmd_byte_ptrQ <= 3'h6; - end else begin - buf_cmd_byte_ptrQ <= 3'h7; - end - end - end else begin - buf_cmd_byte_ptrQ <= 3'h0; - end - end - end - always @(posedge buf_clk or posedge reset) begin - if (reset) begin - buf_byteen <= 8'h0; - end else if (buf_wr_en) begin - buf_byteen <= wrbuf_byteen; - end - end - always @(posedge buf_clk or posedge reset) begin - if (reset) begin - buf_aligned <= 1'h0; - end else if (buf_wr_en) begin - buf_aligned <= buf_aligned_in; - end - end - always @(posedge buf_clk or posedge reset) begin - if (reset) begin - buf_size <= 2'h0; - end else if (buf_wr_en) begin - buf_size <= buf_size_in[1:0]; - end - end - always @(posedge buf_clk or posedge reset) begin - if (reset) begin - buf_write <= 1'h0; - end else if (buf_wr_en) begin - if (_T_49) begin - buf_write <= _T_51; - end else if (_T_101) begin - buf_write <= 1'h0; - end else if (_T_136) begin - buf_write <= 1'h0; - end else if (_T_175) begin - buf_write <= 1'h0; - end else if (_T_186) begin - buf_write <= 1'h0; - end else if (_T_188) begin - buf_write <= 1'h0; - end else begin - buf_write <= _GEN_8; - end - end - end - always @(posedge buf_clk or posedge reset) begin - if (reset) begin - buf_tag <= 3'h0; - end else if (buf_wr_en) begin - if (wr_cmd_vld) begin - buf_tag <= wrbuf_tag; - end else begin - buf_tag <= io_axi_ar_bits_id; - end - end - end -endmodule -module ahb_to_axi4( - input clock, - input reset, - input io_scan_mode, - input io_bus_clk_en, - input io_axi_aw_ready, - output io_axi_aw_valid, - output [31:0] io_axi_aw_bits_addr, - output [2:0] io_axi_aw_bits_size, - output io_axi_w_valid, - output [63:0] io_axi_w_bits_data, - output [7:0] io_axi_w_bits_strb, - input io_axi_ar_ready, - output io_axi_ar_valid, - output [31:0] io_axi_ar_bits_addr, - output [2:0] io_axi_ar_bits_size, - input io_axi_r_valid, - input [63:0] io_axi_r_bits_data, - input [1:0] io_axi_r_bits_resp, - output [63:0] io_ahb_sig_in_hrdata, - output io_ahb_sig_in_hready, - output io_ahb_sig_in_hresp, - input [31:0] io_ahb_sig_out_haddr, - input [2:0] io_ahb_sig_out_hsize, - input [1:0] io_ahb_sig_out_htrans, - input io_ahb_sig_out_hwrite, - input [63:0] io_ahb_sig_out_hwdata, - input io_ahb_hsel, - input io_ahb_hreadyin -); -`ifdef RANDOMIZE_REG_INIT - reg [31:0] _RAND_0; - reg [31:0] _RAND_1; - reg [31:0] _RAND_2; - reg [31:0] _RAND_3; - reg [31:0] _RAND_4; - reg [31:0] _RAND_5; - reg [31:0] _RAND_6; - reg [31:0] _RAND_7; - reg [63:0] _RAND_8; - reg [31:0] _RAND_9; - reg [31:0] _RAND_10; - reg [31:0] _RAND_11; - reg [31:0] _RAND_12; - reg [31:0] _RAND_13; - reg [63:0] _RAND_14; -`endif // RANDOMIZE_REG_INIT - wire rvclkhdr_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_io_en; // @[lib.scala 343:22] - wire rvclkhdr_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_1_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_1_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_1_io_en; // @[lib.scala 343:22] - wire rvclkhdr_1_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_2_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_2_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_2_io_en; // @[lib.scala 343:22] - wire rvclkhdr_2_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_3_io_l1clk; // @[lib.scala 368:23] - wire rvclkhdr_3_io_clk; // @[lib.scala 368:23] - wire rvclkhdr_3_io_en; // @[lib.scala 368:23] - wire rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23] - wire rvclkhdr_4_io_l1clk; // @[lib.scala 368:23] - wire rvclkhdr_4_io_clk; // @[lib.scala 368:23] - wire rvclkhdr_4_io_en; // @[lib.scala 368:23] - wire rvclkhdr_4_io_scan_mode; // @[lib.scala 368:23] - wire rvclkhdr_5_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_5_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_5_io_en; // @[lib.scala 343:22] - wire rvclkhdr_5_io_scan_mode; // @[lib.scala 343:22] - wire ahb_addr_clk = rvclkhdr_1_io_l1clk; // @[ahb_to_axi4.scala 44:33 ahb_to_axi4.scala 133:31] - reg [31:0] ahb_haddr_q; // @[ahb_to_axi4.scala 126:65] - wire ahb_addr_in_dccm = ahb_haddr_q[31:16] == 16'hf004; // @[lib.scala 87:29] - wire ahb_addr_in_iccm = ahb_haddr_q[31:16] == 16'hee00; // @[lib.scala 87:29] - wire ahb_clk = rvclkhdr_io_l1clk; // @[ahb_to_axi4.scala 43:33 ahb_to_axi4.scala 132:31] - reg [1:0] buf_state; // @[Reg.scala 27:20] - wire _T_7 = 2'h0 == buf_state; // @[Conditional.scala 37:30] - wire ahb_hready = io_ahb_sig_in_hready & io_ahb_hreadyin; // @[ahb_to_axi4.scala 104:55] - wire _T_10 = ahb_hready & io_ahb_sig_out_htrans[1]; // @[ahb_to_axi4.scala 76:34] - wire _T_11 = _T_10 & io_ahb_hsel; // @[ahb_to_axi4.scala 76:61] - wire _T_12 = 2'h1 == buf_state; // @[Conditional.scala 37:30] - wire _T_14 = io_ahb_sig_out_htrans == 2'h0; // @[ahb_to_axi4.scala 79:79] - wire _T_15 = io_ahb_sig_in_hresp | _T_14; // @[ahb_to_axi4.scala 79:48] - wire _T_16 = ~io_ahb_hsel; // @[ahb_to_axi4.scala 79:93] - wire _T_17 = _T_15 | _T_16; // @[ahb_to_axi4.scala 79:91] - wire bus_clk = rvclkhdr_5_io_l1clk; // @[ahb_to_axi4.scala 57:33 ahb_to_axi4.scala 180:27] - reg cmdbuf_vld; // @[ahb_to_axi4.scala 139:61] - wire _T_151 = io_axi_aw_valid & io_axi_aw_ready; // @[ahb_to_axi4.scala 137:67] - wire _T_152 = io_axi_ar_valid & io_axi_ar_ready; // @[ahb_to_axi4.scala 137:105] - wire _T_153 = _T_151 | _T_152; // @[ahb_to_axi4.scala 137:86] - wire _T_154 = ~_T_153; // @[ahb_to_axi4.scala 137:48] - wire cmdbuf_full = cmdbuf_vld & _T_154; // @[ahb_to_axi4.scala 137:46] - wire _T_21 = ~cmdbuf_full; // @[ahb_to_axi4.scala 80:24] - wire _T_22 = _T_21 | io_ahb_sig_in_hresp; // @[ahb_to_axi4.scala 80:37] - wire _T_25 = io_ahb_sig_out_htrans == 2'h1; // @[ahb_to_axi4.scala 81:92] - wire _T_26 = _T_25 & io_ahb_hsel; // @[ahb_to_axi4.scala 81:110] - wire _T_27 = io_ahb_sig_in_hresp | _T_26; // @[ahb_to_axi4.scala 81:60] - wire _T_28 = ~_T_27; // @[ahb_to_axi4.scala 81:38] - wire _T_29 = _T_21 & _T_28; // @[ahb_to_axi4.scala 81:36] - wire _T_30 = 2'h2 == buf_state; // @[Conditional.scala 37:30] - wire _T_34 = ~io_ahb_sig_in_hresp; // @[ahb_to_axi4.scala 86:23] - wire _T_36 = _T_34 & _T_21; // @[ahb_to_axi4.scala 86:44] - wire _T_37 = 2'h3 == buf_state; // @[Conditional.scala 37:30] - reg cmdbuf_write; // @[Reg.scala 27:20] - wire _T_38 = ~cmdbuf_write; // @[ahb_to_axi4.scala 90:40] - wire _T_39 = io_axi_r_valid & _T_38; // @[ahb_to_axi4.scala 90:38] - wire _T_41 = |io_axi_r_bits_resp; // @[ahb_to_axi4.scala 92:68] - wire _GEN_1 = _T_37 & _T_39; // @[Conditional.scala 39:67] - wire _GEN_5 = _T_30 ? _T_22 : _GEN_1; // @[Conditional.scala 39:67] - wire _GEN_10 = _T_12 ? _T_22 : _GEN_5; // @[Conditional.scala 39:67] - wire buf_state_en = _T_7 ? _T_11 : _GEN_10; // @[Conditional.scala 40:58] - wire _T_42 = buf_state_en & _T_41; // @[ahb_to_axi4.scala 92:41] - wire _GEN_2 = _T_37 & buf_state_en; // @[Conditional.scala 39:67] - wire _GEN_3 = _T_37 & _T_42; // @[Conditional.scala 39:67] - wire _GEN_6 = _T_30 & _T_36; // @[Conditional.scala 39:67] - wire _GEN_7 = _T_30 ? 1'h0 : _GEN_2; // @[Conditional.scala 39:67] - wire _GEN_11 = _T_12 ? _T_29 : _GEN_6; // @[Conditional.scala 39:67] - wire _GEN_12 = _T_12 ? 1'h0 : _GEN_7; // @[Conditional.scala 39:67] - wire cmdbuf_wr_en = _T_7 ? 1'h0 : _GEN_11; // @[Conditional.scala 40:58] - wire buf_rdata_en = _T_7 ? 1'h0 : _GEN_12; // @[Conditional.scala 40:58] - reg [2:0] ahb_hsize_q; // @[ahb_to_axi4.scala 124:65] - wire _T_46 = ahb_hsize_q == 3'h0; // @[ahb_to_axi4.scala 97:60] - wire [7:0] _T_48 = _T_46 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_50 = 8'h1 << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 97:78] - wire [7:0] _T_51 = _T_48 & _T_50; // @[ahb_to_axi4.scala 97:70] - wire _T_53 = ahb_hsize_q == 3'h1; // @[ahb_to_axi4.scala 98:30] - wire [7:0] _T_55 = _T_53 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [8:0] _T_57 = 9'h3 << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 98:48] - wire [8:0] _GEN_23 = {{1'd0}, _T_55}; // @[ahb_to_axi4.scala 98:40] - wire [8:0] _T_58 = _GEN_23 & _T_57; // @[ahb_to_axi4.scala 98:40] - wire [8:0] _GEN_24 = {{1'd0}, _T_51}; // @[ahb_to_axi4.scala 97:109] - wire [8:0] _T_59 = _GEN_24 | _T_58; // @[ahb_to_axi4.scala 97:109] - wire _T_61 = ahb_hsize_q == 3'h2; // @[ahb_to_axi4.scala 99:30] - wire [7:0] _T_63 = _T_61 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [10:0] _T_65 = 11'hf << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 99:48] - wire [10:0] _GEN_25 = {{3'd0}, _T_63}; // @[ahb_to_axi4.scala 99:40] - wire [10:0] _T_66 = _GEN_25 & _T_65; // @[ahb_to_axi4.scala 99:40] - wire [10:0] _GEN_26 = {{2'd0}, _T_59}; // @[ahb_to_axi4.scala 98:79] - wire [10:0] _T_67 = _GEN_26 | _T_66; // @[ahb_to_axi4.scala 98:79] - wire _T_69 = ahb_hsize_q == 3'h3; // @[ahb_to_axi4.scala 100:30] - wire [7:0] _T_71 = _T_69 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [10:0] _GEN_27 = {{3'd0}, _T_71}; // @[ahb_to_axi4.scala 99:79] - wire [10:0] _T_73 = _T_67 | _GEN_27; // @[ahb_to_axi4.scala 99:79] - reg ahb_hready_q; // @[ahb_to_axi4.scala 122:60] - wire _T_74 = ~ahb_hready_q; // @[ahb_to_axi4.scala 103:80] - reg ahb_hresp_q; // @[ahb_to_axi4.scala 121:60] - wire _T_75 = ahb_hresp_q & _T_74; // @[ahb_to_axi4.scala 103:78] - wire _T_77 = buf_state == 2'h0; // @[ahb_to_axi4.scala 103:124] - wire _T_78 = _T_21 | _T_77; // @[ahb_to_axi4.scala 103:111] - wire _T_79 = buf_state == 2'h2; // @[ahb_to_axi4.scala 103:149] - wire _T_80 = buf_state == 2'h3; // @[ahb_to_axi4.scala 103:168] - wire _T_81 = _T_79 | _T_80; // @[ahb_to_axi4.scala 103:156] - wire _T_82 = ~_T_81; // @[ahb_to_axi4.scala 103:137] - wire _T_83 = _T_78 & _T_82; // @[ahb_to_axi4.scala 103:135] - reg buf_read_error; // @[ahb_to_axi4.scala 118:60] - wire _T_84 = ~buf_read_error; // @[ahb_to_axi4.scala 103:181] - wire _T_85 = _T_83 & _T_84; // @[ahb_to_axi4.scala 103:179] - wire [1:0] _T_89 = io_ahb_hsel ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire buf_rdata_clk = rvclkhdr_2_io_l1clk; // @[ahb_to_axi4.scala 45:33 ahb_to_axi4.scala 134:31] - reg [63:0] buf_rdata; // @[ahb_to_axi4.scala 117:66] - reg [1:0] ahb_htrans_q; // @[ahb_to_axi4.scala 123:60] - wire _T_94 = ahb_htrans_q != 2'h0; // @[ahb_to_axi4.scala 107:61] - wire _T_95 = buf_state != 2'h0; // @[ahb_to_axi4.scala 107:83] - wire _T_96 = _T_94 & _T_95; // @[ahb_to_axi4.scala 107:70] - wire _T_97 = ahb_addr_in_dccm | ahb_addr_in_iccm; // @[ahb_to_axi4.scala 108:26] - wire _T_98 = ~_T_97; // @[ahb_to_axi4.scala 108:7] - reg ahb_hwrite_q; // @[ahb_to_axi4.scala 125:65] - wire _T_99 = ahb_addr_in_dccm & ahb_hwrite_q; // @[ahb_to_axi4.scala 109:46] - wire _T_100 = ahb_addr_in_iccm | _T_99; // @[ahb_to_axi4.scala 109:26] - wire _T_102 = ahb_hsize_q[1:0] == 2'h2; // @[ahb_to_axi4.scala 109:86] - wire _T_104 = ahb_hsize_q[1:0] == 2'h3; // @[ahb_to_axi4.scala 109:115] - wire _T_105 = _T_102 | _T_104; // @[ahb_to_axi4.scala 109:95] - wire _T_106 = ~_T_105; // @[ahb_to_axi4.scala 109:66] - wire _T_107 = _T_100 & _T_106; // @[ahb_to_axi4.scala 109:64] - wire _T_108 = _T_98 | _T_107; // @[ahb_to_axi4.scala 108:47] - wire _T_112 = _T_53 & ahb_haddr_q[0]; // @[ahb_to_axi4.scala 110:35] - wire _T_113 = _T_108 | _T_112; // @[ahb_to_axi4.scala 109:126] - wire _T_117 = |ahb_haddr_q[1:0]; // @[ahb_to_axi4.scala 111:56] - wire _T_118 = _T_61 & _T_117; // @[ahb_to_axi4.scala 111:35] - wire _T_119 = _T_113 | _T_118; // @[ahb_to_axi4.scala 110:55] - wire _T_123 = |ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 112:56] - wire _T_124 = _T_69 & _T_123; // @[ahb_to_axi4.scala 112:35] - wire _T_125 = _T_119 | _T_124; // @[ahb_to_axi4.scala 111:61] - wire _T_126 = _T_96 & _T_125; // @[ahb_to_axi4.scala 107:94] - wire _T_127 = _T_126 | buf_read_error; // @[ahb_to_axi4.scala 112:63] - wire _T_146 = ~cmdbuf_wr_en; // @[ahb_to_axi4.scala 136:113] - wire _T_147 = _T_153 & _T_146; // @[ahb_to_axi4.scala 136:111] - wire _T_149 = io_ahb_sig_in_hresp & _T_38; // @[ahb_to_axi4.scala 136:151] - wire cmdbuf_rst = _T_147 | _T_149; // @[ahb_to_axi4.scala 136:128] - wire _T_157 = cmdbuf_wr_en | cmdbuf_vld; // @[ahb_to_axi4.scala 139:66] - wire _T_158 = ~cmdbuf_rst; // @[ahb_to_axi4.scala 139:110] - reg [2:0] _T_164; // @[Reg.scala 27:20] - reg [7:0] cmdbuf_wstrb; // @[Reg.scala 27:20] - wire [7:0] master_wstrb = _T_73[7:0]; // @[ahb_to_axi4.scala 97:31] - reg [31:0] cmdbuf_addr; // @[lib.scala 374:16] - reg [63:0] cmdbuf_wdata; // @[lib.scala 374:16] - wire [1:0] cmdbuf_size = _T_164[1:0]; // @[ahb_to_axi4.scala 145:31] - rvclkhdr rvclkhdr ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_io_l1clk), - .io_clk(rvclkhdr_io_clk), - .io_en(rvclkhdr_io_en), - .io_scan_mode(rvclkhdr_io_scan_mode) - ); - rvclkhdr rvclkhdr_1 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_1_io_l1clk), - .io_clk(rvclkhdr_1_io_clk), - .io_en(rvclkhdr_1_io_en), - .io_scan_mode(rvclkhdr_1_io_scan_mode) - ); - rvclkhdr rvclkhdr_2 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_2_io_l1clk), - .io_clk(rvclkhdr_2_io_clk), - .io_en(rvclkhdr_2_io_en), - .io_scan_mode(rvclkhdr_2_io_scan_mode) - ); - rvclkhdr rvclkhdr_3 ( // @[lib.scala 368:23] - .io_l1clk(rvclkhdr_3_io_l1clk), - .io_clk(rvclkhdr_3_io_clk), - .io_en(rvclkhdr_3_io_en), - .io_scan_mode(rvclkhdr_3_io_scan_mode) - ); - rvclkhdr rvclkhdr_4 ( // @[lib.scala 368:23] - .io_l1clk(rvclkhdr_4_io_l1clk), - .io_clk(rvclkhdr_4_io_clk), - .io_en(rvclkhdr_4_io_en), - .io_scan_mode(rvclkhdr_4_io_scan_mode) - ); - rvclkhdr rvclkhdr_5 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_5_io_l1clk), - .io_clk(rvclkhdr_5_io_clk), - .io_en(rvclkhdr_5_io_en), - .io_scan_mode(rvclkhdr_5_io_scan_mode) - ); - assign io_axi_aw_valid = cmdbuf_vld & cmdbuf_write; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 156:28] - assign io_axi_aw_bits_addr = cmdbuf_addr; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 158:33] - assign io_axi_aw_bits_size = {1'h0,cmdbuf_size}; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 159:33] - assign io_axi_w_valid = cmdbuf_vld & cmdbuf_write; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 164:28] - assign io_axi_w_bits_data = cmdbuf_wdata; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 165:33] - assign io_axi_w_bits_strb = cmdbuf_wstrb; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 166:33] - assign io_axi_ar_valid = cmdbuf_vld & _T_38; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 171:28] - assign io_axi_ar_bits_addr = cmdbuf_addr; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 173:33] - assign io_axi_ar_bits_size = {1'h0,cmdbuf_size}; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 174:33] - assign io_ahb_sig_in_hrdata = buf_rdata; // @[ahb_to_axi4.scala 106:38] - assign io_ahb_sig_in_hready = io_ahb_sig_in_hresp ? _T_75 : _T_85; // @[ahb_to_axi4.scala 103:38] - assign io_ahb_sig_in_hresp = _T_127 | _T_75; // @[ahb_to_axi4.scala 107:38] - assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_io_en = io_bus_clk_en; // @[lib.scala 345:16] - assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_1_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_1_io_en = io_bus_clk_en & _T_10; // @[lib.scala 345:16] - assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_2_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_2_io_en = io_bus_clk_en & buf_rdata_en; // @[lib.scala 345:16] - assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_3_io_clk = rvclkhdr_5_io_l1clk; // @[lib.scala 370:18] - assign rvclkhdr_3_io_en = _T_7 ? 1'h0 : _GEN_11; // @[lib.scala 371:17] - assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] - assign rvclkhdr_4_io_clk = rvclkhdr_5_io_l1clk; // @[lib.scala 370:18] - assign rvclkhdr_4_io_en = _T_7 ? 1'h0 : _GEN_11; // @[lib.scala 371:17] - assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] - assign rvclkhdr_5_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_5_io_en = io_bus_clk_en; // @[lib.scala 345:16] - assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] -`ifdef RANDOMIZE_GARBAGE_ASSIGN -`define RANDOMIZE -`endif -`ifdef RANDOMIZE_INVALID_ASSIGN -`define RANDOMIZE -`endif -`ifdef RANDOMIZE_REG_INIT -`define RANDOMIZE -`endif -`ifdef RANDOMIZE_MEM_INIT -`define RANDOMIZE -`endif -`ifndef RANDOM -`define RANDOM $random -`endif -`ifdef RANDOMIZE_MEM_INIT - integer initvar; -`endif -`ifndef SYNTHESIS -`ifdef FIRRTL_BEFORE_INITIAL -`FIRRTL_BEFORE_INITIAL -`endif -initial begin - `ifdef RANDOMIZE - `ifdef INIT_RANDOM - `INIT_RANDOM - `endif - `ifndef VERILATOR - `ifdef RANDOMIZE_DELAY - #`RANDOMIZE_DELAY begin end - `else - #0.002 begin end - `endif - `endif -`ifdef RANDOMIZE_REG_INIT - _RAND_0 = {1{`RANDOM}}; - ahb_haddr_q = _RAND_0[31:0]; - _RAND_1 = {1{`RANDOM}}; - buf_state = _RAND_1[1:0]; - _RAND_2 = {1{`RANDOM}}; - cmdbuf_vld = _RAND_2[0:0]; - _RAND_3 = {1{`RANDOM}}; - cmdbuf_write = _RAND_3[0:0]; - _RAND_4 = {1{`RANDOM}}; - ahb_hsize_q = _RAND_4[2:0]; - _RAND_5 = {1{`RANDOM}}; - ahb_hready_q = _RAND_5[0:0]; - _RAND_6 = {1{`RANDOM}}; - ahb_hresp_q = _RAND_6[0:0]; - _RAND_7 = {1{`RANDOM}}; - buf_read_error = _RAND_7[0:0]; - _RAND_8 = {2{`RANDOM}}; - buf_rdata = _RAND_8[63:0]; - _RAND_9 = {1{`RANDOM}}; - ahb_htrans_q = _RAND_9[1:0]; - _RAND_10 = {1{`RANDOM}}; - ahb_hwrite_q = _RAND_10[0:0]; - _RAND_11 = {1{`RANDOM}}; - _T_164 = _RAND_11[2:0]; - _RAND_12 = {1{`RANDOM}}; - cmdbuf_wstrb = _RAND_12[7:0]; - _RAND_13 = {1{`RANDOM}}; - cmdbuf_addr = _RAND_13[31:0]; - _RAND_14 = {2{`RANDOM}}; - cmdbuf_wdata = _RAND_14[63:0]; -`endif // RANDOMIZE_REG_INIT - if (reset) begin - ahb_haddr_q = 32'h0; - end - if (reset) begin - buf_state = 2'h0; - end - if (reset) begin - cmdbuf_vld = 1'h0; - end - if (reset) begin - cmdbuf_write = 1'h0; - end - if (reset) begin - ahb_hsize_q = 3'h0; - end - if (reset) begin - ahb_hready_q = 1'h0; - end - if (reset) begin - ahb_hresp_q = 1'h0; - end - if (reset) begin - buf_read_error = 1'h0; - end - if (reset) begin - buf_rdata = 64'h0; - end - if (reset) begin - ahb_htrans_q = 2'h0; - end - if (reset) begin - ahb_hwrite_q = 1'h0; - end - if (reset) begin - _T_164 = 3'h0; - end - if (reset) begin - cmdbuf_wstrb = 8'h0; - end - if (reset) begin - cmdbuf_addr = 32'h0; - end - if (reset) begin - cmdbuf_wdata = 64'h0; - end - `endif // RANDOMIZE -end // initial -`ifdef FIRRTL_AFTER_INITIAL -`FIRRTL_AFTER_INITIAL -`endif -`endif // SYNTHESIS - always @(posedge ahb_addr_clk or posedge reset) begin - if (reset) begin - ahb_haddr_q <= 32'h0; - end else begin - ahb_haddr_q <= io_ahb_sig_out_haddr; - end - end - always @(posedge ahb_clk or posedge reset) begin - if (reset) begin - buf_state <= 2'h0; - end else if (buf_state_en) begin - if (_T_7) begin - if (io_ahb_sig_out_hwrite) begin - buf_state <= 2'h1; - end else begin - buf_state <= 2'h2; - end - end else if (_T_12) begin - if (_T_17) begin - buf_state <= 2'h0; - end else if (io_ahb_sig_out_hwrite) begin - buf_state <= 2'h1; - end else begin - buf_state <= 2'h2; - end - end else if (_T_30) begin - if (io_ahb_sig_in_hresp) begin - buf_state <= 2'h0; - end else begin - buf_state <= 2'h3; - end - end else begin - buf_state <= 2'h0; - end - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - cmdbuf_vld <= 1'h0; - end else begin - cmdbuf_vld <= _T_157 & _T_158; - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - cmdbuf_write <= 1'h0; - end else if (cmdbuf_wr_en) begin - cmdbuf_write <= ahb_hwrite_q; - end - end - always @(posedge ahb_addr_clk or posedge reset) begin - if (reset) begin - ahb_hsize_q <= 3'h0; - end else begin - ahb_hsize_q <= io_ahb_sig_out_hsize; - end - end - always @(posedge ahb_clk or posedge reset) begin - if (reset) begin - ahb_hready_q <= 1'h0; - end else begin - ahb_hready_q <= io_ahb_sig_in_hready & io_ahb_hreadyin; - end - end - always @(posedge ahb_clk or posedge reset) begin - if (reset) begin - ahb_hresp_q <= 1'h0; - end else begin - ahb_hresp_q <= io_ahb_sig_in_hresp; - end - end - always @(posedge ahb_clk or posedge reset) begin - if (reset) begin - buf_read_error <= 1'h0; - end else if (_T_7) begin - buf_read_error <= 1'h0; - end else if (_T_12) begin - buf_read_error <= 1'h0; - end else if (_T_30) begin - buf_read_error <= 1'h0; - end else begin - buf_read_error <= _GEN_3; - end - end - always @(posedge buf_rdata_clk or posedge reset) begin - if (reset) begin - buf_rdata <= 64'h0; - end else begin - buf_rdata <= io_axi_r_bits_data; - end - end - always @(posedge ahb_clk or posedge reset) begin - if (reset) begin - ahb_htrans_q <= 2'h0; - end else begin - ahb_htrans_q <= _T_89 & io_ahb_sig_out_htrans; - end - end - always @(posedge ahb_addr_clk or posedge reset) begin - if (reset) begin - ahb_hwrite_q <= 1'h0; - end else begin - ahb_hwrite_q <= io_ahb_sig_out_hwrite; - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - _T_164 <= 3'h0; - end else if (cmdbuf_wr_en) begin - _T_164 <= ahb_hsize_q; - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - cmdbuf_wstrb <= 8'h0; - end else if (cmdbuf_wr_en) begin - cmdbuf_wstrb <= master_wstrb; - end - end - always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin - if (reset) begin - cmdbuf_addr <= 32'h0; - end else begin - cmdbuf_addr <= ahb_haddr_q; - end - end - always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin - if (reset) begin - cmdbuf_wdata <= 64'h0; - end else begin - cmdbuf_wdata <= io_ahb_sig_out_hwdata; - end - end -endmodule module quasar( input clock, input reset, - input [63:0] io_lsu_ahb_in_hrdata, - input io_lsu_ahb_in_hready, - input io_lsu_ahb_in_hresp, - output [31:0] io_lsu_ahb_out_haddr, - output [2:0] io_lsu_ahb_out_hsize, - output [1:0] io_lsu_ahb_out_htrans, - output io_lsu_ahb_out_hwrite, - output [63:0] io_lsu_ahb_out_hwdata, - input [63:0] io_ifu_ahb_in_hrdata, - input io_ifu_ahb_in_hready, - input io_ifu_ahb_in_hresp, - output [31:0] io_ifu_ahb_out_haddr, - output [2:0] io_ifu_ahb_out_hsize, - output [1:0] io_ifu_ahb_out_htrans, - output io_ifu_ahb_out_hwrite, - output [63:0] io_ifu_ahb_out_hwdata, - input [63:0] io_sb_ahb_in_hrdata, - input io_sb_ahb_in_hready, - input io_sb_ahb_in_hresp, - output [31:0] io_sb_ahb_out_haddr, - output [2:0] io_sb_ahb_out_hsize, - output [1:0] io_sb_ahb_out_htrans, - output io_sb_ahb_out_hwrite, - output [63:0] io_sb_ahb_out_hwdata, - output [63:0] io_dma_ahb_sig_in_hrdata, - output io_dma_ahb_sig_in_hready, - output io_dma_ahb_sig_in_hresp, - input [31:0] io_dma_ahb_sig_out_haddr, - input [2:0] io_dma_ahb_sig_out_hsize, - input [1:0] io_dma_ahb_sig_out_htrans, - input io_dma_ahb_sig_out_hwrite, - input [63:0] io_dma_ahb_sig_out_hwdata, - input io_dma_ahb_hsel, - input io_dma_ahb_hreadyin, + input io_lsu_axi_aw_ready, + output io_lsu_axi_aw_valid, + output [2:0] io_lsu_axi_aw_bits_id, + output [31:0] io_lsu_axi_aw_bits_addr, + output [3:0] io_lsu_axi_aw_bits_region, + output [2:0] io_lsu_axi_aw_bits_size, + output [3:0] io_lsu_axi_aw_bits_cache, + input io_lsu_axi_w_ready, + output io_lsu_axi_w_valid, + output [63:0] io_lsu_axi_w_bits_data, + output [7:0] io_lsu_axi_w_bits_strb, + input io_lsu_axi_b_valid, + input [2:0] io_lsu_axi_b_bits_id, + input io_lsu_axi_ar_ready, + output io_lsu_axi_ar_valid, + output [2:0] io_lsu_axi_ar_bits_id, + output [31:0] io_lsu_axi_ar_bits_addr, + output [3:0] io_lsu_axi_ar_bits_region, + output [2:0] io_lsu_axi_ar_bits_size, + output [3:0] io_lsu_axi_ar_bits_cache, + input io_lsu_axi_r_valid, + input [2:0] io_lsu_axi_r_bits_id, + input [63:0] io_lsu_axi_r_bits_data, + input [1:0] io_lsu_axi_r_bits_resp, + input io_ifu_axi_ar_ready, + output io_ifu_axi_ar_valid, + output [2:0] io_ifu_axi_ar_bits_id, + output [31:0] io_ifu_axi_ar_bits_addr, + output [3:0] io_ifu_axi_ar_bits_region, + input io_ifu_axi_r_valid, + input [2:0] io_ifu_axi_r_bits_id, + input [63:0] io_ifu_axi_r_bits_data, + input [1:0] io_ifu_axi_r_bits_resp, + input io_sb_axi_aw_ready, + output io_sb_axi_aw_valid, + output [31:0] io_sb_axi_aw_bits_addr, + output [3:0] io_sb_axi_aw_bits_region, + output [2:0] io_sb_axi_aw_bits_size, + input io_sb_axi_w_ready, + output io_sb_axi_w_valid, + output [63:0] io_sb_axi_w_bits_data, + output [7:0] io_sb_axi_w_bits_strb, + input io_sb_axi_b_valid, + input [1:0] io_sb_axi_b_bits_resp, + input io_sb_axi_ar_ready, + output io_sb_axi_ar_valid, + output [31:0] io_sb_axi_ar_bits_addr, + output [3:0] io_sb_axi_ar_bits_region, + output [2:0] io_sb_axi_ar_bits_size, + input io_sb_axi_r_valid, + input [63:0] io_sb_axi_r_bits_data, + input [1:0] io_sb_axi_r_bits_resp, + output io_dma_axi_aw_ready, + input io_dma_axi_aw_valid, + input io_dma_axi_aw_bits_id, + input [31:0] io_dma_axi_aw_bits_addr, + input [2:0] io_dma_axi_aw_bits_size, + output io_dma_axi_w_ready, + input io_dma_axi_w_valid, + input [63:0] io_dma_axi_w_bits_data, + input [7:0] io_dma_axi_w_bits_strb, + input io_dma_axi_b_ready, + output io_dma_axi_b_valid, + output [1:0] io_dma_axi_b_bits_resp, + output io_dma_axi_b_bits_id, + output io_dma_axi_ar_ready, + input io_dma_axi_ar_valid, + input io_dma_axi_ar_bits_id, + input [31:0] io_dma_axi_ar_bits_addr, + input [2:0] io_dma_axi_ar_bits_size, + input io_dma_axi_r_ready, + output io_dma_axi_r_valid, + output io_dma_axi_r_bits_id, + output [63:0] io_dma_axi_r_bits_data, + output [1:0] io_dma_axi_r_bits_resp, input io_dbg_rst_l, input [30:0] io_rst_vec, input io_nmi_int, @@ -83037,6 +80777,7 @@ module quasar( wire ifu_io_ifu_ar_valid; // @[quasar.scala 74:19] wire [2:0] ifu_io_ifu_ar_bits_id; // @[quasar.scala 74:19] wire [31:0] ifu_io_ifu_ar_bits_addr; // @[quasar.scala 74:19] + wire [3:0] ifu_io_ifu_ar_bits_region; // @[quasar.scala 74:19] wire ifu_io_ifu_r_valid; // @[quasar.scala 74:19] wire [2:0] ifu_io_ifu_r_bits_id; // @[quasar.scala 74:19] wire [63:0] ifu_io_ifu_r_bits_data; // @[quasar.scala 74:19] @@ -83157,7 +80898,6 @@ module quasar( wire [31:0] dec_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar.scala 75:19] wire dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 75:19] wire dec_io_dec_tlu_lsu_clk_override; // @[quasar.scala 75:19] - wire dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 75:19] wire dec_io_dec_tlu_pic_clk_override; // @[quasar.scala 75:19] wire dec_io_dec_tlu_dccm_clk_override; // @[quasar.scala 75:19] wire dec_io_dec_tlu_icm_clk_override; // @[quasar.scala 75:19] @@ -83295,6 +81035,7 @@ module quasar( wire dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 75:19] wire dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 75:19] wire dec_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 75:19] + wire dec_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[quasar.scala 75:19] wire dec_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 75:19] wire dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[quasar.scala 75:19] wire dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[quasar.scala 75:19] @@ -83349,6 +81090,7 @@ module quasar( wire dbg_io_sb_axi_aw_ready; // @[quasar.scala 76:19] wire dbg_io_sb_axi_aw_valid; // @[quasar.scala 76:19] wire [31:0] dbg_io_sb_axi_aw_bits_addr; // @[quasar.scala 76:19] + wire [3:0] dbg_io_sb_axi_aw_bits_region; // @[quasar.scala 76:19] wire [2:0] dbg_io_sb_axi_aw_bits_size; // @[quasar.scala 76:19] wire dbg_io_sb_axi_w_ready; // @[quasar.scala 76:19] wire dbg_io_sb_axi_w_valid; // @[quasar.scala 76:19] @@ -83360,6 +81102,7 @@ module quasar( wire dbg_io_sb_axi_ar_ready; // @[quasar.scala 76:19] wire dbg_io_sb_axi_ar_valid; // @[quasar.scala 76:19] wire [31:0] dbg_io_sb_axi_ar_bits_addr; // @[quasar.scala 76:19] + wire [3:0] dbg_io_sb_axi_ar_bits_region; // @[quasar.scala 76:19] wire [2:0] dbg_io_sb_axi_ar_bits_size; // @[quasar.scala 76:19] wire dbg_io_sb_axi_r_ready; // @[quasar.scala 76:19] wire dbg_io_sb_axi_r_valid; // @[quasar.scala 76:19] @@ -83514,6 +81257,7 @@ module quasar( wire lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 78:19] wire lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 78:19] wire lsu_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 78:19] + wire lsu_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[quasar.scala 78:19] wire lsu_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 78:19] wire lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[quasar.scala 78:19] wire lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[quasar.scala 78:19] @@ -83542,7 +81286,9 @@ module quasar( wire lsu_io_axi_aw_valid; // @[quasar.scala 78:19] wire [2:0] lsu_io_axi_aw_bits_id; // @[quasar.scala 78:19] wire [31:0] lsu_io_axi_aw_bits_addr; // @[quasar.scala 78:19] + wire [3:0] lsu_io_axi_aw_bits_region; // @[quasar.scala 78:19] wire [2:0] lsu_io_axi_aw_bits_size; // @[quasar.scala 78:19] + wire [3:0] lsu_io_axi_aw_bits_cache; // @[quasar.scala 78:19] wire lsu_io_axi_w_ready; // @[quasar.scala 78:19] wire lsu_io_axi_w_valid; // @[quasar.scala 78:19] wire [63:0] lsu_io_axi_w_bits_data; // @[quasar.scala 78:19] @@ -83553,7 +81299,9 @@ module quasar( wire lsu_io_axi_ar_valid; // @[quasar.scala 78:19] wire [2:0] lsu_io_axi_ar_bits_id; // @[quasar.scala 78:19] wire [31:0] lsu_io_axi_ar_bits_addr; // @[quasar.scala 78:19] + wire [3:0] lsu_io_axi_ar_bits_region; // @[quasar.scala 78:19] wire [2:0] lsu_io_axi_ar_bits_size; // @[quasar.scala 78:19] + wire [3:0] lsu_io_axi_ar_bits_cache; // @[quasar.scala 78:19] wire lsu_io_axi_r_valid; // @[quasar.scala 78:19] wire [2:0] lsu_io_axi_r_bits_id; // @[quasar.scala 78:19] wire [63:0] lsu_io_axi_r_bits_data; // @[quasar.scala 78:19] @@ -83667,18 +81415,25 @@ module quasar( wire dma_ctrl_io_iccm_ready; // @[quasar.scala 80:24] wire dma_ctrl_io_dma_axi_aw_ready; // @[quasar.scala 80:24] wire dma_ctrl_io_dma_axi_aw_valid; // @[quasar.scala 80:24] + wire dma_ctrl_io_dma_axi_aw_bits_id; // @[quasar.scala 80:24] wire [31:0] dma_ctrl_io_dma_axi_aw_bits_addr; // @[quasar.scala 80:24] wire [2:0] dma_ctrl_io_dma_axi_aw_bits_size; // @[quasar.scala 80:24] wire dma_ctrl_io_dma_axi_w_ready; // @[quasar.scala 80:24] wire dma_ctrl_io_dma_axi_w_valid; // @[quasar.scala 80:24] wire [63:0] dma_ctrl_io_dma_axi_w_bits_data; // @[quasar.scala 80:24] wire [7:0] dma_ctrl_io_dma_axi_w_bits_strb; // @[quasar.scala 80:24] + wire dma_ctrl_io_dma_axi_b_ready; // @[quasar.scala 80:24] wire dma_ctrl_io_dma_axi_b_valid; // @[quasar.scala 80:24] + wire [1:0] dma_ctrl_io_dma_axi_b_bits_resp; // @[quasar.scala 80:24] + wire dma_ctrl_io_dma_axi_b_bits_id; // @[quasar.scala 80:24] wire dma_ctrl_io_dma_axi_ar_ready; // @[quasar.scala 80:24] wire dma_ctrl_io_dma_axi_ar_valid; // @[quasar.scala 80:24] + wire dma_ctrl_io_dma_axi_ar_bits_id; // @[quasar.scala 80:24] wire [31:0] dma_ctrl_io_dma_axi_ar_bits_addr; // @[quasar.scala 80:24] wire [2:0] dma_ctrl_io_dma_axi_ar_bits_size; // @[quasar.scala 80:24] + wire dma_ctrl_io_dma_axi_r_ready; // @[quasar.scala 80:24] wire dma_ctrl_io_dma_axi_r_valid; // @[quasar.scala 80:24] + wire dma_ctrl_io_dma_axi_r_bits_id; // @[quasar.scala 80:24] wire [63:0] dma_ctrl_io_dma_axi_r_bits_data; // @[quasar.scala 80:24] wire [1:0] dma_ctrl_io_dma_axi_r_bits_resp; // @[quasar.scala 80:24] wire dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[quasar.scala 80:24] @@ -83709,130 +81464,6 @@ module quasar( wire rvclkhdr_1_io_clk; // @[lib.scala 343:22] wire rvclkhdr_1_io_en; // @[lib.scala 343:22] wire rvclkhdr_1_io_scan_mode; // @[lib.scala 343:22] - wire axi4_to_ahb_clock; // @[quasar.scala 245:32] - wire axi4_to_ahb_reset; // @[quasar.scala 245:32] - wire axi4_to_ahb_io_scan_mode; // @[quasar.scala 245:32] - wire axi4_to_ahb_io_bus_clk_en; // @[quasar.scala 245:32] - wire axi4_to_ahb_io_clk_override; // @[quasar.scala 245:32] - wire axi4_to_ahb_io_axi_aw_ready; // @[quasar.scala 245:32] - wire axi4_to_ahb_io_axi_aw_valid; // @[quasar.scala 245:32] - wire [31:0] axi4_to_ahb_io_axi_aw_bits_addr; // @[quasar.scala 245:32] - wire [2:0] axi4_to_ahb_io_axi_aw_bits_size; // @[quasar.scala 245:32] - wire axi4_to_ahb_io_axi_w_ready; // @[quasar.scala 245:32] - wire axi4_to_ahb_io_axi_w_valid; // @[quasar.scala 245:32] - wire [63:0] axi4_to_ahb_io_axi_w_bits_data; // @[quasar.scala 245:32] - wire [7:0] axi4_to_ahb_io_axi_w_bits_strb; // @[quasar.scala 245:32] - wire axi4_to_ahb_io_axi_b_valid; // @[quasar.scala 245:32] - wire [1:0] axi4_to_ahb_io_axi_b_bits_resp; // @[quasar.scala 245:32] - wire axi4_to_ahb_io_axi_ar_ready; // @[quasar.scala 245:32] - wire axi4_to_ahb_io_axi_ar_valid; // @[quasar.scala 245:32] - wire [31:0] axi4_to_ahb_io_axi_ar_bits_addr; // @[quasar.scala 245:32] - wire [2:0] axi4_to_ahb_io_axi_ar_bits_size; // @[quasar.scala 245:32] - wire axi4_to_ahb_io_axi_r_valid; // @[quasar.scala 245:32] - wire [63:0] axi4_to_ahb_io_axi_r_bits_data; // @[quasar.scala 245:32] - wire [1:0] axi4_to_ahb_io_axi_r_bits_resp; // @[quasar.scala 245:32] - wire [63:0] axi4_to_ahb_io_ahb_in_hrdata; // @[quasar.scala 245:32] - wire axi4_to_ahb_io_ahb_in_hready; // @[quasar.scala 245:32] - wire axi4_to_ahb_io_ahb_in_hresp; // @[quasar.scala 245:32] - wire [31:0] axi4_to_ahb_io_ahb_out_haddr; // @[quasar.scala 245:32] - wire [2:0] axi4_to_ahb_io_ahb_out_hsize; // @[quasar.scala 245:32] - wire [1:0] axi4_to_ahb_io_ahb_out_htrans; // @[quasar.scala 245:32] - wire axi4_to_ahb_io_ahb_out_hwrite; // @[quasar.scala 245:32] - wire [63:0] axi4_to_ahb_io_ahb_out_hwdata; // @[quasar.scala 245:32] - wire axi4_to_ahb_1_clock; // @[quasar.scala 246:33] - wire axi4_to_ahb_1_reset; // @[quasar.scala 246:33] - wire axi4_to_ahb_1_io_scan_mode; // @[quasar.scala 246:33] - wire axi4_to_ahb_1_io_bus_clk_en; // @[quasar.scala 246:33] - wire axi4_to_ahb_1_io_clk_override; // @[quasar.scala 246:33] - wire axi4_to_ahb_1_io_axi_aw_ready; // @[quasar.scala 246:33] - wire axi4_to_ahb_1_io_axi_aw_valid; // @[quasar.scala 246:33] - wire [2:0] axi4_to_ahb_1_io_axi_aw_bits_id; // @[quasar.scala 246:33] - wire [31:0] axi4_to_ahb_1_io_axi_aw_bits_addr; // @[quasar.scala 246:33] - wire [2:0] axi4_to_ahb_1_io_axi_aw_bits_size; // @[quasar.scala 246:33] - wire axi4_to_ahb_1_io_axi_w_ready; // @[quasar.scala 246:33] - wire axi4_to_ahb_1_io_axi_w_valid; // @[quasar.scala 246:33] - wire [63:0] axi4_to_ahb_1_io_axi_w_bits_data; // @[quasar.scala 246:33] - wire [7:0] axi4_to_ahb_1_io_axi_w_bits_strb; // @[quasar.scala 246:33] - wire axi4_to_ahb_1_io_axi_b_valid; // @[quasar.scala 246:33] - wire [2:0] axi4_to_ahb_1_io_axi_b_bits_id; // @[quasar.scala 246:33] - wire axi4_to_ahb_1_io_axi_ar_ready; // @[quasar.scala 246:33] - wire axi4_to_ahb_1_io_axi_ar_valid; // @[quasar.scala 246:33] - wire [2:0] axi4_to_ahb_1_io_axi_ar_bits_id; // @[quasar.scala 246:33] - wire [31:0] axi4_to_ahb_1_io_axi_ar_bits_addr; // @[quasar.scala 246:33] - wire [2:0] axi4_to_ahb_1_io_axi_ar_bits_size; // @[quasar.scala 246:33] - wire axi4_to_ahb_1_io_axi_r_valid; // @[quasar.scala 246:33] - wire [2:0] axi4_to_ahb_1_io_axi_r_bits_id; // @[quasar.scala 246:33] - wire [63:0] axi4_to_ahb_1_io_axi_r_bits_data; // @[quasar.scala 246:33] - wire [1:0] axi4_to_ahb_1_io_axi_r_bits_resp; // @[quasar.scala 246:33] - wire [63:0] axi4_to_ahb_1_io_ahb_in_hrdata; // @[quasar.scala 246:33] - wire axi4_to_ahb_1_io_ahb_in_hready; // @[quasar.scala 246:33] - wire axi4_to_ahb_1_io_ahb_in_hresp; // @[quasar.scala 246:33] - wire [31:0] axi4_to_ahb_1_io_ahb_out_haddr; // @[quasar.scala 246:33] - wire [2:0] axi4_to_ahb_1_io_ahb_out_hsize; // @[quasar.scala 246:33] - wire [1:0] axi4_to_ahb_1_io_ahb_out_htrans; // @[quasar.scala 246:33] - wire axi4_to_ahb_1_io_ahb_out_hwrite; // @[quasar.scala 246:33] - wire [63:0] axi4_to_ahb_1_io_ahb_out_hwdata; // @[quasar.scala 246:33] - wire axi4_to_ahb_2_clock; // @[quasar.scala 247:33] - wire axi4_to_ahb_2_reset; // @[quasar.scala 247:33] - wire axi4_to_ahb_2_io_scan_mode; // @[quasar.scala 247:33] - wire axi4_to_ahb_2_io_bus_clk_en; // @[quasar.scala 247:33] - wire axi4_to_ahb_2_io_clk_override; // @[quasar.scala 247:33] - wire axi4_to_ahb_2_io_axi_aw_ready; // @[quasar.scala 247:33] - wire axi4_to_ahb_2_io_axi_aw_valid; // @[quasar.scala 247:33] - wire [2:0] axi4_to_ahb_2_io_axi_aw_bits_id; // @[quasar.scala 247:33] - wire [31:0] axi4_to_ahb_2_io_axi_aw_bits_addr; // @[quasar.scala 247:33] - wire [2:0] axi4_to_ahb_2_io_axi_aw_bits_size; // @[quasar.scala 247:33] - wire axi4_to_ahb_2_io_axi_w_ready; // @[quasar.scala 247:33] - wire axi4_to_ahb_2_io_axi_w_valid; // @[quasar.scala 247:33] - wire [63:0] axi4_to_ahb_2_io_axi_w_bits_data; // @[quasar.scala 247:33] - wire [7:0] axi4_to_ahb_2_io_axi_w_bits_strb; // @[quasar.scala 247:33] - wire axi4_to_ahb_2_io_axi_b_valid; // @[quasar.scala 247:33] - wire [2:0] axi4_to_ahb_2_io_axi_b_bits_id; // @[quasar.scala 247:33] - wire axi4_to_ahb_2_io_axi_ar_ready; // @[quasar.scala 247:33] - wire axi4_to_ahb_2_io_axi_ar_valid; // @[quasar.scala 247:33] - wire [2:0] axi4_to_ahb_2_io_axi_ar_bits_id; // @[quasar.scala 247:33] - wire [31:0] axi4_to_ahb_2_io_axi_ar_bits_addr; // @[quasar.scala 247:33] - wire [2:0] axi4_to_ahb_2_io_axi_ar_bits_size; // @[quasar.scala 247:33] - wire axi4_to_ahb_2_io_axi_r_valid; // @[quasar.scala 247:33] - wire [2:0] axi4_to_ahb_2_io_axi_r_bits_id; // @[quasar.scala 247:33] - wire [63:0] axi4_to_ahb_2_io_axi_r_bits_data; // @[quasar.scala 247:33] - wire [1:0] axi4_to_ahb_2_io_axi_r_bits_resp; // @[quasar.scala 247:33] - wire [63:0] axi4_to_ahb_2_io_ahb_in_hrdata; // @[quasar.scala 247:33] - wire axi4_to_ahb_2_io_ahb_in_hready; // @[quasar.scala 247:33] - wire axi4_to_ahb_2_io_ahb_in_hresp; // @[quasar.scala 247:33] - wire [31:0] axi4_to_ahb_2_io_ahb_out_haddr; // @[quasar.scala 247:33] - wire [2:0] axi4_to_ahb_2_io_ahb_out_hsize; // @[quasar.scala 247:33] - wire [1:0] axi4_to_ahb_2_io_ahb_out_htrans; // @[quasar.scala 247:33] - wire axi4_to_ahb_2_io_ahb_out_hwrite; // @[quasar.scala 247:33] - wire [63:0] axi4_to_ahb_2_io_ahb_out_hwdata; // @[quasar.scala 247:33] - wire ahb_to_axi4_clock; // @[quasar.scala 248:33] - wire ahb_to_axi4_reset; // @[quasar.scala 248:33] - wire ahb_to_axi4_io_scan_mode; // @[quasar.scala 248:33] - wire ahb_to_axi4_io_bus_clk_en; // @[quasar.scala 248:33] - wire ahb_to_axi4_io_axi_aw_ready; // @[quasar.scala 248:33] - wire ahb_to_axi4_io_axi_aw_valid; // @[quasar.scala 248:33] - wire [31:0] ahb_to_axi4_io_axi_aw_bits_addr; // @[quasar.scala 248:33] - wire [2:0] ahb_to_axi4_io_axi_aw_bits_size; // @[quasar.scala 248:33] - wire ahb_to_axi4_io_axi_w_valid; // @[quasar.scala 248:33] - wire [63:0] ahb_to_axi4_io_axi_w_bits_data; // @[quasar.scala 248:33] - wire [7:0] ahb_to_axi4_io_axi_w_bits_strb; // @[quasar.scala 248:33] - wire ahb_to_axi4_io_axi_ar_ready; // @[quasar.scala 248:33] - wire ahb_to_axi4_io_axi_ar_valid; // @[quasar.scala 248:33] - wire [31:0] ahb_to_axi4_io_axi_ar_bits_addr; // @[quasar.scala 248:33] - wire [2:0] ahb_to_axi4_io_axi_ar_bits_size; // @[quasar.scala 248:33] - wire ahb_to_axi4_io_axi_r_valid; // @[quasar.scala 248:33] - wire [63:0] ahb_to_axi4_io_axi_r_bits_data; // @[quasar.scala 248:33] - wire [1:0] ahb_to_axi4_io_axi_r_bits_resp; // @[quasar.scala 248:33] - wire [63:0] ahb_to_axi4_io_ahb_sig_in_hrdata; // @[quasar.scala 248:33] - wire ahb_to_axi4_io_ahb_sig_in_hready; // @[quasar.scala 248:33] - wire ahb_to_axi4_io_ahb_sig_in_hresp; // @[quasar.scala 248:33] - wire [31:0] ahb_to_axi4_io_ahb_sig_out_haddr; // @[quasar.scala 248:33] - wire [2:0] ahb_to_axi4_io_ahb_sig_out_hsize; // @[quasar.scala 248:33] - wire [1:0] ahb_to_axi4_io_ahb_sig_out_htrans; // @[quasar.scala 248:33] - wire ahb_to_axi4_io_ahb_sig_out_hwrite; // @[quasar.scala 248:33] - wire [63:0] ahb_to_axi4_io_ahb_sig_out_hwdata; // @[quasar.scala 248:33] - wire ahb_to_axi4_io_ahb_hsel; // @[quasar.scala 248:33] - wire ahb_to_axi4_io_ahb_hreadyin; // @[quasar.scala 248:33] wire _T_1 = dbg_io_dbg_core_rst_l; // @[quasar.scala 82:67] wire _T_2 = _T_1 | io_scan_mode; // @[quasar.scala 82:70] wire _T_5 = ~dec_io_dec_pause_state_cg; // @[quasar.scala 83:23] @@ -83945,6 +81576,7 @@ module quasar( .io_ifu_ar_valid(ifu_io_ifu_ar_valid), .io_ifu_ar_bits_id(ifu_io_ifu_ar_bits_id), .io_ifu_ar_bits_addr(ifu_io_ifu_ar_bits_addr), + .io_ifu_ar_bits_region(ifu_io_ifu_ar_bits_region), .io_ifu_r_valid(ifu_io_ifu_r_valid), .io_ifu_r_bits_id(ifu_io_ifu_r_bits_id), .io_ifu_r_bits_data(ifu_io_ifu_r_bits_data), @@ -84067,7 +81699,6 @@ module quasar( .io_rv_trace_pkt_rv_i_tval_ip(dec_io_rv_trace_pkt_rv_i_tval_ip), .io_dec_tlu_misc_clk_override(dec_io_dec_tlu_misc_clk_override), .io_dec_tlu_lsu_clk_override(dec_io_dec_tlu_lsu_clk_override), - .io_dec_tlu_bus_clk_override(dec_io_dec_tlu_bus_clk_override), .io_dec_tlu_pic_clk_override(dec_io_dec_tlu_pic_clk_override), .io_dec_tlu_dccm_clk_override(dec_io_dec_tlu_dccm_clk_override), .io_dec_tlu_icm_clk_override(dec_io_dec_tlu_icm_clk_override), @@ -84205,6 +81836,7 @@ module quasar( .io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error(dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error), .io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy(dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy), .io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable(dec_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable), + .io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable(dec_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable), .io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable(dec_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable), .io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any(dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any), .io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any(dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any), @@ -84261,6 +81893,7 @@ module quasar( .io_sb_axi_aw_ready(dbg_io_sb_axi_aw_ready), .io_sb_axi_aw_valid(dbg_io_sb_axi_aw_valid), .io_sb_axi_aw_bits_addr(dbg_io_sb_axi_aw_bits_addr), + .io_sb_axi_aw_bits_region(dbg_io_sb_axi_aw_bits_region), .io_sb_axi_aw_bits_size(dbg_io_sb_axi_aw_bits_size), .io_sb_axi_w_ready(dbg_io_sb_axi_w_ready), .io_sb_axi_w_valid(dbg_io_sb_axi_w_valid), @@ -84272,6 +81905,7 @@ module quasar( .io_sb_axi_ar_ready(dbg_io_sb_axi_ar_ready), .io_sb_axi_ar_valid(dbg_io_sb_axi_ar_valid), .io_sb_axi_ar_bits_addr(dbg_io_sb_axi_ar_bits_addr), + .io_sb_axi_ar_bits_region(dbg_io_sb_axi_ar_bits_region), .io_sb_axi_ar_bits_size(dbg_io_sb_axi_ar_bits_size), .io_sb_axi_r_ready(dbg_io_sb_axi_r_ready), .io_sb_axi_r_valid(dbg_io_sb_axi_r_valid), @@ -84430,6 +82064,7 @@ module quasar( .io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error(lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error), .io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy(lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy), .io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable(lsu_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable), + .io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable(lsu_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable), .io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable(lsu_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable), .io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any(lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any), .io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any(lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any), @@ -84458,7 +82093,9 @@ module quasar( .io_axi_aw_valid(lsu_io_axi_aw_valid), .io_axi_aw_bits_id(lsu_io_axi_aw_bits_id), .io_axi_aw_bits_addr(lsu_io_axi_aw_bits_addr), + .io_axi_aw_bits_region(lsu_io_axi_aw_bits_region), .io_axi_aw_bits_size(lsu_io_axi_aw_bits_size), + .io_axi_aw_bits_cache(lsu_io_axi_aw_bits_cache), .io_axi_w_ready(lsu_io_axi_w_ready), .io_axi_w_valid(lsu_io_axi_w_valid), .io_axi_w_bits_data(lsu_io_axi_w_bits_data), @@ -84469,7 +82106,9 @@ module quasar( .io_axi_ar_valid(lsu_io_axi_ar_valid), .io_axi_ar_bits_id(lsu_io_axi_ar_bits_id), .io_axi_ar_bits_addr(lsu_io_axi_ar_bits_addr), + .io_axi_ar_bits_region(lsu_io_axi_ar_bits_region), .io_axi_ar_bits_size(lsu_io_axi_ar_bits_size), + .io_axi_ar_bits_cache(lsu_io_axi_ar_bits_cache), .io_axi_r_valid(lsu_io_axi_r_valid), .io_axi_r_bits_id(lsu_io_axi_r_bits_id), .io_axi_r_bits_data(lsu_io_axi_r_bits_data), @@ -84587,18 +82226,25 @@ module quasar( .io_iccm_ready(dma_ctrl_io_iccm_ready), .io_dma_axi_aw_ready(dma_ctrl_io_dma_axi_aw_ready), .io_dma_axi_aw_valid(dma_ctrl_io_dma_axi_aw_valid), + .io_dma_axi_aw_bits_id(dma_ctrl_io_dma_axi_aw_bits_id), .io_dma_axi_aw_bits_addr(dma_ctrl_io_dma_axi_aw_bits_addr), .io_dma_axi_aw_bits_size(dma_ctrl_io_dma_axi_aw_bits_size), .io_dma_axi_w_ready(dma_ctrl_io_dma_axi_w_ready), .io_dma_axi_w_valid(dma_ctrl_io_dma_axi_w_valid), .io_dma_axi_w_bits_data(dma_ctrl_io_dma_axi_w_bits_data), .io_dma_axi_w_bits_strb(dma_ctrl_io_dma_axi_w_bits_strb), + .io_dma_axi_b_ready(dma_ctrl_io_dma_axi_b_ready), .io_dma_axi_b_valid(dma_ctrl_io_dma_axi_b_valid), + .io_dma_axi_b_bits_resp(dma_ctrl_io_dma_axi_b_bits_resp), + .io_dma_axi_b_bits_id(dma_ctrl_io_dma_axi_b_bits_id), .io_dma_axi_ar_ready(dma_ctrl_io_dma_axi_ar_ready), .io_dma_axi_ar_valid(dma_ctrl_io_dma_axi_ar_valid), + .io_dma_axi_ar_bits_id(dma_ctrl_io_dma_axi_ar_bits_id), .io_dma_axi_ar_bits_addr(dma_ctrl_io_dma_axi_ar_bits_addr), .io_dma_axi_ar_bits_size(dma_ctrl_io_dma_axi_ar_bits_size), + .io_dma_axi_r_ready(dma_ctrl_io_dma_axi_r_ready), .io_dma_axi_r_valid(dma_ctrl_io_dma_axi_r_valid), + .io_dma_axi_r_bits_id(dma_ctrl_io_dma_axi_r_bits_id), .io_dma_axi_r_bits_data(dma_ctrl_io_dma_axi_r_bits_data), .io_dma_axi_r_bits_resp(dma_ctrl_io_dma_axi_r_bits_resp), .io_lsu_dma_dma_lsc_ctl_dma_dccm_req(dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_dccm_req), @@ -84634,676 +82280,500 @@ module quasar( .io_en(rvclkhdr_1_io_en), .io_scan_mode(rvclkhdr_1_io_scan_mode) ); - axi4_to_ahb axi4_to_ahb ( // @[quasar.scala 245:32] - .clock(axi4_to_ahb_clock), - .reset(axi4_to_ahb_reset), - .io_scan_mode(axi4_to_ahb_io_scan_mode), - .io_bus_clk_en(axi4_to_ahb_io_bus_clk_en), - .io_clk_override(axi4_to_ahb_io_clk_override), - .io_axi_aw_ready(axi4_to_ahb_io_axi_aw_ready), - .io_axi_aw_valid(axi4_to_ahb_io_axi_aw_valid), - .io_axi_aw_bits_addr(axi4_to_ahb_io_axi_aw_bits_addr), - .io_axi_aw_bits_size(axi4_to_ahb_io_axi_aw_bits_size), - .io_axi_w_ready(axi4_to_ahb_io_axi_w_ready), - .io_axi_w_valid(axi4_to_ahb_io_axi_w_valid), - .io_axi_w_bits_data(axi4_to_ahb_io_axi_w_bits_data), - .io_axi_w_bits_strb(axi4_to_ahb_io_axi_w_bits_strb), - .io_axi_b_valid(axi4_to_ahb_io_axi_b_valid), - .io_axi_b_bits_resp(axi4_to_ahb_io_axi_b_bits_resp), - .io_axi_ar_ready(axi4_to_ahb_io_axi_ar_ready), - .io_axi_ar_valid(axi4_to_ahb_io_axi_ar_valid), - .io_axi_ar_bits_addr(axi4_to_ahb_io_axi_ar_bits_addr), - .io_axi_ar_bits_size(axi4_to_ahb_io_axi_ar_bits_size), - .io_axi_r_valid(axi4_to_ahb_io_axi_r_valid), - .io_axi_r_bits_data(axi4_to_ahb_io_axi_r_bits_data), - .io_axi_r_bits_resp(axi4_to_ahb_io_axi_r_bits_resp), - .io_ahb_in_hrdata(axi4_to_ahb_io_ahb_in_hrdata), - .io_ahb_in_hready(axi4_to_ahb_io_ahb_in_hready), - .io_ahb_in_hresp(axi4_to_ahb_io_ahb_in_hresp), - .io_ahb_out_haddr(axi4_to_ahb_io_ahb_out_haddr), - .io_ahb_out_hsize(axi4_to_ahb_io_ahb_out_hsize), - .io_ahb_out_htrans(axi4_to_ahb_io_ahb_out_htrans), - .io_ahb_out_hwrite(axi4_to_ahb_io_ahb_out_hwrite), - .io_ahb_out_hwdata(axi4_to_ahb_io_ahb_out_hwdata) - ); - axi4_to_ahb_1 axi4_to_ahb_1 ( // @[quasar.scala 246:33] - .clock(axi4_to_ahb_1_clock), - .reset(axi4_to_ahb_1_reset), - .io_scan_mode(axi4_to_ahb_1_io_scan_mode), - .io_bus_clk_en(axi4_to_ahb_1_io_bus_clk_en), - .io_clk_override(axi4_to_ahb_1_io_clk_override), - .io_axi_aw_ready(axi4_to_ahb_1_io_axi_aw_ready), - .io_axi_aw_valid(axi4_to_ahb_1_io_axi_aw_valid), - .io_axi_aw_bits_id(axi4_to_ahb_1_io_axi_aw_bits_id), - .io_axi_aw_bits_addr(axi4_to_ahb_1_io_axi_aw_bits_addr), - .io_axi_aw_bits_size(axi4_to_ahb_1_io_axi_aw_bits_size), - .io_axi_w_ready(axi4_to_ahb_1_io_axi_w_ready), - .io_axi_w_valid(axi4_to_ahb_1_io_axi_w_valid), - .io_axi_w_bits_data(axi4_to_ahb_1_io_axi_w_bits_data), - .io_axi_w_bits_strb(axi4_to_ahb_1_io_axi_w_bits_strb), - .io_axi_b_valid(axi4_to_ahb_1_io_axi_b_valid), - .io_axi_b_bits_id(axi4_to_ahb_1_io_axi_b_bits_id), - .io_axi_ar_ready(axi4_to_ahb_1_io_axi_ar_ready), - .io_axi_ar_valid(axi4_to_ahb_1_io_axi_ar_valid), - .io_axi_ar_bits_id(axi4_to_ahb_1_io_axi_ar_bits_id), - .io_axi_ar_bits_addr(axi4_to_ahb_1_io_axi_ar_bits_addr), - .io_axi_ar_bits_size(axi4_to_ahb_1_io_axi_ar_bits_size), - .io_axi_r_valid(axi4_to_ahb_1_io_axi_r_valid), - .io_axi_r_bits_id(axi4_to_ahb_1_io_axi_r_bits_id), - .io_axi_r_bits_data(axi4_to_ahb_1_io_axi_r_bits_data), - .io_axi_r_bits_resp(axi4_to_ahb_1_io_axi_r_bits_resp), - .io_ahb_in_hrdata(axi4_to_ahb_1_io_ahb_in_hrdata), - .io_ahb_in_hready(axi4_to_ahb_1_io_ahb_in_hready), - .io_ahb_in_hresp(axi4_to_ahb_1_io_ahb_in_hresp), - .io_ahb_out_haddr(axi4_to_ahb_1_io_ahb_out_haddr), - .io_ahb_out_hsize(axi4_to_ahb_1_io_ahb_out_hsize), - .io_ahb_out_htrans(axi4_to_ahb_1_io_ahb_out_htrans), - .io_ahb_out_hwrite(axi4_to_ahb_1_io_ahb_out_hwrite), - .io_ahb_out_hwdata(axi4_to_ahb_1_io_ahb_out_hwdata) - ); - axi4_to_ahb_1 axi4_to_ahb_2 ( // @[quasar.scala 247:33] - .clock(axi4_to_ahb_2_clock), - .reset(axi4_to_ahb_2_reset), - .io_scan_mode(axi4_to_ahb_2_io_scan_mode), - .io_bus_clk_en(axi4_to_ahb_2_io_bus_clk_en), - .io_clk_override(axi4_to_ahb_2_io_clk_override), - .io_axi_aw_ready(axi4_to_ahb_2_io_axi_aw_ready), - .io_axi_aw_valid(axi4_to_ahb_2_io_axi_aw_valid), - .io_axi_aw_bits_id(axi4_to_ahb_2_io_axi_aw_bits_id), - .io_axi_aw_bits_addr(axi4_to_ahb_2_io_axi_aw_bits_addr), - .io_axi_aw_bits_size(axi4_to_ahb_2_io_axi_aw_bits_size), - .io_axi_w_ready(axi4_to_ahb_2_io_axi_w_ready), - .io_axi_w_valid(axi4_to_ahb_2_io_axi_w_valid), - .io_axi_w_bits_data(axi4_to_ahb_2_io_axi_w_bits_data), - .io_axi_w_bits_strb(axi4_to_ahb_2_io_axi_w_bits_strb), - .io_axi_b_valid(axi4_to_ahb_2_io_axi_b_valid), - .io_axi_b_bits_id(axi4_to_ahb_2_io_axi_b_bits_id), - .io_axi_ar_ready(axi4_to_ahb_2_io_axi_ar_ready), - .io_axi_ar_valid(axi4_to_ahb_2_io_axi_ar_valid), - .io_axi_ar_bits_id(axi4_to_ahb_2_io_axi_ar_bits_id), - .io_axi_ar_bits_addr(axi4_to_ahb_2_io_axi_ar_bits_addr), - .io_axi_ar_bits_size(axi4_to_ahb_2_io_axi_ar_bits_size), - .io_axi_r_valid(axi4_to_ahb_2_io_axi_r_valid), - .io_axi_r_bits_id(axi4_to_ahb_2_io_axi_r_bits_id), - .io_axi_r_bits_data(axi4_to_ahb_2_io_axi_r_bits_data), - .io_axi_r_bits_resp(axi4_to_ahb_2_io_axi_r_bits_resp), - .io_ahb_in_hrdata(axi4_to_ahb_2_io_ahb_in_hrdata), - .io_ahb_in_hready(axi4_to_ahb_2_io_ahb_in_hready), - .io_ahb_in_hresp(axi4_to_ahb_2_io_ahb_in_hresp), - .io_ahb_out_haddr(axi4_to_ahb_2_io_ahb_out_haddr), - .io_ahb_out_hsize(axi4_to_ahb_2_io_ahb_out_hsize), - .io_ahb_out_htrans(axi4_to_ahb_2_io_ahb_out_htrans), - .io_ahb_out_hwrite(axi4_to_ahb_2_io_ahb_out_hwrite), - .io_ahb_out_hwdata(axi4_to_ahb_2_io_ahb_out_hwdata) - ); - ahb_to_axi4 ahb_to_axi4 ( // @[quasar.scala 248:33] - .clock(ahb_to_axi4_clock), - .reset(ahb_to_axi4_reset), - .io_scan_mode(ahb_to_axi4_io_scan_mode), - .io_bus_clk_en(ahb_to_axi4_io_bus_clk_en), - .io_axi_aw_ready(ahb_to_axi4_io_axi_aw_ready), - .io_axi_aw_valid(ahb_to_axi4_io_axi_aw_valid), - .io_axi_aw_bits_addr(ahb_to_axi4_io_axi_aw_bits_addr), - .io_axi_aw_bits_size(ahb_to_axi4_io_axi_aw_bits_size), - .io_axi_w_valid(ahb_to_axi4_io_axi_w_valid), - .io_axi_w_bits_data(ahb_to_axi4_io_axi_w_bits_data), - .io_axi_w_bits_strb(ahb_to_axi4_io_axi_w_bits_strb), - .io_axi_ar_ready(ahb_to_axi4_io_axi_ar_ready), - .io_axi_ar_valid(ahb_to_axi4_io_axi_ar_valid), - .io_axi_ar_bits_addr(ahb_to_axi4_io_axi_ar_bits_addr), - .io_axi_ar_bits_size(ahb_to_axi4_io_axi_ar_bits_size), - .io_axi_r_valid(ahb_to_axi4_io_axi_r_valid), - .io_axi_r_bits_data(ahb_to_axi4_io_axi_r_bits_data), - .io_axi_r_bits_resp(ahb_to_axi4_io_axi_r_bits_resp), - .io_ahb_sig_in_hrdata(ahb_to_axi4_io_ahb_sig_in_hrdata), - .io_ahb_sig_in_hready(ahb_to_axi4_io_ahb_sig_in_hready), - .io_ahb_sig_in_hresp(ahb_to_axi4_io_ahb_sig_in_hresp), - .io_ahb_sig_out_haddr(ahb_to_axi4_io_ahb_sig_out_haddr), - .io_ahb_sig_out_hsize(ahb_to_axi4_io_ahb_sig_out_hsize), - .io_ahb_sig_out_htrans(ahb_to_axi4_io_ahb_sig_out_htrans), - .io_ahb_sig_out_hwrite(ahb_to_axi4_io_ahb_sig_out_hwrite), - .io_ahb_sig_out_hwdata(ahb_to_axi4_io_ahb_sig_out_hwdata), - .io_ahb_hsel(ahb_to_axi4_io_ahb_hsel), - .io_ahb_hreadyin(ahb_to_axi4_io_ahb_hreadyin) - ); - assign io_lsu_ahb_out_haddr = axi4_to_ahb_2_io_ahb_out_haddr; // @[quasar.scala 254:28] - assign io_lsu_ahb_out_hsize = axi4_to_ahb_2_io_ahb_out_hsize; // @[quasar.scala 254:28] - assign io_lsu_ahb_out_htrans = axi4_to_ahb_2_io_ahb_out_htrans; // @[quasar.scala 254:28] - assign io_lsu_ahb_out_hwrite = axi4_to_ahb_2_io_ahb_out_hwrite; // @[quasar.scala 254:28] - assign io_lsu_ahb_out_hwdata = axi4_to_ahb_2_io_ahb_out_hwdata; // @[quasar.scala 254:28] - assign io_ifu_ahb_out_haddr = axi4_to_ahb_1_io_ahb_out_haddr; // @[quasar.scala 260:28] - assign io_ifu_ahb_out_hsize = axi4_to_ahb_1_io_ahb_out_hsize; // @[quasar.scala 260:28] - assign io_ifu_ahb_out_htrans = axi4_to_ahb_1_io_ahb_out_htrans; // @[quasar.scala 260:28] - assign io_ifu_ahb_out_hwrite = axi4_to_ahb_1_io_ahb_out_hwrite; // @[quasar.scala 260:28] - assign io_ifu_ahb_out_hwdata = axi4_to_ahb_1_io_ahb_out_hwdata; // @[quasar.scala 260:28] - assign io_sb_ahb_out_haddr = axi4_to_ahb_io_ahb_out_haddr; // @[quasar.scala 267:27] - assign io_sb_ahb_out_hsize = axi4_to_ahb_io_ahb_out_hsize; // @[quasar.scala 267:27] - assign io_sb_ahb_out_htrans = axi4_to_ahb_io_ahb_out_htrans; // @[quasar.scala 267:27] - assign io_sb_ahb_out_hwrite = axi4_to_ahb_io_ahb_out_hwrite; // @[quasar.scala 267:27] - assign io_sb_ahb_out_hwdata = axi4_to_ahb_io_ahb_out_hwdata; // @[quasar.scala 267:27] - assign io_dma_ahb_sig_in_hrdata = ahb_to_axi4_io_ahb_sig_in_hrdata; // @[quasar.scala 273:28] - assign io_dma_ahb_sig_in_hready = ahb_to_axi4_io_ahb_sig_in_hready; // @[quasar.scala 273:28] - assign io_dma_ahb_sig_in_hresp = ahb_to_axi4_io_ahb_sig_in_hresp; // @[quasar.scala 273:28] + assign io_lsu_axi_aw_valid = lsu_io_axi_aw_valid; // @[quasar.scala 285:27] + assign io_lsu_axi_aw_bits_id = lsu_io_axi_aw_bits_id; // @[quasar.scala 285:27] + assign io_lsu_axi_aw_bits_addr = lsu_io_axi_aw_bits_addr; // @[quasar.scala 285:27] + assign io_lsu_axi_aw_bits_region = lsu_io_axi_aw_bits_region; // @[quasar.scala 285:27] + assign io_lsu_axi_aw_bits_size = lsu_io_axi_aw_bits_size; // @[quasar.scala 285:27] + assign io_lsu_axi_aw_bits_cache = lsu_io_axi_aw_bits_cache; // @[quasar.scala 285:27] + assign io_lsu_axi_w_valid = lsu_io_axi_w_valid; // @[quasar.scala 285:27] + assign io_lsu_axi_w_bits_data = lsu_io_axi_w_bits_data; // @[quasar.scala 285:27] + assign io_lsu_axi_w_bits_strb = lsu_io_axi_w_bits_strb; // @[quasar.scala 285:27] + assign io_lsu_axi_ar_valid = lsu_io_axi_ar_valid; // @[quasar.scala 285:27] + assign io_lsu_axi_ar_bits_id = lsu_io_axi_ar_bits_id; // @[quasar.scala 285:27] + assign io_lsu_axi_ar_bits_addr = lsu_io_axi_ar_bits_addr; // @[quasar.scala 285:27] + assign io_lsu_axi_ar_bits_region = lsu_io_axi_ar_bits_region; // @[quasar.scala 285:27] + assign io_lsu_axi_ar_bits_size = lsu_io_axi_ar_bits_size; // @[quasar.scala 285:27] + assign io_lsu_axi_ar_bits_cache = lsu_io_axi_ar_bits_cache; // @[quasar.scala 285:27] + assign io_ifu_axi_ar_valid = ifu_io_ifu_ar_valid; // @[quasar.scala 284:27] + assign io_ifu_axi_ar_bits_id = ifu_io_ifu_ar_bits_id; // @[quasar.scala 284:27] + assign io_ifu_axi_ar_bits_addr = ifu_io_ifu_ar_bits_addr; // @[quasar.scala 284:27] + assign io_ifu_axi_ar_bits_region = ifu_io_ifu_ar_bits_region; // @[quasar.scala 284:27] + assign io_sb_axi_aw_valid = dbg_io_sb_axi_aw_valid; // @[quasar.scala 283:27] + assign io_sb_axi_aw_bits_addr = dbg_io_sb_axi_aw_bits_addr; // @[quasar.scala 283:27] + assign io_sb_axi_aw_bits_region = dbg_io_sb_axi_aw_bits_region; // @[quasar.scala 283:27] + assign io_sb_axi_aw_bits_size = dbg_io_sb_axi_aw_bits_size; // @[quasar.scala 283:27] + assign io_sb_axi_w_valid = dbg_io_sb_axi_w_valid; // @[quasar.scala 283:27] + assign io_sb_axi_w_bits_data = dbg_io_sb_axi_w_bits_data; // @[quasar.scala 283:27] + assign io_sb_axi_w_bits_strb = dbg_io_sb_axi_w_bits_strb; // @[quasar.scala 283:27] + assign io_sb_axi_ar_valid = dbg_io_sb_axi_ar_valid; // @[quasar.scala 283:27] + assign io_sb_axi_ar_bits_addr = dbg_io_sb_axi_ar_bits_addr; // @[quasar.scala 283:27] + assign io_sb_axi_ar_bits_region = dbg_io_sb_axi_ar_bits_region; // @[quasar.scala 283:27] + assign io_sb_axi_ar_bits_size = dbg_io_sb_axi_ar_bits_size; // @[quasar.scala 283:27] + assign io_dma_axi_aw_ready = dma_ctrl_io_dma_axi_aw_ready; // @[quasar.scala 282:27] + assign io_dma_axi_w_ready = dma_ctrl_io_dma_axi_w_ready; // @[quasar.scala 282:27] + assign io_dma_axi_b_valid = dma_ctrl_io_dma_axi_b_valid; // @[quasar.scala 282:27] + assign io_dma_axi_b_bits_resp = dma_ctrl_io_dma_axi_b_bits_resp; // @[quasar.scala 282:27] + assign io_dma_axi_b_bits_id = dma_ctrl_io_dma_axi_b_bits_id; // @[quasar.scala 282:27] + assign io_dma_axi_ar_ready = dma_ctrl_io_dma_axi_ar_ready; // @[quasar.scala 282:27] + assign io_dma_axi_r_valid = dma_ctrl_io_dma_axi_r_valid; // @[quasar.scala 282:27] + assign io_dma_axi_r_bits_id = dma_ctrl_io_dma_axi_r_bits_id; // @[quasar.scala 282:27] + assign io_dma_axi_r_bits_data = dma_ctrl_io_dma_axi_r_bits_data; // @[quasar.scala 282:27] + assign io_dma_axi_r_bits_resp = dma_ctrl_io_dma_axi_r_bits_resp; // @[quasar.scala 282:27] assign io_core_rst_l = reset & _T_2; // @[quasar.scala 82:17] - assign io_rv_trace_pkt_rv_i_valid_ip = dec_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar.scala 222:19] - assign io_rv_trace_pkt_rv_i_insn_ip = dec_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar.scala 222:19] - assign io_rv_trace_pkt_rv_i_address_ip = dec_io_rv_trace_pkt_rv_i_address_ip; // @[quasar.scala 222:19] - assign io_rv_trace_pkt_rv_i_exception_ip = dec_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar.scala 222:19] - assign io_rv_trace_pkt_rv_i_ecause_ip = dec_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar.scala 222:19] - assign io_rv_trace_pkt_rv_i_interrupt_ip = dec_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar.scala 222:19] - assign io_rv_trace_pkt_rv_i_tval_ip = dec_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar.scala 222:19] - assign io_dccm_clk_override = dec_io_dec_tlu_dccm_clk_override; // @[quasar.scala 225:24] - assign io_icm_clk_override = dec_io_dec_tlu_icm_clk_override; // @[quasar.scala 226:23] - assign io_dec_tlu_core_ecc_disable = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 227:31] - assign io_o_cpu_halt_ack = dec_io_o_cpu_halt_ack; // @[quasar.scala 228:21] - assign io_o_cpu_halt_status = dec_io_o_cpu_halt_status; // @[quasar.scala 229:24] - assign io_o_cpu_run_ack = dec_io_o_cpu_run_ack; // @[quasar.scala 230:20] - assign io_o_debug_mode_status = dec_io_o_debug_mode_status; // @[quasar.scala 231:26] - assign io_mpc_debug_halt_ack = dec_io_mpc_debug_halt_ack; // @[quasar.scala 232:25] - assign io_mpc_debug_run_ack = dec_io_mpc_debug_run_ack; // @[quasar.scala 233:24] - assign io_debug_brkpt_status = dec_io_debug_brkpt_status; // @[quasar.scala 234:25] - assign io_dec_tlu_perfcnt0 = dec_io_dec_tlu_perfcnt0; // @[quasar.scala 235:23] - assign io_dec_tlu_perfcnt1 = dec_io_dec_tlu_perfcnt1; // @[quasar.scala 236:23] - assign io_dec_tlu_perfcnt2 = dec_io_dec_tlu_perfcnt2; // @[quasar.scala 237:23] - assign io_dec_tlu_perfcnt3 = dec_io_dec_tlu_perfcnt3; // @[quasar.scala 238:23] - assign io_dccm_wren = lsu_io_dccm_wren; // @[quasar.scala 242:11] - assign io_dccm_rden = lsu_io_dccm_rden; // @[quasar.scala 242:11] - assign io_dccm_wr_addr_lo = lsu_io_dccm_wr_addr_lo; // @[quasar.scala 242:11] - assign io_dccm_wr_addr_hi = lsu_io_dccm_wr_addr_hi; // @[quasar.scala 242:11] - assign io_dccm_rd_addr_lo = lsu_io_dccm_rd_addr_lo; // @[quasar.scala 242:11] - assign io_dccm_rd_addr_hi = lsu_io_dccm_rd_addr_hi; // @[quasar.scala 242:11] - assign io_dccm_wr_data_lo = lsu_io_dccm_wr_data_lo; // @[quasar.scala 242:11] - assign io_dccm_wr_data_hi = lsu_io_dccm_wr_data_hi; // @[quasar.scala 242:11] - assign io_ic_rw_addr = ifu_io_ic_rw_addr; // @[quasar.scala 103:13] - assign io_ic_tag_valid = ifu_io_ic_tag_valid; // @[quasar.scala 103:13] - assign io_ic_wr_en = ifu_io_ic_wr_en; // @[quasar.scala 103:13] - assign io_ic_rd_en = ifu_io_ic_rd_en; // @[quasar.scala 103:13] - assign io_ic_wr_data_0 = ifu_io_ic_wr_data_0; // @[quasar.scala 103:13] - assign io_ic_wr_data_1 = ifu_io_ic_wr_data_1; // @[quasar.scala 103:13] - assign io_ic_debug_wr_data = ifu_io_ic_debug_wr_data; // @[quasar.scala 103:13] - assign io_ic_debug_addr = ifu_io_ic_debug_addr; // @[quasar.scala 103:13] - assign io_ic_debug_rd_en = ifu_io_ic_debug_rd_en; // @[quasar.scala 103:13] - assign io_ic_debug_wr_en = ifu_io_ic_debug_wr_en; // @[quasar.scala 103:13] - assign io_ic_debug_tag_array = ifu_io_ic_debug_tag_array; // @[quasar.scala 103:13] - assign io_ic_debug_way = ifu_io_ic_debug_way; // @[quasar.scala 103:13] - assign io_ic_premux_data = ifu_io_ic_premux_data; // @[quasar.scala 103:13] - assign io_ic_sel_premux_data = ifu_io_ic_sel_premux_data; // @[quasar.scala 103:13] - assign io_iccm_rw_addr = ifu_io_iccm_rw_addr; // @[quasar.scala 104:15] - assign io_iccm_buf_correct_ecc = ifu_io_iccm_buf_correct_ecc; // @[quasar.scala 104:15] - assign io_iccm_correction_state = ifu_io_iccm_correction_state; // @[quasar.scala 104:15] - assign io_iccm_wren = ifu_io_iccm_wren; // @[quasar.scala 104:15] - assign io_iccm_rden = ifu_io_iccm_rden; // @[quasar.scala 104:15] - assign io_iccm_wr_size = ifu_io_iccm_wr_size; // @[quasar.scala 104:15] - assign io_iccm_wr_data = ifu_io_iccm_wr_data; // @[quasar.scala 104:15] - assign io_dmi_reg_rdata = dbg_io_dmi_reg_rdata; // @[quasar.scala 239:20] + assign io_rv_trace_pkt_rv_i_valid_ip = dec_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar.scala 219:19] + assign io_rv_trace_pkt_rv_i_insn_ip = dec_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar.scala 219:19] + assign io_rv_trace_pkt_rv_i_address_ip = dec_io_rv_trace_pkt_rv_i_address_ip; // @[quasar.scala 219:19] + assign io_rv_trace_pkt_rv_i_exception_ip = dec_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar.scala 219:19] + assign io_rv_trace_pkt_rv_i_ecause_ip = dec_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar.scala 219:19] + assign io_rv_trace_pkt_rv_i_interrupt_ip = dec_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar.scala 219:19] + assign io_rv_trace_pkt_rv_i_tval_ip = dec_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar.scala 219:19] + assign io_dccm_clk_override = dec_io_dec_tlu_dccm_clk_override; // @[quasar.scala 222:24] + assign io_icm_clk_override = dec_io_dec_tlu_icm_clk_override; // @[quasar.scala 223:23] + assign io_dec_tlu_core_ecc_disable = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 224:31] + assign io_o_cpu_halt_ack = dec_io_o_cpu_halt_ack; // @[quasar.scala 225:21] + assign io_o_cpu_halt_status = dec_io_o_cpu_halt_status; // @[quasar.scala 226:24] + assign io_o_cpu_run_ack = dec_io_o_cpu_run_ack; // @[quasar.scala 227:20] + assign io_o_debug_mode_status = dec_io_o_debug_mode_status; // @[quasar.scala 228:26] + assign io_mpc_debug_halt_ack = dec_io_mpc_debug_halt_ack; // @[quasar.scala 229:25] + assign io_mpc_debug_run_ack = dec_io_mpc_debug_run_ack; // @[quasar.scala 230:24] + assign io_debug_brkpt_status = dec_io_debug_brkpt_status; // @[quasar.scala 231:25] + assign io_dec_tlu_perfcnt0 = dec_io_dec_tlu_perfcnt0; // @[quasar.scala 232:23] + assign io_dec_tlu_perfcnt1 = dec_io_dec_tlu_perfcnt1; // @[quasar.scala 233:23] + assign io_dec_tlu_perfcnt2 = dec_io_dec_tlu_perfcnt2; // @[quasar.scala 234:23] + assign io_dec_tlu_perfcnt3 = dec_io_dec_tlu_perfcnt3; // @[quasar.scala 235:23] + assign io_dccm_wren = lsu_io_dccm_wren; // @[quasar.scala 239:11] + assign io_dccm_rden = lsu_io_dccm_rden; // @[quasar.scala 239:11] + assign io_dccm_wr_addr_lo = lsu_io_dccm_wr_addr_lo; // @[quasar.scala 239:11] + assign io_dccm_wr_addr_hi = lsu_io_dccm_wr_addr_hi; // @[quasar.scala 239:11] + assign io_dccm_rd_addr_lo = lsu_io_dccm_rd_addr_lo; // @[quasar.scala 239:11] + assign io_dccm_rd_addr_hi = lsu_io_dccm_rd_addr_hi; // @[quasar.scala 239:11] + assign io_dccm_wr_data_lo = lsu_io_dccm_wr_data_lo; // @[quasar.scala 239:11] + assign io_dccm_wr_data_hi = lsu_io_dccm_wr_data_hi; // @[quasar.scala 239:11] + assign io_ic_rw_addr = ifu_io_ic_rw_addr; // @[quasar.scala 100:13] + assign io_ic_tag_valid = ifu_io_ic_tag_valid; // @[quasar.scala 100:13] + assign io_ic_wr_en = ifu_io_ic_wr_en; // @[quasar.scala 100:13] + assign io_ic_rd_en = ifu_io_ic_rd_en; // @[quasar.scala 100:13] + assign io_ic_wr_data_0 = ifu_io_ic_wr_data_0; // @[quasar.scala 100:13] + assign io_ic_wr_data_1 = ifu_io_ic_wr_data_1; // @[quasar.scala 100:13] + assign io_ic_debug_wr_data = ifu_io_ic_debug_wr_data; // @[quasar.scala 100:13] + assign io_ic_debug_addr = ifu_io_ic_debug_addr; // @[quasar.scala 100:13] + assign io_ic_debug_rd_en = ifu_io_ic_debug_rd_en; // @[quasar.scala 100:13] + assign io_ic_debug_wr_en = ifu_io_ic_debug_wr_en; // @[quasar.scala 100:13] + assign io_ic_debug_tag_array = ifu_io_ic_debug_tag_array; // @[quasar.scala 100:13] + assign io_ic_debug_way = ifu_io_ic_debug_way; // @[quasar.scala 100:13] + assign io_ic_premux_data = ifu_io_ic_premux_data; // @[quasar.scala 100:13] + assign io_ic_sel_premux_data = ifu_io_ic_sel_premux_data; // @[quasar.scala 100:13] + assign io_iccm_rw_addr = ifu_io_iccm_rw_addr; // @[quasar.scala 101:15] + assign io_iccm_buf_correct_ecc = ifu_io_iccm_buf_correct_ecc; // @[quasar.scala 101:15] + assign io_iccm_correction_state = ifu_io_iccm_correction_state; // @[quasar.scala 101:15] + assign io_iccm_wren = ifu_io_iccm_wren; // @[quasar.scala 101:15] + assign io_iccm_rden = ifu_io_iccm_rden; // @[quasar.scala 101:15] + assign io_iccm_wr_size = ifu_io_iccm_wr_size; // @[quasar.scala 101:15] + assign io_iccm_wr_data = ifu_io_iccm_wr_data; // @[quasar.scala 101:15] + assign io_dmi_reg_rdata = dbg_io_dmi_reg_rdata; // @[quasar.scala 236:20] assign ifu_clock = clock; - assign ifu_reset = io_core_rst_l; // @[quasar.scala 93:13] - assign ifu_io_exu_flush_final = dec_io_exu_flush_final; // @[quasar.scala 98:26] - assign ifu_io_exu_flush_path_final = exu_io_exu_flush_path_final; // @[quasar.scala 99:31] - assign ifu_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 95:19] - assign ifu_io_active_clk = rvclkhdr_1_io_l1clk; // @[quasar.scala 96:21] - assign ifu_io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d = dec_io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d; // @[quasar.scala 91:18] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[quasar.scala 91:18] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[quasar.scala 91:18] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 91:18] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb; // @[quasar.scala 91:18] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[quasar.scala 91:18 quasar.scala 109:51] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics; // @[quasar.scala 91:18 quasar.scala 109:51] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[quasar.scala 91:18 quasar.scala 109:51] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[quasar.scala 91:18 quasar.scala 109:51] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 91:18] - assign ifu_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb = dec_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb; // @[quasar.scala 91:18] - assign ifu_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff = dec_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 91:18] - assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid; // @[quasar.scala 91:18] - assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist; // @[quasar.scala 91:18] - assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[quasar.scala 91:18] - assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[quasar.scala 91:18] - assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[quasar.scala 91:18] - assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[quasar.scala 91:18] - assign ifu_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb = dec_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb; // @[quasar.scala 91:18] - assign ifu_io_ifu_dec_dec_bp_dec_tlu_bpred_disable = dec_io_ifu_dec_dec_bp_dec_tlu_bpred_disable; // @[quasar.scala 91:18] - assign ifu_io_exu_ifu_exu_bp_exu_i0_br_index_r = exu_io_dec_exu_tlu_exu_exu_i0_br_index_r; // @[quasar.scala 105:25 quasar.scala 107:43] - assign ifu_io_exu_ifu_exu_bp_exu_i0_br_fghr_r = exu_io_exu_bp_exu_i0_br_fghr_r; // @[quasar.scala 105:25 quasar.scala 106:42] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_misp = exu_io_exu_bp_exu_mp_pkt_bits_misp; // @[quasar.scala 105:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_ataken = exu_io_exu_bp_exu_mp_pkt_bits_ataken; // @[quasar.scala 105:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_boffset = exu_io_exu_bp_exu_mp_pkt_bits_boffset; // @[quasar.scala 105:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pc4 = exu_io_exu_bp_exu_mp_pkt_bits_pc4; // @[quasar.scala 105:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_hist = exu_io_exu_bp_exu_mp_pkt_bits_hist; // @[quasar.scala 105:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_toffset = exu_io_exu_bp_exu_mp_pkt_bits_toffset; // @[quasar.scala 105:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pcall = exu_io_exu_bp_exu_mp_pkt_bits_pcall; // @[quasar.scala 105:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pret = exu_io_exu_bp_exu_mp_pkt_bits_pret; // @[quasar.scala 105:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pja = exu_io_exu_bp_exu_mp_pkt_bits_pja; // @[quasar.scala 105:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_way = exu_io_exu_bp_exu_mp_pkt_bits_way; // @[quasar.scala 105:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_eghr = exu_io_exu_bp_exu_mp_eghr; // @[quasar.scala 105:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_fghr = exu_io_exu_bp_exu_mp_fghr; // @[quasar.scala 105:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_index = exu_io_exu_bp_exu_mp_index; // @[quasar.scala 105:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_btag = exu_io_exu_bp_exu_mp_btag; // @[quasar.scala 105:25] - assign ifu_io_iccm_rd_data = io_iccm_rd_data; // @[quasar.scala 104:15] - assign ifu_io_iccm_rd_data_ecc = io_iccm_rd_data_ecc; // @[quasar.scala 104:15] - assign ifu_io_ic_rd_data = io_ic_rd_data; // @[quasar.scala 103:13] - assign ifu_io_ic_debug_rd_data = io_ic_debug_rd_data; // @[quasar.scala 103:13] - assign ifu_io_ic_tag_debug_rd_data = io_ic_tag_debug_rd_data; // @[quasar.scala 103:13] - assign ifu_io_ic_eccerr = io_ic_eccerr; // @[quasar.scala 103:13] - assign ifu_io_ic_rd_hit = io_ic_rd_hit; // @[quasar.scala 103:13] - assign ifu_io_ic_tag_perr = io_ic_tag_perr; // @[quasar.scala 103:13] - assign ifu_io_ifu_ar_ready = axi4_to_ahb_1_io_axi_ar_ready; // @[quasar.scala 259:28] - assign ifu_io_ifu_r_valid = axi4_to_ahb_1_io_axi_r_valid; // @[quasar.scala 259:28] - assign ifu_io_ifu_r_bits_id = axi4_to_ahb_1_io_axi_r_bits_id; // @[quasar.scala 259:28] - assign ifu_io_ifu_r_bits_data = axi4_to_ahb_1_io_axi_r_bits_data; // @[quasar.scala 259:28] - assign ifu_io_ifu_r_bits_resp = axi4_to_ahb_1_io_axi_r_bits_resp; // @[quasar.scala 259:28] - assign ifu_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[quasar.scala 101:25] - assign ifu_io_ifu_dma_dma_ifc_dma_iccm_stall_any = dma_ctrl_io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[quasar.scala 102:18] - assign ifu_io_ifu_dma_dma_mem_ctl_dma_iccm_req = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[quasar.scala 102:18] - assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_addr = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_addr; // @[quasar.scala 102:18] - assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_sz = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_sz; // @[quasar.scala 102:18] - assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_write = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_write; // @[quasar.scala 102:18] - assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_wdata = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_wdata; // @[quasar.scala 102:18] - assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_tag = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_tag; // @[quasar.scala 102:18] - assign ifu_io_dec_tlu_flush_lower_wb = dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 108:33] - assign ifu_io_scan_mode = io_scan_mode; // @[quasar.scala 94:20] + assign ifu_reset = io_core_rst_l; // @[quasar.scala 90:13] + assign ifu_io_exu_flush_final = dec_io_exu_flush_final; // @[quasar.scala 95:26] + assign ifu_io_exu_flush_path_final = exu_io_exu_flush_path_final; // @[quasar.scala 96:31] + assign ifu_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 92:19] + assign ifu_io_active_clk = rvclkhdr_1_io_l1clk; // @[quasar.scala 93:21] + assign ifu_io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d = dec_io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d; // @[quasar.scala 88:18] + assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[quasar.scala 88:18] + assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[quasar.scala 88:18] + assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 88:18] + assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb; // @[quasar.scala 88:18] + assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[quasar.scala 88:18 quasar.scala 106:51] + assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics; // @[quasar.scala 88:18 quasar.scala 106:51] + assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[quasar.scala 88:18 quasar.scala 106:51] + assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[quasar.scala 88:18 quasar.scala 106:51] + assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 88:18] + assign ifu_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb = dec_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb; // @[quasar.scala 88:18] + assign ifu_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff = dec_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 88:18] + assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid; // @[quasar.scala 88:18] + assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist; // @[quasar.scala 88:18] + assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[quasar.scala 88:18] + assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[quasar.scala 88:18] + assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[quasar.scala 88:18] + assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[quasar.scala 88:18] + assign ifu_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb = dec_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb; // @[quasar.scala 88:18] + assign ifu_io_ifu_dec_dec_bp_dec_tlu_bpred_disable = dec_io_ifu_dec_dec_bp_dec_tlu_bpred_disable; // @[quasar.scala 88:18] + assign ifu_io_exu_ifu_exu_bp_exu_i0_br_index_r = exu_io_dec_exu_tlu_exu_exu_i0_br_index_r; // @[quasar.scala 102:25 quasar.scala 104:43] + assign ifu_io_exu_ifu_exu_bp_exu_i0_br_fghr_r = exu_io_exu_bp_exu_i0_br_fghr_r; // @[quasar.scala 102:25 quasar.scala 103:42] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_misp = exu_io_exu_bp_exu_mp_pkt_bits_misp; // @[quasar.scala 102:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_ataken = exu_io_exu_bp_exu_mp_pkt_bits_ataken; // @[quasar.scala 102:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_boffset = exu_io_exu_bp_exu_mp_pkt_bits_boffset; // @[quasar.scala 102:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pc4 = exu_io_exu_bp_exu_mp_pkt_bits_pc4; // @[quasar.scala 102:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_hist = exu_io_exu_bp_exu_mp_pkt_bits_hist; // @[quasar.scala 102:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_toffset = exu_io_exu_bp_exu_mp_pkt_bits_toffset; // @[quasar.scala 102:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pcall = exu_io_exu_bp_exu_mp_pkt_bits_pcall; // @[quasar.scala 102:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pret = exu_io_exu_bp_exu_mp_pkt_bits_pret; // @[quasar.scala 102:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pja = exu_io_exu_bp_exu_mp_pkt_bits_pja; // @[quasar.scala 102:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_way = exu_io_exu_bp_exu_mp_pkt_bits_way; // @[quasar.scala 102:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_eghr = exu_io_exu_bp_exu_mp_eghr; // @[quasar.scala 102:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_fghr = exu_io_exu_bp_exu_mp_fghr; // @[quasar.scala 102:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_index = exu_io_exu_bp_exu_mp_index; // @[quasar.scala 102:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_btag = exu_io_exu_bp_exu_mp_btag; // @[quasar.scala 102:25] + assign ifu_io_iccm_rd_data = io_iccm_rd_data; // @[quasar.scala 101:15] + assign ifu_io_iccm_rd_data_ecc = io_iccm_rd_data_ecc; // @[quasar.scala 101:15] + assign ifu_io_ic_rd_data = io_ic_rd_data; // @[quasar.scala 100:13] + assign ifu_io_ic_debug_rd_data = io_ic_debug_rd_data; // @[quasar.scala 100:13] + assign ifu_io_ic_tag_debug_rd_data = io_ic_tag_debug_rd_data; // @[quasar.scala 100:13] + assign ifu_io_ic_eccerr = io_ic_eccerr; // @[quasar.scala 100:13] + assign ifu_io_ic_rd_hit = io_ic_rd_hit; // @[quasar.scala 100:13] + assign ifu_io_ic_tag_perr = io_ic_tag_perr; // @[quasar.scala 100:13] + assign ifu_io_ifu_ar_ready = io_ifu_axi_ar_ready; // @[quasar.scala 284:27] + assign ifu_io_ifu_r_valid = io_ifu_axi_r_valid; // @[quasar.scala 284:27] + assign ifu_io_ifu_r_bits_id = io_ifu_axi_r_bits_id; // @[quasar.scala 284:27] + assign ifu_io_ifu_r_bits_data = io_ifu_axi_r_bits_data; // @[quasar.scala 284:27] + assign ifu_io_ifu_r_bits_resp = io_ifu_axi_r_bits_resp; // @[quasar.scala 284:27] + assign ifu_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[quasar.scala 98:25] + assign ifu_io_ifu_dma_dma_ifc_dma_iccm_stall_any = dma_ctrl_io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[quasar.scala 99:18] + assign ifu_io_ifu_dma_dma_mem_ctl_dma_iccm_req = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[quasar.scala 99:18] + assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_addr = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_addr; // @[quasar.scala 99:18] + assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_sz = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_sz; // @[quasar.scala 99:18] + assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_write = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_write; // @[quasar.scala 99:18] + assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_wdata = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_wdata; // @[quasar.scala 99:18] + assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_tag = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_tag; // @[quasar.scala 99:18] + assign ifu_io_dec_tlu_flush_lower_wb = dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 105:33] + assign ifu_io_scan_mode = io_scan_mode; // @[quasar.scala 91:20] assign dec_clock = clock; - assign dec_reset = io_core_rst_l; // @[quasar.scala 112:13] - assign dec_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 113:19] - assign dec_io_active_clk = rvclkhdr_1_io_l1clk; // @[quasar.scala 114:21] - assign dec_io_lsu_fastint_stall_any = lsu_io_lsu_fastint_stall_any; // @[quasar.scala 115:32] - assign dec_io_rst_vec = io_rst_vec; // @[quasar.scala 116:18] - assign dec_io_nmi_int = io_nmi_int; // @[quasar.scala 117:18] - assign dec_io_nmi_vec = io_nmi_vec; // @[quasar.scala 118:18] - assign dec_io_i_cpu_halt_req = io_i_cpu_halt_req; // @[quasar.scala 119:25] - assign dec_io_i_cpu_run_req = io_i_cpu_run_req; // @[quasar.scala 120:24] - assign dec_io_core_id = io_core_id; // @[quasar.scala 121:18] - assign dec_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[quasar.scala 122:29] - assign dec_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[quasar.scala 123:28] - assign dec_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[quasar.scala 124:28] - assign dec_io_lsu_pmu_misaligned_m = lsu_io_lsu_pmu_misaligned_m; // @[quasar.scala 127:31] - assign dec_io_lsu_fir_addr = lsu_io_lsu_fir_addr; // @[quasar.scala 130:23] - assign dec_io_lsu_fir_error = lsu_io_lsu_fir_error; // @[quasar.scala 131:24] - assign dec_io_lsu_trigger_match_m = lsu_io_lsu_trigger_match_m; // @[quasar.scala 132:30] - assign dec_io_lsu_idle_any = lsu_io_lsu_idle_any; // @[quasar.scala 134:23] - assign dec_io_lsu_error_pkt_r_valid = lsu_io_lsu_error_pkt_r_valid; // @[quasar.scala 135:26] - assign dec_io_lsu_error_pkt_r_bits_single_ecc_error = lsu_io_lsu_error_pkt_r_bits_single_ecc_error; // @[quasar.scala 135:26] - assign dec_io_lsu_error_pkt_r_bits_inst_type = lsu_io_lsu_error_pkt_r_bits_inst_type; // @[quasar.scala 135:26] - assign dec_io_lsu_error_pkt_r_bits_exc_type = lsu_io_lsu_error_pkt_r_bits_exc_type; // @[quasar.scala 135:26] - assign dec_io_lsu_error_pkt_r_bits_mscause = lsu_io_lsu_error_pkt_r_bits_mscause; // @[quasar.scala 135:26] - assign dec_io_lsu_error_pkt_r_bits_addr = lsu_io_lsu_error_pkt_r_bits_addr; // @[quasar.scala 135:26] - assign dec_io_lsu_single_ecc_error_incr = lsu_io_lsu_single_ecc_error_incr; // @[quasar.scala 136:36] - assign dec_io_exu_div_result = exu_io_exu_div_result; // @[quasar.scala 137:25] - assign dec_io_exu_div_wren = exu_io_exu_div_wren; // @[quasar.scala 138:23] - assign dec_io_lsu_result_m = lsu_io_lsu_result_m; // @[quasar.scala 139:23] - assign dec_io_lsu_result_corr_r = lsu_io_lsu_result_corr_r; // @[quasar.scala 140:28] - assign dec_io_lsu_load_stall_any = lsu_io_lsu_load_stall_any; // @[quasar.scala 141:29] - assign dec_io_lsu_store_stall_any = lsu_io_lsu_store_stall_any; // @[quasar.scala 142:30] - assign dec_io_iccm_dma_sb_error = ifu_io_iccm_dma_sb_error; // @[quasar.scala 143:28] - assign dec_io_exu_flush_final = exu_io_exu_flush_final; // @[quasar.scala 144:26] - assign dec_io_timer_int = io_timer_int; // @[quasar.scala 150:20] - assign dec_io_soft_int = io_soft_int; // @[quasar.scala 146:19] - assign dec_io_dbg_halt_req = dbg_io_dbg_halt_req; // @[quasar.scala 147:23] - assign dec_io_dbg_resume_req = dbg_io_dbg_resume_req; // @[quasar.scala 148:25] - assign dec_io_exu_i0_br_way_r = exu_io_exu_bp_exu_i0_br_way_r; // @[quasar.scala 149:26] - assign dec_io_scan_mode = io_scan_mode; // @[quasar.scala 151:20] - assign dec_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst = ifu_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst; // @[quasar.scala 91:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf; // @[quasar.scala 91:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type; // @[quasar.scala 91:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1 = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1; // @[quasar.scala 91:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc; // @[quasar.scala 91:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index; // @[quasar.scala 91:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[quasar.scala 91:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag; // @[quasar.scala 91:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid; // @[quasar.scala 91:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr; // @[quasar.scala 91:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc; // @[quasar.scala 91:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4 = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4; // @[quasar.scala 91:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid; // @[quasar.scala 91:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset; // @[quasar.scala 91:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist; // @[quasar.scala 91:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error; // @[quasar.scala 91:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[quasar.scala 91:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett; // @[quasar.scala 91:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way; // @[quasar.scala 91:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret; // @[quasar.scala 91:18] - assign dec_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned = ifu_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned; // @[quasar.scala 91:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss; // @[quasar.scala 91:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[quasar.scala 91:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[quasar.scala 91:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[quasar.scala 91:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[quasar.scala 91:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start = ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[quasar.scala 91:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err = ifu_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[quasar.scala 91:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data = ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[quasar.scala 91:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid = ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[quasar.scala 91:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle = ifu_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle; // @[quasar.scala 91:18] - assign dec_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall = ifu_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall; // @[quasar.scala 91:18] - assign dec_io_dec_exu_dec_alu_exu_i0_pc_x = exu_io_dec_exu_dec_alu_exu_i0_pc_x; // @[quasar.scala 154:18] - assign dec_io_dec_exu_decode_exu_exu_i0_result_x = exu_io_dec_exu_decode_exu_exu_i0_result_x; // @[quasar.scala 154:18] - assign dec_io_dec_exu_decode_exu_exu_csr_rs1_x = exu_io_dec_exu_decode_exu_exu_csr_rs1_x; // @[quasar.scala 154:18] - assign dec_io_dec_exu_tlu_exu_exu_i0_br_hist_r = exu_io_dec_exu_tlu_exu_exu_i0_br_hist_r; // @[quasar.scala 154:18] - assign dec_io_dec_exu_tlu_exu_exu_i0_br_error_r = exu_io_dec_exu_tlu_exu_exu_i0_br_error_r; // @[quasar.scala 154:18] - assign dec_io_dec_exu_tlu_exu_exu_i0_br_start_error_r = exu_io_dec_exu_tlu_exu_exu_i0_br_start_error_r; // @[quasar.scala 154:18] - assign dec_io_dec_exu_tlu_exu_exu_i0_br_valid_r = exu_io_dec_exu_tlu_exu_exu_i0_br_valid_r; // @[quasar.scala 154:18] - assign dec_io_dec_exu_tlu_exu_exu_i0_br_mp_r = exu_io_dec_exu_tlu_exu_exu_i0_br_mp_r; // @[quasar.scala 154:18] - assign dec_io_dec_exu_tlu_exu_exu_i0_br_middle_r = exu_io_dec_exu_tlu_exu_exu_i0_br_middle_r; // @[quasar.scala 154:18] - assign dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp = exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp; // @[quasar.scala 154:18] - assign dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken = exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken; // @[quasar.scala 154:18] - assign dec_io_dec_exu_tlu_exu_exu_pmu_i0_pc4 = exu_io_dec_exu_tlu_exu_exu_pmu_i0_pc4; // @[quasar.scala 154:18] - assign dec_io_dec_exu_tlu_exu_exu_npc_r = exu_io_dec_exu_tlu_exu_exu_npc_r; // @[quasar.scala 154:18] - assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[quasar.scala 125:18] - assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[quasar.scala 125:18] - assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 125:18] - assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 125:18] - assign dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any = lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[quasar.scala 125:18] - assign dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any = lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[quasar.scala 125:18] - assign dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any = lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any; // @[quasar.scala 125:18] - assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m; // @[quasar.scala 125:18] - assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m; // @[quasar.scala 125:18] - assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r; // @[quasar.scala 125:18] - assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[quasar.scala 125:18] - assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid; // @[quasar.scala 125:18] - assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error; // @[quasar.scala 125:18] - assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag; // @[quasar.scala 125:18] - assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data; // @[quasar.scala 125:18] - assign dec_io_lsu_tlu_lsu_pmu_load_external_m = lsu_io_lsu_tlu_lsu_pmu_load_external_m; // @[quasar.scala 126:18] - assign dec_io_lsu_tlu_lsu_pmu_store_external_m = lsu_io_lsu_tlu_lsu_pmu_store_external_m; // @[quasar.scala 126:18] - assign dec_io_dec_dbg_dbg_ib_dbg_cmd_valid = dbg_io_dbg_dec_dbg_ib_dbg_cmd_valid; // @[quasar.scala 133:18] - assign dec_io_dec_dbg_dbg_ib_dbg_cmd_write = dbg_io_dbg_dec_dbg_ib_dbg_cmd_write; // @[quasar.scala 133:18] - assign dec_io_dec_dbg_dbg_ib_dbg_cmd_type = dbg_io_dbg_dec_dbg_ib_dbg_cmd_type; // @[quasar.scala 133:18] - assign dec_io_dec_dbg_dbg_ib_dbg_cmd_addr = dbg_io_dbg_dec_dbg_ib_dbg_cmd_addr; // @[quasar.scala 133:18] - assign dec_io_dec_dbg_dbg_dctl_dbg_cmd_wrdata = dbg_io_dbg_dec_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 133:18] - assign dec_io_dec_dma_dctl_dma_dma_dccm_stall_any = dma_ctrl_io_dec_dma_dctl_dma_dma_dccm_stall_any; // @[quasar.scala 128:18] - assign dec_io_dec_dma_tlu_dma_dma_pmu_dccm_read = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_read; // @[quasar.scala 128:18] - assign dec_io_dec_dma_tlu_dma_dma_pmu_dccm_write = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_write; // @[quasar.scala 128:18] - assign dec_io_dec_dma_tlu_dma_dma_pmu_any_read = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_read; // @[quasar.scala 128:18] - assign dec_io_dec_dma_tlu_dma_dma_pmu_any_write = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_write; // @[quasar.scala 128:18] - assign dec_io_dec_dma_tlu_dma_dma_dccm_stall_any = dma_ctrl_io_dec_dma_tlu_dma_dma_dccm_stall_any; // @[quasar.scala 128:18] - assign dec_io_dec_dma_tlu_dma_dma_iccm_stall_any = dma_ctrl_io_dec_dma_tlu_dma_dma_iccm_stall_any; // @[quasar.scala 128:18] - assign dec_io_dec_pic_pic_claimid = pic_ctrl_inst_io_dec_pic_pic_claimid; // @[quasar.scala 220:28] - assign dec_io_dec_pic_pic_pl = pic_ctrl_inst_io_dec_pic_pic_pl; // @[quasar.scala 220:28] - assign dec_io_dec_pic_mhwakeup = pic_ctrl_inst_io_dec_pic_mhwakeup; // @[quasar.scala 220:28] - assign dec_io_dec_pic_mexintpend = pic_ctrl_inst_io_dec_pic_mexintpend; // @[quasar.scala 220:28] + assign dec_reset = io_core_rst_l; // @[quasar.scala 109:13] + assign dec_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 110:19] + assign dec_io_active_clk = rvclkhdr_1_io_l1clk; // @[quasar.scala 111:21] + assign dec_io_lsu_fastint_stall_any = lsu_io_lsu_fastint_stall_any; // @[quasar.scala 112:32] + assign dec_io_rst_vec = io_rst_vec; // @[quasar.scala 113:18] + assign dec_io_nmi_int = io_nmi_int; // @[quasar.scala 114:18] + assign dec_io_nmi_vec = io_nmi_vec; // @[quasar.scala 115:18] + assign dec_io_i_cpu_halt_req = io_i_cpu_halt_req; // @[quasar.scala 116:25] + assign dec_io_i_cpu_run_req = io_i_cpu_run_req; // @[quasar.scala 117:24] + assign dec_io_core_id = io_core_id; // @[quasar.scala 118:18] + assign dec_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[quasar.scala 119:29] + assign dec_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[quasar.scala 120:28] + assign dec_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[quasar.scala 121:28] + assign dec_io_lsu_pmu_misaligned_m = lsu_io_lsu_pmu_misaligned_m; // @[quasar.scala 124:31] + assign dec_io_lsu_fir_addr = lsu_io_lsu_fir_addr; // @[quasar.scala 127:23] + assign dec_io_lsu_fir_error = lsu_io_lsu_fir_error; // @[quasar.scala 128:24] + assign dec_io_lsu_trigger_match_m = lsu_io_lsu_trigger_match_m; // @[quasar.scala 129:30] + assign dec_io_lsu_idle_any = lsu_io_lsu_idle_any; // @[quasar.scala 131:23] + assign dec_io_lsu_error_pkt_r_valid = lsu_io_lsu_error_pkt_r_valid; // @[quasar.scala 132:26] + assign dec_io_lsu_error_pkt_r_bits_single_ecc_error = lsu_io_lsu_error_pkt_r_bits_single_ecc_error; // @[quasar.scala 132:26] + assign dec_io_lsu_error_pkt_r_bits_inst_type = lsu_io_lsu_error_pkt_r_bits_inst_type; // @[quasar.scala 132:26] + assign dec_io_lsu_error_pkt_r_bits_exc_type = lsu_io_lsu_error_pkt_r_bits_exc_type; // @[quasar.scala 132:26] + assign dec_io_lsu_error_pkt_r_bits_mscause = lsu_io_lsu_error_pkt_r_bits_mscause; // @[quasar.scala 132:26] + assign dec_io_lsu_error_pkt_r_bits_addr = lsu_io_lsu_error_pkt_r_bits_addr; // @[quasar.scala 132:26] + assign dec_io_lsu_single_ecc_error_incr = lsu_io_lsu_single_ecc_error_incr; // @[quasar.scala 133:36] + assign dec_io_exu_div_result = exu_io_exu_div_result; // @[quasar.scala 134:25] + assign dec_io_exu_div_wren = exu_io_exu_div_wren; // @[quasar.scala 135:23] + assign dec_io_lsu_result_m = lsu_io_lsu_result_m; // @[quasar.scala 136:23] + assign dec_io_lsu_result_corr_r = lsu_io_lsu_result_corr_r; // @[quasar.scala 137:28] + assign dec_io_lsu_load_stall_any = lsu_io_lsu_load_stall_any; // @[quasar.scala 138:29] + assign dec_io_lsu_store_stall_any = lsu_io_lsu_store_stall_any; // @[quasar.scala 139:30] + assign dec_io_iccm_dma_sb_error = ifu_io_iccm_dma_sb_error; // @[quasar.scala 140:28] + assign dec_io_exu_flush_final = exu_io_exu_flush_final; // @[quasar.scala 141:26] + assign dec_io_timer_int = io_timer_int; // @[quasar.scala 147:20] + assign dec_io_soft_int = io_soft_int; // @[quasar.scala 143:19] + assign dec_io_dbg_halt_req = dbg_io_dbg_halt_req; // @[quasar.scala 144:23] + assign dec_io_dbg_resume_req = dbg_io_dbg_resume_req; // @[quasar.scala 145:25] + assign dec_io_exu_i0_br_way_r = exu_io_exu_bp_exu_i0_br_way_r; // @[quasar.scala 146:26] + assign dec_io_scan_mode = io_scan_mode; // @[quasar.scala 148:20] + assign dec_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst = ifu_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst; // @[quasar.scala 88:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf; // @[quasar.scala 88:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type; // @[quasar.scala 88:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1 = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1; // @[quasar.scala 88:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc; // @[quasar.scala 88:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index; // @[quasar.scala 88:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[quasar.scala 88:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag; // @[quasar.scala 88:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid; // @[quasar.scala 88:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr; // @[quasar.scala 88:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc; // @[quasar.scala 88:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4 = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4; // @[quasar.scala 88:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid; // @[quasar.scala 88:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset; // @[quasar.scala 88:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist; // @[quasar.scala 88:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error; // @[quasar.scala 88:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[quasar.scala 88:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett; // @[quasar.scala 88:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way; // @[quasar.scala 88:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret; // @[quasar.scala 88:18] + assign dec_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned = ifu_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned; // @[quasar.scala 88:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss; // @[quasar.scala 88:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[quasar.scala 88:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[quasar.scala 88:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[quasar.scala 88:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[quasar.scala 88:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start = ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[quasar.scala 88:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err = ifu_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[quasar.scala 88:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data = ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[quasar.scala 88:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid = ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[quasar.scala 88:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle = ifu_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle; // @[quasar.scala 88:18] + assign dec_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall = ifu_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall; // @[quasar.scala 88:18] + assign dec_io_dec_exu_dec_alu_exu_i0_pc_x = exu_io_dec_exu_dec_alu_exu_i0_pc_x; // @[quasar.scala 151:18] + assign dec_io_dec_exu_decode_exu_exu_i0_result_x = exu_io_dec_exu_decode_exu_exu_i0_result_x; // @[quasar.scala 151:18] + assign dec_io_dec_exu_decode_exu_exu_csr_rs1_x = exu_io_dec_exu_decode_exu_exu_csr_rs1_x; // @[quasar.scala 151:18] + assign dec_io_dec_exu_tlu_exu_exu_i0_br_hist_r = exu_io_dec_exu_tlu_exu_exu_i0_br_hist_r; // @[quasar.scala 151:18] + assign dec_io_dec_exu_tlu_exu_exu_i0_br_error_r = exu_io_dec_exu_tlu_exu_exu_i0_br_error_r; // @[quasar.scala 151:18] + assign dec_io_dec_exu_tlu_exu_exu_i0_br_start_error_r = exu_io_dec_exu_tlu_exu_exu_i0_br_start_error_r; // @[quasar.scala 151:18] + assign dec_io_dec_exu_tlu_exu_exu_i0_br_valid_r = exu_io_dec_exu_tlu_exu_exu_i0_br_valid_r; // @[quasar.scala 151:18] + assign dec_io_dec_exu_tlu_exu_exu_i0_br_mp_r = exu_io_dec_exu_tlu_exu_exu_i0_br_mp_r; // @[quasar.scala 151:18] + assign dec_io_dec_exu_tlu_exu_exu_i0_br_middle_r = exu_io_dec_exu_tlu_exu_exu_i0_br_middle_r; // @[quasar.scala 151:18] + assign dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp = exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp; // @[quasar.scala 151:18] + assign dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken = exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken; // @[quasar.scala 151:18] + assign dec_io_dec_exu_tlu_exu_exu_pmu_i0_pc4 = exu_io_dec_exu_tlu_exu_exu_pmu_i0_pc4; // @[quasar.scala 151:18] + assign dec_io_dec_exu_tlu_exu_exu_npc_r = exu_io_dec_exu_tlu_exu_exu_npc_r; // @[quasar.scala 151:18] + assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[quasar.scala 122:18] + assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[quasar.scala 122:18] + assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 122:18] + assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 122:18] + assign dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any = lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[quasar.scala 122:18] + assign dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any = lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[quasar.scala 122:18] + assign dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any = lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any; // @[quasar.scala 122:18] + assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m; // @[quasar.scala 122:18] + assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m; // @[quasar.scala 122:18] + assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r; // @[quasar.scala 122:18] + assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[quasar.scala 122:18] + assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid; // @[quasar.scala 122:18] + assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error; // @[quasar.scala 122:18] + assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag; // @[quasar.scala 122:18] + assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data; // @[quasar.scala 122:18] + assign dec_io_lsu_tlu_lsu_pmu_load_external_m = lsu_io_lsu_tlu_lsu_pmu_load_external_m; // @[quasar.scala 123:18] + assign dec_io_lsu_tlu_lsu_pmu_store_external_m = lsu_io_lsu_tlu_lsu_pmu_store_external_m; // @[quasar.scala 123:18] + assign dec_io_dec_dbg_dbg_ib_dbg_cmd_valid = dbg_io_dbg_dec_dbg_ib_dbg_cmd_valid; // @[quasar.scala 130:18] + assign dec_io_dec_dbg_dbg_ib_dbg_cmd_write = dbg_io_dbg_dec_dbg_ib_dbg_cmd_write; // @[quasar.scala 130:18] + assign dec_io_dec_dbg_dbg_ib_dbg_cmd_type = dbg_io_dbg_dec_dbg_ib_dbg_cmd_type; // @[quasar.scala 130:18] + assign dec_io_dec_dbg_dbg_ib_dbg_cmd_addr = dbg_io_dbg_dec_dbg_ib_dbg_cmd_addr; // @[quasar.scala 130:18] + assign dec_io_dec_dbg_dbg_dctl_dbg_cmd_wrdata = dbg_io_dbg_dec_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 130:18] + assign dec_io_dec_dma_dctl_dma_dma_dccm_stall_any = dma_ctrl_io_dec_dma_dctl_dma_dma_dccm_stall_any; // @[quasar.scala 125:18] + assign dec_io_dec_dma_tlu_dma_dma_pmu_dccm_read = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_read; // @[quasar.scala 125:18] + assign dec_io_dec_dma_tlu_dma_dma_pmu_dccm_write = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_write; // @[quasar.scala 125:18] + assign dec_io_dec_dma_tlu_dma_dma_pmu_any_read = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_read; // @[quasar.scala 125:18] + assign dec_io_dec_dma_tlu_dma_dma_pmu_any_write = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_write; // @[quasar.scala 125:18] + assign dec_io_dec_dma_tlu_dma_dma_dccm_stall_any = dma_ctrl_io_dec_dma_tlu_dma_dma_dccm_stall_any; // @[quasar.scala 125:18] + assign dec_io_dec_dma_tlu_dma_dma_iccm_stall_any = dma_ctrl_io_dec_dma_tlu_dma_dma_iccm_stall_any; // @[quasar.scala 125:18] + assign dec_io_dec_pic_pic_claimid = pic_ctrl_inst_io_dec_pic_pic_claimid; // @[quasar.scala 217:28] + assign dec_io_dec_pic_pic_pl = pic_ctrl_inst_io_dec_pic_pic_pl; // @[quasar.scala 217:28] + assign dec_io_dec_pic_mhwakeup = pic_ctrl_inst_io_dec_pic_mhwakeup; // @[quasar.scala 217:28] + assign dec_io_dec_pic_mexintpend = pic_ctrl_inst_io_dec_pic_mexintpend; // @[quasar.scala 217:28] assign dbg_clock = clock; - assign dbg_reset = io_core_rst_l; // @[quasar.scala 179:13] - assign dbg_io_core_dbg_rddata = dma_ctrl_io_dma_dbg_cmd_done ? dma_ctrl_io_dma_dbg_rddata : dec_io_dec_dbg_rddata; // @[quasar.scala 180:26] - assign dbg_io_core_dbg_cmd_done = dma_ctrl_io_dma_dbg_cmd_done | dec_io_dec_dbg_cmd_done; // @[quasar.scala 181:28] - assign dbg_io_core_dbg_cmd_fail = dma_ctrl_io_dma_dbg_cmd_fail | dec_io_dec_dbg_cmd_fail; // @[quasar.scala 182:28] - assign dbg_io_dec_tlu_debug_mode = dec_io_dec_tlu_debug_mode; // @[quasar.scala 183:29] - assign dbg_io_dec_tlu_dbg_halted = dec_io_dec_tlu_dbg_halted; // @[quasar.scala 184:29] - assign dbg_io_dec_tlu_mpc_halted_only = dec_io_dec_tlu_mpc_halted_only; // @[quasar.scala 185:34] - assign dbg_io_dec_tlu_resume_ack = dec_io_dec_tlu_resume_ack; // @[quasar.scala 186:29] - assign dbg_io_dmi_reg_en = io_dmi_reg_en; // @[quasar.scala 187:21] - assign dbg_io_dmi_reg_addr = io_dmi_reg_addr; // @[quasar.scala 188:23] - assign dbg_io_dmi_reg_wr_en = io_dmi_reg_wr_en; // @[quasar.scala 189:24] - assign dbg_io_dmi_reg_wdata = io_dmi_reg_wdata; // @[quasar.scala 190:24] - assign dbg_io_sb_axi_aw_ready = axi4_to_ahb_io_axi_aw_ready; // @[quasar.scala 266:27] - assign dbg_io_sb_axi_w_ready = axi4_to_ahb_io_axi_w_ready; // @[quasar.scala 266:27] - assign dbg_io_sb_axi_b_valid = axi4_to_ahb_io_axi_b_valid; // @[quasar.scala 266:27] - assign dbg_io_sb_axi_b_bits_resp = axi4_to_ahb_io_axi_b_bits_resp; // @[quasar.scala 266:27] - assign dbg_io_sb_axi_ar_ready = axi4_to_ahb_io_axi_ar_ready; // @[quasar.scala 266:27] - assign dbg_io_sb_axi_r_valid = axi4_to_ahb_io_axi_r_valid; // @[quasar.scala 266:27] - assign dbg_io_sb_axi_r_bits_data = axi4_to_ahb_io_axi_r_bits_data; // @[quasar.scala 266:27] - assign dbg_io_sb_axi_r_bits_resp = axi4_to_ahb_io_axi_r_bits_resp; // @[quasar.scala 266:27] - assign dbg_io_dbg_dma_io_dma_dbg_ready = dma_ctrl_io_dbg_dma_io_dma_dbg_ready; // @[quasar.scala 204:26] - assign dbg_io_dbg_bus_clk_en = io_dbg_bus_clk_en; // @[quasar.scala 191:25] - assign dbg_io_dbg_rst_l = io_dbg_rst_l; // @[quasar.scala 192:20] - assign dbg_io_clk_override = dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 193:23] - assign dbg_io_scan_mode = io_scan_mode; // @[quasar.scala 194:20] + assign dbg_reset = io_core_rst_l; // @[quasar.scala 176:13] + assign dbg_io_core_dbg_rddata = dma_ctrl_io_dma_dbg_cmd_done ? dma_ctrl_io_dma_dbg_rddata : dec_io_dec_dbg_rddata; // @[quasar.scala 177:26] + assign dbg_io_core_dbg_cmd_done = dma_ctrl_io_dma_dbg_cmd_done | dec_io_dec_dbg_cmd_done; // @[quasar.scala 178:28] + assign dbg_io_core_dbg_cmd_fail = dma_ctrl_io_dma_dbg_cmd_fail | dec_io_dec_dbg_cmd_fail; // @[quasar.scala 179:28] + assign dbg_io_dec_tlu_debug_mode = dec_io_dec_tlu_debug_mode; // @[quasar.scala 180:29] + assign dbg_io_dec_tlu_dbg_halted = dec_io_dec_tlu_dbg_halted; // @[quasar.scala 181:29] + assign dbg_io_dec_tlu_mpc_halted_only = dec_io_dec_tlu_mpc_halted_only; // @[quasar.scala 182:34] + assign dbg_io_dec_tlu_resume_ack = dec_io_dec_tlu_resume_ack; // @[quasar.scala 183:29] + assign dbg_io_dmi_reg_en = io_dmi_reg_en; // @[quasar.scala 184:21] + assign dbg_io_dmi_reg_addr = io_dmi_reg_addr; // @[quasar.scala 185:23] + assign dbg_io_dmi_reg_wr_en = io_dmi_reg_wr_en; // @[quasar.scala 186:24] + assign dbg_io_dmi_reg_wdata = io_dmi_reg_wdata; // @[quasar.scala 187:24] + assign dbg_io_sb_axi_aw_ready = io_sb_axi_aw_ready; // @[quasar.scala 283:27] + assign dbg_io_sb_axi_w_ready = io_sb_axi_w_ready; // @[quasar.scala 283:27] + assign dbg_io_sb_axi_b_valid = io_sb_axi_b_valid; // @[quasar.scala 283:27] + assign dbg_io_sb_axi_b_bits_resp = io_sb_axi_b_bits_resp; // @[quasar.scala 283:27] + assign dbg_io_sb_axi_ar_ready = io_sb_axi_ar_ready; // @[quasar.scala 283:27] + assign dbg_io_sb_axi_r_valid = io_sb_axi_r_valid; // @[quasar.scala 283:27] + assign dbg_io_sb_axi_r_bits_data = io_sb_axi_r_bits_data; // @[quasar.scala 283:27] + assign dbg_io_sb_axi_r_bits_resp = io_sb_axi_r_bits_resp; // @[quasar.scala 283:27] + assign dbg_io_dbg_dma_io_dma_dbg_ready = dma_ctrl_io_dbg_dma_io_dma_dbg_ready; // @[quasar.scala 201:26] + assign dbg_io_dbg_bus_clk_en = io_dbg_bus_clk_en; // @[quasar.scala 188:25] + assign dbg_io_dbg_rst_l = io_dbg_rst_l; // @[quasar.scala 189:20] + assign dbg_io_clk_override = dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 190:23] + assign dbg_io_scan_mode = io_scan_mode; // @[quasar.scala 191:20] assign exu_clock = clock; - assign exu_reset = io_core_rst_l; // @[quasar.scala 155:13] - assign exu_io_scan_mode = io_scan_mode; // @[quasar.scala 156:20] - assign exu_io_dec_exu_dec_alu_dec_i0_alu_decode_d = dec_io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[quasar.scala 154:18] - assign exu_io_dec_exu_dec_alu_dec_csr_ren_d = dec_io_dec_exu_dec_alu_dec_csr_ren_d; // @[quasar.scala 154:18] - assign exu_io_dec_exu_dec_alu_dec_i0_br_immed_d = dec_io_dec_exu_dec_alu_dec_i0_br_immed_d; // @[quasar.scala 154:18] - assign exu_io_dec_exu_dec_div_div_p_valid = dec_io_dec_exu_dec_div_div_p_valid; // @[quasar.scala 154:18] - assign exu_io_dec_exu_dec_div_div_p_bits_unsign = dec_io_dec_exu_dec_div_div_p_bits_unsign; // @[quasar.scala 154:18] - assign exu_io_dec_exu_dec_div_div_p_bits_rem = dec_io_dec_exu_dec_div_div_p_bits_rem; // @[quasar.scala 154:18] - assign exu_io_dec_exu_dec_div_dec_div_cancel = dec_io_dec_exu_dec_div_dec_div_cancel; // @[quasar.scala 154:18] - assign exu_io_dec_exu_decode_exu_dec_data_en = dec_io_dec_exu_decode_exu_dec_data_en; // @[quasar.scala 154:18] - assign exu_io_dec_exu_decode_exu_dec_ctl_en = dec_io_dec_exu_decode_exu_dec_ctl_en; // @[quasar.scala 154:18] - assign exu_io_dec_exu_decode_exu_i0_ap_land = dec_io_dec_exu_decode_exu_i0_ap_land; // @[quasar.scala 154:18] - assign exu_io_dec_exu_decode_exu_i0_ap_lor = dec_io_dec_exu_decode_exu_i0_ap_lor; // @[quasar.scala 154:18] - assign exu_io_dec_exu_decode_exu_i0_ap_lxor = dec_io_dec_exu_decode_exu_i0_ap_lxor; // @[quasar.scala 154:18] - assign exu_io_dec_exu_decode_exu_i0_ap_sll = dec_io_dec_exu_decode_exu_i0_ap_sll; // @[quasar.scala 154:18] - assign exu_io_dec_exu_decode_exu_i0_ap_srl = dec_io_dec_exu_decode_exu_i0_ap_srl; // @[quasar.scala 154:18] - assign exu_io_dec_exu_decode_exu_i0_ap_sra = dec_io_dec_exu_decode_exu_i0_ap_sra; // @[quasar.scala 154:18] - assign exu_io_dec_exu_decode_exu_i0_ap_beq = dec_io_dec_exu_decode_exu_i0_ap_beq; // @[quasar.scala 154:18] - assign exu_io_dec_exu_decode_exu_i0_ap_bne = dec_io_dec_exu_decode_exu_i0_ap_bne; // @[quasar.scala 154:18] - assign exu_io_dec_exu_decode_exu_i0_ap_blt = dec_io_dec_exu_decode_exu_i0_ap_blt; // @[quasar.scala 154:18] - assign exu_io_dec_exu_decode_exu_i0_ap_bge = dec_io_dec_exu_decode_exu_i0_ap_bge; // @[quasar.scala 154:18] - assign exu_io_dec_exu_decode_exu_i0_ap_add = dec_io_dec_exu_decode_exu_i0_ap_add; // @[quasar.scala 154:18] - assign exu_io_dec_exu_decode_exu_i0_ap_sub = dec_io_dec_exu_decode_exu_i0_ap_sub; // @[quasar.scala 154:18] - assign exu_io_dec_exu_decode_exu_i0_ap_slt = dec_io_dec_exu_decode_exu_i0_ap_slt; // @[quasar.scala 154:18] - assign exu_io_dec_exu_decode_exu_i0_ap_unsign = dec_io_dec_exu_decode_exu_i0_ap_unsign; // @[quasar.scala 154:18] - assign exu_io_dec_exu_decode_exu_i0_ap_jal = dec_io_dec_exu_decode_exu_i0_ap_jal; // @[quasar.scala 154:18] - assign exu_io_dec_exu_decode_exu_i0_ap_predict_t = dec_io_dec_exu_decode_exu_i0_ap_predict_t; // @[quasar.scala 154:18] - assign exu_io_dec_exu_decode_exu_i0_ap_predict_nt = dec_io_dec_exu_decode_exu_i0_ap_predict_nt; // @[quasar.scala 154:18] - assign exu_io_dec_exu_decode_exu_i0_ap_csr_write = dec_io_dec_exu_decode_exu_i0_ap_csr_write; // @[quasar.scala 154:18] - assign exu_io_dec_exu_decode_exu_i0_ap_csr_imm = dec_io_dec_exu_decode_exu_i0_ap_csr_imm; // @[quasar.scala 154:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid; // @[quasar.scala 154:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4 = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[quasar.scala 154:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist; // @[quasar.scala 154:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[quasar.scala 154:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[quasar.scala 154:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[quasar.scala 154:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett; // @[quasar.scala 154:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[quasar.scala 154:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret; // @[quasar.scala 154:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja; // @[quasar.scala 154:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way; // @[quasar.scala 154:18] - assign exu_io_dec_exu_decode_exu_i0_predict_fghr_d = dec_io_dec_exu_decode_exu_i0_predict_fghr_d; // @[quasar.scala 154:18] - assign exu_io_dec_exu_decode_exu_i0_predict_index_d = dec_io_dec_exu_decode_exu_i0_predict_index_d; // @[quasar.scala 154:18] - assign exu_io_dec_exu_decode_exu_i0_predict_btag_d = dec_io_dec_exu_decode_exu_i0_predict_btag_d; // @[quasar.scala 154:18] - assign exu_io_dec_exu_decode_exu_dec_i0_rs1_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[quasar.scala 154:18] - assign exu_io_dec_exu_decode_exu_dec_i0_rs2_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[quasar.scala 154:18] - assign exu_io_dec_exu_decode_exu_dec_i0_immed_d = dec_io_dec_exu_decode_exu_dec_i0_immed_d; // @[quasar.scala 154:18] - assign exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_data_d = dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_data_d; // @[quasar.scala 154:18] - assign exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_data_d = dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_data_d; // @[quasar.scala 154:18] - assign exu_io_dec_exu_decode_exu_dec_i0_select_pc_d = dec_io_dec_exu_decode_exu_dec_i0_select_pc_d; // @[quasar.scala 154:18] - assign exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d; // @[quasar.scala 154:18] - assign exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d; // @[quasar.scala 154:18] - assign exu_io_dec_exu_decode_exu_mul_p_valid = dec_io_dec_exu_decode_exu_mul_p_valid; // @[quasar.scala 154:18] - assign exu_io_dec_exu_decode_exu_mul_p_bits_rs1_sign = dec_io_dec_exu_decode_exu_mul_p_bits_rs1_sign; // @[quasar.scala 154:18] - assign exu_io_dec_exu_decode_exu_mul_p_bits_rs2_sign = dec_io_dec_exu_decode_exu_mul_p_bits_rs2_sign; // @[quasar.scala 154:18] - assign exu_io_dec_exu_decode_exu_mul_p_bits_low = dec_io_dec_exu_decode_exu_mul_p_bits_low; // @[quasar.scala 154:18] - assign exu_io_dec_exu_decode_exu_pred_correct_npc_x = dec_io_dec_exu_decode_exu_pred_correct_npc_x; // @[quasar.scala 154:18] - assign exu_io_dec_exu_decode_exu_dec_extint_stall = dec_io_dec_exu_decode_exu_dec_extint_stall; // @[quasar.scala 154:18] - assign exu_io_dec_exu_tlu_exu_dec_tlu_meihap = dec_io_dec_exu_tlu_exu_dec_tlu_meihap; // @[quasar.scala 154:18] - assign exu_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r = dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 154:18] - assign exu_io_dec_exu_tlu_exu_dec_tlu_flush_path_r = dec_io_dec_exu_tlu_exu_dec_tlu_flush_path_r; // @[quasar.scala 154:18] - assign exu_io_dec_exu_ib_exu_dec_i0_pc_d = dec_io_dec_exu_ib_exu_dec_i0_pc_d; // @[quasar.scala 154:18] - assign exu_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d = dec_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[quasar.scala 154:18] - assign exu_io_dec_exu_gpr_exu_gpr_i0_rs1_d = dec_io_dec_exu_gpr_exu_gpr_i0_rs1_d; // @[quasar.scala 154:18] - assign exu_io_dec_exu_gpr_exu_gpr_i0_rs2_d = dec_io_dec_exu_gpr_exu_gpr_i0_rs2_d; // @[quasar.scala 154:18] - assign exu_io_dbg_cmd_wrdata = dbg_io_dbg_dec_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 157:25] + assign exu_reset = io_core_rst_l; // @[quasar.scala 152:13] + assign exu_io_scan_mode = io_scan_mode; // @[quasar.scala 153:20] + assign exu_io_dec_exu_dec_alu_dec_i0_alu_decode_d = dec_io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[quasar.scala 151:18] + assign exu_io_dec_exu_dec_alu_dec_csr_ren_d = dec_io_dec_exu_dec_alu_dec_csr_ren_d; // @[quasar.scala 151:18] + assign exu_io_dec_exu_dec_alu_dec_i0_br_immed_d = dec_io_dec_exu_dec_alu_dec_i0_br_immed_d; // @[quasar.scala 151:18] + assign exu_io_dec_exu_dec_div_div_p_valid = dec_io_dec_exu_dec_div_div_p_valid; // @[quasar.scala 151:18] + assign exu_io_dec_exu_dec_div_div_p_bits_unsign = dec_io_dec_exu_dec_div_div_p_bits_unsign; // @[quasar.scala 151:18] + assign exu_io_dec_exu_dec_div_div_p_bits_rem = dec_io_dec_exu_dec_div_div_p_bits_rem; // @[quasar.scala 151:18] + assign exu_io_dec_exu_dec_div_dec_div_cancel = dec_io_dec_exu_dec_div_dec_div_cancel; // @[quasar.scala 151:18] + assign exu_io_dec_exu_decode_exu_dec_data_en = dec_io_dec_exu_decode_exu_dec_data_en; // @[quasar.scala 151:18] + assign exu_io_dec_exu_decode_exu_dec_ctl_en = dec_io_dec_exu_decode_exu_dec_ctl_en; // @[quasar.scala 151:18] + assign exu_io_dec_exu_decode_exu_i0_ap_land = dec_io_dec_exu_decode_exu_i0_ap_land; // @[quasar.scala 151:18] + assign exu_io_dec_exu_decode_exu_i0_ap_lor = dec_io_dec_exu_decode_exu_i0_ap_lor; // @[quasar.scala 151:18] + assign exu_io_dec_exu_decode_exu_i0_ap_lxor = dec_io_dec_exu_decode_exu_i0_ap_lxor; // @[quasar.scala 151:18] + assign exu_io_dec_exu_decode_exu_i0_ap_sll = dec_io_dec_exu_decode_exu_i0_ap_sll; // @[quasar.scala 151:18] + assign exu_io_dec_exu_decode_exu_i0_ap_srl = dec_io_dec_exu_decode_exu_i0_ap_srl; // @[quasar.scala 151:18] + assign exu_io_dec_exu_decode_exu_i0_ap_sra = dec_io_dec_exu_decode_exu_i0_ap_sra; // @[quasar.scala 151:18] + assign exu_io_dec_exu_decode_exu_i0_ap_beq = dec_io_dec_exu_decode_exu_i0_ap_beq; // @[quasar.scala 151:18] + assign exu_io_dec_exu_decode_exu_i0_ap_bne = dec_io_dec_exu_decode_exu_i0_ap_bne; // @[quasar.scala 151:18] + assign exu_io_dec_exu_decode_exu_i0_ap_blt = dec_io_dec_exu_decode_exu_i0_ap_blt; // @[quasar.scala 151:18] + assign exu_io_dec_exu_decode_exu_i0_ap_bge = dec_io_dec_exu_decode_exu_i0_ap_bge; // @[quasar.scala 151:18] + assign exu_io_dec_exu_decode_exu_i0_ap_add = dec_io_dec_exu_decode_exu_i0_ap_add; // @[quasar.scala 151:18] + assign exu_io_dec_exu_decode_exu_i0_ap_sub = dec_io_dec_exu_decode_exu_i0_ap_sub; // @[quasar.scala 151:18] + assign exu_io_dec_exu_decode_exu_i0_ap_slt = dec_io_dec_exu_decode_exu_i0_ap_slt; // @[quasar.scala 151:18] + assign exu_io_dec_exu_decode_exu_i0_ap_unsign = dec_io_dec_exu_decode_exu_i0_ap_unsign; // @[quasar.scala 151:18] + assign exu_io_dec_exu_decode_exu_i0_ap_jal = dec_io_dec_exu_decode_exu_i0_ap_jal; // @[quasar.scala 151:18] + assign exu_io_dec_exu_decode_exu_i0_ap_predict_t = dec_io_dec_exu_decode_exu_i0_ap_predict_t; // @[quasar.scala 151:18] + assign exu_io_dec_exu_decode_exu_i0_ap_predict_nt = dec_io_dec_exu_decode_exu_i0_ap_predict_nt; // @[quasar.scala 151:18] + assign exu_io_dec_exu_decode_exu_i0_ap_csr_write = dec_io_dec_exu_decode_exu_i0_ap_csr_write; // @[quasar.scala 151:18] + assign exu_io_dec_exu_decode_exu_i0_ap_csr_imm = dec_io_dec_exu_decode_exu_i0_ap_csr_imm; // @[quasar.scala 151:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid; // @[quasar.scala 151:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4 = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[quasar.scala 151:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist; // @[quasar.scala 151:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[quasar.scala 151:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[quasar.scala 151:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[quasar.scala 151:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett; // @[quasar.scala 151:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[quasar.scala 151:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret; // @[quasar.scala 151:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja; // @[quasar.scala 151:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way; // @[quasar.scala 151:18] + assign exu_io_dec_exu_decode_exu_i0_predict_fghr_d = dec_io_dec_exu_decode_exu_i0_predict_fghr_d; // @[quasar.scala 151:18] + assign exu_io_dec_exu_decode_exu_i0_predict_index_d = dec_io_dec_exu_decode_exu_i0_predict_index_d; // @[quasar.scala 151:18] + assign exu_io_dec_exu_decode_exu_i0_predict_btag_d = dec_io_dec_exu_decode_exu_i0_predict_btag_d; // @[quasar.scala 151:18] + assign exu_io_dec_exu_decode_exu_dec_i0_rs1_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[quasar.scala 151:18] + assign exu_io_dec_exu_decode_exu_dec_i0_rs2_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[quasar.scala 151:18] + assign exu_io_dec_exu_decode_exu_dec_i0_immed_d = dec_io_dec_exu_decode_exu_dec_i0_immed_d; // @[quasar.scala 151:18] + assign exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_data_d = dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_data_d; // @[quasar.scala 151:18] + assign exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_data_d = dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_data_d; // @[quasar.scala 151:18] + assign exu_io_dec_exu_decode_exu_dec_i0_select_pc_d = dec_io_dec_exu_decode_exu_dec_i0_select_pc_d; // @[quasar.scala 151:18] + assign exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d; // @[quasar.scala 151:18] + assign exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d; // @[quasar.scala 151:18] + assign exu_io_dec_exu_decode_exu_mul_p_valid = dec_io_dec_exu_decode_exu_mul_p_valid; // @[quasar.scala 151:18] + assign exu_io_dec_exu_decode_exu_mul_p_bits_rs1_sign = dec_io_dec_exu_decode_exu_mul_p_bits_rs1_sign; // @[quasar.scala 151:18] + assign exu_io_dec_exu_decode_exu_mul_p_bits_rs2_sign = dec_io_dec_exu_decode_exu_mul_p_bits_rs2_sign; // @[quasar.scala 151:18] + assign exu_io_dec_exu_decode_exu_mul_p_bits_low = dec_io_dec_exu_decode_exu_mul_p_bits_low; // @[quasar.scala 151:18] + assign exu_io_dec_exu_decode_exu_pred_correct_npc_x = dec_io_dec_exu_decode_exu_pred_correct_npc_x; // @[quasar.scala 151:18] + assign exu_io_dec_exu_decode_exu_dec_extint_stall = dec_io_dec_exu_decode_exu_dec_extint_stall; // @[quasar.scala 151:18] + assign exu_io_dec_exu_tlu_exu_dec_tlu_meihap = dec_io_dec_exu_tlu_exu_dec_tlu_meihap; // @[quasar.scala 151:18] + assign exu_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r = dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 151:18] + assign exu_io_dec_exu_tlu_exu_dec_tlu_flush_path_r = dec_io_dec_exu_tlu_exu_dec_tlu_flush_path_r; // @[quasar.scala 151:18] + assign exu_io_dec_exu_ib_exu_dec_i0_pc_d = dec_io_dec_exu_ib_exu_dec_i0_pc_d; // @[quasar.scala 151:18] + assign exu_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d = dec_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[quasar.scala 151:18] + assign exu_io_dec_exu_gpr_exu_gpr_i0_rs1_d = dec_io_dec_exu_gpr_exu_gpr_i0_rs1_d; // @[quasar.scala 151:18] + assign exu_io_dec_exu_gpr_exu_gpr_i0_rs2_d = dec_io_dec_exu_gpr_exu_gpr_i0_rs2_d; // @[quasar.scala 151:18] + assign exu_io_dbg_cmd_wrdata = dbg_io_dbg_dec_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 154:25] assign lsu_clock = clock; - assign lsu_reset = io_core_rst_l; // @[quasar.scala 160:13] - assign lsu_io_clk_override = dec_io_dec_tlu_lsu_clk_override; // @[quasar.scala 161:23] - assign lsu_io_lsu_dma_dma_lsc_ctl_dma_dccm_req = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[quasar.scala 174:18] - assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_addr = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[quasar.scala 174:18] - assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_sz = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[quasar.scala 174:18] - assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_write = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[quasar.scala 174:18] - assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[quasar.scala 174:18] - assign lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_addr = dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_addr; // @[quasar.scala 174:18] - assign lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata = dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata; // @[quasar.scala 174:18] - assign lsu_io_lsu_dma_dma_mem_tag = dma_ctrl_io_lsu_dma_dma_mem_tag; // @[quasar.scala 174:18] - assign lsu_io_lsu_pic_picm_rd_data = pic_ctrl_inst_io_lsu_pic_picm_rd_data; // @[quasar.scala 219:28] - assign lsu_io_lsu_exu_exu_lsu_rs1_d = exu_io_lsu_exu_exu_lsu_rs1_d; // @[quasar.scala 166:18] - assign lsu_io_lsu_exu_exu_lsu_rs2_d = exu_io_lsu_exu_exu_lsu_rs2_d; // @[quasar.scala 166:18] - assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 125:18] - assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 125:18] - assign lsu_io_dccm_rd_data_lo = io_dccm_rd_data_lo; // @[quasar.scala 242:11] - assign lsu_io_dccm_rd_data_hi = io_dccm_rd_data_hi; // @[quasar.scala 242:11] - assign lsu_io_axi_aw_ready = axi4_to_ahb_2_io_axi_aw_ready; // @[quasar.scala 253:28] - assign lsu_io_axi_w_ready = axi4_to_ahb_2_io_axi_w_ready; // @[quasar.scala 253:28] - assign lsu_io_axi_b_valid = axi4_to_ahb_2_io_axi_b_valid; // @[quasar.scala 253:28] - assign lsu_io_axi_b_bits_id = axi4_to_ahb_2_io_axi_b_bits_id; // @[quasar.scala 253:28] - assign lsu_io_axi_ar_ready = axi4_to_ahb_2_io_axi_ar_ready; // @[quasar.scala 253:28] - assign lsu_io_axi_r_valid = axi4_to_ahb_2_io_axi_r_valid; // @[quasar.scala 253:28] - assign lsu_io_axi_r_bits_id = axi4_to_ahb_2_io_axi_r_bits_id; // @[quasar.scala 253:28] - assign lsu_io_axi_r_bits_data = axi4_to_ahb_2_io_axi_r_bits_data; // @[quasar.scala 253:28] - assign lsu_io_axi_r_bits_resp = axi4_to_ahb_2_io_axi_r_bits_resp; // @[quasar.scala 253:28] - assign lsu_io_dec_tlu_flush_lower_r = dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 162:32] - assign lsu_io_dec_tlu_i0_kill_writeb_r = dec_io_dec_tlu_i0_kill_writeb_r; // @[quasar.scala 163:35] - assign lsu_io_dec_tlu_force_halt = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 164:29] - assign lsu_io_dec_tlu_core_ecc_disable = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 165:35] - assign lsu_io_dec_lsu_offset_d = dec_io_dec_lsu_offset_d; // @[quasar.scala 167:27] - assign lsu_io_lsu_p_valid = dec_io_lsu_p_valid; // @[quasar.scala 168:16] - assign lsu_io_lsu_p_bits_fast_int = dec_io_lsu_p_bits_fast_int; // @[quasar.scala 168:16] - assign lsu_io_lsu_p_bits_by = dec_io_lsu_p_bits_by; // @[quasar.scala 168:16] - assign lsu_io_lsu_p_bits_half = dec_io_lsu_p_bits_half; // @[quasar.scala 168:16] - assign lsu_io_lsu_p_bits_word = dec_io_lsu_p_bits_word; // @[quasar.scala 168:16] - assign lsu_io_lsu_p_bits_load = dec_io_lsu_p_bits_load; // @[quasar.scala 168:16] - assign lsu_io_lsu_p_bits_store = dec_io_lsu_p_bits_store; // @[quasar.scala 168:16] - assign lsu_io_lsu_p_bits_unsign = dec_io_lsu_p_bits_unsign; // @[quasar.scala 168:16] - assign lsu_io_lsu_p_bits_store_data_bypass_d = dec_io_lsu_p_bits_store_data_bypass_d; // @[quasar.scala 168:16] - assign lsu_io_lsu_p_bits_load_ldst_bypass_d = dec_io_lsu_p_bits_load_ldst_bypass_d; // @[quasar.scala 168:16] - assign lsu_io_trigger_pkt_any_0_select = dec_io_trigger_pkt_any_0_select; // @[quasar.scala 171:26] - assign lsu_io_trigger_pkt_any_0_match_pkt = dec_io_trigger_pkt_any_0_match_pkt; // @[quasar.scala 171:26] - assign lsu_io_trigger_pkt_any_0_store = dec_io_trigger_pkt_any_0_store; // @[quasar.scala 171:26] - assign lsu_io_trigger_pkt_any_0_load = dec_io_trigger_pkt_any_0_load; // @[quasar.scala 171:26] - assign lsu_io_trigger_pkt_any_0_tdata2 = dec_io_trigger_pkt_any_0_tdata2; // @[quasar.scala 171:26] - assign lsu_io_trigger_pkt_any_1_select = dec_io_trigger_pkt_any_1_select; // @[quasar.scala 171:26] - assign lsu_io_trigger_pkt_any_1_match_pkt = dec_io_trigger_pkt_any_1_match_pkt; // @[quasar.scala 171:26] - assign lsu_io_trigger_pkt_any_1_store = dec_io_trigger_pkt_any_1_store; // @[quasar.scala 171:26] - assign lsu_io_trigger_pkt_any_1_load = dec_io_trigger_pkt_any_1_load; // @[quasar.scala 171:26] - assign lsu_io_trigger_pkt_any_1_tdata2 = dec_io_trigger_pkt_any_1_tdata2; // @[quasar.scala 171:26] - assign lsu_io_trigger_pkt_any_2_select = dec_io_trigger_pkt_any_2_select; // @[quasar.scala 171:26] - assign lsu_io_trigger_pkt_any_2_match_pkt = dec_io_trigger_pkt_any_2_match_pkt; // @[quasar.scala 171:26] - assign lsu_io_trigger_pkt_any_2_store = dec_io_trigger_pkt_any_2_store; // @[quasar.scala 171:26] - assign lsu_io_trigger_pkt_any_2_load = dec_io_trigger_pkt_any_2_load; // @[quasar.scala 171:26] - assign lsu_io_trigger_pkt_any_2_tdata2 = dec_io_trigger_pkt_any_2_tdata2; // @[quasar.scala 171:26] - assign lsu_io_trigger_pkt_any_3_select = dec_io_trigger_pkt_any_3_select; // @[quasar.scala 171:26] - assign lsu_io_trigger_pkt_any_3_match_pkt = dec_io_trigger_pkt_any_3_match_pkt; // @[quasar.scala 171:26] - assign lsu_io_trigger_pkt_any_3_store = dec_io_trigger_pkt_any_3_store; // @[quasar.scala 171:26] - assign lsu_io_trigger_pkt_any_3_load = dec_io_trigger_pkt_any_3_load; // @[quasar.scala 171:26] - assign lsu_io_trigger_pkt_any_3_tdata2 = dec_io_trigger_pkt_any_3_tdata2; // @[quasar.scala 171:26] - assign lsu_io_dec_lsu_valid_raw_d = dec_io_dec_lsu_valid_raw_d; // @[quasar.scala 169:30] - assign lsu_io_dec_tlu_mrac_ff = dec_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 170:26] - assign lsu_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[quasar.scala 173:25] - assign lsu_io_scan_mode = io_scan_mode; // @[quasar.scala 175:20] - assign lsu_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 176:19] + assign lsu_reset = io_core_rst_l; // @[quasar.scala 157:13] + assign lsu_io_clk_override = dec_io_dec_tlu_lsu_clk_override; // @[quasar.scala 158:23] + assign lsu_io_lsu_dma_dma_lsc_ctl_dma_dccm_req = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[quasar.scala 171:18] + assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_addr = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[quasar.scala 171:18] + assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_sz = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[quasar.scala 171:18] + assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_write = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[quasar.scala 171:18] + assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[quasar.scala 171:18] + assign lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_addr = dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_addr; // @[quasar.scala 171:18] + assign lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata = dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata; // @[quasar.scala 171:18] + assign lsu_io_lsu_dma_dma_mem_tag = dma_ctrl_io_lsu_dma_dma_mem_tag; // @[quasar.scala 171:18] + assign lsu_io_lsu_pic_picm_rd_data = pic_ctrl_inst_io_lsu_pic_picm_rd_data; // @[quasar.scala 216:28] + assign lsu_io_lsu_exu_exu_lsu_rs1_d = exu_io_lsu_exu_exu_lsu_rs1_d; // @[quasar.scala 163:18] + assign lsu_io_lsu_exu_exu_lsu_rs2_d = exu_io_lsu_exu_exu_lsu_rs2_d; // @[quasar.scala 163:18] + assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 122:18] + assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[quasar.scala 122:18] + assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 122:18] + assign lsu_io_dccm_rd_data_lo = io_dccm_rd_data_lo; // @[quasar.scala 239:11] + assign lsu_io_dccm_rd_data_hi = io_dccm_rd_data_hi; // @[quasar.scala 239:11] + assign lsu_io_axi_aw_ready = io_lsu_axi_aw_ready; // @[quasar.scala 285:27] + assign lsu_io_axi_w_ready = io_lsu_axi_w_ready; // @[quasar.scala 285:27] + assign lsu_io_axi_b_valid = io_lsu_axi_b_valid; // @[quasar.scala 285:27] + assign lsu_io_axi_b_bits_id = io_lsu_axi_b_bits_id; // @[quasar.scala 285:27] + assign lsu_io_axi_ar_ready = io_lsu_axi_ar_ready; // @[quasar.scala 285:27] + assign lsu_io_axi_r_valid = io_lsu_axi_r_valid; // @[quasar.scala 285:27] + assign lsu_io_axi_r_bits_id = io_lsu_axi_r_bits_id; // @[quasar.scala 285:27] + assign lsu_io_axi_r_bits_data = io_lsu_axi_r_bits_data; // @[quasar.scala 285:27] + assign lsu_io_axi_r_bits_resp = io_lsu_axi_r_bits_resp; // @[quasar.scala 285:27] + assign lsu_io_dec_tlu_flush_lower_r = dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 159:32] + assign lsu_io_dec_tlu_i0_kill_writeb_r = dec_io_dec_tlu_i0_kill_writeb_r; // @[quasar.scala 160:35] + assign lsu_io_dec_tlu_force_halt = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 161:29] + assign lsu_io_dec_tlu_core_ecc_disable = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 162:35] + assign lsu_io_dec_lsu_offset_d = dec_io_dec_lsu_offset_d; // @[quasar.scala 164:27] + assign lsu_io_lsu_p_valid = dec_io_lsu_p_valid; // @[quasar.scala 165:16] + assign lsu_io_lsu_p_bits_fast_int = dec_io_lsu_p_bits_fast_int; // @[quasar.scala 165:16] + assign lsu_io_lsu_p_bits_by = dec_io_lsu_p_bits_by; // @[quasar.scala 165:16] + assign lsu_io_lsu_p_bits_half = dec_io_lsu_p_bits_half; // @[quasar.scala 165:16] + assign lsu_io_lsu_p_bits_word = dec_io_lsu_p_bits_word; // @[quasar.scala 165:16] + assign lsu_io_lsu_p_bits_load = dec_io_lsu_p_bits_load; // @[quasar.scala 165:16] + assign lsu_io_lsu_p_bits_store = dec_io_lsu_p_bits_store; // @[quasar.scala 165:16] + assign lsu_io_lsu_p_bits_unsign = dec_io_lsu_p_bits_unsign; // @[quasar.scala 165:16] + assign lsu_io_lsu_p_bits_store_data_bypass_d = dec_io_lsu_p_bits_store_data_bypass_d; // @[quasar.scala 165:16] + assign lsu_io_lsu_p_bits_load_ldst_bypass_d = dec_io_lsu_p_bits_load_ldst_bypass_d; // @[quasar.scala 165:16] + assign lsu_io_trigger_pkt_any_0_select = dec_io_trigger_pkt_any_0_select; // @[quasar.scala 168:26] + assign lsu_io_trigger_pkt_any_0_match_pkt = dec_io_trigger_pkt_any_0_match_pkt; // @[quasar.scala 168:26] + assign lsu_io_trigger_pkt_any_0_store = dec_io_trigger_pkt_any_0_store; // @[quasar.scala 168:26] + assign lsu_io_trigger_pkt_any_0_load = dec_io_trigger_pkt_any_0_load; // @[quasar.scala 168:26] + assign lsu_io_trigger_pkt_any_0_tdata2 = dec_io_trigger_pkt_any_0_tdata2; // @[quasar.scala 168:26] + assign lsu_io_trigger_pkt_any_1_select = dec_io_trigger_pkt_any_1_select; // @[quasar.scala 168:26] + assign lsu_io_trigger_pkt_any_1_match_pkt = dec_io_trigger_pkt_any_1_match_pkt; // @[quasar.scala 168:26] + assign lsu_io_trigger_pkt_any_1_store = dec_io_trigger_pkt_any_1_store; // @[quasar.scala 168:26] + assign lsu_io_trigger_pkt_any_1_load = dec_io_trigger_pkt_any_1_load; // @[quasar.scala 168:26] + assign lsu_io_trigger_pkt_any_1_tdata2 = dec_io_trigger_pkt_any_1_tdata2; // @[quasar.scala 168:26] + assign lsu_io_trigger_pkt_any_2_select = dec_io_trigger_pkt_any_2_select; // @[quasar.scala 168:26] + assign lsu_io_trigger_pkt_any_2_match_pkt = dec_io_trigger_pkt_any_2_match_pkt; // @[quasar.scala 168:26] + assign lsu_io_trigger_pkt_any_2_store = dec_io_trigger_pkt_any_2_store; // @[quasar.scala 168:26] + assign lsu_io_trigger_pkt_any_2_load = dec_io_trigger_pkt_any_2_load; // @[quasar.scala 168:26] + assign lsu_io_trigger_pkt_any_2_tdata2 = dec_io_trigger_pkt_any_2_tdata2; // @[quasar.scala 168:26] + assign lsu_io_trigger_pkt_any_3_select = dec_io_trigger_pkt_any_3_select; // @[quasar.scala 168:26] + assign lsu_io_trigger_pkt_any_3_match_pkt = dec_io_trigger_pkt_any_3_match_pkt; // @[quasar.scala 168:26] + assign lsu_io_trigger_pkt_any_3_store = dec_io_trigger_pkt_any_3_store; // @[quasar.scala 168:26] + assign lsu_io_trigger_pkt_any_3_load = dec_io_trigger_pkt_any_3_load; // @[quasar.scala 168:26] + assign lsu_io_trigger_pkt_any_3_tdata2 = dec_io_trigger_pkt_any_3_tdata2; // @[quasar.scala 168:26] + assign lsu_io_dec_lsu_valid_raw_d = dec_io_dec_lsu_valid_raw_d; // @[quasar.scala 166:30] + assign lsu_io_dec_tlu_mrac_ff = dec_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 167:26] + assign lsu_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[quasar.scala 170:25] + assign lsu_io_scan_mode = io_scan_mode; // @[quasar.scala 172:20] + assign lsu_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 173:19] assign pic_ctrl_inst_clock = clock; - assign pic_ctrl_inst_reset = io_core_rst_l; // @[quasar.scala 214:23] - assign pic_ctrl_inst_io_scan_mode = io_scan_mode; // @[quasar.scala 213:30] - assign pic_ctrl_inst_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 215:29] - assign pic_ctrl_inst_io_active_clk = rvclkhdr_1_io_l1clk; // @[quasar.scala 216:31] - assign pic_ctrl_inst_io_clk_override = dec_io_dec_tlu_pic_clk_override; // @[quasar.scala 217:33] - assign pic_ctrl_inst_io_extintsrc_req = {{1'd0}, io_extintsrc_req}; // @[quasar.scala 218:34] - assign pic_ctrl_inst_io_lsu_pic_picm_wren = lsu_io_lsu_pic_picm_wren; // @[quasar.scala 219:28] - assign pic_ctrl_inst_io_lsu_pic_picm_rden = lsu_io_lsu_pic_picm_rden; // @[quasar.scala 219:28] - assign pic_ctrl_inst_io_lsu_pic_picm_mken = lsu_io_lsu_pic_picm_mken; // @[quasar.scala 219:28] - assign pic_ctrl_inst_io_lsu_pic_picm_rdaddr = lsu_io_lsu_pic_picm_rdaddr; // @[quasar.scala 219:28] - assign pic_ctrl_inst_io_lsu_pic_picm_wraddr = lsu_io_lsu_pic_picm_wraddr; // @[quasar.scala 219:28] - assign pic_ctrl_inst_io_lsu_pic_picm_wr_data = lsu_io_lsu_pic_picm_wr_data; // @[quasar.scala 219:28] - assign pic_ctrl_inst_io_dec_pic_dec_tlu_meicurpl = dec_io_dec_pic_dec_tlu_meicurpl; // @[quasar.scala 220:28] - assign pic_ctrl_inst_io_dec_pic_dec_tlu_meipt = dec_io_dec_pic_dec_tlu_meipt; // @[quasar.scala 220:28] + assign pic_ctrl_inst_reset = io_core_rst_l; // @[quasar.scala 211:23] + assign pic_ctrl_inst_io_scan_mode = io_scan_mode; // @[quasar.scala 210:30] + assign pic_ctrl_inst_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 212:29] + assign pic_ctrl_inst_io_active_clk = rvclkhdr_1_io_l1clk; // @[quasar.scala 213:31] + assign pic_ctrl_inst_io_clk_override = dec_io_dec_tlu_pic_clk_override; // @[quasar.scala 214:33] + assign pic_ctrl_inst_io_extintsrc_req = {{1'd0}, io_extintsrc_req}; // @[quasar.scala 215:34] + assign pic_ctrl_inst_io_lsu_pic_picm_wren = lsu_io_lsu_pic_picm_wren; // @[quasar.scala 216:28] + assign pic_ctrl_inst_io_lsu_pic_picm_rden = lsu_io_lsu_pic_picm_rden; // @[quasar.scala 216:28] + assign pic_ctrl_inst_io_lsu_pic_picm_mken = lsu_io_lsu_pic_picm_mken; // @[quasar.scala 216:28] + assign pic_ctrl_inst_io_lsu_pic_picm_rdaddr = lsu_io_lsu_pic_picm_rdaddr; // @[quasar.scala 216:28] + assign pic_ctrl_inst_io_lsu_pic_picm_wraddr = lsu_io_lsu_pic_picm_wraddr; // @[quasar.scala 216:28] + assign pic_ctrl_inst_io_lsu_pic_picm_wr_data = lsu_io_lsu_pic_picm_wr_data; // @[quasar.scala 216:28] + assign pic_ctrl_inst_io_dec_pic_dec_tlu_meicurpl = dec_io_dec_pic_dec_tlu_meicurpl; // @[quasar.scala 217:28] + assign pic_ctrl_inst_io_dec_pic_dec_tlu_meipt = dec_io_dec_pic_dec_tlu_meipt; // @[quasar.scala 217:28] assign dma_ctrl_clock = clock; - assign dma_ctrl_reset = io_core_rst_l; // @[quasar.scala 198:18] - assign dma_ctrl_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 199:24] - assign dma_ctrl_io_dma_bus_clk_en = io_dma_bus_clk_en; // @[quasar.scala 200:30] - assign dma_ctrl_io_clk_override = dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 201:28] - assign dma_ctrl_io_scan_mode = io_scan_mode; // @[quasar.scala 202:25] - assign dma_ctrl_io_dbg_cmd_size = dbg_io_dbg_cmd_size; // @[quasar.scala 205:28] - assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_valid = dbg_io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[quasar.scala 203:23] - assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_write = dbg_io_dbg_dma_dbg_ib_dbg_cmd_write; // @[quasar.scala 203:23] - assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_type = dbg_io_dbg_dma_dbg_ib_dbg_cmd_type; // @[quasar.scala 203:23] - assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_addr = dbg_io_dbg_dma_dbg_ib_dbg_cmd_addr; // @[quasar.scala 203:23] - assign dma_ctrl_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata = dbg_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 203:23] - assign dma_ctrl_io_dbg_dma_io_dbg_dma_bubble = dbg_io_dbg_dma_io_dbg_dma_bubble; // @[quasar.scala 204:26] - assign dma_ctrl_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty = dec_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty; // @[quasar.scala 128:18] - assign dma_ctrl_io_iccm_dma_rvalid = ifu_io_iccm_dma_rvalid; // @[quasar.scala 206:31] - assign dma_ctrl_io_iccm_dma_ecc_error = ifu_io_iccm_dma_ecc_error; // @[quasar.scala 210:34] - assign dma_ctrl_io_iccm_dma_rtag = ifu_io_iccm_dma_rtag; // @[quasar.scala 207:29] - assign dma_ctrl_io_iccm_dma_rdata = ifu_io_iccm_dma_rdata; // @[quasar.scala 208:30] - assign dma_ctrl_io_iccm_ready = ifu_io_iccm_ready; // @[quasar.scala 209:26] - assign dma_ctrl_io_dma_axi_aw_valid = ahb_to_axi4_io_axi_aw_valid; // @[quasar.scala 272:28] - assign dma_ctrl_io_dma_axi_aw_bits_addr = ahb_to_axi4_io_axi_aw_bits_addr; // @[quasar.scala 272:28] - assign dma_ctrl_io_dma_axi_aw_bits_size = ahb_to_axi4_io_axi_aw_bits_size; // @[quasar.scala 272:28] - assign dma_ctrl_io_dma_axi_w_valid = ahb_to_axi4_io_axi_w_valid; // @[quasar.scala 272:28] - assign dma_ctrl_io_dma_axi_w_bits_data = ahb_to_axi4_io_axi_w_bits_data; // @[quasar.scala 272:28] - assign dma_ctrl_io_dma_axi_w_bits_strb = ahb_to_axi4_io_axi_w_bits_strb; // @[quasar.scala 272:28] - assign dma_ctrl_io_dma_axi_ar_valid = ahb_to_axi4_io_axi_ar_valid; // @[quasar.scala 272:28] - assign dma_ctrl_io_dma_axi_ar_bits_addr = ahb_to_axi4_io_axi_ar_bits_addr; // @[quasar.scala 272:28] - assign dma_ctrl_io_dma_axi_ar_bits_size = ahb_to_axi4_io_axi_ar_bits_size; // @[quasar.scala 272:28] - assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid; // @[quasar.scala 174:18] - assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[quasar.scala 174:18] - assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[quasar.scala 174:18] - assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata; // @[quasar.scala 174:18] - assign dma_ctrl_io_lsu_dma_dccm_ready = lsu_io_lsu_dma_dccm_ready; // @[quasar.scala 174:18] + assign dma_ctrl_reset = io_core_rst_l; // @[quasar.scala 195:18] + assign dma_ctrl_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 196:24] + assign dma_ctrl_io_dma_bus_clk_en = io_dma_bus_clk_en; // @[quasar.scala 197:30] + assign dma_ctrl_io_clk_override = dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 198:28] + assign dma_ctrl_io_scan_mode = io_scan_mode; // @[quasar.scala 199:25] + assign dma_ctrl_io_dbg_cmd_size = dbg_io_dbg_cmd_size; // @[quasar.scala 202:28] + assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_valid = dbg_io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[quasar.scala 200:23] + assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_write = dbg_io_dbg_dma_dbg_ib_dbg_cmd_write; // @[quasar.scala 200:23] + assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_type = dbg_io_dbg_dma_dbg_ib_dbg_cmd_type; // @[quasar.scala 200:23] + assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_addr = dbg_io_dbg_dma_dbg_ib_dbg_cmd_addr; // @[quasar.scala 200:23] + assign dma_ctrl_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata = dbg_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 200:23] + assign dma_ctrl_io_dbg_dma_io_dbg_dma_bubble = dbg_io_dbg_dma_io_dbg_dma_bubble; // @[quasar.scala 201:26] + assign dma_ctrl_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty = dec_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty; // @[quasar.scala 125:18] + assign dma_ctrl_io_iccm_dma_rvalid = ifu_io_iccm_dma_rvalid; // @[quasar.scala 203:31] + assign dma_ctrl_io_iccm_dma_ecc_error = ifu_io_iccm_dma_ecc_error; // @[quasar.scala 207:34] + assign dma_ctrl_io_iccm_dma_rtag = ifu_io_iccm_dma_rtag; // @[quasar.scala 204:29] + assign dma_ctrl_io_iccm_dma_rdata = ifu_io_iccm_dma_rdata; // @[quasar.scala 205:30] + assign dma_ctrl_io_iccm_ready = ifu_io_iccm_ready; // @[quasar.scala 206:26] + assign dma_ctrl_io_dma_axi_aw_valid = io_dma_axi_aw_valid; // @[quasar.scala 282:27] + assign dma_ctrl_io_dma_axi_aw_bits_id = io_dma_axi_aw_bits_id; // @[quasar.scala 282:27] + assign dma_ctrl_io_dma_axi_aw_bits_addr = io_dma_axi_aw_bits_addr; // @[quasar.scala 282:27] + assign dma_ctrl_io_dma_axi_aw_bits_size = io_dma_axi_aw_bits_size; // @[quasar.scala 282:27] + assign dma_ctrl_io_dma_axi_w_valid = io_dma_axi_w_valid; // @[quasar.scala 282:27] + assign dma_ctrl_io_dma_axi_w_bits_data = io_dma_axi_w_bits_data; // @[quasar.scala 282:27] + assign dma_ctrl_io_dma_axi_w_bits_strb = io_dma_axi_w_bits_strb; // @[quasar.scala 282:27] + assign dma_ctrl_io_dma_axi_b_ready = io_dma_axi_b_ready; // @[quasar.scala 282:27] + assign dma_ctrl_io_dma_axi_ar_valid = io_dma_axi_ar_valid; // @[quasar.scala 282:27] + assign dma_ctrl_io_dma_axi_ar_bits_id = io_dma_axi_ar_bits_id; // @[quasar.scala 282:27] + assign dma_ctrl_io_dma_axi_ar_bits_addr = io_dma_axi_ar_bits_addr; // @[quasar.scala 282:27] + assign dma_ctrl_io_dma_axi_ar_bits_size = io_dma_axi_ar_bits_size; // @[quasar.scala 282:27] + assign dma_ctrl_io_dma_axi_r_ready = io_dma_axi_r_ready; // @[quasar.scala 282:27] + assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid; // @[quasar.scala 171:18] + assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[quasar.scala 171:18] + assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[quasar.scala 171:18] + assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata; // @[quasar.scala 171:18] + assign dma_ctrl_io_lsu_dma_dccm_ready = lsu_io_lsu_dma_dccm_ready; // @[quasar.scala 171:18] assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17] assign rvclkhdr_io_en = 1'h1; // @[lib.scala 345:16] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] assign rvclkhdr_1_io_clk = clock; // @[lib.scala 344:17] assign rvclkhdr_1_io_en = _T_6 | dec_io_dec_tlu_misc_clk_override; // @[lib.scala 345:16] assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign axi4_to_ahb_clock = clock; - assign axi4_to_ahb_reset = reset; - assign axi4_to_ahb_io_scan_mode = io_scan_mode; // @[quasar.scala 263:33] - assign axi4_to_ahb_io_bus_clk_en = io_dbg_bus_clk_en; // @[quasar.scala 264:34] - assign axi4_to_ahb_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 265:36] - assign axi4_to_ahb_io_axi_aw_valid = dbg_io_sb_axi_aw_valid; // @[quasar.scala 266:27] - assign axi4_to_ahb_io_axi_aw_bits_addr = dbg_io_sb_axi_aw_bits_addr; // @[quasar.scala 266:27] - assign axi4_to_ahb_io_axi_aw_bits_size = dbg_io_sb_axi_aw_bits_size; // @[quasar.scala 266:27] - assign axi4_to_ahb_io_axi_w_valid = dbg_io_sb_axi_w_valid; // @[quasar.scala 266:27] - assign axi4_to_ahb_io_axi_w_bits_data = dbg_io_sb_axi_w_bits_data; // @[quasar.scala 266:27] - assign axi4_to_ahb_io_axi_w_bits_strb = dbg_io_sb_axi_w_bits_strb; // @[quasar.scala 266:27] - assign axi4_to_ahb_io_axi_ar_valid = dbg_io_sb_axi_ar_valid; // @[quasar.scala 266:27] - assign axi4_to_ahb_io_axi_ar_bits_addr = dbg_io_sb_axi_ar_bits_addr; // @[quasar.scala 266:27] - assign axi4_to_ahb_io_axi_ar_bits_size = dbg_io_sb_axi_ar_bits_size; // @[quasar.scala 266:27] - assign axi4_to_ahb_io_ahb_in_hrdata = io_sb_ahb_in_hrdata; // @[quasar.scala 267:27] - assign axi4_to_ahb_io_ahb_in_hready = io_sb_ahb_in_hready; // @[quasar.scala 267:27] - assign axi4_to_ahb_io_ahb_in_hresp = io_sb_ahb_in_hresp; // @[quasar.scala 267:27] - assign axi4_to_ahb_1_clock = clock; - assign axi4_to_ahb_1_reset = reset; - assign axi4_to_ahb_1_io_scan_mode = io_scan_mode; // @[quasar.scala 256:34] - assign axi4_to_ahb_1_io_bus_clk_en = io_ifu_bus_clk_en; // @[quasar.scala 257:35] - assign axi4_to_ahb_1_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 258:37] - assign axi4_to_ahb_1_io_axi_aw_valid = 1'h0; // @[quasar.scala 259:28] - assign axi4_to_ahb_1_io_axi_aw_bits_id = 3'h0; // @[quasar.scala 259:28] - assign axi4_to_ahb_1_io_axi_aw_bits_addr = 32'h0; // @[quasar.scala 259:28] - assign axi4_to_ahb_1_io_axi_aw_bits_size = 3'h0; // @[quasar.scala 259:28] - assign axi4_to_ahb_1_io_axi_w_valid = 1'h0; // @[quasar.scala 259:28] - assign axi4_to_ahb_1_io_axi_w_bits_data = 64'h0; // @[quasar.scala 259:28] - assign axi4_to_ahb_1_io_axi_w_bits_strb = 8'h0; // @[quasar.scala 259:28] - assign axi4_to_ahb_1_io_axi_ar_valid = ifu_io_ifu_ar_valid; // @[quasar.scala 259:28] - assign axi4_to_ahb_1_io_axi_ar_bits_id = ifu_io_ifu_ar_bits_id; // @[quasar.scala 259:28] - assign axi4_to_ahb_1_io_axi_ar_bits_addr = ifu_io_ifu_ar_bits_addr; // @[quasar.scala 259:28] - assign axi4_to_ahb_1_io_axi_ar_bits_size = 3'h3; // @[quasar.scala 259:28] - assign axi4_to_ahb_1_io_ahb_in_hrdata = io_ifu_ahb_in_hrdata; // @[quasar.scala 260:28] - assign axi4_to_ahb_1_io_ahb_in_hready = io_ifu_ahb_in_hready; // @[quasar.scala 260:28] - assign axi4_to_ahb_1_io_ahb_in_hresp = io_ifu_ahb_in_hresp; // @[quasar.scala 260:28] - assign axi4_to_ahb_2_clock = clock; - assign axi4_to_ahb_2_reset = reset; - assign axi4_to_ahb_2_io_scan_mode = io_scan_mode; // @[quasar.scala 250:34] - assign axi4_to_ahb_2_io_bus_clk_en = io_lsu_bus_clk_en; // @[quasar.scala 251:35] - assign axi4_to_ahb_2_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 252:37] - assign axi4_to_ahb_2_io_axi_aw_valid = lsu_io_axi_aw_valid; // @[quasar.scala 253:28] - assign axi4_to_ahb_2_io_axi_aw_bits_id = lsu_io_axi_aw_bits_id; // @[quasar.scala 253:28] - assign axi4_to_ahb_2_io_axi_aw_bits_addr = lsu_io_axi_aw_bits_addr; // @[quasar.scala 253:28] - assign axi4_to_ahb_2_io_axi_aw_bits_size = lsu_io_axi_aw_bits_size; // @[quasar.scala 253:28] - assign axi4_to_ahb_2_io_axi_w_valid = lsu_io_axi_w_valid; // @[quasar.scala 253:28] - assign axi4_to_ahb_2_io_axi_w_bits_data = lsu_io_axi_w_bits_data; // @[quasar.scala 253:28] - assign axi4_to_ahb_2_io_axi_w_bits_strb = lsu_io_axi_w_bits_strb; // @[quasar.scala 253:28] - assign axi4_to_ahb_2_io_axi_ar_valid = lsu_io_axi_ar_valid; // @[quasar.scala 253:28] - assign axi4_to_ahb_2_io_axi_ar_bits_id = lsu_io_axi_ar_bits_id; // @[quasar.scala 253:28] - assign axi4_to_ahb_2_io_axi_ar_bits_addr = lsu_io_axi_ar_bits_addr; // @[quasar.scala 253:28] - assign axi4_to_ahb_2_io_axi_ar_bits_size = lsu_io_axi_ar_bits_size; // @[quasar.scala 253:28] - assign axi4_to_ahb_2_io_ahb_in_hrdata = io_lsu_ahb_in_hrdata; // @[quasar.scala 254:28] - assign axi4_to_ahb_2_io_ahb_in_hready = io_lsu_ahb_in_hready; // @[quasar.scala 254:28] - assign axi4_to_ahb_2_io_ahb_in_hresp = io_lsu_ahb_in_hresp; // @[quasar.scala 254:28] - assign ahb_to_axi4_clock = clock; - assign ahb_to_axi4_reset = reset; - assign ahb_to_axi4_io_scan_mode = io_scan_mode; // @[quasar.scala 269:34] - assign ahb_to_axi4_io_bus_clk_en = io_dma_bus_clk_en; // @[quasar.scala 270:35] - assign ahb_to_axi4_io_axi_aw_ready = dma_ctrl_io_dma_axi_aw_ready; // @[quasar.scala 272:28] - assign ahb_to_axi4_io_axi_ar_ready = dma_ctrl_io_dma_axi_ar_ready; // @[quasar.scala 272:28] - assign ahb_to_axi4_io_axi_r_valid = dma_ctrl_io_dma_axi_r_valid; // @[quasar.scala 272:28] - assign ahb_to_axi4_io_axi_r_bits_data = dma_ctrl_io_dma_axi_r_bits_data; // @[quasar.scala 272:28] - assign ahb_to_axi4_io_axi_r_bits_resp = dma_ctrl_io_dma_axi_r_bits_resp; // @[quasar.scala 272:28] - assign ahb_to_axi4_io_ahb_sig_out_haddr = io_dma_ahb_sig_out_haddr; // @[quasar.scala 273:28] - assign ahb_to_axi4_io_ahb_sig_out_hsize = io_dma_ahb_sig_out_hsize; // @[quasar.scala 273:28] - assign ahb_to_axi4_io_ahb_sig_out_htrans = io_dma_ahb_sig_out_htrans; // @[quasar.scala 273:28] - assign ahb_to_axi4_io_ahb_sig_out_hwrite = io_dma_ahb_sig_out_hwrite; // @[quasar.scala 273:28] - assign ahb_to_axi4_io_ahb_sig_out_hwdata = io_dma_ahb_sig_out_hwdata; // @[quasar.scala 273:28] - assign ahb_to_axi4_io_ahb_hsel = io_dma_ahb_hsel; // @[quasar.scala 273:28] - assign ahb_to_axi4_io_ahb_hreadyin = io_dma_ahb_hreadyin; // @[quasar.scala 273:28] endmodule module quasar_wrapper( input clock, @@ -85313,52 +82783,162 @@ module quasar_wrapper( input io_nmi_int, input [30:0] io_nmi_vec, input [30:0] io_jtag_id, - input [63:0] io_lsu_brg_in_hrdata, - input io_lsu_brg_in_hready, - input io_lsu_brg_in_hresp, - output [31:0] io_lsu_brg_out_haddr, - output [2:0] io_lsu_brg_out_hburst, - output io_lsu_brg_out_hmastlock, - output [3:0] io_lsu_brg_out_hprot, - output [2:0] io_lsu_brg_out_hsize, - output [1:0] io_lsu_brg_out_htrans, - output io_lsu_brg_out_hwrite, - output [63:0] io_lsu_brg_out_hwdata, - input [63:0] io_ifu_brg_in_hrdata, - input io_ifu_brg_in_hready, - input io_ifu_brg_in_hresp, - output [31:0] io_ifu_brg_out_haddr, - output [2:0] io_ifu_brg_out_hburst, - output io_ifu_brg_out_hmastlock, - output [3:0] io_ifu_brg_out_hprot, - output [2:0] io_ifu_brg_out_hsize, - output [1:0] io_ifu_brg_out_htrans, - output io_ifu_brg_out_hwrite, - output [63:0] io_ifu_brg_out_hwdata, - input [63:0] io_sb_brg_in_hrdata, - input io_sb_brg_in_hready, - input io_sb_brg_in_hresp, - output [31:0] io_sb_brg_out_haddr, - output [2:0] io_sb_brg_out_hburst, - output io_sb_brg_out_hmastlock, - output [3:0] io_sb_brg_out_hprot, - output [2:0] io_sb_brg_out_hsize, - output [1:0] io_sb_brg_out_htrans, - output io_sb_brg_out_hwrite, - output [63:0] io_sb_brg_out_hwdata, - output [63:0] io_dma_brg_sig_in_hrdata, - output io_dma_brg_sig_in_hready, - output io_dma_brg_sig_in_hresp, - input [31:0] io_dma_brg_sig_out_haddr, - input [2:0] io_dma_brg_sig_out_hburst, - input io_dma_brg_sig_out_hmastlock, - input [3:0] io_dma_brg_sig_out_hprot, - input [2:0] io_dma_brg_sig_out_hsize, - input [1:0] io_dma_brg_sig_out_htrans, - input io_dma_brg_sig_out_hwrite, - input [63:0] io_dma_brg_sig_out_hwdata, - input io_dma_brg_hsel, - input io_dma_brg_hreadyin, + input io_lsu_brg_aw_ready, + output io_lsu_brg_aw_valid, + output [2:0] io_lsu_brg_aw_bits_id, + output [31:0] io_lsu_brg_aw_bits_addr, + output [3:0] io_lsu_brg_aw_bits_region, + output [7:0] io_lsu_brg_aw_bits_len, + output [2:0] io_lsu_brg_aw_bits_size, + output [1:0] io_lsu_brg_aw_bits_burst, + output io_lsu_brg_aw_bits_lock, + output [3:0] io_lsu_brg_aw_bits_cache, + output [2:0] io_lsu_brg_aw_bits_prot, + output [3:0] io_lsu_brg_aw_bits_qos, + input io_lsu_brg_w_ready, + output io_lsu_brg_w_valid, + output [63:0] io_lsu_brg_w_bits_data, + output [7:0] io_lsu_brg_w_bits_strb, + output io_lsu_brg_w_bits_last, + output io_lsu_brg_b_ready, + input io_lsu_brg_b_valid, + input [1:0] io_lsu_brg_b_bits_resp, + input [2:0] io_lsu_brg_b_bits_id, + input io_lsu_brg_ar_ready, + output io_lsu_brg_ar_valid, + output [2:0] io_lsu_brg_ar_bits_id, + output [31:0] io_lsu_brg_ar_bits_addr, + output [3:0] io_lsu_brg_ar_bits_region, + output [7:0] io_lsu_brg_ar_bits_len, + output [2:0] io_lsu_brg_ar_bits_size, + output [1:0] io_lsu_brg_ar_bits_burst, + output io_lsu_brg_ar_bits_lock, + output [3:0] io_lsu_brg_ar_bits_cache, + output [2:0] io_lsu_brg_ar_bits_prot, + output [3:0] io_lsu_brg_ar_bits_qos, + output io_lsu_brg_r_ready, + input io_lsu_brg_r_valid, + input [2:0] io_lsu_brg_r_bits_id, + input [63:0] io_lsu_brg_r_bits_data, + input [1:0] io_lsu_brg_r_bits_resp, + input io_lsu_brg_r_bits_last, + input io_ifu_brg_aw_ready, + output io_ifu_brg_aw_valid, + output [2:0] io_ifu_brg_aw_bits_id, + output [31:0] io_ifu_brg_aw_bits_addr, + output [3:0] io_ifu_brg_aw_bits_region, + output [7:0] io_ifu_brg_aw_bits_len, + output [2:0] io_ifu_brg_aw_bits_size, + output [1:0] io_ifu_brg_aw_bits_burst, + output io_ifu_brg_aw_bits_lock, + output [3:0] io_ifu_brg_aw_bits_cache, + output [2:0] io_ifu_brg_aw_bits_prot, + output [3:0] io_ifu_brg_aw_bits_qos, + input io_ifu_brg_w_ready, + output io_ifu_brg_w_valid, + output [63:0] io_ifu_brg_w_bits_data, + output [7:0] io_ifu_brg_w_bits_strb, + output io_ifu_brg_w_bits_last, + output io_ifu_brg_b_ready, + input io_ifu_brg_b_valid, + input [1:0] io_ifu_brg_b_bits_resp, + input [2:0] io_ifu_brg_b_bits_id, + input io_ifu_brg_ar_ready, + output io_ifu_brg_ar_valid, + output [2:0] io_ifu_brg_ar_bits_id, + output [31:0] io_ifu_brg_ar_bits_addr, + output [3:0] io_ifu_brg_ar_bits_region, + output [7:0] io_ifu_brg_ar_bits_len, + output [2:0] io_ifu_brg_ar_bits_size, + output [1:0] io_ifu_brg_ar_bits_burst, + output io_ifu_brg_ar_bits_lock, + output [3:0] io_ifu_brg_ar_bits_cache, + output [2:0] io_ifu_brg_ar_bits_prot, + output [3:0] io_ifu_brg_ar_bits_qos, + output io_ifu_brg_r_ready, + input io_ifu_brg_r_valid, + input [2:0] io_ifu_brg_r_bits_id, + input [63:0] io_ifu_brg_r_bits_data, + input [1:0] io_ifu_brg_r_bits_resp, + input io_ifu_brg_r_bits_last, + input io_sb_brg_aw_ready, + output io_sb_brg_aw_valid, + output io_sb_brg_aw_bits_id, + output [31:0] io_sb_brg_aw_bits_addr, + output [3:0] io_sb_brg_aw_bits_region, + output [7:0] io_sb_brg_aw_bits_len, + output [2:0] io_sb_brg_aw_bits_size, + output [1:0] io_sb_brg_aw_bits_burst, + output io_sb_brg_aw_bits_lock, + output [3:0] io_sb_brg_aw_bits_cache, + output [2:0] io_sb_brg_aw_bits_prot, + output [3:0] io_sb_brg_aw_bits_qos, + input io_sb_brg_w_ready, + output io_sb_brg_w_valid, + output [63:0] io_sb_brg_w_bits_data, + output [7:0] io_sb_brg_w_bits_strb, + output io_sb_brg_w_bits_last, + output io_sb_brg_b_ready, + input io_sb_brg_b_valid, + input [1:0] io_sb_brg_b_bits_resp, + input io_sb_brg_b_bits_id, + input io_sb_brg_ar_ready, + output io_sb_brg_ar_valid, + output io_sb_brg_ar_bits_id, + output [31:0] io_sb_brg_ar_bits_addr, + output [3:0] io_sb_brg_ar_bits_region, + output [7:0] io_sb_brg_ar_bits_len, + output [2:0] io_sb_brg_ar_bits_size, + output [1:0] io_sb_brg_ar_bits_burst, + output io_sb_brg_ar_bits_lock, + output [3:0] io_sb_brg_ar_bits_cache, + output [2:0] io_sb_brg_ar_bits_prot, + output [3:0] io_sb_brg_ar_bits_qos, + output io_sb_brg_r_ready, + input io_sb_brg_r_valid, + input io_sb_brg_r_bits_id, + input [63:0] io_sb_brg_r_bits_data, + input [1:0] io_sb_brg_r_bits_resp, + input io_sb_brg_r_bits_last, + output io_dma_brg_aw_ready, + input io_dma_brg_aw_valid, + input io_dma_brg_aw_bits_id, + input [31:0] io_dma_brg_aw_bits_addr, + input [3:0] io_dma_brg_aw_bits_region, + input [7:0] io_dma_brg_aw_bits_len, + input [2:0] io_dma_brg_aw_bits_size, + input [1:0] io_dma_brg_aw_bits_burst, + input io_dma_brg_aw_bits_lock, + input [3:0] io_dma_brg_aw_bits_cache, + input [2:0] io_dma_brg_aw_bits_prot, + input [3:0] io_dma_brg_aw_bits_qos, + output io_dma_brg_w_ready, + input io_dma_brg_w_valid, + input [63:0] io_dma_brg_w_bits_data, + input [7:0] io_dma_brg_w_bits_strb, + input io_dma_brg_w_bits_last, + input io_dma_brg_b_ready, + output io_dma_brg_b_valid, + output [1:0] io_dma_brg_b_bits_resp, + output io_dma_brg_b_bits_id, + output io_dma_brg_ar_ready, + input io_dma_brg_ar_valid, + input io_dma_brg_ar_bits_id, + input [31:0] io_dma_brg_ar_bits_addr, + input [3:0] io_dma_brg_ar_bits_region, + input [7:0] io_dma_brg_ar_bits_len, + input [2:0] io_dma_brg_ar_bits_size, + input [1:0] io_dma_brg_ar_bits_burst, + input io_dma_brg_ar_bits_lock, + input [3:0] io_dma_brg_ar_bits_cache, + input [2:0] io_dma_brg_ar_bits_prot, + input [3:0] io_dma_brg_ar_bits_qos, + input io_dma_brg_r_ready, + output io_dma_brg_r_valid, + output io_dma_brg_r_bits_id, + output [63:0] io_dma_brg_r_bits_data, + output [1:0] io_dma_brg_r_bits_resp, + output io_dma_brg_r_bits_last, input io_lsu_bus_clk_en, input io_ifu_bus_clk_en, input io_dbg_bus_clk_en, @@ -85461,40 +83041,81 @@ module quasar_wrapper( wire dmi_wrapper_dmi_hard_reset; // @[quasar_wrapper.scala 64:27] wire core_clock; // @[quasar_wrapper.scala 65:20] wire core_reset; // @[quasar_wrapper.scala 65:20] - wire [63:0] core_io_lsu_ahb_in_hrdata; // @[quasar_wrapper.scala 65:20] - wire core_io_lsu_ahb_in_hready; // @[quasar_wrapper.scala 65:20] - wire core_io_lsu_ahb_in_hresp; // @[quasar_wrapper.scala 65:20] - wire [31:0] core_io_lsu_ahb_out_haddr; // @[quasar_wrapper.scala 65:20] - wire [2:0] core_io_lsu_ahb_out_hsize; // @[quasar_wrapper.scala 65:20] - wire [1:0] core_io_lsu_ahb_out_htrans; // @[quasar_wrapper.scala 65:20] - wire core_io_lsu_ahb_out_hwrite; // @[quasar_wrapper.scala 65:20] - wire [63:0] core_io_lsu_ahb_out_hwdata; // @[quasar_wrapper.scala 65:20] - wire [63:0] core_io_ifu_ahb_in_hrdata; // @[quasar_wrapper.scala 65:20] - wire core_io_ifu_ahb_in_hready; // @[quasar_wrapper.scala 65:20] - wire core_io_ifu_ahb_in_hresp; // @[quasar_wrapper.scala 65:20] - wire [31:0] core_io_ifu_ahb_out_haddr; // @[quasar_wrapper.scala 65:20] - wire [2:0] core_io_ifu_ahb_out_hsize; // @[quasar_wrapper.scala 65:20] - wire [1:0] core_io_ifu_ahb_out_htrans; // @[quasar_wrapper.scala 65:20] - wire core_io_ifu_ahb_out_hwrite; // @[quasar_wrapper.scala 65:20] - wire [63:0] core_io_ifu_ahb_out_hwdata; // @[quasar_wrapper.scala 65:20] - wire [63:0] core_io_sb_ahb_in_hrdata; // @[quasar_wrapper.scala 65:20] - wire core_io_sb_ahb_in_hready; // @[quasar_wrapper.scala 65:20] - wire core_io_sb_ahb_in_hresp; // @[quasar_wrapper.scala 65:20] - wire [31:0] core_io_sb_ahb_out_haddr; // @[quasar_wrapper.scala 65:20] - wire [2:0] core_io_sb_ahb_out_hsize; // @[quasar_wrapper.scala 65:20] - wire [1:0] core_io_sb_ahb_out_htrans; // @[quasar_wrapper.scala 65:20] - wire core_io_sb_ahb_out_hwrite; // @[quasar_wrapper.scala 65:20] - wire [63:0] core_io_sb_ahb_out_hwdata; // @[quasar_wrapper.scala 65:20] - wire [63:0] core_io_dma_ahb_sig_in_hrdata; // @[quasar_wrapper.scala 65:20] - wire core_io_dma_ahb_sig_in_hready; // @[quasar_wrapper.scala 65:20] - wire core_io_dma_ahb_sig_in_hresp; // @[quasar_wrapper.scala 65:20] - wire [31:0] core_io_dma_ahb_sig_out_haddr; // @[quasar_wrapper.scala 65:20] - wire [2:0] core_io_dma_ahb_sig_out_hsize; // @[quasar_wrapper.scala 65:20] - wire [1:0] core_io_dma_ahb_sig_out_htrans; // @[quasar_wrapper.scala 65:20] - wire core_io_dma_ahb_sig_out_hwrite; // @[quasar_wrapper.scala 65:20] - wire [63:0] core_io_dma_ahb_sig_out_hwdata; // @[quasar_wrapper.scala 65:20] - wire core_io_dma_ahb_hsel; // @[quasar_wrapper.scala 65:20] - wire core_io_dma_ahb_hreadyin; // @[quasar_wrapper.scala 65:20] + wire core_io_lsu_axi_aw_ready; // @[quasar_wrapper.scala 65:20] + wire core_io_lsu_axi_aw_valid; // @[quasar_wrapper.scala 65:20] + wire [2:0] core_io_lsu_axi_aw_bits_id; // @[quasar_wrapper.scala 65:20] + wire [31:0] core_io_lsu_axi_aw_bits_addr; // @[quasar_wrapper.scala 65:20] + wire [3:0] core_io_lsu_axi_aw_bits_region; // @[quasar_wrapper.scala 65:20] + wire [2:0] core_io_lsu_axi_aw_bits_size; // @[quasar_wrapper.scala 65:20] + wire [3:0] core_io_lsu_axi_aw_bits_cache; // @[quasar_wrapper.scala 65:20] + wire core_io_lsu_axi_w_ready; // @[quasar_wrapper.scala 65:20] + wire core_io_lsu_axi_w_valid; // @[quasar_wrapper.scala 65:20] + wire [63:0] core_io_lsu_axi_w_bits_data; // @[quasar_wrapper.scala 65:20] + wire [7:0] core_io_lsu_axi_w_bits_strb; // @[quasar_wrapper.scala 65:20] + wire core_io_lsu_axi_b_valid; // @[quasar_wrapper.scala 65:20] + wire [2:0] core_io_lsu_axi_b_bits_id; // @[quasar_wrapper.scala 65:20] + wire core_io_lsu_axi_ar_ready; // @[quasar_wrapper.scala 65:20] + wire core_io_lsu_axi_ar_valid; // @[quasar_wrapper.scala 65:20] + wire [2:0] core_io_lsu_axi_ar_bits_id; // @[quasar_wrapper.scala 65:20] + wire [31:0] core_io_lsu_axi_ar_bits_addr; // @[quasar_wrapper.scala 65:20] + wire [3:0] core_io_lsu_axi_ar_bits_region; // @[quasar_wrapper.scala 65:20] + wire [2:0] core_io_lsu_axi_ar_bits_size; // @[quasar_wrapper.scala 65:20] + wire [3:0] core_io_lsu_axi_ar_bits_cache; // @[quasar_wrapper.scala 65:20] + wire core_io_lsu_axi_r_valid; // @[quasar_wrapper.scala 65:20] + wire [2:0] core_io_lsu_axi_r_bits_id; // @[quasar_wrapper.scala 65:20] + wire [63:0] core_io_lsu_axi_r_bits_data; // @[quasar_wrapper.scala 65:20] + wire [1:0] core_io_lsu_axi_r_bits_resp; // @[quasar_wrapper.scala 65:20] + wire core_io_ifu_axi_ar_ready; // @[quasar_wrapper.scala 65:20] + wire core_io_ifu_axi_ar_valid; // @[quasar_wrapper.scala 65:20] + wire [2:0] core_io_ifu_axi_ar_bits_id; // @[quasar_wrapper.scala 65:20] + wire [31:0] core_io_ifu_axi_ar_bits_addr; // @[quasar_wrapper.scala 65:20] + wire [3:0] core_io_ifu_axi_ar_bits_region; // @[quasar_wrapper.scala 65:20] + wire core_io_ifu_axi_r_valid; // @[quasar_wrapper.scala 65:20] + wire [2:0] core_io_ifu_axi_r_bits_id; // @[quasar_wrapper.scala 65:20] + wire [63:0] core_io_ifu_axi_r_bits_data; // @[quasar_wrapper.scala 65:20] + wire [1:0] core_io_ifu_axi_r_bits_resp; // @[quasar_wrapper.scala 65:20] + wire core_io_sb_axi_aw_ready; // @[quasar_wrapper.scala 65:20] + wire core_io_sb_axi_aw_valid; // @[quasar_wrapper.scala 65:20] + wire [31:0] core_io_sb_axi_aw_bits_addr; // @[quasar_wrapper.scala 65:20] + wire [3:0] core_io_sb_axi_aw_bits_region; // @[quasar_wrapper.scala 65:20] + wire [2:0] core_io_sb_axi_aw_bits_size; // @[quasar_wrapper.scala 65:20] + wire core_io_sb_axi_w_ready; // @[quasar_wrapper.scala 65:20] + wire core_io_sb_axi_w_valid; // @[quasar_wrapper.scala 65:20] + wire [63:0] core_io_sb_axi_w_bits_data; // @[quasar_wrapper.scala 65:20] + wire [7:0] core_io_sb_axi_w_bits_strb; // @[quasar_wrapper.scala 65:20] + wire core_io_sb_axi_b_valid; // @[quasar_wrapper.scala 65:20] + wire [1:0] core_io_sb_axi_b_bits_resp; // @[quasar_wrapper.scala 65:20] + wire core_io_sb_axi_ar_ready; // @[quasar_wrapper.scala 65:20] + wire core_io_sb_axi_ar_valid; // @[quasar_wrapper.scala 65:20] + wire [31:0] core_io_sb_axi_ar_bits_addr; // @[quasar_wrapper.scala 65:20] + wire [3:0] core_io_sb_axi_ar_bits_region; // @[quasar_wrapper.scala 65:20] + wire [2:0] core_io_sb_axi_ar_bits_size; // @[quasar_wrapper.scala 65:20] + wire core_io_sb_axi_r_valid; // @[quasar_wrapper.scala 65:20] + wire [63:0] core_io_sb_axi_r_bits_data; // @[quasar_wrapper.scala 65:20] + wire [1:0] core_io_sb_axi_r_bits_resp; // @[quasar_wrapper.scala 65:20] + wire core_io_dma_axi_aw_ready; // @[quasar_wrapper.scala 65:20] + wire core_io_dma_axi_aw_valid; // @[quasar_wrapper.scala 65:20] + wire core_io_dma_axi_aw_bits_id; // @[quasar_wrapper.scala 65:20] + wire [31:0] core_io_dma_axi_aw_bits_addr; // @[quasar_wrapper.scala 65:20] + wire [2:0] core_io_dma_axi_aw_bits_size; // @[quasar_wrapper.scala 65:20] + wire core_io_dma_axi_w_ready; // @[quasar_wrapper.scala 65:20] + wire core_io_dma_axi_w_valid; // @[quasar_wrapper.scala 65:20] + wire [63:0] core_io_dma_axi_w_bits_data; // @[quasar_wrapper.scala 65:20] + wire [7:0] core_io_dma_axi_w_bits_strb; // @[quasar_wrapper.scala 65:20] + wire core_io_dma_axi_b_ready; // @[quasar_wrapper.scala 65:20] + wire core_io_dma_axi_b_valid; // @[quasar_wrapper.scala 65:20] + wire [1:0] core_io_dma_axi_b_bits_resp; // @[quasar_wrapper.scala 65:20] + wire core_io_dma_axi_b_bits_id; // @[quasar_wrapper.scala 65:20] + wire core_io_dma_axi_ar_ready; // @[quasar_wrapper.scala 65:20] + wire core_io_dma_axi_ar_valid; // @[quasar_wrapper.scala 65:20] + wire core_io_dma_axi_ar_bits_id; // @[quasar_wrapper.scala 65:20] + wire [31:0] core_io_dma_axi_ar_bits_addr; // @[quasar_wrapper.scala 65:20] + wire [2:0] core_io_dma_axi_ar_bits_size; // @[quasar_wrapper.scala 65:20] + wire core_io_dma_axi_r_ready; // @[quasar_wrapper.scala 65:20] + wire core_io_dma_axi_r_valid; // @[quasar_wrapper.scala 65:20] + wire core_io_dma_axi_r_bits_id; // @[quasar_wrapper.scala 65:20] + wire [63:0] core_io_dma_axi_r_bits_data; // @[quasar_wrapper.scala 65:20] + wire [1:0] core_io_dma_axi_r_bits_resp; // @[quasar_wrapper.scala 65:20] wire core_io_dbg_rst_l; // @[quasar_wrapper.scala 65:20] wire [30:0] core_io_rst_vec; // @[quasar_wrapper.scala 65:20] wire core_io_nmi_int; // @[quasar_wrapper.scala 65:20] @@ -85647,40 +83268,81 @@ module quasar_wrapper( quasar core ( // @[quasar_wrapper.scala 65:20] .clock(core_clock), .reset(core_reset), - .io_lsu_ahb_in_hrdata(core_io_lsu_ahb_in_hrdata), - .io_lsu_ahb_in_hready(core_io_lsu_ahb_in_hready), - .io_lsu_ahb_in_hresp(core_io_lsu_ahb_in_hresp), - .io_lsu_ahb_out_haddr(core_io_lsu_ahb_out_haddr), - .io_lsu_ahb_out_hsize(core_io_lsu_ahb_out_hsize), - .io_lsu_ahb_out_htrans(core_io_lsu_ahb_out_htrans), - .io_lsu_ahb_out_hwrite(core_io_lsu_ahb_out_hwrite), - .io_lsu_ahb_out_hwdata(core_io_lsu_ahb_out_hwdata), - .io_ifu_ahb_in_hrdata(core_io_ifu_ahb_in_hrdata), - .io_ifu_ahb_in_hready(core_io_ifu_ahb_in_hready), - .io_ifu_ahb_in_hresp(core_io_ifu_ahb_in_hresp), - .io_ifu_ahb_out_haddr(core_io_ifu_ahb_out_haddr), - .io_ifu_ahb_out_hsize(core_io_ifu_ahb_out_hsize), - .io_ifu_ahb_out_htrans(core_io_ifu_ahb_out_htrans), - .io_ifu_ahb_out_hwrite(core_io_ifu_ahb_out_hwrite), - .io_ifu_ahb_out_hwdata(core_io_ifu_ahb_out_hwdata), - .io_sb_ahb_in_hrdata(core_io_sb_ahb_in_hrdata), - .io_sb_ahb_in_hready(core_io_sb_ahb_in_hready), - .io_sb_ahb_in_hresp(core_io_sb_ahb_in_hresp), - .io_sb_ahb_out_haddr(core_io_sb_ahb_out_haddr), - .io_sb_ahb_out_hsize(core_io_sb_ahb_out_hsize), - .io_sb_ahb_out_htrans(core_io_sb_ahb_out_htrans), - .io_sb_ahb_out_hwrite(core_io_sb_ahb_out_hwrite), - .io_sb_ahb_out_hwdata(core_io_sb_ahb_out_hwdata), - .io_dma_ahb_sig_in_hrdata(core_io_dma_ahb_sig_in_hrdata), - .io_dma_ahb_sig_in_hready(core_io_dma_ahb_sig_in_hready), - .io_dma_ahb_sig_in_hresp(core_io_dma_ahb_sig_in_hresp), - .io_dma_ahb_sig_out_haddr(core_io_dma_ahb_sig_out_haddr), - .io_dma_ahb_sig_out_hsize(core_io_dma_ahb_sig_out_hsize), - .io_dma_ahb_sig_out_htrans(core_io_dma_ahb_sig_out_htrans), - .io_dma_ahb_sig_out_hwrite(core_io_dma_ahb_sig_out_hwrite), - .io_dma_ahb_sig_out_hwdata(core_io_dma_ahb_sig_out_hwdata), - .io_dma_ahb_hsel(core_io_dma_ahb_hsel), - .io_dma_ahb_hreadyin(core_io_dma_ahb_hreadyin), + .io_lsu_axi_aw_ready(core_io_lsu_axi_aw_ready), + .io_lsu_axi_aw_valid(core_io_lsu_axi_aw_valid), + .io_lsu_axi_aw_bits_id(core_io_lsu_axi_aw_bits_id), + .io_lsu_axi_aw_bits_addr(core_io_lsu_axi_aw_bits_addr), + .io_lsu_axi_aw_bits_region(core_io_lsu_axi_aw_bits_region), + .io_lsu_axi_aw_bits_size(core_io_lsu_axi_aw_bits_size), + .io_lsu_axi_aw_bits_cache(core_io_lsu_axi_aw_bits_cache), + .io_lsu_axi_w_ready(core_io_lsu_axi_w_ready), + .io_lsu_axi_w_valid(core_io_lsu_axi_w_valid), + .io_lsu_axi_w_bits_data(core_io_lsu_axi_w_bits_data), + .io_lsu_axi_w_bits_strb(core_io_lsu_axi_w_bits_strb), + .io_lsu_axi_b_valid(core_io_lsu_axi_b_valid), + .io_lsu_axi_b_bits_id(core_io_lsu_axi_b_bits_id), + .io_lsu_axi_ar_ready(core_io_lsu_axi_ar_ready), + .io_lsu_axi_ar_valid(core_io_lsu_axi_ar_valid), + .io_lsu_axi_ar_bits_id(core_io_lsu_axi_ar_bits_id), + .io_lsu_axi_ar_bits_addr(core_io_lsu_axi_ar_bits_addr), + .io_lsu_axi_ar_bits_region(core_io_lsu_axi_ar_bits_region), + .io_lsu_axi_ar_bits_size(core_io_lsu_axi_ar_bits_size), + .io_lsu_axi_ar_bits_cache(core_io_lsu_axi_ar_bits_cache), + .io_lsu_axi_r_valid(core_io_lsu_axi_r_valid), + .io_lsu_axi_r_bits_id(core_io_lsu_axi_r_bits_id), + .io_lsu_axi_r_bits_data(core_io_lsu_axi_r_bits_data), + .io_lsu_axi_r_bits_resp(core_io_lsu_axi_r_bits_resp), + .io_ifu_axi_ar_ready(core_io_ifu_axi_ar_ready), + .io_ifu_axi_ar_valid(core_io_ifu_axi_ar_valid), + .io_ifu_axi_ar_bits_id(core_io_ifu_axi_ar_bits_id), + .io_ifu_axi_ar_bits_addr(core_io_ifu_axi_ar_bits_addr), + .io_ifu_axi_ar_bits_region(core_io_ifu_axi_ar_bits_region), + .io_ifu_axi_r_valid(core_io_ifu_axi_r_valid), + .io_ifu_axi_r_bits_id(core_io_ifu_axi_r_bits_id), + .io_ifu_axi_r_bits_data(core_io_ifu_axi_r_bits_data), + .io_ifu_axi_r_bits_resp(core_io_ifu_axi_r_bits_resp), + .io_sb_axi_aw_ready(core_io_sb_axi_aw_ready), + .io_sb_axi_aw_valid(core_io_sb_axi_aw_valid), + .io_sb_axi_aw_bits_addr(core_io_sb_axi_aw_bits_addr), + .io_sb_axi_aw_bits_region(core_io_sb_axi_aw_bits_region), + .io_sb_axi_aw_bits_size(core_io_sb_axi_aw_bits_size), + .io_sb_axi_w_ready(core_io_sb_axi_w_ready), + .io_sb_axi_w_valid(core_io_sb_axi_w_valid), + .io_sb_axi_w_bits_data(core_io_sb_axi_w_bits_data), + .io_sb_axi_w_bits_strb(core_io_sb_axi_w_bits_strb), + .io_sb_axi_b_valid(core_io_sb_axi_b_valid), + .io_sb_axi_b_bits_resp(core_io_sb_axi_b_bits_resp), + .io_sb_axi_ar_ready(core_io_sb_axi_ar_ready), + .io_sb_axi_ar_valid(core_io_sb_axi_ar_valid), + .io_sb_axi_ar_bits_addr(core_io_sb_axi_ar_bits_addr), + .io_sb_axi_ar_bits_region(core_io_sb_axi_ar_bits_region), + .io_sb_axi_ar_bits_size(core_io_sb_axi_ar_bits_size), + .io_sb_axi_r_valid(core_io_sb_axi_r_valid), + .io_sb_axi_r_bits_data(core_io_sb_axi_r_bits_data), + .io_sb_axi_r_bits_resp(core_io_sb_axi_r_bits_resp), + .io_dma_axi_aw_ready(core_io_dma_axi_aw_ready), + .io_dma_axi_aw_valid(core_io_dma_axi_aw_valid), + .io_dma_axi_aw_bits_id(core_io_dma_axi_aw_bits_id), + .io_dma_axi_aw_bits_addr(core_io_dma_axi_aw_bits_addr), + .io_dma_axi_aw_bits_size(core_io_dma_axi_aw_bits_size), + .io_dma_axi_w_ready(core_io_dma_axi_w_ready), + .io_dma_axi_w_valid(core_io_dma_axi_w_valid), + .io_dma_axi_w_bits_data(core_io_dma_axi_w_bits_data), + .io_dma_axi_w_bits_strb(core_io_dma_axi_w_bits_strb), + .io_dma_axi_b_ready(core_io_dma_axi_b_ready), + .io_dma_axi_b_valid(core_io_dma_axi_b_valid), + .io_dma_axi_b_bits_resp(core_io_dma_axi_b_bits_resp), + .io_dma_axi_b_bits_id(core_io_dma_axi_b_bits_id), + .io_dma_axi_ar_ready(core_io_dma_axi_ar_ready), + .io_dma_axi_ar_valid(core_io_dma_axi_ar_valid), + .io_dma_axi_ar_bits_id(core_io_dma_axi_ar_bits_id), + .io_dma_axi_ar_bits_addr(core_io_dma_axi_ar_bits_addr), + .io_dma_axi_ar_bits_size(core_io_dma_axi_ar_bits_size), + .io_dma_axi_r_ready(core_io_dma_axi_r_ready), + .io_dma_axi_r_valid(core_io_dma_axi_r_valid), + .io_dma_axi_r_bits_id(core_io_dma_axi_r_bits_id), + .io_dma_axi_r_bits_data(core_io_dma_axi_r_bits_data), + .io_dma_axi_r_bits_resp(core_io_dma_axi_r_bits_resp), .io_dbg_rst_l(core_io_dbg_rst_l), .io_rst_vec(core_io_rst_vec), .io_nmi_int(core_io_nmi_int), @@ -85766,33 +83428,101 @@ module quasar_wrapper( .io_soft_int(core_io_soft_int), .io_scan_mode(core_io_scan_mode) ); - assign io_lsu_brg_out_haddr = core_io_lsu_ahb_out_haddr; // @[quasar_wrapper.scala 111:21] - assign io_lsu_brg_out_hburst = 3'h0; // @[quasar_wrapper.scala 111:21] - assign io_lsu_brg_out_hmastlock = 1'h0; // @[quasar_wrapper.scala 111:21] - assign io_lsu_brg_out_hprot = 4'h3; // @[quasar_wrapper.scala 111:21] - assign io_lsu_brg_out_hsize = core_io_lsu_ahb_out_hsize; // @[quasar_wrapper.scala 111:21] - assign io_lsu_brg_out_htrans = core_io_lsu_ahb_out_htrans; // @[quasar_wrapper.scala 111:21] - assign io_lsu_brg_out_hwrite = core_io_lsu_ahb_out_hwrite; // @[quasar_wrapper.scala 111:21] - assign io_lsu_brg_out_hwdata = core_io_lsu_ahb_out_hwdata; // @[quasar_wrapper.scala 111:21] - assign io_ifu_brg_out_haddr = core_io_ifu_ahb_out_haddr; // @[quasar_wrapper.scala 110:21] - assign io_ifu_brg_out_hburst = 3'h0; // @[quasar_wrapper.scala 110:21] - assign io_ifu_brg_out_hmastlock = 1'h0; // @[quasar_wrapper.scala 110:21] - assign io_ifu_brg_out_hprot = 4'h3; // @[quasar_wrapper.scala 110:21] - assign io_ifu_brg_out_hsize = core_io_ifu_ahb_out_hsize; // @[quasar_wrapper.scala 110:21] - assign io_ifu_brg_out_htrans = core_io_ifu_ahb_out_htrans; // @[quasar_wrapper.scala 110:21] - assign io_ifu_brg_out_hwrite = core_io_ifu_ahb_out_hwrite; // @[quasar_wrapper.scala 110:21] - assign io_ifu_brg_out_hwdata = core_io_ifu_ahb_out_hwdata; // @[quasar_wrapper.scala 110:21] - assign io_sb_brg_out_haddr = core_io_sb_ahb_out_haddr; // @[quasar_wrapper.scala 112:20] - assign io_sb_brg_out_hburst = 3'h0; // @[quasar_wrapper.scala 112:20] - assign io_sb_brg_out_hmastlock = 1'h0; // @[quasar_wrapper.scala 112:20] - assign io_sb_brg_out_hprot = 4'h3; // @[quasar_wrapper.scala 112:20] - assign io_sb_brg_out_hsize = core_io_sb_ahb_out_hsize; // @[quasar_wrapper.scala 112:20] - assign io_sb_brg_out_htrans = core_io_sb_ahb_out_htrans; // @[quasar_wrapper.scala 112:20] - assign io_sb_brg_out_hwrite = core_io_sb_ahb_out_hwrite; // @[quasar_wrapper.scala 112:20] - assign io_sb_brg_out_hwdata = core_io_sb_ahb_out_hwdata; // @[quasar_wrapper.scala 112:20] - assign io_dma_brg_sig_in_hrdata = core_io_dma_ahb_sig_in_hrdata; // @[quasar_wrapper.scala 113:21] - assign io_dma_brg_sig_in_hready = core_io_dma_ahb_sig_in_hready; // @[quasar_wrapper.scala 113:21] - assign io_dma_brg_sig_in_hresp = core_io_dma_ahb_sig_in_hresp; // @[quasar_wrapper.scala 113:21] + assign io_lsu_brg_aw_valid = core_io_lsu_axi_aw_valid; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_aw_bits_id = core_io_lsu_axi_aw_bits_id; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_aw_bits_addr = core_io_lsu_axi_aw_bits_addr; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_aw_bits_region = core_io_lsu_axi_aw_bits_region; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_aw_bits_size = core_io_lsu_axi_aw_bits_size; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_aw_bits_burst = 2'h1; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_aw_bits_cache = core_io_lsu_axi_aw_bits_cache; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_w_valid = core_io_lsu_axi_w_valid; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_w_bits_data = core_io_lsu_axi_w_bits_data; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_w_bits_strb = core_io_lsu_axi_w_bits_strb; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_w_bits_last = 1'h1; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_b_ready = 1'h1; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_ar_valid = core_io_lsu_axi_ar_valid; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_ar_bits_id = core_io_lsu_axi_ar_bits_id; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_ar_bits_addr = core_io_lsu_axi_ar_bits_addr; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_ar_bits_region = core_io_lsu_axi_ar_bits_region; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_ar_bits_size = core_io_lsu_axi_ar_bits_size; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_ar_bits_cache = core_io_lsu_axi_ar_bits_cache; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_r_ready = 1'h1; // @[quasar_wrapper.scala 104:21] + assign io_ifu_brg_aw_valid = 1'h0; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_aw_bits_id = 3'h0; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_aw_bits_addr = 32'h0; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_aw_bits_region = 4'h0; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_aw_bits_size = 3'h0; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_aw_bits_burst = 2'h0; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_aw_bits_cache = 4'h0; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_w_valid = 1'h0; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_w_bits_data = 64'h0; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_w_bits_strb = 8'h0; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_w_bits_last = 1'h0; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_b_ready = 1'h0; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_ar_valid = core_io_ifu_axi_ar_valid; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_ar_bits_id = core_io_ifu_axi_ar_bits_id; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_ar_bits_addr = core_io_ifu_axi_ar_bits_addr; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_ar_bits_region = core_io_ifu_axi_ar_bits_region; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_ar_bits_size = 3'h3; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_ar_bits_cache = 4'hf; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_r_ready = 1'h1; // @[quasar_wrapper.scala 105:21] + assign io_sb_brg_aw_valid = core_io_sb_axi_aw_valid; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_aw_bits_id = 1'h0; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_aw_bits_addr = core_io_sb_axi_aw_bits_addr; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_aw_bits_region = core_io_sb_axi_aw_bits_region; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_aw_bits_size = core_io_sb_axi_aw_bits_size; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_aw_bits_burst = 2'h1; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_aw_bits_cache = 4'hf; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_w_valid = core_io_sb_axi_w_valid; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_w_bits_data = core_io_sb_axi_w_bits_data; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_w_bits_strb = core_io_sb_axi_w_bits_strb; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_w_bits_last = 1'h1; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_b_ready = 1'h1; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_ar_valid = core_io_sb_axi_ar_valid; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_ar_bits_id = 1'h0; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_ar_bits_addr = core_io_sb_axi_ar_bits_addr; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_ar_bits_region = core_io_sb_axi_ar_bits_region; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_ar_bits_size = core_io_sb_axi_ar_bits_size; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_ar_bits_cache = 4'h0; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_r_ready = 1'h1; // @[quasar_wrapper.scala 106:21] + assign io_dma_brg_aw_ready = core_io_dma_axi_aw_ready; // @[quasar_wrapper.scala 107:21] + assign io_dma_brg_w_ready = core_io_dma_axi_w_ready; // @[quasar_wrapper.scala 107:21] + assign io_dma_brg_b_valid = core_io_dma_axi_b_valid; // @[quasar_wrapper.scala 107:21] + assign io_dma_brg_b_bits_resp = core_io_dma_axi_b_bits_resp; // @[quasar_wrapper.scala 107:21] + assign io_dma_brg_b_bits_id = core_io_dma_axi_b_bits_id; // @[quasar_wrapper.scala 107:21] + assign io_dma_brg_ar_ready = core_io_dma_axi_ar_ready; // @[quasar_wrapper.scala 107:21] + assign io_dma_brg_r_valid = core_io_dma_axi_r_valid; // @[quasar_wrapper.scala 107:21] + assign io_dma_brg_r_bits_id = core_io_dma_axi_r_bits_id; // @[quasar_wrapper.scala 107:21] + assign io_dma_brg_r_bits_data = core_io_dma_axi_r_bits_data; // @[quasar_wrapper.scala 107:21] + assign io_dma_brg_r_bits_resp = core_io_dma_axi_r_bits_resp; // @[quasar_wrapper.scala 107:21] + assign io_dma_brg_r_bits_last = 1'h1; // @[quasar_wrapper.scala 107:21] assign io_dec_tlu_perfcnt0 = core_io_dec_tlu_perfcnt0; // @[quasar_wrapper.scala 159:23] assign io_dec_tlu_perfcnt1 = core_io_dec_tlu_perfcnt1; // @[quasar_wrapper.scala 160:23] assign io_dec_tlu_perfcnt2 = core_io_dec_tlu_perfcnt2; // @[quasar_wrapper.scala 161:23] @@ -85857,22 +83587,41 @@ module quasar_wrapper( assign dmi_wrapper_rd_data = core_io_dmi_reg_rdata; // @[quasar_wrapper.scala 73:26] assign core_clock = clock; assign core_reset = reset; - assign core_io_lsu_ahb_in_hrdata = io_lsu_brg_in_hrdata; // @[quasar_wrapper.scala 111:21] - assign core_io_lsu_ahb_in_hready = io_lsu_brg_in_hready; // @[quasar_wrapper.scala 111:21] - assign core_io_lsu_ahb_in_hresp = io_lsu_brg_in_hresp; // @[quasar_wrapper.scala 111:21] - assign core_io_ifu_ahb_in_hrdata = io_ifu_brg_in_hrdata; // @[quasar_wrapper.scala 110:21] - assign core_io_ifu_ahb_in_hready = io_ifu_brg_in_hready; // @[quasar_wrapper.scala 110:21] - assign core_io_ifu_ahb_in_hresp = io_ifu_brg_in_hresp; // @[quasar_wrapper.scala 110:21] - assign core_io_sb_ahb_in_hrdata = io_sb_brg_in_hrdata; // @[quasar_wrapper.scala 112:20] - assign core_io_sb_ahb_in_hready = io_sb_brg_in_hready; // @[quasar_wrapper.scala 112:20] - assign core_io_sb_ahb_in_hresp = io_sb_brg_in_hresp; // @[quasar_wrapper.scala 112:20] - assign core_io_dma_ahb_sig_out_haddr = io_dma_brg_sig_out_haddr; // @[quasar_wrapper.scala 113:21] - assign core_io_dma_ahb_sig_out_hsize = io_dma_brg_sig_out_hsize; // @[quasar_wrapper.scala 113:21] - assign core_io_dma_ahb_sig_out_htrans = io_dma_brg_sig_out_htrans; // @[quasar_wrapper.scala 113:21] - assign core_io_dma_ahb_sig_out_hwrite = io_dma_brg_sig_out_hwrite; // @[quasar_wrapper.scala 113:21] - assign core_io_dma_ahb_sig_out_hwdata = io_dma_brg_sig_out_hwdata; // @[quasar_wrapper.scala 113:21] - assign core_io_dma_ahb_hsel = io_dma_brg_hsel; // @[quasar_wrapper.scala 113:21] - assign core_io_dma_ahb_hreadyin = io_dma_brg_hreadyin; // @[quasar_wrapper.scala 113:21] + assign core_io_lsu_axi_aw_ready = io_lsu_brg_aw_ready; // @[quasar_wrapper.scala 104:21] + assign core_io_lsu_axi_w_ready = io_lsu_brg_w_ready; // @[quasar_wrapper.scala 104:21] + assign core_io_lsu_axi_b_valid = io_lsu_brg_b_valid; // @[quasar_wrapper.scala 104:21] + assign core_io_lsu_axi_b_bits_id = io_lsu_brg_b_bits_id; // @[quasar_wrapper.scala 104:21] + assign core_io_lsu_axi_ar_ready = io_lsu_brg_ar_ready; // @[quasar_wrapper.scala 104:21] + assign core_io_lsu_axi_r_valid = io_lsu_brg_r_valid; // @[quasar_wrapper.scala 104:21] + assign core_io_lsu_axi_r_bits_id = io_lsu_brg_r_bits_id; // @[quasar_wrapper.scala 104:21] + assign core_io_lsu_axi_r_bits_data = io_lsu_brg_r_bits_data; // @[quasar_wrapper.scala 104:21] + assign core_io_lsu_axi_r_bits_resp = io_lsu_brg_r_bits_resp; // @[quasar_wrapper.scala 104:21] + assign core_io_ifu_axi_ar_ready = io_ifu_brg_ar_ready; // @[quasar_wrapper.scala 105:21] + assign core_io_ifu_axi_r_valid = io_ifu_brg_r_valid; // @[quasar_wrapper.scala 105:21] + assign core_io_ifu_axi_r_bits_id = io_ifu_brg_r_bits_id; // @[quasar_wrapper.scala 105:21] + assign core_io_ifu_axi_r_bits_data = io_ifu_brg_r_bits_data; // @[quasar_wrapper.scala 105:21] + assign core_io_ifu_axi_r_bits_resp = io_ifu_brg_r_bits_resp; // @[quasar_wrapper.scala 105:21] + assign core_io_sb_axi_aw_ready = io_sb_brg_aw_ready; // @[quasar_wrapper.scala 106:21] + assign core_io_sb_axi_w_ready = io_sb_brg_w_ready; // @[quasar_wrapper.scala 106:21] + assign core_io_sb_axi_b_valid = io_sb_brg_b_valid; // @[quasar_wrapper.scala 106:21] + assign core_io_sb_axi_b_bits_resp = io_sb_brg_b_bits_resp; // @[quasar_wrapper.scala 106:21] + assign core_io_sb_axi_ar_ready = io_sb_brg_ar_ready; // @[quasar_wrapper.scala 106:21] + assign core_io_sb_axi_r_valid = io_sb_brg_r_valid; // @[quasar_wrapper.scala 106:21] + assign core_io_sb_axi_r_bits_data = io_sb_brg_r_bits_data; // @[quasar_wrapper.scala 106:21] + assign core_io_sb_axi_r_bits_resp = io_sb_brg_r_bits_resp; // @[quasar_wrapper.scala 106:21] + assign core_io_dma_axi_aw_valid = io_dma_brg_aw_valid; // @[quasar_wrapper.scala 107:21] + assign core_io_dma_axi_aw_bits_id = io_dma_brg_aw_bits_id; // @[quasar_wrapper.scala 107:21] + assign core_io_dma_axi_aw_bits_addr = io_dma_brg_aw_bits_addr; // @[quasar_wrapper.scala 107:21] + assign core_io_dma_axi_aw_bits_size = io_dma_brg_aw_bits_size; // @[quasar_wrapper.scala 107:21] + assign core_io_dma_axi_w_valid = io_dma_brg_w_valid; // @[quasar_wrapper.scala 107:21] + assign core_io_dma_axi_w_bits_data = io_dma_brg_w_bits_data; // @[quasar_wrapper.scala 107:21] + assign core_io_dma_axi_w_bits_strb = io_dma_brg_w_bits_strb; // @[quasar_wrapper.scala 107:21] + assign core_io_dma_axi_b_ready = io_dma_brg_b_ready; // @[quasar_wrapper.scala 107:21] + assign core_io_dma_axi_ar_valid = io_dma_brg_ar_valid; // @[quasar_wrapper.scala 107:21] + assign core_io_dma_axi_ar_bits_id = io_dma_brg_ar_bits_id; // @[quasar_wrapper.scala 107:21] + assign core_io_dma_axi_ar_bits_addr = io_dma_brg_ar_bits_addr; // @[quasar_wrapper.scala 107:21] + assign core_io_dma_axi_ar_bits_size = io_dma_brg_ar_bits_size; // @[quasar_wrapper.scala 107:21] + assign core_io_dma_axi_r_ready = io_dma_brg_r_ready; // @[quasar_wrapper.scala 107:21] assign core_io_dbg_rst_l = io_dbg_rst_l; // @[quasar_wrapper.scala 93:21 quasar_wrapper.scala 121:21] assign core_io_rst_vec = io_rst_vec; // @[quasar_wrapper.scala 122:19] assign core_io_nmi_int = io_nmi_int; // @[quasar_wrapper.scala 123:19] diff --git a/src/main/scala/dbg/dbg.scala b/src/main/scala/dbg/dbg.scala index 40b7e7a0..f57c8aff 100644 --- a/src/main/scala/dbg/dbg.scala +++ b/src/main/scala/dbg/dbg.scala @@ -101,8 +101,6 @@ class dbg extends Module with lib with RequireAsyncReset { dontTouch(dbg_dm_rst_l) val rst_temp = (dbg_dm_rst_l.asBool() & reset.asBool()).asAsyncReset() dontTouch(rst_temp) - val rst_not = (!dbg_dm_rst_l.asBool).asAsyncReset() - dontTouch(rst_not) io.dbg_core_rst_l := (!dmcontrol_reg(1)).asBool() val sbcs_wren = (io.dmi_reg_addr === "h38".U) & io.dmi_reg_en & io.dmi_reg_wr_en & (sb_state === sb_state_t.sbidle) @@ -126,7 +124,7 @@ class dbg extends Module with lib with RequireAsyncReset { RegEnable(io.dmi_reg_wdata(19, 15), 0.U, sbcs_wren) } // sbcs_misc_reg - val temp_sbcs_14_12 = withClockAndReset(sb_free_clk, rst_not) { + val temp_sbcs_14_12 = withClockAndReset(sb_free_clk, dbg_dm_rst_l) { RegEnable(sbcs_sberror_din(2, 0), 0.U, sbcs_sberror_wren) } // sbcs_error_reg sbcs_reg := Cat(1.U(3.W), 0.U(6.W), temp_sbcs_22, temp_sbcs_21, temp_sbcs_20, temp_sbcs_19_15, temp_sbcs_14_12, "h20".U(7.W), "b01111".U(5.W)) @@ -456,4 +454,8 @@ class dbg extends Module with lib with RequireAsyncReset { io.dbg_dma.dbg_ib.dbg_cmd_valid := io.dbg_dec.dbg_ib.dbg_cmd_valid io.dbg_dma.dbg_ib.dbg_cmd_write := io.dbg_dec.dbg_ib.dbg_cmd_write io.dbg_dma.dbg_ib.dbg_cmd_type := io.dbg_dec.dbg_ib.dbg_cmd_type -} \ No newline at end of file +} + +object dbg_main extends App { + println((new chisel3.stage.ChiselStage).emitVerilog(new dbg())) +} diff --git a/src/main/scala/dec/dec.scala b/src/main/scala/dec/dec.scala index 2856bb52..b4d0c6b7 100644 --- a/src/main/scala/dec/dec.scala +++ b/src/main/scala/dec/dec.scala @@ -302,4 +302,8 @@ class dec extends Module with param with RequireAsyncReset{ // debug command read data io.dec_dbg_rddata := decode.io.dec_i0_wdata_r -} \ No newline at end of file +} + +object dec_main extends App { + println((new chisel3.stage.ChiselStage).emitVerilog(new dec())) +} diff --git a/src/main/scala/dec/dec_tlu_ctl.scala b/src/main/scala/dec/dec_tlu_ctl.scala index 95f35604..d423c350 100644 --- a/src/main/scala/dec/dec_tlu_ctl.scala +++ b/src/main/scala/dec/dec_tlu_ctl.scala @@ -227,16 +227,16 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{ val trigger_hit_dmode_r_d1 =WireInit(UInt(1.W),0.U) val dcsr_single_step_done_f =WireInit(UInt(1.W),0.U) val debug_halt_req_d1 =WireInit(UInt(1.W),0.U) - val request_debug_mode_r_d1 =WireInit(UInt(1.W),0.U) - val request_debug_mode_done_f =WireInit(UInt(1.W),0.U) - val dcsr_single_step_running_f =WireInit(UInt(1.W),0.U) - val dec_tlu_flush_pause_r_d1 =WireInit(UInt(1.W),0.U) - val dbg_halt_req_held =WireInit(UInt(1.W),0.U) - val debug_halt_req_ns =WireInit(UInt(1.W),0.U) - val internal_dbg_halt_mode =WireInit(UInt(1.W),0.U) - val core_empty =WireInit(UInt(1.W),0.U) - val dbg_halt_req_final =WireInit(UInt(1.W),0.U) - val debug_brkpt_status_ns =WireInit(UInt(1.W),0.U) + val request_debug_mode_r_d1 =WireInit(UInt(1.W),0.U) + val request_debug_mode_done_f =WireInit(UInt(1.W),0.U) + val dcsr_single_step_running_f =WireInit(UInt(1.W),0.U) + val dec_tlu_flush_pause_r_d1 =WireInit(UInt(1.W),0.U) + val dbg_halt_req_held =WireInit(UInt(1.W),0.U) + val debug_halt_req_ns =WireInit(UInt(1.W),0.U) + val internal_dbg_halt_mode =WireInit(UInt(1.W),0.U) + val core_empty =WireInit(UInt(1.W),0.U) + val dbg_halt_req_final =WireInit(UInt(1.W),0.U) + val debug_brkpt_status_ns =WireInit(UInt(1.W),0.U) val mpc_debug_halt_ack_ns =WireInit(UInt(1.W),0.U) val mpc_debug_run_ack_ns =WireInit(UInt(1.W),0.U) val mpc_halt_state_ns =WireInit(UInt(1.W),0.U) @@ -329,9 +329,7 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{ io.dec_tlu_i0_kill_writeb_wb :=withClock(io.free_clk){RegNext(tlu_i0_kill_writeb_r,0.U)} val internal_dbg_halt_mode_f2 =withClock(io.free_clk){RegNext(internal_dbg_halt_mode_f,0.U)} io.tlu_mem.dec_tlu_force_halt :=withClock(io.free_clk){RegNext(force_halt,0.U)} - - - + io.dec_tlu_i0_kill_writeb_r :=tlu_i0_kill_writeb_r val reset_detect =withClock(io.free_clk){RegNext(1.U(1.W),0.U)} val reset_detected =withClock(io.free_clk){RegNext(reset_detect,0.U)} diff --git a/src/main/scala/dma_ctrl.scala b/src/main/scala/dma_ctrl.scala index 34c1c005..1b3f75cf 100644 --- a/src/main/scala/dma_ctrl.scala +++ b/src/main/scala/dma_ctrl.scala @@ -508,3 +508,7 @@ class dma_ctrl extends Module with lib with RequireAsyncReset { io.ifu_dma.dma_mem_ctl.dma_mem_write := io.lsu_dma.dma_lsc_ctl.dma_mem_write io.ifu_dma.dma_mem_ctl.dma_mem_tag := io.lsu_dma.dma_mem_tag } + +object dma extends App { + println((new chisel3.stage.ChiselStage).emitVerilog(new dma_ctrl())) +} diff --git a/src/main/scala/exu/exu.scala b/src/main/scala/exu/exu.scala index 788c2c12..73a47350 100644 --- a/src/main/scala/exu/exu.scala +++ b/src/main/scala/exu/exu.scala @@ -231,4 +231,8 @@ class exu extends Module with lib with RequireAsyncReset{ io.exu_bp.exu_mp_eghr := final_predpipe_mp(PREDPIPESIZE-1,BTB_ADDR_HI-BTB_ADDR_LO+BTB_BTAG_SIZE+1) // mp ghr for bht write io.exu_flush_path_final := Mux(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r.asBool, io.dec_exu.tlu_exu.dec_tlu_flush_path_r, i0_flush_path_d) io.dec_exu.tlu_exu.exu_npc_r := Mux(i0_pred_correct_upper_r===1.U, pred_correct_npc_r, i0_flush_path_upper_r) -} \ No newline at end of file +} + +object exu_main extends App { + println((new chisel3.stage.ChiselStage).emitVerilog(new exu())) +} diff --git a/src/main/scala/ifu/ifu.scala b/src/main/scala/ifu/ifu.scala index 50e381a2..230a8d2b 100644 --- a/src/main/scala/ifu/ifu.scala +++ b/src/main/scala/ifu/ifu.scala @@ -117,3 +117,7 @@ class ifu extends Module with lib with RequireAsyncReset { io.iccm_ready := mem_ctl.io.iccm_ready io.iccm_dma_sb_error := mem_ctl.io.iccm_dma_sb_error } + +object ifu_main extends App { + println((new chisel3.stage.ChiselStage).emitVerilog(new ifu())) +} diff --git a/src/main/scala/include/bundle.scala b/src/main/scala/include/bundle.scala index 9263291d..5e34bd84 100644 --- a/src/main/scala/include/bundle.scala +++ b/src/main/scala/include/bundle.scala @@ -74,14 +74,14 @@ class ahb_channel extends Bundle{ val in = new ahb_in val out = new ahb_out } -class axi_channels(val BUS_TAG :Int=1) extends Bundle with lib{ +class axi_channels(val BUS_TAG :Int=3) extends Bundle with lib{ val aw = Decoupled(new write_addr(BUS_TAG)) val w = Decoupled(new write_data()) val b = Flipped(Decoupled(new write_resp(BUS_TAG))) val ar = Decoupled(new read_addr(BUS_TAG)) val r = Flipped(Decoupled(new read_data(BUS_TAG))) } -class read_addr(val TAG : Int) extends Bundle with lib { // read_address +class read_addr(val TAG : Int=3) extends Bundle with lib { // read_address val id = UInt(TAG.W) val addr = UInt(32.W) val region = UInt(4.W) @@ -93,13 +93,13 @@ class read_addr(val TAG : Int) extends Bundle with lib { // read_address val prot = UInt(3.W) val qos = UInt(4.W) } -class read_data(val TAG : Int) extends Bundle with lib { // read_data +class read_data(val TAG : Int=3) extends Bundle with lib { // read_data val id = UInt(TAG.W) val data = UInt(64.W) val resp = UInt(2.W) val last = Bool() } -class write_addr(val TAG : Int) extends Bundle with lib { // write_address +class write_addr(val TAG : Int=3) extends Bundle with lib { // write_address val id = UInt(TAG.W) val addr = UInt(32.W) val region = UInt(4.W) diff --git a/src/main/scala/lib/param.scala b/src/main/scala/lib/param.scala index 79c7506c..0917162d 100644 --- a/src/main/scala/lib/param.scala +++ b/src/main/scala/lib/param.scala @@ -21,9 +21,9 @@ trait param { val BTB_INDEX3_HI = 0x19 val BTB_INDEX3_LO = 0x12 val BTB_SIZE = 0x200 - val BUILD_AHB_LITE = 0x1 - val BUILD_AXI4 = 0x0 - val BUILD_AXI_NATIVE = 0x0 + val BUILD_AHB_LITE = 0x0 + val BUILD_AXI4 = 0x1 + val BUILD_AXI_NATIVE = 0x1 val BUS_PRTY_DEFAULT = 0x3 val DATA_ACCESS_ADDR0 = 0x00000000 val DATA_ACCESS_ADDR1 = 0xC0000000 diff --git a/src/main/scala/lsu/lsu.scala b/src/main/scala/lsu/lsu.scala index 367287cc..d3494a4a 100644 --- a/src/main/scala/lsu/lsu.scala +++ b/src/main/scala/lsu/lsu.scala @@ -318,4 +318,7 @@ class lsu extends Module with RequireAsyncReset with param with lib { withClock(clkdomain.io.lsu_c2_r_clk){lsu_raw_fwd_hi_r := RegNext(lsu_raw_fwd_hi_m,0.U)} withClock(clkdomain.io.lsu_c2_r_clk){lsu_raw_fwd_lo_r := RegNext(lsu_raw_fwd_lo_m,0.U)} +} +object lsu_top extends App { + println((new chisel3.stage.ChiselStage).emitVerilog(new lsu())) } \ No newline at end of file diff --git a/src/main/scala/lsu/lsu_bus_buffer.scala b/src/main/scala/lsu/lsu_bus_buffer.scala index 821260cc..38741796 100644 --- a/src/main/scala/lsu/lsu_bus_buffer.scala +++ b/src/main/scala/lsu/lsu_bus_buffer.scala @@ -5,6 +5,7 @@ import lib._ import include._ import chisel3.experimental.{ChiselEnum, chiselName} import chisel3.util.ImplicitConversions.intToUInt +import ifu._ @chiselName class lsu_bus_buffer extends Module with RequireAsyncReset with lib { @@ -182,6 +183,7 @@ class lsu_bus_buffer extends Module with RequireAsyncReset with lib { (io.lsu_addr_r(1,0)===1.U)->Cat(0.U(3.W), ldst_byteen_r(3)), (io.lsu_addr_r(1,0)===2.U)->Cat(0.U(2.W), ldst_byteen_r(3,2)), (io.lsu_addr_r(1,0)===3.U)->Cat(0.U(1.W), ldst_byteen_r(3,1)))) + val ldst_byteen_lo_r = Mux1H(Seq((io.lsu_addr_r(1,0)===0.U)->ldst_byteen_r, (io.lsu_addr_r(1,0)===1.U)->Cat(ldst_byteen_r(2,0), 0.U), (io.lsu_addr_r(1,0)===2.U)->Cat(ldst_byteen_r(1,0), 0.U(2.W)), @@ -295,7 +297,6 @@ class lsu_bus_buffer extends Module with RequireAsyncReset with lib { val obuf_merge_en = WireInit(Bool(), false.B) val obuf_merge_in = obuf_merge_en val obuf_tag0_in = Mux(ibuf_buf_byp, WrPtr0_r, CmdPtr0) - //val Cmdptr1 = WireInit(UInt(DEPTH_LOG2.W), 0.U) val obuf_tag1_in = Mux(ibuf_buf_byp, WrPtr1_r, CmdPtr1) val obuf_cmd_done = WireInit(Bool(), false.B) @@ -616,3 +617,7 @@ class lsu_bus_buffer extends Module with RequireAsyncReset with lib { io.lsu_busreq_r := withClock(io.lsu_c2_r_clk){RegNext(io.lsu_busreq_m & !io.flush_r & !io.ld_full_hit_m, false.B)} lsu_nonblock_load_valid_r := withClock(io.lsu_c2_r_clk){RegNext(io.dctl_busbuff.lsu_nonblock_load_valid_m, false.B)} } + +object bus_buffer extends App { + println((new chisel3.stage.ChiselStage).emitVerilog(new lsu_bus_buffer())) +} \ No newline at end of file diff --git a/src/main/scala/lsu/lsu_bus_intf.scala b/src/main/scala/lsu/lsu_bus_intf.scala index 81bc14bd..12692f41 100644 --- a/src/main/scala/lsu/lsu_bus_intf.scala +++ b/src/main/scala/lsu/lsu_bus_intf.scala @@ -3,7 +3,6 @@ import chisel3._ import chisel3.util._ import lib._ import include._ -import ifu._ class lsu_bus_intf extends Module with RequireAsyncReset with lib { val io = IO (new Bundle { diff --git a/src/main/scala/pic_ctrl.scala b/src/main/scala/pic_ctrl.scala index 82803859..fbf1fda4 100644 --- a/src/main/scala/pic_ctrl.scala +++ b/src/main/scala/pic_ctrl.scala @@ -405,3 +405,7 @@ class pic_ctrl extends Module with RequireAsyncReset with lib { } } + +object pic_gen extends App { + println((new chisel3.stage.ChiselStage).emitVerilog(new pic_ctrl())) +} diff --git a/src/main/scala/quasar.scala b/src/main/scala/quasar.scala index b2becd82..97404c7d 100644 --- a/src/main/scala/quasar.scala +++ b/src/main/scala/quasar.scala @@ -83,9 +83,6 @@ class quasar extends Module with RequireAsyncReset with lib { val active_state = (!dec.io.dec_pause_state_cg | dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r) | dec.io.dec_tlu_misc_clk_override val free_clk = rvclkhdr(clock, true.B, io.scan_mode) val active_clk = rvclkhdr(clock, active_state.asBool, io.scan_mode) - val core_dbg_cmd_done = dma_ctrl.io.dma_dbg_cmd_done | dec.io.dec_dbg_cmd_done - val core_dbg_cmd_fail = dma_ctrl.io.dma_dbg_cmd_fail | dec.io.dec_dbg_cmd_fail - val core_dbg_rddata = Mux(dma_ctrl.io.dma_dbg_cmd_done, dma_ctrl.io.dma_dbg_rddata, dec.io.dec_dbg_rddata) // Lets start with IFU ifu.io.ifu_dec <> dec.io.ifu_dec @@ -106,7 +103,7 @@ class quasar extends Module with RequireAsyncReset with lib { ifu.io.exu_ifu.exu_bp.exu_i0_br_fghr_r := exu.io.exu_bp.exu_i0_br_fghr_r ifu.io.exu_ifu.exu_bp.exu_i0_br_index_r := exu.io.dec_exu.tlu_exu.exu_i0_br_index_r ifu.io.dec_tlu_flush_lower_wb := dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt := dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt <> dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt // Lets start with Dec dec.reset := io.core_rst_l @@ -278,10 +275,10 @@ class quasar extends Module with RequireAsyncReset with lib { io.lsu_axi <> 0.U.asTypeOf(io.lsu_axi) } else{ - io.lsu_ahb <> 0.U.asTypeOf(io.lsu_ahb) - io.ifu_ahb <> 0.U.asTypeOf(io.ifu_ahb) - io.sb_ahb <> 0.U.asTypeOf(io.sb_ahb) - io.dma_ahb <> 0.U.asTypeOf(io.dma_ahb) + io.lsu_ahb <> 0.U.asTypeOf(io.lsu_ahb) + io.ifu_ahb <> 0.U.asTypeOf(io.ifu_ahb) + io.sb_ahb <> 0.U.asTypeOf(io.sb_ahb) + io.dma_ahb <> 0.U.asTypeOf(io.dma_ahb) dma_ctrl.io.dma_axi <> io.dma_axi dbg.io.sb_axi <> io.sb_axi ifu.io.ifu <> io.ifu_axi diff --git a/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar b/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar index ce8024770e083f75e4f167dc9acdb15d0f42453f..23a66bd79c4d19c71a1b162df023d19fc68dab07 100644 GIT binary patch delta 124756 zcmb@u1yo$i)-4>|3DCH^y9N*L?h@QBxI^O}+}+(FG@jrZ+#$gsKtg~7O(1{M+;i@^ z=X~*O=v+7N}-TIb2nyLZ}EcP=*M8s!uAqh!nOh94eAa+z~ zuRcNV;HaGgG~!(B>$yO)LQ%8bdmPxvm_h?tqfaMkhXiUi{kZ%$ZIu&@(-An?)=TnJ zByX5;9gFbd8}~w1S!B1gYhW4tW3!ums%gCeZC*NF=+0*sRk<^^cP?PE*XR4@Rdyts6d4WpuNt_~pZ{RNB@0V) zw#OUz^MVv9C^E~2xOx1oCmiUfp7@~2VRpO|GG>xc2r@EE z2ys9L=_qgEAJ2h;I#AnTA*GIc6qP7Q3EWN}76`8W4{Nc&)>?Xduz^3uj;6LwtmY1; zZf=fhADyt&F!EO|^>A^KL&)FOiQ7UOxjU-I!2_GI?YI|kdAV(U)t-NG`3Ud%!PVwH z-I-(z#g)Umy;QGn<9PLh##3vL>gd{d5)z2wZK$*Lxe64$`ZSKHQI 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\ No newline at end of file diff --git a/target/streams/compile/_global/_global/dependencyClasspathFiles/previous b/target/streams/compile/_global/_global/dependencyClasspathFiles/previous index db3d244f..3fc0b0f5 100644 --- a/target/streams/compile/_global/_global/dependencyClasspathFiles/previous +++ b/target/streams/compile/_global/_global/dependencyClasspathFiles/previous @@ -1 +1 @@ -["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar","/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar"]] \ No newline at end of file +["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/abdulhameed.akram/.sbt/boot/scala-2.12.10/lib/scala-library.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar","/home/abdulhameed.akram/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar"]] \ No newline at end of file diff --git a/target/streams/compile/_global/_global/discoveredMainClasses/data b/target/streams/compile/_global/_global/discoveredMainClasses/data index 5249feb6..a109e9d3 100644 --- a/target/streams/compile/_global/_global/discoveredMainClasses/data +++ b/target/streams/compile/_global/_global/discoveredMainClasses/data @@ -1 +1 @@ -["QUASAR_Wrp"] \ No newline at end of file +["QUASAR","QUASAR_Wrp","dbg.dbg_main","dec.dec_main","dma","exu.exu_main","ifu.ifu_main","lib.axi4","lsu.lsu_main","pic_gen"] \ No newline at end of file diff --git a/target/streams/compile/compile/_global/streams/out b/target/streams/compile/compile/_global/streams/out index 0390d08a..918ab064 100644 --- a/target/streams/compile/compile/_global/streams/out +++ b/target/streams/compile/compile/_global/streams/out @@ -1,6 +1,10 @@ -[warn] /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/lib.scala:25:5: match may not be exhaustive. +[warn] /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lib/lib.scala:25:5: match may not be exhaustive. [warn] It would fail on the following inputs: (0, _), (1, _), (??, _), (_, 0), (_, 1), (_, ??), (_, _) [warn]  (ICACHE_WAYPACK, ICACHE_ECC) match{ [warn]  ^ -[warn] there were 3745 feature warnings; re-run with -feature for details -[warn] two warnings found +[warn] /home/abdulhameed.akram/Videos/Quasar/src/main/scala/quasar.scala:292:8: Generated class QUASAR differs only in case from quasar. +[warn]  Such classes will overwrite one another on case-insensitive filesystems. +[warn] object QUASAR extends App { +[warn]  ^ +[warn] there were 3746 feature warnings; re-run with -feature for details +[warn] three warnings found diff --git a/target/streams/compile/compileIncSetup/_global/streams/inc_compile_2.12.zip b/target/streams/compile/compileIncSetup/_global/streams/inc_compile_2.12.zip index 594912b2edd57fb58a9b6d0b11c96979d67545f2..1596eabba1d52f9165a4d66f571b4ad9cd3899a8 100644 GIT binary patch delta 314923 zcmV)LK)Ju&r4z!;6Ae&H0|XQR2nYxONP>@%4I+OFkYw3a7)W&w(&&wTQyOWc*67zN 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/home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar -Xplugin:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalamacros/paradise_2.12.10/2.1.0/paradise_2.12.10-2.1.0.jar -Xsource:2.11.0 /home/waleedbinehsan/Desktop/Quasar/src/main/scala/mem.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/quasar.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dma_ctrl.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/quasar_wrapper.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/pic_ctrl.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_ifc_ctl.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_aln_ctl.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_bp_ctl.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_mem_ctl.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_compress_ctl.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_bus_intf.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_trigger.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_ecc.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_stbuf.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_dccm_ctl.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_lsc_ctl.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_bus_buffer.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_addrcheck.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_clkdomain.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu_mul_ctl.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu_div_ctl.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu_alu_ctl.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dbg/dbg.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/param.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/axi4_to_ahb.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/lib.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/ahb_to_axi4.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dmi/dmi_wrapper.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/include/bundle.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_trigger.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_decode_ctl.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_ib_ctl.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_dec_ctl.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_tlu_ctl.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_gpr_ctl.scala +scalac -bootclasspath /home/abdulhameed.akram/.sbt/boot/scala-2.12.10/lib/scala-library.jar -classpath /home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/abdulhameed.akram/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar -Xplugin:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalamacros/paradise_2.12.10/2.1.0/paradise_2.12.10-2.1.0.jar -Xsource:2.11.0 /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lib/param.scala diff --git a/target/streams/compile/compileIncremental/_global/streams/out b/target/streams/compile/compileIncremental/_global/streams/out index 1113fefa..7ef19cc0 100644 --- a/target/streams/compile/compileIncremental/_global/streams/out +++ b/target/streams/compile/compileIncremental/_global/streams/out @@ -1,1091 +1 @@ -[debug]  -[debug] Initial source changes:  -[debug]  removed:Set(/home/waleedbinehsan/Desktop/Quasar/src/main/scala/snapshot/el2_param.scala) -[debug]  added: Set() -[debug]  modified: Set(/home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_ifc_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/pic_ctrl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dbg/dbg.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/lib.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/include/bundle.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/ahb_to_axi4.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dma_ctrl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/param.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu_alu_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/axi4_to_ahb.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_aln_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_decode_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_tlu_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_bus_intf.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/quasar.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_clkdomain.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_mem_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/quasar_wrapper.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_bus_buffer.scala) -[debug] Invalidated products: Set(/home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dma_mem_ctl.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/ifu/ifu_bp_ctl$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dma_dccm_ctl.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dbg_ib.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/lib$rvdffe$.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu_ecc.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dec_ifc.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/mem/Mem_bundle.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu_lsc_ctl$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dbg_dctl.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_decode_ctl.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/csr_tlu.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu_stbuf$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dbg/state_t.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/aln_ib.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/tlu_busbuff.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/pic_ctrl$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/rets_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/QUASAR_Wrp$delayedInit$body.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dec_mem_ctrl.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu_dccm_ctl$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dec_tlu_csr_pkt.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_decode_ctl$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_trigger.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/trigger_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/ifu_dma.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dmi/dmi_wrapper_module$$anon$2.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/ifu/ifu_compress_ctl.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dec_div.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dctl_busbuff.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/quasar_wrapper$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/pic_ctrl.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/lsu_dec.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/lib$rvecc_encode.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_tlu_ctl_IO.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dbg/dbg$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dec_dbg.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/CSRs.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/lsu_dma.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/trace_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/exu/exu_alu_ctl.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dec_alu.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_ib_ctl.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/ifu/ifu_aln_ctl.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/QUASAR_Wrp$.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dec_dma.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/trap_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/lib$rvclkhdr.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu_clkdomain.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/param.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/exu_bp.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_gpr_ctl.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/tlu_dma.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/lib$rvsyncss$.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/lsu_pic.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dctl_dma.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/ifu_dec.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dccm_ext_in_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu_stbuf.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/predict_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/read_addr.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/ib_exu.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/lib$rvecc_encode_64$$anon$2.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/ifu/ifu_bp_ctl.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu_dccm_ctl.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/lib$gated_latch.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu_trigger.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dest_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dma_ctrl.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/lib$rvclkhdr$.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/lib$rvecc_encode$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dec_bp.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_trigger$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/lib$rvecc_encode_64.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/read_data$.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/ifu/ifu_ifc_ctl.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/exu/exu_alu_ctl$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_dec_ctl$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu_bus_buffer.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/ic_mem.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/ahb_to_axi4.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/inst_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/exu/exu_mul_ctl$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dmi/dmi_wrapper$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_dec_ctl.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dec_pic.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_tlu_ctl.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/exu_ifu.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/lsu_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dec_exu.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/inst_pkt_t$.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/axi_channels.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/ifu/ifu.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dbg/dbg.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dbg/sb_state_t.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/ic_tag_ext_in_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/CSR_IO.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/br_tlu_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/snapshot/pt$.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dmi/dmi_wrapper.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/gpr_exu.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dbg/dbg_dma.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/mem/quasar$.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_decode_csr_read.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/lsu_exu.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dma_ifc.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/lib.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/write_addr$.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/iccm_mem.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/lsu_tlu.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/mem/blackbox_mem.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu_ecc$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/ifu/ifu_aln_ctl$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/ifu/ifu_ifc_ctl$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/quasar_bundle.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dma_ctrl$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dmi/dmi_wrapper_module.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/lib$rvclkhdr$$anon$4.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_timer_ctl_IO.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/mem/mem_lsu.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/quasar_wrapper.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/ifu/ifu$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/exu/exu_div_ctl$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dec_aln.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_gpr_ctl_IO.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/CSR_VAL.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/ccm_ext_in_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/ifu/ifu_compress_ctl$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/exu/exu_div_ctl.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_timer_ctl.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/mem/quasar$mem.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/alu_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/exu/exu_mul_ctl.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dec_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/axi4_to_ahb.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/div_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/read_data.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/mul_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/axi4_to_ahb_IO.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/Config.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu_addrcheck$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/aln_dec.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/snapshot/pt.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_ib_ctl_IO.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/write_addr.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/lib$gated_latch$$anon$3.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu_bus_intf$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/axi_channels$.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/exu/exu$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/mem/quasar.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/ic_data_ext_in_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/ifu/ifu_mem_ctl.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/lsu_error_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/quasar.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/write_resp.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu_trigger$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu_lsc_ctl.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/ahb_to_axi4$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/br_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_decode_csr_read_IO.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu_bus_intf.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/class_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dbg/sb_state_t$.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/decode_exu.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/exu/exu.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu_bus_buffer$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu_addrcheck.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/cache_debug_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/tlu_exu.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/load_cam_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/read_addr$.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_IO.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dma_lsc_ctl.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/write_resp$.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dbg/state_t$.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu_clkdomain$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/write_data.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/reg_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/QUASAR_Wrp.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/ifu/mem_ctl_io.class) -[debug] External API changes: API Changes: Set() -[debug] Modified binary dependencies: Set() -[debug] Initial directly invalidated classes: Set(include.class_pkt_t, lsu.lsu_clkdomain, include.dbg_ib, include.dec_alu, dec.dec_decode_ctl, include.lsu_dma, lib.axi4_to_ahb_IO, lib.lib.gated_latch, include.exu_bp, include.dec_aln, lib.param, ifu.ifu, include.aln_ib, include.dctl_dma, include.div_pkt_t, dec.dec_tlu_ctl_IO, include.gpr_exu, include.aln_dec, include.lsu_exu, dbg.state_t, include.lsu_tlu, include.dccm_ext_in_pkt_t, include.ccm_ext_in_pkt_t, include.inst_pkt_t, lsu.lsu, dec.dec_tlu_ctl, dec.dec_decode_csr_read_IO, lib.ahb_to_axi4, lib.lib.rvecc_encode, lib.axi4_to_ahb, quasar, include.tlu_dma, include.lsu_pic, include.dma_lsc_ctl, include.rets_pkt_t, lib.lib.rvecc_encode_64, include.mul_pkt_t, dec.csr_tlu, include.reg_pkt_t, include.trap_pkt_t, pic_ctrl, include.dma_mem_ctl, include.write_data, include.ic_data_ext_in_pkt_t, dec.CSRs, exu.exu_alu_ctl, lib.lib.rvsyncss, include.tlu_exu, include.ib_exu, include.iccm_mem, include.lsu_dec, QUASAR_Wrp, quasar_bundle, include.predict_pkt_t, include.dec_ifc, include.write_addr, include.ifu_dma, include.tlu_busbuff, ifu.mem_ctl_io, include.lsu_error_pkt_t, lib.Config, lsu.lsu_bus_buffer, quasar_wrapper, include.trigger_pkt_t, include.write_resp, dec.CSR_IO, include.alu_pkt_t, include.trace_pkt_t, include.br_tlu_pkt_t, lib.lib.rvclkhdr, dec.dec_timer_ctl, include.dest_pkt_t, include.dec_exu, lib.lib.rvdffe, include.read_data, ifu.ifu_aln_ctl, dbg.dbg, include.dma_dccm_ctl, include.ic_mem, lsu.lsu_bus_intf, include.br_pkt_t, dec.CSR_VAL, include.cache_debug_pkt_t, include.dec_pic, include.exu_ifu, dbg.sb_state_t, include.ic_tag_ext_in_pkt_t, include.dctl_busbuff, include.read_addr, include.axi_channels, dec.dec_decode_csr_read, include.dec_mem_ctrl, ifu.ifu_mem_ctl, ifu.ifu_ifc_ctl, include.lsu_pkt_t, include.dec_div, include.dec_dma, include.decode_exu, include.dec_pkt_t, dec.dec_timer_ctl_IO, include.dec_dbg, snapshot.pt, include.load_cam_pkt_t, include.dma_ifc, dbg.dbg_dma, include.ifu_dec, lib.lib, include.dec_tlu_csr_pkt, dma_ctrl, include.dec_bp, include.dbg_dctl) -[debug]  -[debug] Sources indirectly invalidated by: -[debug]  product: Set(/home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_ifc_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/pic_ctrl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dbg/dbg.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/lib.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu_div_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_gpr_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/include/bundle.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_dec_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/ahb_to_axi4.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_stbuf.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_dccm_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu_mul_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/mem.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_bp_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dma_ctrl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/param.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu_alu_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_ib_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/axi4_to_ahb.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_ecc.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_aln_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_decode_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_trigger.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_tlu_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_compress_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dmi/dmi_wrapper.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_addrcheck.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_bus_intf.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_trigger.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/quasar.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_clkdomain.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_lsc_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_mem_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/snapshot/el2_param.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/quasar_wrapper.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_bus_buffer.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu.scala) -[debug]  binary dep: Set() -[debug]  external source: Set() -[debug] All initially invalidated classes: Set(include.class_pkt_t, lsu.lsu_clkdomain, include.dbg_ib, include.dec_alu, dec.dec_decode_ctl, include.lsu_dma, lib.axi4_to_ahb_IO, lib.lib.gated_latch, include.exu_bp, include.dec_aln, lib.param, ifu.ifu, include.aln_ib, include.dctl_dma, include.div_pkt_t, dec.dec_tlu_ctl_IO, include.gpr_exu, include.aln_dec, include.lsu_exu, dbg.state_t, include.lsu_tlu, include.dccm_ext_in_pkt_t, include.ccm_ext_in_pkt_t, include.inst_pkt_t, lsu.lsu, dec.dec_tlu_ctl, dec.dec_decode_csr_read_IO, lib.ahb_to_axi4, lib.lib.rvecc_encode, lib.axi4_to_ahb, quasar, include.tlu_dma, include.lsu_pic, include.dma_lsc_ctl, include.rets_pkt_t, lib.lib.rvecc_encode_64, include.mul_pkt_t, dec.csr_tlu, include.reg_pkt_t, include.trap_pkt_t, pic_ctrl, include.dma_mem_ctl, include.write_data, include.ic_data_ext_in_pkt_t, dec.CSRs, exu.exu_alu_ctl, lib.lib.rvsyncss, include.tlu_exu, include.ib_exu, include.iccm_mem, include.lsu_dec, QUASAR_Wrp, quasar_bundle, include.predict_pkt_t, include.dec_ifc, include.write_addr, include.ifu_dma, include.tlu_busbuff, ifu.mem_ctl_io, include.lsu_error_pkt_t, lib.Config, lsu.lsu_bus_buffer, quasar_wrapper, include.trigger_pkt_t, include.write_resp, dec.CSR_IO, include.alu_pkt_t, include.trace_pkt_t, include.br_tlu_pkt_t, lib.lib.rvclkhdr, dec.dec_timer_ctl, include.dest_pkt_t, include.dec_exu, lib.lib.rvdffe, include.read_data, ifu.ifu_aln_ctl, dbg.dbg, include.dma_dccm_ctl, include.ic_mem, lsu.lsu_bus_intf, include.br_pkt_t, dec.CSR_VAL, include.cache_debug_pkt_t, include.dec_pic, include.exu_ifu, dbg.sb_state_t, include.ic_tag_ext_in_pkt_t, include.dctl_busbuff, include.read_addr, include.axi_channels, dec.dec_decode_csr_read, include.dec_mem_ctrl, ifu.ifu_mem_ctl, ifu.ifu_ifc_ctl, include.lsu_pkt_t, include.dec_div, include.dec_dma, include.decode_exu, include.dec_pkt_t, dec.dec_timer_ctl_IO, include.dec_dbg, snapshot.pt, include.load_cam_pkt_t, include.dma_ifc, dbg.dbg_dma, include.ifu_dec, lib.lib, include.dec_tlu_csr_pkt, dma_ctrl, include.dec_bp, include.dbg_dctl) -[debug] All initially invalidated sources:Set(/home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_ifc_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/pic_ctrl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dbg/dbg.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/lib.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu_div_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_gpr_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/include/bundle.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_dec_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/ahb_to_axi4.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_stbuf.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_dccm_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu_mul_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/mem.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_bp_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dma_ctrl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/param.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu_alu_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_ib_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/axi4_to_ahb.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_ecc.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_aln_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_decode_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_trigger.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_tlu_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_compress_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dmi/dmi_wrapper.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_addrcheck.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_bus_intf.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_trigger.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/quasar.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_clkdomain.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_lsc_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_mem_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/snapshot/el2_param.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/quasar_wrapper.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_bus_buffer.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu.scala) -[debug] Initial set of included nodes: include.class_pkt_t, lsu.lsu_clkdomain, include.dbg_ib, include.dec_alu, dec.dec_decode_ctl, include.lsu_dma, lib.axi4_to_ahb_IO, lib.lib.gated_latch, include.exu_bp, include.dec_aln, lib.param, ifu.ifu, include.aln_ib, include.dctl_dma, include.div_pkt_t, dec.dec_tlu_ctl_IO, include.gpr_exu, include.aln_dec, include.lsu_exu, dbg.state_t, include.lsu_tlu, include.dccm_ext_in_pkt_t, include.ccm_ext_in_pkt_t, include.inst_pkt_t, lsu.lsu, dec.dec_tlu_ctl, dec.dec_decode_csr_read_IO, lib.ahb_to_axi4, lib.lib.rvecc_encode, lib.axi4_to_ahb, quasar, include.tlu_dma, include.lsu_pic, include.dma_lsc_ctl, include.rets_pkt_t, lib.lib.rvecc_encode_64, include.mul_pkt_t, dec.csr_tlu, include.reg_pkt_t, include.trap_pkt_t, pic_ctrl, include.dma_mem_ctl, include.write_data, include.ic_data_ext_in_pkt_t, dec.CSRs, exu.exu_alu_ctl, lib.lib.rvsyncss, include.tlu_exu, include.ib_exu, include.iccm_mem, include.lsu_dec, QUASAR_Wrp, quasar_bundle, include.predict_pkt_t, include.dec_ifc, include.write_addr, include.ifu_dma, include.tlu_busbuff, ifu.mem_ctl_io, include.lsu_error_pkt_t, lib.Config, lsu.lsu_bus_buffer, quasar_wrapper, include.trigger_pkt_t, include.write_resp, dec.CSR_IO, include.alu_pkt_t, include.trace_pkt_t, include.br_tlu_pkt_t, lib.lib.rvclkhdr, dec.dec_timer_ctl, include.dest_pkt_t, include.dec_exu, lib.lib.rvdffe, include.read_data, ifu.ifu_aln_ctl, dbg.dbg, include.dma_dccm_ctl, include.ic_mem, lsu.lsu_bus_intf, include.br_pkt_t, dec.CSR_VAL, include.cache_debug_pkt_t, include.dec_pic, include.exu_ifu, dbg.sb_state_t, include.ic_tag_ext_in_pkt_t, include.dctl_busbuff, include.read_addr, include.axi_channels, dec.dec_decode_csr_read, include.dec_mem_ctrl, ifu.ifu_mem_ctl, ifu.ifu_ifc_ctl, include.lsu_pkt_t, include.dec_div, include.dec_dma, include.decode_exu, include.dec_pkt_t, dec.dec_timer_ctl_IO, include.dec_dbg, snapshot.pt, include.load_cam_pkt_t, include.dma_ifc, dbg.dbg_dma, include.ifu_dec, lib.lib, include.dec_tlu_csr_pkt, dma_ctrl, include.dec_bp, include.dbg_dctl -[debug] Including dec.dec by lib.param -[debug] Including dec.dec_ib_ctl_IO by lib.param -[debug] Including lsu.lsu by lib.param -[debug] Including dec.dec_ib_ctl by lib.param -[debug] Including lib.lib by lib.param -[debug] Including exu.exu by lib.lib -[debug] Including lsu.lsu_trigger by lib.lib -[debug] Including dec.dec_gpr_ctl by lib.lib -[debug] Including lsu.lsu_addrcheck by lib.lib -[debug] Including mem.quasar by lib.lib -[debug] Including ifu.ifu by lib.lib -[debug] Including include.aln_ib by lib.lib -[debug] Including dec.dec_tlu_ctl_IO by lib.lib -[debug] Including exu.exu_div_ctl by lib.lib -[debug] Including dec.dec_tlu_ctl by lib.lib -[debug] Including lib.ahb_to_axi4 by lib.lib -[debug] Including lib.axi4_to_ahb by lib.lib -[debug] Including quasar by lib.lib -[debug] Including dec.csr_tlu by lib.lib -[debug] Including lsu.lsu_lsc_ctl by lib.lib -[debug] Including pic_ctrl by lib.lib -[debug] Including include.write_data by lib.lib -[debug] Including exu.exu_alu_ctl by lib.lib -[debug] Including include.tlu_exu by lib.lib -[debug] Including dec.dec_IO by lib.lib -[debug] Including include.iccm_mem by lib.lib -[debug] Including quasar_bundle by lib.lib -[debug] Including lsu.lsu_ecc by lib.lib -[debug] Including mem.blackbox_mem by lib.lib -[debug] Including include.write_addr by lib.lib -[debug] Including ifu.mem_ctl_io by lib.lib -[debug] Including lsu.lsu_bus_buffer by lib.lib -[debug] Including quasar_wrapper by lib.lib -[debug] Including include.write_resp by lib.lib -[debug] Including dec.CSR_IO by lib.lib -[debug] Including dec.dec_timer_ctl by lib.lib -[debug] Including include.dec_exu by lib.lib -[debug] Including include.read_data by lib.lib -[debug] Including ifu.ifu_aln_ctl by lib.lib -[debug] Including dbg.dbg by lib.lib -[debug] Including include.ic_mem by lib.lib -[debug] Including lsu.lsu_bus_intf by lib.lib -[debug] Including exu.exu_mul_ctl by lib.lib -[debug] Including dec.dec_trigger by lib.lib -[debug] Including lsu.lsu_dccm_ctl by lib.lib -[debug] Including ifu.ifu_compress_ctl by lib.lib -[debug] Including ifu.ifu_bp_ctl by lib.lib -[debug] Including mem.Mem_bundle by lib.lib -[debug] Including include.dctl_busbuff by lib.lib -[debug] Including include.read_addr by lib.lib -[debug] Including include.axi_channels by lib.lib -[debug] Including dec.dec_dec_ctl by lib.lib -[debug] Including lsu.lsu_stbuf by lib.lib -[debug] Including mem.mem_lsu by lib.lib -[debug] Including include.dec_mem_ctrl by lib.lib -[debug] Including ifu.ifu_mem_ctl by lib.lib -[debug] Including ifu.ifu_ifc_ctl by lib.lib -[debug] Including include.decode_exu by lib.lib -[debug] Including dma_ctrl by lib.lib -[debug] Recompiling all sources: number of invalidated sources > 50.0% of all sources -[info] Compiling 39 Scala sources to /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes ... -[debug] Getting org.scala-sbt:compiler-bridge_2.12:1.3.5:compile for Scala 2.12.10 -[debug] Getting org.scala-sbt:compiler-bridge_2.12:1.3.5:compile for Scala 2.12.10 -[debug] [zinc] Running cached compiler 1544a576 for Scala compiler version 2.12.10 -[debug] [zinc] The Scala compiler is invoked with: -[debug]  -Xsource:2.11 -[debug]  -Xplugin:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalamacros/paradise_2.12.10/2.1.0/paradise_2.12.10-2.1.0.jar -[debug]  -bootclasspath -[debug]  /home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar -[debug]  -classpath -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar -[debug] Scala compilation took 42.644386776 s -[debug] Done compiling. -[debug] Invalidating (transitively) by inheritance from exu.exu_alu_ctl... -[debug] Initial set of included nodes: exu.exu_alu_ctl -[debug] Invalidated by transitive inheritance dependency: Set(exu.exu_alu_ctl) -[debug] None of the modified names appears in source file of exu.exu. This dependency is not being considered for invalidation. -[debug] Change NamesChange(exu.exu_alu_ctl,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]))) invalidates 1 classes due to The exu.exu_alu_ctl has the following regular definitions changed: -[debug]  UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]). -[debug]  > by transitive inheritance: Set(exu.exu_alu_ctl) -[debug]  >  -[debug]  >  -[debug]   -[debug] Invalidating (transitively) by inheritance from include.write_resp... -[debug] Initial set of included nodes: include.write_resp -[debug] Invalidated by transitive inheritance dependency: Set(include.write_resp) -[debug] The following modified names cause invalidation of dbg.dbg: Set(UsedName(write_resp,[Default])) -[debug] The following modified names cause invalidation of lsu.lsu_bus_buffer: Set(UsedName(asInstanceOf,[Default]), UsedName(==,[Default]), UsedName(write_resp,[Default]), UsedName(isInstanceOf,[Default])) -[debug] The following modified names cause invalidation of lib.axi4_to_ahb: Set(UsedName(asInstanceOf,[Default]), UsedName(==,[Default]), UsedName(write_resp,[Default]), UsedName(isInstanceOf,[Default])) -[debug] The following modified names cause invalidation of dma_ctrl: Set(UsedName(ne,[Default]), UsedName(write_resp,[Default])) -[debug] Change NamesChange(include.write_resp,ModifiedNames(changes = UsedName(notify,[Default]), UsedName(notifyAll,[Default]), UsedName(asInstanceOf,[Default]), UsedName(toString,[Default]), UsedName(finalize,[Default]), UsedName(!=,[Default]), UsedName(synchronized,[Default]), UsedName(wait,[Default]), UsedName(##,[Default]), UsedName(ne,[Default]), UsedName(equals,[Default]), UsedName(bridge_gen,[Default]), UsedName(==,[Default]), UsedName(include;write_resp;init;,[Default]), UsedName($default$1,[Default]), UsedName(write_resp,[Default]), UsedName(isInstanceOf,[Default]), UsedName($isInstanceOf,[Default]), UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(hashCode,[Default]), UsedName(eq,[Default]), UsedName(clone,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]))) invalidates 5 classes due to The include.write_resp has the following regular definitions changed: -[debug]  UsedName(notify,[Default]), UsedName(notifyAll,[Default]), UsedName(asInstanceOf,[Default]), UsedName(toString,[Default]), UsedName(finalize,[Default]), UsedName(!=,[Default]), UsedName(synchronized,[Default]), UsedName(wait,[Default]), UsedName(##,[Default]), UsedName(ne,[Default]), UsedName(equals,[Default]), UsedName(bridge_gen,[Default]), UsedName(==,[Default]), UsedName(include;write_resp;init;,[Default]), UsedName($default$1,[Default]), UsedName(write_resp,[Default]), UsedName(isInstanceOf,[Default]), UsedName($isInstanceOf,[Default]), UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(hashCode,[Default]), UsedName(eq,[Default]), UsedName(clone,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]). -[debug]  > by transitive inheritance: Set(include.write_resp) -[debug]  >  -[debug]  > by member reference: Set(dbg.dbg, lsu.lsu_bus_buffer, lib.axi4_to_ahb, dma_ctrl) -[debug]   -[debug] Invalidating (transitively) by inheritance from ifu.ifu_mem_ctl... -[debug] Initial set of included nodes: ifu.ifu_mem_ctl -[debug] Invalidated by transitive inheritance dependency: Set(ifu.ifu_mem_ctl) -[debug] None of the modified names appears in source file of ifu.ifu. This dependency is not being considered for invalidation. -[debug] Change NamesChange(ifu.ifu_mem_ctl,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]))) invalidates 1 classes due to The ifu.ifu_mem_ctl has the following regular definitions changed: -[debug]  UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]). -[debug]  > by transitive inheritance: Set(ifu.ifu_mem_ctl) -[debug]  >  -[debug]  >  -[debug]   -[debug] Invalidating (transitively) by inheritance from dec.dec_decode_ctl... -[debug] Initial set of included nodes: dec.dec_decode_ctl -[debug] Invalidated by transitive inheritance dependency: Set(dec.dec_decode_ctl) -[debug] None of the modified names appears in source file of dec.dec. This dependency is not being considered for invalidation. -[debug] Change NamesChange(dec.dec_decode_ctl,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]))) invalidates 1 classes due to The dec.dec_decode_ctl has the following regular definitions changed: -[debug]  UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]). -[debug]  > by transitive inheritance: Set(dec.dec_decode_ctl) -[debug]  >  -[debug]  >  -[debug]   -[debug] Invalidating (transitively) by inheritance from include.ahb_channel... -[debug] Initial set of included nodes: include.ahb_channel -[debug] Invalidated by transitive inheritance dependency: Set(include.ahb_channel) -[debug] The following member ref dependencies of include.ahb_channel are invalidated: -[debug]  lib.ahb_to_axi4 -[debug]  lib.axi4_to_ahb -[debug]  lib.axi4_to_ahb_IO -[debug]  lib.lib -[debug]  quasar -[debug]  quasar_bundle -[debug]  quasar_wrapper -[debug] Change NamesChange(include.ahb_channel,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(do_asUInt,[Default]), UsedName(instanceName,[Default]), UsedName(toTarget,[Default]), UsedName(suggestedName,[Default]), UsedName(notify,[Default]), UsedName(notifyAll,[Default]), UsedName(setRef,[Default]), UsedName(topBindingOpt,[Default]), UsedName(asInstanceOf,[Default]), UsedName(isLit,[Default]), UsedName(typeEquivalent,[Default]), UsedName(toString,[Default]), UsedName(direction_=,[Default]), UsedName(finalize,[Default]), UsedName(!=,[Default]), UsedName(isSynthesizable,[Default]), UsedName(synchronized,[Default]), UsedName(topBinding,[Default]), UsedName(asUInt,[Default]), UsedName(pathName,[Default]), UsedName(specifiedDirection,[Default]), UsedName(wait,[Default]), UsedName(getPublicFields,[Default]), UsedName(##,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(width,[Default]), UsedName(ne,[Default]), UsedName(ref,[Default]), UsedName(elements,[Default]), UsedName(equals,[Default]), UsedName(bulkConnect,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(==,[Default]), UsedName(suggestName,[Default]), UsedName(parentModName,[Default]), UsedName(flatten,[Default]), UsedName(out,[Default]), UsedName(binding_=,[Default]), UsedName(_makeLit,[Default]), UsedName(bind$default$2,[Default]), UsedName(parentPathName,[Default]), UsedName(isInstanceOf,[Default]), UsedName(compileOptions,[Implicit]), UsedName($isInstanceOf,[Default]), UsedName(getOptionRef,[Default]), UsedName(className,[Default]), UsedName(widthOption,[Default]), UsedName($init$,[Default]), UsedName(getElements,[Default]), UsedName(connectFromBits,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(include;ahb_channel;init;,[Default]), UsedName(ignoreSeq,[Default]), UsedName(circuitName,[Default]), UsedName(binding,[Default]), UsedName(<>,[Default]), UsedName(litArg,[Default]), UsedName(_onModuleClose,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(lref,[Default]), UsedName(litOption,[Default]), UsedName(allElements,[Default]), UsedName(connect,[Default]), UsedName(bind,[Default]), UsedName(getRef,[Default]), UsedName(getWidth,[Default]), UsedName(addPostnameHook,[Default]), UsedName(litValue,[Default]), UsedName(hashCode,[Default]), UsedName(cloneType,[Default]), UsedName(_parent,[Default]), UsedName(eq,[Default]), UsedName(ahb_channel,[Default]), UsedName(:=,[Default]), UsedName(in,[Default]), UsedName(bindingToString,[Default]), UsedName(clone,[Default]), UsedName(_id,[Default]), UsedName(isWidthKnown,[Default]), UsedName(getClass,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(toPrintable,[Default]), UsedName(forceName,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(direction,[Default]), UsedName($asInstanceOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(toNamed,[Default]), UsedName(badConnect,[Default]))) invalidates 8 classes due to The include.ahb_channel has the following implicit definitions changed: -[debug]  UsedName(compileOptions,[Implicit]). -[debug]  > by transitive inheritance: Set(include.ahb_channel) -[debug]  >  -[debug]  > by member reference: Set(lib.axi4_to_ahb_IO, lib.ahb_to_axi4, lib.axi4_to_ahb, quasar, quasar_bundle, quasar_wrapper, lib.lib) -[debug]   -[debug] Invalidating (transitively) by inheritance from include.read_addr... -[debug] Initial set of included nodes: include.read_addr -[debug] Invalidated by transitive inheritance dependency: Set(include.read_addr) -[debug] The following modified names cause invalidation of lib.ahb_to_axi4: Set(UsedName(asInstanceOf,[Default]), UsedName(read_addr,[Default]), UsedName(ne,[Default]), UsedName(==,[Default]), UsedName(isInstanceOf,[Default])) -[debug] The following modified names cause invalidation of lib.axi4_to_ahb: Set(UsedName(asInstanceOf,[Default]), UsedName(read_addr,[Default]), UsedName(==,[Default]), UsedName(isInstanceOf,[Default])) -[debug] The following modified names cause invalidation of lsu.lsu_bus_buffer: Set(UsedName(asInstanceOf,[Default]), UsedName(read_addr,[Default]), UsedName(==,[Default]), UsedName(isInstanceOf,[Default])) -[debug] The following modified names cause invalidation of dbg.dbg: Set(UsedName(read_addr,[Default])) -[debug] The following modified names cause invalidation of ifu.ifu_mem_ctl: Set(UsedName(asInstanceOf,[Default]), UsedName(read_addr,[Default]), UsedName(==,[Default]), UsedName(isInstanceOf,[Default])) -[debug] The following modified names cause invalidation of dma_ctrl: Set(UsedName(read_addr,[Default]), UsedName(ne,[Default])) -[debug] Change NamesChange(include.read_addr,ModifiedNames(changes = UsedName(include;read_addr;init;,[Default]), UsedName(notify,[Default]), UsedName(notifyAll,[Default]), UsedName(asInstanceOf,[Default]), UsedName(toString,[Default]), UsedName(finalize,[Default]), UsedName(!=,[Default]), UsedName(read_addr,[Default]), UsedName(synchronized,[Default]), UsedName(wait,[Default]), UsedName(##,[Default]), UsedName(ne,[Default]), UsedName(equals,[Default]), UsedName(bridge_gen,[Default]), UsedName(==,[Default]), UsedName($default$1,[Default]), UsedName(isInstanceOf,[Default]), UsedName($isInstanceOf,[Default]), UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(hashCode,[Default]), UsedName(eq,[Default]), UsedName(clone,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]))) invalidates 7 classes due to The include.read_addr has the following regular definitions changed: -[debug]  UsedName(include;read_addr;init;,[Default]), UsedName(notify,[Default]), UsedName(notifyAll,[Default]), UsedName(asInstanceOf,[Default]), UsedName(toString,[Default]), UsedName(finalize,[Default]), UsedName(!=,[Default]), UsedName(read_addr,[Default]), UsedName(synchronized,[Default]), UsedName(wait,[Default]), UsedName(##,[Default]), UsedName(ne,[Default]), UsedName(equals,[Default]), UsedName(bridge_gen,[Default]), UsedName(==,[Default]), UsedName($default$1,[Default]), UsedName(isInstanceOf,[Default]), UsedName($isInstanceOf,[Default]), UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(hashCode,[Default]), UsedName(eq,[Default]), UsedName(clone,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]). -[debug]  > by transitive inheritance: Set(include.read_addr) -[debug]  >  -[debug]  > by member reference: Set(lib.ahb_to_axi4, lib.axi4_to_ahb, lsu.lsu_bus_buffer, dbg.dbg, ifu.ifu_mem_ctl, dma_ctrl) -[debug]   -[debug] Invalidating (transitively) by inheritance from include.iccm_mem... -[debug] Initial set of included nodes: include.iccm_mem -[debug] Invalidated by transitive inheritance dependency: Set(include.iccm_mem) -[debug] None of the modified names appears in source file of ifu.ifu. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of quasar_bundle. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of ifu.mem_ctl_io. This dependency is not being considered for invalidation. -[debug] The following modified names cause invalidation of quasar_wrapper: Set(UsedName(bridge_gen,[Default])) -[debug] None of the modified names appears in source file of mem.Mem_bundle. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of ifu.ifu_mem_ctl. This dependency is not being considered for invalidation. -[debug] Change NamesChange(include.iccm_mem,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]))) invalidates 2 classes due to The include.iccm_mem has the following regular definitions changed: -[debug]  UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]). -[debug]  > by transitive inheritance: Set(include.iccm_mem) -[debug]  >  -[debug]  > by member reference: Set(quasar_wrapper) -[debug]   -[debug] Invalidating (transitively) by inheritance from ifu.mem_ctl_io... -[debug] Initial set of included nodes: ifu.mem_ctl_io -[debug] Invalidated by transitive inheritance dependency: Set(ifu.mem_ctl_io) -[debug] None of the modified names appears in source file of ifu.ifu. This dependency is not being considered for invalidation. -[debug] Change NamesChange(ifu.mem_ctl_io,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]))) invalidates 1 classes due to The ifu.mem_ctl_io has the following regular definitions changed: -[debug]  UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]). -[debug]  > by transitive inheritance: Set(ifu.mem_ctl_io) -[debug]  >  -[debug]  >  -[debug]   -[debug] Invalidating (transitively) by inheritance from include.aln_ib... -[debug] Initial set of included nodes: include.aln_ib -[debug] Invalidated by transitive inheritance dependency: Set(include.aln_ib) -[debug] None of the modified names appears in source file of dec.dec_ib_ctl_IO. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dec.dec_ib_ctl. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of ifu.ifu_aln_ctl. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dec.dec. This dependency is not being considered for invalidation. -[debug] Change NamesChange(include.aln_ib,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]))) invalidates 1 classes due to The include.aln_ib has the following regular definitions changed: -[debug]  UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]). -[debug]  > by transitive inheritance: Set(include.aln_ib) -[debug]  >  -[debug]  >  -[debug]   -[debug] Invalidating (transitively) by inheritance from lib.axi4_to_ahb_IO... -[debug] Initial set of included nodes: lib.axi4_to_ahb_IO -[debug] Invalidated by transitive inheritance dependency: Set(lib.axi4_to_ahb_IO) -[debug] The following modified names cause invalidation of quasar: Set(UsedName(ahb,[Default]), UsedName(axi,[Default])) -[debug] Change NamesChange(lib.axi4_to_ahb_IO,ModifiedNames(changes = UsedName(axi_wlast,[Default]), UsedName(axi_bid,[Default]), UsedName(axi_arready,[Default]), UsedName(axi_awaddr,[Default]), UsedName(axi_rresp,[Default]), UsedName(axi_rready,[Default]), UsedName(axi_wdata,[Default]), UsedName(axi_rvalid,[Default]), UsedName(axi_bready,[Default]), UsedName(axi_arid,[Default]), UsedName(axi_araddr,[Default]), UsedName(ahb_hsize,[Default]), UsedName(ahb_htrans,[Default]), UsedName(axi_wvalid,[Default]), UsedName(ahb_hresp,[Default]), UsedName(axi_arprot,[Default]), UsedName(ahb_hwdata,[Default]), UsedName(axi_arvalid,[Default]), UsedName(axi_wstrb,[Default]), UsedName(axi_awready,[Default]), UsedName(axi_awid,[Default]), UsedName(ahb,[Default]), UsedName(axi_awsize,[Default]), UsedName(ahb_hwrite,[Default]), UsedName(axi_awvalid,[Default]), UsedName(axi_rlast,[Default]), UsedName(ahb_hrdata,[Default]), UsedName(axi_bresp,[Default]), UsedName(ahb_hburst,[Default]), UsedName(axi_rdata,[Default]), UsedName(axi_awprot,[Default]), UsedName(axi_bvalid,[Default]), UsedName(axi_wready,[Default]), UsedName(ahb_haddr,[Default]), UsedName(axi,[Default]), UsedName(ahb_hready,[Default]), UsedName(axi_rid,[Default]), UsedName(ahb_hprot,[Default]), UsedName(axi_arsize,[Default]), UsedName(ahb_hmastlock,[Default]))) invalidates 2 classes due to The lib.axi4_to_ahb_IO has the following regular definitions changed: -[debug]  UsedName(axi_wlast,[Default]), UsedName(axi_bid,[Default]), UsedName(axi_arready,[Default]), UsedName(axi_awaddr,[Default]), UsedName(axi_rresp,[Default]), UsedName(axi_rready,[Default]), UsedName(axi_wdata,[Default]), UsedName(axi_rvalid,[Default]), UsedName(axi_bready,[Default]), UsedName(axi_arid,[Default]), UsedName(axi_araddr,[Default]), UsedName(ahb_hsize,[Default]), UsedName(ahb_htrans,[Default]), UsedName(axi_wvalid,[Default]), UsedName(ahb_hresp,[Default]), UsedName(axi_arprot,[Default]), UsedName(ahb_hwdata,[Default]), UsedName(axi_arvalid,[Default]), UsedName(axi_wstrb,[Default]), UsedName(axi_awready,[Default]), UsedName(axi_awid,[Default]), UsedName(ahb,[Default]), UsedName(axi_awsize,[Default]), UsedName(ahb_hwrite,[Default]), UsedName(axi_awvalid,[Default]), UsedName(axi_rlast,[Default]), UsedName(ahb_hrdata,[Default]), UsedName(axi_bresp,[Default]), UsedName(ahb_hburst,[Default]), UsedName(axi_rdata,[Default]), UsedName(axi_awprot,[Default]), UsedName(axi_bvalid,[Default]), UsedName(axi_wready,[Default]), UsedName(ahb_haddr,[Default]), UsedName(axi,[Default]), UsedName(ahb_hready,[Default]), UsedName(axi_rid,[Default]), UsedName(ahb_hprot,[Default]), UsedName(axi_arsize,[Default]), UsedName(ahb_hmastlock,[Default]). -[debug]  > by transitive inheritance: Set(lib.axi4_to_ahb_IO) -[debug]  >  -[debug]  > by member reference: Set(quasar) -[debug]   -[debug] Invalidating (transitively) by inheritance from dec.CSR_IO... -[debug] Initial set of included nodes: dec.CSR_IO -[debug] Invalidated by transitive inheritance dependency: Set(dec.CSR_IO) -[debug] Change NamesChange(dec.CSR_IO,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]))) invalidates 1 classes due to The dec.CSR_IO has the following regular definitions changed: -[debug]  UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]). -[debug]  > by transitive inheritance: Set(dec.CSR_IO) -[debug]  >  -[debug]  >  -[debug]   -[debug] Invalidating (transitively) by inheritance from snapshot.pt... -[debug] Initial set of included nodes: snapshot.pt -[debug] Invalidated by transitive inheritance dependency: Set(snapshot.pt) -[debug] Change NamesChange(snapshot.pt,ModifiedNames(changes = UsedName(BTB_ADDR_HI,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(notify,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(notifyAll,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_2BANKS,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(toString,[Default]), UsedName(finalize,[Default]), UsedName(!=,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(synchronized,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(wait,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(BTB_SIZE,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(##,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ne,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(equals,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(PIC_BITS,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(==,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(isInstanceOf,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName($isInstanceOf,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(hashCode,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(PIC_REGION,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(eq,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(clone,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(getClass,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName($asInstanceOf,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(pt,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]))) invalidates 1 classes due to The snapshot.pt has the following regular definitions changed: -[debug]  UsedName(BTB_ADDR_HI,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(notify,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(notifyAll,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_2BANKS,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(toString,[Default]), UsedName(finalize,[Default]), UsedName(!=,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(synchronized,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(wait,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(BTB_SIZE,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(##,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ne,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(equals,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(PIC_BITS,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(==,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(isInstanceOf,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName($isInstanceOf,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(hashCode,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(PIC_REGION,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(eq,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(clone,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(getClass,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName($asInstanceOf,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(pt,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]). -[debug]  > by transitive inheritance: Set(snapshot.pt) -[debug]  >  -[debug]  >  -[debug]   -[debug] Invalidating (transitively) by inheritance from lsu.lsu_addrcheck... -[debug] Initial set of included nodes: lsu.lsu_addrcheck -[debug] Invalidated by transitive inheritance dependency: Set(lsu.lsu_addrcheck) -[debug] None of the modified names appears in source file of lsu.lsu_lsc_ctl. This dependency is not being considered for invalidation. -[debug] Change NamesChange(lsu.lsu_addrcheck,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]))) invalidates 1 classes due to The lsu.lsu_addrcheck has the following regular definitions changed: -[debug]  UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]). -[debug]  > by transitive inheritance: Set(lsu.lsu_addrcheck) -[debug]  >  -[debug]  >  -[debug]   -[debug] Invalidating (transitively) by inheritance from lib.ahb_to_axi4... -[debug] Initial set of included nodes: lib.ahb_to_axi4 -[debug] Invalidated by transitive inheritance dependency: Set(lib.ahb_to_axi4) -[debug] The following modified names cause invalidation of quasar: Set(UsedName(hreadyin,[Default]), UsedName(hsel,[Default]), UsedName(ahb,[Default]), UsedName(io,[Default]), UsedName(sig,[Default]), UsedName(axi,[Default])) -[debug] Change NamesChange(lib.ahb_to_axi4,ModifiedNames(changes = UsedName(hreadyin,[Default]), UsedName(axi_wlast,[Default]), UsedName(axi_awburst,[Default]), UsedName(axi_bid,[Default]), UsedName(axi_arready,[Default]), UsedName(axi_awaddr,[Default]), UsedName(axi_awlen,[Default]), UsedName(hsel,[Default]), UsedName(axi_rresp,[Default]), UsedName(axi_rready,[Default]), UsedName(ahb_hreadyin,[Default]), UsedName(bridge_gen,[Default]), UsedName(ahb_hsel,[Default]), UsedName(axi_wdata,[Default]), UsedName(axi_rvalid,[Default]), UsedName(axi_bready,[Default]), UsedName(axi_arid,[Default]), UsedName(axi_araddr,[Default]), UsedName(ahb_hsize,[Default]), UsedName(ahb_htrans,[Default]), UsedName(axi_wvalid,[Default]), UsedName(ahb_hresp,[Default]), UsedName(ahb_bridge_gen,[Default]), UsedName(axi_arprot,[Default]), UsedName(ahb_hwdata,[Default]), UsedName(axi_arvalid,[Default]), UsedName(axi_wstrb,[Default]), UsedName(flip,[Default]), UsedName(axi_awready,[Default]), UsedName(axi_awid,[Default]), UsedName(ahb,[Default]), UsedName(axi_awsize,[Default]), UsedName(ahb_hwrite,[Default]), UsedName(axi_awvalid,[Default]), UsedName(ahb_hrdata,[Default]), UsedName(io,[Default]), UsedName(sig,[Default]), UsedName(axi_bresp,[Default]), UsedName(ahb_hburst,[Default]), UsedName(axi_rdata,[Default]), UsedName(axi_awprot,[Default]), UsedName(axi_bvalid,[Default]), UsedName(axi_wready,[Default]), UsedName(axi_arburst,[Default]), UsedName(ahb_haddr,[Default]), UsedName(axi_arlen,[Default]), UsedName(axi,[Default]), UsedName(axi_rid,[Default]), UsedName(ahb_hprot,[Default]), UsedName(axi_arsize,[Default]), UsedName(ahb_hreadyout,[Default]), UsedName(ahb_hmastlock,[Default]))) invalidates 2 classes due to The lib.ahb_to_axi4 has the following regular definitions changed: -[debug]  UsedName(hreadyin,[Default]), UsedName(axi_wlast,[Default]), UsedName(axi_awburst,[Default]), UsedName(axi_bid,[Default]), UsedName(axi_arready,[Default]), UsedName(axi_awaddr,[Default]), UsedName(axi_awlen,[Default]), UsedName(hsel,[Default]), UsedName(axi_rresp,[Default]), UsedName(axi_rready,[Default]), UsedName(ahb_hreadyin,[Default]), UsedName(bridge_gen,[Default]), UsedName(ahb_hsel,[Default]), UsedName(axi_wdata,[Default]), UsedName(axi_rvalid,[Default]), UsedName(axi_bready,[Default]), UsedName(axi_arid,[Default]), UsedName(axi_araddr,[Default]), UsedName(ahb_hsize,[Default]), UsedName(ahb_htrans,[Default]), UsedName(axi_wvalid,[Default]), UsedName(ahb_hresp,[Default]), UsedName(ahb_bridge_gen,[Default]), UsedName(axi_arprot,[Default]), UsedName(ahb_hwdata,[Default]), UsedName(axi_arvalid,[Default]), UsedName(axi_wstrb,[Default]), UsedName(flip,[Default]), UsedName(axi_awready,[Default]), UsedName(axi_awid,[Default]), UsedName(ahb,[Default]), UsedName(axi_awsize,[Default]), UsedName(ahb_hwrite,[Default]), UsedName(axi_awvalid,[Default]), UsedName(ahb_hrdata,[Default]), UsedName(io,[Default]), UsedName(sig,[Default]), UsedName(axi_bresp,[Default]), UsedName(ahb_hburst,[Default]), UsedName(axi_rdata,[Default]), UsedName(axi_awprot,[Default]), UsedName(axi_bvalid,[Default]), UsedName(axi_wready,[Default]), UsedName(axi_arburst,[Default]), UsedName(ahb_haddr,[Default]), UsedName(axi_arlen,[Default]), UsedName(axi,[Default]), UsedName(axi_rid,[Default]), UsedName(ahb_hprot,[Default]), UsedName(axi_arsize,[Default]), UsedName(ahb_hreadyout,[Default]), UsedName(ahb_hmastlock,[Default]). -[debug]  > by transitive inheritance: Set(lib.ahb_to_axi4) -[debug]  >  -[debug]  > by member reference: Set(quasar) -[debug]   -[debug] Invalidating (transitively) by inheritance from lib.axi4_to_ahb... -[debug] Initial set of included nodes: lib.axi4_to_ahb -[debug] Invalidated by transitive inheritance dependency: Set(lib.axi4_to_ahb) -[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation. -[debug] Change NamesChange(lib.axi4_to_ahb,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]))) invalidates 1 classes due to The lib.axi4_to_ahb has the following regular definitions changed: -[debug]  UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]). -[debug]  > by transitive inheritance: Set(lib.axi4_to_ahb) -[debug]  >  -[debug]  >  -[debug]   -[debug] Invalidating (transitively) by inheritance from dec.dec_trigger... -[debug] Initial set of included nodes: dec.dec_trigger -[debug] Invalidated by transitive inheritance dependency: Set(dec.dec_trigger) -[debug] None of the modified names appears in source file of dec.dec. This dependency is not being considered for invalidation. -[debug] Change NamesChange(dec.dec_trigger,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]))) invalidates 1 classes due to The dec.dec_trigger has the following regular definitions changed: -[debug]  UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]). -[debug]  > by transitive inheritance: Set(dec.dec_trigger) -[debug]  >  -[debug]  >  -[debug]   -[debug] Invalidating (transitively) by inheritance from dma_ctrl... -[debug] Initial set of included nodes: dma_ctrl -[debug] Invalidated by transitive inheritance dependency: Set(dma_ctrl) -[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation. -[debug] Change NamesChange(dma_ctrl,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]))) invalidates 1 classes due to The dma_ctrl has the following regular definitions changed: -[debug]  UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]). -[debug]  > by transitive inheritance: Set(dma_ctrl) -[debug]  >  -[debug]  >  -[debug]   -[debug] Invalidating (transitively) by inheritance from include.ic_mem... -[debug] Initial set of included nodes: include.ic_mem -[debug] Invalidated by transitive inheritance dependency: Set(include.ic_mem) -[debug] None of the modified names appears in source file of ifu.ifu. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of quasar_bundle. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of ifu.mem_ctl_io. This dependency is not being considered for invalidation. -[debug] The following modified names cause invalidation of quasar_wrapper: Set(UsedName(bridge_gen,[Default])) -[debug] None of the modified names appears in source file of mem.Mem_bundle. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of ifu.ifu_mem_ctl. This dependency is not being considered for invalidation. -[debug] Change NamesChange(include.ic_mem,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]))) invalidates 2 classes due to The include.ic_mem has the following regular definitions changed: -[debug]  UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]). -[debug]  > by transitive inheritance: Set(include.ic_mem) -[debug]  >  -[debug]  > by member reference: Set(quasar_wrapper) -[debug]   -[debug] Invalidating (transitively) by inheritance from lsu.lsu_bus_buffer... -[debug] Initial set of included nodes: lsu.lsu_bus_buffer -[debug] Invalidated by transitive inheritance dependency: Set(lsu.lsu_bus_buffer) -[debug] None of the modified names appears in source file of lsu.lsu_bus_intf. This dependency is not being considered for invalidation. -[debug] Change NamesChange(lsu.lsu_bus_buffer,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]))) invalidates 1 classes due to The lsu.lsu_bus_buffer has the following regular definitions changed: -[debug]  UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]). -[debug]  > by transitive inheritance: Set(lsu.lsu_bus_buffer) -[debug]  >  -[debug]  >  -[debug]   -[debug] Invalidating (transitively) by inheritance from dec.dec_gpr_ctl... -[debug] Initial set of included nodes: dec.dec_gpr_ctl -[debug] Invalidated by transitive inheritance dependency: Set(dec.dec_gpr_ctl) -[debug] None of the modified names appears in source file of dec.dec. This dependency is not being considered for invalidation. -[debug] Change NamesChange(dec.dec_gpr_ctl,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]))) invalidates 1 classes due to The dec.dec_gpr_ctl has the following regular definitions changed: -[debug]  UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]). -[debug]  > by transitive inheritance: Set(dec.dec_gpr_ctl) -[debug]  >  -[debug]  >  -[debug]   -[debug] Invalidating (transitively) by inheritance from dec.dec_IO... -[debug] Initial set of included nodes: dec.dec_IO -[debug] Invalidated by transitive inheritance dependency: Set(dec.dec_IO) -[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation. -[debug] Change NamesChange(dec.dec_IO,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]))) invalidates 1 classes due to The dec.dec_IO has the following regular definitions changed: -[debug]  UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]). -[debug]  > by transitive inheritance: Set(dec.dec_IO) -[debug]  >  -[debug]  >  -[debug]   -[debug] Invalidating (transitively) by inheritance from dec.dec_dec_ctl... -[debug] Initial set of included nodes: dec.dec_dec_ctl -[debug] Invalidated by transitive inheritance dependency: Set(dec.dec_dec_ctl) -[debug] None of the modified names appears in source file of dec.dec_decode_ctl. This dependency is not being considered for invalidation. -[debug] Change NamesChange(dec.dec_dec_ctl,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]))) invalidates 1 classes due to The dec.dec_dec_ctl has the following regular definitions changed: -[debug]  UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]). -[debug]  > by transitive inheritance: Set(dec.dec_dec_ctl) -[debug]  >  -[debug]  >  -[debug]   -[debug] Invalidating (transitively) by inheritance from ifu.ifu... -[debug] Initial set of included nodes: ifu.ifu -[debug] Invalidated by transitive inheritance dependency: Set(ifu.ifu) -[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation. -[debug] Change NamesChange(ifu.ifu,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]))) invalidates 1 classes due to The ifu.ifu has the following regular definitions changed: -[debug]  UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]). -[debug]  > by transitive inheritance: Set(ifu.ifu) -[debug]  >  -[debug]  >  -[debug]   -[debug] Invalidating (transitively) by inheritance from quasar_bundle... -[debug] Initial set of included nodes: quasar_bundle -[debug] Invalidated by transitive inheritance dependency: Set(quasar_bundle) -[debug] The following modified names cause invalidation of quasar_wrapper: Set(UsedName(hreadyin,[Default]), UsedName(hsel,[Default]), UsedName(dma_ahb,[Default]), UsedName(ifu_ahb,[Default]), UsedName(bridge_gen,[Default]), UsedName(sb_ahb,[Default]), UsedName(lsu_ahb,[Default]), UsedName(sig,[Default])) -[debug] Change NamesChange(quasar_bundle,ModifiedNames(changes = UsedName(dma_hsize,[Default]), UsedName(lsu_hresp,[Default]), UsedName(hreadyin,[Default]), UsedName(hresp,[Default]), UsedName(lsu_hburst,[Default]), UsedName(dma_hreadyout,[Default]), UsedName(dma_hresp,[Default]), UsedName(hmastlock,[Default]), UsedName(lsu_hsize,[Default]), UsedName(dma_htrans,[Default]), UsedName(hsel,[Default]), UsedName(dma_ahb,[Default]), UsedName(hready,[Default]), UsedName(sb_hwdata,[Default]), UsedName(lsu_hwrite,[Default]), UsedName(sb_hwrite,[Default]), UsedName(hrdata,[Default]), UsedName(hsize,[Default]), UsedName(ifu_ahb,[Default]), UsedName(bridge_gen,[Default]), UsedName(sb_hburst,[Default]), UsedName(htrans,[Default]), UsedName(sb_ahb,[Default]), UsedName(sb_hprot,[Default]), UsedName(hburst,[Default]), UsedName(lsu_hready,[Default]), UsedName(lsu_ahb,[Default]), UsedName(lsu_hmastlock,[Default]), UsedName(dma_hsel,[Default]), UsedName(sb_hsize,[Default]), UsedName(lsu_haddr,[Default]), UsedName(sb_htrans,[Default]), UsedName(ahb_bridge_gen,[Default]), UsedName(sb_hready,[Default]), UsedName(hprot,[Default]), UsedName(dma_hburst,[Default]), UsedName(lsu_htrans,[Default]), UsedName(flip,[Default]), UsedName(dma_haddr,[Default]), UsedName(lsu_hrdata,[Default]), UsedName(dma_hmastlock,[Default]), UsedName(lsu_hprot,[Default]), UsedName(sb_hrdata,[Default]), UsedName(sb_hmastlock,[Default]), UsedName(dma_hrdata,[Default]), UsedName(sb_haddr,[Default]), UsedName(sig,[Default]), UsedName(dma_hwrite,[Default]), UsedName(sb_hresp,[Default]), UsedName(dma_hwdata,[Default]), UsedName(dma_hreadyin,[Default]), UsedName(dma_hprot,[Default]), UsedName(lsu_hwdata,[Default]), UsedName(haddr,[Default]), UsedName(hwrite,[Default]))) invalidates 2 classes due to The quasar_bundle has the following regular definitions changed: -[debug]  UsedName(dma_hsize,[Default]), UsedName(lsu_hresp,[Default]), UsedName(hreadyin,[Default]), UsedName(hresp,[Default]), UsedName(lsu_hburst,[Default]), UsedName(dma_hreadyout,[Default]), UsedName(dma_hresp,[Default]), UsedName(hmastlock,[Default]), UsedName(lsu_hsize,[Default]), UsedName(dma_htrans,[Default]), UsedName(hsel,[Default]), UsedName(dma_ahb,[Default]), UsedName(hready,[Default]), UsedName(sb_hwdata,[Default]), UsedName(lsu_hwrite,[Default]), UsedName(sb_hwrite,[Default]), UsedName(hrdata,[Default]), UsedName(hsize,[Default]), UsedName(ifu_ahb,[Default]), UsedName(bridge_gen,[Default]), UsedName(sb_hburst,[Default]), UsedName(htrans,[Default]), UsedName(sb_ahb,[Default]), UsedName(sb_hprot,[Default]), UsedName(hburst,[Default]), UsedName(lsu_hready,[Default]), UsedName(lsu_ahb,[Default]), UsedName(lsu_hmastlock,[Default]), UsedName(dma_hsel,[Default]), UsedName(sb_hsize,[Default]), UsedName(lsu_haddr,[Default]), UsedName(sb_htrans,[Default]), UsedName(ahb_bridge_gen,[Default]), UsedName(sb_hready,[Default]), UsedName(hprot,[Default]), UsedName(dma_hburst,[Default]), UsedName(lsu_htrans,[Default]), UsedName(flip,[Default]), UsedName(dma_haddr,[Default]), UsedName(lsu_hrdata,[Default]), UsedName(dma_hmastlock,[Default]), UsedName(lsu_hprot,[Default]), UsedName(sb_hrdata,[Default]), UsedName(sb_hmastlock,[Default]), UsedName(dma_hrdata,[Default]), UsedName(sb_haddr,[Default]), UsedName(sig,[Default]), UsedName(dma_hwrite,[Default]), UsedName(sb_hresp,[Default]), UsedName(dma_hwdata,[Default]), UsedName(dma_hreadyin,[Default]), UsedName(dma_hprot,[Default]), UsedName(lsu_hwdata,[Default]), UsedName(haddr,[Default]), UsedName(hwrite,[Default]). -[debug]  > by transitive inheritance: Set(quasar_bundle) -[debug]  >  -[debug]  > by member reference: Set(quasar_wrapper) -[debug]   -[debug] Invalidating (transitively) by inheritance from mem.quasar... -[debug] Initial set of included nodes: mem.quasar -[debug] Invalidated by transitive inheritance dependency: Set(mem.quasar) -[debug] The following modified names cause invalidation of quasar_wrapper: Set(UsedName(bridge_gen,[Default])) -[debug] Change NamesChange(mem.quasar,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]))) invalidates 2 classes due to The mem.quasar has the following regular definitions changed: -[debug]  UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]). -[debug]  > by transitive inheritance: Set(mem.quasar) -[debug]  >  -[debug]  > by member reference: Set(quasar_wrapper) -[debug]   -[debug] Invalidating (transitively) by inheritance from include.decode_exu... -[debug] Initial set of included nodes: include.decode_exu -[debug] Invalidated by transitive inheritance dependency: Set(include.decode_exu) -[debug] None of the modified names appears in source file of dec.dec. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dec.dec_decode_ctl. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of exu.exu. This dependency is not being considered for invalidation. -[debug] Change NamesChange(include.decode_exu,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]))) invalidates 1 classes due to The include.decode_exu has the following regular definitions changed: -[debug]  UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]). -[debug]  > by transitive inheritance: Set(include.decode_exu) -[debug]  >  -[debug]  >  -[debug]   -[debug] Invalidating (transitively) by inheritance from pic_ctrl... -[debug] Initial set of included nodes: pic_ctrl -[debug] Invalidated by transitive inheritance dependency: Set(pic_ctrl) -[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation. -[debug] Change NamesChange(pic_ctrl,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]))) invalidates 1 classes due to The pic_ctrl has the following regular definitions changed: -[debug]  UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]). -[debug]  > by transitive inheritance: Set(pic_ctrl) -[debug]  >  -[debug]  >  -[debug]   -[debug] Invalidating (transitively) by inheritance from lsu.lsu_ecc... -[debug] Initial set of included nodes: lsu.lsu_ecc -[debug] Invalidated by transitive inheritance dependency: Set(lsu.lsu_ecc) -[debug] None of the modified names appears in source file of lsu.lsu. This dependency is not being considered for invalidation. -[debug] Change NamesChange(lsu.lsu_ecc,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]))) invalidates 1 classes due to The lsu.lsu_ecc has the following regular definitions changed: -[debug]  UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]). -[debug]  > by transitive inheritance: Set(lsu.lsu_ecc) -[debug]  >  -[debug]  >  -[debug]   -[debug] Invalidating (transitively) by inheritance from include.ahb_out_dma... -[debug] Initial set of included nodes: include.ahb_out_dma -[debug] Invalidated by transitive inheritance dependency: Set(include.ahb_out_dma) -[debug] Change NamesChange(include.ahb_out_dma,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(do_asUInt,[Default]), UsedName(instanceName,[Default]), UsedName(toTarget,[Default]), UsedName(suggestedName,[Default]), UsedName(notify,[Default]), UsedName(notifyAll,[Default]), UsedName(setRef,[Default]), UsedName(topBindingOpt,[Default]), UsedName(asInstanceOf,[Default]), UsedName(isLit,[Default]), UsedName(typeEquivalent,[Default]), UsedName(hmastlock,[Default]), UsedName(toString,[Default]), UsedName(direction_=,[Default]), UsedName(finalize,[Default]), UsedName(!=,[Default]), UsedName(isSynthesizable,[Default]), UsedName(synchronized,[Default]), UsedName(topBinding,[Default]), UsedName(asUInt,[Default]), UsedName(pathName,[Default]), UsedName(specifiedDirection,[Default]), UsedName(wait,[Default]), UsedName(getPublicFields,[Default]), UsedName(##,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(width,[Default]), UsedName(ne,[Default]), UsedName(ref,[Default]), UsedName(elements,[Default]), UsedName(equals,[Default]), UsedName(hsize,[Default]), UsedName(bulkConnect,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(htrans,[Default]), UsedName(==,[Default]), UsedName(suggestName,[Default]), UsedName(parentModName,[Default]), UsedName(flatten,[Default]), UsedName(hburst,[Default]), UsedName(binding_=,[Default]), UsedName(_makeLit,[Default]), UsedName(bind$default$2,[Default]), UsedName(parentPathName,[Default]), UsedName(isInstanceOf,[Default]), UsedName(compileOptions,[Implicit]), UsedName($isInstanceOf,[Default]), UsedName(getOptionRef,[Default]), UsedName(className,[Default]), UsedName(widthOption,[Default]), UsedName($init$,[Default]), UsedName(getElements,[Default]), UsedName(connectFromBits,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(ignoreSeq,[Default]), UsedName(circuitName,[Default]), UsedName(binding,[Default]), UsedName(<>,[Default]), UsedName(litArg,[Default]), UsedName(hprot,[Default]), UsedName(_onModuleClose,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(lref,[Default]), UsedName(litOption,[Default]), UsedName(include;ahb_out_dma;init;,[Default]), UsedName(allElements,[Default]), UsedName(connect,[Default]), UsedName(bind,[Default]), UsedName(getRef,[Default]), UsedName(getWidth,[Default]), UsedName(addPostnameHook,[Default]), UsedName(litValue,[Default]), UsedName(hashCode,[Default]), UsedName(cloneType,[Default]), UsedName(_parent,[Default]), UsedName(eq,[Default]), UsedName(:=,[Default]), UsedName(ahb_out_dma,[Default]), UsedName(bindingToString,[Default]), UsedName(clone,[Default]), UsedName(_id,[Default]), UsedName(hwdata,[Default]), UsedName(isWidthKnown,[Default]), UsedName(getClass,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(toPrintable,[Default]), UsedName(forceName,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(direction,[Default]), UsedName($asInstanceOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(haddr,[Default]), UsedName(toNamed,[Default]), UsedName(hwrite,[Default]), UsedName(badConnect,[Default]))) invalidates 1 classes due to The include.ahb_out_dma has the following implicit definitions changed: -[debug]  UsedName(compileOptions,[Implicit]). -[debug]  > by transitive inheritance: Set(include.ahb_out_dma) -[debug]  >  -[debug]  >  -[debug]   -[debug] Invalidating (transitively) by inheritance from exu.exu_mul_ctl... -[debug] Initial set of included nodes: exu.exu_mul_ctl -[debug] Invalidated by transitive inheritance dependency: Set(exu.exu_mul_ctl) -[debug] None of the modified names appears in source file of exu.exu. This dependency is not being considered for invalidation. -[debug] Change NamesChange(exu.exu_mul_ctl,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]))) invalidates 1 classes due to The exu.exu_mul_ctl has the following regular definitions changed: -[debug]  UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]). -[debug]  > by transitive inheritance: Set(exu.exu_mul_ctl) -[debug]  >  -[debug]  >  -[debug]   -[debug] Invalidating (transitively) by inheritance from ifu.ifu_aln_ctl... -[debug] Initial set of included nodes: ifu.ifu_aln_ctl -[debug] Invalidated by transitive inheritance dependency: Set(ifu.ifu_aln_ctl) -[debug] None of the modified names appears in source file of ifu.ifu. This dependency is not being considered for invalidation. -[debug] Change NamesChange(ifu.ifu_aln_ctl,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]))) invalidates 1 classes due to The ifu.ifu_aln_ctl has the following regular definitions changed: -[debug]  UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]). -[debug]  > by transitive inheritance: Set(ifu.ifu_aln_ctl) -[debug]  >  -[debug]  >  -[debug]   -[debug] Invalidating (transitively) by inheritance from dec.dec_tlu_ctl_IO... -[debug] Initial set of included nodes: dec.dec_tlu_ctl_IO -[debug] Invalidated by transitive inheritance dependency: Set(dec.dec_tlu_ctl_IO) -[debug] None of the modified names appears in source file of dec.dec. This dependency is not being considered for invalidation. -[debug] Change NamesChange(dec.dec_tlu_ctl_IO,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]))) invalidates 1 classes due to The dec.dec_tlu_ctl_IO has the following regular definitions changed: -[debug]  UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]). -[debug]  > by transitive inheritance: Set(dec.dec_tlu_ctl_IO) -[debug]  >  -[debug]  >  -[debug]   -[debug] Invalidating (transitively) by inheritance from dec.dec_timer_ctl... -[debug] Initial set of included nodes: dec.dec_timer_ctl -[debug] Invalidated by transitive inheritance dependency: Set(dec.dec_timer_ctl) -[debug] Change NamesChange(dec.dec_timer_ctl,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]))) invalidates 1 classes due to The dec.dec_timer_ctl has the following regular definitions changed: -[debug]  UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]). -[debug]  > by transitive inheritance: Set(dec.dec_timer_ctl) -[debug]  >  -[debug]  >  -[debug]   -[debug] Invalidating (transitively) by inheritance from exu.exu_div_ctl... -[debug] Initial set of included nodes: exu.exu_div_ctl -[debug] Invalidated by transitive inheritance dependency: Set(exu.exu_div_ctl) -[debug] None of the modified names appears in source file of exu.exu. This dependency is not being considered for invalidation. -[debug] Change NamesChange(exu.exu_div_ctl,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]))) invalidates 1 classes due to The exu.exu_div_ctl has the following regular definitions changed: -[debug]  UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]). -[debug]  > by transitive inheritance: Set(exu.exu_div_ctl) -[debug]  >  -[debug]  >  -[debug]   -[debug] Invalidating (transitively) by inheritance from include.write_addr... -[debug] Initial set of included nodes: include.write_addr -[debug] Invalidated by transitive inheritance dependency: Set(include.write_addr) -[debug] The following modified names cause invalidation of lib.ahb_to_axi4: Set(UsedName(asInstanceOf,[Default]), UsedName(ne,[Default]), UsedName(==,[Default]), UsedName(isInstanceOf,[Default]), UsedName(write_addr,[Default])) -[debug] The following modified names cause invalidation of lib.axi4_to_ahb: Set(UsedName(asInstanceOf,[Default]), UsedName(==,[Default]), UsedName(isInstanceOf,[Default]), UsedName(write_addr,[Default])) -[debug] The following modified names cause invalidation of lsu.lsu_bus_buffer: Set(UsedName(asInstanceOf,[Default]), UsedName(==,[Default]), UsedName(isInstanceOf,[Default]), UsedName(write_addr,[Default])) -[debug] The following modified names cause invalidation of dbg.dbg: Set(UsedName(write_addr,[Default])) -[debug] The following modified names cause invalidation of ifu.ifu_mem_ctl: Set(UsedName(asInstanceOf,[Default]), UsedName(==,[Default]), UsedName(isInstanceOf,[Default]), UsedName(write_addr,[Default])) -[debug] The following modified names cause invalidation of dma_ctrl: Set(UsedName(ne,[Default]), UsedName(write_addr,[Default])) -[debug] Change NamesChange(include.write_addr,ModifiedNames(changes = UsedName(notify,[Default]), UsedName(notifyAll,[Default]), UsedName(asInstanceOf,[Default]), UsedName(toString,[Default]), UsedName(finalize,[Default]), UsedName(!=,[Default]), UsedName(synchronized,[Default]), UsedName(wait,[Default]), UsedName(##,[Default]), UsedName(ne,[Default]), UsedName(equals,[Default]), UsedName(bridge_gen,[Default]), UsedName(==,[Default]), UsedName($default$1,[Default]), UsedName(isInstanceOf,[Default]), UsedName($isInstanceOf,[Default]), UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(write_addr,[Default]), UsedName(hashCode,[Default]), UsedName(eq,[Default]), UsedName(clone,[Default]), UsedName(getClass,[Default]), UsedName(include;write_addr;init;,[Default]), UsedName($asInstanceOf,[Default]))) invalidates 7 classes due to The include.write_addr has the following regular definitions changed: -[debug]  UsedName(notify,[Default]), UsedName(notifyAll,[Default]), UsedName(asInstanceOf,[Default]), UsedName(toString,[Default]), UsedName(finalize,[Default]), UsedName(!=,[Default]), UsedName(synchronized,[Default]), UsedName(wait,[Default]), UsedName(##,[Default]), UsedName(ne,[Default]), UsedName(equals,[Default]), UsedName(bridge_gen,[Default]), UsedName(==,[Default]), UsedName($default$1,[Default]), UsedName(isInstanceOf,[Default]), UsedName($isInstanceOf,[Default]), UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(write_addr,[Default]), UsedName(hashCode,[Default]), UsedName(eq,[Default]), UsedName(clone,[Default]), UsedName(getClass,[Default]), UsedName(include;write_addr;init;,[Default]), UsedName($asInstanceOf,[Default]). -[debug]  > by transitive inheritance: Set(include.write_addr) -[debug]  >  -[debug]  > by member reference: Set(lib.ahb_to_axi4, lib.axi4_to_ahb, lsu.lsu_bus_buffer, dbg.dbg, ifu.ifu_mem_ctl, dma_ctrl) -[debug]   -[debug] Invalidating (transitively) by inheritance from dec.dec_tlu_ctl... -[debug] Initial set of included nodes: dec.dec_tlu_ctl -[debug] Invalidated by transitive inheritance dependency: Set(dec.dec_tlu_ctl) -[debug] None of the modified names appears in source file of dec.dec. This dependency is not being considered for invalidation. -[debug] Change NamesChange(dec.dec_tlu_ctl,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]))) invalidates 1 classes due to The dec.dec_tlu_ctl has the following regular definitions changed: -[debug]  UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]). -[debug]  > by transitive inheritance: Set(dec.dec_tlu_ctl) -[debug]  >  -[debug]  >  -[debug]   -[debug] Invalidating (transitively) by inheritance from lsu.lsu_stbuf... -[debug] Initial set of included nodes: lsu.lsu_stbuf -[debug] Invalidated by transitive inheritance dependency: Set(lsu.lsu_stbuf) -[debug] None of the modified names appears in source file of lsu.lsu. This dependency is not being considered for invalidation. -[debug] Change NamesChange(lsu.lsu_stbuf,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]))) invalidates 1 classes due to The lsu.lsu_stbuf has the following regular definitions changed: -[debug]  UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]). -[debug]  > by transitive inheritance: Set(lsu.lsu_stbuf) -[debug]  >  -[debug]  >  -[debug]   -[debug] Invalidating (transitively) by inheritance from lsu.lsu... -[debug] Initial set of included nodes: lsu.lsu -[debug] Invalidated by transitive inheritance dependency: Set(lsu.lsu) -[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation. -[debug] Change NamesChange(lsu.lsu,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]))) invalidates 1 classes due to The lsu.lsu has the following regular definitions changed: -[debug]  UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]). -[debug]  > by transitive inheritance: Set(lsu.lsu) -[debug]  >  -[debug]  >  -[debug]   -[debug] Invalidating (transitively) by inheritance from lib.lib... -[debug] Initial set of included nodes: lib.lib -[debug] Including lsu.lsu_clkdomain by lib.lib -[debug] Including exu.exu by lib.lib -[debug] Including dec.dec_decode_ctl by lib.lib -[debug] Including lsu.lsu_trigger by lib.lib -[debug] Including include.exu_bp by lib.lib -[debug] Including dec.dec_gpr_ctl by lib.lib -[debug] Including lsu.lsu_addrcheck by lib.lib -[debug] Including mem.quasar by lib.lib -[debug] Including include.dec_aln by lib.lib -[debug] Including ifu.ifu by lib.lib -[debug] Including include.aln_ib by lib.lib -[debug] Including dec.dec_tlu_ctl_IO by lib.lib -[debug] Including exu.exu_div_ctl by lib.lib -[debug] Including lsu.lsu by lib.lib -[debug] Including dec.dec_tlu_ctl by lib.lib -[debug] Including lib.ahb_to_axi4 by lib.lib -[debug] Including lib.axi4_to_ahb by lib.lib -[debug] Including quasar by lib.lib -[debug] Including dec.csr_tlu by lib.lib -[debug] Including lsu.lsu_lsc_ctl by lib.lib -[debug] Including pic_ctrl by lib.lib -[debug] Including include.write_data by lib.lib -[debug] Including exu.exu_alu_ctl by lib.lib -[debug] Including include.tlu_exu by lib.lib -[debug] Including dec.dec_IO by lib.lib -[debug] Including include.iccm_mem by lib.lib -[debug] Including quasar_bundle by lib.lib -[debug] Including lsu.lsu_ecc by lib.lib -[debug] Including mem.blackbox_mem by lib.lib -[debug] Including include.write_addr by lib.lib -[debug] Including ifu.mem_ctl_io by lib.lib -[debug] Including lsu.lsu_bus_buffer by lib.lib -[debug] Including quasar_wrapper by lib.lib -[debug] Including include.write_resp by lib.lib -[debug] Including dec.CSR_IO by lib.lib -[debug] Including dec.dec_timer_ctl by lib.lib -[debug] Including include.dec_exu by lib.lib -[debug] Including include.read_data by lib.lib -[debug] Including ifu.ifu_aln_ctl by lib.lib -[debug] Including dbg.dbg by lib.lib -[debug] Including include.ic_mem by lib.lib -[debug] Including lsu.lsu_bus_intf by lib.lib -[debug] Including exu.exu_mul_ctl by lib.lib -[debug] Including dec.dec_trigger by lib.lib -[debug] Including lsu.lsu_dccm_ctl by lib.lib -[debug] Including ifu.ifu_compress_ctl by lib.lib -[debug] Including ifu.ifu_bp_ctl by lib.lib -[debug] Including mem.Mem_bundle by lib.lib -[debug] Including include.dctl_busbuff by lib.lib -[debug] Including include.read_addr by lib.lib -[debug] Including include.axi_channels by lib.lib -[debug] Including dec.dec_dec_ctl by lib.lib -[debug] Including lsu.lsu_stbuf by lib.lib -[debug] Including mem.mem_lsu by lib.lib -[debug] Including include.dec_mem_ctrl by lib.lib -[debug] Including ifu.ifu_mem_ctl by lib.lib -[debug] Including ifu.ifu_ifc_ctl by lib.lib -[debug] Including include.decode_exu by lib.lib -[debug] Including dma_ctrl by lib.lib -[debug] Invalidated by transitive inheritance dependency: Set(lsu.lsu_clkdomain, exu.exu, dec.dec_decode_ctl, lsu.lsu_trigger, include.exu_bp, dec.dec_gpr_ctl, lsu.lsu_addrcheck, mem.quasar, include.dec_aln, ifu.ifu, include.aln_ib, dec.dec_tlu_ctl_IO, exu.exu_div_ctl, lsu.lsu, dec.dec_tlu_ctl, lib.ahb_to_axi4, lib.axi4_to_ahb, quasar, dec.csr_tlu, lsu.lsu_lsc_ctl, pic_ctrl, include.write_data, exu.exu_alu_ctl, include.tlu_exu, dec.dec_IO, include.iccm_mem, quasar_bundle, lsu.lsu_ecc, mem.blackbox_mem, include.write_addr, ifu.mem_ctl_io, lsu.lsu_bus_buffer, quasar_wrapper, include.write_resp, dec.CSR_IO, dec.dec_timer_ctl, include.dec_exu, include.read_data, ifu.ifu_aln_ctl, dbg.dbg, include.ic_mem, lsu.lsu_bus_intf, exu.exu_mul_ctl, dec.dec_trigger, lsu.lsu_dccm_ctl, ifu.ifu_compress_ctl, ifu.ifu_bp_ctl, mem.Mem_bundle, include.dctl_busbuff, include.read_addr, include.axi_channels, dec.dec_dec_ctl, lsu.lsu_stbuf, mem.mem_lsu, include.dec_mem_ctrl, ifu.ifu_mem_ctl, ifu.ifu_ifc_ctl, include.decode_exu, lib.lib, dma_ctrl) -[debug] None of the modified names appears in source file of lsu.lsu. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dec.dec. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of lsu.lsu. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of ifu.ifu_bp_ctl. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of ifu.ifu. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of exu.exu. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dec.dec. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of lsu.lsu_lsc_ctl. This dependency is not being considered for invalidation. -[debug] The following modified names cause invalidation of quasar_wrapper: Set(UsedName(bridge_gen,[Default])) -[debug] None of the modified names appears in source file of ifu.ifu_aln_ctl. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of ifu.ifu. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dec.dec. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dec.dec_ib_ctl_IO. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dec.dec_ib_ctl. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of ifu.ifu_aln_ctl. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dec.dec. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dec.dec. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of exu.exu. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dec.dec. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation. -[debug] The following modified names cause invalidation of quasar_wrapper: Set(UsedName(bridge_gen,[Default])) -[debug] None of the modified names appears in source file of lsu.lsu. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of lib.ahb_to_axi4. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of lib.axi4_to_ahb. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of lsu.lsu_bus_buffer. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dbg.dbg. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of ifu.ifu_mem_ctl. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dma_ctrl. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of exu.exu. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dec.dec. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of exu.exu. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dec.dec_tlu_ctl_IO. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dec.dec_tlu_ctl. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of ifu.ifu. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of quasar_bundle. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of ifu.mem_ctl_io. This dependency is not being considered for invalidation. -[debug] The following modified names cause invalidation of quasar_wrapper: Set(UsedName(bridge_gen,[Default])) -[debug] None of the modified names appears in source file of mem.Mem_bundle. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of ifu.ifu_mem_ctl. This dependency is not being considered for invalidation. -[debug] The following modified names cause invalidation of quasar_wrapper: Set(UsedName(bridge_gen,[Default])) -[debug] None of the modified names appears in source file of lsu.lsu. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of lib.ahb_to_axi4. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of lib.axi4_to_ahb. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of lsu.lsu_bus_buffer. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dbg.dbg. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of ifu.ifu_mem_ctl. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dma_ctrl. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of ifu.ifu. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of lsu.lsu_bus_intf. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dbg.dbg. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of lsu.lsu_bus_buffer. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of lib.axi4_to_ahb. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dma_ctrl. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dec.dec_IO. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dec.dec. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of exu.exu. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of lib.ahb_to_axi4. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of lib.axi4_to_ahb. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of lsu.lsu_bus_buffer. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dbg.dbg. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of ifu.ifu_mem_ctl. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dma_ctrl. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of ifu.ifu. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of ifu.ifu. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of quasar_bundle. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of ifu.mem_ctl_io. This dependency is not being considered for invalidation. -[debug] The following modified names cause invalidation of quasar_wrapper: Set(UsedName(bridge_gen,[Default])) -[debug] None of the modified names appears in source file of mem.Mem_bundle. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of ifu.ifu_mem_ctl. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of lsu.lsu. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of exu.exu. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dec.dec. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of lsu.lsu. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of ifu.ifu_aln_ctl. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of ifu.ifu. This dependency is not being considered for invalidation. -[debug] The following modified names cause invalidation of quasar_wrapper: Set(UsedName(bridge_gen,[Default])) -[debug] None of the modified names appears in source file of dec.dec. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dec.dec_decode_ctl. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of lsu.lsu. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of lsu.lsu_bus_buffer. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of lsu.lsu_bus_intf. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of lib.ahb_to_axi4. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of lib.axi4_to_ahb. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of lsu.lsu_bus_buffer. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dbg.dbg. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of ifu.ifu_mem_ctl. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dma_ctrl. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of lib.axi4_to_ahb_IO. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of ifu.ifu. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of lsu.lsu. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of lib.ahb_to_axi4. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of lib.axi4_to_ahb. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of quasar_bundle. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of ifu.mem_ctl_io. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of lsu.lsu_bus_buffer. This dependency is not being considered for invalidation. -[debug] The following modified names cause invalidation of quasar_wrapper: Set(UsedName(bridge_gen,[Default])) -[debug] None of the modified names appears in source file of dbg.dbg. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of lsu.lsu_bus_intf. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of ifu.ifu_mem_ctl. This dependency is not being considered for invalidation. -[debug] The following modified names cause invalidation of lib.lib: Set(UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default])) -[debug] None of the modified names appears in source file of dma_ctrl. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dec.dec_decode_ctl. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of lsu.lsu. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of lsu.lsu. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of quasar_bundle. This dependency is not being considered for invalidation. -[debug] The following modified names cause invalidation of quasar_wrapper: Set(UsedName(bridge_gen,[Default])) -[debug] None of the modified names appears in source file of lsu.lsu_dccm_ctl. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dec.dec. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of ifu.ifu. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dec.dec_tlu_ctl_IO. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dec.dec_tlu_ctl. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of ifu.mem_ctl_io. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of ifu.ifu_mem_ctl. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of ifu.ifu. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of ifu.ifu. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dec.dec. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dec.dec_decode_ctl. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of exu.exu. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of lsu.lsu_clkdomain. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of exu.exu. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dec.dec_decode_ctl. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of lsu.lsu_trigger. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of include.exu_bp. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dec.dec_gpr_ctl. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of lsu.lsu_addrcheck. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of mem.quasar. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of include.dec_aln. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of ifu.ifu. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of include.aln_ib. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dec.dec_tlu_ctl_IO. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of exu.exu_div_ctl. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of lsu.lsu. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dec.dec_tlu_ctl. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of lib.ahb_to_axi4. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of lib.axi4_to_ahb. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dec.csr_tlu. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of lsu.lsu_lsc_ctl. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of pic_ctrl. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of include.write_data. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of exu.exu_alu_ctl. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of include.tlu_exu. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dec.dec_IO. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of include.iccm_mem. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of quasar_bundle. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of lsu.lsu_ecc. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of mem.blackbox_mem. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of include.write_addr. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of ifu.mem_ctl_io. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of lsu.lsu_bus_buffer. This dependency is not being considered for invalidation. -[debug] The following modified names cause invalidation of quasar_wrapper: Set(UsedName(bridge_gen,[Default])) -[debug] None of the modified names appears in source file of include.write_resp. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dec.CSR_IO. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dec.dec_timer_ctl. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of include.dec_exu. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of include.read_data. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of ifu.ifu_aln_ctl. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dbg.dbg. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of include.ic_mem. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of lsu.lsu_bus_intf. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of exu.exu_mul_ctl. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dec.dec_trigger. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of lsu.lsu_dccm_ctl. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of ifu.ifu_compress_ctl. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of ifu.ifu_bp_ctl. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of mem.Mem_bundle. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of include.dctl_busbuff. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of include.read_addr. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of include.axi_channels. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dec.dec_dec_ctl. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of lsu.lsu_stbuf. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of mem.mem_lsu. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of include.dec_mem_ctrl. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of ifu.ifu_mem_ctl. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of ifu.ifu_ifc_ctl. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of include.decode_exu. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dma_ctrl. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation. -[debug] Change NamesChange(lib.lib,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]))) invalidates 60 classes due to The lib.lib has the following regular definitions changed: -[debug]  UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]). -[debug]  > by transitive inheritance: Set(lsu.lsu_clkdomain, exu.exu, dec.dec_decode_ctl, lsu.lsu_trigger, include.exu_bp, dec.dec_gpr_ctl, lsu.lsu_addrcheck, mem.quasar, include.dec_aln, ifu.ifu, include.aln_ib, dec.dec_tlu_ctl_IO, exu.exu_div_ctl, lsu.lsu, dec.dec_tlu_ctl, lib.ahb_to_axi4, lib.axi4_to_ahb, quasar, dec.csr_tlu, lsu.lsu_lsc_ctl, pic_ctrl, include.write_data, exu.exu_alu_ctl, include.tlu_exu, dec.dec_IO, include.iccm_mem, quasar_bundle, lsu.lsu_ecc, mem.blackbox_mem, include.write_addr, ifu.mem_ctl_io, lsu.lsu_bus_buffer, quasar_wrapper, include.write_resp, dec.CSR_IO, dec.dec_timer_ctl, include.dec_exu, include.read_data, ifu.ifu_aln_ctl, dbg.dbg, include.ic_mem, lsu.lsu_bus_intf, exu.exu_mul_ctl, dec.dec_trigger, lsu.lsu_dccm_ctl, ifu.ifu_compress_ctl, ifu.ifu_bp_ctl, mem.Mem_bundle, include.dctl_busbuff, include.read_addr, include.axi_channels, dec.dec_dec_ctl, lsu.lsu_stbuf, mem.mem_lsu, include.dec_mem_ctrl, ifu.ifu_mem_ctl, ifu.ifu_ifc_ctl, include.decode_exu, lib.lib, dma_ctrl) -[debug]  >  -[debug]  > by member reference: Set(quasar_wrapper, lib.lib) -[debug]   -[debug] Invalidating (transitively) by inheritance from include.tlu_exu... -[debug] Initial set of included nodes: include.tlu_exu -[debug] Invalidated by transitive inheritance dependency: Set(include.tlu_exu) -[debug] None of the modified names appears in source file of dec.dec. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of exu.exu. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dec.dec_tlu_ctl_IO. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dec.dec_tlu_ctl. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation. -[debug] Change NamesChange(include.tlu_exu,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]))) invalidates 1 classes due to The include.tlu_exu has the following regular definitions changed: -[debug]  UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]). -[debug]  > by transitive inheritance: Set(include.tlu_exu) -[debug]  >  -[debug]  >  -[debug]   -[debug] Invalidating (transitively) by inheritance from include.dec_mem_ctrl... -[debug] Initial set of included nodes: include.dec_mem_ctrl -[debug] Invalidated by transitive inheritance dependency: Set(include.dec_mem_ctrl) -[debug] None of the modified names appears in source file of dec.dec. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of ifu.ifu. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dec.dec_tlu_ctl_IO. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dec.dec_tlu_ctl. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of ifu.mem_ctl_io. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of ifu.ifu_mem_ctl. This dependency is not being considered for invalidation. -[debug] Change NamesChange(include.dec_mem_ctrl,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]))) invalidates 1 classes due to The include.dec_mem_ctrl has the following regular definitions changed: -[debug]  UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]). -[debug]  > by transitive inheritance: Set(include.dec_mem_ctrl) -[debug]  >  -[debug]  >  -[debug]   -[debug] Invalidating (transitively) by inheritance from lsu.lsu_dccm_ctl... -[debug] Initial set of included nodes: lsu.lsu_dccm_ctl -[debug] Invalidated by transitive inheritance dependency: Set(lsu.lsu_dccm_ctl) -[debug] None of the modified names appears in source file of lsu.lsu. This dependency is not being considered for invalidation. -[debug] Change NamesChange(lsu.lsu_dccm_ctl,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]))) invalidates 1 classes due to The lsu.lsu_dccm_ctl has the following regular definitions changed: -[debug]  UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]). -[debug]  > by transitive inheritance: Set(lsu.lsu_dccm_ctl) -[debug]  >  -[debug]  >  -[debug]   -[debug] Invalidating (transitively) by inheritance from lsu.lsu_lsc_ctl... -[debug] Initial set of included nodes: lsu.lsu_lsc_ctl -[debug] Invalidated by transitive inheritance dependency: Set(lsu.lsu_lsc_ctl) -[debug] None of the modified names appears in source file of lsu.lsu. This dependency is not being considered for invalidation. -[debug] Change NamesChange(lsu.lsu_lsc_ctl,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]))) invalidates 1 classes due to The lsu.lsu_lsc_ctl has the following regular definitions changed: -[debug]  UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]). -[debug]  > by transitive inheritance: Set(lsu.lsu_lsc_ctl) -[debug]  >  -[debug]  >  -[debug]   -[debug] Invalidating (transitively) by inheritance from dec.csr_tlu... -[debug] Initial set of included nodes: dec.csr_tlu -[debug] Invalidated by transitive inheritance dependency: Set(dec.csr_tlu) -[debug] Change NamesChange(dec.csr_tlu,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]))) invalidates 1 classes due to The dec.csr_tlu has the following regular definitions changed: -[debug]  UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]). -[debug]  > by transitive inheritance: Set(dec.csr_tlu) -[debug]  >  -[debug]  >  -[debug]   -[debug] Invalidating (transitively) by inheritance from exu.exu... -[debug] Initial set of included nodes: exu.exu -[debug] Invalidated by transitive inheritance dependency: Set(exu.exu) -[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation. -[debug] Change NamesChange(exu.exu,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]))) invalidates 1 classes due to The exu.exu has the following regular definitions changed: -[debug]  UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]). -[debug]  > by transitive inheritance: Set(exu.exu) -[debug]  >  -[debug]  >  -[debug]   -[debug] Invalidating (transitively) by inheritance from include.dec_aln... -[debug] Initial set of included nodes: include.dec_aln -[debug] Invalidated by transitive inheritance dependency: Set(include.dec_aln) -[debug] None of the modified names appears in source file of ifu.ifu_aln_ctl. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of ifu.ifu. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dec.dec. This dependency is not being considered for invalidation. -[debug] Change NamesChange(include.dec_aln,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]))) invalidates 1 classes due to The include.dec_aln has the following regular definitions changed: -[debug]  UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]). -[debug]  > by transitive inheritance: Set(include.dec_aln) -[debug]  >  -[debug]  >  -[debug]   -[debug] Invalidating (transitively) by inheritance from ifu.ifu_compress_ctl... -[debug] Initial set of included nodes: ifu.ifu_compress_ctl -[debug] Invalidated by transitive inheritance dependency: Set(ifu.ifu_compress_ctl) -[debug] None of the modified names appears in source file of ifu.ifu_aln_ctl. This dependency is not being considered for invalidation. -[debug] Change NamesChange(ifu.ifu_compress_ctl,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]))) invalidates 1 classes due to The ifu.ifu_compress_ctl has the following regular definitions changed: -[debug]  UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]). -[debug]  > by transitive inheritance: Set(ifu.ifu_compress_ctl) -[debug]  >  -[debug]  >  -[debug]   -[debug] Invalidating (transitively) by inheritance from mem.mem_lsu... -[debug] Initial set of included nodes: mem.mem_lsu -[debug] Invalidated by transitive inheritance dependency: Set(mem.mem_lsu) -[debug] None of the modified names appears in source file of lsu.lsu. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of quasar_bundle. This dependency is not being considered for invalidation. -[debug] The following modified names cause invalidation of quasar_wrapper: Set(UsedName(bridge_gen,[Default])) -[debug] None of the modified names appears in source file of lsu.lsu_dccm_ctl. This dependency is not being considered for invalidation. -[debug] Change NamesChange(mem.mem_lsu,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]))) invalidates 2 classes due to The mem.mem_lsu has the following regular definitions changed: -[debug]  UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]). -[debug]  > by transitive inheritance: Set(mem.mem_lsu) -[debug]  >  -[debug]  > by member reference: Set(quasar_wrapper) -[debug]   -[debug] Invalidating (transitively) by inheritance from include.exu_bp... -[debug] Initial set of included nodes: include.exu_bp -[debug] Invalidated by transitive inheritance dependency: Set(include.exu_bp) -[debug] None of the modified names appears in source file of ifu.ifu_bp_ctl. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of ifu.ifu. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of exu.exu. This dependency is not being considered for invalidation. -[debug] Change NamesChange(include.exu_bp,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]))) invalidates 1 classes due to The include.exu_bp has the following regular definitions changed: -[debug]  UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]). -[debug]  > by transitive inheritance: Set(include.exu_bp) -[debug]  >  -[debug]  >  -[debug]   -[debug] Invalidating (transitively) by inheritance from mem.blackbox_mem... -[debug] Initial set of included nodes: mem.blackbox_mem -[debug] Invalidated by transitive inheritance dependency: Set(mem.blackbox_mem) -[debug] Change NamesChange(mem.blackbox_mem,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]))) invalidates 1 classes due to The mem.blackbox_mem has the following regular definitions changed: -[debug]  UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]). -[debug]  > by transitive inheritance: Set(mem.blackbox_mem) -[debug]  >  -[debug]  >  -[debug]   -[debug] Invalidating (transitively) by inheritance from quasar... -[debug] Initial set of included nodes: quasar -[debug] Invalidated by transitive inheritance dependency: Set(quasar) -[debug] The following modified names cause invalidation of quasar_wrapper: Set(UsedName(bridge_gen,[Default])) -[debug] Change NamesChange(quasar,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]))) invalidates 2 classes due to The quasar has the following regular definitions changed: -[debug]  UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]). -[debug]  > by transitive inheritance: Set(quasar) -[debug]  >  -[debug]  > by member reference: Set(quasar_wrapper) -[debug]   -[debug] Invalidating (transitively) by inheritance from mem.Mem_bundle... -[debug] Initial set of included nodes: mem.Mem_bundle -[debug] Invalidated by transitive inheritance dependency: Set(mem.Mem_bundle) -[debug] The following modified names cause invalidation of quasar_wrapper: Set(UsedName(bridge_gen,[Default])) -[debug] Change NamesChange(mem.Mem_bundle,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]))) invalidates 2 classes due to The mem.Mem_bundle has the following regular definitions changed: -[debug]  UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]). -[debug]  > by transitive inheritance: Set(mem.Mem_bundle) -[debug]  >  -[debug]  > by member reference: Set(quasar_wrapper) -[debug]   -[debug] Invalidating (transitively) by inheritance from include.ahb_out... -[debug] Initial set of included nodes: include.ahb_out -[debug] Invalidated by transitive inheritance dependency: Set(include.ahb_out) -[debug] The following member ref dependencies of include.ahb_out are invalidated: -[debug]  lib.ahb_to_axi4 -[debug]  lib.axi4_to_ahb -[debug] Change NamesChange(include.ahb_out,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(do_asUInt,[Default]), UsedName(instanceName,[Default]), UsedName(toTarget,[Default]), UsedName(suggestedName,[Default]), UsedName(notify,[Default]), UsedName(notifyAll,[Default]), UsedName(setRef,[Default]), UsedName(topBindingOpt,[Default]), UsedName(asInstanceOf,[Default]), UsedName(isLit,[Default]), UsedName(typeEquivalent,[Default]), UsedName(hmastlock,[Default]), UsedName(toString,[Default]), UsedName(direction_=,[Default]), UsedName(finalize,[Default]), UsedName(!=,[Default]), UsedName(isSynthesizable,[Default]), UsedName(synchronized,[Default]), UsedName(topBinding,[Default]), UsedName(include;ahb_out;init;,[Default]), UsedName(asUInt,[Default]), UsedName(pathName,[Default]), UsedName(specifiedDirection,[Default]), UsedName(wait,[Default]), UsedName(getPublicFields,[Default]), UsedName(##,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(width,[Default]), UsedName(ne,[Default]), UsedName(ref,[Default]), UsedName(elements,[Default]), UsedName(equals,[Default]), UsedName(hsize,[Default]), UsedName(bulkConnect,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(htrans,[Default]), UsedName(==,[Default]), UsedName(suggestName,[Default]), UsedName(parentModName,[Default]), UsedName(flatten,[Default]), UsedName(hburst,[Default]), UsedName(binding_=,[Default]), UsedName(_makeLit,[Default]), UsedName(bind$default$2,[Default]), UsedName(parentPathName,[Default]), UsedName(isInstanceOf,[Default]), UsedName(compileOptions,[Implicit]), UsedName($isInstanceOf,[Default]), UsedName(getOptionRef,[Default]), UsedName(className,[Default]), UsedName(widthOption,[Default]), UsedName($init$,[Default]), UsedName(getElements,[Default]), UsedName(connectFromBits,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(ignoreSeq,[Default]), UsedName(circuitName,[Default]), UsedName(binding,[Default]), UsedName(<>,[Default]), UsedName(litArg,[Default]), UsedName(hprot,[Default]), UsedName(_onModuleClose,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(lref,[Default]), UsedName(litOption,[Default]), UsedName(allElements,[Default]), UsedName(connect,[Default]), UsedName(bind,[Default]), UsedName(getRef,[Default]), UsedName(getWidth,[Default]), UsedName(addPostnameHook,[Default]), UsedName(litValue,[Default]), UsedName(hashCode,[Default]), UsedName(cloneType,[Default]), UsedName(_parent,[Default]), UsedName(eq,[Default]), UsedName(ahb_out,[Default]), UsedName(:=,[Default]), UsedName(bindingToString,[Default]), UsedName(clone,[Default]), UsedName(_id,[Default]), UsedName(hwdata,[Default]), UsedName(isWidthKnown,[Default]), UsedName(getClass,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(toPrintable,[Default]), UsedName(forceName,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(direction,[Default]), UsedName($asInstanceOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(haddr,[Default]), UsedName(toNamed,[Default]), UsedName(hwrite,[Default]), UsedName(badConnect,[Default]))) invalidates 3 classes due to The include.ahb_out has the following implicit definitions changed: -[debug]  UsedName(compileOptions,[Implicit]). -[debug]  > by transitive inheritance: Set(include.ahb_out) -[debug]  >  -[debug]  > by member reference: Set(lib.ahb_to_axi4, lib.axi4_to_ahb) -[debug]   -[debug] Invalidating (transitively) by inheritance from include.ahb_in... -[debug] Initial set of included nodes: include.ahb_in -[debug] Invalidated by transitive inheritance dependency: Set(include.ahb_in) -[debug] The following member ref dependencies of include.ahb_in are invalidated: -[debug]  lib.ahb_to_axi4 -[debug]  lib.axi4_to_ahb -[debug] Change NamesChange(include.ahb_in,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(do_asUInt,[Default]), UsedName(hresp,[Default]), UsedName(instanceName,[Default]), UsedName(toTarget,[Default]), UsedName(suggestedName,[Default]), UsedName(notify,[Default]), UsedName(notifyAll,[Default]), UsedName(setRef,[Default]), UsedName(topBindingOpt,[Default]), UsedName(asInstanceOf,[Default]), UsedName(isLit,[Default]), UsedName(typeEquivalent,[Default]), UsedName(toString,[Default]), UsedName(direction_=,[Default]), UsedName(finalize,[Default]), UsedName(!=,[Default]), UsedName(isSynthesizable,[Default]), UsedName(synchronized,[Default]), UsedName(topBinding,[Default]), UsedName(asUInt,[Default]), UsedName(pathName,[Default]), UsedName(specifiedDirection,[Default]), UsedName(wait,[Default]), UsedName(hready,[Default]), UsedName(include;ahb_in;init;,[Default]), UsedName(getPublicFields,[Default]), UsedName(##,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(width,[Default]), UsedName(ne,[Default]), UsedName(hrdata,[Default]), UsedName(ref,[Default]), UsedName(elements,[Default]), UsedName(equals,[Default]), UsedName(bulkConnect,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(==,[Default]), UsedName(suggestName,[Default]), UsedName(parentModName,[Default]), UsedName(flatten,[Default]), UsedName(binding_=,[Default]), UsedName(_makeLit,[Default]), UsedName(bind$default$2,[Default]), UsedName(parentPathName,[Default]), UsedName(isInstanceOf,[Default]), UsedName(compileOptions,[Implicit]), UsedName($isInstanceOf,[Default]), UsedName(getOptionRef,[Default]), UsedName(className,[Default]), UsedName(widthOption,[Default]), UsedName($init$,[Default]), UsedName(getElements,[Default]), UsedName(connectFromBits,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(ignoreSeq,[Default]), UsedName(circuitName,[Default]), UsedName(binding,[Default]), UsedName(<>,[Default]), UsedName(litArg,[Default]), UsedName(_onModuleClose,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(lref,[Default]), UsedName(litOption,[Default]), UsedName(allElements,[Default]), UsedName(connect,[Default]), UsedName(bind,[Default]), UsedName(getRef,[Default]), UsedName(getWidth,[Default]), UsedName(addPostnameHook,[Default]), UsedName(litValue,[Default]), UsedName(hashCode,[Default]), UsedName(cloneType,[Default]), UsedName(_parent,[Default]), UsedName(eq,[Default]), UsedName(:=,[Default]), UsedName(bindingToString,[Default]), UsedName(clone,[Default]), UsedName(_id,[Default]), UsedName(isWidthKnown,[Default]), UsedName(ahb_in,[Default]), UsedName(getClass,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(toPrintable,[Default]), UsedName(forceName,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(direction,[Default]), UsedName($asInstanceOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(toNamed,[Default]), UsedName(badConnect,[Default]))) invalidates 3 classes due to The include.ahb_in has the following implicit definitions changed: -[debug]  UsedName(compileOptions,[Implicit]). -[debug]  > by transitive inheritance: Set(include.ahb_in) -[debug]  >  -[debug]  > by member reference: Set(lib.ahb_to_axi4, lib.axi4_to_ahb) -[debug]   -[debug] Invalidating (transitively) by inheritance from lsu.lsu_bus_intf... -[debug] Initial set of included nodes: lsu.lsu_bus_intf -[debug] Invalidated by transitive inheritance dependency: Set(lsu.lsu_bus_intf) -[debug] None of the modified names appears in source file of lsu.lsu. This dependency is not being considered for invalidation. -[debug] Change NamesChange(lsu.lsu_bus_intf,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]))) invalidates 1 classes due to The lsu.lsu_bus_intf has the following regular definitions changed: -[debug]  UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]). -[debug]  > by transitive inheritance: Set(lsu.lsu_bus_intf) -[debug]  >  -[debug]  >  -[debug]   -[debug] Invalidating (transitively) by inheritance from include.dctl_busbuff... -[debug] Initial set of included nodes: include.dctl_busbuff -[debug] Invalidated by transitive inheritance dependency: Set(include.dctl_busbuff) -[debug] None of the modified names appears in source file of dec.dec. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dec.dec_decode_ctl. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of lsu.lsu. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of lsu.lsu_bus_buffer. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of lsu.lsu_bus_intf. This dependency is not being considered for invalidation. -[debug] Change NamesChange(include.dctl_busbuff,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]))) invalidates 1 classes due to The include.dctl_busbuff has the following regular definitions changed: -[debug]  UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]). -[debug]  > by transitive inheritance: Set(include.dctl_busbuff) -[debug]  >  -[debug]  >  -[debug]   -[debug] Invalidating (transitively) by inheritance from quasar_wrapper... -[debug] Initial set of included nodes: quasar_wrapper -[debug] Invalidated by transitive inheritance dependency: Set(quasar_wrapper) -[debug] Change NamesChange(quasar_wrapper,ModifiedNames(changes = UsedName(dma_hsize,[Default]), UsedName(dma_axi,[Default]), UsedName(dma_hreadyout,[Default]), UsedName(dma_hresp,[Default]), UsedName(ifu_brg,[Default]), UsedName(dma_htrans,[Default]), UsedName(bridge_gen,[Default]), UsedName(lsu_axi,[Default]), UsedName(sb_brg,[Default]), UsedName(dma_hsel,[Default]), UsedName(sb_axi,[Default]), UsedName(ahb_bridge_gen,[Default]), UsedName(dma_hburst,[Default]), UsedName(flip,[Default]), UsedName(dma_haddr,[Default]), UsedName(ifu_axi,[Default]), UsedName(dma_hmastlock,[Default]), UsedName(lsu_brg,[Default]), UsedName(dma_hrdata,[Default]), UsedName(io,[Default]), UsedName(dma_hwrite,[Default]), UsedName(dma_brg,[Default]), UsedName(dma_hwdata,[Default]), UsedName(dma_hreadyin,[Default]), UsedName(dma_hprot,[Default]))) invalidates 1 classes due to The quasar_wrapper has the following regular definitions changed: -[debug]  UsedName(dma_hsize,[Default]), UsedName(dma_axi,[Default]), UsedName(dma_hreadyout,[Default]), UsedName(dma_hresp,[Default]), UsedName(ifu_brg,[Default]), UsedName(dma_htrans,[Default]), UsedName(bridge_gen,[Default]), UsedName(lsu_axi,[Default]), UsedName(sb_brg,[Default]), UsedName(dma_hsel,[Default]), UsedName(sb_axi,[Default]), UsedName(ahb_bridge_gen,[Default]), UsedName(dma_hburst,[Default]), UsedName(flip,[Default]), UsedName(dma_haddr,[Default]), UsedName(ifu_axi,[Default]), UsedName(dma_hmastlock,[Default]), UsedName(lsu_brg,[Default]), UsedName(dma_hrdata,[Default]), UsedName(io,[Default]), UsedName(dma_hwrite,[Default]), UsedName(dma_brg,[Default]), UsedName(dma_hwdata,[Default]), UsedName(dma_hreadyin,[Default]), UsedName(dma_hprot,[Default]). -[debug]  > by transitive inheritance: Set(quasar_wrapper) -[debug]  >  -[debug]  >  -[debug]   -[debug] Invalidating (transitively) by inheritance from lsu.lsu_clkdomain... -[debug] Initial set of included nodes: lsu.lsu_clkdomain -[debug] Invalidated by transitive inheritance dependency: Set(lsu.lsu_clkdomain) -[debug] None of the modified names appears in source file of lsu.lsu. This dependency is not being considered for invalidation. -[debug] Change NamesChange(lsu.lsu_clkdomain,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]))) invalidates 1 classes due to The lsu.lsu_clkdomain has the following regular definitions changed: -[debug]  UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]). -[debug]  > by transitive inheritance: Set(lsu.lsu_clkdomain) -[debug]  >  -[debug]  >  -[debug]   -[debug] Invalidating (transitively) by inheritance from include.read_data... -[debug] Initial set of included nodes: include.read_data -[debug] Invalidated by transitive inheritance dependency: Set(include.read_data) -[debug] The following modified names cause invalidation of lib.ahb_to_axi4: Set(UsedName(asInstanceOf,[Default]), UsedName(read_data,[Default]), UsedName(ne,[Default]), UsedName(==,[Default]), UsedName(isInstanceOf,[Default])) -[debug] The following modified names cause invalidation of lib.axi4_to_ahb: Set(UsedName(asInstanceOf,[Default]), UsedName(read_data,[Default]), UsedName(==,[Default]), UsedName(isInstanceOf,[Default])) -[debug] The following modified names cause invalidation of lsu.lsu_bus_buffer: Set(UsedName(asInstanceOf,[Default]), UsedName(read_data,[Default]), UsedName(==,[Default]), UsedName(isInstanceOf,[Default])) -[debug] The following modified names cause invalidation of dbg.dbg: Set(UsedName(read_data,[Default])) -[debug] The following modified names cause invalidation of ifu.ifu_mem_ctl: Set(UsedName(asInstanceOf,[Default]), UsedName(read_data,[Default]), UsedName(==,[Default]), UsedName(isInstanceOf,[Default])) -[debug] The following modified names cause invalidation of dma_ctrl: Set(UsedName(read_data,[Default]), UsedName(ne,[Default])) -[debug] Change NamesChange(include.read_data,ModifiedNames(changes = UsedName(include;read_data;init;,[Default]), UsedName(notify,[Default]), UsedName(notifyAll,[Default]), UsedName(asInstanceOf,[Default]), UsedName(toString,[Default]), UsedName(finalize,[Default]), UsedName(!=,[Default]), UsedName(synchronized,[Default]), UsedName(wait,[Default]), UsedName(read_data,[Default]), UsedName(##,[Default]), UsedName(ne,[Default]), UsedName(equals,[Default]), UsedName(bridge_gen,[Default]), UsedName(==,[Default]), UsedName($default$1,[Default]), UsedName(isInstanceOf,[Default]), UsedName($isInstanceOf,[Default]), UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(hashCode,[Default]), UsedName(eq,[Default]), UsedName(clone,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]))) invalidates 7 classes due to The include.read_data has the following regular definitions changed: -[debug]  UsedName(include;read_data;init;,[Default]), UsedName(notify,[Default]), UsedName(notifyAll,[Default]), UsedName(asInstanceOf,[Default]), UsedName(toString,[Default]), UsedName(finalize,[Default]), UsedName(!=,[Default]), UsedName(synchronized,[Default]), UsedName(wait,[Default]), UsedName(read_data,[Default]), UsedName(##,[Default]), UsedName(ne,[Default]), UsedName(equals,[Default]), UsedName(bridge_gen,[Default]), UsedName(==,[Default]), UsedName($default$1,[Default]), UsedName(isInstanceOf,[Default]), UsedName($isInstanceOf,[Default]), UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(hashCode,[Default]), UsedName(eq,[Default]), UsedName(clone,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]). -[debug]  > by transitive inheritance: Set(include.read_data) -[debug]  >  -[debug]  > by member reference: Set(lib.ahb_to_axi4, lib.axi4_to_ahb, lsu.lsu_bus_buffer, dbg.dbg, ifu.ifu_mem_ctl, dma_ctrl) -[debug]   -[debug] Invalidating (transitively) by inheritance from include.write_data... -[debug] Initial set of included nodes: include.write_data -[debug] Invalidated by transitive inheritance dependency: Set(include.write_data) -[debug] None of the modified names appears in source file of lib.ahb_to_axi4. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of lib.axi4_to_ahb. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of lsu.lsu_bus_buffer. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dbg.dbg. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of ifu.ifu_mem_ctl. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dma_ctrl. This dependency is not being considered for invalidation. -[debug] Change NamesChange(include.write_data,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]))) invalidates 1 classes due to The include.write_data has the following regular definitions changed: -[debug]  UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]). -[debug]  > by transitive inheritance: Set(include.write_data) -[debug]  >  -[debug]  >  -[debug]   -[debug] Invalidating (transitively) by inheritance from include.dec_exu... -[debug] Initial set of included nodes: include.dec_exu -[debug] Invalidated by transitive inheritance dependency: Set(include.dec_exu) -[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dec.dec_IO. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of dec.dec. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of exu.exu. This dependency is not being considered for invalidation. -[debug] Change NamesChange(include.dec_exu,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]))) invalidates 1 classes due to The include.dec_exu has the following regular definitions changed: -[debug]  UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]). -[debug]  > by transitive inheritance: Set(include.dec_exu) -[debug]  >  -[debug]  >  -[debug]   -[debug] Invalidating (transitively) by inheritance from ifu.ifu_ifc_ctl... -[debug] Initial set of included nodes: ifu.ifu_ifc_ctl -[debug] Invalidated by transitive inheritance dependency: Set(ifu.ifu_ifc_ctl) -[debug] None of the modified names appears in source file of ifu.ifu. This dependency is not being considered for invalidation. -[debug] Change NamesChange(ifu.ifu_ifc_ctl,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]))) invalidates 1 classes due to The ifu.ifu_ifc_ctl has the following regular definitions changed: -[debug]  UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]). -[debug]  > by transitive inheritance: Set(ifu.ifu_ifc_ctl) -[debug]  >  -[debug]  >  -[debug]   -[debug] Invalidating (transitively) by inheritance from include.axi_channels... -[debug] Initial set of included nodes: include.axi_channels -[debug] Invalidated by transitive inheritance dependency: Set(include.axi_channels) -[debug] None of the modified names appears in source file of lib.axi4_to_ahb_IO. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of ifu.ifu. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of lsu.lsu. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of lib.ahb_to_axi4. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of lib.axi4_to_ahb. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of quasar_bundle. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of ifu.mem_ctl_io. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of lsu.lsu_bus_buffer. This dependency is not being considered for invalidation. -[debug] The following modified names cause invalidation of quasar_wrapper: Set(UsedName(bridge_gen,[Default])) -[debug] None of the modified names appears in source file of dbg.dbg. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of lsu.lsu_bus_intf. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of ifu.ifu_mem_ctl. This dependency is not being considered for invalidation. -[debug] The following modified names cause invalidation of lib.lib: Set(UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default])) -[debug] None of the modified names appears in source file of dma_ctrl. This dependency is not being considered for invalidation. -[debug] Change NamesChange(include.axi_channels,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]))) invalidates 3 classes due to The include.axi_channels has the following regular definitions changed: -[debug]  UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]). -[debug]  > by transitive inheritance: Set(include.axi_channels) -[debug]  >  -[debug]  > by member reference: Set(quasar_wrapper, lib.lib) -[debug]   -[debug] Invalidating (transitively) by inheritance from ifu.ifu_bp_ctl... -[debug] Initial set of included nodes: ifu.ifu_bp_ctl -[debug] Invalidated by transitive inheritance dependency: Set(ifu.ifu_bp_ctl) -[debug] None of the modified names appears in source file of ifu.ifu. This dependency is not being considered for invalidation. -[debug] Change NamesChange(ifu.ifu_bp_ctl,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]))) invalidates 1 classes due to The ifu.ifu_bp_ctl has the following regular definitions changed: -[debug]  UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]). -[debug]  > by transitive inheritance: Set(ifu.ifu_bp_ctl) -[debug]  >  -[debug]  >  -[debug]   -[debug] Invalidating (transitively) by inheritance from lsu.lsu_trigger... -[debug] Initial set of included nodes: lsu.lsu_trigger -[debug] Invalidated by transitive inheritance dependency: Set(lsu.lsu_trigger) -[debug] None of the modified names appears in source file of lsu.lsu. This dependency is not being considered for invalidation. -[debug] Change NamesChange(lsu.lsu_trigger,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]))) invalidates 1 classes due to The lsu.lsu_trigger has the following regular definitions changed: -[debug]  UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]). -[debug]  > by transitive inheritance: Set(lsu.lsu_trigger) -[debug]  >  -[debug]  >  -[debug]   -[debug] Invalidating (transitively) by inheritance from dbg.dbg... -[debug] Initial set of included nodes: dbg.dbg -[debug] Invalidated by transitive inheritance dependency: Set(dbg.dbg) -[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation. -[debug] Change NamesChange(dbg.dbg,ModifiedNames(changes = UsedName(dbg_dm_rst_l,[Default]), UsedName(rst_not,[Default]), UsedName(bridge_gen,[Default]), UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(rst_temp,[Default]))) invalidates 1 classes due to The dbg.dbg has the following regular definitions changed: -[debug]  UsedName(dbg_dm_rst_l,[Default]), UsedName(rst_not,[Default]), UsedName(bridge_gen,[Default]), UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(rst_temp,[Default]). -[debug]  > by transitive inheritance: Set(dbg.dbg) -[debug]  >  -[debug]  >  -[debug]   -[debug] New invalidations: -[debug]  Set() -[debug] Initial set of included nodes:  -[debug] Previously invalidated, but (transitively) depend on new invalidations: -[debug]  Set() -[debug] No classes were invalidated. +[debug] No changes diff --git a/target/streams/compile/copyResources/_global/streams/copy-resources b/target/streams/compile/copyResources/_global/streams/copy-resources index 1d20d3ea..fdbe99bb 100644 --- a/target/streams/compile/copyResources/_global/streams/copy-resources +++ b/target/streams/compile/copyResources/_global/streams/copy-resources @@ -1 +1 @@ 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\ No newline at end of file diff --git a/target/streams/compile/copyResources/_global/streams/out b/target/streams/compile/copyResources/_global/streams/out index 86bb6e4a..613c3ffb 100644 --- a/target/streams/compile/copyResources/_global/streams/out +++ b/target/streams/compile/copyResources/_global/streams/out @@ -1,14 +1,14 @@ [debug] Copy resource mappings:  -[debug]  (/home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/ifu_iccm_mem.sv,/home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/ifu_iccm_mem.sv) -[debug]  (/home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/dmi_wrapper.sv,/home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/dmi_wrapper.sv) -[debug]  (/home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/dmi_jtag_to_core_sync.sv,/home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/dmi_jtag_to_core_sync.sv) -[debug]  (/home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/gated_latch.v,/home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/gated_latch.v) -[debug]  (/home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/beh_lib.sv,/home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/beh_lib.sv) -[debug]  (/home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/lsu_dccm_mem.sv,/home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/lsu_dccm_mem.sv) -[debug]  (/home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/rvtaj_tap.sv,/home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/rvtaj_tap.sv) -[debug]  (/home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/gated_latch.sv,/home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/gated_latch.sv) -[debug]  (/home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/rvjtag_tap.sv,/home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/rvjtag_tap.sv) -[debug]  (/home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/mem.sv,/home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/mem.sv) -[debug]  (/home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/mem_lib.sv,/home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/mem_lib.sv) -[debug]  (/home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/mem_mod.sv,/home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/mem_mod.sv) -[debug]  (/home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/ifu_ic_mem.sv,/home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/ifu_ic_mem.sv) +[debug]  (/home/abdulhameed.akram/Videos/Quasar/src/main/resources/vsrc/ifu_iccm_mem.sv,/home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/vsrc/ifu_iccm_mem.sv) +[debug]  (/home/abdulhameed.akram/Videos/Quasar/src/main/resources/vsrc/gated_latch.v,/home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/vsrc/gated_latch.v) +[debug]  (/home/abdulhameed.akram/Videos/Quasar/src/main/resources/vsrc/dmi_jtag_to_core_sync.sv,/home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/vsrc/dmi_jtag_to_core_sync.sv) +[debug]  (/home/abdulhameed.akram/Videos/Quasar/src/main/resources/vsrc/lsu_dccm_mem.sv,/home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/vsrc/lsu_dccm_mem.sv) +[debug]  (/home/abdulhameed.akram/Videos/Quasar/src/main/resources/vsrc/dmi_wrapper.sv,/home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/vsrc/dmi_wrapper.sv) +[debug]  (/home/abdulhameed.akram/Videos/Quasar/src/main/resources/vsrc/gated_latch.sv,/home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/vsrc/gated_latch.sv) +[debug]  (/home/abdulhameed.akram/Videos/Quasar/src/main/resources/vsrc/rvjtag_tap.sv,/home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/vsrc/rvjtag_tap.sv) +[debug]  (/home/abdulhameed.akram/Videos/Quasar/src/main/resources/vsrc/rvtaj_tap.sv,/home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/vsrc/rvtaj_tap.sv) +[debug]  (/home/abdulhameed.akram/Videos/Quasar/src/main/resources/vsrc/mem.sv,/home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/vsrc/mem.sv) +[debug]  (/home/abdulhameed.akram/Videos/Quasar/src/main/resources/vsrc/mem_mod.sv,/home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/vsrc/mem_mod.sv) +[debug]  (/home/abdulhameed.akram/Videos/Quasar/src/main/resources/vsrc/beh_lib.sv,/home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/vsrc/beh_lib.sv) +[debug]  (/home/abdulhameed.akram/Videos/Quasar/src/main/resources/vsrc/mem_lib.sv,/home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/vsrc/mem_lib.sv) +[debug]  (/home/abdulhameed.akram/Videos/Quasar/src/main/resources/vsrc/ifu_ic_mem.sv,/home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/vsrc/ifu_ic_mem.sv) diff --git a/target/streams/compile/dependencyClasspath/_global/streams/export b/target/streams/compile/dependencyClasspath/_global/streams/export index 414eb951..58921df4 100644 --- a/target/streams/compile/dependencyClasspath/_global/streams/export +++ b/target/streams/compile/dependencyClasspath/_global/streams/export @@ -1 +1 @@ -/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar +/home/abdulhameed.akram/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/abdulhameed.akram/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar diff --git a/target/streams/compile/exportedProductJars/_global/streams/export b/target/streams/compile/exportedProductJars/_global/streams/export index 230f8ab4..ab1754f8 100644 --- a/target/streams/compile/exportedProductJars/_global/streams/export +++ b/target/streams/compile/exportedProductJars/_global/streams/export @@ -1 +1 @@ -/home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar +/home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar diff --git a/target/streams/compile/exportedProducts/_global/streams/export b/target/streams/compile/exportedProducts/_global/streams/export index 804ab82b..2f56444e 100644 --- a/target/streams/compile/exportedProducts/_global/streams/export +++ b/target/streams/compile/exportedProducts/_global/streams/export @@ -1 +1 @@ -/home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes +/home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes diff --git a/target/streams/compile/packageBin/_global/streams/inputs b/target/streams/compile/packageBin/_global/streams/inputs index a7c00c6a..72822392 100644 --- a/target/streams/compile/packageBin/_global/streams/inputs +++ b/target/streams/compile/packageBin/_global/streams/inputs @@ -1 +1 @@ -793527455 \ No newline at end of file +-629737911 \ No newline at end of file diff --git a/target/streams/compile/packageBin/_global/streams/out b/target/streams/compile/packageBin/_global/streams/out index 2047205e..3971eae1 100644 --- a/target/streams/compile/packageBin/_global/streams/out +++ b/target/streams/compile/packageBin/_global/streams/out @@ -1,421 +1 @@ -[debug] Packaging /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar ... -[debug] Input file mappings: -[debug]  pic_ctrl$$anon$1.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/pic_ctrl$$anon$1.class -[debug]  QUASAR_Wrp$delayedInit$body.class -[debug]  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/home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/ccm_ext_in_pkt_t.class -[debug]  include/dbg_dctl.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dbg_dctl.class -[debug]  include/dec_div.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dec_div.class -[debug]  include/dec_exu.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dec_exu.class -[debug]  include/decode_exu.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/decode_exu.class -[debug]  include/dec_dma.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dec_dma.class -[debug]  include/ic_data_ext_in_pkt_t.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/ic_data_ext_in_pkt_t.class -[debug]  include/dec_ifc.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dec_ifc.class -[debug]  include/ifu_dec.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/ifu_dec.class -[debug]  include/ahb_channel.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/ahb_channel.class -[debug]  include/lsu_pic.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/lsu_pic.class -[debug]  include/dctl_busbuff.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dctl_busbuff.class -[debug]  include/dec_aln.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dec_aln.class -[debug]  include/dma_ifc.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dma_ifc.class -[debug]  include/dccm_ext_in_pkt_t.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dccm_ext_in_pkt_t.class -[debug]  include/ifu_dma.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/ifu_dma.class -[debug]  include/br_pkt_t.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/br_pkt_t.class -[debug]  include/lsu_tlu.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/lsu_tlu.class -[debug]  include/dec_pkt_t.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dec_pkt_t.class -[debug]  include/aln_ib.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/aln_ib.class -[debug]  include/cache_debug_pkt_t.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/cache_debug_pkt_t.class -[debug]  include/load_cam_pkt_t.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/load_cam_pkt_t.class -[debug]  include/dec_mem_ctrl.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dec_mem_ctrl.class -[debug]  include/ahb_in.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/ahb_in.class -[debug]  include/axi_channels$.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/axi_channels$.class -[debug]  include/ic_tag_ext_in_pkt_t.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/ic_tag_ext_in_pkt_t.class -[debug]  include/gpr_exu.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/gpr_exu.class -[debug]  include/inst_pkt_t.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/inst_pkt_t.class -[debug]  include/dec_bp.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dec_bp.class -[debug]  include/dec_pic.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dec_pic.class -[debug]  include/lsu_exu.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/lsu_exu.class -[debug]  include/lsu_dma.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/lsu_dma.class -[debug]  include/class_pkt_t.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/class_pkt_t.class -[debug]  include/dma_mem_ctl.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dma_mem_ctl.class -[debug]  include/dec_dbg.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dec_dbg.class -[debug]  include/dma_dccm_ctl.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dma_dccm_ctl.class -[debug]  include/predict_pkt_t.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/predict_pkt_t.class -[debug]  include/br_tlu_pkt_t.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/br_tlu_pkt_t.class -[debug]  include/exu_bp.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/exu_bp.class -[debug]  include/dec_tlu_csr_pkt.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dec_tlu_csr_pkt.class -[debug]  include/trigger_pkt_t.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/trigger_pkt_t.class -[debug]  include/dec_alu.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dec_alu.class -[debug]  include/lsu_dec.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/lsu_dec.class -[debug]  include/read_data.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/read_data.class -[debug]  include/write_data.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/write_data.class -[debug]  include/alu_pkt_t.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/alu_pkt_t.class -[debug]  include/rets_pkt_t.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/rets_pkt_t.class -[debug]  dec -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec -[debug]  dec/dec_trigger$$anon$1.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_trigger$$anon$1.class -[debug]  dec/dec_IO.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_IO.class -[debug]  dec/CSR_VAL.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/CSR_VAL.class -[debug]  dec/dec_ib_ctl_IO.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_ib_ctl_IO.class -[debug]  dec/dec_tlu_ctl.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_tlu_ctl.class -[debug]  dec/dec_timer_ctl.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_timer_ctl.class -[debug]  dec/dec_dec_ctl$$anon$1.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_dec_ctl$$anon$1.class -[debug]  dec/dec_gpr_ctl_IO.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_gpr_ctl_IO.class -[debug]  dec/dec_ib_ctl.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_ib_ctl.class -[debug]  dec/CSR_IO.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/CSR_IO.class -[debug]  dec/dec_decode_ctl$$anon$1.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_decode_ctl$$anon$1.class -[debug]  dec/dec_decode_csr_read.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_decode_csr_read.class -[debug]  dec/dec.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec.class -[debug]  dec/dec_decode_ctl.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_decode_ctl.class -[debug]  dec/dec_trigger.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_trigger.class -[debug]  dec/csr_tlu.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/csr_tlu.class -[debug]  dec/dec_dec_ctl.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_dec_ctl.class -[debug]  dec/dec_gpr_ctl.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_gpr_ctl.class -[debug]  dec/CSRs.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/CSRs.class -[debug]  dec/dec_decode_csr_read_IO.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_decode_csr_read_IO.class -[debug]  dec/dec_tlu_ctl_IO.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_tlu_ctl_IO.class -[debug]  dec/dec_timer_ctl_IO.class -[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_timer_ctl_IO.class -[debug] Done packaging. +[debug] Jar uptodate: /home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar diff --git a/target/streams/compile/packageBin/_global/streams/output b/target/streams/compile/packageBin/_global/streams/output index ae20b88a..3e238bb9 100644 --- a/target/streams/compile/packageBin/_global/streams/output +++ b/target/streams/compile/packageBin/_global/streams/output @@ -1 +1 @@ --1025085726 \ No newline at end of file +333153426 \ No newline at end of file diff --git a/target/streams/runtime/dependencyClasspathAsJars/_global/streams/export b/target/streams/runtime/dependencyClasspathAsJars/_global/streams/export index b40c29ac..5a4177ae 100644 --- a/target/streams/runtime/dependencyClasspathAsJars/_global/streams/export +++ b/target/streams/runtime/dependencyClasspathAsJars/_global/streams/export @@ -1 +1 @@ -/home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar +/home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar:/home/abdulhameed.akram/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/abdulhameed.akram/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar diff --git a/target/streams/runtime/exportedProductJars/_global/streams/export b/target/streams/runtime/exportedProductJars/_global/streams/export index 230f8ab4..ab1754f8 100644 --- a/target/streams/runtime/exportedProductJars/_global/streams/export +++ b/target/streams/runtime/exportedProductJars/_global/streams/export @@ -1 +1 @@ -/home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar +/home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar diff --git a/target/streams/runtime/fullClasspathAsJars/_global/streams/export b/target/streams/runtime/fullClasspathAsJars/_global/streams/export index b40c29ac..5a4177ae 100644 --- a/target/streams/runtime/fullClasspathAsJars/_global/streams/export +++ b/target/streams/runtime/fullClasspathAsJars/_global/streams/export @@ -1 +1 @@ -/home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar 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diff --git a/target/streams/runtime/internalDependencyAsJars/_global/streams/export b/target/streams/runtime/internalDependencyAsJars/_global/streams/export index 230f8ab4..ab1754f8 100644 --- a/target/streams/runtime/internalDependencyAsJars/_global/streams/export +++ b/target/streams/runtime/internalDependencyAsJars/_global/streams/export @@ -1 +1 @@ -/home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar +/home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar

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