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Aligner Updated

This commit is contained in:
waleed-lm 2020-10-13 15:15:02 +05:00
parent 74c995180c
commit 7ee61fb920
4 changed files with 8 additions and 7 deletions
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4
el2_ifu_aln_ctl.fir
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@ -2618,11 +2618,11 @@ circuit el2_ifu_aln_ctl :
node f1pc_plus1 = tail(_T_362, 1) @[el2_ifu_aln_ctl.scala 277:25] node f1pc_plus1 = tail(_T_362, 1) @[el2_ifu_aln_ctl.scala 277:25]
node _T_363 = bits(f1_shift_2B, 0, 0) @[Bitwise.scala 72:15] node _T_363 = bits(f1_shift_2B, 0, 0) @[Bitwise.scala 72:15]
node _T_364 = mux(_T_363, UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12] node _T_364 = mux(_T_363, UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12]
node _T_365 = and(_T_364, f0pc_plus1) @[el2_ifu_aln_ctl.scala 279:38] node _T_365 = and(_T_364, f1pc_plus1) @[el2_ifu_aln_ctl.scala 279:38]
node _T_366 = eq(f1_shift_2B, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 279:64] node _T_366 = eq(f1_shift_2B, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 279:64]
node _T_367 = bits(_T_366, 0, 0) @[Bitwise.scala 72:15] node _T_367 = bits(_T_366, 0, 0) @[Bitwise.scala 72:15]
node _T_368 = mux(_T_367, UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12] node _T_368 = mux(_T_367, UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12]
node _T_369 = and(_T_368, f0pc) @[el2_ifu_aln_ctl.scala 279:78] node _T_369 = and(_T_368, f1pc) @[el2_ifu_aln_ctl.scala 279:78]
node sf1pc = or(_T_365, _T_369) @[el2_ifu_aln_ctl.scala 279:52] node sf1pc = or(_T_365, _T_369) @[el2_ifu_aln_ctl.scala 279:52]
node _T_370 = bits(fetch_to_f1, 0, 0) @[el2_ifu_aln_ctl.scala 281:36] node _T_370 = bits(fetch_to_f1, 0, 0) @[el2_ifu_aln_ctl.scala 281:36]
node _T_371 = bits(shift_f2_f1, 0, 0) @[el2_ifu_aln_ctl.scala 282:17] node _T_371 = bits(shift_f2_f1, 0, 0) @[el2_ifu_aln_ctl.scala 282:17]

9
el2_ifu_aln_ctl.v
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@ -691,11 +691,10 @@ module el2_ifu_aln_ctl(
wire _T_373 = ~_T_354; // @[el2_ifu_aln_ctl.scala 283:21] wire _T_373 = ~_T_354; // @[el2_ifu_aln_ctl.scala 283:21]
wire _T_374 = _T_372 & _T_373; // @[el2_ifu_aln_ctl.scala 283:19] wire _T_374 = _T_372 & _T_373; // @[el2_ifu_aln_ctl.scala 283:19]
wire [30:0] _T_364 = f1_shift_2B ? 31'h7fffffff : 31'h0; // @[Bitwise.scala 72:12] wire [30:0] _T_364 = f1_shift_2B ? 31'h7fffffff : 31'h0; // @[Bitwise.scala 72:12]
reg [30:0] f0pc; // @[Reg.scala 27:20] wire [30:0] f1pc_plus1 = f1pc + 31'h1; // @[el2_ifu_aln_ctl.scala 277:25]
wire [30:0] f0pc_plus1 = f0pc + 31'h1; // @[el2_ifu_aln_ctl.scala 275:25] wire [30:0] _T_365 = _T_364 & f1pc_plus1; // @[el2_ifu_aln_ctl.scala 279:38]
wire [30:0] _T_365 = _T_364 & f0pc_plus1; // @[el2_ifu_aln_ctl.scala 279:38]
wire [30:0] _T_368 = _T_417 ? 31'h7fffffff : 31'h0; // @[Bitwise.scala 72:12] wire [30:0] _T_368 = _T_417 ? 31'h7fffffff : 31'h0; // @[Bitwise.scala 72:12]
wire [30:0] _T_369 = _T_368 & f0pc; // @[el2_ifu_aln_ctl.scala 279:78] wire [30:0] _T_369 = _T_368 & f1pc; // @[el2_ifu_aln_ctl.scala 279:78]
wire [30:0] sf1pc = _T_365 | _T_369; // @[el2_ifu_aln_ctl.scala 279:52] wire [30:0] sf1pc = _T_365 | _T_369; // @[el2_ifu_aln_ctl.scala 279:52]
wire [30:0] _T_378 = _T_374 ? sf1pc : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_378 = _T_374 ? sf1pc : 31'h0; // @[Mux.scala 27:72]
wire [30:0] f1pc_in = _T_379 | _T_378; // @[Mux.scala 27:72] wire [30:0] f1pc_in = _T_379 | _T_378; // @[Mux.scala 27:72]
@ -705,6 +704,7 @@ module el2_ifu_aln_ctl(
wire _T_28 = _T_27 | _T_353; // @[el2_ifu_aln_ctl.scala 158:47] wire _T_28 = _T_27 | _T_353; // @[el2_ifu_aln_ctl.scala 158:47]
wire _T_29 = _T_28 | shift_2B; // @[el2_ifu_aln_ctl.scala 158:61] wire _T_29 = _T_28 | shift_2B; // @[el2_ifu_aln_ctl.scala 158:61]
wire f0_shift_wr_en = _T_29 | shift_4B; // @[el2_ifu_aln_ctl.scala 158:72] wire f0_shift_wr_en = _T_29 | shift_4B; // @[el2_ifu_aln_ctl.scala 158:72]
reg [30:0] f0pc; // @[Reg.scala 27:20]
wire [30:0] _T_391 = fetch_to_f0 ? io_ifu_fetch_pc : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_391 = fetch_to_f0 ? io_ifu_fetch_pc : 31'h0; // @[Mux.scala 27:72]
wire [30:0] _T_392 = _T_338 ? f2pc : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_392 = _T_338 ? f2pc : 31'h0; // @[Mux.scala 27:72]
wire [30:0] _T_395 = _T_391 | _T_392; // @[Mux.scala 27:72] wire [30:0] _T_395 = _T_391 | _T_392; // @[Mux.scala 27:72]
@ -715,6 +715,7 @@ module el2_ifu_aln_ctl(
wire _T_387 = _T_385 & _T_386; // @[el2_ifu_aln_ctl.scala 288:37] wire _T_387 = _T_385 & _T_386; // @[el2_ifu_aln_ctl.scala 288:37]
wire _T_388 = ~_T_353; // @[el2_ifu_aln_ctl.scala 288:54] wire _T_388 = ~_T_353; // @[el2_ifu_aln_ctl.scala 288:54]
wire _T_389 = _T_387 & _T_388; // @[el2_ifu_aln_ctl.scala 288:52] wire _T_389 = _T_387 & _T_388; // @[el2_ifu_aln_ctl.scala 288:52]
wire [30:0] f0pc_plus1 = f0pc + 31'h1; // @[el2_ifu_aln_ctl.scala 275:25]
wire [30:0] _T_394 = _T_389 ? f0pc_plus1 : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_394 = _T_389 ? f0pc_plus1 : 31'h0; // @[Mux.scala 27:72]
wire [30:0] f0pc_in = _T_396 | _T_394; // @[Mux.scala 27:72] wire [30:0] f0pc_in = _T_396 | _T_394; // @[Mux.scala 27:72]
wire _T_35 = wrptr == 2'h2; // @[el2_ifu_aln_ctl.scala 161:21] wire _T_35 = wrptr == 2'h2; // @[el2_ifu_aln_ctl.scala 161:21]

2
src/main/scala/ifu/el2_ifu_aln_ctl.scala
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@ -276,7 +276,7 @@ class el2_ifu_aln_ctl extends Module with el2_lib {
val f1pc_plus1 = f1pc + 1.U val f1pc_plus1 = f1pc + 1.U
val sf1pc = (Fill(31, f1_shift_2B) & f0pc_plus1) | (Fill(31, !f1_shift_2B) & f0pc) val sf1pc = (Fill(31, f1_shift_2B) & f1pc_plus1) | (Fill(31, !f1_shift_2B) & f1pc)
f1pc_in := Mux1H(Seq(fetch_to_f1.asBool->io.ifu_fetch_pc, f1pc_in := Mux1H(Seq(fetch_to_f1.asBool->io.ifu_fetch_pc,
shift_f2_f1.asBool->f2pc, shift_f2_f1.asBool->f2pc,

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target/scala-2.12/classes/ifu/el2_ifu_aln_ctl.class
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