diff --git a/el2_ifu_mem_ctl.fir b/el2_ifu_mem_ctl.fir
index 780508d1..3e337655 100644
--- a/el2_ifu_mem_ctl.fir
+++ b/el2_ifu_mem_ctl.fir
@@ -2982,7 +2982,7 @@ circuit el2_ifu_mem_ctl :
     node _T_2116 = mux(_T_2113, ic_byp_data_only_pre_new, _T_2115) @[el2_ifu_mem_ctl.scala 444:30]
     ic_byp_data_only_new <= _T_2116 @[el2_ifu_mem_ctl.scala 444:24]
     node _T_2117 = bits(imb_ff, 5, 5) @[el2_ifu_mem_ctl.scala 446:27]
-    node _T_2118 = bits(ifu_fetch_addr_int_f, 6, 6) @[el2_ifu_mem_ctl.scala 446:75]
+    node _T_2118 = bits(ifu_fetch_addr_int_f, 5, 5) @[el2_ifu_mem_ctl.scala 446:75]
     node miss_wrap_f = neq(_T_2117, _T_2118) @[el2_ifu_mem_ctl.scala 446:51]
     node _T_2119 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 447:102]
     node _T_2120 = eq(_T_2119, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 447:127]
diff --git a/el2_ifu_mem_ctl.v b/el2_ifu_mem_ctl.v
index 7c84c815..2233c7bf 100644
--- a/el2_ifu_mem_ctl.v
+++ b/el2_ifu_mem_ctl.v
@@ -829,7 +829,7 @@ module el2_ifu_mem_ctl(
   wire  crit_byp_hit_f = miss_buff_hit_unq_f & _T_2250; // @[el2_ifu_mem_ctl.scala 458:41]
   wire  _T_2233 = miss_state == 3'h6; // @[el2_ifu_mem_ctl.scala 455:30]
   reg [30:0] imb_ff; // @[el2_ifu_mem_ctl.scala 311:20]
-  wire  miss_wrap_f = imb_ff[5] != ifu_fetch_addr_int_f[6]; // @[el2_ifu_mem_ctl.scala 446:51]
+  wire  miss_wrap_f = imb_ff[5] != ifu_fetch_addr_int_f[5]; // @[el2_ifu_mem_ctl.scala 446:51]
   wire  _T_2234 = ~miss_wrap_f; // @[el2_ifu_mem_ctl.scala 455:68]
   wire  _T_2235 = miss_buff_hit_unq_f & _T_2234; // @[el2_ifu_mem_ctl.scala 455:66]
   wire  stream_hit_f = _T_2233 & _T_2235; // @[el2_ifu_mem_ctl.scala 455:43]
diff --git a/src/main/scala/ifu/el2_ifu_mem_ctl.scala b/src/main/scala/ifu/el2_ifu_mem_ctl.scala
index 2cb56da2..84129980 100644
--- a/src/main/scala/ifu/el2_ifu_mem_ctl.scala
+++ b/src/main/scala/ifu/el2_ifu_mem_ctl.scala
@@ -443,7 +443,7 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
 
   ic_byp_data_only_new := Mux(!ifu_fetch_addr_int_f(0).asBool(),ic_byp_data_only_pre_new,Cat(0.U(16.W),ic_byp_data_only_pre_new(79,16)))
 
-  val miss_wrap_f = imb_ff(ICACHE_TAG_INDEX_LO-1) =/= ifu_fetch_addr_int_f(ICACHE_TAG_INDEX_LO)
+  val miss_wrap_f = imb_ff(ICACHE_TAG_INDEX_LO-1) =/= ifu_fetch_addr_int_f(ICACHE_TAG_INDEX_LO-1)
   val ic_miss_buff_data_valid_bypass_index = Mux1H((0 until ICACHE_NUM_BEATS).map(i=>(byp_fetch_index(ICACHE_BEAT_ADDR_HI-1,2)===i.U).asBool->ic_miss_buff_data_valid(i)))
   val ic_miss_buff_data_valid_inc_bypass_index = Mux1H((0 until ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_inc===i.U).asBool->ic_miss_buff_data_valid(i)))
   val miss_buff_hit_unq_f = (ic_miss_buff_data_valid_bypass_index & !byp_fetch_index(1) & !byp_fetch_index(0)) |
diff --git a/target/scala-2.12/classes/ifu/el2_ifu_mem_ctl.class b/target/scala-2.12/classes/ifu/el2_ifu_mem_ctl.class
index 3df81c6e..5d586fad 100644
Binary files a/target/scala-2.12/classes/ifu/el2_ifu_mem_ctl.class and b/target/scala-2.12/classes/ifu/el2_ifu_mem_ctl.class differ