diff --git a/el2_ifu_ifc_ctl.anno.json b/el2_ifu_ifc_ctl.anno.json new file mode 100644 index 00000000..6da8d83b --- /dev/null +++ b/el2_ifu_ifc_ctl.anno.json @@ -0,0 +1,122 @@ +[ + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_dma_access_ok", + "sources":[ + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_final", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_iccm_access_bf", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_bf", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_fb_consume2", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_fb_consume1", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_dec_tlu_flush_noredir_wb", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_addr_bf", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_write_stall", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_bf_raw", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_dma_active", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_bp_btb_target_f", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_path_final", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_addr_f", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_hit_f", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_bp_hit_taken_f", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_f" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_pmu_fetch_stall", + "sources":[ + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_bf_raw", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_dma_active", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_final", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_fb_consume2", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_fb_consume1" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_addr_bf", + "sources":[ + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_bp_btb_target_f", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_path_final", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_addr_f", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_hit_f", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_final", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_bp_hit_taken_f", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_f" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_iccm_access_bf", + "sources":[ + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_addr_bf", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_bp_btb_target_f", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_path_final", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_addr_f", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_hit_f", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_final", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_bp_hit_taken_f", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_f" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_bf", + "sources":[ + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_dec_tlu_flush_noredir_wb", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_write_stall", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_bf_raw", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_dma_active", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_fb_consume2", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_fb_consume1", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_final", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_f", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_hit_f" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_region_acc_fault_bf", + "sources":[ + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_addr_bf", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_bp_btb_target_f", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_path_final", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_addr_f", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_hit_f", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_final", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_bp_hit_taken_f", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_f" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_uncacheable_bf", + "sources":[ + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_dec_tlu_mrac_ff", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_addr_bf", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_bp_btb_target_f", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_path_final", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_addr_f", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_hit_f", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_final", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_bp_hit_taken_f", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_f" + ] + }, + { + "class":"firrtl.EmitCircuitAnnotation", + "emitter":"firrtl.VerilogEmitter" + }, + { + "class":"firrtl.options.TargetDirAnnotation", + "directory":"." + }, + { + "class":"firrtl.options.OutputAnnotationFileAnnotation", + "file":"el2_ifu_ifc_ctl" + }, + { + "class":"firrtl.transforms.BlackBoxTargetDirAnno", + "targetDir":"." + } +] \ No newline at end of file diff --git a/el2_ifu_ifc_ctl.fir b/el2_ifu_ifc_ctl.fir new file mode 100644 index 00000000..f3feae58 --- /dev/null +++ b/el2_ifu_ifc_ctl.fir @@ -0,0 +1,266 @@ +;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 +circuit el2_ifu_ifc_ctl : + module el2_ifu_ifc_ctl : + input clock : Clock + input reset : AsyncReset + output io : {flip free_clk : Clock, flip active_clk : UInt<1>, flip scan_mode : UInt<1>, flip ic_hit_f : UInt<1>, flip ifu_ic_mb_empty : UInt<1>, flip ifu_fb_consume1 : UInt<1>, flip ifu_fb_consume2 : UInt<1>, flip dec_tlu_flush_noredir_wb : UInt<1>, flip exu_flush_final : UInt<1>, flip exu_flush_path_final : UInt<31>, flip ifu_bp_hit_taken_f : UInt<1>, flip ifu_bp_btb_target_f : UInt<31>, flip ic_dma_active : UInt<1>, flip ic_write_stall : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, ifc_fetch_addr_f : UInt<31>, ifc_fetch_addr_bf : UInt<31>, ifc_fetch_req_f : UInt<1>, ifu_pmu_fetch_stall : UInt<1>, ifc_fetch_uncacheable_bf : UInt<1>, ifc_fetch_req_bf : UInt<1>, ifc_fetch_req_bf_raw : UInt<1>, ifc_iccm_access_bf : UInt<1>, ifc_region_acc_fault_bf : UInt<1>, ifc_dma_access_ok : UInt<1>} + + wire fetch_addr_bf : UInt<32> + fetch_addr_bf <= UInt<1>("h00") + wire fetch_addr_next : UInt<32> + fetch_addr_next <= UInt<1>("h00") + wire fb_write_ns : UInt<4> + fb_write_ns <= UInt<1>("h00") + wire fb_write_f : UInt<4> + fb_write_f <= UInt<1>("h00") + wire fb_full_f_ns : UInt<1> + fb_full_f_ns <= UInt<1>("h00") + wire fb_right : UInt<1> + fb_right <= UInt<1>("h00") + wire fb_right2 : UInt<1> + fb_right2 <= UInt<1>("h00") + wire fb_left : UInt<1> + fb_left <= UInt<1>("h00") + wire wfm : UInt<1> + wfm <= UInt<1>("h00") + wire idle : UInt<1> + idle <= UInt<1>("h00") + wire miss_f : UInt<1> + miss_f <= UInt<1>("h00") + wire miss_a : UInt<1> + miss_a <= UInt<1>("h00") + wire flush_fb : UInt<1> + flush_fb <= UInt<1>("h00") + wire mb_empty_mod : UInt<1> + mb_empty_mod <= UInt<1>("h00") + wire goto_idle : UInt<1> + goto_idle <= UInt<1>("h00") + wire leave_idle : UInt<1> + leave_idle <= UInt<1>("h00") + wire fetch_bf_en : UInt<1> + fetch_bf_en <= UInt<1>("h00") + wire line_wrap : UInt<1> + line_wrap <= UInt<1>("h00") + wire state : UInt<2> + state <= UInt<1>("h00") + wire dma_iccm_stall_any_f : UInt<1> + dma_iccm_stall_any_f <= UInt<1>("h00") + node dma_stall = or(io.ic_dma_active, dma_iccm_stall_any_f) @[el2_ifu_ifc_ctl.scala 61:36] + reg _T : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 62:58] + _T <= io.dma_iccm_stall_any @[el2_ifu_ifc_ctl.scala 62:58] + dma_iccm_stall_any_f <= _T @[el2_ifu_ifc_ctl.scala 62:24] + reg _T_1 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 64:44] + _T_1 <= miss_f @[el2_ifu_ifc_ctl.scala 64:44] + miss_a <= _T_1 @[el2_ifu_ifc_ctl.scala 64:10] + node _T_2 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 66:26] + node _T_3 = eq(io.ifc_fetch_req_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 66:49] + node _T_4 = eq(io.ic_hit_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 66:71] + node _T_5 = or(_T_3, _T_4) @[el2_ifu_ifc_ctl.scala 66:69] + node sel_last_addr_bf = and(_T_2, _T_5) @[el2_ifu_ifc_ctl.scala 66:46] + node _T_6 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 67:26] + node _T_7 = and(_T_6, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 67:46] + node _T_8 = and(_T_7, io.ifu_bp_hit_taken_f) @[el2_ifu_ifc_ctl.scala 67:67] + node sel_btb_addr_bf = and(_T_8, io.ic_hit_f) @[el2_ifu_ifc_ctl.scala 67:92] + node _T_9 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 68:26] + node _T_10 = and(_T_9, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 68:46] + node _T_11 = eq(io.ifu_bp_hit_taken_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 68:69] + node _T_12 = and(_T_10, _T_11) @[el2_ifu_ifc_ctl.scala 68:67] + node sel_next_addr_bf = and(_T_12, io.ic_hit_f) @[el2_ifu_ifc_ctl.scala 68:92] + node _T_13 = bits(io.exu_flush_final, 0, 0) @[el2_ifu_ifc_ctl.scala 71:56] + node _T_14 = bits(sel_last_addr_bf, 0, 0) @[el2_ifu_ifc_ctl.scala 72:22] + node _T_15 = bits(sel_btb_addr_bf, 0, 0) @[el2_ifu_ifc_ctl.scala 73:21] + node _T_16 = bits(sel_next_addr_bf, 0, 0) @[el2_ifu_ifc_ctl.scala 74:22] + node _T_17 = mux(_T_13, io.exu_flush_path_final, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_18 = mux(_T_14, io.ifc_fetch_addr_f, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_19 = mux(_T_15, io.ifu_bp_btb_target_f, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_20 = mux(_T_16, fetch_addr_next, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_21 = or(_T_17, _T_18) @[Mux.scala 27:72] + node _T_22 = or(_T_21, _T_19) @[Mux.scala 27:72] + node _T_23 = or(_T_22, _T_20) @[Mux.scala 27:72] + wire _T_24 : UInt<32> @[Mux.scala 27:72] + _T_24 <= _T_23 @[Mux.scala 27:72] + io.ifc_fetch_addr_bf <= _T_24 @[el2_ifu_ifc_ctl.scala 71:24] + line_wrap <= UInt<1>("h00") @[el2_ifu_ifc_ctl.scala 78:13] + node _T_25 = bits(line_wrap, 0, 0) @[el2_ifu_ifc_ctl.scala 79:47] + node _T_26 = bits(io.ifc_fetch_addr_f, 0, 0) @[el2_ifu_ifc_ctl.scala 79:75] + node fetch_addr_next_1 = mux(_T_25, UInt<1>("h00"), _T_26) @[el2_ifu_ifc_ctl.scala 79:30] + node _T_27 = bits(io.ifc_fetch_addr_f, 30, 1) @[el2_ifu_ifc_ctl.scala 80:45] + node _T_28 = add(_T_27, UInt<1>("h01")) @[el2_ifu_ifc_ctl.scala 80:51] + node _T_29 = tail(_T_28, 1) @[el2_ifu_ifc_ctl.scala 80:51] + node _T_30 = cat(_T_29, UInt<1>("h00")) @[Cat.scala 29:58] + fetch_addr_next <= _T_30 @[el2_ifu_ifc_ctl.scala 80:19] + node _T_31 = not(idle) @[el2_ifu_ifc_ctl.scala 83:30] + io.ifc_fetch_req_bf_raw <= _T_31 @[el2_ifu_ifc_ctl.scala 83:27] + node _T_32 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 85:91] + node _T_33 = eq(_T_32, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 85:70] + node _T_34 = and(fb_full_f_ns, _T_33) @[el2_ifu_ifc_ctl.scala 85:68] + node _T_35 = eq(_T_34, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 85:53] + node _T_36 = and(io.ifc_fetch_req_bf_raw, _T_35) @[el2_ifu_ifc_ctl.scala 85:51] + node _T_37 = eq(dma_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 86:5] + node _T_38 = and(_T_36, _T_37) @[el2_ifu_ifc_ctl.scala 85:114] + node _T_39 = eq(io.ic_write_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 86:18] + node _T_40 = and(_T_38, _T_39) @[el2_ifu_ifc_ctl.scala 86:16] + node _T_41 = eq(io.dec_tlu_flush_noredir_wb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 86:39] + node _T_42 = and(_T_40, _T_41) @[el2_ifu_ifc_ctl.scala 86:37] + io.ifc_fetch_req_bf <= _T_42 @[el2_ifu_ifc_ctl.scala 85:23] + node _T_43 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 88:37] + fetch_bf_en <= _T_43 @[el2_ifu_ifc_ctl.scala 88:15] + node _T_44 = eq(io.ic_hit_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 90:34] + node _T_45 = and(io.ifc_fetch_req_f, _T_44) @[el2_ifu_ifc_ctl.scala 90:32] + node _T_46 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 90:49] + node _T_47 = and(_T_45, _T_46) @[el2_ifu_ifc_ctl.scala 90:47] + miss_f <= _T_47 @[el2_ifu_ifc_ctl.scala 90:10] + node _T_48 = or(io.ifu_ic_mb_empty, io.exu_flush_final) @[el2_ifu_ifc_ctl.scala 92:39] + node _T_49 = eq(dma_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 92:63] + node _T_50 = and(_T_48, _T_49) @[el2_ifu_ifc_ctl.scala 92:61] + node _T_51 = eq(miss_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 92:76] + node _T_52 = and(_T_50, _T_51) @[el2_ifu_ifc_ctl.scala 92:74] + node _T_53 = eq(miss_a, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 92:86] + node _T_54 = and(_T_52, _T_53) @[el2_ifu_ifc_ctl.scala 92:84] + mb_empty_mod <= _T_54 @[el2_ifu_ifc_ctl.scala 92:16] + node _T_55 = and(io.exu_flush_final, io.dec_tlu_flush_noredir_wb) @[el2_ifu_ifc_ctl.scala 94:35] + goto_idle <= _T_55 @[el2_ifu_ifc_ctl.scala 94:13] + node _T_56 = eq(io.dec_tlu_flush_noredir_wb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 96:38] + node _T_57 = and(io.exu_flush_final, _T_56) @[el2_ifu_ifc_ctl.scala 96:36] + node _T_58 = and(_T_57, idle) @[el2_ifu_ifc_ctl.scala 96:67] + leave_idle <= _T_58 @[el2_ifu_ifc_ctl.scala 96:14] + node _T_59 = bits(state, 1, 1) @[el2_ifu_ifc_ctl.scala 98:29] + node _T_60 = eq(_T_59, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 98:23] + node _T_61 = bits(state, 0, 0) @[el2_ifu_ifc_ctl.scala 98:40] + node _T_62 = and(_T_60, _T_61) @[el2_ifu_ifc_ctl.scala 98:33] + node _T_63 = and(_T_62, miss_f) @[el2_ifu_ifc_ctl.scala 98:44] + node _T_64 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 98:55] + node _T_65 = and(_T_63, _T_64) @[el2_ifu_ifc_ctl.scala 98:53] + node _T_66 = bits(state, 1, 1) @[el2_ifu_ifc_ctl.scala 99:11] + node _T_67 = eq(mb_empty_mod, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 99:17] + node _T_68 = and(_T_66, _T_67) @[el2_ifu_ifc_ctl.scala 99:15] + node _T_69 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 99:33] + node _T_70 = and(_T_68, _T_69) @[el2_ifu_ifc_ctl.scala 99:31] + node next_state_1 = or(_T_65, _T_70) @[el2_ifu_ifc_ctl.scala 98:67] + node _T_71 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 101:23] + node _T_72 = and(_T_71, leave_idle) @[el2_ifu_ifc_ctl.scala 101:34] + node _T_73 = bits(state, 0, 0) @[el2_ifu_ifc_ctl.scala 101:56] + node _T_74 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 101:62] + node _T_75 = and(_T_73, _T_74) @[el2_ifu_ifc_ctl.scala 101:60] + node next_state_0 = or(_T_72, _T_75) @[el2_ifu_ifc_ctl.scala 101:48] + node _T_76 = cat(next_state_1, next_state_0) @[Cat.scala 29:58] + reg _T_77 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 103:19] + _T_77 <= _T_76 @[el2_ifu_ifc_ctl.scala 103:19] + state <= _T_77 @[el2_ifu_ifc_ctl.scala 103:9] + flush_fb <= io.exu_flush_final @[el2_ifu_ifc_ctl.scala 105:12] + node _T_78 = eq(io.ifu_fb_consume2, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 107:38] + node _T_79 = and(io.ifu_fb_consume1, _T_78) @[el2_ifu_ifc_ctl.scala 107:36] + node _T_80 = eq(io.ifc_fetch_req_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 107:61] + node _T_81 = or(_T_80, miss_f) @[el2_ifu_ifc_ctl.scala 107:81] + node _T_82 = and(_T_79, _T_81) @[el2_ifu_ifc_ctl.scala 107:58] + node _T_83 = and(io.ifu_fb_consume2, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 108:25] + node _T_84 = or(_T_82, _T_83) @[el2_ifu_ifc_ctl.scala 107:92] + fb_right <= _T_84 @[el2_ifu_ifc_ctl.scala 107:12] + node _T_85 = not(io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 110:39] + node _T_86 = or(_T_85, miss_f) @[el2_ifu_ifc_ctl.scala 110:59] + node _T_87 = and(io.ifu_fb_consume2, _T_86) @[el2_ifu_ifc_ctl.scala 110:36] + fb_right2 <= _T_87 @[el2_ifu_ifc_ctl.scala 110:13] + node _T_88 = or(io.ifu_fb_consume1, io.ifu_fb_consume2) @[el2_ifu_ifc_ctl.scala 111:56] + node _T_89 = eq(_T_88, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 111:35] + node _T_90 = and(io.ifc_fetch_req_f, _T_89) @[el2_ifu_ifc_ctl.scala 111:33] + node _T_91 = eq(miss_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 111:80] + node _T_92 = and(_T_90, _T_91) @[el2_ifu_ifc_ctl.scala 111:78] + fb_left <= _T_92 @[el2_ifu_ifc_ctl.scala 111:11] + node _T_93 = bits(flush_fb, 0, 0) @[el2_ifu_ifc_ctl.scala 113:37] + node _T_94 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 114:6] + node _T_95 = and(_T_94, fb_right) @[el2_ifu_ifc_ctl.scala 114:16] + node _T_96 = bits(_T_95, 0, 0) @[el2_ifu_ifc_ctl.scala 114:28] + node _T_97 = bits(fb_write_f, 3, 1) @[el2_ifu_ifc_ctl.scala 114:62] + node _T_98 = cat(UInt<1>("h00"), _T_97) @[Cat.scala 29:58] + node _T_99 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 115:6] + node _T_100 = and(_T_99, fb_right2) @[el2_ifu_ifc_ctl.scala 115:16] + node _T_101 = bits(_T_100, 0, 0) @[el2_ifu_ifc_ctl.scala 115:29] + node _T_102 = bits(fb_write_f, 3, 2) @[el2_ifu_ifc_ctl.scala 115:63] + node _T_103 = cat(UInt<2>("h00"), _T_102) @[Cat.scala 29:58] + node _T_104 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:6] + node _T_105 = and(_T_104, fb_left) @[el2_ifu_ifc_ctl.scala 116:16] + node _T_106 = bits(_T_105, 0, 0) @[el2_ifu_ifc_ctl.scala 116:27] + node _T_107 = bits(fb_write_f, 2, 0) @[el2_ifu_ifc_ctl.scala 116:51] + node _T_108 = cat(_T_107, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_109 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 117:6] + node _T_110 = eq(fb_right, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 117:18] + node _T_111 = and(_T_109, _T_110) @[el2_ifu_ifc_ctl.scala 117:16] + node _T_112 = eq(fb_right2, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 117:30] + node _T_113 = and(_T_111, _T_112) @[el2_ifu_ifc_ctl.scala 117:28] + node _T_114 = eq(fb_left, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 117:43] + node _T_115 = and(_T_113, _T_114) @[el2_ifu_ifc_ctl.scala 117:41] + node _T_116 = bits(_T_115, 0, 0) @[el2_ifu_ifc_ctl.scala 117:53] + node _T_117 = bits(fb_write_f, 3, 0) @[el2_ifu_ifc_ctl.scala 117:73] + node _T_118 = mux(_T_93, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_119 = mux(_T_96, _T_98, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_120 = mux(_T_101, _T_103, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_121 = mux(_T_106, _T_108, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_122 = mux(_T_116, _T_117, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_123 = or(_T_118, _T_119) @[Mux.scala 27:72] + node _T_124 = or(_T_123, _T_120) @[Mux.scala 27:72] + node _T_125 = or(_T_124, _T_121) @[Mux.scala 27:72] + node _T_126 = or(_T_125, _T_122) @[Mux.scala 27:72] + wire _T_127 : UInt<4> @[Mux.scala 27:72] + _T_127 <= _T_126 @[Mux.scala 27:72] + fb_write_ns <= _T_127 @[el2_ifu_ifc_ctl.scala 113:15] + node _T_128 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctl.scala 120:38] + reg _T_129 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 120:26] + _T_129 <= _T_128 @[el2_ifu_ifc_ctl.scala 120:26] + fb_full_f_ns <= _T_129 @[el2_ifu_ifc_ctl.scala 120:16] + node _T_130 = eq(state, UInt<2>("h00")) @[el2_ifu_ifc_ctl.scala 122:17] + idle <= _T_130 @[el2_ifu_ifc_ctl.scala 122:8] + node _T_131 = eq(state, UInt<2>("h03")) @[el2_ifu_ifc_ctl.scala 123:16] + wfm <= _T_131 @[el2_ifu_ifc_ctl.scala 123:7] + node _T_132 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctl.scala 125:30] + fb_full_f_ns <= _T_132 @[el2_ifu_ifc_ctl.scala 125:16] + reg fb_full_f : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 126:26] + fb_full_f <= fb_full_f_ns @[el2_ifu_ifc_ctl.scala 126:26] + reg _T_133 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 127:24] + _T_133 <= fb_write_ns @[el2_ifu_ifc_ctl.scala 127:24] + fb_write_f <= _T_133 @[el2_ifu_ifc_ctl.scala 127:14] + node _T_134 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 130:40] + node _T_135 = or(_T_134, io.exu_flush_final) @[el2_ifu_ifc_ctl.scala 130:61] + node _T_136 = eq(_T_135, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 130:19] + node _T_137 = and(fb_full_f, _T_136) @[el2_ifu_ifc_ctl.scala 130:17] + node _T_138 = or(_T_137, dma_stall) @[el2_ifu_ifc_ctl.scala 130:84] + node _T_139 = and(io.ifc_fetch_req_bf_raw, _T_138) @[el2_ifu_ifc_ctl.scala 129:60] + node _T_140 = or(wfm, _T_139) @[el2_ifu_ifc_ctl.scala 129:33] + io.ifu_pmu_fetch_stall <= _T_140 @[el2_ifu_ifc_ctl.scala 129:26] + node _T_141 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_142 = bits(_T_141, 31, 28) @[el2_lib.scala 211:25] + node iccm_acc_in_region_bf = eq(_T_142, UInt<4>("h0e")) @[el2_lib.scala 211:47] + node _T_143 = bits(_T_141, 31, 16) @[el2_lib.scala 214:14] + node iccm_acc_in_range_bf = eq(_T_143, UInt<16>("h0ee00")) @[el2_lib.scala 214:29] + io.ifc_iccm_access_bf <= iccm_acc_in_range_bf @[el2_ifu_ifc_ctl.scala 135:25] + node _T_144 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 136:30] + node _T_145 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 137:39] + node _T_146 = eq(_T_145, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 137:18] + node _T_147 = and(fb_full_f, _T_146) @[el2_ifu_ifc_ctl.scala 137:16] + node _T_148 = or(_T_144, _T_147) @[el2_ifu_ifc_ctl.scala 136:53] + node _T_149 = eq(io.ifc_fetch_req_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 138:13] + node _T_150 = and(wfm, _T_149) @[el2_ifu_ifc_ctl.scala 138:11] + node _T_151 = or(_T_148, _T_150) @[el2_ifu_ifc_ctl.scala 137:62] + node _T_152 = or(_T_151, idle) @[el2_ifu_ifc_ctl.scala 138:35] + node _T_153 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 138:46] + node _T_154 = and(_T_152, _T_153) @[el2_ifu_ifc_ctl.scala 138:44] + node _T_155 = or(_T_154, dma_iccm_stall_any_f) @[el2_ifu_ifc_ctl.scala 138:67] + io.ifc_dma_access_ok <= _T_155 @[el2_ifu_ifc_ctl.scala 136:24] + node _T_156 = not(iccm_acc_in_range_bf) @[el2_ifu_ifc_ctl.scala 140:33] + node _T_157 = and(_T_156, iccm_acc_in_region_bf) @[el2_ifu_ifc_ctl.scala 140:55] + io.ifc_region_acc_fault_bf <= _T_157 @[el2_ifu_ifc_ctl.scala 140:30] + node _T_158 = bits(io.ifc_fetch_addr_bf, 30, 27) @[el2_ifu_ifc_ctl.scala 141:78] + node _T_159 = cat(_T_158, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_160 = dshr(io.dec_tlu_mrac_ff, _T_159) @[el2_ifu_ifc_ctl.scala 141:53] + node _T_161 = bits(_T_160, 0, 0) @[el2_ifu_ifc_ctl.scala 141:53] + node _T_162 = not(_T_161) @[el2_ifu_ifc_ctl.scala 141:34] + io.ifc_fetch_uncacheable_bf <= _T_162 @[el2_ifu_ifc_ctl.scala 141:31] + reg _T_163 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 143:32] + _T_163 <= io.ifc_fetch_req_bf @[el2_ifu_ifc_ctl.scala 143:32] + io.ifc_fetch_req_f <= _T_163 @[el2_ifu_ifc_ctl.scala 143:22] + node _T_164 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 145:88] + reg _T_165 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_164 : @[Reg.scala 28:19] + _T_165 <= io.ifc_fetch_addr_bf @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.ifc_fetch_addr_f <= _T_165 @[el2_ifu_ifc_ctl.scala 145:23] + diff --git a/el2_ifu_ifc_ctl.v b/el2_ifu_ifc_ctl.v new file mode 100644 index 00000000..c0b5bfd2 --- /dev/null +++ b/el2_ifu_ifc_ctl.v @@ -0,0 +1,294 @@ +module el2_ifu_ifc_ctl( + input clock, + input reset, + input io_free_clk, + input io_active_clk, + input io_scan_mode, + input io_ic_hit_f, + input io_ifu_ic_mb_empty, + input io_ifu_fb_consume1, + input io_ifu_fb_consume2, + input io_dec_tlu_flush_noredir_wb, + input io_exu_flush_final, + input [30:0] io_exu_flush_path_final, + input io_ifu_bp_hit_taken_f, + input [30:0] io_ifu_bp_btb_target_f, + input io_ic_dma_active, + input io_ic_write_stall, + input io_dma_iccm_stall_any, + input [31:0] io_dec_tlu_mrac_ff, + output [30:0] io_ifc_fetch_addr_f, + output [30:0] io_ifc_fetch_addr_bf, + output io_ifc_fetch_req_f, + output io_ifu_pmu_fetch_stall, + output io_ifc_fetch_uncacheable_bf, + output io_ifc_fetch_req_bf, + output io_ifc_fetch_req_bf_raw, + output io_ifc_iccm_access_bf, + output io_ifc_region_acc_fault_bf, + output io_ifc_dma_access_ok +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; +`endif // RANDOMIZE_REG_INIT + reg dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctl.scala 62:58] + wire dma_stall = io_ic_dma_active | dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctl.scala 61:36] + reg miss_a; // @[el2_ifu_ifc_ctl.scala 64:44] + wire _T_2 = ~io_exu_flush_final; // @[el2_ifu_ifc_ctl.scala 66:26] + wire _T_3 = ~io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctl.scala 66:49] + wire _T_4 = ~io_ic_hit_f; // @[el2_ifu_ifc_ctl.scala 66:71] + wire _T_5 = _T_3 | _T_4; // @[el2_ifu_ifc_ctl.scala 66:69] + wire sel_last_addr_bf = _T_2 & _T_5; // @[el2_ifu_ifc_ctl.scala 66:46] + wire _T_7 = _T_2 & io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctl.scala 67:46] + wire _T_8 = _T_7 & io_ifu_bp_hit_taken_f; // @[el2_ifu_ifc_ctl.scala 67:67] + wire sel_btb_addr_bf = _T_8 & io_ic_hit_f; // @[el2_ifu_ifc_ctl.scala 67:92] + wire _T_11 = ~io_ifu_bp_hit_taken_f; // @[el2_ifu_ifc_ctl.scala 68:69] + wire _T_12 = _T_7 & _T_11; // @[el2_ifu_ifc_ctl.scala 68:67] + wire sel_next_addr_bf = _T_12 & io_ic_hit_f; // @[el2_ifu_ifc_ctl.scala 68:92] + wire [30:0] _T_17 = io_exu_flush_final ? io_exu_flush_path_final : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_18 = sel_last_addr_bf ? io_ifc_fetch_addr_f : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_19 = sel_btb_addr_bf ? io_ifu_bp_btb_target_f : 31'h0; // @[Mux.scala 27:72] + wire [29:0] _T_29 = io_ifc_fetch_addr_f[30:1] + 30'h1; // @[el2_ifu_ifc_ctl.scala 80:51] + wire [30:0] _T_30 = {_T_29,1'h0}; // @[Cat.scala 29:58] + wire [31:0] fetch_addr_next = {{1'd0}, _T_30}; // @[el2_ifu_ifc_ctl.scala 80:19] + wire [31:0] _T_20 = sel_next_addr_bf ? fetch_addr_next : 32'h0; // @[Mux.scala 27:72] + wire [30:0] _T_21 = _T_17 | _T_18; // @[Mux.scala 27:72] + wire [30:0] _T_22 = _T_21 | _T_19; // @[Mux.scala 27:72] + wire [31:0] _GEN_1 = {{1'd0}, _T_22}; // @[Mux.scala 27:72] + wire [31:0] _T_23 = _GEN_1 | _T_20; // @[Mux.scala 27:72] + reg [1:0] state; // @[el2_ifu_ifc_ctl.scala 103:19] + wire idle = state == 2'h0; // @[el2_ifu_ifc_ctl.scala 122:17] + wire _T_32 = io_ifu_fb_consume2 | io_ifu_fb_consume1; // @[el2_ifu_ifc_ctl.scala 85:91] + wire _T_33 = ~_T_32; // @[el2_ifu_ifc_ctl.scala 85:70] + wire [3:0] _T_118 = io_exu_flush_final ? 4'h1 : 4'h0; // @[Mux.scala 27:72] + wire _T_78 = ~io_ifu_fb_consume2; // @[el2_ifu_ifc_ctl.scala 107:38] + wire _T_79 = io_ifu_fb_consume1 & _T_78; // @[el2_ifu_ifc_ctl.scala 107:36] + wire _T_45 = io_ifc_fetch_req_f & _T_4; // @[el2_ifu_ifc_ctl.scala 90:32] + wire miss_f = _T_45 & _T_2; // @[el2_ifu_ifc_ctl.scala 90:47] + wire _T_81 = _T_3 | miss_f; // @[el2_ifu_ifc_ctl.scala 107:81] + wire _T_82 = _T_79 & _T_81; // @[el2_ifu_ifc_ctl.scala 107:58] + wire _T_83 = io_ifu_fb_consume2 & io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctl.scala 108:25] + wire fb_right = _T_82 | _T_83; // @[el2_ifu_ifc_ctl.scala 107:92] + wire _T_95 = _T_2 & fb_right; // @[el2_ifu_ifc_ctl.scala 114:16] + reg [3:0] fb_write_f; // @[el2_ifu_ifc_ctl.scala 127:24] + wire [3:0] _T_98 = {1'h0,fb_write_f[3:1]}; // @[Cat.scala 29:58] + wire [3:0] _T_119 = _T_95 ? _T_98 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_123 = _T_118 | _T_119; // @[Mux.scala 27:72] + wire fb_right2 = io_ifu_fb_consume2 & _T_81; // @[el2_ifu_ifc_ctl.scala 110:36] + wire _T_100 = _T_2 & fb_right2; // @[el2_ifu_ifc_ctl.scala 115:16] + wire [3:0] _T_103 = {2'h0,fb_write_f[3:2]}; // @[Cat.scala 29:58] + wire [3:0] _T_120 = _T_100 ? _T_103 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_124 = _T_123 | _T_120; // @[Mux.scala 27:72] + wire _T_88 = io_ifu_fb_consume1 | io_ifu_fb_consume2; // @[el2_ifu_ifc_ctl.scala 111:56] + wire _T_89 = ~_T_88; // @[el2_ifu_ifc_ctl.scala 111:35] + wire _T_90 = io_ifc_fetch_req_f & _T_89; // @[el2_ifu_ifc_ctl.scala 111:33] + wire _T_91 = ~miss_f; // @[el2_ifu_ifc_ctl.scala 111:80] + wire fb_left = _T_90 & _T_91; // @[el2_ifu_ifc_ctl.scala 111:78] + wire _T_105 = _T_2 & fb_left; // @[el2_ifu_ifc_ctl.scala 116:16] + wire [3:0] _T_108 = {fb_write_f[2:0],1'h0}; // @[Cat.scala 29:58] + wire [3:0] _T_121 = _T_105 ? _T_108 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_125 = _T_124 | _T_121; // @[Mux.scala 27:72] + wire _T_110 = ~fb_right; // @[el2_ifu_ifc_ctl.scala 117:18] + wire _T_111 = _T_2 & _T_110; // @[el2_ifu_ifc_ctl.scala 117:16] + wire _T_112 = ~fb_right2; // @[el2_ifu_ifc_ctl.scala 117:30] + wire _T_113 = _T_111 & _T_112; // @[el2_ifu_ifc_ctl.scala 117:28] + wire _T_114 = ~fb_left; // @[el2_ifu_ifc_ctl.scala 117:43] + wire _T_115 = _T_113 & _T_114; // @[el2_ifu_ifc_ctl.scala 117:41] + wire [3:0] _T_122 = _T_115 ? fb_write_f : 4'h0; // @[Mux.scala 27:72] + wire [3:0] fb_write_ns = _T_125 | _T_122; // @[Mux.scala 27:72] + wire fb_full_f_ns = fb_write_ns[3]; // @[el2_ifu_ifc_ctl.scala 125:30] + wire _T_34 = fb_full_f_ns & _T_33; // @[el2_ifu_ifc_ctl.scala 85:68] + wire _T_35 = ~_T_34; // @[el2_ifu_ifc_ctl.scala 85:53] + wire _T_36 = io_ifc_fetch_req_bf_raw & _T_35; // @[el2_ifu_ifc_ctl.scala 85:51] + wire _T_37 = ~dma_stall; // @[el2_ifu_ifc_ctl.scala 86:5] + wire _T_38 = _T_36 & _T_37; // @[el2_ifu_ifc_ctl.scala 85:114] + wire _T_39 = ~io_ic_write_stall; // @[el2_ifu_ifc_ctl.scala 86:18] + wire _T_40 = _T_38 & _T_39; // @[el2_ifu_ifc_ctl.scala 86:16] + wire _T_41 = ~io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctl.scala 86:39] + wire fetch_bf_en = io_exu_flush_final | io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctl.scala 88:37] + wire _T_48 = io_ifu_ic_mb_empty | io_exu_flush_final; // @[el2_ifu_ifc_ctl.scala 92:39] + wire _T_50 = _T_48 & _T_37; // @[el2_ifu_ifc_ctl.scala 92:61] + wire _T_52 = _T_50 & _T_91; // @[el2_ifu_ifc_ctl.scala 92:74] + wire _T_53 = ~miss_a; // @[el2_ifu_ifc_ctl.scala 92:86] + wire mb_empty_mod = _T_52 & _T_53; // @[el2_ifu_ifc_ctl.scala 92:84] + wire goto_idle = io_exu_flush_final & io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctl.scala 94:35] + wire _T_57 = io_exu_flush_final & _T_41; // @[el2_ifu_ifc_ctl.scala 96:36] + wire leave_idle = _T_57 & idle; // @[el2_ifu_ifc_ctl.scala 96:67] + wire _T_60 = ~state[1]; // @[el2_ifu_ifc_ctl.scala 98:23] + wire _T_62 = _T_60 & state[0]; // @[el2_ifu_ifc_ctl.scala 98:33] + wire _T_63 = _T_62 & miss_f; // @[el2_ifu_ifc_ctl.scala 98:44] + wire _T_64 = ~goto_idle; // @[el2_ifu_ifc_ctl.scala 98:55] + wire _T_65 = _T_63 & _T_64; // @[el2_ifu_ifc_ctl.scala 98:53] + wire _T_67 = ~mb_empty_mod; // @[el2_ifu_ifc_ctl.scala 99:17] + wire _T_68 = state[1] & _T_67; // @[el2_ifu_ifc_ctl.scala 99:15] + wire _T_70 = _T_68 & _T_64; // @[el2_ifu_ifc_ctl.scala 99:31] + wire next_state_1 = _T_65 | _T_70; // @[el2_ifu_ifc_ctl.scala 98:67] + wire _T_72 = _T_64 & leave_idle; // @[el2_ifu_ifc_ctl.scala 101:34] + wire _T_75 = state[0] & _T_64; // @[el2_ifu_ifc_ctl.scala 101:60] + wire next_state_0 = _T_72 | _T_75; // @[el2_ifu_ifc_ctl.scala 101:48] + wire wfm = state == 2'h3; // @[el2_ifu_ifc_ctl.scala 123:16] + reg fb_full_f; // @[el2_ifu_ifc_ctl.scala 126:26] + wire _T_135 = _T_32 | io_exu_flush_final; // @[el2_ifu_ifc_ctl.scala 130:61] + wire _T_136 = ~_T_135; // @[el2_ifu_ifc_ctl.scala 130:19] + wire _T_137 = fb_full_f & _T_136; // @[el2_ifu_ifc_ctl.scala 130:17] + wire _T_138 = _T_137 | dma_stall; // @[el2_ifu_ifc_ctl.scala 130:84] + wire _T_139 = io_ifc_fetch_req_bf_raw & _T_138; // @[el2_ifu_ifc_ctl.scala 129:60] + wire [31:0] _T_141 = {io_ifc_fetch_addr_bf,1'h0}; // @[Cat.scala 29:58] + wire iccm_acc_in_region_bf = _T_141[31:28] == 4'he; // @[el2_lib.scala 211:47] + wire iccm_acc_in_range_bf = _T_141[31:16] == 16'hee00; // @[el2_lib.scala 214:29] + wire _T_144 = ~io_ifc_iccm_access_bf; // @[el2_ifu_ifc_ctl.scala 136:30] + wire _T_147 = fb_full_f & _T_33; // @[el2_ifu_ifc_ctl.scala 137:16] + wire _T_148 = _T_144 | _T_147; // @[el2_ifu_ifc_ctl.scala 136:53] + wire _T_149 = ~io_ifc_fetch_req_bf; // @[el2_ifu_ifc_ctl.scala 138:13] + wire _T_150 = wfm & _T_149; // @[el2_ifu_ifc_ctl.scala 138:11] + wire _T_151 = _T_148 | _T_150; // @[el2_ifu_ifc_ctl.scala 137:62] + wire _T_152 = _T_151 | idle; // @[el2_ifu_ifc_ctl.scala 138:35] + wire _T_154 = _T_152 & _T_2; // @[el2_ifu_ifc_ctl.scala 138:44] + wire _T_156 = ~iccm_acc_in_range_bf; // @[el2_ifu_ifc_ctl.scala 140:33] + wire [4:0] _T_159 = {io_ifc_fetch_addr_bf[30:27],1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_160 = io_dec_tlu_mrac_ff >> _T_159; // @[el2_ifu_ifc_ctl.scala 141:53] + reg _T_163; // @[el2_ifu_ifc_ctl.scala 143:32] + reg [30:0] _T_165; // @[Reg.scala 27:20] + assign io_ifc_fetch_addr_f = _T_165; // @[el2_ifu_ifc_ctl.scala 145:23] + assign io_ifc_fetch_addr_bf = _T_23[30:0]; // @[el2_ifu_ifc_ctl.scala 71:24] + assign io_ifc_fetch_req_f = _T_163; // @[el2_ifu_ifc_ctl.scala 143:22] + assign io_ifu_pmu_fetch_stall = wfm | _T_139; // @[el2_ifu_ifc_ctl.scala 129:26] + assign io_ifc_fetch_uncacheable_bf = ~_T_160[0]; // @[el2_ifu_ifc_ctl.scala 141:31] + assign io_ifc_fetch_req_bf = _T_40 & _T_41; // @[el2_ifu_ifc_ctl.scala 85:23] + assign io_ifc_fetch_req_bf_raw = ~idle; // @[el2_ifu_ifc_ctl.scala 83:27] + assign io_ifc_iccm_access_bf = _T_141[31:16] == 16'hee00; // @[el2_ifu_ifc_ctl.scala 135:25] + assign io_ifc_region_acc_fault_bf = _T_156 & iccm_acc_in_region_bf; // @[el2_ifu_ifc_ctl.scala 140:30] + assign io_ifc_dma_access_ok = _T_154 | dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctl.scala 136:24] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + dma_iccm_stall_any_f = _RAND_0[0:0]; + _RAND_1 = {1{`RANDOM}}; + miss_a = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + state = _RAND_2[1:0]; + _RAND_3 = {1{`RANDOM}}; + fb_write_f = _RAND_3[3:0]; + _RAND_4 = {1{`RANDOM}}; + fb_full_f = _RAND_4[0:0]; + _RAND_5 = {1{`RANDOM}}; + _T_163 = _RAND_5[0:0]; + _RAND_6 = {1{`RANDOM}}; + _T_165 = _RAND_6[30:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + dma_iccm_stall_any_f = 1'h0; + end + if (reset) begin + miss_a = 1'h0; + end + if (reset) begin + state = 2'h0; + end + if (reset) begin + fb_write_f = 4'h0; + end + if (reset) begin + fb_full_f = 1'h0; + end + if (reset) begin + _T_163 = 1'h0; + end + if (reset) begin + _T_165 = 31'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + dma_iccm_stall_any_f <= 1'h0; + end else begin + dma_iccm_stall_any_f <= io_dma_iccm_stall_any; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + miss_a <= 1'h0; + end else begin + miss_a <= _T_45 & _T_2; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + state <= 2'h0; + end else begin + state <= {next_state_1,next_state_0}; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + fb_write_f <= 4'h0; + end else begin + fb_write_f <= _T_125 | _T_122; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + fb_full_f <= 1'h0; + end else begin + fb_full_f <= fb_write_ns[3]; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_163 <= 1'h0; + end else begin + _T_163 <= io_ifc_fetch_req_bf; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_165 <= 31'h0; + end else if (fetch_bf_en) begin + _T_165 <= io_ifc_fetch_addr_bf; + end + end +endmodule diff --git a/src/main/scala/ifu/el2_ifu_ifc_ctl.scala b/src/main/scala/ifu/el2_ifu_ifc_ctl.scala index 7376ffb5..2982800f 100644 --- a/src/main/scala/ifu/el2_ifu_ifc_ctl.scala +++ b/src/main/scala/ifu/el2_ifu_ifc_ctl.scala @@ -3,7 +3,7 @@ import lib._ import chisel3._ import chisel3.util._ -class el2_ifu_ifc_ctrl extends Module with el2_lib with RequireAsyncReset { +class el2_ifu_ifc_ctl extends Module with el2_lib with RequireAsyncReset { val io = IO(new Bundle{ val free_clk = Input(Clock()) val active_clk = Input(Bool()) @@ -146,5 +146,5 @@ class el2_ifu_ifc_ctrl extends Module with el2_lib with RequireAsyncReset { } object ifu_ifc extends App { - println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_ifc_ctrl())) + println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_ifc_ctl())) } diff --git a/target/scala-2.12/classes/META-INF/chisel-module-template.kotlin_module b/target/scala-2.12/classes/META-INF/chisel-module-template.kotlin_module new file mode 100644 index 00000000..a49347af Binary files /dev/null and b/target/scala-2.12/classes/META-INF/chisel-module-template.kotlin_module differ diff --git a/target/scala-2.12/classes/ifu/el2_ifu_ifc_ctrl$$anon$1.class b/target/scala-2.12/classes/ifu/el2_ifu_ifc_ctl$$anon$1.class similarity index 81% rename from target/scala-2.12/classes/ifu/el2_ifu_ifc_ctrl$$anon$1.class rename to target/scala-2.12/classes/ifu/el2_ifu_ifc_ctl$$anon$1.class index d2a8d78c..0be8117f 100644 Binary files a/target/scala-2.12/classes/ifu/el2_ifu_ifc_ctrl$$anon$1.class and b/target/scala-2.12/classes/ifu/el2_ifu_ifc_ctl$$anon$1.class differ diff --git a/target/scala-2.12/classes/ifu/el2_ifu_ifc_ctrl.class b/target/scala-2.12/classes/ifu/el2_ifu_ifc_ctl.class similarity index 95% rename from target/scala-2.12/classes/ifu/el2_ifu_ifc_ctrl.class rename to target/scala-2.12/classes/ifu/el2_ifu_ifc_ctl.class index 357485e6..bb6e2092 100644 Binary files a/target/scala-2.12/classes/ifu/el2_ifu_ifc_ctrl.class and b/target/scala-2.12/classes/ifu/el2_ifu_ifc_ctl.class differ diff --git a/target/scala-2.12/classes/ifu/ifu_ifc$.class b/target/scala-2.12/classes/ifu/ifu_ifc$.class index ecf2a42c..2ecfb3ad 100644 Binary files a/target/scala-2.12/classes/ifu/ifu_ifc$.class and b/target/scala-2.12/classes/ifu/ifu_ifc$.class differ