diff --git a/dec.anno.json b/dec.anno.json
index 859bcab3..7af4fcf9 100644
--- a/dec.anno.json
+++ b/dec.anno.json
@@ -516,49 +516,6 @@
       "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist"
     ]
   },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~dec|dec>io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d",
-    "sources":[
-      "~dec|dec>io_lsu_load_stall_any",
-      "~dec|dec>io_dec_dma_dctl_dma_dma_dccm_stall_any",
-      "~dec|dec>io_lsu_store_stall_any",
-      "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m",
-      "~dec|dec>io_dec_dbg_dbg_dctl_dbg_cmd_wrdata",
-      "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid",
-      "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error",
-      "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag",
-      "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid",
-      "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid",
-      "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type",
-      "~dec|dec>io_mpc_reset_run_req",
-      "~dec|dec>io_lsu_fastint_stall_any",
-      "~dec|dec>io_lsu_fir_error",
-      "~dec|dec>io_lsu_error_pkt_r_bits_single_ecc_error",
-      "~dec|dec>io_dbg_halt_req",
-      "~dec|dec>io_lsu_error_pkt_r_bits_inst_type",
-      "~dec|dec>io_lsu_error_pkt_r_valid",
-      "~dec|dec>io_dec_pic_mhwakeup",
-      "~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_error_r",
-      "~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_start_error_r",
-      "~dec|dec>io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any",
-      "~dec|dec>io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any",
-      "~dec|dec>io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle",
-      "~dec|dec>io_lsu_idle_any",
-      "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf",
-      "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc",
-      "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr",
-      "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr",
-      "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write",
-      "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error",
-      "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error",
-      "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret",
-      "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset",
-      "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid",
-      "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist",
-      "~dec|dec>io_lsu_result_corr_r"
-    ]
-  },
   {
     "class":"firrtl.transforms.CombinationalPath",
     "sink":"~dec|dec>io_dec_exu_decode_exu_i0_ap_sbext",
@@ -654,6 +611,49 @@
       "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset"
     ]
   },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~dec|dec>io_dec_i0_decode_d",
+    "sources":[
+      "~dec|dec>io_lsu_load_stall_any",
+      "~dec|dec>io_dec_dma_dctl_dma_dma_dccm_stall_any",
+      "~dec|dec>io_lsu_store_stall_any",
+      "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m",
+      "~dec|dec>io_dec_dbg_dbg_dctl_dbg_cmd_wrdata",
+      "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid",
+      "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error",
+      "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag",
+      "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid",
+      "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid",
+      "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type",
+      "~dec|dec>io_mpc_reset_run_req",
+      "~dec|dec>io_lsu_fastint_stall_any",
+      "~dec|dec>io_lsu_fir_error",
+      "~dec|dec>io_lsu_error_pkt_r_bits_single_ecc_error",
+      "~dec|dec>io_dbg_halt_req",
+      "~dec|dec>io_lsu_error_pkt_r_bits_inst_type",
+      "~dec|dec>io_lsu_error_pkt_r_valid",
+      "~dec|dec>io_dec_pic_mhwakeup",
+      "~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_error_r",
+      "~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_start_error_r",
+      "~dec|dec>io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any",
+      "~dec|dec>io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any",
+      "~dec|dec>io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle",
+      "~dec|dec>io_lsu_idle_any",
+      "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf",
+      "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc",
+      "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr",
+      "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr",
+      "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write",
+      "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error",
+      "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error",
+      "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret",
+      "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset",
+      "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid",
+      "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist",
+      "~dec|dec>io_lsu_result_corr_r"
+    ]
+  },
   {
     "class":"firrtl.transforms.CombinationalPath",
     "sink":"~dec|dec>io_dec_exu_decode_exu_mul_p_bits_low",
diff --git a/dec.fir b/dec.fir
index 81fec2ea..56441765 100644
--- a/dec.fir
+++ b/dec.fir
@@ -4862,83 +4862,83 @@ circuit dec :
   module dec_decode_ctl : 
     input clock : Clock
     input reset : AsyncReset
-    output io : {flip decode_exu : {flip dec_data_en : UInt<2>, flip dec_ctl_en : UInt<2>, flip i0_ap : {clz : UInt<1>, ctz : UInt<1>, pcnt : UInt<1>, sext_b : UInt<1>, sext_h : UInt<1>, slo : UInt<1>, sro : UInt<1>, min : UInt<1>, max : UInt<1>, pack : UInt<1>, packu : UInt<1>, packh : UInt<1>, rol : UInt<1>, ror : UInt<1>, grev : UInt<1>, gorc : UInt<1>, zbb : UInt<1>, sbset : UInt<1>, sbclr : UInt<1>, sbinv : UInt<1>, sbext : UInt<1>, sh1add : UInt<1>, sh2add : UInt<1>, sh3add : UInt<1>, zba : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}}, flip i0_predict_fghr_d : UInt<8>, flip i0_predict_index_d : UInt<8>, flip i0_predict_btag_d : UInt<5>, flip dec_i0_rs1_en_d : UInt<1>, flip dec_i0_branch_d : UInt<1>, flip dec_i0_rs2_en_d : UInt<1>, flip dec_i0_immed_d : UInt<32>, flip dec_i0_result_r : UInt<32>, flip dec_qual_lsu_d : UInt<1>, flip dec_i0_select_pc_d : UInt<1>, flip dec_i0_rs1_bypass_en_d : UInt<4>, flip dec_i0_rs2_bypass_en_d : UInt<4>, flip mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, gorc : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, flip pred_correct_npc_x : UInt<31>, flip dec_extint_stall : UInt<1>, exu_i0_result_x : UInt<32>, exu_csr_rs1_x : UInt<32>}, flip dec_alu : {flip dec_i0_alu_decode_d : UInt<1>, flip dec_csr_ren_d : UInt<1>, flip dec_i0_br_immed_d : UInt<12>, exu_i0_pc_x : UInt<31>}, flip dec_div : {flip div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, flip dec_div_cancel : UInt<1>}, flip dctl_busbuff : {lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>}, dctl_dma : {flip dma_dccm_stall_any : UInt<1>}, flip dec_aln : {flip dec_i0_decode_d : UInt<1>, ifu_i0_cinst : UInt<16>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<32>}, flip dec_tlu_trace_disable : UInt<1>, flip dec_debug_valid_d : UInt<1>, flip dec_tlu_flush_extint : UInt<1>, flip dec_tlu_force_halt : UInt<1>, dec_i0_inst_wb : UInt<32>, dec_i0_pc_wb : UInt<31>, flip dec_i0_trigger_match_d : UInt<4>, flip dec_tlu_wr_pause_r : UInt<1>, flip dec_tlu_pipelining_disable : UInt<1>, flip lsu_trigger_match_m : UInt<4>, flip lsu_pmu_misaligned_m : UInt<1>, flip dec_tlu_debug_stall : UInt<1>, flip dec_tlu_flush_leak_one_r : UInt<1>, flip dec_debug_fence_d : UInt<1>, flip dec_i0_icaf_d : UInt<1>, flip dec_i0_icaf_second_d : UInt<1>, flip dec_i0_icaf_type_d : UInt<2>, flip dec_i0_dbecc_d : UInt<1>, flip dec_i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, flip dec_i0_bp_index : UInt<8>, flip dec_i0_bp_fghr : UInt<8>, flip dec_i0_bp_btag : UInt<5>, flip dec_i0_bp_fa_index : UInt<9>, flip lsu_idle_any : UInt<1>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip exu_div_wren : UInt<1>, flip dec_tlu_i0_kill_writeb_wb : UInt<1>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_i0_kill_writeb_r : UInt<1>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_pause_r : UInt<1>, flip dec_tlu_presync_d : UInt<1>, flip dec_tlu_postsync_d : UInt<1>, flip dec_i0_pc4_d : UInt<1>, flip dec_csr_rddata_d : UInt<32>, flip dec_csr_legal_d : UInt<1>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip exu_flush_final : UInt<1>, flip dec_i0_instr_d : UInt<32>, flip dec_ib0_valid_d : UInt<1>, flip active_clk : Clock, flip free_l2clk : Clock, flip clk_override : UInt<1>, dec_i0_rs1_d : UInt<5>, dec_i0_rs2_d : UInt<5>, dec_i0_waddr_r : UInt<5>, dec_i0_wen_r : UInt<1>, dec_i0_wdata_r : UInt<32>, lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, div_waddr_wb : UInt<5>, dec_lsu_valid_raw_d : UInt<1>, dec_lsu_offset_d : UInt<12>, dec_csr_wen_unq_d : UInt<1>, dec_csr_any_unq_d : UInt<1>, dec_csr_rdaddr_d : UInt<12>, dec_csr_wen_r : UInt<1>, dec_csr_wraddr_r : UInt<12>, dec_csr_wrdata_r : UInt<32>, dec_csr_stall_int_ff : UInt<1>, dec_tlu_i0_valid_r : UInt<1>, dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, dec_tlu_i0_pc_r : UInt<31>, dec_illegal_inst : UInt<32>, dec_fa_error_index : UInt<9>, dec_pmu_instr_decoded : UInt<1>, dec_pmu_decode_stall : UInt<1>, dec_pmu_presync_stall : UInt<1>, dec_pmu_postsync_stall : UInt<1>, dec_nonblock_load_wen : UInt<1>, dec_nonblock_load_waddr : UInt<5>, dec_pause_state : UInt<1>, dec_pause_state_cg : UInt<1>, dec_div_active : UInt<1>, flip scan_mode : UInt<1>}
+    output io : {flip decode_exu : {flip dec_data_en : UInt<2>, flip dec_ctl_en : UInt<2>, flip i0_ap : {clz : UInt<1>, ctz : UInt<1>, pcnt : UInt<1>, sext_b : UInt<1>, sext_h : UInt<1>, slo : UInt<1>, sro : UInt<1>, min : UInt<1>, max : UInt<1>, pack : UInt<1>, packu : UInt<1>, packh : UInt<1>, rol : UInt<1>, ror : UInt<1>, grev : UInt<1>, gorc : UInt<1>, zbb : UInt<1>, sbset : UInt<1>, sbclr : UInt<1>, sbinv : UInt<1>, sbext : UInt<1>, sh1add : UInt<1>, sh2add : UInt<1>, sh3add : UInt<1>, zba : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}}, flip i0_predict_fghr_d : UInt<8>, flip i0_predict_index_d : UInt<8>, flip i0_predict_btag_d : UInt<5>, flip dec_i0_rs1_en_d : UInt<1>, flip dec_i0_branch_d : UInt<1>, flip dec_i0_rs2_en_d : UInt<1>, flip dec_i0_immed_d : UInt<32>, flip dec_i0_result_r : UInt<32>, flip dec_qual_lsu_d : UInt<1>, flip dec_i0_select_pc_d : UInt<1>, flip dec_i0_rs1_bypass_en_d : UInt<4>, flip dec_i0_rs2_bypass_en_d : UInt<4>, flip mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, gorc : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, flip pred_correct_npc_x : UInt<31>, flip dec_extint_stall : UInt<1>, exu_i0_result_x : UInt<32>, exu_csr_rs1_x : UInt<32>}, flip dec_alu : {flip dec_i0_alu_decode_d : UInt<1>, flip dec_csr_ren_d : UInt<1>, flip dec_i0_br_immed_d : UInt<12>, exu_i0_pc_x : UInt<31>}, flip dec_div : {flip div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, flip dec_div_cancel : UInt<1>}, flip dctl_busbuff : {lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>}, dctl_dma : {flip dma_dccm_stall_any : UInt<1>}, flip dec_aln : {ifu_i0_cinst : UInt<16>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<32>}, flip dec_tlu_trace_disable : UInt<1>, flip dec_debug_valid_d : UInt<1>, flip dec_tlu_flush_extint : UInt<1>, flip dec_tlu_force_halt : UInt<1>, dec_i0_inst_wb : UInt<32>, dec_i0_pc_wb : UInt<31>, flip dec_i0_trigger_match_d : UInt<4>, flip dec_tlu_wr_pause_r : UInt<1>, flip dec_tlu_pipelining_disable : UInt<1>, flip lsu_trigger_match_m : UInt<4>, flip lsu_pmu_misaligned_m : UInt<1>, flip dec_tlu_debug_stall : UInt<1>, flip dec_tlu_flush_leak_one_r : UInt<1>, flip dec_debug_fence_d : UInt<1>, flip dec_i0_icaf_d : UInt<1>, flip dec_i0_icaf_second_d : UInt<1>, flip dec_i0_icaf_type_d : UInt<2>, flip dec_i0_dbecc_d : UInt<1>, flip dec_i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, flip dec_i0_bp_index : UInt<8>, flip dec_i0_bp_fghr : UInt<8>, flip dec_i0_bp_btag : UInt<5>, flip dec_i0_bp_fa_index : UInt<9>, flip lsu_idle_any : UInt<1>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip exu_div_wren : UInt<1>, flip dec_tlu_i0_kill_writeb_wb : UInt<1>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_i0_kill_writeb_r : UInt<1>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_pause_r : UInt<1>, flip dec_tlu_presync_d : UInt<1>, flip dec_tlu_postsync_d : UInt<1>, flip dec_i0_pc4_d : UInt<1>, flip dec_csr_rddata_d : UInt<32>, flip dec_csr_legal_d : UInt<1>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip exu_flush_final : UInt<1>, flip dec_i0_instr_d : UInt<32>, flip dec_ib0_valid_d : UInt<1>, flip active_clk : Clock, flip free_l2clk : Clock, flip clk_override : UInt<1>, dec_i0_rs1_d : UInt<5>, dec_i0_rs2_d : UInt<5>, dec_i0_waddr_r : UInt<5>, dec_i0_wen_r : UInt<1>, dec_i0_wdata_r : UInt<32>, lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, div_waddr_wb : UInt<5>, dec_lsu_valid_raw_d : UInt<1>, dec_lsu_offset_d : UInt<12>, dec_csr_wen_unq_d : UInt<1>, dec_csr_any_unq_d : UInt<1>, dec_csr_rdaddr_d : UInt<12>, dec_csr_wen_r : UInt<1>, dec_csr_wraddr_r : UInt<12>, dec_csr_wrdata_r : UInt<32>, dec_csr_stall_int_ff : UInt<1>, dec_tlu_i0_valid_r : UInt<1>, dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, dec_tlu_i0_pc_r : UInt<31>, dec_illegal_inst : UInt<32>, dec_fa_error_index : UInt<9>, dec_pmu_instr_decoded : UInt<1>, dec_pmu_decode_stall : UInt<1>, dec_pmu_presync_stall : UInt<1>, dec_pmu_postsync_stall : UInt<1>, dec_nonblock_load_wen : UInt<1>, dec_nonblock_load_waddr : UInt<5>, dec_pause_state : UInt<1>, dec_pause_state_cg : UInt<1>, dec_div_active : UInt<1>, flip scan_mode : UInt<1>, dec_i0_decode_d : UInt<1>}
     
-    wire _T : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, gorc : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}} @[dec_decode_ctl.scala 117:40]
-    _T.bits.bfp <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40]
-    _T.bits.crc32c_w <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40]
-    _T.bits.crc32c_h <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40]
-    _T.bits.crc32c_b <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40]
-    _T.bits.crc32_w <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40]
-    _T.bits.crc32_h <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40]
-    _T.bits.crc32_b <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40]
-    _T.bits.unshfl <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40]
-    _T.bits.shfl <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40]
-    _T.bits.gorc <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40]
-    _T.bits.grev <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40]
-    _T.bits.clmulr <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40]
-    _T.bits.clmulh <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40]
-    _T.bits.clmul <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40]
-    _T.bits.bdep <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40]
-    _T.bits.bext <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40]
-    _T.bits.low <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40]
-    _T.bits.rs2_sign <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40]
-    _T.bits.rs1_sign <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40]
-    _T.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40]
-    io.decode_exu.mul_p.bits.bfp <= _T.bits.bfp @[dec_decode_ctl.scala 117:25]
-    io.decode_exu.mul_p.bits.crc32c_w <= _T.bits.crc32c_w @[dec_decode_ctl.scala 117:25]
-    io.decode_exu.mul_p.bits.crc32c_h <= _T.bits.crc32c_h @[dec_decode_ctl.scala 117:25]
-    io.decode_exu.mul_p.bits.crc32c_b <= _T.bits.crc32c_b @[dec_decode_ctl.scala 117:25]
-    io.decode_exu.mul_p.bits.crc32_w <= _T.bits.crc32_w @[dec_decode_ctl.scala 117:25]
-    io.decode_exu.mul_p.bits.crc32_h <= _T.bits.crc32_h @[dec_decode_ctl.scala 117:25]
-    io.decode_exu.mul_p.bits.crc32_b <= _T.bits.crc32_b @[dec_decode_ctl.scala 117:25]
-    io.decode_exu.mul_p.bits.unshfl <= _T.bits.unshfl @[dec_decode_ctl.scala 117:25]
-    io.decode_exu.mul_p.bits.shfl <= _T.bits.shfl @[dec_decode_ctl.scala 117:25]
-    io.decode_exu.mul_p.bits.gorc <= _T.bits.gorc @[dec_decode_ctl.scala 117:25]
-    io.decode_exu.mul_p.bits.grev <= _T.bits.grev @[dec_decode_ctl.scala 117:25]
-    io.decode_exu.mul_p.bits.clmulr <= _T.bits.clmulr @[dec_decode_ctl.scala 117:25]
-    io.decode_exu.mul_p.bits.clmulh <= _T.bits.clmulh @[dec_decode_ctl.scala 117:25]
-    io.decode_exu.mul_p.bits.clmul <= _T.bits.clmul @[dec_decode_ctl.scala 117:25]
-    io.decode_exu.mul_p.bits.bdep <= _T.bits.bdep @[dec_decode_ctl.scala 117:25]
-    io.decode_exu.mul_p.bits.bext <= _T.bits.bext @[dec_decode_ctl.scala 117:25]
-    io.decode_exu.mul_p.bits.low <= _T.bits.low @[dec_decode_ctl.scala 117:25]
-    io.decode_exu.mul_p.bits.rs2_sign <= _T.bits.rs2_sign @[dec_decode_ctl.scala 117:25]
-    io.decode_exu.mul_p.bits.rs1_sign <= _T.bits.rs1_sign @[dec_decode_ctl.scala 117:25]
-    io.decode_exu.mul_p.valid <= _T.valid @[dec_decode_ctl.scala 117:25]
+    wire _T : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, gorc : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}} @[dec_decode_ctl.scala 118:40]
+    _T.bits.bfp <= UInt<1>("h00") @[dec_decode_ctl.scala 118:40]
+    _T.bits.crc32c_w <= UInt<1>("h00") @[dec_decode_ctl.scala 118:40]
+    _T.bits.crc32c_h <= UInt<1>("h00") @[dec_decode_ctl.scala 118:40]
+    _T.bits.crc32c_b <= UInt<1>("h00") @[dec_decode_ctl.scala 118:40]
+    _T.bits.crc32_w <= UInt<1>("h00") @[dec_decode_ctl.scala 118:40]
+    _T.bits.crc32_h <= UInt<1>("h00") @[dec_decode_ctl.scala 118:40]
+    _T.bits.crc32_b <= UInt<1>("h00") @[dec_decode_ctl.scala 118:40]
+    _T.bits.unshfl <= UInt<1>("h00") @[dec_decode_ctl.scala 118:40]
+    _T.bits.shfl <= UInt<1>("h00") @[dec_decode_ctl.scala 118:40]
+    _T.bits.gorc <= UInt<1>("h00") @[dec_decode_ctl.scala 118:40]
+    _T.bits.grev <= UInt<1>("h00") @[dec_decode_ctl.scala 118:40]
+    _T.bits.clmulr <= UInt<1>("h00") @[dec_decode_ctl.scala 118:40]
+    _T.bits.clmulh <= UInt<1>("h00") @[dec_decode_ctl.scala 118:40]
+    _T.bits.clmul <= UInt<1>("h00") @[dec_decode_ctl.scala 118:40]
+    _T.bits.bdep <= UInt<1>("h00") @[dec_decode_ctl.scala 118:40]
+    _T.bits.bext <= UInt<1>("h00") @[dec_decode_ctl.scala 118:40]
+    _T.bits.low <= UInt<1>("h00") @[dec_decode_ctl.scala 118:40]
+    _T.bits.rs2_sign <= UInt<1>("h00") @[dec_decode_ctl.scala 118:40]
+    _T.bits.rs1_sign <= UInt<1>("h00") @[dec_decode_ctl.scala 118:40]
+    _T.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 118:40]
+    io.decode_exu.mul_p.bits.bfp <= _T.bits.bfp @[dec_decode_ctl.scala 118:25]
+    io.decode_exu.mul_p.bits.crc32c_w <= _T.bits.crc32c_w @[dec_decode_ctl.scala 118:25]
+    io.decode_exu.mul_p.bits.crc32c_h <= _T.bits.crc32c_h @[dec_decode_ctl.scala 118:25]
+    io.decode_exu.mul_p.bits.crc32c_b <= _T.bits.crc32c_b @[dec_decode_ctl.scala 118:25]
+    io.decode_exu.mul_p.bits.crc32_w <= _T.bits.crc32_w @[dec_decode_ctl.scala 118:25]
+    io.decode_exu.mul_p.bits.crc32_h <= _T.bits.crc32_h @[dec_decode_ctl.scala 118:25]
+    io.decode_exu.mul_p.bits.crc32_b <= _T.bits.crc32_b @[dec_decode_ctl.scala 118:25]
+    io.decode_exu.mul_p.bits.unshfl <= _T.bits.unshfl @[dec_decode_ctl.scala 118:25]
+    io.decode_exu.mul_p.bits.shfl <= _T.bits.shfl @[dec_decode_ctl.scala 118:25]
+    io.decode_exu.mul_p.bits.gorc <= _T.bits.gorc @[dec_decode_ctl.scala 118:25]
+    io.decode_exu.mul_p.bits.grev <= _T.bits.grev @[dec_decode_ctl.scala 118:25]
+    io.decode_exu.mul_p.bits.clmulr <= _T.bits.clmulr @[dec_decode_ctl.scala 118:25]
+    io.decode_exu.mul_p.bits.clmulh <= _T.bits.clmulh @[dec_decode_ctl.scala 118:25]
+    io.decode_exu.mul_p.bits.clmul <= _T.bits.clmul @[dec_decode_ctl.scala 118:25]
+    io.decode_exu.mul_p.bits.bdep <= _T.bits.bdep @[dec_decode_ctl.scala 118:25]
+    io.decode_exu.mul_p.bits.bext <= _T.bits.bext @[dec_decode_ctl.scala 118:25]
+    io.decode_exu.mul_p.bits.low <= _T.bits.low @[dec_decode_ctl.scala 118:25]
+    io.decode_exu.mul_p.bits.rs2_sign <= _T.bits.rs2_sign @[dec_decode_ctl.scala 118:25]
+    io.decode_exu.mul_p.bits.rs1_sign <= _T.bits.rs1_sign @[dec_decode_ctl.scala 118:25]
+    io.decode_exu.mul_p.valid <= _T.valid @[dec_decode_ctl.scala 118:25]
     wire leak1_i1_stall_in : UInt<1>
     leak1_i1_stall_in <= UInt<1>("h00")
     wire leak1_i0_stall_in : UInt<1>
     leak1_i0_stall_in <= UInt<1>("h00")
-    wire i0r : {rs1 : UInt<5>, rs2 : UInt<5>, rd : UInt<5>} @[dec_decode_ctl.scala 121:37]
-    wire d_t : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 122:37]
-    wire x_t : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 123:37]
-    wire x_t_in : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 124:37]
-    wire r_t : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 125:37]
-    wire r_t_in : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 126:37]
-    wire d_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 127:37]
-    wire x_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 128:37]
-    wire r_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 129:37]
-    wire r_d_in : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 130:37]
-    wire wbd : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 131:37]
-    wire i0_d_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 132:37]
-    wire i0_rs1_class_d : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 133:37]
-    wire i0_rs2_class_d : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 134:37]
+    wire i0r : {rs1 : UInt<5>, rs2 : UInt<5>, rd : UInt<5>} @[dec_decode_ctl.scala 122:37]
+    wire d_t : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 123:37]
+    wire x_t : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 124:37]
+    wire x_t_in : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 125:37]
+    wire r_t : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 126:37]
+    wire r_t_in : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 127:37]
+    wire d_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 128:37]
+    wire x_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 129:37]
+    wire r_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 130:37]
+    wire r_d_in : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 131:37]
+    wire wbd : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 132:37]
+    wire i0_d_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 133:37]
+    wire i0_rs1_class_d : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 134:37]
+    wire i0_rs2_class_d : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 135:37]
     wire i0_rs1_depth_d : UInt<2>
     i0_rs1_depth_d <= UInt<1>("h00")
     wire i0_rs2_depth_d : UInt<2>
     i0_rs2_depth_d <= UInt<1>("h00")
     wire cam_wen : UInt<4>
     cam_wen <= UInt<1>("h00")
-    wire cam : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}[4] @[dec_decode_ctl.scala 138:37]
+    wire cam : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}[4] @[dec_decode_ctl.scala 139:37]
     wire cam_write : UInt<1>
     cam_write <= UInt<1>("h00")
-    wire cam_inv_reset_val : UInt<1>[4] @[dec_decode_ctl.scala 140:37]
-    wire cam_data_reset_val : UInt<1>[4] @[dec_decode_ctl.scala 141:37]
-    wire nonblock_load_write : UInt<1>[4] @[dec_decode_ctl.scala 142:37]
-    wire cam_raw : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}[4] @[dec_decode_ctl.scala 143:37]
-    wire cam_in : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}[4] @[dec_decode_ctl.scala 144:37]
-    wire i0_dp : {clz : UInt<1>, ctz : UInt<1>, pcnt : UInt<1>, sext_b : UInt<1>, sext_h : UInt<1>, slo : UInt<1>, sro : UInt<1>, min : UInt<1>, max : UInt<1>, pack : UInt<1>, packu : UInt<1>, packh : UInt<1>, rol : UInt<1>, ror : UInt<1>, grev : UInt<1>, gorc : UInt<1>, zbb : UInt<1>, sbset : UInt<1>, sbclr : UInt<1>, sbinv : UInt<1>, sbext : UInt<1>, zbs : UInt<1>, bext : UInt<1>, bdep : UInt<1>, zbe : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, zbc : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, zbp : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, zbr : UInt<1>, bfp : UInt<1>, zbf : UInt<1>, sh1add : UInt<1>, sh2add : UInt<1>, sh3add : UInt<1>, zba : UInt<1>, alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[dec_decode_ctl.scala 145:37]
-    wire i0_dp_raw : {clz : UInt<1>, ctz : UInt<1>, pcnt : UInt<1>, sext_b : UInt<1>, sext_h : UInt<1>, slo : UInt<1>, sro : UInt<1>, min : UInt<1>, max : UInt<1>, pack : UInt<1>, packu : UInt<1>, packh : UInt<1>, rol : UInt<1>, ror : UInt<1>, grev : UInt<1>, gorc : UInt<1>, zbb : UInt<1>, sbset : UInt<1>, sbclr : UInt<1>, sbinv : UInt<1>, sbext : UInt<1>, zbs : UInt<1>, bext : UInt<1>, bdep : UInt<1>, zbe : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, zbc : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, zbp : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, zbr : UInt<1>, bfp : UInt<1>, zbf : UInt<1>, sh1add : UInt<1>, sh2add : UInt<1>, sh3add : UInt<1>, zba : UInt<1>, alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[dec_decode_ctl.scala 146:37]
+    wire cam_inv_reset_val : UInt<1>[4] @[dec_decode_ctl.scala 141:37]
+    wire cam_data_reset_val : UInt<1>[4] @[dec_decode_ctl.scala 142:37]
+    wire nonblock_load_write : UInt<1>[4] @[dec_decode_ctl.scala 143:37]
+    wire cam_raw : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}[4] @[dec_decode_ctl.scala 144:37]
+    wire cam_in : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}[4] @[dec_decode_ctl.scala 145:37]
+    wire i0_dp : {clz : UInt<1>, ctz : UInt<1>, pcnt : UInt<1>, sext_b : UInt<1>, sext_h : UInt<1>, slo : UInt<1>, sro : UInt<1>, min : UInt<1>, max : UInt<1>, pack : UInt<1>, packu : UInt<1>, packh : UInt<1>, rol : UInt<1>, ror : UInt<1>, grev : UInt<1>, gorc : UInt<1>, zbb : UInt<1>, sbset : UInt<1>, sbclr : UInt<1>, sbinv : UInt<1>, sbext : UInt<1>, zbs : UInt<1>, bext : UInt<1>, bdep : UInt<1>, zbe : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, zbc : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, zbp : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, zbr : UInt<1>, bfp : UInt<1>, zbf : UInt<1>, sh1add : UInt<1>, sh2add : UInt<1>, sh3add : UInt<1>, zba : UInt<1>, alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[dec_decode_ctl.scala 146:37]
+    wire i0_dp_raw : {clz : UInt<1>, ctz : UInt<1>, pcnt : UInt<1>, sext_b : UInt<1>, sext_h : UInt<1>, slo : UInt<1>, sro : UInt<1>, min : UInt<1>, max : UInt<1>, pack : UInt<1>, packu : UInt<1>, packh : UInt<1>, rol : UInt<1>, ror : UInt<1>, grev : UInt<1>, gorc : UInt<1>, zbb : UInt<1>, sbset : UInt<1>, sbclr : UInt<1>, sbinv : UInt<1>, sbext : UInt<1>, zbs : UInt<1>, bext : UInt<1>, bdep : UInt<1>, zbe : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, zbc : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, zbp : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, zbr : UInt<1>, bfp : UInt<1>, zbf : UInt<1>, sh1add : UInt<1>, sh2add : UInt<1>, sh3add : UInt<1>, zba : UInt<1>, alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[dec_decode_ctl.scala 147:37]
     wire i0_rs1bypass : UInt<3>
     i0_rs1bypass <= UInt<1>("h00")
     wire i0_rs2bypass : UInt<3>
@@ -5062,7 +5062,7 @@ circuit dec :
       _T_4 <= leak1_i1_stall_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
     _T_1 <= _T_4 @[lib.scala 451:16]
-    leak1_i1_stall <= _T_1 @[dec_decode_ctl.scala 206:35]
+    leak1_i1_stall <= _T_1 @[dec_decode_ctl.scala 208:35]
     wire _T_5 : UInt
     _T_5 <= UInt<1>("h00")
     node _T_6 = xor(leak1_i0_stall_in, _T_5) @[lib.scala 448:21]
@@ -5072,7 +5072,7 @@ circuit dec :
       _T_8 <= leak1_i0_stall_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
     _T_5 <= _T_8 @[lib.scala 451:16]
-    leak1_i0_stall <= _T_5 @[dec_decode_ctl.scala 207:35]
+    leak1_i0_stall <= _T_5 @[dec_decode_ctl.scala 209:35]
     wire _T_9 : UInt<1>
     _T_9 <= UInt<1>("h00")
     node _T_10 = xor(io.dec_tlu_flush_extint, _T_9) @[lib.scala 470:21]
@@ -5082,7 +5082,7 @@ circuit dec :
       _T_12 <= io.dec_tlu_flush_extint @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
     _T_9 <= _T_12 @[lib.scala 473:16]
-    io.decode_exu.dec_extint_stall <= _T_9 @[dec_decode_ctl.scala 208:35]
+    io.decode_exu.dec_extint_stall <= _T_9 @[dec_decode_ctl.scala 210:35]
     wire _T_13 : UInt<1>
     _T_13 <= UInt<1>("h00")
     node _T_14 = xor(pause_state_in, _T_13) @[lib.scala 470:21]
@@ -5092,7 +5092,7 @@ circuit dec :
       _T_16 <= pause_state_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
     _T_13 <= _T_16 @[lib.scala 473:16]
-    pause_stall <= _T_13 @[dec_decode_ctl.scala 209:35]
+    pause_stall <= _T_13 @[dec_decode_ctl.scala 211:35]
     wire _T_17 : UInt<1>
     _T_17 <= UInt<1>("h00")
     node _T_18 = xor(io.dec_tlu_wr_pause_r, _T_17) @[lib.scala 470:21]
@@ -5102,7 +5102,7 @@ circuit dec :
       _T_20 <= io.dec_tlu_wr_pause_r @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
     _T_17 <= _T_20 @[lib.scala 473:16]
-    tlu_wr_pause_r1 <= _T_17 @[dec_decode_ctl.scala 210:35]
+    tlu_wr_pause_r1 <= _T_17 @[dec_decode_ctl.scala 212:35]
     wire _T_21 : UInt
     _T_21 <= UInt<1>("h00")
     node _T_22 = xor(tlu_wr_pause_r1, _T_21) @[lib.scala 448:21]
@@ -5112,7 +5112,7 @@ circuit dec :
       _T_24 <= tlu_wr_pause_r1 @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
     _T_21 <= _T_24 @[lib.scala 451:16]
-    tlu_wr_pause_r2 <= _T_21 @[dec_decode_ctl.scala 211:35]
+    tlu_wr_pause_r2 <= _T_21 @[dec_decode_ctl.scala 213:35]
     wire _T_25 : UInt
     _T_25 <= UInt<1>("h00")
     node _T_26 = xor(illegal_lockout_in, _T_25) @[lib.scala 448:21]
@@ -5122,7 +5122,7 @@ circuit dec :
       _T_28 <= illegal_lockout_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
     _T_25 <= _T_28 @[lib.scala 451:16]
-    illegal_lockout <= _T_25 @[dec_decode_ctl.scala 212:35]
+    illegal_lockout <= _T_25 @[dec_decode_ctl.scala 214:35]
     wire _T_29 : UInt
     _T_29 <= UInt<1>("h00")
     node _T_30 = xor(ps_stall_in, _T_29) @[lib.scala 448:21]
@@ -5132,7 +5132,7 @@ circuit dec :
       _T_32 <= ps_stall_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
     _T_29 <= _T_32 @[lib.scala 451:16]
-    postsync_stall <= _T_29 @[dec_decode_ctl.scala 213:35]
+    postsync_stall <= _T_29 @[dec_decode_ctl.scala 215:35]
     wire lsu_trigger_match_r : UInt
     lsu_trigger_match_r <= UInt<1>("h00")
     node _T_33 = xor(io.lsu_trigger_match_m, lsu_trigger_match_r) @[lib.scala 448:21]
@@ -5160,7 +5160,7 @@ circuit dec :
       _T_42 <= div_active_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
     _T_39 <= _T_42 @[lib.scala 473:16]
-    io.dec_div_active <= _T_39 @[dec_decode_ctl.scala 217:35]
+    io.dec_div_active <= _T_39 @[dec_decode_ctl.scala 219:35]
     wire _T_43 : UInt<1>
     _T_43 <= UInt<1>("h00")
     node _T_44 = xor(io.exu_flush_final, _T_43) @[lib.scala 470:21]
@@ -5170,7 +5170,7 @@ circuit dec :
       _T_46 <= io.exu_flush_final @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
     _T_43 <= _T_46 @[lib.scala 473:16]
-    flush_final_r <= _T_43 @[dec_decode_ctl.scala 218:35]
+    flush_final_r <= _T_43 @[dec_decode_ctl.scala 220:35]
     wire debug_valid_x : UInt<1>
     debug_valid_x <= UInt<1>("h00")
     node _T_47 = xor(io.dec_debug_valid_d, debug_valid_x) @[lib.scala 470:21]
@@ -5180,439 +5180,439 @@ circuit dec :
       _T_49 <= io.dec_debug_valid_d @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
     debug_valid_x <= _T_49 @[lib.scala 473:16]
-    node i0_icaf_d = or(io.dec_i0_icaf_d, io.dec_i0_dbecc_d) @[dec_decode_ctl.scala 220:43]
-    node _T_50 = eq(leak1_mode, UInt<1>("h00")) @[dec_decode_ctl.scala 222:82]
-    node _T_51 = and(io.dec_i0_brp.valid, _T_50) @[dec_decode_ctl.scala 222:80]
-    node _T_52 = eq(i0_icaf_d, UInt<1>("h00")) @[dec_decode_ctl.scala 222:96]
-    node _T_53 = and(_T_51, _T_52) @[dec_decode_ctl.scala 222:94]
-    i0_brp_valid <= _T_53 @[dec_decode_ctl.scala 222:57]
-    io.decode_exu.dec_i0_predict_p_d.bits.misp <= UInt<1>("h00") @[dec_decode_ctl.scala 223:57]
-    io.decode_exu.dec_i0_predict_p_d.bits.ataken <= UInt<1>("h00") @[dec_decode_ctl.scala 224:57]
-    io.decode_exu.dec_i0_predict_p_d.bits.boffset <= UInt<1>("h00") @[dec_decode_ctl.scala 225:57]
-    io.decode_exu.dec_i0_predict_p_d.bits.pcall <= i0_pcall @[dec_decode_ctl.scala 226:57]
-    io.decode_exu.dec_i0_predict_p_d.bits.pja <= i0_pja @[dec_decode_ctl.scala 227:57]
-    io.decode_exu.dec_i0_predict_p_d.bits.pret <= i0_pret @[dec_decode_ctl.scala 228:57]
-    io.decode_exu.dec_i0_predict_p_d.bits.prett <= io.dec_i0_brp.bits.prett @[dec_decode_ctl.scala 229:57]
-    io.decode_exu.dec_i0_predict_p_d.bits.pc4 <= io.dec_i0_pc4_d @[dec_decode_ctl.scala 230:57]
-    io.decode_exu.dec_i0_predict_p_d.bits.hist <= io.dec_i0_brp.bits.hist @[dec_decode_ctl.scala 231:57]
-    node _T_54 = and(i0_brp_valid, i0_legal_decode_d) @[dec_decode_ctl.scala 232:73]
-    io.decode_exu.dec_i0_predict_p_d.valid <= _T_54 @[dec_decode_ctl.scala 232:57]
-    node _T_55 = or(i0_dp_raw.condbr, i0_pcall_raw) @[dec_decode_ctl.scala 233:94]
-    node _T_56 = or(_T_55, i0_pja_raw) @[dec_decode_ctl.scala 233:109]
-    node _T_57 = or(_T_56, i0_pret_raw) @[dec_decode_ctl.scala 233:122]
-    node _T_58 = eq(_T_57, UInt<1>("h00")) @[dec_decode_ctl.scala 233:75]
-    node _T_59 = and(i0_brp_valid, _T_58) @[dec_decode_ctl.scala 233:73]
-    node _T_60 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[dec_decode_ctl.scala 236:99]
-    node _T_61 = and(i0_brp_valid, _T_60) @[dec_decode_ctl.scala 236:74]
-    node _T_62 = neq(io.dec_i0_brp.bits.toffset, i0_br_offset) @[dec_decode_ctl.scala 236:133]
-    node _T_63 = and(_T_61, _T_62) @[dec_decode_ctl.scala 236:103]
-    node _T_64 = eq(i0_pret_raw, UInt<1>("h00")) @[dec_decode_ctl.scala 236:153]
-    node _T_65 = and(_T_63, _T_64) @[dec_decode_ctl.scala 236:151]
-    node _T_66 = xor(io.dec_i0_brp.bits.ret, i0_pret_raw) @[dec_decode_ctl.scala 237:100]
-    node _T_67 = and(i0_brp_valid, _T_66) @[dec_decode_ctl.scala 237:74]
-    node _T_68 = or(io.dec_i0_brp.bits.br_error, _T_59) @[dec_decode_ctl.scala 238:89]
-    node _T_69 = or(_T_68, _T_65) @[dec_decode_ctl.scala 238:106]
-    node _T_70 = or(_T_69, _T_67) @[dec_decode_ctl.scala 238:128]
-    node _T_71 = and(_T_70, i0_legal_decode_d) @[dec_decode_ctl.scala 239:74]
-    node _T_72 = eq(leak1_mode, UInt<1>("h00")) @[dec_decode_ctl.scala 239:96]
-    node _T_73 = and(_T_71, _T_72) @[dec_decode_ctl.scala 239:94]
-    io.decode_exu.dec_i0_predict_p_d.bits.br_error <= _T_73 @[dec_decode_ctl.scala 239:58]
-    node _T_74 = and(io.dec_i0_brp.bits.br_start_error, i0_legal_decode_d) @[dec_decode_ctl.scala 240:96]
-    node _T_75 = eq(leak1_mode, UInt<1>("h00")) @[dec_decode_ctl.scala 240:118]
-    node _T_76 = and(_T_74, _T_75) @[dec_decode_ctl.scala 240:116]
-    io.decode_exu.dec_i0_predict_p_d.bits.br_start_error <= _T_76 @[dec_decode_ctl.scala 240:58]
-    io.decode_exu.i0_predict_index_d <= io.dec_i0_bp_index @[dec_decode_ctl.scala 241:58]
-    io.decode_exu.i0_predict_btag_d <= io.dec_i0_bp_btag @[dec_decode_ctl.scala 242:58]
-    node _T_77 = or(_T_70, io.dec_i0_brp.bits.br_start_error) @[dec_decode_ctl.scala 243:74]
-    node _T_78 = eq(leak1_mode, UInt<1>("h00")) @[dec_decode_ctl.scala 243:113]
-    node _T_79 = and(_T_77, _T_78) @[dec_decode_ctl.scala 243:111]
-    i0_br_error_all <= _T_79 @[dec_decode_ctl.scala 243:58]
-    io.decode_exu.dec_i0_predict_p_d.bits.toffset <= i0_br_offset @[dec_decode_ctl.scala 244:58]
-    io.decode_exu.i0_predict_fghr_d <= io.dec_i0_bp_fghr @[dec_decode_ctl.scala 245:58]
-    io.decode_exu.dec_i0_predict_p_d.bits.way <= io.dec_i0_brp.bits.way @[dec_decode_ctl.scala 246:58]
-    io.dec_fa_error_index <= UInt<1>("h00") @[dec_decode_ctl.scala 255:29]
-    i0_dp.legal <= i0_dp_raw.legal @[dec_decode_ctl.scala 279:23]
-    i0_dp.pm_alu <= i0_dp_raw.pm_alu @[dec_decode_ctl.scala 279:23]
-    i0_dp.fence_i <= i0_dp_raw.fence_i @[dec_decode_ctl.scala 279:23]
-    i0_dp.fence <= i0_dp_raw.fence @[dec_decode_ctl.scala 279:23]
-    i0_dp.rem <= i0_dp_raw.rem @[dec_decode_ctl.scala 279:23]
-    i0_dp.div <= i0_dp_raw.div @[dec_decode_ctl.scala 279:23]
-    i0_dp.low <= i0_dp_raw.low @[dec_decode_ctl.scala 279:23]
-    i0_dp.rs2_sign <= i0_dp_raw.rs2_sign @[dec_decode_ctl.scala 279:23]
-    i0_dp.rs1_sign <= i0_dp_raw.rs1_sign @[dec_decode_ctl.scala 279:23]
-    i0_dp.mul <= i0_dp_raw.mul @[dec_decode_ctl.scala 279:23]
-    i0_dp.mret <= i0_dp_raw.mret @[dec_decode_ctl.scala 279:23]
-    i0_dp.ecall <= i0_dp_raw.ecall @[dec_decode_ctl.scala 279:23]
-    i0_dp.ebreak <= i0_dp_raw.ebreak @[dec_decode_ctl.scala 279:23]
-    i0_dp.postsync <= i0_dp_raw.postsync @[dec_decode_ctl.scala 279:23]
-    i0_dp.presync <= i0_dp_raw.presync @[dec_decode_ctl.scala 279:23]
-    i0_dp.csr_imm <= i0_dp_raw.csr_imm @[dec_decode_ctl.scala 279:23]
-    i0_dp.csr_write <= i0_dp_raw.csr_write @[dec_decode_ctl.scala 279:23]
-    i0_dp.csr_set <= i0_dp_raw.csr_set @[dec_decode_ctl.scala 279:23]
-    i0_dp.csr_clr <= i0_dp_raw.csr_clr @[dec_decode_ctl.scala 279:23]
-    i0_dp.csr_read <= i0_dp_raw.csr_read @[dec_decode_ctl.scala 279:23]
-    i0_dp.word <= i0_dp_raw.word @[dec_decode_ctl.scala 279:23]
-    i0_dp.half <= i0_dp_raw.half @[dec_decode_ctl.scala 279:23]
-    i0_dp.by <= i0_dp_raw.by @[dec_decode_ctl.scala 279:23]
-    i0_dp.jal <= i0_dp_raw.jal @[dec_decode_ctl.scala 279:23]
-    i0_dp.blt <= i0_dp_raw.blt @[dec_decode_ctl.scala 279:23]
-    i0_dp.bge <= i0_dp_raw.bge @[dec_decode_ctl.scala 279:23]
-    i0_dp.bne <= i0_dp_raw.bne @[dec_decode_ctl.scala 279:23]
-    i0_dp.beq <= i0_dp_raw.beq @[dec_decode_ctl.scala 279:23]
-    i0_dp.condbr <= i0_dp_raw.condbr @[dec_decode_ctl.scala 279:23]
-    i0_dp.unsign <= i0_dp_raw.unsign @[dec_decode_ctl.scala 279:23]
-    i0_dp.slt <= i0_dp_raw.slt @[dec_decode_ctl.scala 279:23]
-    i0_dp.srl <= i0_dp_raw.srl @[dec_decode_ctl.scala 279:23]
-    i0_dp.sra <= i0_dp_raw.sra @[dec_decode_ctl.scala 279:23]
-    i0_dp.sll <= i0_dp_raw.sll @[dec_decode_ctl.scala 279:23]
-    i0_dp.lxor <= i0_dp_raw.lxor @[dec_decode_ctl.scala 279:23]
-    i0_dp.lor <= i0_dp_raw.lor @[dec_decode_ctl.scala 279:23]
-    i0_dp.land <= i0_dp_raw.land @[dec_decode_ctl.scala 279:23]
-    i0_dp.sub <= i0_dp_raw.sub @[dec_decode_ctl.scala 279:23]
-    i0_dp.add <= i0_dp_raw.add @[dec_decode_ctl.scala 279:23]
-    i0_dp.lsu <= i0_dp_raw.lsu @[dec_decode_ctl.scala 279:23]
-    i0_dp.store <= i0_dp_raw.store @[dec_decode_ctl.scala 279:23]
-    i0_dp.load <= i0_dp_raw.load @[dec_decode_ctl.scala 279:23]
-    i0_dp.pc <= i0_dp_raw.pc @[dec_decode_ctl.scala 279:23]
-    i0_dp.imm20 <= i0_dp_raw.imm20 @[dec_decode_ctl.scala 279:23]
-    i0_dp.shimm5 <= i0_dp_raw.shimm5 @[dec_decode_ctl.scala 279:23]
-    i0_dp.rd <= i0_dp_raw.rd @[dec_decode_ctl.scala 279:23]
-    i0_dp.imm12 <= i0_dp_raw.imm12 @[dec_decode_ctl.scala 279:23]
-    i0_dp.rs2 <= i0_dp_raw.rs2 @[dec_decode_ctl.scala 279:23]
-    i0_dp.rs1 <= i0_dp_raw.rs1 @[dec_decode_ctl.scala 279:23]
-    i0_dp.alu <= i0_dp_raw.alu @[dec_decode_ctl.scala 279:23]
-    i0_dp.zba <= i0_dp_raw.zba @[dec_decode_ctl.scala 279:23]
-    i0_dp.sh3add <= i0_dp_raw.sh3add @[dec_decode_ctl.scala 279:23]
-    i0_dp.sh2add <= i0_dp_raw.sh2add @[dec_decode_ctl.scala 279:23]
-    i0_dp.sh1add <= i0_dp_raw.sh1add @[dec_decode_ctl.scala 279:23]
-    i0_dp.zbf <= i0_dp_raw.zbf @[dec_decode_ctl.scala 279:23]
-    i0_dp.bfp <= i0_dp_raw.bfp @[dec_decode_ctl.scala 279:23]
-    i0_dp.zbr <= i0_dp_raw.zbr @[dec_decode_ctl.scala 279:23]
-    i0_dp.crc32c_w <= i0_dp_raw.crc32c_w @[dec_decode_ctl.scala 279:23]
-    i0_dp.crc32c_h <= i0_dp_raw.crc32c_h @[dec_decode_ctl.scala 279:23]
-    i0_dp.crc32c_b <= i0_dp_raw.crc32c_b @[dec_decode_ctl.scala 279:23]
-    i0_dp.crc32_w <= i0_dp_raw.crc32_w @[dec_decode_ctl.scala 279:23]
-    i0_dp.crc32_h <= i0_dp_raw.crc32_h @[dec_decode_ctl.scala 279:23]
-    i0_dp.crc32_b <= i0_dp_raw.crc32_b @[dec_decode_ctl.scala 279:23]
-    i0_dp.zbp <= i0_dp_raw.zbp @[dec_decode_ctl.scala 279:23]
-    i0_dp.unshfl <= i0_dp_raw.unshfl @[dec_decode_ctl.scala 279:23]
-    i0_dp.shfl <= i0_dp_raw.shfl @[dec_decode_ctl.scala 279:23]
-    i0_dp.zbc <= i0_dp_raw.zbc @[dec_decode_ctl.scala 279:23]
-    i0_dp.clmulr <= i0_dp_raw.clmulr @[dec_decode_ctl.scala 279:23]
-    i0_dp.clmulh <= i0_dp_raw.clmulh @[dec_decode_ctl.scala 279:23]
-    i0_dp.clmul <= i0_dp_raw.clmul @[dec_decode_ctl.scala 279:23]
-    i0_dp.zbe <= i0_dp_raw.zbe @[dec_decode_ctl.scala 279:23]
-    i0_dp.bdep <= i0_dp_raw.bdep @[dec_decode_ctl.scala 279:23]
-    i0_dp.bext <= i0_dp_raw.bext @[dec_decode_ctl.scala 279:23]
-    i0_dp.zbs <= i0_dp_raw.zbs @[dec_decode_ctl.scala 279:23]
-    i0_dp.sbext <= i0_dp_raw.sbext @[dec_decode_ctl.scala 279:23]
-    i0_dp.sbinv <= i0_dp_raw.sbinv @[dec_decode_ctl.scala 279:23]
-    i0_dp.sbclr <= i0_dp_raw.sbclr @[dec_decode_ctl.scala 279:23]
-    i0_dp.sbset <= i0_dp_raw.sbset @[dec_decode_ctl.scala 279:23]
-    i0_dp.zbb <= i0_dp_raw.zbb @[dec_decode_ctl.scala 279:23]
-    i0_dp.gorc <= i0_dp_raw.gorc @[dec_decode_ctl.scala 279:23]
-    i0_dp.grev <= i0_dp_raw.grev @[dec_decode_ctl.scala 279:23]
-    i0_dp.ror <= i0_dp_raw.ror @[dec_decode_ctl.scala 279:23]
-    i0_dp.rol <= i0_dp_raw.rol @[dec_decode_ctl.scala 279:23]
-    i0_dp.packh <= i0_dp_raw.packh @[dec_decode_ctl.scala 279:23]
-    i0_dp.packu <= i0_dp_raw.packu @[dec_decode_ctl.scala 279:23]
-    i0_dp.pack <= i0_dp_raw.pack @[dec_decode_ctl.scala 279:23]
-    i0_dp.max <= i0_dp_raw.max @[dec_decode_ctl.scala 279:23]
-    i0_dp.min <= i0_dp_raw.min @[dec_decode_ctl.scala 279:23]
-    i0_dp.sro <= i0_dp_raw.sro @[dec_decode_ctl.scala 279:23]
-    i0_dp.slo <= i0_dp_raw.slo @[dec_decode_ctl.scala 279:23]
-    i0_dp.sext_h <= i0_dp_raw.sext_h @[dec_decode_ctl.scala 279:23]
-    i0_dp.sext_b <= i0_dp_raw.sext_b @[dec_decode_ctl.scala 279:23]
-    i0_dp.pcnt <= i0_dp_raw.pcnt @[dec_decode_ctl.scala 279:23]
-    i0_dp.ctz <= i0_dp_raw.ctz @[dec_decode_ctl.scala 279:23]
-    i0_dp.clz <= i0_dp_raw.clz @[dec_decode_ctl.scala 279:23]
-    node _T_80 = or(i0_br_error_all, i0_icaf_d) @[dec_decode_ctl.scala 280:25]
-    node _T_81 = bits(_T_80, 0, 0) @[dec_decode_ctl.scala 280:43]
-    when _T_81 : @[dec_decode_ctl.scala 280:50]
-      wire _T_82 : {clz : UInt<1>, ctz : UInt<1>, pcnt : UInt<1>, sext_b : UInt<1>, sext_h : UInt<1>, slo : UInt<1>, sro : UInt<1>, min : UInt<1>, max : UInt<1>, pack : UInt<1>, packu : UInt<1>, packh : UInt<1>, rol : UInt<1>, ror : UInt<1>, grev : UInt<1>, gorc : UInt<1>, zbb : UInt<1>, sbset : UInt<1>, sbclr : UInt<1>, sbinv : UInt<1>, sbext : UInt<1>, zbs : UInt<1>, bext : UInt<1>, bdep : UInt<1>, zbe : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, zbc : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, zbp : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, zbr : UInt<1>, bfp : UInt<1>, zbf : UInt<1>, sh1add : UInt<1>, sh2add : UInt<1>, sh3add : UInt<1>, zba : UInt<1>, alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[dec_decode_ctl.scala 281:38]
-      _T_82.legal <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.pm_alu <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.fence_i <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.fence <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.rem <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.div <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.low <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.rs2_sign <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.rs1_sign <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.mret <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.ecall <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.ebreak <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.postsync <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.presync <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.csr_imm <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.csr_write <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.csr_set <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.csr_clr <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.csr_read <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.word <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.half <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.by <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.jal <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.blt <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.bge <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.bne <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.beq <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.condbr <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.unsign <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.slt <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.srl <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.sra <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.sll <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.lxor <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.lor <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.land <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.sub <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.add <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.lsu <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.store <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.load <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.pc <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.imm20 <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.shimm5 <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.rd <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.imm12 <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.rs2 <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.rs1 <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.zba <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.sh3add <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.sh2add <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.sh1add <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.zbf <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.bfp <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.zbr <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.crc32c_w <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.crc32c_h <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.crc32c_b <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.crc32_w <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.crc32_h <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.crc32_b <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.zbp <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.unshfl <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.shfl <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.zbc <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.clmulr <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.clmulh <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.clmul <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.zbe <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.bdep <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.bext <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.zbs <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.sbext <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.sbinv <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.sbclr <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.sbset <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.zbb <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.gorc <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.grev <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.ror <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.rol <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.packh <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.packu <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.pack <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.max <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.min <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.sro <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.slo <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.sext_h <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.sext_b <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.pcnt <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.ctz <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      _T_82.clz <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38]
-      i0_dp.legal <= _T_82.legal @[dec_decode_ctl.scala 281:23]
-      i0_dp.pm_alu <= _T_82.pm_alu @[dec_decode_ctl.scala 281:23]
-      i0_dp.fence_i <= _T_82.fence_i @[dec_decode_ctl.scala 281:23]
-      i0_dp.fence <= _T_82.fence @[dec_decode_ctl.scala 281:23]
-      i0_dp.rem <= _T_82.rem @[dec_decode_ctl.scala 281:23]
-      i0_dp.div <= _T_82.div @[dec_decode_ctl.scala 281:23]
-      i0_dp.low <= _T_82.low @[dec_decode_ctl.scala 281:23]
-      i0_dp.rs2_sign <= _T_82.rs2_sign @[dec_decode_ctl.scala 281:23]
-      i0_dp.rs1_sign <= _T_82.rs1_sign @[dec_decode_ctl.scala 281:23]
-      i0_dp.mul <= _T_82.mul @[dec_decode_ctl.scala 281:23]
-      i0_dp.mret <= _T_82.mret @[dec_decode_ctl.scala 281:23]
-      i0_dp.ecall <= _T_82.ecall @[dec_decode_ctl.scala 281:23]
-      i0_dp.ebreak <= _T_82.ebreak @[dec_decode_ctl.scala 281:23]
-      i0_dp.postsync <= _T_82.postsync @[dec_decode_ctl.scala 281:23]
-      i0_dp.presync <= _T_82.presync @[dec_decode_ctl.scala 281:23]
-      i0_dp.csr_imm <= _T_82.csr_imm @[dec_decode_ctl.scala 281:23]
-      i0_dp.csr_write <= _T_82.csr_write @[dec_decode_ctl.scala 281:23]
-      i0_dp.csr_set <= _T_82.csr_set @[dec_decode_ctl.scala 281:23]
-      i0_dp.csr_clr <= _T_82.csr_clr @[dec_decode_ctl.scala 281:23]
-      i0_dp.csr_read <= _T_82.csr_read @[dec_decode_ctl.scala 281:23]
-      i0_dp.word <= _T_82.word @[dec_decode_ctl.scala 281:23]
-      i0_dp.half <= _T_82.half @[dec_decode_ctl.scala 281:23]
-      i0_dp.by <= _T_82.by @[dec_decode_ctl.scala 281:23]
-      i0_dp.jal <= _T_82.jal @[dec_decode_ctl.scala 281:23]
-      i0_dp.blt <= _T_82.blt @[dec_decode_ctl.scala 281:23]
-      i0_dp.bge <= _T_82.bge @[dec_decode_ctl.scala 281:23]
-      i0_dp.bne <= _T_82.bne @[dec_decode_ctl.scala 281:23]
-      i0_dp.beq <= _T_82.beq @[dec_decode_ctl.scala 281:23]
-      i0_dp.condbr <= _T_82.condbr @[dec_decode_ctl.scala 281:23]
-      i0_dp.unsign <= _T_82.unsign @[dec_decode_ctl.scala 281:23]
-      i0_dp.slt <= _T_82.slt @[dec_decode_ctl.scala 281:23]
-      i0_dp.srl <= _T_82.srl @[dec_decode_ctl.scala 281:23]
-      i0_dp.sra <= _T_82.sra @[dec_decode_ctl.scala 281:23]
-      i0_dp.sll <= _T_82.sll @[dec_decode_ctl.scala 281:23]
-      i0_dp.lxor <= _T_82.lxor @[dec_decode_ctl.scala 281:23]
-      i0_dp.lor <= _T_82.lor @[dec_decode_ctl.scala 281:23]
-      i0_dp.land <= _T_82.land @[dec_decode_ctl.scala 281:23]
-      i0_dp.sub <= _T_82.sub @[dec_decode_ctl.scala 281:23]
-      i0_dp.add <= _T_82.add @[dec_decode_ctl.scala 281:23]
-      i0_dp.lsu <= _T_82.lsu @[dec_decode_ctl.scala 281:23]
-      i0_dp.store <= _T_82.store @[dec_decode_ctl.scala 281:23]
-      i0_dp.load <= _T_82.load @[dec_decode_ctl.scala 281:23]
-      i0_dp.pc <= _T_82.pc @[dec_decode_ctl.scala 281:23]
-      i0_dp.imm20 <= _T_82.imm20 @[dec_decode_ctl.scala 281:23]
-      i0_dp.shimm5 <= _T_82.shimm5 @[dec_decode_ctl.scala 281:23]
-      i0_dp.rd <= _T_82.rd @[dec_decode_ctl.scala 281:23]
-      i0_dp.imm12 <= _T_82.imm12 @[dec_decode_ctl.scala 281:23]
-      i0_dp.rs2 <= _T_82.rs2 @[dec_decode_ctl.scala 281:23]
-      i0_dp.rs1 <= _T_82.rs1 @[dec_decode_ctl.scala 281:23]
-      i0_dp.alu <= _T_82.alu @[dec_decode_ctl.scala 281:23]
-      i0_dp.zba <= _T_82.zba @[dec_decode_ctl.scala 281:23]
-      i0_dp.sh3add <= _T_82.sh3add @[dec_decode_ctl.scala 281:23]
-      i0_dp.sh2add <= _T_82.sh2add @[dec_decode_ctl.scala 281:23]
-      i0_dp.sh1add <= _T_82.sh1add @[dec_decode_ctl.scala 281:23]
-      i0_dp.zbf <= _T_82.zbf @[dec_decode_ctl.scala 281:23]
-      i0_dp.bfp <= _T_82.bfp @[dec_decode_ctl.scala 281:23]
-      i0_dp.zbr <= _T_82.zbr @[dec_decode_ctl.scala 281:23]
-      i0_dp.crc32c_w <= _T_82.crc32c_w @[dec_decode_ctl.scala 281:23]
-      i0_dp.crc32c_h <= _T_82.crc32c_h @[dec_decode_ctl.scala 281:23]
-      i0_dp.crc32c_b <= _T_82.crc32c_b @[dec_decode_ctl.scala 281:23]
-      i0_dp.crc32_w <= _T_82.crc32_w @[dec_decode_ctl.scala 281:23]
-      i0_dp.crc32_h <= _T_82.crc32_h @[dec_decode_ctl.scala 281:23]
-      i0_dp.crc32_b <= _T_82.crc32_b @[dec_decode_ctl.scala 281:23]
-      i0_dp.zbp <= _T_82.zbp @[dec_decode_ctl.scala 281:23]
-      i0_dp.unshfl <= _T_82.unshfl @[dec_decode_ctl.scala 281:23]
-      i0_dp.shfl <= _T_82.shfl @[dec_decode_ctl.scala 281:23]
-      i0_dp.zbc <= _T_82.zbc @[dec_decode_ctl.scala 281:23]
-      i0_dp.clmulr <= _T_82.clmulr @[dec_decode_ctl.scala 281:23]
-      i0_dp.clmulh <= _T_82.clmulh @[dec_decode_ctl.scala 281:23]
-      i0_dp.clmul <= _T_82.clmul @[dec_decode_ctl.scala 281:23]
-      i0_dp.zbe <= _T_82.zbe @[dec_decode_ctl.scala 281:23]
-      i0_dp.bdep <= _T_82.bdep @[dec_decode_ctl.scala 281:23]
-      i0_dp.bext <= _T_82.bext @[dec_decode_ctl.scala 281:23]
-      i0_dp.zbs <= _T_82.zbs @[dec_decode_ctl.scala 281:23]
-      i0_dp.sbext <= _T_82.sbext @[dec_decode_ctl.scala 281:23]
-      i0_dp.sbinv <= _T_82.sbinv @[dec_decode_ctl.scala 281:23]
-      i0_dp.sbclr <= _T_82.sbclr @[dec_decode_ctl.scala 281:23]
-      i0_dp.sbset <= _T_82.sbset @[dec_decode_ctl.scala 281:23]
-      i0_dp.zbb <= _T_82.zbb @[dec_decode_ctl.scala 281:23]
-      i0_dp.gorc <= _T_82.gorc @[dec_decode_ctl.scala 281:23]
-      i0_dp.grev <= _T_82.grev @[dec_decode_ctl.scala 281:23]
-      i0_dp.ror <= _T_82.ror @[dec_decode_ctl.scala 281:23]
-      i0_dp.rol <= _T_82.rol @[dec_decode_ctl.scala 281:23]
-      i0_dp.packh <= _T_82.packh @[dec_decode_ctl.scala 281:23]
-      i0_dp.packu <= _T_82.packu @[dec_decode_ctl.scala 281:23]
-      i0_dp.pack <= _T_82.pack @[dec_decode_ctl.scala 281:23]
-      i0_dp.max <= _T_82.max @[dec_decode_ctl.scala 281:23]
-      i0_dp.min <= _T_82.min @[dec_decode_ctl.scala 281:23]
-      i0_dp.sro <= _T_82.sro @[dec_decode_ctl.scala 281:23]
-      i0_dp.slo <= _T_82.slo @[dec_decode_ctl.scala 281:23]
-      i0_dp.sext_h <= _T_82.sext_h @[dec_decode_ctl.scala 281:23]
-      i0_dp.sext_b <= _T_82.sext_b @[dec_decode_ctl.scala 281:23]
-      i0_dp.pcnt <= _T_82.pcnt @[dec_decode_ctl.scala 281:23]
-      i0_dp.ctz <= _T_82.ctz @[dec_decode_ctl.scala 281:23]
-      i0_dp.clz <= _T_82.clz @[dec_decode_ctl.scala 281:23]
-      i0_dp.alu <= UInt<1>("h01") @[dec_decode_ctl.scala 282:23]
-      i0_dp.rs1 <= UInt<1>("h01") @[dec_decode_ctl.scala 283:23]
-      i0_dp.rs2 <= UInt<1>("h01") @[dec_decode_ctl.scala 284:23]
-      i0_dp.lor <= UInt<1>("h01") @[dec_decode_ctl.scala 285:23]
-      i0_dp.legal <= UInt<1>("h01") @[dec_decode_ctl.scala 286:23]
-      i0_dp.postsync <= UInt<1>("h01") @[dec_decode_ctl.scala 287:23]
-      skip @[dec_decode_ctl.scala 280:50]
-    io.decode_exu.dec_i0_select_pc_d <= i0_dp.pc @[dec_decode_ctl.scala 291:36]
-    node _T_83 = or(i0_dp.condbr, i0_pcall) @[dec_decode_ctl.scala 294:54]
-    node _T_84 = or(_T_83, i0_pja) @[dec_decode_ctl.scala 294:65]
-    node i0_predict_br = or(_T_84, i0_pret) @[dec_decode_ctl.scala 294:74]
-    node _T_85 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[dec_decode_ctl.scala 295:65]
-    node _T_86 = and(_T_85, i0_brp_valid) @[dec_decode_ctl.scala 295:69]
-    node _T_87 = eq(_T_86, UInt<1>("h00")) @[dec_decode_ctl.scala 295:40]
-    node i0_predict_nt = and(_T_87, i0_predict_br) @[dec_decode_ctl.scala 295:85]
-    node _T_88 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[dec_decode_ctl.scala 296:65]
-    node _T_89 = and(_T_88, i0_brp_valid) @[dec_decode_ctl.scala 296:69]
-    node i0_predict_t = and(_T_89, i0_predict_br) @[dec_decode_ctl.scala 296:85]
-    node i0_ap_pc2 = eq(io.dec_i0_pc4_d, UInt<1>("h00")) @[dec_decode_ctl.scala 297:40]
-    io.decode_exu.i0_ap.predict_nt <= i0_predict_nt @[dec_decode_ctl.scala 299:37]
-    io.decode_exu.i0_ap.predict_t <= i0_predict_t @[dec_decode_ctl.scala 300:37]
-    io.decode_exu.i0_ap.add <= i0_dp.add @[dec_decode_ctl.scala 303:33]
-    io.decode_exu.i0_ap.sub <= i0_dp.sub @[dec_decode_ctl.scala 304:33]
-    io.decode_exu.i0_ap.land <= i0_dp.land @[dec_decode_ctl.scala 305:33]
-    io.decode_exu.i0_ap.lor <= i0_dp.lor @[dec_decode_ctl.scala 306:33]
-    io.decode_exu.i0_ap.lxor <= i0_dp.lxor @[dec_decode_ctl.scala 307:33]
-    io.decode_exu.i0_ap.sll <= i0_dp.sll @[dec_decode_ctl.scala 308:33]
-    io.decode_exu.i0_ap.srl <= i0_dp.srl @[dec_decode_ctl.scala 309:33]
-    io.decode_exu.i0_ap.sra <= i0_dp.sra @[dec_decode_ctl.scala 310:33]
-    io.decode_exu.i0_ap.slt <= i0_dp.slt @[dec_decode_ctl.scala 311:33]
-    io.decode_exu.i0_ap.unsign <= i0_dp.unsign @[dec_decode_ctl.scala 312:33]
-    io.decode_exu.i0_ap.beq <= i0_dp.beq @[dec_decode_ctl.scala 313:33]
-    io.decode_exu.i0_ap.bne <= i0_dp.bne @[dec_decode_ctl.scala 314:33]
-    io.decode_exu.i0_ap.blt <= i0_dp.blt @[dec_decode_ctl.scala 315:33]
-    io.decode_exu.i0_ap.bge <= i0_dp.bge @[dec_decode_ctl.scala 316:33]
-    io.decode_exu.i0_ap.clz <= i0_dp.clz @[dec_decode_ctl.scala 317:33]
-    io.decode_exu.i0_ap.ctz <= i0_dp.ctz @[dec_decode_ctl.scala 318:33]
-    io.decode_exu.i0_ap.pcnt <= i0_dp.pcnt @[dec_decode_ctl.scala 319:33]
-    io.decode_exu.i0_ap.sext_b <= i0_dp.sext_b @[dec_decode_ctl.scala 320:33]
-    io.decode_exu.i0_ap.sext_h <= i0_dp.sext_h @[dec_decode_ctl.scala 321:33]
-    io.decode_exu.i0_ap.sh1add <= i0_dp.sh1add @[dec_decode_ctl.scala 322:33]
-    io.decode_exu.i0_ap.sh2add <= i0_dp.sh2add @[dec_decode_ctl.scala 323:33]
-    io.decode_exu.i0_ap.sh3add <= i0_dp.sh3add @[dec_decode_ctl.scala 324:33]
-    io.decode_exu.i0_ap.zba <= i0_dp.zba @[dec_decode_ctl.scala 325:33]
-    io.decode_exu.i0_ap.slo <= i0_dp.slo @[dec_decode_ctl.scala 326:33]
-    io.decode_exu.i0_ap.sro <= i0_dp.sro @[dec_decode_ctl.scala 327:33]
-    io.decode_exu.i0_ap.min <= i0_dp.min @[dec_decode_ctl.scala 328:33]
-    io.decode_exu.i0_ap.max <= i0_dp.max @[dec_decode_ctl.scala 329:33]
-    io.decode_exu.i0_ap.pack <= i0_dp.pack @[dec_decode_ctl.scala 330:33]
-    io.decode_exu.i0_ap.packu <= i0_dp.packu @[dec_decode_ctl.scala 331:33]
-    io.decode_exu.i0_ap.packh <= i0_dp.packh @[dec_decode_ctl.scala 332:33]
-    io.decode_exu.i0_ap.rol <= i0_dp.rol @[dec_decode_ctl.scala 333:33]
-    io.decode_exu.i0_ap.ror <= i0_dp.ror @[dec_decode_ctl.scala 334:33]
-    io.decode_exu.i0_ap.grev <= i0_dp.grev @[dec_decode_ctl.scala 335:33]
-    io.decode_exu.i0_ap.gorc <= i0_dp.gorc @[dec_decode_ctl.scala 336:33]
-    io.decode_exu.i0_ap.zbb <= i0_dp.zbb @[dec_decode_ctl.scala 337:33]
-    io.decode_exu.i0_ap.sbset <= i0_dp.sbset @[dec_decode_ctl.scala 338:33]
-    io.decode_exu.i0_ap.sbclr <= i0_dp.sbclr @[dec_decode_ctl.scala 339:33]
-    io.decode_exu.i0_ap.sbinv <= i0_dp.sbinv @[dec_decode_ctl.scala 340:33]
-    io.decode_exu.i0_ap.sbext <= i0_dp.sbext @[dec_decode_ctl.scala 341:33]
-    io.decode_exu.i0_ap.csr_write <= i0_csr_write_only_d @[dec_decode_ctl.scala 342:33]
-    io.decode_exu.i0_ap.csr_imm <= i0_dp.csr_imm @[dec_decode_ctl.scala 343:33]
-    io.decode_exu.i0_ap.jal <= i0_jal @[dec_decode_ctl.scala 344:33]
-    node _T_90 = eq(cam[0].valid, UInt<1>("h00")) @[dec_decode_ctl.scala 348:78]
-    node _T_91 = bits(_T_90, 0, 0) @[dec_decode_ctl.scala 348:137]
-    node _T_92 = shl(cam_write, 0) @[dec_decode_ctl.scala 348:158]
-    node _T_93 = eq(cam[1].valid, UInt<1>("h00")) @[dec_decode_ctl.scala 348:78]
-    node _T_94 = bits(cam[0].valid, 0, 0) @[dec_decode_ctl.scala 348:120]
-    node _T_95 = bits(_T_93, 0, 0) @[dec_decode_ctl.scala 348:129]
-    node _T_96 = and(_T_94, _T_95) @[dec_decode_ctl.scala 348:126]
-    node _T_97 = bits(_T_96, 0, 0) @[dec_decode_ctl.scala 348:137]
-    node _T_98 = shl(cam_write, 1) @[dec_decode_ctl.scala 348:158]
-    node _T_99 = eq(cam[2].valid, UInt<1>("h00")) @[dec_decode_ctl.scala 348:78]
-    node _T_100 = bits(cam[0].valid, 0, 0) @[dec_decode_ctl.scala 348:120]
-    node _T_101 = bits(cam[1].valid, 0, 0) @[dec_decode_ctl.scala 348:129]
-    node _T_102 = and(_T_100, _T_101) @[dec_decode_ctl.scala 348:126]
-    node _T_103 = bits(_T_102, 0, 0) @[dec_decode_ctl.scala 348:120]
-    node _T_104 = bits(_T_99, 0, 0) @[dec_decode_ctl.scala 348:129]
-    node _T_105 = and(_T_103, _T_104) @[dec_decode_ctl.scala 348:126]
-    node _T_106 = bits(_T_105, 0, 0) @[dec_decode_ctl.scala 348:137]
-    node _T_107 = shl(cam_write, 2) @[dec_decode_ctl.scala 348:158]
-    node _T_108 = eq(cam[3].valid, UInt<1>("h00")) @[dec_decode_ctl.scala 348:78]
-    node _T_109 = bits(cam[0].valid, 0, 0) @[dec_decode_ctl.scala 348:120]
-    node _T_110 = bits(cam[1].valid, 0, 0) @[dec_decode_ctl.scala 348:129]
-    node _T_111 = and(_T_109, _T_110) @[dec_decode_ctl.scala 348:126]
-    node _T_112 = bits(_T_111, 0, 0) @[dec_decode_ctl.scala 348:120]
-    node _T_113 = bits(cam[2].valid, 0, 0) @[dec_decode_ctl.scala 348:129]
-    node _T_114 = and(_T_112, _T_113) @[dec_decode_ctl.scala 348:126]
-    node _T_115 = bits(_T_114, 0, 0) @[dec_decode_ctl.scala 348:120]
-    node _T_116 = bits(_T_108, 0, 0) @[dec_decode_ctl.scala 348:129]
-    node _T_117 = and(_T_115, _T_116) @[dec_decode_ctl.scala 348:126]
-    node _T_118 = bits(_T_117, 0, 0) @[dec_decode_ctl.scala 348:137]
-    node _T_119 = shl(cam_write, 3) @[dec_decode_ctl.scala 348:158]
+    node i0_icaf_d = or(io.dec_i0_icaf_d, io.dec_i0_dbecc_d) @[dec_decode_ctl.scala 222:43]
+    node _T_50 = eq(leak1_mode, UInt<1>("h00")) @[dec_decode_ctl.scala 224:82]
+    node _T_51 = and(io.dec_i0_brp.valid, _T_50) @[dec_decode_ctl.scala 224:80]
+    node _T_52 = eq(i0_icaf_d, UInt<1>("h00")) @[dec_decode_ctl.scala 224:96]
+    node _T_53 = and(_T_51, _T_52) @[dec_decode_ctl.scala 224:94]
+    i0_brp_valid <= _T_53 @[dec_decode_ctl.scala 224:57]
+    io.decode_exu.dec_i0_predict_p_d.bits.misp <= UInt<1>("h00") @[dec_decode_ctl.scala 225:57]
+    io.decode_exu.dec_i0_predict_p_d.bits.ataken <= UInt<1>("h00") @[dec_decode_ctl.scala 226:57]
+    io.decode_exu.dec_i0_predict_p_d.bits.boffset <= UInt<1>("h00") @[dec_decode_ctl.scala 227:57]
+    io.decode_exu.dec_i0_predict_p_d.bits.pcall <= i0_pcall @[dec_decode_ctl.scala 228:57]
+    io.decode_exu.dec_i0_predict_p_d.bits.pja <= i0_pja @[dec_decode_ctl.scala 229:57]
+    io.decode_exu.dec_i0_predict_p_d.bits.pret <= i0_pret @[dec_decode_ctl.scala 230:57]
+    io.decode_exu.dec_i0_predict_p_d.bits.prett <= io.dec_i0_brp.bits.prett @[dec_decode_ctl.scala 231:57]
+    io.decode_exu.dec_i0_predict_p_d.bits.pc4 <= io.dec_i0_pc4_d @[dec_decode_ctl.scala 232:57]
+    io.decode_exu.dec_i0_predict_p_d.bits.hist <= io.dec_i0_brp.bits.hist @[dec_decode_ctl.scala 233:57]
+    node _T_54 = and(i0_brp_valid, i0_legal_decode_d) @[dec_decode_ctl.scala 234:73]
+    io.decode_exu.dec_i0_predict_p_d.valid <= _T_54 @[dec_decode_ctl.scala 234:57]
+    node _T_55 = or(i0_dp_raw.condbr, i0_pcall_raw) @[dec_decode_ctl.scala 235:94]
+    node _T_56 = or(_T_55, i0_pja_raw) @[dec_decode_ctl.scala 235:109]
+    node _T_57 = or(_T_56, i0_pret_raw) @[dec_decode_ctl.scala 235:122]
+    node _T_58 = eq(_T_57, UInt<1>("h00")) @[dec_decode_ctl.scala 235:75]
+    node _T_59 = and(i0_brp_valid, _T_58) @[dec_decode_ctl.scala 235:73]
+    node _T_60 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[dec_decode_ctl.scala 238:99]
+    node _T_61 = and(i0_brp_valid, _T_60) @[dec_decode_ctl.scala 238:74]
+    node _T_62 = neq(io.dec_i0_brp.bits.toffset, i0_br_offset) @[dec_decode_ctl.scala 238:133]
+    node _T_63 = and(_T_61, _T_62) @[dec_decode_ctl.scala 238:103]
+    node _T_64 = eq(i0_pret_raw, UInt<1>("h00")) @[dec_decode_ctl.scala 238:153]
+    node _T_65 = and(_T_63, _T_64) @[dec_decode_ctl.scala 238:151]
+    node _T_66 = xor(io.dec_i0_brp.bits.ret, i0_pret_raw) @[dec_decode_ctl.scala 239:100]
+    node _T_67 = and(i0_brp_valid, _T_66) @[dec_decode_ctl.scala 239:74]
+    node _T_68 = or(io.dec_i0_brp.bits.br_error, _T_59) @[dec_decode_ctl.scala 240:89]
+    node _T_69 = or(_T_68, _T_65) @[dec_decode_ctl.scala 240:106]
+    node _T_70 = or(_T_69, _T_67) @[dec_decode_ctl.scala 240:128]
+    node _T_71 = and(_T_70, i0_legal_decode_d) @[dec_decode_ctl.scala 241:74]
+    node _T_72 = eq(leak1_mode, UInt<1>("h00")) @[dec_decode_ctl.scala 241:96]
+    node _T_73 = and(_T_71, _T_72) @[dec_decode_ctl.scala 241:94]
+    io.decode_exu.dec_i0_predict_p_d.bits.br_error <= _T_73 @[dec_decode_ctl.scala 241:58]
+    node _T_74 = and(io.dec_i0_brp.bits.br_start_error, i0_legal_decode_d) @[dec_decode_ctl.scala 242:96]
+    node _T_75 = eq(leak1_mode, UInt<1>("h00")) @[dec_decode_ctl.scala 242:118]
+    node _T_76 = and(_T_74, _T_75) @[dec_decode_ctl.scala 242:116]
+    io.decode_exu.dec_i0_predict_p_d.bits.br_start_error <= _T_76 @[dec_decode_ctl.scala 242:58]
+    io.decode_exu.i0_predict_index_d <= io.dec_i0_bp_index @[dec_decode_ctl.scala 243:58]
+    io.decode_exu.i0_predict_btag_d <= io.dec_i0_bp_btag @[dec_decode_ctl.scala 244:58]
+    node _T_77 = or(_T_70, io.dec_i0_brp.bits.br_start_error) @[dec_decode_ctl.scala 245:74]
+    node _T_78 = eq(leak1_mode, UInt<1>("h00")) @[dec_decode_ctl.scala 245:113]
+    node _T_79 = and(_T_77, _T_78) @[dec_decode_ctl.scala 245:111]
+    i0_br_error_all <= _T_79 @[dec_decode_ctl.scala 245:58]
+    io.decode_exu.dec_i0_predict_p_d.bits.toffset <= i0_br_offset @[dec_decode_ctl.scala 246:58]
+    io.decode_exu.i0_predict_fghr_d <= io.dec_i0_bp_fghr @[dec_decode_ctl.scala 247:58]
+    io.decode_exu.dec_i0_predict_p_d.bits.way <= io.dec_i0_brp.bits.way @[dec_decode_ctl.scala 248:58]
+    io.dec_fa_error_index <= UInt<1>("h00") @[dec_decode_ctl.scala 257:29]
+    i0_dp.legal <= i0_dp_raw.legal @[dec_decode_ctl.scala 281:23]
+    i0_dp.pm_alu <= i0_dp_raw.pm_alu @[dec_decode_ctl.scala 281:23]
+    i0_dp.fence_i <= i0_dp_raw.fence_i @[dec_decode_ctl.scala 281:23]
+    i0_dp.fence <= i0_dp_raw.fence @[dec_decode_ctl.scala 281:23]
+    i0_dp.rem <= i0_dp_raw.rem @[dec_decode_ctl.scala 281:23]
+    i0_dp.div <= i0_dp_raw.div @[dec_decode_ctl.scala 281:23]
+    i0_dp.low <= i0_dp_raw.low @[dec_decode_ctl.scala 281:23]
+    i0_dp.rs2_sign <= i0_dp_raw.rs2_sign @[dec_decode_ctl.scala 281:23]
+    i0_dp.rs1_sign <= i0_dp_raw.rs1_sign @[dec_decode_ctl.scala 281:23]
+    i0_dp.mul <= i0_dp_raw.mul @[dec_decode_ctl.scala 281:23]
+    i0_dp.mret <= i0_dp_raw.mret @[dec_decode_ctl.scala 281:23]
+    i0_dp.ecall <= i0_dp_raw.ecall @[dec_decode_ctl.scala 281:23]
+    i0_dp.ebreak <= i0_dp_raw.ebreak @[dec_decode_ctl.scala 281:23]
+    i0_dp.postsync <= i0_dp_raw.postsync @[dec_decode_ctl.scala 281:23]
+    i0_dp.presync <= i0_dp_raw.presync @[dec_decode_ctl.scala 281:23]
+    i0_dp.csr_imm <= i0_dp_raw.csr_imm @[dec_decode_ctl.scala 281:23]
+    i0_dp.csr_write <= i0_dp_raw.csr_write @[dec_decode_ctl.scala 281:23]
+    i0_dp.csr_set <= i0_dp_raw.csr_set @[dec_decode_ctl.scala 281:23]
+    i0_dp.csr_clr <= i0_dp_raw.csr_clr @[dec_decode_ctl.scala 281:23]
+    i0_dp.csr_read <= i0_dp_raw.csr_read @[dec_decode_ctl.scala 281:23]
+    i0_dp.word <= i0_dp_raw.word @[dec_decode_ctl.scala 281:23]
+    i0_dp.half <= i0_dp_raw.half @[dec_decode_ctl.scala 281:23]
+    i0_dp.by <= i0_dp_raw.by @[dec_decode_ctl.scala 281:23]
+    i0_dp.jal <= i0_dp_raw.jal @[dec_decode_ctl.scala 281:23]
+    i0_dp.blt <= i0_dp_raw.blt @[dec_decode_ctl.scala 281:23]
+    i0_dp.bge <= i0_dp_raw.bge @[dec_decode_ctl.scala 281:23]
+    i0_dp.bne <= i0_dp_raw.bne @[dec_decode_ctl.scala 281:23]
+    i0_dp.beq <= i0_dp_raw.beq @[dec_decode_ctl.scala 281:23]
+    i0_dp.condbr <= i0_dp_raw.condbr @[dec_decode_ctl.scala 281:23]
+    i0_dp.unsign <= i0_dp_raw.unsign @[dec_decode_ctl.scala 281:23]
+    i0_dp.slt <= i0_dp_raw.slt @[dec_decode_ctl.scala 281:23]
+    i0_dp.srl <= i0_dp_raw.srl @[dec_decode_ctl.scala 281:23]
+    i0_dp.sra <= i0_dp_raw.sra @[dec_decode_ctl.scala 281:23]
+    i0_dp.sll <= i0_dp_raw.sll @[dec_decode_ctl.scala 281:23]
+    i0_dp.lxor <= i0_dp_raw.lxor @[dec_decode_ctl.scala 281:23]
+    i0_dp.lor <= i0_dp_raw.lor @[dec_decode_ctl.scala 281:23]
+    i0_dp.land <= i0_dp_raw.land @[dec_decode_ctl.scala 281:23]
+    i0_dp.sub <= i0_dp_raw.sub @[dec_decode_ctl.scala 281:23]
+    i0_dp.add <= i0_dp_raw.add @[dec_decode_ctl.scala 281:23]
+    i0_dp.lsu <= i0_dp_raw.lsu @[dec_decode_ctl.scala 281:23]
+    i0_dp.store <= i0_dp_raw.store @[dec_decode_ctl.scala 281:23]
+    i0_dp.load <= i0_dp_raw.load @[dec_decode_ctl.scala 281:23]
+    i0_dp.pc <= i0_dp_raw.pc @[dec_decode_ctl.scala 281:23]
+    i0_dp.imm20 <= i0_dp_raw.imm20 @[dec_decode_ctl.scala 281:23]
+    i0_dp.shimm5 <= i0_dp_raw.shimm5 @[dec_decode_ctl.scala 281:23]
+    i0_dp.rd <= i0_dp_raw.rd @[dec_decode_ctl.scala 281:23]
+    i0_dp.imm12 <= i0_dp_raw.imm12 @[dec_decode_ctl.scala 281:23]
+    i0_dp.rs2 <= i0_dp_raw.rs2 @[dec_decode_ctl.scala 281:23]
+    i0_dp.rs1 <= i0_dp_raw.rs1 @[dec_decode_ctl.scala 281:23]
+    i0_dp.alu <= i0_dp_raw.alu @[dec_decode_ctl.scala 281:23]
+    i0_dp.zba <= i0_dp_raw.zba @[dec_decode_ctl.scala 281:23]
+    i0_dp.sh3add <= i0_dp_raw.sh3add @[dec_decode_ctl.scala 281:23]
+    i0_dp.sh2add <= i0_dp_raw.sh2add @[dec_decode_ctl.scala 281:23]
+    i0_dp.sh1add <= i0_dp_raw.sh1add @[dec_decode_ctl.scala 281:23]
+    i0_dp.zbf <= i0_dp_raw.zbf @[dec_decode_ctl.scala 281:23]
+    i0_dp.bfp <= i0_dp_raw.bfp @[dec_decode_ctl.scala 281:23]
+    i0_dp.zbr <= i0_dp_raw.zbr @[dec_decode_ctl.scala 281:23]
+    i0_dp.crc32c_w <= i0_dp_raw.crc32c_w @[dec_decode_ctl.scala 281:23]
+    i0_dp.crc32c_h <= i0_dp_raw.crc32c_h @[dec_decode_ctl.scala 281:23]
+    i0_dp.crc32c_b <= i0_dp_raw.crc32c_b @[dec_decode_ctl.scala 281:23]
+    i0_dp.crc32_w <= i0_dp_raw.crc32_w @[dec_decode_ctl.scala 281:23]
+    i0_dp.crc32_h <= i0_dp_raw.crc32_h @[dec_decode_ctl.scala 281:23]
+    i0_dp.crc32_b <= i0_dp_raw.crc32_b @[dec_decode_ctl.scala 281:23]
+    i0_dp.zbp <= i0_dp_raw.zbp @[dec_decode_ctl.scala 281:23]
+    i0_dp.unshfl <= i0_dp_raw.unshfl @[dec_decode_ctl.scala 281:23]
+    i0_dp.shfl <= i0_dp_raw.shfl @[dec_decode_ctl.scala 281:23]
+    i0_dp.zbc <= i0_dp_raw.zbc @[dec_decode_ctl.scala 281:23]
+    i0_dp.clmulr <= i0_dp_raw.clmulr @[dec_decode_ctl.scala 281:23]
+    i0_dp.clmulh <= i0_dp_raw.clmulh @[dec_decode_ctl.scala 281:23]
+    i0_dp.clmul <= i0_dp_raw.clmul @[dec_decode_ctl.scala 281:23]
+    i0_dp.zbe <= i0_dp_raw.zbe @[dec_decode_ctl.scala 281:23]
+    i0_dp.bdep <= i0_dp_raw.bdep @[dec_decode_ctl.scala 281:23]
+    i0_dp.bext <= i0_dp_raw.bext @[dec_decode_ctl.scala 281:23]
+    i0_dp.zbs <= i0_dp_raw.zbs @[dec_decode_ctl.scala 281:23]
+    i0_dp.sbext <= i0_dp_raw.sbext @[dec_decode_ctl.scala 281:23]
+    i0_dp.sbinv <= i0_dp_raw.sbinv @[dec_decode_ctl.scala 281:23]
+    i0_dp.sbclr <= i0_dp_raw.sbclr @[dec_decode_ctl.scala 281:23]
+    i0_dp.sbset <= i0_dp_raw.sbset @[dec_decode_ctl.scala 281:23]
+    i0_dp.zbb <= i0_dp_raw.zbb @[dec_decode_ctl.scala 281:23]
+    i0_dp.gorc <= i0_dp_raw.gorc @[dec_decode_ctl.scala 281:23]
+    i0_dp.grev <= i0_dp_raw.grev @[dec_decode_ctl.scala 281:23]
+    i0_dp.ror <= i0_dp_raw.ror @[dec_decode_ctl.scala 281:23]
+    i0_dp.rol <= i0_dp_raw.rol @[dec_decode_ctl.scala 281:23]
+    i0_dp.packh <= i0_dp_raw.packh @[dec_decode_ctl.scala 281:23]
+    i0_dp.packu <= i0_dp_raw.packu @[dec_decode_ctl.scala 281:23]
+    i0_dp.pack <= i0_dp_raw.pack @[dec_decode_ctl.scala 281:23]
+    i0_dp.max <= i0_dp_raw.max @[dec_decode_ctl.scala 281:23]
+    i0_dp.min <= i0_dp_raw.min @[dec_decode_ctl.scala 281:23]
+    i0_dp.sro <= i0_dp_raw.sro @[dec_decode_ctl.scala 281:23]
+    i0_dp.slo <= i0_dp_raw.slo @[dec_decode_ctl.scala 281:23]
+    i0_dp.sext_h <= i0_dp_raw.sext_h @[dec_decode_ctl.scala 281:23]
+    i0_dp.sext_b <= i0_dp_raw.sext_b @[dec_decode_ctl.scala 281:23]
+    i0_dp.pcnt <= i0_dp_raw.pcnt @[dec_decode_ctl.scala 281:23]
+    i0_dp.ctz <= i0_dp_raw.ctz @[dec_decode_ctl.scala 281:23]
+    i0_dp.clz <= i0_dp_raw.clz @[dec_decode_ctl.scala 281:23]
+    node _T_80 = or(i0_br_error_all, i0_icaf_d) @[dec_decode_ctl.scala 282:25]
+    node _T_81 = bits(_T_80, 0, 0) @[dec_decode_ctl.scala 282:43]
+    when _T_81 : @[dec_decode_ctl.scala 282:50]
+      wire _T_82 : {clz : UInt<1>, ctz : UInt<1>, pcnt : UInt<1>, sext_b : UInt<1>, sext_h : UInt<1>, slo : UInt<1>, sro : UInt<1>, min : UInt<1>, max : UInt<1>, pack : UInt<1>, packu : UInt<1>, packh : UInt<1>, rol : UInt<1>, ror : UInt<1>, grev : UInt<1>, gorc : UInt<1>, zbb : UInt<1>, sbset : UInt<1>, sbclr : UInt<1>, sbinv : UInt<1>, sbext : UInt<1>, zbs : UInt<1>, bext : UInt<1>, bdep : UInt<1>, zbe : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, zbc : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, zbp : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, zbr : UInt<1>, bfp : UInt<1>, zbf : UInt<1>, sh1add : UInt<1>, sh2add : UInt<1>, sh3add : UInt<1>, zba : UInt<1>, alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[dec_decode_ctl.scala 283:38]
+      _T_82.legal <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.pm_alu <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.fence_i <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.fence <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.rem <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.div <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.low <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.rs2_sign <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.rs1_sign <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.mret <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.ecall <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.ebreak <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.postsync <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.presync <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.csr_imm <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.csr_write <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.csr_set <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.csr_clr <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.csr_read <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.word <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.half <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.by <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.jal <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.blt <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.bge <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.bne <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.beq <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.condbr <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.unsign <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.slt <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.srl <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.sra <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.sll <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.lxor <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.lor <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.land <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.sub <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.add <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.lsu <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.store <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.load <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.pc <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.imm20 <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.shimm5 <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.rd <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.imm12 <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.rs2 <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.rs1 <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.zba <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.sh3add <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.sh2add <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.sh1add <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.zbf <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.bfp <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.zbr <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.crc32c_w <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.crc32c_h <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.crc32c_b <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.crc32_w <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.crc32_h <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.crc32_b <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.zbp <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.unshfl <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.shfl <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.zbc <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.clmulr <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.clmulh <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.clmul <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.zbe <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.bdep <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.bext <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.zbs <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.sbext <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.sbinv <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.sbclr <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.sbset <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.zbb <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.gorc <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.grev <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.ror <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.rol <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.packh <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.packu <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.pack <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.max <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.min <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.sro <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.slo <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.sext_h <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.sext_b <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.pcnt <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.ctz <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      _T_82.clz <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
+      i0_dp.legal <= _T_82.legal @[dec_decode_ctl.scala 283:23]
+      i0_dp.pm_alu <= _T_82.pm_alu @[dec_decode_ctl.scala 283:23]
+      i0_dp.fence_i <= _T_82.fence_i @[dec_decode_ctl.scala 283:23]
+      i0_dp.fence <= _T_82.fence @[dec_decode_ctl.scala 283:23]
+      i0_dp.rem <= _T_82.rem @[dec_decode_ctl.scala 283:23]
+      i0_dp.div <= _T_82.div @[dec_decode_ctl.scala 283:23]
+      i0_dp.low <= _T_82.low @[dec_decode_ctl.scala 283:23]
+      i0_dp.rs2_sign <= _T_82.rs2_sign @[dec_decode_ctl.scala 283:23]
+      i0_dp.rs1_sign <= _T_82.rs1_sign @[dec_decode_ctl.scala 283:23]
+      i0_dp.mul <= _T_82.mul @[dec_decode_ctl.scala 283:23]
+      i0_dp.mret <= _T_82.mret @[dec_decode_ctl.scala 283:23]
+      i0_dp.ecall <= _T_82.ecall @[dec_decode_ctl.scala 283:23]
+      i0_dp.ebreak <= _T_82.ebreak @[dec_decode_ctl.scala 283:23]
+      i0_dp.postsync <= _T_82.postsync @[dec_decode_ctl.scala 283:23]
+      i0_dp.presync <= _T_82.presync @[dec_decode_ctl.scala 283:23]
+      i0_dp.csr_imm <= _T_82.csr_imm @[dec_decode_ctl.scala 283:23]
+      i0_dp.csr_write <= _T_82.csr_write @[dec_decode_ctl.scala 283:23]
+      i0_dp.csr_set <= _T_82.csr_set @[dec_decode_ctl.scala 283:23]
+      i0_dp.csr_clr <= _T_82.csr_clr @[dec_decode_ctl.scala 283:23]
+      i0_dp.csr_read <= _T_82.csr_read @[dec_decode_ctl.scala 283:23]
+      i0_dp.word <= _T_82.word @[dec_decode_ctl.scala 283:23]
+      i0_dp.half <= _T_82.half @[dec_decode_ctl.scala 283:23]
+      i0_dp.by <= _T_82.by @[dec_decode_ctl.scala 283:23]
+      i0_dp.jal <= _T_82.jal @[dec_decode_ctl.scala 283:23]
+      i0_dp.blt <= _T_82.blt @[dec_decode_ctl.scala 283:23]
+      i0_dp.bge <= _T_82.bge @[dec_decode_ctl.scala 283:23]
+      i0_dp.bne <= _T_82.bne @[dec_decode_ctl.scala 283:23]
+      i0_dp.beq <= _T_82.beq @[dec_decode_ctl.scala 283:23]
+      i0_dp.condbr <= _T_82.condbr @[dec_decode_ctl.scala 283:23]
+      i0_dp.unsign <= _T_82.unsign @[dec_decode_ctl.scala 283:23]
+      i0_dp.slt <= _T_82.slt @[dec_decode_ctl.scala 283:23]
+      i0_dp.srl <= _T_82.srl @[dec_decode_ctl.scala 283:23]
+      i0_dp.sra <= _T_82.sra @[dec_decode_ctl.scala 283:23]
+      i0_dp.sll <= _T_82.sll @[dec_decode_ctl.scala 283:23]
+      i0_dp.lxor <= _T_82.lxor @[dec_decode_ctl.scala 283:23]
+      i0_dp.lor <= _T_82.lor @[dec_decode_ctl.scala 283:23]
+      i0_dp.land <= _T_82.land @[dec_decode_ctl.scala 283:23]
+      i0_dp.sub <= _T_82.sub @[dec_decode_ctl.scala 283:23]
+      i0_dp.add <= _T_82.add @[dec_decode_ctl.scala 283:23]
+      i0_dp.lsu <= _T_82.lsu @[dec_decode_ctl.scala 283:23]
+      i0_dp.store <= _T_82.store @[dec_decode_ctl.scala 283:23]
+      i0_dp.load <= _T_82.load @[dec_decode_ctl.scala 283:23]
+      i0_dp.pc <= _T_82.pc @[dec_decode_ctl.scala 283:23]
+      i0_dp.imm20 <= _T_82.imm20 @[dec_decode_ctl.scala 283:23]
+      i0_dp.shimm5 <= _T_82.shimm5 @[dec_decode_ctl.scala 283:23]
+      i0_dp.rd <= _T_82.rd @[dec_decode_ctl.scala 283:23]
+      i0_dp.imm12 <= _T_82.imm12 @[dec_decode_ctl.scala 283:23]
+      i0_dp.rs2 <= _T_82.rs2 @[dec_decode_ctl.scala 283:23]
+      i0_dp.rs1 <= _T_82.rs1 @[dec_decode_ctl.scala 283:23]
+      i0_dp.alu <= _T_82.alu @[dec_decode_ctl.scala 283:23]
+      i0_dp.zba <= _T_82.zba @[dec_decode_ctl.scala 283:23]
+      i0_dp.sh3add <= _T_82.sh3add @[dec_decode_ctl.scala 283:23]
+      i0_dp.sh2add <= _T_82.sh2add @[dec_decode_ctl.scala 283:23]
+      i0_dp.sh1add <= _T_82.sh1add @[dec_decode_ctl.scala 283:23]
+      i0_dp.zbf <= _T_82.zbf @[dec_decode_ctl.scala 283:23]
+      i0_dp.bfp <= _T_82.bfp @[dec_decode_ctl.scala 283:23]
+      i0_dp.zbr <= _T_82.zbr @[dec_decode_ctl.scala 283:23]
+      i0_dp.crc32c_w <= _T_82.crc32c_w @[dec_decode_ctl.scala 283:23]
+      i0_dp.crc32c_h <= _T_82.crc32c_h @[dec_decode_ctl.scala 283:23]
+      i0_dp.crc32c_b <= _T_82.crc32c_b @[dec_decode_ctl.scala 283:23]
+      i0_dp.crc32_w <= _T_82.crc32_w @[dec_decode_ctl.scala 283:23]
+      i0_dp.crc32_h <= _T_82.crc32_h @[dec_decode_ctl.scala 283:23]
+      i0_dp.crc32_b <= _T_82.crc32_b @[dec_decode_ctl.scala 283:23]
+      i0_dp.zbp <= _T_82.zbp @[dec_decode_ctl.scala 283:23]
+      i0_dp.unshfl <= _T_82.unshfl @[dec_decode_ctl.scala 283:23]
+      i0_dp.shfl <= _T_82.shfl @[dec_decode_ctl.scala 283:23]
+      i0_dp.zbc <= _T_82.zbc @[dec_decode_ctl.scala 283:23]
+      i0_dp.clmulr <= _T_82.clmulr @[dec_decode_ctl.scala 283:23]
+      i0_dp.clmulh <= _T_82.clmulh @[dec_decode_ctl.scala 283:23]
+      i0_dp.clmul <= _T_82.clmul @[dec_decode_ctl.scala 283:23]
+      i0_dp.zbe <= _T_82.zbe @[dec_decode_ctl.scala 283:23]
+      i0_dp.bdep <= _T_82.bdep @[dec_decode_ctl.scala 283:23]
+      i0_dp.bext <= _T_82.bext @[dec_decode_ctl.scala 283:23]
+      i0_dp.zbs <= _T_82.zbs @[dec_decode_ctl.scala 283:23]
+      i0_dp.sbext <= _T_82.sbext @[dec_decode_ctl.scala 283:23]
+      i0_dp.sbinv <= _T_82.sbinv @[dec_decode_ctl.scala 283:23]
+      i0_dp.sbclr <= _T_82.sbclr @[dec_decode_ctl.scala 283:23]
+      i0_dp.sbset <= _T_82.sbset @[dec_decode_ctl.scala 283:23]
+      i0_dp.zbb <= _T_82.zbb @[dec_decode_ctl.scala 283:23]
+      i0_dp.gorc <= _T_82.gorc @[dec_decode_ctl.scala 283:23]
+      i0_dp.grev <= _T_82.grev @[dec_decode_ctl.scala 283:23]
+      i0_dp.ror <= _T_82.ror @[dec_decode_ctl.scala 283:23]
+      i0_dp.rol <= _T_82.rol @[dec_decode_ctl.scala 283:23]
+      i0_dp.packh <= _T_82.packh @[dec_decode_ctl.scala 283:23]
+      i0_dp.packu <= _T_82.packu @[dec_decode_ctl.scala 283:23]
+      i0_dp.pack <= _T_82.pack @[dec_decode_ctl.scala 283:23]
+      i0_dp.max <= _T_82.max @[dec_decode_ctl.scala 283:23]
+      i0_dp.min <= _T_82.min @[dec_decode_ctl.scala 283:23]
+      i0_dp.sro <= _T_82.sro @[dec_decode_ctl.scala 283:23]
+      i0_dp.slo <= _T_82.slo @[dec_decode_ctl.scala 283:23]
+      i0_dp.sext_h <= _T_82.sext_h @[dec_decode_ctl.scala 283:23]
+      i0_dp.sext_b <= _T_82.sext_b @[dec_decode_ctl.scala 283:23]
+      i0_dp.pcnt <= _T_82.pcnt @[dec_decode_ctl.scala 283:23]
+      i0_dp.ctz <= _T_82.ctz @[dec_decode_ctl.scala 283:23]
+      i0_dp.clz <= _T_82.clz @[dec_decode_ctl.scala 283:23]
+      i0_dp.alu <= UInt<1>("h01") @[dec_decode_ctl.scala 284:23]
+      i0_dp.rs1 <= UInt<1>("h01") @[dec_decode_ctl.scala 285:23]
+      i0_dp.rs2 <= UInt<1>("h01") @[dec_decode_ctl.scala 286:23]
+      i0_dp.lor <= UInt<1>("h01") @[dec_decode_ctl.scala 287:23]
+      i0_dp.legal <= UInt<1>("h01") @[dec_decode_ctl.scala 288:23]
+      i0_dp.postsync <= UInt<1>("h01") @[dec_decode_ctl.scala 289:23]
+      skip @[dec_decode_ctl.scala 282:50]
+    io.decode_exu.dec_i0_select_pc_d <= i0_dp.pc @[dec_decode_ctl.scala 293:36]
+    node _T_83 = or(i0_dp.condbr, i0_pcall) @[dec_decode_ctl.scala 296:54]
+    node _T_84 = or(_T_83, i0_pja) @[dec_decode_ctl.scala 296:65]
+    node i0_predict_br = or(_T_84, i0_pret) @[dec_decode_ctl.scala 296:74]
+    node _T_85 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[dec_decode_ctl.scala 297:65]
+    node _T_86 = and(_T_85, i0_brp_valid) @[dec_decode_ctl.scala 297:69]
+    node _T_87 = eq(_T_86, UInt<1>("h00")) @[dec_decode_ctl.scala 297:40]
+    node i0_predict_nt = and(_T_87, i0_predict_br) @[dec_decode_ctl.scala 297:85]
+    node _T_88 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[dec_decode_ctl.scala 298:65]
+    node _T_89 = and(_T_88, i0_brp_valid) @[dec_decode_ctl.scala 298:69]
+    node i0_predict_t = and(_T_89, i0_predict_br) @[dec_decode_ctl.scala 298:85]
+    node i0_ap_pc2 = eq(io.dec_i0_pc4_d, UInt<1>("h00")) @[dec_decode_ctl.scala 299:40]
+    io.decode_exu.i0_ap.predict_nt <= i0_predict_nt @[dec_decode_ctl.scala 301:37]
+    io.decode_exu.i0_ap.predict_t <= i0_predict_t @[dec_decode_ctl.scala 302:37]
+    io.decode_exu.i0_ap.add <= i0_dp.add @[dec_decode_ctl.scala 305:33]
+    io.decode_exu.i0_ap.sub <= i0_dp.sub @[dec_decode_ctl.scala 306:33]
+    io.decode_exu.i0_ap.land <= i0_dp.land @[dec_decode_ctl.scala 307:33]
+    io.decode_exu.i0_ap.lor <= i0_dp.lor @[dec_decode_ctl.scala 308:33]
+    io.decode_exu.i0_ap.lxor <= i0_dp.lxor @[dec_decode_ctl.scala 309:33]
+    io.decode_exu.i0_ap.sll <= i0_dp.sll @[dec_decode_ctl.scala 310:33]
+    io.decode_exu.i0_ap.srl <= i0_dp.srl @[dec_decode_ctl.scala 311:33]
+    io.decode_exu.i0_ap.sra <= i0_dp.sra @[dec_decode_ctl.scala 312:33]
+    io.decode_exu.i0_ap.slt <= i0_dp.slt @[dec_decode_ctl.scala 313:33]
+    io.decode_exu.i0_ap.unsign <= i0_dp.unsign @[dec_decode_ctl.scala 314:33]
+    io.decode_exu.i0_ap.beq <= i0_dp.beq @[dec_decode_ctl.scala 315:33]
+    io.decode_exu.i0_ap.bne <= i0_dp.bne @[dec_decode_ctl.scala 316:33]
+    io.decode_exu.i0_ap.blt <= i0_dp.blt @[dec_decode_ctl.scala 317:33]
+    io.decode_exu.i0_ap.bge <= i0_dp.bge @[dec_decode_ctl.scala 318:33]
+    io.decode_exu.i0_ap.clz <= i0_dp.clz @[dec_decode_ctl.scala 319:33]
+    io.decode_exu.i0_ap.ctz <= i0_dp.ctz @[dec_decode_ctl.scala 320:33]
+    io.decode_exu.i0_ap.pcnt <= i0_dp.pcnt @[dec_decode_ctl.scala 321:33]
+    io.decode_exu.i0_ap.sext_b <= i0_dp.sext_b @[dec_decode_ctl.scala 322:33]
+    io.decode_exu.i0_ap.sext_h <= i0_dp.sext_h @[dec_decode_ctl.scala 323:33]
+    io.decode_exu.i0_ap.sh1add <= i0_dp.sh1add @[dec_decode_ctl.scala 324:33]
+    io.decode_exu.i0_ap.sh2add <= i0_dp.sh2add @[dec_decode_ctl.scala 325:33]
+    io.decode_exu.i0_ap.sh3add <= i0_dp.sh3add @[dec_decode_ctl.scala 326:33]
+    io.decode_exu.i0_ap.zba <= i0_dp.zba @[dec_decode_ctl.scala 327:33]
+    io.decode_exu.i0_ap.slo <= i0_dp.slo @[dec_decode_ctl.scala 328:33]
+    io.decode_exu.i0_ap.sro <= i0_dp.sro @[dec_decode_ctl.scala 329:33]
+    io.decode_exu.i0_ap.min <= i0_dp.min @[dec_decode_ctl.scala 330:33]
+    io.decode_exu.i0_ap.max <= i0_dp.max @[dec_decode_ctl.scala 331:33]
+    io.decode_exu.i0_ap.pack <= i0_dp.pack @[dec_decode_ctl.scala 332:33]
+    io.decode_exu.i0_ap.packu <= i0_dp.packu @[dec_decode_ctl.scala 333:33]
+    io.decode_exu.i0_ap.packh <= i0_dp.packh @[dec_decode_ctl.scala 334:33]
+    io.decode_exu.i0_ap.rol <= i0_dp.rol @[dec_decode_ctl.scala 335:33]
+    io.decode_exu.i0_ap.ror <= i0_dp.ror @[dec_decode_ctl.scala 336:33]
+    io.decode_exu.i0_ap.grev <= i0_dp.grev @[dec_decode_ctl.scala 337:33]
+    io.decode_exu.i0_ap.gorc <= i0_dp.gorc @[dec_decode_ctl.scala 338:33]
+    io.decode_exu.i0_ap.zbb <= i0_dp.zbb @[dec_decode_ctl.scala 339:33]
+    io.decode_exu.i0_ap.sbset <= i0_dp.sbset @[dec_decode_ctl.scala 340:33]
+    io.decode_exu.i0_ap.sbclr <= i0_dp.sbclr @[dec_decode_ctl.scala 341:33]
+    io.decode_exu.i0_ap.sbinv <= i0_dp.sbinv @[dec_decode_ctl.scala 342:33]
+    io.decode_exu.i0_ap.sbext <= i0_dp.sbext @[dec_decode_ctl.scala 343:33]
+    io.decode_exu.i0_ap.csr_write <= i0_csr_write_only_d @[dec_decode_ctl.scala 344:33]
+    io.decode_exu.i0_ap.csr_imm <= i0_dp.csr_imm @[dec_decode_ctl.scala 345:33]
+    io.decode_exu.i0_ap.jal <= i0_jal @[dec_decode_ctl.scala 346:33]
+    node _T_90 = eq(cam[0].valid, UInt<1>("h00")) @[dec_decode_ctl.scala 350:78]
+    node _T_91 = bits(_T_90, 0, 0) @[dec_decode_ctl.scala 350:137]
+    node _T_92 = shl(cam_write, 0) @[dec_decode_ctl.scala 350:158]
+    node _T_93 = eq(cam[1].valid, UInt<1>("h00")) @[dec_decode_ctl.scala 350:78]
+    node _T_94 = bits(cam[0].valid, 0, 0) @[dec_decode_ctl.scala 350:120]
+    node _T_95 = bits(_T_93, 0, 0) @[dec_decode_ctl.scala 350:129]
+    node _T_96 = and(_T_94, _T_95) @[dec_decode_ctl.scala 350:126]
+    node _T_97 = bits(_T_96, 0, 0) @[dec_decode_ctl.scala 350:137]
+    node _T_98 = shl(cam_write, 1) @[dec_decode_ctl.scala 350:158]
+    node _T_99 = eq(cam[2].valid, UInt<1>("h00")) @[dec_decode_ctl.scala 350:78]
+    node _T_100 = bits(cam[0].valid, 0, 0) @[dec_decode_ctl.scala 350:120]
+    node _T_101 = bits(cam[1].valid, 0, 0) @[dec_decode_ctl.scala 350:129]
+    node _T_102 = and(_T_100, _T_101) @[dec_decode_ctl.scala 350:126]
+    node _T_103 = bits(_T_102, 0, 0) @[dec_decode_ctl.scala 350:120]
+    node _T_104 = bits(_T_99, 0, 0) @[dec_decode_ctl.scala 350:129]
+    node _T_105 = and(_T_103, _T_104) @[dec_decode_ctl.scala 350:126]
+    node _T_106 = bits(_T_105, 0, 0) @[dec_decode_ctl.scala 350:137]
+    node _T_107 = shl(cam_write, 2) @[dec_decode_ctl.scala 350:158]
+    node _T_108 = eq(cam[3].valid, UInt<1>("h00")) @[dec_decode_ctl.scala 350:78]
+    node _T_109 = bits(cam[0].valid, 0, 0) @[dec_decode_ctl.scala 350:120]
+    node _T_110 = bits(cam[1].valid, 0, 0) @[dec_decode_ctl.scala 350:129]
+    node _T_111 = and(_T_109, _T_110) @[dec_decode_ctl.scala 350:126]
+    node _T_112 = bits(_T_111, 0, 0) @[dec_decode_ctl.scala 350:120]
+    node _T_113 = bits(cam[2].valid, 0, 0) @[dec_decode_ctl.scala 350:129]
+    node _T_114 = and(_T_112, _T_113) @[dec_decode_ctl.scala 350:126]
+    node _T_115 = bits(_T_114, 0, 0) @[dec_decode_ctl.scala 350:120]
+    node _T_116 = bits(_T_108, 0, 0) @[dec_decode_ctl.scala 350:129]
+    node _T_117 = and(_T_115, _T_116) @[dec_decode_ctl.scala 350:126]
+    node _T_118 = bits(_T_117, 0, 0) @[dec_decode_ctl.scala 350:137]
+    node _T_119 = shl(cam_write, 3) @[dec_decode_ctl.scala 350:158]
     node _T_120 = mux(_T_91, _T_92, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_121 = mux(_T_97, _T_98, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_122 = mux(_T_106, _T_107, UInt<1>("h00")) @[Mux.scala 27:72]
@@ -5622,79 +5622,79 @@ circuit dec :
     node _T_126 = or(_T_125, _T_123) @[Mux.scala 27:72]
     wire _T_127 : UInt<4> @[Mux.scala 27:72]
     _T_127 <= _T_126 @[Mux.scala 27:72]
-    cam_wen <= _T_127 @[dec_decode_ctl.scala 348:11]
-    cam_write <= io.dctl_busbuff.lsu_nonblock_load_valid_m @[dec_decode_ctl.scala 350:25]
-    node cam_write_tag = bits(io.dctl_busbuff.lsu_nonblock_load_tag_m, 1, 0) @[dec_decode_ctl.scala 351:67]
-    node cam_data_reset = or(io.dctl_busbuff.lsu_nonblock_load_data_valid, io.dctl_busbuff.lsu_nonblock_load_data_error) @[dec_decode_ctl.scala 356:76]
-    node _T_128 = bits(x_d.bits.i0load, 0, 0) @[dec_decode_ctl.scala 359:48]
-    node nonblock_load_rd = mux(_T_128, x_d.bits.i0rd, UInt<5>("h00")) @[dec_decode_ctl.scala 359:31]
-    node _T_129 = bits(i0_r_ctl_en, 0, 0) @[dec_decode_ctl.scala 363:129]
+    cam_wen <= _T_127 @[dec_decode_ctl.scala 350:11]
+    cam_write <= io.dctl_busbuff.lsu_nonblock_load_valid_m @[dec_decode_ctl.scala 352:25]
+    node cam_write_tag = bits(io.dctl_busbuff.lsu_nonblock_load_tag_m, 1, 0) @[dec_decode_ctl.scala 353:67]
+    node cam_data_reset = or(io.dctl_busbuff.lsu_nonblock_load_data_valid, io.dctl_busbuff.lsu_nonblock_load_data_error) @[dec_decode_ctl.scala 358:76]
+    node _T_128 = bits(x_d.bits.i0load, 0, 0) @[dec_decode_ctl.scala 361:48]
+    node nonblock_load_rd = mux(_T_128, x_d.bits.i0rd, UInt<5>("h00")) @[dec_decode_ctl.scala 361:31]
+    node _T_129 = bits(i0_r_ctl_en, 0, 0) @[dec_decode_ctl.scala 365:129]
     reg nonblock_load_valid_m_delay : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when _T_129 : @[Reg.scala 28:19]
       nonblock_load_valid_m_delay <= io.dctl_busbuff.lsu_nonblock_load_valid_m @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    node i0_load_kill_wen_r = and(nonblock_load_valid_m_delay, r_d.bits.i0load) @[dec_decode_ctl.scala 364:56]
-    node _T_130 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[0].bits.tag) @[dec_decode_ctl.scala 366:66]
-    node _T_131 = and(io.dctl_busbuff.lsu_nonblock_load_inv_r, _T_130) @[dec_decode_ctl.scala 366:45]
-    node _T_132 = and(_T_131, cam[0].valid) @[dec_decode_ctl.scala 366:87]
-    cam_inv_reset_val[0] <= _T_132 @[dec_decode_ctl.scala 366:26]
-    node _T_133 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam[0].bits.tag) @[dec_decode_ctl.scala 367:67]
-    node _T_134 = and(cam_data_reset, _T_133) @[dec_decode_ctl.scala 367:45]
-    node _T_135 = and(_T_134, cam_raw[0].valid) @[dec_decode_ctl.scala 367:88]
-    cam_data_reset_val[0] <= _T_135 @[dec_decode_ctl.scala 367:27]
-    wire _T_136 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 368:28]
-    _T_136.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 368:28]
-    _T_136.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 368:28]
-    _T_136.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 368:28]
-    _T_136.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 368:28]
-    cam_in[0].bits.rd <= _T_136.bits.rd @[dec_decode_ctl.scala 368:14]
-    cam_in[0].bits.tag <= _T_136.bits.tag @[dec_decode_ctl.scala 368:14]
-    cam_in[0].bits.wb <= _T_136.bits.wb @[dec_decode_ctl.scala 368:14]
-    cam_in[0].valid <= _T_136.valid @[dec_decode_ctl.scala 368:14]
-    cam[0].bits.rd <= cam_raw[0].bits.rd @[dec_decode_ctl.scala 369:11]
-    cam[0].bits.tag <= cam_raw[0].bits.tag @[dec_decode_ctl.scala 369:11]
-    cam[0].bits.wb <= cam_raw[0].bits.wb @[dec_decode_ctl.scala 369:11]
-    cam[0].valid <= cam_raw[0].valid @[dec_decode_ctl.scala 369:11]
-    node _T_137 = bits(cam_data_reset_val[0], 0, 0) @[dec_decode_ctl.scala 371:32]
-    when _T_137 : @[dec_decode_ctl.scala 371:39]
-      cam[0].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 372:20]
-      skip @[dec_decode_ctl.scala 371:39]
-    node _T_138 = bits(cam_wen, 0, 0) @[dec_decode_ctl.scala 374:17]
-    node _T_139 = bits(_T_138, 0, 0) @[dec_decode_ctl.scala 374:21]
-    when _T_139 : @[dec_decode_ctl.scala 374:28]
-      cam_in[0].valid <= UInt<1>("h01") @[dec_decode_ctl.scala 375:27]
-      cam_in[0].bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 376:32]
-      cam_in[0].bits.tag <= cam_write_tag @[dec_decode_ctl.scala 377:32]
-      cam_in[0].bits.rd <= nonblock_load_rd @[dec_decode_ctl.scala 378:32]
-      skip @[dec_decode_ctl.scala 374:28]
-    else : @[dec_decode_ctl.scala 379:131]
-      node _T_140 = bits(cam_inv_reset_val[0], 0, 0) @[dec_decode_ctl.scala 379:37]
-      node _T_141 = bits(i0_wen_r, 0, 0) @[dec_decode_ctl.scala 379:57]
-      node _T_142 = eq(r_d_in.bits.i0rd, cam[0].bits.rd) @[dec_decode_ctl.scala 379:85]
-      node _T_143 = and(_T_141, _T_142) @[dec_decode_ctl.scala 379:64]
-      node _T_144 = bits(cam[0].bits.wb, 0, 0) @[dec_decode_ctl.scala 379:123]
-      node _T_145 = and(_T_143, _T_144) @[dec_decode_ctl.scala 379:105]
-      node _T_146 = or(_T_140, _T_145) @[dec_decode_ctl.scala 379:44]
-      when _T_146 : @[dec_decode_ctl.scala 379:131]
-        cam_in[0].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 380:23]
-        skip @[dec_decode_ctl.scala 379:131]
-      else : @[dec_decode_ctl.scala 381:16]
-        cam_in[0].bits.rd <= cam[0].bits.rd @[dec_decode_ctl.scala 382:22]
-        cam_in[0].bits.tag <= cam[0].bits.tag @[dec_decode_ctl.scala 382:22]
-        cam_in[0].bits.wb <= cam[0].bits.wb @[dec_decode_ctl.scala 382:22]
-        cam_in[0].valid <= cam[0].valid @[dec_decode_ctl.scala 382:22]
-        skip @[dec_decode_ctl.scala 381:16]
-    node _T_147 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[dec_decode_ctl.scala 384:37]
-    node _T_148 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[0].bits.tag) @[dec_decode_ctl.scala 384:92]
-    node _T_149 = and(_T_147, _T_148) @[dec_decode_ctl.scala 384:44]
-    node _T_150 = eq(cam[0].valid, UInt<1>("h01")) @[dec_decode_ctl.scala 384:128]
-    node _T_151 = and(_T_149, _T_150) @[dec_decode_ctl.scala 384:113]
-    when _T_151 : @[dec_decode_ctl.scala 384:135]
-      cam_in[0].bits.wb <= UInt<1>("h01") @[dec_decode_ctl.scala 385:25]
-      skip @[dec_decode_ctl.scala 384:135]
-    when io.dec_tlu_force_halt : @[dec_decode_ctl.scala 388:32]
-      cam_in[0].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 389:23]
-      skip @[dec_decode_ctl.scala 388:32]
+    node i0_load_kill_wen_r = and(nonblock_load_valid_m_delay, r_d.bits.i0load) @[dec_decode_ctl.scala 366:56]
+    node _T_130 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[0].bits.tag) @[dec_decode_ctl.scala 368:66]
+    node _T_131 = and(io.dctl_busbuff.lsu_nonblock_load_inv_r, _T_130) @[dec_decode_ctl.scala 368:45]
+    node _T_132 = and(_T_131, cam[0].valid) @[dec_decode_ctl.scala 368:87]
+    cam_inv_reset_val[0] <= _T_132 @[dec_decode_ctl.scala 368:26]
+    node _T_133 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam[0].bits.tag) @[dec_decode_ctl.scala 369:67]
+    node _T_134 = and(cam_data_reset, _T_133) @[dec_decode_ctl.scala 369:45]
+    node _T_135 = and(_T_134, cam_raw[0].valid) @[dec_decode_ctl.scala 369:88]
+    cam_data_reset_val[0] <= _T_135 @[dec_decode_ctl.scala 369:27]
+    wire _T_136 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 370:28]
+    _T_136.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 370:28]
+    _T_136.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 370:28]
+    _T_136.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 370:28]
+    _T_136.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 370:28]
+    cam_in[0].bits.rd <= _T_136.bits.rd @[dec_decode_ctl.scala 370:14]
+    cam_in[0].bits.tag <= _T_136.bits.tag @[dec_decode_ctl.scala 370:14]
+    cam_in[0].bits.wb <= _T_136.bits.wb @[dec_decode_ctl.scala 370:14]
+    cam_in[0].valid <= _T_136.valid @[dec_decode_ctl.scala 370:14]
+    cam[0].bits.rd <= cam_raw[0].bits.rd @[dec_decode_ctl.scala 371:11]
+    cam[0].bits.tag <= cam_raw[0].bits.tag @[dec_decode_ctl.scala 371:11]
+    cam[0].bits.wb <= cam_raw[0].bits.wb @[dec_decode_ctl.scala 371:11]
+    cam[0].valid <= cam_raw[0].valid @[dec_decode_ctl.scala 371:11]
+    node _T_137 = bits(cam_data_reset_val[0], 0, 0) @[dec_decode_ctl.scala 373:32]
+    when _T_137 : @[dec_decode_ctl.scala 373:39]
+      cam[0].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 374:20]
+      skip @[dec_decode_ctl.scala 373:39]
+    node _T_138 = bits(cam_wen, 0, 0) @[dec_decode_ctl.scala 376:17]
+    node _T_139 = bits(_T_138, 0, 0) @[dec_decode_ctl.scala 376:21]
+    when _T_139 : @[dec_decode_ctl.scala 376:28]
+      cam_in[0].valid <= UInt<1>("h01") @[dec_decode_ctl.scala 377:27]
+      cam_in[0].bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 378:32]
+      cam_in[0].bits.tag <= cam_write_tag @[dec_decode_ctl.scala 379:32]
+      cam_in[0].bits.rd <= nonblock_load_rd @[dec_decode_ctl.scala 380:32]
+      skip @[dec_decode_ctl.scala 376:28]
+    else : @[dec_decode_ctl.scala 381:131]
+      node _T_140 = bits(cam_inv_reset_val[0], 0, 0) @[dec_decode_ctl.scala 381:37]
+      node _T_141 = bits(i0_wen_r, 0, 0) @[dec_decode_ctl.scala 381:57]
+      node _T_142 = eq(r_d_in.bits.i0rd, cam[0].bits.rd) @[dec_decode_ctl.scala 381:85]
+      node _T_143 = and(_T_141, _T_142) @[dec_decode_ctl.scala 381:64]
+      node _T_144 = bits(cam[0].bits.wb, 0, 0) @[dec_decode_ctl.scala 381:123]
+      node _T_145 = and(_T_143, _T_144) @[dec_decode_ctl.scala 381:105]
+      node _T_146 = or(_T_140, _T_145) @[dec_decode_ctl.scala 381:44]
+      when _T_146 : @[dec_decode_ctl.scala 381:131]
+        cam_in[0].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 382:23]
+        skip @[dec_decode_ctl.scala 381:131]
+      else : @[dec_decode_ctl.scala 383:16]
+        cam_in[0].bits.rd <= cam[0].bits.rd @[dec_decode_ctl.scala 384:22]
+        cam_in[0].bits.tag <= cam[0].bits.tag @[dec_decode_ctl.scala 384:22]
+        cam_in[0].bits.wb <= cam[0].bits.wb @[dec_decode_ctl.scala 384:22]
+        cam_in[0].valid <= cam[0].valid @[dec_decode_ctl.scala 384:22]
+        skip @[dec_decode_ctl.scala 383:16]
+    node _T_147 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[dec_decode_ctl.scala 386:37]
+    node _T_148 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[0].bits.tag) @[dec_decode_ctl.scala 386:92]
+    node _T_149 = and(_T_147, _T_148) @[dec_decode_ctl.scala 386:44]
+    node _T_150 = eq(cam[0].valid, UInt<1>("h01")) @[dec_decode_ctl.scala 386:128]
+    node _T_151 = and(_T_149, _T_150) @[dec_decode_ctl.scala 386:113]
+    when _T_151 : @[dec_decode_ctl.scala 386:135]
+      cam_in[0].bits.wb <= UInt<1>("h01") @[dec_decode_ctl.scala 387:25]
+      skip @[dec_decode_ctl.scala 386:135]
+    when io.dec_tlu_force_halt : @[dec_decode_ctl.scala 390:32]
+      cam_in[0].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 391:23]
+      skip @[dec_decode_ctl.scala 390:32]
     wire _T_152 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}
     _T_152.bits.rd <= cam_in[0].bits.rd
     _T_152.bits.tag <= cam_in[0].bits.tag
@@ -5725,74 +5725,74 @@ circuit dec :
     _T_152.bits.tag <= _T_163.bits.tag @[lib.scala 497:16]
     _T_152.bits.wb <= _T_163.bits.wb @[lib.scala 497:16]
     _T_152.valid <= _T_163.valid @[lib.scala 497:16]
-    cam_raw[0].bits.rd <= _T_152.bits.rd @[dec_decode_ctl.scala 392:15]
-    cam_raw[0].bits.tag <= _T_152.bits.tag @[dec_decode_ctl.scala 392:15]
-    cam_raw[0].bits.wb <= _T_152.bits.wb @[dec_decode_ctl.scala 392:15]
-    cam_raw[0].valid <= _T_152.valid @[dec_decode_ctl.scala 392:15]
-    node _T_164 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam_raw[0].bits.tag) @[dec_decode_ctl.scala 393:46]
-    node _T_165 = and(_T_164, cam_raw[0].valid) @[dec_decode_ctl.scala 393:71]
-    nonblock_load_write[0] <= _T_165 @[dec_decode_ctl.scala 393:28]
-    node _T_166 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[1].bits.tag) @[dec_decode_ctl.scala 366:66]
-    node _T_167 = and(io.dctl_busbuff.lsu_nonblock_load_inv_r, _T_166) @[dec_decode_ctl.scala 366:45]
-    node _T_168 = and(_T_167, cam[1].valid) @[dec_decode_ctl.scala 366:87]
-    cam_inv_reset_val[1] <= _T_168 @[dec_decode_ctl.scala 366:26]
-    node _T_169 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam[1].bits.tag) @[dec_decode_ctl.scala 367:67]
-    node _T_170 = and(cam_data_reset, _T_169) @[dec_decode_ctl.scala 367:45]
-    node _T_171 = and(_T_170, cam_raw[1].valid) @[dec_decode_ctl.scala 367:88]
-    cam_data_reset_val[1] <= _T_171 @[dec_decode_ctl.scala 367:27]
-    wire _T_172 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 368:28]
-    _T_172.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 368:28]
-    _T_172.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 368:28]
-    _T_172.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 368:28]
-    _T_172.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 368:28]
-    cam_in[1].bits.rd <= _T_172.bits.rd @[dec_decode_ctl.scala 368:14]
-    cam_in[1].bits.tag <= _T_172.bits.tag @[dec_decode_ctl.scala 368:14]
-    cam_in[1].bits.wb <= _T_172.bits.wb @[dec_decode_ctl.scala 368:14]
-    cam_in[1].valid <= _T_172.valid @[dec_decode_ctl.scala 368:14]
-    cam[1].bits.rd <= cam_raw[1].bits.rd @[dec_decode_ctl.scala 369:11]
-    cam[1].bits.tag <= cam_raw[1].bits.tag @[dec_decode_ctl.scala 369:11]
-    cam[1].bits.wb <= cam_raw[1].bits.wb @[dec_decode_ctl.scala 369:11]
-    cam[1].valid <= cam_raw[1].valid @[dec_decode_ctl.scala 369:11]
-    node _T_173 = bits(cam_data_reset_val[1], 0, 0) @[dec_decode_ctl.scala 371:32]
-    when _T_173 : @[dec_decode_ctl.scala 371:39]
-      cam[1].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 372:20]
-      skip @[dec_decode_ctl.scala 371:39]
-    node _T_174 = bits(cam_wen, 1, 1) @[dec_decode_ctl.scala 374:17]
-    node _T_175 = bits(_T_174, 0, 0) @[dec_decode_ctl.scala 374:21]
-    when _T_175 : @[dec_decode_ctl.scala 374:28]
-      cam_in[1].valid <= UInt<1>("h01") @[dec_decode_ctl.scala 375:27]
-      cam_in[1].bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 376:32]
-      cam_in[1].bits.tag <= cam_write_tag @[dec_decode_ctl.scala 377:32]
-      cam_in[1].bits.rd <= nonblock_load_rd @[dec_decode_ctl.scala 378:32]
-      skip @[dec_decode_ctl.scala 374:28]
-    else : @[dec_decode_ctl.scala 379:131]
-      node _T_176 = bits(cam_inv_reset_val[1], 0, 0) @[dec_decode_ctl.scala 379:37]
-      node _T_177 = bits(i0_wen_r, 0, 0) @[dec_decode_ctl.scala 379:57]
-      node _T_178 = eq(r_d_in.bits.i0rd, cam[1].bits.rd) @[dec_decode_ctl.scala 379:85]
-      node _T_179 = and(_T_177, _T_178) @[dec_decode_ctl.scala 379:64]
-      node _T_180 = bits(cam[1].bits.wb, 0, 0) @[dec_decode_ctl.scala 379:123]
-      node _T_181 = and(_T_179, _T_180) @[dec_decode_ctl.scala 379:105]
-      node _T_182 = or(_T_176, _T_181) @[dec_decode_ctl.scala 379:44]
-      when _T_182 : @[dec_decode_ctl.scala 379:131]
-        cam_in[1].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 380:23]
-        skip @[dec_decode_ctl.scala 379:131]
-      else : @[dec_decode_ctl.scala 381:16]
-        cam_in[1].bits.rd <= cam[1].bits.rd @[dec_decode_ctl.scala 382:22]
-        cam_in[1].bits.tag <= cam[1].bits.tag @[dec_decode_ctl.scala 382:22]
-        cam_in[1].bits.wb <= cam[1].bits.wb @[dec_decode_ctl.scala 382:22]
-        cam_in[1].valid <= cam[1].valid @[dec_decode_ctl.scala 382:22]
-        skip @[dec_decode_ctl.scala 381:16]
-    node _T_183 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[dec_decode_ctl.scala 384:37]
-    node _T_184 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[1].bits.tag) @[dec_decode_ctl.scala 384:92]
-    node _T_185 = and(_T_183, _T_184) @[dec_decode_ctl.scala 384:44]
-    node _T_186 = eq(cam[1].valid, UInt<1>("h01")) @[dec_decode_ctl.scala 384:128]
-    node _T_187 = and(_T_185, _T_186) @[dec_decode_ctl.scala 384:113]
-    when _T_187 : @[dec_decode_ctl.scala 384:135]
-      cam_in[1].bits.wb <= UInt<1>("h01") @[dec_decode_ctl.scala 385:25]
-      skip @[dec_decode_ctl.scala 384:135]
-    when io.dec_tlu_force_halt : @[dec_decode_ctl.scala 388:32]
-      cam_in[1].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 389:23]
-      skip @[dec_decode_ctl.scala 388:32]
+    cam_raw[0].bits.rd <= _T_152.bits.rd @[dec_decode_ctl.scala 394:15]
+    cam_raw[0].bits.tag <= _T_152.bits.tag @[dec_decode_ctl.scala 394:15]
+    cam_raw[0].bits.wb <= _T_152.bits.wb @[dec_decode_ctl.scala 394:15]
+    cam_raw[0].valid <= _T_152.valid @[dec_decode_ctl.scala 394:15]
+    node _T_164 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam_raw[0].bits.tag) @[dec_decode_ctl.scala 395:46]
+    node _T_165 = and(_T_164, cam_raw[0].valid) @[dec_decode_ctl.scala 395:71]
+    nonblock_load_write[0] <= _T_165 @[dec_decode_ctl.scala 395:28]
+    node _T_166 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[1].bits.tag) @[dec_decode_ctl.scala 368:66]
+    node _T_167 = and(io.dctl_busbuff.lsu_nonblock_load_inv_r, _T_166) @[dec_decode_ctl.scala 368:45]
+    node _T_168 = and(_T_167, cam[1].valid) @[dec_decode_ctl.scala 368:87]
+    cam_inv_reset_val[1] <= _T_168 @[dec_decode_ctl.scala 368:26]
+    node _T_169 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam[1].bits.tag) @[dec_decode_ctl.scala 369:67]
+    node _T_170 = and(cam_data_reset, _T_169) @[dec_decode_ctl.scala 369:45]
+    node _T_171 = and(_T_170, cam_raw[1].valid) @[dec_decode_ctl.scala 369:88]
+    cam_data_reset_val[1] <= _T_171 @[dec_decode_ctl.scala 369:27]
+    wire _T_172 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 370:28]
+    _T_172.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 370:28]
+    _T_172.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 370:28]
+    _T_172.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 370:28]
+    _T_172.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 370:28]
+    cam_in[1].bits.rd <= _T_172.bits.rd @[dec_decode_ctl.scala 370:14]
+    cam_in[1].bits.tag <= _T_172.bits.tag @[dec_decode_ctl.scala 370:14]
+    cam_in[1].bits.wb <= _T_172.bits.wb @[dec_decode_ctl.scala 370:14]
+    cam_in[1].valid <= _T_172.valid @[dec_decode_ctl.scala 370:14]
+    cam[1].bits.rd <= cam_raw[1].bits.rd @[dec_decode_ctl.scala 371:11]
+    cam[1].bits.tag <= cam_raw[1].bits.tag @[dec_decode_ctl.scala 371:11]
+    cam[1].bits.wb <= cam_raw[1].bits.wb @[dec_decode_ctl.scala 371:11]
+    cam[1].valid <= cam_raw[1].valid @[dec_decode_ctl.scala 371:11]
+    node _T_173 = bits(cam_data_reset_val[1], 0, 0) @[dec_decode_ctl.scala 373:32]
+    when _T_173 : @[dec_decode_ctl.scala 373:39]
+      cam[1].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 374:20]
+      skip @[dec_decode_ctl.scala 373:39]
+    node _T_174 = bits(cam_wen, 1, 1) @[dec_decode_ctl.scala 376:17]
+    node _T_175 = bits(_T_174, 0, 0) @[dec_decode_ctl.scala 376:21]
+    when _T_175 : @[dec_decode_ctl.scala 376:28]
+      cam_in[1].valid <= UInt<1>("h01") @[dec_decode_ctl.scala 377:27]
+      cam_in[1].bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 378:32]
+      cam_in[1].bits.tag <= cam_write_tag @[dec_decode_ctl.scala 379:32]
+      cam_in[1].bits.rd <= nonblock_load_rd @[dec_decode_ctl.scala 380:32]
+      skip @[dec_decode_ctl.scala 376:28]
+    else : @[dec_decode_ctl.scala 381:131]
+      node _T_176 = bits(cam_inv_reset_val[1], 0, 0) @[dec_decode_ctl.scala 381:37]
+      node _T_177 = bits(i0_wen_r, 0, 0) @[dec_decode_ctl.scala 381:57]
+      node _T_178 = eq(r_d_in.bits.i0rd, cam[1].bits.rd) @[dec_decode_ctl.scala 381:85]
+      node _T_179 = and(_T_177, _T_178) @[dec_decode_ctl.scala 381:64]
+      node _T_180 = bits(cam[1].bits.wb, 0, 0) @[dec_decode_ctl.scala 381:123]
+      node _T_181 = and(_T_179, _T_180) @[dec_decode_ctl.scala 381:105]
+      node _T_182 = or(_T_176, _T_181) @[dec_decode_ctl.scala 381:44]
+      when _T_182 : @[dec_decode_ctl.scala 381:131]
+        cam_in[1].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 382:23]
+        skip @[dec_decode_ctl.scala 381:131]
+      else : @[dec_decode_ctl.scala 383:16]
+        cam_in[1].bits.rd <= cam[1].bits.rd @[dec_decode_ctl.scala 384:22]
+        cam_in[1].bits.tag <= cam[1].bits.tag @[dec_decode_ctl.scala 384:22]
+        cam_in[1].bits.wb <= cam[1].bits.wb @[dec_decode_ctl.scala 384:22]
+        cam_in[1].valid <= cam[1].valid @[dec_decode_ctl.scala 384:22]
+        skip @[dec_decode_ctl.scala 383:16]
+    node _T_183 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[dec_decode_ctl.scala 386:37]
+    node _T_184 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[1].bits.tag) @[dec_decode_ctl.scala 386:92]
+    node _T_185 = and(_T_183, _T_184) @[dec_decode_ctl.scala 386:44]
+    node _T_186 = eq(cam[1].valid, UInt<1>("h01")) @[dec_decode_ctl.scala 386:128]
+    node _T_187 = and(_T_185, _T_186) @[dec_decode_ctl.scala 386:113]
+    when _T_187 : @[dec_decode_ctl.scala 386:135]
+      cam_in[1].bits.wb <= UInt<1>("h01") @[dec_decode_ctl.scala 387:25]
+      skip @[dec_decode_ctl.scala 386:135]
+    when io.dec_tlu_force_halt : @[dec_decode_ctl.scala 390:32]
+      cam_in[1].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 391:23]
+      skip @[dec_decode_ctl.scala 390:32]
     wire _T_188 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}
     _T_188.bits.rd <= cam_in[1].bits.rd
     _T_188.bits.tag <= cam_in[1].bits.tag
@@ -5823,74 +5823,74 @@ circuit dec :
     _T_188.bits.tag <= _T_199.bits.tag @[lib.scala 497:16]
     _T_188.bits.wb <= _T_199.bits.wb @[lib.scala 497:16]
     _T_188.valid <= _T_199.valid @[lib.scala 497:16]
-    cam_raw[1].bits.rd <= _T_188.bits.rd @[dec_decode_ctl.scala 392:15]
-    cam_raw[1].bits.tag <= _T_188.bits.tag @[dec_decode_ctl.scala 392:15]
-    cam_raw[1].bits.wb <= _T_188.bits.wb @[dec_decode_ctl.scala 392:15]
-    cam_raw[1].valid <= _T_188.valid @[dec_decode_ctl.scala 392:15]
-    node _T_200 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam_raw[1].bits.tag) @[dec_decode_ctl.scala 393:46]
-    node _T_201 = and(_T_200, cam_raw[1].valid) @[dec_decode_ctl.scala 393:71]
-    nonblock_load_write[1] <= _T_201 @[dec_decode_ctl.scala 393:28]
-    node _T_202 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[2].bits.tag) @[dec_decode_ctl.scala 366:66]
-    node _T_203 = and(io.dctl_busbuff.lsu_nonblock_load_inv_r, _T_202) @[dec_decode_ctl.scala 366:45]
-    node _T_204 = and(_T_203, cam[2].valid) @[dec_decode_ctl.scala 366:87]
-    cam_inv_reset_val[2] <= _T_204 @[dec_decode_ctl.scala 366:26]
-    node _T_205 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam[2].bits.tag) @[dec_decode_ctl.scala 367:67]
-    node _T_206 = and(cam_data_reset, _T_205) @[dec_decode_ctl.scala 367:45]
-    node _T_207 = and(_T_206, cam_raw[2].valid) @[dec_decode_ctl.scala 367:88]
-    cam_data_reset_val[2] <= _T_207 @[dec_decode_ctl.scala 367:27]
-    wire _T_208 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 368:28]
-    _T_208.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 368:28]
-    _T_208.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 368:28]
-    _T_208.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 368:28]
-    _T_208.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 368:28]
-    cam_in[2].bits.rd <= _T_208.bits.rd @[dec_decode_ctl.scala 368:14]
-    cam_in[2].bits.tag <= _T_208.bits.tag @[dec_decode_ctl.scala 368:14]
-    cam_in[2].bits.wb <= _T_208.bits.wb @[dec_decode_ctl.scala 368:14]
-    cam_in[2].valid <= _T_208.valid @[dec_decode_ctl.scala 368:14]
-    cam[2].bits.rd <= cam_raw[2].bits.rd @[dec_decode_ctl.scala 369:11]
-    cam[2].bits.tag <= cam_raw[2].bits.tag @[dec_decode_ctl.scala 369:11]
-    cam[2].bits.wb <= cam_raw[2].bits.wb @[dec_decode_ctl.scala 369:11]
-    cam[2].valid <= cam_raw[2].valid @[dec_decode_ctl.scala 369:11]
-    node _T_209 = bits(cam_data_reset_val[2], 0, 0) @[dec_decode_ctl.scala 371:32]
-    when _T_209 : @[dec_decode_ctl.scala 371:39]
-      cam[2].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 372:20]
-      skip @[dec_decode_ctl.scala 371:39]
-    node _T_210 = bits(cam_wen, 2, 2) @[dec_decode_ctl.scala 374:17]
-    node _T_211 = bits(_T_210, 0, 0) @[dec_decode_ctl.scala 374:21]
-    when _T_211 : @[dec_decode_ctl.scala 374:28]
-      cam_in[2].valid <= UInt<1>("h01") @[dec_decode_ctl.scala 375:27]
-      cam_in[2].bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 376:32]
-      cam_in[2].bits.tag <= cam_write_tag @[dec_decode_ctl.scala 377:32]
-      cam_in[2].bits.rd <= nonblock_load_rd @[dec_decode_ctl.scala 378:32]
-      skip @[dec_decode_ctl.scala 374:28]
-    else : @[dec_decode_ctl.scala 379:131]
-      node _T_212 = bits(cam_inv_reset_val[2], 0, 0) @[dec_decode_ctl.scala 379:37]
-      node _T_213 = bits(i0_wen_r, 0, 0) @[dec_decode_ctl.scala 379:57]
-      node _T_214 = eq(r_d_in.bits.i0rd, cam[2].bits.rd) @[dec_decode_ctl.scala 379:85]
-      node _T_215 = and(_T_213, _T_214) @[dec_decode_ctl.scala 379:64]
-      node _T_216 = bits(cam[2].bits.wb, 0, 0) @[dec_decode_ctl.scala 379:123]
-      node _T_217 = and(_T_215, _T_216) @[dec_decode_ctl.scala 379:105]
-      node _T_218 = or(_T_212, _T_217) @[dec_decode_ctl.scala 379:44]
-      when _T_218 : @[dec_decode_ctl.scala 379:131]
-        cam_in[2].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 380:23]
-        skip @[dec_decode_ctl.scala 379:131]
-      else : @[dec_decode_ctl.scala 381:16]
-        cam_in[2].bits.rd <= cam[2].bits.rd @[dec_decode_ctl.scala 382:22]
-        cam_in[2].bits.tag <= cam[2].bits.tag @[dec_decode_ctl.scala 382:22]
-        cam_in[2].bits.wb <= cam[2].bits.wb @[dec_decode_ctl.scala 382:22]
-        cam_in[2].valid <= cam[2].valid @[dec_decode_ctl.scala 382:22]
-        skip @[dec_decode_ctl.scala 381:16]
-    node _T_219 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[dec_decode_ctl.scala 384:37]
-    node _T_220 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[2].bits.tag) @[dec_decode_ctl.scala 384:92]
-    node _T_221 = and(_T_219, _T_220) @[dec_decode_ctl.scala 384:44]
-    node _T_222 = eq(cam[2].valid, UInt<1>("h01")) @[dec_decode_ctl.scala 384:128]
-    node _T_223 = and(_T_221, _T_222) @[dec_decode_ctl.scala 384:113]
-    when _T_223 : @[dec_decode_ctl.scala 384:135]
-      cam_in[2].bits.wb <= UInt<1>("h01") @[dec_decode_ctl.scala 385:25]
-      skip @[dec_decode_ctl.scala 384:135]
-    when io.dec_tlu_force_halt : @[dec_decode_ctl.scala 388:32]
-      cam_in[2].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 389:23]
-      skip @[dec_decode_ctl.scala 388:32]
+    cam_raw[1].bits.rd <= _T_188.bits.rd @[dec_decode_ctl.scala 394:15]
+    cam_raw[1].bits.tag <= _T_188.bits.tag @[dec_decode_ctl.scala 394:15]
+    cam_raw[1].bits.wb <= _T_188.bits.wb @[dec_decode_ctl.scala 394:15]
+    cam_raw[1].valid <= _T_188.valid @[dec_decode_ctl.scala 394:15]
+    node _T_200 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam_raw[1].bits.tag) @[dec_decode_ctl.scala 395:46]
+    node _T_201 = and(_T_200, cam_raw[1].valid) @[dec_decode_ctl.scala 395:71]
+    nonblock_load_write[1] <= _T_201 @[dec_decode_ctl.scala 395:28]
+    node _T_202 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[2].bits.tag) @[dec_decode_ctl.scala 368:66]
+    node _T_203 = and(io.dctl_busbuff.lsu_nonblock_load_inv_r, _T_202) @[dec_decode_ctl.scala 368:45]
+    node _T_204 = and(_T_203, cam[2].valid) @[dec_decode_ctl.scala 368:87]
+    cam_inv_reset_val[2] <= _T_204 @[dec_decode_ctl.scala 368:26]
+    node _T_205 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam[2].bits.tag) @[dec_decode_ctl.scala 369:67]
+    node _T_206 = and(cam_data_reset, _T_205) @[dec_decode_ctl.scala 369:45]
+    node _T_207 = and(_T_206, cam_raw[2].valid) @[dec_decode_ctl.scala 369:88]
+    cam_data_reset_val[2] <= _T_207 @[dec_decode_ctl.scala 369:27]
+    wire _T_208 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 370:28]
+    _T_208.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 370:28]
+    _T_208.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 370:28]
+    _T_208.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 370:28]
+    _T_208.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 370:28]
+    cam_in[2].bits.rd <= _T_208.bits.rd @[dec_decode_ctl.scala 370:14]
+    cam_in[2].bits.tag <= _T_208.bits.tag @[dec_decode_ctl.scala 370:14]
+    cam_in[2].bits.wb <= _T_208.bits.wb @[dec_decode_ctl.scala 370:14]
+    cam_in[2].valid <= _T_208.valid @[dec_decode_ctl.scala 370:14]
+    cam[2].bits.rd <= cam_raw[2].bits.rd @[dec_decode_ctl.scala 371:11]
+    cam[2].bits.tag <= cam_raw[2].bits.tag @[dec_decode_ctl.scala 371:11]
+    cam[2].bits.wb <= cam_raw[2].bits.wb @[dec_decode_ctl.scala 371:11]
+    cam[2].valid <= cam_raw[2].valid @[dec_decode_ctl.scala 371:11]
+    node _T_209 = bits(cam_data_reset_val[2], 0, 0) @[dec_decode_ctl.scala 373:32]
+    when _T_209 : @[dec_decode_ctl.scala 373:39]
+      cam[2].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 374:20]
+      skip @[dec_decode_ctl.scala 373:39]
+    node _T_210 = bits(cam_wen, 2, 2) @[dec_decode_ctl.scala 376:17]
+    node _T_211 = bits(_T_210, 0, 0) @[dec_decode_ctl.scala 376:21]
+    when _T_211 : @[dec_decode_ctl.scala 376:28]
+      cam_in[2].valid <= UInt<1>("h01") @[dec_decode_ctl.scala 377:27]
+      cam_in[2].bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 378:32]
+      cam_in[2].bits.tag <= cam_write_tag @[dec_decode_ctl.scala 379:32]
+      cam_in[2].bits.rd <= nonblock_load_rd @[dec_decode_ctl.scala 380:32]
+      skip @[dec_decode_ctl.scala 376:28]
+    else : @[dec_decode_ctl.scala 381:131]
+      node _T_212 = bits(cam_inv_reset_val[2], 0, 0) @[dec_decode_ctl.scala 381:37]
+      node _T_213 = bits(i0_wen_r, 0, 0) @[dec_decode_ctl.scala 381:57]
+      node _T_214 = eq(r_d_in.bits.i0rd, cam[2].bits.rd) @[dec_decode_ctl.scala 381:85]
+      node _T_215 = and(_T_213, _T_214) @[dec_decode_ctl.scala 381:64]
+      node _T_216 = bits(cam[2].bits.wb, 0, 0) @[dec_decode_ctl.scala 381:123]
+      node _T_217 = and(_T_215, _T_216) @[dec_decode_ctl.scala 381:105]
+      node _T_218 = or(_T_212, _T_217) @[dec_decode_ctl.scala 381:44]
+      when _T_218 : @[dec_decode_ctl.scala 381:131]
+        cam_in[2].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 382:23]
+        skip @[dec_decode_ctl.scala 381:131]
+      else : @[dec_decode_ctl.scala 383:16]
+        cam_in[2].bits.rd <= cam[2].bits.rd @[dec_decode_ctl.scala 384:22]
+        cam_in[2].bits.tag <= cam[2].bits.tag @[dec_decode_ctl.scala 384:22]
+        cam_in[2].bits.wb <= cam[2].bits.wb @[dec_decode_ctl.scala 384:22]
+        cam_in[2].valid <= cam[2].valid @[dec_decode_ctl.scala 384:22]
+        skip @[dec_decode_ctl.scala 383:16]
+    node _T_219 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[dec_decode_ctl.scala 386:37]
+    node _T_220 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[2].bits.tag) @[dec_decode_ctl.scala 386:92]
+    node _T_221 = and(_T_219, _T_220) @[dec_decode_ctl.scala 386:44]
+    node _T_222 = eq(cam[2].valid, UInt<1>("h01")) @[dec_decode_ctl.scala 386:128]
+    node _T_223 = and(_T_221, _T_222) @[dec_decode_ctl.scala 386:113]
+    when _T_223 : @[dec_decode_ctl.scala 386:135]
+      cam_in[2].bits.wb <= UInt<1>("h01") @[dec_decode_ctl.scala 387:25]
+      skip @[dec_decode_ctl.scala 386:135]
+    when io.dec_tlu_force_halt : @[dec_decode_ctl.scala 390:32]
+      cam_in[2].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 391:23]
+      skip @[dec_decode_ctl.scala 390:32]
     wire _T_224 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}
     _T_224.bits.rd <= cam_in[2].bits.rd
     _T_224.bits.tag <= cam_in[2].bits.tag
@@ -5921,74 +5921,74 @@ circuit dec :
     _T_224.bits.tag <= _T_235.bits.tag @[lib.scala 497:16]
     _T_224.bits.wb <= _T_235.bits.wb @[lib.scala 497:16]
     _T_224.valid <= _T_235.valid @[lib.scala 497:16]
-    cam_raw[2].bits.rd <= _T_224.bits.rd @[dec_decode_ctl.scala 392:15]
-    cam_raw[2].bits.tag <= _T_224.bits.tag @[dec_decode_ctl.scala 392:15]
-    cam_raw[2].bits.wb <= _T_224.bits.wb @[dec_decode_ctl.scala 392:15]
-    cam_raw[2].valid <= _T_224.valid @[dec_decode_ctl.scala 392:15]
-    node _T_236 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam_raw[2].bits.tag) @[dec_decode_ctl.scala 393:46]
-    node _T_237 = and(_T_236, cam_raw[2].valid) @[dec_decode_ctl.scala 393:71]
-    nonblock_load_write[2] <= _T_237 @[dec_decode_ctl.scala 393:28]
-    node _T_238 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[3].bits.tag) @[dec_decode_ctl.scala 366:66]
-    node _T_239 = and(io.dctl_busbuff.lsu_nonblock_load_inv_r, _T_238) @[dec_decode_ctl.scala 366:45]
-    node _T_240 = and(_T_239, cam[3].valid) @[dec_decode_ctl.scala 366:87]
-    cam_inv_reset_val[3] <= _T_240 @[dec_decode_ctl.scala 366:26]
-    node _T_241 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam[3].bits.tag) @[dec_decode_ctl.scala 367:67]
-    node _T_242 = and(cam_data_reset, _T_241) @[dec_decode_ctl.scala 367:45]
-    node _T_243 = and(_T_242, cam_raw[3].valid) @[dec_decode_ctl.scala 367:88]
-    cam_data_reset_val[3] <= _T_243 @[dec_decode_ctl.scala 367:27]
-    wire _T_244 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 368:28]
-    _T_244.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 368:28]
-    _T_244.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 368:28]
-    _T_244.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 368:28]
-    _T_244.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 368:28]
-    cam_in[3].bits.rd <= _T_244.bits.rd @[dec_decode_ctl.scala 368:14]
-    cam_in[3].bits.tag <= _T_244.bits.tag @[dec_decode_ctl.scala 368:14]
-    cam_in[3].bits.wb <= _T_244.bits.wb @[dec_decode_ctl.scala 368:14]
-    cam_in[3].valid <= _T_244.valid @[dec_decode_ctl.scala 368:14]
-    cam[3].bits.rd <= cam_raw[3].bits.rd @[dec_decode_ctl.scala 369:11]
-    cam[3].bits.tag <= cam_raw[3].bits.tag @[dec_decode_ctl.scala 369:11]
-    cam[3].bits.wb <= cam_raw[3].bits.wb @[dec_decode_ctl.scala 369:11]
-    cam[3].valid <= cam_raw[3].valid @[dec_decode_ctl.scala 369:11]
-    node _T_245 = bits(cam_data_reset_val[3], 0, 0) @[dec_decode_ctl.scala 371:32]
-    when _T_245 : @[dec_decode_ctl.scala 371:39]
-      cam[3].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 372:20]
-      skip @[dec_decode_ctl.scala 371:39]
-    node _T_246 = bits(cam_wen, 3, 3) @[dec_decode_ctl.scala 374:17]
-    node _T_247 = bits(_T_246, 0, 0) @[dec_decode_ctl.scala 374:21]
-    when _T_247 : @[dec_decode_ctl.scala 374:28]
-      cam_in[3].valid <= UInt<1>("h01") @[dec_decode_ctl.scala 375:27]
-      cam_in[3].bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 376:32]
-      cam_in[3].bits.tag <= cam_write_tag @[dec_decode_ctl.scala 377:32]
-      cam_in[3].bits.rd <= nonblock_load_rd @[dec_decode_ctl.scala 378:32]
-      skip @[dec_decode_ctl.scala 374:28]
-    else : @[dec_decode_ctl.scala 379:131]
-      node _T_248 = bits(cam_inv_reset_val[3], 0, 0) @[dec_decode_ctl.scala 379:37]
-      node _T_249 = bits(i0_wen_r, 0, 0) @[dec_decode_ctl.scala 379:57]
-      node _T_250 = eq(r_d_in.bits.i0rd, cam[3].bits.rd) @[dec_decode_ctl.scala 379:85]
-      node _T_251 = and(_T_249, _T_250) @[dec_decode_ctl.scala 379:64]
-      node _T_252 = bits(cam[3].bits.wb, 0, 0) @[dec_decode_ctl.scala 379:123]
-      node _T_253 = and(_T_251, _T_252) @[dec_decode_ctl.scala 379:105]
-      node _T_254 = or(_T_248, _T_253) @[dec_decode_ctl.scala 379:44]
-      when _T_254 : @[dec_decode_ctl.scala 379:131]
-        cam_in[3].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 380:23]
-        skip @[dec_decode_ctl.scala 379:131]
-      else : @[dec_decode_ctl.scala 381:16]
-        cam_in[3].bits.rd <= cam[3].bits.rd @[dec_decode_ctl.scala 382:22]
-        cam_in[3].bits.tag <= cam[3].bits.tag @[dec_decode_ctl.scala 382:22]
-        cam_in[3].bits.wb <= cam[3].bits.wb @[dec_decode_ctl.scala 382:22]
-        cam_in[3].valid <= cam[3].valid @[dec_decode_ctl.scala 382:22]
-        skip @[dec_decode_ctl.scala 381:16]
-    node _T_255 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[dec_decode_ctl.scala 384:37]
-    node _T_256 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[3].bits.tag) @[dec_decode_ctl.scala 384:92]
-    node _T_257 = and(_T_255, _T_256) @[dec_decode_ctl.scala 384:44]
-    node _T_258 = eq(cam[3].valid, UInt<1>("h01")) @[dec_decode_ctl.scala 384:128]
-    node _T_259 = and(_T_257, _T_258) @[dec_decode_ctl.scala 384:113]
-    when _T_259 : @[dec_decode_ctl.scala 384:135]
-      cam_in[3].bits.wb <= UInt<1>("h01") @[dec_decode_ctl.scala 385:25]
-      skip @[dec_decode_ctl.scala 384:135]
-    when io.dec_tlu_force_halt : @[dec_decode_ctl.scala 388:32]
-      cam_in[3].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 389:23]
-      skip @[dec_decode_ctl.scala 388:32]
+    cam_raw[2].bits.rd <= _T_224.bits.rd @[dec_decode_ctl.scala 394:15]
+    cam_raw[2].bits.tag <= _T_224.bits.tag @[dec_decode_ctl.scala 394:15]
+    cam_raw[2].bits.wb <= _T_224.bits.wb @[dec_decode_ctl.scala 394:15]
+    cam_raw[2].valid <= _T_224.valid @[dec_decode_ctl.scala 394:15]
+    node _T_236 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam_raw[2].bits.tag) @[dec_decode_ctl.scala 395:46]
+    node _T_237 = and(_T_236, cam_raw[2].valid) @[dec_decode_ctl.scala 395:71]
+    nonblock_load_write[2] <= _T_237 @[dec_decode_ctl.scala 395:28]
+    node _T_238 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[3].bits.tag) @[dec_decode_ctl.scala 368:66]
+    node _T_239 = and(io.dctl_busbuff.lsu_nonblock_load_inv_r, _T_238) @[dec_decode_ctl.scala 368:45]
+    node _T_240 = and(_T_239, cam[3].valid) @[dec_decode_ctl.scala 368:87]
+    cam_inv_reset_val[3] <= _T_240 @[dec_decode_ctl.scala 368:26]
+    node _T_241 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam[3].bits.tag) @[dec_decode_ctl.scala 369:67]
+    node _T_242 = and(cam_data_reset, _T_241) @[dec_decode_ctl.scala 369:45]
+    node _T_243 = and(_T_242, cam_raw[3].valid) @[dec_decode_ctl.scala 369:88]
+    cam_data_reset_val[3] <= _T_243 @[dec_decode_ctl.scala 369:27]
+    wire _T_244 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 370:28]
+    _T_244.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 370:28]
+    _T_244.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 370:28]
+    _T_244.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 370:28]
+    _T_244.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 370:28]
+    cam_in[3].bits.rd <= _T_244.bits.rd @[dec_decode_ctl.scala 370:14]
+    cam_in[3].bits.tag <= _T_244.bits.tag @[dec_decode_ctl.scala 370:14]
+    cam_in[3].bits.wb <= _T_244.bits.wb @[dec_decode_ctl.scala 370:14]
+    cam_in[3].valid <= _T_244.valid @[dec_decode_ctl.scala 370:14]
+    cam[3].bits.rd <= cam_raw[3].bits.rd @[dec_decode_ctl.scala 371:11]
+    cam[3].bits.tag <= cam_raw[3].bits.tag @[dec_decode_ctl.scala 371:11]
+    cam[3].bits.wb <= cam_raw[3].bits.wb @[dec_decode_ctl.scala 371:11]
+    cam[3].valid <= cam_raw[3].valid @[dec_decode_ctl.scala 371:11]
+    node _T_245 = bits(cam_data_reset_val[3], 0, 0) @[dec_decode_ctl.scala 373:32]
+    when _T_245 : @[dec_decode_ctl.scala 373:39]
+      cam[3].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 374:20]
+      skip @[dec_decode_ctl.scala 373:39]
+    node _T_246 = bits(cam_wen, 3, 3) @[dec_decode_ctl.scala 376:17]
+    node _T_247 = bits(_T_246, 0, 0) @[dec_decode_ctl.scala 376:21]
+    when _T_247 : @[dec_decode_ctl.scala 376:28]
+      cam_in[3].valid <= UInt<1>("h01") @[dec_decode_ctl.scala 377:27]
+      cam_in[3].bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 378:32]
+      cam_in[3].bits.tag <= cam_write_tag @[dec_decode_ctl.scala 379:32]
+      cam_in[3].bits.rd <= nonblock_load_rd @[dec_decode_ctl.scala 380:32]
+      skip @[dec_decode_ctl.scala 376:28]
+    else : @[dec_decode_ctl.scala 381:131]
+      node _T_248 = bits(cam_inv_reset_val[3], 0, 0) @[dec_decode_ctl.scala 381:37]
+      node _T_249 = bits(i0_wen_r, 0, 0) @[dec_decode_ctl.scala 381:57]
+      node _T_250 = eq(r_d_in.bits.i0rd, cam[3].bits.rd) @[dec_decode_ctl.scala 381:85]
+      node _T_251 = and(_T_249, _T_250) @[dec_decode_ctl.scala 381:64]
+      node _T_252 = bits(cam[3].bits.wb, 0, 0) @[dec_decode_ctl.scala 381:123]
+      node _T_253 = and(_T_251, _T_252) @[dec_decode_ctl.scala 381:105]
+      node _T_254 = or(_T_248, _T_253) @[dec_decode_ctl.scala 381:44]
+      when _T_254 : @[dec_decode_ctl.scala 381:131]
+        cam_in[3].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 382:23]
+        skip @[dec_decode_ctl.scala 381:131]
+      else : @[dec_decode_ctl.scala 383:16]
+        cam_in[3].bits.rd <= cam[3].bits.rd @[dec_decode_ctl.scala 384:22]
+        cam_in[3].bits.tag <= cam[3].bits.tag @[dec_decode_ctl.scala 384:22]
+        cam_in[3].bits.wb <= cam[3].bits.wb @[dec_decode_ctl.scala 384:22]
+        cam_in[3].valid <= cam[3].valid @[dec_decode_ctl.scala 384:22]
+        skip @[dec_decode_ctl.scala 383:16]
+    node _T_255 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[dec_decode_ctl.scala 386:37]
+    node _T_256 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[3].bits.tag) @[dec_decode_ctl.scala 386:92]
+    node _T_257 = and(_T_255, _T_256) @[dec_decode_ctl.scala 386:44]
+    node _T_258 = eq(cam[3].valid, UInt<1>("h01")) @[dec_decode_ctl.scala 386:128]
+    node _T_259 = and(_T_257, _T_258) @[dec_decode_ctl.scala 386:113]
+    when _T_259 : @[dec_decode_ctl.scala 386:135]
+      cam_in[3].bits.wb <= UInt<1>("h01") @[dec_decode_ctl.scala 387:25]
+      skip @[dec_decode_ctl.scala 386:135]
+    when io.dec_tlu_force_halt : @[dec_decode_ctl.scala 390:32]
+      cam_in[3].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 391:23]
+      skip @[dec_decode_ctl.scala 390:32]
     wire _T_260 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}
     _T_260.bits.rd <= cam_in[3].bits.rd
     _T_260.bits.tag <= cam_in[3].bits.tag
@@ -6019,100 +6019,100 @@ circuit dec :
     _T_260.bits.tag <= _T_271.bits.tag @[lib.scala 497:16]
     _T_260.bits.wb <= _T_271.bits.wb @[lib.scala 497:16]
     _T_260.valid <= _T_271.valid @[lib.scala 497:16]
-    cam_raw[3].bits.rd <= _T_260.bits.rd @[dec_decode_ctl.scala 392:15]
-    cam_raw[3].bits.tag <= _T_260.bits.tag @[dec_decode_ctl.scala 392:15]
-    cam_raw[3].bits.wb <= _T_260.bits.wb @[dec_decode_ctl.scala 392:15]
-    cam_raw[3].valid <= _T_260.valid @[dec_decode_ctl.scala 392:15]
-    node _T_272 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam_raw[3].bits.tag) @[dec_decode_ctl.scala 393:46]
-    node _T_273 = and(_T_272, cam_raw[3].valid) @[dec_decode_ctl.scala 393:71]
-    nonblock_load_write[3] <= _T_273 @[dec_decode_ctl.scala 393:28]
-    io.dec_nonblock_load_waddr <= UInt<5>("h00") @[dec_decode_ctl.scala 396:29]
-    node _T_274 = eq(r_d_in.bits.i0rd, io.dec_nonblock_load_waddr) @[dec_decode_ctl.scala 398:49]
-    node nonblock_load_cancel = and(_T_274, i0_wen_r) @[dec_decode_ctl.scala 398:81]
-    node _T_275 = or(nonblock_load_write[0], nonblock_load_write[1]) @[dec_decode_ctl.scala 399:108]
-    node _T_276 = or(_T_275, nonblock_load_write[2]) @[dec_decode_ctl.scala 399:108]
-    node _T_277 = or(_T_276, nonblock_load_write[3]) @[dec_decode_ctl.scala 399:108]
-    node _T_278 = bits(_T_277, 0, 0) @[dec_decode_ctl.scala 399:112]
-    node _T_279 = and(io.dctl_busbuff.lsu_nonblock_load_data_valid, _T_278) @[dec_decode_ctl.scala 399:77]
-    node _T_280 = eq(nonblock_load_cancel, UInt<1>("h00")) @[dec_decode_ctl.scala 399:122]
-    node _T_281 = and(_T_279, _T_280) @[dec_decode_ctl.scala 399:119]
-    io.dec_nonblock_load_wen <= _T_281 @[dec_decode_ctl.scala 399:28]
-    node _T_282 = eq(nonblock_load_rd, i0r.rs1) @[dec_decode_ctl.scala 400:54]
-    node _T_283 = and(_T_282, io.dctl_busbuff.lsu_nonblock_load_valid_m) @[dec_decode_ctl.scala 400:66]
-    node _T_284 = and(_T_283, io.decode_exu.dec_i0_rs1_en_d) @[dec_decode_ctl.scala 400:110]
-    node _T_285 = eq(nonblock_load_rd, i0r.rs2) @[dec_decode_ctl.scala 400:161]
-    node _T_286 = and(_T_285, io.dctl_busbuff.lsu_nonblock_load_valid_m) @[dec_decode_ctl.scala 400:173]
-    node _T_287 = and(_T_286, io.decode_exu.dec_i0_rs2_en_d) @[dec_decode_ctl.scala 400:217]
-    node i0_nonblock_boundary_stall = or(_T_284, _T_287) @[dec_decode_ctl.scala 400:142]
-    i0_nonblock_load_stall <= i0_nonblock_boundary_stall @[dec_decode_ctl.scala 402:26]
+    cam_raw[3].bits.rd <= _T_260.bits.rd @[dec_decode_ctl.scala 394:15]
+    cam_raw[3].bits.tag <= _T_260.bits.tag @[dec_decode_ctl.scala 394:15]
+    cam_raw[3].bits.wb <= _T_260.bits.wb @[dec_decode_ctl.scala 394:15]
+    cam_raw[3].valid <= _T_260.valid @[dec_decode_ctl.scala 394:15]
+    node _T_272 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam_raw[3].bits.tag) @[dec_decode_ctl.scala 395:46]
+    node _T_273 = and(_T_272, cam_raw[3].valid) @[dec_decode_ctl.scala 395:71]
+    nonblock_load_write[3] <= _T_273 @[dec_decode_ctl.scala 395:28]
+    io.dec_nonblock_load_waddr <= UInt<5>("h00") @[dec_decode_ctl.scala 398:29]
+    node _T_274 = eq(r_d_in.bits.i0rd, io.dec_nonblock_load_waddr) @[dec_decode_ctl.scala 400:49]
+    node nonblock_load_cancel = and(_T_274, i0_wen_r) @[dec_decode_ctl.scala 400:81]
+    node _T_275 = or(nonblock_load_write[0], nonblock_load_write[1]) @[dec_decode_ctl.scala 401:108]
+    node _T_276 = or(_T_275, nonblock_load_write[2]) @[dec_decode_ctl.scala 401:108]
+    node _T_277 = or(_T_276, nonblock_load_write[3]) @[dec_decode_ctl.scala 401:108]
+    node _T_278 = bits(_T_277, 0, 0) @[dec_decode_ctl.scala 401:112]
+    node _T_279 = and(io.dctl_busbuff.lsu_nonblock_load_data_valid, _T_278) @[dec_decode_ctl.scala 401:77]
+    node _T_280 = eq(nonblock_load_cancel, UInt<1>("h00")) @[dec_decode_ctl.scala 401:122]
+    node _T_281 = and(_T_279, _T_280) @[dec_decode_ctl.scala 401:119]
+    io.dec_nonblock_load_wen <= _T_281 @[dec_decode_ctl.scala 401:28]
+    node _T_282 = eq(nonblock_load_rd, i0r.rs1) @[dec_decode_ctl.scala 402:54]
+    node _T_283 = and(_T_282, io.dctl_busbuff.lsu_nonblock_load_valid_m) @[dec_decode_ctl.scala 402:66]
+    node _T_284 = and(_T_283, io.decode_exu.dec_i0_rs1_en_d) @[dec_decode_ctl.scala 402:110]
+    node _T_285 = eq(nonblock_load_rd, i0r.rs2) @[dec_decode_ctl.scala 402:161]
+    node _T_286 = and(_T_285, io.dctl_busbuff.lsu_nonblock_load_valid_m) @[dec_decode_ctl.scala 402:173]
+    node _T_287 = and(_T_286, io.decode_exu.dec_i0_rs2_en_d) @[dec_decode_ctl.scala 402:217]
+    node i0_nonblock_boundary_stall = or(_T_284, _T_287) @[dec_decode_ctl.scala 402:142]
+    i0_nonblock_load_stall <= i0_nonblock_boundary_stall @[dec_decode_ctl.scala 404:26]
     node _T_288 = bits(nonblock_load_write[0], 0, 0) @[Bitwise.scala 72:15]
     node _T_289 = mux(_T_288, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12]
-    node _T_290 = and(_T_289, cam[0].bits.rd) @[dec_decode_ctl.scala 404:88]
-    node _T_291 = and(io.decode_exu.dec_i0_rs1_en_d, cam[0].valid) @[dec_decode_ctl.scala 404:137]
-    node _T_292 = eq(cam[0].bits.rd, i0r.rs1) @[dec_decode_ctl.scala 404:170]
-    node _T_293 = and(_T_291, _T_292) @[dec_decode_ctl.scala 404:152]
-    node _T_294 = and(io.decode_exu.dec_i0_rs2_en_d, cam[0].valid) @[dec_decode_ctl.scala 404:214]
-    node _T_295 = eq(cam[0].bits.rd, i0r.rs2) @[dec_decode_ctl.scala 404:247]
-    node _T_296 = and(_T_294, _T_295) @[dec_decode_ctl.scala 404:229]
+    node _T_290 = and(_T_289, cam[0].bits.rd) @[dec_decode_ctl.scala 406:88]
+    node _T_291 = and(io.decode_exu.dec_i0_rs1_en_d, cam[0].valid) @[dec_decode_ctl.scala 406:137]
+    node _T_292 = eq(cam[0].bits.rd, i0r.rs1) @[dec_decode_ctl.scala 406:170]
+    node _T_293 = and(_T_291, _T_292) @[dec_decode_ctl.scala 406:152]
+    node _T_294 = and(io.decode_exu.dec_i0_rs2_en_d, cam[0].valid) @[dec_decode_ctl.scala 406:214]
+    node _T_295 = eq(cam[0].bits.rd, i0r.rs2) @[dec_decode_ctl.scala 406:247]
+    node _T_296 = and(_T_294, _T_295) @[dec_decode_ctl.scala 406:229]
     node _T_297 = bits(nonblock_load_write[1], 0, 0) @[Bitwise.scala 72:15]
     node _T_298 = mux(_T_297, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12]
-    node _T_299 = and(_T_298, cam[1].bits.rd) @[dec_decode_ctl.scala 404:88]
-    node _T_300 = and(io.decode_exu.dec_i0_rs1_en_d, cam[1].valid) @[dec_decode_ctl.scala 404:137]
-    node _T_301 = eq(cam[1].bits.rd, i0r.rs1) @[dec_decode_ctl.scala 404:170]
-    node _T_302 = and(_T_300, _T_301) @[dec_decode_ctl.scala 404:152]
-    node _T_303 = and(io.decode_exu.dec_i0_rs2_en_d, cam[1].valid) @[dec_decode_ctl.scala 404:214]
-    node _T_304 = eq(cam[1].bits.rd, i0r.rs2) @[dec_decode_ctl.scala 404:247]
-    node _T_305 = and(_T_303, _T_304) @[dec_decode_ctl.scala 404:229]
+    node _T_299 = and(_T_298, cam[1].bits.rd) @[dec_decode_ctl.scala 406:88]
+    node _T_300 = and(io.decode_exu.dec_i0_rs1_en_d, cam[1].valid) @[dec_decode_ctl.scala 406:137]
+    node _T_301 = eq(cam[1].bits.rd, i0r.rs1) @[dec_decode_ctl.scala 406:170]
+    node _T_302 = and(_T_300, _T_301) @[dec_decode_ctl.scala 406:152]
+    node _T_303 = and(io.decode_exu.dec_i0_rs2_en_d, cam[1].valid) @[dec_decode_ctl.scala 406:214]
+    node _T_304 = eq(cam[1].bits.rd, i0r.rs2) @[dec_decode_ctl.scala 406:247]
+    node _T_305 = and(_T_303, _T_304) @[dec_decode_ctl.scala 406:229]
     node _T_306 = bits(nonblock_load_write[2], 0, 0) @[Bitwise.scala 72:15]
     node _T_307 = mux(_T_306, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12]
-    node _T_308 = and(_T_307, cam[2].bits.rd) @[dec_decode_ctl.scala 404:88]
-    node _T_309 = and(io.decode_exu.dec_i0_rs1_en_d, cam[2].valid) @[dec_decode_ctl.scala 404:137]
-    node _T_310 = eq(cam[2].bits.rd, i0r.rs1) @[dec_decode_ctl.scala 404:170]
-    node _T_311 = and(_T_309, _T_310) @[dec_decode_ctl.scala 404:152]
-    node _T_312 = and(io.decode_exu.dec_i0_rs2_en_d, cam[2].valid) @[dec_decode_ctl.scala 404:214]
-    node _T_313 = eq(cam[2].bits.rd, i0r.rs2) @[dec_decode_ctl.scala 404:247]
-    node _T_314 = and(_T_312, _T_313) @[dec_decode_ctl.scala 404:229]
+    node _T_308 = and(_T_307, cam[2].bits.rd) @[dec_decode_ctl.scala 406:88]
+    node _T_309 = and(io.decode_exu.dec_i0_rs1_en_d, cam[2].valid) @[dec_decode_ctl.scala 406:137]
+    node _T_310 = eq(cam[2].bits.rd, i0r.rs1) @[dec_decode_ctl.scala 406:170]
+    node _T_311 = and(_T_309, _T_310) @[dec_decode_ctl.scala 406:152]
+    node _T_312 = and(io.decode_exu.dec_i0_rs2_en_d, cam[2].valid) @[dec_decode_ctl.scala 406:214]
+    node _T_313 = eq(cam[2].bits.rd, i0r.rs2) @[dec_decode_ctl.scala 406:247]
+    node _T_314 = and(_T_312, _T_313) @[dec_decode_ctl.scala 406:229]
     node _T_315 = bits(nonblock_load_write[3], 0, 0) @[Bitwise.scala 72:15]
     node _T_316 = mux(_T_315, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12]
-    node _T_317 = and(_T_316, cam[3].bits.rd) @[dec_decode_ctl.scala 404:88]
-    node _T_318 = and(io.decode_exu.dec_i0_rs1_en_d, cam[3].valid) @[dec_decode_ctl.scala 404:137]
-    node _T_319 = eq(cam[3].bits.rd, i0r.rs1) @[dec_decode_ctl.scala 404:170]
-    node _T_320 = and(_T_318, _T_319) @[dec_decode_ctl.scala 404:152]
-    node _T_321 = and(io.decode_exu.dec_i0_rs2_en_d, cam[3].valid) @[dec_decode_ctl.scala 404:214]
-    node _T_322 = eq(cam[3].bits.rd, i0r.rs2) @[dec_decode_ctl.scala 404:247]
-    node _T_323 = and(_T_321, _T_322) @[dec_decode_ctl.scala 404:229]
-    node _T_324 = or(_T_290, _T_299) @[dec_decode_ctl.scala 405:69]
-    node _T_325 = or(_T_324, _T_308) @[dec_decode_ctl.scala 405:69]
-    node waddr = or(_T_325, _T_317) @[dec_decode_ctl.scala 405:69]
-    node _T_326 = or(_T_293, _T_302) @[dec_decode_ctl.scala 405:102]
-    node _T_327 = or(_T_326, _T_311) @[dec_decode_ctl.scala 405:102]
-    node ld_stall_1 = or(_T_327, _T_320) @[dec_decode_ctl.scala 405:102]
-    node _T_328 = or(_T_296, _T_305) @[dec_decode_ctl.scala 405:134]
-    node _T_329 = or(_T_328, _T_314) @[dec_decode_ctl.scala 405:134]
-    node ld_stall_2 = or(_T_329, _T_323) @[dec_decode_ctl.scala 405:134]
-    io.dec_nonblock_load_waddr <= waddr @[dec_decode_ctl.scala 406:29]
-    node _T_330 = or(ld_stall_1, ld_stall_2) @[dec_decode_ctl.scala 407:38]
-    node _T_331 = or(_T_330, i0_nonblock_boundary_stall) @[dec_decode_ctl.scala 407:51]
-    i0_nonblock_load_stall <= _T_331 @[dec_decode_ctl.scala 407:25]
-    node _T_332 = eq(i0_predict_br, UInt<1>("h00")) @[dec_decode_ctl.scala 416:34]
-    node i0_br_unpred = and(i0_dp.jal, _T_332) @[dec_decode_ctl.scala 416:32]
+    node _T_317 = and(_T_316, cam[3].bits.rd) @[dec_decode_ctl.scala 406:88]
+    node _T_318 = and(io.decode_exu.dec_i0_rs1_en_d, cam[3].valid) @[dec_decode_ctl.scala 406:137]
+    node _T_319 = eq(cam[3].bits.rd, i0r.rs1) @[dec_decode_ctl.scala 406:170]
+    node _T_320 = and(_T_318, _T_319) @[dec_decode_ctl.scala 406:152]
+    node _T_321 = and(io.decode_exu.dec_i0_rs2_en_d, cam[3].valid) @[dec_decode_ctl.scala 406:214]
+    node _T_322 = eq(cam[3].bits.rd, i0r.rs2) @[dec_decode_ctl.scala 406:247]
+    node _T_323 = and(_T_321, _T_322) @[dec_decode_ctl.scala 406:229]
+    node _T_324 = or(_T_290, _T_299) @[dec_decode_ctl.scala 407:69]
+    node _T_325 = or(_T_324, _T_308) @[dec_decode_ctl.scala 407:69]
+    node waddr = or(_T_325, _T_317) @[dec_decode_ctl.scala 407:69]
+    node _T_326 = or(_T_293, _T_302) @[dec_decode_ctl.scala 407:102]
+    node _T_327 = or(_T_326, _T_311) @[dec_decode_ctl.scala 407:102]
+    node ld_stall_1 = or(_T_327, _T_320) @[dec_decode_ctl.scala 407:102]
+    node _T_328 = or(_T_296, _T_305) @[dec_decode_ctl.scala 407:134]
+    node _T_329 = or(_T_328, _T_314) @[dec_decode_ctl.scala 407:134]
+    node ld_stall_2 = or(_T_329, _T_323) @[dec_decode_ctl.scala 407:134]
+    io.dec_nonblock_load_waddr <= waddr @[dec_decode_ctl.scala 408:29]
+    node _T_330 = or(ld_stall_1, ld_stall_2) @[dec_decode_ctl.scala 409:38]
+    node _T_331 = or(_T_330, i0_nonblock_boundary_stall) @[dec_decode_ctl.scala 409:51]
+    i0_nonblock_load_stall <= _T_331 @[dec_decode_ctl.scala 409:25]
+    node _T_332 = eq(i0_predict_br, UInt<1>("h00")) @[dec_decode_ctl.scala 418:34]
+    node i0_br_unpred = and(i0_dp.jal, _T_332) @[dec_decode_ctl.scala 418:32]
     node _T_333 = bits(i0_legal_decode_d, 0, 0) @[Bitwise.scala 72:15]
     node _T_334 = mux(_T_333, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
-    node _T_335 = and(csr_read, io.dec_csr_wen_unq_d) @[dec_decode_ctl.scala 428:16]
-    node _T_336 = bits(_T_335, 0, 0) @[dec_decode_ctl.scala 428:30]
-    node _T_337 = eq(csr_read, UInt<1>("h00")) @[dec_decode_ctl.scala 429:6]
-    node _T_338 = and(_T_337, io.dec_csr_wen_unq_d) @[dec_decode_ctl.scala 429:16]
-    node _T_339 = bits(_T_338, 0, 0) @[dec_decode_ctl.scala 429:30]
-    node _T_340 = eq(io.dec_csr_wen_unq_d, UInt<1>("h00")) @[dec_decode_ctl.scala 430:18]
-    node _T_341 = and(csr_read, _T_340) @[dec_decode_ctl.scala 430:16]
-    node _T_342 = bits(_T_341, 0, 0) @[dec_decode_ctl.scala 430:30]
-    node _T_343 = or(i0_dp.zbb, i0_dp.zbs) @[dec_decode_ctl.scala 431:16]
-    node _T_344 = or(_T_343, i0_dp.zbe) @[dec_decode_ctl.scala 431:28]
-    node _T_345 = or(_T_344, i0_dp.zbc) @[dec_decode_ctl.scala 431:40]
-    node _T_346 = or(_T_345, i0_dp.zbp) @[dec_decode_ctl.scala 431:52]
-    node _T_347 = or(_T_346, i0_dp.zbr) @[dec_decode_ctl.scala 431:65]
-    node _T_348 = or(_T_347, i0_dp.zbf) @[dec_decode_ctl.scala 431:77]
-    node _T_349 = or(_T_348, i0_dp.zba) @[dec_decode_ctl.scala 431:89]
+    node _T_335 = and(csr_read, io.dec_csr_wen_unq_d) @[dec_decode_ctl.scala 430:16]
+    node _T_336 = bits(_T_335, 0, 0) @[dec_decode_ctl.scala 430:30]
+    node _T_337 = eq(csr_read, UInt<1>("h00")) @[dec_decode_ctl.scala 431:6]
+    node _T_338 = and(_T_337, io.dec_csr_wen_unq_d) @[dec_decode_ctl.scala 431:16]
+    node _T_339 = bits(_T_338, 0, 0) @[dec_decode_ctl.scala 431:30]
+    node _T_340 = eq(io.dec_csr_wen_unq_d, UInt<1>("h00")) @[dec_decode_ctl.scala 432:18]
+    node _T_341 = and(csr_read, _T_340) @[dec_decode_ctl.scala 432:16]
+    node _T_342 = bits(_T_341, 0, 0) @[dec_decode_ctl.scala 432:30]
+    node _T_343 = or(i0_dp.zbb, i0_dp.zbs) @[dec_decode_ctl.scala 433:16]
+    node _T_344 = or(_T_343, i0_dp.zbe) @[dec_decode_ctl.scala 433:28]
+    node _T_345 = or(_T_344, i0_dp.zbc) @[dec_decode_ctl.scala 433:40]
+    node _T_346 = or(_T_345, i0_dp.zbp) @[dec_decode_ctl.scala 433:52]
+    node _T_347 = or(_T_346, i0_dp.zbr) @[dec_decode_ctl.scala 433:65]
+    node _T_348 = or(_T_347, i0_dp.zbf) @[dec_decode_ctl.scala 433:77]
+    node _T_349 = or(_T_348, i0_dp.zba) @[dec_decode_ctl.scala 433:89]
     node _T_350 = mux(i0_dp.mul, UInt<4>("h01"), UInt<4>("h00")) @[Mux.scala 98:16]
     node _T_351 = mux(i0_dp.load, UInt<4>("h02"), _T_350) @[Mux.scala 98:16]
     node _T_352 = mux(i0_dp.store, UInt<4>("h03"), _T_351) @[Mux.scala 98:16]
@@ -6128,313 +6128,313 @@ circuit dec :
     node _T_362 = mux(i0_dp.mret, UInt<4>("h0c"), _T_361) @[Mux.scala 98:16]
     node _T_363 = mux(i0_dp.condbr, UInt<4>("h0d"), _T_362) @[Mux.scala 98:16]
     node _T_364 = mux(i0_dp.jal, UInt<4>("h0e"), _T_363) @[Mux.scala 98:16]
-    node _T_365 = and(_T_334, _T_364) @[dec_decode_ctl.scala 420:49]
-    d_t.pmu_i0_itype <= _T_365 @[dec_decode_ctl.scala 420:21]
-    inst i0_dec of dec_dec_ctl @[dec_decode_ctl.scala 438:22]
+    node _T_365 = and(_T_334, _T_364) @[dec_decode_ctl.scala 422:49]
+    d_t.pmu_i0_itype <= _T_365 @[dec_decode_ctl.scala 422:21]
+    inst i0_dec of dec_dec_ctl @[dec_decode_ctl.scala 440:22]
     i0_dec.clock <= clock
     i0_dec.reset <= reset
-    i0_dec.io.ins <= io.dec_i0_instr_d @[dec_decode_ctl.scala 439:16]
-    i0_dp_raw.legal <= i0_dec.io.out.legal @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.pm_alu <= i0_dec.io.out.pm_alu @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.fence_i <= i0_dec.io.out.fence_i @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.fence <= i0_dec.io.out.fence @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.rem <= i0_dec.io.out.rem @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.div <= i0_dec.io.out.div @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.low <= i0_dec.io.out.low @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.rs2_sign <= i0_dec.io.out.rs2_sign @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.rs1_sign <= i0_dec.io.out.rs1_sign @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.mul <= i0_dec.io.out.mul @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.mret <= i0_dec.io.out.mret @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.ecall <= i0_dec.io.out.ecall @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.ebreak <= i0_dec.io.out.ebreak @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.postsync <= i0_dec.io.out.postsync @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.presync <= i0_dec.io.out.presync @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.csr_imm <= i0_dec.io.out.csr_imm @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.csr_write <= i0_dec.io.out.csr_write @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.csr_set <= i0_dec.io.out.csr_set @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.csr_clr <= i0_dec.io.out.csr_clr @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.csr_read <= i0_dec.io.out.csr_read @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.word <= i0_dec.io.out.word @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.half <= i0_dec.io.out.half @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.by <= i0_dec.io.out.by @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.jal <= i0_dec.io.out.jal @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.blt <= i0_dec.io.out.blt @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.bge <= i0_dec.io.out.bge @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.bne <= i0_dec.io.out.bne @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.beq <= i0_dec.io.out.beq @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.condbr <= i0_dec.io.out.condbr @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.unsign <= i0_dec.io.out.unsign @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.slt <= i0_dec.io.out.slt @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.srl <= i0_dec.io.out.srl @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.sra <= i0_dec.io.out.sra @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.sll <= i0_dec.io.out.sll @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.lxor <= i0_dec.io.out.lxor @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.lor <= i0_dec.io.out.lor @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.land <= i0_dec.io.out.land @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.sub <= i0_dec.io.out.sub @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.add <= i0_dec.io.out.add @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.lsu <= i0_dec.io.out.lsu @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.store <= i0_dec.io.out.store @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.load <= i0_dec.io.out.load @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.pc <= i0_dec.io.out.pc @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.imm20 <= i0_dec.io.out.imm20 @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.shimm5 <= i0_dec.io.out.shimm5 @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.rd <= i0_dec.io.out.rd @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.imm12 <= i0_dec.io.out.imm12 @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.rs2 <= i0_dec.io.out.rs2 @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.rs1 <= i0_dec.io.out.rs1 @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.alu <= i0_dec.io.out.alu @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.zba <= i0_dec.io.out.zba @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.sh3add <= i0_dec.io.out.sh3add @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.sh2add <= i0_dec.io.out.sh2add @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.sh1add <= i0_dec.io.out.sh1add @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.zbf <= i0_dec.io.out.zbf @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.bfp <= i0_dec.io.out.bfp @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.zbr <= i0_dec.io.out.zbr @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.crc32c_w <= i0_dec.io.out.crc32c_w @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.crc32c_h <= i0_dec.io.out.crc32c_h @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.crc32c_b <= i0_dec.io.out.crc32c_b @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.crc32_w <= i0_dec.io.out.crc32_w @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.crc32_h <= i0_dec.io.out.crc32_h @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.crc32_b <= i0_dec.io.out.crc32_b @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.zbp <= i0_dec.io.out.zbp @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.unshfl <= i0_dec.io.out.unshfl @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.shfl <= i0_dec.io.out.shfl @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.zbc <= i0_dec.io.out.zbc @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.clmulr <= i0_dec.io.out.clmulr @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.clmulh <= i0_dec.io.out.clmulh @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.clmul <= i0_dec.io.out.clmul @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.zbe <= i0_dec.io.out.zbe @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.bdep <= i0_dec.io.out.bdep @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.bext <= i0_dec.io.out.bext @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.zbs <= i0_dec.io.out.zbs @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.sbext <= i0_dec.io.out.sbext @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.sbinv <= i0_dec.io.out.sbinv @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.sbclr <= i0_dec.io.out.sbclr @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.sbset <= i0_dec.io.out.sbset @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.zbb <= i0_dec.io.out.zbb @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.gorc <= i0_dec.io.out.gorc @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.grev <= i0_dec.io.out.grev @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.ror <= i0_dec.io.out.ror @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.rol <= i0_dec.io.out.rol @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.packh <= i0_dec.io.out.packh @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.packu <= i0_dec.io.out.packu @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.pack <= i0_dec.io.out.pack @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.max <= i0_dec.io.out.max @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.min <= i0_dec.io.out.min @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.sro <= i0_dec.io.out.sro @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.slo <= i0_dec.io.out.slo @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.sext_h <= i0_dec.io.out.sext_h @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.sext_b <= i0_dec.io.out.sext_b @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.pcnt <= i0_dec.io.out.pcnt @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.ctz <= i0_dec.io.out.ctz @[dec_decode_ctl.scala 440:12]
-    i0_dp_raw.clz <= i0_dec.io.out.clz @[dec_decode_ctl.scala 440:12]
-    reg _T_366 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 442:45]
-    _T_366 <= io.lsu_idle_any @[dec_decode_ctl.scala 442:45]
-    lsu_idle <= _T_366 @[dec_decode_ctl.scala 442:11]
-    node _T_367 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 445:73]
-    node _T_368 = and(leak1_i1_stall, _T_367) @[dec_decode_ctl.scala 445:71]
-    node _T_369 = or(io.dec_tlu_flush_leak_one_r, _T_368) @[dec_decode_ctl.scala 445:53]
-    leak1_i1_stall_in <= _T_369 @[dec_decode_ctl.scala 445:21]
-    leak1_mode <= leak1_i1_stall @[dec_decode_ctl.scala 446:14]
-    node _T_370 = and(io.dec_aln.dec_i0_decode_d, leak1_i1_stall) @[dec_decode_ctl.scala 447:53]
-    node _T_371 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 447:91]
-    node _T_372 = and(leak1_i0_stall, _T_371) @[dec_decode_ctl.scala 447:89]
-    node _T_373 = or(_T_370, _T_372) @[dec_decode_ctl.scala 447:71]
-    leak1_i0_stall_in <= _T_373 @[dec_decode_ctl.scala 447:21]
-    node _T_374 = bits(io.dec_i0_instr_d, 31, 31) @[dec_decode_ctl.scala 451:29]
-    node _T_375 = bits(io.dec_i0_instr_d, 19, 12) @[dec_decode_ctl.scala 451:36]
-    node _T_376 = bits(io.dec_i0_instr_d, 20, 20) @[dec_decode_ctl.scala 451:46]
-    node _T_377 = bits(io.dec_i0_instr_d, 30, 21) @[dec_decode_ctl.scala 451:53]
+    i0_dec.io.ins <= io.dec_i0_instr_d @[dec_decode_ctl.scala 441:16]
+    i0_dp_raw.legal <= i0_dec.io.out.legal @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.pm_alu <= i0_dec.io.out.pm_alu @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.fence_i <= i0_dec.io.out.fence_i @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.fence <= i0_dec.io.out.fence @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.rem <= i0_dec.io.out.rem @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.div <= i0_dec.io.out.div @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.low <= i0_dec.io.out.low @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.rs2_sign <= i0_dec.io.out.rs2_sign @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.rs1_sign <= i0_dec.io.out.rs1_sign @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.mul <= i0_dec.io.out.mul @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.mret <= i0_dec.io.out.mret @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.ecall <= i0_dec.io.out.ecall @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.ebreak <= i0_dec.io.out.ebreak @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.postsync <= i0_dec.io.out.postsync @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.presync <= i0_dec.io.out.presync @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.csr_imm <= i0_dec.io.out.csr_imm @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.csr_write <= i0_dec.io.out.csr_write @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.csr_set <= i0_dec.io.out.csr_set @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.csr_clr <= i0_dec.io.out.csr_clr @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.csr_read <= i0_dec.io.out.csr_read @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.word <= i0_dec.io.out.word @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.half <= i0_dec.io.out.half @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.by <= i0_dec.io.out.by @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.jal <= i0_dec.io.out.jal @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.blt <= i0_dec.io.out.blt @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.bge <= i0_dec.io.out.bge @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.bne <= i0_dec.io.out.bne @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.beq <= i0_dec.io.out.beq @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.condbr <= i0_dec.io.out.condbr @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.unsign <= i0_dec.io.out.unsign @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.slt <= i0_dec.io.out.slt @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.srl <= i0_dec.io.out.srl @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.sra <= i0_dec.io.out.sra @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.sll <= i0_dec.io.out.sll @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.lxor <= i0_dec.io.out.lxor @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.lor <= i0_dec.io.out.lor @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.land <= i0_dec.io.out.land @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.sub <= i0_dec.io.out.sub @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.add <= i0_dec.io.out.add @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.lsu <= i0_dec.io.out.lsu @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.store <= i0_dec.io.out.store @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.load <= i0_dec.io.out.load @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.pc <= i0_dec.io.out.pc @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.imm20 <= i0_dec.io.out.imm20 @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.shimm5 <= i0_dec.io.out.shimm5 @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.rd <= i0_dec.io.out.rd @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.imm12 <= i0_dec.io.out.imm12 @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.rs2 <= i0_dec.io.out.rs2 @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.rs1 <= i0_dec.io.out.rs1 @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.alu <= i0_dec.io.out.alu @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.zba <= i0_dec.io.out.zba @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.sh3add <= i0_dec.io.out.sh3add @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.sh2add <= i0_dec.io.out.sh2add @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.sh1add <= i0_dec.io.out.sh1add @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.zbf <= i0_dec.io.out.zbf @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.bfp <= i0_dec.io.out.bfp @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.zbr <= i0_dec.io.out.zbr @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.crc32c_w <= i0_dec.io.out.crc32c_w @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.crc32c_h <= i0_dec.io.out.crc32c_h @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.crc32c_b <= i0_dec.io.out.crc32c_b @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.crc32_w <= i0_dec.io.out.crc32_w @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.crc32_h <= i0_dec.io.out.crc32_h @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.crc32_b <= i0_dec.io.out.crc32_b @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.zbp <= i0_dec.io.out.zbp @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.unshfl <= i0_dec.io.out.unshfl @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.shfl <= i0_dec.io.out.shfl @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.zbc <= i0_dec.io.out.zbc @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.clmulr <= i0_dec.io.out.clmulr @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.clmulh <= i0_dec.io.out.clmulh @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.clmul <= i0_dec.io.out.clmul @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.zbe <= i0_dec.io.out.zbe @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.bdep <= i0_dec.io.out.bdep @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.bext <= i0_dec.io.out.bext @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.zbs <= i0_dec.io.out.zbs @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.sbext <= i0_dec.io.out.sbext @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.sbinv <= i0_dec.io.out.sbinv @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.sbclr <= i0_dec.io.out.sbclr @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.sbset <= i0_dec.io.out.sbset @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.zbb <= i0_dec.io.out.zbb @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.gorc <= i0_dec.io.out.gorc @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.grev <= i0_dec.io.out.grev @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.ror <= i0_dec.io.out.ror @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.rol <= i0_dec.io.out.rol @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.packh <= i0_dec.io.out.packh @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.packu <= i0_dec.io.out.packu @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.pack <= i0_dec.io.out.pack @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.max <= i0_dec.io.out.max @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.min <= i0_dec.io.out.min @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.sro <= i0_dec.io.out.sro @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.slo <= i0_dec.io.out.slo @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.sext_h <= i0_dec.io.out.sext_h @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.sext_b <= i0_dec.io.out.sext_b @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.pcnt <= i0_dec.io.out.pcnt @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.ctz <= i0_dec.io.out.ctz @[dec_decode_ctl.scala 442:12]
+    i0_dp_raw.clz <= i0_dec.io.out.clz @[dec_decode_ctl.scala 442:12]
+    reg _T_366 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 444:45]
+    _T_366 <= io.lsu_idle_any @[dec_decode_ctl.scala 444:45]
+    lsu_idle <= _T_366 @[dec_decode_ctl.scala 444:11]
+    node _T_367 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 447:73]
+    node _T_368 = and(leak1_i1_stall, _T_367) @[dec_decode_ctl.scala 447:71]
+    node _T_369 = or(io.dec_tlu_flush_leak_one_r, _T_368) @[dec_decode_ctl.scala 447:53]
+    leak1_i1_stall_in <= _T_369 @[dec_decode_ctl.scala 447:21]
+    leak1_mode <= leak1_i1_stall @[dec_decode_ctl.scala 448:14]
+    node _T_370 = and(io.dec_i0_decode_d, leak1_i1_stall) @[dec_decode_ctl.scala 449:45]
+    node _T_371 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 449:83]
+    node _T_372 = and(leak1_i0_stall, _T_371) @[dec_decode_ctl.scala 449:81]
+    node _T_373 = or(_T_370, _T_372) @[dec_decode_ctl.scala 449:63]
+    leak1_i0_stall_in <= _T_373 @[dec_decode_ctl.scala 449:21]
+    node _T_374 = bits(io.dec_i0_instr_d, 31, 31) @[dec_decode_ctl.scala 453:29]
+    node _T_375 = bits(io.dec_i0_instr_d, 19, 12) @[dec_decode_ctl.scala 453:36]
+    node _T_376 = bits(io.dec_i0_instr_d, 20, 20) @[dec_decode_ctl.scala 453:46]
+    node _T_377 = bits(io.dec_i0_instr_d, 30, 21) @[dec_decode_ctl.scala 453:53]
     node _T_378 = cat(_T_376, _T_377) @[Cat.scala 29:58]
     node _T_379 = cat(_T_374, _T_375) @[Cat.scala 29:58]
     node i0_pcall_imm = cat(_T_379, _T_378) @[Cat.scala 29:58]
-    node _T_380 = bits(i0_pcall_imm, 11, 11) @[dec_decode_ctl.scala 452:46]
-    node _T_381 = bits(_T_380, 0, 0) @[dec_decode_ctl.scala 452:51]
-    node _T_382 = bits(i0_pcall_imm, 19, 12) @[dec_decode_ctl.scala 452:71]
-    node _T_383 = eq(_T_382, UInt<8>("h0ff")) @[dec_decode_ctl.scala 452:79]
-    node _T_384 = bits(i0_pcall_imm, 19, 12) @[dec_decode_ctl.scala 452:104]
-    node _T_385 = eq(_T_384, UInt<8>("h00")) @[dec_decode_ctl.scala 452:112]
-    node i0_pcall_12b_offset = mux(_T_381, _T_383, _T_385) @[dec_decode_ctl.scala 452:33]
-    node _T_386 = and(i0_pcall_12b_offset, i0_dp_raw.imm20) @[dec_decode_ctl.scala 453:47]
-    node _T_387 = eq(i0r.rd, UInt<5>("h01")) @[dec_decode_ctl.scala 453:76]
-    node _T_388 = eq(i0r.rd, UInt<5>("h05")) @[dec_decode_ctl.scala 453:98]
-    node _T_389 = or(_T_387, _T_388) @[dec_decode_ctl.scala 453:89]
-    node i0_pcall_case = and(_T_386, _T_389) @[dec_decode_ctl.scala 453:65]
-    node _T_390 = and(i0_pcall_12b_offset, i0_dp_raw.imm20) @[dec_decode_ctl.scala 454:47]
-    node _T_391 = eq(i0r.rd, UInt<5>("h01")) @[dec_decode_ctl.scala 454:76]
-    node _T_392 = eq(i0r.rd, UInt<5>("h05")) @[dec_decode_ctl.scala 454:98]
-    node _T_393 = or(_T_391, _T_392) @[dec_decode_ctl.scala 454:89]
-    node _T_394 = eq(_T_393, UInt<1>("h00")) @[dec_decode_ctl.scala 454:67]
-    node i0_pja_case = and(_T_390, _T_394) @[dec_decode_ctl.scala 454:65]
-    node _T_395 = and(i0_dp_raw.jal, i0_pcall_case) @[dec_decode_ctl.scala 455:38]
-    i0_pcall_raw <= _T_395 @[dec_decode_ctl.scala 455:20]
-    node _T_396 = and(i0_dp.jal, i0_pcall_case) @[dec_decode_ctl.scala 456:38]
-    i0_pcall <= _T_396 @[dec_decode_ctl.scala 456:20]
-    node _T_397 = and(i0_dp_raw.jal, i0_pja_case) @[dec_decode_ctl.scala 457:38]
-    i0_pja_raw <= _T_397 @[dec_decode_ctl.scala 457:20]
-    node _T_398 = and(i0_dp.jal, i0_pja_case) @[dec_decode_ctl.scala 458:38]
-    i0_pja <= _T_398 @[dec_decode_ctl.scala 458:20]
-    node _T_399 = or(i0_pcall_raw, i0_pja_raw) @[dec_decode_ctl.scala 459:41]
-    node _T_400 = bits(_T_399, 0, 0) @[dec_decode_ctl.scala 459:55]
-    node _T_401 = bits(i0_pcall_imm, 11, 0) @[dec_decode_ctl.scala 459:75]
-    node _T_402 = bits(io.dec_i0_instr_d, 31, 31) @[dec_decode_ctl.scala 459:90]
-    node _T_403 = bits(io.dec_i0_instr_d, 7, 7) @[dec_decode_ctl.scala 459:97]
-    node _T_404 = bits(io.dec_i0_instr_d, 30, 25) @[dec_decode_ctl.scala 459:103]
-    node _T_405 = bits(io.dec_i0_instr_d, 11, 8) @[dec_decode_ctl.scala 459:113]
+    node _T_380 = bits(i0_pcall_imm, 11, 11) @[dec_decode_ctl.scala 454:46]
+    node _T_381 = bits(_T_380, 0, 0) @[dec_decode_ctl.scala 454:51]
+    node _T_382 = bits(i0_pcall_imm, 19, 12) @[dec_decode_ctl.scala 454:71]
+    node _T_383 = eq(_T_382, UInt<8>("h0ff")) @[dec_decode_ctl.scala 454:79]
+    node _T_384 = bits(i0_pcall_imm, 19, 12) @[dec_decode_ctl.scala 454:104]
+    node _T_385 = eq(_T_384, UInt<8>("h00")) @[dec_decode_ctl.scala 454:112]
+    node i0_pcall_12b_offset = mux(_T_381, _T_383, _T_385) @[dec_decode_ctl.scala 454:33]
+    node _T_386 = and(i0_pcall_12b_offset, i0_dp_raw.imm20) @[dec_decode_ctl.scala 455:47]
+    node _T_387 = eq(i0r.rd, UInt<5>("h01")) @[dec_decode_ctl.scala 455:76]
+    node _T_388 = eq(i0r.rd, UInt<5>("h05")) @[dec_decode_ctl.scala 455:98]
+    node _T_389 = or(_T_387, _T_388) @[dec_decode_ctl.scala 455:89]
+    node i0_pcall_case = and(_T_386, _T_389) @[dec_decode_ctl.scala 455:65]
+    node _T_390 = and(i0_pcall_12b_offset, i0_dp_raw.imm20) @[dec_decode_ctl.scala 456:47]
+    node _T_391 = eq(i0r.rd, UInt<5>("h01")) @[dec_decode_ctl.scala 456:76]
+    node _T_392 = eq(i0r.rd, UInt<5>("h05")) @[dec_decode_ctl.scala 456:98]
+    node _T_393 = or(_T_391, _T_392) @[dec_decode_ctl.scala 456:89]
+    node _T_394 = eq(_T_393, UInt<1>("h00")) @[dec_decode_ctl.scala 456:67]
+    node i0_pja_case = and(_T_390, _T_394) @[dec_decode_ctl.scala 456:65]
+    node _T_395 = and(i0_dp_raw.jal, i0_pcall_case) @[dec_decode_ctl.scala 457:38]
+    i0_pcall_raw <= _T_395 @[dec_decode_ctl.scala 457:20]
+    node _T_396 = and(i0_dp.jal, i0_pcall_case) @[dec_decode_ctl.scala 458:38]
+    i0_pcall <= _T_396 @[dec_decode_ctl.scala 458:20]
+    node _T_397 = and(i0_dp_raw.jal, i0_pja_case) @[dec_decode_ctl.scala 459:38]
+    i0_pja_raw <= _T_397 @[dec_decode_ctl.scala 459:20]
+    node _T_398 = and(i0_dp.jal, i0_pja_case) @[dec_decode_ctl.scala 460:38]
+    i0_pja <= _T_398 @[dec_decode_ctl.scala 460:20]
+    node _T_399 = or(i0_pcall_raw, i0_pja_raw) @[dec_decode_ctl.scala 461:41]
+    node _T_400 = bits(_T_399, 0, 0) @[dec_decode_ctl.scala 461:55]
+    node _T_401 = bits(i0_pcall_imm, 11, 0) @[dec_decode_ctl.scala 461:75]
+    node _T_402 = bits(io.dec_i0_instr_d, 31, 31) @[dec_decode_ctl.scala 461:90]
+    node _T_403 = bits(io.dec_i0_instr_d, 7, 7) @[dec_decode_ctl.scala 461:97]
+    node _T_404 = bits(io.dec_i0_instr_d, 30, 25) @[dec_decode_ctl.scala 461:103]
+    node _T_405 = bits(io.dec_i0_instr_d, 11, 8) @[dec_decode_ctl.scala 461:113]
     node _T_406 = cat(_T_404, _T_405) @[Cat.scala 29:58]
     node _T_407 = cat(_T_402, _T_403) @[Cat.scala 29:58]
     node _T_408 = cat(_T_407, _T_406) @[Cat.scala 29:58]
-    node _T_409 = mux(_T_400, _T_401, _T_408) @[dec_decode_ctl.scala 459:26]
-    i0_br_offset <= _T_409 @[dec_decode_ctl.scala 459:20]
-    node _T_410 = and(i0_dp_raw.jal, i0_dp_raw.imm12) @[dec_decode_ctl.scala 461:37]
-    node _T_411 = eq(i0r.rd, UInt<5>("h00")) @[dec_decode_ctl.scala 461:65]
-    node _T_412 = and(_T_410, _T_411) @[dec_decode_ctl.scala 461:55]
-    node _T_413 = eq(i0r.rs1, UInt<5>("h01")) @[dec_decode_ctl.scala 461:89]
-    node _T_414 = eq(i0r.rs1, UInt<5>("h05")) @[dec_decode_ctl.scala 461:111]
-    node _T_415 = or(_T_413, _T_414) @[dec_decode_ctl.scala 461:101]
-    node i0_pret_case = and(_T_412, _T_415) @[dec_decode_ctl.scala 461:79]
-    node _T_416 = and(i0_dp_raw.jal, i0_pret_case) @[dec_decode_ctl.scala 462:32]
-    i0_pret_raw <= _T_416 @[dec_decode_ctl.scala 462:15]
-    node _T_417 = and(i0_dp.jal, i0_pret_case) @[dec_decode_ctl.scala 463:32]
-    i0_pret <= _T_417 @[dec_decode_ctl.scala 463:15]
-    node _T_418 = eq(i0_pcall_case, UInt<1>("h00")) @[dec_decode_ctl.scala 464:35]
-    node _T_419 = and(i0_dp.jal, _T_418) @[dec_decode_ctl.scala 464:32]
-    node _T_420 = eq(i0_pja_case, UInt<1>("h00")) @[dec_decode_ctl.scala 464:52]
-    node _T_421 = and(_T_419, _T_420) @[dec_decode_ctl.scala 464:50]
-    node _T_422 = eq(i0_pret_case, UInt<1>("h00")) @[dec_decode_ctl.scala 464:67]
-    node _T_423 = and(_T_421, _T_422) @[dec_decode_ctl.scala 464:65]
-    i0_jal <= _T_423 @[dec_decode_ctl.scala 464:15]
-    io.dec_div.div_p.valid <= div_decode_d @[dec_decode_ctl.scala 467:29]
-    io.dec_div.div_p.bits.unsign <= i0_dp.unsign @[dec_decode_ctl.scala 468:34]
-    io.dec_div.div_p.bits.rem <= i0_dp.rem @[dec_decode_ctl.scala 469:34]
-    io.decode_exu.mul_p.valid <= mul_decode_d @[dec_decode_ctl.scala 471:32]
-    io.decode_exu.mul_p.bits.rs1_sign <= i0_dp.rs1_sign @[dec_decode_ctl.scala 472:37]
-    io.decode_exu.mul_p.bits.rs2_sign <= i0_dp.rs2_sign @[dec_decode_ctl.scala 473:37]
-    io.decode_exu.mul_p.bits.low <= i0_dp.low @[dec_decode_ctl.scala 474:37]
-    io.decode_exu.mul_p.bits.bext <= i0_dp.bext @[dec_decode_ctl.scala 475:37]
-    io.decode_exu.mul_p.bits.bdep <= i0_dp.bdep @[dec_decode_ctl.scala 476:37]
-    io.decode_exu.mul_p.bits.clmul <= i0_dp.clmul @[dec_decode_ctl.scala 477:37]
-    io.decode_exu.mul_p.bits.clmulh <= i0_dp.clmulh @[dec_decode_ctl.scala 478:37]
-    io.decode_exu.mul_p.bits.clmulr <= i0_dp.clmulr @[dec_decode_ctl.scala 479:37]
-    io.decode_exu.mul_p.bits.grev <= i0_dp.grev @[dec_decode_ctl.scala 480:37]
-    io.decode_exu.mul_p.bits.gorc <= i0_dp.gorc @[dec_decode_ctl.scala 481:37]
-    io.decode_exu.mul_p.bits.shfl <= i0_dp.shfl @[dec_decode_ctl.scala 482:37]
-    io.decode_exu.mul_p.bits.unshfl <= i0_dp.unshfl @[dec_decode_ctl.scala 483:37]
-    io.decode_exu.mul_p.bits.crc32_b <= i0_dp.crc32_b @[dec_decode_ctl.scala 484:37]
-    io.decode_exu.mul_p.bits.crc32_h <= i0_dp.crc32_h @[dec_decode_ctl.scala 485:37]
-    io.decode_exu.mul_p.bits.crc32_w <= i0_dp.crc32_w @[dec_decode_ctl.scala 486:37]
-    io.decode_exu.mul_p.bits.crc32c_b <= i0_dp.crc32c_b @[dec_decode_ctl.scala 487:37]
-    io.decode_exu.mul_p.bits.crc32c_h <= i0_dp.crc32c_h @[dec_decode_ctl.scala 488:37]
-    io.decode_exu.mul_p.bits.crc32c_w <= i0_dp.crc32c_w @[dec_decode_ctl.scala 489:37]
-    io.decode_exu.mul_p.bits.bfp <= i0_dp.bfp @[dec_decode_ctl.scala 490:37]
-    wire _T_424 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[dec_decode_ctl.scala 493:27]
-    _T_424.bits.store_data_bypass_m <= UInt<1>("h00") @[dec_decode_ctl.scala 493:27]
-    _T_424.bits.load_ldst_bypass_d <= UInt<1>("h00") @[dec_decode_ctl.scala 493:27]
-    _T_424.bits.store_data_bypass_d <= UInt<1>("h00") @[dec_decode_ctl.scala 493:27]
-    _T_424.bits.dma <= UInt<1>("h00") @[dec_decode_ctl.scala 493:27]
-    _T_424.bits.unsign <= UInt<1>("h00") @[dec_decode_ctl.scala 493:27]
-    _T_424.bits.store <= UInt<1>("h00") @[dec_decode_ctl.scala 493:27]
-    _T_424.bits.load <= UInt<1>("h00") @[dec_decode_ctl.scala 493:27]
-    _T_424.bits.dword <= UInt<1>("h00") @[dec_decode_ctl.scala 493:27]
-    _T_424.bits.word <= UInt<1>("h00") @[dec_decode_ctl.scala 493:27]
-    _T_424.bits.half <= UInt<1>("h00") @[dec_decode_ctl.scala 493:27]
-    _T_424.bits.by <= UInt<1>("h00") @[dec_decode_ctl.scala 493:27]
-    _T_424.bits.stack <= UInt<1>("h00") @[dec_decode_ctl.scala 493:27]
-    _T_424.bits.fast_int <= UInt<1>("h00") @[dec_decode_ctl.scala 493:27]
-    _T_424.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 493:27]
-    io.lsu_p.bits.store_data_bypass_m <= _T_424.bits.store_data_bypass_m @[dec_decode_ctl.scala 493:12]
-    io.lsu_p.bits.load_ldst_bypass_d <= _T_424.bits.load_ldst_bypass_d @[dec_decode_ctl.scala 493:12]
-    io.lsu_p.bits.store_data_bypass_d <= _T_424.bits.store_data_bypass_d @[dec_decode_ctl.scala 493:12]
-    io.lsu_p.bits.dma <= _T_424.bits.dma @[dec_decode_ctl.scala 493:12]
-    io.lsu_p.bits.unsign <= _T_424.bits.unsign @[dec_decode_ctl.scala 493:12]
-    io.lsu_p.bits.store <= _T_424.bits.store @[dec_decode_ctl.scala 493:12]
-    io.lsu_p.bits.load <= _T_424.bits.load @[dec_decode_ctl.scala 493:12]
-    io.lsu_p.bits.dword <= _T_424.bits.dword @[dec_decode_ctl.scala 493:12]
-    io.lsu_p.bits.word <= _T_424.bits.word @[dec_decode_ctl.scala 493:12]
-    io.lsu_p.bits.half <= _T_424.bits.half @[dec_decode_ctl.scala 493:12]
-    io.lsu_p.bits.by <= _T_424.bits.by @[dec_decode_ctl.scala 493:12]
-    io.lsu_p.bits.stack <= _T_424.bits.stack @[dec_decode_ctl.scala 493:12]
-    io.lsu_p.bits.fast_int <= _T_424.bits.fast_int @[dec_decode_ctl.scala 493:12]
-    io.lsu_p.valid <= _T_424.valid @[dec_decode_ctl.scala 493:12]
-    when io.decode_exu.dec_extint_stall : @[dec_decode_ctl.scala 494:40]
-      io.lsu_p.bits.load <= UInt<1>("h01") @[dec_decode_ctl.scala 495:29]
-      io.lsu_p.bits.word <= UInt<1>("h01") @[dec_decode_ctl.scala 496:29]
-      io.lsu_p.bits.fast_int <= UInt<1>("h01") @[dec_decode_ctl.scala 497:29]
-      io.lsu_p.valid <= UInt<1>("h01") @[dec_decode_ctl.scala 498:24]
-      skip @[dec_decode_ctl.scala 494:40]
-    else : @[dec_decode_ctl.scala 501:15]
-      io.lsu_p.valid <= lsu_decode_d @[dec_decode_ctl.scala 502:35]
-      io.lsu_p.bits.load <= i0_dp.load @[dec_decode_ctl.scala 503:40]
-      io.lsu_p.bits.store <= i0_dp.store @[dec_decode_ctl.scala 504:40]
-      io.lsu_p.bits.by <= i0_dp.by @[dec_decode_ctl.scala 505:40]
-      io.lsu_p.bits.half <= i0_dp.half @[dec_decode_ctl.scala 506:40]
-      io.lsu_p.bits.word <= i0_dp.word @[dec_decode_ctl.scala 507:40]
-      node _T_425 = eq(i0r.rs1, UInt<5>("h02")) @[dec_decode_ctl.scala 508:41]
-      io.lsu_p.bits.stack <= _T_425 @[dec_decode_ctl.scala 508:29]
-      io.lsu_p.bits.load_ldst_bypass_d <= load_ldst_bypass_d @[dec_decode_ctl.scala 509:40]
-      io.lsu_p.bits.store_data_bypass_d <= store_data_bypass_d @[dec_decode_ctl.scala 510:40]
-      io.lsu_p.bits.store_data_bypass_m <= store_data_bypass_m @[dec_decode_ctl.scala 511:40]
-      io.lsu_p.bits.unsign <= i0_dp.unsign @[dec_decode_ctl.scala 512:40]
-      skip @[dec_decode_ctl.scala 501:15]
-    node _T_426 = and(i0_dp.csr_read, io.dec_ib0_valid_d) @[dec_decode_ctl.scala 516:47]
-    io.dec_alu.dec_csr_ren_d <= _T_426 @[dec_decode_ctl.scala 516:29]
-    node _T_427 = bits(i0_legal_decode_d, 0, 0) @[dec_decode_ctl.scala 517:56]
-    node _T_428 = and(i0_dp.csr_read, _T_427) @[dec_decode_ctl.scala 517:36]
-    csr_read <= _T_428 @[dec_decode_ctl.scala 517:18]
-    node _T_429 = eq(io.dec_debug_fence_d, UInt<1>("h00")) @[dec_decode_ctl.scala 519:42]
-    node i0_csr_write = and(i0_dp.csr_write, _T_429) @[dec_decode_ctl.scala 519:40]
-    node _T_430 = bits(i0_legal_decode_d, 0, 0) @[dec_decode_ctl.scala 520:61]
-    node csr_clr_d = and(i0_dp.csr_clr, _T_430) @[dec_decode_ctl.scala 520:41]
-    node _T_431 = bits(i0_legal_decode_d, 0, 0) @[dec_decode_ctl.scala 521:59]
-    node csr_set_d = and(i0_dp.csr_set, _T_431) @[dec_decode_ctl.scala 521:39]
-    node _T_432 = bits(i0_legal_decode_d, 0, 0) @[dec_decode_ctl.scala 522:59]
-    node csr_write_d = and(i0_csr_write, _T_432) @[dec_decode_ctl.scala 522:39]
-    node _T_433 = eq(i0_dp.csr_read, UInt<1>("h00")) @[dec_decode_ctl.scala 524:41]
-    node _T_434 = and(i0_csr_write, _T_433) @[dec_decode_ctl.scala 524:39]
-    i0_csr_write_only_d <= _T_434 @[dec_decode_ctl.scala 524:23]
-    node _T_435 = or(i0_dp.csr_clr, i0_dp.csr_set) @[dec_decode_ctl.scala 525:42]
-    node _T_436 = or(_T_435, i0_csr_write) @[dec_decode_ctl.scala 525:58]
-    node _T_437 = and(_T_436, io.dec_ib0_valid_d) @[dec_decode_ctl.scala 525:74]
-    io.dec_csr_wen_unq_d <= _T_437 @[dec_decode_ctl.scala 525:24]
-    node any_csr_d = or(i0_dp.csr_read, i0_csr_write) @[dec_decode_ctl.scala 527:34]
-    node _T_438 = and(any_csr_d, io.dec_ib0_valid_d) @[dec_decode_ctl.scala 528:37]
-    io.dec_csr_any_unq_d <= _T_438 @[dec_decode_ctl.scala 528:24]
+    node _T_409 = mux(_T_400, _T_401, _T_408) @[dec_decode_ctl.scala 461:26]
+    i0_br_offset <= _T_409 @[dec_decode_ctl.scala 461:20]
+    node _T_410 = and(i0_dp_raw.jal, i0_dp_raw.imm12) @[dec_decode_ctl.scala 463:37]
+    node _T_411 = eq(i0r.rd, UInt<5>("h00")) @[dec_decode_ctl.scala 463:65]
+    node _T_412 = and(_T_410, _T_411) @[dec_decode_ctl.scala 463:55]
+    node _T_413 = eq(i0r.rs1, UInt<5>("h01")) @[dec_decode_ctl.scala 463:89]
+    node _T_414 = eq(i0r.rs1, UInt<5>("h05")) @[dec_decode_ctl.scala 463:111]
+    node _T_415 = or(_T_413, _T_414) @[dec_decode_ctl.scala 463:101]
+    node i0_pret_case = and(_T_412, _T_415) @[dec_decode_ctl.scala 463:79]
+    node _T_416 = and(i0_dp_raw.jal, i0_pret_case) @[dec_decode_ctl.scala 464:32]
+    i0_pret_raw <= _T_416 @[dec_decode_ctl.scala 464:15]
+    node _T_417 = and(i0_dp.jal, i0_pret_case) @[dec_decode_ctl.scala 465:32]
+    i0_pret <= _T_417 @[dec_decode_ctl.scala 465:15]
+    node _T_418 = eq(i0_pcall_case, UInt<1>("h00")) @[dec_decode_ctl.scala 466:35]
+    node _T_419 = and(i0_dp.jal, _T_418) @[dec_decode_ctl.scala 466:32]
+    node _T_420 = eq(i0_pja_case, UInt<1>("h00")) @[dec_decode_ctl.scala 466:52]
+    node _T_421 = and(_T_419, _T_420) @[dec_decode_ctl.scala 466:50]
+    node _T_422 = eq(i0_pret_case, UInt<1>("h00")) @[dec_decode_ctl.scala 466:67]
+    node _T_423 = and(_T_421, _T_422) @[dec_decode_ctl.scala 466:65]
+    i0_jal <= _T_423 @[dec_decode_ctl.scala 466:15]
+    io.dec_div.div_p.valid <= div_decode_d @[dec_decode_ctl.scala 469:29]
+    io.dec_div.div_p.bits.unsign <= i0_dp.unsign @[dec_decode_ctl.scala 470:34]
+    io.dec_div.div_p.bits.rem <= i0_dp.rem @[dec_decode_ctl.scala 471:34]
+    io.decode_exu.mul_p.valid <= mul_decode_d @[dec_decode_ctl.scala 473:32]
+    io.decode_exu.mul_p.bits.rs1_sign <= i0_dp.rs1_sign @[dec_decode_ctl.scala 474:37]
+    io.decode_exu.mul_p.bits.rs2_sign <= i0_dp.rs2_sign @[dec_decode_ctl.scala 475:37]
+    io.decode_exu.mul_p.bits.low <= i0_dp.low @[dec_decode_ctl.scala 476:37]
+    io.decode_exu.mul_p.bits.bext <= i0_dp.bext @[dec_decode_ctl.scala 477:37]
+    io.decode_exu.mul_p.bits.bdep <= i0_dp.bdep @[dec_decode_ctl.scala 478:37]
+    io.decode_exu.mul_p.bits.clmul <= i0_dp.clmul @[dec_decode_ctl.scala 479:37]
+    io.decode_exu.mul_p.bits.clmulh <= i0_dp.clmulh @[dec_decode_ctl.scala 480:37]
+    io.decode_exu.mul_p.bits.clmulr <= i0_dp.clmulr @[dec_decode_ctl.scala 481:37]
+    io.decode_exu.mul_p.bits.grev <= i0_dp.grev @[dec_decode_ctl.scala 482:37]
+    io.decode_exu.mul_p.bits.gorc <= i0_dp.gorc @[dec_decode_ctl.scala 483:37]
+    io.decode_exu.mul_p.bits.shfl <= i0_dp.shfl @[dec_decode_ctl.scala 484:37]
+    io.decode_exu.mul_p.bits.unshfl <= i0_dp.unshfl @[dec_decode_ctl.scala 485:37]
+    io.decode_exu.mul_p.bits.crc32_b <= i0_dp.crc32_b @[dec_decode_ctl.scala 486:37]
+    io.decode_exu.mul_p.bits.crc32_h <= i0_dp.crc32_h @[dec_decode_ctl.scala 487:37]
+    io.decode_exu.mul_p.bits.crc32_w <= i0_dp.crc32_w @[dec_decode_ctl.scala 488:37]
+    io.decode_exu.mul_p.bits.crc32c_b <= i0_dp.crc32c_b @[dec_decode_ctl.scala 489:37]
+    io.decode_exu.mul_p.bits.crc32c_h <= i0_dp.crc32c_h @[dec_decode_ctl.scala 490:37]
+    io.decode_exu.mul_p.bits.crc32c_w <= i0_dp.crc32c_w @[dec_decode_ctl.scala 491:37]
+    io.decode_exu.mul_p.bits.bfp <= i0_dp.bfp @[dec_decode_ctl.scala 492:37]
+    wire _T_424 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[dec_decode_ctl.scala 495:27]
+    _T_424.bits.store_data_bypass_m <= UInt<1>("h00") @[dec_decode_ctl.scala 495:27]
+    _T_424.bits.load_ldst_bypass_d <= UInt<1>("h00") @[dec_decode_ctl.scala 495:27]
+    _T_424.bits.store_data_bypass_d <= UInt<1>("h00") @[dec_decode_ctl.scala 495:27]
+    _T_424.bits.dma <= UInt<1>("h00") @[dec_decode_ctl.scala 495:27]
+    _T_424.bits.unsign <= UInt<1>("h00") @[dec_decode_ctl.scala 495:27]
+    _T_424.bits.store <= UInt<1>("h00") @[dec_decode_ctl.scala 495:27]
+    _T_424.bits.load <= UInt<1>("h00") @[dec_decode_ctl.scala 495:27]
+    _T_424.bits.dword <= UInt<1>("h00") @[dec_decode_ctl.scala 495:27]
+    _T_424.bits.word <= UInt<1>("h00") @[dec_decode_ctl.scala 495:27]
+    _T_424.bits.half <= UInt<1>("h00") @[dec_decode_ctl.scala 495:27]
+    _T_424.bits.by <= UInt<1>("h00") @[dec_decode_ctl.scala 495:27]
+    _T_424.bits.stack <= UInt<1>("h00") @[dec_decode_ctl.scala 495:27]
+    _T_424.bits.fast_int <= UInt<1>("h00") @[dec_decode_ctl.scala 495:27]
+    _T_424.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 495:27]
+    io.lsu_p.bits.store_data_bypass_m <= _T_424.bits.store_data_bypass_m @[dec_decode_ctl.scala 495:12]
+    io.lsu_p.bits.load_ldst_bypass_d <= _T_424.bits.load_ldst_bypass_d @[dec_decode_ctl.scala 495:12]
+    io.lsu_p.bits.store_data_bypass_d <= _T_424.bits.store_data_bypass_d @[dec_decode_ctl.scala 495:12]
+    io.lsu_p.bits.dma <= _T_424.bits.dma @[dec_decode_ctl.scala 495:12]
+    io.lsu_p.bits.unsign <= _T_424.bits.unsign @[dec_decode_ctl.scala 495:12]
+    io.lsu_p.bits.store <= _T_424.bits.store @[dec_decode_ctl.scala 495:12]
+    io.lsu_p.bits.load <= _T_424.bits.load @[dec_decode_ctl.scala 495:12]
+    io.lsu_p.bits.dword <= _T_424.bits.dword @[dec_decode_ctl.scala 495:12]
+    io.lsu_p.bits.word <= _T_424.bits.word @[dec_decode_ctl.scala 495:12]
+    io.lsu_p.bits.half <= _T_424.bits.half @[dec_decode_ctl.scala 495:12]
+    io.lsu_p.bits.by <= _T_424.bits.by @[dec_decode_ctl.scala 495:12]
+    io.lsu_p.bits.stack <= _T_424.bits.stack @[dec_decode_ctl.scala 495:12]
+    io.lsu_p.bits.fast_int <= _T_424.bits.fast_int @[dec_decode_ctl.scala 495:12]
+    io.lsu_p.valid <= _T_424.valid @[dec_decode_ctl.scala 495:12]
+    when io.decode_exu.dec_extint_stall : @[dec_decode_ctl.scala 496:40]
+      io.lsu_p.bits.load <= UInt<1>("h01") @[dec_decode_ctl.scala 497:29]
+      io.lsu_p.bits.word <= UInt<1>("h01") @[dec_decode_ctl.scala 498:29]
+      io.lsu_p.bits.fast_int <= UInt<1>("h01") @[dec_decode_ctl.scala 499:29]
+      io.lsu_p.valid <= UInt<1>("h01") @[dec_decode_ctl.scala 500:24]
+      skip @[dec_decode_ctl.scala 496:40]
+    else : @[dec_decode_ctl.scala 503:15]
+      io.lsu_p.valid <= lsu_decode_d @[dec_decode_ctl.scala 504:35]
+      io.lsu_p.bits.load <= i0_dp.load @[dec_decode_ctl.scala 505:40]
+      io.lsu_p.bits.store <= i0_dp.store @[dec_decode_ctl.scala 506:40]
+      io.lsu_p.bits.by <= i0_dp.by @[dec_decode_ctl.scala 507:40]
+      io.lsu_p.bits.half <= i0_dp.half @[dec_decode_ctl.scala 508:40]
+      io.lsu_p.bits.word <= i0_dp.word @[dec_decode_ctl.scala 509:40]
+      node _T_425 = eq(i0r.rs1, UInt<5>("h02")) @[dec_decode_ctl.scala 510:41]
+      io.lsu_p.bits.stack <= _T_425 @[dec_decode_ctl.scala 510:29]
+      io.lsu_p.bits.load_ldst_bypass_d <= load_ldst_bypass_d @[dec_decode_ctl.scala 511:40]
+      io.lsu_p.bits.store_data_bypass_d <= store_data_bypass_d @[dec_decode_ctl.scala 512:40]
+      io.lsu_p.bits.store_data_bypass_m <= store_data_bypass_m @[dec_decode_ctl.scala 513:40]
+      io.lsu_p.bits.unsign <= i0_dp.unsign @[dec_decode_ctl.scala 514:40]
+      skip @[dec_decode_ctl.scala 503:15]
+    node _T_426 = and(i0_dp.csr_read, io.dec_ib0_valid_d) @[dec_decode_ctl.scala 518:47]
+    io.dec_alu.dec_csr_ren_d <= _T_426 @[dec_decode_ctl.scala 518:29]
+    node _T_427 = bits(i0_legal_decode_d, 0, 0) @[dec_decode_ctl.scala 519:56]
+    node _T_428 = and(i0_dp.csr_read, _T_427) @[dec_decode_ctl.scala 519:36]
+    csr_read <= _T_428 @[dec_decode_ctl.scala 519:18]
+    node _T_429 = eq(io.dec_debug_fence_d, UInt<1>("h00")) @[dec_decode_ctl.scala 521:42]
+    node i0_csr_write = and(i0_dp.csr_write, _T_429) @[dec_decode_ctl.scala 521:40]
+    node _T_430 = bits(i0_legal_decode_d, 0, 0) @[dec_decode_ctl.scala 522:61]
+    node csr_clr_d = and(i0_dp.csr_clr, _T_430) @[dec_decode_ctl.scala 522:41]
+    node _T_431 = bits(i0_legal_decode_d, 0, 0) @[dec_decode_ctl.scala 523:59]
+    node csr_set_d = and(i0_dp.csr_set, _T_431) @[dec_decode_ctl.scala 523:39]
+    node _T_432 = bits(i0_legal_decode_d, 0, 0) @[dec_decode_ctl.scala 524:59]
+    node csr_write_d = and(i0_csr_write, _T_432) @[dec_decode_ctl.scala 524:39]
+    node _T_433 = eq(i0_dp.csr_read, UInt<1>("h00")) @[dec_decode_ctl.scala 526:41]
+    node _T_434 = and(i0_csr_write, _T_433) @[dec_decode_ctl.scala 526:39]
+    i0_csr_write_only_d <= _T_434 @[dec_decode_ctl.scala 526:23]
+    node _T_435 = or(i0_dp.csr_clr, i0_dp.csr_set) @[dec_decode_ctl.scala 527:42]
+    node _T_436 = or(_T_435, i0_csr_write) @[dec_decode_ctl.scala 527:58]
+    node _T_437 = and(_T_436, io.dec_ib0_valid_d) @[dec_decode_ctl.scala 527:74]
+    io.dec_csr_wen_unq_d <= _T_437 @[dec_decode_ctl.scala 527:24]
+    node any_csr_d = or(i0_dp.csr_read, i0_csr_write) @[dec_decode_ctl.scala 529:34]
+    node _T_438 = and(any_csr_d, io.dec_ib0_valid_d) @[dec_decode_ctl.scala 530:37]
+    io.dec_csr_any_unq_d <= _T_438 @[dec_decode_ctl.scala 530:24]
     node _T_439 = bits(io.dec_csr_any_unq_d, 0, 0) @[Bitwise.scala 72:15]
     node _T_440 = mux(_T_439, UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12]
-    node _T_441 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 529:62]
-    node _T_442 = and(_T_440, _T_441) @[dec_decode_ctl.scala 529:58]
-    io.dec_csr_rdaddr_d <= _T_442 @[dec_decode_ctl.scala 529:24]
-    node _T_443 = and(r_d.bits.csrwen, r_d.valid) @[dec_decode_ctl.scala 530:53]
+    node _T_441 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 531:62]
+    node _T_442 = and(_T_440, _T_441) @[dec_decode_ctl.scala 531:58]
+    io.dec_csr_rdaddr_d <= _T_442 @[dec_decode_ctl.scala 531:24]
+    node _T_443 = and(r_d.bits.csrwen, r_d.valid) @[dec_decode_ctl.scala 532:53]
     node _T_444 = bits(_T_443, 0, 0) @[Bitwise.scala 72:15]
     node _T_445 = mux(_T_444, UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12]
-    node _T_446 = and(_T_445, r_d.bits.csrwaddr) @[dec_decode_ctl.scala 530:67]
-    io.dec_csr_wraddr_r <= _T_446 @[dec_decode_ctl.scala 530:24]
-    node _T_447 = and(r_d.bits.csrwen, r_d.valid) @[dec_decode_ctl.scala 534:39]
-    node _T_448 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[dec_decode_ctl.scala 534:53]
-    node _T_449 = and(_T_447, _T_448) @[dec_decode_ctl.scala 534:51]
-    io.dec_csr_wen_r <= _T_449 @[dec_decode_ctl.scala 534:20]
-    node _T_450 = eq(r_d.bits.csrwaddr, UInt<10>("h0300")) @[dec_decode_ctl.scala 537:50]
-    node _T_451 = eq(r_d.bits.csrwaddr, UInt<10>("h0304")) @[dec_decode_ctl.scala 537:85]
-    node _T_452 = or(_T_450, _T_451) @[dec_decode_ctl.scala 537:64]
-    node _T_453 = and(_T_452, r_d.bits.csrwen) @[dec_decode_ctl.scala 537:100]
-    node _T_454 = and(_T_453, r_d.valid) @[dec_decode_ctl.scala 537:118]
-    node _T_455 = eq(io.dec_tlu_i0_kill_writeb_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 537:132]
-    node _T_456 = and(_T_454, _T_455) @[dec_decode_ctl.scala 537:130]
-    io.dec_csr_stall_int_ff <= _T_456 @[dec_decode_ctl.scala 537:27]
-    reg csr_read_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 539:52]
-    csr_read_x <= csr_read @[dec_decode_ctl.scala 539:52]
-    reg csr_clr_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 540:51]
-    csr_clr_x <= csr_clr_d @[dec_decode_ctl.scala 540:51]
-    reg csr_set_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 541:51]
-    csr_set_x <= csr_set_d @[dec_decode_ctl.scala 541:51]
-    reg csr_write_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 542:53]
-    csr_write_x <= csr_write_d @[dec_decode_ctl.scala 542:53]
-    reg csr_imm_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 543:51]
-    csr_imm_x <= i0_dp.csr_imm @[dec_decode_ctl.scala 543:51]
-    node _T_457 = bits(io.dec_i0_instr_d, 19, 15) @[dec_decode_ctl.scala 546:27]
-    node _T_458 = bits(any_csr_d, 0, 0) @[dec_decode_ctl.scala 546:60]
-    node _T_459 = and(i0_x_data_en, _T_458) @[dec_decode_ctl.scala 546:48]
+    node _T_446 = and(_T_445, r_d.bits.csrwaddr) @[dec_decode_ctl.scala 532:67]
+    io.dec_csr_wraddr_r <= _T_446 @[dec_decode_ctl.scala 532:24]
+    node _T_447 = and(r_d.bits.csrwen, r_d.valid) @[dec_decode_ctl.scala 536:39]
+    node _T_448 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[dec_decode_ctl.scala 536:53]
+    node _T_449 = and(_T_447, _T_448) @[dec_decode_ctl.scala 536:51]
+    io.dec_csr_wen_r <= _T_449 @[dec_decode_ctl.scala 536:20]
+    node _T_450 = eq(r_d.bits.csrwaddr, UInt<10>("h0300")) @[dec_decode_ctl.scala 539:50]
+    node _T_451 = eq(r_d.bits.csrwaddr, UInt<10>("h0304")) @[dec_decode_ctl.scala 539:85]
+    node _T_452 = or(_T_450, _T_451) @[dec_decode_ctl.scala 539:64]
+    node _T_453 = and(_T_452, r_d.bits.csrwen) @[dec_decode_ctl.scala 539:100]
+    node _T_454 = and(_T_453, r_d.valid) @[dec_decode_ctl.scala 539:118]
+    node _T_455 = eq(io.dec_tlu_i0_kill_writeb_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 539:132]
+    node _T_456 = and(_T_454, _T_455) @[dec_decode_ctl.scala 539:130]
+    io.dec_csr_stall_int_ff <= _T_456 @[dec_decode_ctl.scala 539:27]
+    reg csr_read_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 541:52]
+    csr_read_x <= csr_read @[dec_decode_ctl.scala 541:52]
+    reg csr_clr_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 542:51]
+    csr_clr_x <= csr_clr_d @[dec_decode_ctl.scala 542:51]
+    reg csr_set_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 543:51]
+    csr_set_x <= csr_set_d @[dec_decode_ctl.scala 543:51]
+    reg csr_write_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 544:53]
+    csr_write_x <= csr_write_d @[dec_decode_ctl.scala 544:53]
+    reg csr_imm_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 545:51]
+    csr_imm_x <= i0_dp.csr_imm @[dec_decode_ctl.scala 545:51]
+    node _T_457 = bits(io.dec_i0_instr_d, 19, 15) @[dec_decode_ctl.scala 548:27]
+    node _T_458 = bits(any_csr_d, 0, 0) @[dec_decode_ctl.scala 548:60]
+    node _T_459 = and(i0_x_data_en, _T_458) @[dec_decode_ctl.scala 548:48]
     node _T_460 = bits(_T_459, 0, 0) @[lib.scala 8:44]
     inst rvclkhdr of rvclkhdr @[lib.scala 404:23]
     rvclkhdr.clock <= clock
@@ -6446,8 +6446,8 @@ circuit dec :
     when _T_460 : @[Reg.scala 28:19]
       csrimm_x <= _T_457 @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    node _T_461 = bits(any_csr_d, 0, 0) @[dec_decode_ctl.scala 547:74]
-    node _T_462 = and(i0_x_data_en, _T_461) @[dec_decode_ctl.scala 547:62]
+    node _T_461 = bits(any_csr_d, 0, 0) @[dec_decode_ctl.scala 549:74]
+    node _T_462 = and(i0_x_data_en, _T_461) @[dec_decode_ctl.scala 549:62]
     node _T_463 = bits(_T_462, 0, 0) @[lib.scala 8:44]
     inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 404:23]
     rvclkhdr_1.clock <= clock
@@ -6459,7 +6459,7 @@ circuit dec :
     when _T_463 : @[Reg.scala 28:19]
       csr_rddata_x <= io.dec_csr_rddata_d @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    node _T_464 = bits(csr_imm_x, 0, 0) @[dec_decode_ctl.scala 550:15]
+    node _T_464 = bits(csr_imm_x, 0, 0) @[dec_decode_ctl.scala 552:15]
     wire _T_465 : UInt<1>[27] @[lib.scala 12:48]
     _T_465[0] <= UInt<1>("h00") @[lib.scala 12:48]
     _T_465[1] <= UInt<1>("h00") @[lib.scala 12:48]
@@ -6514,18 +6514,18 @@ circuit dec :
     node _T_489 = cat(_T_488, _T_465[24]) @[Cat.scala 29:58]
     node _T_490 = cat(_T_489, _T_465[25]) @[Cat.scala 29:58]
     node _T_491 = cat(_T_490, _T_465[26]) @[Cat.scala 29:58]
-    node _T_492 = bits(csrimm_x, 4, 0) @[dec_decode_ctl.scala 550:53]
+    node _T_492 = bits(csrimm_x, 4, 0) @[dec_decode_ctl.scala 552:53]
     node _T_493 = cat(_T_491, _T_492) @[Cat.scala 29:58]
-    node _T_494 = bits(csr_imm_x, 0, 0) @[dec_decode_ctl.scala 551:16]
-    node _T_495 = eq(_T_494, UInt<1>("h00")) @[dec_decode_ctl.scala 551:5]
+    node _T_494 = bits(csr_imm_x, 0, 0) @[dec_decode_ctl.scala 553:16]
+    node _T_495 = eq(_T_494, UInt<1>("h00")) @[dec_decode_ctl.scala 553:5]
     node _T_496 = mux(_T_464, _T_493, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_497 = mux(_T_495, io.decode_exu.exu_csr_rs1_x, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_498 = or(_T_496, _T_497) @[Mux.scala 27:72]
     wire csr_mask_x : UInt<32> @[Mux.scala 27:72]
     csr_mask_x <= _T_498 @[Mux.scala 27:72]
-    node _T_499 = not(csr_mask_x) @[dec_decode_ctl.scala 554:38]
-    node _T_500 = and(csr_rddata_x, _T_499) @[dec_decode_ctl.scala 554:35]
-    node _T_501 = or(csr_rddata_x, csr_mask_x) @[dec_decode_ctl.scala 555:35]
+    node _T_499 = not(csr_mask_x) @[dec_decode_ctl.scala 556:38]
+    node _T_500 = and(csr_rddata_x, _T_499) @[dec_decode_ctl.scala 556:35]
+    node _T_501 = or(csr_rddata_x, csr_mask_x) @[dec_decode_ctl.scala 557:35]
     node _T_502 = mux(csr_clr_x, _T_500, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_503 = mux(csr_set_x, _T_501, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_504 = mux(csr_write_x, csr_mask_x, UInt<1>("h00")) @[Mux.scala 27:72]
@@ -6533,33 +6533,33 @@ circuit dec :
     node _T_506 = or(_T_505, _T_504) @[Mux.scala 27:72]
     wire write_csr_data_x : UInt @[Mux.scala 27:72]
     write_csr_data_x <= _T_506 @[Mux.scala 27:72]
-    node _T_507 = eq(io.dec_tlu_flush_pause_r, UInt<1>("h00")) @[dec_decode_ctl.scala 558:49]
-    node _T_508 = and(io.dec_tlu_flush_lower_r, _T_507) @[dec_decode_ctl.scala 558:47]
+    node _T_507 = eq(io.dec_tlu_flush_pause_r, UInt<1>("h00")) @[dec_decode_ctl.scala 560:49]
+    node _T_508 = and(io.dec_tlu_flush_lower_r, _T_507) @[dec_decode_ctl.scala 560:47]
     node _T_509 = mux(UInt<1>("h00"), UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12]
-    node _T_510 = bits(write_csr_data, 0, 0) @[dec_decode_ctl.scala 558:145]
+    node _T_510 = bits(write_csr_data, 0, 0) @[dec_decode_ctl.scala 560:145]
     node _T_511 = cat(_T_509, _T_510) @[Cat.scala 29:58]
-    node _T_512 = eq(write_csr_data, _T_511) @[dec_decode_ctl.scala 558:109]
-    node _T_513 = and(pause_stall, _T_512) @[dec_decode_ctl.scala 558:91]
-    node clear_pause = or(_T_508, _T_513) @[dec_decode_ctl.scala 558:76]
-    node _T_514 = or(io.dec_tlu_wr_pause_r, pause_stall) @[dec_decode_ctl.scala 559:44]
-    node _T_515 = eq(clear_pause, UInt<1>("h00")) @[dec_decode_ctl.scala 559:61]
-    node _T_516 = and(_T_514, _T_515) @[dec_decode_ctl.scala 559:59]
-    pause_state_in <= _T_516 @[dec_decode_ctl.scala 559:18]
-    io.dec_pause_state <= pause_stall @[dec_decode_ctl.scala 560:22]
-    node _T_517 = eq(tlu_wr_pause_r1, UInt<1>("h00")) @[dec_decode_ctl.scala 562:44]
-    node _T_518 = eq(tlu_wr_pause_r2, UInt<1>("h00")) @[dec_decode_ctl.scala 562:64]
-    node _T_519 = and(_T_517, _T_518) @[dec_decode_ctl.scala 562:61]
-    node _T_520 = and(pause_stall, _T_519) @[dec_decode_ctl.scala 562:41]
-    io.dec_pause_state_cg <= _T_520 @[dec_decode_ctl.scala 562:25]
-    node _T_521 = sub(write_csr_data, UInt<32>("h01")) @[dec_decode_ctl.scala 565:59]
-    node _T_522 = tail(_T_521, 1) @[dec_decode_ctl.scala 565:59]
-    node _T_523 = mux(io.dec_tlu_wr_pause_r, io.dec_csr_wrdata_r, write_csr_data_x) @[dec_decode_ctl.scala 566:8]
-    node write_csr_data_in = mux(pause_stall, _T_522, _T_523) @[dec_decode_ctl.scala 565:30]
-    node _T_524 = or(csr_clr_x, csr_set_x) @[dec_decode_ctl.scala 567:34]
-    node _T_525 = or(_T_524, csr_write_x) @[dec_decode_ctl.scala 567:46]
-    node _T_526 = and(_T_525, csr_read_x) @[dec_decode_ctl.scala 567:61]
-    node _T_527 = or(_T_526, io.dec_tlu_wr_pause_r) @[dec_decode_ctl.scala 567:75]
-    node csr_data_wen = or(_T_527, pause_stall) @[dec_decode_ctl.scala 567:99]
+    node _T_512 = eq(write_csr_data, _T_511) @[dec_decode_ctl.scala 560:109]
+    node _T_513 = and(pause_stall, _T_512) @[dec_decode_ctl.scala 560:91]
+    node clear_pause = or(_T_508, _T_513) @[dec_decode_ctl.scala 560:76]
+    node _T_514 = or(io.dec_tlu_wr_pause_r, pause_stall) @[dec_decode_ctl.scala 561:44]
+    node _T_515 = eq(clear_pause, UInt<1>("h00")) @[dec_decode_ctl.scala 561:61]
+    node _T_516 = and(_T_514, _T_515) @[dec_decode_ctl.scala 561:59]
+    pause_state_in <= _T_516 @[dec_decode_ctl.scala 561:18]
+    io.dec_pause_state <= pause_stall @[dec_decode_ctl.scala 562:22]
+    node _T_517 = eq(tlu_wr_pause_r1, UInt<1>("h00")) @[dec_decode_ctl.scala 564:44]
+    node _T_518 = eq(tlu_wr_pause_r2, UInt<1>("h00")) @[dec_decode_ctl.scala 564:64]
+    node _T_519 = and(_T_517, _T_518) @[dec_decode_ctl.scala 564:61]
+    node _T_520 = and(pause_stall, _T_519) @[dec_decode_ctl.scala 564:41]
+    io.dec_pause_state_cg <= _T_520 @[dec_decode_ctl.scala 564:25]
+    node _T_521 = sub(write_csr_data, UInt<32>("h01")) @[dec_decode_ctl.scala 567:59]
+    node _T_522 = tail(_T_521, 1) @[dec_decode_ctl.scala 567:59]
+    node _T_523 = mux(io.dec_tlu_wr_pause_r, io.dec_csr_wrdata_r, write_csr_data_x) @[dec_decode_ctl.scala 568:8]
+    node write_csr_data_in = mux(pause_stall, _T_522, _T_523) @[dec_decode_ctl.scala 567:30]
+    node _T_524 = or(csr_clr_x, csr_set_x) @[dec_decode_ctl.scala 569:34]
+    node _T_525 = or(_T_524, csr_write_x) @[dec_decode_ctl.scala 569:46]
+    node _T_526 = and(_T_525, csr_read_x) @[dec_decode_ctl.scala 569:61]
+    node _T_527 = or(_T_526, io.dec_tlu_wr_pause_r) @[dec_decode_ctl.scala 569:75]
+    node csr_data_wen = or(_T_527, pause_stall) @[dec_decode_ctl.scala 569:99]
     inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 404:23]
     rvclkhdr_2.clock <= clock
     rvclkhdr_2.reset <= reset
@@ -6570,32 +6570,32 @@ circuit dec :
     when csr_data_wen : @[Reg.scala 28:19]
       _T_528 <= write_csr_data_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    write_csr_data <= _T_528 @[dec_decode_ctl.scala 568:18]
-    node _T_529 = and(r_d.bits.csrwonly, r_d.valid) @[dec_decode_ctl.scala 574:50]
-    node _T_530 = bits(_T_529, 0, 0) @[dec_decode_ctl.scala 574:63]
-    node _T_531 = mux(_T_530, i0_result_corr_r, write_csr_data) @[dec_decode_ctl.scala 574:30]
-    io.dec_csr_wrdata_r <= _T_531 @[dec_decode_ctl.scala 574:24]
-    node _T_532 = or(x_d.bits.csrwonly, r_d.bits.csrwonly) @[dec_decode_ctl.scala 576:43]
-    node prior_csr_write = or(_T_532, wbd.bits.csrwonly) @[dec_decode_ctl.scala 576:63]
-    node _T_533 = bits(io.dbg_dctl.dbg_cmd_wrdata, 0, 0) @[dec_decode_ctl.scala 578:76]
-    node debug_fence_i = and(io.dec_debug_fence_d, _T_533) @[dec_decode_ctl.scala 578:48]
-    node _T_534 = bits(io.dbg_dctl.dbg_cmd_wrdata, 1, 1) @[dec_decode_ctl.scala 579:76]
-    node debug_fence_raw = and(io.dec_debug_fence_d, _T_534) @[dec_decode_ctl.scala 579:48]
-    node _T_535 = or(debug_fence_raw, debug_fence_i) @[dec_decode_ctl.scala 580:40]
-    debug_fence <= _T_535 @[dec_decode_ctl.scala 580:21]
-    node _T_536 = or(i0_dp.presync, io.dec_tlu_presync_d) @[dec_decode_ctl.scala 583:34]
-    node _T_537 = or(_T_536, debug_fence_i) @[dec_decode_ctl.scala 583:57]
-    node _T_538 = or(_T_537, debug_fence_raw) @[dec_decode_ctl.scala 583:73]
-    node i0_presync = or(_T_538, io.dec_tlu_pipelining_disable) @[dec_decode_ctl.scala 583:91]
-    node _T_539 = or(i0_dp.postsync, io.dec_tlu_postsync_d) @[dec_decode_ctl.scala 586:36]
-    node _T_540 = or(_T_539, debug_fence_i) @[dec_decode_ctl.scala 586:60]
-    node _T_541 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 586:104]
-    node _T_542 = eq(_T_541, UInt<11>("h07c2")) @[dec_decode_ctl.scala 586:112]
-    node _T_543 = and(i0_csr_write_only_d, _T_542) @[dec_decode_ctl.scala 586:99]
-    node i0_postsync = or(_T_540, _T_543) @[dec_decode_ctl.scala 586:76]
-    node _T_544 = eq(any_csr_d, UInt<1>("h00")) @[dec_decode_ctl.scala 590:40]
-    node _T_545 = or(_T_544, io.dec_csr_legal_d) @[dec_decode_ctl.scala 590:51]
-    node i0_legal = and(i0_dp.legal, _T_545) @[dec_decode_ctl.scala 590:37]
+    write_csr_data <= _T_528 @[dec_decode_ctl.scala 570:18]
+    node _T_529 = and(r_d.bits.csrwonly, r_d.valid) @[dec_decode_ctl.scala 576:50]
+    node _T_530 = bits(_T_529, 0, 0) @[dec_decode_ctl.scala 576:63]
+    node _T_531 = mux(_T_530, i0_result_corr_r, write_csr_data) @[dec_decode_ctl.scala 576:30]
+    io.dec_csr_wrdata_r <= _T_531 @[dec_decode_ctl.scala 576:24]
+    node _T_532 = or(x_d.bits.csrwonly, r_d.bits.csrwonly) @[dec_decode_ctl.scala 578:43]
+    node prior_csr_write = or(_T_532, wbd.bits.csrwonly) @[dec_decode_ctl.scala 578:63]
+    node _T_533 = bits(io.dbg_dctl.dbg_cmd_wrdata, 0, 0) @[dec_decode_ctl.scala 580:76]
+    node debug_fence_i = and(io.dec_debug_fence_d, _T_533) @[dec_decode_ctl.scala 580:48]
+    node _T_534 = bits(io.dbg_dctl.dbg_cmd_wrdata, 1, 1) @[dec_decode_ctl.scala 581:76]
+    node debug_fence_raw = and(io.dec_debug_fence_d, _T_534) @[dec_decode_ctl.scala 581:48]
+    node _T_535 = or(debug_fence_raw, debug_fence_i) @[dec_decode_ctl.scala 582:40]
+    debug_fence <= _T_535 @[dec_decode_ctl.scala 582:21]
+    node _T_536 = or(i0_dp.presync, io.dec_tlu_presync_d) @[dec_decode_ctl.scala 585:34]
+    node _T_537 = or(_T_536, debug_fence_i) @[dec_decode_ctl.scala 585:57]
+    node _T_538 = or(_T_537, debug_fence_raw) @[dec_decode_ctl.scala 585:73]
+    node i0_presync = or(_T_538, io.dec_tlu_pipelining_disable) @[dec_decode_ctl.scala 585:91]
+    node _T_539 = or(i0_dp.postsync, io.dec_tlu_postsync_d) @[dec_decode_ctl.scala 588:36]
+    node _T_540 = or(_T_539, debug_fence_i) @[dec_decode_ctl.scala 588:60]
+    node _T_541 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 588:104]
+    node _T_542 = eq(_T_541, UInt<11>("h07c2")) @[dec_decode_ctl.scala 588:112]
+    node _T_543 = and(i0_csr_write_only_d, _T_542) @[dec_decode_ctl.scala 588:99]
+    node i0_postsync = or(_T_540, _T_543) @[dec_decode_ctl.scala 588:76]
+    node _T_544 = eq(any_csr_d, UInt<1>("h00")) @[dec_decode_ctl.scala 592:40]
+    node _T_545 = or(_T_544, io.dec_csr_legal_d) @[dec_decode_ctl.scala 592:51]
+    node i0_legal = and(i0_dp.legal, _T_545) @[dec_decode_ctl.scala 592:37]
     wire _T_546 : UInt<1>[16] @[lib.scala 12:48]
     _T_546[0] <= UInt<1>("h00") @[lib.scala 12:48]
     _T_546[1] <= UInt<1>("h00") @[lib.scala 12:48]
@@ -6629,11 +6629,11 @@ circuit dec :
     node _T_560 = cat(_T_559, _T_546[14]) @[Cat.scala 29:58]
     node _T_561 = cat(_T_560, _T_546[15]) @[Cat.scala 29:58]
     node _T_562 = cat(_T_561, io.dec_aln.ifu_i0_cinst) @[Cat.scala 29:58]
-    node i0_inst_d = mux(io.dec_i0_pc4_d, io.dec_i0_instr_d, _T_562) @[dec_decode_ctl.scala 591:27]
-    node _T_563 = eq(i0_legal, UInt<1>("h00")) @[dec_decode_ctl.scala 594:57]
-    node shift_illegal = and(io.dec_aln.dec_i0_decode_d, _T_563) @[dec_decode_ctl.scala 594:55]
-    node _T_564 = eq(illegal_lockout, UInt<1>("h00")) @[dec_decode_ctl.scala 595:44]
-    node illegal_inst_en = and(shift_illegal, _T_564) @[dec_decode_ctl.scala 595:42]
+    node i0_inst_d = mux(io.dec_i0_pc4_d, io.dec_i0_instr_d, _T_562) @[dec_decode_ctl.scala 593:27]
+    node _T_563 = eq(i0_legal, UInt<1>("h00")) @[dec_decode_ctl.scala 596:49]
+    node shift_illegal = and(io.dec_i0_decode_d, _T_563) @[dec_decode_ctl.scala 596:47]
+    node _T_564 = eq(illegal_lockout, UInt<1>("h00")) @[dec_decode_ctl.scala 597:44]
+    node illegal_inst_en = and(shift_illegal, _T_564) @[dec_decode_ctl.scala 597:42]
     inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 404:23]
     rvclkhdr_3.clock <= clock
     rvclkhdr_3.reset <= reset
@@ -6644,105 +6644,105 @@ circuit dec :
     when illegal_inst_en : @[Reg.scala 28:19]
       _T_565 <= i0_inst_d @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    io.dec_illegal_inst <= _T_565 @[dec_decode_ctl.scala 596:23]
-    node _T_566 = or(shift_illegal, illegal_lockout) @[dec_decode_ctl.scala 597:40]
-    node _T_567 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 597:61]
-    node _T_568 = and(_T_566, _T_567) @[dec_decode_ctl.scala 597:59]
-    illegal_lockout_in <= _T_568 @[dec_decode_ctl.scala 597:22]
-    node i0_div_prior_div_stall = and(i0_dp.div, io.dec_div_active) @[dec_decode_ctl.scala 598:42]
-    node _T_569 = and(i0_dp.csr_read, prior_csr_write) @[dec_decode_ctl.scala 600:40]
-    node _T_570 = or(_T_569, io.decode_exu.dec_extint_stall) @[dec_decode_ctl.scala 600:59]
-    node _T_571 = or(_T_570, pause_stall) @[dec_decode_ctl.scala 600:92]
-    node _T_572 = or(_T_571, leak1_i0_stall) @[dec_decode_ctl.scala 600:106]
-    node _T_573 = or(_T_572, io.dec_tlu_debug_stall) @[dec_decode_ctl.scala 601:20]
-    node _T_574 = or(_T_573, postsync_stall) @[dec_decode_ctl.scala 601:45]
-    node _T_575 = or(_T_574, presync_stall) @[dec_decode_ctl.scala 601:62]
-    node _T_576 = or(i0_dp.fence, debug_fence) @[dec_decode_ctl.scala 602:19]
-    node _T_577 = eq(lsu_idle, UInt<1>("h00")) @[dec_decode_ctl.scala 602:36]
-    node _T_578 = and(_T_576, _T_577) @[dec_decode_ctl.scala 602:34]
-    node _T_579 = or(_T_575, _T_578) @[dec_decode_ctl.scala 601:79]
-    node _T_580 = or(_T_579, i0_nonblock_load_stall) @[dec_decode_ctl.scala 602:47]
-    node _T_581 = or(_T_580, i0_load_block_d) @[dec_decode_ctl.scala 602:72]
-    node _T_582 = or(_T_581, i0_nonblock_div_stall) @[dec_decode_ctl.scala 603:21]
-    node i0_block_raw_d = or(_T_582, i0_div_prior_div_stall) @[dec_decode_ctl.scala 603:45]
-    node _T_583 = or(io.lsu_store_stall_any, io.dctl_dma.dma_dccm_stall_any) @[dec_decode_ctl.scala 605:65]
-    node i0_store_stall_d = and(i0_dp.store, _T_583) @[dec_decode_ctl.scala 605:39]
-    node _T_584 = or(io.lsu_load_stall_any, io.dctl_dma.dma_dccm_stall_any) @[dec_decode_ctl.scala 606:63]
-    node i0_load_stall_d = and(i0_dp.load, _T_584) @[dec_decode_ctl.scala 606:38]
-    node _T_585 = or(i0_block_raw_d, i0_store_stall_d) @[dec_decode_ctl.scala 607:38]
-    node i0_block_d = or(_T_585, i0_load_stall_d) @[dec_decode_ctl.scala 607:57]
-    node _T_586 = eq(i0_block_d, UInt<1>("h00")) @[dec_decode_ctl.scala 611:54]
-    node _T_587 = and(io.dec_ib0_valid_d, _T_586) @[dec_decode_ctl.scala 611:52]
-    node _T_588 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 611:71]
-    node _T_589 = and(_T_587, _T_588) @[dec_decode_ctl.scala 611:69]
-    node _T_590 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 611:99]
-    node _T_591 = and(_T_589, _T_590) @[dec_decode_ctl.scala 611:97]
-    io.dec_aln.dec_i0_decode_d <= _T_591 @[dec_decode_ctl.scala 611:30]
-    node _T_592 = eq(i0_block_raw_d, UInt<1>("h00")) @[dec_decode_ctl.scala 612:46]
-    node _T_593 = and(io.dec_ib0_valid_d, _T_592) @[dec_decode_ctl.scala 612:44]
-    node _T_594 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 612:63]
-    node _T_595 = and(_T_593, _T_594) @[dec_decode_ctl.scala 612:61]
-    node _T_596 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 612:91]
-    node i0_exudecode_d = and(_T_595, _T_596) @[dec_decode_ctl.scala 612:89]
-    node i0_exulegal_decode_d = and(i0_exudecode_d, i0_legal) @[dec_decode_ctl.scala 613:46]
-    io.dec_pmu_instr_decoded <= io.dec_aln.dec_i0_decode_d @[dec_decode_ctl.scala 616:28]
-    node _T_597 = eq(io.dec_aln.dec_i0_decode_d, UInt<1>("h00")) @[dec_decode_ctl.scala 617:51]
-    node _T_598 = and(io.dec_ib0_valid_d, _T_597) @[dec_decode_ctl.scala 617:49]
-    io.dec_pmu_decode_stall <= _T_598 @[dec_decode_ctl.scala 617:27]
-    node _T_599 = bits(postsync_stall, 0, 0) @[dec_decode_ctl.scala 618:47]
-    node _T_600 = and(_T_599, io.dec_ib0_valid_d) @[dec_decode_ctl.scala 618:54]
-    io.dec_pmu_postsync_stall <= _T_600 @[dec_decode_ctl.scala 618:29]
-    node _T_601 = bits(presync_stall, 0, 0) @[dec_decode_ctl.scala 619:46]
-    node _T_602 = and(_T_601, io.dec_ib0_valid_d) @[dec_decode_ctl.scala 619:53]
-    io.dec_pmu_presync_stall <= _T_602 @[dec_decode_ctl.scala 619:29]
-    node prior_inflight = or(x_d.valid, r_d.valid) @[dec_decode_ctl.scala 623:41]
-    node prior_inflight_eff = mux(i0_dp.div, x_d.valid, prior_inflight) @[dec_decode_ctl.scala 624:31]
-    node _T_603 = and(i0_presync, prior_inflight_eff) @[dec_decode_ctl.scala 626:37]
-    presync_stall <= _T_603 @[dec_decode_ctl.scala 626:22]
-    node _T_604 = eq(i0_legal, UInt<1>("h00")) @[dec_decode_ctl.scala 628:64]
-    node _T_605 = or(i0_postsync, _T_604) @[dec_decode_ctl.scala 628:62]
-    node _T_606 = and(io.dec_aln.dec_i0_decode_d, _T_605) @[dec_decode_ctl.scala 628:47]
-    node _T_607 = and(postsync_stall, x_d.valid) @[dec_decode_ctl.scala 628:96]
-    node _T_608 = or(_T_606, _T_607) @[dec_decode_ctl.scala 628:77]
-    ps_stall_in <= _T_608 @[dec_decode_ctl.scala 628:15]
-    node _T_609 = and(i0_exulegal_decode_d, i0_dp.alu) @[dec_decode_ctl.scala 630:58]
-    io.dec_alu.dec_i0_alu_decode_d <= _T_609 @[dec_decode_ctl.scala 630:34]
-    node _T_610 = or(i0_dp.condbr, i0_dp.jal) @[dec_decode_ctl.scala 631:53]
-    node _T_611 = or(_T_610, i0_br_error_all) @[dec_decode_ctl.scala 631:65]
-    io.decode_exu.dec_i0_branch_d <= _T_611 @[dec_decode_ctl.scala 631:37]
-    node _T_612 = and(i0_legal_decode_d, i0_dp.lsu) @[dec_decode_ctl.scala 633:40]
-    lsu_decode_d <= _T_612 @[dec_decode_ctl.scala 633:16]
-    node _T_613 = and(i0_exulegal_decode_d, i0_dp.mul) @[dec_decode_ctl.scala 634:40]
-    mul_decode_d <= _T_613 @[dec_decode_ctl.scala 634:16]
-    node _T_614 = and(i0_exulegal_decode_d, i0_dp.div) @[dec_decode_ctl.scala 635:40]
-    div_decode_d <= _T_614 @[dec_decode_ctl.scala 635:16]
-    io.decode_exu.dec_qual_lsu_d <= i0_dp.lsu @[dec_decode_ctl.scala 636:32]
-    node _T_615 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 637:45]
-    node _T_616 = and(r_d.valid, _T_615) @[dec_decode_ctl.scala 637:43]
-    io.dec_tlu_i0_valid_r <= _T_616 @[dec_decode_ctl.scala 637:29]
-    d_t.legal <= i0_legal_decode_d @[dec_decode_ctl.scala 640:26]
-    node _T_617 = and(i0_icaf_d, i0_legal_decode_d) @[dec_decode_ctl.scala 641:40]
-    d_t.icaf <= _T_617 @[dec_decode_ctl.scala 641:26]
-    node _T_618 = and(io.dec_i0_icaf_second_d, i0_legal_decode_d) @[dec_decode_ctl.scala 642:58]
-    d_t.icaf_second <= _T_618 @[dec_decode_ctl.scala 642:30]
-    d_t.icaf_type <= io.dec_i0_icaf_type_d @[dec_decode_ctl.scala 643:26]
-    node _T_619 = or(i0_dp.fence_i, debug_fence_i) @[dec_decode_ctl.scala 645:44]
-    node _T_620 = and(_T_619, i0_legal_decode_d) @[dec_decode_ctl.scala 645:61]
-    d_t.fence_i <= _T_620 @[dec_decode_ctl.scala 645:26]
-    d_t.pmu_i0_br_unpred <= i0_br_unpred @[dec_decode_ctl.scala 648:26]
-    d_t.pmu_divide <= UInt<1>("h00") @[dec_decode_ctl.scala 649:26]
-    d_t.pmu_lsu_misaligned <= UInt<1>("h00") @[dec_decode_ctl.scala 650:26]
+    io.dec_illegal_inst <= _T_565 @[dec_decode_ctl.scala 598:23]
+    node _T_566 = or(shift_illegal, illegal_lockout) @[dec_decode_ctl.scala 599:40]
+    node _T_567 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 599:61]
+    node _T_568 = and(_T_566, _T_567) @[dec_decode_ctl.scala 599:59]
+    illegal_lockout_in <= _T_568 @[dec_decode_ctl.scala 599:22]
+    node i0_div_prior_div_stall = and(i0_dp.div, io.dec_div_active) @[dec_decode_ctl.scala 600:42]
+    node _T_569 = and(i0_dp.csr_read, prior_csr_write) @[dec_decode_ctl.scala 602:40]
+    node _T_570 = or(_T_569, io.decode_exu.dec_extint_stall) @[dec_decode_ctl.scala 602:59]
+    node _T_571 = or(_T_570, pause_stall) @[dec_decode_ctl.scala 602:92]
+    node _T_572 = or(_T_571, leak1_i0_stall) @[dec_decode_ctl.scala 602:106]
+    node _T_573 = or(_T_572, io.dec_tlu_debug_stall) @[dec_decode_ctl.scala 603:20]
+    node _T_574 = or(_T_573, postsync_stall) @[dec_decode_ctl.scala 603:45]
+    node _T_575 = or(_T_574, presync_stall) @[dec_decode_ctl.scala 603:62]
+    node _T_576 = or(i0_dp.fence, debug_fence) @[dec_decode_ctl.scala 604:19]
+    node _T_577 = eq(lsu_idle, UInt<1>("h00")) @[dec_decode_ctl.scala 604:36]
+    node _T_578 = and(_T_576, _T_577) @[dec_decode_ctl.scala 604:34]
+    node _T_579 = or(_T_575, _T_578) @[dec_decode_ctl.scala 603:79]
+    node _T_580 = or(_T_579, i0_nonblock_load_stall) @[dec_decode_ctl.scala 604:47]
+    node _T_581 = or(_T_580, i0_load_block_d) @[dec_decode_ctl.scala 604:72]
+    node _T_582 = or(_T_581, i0_nonblock_div_stall) @[dec_decode_ctl.scala 605:21]
+    node i0_block_raw_d = or(_T_582, i0_div_prior_div_stall) @[dec_decode_ctl.scala 605:45]
+    node _T_583 = or(io.lsu_store_stall_any, io.dctl_dma.dma_dccm_stall_any) @[dec_decode_ctl.scala 607:65]
+    node i0_store_stall_d = and(i0_dp.store, _T_583) @[dec_decode_ctl.scala 607:39]
+    node _T_584 = or(io.lsu_load_stall_any, io.dctl_dma.dma_dccm_stall_any) @[dec_decode_ctl.scala 608:63]
+    node i0_load_stall_d = and(i0_dp.load, _T_584) @[dec_decode_ctl.scala 608:38]
+    node _T_585 = or(i0_block_raw_d, i0_store_stall_d) @[dec_decode_ctl.scala 609:38]
+    node i0_block_d = or(_T_585, i0_load_stall_d) @[dec_decode_ctl.scala 609:57]
+    node _T_586 = eq(i0_block_d, UInt<1>("h00")) @[dec_decode_ctl.scala 613:46]
+    node _T_587 = and(io.dec_ib0_valid_d, _T_586) @[dec_decode_ctl.scala 613:44]
+    node _T_588 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 613:63]
+    node _T_589 = and(_T_587, _T_588) @[dec_decode_ctl.scala 613:61]
+    node _T_590 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 613:91]
+    node _T_591 = and(_T_589, _T_590) @[dec_decode_ctl.scala 613:89]
+    io.dec_i0_decode_d <= _T_591 @[dec_decode_ctl.scala 613:22]
+    node _T_592 = eq(i0_block_raw_d, UInt<1>("h00")) @[dec_decode_ctl.scala 614:46]
+    node _T_593 = and(io.dec_ib0_valid_d, _T_592) @[dec_decode_ctl.scala 614:44]
+    node _T_594 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 614:63]
+    node _T_595 = and(_T_593, _T_594) @[dec_decode_ctl.scala 614:61]
+    node _T_596 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 614:91]
+    node i0_exudecode_d = and(_T_595, _T_596) @[dec_decode_ctl.scala 614:89]
+    node i0_exulegal_decode_d = and(i0_exudecode_d, i0_legal) @[dec_decode_ctl.scala 615:46]
+    io.dec_pmu_instr_decoded <= io.dec_i0_decode_d @[dec_decode_ctl.scala 618:28]
+    node _T_597 = eq(io.dec_i0_decode_d, UInt<1>("h00")) @[dec_decode_ctl.scala 619:51]
+    node _T_598 = and(io.dec_ib0_valid_d, _T_597) @[dec_decode_ctl.scala 619:49]
+    io.dec_pmu_decode_stall <= _T_598 @[dec_decode_ctl.scala 619:27]
+    node _T_599 = bits(postsync_stall, 0, 0) @[dec_decode_ctl.scala 620:47]
+    node _T_600 = and(_T_599, io.dec_ib0_valid_d) @[dec_decode_ctl.scala 620:54]
+    io.dec_pmu_postsync_stall <= _T_600 @[dec_decode_ctl.scala 620:29]
+    node _T_601 = bits(presync_stall, 0, 0) @[dec_decode_ctl.scala 621:46]
+    node _T_602 = and(_T_601, io.dec_ib0_valid_d) @[dec_decode_ctl.scala 621:53]
+    io.dec_pmu_presync_stall <= _T_602 @[dec_decode_ctl.scala 621:29]
+    node prior_inflight = or(x_d.valid, r_d.valid) @[dec_decode_ctl.scala 625:41]
+    node prior_inflight_eff = mux(i0_dp.div, x_d.valid, prior_inflight) @[dec_decode_ctl.scala 626:31]
+    node _T_603 = and(i0_presync, prior_inflight_eff) @[dec_decode_ctl.scala 628:37]
+    presync_stall <= _T_603 @[dec_decode_ctl.scala 628:22]
+    node _T_604 = eq(i0_legal, UInt<1>("h00")) @[dec_decode_ctl.scala 630:56]
+    node _T_605 = or(i0_postsync, _T_604) @[dec_decode_ctl.scala 630:54]
+    node _T_606 = and(io.dec_i0_decode_d, _T_605) @[dec_decode_ctl.scala 630:39]
+    node _T_607 = and(postsync_stall, x_d.valid) @[dec_decode_ctl.scala 630:88]
+    node _T_608 = or(_T_606, _T_607) @[dec_decode_ctl.scala 630:69]
+    ps_stall_in <= _T_608 @[dec_decode_ctl.scala 630:15]
+    node _T_609 = and(i0_exulegal_decode_d, i0_dp.alu) @[dec_decode_ctl.scala 632:58]
+    io.dec_alu.dec_i0_alu_decode_d <= _T_609 @[dec_decode_ctl.scala 632:34]
+    node _T_610 = or(i0_dp.condbr, i0_dp.jal) @[dec_decode_ctl.scala 633:53]
+    node _T_611 = or(_T_610, i0_br_error_all) @[dec_decode_ctl.scala 633:65]
+    io.decode_exu.dec_i0_branch_d <= _T_611 @[dec_decode_ctl.scala 633:37]
+    node _T_612 = and(i0_legal_decode_d, i0_dp.lsu) @[dec_decode_ctl.scala 635:40]
+    lsu_decode_d <= _T_612 @[dec_decode_ctl.scala 635:16]
+    node _T_613 = and(i0_exulegal_decode_d, i0_dp.mul) @[dec_decode_ctl.scala 636:40]
+    mul_decode_d <= _T_613 @[dec_decode_ctl.scala 636:16]
+    node _T_614 = and(i0_exulegal_decode_d, i0_dp.div) @[dec_decode_ctl.scala 637:40]
+    div_decode_d <= _T_614 @[dec_decode_ctl.scala 637:16]
+    io.decode_exu.dec_qual_lsu_d <= i0_dp.lsu @[dec_decode_ctl.scala 638:32]
+    node _T_615 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 639:45]
+    node _T_616 = and(r_d.valid, _T_615) @[dec_decode_ctl.scala 639:43]
+    io.dec_tlu_i0_valid_r <= _T_616 @[dec_decode_ctl.scala 639:29]
+    d_t.legal <= i0_legal_decode_d @[dec_decode_ctl.scala 642:26]
+    node _T_617 = and(i0_icaf_d, i0_legal_decode_d) @[dec_decode_ctl.scala 643:40]
+    d_t.icaf <= _T_617 @[dec_decode_ctl.scala 643:26]
+    node _T_618 = and(io.dec_i0_icaf_second_d, i0_legal_decode_d) @[dec_decode_ctl.scala 644:58]
+    d_t.icaf_second <= _T_618 @[dec_decode_ctl.scala 644:30]
+    d_t.icaf_type <= io.dec_i0_icaf_type_d @[dec_decode_ctl.scala 645:26]
+    node _T_619 = or(i0_dp.fence_i, debug_fence_i) @[dec_decode_ctl.scala 647:44]
+    node _T_620 = and(_T_619, i0_legal_decode_d) @[dec_decode_ctl.scala 647:61]
+    d_t.fence_i <= _T_620 @[dec_decode_ctl.scala 647:26]
+    d_t.pmu_i0_br_unpred <= i0_br_unpred @[dec_decode_ctl.scala 650:26]
+    d_t.pmu_divide <= UInt<1>("h00") @[dec_decode_ctl.scala 651:26]
+    d_t.pmu_lsu_misaligned <= UInt<1>("h00") @[dec_decode_ctl.scala 652:26]
     wire _T_621 : UInt<1>[4] @[lib.scala 12:48]
-    _T_621[0] <= io.dec_aln.dec_i0_decode_d @[lib.scala 12:48]
-    _T_621[1] <= io.dec_aln.dec_i0_decode_d @[lib.scala 12:48]
-    _T_621[2] <= io.dec_aln.dec_i0_decode_d @[lib.scala 12:48]
-    _T_621[3] <= io.dec_aln.dec_i0_decode_d @[lib.scala 12:48]
+    _T_621[0] <= io.dec_i0_decode_d @[lib.scala 12:48]
+    _T_621[1] <= io.dec_i0_decode_d @[lib.scala 12:48]
+    _T_621[2] <= io.dec_i0_decode_d @[lib.scala 12:48]
+    _T_621[3] <= io.dec_i0_decode_d @[lib.scala 12:48]
     node _T_622 = cat(_T_621[0], _T_621[1]) @[Cat.scala 29:58]
     node _T_623 = cat(_T_622, _T_621[2]) @[Cat.scala 29:58]
     node _T_624 = cat(_T_623, _T_621[3]) @[Cat.scala 29:58]
-    node _T_625 = and(io.dec_i0_trigger_match_d, _T_624) @[dec_decode_ctl.scala 652:56]
-    d_t.i0trigger <= _T_625 @[dec_decode_ctl.scala 652:26]
-    node _T_626 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 655:60]
+    node _T_625 = and(io.dec_i0_trigger_match_d, _T_624) @[dec_decode_ctl.scala 654:56]
+    d_t.i0trigger <= _T_625 @[dec_decode_ctl.scala 654:26]
+    node _T_626 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 657:60]
     wire _T_627 : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[lib.scala 630:37]
     _T_627.pmu_lsu_misaligned <= UInt<1>("h00") @[lib.scala 630:37]
     _T_627.pmu_divide <= UInt<1>("h00") @[lib.scala 630:37]
@@ -6767,26 +6767,26 @@ circuit dec :
       _T_628.icaf <= d_t.icaf @[Reg.scala 28:23]
       _T_628.legal <= d_t.legal @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    x_t.pmu_lsu_misaligned <= _T_628.pmu_lsu_misaligned @[dec_decode_ctl.scala 655:7]
-    x_t.pmu_divide <= _T_628.pmu_divide @[dec_decode_ctl.scala 655:7]
-    x_t.pmu_i0_br_unpred <= _T_628.pmu_i0_br_unpred @[dec_decode_ctl.scala 655:7]
-    x_t.pmu_i0_itype <= _T_628.pmu_i0_itype @[dec_decode_ctl.scala 655:7]
-    x_t.i0trigger <= _T_628.i0trigger @[dec_decode_ctl.scala 655:7]
-    x_t.fence_i <= _T_628.fence_i @[dec_decode_ctl.scala 655:7]
-    x_t.icaf_type <= _T_628.icaf_type @[dec_decode_ctl.scala 655:7]
-    x_t.icaf_second <= _T_628.icaf_second @[dec_decode_ctl.scala 655:7]
-    x_t.icaf <= _T_628.icaf @[dec_decode_ctl.scala 655:7]
-    x_t.legal <= _T_628.legal @[dec_decode_ctl.scala 655:7]
-    x_t_in.pmu_lsu_misaligned <= x_t.pmu_lsu_misaligned @[dec_decode_ctl.scala 657:10]
-    x_t_in.pmu_divide <= x_t.pmu_divide @[dec_decode_ctl.scala 657:10]
-    x_t_in.pmu_i0_br_unpred <= x_t.pmu_i0_br_unpred @[dec_decode_ctl.scala 657:10]
-    x_t_in.pmu_i0_itype <= x_t.pmu_i0_itype @[dec_decode_ctl.scala 657:10]
-    x_t_in.i0trigger <= x_t.i0trigger @[dec_decode_ctl.scala 657:10]
-    x_t_in.fence_i <= x_t.fence_i @[dec_decode_ctl.scala 657:10]
-    x_t_in.icaf_type <= x_t.icaf_type @[dec_decode_ctl.scala 657:10]
-    x_t_in.icaf_second <= x_t.icaf_second @[dec_decode_ctl.scala 657:10]
-    x_t_in.icaf <= x_t.icaf @[dec_decode_ctl.scala 657:10]
-    x_t_in.legal <= x_t.legal @[dec_decode_ctl.scala 657:10]
+    x_t.pmu_lsu_misaligned <= _T_628.pmu_lsu_misaligned @[dec_decode_ctl.scala 657:7]
+    x_t.pmu_divide <= _T_628.pmu_divide @[dec_decode_ctl.scala 657:7]
+    x_t.pmu_i0_br_unpred <= _T_628.pmu_i0_br_unpred @[dec_decode_ctl.scala 657:7]
+    x_t.pmu_i0_itype <= _T_628.pmu_i0_itype @[dec_decode_ctl.scala 657:7]
+    x_t.i0trigger <= _T_628.i0trigger @[dec_decode_ctl.scala 657:7]
+    x_t.fence_i <= _T_628.fence_i @[dec_decode_ctl.scala 657:7]
+    x_t.icaf_type <= _T_628.icaf_type @[dec_decode_ctl.scala 657:7]
+    x_t.icaf_second <= _T_628.icaf_second @[dec_decode_ctl.scala 657:7]
+    x_t.icaf <= _T_628.icaf @[dec_decode_ctl.scala 657:7]
+    x_t.legal <= _T_628.legal @[dec_decode_ctl.scala 657:7]
+    x_t_in.pmu_lsu_misaligned <= x_t.pmu_lsu_misaligned @[dec_decode_ctl.scala 659:10]
+    x_t_in.pmu_divide <= x_t.pmu_divide @[dec_decode_ctl.scala 659:10]
+    x_t_in.pmu_i0_br_unpred <= x_t.pmu_i0_br_unpred @[dec_decode_ctl.scala 659:10]
+    x_t_in.pmu_i0_itype <= x_t.pmu_i0_itype @[dec_decode_ctl.scala 659:10]
+    x_t_in.i0trigger <= x_t.i0trigger @[dec_decode_ctl.scala 659:10]
+    x_t_in.fence_i <= x_t.fence_i @[dec_decode_ctl.scala 659:10]
+    x_t_in.icaf_type <= x_t.icaf_type @[dec_decode_ctl.scala 659:10]
+    x_t_in.icaf_second <= x_t.icaf_second @[dec_decode_ctl.scala 659:10]
+    x_t_in.icaf <= x_t.icaf @[dec_decode_ctl.scala 659:10]
+    x_t_in.legal <= x_t.legal @[dec_decode_ctl.scala 659:10]
     wire _T_629 : UInt<1>[4] @[lib.scala 12:48]
     _T_629[0] <= io.dec_tlu_flush_lower_wb @[lib.scala 12:48]
     _T_629[1] <= io.dec_tlu_flush_lower_wb @[lib.scala 12:48]
@@ -6795,10 +6795,10 @@ circuit dec :
     node _T_630 = cat(_T_629[0], _T_629[1]) @[Cat.scala 29:58]
     node _T_631 = cat(_T_630, _T_629[2]) @[Cat.scala 29:58]
     node _T_632 = cat(_T_631, _T_629[3]) @[Cat.scala 29:58]
-    node _T_633 = not(_T_632) @[dec_decode_ctl.scala 658:39]
-    node _T_634 = and(x_t.i0trigger, _T_633) @[dec_decode_ctl.scala 658:37]
-    x_t_in.i0trigger <= _T_634 @[dec_decode_ctl.scala 658:20]
-    node _T_635 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 660:63]
+    node _T_633 = not(_T_632) @[dec_decode_ctl.scala 660:39]
+    node _T_634 = and(x_t.i0trigger, _T_633) @[dec_decode_ctl.scala 660:37]
+    x_t_in.i0trigger <= _T_634 @[dec_decode_ctl.scala 660:20]
+    node _T_635 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 662:63]
     wire _T_636 : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[lib.scala 630:37]
     _T_636.pmu_lsu_misaligned <= UInt<1>("h00") @[lib.scala 630:37]
     _T_636.pmu_divide <= UInt<1>("h00") @[lib.scala 630:37]
@@ -6823,27 +6823,27 @@ circuit dec :
       _T_637.icaf <= x_t_in.icaf @[Reg.scala 28:23]
       _T_637.legal <= x_t_in.legal @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    r_t.pmu_lsu_misaligned <= _T_637.pmu_lsu_misaligned @[dec_decode_ctl.scala 660:7]
-    r_t.pmu_divide <= _T_637.pmu_divide @[dec_decode_ctl.scala 660:7]
-    r_t.pmu_i0_br_unpred <= _T_637.pmu_i0_br_unpred @[dec_decode_ctl.scala 660:7]
-    r_t.pmu_i0_itype <= _T_637.pmu_i0_itype @[dec_decode_ctl.scala 660:7]
-    r_t.i0trigger <= _T_637.i0trigger @[dec_decode_ctl.scala 660:7]
-    r_t.fence_i <= _T_637.fence_i @[dec_decode_ctl.scala 660:7]
-    r_t.icaf_type <= _T_637.icaf_type @[dec_decode_ctl.scala 660:7]
-    r_t.icaf_second <= _T_637.icaf_second @[dec_decode_ctl.scala 660:7]
-    r_t.icaf <= _T_637.icaf @[dec_decode_ctl.scala 660:7]
-    r_t.legal <= _T_637.legal @[dec_decode_ctl.scala 660:7]
-    r_t_in.pmu_lsu_misaligned <= r_t.pmu_lsu_misaligned @[dec_decode_ctl.scala 662:10]
-    r_t_in.pmu_divide <= r_t.pmu_divide @[dec_decode_ctl.scala 662:10]
-    r_t_in.pmu_i0_br_unpred <= r_t.pmu_i0_br_unpred @[dec_decode_ctl.scala 662:10]
-    r_t_in.pmu_i0_itype <= r_t.pmu_i0_itype @[dec_decode_ctl.scala 662:10]
-    r_t_in.i0trigger <= r_t.i0trigger @[dec_decode_ctl.scala 662:10]
-    r_t_in.fence_i <= r_t.fence_i @[dec_decode_ctl.scala 662:10]
-    r_t_in.icaf_type <= r_t.icaf_type @[dec_decode_ctl.scala 662:10]
-    r_t_in.icaf_second <= r_t.icaf_second @[dec_decode_ctl.scala 662:10]
-    r_t_in.icaf <= r_t.icaf @[dec_decode_ctl.scala 662:10]
-    r_t_in.legal <= r_t.legal @[dec_decode_ctl.scala 662:10]
-    node _T_638 = or(r_d.bits.i0load, r_d.bits.i0store) @[dec_decode_ctl.scala 664:61]
+    r_t.pmu_lsu_misaligned <= _T_637.pmu_lsu_misaligned @[dec_decode_ctl.scala 662:7]
+    r_t.pmu_divide <= _T_637.pmu_divide @[dec_decode_ctl.scala 662:7]
+    r_t.pmu_i0_br_unpred <= _T_637.pmu_i0_br_unpred @[dec_decode_ctl.scala 662:7]
+    r_t.pmu_i0_itype <= _T_637.pmu_i0_itype @[dec_decode_ctl.scala 662:7]
+    r_t.i0trigger <= _T_637.i0trigger @[dec_decode_ctl.scala 662:7]
+    r_t.fence_i <= _T_637.fence_i @[dec_decode_ctl.scala 662:7]
+    r_t.icaf_type <= _T_637.icaf_type @[dec_decode_ctl.scala 662:7]
+    r_t.icaf_second <= _T_637.icaf_second @[dec_decode_ctl.scala 662:7]
+    r_t.icaf <= _T_637.icaf @[dec_decode_ctl.scala 662:7]
+    r_t.legal <= _T_637.legal @[dec_decode_ctl.scala 662:7]
+    r_t_in.pmu_lsu_misaligned <= r_t.pmu_lsu_misaligned @[dec_decode_ctl.scala 664:10]
+    r_t_in.pmu_divide <= r_t.pmu_divide @[dec_decode_ctl.scala 664:10]
+    r_t_in.pmu_i0_br_unpred <= r_t.pmu_i0_br_unpred @[dec_decode_ctl.scala 664:10]
+    r_t_in.pmu_i0_itype <= r_t.pmu_i0_itype @[dec_decode_ctl.scala 664:10]
+    r_t_in.i0trigger <= r_t.i0trigger @[dec_decode_ctl.scala 664:10]
+    r_t_in.fence_i <= r_t.fence_i @[dec_decode_ctl.scala 664:10]
+    r_t_in.icaf_type <= r_t.icaf_type @[dec_decode_ctl.scala 664:10]
+    r_t_in.icaf_second <= r_t.icaf_second @[dec_decode_ctl.scala 664:10]
+    r_t_in.icaf <= r_t.icaf @[dec_decode_ctl.scala 664:10]
+    r_t_in.legal <= r_t.legal @[dec_decode_ctl.scala 664:10]
+    node _T_638 = or(r_d.bits.i0load, r_d.bits.i0store) @[dec_decode_ctl.scala 666:61]
     wire _T_639 : UInt<1>[4] @[lib.scala 12:48]
     _T_639[0] <= _T_638 @[lib.scala 12:48]
     _T_639[1] <= _T_638 @[lib.scala 12:48]
@@ -6852,73 +6852,73 @@ circuit dec :
     node _T_640 = cat(_T_639[0], _T_639[1]) @[Cat.scala 29:58]
     node _T_641 = cat(_T_640, _T_639[2]) @[Cat.scala 29:58]
     node _T_642 = cat(_T_641, _T_639[3]) @[Cat.scala 29:58]
-    node _T_643 = and(_T_642, lsu_trigger_match_r) @[dec_decode_ctl.scala 664:82]
-    node _T_644 = or(_T_643, r_t.i0trigger) @[dec_decode_ctl.scala 664:105]
-    r_t_in.i0trigger <= _T_644 @[dec_decode_ctl.scala 664:33]
-    r_t_in.pmu_lsu_misaligned <= lsu_pmu_misaligned_r @[dec_decode_ctl.scala 665:33]
-    node _T_645 = bits(io.dec_tlu_flush_lower_wb, 0, 0) @[dec_decode_ctl.scala 667:35]
-    when _T_645 : @[dec_decode_ctl.scala 667:43]
-      wire _T_646 : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 667:66]
-      _T_646.pmu_lsu_misaligned <= UInt<1>("h00") @[dec_decode_ctl.scala 667:66]
-      _T_646.pmu_divide <= UInt<1>("h00") @[dec_decode_ctl.scala 667:66]
-      _T_646.pmu_i0_br_unpred <= UInt<1>("h00") @[dec_decode_ctl.scala 667:66]
-      _T_646.pmu_i0_itype <= UInt<4>("h00") @[dec_decode_ctl.scala 667:66]
-      _T_646.i0trigger <= UInt<4>("h00") @[dec_decode_ctl.scala 667:66]
-      _T_646.fence_i <= UInt<1>("h00") @[dec_decode_ctl.scala 667:66]
-      _T_646.icaf_type <= UInt<2>("h00") @[dec_decode_ctl.scala 667:66]
-      _T_646.icaf_second <= UInt<1>("h00") @[dec_decode_ctl.scala 667:66]
-      _T_646.icaf <= UInt<1>("h00") @[dec_decode_ctl.scala 667:66]
-      _T_646.legal <= UInt<1>("h00") @[dec_decode_ctl.scala 667:66]
-      r_t_in.pmu_lsu_misaligned <= _T_646.pmu_lsu_misaligned @[dec_decode_ctl.scala 667:51]
-      r_t_in.pmu_divide <= _T_646.pmu_divide @[dec_decode_ctl.scala 667:51]
-      r_t_in.pmu_i0_br_unpred <= _T_646.pmu_i0_br_unpred @[dec_decode_ctl.scala 667:51]
-      r_t_in.pmu_i0_itype <= _T_646.pmu_i0_itype @[dec_decode_ctl.scala 667:51]
-      r_t_in.i0trigger <= _T_646.i0trigger @[dec_decode_ctl.scala 667:51]
-      r_t_in.fence_i <= _T_646.fence_i @[dec_decode_ctl.scala 667:51]
-      r_t_in.icaf_type <= _T_646.icaf_type @[dec_decode_ctl.scala 667:51]
-      r_t_in.icaf_second <= _T_646.icaf_second @[dec_decode_ctl.scala 667:51]
-      r_t_in.icaf <= _T_646.icaf @[dec_decode_ctl.scala 667:51]
-      r_t_in.legal <= _T_646.legal @[dec_decode_ctl.scala 667:51]
-      skip @[dec_decode_ctl.scala 667:43]
-    io.dec_tlu_packet_r.pmu_lsu_misaligned <= r_t_in.pmu_lsu_misaligned @[dec_decode_ctl.scala 669:39]
-    io.dec_tlu_packet_r.pmu_divide <= r_t_in.pmu_divide @[dec_decode_ctl.scala 669:39]
-    io.dec_tlu_packet_r.pmu_i0_br_unpred <= r_t_in.pmu_i0_br_unpred @[dec_decode_ctl.scala 669:39]
-    io.dec_tlu_packet_r.pmu_i0_itype <= r_t_in.pmu_i0_itype @[dec_decode_ctl.scala 669:39]
-    io.dec_tlu_packet_r.i0trigger <= r_t_in.i0trigger @[dec_decode_ctl.scala 669:39]
-    io.dec_tlu_packet_r.fence_i <= r_t_in.fence_i @[dec_decode_ctl.scala 669:39]
-    io.dec_tlu_packet_r.icaf_type <= r_t_in.icaf_type @[dec_decode_ctl.scala 669:39]
-    io.dec_tlu_packet_r.icaf_second <= r_t_in.icaf_second @[dec_decode_ctl.scala 669:39]
-    io.dec_tlu_packet_r.icaf <= r_t_in.icaf @[dec_decode_ctl.scala 669:39]
-    io.dec_tlu_packet_r.legal <= r_t_in.legal @[dec_decode_ctl.scala 669:39]
-    node _T_647 = and(r_d.bits.i0div, r_d.valid) @[dec_decode_ctl.scala 670:58]
-    io.dec_tlu_packet_r.pmu_divide <= _T_647 @[dec_decode_ctl.scala 670:39]
-    node _T_648 = eq(i0_block_d, UInt<1>("h00")) @[dec_decode_ctl.scala 674:54]
-    node _T_649 = and(io.dec_ib0_valid_d, _T_648) @[dec_decode_ctl.scala 674:52]
-    node _T_650 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 674:68]
-    node _T_651 = and(_T_649, _T_650) @[dec_decode_ctl.scala 674:66]
-    node _T_652 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 674:96]
-    node _T_653 = and(_T_651, _T_652) @[dec_decode_ctl.scala 674:94]
-    io.dec_aln.dec_i0_decode_d <= _T_653 @[dec_decode_ctl.scala 674:30]
-    node _T_654 = bits(io.dec_i0_instr_d, 19, 15) @[dec_decode_ctl.scala 676:16]
-    i0r.rs1 <= _T_654 @[dec_decode_ctl.scala 676:11]
-    node _T_655 = bits(io.dec_i0_instr_d, 24, 20) @[dec_decode_ctl.scala 677:16]
-    i0r.rs2 <= _T_655 @[dec_decode_ctl.scala 677:11]
-    node _T_656 = bits(io.dec_i0_instr_d, 11, 7) @[dec_decode_ctl.scala 678:16]
-    i0r.rd <= _T_656 @[dec_decode_ctl.scala 678:11]
-    node _T_657 = neq(i0r.rs1, UInt<5>("h00")) @[dec_decode_ctl.scala 680:60]
-    node _T_658 = and(i0_dp.rs1, _T_657) @[dec_decode_ctl.scala 680:49]
-    io.decode_exu.dec_i0_rs1_en_d <= _T_658 @[dec_decode_ctl.scala 680:35]
-    node _T_659 = neq(i0r.rs2, UInt<5>("h00")) @[dec_decode_ctl.scala 681:60]
-    node _T_660 = and(i0_dp.rs2, _T_659) @[dec_decode_ctl.scala 681:49]
-    io.decode_exu.dec_i0_rs2_en_d <= _T_660 @[dec_decode_ctl.scala 681:35]
-    node _T_661 = neq(i0r.rd, UInt<5>("h00")) @[dec_decode_ctl.scala 682:48]
-    node i0_rd_en_d = and(i0_dp.rd, _T_661) @[dec_decode_ctl.scala 682:37]
-    io.dec_i0_rs1_d <= i0r.rs1 @[dec_decode_ctl.scala 683:19]
-    io.dec_i0_rs2_d <= i0r.rs2 @[dec_decode_ctl.scala 684:19]
-    node i0_jalimm20 = and(i0_dp.jal, i0_dp.imm20) @[dec_decode_ctl.scala 686:38]
-    node _T_662 = eq(i0_dp.jal, UInt<1>("h00")) @[dec_decode_ctl.scala 687:27]
-    node i0_uiimm20 = and(_T_662, i0_dp.imm20) @[dec_decode_ctl.scala 687:38]
-    node _T_663 = bits(io.dec_i0_instr_d, 31, 31) @[dec_decode_ctl.scala 694:38]
+    node _T_643 = and(_T_642, lsu_trigger_match_r) @[dec_decode_ctl.scala 666:82]
+    node _T_644 = or(_T_643, r_t.i0trigger) @[dec_decode_ctl.scala 666:105]
+    r_t_in.i0trigger <= _T_644 @[dec_decode_ctl.scala 666:33]
+    r_t_in.pmu_lsu_misaligned <= lsu_pmu_misaligned_r @[dec_decode_ctl.scala 667:33]
+    node _T_645 = bits(io.dec_tlu_flush_lower_wb, 0, 0) @[dec_decode_ctl.scala 669:35]
+    when _T_645 : @[dec_decode_ctl.scala 669:43]
+      wire _T_646 : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 669:66]
+      _T_646.pmu_lsu_misaligned <= UInt<1>("h00") @[dec_decode_ctl.scala 669:66]
+      _T_646.pmu_divide <= UInt<1>("h00") @[dec_decode_ctl.scala 669:66]
+      _T_646.pmu_i0_br_unpred <= UInt<1>("h00") @[dec_decode_ctl.scala 669:66]
+      _T_646.pmu_i0_itype <= UInt<4>("h00") @[dec_decode_ctl.scala 669:66]
+      _T_646.i0trigger <= UInt<4>("h00") @[dec_decode_ctl.scala 669:66]
+      _T_646.fence_i <= UInt<1>("h00") @[dec_decode_ctl.scala 669:66]
+      _T_646.icaf_type <= UInt<2>("h00") @[dec_decode_ctl.scala 669:66]
+      _T_646.icaf_second <= UInt<1>("h00") @[dec_decode_ctl.scala 669:66]
+      _T_646.icaf <= UInt<1>("h00") @[dec_decode_ctl.scala 669:66]
+      _T_646.legal <= UInt<1>("h00") @[dec_decode_ctl.scala 669:66]
+      r_t_in.pmu_lsu_misaligned <= _T_646.pmu_lsu_misaligned @[dec_decode_ctl.scala 669:51]
+      r_t_in.pmu_divide <= _T_646.pmu_divide @[dec_decode_ctl.scala 669:51]
+      r_t_in.pmu_i0_br_unpred <= _T_646.pmu_i0_br_unpred @[dec_decode_ctl.scala 669:51]
+      r_t_in.pmu_i0_itype <= _T_646.pmu_i0_itype @[dec_decode_ctl.scala 669:51]
+      r_t_in.i0trigger <= _T_646.i0trigger @[dec_decode_ctl.scala 669:51]
+      r_t_in.fence_i <= _T_646.fence_i @[dec_decode_ctl.scala 669:51]
+      r_t_in.icaf_type <= _T_646.icaf_type @[dec_decode_ctl.scala 669:51]
+      r_t_in.icaf_second <= _T_646.icaf_second @[dec_decode_ctl.scala 669:51]
+      r_t_in.icaf <= _T_646.icaf @[dec_decode_ctl.scala 669:51]
+      r_t_in.legal <= _T_646.legal @[dec_decode_ctl.scala 669:51]
+      skip @[dec_decode_ctl.scala 669:43]
+    io.dec_tlu_packet_r.pmu_lsu_misaligned <= r_t_in.pmu_lsu_misaligned @[dec_decode_ctl.scala 671:39]
+    io.dec_tlu_packet_r.pmu_divide <= r_t_in.pmu_divide @[dec_decode_ctl.scala 671:39]
+    io.dec_tlu_packet_r.pmu_i0_br_unpred <= r_t_in.pmu_i0_br_unpred @[dec_decode_ctl.scala 671:39]
+    io.dec_tlu_packet_r.pmu_i0_itype <= r_t_in.pmu_i0_itype @[dec_decode_ctl.scala 671:39]
+    io.dec_tlu_packet_r.i0trigger <= r_t_in.i0trigger @[dec_decode_ctl.scala 671:39]
+    io.dec_tlu_packet_r.fence_i <= r_t_in.fence_i @[dec_decode_ctl.scala 671:39]
+    io.dec_tlu_packet_r.icaf_type <= r_t_in.icaf_type @[dec_decode_ctl.scala 671:39]
+    io.dec_tlu_packet_r.icaf_second <= r_t_in.icaf_second @[dec_decode_ctl.scala 671:39]
+    io.dec_tlu_packet_r.icaf <= r_t_in.icaf @[dec_decode_ctl.scala 671:39]
+    io.dec_tlu_packet_r.legal <= r_t_in.legal @[dec_decode_ctl.scala 671:39]
+    node _T_647 = and(r_d.bits.i0div, r_d.valid) @[dec_decode_ctl.scala 672:58]
+    io.dec_tlu_packet_r.pmu_divide <= _T_647 @[dec_decode_ctl.scala 672:39]
+    node _T_648 = eq(i0_block_d, UInt<1>("h00")) @[dec_decode_ctl.scala 676:46]
+    node _T_649 = and(io.dec_ib0_valid_d, _T_648) @[dec_decode_ctl.scala 676:44]
+    node _T_650 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 676:60]
+    node _T_651 = and(_T_649, _T_650) @[dec_decode_ctl.scala 676:58]
+    node _T_652 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 676:88]
+    node _T_653 = and(_T_651, _T_652) @[dec_decode_ctl.scala 676:86]
+    io.dec_i0_decode_d <= _T_653 @[dec_decode_ctl.scala 676:22]
+    node _T_654 = bits(io.dec_i0_instr_d, 19, 15) @[dec_decode_ctl.scala 678:16]
+    i0r.rs1 <= _T_654 @[dec_decode_ctl.scala 678:11]
+    node _T_655 = bits(io.dec_i0_instr_d, 24, 20) @[dec_decode_ctl.scala 679:16]
+    i0r.rs2 <= _T_655 @[dec_decode_ctl.scala 679:11]
+    node _T_656 = bits(io.dec_i0_instr_d, 11, 7) @[dec_decode_ctl.scala 680:16]
+    i0r.rd <= _T_656 @[dec_decode_ctl.scala 680:11]
+    node _T_657 = neq(i0r.rs1, UInt<5>("h00")) @[dec_decode_ctl.scala 682:60]
+    node _T_658 = and(i0_dp.rs1, _T_657) @[dec_decode_ctl.scala 682:49]
+    io.decode_exu.dec_i0_rs1_en_d <= _T_658 @[dec_decode_ctl.scala 682:35]
+    node _T_659 = neq(i0r.rs2, UInt<5>("h00")) @[dec_decode_ctl.scala 683:60]
+    node _T_660 = and(i0_dp.rs2, _T_659) @[dec_decode_ctl.scala 683:49]
+    io.decode_exu.dec_i0_rs2_en_d <= _T_660 @[dec_decode_ctl.scala 683:35]
+    node _T_661 = neq(i0r.rd, UInt<5>("h00")) @[dec_decode_ctl.scala 684:48]
+    node i0_rd_en_d = and(i0_dp.rd, _T_661) @[dec_decode_ctl.scala 684:37]
+    io.dec_i0_rs1_d <= i0r.rs1 @[dec_decode_ctl.scala 685:19]
+    io.dec_i0_rs2_d <= i0r.rs2 @[dec_decode_ctl.scala 686:19]
+    node i0_jalimm20 = and(i0_dp.jal, i0_dp.imm20) @[dec_decode_ctl.scala 688:38]
+    node _T_662 = eq(i0_dp.jal, UInt<1>("h00")) @[dec_decode_ctl.scala 689:27]
+    node i0_uiimm20 = and(_T_662, i0_dp.imm20) @[dec_decode_ctl.scala 689:38]
+    node _T_663 = bits(io.dec_i0_instr_d, 31, 31) @[dec_decode_ctl.scala 696:38]
     wire _T_664 : UInt<1>[20] @[lib.scala 12:48]
     _T_664[0] <= _T_663 @[lib.scala 12:48]
     _T_664[1] <= _T_663 @[lib.scala 12:48]
@@ -6959,7 +6959,7 @@ circuit dec :
     node _T_681 = cat(_T_680, _T_664[17]) @[Cat.scala 29:58]
     node _T_682 = cat(_T_681, _T_664[18]) @[Cat.scala 29:58]
     node _T_683 = cat(_T_682, _T_664[19]) @[Cat.scala 29:58]
-    node _T_684 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 694:46]
+    node _T_684 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 696:46]
     node _T_685 = cat(_T_683, _T_684) @[Cat.scala 29:58]
     wire _T_686 : UInt<1>[27] @[lib.scala 12:48]
     _T_686[0] <= UInt<1>("h00") @[lib.scala 12:48]
@@ -7015,9 +7015,9 @@ circuit dec :
     node _T_710 = cat(_T_709, _T_686[24]) @[Cat.scala 29:58]
     node _T_711 = cat(_T_710, _T_686[25]) @[Cat.scala 29:58]
     node _T_712 = cat(_T_711, _T_686[26]) @[Cat.scala 29:58]
-    node _T_713 = bits(io.dec_i0_instr_d, 24, 20) @[dec_decode_ctl.scala 695:43]
+    node _T_713 = bits(io.dec_i0_instr_d, 24, 20) @[dec_decode_ctl.scala 697:43]
     node _T_714 = cat(_T_712, _T_713) @[Cat.scala 29:58]
-    node _T_715 = bits(io.dec_i0_instr_d, 31, 31) @[dec_decode_ctl.scala 696:38]
+    node _T_715 = bits(io.dec_i0_instr_d, 31, 31) @[dec_decode_ctl.scala 698:38]
     wire _T_716 : UInt<1>[12] @[lib.scala 12:48]
     _T_716[0] <= _T_715 @[lib.scala 12:48]
     _T_716[1] <= _T_715 @[lib.scala 12:48]
@@ -7042,14 +7042,14 @@ circuit dec :
     node _T_725 = cat(_T_724, _T_716[9]) @[Cat.scala 29:58]
     node _T_726 = cat(_T_725, _T_716[10]) @[Cat.scala 29:58]
     node _T_727 = cat(_T_726, _T_716[11]) @[Cat.scala 29:58]
-    node _T_728 = bits(io.dec_i0_instr_d, 19, 12) @[dec_decode_ctl.scala 696:46]
-    node _T_729 = bits(io.dec_i0_instr_d, 20, 20) @[dec_decode_ctl.scala 696:56]
-    node _T_730 = bits(io.dec_i0_instr_d, 30, 21) @[dec_decode_ctl.scala 696:63]
+    node _T_728 = bits(io.dec_i0_instr_d, 19, 12) @[dec_decode_ctl.scala 698:46]
+    node _T_729 = bits(io.dec_i0_instr_d, 20, 20) @[dec_decode_ctl.scala 698:56]
+    node _T_730 = bits(io.dec_i0_instr_d, 30, 21) @[dec_decode_ctl.scala 698:63]
     node _T_731 = cat(_T_730, UInt<1>("h00")) @[Cat.scala 29:58]
     node _T_732 = cat(_T_727, _T_728) @[Cat.scala 29:58]
     node _T_733 = cat(_T_732, _T_729) @[Cat.scala 29:58]
     node _T_734 = cat(_T_733, _T_731) @[Cat.scala 29:58]
-    node _T_735 = bits(io.dec_i0_instr_d, 31, 12) @[dec_decode_ctl.scala 697:30]
+    node _T_735 = bits(io.dec_i0_instr_d, 31, 12) @[dec_decode_ctl.scala 699:30]
     wire _T_736 : UInt<1>[12] @[lib.scala 12:48]
     _T_736[0] <= UInt<1>("h00") @[lib.scala 12:48]
     _T_736[1] <= UInt<1>("h00") @[lib.scala 12:48]
@@ -7075,8 +7075,8 @@ circuit dec :
     node _T_746 = cat(_T_745, _T_736[10]) @[Cat.scala 29:58]
     node _T_747 = cat(_T_746, _T_736[11]) @[Cat.scala 29:58]
     node _T_748 = cat(_T_735, _T_747) @[Cat.scala 29:58]
-    node _T_749 = and(i0_csr_write_only_d, i0_dp.csr_imm) @[dec_decode_ctl.scala 698:26]
-    node _T_750 = bits(_T_749, 0, 0) @[dec_decode_ctl.scala 698:43]
+    node _T_749 = and(i0_csr_write_only_d, i0_dp.csr_imm) @[dec_decode_ctl.scala 700:26]
+    node _T_750 = bits(_T_749, 0, 0) @[dec_decode_ctl.scala 700:43]
     wire _T_751 : UInt<1>[27] @[lib.scala 12:48]
     _T_751[0] <= UInt<1>("h00") @[lib.scala 12:48]
     _T_751[1] <= UInt<1>("h00") @[lib.scala 12:48]
@@ -7131,7 +7131,7 @@ circuit dec :
     node _T_775 = cat(_T_774, _T_751[24]) @[Cat.scala 29:58]
     node _T_776 = cat(_T_775, _T_751[25]) @[Cat.scala 29:58]
     node _T_777 = cat(_T_776, _T_751[26]) @[Cat.scala 29:58]
-    node _T_778 = bits(io.dec_i0_instr_d, 19, 15) @[dec_decode_ctl.scala 698:72]
+    node _T_778 = bits(io.dec_i0_instr_d, 19, 15) @[dec_decode_ctl.scala 700:72]
     node _T_779 = cat(_T_777, _T_778) @[Cat.scala 29:58]
     node _T_780 = mux(i0_dp.imm12, _T_685, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_781 = mux(i0_dp.shimm5, _T_714, UInt<1>("h00")) @[Mux.scala 27:72]
@@ -7144,7 +7144,7 @@ circuit dec :
     node _T_788 = or(_T_787, _T_784) @[Mux.scala 27:72]
     wire _T_789 : UInt<32> @[Mux.scala 27:72]
     _T_789 <= _T_788 @[Mux.scala 27:72]
-    io.decode_exu.dec_i0_immed_d <= _T_789 @[dec_decode_ctl.scala 693:32]
+    io.decode_exu.dec_i0_immed_d <= _T_789 @[dec_decode_ctl.scala 695:32]
     wire bitmanip_zbb_legal : UInt<1>
     bitmanip_zbb_legal <= UInt<1>("h00")
     wire bitmanip_zbs_legal : UInt<1>
@@ -7165,111 +7165,111 @@ circuit dec :
     bitmanip_zbb_zbp_legal <= UInt<1>("h00")
     wire bitmanip_legal : UInt<1>
     bitmanip_legal <= UInt<1>("h00")
-    bitmanip_zbb_legal <= UInt<1>("h01") @[dec_decode_ctl.scala 711:29]
-    bitmanip_zbs_legal <= UInt<1>("h01") @[dec_decode_ctl.scala 716:29]
-    node _T_790 = eq(i0_dp.zbe, UInt<1>("h00")) @[dec_decode_ctl.scala 723:32]
-    bitmanip_zbe_legal <= _T_790 @[dec_decode_ctl.scala 723:29]
-    node _T_791 = eq(i0_dp.zbc, UInt<1>("h00")) @[dec_decode_ctl.scala 728:32]
-    bitmanip_zbc_legal <= _T_791 @[dec_decode_ctl.scala 728:29]
-    node _T_792 = eq(i0_dp.zbb, UInt<1>("h00")) @[dec_decode_ctl.scala 733:46]
-    node _T_793 = and(i0_dp.zbp, _T_792) @[dec_decode_ctl.scala 733:44]
-    node _T_794 = eq(_T_793, UInt<1>("h00")) @[dec_decode_ctl.scala 733:32]
-    bitmanip_zbp_legal <= _T_794 @[dec_decode_ctl.scala 733:29]
-    node _T_795 = eq(i0_dp.zbr, UInt<1>("h00")) @[dec_decode_ctl.scala 738:32]
-    bitmanip_zbr_legal <= _T_795 @[dec_decode_ctl.scala 738:29]
-    node _T_796 = eq(i0_dp.zbf, UInt<1>("h00")) @[dec_decode_ctl.scala 743:32]
-    bitmanip_zbf_legal <= _T_796 @[dec_decode_ctl.scala 743:29]
-    node _T_797 = eq(i0_dp.zba, UInt<1>("h00")) @[dec_decode_ctl.scala 748:32]
-    bitmanip_zba_legal <= _T_797 @[dec_decode_ctl.scala 748:29]
-    bitmanip_zbb_zbp_legal <= UInt<1>("h01") @[dec_decode_ctl.scala 751:29]
-    node _T_798 = and(bitmanip_zbb_legal, bitmanip_zbs_legal) @[dec_decode_ctl.scala 755:41]
-    node _T_799 = and(_T_798, bitmanip_zbe_legal) @[dec_decode_ctl.scala 755:62]
-    node _T_800 = and(_T_799, bitmanip_zbc_legal) @[dec_decode_ctl.scala 755:83]
-    node _T_801 = and(_T_800, bitmanip_zbp_legal) @[dec_decode_ctl.scala 755:104]
-    node _T_802 = and(_T_801, bitmanip_zbr_legal) @[dec_decode_ctl.scala 755:125]
-    node _T_803 = and(_T_802, bitmanip_zbf_legal) @[dec_decode_ctl.scala 755:146]
-    node _T_804 = and(_T_803, bitmanip_zba_legal) @[dec_decode_ctl.scala 755:167]
-    node _T_805 = and(_T_804, bitmanip_zbb_zbp_legal) @[dec_decode_ctl.scala 755:188]
-    bitmanip_legal <= _T_805 @[dec_decode_ctl.scala 755:18]
-    node _T_806 = and(io.dec_aln.dec_i0_decode_d, i0_legal) @[dec_decode_ctl.scala 756:54]
-    i0_legal_decode_d <= _T_806 @[dec_decode_ctl.scala 756:24]
-    node _T_807 = and(i0_dp.mul, i0_legal_decode_d) @[dec_decode_ctl.scala 758:44]
-    i0_d_c.mul <= _T_807 @[dec_decode_ctl.scala 758:29]
-    node _T_808 = and(i0_dp.load, i0_legal_decode_d) @[dec_decode_ctl.scala 759:44]
-    i0_d_c.load <= _T_808 @[dec_decode_ctl.scala 759:29]
-    node _T_809 = and(i0_dp.alu, i0_legal_decode_d) @[dec_decode_ctl.scala 760:44]
-    i0_d_c.alu <= _T_809 @[dec_decode_ctl.scala 760:29]
-    wire _T_810 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 762:70]
-    _T_810.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 762:70]
-    _T_810.load <= UInt<1>("h00") @[dec_decode_ctl.scala 762:70]
-    _T_810.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 762:70]
-    node _T_811 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 762:92]
+    bitmanip_zbb_legal <= UInt<1>("h01") @[dec_decode_ctl.scala 713:29]
+    bitmanip_zbs_legal <= UInt<1>("h01") @[dec_decode_ctl.scala 718:29]
+    node _T_790 = eq(i0_dp.zbe, UInt<1>("h00")) @[dec_decode_ctl.scala 725:32]
+    bitmanip_zbe_legal <= _T_790 @[dec_decode_ctl.scala 725:29]
+    node _T_791 = eq(i0_dp.zbc, UInt<1>("h00")) @[dec_decode_ctl.scala 730:32]
+    bitmanip_zbc_legal <= _T_791 @[dec_decode_ctl.scala 730:29]
+    node _T_792 = eq(i0_dp.zbb, UInt<1>("h00")) @[dec_decode_ctl.scala 735:46]
+    node _T_793 = and(i0_dp.zbp, _T_792) @[dec_decode_ctl.scala 735:44]
+    node _T_794 = eq(_T_793, UInt<1>("h00")) @[dec_decode_ctl.scala 735:32]
+    bitmanip_zbp_legal <= _T_794 @[dec_decode_ctl.scala 735:29]
+    node _T_795 = eq(i0_dp.zbr, UInt<1>("h00")) @[dec_decode_ctl.scala 740:32]
+    bitmanip_zbr_legal <= _T_795 @[dec_decode_ctl.scala 740:29]
+    node _T_796 = eq(i0_dp.zbf, UInt<1>("h00")) @[dec_decode_ctl.scala 745:32]
+    bitmanip_zbf_legal <= _T_796 @[dec_decode_ctl.scala 745:29]
+    node _T_797 = eq(i0_dp.zba, UInt<1>("h00")) @[dec_decode_ctl.scala 750:32]
+    bitmanip_zba_legal <= _T_797 @[dec_decode_ctl.scala 750:29]
+    bitmanip_zbb_zbp_legal <= UInt<1>("h01") @[dec_decode_ctl.scala 753:29]
+    node _T_798 = and(bitmanip_zbb_legal, bitmanip_zbs_legal) @[dec_decode_ctl.scala 757:41]
+    node _T_799 = and(_T_798, bitmanip_zbe_legal) @[dec_decode_ctl.scala 757:62]
+    node _T_800 = and(_T_799, bitmanip_zbc_legal) @[dec_decode_ctl.scala 757:83]
+    node _T_801 = and(_T_800, bitmanip_zbp_legal) @[dec_decode_ctl.scala 757:104]
+    node _T_802 = and(_T_801, bitmanip_zbr_legal) @[dec_decode_ctl.scala 757:125]
+    node _T_803 = and(_T_802, bitmanip_zbf_legal) @[dec_decode_ctl.scala 757:146]
+    node _T_804 = and(_T_803, bitmanip_zba_legal) @[dec_decode_ctl.scala 757:167]
+    node _T_805 = and(_T_804, bitmanip_zbb_zbp_legal) @[dec_decode_ctl.scala 757:188]
+    bitmanip_legal <= _T_805 @[dec_decode_ctl.scala 757:18]
+    node _T_806 = and(io.dec_i0_decode_d, i0_legal) @[dec_decode_ctl.scala 758:46]
+    i0_legal_decode_d <= _T_806 @[dec_decode_ctl.scala 758:24]
+    node _T_807 = and(i0_dp.mul, i0_legal_decode_d) @[dec_decode_ctl.scala 760:44]
+    i0_d_c.mul <= _T_807 @[dec_decode_ctl.scala 760:29]
+    node _T_808 = and(i0_dp.load, i0_legal_decode_d) @[dec_decode_ctl.scala 761:44]
+    i0_d_c.load <= _T_808 @[dec_decode_ctl.scala 761:29]
+    node _T_809 = and(i0_dp.alu, i0_legal_decode_d) @[dec_decode_ctl.scala 762:44]
+    i0_d_c.alu <= _T_809 @[dec_decode_ctl.scala 762:29]
+    wire _T_810 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 764:70]
+    _T_810.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 764:70]
+    _T_810.load <= UInt<1>("h00") @[dec_decode_ctl.scala 764:70]
+    _T_810.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 764:70]
+    node _T_811 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 764:92]
     reg i0_x_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>}, io.active_clk with : (reset => (reset, _T_810)) @[Reg.scala 27:20]
     when _T_811 : @[Reg.scala 28:19]
       i0_x_c.alu <= i0_d_c.alu @[Reg.scala 28:23]
       i0_x_c.load <= i0_d_c.load @[Reg.scala 28:23]
       i0_x_c.mul <= i0_d_c.mul @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    wire _T_812 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 763:70]
-    _T_812.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 763:70]
-    _T_812.load <= UInt<1>("h00") @[dec_decode_ctl.scala 763:70]
-    _T_812.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 763:70]
-    node _T_813 = bits(i0_r_ctl_en, 0, 0) @[dec_decode_ctl.scala 763:92]
+    wire _T_812 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 765:70]
+    _T_812.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 765:70]
+    _T_812.load <= UInt<1>("h00") @[dec_decode_ctl.scala 765:70]
+    _T_812.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 765:70]
+    node _T_813 = bits(i0_r_ctl_en, 0, 0) @[dec_decode_ctl.scala 765:92]
     reg i0_r_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>}, io.active_clk with : (reset => (reset, _T_812)) @[Reg.scala 27:20]
     when _T_813 : @[Reg.scala 28:19]
       i0_r_c.alu <= i0_x_c.alu @[Reg.scala 28:23]
       i0_r_c.load <= i0_x_c.load @[Reg.scala 28:23]
       i0_r_c.mul <= i0_x_c.mul @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    node _T_814 = bits(i0_pipe_en, 3, 1) @[dec_decode_ctl.scala 764:91]
-    reg _T_815 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 764:80]
-    _T_815 <= _T_814 @[dec_decode_ctl.scala 764:80]
-    node _T_816 = cat(io.dec_aln.dec_i0_decode_d, _T_815) @[Cat.scala 29:58]
-    i0_pipe_en <= _T_816 @[dec_decode_ctl.scala 764:14]
-    node _T_817 = bits(i0_pipe_en, 3, 2) @[dec_decode_ctl.scala 766:43]
-    node _T_818 = orr(_T_817) @[dec_decode_ctl.scala 766:49]
-    node _T_819 = or(_T_818, io.clk_override) @[dec_decode_ctl.scala 766:53]
-    i0_x_ctl_en <= _T_819 @[dec_decode_ctl.scala 766:29]
-    node _T_820 = bits(i0_pipe_en, 2, 1) @[dec_decode_ctl.scala 767:43]
-    node _T_821 = orr(_T_820) @[dec_decode_ctl.scala 767:49]
-    node _T_822 = or(_T_821, io.clk_override) @[dec_decode_ctl.scala 767:53]
-    i0_r_ctl_en <= _T_822 @[dec_decode_ctl.scala 767:29]
-    node _T_823 = bits(i0_pipe_en, 1, 0) @[dec_decode_ctl.scala 768:43]
-    node _T_824 = orr(_T_823) @[dec_decode_ctl.scala 768:49]
-    node _T_825 = or(_T_824, io.clk_override) @[dec_decode_ctl.scala 768:53]
-    i0_wb_ctl_en <= _T_825 @[dec_decode_ctl.scala 768:29]
-    node _T_826 = bits(i0_pipe_en, 3, 3) @[dec_decode_ctl.scala 769:44]
-    node _T_827 = or(_T_826, io.clk_override) @[dec_decode_ctl.scala 769:50]
-    i0_x_data_en <= _T_827 @[dec_decode_ctl.scala 769:29]
-    node _T_828 = bits(i0_pipe_en, 2, 2) @[dec_decode_ctl.scala 770:44]
-    node _T_829 = or(_T_828, io.clk_override) @[dec_decode_ctl.scala 770:50]
-    i0_r_data_en <= _T_829 @[dec_decode_ctl.scala 770:29]
-    node _T_830 = bits(i0_pipe_en, 1, 1) @[dec_decode_ctl.scala 771:44]
-    node _T_831 = or(_T_830, io.clk_override) @[dec_decode_ctl.scala 771:50]
-    i0_wb_data_en <= _T_831 @[dec_decode_ctl.scala 771:29]
+    node _T_814 = bits(i0_pipe_en, 3, 1) @[dec_decode_ctl.scala 766:83]
+    reg _T_815 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 766:72]
+    _T_815 <= _T_814 @[dec_decode_ctl.scala 766:72]
+    node _T_816 = cat(io.dec_i0_decode_d, _T_815) @[Cat.scala 29:58]
+    i0_pipe_en <= _T_816 @[dec_decode_ctl.scala 766:14]
+    node _T_817 = bits(i0_pipe_en, 3, 2) @[dec_decode_ctl.scala 768:43]
+    node _T_818 = orr(_T_817) @[dec_decode_ctl.scala 768:49]
+    node _T_819 = or(_T_818, io.clk_override) @[dec_decode_ctl.scala 768:53]
+    i0_x_ctl_en <= _T_819 @[dec_decode_ctl.scala 768:29]
+    node _T_820 = bits(i0_pipe_en, 2, 1) @[dec_decode_ctl.scala 769:43]
+    node _T_821 = orr(_T_820) @[dec_decode_ctl.scala 769:49]
+    node _T_822 = or(_T_821, io.clk_override) @[dec_decode_ctl.scala 769:53]
+    i0_r_ctl_en <= _T_822 @[dec_decode_ctl.scala 769:29]
+    node _T_823 = bits(i0_pipe_en, 1, 0) @[dec_decode_ctl.scala 770:43]
+    node _T_824 = orr(_T_823) @[dec_decode_ctl.scala 770:49]
+    node _T_825 = or(_T_824, io.clk_override) @[dec_decode_ctl.scala 770:53]
+    i0_wb_ctl_en <= _T_825 @[dec_decode_ctl.scala 770:29]
+    node _T_826 = bits(i0_pipe_en, 3, 3) @[dec_decode_ctl.scala 771:44]
+    node _T_827 = or(_T_826, io.clk_override) @[dec_decode_ctl.scala 771:50]
+    i0_x_data_en <= _T_827 @[dec_decode_ctl.scala 771:29]
+    node _T_828 = bits(i0_pipe_en, 2, 2) @[dec_decode_ctl.scala 772:44]
+    node _T_829 = or(_T_828, io.clk_override) @[dec_decode_ctl.scala 772:50]
+    i0_r_data_en <= _T_829 @[dec_decode_ctl.scala 772:29]
+    node _T_830 = bits(i0_pipe_en, 1, 1) @[dec_decode_ctl.scala 773:44]
+    node _T_831 = or(_T_830, io.clk_override) @[dec_decode_ctl.scala 773:50]
+    i0_wb_data_en <= _T_831 @[dec_decode_ctl.scala 773:29]
     node _T_832 = cat(i0_x_data_en, i0_r_data_en) @[Cat.scala 29:58]
-    io.decode_exu.dec_data_en <= _T_832 @[dec_decode_ctl.scala 773:38]
+    io.decode_exu.dec_data_en <= _T_832 @[dec_decode_ctl.scala 775:38]
     node _T_833 = cat(i0_x_ctl_en, i0_r_ctl_en) @[Cat.scala 29:58]
-    io.decode_exu.dec_ctl_en <= _T_833 @[dec_decode_ctl.scala 774:38]
-    d_d.bits.i0rd <= i0r.rd @[dec_decode_ctl.scala 776:34]
-    node _T_834 = and(i0_rd_en_d, i0_legal_decode_d) @[dec_decode_ctl.scala 777:50]
-    d_d.bits.i0v <= _T_834 @[dec_decode_ctl.scala 777:34]
-    d_d.valid <= io.dec_aln.dec_i0_decode_d @[dec_decode_ctl.scala 778:27]
-    node _T_835 = and(i0_dp.load, i0_legal_decode_d) @[dec_decode_ctl.scala 780:50]
-    d_d.bits.i0load <= _T_835 @[dec_decode_ctl.scala 780:34]
-    node _T_836 = and(i0_dp.store, i0_legal_decode_d) @[dec_decode_ctl.scala 781:50]
-    d_d.bits.i0store <= _T_836 @[dec_decode_ctl.scala 781:34]
-    node _T_837 = and(i0_dp.div, i0_legal_decode_d) @[dec_decode_ctl.scala 782:50]
-    d_d.bits.i0div <= _T_837 @[dec_decode_ctl.scala 782:34]
-    node _T_838 = and(io.dec_csr_wen_unq_d, i0_legal_decode_d) @[dec_decode_ctl.scala 784:61]
-    d_d.bits.csrwen <= _T_838 @[dec_decode_ctl.scala 784:34]
-    node _T_839 = and(i0_csr_write_only_d, io.dec_aln.dec_i0_decode_d) @[dec_decode_ctl.scala 785:58]
-    d_d.bits.csrwonly <= _T_839 @[dec_decode_ctl.scala 785:34]
+    io.decode_exu.dec_ctl_en <= _T_833 @[dec_decode_ctl.scala 776:38]
+    d_d.bits.i0rd <= i0r.rd @[dec_decode_ctl.scala 778:34]
+    node _T_834 = and(i0_rd_en_d, i0_legal_decode_d) @[dec_decode_ctl.scala 779:50]
+    d_d.bits.i0v <= _T_834 @[dec_decode_ctl.scala 779:34]
+    d_d.valid <= io.dec_i0_decode_d @[dec_decode_ctl.scala 780:35]
+    node _T_835 = and(i0_dp.load, i0_legal_decode_d) @[dec_decode_ctl.scala 782:50]
+    d_d.bits.i0load <= _T_835 @[dec_decode_ctl.scala 782:34]
+    node _T_836 = and(i0_dp.store, i0_legal_decode_d) @[dec_decode_ctl.scala 783:50]
+    d_d.bits.i0store <= _T_836 @[dec_decode_ctl.scala 783:34]
+    node _T_837 = and(i0_dp.div, i0_legal_decode_d) @[dec_decode_ctl.scala 784:50]
+    d_d.bits.i0div <= _T_837 @[dec_decode_ctl.scala 784:34]
+    node _T_838 = and(io.dec_csr_wen_unq_d, i0_legal_decode_d) @[dec_decode_ctl.scala 786:61]
+    d_d.bits.csrwen <= _T_838 @[dec_decode_ctl.scala 786:34]
+    node _T_839 = and(i0_csr_write_only_d, io.dec_i0_decode_d) @[dec_decode_ctl.scala 787:58]
+    d_d.bits.csrwonly <= _T_839 @[dec_decode_ctl.scala 787:34]
     node _T_840 = bits(d_d.bits.csrwen, 0, 0) @[lib.scala 8:44]
-    node _T_841 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 786:61]
-    node _T_842 = mux(_T_840, _T_841, UInt<1>("h00")) @[dec_decode_ctl.scala 786:41]
-    d_d.bits.csrwaddr <= _T_842 @[dec_decode_ctl.scala 786:34]
-    node _T_843 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 788:63]
+    node _T_841 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 788:61]
+    node _T_842 = mux(_T_840, _T_841, UInt<1>("h00")) @[dec_decode_ctl.scala 788:41]
+    d_d.bits.csrwaddr <= _T_842 @[dec_decode_ctl.scala 788:34]
+    node _T_843 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 790:63]
     wire _T_844 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[lib.scala 630:37]
     _T_844.bits.csrwaddr <= UInt<12>("h00") @[lib.scala 630:37]
     _T_844.bits.csrwonly <= UInt<1>("h00") @[lib.scala 630:37]
@@ -7292,36 +7292,36 @@ circuit dec :
       _T_845.bits.i0rd <= d_d.bits.i0rd @[Reg.scala 28:23]
       _T_845.valid <= d_d.valid @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    x_d.bits.csrwaddr <= _T_845.bits.csrwaddr @[dec_decode_ctl.scala 788:7]
-    x_d.bits.csrwonly <= _T_845.bits.csrwonly @[dec_decode_ctl.scala 788:7]
-    x_d.bits.csrwen <= _T_845.bits.csrwen @[dec_decode_ctl.scala 788:7]
-    x_d.bits.i0v <= _T_845.bits.i0v @[dec_decode_ctl.scala 788:7]
-    x_d.bits.i0div <= _T_845.bits.i0div @[dec_decode_ctl.scala 788:7]
-    x_d.bits.i0store <= _T_845.bits.i0store @[dec_decode_ctl.scala 788:7]
-    x_d.bits.i0load <= _T_845.bits.i0load @[dec_decode_ctl.scala 788:7]
-    x_d.bits.i0rd <= _T_845.bits.i0rd @[dec_decode_ctl.scala 788:7]
-    x_d.valid <= _T_845.valid @[dec_decode_ctl.scala 788:7]
-    wire x_d_in : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 789:20]
-    x_d_in.bits.csrwaddr <= x_d.bits.csrwaddr @[dec_decode_ctl.scala 790:10]
-    x_d_in.bits.csrwonly <= x_d.bits.csrwonly @[dec_decode_ctl.scala 790:10]
-    x_d_in.bits.csrwen <= x_d.bits.csrwen @[dec_decode_ctl.scala 790:10]
-    x_d_in.bits.i0v <= x_d.bits.i0v @[dec_decode_ctl.scala 790:10]
-    x_d_in.bits.i0div <= x_d.bits.i0div @[dec_decode_ctl.scala 790:10]
-    x_d_in.bits.i0store <= x_d.bits.i0store @[dec_decode_ctl.scala 790:10]
-    x_d_in.bits.i0load <= x_d.bits.i0load @[dec_decode_ctl.scala 790:10]
-    x_d_in.bits.i0rd <= x_d.bits.i0rd @[dec_decode_ctl.scala 790:10]
-    x_d_in.valid <= x_d.valid @[dec_decode_ctl.scala 790:10]
-    node _T_846 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 791:49]
-    node _T_847 = and(x_d.bits.i0v, _T_846) @[dec_decode_ctl.scala 791:47]
-    node _T_848 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 791:78]
-    node _T_849 = and(_T_847, _T_848) @[dec_decode_ctl.scala 791:76]
-    x_d_in.bits.i0v <= _T_849 @[dec_decode_ctl.scala 791:27]
-    node _T_850 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 792:35]
-    node _T_851 = and(x_d.valid, _T_850) @[dec_decode_ctl.scala 792:33]
-    node _T_852 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 792:64]
-    node _T_853 = and(_T_851, _T_852) @[dec_decode_ctl.scala 792:62]
-    x_d_in.valid <= _T_853 @[dec_decode_ctl.scala 792:20]
-    node _T_854 = bits(i0_r_ctl_en, 0, 0) @[dec_decode_ctl.scala 794:65]
+    x_d.bits.csrwaddr <= _T_845.bits.csrwaddr @[dec_decode_ctl.scala 790:7]
+    x_d.bits.csrwonly <= _T_845.bits.csrwonly @[dec_decode_ctl.scala 790:7]
+    x_d.bits.csrwen <= _T_845.bits.csrwen @[dec_decode_ctl.scala 790:7]
+    x_d.bits.i0v <= _T_845.bits.i0v @[dec_decode_ctl.scala 790:7]
+    x_d.bits.i0div <= _T_845.bits.i0div @[dec_decode_ctl.scala 790:7]
+    x_d.bits.i0store <= _T_845.bits.i0store @[dec_decode_ctl.scala 790:7]
+    x_d.bits.i0load <= _T_845.bits.i0load @[dec_decode_ctl.scala 790:7]
+    x_d.bits.i0rd <= _T_845.bits.i0rd @[dec_decode_ctl.scala 790:7]
+    x_d.valid <= _T_845.valid @[dec_decode_ctl.scala 790:7]
+    wire x_d_in : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 791:20]
+    x_d_in.bits.csrwaddr <= x_d.bits.csrwaddr @[dec_decode_ctl.scala 792:10]
+    x_d_in.bits.csrwonly <= x_d.bits.csrwonly @[dec_decode_ctl.scala 792:10]
+    x_d_in.bits.csrwen <= x_d.bits.csrwen @[dec_decode_ctl.scala 792:10]
+    x_d_in.bits.i0v <= x_d.bits.i0v @[dec_decode_ctl.scala 792:10]
+    x_d_in.bits.i0div <= x_d.bits.i0div @[dec_decode_ctl.scala 792:10]
+    x_d_in.bits.i0store <= x_d.bits.i0store @[dec_decode_ctl.scala 792:10]
+    x_d_in.bits.i0load <= x_d.bits.i0load @[dec_decode_ctl.scala 792:10]
+    x_d_in.bits.i0rd <= x_d.bits.i0rd @[dec_decode_ctl.scala 792:10]
+    x_d_in.valid <= x_d.valid @[dec_decode_ctl.scala 792:10]
+    node _T_846 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 793:49]
+    node _T_847 = and(x_d.bits.i0v, _T_846) @[dec_decode_ctl.scala 793:47]
+    node _T_848 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 793:78]
+    node _T_849 = and(_T_847, _T_848) @[dec_decode_ctl.scala 793:76]
+    x_d_in.bits.i0v <= _T_849 @[dec_decode_ctl.scala 793:27]
+    node _T_850 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 794:35]
+    node _T_851 = and(x_d.valid, _T_850) @[dec_decode_ctl.scala 794:33]
+    node _T_852 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 794:64]
+    node _T_853 = and(_T_851, _T_852) @[dec_decode_ctl.scala 794:62]
+    x_d_in.valid <= _T_853 @[dec_decode_ctl.scala 794:20]
+    node _T_854 = bits(i0_r_ctl_en, 0, 0) @[dec_decode_ctl.scala 796:65]
     wire _T_855 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[lib.scala 630:37]
     _T_855.bits.csrwaddr <= UInt<12>("h00") @[lib.scala 630:37]
     _T_855.bits.csrwonly <= UInt<1>("h00") @[lib.scala 630:37]
@@ -7344,38 +7344,38 @@ circuit dec :
       _T_856.bits.i0rd <= x_d_in.bits.i0rd @[Reg.scala 28:23]
       _T_856.valid <= x_d_in.valid @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    r_d.bits.csrwaddr <= _T_856.bits.csrwaddr @[dec_decode_ctl.scala 794:7]
-    r_d.bits.csrwonly <= _T_856.bits.csrwonly @[dec_decode_ctl.scala 794:7]
-    r_d.bits.csrwen <= _T_856.bits.csrwen @[dec_decode_ctl.scala 794:7]
-    r_d.bits.i0v <= _T_856.bits.i0v @[dec_decode_ctl.scala 794:7]
-    r_d.bits.i0div <= _T_856.bits.i0div @[dec_decode_ctl.scala 794:7]
-    r_d.bits.i0store <= _T_856.bits.i0store @[dec_decode_ctl.scala 794:7]
-    r_d.bits.i0load <= _T_856.bits.i0load @[dec_decode_ctl.scala 794:7]
-    r_d.bits.i0rd <= _T_856.bits.i0rd @[dec_decode_ctl.scala 794:7]
-    r_d.valid <= _T_856.valid @[dec_decode_ctl.scala 794:7]
-    r_d_in.bits.csrwaddr <= r_d.bits.csrwaddr @[dec_decode_ctl.scala 795:10]
-    r_d_in.bits.csrwonly <= r_d.bits.csrwonly @[dec_decode_ctl.scala 795:10]
-    r_d_in.bits.csrwen <= r_d.bits.csrwen @[dec_decode_ctl.scala 795:10]
-    r_d_in.bits.i0v <= r_d.bits.i0v @[dec_decode_ctl.scala 795:10]
-    r_d_in.bits.i0div <= r_d.bits.i0div @[dec_decode_ctl.scala 795:10]
-    r_d_in.bits.i0store <= r_d.bits.i0store @[dec_decode_ctl.scala 795:10]
-    r_d_in.bits.i0load <= r_d.bits.i0load @[dec_decode_ctl.scala 795:10]
-    r_d_in.bits.i0rd <= r_d.bits.i0rd @[dec_decode_ctl.scala 795:10]
-    r_d_in.valid <= r_d.valid @[dec_decode_ctl.scala 795:10]
-    r_d_in.bits.i0rd <= r_d.bits.i0rd @[dec_decode_ctl.scala 796:22]
-    node _T_857 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 798:51]
-    node _T_858 = and(r_d.bits.i0v, _T_857) @[dec_decode_ctl.scala 798:49]
-    r_d_in.bits.i0v <= _T_858 @[dec_decode_ctl.scala 798:27]
-    node _T_859 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 799:37]
-    node _T_860 = and(r_d.valid, _T_859) @[dec_decode_ctl.scala 799:35]
-    r_d_in.valid <= _T_860 @[dec_decode_ctl.scala 799:20]
-    node _T_861 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 800:51]
-    node _T_862 = and(r_d.bits.i0load, _T_861) @[dec_decode_ctl.scala 800:49]
-    r_d_in.bits.i0load <= _T_862 @[dec_decode_ctl.scala 800:27]
-    node _T_863 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 801:51]
-    node _T_864 = and(r_d.bits.i0store, _T_863) @[dec_decode_ctl.scala 801:49]
-    r_d_in.bits.i0store <= _T_864 @[dec_decode_ctl.scala 801:27]
-    node _T_865 = bits(i0_wb_ctl_en, 0, 0) @[dec_decode_ctl.scala 803:66]
+    r_d.bits.csrwaddr <= _T_856.bits.csrwaddr @[dec_decode_ctl.scala 796:7]
+    r_d.bits.csrwonly <= _T_856.bits.csrwonly @[dec_decode_ctl.scala 796:7]
+    r_d.bits.csrwen <= _T_856.bits.csrwen @[dec_decode_ctl.scala 796:7]
+    r_d.bits.i0v <= _T_856.bits.i0v @[dec_decode_ctl.scala 796:7]
+    r_d.bits.i0div <= _T_856.bits.i0div @[dec_decode_ctl.scala 796:7]
+    r_d.bits.i0store <= _T_856.bits.i0store @[dec_decode_ctl.scala 796:7]
+    r_d.bits.i0load <= _T_856.bits.i0load @[dec_decode_ctl.scala 796:7]
+    r_d.bits.i0rd <= _T_856.bits.i0rd @[dec_decode_ctl.scala 796:7]
+    r_d.valid <= _T_856.valid @[dec_decode_ctl.scala 796:7]
+    r_d_in.bits.csrwaddr <= r_d.bits.csrwaddr @[dec_decode_ctl.scala 797:10]
+    r_d_in.bits.csrwonly <= r_d.bits.csrwonly @[dec_decode_ctl.scala 797:10]
+    r_d_in.bits.csrwen <= r_d.bits.csrwen @[dec_decode_ctl.scala 797:10]
+    r_d_in.bits.i0v <= r_d.bits.i0v @[dec_decode_ctl.scala 797:10]
+    r_d_in.bits.i0div <= r_d.bits.i0div @[dec_decode_ctl.scala 797:10]
+    r_d_in.bits.i0store <= r_d.bits.i0store @[dec_decode_ctl.scala 797:10]
+    r_d_in.bits.i0load <= r_d.bits.i0load @[dec_decode_ctl.scala 797:10]
+    r_d_in.bits.i0rd <= r_d.bits.i0rd @[dec_decode_ctl.scala 797:10]
+    r_d_in.valid <= r_d.valid @[dec_decode_ctl.scala 797:10]
+    r_d_in.bits.i0rd <= r_d.bits.i0rd @[dec_decode_ctl.scala 798:22]
+    node _T_857 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 800:51]
+    node _T_858 = and(r_d.bits.i0v, _T_857) @[dec_decode_ctl.scala 800:49]
+    r_d_in.bits.i0v <= _T_858 @[dec_decode_ctl.scala 800:27]
+    node _T_859 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 801:37]
+    node _T_860 = and(r_d.valid, _T_859) @[dec_decode_ctl.scala 801:35]
+    r_d_in.valid <= _T_860 @[dec_decode_ctl.scala 801:20]
+    node _T_861 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 802:51]
+    node _T_862 = and(r_d.bits.i0load, _T_861) @[dec_decode_ctl.scala 802:49]
+    r_d_in.bits.i0load <= _T_862 @[dec_decode_ctl.scala 802:27]
+    node _T_863 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 803:51]
+    node _T_864 = and(r_d.bits.i0store, _T_863) @[dec_decode_ctl.scala 803:49]
+    r_d_in.bits.i0store <= _T_864 @[dec_decode_ctl.scala 803:27]
+    node _T_865 = bits(i0_wb_ctl_en, 0, 0) @[dec_decode_ctl.scala 805:66]
     wire _T_866 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[lib.scala 630:37]
     _T_866.bits.csrwaddr <= UInt<12>("h00") @[lib.scala 630:37]
     _T_866.bits.csrwonly <= UInt<1>("h00") @[lib.scala 630:37]
@@ -7398,29 +7398,29 @@ circuit dec :
       _T_867.bits.i0rd <= r_d_in.bits.i0rd @[Reg.scala 28:23]
       _T_867.valid <= r_d_in.valid @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    wbd.bits.csrwaddr <= _T_867.bits.csrwaddr @[dec_decode_ctl.scala 803:7]
-    wbd.bits.csrwonly <= _T_867.bits.csrwonly @[dec_decode_ctl.scala 803:7]
-    wbd.bits.csrwen <= _T_867.bits.csrwen @[dec_decode_ctl.scala 803:7]
-    wbd.bits.i0v <= _T_867.bits.i0v @[dec_decode_ctl.scala 803:7]
-    wbd.bits.i0div <= _T_867.bits.i0div @[dec_decode_ctl.scala 803:7]
-    wbd.bits.i0store <= _T_867.bits.i0store @[dec_decode_ctl.scala 803:7]
-    wbd.bits.i0load <= _T_867.bits.i0load @[dec_decode_ctl.scala 803:7]
-    wbd.bits.i0rd <= _T_867.bits.i0rd @[dec_decode_ctl.scala 803:7]
-    wbd.valid <= _T_867.valid @[dec_decode_ctl.scala 803:7]
-    io.dec_i0_waddr_r <= r_d_in.bits.i0rd @[dec_decode_ctl.scala 805:27]
-    node _T_868 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[dec_decode_ctl.scala 806:47]
-    node _T_869 = and(r_d_in.bits.i0v, _T_868) @[dec_decode_ctl.scala 806:45]
-    i0_wen_r <= _T_869 @[dec_decode_ctl.scala 806:25]
-    node _T_870 = eq(r_d_in.bits.i0div, UInt<1>("h00")) @[dec_decode_ctl.scala 807:49]
-    node _T_871 = and(i0_wen_r, _T_870) @[dec_decode_ctl.scala 807:47]
-    node _T_872 = eq(i0_load_kill_wen_r, UInt<1>("h00")) @[dec_decode_ctl.scala 807:70]
-    node _T_873 = and(_T_871, _T_872) @[dec_decode_ctl.scala 807:68]
-    io.dec_i0_wen_r <= _T_873 @[dec_decode_ctl.scala 807:32]
-    io.dec_i0_wdata_r <= i0_result_corr_r @[dec_decode_ctl.scala 808:26]
-    node _T_874 = or(x_d.bits.i0v, x_d.bits.csrwen) @[dec_decode_ctl.scala 811:74]
-    node _T_875 = or(_T_874, debug_valid_x) @[dec_decode_ctl.scala 811:92]
-    node _T_876 = and(i0_r_data_en, _T_875) @[dec_decode_ctl.scala 811:58]
-    node _T_877 = eq(_T_876, UInt<1>("h01")) @[dec_decode_ctl.scala 811:110]
+    wbd.bits.csrwaddr <= _T_867.bits.csrwaddr @[dec_decode_ctl.scala 805:7]
+    wbd.bits.csrwonly <= _T_867.bits.csrwonly @[dec_decode_ctl.scala 805:7]
+    wbd.bits.csrwen <= _T_867.bits.csrwen @[dec_decode_ctl.scala 805:7]
+    wbd.bits.i0v <= _T_867.bits.i0v @[dec_decode_ctl.scala 805:7]
+    wbd.bits.i0div <= _T_867.bits.i0div @[dec_decode_ctl.scala 805:7]
+    wbd.bits.i0store <= _T_867.bits.i0store @[dec_decode_ctl.scala 805:7]
+    wbd.bits.i0load <= _T_867.bits.i0load @[dec_decode_ctl.scala 805:7]
+    wbd.bits.i0rd <= _T_867.bits.i0rd @[dec_decode_ctl.scala 805:7]
+    wbd.valid <= _T_867.valid @[dec_decode_ctl.scala 805:7]
+    io.dec_i0_waddr_r <= r_d_in.bits.i0rd @[dec_decode_ctl.scala 807:27]
+    node _T_868 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[dec_decode_ctl.scala 808:47]
+    node _T_869 = and(r_d_in.bits.i0v, _T_868) @[dec_decode_ctl.scala 808:45]
+    i0_wen_r <= _T_869 @[dec_decode_ctl.scala 808:25]
+    node _T_870 = eq(r_d_in.bits.i0div, UInt<1>("h00")) @[dec_decode_ctl.scala 809:49]
+    node _T_871 = and(i0_wen_r, _T_870) @[dec_decode_ctl.scala 809:47]
+    node _T_872 = eq(i0_load_kill_wen_r, UInt<1>("h00")) @[dec_decode_ctl.scala 809:70]
+    node _T_873 = and(_T_871, _T_872) @[dec_decode_ctl.scala 809:68]
+    io.dec_i0_wen_r <= _T_873 @[dec_decode_ctl.scala 809:32]
+    io.dec_i0_wdata_r <= i0_result_corr_r @[dec_decode_ctl.scala 810:26]
+    node _T_874 = or(x_d.bits.i0v, x_d.bits.csrwen) @[dec_decode_ctl.scala 813:74]
+    node _T_875 = or(_T_874, debug_valid_x) @[dec_decode_ctl.scala 813:92]
+    node _T_876 = and(i0_r_data_en, _T_875) @[dec_decode_ctl.scala 813:58]
+    node _T_877 = eq(_T_876, UInt<1>("h01")) @[dec_decode_ctl.scala 813:110]
     inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 404:23]
     rvclkhdr_4.clock <= clock
     rvclkhdr_4.reset <= reset
@@ -7431,18 +7431,18 @@ circuit dec :
     when _T_877 : @[Reg.scala 28:19]
       i0_result_r_raw <= i0_result_x @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    node _T_878 = and(x_d.bits.i0v, x_d.bits.i0load) @[dec_decode_ctl.scala 817:47]
-    node _T_879 = bits(_T_878, 0, 0) @[dec_decode_ctl.scala 817:66]
-    node _T_880 = mux(_T_879, io.lsu_result_m, io.decode_exu.exu_i0_result_x) @[dec_decode_ctl.scala 817:32]
-    i0_result_x <= _T_880 @[dec_decode_ctl.scala 817:26]
-    i0_result_r <= i0_result_r_raw @[dec_decode_ctl.scala 818:26]
-    node _T_881 = and(r_d.bits.i0v, r_d.bits.i0load) @[dec_decode_ctl.scala 822:42]
-    node _T_882 = bits(_T_881, 0, 0) @[dec_decode_ctl.scala 822:61]
-    node _T_883 = mux(_T_882, io.lsu_result_corr_r, i0_result_r_raw) @[dec_decode_ctl.scala 822:27]
-    i0_result_corr_r <= _T_883 @[dec_decode_ctl.scala 822:21]
-    node _T_884 = eq(i0_dp.jal, UInt<1>("h00")) @[dec_decode_ctl.scala 823:73]
-    node _T_885 = and(io.decode_exu.i0_ap.predict_nt, _T_884) @[dec_decode_ctl.scala 823:71]
-    node _T_886 = bits(_T_885, 0, 0) @[dec_decode_ctl.scala 823:85]
+    node _T_878 = and(x_d.bits.i0v, x_d.bits.i0load) @[dec_decode_ctl.scala 819:47]
+    node _T_879 = bits(_T_878, 0, 0) @[dec_decode_ctl.scala 819:66]
+    node _T_880 = mux(_T_879, io.lsu_result_m, io.decode_exu.exu_i0_result_x) @[dec_decode_ctl.scala 819:32]
+    i0_result_x <= _T_880 @[dec_decode_ctl.scala 819:26]
+    i0_result_r <= i0_result_r_raw @[dec_decode_ctl.scala 820:26]
+    node _T_881 = and(r_d.bits.i0v, r_d.bits.i0load) @[dec_decode_ctl.scala 824:42]
+    node _T_882 = bits(_T_881, 0, 0) @[dec_decode_ctl.scala 824:61]
+    node _T_883 = mux(_T_882, io.lsu_result_corr_r, i0_result_r_raw) @[dec_decode_ctl.scala 824:27]
+    i0_result_corr_r <= _T_883 @[dec_decode_ctl.scala 824:21]
+    node _T_884 = eq(i0_dp.jal, UInt<1>("h00")) @[dec_decode_ctl.scala 825:73]
+    node _T_885 = and(io.decode_exu.i0_ap.predict_nt, _T_884) @[dec_decode_ctl.scala 825:71]
+    node _T_886 = bits(_T_885, 0, 0) @[dec_decode_ctl.scala 825:85]
     wire _T_887 : UInt<1>[10] @[lib.scala 12:48]
     _T_887[0] <= UInt<1>("h00") @[lib.scala 12:48]
     _T_887[1] <= UInt<1>("h00") @[lib.scala 12:48]
@@ -7465,11 +7465,11 @@ circuit dec :
     node _T_896 = cat(_T_895, _T_887[9]) @[Cat.scala 29:58]
     node _T_897 = cat(_T_896, io.dec_i0_pc4_d) @[Cat.scala 29:58]
     node _T_898 = cat(_T_897, i0_ap_pc2) @[Cat.scala 29:58]
-    node _T_899 = mux(_T_886, i0_br_offset, _T_898) @[dec_decode_ctl.scala 823:38]
-    io.dec_alu.dec_i0_br_immed_d <= _T_899 @[dec_decode_ctl.scala 823:32]
+    node _T_899 = mux(_T_886, i0_br_offset, _T_898) @[dec_decode_ctl.scala 825:38]
+    io.dec_alu.dec_i0_br_immed_d <= _T_899 @[dec_decode_ctl.scala 825:32]
     wire last_br_immed_d : UInt<12>
     last_br_immed_d <= UInt<1>("h00")
-    node _T_900 = bits(io.decode_exu.i0_ap.predict_nt, 0, 0) @[dec_decode_ctl.scala 825:59]
+    node _T_900 = bits(io.decode_exu.i0_ap.predict_nt, 0, 0) @[dec_decode_ctl.scala 827:59]
     wire _T_901 : UInt<1>[10] @[lib.scala 12:48]
     _T_901[0] <= UInt<1>("h00") @[lib.scala 12:48]
     _T_901[1] <= UInt<1>("h00") @[lib.scala 12:48]
@@ -7492,11 +7492,11 @@ circuit dec :
     node _T_910 = cat(_T_909, _T_901[9]) @[Cat.scala 29:58]
     node _T_911 = cat(_T_910, io.dec_i0_pc4_d) @[Cat.scala 29:58]
     node _T_912 = cat(_T_911, i0_ap_pc2) @[Cat.scala 29:58]
-    node _T_913 = mux(_T_900, _T_912, i0_br_offset) @[dec_decode_ctl.scala 825:25]
-    last_br_immed_d <= _T_913 @[dec_decode_ctl.scala 825:19]
+    node _T_913 = mux(_T_900, _T_912, i0_br_offset) @[dec_decode_ctl.scala 827:25]
+    last_br_immed_d <= _T_913 @[dec_decode_ctl.scala 827:19]
     wire last_br_immed_x : UInt<12>
     last_br_immed_x <= UInt<1>("h00")
-    node _T_914 = bits(i0_x_data_en, 0, 0) @[dec_decode_ctl.scala 827:58]
+    node _T_914 = bits(i0_x_data_en, 0, 0) @[dec_decode_ctl.scala 829:58]
     inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 404:23]
     rvclkhdr_5.clock <= clock
     rvclkhdr_5.reset <= reset
@@ -7507,46 +7507,46 @@ circuit dec :
     when _T_914 : @[Reg.scala 28:19]
       _T_915 <= last_br_immed_d @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    last_br_immed_x <= _T_915 @[dec_decode_ctl.scala 827:19]
-    node _T_916 = and(x_d.bits.i0div, x_d.valid) @[dec_decode_ctl.scala 831:45]
-    node _T_917 = and(r_d.bits.i0div, r_d.valid) @[dec_decode_ctl.scala 831:76]
-    node div_e1_to_r = or(_T_916, _T_917) @[dec_decode_ctl.scala 831:58]
-    node _T_918 = and(x_d.bits.i0div, x_d.valid) @[dec_decode_ctl.scala 833:48]
-    node _T_919 = eq(x_d.bits.i0rd, UInt<5>("h00")) @[dec_decode_ctl.scala 833:77]
-    node _T_920 = and(_T_918, _T_919) @[dec_decode_ctl.scala 833:60]
-    node _T_921 = and(x_d.bits.i0div, x_d.valid) @[dec_decode_ctl.scala 834:21]
-    node _T_922 = and(_T_921, io.dec_tlu_flush_lower_r) @[dec_decode_ctl.scala 834:33]
-    node _T_923 = or(_T_920, _T_922) @[dec_decode_ctl.scala 833:94]
-    node _T_924 = and(r_d.bits.i0div, r_d.valid) @[dec_decode_ctl.scala 835:21]
-    node _T_925 = and(_T_924, io.dec_tlu_flush_lower_r) @[dec_decode_ctl.scala 835:33]
-    node _T_926 = and(_T_925, io.dec_tlu_i0_kill_writeb_r) @[dec_decode_ctl.scala 835:60]
-    node div_flush = or(_T_923, _T_926) @[dec_decode_ctl.scala 834:62]
-    node _T_927 = and(io.dec_div_active, div_flush) @[dec_decode_ctl.scala 839:51]
-    node _T_928 = eq(div_e1_to_r, UInt<1>("h00")) @[dec_decode_ctl.scala 840:26]
-    node _T_929 = and(io.dec_div_active, _T_928) @[dec_decode_ctl.scala 840:24]
-    node _T_930 = eq(r_d.bits.i0rd, io.div_waddr_wb) @[dec_decode_ctl.scala 840:56]
-    node _T_931 = and(_T_929, _T_930) @[dec_decode_ctl.scala 840:39]
-    node _T_932 = and(_T_931, i0_wen_r) @[dec_decode_ctl.scala 840:77]
-    node nonblock_div_cancel = or(_T_927, _T_932) @[dec_decode_ctl.scala 839:65]
-    node _T_933 = bits(nonblock_div_cancel, 0, 0) @[dec_decode_ctl.scala 842:61]
-    io.dec_div.dec_div_cancel <= _T_933 @[dec_decode_ctl.scala 842:37]
-    node i0_div_decode_d = and(i0_legal_decode_d, i0_dp.div) @[dec_decode_ctl.scala 843:55]
-    node _T_934 = eq(io.exu_div_wren, UInt<1>("h00")) @[dec_decode_ctl.scala 845:59]
-    node _T_935 = and(io.dec_div_active, _T_934) @[dec_decode_ctl.scala 845:57]
-    node _T_936 = eq(nonblock_div_cancel, UInt<1>("h00")) @[dec_decode_ctl.scala 845:78]
-    node _T_937 = and(_T_935, _T_936) @[dec_decode_ctl.scala 845:76]
-    node _T_938 = or(i0_div_decode_d, _T_937) @[dec_decode_ctl.scala 845:36]
-    div_active_in <= _T_938 @[dec_decode_ctl.scala 845:17]
-    node _T_939 = and(io.decode_exu.dec_i0_rs1_en_d, io.dec_div_active) @[dec_decode_ctl.scala 850:60]
-    node _T_940 = eq(io.div_waddr_wb, i0r.rs1) @[dec_decode_ctl.scala 850:99]
-    node _T_941 = and(_T_939, _T_940) @[dec_decode_ctl.scala 850:80]
-    node _T_942 = and(io.decode_exu.dec_i0_rs2_en_d, io.dec_div_active) @[dec_decode_ctl.scala 851:36]
-    node _T_943 = eq(io.div_waddr_wb, i0r.rs2) @[dec_decode_ctl.scala 851:75]
-    node _T_944 = and(_T_942, _T_943) @[dec_decode_ctl.scala 851:56]
-    node _T_945 = or(_T_941, _T_944) @[dec_decode_ctl.scala 850:113]
-    i0_nonblock_div_stall <= _T_945 @[dec_decode_ctl.scala 850:26]
-    node trace_enable = not(io.dec_tlu_trace_disable) @[dec_decode_ctl.scala 858:22]
-    node _T_946 = bits(i0_div_decode_d, 0, 0) @[dec_decode_ctl.scala 860:58]
+    last_br_immed_x <= _T_915 @[dec_decode_ctl.scala 829:19]
+    node _T_916 = and(x_d.bits.i0div, x_d.valid) @[dec_decode_ctl.scala 833:45]
+    node _T_917 = and(r_d.bits.i0div, r_d.valid) @[dec_decode_ctl.scala 833:76]
+    node div_e1_to_r = or(_T_916, _T_917) @[dec_decode_ctl.scala 833:58]
+    node _T_918 = and(x_d.bits.i0div, x_d.valid) @[dec_decode_ctl.scala 835:48]
+    node _T_919 = eq(x_d.bits.i0rd, UInt<5>("h00")) @[dec_decode_ctl.scala 835:77]
+    node _T_920 = and(_T_918, _T_919) @[dec_decode_ctl.scala 835:60]
+    node _T_921 = and(x_d.bits.i0div, x_d.valid) @[dec_decode_ctl.scala 836:21]
+    node _T_922 = and(_T_921, io.dec_tlu_flush_lower_r) @[dec_decode_ctl.scala 836:33]
+    node _T_923 = or(_T_920, _T_922) @[dec_decode_ctl.scala 835:94]
+    node _T_924 = and(r_d.bits.i0div, r_d.valid) @[dec_decode_ctl.scala 837:21]
+    node _T_925 = and(_T_924, io.dec_tlu_flush_lower_r) @[dec_decode_ctl.scala 837:33]
+    node _T_926 = and(_T_925, io.dec_tlu_i0_kill_writeb_r) @[dec_decode_ctl.scala 837:60]
+    node div_flush = or(_T_923, _T_926) @[dec_decode_ctl.scala 836:62]
+    node _T_927 = and(io.dec_div_active, div_flush) @[dec_decode_ctl.scala 841:51]
+    node _T_928 = eq(div_e1_to_r, UInt<1>("h00")) @[dec_decode_ctl.scala 842:26]
+    node _T_929 = and(io.dec_div_active, _T_928) @[dec_decode_ctl.scala 842:24]
+    node _T_930 = eq(r_d.bits.i0rd, io.div_waddr_wb) @[dec_decode_ctl.scala 842:56]
+    node _T_931 = and(_T_929, _T_930) @[dec_decode_ctl.scala 842:39]
+    node _T_932 = and(_T_931, i0_wen_r) @[dec_decode_ctl.scala 842:77]
+    node nonblock_div_cancel = or(_T_927, _T_932) @[dec_decode_ctl.scala 841:65]
+    node _T_933 = bits(nonblock_div_cancel, 0, 0) @[dec_decode_ctl.scala 844:61]
+    io.dec_div.dec_div_cancel <= _T_933 @[dec_decode_ctl.scala 844:37]
+    node i0_div_decode_d = and(i0_legal_decode_d, i0_dp.div) @[dec_decode_ctl.scala 845:55]
+    node _T_934 = eq(io.exu_div_wren, UInt<1>("h00")) @[dec_decode_ctl.scala 847:59]
+    node _T_935 = and(io.dec_div_active, _T_934) @[dec_decode_ctl.scala 847:57]
+    node _T_936 = eq(nonblock_div_cancel, UInt<1>("h00")) @[dec_decode_ctl.scala 847:78]
+    node _T_937 = and(_T_935, _T_936) @[dec_decode_ctl.scala 847:76]
+    node _T_938 = or(i0_div_decode_d, _T_937) @[dec_decode_ctl.scala 847:36]
+    div_active_in <= _T_938 @[dec_decode_ctl.scala 847:17]
+    node _T_939 = and(io.decode_exu.dec_i0_rs1_en_d, io.dec_div_active) @[dec_decode_ctl.scala 852:60]
+    node _T_940 = eq(io.div_waddr_wb, i0r.rs1) @[dec_decode_ctl.scala 852:99]
+    node _T_941 = and(_T_939, _T_940) @[dec_decode_ctl.scala 852:80]
+    node _T_942 = and(io.decode_exu.dec_i0_rs2_en_d, io.dec_div_active) @[dec_decode_ctl.scala 853:36]
+    node _T_943 = eq(io.div_waddr_wb, i0r.rs2) @[dec_decode_ctl.scala 853:75]
+    node _T_944 = and(_T_942, _T_943) @[dec_decode_ctl.scala 853:56]
+    node _T_945 = or(_T_941, _T_944) @[dec_decode_ctl.scala 852:113]
+    i0_nonblock_div_stall <= _T_945 @[dec_decode_ctl.scala 852:26]
+    node trace_enable = not(io.dec_tlu_trace_disable) @[dec_decode_ctl.scala 860:22]
+    node _T_946 = bits(i0_div_decode_d, 0, 0) @[dec_decode_ctl.scala 862:58]
     inst rvclkhdr_6 of rvclkhdr_6 @[lib.scala 404:23]
     rvclkhdr_6.clock <= clock
     rvclkhdr_6.reset <= reset
@@ -7557,8 +7557,8 @@ circuit dec :
     when _T_946 : @[Reg.scala 28:19]
       _T_947 <= i0r.rd @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    io.div_waddr_wb <= _T_947 @[dec_decode_ctl.scala 860:19]
-    node _T_948 = and(i0_x_data_en, trace_enable) @[dec_decode_ctl.scala 862:50]
+    io.div_waddr_wb <= _T_947 @[dec_decode_ctl.scala 862:19]
+    node _T_948 = and(i0_x_data_en, trace_enable) @[dec_decode_ctl.scala 864:50]
     node _T_949 = bits(_T_948, 0, 0) @[lib.scala 8:44]
     inst rvclkhdr_7 of rvclkhdr_7 @[lib.scala 404:23]
     rvclkhdr_7.clock <= clock
@@ -7570,7 +7570,7 @@ circuit dec :
     when _T_949 : @[Reg.scala 28:19]
       i0_inst_x <= i0_inst_d @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    node _T_950 = and(i0_r_data_en, trace_enable) @[dec_decode_ctl.scala 863:50]
+    node _T_950 = and(i0_r_data_en, trace_enable) @[dec_decode_ctl.scala 865:50]
     node _T_951 = bits(_T_950, 0, 0) @[lib.scala 8:44]
     inst rvclkhdr_8 of rvclkhdr_8 @[lib.scala 404:23]
     rvclkhdr_8.clock <= clock
@@ -7582,7 +7582,7 @@ circuit dec :
     when _T_951 : @[Reg.scala 28:19]
       i0_inst_r <= i0_inst_x @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    node _T_952 = and(i0_wb_data_en, trace_enable) @[dec_decode_ctl.scala 865:51]
+    node _T_952 = and(i0_wb_data_en, trace_enable) @[dec_decode_ctl.scala 867:51]
     node _T_953 = bits(_T_952, 0, 0) @[lib.scala 8:44]
     inst rvclkhdr_9 of rvclkhdr_9 @[lib.scala 404:23]
     rvclkhdr_9.clock <= clock
@@ -7594,7 +7594,7 @@ circuit dec :
     when _T_953 : @[Reg.scala 28:19]
       i0_inst_wb <= i0_inst_r @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    node _T_954 = and(i0_wb_data_en, trace_enable) @[dec_decode_ctl.scala 866:54]
+    node _T_954 = and(i0_wb_data_en, trace_enable) @[dec_decode_ctl.scala 868:54]
     node _T_955 = bits(_T_954, 0, 0) @[lib.scala 8:44]
     inst rvclkhdr_10 of rvclkhdr_10 @[lib.scala 404:23]
     rvclkhdr_10.clock <= clock
@@ -7606,16 +7606,16 @@ circuit dec :
     when _T_955 : @[Reg.scala 28:19]
       i0_pc_wb <= io.dec_tlu_i0_pc_r @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    io.dec_i0_inst_wb <= i0_inst_wb @[dec_decode_ctl.scala 868:21]
-    io.dec_i0_pc_wb <= i0_pc_wb @[dec_decode_ctl.scala 869:19]
-    node _T_956 = bits(i0_r_data_en, 0, 0) @[dec_decode_ctl.scala 870:67]
+    io.dec_i0_inst_wb <= i0_inst_wb @[dec_decode_ctl.scala 870:21]
+    io.dec_i0_pc_wb <= i0_pc_wb @[dec_decode_ctl.scala 871:19]
+    node _T_956 = bits(i0_r_data_en, 0, 0) @[dec_decode_ctl.scala 872:67]
     wire _T_957 : UInt<31> @[lib.scala 648:38]
     _T_957 <= UInt<1>("h00") @[lib.scala 648:38]
     reg dec_i0_pc_r : UInt, clock with : (reset => (reset, _T_957)) @[Reg.scala 27:20]
     when _T_956 : @[Reg.scala 28:19]
       dec_i0_pc_r <= io.dec_alu.exu_i0_pc_x @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    io.dec_tlu_i0_pc_r <= dec_i0_pc_r @[dec_decode_ctl.scala 872:27]
+    io.dec_tlu_i0_pc_r <= dec_i0_pc_r @[dec_decode_ctl.scala 874:27]
     node _T_958 = cat(io.dec_alu.exu_i0_pc_x, UInt<1>("h00")) @[Cat.scala 29:58]
     node _T_959 = cat(last_br_immed_x, UInt<1>("h00")) @[Cat.scala 29:58]
     node _T_960 = bits(_T_958, 12, 1) @[lib.scala 68:24]
@@ -7651,152 +7651,152 @@ circuit dec :
     node _T_989 = bits(_T_962, 11, 0) @[lib.scala 74:94]
     node _T_990 = cat(_T_988, _T_989) @[Cat.scala 29:58]
     node temp_pred_correct_npc_x = cat(_T_990, UInt<1>("h00")) @[Cat.scala 29:58]
-    node _T_991 = bits(temp_pred_correct_npc_x, 31, 1) @[dec_decode_ctl.scala 877:62]
-    io.decode_exu.pred_correct_npc_x <= _T_991 @[dec_decode_ctl.scala 877:36]
-    node _T_992 = and(io.decode_exu.dec_i0_rs1_en_d, x_d.bits.i0v) @[dec_decode_ctl.scala 881:59]
-    node _T_993 = eq(x_d.bits.i0rd, i0r.rs1) @[dec_decode_ctl.scala 881:91]
-    node i0_rs1_depend_i0_x = and(_T_992, _T_993) @[dec_decode_ctl.scala 881:74]
-    node _T_994 = and(io.decode_exu.dec_i0_rs1_en_d, r_d.bits.i0v) @[dec_decode_ctl.scala 882:59]
-    node _T_995 = eq(r_d.bits.i0rd, i0r.rs1) @[dec_decode_ctl.scala 882:91]
-    node i0_rs1_depend_i0_r = and(_T_994, _T_995) @[dec_decode_ctl.scala 882:74]
-    node _T_996 = and(io.decode_exu.dec_i0_rs2_en_d, x_d.bits.i0v) @[dec_decode_ctl.scala 884:59]
-    node _T_997 = eq(x_d.bits.i0rd, i0r.rs2) @[dec_decode_ctl.scala 884:91]
-    node i0_rs2_depend_i0_x = and(_T_996, _T_997) @[dec_decode_ctl.scala 884:74]
-    node _T_998 = and(io.decode_exu.dec_i0_rs2_en_d, r_d.bits.i0v) @[dec_decode_ctl.scala 885:59]
-    node _T_999 = eq(r_d.bits.i0rd, i0r.rs2) @[dec_decode_ctl.scala 885:91]
-    node i0_rs2_depend_i0_r = and(_T_998, _T_999) @[dec_decode_ctl.scala 885:74]
-    node _T_1000 = bits(i0_rs1_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 887:44]
-    node _T_1001 = bits(i0_rs1_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 887:81]
-    wire _T_1002 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 887:109]
-    _T_1002.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 887:109]
-    _T_1002.load <= UInt<1>("h00") @[dec_decode_ctl.scala 887:109]
-    _T_1002.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 887:109]
-    node _T_1003 = mux(_T_1001, i0_r_c, _T_1002) @[dec_decode_ctl.scala 887:61]
-    node _T_1004 = mux(_T_1000, i0_x_c, _T_1003) @[dec_decode_ctl.scala 887:24]
-    i0_rs1_class_d.alu <= _T_1004.alu @[dec_decode_ctl.scala 887:18]
-    i0_rs1_class_d.load <= _T_1004.load @[dec_decode_ctl.scala 887:18]
-    i0_rs1_class_d.mul <= _T_1004.mul @[dec_decode_ctl.scala 887:18]
-    node _T_1005 = bits(i0_rs1_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 888:44]
-    node _T_1006 = bits(i0_rs1_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 888:83]
-    node _T_1007 = mux(_T_1006, UInt<2>("h02"), UInt<1>("h00")) @[dec_decode_ctl.scala 888:63]
-    node _T_1008 = mux(_T_1005, UInt<2>("h01"), _T_1007) @[dec_decode_ctl.scala 888:24]
-    i0_rs1_depth_d <= _T_1008 @[dec_decode_ctl.scala 888:18]
-    node _T_1009 = bits(i0_rs2_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 889:44]
-    node _T_1010 = bits(i0_rs2_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 889:81]
-    wire _T_1011 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 889:109]
-    _T_1011.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 889:109]
-    _T_1011.load <= UInt<1>("h00") @[dec_decode_ctl.scala 889:109]
-    _T_1011.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 889:109]
-    node _T_1012 = mux(_T_1010, i0_r_c, _T_1011) @[dec_decode_ctl.scala 889:61]
-    node _T_1013 = mux(_T_1009, i0_x_c, _T_1012) @[dec_decode_ctl.scala 889:24]
-    i0_rs2_class_d.alu <= _T_1013.alu @[dec_decode_ctl.scala 889:18]
-    i0_rs2_class_d.load <= _T_1013.load @[dec_decode_ctl.scala 889:18]
-    i0_rs2_class_d.mul <= _T_1013.mul @[dec_decode_ctl.scala 889:18]
-    node _T_1014 = bits(i0_rs2_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 890:44]
-    node _T_1015 = bits(i0_rs2_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 890:83]
-    node _T_1016 = mux(_T_1015, UInt<2>("h02"), UInt<1>("h00")) @[dec_decode_ctl.scala 890:63]
-    node _T_1017 = mux(_T_1014, UInt<2>("h01"), _T_1016) @[dec_decode_ctl.scala 890:24]
-    i0_rs2_depth_d <= _T_1017 @[dec_decode_ctl.scala 890:18]
-    i0_load_block_d <= UInt<1>("h00") @[dec_decode_ctl.scala 900:21]
-    node _T_1018 = or(i0_dp.load, i0_dp.store) @[dec_decode_ctl.scala 901:43]
-    node _T_1019 = bits(i0_rs1_depth_d, 0, 0) @[dec_decode_ctl.scala 901:74]
-    node _T_1020 = and(_T_1018, _T_1019) @[dec_decode_ctl.scala 901:58]
-    node _T_1021 = and(_T_1020, i0_rs1_class_d.load) @[dec_decode_ctl.scala 901:78]
-    load_ldst_bypass_d <= _T_1021 @[dec_decode_ctl.scala 901:27]
-    node _T_1022 = bits(i0_rs2_depth_d, 0, 0) @[dec_decode_ctl.scala 902:59]
-    node _T_1023 = and(i0_dp.store, _T_1022) @[dec_decode_ctl.scala 902:43]
-    node _T_1024 = and(_T_1023, i0_rs2_class_d.load) @[dec_decode_ctl.scala 902:63]
-    store_data_bypass_d <= _T_1024 @[dec_decode_ctl.scala 902:25]
-    store_data_bypass_m <= UInt<1>("h00") @[dec_decode_ctl.scala 903:25]
-    node _T_1025 = and(io.decode_exu.dec_i0_rs1_en_d, io.dec_nonblock_load_wen) @[dec_decode_ctl.scala 907:73]
-    node _T_1026 = eq(io.dec_nonblock_load_waddr, i0r.rs1) @[dec_decode_ctl.scala 907:130]
-    node i0_rs1_nonblock_load_bypass_en_d = and(_T_1025, _T_1026) @[dec_decode_ctl.scala 907:100]
-    node _T_1027 = and(io.decode_exu.dec_i0_rs2_en_d, io.dec_nonblock_load_wen) @[dec_decode_ctl.scala 909:73]
-    node _T_1028 = eq(io.dec_nonblock_load_waddr, i0r.rs2) @[dec_decode_ctl.scala 909:130]
-    node i0_rs2_nonblock_load_bypass_en_d = and(_T_1027, _T_1028) @[dec_decode_ctl.scala 909:100]
-    node _T_1029 = bits(i0_rs1_depth_d, 0, 0) @[dec_decode_ctl.scala 912:41]
-    node _T_1030 = or(i0_rs1_class_d.alu, i0_rs1_class_d.mul) @[dec_decode_ctl.scala 912:66]
-    node _T_1031 = and(_T_1029, _T_1030) @[dec_decode_ctl.scala 912:45]
-    node _T_1032 = bits(i0_rs1_depth_d, 0, 0) @[dec_decode_ctl.scala 912:104]
-    node _T_1033 = and(_T_1032, i0_rs1_class_d.load) @[dec_decode_ctl.scala 912:108]
-    node _T_1034 = bits(i0_rs1_depth_d, 1, 1) @[dec_decode_ctl.scala 912:149]
-    node _T_1035 = or(i0_rs1_class_d.alu, i0_rs1_class_d.mul) @[dec_decode_ctl.scala 912:175]
-    node _T_1036 = or(_T_1035, i0_rs1_class_d.load) @[dec_decode_ctl.scala 912:196]
-    node _T_1037 = and(_T_1034, _T_1036) @[dec_decode_ctl.scala 912:153]
+    node _T_991 = bits(temp_pred_correct_npc_x, 31, 1) @[dec_decode_ctl.scala 879:62]
+    io.decode_exu.pred_correct_npc_x <= _T_991 @[dec_decode_ctl.scala 879:36]
+    node _T_992 = and(io.decode_exu.dec_i0_rs1_en_d, x_d.bits.i0v) @[dec_decode_ctl.scala 883:59]
+    node _T_993 = eq(x_d.bits.i0rd, i0r.rs1) @[dec_decode_ctl.scala 883:91]
+    node i0_rs1_depend_i0_x = and(_T_992, _T_993) @[dec_decode_ctl.scala 883:74]
+    node _T_994 = and(io.decode_exu.dec_i0_rs1_en_d, r_d.bits.i0v) @[dec_decode_ctl.scala 884:59]
+    node _T_995 = eq(r_d.bits.i0rd, i0r.rs1) @[dec_decode_ctl.scala 884:91]
+    node i0_rs1_depend_i0_r = and(_T_994, _T_995) @[dec_decode_ctl.scala 884:74]
+    node _T_996 = and(io.decode_exu.dec_i0_rs2_en_d, x_d.bits.i0v) @[dec_decode_ctl.scala 886:59]
+    node _T_997 = eq(x_d.bits.i0rd, i0r.rs2) @[dec_decode_ctl.scala 886:91]
+    node i0_rs2_depend_i0_x = and(_T_996, _T_997) @[dec_decode_ctl.scala 886:74]
+    node _T_998 = and(io.decode_exu.dec_i0_rs2_en_d, r_d.bits.i0v) @[dec_decode_ctl.scala 887:59]
+    node _T_999 = eq(r_d.bits.i0rd, i0r.rs2) @[dec_decode_ctl.scala 887:91]
+    node i0_rs2_depend_i0_r = and(_T_998, _T_999) @[dec_decode_ctl.scala 887:74]
+    node _T_1000 = bits(i0_rs1_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 889:44]
+    node _T_1001 = bits(i0_rs1_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 889:81]
+    wire _T_1002 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 889:109]
+    _T_1002.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 889:109]
+    _T_1002.load <= UInt<1>("h00") @[dec_decode_ctl.scala 889:109]
+    _T_1002.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 889:109]
+    node _T_1003 = mux(_T_1001, i0_r_c, _T_1002) @[dec_decode_ctl.scala 889:61]
+    node _T_1004 = mux(_T_1000, i0_x_c, _T_1003) @[dec_decode_ctl.scala 889:24]
+    i0_rs1_class_d.alu <= _T_1004.alu @[dec_decode_ctl.scala 889:18]
+    i0_rs1_class_d.load <= _T_1004.load @[dec_decode_ctl.scala 889:18]
+    i0_rs1_class_d.mul <= _T_1004.mul @[dec_decode_ctl.scala 889:18]
+    node _T_1005 = bits(i0_rs1_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 890:44]
+    node _T_1006 = bits(i0_rs1_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 890:83]
+    node _T_1007 = mux(_T_1006, UInt<2>("h02"), UInt<1>("h00")) @[dec_decode_ctl.scala 890:63]
+    node _T_1008 = mux(_T_1005, UInt<2>("h01"), _T_1007) @[dec_decode_ctl.scala 890:24]
+    i0_rs1_depth_d <= _T_1008 @[dec_decode_ctl.scala 890:18]
+    node _T_1009 = bits(i0_rs2_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 891:44]
+    node _T_1010 = bits(i0_rs2_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 891:81]
+    wire _T_1011 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 891:109]
+    _T_1011.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 891:109]
+    _T_1011.load <= UInt<1>("h00") @[dec_decode_ctl.scala 891:109]
+    _T_1011.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 891:109]
+    node _T_1012 = mux(_T_1010, i0_r_c, _T_1011) @[dec_decode_ctl.scala 891:61]
+    node _T_1013 = mux(_T_1009, i0_x_c, _T_1012) @[dec_decode_ctl.scala 891:24]
+    i0_rs2_class_d.alu <= _T_1013.alu @[dec_decode_ctl.scala 891:18]
+    i0_rs2_class_d.load <= _T_1013.load @[dec_decode_ctl.scala 891:18]
+    i0_rs2_class_d.mul <= _T_1013.mul @[dec_decode_ctl.scala 891:18]
+    node _T_1014 = bits(i0_rs2_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 892:44]
+    node _T_1015 = bits(i0_rs2_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 892:83]
+    node _T_1016 = mux(_T_1015, UInt<2>("h02"), UInt<1>("h00")) @[dec_decode_ctl.scala 892:63]
+    node _T_1017 = mux(_T_1014, UInt<2>("h01"), _T_1016) @[dec_decode_ctl.scala 892:24]
+    i0_rs2_depth_d <= _T_1017 @[dec_decode_ctl.scala 892:18]
+    i0_load_block_d <= UInt<1>("h00") @[dec_decode_ctl.scala 902:21]
+    node _T_1018 = or(i0_dp.load, i0_dp.store) @[dec_decode_ctl.scala 903:43]
+    node _T_1019 = bits(i0_rs1_depth_d, 0, 0) @[dec_decode_ctl.scala 903:74]
+    node _T_1020 = and(_T_1018, _T_1019) @[dec_decode_ctl.scala 903:58]
+    node _T_1021 = and(_T_1020, i0_rs1_class_d.load) @[dec_decode_ctl.scala 903:78]
+    load_ldst_bypass_d <= _T_1021 @[dec_decode_ctl.scala 903:27]
+    node _T_1022 = bits(i0_rs2_depth_d, 0, 0) @[dec_decode_ctl.scala 904:59]
+    node _T_1023 = and(i0_dp.store, _T_1022) @[dec_decode_ctl.scala 904:43]
+    node _T_1024 = and(_T_1023, i0_rs2_class_d.load) @[dec_decode_ctl.scala 904:63]
+    store_data_bypass_d <= _T_1024 @[dec_decode_ctl.scala 904:25]
+    store_data_bypass_m <= UInt<1>("h00") @[dec_decode_ctl.scala 905:25]
+    node _T_1025 = and(io.decode_exu.dec_i0_rs1_en_d, io.dec_nonblock_load_wen) @[dec_decode_ctl.scala 909:73]
+    node _T_1026 = eq(io.dec_nonblock_load_waddr, i0r.rs1) @[dec_decode_ctl.scala 909:130]
+    node i0_rs1_nonblock_load_bypass_en_d = and(_T_1025, _T_1026) @[dec_decode_ctl.scala 909:100]
+    node _T_1027 = and(io.decode_exu.dec_i0_rs2_en_d, io.dec_nonblock_load_wen) @[dec_decode_ctl.scala 911:73]
+    node _T_1028 = eq(io.dec_nonblock_load_waddr, i0r.rs2) @[dec_decode_ctl.scala 911:130]
+    node i0_rs2_nonblock_load_bypass_en_d = and(_T_1027, _T_1028) @[dec_decode_ctl.scala 911:100]
+    node _T_1029 = bits(i0_rs1_depth_d, 0, 0) @[dec_decode_ctl.scala 914:41]
+    node _T_1030 = or(i0_rs1_class_d.alu, i0_rs1_class_d.mul) @[dec_decode_ctl.scala 914:66]
+    node _T_1031 = and(_T_1029, _T_1030) @[dec_decode_ctl.scala 914:45]
+    node _T_1032 = bits(i0_rs1_depth_d, 0, 0) @[dec_decode_ctl.scala 914:104]
+    node _T_1033 = and(_T_1032, i0_rs1_class_d.load) @[dec_decode_ctl.scala 914:108]
+    node _T_1034 = bits(i0_rs1_depth_d, 1, 1) @[dec_decode_ctl.scala 914:149]
+    node _T_1035 = or(i0_rs1_class_d.alu, i0_rs1_class_d.mul) @[dec_decode_ctl.scala 914:175]
+    node _T_1036 = or(_T_1035, i0_rs1_class_d.load) @[dec_decode_ctl.scala 914:196]
+    node _T_1037 = and(_T_1034, _T_1036) @[dec_decode_ctl.scala 914:153]
     node _T_1038 = cat(_T_1031, _T_1033) @[Cat.scala 29:58]
     node _T_1039 = cat(_T_1038, _T_1037) @[Cat.scala 29:58]
-    i0_rs1bypass <= _T_1039 @[dec_decode_ctl.scala 912:18]
-    node _T_1040 = bits(i0_rs2_depth_d, 0, 0) @[dec_decode_ctl.scala 914:41]
-    node _T_1041 = or(i0_rs2_class_d.alu, i0_rs2_class_d.mul) @[dec_decode_ctl.scala 914:67]
-    node _T_1042 = and(_T_1040, _T_1041) @[dec_decode_ctl.scala 914:45]
-    node _T_1043 = bits(i0_rs2_depth_d, 0, 0) @[dec_decode_ctl.scala 914:105]
-    node _T_1044 = and(_T_1043, i0_rs2_class_d.load) @[dec_decode_ctl.scala 914:109]
-    node _T_1045 = bits(i0_rs2_depth_d, 1, 1) @[dec_decode_ctl.scala 914:149]
-    node _T_1046 = or(i0_rs2_class_d.alu, i0_rs2_class_d.mul) @[dec_decode_ctl.scala 914:175]
-    node _T_1047 = or(_T_1046, i0_rs2_class_d.load) @[dec_decode_ctl.scala 914:196]
-    node _T_1048 = and(_T_1045, _T_1047) @[dec_decode_ctl.scala 914:153]
+    i0_rs1bypass <= _T_1039 @[dec_decode_ctl.scala 914:18]
+    node _T_1040 = bits(i0_rs2_depth_d, 0, 0) @[dec_decode_ctl.scala 916:41]
+    node _T_1041 = or(i0_rs2_class_d.alu, i0_rs2_class_d.mul) @[dec_decode_ctl.scala 916:67]
+    node _T_1042 = and(_T_1040, _T_1041) @[dec_decode_ctl.scala 916:45]
+    node _T_1043 = bits(i0_rs2_depth_d, 0, 0) @[dec_decode_ctl.scala 916:105]
+    node _T_1044 = and(_T_1043, i0_rs2_class_d.load) @[dec_decode_ctl.scala 916:109]
+    node _T_1045 = bits(i0_rs2_depth_d, 1, 1) @[dec_decode_ctl.scala 916:149]
+    node _T_1046 = or(i0_rs2_class_d.alu, i0_rs2_class_d.mul) @[dec_decode_ctl.scala 916:175]
+    node _T_1047 = or(_T_1046, i0_rs2_class_d.load) @[dec_decode_ctl.scala 916:196]
+    node _T_1048 = and(_T_1045, _T_1047) @[dec_decode_ctl.scala 916:153]
     node _T_1049 = cat(_T_1042, _T_1044) @[Cat.scala 29:58]
     node _T_1050 = cat(_T_1049, _T_1048) @[Cat.scala 29:58]
-    i0_rs2bypass <= _T_1050 @[dec_decode_ctl.scala 914:18]
-    node _T_1051 = bits(i0_rs1bypass, 0, 0) @[dec_decode_ctl.scala 916:66]
-    node _T_1052 = eq(_T_1051, UInt<1>("h00")) @[dec_decode_ctl.scala 916:53]
-    node _T_1053 = bits(i0_rs1bypass, 1, 1) @[dec_decode_ctl.scala 916:85]
-    node _T_1054 = eq(_T_1053, UInt<1>("h00")) @[dec_decode_ctl.scala 916:72]
-    node _T_1055 = and(_T_1052, _T_1054) @[dec_decode_ctl.scala 916:70]
-    node _T_1056 = bits(i0_rs1bypass, 2, 2) @[dec_decode_ctl.scala 916:104]
-    node _T_1057 = eq(_T_1056, UInt<1>("h00")) @[dec_decode_ctl.scala 916:91]
-    node _T_1058 = and(_T_1055, _T_1057) @[dec_decode_ctl.scala 916:89]
-    node _T_1059 = and(_T_1058, i0_rs1_nonblock_load_bypass_en_d) @[dec_decode_ctl.scala 916:108]
-    node _T_1060 = bits(i0_rs1bypass, 2, 2) @[dec_decode_ctl.scala 916:155]
-    node _T_1061 = bits(i0_rs1bypass, 1, 1) @[dec_decode_ctl.scala 916:171]
-    node _T_1062 = bits(i0_rs1bypass, 0, 0) @[dec_decode_ctl.scala 916:187]
+    i0_rs2bypass <= _T_1050 @[dec_decode_ctl.scala 916:18]
+    node _T_1051 = bits(i0_rs1bypass, 0, 0) @[dec_decode_ctl.scala 918:66]
+    node _T_1052 = eq(_T_1051, UInt<1>("h00")) @[dec_decode_ctl.scala 918:53]
+    node _T_1053 = bits(i0_rs1bypass, 1, 1) @[dec_decode_ctl.scala 918:85]
+    node _T_1054 = eq(_T_1053, UInt<1>("h00")) @[dec_decode_ctl.scala 918:72]
+    node _T_1055 = and(_T_1052, _T_1054) @[dec_decode_ctl.scala 918:70]
+    node _T_1056 = bits(i0_rs1bypass, 2, 2) @[dec_decode_ctl.scala 918:104]
+    node _T_1057 = eq(_T_1056, UInt<1>("h00")) @[dec_decode_ctl.scala 918:91]
+    node _T_1058 = and(_T_1055, _T_1057) @[dec_decode_ctl.scala 918:89]
+    node _T_1059 = and(_T_1058, i0_rs1_nonblock_load_bypass_en_d) @[dec_decode_ctl.scala 918:108]
+    node _T_1060 = bits(i0_rs1bypass, 2, 2) @[dec_decode_ctl.scala 918:155]
+    node _T_1061 = bits(i0_rs1bypass, 1, 1) @[dec_decode_ctl.scala 918:171]
+    node _T_1062 = bits(i0_rs1bypass, 0, 0) @[dec_decode_ctl.scala 918:187]
     node _T_1063 = cat(_T_1061, _T_1062) @[Cat.scala 29:58]
     node _T_1064 = cat(_T_1059, _T_1060) @[Cat.scala 29:58]
     node _T_1065 = cat(_T_1064, _T_1063) @[Cat.scala 29:58]
-    io.decode_exu.dec_i0_rs1_bypass_en_d <= _T_1065 @[dec_decode_ctl.scala 916:45]
-    node _T_1066 = bits(i0_rs2bypass, 0, 0) @[dec_decode_ctl.scala 917:66]
-    node _T_1067 = eq(_T_1066, UInt<1>("h00")) @[dec_decode_ctl.scala 917:53]
-    node _T_1068 = bits(i0_rs2bypass, 1, 1) @[dec_decode_ctl.scala 917:85]
-    node _T_1069 = eq(_T_1068, UInt<1>("h00")) @[dec_decode_ctl.scala 917:72]
-    node _T_1070 = and(_T_1067, _T_1069) @[dec_decode_ctl.scala 917:70]
-    node _T_1071 = bits(i0_rs2bypass, 2, 2) @[dec_decode_ctl.scala 917:104]
-    node _T_1072 = eq(_T_1071, UInt<1>("h00")) @[dec_decode_ctl.scala 917:91]
-    node _T_1073 = and(_T_1070, _T_1072) @[dec_decode_ctl.scala 917:89]
-    node _T_1074 = and(_T_1073, i0_rs2_nonblock_load_bypass_en_d) @[dec_decode_ctl.scala 917:108]
-    node _T_1075 = bits(i0_rs2bypass, 2, 2) @[dec_decode_ctl.scala 917:155]
-    node _T_1076 = bits(i0_rs2bypass, 1, 1) @[dec_decode_ctl.scala 917:171]
-    node _T_1077 = bits(i0_rs2bypass, 0, 0) @[dec_decode_ctl.scala 917:187]
+    io.decode_exu.dec_i0_rs1_bypass_en_d <= _T_1065 @[dec_decode_ctl.scala 918:45]
+    node _T_1066 = bits(i0_rs2bypass, 0, 0) @[dec_decode_ctl.scala 919:66]
+    node _T_1067 = eq(_T_1066, UInt<1>("h00")) @[dec_decode_ctl.scala 919:53]
+    node _T_1068 = bits(i0_rs2bypass, 1, 1) @[dec_decode_ctl.scala 919:85]
+    node _T_1069 = eq(_T_1068, UInt<1>("h00")) @[dec_decode_ctl.scala 919:72]
+    node _T_1070 = and(_T_1067, _T_1069) @[dec_decode_ctl.scala 919:70]
+    node _T_1071 = bits(i0_rs2bypass, 2, 2) @[dec_decode_ctl.scala 919:104]
+    node _T_1072 = eq(_T_1071, UInt<1>("h00")) @[dec_decode_ctl.scala 919:91]
+    node _T_1073 = and(_T_1070, _T_1072) @[dec_decode_ctl.scala 919:89]
+    node _T_1074 = and(_T_1073, i0_rs2_nonblock_load_bypass_en_d) @[dec_decode_ctl.scala 919:108]
+    node _T_1075 = bits(i0_rs2bypass, 2, 2) @[dec_decode_ctl.scala 919:155]
+    node _T_1076 = bits(i0_rs2bypass, 1, 1) @[dec_decode_ctl.scala 919:171]
+    node _T_1077 = bits(i0_rs2bypass, 0, 0) @[dec_decode_ctl.scala 919:187]
     node _T_1078 = cat(_T_1076, _T_1077) @[Cat.scala 29:58]
     node _T_1079 = cat(_T_1074, _T_1075) @[Cat.scala 29:58]
     node _T_1080 = cat(_T_1079, _T_1078) @[Cat.scala 29:58]
-    io.decode_exu.dec_i0_rs2_bypass_en_d <= _T_1080 @[dec_decode_ctl.scala 917:45]
-    io.decode_exu.dec_i0_result_r <= i0_result_r @[dec_decode_ctl.scala 919:41]
-    node _T_1081 = or(i0_dp_raw.load, i0_dp_raw.store) @[dec_decode_ctl.scala 921:68]
-    node _T_1082 = and(io.dec_ib0_valid_d, _T_1081) @[dec_decode_ctl.scala 921:50]
-    node _T_1083 = eq(io.dctl_dma.dma_dccm_stall_any, UInt<1>("h00")) @[dec_decode_ctl.scala 921:89]
-    node _T_1084 = and(_T_1082, _T_1083) @[dec_decode_ctl.scala 921:87]
-    node _T_1085 = eq(i0_block_raw_d, UInt<1>("h00")) @[dec_decode_ctl.scala 921:123]
-    node _T_1086 = and(_T_1084, _T_1085) @[dec_decode_ctl.scala 921:121]
-    node _T_1087 = or(_T_1086, io.decode_exu.dec_extint_stall) @[dec_decode_ctl.scala 921:140]
-    io.dec_lsu_valid_raw_d <= _T_1087 @[dec_decode_ctl.scala 921:26]
-    node _T_1088 = eq(io.decode_exu.dec_extint_stall, UInt<1>("h00")) @[dec_decode_ctl.scala 923:6]
-    node _T_1089 = and(_T_1088, i0_dp.lsu) @[dec_decode_ctl.scala 923:38]
-    node _T_1090 = and(_T_1089, i0_dp.load) @[dec_decode_ctl.scala 923:50]
-    node _T_1091 = bits(_T_1090, 0, 0) @[dec_decode_ctl.scala 923:64]
-    node _T_1092 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 923:81]
-    node _T_1093 = eq(io.decode_exu.dec_extint_stall, UInt<1>("h00")) @[dec_decode_ctl.scala 924:6]
-    node _T_1094 = and(_T_1093, i0_dp.lsu) @[dec_decode_ctl.scala 924:38]
-    node _T_1095 = and(_T_1094, i0_dp.store) @[dec_decode_ctl.scala 924:50]
-    node _T_1096 = bits(_T_1095, 0, 0) @[dec_decode_ctl.scala 924:65]
-    node _T_1097 = bits(io.dec_i0_instr_d, 31, 25) @[dec_decode_ctl.scala 924:85]
-    node _T_1098 = bits(io.dec_i0_instr_d, 11, 7) @[dec_decode_ctl.scala 924:95]
+    io.decode_exu.dec_i0_rs2_bypass_en_d <= _T_1080 @[dec_decode_ctl.scala 919:45]
+    io.decode_exu.dec_i0_result_r <= i0_result_r @[dec_decode_ctl.scala 921:41]
+    node _T_1081 = or(i0_dp_raw.load, i0_dp_raw.store) @[dec_decode_ctl.scala 923:68]
+    node _T_1082 = and(io.dec_ib0_valid_d, _T_1081) @[dec_decode_ctl.scala 923:50]
+    node _T_1083 = eq(io.dctl_dma.dma_dccm_stall_any, UInt<1>("h00")) @[dec_decode_ctl.scala 923:89]
+    node _T_1084 = and(_T_1082, _T_1083) @[dec_decode_ctl.scala 923:87]
+    node _T_1085 = eq(i0_block_raw_d, UInt<1>("h00")) @[dec_decode_ctl.scala 923:123]
+    node _T_1086 = and(_T_1084, _T_1085) @[dec_decode_ctl.scala 923:121]
+    node _T_1087 = or(_T_1086, io.decode_exu.dec_extint_stall) @[dec_decode_ctl.scala 923:140]
+    io.dec_lsu_valid_raw_d <= _T_1087 @[dec_decode_ctl.scala 923:26]
+    node _T_1088 = eq(io.decode_exu.dec_extint_stall, UInt<1>("h00")) @[dec_decode_ctl.scala 925:6]
+    node _T_1089 = and(_T_1088, i0_dp.lsu) @[dec_decode_ctl.scala 925:38]
+    node _T_1090 = and(_T_1089, i0_dp.load) @[dec_decode_ctl.scala 925:50]
+    node _T_1091 = bits(_T_1090, 0, 0) @[dec_decode_ctl.scala 925:64]
+    node _T_1092 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 925:81]
+    node _T_1093 = eq(io.decode_exu.dec_extint_stall, UInt<1>("h00")) @[dec_decode_ctl.scala 926:6]
+    node _T_1094 = and(_T_1093, i0_dp.lsu) @[dec_decode_ctl.scala 926:38]
+    node _T_1095 = and(_T_1094, i0_dp.store) @[dec_decode_ctl.scala 926:50]
+    node _T_1096 = bits(_T_1095, 0, 0) @[dec_decode_ctl.scala 926:65]
+    node _T_1097 = bits(io.dec_i0_instr_d, 31, 25) @[dec_decode_ctl.scala 926:85]
+    node _T_1098 = bits(io.dec_i0_instr_d, 11, 7) @[dec_decode_ctl.scala 926:95]
     node _T_1099 = cat(_T_1097, _T_1098) @[Cat.scala 29:58]
     node _T_1100 = mux(_T_1091, _T_1092, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_1101 = mux(_T_1096, _T_1099, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_1102 = or(_T_1100, _T_1101) @[Mux.scala 27:72]
     wire _T_1103 : UInt<12> @[Mux.scala 27:72]
     _T_1103 <= _T_1102 @[Mux.scala 27:72]
-    io.dec_lsu_offset_d <= _T_1103 @[dec_decode_ctl.scala 922:23]
+    io.dec_lsu_offset_d <= _T_1103 @[dec_decode_ctl.scala 924:23]
     
   extmodule gated_latch_11 : 
     output Q : Clock
@@ -21237,7 +21237,7 @@ circuit dec :
   module dec : 
     input clock : Clock
     input reset : AsyncReset
-    output io : {flip free_clk : Clock, flip active_clk : Clock, flip free_l2clk : Clock, flip lsu_fastint_stall_any : UInt<1>, dec_pause_state_cg : UInt<1>, dec_tlu_core_empty : UInt<1>, flip rst_vec : UInt<31>, flip ifu_i0_fa_index : UInt<9>, dec_fa_error_index : UInt<9>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip lsu_nonblock_load_data : UInt<32>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, flip lsu_pmu_misaligned_m : UInt<1>, flip lsu_fir_addr : UInt<31>, flip lsu_fir_error : UInt<2>, flip lsu_trigger_match_m : UInt<4>, flip lsu_idle_any : UInt<1>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, flip lsu_single_ecc_error_incr : UInt<1>, flip exu_div_result : UInt<32>, flip exu_div_wren : UInt<1>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip iccm_dma_sb_error : UInt<1>, flip exu_flush_final : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip dbg_halt_req : UInt<1>, flip dbg_resume_req : UInt<1>, dec_tlu_dbg_halted : UInt<1>, dec_tlu_debug_mode : UInt<1>, dec_tlu_resume_ack : UInt<1>, dec_tlu_mpc_halted_only : UInt<1>, dec_dbg_rddata : UInt<32>, dec_csr_rddata_d : UInt<32>, dec_dbg_cmd_done : UInt<1>, dec_dbg_cmd_fail : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip exu_i0_br_way_r : UInt<1>, lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, dec_lsu_offset_d : UInt<12>, dec_tlu_i0_kill_writeb_r : UInt<1>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, dec_tlu_flush_lower_wb : UInt<1>, dec_lsu_valid_raw_d : UInt<1>, trace_rv_trace_pkt : {rv_i_valid_ip : UInt<1>, rv_i_insn_ip : UInt<32>, rv_i_address_ip : UInt<32>, rv_i_exception_ip : UInt<1>, rv_i_ecause_ip : UInt<5>, rv_i_interrupt_ip : UInt<1>, rv_i_tval_ip : UInt<32>}, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_picio_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>, flip scan_mode : UInt<1>, flip ifu_dec : {dec_aln : {aln_dec : {flip dec_i0_decode_d : UInt<1>, ifu_i0_cinst : UInt<16>}, aln_ib : {ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_icaf_second : UInt<1>, ifu_i0_dbecc : UInt<1>, ifu_i0_bp_index : UInt<8>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, ifu_i0_valid : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<31>, ifu_i0_pc4 : UInt<1>, i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}}, ifu_pmu_instr_aligned : UInt<1>}, dec_mem_ctrl : {flip dec_tlu_flush_err_wb : UInt<1>, flip dec_tlu_i0_commit_cmt : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip dec_tlu_fence_i_wb : UInt<1>, flip dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip dec_tlu_core_ecc_disable : UInt<1>, ifu_pmu_ic_miss : UInt<1>, ifu_pmu_ic_hit : UInt<1>, ifu_pmu_bus_error : UInt<1>, ifu_pmu_bus_busy : UInt<1>, ifu_pmu_bus_trxn : UInt<1>, ifu_ic_error_start : UInt<1>, ifu_iccm_rd_ecc_single_err : UInt<1>, ifu_ic_debug_rd_data : UInt<71>, ifu_ic_debug_rd_data_valid : UInt<1>, ifu_miss_state_idle : UInt<1>}, dec_ifc : {flip dec_tlu_flush_noredir_wb : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, ifu_pmu_fetch_stall : UInt<1>}, dec_bp : {flip dec_tlu_br0_r_pkt : {valid : UInt<1>, bits : {hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}}, flip dec_tlu_flush_leak_one_wb : UInt<1>, flip dec_tlu_bpred_disable : UInt<1>}}, flip dec_exu : {dec_alu : {flip dec_i0_alu_decode_d : UInt<1>, flip dec_csr_ren_d : UInt<1>, flip dec_i0_br_immed_d : UInt<12>, exu_i0_pc_x : UInt<31>}, dec_div : {flip div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, flip dec_div_cancel : UInt<1>}, decode_exu : {flip dec_data_en : UInt<2>, flip dec_ctl_en : UInt<2>, flip i0_ap : {clz : UInt<1>, ctz : UInt<1>, pcnt : UInt<1>, sext_b : UInt<1>, sext_h : UInt<1>, slo : UInt<1>, sro : UInt<1>, min : UInt<1>, max : UInt<1>, pack : UInt<1>, packu : UInt<1>, packh : UInt<1>, rol : UInt<1>, ror : UInt<1>, grev : UInt<1>, gorc : UInt<1>, zbb : UInt<1>, sbset : UInt<1>, sbclr : UInt<1>, sbinv : UInt<1>, sbext : UInt<1>, sh1add : UInt<1>, sh2add : UInt<1>, sh3add : UInt<1>, zba : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}}, flip i0_predict_fghr_d : UInt<8>, flip i0_predict_index_d : UInt<8>, flip i0_predict_btag_d : UInt<5>, flip dec_i0_rs1_en_d : UInt<1>, flip dec_i0_branch_d : UInt<1>, flip dec_i0_rs2_en_d : UInt<1>, flip dec_i0_immed_d : UInt<32>, flip dec_i0_result_r : UInt<32>, flip dec_qual_lsu_d : UInt<1>, flip dec_i0_select_pc_d : UInt<1>, flip dec_i0_rs1_bypass_en_d : UInt<4>, flip dec_i0_rs2_bypass_en_d : UInt<4>, flip mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, gorc : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, flip pred_correct_npc_x : UInt<31>, flip dec_extint_stall : UInt<1>, exu_i0_result_x : UInt<32>, exu_csr_rs1_x : UInt<32>}, tlu_exu : {flip dec_tlu_meihap : UInt<30>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_path_r : UInt<31>, exu_i0_br_hist_r : UInt<2>, exu_i0_br_error_r : UInt<1>, exu_i0_br_start_error_r : UInt<1>, exu_i0_br_index_r : UInt<8>, exu_i0_br_valid_r : UInt<1>, exu_i0_br_mp_r : UInt<1>, exu_i0_br_middle_r : UInt<1>, exu_pmu_i0_br_misp : UInt<1>, exu_pmu_i0_br_ataken : UInt<1>, exu_pmu_i0_pc4 : UInt<1>, exu_npc_r : UInt<31>}, ib_exu : {flip dec_i0_pc_d : UInt<31>, flip dec_debug_wdata_rs1_d : UInt<1>}, gpr_exu : {flip gpr_i0_rs1_d : UInt<32>, flip gpr_i0_rs2_d : UInt<32>}}, flip lsu_dec : {tlu_busbuff : {lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>}, dctl_busbuff : {lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>}}, flip lsu_tlu : {lsu_pmu_load_external_m : UInt<1>, lsu_pmu_store_external_m : UInt<1>}, dec_dbg : {dbg_ib : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<32>}}, dec_dma : {dctl_dma : {flip dma_dccm_stall_any : UInt<1>}, tlu_dma : {flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>}}, dec_pic : {flip pic_claimid : UInt<8>, flip pic_pl : UInt<4>, flip mhwakeup : UInt<1>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meipt : UInt<4>, flip mexintpend : UInt<1>}}
+    output io : {flip free_clk : Clock, flip active_clk : Clock, flip free_l2clk : Clock, flip lsu_fastint_stall_any : UInt<1>, dec_pause_state_cg : UInt<1>, dec_tlu_core_empty : UInt<1>, flip rst_vec : UInt<31>, flip ifu_i0_fa_index : UInt<9>, dec_fa_error_index : UInt<9>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip lsu_nonblock_load_data : UInt<32>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, flip lsu_pmu_misaligned_m : UInt<1>, flip lsu_fir_addr : UInt<31>, flip lsu_fir_error : UInt<2>, flip lsu_trigger_match_m : UInt<4>, flip lsu_idle_any : UInt<1>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, flip lsu_single_ecc_error_incr : UInt<1>, flip exu_div_result : UInt<32>, flip exu_div_wren : UInt<1>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip iccm_dma_sb_error : UInt<1>, flip exu_flush_final : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip dbg_halt_req : UInt<1>, flip dbg_resume_req : UInt<1>, dec_tlu_dbg_halted : UInt<1>, dec_tlu_debug_mode : UInt<1>, dec_tlu_resume_ack : UInt<1>, dec_tlu_mpc_halted_only : UInt<1>, dec_dbg_rddata : UInt<32>, dec_csr_rddata_d : UInt<32>, dec_dbg_cmd_done : UInt<1>, dec_dbg_cmd_fail : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip exu_i0_br_way_r : UInt<1>, lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, dec_lsu_offset_d : UInt<12>, dec_tlu_i0_kill_writeb_r : UInt<1>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, dec_tlu_flush_lower_wb : UInt<1>, dec_lsu_valid_raw_d : UInt<1>, trace_rv_trace_pkt : {rv_i_valid_ip : UInt<1>, rv_i_insn_ip : UInt<32>, rv_i_address_ip : UInt<32>, rv_i_exception_ip : UInt<1>, rv_i_ecause_ip : UInt<5>, rv_i_interrupt_ip : UInt<1>, rv_i_tval_ip : UInt<32>}, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_picio_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>, dec_i0_decode_d : UInt<1>, flip scan_mode : UInt<1>, flip ifu_dec : {dec_aln : {aln_dec : {ifu_i0_cinst : UInt<16>}, aln_ib : {ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_icaf_second : UInt<1>, ifu_i0_dbecc : UInt<1>, ifu_i0_bp_index : UInt<8>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, ifu_i0_valid : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<31>, ifu_i0_pc4 : UInt<1>, i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}}, ifu_pmu_instr_aligned : UInt<1>}, dec_mem_ctrl : {flip dec_tlu_flush_err_wb : UInt<1>, flip dec_tlu_i0_commit_cmt : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip dec_tlu_fence_i_wb : UInt<1>, flip dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip dec_tlu_core_ecc_disable : UInt<1>, ifu_pmu_ic_miss : UInt<1>, ifu_pmu_ic_hit : UInt<1>, ifu_pmu_bus_error : UInt<1>, ifu_pmu_bus_busy : UInt<1>, ifu_pmu_bus_trxn : UInt<1>, ifu_ic_error_start : UInt<1>, ifu_iccm_rd_ecc_single_err : UInt<1>, ifu_ic_debug_rd_data : UInt<71>, ifu_ic_debug_rd_data_valid : UInt<1>, ifu_miss_state_idle : UInt<1>}, dec_ifc : {flip dec_tlu_flush_noredir_wb : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, ifu_pmu_fetch_stall : UInt<1>}, dec_bp : {flip dec_tlu_br0_r_pkt : {valid : UInt<1>, bits : {hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}}, flip dec_tlu_flush_leak_one_wb : UInt<1>, flip dec_tlu_bpred_disable : UInt<1>}}, flip dec_exu : {dec_alu : {flip dec_i0_alu_decode_d : UInt<1>, flip dec_csr_ren_d : UInt<1>, flip dec_i0_br_immed_d : UInt<12>, exu_i0_pc_x : UInt<31>}, dec_div : {flip div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, flip dec_div_cancel : UInt<1>}, decode_exu : {flip dec_data_en : UInt<2>, flip dec_ctl_en : UInt<2>, flip i0_ap : {clz : UInt<1>, ctz : UInt<1>, pcnt : UInt<1>, sext_b : UInt<1>, sext_h : UInt<1>, slo : UInt<1>, sro : UInt<1>, min : UInt<1>, max : UInt<1>, pack : UInt<1>, packu : UInt<1>, packh : UInt<1>, rol : UInt<1>, ror : UInt<1>, grev : UInt<1>, gorc : UInt<1>, zbb : UInt<1>, sbset : UInt<1>, sbclr : UInt<1>, sbinv : UInt<1>, sbext : UInt<1>, sh1add : UInt<1>, sh2add : UInt<1>, sh3add : UInt<1>, zba : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}}, flip i0_predict_fghr_d : UInt<8>, flip i0_predict_index_d : UInt<8>, flip i0_predict_btag_d : UInt<5>, flip dec_i0_rs1_en_d : UInt<1>, flip dec_i0_branch_d : UInt<1>, flip dec_i0_rs2_en_d : UInt<1>, flip dec_i0_immed_d : UInt<32>, flip dec_i0_result_r : UInt<32>, flip dec_qual_lsu_d : UInt<1>, flip dec_i0_select_pc_d : UInt<1>, flip dec_i0_rs1_bypass_en_d : UInt<4>, flip dec_i0_rs2_bypass_en_d : UInt<4>, flip mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, gorc : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, flip pred_correct_npc_x : UInt<31>, flip dec_extint_stall : UInt<1>, exu_i0_result_x : UInt<32>, exu_csr_rs1_x : UInt<32>}, tlu_exu : {flip dec_tlu_meihap : UInt<30>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_path_r : UInt<31>, exu_i0_br_hist_r : UInt<2>, exu_i0_br_error_r : UInt<1>, exu_i0_br_start_error_r : UInt<1>, exu_i0_br_index_r : UInt<8>, exu_i0_br_valid_r : UInt<1>, exu_i0_br_mp_r : UInt<1>, exu_i0_br_middle_r : UInt<1>, exu_pmu_i0_br_misp : UInt<1>, exu_pmu_i0_br_ataken : UInt<1>, exu_pmu_i0_pc4 : UInt<1>, exu_npc_r : UInt<31>}, ib_exu : {flip dec_i0_pc_d : UInt<31>, flip dec_debug_wdata_rs1_d : UInt<1>}, gpr_exu : {flip gpr_i0_rs1_d : UInt<32>, flip gpr_i0_rs2_d : UInt<32>}}, flip lsu_dec : {tlu_busbuff : {lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>}, dctl_busbuff : {lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>}}, flip lsu_tlu : {lsu_pmu_load_external_m : UInt<1>, lsu_pmu_store_external_m : UInt<1>}, dec_dbg : {dbg_ib : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<32>}}, dec_dma : {dctl_dma : {flip dma_dccm_stall_any : UInt<1>}, tlu_dma : {flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>}}, dec_pic : {flip pic_claimid : UInt<8>, flip pic_pl : UInt<4>, flip mhwakeup : UInt<1>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meipt : UInt<4>, flip mexintpend : UInt<1>}}
     
     wire dec_i0_inst_wb1 : UInt<32>
     dec_i0_inst_wb1 <= UInt<1>("h00")
@@ -21255,479 +21255,479 @@ circuit dec :
     dec_tlu_i0_exc_valid_wb1 <= UInt<1>("h00")
     wire dec_tlu_trace_disable : UInt<1>
     dec_tlu_trace_disable <= UInt<1>("h00")
-    inst instbuff of dec_ib_ctl @[dec.scala 128:24]
+    inst instbuff of dec_ib_ctl @[dec.scala 130:24]
     instbuff.clock <= clock
     instbuff.reset <= reset
-    inst decode of dec_decode_ctl @[dec.scala 129:22]
+    inst decode of dec_decode_ctl @[dec.scala 131:22]
     decode.clock <= clock
     decode.reset <= reset
-    inst gpr of dec_gpr_ctl @[dec.scala 130:19]
+    inst gpr of dec_gpr_ctl @[dec.scala 132:19]
     gpr.clock <= clock
     gpr.reset <= reset
-    inst tlu of dec_tlu_ctl @[dec.scala 131:19]
+    inst tlu of dec_tlu_ctl @[dec.scala 133:19]
     tlu.clock <= clock
     tlu.reset <= reset
-    inst dec_trigger of dec_trigger @[dec.scala 132:27]
+    inst dec_trigger of dec_trigger @[dec.scala 134:27]
     dec_trigger.clock <= clock
     dec_trigger.reset <= reset
-    instbuff.io.ifu_ib.i0_brp.bits.ret <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.ret @[dec.scala 136:22]
-    instbuff.io.ifu_ib.i0_brp.bits.way <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.way @[dec.scala 136:22]
-    instbuff.io.ifu_ib.i0_brp.bits.prett <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.prett @[dec.scala 136:22]
-    instbuff.io.ifu_ib.i0_brp.bits.bank <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.bank @[dec.scala 136:22]
-    instbuff.io.ifu_ib.i0_brp.bits.br_start_error <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_start_error @[dec.scala 136:22]
-    instbuff.io.ifu_ib.i0_brp.bits.br_error <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_error @[dec.scala 136:22]
-    instbuff.io.ifu_ib.i0_brp.bits.hist <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.hist @[dec.scala 136:22]
-    instbuff.io.ifu_ib.i0_brp.bits.toffset <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.toffset @[dec.scala 136:22]
-    instbuff.io.ifu_ib.i0_brp.valid <= io.ifu_dec.dec_aln.aln_ib.i0_brp.valid @[dec.scala 136:22]
-    instbuff.io.ifu_ib.ifu_i0_pc4 <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc4 @[dec.scala 136:22]
-    instbuff.io.ifu_ib.ifu_i0_pc <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc @[dec.scala 136:22]
-    instbuff.io.ifu_ib.ifu_i0_instr <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_instr @[dec.scala 136:22]
-    instbuff.io.ifu_ib.ifu_i0_valid <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_valid @[dec.scala 136:22]
-    instbuff.io.ifu_ib.ifu_i0_bp_btag <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_btag @[dec.scala 136:22]
-    instbuff.io.ifu_ib.ifu_i0_bp_fghr <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_fghr @[dec.scala 136:22]
-    instbuff.io.ifu_ib.ifu_i0_bp_index <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_index @[dec.scala 136:22]
-    instbuff.io.ifu_ib.ifu_i0_dbecc <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_dbecc @[dec.scala 136:22]
-    instbuff.io.ifu_ib.ifu_i0_icaf_second <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_second @[dec.scala 136:22]
-    instbuff.io.ifu_ib.ifu_i0_icaf_type <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_type @[dec.scala 136:22]
-    instbuff.io.ifu_ib.ifu_i0_icaf <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf @[dec.scala 136:22]
-    io.dec_exu.ib_exu.dec_debug_wdata_rs1_d <= instbuff.io.ib_exu.dec_debug_wdata_rs1_d @[dec.scala 137:22]
-    io.dec_exu.ib_exu.dec_i0_pc_d <= instbuff.io.ib_exu.dec_i0_pc_d @[dec.scala 137:22]
-    instbuff.io.dbg_ib.dbg_cmd_addr <= io.dec_dbg.dbg_ib.dbg_cmd_addr @[dec.scala 138:22]
-    instbuff.io.dbg_ib.dbg_cmd_type <= io.dec_dbg.dbg_ib.dbg_cmd_type @[dec.scala 138:22]
-    instbuff.io.dbg_ib.dbg_cmd_write <= io.dec_dbg.dbg_ib.dbg_cmd_write @[dec.scala 138:22]
-    instbuff.io.dbg_ib.dbg_cmd_valid <= io.dec_dbg.dbg_ib.dbg_cmd_valid @[dec.scala 138:22]
-    instbuff.io.ifu_i0_fa_index <= io.ifu_i0_fa_index @[dec.scala 139:31]
-    dec_trigger.io.dec_i0_pc_d <= instbuff.io.ib_exu.dec_i0_pc_d @[dec.scala 140:30]
-    dec_trigger.io.trigger_pkt_any[0].tdata2 <= tlu.io.trigger_pkt_any[0].tdata2 @[dec.scala 141:34]
-    dec_trigger.io.trigger_pkt_any[0].m <= tlu.io.trigger_pkt_any[0].m @[dec.scala 141:34]
-    dec_trigger.io.trigger_pkt_any[0].execute <= tlu.io.trigger_pkt_any[0].execute @[dec.scala 141:34]
-    dec_trigger.io.trigger_pkt_any[0].load <= tlu.io.trigger_pkt_any[0].load @[dec.scala 141:34]
-    dec_trigger.io.trigger_pkt_any[0].store <= tlu.io.trigger_pkt_any[0].store @[dec.scala 141:34]
-    dec_trigger.io.trigger_pkt_any[0].match_pkt <= tlu.io.trigger_pkt_any[0].match_pkt @[dec.scala 141:34]
-    dec_trigger.io.trigger_pkt_any[0].select <= tlu.io.trigger_pkt_any[0].select @[dec.scala 141:34]
-    dec_trigger.io.trigger_pkt_any[1].tdata2 <= tlu.io.trigger_pkt_any[1].tdata2 @[dec.scala 141:34]
-    dec_trigger.io.trigger_pkt_any[1].m <= tlu.io.trigger_pkt_any[1].m @[dec.scala 141:34]
-    dec_trigger.io.trigger_pkt_any[1].execute <= tlu.io.trigger_pkt_any[1].execute @[dec.scala 141:34]
-    dec_trigger.io.trigger_pkt_any[1].load <= tlu.io.trigger_pkt_any[1].load @[dec.scala 141:34]
-    dec_trigger.io.trigger_pkt_any[1].store <= tlu.io.trigger_pkt_any[1].store @[dec.scala 141:34]
-    dec_trigger.io.trigger_pkt_any[1].match_pkt <= tlu.io.trigger_pkt_any[1].match_pkt @[dec.scala 141:34]
-    dec_trigger.io.trigger_pkt_any[1].select <= tlu.io.trigger_pkt_any[1].select @[dec.scala 141:34]
-    dec_trigger.io.trigger_pkt_any[2].tdata2 <= tlu.io.trigger_pkt_any[2].tdata2 @[dec.scala 141:34]
-    dec_trigger.io.trigger_pkt_any[2].m <= tlu.io.trigger_pkt_any[2].m @[dec.scala 141:34]
-    dec_trigger.io.trigger_pkt_any[2].execute <= tlu.io.trigger_pkt_any[2].execute @[dec.scala 141:34]
-    dec_trigger.io.trigger_pkt_any[2].load <= tlu.io.trigger_pkt_any[2].load @[dec.scala 141:34]
-    dec_trigger.io.trigger_pkt_any[2].store <= tlu.io.trigger_pkt_any[2].store @[dec.scala 141:34]
-    dec_trigger.io.trigger_pkt_any[2].match_pkt <= tlu.io.trigger_pkt_any[2].match_pkt @[dec.scala 141:34]
-    dec_trigger.io.trigger_pkt_any[2].select <= tlu.io.trigger_pkt_any[2].select @[dec.scala 141:34]
-    dec_trigger.io.trigger_pkt_any[3].tdata2 <= tlu.io.trigger_pkt_any[3].tdata2 @[dec.scala 141:34]
-    dec_trigger.io.trigger_pkt_any[3].m <= tlu.io.trigger_pkt_any[3].m @[dec.scala 141:34]
-    dec_trigger.io.trigger_pkt_any[3].execute <= tlu.io.trigger_pkt_any[3].execute @[dec.scala 141:34]
-    dec_trigger.io.trigger_pkt_any[3].load <= tlu.io.trigger_pkt_any[3].load @[dec.scala 141:34]
-    dec_trigger.io.trigger_pkt_any[3].store <= tlu.io.trigger_pkt_any[3].store @[dec.scala 141:34]
-    dec_trigger.io.trigger_pkt_any[3].match_pkt <= tlu.io.trigger_pkt_any[3].match_pkt @[dec.scala 141:34]
-    dec_trigger.io.trigger_pkt_any[3].select <= tlu.io.trigger_pkt_any[3].select @[dec.scala 141:34]
-    decode.io.dec_aln.ifu_i0_cinst <= io.ifu_dec.dec_aln.aln_dec.ifu_i0_cinst @[dec.scala 145:21]
-    io.ifu_dec.dec_aln.aln_dec.dec_i0_decode_d <= decode.io.dec_aln.dec_i0_decode_d @[dec.scala 145:21]
-    decode.io.decode_exu.exu_csr_rs1_x <= io.dec_exu.decode_exu.exu_csr_rs1_x @[dec.scala 147:23]
-    decode.io.decode_exu.exu_i0_result_x <= io.dec_exu.decode_exu.exu_i0_result_x @[dec.scala 147:23]
-    io.dec_exu.decode_exu.dec_extint_stall <= decode.io.decode_exu.dec_extint_stall @[dec.scala 147:23]
-    io.dec_exu.decode_exu.pred_correct_npc_x <= decode.io.decode_exu.pred_correct_npc_x @[dec.scala 147:23]
-    io.dec_exu.decode_exu.mul_p.bits.bfp <= decode.io.decode_exu.mul_p.bits.bfp @[dec.scala 147:23]
-    io.dec_exu.decode_exu.mul_p.bits.crc32c_w <= decode.io.decode_exu.mul_p.bits.crc32c_w @[dec.scala 147:23]
-    io.dec_exu.decode_exu.mul_p.bits.crc32c_h <= decode.io.decode_exu.mul_p.bits.crc32c_h @[dec.scala 147:23]
-    io.dec_exu.decode_exu.mul_p.bits.crc32c_b <= decode.io.decode_exu.mul_p.bits.crc32c_b @[dec.scala 147:23]
-    io.dec_exu.decode_exu.mul_p.bits.crc32_w <= decode.io.decode_exu.mul_p.bits.crc32_w @[dec.scala 147:23]
-    io.dec_exu.decode_exu.mul_p.bits.crc32_h <= decode.io.decode_exu.mul_p.bits.crc32_h @[dec.scala 147:23]
-    io.dec_exu.decode_exu.mul_p.bits.crc32_b <= decode.io.decode_exu.mul_p.bits.crc32_b @[dec.scala 147:23]
-    io.dec_exu.decode_exu.mul_p.bits.unshfl <= decode.io.decode_exu.mul_p.bits.unshfl @[dec.scala 147:23]
-    io.dec_exu.decode_exu.mul_p.bits.shfl <= decode.io.decode_exu.mul_p.bits.shfl @[dec.scala 147:23]
-    io.dec_exu.decode_exu.mul_p.bits.gorc <= decode.io.decode_exu.mul_p.bits.gorc @[dec.scala 147:23]
-    io.dec_exu.decode_exu.mul_p.bits.grev <= decode.io.decode_exu.mul_p.bits.grev @[dec.scala 147:23]
-    io.dec_exu.decode_exu.mul_p.bits.clmulr <= decode.io.decode_exu.mul_p.bits.clmulr @[dec.scala 147:23]
-    io.dec_exu.decode_exu.mul_p.bits.clmulh <= decode.io.decode_exu.mul_p.bits.clmulh @[dec.scala 147:23]
-    io.dec_exu.decode_exu.mul_p.bits.clmul <= decode.io.decode_exu.mul_p.bits.clmul @[dec.scala 147:23]
-    io.dec_exu.decode_exu.mul_p.bits.bdep <= decode.io.decode_exu.mul_p.bits.bdep @[dec.scala 147:23]
-    io.dec_exu.decode_exu.mul_p.bits.bext <= decode.io.decode_exu.mul_p.bits.bext @[dec.scala 147:23]
-    io.dec_exu.decode_exu.mul_p.bits.low <= decode.io.decode_exu.mul_p.bits.low @[dec.scala 147:23]
-    io.dec_exu.decode_exu.mul_p.bits.rs2_sign <= decode.io.decode_exu.mul_p.bits.rs2_sign @[dec.scala 147:23]
-    io.dec_exu.decode_exu.mul_p.bits.rs1_sign <= decode.io.decode_exu.mul_p.bits.rs1_sign @[dec.scala 147:23]
-    io.dec_exu.decode_exu.mul_p.valid <= decode.io.decode_exu.mul_p.valid @[dec.scala 147:23]
-    io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d <= decode.io.decode_exu.dec_i0_rs2_bypass_en_d @[dec.scala 147:23]
-    io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d <= decode.io.decode_exu.dec_i0_rs1_bypass_en_d @[dec.scala 147:23]
-    io.dec_exu.decode_exu.dec_i0_select_pc_d <= decode.io.decode_exu.dec_i0_select_pc_d @[dec.scala 147:23]
-    io.dec_exu.decode_exu.dec_qual_lsu_d <= decode.io.decode_exu.dec_qual_lsu_d @[dec.scala 147:23]
-    io.dec_exu.decode_exu.dec_i0_result_r <= decode.io.decode_exu.dec_i0_result_r @[dec.scala 147:23]
-    io.dec_exu.decode_exu.dec_i0_immed_d <= decode.io.decode_exu.dec_i0_immed_d @[dec.scala 147:23]
-    io.dec_exu.decode_exu.dec_i0_rs2_en_d <= decode.io.decode_exu.dec_i0_rs2_en_d @[dec.scala 147:23]
-    io.dec_exu.decode_exu.dec_i0_branch_d <= decode.io.decode_exu.dec_i0_branch_d @[dec.scala 147:23]
-    io.dec_exu.decode_exu.dec_i0_rs1_en_d <= decode.io.decode_exu.dec_i0_rs1_en_d @[dec.scala 147:23]
-    io.dec_exu.decode_exu.i0_predict_btag_d <= decode.io.decode_exu.i0_predict_btag_d @[dec.scala 147:23]
-    io.dec_exu.decode_exu.i0_predict_index_d <= decode.io.decode_exu.i0_predict_index_d @[dec.scala 147:23]
-    io.dec_exu.decode_exu.i0_predict_fghr_d <= decode.io.decode_exu.i0_predict_fghr_d @[dec.scala 147:23]
-    io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.prett <= decode.io.decode_exu.dec_i0_predict_p_d.bits.prett @[dec.scala 147:23]
-    io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pret <= decode.io.decode_exu.dec_i0_predict_p_d.bits.pret @[dec.scala 147:23]
-    io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.way <= decode.io.decode_exu.dec_i0_predict_p_d.bits.way @[dec.scala 147:23]
-    io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pja <= decode.io.decode_exu.dec_i0_predict_p_d.bits.pja @[dec.scala 147:23]
-    io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pcall <= decode.io.decode_exu.dec_i0_predict_p_d.bits.pcall @[dec.scala 147:23]
-    io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_start_error <= decode.io.decode_exu.dec_i0_predict_p_d.bits.br_start_error @[dec.scala 147:23]
-    io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_error <= decode.io.decode_exu.dec_i0_predict_p_d.bits.br_error @[dec.scala 147:23]
-    io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.toffset <= decode.io.decode_exu.dec_i0_predict_p_d.bits.toffset @[dec.scala 147:23]
-    io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.hist <= decode.io.decode_exu.dec_i0_predict_p_d.bits.hist @[dec.scala 147:23]
-    io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pc4 <= decode.io.decode_exu.dec_i0_predict_p_d.bits.pc4 @[dec.scala 147:23]
-    io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.boffset <= decode.io.decode_exu.dec_i0_predict_p_d.bits.boffset @[dec.scala 147:23]
-    io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.ataken <= decode.io.decode_exu.dec_i0_predict_p_d.bits.ataken @[dec.scala 147:23]
-    io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.misp <= decode.io.decode_exu.dec_i0_predict_p_d.bits.misp @[dec.scala 147:23]
-    io.dec_exu.decode_exu.dec_i0_predict_p_d.valid <= decode.io.decode_exu.dec_i0_predict_p_d.valid @[dec.scala 147:23]
-    io.dec_exu.decode_exu.i0_ap.csr_imm <= decode.io.decode_exu.i0_ap.csr_imm @[dec.scala 147:23]
-    io.dec_exu.decode_exu.i0_ap.csr_write <= decode.io.decode_exu.i0_ap.csr_write @[dec.scala 147:23]
-    io.dec_exu.decode_exu.i0_ap.predict_nt <= decode.io.decode_exu.i0_ap.predict_nt @[dec.scala 147:23]
-    io.dec_exu.decode_exu.i0_ap.predict_t <= decode.io.decode_exu.i0_ap.predict_t @[dec.scala 147:23]
-    io.dec_exu.decode_exu.i0_ap.jal <= decode.io.decode_exu.i0_ap.jal @[dec.scala 147:23]
-    io.dec_exu.decode_exu.i0_ap.unsign <= decode.io.decode_exu.i0_ap.unsign @[dec.scala 147:23]
-    io.dec_exu.decode_exu.i0_ap.slt <= decode.io.decode_exu.i0_ap.slt @[dec.scala 147:23]
-    io.dec_exu.decode_exu.i0_ap.sub <= decode.io.decode_exu.i0_ap.sub @[dec.scala 147:23]
-    io.dec_exu.decode_exu.i0_ap.add <= decode.io.decode_exu.i0_ap.add @[dec.scala 147:23]
-    io.dec_exu.decode_exu.i0_ap.bge <= decode.io.decode_exu.i0_ap.bge @[dec.scala 147:23]
-    io.dec_exu.decode_exu.i0_ap.blt <= decode.io.decode_exu.i0_ap.blt @[dec.scala 147:23]
-    io.dec_exu.decode_exu.i0_ap.bne <= decode.io.decode_exu.i0_ap.bne @[dec.scala 147:23]
-    io.dec_exu.decode_exu.i0_ap.beq <= decode.io.decode_exu.i0_ap.beq @[dec.scala 147:23]
-    io.dec_exu.decode_exu.i0_ap.sra <= decode.io.decode_exu.i0_ap.sra @[dec.scala 147:23]
-    io.dec_exu.decode_exu.i0_ap.srl <= decode.io.decode_exu.i0_ap.srl @[dec.scala 147:23]
-    io.dec_exu.decode_exu.i0_ap.sll <= decode.io.decode_exu.i0_ap.sll @[dec.scala 147:23]
-    io.dec_exu.decode_exu.i0_ap.lxor <= decode.io.decode_exu.i0_ap.lxor @[dec.scala 147:23]
-    io.dec_exu.decode_exu.i0_ap.lor <= decode.io.decode_exu.i0_ap.lor @[dec.scala 147:23]
-    io.dec_exu.decode_exu.i0_ap.land <= decode.io.decode_exu.i0_ap.land @[dec.scala 147:23]
-    io.dec_exu.decode_exu.i0_ap.zba <= decode.io.decode_exu.i0_ap.zba @[dec.scala 147:23]
-    io.dec_exu.decode_exu.i0_ap.sh3add <= decode.io.decode_exu.i0_ap.sh3add @[dec.scala 147:23]
-    io.dec_exu.decode_exu.i0_ap.sh2add <= decode.io.decode_exu.i0_ap.sh2add @[dec.scala 147:23]
-    io.dec_exu.decode_exu.i0_ap.sh1add <= decode.io.decode_exu.i0_ap.sh1add @[dec.scala 147:23]
-    io.dec_exu.decode_exu.i0_ap.sbext <= decode.io.decode_exu.i0_ap.sbext @[dec.scala 147:23]
-    io.dec_exu.decode_exu.i0_ap.sbinv <= decode.io.decode_exu.i0_ap.sbinv @[dec.scala 147:23]
-    io.dec_exu.decode_exu.i0_ap.sbclr <= decode.io.decode_exu.i0_ap.sbclr @[dec.scala 147:23]
-    io.dec_exu.decode_exu.i0_ap.sbset <= decode.io.decode_exu.i0_ap.sbset @[dec.scala 147:23]
-    io.dec_exu.decode_exu.i0_ap.zbb <= decode.io.decode_exu.i0_ap.zbb @[dec.scala 147:23]
-    io.dec_exu.decode_exu.i0_ap.gorc <= decode.io.decode_exu.i0_ap.gorc @[dec.scala 147:23]
-    io.dec_exu.decode_exu.i0_ap.grev <= decode.io.decode_exu.i0_ap.grev @[dec.scala 147:23]
-    io.dec_exu.decode_exu.i0_ap.ror <= decode.io.decode_exu.i0_ap.ror @[dec.scala 147:23]
-    io.dec_exu.decode_exu.i0_ap.rol <= decode.io.decode_exu.i0_ap.rol @[dec.scala 147:23]
-    io.dec_exu.decode_exu.i0_ap.packh <= decode.io.decode_exu.i0_ap.packh @[dec.scala 147:23]
-    io.dec_exu.decode_exu.i0_ap.packu <= decode.io.decode_exu.i0_ap.packu @[dec.scala 147:23]
-    io.dec_exu.decode_exu.i0_ap.pack <= decode.io.decode_exu.i0_ap.pack @[dec.scala 147:23]
-    io.dec_exu.decode_exu.i0_ap.max <= decode.io.decode_exu.i0_ap.max @[dec.scala 147:23]
-    io.dec_exu.decode_exu.i0_ap.min <= decode.io.decode_exu.i0_ap.min @[dec.scala 147:23]
-    io.dec_exu.decode_exu.i0_ap.sro <= decode.io.decode_exu.i0_ap.sro @[dec.scala 147:23]
-    io.dec_exu.decode_exu.i0_ap.slo <= decode.io.decode_exu.i0_ap.slo @[dec.scala 147:23]
-    io.dec_exu.decode_exu.i0_ap.sext_h <= decode.io.decode_exu.i0_ap.sext_h @[dec.scala 147:23]
-    io.dec_exu.decode_exu.i0_ap.sext_b <= decode.io.decode_exu.i0_ap.sext_b @[dec.scala 147:23]
-    io.dec_exu.decode_exu.i0_ap.pcnt <= decode.io.decode_exu.i0_ap.pcnt @[dec.scala 147:23]
-    io.dec_exu.decode_exu.i0_ap.ctz <= decode.io.decode_exu.i0_ap.ctz @[dec.scala 147:23]
-    io.dec_exu.decode_exu.i0_ap.clz <= decode.io.decode_exu.i0_ap.clz @[dec.scala 147:23]
-    io.dec_exu.decode_exu.dec_ctl_en <= decode.io.decode_exu.dec_ctl_en @[dec.scala 147:23]
-    io.dec_exu.decode_exu.dec_data_en <= decode.io.decode_exu.dec_data_en @[dec.scala 147:23]
-    decode.io.dec_alu.exu_i0_pc_x <= io.dec_exu.dec_alu.exu_i0_pc_x @[dec.scala 148:20]
-    io.dec_exu.dec_alu.dec_i0_br_immed_d <= decode.io.dec_alu.dec_i0_br_immed_d @[dec.scala 148:20]
-    io.dec_exu.dec_alu.dec_csr_ren_d <= decode.io.dec_alu.dec_csr_ren_d @[dec.scala 148:20]
-    io.dec_exu.dec_alu.dec_i0_alu_decode_d <= decode.io.dec_alu.dec_i0_alu_decode_d @[dec.scala 148:20]
-    io.dec_exu.dec_div.dec_div_cancel <= decode.io.dec_div.dec_div_cancel @[dec.scala 149:20]
-    io.dec_exu.dec_div.div_p.bits.rem <= decode.io.dec_div.div_p.bits.rem @[dec.scala 149:20]
-    io.dec_exu.dec_div.div_p.bits.unsign <= decode.io.dec_div.div_p.bits.unsign @[dec.scala 149:20]
-    io.dec_exu.dec_div.div_p.valid <= decode.io.dec_div.div_p.valid @[dec.scala 149:20]
-    decode.io.dctl_dma.dma_dccm_stall_any <= io.dec_dma.dctl_dma.dma_dccm_stall_any @[dec.scala 150:22]
-    decode.io.dec_tlu_trace_disable <= tlu.io.dec_tlu_trace_disable @[dec.scala 151:48]
-    decode.io.dec_debug_valid_d <= instbuff.io.dec_debug_fence_d @[dec.scala 152:48]
-    decode.io.dec_tlu_flush_extint <= tlu.io.dec_tlu_flush_extint @[dec.scala 153:48]
-    decode.io.dec_tlu_force_halt <= tlu.io.tlu_mem.dec_tlu_force_halt @[dec.scala 154:48]
-    decode.io.dctl_busbuff.lsu_nonblock_load_data_tag <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_tag @[dec.scala 155:26]
-    decode.io.dctl_busbuff.lsu_nonblock_load_data_error <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_error @[dec.scala 155:26]
-    decode.io.dctl_busbuff.lsu_nonblock_load_data_valid <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_valid @[dec.scala 155:26]
-    decode.io.dctl_busbuff.lsu_nonblock_load_inv_tag_r <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_tag_r @[dec.scala 155:26]
-    decode.io.dctl_busbuff.lsu_nonblock_load_inv_r <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_r @[dec.scala 155:26]
-    decode.io.dctl_busbuff.lsu_nonblock_load_tag_m <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_tag_m @[dec.scala 155:26]
-    decode.io.dctl_busbuff.lsu_nonblock_load_valid_m <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_valid_m @[dec.scala 155:26]
-    decode.io.dec_i0_trigger_match_d <= dec_trigger.io.dec_i0_trigger_match_d @[dec.scala 156:48]
-    decode.io.dec_tlu_wr_pause_r <= tlu.io.dec_tlu_wr_pause_r @[dec.scala 157:48]
-    decode.io.dec_tlu_pipelining_disable <= tlu.io.dec_tlu_pipelining_disable @[dec.scala 158:48]
-    decode.io.lsu_trigger_match_m <= io.lsu_trigger_match_m @[dec.scala 159:48]
-    decode.io.lsu_pmu_misaligned_m <= io.lsu_pmu_misaligned_m @[dec.scala 160:48]
-    decode.io.dec_tlu_debug_stall <= tlu.io.dec_tlu_debug_stall @[dec.scala 161:48]
-    decode.io.dec_i0_bp_fa_index <= instbuff.io.dec_i0_bp_fa_index @[dec.scala 162:48]
-    decode.io.dec_tlu_flush_leak_one_r <= tlu.io.tlu_bp.dec_tlu_flush_leak_one_wb @[dec.scala 163:48]
-    decode.io.dec_debug_fence_d <= instbuff.io.dec_debug_fence_d @[dec.scala 164:48]
-    decode.io.dbg_dctl.dbg_cmd_wrdata <= io.dec_dbg.dbg_dctl.dbg_cmd_wrdata @[dec.scala 165:22]
-    decode.io.dec_i0_icaf_d <= instbuff.io.dec_i0_icaf_d @[dec.scala 166:48]
-    decode.io.dec_i0_icaf_second_d <= instbuff.io.dec_i0_icaf_second_d @[dec.scala 167:48]
-    decode.io.dec_i0_icaf_type_d <= instbuff.io.dec_i0_icaf_type_d @[dec.scala 168:48]
-    decode.io.dec_i0_dbecc_d <= instbuff.io.dec_i0_dbecc_d @[dec.scala 169:48]
-    decode.io.dec_i0_brp.bits.ret <= instbuff.io.dec_i0_brp.bits.ret @[dec.scala 170:48]
-    decode.io.dec_i0_brp.bits.way <= instbuff.io.dec_i0_brp.bits.way @[dec.scala 170:48]
-    decode.io.dec_i0_brp.bits.prett <= instbuff.io.dec_i0_brp.bits.prett @[dec.scala 170:48]
-    decode.io.dec_i0_brp.bits.bank <= instbuff.io.dec_i0_brp.bits.bank @[dec.scala 170:48]
-    decode.io.dec_i0_brp.bits.br_start_error <= instbuff.io.dec_i0_brp.bits.br_start_error @[dec.scala 170:48]
-    decode.io.dec_i0_brp.bits.br_error <= instbuff.io.dec_i0_brp.bits.br_error @[dec.scala 170:48]
-    decode.io.dec_i0_brp.bits.hist <= instbuff.io.dec_i0_brp.bits.hist @[dec.scala 170:48]
-    decode.io.dec_i0_brp.bits.toffset <= instbuff.io.dec_i0_brp.bits.toffset @[dec.scala 170:48]
-    decode.io.dec_i0_brp.valid <= instbuff.io.dec_i0_brp.valid @[dec.scala 170:48]
-    decode.io.dec_i0_bp_index <= instbuff.io.dec_i0_bp_index @[dec.scala 171:48]
-    decode.io.dec_i0_bp_fghr <= instbuff.io.dec_i0_bp_fghr @[dec.scala 172:48]
-    decode.io.dec_i0_bp_btag <= instbuff.io.dec_i0_bp_btag @[dec.scala 173:48]
-    decode.io.lsu_idle_any <= io.lsu_idle_any @[dec.scala 174:48]
-    decode.io.lsu_load_stall_any <= io.lsu_load_stall_any @[dec.scala 175:48]
-    decode.io.lsu_store_stall_any <= io.lsu_store_stall_any @[dec.scala 176:48]
-    decode.io.exu_div_wren <= io.exu_div_wren @[dec.scala 177:48]
-    decode.io.dec_tlu_i0_kill_writeb_wb <= tlu.io.dec_tlu_i0_kill_writeb_wb @[dec.scala 178:48]
-    decode.io.dec_tlu_flush_lower_wb <= tlu.io.dec_tlu_flush_lower_wb @[dec.scala 179:48]
-    decode.io.dec_tlu_i0_kill_writeb_r <= tlu.io.dec_tlu_i0_kill_writeb_r @[dec.scala 180:48]
-    decode.io.dec_tlu_flush_lower_r <= tlu.io.tlu_exu.dec_tlu_flush_lower_r @[dec.scala 181:48]
-    decode.io.dec_tlu_flush_pause_r <= tlu.io.dec_tlu_flush_pause_r @[dec.scala 182:48]
-    decode.io.dec_tlu_presync_d <= tlu.io.dec_tlu_presync_d @[dec.scala 183:48]
-    decode.io.dec_tlu_postsync_d <= tlu.io.dec_tlu_postsync_d @[dec.scala 184:48]
-    decode.io.dec_i0_pc4_d <= instbuff.io.dec_i0_pc4_d @[dec.scala 185:48]
-    decode.io.dec_csr_rddata_d <= tlu.io.dec_csr_rddata_d @[dec.scala 186:48]
-    decode.io.dec_csr_legal_d <= tlu.io.dec_csr_legal_d @[dec.scala 187:48]
-    decode.io.lsu_result_m <= io.lsu_result_m @[dec.scala 188:48]
-    decode.io.lsu_result_corr_r <= io.lsu_result_corr_r @[dec.scala 189:48]
-    decode.io.exu_flush_final <= io.exu_flush_final @[dec.scala 190:48]
-    decode.io.dec_i0_instr_d <= instbuff.io.dec_i0_instr_d @[dec.scala 191:48]
-    decode.io.dec_ib0_valid_d <= instbuff.io.dec_ib0_valid_d @[dec.scala 192:48]
-    decode.io.free_l2clk <= io.free_l2clk @[dec.scala 193:48]
-    decode.io.active_clk <= io.active_clk @[dec.scala 194:48]
-    decode.io.clk_override <= tlu.io.dec_tlu_dec_clk_override @[dec.scala 195:48]
-    decode.io.scan_mode <= io.scan_mode @[dec.scala 196:48]
-    dec_i0_inst_wb1 <= decode.io.dec_i0_inst_wb @[dec.scala 197:48]
-    dec_i0_pc_wb1 <= decode.io.dec_i0_pc_wb @[dec.scala 198:48]
-    io.lsu_p.bits.store_data_bypass_m <= decode.io.lsu_p.bits.store_data_bypass_m @[dec.scala 199:48]
-    io.lsu_p.bits.load_ldst_bypass_d <= decode.io.lsu_p.bits.load_ldst_bypass_d @[dec.scala 199:48]
-    io.lsu_p.bits.store_data_bypass_d <= decode.io.lsu_p.bits.store_data_bypass_d @[dec.scala 199:48]
-    io.lsu_p.bits.dma <= decode.io.lsu_p.bits.dma @[dec.scala 199:48]
-    io.lsu_p.bits.unsign <= decode.io.lsu_p.bits.unsign @[dec.scala 199:48]
-    io.lsu_p.bits.store <= decode.io.lsu_p.bits.store @[dec.scala 199:48]
-    io.lsu_p.bits.load <= decode.io.lsu_p.bits.load @[dec.scala 199:48]
-    io.lsu_p.bits.dword <= decode.io.lsu_p.bits.dword @[dec.scala 199:48]
-    io.lsu_p.bits.word <= decode.io.lsu_p.bits.word @[dec.scala 199:48]
-    io.lsu_p.bits.half <= decode.io.lsu_p.bits.half @[dec.scala 199:48]
-    io.lsu_p.bits.by <= decode.io.lsu_p.bits.by @[dec.scala 199:48]
-    io.lsu_p.bits.stack <= decode.io.lsu_p.bits.stack @[dec.scala 199:48]
-    io.lsu_p.bits.fast_int <= decode.io.lsu_p.bits.fast_int @[dec.scala 199:48]
-    io.lsu_p.valid <= decode.io.lsu_p.valid @[dec.scala 199:48]
-    io.dec_lsu_valid_raw_d <= decode.io.dec_lsu_valid_raw_d @[dec.scala 200:48]
-    io.dec_lsu_offset_d <= decode.io.dec_lsu_offset_d @[dec.scala 201:48]
-    io.dec_pause_state_cg <= decode.io.dec_pause_state_cg @[dec.scala 202:48]
-    io.dec_exu.decode_exu.dec_qual_lsu_d <= decode.io.decode_exu.dec_qual_lsu_d @[dec.scala 203:48]
-    io.dec_fa_error_index <= decode.io.dec_fa_error_index @[dec.scala 204:48]
-    gpr.io.raddr0 <= decode.io.dec_i0_rs1_d @[dec.scala 206:23]
-    gpr.io.raddr1 <= decode.io.dec_i0_rs2_d @[dec.scala 207:23]
-    gpr.io.wen0 <= decode.io.dec_i0_wen_r @[dec.scala 208:23]
-    gpr.io.waddr0 <= decode.io.dec_i0_waddr_r @[dec.scala 209:23]
-    gpr.io.wd0 <= decode.io.dec_i0_wdata_r @[dec.scala 210:23]
-    gpr.io.wen1 <= decode.io.dec_nonblock_load_wen @[dec.scala 211:23]
-    gpr.io.waddr1 <= decode.io.dec_nonblock_load_waddr @[dec.scala 212:23]
-    gpr.io.wd1 <= io.lsu_nonblock_load_data @[dec.scala 213:23]
-    gpr.io.wen2 <= io.exu_div_wren @[dec.scala 214:23]
-    gpr.io.waddr2 <= decode.io.div_waddr_wb @[dec.scala 215:23]
-    gpr.io.wd2 <= io.exu_div_result @[dec.scala 216:23]
-    gpr.io.scan_mode <= io.scan_mode @[dec.scala 217:23]
-    io.dec_exu.gpr_exu.gpr_i0_rs2_d <= gpr.io.gpr_exu.gpr_i0_rs2_d @[dec.scala 218:22]
-    io.dec_exu.gpr_exu.gpr_i0_rs1_d <= gpr.io.gpr_exu.gpr_i0_rs1_d @[dec.scala 218:22]
-    tlu.io.tlu_mem.ifu_miss_state_idle <= io.ifu_dec.dec_mem_ctrl.ifu_miss_state_idle @[dec.scala 220:18]
-    tlu.io.tlu_mem.ifu_ic_debug_rd_data_valid <= io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data_valid @[dec.scala 220:18]
-    tlu.io.tlu_mem.ifu_ic_debug_rd_data <= io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data @[dec.scala 220:18]
-    tlu.io.tlu_mem.ifu_iccm_rd_ecc_single_err <= io.ifu_dec.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err @[dec.scala 220:18]
-    tlu.io.tlu_mem.ifu_ic_error_start <= io.ifu_dec.dec_mem_ctrl.ifu_ic_error_start @[dec.scala 220:18]
-    tlu.io.tlu_mem.ifu_pmu_bus_trxn <= io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_trxn @[dec.scala 220:18]
-    tlu.io.tlu_mem.ifu_pmu_bus_busy <= io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_busy @[dec.scala 220:18]
-    tlu.io.tlu_mem.ifu_pmu_bus_error <= io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_error @[dec.scala 220:18]
-    tlu.io.tlu_mem.ifu_pmu_ic_hit <= io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_hit @[dec.scala 220:18]
-    tlu.io.tlu_mem.ifu_pmu_ic_miss <= io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_miss @[dec.scala 220:18]
-    io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable <= tlu.io.tlu_mem.dec_tlu_core_ecc_disable @[dec.scala 220:18]
-    io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid <= tlu.io.tlu_mem.dec_tlu_ic_diag_pkt.icache_wr_valid @[dec.scala 220:18]
-    io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid <= tlu.io.tlu_mem.dec_tlu_ic_diag_pkt.icache_rd_valid @[dec.scala 220:18]
-    io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics <= tlu.io.tlu_mem.dec_tlu_ic_diag_pkt.icache_dicawics @[dec.scala 220:18]
-    io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata <= tlu.io.tlu_mem.dec_tlu_ic_diag_pkt.icache_wrdata @[dec.scala 220:18]
-    io.ifu_dec.dec_mem_ctrl.dec_tlu_fence_i_wb <= tlu.io.tlu_mem.dec_tlu_fence_i_wb @[dec.scala 220:18]
-    io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt <= tlu.io.tlu_mem.dec_tlu_force_halt @[dec.scala 220:18]
-    io.ifu_dec.dec_mem_ctrl.dec_tlu_i0_commit_cmt <= tlu.io.tlu_mem.dec_tlu_i0_commit_cmt @[dec.scala 220:18]
-    io.ifu_dec.dec_mem_ctrl.dec_tlu_flush_err_wb <= tlu.io.tlu_mem.dec_tlu_flush_err_wb @[dec.scala 220:18]
-    tlu.io.tlu_ifc.ifu_pmu_fetch_stall <= io.ifu_dec.dec_ifc.ifu_pmu_fetch_stall @[dec.scala 221:18]
-    io.ifu_dec.dec_ifc.dec_tlu_mrac_ff <= tlu.io.tlu_ifc.dec_tlu_mrac_ff @[dec.scala 221:18]
-    io.ifu_dec.dec_ifc.dec_tlu_flush_noredir_wb <= tlu.io.tlu_ifc.dec_tlu_flush_noredir_wb @[dec.scala 221:18]
-    io.ifu_dec.dec_bp.dec_tlu_bpred_disable <= tlu.io.tlu_bp.dec_tlu_bpred_disable @[dec.scala 222:18]
-    io.ifu_dec.dec_bp.dec_tlu_flush_leak_one_wb <= tlu.io.tlu_bp.dec_tlu_flush_leak_one_wb @[dec.scala 222:18]
-    io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.middle <= tlu.io.tlu_bp.dec_tlu_br0_r_pkt.bits.middle @[dec.scala 222:18]
-    io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.way <= tlu.io.tlu_bp.dec_tlu_br0_r_pkt.bits.way @[dec.scala 222:18]
-    io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_start_error <= tlu.io.tlu_bp.dec_tlu_br0_r_pkt.bits.br_start_error @[dec.scala 222:18]
-    io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_error <= tlu.io.tlu_bp.dec_tlu_br0_r_pkt.bits.br_error @[dec.scala 222:18]
-    io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.hist <= tlu.io.tlu_bp.dec_tlu_br0_r_pkt.bits.hist @[dec.scala 222:18]
-    io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.valid <= tlu.io.tlu_bp.dec_tlu_br0_r_pkt.valid @[dec.scala 222:18]
-    tlu.io.tlu_exu.exu_npc_r <= io.dec_exu.tlu_exu.exu_npc_r @[dec.scala 223:18]
-    tlu.io.tlu_exu.exu_pmu_i0_pc4 <= io.dec_exu.tlu_exu.exu_pmu_i0_pc4 @[dec.scala 223:18]
-    tlu.io.tlu_exu.exu_pmu_i0_br_ataken <= io.dec_exu.tlu_exu.exu_pmu_i0_br_ataken @[dec.scala 223:18]
-    tlu.io.tlu_exu.exu_pmu_i0_br_misp <= io.dec_exu.tlu_exu.exu_pmu_i0_br_misp @[dec.scala 223:18]
-    tlu.io.tlu_exu.exu_i0_br_middle_r <= io.dec_exu.tlu_exu.exu_i0_br_middle_r @[dec.scala 223:18]
-    tlu.io.tlu_exu.exu_i0_br_mp_r <= io.dec_exu.tlu_exu.exu_i0_br_mp_r @[dec.scala 223:18]
-    tlu.io.tlu_exu.exu_i0_br_valid_r <= io.dec_exu.tlu_exu.exu_i0_br_valid_r @[dec.scala 223:18]
-    tlu.io.tlu_exu.exu_i0_br_index_r <= io.dec_exu.tlu_exu.exu_i0_br_index_r @[dec.scala 223:18]
-    tlu.io.tlu_exu.exu_i0_br_start_error_r <= io.dec_exu.tlu_exu.exu_i0_br_start_error_r @[dec.scala 223:18]
-    tlu.io.tlu_exu.exu_i0_br_error_r <= io.dec_exu.tlu_exu.exu_i0_br_error_r @[dec.scala 223:18]
-    tlu.io.tlu_exu.exu_i0_br_hist_r <= io.dec_exu.tlu_exu.exu_i0_br_hist_r @[dec.scala 223:18]
-    io.dec_exu.tlu_exu.dec_tlu_flush_path_r <= tlu.io.tlu_exu.dec_tlu_flush_path_r @[dec.scala 223:18]
-    io.dec_exu.tlu_exu.dec_tlu_flush_lower_r <= tlu.io.tlu_exu.dec_tlu_flush_lower_r @[dec.scala 223:18]
-    io.dec_exu.tlu_exu.dec_tlu_meihap <= tlu.io.tlu_exu.dec_tlu_meihap @[dec.scala 223:18]
-    tlu.io.tlu_dma.dma_iccm_stall_any <= io.dec_dma.tlu_dma.dma_iccm_stall_any @[dec.scala 224:18]
-    tlu.io.tlu_dma.dma_dccm_stall_any <= io.dec_dma.tlu_dma.dma_dccm_stall_any @[dec.scala 224:18]
-    io.dec_dma.tlu_dma.dec_tlu_dma_qos_prty <= tlu.io.tlu_dma.dec_tlu_dma_qos_prty @[dec.scala 224:18]
-    tlu.io.tlu_dma.dma_pmu_any_write <= io.dec_dma.tlu_dma.dma_pmu_any_write @[dec.scala 224:18]
-    tlu.io.tlu_dma.dma_pmu_any_read <= io.dec_dma.tlu_dma.dma_pmu_any_read @[dec.scala 224:18]
-    tlu.io.tlu_dma.dma_pmu_dccm_write <= io.dec_dma.tlu_dma.dma_pmu_dccm_write @[dec.scala 224:18]
-    tlu.io.tlu_dma.dma_pmu_dccm_read <= io.dec_dma.tlu_dma.dma_pmu_dccm_read @[dec.scala 224:18]
-    tlu.io.free_l2clk <= io.free_l2clk @[dec.scala 225:45]
-    tlu.io.free_clk <= io.free_clk @[dec.scala 226:45]
-    tlu.io.scan_mode <= io.scan_mode @[dec.scala 227:45]
-    tlu.io.rst_vec <= io.rst_vec @[dec.scala 228:45]
-    tlu.io.nmi_int <= io.nmi_int @[dec.scala 229:45]
-    tlu.io.nmi_vec <= io.nmi_vec @[dec.scala 230:45]
-    tlu.io.i_cpu_halt_req <= io.i_cpu_halt_req @[dec.scala 231:45]
-    tlu.io.i_cpu_run_req <= io.i_cpu_run_req @[dec.scala 232:45]
-    tlu.io.lsu_fastint_stall_any <= io.lsu_fastint_stall_any @[dec.scala 233:45]
-    tlu.io.ifu_pmu_instr_aligned <= io.ifu_dec.dec_aln.ifu_pmu_instr_aligned @[dec.scala 234:45]
-    tlu.io.dec_pmu_instr_decoded <= decode.io.dec_pmu_instr_decoded @[dec.scala 235:45]
-    tlu.io.dec_pmu_decode_stall <= decode.io.dec_pmu_decode_stall @[dec.scala 236:45]
-    tlu.io.dec_pmu_presync_stall <= decode.io.dec_pmu_presync_stall @[dec.scala 237:45]
-    tlu.io.dec_pmu_postsync_stall <= decode.io.dec_pmu_postsync_stall @[dec.scala 238:45]
-    tlu.io.lsu_store_stall_any <= io.lsu_store_stall_any @[dec.scala 239:45]
-    tlu.io.tlu_busbuff.lsu_imprecise_error_addr_any <= io.lsu_dec.tlu_busbuff.lsu_imprecise_error_addr_any @[dec.scala 240:26]
-    tlu.io.tlu_busbuff.lsu_imprecise_error_store_any <= io.lsu_dec.tlu_busbuff.lsu_imprecise_error_store_any @[dec.scala 240:26]
-    tlu.io.tlu_busbuff.lsu_imprecise_error_load_any <= io.lsu_dec.tlu_busbuff.lsu_imprecise_error_load_any @[dec.scala 240:26]
-    io.lsu_dec.tlu_busbuff.dec_tlu_sideeffect_posted_disable <= tlu.io.tlu_busbuff.dec_tlu_sideeffect_posted_disable @[dec.scala 240:26]
-    io.lsu_dec.tlu_busbuff.dec_tlu_wb_coalescing_disable <= tlu.io.tlu_busbuff.dec_tlu_wb_coalescing_disable @[dec.scala 240:26]
-    io.lsu_dec.tlu_busbuff.dec_tlu_external_ldfwd_disable <= tlu.io.tlu_busbuff.dec_tlu_external_ldfwd_disable @[dec.scala 240:26]
-    tlu.io.tlu_busbuff.lsu_pmu_bus_busy <= io.lsu_dec.tlu_busbuff.lsu_pmu_bus_busy @[dec.scala 240:26]
-    tlu.io.tlu_busbuff.lsu_pmu_bus_error <= io.lsu_dec.tlu_busbuff.lsu_pmu_bus_error @[dec.scala 240:26]
-    tlu.io.tlu_busbuff.lsu_pmu_bus_misaligned <= io.lsu_dec.tlu_busbuff.lsu_pmu_bus_misaligned @[dec.scala 240:26]
-    tlu.io.tlu_busbuff.lsu_pmu_bus_trxn <= io.lsu_dec.tlu_busbuff.lsu_pmu_bus_trxn @[dec.scala 240:26]
-    tlu.io.lsu_tlu.lsu_pmu_store_external_m <= io.lsu_tlu.lsu_pmu_store_external_m @[dec.scala 241:14]
-    tlu.io.lsu_tlu.lsu_pmu_load_external_m <= io.lsu_tlu.lsu_pmu_load_external_m @[dec.scala 241:14]
-    tlu.io.dec_pic.mexintpend <= io.dec_pic.mexintpend @[dec.scala 242:14]
-    io.dec_pic.dec_tlu_meipt <= tlu.io.dec_pic.dec_tlu_meipt @[dec.scala 242:14]
-    io.dec_pic.dec_tlu_meicurpl <= tlu.io.dec_pic.dec_tlu_meicurpl @[dec.scala 242:14]
-    tlu.io.dec_pic.mhwakeup <= io.dec_pic.mhwakeup @[dec.scala 242:14]
-    tlu.io.dec_pic.pic_pl <= io.dec_pic.pic_pl @[dec.scala 242:14]
-    tlu.io.dec_pic.pic_claimid <= io.dec_pic.pic_claimid @[dec.scala 242:14]
-    tlu.io.lsu_fir_addr <= io.lsu_fir_addr @[dec.scala 243:45]
-    tlu.io.lsu_fir_error <= io.lsu_fir_error @[dec.scala 244:45]
-    tlu.io.iccm_dma_sb_error <= io.iccm_dma_sb_error @[dec.scala 245:45]
-    tlu.io.lsu_error_pkt_r.bits.addr <= io.lsu_error_pkt_r.bits.addr @[dec.scala 246:45]
-    tlu.io.lsu_error_pkt_r.bits.mscause <= io.lsu_error_pkt_r.bits.mscause @[dec.scala 246:45]
-    tlu.io.lsu_error_pkt_r.bits.exc_type <= io.lsu_error_pkt_r.bits.exc_type @[dec.scala 246:45]
-    tlu.io.lsu_error_pkt_r.bits.inst_type <= io.lsu_error_pkt_r.bits.inst_type @[dec.scala 246:45]
-    tlu.io.lsu_error_pkt_r.bits.single_ecc_error <= io.lsu_error_pkt_r.bits.single_ecc_error @[dec.scala 246:45]
-    tlu.io.lsu_error_pkt_r.valid <= io.lsu_error_pkt_r.valid @[dec.scala 246:45]
-    tlu.io.lsu_single_ecc_error_incr <= io.lsu_single_ecc_error_incr @[dec.scala 247:45]
-    tlu.io.dec_pause_state <= decode.io.dec_pause_state @[dec.scala 248:45]
-    tlu.io.dec_csr_wen_unq_d <= decode.io.dec_csr_wen_unq_d @[dec.scala 249:45]
-    tlu.io.dec_csr_any_unq_d <= decode.io.dec_csr_any_unq_d @[dec.scala 250:45]
-    tlu.io.dec_csr_rdaddr_d <= decode.io.dec_csr_rdaddr_d @[dec.scala 251:45]
-    tlu.io.dec_csr_wen_r <= decode.io.dec_csr_wen_r @[dec.scala 252:45]
-    tlu.io.dec_csr_wraddr_r <= decode.io.dec_csr_wraddr_r @[dec.scala 253:45]
-    tlu.io.dec_csr_wrdata_r <= decode.io.dec_csr_wrdata_r @[dec.scala 254:45]
-    tlu.io.dec_csr_stall_int_ff <= decode.io.dec_csr_stall_int_ff @[dec.scala 255:45]
-    tlu.io.dec_tlu_i0_valid_r <= decode.io.dec_tlu_i0_valid_r @[dec.scala 256:45]
-    tlu.io.dec_tlu_i0_pc_r <= decode.io.dec_tlu_i0_pc_r @[dec.scala 257:45]
-    tlu.io.dec_tlu_packet_r.pmu_lsu_misaligned <= decode.io.dec_tlu_packet_r.pmu_lsu_misaligned @[dec.scala 258:45]
-    tlu.io.dec_tlu_packet_r.pmu_divide <= decode.io.dec_tlu_packet_r.pmu_divide @[dec.scala 258:45]
-    tlu.io.dec_tlu_packet_r.pmu_i0_br_unpred <= decode.io.dec_tlu_packet_r.pmu_i0_br_unpred @[dec.scala 258:45]
-    tlu.io.dec_tlu_packet_r.pmu_i0_itype <= decode.io.dec_tlu_packet_r.pmu_i0_itype @[dec.scala 258:45]
-    tlu.io.dec_tlu_packet_r.i0trigger <= decode.io.dec_tlu_packet_r.i0trigger @[dec.scala 258:45]
-    tlu.io.dec_tlu_packet_r.fence_i <= decode.io.dec_tlu_packet_r.fence_i @[dec.scala 258:45]
-    tlu.io.dec_tlu_packet_r.icaf_type <= decode.io.dec_tlu_packet_r.icaf_type @[dec.scala 258:45]
-    tlu.io.dec_tlu_packet_r.icaf_second <= decode.io.dec_tlu_packet_r.icaf_second @[dec.scala 258:45]
-    tlu.io.dec_tlu_packet_r.icaf <= decode.io.dec_tlu_packet_r.icaf @[dec.scala 258:45]
-    tlu.io.dec_tlu_packet_r.legal <= decode.io.dec_tlu_packet_r.legal @[dec.scala 258:45]
-    tlu.io.dec_illegal_inst <= decode.io.dec_illegal_inst @[dec.scala 259:45]
-    tlu.io.dec_i0_decode_d <= decode.io.dec_aln.dec_i0_decode_d @[dec.scala 260:45]
-    tlu.io.exu_i0_br_way_r <= io.exu_i0_br_way_r @[dec.scala 261:45]
-    tlu.io.dbg_halt_req <= io.dbg_halt_req @[dec.scala 262:45]
-    tlu.io.dbg_resume_req <= io.dbg_resume_req @[dec.scala 263:45]
-    tlu.io.lsu_idle_any <= io.lsu_idle_any @[dec.scala 264:45]
-    tlu.io.dec_div_active <= decode.io.dec_div_active @[dec.scala 265:45]
-    tlu.io.timer_int <= io.timer_int @[dec.scala 266:45]
-    tlu.io.soft_int <= io.soft_int @[dec.scala 267:45]
-    tlu.io.core_id <= io.core_id @[dec.scala 268:45]
-    tlu.io.mpc_debug_halt_req <= io.mpc_debug_halt_req @[dec.scala 269:45]
-    tlu.io.mpc_debug_run_req <= io.mpc_debug_run_req @[dec.scala 270:45]
-    tlu.io.mpc_reset_run_req <= io.mpc_reset_run_req @[dec.scala 271:45]
-    io.dec_dbg_cmd_done <= tlu.io.dec_dbg_cmd_done @[dec.scala 272:28]
-    io.dec_dbg_cmd_fail <= tlu.io.dec_dbg_cmd_fail @[dec.scala 273:28]
-    io.dec_tlu_dbg_halted <= tlu.io.dec_tlu_dbg_halted @[dec.scala 274:28]
-    io.dec_tlu_debug_mode <= tlu.io.dec_tlu_debug_mode @[dec.scala 275:28]
-    io.dec_tlu_resume_ack <= tlu.io.dec_tlu_resume_ack @[dec.scala 276:28]
-    io.dec_tlu_mpc_halted_only <= tlu.io.dec_tlu_mpc_halted_only @[dec.scala 277:51]
-    io.trigger_pkt_any[0].tdata2 <= tlu.io.trigger_pkt_any[0].tdata2 @[dec.scala 278:29]
-    io.trigger_pkt_any[0].m <= tlu.io.trigger_pkt_any[0].m @[dec.scala 278:29]
-    io.trigger_pkt_any[0].execute <= tlu.io.trigger_pkt_any[0].execute @[dec.scala 278:29]
-    io.trigger_pkt_any[0].load <= tlu.io.trigger_pkt_any[0].load @[dec.scala 278:29]
-    io.trigger_pkt_any[0].store <= tlu.io.trigger_pkt_any[0].store @[dec.scala 278:29]
-    io.trigger_pkt_any[0].match_pkt <= tlu.io.trigger_pkt_any[0].match_pkt @[dec.scala 278:29]
-    io.trigger_pkt_any[0].select <= tlu.io.trigger_pkt_any[0].select @[dec.scala 278:29]
-    io.trigger_pkt_any[1].tdata2 <= tlu.io.trigger_pkt_any[1].tdata2 @[dec.scala 278:29]
-    io.trigger_pkt_any[1].m <= tlu.io.trigger_pkt_any[1].m @[dec.scala 278:29]
-    io.trigger_pkt_any[1].execute <= tlu.io.trigger_pkt_any[1].execute @[dec.scala 278:29]
-    io.trigger_pkt_any[1].load <= tlu.io.trigger_pkt_any[1].load @[dec.scala 278:29]
-    io.trigger_pkt_any[1].store <= tlu.io.trigger_pkt_any[1].store @[dec.scala 278:29]
-    io.trigger_pkt_any[1].match_pkt <= tlu.io.trigger_pkt_any[1].match_pkt @[dec.scala 278:29]
-    io.trigger_pkt_any[1].select <= tlu.io.trigger_pkt_any[1].select @[dec.scala 278:29]
-    io.trigger_pkt_any[2].tdata2 <= tlu.io.trigger_pkt_any[2].tdata2 @[dec.scala 278:29]
-    io.trigger_pkt_any[2].m <= tlu.io.trigger_pkt_any[2].m @[dec.scala 278:29]
-    io.trigger_pkt_any[2].execute <= tlu.io.trigger_pkt_any[2].execute @[dec.scala 278:29]
-    io.trigger_pkt_any[2].load <= tlu.io.trigger_pkt_any[2].load @[dec.scala 278:29]
-    io.trigger_pkt_any[2].store <= tlu.io.trigger_pkt_any[2].store @[dec.scala 278:29]
-    io.trigger_pkt_any[2].match_pkt <= tlu.io.trigger_pkt_any[2].match_pkt @[dec.scala 278:29]
-    io.trigger_pkt_any[2].select <= tlu.io.trigger_pkt_any[2].select @[dec.scala 278:29]
-    io.trigger_pkt_any[3].tdata2 <= tlu.io.trigger_pkt_any[3].tdata2 @[dec.scala 278:29]
-    io.trigger_pkt_any[3].m <= tlu.io.trigger_pkt_any[3].m @[dec.scala 278:29]
-    io.trigger_pkt_any[3].execute <= tlu.io.trigger_pkt_any[3].execute @[dec.scala 278:29]
-    io.trigger_pkt_any[3].load <= tlu.io.trigger_pkt_any[3].load @[dec.scala 278:29]
-    io.trigger_pkt_any[3].store <= tlu.io.trigger_pkt_any[3].store @[dec.scala 278:29]
-    io.trigger_pkt_any[3].match_pkt <= tlu.io.trigger_pkt_any[3].match_pkt @[dec.scala 278:29]
-    io.trigger_pkt_any[3].select <= tlu.io.trigger_pkt_any[3].select @[dec.scala 278:29]
-    io.o_cpu_halt_status <= tlu.io.o_cpu_halt_status @[dec.scala 279:29]
-    io.o_cpu_halt_ack <= tlu.io.o_cpu_halt_ack @[dec.scala 280:29]
-    io.o_cpu_run_ack <= tlu.io.o_cpu_run_ack @[dec.scala 281:29]
-    io.o_debug_mode_status <= tlu.io.o_debug_mode_status @[dec.scala 282:29]
-    io.mpc_debug_halt_ack <= tlu.io.mpc_debug_halt_ack @[dec.scala 283:29]
-    io.mpc_debug_run_ack <= tlu.io.mpc_debug_run_ack @[dec.scala 284:29]
-    io.debug_brkpt_status <= tlu.io.debug_brkpt_status @[dec.scala 285:29]
-    io.dec_tlu_i0_kill_writeb_r <= tlu.io.dec_tlu_i0_kill_writeb_r @[dec.scala 286:34]
-    io.dec_tlu_perfcnt0 <= tlu.io.dec_tlu_perfcnt0 @[dec.scala 287:29]
-    io.dec_tlu_perfcnt1 <= tlu.io.dec_tlu_perfcnt1 @[dec.scala 288:29]
-    io.dec_tlu_perfcnt2 <= tlu.io.dec_tlu_perfcnt2 @[dec.scala 289:29]
-    io.dec_tlu_perfcnt3 <= tlu.io.dec_tlu_perfcnt3 @[dec.scala 290:29]
-    dec_tlu_i0_exc_valid_wb1 <= tlu.io.dec_tlu_i0_exc_valid_wb1 @[dec.scala 291:32]
-    dec_tlu_i0_valid_wb1 <= tlu.io.dec_tlu_i0_valid_wb1 @[dec.scala 292:32]
-    dec_tlu_int_valid_wb1 <= tlu.io.dec_tlu_int_valid_wb1 @[dec.scala 293:32]
-    dec_tlu_exc_cause_wb1 <= tlu.io.dec_tlu_exc_cause_wb1 @[dec.scala 294:32]
-    dec_tlu_mtval_wb1 <= tlu.io.dec_tlu_mtval_wb1 @[dec.scala 295:32]
-    io.dec_tlu_misc_clk_override <= tlu.io.dec_tlu_misc_clk_override @[dec.scala 296:35]
-    io.dec_tlu_ifu_clk_override <= tlu.io.dec_tlu_ifu_clk_override @[dec.scala 297:36]
-    io.dec_tlu_lsu_clk_override <= tlu.io.dec_tlu_lsu_clk_override @[dec.scala 298:36]
-    io.dec_tlu_bus_clk_override <= tlu.io.dec_tlu_bus_clk_override @[dec.scala 299:36]
-    io.dec_tlu_pic_clk_override <= tlu.io.dec_tlu_pic_clk_override @[dec.scala 300:36]
-    io.dec_tlu_dccm_clk_override <= tlu.io.dec_tlu_dccm_clk_override @[dec.scala 301:36]
-    io.dec_tlu_icm_clk_override <= tlu.io.dec_tlu_icm_clk_override @[dec.scala 302:36]
-    io.dec_tlu_picio_clk_override <= tlu.io.dec_tlu_icm_clk_override @[dec.scala 303:36]
-    io.dec_tlu_core_empty <= tlu.io.dec_tlu_core_empty @[dec.scala 304:36]
-    io.dec_csr_rddata_d <= tlu.io.dec_csr_rddata_d @[dec.scala 305:36]
-    io.dec_tlu_flush_lower_wb <= tlu.io.dec_tlu_flush_lower_wb @[dec.scala 306:36]
-    io.trace_rv_trace_pkt.rv_i_insn_ip <= decode.io.dec_i0_inst_wb @[dec.scala 310:38]
+    instbuff.io.ifu_ib.i0_brp.bits.ret <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.ret @[dec.scala 138:22]
+    instbuff.io.ifu_ib.i0_brp.bits.way <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.way @[dec.scala 138:22]
+    instbuff.io.ifu_ib.i0_brp.bits.prett <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.prett @[dec.scala 138:22]
+    instbuff.io.ifu_ib.i0_brp.bits.bank <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.bank @[dec.scala 138:22]
+    instbuff.io.ifu_ib.i0_brp.bits.br_start_error <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_start_error @[dec.scala 138:22]
+    instbuff.io.ifu_ib.i0_brp.bits.br_error <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_error @[dec.scala 138:22]
+    instbuff.io.ifu_ib.i0_brp.bits.hist <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.hist @[dec.scala 138:22]
+    instbuff.io.ifu_ib.i0_brp.bits.toffset <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.toffset @[dec.scala 138:22]
+    instbuff.io.ifu_ib.i0_brp.valid <= io.ifu_dec.dec_aln.aln_ib.i0_brp.valid @[dec.scala 138:22]
+    instbuff.io.ifu_ib.ifu_i0_pc4 <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc4 @[dec.scala 138:22]
+    instbuff.io.ifu_ib.ifu_i0_pc <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc @[dec.scala 138:22]
+    instbuff.io.ifu_ib.ifu_i0_instr <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_instr @[dec.scala 138:22]
+    instbuff.io.ifu_ib.ifu_i0_valid <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_valid @[dec.scala 138:22]
+    instbuff.io.ifu_ib.ifu_i0_bp_btag <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_btag @[dec.scala 138:22]
+    instbuff.io.ifu_ib.ifu_i0_bp_fghr <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_fghr @[dec.scala 138:22]
+    instbuff.io.ifu_ib.ifu_i0_bp_index <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_index @[dec.scala 138:22]
+    instbuff.io.ifu_ib.ifu_i0_dbecc <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_dbecc @[dec.scala 138:22]
+    instbuff.io.ifu_ib.ifu_i0_icaf_second <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_second @[dec.scala 138:22]
+    instbuff.io.ifu_ib.ifu_i0_icaf_type <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_type @[dec.scala 138:22]
+    instbuff.io.ifu_ib.ifu_i0_icaf <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf @[dec.scala 138:22]
+    io.dec_exu.ib_exu.dec_debug_wdata_rs1_d <= instbuff.io.ib_exu.dec_debug_wdata_rs1_d @[dec.scala 139:22]
+    io.dec_exu.ib_exu.dec_i0_pc_d <= instbuff.io.ib_exu.dec_i0_pc_d @[dec.scala 139:22]
+    instbuff.io.dbg_ib.dbg_cmd_addr <= io.dec_dbg.dbg_ib.dbg_cmd_addr @[dec.scala 140:22]
+    instbuff.io.dbg_ib.dbg_cmd_type <= io.dec_dbg.dbg_ib.dbg_cmd_type @[dec.scala 140:22]
+    instbuff.io.dbg_ib.dbg_cmd_write <= io.dec_dbg.dbg_ib.dbg_cmd_write @[dec.scala 140:22]
+    instbuff.io.dbg_ib.dbg_cmd_valid <= io.dec_dbg.dbg_ib.dbg_cmd_valid @[dec.scala 140:22]
+    instbuff.io.ifu_i0_fa_index <= io.ifu_i0_fa_index @[dec.scala 141:31]
+    dec_trigger.io.dec_i0_pc_d <= instbuff.io.ib_exu.dec_i0_pc_d @[dec.scala 142:30]
+    dec_trigger.io.trigger_pkt_any[0].tdata2 <= tlu.io.trigger_pkt_any[0].tdata2 @[dec.scala 143:34]
+    dec_trigger.io.trigger_pkt_any[0].m <= tlu.io.trigger_pkt_any[0].m @[dec.scala 143:34]
+    dec_trigger.io.trigger_pkt_any[0].execute <= tlu.io.trigger_pkt_any[0].execute @[dec.scala 143:34]
+    dec_trigger.io.trigger_pkt_any[0].load <= tlu.io.trigger_pkt_any[0].load @[dec.scala 143:34]
+    dec_trigger.io.trigger_pkt_any[0].store <= tlu.io.trigger_pkt_any[0].store @[dec.scala 143:34]
+    dec_trigger.io.trigger_pkt_any[0].match_pkt <= tlu.io.trigger_pkt_any[0].match_pkt @[dec.scala 143:34]
+    dec_trigger.io.trigger_pkt_any[0].select <= tlu.io.trigger_pkt_any[0].select @[dec.scala 143:34]
+    dec_trigger.io.trigger_pkt_any[1].tdata2 <= tlu.io.trigger_pkt_any[1].tdata2 @[dec.scala 143:34]
+    dec_trigger.io.trigger_pkt_any[1].m <= tlu.io.trigger_pkt_any[1].m @[dec.scala 143:34]
+    dec_trigger.io.trigger_pkt_any[1].execute <= tlu.io.trigger_pkt_any[1].execute @[dec.scala 143:34]
+    dec_trigger.io.trigger_pkt_any[1].load <= tlu.io.trigger_pkt_any[1].load @[dec.scala 143:34]
+    dec_trigger.io.trigger_pkt_any[1].store <= tlu.io.trigger_pkt_any[1].store @[dec.scala 143:34]
+    dec_trigger.io.trigger_pkt_any[1].match_pkt <= tlu.io.trigger_pkt_any[1].match_pkt @[dec.scala 143:34]
+    dec_trigger.io.trigger_pkt_any[1].select <= tlu.io.trigger_pkt_any[1].select @[dec.scala 143:34]
+    dec_trigger.io.trigger_pkt_any[2].tdata2 <= tlu.io.trigger_pkt_any[2].tdata2 @[dec.scala 143:34]
+    dec_trigger.io.trigger_pkt_any[2].m <= tlu.io.trigger_pkt_any[2].m @[dec.scala 143:34]
+    dec_trigger.io.trigger_pkt_any[2].execute <= tlu.io.trigger_pkt_any[2].execute @[dec.scala 143:34]
+    dec_trigger.io.trigger_pkt_any[2].load <= tlu.io.trigger_pkt_any[2].load @[dec.scala 143:34]
+    dec_trigger.io.trigger_pkt_any[2].store <= tlu.io.trigger_pkt_any[2].store @[dec.scala 143:34]
+    dec_trigger.io.trigger_pkt_any[2].match_pkt <= tlu.io.trigger_pkt_any[2].match_pkt @[dec.scala 143:34]
+    dec_trigger.io.trigger_pkt_any[2].select <= tlu.io.trigger_pkt_any[2].select @[dec.scala 143:34]
+    dec_trigger.io.trigger_pkt_any[3].tdata2 <= tlu.io.trigger_pkt_any[3].tdata2 @[dec.scala 143:34]
+    dec_trigger.io.trigger_pkt_any[3].m <= tlu.io.trigger_pkt_any[3].m @[dec.scala 143:34]
+    dec_trigger.io.trigger_pkt_any[3].execute <= tlu.io.trigger_pkt_any[3].execute @[dec.scala 143:34]
+    dec_trigger.io.trigger_pkt_any[3].load <= tlu.io.trigger_pkt_any[3].load @[dec.scala 143:34]
+    dec_trigger.io.trigger_pkt_any[3].store <= tlu.io.trigger_pkt_any[3].store @[dec.scala 143:34]
+    dec_trigger.io.trigger_pkt_any[3].match_pkt <= tlu.io.trigger_pkt_any[3].match_pkt @[dec.scala 143:34]
+    dec_trigger.io.trigger_pkt_any[3].select <= tlu.io.trigger_pkt_any[3].select @[dec.scala 143:34]
+    decode.io.dec_aln.ifu_i0_cinst <= io.ifu_dec.dec_aln.aln_dec.ifu_i0_cinst @[dec.scala 147:21]
+    io.dec_i0_decode_d <= decode.io.dec_i0_decode_d @[dec.scala 148:22]
+    decode.io.decode_exu.exu_csr_rs1_x <= io.dec_exu.decode_exu.exu_csr_rs1_x @[dec.scala 149:23]
+    decode.io.decode_exu.exu_i0_result_x <= io.dec_exu.decode_exu.exu_i0_result_x @[dec.scala 149:23]
+    io.dec_exu.decode_exu.dec_extint_stall <= decode.io.decode_exu.dec_extint_stall @[dec.scala 149:23]
+    io.dec_exu.decode_exu.pred_correct_npc_x <= decode.io.decode_exu.pred_correct_npc_x @[dec.scala 149:23]
+    io.dec_exu.decode_exu.mul_p.bits.bfp <= decode.io.decode_exu.mul_p.bits.bfp @[dec.scala 149:23]
+    io.dec_exu.decode_exu.mul_p.bits.crc32c_w <= decode.io.decode_exu.mul_p.bits.crc32c_w @[dec.scala 149:23]
+    io.dec_exu.decode_exu.mul_p.bits.crc32c_h <= decode.io.decode_exu.mul_p.bits.crc32c_h @[dec.scala 149:23]
+    io.dec_exu.decode_exu.mul_p.bits.crc32c_b <= decode.io.decode_exu.mul_p.bits.crc32c_b @[dec.scala 149:23]
+    io.dec_exu.decode_exu.mul_p.bits.crc32_w <= decode.io.decode_exu.mul_p.bits.crc32_w @[dec.scala 149:23]
+    io.dec_exu.decode_exu.mul_p.bits.crc32_h <= decode.io.decode_exu.mul_p.bits.crc32_h @[dec.scala 149:23]
+    io.dec_exu.decode_exu.mul_p.bits.crc32_b <= decode.io.decode_exu.mul_p.bits.crc32_b @[dec.scala 149:23]
+    io.dec_exu.decode_exu.mul_p.bits.unshfl <= decode.io.decode_exu.mul_p.bits.unshfl @[dec.scala 149:23]
+    io.dec_exu.decode_exu.mul_p.bits.shfl <= decode.io.decode_exu.mul_p.bits.shfl @[dec.scala 149:23]
+    io.dec_exu.decode_exu.mul_p.bits.gorc <= decode.io.decode_exu.mul_p.bits.gorc @[dec.scala 149:23]
+    io.dec_exu.decode_exu.mul_p.bits.grev <= decode.io.decode_exu.mul_p.bits.grev @[dec.scala 149:23]
+    io.dec_exu.decode_exu.mul_p.bits.clmulr <= decode.io.decode_exu.mul_p.bits.clmulr @[dec.scala 149:23]
+    io.dec_exu.decode_exu.mul_p.bits.clmulh <= decode.io.decode_exu.mul_p.bits.clmulh @[dec.scala 149:23]
+    io.dec_exu.decode_exu.mul_p.bits.clmul <= decode.io.decode_exu.mul_p.bits.clmul @[dec.scala 149:23]
+    io.dec_exu.decode_exu.mul_p.bits.bdep <= decode.io.decode_exu.mul_p.bits.bdep @[dec.scala 149:23]
+    io.dec_exu.decode_exu.mul_p.bits.bext <= decode.io.decode_exu.mul_p.bits.bext @[dec.scala 149:23]
+    io.dec_exu.decode_exu.mul_p.bits.low <= decode.io.decode_exu.mul_p.bits.low @[dec.scala 149:23]
+    io.dec_exu.decode_exu.mul_p.bits.rs2_sign <= decode.io.decode_exu.mul_p.bits.rs2_sign @[dec.scala 149:23]
+    io.dec_exu.decode_exu.mul_p.bits.rs1_sign <= decode.io.decode_exu.mul_p.bits.rs1_sign @[dec.scala 149:23]
+    io.dec_exu.decode_exu.mul_p.valid <= decode.io.decode_exu.mul_p.valid @[dec.scala 149:23]
+    io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d <= decode.io.decode_exu.dec_i0_rs2_bypass_en_d @[dec.scala 149:23]
+    io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d <= decode.io.decode_exu.dec_i0_rs1_bypass_en_d @[dec.scala 149:23]
+    io.dec_exu.decode_exu.dec_i0_select_pc_d <= decode.io.decode_exu.dec_i0_select_pc_d @[dec.scala 149:23]
+    io.dec_exu.decode_exu.dec_qual_lsu_d <= decode.io.decode_exu.dec_qual_lsu_d @[dec.scala 149:23]
+    io.dec_exu.decode_exu.dec_i0_result_r <= decode.io.decode_exu.dec_i0_result_r @[dec.scala 149:23]
+    io.dec_exu.decode_exu.dec_i0_immed_d <= decode.io.decode_exu.dec_i0_immed_d @[dec.scala 149:23]
+    io.dec_exu.decode_exu.dec_i0_rs2_en_d <= decode.io.decode_exu.dec_i0_rs2_en_d @[dec.scala 149:23]
+    io.dec_exu.decode_exu.dec_i0_branch_d <= decode.io.decode_exu.dec_i0_branch_d @[dec.scala 149:23]
+    io.dec_exu.decode_exu.dec_i0_rs1_en_d <= decode.io.decode_exu.dec_i0_rs1_en_d @[dec.scala 149:23]
+    io.dec_exu.decode_exu.i0_predict_btag_d <= decode.io.decode_exu.i0_predict_btag_d @[dec.scala 149:23]
+    io.dec_exu.decode_exu.i0_predict_index_d <= decode.io.decode_exu.i0_predict_index_d @[dec.scala 149:23]
+    io.dec_exu.decode_exu.i0_predict_fghr_d <= decode.io.decode_exu.i0_predict_fghr_d @[dec.scala 149:23]
+    io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.prett <= decode.io.decode_exu.dec_i0_predict_p_d.bits.prett @[dec.scala 149:23]
+    io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pret <= decode.io.decode_exu.dec_i0_predict_p_d.bits.pret @[dec.scala 149:23]
+    io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.way <= decode.io.decode_exu.dec_i0_predict_p_d.bits.way @[dec.scala 149:23]
+    io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pja <= decode.io.decode_exu.dec_i0_predict_p_d.bits.pja @[dec.scala 149:23]
+    io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pcall <= decode.io.decode_exu.dec_i0_predict_p_d.bits.pcall @[dec.scala 149:23]
+    io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_start_error <= decode.io.decode_exu.dec_i0_predict_p_d.bits.br_start_error @[dec.scala 149:23]
+    io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_error <= decode.io.decode_exu.dec_i0_predict_p_d.bits.br_error @[dec.scala 149:23]
+    io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.toffset <= decode.io.decode_exu.dec_i0_predict_p_d.bits.toffset @[dec.scala 149:23]
+    io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.hist <= decode.io.decode_exu.dec_i0_predict_p_d.bits.hist @[dec.scala 149:23]
+    io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pc4 <= decode.io.decode_exu.dec_i0_predict_p_d.bits.pc4 @[dec.scala 149:23]
+    io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.boffset <= decode.io.decode_exu.dec_i0_predict_p_d.bits.boffset @[dec.scala 149:23]
+    io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.ataken <= decode.io.decode_exu.dec_i0_predict_p_d.bits.ataken @[dec.scala 149:23]
+    io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.misp <= decode.io.decode_exu.dec_i0_predict_p_d.bits.misp @[dec.scala 149:23]
+    io.dec_exu.decode_exu.dec_i0_predict_p_d.valid <= decode.io.decode_exu.dec_i0_predict_p_d.valid @[dec.scala 149:23]
+    io.dec_exu.decode_exu.i0_ap.csr_imm <= decode.io.decode_exu.i0_ap.csr_imm @[dec.scala 149:23]
+    io.dec_exu.decode_exu.i0_ap.csr_write <= decode.io.decode_exu.i0_ap.csr_write @[dec.scala 149:23]
+    io.dec_exu.decode_exu.i0_ap.predict_nt <= decode.io.decode_exu.i0_ap.predict_nt @[dec.scala 149:23]
+    io.dec_exu.decode_exu.i0_ap.predict_t <= decode.io.decode_exu.i0_ap.predict_t @[dec.scala 149:23]
+    io.dec_exu.decode_exu.i0_ap.jal <= decode.io.decode_exu.i0_ap.jal @[dec.scala 149:23]
+    io.dec_exu.decode_exu.i0_ap.unsign <= decode.io.decode_exu.i0_ap.unsign @[dec.scala 149:23]
+    io.dec_exu.decode_exu.i0_ap.slt <= decode.io.decode_exu.i0_ap.slt @[dec.scala 149:23]
+    io.dec_exu.decode_exu.i0_ap.sub <= decode.io.decode_exu.i0_ap.sub @[dec.scala 149:23]
+    io.dec_exu.decode_exu.i0_ap.add <= decode.io.decode_exu.i0_ap.add @[dec.scala 149:23]
+    io.dec_exu.decode_exu.i0_ap.bge <= decode.io.decode_exu.i0_ap.bge @[dec.scala 149:23]
+    io.dec_exu.decode_exu.i0_ap.blt <= decode.io.decode_exu.i0_ap.blt @[dec.scala 149:23]
+    io.dec_exu.decode_exu.i0_ap.bne <= decode.io.decode_exu.i0_ap.bne @[dec.scala 149:23]
+    io.dec_exu.decode_exu.i0_ap.beq <= decode.io.decode_exu.i0_ap.beq @[dec.scala 149:23]
+    io.dec_exu.decode_exu.i0_ap.sra <= decode.io.decode_exu.i0_ap.sra @[dec.scala 149:23]
+    io.dec_exu.decode_exu.i0_ap.srl <= decode.io.decode_exu.i0_ap.srl @[dec.scala 149:23]
+    io.dec_exu.decode_exu.i0_ap.sll <= decode.io.decode_exu.i0_ap.sll @[dec.scala 149:23]
+    io.dec_exu.decode_exu.i0_ap.lxor <= decode.io.decode_exu.i0_ap.lxor @[dec.scala 149:23]
+    io.dec_exu.decode_exu.i0_ap.lor <= decode.io.decode_exu.i0_ap.lor @[dec.scala 149:23]
+    io.dec_exu.decode_exu.i0_ap.land <= decode.io.decode_exu.i0_ap.land @[dec.scala 149:23]
+    io.dec_exu.decode_exu.i0_ap.zba <= decode.io.decode_exu.i0_ap.zba @[dec.scala 149:23]
+    io.dec_exu.decode_exu.i0_ap.sh3add <= decode.io.decode_exu.i0_ap.sh3add @[dec.scala 149:23]
+    io.dec_exu.decode_exu.i0_ap.sh2add <= decode.io.decode_exu.i0_ap.sh2add @[dec.scala 149:23]
+    io.dec_exu.decode_exu.i0_ap.sh1add <= decode.io.decode_exu.i0_ap.sh1add @[dec.scala 149:23]
+    io.dec_exu.decode_exu.i0_ap.sbext <= decode.io.decode_exu.i0_ap.sbext @[dec.scala 149:23]
+    io.dec_exu.decode_exu.i0_ap.sbinv <= decode.io.decode_exu.i0_ap.sbinv @[dec.scala 149:23]
+    io.dec_exu.decode_exu.i0_ap.sbclr <= decode.io.decode_exu.i0_ap.sbclr @[dec.scala 149:23]
+    io.dec_exu.decode_exu.i0_ap.sbset <= decode.io.decode_exu.i0_ap.sbset @[dec.scala 149:23]
+    io.dec_exu.decode_exu.i0_ap.zbb <= decode.io.decode_exu.i0_ap.zbb @[dec.scala 149:23]
+    io.dec_exu.decode_exu.i0_ap.gorc <= decode.io.decode_exu.i0_ap.gorc @[dec.scala 149:23]
+    io.dec_exu.decode_exu.i0_ap.grev <= decode.io.decode_exu.i0_ap.grev @[dec.scala 149:23]
+    io.dec_exu.decode_exu.i0_ap.ror <= decode.io.decode_exu.i0_ap.ror @[dec.scala 149:23]
+    io.dec_exu.decode_exu.i0_ap.rol <= decode.io.decode_exu.i0_ap.rol @[dec.scala 149:23]
+    io.dec_exu.decode_exu.i0_ap.packh <= decode.io.decode_exu.i0_ap.packh @[dec.scala 149:23]
+    io.dec_exu.decode_exu.i0_ap.packu <= decode.io.decode_exu.i0_ap.packu @[dec.scala 149:23]
+    io.dec_exu.decode_exu.i0_ap.pack <= decode.io.decode_exu.i0_ap.pack @[dec.scala 149:23]
+    io.dec_exu.decode_exu.i0_ap.max <= decode.io.decode_exu.i0_ap.max @[dec.scala 149:23]
+    io.dec_exu.decode_exu.i0_ap.min <= decode.io.decode_exu.i0_ap.min @[dec.scala 149:23]
+    io.dec_exu.decode_exu.i0_ap.sro <= decode.io.decode_exu.i0_ap.sro @[dec.scala 149:23]
+    io.dec_exu.decode_exu.i0_ap.slo <= decode.io.decode_exu.i0_ap.slo @[dec.scala 149:23]
+    io.dec_exu.decode_exu.i0_ap.sext_h <= decode.io.decode_exu.i0_ap.sext_h @[dec.scala 149:23]
+    io.dec_exu.decode_exu.i0_ap.sext_b <= decode.io.decode_exu.i0_ap.sext_b @[dec.scala 149:23]
+    io.dec_exu.decode_exu.i0_ap.pcnt <= decode.io.decode_exu.i0_ap.pcnt @[dec.scala 149:23]
+    io.dec_exu.decode_exu.i0_ap.ctz <= decode.io.decode_exu.i0_ap.ctz @[dec.scala 149:23]
+    io.dec_exu.decode_exu.i0_ap.clz <= decode.io.decode_exu.i0_ap.clz @[dec.scala 149:23]
+    io.dec_exu.decode_exu.dec_ctl_en <= decode.io.decode_exu.dec_ctl_en @[dec.scala 149:23]
+    io.dec_exu.decode_exu.dec_data_en <= decode.io.decode_exu.dec_data_en @[dec.scala 149:23]
+    decode.io.dec_alu.exu_i0_pc_x <= io.dec_exu.dec_alu.exu_i0_pc_x @[dec.scala 150:20]
+    io.dec_exu.dec_alu.dec_i0_br_immed_d <= decode.io.dec_alu.dec_i0_br_immed_d @[dec.scala 150:20]
+    io.dec_exu.dec_alu.dec_csr_ren_d <= decode.io.dec_alu.dec_csr_ren_d @[dec.scala 150:20]
+    io.dec_exu.dec_alu.dec_i0_alu_decode_d <= decode.io.dec_alu.dec_i0_alu_decode_d @[dec.scala 150:20]
+    io.dec_exu.dec_div.dec_div_cancel <= decode.io.dec_div.dec_div_cancel @[dec.scala 151:20]
+    io.dec_exu.dec_div.div_p.bits.rem <= decode.io.dec_div.div_p.bits.rem @[dec.scala 151:20]
+    io.dec_exu.dec_div.div_p.bits.unsign <= decode.io.dec_div.div_p.bits.unsign @[dec.scala 151:20]
+    io.dec_exu.dec_div.div_p.valid <= decode.io.dec_div.div_p.valid @[dec.scala 151:20]
+    decode.io.dctl_dma.dma_dccm_stall_any <= io.dec_dma.dctl_dma.dma_dccm_stall_any @[dec.scala 152:22]
+    decode.io.dec_tlu_trace_disable <= tlu.io.dec_tlu_trace_disable @[dec.scala 153:48]
+    decode.io.dec_debug_valid_d <= instbuff.io.dec_debug_fence_d @[dec.scala 154:48]
+    decode.io.dec_tlu_flush_extint <= tlu.io.dec_tlu_flush_extint @[dec.scala 155:48]
+    decode.io.dec_tlu_force_halt <= tlu.io.tlu_mem.dec_tlu_force_halt @[dec.scala 156:48]
+    decode.io.dctl_busbuff.lsu_nonblock_load_data_tag <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_tag @[dec.scala 157:26]
+    decode.io.dctl_busbuff.lsu_nonblock_load_data_error <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_error @[dec.scala 157:26]
+    decode.io.dctl_busbuff.lsu_nonblock_load_data_valid <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_valid @[dec.scala 157:26]
+    decode.io.dctl_busbuff.lsu_nonblock_load_inv_tag_r <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_tag_r @[dec.scala 157:26]
+    decode.io.dctl_busbuff.lsu_nonblock_load_inv_r <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_r @[dec.scala 157:26]
+    decode.io.dctl_busbuff.lsu_nonblock_load_tag_m <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_tag_m @[dec.scala 157:26]
+    decode.io.dctl_busbuff.lsu_nonblock_load_valid_m <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_valid_m @[dec.scala 157:26]
+    decode.io.dec_i0_trigger_match_d <= dec_trigger.io.dec_i0_trigger_match_d @[dec.scala 158:48]
+    decode.io.dec_tlu_wr_pause_r <= tlu.io.dec_tlu_wr_pause_r @[dec.scala 159:48]
+    decode.io.dec_tlu_pipelining_disable <= tlu.io.dec_tlu_pipelining_disable @[dec.scala 160:48]
+    decode.io.lsu_trigger_match_m <= io.lsu_trigger_match_m @[dec.scala 161:48]
+    decode.io.lsu_pmu_misaligned_m <= io.lsu_pmu_misaligned_m @[dec.scala 162:48]
+    decode.io.dec_tlu_debug_stall <= tlu.io.dec_tlu_debug_stall @[dec.scala 163:48]
+    decode.io.dec_i0_bp_fa_index <= instbuff.io.dec_i0_bp_fa_index @[dec.scala 164:48]
+    decode.io.dec_tlu_flush_leak_one_r <= tlu.io.tlu_bp.dec_tlu_flush_leak_one_wb @[dec.scala 165:48]
+    decode.io.dec_debug_fence_d <= instbuff.io.dec_debug_fence_d @[dec.scala 166:48]
+    decode.io.dbg_dctl.dbg_cmd_wrdata <= io.dec_dbg.dbg_dctl.dbg_cmd_wrdata @[dec.scala 167:22]
+    decode.io.dec_i0_icaf_d <= instbuff.io.dec_i0_icaf_d @[dec.scala 168:48]
+    decode.io.dec_i0_icaf_second_d <= instbuff.io.dec_i0_icaf_second_d @[dec.scala 169:48]
+    decode.io.dec_i0_icaf_type_d <= instbuff.io.dec_i0_icaf_type_d @[dec.scala 170:48]
+    decode.io.dec_i0_dbecc_d <= instbuff.io.dec_i0_dbecc_d @[dec.scala 171:48]
+    decode.io.dec_i0_brp.bits.ret <= instbuff.io.dec_i0_brp.bits.ret @[dec.scala 172:48]
+    decode.io.dec_i0_brp.bits.way <= instbuff.io.dec_i0_brp.bits.way @[dec.scala 172:48]
+    decode.io.dec_i0_brp.bits.prett <= instbuff.io.dec_i0_brp.bits.prett @[dec.scala 172:48]
+    decode.io.dec_i0_brp.bits.bank <= instbuff.io.dec_i0_brp.bits.bank @[dec.scala 172:48]
+    decode.io.dec_i0_brp.bits.br_start_error <= instbuff.io.dec_i0_brp.bits.br_start_error @[dec.scala 172:48]
+    decode.io.dec_i0_brp.bits.br_error <= instbuff.io.dec_i0_brp.bits.br_error @[dec.scala 172:48]
+    decode.io.dec_i0_brp.bits.hist <= instbuff.io.dec_i0_brp.bits.hist @[dec.scala 172:48]
+    decode.io.dec_i0_brp.bits.toffset <= instbuff.io.dec_i0_brp.bits.toffset @[dec.scala 172:48]
+    decode.io.dec_i0_brp.valid <= instbuff.io.dec_i0_brp.valid @[dec.scala 172:48]
+    decode.io.dec_i0_bp_index <= instbuff.io.dec_i0_bp_index @[dec.scala 173:48]
+    decode.io.dec_i0_bp_fghr <= instbuff.io.dec_i0_bp_fghr @[dec.scala 174:48]
+    decode.io.dec_i0_bp_btag <= instbuff.io.dec_i0_bp_btag @[dec.scala 175:48]
+    decode.io.lsu_idle_any <= io.lsu_idle_any @[dec.scala 176:48]
+    decode.io.lsu_load_stall_any <= io.lsu_load_stall_any @[dec.scala 177:48]
+    decode.io.lsu_store_stall_any <= io.lsu_store_stall_any @[dec.scala 178:48]
+    decode.io.exu_div_wren <= io.exu_div_wren @[dec.scala 179:48]
+    decode.io.dec_tlu_i0_kill_writeb_wb <= tlu.io.dec_tlu_i0_kill_writeb_wb @[dec.scala 180:48]
+    decode.io.dec_tlu_flush_lower_wb <= tlu.io.dec_tlu_flush_lower_wb @[dec.scala 181:48]
+    decode.io.dec_tlu_i0_kill_writeb_r <= tlu.io.dec_tlu_i0_kill_writeb_r @[dec.scala 182:48]
+    decode.io.dec_tlu_flush_lower_r <= tlu.io.tlu_exu.dec_tlu_flush_lower_r @[dec.scala 183:48]
+    decode.io.dec_tlu_flush_pause_r <= tlu.io.dec_tlu_flush_pause_r @[dec.scala 184:48]
+    decode.io.dec_tlu_presync_d <= tlu.io.dec_tlu_presync_d @[dec.scala 185:48]
+    decode.io.dec_tlu_postsync_d <= tlu.io.dec_tlu_postsync_d @[dec.scala 186:48]
+    decode.io.dec_i0_pc4_d <= instbuff.io.dec_i0_pc4_d @[dec.scala 187:48]
+    decode.io.dec_csr_rddata_d <= tlu.io.dec_csr_rddata_d @[dec.scala 188:48]
+    decode.io.dec_csr_legal_d <= tlu.io.dec_csr_legal_d @[dec.scala 189:48]
+    decode.io.lsu_result_m <= io.lsu_result_m @[dec.scala 190:48]
+    decode.io.lsu_result_corr_r <= io.lsu_result_corr_r @[dec.scala 191:48]
+    decode.io.exu_flush_final <= io.exu_flush_final @[dec.scala 192:48]
+    decode.io.dec_i0_instr_d <= instbuff.io.dec_i0_instr_d @[dec.scala 193:48]
+    decode.io.dec_ib0_valid_d <= instbuff.io.dec_ib0_valid_d @[dec.scala 194:48]
+    decode.io.free_l2clk <= io.free_l2clk @[dec.scala 195:48]
+    decode.io.active_clk <= io.active_clk @[dec.scala 196:48]
+    decode.io.clk_override <= tlu.io.dec_tlu_dec_clk_override @[dec.scala 197:48]
+    decode.io.scan_mode <= io.scan_mode @[dec.scala 198:48]
+    dec_i0_inst_wb1 <= decode.io.dec_i0_inst_wb @[dec.scala 199:48]
+    dec_i0_pc_wb1 <= decode.io.dec_i0_pc_wb @[dec.scala 200:48]
+    io.lsu_p.bits.store_data_bypass_m <= decode.io.lsu_p.bits.store_data_bypass_m @[dec.scala 201:48]
+    io.lsu_p.bits.load_ldst_bypass_d <= decode.io.lsu_p.bits.load_ldst_bypass_d @[dec.scala 201:48]
+    io.lsu_p.bits.store_data_bypass_d <= decode.io.lsu_p.bits.store_data_bypass_d @[dec.scala 201:48]
+    io.lsu_p.bits.dma <= decode.io.lsu_p.bits.dma @[dec.scala 201:48]
+    io.lsu_p.bits.unsign <= decode.io.lsu_p.bits.unsign @[dec.scala 201:48]
+    io.lsu_p.bits.store <= decode.io.lsu_p.bits.store @[dec.scala 201:48]
+    io.lsu_p.bits.load <= decode.io.lsu_p.bits.load @[dec.scala 201:48]
+    io.lsu_p.bits.dword <= decode.io.lsu_p.bits.dword @[dec.scala 201:48]
+    io.lsu_p.bits.word <= decode.io.lsu_p.bits.word @[dec.scala 201:48]
+    io.lsu_p.bits.half <= decode.io.lsu_p.bits.half @[dec.scala 201:48]
+    io.lsu_p.bits.by <= decode.io.lsu_p.bits.by @[dec.scala 201:48]
+    io.lsu_p.bits.stack <= decode.io.lsu_p.bits.stack @[dec.scala 201:48]
+    io.lsu_p.bits.fast_int <= decode.io.lsu_p.bits.fast_int @[dec.scala 201:48]
+    io.lsu_p.valid <= decode.io.lsu_p.valid @[dec.scala 201:48]
+    io.dec_lsu_valid_raw_d <= decode.io.dec_lsu_valid_raw_d @[dec.scala 202:48]
+    io.dec_lsu_offset_d <= decode.io.dec_lsu_offset_d @[dec.scala 203:48]
+    io.dec_pause_state_cg <= decode.io.dec_pause_state_cg @[dec.scala 204:48]
+    io.dec_exu.decode_exu.dec_qual_lsu_d <= decode.io.decode_exu.dec_qual_lsu_d @[dec.scala 205:48]
+    io.dec_fa_error_index <= decode.io.dec_fa_error_index @[dec.scala 206:48]
+    gpr.io.raddr0 <= decode.io.dec_i0_rs1_d @[dec.scala 208:23]
+    gpr.io.raddr1 <= decode.io.dec_i0_rs2_d @[dec.scala 209:23]
+    gpr.io.wen0 <= decode.io.dec_i0_wen_r @[dec.scala 210:23]
+    gpr.io.waddr0 <= decode.io.dec_i0_waddr_r @[dec.scala 211:23]
+    gpr.io.wd0 <= decode.io.dec_i0_wdata_r @[dec.scala 212:23]
+    gpr.io.wen1 <= decode.io.dec_nonblock_load_wen @[dec.scala 213:23]
+    gpr.io.waddr1 <= decode.io.dec_nonblock_load_waddr @[dec.scala 214:23]
+    gpr.io.wd1 <= io.lsu_nonblock_load_data @[dec.scala 215:23]
+    gpr.io.wen2 <= io.exu_div_wren @[dec.scala 216:23]
+    gpr.io.waddr2 <= decode.io.div_waddr_wb @[dec.scala 217:23]
+    gpr.io.wd2 <= io.exu_div_result @[dec.scala 218:23]
+    gpr.io.scan_mode <= io.scan_mode @[dec.scala 219:23]
+    io.dec_exu.gpr_exu.gpr_i0_rs2_d <= gpr.io.gpr_exu.gpr_i0_rs2_d @[dec.scala 220:22]
+    io.dec_exu.gpr_exu.gpr_i0_rs1_d <= gpr.io.gpr_exu.gpr_i0_rs1_d @[dec.scala 220:22]
+    tlu.io.tlu_mem.ifu_miss_state_idle <= io.ifu_dec.dec_mem_ctrl.ifu_miss_state_idle @[dec.scala 222:18]
+    tlu.io.tlu_mem.ifu_ic_debug_rd_data_valid <= io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data_valid @[dec.scala 222:18]
+    tlu.io.tlu_mem.ifu_ic_debug_rd_data <= io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data @[dec.scala 222:18]
+    tlu.io.tlu_mem.ifu_iccm_rd_ecc_single_err <= io.ifu_dec.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err @[dec.scala 222:18]
+    tlu.io.tlu_mem.ifu_ic_error_start <= io.ifu_dec.dec_mem_ctrl.ifu_ic_error_start @[dec.scala 222:18]
+    tlu.io.tlu_mem.ifu_pmu_bus_trxn <= io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_trxn @[dec.scala 222:18]
+    tlu.io.tlu_mem.ifu_pmu_bus_busy <= io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_busy @[dec.scala 222:18]
+    tlu.io.tlu_mem.ifu_pmu_bus_error <= io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_error @[dec.scala 222:18]
+    tlu.io.tlu_mem.ifu_pmu_ic_hit <= io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_hit @[dec.scala 222:18]
+    tlu.io.tlu_mem.ifu_pmu_ic_miss <= io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_miss @[dec.scala 222:18]
+    io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable <= tlu.io.tlu_mem.dec_tlu_core_ecc_disable @[dec.scala 222:18]
+    io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid <= tlu.io.tlu_mem.dec_tlu_ic_diag_pkt.icache_wr_valid @[dec.scala 222:18]
+    io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid <= tlu.io.tlu_mem.dec_tlu_ic_diag_pkt.icache_rd_valid @[dec.scala 222:18]
+    io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics <= tlu.io.tlu_mem.dec_tlu_ic_diag_pkt.icache_dicawics @[dec.scala 222:18]
+    io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata <= tlu.io.tlu_mem.dec_tlu_ic_diag_pkt.icache_wrdata @[dec.scala 222:18]
+    io.ifu_dec.dec_mem_ctrl.dec_tlu_fence_i_wb <= tlu.io.tlu_mem.dec_tlu_fence_i_wb @[dec.scala 222:18]
+    io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt <= tlu.io.tlu_mem.dec_tlu_force_halt @[dec.scala 222:18]
+    io.ifu_dec.dec_mem_ctrl.dec_tlu_i0_commit_cmt <= tlu.io.tlu_mem.dec_tlu_i0_commit_cmt @[dec.scala 222:18]
+    io.ifu_dec.dec_mem_ctrl.dec_tlu_flush_err_wb <= tlu.io.tlu_mem.dec_tlu_flush_err_wb @[dec.scala 222:18]
+    tlu.io.tlu_ifc.ifu_pmu_fetch_stall <= io.ifu_dec.dec_ifc.ifu_pmu_fetch_stall @[dec.scala 223:18]
+    io.ifu_dec.dec_ifc.dec_tlu_mrac_ff <= tlu.io.tlu_ifc.dec_tlu_mrac_ff @[dec.scala 223:18]
+    io.ifu_dec.dec_ifc.dec_tlu_flush_noredir_wb <= tlu.io.tlu_ifc.dec_tlu_flush_noredir_wb @[dec.scala 223:18]
+    io.ifu_dec.dec_bp.dec_tlu_bpred_disable <= tlu.io.tlu_bp.dec_tlu_bpred_disable @[dec.scala 224:18]
+    io.ifu_dec.dec_bp.dec_tlu_flush_leak_one_wb <= tlu.io.tlu_bp.dec_tlu_flush_leak_one_wb @[dec.scala 224:18]
+    io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.middle <= tlu.io.tlu_bp.dec_tlu_br0_r_pkt.bits.middle @[dec.scala 224:18]
+    io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.way <= tlu.io.tlu_bp.dec_tlu_br0_r_pkt.bits.way @[dec.scala 224:18]
+    io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_start_error <= tlu.io.tlu_bp.dec_tlu_br0_r_pkt.bits.br_start_error @[dec.scala 224:18]
+    io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_error <= tlu.io.tlu_bp.dec_tlu_br0_r_pkt.bits.br_error @[dec.scala 224:18]
+    io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.hist <= tlu.io.tlu_bp.dec_tlu_br0_r_pkt.bits.hist @[dec.scala 224:18]
+    io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.valid <= tlu.io.tlu_bp.dec_tlu_br0_r_pkt.valid @[dec.scala 224:18]
+    tlu.io.tlu_exu.exu_npc_r <= io.dec_exu.tlu_exu.exu_npc_r @[dec.scala 225:18]
+    tlu.io.tlu_exu.exu_pmu_i0_pc4 <= io.dec_exu.tlu_exu.exu_pmu_i0_pc4 @[dec.scala 225:18]
+    tlu.io.tlu_exu.exu_pmu_i0_br_ataken <= io.dec_exu.tlu_exu.exu_pmu_i0_br_ataken @[dec.scala 225:18]
+    tlu.io.tlu_exu.exu_pmu_i0_br_misp <= io.dec_exu.tlu_exu.exu_pmu_i0_br_misp @[dec.scala 225:18]
+    tlu.io.tlu_exu.exu_i0_br_middle_r <= io.dec_exu.tlu_exu.exu_i0_br_middle_r @[dec.scala 225:18]
+    tlu.io.tlu_exu.exu_i0_br_mp_r <= io.dec_exu.tlu_exu.exu_i0_br_mp_r @[dec.scala 225:18]
+    tlu.io.tlu_exu.exu_i0_br_valid_r <= io.dec_exu.tlu_exu.exu_i0_br_valid_r @[dec.scala 225:18]
+    tlu.io.tlu_exu.exu_i0_br_index_r <= io.dec_exu.tlu_exu.exu_i0_br_index_r @[dec.scala 225:18]
+    tlu.io.tlu_exu.exu_i0_br_start_error_r <= io.dec_exu.tlu_exu.exu_i0_br_start_error_r @[dec.scala 225:18]
+    tlu.io.tlu_exu.exu_i0_br_error_r <= io.dec_exu.tlu_exu.exu_i0_br_error_r @[dec.scala 225:18]
+    tlu.io.tlu_exu.exu_i0_br_hist_r <= io.dec_exu.tlu_exu.exu_i0_br_hist_r @[dec.scala 225:18]
+    io.dec_exu.tlu_exu.dec_tlu_flush_path_r <= tlu.io.tlu_exu.dec_tlu_flush_path_r @[dec.scala 225:18]
+    io.dec_exu.tlu_exu.dec_tlu_flush_lower_r <= tlu.io.tlu_exu.dec_tlu_flush_lower_r @[dec.scala 225:18]
+    io.dec_exu.tlu_exu.dec_tlu_meihap <= tlu.io.tlu_exu.dec_tlu_meihap @[dec.scala 225:18]
+    tlu.io.tlu_dma.dma_iccm_stall_any <= io.dec_dma.tlu_dma.dma_iccm_stall_any @[dec.scala 226:18]
+    tlu.io.tlu_dma.dma_dccm_stall_any <= io.dec_dma.tlu_dma.dma_dccm_stall_any @[dec.scala 226:18]
+    io.dec_dma.tlu_dma.dec_tlu_dma_qos_prty <= tlu.io.tlu_dma.dec_tlu_dma_qos_prty @[dec.scala 226:18]
+    tlu.io.tlu_dma.dma_pmu_any_write <= io.dec_dma.tlu_dma.dma_pmu_any_write @[dec.scala 226:18]
+    tlu.io.tlu_dma.dma_pmu_any_read <= io.dec_dma.tlu_dma.dma_pmu_any_read @[dec.scala 226:18]
+    tlu.io.tlu_dma.dma_pmu_dccm_write <= io.dec_dma.tlu_dma.dma_pmu_dccm_write @[dec.scala 226:18]
+    tlu.io.tlu_dma.dma_pmu_dccm_read <= io.dec_dma.tlu_dma.dma_pmu_dccm_read @[dec.scala 226:18]
+    tlu.io.free_l2clk <= io.free_l2clk @[dec.scala 227:45]
+    tlu.io.free_clk <= io.free_clk @[dec.scala 228:45]
+    tlu.io.scan_mode <= io.scan_mode @[dec.scala 229:45]
+    tlu.io.rst_vec <= io.rst_vec @[dec.scala 230:45]
+    tlu.io.nmi_int <= io.nmi_int @[dec.scala 231:45]
+    tlu.io.nmi_vec <= io.nmi_vec @[dec.scala 232:45]
+    tlu.io.i_cpu_halt_req <= io.i_cpu_halt_req @[dec.scala 233:45]
+    tlu.io.i_cpu_run_req <= io.i_cpu_run_req @[dec.scala 234:45]
+    tlu.io.lsu_fastint_stall_any <= io.lsu_fastint_stall_any @[dec.scala 235:45]
+    tlu.io.ifu_pmu_instr_aligned <= io.ifu_dec.dec_aln.ifu_pmu_instr_aligned @[dec.scala 236:45]
+    tlu.io.dec_pmu_instr_decoded <= decode.io.dec_pmu_instr_decoded @[dec.scala 237:45]
+    tlu.io.dec_pmu_decode_stall <= decode.io.dec_pmu_decode_stall @[dec.scala 238:45]
+    tlu.io.dec_pmu_presync_stall <= decode.io.dec_pmu_presync_stall @[dec.scala 239:45]
+    tlu.io.dec_pmu_postsync_stall <= decode.io.dec_pmu_postsync_stall @[dec.scala 240:45]
+    tlu.io.lsu_store_stall_any <= io.lsu_store_stall_any @[dec.scala 241:45]
+    tlu.io.tlu_busbuff.lsu_imprecise_error_addr_any <= io.lsu_dec.tlu_busbuff.lsu_imprecise_error_addr_any @[dec.scala 242:26]
+    tlu.io.tlu_busbuff.lsu_imprecise_error_store_any <= io.lsu_dec.tlu_busbuff.lsu_imprecise_error_store_any @[dec.scala 242:26]
+    tlu.io.tlu_busbuff.lsu_imprecise_error_load_any <= io.lsu_dec.tlu_busbuff.lsu_imprecise_error_load_any @[dec.scala 242:26]
+    io.lsu_dec.tlu_busbuff.dec_tlu_sideeffect_posted_disable <= tlu.io.tlu_busbuff.dec_tlu_sideeffect_posted_disable @[dec.scala 242:26]
+    io.lsu_dec.tlu_busbuff.dec_tlu_wb_coalescing_disable <= tlu.io.tlu_busbuff.dec_tlu_wb_coalescing_disable @[dec.scala 242:26]
+    io.lsu_dec.tlu_busbuff.dec_tlu_external_ldfwd_disable <= tlu.io.tlu_busbuff.dec_tlu_external_ldfwd_disable @[dec.scala 242:26]
+    tlu.io.tlu_busbuff.lsu_pmu_bus_busy <= io.lsu_dec.tlu_busbuff.lsu_pmu_bus_busy @[dec.scala 242:26]
+    tlu.io.tlu_busbuff.lsu_pmu_bus_error <= io.lsu_dec.tlu_busbuff.lsu_pmu_bus_error @[dec.scala 242:26]
+    tlu.io.tlu_busbuff.lsu_pmu_bus_misaligned <= io.lsu_dec.tlu_busbuff.lsu_pmu_bus_misaligned @[dec.scala 242:26]
+    tlu.io.tlu_busbuff.lsu_pmu_bus_trxn <= io.lsu_dec.tlu_busbuff.lsu_pmu_bus_trxn @[dec.scala 242:26]
+    tlu.io.lsu_tlu.lsu_pmu_store_external_m <= io.lsu_tlu.lsu_pmu_store_external_m @[dec.scala 243:14]
+    tlu.io.lsu_tlu.lsu_pmu_load_external_m <= io.lsu_tlu.lsu_pmu_load_external_m @[dec.scala 243:14]
+    tlu.io.dec_pic.mexintpend <= io.dec_pic.mexintpend @[dec.scala 244:14]
+    io.dec_pic.dec_tlu_meipt <= tlu.io.dec_pic.dec_tlu_meipt @[dec.scala 244:14]
+    io.dec_pic.dec_tlu_meicurpl <= tlu.io.dec_pic.dec_tlu_meicurpl @[dec.scala 244:14]
+    tlu.io.dec_pic.mhwakeup <= io.dec_pic.mhwakeup @[dec.scala 244:14]
+    tlu.io.dec_pic.pic_pl <= io.dec_pic.pic_pl @[dec.scala 244:14]
+    tlu.io.dec_pic.pic_claimid <= io.dec_pic.pic_claimid @[dec.scala 244:14]
+    tlu.io.lsu_fir_addr <= io.lsu_fir_addr @[dec.scala 245:45]
+    tlu.io.lsu_fir_error <= io.lsu_fir_error @[dec.scala 246:45]
+    tlu.io.iccm_dma_sb_error <= io.iccm_dma_sb_error @[dec.scala 247:45]
+    tlu.io.lsu_error_pkt_r.bits.addr <= io.lsu_error_pkt_r.bits.addr @[dec.scala 248:45]
+    tlu.io.lsu_error_pkt_r.bits.mscause <= io.lsu_error_pkt_r.bits.mscause @[dec.scala 248:45]
+    tlu.io.lsu_error_pkt_r.bits.exc_type <= io.lsu_error_pkt_r.bits.exc_type @[dec.scala 248:45]
+    tlu.io.lsu_error_pkt_r.bits.inst_type <= io.lsu_error_pkt_r.bits.inst_type @[dec.scala 248:45]
+    tlu.io.lsu_error_pkt_r.bits.single_ecc_error <= io.lsu_error_pkt_r.bits.single_ecc_error @[dec.scala 248:45]
+    tlu.io.lsu_error_pkt_r.valid <= io.lsu_error_pkt_r.valid @[dec.scala 248:45]
+    tlu.io.lsu_single_ecc_error_incr <= io.lsu_single_ecc_error_incr @[dec.scala 249:45]
+    tlu.io.dec_pause_state <= decode.io.dec_pause_state @[dec.scala 250:45]
+    tlu.io.dec_csr_wen_unq_d <= decode.io.dec_csr_wen_unq_d @[dec.scala 251:45]
+    tlu.io.dec_csr_any_unq_d <= decode.io.dec_csr_any_unq_d @[dec.scala 252:45]
+    tlu.io.dec_csr_rdaddr_d <= decode.io.dec_csr_rdaddr_d @[dec.scala 253:45]
+    tlu.io.dec_csr_wen_r <= decode.io.dec_csr_wen_r @[dec.scala 254:45]
+    tlu.io.dec_csr_wraddr_r <= decode.io.dec_csr_wraddr_r @[dec.scala 255:45]
+    tlu.io.dec_csr_wrdata_r <= decode.io.dec_csr_wrdata_r @[dec.scala 256:45]
+    tlu.io.dec_csr_stall_int_ff <= decode.io.dec_csr_stall_int_ff @[dec.scala 257:45]
+    tlu.io.dec_tlu_i0_valid_r <= decode.io.dec_tlu_i0_valid_r @[dec.scala 258:45]
+    tlu.io.dec_tlu_i0_pc_r <= decode.io.dec_tlu_i0_pc_r @[dec.scala 259:45]
+    tlu.io.dec_tlu_packet_r.pmu_lsu_misaligned <= decode.io.dec_tlu_packet_r.pmu_lsu_misaligned @[dec.scala 260:45]
+    tlu.io.dec_tlu_packet_r.pmu_divide <= decode.io.dec_tlu_packet_r.pmu_divide @[dec.scala 260:45]
+    tlu.io.dec_tlu_packet_r.pmu_i0_br_unpred <= decode.io.dec_tlu_packet_r.pmu_i0_br_unpred @[dec.scala 260:45]
+    tlu.io.dec_tlu_packet_r.pmu_i0_itype <= decode.io.dec_tlu_packet_r.pmu_i0_itype @[dec.scala 260:45]
+    tlu.io.dec_tlu_packet_r.i0trigger <= decode.io.dec_tlu_packet_r.i0trigger @[dec.scala 260:45]
+    tlu.io.dec_tlu_packet_r.fence_i <= decode.io.dec_tlu_packet_r.fence_i @[dec.scala 260:45]
+    tlu.io.dec_tlu_packet_r.icaf_type <= decode.io.dec_tlu_packet_r.icaf_type @[dec.scala 260:45]
+    tlu.io.dec_tlu_packet_r.icaf_second <= decode.io.dec_tlu_packet_r.icaf_second @[dec.scala 260:45]
+    tlu.io.dec_tlu_packet_r.icaf <= decode.io.dec_tlu_packet_r.icaf @[dec.scala 260:45]
+    tlu.io.dec_tlu_packet_r.legal <= decode.io.dec_tlu_packet_r.legal @[dec.scala 260:45]
+    tlu.io.dec_illegal_inst <= decode.io.dec_illegal_inst @[dec.scala 261:45]
+    tlu.io.dec_i0_decode_d <= decode.io.dec_i0_decode_d @[dec.scala 262:45]
+    tlu.io.exu_i0_br_way_r <= io.exu_i0_br_way_r @[dec.scala 263:45]
+    tlu.io.dbg_halt_req <= io.dbg_halt_req @[dec.scala 264:45]
+    tlu.io.dbg_resume_req <= io.dbg_resume_req @[dec.scala 265:45]
+    tlu.io.lsu_idle_any <= io.lsu_idle_any @[dec.scala 266:45]
+    tlu.io.dec_div_active <= decode.io.dec_div_active @[dec.scala 267:45]
+    tlu.io.timer_int <= io.timer_int @[dec.scala 268:45]
+    tlu.io.soft_int <= io.soft_int @[dec.scala 269:45]
+    tlu.io.core_id <= io.core_id @[dec.scala 270:45]
+    tlu.io.mpc_debug_halt_req <= io.mpc_debug_halt_req @[dec.scala 271:45]
+    tlu.io.mpc_debug_run_req <= io.mpc_debug_run_req @[dec.scala 272:45]
+    tlu.io.mpc_reset_run_req <= io.mpc_reset_run_req @[dec.scala 273:45]
+    io.dec_dbg_cmd_done <= tlu.io.dec_dbg_cmd_done @[dec.scala 274:28]
+    io.dec_dbg_cmd_fail <= tlu.io.dec_dbg_cmd_fail @[dec.scala 275:28]
+    io.dec_tlu_dbg_halted <= tlu.io.dec_tlu_dbg_halted @[dec.scala 276:28]
+    io.dec_tlu_debug_mode <= tlu.io.dec_tlu_debug_mode @[dec.scala 277:28]
+    io.dec_tlu_resume_ack <= tlu.io.dec_tlu_resume_ack @[dec.scala 278:28]
+    io.dec_tlu_mpc_halted_only <= tlu.io.dec_tlu_mpc_halted_only @[dec.scala 279:51]
+    io.trigger_pkt_any[0].tdata2 <= tlu.io.trigger_pkt_any[0].tdata2 @[dec.scala 280:29]
+    io.trigger_pkt_any[0].m <= tlu.io.trigger_pkt_any[0].m @[dec.scala 280:29]
+    io.trigger_pkt_any[0].execute <= tlu.io.trigger_pkt_any[0].execute @[dec.scala 280:29]
+    io.trigger_pkt_any[0].load <= tlu.io.trigger_pkt_any[0].load @[dec.scala 280:29]
+    io.trigger_pkt_any[0].store <= tlu.io.trigger_pkt_any[0].store @[dec.scala 280:29]
+    io.trigger_pkt_any[0].match_pkt <= tlu.io.trigger_pkt_any[0].match_pkt @[dec.scala 280:29]
+    io.trigger_pkt_any[0].select <= tlu.io.trigger_pkt_any[0].select @[dec.scala 280:29]
+    io.trigger_pkt_any[1].tdata2 <= tlu.io.trigger_pkt_any[1].tdata2 @[dec.scala 280:29]
+    io.trigger_pkt_any[1].m <= tlu.io.trigger_pkt_any[1].m @[dec.scala 280:29]
+    io.trigger_pkt_any[1].execute <= tlu.io.trigger_pkt_any[1].execute @[dec.scala 280:29]
+    io.trigger_pkt_any[1].load <= tlu.io.trigger_pkt_any[1].load @[dec.scala 280:29]
+    io.trigger_pkt_any[1].store <= tlu.io.trigger_pkt_any[1].store @[dec.scala 280:29]
+    io.trigger_pkt_any[1].match_pkt <= tlu.io.trigger_pkt_any[1].match_pkt @[dec.scala 280:29]
+    io.trigger_pkt_any[1].select <= tlu.io.trigger_pkt_any[1].select @[dec.scala 280:29]
+    io.trigger_pkt_any[2].tdata2 <= tlu.io.trigger_pkt_any[2].tdata2 @[dec.scala 280:29]
+    io.trigger_pkt_any[2].m <= tlu.io.trigger_pkt_any[2].m @[dec.scala 280:29]
+    io.trigger_pkt_any[2].execute <= tlu.io.trigger_pkt_any[2].execute @[dec.scala 280:29]
+    io.trigger_pkt_any[2].load <= tlu.io.trigger_pkt_any[2].load @[dec.scala 280:29]
+    io.trigger_pkt_any[2].store <= tlu.io.trigger_pkt_any[2].store @[dec.scala 280:29]
+    io.trigger_pkt_any[2].match_pkt <= tlu.io.trigger_pkt_any[2].match_pkt @[dec.scala 280:29]
+    io.trigger_pkt_any[2].select <= tlu.io.trigger_pkt_any[2].select @[dec.scala 280:29]
+    io.trigger_pkt_any[3].tdata2 <= tlu.io.trigger_pkt_any[3].tdata2 @[dec.scala 280:29]
+    io.trigger_pkt_any[3].m <= tlu.io.trigger_pkt_any[3].m @[dec.scala 280:29]
+    io.trigger_pkt_any[3].execute <= tlu.io.trigger_pkt_any[3].execute @[dec.scala 280:29]
+    io.trigger_pkt_any[3].load <= tlu.io.trigger_pkt_any[3].load @[dec.scala 280:29]
+    io.trigger_pkt_any[3].store <= tlu.io.trigger_pkt_any[3].store @[dec.scala 280:29]
+    io.trigger_pkt_any[3].match_pkt <= tlu.io.trigger_pkt_any[3].match_pkt @[dec.scala 280:29]
+    io.trigger_pkt_any[3].select <= tlu.io.trigger_pkt_any[3].select @[dec.scala 280:29]
+    io.o_cpu_halt_status <= tlu.io.o_cpu_halt_status @[dec.scala 281:29]
+    io.o_cpu_halt_ack <= tlu.io.o_cpu_halt_ack @[dec.scala 282:29]
+    io.o_cpu_run_ack <= tlu.io.o_cpu_run_ack @[dec.scala 283:29]
+    io.o_debug_mode_status <= tlu.io.o_debug_mode_status @[dec.scala 284:29]
+    io.mpc_debug_halt_ack <= tlu.io.mpc_debug_halt_ack @[dec.scala 285:29]
+    io.mpc_debug_run_ack <= tlu.io.mpc_debug_run_ack @[dec.scala 286:29]
+    io.debug_brkpt_status <= tlu.io.debug_brkpt_status @[dec.scala 287:29]
+    io.dec_tlu_i0_kill_writeb_r <= tlu.io.dec_tlu_i0_kill_writeb_r @[dec.scala 288:34]
+    io.dec_tlu_perfcnt0 <= tlu.io.dec_tlu_perfcnt0 @[dec.scala 289:29]
+    io.dec_tlu_perfcnt1 <= tlu.io.dec_tlu_perfcnt1 @[dec.scala 290:29]
+    io.dec_tlu_perfcnt2 <= tlu.io.dec_tlu_perfcnt2 @[dec.scala 291:29]
+    io.dec_tlu_perfcnt3 <= tlu.io.dec_tlu_perfcnt3 @[dec.scala 292:29]
+    dec_tlu_i0_exc_valid_wb1 <= tlu.io.dec_tlu_i0_exc_valid_wb1 @[dec.scala 293:32]
+    dec_tlu_i0_valid_wb1 <= tlu.io.dec_tlu_i0_valid_wb1 @[dec.scala 294:32]
+    dec_tlu_int_valid_wb1 <= tlu.io.dec_tlu_int_valid_wb1 @[dec.scala 295:32]
+    dec_tlu_exc_cause_wb1 <= tlu.io.dec_tlu_exc_cause_wb1 @[dec.scala 296:32]
+    dec_tlu_mtval_wb1 <= tlu.io.dec_tlu_mtval_wb1 @[dec.scala 297:32]
+    io.dec_tlu_misc_clk_override <= tlu.io.dec_tlu_misc_clk_override @[dec.scala 298:35]
+    io.dec_tlu_ifu_clk_override <= tlu.io.dec_tlu_ifu_clk_override @[dec.scala 299:36]
+    io.dec_tlu_lsu_clk_override <= tlu.io.dec_tlu_lsu_clk_override @[dec.scala 300:36]
+    io.dec_tlu_bus_clk_override <= tlu.io.dec_tlu_bus_clk_override @[dec.scala 301:36]
+    io.dec_tlu_pic_clk_override <= tlu.io.dec_tlu_pic_clk_override @[dec.scala 302:36]
+    io.dec_tlu_dccm_clk_override <= tlu.io.dec_tlu_dccm_clk_override @[dec.scala 303:36]
+    io.dec_tlu_icm_clk_override <= tlu.io.dec_tlu_icm_clk_override @[dec.scala 304:36]
+    io.dec_tlu_picio_clk_override <= tlu.io.dec_tlu_picio_clk_override @[dec.scala 305:36]
+    io.dec_tlu_core_empty <= tlu.io.dec_tlu_core_empty @[dec.scala 306:36]
+    io.dec_csr_rddata_d <= tlu.io.dec_csr_rddata_d @[dec.scala 307:36]
+    io.dec_tlu_flush_lower_wb <= tlu.io.dec_tlu_flush_lower_wb @[dec.scala 308:36]
+    io.trace_rv_trace_pkt.rv_i_insn_ip <= decode.io.dec_i0_inst_wb @[dec.scala 312:38]
     node _T = cat(decode.io.dec_i0_pc_wb, UInt<1>("h00")) @[Cat.scala 29:58]
-    io.trace_rv_trace_pkt.rv_i_address_ip <= _T @[dec.scala 311:41]
-    node _T_1 = or(tlu.io.dec_tlu_int_valid_wb1, tlu.io.dec_tlu_i0_valid_wb1) @[dec.scala 312:71]
-    node _T_2 = or(_T_1, tlu.io.dec_tlu_i0_exc_valid_wb1) @[dec.scala 312:101]
-    io.trace_rv_trace_pkt.rv_i_valid_ip <= _T_2 @[dec.scala 312:39]
-    node _T_3 = or(tlu.io.dec_tlu_int_valid_wb1, tlu.io.dec_tlu_i0_exc_valid_wb1) @[dec.scala 313:75]
-    io.trace_rv_trace_pkt.rv_i_exception_ip <= _T_3 @[dec.scala 313:43]
-    node _T_4 = bits(tlu.io.dec_tlu_exc_cause_wb1, 4, 0) @[dec.scala 314:71]
-    io.trace_rv_trace_pkt.rv_i_ecause_ip <= _T_4 @[dec.scala 314:40]
-    io.trace_rv_trace_pkt.rv_i_interrupt_ip <= tlu.io.dec_tlu_int_valid_wb1 @[dec.scala 315:43]
-    io.trace_rv_trace_pkt.rv_i_tval_ip <= tlu.io.dec_tlu_mtval_wb1 @[dec.scala 316:38]
-    io.dec_dbg_rddata <= decode.io.dec_i0_wdata_r @[dec.scala 320:21]
+    io.trace_rv_trace_pkt.rv_i_address_ip <= _T @[dec.scala 313:41]
+    node _T_1 = or(tlu.io.dec_tlu_int_valid_wb1, tlu.io.dec_tlu_i0_valid_wb1) @[dec.scala 314:71]
+    node _T_2 = or(_T_1, tlu.io.dec_tlu_i0_exc_valid_wb1) @[dec.scala 314:101]
+    io.trace_rv_trace_pkt.rv_i_valid_ip <= _T_2 @[dec.scala 314:39]
+    node _T_3 = or(tlu.io.dec_tlu_int_valid_wb1, tlu.io.dec_tlu_i0_exc_valid_wb1) @[dec.scala 315:75]
+    io.trace_rv_trace_pkt.rv_i_exception_ip <= _T_3 @[dec.scala 315:43]
+    node _T_4 = bits(tlu.io.dec_tlu_exc_cause_wb1, 4, 0) @[dec.scala 316:71]
+    io.trace_rv_trace_pkt.rv_i_ecause_ip <= _T_4 @[dec.scala 316:40]
+    io.trace_rv_trace_pkt.rv_i_interrupt_ip <= tlu.io.dec_tlu_int_valid_wb1 @[dec.scala 317:43]
+    io.trace_rv_trace_pkt.rv_i_tval_ip <= tlu.io.dec_tlu_mtval_wb1 @[dec.scala 318:38]
+    io.dec_dbg_rddata <= decode.io.dec_i0_wdata_r @[dec.scala 322:21]
     
diff --git a/dec.v b/dec.v
index 2cd946dc..c8ac23c8 100644
--- a/dec.v
+++ b/dec.v
@@ -1715,7 +1715,6 @@ module dec_decode_ctl(
   input         io_dctl_busbuff_lsu_nonblock_load_data_error,
   input  [1:0]  io_dctl_busbuff_lsu_nonblock_load_data_tag,
   input         io_dctl_dma_dma_dccm_stall_any,
-  output        io_dec_aln_dec_i0_decode_d,
   input  [15:0] io_dec_aln_ifu_i0_cinst,
   input  [31:0] io_dbg_dctl_dbg_cmd_wrdata,
   input         io_dec_tlu_trace_disable,
@@ -1816,7 +1815,8 @@ module dec_decode_ctl(
   output [4:0]  io_dec_nonblock_load_waddr,
   output        io_dec_pause_state,
   output        io_dec_pause_state_cg,
-  output        io_dec_div_active
+  output        io_dec_div_active,
+  output        io_dec_i0_decode_d
 );
 `ifdef RANDOMIZE_REG_INIT
   reg [31:0] _RAND_0;
@@ -1910,102 +1910,102 @@ module dec_decode_ctl(
   reg [31:0] _RAND_88;
   reg [31:0] _RAND_89;
 `endif // RANDOMIZE_REG_INIT
-  wire [31:0] i0_dec_io_ins; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_clz; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_ctz; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_pcnt; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_sext_b; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_sext_h; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_slo; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_sro; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_min; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_max; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_pack; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_packu; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_packh; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_rol; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_ror; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_grev; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_gorc; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_zbb; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_sbset; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_sbclr; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_sbinv; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_sbext; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_zbs; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_bext; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_bdep; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_zbe; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_clmul; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_clmulh; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_clmulr; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_zbc; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_shfl; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_unshfl; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_zbp; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_crc32_b; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_crc32_h; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_crc32_w; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_crc32c_b; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_crc32c_h; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_crc32c_w; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_zbr; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_bfp; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_zbf; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_sh1add; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_sh2add; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_sh3add; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_zba; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_alu; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_rs1; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_rs2; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_imm12; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_rd; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_shimm5; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_imm20; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_pc; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_load; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_store; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_lsu; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_add; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_sub; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_land; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_lor; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_lxor; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_sll; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_sra; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_srl; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_slt; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_unsign; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_condbr; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_beq; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_bne; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_bge; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_blt; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_jal; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_by; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_half; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_word; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_csr_read; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_csr_clr; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_csr_set; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_csr_write; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_csr_imm; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_presync; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_postsync; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_ebreak; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_ecall; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_mret; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_mul; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_rs1_sign; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_rs2_sign; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_low; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_div; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_rem; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_fence; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_fence_i; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_pm_alu; // @[dec_decode_ctl.scala 438:22]
-  wire  i0_dec_io_out_legal; // @[dec_decode_ctl.scala 438:22]
+  wire [31:0] i0_dec_io_ins; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_clz; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_ctz; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_pcnt; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_sext_b; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_sext_h; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_slo; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_sro; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_min; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_max; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_pack; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_packu; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_packh; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_rol; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_ror; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_grev; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_gorc; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_zbb; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_sbset; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_sbclr; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_sbinv; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_sbext; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_zbs; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_bext; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_bdep; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_zbe; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_clmul; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_clmulh; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_clmulr; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_zbc; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_shfl; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_unshfl; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_zbp; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_crc32_b; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_crc32_h; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_crc32_w; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_crc32c_b; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_crc32c_h; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_crc32c_w; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_zbr; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_bfp; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_zbf; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_sh1add; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_sh2add; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_sh3add; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_zba; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_alu; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_rs1; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_rs2; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_imm12; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_rd; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_shimm5; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_imm20; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_pc; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_load; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_store; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_lsu; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_add; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_sub; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_land; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_lor; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_lxor; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_sll; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_sra; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_srl; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_slt; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_unsign; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_condbr; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_beq; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_bne; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_bge; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_blt; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_jal; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_by; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_half; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_word; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_csr_read; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_csr_clr; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_csr_set; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_csr_write; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_csr_imm; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_presync; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_postsync; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_ebreak; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_ecall; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_mret; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_mul; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_rs1_sign; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_rs2_sign; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_low; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_div; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_rem; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_fence; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_fence_i; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_pm_alu; // @[dec_decode_ctl.scala 440:22]
+  wire  i0_dec_io_out_legal; // @[dec_decode_ctl.scala 440:22]
   wire  rvclkhdr_io_clk; // @[lib.scala 404:23]
   wire  rvclkhdr_io_en; // @[lib.scala 404:23]
   wire  rvclkhdr_1_io_clk; // @[lib.scala 404:23]
@@ -2029,31 +2029,31 @@ module dec_decode_ctl(
   wire  rvclkhdr_10_io_clk; // @[lib.scala 404:23]
   wire  rvclkhdr_10_io_en; // @[lib.scala 404:23]
   reg  leak1_i1_stall; // @[Reg.scala 27:20]
-  wire  _T_367 = ~io_dec_tlu_flush_lower_r; // @[dec_decode_ctl.scala 445:73]
-  wire  _T_368 = leak1_i1_stall & _T_367; // @[dec_decode_ctl.scala 445:71]
-  wire  leak1_i1_stall_in = io_dec_tlu_flush_leak_one_r | _T_368; // @[dec_decode_ctl.scala 445:53]
+  wire  _T_367 = ~io_dec_tlu_flush_lower_r; // @[dec_decode_ctl.scala 447:73]
+  wire  _T_368 = leak1_i1_stall & _T_367; // @[dec_decode_ctl.scala 447:71]
+  wire  leak1_i1_stall_in = io_dec_tlu_flush_leak_one_r | _T_368; // @[dec_decode_ctl.scala 447:53]
   wire  _T_2 = leak1_i1_stall_in ^ leak1_i1_stall; // @[lib.scala 448:21]
   wire  _T_3 = |_T_2; // @[lib.scala 448:29]
-  wire  _T_370 = io_dec_aln_dec_i0_decode_d & leak1_i1_stall; // @[dec_decode_ctl.scala 447:53]
+  wire  _T_370 = io_dec_i0_decode_d & leak1_i1_stall; // @[dec_decode_ctl.scala 449:45]
   reg  leak1_i0_stall; // @[Reg.scala 27:20]
-  wire  _T_372 = leak1_i0_stall & _T_367; // @[dec_decode_ctl.scala 447:89]
-  wire  leak1_i0_stall_in = _T_370 | _T_372; // @[dec_decode_ctl.scala 447:71]
+  wire  _T_372 = leak1_i0_stall & _T_367; // @[dec_decode_ctl.scala 449:81]
+  wire  leak1_i0_stall_in = _T_370 | _T_372; // @[dec_decode_ctl.scala 449:63]
   wire  _T_6 = leak1_i0_stall_in ^ leak1_i0_stall; // @[lib.scala 448:21]
   wire  _T_7 = |_T_6; // @[lib.scala 448:29]
   reg  _T_12; // @[Reg.scala 27:20]
   wire  _T_10 = io_dec_tlu_flush_extint ^ _T_12; // @[lib.scala 470:21]
   wire  _T_11 = |_T_10; // @[lib.scala 470:29]
   reg  pause_stall; // @[Reg.scala 27:20]
-  wire  _T_514 = io_dec_tlu_wr_pause_r | pause_stall; // @[dec_decode_ctl.scala 559:44]
-  wire  _T_507 = ~io_dec_tlu_flush_pause_r; // @[dec_decode_ctl.scala 558:49]
-  wire  _T_508 = io_dec_tlu_flush_lower_r & _T_507; // @[dec_decode_ctl.scala 558:47]
+  wire  _T_514 = io_dec_tlu_wr_pause_r | pause_stall; // @[dec_decode_ctl.scala 561:44]
+  wire  _T_507 = ~io_dec_tlu_flush_pause_r; // @[dec_decode_ctl.scala 560:49]
+  wire  _T_508 = io_dec_tlu_flush_lower_r & _T_507; // @[dec_decode_ctl.scala 560:47]
   reg [31:0] write_csr_data; // @[Reg.scala 27:20]
   wire [31:0] _T_511 = {31'h0,write_csr_data[0]}; // @[Cat.scala 29:58]
-  wire  _T_512 = write_csr_data == _T_511; // @[dec_decode_ctl.scala 558:109]
-  wire  _T_513 = pause_stall & _T_512; // @[dec_decode_ctl.scala 558:91]
-  wire  clear_pause = _T_508 | _T_513; // @[dec_decode_ctl.scala 558:76]
-  wire  _T_515 = ~clear_pause; // @[dec_decode_ctl.scala 559:61]
-  wire  pause_state_in = _T_514 & _T_515; // @[dec_decode_ctl.scala 559:59]
+  wire  _T_512 = write_csr_data == _T_511; // @[dec_decode_ctl.scala 560:109]
+  wire  _T_513 = pause_stall & _T_512; // @[dec_decode_ctl.scala 560:91]
+  wire  clear_pause = _T_508 | _T_513; // @[dec_decode_ctl.scala 560:76]
+  wire  _T_515 = ~clear_pause; // @[dec_decode_ctl.scala 561:61]
+  wire  pause_state_in = _T_514 & _T_515; // @[dec_decode_ctl.scala 561:59]
   wire  _T_14 = pause_state_in ^ pause_stall; // @[lib.scala 470:21]
   wire  _T_15 = |_T_14; // @[lib.scala 470:29]
   reg  tlu_wr_pause_r1; // @[Reg.scala 27:20]
@@ -2062,96 +2062,96 @@ module dec_decode_ctl(
   reg  tlu_wr_pause_r2; // @[Reg.scala 27:20]
   wire  _T_22 = tlu_wr_pause_r1 ^ tlu_wr_pause_r2; // @[lib.scala 448:21]
   wire  _T_23 = |_T_22; // @[lib.scala 448:29]
-  wire  _T_50 = ~leak1_i1_stall; // @[dec_decode_ctl.scala 222:82]
-  wire  _T_51 = io_dec_i0_brp_valid & _T_50; // @[dec_decode_ctl.scala 222:80]
-  wire  i0_icaf_d = io_dec_i0_icaf_d | io_dec_i0_dbecc_d; // @[dec_decode_ctl.scala 220:43]
-  wire  _T_52 = ~i0_icaf_d; // @[dec_decode_ctl.scala 222:96]
-  wire  i0_brp_valid = _T_51 & _T_52; // @[dec_decode_ctl.scala 222:94]
-  wire  i0_dp_raw_condbr = i0_dec_io_out_condbr; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_raw_jal = i0_dec_io_out_jal; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
+  wire  _T_50 = ~leak1_i1_stall; // @[dec_decode_ctl.scala 224:82]
+  wire  _T_51 = io_dec_i0_brp_valid & _T_50; // @[dec_decode_ctl.scala 224:80]
+  wire  i0_icaf_d = io_dec_i0_icaf_d | io_dec_i0_dbecc_d; // @[dec_decode_ctl.scala 222:43]
+  wire  _T_52 = ~i0_icaf_d; // @[dec_decode_ctl.scala 224:96]
+  wire  i0_brp_valid = _T_51 & _T_52; // @[dec_decode_ctl.scala 224:94]
+  wire  i0_dp_raw_condbr = i0_dec_io_out_condbr; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_raw_jal = i0_dec_io_out_jal; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
   wire [19:0] i0_pcall_imm = {io_dec_i0_instr_d[31],io_dec_i0_instr_d[19:12],io_dec_i0_instr_d[20],io_dec_i0_instr_d[30:21]}; // @[Cat.scala 29:58]
-  wire  _T_383 = i0_pcall_imm[19:12] == 8'hff; // @[dec_decode_ctl.scala 452:79]
-  wire  _T_385 = i0_pcall_imm[19:12] == 8'h0; // @[dec_decode_ctl.scala 452:112]
-  wire  i0_pcall_12b_offset = i0_pcall_imm[11] ? _T_383 : _T_385; // @[dec_decode_ctl.scala 452:33]
-  wire  i0_dp_raw_imm20 = i0_dec_io_out_imm20; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  _T_386 = i0_pcall_12b_offset & i0_dp_raw_imm20; // @[dec_decode_ctl.scala 453:47]
-  wire [4:0] i0r_rd = io_dec_i0_instr_d[11:7]; // @[dec_decode_ctl.scala 678:16]
-  wire  _T_387 = i0r_rd == 5'h1; // @[dec_decode_ctl.scala 453:76]
-  wire  _T_388 = i0r_rd == 5'h5; // @[dec_decode_ctl.scala 453:98]
-  wire  _T_389 = _T_387 | _T_388; // @[dec_decode_ctl.scala 453:89]
-  wire  i0_pcall_case = _T_386 & _T_389; // @[dec_decode_ctl.scala 453:65]
-  wire  i0_pcall_raw = i0_dp_raw_jal & i0_pcall_case; // @[dec_decode_ctl.scala 455:38]
-  wire  _T_55 = i0_dp_raw_condbr | i0_pcall_raw; // @[dec_decode_ctl.scala 233:94]
-  wire  _T_394 = ~_T_389; // @[dec_decode_ctl.scala 454:67]
-  wire  i0_pja_case = _T_386 & _T_394; // @[dec_decode_ctl.scala 454:65]
-  wire  i0_pja_raw = i0_dp_raw_jal & i0_pja_case; // @[dec_decode_ctl.scala 457:38]
-  wire  _T_56 = _T_55 | i0_pja_raw; // @[dec_decode_ctl.scala 233:109]
-  wire  i0_dp_raw_imm12 = i0_dec_io_out_imm12; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  _T_410 = i0_dp_raw_jal & i0_dp_raw_imm12; // @[dec_decode_ctl.scala 461:37]
-  wire  _T_411 = i0r_rd == 5'h0; // @[dec_decode_ctl.scala 461:65]
-  wire  _T_412 = _T_410 & _T_411; // @[dec_decode_ctl.scala 461:55]
-  wire [4:0] i0r_rs1 = io_dec_i0_instr_d[19:15]; // @[dec_decode_ctl.scala 676:16]
-  wire  _T_413 = i0r_rs1 == 5'h1; // @[dec_decode_ctl.scala 461:89]
-  wire  _T_414 = i0r_rs1 == 5'h5; // @[dec_decode_ctl.scala 461:111]
-  wire  _T_415 = _T_413 | _T_414; // @[dec_decode_ctl.scala 461:101]
-  wire  i0_pret_case = _T_412 & _T_415; // @[dec_decode_ctl.scala 461:79]
-  wire  i0_pret_raw = i0_dp_raw_jal & i0_pret_case; // @[dec_decode_ctl.scala 462:32]
-  wire  _T_57 = _T_56 | i0_pret_raw; // @[dec_decode_ctl.scala 233:122]
-  wire  _T_58 = ~_T_57; // @[dec_decode_ctl.scala 233:75]
-  wire  _T_59 = i0_brp_valid & _T_58; // @[dec_decode_ctl.scala 233:73]
-  wire  _T_68 = io_dec_i0_brp_bits_br_error | _T_59; // @[dec_decode_ctl.scala 238:89]
-  wire  _T_61 = i0_brp_valid & io_dec_i0_brp_bits_hist[1]; // @[dec_decode_ctl.scala 236:74]
-  wire  _T_399 = i0_pcall_raw | i0_pja_raw; // @[dec_decode_ctl.scala 459:41]
+  wire  _T_383 = i0_pcall_imm[19:12] == 8'hff; // @[dec_decode_ctl.scala 454:79]
+  wire  _T_385 = i0_pcall_imm[19:12] == 8'h0; // @[dec_decode_ctl.scala 454:112]
+  wire  i0_pcall_12b_offset = i0_pcall_imm[11] ? _T_383 : _T_385; // @[dec_decode_ctl.scala 454:33]
+  wire  i0_dp_raw_imm20 = i0_dec_io_out_imm20; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  _T_386 = i0_pcall_12b_offset & i0_dp_raw_imm20; // @[dec_decode_ctl.scala 455:47]
+  wire [4:0] i0r_rd = io_dec_i0_instr_d[11:7]; // @[dec_decode_ctl.scala 680:16]
+  wire  _T_387 = i0r_rd == 5'h1; // @[dec_decode_ctl.scala 455:76]
+  wire  _T_388 = i0r_rd == 5'h5; // @[dec_decode_ctl.scala 455:98]
+  wire  _T_389 = _T_387 | _T_388; // @[dec_decode_ctl.scala 455:89]
+  wire  i0_pcall_case = _T_386 & _T_389; // @[dec_decode_ctl.scala 455:65]
+  wire  i0_pcall_raw = i0_dp_raw_jal & i0_pcall_case; // @[dec_decode_ctl.scala 457:38]
+  wire  _T_55 = i0_dp_raw_condbr | i0_pcall_raw; // @[dec_decode_ctl.scala 235:94]
+  wire  _T_394 = ~_T_389; // @[dec_decode_ctl.scala 456:67]
+  wire  i0_pja_case = _T_386 & _T_394; // @[dec_decode_ctl.scala 456:65]
+  wire  i0_pja_raw = i0_dp_raw_jal & i0_pja_case; // @[dec_decode_ctl.scala 459:38]
+  wire  _T_56 = _T_55 | i0_pja_raw; // @[dec_decode_ctl.scala 235:109]
+  wire  i0_dp_raw_imm12 = i0_dec_io_out_imm12; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  _T_410 = i0_dp_raw_jal & i0_dp_raw_imm12; // @[dec_decode_ctl.scala 463:37]
+  wire  _T_411 = i0r_rd == 5'h0; // @[dec_decode_ctl.scala 463:65]
+  wire  _T_412 = _T_410 & _T_411; // @[dec_decode_ctl.scala 463:55]
+  wire [4:0] i0r_rs1 = io_dec_i0_instr_d[19:15]; // @[dec_decode_ctl.scala 678:16]
+  wire  _T_413 = i0r_rs1 == 5'h1; // @[dec_decode_ctl.scala 463:89]
+  wire  _T_414 = i0r_rs1 == 5'h5; // @[dec_decode_ctl.scala 463:111]
+  wire  _T_415 = _T_413 | _T_414; // @[dec_decode_ctl.scala 463:101]
+  wire  i0_pret_case = _T_412 & _T_415; // @[dec_decode_ctl.scala 463:79]
+  wire  i0_pret_raw = i0_dp_raw_jal & i0_pret_case; // @[dec_decode_ctl.scala 464:32]
+  wire  _T_57 = _T_56 | i0_pret_raw; // @[dec_decode_ctl.scala 235:122]
+  wire  _T_58 = ~_T_57; // @[dec_decode_ctl.scala 235:75]
+  wire  _T_59 = i0_brp_valid & _T_58; // @[dec_decode_ctl.scala 235:73]
+  wire  _T_68 = io_dec_i0_brp_bits_br_error | _T_59; // @[dec_decode_ctl.scala 240:89]
+  wire  _T_61 = i0_brp_valid & io_dec_i0_brp_bits_hist[1]; // @[dec_decode_ctl.scala 238:74]
+  wire  _T_399 = i0_pcall_raw | i0_pja_raw; // @[dec_decode_ctl.scala 461:41]
   wire [11:0] _T_408 = {io_dec_i0_instr_d[31],io_dec_i0_instr_d[7],io_dec_i0_instr_d[30:25],io_dec_i0_instr_d[11:8]}; // @[Cat.scala 29:58]
-  wire [11:0] i0_br_offset = _T_399 ? i0_pcall_imm[11:0] : _T_408; // @[dec_decode_ctl.scala 459:26]
-  wire  _T_62 = io_dec_i0_brp_bits_toffset != i0_br_offset; // @[dec_decode_ctl.scala 236:133]
-  wire  _T_63 = _T_61 & _T_62; // @[dec_decode_ctl.scala 236:103]
-  wire  _T_64 = ~i0_pret_raw; // @[dec_decode_ctl.scala 236:153]
-  wire  _T_65 = _T_63 & _T_64; // @[dec_decode_ctl.scala 236:151]
-  wire  _T_69 = _T_68 | _T_65; // @[dec_decode_ctl.scala 238:106]
-  wire  _T_66 = io_dec_i0_brp_bits_ret ^ i0_pret_raw; // @[dec_decode_ctl.scala 237:100]
-  wire  _T_67 = i0_brp_valid & _T_66; // @[dec_decode_ctl.scala 237:74]
-  wire  _T_70 = _T_69 | _T_67; // @[dec_decode_ctl.scala 238:128]
-  wire  _T_77 = _T_70 | io_dec_i0_brp_bits_br_start_error; // @[dec_decode_ctl.scala 243:74]
-  wire  i0_br_error_all = _T_77 & _T_50; // @[dec_decode_ctl.scala 243:111]
-  wire  _T_80 = i0_br_error_all | i0_icaf_d; // @[dec_decode_ctl.scala 280:25]
-  wire  i0_dp_raw_legal = i0_dec_io_out_legal; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_legal = _T_80 | i0_dp_raw_legal; // @[dec_decode_ctl.scala 280:50]
-  wire  i0_dp_raw_csr_read = i0_dec_io_out_csr_read; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_csr_read = _T_80 ? 1'h0 : i0_dp_raw_csr_read; // @[dec_decode_ctl.scala 280:50]
-  wire  i0_dp_raw_csr_write = i0_dec_io_out_csr_write; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_csr_write = _T_80 ? 1'h0 : i0_dp_raw_csr_write; // @[dec_decode_ctl.scala 280:50]
-  wire  _T_429 = ~io_dec_debug_fence_d; // @[dec_decode_ctl.scala 519:42]
-  wire  i0_csr_write = i0_dp_csr_write & _T_429; // @[dec_decode_ctl.scala 519:40]
-  wire  any_csr_d = i0_dp_csr_read | i0_csr_write; // @[dec_decode_ctl.scala 527:34]
-  wire  _T_544 = ~any_csr_d; // @[dec_decode_ctl.scala 590:40]
-  wire  _T_545 = _T_544 | io_dec_csr_legal_d; // @[dec_decode_ctl.scala 590:51]
-  wire  i0_legal = i0_dp_legal & _T_545; // @[dec_decode_ctl.scala 590:37]
-  wire  _T_563 = ~i0_legal; // @[dec_decode_ctl.scala 594:57]
-  wire  shift_illegal = io_dec_aln_dec_i0_decode_d & _T_563; // @[dec_decode_ctl.scala 594:55]
+  wire [11:0] i0_br_offset = _T_399 ? i0_pcall_imm[11:0] : _T_408; // @[dec_decode_ctl.scala 461:26]
+  wire  _T_62 = io_dec_i0_brp_bits_toffset != i0_br_offset; // @[dec_decode_ctl.scala 238:133]
+  wire  _T_63 = _T_61 & _T_62; // @[dec_decode_ctl.scala 238:103]
+  wire  _T_64 = ~i0_pret_raw; // @[dec_decode_ctl.scala 238:153]
+  wire  _T_65 = _T_63 & _T_64; // @[dec_decode_ctl.scala 238:151]
+  wire  _T_69 = _T_68 | _T_65; // @[dec_decode_ctl.scala 240:106]
+  wire  _T_66 = io_dec_i0_brp_bits_ret ^ i0_pret_raw; // @[dec_decode_ctl.scala 239:100]
+  wire  _T_67 = i0_brp_valid & _T_66; // @[dec_decode_ctl.scala 239:74]
+  wire  _T_70 = _T_69 | _T_67; // @[dec_decode_ctl.scala 240:128]
+  wire  _T_77 = _T_70 | io_dec_i0_brp_bits_br_start_error; // @[dec_decode_ctl.scala 245:74]
+  wire  i0_br_error_all = _T_77 & _T_50; // @[dec_decode_ctl.scala 245:111]
+  wire  _T_80 = i0_br_error_all | i0_icaf_d; // @[dec_decode_ctl.scala 282:25]
+  wire  i0_dp_raw_legal = i0_dec_io_out_legal; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_legal = _T_80 | i0_dp_raw_legal; // @[dec_decode_ctl.scala 282:50]
+  wire  i0_dp_raw_csr_read = i0_dec_io_out_csr_read; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_csr_read = _T_80 ? 1'h0 : i0_dp_raw_csr_read; // @[dec_decode_ctl.scala 282:50]
+  wire  i0_dp_raw_csr_write = i0_dec_io_out_csr_write; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_csr_write = _T_80 ? 1'h0 : i0_dp_raw_csr_write; // @[dec_decode_ctl.scala 282:50]
+  wire  _T_429 = ~io_dec_debug_fence_d; // @[dec_decode_ctl.scala 521:42]
+  wire  i0_csr_write = i0_dp_csr_write & _T_429; // @[dec_decode_ctl.scala 521:40]
+  wire  any_csr_d = i0_dp_csr_read | i0_csr_write; // @[dec_decode_ctl.scala 529:34]
+  wire  _T_544 = ~any_csr_d; // @[dec_decode_ctl.scala 592:40]
+  wire  _T_545 = _T_544 | io_dec_csr_legal_d; // @[dec_decode_ctl.scala 592:51]
+  wire  i0_legal = i0_dp_legal & _T_545; // @[dec_decode_ctl.scala 592:37]
+  wire  _T_563 = ~i0_legal; // @[dec_decode_ctl.scala 596:49]
+  wire  shift_illegal = io_dec_i0_decode_d & _T_563; // @[dec_decode_ctl.scala 596:47]
   reg  illegal_lockout; // @[Reg.scala 27:20]
-  wire  _T_566 = shift_illegal | illegal_lockout; // @[dec_decode_ctl.scala 597:40]
+  wire  _T_566 = shift_illegal | illegal_lockout; // @[dec_decode_ctl.scala 599:40]
   reg  flush_final_r; // @[Reg.scala 27:20]
-  wire  _T_567 = ~flush_final_r; // @[dec_decode_ctl.scala 597:61]
-  wire  illegal_lockout_in = _T_566 & _T_567; // @[dec_decode_ctl.scala 597:59]
+  wire  _T_567 = ~flush_final_r; // @[dec_decode_ctl.scala 599:61]
+  wire  illegal_lockout_in = _T_566 & _T_567; // @[dec_decode_ctl.scala 599:59]
   wire  _T_26 = illegal_lockout_in ^ illegal_lockout; // @[lib.scala 448:21]
   wire  _T_27 = |_T_26; // @[lib.scala 448:29]
-  wire  i0_dp_raw_postsync = i0_dec_io_out_postsync; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_postsync = _T_80 | i0_dp_raw_postsync; // @[dec_decode_ctl.scala 280:50]
-  wire  _T_539 = i0_dp_postsync | io_dec_tlu_postsync_d; // @[dec_decode_ctl.scala 586:36]
-  wire  debug_fence_i = io_dec_debug_fence_d & io_dbg_dctl_dbg_cmd_wrdata[0]; // @[dec_decode_ctl.scala 578:48]
-  wire  _T_540 = _T_539 | debug_fence_i; // @[dec_decode_ctl.scala 586:60]
-  wire  _T_433 = ~i0_dp_csr_read; // @[dec_decode_ctl.scala 524:41]
-  wire  i0_csr_write_only_d = i0_csr_write & _T_433; // @[dec_decode_ctl.scala 524:39]
-  wire  _T_542 = io_dec_i0_instr_d[31:20] == 12'h7c2; // @[dec_decode_ctl.scala 586:112]
-  wire  _T_543 = i0_csr_write_only_d & _T_542; // @[dec_decode_ctl.scala 586:99]
-  wire  i0_postsync = _T_540 | _T_543; // @[dec_decode_ctl.scala 586:76]
-  wire  _T_605 = i0_postsync | _T_563; // @[dec_decode_ctl.scala 628:62]
-  wire  _T_606 = io_dec_aln_dec_i0_decode_d & _T_605; // @[dec_decode_ctl.scala 628:47]
+  wire  i0_dp_raw_postsync = i0_dec_io_out_postsync; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_postsync = _T_80 | i0_dp_raw_postsync; // @[dec_decode_ctl.scala 282:50]
+  wire  _T_539 = i0_dp_postsync | io_dec_tlu_postsync_d; // @[dec_decode_ctl.scala 588:36]
+  wire  debug_fence_i = io_dec_debug_fence_d & io_dbg_dctl_dbg_cmd_wrdata[0]; // @[dec_decode_ctl.scala 580:48]
+  wire  _T_540 = _T_539 | debug_fence_i; // @[dec_decode_ctl.scala 588:60]
+  wire  _T_433 = ~i0_dp_csr_read; // @[dec_decode_ctl.scala 526:41]
+  wire  i0_csr_write_only_d = i0_csr_write & _T_433; // @[dec_decode_ctl.scala 526:39]
+  wire  _T_542 = io_dec_i0_instr_d[31:20] == 12'h7c2; // @[dec_decode_ctl.scala 588:112]
+  wire  _T_543 = i0_csr_write_only_d & _T_542; // @[dec_decode_ctl.scala 588:99]
+  wire  i0_postsync = _T_540 | _T_543; // @[dec_decode_ctl.scala 588:76]
+  wire  _T_605 = i0_postsync | _T_563; // @[dec_decode_ctl.scala 630:54]
+  wire  _T_606 = io_dec_i0_decode_d & _T_605; // @[dec_decode_ctl.scala 630:39]
   reg  postsync_stall; // @[Reg.scala 27:20]
   reg  x_d_valid; // @[Reg.scala 27:20]
-  wire  _T_607 = postsync_stall & x_d_valid; // @[dec_decode_ctl.scala 628:96]
-  wire  ps_stall_in = _T_606 | _T_607; // @[dec_decode_ctl.scala 628:77]
+  wire  _T_607 = postsync_stall & x_d_valid; // @[dec_decode_ctl.scala 630:88]
+  wire  ps_stall_in = _T_606 | _T_607; // @[dec_decode_ctl.scala 630:69]
   wire  _T_30 = ps_stall_in ^ postsync_stall; // @[lib.scala 448:21]
   wire  _T_31 = |_T_30; // @[lib.scala 448:29]
   reg [3:0] lsu_trigger_match_r; // @[Reg.scala 27:20]
@@ -2160,42 +2160,42 @@ module dec_decode_ctl(
   reg  lsu_pmu_misaligned_r; // @[Reg.scala 27:20]
   wire  _T_36 = io_lsu_pmu_misaligned_m ^ lsu_pmu_misaligned_r; // @[lib.scala 470:21]
   wire  _T_37 = |_T_36; // @[lib.scala 470:29]
-  wire  i0_legal_decode_d = io_dec_aln_dec_i0_decode_d & i0_legal; // @[dec_decode_ctl.scala 756:54]
-  wire  i0_dp_raw_div = i0_dec_io_out_div; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_div = _T_80 ? 1'h0 : i0_dp_raw_div; // @[dec_decode_ctl.scala 280:50]
-  wire  i0_div_decode_d = i0_legal_decode_d & i0_dp_div; // @[dec_decode_ctl.scala 843:55]
-  wire  _T_934 = ~io_exu_div_wren; // @[dec_decode_ctl.scala 845:59]
-  wire  _T_935 = io_dec_div_active & _T_934; // @[dec_decode_ctl.scala 845:57]
+  wire  i0_legal_decode_d = io_dec_i0_decode_d & i0_legal; // @[dec_decode_ctl.scala 758:46]
+  wire  i0_dp_raw_div = i0_dec_io_out_div; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_div = _T_80 ? 1'h0 : i0_dp_raw_div; // @[dec_decode_ctl.scala 282:50]
+  wire  i0_div_decode_d = i0_legal_decode_d & i0_dp_div; // @[dec_decode_ctl.scala 845:55]
+  wire  _T_934 = ~io_exu_div_wren; // @[dec_decode_ctl.scala 847:59]
+  wire  _T_935 = io_dec_div_active & _T_934; // @[dec_decode_ctl.scala 847:57]
   reg  x_d_bits_i0div; // @[Reg.scala 27:20]
-  wire  _T_918 = x_d_bits_i0div & x_d_valid; // @[dec_decode_ctl.scala 833:48]
+  wire  _T_918 = x_d_bits_i0div & x_d_valid; // @[dec_decode_ctl.scala 835:48]
   reg [4:0] x_d_bits_i0rd; // @[Reg.scala 27:20]
-  wire  _T_919 = x_d_bits_i0rd == 5'h0; // @[dec_decode_ctl.scala 833:77]
-  wire  _T_920 = _T_918 & _T_919; // @[dec_decode_ctl.scala 833:60]
-  wire  _T_922 = _T_918 & io_dec_tlu_flush_lower_r; // @[dec_decode_ctl.scala 834:33]
-  wire  _T_923 = _T_920 | _T_922; // @[dec_decode_ctl.scala 833:94]
+  wire  _T_919 = x_d_bits_i0rd == 5'h0; // @[dec_decode_ctl.scala 835:77]
+  wire  _T_920 = _T_918 & _T_919; // @[dec_decode_ctl.scala 835:60]
+  wire  _T_922 = _T_918 & io_dec_tlu_flush_lower_r; // @[dec_decode_ctl.scala 836:33]
+  wire  _T_923 = _T_920 | _T_922; // @[dec_decode_ctl.scala 835:94]
   reg  r_d_bits_i0div; // @[Reg.scala 27:20]
   reg  r_d_valid; // @[Reg.scala 27:20]
-  wire  _T_924 = r_d_bits_i0div & r_d_valid; // @[dec_decode_ctl.scala 835:21]
-  wire  _T_925 = _T_924 & io_dec_tlu_flush_lower_r; // @[dec_decode_ctl.scala 835:33]
-  wire  _T_926 = _T_925 & io_dec_tlu_i0_kill_writeb_r; // @[dec_decode_ctl.scala 835:60]
-  wire  div_flush = _T_923 | _T_926; // @[dec_decode_ctl.scala 834:62]
-  wire  _T_927 = io_dec_div_active & div_flush; // @[dec_decode_ctl.scala 839:51]
-  wire  div_e1_to_r = _T_918 | _T_924; // @[dec_decode_ctl.scala 831:58]
-  wire  _T_928 = ~div_e1_to_r; // @[dec_decode_ctl.scala 840:26]
-  wire  _T_929 = io_dec_div_active & _T_928; // @[dec_decode_ctl.scala 840:24]
+  wire  _T_924 = r_d_bits_i0div & r_d_valid; // @[dec_decode_ctl.scala 837:21]
+  wire  _T_925 = _T_924 & io_dec_tlu_flush_lower_r; // @[dec_decode_ctl.scala 837:33]
+  wire  _T_926 = _T_925 & io_dec_tlu_i0_kill_writeb_r; // @[dec_decode_ctl.scala 837:60]
+  wire  div_flush = _T_923 | _T_926; // @[dec_decode_ctl.scala 836:62]
+  wire  _T_927 = io_dec_div_active & div_flush; // @[dec_decode_ctl.scala 841:51]
+  wire  div_e1_to_r = _T_918 | _T_924; // @[dec_decode_ctl.scala 833:58]
+  wire  _T_928 = ~div_e1_to_r; // @[dec_decode_ctl.scala 842:26]
+  wire  _T_929 = io_dec_div_active & _T_928; // @[dec_decode_ctl.scala 842:24]
   reg [4:0] r_d_bits_i0rd; // @[Reg.scala 27:20]
-  wire  _T_930 = r_d_bits_i0rd == io_div_waddr_wb; // @[dec_decode_ctl.scala 840:56]
-  wire  _T_931 = _T_929 & _T_930; // @[dec_decode_ctl.scala 840:39]
+  wire  _T_930 = r_d_bits_i0rd == io_div_waddr_wb; // @[dec_decode_ctl.scala 842:56]
+  wire  _T_931 = _T_929 & _T_930; // @[dec_decode_ctl.scala 842:39]
   reg  r_d_bits_i0v; // @[Reg.scala 27:20]
-  wire  _T_857 = ~io_dec_tlu_flush_lower_wb; // @[dec_decode_ctl.scala 798:51]
-  wire  r_d_in_bits_i0v = r_d_bits_i0v & _T_857; // @[dec_decode_ctl.scala 798:49]
-  wire  _T_868 = ~io_dec_tlu_i0_kill_writeb_r; // @[dec_decode_ctl.scala 806:47]
-  wire  i0_wen_r = r_d_in_bits_i0v & _T_868; // @[dec_decode_ctl.scala 806:45]
-  wire  _T_932 = _T_931 & i0_wen_r; // @[dec_decode_ctl.scala 840:77]
-  wire  nonblock_div_cancel = _T_927 | _T_932; // @[dec_decode_ctl.scala 839:65]
-  wire  _T_936 = ~nonblock_div_cancel; // @[dec_decode_ctl.scala 845:78]
-  wire  _T_937 = _T_935 & _T_936; // @[dec_decode_ctl.scala 845:76]
-  wire  div_active_in = i0_div_decode_d | _T_937; // @[dec_decode_ctl.scala 845:36]
+  wire  _T_857 = ~io_dec_tlu_flush_lower_wb; // @[dec_decode_ctl.scala 800:51]
+  wire  r_d_in_bits_i0v = r_d_bits_i0v & _T_857; // @[dec_decode_ctl.scala 800:49]
+  wire  _T_868 = ~io_dec_tlu_i0_kill_writeb_r; // @[dec_decode_ctl.scala 808:47]
+  wire  i0_wen_r = r_d_in_bits_i0v & _T_868; // @[dec_decode_ctl.scala 808:45]
+  wire  _T_932 = _T_931 & i0_wen_r; // @[dec_decode_ctl.scala 842:77]
+  wire  nonblock_div_cancel = _T_927 | _T_932; // @[dec_decode_ctl.scala 841:65]
+  wire  _T_936 = ~nonblock_div_cancel; // @[dec_decode_ctl.scala 847:78]
+  wire  _T_937 = _T_935 & _T_936; // @[dec_decode_ctl.scala 847:76]
+  wire  div_active_in = i0_div_decode_d | _T_937; // @[dec_decode_ctl.scala 847:36]
   reg  _T_42; // @[Reg.scala 27:20]
   wire  _T_40 = div_active_in ^ _T_42; // @[lib.scala 470:21]
   wire  _T_41 = |_T_40; // @[lib.scala 470:29]
@@ -2204,176 +2204,176 @@ module dec_decode_ctl(
   reg  debug_valid_x; // @[Reg.scala 27:20]
   wire  _T_47 = io_dec_debug_valid_d ^ debug_valid_x; // @[lib.scala 470:21]
   wire  _T_48 = |_T_47; // @[lib.scala 470:29]
-  wire  _T_71 = _T_70 & i0_legal_decode_d; // @[dec_decode_ctl.scala 239:74]
-  wire  _T_74 = io_dec_i0_brp_bits_br_start_error & i0_legal_decode_d; // @[dec_decode_ctl.scala 240:96]
-  wire  i0_dp_raw_pm_alu = i0_dec_io_out_pm_alu; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_pm_alu = _T_80 ? 1'h0 : i0_dp_raw_pm_alu; // @[dec_decode_ctl.scala 280:50]
-  wire  i0_dp_raw_fence_i = i0_dec_io_out_fence_i; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_fence_i = _T_80 ? 1'h0 : i0_dp_raw_fence_i; // @[dec_decode_ctl.scala 280:50]
-  wire  i0_dp_raw_fence = i0_dec_io_out_fence; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_fence = _T_80 ? 1'h0 : i0_dp_raw_fence; // @[dec_decode_ctl.scala 280:50]
-  wire  i0_dp_raw_rem = i0_dec_io_out_rem; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_raw_low = i0_dec_io_out_low; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_raw_rs2_sign = i0_dec_io_out_rs2_sign; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_raw_rs1_sign = i0_dec_io_out_rs1_sign; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_raw_mul = i0_dec_io_out_mul; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_mul = _T_80 ? 1'h0 : i0_dp_raw_mul; // @[dec_decode_ctl.scala 280:50]
-  wire  i0_dp_raw_mret = i0_dec_io_out_mret; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_mret = _T_80 ? 1'h0 : i0_dp_raw_mret; // @[dec_decode_ctl.scala 280:50]
-  wire  i0_dp_raw_ecall = i0_dec_io_out_ecall; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_ecall = _T_80 ? 1'h0 : i0_dp_raw_ecall; // @[dec_decode_ctl.scala 280:50]
-  wire  i0_dp_raw_ebreak = i0_dec_io_out_ebreak; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_ebreak = _T_80 ? 1'h0 : i0_dp_raw_ebreak; // @[dec_decode_ctl.scala 280:50]
-  wire  i0_dp_raw_presync = i0_dec_io_out_presync; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_presync = _T_80 ? 1'h0 : i0_dp_raw_presync; // @[dec_decode_ctl.scala 280:50]
-  wire  i0_dp_raw_csr_imm = i0_dec_io_out_csr_imm; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_csr_imm = _T_80 ? 1'h0 : i0_dp_raw_csr_imm; // @[dec_decode_ctl.scala 280:50]
-  wire  i0_dp_raw_csr_set = i0_dec_io_out_csr_set; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_csr_set = _T_80 ? 1'h0 : i0_dp_raw_csr_set; // @[dec_decode_ctl.scala 280:50]
-  wire  i0_dp_raw_csr_clr = i0_dec_io_out_csr_clr; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_csr_clr = _T_80 ? 1'h0 : i0_dp_raw_csr_clr; // @[dec_decode_ctl.scala 280:50]
-  wire  i0_dp_raw_word = i0_dec_io_out_word; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_word = _T_80 ? 1'h0 : i0_dp_raw_word; // @[dec_decode_ctl.scala 280:50]
-  wire  i0_dp_raw_half = i0_dec_io_out_half; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_half = _T_80 ? 1'h0 : i0_dp_raw_half; // @[dec_decode_ctl.scala 280:50]
-  wire  i0_dp_raw_by = i0_dec_io_out_by; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_by = _T_80 ? 1'h0 : i0_dp_raw_by; // @[dec_decode_ctl.scala 280:50]
-  wire  i0_dp_jal = _T_80 ? 1'h0 : i0_dp_raw_jal; // @[dec_decode_ctl.scala 280:50]
-  wire  i0_dp_raw_blt = i0_dec_io_out_blt; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_raw_bge = i0_dec_io_out_bge; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_raw_bne = i0_dec_io_out_bne; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_raw_beq = i0_dec_io_out_beq; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_condbr = _T_80 ? 1'h0 : i0_dp_raw_condbr; // @[dec_decode_ctl.scala 280:50]
-  wire  i0_dp_raw_unsign = i0_dec_io_out_unsign; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_unsign = _T_80 ? 1'h0 : i0_dp_raw_unsign; // @[dec_decode_ctl.scala 280:50]
-  wire  i0_dp_raw_slt = i0_dec_io_out_slt; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_raw_srl = i0_dec_io_out_srl; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_raw_sra = i0_dec_io_out_sra; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_raw_sll = i0_dec_io_out_sll; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_raw_lxor = i0_dec_io_out_lxor; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_raw_lor = i0_dec_io_out_lor; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_raw_land = i0_dec_io_out_land; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_raw_sub = i0_dec_io_out_sub; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_raw_add = i0_dec_io_out_add; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_raw_lsu = i0_dec_io_out_lsu; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_lsu = _T_80 ? 1'h0 : i0_dp_raw_lsu; // @[dec_decode_ctl.scala 280:50]
-  wire  i0_dp_raw_store = i0_dec_io_out_store; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_store = _T_80 ? 1'h0 : i0_dp_raw_store; // @[dec_decode_ctl.scala 280:50]
-  wire  i0_dp_raw_load = i0_dec_io_out_load; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_load = _T_80 ? 1'h0 : i0_dp_raw_load; // @[dec_decode_ctl.scala 280:50]
-  wire  i0_dp_raw_pc = i0_dec_io_out_pc; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_imm20 = _T_80 ? 1'h0 : i0_dp_raw_imm20; // @[dec_decode_ctl.scala 280:50]
-  wire  i0_dp_raw_shimm5 = i0_dec_io_out_shimm5; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_shimm5 = _T_80 ? 1'h0 : i0_dp_raw_shimm5; // @[dec_decode_ctl.scala 280:50]
-  wire  i0_dp_raw_rd = i0_dec_io_out_rd; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_rd = _T_80 ? 1'h0 : i0_dp_raw_rd; // @[dec_decode_ctl.scala 280:50]
-  wire  i0_dp_imm12 = _T_80 ? 1'h0 : i0_dp_raw_imm12; // @[dec_decode_ctl.scala 280:50]
-  wire  i0_dp_raw_rs2 = i0_dec_io_out_rs2; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_rs2 = _T_80 | i0_dp_raw_rs2; // @[dec_decode_ctl.scala 280:50]
-  wire  i0_dp_raw_rs1 = i0_dec_io_out_rs1; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_rs1 = _T_80 | i0_dp_raw_rs1; // @[dec_decode_ctl.scala 280:50]
-  wire  i0_dp_raw_alu = i0_dec_io_out_alu; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_alu = _T_80 | i0_dp_raw_alu; // @[dec_decode_ctl.scala 280:50]
-  wire  i0_dp_raw_zba = i0_dec_io_out_zba; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_zba = _T_80 ? 1'h0 : i0_dp_raw_zba; // @[dec_decode_ctl.scala 280:50]
-  wire  i0_dp_raw_sh3add = i0_dec_io_out_sh3add; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_raw_sh2add = i0_dec_io_out_sh2add; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_raw_sh1add = i0_dec_io_out_sh1add; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_raw_zbf = i0_dec_io_out_zbf; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_zbf = _T_80 ? 1'h0 : i0_dp_raw_zbf; // @[dec_decode_ctl.scala 280:50]
-  wire  i0_dp_raw_bfp = i0_dec_io_out_bfp; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_raw_zbr = i0_dec_io_out_zbr; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_zbr = _T_80 ? 1'h0 : i0_dp_raw_zbr; // @[dec_decode_ctl.scala 280:50]
-  wire  i0_dp_raw_crc32c_w = i0_dec_io_out_crc32c_w; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_raw_crc32c_h = i0_dec_io_out_crc32c_h; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_raw_crc32c_b = i0_dec_io_out_crc32c_b; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_raw_crc32_w = i0_dec_io_out_crc32_w; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_raw_crc32_h = i0_dec_io_out_crc32_h; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_raw_crc32_b = i0_dec_io_out_crc32_b; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_raw_zbp = i0_dec_io_out_zbp; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_zbp = _T_80 ? 1'h0 : i0_dp_raw_zbp; // @[dec_decode_ctl.scala 280:50]
-  wire  i0_dp_raw_unshfl = i0_dec_io_out_unshfl; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_raw_shfl = i0_dec_io_out_shfl; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_raw_zbc = i0_dec_io_out_zbc; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_zbc = _T_80 ? 1'h0 : i0_dp_raw_zbc; // @[dec_decode_ctl.scala 280:50]
-  wire  i0_dp_raw_clmulr = i0_dec_io_out_clmulr; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_raw_clmulh = i0_dec_io_out_clmulh; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_raw_clmul = i0_dec_io_out_clmul; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_raw_zbe = i0_dec_io_out_zbe; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_zbe = _T_80 ? 1'h0 : i0_dp_raw_zbe; // @[dec_decode_ctl.scala 280:50]
-  wire  i0_dp_raw_bdep = i0_dec_io_out_bdep; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_raw_bext = i0_dec_io_out_bext; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_raw_zbs = i0_dec_io_out_zbs; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_zbs = _T_80 ? 1'h0 : i0_dp_raw_zbs; // @[dec_decode_ctl.scala 280:50]
-  wire  i0_dp_raw_sbext = i0_dec_io_out_sbext; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_raw_sbinv = i0_dec_io_out_sbinv; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_raw_sbclr = i0_dec_io_out_sbclr; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_raw_sbset = i0_dec_io_out_sbset; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_raw_zbb = i0_dec_io_out_zbb; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_zbb = _T_80 ? 1'h0 : i0_dp_raw_zbb; // @[dec_decode_ctl.scala 280:50]
-  wire  i0_dp_raw_gorc = i0_dec_io_out_gorc; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_raw_grev = i0_dec_io_out_grev; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_raw_ror = i0_dec_io_out_ror; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_raw_rol = i0_dec_io_out_rol; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_raw_packh = i0_dec_io_out_packh; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_raw_packu = i0_dec_io_out_packu; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_raw_pack = i0_dec_io_out_pack; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_raw_max = i0_dec_io_out_max; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_raw_min = i0_dec_io_out_min; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_raw_sro = i0_dec_io_out_sro; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_raw_slo = i0_dec_io_out_slo; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_raw_sext_h = i0_dec_io_out_sext_h; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_raw_sext_b = i0_dec_io_out_sext_b; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_raw_pcnt = i0_dec_io_out_pcnt; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_raw_ctz = i0_dec_io_out_ctz; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_dp_raw_clz = i0_dec_io_out_clz; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12]
-  wire  i0_pcall = i0_dp_jal & i0_pcall_case; // @[dec_decode_ctl.scala 456:38]
-  wire  _T_83 = i0_dp_condbr | i0_pcall; // @[dec_decode_ctl.scala 294:54]
-  wire  i0_pja = i0_dp_jal & i0_pja_case; // @[dec_decode_ctl.scala 458:38]
-  wire  _T_84 = _T_83 | i0_pja; // @[dec_decode_ctl.scala 294:65]
-  wire  i0_pret = i0_dp_jal & i0_pret_case; // @[dec_decode_ctl.scala 463:32]
-  wire  i0_predict_br = _T_84 | i0_pret; // @[dec_decode_ctl.scala 294:74]
-  wire  _T_86 = io_dec_i0_brp_bits_hist[1] & i0_brp_valid; // @[dec_decode_ctl.scala 295:69]
-  wire  _T_87 = ~_T_86; // @[dec_decode_ctl.scala 295:40]
-  wire  i0_ap_pc2 = ~io_dec_i0_pc4_d; // @[dec_decode_ctl.scala 297:40]
-  wire  cam_data_reset = io_dctl_busbuff_lsu_nonblock_load_data_valid | io_dctl_busbuff_lsu_nonblock_load_data_error; // @[dec_decode_ctl.scala 356:76]
+  wire  _T_71 = _T_70 & i0_legal_decode_d; // @[dec_decode_ctl.scala 241:74]
+  wire  _T_74 = io_dec_i0_brp_bits_br_start_error & i0_legal_decode_d; // @[dec_decode_ctl.scala 242:96]
+  wire  i0_dp_raw_pm_alu = i0_dec_io_out_pm_alu; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_pm_alu = _T_80 ? 1'h0 : i0_dp_raw_pm_alu; // @[dec_decode_ctl.scala 282:50]
+  wire  i0_dp_raw_fence_i = i0_dec_io_out_fence_i; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_fence_i = _T_80 ? 1'h0 : i0_dp_raw_fence_i; // @[dec_decode_ctl.scala 282:50]
+  wire  i0_dp_raw_fence = i0_dec_io_out_fence; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_fence = _T_80 ? 1'h0 : i0_dp_raw_fence; // @[dec_decode_ctl.scala 282:50]
+  wire  i0_dp_raw_rem = i0_dec_io_out_rem; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_raw_low = i0_dec_io_out_low; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_raw_rs2_sign = i0_dec_io_out_rs2_sign; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_raw_rs1_sign = i0_dec_io_out_rs1_sign; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_raw_mul = i0_dec_io_out_mul; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_mul = _T_80 ? 1'h0 : i0_dp_raw_mul; // @[dec_decode_ctl.scala 282:50]
+  wire  i0_dp_raw_mret = i0_dec_io_out_mret; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_mret = _T_80 ? 1'h0 : i0_dp_raw_mret; // @[dec_decode_ctl.scala 282:50]
+  wire  i0_dp_raw_ecall = i0_dec_io_out_ecall; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_ecall = _T_80 ? 1'h0 : i0_dp_raw_ecall; // @[dec_decode_ctl.scala 282:50]
+  wire  i0_dp_raw_ebreak = i0_dec_io_out_ebreak; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_ebreak = _T_80 ? 1'h0 : i0_dp_raw_ebreak; // @[dec_decode_ctl.scala 282:50]
+  wire  i0_dp_raw_presync = i0_dec_io_out_presync; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_presync = _T_80 ? 1'h0 : i0_dp_raw_presync; // @[dec_decode_ctl.scala 282:50]
+  wire  i0_dp_raw_csr_imm = i0_dec_io_out_csr_imm; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_csr_imm = _T_80 ? 1'h0 : i0_dp_raw_csr_imm; // @[dec_decode_ctl.scala 282:50]
+  wire  i0_dp_raw_csr_set = i0_dec_io_out_csr_set; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_csr_set = _T_80 ? 1'h0 : i0_dp_raw_csr_set; // @[dec_decode_ctl.scala 282:50]
+  wire  i0_dp_raw_csr_clr = i0_dec_io_out_csr_clr; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_csr_clr = _T_80 ? 1'h0 : i0_dp_raw_csr_clr; // @[dec_decode_ctl.scala 282:50]
+  wire  i0_dp_raw_word = i0_dec_io_out_word; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_word = _T_80 ? 1'h0 : i0_dp_raw_word; // @[dec_decode_ctl.scala 282:50]
+  wire  i0_dp_raw_half = i0_dec_io_out_half; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_half = _T_80 ? 1'h0 : i0_dp_raw_half; // @[dec_decode_ctl.scala 282:50]
+  wire  i0_dp_raw_by = i0_dec_io_out_by; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_by = _T_80 ? 1'h0 : i0_dp_raw_by; // @[dec_decode_ctl.scala 282:50]
+  wire  i0_dp_jal = _T_80 ? 1'h0 : i0_dp_raw_jal; // @[dec_decode_ctl.scala 282:50]
+  wire  i0_dp_raw_blt = i0_dec_io_out_blt; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_raw_bge = i0_dec_io_out_bge; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_raw_bne = i0_dec_io_out_bne; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_raw_beq = i0_dec_io_out_beq; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_condbr = _T_80 ? 1'h0 : i0_dp_raw_condbr; // @[dec_decode_ctl.scala 282:50]
+  wire  i0_dp_raw_unsign = i0_dec_io_out_unsign; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_unsign = _T_80 ? 1'h0 : i0_dp_raw_unsign; // @[dec_decode_ctl.scala 282:50]
+  wire  i0_dp_raw_slt = i0_dec_io_out_slt; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_raw_srl = i0_dec_io_out_srl; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_raw_sra = i0_dec_io_out_sra; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_raw_sll = i0_dec_io_out_sll; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_raw_lxor = i0_dec_io_out_lxor; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_raw_lor = i0_dec_io_out_lor; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_raw_land = i0_dec_io_out_land; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_raw_sub = i0_dec_io_out_sub; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_raw_add = i0_dec_io_out_add; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_raw_lsu = i0_dec_io_out_lsu; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_lsu = _T_80 ? 1'h0 : i0_dp_raw_lsu; // @[dec_decode_ctl.scala 282:50]
+  wire  i0_dp_raw_store = i0_dec_io_out_store; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_store = _T_80 ? 1'h0 : i0_dp_raw_store; // @[dec_decode_ctl.scala 282:50]
+  wire  i0_dp_raw_load = i0_dec_io_out_load; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_load = _T_80 ? 1'h0 : i0_dp_raw_load; // @[dec_decode_ctl.scala 282:50]
+  wire  i0_dp_raw_pc = i0_dec_io_out_pc; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_imm20 = _T_80 ? 1'h0 : i0_dp_raw_imm20; // @[dec_decode_ctl.scala 282:50]
+  wire  i0_dp_raw_shimm5 = i0_dec_io_out_shimm5; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_shimm5 = _T_80 ? 1'h0 : i0_dp_raw_shimm5; // @[dec_decode_ctl.scala 282:50]
+  wire  i0_dp_raw_rd = i0_dec_io_out_rd; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_rd = _T_80 ? 1'h0 : i0_dp_raw_rd; // @[dec_decode_ctl.scala 282:50]
+  wire  i0_dp_imm12 = _T_80 ? 1'h0 : i0_dp_raw_imm12; // @[dec_decode_ctl.scala 282:50]
+  wire  i0_dp_raw_rs2 = i0_dec_io_out_rs2; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_rs2 = _T_80 | i0_dp_raw_rs2; // @[dec_decode_ctl.scala 282:50]
+  wire  i0_dp_raw_rs1 = i0_dec_io_out_rs1; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_rs1 = _T_80 | i0_dp_raw_rs1; // @[dec_decode_ctl.scala 282:50]
+  wire  i0_dp_raw_alu = i0_dec_io_out_alu; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_alu = _T_80 | i0_dp_raw_alu; // @[dec_decode_ctl.scala 282:50]
+  wire  i0_dp_raw_zba = i0_dec_io_out_zba; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_zba = _T_80 ? 1'h0 : i0_dp_raw_zba; // @[dec_decode_ctl.scala 282:50]
+  wire  i0_dp_raw_sh3add = i0_dec_io_out_sh3add; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_raw_sh2add = i0_dec_io_out_sh2add; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_raw_sh1add = i0_dec_io_out_sh1add; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_raw_zbf = i0_dec_io_out_zbf; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_zbf = _T_80 ? 1'h0 : i0_dp_raw_zbf; // @[dec_decode_ctl.scala 282:50]
+  wire  i0_dp_raw_bfp = i0_dec_io_out_bfp; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_raw_zbr = i0_dec_io_out_zbr; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_zbr = _T_80 ? 1'h0 : i0_dp_raw_zbr; // @[dec_decode_ctl.scala 282:50]
+  wire  i0_dp_raw_crc32c_w = i0_dec_io_out_crc32c_w; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_raw_crc32c_h = i0_dec_io_out_crc32c_h; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_raw_crc32c_b = i0_dec_io_out_crc32c_b; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_raw_crc32_w = i0_dec_io_out_crc32_w; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_raw_crc32_h = i0_dec_io_out_crc32_h; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_raw_crc32_b = i0_dec_io_out_crc32_b; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_raw_zbp = i0_dec_io_out_zbp; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_zbp = _T_80 ? 1'h0 : i0_dp_raw_zbp; // @[dec_decode_ctl.scala 282:50]
+  wire  i0_dp_raw_unshfl = i0_dec_io_out_unshfl; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_raw_shfl = i0_dec_io_out_shfl; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_raw_zbc = i0_dec_io_out_zbc; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_zbc = _T_80 ? 1'h0 : i0_dp_raw_zbc; // @[dec_decode_ctl.scala 282:50]
+  wire  i0_dp_raw_clmulr = i0_dec_io_out_clmulr; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_raw_clmulh = i0_dec_io_out_clmulh; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_raw_clmul = i0_dec_io_out_clmul; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_raw_zbe = i0_dec_io_out_zbe; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_zbe = _T_80 ? 1'h0 : i0_dp_raw_zbe; // @[dec_decode_ctl.scala 282:50]
+  wire  i0_dp_raw_bdep = i0_dec_io_out_bdep; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_raw_bext = i0_dec_io_out_bext; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_raw_zbs = i0_dec_io_out_zbs; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_zbs = _T_80 ? 1'h0 : i0_dp_raw_zbs; // @[dec_decode_ctl.scala 282:50]
+  wire  i0_dp_raw_sbext = i0_dec_io_out_sbext; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_raw_sbinv = i0_dec_io_out_sbinv; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_raw_sbclr = i0_dec_io_out_sbclr; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_raw_sbset = i0_dec_io_out_sbset; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_raw_zbb = i0_dec_io_out_zbb; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_zbb = _T_80 ? 1'h0 : i0_dp_raw_zbb; // @[dec_decode_ctl.scala 282:50]
+  wire  i0_dp_raw_gorc = i0_dec_io_out_gorc; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_raw_grev = i0_dec_io_out_grev; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_raw_ror = i0_dec_io_out_ror; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_raw_rol = i0_dec_io_out_rol; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_raw_packh = i0_dec_io_out_packh; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_raw_packu = i0_dec_io_out_packu; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_raw_pack = i0_dec_io_out_pack; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_raw_max = i0_dec_io_out_max; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_raw_min = i0_dec_io_out_min; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_raw_sro = i0_dec_io_out_sro; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_raw_slo = i0_dec_io_out_slo; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_raw_sext_h = i0_dec_io_out_sext_h; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_raw_sext_b = i0_dec_io_out_sext_b; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_raw_pcnt = i0_dec_io_out_pcnt; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_raw_ctz = i0_dec_io_out_ctz; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_dp_raw_clz = i0_dec_io_out_clz; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
+  wire  i0_pcall = i0_dp_jal & i0_pcall_case; // @[dec_decode_ctl.scala 458:38]
+  wire  _T_83 = i0_dp_condbr | i0_pcall; // @[dec_decode_ctl.scala 296:54]
+  wire  i0_pja = i0_dp_jal & i0_pja_case; // @[dec_decode_ctl.scala 460:38]
+  wire  _T_84 = _T_83 | i0_pja; // @[dec_decode_ctl.scala 296:65]
+  wire  i0_pret = i0_dp_jal & i0_pret_case; // @[dec_decode_ctl.scala 465:32]
+  wire  i0_predict_br = _T_84 | i0_pret; // @[dec_decode_ctl.scala 296:74]
+  wire  _T_86 = io_dec_i0_brp_bits_hist[1] & i0_brp_valid; // @[dec_decode_ctl.scala 297:69]
+  wire  _T_87 = ~_T_86; // @[dec_decode_ctl.scala 297:40]
+  wire  i0_ap_pc2 = ~io_dec_i0_pc4_d; // @[dec_decode_ctl.scala 299:40]
+  wire  cam_data_reset = io_dctl_busbuff_lsu_nonblock_load_data_valid | io_dctl_busbuff_lsu_nonblock_load_data_error; // @[dec_decode_ctl.scala 358:76]
   reg [2:0] cam_raw_0_bits_tag; // @[Reg.scala 27:20]
-  wire [2:0] _GEN_256 = {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_data_tag}; // @[dec_decode_ctl.scala 367:67]
-  wire  _T_133 = _GEN_256 == cam_raw_0_bits_tag; // @[dec_decode_ctl.scala 367:67]
-  wire  _T_134 = cam_data_reset & _T_133; // @[dec_decode_ctl.scala 367:45]
+  wire [2:0] _GEN_256 = {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_data_tag}; // @[dec_decode_ctl.scala 369:67]
+  wire  _T_133 = _GEN_256 == cam_raw_0_bits_tag; // @[dec_decode_ctl.scala 369:67]
+  wire  _T_134 = cam_data_reset & _T_133; // @[dec_decode_ctl.scala 369:45]
   reg  cam_raw_0_valid; // @[Reg.scala 27:20]
-  wire  cam_data_reset_val_0 = _T_134 & cam_raw_0_valid; // @[dec_decode_ctl.scala 367:88]
-  wire  cam_0_valid = cam_data_reset_val_0 ? 1'h0 : cam_raw_0_valid; // @[dec_decode_ctl.scala 371:39]
-  wire  _T_90 = ~cam_0_valid; // @[dec_decode_ctl.scala 348:78]
+  wire  cam_data_reset_val_0 = _T_134 & cam_raw_0_valid; // @[dec_decode_ctl.scala 369:88]
+  wire  cam_0_valid = cam_data_reset_val_0 ? 1'h0 : cam_raw_0_valid; // @[dec_decode_ctl.scala 373:39]
+  wire  _T_90 = ~cam_0_valid; // @[dec_decode_ctl.scala 350:78]
   reg [2:0] cam_raw_1_bits_tag; // @[Reg.scala 27:20]
-  wire  _T_169 = _GEN_256 == cam_raw_1_bits_tag; // @[dec_decode_ctl.scala 367:67]
-  wire  _T_170 = cam_data_reset & _T_169; // @[dec_decode_ctl.scala 367:45]
+  wire  _T_169 = _GEN_256 == cam_raw_1_bits_tag; // @[dec_decode_ctl.scala 369:67]
+  wire  _T_170 = cam_data_reset & _T_169; // @[dec_decode_ctl.scala 369:45]
   reg  cam_raw_1_valid; // @[Reg.scala 27:20]
-  wire  cam_data_reset_val_1 = _T_170 & cam_raw_1_valid; // @[dec_decode_ctl.scala 367:88]
-  wire  cam_1_valid = cam_data_reset_val_1 ? 1'h0 : cam_raw_1_valid; // @[dec_decode_ctl.scala 371:39]
-  wire  _T_93 = ~cam_1_valid; // @[dec_decode_ctl.scala 348:78]
-  wire  _T_96 = cam_0_valid & _T_93; // @[dec_decode_ctl.scala 348:126]
-  wire [1:0] _T_98 = {io_dctl_busbuff_lsu_nonblock_load_valid_m, 1'h0}; // @[dec_decode_ctl.scala 348:158]
+  wire  cam_data_reset_val_1 = _T_170 & cam_raw_1_valid; // @[dec_decode_ctl.scala 369:88]
+  wire  cam_1_valid = cam_data_reset_val_1 ? 1'h0 : cam_raw_1_valid; // @[dec_decode_ctl.scala 373:39]
+  wire  _T_93 = ~cam_1_valid; // @[dec_decode_ctl.scala 350:78]
+  wire  _T_96 = cam_0_valid & _T_93; // @[dec_decode_ctl.scala 350:126]
+  wire [1:0] _T_98 = {io_dctl_busbuff_lsu_nonblock_load_valid_m, 1'h0}; // @[dec_decode_ctl.scala 350:158]
   reg [2:0] cam_raw_2_bits_tag; // @[Reg.scala 27:20]
-  wire  _T_205 = _GEN_256 == cam_raw_2_bits_tag; // @[dec_decode_ctl.scala 367:67]
-  wire  _T_206 = cam_data_reset & _T_205; // @[dec_decode_ctl.scala 367:45]
+  wire  _T_205 = _GEN_256 == cam_raw_2_bits_tag; // @[dec_decode_ctl.scala 369:67]
+  wire  _T_206 = cam_data_reset & _T_205; // @[dec_decode_ctl.scala 369:45]
   reg  cam_raw_2_valid; // @[Reg.scala 27:20]
-  wire  cam_data_reset_val_2 = _T_206 & cam_raw_2_valid; // @[dec_decode_ctl.scala 367:88]
-  wire  cam_2_valid = cam_data_reset_val_2 ? 1'h0 : cam_raw_2_valid; // @[dec_decode_ctl.scala 371:39]
-  wire  _T_99 = ~cam_2_valid; // @[dec_decode_ctl.scala 348:78]
-  wire  _T_102 = cam_0_valid & cam_1_valid; // @[dec_decode_ctl.scala 348:126]
-  wire  _T_105 = _T_102 & _T_99; // @[dec_decode_ctl.scala 348:126]
-  wire [2:0] _T_107 = {io_dctl_busbuff_lsu_nonblock_load_valid_m, 2'h0}; // @[dec_decode_ctl.scala 348:158]
+  wire  cam_data_reset_val_2 = _T_206 & cam_raw_2_valid; // @[dec_decode_ctl.scala 369:88]
+  wire  cam_2_valid = cam_data_reset_val_2 ? 1'h0 : cam_raw_2_valid; // @[dec_decode_ctl.scala 373:39]
+  wire  _T_99 = ~cam_2_valid; // @[dec_decode_ctl.scala 350:78]
+  wire  _T_102 = cam_0_valid & cam_1_valid; // @[dec_decode_ctl.scala 350:126]
+  wire  _T_105 = _T_102 & _T_99; // @[dec_decode_ctl.scala 350:126]
+  wire [2:0] _T_107 = {io_dctl_busbuff_lsu_nonblock_load_valid_m, 2'h0}; // @[dec_decode_ctl.scala 350:158]
   reg [2:0] cam_raw_3_bits_tag; // @[Reg.scala 27:20]
-  wire  _T_241 = _GEN_256 == cam_raw_3_bits_tag; // @[dec_decode_ctl.scala 367:67]
-  wire  _T_242 = cam_data_reset & _T_241; // @[dec_decode_ctl.scala 367:45]
+  wire  _T_241 = _GEN_256 == cam_raw_3_bits_tag; // @[dec_decode_ctl.scala 369:67]
+  wire  _T_242 = cam_data_reset & _T_241; // @[dec_decode_ctl.scala 369:45]
   reg  cam_raw_3_valid; // @[Reg.scala 27:20]
-  wire  cam_data_reset_val_3 = _T_242 & cam_raw_3_valid; // @[dec_decode_ctl.scala 367:88]
-  wire  cam_3_valid = cam_data_reset_val_3 ? 1'h0 : cam_raw_3_valid; // @[dec_decode_ctl.scala 371:39]
-  wire  _T_108 = ~cam_3_valid; // @[dec_decode_ctl.scala 348:78]
-  wire  _T_114 = _T_102 & cam_2_valid; // @[dec_decode_ctl.scala 348:126]
-  wire  _T_117 = _T_114 & _T_108; // @[dec_decode_ctl.scala 348:126]
-  wire [3:0] _T_119 = {io_dctl_busbuff_lsu_nonblock_load_valid_m, 3'h0}; // @[dec_decode_ctl.scala 348:158]
+  wire  cam_data_reset_val_3 = _T_242 & cam_raw_3_valid; // @[dec_decode_ctl.scala 369:88]
+  wire  cam_3_valid = cam_data_reset_val_3 ? 1'h0 : cam_raw_3_valid; // @[dec_decode_ctl.scala 373:39]
+  wire  _T_108 = ~cam_3_valid; // @[dec_decode_ctl.scala 350:78]
+  wire  _T_114 = _T_102 & cam_2_valid; // @[dec_decode_ctl.scala 350:126]
+  wire  _T_117 = _T_114 & _T_108; // @[dec_decode_ctl.scala 350:126]
+  wire [3:0] _T_119 = {io_dctl_busbuff_lsu_nonblock_load_valid_m, 3'h0}; // @[dec_decode_ctl.scala 350:158]
   wire  _T_120 = _T_90 & io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[Mux.scala 27:72]
   wire [1:0] _T_121 = _T_96 ? _T_98 : 2'h0; // @[Mux.scala 27:72]
   wire [2:0] _T_122 = _T_105 ? _T_107 : 3'h0; // @[Mux.scala 27:72]
@@ -2385,36 +2385,36 @@ module dec_decode_ctl(
   wire [3:0] _GEN_262 = {{1'd0}, _T_125}; // @[Mux.scala 27:72]
   wire [3:0] cam_wen = _GEN_262 | _T_123; // @[Mux.scala 27:72]
   reg  x_d_bits_i0load; // @[Reg.scala 27:20]
-  wire [4:0] nonblock_load_rd = x_d_bits_i0load ? x_d_bits_i0rd : 5'h0; // @[dec_decode_ctl.scala 359:31]
-  reg [2:0] _T_815; // @[dec_decode_ctl.scala 764:80]
-  wire [3:0] i0_pipe_en = {io_dec_aln_dec_i0_decode_d,_T_815}; // @[Cat.scala 29:58]
-  wire  _T_821 = |i0_pipe_en[2:1]; // @[dec_decode_ctl.scala 767:49]
-  wire  i0_r_ctl_en = _T_821 | io_clk_override; // @[dec_decode_ctl.scala 767:53]
+  wire [4:0] nonblock_load_rd = x_d_bits_i0load ? x_d_bits_i0rd : 5'h0; // @[dec_decode_ctl.scala 361:31]
+  reg [2:0] _T_815; // @[dec_decode_ctl.scala 766:72]
+  wire [3:0] i0_pipe_en = {io_dec_i0_decode_d,_T_815}; // @[Cat.scala 29:58]
+  wire  _T_821 = |i0_pipe_en[2:1]; // @[dec_decode_ctl.scala 769:49]
+  wire  i0_r_ctl_en = _T_821 | io_clk_override; // @[dec_decode_ctl.scala 769:53]
   reg  nonblock_load_valid_m_delay; // @[Reg.scala 27:20]
   reg  r_d_bits_i0load; // @[Reg.scala 27:20]
-  wire  i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d_bits_i0load; // @[dec_decode_ctl.scala 364:56]
-  wire [2:0] _GEN_263 = {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_inv_tag_r}; // @[dec_decode_ctl.scala 366:66]
-  wire  _T_130 = _GEN_263 == cam_raw_0_bits_tag; // @[dec_decode_ctl.scala 366:66]
-  wire  _T_131 = io_dctl_busbuff_lsu_nonblock_load_inv_r & _T_130; // @[dec_decode_ctl.scala 366:45]
-  wire  cam_inv_reset_val_0 = _T_131 & cam_0_valid; // @[dec_decode_ctl.scala 366:87]
+  wire  i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d_bits_i0load; // @[dec_decode_ctl.scala 366:56]
+  wire [2:0] _GEN_263 = {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_inv_tag_r}; // @[dec_decode_ctl.scala 368:66]
+  wire  _T_130 = _GEN_263 == cam_raw_0_bits_tag; // @[dec_decode_ctl.scala 368:66]
+  wire  _T_131 = io_dctl_busbuff_lsu_nonblock_load_inv_r & _T_130; // @[dec_decode_ctl.scala 368:45]
+  wire  cam_inv_reset_val_0 = _T_131 & cam_0_valid; // @[dec_decode_ctl.scala 368:87]
   reg [4:0] cam_raw_0_bits_rd; // @[Reg.scala 27:20]
-  wire  _T_142 = r_d_bits_i0rd == cam_raw_0_bits_rd; // @[dec_decode_ctl.scala 379:85]
-  wire  _T_143 = i0_wen_r & _T_142; // @[dec_decode_ctl.scala 379:64]
+  wire  _T_142 = r_d_bits_i0rd == cam_raw_0_bits_rd; // @[dec_decode_ctl.scala 381:85]
+  wire  _T_143 = i0_wen_r & _T_142; // @[dec_decode_ctl.scala 381:64]
   reg  cam_raw_0_bits_wb; // @[Reg.scala 27:20]
-  wire  _T_145 = _T_143 & cam_raw_0_bits_wb; // @[dec_decode_ctl.scala 379:105]
-  wire  _T_146 = cam_inv_reset_val_0 | _T_145; // @[dec_decode_ctl.scala 379:44]
-  wire  _GEN_110 = _T_146 ? 1'h0 : cam_0_valid; // @[dec_decode_ctl.scala 379:131]
-  wire [4:0] _GEN_111 = _T_146 ? 5'h0 : cam_raw_0_bits_rd; // @[dec_decode_ctl.scala 379:131]
-  wire [2:0] _GEN_112 = _T_146 ? 3'h0 : cam_raw_0_bits_tag; // @[dec_decode_ctl.scala 379:131]
-  wire  _GEN_113 = _T_146 ? 1'h0 : cam_raw_0_bits_wb; // @[dec_decode_ctl.scala 379:131]
-  wire  _GEN_114 = cam_wen[0] | _GEN_110; // @[dec_decode_ctl.scala 374:28]
-  wire  _GEN_115 = cam_wen[0] ? 1'h0 : _GEN_113; // @[dec_decode_ctl.scala 374:28]
-  wire [2:0] cam_in_0_bits_tag = cam_wen[0] ? {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_tag_m} : _GEN_112; // @[dec_decode_ctl.scala 374:28]
-  wire [4:0] cam_in_0_bits_rd = cam_wen[0] ? nonblock_load_rd : _GEN_111; // @[dec_decode_ctl.scala 374:28]
-  wire  _T_149 = nonblock_load_valid_m_delay & _T_130; // @[dec_decode_ctl.scala 384:44]
-  wire  _T_151 = _T_149 & cam_0_valid; // @[dec_decode_ctl.scala 384:113]
-  wire  cam_in_0_bits_wb = _T_151 | _GEN_115; // @[dec_decode_ctl.scala 384:135]
-  wire  cam_in_0_valid = io_dec_tlu_force_halt ? 1'h0 : _GEN_114; // @[dec_decode_ctl.scala 388:32]
+  wire  _T_145 = _T_143 & cam_raw_0_bits_wb; // @[dec_decode_ctl.scala 381:105]
+  wire  _T_146 = cam_inv_reset_val_0 | _T_145; // @[dec_decode_ctl.scala 381:44]
+  wire  _GEN_110 = _T_146 ? 1'h0 : cam_0_valid; // @[dec_decode_ctl.scala 381:131]
+  wire [4:0] _GEN_111 = _T_146 ? 5'h0 : cam_raw_0_bits_rd; // @[dec_decode_ctl.scala 381:131]
+  wire [2:0] _GEN_112 = _T_146 ? 3'h0 : cam_raw_0_bits_tag; // @[dec_decode_ctl.scala 381:131]
+  wire  _GEN_113 = _T_146 ? 1'h0 : cam_raw_0_bits_wb; // @[dec_decode_ctl.scala 381:131]
+  wire  _GEN_114 = cam_wen[0] | _GEN_110; // @[dec_decode_ctl.scala 376:28]
+  wire  _GEN_115 = cam_wen[0] ? 1'h0 : _GEN_113; // @[dec_decode_ctl.scala 376:28]
+  wire [2:0] cam_in_0_bits_tag = cam_wen[0] ? {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_tag_m} : _GEN_112; // @[dec_decode_ctl.scala 376:28]
+  wire [4:0] cam_in_0_bits_rd = cam_wen[0] ? nonblock_load_rd : _GEN_111; // @[dec_decode_ctl.scala 376:28]
+  wire  _T_149 = nonblock_load_valid_m_delay & _T_130; // @[dec_decode_ctl.scala 386:44]
+  wire  _T_151 = _T_149 & cam_0_valid; // @[dec_decode_ctl.scala 386:113]
+  wire  cam_in_0_bits_wb = _T_151 | _GEN_115; // @[dec_decode_ctl.scala 386:135]
+  wire  cam_in_0_valid = io_dec_tlu_force_halt ? 1'h0 : _GEN_114; // @[dec_decode_ctl.scala 390:32]
   wire [8:0] _T_154 = {cam_in_0_bits_wb,cam_in_0_bits_tag,cam_in_0_bits_rd}; // @[lib.scala 494:61]
   wire [8:0] _T_156 = {cam_raw_0_bits_wb,cam_raw_0_bits_tag,cam_raw_0_bits_rd}; // @[lib.scala 494:74]
   wire [8:0] _T_157 = _T_154 ^ _T_156; // @[lib.scala 494:68]
@@ -2422,28 +2422,28 @@ module dec_decode_ctl(
   wire  _T_159 = cam_in_0_valid ^ cam_raw_0_valid; // @[lib.scala 494:68]
   wire  _T_160 = |_T_159; // @[lib.scala 494:82]
   wire  _T_161 = _T_158 | _T_160; // @[lib.scala 494:97]
-  wire  nonblock_load_write_0 = _T_133 & cam_raw_0_valid; // @[dec_decode_ctl.scala 393:71]
-  wire  _T_166 = _GEN_263 == cam_raw_1_bits_tag; // @[dec_decode_ctl.scala 366:66]
-  wire  _T_167 = io_dctl_busbuff_lsu_nonblock_load_inv_r & _T_166; // @[dec_decode_ctl.scala 366:45]
-  wire  cam_inv_reset_val_1 = _T_167 & cam_1_valid; // @[dec_decode_ctl.scala 366:87]
+  wire  nonblock_load_write_0 = _T_133 & cam_raw_0_valid; // @[dec_decode_ctl.scala 395:71]
+  wire  _T_166 = _GEN_263 == cam_raw_1_bits_tag; // @[dec_decode_ctl.scala 368:66]
+  wire  _T_167 = io_dctl_busbuff_lsu_nonblock_load_inv_r & _T_166; // @[dec_decode_ctl.scala 368:45]
+  wire  cam_inv_reset_val_1 = _T_167 & cam_1_valid; // @[dec_decode_ctl.scala 368:87]
   reg [4:0] cam_raw_1_bits_rd; // @[Reg.scala 27:20]
-  wire  _T_178 = r_d_bits_i0rd == cam_raw_1_bits_rd; // @[dec_decode_ctl.scala 379:85]
-  wire  _T_179 = i0_wen_r & _T_178; // @[dec_decode_ctl.scala 379:64]
+  wire  _T_178 = r_d_bits_i0rd == cam_raw_1_bits_rd; // @[dec_decode_ctl.scala 381:85]
+  wire  _T_179 = i0_wen_r & _T_178; // @[dec_decode_ctl.scala 381:64]
   reg  cam_raw_1_bits_wb; // @[Reg.scala 27:20]
-  wire  _T_181 = _T_179 & cam_raw_1_bits_wb; // @[dec_decode_ctl.scala 379:105]
-  wire  _T_182 = cam_inv_reset_val_1 | _T_181; // @[dec_decode_ctl.scala 379:44]
-  wire  _GEN_125 = _T_182 ? 1'h0 : cam_1_valid; // @[dec_decode_ctl.scala 379:131]
-  wire [4:0] _GEN_126 = _T_182 ? 5'h0 : cam_raw_1_bits_rd; // @[dec_decode_ctl.scala 379:131]
-  wire [2:0] _GEN_127 = _T_182 ? 3'h0 : cam_raw_1_bits_tag; // @[dec_decode_ctl.scala 379:131]
-  wire  _GEN_128 = _T_182 ? 1'h0 : cam_raw_1_bits_wb; // @[dec_decode_ctl.scala 379:131]
-  wire  _GEN_129 = cam_wen[1] | _GEN_125; // @[dec_decode_ctl.scala 374:28]
-  wire  _GEN_130 = cam_wen[1] ? 1'h0 : _GEN_128; // @[dec_decode_ctl.scala 374:28]
-  wire [2:0] cam_in_1_bits_tag = cam_wen[1] ? {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_tag_m} : _GEN_127; // @[dec_decode_ctl.scala 374:28]
-  wire [4:0] cam_in_1_bits_rd = cam_wen[1] ? nonblock_load_rd : _GEN_126; // @[dec_decode_ctl.scala 374:28]
-  wire  _T_185 = nonblock_load_valid_m_delay & _T_166; // @[dec_decode_ctl.scala 384:44]
-  wire  _T_187 = _T_185 & cam_1_valid; // @[dec_decode_ctl.scala 384:113]
-  wire  cam_in_1_bits_wb = _T_187 | _GEN_130; // @[dec_decode_ctl.scala 384:135]
-  wire  cam_in_1_valid = io_dec_tlu_force_halt ? 1'h0 : _GEN_129; // @[dec_decode_ctl.scala 388:32]
+  wire  _T_181 = _T_179 & cam_raw_1_bits_wb; // @[dec_decode_ctl.scala 381:105]
+  wire  _T_182 = cam_inv_reset_val_1 | _T_181; // @[dec_decode_ctl.scala 381:44]
+  wire  _GEN_125 = _T_182 ? 1'h0 : cam_1_valid; // @[dec_decode_ctl.scala 381:131]
+  wire [4:0] _GEN_126 = _T_182 ? 5'h0 : cam_raw_1_bits_rd; // @[dec_decode_ctl.scala 381:131]
+  wire [2:0] _GEN_127 = _T_182 ? 3'h0 : cam_raw_1_bits_tag; // @[dec_decode_ctl.scala 381:131]
+  wire  _GEN_128 = _T_182 ? 1'h0 : cam_raw_1_bits_wb; // @[dec_decode_ctl.scala 381:131]
+  wire  _GEN_129 = cam_wen[1] | _GEN_125; // @[dec_decode_ctl.scala 376:28]
+  wire  _GEN_130 = cam_wen[1] ? 1'h0 : _GEN_128; // @[dec_decode_ctl.scala 376:28]
+  wire [2:0] cam_in_1_bits_tag = cam_wen[1] ? {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_tag_m} : _GEN_127; // @[dec_decode_ctl.scala 376:28]
+  wire [4:0] cam_in_1_bits_rd = cam_wen[1] ? nonblock_load_rd : _GEN_126; // @[dec_decode_ctl.scala 376:28]
+  wire  _T_185 = nonblock_load_valid_m_delay & _T_166; // @[dec_decode_ctl.scala 386:44]
+  wire  _T_187 = _T_185 & cam_1_valid; // @[dec_decode_ctl.scala 386:113]
+  wire  cam_in_1_bits_wb = _T_187 | _GEN_130; // @[dec_decode_ctl.scala 386:135]
+  wire  cam_in_1_valid = io_dec_tlu_force_halt ? 1'h0 : _GEN_129; // @[dec_decode_ctl.scala 390:32]
   wire [8:0] _T_190 = {cam_in_1_bits_wb,cam_in_1_bits_tag,cam_in_1_bits_rd}; // @[lib.scala 494:61]
   wire [8:0] _T_192 = {cam_raw_1_bits_wb,cam_raw_1_bits_tag,cam_raw_1_bits_rd}; // @[lib.scala 494:74]
   wire [8:0] _T_193 = _T_190 ^ _T_192; // @[lib.scala 494:68]
@@ -2451,28 +2451,28 @@ module dec_decode_ctl(
   wire  _T_195 = cam_in_1_valid ^ cam_raw_1_valid; // @[lib.scala 494:68]
   wire  _T_196 = |_T_195; // @[lib.scala 494:82]
   wire  _T_197 = _T_194 | _T_196; // @[lib.scala 494:97]
-  wire  nonblock_load_write_1 = _T_169 & cam_raw_1_valid; // @[dec_decode_ctl.scala 393:71]
-  wire  _T_202 = _GEN_263 == cam_raw_2_bits_tag; // @[dec_decode_ctl.scala 366:66]
-  wire  _T_203 = io_dctl_busbuff_lsu_nonblock_load_inv_r & _T_202; // @[dec_decode_ctl.scala 366:45]
-  wire  cam_inv_reset_val_2 = _T_203 & cam_2_valid; // @[dec_decode_ctl.scala 366:87]
+  wire  nonblock_load_write_1 = _T_169 & cam_raw_1_valid; // @[dec_decode_ctl.scala 395:71]
+  wire  _T_202 = _GEN_263 == cam_raw_2_bits_tag; // @[dec_decode_ctl.scala 368:66]
+  wire  _T_203 = io_dctl_busbuff_lsu_nonblock_load_inv_r & _T_202; // @[dec_decode_ctl.scala 368:45]
+  wire  cam_inv_reset_val_2 = _T_203 & cam_2_valid; // @[dec_decode_ctl.scala 368:87]
   reg [4:0] cam_raw_2_bits_rd; // @[Reg.scala 27:20]
-  wire  _T_214 = r_d_bits_i0rd == cam_raw_2_bits_rd; // @[dec_decode_ctl.scala 379:85]
-  wire  _T_215 = i0_wen_r & _T_214; // @[dec_decode_ctl.scala 379:64]
+  wire  _T_214 = r_d_bits_i0rd == cam_raw_2_bits_rd; // @[dec_decode_ctl.scala 381:85]
+  wire  _T_215 = i0_wen_r & _T_214; // @[dec_decode_ctl.scala 381:64]
   reg  cam_raw_2_bits_wb; // @[Reg.scala 27:20]
-  wire  _T_217 = _T_215 & cam_raw_2_bits_wb; // @[dec_decode_ctl.scala 379:105]
-  wire  _T_218 = cam_inv_reset_val_2 | _T_217; // @[dec_decode_ctl.scala 379:44]
-  wire  _GEN_140 = _T_218 ? 1'h0 : cam_2_valid; // @[dec_decode_ctl.scala 379:131]
-  wire [4:0] _GEN_141 = _T_218 ? 5'h0 : cam_raw_2_bits_rd; // @[dec_decode_ctl.scala 379:131]
-  wire [2:0] _GEN_142 = _T_218 ? 3'h0 : cam_raw_2_bits_tag; // @[dec_decode_ctl.scala 379:131]
-  wire  _GEN_143 = _T_218 ? 1'h0 : cam_raw_2_bits_wb; // @[dec_decode_ctl.scala 379:131]
-  wire  _GEN_144 = cam_wen[2] | _GEN_140; // @[dec_decode_ctl.scala 374:28]
-  wire  _GEN_145 = cam_wen[2] ? 1'h0 : _GEN_143; // @[dec_decode_ctl.scala 374:28]
-  wire [2:0] cam_in_2_bits_tag = cam_wen[2] ? {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_tag_m} : _GEN_142; // @[dec_decode_ctl.scala 374:28]
-  wire [4:0] cam_in_2_bits_rd = cam_wen[2] ? nonblock_load_rd : _GEN_141; // @[dec_decode_ctl.scala 374:28]
-  wire  _T_221 = nonblock_load_valid_m_delay & _T_202; // @[dec_decode_ctl.scala 384:44]
-  wire  _T_223 = _T_221 & cam_2_valid; // @[dec_decode_ctl.scala 384:113]
-  wire  cam_in_2_bits_wb = _T_223 | _GEN_145; // @[dec_decode_ctl.scala 384:135]
-  wire  cam_in_2_valid = io_dec_tlu_force_halt ? 1'h0 : _GEN_144; // @[dec_decode_ctl.scala 388:32]
+  wire  _T_217 = _T_215 & cam_raw_2_bits_wb; // @[dec_decode_ctl.scala 381:105]
+  wire  _T_218 = cam_inv_reset_val_2 | _T_217; // @[dec_decode_ctl.scala 381:44]
+  wire  _GEN_140 = _T_218 ? 1'h0 : cam_2_valid; // @[dec_decode_ctl.scala 381:131]
+  wire [4:0] _GEN_141 = _T_218 ? 5'h0 : cam_raw_2_bits_rd; // @[dec_decode_ctl.scala 381:131]
+  wire [2:0] _GEN_142 = _T_218 ? 3'h0 : cam_raw_2_bits_tag; // @[dec_decode_ctl.scala 381:131]
+  wire  _GEN_143 = _T_218 ? 1'h0 : cam_raw_2_bits_wb; // @[dec_decode_ctl.scala 381:131]
+  wire  _GEN_144 = cam_wen[2] | _GEN_140; // @[dec_decode_ctl.scala 376:28]
+  wire  _GEN_145 = cam_wen[2] ? 1'h0 : _GEN_143; // @[dec_decode_ctl.scala 376:28]
+  wire [2:0] cam_in_2_bits_tag = cam_wen[2] ? {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_tag_m} : _GEN_142; // @[dec_decode_ctl.scala 376:28]
+  wire [4:0] cam_in_2_bits_rd = cam_wen[2] ? nonblock_load_rd : _GEN_141; // @[dec_decode_ctl.scala 376:28]
+  wire  _T_221 = nonblock_load_valid_m_delay & _T_202; // @[dec_decode_ctl.scala 386:44]
+  wire  _T_223 = _T_221 & cam_2_valid; // @[dec_decode_ctl.scala 386:113]
+  wire  cam_in_2_bits_wb = _T_223 | _GEN_145; // @[dec_decode_ctl.scala 386:135]
+  wire  cam_in_2_valid = io_dec_tlu_force_halt ? 1'h0 : _GEN_144; // @[dec_decode_ctl.scala 390:32]
   wire [8:0] _T_226 = {cam_in_2_bits_wb,cam_in_2_bits_tag,cam_in_2_bits_rd}; // @[lib.scala 494:61]
   wire [8:0] _T_228 = {cam_raw_2_bits_wb,cam_raw_2_bits_tag,cam_raw_2_bits_rd}; // @[lib.scala 494:74]
   wire [8:0] _T_229 = _T_226 ^ _T_228; // @[lib.scala 494:68]
@@ -2480,28 +2480,28 @@ module dec_decode_ctl(
   wire  _T_231 = cam_in_2_valid ^ cam_raw_2_valid; // @[lib.scala 494:68]
   wire  _T_232 = |_T_231; // @[lib.scala 494:82]
   wire  _T_233 = _T_230 | _T_232; // @[lib.scala 494:97]
-  wire  nonblock_load_write_2 = _T_205 & cam_raw_2_valid; // @[dec_decode_ctl.scala 393:71]
-  wire  _T_238 = _GEN_263 == cam_raw_3_bits_tag; // @[dec_decode_ctl.scala 366:66]
-  wire  _T_239 = io_dctl_busbuff_lsu_nonblock_load_inv_r & _T_238; // @[dec_decode_ctl.scala 366:45]
-  wire  cam_inv_reset_val_3 = _T_239 & cam_3_valid; // @[dec_decode_ctl.scala 366:87]
+  wire  nonblock_load_write_2 = _T_205 & cam_raw_2_valid; // @[dec_decode_ctl.scala 395:71]
+  wire  _T_238 = _GEN_263 == cam_raw_3_bits_tag; // @[dec_decode_ctl.scala 368:66]
+  wire  _T_239 = io_dctl_busbuff_lsu_nonblock_load_inv_r & _T_238; // @[dec_decode_ctl.scala 368:45]
+  wire  cam_inv_reset_val_3 = _T_239 & cam_3_valid; // @[dec_decode_ctl.scala 368:87]
   reg [4:0] cam_raw_3_bits_rd; // @[Reg.scala 27:20]
-  wire  _T_250 = r_d_bits_i0rd == cam_raw_3_bits_rd; // @[dec_decode_ctl.scala 379:85]
-  wire  _T_251 = i0_wen_r & _T_250; // @[dec_decode_ctl.scala 379:64]
+  wire  _T_250 = r_d_bits_i0rd == cam_raw_3_bits_rd; // @[dec_decode_ctl.scala 381:85]
+  wire  _T_251 = i0_wen_r & _T_250; // @[dec_decode_ctl.scala 381:64]
   reg  cam_raw_3_bits_wb; // @[Reg.scala 27:20]
-  wire  _T_253 = _T_251 & cam_raw_3_bits_wb; // @[dec_decode_ctl.scala 379:105]
-  wire  _T_254 = cam_inv_reset_val_3 | _T_253; // @[dec_decode_ctl.scala 379:44]
-  wire  _GEN_155 = _T_254 ? 1'h0 : cam_3_valid; // @[dec_decode_ctl.scala 379:131]
-  wire [4:0] _GEN_156 = _T_254 ? 5'h0 : cam_raw_3_bits_rd; // @[dec_decode_ctl.scala 379:131]
-  wire [2:0] _GEN_157 = _T_254 ? 3'h0 : cam_raw_3_bits_tag; // @[dec_decode_ctl.scala 379:131]
-  wire  _GEN_158 = _T_254 ? 1'h0 : cam_raw_3_bits_wb; // @[dec_decode_ctl.scala 379:131]
-  wire  _GEN_159 = cam_wen[3] | _GEN_155; // @[dec_decode_ctl.scala 374:28]
-  wire  _GEN_160 = cam_wen[3] ? 1'h0 : _GEN_158; // @[dec_decode_ctl.scala 374:28]
-  wire [2:0] cam_in_3_bits_tag = cam_wen[3] ? {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_tag_m} : _GEN_157; // @[dec_decode_ctl.scala 374:28]
-  wire [4:0] cam_in_3_bits_rd = cam_wen[3] ? nonblock_load_rd : _GEN_156; // @[dec_decode_ctl.scala 374:28]
-  wire  _T_257 = nonblock_load_valid_m_delay & _T_238; // @[dec_decode_ctl.scala 384:44]
-  wire  _T_259 = _T_257 & cam_3_valid; // @[dec_decode_ctl.scala 384:113]
-  wire  cam_in_3_bits_wb = _T_259 | _GEN_160; // @[dec_decode_ctl.scala 384:135]
-  wire  cam_in_3_valid = io_dec_tlu_force_halt ? 1'h0 : _GEN_159; // @[dec_decode_ctl.scala 388:32]
+  wire  _T_253 = _T_251 & cam_raw_3_bits_wb; // @[dec_decode_ctl.scala 381:105]
+  wire  _T_254 = cam_inv_reset_val_3 | _T_253; // @[dec_decode_ctl.scala 381:44]
+  wire  _GEN_155 = _T_254 ? 1'h0 : cam_3_valid; // @[dec_decode_ctl.scala 381:131]
+  wire [4:0] _GEN_156 = _T_254 ? 5'h0 : cam_raw_3_bits_rd; // @[dec_decode_ctl.scala 381:131]
+  wire [2:0] _GEN_157 = _T_254 ? 3'h0 : cam_raw_3_bits_tag; // @[dec_decode_ctl.scala 381:131]
+  wire  _GEN_158 = _T_254 ? 1'h0 : cam_raw_3_bits_wb; // @[dec_decode_ctl.scala 381:131]
+  wire  _GEN_159 = cam_wen[3] | _GEN_155; // @[dec_decode_ctl.scala 376:28]
+  wire  _GEN_160 = cam_wen[3] ? 1'h0 : _GEN_158; // @[dec_decode_ctl.scala 376:28]
+  wire [2:0] cam_in_3_bits_tag = cam_wen[3] ? {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_tag_m} : _GEN_157; // @[dec_decode_ctl.scala 376:28]
+  wire [4:0] cam_in_3_bits_rd = cam_wen[3] ? nonblock_load_rd : _GEN_156; // @[dec_decode_ctl.scala 376:28]
+  wire  _T_257 = nonblock_load_valid_m_delay & _T_238; // @[dec_decode_ctl.scala 386:44]
+  wire  _T_259 = _T_257 & cam_3_valid; // @[dec_decode_ctl.scala 386:113]
+  wire  cam_in_3_bits_wb = _T_259 | _GEN_160; // @[dec_decode_ctl.scala 386:135]
+  wire  cam_in_3_valid = io_dec_tlu_force_halt ? 1'h0 : _GEN_159; // @[dec_decode_ctl.scala 390:32]
   wire [8:0] _T_262 = {cam_in_3_bits_wb,cam_in_3_bits_tag,cam_in_3_bits_rd}; // @[lib.scala 494:61]
   wire [8:0] _T_264 = {cam_raw_3_bits_wb,cam_raw_3_bits_tag,cam_raw_3_bits_rd}; // @[lib.scala 494:74]
   wire [8:0] _T_265 = _T_262 ^ _T_264; // @[lib.scala 494:68]
@@ -2509,80 +2509,80 @@ module dec_decode_ctl(
   wire  _T_267 = cam_in_3_valid ^ cam_raw_3_valid; // @[lib.scala 494:68]
   wire  _T_268 = |_T_267; // @[lib.scala 494:82]
   wire  _T_269 = _T_266 | _T_268; // @[lib.scala 494:97]
-  wire  nonblock_load_write_3 = _T_241 & cam_raw_3_valid; // @[dec_decode_ctl.scala 393:71]
-  wire  _T_274 = r_d_bits_i0rd == io_dec_nonblock_load_waddr; // @[dec_decode_ctl.scala 398:49]
-  wire  nonblock_load_cancel = _T_274 & i0_wen_r; // @[dec_decode_ctl.scala 398:81]
-  wire  _T_275 = nonblock_load_write_0 | nonblock_load_write_1; // @[dec_decode_ctl.scala 399:108]
-  wire  _T_276 = _T_275 | nonblock_load_write_2; // @[dec_decode_ctl.scala 399:108]
-  wire  _T_277 = _T_276 | nonblock_load_write_3; // @[dec_decode_ctl.scala 399:108]
-  wire  _T_279 = io_dctl_busbuff_lsu_nonblock_load_data_valid & _T_277; // @[dec_decode_ctl.scala 399:77]
-  wire  _T_280 = ~nonblock_load_cancel; // @[dec_decode_ctl.scala 399:122]
-  wire  _T_282 = nonblock_load_rd == i0r_rs1; // @[dec_decode_ctl.scala 400:54]
-  wire  _T_283 = _T_282 & io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[dec_decode_ctl.scala 400:66]
-  wire  _T_284 = _T_283 & io_decode_exu_dec_i0_rs1_en_d; // @[dec_decode_ctl.scala 400:110]
-  wire [4:0] i0r_rs2 = io_dec_i0_instr_d[24:20]; // @[dec_decode_ctl.scala 677:16]
-  wire  _T_285 = nonblock_load_rd == i0r_rs2; // @[dec_decode_ctl.scala 400:161]
-  wire  _T_286 = _T_285 & io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[dec_decode_ctl.scala 400:173]
-  wire  _T_287 = _T_286 & io_decode_exu_dec_i0_rs2_en_d; // @[dec_decode_ctl.scala 400:217]
-  wire  i0_nonblock_boundary_stall = _T_284 | _T_287; // @[dec_decode_ctl.scala 400:142]
+  wire  nonblock_load_write_3 = _T_241 & cam_raw_3_valid; // @[dec_decode_ctl.scala 395:71]
+  wire  _T_274 = r_d_bits_i0rd == io_dec_nonblock_load_waddr; // @[dec_decode_ctl.scala 400:49]
+  wire  nonblock_load_cancel = _T_274 & i0_wen_r; // @[dec_decode_ctl.scala 400:81]
+  wire  _T_275 = nonblock_load_write_0 | nonblock_load_write_1; // @[dec_decode_ctl.scala 401:108]
+  wire  _T_276 = _T_275 | nonblock_load_write_2; // @[dec_decode_ctl.scala 401:108]
+  wire  _T_277 = _T_276 | nonblock_load_write_3; // @[dec_decode_ctl.scala 401:108]
+  wire  _T_279 = io_dctl_busbuff_lsu_nonblock_load_data_valid & _T_277; // @[dec_decode_ctl.scala 401:77]
+  wire  _T_280 = ~nonblock_load_cancel; // @[dec_decode_ctl.scala 401:122]
+  wire  _T_282 = nonblock_load_rd == i0r_rs1; // @[dec_decode_ctl.scala 402:54]
+  wire  _T_283 = _T_282 & io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[dec_decode_ctl.scala 402:66]
+  wire  _T_284 = _T_283 & io_decode_exu_dec_i0_rs1_en_d; // @[dec_decode_ctl.scala 402:110]
+  wire [4:0] i0r_rs2 = io_dec_i0_instr_d[24:20]; // @[dec_decode_ctl.scala 679:16]
+  wire  _T_285 = nonblock_load_rd == i0r_rs2; // @[dec_decode_ctl.scala 402:161]
+  wire  _T_286 = _T_285 & io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[dec_decode_ctl.scala 402:173]
+  wire  _T_287 = _T_286 & io_decode_exu_dec_i0_rs2_en_d; // @[dec_decode_ctl.scala 402:217]
+  wire  i0_nonblock_boundary_stall = _T_284 | _T_287; // @[dec_decode_ctl.scala 402:142]
   wire [4:0] _T_289 = nonblock_load_write_0 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12]
-  wire [4:0] _T_290 = _T_289 & cam_raw_0_bits_rd; // @[dec_decode_ctl.scala 404:88]
-  wire  _T_291 = io_decode_exu_dec_i0_rs1_en_d & cam_0_valid; // @[dec_decode_ctl.scala 404:137]
-  wire  _T_292 = cam_raw_0_bits_rd == i0r_rs1; // @[dec_decode_ctl.scala 404:170]
-  wire  _T_293 = _T_291 & _T_292; // @[dec_decode_ctl.scala 404:152]
-  wire  _T_294 = io_decode_exu_dec_i0_rs2_en_d & cam_0_valid; // @[dec_decode_ctl.scala 404:214]
-  wire  _T_295 = cam_raw_0_bits_rd == i0r_rs2; // @[dec_decode_ctl.scala 404:247]
-  wire  _T_296 = _T_294 & _T_295; // @[dec_decode_ctl.scala 404:229]
+  wire [4:0] _T_290 = _T_289 & cam_raw_0_bits_rd; // @[dec_decode_ctl.scala 406:88]
+  wire  _T_291 = io_decode_exu_dec_i0_rs1_en_d & cam_0_valid; // @[dec_decode_ctl.scala 406:137]
+  wire  _T_292 = cam_raw_0_bits_rd == i0r_rs1; // @[dec_decode_ctl.scala 406:170]
+  wire  _T_293 = _T_291 & _T_292; // @[dec_decode_ctl.scala 406:152]
+  wire  _T_294 = io_decode_exu_dec_i0_rs2_en_d & cam_0_valid; // @[dec_decode_ctl.scala 406:214]
+  wire  _T_295 = cam_raw_0_bits_rd == i0r_rs2; // @[dec_decode_ctl.scala 406:247]
+  wire  _T_296 = _T_294 & _T_295; // @[dec_decode_ctl.scala 406:229]
   wire [4:0] _T_298 = nonblock_load_write_1 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12]
-  wire [4:0] _T_299 = _T_298 & cam_raw_1_bits_rd; // @[dec_decode_ctl.scala 404:88]
-  wire  _T_300 = io_decode_exu_dec_i0_rs1_en_d & cam_1_valid; // @[dec_decode_ctl.scala 404:137]
-  wire  _T_301 = cam_raw_1_bits_rd == i0r_rs1; // @[dec_decode_ctl.scala 404:170]
-  wire  _T_302 = _T_300 & _T_301; // @[dec_decode_ctl.scala 404:152]
-  wire  _T_303 = io_decode_exu_dec_i0_rs2_en_d & cam_1_valid; // @[dec_decode_ctl.scala 404:214]
-  wire  _T_304 = cam_raw_1_bits_rd == i0r_rs2; // @[dec_decode_ctl.scala 404:247]
-  wire  _T_305 = _T_303 & _T_304; // @[dec_decode_ctl.scala 404:229]
+  wire [4:0] _T_299 = _T_298 & cam_raw_1_bits_rd; // @[dec_decode_ctl.scala 406:88]
+  wire  _T_300 = io_decode_exu_dec_i0_rs1_en_d & cam_1_valid; // @[dec_decode_ctl.scala 406:137]
+  wire  _T_301 = cam_raw_1_bits_rd == i0r_rs1; // @[dec_decode_ctl.scala 406:170]
+  wire  _T_302 = _T_300 & _T_301; // @[dec_decode_ctl.scala 406:152]
+  wire  _T_303 = io_decode_exu_dec_i0_rs2_en_d & cam_1_valid; // @[dec_decode_ctl.scala 406:214]
+  wire  _T_304 = cam_raw_1_bits_rd == i0r_rs2; // @[dec_decode_ctl.scala 406:247]
+  wire  _T_305 = _T_303 & _T_304; // @[dec_decode_ctl.scala 406:229]
   wire [4:0] _T_307 = nonblock_load_write_2 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12]
-  wire [4:0] _T_308 = _T_307 & cam_raw_2_bits_rd; // @[dec_decode_ctl.scala 404:88]
-  wire  _T_309 = io_decode_exu_dec_i0_rs1_en_d & cam_2_valid; // @[dec_decode_ctl.scala 404:137]
-  wire  _T_310 = cam_raw_2_bits_rd == i0r_rs1; // @[dec_decode_ctl.scala 404:170]
-  wire  _T_311 = _T_309 & _T_310; // @[dec_decode_ctl.scala 404:152]
-  wire  _T_312 = io_decode_exu_dec_i0_rs2_en_d & cam_2_valid; // @[dec_decode_ctl.scala 404:214]
-  wire  _T_313 = cam_raw_2_bits_rd == i0r_rs2; // @[dec_decode_ctl.scala 404:247]
-  wire  _T_314 = _T_312 & _T_313; // @[dec_decode_ctl.scala 404:229]
+  wire [4:0] _T_308 = _T_307 & cam_raw_2_bits_rd; // @[dec_decode_ctl.scala 406:88]
+  wire  _T_309 = io_decode_exu_dec_i0_rs1_en_d & cam_2_valid; // @[dec_decode_ctl.scala 406:137]
+  wire  _T_310 = cam_raw_2_bits_rd == i0r_rs1; // @[dec_decode_ctl.scala 406:170]
+  wire  _T_311 = _T_309 & _T_310; // @[dec_decode_ctl.scala 406:152]
+  wire  _T_312 = io_decode_exu_dec_i0_rs2_en_d & cam_2_valid; // @[dec_decode_ctl.scala 406:214]
+  wire  _T_313 = cam_raw_2_bits_rd == i0r_rs2; // @[dec_decode_ctl.scala 406:247]
+  wire  _T_314 = _T_312 & _T_313; // @[dec_decode_ctl.scala 406:229]
   wire [4:0] _T_316 = nonblock_load_write_3 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12]
-  wire [4:0] _T_317 = _T_316 & cam_raw_3_bits_rd; // @[dec_decode_ctl.scala 404:88]
-  wire  _T_318 = io_decode_exu_dec_i0_rs1_en_d & cam_3_valid; // @[dec_decode_ctl.scala 404:137]
-  wire  _T_319 = cam_raw_3_bits_rd == i0r_rs1; // @[dec_decode_ctl.scala 404:170]
-  wire  _T_320 = _T_318 & _T_319; // @[dec_decode_ctl.scala 404:152]
-  wire  _T_321 = io_decode_exu_dec_i0_rs2_en_d & cam_3_valid; // @[dec_decode_ctl.scala 404:214]
-  wire  _T_322 = cam_raw_3_bits_rd == i0r_rs2; // @[dec_decode_ctl.scala 404:247]
-  wire  _T_323 = _T_321 & _T_322; // @[dec_decode_ctl.scala 404:229]
-  wire [4:0] _T_324 = _T_290 | _T_299; // @[dec_decode_ctl.scala 405:69]
-  wire [4:0] _T_325 = _T_324 | _T_308; // @[dec_decode_ctl.scala 405:69]
-  wire  _T_326 = _T_293 | _T_302; // @[dec_decode_ctl.scala 405:102]
-  wire  _T_327 = _T_326 | _T_311; // @[dec_decode_ctl.scala 405:102]
-  wire  ld_stall_1 = _T_327 | _T_320; // @[dec_decode_ctl.scala 405:102]
-  wire  _T_328 = _T_296 | _T_305; // @[dec_decode_ctl.scala 405:134]
-  wire  _T_329 = _T_328 | _T_314; // @[dec_decode_ctl.scala 405:134]
-  wire  ld_stall_2 = _T_329 | _T_323; // @[dec_decode_ctl.scala 405:134]
-  wire  _T_330 = ld_stall_1 | ld_stall_2; // @[dec_decode_ctl.scala 407:38]
-  wire  i0_nonblock_load_stall = _T_330 | i0_nonblock_boundary_stall; // @[dec_decode_ctl.scala 407:51]
-  wire  _T_332 = ~i0_predict_br; // @[dec_decode_ctl.scala 416:34]
-  wire  i0_br_unpred = i0_dp_jal & _T_332; // @[dec_decode_ctl.scala 416:32]
+  wire [4:0] _T_317 = _T_316 & cam_raw_3_bits_rd; // @[dec_decode_ctl.scala 406:88]
+  wire  _T_318 = io_decode_exu_dec_i0_rs1_en_d & cam_3_valid; // @[dec_decode_ctl.scala 406:137]
+  wire  _T_319 = cam_raw_3_bits_rd == i0r_rs1; // @[dec_decode_ctl.scala 406:170]
+  wire  _T_320 = _T_318 & _T_319; // @[dec_decode_ctl.scala 406:152]
+  wire  _T_321 = io_decode_exu_dec_i0_rs2_en_d & cam_3_valid; // @[dec_decode_ctl.scala 406:214]
+  wire  _T_322 = cam_raw_3_bits_rd == i0r_rs2; // @[dec_decode_ctl.scala 406:247]
+  wire  _T_323 = _T_321 & _T_322; // @[dec_decode_ctl.scala 406:229]
+  wire [4:0] _T_324 = _T_290 | _T_299; // @[dec_decode_ctl.scala 407:69]
+  wire [4:0] _T_325 = _T_324 | _T_308; // @[dec_decode_ctl.scala 407:69]
+  wire  _T_326 = _T_293 | _T_302; // @[dec_decode_ctl.scala 407:102]
+  wire  _T_327 = _T_326 | _T_311; // @[dec_decode_ctl.scala 407:102]
+  wire  ld_stall_1 = _T_327 | _T_320; // @[dec_decode_ctl.scala 407:102]
+  wire  _T_328 = _T_296 | _T_305; // @[dec_decode_ctl.scala 407:134]
+  wire  _T_329 = _T_328 | _T_314; // @[dec_decode_ctl.scala 407:134]
+  wire  ld_stall_2 = _T_329 | _T_323; // @[dec_decode_ctl.scala 407:134]
+  wire  _T_330 = ld_stall_1 | ld_stall_2; // @[dec_decode_ctl.scala 409:38]
+  wire  i0_nonblock_load_stall = _T_330 | i0_nonblock_boundary_stall; // @[dec_decode_ctl.scala 409:51]
+  wire  _T_332 = ~i0_predict_br; // @[dec_decode_ctl.scala 418:34]
+  wire  i0_br_unpred = i0_dp_jal & _T_332; // @[dec_decode_ctl.scala 418:32]
   wire [3:0] _T_334 = i0_legal_decode_d ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
-  wire  csr_read = i0_dp_csr_read & i0_legal_decode_d; // @[dec_decode_ctl.scala 517:36]
-  wire  _T_335 = csr_read & io_dec_csr_wen_unq_d; // @[dec_decode_ctl.scala 428:16]
-  wire  _T_337 = ~csr_read; // @[dec_decode_ctl.scala 429:6]
-  wire  _T_338 = _T_337 & io_dec_csr_wen_unq_d; // @[dec_decode_ctl.scala 429:16]
-  wire  _T_340 = ~io_dec_csr_wen_unq_d; // @[dec_decode_ctl.scala 430:18]
-  wire  _T_341 = csr_read & _T_340; // @[dec_decode_ctl.scala 430:16]
-  wire  _T_343 = i0_dp_zbb | i0_dp_zbs; // @[dec_decode_ctl.scala 431:16]
-  wire  _T_344 = _T_343 | i0_dp_zbe; // @[dec_decode_ctl.scala 431:28]
-  wire  _T_345 = _T_344 | i0_dp_zbc; // @[dec_decode_ctl.scala 431:40]
-  wire  _T_346 = _T_345 | i0_dp_zbp; // @[dec_decode_ctl.scala 431:52]
-  wire  _T_347 = _T_346 | i0_dp_zbr; // @[dec_decode_ctl.scala 431:65]
-  wire  _T_348 = _T_347 | i0_dp_zbf; // @[dec_decode_ctl.scala 431:77]
-  wire  _T_349 = _T_348 | i0_dp_zba; // @[dec_decode_ctl.scala 431:89]
+  wire  csr_read = i0_dp_csr_read & i0_legal_decode_d; // @[dec_decode_ctl.scala 519:36]
+  wire  _T_335 = csr_read & io_dec_csr_wen_unq_d; // @[dec_decode_ctl.scala 430:16]
+  wire  _T_337 = ~csr_read; // @[dec_decode_ctl.scala 431:6]
+  wire  _T_338 = _T_337 & io_dec_csr_wen_unq_d; // @[dec_decode_ctl.scala 431:16]
+  wire  _T_340 = ~io_dec_csr_wen_unq_d; // @[dec_decode_ctl.scala 432:18]
+  wire  _T_341 = csr_read & _T_340; // @[dec_decode_ctl.scala 432:16]
+  wire  _T_343 = i0_dp_zbb | i0_dp_zbs; // @[dec_decode_ctl.scala 433:16]
+  wire  _T_344 = _T_343 | i0_dp_zbe; // @[dec_decode_ctl.scala 433:28]
+  wire  _T_345 = _T_344 | i0_dp_zbc; // @[dec_decode_ctl.scala 433:40]
+  wire  _T_346 = _T_345 | i0_dp_zbp; // @[dec_decode_ctl.scala 433:52]
+  wire  _T_347 = _T_346 | i0_dp_zbr; // @[dec_decode_ctl.scala 433:65]
+  wire  _T_348 = _T_347 | i0_dp_zbf; // @[dec_decode_ctl.scala 433:77]
+  wire  _T_349 = _T_348 | i0_dp_zba; // @[dec_decode_ctl.scala 433:89]
   wire [3:0] _T_350 = i0_dp_mul ? 4'h1 : 4'h0; // @[Mux.scala 98:16]
   wire [3:0] _T_351 = i0_dp_load ? 4'h2 : _T_350; // @[Mux.scala 98:16]
   wire [3:0] _T_352 = i0_dp_store ? 4'h3 : _T_351; // @[Mux.scala 98:16]
@@ -2598,155 +2598,155 @@ module dec_decode_ctl(
   wire [3:0] _T_362 = i0_dp_mret ? 4'hc : _T_361; // @[Mux.scala 98:16]
   wire [3:0] _T_363 = i0_dp_condbr ? 4'hd : _T_362; // @[Mux.scala 98:16]
   wire [3:0] _T_364 = i0_dp_jal ? 4'he : _T_363; // @[Mux.scala 98:16]
-  wire [3:0] d_t_pmu_i0_itype = _T_334 & _T_364; // @[dec_decode_ctl.scala 420:49]
-  reg  lsu_idle; // @[dec_decode_ctl.scala 442:45]
-  wire  _T_418 = ~i0_pcall_case; // @[dec_decode_ctl.scala 464:35]
-  wire  _T_419 = i0_dp_jal & _T_418; // @[dec_decode_ctl.scala 464:32]
-  wire  _T_420 = ~i0_pja_case; // @[dec_decode_ctl.scala 464:52]
-  wire  _T_421 = _T_419 & _T_420; // @[dec_decode_ctl.scala 464:50]
-  wire  _T_422 = ~i0_pret_case; // @[dec_decode_ctl.scala 464:67]
-  wire  _T_425 = i0r_rs1 == 5'h2; // @[dec_decode_ctl.scala 508:41]
-  wire  lsu_decode_d = i0_legal_decode_d & i0_dp_lsu; // @[dec_decode_ctl.scala 633:40]
-  wire  _T_1018 = i0_dp_load | i0_dp_store; // @[dec_decode_ctl.scala 901:43]
+  wire [3:0] d_t_pmu_i0_itype = _T_334 & _T_364; // @[dec_decode_ctl.scala 422:49]
+  reg  lsu_idle; // @[dec_decode_ctl.scala 444:45]
+  wire  _T_418 = ~i0_pcall_case; // @[dec_decode_ctl.scala 466:35]
+  wire  _T_419 = i0_dp_jal & _T_418; // @[dec_decode_ctl.scala 466:32]
+  wire  _T_420 = ~i0_pja_case; // @[dec_decode_ctl.scala 466:52]
+  wire  _T_421 = _T_419 & _T_420; // @[dec_decode_ctl.scala 466:50]
+  wire  _T_422 = ~i0_pret_case; // @[dec_decode_ctl.scala 466:67]
+  wire  _T_425 = i0r_rs1 == 5'h2; // @[dec_decode_ctl.scala 510:41]
+  wire  lsu_decode_d = i0_legal_decode_d & i0_dp_lsu; // @[dec_decode_ctl.scala 635:40]
+  wire  _T_1018 = i0_dp_load | i0_dp_store; // @[dec_decode_ctl.scala 903:43]
   reg  x_d_bits_i0v; // @[Reg.scala 27:20]
-  wire  _T_992 = io_decode_exu_dec_i0_rs1_en_d & x_d_bits_i0v; // @[dec_decode_ctl.scala 881:59]
-  wire  _T_993 = x_d_bits_i0rd == i0r_rs1; // @[dec_decode_ctl.scala 881:91]
-  wire  i0_rs1_depend_i0_x = _T_992 & _T_993; // @[dec_decode_ctl.scala 881:74]
-  wire  _T_994 = io_decode_exu_dec_i0_rs1_en_d & r_d_bits_i0v; // @[dec_decode_ctl.scala 882:59]
-  wire  _T_995 = r_d_bits_i0rd == i0r_rs1; // @[dec_decode_ctl.scala 882:91]
-  wire  i0_rs1_depend_i0_r = _T_994 & _T_995; // @[dec_decode_ctl.scala 882:74]
-  wire [1:0] _T_1007 = i0_rs1_depend_i0_r ? 2'h2 : 2'h0; // @[dec_decode_ctl.scala 888:63]
-  wire [1:0] i0_rs1_depth_d = i0_rs1_depend_i0_x ? 2'h1 : _T_1007; // @[dec_decode_ctl.scala 888:24]
-  wire  _T_1020 = _T_1018 & i0_rs1_depth_d[0]; // @[dec_decode_ctl.scala 901:58]
+  wire  _T_992 = io_decode_exu_dec_i0_rs1_en_d & x_d_bits_i0v; // @[dec_decode_ctl.scala 883:59]
+  wire  _T_993 = x_d_bits_i0rd == i0r_rs1; // @[dec_decode_ctl.scala 883:91]
+  wire  i0_rs1_depend_i0_x = _T_992 & _T_993; // @[dec_decode_ctl.scala 883:74]
+  wire  _T_994 = io_decode_exu_dec_i0_rs1_en_d & r_d_bits_i0v; // @[dec_decode_ctl.scala 884:59]
+  wire  _T_995 = r_d_bits_i0rd == i0r_rs1; // @[dec_decode_ctl.scala 884:91]
+  wire  i0_rs1_depend_i0_r = _T_994 & _T_995; // @[dec_decode_ctl.scala 884:74]
+  wire [1:0] _T_1007 = i0_rs1_depend_i0_r ? 2'h2 : 2'h0; // @[dec_decode_ctl.scala 890:63]
+  wire [1:0] i0_rs1_depth_d = i0_rs1_depend_i0_x ? 2'h1 : _T_1007; // @[dec_decode_ctl.scala 890:24]
+  wire  _T_1020 = _T_1018 & i0_rs1_depth_d[0]; // @[dec_decode_ctl.scala 903:58]
   reg  i0_x_c_load; // @[Reg.scala 27:20]
   reg  i0_r_c_load; // @[Reg.scala 27:20]
-  wire  _T_1003_load = i0_rs1_depend_i0_r & i0_r_c_load; // @[dec_decode_ctl.scala 887:61]
-  wire  i0_rs1_class_d_load = i0_rs1_depend_i0_x ? i0_x_c_load : _T_1003_load; // @[dec_decode_ctl.scala 887:24]
-  wire  load_ldst_bypass_d = _T_1020 & i0_rs1_class_d_load; // @[dec_decode_ctl.scala 901:78]
-  wire  _T_996 = io_decode_exu_dec_i0_rs2_en_d & x_d_bits_i0v; // @[dec_decode_ctl.scala 884:59]
-  wire  _T_997 = x_d_bits_i0rd == i0r_rs2; // @[dec_decode_ctl.scala 884:91]
-  wire  i0_rs2_depend_i0_x = _T_996 & _T_997; // @[dec_decode_ctl.scala 884:74]
-  wire  _T_998 = io_decode_exu_dec_i0_rs2_en_d & r_d_bits_i0v; // @[dec_decode_ctl.scala 885:59]
-  wire  _T_999 = r_d_bits_i0rd == i0r_rs2; // @[dec_decode_ctl.scala 885:91]
-  wire  i0_rs2_depend_i0_r = _T_998 & _T_999; // @[dec_decode_ctl.scala 885:74]
-  wire [1:0] _T_1016 = i0_rs2_depend_i0_r ? 2'h2 : 2'h0; // @[dec_decode_ctl.scala 890:63]
-  wire [1:0] i0_rs2_depth_d = i0_rs2_depend_i0_x ? 2'h1 : _T_1016; // @[dec_decode_ctl.scala 890:24]
-  wire  _T_1023 = i0_dp_store & i0_rs2_depth_d[0]; // @[dec_decode_ctl.scala 902:43]
-  wire  _T_1012_load = i0_rs2_depend_i0_r & i0_r_c_load; // @[dec_decode_ctl.scala 889:61]
-  wire  i0_rs2_class_d_load = i0_rs2_depend_i0_x ? i0_x_c_load : _T_1012_load; // @[dec_decode_ctl.scala 889:24]
-  wire  store_data_bypass_d = _T_1023 & i0_rs2_class_d_load; // @[dec_decode_ctl.scala 902:63]
-  wire  _T_435 = i0_dp_csr_clr | i0_dp_csr_set; // @[dec_decode_ctl.scala 525:42]
-  wire  _T_436 = _T_435 | i0_csr_write; // @[dec_decode_ctl.scala 525:58]
+  wire  _T_1003_load = i0_rs1_depend_i0_r & i0_r_c_load; // @[dec_decode_ctl.scala 889:61]
+  wire  i0_rs1_class_d_load = i0_rs1_depend_i0_x ? i0_x_c_load : _T_1003_load; // @[dec_decode_ctl.scala 889:24]
+  wire  load_ldst_bypass_d = _T_1020 & i0_rs1_class_d_load; // @[dec_decode_ctl.scala 903:78]
+  wire  _T_996 = io_decode_exu_dec_i0_rs2_en_d & x_d_bits_i0v; // @[dec_decode_ctl.scala 886:59]
+  wire  _T_997 = x_d_bits_i0rd == i0r_rs2; // @[dec_decode_ctl.scala 886:91]
+  wire  i0_rs2_depend_i0_x = _T_996 & _T_997; // @[dec_decode_ctl.scala 886:74]
+  wire  _T_998 = io_decode_exu_dec_i0_rs2_en_d & r_d_bits_i0v; // @[dec_decode_ctl.scala 887:59]
+  wire  _T_999 = r_d_bits_i0rd == i0r_rs2; // @[dec_decode_ctl.scala 887:91]
+  wire  i0_rs2_depend_i0_r = _T_998 & _T_999; // @[dec_decode_ctl.scala 887:74]
+  wire [1:0] _T_1016 = i0_rs2_depend_i0_r ? 2'h2 : 2'h0; // @[dec_decode_ctl.scala 892:63]
+  wire [1:0] i0_rs2_depth_d = i0_rs2_depend_i0_x ? 2'h1 : _T_1016; // @[dec_decode_ctl.scala 892:24]
+  wire  _T_1023 = i0_dp_store & i0_rs2_depth_d[0]; // @[dec_decode_ctl.scala 904:43]
+  wire  _T_1012_load = i0_rs2_depend_i0_r & i0_r_c_load; // @[dec_decode_ctl.scala 891:61]
+  wire  i0_rs2_class_d_load = i0_rs2_depend_i0_x ? i0_x_c_load : _T_1012_load; // @[dec_decode_ctl.scala 891:24]
+  wire  store_data_bypass_d = _T_1023 & i0_rs2_class_d_load; // @[dec_decode_ctl.scala 904:63]
+  wire  _T_435 = i0_dp_csr_clr | i0_dp_csr_set; // @[dec_decode_ctl.scala 527:42]
+  wire  _T_436 = _T_435 | i0_csr_write; // @[dec_decode_ctl.scala 527:58]
   wire [11:0] _T_440 = io_dec_csr_any_unq_d ? 12'hfff : 12'h0; // @[Bitwise.scala 72:12]
   reg  r_d_bits_csrwen; // @[Reg.scala 27:20]
-  wire  _T_443 = r_d_bits_csrwen & r_d_valid; // @[dec_decode_ctl.scala 530:53]
+  wire  _T_443 = r_d_bits_csrwen & r_d_valid; // @[dec_decode_ctl.scala 532:53]
   wire [11:0] _T_445 = _T_443 ? 12'hfff : 12'h0; // @[Bitwise.scala 72:12]
   reg [11:0] r_d_bits_csrwaddr; // @[Reg.scala 27:20]
-  wire  _T_450 = r_d_bits_csrwaddr == 12'h300; // @[dec_decode_ctl.scala 537:50]
-  wire  _T_451 = r_d_bits_csrwaddr == 12'h304; // @[dec_decode_ctl.scala 537:85]
-  wire  _T_452 = _T_450 | _T_451; // @[dec_decode_ctl.scala 537:64]
-  wire  _T_453 = _T_452 & r_d_bits_csrwen; // @[dec_decode_ctl.scala 537:100]
-  wire  _T_454 = _T_453 & r_d_valid; // @[dec_decode_ctl.scala 537:118]
-  wire  _T_455 = ~io_dec_tlu_i0_kill_writeb_wb; // @[dec_decode_ctl.scala 537:132]
-  reg  csr_read_x; // @[dec_decode_ctl.scala 539:52]
-  reg  csr_clr_x; // @[dec_decode_ctl.scala 540:51]
-  reg  csr_set_x; // @[dec_decode_ctl.scala 541:51]
-  reg  csr_write_x; // @[dec_decode_ctl.scala 542:53]
-  reg  csr_imm_x; // @[dec_decode_ctl.scala 543:51]
-  wire  i0_x_data_en = i0_pipe_en[3] | io_clk_override; // @[dec_decode_ctl.scala 769:50]
-  wire  _T_459 = i0_x_data_en & any_csr_d; // @[dec_decode_ctl.scala 546:48]
+  wire  _T_450 = r_d_bits_csrwaddr == 12'h300; // @[dec_decode_ctl.scala 539:50]
+  wire  _T_451 = r_d_bits_csrwaddr == 12'h304; // @[dec_decode_ctl.scala 539:85]
+  wire  _T_452 = _T_450 | _T_451; // @[dec_decode_ctl.scala 539:64]
+  wire  _T_453 = _T_452 & r_d_bits_csrwen; // @[dec_decode_ctl.scala 539:100]
+  wire  _T_454 = _T_453 & r_d_valid; // @[dec_decode_ctl.scala 539:118]
+  wire  _T_455 = ~io_dec_tlu_i0_kill_writeb_wb; // @[dec_decode_ctl.scala 539:132]
+  reg  csr_read_x; // @[dec_decode_ctl.scala 541:52]
+  reg  csr_clr_x; // @[dec_decode_ctl.scala 542:51]
+  reg  csr_set_x; // @[dec_decode_ctl.scala 543:51]
+  reg  csr_write_x; // @[dec_decode_ctl.scala 544:53]
+  reg  csr_imm_x; // @[dec_decode_ctl.scala 545:51]
+  wire  i0_x_data_en = i0_pipe_en[3] | io_clk_override; // @[dec_decode_ctl.scala 771:50]
+  wire  _T_459 = i0_x_data_en & any_csr_d; // @[dec_decode_ctl.scala 548:48]
   reg [4:0] csrimm_x; // @[Reg.scala 27:20]
   reg [31:0] csr_rddata_x; // @[Reg.scala 27:20]
   wire [31:0] _T_493 = {27'h0,csrimm_x}; // @[Cat.scala 29:58]
-  wire  _T_495 = ~csr_imm_x; // @[dec_decode_ctl.scala 551:5]
+  wire  _T_495 = ~csr_imm_x; // @[dec_decode_ctl.scala 553:5]
   wire [31:0] _T_496 = csr_imm_x ? _T_493 : 32'h0; // @[Mux.scala 27:72]
   wire [31:0] _T_497 = _T_495 ? io_decode_exu_exu_csr_rs1_x : 32'h0; // @[Mux.scala 27:72]
   wire [31:0] csr_mask_x = _T_496 | _T_497; // @[Mux.scala 27:72]
-  wire [31:0] _T_499 = ~csr_mask_x; // @[dec_decode_ctl.scala 554:38]
-  wire [31:0] _T_500 = csr_rddata_x & _T_499; // @[dec_decode_ctl.scala 554:35]
-  wire [31:0] _T_501 = csr_rddata_x | csr_mask_x; // @[dec_decode_ctl.scala 555:35]
+  wire [31:0] _T_499 = ~csr_mask_x; // @[dec_decode_ctl.scala 556:38]
+  wire [31:0] _T_500 = csr_rddata_x & _T_499; // @[dec_decode_ctl.scala 556:35]
+  wire [31:0] _T_501 = csr_rddata_x | csr_mask_x; // @[dec_decode_ctl.scala 557:35]
   wire [31:0] _T_502 = csr_clr_x ? _T_500 : 32'h0; // @[Mux.scala 27:72]
   wire [31:0] _T_503 = csr_set_x ? _T_501 : 32'h0; // @[Mux.scala 27:72]
   wire [31:0] _T_504 = csr_write_x ? csr_mask_x : 32'h0; // @[Mux.scala 27:72]
   wire [31:0] _T_505 = _T_502 | _T_503; // @[Mux.scala 27:72]
   wire [31:0] write_csr_data_x = _T_505 | _T_504; // @[Mux.scala 27:72]
-  wire  _T_517 = ~tlu_wr_pause_r1; // @[dec_decode_ctl.scala 562:44]
-  wire  _T_518 = ~tlu_wr_pause_r2; // @[dec_decode_ctl.scala 562:64]
-  wire  _T_519 = _T_517 & _T_518; // @[dec_decode_ctl.scala 562:61]
-  wire [31:0] _T_522 = write_csr_data - 32'h1; // @[dec_decode_ctl.scala 565:59]
-  wire  _T_524 = csr_clr_x | csr_set_x; // @[dec_decode_ctl.scala 567:34]
-  wire  _T_525 = _T_524 | csr_write_x; // @[dec_decode_ctl.scala 567:46]
-  wire  _T_526 = _T_525 & csr_read_x; // @[dec_decode_ctl.scala 567:61]
-  wire  _T_527 = _T_526 | io_dec_tlu_wr_pause_r; // @[dec_decode_ctl.scala 567:75]
-  wire  csr_data_wen = _T_527 | pause_stall; // @[dec_decode_ctl.scala 567:99]
+  wire  _T_517 = ~tlu_wr_pause_r1; // @[dec_decode_ctl.scala 564:44]
+  wire  _T_518 = ~tlu_wr_pause_r2; // @[dec_decode_ctl.scala 564:64]
+  wire  _T_519 = _T_517 & _T_518; // @[dec_decode_ctl.scala 564:61]
+  wire [31:0] _T_522 = write_csr_data - 32'h1; // @[dec_decode_ctl.scala 567:59]
+  wire  _T_524 = csr_clr_x | csr_set_x; // @[dec_decode_ctl.scala 569:34]
+  wire  _T_525 = _T_524 | csr_write_x; // @[dec_decode_ctl.scala 569:46]
+  wire  _T_526 = _T_525 & csr_read_x; // @[dec_decode_ctl.scala 569:61]
+  wire  _T_527 = _T_526 | io_dec_tlu_wr_pause_r; // @[dec_decode_ctl.scala 569:75]
+  wire  csr_data_wen = _T_527 | pause_stall; // @[dec_decode_ctl.scala 569:99]
   reg  r_d_bits_csrwonly; // @[Reg.scala 27:20]
-  wire  _T_529 = r_d_bits_csrwonly & r_d_valid; // @[dec_decode_ctl.scala 574:50]
-  wire  _T_881 = r_d_bits_i0v & r_d_bits_i0load; // @[dec_decode_ctl.scala 822:42]
+  wire  _T_529 = r_d_bits_csrwonly & r_d_valid; // @[dec_decode_ctl.scala 576:50]
+  wire  _T_881 = r_d_bits_i0v & r_d_bits_i0load; // @[dec_decode_ctl.scala 824:42]
   reg [31:0] i0_result_r_raw; // @[Reg.scala 27:20]
-  wire [31:0] i0_result_corr_r = _T_881 ? io_lsu_result_corr_r : i0_result_r_raw; // @[dec_decode_ctl.scala 822:27]
+  wire [31:0] i0_result_corr_r = _T_881 ? io_lsu_result_corr_r : i0_result_r_raw; // @[dec_decode_ctl.scala 824:27]
   reg  x_d_bits_csrwonly; // @[Reg.scala 27:20]
-  wire  _T_532 = x_d_bits_csrwonly | r_d_bits_csrwonly; // @[dec_decode_ctl.scala 576:43]
+  wire  _T_532 = x_d_bits_csrwonly | r_d_bits_csrwonly; // @[dec_decode_ctl.scala 578:43]
   reg  wbd_bits_csrwonly; // @[Reg.scala 27:20]
-  wire  prior_csr_write = _T_532 | wbd_bits_csrwonly; // @[dec_decode_ctl.scala 576:63]
-  wire  debug_fence_raw = io_dec_debug_fence_d & io_dbg_dctl_dbg_cmd_wrdata[1]; // @[dec_decode_ctl.scala 579:48]
-  wire  debug_fence = debug_fence_raw | debug_fence_i; // @[dec_decode_ctl.scala 580:40]
-  wire  _T_536 = i0_dp_presync | io_dec_tlu_presync_d; // @[dec_decode_ctl.scala 583:34]
-  wire  _T_537 = _T_536 | debug_fence_i; // @[dec_decode_ctl.scala 583:57]
-  wire  _T_538 = _T_537 | debug_fence_raw; // @[dec_decode_ctl.scala 583:73]
-  wire  i0_presync = _T_538 | io_dec_tlu_pipelining_disable; // @[dec_decode_ctl.scala 583:91]
+  wire  prior_csr_write = _T_532 | wbd_bits_csrwonly; // @[dec_decode_ctl.scala 578:63]
+  wire  debug_fence_raw = io_dec_debug_fence_d & io_dbg_dctl_dbg_cmd_wrdata[1]; // @[dec_decode_ctl.scala 581:48]
+  wire  debug_fence = debug_fence_raw | debug_fence_i; // @[dec_decode_ctl.scala 582:40]
+  wire  _T_536 = i0_dp_presync | io_dec_tlu_presync_d; // @[dec_decode_ctl.scala 585:34]
+  wire  _T_537 = _T_536 | debug_fence_i; // @[dec_decode_ctl.scala 585:57]
+  wire  _T_538 = _T_537 | debug_fence_raw; // @[dec_decode_ctl.scala 585:73]
+  wire  i0_presync = _T_538 | io_dec_tlu_pipelining_disable; // @[dec_decode_ctl.scala 585:91]
   wire [31:0] _T_562 = {16'h0,io_dec_aln_ifu_i0_cinst}; // @[Cat.scala 29:58]
-  wire  _T_564 = ~illegal_lockout; // @[dec_decode_ctl.scala 595:44]
-  wire  illegal_inst_en = shift_illegal & _T_564; // @[dec_decode_ctl.scala 595:42]
+  wire  _T_564 = ~illegal_lockout; // @[dec_decode_ctl.scala 597:44]
+  wire  illegal_inst_en = shift_illegal & _T_564; // @[dec_decode_ctl.scala 597:42]
   reg [31:0] _T_565; // @[Reg.scala 27:20]
-  wire  i0_div_prior_div_stall = i0_dp_div & io_dec_div_active; // @[dec_decode_ctl.scala 598:42]
-  wire  _T_569 = i0_dp_csr_read & prior_csr_write; // @[dec_decode_ctl.scala 600:40]
-  wire  _T_570 = _T_569 | io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 600:59]
-  wire  _T_571 = _T_570 | pause_stall; // @[dec_decode_ctl.scala 600:92]
-  wire  _T_572 = _T_571 | leak1_i0_stall; // @[dec_decode_ctl.scala 600:106]
-  wire  _T_573 = _T_572 | io_dec_tlu_debug_stall; // @[dec_decode_ctl.scala 601:20]
-  wire  _T_574 = _T_573 | postsync_stall; // @[dec_decode_ctl.scala 601:45]
-  wire  prior_inflight = x_d_valid | r_d_valid; // @[dec_decode_ctl.scala 623:41]
-  wire  prior_inflight_eff = i0_dp_div ? x_d_valid : prior_inflight; // @[dec_decode_ctl.scala 624:31]
-  wire  presync_stall = i0_presync & prior_inflight_eff; // @[dec_decode_ctl.scala 626:37]
-  wire  _T_575 = _T_574 | presync_stall; // @[dec_decode_ctl.scala 601:62]
-  wire  _T_576 = i0_dp_fence | debug_fence; // @[dec_decode_ctl.scala 602:19]
-  wire  _T_577 = ~lsu_idle; // @[dec_decode_ctl.scala 602:36]
-  wire  _T_578 = _T_576 & _T_577; // @[dec_decode_ctl.scala 602:34]
-  wire  _T_579 = _T_575 | _T_578; // @[dec_decode_ctl.scala 601:79]
-  wire  _T_580 = _T_579 | i0_nonblock_load_stall; // @[dec_decode_ctl.scala 602:47]
-  wire  _T_939 = io_decode_exu_dec_i0_rs1_en_d & io_dec_div_active; // @[dec_decode_ctl.scala 850:60]
-  wire  _T_940 = io_div_waddr_wb == i0r_rs1; // @[dec_decode_ctl.scala 850:99]
-  wire  _T_941 = _T_939 & _T_940; // @[dec_decode_ctl.scala 850:80]
-  wire  _T_942 = io_decode_exu_dec_i0_rs2_en_d & io_dec_div_active; // @[dec_decode_ctl.scala 851:36]
-  wire  _T_943 = io_div_waddr_wb == i0r_rs2; // @[dec_decode_ctl.scala 851:75]
-  wire  _T_944 = _T_942 & _T_943; // @[dec_decode_ctl.scala 851:56]
-  wire  i0_nonblock_div_stall = _T_941 | _T_944; // @[dec_decode_ctl.scala 850:113]
-  wire  _T_582 = _T_580 | i0_nonblock_div_stall; // @[dec_decode_ctl.scala 603:21]
-  wire  i0_block_raw_d = _T_582 | i0_div_prior_div_stall; // @[dec_decode_ctl.scala 603:45]
-  wire  _T_583 = io_lsu_store_stall_any | io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 605:65]
-  wire  i0_store_stall_d = i0_dp_store & _T_583; // @[dec_decode_ctl.scala 605:39]
-  wire  _T_584 = io_lsu_load_stall_any | io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 606:63]
-  wire  i0_load_stall_d = i0_dp_load & _T_584; // @[dec_decode_ctl.scala 606:38]
-  wire  _T_585 = i0_block_raw_d | i0_store_stall_d; // @[dec_decode_ctl.scala 607:38]
-  wire  i0_block_d = _T_585 | i0_load_stall_d; // @[dec_decode_ctl.scala 607:57]
-  wire  _T_586 = ~i0_block_d; // @[dec_decode_ctl.scala 611:54]
-  wire  _T_587 = io_dec_ib0_valid_d & _T_586; // @[dec_decode_ctl.scala 611:52]
-  wire  _T_589 = _T_587 & _T_367; // @[dec_decode_ctl.scala 611:69]
-  wire  _T_592 = ~i0_block_raw_d; // @[dec_decode_ctl.scala 612:46]
-  wire  _T_593 = io_dec_ib0_valid_d & _T_592; // @[dec_decode_ctl.scala 612:44]
-  wire  _T_595 = _T_593 & _T_367; // @[dec_decode_ctl.scala 612:61]
-  wire  i0_exudecode_d = _T_595 & _T_567; // @[dec_decode_ctl.scala 612:89]
-  wire  i0_exulegal_decode_d = i0_exudecode_d & i0_legal; // @[dec_decode_ctl.scala 613:46]
-  wire  _T_597 = ~io_dec_aln_dec_i0_decode_d; // @[dec_decode_ctl.scala 617:51]
-  wire  _T_610 = i0_dp_condbr | i0_dp_jal; // @[dec_decode_ctl.scala 631:53]
-  wire  d_t_icaf = i0_icaf_d & i0_legal_decode_d; // @[dec_decode_ctl.scala 641:40]
-  wire  d_t_icaf_second = io_dec_i0_icaf_second_d & i0_legal_decode_d; // @[dec_decode_ctl.scala 642:58]
-  wire  _T_619 = i0_dp_fence_i | debug_fence_i; // @[dec_decode_ctl.scala 645:44]
-  wire  d_t_fence_i = _T_619 & i0_legal_decode_d; // @[dec_decode_ctl.scala 645:61]
-  wire [3:0] _T_624 = {io_dec_aln_dec_i0_decode_d,io_dec_aln_dec_i0_decode_d,io_dec_aln_dec_i0_decode_d,io_dec_aln_dec_i0_decode_d}; // @[Cat.scala 29:58]
-  wire [3:0] d_t_i0trigger = io_dec_i0_trigger_match_d & _T_624; // @[dec_decode_ctl.scala 652:56]
-  wire  _T_818 = |i0_pipe_en[3:2]; // @[dec_decode_ctl.scala 766:49]
-  wire  i0_x_ctl_en = _T_818 | io_clk_override; // @[dec_decode_ctl.scala 766:53]
+  wire  i0_div_prior_div_stall = i0_dp_div & io_dec_div_active; // @[dec_decode_ctl.scala 600:42]
+  wire  _T_569 = i0_dp_csr_read & prior_csr_write; // @[dec_decode_ctl.scala 602:40]
+  wire  _T_570 = _T_569 | io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 602:59]
+  wire  _T_571 = _T_570 | pause_stall; // @[dec_decode_ctl.scala 602:92]
+  wire  _T_572 = _T_571 | leak1_i0_stall; // @[dec_decode_ctl.scala 602:106]
+  wire  _T_573 = _T_572 | io_dec_tlu_debug_stall; // @[dec_decode_ctl.scala 603:20]
+  wire  _T_574 = _T_573 | postsync_stall; // @[dec_decode_ctl.scala 603:45]
+  wire  prior_inflight = x_d_valid | r_d_valid; // @[dec_decode_ctl.scala 625:41]
+  wire  prior_inflight_eff = i0_dp_div ? x_d_valid : prior_inflight; // @[dec_decode_ctl.scala 626:31]
+  wire  presync_stall = i0_presync & prior_inflight_eff; // @[dec_decode_ctl.scala 628:37]
+  wire  _T_575 = _T_574 | presync_stall; // @[dec_decode_ctl.scala 603:62]
+  wire  _T_576 = i0_dp_fence | debug_fence; // @[dec_decode_ctl.scala 604:19]
+  wire  _T_577 = ~lsu_idle; // @[dec_decode_ctl.scala 604:36]
+  wire  _T_578 = _T_576 & _T_577; // @[dec_decode_ctl.scala 604:34]
+  wire  _T_579 = _T_575 | _T_578; // @[dec_decode_ctl.scala 603:79]
+  wire  _T_580 = _T_579 | i0_nonblock_load_stall; // @[dec_decode_ctl.scala 604:47]
+  wire  _T_939 = io_decode_exu_dec_i0_rs1_en_d & io_dec_div_active; // @[dec_decode_ctl.scala 852:60]
+  wire  _T_940 = io_div_waddr_wb == i0r_rs1; // @[dec_decode_ctl.scala 852:99]
+  wire  _T_941 = _T_939 & _T_940; // @[dec_decode_ctl.scala 852:80]
+  wire  _T_942 = io_decode_exu_dec_i0_rs2_en_d & io_dec_div_active; // @[dec_decode_ctl.scala 853:36]
+  wire  _T_943 = io_div_waddr_wb == i0r_rs2; // @[dec_decode_ctl.scala 853:75]
+  wire  _T_944 = _T_942 & _T_943; // @[dec_decode_ctl.scala 853:56]
+  wire  i0_nonblock_div_stall = _T_941 | _T_944; // @[dec_decode_ctl.scala 852:113]
+  wire  _T_582 = _T_580 | i0_nonblock_div_stall; // @[dec_decode_ctl.scala 605:21]
+  wire  i0_block_raw_d = _T_582 | i0_div_prior_div_stall; // @[dec_decode_ctl.scala 605:45]
+  wire  _T_583 = io_lsu_store_stall_any | io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 607:65]
+  wire  i0_store_stall_d = i0_dp_store & _T_583; // @[dec_decode_ctl.scala 607:39]
+  wire  _T_584 = io_lsu_load_stall_any | io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 608:63]
+  wire  i0_load_stall_d = i0_dp_load & _T_584; // @[dec_decode_ctl.scala 608:38]
+  wire  _T_585 = i0_block_raw_d | i0_store_stall_d; // @[dec_decode_ctl.scala 609:38]
+  wire  i0_block_d = _T_585 | i0_load_stall_d; // @[dec_decode_ctl.scala 609:57]
+  wire  _T_586 = ~i0_block_d; // @[dec_decode_ctl.scala 613:46]
+  wire  _T_587 = io_dec_ib0_valid_d & _T_586; // @[dec_decode_ctl.scala 613:44]
+  wire  _T_589 = _T_587 & _T_367; // @[dec_decode_ctl.scala 613:61]
+  wire  _T_592 = ~i0_block_raw_d; // @[dec_decode_ctl.scala 614:46]
+  wire  _T_593 = io_dec_ib0_valid_d & _T_592; // @[dec_decode_ctl.scala 614:44]
+  wire  _T_595 = _T_593 & _T_367; // @[dec_decode_ctl.scala 614:61]
+  wire  i0_exudecode_d = _T_595 & _T_567; // @[dec_decode_ctl.scala 614:89]
+  wire  i0_exulegal_decode_d = i0_exudecode_d & i0_legal; // @[dec_decode_ctl.scala 615:46]
+  wire  _T_597 = ~io_dec_i0_decode_d; // @[dec_decode_ctl.scala 619:51]
+  wire  _T_610 = i0_dp_condbr | i0_dp_jal; // @[dec_decode_ctl.scala 633:53]
+  wire  d_t_icaf = i0_icaf_d & i0_legal_decode_d; // @[dec_decode_ctl.scala 643:40]
+  wire  d_t_icaf_second = io_dec_i0_icaf_second_d & i0_legal_decode_d; // @[dec_decode_ctl.scala 644:58]
+  wire  _T_619 = i0_dp_fence_i | debug_fence_i; // @[dec_decode_ctl.scala 647:44]
+  wire  d_t_fence_i = _T_619 & i0_legal_decode_d; // @[dec_decode_ctl.scala 647:61]
+  wire [3:0] _T_624 = {io_dec_i0_decode_d,io_dec_i0_decode_d,io_dec_i0_decode_d,io_dec_i0_decode_d}; // @[Cat.scala 29:58]
+  wire [3:0] d_t_i0trigger = io_dec_i0_trigger_match_d & _T_624; // @[dec_decode_ctl.scala 654:56]
+  wire  _T_818 = |i0_pipe_en[3:2]; // @[dec_decode_ctl.scala 768:49]
+  wire  i0_x_ctl_en = _T_818 | io_clk_override; // @[dec_decode_ctl.scala 768:53]
   reg  x_t_legal; // @[Reg.scala 27:20]
   reg  x_t_icaf; // @[Reg.scala 27:20]
   reg  x_t_icaf_second; // @[Reg.scala 27:20]
@@ -2756,8 +2756,8 @@ module dec_decode_ctl(
   reg [3:0] x_t_pmu_i0_itype; // @[Reg.scala 27:20]
   reg  x_t_pmu_i0_br_unpred; // @[Reg.scala 27:20]
   wire [3:0] _T_632 = {io_dec_tlu_flush_lower_wb,io_dec_tlu_flush_lower_wb,io_dec_tlu_flush_lower_wb,io_dec_tlu_flush_lower_wb}; // @[Cat.scala 29:58]
-  wire [3:0] _T_633 = ~_T_632; // @[dec_decode_ctl.scala 658:39]
-  wire [3:0] x_t_in_i0trigger = x_t_i0trigger & _T_633; // @[dec_decode_ctl.scala 658:37]
+  wire [3:0] _T_633 = ~_T_632; // @[dec_decode_ctl.scala 660:39]
+  wire [3:0] x_t_in_i0trigger = x_t_i0trigger & _T_633; // @[dec_decode_ctl.scala 660:37]
   reg  r_t_legal; // @[Reg.scala 27:20]
   reg  r_t_icaf; // @[Reg.scala 27:20]
   reg  r_t_icaf_second; // @[Reg.scala 27:20]
@@ -2767,24 +2767,24 @@ module dec_decode_ctl(
   reg [3:0] r_t_pmu_i0_itype; // @[Reg.scala 27:20]
   reg  r_t_pmu_i0_br_unpred; // @[Reg.scala 27:20]
   reg  r_d_bits_i0store; // @[Reg.scala 27:20]
-  wire  _T_638 = r_d_bits_i0load | r_d_bits_i0store; // @[dec_decode_ctl.scala 664:61]
+  wire  _T_638 = r_d_bits_i0load | r_d_bits_i0store; // @[dec_decode_ctl.scala 666:61]
   wire [3:0] _T_642 = {_T_638,_T_638,_T_638,_T_638}; // @[Cat.scala 29:58]
-  wire [3:0] _T_643 = _T_642 & lsu_trigger_match_r; // @[dec_decode_ctl.scala 664:82]
-  wire [3:0] _T_644 = _T_643 | r_t_i0trigger; // @[dec_decode_ctl.scala 664:105]
-  wire  _T_657 = i0r_rs1 != 5'h0; // @[dec_decode_ctl.scala 680:60]
-  wire  _T_659 = i0r_rs2 != 5'h0; // @[dec_decode_ctl.scala 681:60]
-  wire  _T_661 = i0r_rd != 5'h0; // @[dec_decode_ctl.scala 682:48]
-  wire  i0_rd_en_d = i0_dp_rd & _T_661; // @[dec_decode_ctl.scala 682:37]
-  wire  i0_jalimm20 = i0_dp_jal & i0_dp_imm20; // @[dec_decode_ctl.scala 686:38]
-  wire  _T_662 = ~i0_dp_jal; // @[dec_decode_ctl.scala 687:27]
-  wire  i0_uiimm20 = _T_662 & i0_dp_imm20; // @[dec_decode_ctl.scala 687:38]
+  wire [3:0] _T_643 = _T_642 & lsu_trigger_match_r; // @[dec_decode_ctl.scala 666:82]
+  wire [3:0] _T_644 = _T_643 | r_t_i0trigger; // @[dec_decode_ctl.scala 666:105]
+  wire  _T_657 = i0r_rs1 != 5'h0; // @[dec_decode_ctl.scala 682:60]
+  wire  _T_659 = i0r_rs2 != 5'h0; // @[dec_decode_ctl.scala 683:60]
+  wire  _T_661 = i0r_rd != 5'h0; // @[dec_decode_ctl.scala 684:48]
+  wire  i0_rd_en_d = i0_dp_rd & _T_661; // @[dec_decode_ctl.scala 684:37]
+  wire  i0_jalimm20 = i0_dp_jal & i0_dp_imm20; // @[dec_decode_ctl.scala 688:38]
+  wire  _T_662 = ~i0_dp_jal; // @[dec_decode_ctl.scala 689:27]
+  wire  i0_uiimm20 = _T_662 & i0_dp_imm20; // @[dec_decode_ctl.scala 689:38]
   wire [9:0] _T_673 = {io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31]}; // @[Cat.scala 29:58]
   wire [18:0] _T_682 = {_T_673,io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31]}; // @[Cat.scala 29:58]
   wire [31:0] _T_685 = {_T_682,io_dec_i0_instr_d[31],io_dec_i0_instr_d[31:20]}; // @[Cat.scala 29:58]
   wire [31:0] _T_714 = {27'h0,i0r_rs2}; // @[Cat.scala 29:58]
   wire [31:0] _T_734 = {_T_673,io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[19:12],io_dec_i0_instr_d[20],io_dec_i0_instr_d[30:21],1'h0}; // @[Cat.scala 29:58]
   wire [31:0] _T_748 = {io_dec_i0_instr_d[31:12],12'h0}; // @[Cat.scala 29:58]
-  wire  _T_749 = i0_csr_write_only_d & i0_dp_csr_imm; // @[dec_decode_ctl.scala 698:26]
+  wire  _T_749 = i0_csr_write_only_d & i0_dp_csr_imm; // @[dec_decode_ctl.scala 700:26]
   wire [31:0] _T_779 = {27'h0,i0r_rs1}; // @[Cat.scala 29:58]
   wire [31:0] _T_780 = i0_dp_imm12 ? _T_685 : 32'h0; // @[Mux.scala 27:72]
   wire [31:0] _T_781 = i0_dp_shimm5 ? _T_714 : 32'h0; // @[Mux.scala 27:72]
@@ -2794,46 +2794,46 @@ module dec_decode_ctl(
   wire [31:0] _T_785 = _T_780 | _T_781; // @[Mux.scala 27:72]
   wire [31:0] _T_786 = _T_785 | _T_782; // @[Mux.scala 27:72]
   wire [31:0] _T_787 = _T_786 | _T_783; // @[Mux.scala 27:72]
-  wire  i0_d_c_mul = i0_dp_mul & i0_legal_decode_d; // @[dec_decode_ctl.scala 758:44]
-  wire  i0_d_c_load = i0_dp_load & i0_legal_decode_d; // @[dec_decode_ctl.scala 759:44]
-  wire  i0_d_c_alu = i0_dp_alu & i0_legal_decode_d; // @[dec_decode_ctl.scala 760:44]
+  wire  i0_d_c_mul = i0_dp_mul & i0_legal_decode_d; // @[dec_decode_ctl.scala 760:44]
+  wire  i0_d_c_load = i0_dp_load & i0_legal_decode_d; // @[dec_decode_ctl.scala 761:44]
+  wire  i0_d_c_alu = i0_dp_alu & i0_legal_decode_d; // @[dec_decode_ctl.scala 762:44]
   reg  i0_x_c_mul; // @[Reg.scala 27:20]
   reg  i0_x_c_alu; // @[Reg.scala 27:20]
   reg  i0_r_c_mul; // @[Reg.scala 27:20]
   reg  i0_r_c_alu; // @[Reg.scala 27:20]
-  wire  _T_824 = |i0_pipe_en[1:0]; // @[dec_decode_ctl.scala 768:49]
-  wire  i0_wb_ctl_en = _T_824 | io_clk_override; // @[dec_decode_ctl.scala 768:53]
-  wire  i0_r_data_en = i0_pipe_en[2] | io_clk_override; // @[dec_decode_ctl.scala 770:50]
-  wire  i0_wb_data_en = i0_pipe_en[1] | io_clk_override; // @[dec_decode_ctl.scala 771:50]
-  wire  d_d_bits_i0v = i0_rd_en_d & i0_legal_decode_d; // @[dec_decode_ctl.scala 777:50]
-  wire  d_d_bits_i0store = i0_dp_store & i0_legal_decode_d; // @[dec_decode_ctl.scala 781:50]
-  wire  d_d_bits_i0div = i0_dp_div & i0_legal_decode_d; // @[dec_decode_ctl.scala 782:50]
-  wire  d_d_bits_csrwen = io_dec_csr_wen_unq_d & i0_legal_decode_d; // @[dec_decode_ctl.scala 784:61]
-  wire  d_d_bits_csrwonly = i0_csr_write_only_d & io_dec_aln_dec_i0_decode_d; // @[dec_decode_ctl.scala 785:58]
+  wire  _T_824 = |i0_pipe_en[1:0]; // @[dec_decode_ctl.scala 770:49]
+  wire  i0_wb_ctl_en = _T_824 | io_clk_override; // @[dec_decode_ctl.scala 770:53]
+  wire  i0_r_data_en = i0_pipe_en[2] | io_clk_override; // @[dec_decode_ctl.scala 772:50]
+  wire  i0_wb_data_en = i0_pipe_en[1] | io_clk_override; // @[dec_decode_ctl.scala 773:50]
+  wire  d_d_bits_i0v = i0_rd_en_d & i0_legal_decode_d; // @[dec_decode_ctl.scala 779:50]
+  wire  d_d_bits_i0store = i0_dp_store & i0_legal_decode_d; // @[dec_decode_ctl.scala 783:50]
+  wire  d_d_bits_i0div = i0_dp_div & i0_legal_decode_d; // @[dec_decode_ctl.scala 784:50]
+  wire  d_d_bits_csrwen = io_dec_csr_wen_unq_d & i0_legal_decode_d; // @[dec_decode_ctl.scala 786:61]
+  wire  d_d_bits_csrwonly = i0_csr_write_only_d & io_dec_i0_decode_d; // @[dec_decode_ctl.scala 787:58]
   reg  x_d_bits_i0store; // @[Reg.scala 27:20]
   reg  x_d_bits_csrwen; // @[Reg.scala 27:20]
   reg [11:0] x_d_bits_csrwaddr; // @[Reg.scala 27:20]
-  wire  _T_847 = x_d_bits_i0v & _T_857; // @[dec_decode_ctl.scala 791:47]
-  wire  x_d_in_bits_i0v = _T_847 & _T_367; // @[dec_decode_ctl.scala 791:76]
-  wire  _T_851 = x_d_valid & _T_857; // @[dec_decode_ctl.scala 792:33]
-  wire  x_d_in_valid = _T_851 & _T_367; // @[dec_decode_ctl.scala 792:62]
-  wire  _T_870 = ~r_d_bits_i0div; // @[dec_decode_ctl.scala 807:49]
-  wire  _T_871 = i0_wen_r & _T_870; // @[dec_decode_ctl.scala 807:47]
-  wire  _T_872 = ~i0_load_kill_wen_r; // @[dec_decode_ctl.scala 807:70]
-  wire  _T_874 = x_d_bits_i0v | x_d_bits_csrwen; // @[dec_decode_ctl.scala 811:74]
-  wire  _T_875 = _T_874 | debug_valid_x; // @[dec_decode_ctl.scala 811:92]
-  wire  _T_876 = i0_r_data_en & _T_875; // @[dec_decode_ctl.scala 811:58]
-  wire  _T_878 = x_d_bits_i0v & x_d_bits_i0load; // @[dec_decode_ctl.scala 817:47]
-  wire  _T_885 = io_decode_exu_i0_ap_predict_nt & _T_662; // @[dec_decode_ctl.scala 823:71]
+  wire  _T_847 = x_d_bits_i0v & _T_857; // @[dec_decode_ctl.scala 793:47]
+  wire  x_d_in_bits_i0v = _T_847 & _T_367; // @[dec_decode_ctl.scala 793:76]
+  wire  _T_851 = x_d_valid & _T_857; // @[dec_decode_ctl.scala 794:33]
+  wire  x_d_in_valid = _T_851 & _T_367; // @[dec_decode_ctl.scala 794:62]
+  wire  _T_870 = ~r_d_bits_i0div; // @[dec_decode_ctl.scala 809:49]
+  wire  _T_871 = i0_wen_r & _T_870; // @[dec_decode_ctl.scala 809:47]
+  wire  _T_872 = ~i0_load_kill_wen_r; // @[dec_decode_ctl.scala 809:70]
+  wire  _T_874 = x_d_bits_i0v | x_d_bits_csrwen; // @[dec_decode_ctl.scala 813:74]
+  wire  _T_875 = _T_874 | debug_valid_x; // @[dec_decode_ctl.scala 813:92]
+  wire  _T_876 = i0_r_data_en & _T_875; // @[dec_decode_ctl.scala 813:58]
+  wire  _T_878 = x_d_bits_i0v & x_d_bits_i0load; // @[dec_decode_ctl.scala 819:47]
+  wire  _T_885 = io_decode_exu_i0_ap_predict_nt & _T_662; // @[dec_decode_ctl.scala 825:71]
   wire [11:0] _T_898 = {10'h0,io_dec_i0_pc4_d,i0_ap_pc2}; // @[Cat.scala 29:58]
   reg [11:0] last_br_immed_x; // @[Reg.scala 27:20]
-  wire  trace_enable = ~io_dec_tlu_trace_disable; // @[dec_decode_ctl.scala 858:22]
+  wire  trace_enable = ~io_dec_tlu_trace_disable; // @[dec_decode_ctl.scala 860:22]
   reg [4:0] _T_947; // @[Reg.scala 27:20]
-  wire  _T_948 = i0_x_data_en & trace_enable; // @[dec_decode_ctl.scala 862:50]
+  wire  _T_948 = i0_x_data_en & trace_enable; // @[dec_decode_ctl.scala 864:50]
   reg [31:0] i0_inst_x; // @[Reg.scala 27:20]
-  wire  _T_950 = i0_r_data_en & trace_enable; // @[dec_decode_ctl.scala 863:50]
+  wire  _T_950 = i0_r_data_en & trace_enable; // @[dec_decode_ctl.scala 865:50]
   reg [31:0] i0_inst_r; // @[Reg.scala 27:20]
-  wire  _T_952 = i0_wb_data_en & trace_enable; // @[dec_decode_ctl.scala 865:51]
+  wire  _T_952 = i0_wb_data_en & trace_enable; // @[dec_decode_ctl.scala 867:51]
   reg [31:0] i0_inst_wb; // @[Reg.scala 27:20]
   reg [30:0] i0_pc_wb; // @[Reg.scala 27:20]
   reg [30:0] dec_i0_pc_r; // @[Reg.scala 27:20]
@@ -2853,61 +2853,61 @@ module dec_decode_ctl(
   wire [18:0] _T_986 = _T_983 | _T_984; // @[Mux.scala 27:72]
   wire [18:0] _T_987 = _T_986 | _T_985; // @[Mux.scala 27:72]
   wire [31:0] temp_pred_correct_npc_x = {_T_987,_T_962[11:0],1'h0}; // @[Cat.scala 29:58]
-  wire  _T_1003_mul = i0_rs1_depend_i0_r & i0_r_c_mul; // @[dec_decode_ctl.scala 887:61]
-  wire  _T_1003_alu = i0_rs1_depend_i0_r & i0_r_c_alu; // @[dec_decode_ctl.scala 887:61]
-  wire  i0_rs1_class_d_mul = i0_rs1_depend_i0_x ? i0_x_c_mul : _T_1003_mul; // @[dec_decode_ctl.scala 887:24]
-  wire  i0_rs1_class_d_alu = i0_rs1_depend_i0_x ? i0_x_c_alu : _T_1003_alu; // @[dec_decode_ctl.scala 887:24]
-  wire  _T_1012_mul = i0_rs2_depend_i0_r & i0_r_c_mul; // @[dec_decode_ctl.scala 889:61]
-  wire  _T_1012_alu = i0_rs2_depend_i0_r & i0_r_c_alu; // @[dec_decode_ctl.scala 889:61]
-  wire  i0_rs2_class_d_mul = i0_rs2_depend_i0_x ? i0_x_c_mul : _T_1012_mul; // @[dec_decode_ctl.scala 889:24]
-  wire  i0_rs2_class_d_alu = i0_rs2_depend_i0_x ? i0_x_c_alu : _T_1012_alu; // @[dec_decode_ctl.scala 889:24]
-  wire  _T_1025 = io_decode_exu_dec_i0_rs1_en_d & io_dec_nonblock_load_wen; // @[dec_decode_ctl.scala 907:73]
-  wire  _T_1026 = io_dec_nonblock_load_waddr == i0r_rs1; // @[dec_decode_ctl.scala 907:130]
-  wire  i0_rs1_nonblock_load_bypass_en_d = _T_1025 & _T_1026; // @[dec_decode_ctl.scala 907:100]
-  wire  _T_1027 = io_decode_exu_dec_i0_rs2_en_d & io_dec_nonblock_load_wen; // @[dec_decode_ctl.scala 909:73]
-  wire  _T_1028 = io_dec_nonblock_load_waddr == i0r_rs2; // @[dec_decode_ctl.scala 909:130]
-  wire  i0_rs2_nonblock_load_bypass_en_d = _T_1027 & _T_1028; // @[dec_decode_ctl.scala 909:100]
-  wire  _T_1030 = i0_rs1_class_d_alu | i0_rs1_class_d_mul; // @[dec_decode_ctl.scala 912:66]
-  wire  _T_1031 = i0_rs1_depth_d[0] & _T_1030; // @[dec_decode_ctl.scala 912:45]
-  wire  _T_1033 = i0_rs1_depth_d[0] & i0_rs1_class_d_load; // @[dec_decode_ctl.scala 912:108]
-  wire  _T_1036 = _T_1030 | i0_rs1_class_d_load; // @[dec_decode_ctl.scala 912:196]
-  wire  _T_1037 = i0_rs1_depth_d[1] & _T_1036; // @[dec_decode_ctl.scala 912:153]
+  wire  _T_1003_mul = i0_rs1_depend_i0_r & i0_r_c_mul; // @[dec_decode_ctl.scala 889:61]
+  wire  _T_1003_alu = i0_rs1_depend_i0_r & i0_r_c_alu; // @[dec_decode_ctl.scala 889:61]
+  wire  i0_rs1_class_d_mul = i0_rs1_depend_i0_x ? i0_x_c_mul : _T_1003_mul; // @[dec_decode_ctl.scala 889:24]
+  wire  i0_rs1_class_d_alu = i0_rs1_depend_i0_x ? i0_x_c_alu : _T_1003_alu; // @[dec_decode_ctl.scala 889:24]
+  wire  _T_1012_mul = i0_rs2_depend_i0_r & i0_r_c_mul; // @[dec_decode_ctl.scala 891:61]
+  wire  _T_1012_alu = i0_rs2_depend_i0_r & i0_r_c_alu; // @[dec_decode_ctl.scala 891:61]
+  wire  i0_rs2_class_d_mul = i0_rs2_depend_i0_x ? i0_x_c_mul : _T_1012_mul; // @[dec_decode_ctl.scala 891:24]
+  wire  i0_rs2_class_d_alu = i0_rs2_depend_i0_x ? i0_x_c_alu : _T_1012_alu; // @[dec_decode_ctl.scala 891:24]
+  wire  _T_1025 = io_decode_exu_dec_i0_rs1_en_d & io_dec_nonblock_load_wen; // @[dec_decode_ctl.scala 909:73]
+  wire  _T_1026 = io_dec_nonblock_load_waddr == i0r_rs1; // @[dec_decode_ctl.scala 909:130]
+  wire  i0_rs1_nonblock_load_bypass_en_d = _T_1025 & _T_1026; // @[dec_decode_ctl.scala 909:100]
+  wire  _T_1027 = io_decode_exu_dec_i0_rs2_en_d & io_dec_nonblock_load_wen; // @[dec_decode_ctl.scala 911:73]
+  wire  _T_1028 = io_dec_nonblock_load_waddr == i0r_rs2; // @[dec_decode_ctl.scala 911:130]
+  wire  i0_rs2_nonblock_load_bypass_en_d = _T_1027 & _T_1028; // @[dec_decode_ctl.scala 911:100]
+  wire  _T_1030 = i0_rs1_class_d_alu | i0_rs1_class_d_mul; // @[dec_decode_ctl.scala 914:66]
+  wire  _T_1031 = i0_rs1_depth_d[0] & _T_1030; // @[dec_decode_ctl.scala 914:45]
+  wire  _T_1033 = i0_rs1_depth_d[0] & i0_rs1_class_d_load; // @[dec_decode_ctl.scala 914:108]
+  wire  _T_1036 = _T_1030 | i0_rs1_class_d_load; // @[dec_decode_ctl.scala 914:196]
+  wire  _T_1037 = i0_rs1_depth_d[1] & _T_1036; // @[dec_decode_ctl.scala 914:153]
   wire [2:0] i0_rs1bypass = {_T_1031,_T_1033,_T_1037}; // @[Cat.scala 29:58]
-  wire  _T_1041 = i0_rs2_class_d_alu | i0_rs2_class_d_mul; // @[dec_decode_ctl.scala 914:67]
-  wire  _T_1042 = i0_rs2_depth_d[0] & _T_1041; // @[dec_decode_ctl.scala 914:45]
-  wire  _T_1044 = i0_rs2_depth_d[0] & i0_rs2_class_d_load; // @[dec_decode_ctl.scala 914:109]
-  wire  _T_1047 = _T_1041 | i0_rs2_class_d_load; // @[dec_decode_ctl.scala 914:196]
-  wire  _T_1048 = i0_rs2_depth_d[1] & _T_1047; // @[dec_decode_ctl.scala 914:153]
+  wire  _T_1041 = i0_rs2_class_d_alu | i0_rs2_class_d_mul; // @[dec_decode_ctl.scala 916:67]
+  wire  _T_1042 = i0_rs2_depth_d[0] & _T_1041; // @[dec_decode_ctl.scala 916:45]
+  wire  _T_1044 = i0_rs2_depth_d[0] & i0_rs2_class_d_load; // @[dec_decode_ctl.scala 916:109]
+  wire  _T_1047 = _T_1041 | i0_rs2_class_d_load; // @[dec_decode_ctl.scala 916:196]
+  wire  _T_1048 = i0_rs2_depth_d[1] & _T_1047; // @[dec_decode_ctl.scala 916:153]
   wire [2:0] i0_rs2bypass = {_T_1042,_T_1044,_T_1048}; // @[Cat.scala 29:58]
-  wire  _T_1052 = ~i0_rs1bypass[0]; // @[dec_decode_ctl.scala 916:53]
-  wire  _T_1054 = ~i0_rs1bypass[1]; // @[dec_decode_ctl.scala 916:72]
-  wire  _T_1055 = _T_1052 & _T_1054; // @[dec_decode_ctl.scala 916:70]
-  wire  _T_1057 = ~i0_rs1bypass[2]; // @[dec_decode_ctl.scala 916:91]
-  wire  _T_1058 = _T_1055 & _T_1057; // @[dec_decode_ctl.scala 916:89]
-  wire  _T_1059 = _T_1058 & i0_rs1_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 916:108]
+  wire  _T_1052 = ~i0_rs1bypass[0]; // @[dec_decode_ctl.scala 918:53]
+  wire  _T_1054 = ~i0_rs1bypass[1]; // @[dec_decode_ctl.scala 918:72]
+  wire  _T_1055 = _T_1052 & _T_1054; // @[dec_decode_ctl.scala 918:70]
+  wire  _T_1057 = ~i0_rs1bypass[2]; // @[dec_decode_ctl.scala 918:91]
+  wire  _T_1058 = _T_1055 & _T_1057; // @[dec_decode_ctl.scala 918:89]
+  wire  _T_1059 = _T_1058 & i0_rs1_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 918:108]
   wire [1:0] _T_1063 = {i0_rs1bypass[1],i0_rs1bypass[0]}; // @[Cat.scala 29:58]
   wire [1:0] _T_1064 = {_T_1059,i0_rs1bypass[2]}; // @[Cat.scala 29:58]
-  wire  _T_1067 = ~i0_rs2bypass[0]; // @[dec_decode_ctl.scala 917:53]
-  wire  _T_1069 = ~i0_rs2bypass[1]; // @[dec_decode_ctl.scala 917:72]
-  wire  _T_1070 = _T_1067 & _T_1069; // @[dec_decode_ctl.scala 917:70]
-  wire  _T_1072 = ~i0_rs2bypass[2]; // @[dec_decode_ctl.scala 917:91]
-  wire  _T_1073 = _T_1070 & _T_1072; // @[dec_decode_ctl.scala 917:89]
-  wire  _T_1074 = _T_1073 & i0_rs2_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 917:108]
+  wire  _T_1067 = ~i0_rs2bypass[0]; // @[dec_decode_ctl.scala 919:53]
+  wire  _T_1069 = ~i0_rs2bypass[1]; // @[dec_decode_ctl.scala 919:72]
+  wire  _T_1070 = _T_1067 & _T_1069; // @[dec_decode_ctl.scala 919:70]
+  wire  _T_1072 = ~i0_rs2bypass[2]; // @[dec_decode_ctl.scala 919:91]
+  wire  _T_1073 = _T_1070 & _T_1072; // @[dec_decode_ctl.scala 919:89]
+  wire  _T_1074 = _T_1073 & i0_rs2_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 919:108]
   wire [1:0] _T_1078 = {i0_rs2bypass[1],i0_rs2bypass[0]}; // @[Cat.scala 29:58]
   wire [1:0] _T_1079 = {_T_1074,i0_rs2bypass[2]}; // @[Cat.scala 29:58]
-  wire  _T_1081 = i0_dp_raw_load | i0_dp_raw_store; // @[dec_decode_ctl.scala 921:68]
-  wire  _T_1082 = io_dec_ib0_valid_d & _T_1081; // @[dec_decode_ctl.scala 921:50]
-  wire  _T_1083 = ~io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 921:89]
-  wire  _T_1084 = _T_1082 & _T_1083; // @[dec_decode_ctl.scala 921:87]
-  wire  _T_1086 = _T_1084 & _T_592; // @[dec_decode_ctl.scala 921:121]
-  wire  _T_1088 = ~io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 923:6]
-  wire  _T_1089 = _T_1088 & i0_dp_lsu; // @[dec_decode_ctl.scala 923:38]
-  wire  _T_1090 = _T_1089 & i0_dp_load; // @[dec_decode_ctl.scala 923:50]
-  wire  _T_1095 = _T_1089 & i0_dp_store; // @[dec_decode_ctl.scala 924:50]
+  wire  _T_1081 = i0_dp_raw_load | i0_dp_raw_store; // @[dec_decode_ctl.scala 923:68]
+  wire  _T_1082 = io_dec_ib0_valid_d & _T_1081; // @[dec_decode_ctl.scala 923:50]
+  wire  _T_1083 = ~io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 923:89]
+  wire  _T_1084 = _T_1082 & _T_1083; // @[dec_decode_ctl.scala 923:87]
+  wire  _T_1086 = _T_1084 & _T_592; // @[dec_decode_ctl.scala 923:121]
+  wire  _T_1088 = ~io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 925:6]
+  wire  _T_1089 = _T_1088 & i0_dp_lsu; // @[dec_decode_ctl.scala 925:38]
+  wire  _T_1090 = _T_1089 & i0_dp_load; // @[dec_decode_ctl.scala 925:50]
+  wire  _T_1095 = _T_1089 & i0_dp_store; // @[dec_decode_ctl.scala 926:50]
   wire [11:0] _T_1099 = {io_dec_i0_instr_d[31:25],i0r_rd}; // @[Cat.scala 29:58]
   wire [11:0] _T_1100 = _T_1090 ? io_dec_i0_instr_d[31:20] : 12'h0; // @[Mux.scala 27:72]
   wire [11:0] _T_1101 = _T_1095 ? _T_1099 : 12'h0; // @[Mux.scala 27:72]
-  dec_dec_ctl i0_dec ( // @[dec_decode_ctl.scala 438:22]
+  dec_dec_ctl i0_dec ( // @[dec_decode_ctl.scala 440:22]
     .io_ins(i0_dec_io_ins),
     .io_out_clz(i0_dec_io_out_clz),
     .io_out_ctz(i0_dec_io_out_ctz),
@@ -3049,156 +3049,156 @@ module dec_decode_ctl(
     .io_clk(rvclkhdr_10_io_clk),
     .io_en(rvclkhdr_10_io_en)
   );
-  assign io_decode_exu_dec_data_en = {i0_x_data_en,i0_r_data_en}; // @[dec_decode_ctl.scala 773:38]
-  assign io_decode_exu_dec_ctl_en = {i0_x_ctl_en,i0_r_ctl_en}; // @[dec_decode_ctl.scala 774:38]
-  assign io_decode_exu_i0_ap_clz = _T_80 ? 1'h0 : i0_dp_raw_clz; // @[dec_decode_ctl.scala 317:33]
-  assign io_decode_exu_i0_ap_ctz = _T_80 ? 1'h0 : i0_dp_raw_ctz; // @[dec_decode_ctl.scala 318:33]
-  assign io_decode_exu_i0_ap_pcnt = _T_80 ? 1'h0 : i0_dp_raw_pcnt; // @[dec_decode_ctl.scala 319:33]
-  assign io_decode_exu_i0_ap_sext_b = _T_80 ? 1'h0 : i0_dp_raw_sext_b; // @[dec_decode_ctl.scala 320:33]
-  assign io_decode_exu_i0_ap_sext_h = _T_80 ? 1'h0 : i0_dp_raw_sext_h; // @[dec_decode_ctl.scala 321:33]
-  assign io_decode_exu_i0_ap_slo = _T_80 ? 1'h0 : i0_dp_raw_slo; // @[dec_decode_ctl.scala 326:33]
-  assign io_decode_exu_i0_ap_sro = _T_80 ? 1'h0 : i0_dp_raw_sro; // @[dec_decode_ctl.scala 327:33]
-  assign io_decode_exu_i0_ap_min = _T_80 ? 1'h0 : i0_dp_raw_min; // @[dec_decode_ctl.scala 328:33]
-  assign io_decode_exu_i0_ap_max = _T_80 ? 1'h0 : i0_dp_raw_max; // @[dec_decode_ctl.scala 329:33]
-  assign io_decode_exu_i0_ap_pack = _T_80 ? 1'h0 : i0_dp_raw_pack; // @[dec_decode_ctl.scala 330:33]
-  assign io_decode_exu_i0_ap_packu = _T_80 ? 1'h0 : i0_dp_raw_packu; // @[dec_decode_ctl.scala 331:33]
-  assign io_decode_exu_i0_ap_packh = _T_80 ? 1'h0 : i0_dp_raw_packh; // @[dec_decode_ctl.scala 332:33]
-  assign io_decode_exu_i0_ap_rol = _T_80 ? 1'h0 : i0_dp_raw_rol; // @[dec_decode_ctl.scala 333:33]
-  assign io_decode_exu_i0_ap_ror = _T_80 ? 1'h0 : i0_dp_raw_ror; // @[dec_decode_ctl.scala 334:33]
-  assign io_decode_exu_i0_ap_grev = _T_80 ? 1'h0 : i0_dp_raw_grev; // @[dec_decode_ctl.scala 335:33]
-  assign io_decode_exu_i0_ap_gorc = _T_80 ? 1'h0 : i0_dp_raw_gorc; // @[dec_decode_ctl.scala 336:33]
-  assign io_decode_exu_i0_ap_zbb = _T_80 ? 1'h0 : i0_dp_raw_zbb; // @[dec_decode_ctl.scala 337:33]
-  assign io_decode_exu_i0_ap_sbset = _T_80 ? 1'h0 : i0_dp_raw_sbset; // @[dec_decode_ctl.scala 338:33]
-  assign io_decode_exu_i0_ap_sbclr = _T_80 ? 1'h0 : i0_dp_raw_sbclr; // @[dec_decode_ctl.scala 339:33]
-  assign io_decode_exu_i0_ap_sbinv = _T_80 ? 1'h0 : i0_dp_raw_sbinv; // @[dec_decode_ctl.scala 340:33]
-  assign io_decode_exu_i0_ap_sbext = _T_80 ? 1'h0 : i0_dp_raw_sbext; // @[dec_decode_ctl.scala 341:33]
-  assign io_decode_exu_i0_ap_sh1add = _T_80 ? 1'h0 : i0_dp_raw_sh1add; // @[dec_decode_ctl.scala 322:33]
-  assign io_decode_exu_i0_ap_sh2add = _T_80 ? 1'h0 : i0_dp_raw_sh2add; // @[dec_decode_ctl.scala 323:33]
-  assign io_decode_exu_i0_ap_sh3add = _T_80 ? 1'h0 : i0_dp_raw_sh3add; // @[dec_decode_ctl.scala 324:33]
-  assign io_decode_exu_i0_ap_zba = _T_80 ? 1'h0 : i0_dp_raw_zba; // @[dec_decode_ctl.scala 325:33]
-  assign io_decode_exu_i0_ap_land = _T_80 ? 1'h0 : i0_dp_raw_land; // @[dec_decode_ctl.scala 305:33]
-  assign io_decode_exu_i0_ap_lor = _T_80 | i0_dp_raw_lor; // @[dec_decode_ctl.scala 306:33]
-  assign io_decode_exu_i0_ap_lxor = _T_80 ? 1'h0 : i0_dp_raw_lxor; // @[dec_decode_ctl.scala 307:33]
-  assign io_decode_exu_i0_ap_sll = _T_80 ? 1'h0 : i0_dp_raw_sll; // @[dec_decode_ctl.scala 308:33]
-  assign io_decode_exu_i0_ap_srl = _T_80 ? 1'h0 : i0_dp_raw_srl; // @[dec_decode_ctl.scala 309:33]
-  assign io_decode_exu_i0_ap_sra = _T_80 ? 1'h0 : i0_dp_raw_sra; // @[dec_decode_ctl.scala 310:33]
-  assign io_decode_exu_i0_ap_beq = _T_80 ? 1'h0 : i0_dp_raw_beq; // @[dec_decode_ctl.scala 313:33]
-  assign io_decode_exu_i0_ap_bne = _T_80 ? 1'h0 : i0_dp_raw_bne; // @[dec_decode_ctl.scala 314:33]
-  assign io_decode_exu_i0_ap_blt = _T_80 ? 1'h0 : i0_dp_raw_blt; // @[dec_decode_ctl.scala 315:33]
-  assign io_decode_exu_i0_ap_bge = _T_80 ? 1'h0 : i0_dp_raw_bge; // @[dec_decode_ctl.scala 316:33]
-  assign io_decode_exu_i0_ap_add = _T_80 ? 1'h0 : i0_dp_raw_add; // @[dec_decode_ctl.scala 303:33]
-  assign io_decode_exu_i0_ap_sub = _T_80 ? 1'h0 : i0_dp_raw_sub; // @[dec_decode_ctl.scala 304:33]
-  assign io_decode_exu_i0_ap_slt = _T_80 ? 1'h0 : i0_dp_raw_slt; // @[dec_decode_ctl.scala 311:33]
-  assign io_decode_exu_i0_ap_unsign = _T_80 ? 1'h0 : i0_dp_raw_unsign; // @[dec_decode_ctl.scala 312:33]
-  assign io_decode_exu_i0_ap_jal = _T_421 & _T_422; // @[dec_decode_ctl.scala 344:33]
-  assign io_decode_exu_i0_ap_predict_t = _T_86 & i0_predict_br; // @[dec_decode_ctl.scala 300:37]
-  assign io_decode_exu_i0_ap_predict_nt = _T_87 & i0_predict_br; // @[dec_decode_ctl.scala 299:37]
-  assign io_decode_exu_i0_ap_csr_write = i0_csr_write & _T_433; // @[dec_decode_ctl.scala 342:33]
-  assign io_decode_exu_i0_ap_csr_imm = _T_80 ? 1'h0 : i0_dp_raw_csr_imm; // @[dec_decode_ctl.scala 343:33]
-  assign io_decode_exu_dec_i0_predict_p_d_valid = i0_brp_valid & i0_legal_decode_d; // @[dec_decode_ctl.scala 232:57]
-  assign io_decode_exu_dec_i0_predict_p_d_bits_pc4 = io_dec_i0_pc4_d; // @[dec_decode_ctl.scala 230:57]
-  assign io_decode_exu_dec_i0_predict_p_d_bits_hist = io_dec_i0_brp_bits_hist; // @[dec_decode_ctl.scala 231:57]
-  assign io_decode_exu_dec_i0_predict_p_d_bits_toffset = _T_399 ? i0_pcall_imm[11:0] : _T_408; // @[dec_decode_ctl.scala 244:58]
-  assign io_decode_exu_dec_i0_predict_p_d_bits_br_error = _T_71 & _T_50; // @[dec_decode_ctl.scala 239:58]
-  assign io_decode_exu_dec_i0_predict_p_d_bits_br_start_error = _T_74 & _T_50; // @[dec_decode_ctl.scala 240:58]
-  assign io_decode_exu_dec_i0_predict_p_d_bits_pcall = i0_dp_jal & i0_pcall_case; // @[dec_decode_ctl.scala 226:57]
-  assign io_decode_exu_dec_i0_predict_p_d_bits_pja = i0_dp_jal & i0_pja_case; // @[dec_decode_ctl.scala 227:57]
-  assign io_decode_exu_dec_i0_predict_p_d_bits_way = io_dec_i0_brp_bits_way; // @[dec_decode_ctl.scala 246:58]
-  assign io_decode_exu_dec_i0_predict_p_d_bits_pret = i0_dp_jal & i0_pret_case; // @[dec_decode_ctl.scala 228:57]
-  assign io_decode_exu_dec_i0_predict_p_d_bits_prett = io_dec_i0_brp_bits_prett; // @[dec_decode_ctl.scala 229:57]
-  assign io_decode_exu_i0_predict_fghr_d = io_dec_i0_bp_fghr; // @[dec_decode_ctl.scala 245:58]
-  assign io_decode_exu_i0_predict_index_d = io_dec_i0_bp_index; // @[dec_decode_ctl.scala 241:58]
-  assign io_decode_exu_i0_predict_btag_d = io_dec_i0_bp_btag; // @[dec_decode_ctl.scala 242:58]
-  assign io_decode_exu_dec_i0_rs1_en_d = i0_dp_rs1 & _T_657; // @[dec_decode_ctl.scala 680:35]
-  assign io_decode_exu_dec_i0_branch_d = _T_610 | i0_br_error_all; // @[dec_decode_ctl.scala 631:37]
-  assign io_decode_exu_dec_i0_rs2_en_d = i0_dp_rs2 & _T_659; // @[dec_decode_ctl.scala 681:35]
-  assign io_decode_exu_dec_i0_immed_d = _T_787 | _T_784; // @[dec_decode_ctl.scala 693:32]
-  assign io_decode_exu_dec_i0_result_r = i0_result_r_raw; // @[dec_decode_ctl.scala 919:41]
-  assign io_decode_exu_dec_qual_lsu_d = _T_80 ? 1'h0 : i0_dp_raw_lsu; // @[dec_decode_ctl.scala 636:32]
-  assign io_decode_exu_dec_i0_select_pc_d = _T_80 ? 1'h0 : i0_dp_raw_pc; // @[dec_decode_ctl.scala 291:36]
-  assign io_decode_exu_dec_i0_rs1_bypass_en_d = {_T_1064,_T_1063}; // @[dec_decode_ctl.scala 916:45]
-  assign io_decode_exu_dec_i0_rs2_bypass_en_d = {_T_1079,_T_1078}; // @[dec_decode_ctl.scala 917:45]
-  assign io_decode_exu_mul_p_valid = i0_exulegal_decode_d & i0_dp_mul; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 471:32]
-  assign io_decode_exu_mul_p_bits_rs1_sign = _T_80 ? 1'h0 : i0_dp_raw_rs1_sign; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 472:37]
-  assign io_decode_exu_mul_p_bits_rs2_sign = _T_80 ? 1'h0 : i0_dp_raw_rs2_sign; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 473:37]
-  assign io_decode_exu_mul_p_bits_low = _T_80 ? 1'h0 : i0_dp_raw_low; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 474:37]
-  assign io_decode_exu_mul_p_bits_bext = _T_80 ? 1'h0 : i0_dp_raw_bext; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 475:37]
-  assign io_decode_exu_mul_p_bits_bdep = _T_80 ? 1'h0 : i0_dp_raw_bdep; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 476:37]
-  assign io_decode_exu_mul_p_bits_clmul = _T_80 ? 1'h0 : i0_dp_raw_clmul; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 477:37]
-  assign io_decode_exu_mul_p_bits_clmulh = _T_80 ? 1'h0 : i0_dp_raw_clmulh; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 478:37]
-  assign io_decode_exu_mul_p_bits_clmulr = _T_80 ? 1'h0 : i0_dp_raw_clmulr; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 479:37]
-  assign io_decode_exu_mul_p_bits_grev = _T_80 ? 1'h0 : i0_dp_raw_grev; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 480:37]
-  assign io_decode_exu_mul_p_bits_gorc = _T_80 ? 1'h0 : i0_dp_raw_gorc; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 481:37]
-  assign io_decode_exu_mul_p_bits_shfl = _T_80 ? 1'h0 : i0_dp_raw_shfl; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 482:37]
-  assign io_decode_exu_mul_p_bits_unshfl = _T_80 ? 1'h0 : i0_dp_raw_unshfl; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 483:37]
-  assign io_decode_exu_mul_p_bits_crc32_b = _T_80 ? 1'h0 : i0_dp_raw_crc32_b; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 484:37]
-  assign io_decode_exu_mul_p_bits_crc32_h = _T_80 ? 1'h0 : i0_dp_raw_crc32_h; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 485:37]
-  assign io_decode_exu_mul_p_bits_crc32_w = _T_80 ? 1'h0 : i0_dp_raw_crc32_w; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 486:37]
-  assign io_decode_exu_mul_p_bits_crc32c_b = _T_80 ? 1'h0 : i0_dp_raw_crc32c_b; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 487:37]
-  assign io_decode_exu_mul_p_bits_crc32c_h = _T_80 ? 1'h0 : i0_dp_raw_crc32c_h; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 488:37]
-  assign io_decode_exu_mul_p_bits_crc32c_w = _T_80 ? 1'h0 : i0_dp_raw_crc32c_w; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 489:37]
-  assign io_decode_exu_mul_p_bits_bfp = _T_80 ? 1'h0 : i0_dp_raw_bfp; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 490:37]
-  assign io_decode_exu_pred_correct_npc_x = temp_pred_correct_npc_x[31:1]; // @[dec_decode_ctl.scala 877:36]
-  assign io_decode_exu_dec_extint_stall = _T_12; // @[dec_decode_ctl.scala 208:35]
-  assign io_dec_alu_dec_i0_alu_decode_d = i0_exulegal_decode_d & i0_dp_alu; // @[dec_decode_ctl.scala 630:34]
-  assign io_dec_alu_dec_csr_ren_d = i0_dp_csr_read & io_dec_ib0_valid_d; // @[dec_decode_ctl.scala 516:29]
-  assign io_dec_alu_dec_i0_br_immed_d = _T_885 ? i0_br_offset : _T_898; // @[dec_decode_ctl.scala 823:32]
-  assign io_dec_div_div_p_valid = i0_exulegal_decode_d & i0_dp_div; // @[dec_decode_ctl.scala 467:29]
-  assign io_dec_div_div_p_bits_unsign = _T_80 ? 1'h0 : i0_dp_raw_unsign; // @[dec_decode_ctl.scala 468:34]
-  assign io_dec_div_div_p_bits_rem = _T_80 ? 1'h0 : i0_dp_raw_rem; // @[dec_decode_ctl.scala 469:34]
-  assign io_dec_div_dec_div_cancel = _T_927 | _T_932; // @[dec_decode_ctl.scala 842:37]
-  assign io_dec_aln_dec_i0_decode_d = _T_589 & _T_567; // @[dec_decode_ctl.scala 611:30 dec_decode_ctl.scala 674:30]
-  assign io_dec_i0_inst_wb = i0_inst_wb; // @[dec_decode_ctl.scala 868:21]
-  assign io_dec_i0_pc_wb = i0_pc_wb; // @[dec_decode_ctl.scala 869:19]
-  assign io_dec_i0_rs1_d = io_dec_i0_instr_d[19:15]; // @[dec_decode_ctl.scala 683:19]
-  assign io_dec_i0_rs2_d = io_dec_i0_instr_d[24:20]; // @[dec_decode_ctl.scala 684:19]
-  assign io_dec_i0_waddr_r = r_d_bits_i0rd; // @[dec_decode_ctl.scala 805:27]
-  assign io_dec_i0_wen_r = _T_871 & _T_872; // @[dec_decode_ctl.scala 807:32]
-  assign io_dec_i0_wdata_r = _T_881 ? io_lsu_result_corr_r : i0_result_r_raw; // @[dec_decode_ctl.scala 808:26]
-  assign io_lsu_p_valid = io_decode_exu_dec_extint_stall | lsu_decode_d; // @[dec_decode_ctl.scala 493:12 dec_decode_ctl.scala 498:24 dec_decode_ctl.scala 502:35]
-  assign io_lsu_p_bits_fast_int = io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 493:12 dec_decode_ctl.scala 497:29]
-  assign io_lsu_p_bits_stack = io_decode_exu_dec_extint_stall ? 1'h0 : _T_425; // @[dec_decode_ctl.scala 493:12 dec_decode_ctl.scala 508:29]
-  assign io_lsu_p_bits_by = io_decode_exu_dec_extint_stall ? 1'h0 : i0_dp_by; // @[dec_decode_ctl.scala 493:12 dec_decode_ctl.scala 505:40]
-  assign io_lsu_p_bits_half = io_decode_exu_dec_extint_stall ? 1'h0 : i0_dp_half; // @[dec_decode_ctl.scala 493:12 dec_decode_ctl.scala 506:40]
-  assign io_lsu_p_bits_word = io_decode_exu_dec_extint_stall | i0_dp_word; // @[dec_decode_ctl.scala 493:12 dec_decode_ctl.scala 496:29 dec_decode_ctl.scala 507:40]
-  assign io_lsu_p_bits_load = io_decode_exu_dec_extint_stall | i0_dp_load; // @[dec_decode_ctl.scala 493:12 dec_decode_ctl.scala 495:29 dec_decode_ctl.scala 503:40]
-  assign io_lsu_p_bits_store = io_decode_exu_dec_extint_stall ? 1'h0 : i0_dp_store; // @[dec_decode_ctl.scala 493:12 dec_decode_ctl.scala 504:40]
-  assign io_lsu_p_bits_unsign = io_decode_exu_dec_extint_stall ? 1'h0 : i0_dp_unsign; // @[dec_decode_ctl.scala 493:12 dec_decode_ctl.scala 512:40]
-  assign io_lsu_p_bits_store_data_bypass_d = io_decode_exu_dec_extint_stall ? 1'h0 : store_data_bypass_d; // @[dec_decode_ctl.scala 493:12 dec_decode_ctl.scala 510:40]
-  assign io_lsu_p_bits_load_ldst_bypass_d = io_decode_exu_dec_extint_stall ? 1'h0 : load_ldst_bypass_d; // @[dec_decode_ctl.scala 493:12 dec_decode_ctl.scala 509:40]
-  assign io_div_waddr_wb = _T_947; // @[dec_decode_ctl.scala 860:19]
-  assign io_dec_lsu_valid_raw_d = _T_1086 | io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 921:26]
-  assign io_dec_lsu_offset_d = _T_1100 | _T_1101; // @[dec_decode_ctl.scala 922:23]
-  assign io_dec_csr_wen_unq_d = _T_436 & io_dec_ib0_valid_d; // @[dec_decode_ctl.scala 525:24]
-  assign io_dec_csr_any_unq_d = any_csr_d & io_dec_ib0_valid_d; // @[dec_decode_ctl.scala 528:24]
-  assign io_dec_csr_rdaddr_d = _T_440 & io_dec_i0_instr_d[31:20]; // @[dec_decode_ctl.scala 529:24]
-  assign io_dec_csr_wen_r = _T_443 & _T_868; // @[dec_decode_ctl.scala 534:20]
-  assign io_dec_csr_wraddr_r = _T_445 & r_d_bits_csrwaddr; // @[dec_decode_ctl.scala 530:24]
-  assign io_dec_csr_wrdata_r = _T_529 ? i0_result_corr_r : write_csr_data; // @[dec_decode_ctl.scala 574:24]
-  assign io_dec_csr_stall_int_ff = _T_454 & _T_455; // @[dec_decode_ctl.scala 537:27]
-  assign io_dec_tlu_i0_valid_r = r_d_valid & _T_857; // @[dec_decode_ctl.scala 637:29]
-  assign io_dec_tlu_packet_r_legal = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_legal; // @[dec_decode_ctl.scala 669:39]
-  assign io_dec_tlu_packet_r_icaf = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf; // @[dec_decode_ctl.scala 669:39]
-  assign io_dec_tlu_packet_r_icaf_second = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf_second; // @[dec_decode_ctl.scala 669:39]
-  assign io_dec_tlu_packet_r_icaf_type = io_dec_tlu_flush_lower_wb ? 2'h0 : r_t_icaf_type; // @[dec_decode_ctl.scala 669:39]
-  assign io_dec_tlu_packet_r_fence_i = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_fence_i; // @[dec_decode_ctl.scala 669:39]
-  assign io_dec_tlu_packet_r_i0trigger = io_dec_tlu_flush_lower_wb ? 4'h0 : _T_644; // @[dec_decode_ctl.scala 669:39]
-  assign io_dec_tlu_packet_r_pmu_i0_itype = io_dec_tlu_flush_lower_wb ? 4'h0 : r_t_pmu_i0_itype; // @[dec_decode_ctl.scala 669:39]
-  assign io_dec_tlu_packet_r_pmu_i0_br_unpred = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_pmu_i0_br_unpred; // @[dec_decode_ctl.scala 669:39]
-  assign io_dec_tlu_packet_r_pmu_divide = r_d_bits_i0div & r_d_valid; // @[dec_decode_ctl.scala 669:39 dec_decode_ctl.scala 670:39]
-  assign io_dec_tlu_packet_r_pmu_lsu_misaligned = io_dec_tlu_flush_lower_wb ? 1'h0 : lsu_pmu_misaligned_r; // @[dec_decode_ctl.scala 669:39]
-  assign io_dec_tlu_i0_pc_r = dec_i0_pc_r; // @[dec_decode_ctl.scala 872:27]
-  assign io_dec_illegal_inst = _T_565; // @[dec_decode_ctl.scala 596:23]
-  assign io_dec_pmu_instr_decoded = io_dec_aln_dec_i0_decode_d; // @[dec_decode_ctl.scala 616:28]
-  assign io_dec_pmu_decode_stall = io_dec_ib0_valid_d & _T_597; // @[dec_decode_ctl.scala 617:27]
-  assign io_dec_pmu_presync_stall = presync_stall & io_dec_ib0_valid_d; // @[dec_decode_ctl.scala 619:29]
-  assign io_dec_pmu_postsync_stall = postsync_stall & io_dec_ib0_valid_d; // @[dec_decode_ctl.scala 618:29]
-  assign io_dec_nonblock_load_wen = _T_279 & _T_280; // @[dec_decode_ctl.scala 399:28]
-  assign io_dec_nonblock_load_waddr = _T_325 | _T_317; // @[dec_decode_ctl.scala 396:29 dec_decode_ctl.scala 406:29]
-  assign io_dec_pause_state = pause_stall; // @[dec_decode_ctl.scala 560:22]
-  assign io_dec_pause_state_cg = pause_stall & _T_519; // @[dec_decode_ctl.scala 562:25]
-  assign io_dec_div_active = _T_42; // @[dec_decode_ctl.scala 217:35]
-  assign i0_dec_io_ins = io_dec_i0_instr_d; // @[dec_decode_ctl.scala 439:16]
+  assign io_decode_exu_dec_data_en = {i0_x_data_en,i0_r_data_en}; // @[dec_decode_ctl.scala 775:38]
+  assign io_decode_exu_dec_ctl_en = {i0_x_ctl_en,i0_r_ctl_en}; // @[dec_decode_ctl.scala 776:38]
+  assign io_decode_exu_i0_ap_clz = _T_80 ? 1'h0 : i0_dp_raw_clz; // @[dec_decode_ctl.scala 319:33]
+  assign io_decode_exu_i0_ap_ctz = _T_80 ? 1'h0 : i0_dp_raw_ctz; // @[dec_decode_ctl.scala 320:33]
+  assign io_decode_exu_i0_ap_pcnt = _T_80 ? 1'h0 : i0_dp_raw_pcnt; // @[dec_decode_ctl.scala 321:33]
+  assign io_decode_exu_i0_ap_sext_b = _T_80 ? 1'h0 : i0_dp_raw_sext_b; // @[dec_decode_ctl.scala 322:33]
+  assign io_decode_exu_i0_ap_sext_h = _T_80 ? 1'h0 : i0_dp_raw_sext_h; // @[dec_decode_ctl.scala 323:33]
+  assign io_decode_exu_i0_ap_slo = _T_80 ? 1'h0 : i0_dp_raw_slo; // @[dec_decode_ctl.scala 328:33]
+  assign io_decode_exu_i0_ap_sro = _T_80 ? 1'h0 : i0_dp_raw_sro; // @[dec_decode_ctl.scala 329:33]
+  assign io_decode_exu_i0_ap_min = _T_80 ? 1'h0 : i0_dp_raw_min; // @[dec_decode_ctl.scala 330:33]
+  assign io_decode_exu_i0_ap_max = _T_80 ? 1'h0 : i0_dp_raw_max; // @[dec_decode_ctl.scala 331:33]
+  assign io_decode_exu_i0_ap_pack = _T_80 ? 1'h0 : i0_dp_raw_pack; // @[dec_decode_ctl.scala 332:33]
+  assign io_decode_exu_i0_ap_packu = _T_80 ? 1'h0 : i0_dp_raw_packu; // @[dec_decode_ctl.scala 333:33]
+  assign io_decode_exu_i0_ap_packh = _T_80 ? 1'h0 : i0_dp_raw_packh; // @[dec_decode_ctl.scala 334:33]
+  assign io_decode_exu_i0_ap_rol = _T_80 ? 1'h0 : i0_dp_raw_rol; // @[dec_decode_ctl.scala 335:33]
+  assign io_decode_exu_i0_ap_ror = _T_80 ? 1'h0 : i0_dp_raw_ror; // @[dec_decode_ctl.scala 336:33]
+  assign io_decode_exu_i0_ap_grev = _T_80 ? 1'h0 : i0_dp_raw_grev; // @[dec_decode_ctl.scala 337:33]
+  assign io_decode_exu_i0_ap_gorc = _T_80 ? 1'h0 : i0_dp_raw_gorc; // @[dec_decode_ctl.scala 338:33]
+  assign io_decode_exu_i0_ap_zbb = _T_80 ? 1'h0 : i0_dp_raw_zbb; // @[dec_decode_ctl.scala 339:33]
+  assign io_decode_exu_i0_ap_sbset = _T_80 ? 1'h0 : i0_dp_raw_sbset; // @[dec_decode_ctl.scala 340:33]
+  assign io_decode_exu_i0_ap_sbclr = _T_80 ? 1'h0 : i0_dp_raw_sbclr; // @[dec_decode_ctl.scala 341:33]
+  assign io_decode_exu_i0_ap_sbinv = _T_80 ? 1'h0 : i0_dp_raw_sbinv; // @[dec_decode_ctl.scala 342:33]
+  assign io_decode_exu_i0_ap_sbext = _T_80 ? 1'h0 : i0_dp_raw_sbext; // @[dec_decode_ctl.scala 343:33]
+  assign io_decode_exu_i0_ap_sh1add = _T_80 ? 1'h0 : i0_dp_raw_sh1add; // @[dec_decode_ctl.scala 324:33]
+  assign io_decode_exu_i0_ap_sh2add = _T_80 ? 1'h0 : i0_dp_raw_sh2add; // @[dec_decode_ctl.scala 325:33]
+  assign io_decode_exu_i0_ap_sh3add = _T_80 ? 1'h0 : i0_dp_raw_sh3add; // @[dec_decode_ctl.scala 326:33]
+  assign io_decode_exu_i0_ap_zba = _T_80 ? 1'h0 : i0_dp_raw_zba; // @[dec_decode_ctl.scala 327:33]
+  assign io_decode_exu_i0_ap_land = _T_80 ? 1'h0 : i0_dp_raw_land; // @[dec_decode_ctl.scala 307:33]
+  assign io_decode_exu_i0_ap_lor = _T_80 | i0_dp_raw_lor; // @[dec_decode_ctl.scala 308:33]
+  assign io_decode_exu_i0_ap_lxor = _T_80 ? 1'h0 : i0_dp_raw_lxor; // @[dec_decode_ctl.scala 309:33]
+  assign io_decode_exu_i0_ap_sll = _T_80 ? 1'h0 : i0_dp_raw_sll; // @[dec_decode_ctl.scala 310:33]
+  assign io_decode_exu_i0_ap_srl = _T_80 ? 1'h0 : i0_dp_raw_srl; // @[dec_decode_ctl.scala 311:33]
+  assign io_decode_exu_i0_ap_sra = _T_80 ? 1'h0 : i0_dp_raw_sra; // @[dec_decode_ctl.scala 312:33]
+  assign io_decode_exu_i0_ap_beq = _T_80 ? 1'h0 : i0_dp_raw_beq; // @[dec_decode_ctl.scala 315:33]
+  assign io_decode_exu_i0_ap_bne = _T_80 ? 1'h0 : i0_dp_raw_bne; // @[dec_decode_ctl.scala 316:33]
+  assign io_decode_exu_i0_ap_blt = _T_80 ? 1'h0 : i0_dp_raw_blt; // @[dec_decode_ctl.scala 317:33]
+  assign io_decode_exu_i0_ap_bge = _T_80 ? 1'h0 : i0_dp_raw_bge; // @[dec_decode_ctl.scala 318:33]
+  assign io_decode_exu_i0_ap_add = _T_80 ? 1'h0 : i0_dp_raw_add; // @[dec_decode_ctl.scala 305:33]
+  assign io_decode_exu_i0_ap_sub = _T_80 ? 1'h0 : i0_dp_raw_sub; // @[dec_decode_ctl.scala 306:33]
+  assign io_decode_exu_i0_ap_slt = _T_80 ? 1'h0 : i0_dp_raw_slt; // @[dec_decode_ctl.scala 313:33]
+  assign io_decode_exu_i0_ap_unsign = _T_80 ? 1'h0 : i0_dp_raw_unsign; // @[dec_decode_ctl.scala 314:33]
+  assign io_decode_exu_i0_ap_jal = _T_421 & _T_422; // @[dec_decode_ctl.scala 346:33]
+  assign io_decode_exu_i0_ap_predict_t = _T_86 & i0_predict_br; // @[dec_decode_ctl.scala 302:37]
+  assign io_decode_exu_i0_ap_predict_nt = _T_87 & i0_predict_br; // @[dec_decode_ctl.scala 301:37]
+  assign io_decode_exu_i0_ap_csr_write = i0_csr_write & _T_433; // @[dec_decode_ctl.scala 344:33]
+  assign io_decode_exu_i0_ap_csr_imm = _T_80 ? 1'h0 : i0_dp_raw_csr_imm; // @[dec_decode_ctl.scala 345:33]
+  assign io_decode_exu_dec_i0_predict_p_d_valid = i0_brp_valid & i0_legal_decode_d; // @[dec_decode_ctl.scala 234:57]
+  assign io_decode_exu_dec_i0_predict_p_d_bits_pc4 = io_dec_i0_pc4_d; // @[dec_decode_ctl.scala 232:57]
+  assign io_decode_exu_dec_i0_predict_p_d_bits_hist = io_dec_i0_brp_bits_hist; // @[dec_decode_ctl.scala 233:57]
+  assign io_decode_exu_dec_i0_predict_p_d_bits_toffset = _T_399 ? i0_pcall_imm[11:0] : _T_408; // @[dec_decode_ctl.scala 246:58]
+  assign io_decode_exu_dec_i0_predict_p_d_bits_br_error = _T_71 & _T_50; // @[dec_decode_ctl.scala 241:58]
+  assign io_decode_exu_dec_i0_predict_p_d_bits_br_start_error = _T_74 & _T_50; // @[dec_decode_ctl.scala 242:58]
+  assign io_decode_exu_dec_i0_predict_p_d_bits_pcall = i0_dp_jal & i0_pcall_case; // @[dec_decode_ctl.scala 228:57]
+  assign io_decode_exu_dec_i0_predict_p_d_bits_pja = i0_dp_jal & i0_pja_case; // @[dec_decode_ctl.scala 229:57]
+  assign io_decode_exu_dec_i0_predict_p_d_bits_way = io_dec_i0_brp_bits_way; // @[dec_decode_ctl.scala 248:58]
+  assign io_decode_exu_dec_i0_predict_p_d_bits_pret = i0_dp_jal & i0_pret_case; // @[dec_decode_ctl.scala 230:57]
+  assign io_decode_exu_dec_i0_predict_p_d_bits_prett = io_dec_i0_brp_bits_prett; // @[dec_decode_ctl.scala 231:57]
+  assign io_decode_exu_i0_predict_fghr_d = io_dec_i0_bp_fghr; // @[dec_decode_ctl.scala 247:58]
+  assign io_decode_exu_i0_predict_index_d = io_dec_i0_bp_index; // @[dec_decode_ctl.scala 243:58]
+  assign io_decode_exu_i0_predict_btag_d = io_dec_i0_bp_btag; // @[dec_decode_ctl.scala 244:58]
+  assign io_decode_exu_dec_i0_rs1_en_d = i0_dp_rs1 & _T_657; // @[dec_decode_ctl.scala 682:35]
+  assign io_decode_exu_dec_i0_branch_d = _T_610 | i0_br_error_all; // @[dec_decode_ctl.scala 633:37]
+  assign io_decode_exu_dec_i0_rs2_en_d = i0_dp_rs2 & _T_659; // @[dec_decode_ctl.scala 683:35]
+  assign io_decode_exu_dec_i0_immed_d = _T_787 | _T_784; // @[dec_decode_ctl.scala 695:32]
+  assign io_decode_exu_dec_i0_result_r = i0_result_r_raw; // @[dec_decode_ctl.scala 921:41]
+  assign io_decode_exu_dec_qual_lsu_d = _T_80 ? 1'h0 : i0_dp_raw_lsu; // @[dec_decode_ctl.scala 638:32]
+  assign io_decode_exu_dec_i0_select_pc_d = _T_80 ? 1'h0 : i0_dp_raw_pc; // @[dec_decode_ctl.scala 293:36]
+  assign io_decode_exu_dec_i0_rs1_bypass_en_d = {_T_1064,_T_1063}; // @[dec_decode_ctl.scala 918:45]
+  assign io_decode_exu_dec_i0_rs2_bypass_en_d = {_T_1079,_T_1078}; // @[dec_decode_ctl.scala 919:45]
+  assign io_decode_exu_mul_p_valid = i0_exulegal_decode_d & i0_dp_mul; // @[dec_decode_ctl.scala 118:25 dec_decode_ctl.scala 473:32]
+  assign io_decode_exu_mul_p_bits_rs1_sign = _T_80 ? 1'h0 : i0_dp_raw_rs1_sign; // @[dec_decode_ctl.scala 118:25 dec_decode_ctl.scala 474:37]
+  assign io_decode_exu_mul_p_bits_rs2_sign = _T_80 ? 1'h0 : i0_dp_raw_rs2_sign; // @[dec_decode_ctl.scala 118:25 dec_decode_ctl.scala 475:37]
+  assign io_decode_exu_mul_p_bits_low = _T_80 ? 1'h0 : i0_dp_raw_low; // @[dec_decode_ctl.scala 118:25 dec_decode_ctl.scala 476:37]
+  assign io_decode_exu_mul_p_bits_bext = _T_80 ? 1'h0 : i0_dp_raw_bext; // @[dec_decode_ctl.scala 118:25 dec_decode_ctl.scala 477:37]
+  assign io_decode_exu_mul_p_bits_bdep = _T_80 ? 1'h0 : i0_dp_raw_bdep; // @[dec_decode_ctl.scala 118:25 dec_decode_ctl.scala 478:37]
+  assign io_decode_exu_mul_p_bits_clmul = _T_80 ? 1'h0 : i0_dp_raw_clmul; // @[dec_decode_ctl.scala 118:25 dec_decode_ctl.scala 479:37]
+  assign io_decode_exu_mul_p_bits_clmulh = _T_80 ? 1'h0 : i0_dp_raw_clmulh; // @[dec_decode_ctl.scala 118:25 dec_decode_ctl.scala 480:37]
+  assign io_decode_exu_mul_p_bits_clmulr = _T_80 ? 1'h0 : i0_dp_raw_clmulr; // @[dec_decode_ctl.scala 118:25 dec_decode_ctl.scala 481:37]
+  assign io_decode_exu_mul_p_bits_grev = _T_80 ? 1'h0 : i0_dp_raw_grev; // @[dec_decode_ctl.scala 118:25 dec_decode_ctl.scala 482:37]
+  assign io_decode_exu_mul_p_bits_gorc = _T_80 ? 1'h0 : i0_dp_raw_gorc; // @[dec_decode_ctl.scala 118:25 dec_decode_ctl.scala 483:37]
+  assign io_decode_exu_mul_p_bits_shfl = _T_80 ? 1'h0 : i0_dp_raw_shfl; // @[dec_decode_ctl.scala 118:25 dec_decode_ctl.scala 484:37]
+  assign io_decode_exu_mul_p_bits_unshfl = _T_80 ? 1'h0 : i0_dp_raw_unshfl; // @[dec_decode_ctl.scala 118:25 dec_decode_ctl.scala 485:37]
+  assign io_decode_exu_mul_p_bits_crc32_b = _T_80 ? 1'h0 : i0_dp_raw_crc32_b; // @[dec_decode_ctl.scala 118:25 dec_decode_ctl.scala 486:37]
+  assign io_decode_exu_mul_p_bits_crc32_h = _T_80 ? 1'h0 : i0_dp_raw_crc32_h; // @[dec_decode_ctl.scala 118:25 dec_decode_ctl.scala 487:37]
+  assign io_decode_exu_mul_p_bits_crc32_w = _T_80 ? 1'h0 : i0_dp_raw_crc32_w; // @[dec_decode_ctl.scala 118:25 dec_decode_ctl.scala 488:37]
+  assign io_decode_exu_mul_p_bits_crc32c_b = _T_80 ? 1'h0 : i0_dp_raw_crc32c_b; // @[dec_decode_ctl.scala 118:25 dec_decode_ctl.scala 489:37]
+  assign io_decode_exu_mul_p_bits_crc32c_h = _T_80 ? 1'h0 : i0_dp_raw_crc32c_h; // @[dec_decode_ctl.scala 118:25 dec_decode_ctl.scala 490:37]
+  assign io_decode_exu_mul_p_bits_crc32c_w = _T_80 ? 1'h0 : i0_dp_raw_crc32c_w; // @[dec_decode_ctl.scala 118:25 dec_decode_ctl.scala 491:37]
+  assign io_decode_exu_mul_p_bits_bfp = _T_80 ? 1'h0 : i0_dp_raw_bfp; // @[dec_decode_ctl.scala 118:25 dec_decode_ctl.scala 492:37]
+  assign io_decode_exu_pred_correct_npc_x = temp_pred_correct_npc_x[31:1]; // @[dec_decode_ctl.scala 879:36]
+  assign io_decode_exu_dec_extint_stall = _T_12; // @[dec_decode_ctl.scala 210:35]
+  assign io_dec_alu_dec_i0_alu_decode_d = i0_exulegal_decode_d & i0_dp_alu; // @[dec_decode_ctl.scala 632:34]
+  assign io_dec_alu_dec_csr_ren_d = i0_dp_csr_read & io_dec_ib0_valid_d; // @[dec_decode_ctl.scala 518:29]
+  assign io_dec_alu_dec_i0_br_immed_d = _T_885 ? i0_br_offset : _T_898; // @[dec_decode_ctl.scala 825:32]
+  assign io_dec_div_div_p_valid = i0_exulegal_decode_d & i0_dp_div; // @[dec_decode_ctl.scala 469:29]
+  assign io_dec_div_div_p_bits_unsign = _T_80 ? 1'h0 : i0_dp_raw_unsign; // @[dec_decode_ctl.scala 470:34]
+  assign io_dec_div_div_p_bits_rem = _T_80 ? 1'h0 : i0_dp_raw_rem; // @[dec_decode_ctl.scala 471:34]
+  assign io_dec_div_dec_div_cancel = _T_927 | _T_932; // @[dec_decode_ctl.scala 844:37]
+  assign io_dec_i0_inst_wb = i0_inst_wb; // @[dec_decode_ctl.scala 870:21]
+  assign io_dec_i0_pc_wb = i0_pc_wb; // @[dec_decode_ctl.scala 871:19]
+  assign io_dec_i0_rs1_d = io_dec_i0_instr_d[19:15]; // @[dec_decode_ctl.scala 685:19]
+  assign io_dec_i0_rs2_d = io_dec_i0_instr_d[24:20]; // @[dec_decode_ctl.scala 686:19]
+  assign io_dec_i0_waddr_r = r_d_bits_i0rd; // @[dec_decode_ctl.scala 807:27]
+  assign io_dec_i0_wen_r = _T_871 & _T_872; // @[dec_decode_ctl.scala 809:32]
+  assign io_dec_i0_wdata_r = _T_881 ? io_lsu_result_corr_r : i0_result_r_raw; // @[dec_decode_ctl.scala 810:26]
+  assign io_lsu_p_valid = io_decode_exu_dec_extint_stall | lsu_decode_d; // @[dec_decode_ctl.scala 495:12 dec_decode_ctl.scala 500:24 dec_decode_ctl.scala 504:35]
+  assign io_lsu_p_bits_fast_int = io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 495:12 dec_decode_ctl.scala 499:29]
+  assign io_lsu_p_bits_stack = io_decode_exu_dec_extint_stall ? 1'h0 : _T_425; // @[dec_decode_ctl.scala 495:12 dec_decode_ctl.scala 510:29]
+  assign io_lsu_p_bits_by = io_decode_exu_dec_extint_stall ? 1'h0 : i0_dp_by; // @[dec_decode_ctl.scala 495:12 dec_decode_ctl.scala 507:40]
+  assign io_lsu_p_bits_half = io_decode_exu_dec_extint_stall ? 1'h0 : i0_dp_half; // @[dec_decode_ctl.scala 495:12 dec_decode_ctl.scala 508:40]
+  assign io_lsu_p_bits_word = io_decode_exu_dec_extint_stall | i0_dp_word; // @[dec_decode_ctl.scala 495:12 dec_decode_ctl.scala 498:29 dec_decode_ctl.scala 509:40]
+  assign io_lsu_p_bits_load = io_decode_exu_dec_extint_stall | i0_dp_load; // @[dec_decode_ctl.scala 495:12 dec_decode_ctl.scala 497:29 dec_decode_ctl.scala 505:40]
+  assign io_lsu_p_bits_store = io_decode_exu_dec_extint_stall ? 1'h0 : i0_dp_store; // @[dec_decode_ctl.scala 495:12 dec_decode_ctl.scala 506:40]
+  assign io_lsu_p_bits_unsign = io_decode_exu_dec_extint_stall ? 1'h0 : i0_dp_unsign; // @[dec_decode_ctl.scala 495:12 dec_decode_ctl.scala 514:40]
+  assign io_lsu_p_bits_store_data_bypass_d = io_decode_exu_dec_extint_stall ? 1'h0 : store_data_bypass_d; // @[dec_decode_ctl.scala 495:12 dec_decode_ctl.scala 512:40]
+  assign io_lsu_p_bits_load_ldst_bypass_d = io_decode_exu_dec_extint_stall ? 1'h0 : load_ldst_bypass_d; // @[dec_decode_ctl.scala 495:12 dec_decode_ctl.scala 511:40]
+  assign io_div_waddr_wb = _T_947; // @[dec_decode_ctl.scala 862:19]
+  assign io_dec_lsu_valid_raw_d = _T_1086 | io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 923:26]
+  assign io_dec_lsu_offset_d = _T_1100 | _T_1101; // @[dec_decode_ctl.scala 924:23]
+  assign io_dec_csr_wen_unq_d = _T_436 & io_dec_ib0_valid_d; // @[dec_decode_ctl.scala 527:24]
+  assign io_dec_csr_any_unq_d = any_csr_d & io_dec_ib0_valid_d; // @[dec_decode_ctl.scala 530:24]
+  assign io_dec_csr_rdaddr_d = _T_440 & io_dec_i0_instr_d[31:20]; // @[dec_decode_ctl.scala 531:24]
+  assign io_dec_csr_wen_r = _T_443 & _T_868; // @[dec_decode_ctl.scala 536:20]
+  assign io_dec_csr_wraddr_r = _T_445 & r_d_bits_csrwaddr; // @[dec_decode_ctl.scala 532:24]
+  assign io_dec_csr_wrdata_r = _T_529 ? i0_result_corr_r : write_csr_data; // @[dec_decode_ctl.scala 576:24]
+  assign io_dec_csr_stall_int_ff = _T_454 & _T_455; // @[dec_decode_ctl.scala 539:27]
+  assign io_dec_tlu_i0_valid_r = r_d_valid & _T_857; // @[dec_decode_ctl.scala 639:29]
+  assign io_dec_tlu_packet_r_legal = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_legal; // @[dec_decode_ctl.scala 671:39]
+  assign io_dec_tlu_packet_r_icaf = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf; // @[dec_decode_ctl.scala 671:39]
+  assign io_dec_tlu_packet_r_icaf_second = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf_second; // @[dec_decode_ctl.scala 671:39]
+  assign io_dec_tlu_packet_r_icaf_type = io_dec_tlu_flush_lower_wb ? 2'h0 : r_t_icaf_type; // @[dec_decode_ctl.scala 671:39]
+  assign io_dec_tlu_packet_r_fence_i = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_fence_i; // @[dec_decode_ctl.scala 671:39]
+  assign io_dec_tlu_packet_r_i0trigger = io_dec_tlu_flush_lower_wb ? 4'h0 : _T_644; // @[dec_decode_ctl.scala 671:39]
+  assign io_dec_tlu_packet_r_pmu_i0_itype = io_dec_tlu_flush_lower_wb ? 4'h0 : r_t_pmu_i0_itype; // @[dec_decode_ctl.scala 671:39]
+  assign io_dec_tlu_packet_r_pmu_i0_br_unpred = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_pmu_i0_br_unpred; // @[dec_decode_ctl.scala 671:39]
+  assign io_dec_tlu_packet_r_pmu_divide = r_d_bits_i0div & r_d_valid; // @[dec_decode_ctl.scala 671:39 dec_decode_ctl.scala 672:39]
+  assign io_dec_tlu_packet_r_pmu_lsu_misaligned = io_dec_tlu_flush_lower_wb ? 1'h0 : lsu_pmu_misaligned_r; // @[dec_decode_ctl.scala 671:39]
+  assign io_dec_tlu_i0_pc_r = dec_i0_pc_r; // @[dec_decode_ctl.scala 874:27]
+  assign io_dec_illegal_inst = _T_565; // @[dec_decode_ctl.scala 598:23]
+  assign io_dec_pmu_instr_decoded = io_dec_i0_decode_d; // @[dec_decode_ctl.scala 618:28]
+  assign io_dec_pmu_decode_stall = io_dec_ib0_valid_d & _T_597; // @[dec_decode_ctl.scala 619:27]
+  assign io_dec_pmu_presync_stall = presync_stall & io_dec_ib0_valid_d; // @[dec_decode_ctl.scala 621:29]
+  assign io_dec_pmu_postsync_stall = postsync_stall & io_dec_ib0_valid_d; // @[dec_decode_ctl.scala 620:29]
+  assign io_dec_nonblock_load_wen = _T_279 & _T_280; // @[dec_decode_ctl.scala 401:28]
+  assign io_dec_nonblock_load_waddr = _T_325 | _T_317; // @[dec_decode_ctl.scala 398:29 dec_decode_ctl.scala 408:29]
+  assign io_dec_pause_state = pause_stall; // @[dec_decode_ctl.scala 562:22]
+  assign io_dec_pause_state_cg = pause_stall & _T_519; // @[dec_decode_ctl.scala 564:25]
+  assign io_dec_div_active = _T_42; // @[dec_decode_ctl.scala 219:35]
+  assign io_dec_i0_decode_d = _T_589 & _T_567; // @[dec_decode_ctl.scala 613:22 dec_decode_ctl.scala 676:22]
+  assign i0_dec_io_ins = io_dec_i0_instr_d; // @[dec_decode_ctl.scala 441:16]
   assign rvclkhdr_io_clk = clock; // @[lib.scala 406:18]
   assign rvclkhdr_io_en = i0_x_data_en & any_csr_d; // @[lib.scala 407:17]
   assign rvclkhdr_1_io_clk = clock; // @[lib.scala 406:18]
@@ -3793,7 +3793,7 @@ end // initial
     if (reset) begin
       x_d_valid <= 1'h0;
     end else if (i0_x_ctl_en) begin
-      x_d_valid <= io_dec_aln_dec_i0_decode_d;
+      x_d_valid <= io_dec_i0_decode_d;
     end
   end
   always @(posedge io_free_l2clk or posedge reset) begin
@@ -8127,6 +8127,7 @@ module csr_tlu(
   input         io_dec_tlu_i0_valid_r,
   input         io_dec_csr_any_unq_d,
   output        io_dec_tlu_misc_clk_override,
+  output        io_dec_tlu_picio_clk_override,
   output        io_dec_tlu_dec_clk_override,
   output        io_dec_tlu_ifu_clk_override,
   output        io_dec_tlu_lsu_clk_override,
@@ -9632,6 +9633,7 @@ module csr_tlu(
   assign io_dec_tlu_perfcnt2 = perf_csrs_io_dec_tlu_perfcnt2; // @[dec_tlu_ctl.scala 2438:29]
   assign io_dec_tlu_perfcnt3 = perf_csrs_io_dec_tlu_perfcnt3; // @[dec_tlu_ctl.scala 2439:29]
   assign io_dec_tlu_misc_clk_override = mcgc[8]; // @[dec_tlu_ctl.scala 1757:38]
+  assign io_dec_tlu_picio_clk_override = mcgc[9]; // @[dec_tlu_ctl.scala 1756:39]
   assign io_dec_tlu_dec_clk_override = mcgc[7]; // @[dec_tlu_ctl.scala 1758:38]
   assign io_dec_tlu_ifu_clk_override = mcgc[5]; // @[dec_tlu_ctl.scala 1759:38]
   assign io_dec_tlu_lsu_clk_override = mcgc[4]; // @[dec_tlu_ctl.scala 1760:38]
@@ -11464,6 +11466,7 @@ module dec_tlu_ctl(
   output        io_dec_tlu_lsu_clk_override,
   output        io_dec_tlu_bus_clk_override,
   output        io_dec_tlu_pic_clk_override,
+  output        io_dec_tlu_picio_clk_override,
   output        io_dec_tlu_dccm_clk_override,
   output        io_dec_tlu_icm_clk_override,
   output        io_dec_tlu_flush_lower_wb,
@@ -11757,6 +11760,7 @@ module dec_tlu_ctl(
   wire  csr_io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 283:23]
   wire  csr_io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 283:23]
   wire  csr_io_dec_tlu_misc_clk_override; // @[dec_tlu_ctl.scala 283:23]
+  wire  csr_io_dec_tlu_picio_clk_override; // @[dec_tlu_ctl.scala 283:23]
   wire  csr_io_dec_tlu_dec_clk_override; // @[dec_tlu_ctl.scala 283:23]
   wire  csr_io_dec_tlu_ifu_clk_override; // @[dec_tlu_ctl.scala 283:23]
   wire  csr_io_dec_tlu_lsu_clk_override; // @[dec_tlu_ctl.scala 283:23]
@@ -12822,6 +12826,7 @@ module dec_tlu_ctl(
     .io_dec_tlu_i0_valid_r(csr_io_dec_tlu_i0_valid_r),
     .io_dec_csr_any_unq_d(csr_io_dec_csr_any_unq_d),
     .io_dec_tlu_misc_clk_override(csr_io_dec_tlu_misc_clk_override),
+    .io_dec_tlu_picio_clk_override(csr_io_dec_tlu_picio_clk_override),
     .io_dec_tlu_dec_clk_override(csr_io_dec_tlu_dec_clk_override),
     .io_dec_tlu_ifu_clk_override(csr_io_dec_tlu_ifu_clk_override),
     .io_dec_tlu_lsu_clk_override(csr_io_dec_tlu_lsu_clk_override),
@@ -13180,6 +13185,7 @@ module dec_tlu_ctl(
   assign io_dec_tlu_lsu_clk_override = csr_io_dec_tlu_lsu_clk_override; // @[dec_tlu_ctl.scala 896:46]
   assign io_dec_tlu_bus_clk_override = csr_io_dec_tlu_bus_clk_override; // @[dec_tlu_ctl.scala 897:46]
   assign io_dec_tlu_pic_clk_override = csr_io_dec_tlu_pic_clk_override; // @[dec_tlu_ctl.scala 898:46]
+  assign io_dec_tlu_picio_clk_override = csr_io_dec_tlu_picio_clk_override; // @[dec_tlu_ctl.scala 893:46]
   assign io_dec_tlu_dccm_clk_override = csr_io_dec_tlu_dccm_clk_override; // @[dec_tlu_ctl.scala 899:46]
   assign io_dec_tlu_icm_clk_override = csr_io_dec_tlu_icm_clk_override; // @[dec_tlu_ctl.scala 900:46]
   assign io_dec_tlu_flush_lower_wb = int_exc_io_dec_tlu_flush_lower_wb; // @[dec_tlu_ctl.scala 809:46]
@@ -14930,8 +14936,8 @@ module dec(
   output        io_dec_tlu_picio_clk_override,
   output        io_dec_tlu_dccm_clk_override,
   output        io_dec_tlu_icm_clk_override,
+  output        io_dec_i0_decode_d,
   input         io_scan_mode,
-  output        io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d,
   input  [15:0] io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst,
   input         io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf,
   input  [1:0]  io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type,
@@ -15145,501 +15151,502 @@ module dec(
   output [3:0]  io_dec_pic_dec_tlu_meipt,
   input         io_dec_pic_mexintpend
 );
-  wire  instbuff_io_ifu_ib_ifu_i0_icaf; // @[dec.scala 128:24]
-  wire [1:0] instbuff_io_ifu_ib_ifu_i0_icaf_type; // @[dec.scala 128:24]
-  wire  instbuff_io_ifu_ib_ifu_i0_icaf_second; // @[dec.scala 128:24]
-  wire  instbuff_io_ifu_ib_ifu_i0_dbecc; // @[dec.scala 128:24]
-  wire [7:0] instbuff_io_ifu_ib_ifu_i0_bp_index; // @[dec.scala 128:24]
-  wire [7:0] instbuff_io_ifu_ib_ifu_i0_bp_fghr; // @[dec.scala 128:24]
-  wire [4:0] instbuff_io_ifu_ib_ifu_i0_bp_btag; // @[dec.scala 128:24]
-  wire  instbuff_io_ifu_ib_ifu_i0_valid; // @[dec.scala 128:24]
-  wire [31:0] instbuff_io_ifu_ib_ifu_i0_instr; // @[dec.scala 128:24]
-  wire [30:0] instbuff_io_ifu_ib_ifu_i0_pc; // @[dec.scala 128:24]
-  wire  instbuff_io_ifu_ib_ifu_i0_pc4; // @[dec.scala 128:24]
-  wire  instbuff_io_ifu_ib_i0_brp_valid; // @[dec.scala 128:24]
-  wire [11:0] instbuff_io_ifu_ib_i0_brp_bits_toffset; // @[dec.scala 128:24]
-  wire [1:0] instbuff_io_ifu_ib_i0_brp_bits_hist; // @[dec.scala 128:24]
-  wire  instbuff_io_ifu_ib_i0_brp_bits_br_error; // @[dec.scala 128:24]
-  wire  instbuff_io_ifu_ib_i0_brp_bits_br_start_error; // @[dec.scala 128:24]
-  wire [30:0] instbuff_io_ifu_ib_i0_brp_bits_prett; // @[dec.scala 128:24]
-  wire  instbuff_io_ifu_ib_i0_brp_bits_way; // @[dec.scala 128:24]
-  wire  instbuff_io_ifu_ib_i0_brp_bits_ret; // @[dec.scala 128:24]
-  wire [30:0] instbuff_io_ib_exu_dec_i0_pc_d; // @[dec.scala 128:24]
-  wire  instbuff_io_ib_exu_dec_debug_wdata_rs1_d; // @[dec.scala 128:24]
-  wire  instbuff_io_dbg_ib_dbg_cmd_valid; // @[dec.scala 128:24]
-  wire  instbuff_io_dbg_ib_dbg_cmd_write; // @[dec.scala 128:24]
-  wire [1:0] instbuff_io_dbg_ib_dbg_cmd_type; // @[dec.scala 128:24]
-  wire [31:0] instbuff_io_dbg_ib_dbg_cmd_addr; // @[dec.scala 128:24]
-  wire  instbuff_io_dec_ib0_valid_d; // @[dec.scala 128:24]
-  wire [1:0] instbuff_io_dec_i0_icaf_type_d; // @[dec.scala 128:24]
-  wire [31:0] instbuff_io_dec_i0_instr_d; // @[dec.scala 128:24]
-  wire  instbuff_io_dec_i0_pc4_d; // @[dec.scala 128:24]
-  wire  instbuff_io_dec_i0_brp_valid; // @[dec.scala 128:24]
-  wire [11:0] instbuff_io_dec_i0_brp_bits_toffset; // @[dec.scala 128:24]
-  wire [1:0] instbuff_io_dec_i0_brp_bits_hist; // @[dec.scala 128:24]
-  wire  instbuff_io_dec_i0_brp_bits_br_error; // @[dec.scala 128:24]
-  wire  instbuff_io_dec_i0_brp_bits_br_start_error; // @[dec.scala 128:24]
-  wire [30:0] instbuff_io_dec_i0_brp_bits_prett; // @[dec.scala 128:24]
-  wire  instbuff_io_dec_i0_brp_bits_way; // @[dec.scala 128:24]
-  wire  instbuff_io_dec_i0_brp_bits_ret; // @[dec.scala 128:24]
-  wire [7:0] instbuff_io_dec_i0_bp_index; // @[dec.scala 128:24]
-  wire [7:0] instbuff_io_dec_i0_bp_fghr; // @[dec.scala 128:24]
-  wire [4:0] instbuff_io_dec_i0_bp_btag; // @[dec.scala 128:24]
-  wire  instbuff_io_dec_i0_icaf_d; // @[dec.scala 128:24]
-  wire  instbuff_io_dec_i0_icaf_second_d; // @[dec.scala 128:24]
-  wire  instbuff_io_dec_i0_dbecc_d; // @[dec.scala 128:24]
-  wire  instbuff_io_dec_debug_fence_d; // @[dec.scala 128:24]
-  wire  decode_clock; // @[dec.scala 129:22]
-  wire  decode_reset; // @[dec.scala 129:22]
-  wire [1:0] decode_io_decode_exu_dec_data_en; // @[dec.scala 129:22]
-  wire [1:0] decode_io_decode_exu_dec_ctl_en; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_i0_ap_clz; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_i0_ap_ctz; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_i0_ap_pcnt; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_i0_ap_sext_b; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_i0_ap_sext_h; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_i0_ap_slo; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_i0_ap_sro; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_i0_ap_min; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_i0_ap_max; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_i0_ap_pack; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_i0_ap_packu; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_i0_ap_packh; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_i0_ap_rol; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_i0_ap_ror; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_i0_ap_grev; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_i0_ap_gorc; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_i0_ap_zbb; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_i0_ap_sbset; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_i0_ap_sbclr; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_i0_ap_sbinv; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_i0_ap_sbext; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_i0_ap_sh1add; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_i0_ap_sh2add; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_i0_ap_sh3add; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_i0_ap_zba; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_i0_ap_land; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_i0_ap_lor; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_i0_ap_lxor; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_i0_ap_sll; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_i0_ap_srl; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_i0_ap_sra; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_i0_ap_beq; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_i0_ap_bne; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_i0_ap_blt; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_i0_ap_bge; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_i0_ap_add; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_i0_ap_sub; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_i0_ap_slt; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_i0_ap_unsign; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_i0_ap_jal; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_i0_ap_predict_t; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_i0_ap_predict_nt; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_i0_ap_csr_write; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_i0_ap_csr_imm; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_dec_i0_predict_p_d_valid; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[dec.scala 129:22]
-  wire [1:0] decode_io_decode_exu_dec_i0_predict_p_d_bits_hist; // @[dec.scala 129:22]
-  wire [11:0] decode_io_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_dec_i0_predict_p_d_bits_pja; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_dec_i0_predict_p_d_bits_way; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_dec_i0_predict_p_d_bits_pret; // @[dec.scala 129:22]
-  wire [30:0] decode_io_decode_exu_dec_i0_predict_p_d_bits_prett; // @[dec.scala 129:22]
-  wire [7:0] decode_io_decode_exu_i0_predict_fghr_d; // @[dec.scala 129:22]
-  wire [7:0] decode_io_decode_exu_i0_predict_index_d; // @[dec.scala 129:22]
-  wire [4:0] decode_io_decode_exu_i0_predict_btag_d; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_dec_i0_rs1_en_d; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_dec_i0_branch_d; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_dec_i0_rs2_en_d; // @[dec.scala 129:22]
-  wire [31:0] decode_io_decode_exu_dec_i0_immed_d; // @[dec.scala 129:22]
-  wire [31:0] decode_io_decode_exu_dec_i0_result_r; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_dec_qual_lsu_d; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_dec_i0_select_pc_d; // @[dec.scala 129:22]
-  wire [3:0] decode_io_decode_exu_dec_i0_rs1_bypass_en_d; // @[dec.scala 129:22]
-  wire [3:0] decode_io_decode_exu_dec_i0_rs2_bypass_en_d; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_mul_p_valid; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_mul_p_bits_rs1_sign; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_mul_p_bits_rs2_sign; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_mul_p_bits_low; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_mul_p_bits_bext; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_mul_p_bits_bdep; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_mul_p_bits_clmul; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_mul_p_bits_clmulh; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_mul_p_bits_clmulr; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_mul_p_bits_grev; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_mul_p_bits_gorc; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_mul_p_bits_shfl; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_mul_p_bits_unshfl; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_mul_p_bits_crc32_b; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_mul_p_bits_crc32_h; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_mul_p_bits_crc32_w; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_mul_p_bits_crc32c_b; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_mul_p_bits_crc32c_h; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_mul_p_bits_crc32c_w; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_mul_p_bits_bfp; // @[dec.scala 129:22]
-  wire [30:0] decode_io_decode_exu_pred_correct_npc_x; // @[dec.scala 129:22]
-  wire  decode_io_decode_exu_dec_extint_stall; // @[dec.scala 129:22]
-  wire [31:0] decode_io_decode_exu_exu_i0_result_x; // @[dec.scala 129:22]
-  wire [31:0] decode_io_decode_exu_exu_csr_rs1_x; // @[dec.scala 129:22]
-  wire  decode_io_dec_alu_dec_i0_alu_decode_d; // @[dec.scala 129:22]
-  wire  decode_io_dec_alu_dec_csr_ren_d; // @[dec.scala 129:22]
-  wire [11:0] decode_io_dec_alu_dec_i0_br_immed_d; // @[dec.scala 129:22]
-  wire [30:0] decode_io_dec_alu_exu_i0_pc_x; // @[dec.scala 129:22]
-  wire  decode_io_dec_div_div_p_valid; // @[dec.scala 129:22]
-  wire  decode_io_dec_div_div_p_bits_unsign; // @[dec.scala 129:22]
-  wire  decode_io_dec_div_div_p_bits_rem; // @[dec.scala 129:22]
-  wire  decode_io_dec_div_dec_div_cancel; // @[dec.scala 129:22]
-  wire  decode_io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[dec.scala 129:22]
-  wire [1:0] decode_io_dctl_busbuff_lsu_nonblock_load_tag_m; // @[dec.scala 129:22]
-  wire  decode_io_dctl_busbuff_lsu_nonblock_load_inv_r; // @[dec.scala 129:22]
-  wire [1:0] decode_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[dec.scala 129:22]
-  wire  decode_io_dctl_busbuff_lsu_nonblock_load_data_valid; // @[dec.scala 129:22]
-  wire  decode_io_dctl_busbuff_lsu_nonblock_load_data_error; // @[dec.scala 129:22]
-  wire [1:0] decode_io_dctl_busbuff_lsu_nonblock_load_data_tag; // @[dec.scala 129:22]
-  wire  decode_io_dctl_dma_dma_dccm_stall_any; // @[dec.scala 129:22]
-  wire  decode_io_dec_aln_dec_i0_decode_d; // @[dec.scala 129:22]
-  wire [15:0] decode_io_dec_aln_ifu_i0_cinst; // @[dec.scala 129:22]
-  wire [31:0] decode_io_dbg_dctl_dbg_cmd_wrdata; // @[dec.scala 129:22]
-  wire  decode_io_dec_tlu_trace_disable; // @[dec.scala 129:22]
-  wire  decode_io_dec_debug_valid_d; // @[dec.scala 129:22]
-  wire  decode_io_dec_tlu_flush_extint; // @[dec.scala 129:22]
-  wire  decode_io_dec_tlu_force_halt; // @[dec.scala 129:22]
-  wire [31:0] decode_io_dec_i0_inst_wb; // @[dec.scala 129:22]
-  wire [30:0] decode_io_dec_i0_pc_wb; // @[dec.scala 129:22]
-  wire [3:0] decode_io_dec_i0_trigger_match_d; // @[dec.scala 129:22]
-  wire  decode_io_dec_tlu_wr_pause_r; // @[dec.scala 129:22]
-  wire  decode_io_dec_tlu_pipelining_disable; // @[dec.scala 129:22]
-  wire [3:0] decode_io_lsu_trigger_match_m; // @[dec.scala 129:22]
-  wire  decode_io_lsu_pmu_misaligned_m; // @[dec.scala 129:22]
-  wire  decode_io_dec_tlu_debug_stall; // @[dec.scala 129:22]
-  wire  decode_io_dec_tlu_flush_leak_one_r; // @[dec.scala 129:22]
-  wire  decode_io_dec_debug_fence_d; // @[dec.scala 129:22]
-  wire  decode_io_dec_i0_icaf_d; // @[dec.scala 129:22]
-  wire  decode_io_dec_i0_icaf_second_d; // @[dec.scala 129:22]
-  wire [1:0] decode_io_dec_i0_icaf_type_d; // @[dec.scala 129:22]
-  wire  decode_io_dec_i0_dbecc_d; // @[dec.scala 129:22]
-  wire  decode_io_dec_i0_brp_valid; // @[dec.scala 129:22]
-  wire [11:0] decode_io_dec_i0_brp_bits_toffset; // @[dec.scala 129:22]
-  wire [1:0] decode_io_dec_i0_brp_bits_hist; // @[dec.scala 129:22]
-  wire  decode_io_dec_i0_brp_bits_br_error; // @[dec.scala 129:22]
-  wire  decode_io_dec_i0_brp_bits_br_start_error; // @[dec.scala 129:22]
-  wire [30:0] decode_io_dec_i0_brp_bits_prett; // @[dec.scala 129:22]
-  wire  decode_io_dec_i0_brp_bits_way; // @[dec.scala 129:22]
-  wire  decode_io_dec_i0_brp_bits_ret; // @[dec.scala 129:22]
-  wire [7:0] decode_io_dec_i0_bp_index; // @[dec.scala 129:22]
-  wire [7:0] decode_io_dec_i0_bp_fghr; // @[dec.scala 129:22]
-  wire [4:0] decode_io_dec_i0_bp_btag; // @[dec.scala 129:22]
-  wire  decode_io_lsu_idle_any; // @[dec.scala 129:22]
-  wire  decode_io_lsu_load_stall_any; // @[dec.scala 129:22]
-  wire  decode_io_lsu_store_stall_any; // @[dec.scala 129:22]
-  wire  decode_io_exu_div_wren; // @[dec.scala 129:22]
-  wire  decode_io_dec_tlu_i0_kill_writeb_wb; // @[dec.scala 129:22]
-  wire  decode_io_dec_tlu_flush_lower_wb; // @[dec.scala 129:22]
-  wire  decode_io_dec_tlu_i0_kill_writeb_r; // @[dec.scala 129:22]
-  wire  decode_io_dec_tlu_flush_lower_r; // @[dec.scala 129:22]
-  wire  decode_io_dec_tlu_flush_pause_r; // @[dec.scala 129:22]
-  wire  decode_io_dec_tlu_presync_d; // @[dec.scala 129:22]
-  wire  decode_io_dec_tlu_postsync_d; // @[dec.scala 129:22]
-  wire  decode_io_dec_i0_pc4_d; // @[dec.scala 129:22]
-  wire [31:0] decode_io_dec_csr_rddata_d; // @[dec.scala 129:22]
-  wire  decode_io_dec_csr_legal_d; // @[dec.scala 129:22]
-  wire [31:0] decode_io_lsu_result_m; // @[dec.scala 129:22]
-  wire [31:0] decode_io_lsu_result_corr_r; // @[dec.scala 129:22]
-  wire  decode_io_exu_flush_final; // @[dec.scala 129:22]
-  wire [31:0] decode_io_dec_i0_instr_d; // @[dec.scala 129:22]
-  wire  decode_io_dec_ib0_valid_d; // @[dec.scala 129:22]
-  wire  decode_io_active_clk; // @[dec.scala 129:22]
-  wire  decode_io_free_l2clk; // @[dec.scala 129:22]
-  wire  decode_io_clk_override; // @[dec.scala 129:22]
-  wire [4:0] decode_io_dec_i0_rs1_d; // @[dec.scala 129:22]
-  wire [4:0] decode_io_dec_i0_rs2_d; // @[dec.scala 129:22]
-  wire [4:0] decode_io_dec_i0_waddr_r; // @[dec.scala 129:22]
-  wire  decode_io_dec_i0_wen_r; // @[dec.scala 129:22]
-  wire [31:0] decode_io_dec_i0_wdata_r; // @[dec.scala 129:22]
-  wire  decode_io_lsu_p_valid; // @[dec.scala 129:22]
-  wire  decode_io_lsu_p_bits_fast_int; // @[dec.scala 129:22]
-  wire  decode_io_lsu_p_bits_stack; // @[dec.scala 129:22]
-  wire  decode_io_lsu_p_bits_by; // @[dec.scala 129:22]
-  wire  decode_io_lsu_p_bits_half; // @[dec.scala 129:22]
-  wire  decode_io_lsu_p_bits_word; // @[dec.scala 129:22]
-  wire  decode_io_lsu_p_bits_load; // @[dec.scala 129:22]
-  wire  decode_io_lsu_p_bits_store; // @[dec.scala 129:22]
-  wire  decode_io_lsu_p_bits_unsign; // @[dec.scala 129:22]
-  wire  decode_io_lsu_p_bits_store_data_bypass_d; // @[dec.scala 129:22]
-  wire  decode_io_lsu_p_bits_load_ldst_bypass_d; // @[dec.scala 129:22]
-  wire [4:0] decode_io_div_waddr_wb; // @[dec.scala 129:22]
-  wire  decode_io_dec_lsu_valid_raw_d; // @[dec.scala 129:22]
-  wire [11:0] decode_io_dec_lsu_offset_d; // @[dec.scala 129:22]
-  wire  decode_io_dec_csr_wen_unq_d; // @[dec.scala 129:22]
-  wire  decode_io_dec_csr_any_unq_d; // @[dec.scala 129:22]
-  wire [11:0] decode_io_dec_csr_rdaddr_d; // @[dec.scala 129:22]
-  wire  decode_io_dec_csr_wen_r; // @[dec.scala 129:22]
-  wire [11:0] decode_io_dec_csr_wraddr_r; // @[dec.scala 129:22]
-  wire [31:0] decode_io_dec_csr_wrdata_r; // @[dec.scala 129:22]
-  wire  decode_io_dec_csr_stall_int_ff; // @[dec.scala 129:22]
-  wire  decode_io_dec_tlu_i0_valid_r; // @[dec.scala 129:22]
-  wire  decode_io_dec_tlu_packet_r_legal; // @[dec.scala 129:22]
-  wire  decode_io_dec_tlu_packet_r_icaf; // @[dec.scala 129:22]
-  wire  decode_io_dec_tlu_packet_r_icaf_second; // @[dec.scala 129:22]
-  wire [1:0] decode_io_dec_tlu_packet_r_icaf_type; // @[dec.scala 129:22]
-  wire  decode_io_dec_tlu_packet_r_fence_i; // @[dec.scala 129:22]
-  wire [3:0] decode_io_dec_tlu_packet_r_i0trigger; // @[dec.scala 129:22]
-  wire [3:0] decode_io_dec_tlu_packet_r_pmu_i0_itype; // @[dec.scala 129:22]
-  wire  decode_io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[dec.scala 129:22]
-  wire  decode_io_dec_tlu_packet_r_pmu_divide; // @[dec.scala 129:22]
-  wire  decode_io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec.scala 129:22]
-  wire [30:0] decode_io_dec_tlu_i0_pc_r; // @[dec.scala 129:22]
-  wire [31:0] decode_io_dec_illegal_inst; // @[dec.scala 129:22]
-  wire  decode_io_dec_pmu_instr_decoded; // @[dec.scala 129:22]
-  wire  decode_io_dec_pmu_decode_stall; // @[dec.scala 129:22]
-  wire  decode_io_dec_pmu_presync_stall; // @[dec.scala 129:22]
-  wire  decode_io_dec_pmu_postsync_stall; // @[dec.scala 129:22]
-  wire  decode_io_dec_nonblock_load_wen; // @[dec.scala 129:22]
-  wire [4:0] decode_io_dec_nonblock_load_waddr; // @[dec.scala 129:22]
-  wire  decode_io_dec_pause_state; // @[dec.scala 129:22]
-  wire  decode_io_dec_pause_state_cg; // @[dec.scala 129:22]
-  wire  decode_io_dec_div_active; // @[dec.scala 129:22]
-  wire  gpr_clock; // @[dec.scala 130:19]
-  wire  gpr_reset; // @[dec.scala 130:19]
-  wire [4:0] gpr_io_raddr0; // @[dec.scala 130:19]
-  wire [4:0] gpr_io_raddr1; // @[dec.scala 130:19]
-  wire  gpr_io_wen0; // @[dec.scala 130:19]
-  wire [4:0] gpr_io_waddr0; // @[dec.scala 130:19]
-  wire [31:0] gpr_io_wd0; // @[dec.scala 130:19]
-  wire  gpr_io_wen1; // @[dec.scala 130:19]
-  wire [4:0] gpr_io_waddr1; // @[dec.scala 130:19]
-  wire [31:0] gpr_io_wd1; // @[dec.scala 130:19]
-  wire  gpr_io_wen2; // @[dec.scala 130:19]
-  wire [4:0] gpr_io_waddr2; // @[dec.scala 130:19]
-  wire [31:0] gpr_io_wd2; // @[dec.scala 130:19]
-  wire [31:0] gpr_io_gpr_exu_gpr_i0_rs1_d; // @[dec.scala 130:19]
-  wire [31:0] gpr_io_gpr_exu_gpr_i0_rs2_d; // @[dec.scala 130:19]
-  wire  tlu_clock; // @[dec.scala 131:19]
-  wire  tlu_reset; // @[dec.scala 131:19]
-  wire [29:0] tlu_io_tlu_exu_dec_tlu_meihap; // @[dec.scala 131:19]
-  wire  tlu_io_tlu_exu_dec_tlu_flush_lower_r; // @[dec.scala 131:19]
-  wire [30:0] tlu_io_tlu_exu_dec_tlu_flush_path_r; // @[dec.scala 131:19]
-  wire [1:0] tlu_io_tlu_exu_exu_i0_br_hist_r; // @[dec.scala 131:19]
-  wire  tlu_io_tlu_exu_exu_i0_br_error_r; // @[dec.scala 131:19]
-  wire  tlu_io_tlu_exu_exu_i0_br_start_error_r; // @[dec.scala 131:19]
-  wire  tlu_io_tlu_exu_exu_i0_br_valid_r; // @[dec.scala 131:19]
-  wire  tlu_io_tlu_exu_exu_i0_br_mp_r; // @[dec.scala 131:19]
-  wire  tlu_io_tlu_exu_exu_i0_br_middle_r; // @[dec.scala 131:19]
-  wire  tlu_io_tlu_exu_exu_pmu_i0_br_misp; // @[dec.scala 131:19]
-  wire  tlu_io_tlu_exu_exu_pmu_i0_br_ataken; // @[dec.scala 131:19]
-  wire  tlu_io_tlu_exu_exu_pmu_i0_pc4; // @[dec.scala 131:19]
-  wire [30:0] tlu_io_tlu_exu_exu_npc_r; // @[dec.scala 131:19]
-  wire  tlu_io_tlu_dma_dma_pmu_dccm_read; // @[dec.scala 131:19]
-  wire  tlu_io_tlu_dma_dma_pmu_dccm_write; // @[dec.scala 131:19]
-  wire  tlu_io_tlu_dma_dma_pmu_any_read; // @[dec.scala 131:19]
-  wire  tlu_io_tlu_dma_dma_pmu_any_write; // @[dec.scala 131:19]
-  wire [2:0] tlu_io_tlu_dma_dec_tlu_dma_qos_prty; // @[dec.scala 131:19]
-  wire  tlu_io_tlu_dma_dma_dccm_stall_any; // @[dec.scala 131:19]
-  wire  tlu_io_tlu_dma_dma_iccm_stall_any; // @[dec.scala 131:19]
-  wire  tlu_io_free_clk; // @[dec.scala 131:19]
-  wire  tlu_io_free_l2clk; // @[dec.scala 131:19]
-  wire [30:0] tlu_io_rst_vec; // @[dec.scala 131:19]
-  wire  tlu_io_nmi_int; // @[dec.scala 131:19]
-  wire [30:0] tlu_io_nmi_vec; // @[dec.scala 131:19]
-  wire  tlu_io_i_cpu_halt_req; // @[dec.scala 131:19]
-  wire  tlu_io_i_cpu_run_req; // @[dec.scala 131:19]
-  wire  tlu_io_lsu_fastint_stall_any; // @[dec.scala 131:19]
-  wire  tlu_io_lsu_idle_any; // @[dec.scala 131:19]
-  wire  tlu_io_dec_pmu_instr_decoded; // @[dec.scala 131:19]
-  wire  tlu_io_dec_pmu_decode_stall; // @[dec.scala 131:19]
-  wire  tlu_io_dec_pmu_presync_stall; // @[dec.scala 131:19]
-  wire  tlu_io_dec_pmu_postsync_stall; // @[dec.scala 131:19]
-  wire  tlu_io_lsu_store_stall_any; // @[dec.scala 131:19]
-  wire [30:0] tlu_io_lsu_fir_addr; // @[dec.scala 131:19]
-  wire [1:0] tlu_io_lsu_fir_error; // @[dec.scala 131:19]
-  wire  tlu_io_iccm_dma_sb_error; // @[dec.scala 131:19]
-  wire  tlu_io_lsu_error_pkt_r_valid; // @[dec.scala 131:19]
-  wire  tlu_io_lsu_error_pkt_r_bits_single_ecc_error; // @[dec.scala 131:19]
-  wire  tlu_io_lsu_error_pkt_r_bits_inst_type; // @[dec.scala 131:19]
-  wire  tlu_io_lsu_error_pkt_r_bits_exc_type; // @[dec.scala 131:19]
-  wire [3:0] tlu_io_lsu_error_pkt_r_bits_mscause; // @[dec.scala 131:19]
-  wire [31:0] tlu_io_lsu_error_pkt_r_bits_addr; // @[dec.scala 131:19]
-  wire  tlu_io_lsu_single_ecc_error_incr; // @[dec.scala 131:19]
-  wire  tlu_io_dec_pause_state; // @[dec.scala 131:19]
-  wire  tlu_io_dec_csr_wen_unq_d; // @[dec.scala 131:19]
-  wire  tlu_io_dec_csr_any_unq_d; // @[dec.scala 131:19]
-  wire [11:0] tlu_io_dec_csr_rdaddr_d; // @[dec.scala 131:19]
-  wire  tlu_io_dec_csr_wen_r; // @[dec.scala 131:19]
-  wire [11:0] tlu_io_dec_csr_wraddr_r; // @[dec.scala 131:19]
-  wire [31:0] tlu_io_dec_csr_wrdata_r; // @[dec.scala 131:19]
-  wire  tlu_io_dec_csr_stall_int_ff; // @[dec.scala 131:19]
-  wire  tlu_io_dec_tlu_i0_valid_r; // @[dec.scala 131:19]
-  wire [30:0] tlu_io_dec_tlu_i0_pc_r; // @[dec.scala 131:19]
-  wire  tlu_io_dec_tlu_packet_r_legal; // @[dec.scala 131:19]
-  wire  tlu_io_dec_tlu_packet_r_icaf; // @[dec.scala 131:19]
-  wire  tlu_io_dec_tlu_packet_r_icaf_second; // @[dec.scala 131:19]
-  wire [1:0] tlu_io_dec_tlu_packet_r_icaf_type; // @[dec.scala 131:19]
-  wire  tlu_io_dec_tlu_packet_r_fence_i; // @[dec.scala 131:19]
-  wire [3:0] tlu_io_dec_tlu_packet_r_i0trigger; // @[dec.scala 131:19]
-  wire [3:0] tlu_io_dec_tlu_packet_r_pmu_i0_itype; // @[dec.scala 131:19]
-  wire  tlu_io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[dec.scala 131:19]
-  wire  tlu_io_dec_tlu_packet_r_pmu_divide; // @[dec.scala 131:19]
-  wire  tlu_io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec.scala 131:19]
-  wire [31:0] tlu_io_dec_illegal_inst; // @[dec.scala 131:19]
-  wire  tlu_io_dec_i0_decode_d; // @[dec.scala 131:19]
-  wire  tlu_io_exu_i0_br_way_r; // @[dec.scala 131:19]
-  wire  tlu_io_dec_tlu_core_empty; // @[dec.scala 131:19]
-  wire  tlu_io_dec_dbg_cmd_done; // @[dec.scala 131:19]
-  wire  tlu_io_dec_dbg_cmd_fail; // @[dec.scala 131:19]
-  wire  tlu_io_dec_tlu_dbg_halted; // @[dec.scala 131:19]
-  wire  tlu_io_dec_tlu_debug_mode; // @[dec.scala 131:19]
-  wire  tlu_io_dec_tlu_resume_ack; // @[dec.scala 131:19]
-  wire  tlu_io_dec_tlu_debug_stall; // @[dec.scala 131:19]
-  wire  tlu_io_dec_tlu_mpc_halted_only; // @[dec.scala 131:19]
-  wire  tlu_io_dec_tlu_flush_extint; // @[dec.scala 131:19]
-  wire  tlu_io_dbg_halt_req; // @[dec.scala 131:19]
-  wire  tlu_io_dbg_resume_req; // @[dec.scala 131:19]
-  wire  tlu_io_dec_div_active; // @[dec.scala 131:19]
-  wire  tlu_io_trigger_pkt_any_0_select; // @[dec.scala 131:19]
-  wire  tlu_io_trigger_pkt_any_0_match_pkt; // @[dec.scala 131:19]
-  wire  tlu_io_trigger_pkt_any_0_store; // @[dec.scala 131:19]
-  wire  tlu_io_trigger_pkt_any_0_load; // @[dec.scala 131:19]
-  wire  tlu_io_trigger_pkt_any_0_execute; // @[dec.scala 131:19]
-  wire  tlu_io_trigger_pkt_any_0_m; // @[dec.scala 131:19]
-  wire [31:0] tlu_io_trigger_pkt_any_0_tdata2; // @[dec.scala 131:19]
-  wire  tlu_io_trigger_pkt_any_1_select; // @[dec.scala 131:19]
-  wire  tlu_io_trigger_pkt_any_1_match_pkt; // @[dec.scala 131:19]
-  wire  tlu_io_trigger_pkt_any_1_store; // @[dec.scala 131:19]
-  wire  tlu_io_trigger_pkt_any_1_load; // @[dec.scala 131:19]
-  wire  tlu_io_trigger_pkt_any_1_execute; // @[dec.scala 131:19]
-  wire  tlu_io_trigger_pkt_any_1_m; // @[dec.scala 131:19]
-  wire [31:0] tlu_io_trigger_pkt_any_1_tdata2; // @[dec.scala 131:19]
-  wire  tlu_io_trigger_pkt_any_2_select; // @[dec.scala 131:19]
-  wire  tlu_io_trigger_pkt_any_2_match_pkt; // @[dec.scala 131:19]
-  wire  tlu_io_trigger_pkt_any_2_store; // @[dec.scala 131:19]
-  wire  tlu_io_trigger_pkt_any_2_load; // @[dec.scala 131:19]
-  wire  tlu_io_trigger_pkt_any_2_execute; // @[dec.scala 131:19]
-  wire  tlu_io_trigger_pkt_any_2_m; // @[dec.scala 131:19]
-  wire [31:0] tlu_io_trigger_pkt_any_2_tdata2; // @[dec.scala 131:19]
-  wire  tlu_io_trigger_pkt_any_3_select; // @[dec.scala 131:19]
-  wire  tlu_io_trigger_pkt_any_3_match_pkt; // @[dec.scala 131:19]
-  wire  tlu_io_trigger_pkt_any_3_store; // @[dec.scala 131:19]
-  wire  tlu_io_trigger_pkt_any_3_load; // @[dec.scala 131:19]
-  wire  tlu_io_trigger_pkt_any_3_execute; // @[dec.scala 131:19]
-  wire  tlu_io_trigger_pkt_any_3_m; // @[dec.scala 131:19]
-  wire [31:0] tlu_io_trigger_pkt_any_3_tdata2; // @[dec.scala 131:19]
-  wire  tlu_io_timer_int; // @[dec.scala 131:19]
-  wire  tlu_io_soft_int; // @[dec.scala 131:19]
-  wire  tlu_io_o_cpu_halt_status; // @[dec.scala 131:19]
-  wire  tlu_io_o_cpu_halt_ack; // @[dec.scala 131:19]
-  wire  tlu_io_o_cpu_run_ack; // @[dec.scala 131:19]
-  wire  tlu_io_o_debug_mode_status; // @[dec.scala 131:19]
-  wire [27:0] tlu_io_core_id; // @[dec.scala 131:19]
-  wire  tlu_io_mpc_debug_halt_req; // @[dec.scala 131:19]
-  wire  tlu_io_mpc_debug_run_req; // @[dec.scala 131:19]
-  wire  tlu_io_mpc_reset_run_req; // @[dec.scala 131:19]
-  wire  tlu_io_mpc_debug_halt_ack; // @[dec.scala 131:19]
-  wire  tlu_io_mpc_debug_run_ack; // @[dec.scala 131:19]
-  wire  tlu_io_debug_brkpt_status; // @[dec.scala 131:19]
-  wire [31:0] tlu_io_dec_csr_rddata_d; // @[dec.scala 131:19]
-  wire  tlu_io_dec_csr_legal_d; // @[dec.scala 131:19]
-  wire  tlu_io_dec_tlu_i0_kill_writeb_wb; // @[dec.scala 131:19]
-  wire  tlu_io_dec_tlu_i0_kill_writeb_r; // @[dec.scala 131:19]
-  wire  tlu_io_dec_tlu_wr_pause_r; // @[dec.scala 131:19]
-  wire  tlu_io_dec_tlu_flush_pause_r; // @[dec.scala 131:19]
-  wire  tlu_io_dec_tlu_presync_d; // @[dec.scala 131:19]
-  wire  tlu_io_dec_tlu_postsync_d; // @[dec.scala 131:19]
-  wire  tlu_io_dec_tlu_perfcnt0; // @[dec.scala 131:19]
-  wire  tlu_io_dec_tlu_perfcnt1; // @[dec.scala 131:19]
-  wire  tlu_io_dec_tlu_perfcnt2; // @[dec.scala 131:19]
-  wire  tlu_io_dec_tlu_perfcnt3; // @[dec.scala 131:19]
-  wire  tlu_io_dec_tlu_i0_exc_valid_wb1; // @[dec.scala 131:19]
-  wire  tlu_io_dec_tlu_i0_valid_wb1; // @[dec.scala 131:19]
-  wire  tlu_io_dec_tlu_int_valid_wb1; // @[dec.scala 131:19]
-  wire [4:0] tlu_io_dec_tlu_exc_cause_wb1; // @[dec.scala 131:19]
-  wire [31:0] tlu_io_dec_tlu_mtval_wb1; // @[dec.scala 131:19]
-  wire  tlu_io_dec_tlu_pipelining_disable; // @[dec.scala 131:19]
-  wire  tlu_io_dec_tlu_trace_disable; // @[dec.scala 131:19]
-  wire  tlu_io_dec_tlu_misc_clk_override; // @[dec.scala 131:19]
-  wire  tlu_io_dec_tlu_dec_clk_override; // @[dec.scala 131:19]
-  wire  tlu_io_dec_tlu_ifu_clk_override; // @[dec.scala 131:19]
-  wire  tlu_io_dec_tlu_lsu_clk_override; // @[dec.scala 131:19]
-  wire  tlu_io_dec_tlu_bus_clk_override; // @[dec.scala 131:19]
-  wire  tlu_io_dec_tlu_pic_clk_override; // @[dec.scala 131:19]
-  wire  tlu_io_dec_tlu_dccm_clk_override; // @[dec.scala 131:19]
-  wire  tlu_io_dec_tlu_icm_clk_override; // @[dec.scala 131:19]
-  wire  tlu_io_dec_tlu_flush_lower_wb; // @[dec.scala 131:19]
-  wire  tlu_io_ifu_pmu_instr_aligned; // @[dec.scala 131:19]
-  wire  tlu_io_tlu_bp_dec_tlu_br0_r_pkt_valid; // @[dec.scala 131:19]
-  wire [1:0] tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_hist; // @[dec.scala 131:19]
-  wire  tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[dec.scala 131:19]
-  wire  tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[dec.scala 131:19]
-  wire  tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_way; // @[dec.scala 131:19]
-  wire  tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_middle; // @[dec.scala 131:19]
-  wire  tlu_io_tlu_bp_dec_tlu_flush_leak_one_wb; // @[dec.scala 131:19]
-  wire  tlu_io_tlu_bp_dec_tlu_bpred_disable; // @[dec.scala 131:19]
-  wire  tlu_io_tlu_ifc_dec_tlu_flush_noredir_wb; // @[dec.scala 131:19]
-  wire [31:0] tlu_io_tlu_ifc_dec_tlu_mrac_ff; // @[dec.scala 131:19]
-  wire  tlu_io_tlu_ifc_ifu_pmu_fetch_stall; // @[dec.scala 131:19]
-  wire  tlu_io_tlu_mem_dec_tlu_flush_err_wb; // @[dec.scala 131:19]
-  wire  tlu_io_tlu_mem_dec_tlu_i0_commit_cmt; // @[dec.scala 131:19]
-  wire  tlu_io_tlu_mem_dec_tlu_force_halt; // @[dec.scala 131:19]
-  wire  tlu_io_tlu_mem_dec_tlu_fence_i_wb; // @[dec.scala 131:19]
-  wire [70:0] tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wrdata; // @[dec.scala 131:19]
-  wire [16:0] tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_dicawics; // @[dec.scala 131:19]
-  wire  tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[dec.scala 131:19]
-  wire  tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[dec.scala 131:19]
-  wire  tlu_io_tlu_mem_dec_tlu_core_ecc_disable; // @[dec.scala 131:19]
-  wire  tlu_io_tlu_mem_ifu_pmu_ic_miss; // @[dec.scala 131:19]
-  wire  tlu_io_tlu_mem_ifu_pmu_ic_hit; // @[dec.scala 131:19]
-  wire  tlu_io_tlu_mem_ifu_pmu_bus_error; // @[dec.scala 131:19]
-  wire  tlu_io_tlu_mem_ifu_pmu_bus_busy; // @[dec.scala 131:19]
-  wire  tlu_io_tlu_mem_ifu_pmu_bus_trxn; // @[dec.scala 131:19]
-  wire  tlu_io_tlu_mem_ifu_ic_error_start; // @[dec.scala 131:19]
-  wire  tlu_io_tlu_mem_ifu_iccm_rd_ecc_single_err; // @[dec.scala 131:19]
-  wire [70:0] tlu_io_tlu_mem_ifu_ic_debug_rd_data; // @[dec.scala 131:19]
-  wire  tlu_io_tlu_mem_ifu_ic_debug_rd_data_valid; // @[dec.scala 131:19]
-  wire  tlu_io_tlu_mem_ifu_miss_state_idle; // @[dec.scala 131:19]
-  wire  tlu_io_tlu_busbuff_lsu_pmu_bus_trxn; // @[dec.scala 131:19]
-  wire  tlu_io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[dec.scala 131:19]
-  wire  tlu_io_tlu_busbuff_lsu_pmu_bus_error; // @[dec.scala 131:19]
-  wire  tlu_io_tlu_busbuff_lsu_pmu_bus_busy; // @[dec.scala 131:19]
-  wire  tlu_io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[dec.scala 131:19]
-  wire  tlu_io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[dec.scala 131:19]
-  wire  tlu_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[dec.scala 131:19]
-  wire  tlu_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[dec.scala 131:19]
-  wire  tlu_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[dec.scala 131:19]
-  wire [31:0] tlu_io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[dec.scala 131:19]
-  wire  tlu_io_lsu_tlu_lsu_pmu_load_external_m; // @[dec.scala 131:19]
-  wire  tlu_io_lsu_tlu_lsu_pmu_store_external_m; // @[dec.scala 131:19]
-  wire [7:0] tlu_io_dec_pic_pic_claimid; // @[dec.scala 131:19]
-  wire [3:0] tlu_io_dec_pic_pic_pl; // @[dec.scala 131:19]
-  wire  tlu_io_dec_pic_mhwakeup; // @[dec.scala 131:19]
-  wire [3:0] tlu_io_dec_pic_dec_tlu_meicurpl; // @[dec.scala 131:19]
-  wire [3:0] tlu_io_dec_pic_dec_tlu_meipt; // @[dec.scala 131:19]
-  wire  tlu_io_dec_pic_mexintpend; // @[dec.scala 131:19]
-  wire  dec_trigger_io_trigger_pkt_any_0_select; // @[dec.scala 132:27]
-  wire  dec_trigger_io_trigger_pkt_any_0_match_pkt; // @[dec.scala 132:27]
-  wire  dec_trigger_io_trigger_pkt_any_0_execute; // @[dec.scala 132:27]
-  wire  dec_trigger_io_trigger_pkt_any_0_m; // @[dec.scala 132:27]
-  wire [31:0] dec_trigger_io_trigger_pkt_any_0_tdata2; // @[dec.scala 132:27]
-  wire  dec_trigger_io_trigger_pkt_any_1_select; // @[dec.scala 132:27]
-  wire  dec_trigger_io_trigger_pkt_any_1_match_pkt; // @[dec.scala 132:27]
-  wire  dec_trigger_io_trigger_pkt_any_1_execute; // @[dec.scala 132:27]
-  wire  dec_trigger_io_trigger_pkt_any_1_m; // @[dec.scala 132:27]
-  wire [31:0] dec_trigger_io_trigger_pkt_any_1_tdata2; // @[dec.scala 132:27]
-  wire  dec_trigger_io_trigger_pkt_any_2_select; // @[dec.scala 132:27]
-  wire  dec_trigger_io_trigger_pkt_any_2_match_pkt; // @[dec.scala 132:27]
-  wire  dec_trigger_io_trigger_pkt_any_2_execute; // @[dec.scala 132:27]
-  wire  dec_trigger_io_trigger_pkt_any_2_m; // @[dec.scala 132:27]
-  wire [31:0] dec_trigger_io_trigger_pkt_any_2_tdata2; // @[dec.scala 132:27]
-  wire  dec_trigger_io_trigger_pkt_any_3_select; // @[dec.scala 132:27]
-  wire  dec_trigger_io_trigger_pkt_any_3_match_pkt; // @[dec.scala 132:27]
-  wire  dec_trigger_io_trigger_pkt_any_3_execute; // @[dec.scala 132:27]
-  wire  dec_trigger_io_trigger_pkt_any_3_m; // @[dec.scala 132:27]
-  wire [31:0] dec_trigger_io_trigger_pkt_any_3_tdata2; // @[dec.scala 132:27]
-  wire [30:0] dec_trigger_io_dec_i0_pc_d; // @[dec.scala 132:27]
-  wire [3:0] dec_trigger_io_dec_i0_trigger_match_d; // @[dec.scala 132:27]
-  wire  _T_1 = tlu_io_dec_tlu_int_valid_wb1 | tlu_io_dec_tlu_i0_valid_wb1; // @[dec.scala 312:71]
-  dec_ib_ctl instbuff ( // @[dec.scala 128:24]
+  wire  instbuff_io_ifu_ib_ifu_i0_icaf; // @[dec.scala 130:24]
+  wire [1:0] instbuff_io_ifu_ib_ifu_i0_icaf_type; // @[dec.scala 130:24]
+  wire  instbuff_io_ifu_ib_ifu_i0_icaf_second; // @[dec.scala 130:24]
+  wire  instbuff_io_ifu_ib_ifu_i0_dbecc; // @[dec.scala 130:24]
+  wire [7:0] instbuff_io_ifu_ib_ifu_i0_bp_index; // @[dec.scala 130:24]
+  wire [7:0] instbuff_io_ifu_ib_ifu_i0_bp_fghr; // @[dec.scala 130:24]
+  wire [4:0] instbuff_io_ifu_ib_ifu_i0_bp_btag; // @[dec.scala 130:24]
+  wire  instbuff_io_ifu_ib_ifu_i0_valid; // @[dec.scala 130:24]
+  wire [31:0] instbuff_io_ifu_ib_ifu_i0_instr; // @[dec.scala 130:24]
+  wire [30:0] instbuff_io_ifu_ib_ifu_i0_pc; // @[dec.scala 130:24]
+  wire  instbuff_io_ifu_ib_ifu_i0_pc4; // @[dec.scala 130:24]
+  wire  instbuff_io_ifu_ib_i0_brp_valid; // @[dec.scala 130:24]
+  wire [11:0] instbuff_io_ifu_ib_i0_brp_bits_toffset; // @[dec.scala 130:24]
+  wire [1:0] instbuff_io_ifu_ib_i0_brp_bits_hist; // @[dec.scala 130:24]
+  wire  instbuff_io_ifu_ib_i0_brp_bits_br_error; // @[dec.scala 130:24]
+  wire  instbuff_io_ifu_ib_i0_brp_bits_br_start_error; // @[dec.scala 130:24]
+  wire [30:0] instbuff_io_ifu_ib_i0_brp_bits_prett; // @[dec.scala 130:24]
+  wire  instbuff_io_ifu_ib_i0_brp_bits_way; // @[dec.scala 130:24]
+  wire  instbuff_io_ifu_ib_i0_brp_bits_ret; // @[dec.scala 130:24]
+  wire [30:0] instbuff_io_ib_exu_dec_i0_pc_d; // @[dec.scala 130:24]
+  wire  instbuff_io_ib_exu_dec_debug_wdata_rs1_d; // @[dec.scala 130:24]
+  wire  instbuff_io_dbg_ib_dbg_cmd_valid; // @[dec.scala 130:24]
+  wire  instbuff_io_dbg_ib_dbg_cmd_write; // @[dec.scala 130:24]
+  wire [1:0] instbuff_io_dbg_ib_dbg_cmd_type; // @[dec.scala 130:24]
+  wire [31:0] instbuff_io_dbg_ib_dbg_cmd_addr; // @[dec.scala 130:24]
+  wire  instbuff_io_dec_ib0_valid_d; // @[dec.scala 130:24]
+  wire [1:0] instbuff_io_dec_i0_icaf_type_d; // @[dec.scala 130:24]
+  wire [31:0] instbuff_io_dec_i0_instr_d; // @[dec.scala 130:24]
+  wire  instbuff_io_dec_i0_pc4_d; // @[dec.scala 130:24]
+  wire  instbuff_io_dec_i0_brp_valid; // @[dec.scala 130:24]
+  wire [11:0] instbuff_io_dec_i0_brp_bits_toffset; // @[dec.scala 130:24]
+  wire [1:0] instbuff_io_dec_i0_brp_bits_hist; // @[dec.scala 130:24]
+  wire  instbuff_io_dec_i0_brp_bits_br_error; // @[dec.scala 130:24]
+  wire  instbuff_io_dec_i0_brp_bits_br_start_error; // @[dec.scala 130:24]
+  wire [30:0] instbuff_io_dec_i0_brp_bits_prett; // @[dec.scala 130:24]
+  wire  instbuff_io_dec_i0_brp_bits_way; // @[dec.scala 130:24]
+  wire  instbuff_io_dec_i0_brp_bits_ret; // @[dec.scala 130:24]
+  wire [7:0] instbuff_io_dec_i0_bp_index; // @[dec.scala 130:24]
+  wire [7:0] instbuff_io_dec_i0_bp_fghr; // @[dec.scala 130:24]
+  wire [4:0] instbuff_io_dec_i0_bp_btag; // @[dec.scala 130:24]
+  wire  instbuff_io_dec_i0_icaf_d; // @[dec.scala 130:24]
+  wire  instbuff_io_dec_i0_icaf_second_d; // @[dec.scala 130:24]
+  wire  instbuff_io_dec_i0_dbecc_d; // @[dec.scala 130:24]
+  wire  instbuff_io_dec_debug_fence_d; // @[dec.scala 130:24]
+  wire  decode_clock; // @[dec.scala 131:22]
+  wire  decode_reset; // @[dec.scala 131:22]
+  wire [1:0] decode_io_decode_exu_dec_data_en; // @[dec.scala 131:22]
+  wire [1:0] decode_io_decode_exu_dec_ctl_en; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_i0_ap_clz; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_i0_ap_ctz; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_i0_ap_pcnt; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_i0_ap_sext_b; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_i0_ap_sext_h; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_i0_ap_slo; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_i0_ap_sro; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_i0_ap_min; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_i0_ap_max; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_i0_ap_pack; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_i0_ap_packu; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_i0_ap_packh; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_i0_ap_rol; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_i0_ap_ror; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_i0_ap_grev; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_i0_ap_gorc; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_i0_ap_zbb; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_i0_ap_sbset; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_i0_ap_sbclr; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_i0_ap_sbinv; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_i0_ap_sbext; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_i0_ap_sh1add; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_i0_ap_sh2add; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_i0_ap_sh3add; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_i0_ap_zba; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_i0_ap_land; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_i0_ap_lor; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_i0_ap_lxor; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_i0_ap_sll; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_i0_ap_srl; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_i0_ap_sra; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_i0_ap_beq; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_i0_ap_bne; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_i0_ap_blt; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_i0_ap_bge; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_i0_ap_add; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_i0_ap_sub; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_i0_ap_slt; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_i0_ap_unsign; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_i0_ap_jal; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_i0_ap_predict_t; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_i0_ap_predict_nt; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_i0_ap_csr_write; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_i0_ap_csr_imm; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_dec_i0_predict_p_d_valid; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[dec.scala 131:22]
+  wire [1:0] decode_io_decode_exu_dec_i0_predict_p_d_bits_hist; // @[dec.scala 131:22]
+  wire [11:0] decode_io_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_dec_i0_predict_p_d_bits_pja; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_dec_i0_predict_p_d_bits_way; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_dec_i0_predict_p_d_bits_pret; // @[dec.scala 131:22]
+  wire [30:0] decode_io_decode_exu_dec_i0_predict_p_d_bits_prett; // @[dec.scala 131:22]
+  wire [7:0] decode_io_decode_exu_i0_predict_fghr_d; // @[dec.scala 131:22]
+  wire [7:0] decode_io_decode_exu_i0_predict_index_d; // @[dec.scala 131:22]
+  wire [4:0] decode_io_decode_exu_i0_predict_btag_d; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_dec_i0_rs1_en_d; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_dec_i0_branch_d; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_dec_i0_rs2_en_d; // @[dec.scala 131:22]
+  wire [31:0] decode_io_decode_exu_dec_i0_immed_d; // @[dec.scala 131:22]
+  wire [31:0] decode_io_decode_exu_dec_i0_result_r; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_dec_qual_lsu_d; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_dec_i0_select_pc_d; // @[dec.scala 131:22]
+  wire [3:0] decode_io_decode_exu_dec_i0_rs1_bypass_en_d; // @[dec.scala 131:22]
+  wire [3:0] decode_io_decode_exu_dec_i0_rs2_bypass_en_d; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_mul_p_valid; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_mul_p_bits_rs1_sign; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_mul_p_bits_rs2_sign; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_mul_p_bits_low; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_mul_p_bits_bext; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_mul_p_bits_bdep; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_mul_p_bits_clmul; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_mul_p_bits_clmulh; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_mul_p_bits_clmulr; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_mul_p_bits_grev; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_mul_p_bits_gorc; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_mul_p_bits_shfl; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_mul_p_bits_unshfl; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_mul_p_bits_crc32_b; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_mul_p_bits_crc32_h; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_mul_p_bits_crc32_w; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_mul_p_bits_crc32c_b; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_mul_p_bits_crc32c_h; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_mul_p_bits_crc32c_w; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_mul_p_bits_bfp; // @[dec.scala 131:22]
+  wire [30:0] decode_io_decode_exu_pred_correct_npc_x; // @[dec.scala 131:22]
+  wire  decode_io_decode_exu_dec_extint_stall; // @[dec.scala 131:22]
+  wire [31:0] decode_io_decode_exu_exu_i0_result_x; // @[dec.scala 131:22]
+  wire [31:0] decode_io_decode_exu_exu_csr_rs1_x; // @[dec.scala 131:22]
+  wire  decode_io_dec_alu_dec_i0_alu_decode_d; // @[dec.scala 131:22]
+  wire  decode_io_dec_alu_dec_csr_ren_d; // @[dec.scala 131:22]
+  wire [11:0] decode_io_dec_alu_dec_i0_br_immed_d; // @[dec.scala 131:22]
+  wire [30:0] decode_io_dec_alu_exu_i0_pc_x; // @[dec.scala 131:22]
+  wire  decode_io_dec_div_div_p_valid; // @[dec.scala 131:22]
+  wire  decode_io_dec_div_div_p_bits_unsign; // @[dec.scala 131:22]
+  wire  decode_io_dec_div_div_p_bits_rem; // @[dec.scala 131:22]
+  wire  decode_io_dec_div_dec_div_cancel; // @[dec.scala 131:22]
+  wire  decode_io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[dec.scala 131:22]
+  wire [1:0] decode_io_dctl_busbuff_lsu_nonblock_load_tag_m; // @[dec.scala 131:22]
+  wire  decode_io_dctl_busbuff_lsu_nonblock_load_inv_r; // @[dec.scala 131:22]
+  wire [1:0] decode_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[dec.scala 131:22]
+  wire  decode_io_dctl_busbuff_lsu_nonblock_load_data_valid; // @[dec.scala 131:22]
+  wire  decode_io_dctl_busbuff_lsu_nonblock_load_data_error; // @[dec.scala 131:22]
+  wire [1:0] decode_io_dctl_busbuff_lsu_nonblock_load_data_tag; // @[dec.scala 131:22]
+  wire  decode_io_dctl_dma_dma_dccm_stall_any; // @[dec.scala 131:22]
+  wire [15:0] decode_io_dec_aln_ifu_i0_cinst; // @[dec.scala 131:22]
+  wire [31:0] decode_io_dbg_dctl_dbg_cmd_wrdata; // @[dec.scala 131:22]
+  wire  decode_io_dec_tlu_trace_disable; // @[dec.scala 131:22]
+  wire  decode_io_dec_debug_valid_d; // @[dec.scala 131:22]
+  wire  decode_io_dec_tlu_flush_extint; // @[dec.scala 131:22]
+  wire  decode_io_dec_tlu_force_halt; // @[dec.scala 131:22]
+  wire [31:0] decode_io_dec_i0_inst_wb; // @[dec.scala 131:22]
+  wire [30:0] decode_io_dec_i0_pc_wb; // @[dec.scala 131:22]
+  wire [3:0] decode_io_dec_i0_trigger_match_d; // @[dec.scala 131:22]
+  wire  decode_io_dec_tlu_wr_pause_r; // @[dec.scala 131:22]
+  wire  decode_io_dec_tlu_pipelining_disable; // @[dec.scala 131:22]
+  wire [3:0] decode_io_lsu_trigger_match_m; // @[dec.scala 131:22]
+  wire  decode_io_lsu_pmu_misaligned_m; // @[dec.scala 131:22]
+  wire  decode_io_dec_tlu_debug_stall; // @[dec.scala 131:22]
+  wire  decode_io_dec_tlu_flush_leak_one_r; // @[dec.scala 131:22]
+  wire  decode_io_dec_debug_fence_d; // @[dec.scala 131:22]
+  wire  decode_io_dec_i0_icaf_d; // @[dec.scala 131:22]
+  wire  decode_io_dec_i0_icaf_second_d; // @[dec.scala 131:22]
+  wire [1:0] decode_io_dec_i0_icaf_type_d; // @[dec.scala 131:22]
+  wire  decode_io_dec_i0_dbecc_d; // @[dec.scala 131:22]
+  wire  decode_io_dec_i0_brp_valid; // @[dec.scala 131:22]
+  wire [11:0] decode_io_dec_i0_brp_bits_toffset; // @[dec.scala 131:22]
+  wire [1:0] decode_io_dec_i0_brp_bits_hist; // @[dec.scala 131:22]
+  wire  decode_io_dec_i0_brp_bits_br_error; // @[dec.scala 131:22]
+  wire  decode_io_dec_i0_brp_bits_br_start_error; // @[dec.scala 131:22]
+  wire [30:0] decode_io_dec_i0_brp_bits_prett; // @[dec.scala 131:22]
+  wire  decode_io_dec_i0_brp_bits_way; // @[dec.scala 131:22]
+  wire  decode_io_dec_i0_brp_bits_ret; // @[dec.scala 131:22]
+  wire [7:0] decode_io_dec_i0_bp_index; // @[dec.scala 131:22]
+  wire [7:0] decode_io_dec_i0_bp_fghr; // @[dec.scala 131:22]
+  wire [4:0] decode_io_dec_i0_bp_btag; // @[dec.scala 131:22]
+  wire  decode_io_lsu_idle_any; // @[dec.scala 131:22]
+  wire  decode_io_lsu_load_stall_any; // @[dec.scala 131:22]
+  wire  decode_io_lsu_store_stall_any; // @[dec.scala 131:22]
+  wire  decode_io_exu_div_wren; // @[dec.scala 131:22]
+  wire  decode_io_dec_tlu_i0_kill_writeb_wb; // @[dec.scala 131:22]
+  wire  decode_io_dec_tlu_flush_lower_wb; // @[dec.scala 131:22]
+  wire  decode_io_dec_tlu_i0_kill_writeb_r; // @[dec.scala 131:22]
+  wire  decode_io_dec_tlu_flush_lower_r; // @[dec.scala 131:22]
+  wire  decode_io_dec_tlu_flush_pause_r; // @[dec.scala 131:22]
+  wire  decode_io_dec_tlu_presync_d; // @[dec.scala 131:22]
+  wire  decode_io_dec_tlu_postsync_d; // @[dec.scala 131:22]
+  wire  decode_io_dec_i0_pc4_d; // @[dec.scala 131:22]
+  wire [31:0] decode_io_dec_csr_rddata_d; // @[dec.scala 131:22]
+  wire  decode_io_dec_csr_legal_d; // @[dec.scala 131:22]
+  wire [31:0] decode_io_lsu_result_m; // @[dec.scala 131:22]
+  wire [31:0] decode_io_lsu_result_corr_r; // @[dec.scala 131:22]
+  wire  decode_io_exu_flush_final; // @[dec.scala 131:22]
+  wire [31:0] decode_io_dec_i0_instr_d; // @[dec.scala 131:22]
+  wire  decode_io_dec_ib0_valid_d; // @[dec.scala 131:22]
+  wire  decode_io_active_clk; // @[dec.scala 131:22]
+  wire  decode_io_free_l2clk; // @[dec.scala 131:22]
+  wire  decode_io_clk_override; // @[dec.scala 131:22]
+  wire [4:0] decode_io_dec_i0_rs1_d; // @[dec.scala 131:22]
+  wire [4:0] decode_io_dec_i0_rs2_d; // @[dec.scala 131:22]
+  wire [4:0] decode_io_dec_i0_waddr_r; // @[dec.scala 131:22]
+  wire  decode_io_dec_i0_wen_r; // @[dec.scala 131:22]
+  wire [31:0] decode_io_dec_i0_wdata_r; // @[dec.scala 131:22]
+  wire  decode_io_lsu_p_valid; // @[dec.scala 131:22]
+  wire  decode_io_lsu_p_bits_fast_int; // @[dec.scala 131:22]
+  wire  decode_io_lsu_p_bits_stack; // @[dec.scala 131:22]
+  wire  decode_io_lsu_p_bits_by; // @[dec.scala 131:22]
+  wire  decode_io_lsu_p_bits_half; // @[dec.scala 131:22]
+  wire  decode_io_lsu_p_bits_word; // @[dec.scala 131:22]
+  wire  decode_io_lsu_p_bits_load; // @[dec.scala 131:22]
+  wire  decode_io_lsu_p_bits_store; // @[dec.scala 131:22]
+  wire  decode_io_lsu_p_bits_unsign; // @[dec.scala 131:22]
+  wire  decode_io_lsu_p_bits_store_data_bypass_d; // @[dec.scala 131:22]
+  wire  decode_io_lsu_p_bits_load_ldst_bypass_d; // @[dec.scala 131:22]
+  wire [4:0] decode_io_div_waddr_wb; // @[dec.scala 131:22]
+  wire  decode_io_dec_lsu_valid_raw_d; // @[dec.scala 131:22]
+  wire [11:0] decode_io_dec_lsu_offset_d; // @[dec.scala 131:22]
+  wire  decode_io_dec_csr_wen_unq_d; // @[dec.scala 131:22]
+  wire  decode_io_dec_csr_any_unq_d; // @[dec.scala 131:22]
+  wire [11:0] decode_io_dec_csr_rdaddr_d; // @[dec.scala 131:22]
+  wire  decode_io_dec_csr_wen_r; // @[dec.scala 131:22]
+  wire [11:0] decode_io_dec_csr_wraddr_r; // @[dec.scala 131:22]
+  wire [31:0] decode_io_dec_csr_wrdata_r; // @[dec.scala 131:22]
+  wire  decode_io_dec_csr_stall_int_ff; // @[dec.scala 131:22]
+  wire  decode_io_dec_tlu_i0_valid_r; // @[dec.scala 131:22]
+  wire  decode_io_dec_tlu_packet_r_legal; // @[dec.scala 131:22]
+  wire  decode_io_dec_tlu_packet_r_icaf; // @[dec.scala 131:22]
+  wire  decode_io_dec_tlu_packet_r_icaf_second; // @[dec.scala 131:22]
+  wire [1:0] decode_io_dec_tlu_packet_r_icaf_type; // @[dec.scala 131:22]
+  wire  decode_io_dec_tlu_packet_r_fence_i; // @[dec.scala 131:22]
+  wire [3:0] decode_io_dec_tlu_packet_r_i0trigger; // @[dec.scala 131:22]
+  wire [3:0] decode_io_dec_tlu_packet_r_pmu_i0_itype; // @[dec.scala 131:22]
+  wire  decode_io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[dec.scala 131:22]
+  wire  decode_io_dec_tlu_packet_r_pmu_divide; // @[dec.scala 131:22]
+  wire  decode_io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec.scala 131:22]
+  wire [30:0] decode_io_dec_tlu_i0_pc_r; // @[dec.scala 131:22]
+  wire [31:0] decode_io_dec_illegal_inst; // @[dec.scala 131:22]
+  wire  decode_io_dec_pmu_instr_decoded; // @[dec.scala 131:22]
+  wire  decode_io_dec_pmu_decode_stall; // @[dec.scala 131:22]
+  wire  decode_io_dec_pmu_presync_stall; // @[dec.scala 131:22]
+  wire  decode_io_dec_pmu_postsync_stall; // @[dec.scala 131:22]
+  wire  decode_io_dec_nonblock_load_wen; // @[dec.scala 131:22]
+  wire [4:0] decode_io_dec_nonblock_load_waddr; // @[dec.scala 131:22]
+  wire  decode_io_dec_pause_state; // @[dec.scala 131:22]
+  wire  decode_io_dec_pause_state_cg; // @[dec.scala 131:22]
+  wire  decode_io_dec_div_active; // @[dec.scala 131:22]
+  wire  decode_io_dec_i0_decode_d; // @[dec.scala 131:22]
+  wire  gpr_clock; // @[dec.scala 132:19]
+  wire  gpr_reset; // @[dec.scala 132:19]
+  wire [4:0] gpr_io_raddr0; // @[dec.scala 132:19]
+  wire [4:0] gpr_io_raddr1; // @[dec.scala 132:19]
+  wire  gpr_io_wen0; // @[dec.scala 132:19]
+  wire [4:0] gpr_io_waddr0; // @[dec.scala 132:19]
+  wire [31:0] gpr_io_wd0; // @[dec.scala 132:19]
+  wire  gpr_io_wen1; // @[dec.scala 132:19]
+  wire [4:0] gpr_io_waddr1; // @[dec.scala 132:19]
+  wire [31:0] gpr_io_wd1; // @[dec.scala 132:19]
+  wire  gpr_io_wen2; // @[dec.scala 132:19]
+  wire [4:0] gpr_io_waddr2; // @[dec.scala 132:19]
+  wire [31:0] gpr_io_wd2; // @[dec.scala 132:19]
+  wire [31:0] gpr_io_gpr_exu_gpr_i0_rs1_d; // @[dec.scala 132:19]
+  wire [31:0] gpr_io_gpr_exu_gpr_i0_rs2_d; // @[dec.scala 132:19]
+  wire  tlu_clock; // @[dec.scala 133:19]
+  wire  tlu_reset; // @[dec.scala 133:19]
+  wire [29:0] tlu_io_tlu_exu_dec_tlu_meihap; // @[dec.scala 133:19]
+  wire  tlu_io_tlu_exu_dec_tlu_flush_lower_r; // @[dec.scala 133:19]
+  wire [30:0] tlu_io_tlu_exu_dec_tlu_flush_path_r; // @[dec.scala 133:19]
+  wire [1:0] tlu_io_tlu_exu_exu_i0_br_hist_r; // @[dec.scala 133:19]
+  wire  tlu_io_tlu_exu_exu_i0_br_error_r; // @[dec.scala 133:19]
+  wire  tlu_io_tlu_exu_exu_i0_br_start_error_r; // @[dec.scala 133:19]
+  wire  tlu_io_tlu_exu_exu_i0_br_valid_r; // @[dec.scala 133:19]
+  wire  tlu_io_tlu_exu_exu_i0_br_mp_r; // @[dec.scala 133:19]
+  wire  tlu_io_tlu_exu_exu_i0_br_middle_r; // @[dec.scala 133:19]
+  wire  tlu_io_tlu_exu_exu_pmu_i0_br_misp; // @[dec.scala 133:19]
+  wire  tlu_io_tlu_exu_exu_pmu_i0_br_ataken; // @[dec.scala 133:19]
+  wire  tlu_io_tlu_exu_exu_pmu_i0_pc4; // @[dec.scala 133:19]
+  wire [30:0] tlu_io_tlu_exu_exu_npc_r; // @[dec.scala 133:19]
+  wire  tlu_io_tlu_dma_dma_pmu_dccm_read; // @[dec.scala 133:19]
+  wire  tlu_io_tlu_dma_dma_pmu_dccm_write; // @[dec.scala 133:19]
+  wire  tlu_io_tlu_dma_dma_pmu_any_read; // @[dec.scala 133:19]
+  wire  tlu_io_tlu_dma_dma_pmu_any_write; // @[dec.scala 133:19]
+  wire [2:0] tlu_io_tlu_dma_dec_tlu_dma_qos_prty; // @[dec.scala 133:19]
+  wire  tlu_io_tlu_dma_dma_dccm_stall_any; // @[dec.scala 133:19]
+  wire  tlu_io_tlu_dma_dma_iccm_stall_any; // @[dec.scala 133:19]
+  wire  tlu_io_free_clk; // @[dec.scala 133:19]
+  wire  tlu_io_free_l2clk; // @[dec.scala 133:19]
+  wire [30:0] tlu_io_rst_vec; // @[dec.scala 133:19]
+  wire  tlu_io_nmi_int; // @[dec.scala 133:19]
+  wire [30:0] tlu_io_nmi_vec; // @[dec.scala 133:19]
+  wire  tlu_io_i_cpu_halt_req; // @[dec.scala 133:19]
+  wire  tlu_io_i_cpu_run_req; // @[dec.scala 133:19]
+  wire  tlu_io_lsu_fastint_stall_any; // @[dec.scala 133:19]
+  wire  tlu_io_lsu_idle_any; // @[dec.scala 133:19]
+  wire  tlu_io_dec_pmu_instr_decoded; // @[dec.scala 133:19]
+  wire  tlu_io_dec_pmu_decode_stall; // @[dec.scala 133:19]
+  wire  tlu_io_dec_pmu_presync_stall; // @[dec.scala 133:19]
+  wire  tlu_io_dec_pmu_postsync_stall; // @[dec.scala 133:19]
+  wire  tlu_io_lsu_store_stall_any; // @[dec.scala 133:19]
+  wire [30:0] tlu_io_lsu_fir_addr; // @[dec.scala 133:19]
+  wire [1:0] tlu_io_lsu_fir_error; // @[dec.scala 133:19]
+  wire  tlu_io_iccm_dma_sb_error; // @[dec.scala 133:19]
+  wire  tlu_io_lsu_error_pkt_r_valid; // @[dec.scala 133:19]
+  wire  tlu_io_lsu_error_pkt_r_bits_single_ecc_error; // @[dec.scala 133:19]
+  wire  tlu_io_lsu_error_pkt_r_bits_inst_type; // @[dec.scala 133:19]
+  wire  tlu_io_lsu_error_pkt_r_bits_exc_type; // @[dec.scala 133:19]
+  wire [3:0] tlu_io_lsu_error_pkt_r_bits_mscause; // @[dec.scala 133:19]
+  wire [31:0] tlu_io_lsu_error_pkt_r_bits_addr; // @[dec.scala 133:19]
+  wire  tlu_io_lsu_single_ecc_error_incr; // @[dec.scala 133:19]
+  wire  tlu_io_dec_pause_state; // @[dec.scala 133:19]
+  wire  tlu_io_dec_csr_wen_unq_d; // @[dec.scala 133:19]
+  wire  tlu_io_dec_csr_any_unq_d; // @[dec.scala 133:19]
+  wire [11:0] tlu_io_dec_csr_rdaddr_d; // @[dec.scala 133:19]
+  wire  tlu_io_dec_csr_wen_r; // @[dec.scala 133:19]
+  wire [11:0] tlu_io_dec_csr_wraddr_r; // @[dec.scala 133:19]
+  wire [31:0] tlu_io_dec_csr_wrdata_r; // @[dec.scala 133:19]
+  wire  tlu_io_dec_csr_stall_int_ff; // @[dec.scala 133:19]
+  wire  tlu_io_dec_tlu_i0_valid_r; // @[dec.scala 133:19]
+  wire [30:0] tlu_io_dec_tlu_i0_pc_r; // @[dec.scala 133:19]
+  wire  tlu_io_dec_tlu_packet_r_legal; // @[dec.scala 133:19]
+  wire  tlu_io_dec_tlu_packet_r_icaf; // @[dec.scala 133:19]
+  wire  tlu_io_dec_tlu_packet_r_icaf_second; // @[dec.scala 133:19]
+  wire [1:0] tlu_io_dec_tlu_packet_r_icaf_type; // @[dec.scala 133:19]
+  wire  tlu_io_dec_tlu_packet_r_fence_i; // @[dec.scala 133:19]
+  wire [3:0] tlu_io_dec_tlu_packet_r_i0trigger; // @[dec.scala 133:19]
+  wire [3:0] tlu_io_dec_tlu_packet_r_pmu_i0_itype; // @[dec.scala 133:19]
+  wire  tlu_io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[dec.scala 133:19]
+  wire  tlu_io_dec_tlu_packet_r_pmu_divide; // @[dec.scala 133:19]
+  wire  tlu_io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec.scala 133:19]
+  wire [31:0] tlu_io_dec_illegal_inst; // @[dec.scala 133:19]
+  wire  tlu_io_dec_i0_decode_d; // @[dec.scala 133:19]
+  wire  tlu_io_exu_i0_br_way_r; // @[dec.scala 133:19]
+  wire  tlu_io_dec_tlu_core_empty; // @[dec.scala 133:19]
+  wire  tlu_io_dec_dbg_cmd_done; // @[dec.scala 133:19]
+  wire  tlu_io_dec_dbg_cmd_fail; // @[dec.scala 133:19]
+  wire  tlu_io_dec_tlu_dbg_halted; // @[dec.scala 133:19]
+  wire  tlu_io_dec_tlu_debug_mode; // @[dec.scala 133:19]
+  wire  tlu_io_dec_tlu_resume_ack; // @[dec.scala 133:19]
+  wire  tlu_io_dec_tlu_debug_stall; // @[dec.scala 133:19]
+  wire  tlu_io_dec_tlu_mpc_halted_only; // @[dec.scala 133:19]
+  wire  tlu_io_dec_tlu_flush_extint; // @[dec.scala 133:19]
+  wire  tlu_io_dbg_halt_req; // @[dec.scala 133:19]
+  wire  tlu_io_dbg_resume_req; // @[dec.scala 133:19]
+  wire  tlu_io_dec_div_active; // @[dec.scala 133:19]
+  wire  tlu_io_trigger_pkt_any_0_select; // @[dec.scala 133:19]
+  wire  tlu_io_trigger_pkt_any_0_match_pkt; // @[dec.scala 133:19]
+  wire  tlu_io_trigger_pkt_any_0_store; // @[dec.scala 133:19]
+  wire  tlu_io_trigger_pkt_any_0_load; // @[dec.scala 133:19]
+  wire  tlu_io_trigger_pkt_any_0_execute; // @[dec.scala 133:19]
+  wire  tlu_io_trigger_pkt_any_0_m; // @[dec.scala 133:19]
+  wire [31:0] tlu_io_trigger_pkt_any_0_tdata2; // @[dec.scala 133:19]
+  wire  tlu_io_trigger_pkt_any_1_select; // @[dec.scala 133:19]
+  wire  tlu_io_trigger_pkt_any_1_match_pkt; // @[dec.scala 133:19]
+  wire  tlu_io_trigger_pkt_any_1_store; // @[dec.scala 133:19]
+  wire  tlu_io_trigger_pkt_any_1_load; // @[dec.scala 133:19]
+  wire  tlu_io_trigger_pkt_any_1_execute; // @[dec.scala 133:19]
+  wire  tlu_io_trigger_pkt_any_1_m; // @[dec.scala 133:19]
+  wire [31:0] tlu_io_trigger_pkt_any_1_tdata2; // @[dec.scala 133:19]
+  wire  tlu_io_trigger_pkt_any_2_select; // @[dec.scala 133:19]
+  wire  tlu_io_trigger_pkt_any_2_match_pkt; // @[dec.scala 133:19]
+  wire  tlu_io_trigger_pkt_any_2_store; // @[dec.scala 133:19]
+  wire  tlu_io_trigger_pkt_any_2_load; // @[dec.scala 133:19]
+  wire  tlu_io_trigger_pkt_any_2_execute; // @[dec.scala 133:19]
+  wire  tlu_io_trigger_pkt_any_2_m; // @[dec.scala 133:19]
+  wire [31:0] tlu_io_trigger_pkt_any_2_tdata2; // @[dec.scala 133:19]
+  wire  tlu_io_trigger_pkt_any_3_select; // @[dec.scala 133:19]
+  wire  tlu_io_trigger_pkt_any_3_match_pkt; // @[dec.scala 133:19]
+  wire  tlu_io_trigger_pkt_any_3_store; // @[dec.scala 133:19]
+  wire  tlu_io_trigger_pkt_any_3_load; // @[dec.scala 133:19]
+  wire  tlu_io_trigger_pkt_any_3_execute; // @[dec.scala 133:19]
+  wire  tlu_io_trigger_pkt_any_3_m; // @[dec.scala 133:19]
+  wire [31:0] tlu_io_trigger_pkt_any_3_tdata2; // @[dec.scala 133:19]
+  wire  tlu_io_timer_int; // @[dec.scala 133:19]
+  wire  tlu_io_soft_int; // @[dec.scala 133:19]
+  wire  tlu_io_o_cpu_halt_status; // @[dec.scala 133:19]
+  wire  tlu_io_o_cpu_halt_ack; // @[dec.scala 133:19]
+  wire  tlu_io_o_cpu_run_ack; // @[dec.scala 133:19]
+  wire  tlu_io_o_debug_mode_status; // @[dec.scala 133:19]
+  wire [27:0] tlu_io_core_id; // @[dec.scala 133:19]
+  wire  tlu_io_mpc_debug_halt_req; // @[dec.scala 133:19]
+  wire  tlu_io_mpc_debug_run_req; // @[dec.scala 133:19]
+  wire  tlu_io_mpc_reset_run_req; // @[dec.scala 133:19]
+  wire  tlu_io_mpc_debug_halt_ack; // @[dec.scala 133:19]
+  wire  tlu_io_mpc_debug_run_ack; // @[dec.scala 133:19]
+  wire  tlu_io_debug_brkpt_status; // @[dec.scala 133:19]
+  wire [31:0] tlu_io_dec_csr_rddata_d; // @[dec.scala 133:19]
+  wire  tlu_io_dec_csr_legal_d; // @[dec.scala 133:19]
+  wire  tlu_io_dec_tlu_i0_kill_writeb_wb; // @[dec.scala 133:19]
+  wire  tlu_io_dec_tlu_i0_kill_writeb_r; // @[dec.scala 133:19]
+  wire  tlu_io_dec_tlu_wr_pause_r; // @[dec.scala 133:19]
+  wire  tlu_io_dec_tlu_flush_pause_r; // @[dec.scala 133:19]
+  wire  tlu_io_dec_tlu_presync_d; // @[dec.scala 133:19]
+  wire  tlu_io_dec_tlu_postsync_d; // @[dec.scala 133:19]
+  wire  tlu_io_dec_tlu_perfcnt0; // @[dec.scala 133:19]
+  wire  tlu_io_dec_tlu_perfcnt1; // @[dec.scala 133:19]
+  wire  tlu_io_dec_tlu_perfcnt2; // @[dec.scala 133:19]
+  wire  tlu_io_dec_tlu_perfcnt3; // @[dec.scala 133:19]
+  wire  tlu_io_dec_tlu_i0_exc_valid_wb1; // @[dec.scala 133:19]
+  wire  tlu_io_dec_tlu_i0_valid_wb1; // @[dec.scala 133:19]
+  wire  tlu_io_dec_tlu_int_valid_wb1; // @[dec.scala 133:19]
+  wire [4:0] tlu_io_dec_tlu_exc_cause_wb1; // @[dec.scala 133:19]
+  wire [31:0] tlu_io_dec_tlu_mtval_wb1; // @[dec.scala 133:19]
+  wire  tlu_io_dec_tlu_pipelining_disable; // @[dec.scala 133:19]
+  wire  tlu_io_dec_tlu_trace_disable; // @[dec.scala 133:19]
+  wire  tlu_io_dec_tlu_misc_clk_override; // @[dec.scala 133:19]
+  wire  tlu_io_dec_tlu_dec_clk_override; // @[dec.scala 133:19]
+  wire  tlu_io_dec_tlu_ifu_clk_override; // @[dec.scala 133:19]
+  wire  tlu_io_dec_tlu_lsu_clk_override; // @[dec.scala 133:19]
+  wire  tlu_io_dec_tlu_bus_clk_override; // @[dec.scala 133:19]
+  wire  tlu_io_dec_tlu_pic_clk_override; // @[dec.scala 133:19]
+  wire  tlu_io_dec_tlu_picio_clk_override; // @[dec.scala 133:19]
+  wire  tlu_io_dec_tlu_dccm_clk_override; // @[dec.scala 133:19]
+  wire  tlu_io_dec_tlu_icm_clk_override; // @[dec.scala 133:19]
+  wire  tlu_io_dec_tlu_flush_lower_wb; // @[dec.scala 133:19]
+  wire  tlu_io_ifu_pmu_instr_aligned; // @[dec.scala 133:19]
+  wire  tlu_io_tlu_bp_dec_tlu_br0_r_pkt_valid; // @[dec.scala 133:19]
+  wire [1:0] tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_hist; // @[dec.scala 133:19]
+  wire  tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[dec.scala 133:19]
+  wire  tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[dec.scala 133:19]
+  wire  tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_way; // @[dec.scala 133:19]
+  wire  tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_middle; // @[dec.scala 133:19]
+  wire  tlu_io_tlu_bp_dec_tlu_flush_leak_one_wb; // @[dec.scala 133:19]
+  wire  tlu_io_tlu_bp_dec_tlu_bpred_disable; // @[dec.scala 133:19]
+  wire  tlu_io_tlu_ifc_dec_tlu_flush_noredir_wb; // @[dec.scala 133:19]
+  wire [31:0] tlu_io_tlu_ifc_dec_tlu_mrac_ff; // @[dec.scala 133:19]
+  wire  tlu_io_tlu_ifc_ifu_pmu_fetch_stall; // @[dec.scala 133:19]
+  wire  tlu_io_tlu_mem_dec_tlu_flush_err_wb; // @[dec.scala 133:19]
+  wire  tlu_io_tlu_mem_dec_tlu_i0_commit_cmt; // @[dec.scala 133:19]
+  wire  tlu_io_tlu_mem_dec_tlu_force_halt; // @[dec.scala 133:19]
+  wire  tlu_io_tlu_mem_dec_tlu_fence_i_wb; // @[dec.scala 133:19]
+  wire [70:0] tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wrdata; // @[dec.scala 133:19]
+  wire [16:0] tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_dicawics; // @[dec.scala 133:19]
+  wire  tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[dec.scala 133:19]
+  wire  tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[dec.scala 133:19]
+  wire  tlu_io_tlu_mem_dec_tlu_core_ecc_disable; // @[dec.scala 133:19]
+  wire  tlu_io_tlu_mem_ifu_pmu_ic_miss; // @[dec.scala 133:19]
+  wire  tlu_io_tlu_mem_ifu_pmu_ic_hit; // @[dec.scala 133:19]
+  wire  tlu_io_tlu_mem_ifu_pmu_bus_error; // @[dec.scala 133:19]
+  wire  tlu_io_tlu_mem_ifu_pmu_bus_busy; // @[dec.scala 133:19]
+  wire  tlu_io_tlu_mem_ifu_pmu_bus_trxn; // @[dec.scala 133:19]
+  wire  tlu_io_tlu_mem_ifu_ic_error_start; // @[dec.scala 133:19]
+  wire  tlu_io_tlu_mem_ifu_iccm_rd_ecc_single_err; // @[dec.scala 133:19]
+  wire [70:0] tlu_io_tlu_mem_ifu_ic_debug_rd_data; // @[dec.scala 133:19]
+  wire  tlu_io_tlu_mem_ifu_ic_debug_rd_data_valid; // @[dec.scala 133:19]
+  wire  tlu_io_tlu_mem_ifu_miss_state_idle; // @[dec.scala 133:19]
+  wire  tlu_io_tlu_busbuff_lsu_pmu_bus_trxn; // @[dec.scala 133:19]
+  wire  tlu_io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[dec.scala 133:19]
+  wire  tlu_io_tlu_busbuff_lsu_pmu_bus_error; // @[dec.scala 133:19]
+  wire  tlu_io_tlu_busbuff_lsu_pmu_bus_busy; // @[dec.scala 133:19]
+  wire  tlu_io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[dec.scala 133:19]
+  wire  tlu_io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[dec.scala 133:19]
+  wire  tlu_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[dec.scala 133:19]
+  wire  tlu_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[dec.scala 133:19]
+  wire  tlu_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[dec.scala 133:19]
+  wire [31:0] tlu_io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[dec.scala 133:19]
+  wire  tlu_io_lsu_tlu_lsu_pmu_load_external_m; // @[dec.scala 133:19]
+  wire  tlu_io_lsu_tlu_lsu_pmu_store_external_m; // @[dec.scala 133:19]
+  wire [7:0] tlu_io_dec_pic_pic_claimid; // @[dec.scala 133:19]
+  wire [3:0] tlu_io_dec_pic_pic_pl; // @[dec.scala 133:19]
+  wire  tlu_io_dec_pic_mhwakeup; // @[dec.scala 133:19]
+  wire [3:0] tlu_io_dec_pic_dec_tlu_meicurpl; // @[dec.scala 133:19]
+  wire [3:0] tlu_io_dec_pic_dec_tlu_meipt; // @[dec.scala 133:19]
+  wire  tlu_io_dec_pic_mexintpend; // @[dec.scala 133:19]
+  wire  dec_trigger_io_trigger_pkt_any_0_select; // @[dec.scala 134:27]
+  wire  dec_trigger_io_trigger_pkt_any_0_match_pkt; // @[dec.scala 134:27]
+  wire  dec_trigger_io_trigger_pkt_any_0_execute; // @[dec.scala 134:27]
+  wire  dec_trigger_io_trigger_pkt_any_0_m; // @[dec.scala 134:27]
+  wire [31:0] dec_trigger_io_trigger_pkt_any_0_tdata2; // @[dec.scala 134:27]
+  wire  dec_trigger_io_trigger_pkt_any_1_select; // @[dec.scala 134:27]
+  wire  dec_trigger_io_trigger_pkt_any_1_match_pkt; // @[dec.scala 134:27]
+  wire  dec_trigger_io_trigger_pkt_any_1_execute; // @[dec.scala 134:27]
+  wire  dec_trigger_io_trigger_pkt_any_1_m; // @[dec.scala 134:27]
+  wire [31:0] dec_trigger_io_trigger_pkt_any_1_tdata2; // @[dec.scala 134:27]
+  wire  dec_trigger_io_trigger_pkt_any_2_select; // @[dec.scala 134:27]
+  wire  dec_trigger_io_trigger_pkt_any_2_match_pkt; // @[dec.scala 134:27]
+  wire  dec_trigger_io_trigger_pkt_any_2_execute; // @[dec.scala 134:27]
+  wire  dec_trigger_io_trigger_pkt_any_2_m; // @[dec.scala 134:27]
+  wire [31:0] dec_trigger_io_trigger_pkt_any_2_tdata2; // @[dec.scala 134:27]
+  wire  dec_trigger_io_trigger_pkt_any_3_select; // @[dec.scala 134:27]
+  wire  dec_trigger_io_trigger_pkt_any_3_match_pkt; // @[dec.scala 134:27]
+  wire  dec_trigger_io_trigger_pkt_any_3_execute; // @[dec.scala 134:27]
+  wire  dec_trigger_io_trigger_pkt_any_3_m; // @[dec.scala 134:27]
+  wire [31:0] dec_trigger_io_trigger_pkt_any_3_tdata2; // @[dec.scala 134:27]
+  wire [30:0] dec_trigger_io_dec_i0_pc_d; // @[dec.scala 134:27]
+  wire [3:0] dec_trigger_io_dec_i0_trigger_match_d; // @[dec.scala 134:27]
+  wire  _T_1 = tlu_io_dec_tlu_int_valid_wb1 | tlu_io_dec_tlu_i0_valid_wb1; // @[dec.scala 314:71]
+  dec_ib_ctl instbuff ( // @[dec.scala 130:24]
     .io_ifu_ib_ifu_i0_icaf(instbuff_io_ifu_ib_ifu_i0_icaf),
     .io_ifu_ib_ifu_i0_icaf_type(instbuff_io_ifu_ib_ifu_i0_icaf_type),
     .io_ifu_ib_ifu_i0_icaf_second(instbuff_io_ifu_ib_ifu_i0_icaf_second),
@@ -15685,7 +15692,7 @@ module dec(
     .io_dec_i0_dbecc_d(instbuff_io_dec_i0_dbecc_d),
     .io_dec_debug_fence_d(instbuff_io_dec_debug_fence_d)
   );
-  dec_decode_ctl decode ( // @[dec.scala 129:22]
+  dec_decode_ctl decode ( // @[dec.scala 131:22]
     .clock(decode_clock),
     .reset(decode_reset),
     .io_decode_exu_dec_data_en(decode_io_decode_exu_dec_data_en),
@@ -15797,7 +15804,6 @@ module dec(
     .io_dctl_busbuff_lsu_nonblock_load_data_error(decode_io_dctl_busbuff_lsu_nonblock_load_data_error),
     .io_dctl_busbuff_lsu_nonblock_load_data_tag(decode_io_dctl_busbuff_lsu_nonblock_load_data_tag),
     .io_dctl_dma_dma_dccm_stall_any(decode_io_dctl_dma_dma_dccm_stall_any),
-    .io_dec_aln_dec_i0_decode_d(decode_io_dec_aln_dec_i0_decode_d),
     .io_dec_aln_ifu_i0_cinst(decode_io_dec_aln_ifu_i0_cinst),
     .io_dbg_dctl_dbg_cmd_wrdata(decode_io_dbg_dctl_dbg_cmd_wrdata),
     .io_dec_tlu_trace_disable(decode_io_dec_tlu_trace_disable),
@@ -15898,9 +15904,10 @@ module dec(
     .io_dec_nonblock_load_waddr(decode_io_dec_nonblock_load_waddr),
     .io_dec_pause_state(decode_io_dec_pause_state),
     .io_dec_pause_state_cg(decode_io_dec_pause_state_cg),
-    .io_dec_div_active(decode_io_dec_div_active)
+    .io_dec_div_active(decode_io_dec_div_active),
+    .io_dec_i0_decode_d(decode_io_dec_i0_decode_d)
   );
-  dec_gpr_ctl gpr ( // @[dec.scala 130:19]
+  dec_gpr_ctl gpr ( // @[dec.scala 132:19]
     .clock(gpr_clock),
     .reset(gpr_reset),
     .io_raddr0(gpr_io_raddr0),
@@ -15917,7 +15924,7 @@ module dec(
     .io_gpr_exu_gpr_i0_rs1_d(gpr_io_gpr_exu_gpr_i0_rs1_d),
     .io_gpr_exu_gpr_i0_rs2_d(gpr_io_gpr_exu_gpr_i0_rs2_d)
   );
-  dec_tlu_ctl tlu ( // @[dec.scala 131:19]
+  dec_tlu_ctl tlu ( // @[dec.scala 133:19]
     .clock(tlu_clock),
     .reset(tlu_reset),
     .io_tlu_exu_dec_tlu_meihap(tlu_io_tlu_exu_dec_tlu_meihap),
@@ -16065,6 +16072,7 @@ module dec(
     .io_dec_tlu_lsu_clk_override(tlu_io_dec_tlu_lsu_clk_override),
     .io_dec_tlu_bus_clk_override(tlu_io_dec_tlu_bus_clk_override),
     .io_dec_tlu_pic_clk_override(tlu_io_dec_tlu_pic_clk_override),
+    .io_dec_tlu_picio_clk_override(tlu_io_dec_tlu_picio_clk_override),
     .io_dec_tlu_dccm_clk_override(tlu_io_dec_tlu_dccm_clk_override),
     .io_dec_tlu_icm_clk_override(tlu_io_dec_tlu_icm_clk_override),
     .io_dec_tlu_flush_lower_wb(tlu_io_dec_tlu_flush_lower_wb),
@@ -16118,7 +16126,7 @@ module dec(
     .io_dec_pic_dec_tlu_meipt(tlu_io_dec_pic_dec_tlu_meipt),
     .io_dec_pic_mexintpend(tlu_io_dec_pic_mexintpend)
   );
-  dec_trigger dec_trigger ( // @[dec.scala 132:27]
+  dec_trigger dec_trigger ( // @[dec.scala 134:27]
     .io_trigger_pkt_any_0_select(dec_trigger_io_trigger_pkt_any_0_select),
     .io_trigger_pkt_any_0_match_pkt(dec_trigger_io_trigger_pkt_any_0_match_pkt),
     .io_trigger_pkt_any_0_execute(dec_trigger_io_trigger_pkt_any_0_execute),
@@ -16142,441 +16150,441 @@ module dec(
     .io_dec_i0_pc_d(dec_trigger_io_dec_i0_pc_d),
     .io_dec_i0_trigger_match_d(dec_trigger_io_dec_i0_trigger_match_d)
   );
-  assign io_dec_pause_state_cg = decode_io_dec_pause_state_cg; // @[dec.scala 202:48]
-  assign io_dec_tlu_core_empty = tlu_io_dec_tlu_core_empty; // @[dec.scala 304:36]
-  assign io_dec_fa_error_index = 9'h0; // @[dec.scala 204:48]
-  assign io_o_cpu_halt_status = tlu_io_o_cpu_halt_status; // @[dec.scala 279:29]
-  assign io_o_cpu_halt_ack = tlu_io_o_cpu_halt_ack; // @[dec.scala 280:29]
-  assign io_o_cpu_run_ack = tlu_io_o_cpu_run_ack; // @[dec.scala 281:29]
-  assign io_o_debug_mode_status = tlu_io_o_debug_mode_status; // @[dec.scala 282:29]
-  assign io_mpc_debug_halt_ack = tlu_io_mpc_debug_halt_ack; // @[dec.scala 283:29]
-  assign io_mpc_debug_run_ack = tlu_io_mpc_debug_run_ack; // @[dec.scala 284:29]
-  assign io_debug_brkpt_status = tlu_io_debug_brkpt_status; // @[dec.scala 285:29]
-  assign io_dec_tlu_dbg_halted = tlu_io_dec_tlu_dbg_halted; // @[dec.scala 274:28]
-  assign io_dec_tlu_debug_mode = tlu_io_dec_tlu_debug_mode; // @[dec.scala 275:28]
-  assign io_dec_tlu_resume_ack = tlu_io_dec_tlu_resume_ack; // @[dec.scala 276:28]
-  assign io_dec_tlu_mpc_halted_only = tlu_io_dec_tlu_mpc_halted_only; // @[dec.scala 277:51]
-  assign io_dec_dbg_rddata = decode_io_dec_i0_wdata_r; // @[dec.scala 320:21]
-  assign io_dec_csr_rddata_d = tlu_io_dec_csr_rddata_d; // @[dec.scala 305:36]
-  assign io_dec_dbg_cmd_done = tlu_io_dec_dbg_cmd_done; // @[dec.scala 272:28]
-  assign io_dec_dbg_cmd_fail = tlu_io_dec_dbg_cmd_fail; // @[dec.scala 273:28]
-  assign io_trigger_pkt_any_0_select = tlu_io_trigger_pkt_any_0_select; // @[dec.scala 278:29]
-  assign io_trigger_pkt_any_0_match_pkt = tlu_io_trigger_pkt_any_0_match_pkt; // @[dec.scala 278:29]
-  assign io_trigger_pkt_any_0_store = tlu_io_trigger_pkt_any_0_store; // @[dec.scala 278:29]
-  assign io_trigger_pkt_any_0_load = tlu_io_trigger_pkt_any_0_load; // @[dec.scala 278:29]
-  assign io_trigger_pkt_any_0_execute = tlu_io_trigger_pkt_any_0_execute; // @[dec.scala 278:29]
-  assign io_trigger_pkt_any_0_m = tlu_io_trigger_pkt_any_0_m; // @[dec.scala 278:29]
-  assign io_trigger_pkt_any_0_tdata2 = tlu_io_trigger_pkt_any_0_tdata2; // @[dec.scala 278:29]
-  assign io_trigger_pkt_any_1_select = tlu_io_trigger_pkt_any_1_select; // @[dec.scala 278:29]
-  assign io_trigger_pkt_any_1_match_pkt = tlu_io_trigger_pkt_any_1_match_pkt; // @[dec.scala 278:29]
-  assign io_trigger_pkt_any_1_store = tlu_io_trigger_pkt_any_1_store; // @[dec.scala 278:29]
-  assign io_trigger_pkt_any_1_load = tlu_io_trigger_pkt_any_1_load; // @[dec.scala 278:29]
-  assign io_trigger_pkt_any_1_execute = tlu_io_trigger_pkt_any_1_execute; // @[dec.scala 278:29]
-  assign io_trigger_pkt_any_1_m = tlu_io_trigger_pkt_any_1_m; // @[dec.scala 278:29]
-  assign io_trigger_pkt_any_1_tdata2 = tlu_io_trigger_pkt_any_1_tdata2; // @[dec.scala 278:29]
-  assign io_trigger_pkt_any_2_select = tlu_io_trigger_pkt_any_2_select; // @[dec.scala 278:29]
-  assign io_trigger_pkt_any_2_match_pkt = tlu_io_trigger_pkt_any_2_match_pkt; // @[dec.scala 278:29]
-  assign io_trigger_pkt_any_2_store = tlu_io_trigger_pkt_any_2_store; // @[dec.scala 278:29]
-  assign io_trigger_pkt_any_2_load = tlu_io_trigger_pkt_any_2_load; // @[dec.scala 278:29]
-  assign io_trigger_pkt_any_2_execute = tlu_io_trigger_pkt_any_2_execute; // @[dec.scala 278:29]
-  assign io_trigger_pkt_any_2_m = tlu_io_trigger_pkt_any_2_m; // @[dec.scala 278:29]
-  assign io_trigger_pkt_any_2_tdata2 = tlu_io_trigger_pkt_any_2_tdata2; // @[dec.scala 278:29]
-  assign io_trigger_pkt_any_3_select = tlu_io_trigger_pkt_any_3_select; // @[dec.scala 278:29]
-  assign io_trigger_pkt_any_3_match_pkt = tlu_io_trigger_pkt_any_3_match_pkt; // @[dec.scala 278:29]
-  assign io_trigger_pkt_any_3_store = tlu_io_trigger_pkt_any_3_store; // @[dec.scala 278:29]
-  assign io_trigger_pkt_any_3_load = tlu_io_trigger_pkt_any_3_load; // @[dec.scala 278:29]
-  assign io_trigger_pkt_any_3_execute = tlu_io_trigger_pkt_any_3_execute; // @[dec.scala 278:29]
-  assign io_trigger_pkt_any_3_m = tlu_io_trigger_pkt_any_3_m; // @[dec.scala 278:29]
-  assign io_trigger_pkt_any_3_tdata2 = tlu_io_trigger_pkt_any_3_tdata2; // @[dec.scala 278:29]
-  assign io_lsu_p_valid = decode_io_lsu_p_valid; // @[dec.scala 199:48]
-  assign io_lsu_p_bits_fast_int = decode_io_lsu_p_bits_fast_int; // @[dec.scala 199:48]
-  assign io_lsu_p_bits_stack = decode_io_lsu_p_bits_stack; // @[dec.scala 199:48]
-  assign io_lsu_p_bits_by = decode_io_lsu_p_bits_by; // @[dec.scala 199:48]
-  assign io_lsu_p_bits_half = decode_io_lsu_p_bits_half; // @[dec.scala 199:48]
-  assign io_lsu_p_bits_word = decode_io_lsu_p_bits_word; // @[dec.scala 199:48]
-  assign io_lsu_p_bits_dword = 1'h0; // @[dec.scala 199:48]
-  assign io_lsu_p_bits_load = decode_io_lsu_p_bits_load; // @[dec.scala 199:48]
-  assign io_lsu_p_bits_store = decode_io_lsu_p_bits_store; // @[dec.scala 199:48]
-  assign io_lsu_p_bits_unsign = decode_io_lsu_p_bits_unsign; // @[dec.scala 199:48]
-  assign io_lsu_p_bits_dma = 1'h0; // @[dec.scala 199:48]
-  assign io_lsu_p_bits_store_data_bypass_d = decode_io_lsu_p_bits_store_data_bypass_d; // @[dec.scala 199:48]
-  assign io_lsu_p_bits_load_ldst_bypass_d = decode_io_lsu_p_bits_load_ldst_bypass_d; // @[dec.scala 199:48]
-  assign io_lsu_p_bits_store_data_bypass_m = 1'h0; // @[dec.scala 199:48]
-  assign io_dec_lsu_offset_d = decode_io_dec_lsu_offset_d; // @[dec.scala 201:48]
-  assign io_dec_tlu_i0_kill_writeb_r = tlu_io_dec_tlu_i0_kill_writeb_r; // @[dec.scala 286:34]
-  assign io_dec_tlu_perfcnt0 = tlu_io_dec_tlu_perfcnt0; // @[dec.scala 287:29]
-  assign io_dec_tlu_perfcnt1 = tlu_io_dec_tlu_perfcnt1; // @[dec.scala 288:29]
-  assign io_dec_tlu_perfcnt2 = tlu_io_dec_tlu_perfcnt2; // @[dec.scala 289:29]
-  assign io_dec_tlu_perfcnt3 = tlu_io_dec_tlu_perfcnt3; // @[dec.scala 290:29]
-  assign io_dec_tlu_flush_lower_wb = tlu_io_dec_tlu_flush_lower_wb; // @[dec.scala 306:36]
-  assign io_dec_lsu_valid_raw_d = decode_io_dec_lsu_valid_raw_d; // @[dec.scala 200:48]
-  assign io_trace_rv_trace_pkt_rv_i_valid_ip = _T_1 | tlu_io_dec_tlu_i0_exc_valid_wb1; // @[dec.scala 312:39]
-  assign io_trace_rv_trace_pkt_rv_i_insn_ip = decode_io_dec_i0_inst_wb; // @[dec.scala 310:38]
-  assign io_trace_rv_trace_pkt_rv_i_address_ip = {decode_io_dec_i0_pc_wb,1'h0}; // @[dec.scala 311:41]
-  assign io_trace_rv_trace_pkt_rv_i_exception_ip = tlu_io_dec_tlu_int_valid_wb1 | tlu_io_dec_tlu_i0_exc_valid_wb1; // @[dec.scala 313:43]
-  assign io_trace_rv_trace_pkt_rv_i_ecause_ip = tlu_io_dec_tlu_exc_cause_wb1; // @[dec.scala 314:40]
-  assign io_trace_rv_trace_pkt_rv_i_interrupt_ip = tlu_io_dec_tlu_int_valid_wb1; // @[dec.scala 315:43]
-  assign io_trace_rv_trace_pkt_rv_i_tval_ip = tlu_io_dec_tlu_mtval_wb1; // @[dec.scala 316:38]
-  assign io_dec_tlu_misc_clk_override = tlu_io_dec_tlu_misc_clk_override; // @[dec.scala 296:35]
-  assign io_dec_tlu_ifu_clk_override = tlu_io_dec_tlu_ifu_clk_override; // @[dec.scala 297:36]
-  assign io_dec_tlu_lsu_clk_override = tlu_io_dec_tlu_lsu_clk_override; // @[dec.scala 298:36]
-  assign io_dec_tlu_bus_clk_override = tlu_io_dec_tlu_bus_clk_override; // @[dec.scala 299:36]
-  assign io_dec_tlu_pic_clk_override = tlu_io_dec_tlu_pic_clk_override; // @[dec.scala 300:36]
-  assign io_dec_tlu_picio_clk_override = tlu_io_dec_tlu_icm_clk_override; // @[dec.scala 303:36]
-  assign io_dec_tlu_dccm_clk_override = tlu_io_dec_tlu_dccm_clk_override; // @[dec.scala 301:36]
-  assign io_dec_tlu_icm_clk_override = tlu_io_dec_tlu_icm_clk_override; // @[dec.scala 302:36]
-  assign io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d = decode_io_dec_aln_dec_i0_decode_d; // @[dec.scala 145:21]
-  assign io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb = tlu_io_tlu_mem_dec_tlu_flush_err_wb; // @[dec.scala 220:18]
-  assign io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt = tlu_io_tlu_mem_dec_tlu_i0_commit_cmt; // @[dec.scala 220:18]
-  assign io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt = tlu_io_tlu_mem_dec_tlu_force_halt; // @[dec.scala 220:18]
-  assign io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb = tlu_io_tlu_mem_dec_tlu_fence_i_wb; // @[dec.scala 220:18]
-  assign io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata = tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wrdata; // @[dec.scala 220:18]
-  assign io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics = tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_dicawics; // @[dec.scala 220:18]
-  assign io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid = tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[dec.scala 220:18]
-  assign io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid = tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[dec.scala 220:18]
-  assign io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable = tlu_io_tlu_mem_dec_tlu_core_ecc_disable; // @[dec.scala 220:18]
-  assign io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb = tlu_io_tlu_ifc_dec_tlu_flush_noredir_wb; // @[dec.scala 221:18]
-  assign io_ifu_dec_dec_ifc_dec_tlu_mrac_ff = tlu_io_tlu_ifc_dec_tlu_mrac_ff; // @[dec.scala 221:18]
-  assign io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid = tlu_io_tlu_bp_dec_tlu_br0_r_pkt_valid; // @[dec.scala 222:18]
-  assign io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist = tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_hist; // @[dec.scala 222:18]
-  assign io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error = tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[dec.scala 222:18]
-  assign io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error = tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[dec.scala 222:18]
-  assign io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way = tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_way; // @[dec.scala 222:18]
-  assign io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle = tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_middle; // @[dec.scala 222:18]
-  assign io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb = tlu_io_tlu_bp_dec_tlu_flush_leak_one_wb; // @[dec.scala 222:18]
-  assign io_ifu_dec_dec_bp_dec_tlu_bpred_disable = tlu_io_tlu_bp_dec_tlu_bpred_disable; // @[dec.scala 222:18]
-  assign io_dec_exu_dec_alu_dec_i0_alu_decode_d = decode_io_dec_alu_dec_i0_alu_decode_d; // @[dec.scala 148:20]
-  assign io_dec_exu_dec_alu_dec_csr_ren_d = decode_io_dec_alu_dec_csr_ren_d; // @[dec.scala 148:20]
-  assign io_dec_exu_dec_alu_dec_i0_br_immed_d = decode_io_dec_alu_dec_i0_br_immed_d; // @[dec.scala 148:20]
-  assign io_dec_exu_dec_div_div_p_valid = decode_io_dec_div_div_p_valid; // @[dec.scala 149:20]
-  assign io_dec_exu_dec_div_div_p_bits_unsign = decode_io_dec_div_div_p_bits_unsign; // @[dec.scala 149:20]
-  assign io_dec_exu_dec_div_div_p_bits_rem = decode_io_dec_div_div_p_bits_rem; // @[dec.scala 149:20]
-  assign io_dec_exu_dec_div_dec_div_cancel = decode_io_dec_div_dec_div_cancel; // @[dec.scala 149:20]
-  assign io_dec_exu_decode_exu_dec_data_en = decode_io_decode_exu_dec_data_en; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_dec_ctl_en = decode_io_decode_exu_dec_ctl_en; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_i0_ap_clz = decode_io_decode_exu_i0_ap_clz; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_i0_ap_ctz = decode_io_decode_exu_i0_ap_ctz; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_i0_ap_pcnt = decode_io_decode_exu_i0_ap_pcnt; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_i0_ap_sext_b = decode_io_decode_exu_i0_ap_sext_b; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_i0_ap_sext_h = decode_io_decode_exu_i0_ap_sext_h; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_i0_ap_slo = decode_io_decode_exu_i0_ap_slo; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_i0_ap_sro = decode_io_decode_exu_i0_ap_sro; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_i0_ap_min = decode_io_decode_exu_i0_ap_min; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_i0_ap_max = decode_io_decode_exu_i0_ap_max; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_i0_ap_pack = decode_io_decode_exu_i0_ap_pack; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_i0_ap_packu = decode_io_decode_exu_i0_ap_packu; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_i0_ap_packh = decode_io_decode_exu_i0_ap_packh; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_i0_ap_rol = decode_io_decode_exu_i0_ap_rol; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_i0_ap_ror = decode_io_decode_exu_i0_ap_ror; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_i0_ap_grev = decode_io_decode_exu_i0_ap_grev; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_i0_ap_gorc = decode_io_decode_exu_i0_ap_gorc; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_i0_ap_zbb = decode_io_decode_exu_i0_ap_zbb; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_i0_ap_sbset = decode_io_decode_exu_i0_ap_sbset; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_i0_ap_sbclr = decode_io_decode_exu_i0_ap_sbclr; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_i0_ap_sbinv = decode_io_decode_exu_i0_ap_sbinv; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_i0_ap_sbext = decode_io_decode_exu_i0_ap_sbext; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_i0_ap_sh1add = decode_io_decode_exu_i0_ap_sh1add; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_i0_ap_sh2add = decode_io_decode_exu_i0_ap_sh2add; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_i0_ap_sh3add = decode_io_decode_exu_i0_ap_sh3add; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_i0_ap_zba = decode_io_decode_exu_i0_ap_zba; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_i0_ap_land = decode_io_decode_exu_i0_ap_land; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_i0_ap_lor = decode_io_decode_exu_i0_ap_lor; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_i0_ap_lxor = decode_io_decode_exu_i0_ap_lxor; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_i0_ap_sll = decode_io_decode_exu_i0_ap_sll; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_i0_ap_srl = decode_io_decode_exu_i0_ap_srl; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_i0_ap_sra = decode_io_decode_exu_i0_ap_sra; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_i0_ap_beq = decode_io_decode_exu_i0_ap_beq; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_i0_ap_bne = decode_io_decode_exu_i0_ap_bne; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_i0_ap_blt = decode_io_decode_exu_i0_ap_blt; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_i0_ap_bge = decode_io_decode_exu_i0_ap_bge; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_i0_ap_add = decode_io_decode_exu_i0_ap_add; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_i0_ap_sub = decode_io_decode_exu_i0_ap_sub; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_i0_ap_slt = decode_io_decode_exu_i0_ap_slt; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_i0_ap_unsign = decode_io_decode_exu_i0_ap_unsign; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_i0_ap_jal = decode_io_decode_exu_i0_ap_jal; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_i0_ap_predict_t = decode_io_decode_exu_i0_ap_predict_t; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_i0_ap_predict_nt = decode_io_decode_exu_i0_ap_predict_nt; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_i0_ap_csr_write = decode_io_decode_exu_i0_ap_csr_write; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_i0_ap_csr_imm = decode_io_decode_exu_i0_ap_csr_imm; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_dec_i0_predict_p_d_valid = decode_io_decode_exu_dec_i0_predict_p_d_valid; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_misp = 1'h0; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_ataken = 1'h0; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_boffset = 1'h0; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4 = decode_io_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist = decode_io_decode_exu_dec_i0_predict_p_d_bits_hist; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset = decode_io_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error = decode_io_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error = decode_io_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall = decode_io_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja = decode_io_decode_exu_dec_i0_predict_p_d_bits_pja; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way = decode_io_decode_exu_dec_i0_predict_p_d_bits_way; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret = decode_io_decode_exu_dec_i0_predict_p_d_bits_pret; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett = decode_io_decode_exu_dec_i0_predict_p_d_bits_prett; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_i0_predict_fghr_d = decode_io_decode_exu_i0_predict_fghr_d; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_i0_predict_index_d = decode_io_decode_exu_i0_predict_index_d; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_i0_predict_btag_d = decode_io_decode_exu_i0_predict_btag_d; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_dec_i0_rs1_en_d = decode_io_decode_exu_dec_i0_rs1_en_d; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_dec_i0_branch_d = decode_io_decode_exu_dec_i0_branch_d; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_dec_i0_rs2_en_d = decode_io_decode_exu_dec_i0_rs2_en_d; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_dec_i0_immed_d = decode_io_decode_exu_dec_i0_immed_d; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_dec_i0_result_r = decode_io_decode_exu_dec_i0_result_r; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_dec_qual_lsu_d = decode_io_decode_exu_dec_qual_lsu_d; // @[dec.scala 147:23 dec.scala 203:48]
-  assign io_dec_exu_decode_exu_dec_i0_select_pc_d = decode_io_decode_exu_dec_i0_select_pc_d; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d = decode_io_decode_exu_dec_i0_rs1_bypass_en_d; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d = decode_io_decode_exu_dec_i0_rs2_bypass_en_d; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_mul_p_valid = decode_io_decode_exu_mul_p_valid; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_mul_p_bits_rs1_sign = decode_io_decode_exu_mul_p_bits_rs1_sign; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_mul_p_bits_rs2_sign = decode_io_decode_exu_mul_p_bits_rs2_sign; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_mul_p_bits_low = decode_io_decode_exu_mul_p_bits_low; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_mul_p_bits_bext = decode_io_decode_exu_mul_p_bits_bext; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_mul_p_bits_bdep = decode_io_decode_exu_mul_p_bits_bdep; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_mul_p_bits_clmul = decode_io_decode_exu_mul_p_bits_clmul; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_mul_p_bits_clmulh = decode_io_decode_exu_mul_p_bits_clmulh; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_mul_p_bits_clmulr = decode_io_decode_exu_mul_p_bits_clmulr; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_mul_p_bits_grev = decode_io_decode_exu_mul_p_bits_grev; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_mul_p_bits_gorc = decode_io_decode_exu_mul_p_bits_gorc; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_mul_p_bits_shfl = decode_io_decode_exu_mul_p_bits_shfl; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_mul_p_bits_unshfl = decode_io_decode_exu_mul_p_bits_unshfl; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_mul_p_bits_crc32_b = decode_io_decode_exu_mul_p_bits_crc32_b; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_mul_p_bits_crc32_h = decode_io_decode_exu_mul_p_bits_crc32_h; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_mul_p_bits_crc32_w = decode_io_decode_exu_mul_p_bits_crc32_w; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_mul_p_bits_crc32c_b = decode_io_decode_exu_mul_p_bits_crc32c_b; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_mul_p_bits_crc32c_h = decode_io_decode_exu_mul_p_bits_crc32c_h; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_mul_p_bits_crc32c_w = decode_io_decode_exu_mul_p_bits_crc32c_w; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_mul_p_bits_bfp = decode_io_decode_exu_mul_p_bits_bfp; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_pred_correct_npc_x = decode_io_decode_exu_pred_correct_npc_x; // @[dec.scala 147:23]
-  assign io_dec_exu_decode_exu_dec_extint_stall = decode_io_decode_exu_dec_extint_stall; // @[dec.scala 147:23]
-  assign io_dec_exu_tlu_exu_dec_tlu_meihap = tlu_io_tlu_exu_dec_tlu_meihap; // @[dec.scala 223:18]
-  assign io_dec_exu_tlu_exu_dec_tlu_flush_lower_r = tlu_io_tlu_exu_dec_tlu_flush_lower_r; // @[dec.scala 223:18]
-  assign io_dec_exu_tlu_exu_dec_tlu_flush_path_r = tlu_io_tlu_exu_dec_tlu_flush_path_r; // @[dec.scala 223:18]
-  assign io_dec_exu_ib_exu_dec_i0_pc_d = instbuff_io_ib_exu_dec_i0_pc_d; // @[dec.scala 137:22]
-  assign io_dec_exu_ib_exu_dec_debug_wdata_rs1_d = instbuff_io_ib_exu_dec_debug_wdata_rs1_d; // @[dec.scala 137:22]
-  assign io_dec_exu_gpr_exu_gpr_i0_rs1_d = gpr_io_gpr_exu_gpr_i0_rs1_d; // @[dec.scala 218:22]
-  assign io_dec_exu_gpr_exu_gpr_i0_rs2_d = gpr_io_gpr_exu_gpr_i0_rs2_d; // @[dec.scala 218:22]
-  assign io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable = tlu_io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[dec.scala 240:26]
-  assign io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable = tlu_io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[dec.scala 240:26]
-  assign io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable = tlu_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[dec.scala 240:26]
-  assign io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty = tlu_io_tlu_dma_dec_tlu_dma_qos_prty; // @[dec.scala 224:18]
-  assign io_dec_pic_dec_tlu_meicurpl = tlu_io_dec_pic_dec_tlu_meicurpl; // @[dec.scala 242:14]
-  assign io_dec_pic_dec_tlu_meipt = tlu_io_dec_pic_dec_tlu_meipt; // @[dec.scala 242:14]
-  assign instbuff_io_ifu_ib_ifu_i0_icaf = io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf; // @[dec.scala 136:22]
-  assign instbuff_io_ifu_ib_ifu_i0_icaf_type = io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type; // @[dec.scala 136:22]
-  assign instbuff_io_ifu_ib_ifu_i0_icaf_second = io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_second; // @[dec.scala 136:22]
-  assign instbuff_io_ifu_ib_ifu_i0_dbecc = io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc; // @[dec.scala 136:22]
-  assign instbuff_io_ifu_ib_ifu_i0_bp_index = io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index; // @[dec.scala 136:22]
-  assign instbuff_io_ifu_ib_ifu_i0_bp_fghr = io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[dec.scala 136:22]
-  assign instbuff_io_ifu_ib_ifu_i0_bp_btag = io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag; // @[dec.scala 136:22]
-  assign instbuff_io_ifu_ib_ifu_i0_valid = io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid; // @[dec.scala 136:22]
-  assign instbuff_io_ifu_ib_ifu_i0_instr = io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr; // @[dec.scala 136:22]
-  assign instbuff_io_ifu_ib_ifu_i0_pc = io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc; // @[dec.scala 136:22]
-  assign instbuff_io_ifu_ib_ifu_i0_pc4 = io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4; // @[dec.scala 136:22]
-  assign instbuff_io_ifu_ib_i0_brp_valid = io_ifu_dec_dec_aln_aln_ib_i0_brp_valid; // @[dec.scala 136:22]
-  assign instbuff_io_ifu_ib_i0_brp_bits_toffset = io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset; // @[dec.scala 136:22]
-  assign instbuff_io_ifu_ib_i0_brp_bits_hist = io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist; // @[dec.scala 136:22]
-  assign instbuff_io_ifu_ib_i0_brp_bits_br_error = io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error; // @[dec.scala 136:22]
-  assign instbuff_io_ifu_ib_i0_brp_bits_br_start_error = io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[dec.scala 136:22]
-  assign instbuff_io_ifu_ib_i0_brp_bits_prett = io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett; // @[dec.scala 136:22]
-  assign instbuff_io_ifu_ib_i0_brp_bits_way = io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way; // @[dec.scala 136:22]
-  assign instbuff_io_ifu_ib_i0_brp_bits_ret = io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret; // @[dec.scala 136:22]
-  assign instbuff_io_dbg_ib_dbg_cmd_valid = io_dec_dbg_dbg_ib_dbg_cmd_valid; // @[dec.scala 138:22]
-  assign instbuff_io_dbg_ib_dbg_cmd_write = io_dec_dbg_dbg_ib_dbg_cmd_write; // @[dec.scala 138:22]
-  assign instbuff_io_dbg_ib_dbg_cmd_type = io_dec_dbg_dbg_ib_dbg_cmd_type; // @[dec.scala 138:22]
-  assign instbuff_io_dbg_ib_dbg_cmd_addr = io_dec_dbg_dbg_ib_dbg_cmd_addr; // @[dec.scala 138:22]
+  assign io_dec_pause_state_cg = decode_io_dec_pause_state_cg; // @[dec.scala 204:48]
+  assign io_dec_tlu_core_empty = tlu_io_dec_tlu_core_empty; // @[dec.scala 306:36]
+  assign io_dec_fa_error_index = 9'h0; // @[dec.scala 206:48]
+  assign io_o_cpu_halt_status = tlu_io_o_cpu_halt_status; // @[dec.scala 281:29]
+  assign io_o_cpu_halt_ack = tlu_io_o_cpu_halt_ack; // @[dec.scala 282:29]
+  assign io_o_cpu_run_ack = tlu_io_o_cpu_run_ack; // @[dec.scala 283:29]
+  assign io_o_debug_mode_status = tlu_io_o_debug_mode_status; // @[dec.scala 284:29]
+  assign io_mpc_debug_halt_ack = tlu_io_mpc_debug_halt_ack; // @[dec.scala 285:29]
+  assign io_mpc_debug_run_ack = tlu_io_mpc_debug_run_ack; // @[dec.scala 286:29]
+  assign io_debug_brkpt_status = tlu_io_debug_brkpt_status; // @[dec.scala 287:29]
+  assign io_dec_tlu_dbg_halted = tlu_io_dec_tlu_dbg_halted; // @[dec.scala 276:28]
+  assign io_dec_tlu_debug_mode = tlu_io_dec_tlu_debug_mode; // @[dec.scala 277:28]
+  assign io_dec_tlu_resume_ack = tlu_io_dec_tlu_resume_ack; // @[dec.scala 278:28]
+  assign io_dec_tlu_mpc_halted_only = tlu_io_dec_tlu_mpc_halted_only; // @[dec.scala 279:51]
+  assign io_dec_dbg_rddata = decode_io_dec_i0_wdata_r; // @[dec.scala 322:21]
+  assign io_dec_csr_rddata_d = tlu_io_dec_csr_rddata_d; // @[dec.scala 307:36]
+  assign io_dec_dbg_cmd_done = tlu_io_dec_dbg_cmd_done; // @[dec.scala 274:28]
+  assign io_dec_dbg_cmd_fail = tlu_io_dec_dbg_cmd_fail; // @[dec.scala 275:28]
+  assign io_trigger_pkt_any_0_select = tlu_io_trigger_pkt_any_0_select; // @[dec.scala 280:29]
+  assign io_trigger_pkt_any_0_match_pkt = tlu_io_trigger_pkt_any_0_match_pkt; // @[dec.scala 280:29]
+  assign io_trigger_pkt_any_0_store = tlu_io_trigger_pkt_any_0_store; // @[dec.scala 280:29]
+  assign io_trigger_pkt_any_0_load = tlu_io_trigger_pkt_any_0_load; // @[dec.scala 280:29]
+  assign io_trigger_pkt_any_0_execute = tlu_io_trigger_pkt_any_0_execute; // @[dec.scala 280:29]
+  assign io_trigger_pkt_any_0_m = tlu_io_trigger_pkt_any_0_m; // @[dec.scala 280:29]
+  assign io_trigger_pkt_any_0_tdata2 = tlu_io_trigger_pkt_any_0_tdata2; // @[dec.scala 280:29]
+  assign io_trigger_pkt_any_1_select = tlu_io_trigger_pkt_any_1_select; // @[dec.scala 280:29]
+  assign io_trigger_pkt_any_1_match_pkt = tlu_io_trigger_pkt_any_1_match_pkt; // @[dec.scala 280:29]
+  assign io_trigger_pkt_any_1_store = tlu_io_trigger_pkt_any_1_store; // @[dec.scala 280:29]
+  assign io_trigger_pkt_any_1_load = tlu_io_trigger_pkt_any_1_load; // @[dec.scala 280:29]
+  assign io_trigger_pkt_any_1_execute = tlu_io_trigger_pkt_any_1_execute; // @[dec.scala 280:29]
+  assign io_trigger_pkt_any_1_m = tlu_io_trigger_pkt_any_1_m; // @[dec.scala 280:29]
+  assign io_trigger_pkt_any_1_tdata2 = tlu_io_trigger_pkt_any_1_tdata2; // @[dec.scala 280:29]
+  assign io_trigger_pkt_any_2_select = tlu_io_trigger_pkt_any_2_select; // @[dec.scala 280:29]
+  assign io_trigger_pkt_any_2_match_pkt = tlu_io_trigger_pkt_any_2_match_pkt; // @[dec.scala 280:29]
+  assign io_trigger_pkt_any_2_store = tlu_io_trigger_pkt_any_2_store; // @[dec.scala 280:29]
+  assign io_trigger_pkt_any_2_load = tlu_io_trigger_pkt_any_2_load; // @[dec.scala 280:29]
+  assign io_trigger_pkt_any_2_execute = tlu_io_trigger_pkt_any_2_execute; // @[dec.scala 280:29]
+  assign io_trigger_pkt_any_2_m = tlu_io_trigger_pkt_any_2_m; // @[dec.scala 280:29]
+  assign io_trigger_pkt_any_2_tdata2 = tlu_io_trigger_pkt_any_2_tdata2; // @[dec.scala 280:29]
+  assign io_trigger_pkt_any_3_select = tlu_io_trigger_pkt_any_3_select; // @[dec.scala 280:29]
+  assign io_trigger_pkt_any_3_match_pkt = tlu_io_trigger_pkt_any_3_match_pkt; // @[dec.scala 280:29]
+  assign io_trigger_pkt_any_3_store = tlu_io_trigger_pkt_any_3_store; // @[dec.scala 280:29]
+  assign io_trigger_pkt_any_3_load = tlu_io_trigger_pkt_any_3_load; // @[dec.scala 280:29]
+  assign io_trigger_pkt_any_3_execute = tlu_io_trigger_pkt_any_3_execute; // @[dec.scala 280:29]
+  assign io_trigger_pkt_any_3_m = tlu_io_trigger_pkt_any_3_m; // @[dec.scala 280:29]
+  assign io_trigger_pkt_any_3_tdata2 = tlu_io_trigger_pkt_any_3_tdata2; // @[dec.scala 280:29]
+  assign io_lsu_p_valid = decode_io_lsu_p_valid; // @[dec.scala 201:48]
+  assign io_lsu_p_bits_fast_int = decode_io_lsu_p_bits_fast_int; // @[dec.scala 201:48]
+  assign io_lsu_p_bits_stack = decode_io_lsu_p_bits_stack; // @[dec.scala 201:48]
+  assign io_lsu_p_bits_by = decode_io_lsu_p_bits_by; // @[dec.scala 201:48]
+  assign io_lsu_p_bits_half = decode_io_lsu_p_bits_half; // @[dec.scala 201:48]
+  assign io_lsu_p_bits_word = decode_io_lsu_p_bits_word; // @[dec.scala 201:48]
+  assign io_lsu_p_bits_dword = 1'h0; // @[dec.scala 201:48]
+  assign io_lsu_p_bits_load = decode_io_lsu_p_bits_load; // @[dec.scala 201:48]
+  assign io_lsu_p_bits_store = decode_io_lsu_p_bits_store; // @[dec.scala 201:48]
+  assign io_lsu_p_bits_unsign = decode_io_lsu_p_bits_unsign; // @[dec.scala 201:48]
+  assign io_lsu_p_bits_dma = 1'h0; // @[dec.scala 201:48]
+  assign io_lsu_p_bits_store_data_bypass_d = decode_io_lsu_p_bits_store_data_bypass_d; // @[dec.scala 201:48]
+  assign io_lsu_p_bits_load_ldst_bypass_d = decode_io_lsu_p_bits_load_ldst_bypass_d; // @[dec.scala 201:48]
+  assign io_lsu_p_bits_store_data_bypass_m = 1'h0; // @[dec.scala 201:48]
+  assign io_dec_lsu_offset_d = decode_io_dec_lsu_offset_d; // @[dec.scala 203:48]
+  assign io_dec_tlu_i0_kill_writeb_r = tlu_io_dec_tlu_i0_kill_writeb_r; // @[dec.scala 288:34]
+  assign io_dec_tlu_perfcnt0 = tlu_io_dec_tlu_perfcnt0; // @[dec.scala 289:29]
+  assign io_dec_tlu_perfcnt1 = tlu_io_dec_tlu_perfcnt1; // @[dec.scala 290:29]
+  assign io_dec_tlu_perfcnt2 = tlu_io_dec_tlu_perfcnt2; // @[dec.scala 291:29]
+  assign io_dec_tlu_perfcnt3 = tlu_io_dec_tlu_perfcnt3; // @[dec.scala 292:29]
+  assign io_dec_tlu_flush_lower_wb = tlu_io_dec_tlu_flush_lower_wb; // @[dec.scala 308:36]
+  assign io_dec_lsu_valid_raw_d = decode_io_dec_lsu_valid_raw_d; // @[dec.scala 202:48]
+  assign io_trace_rv_trace_pkt_rv_i_valid_ip = _T_1 | tlu_io_dec_tlu_i0_exc_valid_wb1; // @[dec.scala 314:39]
+  assign io_trace_rv_trace_pkt_rv_i_insn_ip = decode_io_dec_i0_inst_wb; // @[dec.scala 312:38]
+  assign io_trace_rv_trace_pkt_rv_i_address_ip = {decode_io_dec_i0_pc_wb,1'h0}; // @[dec.scala 313:41]
+  assign io_trace_rv_trace_pkt_rv_i_exception_ip = tlu_io_dec_tlu_int_valid_wb1 | tlu_io_dec_tlu_i0_exc_valid_wb1; // @[dec.scala 315:43]
+  assign io_trace_rv_trace_pkt_rv_i_ecause_ip = tlu_io_dec_tlu_exc_cause_wb1; // @[dec.scala 316:40]
+  assign io_trace_rv_trace_pkt_rv_i_interrupt_ip = tlu_io_dec_tlu_int_valid_wb1; // @[dec.scala 317:43]
+  assign io_trace_rv_trace_pkt_rv_i_tval_ip = tlu_io_dec_tlu_mtval_wb1; // @[dec.scala 318:38]
+  assign io_dec_tlu_misc_clk_override = tlu_io_dec_tlu_misc_clk_override; // @[dec.scala 298:35]
+  assign io_dec_tlu_ifu_clk_override = tlu_io_dec_tlu_ifu_clk_override; // @[dec.scala 299:36]
+  assign io_dec_tlu_lsu_clk_override = tlu_io_dec_tlu_lsu_clk_override; // @[dec.scala 300:36]
+  assign io_dec_tlu_bus_clk_override = tlu_io_dec_tlu_bus_clk_override; // @[dec.scala 301:36]
+  assign io_dec_tlu_pic_clk_override = tlu_io_dec_tlu_pic_clk_override; // @[dec.scala 302:36]
+  assign io_dec_tlu_picio_clk_override = tlu_io_dec_tlu_picio_clk_override; // @[dec.scala 305:36]
+  assign io_dec_tlu_dccm_clk_override = tlu_io_dec_tlu_dccm_clk_override; // @[dec.scala 303:36]
+  assign io_dec_tlu_icm_clk_override = tlu_io_dec_tlu_icm_clk_override; // @[dec.scala 304:36]
+  assign io_dec_i0_decode_d = decode_io_dec_i0_decode_d; // @[dec.scala 148:22]
+  assign io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb = tlu_io_tlu_mem_dec_tlu_flush_err_wb; // @[dec.scala 222:18]
+  assign io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt = tlu_io_tlu_mem_dec_tlu_i0_commit_cmt; // @[dec.scala 222:18]
+  assign io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt = tlu_io_tlu_mem_dec_tlu_force_halt; // @[dec.scala 222:18]
+  assign io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb = tlu_io_tlu_mem_dec_tlu_fence_i_wb; // @[dec.scala 222:18]
+  assign io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata = tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wrdata; // @[dec.scala 222:18]
+  assign io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics = tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_dicawics; // @[dec.scala 222:18]
+  assign io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid = tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[dec.scala 222:18]
+  assign io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid = tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[dec.scala 222:18]
+  assign io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable = tlu_io_tlu_mem_dec_tlu_core_ecc_disable; // @[dec.scala 222:18]
+  assign io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb = tlu_io_tlu_ifc_dec_tlu_flush_noredir_wb; // @[dec.scala 223:18]
+  assign io_ifu_dec_dec_ifc_dec_tlu_mrac_ff = tlu_io_tlu_ifc_dec_tlu_mrac_ff; // @[dec.scala 223:18]
+  assign io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid = tlu_io_tlu_bp_dec_tlu_br0_r_pkt_valid; // @[dec.scala 224:18]
+  assign io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist = tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_hist; // @[dec.scala 224:18]
+  assign io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error = tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[dec.scala 224:18]
+  assign io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error = tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[dec.scala 224:18]
+  assign io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way = tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_way; // @[dec.scala 224:18]
+  assign io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle = tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_middle; // @[dec.scala 224:18]
+  assign io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb = tlu_io_tlu_bp_dec_tlu_flush_leak_one_wb; // @[dec.scala 224:18]
+  assign io_ifu_dec_dec_bp_dec_tlu_bpred_disable = tlu_io_tlu_bp_dec_tlu_bpred_disable; // @[dec.scala 224:18]
+  assign io_dec_exu_dec_alu_dec_i0_alu_decode_d = decode_io_dec_alu_dec_i0_alu_decode_d; // @[dec.scala 150:20]
+  assign io_dec_exu_dec_alu_dec_csr_ren_d = decode_io_dec_alu_dec_csr_ren_d; // @[dec.scala 150:20]
+  assign io_dec_exu_dec_alu_dec_i0_br_immed_d = decode_io_dec_alu_dec_i0_br_immed_d; // @[dec.scala 150:20]
+  assign io_dec_exu_dec_div_div_p_valid = decode_io_dec_div_div_p_valid; // @[dec.scala 151:20]
+  assign io_dec_exu_dec_div_div_p_bits_unsign = decode_io_dec_div_div_p_bits_unsign; // @[dec.scala 151:20]
+  assign io_dec_exu_dec_div_div_p_bits_rem = decode_io_dec_div_div_p_bits_rem; // @[dec.scala 151:20]
+  assign io_dec_exu_dec_div_dec_div_cancel = decode_io_dec_div_dec_div_cancel; // @[dec.scala 151:20]
+  assign io_dec_exu_decode_exu_dec_data_en = decode_io_decode_exu_dec_data_en; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_dec_ctl_en = decode_io_decode_exu_dec_ctl_en; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_i0_ap_clz = decode_io_decode_exu_i0_ap_clz; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_i0_ap_ctz = decode_io_decode_exu_i0_ap_ctz; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_i0_ap_pcnt = decode_io_decode_exu_i0_ap_pcnt; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_i0_ap_sext_b = decode_io_decode_exu_i0_ap_sext_b; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_i0_ap_sext_h = decode_io_decode_exu_i0_ap_sext_h; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_i0_ap_slo = decode_io_decode_exu_i0_ap_slo; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_i0_ap_sro = decode_io_decode_exu_i0_ap_sro; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_i0_ap_min = decode_io_decode_exu_i0_ap_min; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_i0_ap_max = decode_io_decode_exu_i0_ap_max; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_i0_ap_pack = decode_io_decode_exu_i0_ap_pack; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_i0_ap_packu = decode_io_decode_exu_i0_ap_packu; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_i0_ap_packh = decode_io_decode_exu_i0_ap_packh; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_i0_ap_rol = decode_io_decode_exu_i0_ap_rol; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_i0_ap_ror = decode_io_decode_exu_i0_ap_ror; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_i0_ap_grev = decode_io_decode_exu_i0_ap_grev; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_i0_ap_gorc = decode_io_decode_exu_i0_ap_gorc; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_i0_ap_zbb = decode_io_decode_exu_i0_ap_zbb; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_i0_ap_sbset = decode_io_decode_exu_i0_ap_sbset; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_i0_ap_sbclr = decode_io_decode_exu_i0_ap_sbclr; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_i0_ap_sbinv = decode_io_decode_exu_i0_ap_sbinv; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_i0_ap_sbext = decode_io_decode_exu_i0_ap_sbext; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_i0_ap_sh1add = decode_io_decode_exu_i0_ap_sh1add; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_i0_ap_sh2add = decode_io_decode_exu_i0_ap_sh2add; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_i0_ap_sh3add = decode_io_decode_exu_i0_ap_sh3add; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_i0_ap_zba = decode_io_decode_exu_i0_ap_zba; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_i0_ap_land = decode_io_decode_exu_i0_ap_land; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_i0_ap_lor = decode_io_decode_exu_i0_ap_lor; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_i0_ap_lxor = decode_io_decode_exu_i0_ap_lxor; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_i0_ap_sll = decode_io_decode_exu_i0_ap_sll; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_i0_ap_srl = decode_io_decode_exu_i0_ap_srl; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_i0_ap_sra = decode_io_decode_exu_i0_ap_sra; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_i0_ap_beq = decode_io_decode_exu_i0_ap_beq; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_i0_ap_bne = decode_io_decode_exu_i0_ap_bne; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_i0_ap_blt = decode_io_decode_exu_i0_ap_blt; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_i0_ap_bge = decode_io_decode_exu_i0_ap_bge; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_i0_ap_add = decode_io_decode_exu_i0_ap_add; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_i0_ap_sub = decode_io_decode_exu_i0_ap_sub; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_i0_ap_slt = decode_io_decode_exu_i0_ap_slt; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_i0_ap_unsign = decode_io_decode_exu_i0_ap_unsign; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_i0_ap_jal = decode_io_decode_exu_i0_ap_jal; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_i0_ap_predict_t = decode_io_decode_exu_i0_ap_predict_t; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_i0_ap_predict_nt = decode_io_decode_exu_i0_ap_predict_nt; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_i0_ap_csr_write = decode_io_decode_exu_i0_ap_csr_write; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_i0_ap_csr_imm = decode_io_decode_exu_i0_ap_csr_imm; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_dec_i0_predict_p_d_valid = decode_io_decode_exu_dec_i0_predict_p_d_valid; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_misp = 1'h0; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_ataken = 1'h0; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_boffset = 1'h0; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4 = decode_io_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist = decode_io_decode_exu_dec_i0_predict_p_d_bits_hist; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset = decode_io_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error = decode_io_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error = decode_io_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall = decode_io_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja = decode_io_decode_exu_dec_i0_predict_p_d_bits_pja; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way = decode_io_decode_exu_dec_i0_predict_p_d_bits_way; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret = decode_io_decode_exu_dec_i0_predict_p_d_bits_pret; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett = decode_io_decode_exu_dec_i0_predict_p_d_bits_prett; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_i0_predict_fghr_d = decode_io_decode_exu_i0_predict_fghr_d; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_i0_predict_index_d = decode_io_decode_exu_i0_predict_index_d; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_i0_predict_btag_d = decode_io_decode_exu_i0_predict_btag_d; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_dec_i0_rs1_en_d = decode_io_decode_exu_dec_i0_rs1_en_d; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_dec_i0_branch_d = decode_io_decode_exu_dec_i0_branch_d; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_dec_i0_rs2_en_d = decode_io_decode_exu_dec_i0_rs2_en_d; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_dec_i0_immed_d = decode_io_decode_exu_dec_i0_immed_d; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_dec_i0_result_r = decode_io_decode_exu_dec_i0_result_r; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_dec_qual_lsu_d = decode_io_decode_exu_dec_qual_lsu_d; // @[dec.scala 149:23 dec.scala 205:48]
+  assign io_dec_exu_decode_exu_dec_i0_select_pc_d = decode_io_decode_exu_dec_i0_select_pc_d; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d = decode_io_decode_exu_dec_i0_rs1_bypass_en_d; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d = decode_io_decode_exu_dec_i0_rs2_bypass_en_d; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_mul_p_valid = decode_io_decode_exu_mul_p_valid; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_mul_p_bits_rs1_sign = decode_io_decode_exu_mul_p_bits_rs1_sign; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_mul_p_bits_rs2_sign = decode_io_decode_exu_mul_p_bits_rs2_sign; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_mul_p_bits_low = decode_io_decode_exu_mul_p_bits_low; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_mul_p_bits_bext = decode_io_decode_exu_mul_p_bits_bext; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_mul_p_bits_bdep = decode_io_decode_exu_mul_p_bits_bdep; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_mul_p_bits_clmul = decode_io_decode_exu_mul_p_bits_clmul; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_mul_p_bits_clmulh = decode_io_decode_exu_mul_p_bits_clmulh; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_mul_p_bits_clmulr = decode_io_decode_exu_mul_p_bits_clmulr; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_mul_p_bits_grev = decode_io_decode_exu_mul_p_bits_grev; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_mul_p_bits_gorc = decode_io_decode_exu_mul_p_bits_gorc; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_mul_p_bits_shfl = decode_io_decode_exu_mul_p_bits_shfl; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_mul_p_bits_unshfl = decode_io_decode_exu_mul_p_bits_unshfl; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_mul_p_bits_crc32_b = decode_io_decode_exu_mul_p_bits_crc32_b; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_mul_p_bits_crc32_h = decode_io_decode_exu_mul_p_bits_crc32_h; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_mul_p_bits_crc32_w = decode_io_decode_exu_mul_p_bits_crc32_w; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_mul_p_bits_crc32c_b = decode_io_decode_exu_mul_p_bits_crc32c_b; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_mul_p_bits_crc32c_h = decode_io_decode_exu_mul_p_bits_crc32c_h; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_mul_p_bits_crc32c_w = decode_io_decode_exu_mul_p_bits_crc32c_w; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_mul_p_bits_bfp = decode_io_decode_exu_mul_p_bits_bfp; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_pred_correct_npc_x = decode_io_decode_exu_pred_correct_npc_x; // @[dec.scala 149:23]
+  assign io_dec_exu_decode_exu_dec_extint_stall = decode_io_decode_exu_dec_extint_stall; // @[dec.scala 149:23]
+  assign io_dec_exu_tlu_exu_dec_tlu_meihap = tlu_io_tlu_exu_dec_tlu_meihap; // @[dec.scala 225:18]
+  assign io_dec_exu_tlu_exu_dec_tlu_flush_lower_r = tlu_io_tlu_exu_dec_tlu_flush_lower_r; // @[dec.scala 225:18]
+  assign io_dec_exu_tlu_exu_dec_tlu_flush_path_r = tlu_io_tlu_exu_dec_tlu_flush_path_r; // @[dec.scala 225:18]
+  assign io_dec_exu_ib_exu_dec_i0_pc_d = instbuff_io_ib_exu_dec_i0_pc_d; // @[dec.scala 139:22]
+  assign io_dec_exu_ib_exu_dec_debug_wdata_rs1_d = instbuff_io_ib_exu_dec_debug_wdata_rs1_d; // @[dec.scala 139:22]
+  assign io_dec_exu_gpr_exu_gpr_i0_rs1_d = gpr_io_gpr_exu_gpr_i0_rs1_d; // @[dec.scala 220:22]
+  assign io_dec_exu_gpr_exu_gpr_i0_rs2_d = gpr_io_gpr_exu_gpr_i0_rs2_d; // @[dec.scala 220:22]
+  assign io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable = tlu_io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[dec.scala 242:26]
+  assign io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable = tlu_io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[dec.scala 242:26]
+  assign io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable = tlu_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[dec.scala 242:26]
+  assign io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty = tlu_io_tlu_dma_dec_tlu_dma_qos_prty; // @[dec.scala 226:18]
+  assign io_dec_pic_dec_tlu_meicurpl = tlu_io_dec_pic_dec_tlu_meicurpl; // @[dec.scala 244:14]
+  assign io_dec_pic_dec_tlu_meipt = tlu_io_dec_pic_dec_tlu_meipt; // @[dec.scala 244:14]
+  assign instbuff_io_ifu_ib_ifu_i0_icaf = io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf; // @[dec.scala 138:22]
+  assign instbuff_io_ifu_ib_ifu_i0_icaf_type = io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type; // @[dec.scala 138:22]
+  assign instbuff_io_ifu_ib_ifu_i0_icaf_second = io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_second; // @[dec.scala 138:22]
+  assign instbuff_io_ifu_ib_ifu_i0_dbecc = io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc; // @[dec.scala 138:22]
+  assign instbuff_io_ifu_ib_ifu_i0_bp_index = io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index; // @[dec.scala 138:22]
+  assign instbuff_io_ifu_ib_ifu_i0_bp_fghr = io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[dec.scala 138:22]
+  assign instbuff_io_ifu_ib_ifu_i0_bp_btag = io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag; // @[dec.scala 138:22]
+  assign instbuff_io_ifu_ib_ifu_i0_valid = io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid; // @[dec.scala 138:22]
+  assign instbuff_io_ifu_ib_ifu_i0_instr = io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr; // @[dec.scala 138:22]
+  assign instbuff_io_ifu_ib_ifu_i0_pc = io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc; // @[dec.scala 138:22]
+  assign instbuff_io_ifu_ib_ifu_i0_pc4 = io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4; // @[dec.scala 138:22]
+  assign instbuff_io_ifu_ib_i0_brp_valid = io_ifu_dec_dec_aln_aln_ib_i0_brp_valid; // @[dec.scala 138:22]
+  assign instbuff_io_ifu_ib_i0_brp_bits_toffset = io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset; // @[dec.scala 138:22]
+  assign instbuff_io_ifu_ib_i0_brp_bits_hist = io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist; // @[dec.scala 138:22]
+  assign instbuff_io_ifu_ib_i0_brp_bits_br_error = io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error; // @[dec.scala 138:22]
+  assign instbuff_io_ifu_ib_i0_brp_bits_br_start_error = io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[dec.scala 138:22]
+  assign instbuff_io_ifu_ib_i0_brp_bits_prett = io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett; // @[dec.scala 138:22]
+  assign instbuff_io_ifu_ib_i0_brp_bits_way = io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way; // @[dec.scala 138:22]
+  assign instbuff_io_ifu_ib_i0_brp_bits_ret = io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret; // @[dec.scala 138:22]
+  assign instbuff_io_dbg_ib_dbg_cmd_valid = io_dec_dbg_dbg_ib_dbg_cmd_valid; // @[dec.scala 140:22]
+  assign instbuff_io_dbg_ib_dbg_cmd_write = io_dec_dbg_dbg_ib_dbg_cmd_write; // @[dec.scala 140:22]
+  assign instbuff_io_dbg_ib_dbg_cmd_type = io_dec_dbg_dbg_ib_dbg_cmd_type; // @[dec.scala 140:22]
+  assign instbuff_io_dbg_ib_dbg_cmd_addr = io_dec_dbg_dbg_ib_dbg_cmd_addr; // @[dec.scala 140:22]
   assign decode_clock = clock;
   assign decode_reset = reset;
-  assign decode_io_decode_exu_exu_i0_result_x = io_dec_exu_decode_exu_exu_i0_result_x; // @[dec.scala 147:23]
-  assign decode_io_decode_exu_exu_csr_rs1_x = io_dec_exu_decode_exu_exu_csr_rs1_x; // @[dec.scala 147:23]
-  assign decode_io_dec_alu_exu_i0_pc_x = io_dec_exu_dec_alu_exu_i0_pc_x; // @[dec.scala 148:20]
-  assign decode_io_dctl_busbuff_lsu_nonblock_load_valid_m = io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m; // @[dec.scala 155:26]
-  assign decode_io_dctl_busbuff_lsu_nonblock_load_tag_m = io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m; // @[dec.scala 155:26]
-  assign decode_io_dctl_busbuff_lsu_nonblock_load_inv_r = io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r; // @[dec.scala 155:26]
-  assign decode_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r = io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[dec.scala 155:26]
-  assign decode_io_dctl_busbuff_lsu_nonblock_load_data_valid = io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid; // @[dec.scala 155:26]
-  assign decode_io_dctl_busbuff_lsu_nonblock_load_data_error = io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error; // @[dec.scala 155:26]
-  assign decode_io_dctl_busbuff_lsu_nonblock_load_data_tag = io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag; // @[dec.scala 155:26]
-  assign decode_io_dctl_dma_dma_dccm_stall_any = io_dec_dma_dctl_dma_dma_dccm_stall_any; // @[dec.scala 150:22]
-  assign decode_io_dec_aln_ifu_i0_cinst = io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst; // @[dec.scala 145:21]
-  assign decode_io_dbg_dctl_dbg_cmd_wrdata = io_dec_dbg_dbg_dctl_dbg_cmd_wrdata; // @[dec.scala 165:22]
-  assign decode_io_dec_tlu_trace_disable = tlu_io_dec_tlu_trace_disable; // @[dec.scala 151:48]
-  assign decode_io_dec_debug_valid_d = instbuff_io_dec_debug_fence_d; // @[dec.scala 152:48]
-  assign decode_io_dec_tlu_flush_extint = tlu_io_dec_tlu_flush_extint; // @[dec.scala 153:48]
-  assign decode_io_dec_tlu_force_halt = tlu_io_tlu_mem_dec_tlu_force_halt; // @[dec.scala 154:48]
-  assign decode_io_dec_i0_trigger_match_d = dec_trigger_io_dec_i0_trigger_match_d; // @[dec.scala 156:48]
-  assign decode_io_dec_tlu_wr_pause_r = tlu_io_dec_tlu_wr_pause_r; // @[dec.scala 157:48]
-  assign decode_io_dec_tlu_pipelining_disable = tlu_io_dec_tlu_pipelining_disable; // @[dec.scala 158:48]
-  assign decode_io_lsu_trigger_match_m = io_lsu_trigger_match_m; // @[dec.scala 159:48]
-  assign decode_io_lsu_pmu_misaligned_m = io_lsu_pmu_misaligned_m; // @[dec.scala 160:48]
-  assign decode_io_dec_tlu_debug_stall = tlu_io_dec_tlu_debug_stall; // @[dec.scala 161:48]
-  assign decode_io_dec_tlu_flush_leak_one_r = tlu_io_tlu_bp_dec_tlu_flush_leak_one_wb; // @[dec.scala 163:48]
-  assign decode_io_dec_debug_fence_d = instbuff_io_dec_debug_fence_d; // @[dec.scala 164:48]
-  assign decode_io_dec_i0_icaf_d = instbuff_io_dec_i0_icaf_d; // @[dec.scala 166:48]
-  assign decode_io_dec_i0_icaf_second_d = instbuff_io_dec_i0_icaf_second_d; // @[dec.scala 167:48]
-  assign decode_io_dec_i0_icaf_type_d = instbuff_io_dec_i0_icaf_type_d; // @[dec.scala 168:48]
-  assign decode_io_dec_i0_dbecc_d = instbuff_io_dec_i0_dbecc_d; // @[dec.scala 169:48]
-  assign decode_io_dec_i0_brp_valid = instbuff_io_dec_i0_brp_valid; // @[dec.scala 170:48]
-  assign decode_io_dec_i0_brp_bits_toffset = instbuff_io_dec_i0_brp_bits_toffset; // @[dec.scala 170:48]
-  assign decode_io_dec_i0_brp_bits_hist = instbuff_io_dec_i0_brp_bits_hist; // @[dec.scala 170:48]
-  assign decode_io_dec_i0_brp_bits_br_error = instbuff_io_dec_i0_brp_bits_br_error; // @[dec.scala 170:48]
-  assign decode_io_dec_i0_brp_bits_br_start_error = instbuff_io_dec_i0_brp_bits_br_start_error; // @[dec.scala 170:48]
-  assign decode_io_dec_i0_brp_bits_prett = instbuff_io_dec_i0_brp_bits_prett; // @[dec.scala 170:48]
-  assign decode_io_dec_i0_brp_bits_way = instbuff_io_dec_i0_brp_bits_way; // @[dec.scala 170:48]
-  assign decode_io_dec_i0_brp_bits_ret = instbuff_io_dec_i0_brp_bits_ret; // @[dec.scala 170:48]
-  assign decode_io_dec_i0_bp_index = instbuff_io_dec_i0_bp_index; // @[dec.scala 171:48]
-  assign decode_io_dec_i0_bp_fghr = instbuff_io_dec_i0_bp_fghr; // @[dec.scala 172:48]
-  assign decode_io_dec_i0_bp_btag = instbuff_io_dec_i0_bp_btag; // @[dec.scala 173:48]
-  assign decode_io_lsu_idle_any = io_lsu_idle_any; // @[dec.scala 174:48]
-  assign decode_io_lsu_load_stall_any = io_lsu_load_stall_any; // @[dec.scala 175:48]
-  assign decode_io_lsu_store_stall_any = io_lsu_store_stall_any; // @[dec.scala 176:48]
-  assign decode_io_exu_div_wren = io_exu_div_wren; // @[dec.scala 177:48]
-  assign decode_io_dec_tlu_i0_kill_writeb_wb = tlu_io_dec_tlu_i0_kill_writeb_wb; // @[dec.scala 178:48]
-  assign decode_io_dec_tlu_flush_lower_wb = tlu_io_dec_tlu_flush_lower_wb; // @[dec.scala 179:48]
-  assign decode_io_dec_tlu_i0_kill_writeb_r = tlu_io_dec_tlu_i0_kill_writeb_r; // @[dec.scala 180:48]
-  assign decode_io_dec_tlu_flush_lower_r = tlu_io_tlu_exu_dec_tlu_flush_lower_r; // @[dec.scala 181:48]
-  assign decode_io_dec_tlu_flush_pause_r = tlu_io_dec_tlu_flush_pause_r; // @[dec.scala 182:48]
-  assign decode_io_dec_tlu_presync_d = tlu_io_dec_tlu_presync_d; // @[dec.scala 183:48]
-  assign decode_io_dec_tlu_postsync_d = tlu_io_dec_tlu_postsync_d; // @[dec.scala 184:48]
-  assign decode_io_dec_i0_pc4_d = instbuff_io_dec_i0_pc4_d; // @[dec.scala 185:48]
-  assign decode_io_dec_csr_rddata_d = tlu_io_dec_csr_rddata_d; // @[dec.scala 186:48]
-  assign decode_io_dec_csr_legal_d = tlu_io_dec_csr_legal_d; // @[dec.scala 187:48]
-  assign decode_io_lsu_result_m = io_lsu_result_m; // @[dec.scala 188:48]
-  assign decode_io_lsu_result_corr_r = io_lsu_result_corr_r; // @[dec.scala 189:48]
-  assign decode_io_exu_flush_final = io_exu_flush_final; // @[dec.scala 190:48]
-  assign decode_io_dec_i0_instr_d = instbuff_io_dec_i0_instr_d; // @[dec.scala 191:48]
-  assign decode_io_dec_ib0_valid_d = instbuff_io_dec_ib0_valid_d; // @[dec.scala 192:48]
-  assign decode_io_active_clk = io_active_clk; // @[dec.scala 194:48]
-  assign decode_io_free_l2clk = io_free_l2clk; // @[dec.scala 193:48]
-  assign decode_io_clk_override = tlu_io_dec_tlu_dec_clk_override; // @[dec.scala 195:48]
+  assign decode_io_decode_exu_exu_i0_result_x = io_dec_exu_decode_exu_exu_i0_result_x; // @[dec.scala 149:23]
+  assign decode_io_decode_exu_exu_csr_rs1_x = io_dec_exu_decode_exu_exu_csr_rs1_x; // @[dec.scala 149:23]
+  assign decode_io_dec_alu_exu_i0_pc_x = io_dec_exu_dec_alu_exu_i0_pc_x; // @[dec.scala 150:20]
+  assign decode_io_dctl_busbuff_lsu_nonblock_load_valid_m = io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m; // @[dec.scala 157:26]
+  assign decode_io_dctl_busbuff_lsu_nonblock_load_tag_m = io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m; // @[dec.scala 157:26]
+  assign decode_io_dctl_busbuff_lsu_nonblock_load_inv_r = io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r; // @[dec.scala 157:26]
+  assign decode_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r = io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[dec.scala 157:26]
+  assign decode_io_dctl_busbuff_lsu_nonblock_load_data_valid = io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid; // @[dec.scala 157:26]
+  assign decode_io_dctl_busbuff_lsu_nonblock_load_data_error = io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error; // @[dec.scala 157:26]
+  assign decode_io_dctl_busbuff_lsu_nonblock_load_data_tag = io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag; // @[dec.scala 157:26]
+  assign decode_io_dctl_dma_dma_dccm_stall_any = io_dec_dma_dctl_dma_dma_dccm_stall_any; // @[dec.scala 152:22]
+  assign decode_io_dec_aln_ifu_i0_cinst = io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst; // @[dec.scala 147:21]
+  assign decode_io_dbg_dctl_dbg_cmd_wrdata = io_dec_dbg_dbg_dctl_dbg_cmd_wrdata; // @[dec.scala 167:22]
+  assign decode_io_dec_tlu_trace_disable = tlu_io_dec_tlu_trace_disable; // @[dec.scala 153:48]
+  assign decode_io_dec_debug_valid_d = instbuff_io_dec_debug_fence_d; // @[dec.scala 154:48]
+  assign decode_io_dec_tlu_flush_extint = tlu_io_dec_tlu_flush_extint; // @[dec.scala 155:48]
+  assign decode_io_dec_tlu_force_halt = tlu_io_tlu_mem_dec_tlu_force_halt; // @[dec.scala 156:48]
+  assign decode_io_dec_i0_trigger_match_d = dec_trigger_io_dec_i0_trigger_match_d; // @[dec.scala 158:48]
+  assign decode_io_dec_tlu_wr_pause_r = tlu_io_dec_tlu_wr_pause_r; // @[dec.scala 159:48]
+  assign decode_io_dec_tlu_pipelining_disable = tlu_io_dec_tlu_pipelining_disable; // @[dec.scala 160:48]
+  assign decode_io_lsu_trigger_match_m = io_lsu_trigger_match_m; // @[dec.scala 161:48]
+  assign decode_io_lsu_pmu_misaligned_m = io_lsu_pmu_misaligned_m; // @[dec.scala 162:48]
+  assign decode_io_dec_tlu_debug_stall = tlu_io_dec_tlu_debug_stall; // @[dec.scala 163:48]
+  assign decode_io_dec_tlu_flush_leak_one_r = tlu_io_tlu_bp_dec_tlu_flush_leak_one_wb; // @[dec.scala 165:48]
+  assign decode_io_dec_debug_fence_d = instbuff_io_dec_debug_fence_d; // @[dec.scala 166:48]
+  assign decode_io_dec_i0_icaf_d = instbuff_io_dec_i0_icaf_d; // @[dec.scala 168:48]
+  assign decode_io_dec_i0_icaf_second_d = instbuff_io_dec_i0_icaf_second_d; // @[dec.scala 169:48]
+  assign decode_io_dec_i0_icaf_type_d = instbuff_io_dec_i0_icaf_type_d; // @[dec.scala 170:48]
+  assign decode_io_dec_i0_dbecc_d = instbuff_io_dec_i0_dbecc_d; // @[dec.scala 171:48]
+  assign decode_io_dec_i0_brp_valid = instbuff_io_dec_i0_brp_valid; // @[dec.scala 172:48]
+  assign decode_io_dec_i0_brp_bits_toffset = instbuff_io_dec_i0_brp_bits_toffset; // @[dec.scala 172:48]
+  assign decode_io_dec_i0_brp_bits_hist = instbuff_io_dec_i0_brp_bits_hist; // @[dec.scala 172:48]
+  assign decode_io_dec_i0_brp_bits_br_error = instbuff_io_dec_i0_brp_bits_br_error; // @[dec.scala 172:48]
+  assign decode_io_dec_i0_brp_bits_br_start_error = instbuff_io_dec_i0_brp_bits_br_start_error; // @[dec.scala 172:48]
+  assign decode_io_dec_i0_brp_bits_prett = instbuff_io_dec_i0_brp_bits_prett; // @[dec.scala 172:48]
+  assign decode_io_dec_i0_brp_bits_way = instbuff_io_dec_i0_brp_bits_way; // @[dec.scala 172:48]
+  assign decode_io_dec_i0_brp_bits_ret = instbuff_io_dec_i0_brp_bits_ret; // @[dec.scala 172:48]
+  assign decode_io_dec_i0_bp_index = instbuff_io_dec_i0_bp_index; // @[dec.scala 173:48]
+  assign decode_io_dec_i0_bp_fghr = instbuff_io_dec_i0_bp_fghr; // @[dec.scala 174:48]
+  assign decode_io_dec_i0_bp_btag = instbuff_io_dec_i0_bp_btag; // @[dec.scala 175:48]
+  assign decode_io_lsu_idle_any = io_lsu_idle_any; // @[dec.scala 176:48]
+  assign decode_io_lsu_load_stall_any = io_lsu_load_stall_any; // @[dec.scala 177:48]
+  assign decode_io_lsu_store_stall_any = io_lsu_store_stall_any; // @[dec.scala 178:48]
+  assign decode_io_exu_div_wren = io_exu_div_wren; // @[dec.scala 179:48]
+  assign decode_io_dec_tlu_i0_kill_writeb_wb = tlu_io_dec_tlu_i0_kill_writeb_wb; // @[dec.scala 180:48]
+  assign decode_io_dec_tlu_flush_lower_wb = tlu_io_dec_tlu_flush_lower_wb; // @[dec.scala 181:48]
+  assign decode_io_dec_tlu_i0_kill_writeb_r = tlu_io_dec_tlu_i0_kill_writeb_r; // @[dec.scala 182:48]
+  assign decode_io_dec_tlu_flush_lower_r = tlu_io_tlu_exu_dec_tlu_flush_lower_r; // @[dec.scala 183:48]
+  assign decode_io_dec_tlu_flush_pause_r = tlu_io_dec_tlu_flush_pause_r; // @[dec.scala 184:48]
+  assign decode_io_dec_tlu_presync_d = tlu_io_dec_tlu_presync_d; // @[dec.scala 185:48]
+  assign decode_io_dec_tlu_postsync_d = tlu_io_dec_tlu_postsync_d; // @[dec.scala 186:48]
+  assign decode_io_dec_i0_pc4_d = instbuff_io_dec_i0_pc4_d; // @[dec.scala 187:48]
+  assign decode_io_dec_csr_rddata_d = tlu_io_dec_csr_rddata_d; // @[dec.scala 188:48]
+  assign decode_io_dec_csr_legal_d = tlu_io_dec_csr_legal_d; // @[dec.scala 189:48]
+  assign decode_io_lsu_result_m = io_lsu_result_m; // @[dec.scala 190:48]
+  assign decode_io_lsu_result_corr_r = io_lsu_result_corr_r; // @[dec.scala 191:48]
+  assign decode_io_exu_flush_final = io_exu_flush_final; // @[dec.scala 192:48]
+  assign decode_io_dec_i0_instr_d = instbuff_io_dec_i0_instr_d; // @[dec.scala 193:48]
+  assign decode_io_dec_ib0_valid_d = instbuff_io_dec_ib0_valid_d; // @[dec.scala 194:48]
+  assign decode_io_active_clk = io_active_clk; // @[dec.scala 196:48]
+  assign decode_io_free_l2clk = io_free_l2clk; // @[dec.scala 195:48]
+  assign decode_io_clk_override = tlu_io_dec_tlu_dec_clk_override; // @[dec.scala 197:48]
   assign gpr_clock = clock;
   assign gpr_reset = reset;
-  assign gpr_io_raddr0 = decode_io_dec_i0_rs1_d; // @[dec.scala 206:23]
-  assign gpr_io_raddr1 = decode_io_dec_i0_rs2_d; // @[dec.scala 207:23]
-  assign gpr_io_wen0 = decode_io_dec_i0_wen_r; // @[dec.scala 208:23]
-  assign gpr_io_waddr0 = decode_io_dec_i0_waddr_r; // @[dec.scala 209:23]
-  assign gpr_io_wd0 = decode_io_dec_i0_wdata_r; // @[dec.scala 210:23]
-  assign gpr_io_wen1 = decode_io_dec_nonblock_load_wen; // @[dec.scala 211:23]
-  assign gpr_io_waddr1 = decode_io_dec_nonblock_load_waddr; // @[dec.scala 212:23]
-  assign gpr_io_wd1 = io_lsu_nonblock_load_data; // @[dec.scala 213:23]
-  assign gpr_io_wen2 = io_exu_div_wren; // @[dec.scala 214:23]
-  assign gpr_io_waddr2 = decode_io_div_waddr_wb; // @[dec.scala 215:23]
-  assign gpr_io_wd2 = io_exu_div_result; // @[dec.scala 216:23]
+  assign gpr_io_raddr0 = decode_io_dec_i0_rs1_d; // @[dec.scala 208:23]
+  assign gpr_io_raddr1 = decode_io_dec_i0_rs2_d; // @[dec.scala 209:23]
+  assign gpr_io_wen0 = decode_io_dec_i0_wen_r; // @[dec.scala 210:23]
+  assign gpr_io_waddr0 = decode_io_dec_i0_waddr_r; // @[dec.scala 211:23]
+  assign gpr_io_wd0 = decode_io_dec_i0_wdata_r; // @[dec.scala 212:23]
+  assign gpr_io_wen1 = decode_io_dec_nonblock_load_wen; // @[dec.scala 213:23]
+  assign gpr_io_waddr1 = decode_io_dec_nonblock_load_waddr; // @[dec.scala 214:23]
+  assign gpr_io_wd1 = io_lsu_nonblock_load_data; // @[dec.scala 215:23]
+  assign gpr_io_wen2 = io_exu_div_wren; // @[dec.scala 216:23]
+  assign gpr_io_waddr2 = decode_io_div_waddr_wb; // @[dec.scala 217:23]
+  assign gpr_io_wd2 = io_exu_div_result; // @[dec.scala 218:23]
   assign tlu_clock = clock;
   assign tlu_reset = reset;
-  assign tlu_io_tlu_exu_exu_i0_br_hist_r = io_dec_exu_tlu_exu_exu_i0_br_hist_r; // @[dec.scala 223:18]
-  assign tlu_io_tlu_exu_exu_i0_br_error_r = io_dec_exu_tlu_exu_exu_i0_br_error_r; // @[dec.scala 223:18]
-  assign tlu_io_tlu_exu_exu_i0_br_start_error_r = io_dec_exu_tlu_exu_exu_i0_br_start_error_r; // @[dec.scala 223:18]
-  assign tlu_io_tlu_exu_exu_i0_br_valid_r = io_dec_exu_tlu_exu_exu_i0_br_valid_r; // @[dec.scala 223:18]
-  assign tlu_io_tlu_exu_exu_i0_br_mp_r = io_dec_exu_tlu_exu_exu_i0_br_mp_r; // @[dec.scala 223:18]
-  assign tlu_io_tlu_exu_exu_i0_br_middle_r = io_dec_exu_tlu_exu_exu_i0_br_middle_r; // @[dec.scala 223:18]
-  assign tlu_io_tlu_exu_exu_pmu_i0_br_misp = io_dec_exu_tlu_exu_exu_pmu_i0_br_misp; // @[dec.scala 223:18]
-  assign tlu_io_tlu_exu_exu_pmu_i0_br_ataken = io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken; // @[dec.scala 223:18]
-  assign tlu_io_tlu_exu_exu_pmu_i0_pc4 = io_dec_exu_tlu_exu_exu_pmu_i0_pc4; // @[dec.scala 223:18]
-  assign tlu_io_tlu_exu_exu_npc_r = io_dec_exu_tlu_exu_exu_npc_r; // @[dec.scala 223:18]
-  assign tlu_io_tlu_dma_dma_pmu_dccm_read = io_dec_dma_tlu_dma_dma_pmu_dccm_read; // @[dec.scala 224:18]
-  assign tlu_io_tlu_dma_dma_pmu_dccm_write = io_dec_dma_tlu_dma_dma_pmu_dccm_write; // @[dec.scala 224:18]
-  assign tlu_io_tlu_dma_dma_pmu_any_read = io_dec_dma_tlu_dma_dma_pmu_any_read; // @[dec.scala 224:18]
-  assign tlu_io_tlu_dma_dma_pmu_any_write = io_dec_dma_tlu_dma_dma_pmu_any_write; // @[dec.scala 224:18]
-  assign tlu_io_tlu_dma_dma_dccm_stall_any = io_dec_dma_tlu_dma_dma_dccm_stall_any; // @[dec.scala 224:18]
-  assign tlu_io_tlu_dma_dma_iccm_stall_any = io_dec_dma_tlu_dma_dma_iccm_stall_any; // @[dec.scala 224:18]
-  assign tlu_io_free_clk = io_free_clk; // @[dec.scala 226:45]
-  assign tlu_io_free_l2clk = io_free_l2clk; // @[dec.scala 225:45]
-  assign tlu_io_rst_vec = io_rst_vec; // @[dec.scala 228:45]
-  assign tlu_io_nmi_int = io_nmi_int; // @[dec.scala 229:45]
-  assign tlu_io_nmi_vec = io_nmi_vec; // @[dec.scala 230:45]
-  assign tlu_io_i_cpu_halt_req = io_i_cpu_halt_req; // @[dec.scala 231:45]
-  assign tlu_io_i_cpu_run_req = io_i_cpu_run_req; // @[dec.scala 232:45]
-  assign tlu_io_lsu_fastint_stall_any = io_lsu_fastint_stall_any; // @[dec.scala 233:45]
-  assign tlu_io_lsu_idle_any = io_lsu_idle_any; // @[dec.scala 264:45]
-  assign tlu_io_dec_pmu_instr_decoded = decode_io_dec_pmu_instr_decoded; // @[dec.scala 235:45]
-  assign tlu_io_dec_pmu_decode_stall = decode_io_dec_pmu_decode_stall; // @[dec.scala 236:45]
-  assign tlu_io_dec_pmu_presync_stall = decode_io_dec_pmu_presync_stall; // @[dec.scala 237:45]
-  assign tlu_io_dec_pmu_postsync_stall = decode_io_dec_pmu_postsync_stall; // @[dec.scala 238:45]
-  assign tlu_io_lsu_store_stall_any = io_lsu_store_stall_any; // @[dec.scala 239:45]
-  assign tlu_io_lsu_fir_addr = io_lsu_fir_addr; // @[dec.scala 243:45]
-  assign tlu_io_lsu_fir_error = io_lsu_fir_error; // @[dec.scala 244:45]
-  assign tlu_io_iccm_dma_sb_error = io_iccm_dma_sb_error; // @[dec.scala 245:45]
-  assign tlu_io_lsu_error_pkt_r_valid = io_lsu_error_pkt_r_valid; // @[dec.scala 246:45]
-  assign tlu_io_lsu_error_pkt_r_bits_single_ecc_error = io_lsu_error_pkt_r_bits_single_ecc_error; // @[dec.scala 246:45]
-  assign tlu_io_lsu_error_pkt_r_bits_inst_type = io_lsu_error_pkt_r_bits_inst_type; // @[dec.scala 246:45]
-  assign tlu_io_lsu_error_pkt_r_bits_exc_type = io_lsu_error_pkt_r_bits_exc_type; // @[dec.scala 246:45]
-  assign tlu_io_lsu_error_pkt_r_bits_mscause = io_lsu_error_pkt_r_bits_mscause; // @[dec.scala 246:45]
-  assign tlu_io_lsu_error_pkt_r_bits_addr = io_lsu_error_pkt_r_bits_addr; // @[dec.scala 246:45]
-  assign tlu_io_lsu_single_ecc_error_incr = io_lsu_single_ecc_error_incr; // @[dec.scala 247:45]
-  assign tlu_io_dec_pause_state = decode_io_dec_pause_state; // @[dec.scala 248:45]
-  assign tlu_io_dec_csr_wen_unq_d = decode_io_dec_csr_wen_unq_d; // @[dec.scala 249:45]
-  assign tlu_io_dec_csr_any_unq_d = decode_io_dec_csr_any_unq_d; // @[dec.scala 250:45]
-  assign tlu_io_dec_csr_rdaddr_d = decode_io_dec_csr_rdaddr_d; // @[dec.scala 251:45]
-  assign tlu_io_dec_csr_wen_r = decode_io_dec_csr_wen_r; // @[dec.scala 252:45]
-  assign tlu_io_dec_csr_wraddr_r = decode_io_dec_csr_wraddr_r; // @[dec.scala 253:45]
-  assign tlu_io_dec_csr_wrdata_r = decode_io_dec_csr_wrdata_r; // @[dec.scala 254:45]
-  assign tlu_io_dec_csr_stall_int_ff = decode_io_dec_csr_stall_int_ff; // @[dec.scala 255:45]
-  assign tlu_io_dec_tlu_i0_valid_r = decode_io_dec_tlu_i0_valid_r; // @[dec.scala 256:45]
-  assign tlu_io_dec_tlu_i0_pc_r = decode_io_dec_tlu_i0_pc_r; // @[dec.scala 257:45]
-  assign tlu_io_dec_tlu_packet_r_legal = decode_io_dec_tlu_packet_r_legal; // @[dec.scala 258:45]
-  assign tlu_io_dec_tlu_packet_r_icaf = decode_io_dec_tlu_packet_r_icaf; // @[dec.scala 258:45]
-  assign tlu_io_dec_tlu_packet_r_icaf_second = decode_io_dec_tlu_packet_r_icaf_second; // @[dec.scala 258:45]
-  assign tlu_io_dec_tlu_packet_r_icaf_type = decode_io_dec_tlu_packet_r_icaf_type; // @[dec.scala 258:45]
-  assign tlu_io_dec_tlu_packet_r_fence_i = decode_io_dec_tlu_packet_r_fence_i; // @[dec.scala 258:45]
-  assign tlu_io_dec_tlu_packet_r_i0trigger = decode_io_dec_tlu_packet_r_i0trigger; // @[dec.scala 258:45]
-  assign tlu_io_dec_tlu_packet_r_pmu_i0_itype = decode_io_dec_tlu_packet_r_pmu_i0_itype; // @[dec.scala 258:45]
-  assign tlu_io_dec_tlu_packet_r_pmu_i0_br_unpred = decode_io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[dec.scala 258:45]
-  assign tlu_io_dec_tlu_packet_r_pmu_divide = decode_io_dec_tlu_packet_r_pmu_divide; // @[dec.scala 258:45]
-  assign tlu_io_dec_tlu_packet_r_pmu_lsu_misaligned = decode_io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec.scala 258:45]
-  assign tlu_io_dec_illegal_inst = decode_io_dec_illegal_inst; // @[dec.scala 259:45]
-  assign tlu_io_dec_i0_decode_d = decode_io_dec_aln_dec_i0_decode_d; // @[dec.scala 260:45]
-  assign tlu_io_exu_i0_br_way_r = io_exu_i0_br_way_r; // @[dec.scala 261:45]
-  assign tlu_io_dbg_halt_req = io_dbg_halt_req; // @[dec.scala 262:45]
-  assign tlu_io_dbg_resume_req = io_dbg_resume_req; // @[dec.scala 263:45]
-  assign tlu_io_dec_div_active = decode_io_dec_div_active; // @[dec.scala 265:45]
-  assign tlu_io_timer_int = io_timer_int; // @[dec.scala 266:45]
-  assign tlu_io_soft_int = io_soft_int; // @[dec.scala 267:45]
-  assign tlu_io_core_id = io_core_id; // @[dec.scala 268:45]
-  assign tlu_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[dec.scala 269:45]
-  assign tlu_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[dec.scala 270:45]
-  assign tlu_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[dec.scala 271:45]
-  assign tlu_io_ifu_pmu_instr_aligned = io_ifu_dec_dec_aln_ifu_pmu_instr_aligned; // @[dec.scala 234:45]
-  assign tlu_io_tlu_ifc_ifu_pmu_fetch_stall = io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall; // @[dec.scala 221:18]
-  assign tlu_io_tlu_mem_ifu_pmu_ic_miss = io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss; // @[dec.scala 220:18]
-  assign tlu_io_tlu_mem_ifu_pmu_ic_hit = io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[dec.scala 220:18]
-  assign tlu_io_tlu_mem_ifu_pmu_bus_error = io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[dec.scala 220:18]
-  assign tlu_io_tlu_mem_ifu_pmu_bus_busy = io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[dec.scala 220:18]
-  assign tlu_io_tlu_mem_ifu_pmu_bus_trxn = io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[dec.scala 220:18]
-  assign tlu_io_tlu_mem_ifu_ic_error_start = io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[dec.scala 220:18]
-  assign tlu_io_tlu_mem_ifu_iccm_rd_ecc_single_err = io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[dec.scala 220:18]
-  assign tlu_io_tlu_mem_ifu_ic_debug_rd_data = io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[dec.scala 220:18]
-  assign tlu_io_tlu_mem_ifu_ic_debug_rd_data_valid = io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[dec.scala 220:18]
-  assign tlu_io_tlu_mem_ifu_miss_state_idle = io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle; // @[dec.scala 220:18]
-  assign tlu_io_tlu_busbuff_lsu_pmu_bus_trxn = io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[dec.scala 240:26]
-  assign tlu_io_tlu_busbuff_lsu_pmu_bus_misaligned = io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[dec.scala 240:26]
-  assign tlu_io_tlu_busbuff_lsu_pmu_bus_error = io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[dec.scala 240:26]
-  assign tlu_io_tlu_busbuff_lsu_pmu_bus_busy = io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[dec.scala 240:26]
-  assign tlu_io_tlu_busbuff_lsu_imprecise_error_load_any = io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[dec.scala 240:26]
-  assign tlu_io_tlu_busbuff_lsu_imprecise_error_store_any = io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[dec.scala 240:26]
-  assign tlu_io_tlu_busbuff_lsu_imprecise_error_addr_any = io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any; // @[dec.scala 240:26]
-  assign tlu_io_lsu_tlu_lsu_pmu_load_external_m = io_lsu_tlu_lsu_pmu_load_external_m; // @[dec.scala 241:14]
-  assign tlu_io_lsu_tlu_lsu_pmu_store_external_m = io_lsu_tlu_lsu_pmu_store_external_m; // @[dec.scala 241:14]
-  assign tlu_io_dec_pic_pic_claimid = io_dec_pic_pic_claimid; // @[dec.scala 242:14]
-  assign tlu_io_dec_pic_pic_pl = io_dec_pic_pic_pl; // @[dec.scala 242:14]
-  assign tlu_io_dec_pic_mhwakeup = io_dec_pic_mhwakeup; // @[dec.scala 242:14]
-  assign tlu_io_dec_pic_mexintpend = io_dec_pic_mexintpend; // @[dec.scala 242:14]
-  assign dec_trigger_io_trigger_pkt_any_0_select = tlu_io_trigger_pkt_any_0_select; // @[dec.scala 141:34]
-  assign dec_trigger_io_trigger_pkt_any_0_match_pkt = tlu_io_trigger_pkt_any_0_match_pkt; // @[dec.scala 141:34]
-  assign dec_trigger_io_trigger_pkt_any_0_execute = tlu_io_trigger_pkt_any_0_execute; // @[dec.scala 141:34]
-  assign dec_trigger_io_trigger_pkt_any_0_m = tlu_io_trigger_pkt_any_0_m; // @[dec.scala 141:34]
-  assign dec_trigger_io_trigger_pkt_any_0_tdata2 = tlu_io_trigger_pkt_any_0_tdata2; // @[dec.scala 141:34]
-  assign dec_trigger_io_trigger_pkt_any_1_select = tlu_io_trigger_pkt_any_1_select; // @[dec.scala 141:34]
-  assign dec_trigger_io_trigger_pkt_any_1_match_pkt = tlu_io_trigger_pkt_any_1_match_pkt; // @[dec.scala 141:34]
-  assign dec_trigger_io_trigger_pkt_any_1_execute = tlu_io_trigger_pkt_any_1_execute; // @[dec.scala 141:34]
-  assign dec_trigger_io_trigger_pkt_any_1_m = tlu_io_trigger_pkt_any_1_m; // @[dec.scala 141:34]
-  assign dec_trigger_io_trigger_pkt_any_1_tdata2 = tlu_io_trigger_pkt_any_1_tdata2; // @[dec.scala 141:34]
-  assign dec_trigger_io_trigger_pkt_any_2_select = tlu_io_trigger_pkt_any_2_select; // @[dec.scala 141:34]
-  assign dec_trigger_io_trigger_pkt_any_2_match_pkt = tlu_io_trigger_pkt_any_2_match_pkt; // @[dec.scala 141:34]
-  assign dec_trigger_io_trigger_pkt_any_2_execute = tlu_io_trigger_pkt_any_2_execute; // @[dec.scala 141:34]
-  assign dec_trigger_io_trigger_pkt_any_2_m = tlu_io_trigger_pkt_any_2_m; // @[dec.scala 141:34]
-  assign dec_trigger_io_trigger_pkt_any_2_tdata2 = tlu_io_trigger_pkt_any_2_tdata2; // @[dec.scala 141:34]
-  assign dec_trigger_io_trigger_pkt_any_3_select = tlu_io_trigger_pkt_any_3_select; // @[dec.scala 141:34]
-  assign dec_trigger_io_trigger_pkt_any_3_match_pkt = tlu_io_trigger_pkt_any_3_match_pkt; // @[dec.scala 141:34]
-  assign dec_trigger_io_trigger_pkt_any_3_execute = tlu_io_trigger_pkt_any_3_execute; // @[dec.scala 141:34]
-  assign dec_trigger_io_trigger_pkt_any_3_m = tlu_io_trigger_pkt_any_3_m; // @[dec.scala 141:34]
-  assign dec_trigger_io_trigger_pkt_any_3_tdata2 = tlu_io_trigger_pkt_any_3_tdata2; // @[dec.scala 141:34]
-  assign dec_trigger_io_dec_i0_pc_d = instbuff_io_ib_exu_dec_i0_pc_d; // @[dec.scala 140:30]
+  assign tlu_io_tlu_exu_exu_i0_br_hist_r = io_dec_exu_tlu_exu_exu_i0_br_hist_r; // @[dec.scala 225:18]
+  assign tlu_io_tlu_exu_exu_i0_br_error_r = io_dec_exu_tlu_exu_exu_i0_br_error_r; // @[dec.scala 225:18]
+  assign tlu_io_tlu_exu_exu_i0_br_start_error_r = io_dec_exu_tlu_exu_exu_i0_br_start_error_r; // @[dec.scala 225:18]
+  assign tlu_io_tlu_exu_exu_i0_br_valid_r = io_dec_exu_tlu_exu_exu_i0_br_valid_r; // @[dec.scala 225:18]
+  assign tlu_io_tlu_exu_exu_i0_br_mp_r = io_dec_exu_tlu_exu_exu_i0_br_mp_r; // @[dec.scala 225:18]
+  assign tlu_io_tlu_exu_exu_i0_br_middle_r = io_dec_exu_tlu_exu_exu_i0_br_middle_r; // @[dec.scala 225:18]
+  assign tlu_io_tlu_exu_exu_pmu_i0_br_misp = io_dec_exu_tlu_exu_exu_pmu_i0_br_misp; // @[dec.scala 225:18]
+  assign tlu_io_tlu_exu_exu_pmu_i0_br_ataken = io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken; // @[dec.scala 225:18]
+  assign tlu_io_tlu_exu_exu_pmu_i0_pc4 = io_dec_exu_tlu_exu_exu_pmu_i0_pc4; // @[dec.scala 225:18]
+  assign tlu_io_tlu_exu_exu_npc_r = io_dec_exu_tlu_exu_exu_npc_r; // @[dec.scala 225:18]
+  assign tlu_io_tlu_dma_dma_pmu_dccm_read = io_dec_dma_tlu_dma_dma_pmu_dccm_read; // @[dec.scala 226:18]
+  assign tlu_io_tlu_dma_dma_pmu_dccm_write = io_dec_dma_tlu_dma_dma_pmu_dccm_write; // @[dec.scala 226:18]
+  assign tlu_io_tlu_dma_dma_pmu_any_read = io_dec_dma_tlu_dma_dma_pmu_any_read; // @[dec.scala 226:18]
+  assign tlu_io_tlu_dma_dma_pmu_any_write = io_dec_dma_tlu_dma_dma_pmu_any_write; // @[dec.scala 226:18]
+  assign tlu_io_tlu_dma_dma_dccm_stall_any = io_dec_dma_tlu_dma_dma_dccm_stall_any; // @[dec.scala 226:18]
+  assign tlu_io_tlu_dma_dma_iccm_stall_any = io_dec_dma_tlu_dma_dma_iccm_stall_any; // @[dec.scala 226:18]
+  assign tlu_io_free_clk = io_free_clk; // @[dec.scala 228:45]
+  assign tlu_io_free_l2clk = io_free_l2clk; // @[dec.scala 227:45]
+  assign tlu_io_rst_vec = io_rst_vec; // @[dec.scala 230:45]
+  assign tlu_io_nmi_int = io_nmi_int; // @[dec.scala 231:45]
+  assign tlu_io_nmi_vec = io_nmi_vec; // @[dec.scala 232:45]
+  assign tlu_io_i_cpu_halt_req = io_i_cpu_halt_req; // @[dec.scala 233:45]
+  assign tlu_io_i_cpu_run_req = io_i_cpu_run_req; // @[dec.scala 234:45]
+  assign tlu_io_lsu_fastint_stall_any = io_lsu_fastint_stall_any; // @[dec.scala 235:45]
+  assign tlu_io_lsu_idle_any = io_lsu_idle_any; // @[dec.scala 266:45]
+  assign tlu_io_dec_pmu_instr_decoded = decode_io_dec_pmu_instr_decoded; // @[dec.scala 237:45]
+  assign tlu_io_dec_pmu_decode_stall = decode_io_dec_pmu_decode_stall; // @[dec.scala 238:45]
+  assign tlu_io_dec_pmu_presync_stall = decode_io_dec_pmu_presync_stall; // @[dec.scala 239:45]
+  assign tlu_io_dec_pmu_postsync_stall = decode_io_dec_pmu_postsync_stall; // @[dec.scala 240:45]
+  assign tlu_io_lsu_store_stall_any = io_lsu_store_stall_any; // @[dec.scala 241:45]
+  assign tlu_io_lsu_fir_addr = io_lsu_fir_addr; // @[dec.scala 245:45]
+  assign tlu_io_lsu_fir_error = io_lsu_fir_error; // @[dec.scala 246:45]
+  assign tlu_io_iccm_dma_sb_error = io_iccm_dma_sb_error; // @[dec.scala 247:45]
+  assign tlu_io_lsu_error_pkt_r_valid = io_lsu_error_pkt_r_valid; // @[dec.scala 248:45]
+  assign tlu_io_lsu_error_pkt_r_bits_single_ecc_error = io_lsu_error_pkt_r_bits_single_ecc_error; // @[dec.scala 248:45]
+  assign tlu_io_lsu_error_pkt_r_bits_inst_type = io_lsu_error_pkt_r_bits_inst_type; // @[dec.scala 248:45]
+  assign tlu_io_lsu_error_pkt_r_bits_exc_type = io_lsu_error_pkt_r_bits_exc_type; // @[dec.scala 248:45]
+  assign tlu_io_lsu_error_pkt_r_bits_mscause = io_lsu_error_pkt_r_bits_mscause; // @[dec.scala 248:45]
+  assign tlu_io_lsu_error_pkt_r_bits_addr = io_lsu_error_pkt_r_bits_addr; // @[dec.scala 248:45]
+  assign tlu_io_lsu_single_ecc_error_incr = io_lsu_single_ecc_error_incr; // @[dec.scala 249:45]
+  assign tlu_io_dec_pause_state = decode_io_dec_pause_state; // @[dec.scala 250:45]
+  assign tlu_io_dec_csr_wen_unq_d = decode_io_dec_csr_wen_unq_d; // @[dec.scala 251:45]
+  assign tlu_io_dec_csr_any_unq_d = decode_io_dec_csr_any_unq_d; // @[dec.scala 252:45]
+  assign tlu_io_dec_csr_rdaddr_d = decode_io_dec_csr_rdaddr_d; // @[dec.scala 253:45]
+  assign tlu_io_dec_csr_wen_r = decode_io_dec_csr_wen_r; // @[dec.scala 254:45]
+  assign tlu_io_dec_csr_wraddr_r = decode_io_dec_csr_wraddr_r; // @[dec.scala 255:45]
+  assign tlu_io_dec_csr_wrdata_r = decode_io_dec_csr_wrdata_r; // @[dec.scala 256:45]
+  assign tlu_io_dec_csr_stall_int_ff = decode_io_dec_csr_stall_int_ff; // @[dec.scala 257:45]
+  assign tlu_io_dec_tlu_i0_valid_r = decode_io_dec_tlu_i0_valid_r; // @[dec.scala 258:45]
+  assign tlu_io_dec_tlu_i0_pc_r = decode_io_dec_tlu_i0_pc_r; // @[dec.scala 259:45]
+  assign tlu_io_dec_tlu_packet_r_legal = decode_io_dec_tlu_packet_r_legal; // @[dec.scala 260:45]
+  assign tlu_io_dec_tlu_packet_r_icaf = decode_io_dec_tlu_packet_r_icaf; // @[dec.scala 260:45]
+  assign tlu_io_dec_tlu_packet_r_icaf_second = decode_io_dec_tlu_packet_r_icaf_second; // @[dec.scala 260:45]
+  assign tlu_io_dec_tlu_packet_r_icaf_type = decode_io_dec_tlu_packet_r_icaf_type; // @[dec.scala 260:45]
+  assign tlu_io_dec_tlu_packet_r_fence_i = decode_io_dec_tlu_packet_r_fence_i; // @[dec.scala 260:45]
+  assign tlu_io_dec_tlu_packet_r_i0trigger = decode_io_dec_tlu_packet_r_i0trigger; // @[dec.scala 260:45]
+  assign tlu_io_dec_tlu_packet_r_pmu_i0_itype = decode_io_dec_tlu_packet_r_pmu_i0_itype; // @[dec.scala 260:45]
+  assign tlu_io_dec_tlu_packet_r_pmu_i0_br_unpred = decode_io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[dec.scala 260:45]
+  assign tlu_io_dec_tlu_packet_r_pmu_divide = decode_io_dec_tlu_packet_r_pmu_divide; // @[dec.scala 260:45]
+  assign tlu_io_dec_tlu_packet_r_pmu_lsu_misaligned = decode_io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec.scala 260:45]
+  assign tlu_io_dec_illegal_inst = decode_io_dec_illegal_inst; // @[dec.scala 261:45]
+  assign tlu_io_dec_i0_decode_d = decode_io_dec_i0_decode_d; // @[dec.scala 262:45]
+  assign tlu_io_exu_i0_br_way_r = io_exu_i0_br_way_r; // @[dec.scala 263:45]
+  assign tlu_io_dbg_halt_req = io_dbg_halt_req; // @[dec.scala 264:45]
+  assign tlu_io_dbg_resume_req = io_dbg_resume_req; // @[dec.scala 265:45]
+  assign tlu_io_dec_div_active = decode_io_dec_div_active; // @[dec.scala 267:45]
+  assign tlu_io_timer_int = io_timer_int; // @[dec.scala 268:45]
+  assign tlu_io_soft_int = io_soft_int; // @[dec.scala 269:45]
+  assign tlu_io_core_id = io_core_id; // @[dec.scala 270:45]
+  assign tlu_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[dec.scala 271:45]
+  assign tlu_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[dec.scala 272:45]
+  assign tlu_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[dec.scala 273:45]
+  assign tlu_io_ifu_pmu_instr_aligned = io_ifu_dec_dec_aln_ifu_pmu_instr_aligned; // @[dec.scala 236:45]
+  assign tlu_io_tlu_ifc_ifu_pmu_fetch_stall = io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall; // @[dec.scala 223:18]
+  assign tlu_io_tlu_mem_ifu_pmu_ic_miss = io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss; // @[dec.scala 222:18]
+  assign tlu_io_tlu_mem_ifu_pmu_ic_hit = io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[dec.scala 222:18]
+  assign tlu_io_tlu_mem_ifu_pmu_bus_error = io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[dec.scala 222:18]
+  assign tlu_io_tlu_mem_ifu_pmu_bus_busy = io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[dec.scala 222:18]
+  assign tlu_io_tlu_mem_ifu_pmu_bus_trxn = io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[dec.scala 222:18]
+  assign tlu_io_tlu_mem_ifu_ic_error_start = io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[dec.scala 222:18]
+  assign tlu_io_tlu_mem_ifu_iccm_rd_ecc_single_err = io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[dec.scala 222:18]
+  assign tlu_io_tlu_mem_ifu_ic_debug_rd_data = io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[dec.scala 222:18]
+  assign tlu_io_tlu_mem_ifu_ic_debug_rd_data_valid = io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[dec.scala 222:18]
+  assign tlu_io_tlu_mem_ifu_miss_state_idle = io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle; // @[dec.scala 222:18]
+  assign tlu_io_tlu_busbuff_lsu_pmu_bus_trxn = io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[dec.scala 242:26]
+  assign tlu_io_tlu_busbuff_lsu_pmu_bus_misaligned = io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[dec.scala 242:26]
+  assign tlu_io_tlu_busbuff_lsu_pmu_bus_error = io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[dec.scala 242:26]
+  assign tlu_io_tlu_busbuff_lsu_pmu_bus_busy = io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[dec.scala 242:26]
+  assign tlu_io_tlu_busbuff_lsu_imprecise_error_load_any = io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[dec.scala 242:26]
+  assign tlu_io_tlu_busbuff_lsu_imprecise_error_store_any = io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[dec.scala 242:26]
+  assign tlu_io_tlu_busbuff_lsu_imprecise_error_addr_any = io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any; // @[dec.scala 242:26]
+  assign tlu_io_lsu_tlu_lsu_pmu_load_external_m = io_lsu_tlu_lsu_pmu_load_external_m; // @[dec.scala 243:14]
+  assign tlu_io_lsu_tlu_lsu_pmu_store_external_m = io_lsu_tlu_lsu_pmu_store_external_m; // @[dec.scala 243:14]
+  assign tlu_io_dec_pic_pic_claimid = io_dec_pic_pic_claimid; // @[dec.scala 244:14]
+  assign tlu_io_dec_pic_pic_pl = io_dec_pic_pic_pl; // @[dec.scala 244:14]
+  assign tlu_io_dec_pic_mhwakeup = io_dec_pic_mhwakeup; // @[dec.scala 244:14]
+  assign tlu_io_dec_pic_mexintpend = io_dec_pic_mexintpend; // @[dec.scala 244:14]
+  assign dec_trigger_io_trigger_pkt_any_0_select = tlu_io_trigger_pkt_any_0_select; // @[dec.scala 143:34]
+  assign dec_trigger_io_trigger_pkt_any_0_match_pkt = tlu_io_trigger_pkt_any_0_match_pkt; // @[dec.scala 143:34]
+  assign dec_trigger_io_trigger_pkt_any_0_execute = tlu_io_trigger_pkt_any_0_execute; // @[dec.scala 143:34]
+  assign dec_trigger_io_trigger_pkt_any_0_m = tlu_io_trigger_pkt_any_0_m; // @[dec.scala 143:34]
+  assign dec_trigger_io_trigger_pkt_any_0_tdata2 = tlu_io_trigger_pkt_any_0_tdata2; // @[dec.scala 143:34]
+  assign dec_trigger_io_trigger_pkt_any_1_select = tlu_io_trigger_pkt_any_1_select; // @[dec.scala 143:34]
+  assign dec_trigger_io_trigger_pkt_any_1_match_pkt = tlu_io_trigger_pkt_any_1_match_pkt; // @[dec.scala 143:34]
+  assign dec_trigger_io_trigger_pkt_any_1_execute = tlu_io_trigger_pkt_any_1_execute; // @[dec.scala 143:34]
+  assign dec_trigger_io_trigger_pkt_any_1_m = tlu_io_trigger_pkt_any_1_m; // @[dec.scala 143:34]
+  assign dec_trigger_io_trigger_pkt_any_1_tdata2 = tlu_io_trigger_pkt_any_1_tdata2; // @[dec.scala 143:34]
+  assign dec_trigger_io_trigger_pkt_any_2_select = tlu_io_trigger_pkt_any_2_select; // @[dec.scala 143:34]
+  assign dec_trigger_io_trigger_pkt_any_2_match_pkt = tlu_io_trigger_pkt_any_2_match_pkt; // @[dec.scala 143:34]
+  assign dec_trigger_io_trigger_pkt_any_2_execute = tlu_io_trigger_pkt_any_2_execute; // @[dec.scala 143:34]
+  assign dec_trigger_io_trigger_pkt_any_2_m = tlu_io_trigger_pkt_any_2_m; // @[dec.scala 143:34]
+  assign dec_trigger_io_trigger_pkt_any_2_tdata2 = tlu_io_trigger_pkt_any_2_tdata2; // @[dec.scala 143:34]
+  assign dec_trigger_io_trigger_pkt_any_3_select = tlu_io_trigger_pkt_any_3_select; // @[dec.scala 143:34]
+  assign dec_trigger_io_trigger_pkt_any_3_match_pkt = tlu_io_trigger_pkt_any_3_match_pkt; // @[dec.scala 143:34]
+  assign dec_trigger_io_trigger_pkt_any_3_execute = tlu_io_trigger_pkt_any_3_execute; // @[dec.scala 143:34]
+  assign dec_trigger_io_trigger_pkt_any_3_m = tlu_io_trigger_pkt_any_3_m; // @[dec.scala 143:34]
+  assign dec_trigger_io_trigger_pkt_any_3_tdata2 = tlu_io_trigger_pkt_any_3_tdata2; // @[dec.scala 143:34]
+  assign dec_trigger_io_dec_i0_pc_d = instbuff_io_ib_exu_dec_i0_pc_d; // @[dec.scala 142:30]
 endmodule
diff --git a/src/main/scala/dec/dec.scala b/src/main/scala/dec/dec.scala
index a828ce73..16bc5bc1 100644
--- a/src/main/scala/dec/dec.scala
+++ b/src/main/scala/dec/dec.scala
@@ -98,6 +98,8 @@ class dec_IO extends Bundle with lib {
   val dec_tlu_dccm_clk_override = Output(Bool())       // override DCCM clock domain gating
   val dec_tlu_icm_clk_override  = Output(Bool())       // override ICCM clock domain gating
 
+  val dec_i0_decode_d           =   Output(Bool())
+
   val scan_mode                 = Input(Bool())
   val ifu_dec = Flipped(new ifu_dec)
   val dec_exu = Flipped(new dec_exu)
@@ -143,7 +145,7 @@ class dec extends Module with param with RequireAsyncReset{
   val dec_i0_trigger_match_d = dec_trigger.io.dec_i0_trigger_match_d
   dontTouch(dec_i0_trigger_match_d)
   decode.io.dec_aln <> io.ifu_dec.dec_aln.aln_dec
-
+  io.dec_i0_decode_d := decode.io.dec_i0_decode_d
   decode.io.decode_exu<> io.dec_exu.decode_exu
   decode.io.dec_alu<> io.dec_exu.dec_alu
   decode.io.dec_div<> io.dec_exu.dec_div
@@ -257,7 +259,7 @@ class dec extends Module with param with RequireAsyncReset{
   tlu.io.dec_tlu_i0_pc_r                    :=  decode.io.dec_tlu_i0_pc_r
   tlu.io.dec_tlu_packet_r                   :=  decode.io.dec_tlu_packet_r
   tlu.io.dec_illegal_inst                   :=  decode.io.dec_illegal_inst
-  tlu.io.dec_i0_decode_d                    :=  decode.io.dec_aln.dec_i0_decode_d
+  tlu.io.dec_i0_decode_d                    :=  decode.io.dec_i0_decode_d
   tlu.io.exu_i0_br_way_r                    :=  io.exu_i0_br_way_r
   tlu.io.dbg_halt_req                       :=  io.dbg_halt_req
   tlu.io.dbg_resume_req                     :=  io.dbg_resume_req
@@ -300,7 +302,7 @@ class dec extends Module with param with RequireAsyncReset{
   io.dec_tlu_pic_clk_override      := tlu.io.dec_tlu_pic_clk_override
   io.dec_tlu_dccm_clk_override     := tlu.io.dec_tlu_dccm_clk_override
   io.dec_tlu_icm_clk_override      := tlu.io.dec_tlu_icm_clk_override
-  io.dec_tlu_picio_clk_override    := tlu.io.dec_tlu_icm_clk_override
+  io.dec_tlu_picio_clk_override    := tlu.io.dec_tlu_picio_clk_override
   io.dec_tlu_core_empty            := tlu.io.dec_tlu_core_empty
   io.dec_csr_rddata_d              := tlu.io.dec_csr_rddata_d
   io.dec_tlu_flush_lower_wb        := tlu.io.dec_tlu_flush_lower_wb
diff --git a/src/main/scala/dec/dec_decode_ctl.scala b/src/main/scala/dec/dec_decode_ctl.scala
index aeaf2437..4b01aca9 100644
--- a/src/main/scala/dec/dec_decode_ctl.scala
+++ b/src/main/scala/dec/dec_decode_ctl.scala
@@ -112,6 +112,7 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{
     val dec_pause_state_cg            =   Output(Bool())    // pause state for clock-gating
     val dec_div_active                =   Output(Bool())    // non-block divide is active
     val scan_mode                     =   Input(Bool())
+    val dec_i0_decode_d           =   Output(Bool())
   })
   //packets zero initialization
   io.decode_exu.mul_p   := 0.U.asTypeOf(io.decode_exu.mul_p)
@@ -201,6 +202,7 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{
   val fa_error_index_ns     = WireInit(Bool(),0.B)
   val btb_error_found       = WireInit(Bool(),0.B)
   val div_active_in          = WireInit(Bool(),0.B)
+
   //////////////////////////////////////////////////////////////////////
 
   leak1_i1_stall                  := rvdffie(leak1_i1_stall_in, io.free_l2clk, reset.asAsyncReset(), io.scan_mode)
@@ -444,7 +446,7 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{
   // can't make this clock active_clock
   leak1_i1_stall_in := (io.dec_tlu_flush_leak_one_r | (leak1_i1_stall & !io.dec_tlu_flush_lower_r))
   leak1_mode := leak1_i1_stall
-  leak1_i0_stall_in := ((io.dec_aln.dec_i0_decode_d & leak1_i1_stall) | (leak1_i0_stall & !io.dec_tlu_flush_lower_r))
+  leak1_i0_stall_in := ((io.dec_i0_decode_d & leak1_i1_stall) | (leak1_i0_stall & !io.dec_tlu_flush_lower_r))
 
   // 12b jal's can be predicted - these are calls
 
@@ -591,7 +593,7 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{
   val i0_inst_d      = Mux(io.dec_i0_pc4_d,i0,Cat(repl(16,0.U), io.dec_aln.ifu_i0_cinst))
   // illegal inst handling
 
-  val shift_illegal      = io.dec_aln.dec_i0_decode_d & !i0_legal//lm: valid but not legal
+  val shift_illegal      = io.dec_i0_decode_d & !i0_legal//lm: valid but not legal
   val illegal_inst_en    = shift_illegal & !illegal_lockout
   io.dec_illegal_inst := rvdffe(i0_inst_d,illegal_inst_en,clock,io.scan_mode)
   illegal_lockout_in := (shift_illegal | illegal_lockout) & !flush_final_r
@@ -608,13 +610,13 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{
   val i0_exublock_d = i0_block_raw_d
 
   //decode valid
-  io.dec_aln.dec_i0_decode_d := io.dec_ib0_valid_d & !i0_block_d    & !io.dec_tlu_flush_lower_r & !flush_final_r
+  io.dec_i0_decode_d := io.dec_ib0_valid_d & !i0_block_d    & !io.dec_tlu_flush_lower_r & !flush_final_r
   val i0_exudecode_d  = io.dec_ib0_valid_d & !i0_exublock_d & !io.dec_tlu_flush_lower_r & !flush_final_r
   val i0_exulegal_decode_d = i0_exudecode_d  & i0_legal
 
   // performance monitor signals
-  io.dec_pmu_instr_decoded := io.dec_aln.dec_i0_decode_d
-  io.dec_pmu_decode_stall := io.dec_ib0_valid_d & !io.dec_aln.dec_i0_decode_d
+  io.dec_pmu_instr_decoded := io.dec_i0_decode_d
+  io.dec_pmu_decode_stall := io.dec_ib0_valid_d & !io.dec_i0_decode_d
   io.dec_pmu_postsync_stall := postsync_stall.asBool & io.dec_ib0_valid_d
   io.dec_pmu_presync_stall  := presync_stall.asBool & io.dec_ib0_valid_d
 
@@ -625,7 +627,7 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{
 
   presync_stall      := (i0_presync & prior_inflight_eff)
   // illegals will postsync
-  ps_stall_in :=  (io.dec_aln.dec_i0_decode_d & (i0_postsync | !i0_legal) ) | ( postsync_stall & prior_inflight_x)
+  ps_stall_in :=  (io.dec_i0_decode_d & (i0_postsync | !i0_legal) ) | ( postsync_stall & prior_inflight_x)
 
   io.dec_alu.dec_i0_alu_decode_d := i0_exulegal_decode_d & i0_dp.alu
   io.decode_exu.dec_i0_branch_d     := i0_dp.condbr | i0_dp.jal | i0_br_error_all
@@ -649,7 +651,7 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{
   d_t.pmu_divide         :=  0.U(1.W)
   d_t.pmu_lsu_misaligned :=  0.U(1.W)
 
-  d_t.i0trigger          :=  io.dec_i0_trigger_match_d & repl(4,io.dec_aln.dec_i0_decode_d)
+  d_t.i0trigger          :=  io.dec_i0_trigger_match_d & repl(4,io.dec_i0_decode_d)
 
 
   x_t := rvdfflie(d_t,clock,reset.asAsyncReset,i0_x_ctl_en.asBool,io.scan_mode, elements = 3)
@@ -671,7 +673,7 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{
   // end tlu stuff
 
 
-  io.dec_aln.dec_i0_decode_d := io.dec_ib0_valid_d & !i0_block_d & !io.dec_tlu_flush_lower_r & !flush_final_r
+  io.dec_i0_decode_d := io.dec_ib0_valid_d & !i0_block_d & !io.dec_tlu_flush_lower_r & !flush_final_r
 
   i0r.rs1 := i0(19,15) //H: ing reg packets the instructions bits
   i0r.rs2 := i0(24,20)
@@ -753,7 +755,7 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{
     bitmanip_zbb_zbp_legal  := !(i0_dp.zbb & i0_dp.zbp)
 
   bitmanip_legal :=  bitmanip_zbb_legal & bitmanip_zbs_legal & bitmanip_zbe_legal & bitmanip_zbc_legal & bitmanip_zbp_legal & bitmanip_zbr_legal & bitmanip_zbf_legal & bitmanip_zba_legal & bitmanip_zbb_zbp_legal
-  i0_legal_decode_d    := io.dec_aln.dec_i0_decode_d & i0_legal
+  i0_legal_decode_d    := io.dec_i0_decode_d & i0_legal
 
   i0_d_c.mul                :=  i0_dp.mul  & i0_legal_decode_d
   i0_d_c.load               :=  i0_dp.load & i0_legal_decode_d
@@ -761,7 +763,7 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{
 
   val i0_x_c = withClock(io.active_clk){RegEnable(i0_d_c,0.U.asTypeOf(i0_d_c), i0_x_ctl_en.asBool)}
   val i0_r_c = withClock(io.active_clk){RegEnable(i0_x_c,0.U.asTypeOf(i0_x_c), i0_r_ctl_en.asBool)}
-  i0_pipe_en := Cat(io.dec_aln.dec_i0_decode_d,withClock(io.active_clk){RegNext(i0_pipe_en(3,1), init=0.U)})
+  i0_pipe_en := Cat(io.dec_i0_decode_d,withClock(io.active_clk){RegNext(i0_pipe_en(3,1), init=0.U)})
 
   i0_x_ctl_en               := (i0_pipe_en(3,2).orR | io.clk_override)
   i0_r_ctl_en               := (i0_pipe_en(2,1).orR | io.clk_override)
@@ -775,14 +777,14 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{
 
   d_d.bits.i0rd                  :=  i0r.rd
   d_d.bits.i0v                   :=  i0_rd_en_d  & i0_legal_decode_d
-  d_d.valid               :=  io.dec_aln.dec_i0_decode_d  // has flush_final_r
+  d_d.valid                       :=  io.dec_i0_decode_d  // has flush_final_r
 
   d_d.bits.i0load                :=  i0_dp.load  & i0_legal_decode_d
   d_d.bits.i0store               :=  i0_dp.store & i0_legal_decode_d
   d_d.bits.i0div                 :=  i0_dp.div   & i0_legal_decode_d
 
   d_d.bits.csrwen                :=  io.dec_csr_wen_unq_d   & i0_legal_decode_d
-  d_d.bits.csrwonly              :=  i0_csr_write_only_d & io.dec_aln.dec_i0_decode_d
+  d_d.bits.csrwonly              :=  i0_csr_write_only_d & io.dec_i0_decode_d
   d_d.bits.csrwaddr              :=  Mux(d_d.bits.csrwen, i0(31,20), 0.U)
 
   x_d := rvdfflie(d_d,clock,reset.asAsyncReset(), i0_x_ctl_en.asBool,io.scan_mode,elements = 4)
diff --git a/src/main/scala/ifu/ifu_aln_ctl.scala b/src/main/scala/ifu/ifu_aln_ctl.scala
index 5b6040f3..7414c781 100644
--- a/src/main/scala/ifu/ifu_aln_ctl.scala
+++ b/src/main/scala/ifu/ifu_aln_ctl.scala
@@ -1,405 +1,405 @@
-package ifu
-import lib._
-import chisel3._
-import chisel3.util._
-import include._
-
-class ifu_aln_ctl extends Module with lib with RequireAsyncReset {
-  val io = IO(new Bundle{
-    val scan_mode = Input(Bool())
-    val active_clk              = Input(Clock())
-    val ifu_async_error_start   = Input(Bool()) // Error coming from mem-ctl
-    val iccm_rd_ecc_double_err  = Input(Bool()) // ICCM double error coming from mem-ctl
-    val ic_access_fault_f       = Input(Bool()) // Access fault in I$
-    val ic_access_fault_type_f  = Input(UInt(2.W)) // Type of access fault occured
-    val ifu_bp_fghr_f           = Input(UInt(BHT_GHR_SIZE.W)) // Data coming from the branch predictor to put in the FP
-    val ifu_bp_btb_target_f     = Input(UInt(31.W)) // Target for the instruction enqueue in the FP
-    val ifu_bp_poffset_f        = Input(UInt(12.W)) // Offset to the current PC for branch
-    val ifu_bp_hist0_f          = Input(UInt(2.W)) // History to EXU
-    val ifu_bp_hist1_f          = Input(UInt(2.W)) // History to EXU
-    val ifu_bp_pc4_f            = Input(UInt(2.W)) // PC4
-    val ifu_bp_way_f            = Input(UInt(2.W)) // Way to help in miss prediction
-    val ifu_bp_valid_f          = Input(UInt(2.W)) // Valid Branch prediction
-    val ifu_bp_ret_f            = Input(UInt(2.W)) // BP ret
-    val exu_flush_final         = Input(Bool()) // Miss prediction
-    val dec_aln                 = new dec_aln() // Data going to the dec from the ALN
-    val ifu_fetch_data_f        = Input(UInt(32.W)) // PC of the current instruction in the FP
-    val ifu_fetch_val           = Input(UInt(2.W)) // PC boundary i.e 'x' of 2 or 4
-    val ifu_fetch_pc            = Input(UInt(31.W)) // Current PC
-   /////////////////////////////////////////////////
-    val ifu_fb_consume1         = Output(Bool()) // FP used 1
-    val ifu_fb_consume2         = Output(Bool()) // FP used 2
-
-  })
-  val MHI = 46+BHT_GHR_SIZE // 54
-  val MSIZE = 47+BHT_GHR_SIZE // 55
-  val BRDATA_SIZE = 12
-  val error_stall_in = WireInit(Bool(),0.U)
-  val alignval = WireInit(UInt(2.W), 0.U)
-  val q0final = WireInit(UInt(32.W), 0.U)
-  val q1final = WireInit(UInt(16.W), 0.U)
-  val wrptr_in = WireInit(UInt(2.W), init = 0.U)
-  val rdptr_in = WireInit(UInt(2.W), init = 0.U)
-
-  val f2val_in = WireInit(UInt(2.W), init = 0.U)
-  val f1val_in = WireInit(UInt(2.W), init = 0.U)
-  val f0val_in = WireInit(UInt(2.W), init = 0.U)
-
-  val q2off_in = WireInit(UInt(1.W), init = 0.U)
-  val q1off_in = WireInit(UInt(1.W), init = 0.U)
-  val q0off_in = WireInit(UInt(1.W), init = 0.U)
-
-  val sf0_valid = WireInit(Bool(), init = 0.U)
-  val sf1_valid = WireInit(Bool(), init = 0.U)
-
-  val f2_valid = WireInit(Bool(), init = 0.U)
-  val ifvalid = WireInit(Bool(), init = 0.U)
-  val shift_f2_f1 = WireInit(Bool(), init = 0.U)
-  val shift_f2_f0 = WireInit(Bool(), init = 0.U)
-  val shift_f1_f0 = WireInit(Bool(), init = 0.U)
-
-  val f0icaf = WireInit(Bool(), init = 0.U)
-  val f1icaf = WireInit(Bool(), init = 0.U)
-
-  val sf0val = WireInit(UInt(2.W), 0.U)
-  val sf1val = WireInit(UInt(2.W), 0.U)
-
-  val misc0 = WireInit(UInt((MHI+1).W), 0.U)
-  val misc1 = WireInit(UInt((MHI+1).W), 0.U)
-  val misc2 = WireInit(UInt((MHI+1).W), 0.U)
-
-  val brdata1 = WireInit(UInt(12.W), init = 0.U)
-  val brdata0 = WireInit(UInt(12.W), init = 0.U)
-  val brdata2 = WireInit(UInt(12.W), init = 0.U)
-
-  val q0 = WireInit(UInt(32.W), init = 0.U)
-  val q1 = WireInit(UInt(32.W), init = 0.U)
-  val q2 = WireInit(UInt(32.W), init = 0.U)
-
-  val f1pc_in = WireInit(UInt(31.W), 0.U)
-  val f0pc_in = WireInit(UInt(31.W), 0.U)
-  val error_stall = WireInit(Bool(), 0.U)
-  val f2_wr_en = WireInit(Bool(), 0.U)
-  val shift_4B = WireInit(Bool(), 0.U)
-  val f1_shift_wr_en = WireInit(Bool(), 0.U)
-  val f0_shift_wr_en = WireInit(Bool(), 0.U)
-  val qwen = WireInit(UInt(3.W), 0.U)
-  val brdata_in = WireInit(UInt(BRDATA_SIZE.W), 0.U)
-  val misc_data_in = WireInit(UInt((MHI+1).W), 0.U)
-
-  val fetch_to_f0 = WireInit(Bool(), 0.U)
-  val fetch_to_f1 = WireInit(Bool(), 0.U)
-  val fetch_to_f2 = WireInit(Bool(), 0.U)
-  val f1_shift_2B = WireInit(Bool(), 0.U)
-  val first4B = WireInit(Bool(), 0.U)
-  val shift_2B = WireInit(Bool(), 0.U)
-  val f0_shift_2B = WireInit(Bool(), 0.U)
-
-  // Stall if there is an error in the instrucion
-  error_stall_in := (error_stall | io.ifu_async_error_start) & !io.exu_flush_final
-
-  // Flop the stall until flush
-  error_stall := withClock(io.active_clk) {RegNext(error_stall_in, init = 0.U)}
-  // Write Ptr of the FP
-  val wrptr = withClock(io.active_clk) {RegNext(wrptr_in, init = 0.U)}
-  // Read Ptr of the FP
-  val rdptr = withClock(io.active_clk) {RegNext(rdptr_in, init = 0.U)}
-  // Fetch Instruction boundary
-  val f2val = withClock(io.active_clk) {RegNext(f2val_in, init = 0.U)}
-  val f1val = withClock(io.active_clk) {RegNext(f1val_in, init = 0.U)}
-  val f0val = withClock(io.active_clk) {RegNext(f0val_in, init = 0.U)}
-
-  val q2off = withClock(io.active_clk) {RegNext(q2off_in, init = 0.U)}
-  val q1off = withClock(io.active_clk) {RegNext(q1off_in, init = 0.U)}
-  val q0off = withClock(io.active_clk) {RegNext(q0off_in, init = 0.U)}
-  // Instrution PC to the FP
-  val f2pc = rvdffe(io.ifu_fetch_pc, f2_wr_en.asBool, clock, io.scan_mode)
-  val f1pc = rvdffe(f1pc_in, f1_shift_wr_en.asBool, clock, io.scan_mode)
-  val f0pc = rvdffe(f0pc_in, f0_shift_wr_en.asBool, clock, io.scan_mode)
-  // Branch data to the FP
-  brdata2 := rvdffe(brdata_in, qwen(2), clock, io.scan_mode)
-  brdata1 := rvdffe(brdata_in, qwen(1), clock, io.scan_mode)
-  brdata0 := rvdffe(brdata_in, qwen(0), clock, io.scan_mode)
-  // Miscalanious data to the FP including error's
-  misc2 := rvdffe(misc_data_in, qwen(2), clock, io.scan_mode)
-  misc1 := rvdffe(misc_data_in, qwen(1), clock, io.scan_mode)
-  misc0 := rvdffe(misc_data_in, qwen(0), clock, io.scan_mode)
-  // Instruction in the FP
-  q2 := rvdffe(io.ifu_fetch_data_f, qwen(2), clock, io.scan_mode)
-  q1 := rvdffe(io.ifu_fetch_data_f, qwen(1), clock, io.scan_mode)
-  q0 := rvdffe(io.ifu_fetch_data_f, qwen(0), clock, io.scan_mode)
-
-  // Shift FP logic
-  f2_wr_en       := fetch_to_f2
-  f1_shift_wr_en := fetch_to_f1 | shift_f2_f1 | f1_shift_2B
-  f0_shift_wr_en := fetch_to_f0 | shift_f2_f0 | shift_f1_f0 | shift_2B | shift_4B
-  // FP read enable .. 3-bit for Implemenation of 1HMux
-  val qren = Cat(rdptr === 2.U, rdptr === 1.U, rdptr === 0.U)
-  // FP write enable .. 3-bit for Implemenation of 1HMux
-  qwen := Cat(wrptr === 2.U & ifvalid, wrptr === 1.U & ifvalid, wrptr === 0.U & ifvalid)
-
-  // Read Pointer calculation
-  // Next rdptr = # of consume + current ptr location (Rounding it from 2)
-  rdptr_in := Mux1H(Seq((qren(0) & io.ifu_fb_consume1 & !io.exu_flush_final).asBool -> 1.U,
-    (qren(1) & io.ifu_fb_consume1 & !io.exu_flush_final).asBool -> 2.U,
-    (qren(2) & io.ifu_fb_consume1 & !io.exu_flush_final).asBool -> 0.U,
-    (qren(0) & io.ifu_fb_consume2 & !io.exu_flush_final).asBool -> 2.U,
-    (qren(1) & io.ifu_fb_consume2 & !io.exu_flush_final).asBool -> 0.U,
-    (qren(2) & io.ifu_fb_consume2 & !io.exu_flush_final).asBool -> 1.U,
-    (!io.ifu_fb_consume1 & !io.ifu_fb_consume2 & !io.exu_flush_final).asBool -> rdptr))
-
-  // As there is only 1 enqueue so each time move by 1
-  wrptr_in := Mux1H(Seq((qwen(0) & !io.exu_flush_final).asBool -> 1.U,
-    (qwen(1) & !io.exu_flush_final).asBool -> 2.U,
-    (qwen(2) & !io.exu_flush_final).asBool -> 0.U,
-    (!ifvalid & !io.exu_flush_final).asBool->wrptr))
-
-  q2off_in := Mux1H(Seq((!qwen(2) & (rdptr===2.U)).asBool->(q2off.asUInt | f0_shift_2B),
-    (!qwen(2) & (rdptr===1.U)).asBool->(q2off.asUInt | f1_shift_2B),
-    (!qwen(2) & (rdptr===0.U)).asBool->q2off))
-
-  q1off_in := Mux1H(Seq((!qwen(1) & (rdptr===1.U)).asBool->(q1off.asUInt | f0_shift_2B),
-    (!qwen(1) & (rdptr===0.U)).asBool->(q1off.asUInt | f1_shift_2B),
-    (!qwen(1) & (rdptr===2.U)).asBool->q1off))
-
-  q0off_in := Mux1H(Seq((!qwen(0) & (rdptr===0.U)).asBool -> (q0off.asUInt | f0_shift_2B),
-                        (!qwen(0) & (rdptr===2.U)).asBool -> (q0off.asUInt | f1_shift_2B),
-                        (!qwen(0) & (rdptr===1.U)).asBool ->  q0off))
-
-  val q0ptr = Mux1H(Seq((rdptr===0.U)->q0off,
-    (rdptr===1.U)->q1off,
-    (rdptr===2.U)->q2off))
-
-  val  q1ptr = Mux1H(Seq((rdptr===0.U) -> q1off, (rdptr === 1.U) -> q2off, (rdptr === 2.U) -> q0off))
-
-  val q0sel = Cat(q0ptr, !q0ptr)
-
-  val q1sel = Cat(q1ptr, !q1ptr)
-  // Misc data error, access-fault, type of fault, target, offset and ghr value
-  misc_data_in := Cat(io.iccm_rd_ecc_double_err, io.ic_access_fault_f, io.ic_access_fault_type_f,
-    io.ifu_bp_btb_target_f, io.ifu_bp_poffset_f, io.ifu_bp_fghr_f)
-
-  val misceff = Mux1H(Seq(qren(0).asBool() -> Cat(misc1, misc0),
-    qren(1).asBool()->Cat(misc2, misc1),
-    qren(2).asBool()->Cat(misc0, misc2)))
-
-  val misc1eff = misceff(misceff.getWidth-1,MHI+1)
-  val misc0eff = misceff(MHI, 0)
-
-
-  val f1dbecc = misc1eff(misc1eff.getWidth-1)
-  f1icaf := misc1eff(misc1eff.getWidth-2)
-  val f1ictype = misc1eff(misc1eff.getWidth-3,misc1eff.getWidth-4)
-  val f1prett = misc1eff(misc1eff.getWidth-5,misc1eff.getWidth-35)
-  val f1poffset = misc1eff(BHT_GHR_SIZE+11, BHT_GHR_SIZE)
-  val f1fghr = misc1eff(BHT_GHR_SIZE-1, 0)
-
-  val f0dbecc = misc0eff(misc1eff.getWidth-1)
-  f0icaf := misc0eff(misc1eff.getWidth-2)
-  val f0ictype = misc0eff(misc1eff.getWidth-3,misc1eff.getWidth-4)
-  val f0prett = misc0eff(misc1eff.getWidth-5,misc1eff.getWidth-35)
-  val f0poffset = misc0eff(BHT_GHR_SIZE+11, BHT_GHR_SIZE)
-  val f0fghr = misc0eff(BHT_GHR_SIZE-1, 0)
-
-  // Branch information
-  brdata_in := Cat(io.ifu_bp_hist1_f(1),io.ifu_bp_hist0_f(1),io.ifu_bp_pc4_f(1),io.ifu_bp_way_f(1),io.ifu_bp_valid_f(1),
-    io.ifu_bp_ret_f(1), io.ifu_bp_hist1_f(0),io.ifu_bp_hist0_f(0),io.ifu_bp_pc4_f(0),io.ifu_bp_way_f(0),
-    io.ifu_bp_valid_f(0),io.ifu_bp_ret_f(0))
-  // Effective branch information
-  val brdataeff = Mux1H(Seq(qren(0).asBool->Cat(brdata1,brdata0),
-    qren(1).asBool->Cat(brdata2,brdata1),
-    qren(2).asBool->Cat(brdata0,brdata2)))
-
-  val (brdata0eff,brdata1eff) = (brdataeff(11,0) , brdataeff(23,12))
-
-  val brdata0final = Mux1H(Seq(q0sel(0).asBool -> brdata0eff, q0sel(1).asBool -> brdata0eff(11,6)))
-  val brdata1final = Mux1H(Seq(q1sel(0).asBool -> brdata1eff, q1sel(1).asBool -> brdata1eff(11,6)))
-
-  val f0ret = Cat(brdata0final(6),brdata0final(0))
-  val f0brend = Cat(brdata0final(7),brdata0final(1))
-  val f0way = Cat(brdata0final(8),brdata0final(2))
-  val f0pc4 = Cat(brdata0final(9),brdata0final(3))
-  val f0hist0 = Cat(brdata0final(10),brdata0final(4))
-  val f0hist1 = Cat(brdata0final(11),brdata0final(5))
-
-  val f1ret = Cat(brdata1final(6),brdata1final(0))
-  val f1brend = Cat(brdata1final(7),brdata1final(1))
-  val f1way = Cat(brdata1final(8),brdata1final(2))
-  val f1pc4 = Cat(brdata1final(9),brdata1final(3))
-  val f1hist0 = Cat(brdata1final(10),brdata1final(4))
-  val f1hist1 = Cat(brdata1final(11),brdata1final(5))
-
-
-  f2_valid := f2val(0)
-  sf1_valid := sf1val(0)
-  sf0_valid := sf0val(0)
-
-  val consume_fb0 = !sf0val(0) & f0val(0)
-  val consume_fb1 = !sf1val(0) & f1val(0)
-
-  // Depending on type of instruction and boundary determine how many FP to consume
-  io.ifu_fb_consume1 := consume_fb0 & !consume_fb1 & !io.exu_flush_final
-  io.ifu_fb_consume2 := consume_fb0 &  consume_fb1 & !io.exu_flush_final
-
-  ifvalid := io.ifu_fetch_val(0)
-
-  // Shift logic for each dequeue
-  shift_f1_f0 := !sf0_valid &  sf1_valid
-  shift_f2_f0 := !sf0_valid & !sf1_valid &  f2_valid
-  shift_f2_f1 := !sf0_valid &  sf1_valid &  f2_valid
-
-  fetch_to_f0        :=  !sf0_valid & !sf1_valid & !f2_valid & ifvalid
-  fetch_to_f1        := (!sf0_valid & !sf1_valid &  f2_valid & ifvalid)  |
-                        (!sf0_valid &  sf1_valid & !f2_valid & ifvalid)  |
-                        ( sf0_valid & !sf1_valid & !f2_valid & ifvalid)
-
-  fetch_to_f2        := (!sf0_valid &  sf1_valid &  f2_valid & ifvalid)  |
-                        ( sf0_valid &  sf1_valid & !f2_valid & ifvalid)
-
-  val f0pc_plus1 = f0pc + 1.U
-
-  val f1pc_plus1 = f1pc + 1.U
-
-  val sf1pc = (Fill(31, f1_shift_2B) & f1pc_plus1) | (Fill(31, !f1_shift_2B) & f1pc)
-
-  f1pc_in := Mux1H(Seq(fetch_to_f1.asBool->io.ifu_fetch_pc,
-    shift_f2_f1.asBool->f2pc,
-    (!fetch_to_f1 & !shift_f2_f1).asBool -> sf1pc))
-
-  f0pc_in := Mux1H(Seq(fetch_to_f0.asBool->io.ifu_fetch_pc,
-                       shift_f2_f0.asBool->f2pc,
-                       shift_f1_f0.asBool->sf1pc,
-                      (!fetch_to_f0 & !shift_f2_f0 & !shift_f1_f0).asBool->f0pc_plus1))
-
-  f2val_in := Mux1H(Seq((fetch_to_f2 & !io.exu_flush_final).asBool->io.ifu_fetch_val,
-                       (!fetch_to_f2 & !shift_f2_f1 & !shift_f2_f0 & !io.exu_flush_final).asBool->f2val))
-
-  sf1val := Mux1H(Seq(f1_shift_2B.asBool->f1val(1), !f1_shift_2B.asBool->f1val))
-
-  f1val_in := Mux1H(Seq(( fetch_to_f1 &                               !io.exu_flush_final).asBool -> io.ifu_fetch_val,
-                        (                shift_f2_f1 &                !io.exu_flush_final).asBool->f2val,
-                        (!fetch_to_f1 & !shift_f2_f1 & !shift_f1_f0 & !io.exu_flush_final).asBool->sf1val))
-
-  sf0val := Mux1H(Seq(shift_2B.asBool->Cat(0.U, f0val(1)),
-                (!shift_2B & !shift_4B).asBool->f0val))
-
-  f0val_in := Mux1H(Seq((fetch_to_f0 &                                !io.exu_flush_final).asBool->io.ifu_fetch_val,
-                        (                shift_f2_f0 &                !io.exu_flush_final).asBool->f2val,
-                        (                               shift_f1_f0 & !io.exu_flush_final).asBool->sf1val,
-                        (!fetch_to_f0 & !shift_f2_f0 & !shift_f1_f0 & !io.exu_flush_final).asBool->sf0val))
-
-  val qeff = Mux1H(Seq(qren(0).asBool->Cat(q1,q0),
-    qren(1).asBool->Cat(q2,q1),
-    qren(2).asBool->Cat(q0,q2)))
-  val (q1eff, q0eff) = (qeff(63,32), qeff(31,0))
-
-  q0final := Mux1H(Seq(q0sel(0).asBool->q0eff, q0sel(1).asBool->q0eff(31,16)))
-
-  q1final := Mux1H(Seq(q1sel(0).asBool->q1eff(15,0), q1sel(1).asBool->q1eff(31,16)))
-
-  // Alinging the data according to the boundary of PC
-  val aligndata = Mux1H(Seq(f0val(1).asBool -> q0final, (~f0val(1) & f0val(0)).asBool -> Cat(q1final(15,0),q0final(15,0))))
-
-  alignval := Mux1H(Seq(f0val(1).asBool->3.U, (!f0val(1) & f0val(0)) -> Cat(f1val(0),1.U)))
-
-  val alignicaf = Mux1H(Seq(f0val(1).asBool -> f0icaf, (~f0val(1) & f0val(0)).asBool -> Cat(f1icaf,f0icaf)))
-
-  val aligndbecc = Mux1H(Seq(f0val(1).asBool -> Fill(2,f0dbecc), (!f0val(1) & f0val(0)).asBool -> Cat(f1dbecc,f0dbecc)))
-
-  val alignbrend = Mux1H(Seq(f0val(1).asBool()->f0brend, (!f0val(1) & f0val(0)).asBool->Cat(f1brend(0),f0brend(0))))
-
-  val alignpc4 = Mux1H(Seq(f0val(1).asBool()->f0pc4, (!f0val(1) & f0val(0)).asBool->Cat(f1pc4(0),f0pc4(0))))
-
-  val alignret = Mux1H(Seq(f0val(1).asBool()->f0ret, (!f0val(1) & f0val(0)).asBool->Cat(f1ret(0),f0ret(0))))
-
-  val alignway = Mux1H(Seq(f0val(1).asBool()->f0way, (!f0val(1) & f0val(0)).asBool->Cat(f1way(0),f0way(0))))
-
-  val alignhist1 = Mux1H(Seq(f0val(1).asBool()->f0hist1, (!f0val(1) & f0val(0)).asBool->Cat(f1hist1(0),f0hist1(0))))
-
-  val alignhist0 = Mux1H(Seq(f0val(1).asBool()->f0hist0, (!f0val(1) & f0val(0)).asBool->Cat(f1hist0(0),f0hist0(0))))
-
-  val alignfromf1 = !f0val(1) & f0val(0)
-
-  val secondpc = Mux1H(Seq(f0val(1).asBool()->f0pc_plus1 , (!f0val(1) & f0val(0)).asBool->f1pc))
-
-  io.dec_aln.aln_ib.ifu_i0_pc := f0pc
-
-  val firstpc = f0pc
-
-  io.dec_aln.aln_ib.ifu_i0_pc4 := first4B
-
-  io.dec_aln.aln_dec.ifu_i0_cinst := aligndata(15,0)
-
-  // Instruction is compressed or not
-  first4B := aligndata(1,0) === 3.U
-
-  val first2B = ~first4B
-
-  io.dec_aln.aln_ib.ifu_i0_valid := Mux1H(Seq(first4B.asBool -> alignval(1), first2B.asBool -> alignval(0)))
-
-  io.dec_aln.aln_ib.ifu_i0_icaf := Mux1H(Seq(first4B.asBool -> alignicaf.orR, first2B.asBool -> alignicaf(0)))
-
-  io.dec_aln.aln_ib.ifu_i0_icaf_type := Mux((first4B & !f0val(1) & f0val(0) & !alignicaf(0) & !aligndbecc(0)).asBool, f1ictype, f0ictype)
-
-  val icaf_eff = alignicaf(1) | aligndbecc(1)
-
-  io.dec_aln.aln_ib.ifu_i0_icaf_second := first4B & icaf_eff & alignfromf1
-
-  io.dec_aln.aln_ib.ifu_i0_dbecc := Mux1H(Seq(first4B.asBool->aligndbecc.orR, first2B.asBool->aligndbecc(0)))
-
-  val ifirst = aligndata
-  // Expander from 16-bit to 32-bit
-  val decompressed = Module(new ifu_compress_ctl())
-
-  io.dec_aln.aln_ib.ifu_i0_instr := Mux1H(Seq(first4B.asBool -> ifirst, first2B.asBool -> decompressed.io.dout))
-
-  // Hashing the PC
-  val firstpc_hash =  btb_addr_hash(f0pc)
-
-  val secondpc_hash = btb_addr_hash(secondpc)
-
-  val firstbrtag_hash = if(BTB_BTAG_FOLD) btb_tag_hash_fold(firstpc) else btb_tag_hash(firstpc)
-
-  val secondbrtag_hash = if(BTB_BTAG_FOLD) btb_tag_hash_fold(secondpc) else btb_tag_hash(secondpc)
-
-  io.dec_aln.aln_ib.i0_brp.valid :=(first2B & alignbrend(0)) | (first4B & alignbrend(1)) | (first4B & alignval(1) & alignbrend(0))
-
-  io.dec_aln.aln_ib.i0_brp.bits.ret := (first2B & alignret(0)) | (first4B & alignret(1))
-
-  val i0_brp_pc4 = (first2B & alignpc4(0)) | (first4B & alignpc4(1))
-
-  io.dec_aln.aln_ib.i0_brp.bits.way := Mux((first2B | alignbrend(0)).asBool, alignway(0),  alignway(1))
-
-  io.dec_aln.aln_ib.i0_brp.bits.hist := Cat((first2B & alignhist1(0)) | (first4B & alignhist1(1)),
-    (first2B & alignhist0(0)) | (first4B & alignhist0(1)))
-
-  val i0_ends_f1 = first4B & alignfromf1
-  io.dec_aln.aln_ib.i0_brp.bits.toffset := Mux(i0_ends_f1.asBool, f1poffset, f0poffset)
-
-  io.dec_aln.aln_ib.i0_brp.bits.prett := Mux(i0_ends_f1.asBool, f1prett, f0prett)
-
-  io.dec_aln.aln_ib.i0_brp.bits.br_start_error  := (first4B & alignval(1) & alignbrend(0))
-
-  io.dec_aln.aln_ib.i0_brp.bits.bank            := Mux((first2B | alignbrend(0)).asBool, firstpc(0), secondpc(0))
-
-  io.dec_aln.aln_ib.i0_brp.bits.br_error := (io.dec_aln.aln_ib.i0_brp.valid &  i0_brp_pc4 &  first2B) | (io.dec_aln.aln_ib.i0_brp.valid & !i0_brp_pc4 &  first4B)
-
-  io.dec_aln.aln_ib.ifu_i0_bp_index := Mux((first2B | alignbrend(0)).asBool, firstpc_hash, secondpc_hash)
-
-  io.dec_aln.aln_ib.ifu_i0_bp_fghr := Mux((first4B & alignfromf1).asBool, f1fghr, f0fghr)
-
-  io.dec_aln.aln_ib.ifu_i0_bp_btag := Mux((first2B | alignbrend(0)).asBool, firstbrtag_hash, secondbrtag_hash)
-
-  decompressed.io.din := aligndata
-
-  val i0_shift = io.dec_aln.aln_dec.dec_i0_decode_d & ~error_stall
-
-  io.dec_aln.ifu_pmu_instr_aligned := i0_shift
-
-  shift_2B := i0_shift & first2B
-  shift_4B := i0_shift & first4B
-
-  f0_shift_2B := Mux1H(Seq(shift_2B.asBool -> f0val(0), shift_4B.asBool -> (f0val(0) & !f0val(1))))
-  f1_shift_2B :=  f0val(0) & !f0val(1) & shift_4B
-
-}
+//package ifu
+//import lib._
+//import chisel3._
+//import chisel3.util._
+//import include._
+//
+//class ifu_aln_ctl extends Module with lib with RequireAsyncReset {
+//  val io = IO(new Bundle{
+//    val scan_mode = Input(Bool())
+//    val active_clk              = Input(Clock())
+//    val ifu_async_error_start   = Input(Bool()) // Error coming from mem-ctl
+//    val iccm_rd_ecc_double_err  = Input(Bool()) // ICCM double error coming from mem-ctl
+//    val ic_access_fault_f       = Input(Bool()) // Access fault in I$
+//    val ic_access_fault_type_f  = Input(UInt(2.W)) // Type of access fault occured
+//    val ifu_bp_fghr_f           = Input(UInt(BHT_GHR_SIZE.W)) // Data coming from the branch predictor to put in the FP
+//    val ifu_bp_btb_target_f     = Input(UInt(31.W)) // Target for the instruction enqueue in the FP
+//    val ifu_bp_poffset_f        = Input(UInt(12.W)) // Offset to the current PC for branch
+//    val ifu_bp_hist0_f          = Input(UInt(2.W)) // History to EXU
+//    val ifu_bp_hist1_f          = Input(UInt(2.W)) // History to EXU
+//    val ifu_bp_pc4_f            = Input(UInt(2.W)) // PC4
+//    val ifu_bp_way_f            = Input(UInt(2.W)) // Way to help in miss prediction
+//    val ifu_bp_valid_f          = Input(UInt(2.W)) // Valid Branch prediction
+//    val ifu_bp_ret_f            = Input(UInt(2.W)) // BP ret
+//    val exu_flush_final         = Input(Bool()) // Miss prediction
+//    val dec_aln                 = new dec_aln() // Data going to the dec from the ALN
+//    val ifu_fetch_data_f        = Input(UInt(32.W)) // PC of the current instruction in the FP
+//    val ifu_fetch_val           = Input(UInt(2.W)) // PC boundary i.e 'x' of 2 or 4
+//    val ifu_fetch_pc            = Input(UInt(31.W)) // Current PC
+//   /////////////////////////////////////////////////
+//    val ifu_fb_consume1         = Output(Bool()) // FP used 1
+//    val ifu_fb_consume2         = Output(Bool()) // FP used 2
+//
+//  })
+//  val MHI = 46+BHT_GHR_SIZE // 54
+//  val MSIZE = 47+BHT_GHR_SIZE // 55
+//  val BRDATA_SIZE = 12
+//  val error_stall_in = WireInit(Bool(),0.U)
+//  val alignval = WireInit(UInt(2.W), 0.U)
+//  val q0final = WireInit(UInt(32.W), 0.U)
+//  val q1final = WireInit(UInt(16.W), 0.U)
+//  val wrptr_in = WireInit(UInt(2.W), init = 0.U)
+//  val rdptr_in = WireInit(UInt(2.W), init = 0.U)
+//
+//  val f2val_in = WireInit(UInt(2.W), init = 0.U)
+//  val f1val_in = WireInit(UInt(2.W), init = 0.U)
+//  val f0val_in = WireInit(UInt(2.W), init = 0.U)
+//
+//  val q2off_in = WireInit(UInt(1.W), init = 0.U)
+//  val q1off_in = WireInit(UInt(1.W), init = 0.U)
+//  val q0off_in = WireInit(UInt(1.W), init = 0.U)
+//
+//  val sf0_valid = WireInit(Bool(), init = 0.U)
+//  val sf1_valid = WireInit(Bool(), init = 0.U)
+//
+//  val f2_valid = WireInit(Bool(), init = 0.U)
+//  val ifvalid = WireInit(Bool(), init = 0.U)
+//  val shift_f2_f1 = WireInit(Bool(), init = 0.U)
+//  val shift_f2_f0 = WireInit(Bool(), init = 0.U)
+//  val shift_f1_f0 = WireInit(Bool(), init = 0.U)
+//
+//  val f0icaf = WireInit(Bool(), init = 0.U)
+//  val f1icaf = WireInit(Bool(), init = 0.U)
+//
+//  val sf0val = WireInit(UInt(2.W), 0.U)
+//  val sf1val = WireInit(UInt(2.W), 0.U)
+//
+//  val misc0 = WireInit(UInt((MHI+1).W), 0.U)
+//  val misc1 = WireInit(UInt((MHI+1).W), 0.U)
+//  val misc2 = WireInit(UInt((MHI+1).W), 0.U)
+//
+//  val brdata1 = WireInit(UInt(12.W), init = 0.U)
+//  val brdata0 = WireInit(UInt(12.W), init = 0.U)
+//  val brdata2 = WireInit(UInt(12.W), init = 0.U)
+//
+//  val q0 = WireInit(UInt(32.W), init = 0.U)
+//  val q1 = WireInit(UInt(32.W), init = 0.U)
+//  val q2 = WireInit(UInt(32.W), init = 0.U)
+//
+//  val f1pc_in = WireInit(UInt(31.W), 0.U)
+//  val f0pc_in = WireInit(UInt(31.W), 0.U)
+//  val error_stall = WireInit(Bool(), 0.U)
+//  val f2_wr_en = WireInit(Bool(), 0.U)
+//  val shift_4B = WireInit(Bool(), 0.U)
+//  val f1_shift_wr_en = WireInit(Bool(), 0.U)
+//  val f0_shift_wr_en = WireInit(Bool(), 0.U)
+//  val qwen = WireInit(UInt(3.W), 0.U)
+//  val brdata_in = WireInit(UInt(BRDATA_SIZE.W), 0.U)
+//  val misc_data_in = WireInit(UInt((MHI+1).W), 0.U)
+//
+//  val fetch_to_f0 = WireInit(Bool(), 0.U)
+//  val fetch_to_f1 = WireInit(Bool(), 0.U)
+//  val fetch_to_f2 = WireInit(Bool(), 0.U)
+//  val f1_shift_2B = WireInit(Bool(), 0.U)
+//  val first4B = WireInit(Bool(), 0.U)
+//  val shift_2B = WireInit(Bool(), 0.U)
+//  val f0_shift_2B = WireInit(Bool(), 0.U)
+//
+//  // Stall if there is an error in the instrucion
+//  error_stall_in := (error_stall | io.ifu_async_error_start) & !io.exu_flush_final
+//
+//  // Flop the stall until flush
+//  error_stall := withClock(io.active_clk) {RegNext(error_stall_in, init = 0.U)}
+//  // Write Ptr of the FP
+//  val wrptr = withClock(io.active_clk) {RegNext(wrptr_in, init = 0.U)}
+//  // Read Ptr of the FP
+//  val rdptr = withClock(io.active_clk) {RegNext(rdptr_in, init = 0.U)}
+//  // Fetch Instruction boundary
+//  val f2val = withClock(io.active_clk) {RegNext(f2val_in, init = 0.U)}
+//  val f1val = withClock(io.active_clk) {RegNext(f1val_in, init = 0.U)}
+//  val f0val = withClock(io.active_clk) {RegNext(f0val_in, init = 0.U)}
+//
+//  val q2off = withClock(io.active_clk) {RegNext(q2off_in, init = 0.U)}
+//  val q1off = withClock(io.active_clk) {RegNext(q1off_in, init = 0.U)}
+//  val q0off = withClock(io.active_clk) {RegNext(q0off_in, init = 0.U)}
+//  // Instrution PC to the FP
+//  val f2pc = rvdffe(io.ifu_fetch_pc, f2_wr_en.asBool, clock, io.scan_mode)
+//  val f1pc = rvdffe(f1pc_in, f1_shift_wr_en.asBool, clock, io.scan_mode)
+//  val f0pc = rvdffe(f0pc_in, f0_shift_wr_en.asBool, clock, io.scan_mode)
+//  // Branch data to the FP
+//  brdata2 := rvdffe(brdata_in, qwen(2), clock, io.scan_mode)
+//  brdata1 := rvdffe(brdata_in, qwen(1), clock, io.scan_mode)
+//  brdata0 := rvdffe(brdata_in, qwen(0), clock, io.scan_mode)
+//  // Miscalanious data to the FP including error's
+//  misc2 := rvdffe(misc_data_in, qwen(2), clock, io.scan_mode)
+//  misc1 := rvdffe(misc_data_in, qwen(1), clock, io.scan_mode)
+//  misc0 := rvdffe(misc_data_in, qwen(0), clock, io.scan_mode)
+//  // Instruction in the FP
+//  q2 := rvdffe(io.ifu_fetch_data_f, qwen(2), clock, io.scan_mode)
+//  q1 := rvdffe(io.ifu_fetch_data_f, qwen(1), clock, io.scan_mode)
+//  q0 := rvdffe(io.ifu_fetch_data_f, qwen(0), clock, io.scan_mode)
+//
+//  // Shift FP logic
+//  f2_wr_en       := fetch_to_f2
+//  f1_shift_wr_en := fetch_to_f1 | shift_f2_f1 | f1_shift_2B
+//  f0_shift_wr_en := fetch_to_f0 | shift_f2_f0 | shift_f1_f0 | shift_2B | shift_4B
+//  // FP read enable .. 3-bit for Implemenation of 1HMux
+//  val qren = Cat(rdptr === 2.U, rdptr === 1.U, rdptr === 0.U)
+//  // FP write enable .. 3-bit for Implemenation of 1HMux
+//  qwen := Cat(wrptr === 2.U & ifvalid, wrptr === 1.U & ifvalid, wrptr === 0.U & ifvalid)
+//
+//  // Read Pointer calculation
+//  // Next rdptr = # of consume + current ptr location (Rounding it from 2)
+//  rdptr_in := Mux1H(Seq((qren(0) & io.ifu_fb_consume1 & !io.exu_flush_final).asBool -> 1.U,
+//    (qren(1) & io.ifu_fb_consume1 & !io.exu_flush_final).asBool -> 2.U,
+//    (qren(2) & io.ifu_fb_consume1 & !io.exu_flush_final).asBool -> 0.U,
+//    (qren(0) & io.ifu_fb_consume2 & !io.exu_flush_final).asBool -> 2.U,
+//    (qren(1) & io.ifu_fb_consume2 & !io.exu_flush_final).asBool -> 0.U,
+//    (qren(2) & io.ifu_fb_consume2 & !io.exu_flush_final).asBool -> 1.U,
+//    (!io.ifu_fb_consume1 & !io.ifu_fb_consume2 & !io.exu_flush_final).asBool -> rdptr))
+//
+//  // As there is only 1 enqueue so each time move by 1
+//  wrptr_in := Mux1H(Seq((qwen(0) & !io.exu_flush_final).asBool -> 1.U,
+//    (qwen(1) & !io.exu_flush_final).asBool -> 2.U,
+//    (qwen(2) & !io.exu_flush_final).asBool -> 0.U,
+//    (!ifvalid & !io.exu_flush_final).asBool->wrptr))
+//
+//  q2off_in := Mux1H(Seq((!qwen(2) & (rdptr===2.U)).asBool->(q2off.asUInt | f0_shift_2B),
+//    (!qwen(2) & (rdptr===1.U)).asBool->(q2off.asUInt | f1_shift_2B),
+//    (!qwen(2) & (rdptr===0.U)).asBool->q2off))
+//
+//  q1off_in := Mux1H(Seq((!qwen(1) & (rdptr===1.U)).asBool->(q1off.asUInt | f0_shift_2B),
+//    (!qwen(1) & (rdptr===0.U)).asBool->(q1off.asUInt | f1_shift_2B),
+//    (!qwen(1) & (rdptr===2.U)).asBool->q1off))
+//
+//  q0off_in := Mux1H(Seq((!qwen(0) & (rdptr===0.U)).asBool -> (q0off.asUInt | f0_shift_2B),
+//                        (!qwen(0) & (rdptr===2.U)).asBool -> (q0off.asUInt | f1_shift_2B),
+//                        (!qwen(0) & (rdptr===1.U)).asBool ->  q0off))
+//
+//  val q0ptr = Mux1H(Seq((rdptr===0.U)->q0off,
+//    (rdptr===1.U)->q1off,
+//    (rdptr===2.U)->q2off))
+//
+//  val  q1ptr = Mux1H(Seq((rdptr===0.U) -> q1off, (rdptr === 1.U) -> q2off, (rdptr === 2.U) -> q0off))
+//
+//  val q0sel = Cat(q0ptr, !q0ptr)
+//
+//  val q1sel = Cat(q1ptr, !q1ptr)
+//  // Misc data error, access-fault, type of fault, target, offset and ghr value
+//  misc_data_in := Cat(io.iccm_rd_ecc_double_err, io.ic_access_fault_f, io.ic_access_fault_type_f,
+//    io.ifu_bp_btb_target_f, io.ifu_bp_poffset_f, io.ifu_bp_fghr_f)
+//
+//  val misceff = Mux1H(Seq(qren(0).asBool() -> Cat(misc1, misc0),
+//    qren(1).asBool()->Cat(misc2, misc1),
+//    qren(2).asBool()->Cat(misc0, misc2)))
+//
+//  val misc1eff = misceff(misceff.getWidth-1,MHI+1)
+//  val misc0eff = misceff(MHI, 0)
+//
+//
+//  val f1dbecc = misc1eff(misc1eff.getWidth-1)
+//  f1icaf := misc1eff(misc1eff.getWidth-2)
+//  val f1ictype = misc1eff(misc1eff.getWidth-3,misc1eff.getWidth-4)
+//  val f1prett = misc1eff(misc1eff.getWidth-5,misc1eff.getWidth-35)
+//  val f1poffset = misc1eff(BHT_GHR_SIZE+11, BHT_GHR_SIZE)
+//  val f1fghr = misc1eff(BHT_GHR_SIZE-1, 0)
+//
+//  val f0dbecc = misc0eff(misc1eff.getWidth-1)
+//  f0icaf := misc0eff(misc1eff.getWidth-2)
+//  val f0ictype = misc0eff(misc1eff.getWidth-3,misc1eff.getWidth-4)
+//  val f0prett = misc0eff(misc1eff.getWidth-5,misc1eff.getWidth-35)
+//  val f0poffset = misc0eff(BHT_GHR_SIZE+11, BHT_GHR_SIZE)
+//  val f0fghr = misc0eff(BHT_GHR_SIZE-1, 0)
+//
+//  // Branch information
+//  brdata_in := Cat(io.ifu_bp_hist1_f(1),io.ifu_bp_hist0_f(1),io.ifu_bp_pc4_f(1),io.ifu_bp_way_f(1),io.ifu_bp_valid_f(1),
+//    io.ifu_bp_ret_f(1), io.ifu_bp_hist1_f(0),io.ifu_bp_hist0_f(0),io.ifu_bp_pc4_f(0),io.ifu_bp_way_f(0),
+//    io.ifu_bp_valid_f(0),io.ifu_bp_ret_f(0))
+//  // Effective branch information
+//  val brdataeff = Mux1H(Seq(qren(0).asBool->Cat(brdata1,brdata0),
+//    qren(1).asBool->Cat(brdata2,brdata1),
+//    qren(2).asBool->Cat(brdata0,brdata2)))
+//
+//  val (brdata0eff,brdata1eff) = (brdataeff(11,0) , brdataeff(23,12))
+//
+//  val brdata0final = Mux1H(Seq(q0sel(0).asBool -> brdata0eff, q0sel(1).asBool -> brdata0eff(11,6)))
+//  val brdata1final = Mux1H(Seq(q1sel(0).asBool -> brdata1eff, q1sel(1).asBool -> brdata1eff(11,6)))
+//
+//  val f0ret = Cat(brdata0final(6),brdata0final(0))
+//  val f0brend = Cat(brdata0final(7),brdata0final(1))
+//  val f0way = Cat(brdata0final(8),brdata0final(2))
+//  val f0pc4 = Cat(brdata0final(9),brdata0final(3))
+//  val f0hist0 = Cat(brdata0final(10),brdata0final(4))
+//  val f0hist1 = Cat(brdata0final(11),brdata0final(5))
+//
+//  val f1ret = Cat(brdata1final(6),brdata1final(0))
+//  val f1brend = Cat(brdata1final(7),brdata1final(1))
+//  val f1way = Cat(brdata1final(8),brdata1final(2))
+//  val f1pc4 = Cat(brdata1final(9),brdata1final(3))
+//  val f1hist0 = Cat(brdata1final(10),brdata1final(4))
+//  val f1hist1 = Cat(brdata1final(11),brdata1final(5))
+//
+//
+//  f2_valid := f2val(0)
+//  sf1_valid := sf1val(0)
+//  sf0_valid := sf0val(0)
+//
+//  val consume_fb0 = !sf0val(0) & f0val(0)
+//  val consume_fb1 = !sf1val(0) & f1val(0)
+//
+//  // Depending on type of instruction and boundary determine how many FP to consume
+//  io.ifu_fb_consume1 := consume_fb0 & !consume_fb1 & !io.exu_flush_final
+//  io.ifu_fb_consume2 := consume_fb0 &  consume_fb1 & !io.exu_flush_final
+//
+//  ifvalid := io.ifu_fetch_val(0)
+//
+//  // Shift logic for each dequeue
+//  shift_f1_f0 := !sf0_valid &  sf1_valid
+//  shift_f2_f0 := !sf0_valid & !sf1_valid &  f2_valid
+//  shift_f2_f1 := !sf0_valid &  sf1_valid &  f2_valid
+//
+//  fetch_to_f0        :=  !sf0_valid & !sf1_valid & !f2_valid & ifvalid
+//  fetch_to_f1        := (!sf0_valid & !sf1_valid &  f2_valid & ifvalid)  |
+//                        (!sf0_valid &  sf1_valid & !f2_valid & ifvalid)  |
+//                        ( sf0_valid & !sf1_valid & !f2_valid & ifvalid)
+//
+//  fetch_to_f2        := (!sf0_valid &  sf1_valid &  f2_valid & ifvalid)  |
+//                        ( sf0_valid &  sf1_valid & !f2_valid & ifvalid)
+//
+//  val f0pc_plus1 = f0pc + 1.U
+//
+//  val f1pc_plus1 = f1pc + 1.U
+//
+//  val sf1pc = (Fill(31, f1_shift_2B) & f1pc_plus1) | (Fill(31, !f1_shift_2B) & f1pc)
+//
+//  f1pc_in := Mux1H(Seq(fetch_to_f1.asBool->io.ifu_fetch_pc,
+//    shift_f2_f1.asBool->f2pc,
+//    (!fetch_to_f1 & !shift_f2_f1).asBool -> sf1pc))
+//
+//  f0pc_in := Mux1H(Seq(fetch_to_f0.asBool->io.ifu_fetch_pc,
+//                       shift_f2_f0.asBool->f2pc,
+//                       shift_f1_f0.asBool->sf1pc,
+//                      (!fetch_to_f0 & !shift_f2_f0 & !shift_f1_f0).asBool->f0pc_plus1))
+//
+//  f2val_in := Mux1H(Seq((fetch_to_f2 & !io.exu_flush_final).asBool->io.ifu_fetch_val,
+//                       (!fetch_to_f2 & !shift_f2_f1 & !shift_f2_f0 & !io.exu_flush_final).asBool->f2val))
+//
+//  sf1val := Mux1H(Seq(f1_shift_2B.asBool->f1val(1), !f1_shift_2B.asBool->f1val))
+//
+//  f1val_in := Mux1H(Seq(( fetch_to_f1 &                               !io.exu_flush_final).asBool -> io.ifu_fetch_val,
+//                        (                shift_f2_f1 &                !io.exu_flush_final).asBool->f2val,
+//                        (!fetch_to_f1 & !shift_f2_f1 & !shift_f1_f0 & !io.exu_flush_final).asBool->sf1val))
+//
+//  sf0val := Mux1H(Seq(shift_2B.asBool->Cat(0.U, f0val(1)),
+//                (!shift_2B & !shift_4B).asBool->f0val))
+//
+//  f0val_in := Mux1H(Seq((fetch_to_f0 &                                !io.exu_flush_final).asBool->io.ifu_fetch_val,
+//                        (                shift_f2_f0 &                !io.exu_flush_final).asBool->f2val,
+//                        (                               shift_f1_f0 & !io.exu_flush_final).asBool->sf1val,
+//                        (!fetch_to_f0 & !shift_f2_f0 & !shift_f1_f0 & !io.exu_flush_final).asBool->sf0val))
+//
+//  val qeff = Mux1H(Seq(qren(0).asBool->Cat(q1,q0),
+//    qren(1).asBool->Cat(q2,q1),
+//    qren(2).asBool->Cat(q0,q2)))
+//  val (q1eff, q0eff) = (qeff(63,32), qeff(31,0))
+//
+//  q0final := Mux1H(Seq(q0sel(0).asBool->q0eff, q0sel(1).asBool->q0eff(31,16)))
+//
+//  q1final := Mux1H(Seq(q1sel(0).asBool->q1eff(15,0), q1sel(1).asBool->q1eff(31,16)))
+//
+//  // Alinging the data according to the boundary of PC
+//  val aligndata = Mux1H(Seq(f0val(1).asBool -> q0final, (~f0val(1) & f0val(0)).asBool -> Cat(q1final(15,0),q0final(15,0))))
+//
+//  alignval := Mux1H(Seq(f0val(1).asBool->3.U, (!f0val(1) & f0val(0)) -> Cat(f1val(0),1.U)))
+//
+//  val alignicaf = Mux1H(Seq(f0val(1).asBool -> f0icaf, (~f0val(1) & f0val(0)).asBool -> Cat(f1icaf,f0icaf)))
+//
+//  val aligndbecc = Mux1H(Seq(f0val(1).asBool -> Fill(2,f0dbecc), (!f0val(1) & f0val(0)).asBool -> Cat(f1dbecc,f0dbecc)))
+//
+//  val alignbrend = Mux1H(Seq(f0val(1).asBool()->f0brend, (!f0val(1) & f0val(0)).asBool->Cat(f1brend(0),f0brend(0))))
+//
+//  val alignpc4 = Mux1H(Seq(f0val(1).asBool()->f0pc4, (!f0val(1) & f0val(0)).asBool->Cat(f1pc4(0),f0pc4(0))))
+//
+//  val alignret = Mux1H(Seq(f0val(1).asBool()->f0ret, (!f0val(1) & f0val(0)).asBool->Cat(f1ret(0),f0ret(0))))
+//
+//  val alignway = Mux1H(Seq(f0val(1).asBool()->f0way, (!f0val(1) & f0val(0)).asBool->Cat(f1way(0),f0way(0))))
+//
+//  val alignhist1 = Mux1H(Seq(f0val(1).asBool()->f0hist1, (!f0val(1) & f0val(0)).asBool->Cat(f1hist1(0),f0hist1(0))))
+//
+//  val alignhist0 = Mux1H(Seq(f0val(1).asBool()->f0hist0, (!f0val(1) & f0val(0)).asBool->Cat(f1hist0(0),f0hist0(0))))
+//
+//  val alignfromf1 = !f0val(1) & f0val(0)
+//
+//  val secondpc = Mux1H(Seq(f0val(1).asBool()->f0pc_plus1 , (!f0val(1) & f0val(0)).asBool->f1pc))
+//
+//  io.dec_aln.aln_ib.ifu_i0_pc := f0pc
+//
+//  val firstpc = f0pc
+//
+//  io.dec_aln.aln_ib.ifu_i0_pc4 := first4B
+//
+//  io.dec_aln.aln_dec.ifu_i0_cinst := aligndata(15,0)
+//
+//  // Instruction is compressed or not
+//  first4B := aligndata(1,0) === 3.U
+//
+//  val first2B = ~first4B
+//
+//  io.dec_aln.aln_ib.ifu_i0_valid := Mux1H(Seq(first4B.asBool -> alignval(1), first2B.asBool -> alignval(0)))
+//
+//  io.dec_aln.aln_ib.ifu_i0_icaf := Mux1H(Seq(first4B.asBool -> alignicaf.orR, first2B.asBool -> alignicaf(0)))
+//
+//  io.dec_aln.aln_ib.ifu_i0_icaf_type := Mux((first4B & !f0val(1) & f0val(0) & !alignicaf(0) & !aligndbecc(0)).asBool, f1ictype, f0ictype)
+//
+//  val icaf_eff = alignicaf(1) | aligndbecc(1)
+//
+//  io.dec_aln.aln_ib.ifu_i0_icaf_second := first4B & icaf_eff & alignfromf1
+//
+//  io.dec_aln.aln_ib.ifu_i0_dbecc := Mux1H(Seq(first4B.asBool->aligndbecc.orR, first2B.asBool->aligndbecc(0)))
+//
+//  val ifirst = aligndata
+//  // Expander from 16-bit to 32-bit
+//  val decompressed = Module(new ifu_compress_ctl())
+//
+//  io.dec_aln.aln_ib.ifu_i0_instr := Mux1H(Seq(first4B.asBool -> ifirst, first2B.asBool -> decompressed.io.dout))
+//
+//  // Hashing the PC
+//  val firstpc_hash =  btb_addr_hash(f0pc)
+//
+//  val secondpc_hash = btb_addr_hash(secondpc)
+//
+//  val firstbrtag_hash = if(BTB_BTAG_FOLD) btb_tag_hash_fold(firstpc) else btb_tag_hash(firstpc)
+//
+//  val secondbrtag_hash = if(BTB_BTAG_FOLD) btb_tag_hash_fold(secondpc) else btb_tag_hash(secondpc)
+//
+//  io.dec_aln.aln_ib.i0_brp.valid :=(first2B & alignbrend(0)) | (first4B & alignbrend(1)) | (first4B & alignval(1) & alignbrend(0))
+//
+//  io.dec_aln.aln_ib.i0_brp.bits.ret := (first2B & alignret(0)) | (first4B & alignret(1))
+//
+//  val i0_brp_pc4 = (first2B & alignpc4(0)) | (first4B & alignpc4(1))
+//
+//  io.dec_aln.aln_ib.i0_brp.bits.way := Mux((first2B | alignbrend(0)).asBool, alignway(0),  alignway(1))
+//
+//  io.dec_aln.aln_ib.i0_brp.bits.hist := Cat((first2B & alignhist1(0)) | (first4B & alignhist1(1)),
+//    (first2B & alignhist0(0)) | (first4B & alignhist0(1)))
+//
+//  val i0_ends_f1 = first4B & alignfromf1
+//  io.dec_aln.aln_ib.i0_brp.bits.toffset := Mux(i0_ends_f1.asBool, f1poffset, f0poffset)
+//
+//  io.dec_aln.aln_ib.i0_brp.bits.prett := Mux(i0_ends_f1.asBool, f1prett, f0prett)
+//
+//  io.dec_aln.aln_ib.i0_brp.bits.br_start_error  := (first4B & alignval(1) & alignbrend(0))
+//
+//  io.dec_aln.aln_ib.i0_brp.bits.bank            := Mux((first2B | alignbrend(0)).asBool, firstpc(0), secondpc(0))
+//
+//  io.dec_aln.aln_ib.i0_brp.bits.br_error := (io.dec_aln.aln_ib.i0_brp.valid &  i0_brp_pc4 &  first2B) | (io.dec_aln.aln_ib.i0_brp.valid & !i0_brp_pc4 &  first4B)
+//
+//  io.dec_aln.aln_ib.ifu_i0_bp_index := Mux((first2B | alignbrend(0)).asBool, firstpc_hash, secondpc_hash)
+//
+//  io.dec_aln.aln_ib.ifu_i0_bp_fghr := Mux((first4B & alignfromf1).asBool, f1fghr, f0fghr)
+//
+//  io.dec_aln.aln_ib.ifu_i0_bp_btag := Mux((first2B | alignbrend(0)).asBool, firstbrtag_hash, secondbrtag_hash)
+//
+//  decompressed.io.din := aligndata
+//
+//  val i0_shift = io.dec_aln.aln_dec.dec_i0_decode_d & ~error_stall
+//
+//  io.dec_aln.ifu_pmu_instr_aligned := i0_shift
+//
+//  shift_2B := i0_shift & first2B
+//  shift_4B := i0_shift & first4B
+//
+//  f0_shift_2B := Mux1H(Seq(shift_2B.asBool -> f0val(0), shift_4B.asBool -> (f0val(0) & !f0val(1))))
+//  f1_shift_2B :=  f0val(0) & !f0val(1) & shift_4B
+//
+//}
diff --git a/src/main/scala/include/bundle.scala b/src/main/scala/include/bundle.scala
index 91bf90bb..1599b4f6 100644
--- a/src/main/scala/include/bundle.scala
+++ b/src/main/scala/include/bundle.scala
@@ -258,7 +258,7 @@ class aln_ib extends Bundle with lib{
   val i0_brp                  = Valid(new br_pkt_t)
 }
 class aln_dec extends Bundle{
-  val dec_i0_decode_d = Input(Bool()) // Dec
+  //val dec_i0_decode_d         = Input(Bool()) // Dec
   val ifu_i0_cinst            = Output(UInt(16.W)) // Dec
 }
 class dec_aln extends Bundle with lib {
diff --git a/target/scala-2.12/classes/dec/dec.class b/target/scala-2.12/classes/dec/dec.class
index 7d089628..2e2196e8 100644
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diff --git a/target/scala-2.12/classes/dec/dec_decode_ctl$$anon$1.class b/target/scala-2.12/classes/dec/dec_decode_ctl$$anon$1.class
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diff --git a/target/scala-2.12/classes/ifu/ifu_aln_ctl$$anon$1.class b/target/scala-2.12/classes/ifu/ifu_aln_ctl$$anon$1.class
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diff --git a/target/scala-2.12/classes/include/aln_dec.class b/target/scala-2.12/classes/include/aln_dec.class
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