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AHB/AXI updated

This commit is contained in:
​Laraib Khan 2021-01-15 10:32:49 +05:00
parent 43cddfd8b7
commit 81f85d455b
6 changed files with 558 additions and 647 deletions
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672
ahb_to_axi4.fir
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@ -138,392 +138,332 @@ circuit ahb_to_axi4 :
buf_state_en <= UInt<1>("h00") buf_state_en <= UInt<1>("h00")
wire buf_read_error_in : UInt<1> wire buf_read_error_in : UInt<1>
buf_read_error_in <= UInt<1>("h00") buf_read_error_in <= UInt<1>("h00")
wire buf_read_error : UInt<1> node ahb_hready = and(io.ahb.sig.in.hready, io.ahb.hreadyin) @[ahb_to_axi4.scala 27:50]
buf_read_error <= UInt<1>("h00") node _T_1 = bits(io.ahb.hsel, 0, 0) @[Bitwise.scala 72:15]
wire buf_rdata : UInt<64> node _T_2 = mux(_T_1, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
buf_rdata <= UInt<64>("h00") node _T_3 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 28:72]
wire ahb_hready : UInt<1> node ahb_htrans_in = and(_T_2, _T_3) @[ahb_to_axi4.scala 28:49]
ahb_hready <= UInt<1>("h00")
wire ahb_hready_q : UInt<1>
ahb_hready_q <= UInt<1>("h00")
wire ahb_htrans_in : UInt<2>
ahb_htrans_in <= UInt<2>("h00")
wire ahb_htrans_q : UInt<2>
ahb_htrans_q <= UInt<2>("h00")
wire ahb_hsize_q : UInt<3>
ahb_hsize_q <= UInt<3>("h00")
wire ahb_hwrite_q : UInt<1>
ahb_hwrite_q <= UInt<1>("h00")
wire ahb_haddr_q : UInt<32>
ahb_haddr_q <= UInt<32>("h00")
wire ahb_hwdata_q : UInt<64> wire ahb_hwdata_q : UInt<64>
ahb_hwdata_q <= UInt<64>("h00") ahb_hwdata_q <= UInt<64>("h00")
wire ahb_hresp_q : UInt<1>
ahb_hresp_q <= UInt<1>("h00")
wire buf_rdata_en : UInt<1> wire buf_rdata_en : UInt<1>
buf_rdata_en <= UInt<1>("h00") buf_rdata_en <= UInt<1>("h00")
wire ahb_addr_clk_en : UInt<1> wire bus_clk : Clock @[ahb_to_axi4.scala 33:33]
ahb_addr_clk_en <= UInt<1>("h00") wire ahb_addr_clk : Clock @[ahb_to_axi4.scala 34:33]
wire buf_rdata_clk_en : UInt<1> wire buf_rdata_clk : Clock @[ahb_to_axi4.scala 35:33]
buf_rdata_clk_en <= UInt<1>("h00") node _T_4 = bits(io.ahb.sig.out.htrans, 1, 1) @[ahb_to_axi4.scala 36:80]
wire bus_clk : Clock @[ahb_to_axi4.scala 43:33] node _T_5 = and(ahb_hready, _T_4) @[ahb_to_axi4.scala 36:57]
wire ahb_addr_clk : Clock @[ahb_to_axi4.scala 44:33] node ahb_addr_clk_en = and(io.bus_clk_en, _T_5) @[ahb_to_axi4.scala 36:43]
wire buf_rdata_clk : Clock @[ahb_to_axi4.scala 45:33] node buf_rdata_clk_en = and(io.bus_clk_en, buf_rdata_en) @[ahb_to_axi4.scala 37:43]
node _T_6 = asClock(UInt<1>("h00")) @[ahb_to_axi4.scala 40:33]
bus_clk <= _T_6 @[ahb_to_axi4.scala 40:19]
node _T_7 = asClock(UInt<1>("h00")) @[ahb_to_axi4.scala 41:33]
ahb_addr_clk <= _T_7 @[ahb_to_axi4.scala 41:19]
node _T_8 = asClock(UInt<1>("h00")) @[ahb_to_axi4.scala 42:33]
buf_rdata_clk <= _T_8 @[ahb_to_axi4.scala 42:19]
reg buf_read_error : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when io.bus_clk_en : @[Reg.scala 28:19]
buf_read_error <= buf_read_error_in @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
reg buf_rdata : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when buf_rdata_clk_en : @[Reg.scala 28:19]
buf_rdata <= io.axi.r.bits.data @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
reg ahb_hresp_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when io.bus_clk_en : @[Reg.scala 28:19]
ahb_hresp_q <= io.ahb.sig.in.hresp @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
reg ahb_hsize_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when ahb_addr_clk_en : @[Reg.scala 28:19]
ahb_hsize_q <= io.ahb.sig.out.hsize @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
reg ahb_hwrite_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when ahb_addr_clk_en : @[Reg.scala 28:19]
ahb_hwrite_q <= io.ahb.sig.out.hwrite @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
reg ahb_haddr_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when ahb_addr_clk_en : @[Reg.scala 28:19]
ahb_haddr_q <= io.ahb.sig.out.haddr @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
reg ahb_hready_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when io.bus_clk_en : @[Reg.scala 28:19]
ahb_hready_q <= ahb_hready @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
reg ahb_htrans_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when io.bus_clk_en : @[Reg.scala 28:19]
ahb_htrans_q <= ahb_htrans_in @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
wire cmdbuf_wr_en : UInt<1> wire cmdbuf_wr_en : UInt<1>
cmdbuf_wr_en <= UInt<1>("h00") cmdbuf_wr_en <= UInt<1>("h00")
wire cmdbuf_rst : UInt<1> node _T_9 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 60:70]
cmdbuf_rst <= UInt<1>("h00") node _T_10 = and(io.bus_clk_en, _T_9) @[lib.scala 383:57]
wire cmdbuf_full : UInt<1> reg cmdbuf_write : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
cmdbuf_full <= UInt<1>("h00") when _T_10 : @[Reg.scala 28:19]
wire cmdbuf_vld : UInt<1> cmdbuf_write <= ahb_hwrite_q @[Reg.scala 28:23]
cmdbuf_vld <= UInt<1>("h00")
wire cmdbuf_write : UInt<1>
cmdbuf_write <= UInt<1>("h00")
wire cmdbuf_size : UInt<2>
cmdbuf_size <= UInt<2>("h00")
wire cmdbuf_wstrb : UInt<8>
cmdbuf_wstrb <= UInt<8>("h00")
wire cmdbuf_addr : UInt<32>
cmdbuf_addr <= UInt<32>("h00")
wire cmdbuf_wdata : UInt<64>
cmdbuf_wdata <= UInt<64>("h00")
node _T_1 = bits(ahb_haddr_q, 31, 28) @[lib.scala 84:25]
node ahb_addr_in_dccm_region_nc = eq(_T_1, UInt<4>("h0f")) @[lib.scala 84:47]
node _T_2 = bits(ahb_haddr_q, 31, 16) @[lib.scala 87:14]
node ahb_addr_in_dccm = eq(_T_2, UInt<16>("h0f004")) @[lib.scala 87:29]
node _T_3 = bits(ahb_haddr_q, 31, 28) @[lib.scala 84:25]
node ahb_addr_in_iccm_region_nc = eq(_T_3, UInt<4>("h0e")) @[lib.scala 84:47]
node _T_4 = bits(ahb_haddr_q, 31, 16) @[lib.scala 87:14]
node ahb_addr_in_iccm = eq(_T_4, UInt<16>("h0ee00")) @[lib.scala 87:29]
node _T_5 = bits(ahb_haddr_q, 31, 28) @[lib.scala 84:25]
node ahb_addr_in_pic_region_nc = eq(_T_5, UInt<4>("h0f")) @[lib.scala 84:47]
node _T_6 = bits(ahb_haddr_q, 31, 15) @[lib.scala 87:14]
node ahb_addr_in_pic = eq(_T_6, UInt<17>("h01e018")) @[lib.scala 87:29]
wire buf_state : UInt<2>
buf_state <= UInt<2>("h00")
wire buf_nxtstate : UInt<2>
buf_nxtstate <= UInt<2>("h00")
buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 66:31]
buf_state_en <= UInt<1>("h00") @[ahb_to_axi4.scala 67:31]
buf_rdata_en <= UInt<1>("h00") @[ahb_to_axi4.scala 68:31]
buf_read_error_in <= UInt<1>("h00") @[ahb_to_axi4.scala 69:31]
cmdbuf_wr_en <= UInt<1>("h00") @[ahb_to_axi4.scala 70:31]
node _T_7 = eq(UInt<2>("h00"), buf_state) @[Conditional.scala 37:30]
when _T_7 : @[Conditional.scala 40:58]
node _T_8 = mux(io.ahb.sig.out.hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 74:26]
buf_nxtstate <= _T_8 @[ahb_to_axi4.scala 74:20]
node _T_9 = bits(io.ahb.sig.out.htrans, 1, 1) @[ahb_to_axi4.scala 75:57]
node _T_10 = and(ahb_hready, _T_9) @[ahb_to_axi4.scala 75:34]
node _T_11 = and(_T_10, io.ahb.hsel) @[ahb_to_axi4.scala 75:61]
buf_state_en <= _T_11 @[ahb_to_axi4.scala 75:20]
skip @[Conditional.scala 40:58]
else : @[Conditional.scala 39:67]
node _T_12 = eq(UInt<2>("h01"), buf_state) @[Conditional.scala 37:30]
when _T_12 : @[Conditional.scala 39:67]
node _T_13 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 78:72]
node _T_14 = eq(_T_13, UInt<1>("h00")) @[ahb_to_axi4.scala 78:79]
node _T_15 = or(io.ahb.sig.in.hresp, _T_14) @[ahb_to_axi4.scala 78:48]
node _T_16 = eq(io.ahb.hsel, UInt<1>("h00")) @[ahb_to_axi4.scala 78:93]
node _T_17 = or(_T_15, _T_16) @[ahb_to_axi4.scala 78:91]
node _T_18 = bits(_T_17, 0, 0) @[ahb_to_axi4.scala 78:107]
node _T_19 = mux(io.ahb.sig.out.hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 78:124]
node _T_20 = mux(_T_18, UInt<2>("h00"), _T_19) @[ahb_to_axi4.scala 78:26]
buf_nxtstate <= _T_20 @[ahb_to_axi4.scala 78:20]
node _T_21 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 79:24]
node _T_22 = or(_T_21, io.ahb.sig.in.hresp) @[ahb_to_axi4.scala 79:37]
buf_state_en <= _T_22 @[ahb_to_axi4.scala 79:20]
node _T_23 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 80:23]
node _T_24 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 80:85]
node _T_25 = eq(_T_24, UInt<2>("h01")) @[ahb_to_axi4.scala 80:92]
node _T_26 = and(_T_25, io.ahb.hsel) @[ahb_to_axi4.scala 80:110]
node _T_27 = or(io.ahb.sig.in.hresp, _T_26) @[ahb_to_axi4.scala 80:60]
node _T_28 = eq(_T_27, UInt<1>("h00")) @[ahb_to_axi4.scala 80:38]
node _T_29 = and(_T_23, _T_28) @[ahb_to_axi4.scala 80:36]
cmdbuf_wr_en <= _T_29 @[ahb_to_axi4.scala 80:20]
skip @[Conditional.scala 39:67]
else : @[Conditional.scala 39:67]
node _T_30 = eq(UInt<2>("h02"), buf_state) @[Conditional.scala 37:30]
when _T_30 : @[Conditional.scala 39:67]
node _T_31 = mux(io.ahb.sig.in.hresp, UInt<2>("h00"), UInt<2>("h03")) @[ahb_to_axi4.scala 83:26]
buf_nxtstate <= _T_31 @[ahb_to_axi4.scala 83:20]
node _T_32 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 84:24]
node _T_33 = or(_T_32, io.ahb.sig.in.hresp) @[ahb_to_axi4.scala 84:37]
buf_state_en <= _T_33 @[ahb_to_axi4.scala 84:20]
node _T_34 = eq(io.ahb.sig.in.hresp, UInt<1>("h00")) @[ahb_to_axi4.scala 85:23]
node _T_35 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 85:46]
node _T_36 = and(_T_34, _T_35) @[ahb_to_axi4.scala 85:44]
cmdbuf_wr_en <= _T_36 @[ahb_to_axi4.scala 85:20]
skip @[Conditional.scala 39:67]
else : @[Conditional.scala 39:67]
node _T_37 = eq(UInt<2>("h03"), buf_state) @[Conditional.scala 37:30]
when _T_37 : @[Conditional.scala 39:67]
buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 88:20]
node _T_38 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 89:40]
node _T_39 = and(io.axi.r.valid, _T_38) @[ahb_to_axi4.scala 89:38]
buf_state_en <= _T_39 @[ahb_to_axi4.scala 89:20]
buf_rdata_en <= buf_state_en @[ahb_to_axi4.scala 90:20]
node _T_40 = bits(io.axi.r.bits.resp, 1, 0) @[ahb_to_axi4.scala 91:61]
node _T_41 = orr(_T_40) @[ahb_to_axi4.scala 91:68]
node _T_42 = and(buf_state_en, _T_41) @[ahb_to_axi4.scala 91:41]
buf_read_error_in <= _T_42 @[ahb_to_axi4.scala 91:25]
skip @[Conditional.scala 39:67]
node _T_43 = bits(buf_state_en, 0, 0) @[ahb_to_axi4.scala 94:78]
node _T_44 = and(io.bus_clk_en, _T_43) @[lib.scala 383:57]
reg _T_45 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_44 : @[Reg.scala 28:19]
_T_45 <= buf_nxtstate @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
buf_state <= _T_45 @[ahb_to_axi4.scala 94:31] node _T_11 = and(io.axi.aw.valid, io.axi.aw.ready) @[ahb_to_axi4.scala 61:44]
node _T_46 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 96:54] node _T_12 = and(io.axi.ar.valid, io.axi.ar.ready) @[ahb_to_axi4.scala 61:82]
node _T_47 = eq(_T_46, UInt<1>("h00")) @[ahb_to_axi4.scala 96:60] node _T_13 = or(_T_11, _T_12) @[ahb_to_axi4.scala 61:63]
node _T_48 = bits(_T_47, 0, 0) @[Bitwise.scala 72:15] node _T_14 = eq(cmdbuf_wr_en, UInt<1>("h00")) @[ahb_to_axi4.scala 61:104]
node _T_49 = mux(_T_48, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] node _T_15 = and(_T_13, _T_14) @[ahb_to_axi4.scala 61:102]
node _T_50 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 96:92] node _T_16 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 61:144]
node _T_51 = dshl(UInt<1>("h01"), _T_50) @[ahb_to_axi4.scala 96:78] node _T_17 = and(io.ahb.sig.in.hresp, _T_16) @[ahb_to_axi4.scala 61:142]
node _T_52 = and(_T_49, _T_51) @[ahb_to_axi4.scala 96:70] node cmdbuf_rst = or(_T_15, _T_17) @[ahb_to_axi4.scala 61:119]
node _T_53 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 97:24] node _T_18 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 62:64]
node _T_54 = eq(_T_53, UInt<1>("h01")) @[ahb_to_axi4.scala 97:30] wire cmdbuf_vld : UInt @[lib.scala 389:21]
node _T_55 = bits(_T_54, 0, 0) @[Bitwise.scala 72:15] node _T_19 = eq(cmdbuf_rst, UInt<1>("h00")) @[lib.scala 391:73]
node _T_56 = mux(_T_55, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] node _T_20 = and(UInt<1>("h01"), _T_19) @[lib.scala 391:53]
node _T_57 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 97:62] node _T_21 = or(_T_18, cmdbuf_rst) @[lib.scala 391:92]
node _T_58 = dshl(UInt<2>("h03"), _T_57) @[ahb_to_axi4.scala 97:48] node _T_22 = and(_T_21, io.bus_clk_en) @[lib.scala 391:99]
node _T_59 = and(_T_56, _T_58) @[ahb_to_axi4.scala 97:40] node _T_23 = bits(_T_22, 0, 0) @[lib.scala 8:44]
node _T_60 = or(_T_52, _T_59) @[ahb_to_axi4.scala 96:109] reg _T_24 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
node _T_61 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 98:24] when _T_23 : @[Reg.scala 28:19]
node _T_62 = eq(_T_61, UInt<2>("h02")) @[ahb_to_axi4.scala 98:30] _T_24 <= _T_20 @[Reg.scala 28:23]
node _T_63 = bits(_T_62, 0, 0) @[Bitwise.scala 72:15]
node _T_64 = mux(_T_63, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
node _T_65 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 98:62]
node _T_66 = dshl(UInt<4>("h0f"), _T_65) @[ahb_to_axi4.scala 98:48]
node _T_67 = and(_T_64, _T_66) @[ahb_to_axi4.scala 98:40]
node _T_68 = or(_T_60, _T_67) @[ahb_to_axi4.scala 97:79]
node _T_69 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 99:24]
node _T_70 = eq(_T_69, UInt<2>("h03")) @[ahb_to_axi4.scala 99:30]
node _T_71 = bits(_T_70, 0, 0) @[Bitwise.scala 72:15]
node _T_72 = mux(_T_71, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
node _T_73 = and(_T_72, UInt<8>("h0ff")) @[ahb_to_axi4.scala 99:40]
node _T_74 = or(_T_68, _T_73) @[ahb_to_axi4.scala 98:79]
master_wstrb <= _T_74 @[ahb_to_axi4.scala 96:31]
node _T_75 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 102:80]
node _T_76 = and(ahb_hresp_q, _T_75) @[ahb_to_axi4.scala 102:78]
node _T_77 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 102:98]
node _T_78 = eq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 102:124]
node _T_79 = or(_T_77, _T_78) @[ahb_to_axi4.scala 102:111]
node _T_80 = eq(buf_state, UInt<2>("h02")) @[ahb_to_axi4.scala 102:149]
node _T_81 = eq(buf_state, UInt<2>("h03")) @[ahb_to_axi4.scala 102:168]
node _T_82 = or(_T_80, _T_81) @[ahb_to_axi4.scala 102:156]
node _T_83 = eq(_T_82, UInt<1>("h00")) @[ahb_to_axi4.scala 102:137]
node _T_84 = and(_T_79, _T_83) @[ahb_to_axi4.scala 102:135]
node _T_85 = eq(buf_read_error, UInt<1>("h00")) @[ahb_to_axi4.scala 102:181]
node _T_86 = and(_T_84, _T_85) @[ahb_to_axi4.scala 102:179]
node _T_87 = mux(io.ahb.sig.in.hresp, _T_76, _T_86) @[ahb_to_axi4.scala 102:44]
io.ahb.sig.in.hready <= _T_87 @[ahb_to_axi4.scala 102:38]
node _T_88 = and(io.ahb.sig.in.hready, io.ahb.hreadyin) @[ahb_to_axi4.scala 103:55]
ahb_hready <= _T_88 @[ahb_to_axi4.scala 103:31]
node _T_89 = bits(io.ahb.hsel, 0, 0) @[Bitwise.scala 72:15]
node _T_90 = mux(_T_89, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
node _T_91 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 104:77]
node _T_92 = and(_T_90, _T_91) @[ahb_to_axi4.scala 104:54]
ahb_htrans_in <= _T_92 @[ahb_to_axi4.scala 104:31]
node _T_93 = bits(buf_rdata, 63, 0) @[ahb_to_axi4.scala 105:50]
io.ahb.sig.in.hrdata <= _T_93 @[ahb_to_axi4.scala 105:38]
node _T_94 = bits(ahb_htrans_q, 1, 0) @[ahb_to_axi4.scala 106:55]
node _T_95 = neq(_T_94, UInt<1>("h00")) @[ahb_to_axi4.scala 106:61]
node _T_96 = neq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 106:83]
node _T_97 = and(_T_95, _T_96) @[ahb_to_axi4.scala 106:70]
node _T_98 = or(ahb_addr_in_dccm, ahb_addr_in_iccm) @[ahb_to_axi4.scala 107:26]
node _T_99 = eq(_T_98, UInt<1>("h00")) @[ahb_to_axi4.scala 107:7]
node _T_100 = and(ahb_addr_in_dccm, ahb_hwrite_q) @[ahb_to_axi4.scala 108:46]
node _T_101 = or(ahb_addr_in_iccm, _T_100) @[ahb_to_axi4.scala 108:26]
node _T_102 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 108:80]
node _T_103 = eq(_T_102, UInt<2>("h02")) @[ahb_to_axi4.scala 108:86]
node _T_104 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 108:109]
node _T_105 = eq(_T_104, UInt<2>("h03")) @[ahb_to_axi4.scala 108:115]
node _T_106 = or(_T_103, _T_105) @[ahb_to_axi4.scala 108:95]
node _T_107 = eq(_T_106, UInt<1>("h00")) @[ahb_to_axi4.scala 108:66]
node _T_108 = and(_T_101, _T_107) @[ahb_to_axi4.scala 108:64]
node _T_109 = or(_T_99, _T_108) @[ahb_to_axi4.scala 107:47]
node _T_110 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 109:20]
node _T_111 = eq(_T_110, UInt<1>("h01")) @[ahb_to_axi4.scala 109:26]
node _T_112 = bits(ahb_haddr_q, 0, 0) @[ahb_to_axi4.scala 109:48]
node _T_113 = and(_T_111, _T_112) @[ahb_to_axi4.scala 109:35]
node _T_114 = or(_T_109, _T_113) @[ahb_to_axi4.scala 108:126]
node _T_115 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 110:20]
node _T_116 = eq(_T_115, UInt<2>("h02")) @[ahb_to_axi4.scala 110:26]
node _T_117 = bits(ahb_haddr_q, 1, 0) @[ahb_to_axi4.scala 110:49]
node _T_118 = orr(_T_117) @[ahb_to_axi4.scala 110:56]
node _T_119 = and(_T_116, _T_118) @[ahb_to_axi4.scala 110:35]
node _T_120 = or(_T_114, _T_119) @[ahb_to_axi4.scala 109:55]
node _T_121 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 111:20]
node _T_122 = eq(_T_121, UInt<2>("h03")) @[ahb_to_axi4.scala 111:26]
node _T_123 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 111:49]
node _T_124 = orr(_T_123) @[ahb_to_axi4.scala 111:56]
node _T_125 = and(_T_122, _T_124) @[ahb_to_axi4.scala 111:35]
node _T_126 = or(_T_120, _T_125) @[ahb_to_axi4.scala 110:61]
node _T_127 = and(_T_97, _T_126) @[ahb_to_axi4.scala 106:94]
node _T_128 = or(_T_127, buf_read_error) @[ahb_to_axi4.scala 111:63]
node _T_129 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 113:20]
node _T_130 = and(ahb_hresp_q, _T_129) @[ahb_to_axi4.scala 113:18]
node _T_131 = or(_T_128, _T_130) @[ahb_to_axi4.scala 112:20]
io.ahb.sig.in.hresp <= _T_131 @[ahb_to_axi4.scala 106:38]
reg _T_132 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when buf_rdata_clk_en : @[Reg.scala 28:19]
_T_132 <= io.axi.r.bits.data @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
buf_rdata <= _T_132 @[ahb_to_axi4.scala 116:31] cmdbuf_vld <= _T_24 @[lib.scala 391:14]
reg _T_133 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] node _T_25 = and(io.axi.aw.valid, io.axi.aw.ready) @[ahb_to_axi4.scala 63:58]
when io.bus_clk_en : @[Reg.scala 28:19] node _T_26 = and(io.axi.ar.valid, io.axi.ar.ready) @[ahb_to_axi4.scala 63:96]
_T_133 <= buf_read_error_in @[Reg.scala 28:23] node _T_27 = or(_T_25, _T_26) @[ahb_to_axi4.scala 63:77]
node _T_28 = eq(_T_27, UInt<1>("h00")) @[ahb_to_axi4.scala 63:39]
node cmdbuf_full = and(cmdbuf_vld, _T_28) @[ahb_to_axi4.scala 63:37]
node _T_29 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 64:48]
node _T_30 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 64:74]
node _T_31 = and(io.bus_clk_en, _T_30) @[lib.scala 383:57]
reg cmdbuf_size : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_31 : @[Reg.scala 28:19]
cmdbuf_size <= _T_29 @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
buf_read_error <= _T_133 @[ahb_to_axi4.scala 117:31] node _T_32 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 65:70]
reg _T_134 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] node _T_33 = and(io.bus_clk_en, _T_32) @[lib.scala 383:57]
when io.bus_clk_en : @[Reg.scala 28:19] reg cmdbuf_wstrb : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
_T_134 <= io.ahb.sig.in.hresp @[Reg.scala 28:23] when _T_33 : @[Reg.scala 28:19]
cmdbuf_wstrb <= master_wstrb @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
ahb_hresp_q <= _T_134 @[ahb_to_axi4.scala 120:31] node _T_34 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 66:64]
reg _T_135 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] node _T_35 = and(_T_34, io.bus_clk_en) @[ahb_to_axi4.scala 66:66]
when io.bus_clk_en : @[Reg.scala 28:19]
_T_135 <= ahb_hready @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
ahb_hready_q <= _T_135 @[ahb_to_axi4.scala 121:31]
reg _T_136 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when io.bus_clk_en : @[Reg.scala 28:19]
_T_136 <= ahb_htrans_in @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
ahb_htrans_q <= _T_136 @[ahb_to_axi4.scala 122:31]
reg _T_137 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when ahb_addr_clk_en : @[Reg.scala 28:19]
_T_137 <= io.ahb.sig.out.hsize @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
ahb_hsize_q <= _T_137 @[ahb_to_axi4.scala 123:31]
reg _T_138 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when ahb_addr_clk_en : @[Reg.scala 28:19]
_T_138 <= io.ahb.sig.out.hwrite @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
ahb_hwrite_q <= _T_138 @[ahb_to_axi4.scala 124:31]
reg _T_139 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when ahb_addr_clk_en : @[Reg.scala 28:19]
_T_139 <= io.ahb.sig.out.haddr @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
ahb_haddr_q <= _T_139 @[ahb_to_axi4.scala 125:31]
node _T_140 = bits(io.ahb.sig.out.htrans, 1, 1) @[ahb_to_axi4.scala 128:81]
node _T_141 = and(ahb_hready, _T_140) @[ahb_to_axi4.scala 128:58]
node _T_142 = and(io.bus_clk_en, _T_141) @[ahb_to_axi4.scala 128:44]
ahb_addr_clk_en <= _T_142 @[ahb_to_axi4.scala 128:27]
node _T_143 = and(io.bus_clk_en, buf_rdata_en) @[ahb_to_axi4.scala 129:48]
buf_rdata_clk_en <= _T_143 @[ahb_to_axi4.scala 129:31]
node _T_144 = asClock(UInt<1>("h00")) @[ahb_to_axi4.scala 132:34]
bus_clk <= _T_144 @[ahb_to_axi4.scala 132:20]
node _T_145 = asClock(UInt<1>("h00")) @[ahb_to_axi4.scala 133:34]
ahb_addr_clk <= _T_145 @[ahb_to_axi4.scala 133:20]
node _T_146 = asClock(UInt<1>("h00")) @[ahb_to_axi4.scala 134:34]
buf_rdata_clk <= _T_146 @[ahb_to_axi4.scala 134:20]
node _T_147 = and(io.axi.aw.valid, io.axi.aw.ready) @[ahb_to_axi4.scala 141:53]
node _T_148 = and(io.axi.ar.valid, io.axi.ar.ready) @[ahb_to_axi4.scala 141:91]
node _T_149 = or(_T_147, _T_148) @[ahb_to_axi4.scala 141:72]
node _T_150 = eq(cmdbuf_wr_en, UInt<1>("h00")) @[ahb_to_axi4.scala 141:113]
node _T_151 = and(_T_149, _T_150) @[ahb_to_axi4.scala 141:111]
node _T_152 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 141:153]
node _T_153 = and(io.ahb.sig.in.hresp, _T_152) @[ahb_to_axi4.scala 141:151]
node _T_154 = or(_T_151, _T_153) @[ahb_to_axi4.scala 141:128]
cmdbuf_rst <= _T_154 @[ahb_to_axi4.scala 141:31]
node _T_155 = and(io.axi.aw.valid, io.axi.aw.ready) @[ahb_to_axi4.scala 142:67]
node _T_156 = and(io.axi.ar.valid, io.axi.ar.ready) @[ahb_to_axi4.scala 142:105]
node _T_157 = or(_T_155, _T_156) @[ahb_to_axi4.scala 142:86]
node _T_158 = eq(_T_157, UInt<1>("h00")) @[ahb_to_axi4.scala 142:48]
node _T_159 = and(cmdbuf_vld, _T_158) @[ahb_to_axi4.scala 142:46]
cmdbuf_full <= _T_159 @[ahb_to_axi4.scala 142:31]
node _T_160 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 144:73]
wire _T_161 : UInt @[lib.scala 389:21]
node _T_162 = eq(cmdbuf_rst, UInt<1>("h00")) @[lib.scala 391:75]
node _T_163 = and(UInt<1>("h01"), _T_162) @[lib.scala 391:53]
node _T_164 = or(_T_160, cmdbuf_rst) @[lib.scala 391:95]
node _T_165 = and(_T_164, io.bus_clk_en) @[lib.scala 391:102]
node _T_166 = bits(_T_165, 0, 0) @[lib.scala 8:44]
reg _T_167 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_166 : @[Reg.scala 28:19]
_T_167 <= _T_163 @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
_T_161 <= _T_167 @[lib.scala 391:14]
cmdbuf_vld <= _T_161 @[ahb_to_axi4.scala 144:31]
node _T_168 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 146:79]
node _T_169 = and(io.bus_clk_en, _T_168) @[lib.scala 383:57]
reg _T_170 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_169 : @[Reg.scala 28:19]
_T_170 <= ahb_hwrite_q @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
cmdbuf_write <= _T_170 @[ahb_to_axi4.scala 146:31]
node _T_171 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 147:57]
node _T_172 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 147:83]
node _T_173 = and(io.bus_clk_en, _T_172) @[lib.scala 383:57]
reg _T_174 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_173 : @[Reg.scala 28:19]
_T_174 <= _T_171 @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
cmdbuf_size <= _T_174 @[ahb_to_axi4.scala 147:31]
node _T_175 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 148:79]
node _T_176 = and(io.bus_clk_en, _T_175) @[lib.scala 383:57]
reg _T_177 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_176 : @[Reg.scala 28:19]
_T_177 <= master_wstrb @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
cmdbuf_wstrb <= _T_177 @[ahb_to_axi4.scala 148:31]
node _T_178 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 150:57]
node _T_179 = and(_T_178, io.bus_clk_en) @[ahb_to_axi4.scala 150:59]
inst rvclkhdr of rvclkhdr @[lib.scala 399:23] inst rvclkhdr of rvclkhdr @[lib.scala 399:23]
rvclkhdr.clock <= clock rvclkhdr.clock <= clock
rvclkhdr.reset <= reset rvclkhdr.reset <= reset
rvclkhdr.io.clk <= clock @[lib.scala 401:18] rvclkhdr.io.clk <= clock @[lib.scala 401:18]
rvclkhdr.io.en <= _T_179 @[lib.scala 402:17] rvclkhdr.io.en <= _T_35 @[lib.scala 402:17]
rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24]
reg _T_180 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] reg cmdbuf_addr : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_179 : @[Reg.scala 28:19] when _T_35 : @[Reg.scala 28:19]
_T_180 <= ahb_haddr_q @[Reg.scala 28:23] cmdbuf_addr <= ahb_haddr_q @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
cmdbuf_addr <= _T_180 @[ahb_to_axi4.scala 150:15] node _T_36 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 67:74]
node _T_181 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 151:68] node _T_37 = and(_T_36, io.bus_clk_en) @[ahb_to_axi4.scala 67:76]
node _T_182 = and(_T_181, io.bus_clk_en) @[ahb_to_axi4.scala 151:70]
inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 399:23] inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 399:23]
rvclkhdr_1.clock <= clock rvclkhdr_1.clock <= clock
rvclkhdr_1.reset <= reset rvclkhdr_1.reset <= reset
rvclkhdr_1.io.clk <= clock @[lib.scala 401:18] rvclkhdr_1.io.clk <= clock @[lib.scala 401:18]
rvclkhdr_1.io.en <= _T_182 @[lib.scala 402:17] rvclkhdr_1.io.en <= _T_37 @[lib.scala 402:17]
rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24]
reg _T_183 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] reg cmdbuf_wdata : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_182 : @[Reg.scala 28:19] when _T_37 : @[Reg.scala 28:19]
_T_183 <= io.ahb.sig.out.hwdata @[Reg.scala 28:23] cmdbuf_wdata <= io.ahb.sig.out.hwdata @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
cmdbuf_wdata <= _T_183 @[ahb_to_axi4.scala 151:16] node _T_38 = bits(ahb_haddr_q, 31, 28) @[lib.scala 84:25]
node _T_184 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 154:42] node ahb_addr_in_dccm_region_nc = eq(_T_38, UInt<4>("h0f")) @[lib.scala 84:47]
io.axi.aw.valid <= _T_184 @[ahb_to_axi4.scala 154:28] node _T_39 = bits(ahb_haddr_q, 31, 16) @[lib.scala 87:14]
io.axi.aw.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 155:33] node ahb_addr_in_dccm = eq(_T_39, UInt<16>("h0f004")) @[lib.scala 87:29]
io.axi.aw.bits.addr <= cmdbuf_addr @[ahb_to_axi4.scala 156:33] node _T_40 = bits(ahb_haddr_q, 31, 28) @[lib.scala 84:25]
node _T_185 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 157:59] node ahb_addr_in_iccm_region_nc = eq(_T_40, UInt<4>("h0e")) @[lib.scala 84:47]
node _T_186 = cat(UInt<1>("h00"), _T_185) @[Cat.scala 29:58] node _T_41 = bits(ahb_haddr_q, 31, 16) @[lib.scala 87:14]
io.axi.aw.bits.size <= _T_186 @[ahb_to_axi4.scala 157:33] node ahb_addr_in_iccm = eq(_T_41, UInt<16>("h0ee00")) @[lib.scala 87:29]
node _T_187 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] node _T_42 = bits(ahb_haddr_q, 31, 28) @[lib.scala 84:25]
io.axi.aw.bits.prot <= _T_187 @[ahb_to_axi4.scala 158:33] node ahb_addr_in_pic_region_nc = eq(_T_42, UInt<4>("h0f")) @[lib.scala 84:47]
node _T_188 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] node _T_43 = bits(ahb_haddr_q, 31, 15) @[lib.scala 87:14]
io.axi.aw.bits.len <= _T_188 @[ahb_to_axi4.scala 159:33] node ahb_addr_in_pic = eq(_T_43, UInt<17>("h01e018")) @[lib.scala 87:29]
io.axi.aw.bits.burst <= UInt<2>("h01") @[ahb_to_axi4.scala 160:33] wire buf_state : UInt<2>
node _T_189 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 162:42] buf_state <= UInt<2>("h00")
io.axi.w.valid <= _T_189 @[ahb_to_axi4.scala 162:28] wire buf_nxtstate : UInt<2>
io.axi.w.bits.data <= cmdbuf_wdata @[ahb_to_axi4.scala 163:33] buf_nxtstate <= UInt<2>("h00")
io.axi.w.bits.strb <= cmdbuf_wstrb @[ahb_to_axi4.scala 164:33] buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 76:31]
io.axi.w.bits.last <= UInt<1>("h01") @[ahb_to_axi4.scala 165:33] buf_state_en <= UInt<1>("h00") @[ahb_to_axi4.scala 77:31]
io.axi.b.ready <= UInt<1>("h01") @[ahb_to_axi4.scala 167:28] buf_rdata_en <= UInt<1>("h00") @[ahb_to_axi4.scala 78:31]
node _T_190 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 169:44] buf_read_error_in <= UInt<1>("h00") @[ahb_to_axi4.scala 79:31]
node _T_191 = and(cmdbuf_vld, _T_190) @[ahb_to_axi4.scala 169:42] cmdbuf_wr_en <= UInt<1>("h00") @[ahb_to_axi4.scala 80:31]
io.axi.ar.valid <= _T_191 @[ahb_to_axi4.scala 169:28] node _T_44 = eq(UInt<2>("h00"), buf_state) @[Conditional.scala 37:30]
io.axi.ar.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 170:33] when _T_44 : @[Conditional.scala 40:58]
io.axi.ar.bits.addr <= cmdbuf_addr @[ahb_to_axi4.scala 171:33] node _T_45 = mux(io.ahb.sig.out.hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 84:26]
node _T_192 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 172:59] buf_nxtstate <= _T_45 @[ahb_to_axi4.scala 84:20]
node _T_193 = cat(UInt<1>("h00"), _T_192) @[Cat.scala 29:58] node _T_46 = bits(io.ahb.sig.out.htrans, 1, 1) @[ahb_to_axi4.scala 85:57]
io.axi.ar.bits.size <= _T_193 @[ahb_to_axi4.scala 172:33] node _T_47 = and(ahb_hready, _T_46) @[ahb_to_axi4.scala 85:34]
node _T_194 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] node _T_48 = and(_T_47, io.ahb.hsel) @[ahb_to_axi4.scala 85:61]
io.axi.ar.bits.prot <= _T_194 @[ahb_to_axi4.scala 173:33] buf_state_en <= _T_48 @[ahb_to_axi4.scala 85:20]
node _T_195 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] skip @[Conditional.scala 40:58]
io.axi.ar.bits.len <= _T_195 @[ahb_to_axi4.scala 174:33] else : @[Conditional.scala 39:67]
io.axi.ar.bits.burst <= UInt<2>("h01") @[ahb_to_axi4.scala 175:33] node _T_49 = eq(UInt<2>("h01"), buf_state) @[Conditional.scala 37:30]
io.axi.r.ready <= UInt<1>("h01") @[ahb_to_axi4.scala 177:28] when _T_49 : @[Conditional.scala 39:67]
node _T_50 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 88:72]
node _T_51 = eq(_T_50, UInt<1>("h00")) @[ahb_to_axi4.scala 88:79]
node _T_52 = or(io.ahb.sig.in.hresp, _T_51) @[ahb_to_axi4.scala 88:48]
node _T_53 = eq(io.ahb.hsel, UInt<1>("h00")) @[ahb_to_axi4.scala 88:93]
node _T_54 = or(_T_52, _T_53) @[ahb_to_axi4.scala 88:91]
node _T_55 = bits(_T_54, 0, 0) @[ahb_to_axi4.scala 88:107]
node _T_56 = mux(io.ahb.sig.out.hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 88:124]
node _T_57 = mux(_T_55, UInt<2>("h00"), _T_56) @[ahb_to_axi4.scala 88:26]
buf_nxtstate <= _T_57 @[ahb_to_axi4.scala 88:20]
node _T_58 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 89:24]
node _T_59 = or(_T_58, io.ahb.sig.in.hresp) @[ahb_to_axi4.scala 89:37]
buf_state_en <= _T_59 @[ahb_to_axi4.scala 89:20]
node _T_60 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 90:23]
node _T_61 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 90:85]
node _T_62 = eq(_T_61, UInt<2>("h01")) @[ahb_to_axi4.scala 90:92]
node _T_63 = and(_T_62, io.ahb.hsel) @[ahb_to_axi4.scala 90:110]
node _T_64 = or(io.ahb.sig.in.hresp, _T_63) @[ahb_to_axi4.scala 90:60]
node _T_65 = eq(_T_64, UInt<1>("h00")) @[ahb_to_axi4.scala 90:38]
node _T_66 = and(_T_60, _T_65) @[ahb_to_axi4.scala 90:36]
cmdbuf_wr_en <= _T_66 @[ahb_to_axi4.scala 90:20]
skip @[Conditional.scala 39:67]
else : @[Conditional.scala 39:67]
node _T_67 = eq(UInt<2>("h02"), buf_state) @[Conditional.scala 37:30]
when _T_67 : @[Conditional.scala 39:67]
node _T_68 = mux(io.ahb.sig.in.hresp, UInt<2>("h00"), UInt<2>("h03")) @[ahb_to_axi4.scala 93:26]
buf_nxtstate <= _T_68 @[ahb_to_axi4.scala 93:20]
node _T_69 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 94:24]
node _T_70 = or(_T_69, io.ahb.sig.in.hresp) @[ahb_to_axi4.scala 94:37]
buf_state_en <= _T_70 @[ahb_to_axi4.scala 94:20]
node _T_71 = eq(io.ahb.sig.in.hresp, UInt<1>("h00")) @[ahb_to_axi4.scala 95:23]
node _T_72 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 95:46]
node _T_73 = and(_T_71, _T_72) @[ahb_to_axi4.scala 95:44]
cmdbuf_wr_en <= _T_73 @[ahb_to_axi4.scala 95:20]
skip @[Conditional.scala 39:67]
else : @[Conditional.scala 39:67]
node _T_74 = eq(UInt<2>("h03"), buf_state) @[Conditional.scala 37:30]
when _T_74 : @[Conditional.scala 39:67]
buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 98:20]
node _T_75 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 99:40]
node _T_76 = and(io.axi.r.valid, _T_75) @[ahb_to_axi4.scala 99:38]
buf_state_en <= _T_76 @[ahb_to_axi4.scala 99:20]
buf_rdata_en <= buf_state_en @[ahb_to_axi4.scala 100:20]
node _T_77 = bits(io.axi.r.bits.resp, 1, 0) @[ahb_to_axi4.scala 101:61]
node _T_78 = orr(_T_77) @[ahb_to_axi4.scala 101:68]
node _T_79 = and(buf_state_en, _T_78) @[ahb_to_axi4.scala 101:41]
buf_read_error_in <= _T_79 @[ahb_to_axi4.scala 101:25]
skip @[Conditional.scala 39:67]
node _T_80 = bits(buf_state_en, 0, 0) @[ahb_to_axi4.scala 104:78]
node _T_81 = and(io.bus_clk_en, _T_80) @[lib.scala 383:57]
reg _T_82 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_81 : @[Reg.scala 28:19]
_T_82 <= buf_nxtstate @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
buf_state <= _T_82 @[ahb_to_axi4.scala 104:31]
node _T_83 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 106:54]
node _T_84 = eq(_T_83, UInt<1>("h00")) @[ahb_to_axi4.scala 106:60]
node _T_85 = bits(_T_84, 0, 0) @[Bitwise.scala 72:15]
node _T_86 = mux(_T_85, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
node _T_87 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 106:92]
node _T_88 = dshl(UInt<1>("h01"), _T_87) @[ahb_to_axi4.scala 106:78]
node _T_89 = and(_T_86, _T_88) @[ahb_to_axi4.scala 106:70]
node _T_90 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 107:24]
node _T_91 = eq(_T_90, UInt<1>("h01")) @[ahb_to_axi4.scala 107:30]
node _T_92 = bits(_T_91, 0, 0) @[Bitwise.scala 72:15]
node _T_93 = mux(_T_92, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
node _T_94 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 107:62]
node _T_95 = dshl(UInt<2>("h03"), _T_94) @[ahb_to_axi4.scala 107:48]
node _T_96 = and(_T_93, _T_95) @[ahb_to_axi4.scala 107:40]
node _T_97 = or(_T_89, _T_96) @[ahb_to_axi4.scala 106:109]
node _T_98 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 108:24]
node _T_99 = eq(_T_98, UInt<2>("h02")) @[ahb_to_axi4.scala 108:30]
node _T_100 = bits(_T_99, 0, 0) @[Bitwise.scala 72:15]
node _T_101 = mux(_T_100, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
node _T_102 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 108:62]
node _T_103 = dshl(UInt<4>("h0f"), _T_102) @[ahb_to_axi4.scala 108:48]
node _T_104 = and(_T_101, _T_103) @[ahb_to_axi4.scala 108:40]
node _T_105 = or(_T_97, _T_104) @[ahb_to_axi4.scala 107:79]
node _T_106 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 109:24]
node _T_107 = eq(_T_106, UInt<2>("h03")) @[ahb_to_axi4.scala 109:30]
node _T_108 = bits(_T_107, 0, 0) @[Bitwise.scala 72:15]
node _T_109 = mux(_T_108, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
node _T_110 = and(_T_109, UInt<8>("h0ff")) @[ahb_to_axi4.scala 109:40]
node _T_111 = or(_T_105, _T_110) @[ahb_to_axi4.scala 108:79]
master_wstrb <= _T_111 @[ahb_to_axi4.scala 106:31]
node _T_112 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 112:80]
node _T_113 = and(ahb_hresp_q, _T_112) @[ahb_to_axi4.scala 112:78]
node _T_114 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 112:98]
node _T_115 = eq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 112:124]
node _T_116 = or(_T_114, _T_115) @[ahb_to_axi4.scala 112:111]
node _T_117 = eq(buf_state, UInt<2>("h02")) @[ahb_to_axi4.scala 112:149]
node _T_118 = eq(buf_state, UInt<2>("h03")) @[ahb_to_axi4.scala 112:168]
node _T_119 = or(_T_117, _T_118) @[ahb_to_axi4.scala 112:156]
node _T_120 = eq(_T_119, UInt<1>("h00")) @[ahb_to_axi4.scala 112:137]
node _T_121 = and(_T_116, _T_120) @[ahb_to_axi4.scala 112:135]
node _T_122 = eq(buf_read_error, UInt<1>("h00")) @[ahb_to_axi4.scala 112:181]
node _T_123 = and(_T_121, _T_122) @[ahb_to_axi4.scala 112:179]
node _T_124 = mux(io.ahb.sig.in.hresp, _T_113, _T_123) @[ahb_to_axi4.scala 112:44]
io.ahb.sig.in.hready <= _T_124 @[ahb_to_axi4.scala 112:38]
node _T_125 = bits(buf_rdata, 63, 0) @[ahb_to_axi4.scala 113:50]
io.ahb.sig.in.hrdata <= _T_125 @[ahb_to_axi4.scala 113:38]
node _T_126 = bits(ahb_htrans_q, 1, 0) @[ahb_to_axi4.scala 114:55]
node _T_127 = neq(_T_126, UInt<1>("h00")) @[ahb_to_axi4.scala 114:61]
node _T_128 = neq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 114:83]
node _T_129 = and(_T_127, _T_128) @[ahb_to_axi4.scala 114:70]
node _T_130 = or(ahb_addr_in_dccm, ahb_addr_in_iccm) @[ahb_to_axi4.scala 115:26]
node _T_131 = eq(_T_130, UInt<1>("h00")) @[ahb_to_axi4.scala 115:7]
node _T_132 = and(ahb_addr_in_dccm, ahb_hwrite_q) @[ahb_to_axi4.scala 116:46]
node _T_133 = or(ahb_addr_in_iccm, _T_132) @[ahb_to_axi4.scala 116:26]
node _T_134 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 116:80]
node _T_135 = eq(_T_134, UInt<2>("h02")) @[ahb_to_axi4.scala 116:86]
node _T_136 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 116:109]
node _T_137 = eq(_T_136, UInt<2>("h03")) @[ahb_to_axi4.scala 116:115]
node _T_138 = or(_T_135, _T_137) @[ahb_to_axi4.scala 116:95]
node _T_139 = eq(_T_138, UInt<1>("h00")) @[ahb_to_axi4.scala 116:66]
node _T_140 = and(_T_133, _T_139) @[ahb_to_axi4.scala 116:64]
node _T_141 = or(_T_131, _T_140) @[ahb_to_axi4.scala 115:47]
node _T_142 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 117:20]
node _T_143 = eq(_T_142, UInt<1>("h01")) @[ahb_to_axi4.scala 117:26]
node _T_144 = bits(ahb_haddr_q, 0, 0) @[ahb_to_axi4.scala 117:48]
node _T_145 = and(_T_143, _T_144) @[ahb_to_axi4.scala 117:35]
node _T_146 = or(_T_141, _T_145) @[ahb_to_axi4.scala 116:126]
node _T_147 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 118:20]
node _T_148 = eq(_T_147, UInt<2>("h02")) @[ahb_to_axi4.scala 118:26]
node _T_149 = bits(ahb_haddr_q, 1, 0) @[ahb_to_axi4.scala 118:49]
node _T_150 = orr(_T_149) @[ahb_to_axi4.scala 118:56]
node _T_151 = and(_T_148, _T_150) @[ahb_to_axi4.scala 118:35]
node _T_152 = or(_T_146, _T_151) @[ahb_to_axi4.scala 117:55]
node _T_153 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 119:20]
node _T_154 = eq(_T_153, UInt<2>("h03")) @[ahb_to_axi4.scala 119:26]
node _T_155 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 119:49]
node _T_156 = orr(_T_155) @[ahb_to_axi4.scala 119:56]
node _T_157 = and(_T_154, _T_156) @[ahb_to_axi4.scala 119:35]
node _T_158 = or(_T_152, _T_157) @[ahb_to_axi4.scala 118:61]
node _T_159 = and(_T_129, _T_158) @[ahb_to_axi4.scala 114:94]
node _T_160 = or(_T_159, buf_read_error) @[ahb_to_axi4.scala 119:63]
node _T_161 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 121:20]
node _T_162 = and(ahb_hresp_q, _T_161) @[ahb_to_axi4.scala 121:18]
node _T_163 = or(_T_160, _T_162) @[ahb_to_axi4.scala 120:20]
io.ahb.sig.in.hresp <= _T_163 @[ahb_to_axi4.scala 114:38]
node _T_164 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 124:47]
io.axi.aw.valid <= _T_164 @[ahb_to_axi4.scala 124:33]
io.axi.aw.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 125:33]
io.axi.aw.bits.addr <= cmdbuf_addr @[ahb_to_axi4.scala 126:33]
node _T_165 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 127:59]
node _T_166 = cat(UInt<1>("h00"), _T_165) @[Cat.scala 29:58]
io.axi.aw.bits.size <= _T_166 @[ahb_to_axi4.scala 127:33]
node _T_167 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
io.axi.aw.bits.prot <= _T_167 @[ahb_to_axi4.scala 128:33]
node _T_168 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
io.axi.aw.bits.len <= _T_168 @[ahb_to_axi4.scala 129:33]
io.axi.aw.bits.burst <= UInt<2>("h01") @[ahb_to_axi4.scala 130:33]
node _T_169 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 132:47]
io.axi.w.valid <= _T_169 @[ahb_to_axi4.scala 132:33]
io.axi.w.bits.data <= cmdbuf_wdata @[ahb_to_axi4.scala 133:33]
io.axi.w.bits.strb <= cmdbuf_wstrb @[ahb_to_axi4.scala 134:33]
io.axi.w.bits.last <= UInt<1>("h01") @[ahb_to_axi4.scala 135:33]
io.axi.b.ready <= UInt<1>("h01") @[ahb_to_axi4.scala 137:33]
node _T_170 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 139:49]
node _T_171 = and(cmdbuf_vld, _T_170) @[ahb_to_axi4.scala 139:47]
io.axi.ar.valid <= _T_171 @[ahb_to_axi4.scala 139:33]
io.axi.ar.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 140:33]
io.axi.ar.bits.addr <= cmdbuf_addr @[ahb_to_axi4.scala 141:33]
node _T_172 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 142:59]
node _T_173 = cat(UInt<1>("h00"), _T_172) @[Cat.scala 29:58]
io.axi.ar.bits.size <= _T_173 @[ahb_to_axi4.scala 142:33]
node _T_174 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
io.axi.ar.bits.prot <= _T_174 @[ahb_to_axi4.scala 143:33]
node _T_175 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
io.axi.ar.bits.len <= _T_175 @[ahb_to_axi4.scala 144:33]
io.axi.ar.bits.burst <= UInt<2>("h01") @[ahb_to_axi4.scala 145:33]
io.axi.r.ready <= UInt<1>("h01") @[ahb_to_axi4.scala 147:28]

432
ahb_to_axi4.v
View File

@ -80,11 +80,11 @@ module ahb_to_axi4(
reg [31:0] _RAND_1; reg [31:0] _RAND_1;
reg [31:0] _RAND_2; reg [31:0] _RAND_2;
reg [31:0] _RAND_3; reg [31:0] _RAND_3;
reg [31:0] _RAND_4; reg [63:0] _RAND_4;
reg [31:0] _RAND_5; reg [31:0] _RAND_5;
reg [31:0] _RAND_6; reg [31:0] _RAND_6;
reg [31:0] _RAND_7; reg [31:0] _RAND_7;
reg [63:0] _RAND_8; reg [31:0] _RAND_8;
reg [31:0] _RAND_9; reg [31:0] _RAND_9;
reg [31:0] _RAND_10; reg [31:0] _RAND_10;
reg [31:0] _RAND_11; reg [31:0] _RAND_11;
@ -96,135 +96,135 @@ module ahb_to_axi4(
wire rvclkhdr_io_en; // @[lib.scala 399:23] wire rvclkhdr_io_en; // @[lib.scala 399:23]
wire rvclkhdr_1_io_clk; // @[lib.scala 399:23] wire rvclkhdr_1_io_clk; // @[lib.scala 399:23]
wire rvclkhdr_1_io_en; // @[lib.scala 399:23] wire rvclkhdr_1_io_en; // @[lib.scala 399:23]
reg [31:0] ahb_haddr_q; // @[Reg.scala 27:20] wire ahb_hready = io_ahb_sig_in_hready & io_ahb_hreadyin; // @[ahb_to_axi4.scala 27:50]
wire ahb_addr_in_dccm = ahb_haddr_q[31:16] == 16'hf004; // @[lib.scala 87:29] wire [1:0] _T_2 = io_ahb_hsel ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire ahb_addr_in_iccm = ahb_haddr_q[31:16] == 16'hee00; // @[lib.scala 87:29] wire [1:0] ahb_htrans_in = _T_2 & io_ahb_sig_out_htrans; // @[ahb_to_axi4.scala 28:49]
wire _T_5 = ahb_hready & io_ahb_sig_out_htrans[1]; // @[ahb_to_axi4.scala 36:57]
wire ahb_addr_clk_en = io_bus_clk_en & _T_5; // @[ahb_to_axi4.scala 36:43]
reg [1:0] buf_state; // @[Reg.scala 27:20] reg [1:0] buf_state; // @[Reg.scala 27:20]
wire _T_7 = 2'h0 == buf_state; // @[Conditional.scala 37:30] wire _T_44 = 2'h0 == buf_state; // @[Conditional.scala 37:30]
wire ahb_hready = io_ahb_sig_in_hready & io_ahb_hreadyin; // @[ahb_to_axi4.scala 103:55] wire _T_49 = 2'h1 == buf_state; // @[Conditional.scala 37:30]
wire _T_10 = ahb_hready & io_ahb_sig_out_htrans[1]; // @[ahb_to_axi4.scala 75:34] wire _T_67 = 2'h2 == buf_state; // @[Conditional.scala 37:30]
wire _T_11 = _T_10 & io_ahb_hsel; // @[ahb_to_axi4.scala 75:61] wire _T_74 = 2'h3 == buf_state; // @[Conditional.scala 37:30]
wire _T_12 = 2'h1 == buf_state; // @[Conditional.scala 37:30] wire _T_48 = _T_5 & io_ahb_hsel; // @[ahb_to_axi4.scala 85:61]
wire _T_14 = io_ahb_sig_out_htrans == 2'h0; // @[ahb_to_axi4.scala 78:79]
wire _T_15 = io_ahb_sig_in_hresp | _T_14; // @[ahb_to_axi4.scala 78:48]
wire _T_16 = ~io_ahb_hsel; // @[ahb_to_axi4.scala 78:93]
wire _T_17 = _T_15 | _T_16; // @[ahb_to_axi4.scala 78:91]
reg cmdbuf_vld; // @[Reg.scala 27:20] reg cmdbuf_vld; // @[Reg.scala 27:20]
wire _T_155 = io_axi_aw_valid & io_axi_aw_ready; // @[ahb_to_axi4.scala 142:67] wire _T_25 = io_axi_aw_valid & io_axi_aw_ready; // @[ahb_to_axi4.scala 63:58]
wire _T_156 = io_axi_ar_valid & io_axi_ar_ready; // @[ahb_to_axi4.scala 142:105] wire _T_26 = io_axi_ar_valid & io_axi_ar_ready; // @[ahb_to_axi4.scala 63:96]
wire _T_157 = _T_155 | _T_156; // @[ahb_to_axi4.scala 142:86] wire _T_27 = _T_25 | _T_26; // @[ahb_to_axi4.scala 63:77]
wire _T_158 = ~_T_157; // @[ahb_to_axi4.scala 142:48] wire _T_28 = ~_T_27; // @[ahb_to_axi4.scala 63:39]
wire cmdbuf_full = cmdbuf_vld & _T_158; // @[ahb_to_axi4.scala 142:46] wire cmdbuf_full = cmdbuf_vld & _T_28; // @[ahb_to_axi4.scala 63:37]
wire _T_21 = ~cmdbuf_full; // @[ahb_to_axi4.scala 79:24] wire _T_58 = ~cmdbuf_full; // @[ahb_to_axi4.scala 89:24]
wire _T_22 = _T_21 | io_ahb_sig_in_hresp; // @[ahb_to_axi4.scala 79:37] wire _T_59 = _T_58 | io_ahb_sig_in_hresp; // @[ahb_to_axi4.scala 89:37]
wire _T_25 = io_ahb_sig_out_htrans == 2'h1; // @[ahb_to_axi4.scala 80:92]
wire _T_26 = _T_25 & io_ahb_hsel; // @[ahb_to_axi4.scala 80:110]
wire _T_27 = io_ahb_sig_in_hresp | _T_26; // @[ahb_to_axi4.scala 80:60]
wire _T_28 = ~_T_27; // @[ahb_to_axi4.scala 80:38]
wire _T_29 = _T_21 & _T_28; // @[ahb_to_axi4.scala 80:36]
wire _T_30 = 2'h2 == buf_state; // @[Conditional.scala 37:30]
wire _T_34 = ~io_ahb_sig_in_hresp; // @[ahb_to_axi4.scala 85:23]
wire _T_36 = _T_34 & _T_21; // @[ahb_to_axi4.scala 85:44]
wire _T_37 = 2'h3 == buf_state; // @[Conditional.scala 37:30]
reg cmdbuf_write; // @[Reg.scala 27:20] reg cmdbuf_write; // @[Reg.scala 27:20]
wire _T_38 = ~cmdbuf_write; // @[ahb_to_axi4.scala 89:40] wire _T_75 = ~cmdbuf_write; // @[ahb_to_axi4.scala 99:40]
wire _T_39 = io_axi_r_valid & _T_38; // @[ahb_to_axi4.scala 89:38] wire _T_76 = io_axi_r_valid & _T_75; // @[ahb_to_axi4.scala 99:38]
wire _T_41 = |io_axi_r_bits_resp; // @[ahb_to_axi4.scala 91:68] wire _GEN_15 = _T_74 & _T_76; // @[Conditional.scala 39:67]
wire _GEN_1 = _T_37 & _T_39; // @[Conditional.scala 39:67] wire _GEN_19 = _T_67 ? _T_59 : _GEN_15; // @[Conditional.scala 39:67]
wire _GEN_5 = _T_30 ? _T_22 : _GEN_1; // @[Conditional.scala 39:67] wire _GEN_24 = _T_49 ? _T_59 : _GEN_19; // @[Conditional.scala 39:67]
wire _GEN_10 = _T_12 ? _T_22 : _GEN_5; // @[Conditional.scala 39:67] wire buf_state_en = _T_44 ? _T_48 : _GEN_24; // @[Conditional.scala 40:58]
wire buf_state_en = _T_7 ? _T_11 : _GEN_10; // @[Conditional.scala 40:58] wire _GEN_16 = _T_74 & buf_state_en; // @[Conditional.scala 39:67]
wire _T_42 = buf_state_en & _T_41; // @[ahb_to_axi4.scala 91:41] wire _GEN_21 = _T_67 ? 1'h0 : _GEN_16; // @[Conditional.scala 39:67]
wire _GEN_2 = _T_37 & buf_state_en; // @[Conditional.scala 39:67] wire _GEN_26 = _T_49 ? 1'h0 : _GEN_21; // @[Conditional.scala 39:67]
wire _GEN_3 = _T_37 & _T_42; // @[Conditional.scala 39:67] wire buf_rdata_en = _T_44 ? 1'h0 : _GEN_26; // @[Conditional.scala 40:58]
wire _GEN_6 = _T_30 & _T_36; // @[Conditional.scala 39:67] wire buf_rdata_clk_en = io_bus_clk_en & buf_rdata_en; // @[ahb_to_axi4.scala 37:43]
wire _GEN_7 = _T_30 ? 1'h0 : _GEN_2; // @[Conditional.scala 39:67]
wire _GEN_11 = _T_12 ? _T_29 : _GEN_6; // @[Conditional.scala 39:67]
wire _GEN_12 = _T_12 ? 1'h0 : _GEN_7; // @[Conditional.scala 39:67]
wire cmdbuf_wr_en = _T_7 ? 1'h0 : _GEN_11; // @[Conditional.scala 40:58]
wire buf_rdata_en = _T_7 ? 1'h0 : _GEN_12; // @[Conditional.scala 40:58]
wire _T_44 = io_bus_clk_en & buf_state_en; // @[lib.scala 383:57]
reg [2:0] ahb_hsize_q; // @[Reg.scala 27:20]
wire _T_47 = ahb_hsize_q == 3'h0; // @[ahb_to_axi4.scala 96:60]
wire [7:0] _T_49 = _T_47 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [7:0] _T_51 = 8'h1 << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 96:78]
wire [7:0] _T_52 = _T_49 & _T_51; // @[ahb_to_axi4.scala 96:70]
wire _T_54 = ahb_hsize_q == 3'h1; // @[ahb_to_axi4.scala 97:30]
wire [7:0] _T_56 = _T_54 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [8:0] _T_58 = 9'h3 << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 97:48]
wire [8:0] _GEN_34 = {{1'd0}, _T_56}; // @[ahb_to_axi4.scala 97:40]
wire [8:0] _T_59 = _GEN_34 & _T_58; // @[ahb_to_axi4.scala 97:40]
wire [8:0] _GEN_35 = {{1'd0}, _T_52}; // @[ahb_to_axi4.scala 96:109]
wire [8:0] _T_60 = _GEN_35 | _T_59; // @[ahb_to_axi4.scala 96:109]
wire _T_62 = ahb_hsize_q == 3'h2; // @[ahb_to_axi4.scala 98:30]
wire [7:0] _T_64 = _T_62 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [10:0] _T_66 = 11'hf << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 98:48]
wire [10:0] _GEN_36 = {{3'd0}, _T_64}; // @[ahb_to_axi4.scala 98:40]
wire [10:0] _T_67 = _GEN_36 & _T_66; // @[ahb_to_axi4.scala 98:40]
wire [10:0] _GEN_37 = {{2'd0}, _T_60}; // @[ahb_to_axi4.scala 97:79]
wire [10:0] _T_68 = _GEN_37 | _T_67; // @[ahb_to_axi4.scala 97:79]
wire _T_70 = ahb_hsize_q == 3'h3; // @[ahb_to_axi4.scala 99:30]
wire [7:0] _T_72 = _T_70 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [10:0] _GEN_38 = {{3'd0}, _T_72}; // @[ahb_to_axi4.scala 98:79]
wire [10:0] _T_74 = _T_68 | _GEN_38; // @[ahb_to_axi4.scala 98:79]
reg ahb_hready_q; // @[Reg.scala 27:20]
wire _T_75 = ~ahb_hready_q; // @[ahb_to_axi4.scala 102:80]
reg ahb_hresp_q; // @[Reg.scala 27:20]
wire _T_76 = ahb_hresp_q & _T_75; // @[ahb_to_axi4.scala 102:78]
wire _T_78 = buf_state == 2'h0; // @[ahb_to_axi4.scala 102:124]
wire _T_79 = _T_21 | _T_78; // @[ahb_to_axi4.scala 102:111]
wire _T_80 = buf_state == 2'h2; // @[ahb_to_axi4.scala 102:149]
wire _T_81 = buf_state == 2'h3; // @[ahb_to_axi4.scala 102:168]
wire _T_82 = _T_80 | _T_81; // @[ahb_to_axi4.scala 102:156]
wire _T_83 = ~_T_82; // @[ahb_to_axi4.scala 102:137]
wire _T_84 = _T_79 & _T_83; // @[ahb_to_axi4.scala 102:135]
reg buf_read_error; // @[Reg.scala 27:20] reg buf_read_error; // @[Reg.scala 27:20]
wire _T_85 = ~buf_read_error; // @[ahb_to_axi4.scala 102:181] wire _T_78 = |io_axi_r_bits_resp; // @[ahb_to_axi4.scala 101:68]
wire _T_86 = _T_84 & _T_85; // @[ahb_to_axi4.scala 102:179] wire _T_79 = buf_state_en & _T_78; // @[ahb_to_axi4.scala 101:41]
wire [1:0] _T_90 = io_ahb_hsel ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] wire _GEN_17 = _T_74 & _T_79; // @[Conditional.scala 39:67]
wire [1:0] ahb_htrans_in = _T_90 & io_ahb_sig_out_htrans; // @[ahb_to_axi4.scala 104:54]
reg [63:0] buf_rdata; // @[Reg.scala 27:20] reg [63:0] buf_rdata; // @[Reg.scala 27:20]
reg [1:0] ahb_htrans_q; // @[Reg.scala 27:20] reg ahb_hresp_q; // @[Reg.scala 27:20]
wire _T_95 = ahb_htrans_q != 2'h0; // @[ahb_to_axi4.scala 106:61] reg [2:0] ahb_hsize_q; // @[Reg.scala 27:20]
wire _T_96 = buf_state != 2'h0; // @[ahb_to_axi4.scala 106:83]
wire _T_97 = _T_95 & _T_96; // @[ahb_to_axi4.scala 106:70]
wire _T_98 = ahb_addr_in_dccm | ahb_addr_in_iccm; // @[ahb_to_axi4.scala 107:26]
wire _T_99 = ~_T_98; // @[ahb_to_axi4.scala 107:7]
reg ahb_hwrite_q; // @[Reg.scala 27:20] reg ahb_hwrite_q; // @[Reg.scala 27:20]
wire _T_100 = ahb_addr_in_dccm & ahb_hwrite_q; // @[ahb_to_axi4.scala 108:46] reg [31:0] ahb_haddr_q; // @[Reg.scala 27:20]
wire _T_101 = ahb_addr_in_iccm | _T_100; // @[ahb_to_axi4.scala 108:26] reg ahb_hready_q; // @[Reg.scala 27:20]
wire _T_103 = ahb_hsize_q[1:0] == 2'h2; // @[ahb_to_axi4.scala 108:86] reg [1:0] ahb_htrans_q; // @[Reg.scala 27:20]
wire _T_105 = ahb_hsize_q[1:0] == 2'h3; // @[ahb_to_axi4.scala 108:115] wire _T_62 = io_ahb_sig_out_htrans == 2'h1; // @[ahb_to_axi4.scala 90:92]
wire _T_106 = _T_103 | _T_105; // @[ahb_to_axi4.scala 108:95] wire _T_63 = _T_62 & io_ahb_hsel; // @[ahb_to_axi4.scala 90:110]
wire _T_107 = ~_T_106; // @[ahb_to_axi4.scala 108:66] wire _T_64 = io_ahb_sig_in_hresp | _T_63; // @[ahb_to_axi4.scala 90:60]
wire _T_108 = _T_101 & _T_107; // @[ahb_to_axi4.scala 108:64] wire _T_65 = ~_T_64; // @[ahb_to_axi4.scala 90:38]
wire _T_109 = _T_99 | _T_108; // @[ahb_to_axi4.scala 107:47] wire _T_66 = _T_58 & _T_65; // @[ahb_to_axi4.scala 90:36]
wire _T_113 = _T_54 & ahb_haddr_q[0]; // @[ahb_to_axi4.scala 109:35] wire _T_71 = ~io_ahb_sig_in_hresp; // @[ahb_to_axi4.scala 95:23]
wire _T_114 = _T_109 | _T_113; // @[ahb_to_axi4.scala 108:126] wire _T_73 = _T_71 & _T_58; // @[ahb_to_axi4.scala 95:44]
wire _T_118 = |ahb_haddr_q[1:0]; // @[ahb_to_axi4.scala 110:56] wire _GEN_20 = _T_67 & _T_73; // @[Conditional.scala 39:67]
wire _T_119 = _T_62 & _T_118; // @[ahb_to_axi4.scala 110:35] wire _GEN_25 = _T_49 ? _T_66 : _GEN_20; // @[Conditional.scala 39:67]
wire _T_120 = _T_114 | _T_119; // @[ahb_to_axi4.scala 109:55] wire cmdbuf_wr_en = _T_44 ? 1'h0 : _GEN_25; // @[Conditional.scala 40:58]
wire _T_124 = |ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 111:56] wire _T_10 = io_bus_clk_en & cmdbuf_wr_en; // @[lib.scala 383:57]
wire _T_125 = _T_70 & _T_124; // @[ahb_to_axi4.scala 111:35] wire _T_14 = ~cmdbuf_wr_en; // @[ahb_to_axi4.scala 61:104]
wire _T_126 = _T_120 | _T_125; // @[ahb_to_axi4.scala 110:61] wire _T_15 = _T_27 & _T_14; // @[ahb_to_axi4.scala 61:102]
wire _T_127 = _T_97 & _T_126; // @[ahb_to_axi4.scala 106:94] wire _T_17 = io_ahb_sig_in_hresp & _T_75; // @[ahb_to_axi4.scala 61:142]
wire _T_128 = _T_127 | buf_read_error; // @[ahb_to_axi4.scala 111:63] wire cmdbuf_rst = _T_15 | _T_17; // @[ahb_to_axi4.scala 61:119]
wire buf_rdata_clk_en = io_bus_clk_en & buf_rdata_en; // @[ahb_to_axi4.scala 129:48] wire _T_19 = ~cmdbuf_rst; // @[lib.scala 391:73]
wire ahb_addr_clk_en = io_bus_clk_en & _T_10; // @[ahb_to_axi4.scala 128:44] wire _T_21 = cmdbuf_wr_en | cmdbuf_rst; // @[lib.scala 391:92]
wire _T_150 = ~cmdbuf_wr_en; // @[ahb_to_axi4.scala 141:113] wire _T_22 = _T_21 & io_bus_clk_en; // @[lib.scala 391:99]
wire _T_151 = _T_157 & _T_150; // @[ahb_to_axi4.scala 141:111]
wire _T_153 = io_ahb_sig_in_hresp & _T_38; // @[ahb_to_axi4.scala 141:151]
wire cmdbuf_rst = _T_151 | _T_153; // @[ahb_to_axi4.scala 141:128]
wire _T_162 = ~cmdbuf_rst; // @[lib.scala 391:75]
wire _T_164 = cmdbuf_wr_en | cmdbuf_rst; // @[lib.scala 391:95]
wire _T_165 = _T_164 & io_bus_clk_en; // @[lib.scala 391:102]
wire _T_169 = io_bus_clk_en & cmdbuf_wr_en; // @[lib.scala 383:57]
reg [1:0] cmdbuf_size; // @[Reg.scala 27:20] reg [1:0] cmdbuf_size; // @[Reg.scala 27:20]
reg [7:0] cmdbuf_wstrb; // @[Reg.scala 27:20] reg [7:0] cmdbuf_wstrb; // @[Reg.scala 27:20]
wire [7:0] master_wstrb = _T_74[7:0]; // @[ahb_to_axi4.scala 96:31] wire _T_84 = ahb_hsize_q == 3'h0; // @[ahb_to_axi4.scala 106:60]
wire _T_179 = cmdbuf_wr_en & io_bus_clk_en; // @[ahb_to_axi4.scala 150:59] wire [7:0] _T_86 = _T_84 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [7:0] _T_88 = 8'h1 << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 106:78]
wire [7:0] _T_89 = _T_86 & _T_88; // @[ahb_to_axi4.scala 106:70]
wire _T_91 = ahb_hsize_q == 3'h1; // @[ahb_to_axi4.scala 107:30]
wire [7:0] _T_93 = _T_91 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [8:0] _T_95 = 9'h3 << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 107:48]
wire [8:0] _GEN_34 = {{1'd0}, _T_93}; // @[ahb_to_axi4.scala 107:40]
wire [8:0] _T_96 = _GEN_34 & _T_95; // @[ahb_to_axi4.scala 107:40]
wire [8:0] _GEN_35 = {{1'd0}, _T_89}; // @[ahb_to_axi4.scala 106:109]
wire [8:0] _T_97 = _GEN_35 | _T_96; // @[ahb_to_axi4.scala 106:109]
wire _T_99 = ahb_hsize_q == 3'h2; // @[ahb_to_axi4.scala 108:30]
wire [7:0] _T_101 = _T_99 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [10:0] _T_103 = 11'hf << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 108:48]
wire [10:0] _GEN_36 = {{3'd0}, _T_101}; // @[ahb_to_axi4.scala 108:40]
wire [10:0] _T_104 = _GEN_36 & _T_103; // @[ahb_to_axi4.scala 108:40]
wire [10:0] _GEN_37 = {{2'd0}, _T_97}; // @[ahb_to_axi4.scala 107:79]
wire [10:0] _T_105 = _GEN_37 | _T_104; // @[ahb_to_axi4.scala 107:79]
wire _T_107 = ahb_hsize_q == 3'h3; // @[ahb_to_axi4.scala 109:30]
wire [7:0] _T_109 = _T_107 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [10:0] _GEN_38 = {{3'd0}, _T_109}; // @[ahb_to_axi4.scala 108:79]
wire [10:0] _T_111 = _T_105 | _GEN_38; // @[ahb_to_axi4.scala 108:79]
wire [7:0] master_wstrb = _T_111[7:0]; // @[ahb_to_axi4.scala 106:31]
wire _T_35 = cmdbuf_wr_en & io_bus_clk_en; // @[ahb_to_axi4.scala 66:66]
reg [31:0] cmdbuf_addr; // @[Reg.scala 27:20] reg [31:0] cmdbuf_addr; // @[Reg.scala 27:20]
reg [63:0] cmdbuf_wdata; // @[Reg.scala 27:20] reg [63:0] cmdbuf_wdata; // @[Reg.scala 27:20]
wire ahb_addr_in_dccm = ahb_haddr_q[31:16] == 16'hf004; // @[lib.scala 87:29]
wire ahb_addr_in_iccm = ahb_haddr_q[31:16] == 16'hee00; // @[lib.scala 87:29]
wire _T_51 = io_ahb_sig_out_htrans == 2'h0; // @[ahb_to_axi4.scala 88:79]
wire _T_52 = io_ahb_sig_in_hresp | _T_51; // @[ahb_to_axi4.scala 88:48]
wire _T_53 = ~io_ahb_hsel; // @[ahb_to_axi4.scala 88:93]
wire _T_54 = _T_52 | _T_53; // @[ahb_to_axi4.scala 88:91]
wire _T_81 = io_bus_clk_en & buf_state_en; // @[lib.scala 383:57]
wire _T_112 = ~ahb_hready_q; // @[ahb_to_axi4.scala 112:80]
wire _T_113 = ahb_hresp_q & _T_112; // @[ahb_to_axi4.scala 112:78]
wire _T_115 = buf_state == 2'h0; // @[ahb_to_axi4.scala 112:124]
wire _T_116 = _T_58 | _T_115; // @[ahb_to_axi4.scala 112:111]
wire _T_117 = buf_state == 2'h2; // @[ahb_to_axi4.scala 112:149]
wire _T_118 = buf_state == 2'h3; // @[ahb_to_axi4.scala 112:168]
wire _T_119 = _T_117 | _T_118; // @[ahb_to_axi4.scala 112:156]
wire _T_120 = ~_T_119; // @[ahb_to_axi4.scala 112:137]
wire _T_121 = _T_116 & _T_120; // @[ahb_to_axi4.scala 112:135]
wire _T_122 = ~buf_read_error; // @[ahb_to_axi4.scala 112:181]
wire _T_123 = _T_121 & _T_122; // @[ahb_to_axi4.scala 112:179]
wire _T_127 = ahb_htrans_q != 2'h0; // @[ahb_to_axi4.scala 114:61]
wire _T_128 = buf_state != 2'h0; // @[ahb_to_axi4.scala 114:83]
wire _T_129 = _T_127 & _T_128; // @[ahb_to_axi4.scala 114:70]
wire _T_130 = ahb_addr_in_dccm | ahb_addr_in_iccm; // @[ahb_to_axi4.scala 115:26]
wire _T_131 = ~_T_130; // @[ahb_to_axi4.scala 115:7]
wire _T_132 = ahb_addr_in_dccm & ahb_hwrite_q; // @[ahb_to_axi4.scala 116:46]
wire _T_133 = ahb_addr_in_iccm | _T_132; // @[ahb_to_axi4.scala 116:26]
wire _T_135 = ahb_hsize_q[1:0] == 2'h2; // @[ahb_to_axi4.scala 116:86]
wire _T_137 = ahb_hsize_q[1:0] == 2'h3; // @[ahb_to_axi4.scala 116:115]
wire _T_138 = _T_135 | _T_137; // @[ahb_to_axi4.scala 116:95]
wire _T_139 = ~_T_138; // @[ahb_to_axi4.scala 116:66]
wire _T_140 = _T_133 & _T_139; // @[ahb_to_axi4.scala 116:64]
wire _T_141 = _T_131 | _T_140; // @[ahb_to_axi4.scala 115:47]
wire _T_145 = _T_91 & ahb_haddr_q[0]; // @[ahb_to_axi4.scala 117:35]
wire _T_146 = _T_141 | _T_145; // @[ahb_to_axi4.scala 116:126]
wire _T_150 = |ahb_haddr_q[1:0]; // @[ahb_to_axi4.scala 118:56]
wire _T_151 = _T_99 & _T_150; // @[ahb_to_axi4.scala 118:35]
wire _T_152 = _T_146 | _T_151; // @[ahb_to_axi4.scala 117:55]
wire _T_156 = |ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 119:56]
wire _T_157 = _T_107 & _T_156; // @[ahb_to_axi4.scala 119:35]
wire _T_158 = _T_152 | _T_157; // @[ahb_to_axi4.scala 118:61]
wire _T_159 = _T_129 & _T_158; // @[ahb_to_axi4.scala 114:94]
wire _T_160 = _T_159 | buf_read_error; // @[ahb_to_axi4.scala 119:63]
rvclkhdr rvclkhdr ( // @[lib.scala 399:23] rvclkhdr rvclkhdr ( // @[lib.scala 399:23]
.io_clk(rvclkhdr_io_clk), .io_clk(rvclkhdr_io_clk),
.io_en(rvclkhdr_io_en) .io_en(rvclkhdr_io_en)
@ -233,37 +233,37 @@ module ahb_to_axi4(
.io_clk(rvclkhdr_1_io_clk), .io_clk(rvclkhdr_1_io_clk),
.io_en(rvclkhdr_1_io_en) .io_en(rvclkhdr_1_io_en)
); );
assign io_axi_aw_valid = cmdbuf_vld & cmdbuf_write; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 154:28] assign io_axi_aw_valid = cmdbuf_vld & cmdbuf_write; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 124:33]
assign io_axi_aw_bits_id = 1'h0; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 155:33] assign io_axi_aw_bits_id = 1'h0; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 125:33]
assign io_axi_aw_bits_addr = cmdbuf_addr; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 156:33] assign io_axi_aw_bits_addr = cmdbuf_addr; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 126:33]
assign io_axi_aw_bits_region = 4'h0; // @[ahb_to_axi4.scala 20:10] assign io_axi_aw_bits_region = 4'h0; // @[ahb_to_axi4.scala 20:10]
assign io_axi_aw_bits_len = 8'h0; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 159:33] assign io_axi_aw_bits_len = 8'h0; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 129:33]
assign io_axi_aw_bits_size = {1'h0,cmdbuf_size}; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 157:33] assign io_axi_aw_bits_size = {1'h0,cmdbuf_size}; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 127:33]
assign io_axi_aw_bits_burst = 2'h1; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 160:33] assign io_axi_aw_bits_burst = 2'h1; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 130:33]
assign io_axi_aw_bits_lock = 1'h0; // @[ahb_to_axi4.scala 20:10] assign io_axi_aw_bits_lock = 1'h0; // @[ahb_to_axi4.scala 20:10]
assign io_axi_aw_bits_cache = 4'h0; // @[ahb_to_axi4.scala 20:10] assign io_axi_aw_bits_cache = 4'h0; // @[ahb_to_axi4.scala 20:10]
assign io_axi_aw_bits_prot = 3'h0; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 158:33] assign io_axi_aw_bits_prot = 3'h0; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 128:33]
assign io_axi_aw_bits_qos = 4'h0; // @[ahb_to_axi4.scala 20:10] assign io_axi_aw_bits_qos = 4'h0; // @[ahb_to_axi4.scala 20:10]
assign io_axi_w_valid = cmdbuf_vld & cmdbuf_write; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 162:28] assign io_axi_w_valid = cmdbuf_vld & cmdbuf_write; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 132:33]
assign io_axi_w_bits_data = cmdbuf_wdata; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 163:33] assign io_axi_w_bits_data = cmdbuf_wdata; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 133:33]
assign io_axi_w_bits_strb = cmdbuf_wstrb; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 164:33] assign io_axi_w_bits_strb = cmdbuf_wstrb; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 134:33]
assign io_axi_w_bits_last = 1'h1; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 165:33] assign io_axi_w_bits_last = 1'h1; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 135:33]
assign io_axi_b_ready = 1'h1; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 167:28] assign io_axi_b_ready = 1'h1; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 137:33]
assign io_axi_ar_valid = cmdbuf_vld & _T_38; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 169:28] assign io_axi_ar_valid = cmdbuf_vld & _T_75; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 139:33]
assign io_axi_ar_bits_id = 1'h0; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 170:33] assign io_axi_ar_bits_id = 1'h0; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 140:33]
assign io_axi_ar_bits_addr = cmdbuf_addr; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 171:33] assign io_axi_ar_bits_addr = cmdbuf_addr; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 141:33]
assign io_axi_ar_bits_region = 4'h0; // @[ahb_to_axi4.scala 20:10] assign io_axi_ar_bits_region = 4'h0; // @[ahb_to_axi4.scala 20:10]
assign io_axi_ar_bits_len = 8'h0; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 174:33] assign io_axi_ar_bits_len = 8'h0; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 144:33]
assign io_axi_ar_bits_size = {1'h0,cmdbuf_size}; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 172:33] assign io_axi_ar_bits_size = {1'h0,cmdbuf_size}; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 142:33]
assign io_axi_ar_bits_burst = 2'h1; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 175:33] assign io_axi_ar_bits_burst = 2'h1; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 145:33]
assign io_axi_ar_bits_lock = 1'h0; // @[ahb_to_axi4.scala 20:10] assign io_axi_ar_bits_lock = 1'h0; // @[ahb_to_axi4.scala 20:10]
assign io_axi_ar_bits_cache = 4'h0; // @[ahb_to_axi4.scala 20:10] assign io_axi_ar_bits_cache = 4'h0; // @[ahb_to_axi4.scala 20:10]
assign io_axi_ar_bits_prot = 3'h0; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 173:33] assign io_axi_ar_bits_prot = 3'h0; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 143:33]
assign io_axi_ar_bits_qos = 4'h0; // @[ahb_to_axi4.scala 20:10] assign io_axi_ar_bits_qos = 4'h0; // @[ahb_to_axi4.scala 20:10]
assign io_axi_r_ready = 1'h1; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 177:28] assign io_axi_r_ready = 1'h1; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 147:28]
assign io_ahb_sig_in_hrdata = buf_rdata; // @[ahb_to_axi4.scala 105:38] assign io_ahb_sig_in_hrdata = buf_rdata; // @[ahb_to_axi4.scala 113:38]
assign io_ahb_sig_in_hready = io_ahb_sig_in_hresp ? _T_76 : _T_86; // @[ahb_to_axi4.scala 102:38] assign io_ahb_sig_in_hready = io_ahb_sig_in_hresp ? _T_113 : _T_123; // @[ahb_to_axi4.scala 112:38]
assign io_ahb_sig_in_hresp = _T_128 | _T_76; // @[ahb_to_axi4.scala 106:38] assign io_ahb_sig_in_hresp = _T_160 | _T_113; // @[ahb_to_axi4.scala 114:38]
assign rvclkhdr_io_clk = clock; // @[lib.scala 401:18] assign rvclkhdr_io_clk = clock; // @[lib.scala 401:18]
assign rvclkhdr_io_en = cmdbuf_wr_en & io_bus_clk_en; // @[lib.scala 402:17] assign rvclkhdr_io_en = cmdbuf_wr_en & io_bus_clk_en; // @[lib.scala 402:17]
assign rvclkhdr_1_io_clk = clock; // @[lib.scala 401:18] assign rvclkhdr_1_io_clk = clock; // @[lib.scala 401:18]
@ -304,27 +304,27 @@ initial begin
`endif `endif
`ifdef RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}}; _RAND_0 = {1{`RANDOM}};
ahb_haddr_q = _RAND_0[31:0]; buf_state = _RAND_0[1:0];
_RAND_1 = {1{`RANDOM}}; _RAND_1 = {1{`RANDOM}};
buf_state = _RAND_1[1:0]; cmdbuf_vld = _RAND_1[0:0];
_RAND_2 = {1{`RANDOM}}; _RAND_2 = {1{`RANDOM}};
cmdbuf_vld = _RAND_2[0:0]; cmdbuf_write = _RAND_2[0:0];
_RAND_3 = {1{`RANDOM}}; _RAND_3 = {1{`RANDOM}};
cmdbuf_write = _RAND_3[0:0]; buf_read_error = _RAND_3[0:0];
_RAND_4 = {1{`RANDOM}}; _RAND_4 = {2{`RANDOM}};
ahb_hsize_q = _RAND_4[2:0]; buf_rdata = _RAND_4[63:0];
_RAND_5 = {1{`RANDOM}}; _RAND_5 = {1{`RANDOM}};
ahb_hready_q = _RAND_5[0:0]; ahb_hresp_q = _RAND_5[0:0];
_RAND_6 = {1{`RANDOM}}; _RAND_6 = {1{`RANDOM}};
ahb_hresp_q = _RAND_6[0:0]; ahb_hsize_q = _RAND_6[2:0];
_RAND_7 = {1{`RANDOM}}; _RAND_7 = {1{`RANDOM}};
buf_read_error = _RAND_7[0:0]; ahb_hwrite_q = _RAND_7[0:0];
_RAND_8 = {2{`RANDOM}}; _RAND_8 = {1{`RANDOM}};
buf_rdata = _RAND_8[63:0]; ahb_haddr_q = _RAND_8[31:0];
_RAND_9 = {1{`RANDOM}}; _RAND_9 = {1{`RANDOM}};
ahb_htrans_q = _RAND_9[1:0]; ahb_hready_q = _RAND_9[0:0];
_RAND_10 = {1{`RANDOM}}; _RAND_10 = {1{`RANDOM}};
ahb_hwrite_q = _RAND_10[0:0]; ahb_htrans_q = _RAND_10[1:0];
_RAND_11 = {1{`RANDOM}}; _RAND_11 = {1{`RANDOM}};
cmdbuf_size = _RAND_11[1:0]; cmdbuf_size = _RAND_11[1:0];
_RAND_12 = {1{`RANDOM}}; _RAND_12 = {1{`RANDOM}};
@ -334,9 +334,6 @@ initial begin
_RAND_14 = {2{`RANDOM}}; _RAND_14 = {2{`RANDOM}};
cmdbuf_wdata = _RAND_14[63:0]; cmdbuf_wdata = _RAND_14[63:0];
`endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE_REG_INIT
if (reset) begin
ahb_haddr_q = 32'h0;
end
if (reset) begin if (reset) begin
buf_state = 2'h0; buf_state = 2'h0;
end end
@ -346,15 +343,6 @@ initial begin
if (reset) begin if (reset) begin
cmdbuf_write = 1'h0; cmdbuf_write = 1'h0;
end end
if (reset) begin
ahb_hsize_q = 3'h0;
end
if (reset) begin
ahb_hready_q = 1'h0;
end
if (reset) begin
ahb_hresp_q = 1'h0;
end
if (reset) begin if (reset) begin
buf_read_error = 1'h0; buf_read_error = 1'h0;
end end
@ -362,11 +350,23 @@ initial begin
buf_rdata = 64'h0; buf_rdata = 64'h0;
end end
if (reset) begin if (reset) begin
ahb_htrans_q = 2'h0; ahb_hresp_q = 1'h0;
end
if (reset) begin
ahb_hsize_q = 3'h0;
end end
if (reset) begin if (reset) begin
ahb_hwrite_q = 1'h0; ahb_hwrite_q = 1'h0;
end end
if (reset) begin
ahb_haddr_q = 32'h0;
end
if (reset) begin
ahb_hready_q = 1'h0;
end
if (reset) begin
ahb_htrans_q = 2'h0;
end
if (reset) begin if (reset) begin
cmdbuf_size = 2'h0; cmdbuf_size = 2'h0;
end end
@ -385,32 +385,25 @@ end // initial
`FIRRTL_AFTER_INITIAL `FIRRTL_AFTER_INITIAL
`endif `endif
`endif // SYNTHESIS `endif // SYNTHESIS
always @(posedge clock or posedge reset) begin
if (reset) begin
ahb_haddr_q <= 32'h0;
end else if (ahb_addr_clk_en) begin
ahb_haddr_q <= io_ahb_sig_out_haddr;
end
end
always @(posedge clock or posedge reset) begin always @(posedge clock or posedge reset) begin
if (reset) begin if (reset) begin
buf_state <= 2'h0; buf_state <= 2'h0;
end else if (_T_44) begin end else if (_T_81) begin
if (_T_7) begin if (_T_44) begin
if (io_ahb_sig_out_hwrite) begin if (io_ahb_sig_out_hwrite) begin
buf_state <= 2'h1; buf_state <= 2'h1;
end else begin end else begin
buf_state <= 2'h2; buf_state <= 2'h2;
end end
end else if (_T_12) begin end else if (_T_49) begin
if (_T_17) begin if (_T_54) begin
buf_state <= 2'h0; buf_state <= 2'h0;
end else if (io_ahb_sig_out_hwrite) begin end else if (io_ahb_sig_out_hwrite) begin
buf_state <= 2'h1; buf_state <= 2'h1;
end else begin end else begin
buf_state <= 2'h2; buf_state <= 2'h2;
end end
end else if (_T_30) begin end else if (_T_67) begin
if (io_ahb_sig_in_hresp) begin if (io_ahb_sig_in_hresp) begin
buf_state <= 2'h0; buf_state <= 2'h0;
end else begin end else begin
@ -424,50 +417,29 @@ end // initial
always @(posedge clock or posedge reset) begin always @(posedge clock or posedge reset) begin
if (reset) begin if (reset) begin
cmdbuf_vld <= 1'h0; cmdbuf_vld <= 1'h0;
end else if (_T_165) begin end else if (_T_22) begin
cmdbuf_vld <= _T_162; cmdbuf_vld <= _T_19;
end end
end end
always @(posedge clock or posedge reset) begin always @(posedge clock or posedge reset) begin
if (reset) begin if (reset) begin
cmdbuf_write <= 1'h0; cmdbuf_write <= 1'h0;
end else if (_T_169) begin end else if (_T_10) begin
cmdbuf_write <= ahb_hwrite_q; cmdbuf_write <= ahb_hwrite_q;
end end
end end
always @(posedge clock or posedge reset) begin
if (reset) begin
ahb_hsize_q <= 3'h0;
end else if (ahb_addr_clk_en) begin
ahb_hsize_q <= io_ahb_sig_out_hsize;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
ahb_hready_q <= 1'h0;
end else if (io_bus_clk_en) begin
ahb_hready_q <= ahb_hready;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
ahb_hresp_q <= 1'h0;
end else if (io_bus_clk_en) begin
ahb_hresp_q <= io_ahb_sig_in_hresp;
end
end
always @(posedge clock or posedge reset) begin always @(posedge clock or posedge reset) begin
if (reset) begin if (reset) begin
buf_read_error <= 1'h0; buf_read_error <= 1'h0;
end else if (io_bus_clk_en) begin end else if (io_bus_clk_en) begin
if (_T_7) begin if (_T_44) begin
buf_read_error <= 1'h0; buf_read_error <= 1'h0;
end else if (_T_12) begin end else if (_T_49) begin
buf_read_error <= 1'h0; buf_read_error <= 1'h0;
end else if (_T_30) begin end else if (_T_67) begin
buf_read_error <= 1'h0; buf_read_error <= 1'h0;
end else begin end else begin
buf_read_error <= _GEN_3; buf_read_error <= _GEN_17;
end end
end end
end end
@ -480,9 +452,16 @@ end // initial
end end
always @(posedge clock or posedge reset) begin always @(posedge clock or posedge reset) begin
if (reset) begin if (reset) begin
ahb_htrans_q <= 2'h0; ahb_hresp_q <= 1'h0;
end else if (io_bus_clk_en) begin end else if (io_bus_clk_en) begin
ahb_htrans_q <= ahb_htrans_in; ahb_hresp_q <= io_ahb_sig_in_hresp;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
ahb_hsize_q <= 3'h0;
end else if (ahb_addr_clk_en) begin
ahb_hsize_q <= io_ahb_sig_out_hsize;
end end
end end
always @(posedge clock or posedge reset) begin always @(posedge clock or posedge reset) begin
@ -492,31 +471,52 @@ end // initial
ahb_hwrite_q <= io_ahb_sig_out_hwrite; ahb_hwrite_q <= io_ahb_sig_out_hwrite;
end end
end end
always @(posedge clock or posedge reset) begin
if (reset) begin
ahb_haddr_q <= 32'h0;
end else if (ahb_addr_clk_en) begin
ahb_haddr_q <= io_ahb_sig_out_haddr;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
ahb_hready_q <= 1'h0;
end else if (io_bus_clk_en) begin
ahb_hready_q <= ahb_hready;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
ahb_htrans_q <= 2'h0;
end else if (io_bus_clk_en) begin
ahb_htrans_q <= ahb_htrans_in;
end
end
always @(posedge clock or posedge reset) begin always @(posedge clock or posedge reset) begin
if (reset) begin if (reset) begin
cmdbuf_size <= 2'h0; cmdbuf_size <= 2'h0;
end else if (_T_169) begin end else if (_T_10) begin
cmdbuf_size <= ahb_hsize_q[1:0]; cmdbuf_size <= ahb_hsize_q[1:0];
end end
end end
always @(posedge clock or posedge reset) begin always @(posedge clock or posedge reset) begin
if (reset) begin if (reset) begin
cmdbuf_wstrb <= 8'h0; cmdbuf_wstrb <= 8'h0;
end else if (_T_169) begin end else if (_T_10) begin
cmdbuf_wstrb <= master_wstrb; cmdbuf_wstrb <= master_wstrb;
end end
end end
always @(posedge clock or posedge reset) begin always @(posedge clock or posedge reset) begin
if (reset) begin if (reset) begin
cmdbuf_addr <= 32'h0; cmdbuf_addr <= 32'h0;
end else if (_T_179) begin end else if (_T_35) begin
cmdbuf_addr <= ahb_haddr_q; cmdbuf_addr <= ahb_haddr_q;
end end
end end
always @(posedge clock or posedge reset) begin always @(posedge clock or posedge reset) begin
if (reset) begin if (reset) begin
cmdbuf_wdata <= 64'h0; cmdbuf_wdata <= 64'h0;
end else if (_T_179) begin end else if (_T_35) begin
cmdbuf_wdata <= io_ahb_sig_out_hwdata; cmdbuf_wdata <= io_ahb_sig_out_hwdata;
end end
end end

101
src/main/scala/lib/ahb_to_axi4.scala
View File

@ -24,41 +24,51 @@ class ahb_to_axi4(TAG : Int) extends Module with lib with RequireAsyncReset {
// Buffer signals (one entry buffer) // Buffer signals (one entry buffer)
val buf_read_error_in = WireInit(false.B) val buf_read_error_in = WireInit(false.B)
val buf_read_error = WireInit(false.B) val ahb_hready = io.ahb.sig.in.hready & io.ahb.hreadyin
val buf_rdata = WireInit(0.U(64.W)) val ahb_htrans_in = Fill(2,io.ahb.hsel) & io.ahb.sig.out.htrans(1,0)
val ahb_hready = WireInit(Bool(), false.B)
val ahb_hready_q = WireInit(Bool(), false.B)
val ahb_htrans_in = WireInit(0.U(2.W))
val ahb_htrans_q = WireInit(0.U(2.W))
val ahb_hsize_q = WireInit(0.U(3.W))
val ahb_hwrite_q = WireInit(Bool(), false.B)
val ahb_haddr_q = WireInit(0.U(32.W))
val ahb_hwdata_q = WireInit(0.U(64.W)) val ahb_hwdata_q = WireInit(0.U(64.W))
val ahb_hresp_q = WireInit(Bool(), false.B)
// signals needed for the read data coming back from the core and to block any further commands as AHB is a blocking bus // signals needed for the read data coming back from the core and to block any further commands as AHB is a blocking bus
val buf_rdata_en = WireInit(Bool(), false.B) val buf_rdata_en = WireInit(Bool(), false.B)
val ahb_addr_clk_en = WireInit(Bool(), false.B)
val buf_rdata_clk_en = WireInit(Bool(), false.B)
val bus_clk = Wire(Clock()) val bus_clk = Wire(Clock())
val ahb_addr_clk = Wire(Clock()) val ahb_addr_clk = Wire(Clock())
val buf_rdata_clk = Wire(Clock()) val buf_rdata_clk = Wire(Clock())
val ahb_addr_clk_en = io.bus_clk_en & (ahb_hready & io.ahb.sig.out.htrans(1))
val buf_rdata_clk_en = io.bus_clk_en & buf_rdata_en
if(RV_FPGA_OPTIMIZE){
bus_clk := 0.B.asClock()
ahb_addr_clk := 0.B.asClock()
buf_rdata_clk := 0.B.asClock()
}
else {
bus_clk := rvclkhdr(clock, io.bus_clk_en, io.scan_mode)
ahb_addr_clk := rvclkhdr(clock, ahb_addr_clk_en, io.scan_mode)
buf_rdata_clk := rvclkhdr(clock, buf_rdata_clk_en, io.scan_mode)
}
val buf_read_error = rvdff_fpga(buf_read_error_in,bus_clk,io.bus_clk_en,clock)
val buf_rdata = rvdff_fpga(io.axi.r.bits.data,buf_rdata_clk,buf_rdata_clk_en,clock)
val ahb_hresp_q = rvdff_fpga (io.ahb.sig.in.hresp,bus_clk,io.bus_clk_en,clock)
val ahb_hsize_q = rvdff_fpga (io.ahb.sig.out.hsize,ahb_addr_clk,ahb_addr_clk_en,clock)
val ahb_hwrite_q = rvdff_fpga (io.ahb.sig.out.hwrite,ahb_addr_clk,ahb_addr_clk_en,clock)
val ahb_haddr_q = rvdff_fpga (io.ahb.sig.out.haddr,ahb_addr_clk,ahb_addr_clk_en,clock)
val ahb_hready_q = rvdff_fpga (ahb_hready,bus_clk,io.bus_clk_en,clock)
val ahb_htrans_q = rvdff_fpga (ahb_htrans_in,bus_clk,io.bus_clk_en,clock)
// Command buffer is the holding station where we convert to AXI and send to core // Command buffer is the holding station where we convert to AXI and send to core
val cmdbuf_wr_en = WireInit(Bool(), false.B) val cmdbuf_wr_en = WireInit(Bool(), false.B)
val cmdbuf_rst = WireInit(Bool(), false.B) val cmdbuf_write = rvdffs_fpga(ahb_hwrite_q, cmdbuf_wr_en.asBool(),bus_clk,io.bus_clk_en,clock)
val cmdbuf_full = WireInit(Bool(), false.B) val cmdbuf_rst = (((io.axi.aw.valid & io.axi.aw.ready) | (io.axi.ar.valid & io.axi.ar.ready)) & !cmdbuf_wr_en) | (io.ahb.sig.in.hresp & !cmdbuf_write)
val cmdbuf_vld = WireInit(Bool(), false.B) val cmdbuf_vld = rvdffsc_fpga("b1".U,cmdbuf_wr_en.asBool(),cmdbuf_rst,bus_clk,io.bus_clk_en,clock)
val cmdbuf_write = WireInit(Bool(), false.B) val cmdbuf_full = (cmdbuf_vld & !((io.axi.aw.valid & io.axi.aw.ready) | (io.axi.ar.valid & io.axi.ar.ready)))
val cmdbuf_size = WireInit(0.U(2.W)) val cmdbuf_size = rvdffs_fpga(ahb_hsize_q(1,0), cmdbuf_wr_en.asBool(),bus_clk,io.bus_clk_en,clock)
val cmdbuf_wstrb = WireInit(0.U(8.W)) val cmdbuf_wstrb = rvdffs_fpga(master_wstrb, cmdbuf_wr_en.asBool(),bus_clk,io.bus_clk_en,clock)
val cmdbuf_addr = WireInit(0.U(32.W)) val cmdbuf_addr = rvdffe(ahb_haddr_q, cmdbuf_wr_en.asBool()& io.bus_clk_en,clock,io.scan_mode)
val cmdbuf_wdata = WireInit(0.U(64.W)) val cmdbuf_wdata = rvdffe(io.ahb.sig.out.hwdata, cmdbuf_wr_en.asBool()& io.bus_clk_en,clock,io.scan_mode)
// Address check dccm // Address check dccm
val (ahb_addr_in_dccm_region_nc,ahb_addr_in_dccm) = rvrangecheck(DCCM_SADR,DCCM_SIZE,ahb_haddr_q) val (ahb_addr_in_dccm_region_nc,ahb_addr_in_dccm) = rvrangecheck(DCCM_SADR,DCCM_SIZE,ahb_haddr_q)
val (ahb_addr_in_iccm_region_nc,ahb_addr_in_iccm) = if(ICCM_ENABLE) rvrangecheck(ICCM_SADR ,ICCM_SIZE,ahb_haddr_q) else (0.U,0.U) val (ahb_addr_in_iccm_region_nc,ahb_addr_in_iccm) = if(ICCM_ENABLE) rvrangecheck(ICCM_SADR ,ICCM_SIZE,ahb_haddr_q) else (0.U,0.U)
val (ahb_addr_in_pic_region_nc, ahb_addr_in_pic) = rvrangecheck(PIC_BASE_ADDR,PIC_SIZE,ahb_haddr_q) val (ahb_addr_in_pic_region_nc, ahb_addr_in_pic) = rvrangecheck(PIC_BASE_ADDR,PIC_SIZE,ahb_haddr_q)
// PIC memory address check // PIC memory address check
// FSM to control the bus states and when to block the hready and load the command buffer // FSM to control the bus states and when to block the hready and load the command buffer
val buf_state = WireInit(idle) val buf_state = WireInit(idle)
@ -100,8 +110,6 @@ class ahb_to_axi4(TAG : Int) extends Module with lib with RequireAsyncReset {
// AHB signals // AHB signals
io.ahb.sig.in.hready := Mux(io.ahb.sig.in.hresp,(ahb_hresp_q & !ahb_hready_q), ((!cmdbuf_full | (buf_state === idle)) & !(buf_state === rd | buf_state === pend) & !buf_read_error)) io.ahb.sig.in.hready := Mux(io.ahb.sig.in.hresp,(ahb_hresp_q & !ahb_hready_q), ((!cmdbuf_full | (buf_state === idle)) & !(buf_state === rd | buf_state === pend) & !buf_read_error))
ahb_hready := io.ahb.sig.in.hready & io.ahb.hreadyin
ahb_htrans_in := Fill(2,io.ahb.hsel) & io.ahb.sig.out.htrans(1,0)
io.ahb.sig.in.hrdata := buf_rdata(63,0) io.ahb.sig.in.hrdata := buf_rdata(63,0)
io.ahb.sig.in.hresp := ((ahb_htrans_q(1,0) =/= 0.U) & (buf_state =/= idle) & io.ahb.sig.in.hresp := ((ahb_htrans_q(1,0) =/= 0.U) & (buf_state =/= idle) &
((!(ahb_addr_in_dccm | ahb_addr_in_iccm)) | // request not for ICCM or DCCM ((!(ahb_addr_in_dccm | ahb_addr_in_iccm)) | // request not for ICCM or DCCM
@ -111,46 +119,9 @@ class ahb_to_axi4(TAG : Int) extends Module with lib with RequireAsyncReset {
((ahb_hsize_q(2,0) === 3.U) & (ahb_haddr_q(2,0)).orR))) | // DW size but unaligned ((ahb_hsize_q(2,0) === 3.U) & (ahb_haddr_q(2,0)).orR))) | // DW size but unaligned
buf_read_error | // Read ECC error buf_read_error | // Read ECC error
(ahb_hresp_q & !ahb_hready_q) (ahb_hresp_q & !ahb_hready_q)
// Buffer signals - needed for the read data and ECC error response
buf_rdata := rvdff_fpga(io.axi.r.bits.data,buf_rdata_clk,buf_rdata_clk_en,clock)
buf_read_error := rvdff_fpga(buf_read_error_in,bus_clk,io.bus_clk_en,clock)
// All the Master signals are captured before presenting it to the command buffer. We check for Hresp before sending it to the cmd buffer.
ahb_hresp_q := rvdff_fpga (io.ahb.sig.in.hresp,bus_clk,io.bus_clk_en,clock)
ahb_hready_q := rvdff_fpga (ahb_hready,bus_clk,io.bus_clk_en,clock)
ahb_htrans_q := rvdff_fpga (ahb_htrans_in,bus_clk,io.bus_clk_en,clock)
ahb_hsize_q := rvdff_fpga (io.ahb.sig.out.hsize,ahb_addr_clk,ahb_addr_clk_en,clock)
ahb_hwrite_q := rvdff_fpga (io.ahb.sig.out.hwrite,ahb_addr_clk,ahb_addr_clk_en,clock)
ahb_haddr_q := rvdff_fpga (io.ahb.sig.out.haddr,ahb_addr_clk,ahb_addr_clk_en,clock)
// Clock header logic
ahb_addr_clk_en := io.bus_clk_en & (ahb_hready & io.ahb.sig.out.htrans(1))
buf_rdata_clk_en := io.bus_clk_en & buf_rdata_en
if(RV_FPGA_OPTIMIZE){
bus_clk := 0.B.asClock()
ahb_addr_clk := 0.B.asClock()
buf_rdata_clk := 0.B.asClock()
}
else {
bus_clk := rvclkhdr(clock, io.bus_clk_en, io.scan_mode)
ahb_addr_clk := rvclkhdr(clock, ahb_addr_clk_en, io.scan_mode)
buf_rdata_clk := rvclkhdr(clock, buf_rdata_clk_en, io.scan_mode)
}
cmdbuf_rst := (((io.axi.aw.valid & io.axi.aw.ready) | (io.axi.ar.valid & io.axi.ar.ready)) & !cmdbuf_wr_en) | (io.ahb.sig.in.hresp & !cmdbuf_write)
cmdbuf_full := (cmdbuf_vld & !((io.axi.aw.valid & io.axi.aw.ready) | (io.axi.ar.valid & io.axi.ar.ready)))
//rvdffsc
cmdbuf_vld := rvdffsc_fpga("b1".U,cmdbuf_wr_en.asBool(),cmdbuf_rst,bus_clk,io.bus_clk_en,clock)
//dffs
cmdbuf_write := rvdffs_fpga(ahb_hwrite_q, cmdbuf_wr_en.asBool(),bus_clk,io.bus_clk_en,clock)
cmdbuf_size := rvdffs_fpga(ahb_hsize_q(1,0), cmdbuf_wr_en.asBool(),bus_clk,io.bus_clk_en,clock)
cmdbuf_wstrb := rvdffs_fpga(master_wstrb, cmdbuf_wr_en.asBool(),bus_clk,io.bus_clk_en,clock)
//rvdffe
cmdbuf_addr := rvdffe(ahb_haddr_q, cmdbuf_wr_en.asBool()& io.bus_clk_en,clock,io.scan_mode)
cmdbuf_wdata := rvdffe(io.ahb.sig.out.hwdata, cmdbuf_wr_en.asBool()& io.bus_clk_en,clock,io.scan_mode)
// AXI Write Command Channel // AXI Write Command Channel
io.axi.aw.valid := cmdbuf_vld & cmdbuf_write io.axi.aw.valid := cmdbuf_vld & cmdbuf_write
io.axi.aw.bits.id := Fill(TAG, 0.U) io.axi.aw.bits.id := Fill(TAG, 0.U)
io.axi.aw.bits.addr := cmdbuf_addr io.axi.aw.bits.addr := cmdbuf_addr
io.axi.aw.bits.size := Cat("b0".U, cmdbuf_size(1, 0)) io.axi.aw.bits.size := Cat("b0".U, cmdbuf_size(1, 0))
@ -158,14 +129,14 @@ class ahb_to_axi4(TAG : Int) extends Module with lib with RequireAsyncReset {
io.axi.aw.bits.len := Fill(8, 0.U) io.axi.aw.bits.len := Fill(8, 0.U)
io.axi.aw.bits.burst := "b01".U(2.W) io.axi.aw.bits.burst := "b01".U(2.W)
// AXI Write Data Channel - This is tied to the command channel as we only write the command buffer once we have the data. // AXI Write Data Channel - This is tied to the command channel as we only write the command buffer once we have the data.
io.axi.w.valid := cmdbuf_vld & cmdbuf_write io.axi.w.valid := cmdbuf_vld & cmdbuf_write
io.axi.w.bits.data := cmdbuf_wdata io.axi.w.bits.data := cmdbuf_wdata
io.axi.w.bits.strb := cmdbuf_wstrb io.axi.w.bits.strb := cmdbuf_wstrb
io.axi.w.bits.last := "b1".U io.axi.w.bits.last := "b1".U
// AXI Write Response - Always ready. AHB does not require a write response. // AXI Write Response - Always ready. AHB does not require a write response.
io.axi.b.ready := "b1".U io.axi.b.ready := "b1".U
// AXI Read Channels // AXI Read Channels
io.axi.ar.valid := cmdbuf_vld & !cmdbuf_write io.axi.ar.valid := cmdbuf_vld & !cmdbuf_write
io.axi.ar.bits.id := Fill(TAG, 0.U) io.axi.ar.bits.id := Fill(TAG, 0.U)
io.axi.ar.bits.addr := cmdbuf_addr io.axi.ar.bits.addr := cmdbuf_addr
io.axi.ar.bits.size := Cat("b0".U, cmdbuf_size(1, 0)) io.axi.ar.bits.size := Cat("b0".U, cmdbuf_size(1, 0))

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