diff --git a/quasar_wrapper.fir b/quasar_wrapper.fir
index 73543600..67bd698b 100644
--- a/quasar_wrapper.fir
+++ b/quasar_wrapper.fir
@@ -68700,105 +68700,113 @@ circuit quasar_wrapper :
     i0_d_c.load <= _T_699 @[dec_decode_ctl.scala 617:29]
     node _T_700 = and(i0_dp.alu, i0_legal_decode_d) @[dec_decode_ctl.scala 618:44]
     i0_d_c.alu <= _T_700 @[dec_decode_ctl.scala 618:29]
-    node _T_701 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 620:71]
-    reg i0_x_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>}, io.active_clk @[Reg.scala 15:16]
-    when _T_701 : @[Reg.scala 16:19]
-      i0_x_c.alu <= i0_d_c.alu @[Reg.scala 16:23]
-      i0_x_c.load <= i0_d_c.load @[Reg.scala 16:23]
-      i0_x_c.mul <= i0_d_c.mul @[Reg.scala 16:23]
-      skip @[Reg.scala 16:19]
-    node _T_702 = bits(i0_r_ctl_en, 0, 0) @[dec_decode_ctl.scala 621:71]
-    reg i0_r_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>}, io.active_clk @[Reg.scala 15:16]
-    when _T_702 : @[Reg.scala 16:19]
-      i0_r_c.alu <= i0_x_c.alu @[Reg.scala 16:23]
-      i0_r_c.load <= i0_x_c.load @[Reg.scala 16:23]
-      i0_r_c.mul <= i0_x_c.mul @[Reg.scala 16:23]
-      skip @[Reg.scala 16:19]
-    node _T_703 = bits(i0_pipe_en, 3, 1) @[dec_decode_ctl.scala 622:91]
-    reg _T_704 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 622:80]
-    _T_704 <= _T_703 @[dec_decode_ctl.scala 622:80]
-    node _T_705 = cat(io.dec_aln.dec_i0_decode_d, _T_704) @[Cat.scala 29:58]
-    i0_pipe_en <= _T_705 @[dec_decode_ctl.scala 622:14]
-    node _T_706 = bits(i0_pipe_en, 3, 2) @[dec_decode_ctl.scala 624:43]
-    node _T_707 = orr(_T_706) @[dec_decode_ctl.scala 624:49]
-    node _T_708 = or(_T_707, io.clk_override) @[dec_decode_ctl.scala 624:53]
-    i0_x_ctl_en <= _T_708 @[dec_decode_ctl.scala 624:29]
-    node _T_709 = bits(i0_pipe_en, 2, 1) @[dec_decode_ctl.scala 625:43]
-    node _T_710 = orr(_T_709) @[dec_decode_ctl.scala 625:49]
-    node _T_711 = or(_T_710, io.clk_override) @[dec_decode_ctl.scala 625:53]
-    i0_r_ctl_en <= _T_711 @[dec_decode_ctl.scala 625:29]
-    node _T_712 = bits(i0_pipe_en, 1, 0) @[dec_decode_ctl.scala 626:43]
-    node _T_713 = orr(_T_712) @[dec_decode_ctl.scala 626:49]
-    node _T_714 = or(_T_713, io.clk_override) @[dec_decode_ctl.scala 626:53]
-    i0_wb_ctl_en <= _T_714 @[dec_decode_ctl.scala 626:29]
-    node _T_715 = bits(i0_pipe_en, 3, 3) @[dec_decode_ctl.scala 627:44]
-    node _T_716 = or(_T_715, io.clk_override) @[dec_decode_ctl.scala 627:50]
-    i0_x_data_en <= _T_716 @[dec_decode_ctl.scala 627:29]
-    node _T_717 = bits(i0_pipe_en, 2, 2) @[dec_decode_ctl.scala 628:44]
-    node _T_718 = or(_T_717, io.clk_override) @[dec_decode_ctl.scala 628:50]
-    i0_r_data_en <= _T_718 @[dec_decode_ctl.scala 628:29]
-    node _T_719 = bits(i0_pipe_en, 1, 1) @[dec_decode_ctl.scala 629:44]
-    node _T_720 = or(_T_719, io.clk_override) @[dec_decode_ctl.scala 629:50]
-    i0_wb_data_en <= _T_720 @[dec_decode_ctl.scala 629:29]
-    node _T_721 = bits(i0_pipe_en, 0, 0) @[dec_decode_ctl.scala 630:44]
-    node _T_722 = or(_T_721, io.clk_override) @[dec_decode_ctl.scala 630:50]
-    i0_wb1_data_en <= _T_722 @[dec_decode_ctl.scala 630:29]
-    node _T_723 = cat(i0_x_data_en, i0_r_data_en) @[Cat.scala 29:58]
-    io.decode_exu.dec_data_en <= _T_723 @[dec_decode_ctl.scala 632:38]
-    node _T_724 = cat(i0_x_ctl_en, i0_r_ctl_en) @[Cat.scala 29:58]
-    io.decode_exu.dec_ctl_en <= _T_724 @[dec_decode_ctl.scala 633:38]
+    wire _T_701 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 620:70]
+    _T_701.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 620:70]
+    _T_701.load <= UInt<1>("h00") @[dec_decode_ctl.scala 620:70]
+    _T_701.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 620:70]
+    node _T_702 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 620:92]
+    reg i0_x_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>}, io.active_clk with : (reset => (reset, _T_701)) @[Reg.scala 27:20]
+    when _T_702 : @[Reg.scala 28:19]
+      i0_x_c.alu <= i0_d_c.alu @[Reg.scala 28:23]
+      i0_x_c.load <= i0_d_c.load @[Reg.scala 28:23]
+      i0_x_c.mul <= i0_d_c.mul @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    wire _T_703 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 621:70]
+    _T_703.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 621:70]
+    _T_703.load <= UInt<1>("h00") @[dec_decode_ctl.scala 621:70]
+    _T_703.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 621:70]
+    node _T_704 = bits(i0_r_ctl_en, 0, 0) @[dec_decode_ctl.scala 621:92]
+    reg i0_r_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>}, io.active_clk with : (reset => (reset, _T_703)) @[Reg.scala 27:20]
+    when _T_704 : @[Reg.scala 28:19]
+      i0_r_c.alu <= i0_x_c.alu @[Reg.scala 28:23]
+      i0_r_c.load <= i0_x_c.load @[Reg.scala 28:23]
+      i0_r_c.mul <= i0_x_c.mul @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    node _T_705 = bits(i0_pipe_en, 3, 1) @[dec_decode_ctl.scala 622:91]
+    reg _T_706 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 622:80]
+    _T_706 <= _T_705 @[dec_decode_ctl.scala 622:80]
+    node _T_707 = cat(io.dec_aln.dec_i0_decode_d, _T_706) @[Cat.scala 29:58]
+    i0_pipe_en <= _T_707 @[dec_decode_ctl.scala 622:14]
+    node _T_708 = bits(i0_pipe_en, 3, 2) @[dec_decode_ctl.scala 624:43]
+    node _T_709 = orr(_T_708) @[dec_decode_ctl.scala 624:49]
+    node _T_710 = or(_T_709, io.clk_override) @[dec_decode_ctl.scala 624:53]
+    i0_x_ctl_en <= _T_710 @[dec_decode_ctl.scala 624:29]
+    node _T_711 = bits(i0_pipe_en, 2, 1) @[dec_decode_ctl.scala 625:43]
+    node _T_712 = orr(_T_711) @[dec_decode_ctl.scala 625:49]
+    node _T_713 = or(_T_712, io.clk_override) @[dec_decode_ctl.scala 625:53]
+    i0_r_ctl_en <= _T_713 @[dec_decode_ctl.scala 625:29]
+    node _T_714 = bits(i0_pipe_en, 1, 0) @[dec_decode_ctl.scala 626:43]
+    node _T_715 = orr(_T_714) @[dec_decode_ctl.scala 626:49]
+    node _T_716 = or(_T_715, io.clk_override) @[dec_decode_ctl.scala 626:53]
+    i0_wb_ctl_en <= _T_716 @[dec_decode_ctl.scala 626:29]
+    node _T_717 = bits(i0_pipe_en, 3, 3) @[dec_decode_ctl.scala 627:44]
+    node _T_718 = or(_T_717, io.clk_override) @[dec_decode_ctl.scala 627:50]
+    i0_x_data_en <= _T_718 @[dec_decode_ctl.scala 627:29]
+    node _T_719 = bits(i0_pipe_en, 2, 2) @[dec_decode_ctl.scala 628:44]
+    node _T_720 = or(_T_719, io.clk_override) @[dec_decode_ctl.scala 628:50]
+    i0_r_data_en <= _T_720 @[dec_decode_ctl.scala 628:29]
+    node _T_721 = bits(i0_pipe_en, 1, 1) @[dec_decode_ctl.scala 629:44]
+    node _T_722 = or(_T_721, io.clk_override) @[dec_decode_ctl.scala 629:50]
+    i0_wb_data_en <= _T_722 @[dec_decode_ctl.scala 629:29]
+    node _T_723 = bits(i0_pipe_en, 0, 0) @[dec_decode_ctl.scala 630:44]
+    node _T_724 = or(_T_723, io.clk_override) @[dec_decode_ctl.scala 630:50]
+    i0_wb1_data_en <= _T_724 @[dec_decode_ctl.scala 630:29]
+    node _T_725 = cat(i0_x_data_en, i0_r_data_en) @[Cat.scala 29:58]
+    io.decode_exu.dec_data_en <= _T_725 @[dec_decode_ctl.scala 632:38]
+    node _T_726 = cat(i0_x_ctl_en, i0_r_ctl_en) @[Cat.scala 29:58]
+    io.decode_exu.dec_ctl_en <= _T_726 @[dec_decode_ctl.scala 633:38]
     d_d.bits.i0rd <= i0r.rd @[dec_decode_ctl.scala 635:34]
-    node _T_725 = and(i0_rd_en_d, i0_legal_decode_d) @[dec_decode_ctl.scala 636:50]
-    d_d.bits.i0v <= _T_725 @[dec_decode_ctl.scala 636:34]
+    node _T_727 = and(i0_rd_en_d, i0_legal_decode_d) @[dec_decode_ctl.scala 636:50]
+    d_d.bits.i0v <= _T_727 @[dec_decode_ctl.scala 636:34]
     d_d.valid <= io.dec_aln.dec_i0_decode_d @[dec_decode_ctl.scala 637:27]
-    node _T_726 = and(i0_dp.load, i0_legal_decode_d) @[dec_decode_ctl.scala 639:50]
-    d_d.bits.i0load <= _T_726 @[dec_decode_ctl.scala 639:34]
-    node _T_727 = and(i0_dp.store, i0_legal_decode_d) @[dec_decode_ctl.scala 640:50]
-    d_d.bits.i0store <= _T_727 @[dec_decode_ctl.scala 640:34]
-    node _T_728 = and(i0_dp.div, i0_legal_decode_d) @[dec_decode_ctl.scala 641:50]
-    d_d.bits.i0div <= _T_728 @[dec_decode_ctl.scala 641:34]
-    node _T_729 = and(io.dec_csr_wen_unq_d, i0_legal_decode_d) @[dec_decode_ctl.scala 643:61]
-    d_d.bits.csrwen <= _T_729 @[dec_decode_ctl.scala 643:34]
-    node _T_730 = and(i0_csr_write_only_d, io.dec_aln.dec_i0_decode_d) @[dec_decode_ctl.scala 644:58]
-    d_d.bits.csrwonly <= _T_730 @[dec_decode_ctl.scala 644:34]
-    node _T_731 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 645:40]
-    d_d.bits.csrwaddr <= _T_731 @[dec_decode_ctl.scala 645:34]
-    node _T_732 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 647:34]
+    node _T_728 = and(i0_dp.load, i0_legal_decode_d) @[dec_decode_ctl.scala 639:50]
+    d_d.bits.i0load <= _T_728 @[dec_decode_ctl.scala 639:34]
+    node _T_729 = and(i0_dp.store, i0_legal_decode_d) @[dec_decode_ctl.scala 640:50]
+    d_d.bits.i0store <= _T_729 @[dec_decode_ctl.scala 640:34]
+    node _T_730 = and(i0_dp.div, i0_legal_decode_d) @[dec_decode_ctl.scala 641:50]
+    d_d.bits.i0div <= _T_730 @[dec_decode_ctl.scala 641:34]
+    node _T_731 = and(io.dec_csr_wen_unq_d, i0_legal_decode_d) @[dec_decode_ctl.scala 643:61]
+    d_d.bits.csrwen <= _T_731 @[dec_decode_ctl.scala 643:34]
+    node _T_732 = and(i0_csr_write_only_d, io.dec_aln.dec_i0_decode_d) @[dec_decode_ctl.scala 644:58]
+    d_d.bits.csrwonly <= _T_732 @[dec_decode_ctl.scala 644:34]
+    node _T_733 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 645:40]
+    d_d.bits.csrwaddr <= _T_733 @[dec_decode_ctl.scala 645:34]
+    node _T_734 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 647:34]
     inst rvclkhdr_7 of rvclkhdr_668 @[lib.scala 362:23]
     rvclkhdr_7.clock <= clock
     rvclkhdr_7.reset <= reset
     rvclkhdr_7.io.clk <= clock @[lib.scala 364:18]
-    rvclkhdr_7.io.en <= _T_732 @[lib.scala 365:17]
+    rvclkhdr_7.io.en <= _T_734 @[lib.scala 365:17]
     rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 366:24]
-    wire _T_733 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[lib.scala 368:33]
-    _T_733.bits.csrwaddr <= UInt<12>("h00") @[lib.scala 368:33]
-    _T_733.bits.csrwonly <= UInt<1>("h00") @[lib.scala 368:33]
-    _T_733.bits.csrwen <= UInt<1>("h00") @[lib.scala 368:33]
-    _T_733.bits.i0v <= UInt<1>("h00") @[lib.scala 368:33]
-    _T_733.bits.i0div <= UInt<1>("h00") @[lib.scala 368:33]
-    _T_733.bits.i0store <= UInt<1>("h00") @[lib.scala 368:33]
-    _T_733.bits.i0load <= UInt<1>("h00") @[lib.scala 368:33]
-    _T_733.bits.i0rd <= UInt<5>("h00") @[lib.scala 368:33]
-    _T_733.valid <= UInt<1>("h00") @[lib.scala 368:33]
-    reg _T_734 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, rvclkhdr_7.io.l1clk with : (reset => (reset, _T_733)) @[lib.scala 368:16]
-    _T_734.bits.csrwaddr <= d_d.bits.csrwaddr @[lib.scala 368:16]
-    _T_734.bits.csrwonly <= d_d.bits.csrwonly @[lib.scala 368:16]
-    _T_734.bits.csrwen <= d_d.bits.csrwen @[lib.scala 368:16]
-    _T_734.bits.i0v <= d_d.bits.i0v @[lib.scala 368:16]
-    _T_734.bits.i0div <= d_d.bits.i0div @[lib.scala 368:16]
-    _T_734.bits.i0store <= d_d.bits.i0store @[lib.scala 368:16]
-    _T_734.bits.i0load <= d_d.bits.i0load @[lib.scala 368:16]
-    _T_734.bits.i0rd <= d_d.bits.i0rd @[lib.scala 368:16]
-    _T_734.valid <= d_d.valid @[lib.scala 368:16]
-    x_d.bits.csrwaddr <= _T_734.bits.csrwaddr @[dec_decode_ctl.scala 647:7]
-    x_d.bits.csrwonly <= _T_734.bits.csrwonly @[dec_decode_ctl.scala 647:7]
-    x_d.bits.csrwen <= _T_734.bits.csrwen @[dec_decode_ctl.scala 647:7]
-    x_d.bits.i0v <= _T_734.bits.i0v @[dec_decode_ctl.scala 647:7]
-    x_d.bits.i0div <= _T_734.bits.i0div @[dec_decode_ctl.scala 647:7]
-    x_d.bits.i0store <= _T_734.bits.i0store @[dec_decode_ctl.scala 647:7]
-    x_d.bits.i0load <= _T_734.bits.i0load @[dec_decode_ctl.scala 647:7]
-    x_d.bits.i0rd <= _T_734.bits.i0rd @[dec_decode_ctl.scala 647:7]
-    x_d.valid <= _T_734.valid @[dec_decode_ctl.scala 647:7]
+    wire _T_735 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[lib.scala 368:33]
+    _T_735.bits.csrwaddr <= UInt<12>("h00") @[lib.scala 368:33]
+    _T_735.bits.csrwonly <= UInt<1>("h00") @[lib.scala 368:33]
+    _T_735.bits.csrwen <= UInt<1>("h00") @[lib.scala 368:33]
+    _T_735.bits.i0v <= UInt<1>("h00") @[lib.scala 368:33]
+    _T_735.bits.i0div <= UInt<1>("h00") @[lib.scala 368:33]
+    _T_735.bits.i0store <= UInt<1>("h00") @[lib.scala 368:33]
+    _T_735.bits.i0load <= UInt<1>("h00") @[lib.scala 368:33]
+    _T_735.bits.i0rd <= UInt<5>("h00") @[lib.scala 368:33]
+    _T_735.valid <= UInt<1>("h00") @[lib.scala 368:33]
+    reg _T_736 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, rvclkhdr_7.io.l1clk with : (reset => (reset, _T_735)) @[lib.scala 368:16]
+    _T_736.bits.csrwaddr <= d_d.bits.csrwaddr @[lib.scala 368:16]
+    _T_736.bits.csrwonly <= d_d.bits.csrwonly @[lib.scala 368:16]
+    _T_736.bits.csrwen <= d_d.bits.csrwen @[lib.scala 368:16]
+    _T_736.bits.i0v <= d_d.bits.i0v @[lib.scala 368:16]
+    _T_736.bits.i0div <= d_d.bits.i0div @[lib.scala 368:16]
+    _T_736.bits.i0store <= d_d.bits.i0store @[lib.scala 368:16]
+    _T_736.bits.i0load <= d_d.bits.i0load @[lib.scala 368:16]
+    _T_736.bits.i0rd <= d_d.bits.i0rd @[lib.scala 368:16]
+    _T_736.valid <= d_d.valid @[lib.scala 368:16]
+    x_d.bits.csrwaddr <= _T_736.bits.csrwaddr @[dec_decode_ctl.scala 647:7]
+    x_d.bits.csrwonly <= _T_736.bits.csrwonly @[dec_decode_ctl.scala 647:7]
+    x_d.bits.csrwen <= _T_736.bits.csrwen @[dec_decode_ctl.scala 647:7]
+    x_d.bits.i0v <= _T_736.bits.i0v @[dec_decode_ctl.scala 647:7]
+    x_d.bits.i0div <= _T_736.bits.i0div @[dec_decode_ctl.scala 647:7]
+    x_d.bits.i0store <= _T_736.bits.i0store @[dec_decode_ctl.scala 647:7]
+    x_d.bits.i0load <= _T_736.bits.i0load @[dec_decode_ctl.scala 647:7]
+    x_d.bits.i0rd <= _T_736.bits.i0rd @[dec_decode_ctl.scala 647:7]
+    x_d.valid <= _T_736.valid @[dec_decode_ctl.scala 647:7]
     wire x_d_in : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 648:20]
     x_d_in.bits.csrwaddr <= x_d.bits.csrwaddr @[dec_decode_ctl.scala 649:10]
     x_d_in.bits.csrwonly <= x_d.bits.csrwonly @[dec_decode_ctl.scala 649:10]
@@ -68809,52 +68817,52 @@ circuit quasar_wrapper :
     x_d_in.bits.i0load <= x_d.bits.i0load @[dec_decode_ctl.scala 649:10]
     x_d_in.bits.i0rd <= x_d.bits.i0rd @[dec_decode_ctl.scala 649:10]
     x_d_in.valid <= x_d.valid @[dec_decode_ctl.scala 649:10]
-    node _T_735 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 650:49]
-    node _T_736 = and(x_d.bits.i0v, _T_735) @[dec_decode_ctl.scala 650:47]
-    node _T_737 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 650:78]
-    node _T_738 = and(_T_736, _T_737) @[dec_decode_ctl.scala 650:76]
-    x_d_in.bits.i0v <= _T_738 @[dec_decode_ctl.scala 650:27]
-    node _T_739 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 651:35]
-    node _T_740 = and(x_d.valid, _T_739) @[dec_decode_ctl.scala 651:33]
-    node _T_741 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 651:64]
-    node _T_742 = and(_T_740, _T_741) @[dec_decode_ctl.scala 651:62]
-    x_d_in.valid <= _T_742 @[dec_decode_ctl.scala 651:20]
-    node _T_743 = bits(i0_r_ctl_en, 0, 0) @[dec_decode_ctl.scala 653:36]
+    node _T_737 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 650:49]
+    node _T_738 = and(x_d.bits.i0v, _T_737) @[dec_decode_ctl.scala 650:47]
+    node _T_739 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 650:78]
+    node _T_740 = and(_T_738, _T_739) @[dec_decode_ctl.scala 650:76]
+    x_d_in.bits.i0v <= _T_740 @[dec_decode_ctl.scala 650:27]
+    node _T_741 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 651:35]
+    node _T_742 = and(x_d.valid, _T_741) @[dec_decode_ctl.scala 651:33]
+    node _T_743 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 651:64]
+    node _T_744 = and(_T_742, _T_743) @[dec_decode_ctl.scala 651:62]
+    x_d_in.valid <= _T_744 @[dec_decode_ctl.scala 651:20]
+    node _T_745 = bits(i0_r_ctl_en, 0, 0) @[dec_decode_ctl.scala 653:36]
     inst rvclkhdr_8 of rvclkhdr_669 @[lib.scala 362:23]
     rvclkhdr_8.clock <= clock
     rvclkhdr_8.reset <= reset
     rvclkhdr_8.io.clk <= clock @[lib.scala 364:18]
-    rvclkhdr_8.io.en <= _T_743 @[lib.scala 365:17]
+    rvclkhdr_8.io.en <= _T_745 @[lib.scala 365:17]
     rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 366:24]
-    wire _T_744 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[lib.scala 368:33]
-    _T_744.bits.csrwaddr <= UInt<12>("h00") @[lib.scala 368:33]
-    _T_744.bits.csrwonly <= UInt<1>("h00") @[lib.scala 368:33]
-    _T_744.bits.csrwen <= UInt<1>("h00") @[lib.scala 368:33]
-    _T_744.bits.i0v <= UInt<1>("h00") @[lib.scala 368:33]
-    _T_744.bits.i0div <= UInt<1>("h00") @[lib.scala 368:33]
-    _T_744.bits.i0store <= UInt<1>("h00") @[lib.scala 368:33]
-    _T_744.bits.i0load <= UInt<1>("h00") @[lib.scala 368:33]
-    _T_744.bits.i0rd <= UInt<5>("h00") @[lib.scala 368:33]
-    _T_744.valid <= UInt<1>("h00") @[lib.scala 368:33]
-    reg _T_745 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, rvclkhdr_8.io.l1clk with : (reset => (reset, _T_744)) @[lib.scala 368:16]
-    _T_745.bits.csrwaddr <= x_d_in.bits.csrwaddr @[lib.scala 368:16]
-    _T_745.bits.csrwonly <= x_d_in.bits.csrwonly @[lib.scala 368:16]
-    _T_745.bits.csrwen <= x_d_in.bits.csrwen @[lib.scala 368:16]
-    _T_745.bits.i0v <= x_d_in.bits.i0v @[lib.scala 368:16]
-    _T_745.bits.i0div <= x_d_in.bits.i0div @[lib.scala 368:16]
-    _T_745.bits.i0store <= x_d_in.bits.i0store @[lib.scala 368:16]
-    _T_745.bits.i0load <= x_d_in.bits.i0load @[lib.scala 368:16]
-    _T_745.bits.i0rd <= x_d_in.bits.i0rd @[lib.scala 368:16]
-    _T_745.valid <= x_d_in.valid @[lib.scala 368:16]
-    r_d.bits.csrwaddr <= _T_745.bits.csrwaddr @[dec_decode_ctl.scala 653:7]
-    r_d.bits.csrwonly <= _T_745.bits.csrwonly @[dec_decode_ctl.scala 653:7]
-    r_d.bits.csrwen <= _T_745.bits.csrwen @[dec_decode_ctl.scala 653:7]
-    r_d.bits.i0v <= _T_745.bits.i0v @[dec_decode_ctl.scala 653:7]
-    r_d.bits.i0div <= _T_745.bits.i0div @[dec_decode_ctl.scala 653:7]
-    r_d.bits.i0store <= _T_745.bits.i0store @[dec_decode_ctl.scala 653:7]
-    r_d.bits.i0load <= _T_745.bits.i0load @[dec_decode_ctl.scala 653:7]
-    r_d.bits.i0rd <= _T_745.bits.i0rd @[dec_decode_ctl.scala 653:7]
-    r_d.valid <= _T_745.valid @[dec_decode_ctl.scala 653:7]
+    wire _T_746 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[lib.scala 368:33]
+    _T_746.bits.csrwaddr <= UInt<12>("h00") @[lib.scala 368:33]
+    _T_746.bits.csrwonly <= UInt<1>("h00") @[lib.scala 368:33]
+    _T_746.bits.csrwen <= UInt<1>("h00") @[lib.scala 368:33]
+    _T_746.bits.i0v <= UInt<1>("h00") @[lib.scala 368:33]
+    _T_746.bits.i0div <= UInt<1>("h00") @[lib.scala 368:33]
+    _T_746.bits.i0store <= UInt<1>("h00") @[lib.scala 368:33]
+    _T_746.bits.i0load <= UInt<1>("h00") @[lib.scala 368:33]
+    _T_746.bits.i0rd <= UInt<5>("h00") @[lib.scala 368:33]
+    _T_746.valid <= UInt<1>("h00") @[lib.scala 368:33]
+    reg _T_747 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, rvclkhdr_8.io.l1clk with : (reset => (reset, _T_746)) @[lib.scala 368:16]
+    _T_747.bits.csrwaddr <= x_d_in.bits.csrwaddr @[lib.scala 368:16]
+    _T_747.bits.csrwonly <= x_d_in.bits.csrwonly @[lib.scala 368:16]
+    _T_747.bits.csrwen <= x_d_in.bits.csrwen @[lib.scala 368:16]
+    _T_747.bits.i0v <= x_d_in.bits.i0v @[lib.scala 368:16]
+    _T_747.bits.i0div <= x_d_in.bits.i0div @[lib.scala 368:16]
+    _T_747.bits.i0store <= x_d_in.bits.i0store @[lib.scala 368:16]
+    _T_747.bits.i0load <= x_d_in.bits.i0load @[lib.scala 368:16]
+    _T_747.bits.i0rd <= x_d_in.bits.i0rd @[lib.scala 368:16]
+    _T_747.valid <= x_d_in.valid @[lib.scala 368:16]
+    r_d.bits.csrwaddr <= _T_747.bits.csrwaddr @[dec_decode_ctl.scala 653:7]
+    r_d.bits.csrwonly <= _T_747.bits.csrwonly @[dec_decode_ctl.scala 653:7]
+    r_d.bits.csrwen <= _T_747.bits.csrwen @[dec_decode_ctl.scala 653:7]
+    r_d.bits.i0v <= _T_747.bits.i0v @[dec_decode_ctl.scala 653:7]
+    r_d.bits.i0div <= _T_747.bits.i0div @[dec_decode_ctl.scala 653:7]
+    r_d.bits.i0store <= _T_747.bits.i0store @[dec_decode_ctl.scala 653:7]
+    r_d.bits.i0load <= _T_747.bits.i0load @[dec_decode_ctl.scala 653:7]
+    r_d.bits.i0rd <= _T_747.bits.i0rd @[dec_decode_ctl.scala 653:7]
+    r_d.valid <= _T_747.valid @[dec_decode_ctl.scala 653:7]
     r_d_in.bits.csrwaddr <= r_d.bits.csrwaddr @[dec_decode_ctl.scala 654:10]
     r_d_in.bits.csrwonly <= r_d.bits.csrwonly @[dec_decode_ctl.scala 654:10]
     r_d_in.bits.csrwen <= r_d.bits.csrwen @[dec_decode_ctl.scala 654:10]
@@ -68865,475 +68873,475 @@ circuit quasar_wrapper :
     r_d_in.bits.i0rd <= r_d.bits.i0rd @[dec_decode_ctl.scala 654:10]
     r_d_in.valid <= r_d.valid @[dec_decode_ctl.scala 654:10]
     r_d_in.bits.i0rd <= r_d.bits.i0rd @[dec_decode_ctl.scala 655:22]
-    node _T_746 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 657:51]
-    node _T_747 = and(r_d.bits.i0v, _T_746) @[dec_decode_ctl.scala 657:49]
-    r_d_in.bits.i0v <= _T_747 @[dec_decode_ctl.scala 657:27]
-    node _T_748 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 658:37]
-    node _T_749 = and(r_d.valid, _T_748) @[dec_decode_ctl.scala 658:35]
-    r_d_in.valid <= _T_749 @[dec_decode_ctl.scala 658:20]
-    node _T_750 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 659:51]
-    node _T_751 = and(r_d.bits.i0load, _T_750) @[dec_decode_ctl.scala 659:49]
-    r_d_in.bits.i0load <= _T_751 @[dec_decode_ctl.scala 659:27]
-    node _T_752 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 660:51]
-    node _T_753 = and(r_d.bits.i0store, _T_752) @[dec_decode_ctl.scala 660:49]
-    r_d_in.bits.i0store <= _T_753 @[dec_decode_ctl.scala 660:27]
-    node _T_754 = bits(i0_wb_ctl_en, 0, 0) @[dec_decode_ctl.scala 662:37]
+    node _T_748 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 657:51]
+    node _T_749 = and(r_d.bits.i0v, _T_748) @[dec_decode_ctl.scala 657:49]
+    r_d_in.bits.i0v <= _T_749 @[dec_decode_ctl.scala 657:27]
+    node _T_750 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 658:37]
+    node _T_751 = and(r_d.valid, _T_750) @[dec_decode_ctl.scala 658:35]
+    r_d_in.valid <= _T_751 @[dec_decode_ctl.scala 658:20]
+    node _T_752 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 659:51]
+    node _T_753 = and(r_d.bits.i0load, _T_752) @[dec_decode_ctl.scala 659:49]
+    r_d_in.bits.i0load <= _T_753 @[dec_decode_ctl.scala 659:27]
+    node _T_754 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 660:51]
+    node _T_755 = and(r_d.bits.i0store, _T_754) @[dec_decode_ctl.scala 660:49]
+    r_d_in.bits.i0store <= _T_755 @[dec_decode_ctl.scala 660:27]
+    node _T_756 = bits(i0_wb_ctl_en, 0, 0) @[dec_decode_ctl.scala 662:37]
     inst rvclkhdr_9 of rvclkhdr_670 @[lib.scala 362:23]
     rvclkhdr_9.clock <= clock
     rvclkhdr_9.reset <= reset
     rvclkhdr_9.io.clk <= clock @[lib.scala 364:18]
-    rvclkhdr_9.io.en <= _T_754 @[lib.scala 365:17]
+    rvclkhdr_9.io.en <= _T_756 @[lib.scala 365:17]
     rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 366:24]
-    wire _T_755 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[lib.scala 368:33]
-    _T_755.bits.csrwaddr <= UInt<12>("h00") @[lib.scala 368:33]
-    _T_755.bits.csrwonly <= UInt<1>("h00") @[lib.scala 368:33]
-    _T_755.bits.csrwen <= UInt<1>("h00") @[lib.scala 368:33]
-    _T_755.bits.i0v <= UInt<1>("h00") @[lib.scala 368:33]
-    _T_755.bits.i0div <= UInt<1>("h00") @[lib.scala 368:33]
-    _T_755.bits.i0store <= UInt<1>("h00") @[lib.scala 368:33]
-    _T_755.bits.i0load <= UInt<1>("h00") @[lib.scala 368:33]
-    _T_755.bits.i0rd <= UInt<5>("h00") @[lib.scala 368:33]
-    _T_755.valid <= UInt<1>("h00") @[lib.scala 368:33]
-    reg _T_756 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, rvclkhdr_9.io.l1clk with : (reset => (reset, _T_755)) @[lib.scala 368:16]
-    _T_756.bits.csrwaddr <= r_d_in.bits.csrwaddr @[lib.scala 368:16]
-    _T_756.bits.csrwonly <= r_d_in.bits.csrwonly @[lib.scala 368:16]
-    _T_756.bits.csrwen <= r_d_in.bits.csrwen @[lib.scala 368:16]
-    _T_756.bits.i0v <= r_d_in.bits.i0v @[lib.scala 368:16]
-    _T_756.bits.i0div <= r_d_in.bits.i0div @[lib.scala 368:16]
-    _T_756.bits.i0store <= r_d_in.bits.i0store @[lib.scala 368:16]
-    _T_756.bits.i0load <= r_d_in.bits.i0load @[lib.scala 368:16]
-    _T_756.bits.i0rd <= r_d_in.bits.i0rd @[lib.scala 368:16]
-    _T_756.valid <= r_d_in.valid @[lib.scala 368:16]
-    wbd.bits.csrwaddr <= _T_756.bits.csrwaddr @[dec_decode_ctl.scala 662:7]
-    wbd.bits.csrwonly <= _T_756.bits.csrwonly @[dec_decode_ctl.scala 662:7]
-    wbd.bits.csrwen <= _T_756.bits.csrwen @[dec_decode_ctl.scala 662:7]
-    wbd.bits.i0v <= _T_756.bits.i0v @[dec_decode_ctl.scala 662:7]
-    wbd.bits.i0div <= _T_756.bits.i0div @[dec_decode_ctl.scala 662:7]
-    wbd.bits.i0store <= _T_756.bits.i0store @[dec_decode_ctl.scala 662:7]
-    wbd.bits.i0load <= _T_756.bits.i0load @[dec_decode_ctl.scala 662:7]
-    wbd.bits.i0rd <= _T_756.bits.i0rd @[dec_decode_ctl.scala 662:7]
-    wbd.valid <= _T_756.valid @[dec_decode_ctl.scala 662:7]
+    wire _T_757 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[lib.scala 368:33]
+    _T_757.bits.csrwaddr <= UInt<12>("h00") @[lib.scala 368:33]
+    _T_757.bits.csrwonly <= UInt<1>("h00") @[lib.scala 368:33]
+    _T_757.bits.csrwen <= UInt<1>("h00") @[lib.scala 368:33]
+    _T_757.bits.i0v <= UInt<1>("h00") @[lib.scala 368:33]
+    _T_757.bits.i0div <= UInt<1>("h00") @[lib.scala 368:33]
+    _T_757.bits.i0store <= UInt<1>("h00") @[lib.scala 368:33]
+    _T_757.bits.i0load <= UInt<1>("h00") @[lib.scala 368:33]
+    _T_757.bits.i0rd <= UInt<5>("h00") @[lib.scala 368:33]
+    _T_757.valid <= UInt<1>("h00") @[lib.scala 368:33]
+    reg _T_758 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, rvclkhdr_9.io.l1clk with : (reset => (reset, _T_757)) @[lib.scala 368:16]
+    _T_758.bits.csrwaddr <= r_d_in.bits.csrwaddr @[lib.scala 368:16]
+    _T_758.bits.csrwonly <= r_d_in.bits.csrwonly @[lib.scala 368:16]
+    _T_758.bits.csrwen <= r_d_in.bits.csrwen @[lib.scala 368:16]
+    _T_758.bits.i0v <= r_d_in.bits.i0v @[lib.scala 368:16]
+    _T_758.bits.i0div <= r_d_in.bits.i0div @[lib.scala 368:16]
+    _T_758.bits.i0store <= r_d_in.bits.i0store @[lib.scala 368:16]
+    _T_758.bits.i0load <= r_d_in.bits.i0load @[lib.scala 368:16]
+    _T_758.bits.i0rd <= r_d_in.bits.i0rd @[lib.scala 368:16]
+    _T_758.valid <= r_d_in.valid @[lib.scala 368:16]
+    wbd.bits.csrwaddr <= _T_758.bits.csrwaddr @[dec_decode_ctl.scala 662:7]
+    wbd.bits.csrwonly <= _T_758.bits.csrwonly @[dec_decode_ctl.scala 662:7]
+    wbd.bits.csrwen <= _T_758.bits.csrwen @[dec_decode_ctl.scala 662:7]
+    wbd.bits.i0v <= _T_758.bits.i0v @[dec_decode_ctl.scala 662:7]
+    wbd.bits.i0div <= _T_758.bits.i0div @[dec_decode_ctl.scala 662:7]
+    wbd.bits.i0store <= _T_758.bits.i0store @[dec_decode_ctl.scala 662:7]
+    wbd.bits.i0load <= _T_758.bits.i0load @[dec_decode_ctl.scala 662:7]
+    wbd.bits.i0rd <= _T_758.bits.i0rd @[dec_decode_ctl.scala 662:7]
+    wbd.valid <= _T_758.valid @[dec_decode_ctl.scala 662:7]
     io.dec_i0_waddr_r <= r_d_in.bits.i0rd @[dec_decode_ctl.scala 664:27]
-    node _T_757 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[dec_decode_ctl.scala 665:47]
-    node _T_758 = and(r_d_in.bits.i0v, _T_757) @[dec_decode_ctl.scala 665:45]
-    i0_wen_r <= _T_758 @[dec_decode_ctl.scala 665:25]
-    node _T_759 = eq(r_d_in.bits.i0div, UInt<1>("h00")) @[dec_decode_ctl.scala 666:49]
-    node _T_760 = and(i0_wen_r, _T_759) @[dec_decode_ctl.scala 666:47]
-    node _T_761 = eq(i0_load_kill_wen_r, UInt<1>("h00")) @[dec_decode_ctl.scala 666:70]
-    node _T_762 = and(_T_760, _T_761) @[dec_decode_ctl.scala 666:68]
-    io.dec_i0_wen_r <= _T_762 @[dec_decode_ctl.scala 666:32]
+    node _T_759 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[dec_decode_ctl.scala 665:47]
+    node _T_760 = and(r_d_in.bits.i0v, _T_759) @[dec_decode_ctl.scala 665:45]
+    i0_wen_r <= _T_760 @[dec_decode_ctl.scala 665:25]
+    node _T_761 = eq(r_d_in.bits.i0div, UInt<1>("h00")) @[dec_decode_ctl.scala 666:49]
+    node _T_762 = and(i0_wen_r, _T_761) @[dec_decode_ctl.scala 666:47]
+    node _T_763 = eq(i0_load_kill_wen_r, UInt<1>("h00")) @[dec_decode_ctl.scala 666:70]
+    node _T_764 = and(_T_762, _T_763) @[dec_decode_ctl.scala 666:68]
+    io.dec_i0_wen_r <= _T_764 @[dec_decode_ctl.scala 666:32]
     io.dec_i0_wdata_r <= i0_result_corr_r @[dec_decode_ctl.scala 667:26]
-    node _T_763 = bits(i0_r_data_en, 0, 0) @[dec_decode_ctl.scala 669:57]
+    node _T_765 = bits(i0_r_data_en, 0, 0) @[dec_decode_ctl.scala 669:57]
     inst rvclkhdr_10 of rvclkhdr_671 @[lib.scala 352:23]
     rvclkhdr_10.clock <= clock
     rvclkhdr_10.reset <= reset
     rvclkhdr_10.io.clk <= clock @[lib.scala 354:18]
-    rvclkhdr_10.io.en <= _T_763 @[lib.scala 355:17]
+    rvclkhdr_10.io.en <= _T_765 @[lib.scala 355:17]
     rvclkhdr_10.io.scan_mode <= io.scan_mode @[lib.scala 356:24]
     reg i0_result_r_raw : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16]
     i0_result_r_raw <= i0_result_x @[lib.scala 358:16]
-    node _T_764 = and(x_d.bits.i0v, x_d.bits.i0load) @[dec_decode_ctl.scala 675:47]
-    node _T_765 = bits(_T_764, 0, 0) @[dec_decode_ctl.scala 675:66]
-    node _T_766 = mux(_T_765, io.lsu_result_m, io.decode_exu.exu_i0_result_x) @[dec_decode_ctl.scala 675:32]
-    i0_result_x <= _T_766 @[dec_decode_ctl.scala 675:26]
+    node _T_766 = and(x_d.bits.i0v, x_d.bits.i0load) @[dec_decode_ctl.scala 675:47]
+    node _T_767 = bits(_T_766, 0, 0) @[dec_decode_ctl.scala 675:66]
+    node _T_768 = mux(_T_767, io.lsu_result_m, io.decode_exu.exu_i0_result_x) @[dec_decode_ctl.scala 675:32]
+    i0_result_x <= _T_768 @[dec_decode_ctl.scala 675:26]
     i0_result_r <= i0_result_r_raw @[dec_decode_ctl.scala 676:26]
-    node _T_767 = and(r_d.bits.i0v, r_d.bits.i0load) @[dec_decode_ctl.scala 680:42]
-    node _T_768 = bits(_T_767, 0, 0) @[dec_decode_ctl.scala 680:61]
-    node _T_769 = mux(_T_768, io.lsu_result_corr_r, i0_result_r_raw) @[dec_decode_ctl.scala 680:27]
-    i0_result_corr_r <= _T_769 @[dec_decode_ctl.scala 680:21]
-    node _T_770 = eq(i0_dp.jal, UInt<1>("h00")) @[dec_decode_ctl.scala 681:73]
-    node _T_771 = and(io.decode_exu.i0_ap.predict_nt, _T_770) @[dec_decode_ctl.scala 681:71]
-    node _T_772 = bits(_T_771, 0, 0) @[dec_decode_ctl.scala 681:85]
-    wire _T_773 : UInt<1>[10] @[lib.scala 5:48]
-    _T_773[0] <= UInt<1>("h00") @[lib.scala 5:48]
-    _T_773[1] <= UInt<1>("h00") @[lib.scala 5:48]
-    _T_773[2] <= UInt<1>("h00") @[lib.scala 5:48]
-    _T_773[3] <= UInt<1>("h00") @[lib.scala 5:48]
-    _T_773[4] <= UInt<1>("h00") @[lib.scala 5:48]
-    _T_773[5] <= UInt<1>("h00") @[lib.scala 5:48]
-    _T_773[6] <= UInt<1>("h00") @[lib.scala 5:48]
-    _T_773[7] <= UInt<1>("h00") @[lib.scala 5:48]
-    _T_773[8] <= UInt<1>("h00") @[lib.scala 5:48]
-    _T_773[9] <= UInt<1>("h00") @[lib.scala 5:48]
-    node _T_774 = cat(_T_773[0], _T_773[1]) @[Cat.scala 29:58]
-    node _T_775 = cat(_T_774, _T_773[2]) @[Cat.scala 29:58]
-    node _T_776 = cat(_T_775, _T_773[3]) @[Cat.scala 29:58]
-    node _T_777 = cat(_T_776, _T_773[4]) @[Cat.scala 29:58]
-    node _T_778 = cat(_T_777, _T_773[5]) @[Cat.scala 29:58]
-    node _T_779 = cat(_T_778, _T_773[6]) @[Cat.scala 29:58]
-    node _T_780 = cat(_T_779, _T_773[7]) @[Cat.scala 29:58]
-    node _T_781 = cat(_T_780, _T_773[8]) @[Cat.scala 29:58]
-    node _T_782 = cat(_T_781, _T_773[9]) @[Cat.scala 29:58]
-    node _T_783 = cat(_T_782, io.dec_i0_pc4_d) @[Cat.scala 29:58]
-    node _T_784 = cat(_T_783, i0_ap_pc2) @[Cat.scala 29:58]
-    node _T_785 = mux(_T_772, i0_br_offset, _T_784) @[dec_decode_ctl.scala 681:38]
-    io.dec_alu.dec_i0_br_immed_d <= _T_785 @[dec_decode_ctl.scala 681:32]
+    node _T_769 = and(r_d.bits.i0v, r_d.bits.i0load) @[dec_decode_ctl.scala 680:42]
+    node _T_770 = bits(_T_769, 0, 0) @[dec_decode_ctl.scala 680:61]
+    node _T_771 = mux(_T_770, io.lsu_result_corr_r, i0_result_r_raw) @[dec_decode_ctl.scala 680:27]
+    i0_result_corr_r <= _T_771 @[dec_decode_ctl.scala 680:21]
+    node _T_772 = eq(i0_dp.jal, UInt<1>("h00")) @[dec_decode_ctl.scala 681:73]
+    node _T_773 = and(io.decode_exu.i0_ap.predict_nt, _T_772) @[dec_decode_ctl.scala 681:71]
+    node _T_774 = bits(_T_773, 0, 0) @[dec_decode_ctl.scala 681:85]
+    wire _T_775 : UInt<1>[10] @[lib.scala 5:48]
+    _T_775[0] <= UInt<1>("h00") @[lib.scala 5:48]
+    _T_775[1] <= UInt<1>("h00") @[lib.scala 5:48]
+    _T_775[2] <= UInt<1>("h00") @[lib.scala 5:48]
+    _T_775[3] <= UInt<1>("h00") @[lib.scala 5:48]
+    _T_775[4] <= UInt<1>("h00") @[lib.scala 5:48]
+    _T_775[5] <= UInt<1>("h00") @[lib.scala 5:48]
+    _T_775[6] <= UInt<1>("h00") @[lib.scala 5:48]
+    _T_775[7] <= UInt<1>("h00") @[lib.scala 5:48]
+    _T_775[8] <= UInt<1>("h00") @[lib.scala 5:48]
+    _T_775[9] <= UInt<1>("h00") @[lib.scala 5:48]
+    node _T_776 = cat(_T_775[0], _T_775[1]) @[Cat.scala 29:58]
+    node _T_777 = cat(_T_776, _T_775[2]) @[Cat.scala 29:58]
+    node _T_778 = cat(_T_777, _T_775[3]) @[Cat.scala 29:58]
+    node _T_779 = cat(_T_778, _T_775[4]) @[Cat.scala 29:58]
+    node _T_780 = cat(_T_779, _T_775[5]) @[Cat.scala 29:58]
+    node _T_781 = cat(_T_780, _T_775[6]) @[Cat.scala 29:58]
+    node _T_782 = cat(_T_781, _T_775[7]) @[Cat.scala 29:58]
+    node _T_783 = cat(_T_782, _T_775[8]) @[Cat.scala 29:58]
+    node _T_784 = cat(_T_783, _T_775[9]) @[Cat.scala 29:58]
+    node _T_785 = cat(_T_784, io.dec_i0_pc4_d) @[Cat.scala 29:58]
+    node _T_786 = cat(_T_785, i0_ap_pc2) @[Cat.scala 29:58]
+    node _T_787 = mux(_T_774, i0_br_offset, _T_786) @[dec_decode_ctl.scala 681:38]
+    io.dec_alu.dec_i0_br_immed_d <= _T_787 @[dec_decode_ctl.scala 681:32]
     wire last_br_immed_d : UInt<12>
     last_br_immed_d <= UInt<1>("h00")
-    node _T_786 = bits(io.decode_exu.i0_ap.predict_nt, 0, 0) @[dec_decode_ctl.scala 683:59]
-    wire _T_787 : UInt<1>[10] @[lib.scala 5:48]
-    _T_787[0] <= UInt<1>("h00") @[lib.scala 5:48]
-    _T_787[1] <= UInt<1>("h00") @[lib.scala 5:48]
-    _T_787[2] <= UInt<1>("h00") @[lib.scala 5:48]
-    _T_787[3] <= UInt<1>("h00") @[lib.scala 5:48]
-    _T_787[4] <= UInt<1>("h00") @[lib.scala 5:48]
-    _T_787[5] <= UInt<1>("h00") @[lib.scala 5:48]
-    _T_787[6] <= UInt<1>("h00") @[lib.scala 5:48]
-    _T_787[7] <= UInt<1>("h00") @[lib.scala 5:48]
-    _T_787[8] <= UInt<1>("h00") @[lib.scala 5:48]
-    _T_787[9] <= UInt<1>("h00") @[lib.scala 5:48]
-    node _T_788 = cat(_T_787[0], _T_787[1]) @[Cat.scala 29:58]
-    node _T_789 = cat(_T_788, _T_787[2]) @[Cat.scala 29:58]
-    node _T_790 = cat(_T_789, _T_787[3]) @[Cat.scala 29:58]
-    node _T_791 = cat(_T_790, _T_787[4]) @[Cat.scala 29:58]
-    node _T_792 = cat(_T_791, _T_787[5]) @[Cat.scala 29:58]
-    node _T_793 = cat(_T_792, _T_787[6]) @[Cat.scala 29:58]
-    node _T_794 = cat(_T_793, _T_787[7]) @[Cat.scala 29:58]
-    node _T_795 = cat(_T_794, _T_787[8]) @[Cat.scala 29:58]
-    node _T_796 = cat(_T_795, _T_787[9]) @[Cat.scala 29:58]
-    node _T_797 = cat(_T_796, io.dec_i0_pc4_d) @[Cat.scala 29:58]
-    node _T_798 = cat(_T_797, i0_ap_pc2) @[Cat.scala 29:58]
-    node _T_799 = mux(_T_786, _T_798, i0_br_offset) @[dec_decode_ctl.scala 683:25]
-    last_br_immed_d <= _T_799 @[dec_decode_ctl.scala 683:19]
+    node _T_788 = bits(io.decode_exu.i0_ap.predict_nt, 0, 0) @[dec_decode_ctl.scala 683:59]
+    wire _T_789 : UInt<1>[10] @[lib.scala 5:48]
+    _T_789[0] <= UInt<1>("h00") @[lib.scala 5:48]
+    _T_789[1] <= UInt<1>("h00") @[lib.scala 5:48]
+    _T_789[2] <= UInt<1>("h00") @[lib.scala 5:48]
+    _T_789[3] <= UInt<1>("h00") @[lib.scala 5:48]
+    _T_789[4] <= UInt<1>("h00") @[lib.scala 5:48]
+    _T_789[5] <= UInt<1>("h00") @[lib.scala 5:48]
+    _T_789[6] <= UInt<1>("h00") @[lib.scala 5:48]
+    _T_789[7] <= UInt<1>("h00") @[lib.scala 5:48]
+    _T_789[8] <= UInt<1>("h00") @[lib.scala 5:48]
+    _T_789[9] <= UInt<1>("h00") @[lib.scala 5:48]
+    node _T_790 = cat(_T_789[0], _T_789[1]) @[Cat.scala 29:58]
+    node _T_791 = cat(_T_790, _T_789[2]) @[Cat.scala 29:58]
+    node _T_792 = cat(_T_791, _T_789[3]) @[Cat.scala 29:58]
+    node _T_793 = cat(_T_792, _T_789[4]) @[Cat.scala 29:58]
+    node _T_794 = cat(_T_793, _T_789[5]) @[Cat.scala 29:58]
+    node _T_795 = cat(_T_794, _T_789[6]) @[Cat.scala 29:58]
+    node _T_796 = cat(_T_795, _T_789[7]) @[Cat.scala 29:58]
+    node _T_797 = cat(_T_796, _T_789[8]) @[Cat.scala 29:58]
+    node _T_798 = cat(_T_797, _T_789[9]) @[Cat.scala 29:58]
+    node _T_799 = cat(_T_798, io.dec_i0_pc4_d) @[Cat.scala 29:58]
+    node _T_800 = cat(_T_799, i0_ap_pc2) @[Cat.scala 29:58]
+    node _T_801 = mux(_T_788, _T_800, i0_br_offset) @[dec_decode_ctl.scala 683:25]
+    last_br_immed_d <= _T_801 @[dec_decode_ctl.scala 683:19]
     wire last_br_immed_x : UInt<12>
     last_br_immed_x <= UInt<1>("h00")
-    node _T_800 = bits(i0_x_data_en, 0, 0) @[dec_decode_ctl.scala 685:58]
+    node _T_802 = bits(i0_x_data_en, 0, 0) @[dec_decode_ctl.scala 685:58]
     inst rvclkhdr_11 of rvclkhdr_672 @[lib.scala 352:23]
     rvclkhdr_11.clock <= clock
     rvclkhdr_11.reset <= reset
     rvclkhdr_11.io.clk <= clock @[lib.scala 354:18]
-    rvclkhdr_11.io.en <= _T_800 @[lib.scala 355:17]
+    rvclkhdr_11.io.en <= _T_802 @[lib.scala 355:17]
     rvclkhdr_11.io.scan_mode <= io.scan_mode @[lib.scala 356:24]
-    reg _T_801 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16]
-    _T_801 <= last_br_immed_d @[lib.scala 358:16]
-    last_br_immed_x <= _T_801 @[dec_decode_ctl.scala 685:19]
-    node _T_802 = and(x_d.bits.i0div, x_d.valid) @[dec_decode_ctl.scala 689:45]
-    node _T_803 = and(r_d.bits.i0div, r_d.valid) @[dec_decode_ctl.scala 689:76]
-    node div_e1_to_r = or(_T_802, _T_803) @[dec_decode_ctl.scala 689:58]
-    node _T_804 = and(x_d.bits.i0div, x_d.valid) @[dec_decode_ctl.scala 691:48]
-    node _T_805 = eq(x_d.bits.i0rd, UInt<5>("h00")) @[dec_decode_ctl.scala 691:77]
-    node _T_806 = and(_T_804, _T_805) @[dec_decode_ctl.scala 691:60]
-    node _T_807 = and(x_d.bits.i0div, x_d.valid) @[dec_decode_ctl.scala 692:21]
-    node _T_808 = and(_T_807, io.dec_tlu_flush_lower_r) @[dec_decode_ctl.scala 692:33]
-    node _T_809 = or(_T_806, _T_808) @[dec_decode_ctl.scala 691:94]
-    node _T_810 = and(r_d.bits.i0div, r_d.valid) @[dec_decode_ctl.scala 693:21]
-    node _T_811 = and(_T_810, io.dec_tlu_flush_lower_r) @[dec_decode_ctl.scala 693:33]
-    node _T_812 = and(_T_811, io.dec_tlu_i0_kill_writeb_r) @[dec_decode_ctl.scala 693:60]
-    node div_flush = or(_T_809, _T_812) @[dec_decode_ctl.scala 692:62]
-    node _T_813 = and(io.dec_div_active, div_flush) @[dec_decode_ctl.scala 697:51]
-    node _T_814 = eq(div_e1_to_r, UInt<1>("h00")) @[dec_decode_ctl.scala 698:26]
-    node _T_815 = and(io.dec_div_active, _T_814) @[dec_decode_ctl.scala 698:24]
-    node _T_816 = eq(r_d.bits.i0rd, io.div_waddr_wb) @[dec_decode_ctl.scala 698:56]
-    node _T_817 = and(_T_815, _T_816) @[dec_decode_ctl.scala 698:39]
-    node _T_818 = and(_T_817, i0_wen_r) @[dec_decode_ctl.scala 698:77]
-    node nonblock_div_cancel = or(_T_813, _T_818) @[dec_decode_ctl.scala 697:65]
-    node _T_819 = bits(nonblock_div_cancel, 0, 0) @[dec_decode_ctl.scala 700:61]
-    io.dec_div.dec_div_cancel <= _T_819 @[dec_decode_ctl.scala 700:37]
+    reg _T_803 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16]
+    _T_803 <= last_br_immed_d @[lib.scala 358:16]
+    last_br_immed_x <= _T_803 @[dec_decode_ctl.scala 685:19]
+    node _T_804 = and(x_d.bits.i0div, x_d.valid) @[dec_decode_ctl.scala 689:45]
+    node _T_805 = and(r_d.bits.i0div, r_d.valid) @[dec_decode_ctl.scala 689:76]
+    node div_e1_to_r = or(_T_804, _T_805) @[dec_decode_ctl.scala 689:58]
+    node _T_806 = and(x_d.bits.i0div, x_d.valid) @[dec_decode_ctl.scala 691:48]
+    node _T_807 = eq(x_d.bits.i0rd, UInt<5>("h00")) @[dec_decode_ctl.scala 691:77]
+    node _T_808 = and(_T_806, _T_807) @[dec_decode_ctl.scala 691:60]
+    node _T_809 = and(x_d.bits.i0div, x_d.valid) @[dec_decode_ctl.scala 692:21]
+    node _T_810 = and(_T_809, io.dec_tlu_flush_lower_r) @[dec_decode_ctl.scala 692:33]
+    node _T_811 = or(_T_808, _T_810) @[dec_decode_ctl.scala 691:94]
+    node _T_812 = and(r_d.bits.i0div, r_d.valid) @[dec_decode_ctl.scala 693:21]
+    node _T_813 = and(_T_812, io.dec_tlu_flush_lower_r) @[dec_decode_ctl.scala 693:33]
+    node _T_814 = and(_T_813, io.dec_tlu_i0_kill_writeb_r) @[dec_decode_ctl.scala 693:60]
+    node div_flush = or(_T_811, _T_814) @[dec_decode_ctl.scala 692:62]
+    node _T_815 = and(io.dec_div_active, div_flush) @[dec_decode_ctl.scala 697:51]
+    node _T_816 = eq(div_e1_to_r, UInt<1>("h00")) @[dec_decode_ctl.scala 698:26]
+    node _T_817 = and(io.dec_div_active, _T_816) @[dec_decode_ctl.scala 698:24]
+    node _T_818 = eq(r_d.bits.i0rd, io.div_waddr_wb) @[dec_decode_ctl.scala 698:56]
+    node _T_819 = and(_T_817, _T_818) @[dec_decode_ctl.scala 698:39]
+    node _T_820 = and(_T_819, i0_wen_r) @[dec_decode_ctl.scala 698:77]
+    node nonblock_div_cancel = or(_T_815, _T_820) @[dec_decode_ctl.scala 697:65]
+    node _T_821 = bits(nonblock_div_cancel, 0, 0) @[dec_decode_ctl.scala 700:61]
+    io.dec_div.dec_div_cancel <= _T_821 @[dec_decode_ctl.scala 700:37]
     node i0_div_decode_d = and(i0_legal_decode_d, i0_dp.div) @[dec_decode_ctl.scala 701:55]
-    node _T_820 = eq(io.exu_div_wren, UInt<1>("h00")) @[dec_decode_ctl.scala 703:62]
-    node _T_821 = and(io.dec_div_active, _T_820) @[dec_decode_ctl.scala 703:60]
-    node _T_822 = eq(nonblock_div_cancel, UInt<1>("h00")) @[dec_decode_ctl.scala 703:81]
-    node _T_823 = and(_T_821, _T_822) @[dec_decode_ctl.scala 703:79]
-    node div_active_in = or(i0_div_decode_d, _T_823) @[dec_decode_ctl.scala 703:39]
-    reg _T_824 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 705:54]
-    _T_824 <= div_active_in @[dec_decode_ctl.scala 705:54]
-    io.dec_div_active <= _T_824 @[dec_decode_ctl.scala 705:21]
-    node _T_825 = and(io.decode_exu.dec_i0_rs1_en_d, io.dec_div_active) @[dec_decode_ctl.scala 708:60]
-    node _T_826 = eq(io.div_waddr_wb, i0r.rs1) @[dec_decode_ctl.scala 708:99]
-    node _T_827 = and(_T_825, _T_826) @[dec_decode_ctl.scala 708:80]
-    node _T_828 = and(io.decode_exu.dec_i0_rs2_en_d, io.dec_div_active) @[dec_decode_ctl.scala 709:36]
-    node _T_829 = eq(io.div_waddr_wb, i0r.rs2) @[dec_decode_ctl.scala 709:75]
-    node _T_830 = and(_T_828, _T_829) @[dec_decode_ctl.scala 709:56]
-    node _T_831 = or(_T_827, _T_830) @[dec_decode_ctl.scala 708:113]
-    i0_nonblock_div_stall <= _T_831 @[dec_decode_ctl.scala 708:26]
-    node _T_832 = bits(i0_div_decode_d, 0, 0) @[dec_decode_ctl.scala 711:59]
-    reg _T_833 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_832 : @[Reg.scala 28:19]
-      _T_833 <= i0r.rd @[Reg.scala 28:23]
+    node _T_822 = eq(io.exu_div_wren, UInt<1>("h00")) @[dec_decode_ctl.scala 703:62]
+    node _T_823 = and(io.dec_div_active, _T_822) @[dec_decode_ctl.scala 703:60]
+    node _T_824 = eq(nonblock_div_cancel, UInt<1>("h00")) @[dec_decode_ctl.scala 703:81]
+    node _T_825 = and(_T_823, _T_824) @[dec_decode_ctl.scala 703:79]
+    node div_active_in = or(i0_div_decode_d, _T_825) @[dec_decode_ctl.scala 703:39]
+    reg _T_826 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 705:54]
+    _T_826 <= div_active_in @[dec_decode_ctl.scala 705:54]
+    io.dec_div_active <= _T_826 @[dec_decode_ctl.scala 705:21]
+    node _T_827 = and(io.decode_exu.dec_i0_rs1_en_d, io.dec_div_active) @[dec_decode_ctl.scala 708:60]
+    node _T_828 = eq(io.div_waddr_wb, i0r.rs1) @[dec_decode_ctl.scala 708:99]
+    node _T_829 = and(_T_827, _T_828) @[dec_decode_ctl.scala 708:80]
+    node _T_830 = and(io.decode_exu.dec_i0_rs2_en_d, io.dec_div_active) @[dec_decode_ctl.scala 709:36]
+    node _T_831 = eq(io.div_waddr_wb, i0r.rs2) @[dec_decode_ctl.scala 709:75]
+    node _T_832 = and(_T_830, _T_831) @[dec_decode_ctl.scala 709:56]
+    node _T_833 = or(_T_829, _T_832) @[dec_decode_ctl.scala 708:113]
+    i0_nonblock_div_stall <= _T_833 @[dec_decode_ctl.scala 708:26]
+    node _T_834 = bits(i0_div_decode_d, 0, 0) @[dec_decode_ctl.scala 711:59]
+    reg _T_835 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_834 : @[Reg.scala 28:19]
+      _T_835 <= i0r.rd @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    io.div_waddr_wb <= _T_833 @[dec_decode_ctl.scala 711:19]
-    node _T_834 = bits(i0_inst_d, 24, 7) @[dec_decode_ctl.scala 718:34]
-    node _T_835 = bits(i0_div_decode_d, 0, 0) @[dec_decode_ctl.scala 718:57]
+    io.div_waddr_wb <= _T_835 @[dec_decode_ctl.scala 711:19]
+    node _T_836 = bits(i0_inst_d, 24, 7) @[dec_decode_ctl.scala 718:34]
+    node _T_837 = bits(i0_div_decode_d, 0, 0) @[dec_decode_ctl.scala 718:57]
     inst rvclkhdr_12 of rvclkhdr_673 @[lib.scala 352:23]
     rvclkhdr_12.clock <= clock
     rvclkhdr_12.reset <= reset
     rvclkhdr_12.io.clk <= clock @[lib.scala 354:18]
-    rvclkhdr_12.io.en <= _T_835 @[lib.scala 355:17]
+    rvclkhdr_12.io.en <= _T_837 @[lib.scala 355:17]
     rvclkhdr_12.io.scan_mode <= io.scan_mode @[lib.scala 356:24]
     reg div_inst : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16]
-    div_inst <= _T_834 @[lib.scala 358:16]
-    node _T_836 = bits(i0_x_data_en, 0, 0) @[dec_decode_ctl.scala 719:49]
+    div_inst <= _T_836 @[lib.scala 358:16]
+    node _T_838 = bits(i0_x_data_en, 0, 0) @[dec_decode_ctl.scala 719:49]
     inst rvclkhdr_13 of rvclkhdr_674 @[lib.scala 352:23]
     rvclkhdr_13.clock <= clock
     rvclkhdr_13.reset <= reset
     rvclkhdr_13.io.clk <= clock @[lib.scala 354:18]
-    rvclkhdr_13.io.en <= _T_836 @[lib.scala 355:17]
+    rvclkhdr_13.io.en <= _T_838 @[lib.scala 355:17]
     rvclkhdr_13.io.scan_mode <= io.scan_mode @[lib.scala 356:24]
     reg i0_inst_x : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16]
     i0_inst_x <= i0_inst_d @[lib.scala 358:16]
-    node _T_837 = bits(i0_r_data_en, 0, 0) @[dec_decode_ctl.scala 720:49]
+    node _T_839 = bits(i0_r_data_en, 0, 0) @[dec_decode_ctl.scala 720:49]
     inst rvclkhdr_14 of rvclkhdr_675 @[lib.scala 352:23]
     rvclkhdr_14.clock <= clock
     rvclkhdr_14.reset <= reset
     rvclkhdr_14.io.clk <= clock @[lib.scala 354:18]
-    rvclkhdr_14.io.en <= _T_837 @[lib.scala 355:17]
+    rvclkhdr_14.io.en <= _T_839 @[lib.scala 355:17]
     rvclkhdr_14.io.scan_mode <= io.scan_mode @[lib.scala 356:24]
     reg i0_inst_r : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16]
     i0_inst_r <= i0_inst_x @[lib.scala 358:16]
-    node _T_838 = bits(i0_wb_data_en, 0, 0) @[dec_decode_ctl.scala 722:50]
+    node _T_840 = bits(i0_wb_data_en, 0, 0) @[dec_decode_ctl.scala 722:50]
     inst rvclkhdr_15 of rvclkhdr_676 @[lib.scala 352:23]
     rvclkhdr_15.clock <= clock
     rvclkhdr_15.reset <= reset
     rvclkhdr_15.io.clk <= clock @[lib.scala 354:18]
-    rvclkhdr_15.io.en <= _T_838 @[lib.scala 355:17]
+    rvclkhdr_15.io.en <= _T_840 @[lib.scala 355:17]
     rvclkhdr_15.io.scan_mode <= io.scan_mode @[lib.scala 356:24]
     reg i0_inst_wb : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16]
     i0_inst_wb <= i0_inst_r @[lib.scala 358:16]
-    node _T_839 = bits(i0_wb1_data_en, 0, 0) @[dec_decode_ctl.scala 723:53]
+    node _T_841 = bits(i0_wb1_data_en, 0, 0) @[dec_decode_ctl.scala 723:53]
     inst rvclkhdr_16 of rvclkhdr_677 @[lib.scala 352:23]
     rvclkhdr_16.clock <= clock
     rvclkhdr_16.reset <= reset
     rvclkhdr_16.io.clk <= clock @[lib.scala 354:18]
-    rvclkhdr_16.io.en <= _T_839 @[lib.scala 355:17]
+    rvclkhdr_16.io.en <= _T_841 @[lib.scala 355:17]
     rvclkhdr_16.io.scan_mode <= io.scan_mode @[lib.scala 356:24]
-    reg _T_840 : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16]
-    _T_840 <= i0_inst_wb @[lib.scala 358:16]
-    io.dec_i0_inst_wb1 <= _T_840 @[dec_decode_ctl.scala 723:22]
-    node _T_841 = bits(i0_wb_data_en, 0, 0) @[dec_decode_ctl.scala 724:53]
+    reg _T_842 : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16]
+    _T_842 <= i0_inst_wb @[lib.scala 358:16]
+    io.dec_i0_inst_wb1 <= _T_842 @[dec_decode_ctl.scala 723:22]
+    node _T_843 = bits(i0_wb_data_en, 0, 0) @[dec_decode_ctl.scala 724:53]
     inst rvclkhdr_17 of rvclkhdr_678 @[lib.scala 352:23]
     rvclkhdr_17.clock <= clock
     rvclkhdr_17.reset <= reset
     rvclkhdr_17.io.clk <= clock @[lib.scala 354:18]
-    rvclkhdr_17.io.en <= _T_841 @[lib.scala 355:17]
+    rvclkhdr_17.io.en <= _T_843 @[lib.scala 355:17]
     rvclkhdr_17.io.scan_mode <= io.scan_mode @[lib.scala 356:24]
     reg i0_pc_wb : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16]
     i0_pc_wb <= io.dec_tlu_i0_pc_r @[lib.scala 358:16]
-    node _T_842 = bits(i0_wb1_data_en, 0, 0) @[dec_decode_ctl.scala 726:49]
+    node _T_844 = bits(i0_wb1_data_en, 0, 0) @[dec_decode_ctl.scala 726:49]
     inst rvclkhdr_18 of rvclkhdr_679 @[lib.scala 352:23]
     rvclkhdr_18.clock <= clock
     rvclkhdr_18.reset <= reset
     rvclkhdr_18.io.clk <= clock @[lib.scala 354:18]
-    rvclkhdr_18.io.en <= _T_842 @[lib.scala 355:17]
+    rvclkhdr_18.io.en <= _T_844 @[lib.scala 355:17]
     rvclkhdr_18.io.scan_mode <= io.scan_mode @[lib.scala 356:24]
-    reg _T_843 : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16]
-    _T_843 <= i0_pc_wb @[lib.scala 358:16]
-    io.dec_i0_pc_wb1 <= _T_843 @[dec_decode_ctl.scala 726:20]
-    node _T_844 = bits(i0_r_data_en, 0, 0) @[dec_decode_ctl.scala 727:64]
+    reg _T_845 : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16]
+    _T_845 <= i0_pc_wb @[lib.scala 358:16]
+    io.dec_i0_pc_wb1 <= _T_845 @[dec_decode_ctl.scala 726:20]
+    node _T_846 = bits(i0_r_data_en, 0, 0) @[dec_decode_ctl.scala 727:64]
     inst rvclkhdr_19 of rvclkhdr_680 @[lib.scala 352:23]
     rvclkhdr_19.clock <= clock
     rvclkhdr_19.reset <= reset
     rvclkhdr_19.io.clk <= clock @[lib.scala 354:18]
-    rvclkhdr_19.io.en <= _T_844 @[lib.scala 355:17]
+    rvclkhdr_19.io.en <= _T_846 @[lib.scala 355:17]
     rvclkhdr_19.io.scan_mode <= io.scan_mode @[lib.scala 356:24]
     reg dec_i0_pc_r : UInt, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16]
     dec_i0_pc_r <= io.dec_alu.exu_i0_pc_x @[lib.scala 358:16]
     io.dec_tlu_i0_pc_r <= dec_i0_pc_r @[dec_decode_ctl.scala 729:27]
-    node _T_845 = cat(io.dec_alu.exu_i0_pc_x, UInt<1>("h00")) @[Cat.scala 29:58]
-    node _T_846 = cat(last_br_immed_x, UInt<1>("h00")) @[Cat.scala 29:58]
-    node _T_847 = bits(_T_845, 12, 1) @[lib.scala 52:24]
-    node _T_848 = bits(_T_846, 12, 1) @[lib.scala 52:40]
-    node _T_849 = add(_T_847, _T_848) @[lib.scala 52:31]
-    node _T_850 = bits(_T_845, 31, 13) @[lib.scala 53:20]
-    node _T_851 = add(_T_850, UInt<1>("h01")) @[lib.scala 53:27]
-    node _T_852 = tail(_T_851, 1) @[lib.scala 53:27]
-    node _T_853 = bits(_T_845, 31, 13) @[lib.scala 54:20]
-    node _T_854 = sub(_T_853, UInt<1>("h01")) @[lib.scala 54:27]
-    node _T_855 = tail(_T_854, 1) @[lib.scala 54:27]
-    node _T_856 = bits(_T_846, 12, 12) @[lib.scala 55:22]
-    node _T_857 = bits(_T_849, 12, 12) @[lib.scala 56:39]
-    node _T_858 = eq(_T_857, UInt<1>("h00")) @[lib.scala 56:28]
-    node _T_859 = xor(_T_856, _T_858) @[lib.scala 56:26]
-    node _T_860 = bits(_T_859, 0, 0) @[lib.scala 56:64]
-    node _T_861 = bits(_T_845, 31, 13) @[lib.scala 56:76]
-    node _T_862 = eq(_T_856, UInt<1>("h00")) @[lib.scala 57:20]
-    node _T_863 = bits(_T_849, 12, 12) @[lib.scala 57:39]
-    node _T_864 = and(_T_862, _T_863) @[lib.scala 57:26]
-    node _T_865 = bits(_T_864, 0, 0) @[lib.scala 57:64]
-    node _T_866 = bits(_T_849, 12, 12) @[lib.scala 58:39]
-    node _T_867 = eq(_T_866, UInt<1>("h00")) @[lib.scala 58:28]
-    node _T_868 = and(_T_856, _T_867) @[lib.scala 58:26]
-    node _T_869 = bits(_T_868, 0, 0) @[lib.scala 58:64]
-    node _T_870 = mux(_T_860, _T_861, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_871 = mux(_T_865, _T_852, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_872 = mux(_T_869, _T_855, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_873 = or(_T_870, _T_871) @[Mux.scala 27:72]
-    node _T_874 = or(_T_873, _T_872) @[Mux.scala 27:72]
-    wire _T_875 : UInt<19> @[Mux.scala 27:72]
-    _T_875 <= _T_874 @[Mux.scala 27:72]
-    node _T_876 = bits(_T_849, 11, 0) @[lib.scala 58:94]
-    node _T_877 = cat(_T_875, _T_876) @[Cat.scala 29:58]
-    node temp_pred_correct_npc_x = cat(_T_877, UInt<1>("h00")) @[Cat.scala 29:58]
-    node _T_878 = bits(temp_pred_correct_npc_x, 31, 1) @[dec_decode_ctl.scala 734:62]
-    io.decode_exu.pred_correct_npc_x <= _T_878 @[dec_decode_ctl.scala 734:36]
-    node _T_879 = and(io.decode_exu.dec_i0_rs1_en_d, x_d.bits.i0v) @[dec_decode_ctl.scala 738:59]
-    node _T_880 = eq(x_d.bits.i0rd, i0r.rs1) @[dec_decode_ctl.scala 738:91]
-    node i0_rs1_depend_i0_x = and(_T_879, _T_880) @[dec_decode_ctl.scala 738:74]
-    node _T_881 = and(io.decode_exu.dec_i0_rs1_en_d, r_d.bits.i0v) @[dec_decode_ctl.scala 739:59]
-    node _T_882 = eq(r_d.bits.i0rd, i0r.rs1) @[dec_decode_ctl.scala 739:91]
-    node i0_rs1_depend_i0_r = and(_T_881, _T_882) @[dec_decode_ctl.scala 739:74]
-    node _T_883 = and(io.decode_exu.dec_i0_rs2_en_d, x_d.bits.i0v) @[dec_decode_ctl.scala 741:59]
-    node _T_884 = eq(x_d.bits.i0rd, i0r.rs2) @[dec_decode_ctl.scala 741:91]
-    node i0_rs2_depend_i0_x = and(_T_883, _T_884) @[dec_decode_ctl.scala 741:74]
-    node _T_885 = and(io.decode_exu.dec_i0_rs2_en_d, r_d.bits.i0v) @[dec_decode_ctl.scala 742:59]
-    node _T_886 = eq(r_d.bits.i0rd, i0r.rs2) @[dec_decode_ctl.scala 742:91]
-    node i0_rs2_depend_i0_r = and(_T_885, _T_886) @[dec_decode_ctl.scala 742:74]
-    node _T_887 = bits(i0_rs1_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 744:44]
-    node _T_888 = bits(i0_rs1_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 744:81]
-    wire _T_889 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 744:109]
-    _T_889.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 744:109]
-    _T_889.load <= UInt<1>("h00") @[dec_decode_ctl.scala 744:109]
-    _T_889.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 744:109]
-    node _T_890 = mux(_T_888, i0_r_c, _T_889) @[dec_decode_ctl.scala 744:61]
-    node _T_891 = mux(_T_887, i0_x_c, _T_890) @[dec_decode_ctl.scala 744:24]
-    i0_rs1_class_d.alu <= _T_891.alu @[dec_decode_ctl.scala 744:18]
-    i0_rs1_class_d.load <= _T_891.load @[dec_decode_ctl.scala 744:18]
-    i0_rs1_class_d.mul <= _T_891.mul @[dec_decode_ctl.scala 744:18]
-    node _T_892 = bits(i0_rs1_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 745:44]
-    node _T_893 = bits(i0_rs1_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 745:83]
-    node _T_894 = mux(_T_893, UInt<2>("h02"), UInt<1>("h00")) @[dec_decode_ctl.scala 745:63]
-    node _T_895 = mux(_T_892, UInt<2>("h01"), _T_894) @[dec_decode_ctl.scala 745:24]
-    i0_rs1_depth_d <= _T_895 @[dec_decode_ctl.scala 745:18]
-    node _T_896 = bits(i0_rs2_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 746:44]
-    node _T_897 = bits(i0_rs2_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 746:81]
-    wire _T_898 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 746:109]
-    _T_898.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 746:109]
-    _T_898.load <= UInt<1>("h00") @[dec_decode_ctl.scala 746:109]
-    _T_898.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 746:109]
-    node _T_899 = mux(_T_897, i0_r_c, _T_898) @[dec_decode_ctl.scala 746:61]
-    node _T_900 = mux(_T_896, i0_x_c, _T_899) @[dec_decode_ctl.scala 746:24]
-    i0_rs2_class_d.alu <= _T_900.alu @[dec_decode_ctl.scala 746:18]
-    i0_rs2_class_d.load <= _T_900.load @[dec_decode_ctl.scala 746:18]
-    i0_rs2_class_d.mul <= _T_900.mul @[dec_decode_ctl.scala 746:18]
-    node _T_901 = bits(i0_rs2_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 747:44]
-    node _T_902 = bits(i0_rs2_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 747:83]
-    node _T_903 = mux(_T_902, UInt<2>("h02"), UInt<1>("h00")) @[dec_decode_ctl.scala 747:63]
-    node _T_904 = mux(_T_901, UInt<2>("h01"), _T_903) @[dec_decode_ctl.scala 747:24]
-    i0_rs2_depth_d <= _T_904 @[dec_decode_ctl.scala 747:18]
+    node _T_847 = cat(io.dec_alu.exu_i0_pc_x, UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_848 = cat(last_br_immed_x, UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_849 = bits(_T_847, 12, 1) @[lib.scala 52:24]
+    node _T_850 = bits(_T_848, 12, 1) @[lib.scala 52:40]
+    node _T_851 = add(_T_849, _T_850) @[lib.scala 52:31]
+    node _T_852 = bits(_T_847, 31, 13) @[lib.scala 53:20]
+    node _T_853 = add(_T_852, UInt<1>("h01")) @[lib.scala 53:27]
+    node _T_854 = tail(_T_853, 1) @[lib.scala 53:27]
+    node _T_855 = bits(_T_847, 31, 13) @[lib.scala 54:20]
+    node _T_856 = sub(_T_855, UInt<1>("h01")) @[lib.scala 54:27]
+    node _T_857 = tail(_T_856, 1) @[lib.scala 54:27]
+    node _T_858 = bits(_T_848, 12, 12) @[lib.scala 55:22]
+    node _T_859 = bits(_T_851, 12, 12) @[lib.scala 56:39]
+    node _T_860 = eq(_T_859, UInt<1>("h00")) @[lib.scala 56:28]
+    node _T_861 = xor(_T_858, _T_860) @[lib.scala 56:26]
+    node _T_862 = bits(_T_861, 0, 0) @[lib.scala 56:64]
+    node _T_863 = bits(_T_847, 31, 13) @[lib.scala 56:76]
+    node _T_864 = eq(_T_858, UInt<1>("h00")) @[lib.scala 57:20]
+    node _T_865 = bits(_T_851, 12, 12) @[lib.scala 57:39]
+    node _T_866 = and(_T_864, _T_865) @[lib.scala 57:26]
+    node _T_867 = bits(_T_866, 0, 0) @[lib.scala 57:64]
+    node _T_868 = bits(_T_851, 12, 12) @[lib.scala 58:39]
+    node _T_869 = eq(_T_868, UInt<1>("h00")) @[lib.scala 58:28]
+    node _T_870 = and(_T_858, _T_869) @[lib.scala 58:26]
+    node _T_871 = bits(_T_870, 0, 0) @[lib.scala 58:64]
+    node _T_872 = mux(_T_862, _T_863, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_873 = mux(_T_867, _T_854, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_874 = mux(_T_871, _T_857, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_875 = or(_T_872, _T_873) @[Mux.scala 27:72]
+    node _T_876 = or(_T_875, _T_874) @[Mux.scala 27:72]
+    wire _T_877 : UInt<19> @[Mux.scala 27:72]
+    _T_877 <= _T_876 @[Mux.scala 27:72]
+    node _T_878 = bits(_T_851, 11, 0) @[lib.scala 58:94]
+    node _T_879 = cat(_T_877, _T_878) @[Cat.scala 29:58]
+    node temp_pred_correct_npc_x = cat(_T_879, UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_880 = bits(temp_pred_correct_npc_x, 31, 1) @[dec_decode_ctl.scala 734:62]
+    io.decode_exu.pred_correct_npc_x <= _T_880 @[dec_decode_ctl.scala 734:36]
+    node _T_881 = and(io.decode_exu.dec_i0_rs1_en_d, x_d.bits.i0v) @[dec_decode_ctl.scala 738:59]
+    node _T_882 = eq(x_d.bits.i0rd, i0r.rs1) @[dec_decode_ctl.scala 738:91]
+    node i0_rs1_depend_i0_x = and(_T_881, _T_882) @[dec_decode_ctl.scala 738:74]
+    node _T_883 = and(io.decode_exu.dec_i0_rs1_en_d, r_d.bits.i0v) @[dec_decode_ctl.scala 739:59]
+    node _T_884 = eq(r_d.bits.i0rd, i0r.rs1) @[dec_decode_ctl.scala 739:91]
+    node i0_rs1_depend_i0_r = and(_T_883, _T_884) @[dec_decode_ctl.scala 739:74]
+    node _T_885 = and(io.decode_exu.dec_i0_rs2_en_d, x_d.bits.i0v) @[dec_decode_ctl.scala 741:59]
+    node _T_886 = eq(x_d.bits.i0rd, i0r.rs2) @[dec_decode_ctl.scala 741:91]
+    node i0_rs2_depend_i0_x = and(_T_885, _T_886) @[dec_decode_ctl.scala 741:74]
+    node _T_887 = and(io.decode_exu.dec_i0_rs2_en_d, r_d.bits.i0v) @[dec_decode_ctl.scala 742:59]
+    node _T_888 = eq(r_d.bits.i0rd, i0r.rs2) @[dec_decode_ctl.scala 742:91]
+    node i0_rs2_depend_i0_r = and(_T_887, _T_888) @[dec_decode_ctl.scala 742:74]
+    node _T_889 = bits(i0_rs1_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 744:44]
+    node _T_890 = bits(i0_rs1_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 744:81]
+    wire _T_891 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 744:109]
+    _T_891.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 744:109]
+    _T_891.load <= UInt<1>("h00") @[dec_decode_ctl.scala 744:109]
+    _T_891.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 744:109]
+    node _T_892 = mux(_T_890, i0_r_c, _T_891) @[dec_decode_ctl.scala 744:61]
+    node _T_893 = mux(_T_889, i0_x_c, _T_892) @[dec_decode_ctl.scala 744:24]
+    i0_rs1_class_d.alu <= _T_893.alu @[dec_decode_ctl.scala 744:18]
+    i0_rs1_class_d.load <= _T_893.load @[dec_decode_ctl.scala 744:18]
+    i0_rs1_class_d.mul <= _T_893.mul @[dec_decode_ctl.scala 744:18]
+    node _T_894 = bits(i0_rs1_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 745:44]
+    node _T_895 = bits(i0_rs1_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 745:83]
+    node _T_896 = mux(_T_895, UInt<2>("h02"), UInt<1>("h00")) @[dec_decode_ctl.scala 745:63]
+    node _T_897 = mux(_T_894, UInt<2>("h01"), _T_896) @[dec_decode_ctl.scala 745:24]
+    i0_rs1_depth_d <= _T_897 @[dec_decode_ctl.scala 745:18]
+    node _T_898 = bits(i0_rs2_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 746:44]
+    node _T_899 = bits(i0_rs2_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 746:81]
+    wire _T_900 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 746:109]
+    _T_900.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 746:109]
+    _T_900.load <= UInt<1>("h00") @[dec_decode_ctl.scala 746:109]
+    _T_900.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 746:109]
+    node _T_901 = mux(_T_899, i0_r_c, _T_900) @[dec_decode_ctl.scala 746:61]
+    node _T_902 = mux(_T_898, i0_x_c, _T_901) @[dec_decode_ctl.scala 746:24]
+    i0_rs2_class_d.alu <= _T_902.alu @[dec_decode_ctl.scala 746:18]
+    i0_rs2_class_d.load <= _T_902.load @[dec_decode_ctl.scala 746:18]
+    i0_rs2_class_d.mul <= _T_902.mul @[dec_decode_ctl.scala 746:18]
+    node _T_903 = bits(i0_rs2_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 747:44]
+    node _T_904 = bits(i0_rs2_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 747:83]
+    node _T_905 = mux(_T_904, UInt<2>("h02"), UInt<1>("h00")) @[dec_decode_ctl.scala 747:63]
+    node _T_906 = mux(_T_903, UInt<2>("h01"), _T_905) @[dec_decode_ctl.scala 747:24]
+    i0_rs2_depth_d <= _T_906 @[dec_decode_ctl.scala 747:18]
     i0_load_block_d <= UInt<1>("h00") @[dec_decode_ctl.scala 757:21]
-    node _T_905 = or(i0_dp.load, i0_dp.store) @[dec_decode_ctl.scala 758:43]
-    node _T_906 = bits(i0_rs1_depth_d, 0, 0) @[dec_decode_ctl.scala 758:74]
-    node _T_907 = and(_T_905, _T_906) @[dec_decode_ctl.scala 758:58]
-    node _T_908 = and(_T_907, i0_rs1_class_d.load) @[dec_decode_ctl.scala 758:78]
-    load_ldst_bypass_d <= _T_908 @[dec_decode_ctl.scala 758:27]
-    node _T_909 = bits(i0_rs2_depth_d, 0, 0) @[dec_decode_ctl.scala 759:59]
-    node _T_910 = and(i0_dp.store, _T_909) @[dec_decode_ctl.scala 759:43]
-    node _T_911 = and(_T_910, i0_rs2_class_d.load) @[dec_decode_ctl.scala 759:63]
-    store_data_bypass_d <= _T_911 @[dec_decode_ctl.scala 759:25]
+    node _T_907 = or(i0_dp.load, i0_dp.store) @[dec_decode_ctl.scala 758:43]
+    node _T_908 = bits(i0_rs1_depth_d, 0, 0) @[dec_decode_ctl.scala 758:74]
+    node _T_909 = and(_T_907, _T_908) @[dec_decode_ctl.scala 758:58]
+    node _T_910 = and(_T_909, i0_rs1_class_d.load) @[dec_decode_ctl.scala 758:78]
+    load_ldst_bypass_d <= _T_910 @[dec_decode_ctl.scala 758:27]
+    node _T_911 = bits(i0_rs2_depth_d, 0, 0) @[dec_decode_ctl.scala 759:59]
+    node _T_912 = and(i0_dp.store, _T_911) @[dec_decode_ctl.scala 759:43]
+    node _T_913 = and(_T_912, i0_rs2_class_d.load) @[dec_decode_ctl.scala 759:63]
+    store_data_bypass_d <= _T_913 @[dec_decode_ctl.scala 759:25]
     store_data_bypass_m <= UInt<1>("h00") @[dec_decode_ctl.scala 760:25]
-    node _T_912 = and(io.decode_exu.dec_i0_rs1_en_d, io.dec_nonblock_load_wen) @[dec_decode_ctl.scala 764:73]
-    node _T_913 = eq(io.dec_nonblock_load_waddr, i0r.rs1) @[dec_decode_ctl.scala 764:130]
-    node i0_rs1_nonblock_load_bypass_en_d = and(_T_912, _T_913) @[dec_decode_ctl.scala 764:100]
-    node _T_914 = and(io.decode_exu.dec_i0_rs2_en_d, io.dec_nonblock_load_wen) @[dec_decode_ctl.scala 766:73]
-    node _T_915 = eq(io.dec_nonblock_load_waddr, i0r.rs2) @[dec_decode_ctl.scala 766:130]
-    node i0_rs2_nonblock_load_bypass_en_d = and(_T_914, _T_915) @[dec_decode_ctl.scala 766:100]
-    node _T_916 = bits(i0_rs1_depth_d, 0, 0) @[dec_decode_ctl.scala 769:41]
-    node _T_917 = or(i0_rs1_class_d.alu, i0_rs1_class_d.mul) @[dec_decode_ctl.scala 769:66]
-    node _T_918 = and(_T_916, _T_917) @[dec_decode_ctl.scala 769:45]
-    node _T_919 = bits(i0_rs1_depth_d, 0, 0) @[dec_decode_ctl.scala 769:104]
-    node _T_920 = and(_T_919, i0_rs1_class_d.load) @[dec_decode_ctl.scala 769:108]
-    node _T_921 = bits(i0_rs1_depth_d, 1, 1) @[dec_decode_ctl.scala 769:149]
-    node _T_922 = or(i0_rs1_class_d.alu, i0_rs1_class_d.mul) @[dec_decode_ctl.scala 769:175]
-    node _T_923 = or(_T_922, i0_rs1_class_d.load) @[dec_decode_ctl.scala 769:196]
-    node _T_924 = and(_T_921, _T_923) @[dec_decode_ctl.scala 769:153]
-    node _T_925 = cat(_T_918, _T_920) @[Cat.scala 29:58]
-    node _T_926 = cat(_T_925, _T_924) @[Cat.scala 29:58]
-    i0_rs1bypass <= _T_926 @[dec_decode_ctl.scala 769:18]
-    node _T_927 = bits(i0_rs2_depth_d, 0, 0) @[dec_decode_ctl.scala 771:41]
-    node _T_928 = or(i0_rs2_class_d.alu, i0_rs2_class_d.mul) @[dec_decode_ctl.scala 771:67]
-    node _T_929 = and(_T_927, _T_928) @[dec_decode_ctl.scala 771:45]
-    node _T_930 = bits(i0_rs2_depth_d, 0, 0) @[dec_decode_ctl.scala 771:105]
-    node _T_931 = and(_T_930, i0_rs2_class_d.load) @[dec_decode_ctl.scala 771:109]
-    node _T_932 = bits(i0_rs2_depth_d, 1, 1) @[dec_decode_ctl.scala 771:149]
-    node _T_933 = or(i0_rs2_class_d.alu, i0_rs2_class_d.mul) @[dec_decode_ctl.scala 771:175]
-    node _T_934 = or(_T_933, i0_rs2_class_d.load) @[dec_decode_ctl.scala 771:196]
-    node _T_935 = and(_T_932, _T_934) @[dec_decode_ctl.scala 771:153]
-    node _T_936 = cat(_T_929, _T_931) @[Cat.scala 29:58]
-    node _T_937 = cat(_T_936, _T_935) @[Cat.scala 29:58]
-    i0_rs2bypass <= _T_937 @[dec_decode_ctl.scala 771:18]
-    node _T_938 = bits(i0_rs1bypass, 2, 2) @[dec_decode_ctl.scala 773:65]
-    node _T_939 = bits(i0_rs1bypass, 1, 1) @[dec_decode_ctl.scala 773:82]
-    node _T_940 = bits(i0_rs1bypass, 0, 0) @[dec_decode_ctl.scala 773:100]
-    node _T_941 = or(_T_939, _T_940) @[dec_decode_ctl.scala 773:86]
-    node _T_942 = bits(i0_rs1bypass, 2, 2) @[dec_decode_ctl.scala 773:120]
-    node _T_943 = eq(_T_942, UInt<1>("h00")) @[dec_decode_ctl.scala 773:107]
-    node _T_944 = and(_T_943, i0_rs1_nonblock_load_bypass_en_d) @[dec_decode_ctl.scala 773:124]
-    node _T_945 = or(_T_941, _T_944) @[dec_decode_ctl.scala 773:104]
-    node _T_946 = cat(_T_938, _T_945) @[Cat.scala 29:58]
-    io.decode_exu.dec_i0_rs1_bypass_en_d <= _T_946 @[dec_decode_ctl.scala 773:45]
-    node _T_947 = bits(i0_rs2bypass, 2, 2) @[dec_decode_ctl.scala 774:65]
-    node _T_948 = bits(i0_rs2bypass, 1, 1) @[dec_decode_ctl.scala 774:82]
-    node _T_949 = bits(i0_rs2bypass, 0, 0) @[dec_decode_ctl.scala 774:100]
-    node _T_950 = or(_T_948, _T_949) @[dec_decode_ctl.scala 774:86]
-    node _T_951 = bits(i0_rs2bypass, 2, 2) @[dec_decode_ctl.scala 774:120]
-    node _T_952 = eq(_T_951, UInt<1>("h00")) @[dec_decode_ctl.scala 774:107]
-    node _T_953 = and(_T_952, i0_rs2_nonblock_load_bypass_en_d) @[dec_decode_ctl.scala 774:124]
-    node _T_954 = or(_T_950, _T_953) @[dec_decode_ctl.scala 774:104]
-    node _T_955 = cat(_T_947, _T_954) @[Cat.scala 29:58]
-    io.decode_exu.dec_i0_rs2_bypass_en_d <= _T_955 @[dec_decode_ctl.scala 774:45]
-    node _T_956 = bits(i0_rs1bypass, 1, 1) @[dec_decode_ctl.scala 778:17]
-    node _T_957 = bits(_T_956, 0, 0) @[dec_decode_ctl.scala 778:21]
-    node _T_958 = bits(i0_rs1bypass, 0, 0) @[dec_decode_ctl.scala 779:17]
-    node _T_959 = bits(_T_958, 0, 0) @[dec_decode_ctl.scala 779:21]
-    node _T_960 = bits(i0_rs1bypass, 1, 1) @[dec_decode_ctl.scala 780:19]
-    node _T_961 = eq(_T_960, UInt<1>("h00")) @[dec_decode_ctl.scala 780:6]
-    node _T_962 = bits(i0_rs1bypass, 0, 0) @[dec_decode_ctl.scala 780:38]
-    node _T_963 = eq(_T_962, UInt<1>("h00")) @[dec_decode_ctl.scala 780:25]
-    node _T_964 = and(_T_961, _T_963) @[dec_decode_ctl.scala 780:23]
-    node _T_965 = and(_T_964, i0_rs1_nonblock_load_bypass_en_d) @[dec_decode_ctl.scala 780:42]
-    node _T_966 = bits(_T_965, 0, 0) @[dec_decode_ctl.scala 780:78]
-    node _T_967 = mux(_T_957, io.lsu_result_m, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_968 = mux(_T_959, i0_result_r, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_969 = mux(_T_966, io.dctl_busbuff.lsu_nonblock_load_data, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_970 = or(_T_967, _T_968) @[Mux.scala 27:72]
-    node _T_971 = or(_T_970, _T_969) @[Mux.scala 27:72]
-    wire _T_972 : UInt<32> @[Mux.scala 27:72]
-    _T_972 <= _T_971 @[Mux.scala 27:72]
-    io.decode_exu.dec_i0_rs1_bypass_data_d <= _T_972 @[dec_decode_ctl.scala 777:42]
-    node _T_973 = bits(i0_rs2bypass, 1, 1) @[dec_decode_ctl.scala 783:17]
-    node _T_974 = bits(_T_973, 0, 0) @[dec_decode_ctl.scala 783:21]
-    node _T_975 = bits(i0_rs2bypass, 0, 0) @[dec_decode_ctl.scala 784:17]
-    node _T_976 = bits(_T_975, 0, 0) @[dec_decode_ctl.scala 784:21]
-    node _T_977 = bits(i0_rs2bypass, 1, 1) @[dec_decode_ctl.scala 785:19]
-    node _T_978 = eq(_T_977, UInt<1>("h00")) @[dec_decode_ctl.scala 785:6]
-    node _T_979 = bits(i0_rs2bypass, 0, 0) @[dec_decode_ctl.scala 785:38]
-    node _T_980 = eq(_T_979, UInt<1>("h00")) @[dec_decode_ctl.scala 785:25]
-    node _T_981 = and(_T_978, _T_980) @[dec_decode_ctl.scala 785:23]
-    node _T_982 = and(_T_981, i0_rs2_nonblock_load_bypass_en_d) @[dec_decode_ctl.scala 785:42]
-    node _T_983 = bits(_T_982, 0, 0) @[dec_decode_ctl.scala 785:78]
-    node _T_984 = mux(_T_974, io.lsu_result_m, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_985 = mux(_T_976, i0_result_r, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_986 = mux(_T_983, io.dctl_busbuff.lsu_nonblock_load_data, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_987 = or(_T_984, _T_985) @[Mux.scala 27:72]
-    node _T_988 = or(_T_987, _T_986) @[Mux.scala 27:72]
-    wire _T_989 : UInt<32> @[Mux.scala 27:72]
-    _T_989 <= _T_988 @[Mux.scala 27:72]
-    io.decode_exu.dec_i0_rs2_bypass_data_d <= _T_989 @[dec_decode_ctl.scala 782:42]
-    node _T_990 = or(i0_dp_raw.load, i0_dp_raw.store) @[dec_decode_ctl.scala 787:68]
-    node _T_991 = and(io.dec_ib0_valid_d, _T_990) @[dec_decode_ctl.scala 787:50]
-    node _T_992 = eq(io.dctl_dma.dma_dccm_stall_any, UInt<1>("h00")) @[dec_decode_ctl.scala 787:89]
-    node _T_993 = and(_T_991, _T_992) @[dec_decode_ctl.scala 787:87]
-    node _T_994 = eq(i0_block_raw_d, UInt<1>("h00")) @[dec_decode_ctl.scala 787:123]
-    node _T_995 = and(_T_993, _T_994) @[dec_decode_ctl.scala 787:121]
-    node _T_996 = or(_T_995, io.decode_exu.dec_extint_stall) @[dec_decode_ctl.scala 787:140]
-    io.dec_lsu_valid_raw_d <= _T_996 @[dec_decode_ctl.scala 787:26]
-    node _T_997 = eq(io.decode_exu.dec_extint_stall, UInt<1>("h00")) @[dec_decode_ctl.scala 789:6]
-    node _T_998 = and(_T_997, i0_dp.lsu) @[dec_decode_ctl.scala 789:38]
-    node _T_999 = and(_T_998, i0_dp.load) @[dec_decode_ctl.scala 789:50]
-    node _T_1000 = bits(_T_999, 0, 0) @[dec_decode_ctl.scala 789:64]
-    node _T_1001 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 789:81]
-    node _T_1002 = eq(io.decode_exu.dec_extint_stall, UInt<1>("h00")) @[dec_decode_ctl.scala 790:6]
-    node _T_1003 = and(_T_1002, i0_dp.lsu) @[dec_decode_ctl.scala 790:38]
-    node _T_1004 = and(_T_1003, i0_dp.store) @[dec_decode_ctl.scala 790:50]
-    node _T_1005 = bits(_T_1004, 0, 0) @[dec_decode_ctl.scala 790:65]
-    node _T_1006 = bits(io.dec_i0_instr_d, 31, 25) @[dec_decode_ctl.scala 790:85]
-    node _T_1007 = bits(io.dec_i0_instr_d, 11, 7) @[dec_decode_ctl.scala 790:95]
-    node _T_1008 = cat(_T_1006, _T_1007) @[Cat.scala 29:58]
-    node _T_1009 = mux(_T_1000, _T_1001, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1010 = mux(_T_1005, _T_1008, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1011 = or(_T_1009, _T_1010) @[Mux.scala 27:72]
-    wire _T_1012 : UInt<12> @[Mux.scala 27:72]
-    _T_1012 <= _T_1011 @[Mux.scala 27:72]
-    io.dec_lsu_offset_d <= _T_1012 @[dec_decode_ctl.scala 788:23]
+    node _T_914 = and(io.decode_exu.dec_i0_rs1_en_d, io.dec_nonblock_load_wen) @[dec_decode_ctl.scala 764:73]
+    node _T_915 = eq(io.dec_nonblock_load_waddr, i0r.rs1) @[dec_decode_ctl.scala 764:130]
+    node i0_rs1_nonblock_load_bypass_en_d = and(_T_914, _T_915) @[dec_decode_ctl.scala 764:100]
+    node _T_916 = and(io.decode_exu.dec_i0_rs2_en_d, io.dec_nonblock_load_wen) @[dec_decode_ctl.scala 766:73]
+    node _T_917 = eq(io.dec_nonblock_load_waddr, i0r.rs2) @[dec_decode_ctl.scala 766:130]
+    node i0_rs2_nonblock_load_bypass_en_d = and(_T_916, _T_917) @[dec_decode_ctl.scala 766:100]
+    node _T_918 = bits(i0_rs1_depth_d, 0, 0) @[dec_decode_ctl.scala 769:41]
+    node _T_919 = or(i0_rs1_class_d.alu, i0_rs1_class_d.mul) @[dec_decode_ctl.scala 769:66]
+    node _T_920 = and(_T_918, _T_919) @[dec_decode_ctl.scala 769:45]
+    node _T_921 = bits(i0_rs1_depth_d, 0, 0) @[dec_decode_ctl.scala 769:104]
+    node _T_922 = and(_T_921, i0_rs1_class_d.load) @[dec_decode_ctl.scala 769:108]
+    node _T_923 = bits(i0_rs1_depth_d, 1, 1) @[dec_decode_ctl.scala 769:149]
+    node _T_924 = or(i0_rs1_class_d.alu, i0_rs1_class_d.mul) @[dec_decode_ctl.scala 769:175]
+    node _T_925 = or(_T_924, i0_rs1_class_d.load) @[dec_decode_ctl.scala 769:196]
+    node _T_926 = and(_T_923, _T_925) @[dec_decode_ctl.scala 769:153]
+    node _T_927 = cat(_T_920, _T_922) @[Cat.scala 29:58]
+    node _T_928 = cat(_T_927, _T_926) @[Cat.scala 29:58]
+    i0_rs1bypass <= _T_928 @[dec_decode_ctl.scala 769:18]
+    node _T_929 = bits(i0_rs2_depth_d, 0, 0) @[dec_decode_ctl.scala 771:41]
+    node _T_930 = or(i0_rs2_class_d.alu, i0_rs2_class_d.mul) @[dec_decode_ctl.scala 771:67]
+    node _T_931 = and(_T_929, _T_930) @[dec_decode_ctl.scala 771:45]
+    node _T_932 = bits(i0_rs2_depth_d, 0, 0) @[dec_decode_ctl.scala 771:105]
+    node _T_933 = and(_T_932, i0_rs2_class_d.load) @[dec_decode_ctl.scala 771:109]
+    node _T_934 = bits(i0_rs2_depth_d, 1, 1) @[dec_decode_ctl.scala 771:149]
+    node _T_935 = or(i0_rs2_class_d.alu, i0_rs2_class_d.mul) @[dec_decode_ctl.scala 771:175]
+    node _T_936 = or(_T_935, i0_rs2_class_d.load) @[dec_decode_ctl.scala 771:196]
+    node _T_937 = and(_T_934, _T_936) @[dec_decode_ctl.scala 771:153]
+    node _T_938 = cat(_T_931, _T_933) @[Cat.scala 29:58]
+    node _T_939 = cat(_T_938, _T_937) @[Cat.scala 29:58]
+    i0_rs2bypass <= _T_939 @[dec_decode_ctl.scala 771:18]
+    node _T_940 = bits(i0_rs1bypass, 2, 2) @[dec_decode_ctl.scala 773:65]
+    node _T_941 = bits(i0_rs1bypass, 1, 1) @[dec_decode_ctl.scala 773:82]
+    node _T_942 = bits(i0_rs1bypass, 0, 0) @[dec_decode_ctl.scala 773:100]
+    node _T_943 = or(_T_941, _T_942) @[dec_decode_ctl.scala 773:86]
+    node _T_944 = bits(i0_rs1bypass, 2, 2) @[dec_decode_ctl.scala 773:120]
+    node _T_945 = eq(_T_944, UInt<1>("h00")) @[dec_decode_ctl.scala 773:107]
+    node _T_946 = and(_T_945, i0_rs1_nonblock_load_bypass_en_d) @[dec_decode_ctl.scala 773:124]
+    node _T_947 = or(_T_943, _T_946) @[dec_decode_ctl.scala 773:104]
+    node _T_948 = cat(_T_940, _T_947) @[Cat.scala 29:58]
+    io.decode_exu.dec_i0_rs1_bypass_en_d <= _T_948 @[dec_decode_ctl.scala 773:45]
+    node _T_949 = bits(i0_rs2bypass, 2, 2) @[dec_decode_ctl.scala 774:65]
+    node _T_950 = bits(i0_rs2bypass, 1, 1) @[dec_decode_ctl.scala 774:82]
+    node _T_951 = bits(i0_rs2bypass, 0, 0) @[dec_decode_ctl.scala 774:100]
+    node _T_952 = or(_T_950, _T_951) @[dec_decode_ctl.scala 774:86]
+    node _T_953 = bits(i0_rs2bypass, 2, 2) @[dec_decode_ctl.scala 774:120]
+    node _T_954 = eq(_T_953, UInt<1>("h00")) @[dec_decode_ctl.scala 774:107]
+    node _T_955 = and(_T_954, i0_rs2_nonblock_load_bypass_en_d) @[dec_decode_ctl.scala 774:124]
+    node _T_956 = or(_T_952, _T_955) @[dec_decode_ctl.scala 774:104]
+    node _T_957 = cat(_T_949, _T_956) @[Cat.scala 29:58]
+    io.decode_exu.dec_i0_rs2_bypass_en_d <= _T_957 @[dec_decode_ctl.scala 774:45]
+    node _T_958 = bits(i0_rs1bypass, 1, 1) @[dec_decode_ctl.scala 778:17]
+    node _T_959 = bits(_T_958, 0, 0) @[dec_decode_ctl.scala 778:21]
+    node _T_960 = bits(i0_rs1bypass, 0, 0) @[dec_decode_ctl.scala 779:17]
+    node _T_961 = bits(_T_960, 0, 0) @[dec_decode_ctl.scala 779:21]
+    node _T_962 = bits(i0_rs1bypass, 1, 1) @[dec_decode_ctl.scala 780:19]
+    node _T_963 = eq(_T_962, UInt<1>("h00")) @[dec_decode_ctl.scala 780:6]
+    node _T_964 = bits(i0_rs1bypass, 0, 0) @[dec_decode_ctl.scala 780:38]
+    node _T_965 = eq(_T_964, UInt<1>("h00")) @[dec_decode_ctl.scala 780:25]
+    node _T_966 = and(_T_963, _T_965) @[dec_decode_ctl.scala 780:23]
+    node _T_967 = and(_T_966, i0_rs1_nonblock_load_bypass_en_d) @[dec_decode_ctl.scala 780:42]
+    node _T_968 = bits(_T_967, 0, 0) @[dec_decode_ctl.scala 780:78]
+    node _T_969 = mux(_T_959, io.lsu_result_m, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_970 = mux(_T_961, i0_result_r, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_971 = mux(_T_968, io.dctl_busbuff.lsu_nonblock_load_data, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_972 = or(_T_969, _T_970) @[Mux.scala 27:72]
+    node _T_973 = or(_T_972, _T_971) @[Mux.scala 27:72]
+    wire _T_974 : UInt<32> @[Mux.scala 27:72]
+    _T_974 <= _T_973 @[Mux.scala 27:72]
+    io.decode_exu.dec_i0_rs1_bypass_data_d <= _T_974 @[dec_decode_ctl.scala 777:42]
+    node _T_975 = bits(i0_rs2bypass, 1, 1) @[dec_decode_ctl.scala 783:17]
+    node _T_976 = bits(_T_975, 0, 0) @[dec_decode_ctl.scala 783:21]
+    node _T_977 = bits(i0_rs2bypass, 0, 0) @[dec_decode_ctl.scala 784:17]
+    node _T_978 = bits(_T_977, 0, 0) @[dec_decode_ctl.scala 784:21]
+    node _T_979 = bits(i0_rs2bypass, 1, 1) @[dec_decode_ctl.scala 785:19]
+    node _T_980 = eq(_T_979, UInt<1>("h00")) @[dec_decode_ctl.scala 785:6]
+    node _T_981 = bits(i0_rs2bypass, 0, 0) @[dec_decode_ctl.scala 785:38]
+    node _T_982 = eq(_T_981, UInt<1>("h00")) @[dec_decode_ctl.scala 785:25]
+    node _T_983 = and(_T_980, _T_982) @[dec_decode_ctl.scala 785:23]
+    node _T_984 = and(_T_983, i0_rs2_nonblock_load_bypass_en_d) @[dec_decode_ctl.scala 785:42]
+    node _T_985 = bits(_T_984, 0, 0) @[dec_decode_ctl.scala 785:78]
+    node _T_986 = mux(_T_976, io.lsu_result_m, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_987 = mux(_T_978, i0_result_r, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_988 = mux(_T_985, io.dctl_busbuff.lsu_nonblock_load_data, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_989 = or(_T_986, _T_987) @[Mux.scala 27:72]
+    node _T_990 = or(_T_989, _T_988) @[Mux.scala 27:72]
+    wire _T_991 : UInt<32> @[Mux.scala 27:72]
+    _T_991 <= _T_990 @[Mux.scala 27:72]
+    io.decode_exu.dec_i0_rs2_bypass_data_d <= _T_991 @[dec_decode_ctl.scala 782:42]
+    node _T_992 = or(i0_dp_raw.load, i0_dp_raw.store) @[dec_decode_ctl.scala 787:68]
+    node _T_993 = and(io.dec_ib0_valid_d, _T_992) @[dec_decode_ctl.scala 787:50]
+    node _T_994 = eq(io.dctl_dma.dma_dccm_stall_any, UInt<1>("h00")) @[dec_decode_ctl.scala 787:89]
+    node _T_995 = and(_T_993, _T_994) @[dec_decode_ctl.scala 787:87]
+    node _T_996 = eq(i0_block_raw_d, UInt<1>("h00")) @[dec_decode_ctl.scala 787:123]
+    node _T_997 = and(_T_995, _T_996) @[dec_decode_ctl.scala 787:121]
+    node _T_998 = or(_T_997, io.decode_exu.dec_extint_stall) @[dec_decode_ctl.scala 787:140]
+    io.dec_lsu_valid_raw_d <= _T_998 @[dec_decode_ctl.scala 787:26]
+    node _T_999 = eq(io.decode_exu.dec_extint_stall, UInt<1>("h00")) @[dec_decode_ctl.scala 789:6]
+    node _T_1000 = and(_T_999, i0_dp.lsu) @[dec_decode_ctl.scala 789:38]
+    node _T_1001 = and(_T_1000, i0_dp.load) @[dec_decode_ctl.scala 789:50]
+    node _T_1002 = bits(_T_1001, 0, 0) @[dec_decode_ctl.scala 789:64]
+    node _T_1003 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 789:81]
+    node _T_1004 = eq(io.decode_exu.dec_extint_stall, UInt<1>("h00")) @[dec_decode_ctl.scala 790:6]
+    node _T_1005 = and(_T_1004, i0_dp.lsu) @[dec_decode_ctl.scala 790:38]
+    node _T_1006 = and(_T_1005, i0_dp.store) @[dec_decode_ctl.scala 790:50]
+    node _T_1007 = bits(_T_1006, 0, 0) @[dec_decode_ctl.scala 790:65]
+    node _T_1008 = bits(io.dec_i0_instr_d, 31, 25) @[dec_decode_ctl.scala 790:85]
+    node _T_1009 = bits(io.dec_i0_instr_d, 11, 7) @[dec_decode_ctl.scala 790:95]
+    node _T_1010 = cat(_T_1008, _T_1009) @[Cat.scala 29:58]
+    node _T_1011 = mux(_T_1002, _T_1003, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1012 = mux(_T_1007, _T_1010, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1013 = or(_T_1011, _T_1012) @[Mux.scala 27:72]
+    wire _T_1014 : UInt<12> @[Mux.scala 27:72]
+    _T_1014 <= _T_1013 @[Mux.scala 27:72]
+    io.dec_lsu_offset_d <= _T_1014 @[dec_decode_ctl.scala 788:23]
     
   extmodule gated_latch_681 : 
     output Q : Clock
diff --git a/quasar_wrapper.v b/quasar_wrapper.v
index 58f085d8..51e88d96 100644
--- a/quasar_wrapper.v
+++ b/quasar_wrapper.v
@@ -46630,10 +46630,10 @@ module dec_decode_ctl(
   reg  x_d_bits_i0load; // @[lib.scala 368:16]
   reg [4:0] x_d_bits_i0rd; // @[lib.scala 368:16]
   wire [4:0] nonblock_load_rd = x_d_bits_i0load ? x_d_bits_i0rd : 5'h0; // @[dec_decode_ctl.scala 284:31]
-  reg [2:0] _T_704; // @[dec_decode_ctl.scala 622:80]
-  wire [3:0] i0_pipe_en = {io_dec_aln_dec_i0_decode_d,_T_704}; // @[Cat.scala 29:58]
-  wire  _T_710 = |i0_pipe_en[2:1]; // @[dec_decode_ctl.scala 625:49]
-  wire  i0_r_ctl_en = _T_710 | io_clk_override; // @[dec_decode_ctl.scala 625:53]
+  reg [2:0] _T_706; // @[dec_decode_ctl.scala 622:80]
+  wire [3:0] i0_pipe_en = {io_dec_aln_dec_i0_decode_d,_T_706}; // @[Cat.scala 29:58]
+  wire  _T_712 = |i0_pipe_en[2:1]; // @[dec_decode_ctl.scala 625:49]
+  wire  i0_r_ctl_en = _T_712 | io_clk_override; // @[dec_decode_ctl.scala 625:53]
   reg  nonblock_load_valid_m_delay; // @[Reg.scala 27:20]
   reg  r_d_bits_i0load; // @[lib.scala 368:16]
   wire  i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d_bits_i0load; // @[dec_decode_ctl.scala 289:56]
@@ -46642,10 +46642,10 @@ module dec_decode_ctl(
   wire  _T_92 = io_dctl_busbuff_lsu_nonblock_load_inv_r & _T_91; // @[dec_decode_ctl.scala 291:45]
   wire  cam_inv_reset_val_0 = _T_92 & cam_0_valid; // @[dec_decode_ctl.scala 291:87]
   reg  r_d_bits_i0v; // @[lib.scala 368:16]
-  wire  _T_746 = ~io_dec_tlu_flush_lower_wb; // @[dec_decode_ctl.scala 657:51]
-  wire  r_d_in_bits_i0v = r_d_bits_i0v & _T_746; // @[dec_decode_ctl.scala 657:49]
-  wire  _T_757 = ~io_dec_tlu_i0_kill_writeb_r; // @[dec_decode_ctl.scala 665:47]
-  wire  i0_wen_r = r_d_in_bits_i0v & _T_757; // @[dec_decode_ctl.scala 665:45]
+  wire  _T_748 = ~io_dec_tlu_flush_lower_wb; // @[dec_decode_ctl.scala 657:51]
+  wire  r_d_in_bits_i0v = r_d_bits_i0v & _T_748; // @[dec_decode_ctl.scala 657:49]
+  wire  _T_759 = ~io_dec_tlu_i0_kill_writeb_r; // @[dec_decode_ctl.scala 665:47]
+  wire  i0_wen_r = r_d_in_bits_i0v & _T_759; // @[dec_decode_ctl.scala 665:45]
   reg [4:0] r_d_bits_i0rd; // @[lib.scala 368:16]
   reg [4:0] cam_raw_0_bits_rd; // @[dec_decode_ctl.scala 317:47]
   wire  _T_103 = r_d_bits_i0rd == cam_raw_0_bits_rd; // @[dec_decode_ctl.scala 304:85]
@@ -46795,34 +46795,34 @@ module dec_decode_ctl(
   wire  _T_337 = ~i0_pret_case; // @[dec_decode_ctl.scala 390:67]
   reg  _T_339; // @[dec_decode_ctl.scala 402:69]
   wire  lsu_decode_d = i0_legal_decode_d & i0_dp_lsu; // @[dec_decode_ctl.scala 544:40]
-  wire  _T_905 = i0_dp_load | i0_dp_store; // @[dec_decode_ctl.scala 758:43]
+  wire  _T_907 = i0_dp_load | i0_dp_store; // @[dec_decode_ctl.scala 758:43]
   reg  x_d_bits_i0v; // @[lib.scala 368:16]
-  wire  _T_879 = io_decode_exu_dec_i0_rs1_en_d & x_d_bits_i0v; // @[dec_decode_ctl.scala 738:59]
-  wire  _T_880 = x_d_bits_i0rd == i0r_rs1; // @[dec_decode_ctl.scala 738:91]
-  wire  i0_rs1_depend_i0_x = _T_879 & _T_880; // @[dec_decode_ctl.scala 738:74]
-  wire  _T_881 = io_decode_exu_dec_i0_rs1_en_d & r_d_bits_i0v; // @[dec_decode_ctl.scala 739:59]
-  wire  _T_882 = r_d_bits_i0rd == i0r_rs1; // @[dec_decode_ctl.scala 739:91]
-  wire  i0_rs1_depend_i0_r = _T_881 & _T_882; // @[dec_decode_ctl.scala 739:74]
-  wire [1:0] _T_894 = i0_rs1_depend_i0_r ? 2'h2 : 2'h0; // @[dec_decode_ctl.scala 745:63]
-  wire [1:0] i0_rs1_depth_d = i0_rs1_depend_i0_x ? 2'h1 : _T_894; // @[dec_decode_ctl.scala 745:24]
-  wire  _T_907 = _T_905 & i0_rs1_depth_d[0]; // @[dec_decode_ctl.scala 758:58]
-  reg  i0_x_c_load; // @[Reg.scala 15:16]
-  reg  i0_r_c_load; // @[Reg.scala 15:16]
-  wire  _T_890_load = i0_rs1_depend_i0_r & i0_r_c_load; // @[dec_decode_ctl.scala 744:61]
-  wire  i0_rs1_class_d_load = i0_rs1_depend_i0_x ? i0_x_c_load : _T_890_load; // @[dec_decode_ctl.scala 744:24]
-  wire  load_ldst_bypass_d = _T_907 & i0_rs1_class_d_load; // @[dec_decode_ctl.scala 758:78]
-  wire  _T_883 = io_decode_exu_dec_i0_rs2_en_d & x_d_bits_i0v; // @[dec_decode_ctl.scala 741:59]
-  wire  _T_884 = x_d_bits_i0rd == i0r_rs2; // @[dec_decode_ctl.scala 741:91]
-  wire  i0_rs2_depend_i0_x = _T_883 & _T_884; // @[dec_decode_ctl.scala 741:74]
-  wire  _T_885 = io_decode_exu_dec_i0_rs2_en_d & r_d_bits_i0v; // @[dec_decode_ctl.scala 742:59]
-  wire  _T_886 = r_d_bits_i0rd == i0r_rs2; // @[dec_decode_ctl.scala 742:91]
-  wire  i0_rs2_depend_i0_r = _T_885 & _T_886; // @[dec_decode_ctl.scala 742:74]
-  wire [1:0] _T_903 = i0_rs2_depend_i0_r ? 2'h2 : 2'h0; // @[dec_decode_ctl.scala 747:63]
-  wire [1:0] i0_rs2_depth_d = i0_rs2_depend_i0_x ? 2'h1 : _T_903; // @[dec_decode_ctl.scala 747:24]
-  wire  _T_910 = i0_dp_store & i0_rs2_depth_d[0]; // @[dec_decode_ctl.scala 759:43]
-  wire  _T_899_load = i0_rs2_depend_i0_r & i0_r_c_load; // @[dec_decode_ctl.scala 746:61]
-  wire  i0_rs2_class_d_load = i0_rs2_depend_i0_x ? i0_x_c_load : _T_899_load; // @[dec_decode_ctl.scala 746:24]
-  wire  store_data_bypass_d = _T_910 & i0_rs2_class_d_load; // @[dec_decode_ctl.scala 759:63]
+  wire  _T_881 = io_decode_exu_dec_i0_rs1_en_d & x_d_bits_i0v; // @[dec_decode_ctl.scala 738:59]
+  wire  _T_882 = x_d_bits_i0rd == i0r_rs1; // @[dec_decode_ctl.scala 738:91]
+  wire  i0_rs1_depend_i0_x = _T_881 & _T_882; // @[dec_decode_ctl.scala 738:74]
+  wire  _T_883 = io_decode_exu_dec_i0_rs1_en_d & r_d_bits_i0v; // @[dec_decode_ctl.scala 739:59]
+  wire  _T_884 = r_d_bits_i0rd == i0r_rs1; // @[dec_decode_ctl.scala 739:91]
+  wire  i0_rs1_depend_i0_r = _T_883 & _T_884; // @[dec_decode_ctl.scala 739:74]
+  wire [1:0] _T_896 = i0_rs1_depend_i0_r ? 2'h2 : 2'h0; // @[dec_decode_ctl.scala 745:63]
+  wire [1:0] i0_rs1_depth_d = i0_rs1_depend_i0_x ? 2'h1 : _T_896; // @[dec_decode_ctl.scala 745:24]
+  wire  _T_909 = _T_907 & i0_rs1_depth_d[0]; // @[dec_decode_ctl.scala 758:58]
+  reg  i0_x_c_load; // @[Reg.scala 27:20]
+  reg  i0_r_c_load; // @[Reg.scala 27:20]
+  wire  _T_892_load = i0_rs1_depend_i0_r & i0_r_c_load; // @[dec_decode_ctl.scala 744:61]
+  wire  i0_rs1_class_d_load = i0_rs1_depend_i0_x ? i0_x_c_load : _T_892_load; // @[dec_decode_ctl.scala 744:24]
+  wire  load_ldst_bypass_d = _T_909 & i0_rs1_class_d_load; // @[dec_decode_ctl.scala 758:78]
+  wire  _T_885 = io_decode_exu_dec_i0_rs2_en_d & x_d_bits_i0v; // @[dec_decode_ctl.scala 741:59]
+  wire  _T_886 = x_d_bits_i0rd == i0r_rs2; // @[dec_decode_ctl.scala 741:91]
+  wire  i0_rs2_depend_i0_x = _T_885 & _T_886; // @[dec_decode_ctl.scala 741:74]
+  wire  _T_887 = io_decode_exu_dec_i0_rs2_en_d & r_d_bits_i0v; // @[dec_decode_ctl.scala 742:59]
+  wire  _T_888 = r_d_bits_i0rd == i0r_rs2; // @[dec_decode_ctl.scala 742:91]
+  wire  i0_rs2_depend_i0_r = _T_887 & _T_888; // @[dec_decode_ctl.scala 742:74]
+  wire [1:0] _T_905 = i0_rs2_depend_i0_r ? 2'h2 : 2'h0; // @[dec_decode_ctl.scala 747:63]
+  wire [1:0] i0_rs2_depth_d = i0_rs2_depend_i0_x ? 2'h1 : _T_905; // @[dec_decode_ctl.scala 747:24]
+  wire  _T_912 = i0_dp_store & i0_rs2_depth_d[0]; // @[dec_decode_ctl.scala 759:43]
+  wire  _T_901_load = i0_rs2_depend_i0_r & i0_r_c_load; // @[dec_decode_ctl.scala 746:61]
+  wire  i0_rs2_class_d_load = i0_rs2_depend_i0_x ? i0_x_c_load : _T_901_load; // @[dec_decode_ctl.scala 746:24]
+  wire  store_data_bypass_d = _T_912 & i0_rs2_class_d_load; // @[dec_decode_ctl.scala 759:63]
   wire  _T_349 = i0_dp_csr_clr | i0_dp_csr_set; // @[dec_decode_ctl.scala 433:42]
   reg  r_d_bits_csrwen; // @[lib.scala 368:16]
   reg  r_d_valid; // @[lib.scala 368:16]
@@ -46864,9 +46864,9 @@ module dec_decode_ctl(
   wire  _T_430 = _T_429 & csr_read_x; // @[dec_decode_ctl.scala 477:61]
   wire  _T_431 = _T_430 | io_dec_tlu_wr_pause_r; // @[dec_decode_ctl.scala 477:75]
   reg  r_d_bits_csrwonly; // @[lib.scala 368:16]
-  wire  _T_767 = r_d_bits_i0v & r_d_bits_i0load; // @[dec_decode_ctl.scala 680:42]
+  wire  _T_769 = r_d_bits_i0v & r_d_bits_i0load; // @[dec_decode_ctl.scala 680:42]
   reg [31:0] i0_result_r_raw; // @[lib.scala 358:16]
-  wire [31:0] i0_result_corr_r = _T_767 ? io_lsu_result_corr_r : i0_result_r_raw; // @[dec_decode_ctl.scala 680:27]
+  wire [31:0] i0_result_corr_r = _T_769 ? io_lsu_result_corr_r : i0_result_r_raw; // @[dec_decode_ctl.scala 680:27]
   reg  x_d_bits_csrwonly; // @[lib.scala 368:16]
   wire  _T_435 = x_d_bits_csrwonly | r_d_bits_csrwonly; // @[dec_decode_ctl.scala 486:43]
   reg  wbd_bits_csrwonly; // @[lib.scala 368:16]
@@ -46896,13 +46896,13 @@ module dec_decode_ctl(
   wire  _T_482 = _T_480 & _T_481; // @[dec_decode_ctl.scala 513:34]
   wire  _T_483 = _T_479 | _T_482; // @[dec_decode_ctl.scala 512:79]
   wire  _T_484 = _T_483 | i0_nonblock_load_stall; // @[dec_decode_ctl.scala 513:47]
-  wire  _T_825 = io_decode_exu_dec_i0_rs1_en_d & io_dec_div_active; // @[dec_decode_ctl.scala 708:60]
-  wire  _T_826 = io_div_waddr_wb == i0r_rs1; // @[dec_decode_ctl.scala 708:99]
-  wire  _T_827 = _T_825 & _T_826; // @[dec_decode_ctl.scala 708:80]
-  wire  _T_828 = io_decode_exu_dec_i0_rs2_en_d & io_dec_div_active; // @[dec_decode_ctl.scala 709:36]
-  wire  _T_829 = io_div_waddr_wb == i0r_rs2; // @[dec_decode_ctl.scala 709:75]
-  wire  _T_830 = _T_828 & _T_829; // @[dec_decode_ctl.scala 709:56]
-  wire  i0_nonblock_div_stall = _T_827 | _T_830; // @[dec_decode_ctl.scala 708:113]
+  wire  _T_827 = io_decode_exu_dec_i0_rs1_en_d & io_dec_div_active; // @[dec_decode_ctl.scala 708:60]
+  wire  _T_828 = io_div_waddr_wb == i0r_rs1; // @[dec_decode_ctl.scala 708:99]
+  wire  _T_829 = _T_827 & _T_828; // @[dec_decode_ctl.scala 708:80]
+  wire  _T_830 = io_decode_exu_dec_i0_rs2_en_d & io_dec_div_active; // @[dec_decode_ctl.scala 709:36]
+  wire  _T_831 = io_div_waddr_wb == i0r_rs2; // @[dec_decode_ctl.scala 709:75]
+  wire  _T_832 = _T_830 & _T_831; // @[dec_decode_ctl.scala 709:56]
+  wire  i0_nonblock_div_stall = _T_829 | _T_832; // @[dec_decode_ctl.scala 708:113]
   wire  _T_486 = _T_484 | i0_nonblock_div_stall; // @[dec_decode_ctl.scala 514:21]
   wire  i0_block_raw_d = _T_486 | i0_div_prior_div_stall; // @[dec_decode_ctl.scala 514:45]
   wire  _T_487 = io_lsu_store_stall_any | io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 516:65]
@@ -46922,8 +46922,8 @@ module dec_decode_ctl(
   wire  _T_501 = ~io_dec_aln_dec_i0_decode_d; // @[dec_decode_ctl.scala 528:51]
   wire  _T_520 = i0_dp_fence_i | debug_fence_i; // @[dec_decode_ctl.scala 556:44]
   wire [3:0] _T_525 = {io_dec_aln_dec_i0_decode_d,io_dec_aln_dec_i0_decode_d,io_dec_aln_dec_i0_decode_d,io_dec_aln_dec_i0_decode_d}; // @[Cat.scala 29:58]
-  wire  _T_707 = |i0_pipe_en[3:2]; // @[dec_decode_ctl.scala 624:49]
-  wire  i0_x_ctl_en = _T_707 | io_clk_override; // @[dec_decode_ctl.scala 624:53]
+  wire  _T_709 = |i0_pipe_en[3:2]; // @[dec_decode_ctl.scala 624:49]
+  wire  i0_x_ctl_en = _T_709 | io_clk_override; // @[dec_decode_ctl.scala 624:53]
   reg  x_t_legal; // @[lib.scala 368:16]
   reg  x_t_icaf; // @[lib.scala 368:16]
   reg  x_t_icaf_f1; // @[lib.scala 368:16]
@@ -46980,133 +46980,133 @@ module dec_decode_ctl(
   wire  i0_d_c_mul = i0_dp_mul & i0_legal_decode_d; // @[dec_decode_ctl.scala 616:44]
   wire  i0_d_c_load = i0_dp_load & i0_legal_decode_d; // @[dec_decode_ctl.scala 617:44]
   wire  i0_d_c_alu = i0_dp_alu & i0_legal_decode_d; // @[dec_decode_ctl.scala 618:44]
-  reg  i0_x_c_mul; // @[Reg.scala 15:16]
-  reg  i0_x_c_alu; // @[Reg.scala 15:16]
-  reg  i0_r_c_mul; // @[Reg.scala 15:16]
-  reg  i0_r_c_alu; // @[Reg.scala 15:16]
-  wire  _T_713 = |i0_pipe_en[1:0]; // @[dec_decode_ctl.scala 626:49]
+  reg  i0_x_c_mul; // @[Reg.scala 27:20]
+  reg  i0_x_c_alu; // @[Reg.scala 27:20]
+  reg  i0_r_c_mul; // @[Reg.scala 27:20]
+  reg  i0_r_c_alu; // @[Reg.scala 27:20]
+  wire  _T_715 = |i0_pipe_en[1:0]; // @[dec_decode_ctl.scala 626:49]
   wire  i0_r_data_en = i0_pipe_en[2] | io_clk_override; // @[dec_decode_ctl.scala 628:50]
   reg  x_d_bits_i0store; // @[lib.scala 368:16]
   reg  x_d_bits_i0div; // @[lib.scala 368:16]
   reg  x_d_bits_csrwen; // @[lib.scala 368:16]
   reg [11:0] x_d_bits_csrwaddr; // @[lib.scala 368:16]
-  wire  _T_736 = x_d_bits_i0v & _T_746; // @[dec_decode_ctl.scala 650:47]
-  wire  _T_740 = x_d_valid & _T_746; // @[dec_decode_ctl.scala 651:33]
-  wire  _T_759 = ~r_d_bits_i0div; // @[dec_decode_ctl.scala 666:49]
-  wire  _T_760 = i0_wen_r & _T_759; // @[dec_decode_ctl.scala 666:47]
-  wire  _T_761 = ~i0_load_kill_wen_r; // @[dec_decode_ctl.scala 666:70]
-  wire  _T_764 = x_d_bits_i0v & x_d_bits_i0load; // @[dec_decode_ctl.scala 675:47]
-  wire  _T_771 = io_decode_exu_i0_ap_predict_nt & _T_564; // @[dec_decode_ctl.scala 681:71]
-  wire [11:0] _T_784 = {10'h0,io_dec_i0_pc4_d,i0_ap_pc2}; // @[Cat.scala 29:58]
+  wire  _T_738 = x_d_bits_i0v & _T_748; // @[dec_decode_ctl.scala 650:47]
+  wire  _T_742 = x_d_valid & _T_748; // @[dec_decode_ctl.scala 651:33]
+  wire  _T_761 = ~r_d_bits_i0div; // @[dec_decode_ctl.scala 666:49]
+  wire  _T_762 = i0_wen_r & _T_761; // @[dec_decode_ctl.scala 666:47]
+  wire  _T_763 = ~i0_load_kill_wen_r; // @[dec_decode_ctl.scala 666:70]
+  wire  _T_766 = x_d_bits_i0v & x_d_bits_i0load; // @[dec_decode_ctl.scala 675:47]
+  wire  _T_773 = io_decode_exu_i0_ap_predict_nt & _T_564; // @[dec_decode_ctl.scala 681:71]
+  wire [11:0] _T_786 = {10'h0,io_dec_i0_pc4_d,i0_ap_pc2}; // @[Cat.scala 29:58]
   reg [11:0] last_br_immed_x; // @[lib.scala 358:16]
-  wire  _T_802 = x_d_bits_i0div & x_d_valid; // @[dec_decode_ctl.scala 689:45]
-  wire  div_e1_to_r = _T_802 | _T_548; // @[dec_decode_ctl.scala 689:58]
-  wire  _T_805 = x_d_bits_i0rd == 5'h0; // @[dec_decode_ctl.scala 691:77]
-  wire  _T_806 = _T_802 & _T_805; // @[dec_decode_ctl.scala 691:60]
-  wire  _T_808 = _T_802 & io_dec_tlu_flush_lower_r; // @[dec_decode_ctl.scala 692:33]
-  wire  _T_809 = _T_806 | _T_808; // @[dec_decode_ctl.scala 691:94]
-  wire  _T_811 = _T_548 & io_dec_tlu_flush_lower_r; // @[dec_decode_ctl.scala 693:33]
-  wire  _T_812 = _T_811 & io_dec_tlu_i0_kill_writeb_r; // @[dec_decode_ctl.scala 693:60]
-  wire  div_flush = _T_809 | _T_812; // @[dec_decode_ctl.scala 692:62]
-  wire  _T_813 = io_dec_div_active & div_flush; // @[dec_decode_ctl.scala 697:51]
-  wire  _T_814 = ~div_e1_to_r; // @[dec_decode_ctl.scala 698:26]
-  wire  _T_815 = io_dec_div_active & _T_814; // @[dec_decode_ctl.scala 698:24]
-  wire  _T_816 = r_d_bits_i0rd == io_div_waddr_wb; // @[dec_decode_ctl.scala 698:56]
-  wire  _T_817 = _T_815 & _T_816; // @[dec_decode_ctl.scala 698:39]
-  wire  _T_818 = _T_817 & i0_wen_r; // @[dec_decode_ctl.scala 698:77]
-  wire  nonblock_div_cancel = _T_813 | _T_818; // @[dec_decode_ctl.scala 697:65]
+  wire  _T_804 = x_d_bits_i0div & x_d_valid; // @[dec_decode_ctl.scala 689:45]
+  wire  div_e1_to_r = _T_804 | _T_548; // @[dec_decode_ctl.scala 689:58]
+  wire  _T_807 = x_d_bits_i0rd == 5'h0; // @[dec_decode_ctl.scala 691:77]
+  wire  _T_808 = _T_804 & _T_807; // @[dec_decode_ctl.scala 691:60]
+  wire  _T_810 = _T_804 & io_dec_tlu_flush_lower_r; // @[dec_decode_ctl.scala 692:33]
+  wire  _T_811 = _T_808 | _T_810; // @[dec_decode_ctl.scala 691:94]
+  wire  _T_813 = _T_548 & io_dec_tlu_flush_lower_r; // @[dec_decode_ctl.scala 693:33]
+  wire  _T_814 = _T_813 & io_dec_tlu_i0_kill_writeb_r; // @[dec_decode_ctl.scala 693:60]
+  wire  div_flush = _T_811 | _T_814; // @[dec_decode_ctl.scala 692:62]
+  wire  _T_815 = io_dec_div_active & div_flush; // @[dec_decode_ctl.scala 697:51]
+  wire  _T_816 = ~div_e1_to_r; // @[dec_decode_ctl.scala 698:26]
+  wire  _T_817 = io_dec_div_active & _T_816; // @[dec_decode_ctl.scala 698:24]
+  wire  _T_818 = r_d_bits_i0rd == io_div_waddr_wb; // @[dec_decode_ctl.scala 698:56]
+  wire  _T_819 = _T_817 & _T_818; // @[dec_decode_ctl.scala 698:39]
+  wire  _T_820 = _T_819 & i0_wen_r; // @[dec_decode_ctl.scala 698:77]
+  wire  nonblock_div_cancel = _T_815 | _T_820; // @[dec_decode_ctl.scala 697:65]
   wire  i0_div_decode_d = i0_legal_decode_d & i0_dp_div; // @[dec_decode_ctl.scala 701:55]
-  wire  _T_820 = ~io_exu_div_wren; // @[dec_decode_ctl.scala 703:62]
-  wire  _T_821 = io_dec_div_active & _T_820; // @[dec_decode_ctl.scala 703:60]
-  wire  _T_822 = ~nonblock_div_cancel; // @[dec_decode_ctl.scala 703:81]
-  wire  _T_823 = _T_821 & _T_822; // @[dec_decode_ctl.scala 703:79]
-  reg  _T_824; // @[dec_decode_ctl.scala 705:54]
-  reg [4:0] _T_833; // @[Reg.scala 27:20]
+  wire  _T_822 = ~io_exu_div_wren; // @[dec_decode_ctl.scala 703:62]
+  wire  _T_823 = io_dec_div_active & _T_822; // @[dec_decode_ctl.scala 703:60]
+  wire  _T_824 = ~nonblock_div_cancel; // @[dec_decode_ctl.scala 703:81]
+  wire  _T_825 = _T_823 & _T_824; // @[dec_decode_ctl.scala 703:79]
+  reg  _T_826; // @[dec_decode_ctl.scala 705:54]
+  reg [4:0] _T_835; // @[Reg.scala 27:20]
   reg [31:0] i0_inst_x; // @[lib.scala 358:16]
   reg [31:0] i0_inst_r; // @[lib.scala 358:16]
   reg [31:0] i0_inst_wb; // @[lib.scala 358:16]
-  reg [31:0] _T_840; // @[lib.scala 358:16]
+  reg [31:0] _T_842; // @[lib.scala 358:16]
   reg [30:0] i0_pc_wb; // @[lib.scala 358:16]
-  reg [30:0] _T_843; // @[lib.scala 358:16]
+  reg [30:0] _T_845; // @[lib.scala 358:16]
   reg [30:0] dec_i0_pc_r; // @[lib.scala 358:16]
-  wire [31:0] _T_845 = {io_dec_alu_exu_i0_pc_x,1'h0}; // @[Cat.scala 29:58]
-  wire [12:0] _T_846 = {last_br_immed_x,1'h0}; // @[Cat.scala 29:58]
-  wire [12:0] _T_849 = _T_845[12:1] + _T_846[12:1]; // @[lib.scala 52:31]
-  wire [18:0] _T_852 = _T_845[31:13] + 19'h1; // @[lib.scala 53:27]
-  wire [18:0] _T_855 = _T_845[31:13] - 19'h1; // @[lib.scala 54:27]
-  wire  _T_858 = ~_T_849[12]; // @[lib.scala 56:28]
-  wire  _T_859 = _T_846[12] ^ _T_858; // @[lib.scala 56:26]
-  wire  _T_862 = ~_T_846[12]; // @[lib.scala 57:20]
-  wire  _T_864 = _T_862 & _T_849[12]; // @[lib.scala 57:26]
-  wire  _T_868 = _T_846[12] & _T_858; // @[lib.scala 58:26]
-  wire [18:0] _T_870 = _T_859 ? _T_845[31:13] : 19'h0; // @[Mux.scala 27:72]
-  wire [18:0] _T_871 = _T_864 ? _T_852 : 19'h0; // @[Mux.scala 27:72]
-  wire [18:0] _T_872 = _T_868 ? _T_855 : 19'h0; // @[Mux.scala 27:72]
-  wire [18:0] _T_873 = _T_870 | _T_871; // @[Mux.scala 27:72]
-  wire [18:0] _T_874 = _T_873 | _T_872; // @[Mux.scala 27:72]
-  wire [31:0] temp_pred_correct_npc_x = {_T_874,_T_849[11:0],1'h0}; // @[Cat.scala 29:58]
-  wire  _T_890_mul = i0_rs1_depend_i0_r & i0_r_c_mul; // @[dec_decode_ctl.scala 744:61]
-  wire  _T_890_alu = i0_rs1_depend_i0_r & i0_r_c_alu; // @[dec_decode_ctl.scala 744:61]
-  wire  i0_rs1_class_d_mul = i0_rs1_depend_i0_x ? i0_x_c_mul : _T_890_mul; // @[dec_decode_ctl.scala 744:24]
-  wire  i0_rs1_class_d_alu = i0_rs1_depend_i0_x ? i0_x_c_alu : _T_890_alu; // @[dec_decode_ctl.scala 744:24]
-  wire  _T_899_mul = i0_rs2_depend_i0_r & i0_r_c_mul; // @[dec_decode_ctl.scala 746:61]
-  wire  _T_899_alu = i0_rs2_depend_i0_r & i0_r_c_alu; // @[dec_decode_ctl.scala 746:61]
-  wire  i0_rs2_class_d_mul = i0_rs2_depend_i0_x ? i0_x_c_mul : _T_899_mul; // @[dec_decode_ctl.scala 746:24]
-  wire  i0_rs2_class_d_alu = i0_rs2_depend_i0_x ? i0_x_c_alu : _T_899_alu; // @[dec_decode_ctl.scala 746:24]
-  wire  _T_912 = io_decode_exu_dec_i0_rs1_en_d & io_dec_nonblock_load_wen; // @[dec_decode_ctl.scala 764:73]
-  wire  _T_913 = io_dec_nonblock_load_waddr == i0r_rs1; // @[dec_decode_ctl.scala 764:130]
-  wire  i0_rs1_nonblock_load_bypass_en_d = _T_912 & _T_913; // @[dec_decode_ctl.scala 764:100]
-  wire  _T_914 = io_decode_exu_dec_i0_rs2_en_d & io_dec_nonblock_load_wen; // @[dec_decode_ctl.scala 766:73]
-  wire  _T_915 = io_dec_nonblock_load_waddr == i0r_rs2; // @[dec_decode_ctl.scala 766:130]
-  wire  i0_rs2_nonblock_load_bypass_en_d = _T_914 & _T_915; // @[dec_decode_ctl.scala 766:100]
-  wire  _T_917 = i0_rs1_class_d_alu | i0_rs1_class_d_mul; // @[dec_decode_ctl.scala 769:66]
-  wire  _T_918 = i0_rs1_depth_d[0] & _T_917; // @[dec_decode_ctl.scala 769:45]
-  wire  _T_920 = i0_rs1_depth_d[0] & i0_rs1_class_d_load; // @[dec_decode_ctl.scala 769:108]
-  wire  _T_923 = _T_917 | i0_rs1_class_d_load; // @[dec_decode_ctl.scala 769:196]
-  wire  _T_924 = i0_rs1_depth_d[1] & _T_923; // @[dec_decode_ctl.scala 769:153]
-  wire [2:0] i0_rs1bypass = {_T_918,_T_920,_T_924}; // @[Cat.scala 29:58]
-  wire  _T_928 = i0_rs2_class_d_alu | i0_rs2_class_d_mul; // @[dec_decode_ctl.scala 771:67]
-  wire  _T_929 = i0_rs2_depth_d[0] & _T_928; // @[dec_decode_ctl.scala 771:45]
-  wire  _T_931 = i0_rs2_depth_d[0] & i0_rs2_class_d_load; // @[dec_decode_ctl.scala 771:109]
-  wire  _T_934 = _T_928 | i0_rs2_class_d_load; // @[dec_decode_ctl.scala 771:196]
-  wire  _T_935 = i0_rs2_depth_d[1] & _T_934; // @[dec_decode_ctl.scala 771:153]
-  wire [2:0] i0_rs2bypass = {_T_929,_T_931,_T_935}; // @[Cat.scala 29:58]
-  wire  _T_941 = i0_rs1bypass[1] | i0_rs1bypass[0]; // @[dec_decode_ctl.scala 773:86]
-  wire  _T_943 = ~i0_rs1bypass[2]; // @[dec_decode_ctl.scala 773:107]
-  wire  _T_944 = _T_943 & i0_rs1_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 773:124]
-  wire  _T_945 = _T_941 | _T_944; // @[dec_decode_ctl.scala 773:104]
-  wire  _T_950 = i0_rs2bypass[1] | i0_rs2bypass[0]; // @[dec_decode_ctl.scala 774:86]
-  wire  _T_952 = ~i0_rs2bypass[2]; // @[dec_decode_ctl.scala 774:107]
-  wire  _T_953 = _T_952 & i0_rs2_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 774:124]
-  wire  _T_954 = _T_950 | _T_953; // @[dec_decode_ctl.scala 774:104]
-  wire  _T_961 = ~i0_rs1bypass[1]; // @[dec_decode_ctl.scala 780:6]
-  wire  _T_963 = ~i0_rs1bypass[0]; // @[dec_decode_ctl.scala 780:25]
-  wire  _T_964 = _T_961 & _T_963; // @[dec_decode_ctl.scala 780:23]
-  wire  _T_965 = _T_964 & i0_rs1_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 780:42]
-  wire [31:0] _T_967 = i0_rs1bypass[1] ? io_lsu_result_m : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_968 = i0_rs1bypass[0] ? i0_result_r_raw : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_969 = _T_965 ? io_dctl_busbuff_lsu_nonblock_load_data : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_970 = _T_967 | _T_968; // @[Mux.scala 27:72]
-  wire  _T_978 = ~i0_rs2bypass[1]; // @[dec_decode_ctl.scala 785:6]
-  wire  _T_980 = ~i0_rs2bypass[0]; // @[dec_decode_ctl.scala 785:25]
-  wire  _T_981 = _T_978 & _T_980; // @[dec_decode_ctl.scala 785:23]
-  wire  _T_982 = _T_981 & i0_rs2_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 785:42]
-  wire [31:0] _T_984 = i0_rs2bypass[1] ? io_lsu_result_m : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_985 = i0_rs2bypass[0] ? i0_result_r_raw : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_986 = _T_982 ? io_dctl_busbuff_lsu_nonblock_load_data : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_987 = _T_984 | _T_985; // @[Mux.scala 27:72]
-  wire  _T_990 = i0_dp_raw_load | i0_dp_raw_store; // @[dec_decode_ctl.scala 787:68]
-  wire  _T_991 = io_dec_ib0_valid_d & _T_990; // @[dec_decode_ctl.scala 787:50]
-  wire  _T_992 = ~io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 787:89]
-  wire  _T_993 = _T_991 & _T_992; // @[dec_decode_ctl.scala 787:87]
-  wire  _T_995 = _T_993 & _T_496; // @[dec_decode_ctl.scala 787:121]
-  wire  _T_997 = ~io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 789:6]
-  wire  _T_998 = _T_997 & i0_dp_lsu; // @[dec_decode_ctl.scala 789:38]
-  wire  _T_999 = _T_998 & i0_dp_load; // @[dec_decode_ctl.scala 789:50]
-  wire  _T_1004 = _T_998 & i0_dp_store; // @[dec_decode_ctl.scala 790:50]
-  wire [11:0] _T_1008 = {io_dec_i0_instr_d[31:25],i0r_rd}; // @[Cat.scala 29:58]
-  wire [11:0] _T_1009 = _T_999 ? io_dec_i0_instr_d[31:20] : 12'h0; // @[Mux.scala 27:72]
-  wire [11:0] _T_1010 = _T_1004 ? _T_1008 : 12'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_847 = {io_dec_alu_exu_i0_pc_x,1'h0}; // @[Cat.scala 29:58]
+  wire [12:0] _T_848 = {last_br_immed_x,1'h0}; // @[Cat.scala 29:58]
+  wire [12:0] _T_851 = _T_847[12:1] + _T_848[12:1]; // @[lib.scala 52:31]
+  wire [18:0] _T_854 = _T_847[31:13] + 19'h1; // @[lib.scala 53:27]
+  wire [18:0] _T_857 = _T_847[31:13] - 19'h1; // @[lib.scala 54:27]
+  wire  _T_860 = ~_T_851[12]; // @[lib.scala 56:28]
+  wire  _T_861 = _T_848[12] ^ _T_860; // @[lib.scala 56:26]
+  wire  _T_864 = ~_T_848[12]; // @[lib.scala 57:20]
+  wire  _T_866 = _T_864 & _T_851[12]; // @[lib.scala 57:26]
+  wire  _T_870 = _T_848[12] & _T_860; // @[lib.scala 58:26]
+  wire [18:0] _T_872 = _T_861 ? _T_847[31:13] : 19'h0; // @[Mux.scala 27:72]
+  wire [18:0] _T_873 = _T_866 ? _T_854 : 19'h0; // @[Mux.scala 27:72]
+  wire [18:0] _T_874 = _T_870 ? _T_857 : 19'h0; // @[Mux.scala 27:72]
+  wire [18:0] _T_875 = _T_872 | _T_873; // @[Mux.scala 27:72]
+  wire [18:0] _T_876 = _T_875 | _T_874; // @[Mux.scala 27:72]
+  wire [31:0] temp_pred_correct_npc_x = {_T_876,_T_851[11:0],1'h0}; // @[Cat.scala 29:58]
+  wire  _T_892_mul = i0_rs1_depend_i0_r & i0_r_c_mul; // @[dec_decode_ctl.scala 744:61]
+  wire  _T_892_alu = i0_rs1_depend_i0_r & i0_r_c_alu; // @[dec_decode_ctl.scala 744:61]
+  wire  i0_rs1_class_d_mul = i0_rs1_depend_i0_x ? i0_x_c_mul : _T_892_mul; // @[dec_decode_ctl.scala 744:24]
+  wire  i0_rs1_class_d_alu = i0_rs1_depend_i0_x ? i0_x_c_alu : _T_892_alu; // @[dec_decode_ctl.scala 744:24]
+  wire  _T_901_mul = i0_rs2_depend_i0_r & i0_r_c_mul; // @[dec_decode_ctl.scala 746:61]
+  wire  _T_901_alu = i0_rs2_depend_i0_r & i0_r_c_alu; // @[dec_decode_ctl.scala 746:61]
+  wire  i0_rs2_class_d_mul = i0_rs2_depend_i0_x ? i0_x_c_mul : _T_901_mul; // @[dec_decode_ctl.scala 746:24]
+  wire  i0_rs2_class_d_alu = i0_rs2_depend_i0_x ? i0_x_c_alu : _T_901_alu; // @[dec_decode_ctl.scala 746:24]
+  wire  _T_914 = io_decode_exu_dec_i0_rs1_en_d & io_dec_nonblock_load_wen; // @[dec_decode_ctl.scala 764:73]
+  wire  _T_915 = io_dec_nonblock_load_waddr == i0r_rs1; // @[dec_decode_ctl.scala 764:130]
+  wire  i0_rs1_nonblock_load_bypass_en_d = _T_914 & _T_915; // @[dec_decode_ctl.scala 764:100]
+  wire  _T_916 = io_decode_exu_dec_i0_rs2_en_d & io_dec_nonblock_load_wen; // @[dec_decode_ctl.scala 766:73]
+  wire  _T_917 = io_dec_nonblock_load_waddr == i0r_rs2; // @[dec_decode_ctl.scala 766:130]
+  wire  i0_rs2_nonblock_load_bypass_en_d = _T_916 & _T_917; // @[dec_decode_ctl.scala 766:100]
+  wire  _T_919 = i0_rs1_class_d_alu | i0_rs1_class_d_mul; // @[dec_decode_ctl.scala 769:66]
+  wire  _T_920 = i0_rs1_depth_d[0] & _T_919; // @[dec_decode_ctl.scala 769:45]
+  wire  _T_922 = i0_rs1_depth_d[0] & i0_rs1_class_d_load; // @[dec_decode_ctl.scala 769:108]
+  wire  _T_925 = _T_919 | i0_rs1_class_d_load; // @[dec_decode_ctl.scala 769:196]
+  wire  _T_926 = i0_rs1_depth_d[1] & _T_925; // @[dec_decode_ctl.scala 769:153]
+  wire [2:0] i0_rs1bypass = {_T_920,_T_922,_T_926}; // @[Cat.scala 29:58]
+  wire  _T_930 = i0_rs2_class_d_alu | i0_rs2_class_d_mul; // @[dec_decode_ctl.scala 771:67]
+  wire  _T_931 = i0_rs2_depth_d[0] & _T_930; // @[dec_decode_ctl.scala 771:45]
+  wire  _T_933 = i0_rs2_depth_d[0] & i0_rs2_class_d_load; // @[dec_decode_ctl.scala 771:109]
+  wire  _T_936 = _T_930 | i0_rs2_class_d_load; // @[dec_decode_ctl.scala 771:196]
+  wire  _T_937 = i0_rs2_depth_d[1] & _T_936; // @[dec_decode_ctl.scala 771:153]
+  wire [2:0] i0_rs2bypass = {_T_931,_T_933,_T_937}; // @[Cat.scala 29:58]
+  wire  _T_943 = i0_rs1bypass[1] | i0_rs1bypass[0]; // @[dec_decode_ctl.scala 773:86]
+  wire  _T_945 = ~i0_rs1bypass[2]; // @[dec_decode_ctl.scala 773:107]
+  wire  _T_946 = _T_945 & i0_rs1_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 773:124]
+  wire  _T_947 = _T_943 | _T_946; // @[dec_decode_ctl.scala 773:104]
+  wire  _T_952 = i0_rs2bypass[1] | i0_rs2bypass[0]; // @[dec_decode_ctl.scala 774:86]
+  wire  _T_954 = ~i0_rs2bypass[2]; // @[dec_decode_ctl.scala 774:107]
+  wire  _T_955 = _T_954 & i0_rs2_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 774:124]
+  wire  _T_956 = _T_952 | _T_955; // @[dec_decode_ctl.scala 774:104]
+  wire  _T_963 = ~i0_rs1bypass[1]; // @[dec_decode_ctl.scala 780:6]
+  wire  _T_965 = ~i0_rs1bypass[0]; // @[dec_decode_ctl.scala 780:25]
+  wire  _T_966 = _T_963 & _T_965; // @[dec_decode_ctl.scala 780:23]
+  wire  _T_967 = _T_966 & i0_rs1_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 780:42]
+  wire [31:0] _T_969 = i0_rs1bypass[1] ? io_lsu_result_m : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_970 = i0_rs1bypass[0] ? i0_result_r_raw : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_971 = _T_967 ? io_dctl_busbuff_lsu_nonblock_load_data : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_972 = _T_969 | _T_970; // @[Mux.scala 27:72]
+  wire  _T_980 = ~i0_rs2bypass[1]; // @[dec_decode_ctl.scala 785:6]
+  wire  _T_982 = ~i0_rs2bypass[0]; // @[dec_decode_ctl.scala 785:25]
+  wire  _T_983 = _T_980 & _T_982; // @[dec_decode_ctl.scala 785:23]
+  wire  _T_984 = _T_983 & i0_rs2_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 785:42]
+  wire [31:0] _T_986 = i0_rs2bypass[1] ? io_lsu_result_m : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_987 = i0_rs2bypass[0] ? i0_result_r_raw : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_988 = _T_984 ? io_dctl_busbuff_lsu_nonblock_load_data : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_989 = _T_986 | _T_987; // @[Mux.scala 27:72]
+  wire  _T_992 = i0_dp_raw_load | i0_dp_raw_store; // @[dec_decode_ctl.scala 787:68]
+  wire  _T_993 = io_dec_ib0_valid_d & _T_992; // @[dec_decode_ctl.scala 787:50]
+  wire  _T_994 = ~io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 787:89]
+  wire  _T_995 = _T_993 & _T_994; // @[dec_decode_ctl.scala 787:87]
+  wire  _T_997 = _T_995 & _T_496; // @[dec_decode_ctl.scala 787:121]
+  wire  _T_999 = ~io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 789:6]
+  wire  _T_1000 = _T_999 & i0_dp_lsu; // @[dec_decode_ctl.scala 789:38]
+  wire  _T_1001 = _T_1000 & i0_dp_load; // @[dec_decode_ctl.scala 789:50]
+  wire  _T_1006 = _T_1000 & i0_dp_store; // @[dec_decode_ctl.scala 790:50]
+  wire [11:0] _T_1010 = {io_dec_i0_instr_d[31:25],i0r_rd}; // @[Cat.scala 29:58]
+  wire [11:0] _T_1011 = _T_1001 ? io_dec_i0_instr_d[31:20] : 12'h0; // @[Mux.scala 27:72]
+  wire [11:0] _T_1012 = _T_1006 ? _T_1010 : 12'h0; // @[Mux.scala 27:72]
   rvclkhdr rvclkhdr ( // @[lib.scala 327:22]
     .io_l1clk(rvclkhdr_io_l1clk),
     .io_clk(rvclkhdr_io_clk),
@@ -47318,11 +47318,11 @@ module dec_decode_ctl(
   assign io_decode_exu_dec_i0_rs1_en_d = i0_dp_rs1 & _T_559; // @[dec_decode_ctl.scala 594:35]
   assign io_decode_exu_dec_i0_rs2_en_d = i0_dp_rs2 & _T_561; // @[dec_decode_ctl.scala 595:35]
   assign io_decode_exu_dec_i0_immed_d = _T_566 | _T_567; // @[dec_decode_ctl.scala 603:32]
-  assign io_decode_exu_dec_i0_rs1_bypass_data_d = _T_970 | _T_969; // @[dec_decode_ctl.scala 777:42]
-  assign io_decode_exu_dec_i0_rs2_bypass_data_d = _T_987 | _T_986; // @[dec_decode_ctl.scala 782:42]
+  assign io_decode_exu_dec_i0_rs1_bypass_data_d = _T_972 | _T_971; // @[dec_decode_ctl.scala 777:42]
+  assign io_decode_exu_dec_i0_rs2_bypass_data_d = _T_989 | _T_988; // @[dec_decode_ctl.scala 782:42]
   assign io_decode_exu_dec_i0_select_pc_d = _T_41 ? 1'h0 : i0_dp_raw_pc; // @[dec_decode_ctl.scala 241:36]
-  assign io_decode_exu_dec_i0_rs1_bypass_en_d = {i0_rs1bypass[2],_T_945}; // @[dec_decode_ctl.scala 773:45]
-  assign io_decode_exu_dec_i0_rs2_bypass_en_d = {i0_rs2bypass[2],_T_954}; // @[dec_decode_ctl.scala 774:45]
+  assign io_decode_exu_dec_i0_rs1_bypass_en_d = {i0_rs1bypass[2],_T_947}; // @[dec_decode_ctl.scala 773:45]
+  assign io_decode_exu_dec_i0_rs2_bypass_en_d = {i0_rs2bypass[2],_T_956}; // @[dec_decode_ctl.scala 774:45]
   assign io_decode_exu_mul_p_valid = i0_exulegal_decode_d & i0_dp_mul; // @[dec_decode_ctl.scala 97:23 dec_decode_ctl.scala 397:32]
   assign io_decode_exu_mul_p_bits_rs1_sign = _T_41 ? 1'h0 : i0_dp_raw_rs1_sign; // @[dec_decode_ctl.scala 97:23 dec_decode_ctl.scala 398:37]
   assign io_decode_exu_mul_p_bits_rs2_sign = _T_41 ? 1'h0 : i0_dp_raw_rs2_sign; // @[dec_decode_ctl.scala 97:23 dec_decode_ctl.scala 399:37]
@@ -47331,18 +47331,18 @@ module dec_decode_ctl(
   assign io_decode_exu_dec_extint_stall = _T_339; // @[dec_decode_ctl.scala 402:34]
   assign io_dec_alu_dec_i0_alu_decode_d = i0_exulegal_decode_d & i0_dp_alu; // @[dec_decode_ctl.scala 542:34]
   assign io_dec_alu_dec_csr_ren_d = _T_41 ? 1'h0 : i0_dp_raw_csr_read; // @[dec_decode_ctl.scala 424:29]
-  assign io_dec_alu_dec_i0_br_immed_d = _T_771 ? i0_br_offset : _T_784; // @[dec_decode_ctl.scala 681:32]
+  assign io_dec_alu_dec_i0_br_immed_d = _T_773 ? i0_br_offset : _T_786; // @[dec_decode_ctl.scala 681:32]
   assign io_dec_div_div_p_valid = i0_exulegal_decode_d & i0_dp_div; // @[dec_decode_ctl.scala 393:29]
   assign io_dec_div_div_p_bits_unsign = _T_41 ? 1'h0 : i0_dp_raw_unsign; // @[dec_decode_ctl.scala 394:34]
   assign io_dec_div_div_p_bits_rem = _T_41 ? 1'h0 : i0_dp_raw_rem; // @[dec_decode_ctl.scala 395:34]
-  assign io_dec_div_dec_div_cancel = _T_813 | _T_818; // @[dec_decode_ctl.scala 700:37]
-  assign io_dec_i0_inst_wb1 = _T_840; // @[dec_decode_ctl.scala 723:22]
-  assign io_dec_i0_pc_wb1 = _T_843; // @[dec_decode_ctl.scala 726:20]
+  assign io_dec_div_dec_div_cancel = _T_815 | _T_820; // @[dec_decode_ctl.scala 700:37]
+  assign io_dec_i0_inst_wb1 = _T_842; // @[dec_decode_ctl.scala 723:22]
+  assign io_dec_i0_pc_wb1 = _T_845; // @[dec_decode_ctl.scala 726:20]
   assign io_dec_i0_rs1_d = io_dec_i0_instr_d[19:15]; // @[dec_decode_ctl.scala 597:19]
   assign io_dec_i0_rs2_d = io_dec_i0_instr_d[24:20]; // @[dec_decode_ctl.scala 598:19]
   assign io_dec_i0_waddr_r = r_d_bits_i0rd; // @[dec_decode_ctl.scala 664:27]
-  assign io_dec_i0_wen_r = _T_760 & _T_761; // @[dec_decode_ctl.scala 666:32]
-  assign io_dec_i0_wdata_r = _T_767 ? io_lsu_result_corr_r : i0_result_r_raw; // @[dec_decode_ctl.scala 667:26]
+  assign io_dec_i0_wen_r = _T_762 & _T_763; // @[dec_decode_ctl.scala 666:32]
+  assign io_dec_i0_wdata_r = _T_769 ? io_lsu_result_corr_r : i0_result_r_raw; // @[dec_decode_ctl.scala 667:26]
   assign io_lsu_p_valid = io_decode_exu_dec_extint_stall | lsu_decode_d; // @[dec_decode_ctl.scala 404:12 dec_decode_ctl.scala 409:24 dec_decode_ctl.scala 411:35]
   assign io_lsu_p_bits_fast_int = io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 404:12 dec_decode_ctl.scala 408:29]
   assign io_lsu_p_bits_by = io_decode_exu_dec_extint_stall ? 1'h0 : i0_dp_by; // @[dec_decode_ctl.scala 404:12 dec_decode_ctl.scala 414:40]
@@ -47353,17 +47353,17 @@ module dec_decode_ctl(
   assign io_lsu_p_bits_unsign = io_decode_exu_dec_extint_stall ? 1'h0 : i0_dp_unsign; // @[dec_decode_ctl.scala 404:12 dec_decode_ctl.scala 420:40]
   assign io_lsu_p_bits_store_data_bypass_d = io_decode_exu_dec_extint_stall ? 1'h0 : store_data_bypass_d; // @[dec_decode_ctl.scala 404:12 dec_decode_ctl.scala 418:40]
   assign io_lsu_p_bits_load_ldst_bypass_d = io_decode_exu_dec_extint_stall ? 1'h0 : load_ldst_bypass_d; // @[dec_decode_ctl.scala 404:12 dec_decode_ctl.scala 417:40]
-  assign io_div_waddr_wb = _T_833; // @[dec_decode_ctl.scala 711:19]
-  assign io_dec_lsu_valid_raw_d = _T_995 | io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 787:26]
-  assign io_dec_lsu_offset_d = _T_1009 | _T_1010; // @[dec_decode_ctl.scala 788:23]
+  assign io_div_waddr_wb = _T_835; // @[dec_decode_ctl.scala 711:19]
+  assign io_dec_lsu_valid_raw_d = _T_997 | io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 787:26]
+  assign io_dec_lsu_offset_d = _T_1011 | _T_1012; // @[dec_decode_ctl.scala 788:23]
   assign io_dec_csr_wen_unq_d = _T_349 | i0_csr_write; // @[dec_decode_ctl.scala 433:24]
   assign io_dec_csr_any_unq_d = i0_dp_csr_read | i0_csr_write; // @[dec_decode_ctl.scala 499:24]
   assign io_dec_csr_rdaddr_d = io_dec_i0_instr_d[31:20]; // @[dec_decode_ctl.scala 436:24]
-  assign io_dec_csr_wen_r = _T_352 & _T_757; // @[dec_decode_ctl.scala 441:20]
+  assign io_dec_csr_wen_r = _T_352 & _T_759; // @[dec_decode_ctl.scala 441:20]
   assign io_dec_csr_wraddr_r = r_d_bits_csrwaddr; // @[dec_decode_ctl.scala 437:23]
   assign io_dec_csr_wrdata_r = r_d_bits_csrwonly ? i0_result_corr_r : write_csr_data; // @[dec_decode_ctl.scala 484:24]
   assign io_dec_csr_stall_int_ff = _T_359 & _T_360; // @[dec_decode_ctl.scala 444:27]
-  assign io_dec_tlu_i0_valid_r = r_d_valid & _T_746; // @[dec_decode_ctl.scala 548:29]
+  assign io_dec_tlu_i0_valid_r = r_d_valid & _T_748; // @[dec_decode_ctl.scala 548:29]
   assign io_dec_tlu_packet_r_legal = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_legal; // @[dec_decode_ctl.scala 582:39]
   assign io_dec_tlu_packet_r_icaf = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf; // @[dec_decode_ctl.scala 582:39]
   assign io_dec_tlu_packet_r_icaf_f1 = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf_f1; // @[dec_decode_ctl.scala 582:39]
@@ -47384,7 +47384,7 @@ module dec_decode_ctl(
   assign io_dec_nonblock_load_waddr = _T_246 | _T_238; // @[dec_decode_ctl.scala 321:29 dec_decode_ctl.scala 331:29]
   assign io_dec_pause_state = pause_stall; // @[dec_decode_ctl.scala 468:22]
   assign io_dec_pause_state_cg = pause_stall & _T_423; // @[dec_decode_ctl.scala 472:25]
-  assign io_dec_div_active = _T_824; // @[dec_decode_ctl.scala 705:21]
+  assign io_dec_div_active = _T_826; // @[dec_decode_ctl.scala 705:21]
   assign io_dec_aln_dec_i0_decode_d = _T_493 & _T_470; // @[dec_decode_ctl.scala 522:30 dec_decode_ctl.scala 588:30]
   assign rvclkhdr_io_clk = clock; // @[lib.scala 328:17]
   assign rvclkhdr_io_en = _T_15 | _T_16; // @[lib.scala 329:16]
@@ -47403,19 +47403,19 @@ module dec_decode_ctl(
   assign rvclkhdr_4_io_en = shift_illegal & _T_467; // @[lib.scala 355:17]
   assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 356:24]
   assign rvclkhdr_5_io_clk = clock; // @[lib.scala 364:18]
-  assign rvclkhdr_5_io_en = _T_707 | io_clk_override; // @[lib.scala 365:17]
+  assign rvclkhdr_5_io_en = _T_709 | io_clk_override; // @[lib.scala 365:17]
   assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 366:24]
   assign rvclkhdr_6_io_clk = clock; // @[lib.scala 364:18]
-  assign rvclkhdr_6_io_en = _T_707 | io_clk_override; // @[lib.scala 365:17]
+  assign rvclkhdr_6_io_en = _T_709 | io_clk_override; // @[lib.scala 365:17]
   assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[lib.scala 366:24]
   assign rvclkhdr_7_io_clk = clock; // @[lib.scala 364:18]
-  assign rvclkhdr_7_io_en = _T_707 | io_clk_override; // @[lib.scala 365:17]
+  assign rvclkhdr_7_io_en = _T_709 | io_clk_override; // @[lib.scala 365:17]
   assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 366:24]
   assign rvclkhdr_8_io_clk = clock; // @[lib.scala 364:18]
-  assign rvclkhdr_8_io_en = _T_710 | io_clk_override; // @[lib.scala 365:17]
+  assign rvclkhdr_8_io_en = _T_712 | io_clk_override; // @[lib.scala 365:17]
   assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[lib.scala 366:24]
   assign rvclkhdr_9_io_clk = clock; // @[lib.scala 364:18]
-  assign rvclkhdr_9_io_en = _T_713 | io_clk_override; // @[lib.scala 365:17]
+  assign rvclkhdr_9_io_en = _T_715 | io_clk_override; // @[lib.scala 365:17]
   assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[lib.scala 366:24]
   assign rvclkhdr_10_io_clk = clock; // @[lib.scala 354:18]
   assign rvclkhdr_10_io_en = i0_pipe_en[2] | io_clk_override; // @[lib.scala 355:17]
@@ -47523,7 +47523,7 @@ initial begin
   _RAND_19 = {1{`RANDOM}};
   x_d_bits_i0rd = _RAND_19[4:0];
   _RAND_20 = {1{`RANDOM}};
-  _T_704 = _RAND_20[2:0];
+  _T_706 = _RAND_20[2:0];
   _RAND_21 = {1{`RANDOM}};
   nonblock_load_valid_m_delay = _RAND_21[0:0];
   _RAND_22 = {1{`RANDOM}};
@@ -47647,9 +47647,9 @@ initial begin
   _RAND_81 = {1{`RANDOM}};
   last_br_immed_x = _RAND_81[11:0];
   _RAND_82 = {1{`RANDOM}};
-  _T_824 = _RAND_82[0:0];
+  _T_826 = _RAND_82[0:0];
   _RAND_83 = {1{`RANDOM}};
-  _T_833 = _RAND_83[4:0];
+  _T_835 = _RAND_83[4:0];
   _RAND_84 = {1{`RANDOM}};
   i0_inst_x = _RAND_84[31:0];
   _RAND_85 = {1{`RANDOM}};
@@ -47657,11 +47657,11 @@ initial begin
   _RAND_86 = {1{`RANDOM}};
   i0_inst_wb = _RAND_86[31:0];
   _RAND_87 = {1{`RANDOM}};
-  _T_840 = _RAND_87[31:0];
+  _T_842 = _RAND_87[31:0];
   _RAND_88 = {1{`RANDOM}};
   i0_pc_wb = _RAND_88[30:0];
   _RAND_89 = {1{`RANDOM}};
-  _T_843 = _RAND_89[30:0];
+  _T_845 = _RAND_89[30:0];
   _RAND_90 = {1{`RANDOM}};
   dec_i0_pc_r = _RAND_90[30:0];
 `endif // RANDOMIZE_REG_INIT
@@ -47726,7 +47726,7 @@ initial begin
     x_d_bits_i0rd = 5'h0;
   end
   if (reset) begin
-    _T_704 = 3'h0;
+    _T_706 = 3'h0;
   end
   if (reset) begin
     nonblock_load_valid_m_delay = 1'h0;
@@ -47773,6 +47773,12 @@ initial begin
   if (reset) begin
     x_d_bits_i0v = 1'h0;
   end
+  if (reset) begin
+    i0_x_c_load = 1'h0;
+  end
+  if (reset) begin
+    i0_r_c_load = 1'h0;
+  end
   if (reset) begin
     r_d_bits_csrwen = 1'h0;
   end
@@ -47878,6 +47884,18 @@ initial begin
   if (reset) begin
     r_d_bits_i0div = 1'h0;
   end
+  if (reset) begin
+    i0_x_c_mul = 1'h0;
+  end
+  if (reset) begin
+    i0_x_c_alu = 1'h0;
+  end
+  if (reset) begin
+    i0_r_c_mul = 1'h0;
+  end
+  if (reset) begin
+    i0_r_c_alu = 1'h0;
+  end
   if (reset) begin
     x_d_bits_i0store = 1'h0;
   end
@@ -47894,10 +47912,10 @@ initial begin
     last_br_immed_x = 12'h0;
   end
   if (reset) begin
-    _T_824 = 1'h0;
+    _T_826 = 1'h0;
   end
   if (reset) begin
-    _T_833 = 5'h0;
+    _T_835 = 5'h0;
   end
   if (reset) begin
     i0_inst_x = 32'h0;
@@ -47909,13 +47927,13 @@ initial begin
     i0_inst_wb = 32'h0;
   end
   if (reset) begin
-    _T_840 = 32'h0;
+    _T_842 = 32'h0;
   end
   if (reset) begin
     i0_pc_wb = 31'h0;
   end
   if (reset) begin
-    _T_843 = 31'h0;
+    _T_845 = 31'h0;
   end
   if (reset) begin
     dec_i0_pc_r = 31'h0;
@@ -47926,26 +47944,6 @@ end // initial
 `FIRRTL_AFTER_INITIAL
 `endif
 `endif // SYNTHESIS
-  always @(posedge io_active_clk) begin
-    if (i0_x_ctl_en) begin
-      i0_x_c_load <= i0_d_c_load;
-    end
-    if (i0_r_ctl_en) begin
-      i0_r_c_load <= i0_x_c_load;
-    end
-    if (i0_x_ctl_en) begin
-      i0_x_c_mul <= i0_d_c_mul;
-    end
-    if (i0_x_ctl_en) begin
-      i0_x_c_alu <= i0_d_c_alu;
-    end
-    if (i0_r_ctl_en) begin
-      i0_r_c_mul <= i0_x_c_mul;
-    end
-    if (i0_r_ctl_en) begin
-      i0_r_c_alu <= i0_x_c_alu;
-    end
-  end
   always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
     if (reset) begin
       tlu_wr_pause_r1 <= 1'h0;
@@ -48108,9 +48106,9 @@ end // initial
   end
   always @(posedge io_active_clk or posedge reset) begin
     if (reset) begin
-      _T_704 <= 3'h0;
+      _T_706 <= 3'h0;
     end else begin
-      _T_704 <= i0_pipe_en[3:1];
+      _T_706 <= i0_pipe_en[3:1];
     end
   end
   always @(posedge io_active_clk or posedge reset) begin
@@ -48131,7 +48129,7 @@ end // initial
     if (reset) begin
       r_d_bits_i0v <= 1'h0;
     end else begin
-      r_d_bits_i0v <= _T_736 & _T_280;
+      r_d_bits_i0v <= _T_738 & _T_280;
     end
   end
   always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin
@@ -48242,6 +48240,20 @@ end // initial
       x_d_bits_i0v <= i0_rd_en_d & i0_legal_decode_d;
     end
   end
+  always @(posedge io_active_clk or posedge reset) begin
+    if (reset) begin
+      i0_x_c_load <= 1'h0;
+    end else if (i0_x_ctl_en) begin
+      i0_x_c_load <= i0_d_c_load;
+    end
+  end
+  always @(posedge io_active_clk or posedge reset) begin
+    if (reset) begin
+      i0_r_c_load <= 1'h0;
+    end else if (i0_r_ctl_en) begin
+      i0_r_c_load <= i0_x_c_load;
+    end
+  end
   always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin
     if (reset) begin
       r_d_bits_csrwen <= 1'h0;
@@ -48253,7 +48265,7 @@ end // initial
     if (reset) begin
       r_d_valid <= 1'h0;
     end else begin
-      r_d_valid <= _T_740 & _T_280;
+      r_d_valid <= _T_742 & _T_280;
     end
   end
   always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin
@@ -48324,7 +48336,7 @@ end // initial
   always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin
     if (reset) begin
       i0_result_r_raw <= 32'h0;
-    end else if (_T_764) begin
+    end else if (_T_766) begin
       i0_result_r_raw <= io_lsu_result_m;
     end else begin
       i0_result_r_raw <= io_decode_exu_exu_i0_result_x;
@@ -48493,6 +48505,34 @@ end // initial
       r_d_bits_i0div <= x_d_bits_i0div;
     end
   end
+  always @(posedge io_active_clk or posedge reset) begin
+    if (reset) begin
+      i0_x_c_mul <= 1'h0;
+    end else if (i0_x_ctl_en) begin
+      i0_x_c_mul <= i0_d_c_mul;
+    end
+  end
+  always @(posedge io_active_clk or posedge reset) begin
+    if (reset) begin
+      i0_x_c_alu <= 1'h0;
+    end else if (i0_x_ctl_en) begin
+      i0_x_c_alu <= i0_d_c_alu;
+    end
+  end
+  always @(posedge io_active_clk or posedge reset) begin
+    if (reset) begin
+      i0_r_c_mul <= 1'h0;
+    end else if (i0_r_ctl_en) begin
+      i0_r_c_mul <= i0_x_c_mul;
+    end
+  end
+  always @(posedge io_active_clk or posedge reset) begin
+    if (reset) begin
+      i0_r_c_alu <= 1'h0;
+    end else if (i0_r_ctl_en) begin
+      i0_r_c_alu <= i0_x_c_alu;
+    end
+  end
   always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin
     if (reset) begin
       x_d_bits_i0store <= 1'h0;
@@ -48525,7 +48565,7 @@ end // initial
     if (reset) begin
       last_br_immed_x <= 12'h0;
     end else if (io_decode_exu_i0_ap_predict_nt) begin
-      last_br_immed_x <= _T_784;
+      last_br_immed_x <= _T_786;
     end else if (_T_314) begin
       last_br_immed_x <= i0_pcall_imm[11:0];
     end else begin
@@ -48534,16 +48574,16 @@ end // initial
   end
   always @(posedge io_free_clk or posedge reset) begin
     if (reset) begin
-      _T_824 <= 1'h0;
+      _T_826 <= 1'h0;
     end else begin
-      _T_824 <= i0_div_decode_d | _T_823;
+      _T_826 <= i0_div_decode_d | _T_825;
     end
   end
   always @(posedge clock or posedge reset) begin
     if (reset) begin
-      _T_833 <= 5'h0;
+      _T_835 <= 5'h0;
     end else if (i0_div_decode_d) begin
-      _T_833 <= i0r_rd;
+      _T_835 <= i0r_rd;
     end
   end
   always @(posedge rvclkhdr_13_io_l1clk or posedge reset) begin
@@ -48571,9 +48611,9 @@ end // initial
   end
   always @(posedge rvclkhdr_16_io_l1clk or posedge reset) begin
     if (reset) begin
-      _T_840 <= 32'h0;
+      _T_842 <= 32'h0;
     end else begin
-      _T_840 <= i0_inst_wb;
+      _T_842 <= i0_inst_wb;
     end
   end
   always @(posedge rvclkhdr_17_io_l1clk or posedge reset) begin
@@ -48585,9 +48625,9 @@ end // initial
   end
   always @(posedge rvclkhdr_18_io_l1clk or posedge reset) begin
     if (reset) begin
-      _T_843 <= 31'h0;
+      _T_845 <= 31'h0;
     end else begin
-      _T_843 <= i0_pc_wb;
+      _T_845 <= i0_pc_wb;
     end
   end
   always @(posedge rvclkhdr_19_io_l1clk or posedge reset) begin
diff --git a/src/main/scala/dec/dec_decode_ctl.scala b/src/main/scala/dec/dec_decode_ctl.scala
index b4ec20b6..14fffb3a 100644
--- a/src/main/scala/dec/dec_decode_ctl.scala
+++ b/src/main/scala/dec/dec_decode_ctl.scala
@@ -617,8 +617,8 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{
   i0_d_c.load               :=  i0_dp.load & i0_legal_decode_d
   i0_d_c.alu                :=  i0_dp.alu  & i0_legal_decode_d
 
-  val i0_x_c = withClock(io.active_clk){RegEnable(i0_d_c, i0_x_ctl_en.asBool)}
-  val i0_r_c = withClock(io.active_clk){RegEnable(i0_x_c, i0_r_ctl_en.asBool)}
+  val i0_x_c = withClock(io.active_clk){RegEnable(i0_d_c,0.U.asTypeOf(i0_d_c), i0_x_ctl_en.asBool)}
+  val i0_r_c = withClock(io.active_clk){RegEnable(i0_x_c,0.U.asTypeOf(i0_x_c), i0_r_ctl_en.asBool)}
   i0_pipe_en := Cat(io.dec_aln.dec_i0_decode_d,withClock(io.active_clk){RegNext(i0_pipe_en(3,1), init=0.U)})
 
   i0_x_ctl_en               := (i0_pipe_en(3,2).orR | io.clk_override)
@@ -667,7 +667,7 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{
   io.dec_i0_wdata_r      :=  i0_result_corr_r
 
   val i0_result_r_raw = rvdffe(i0_result_x,i0_r_data_en.asBool,clock,io.scan_mode)
-  if ( LOAD_TO_USE_PLUS1 == 1 ) {
+  if ( LOAD_TO_USE_PLUS1) {
     i0_result_x         := io.decode_exu.exu_i0_result_x
     i0_result_r         := Mux((r_d.bits.i0v & r_d.bits.i0load).asBool,io.lsu_result_m, i0_result_r_raw)
   }
@@ -747,7 +747,7 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{
   i0_rs2_depth_d := Mux(i0_rs2_depend_i0_x.asBool,1.U(2.W),Mux(i0_rs2_depend_i0_r.asBool, 2.U(2.W), 0.U))
 
   // stores will bypass load data in the lsu pipe
-  if (LOAD_TO_USE_PLUS1 == 1) {
+  if (LOAD_TO_USE_PLUS1) {
     i0_load_block_d  := (i0_rs1_class_d.load & i0_rs1_depth_d) | (i0_rs2_class_d.load & i0_rs2_depth_d(0) & !i0_dp.store)
     load_ldst_bypass_d := (i0_dp.load | i0_dp.store) & i0_rs1_depth_d(1) & i0_rs1_class_d.load
     store_data_bypass_d := i0_dp.store & (i0_rs2_depth_d(1) & i0_rs2_class_d.load)
diff --git a/target/scala-2.12/classes/dec/dec_decode_ctl.class b/target/scala-2.12/classes/dec/dec_decode_ctl.class
index c6e38a51..5d8a7c40 100644
Binary files a/target/scala-2.12/classes/dec/dec_decode_ctl.class and b/target/scala-2.12/classes/dec/dec_decode_ctl.class differ