From 85b5ac0f8b05726393d55a15617df640c389c58f Mon Sep 17 00:00:00 2001 From: colin Date: Fri, 11 Mar 2022 03:05:36 +0000 Subject: [PATCH] Add clk output for led. --- soc/soc_top.sv | 28 ++++++++++++++++++---------- 1 file changed, 18 insertions(+), 10 deletions(-) diff --git a/soc/soc_top.sv b/soc/soc_top.sv index 9a8db939..811fb5c0 100644 --- a/soc/soc_top.sv +++ b/soc/soc_top.sv @@ -6,7 +6,8 @@ module soc_top ( input jtag_tck, input jtag_tms, input jtag_tdi, - input jtag_trst_n + input jtag_trst_n, + output clk_o ); logic nmi_int; @@ -301,6 +302,13 @@ module soc_top ( nmi_int = 0; end + localparam WIDTH = $clog2(25_000_000); + reg [WIDTH-1:0] clk_count; + assign clk_o = clk_count[WIDTH-1]; + always @(posedge clk) begin + clk_count <= clk_count + 1'b1; + end + //=========================================================================- // RTL instance //=========================================================================- @@ -503,10 +511,10 @@ module soc_top ( .io_timer_int (1'b0), .io_extintsrc_req('0), - .io_lsu_bus_clk_en ( 1'b1 ),// Clock ratio b/w cpu core clk & AHB master interface - .io_ifu_bus_clk_en ( 1'b1 ),// Clock ratio b/w cpu core clk & AHB master interface - .io_dbg_bus_clk_en ( 1'b1 ),// Clock ratio b/w cpu core clk & AHB Debug master interface - .io_dma_bus_clk_en ( 1'b1 ),// Clock ratio b/w cpu core clk & AHB slave interface + .io_lsu_bus_clk_en(1'b1), // Clock ratio b/w cpu core clk & AHB master interface + .io_ifu_bus_clk_en(1'b1), // Clock ratio b/w cpu core clk & AHB master interface + .io_dbg_bus_clk_en(1'b1), // Clock ratio b/w cpu core clk & AHB Debug master interface + .io_dma_bus_clk_en(1'b1), // Clock ratio b/w cpu core clk & AHB slave interface .io_rv_trace_pkt_rv_i_insn_ip (trace_rv_i_insn_ip), .io_rv_trace_pkt_rv_i_address_ip (trace_rv_i_address_ip), @@ -529,12 +537,12 @@ module soc_top ( .io_mpc_reset_run_req (1'b1), // Start running after reset .io_debug_brkpt_status(debug_brkpt_status), - .io_i_cpu_halt_req(1'b0), // Async halt req to CPU - .io_o_cpu_halt_ack(o_cpu_halt_ack), // core response to halt - .io_o_cpu_halt_status ( o_cpu_halt_status ), // 1'b1 indicates core is halted - .io_i_cpu_run_req(1'b0), // Async restart req to CPU + .io_i_cpu_halt_req (1'b0), // Async halt req to CPU + .io_o_cpu_halt_ack (o_cpu_halt_ack), // core response to halt + .io_o_cpu_halt_status (o_cpu_halt_status), // 1'b1 indicates core is halted + .io_i_cpu_run_req (1'b0), // Async restart req to CPU .io_o_debug_mode_status(o_debug_mode_status), - .io_o_cpu_run_ack(o_cpu_run_ack), // Core response to run req + .io_o_cpu_run_ack (o_cpu_run_ack), // Core response to run req .io_dccm_ext_in_pkt_TEST1_0('0), .io_dccm_ext_in_pkt_TEST1_1('0),