Bus Buffer Update

This commit is contained in:
​Laraib Khan 2020-12-10 12:09:34 +05:00
parent 3a1fa4fbd7
commit 8616219c43
10 changed files with 9126 additions and 9114 deletions

6637
lsu.fir

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2467
lsu.v

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File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

View File

@ -296,7 +296,6 @@ class lsu_bus_buffer extends Module with RequireAsyncReset with lib {
val obuf_merge_en = WireInit(Bool(), false.B)
val obuf_merge_in = obuf_merge_en
val obuf_tag0_in = Mux(ibuf_buf_byp, WrPtr0_r, CmdPtr0)
//val Cmdptr1 = WireInit(UInt(DEPTH_LOG2.W), 0.U)
val obuf_tag1_in = Mux(ibuf_buf_byp, WrPtr1_r, CmdPtr1)
val obuf_cmd_done = WireInit(Bool(), false.B)
@ -549,7 +548,7 @@ class lsu_bus_buffer extends Module with RequireAsyncReset with lib {
(!lsu_nonblock_unsign & (lsu_nonblock_sz===0.U)) -> Cat(Fill(24,lsu_nonblock_data_unalgn(7)), lsu_nonblock_data_unalgn(7,0)),
(!lsu_nonblock_unsign & (lsu_nonblock_sz===1.U)) -> Cat(Fill(16,lsu_nonblock_data_unalgn(15)), lsu_nonblock_data_unalgn(15,0)),
(lsu_nonblock_sz===2.U) -> lsu_nonblock_data_unalgn))
bus_sideeffect_pend := (0 until DEPTH).map(i=>(buf_state(i)===resp_C) & buf_sideeffect(i) & io.tlu_busbuff.dec_tlu_sideeffect_posted_disable).reduce(_|_)
bus_sideeffect_pend := (0 until DEPTH).map(i=>(buf_state(i)===resp_C) & buf_sideeffect(i) & io.tlu_busbuff.dec_tlu_sideeffect_posted_disable).reduce(_|_) | (obuf_valid & obuf_sideeffect & io.tlu_busbuff.dec_tlu_sideeffect_posted_disable)
bus_addr_match_pending := Mux1H((0 until DEPTH).map(i=>(buf_state(i)===resp_C)->
(BUILD_AXI_NATIVE.B & obuf_valid & (obuf_addr(31,3)===buf_addr(i)(31,3)) & !((obuf_tag0===i.U) | (obuf_merge & (obuf_tag1===i.U))))))
@ -617,6 +616,7 @@ class lsu_bus_buffer extends Module with RequireAsyncReset with lib {
io.lsu_busreq_r := withClock(io.lsu_c2_r_clk){RegNext(io.lsu_busreq_m & !io.flush_r & !io.ld_full_hit_m, false.B)}
lsu_nonblock_load_valid_r := withClock(io.lsu_c2_r_clk){RegNext(io.dctl_busbuff.lsu_nonblock_load_valid_m, false.B)}
}
object busbuff extends App {
object bus_buffer extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new lsu_bus_buffer()))
}

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