diff --git a/src/main/scala/lib/ahb_to_axi4.scala b/src/main/scala/lib/ahb_to_axi4.scala
index 3975c47a..2dc7eb6d 100644
--- a/src/main/scala/lib/ahb_to_axi4.scala
+++ b/src/main/scala/lib/ahb_to_axi4.scala
@@ -180,6 +180,6 @@ class ahb_to_axi4(TAG : Int) extends Module with lib with RequireAsyncReset {
   bus_clk                 := rvclkhdr(clock, io.bus_clk_en, io.scan_mode)
 }
 
-object ahb_to_axi4 extends App {
-  println((new chisel3.stage.ChiselStage).emitVerilog(new ahb_to_axi4(3)))
-}
+//object ahb_to_axi4 extends App {
+ // println((new chisel3.stage.ChiselStage).emitVerilog(new ahb_to_axi4(3)))
+//}
diff --git a/src/main/scala/lib/axi4_to_ahb.scala b/src/main/scala/lib/axi4_to_ahb.scala
index 16944b78..3460c11f 100644
--- a/src/main/scala/lib/axi4_to_ahb.scala
+++ b/src/main/scala/lib/axi4_to_ahb.scala
@@ -335,6 +335,6 @@ class axi4_to_ahb(val TAG : Int = 3) extends Module with lib with RequireAsyncRe
   ahbm_data_clk := rvclkhdr(clock, ahbm_data_clken, io.scan_mode)
 }
 
-object axi4_to_ahb extends App {
-  println((new chisel3.stage.ChiselStage).emitVerilog(new axi4_to_ahb(3)))
-}
+//object axi4_to_ahb extends App {
+//  println((new chisel3.stage.ChiselStage).emitVerilog(new axi4_to_ahb(3)))
+//}
diff --git a/target/scala-2.12/classes/lib/ahb_to_axi4$.class b/target/scala-2.12/classes/lib/ahb_to_axi4$.class
deleted file mode 100644
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diff --git a/target/scala-2.12/classes/lib/ahb_to_axi4$delayedInit$body.class b/target/scala-2.12/classes/lib/ahb_to_axi4$delayedInit$body.class
deleted file mode 100644
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diff --git a/target/scala-2.12/classes/lib/ahb_to_axi4.class b/target/scala-2.12/classes/lib/ahb_to_axi4.class
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diff --git a/target/scala-2.12/classes/lib/axi4_to_ahb$.class b/target/scala-2.12/classes/lib/axi4_to_ahb$.class
index a5878803..1f02f9de 100644
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diff --git a/target/scala-2.12/classes/lib/axi4_to_ahb$delayedInit$body.class b/target/scala-2.12/classes/lib/axi4_to_ahb$delayedInit$body.class
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