IMC DONE

el2_ifu_mem_ctl.fir

@@ -4394,7 +4394,7 @@ circuit el2_ifu_mem_ctl :
     node _T_3265 = eq(_T_3264, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 663:9]
     node _T_3266 = and(_T_3265, iccm_correct_ecc) @[el2_ifu_mem_ctl.scala 663:50]
     node _T_3267 = cat(iccm_ecc_corr_index_ff, UInt<1>("h00")) @[Cat.scala 29:58]
-    node _T_3268 = bits(io.ifc_fetch_addr_bf, 15, 0) @[el2_ifu_mem_ctl.scala 663:124]
+    node _T_3268 = bits(io.ifc_fetch_addr_bf, 14, 0) @[el2_ifu_mem_ctl.scala 663:124]
     node _T_3269 = mux(_T_3266, _T_3267, _T_3268) @[el2_ifu_mem_ctl.scala 663:8]
     node _T_3270 = mux(_T_3263, io.dma_mem_addr, _T_3269) @[el2_ifu_mem_ctl.scala 662:25]
     io.iccm_rw_addr <= _T_3270 @[el2_ifu_mem_ctl.scala 662:19]

el2_ifu_mem_ctl.v

@@ -3394,8 +3394,8 @@ module el2_ifu_mem_ctl(
   wire  _T_3266 = _T_3244 & iccm_correct_ecc; // @[el2_ifu_mem_ctl.scala 663:50]
   reg [13:0] iccm_ecc_corr_index_ff; // @[Reg.scala 27:20]
   wire [14:0] _T_3267 = {iccm_ecc_corr_index_ff,1'h0}; // @[Cat.scala 29:58]
-  wire [15:0] _T_3269 = _T_3266 ? {{1'd0}, _T_3267} : io_ifc_fetch_addr_bf[15:0]; // @[el2_ifu_mem_ctl.scala 663:8]
+  wire [14:0] _T_3269 = _T_3266 ? _T_3267 : io_ifc_fetch_addr_bf[14:0]; // @[el2_ifu_mem_ctl.scala 663:8]
-  wire [31:0] _T_3270 = _T_3263 ? io_dma_mem_addr : {{16'd0}, _T_3269}; // @[el2_ifu_mem_ctl.scala 662:25]
+  wire [31:0] _T_3270 = _T_3263 ? io_dma_mem_addr : {{17'd0}, _T_3269}; // @[el2_ifu_mem_ctl.scala 662:25]
   wire  _T_3659 = _T_3497 == 7'h40; // @[el2_lib.scala 330:62]
   wire  _T_3660 = _T_3647[38] ^ _T_3659; // @[el2_lib.scala 330:44]
   wire [6:0] iccm_corrected_ecc_0 = {_T_3660,_T_3647[31],_T_3647[15],_T_3647[7],_T_3647[3],_T_3647[1:0]}; // @[Cat.scala 29:58]

src/main/scala/ifu/el2_ifu_mem_ctl.scala

@@ -660,7 +660,7 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
   io.iccm_dma_rdata := iccm_dma_rdata_temp
   val iccm_ecc_corr_index_ff = WireInit(UInt((ICCM_BITS-2).W), 0.U)
   io.iccm_rw_addr := Mux(ifc_dma_access_q_ok & io.dma_iccm_req  & !iccm_correct_ecc, io.dma_mem_addr,
-    Mux(!(ifc_dma_access_q_ok & io.dma_iccm_req) & iccm_correct_ecc, Cat(iccm_ecc_corr_index_ff, 0.U), io.ifc_fetch_addr_bf(ICCM_BITS-1,0)))
+    Mux(!(ifc_dma_access_q_ok & io.dma_iccm_req) & iccm_correct_ecc, Cat(iccm_ecc_corr_index_ff, 0.U), io.ifc_fetch_addr_bf(ICCM_BITS-2,0)))
   val ic_fetch_val_int_f = Cat(0.U(2.W), io.ic_fetch_val_f)
   val ic_fetch_val_shift_right = ic_fetch_val_int_f << ifu_fetch_addr_int_f(0)
   val iccm_rdmux_data = io.iccm_rd_data_ecc