Packets updated with Valid
This commit is contained in:
Laraib Khan
parent
37641a8a14
commit
89e70f46c8
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@ -0,0 +1,23 @@
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[
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{
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"class":"firrtl.EmitCircuitAnnotation",
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"emitter":"firrtl.VerilogEmitter"
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},
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{
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"class":"firrtl.transforms.BlackBoxResourceAnno",
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"target":"dmi_wrapper_module.dmi_wrapper",
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"resourceId":"/vsrc/dmi_wrapper.sv"
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},
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{
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"class":"firrtl.options.TargetDirAnnotation",
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"directory":"."
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},
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{
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"class":"firrtl.options.OutputAnnotationFileAnnotation",
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"file":"dmi_wrapper_module"
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},
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{
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"class":"firrtl.transforms.BlackBoxTargetDirAnno",
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"targetDir":"."
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}
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]
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@ -0,0 +1,59 @@
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;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
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circuit dmi_wrapper_module :
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extmodule dmi_wrapper :
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input trst_n : UInt<1>
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input tck : Clock
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input tms : UInt<1>
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input tdi : UInt<1>
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output tdo : UInt<1>
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output tdoEnable : UInt<1>
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input core_rst_n : AsyncReset
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input core_clk : Clock
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input jtag_id : UInt<31>
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input rd_data : UInt<32>
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output reg_wr_data : UInt<32>
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output reg_wr_addr : UInt<7>
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output reg_en : UInt<1>
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output reg_wr_en : UInt<1>
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output dmi_hard_reset : UInt<1>
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defname = dmi_wrapper
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module dmi_wrapper_module :
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input clock : Clock
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input reset : UInt<1>
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output io : {flip trst_n : UInt<1>, flip tck : Clock, flip tms : UInt<1>, flip tdi : UInt<1>, tdo : UInt<1>, tdoEnable : UInt<1>, flip core_rst_n : AsyncReset, flip core_clk : Clock, flip jtag_id : UInt<32>, flip rd_data : UInt<32>, reg_wr_data : UInt<32>, reg_wr_addr : UInt<7>, reg_en : UInt<1>, reg_wr_en : UInt<1>, dmi_hard_reset : UInt<1>}
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inst dwrap of dmi_wrapper @[dmi_wrapper.scala 45:21]
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dwrap.dmi_hard_reset is invalid
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dwrap.reg_wr_en is invalid
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dwrap.reg_en is invalid
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dwrap.reg_wr_addr is invalid
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dwrap.reg_wr_data is invalid
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dwrap.rd_data is invalid
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dwrap.jtag_id is invalid
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dwrap.core_clk is invalid
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dwrap.core_rst_n is invalid
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dwrap.tdoEnable is invalid
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dwrap.tdo is invalid
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dwrap.tdi is invalid
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dwrap.tms is invalid
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dwrap.tck is invalid
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dwrap.trst_n is invalid
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io.dmi_hard_reset <= dwrap.dmi_hard_reset @[dmi_wrapper.scala 46:12]
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io.reg_wr_en <= dwrap.reg_wr_en @[dmi_wrapper.scala 46:12]
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io.reg_en <= dwrap.reg_en @[dmi_wrapper.scala 46:12]
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io.reg_wr_addr <= dwrap.reg_wr_addr @[dmi_wrapper.scala 46:12]
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io.reg_wr_data <= dwrap.reg_wr_data @[dmi_wrapper.scala 46:12]
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dwrap.rd_data <= io.rd_data @[dmi_wrapper.scala 46:12]
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dwrap.jtag_id <= io.jtag_id @[dmi_wrapper.scala 46:12]
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dwrap.core_clk <= io.core_clk @[dmi_wrapper.scala 46:12]
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dwrap.core_rst_n <= io.core_rst_n @[dmi_wrapper.scala 46:12]
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io.tdoEnable <= dwrap.tdoEnable @[dmi_wrapper.scala 46:12]
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io.tdo <= dwrap.tdo @[dmi_wrapper.scala 46:12]
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dwrap.tdi <= io.tdi @[dmi_wrapper.scala 46:12]
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dwrap.tms <= io.tms @[dmi_wrapper.scala 46:12]
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dwrap.tck <= io.tck @[dmi_wrapper.scala 46:12]
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dwrap.trst_n <= io.trst_n @[dmi_wrapper.scala 46:12]
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@ -0,0 +1,67 @@
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module dmi_wrapper_module(
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input clock,
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input reset,
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input io_trst_n,
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input io_tck,
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input io_tms,
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input io_tdi,
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output io_tdo,
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output io_tdoEnable,
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input io_core_rst_n,
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input io_core_clk,
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input [31:0] io_jtag_id,
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input [31:0] io_rd_data,
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output [31:0] io_reg_wr_data,
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output [6:0] io_reg_wr_addr,
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output io_reg_en,
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output io_reg_wr_en,
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output io_dmi_hard_reset
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);
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wire dwrap_trst_n; // @[dmi_wrapper.scala 45:21]
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wire dwrap_tck; // @[dmi_wrapper.scala 45:21]
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wire dwrap_tms; // @[dmi_wrapper.scala 45:21]
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wire dwrap_tdi; // @[dmi_wrapper.scala 45:21]
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wire dwrap_tdo; // @[dmi_wrapper.scala 45:21]
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wire dwrap_tdoEnable; // @[dmi_wrapper.scala 45:21]
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wire dwrap_core_rst_n; // @[dmi_wrapper.scala 45:21]
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wire dwrap_core_clk; // @[dmi_wrapper.scala 45:21]
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wire [30:0] dwrap_jtag_id; // @[dmi_wrapper.scala 45:21]
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wire [31:0] dwrap_rd_data; // @[dmi_wrapper.scala 45:21]
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wire [31:0] dwrap_reg_wr_data; // @[dmi_wrapper.scala 45:21]
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wire [6:0] dwrap_reg_wr_addr; // @[dmi_wrapper.scala 45:21]
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wire dwrap_reg_en; // @[dmi_wrapper.scala 45:21]
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wire dwrap_reg_wr_en; // @[dmi_wrapper.scala 45:21]
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wire dwrap_dmi_hard_reset; // @[dmi_wrapper.scala 45:21]
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dmi_wrapper dwrap ( // @[dmi_wrapper.scala 45:21]
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.trst_n(dwrap_trst_n),
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.tck(dwrap_tck),
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.tms(dwrap_tms),
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.tdi(dwrap_tdi),
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.tdo(dwrap_tdo),
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.tdoEnable(dwrap_tdoEnable),
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.core_rst_n(dwrap_core_rst_n),
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.core_clk(dwrap_core_clk),
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.jtag_id(dwrap_jtag_id),
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.rd_data(dwrap_rd_data),
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.reg_wr_data(dwrap_reg_wr_data),
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.reg_wr_addr(dwrap_reg_wr_addr),
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.reg_en(dwrap_reg_en),
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.reg_wr_en(dwrap_reg_wr_en),
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.dmi_hard_reset(dwrap_dmi_hard_reset)
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);
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assign io_tdo = dwrap_tdo; // @[dmi_wrapper.scala 46:12]
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assign io_tdoEnable = dwrap_tdoEnable; // @[dmi_wrapper.scala 46:12]
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assign io_reg_wr_data = dwrap_reg_wr_data; // @[dmi_wrapper.scala 46:12]
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assign io_reg_wr_addr = dwrap_reg_wr_addr; // @[dmi_wrapper.scala 46:12]
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assign io_reg_en = dwrap_reg_en; // @[dmi_wrapper.scala 46:12]
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assign io_reg_wr_en = dwrap_reg_wr_en; // @[dmi_wrapper.scala 46:12]
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assign io_dmi_hard_reset = dwrap_dmi_hard_reset; // @[dmi_wrapper.scala 46:12]
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assign dwrap_trst_n = io_trst_n; // @[dmi_wrapper.scala 46:12]
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assign dwrap_tck = io_tck; // @[dmi_wrapper.scala 46:12]
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assign dwrap_tms = io_tms; // @[dmi_wrapper.scala 46:12]
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assign dwrap_tdi = io_tdi; // @[dmi_wrapper.scala 46:12]
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assign dwrap_core_rst_n = io_core_rst_n; // @[dmi_wrapper.scala 46:12]
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assign dwrap_core_clk = io_core_clk; // @[dmi_wrapper.scala 46:12]
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assign dwrap_jtag_id = io_jtag_id[30:0]; // @[dmi_wrapper.scala 46:12]
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assign dwrap_rd_data = io_rd_data; // @[dmi_wrapper.scala 46:12]
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endmodule
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@ -0,0 +1,169 @@
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module el2_mem #(
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parameter ICACHE_BEAT_BITS,
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parameter ICCM_BITS,
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parameter ICACHE_NUM_WAYS,
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parameter DCCM_BYTE_WIDTH,
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parameter ICCM_BANK_INDEX_LO,
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parameter ICACHE_BANK_BITS,
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parameter DCCM_BITS,
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parameter ICACHE_BEAT_ADDR_HI,
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parameter ICCM_INDEX_BITS,
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parameter ICCM_BANK_HI,
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parameter ICACHE_BANKS_WAY,
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parameter ICACHE_INDEX_HI,
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parameter DCCM_NUM_BANKS,
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parameter ICACHE_BANK_HI,
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parameter ICACHE_BANK_LO,
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parameter DCCM_ENABLE,
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parameter ICACHE_TAG_LO,
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parameter ICACHE_DATA_INDEX_LO,
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parameter ICCM_NUM_BANKS,
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parameter ICACHE_ECC,
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parameter ICACHE_ENABLE,
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parameter DCCM_BANK_BITS,
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parameter ICCM_ENABLE,
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parameter ICCM_BANK_BITS,
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parameter ICACHE_TAG_DEPTH,
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parameter ICACHE_WAYPACK,
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parameter DCCM_SIZE,
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parameter DCCM_FDATA_WIDTH,
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parameter ICACHE_TAG_INDEX_LO,
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parameter ICACHE_DATA_DEPTH)
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(
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input logic clk,
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input logic rst_l,
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input logic dccm_clk_override,
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input logic icm_clk_override,
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input logic dec_tlu_core_ecc_disable,
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//DCCM ports
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input logic dccm_wren,
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input logic dccm_rden,
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input logic [DCCM_BITS-1:0] dccm_wr_addr_lo,
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input logic [DCCM_BITS-1:0] dccm_wr_addr_hi,
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input logic [DCCM_BITS-1:0] dccm_rd_addr_lo,
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input logic [DCCM_BITS-1:0] dccm_rd_addr_hi,
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input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo,
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input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi,
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output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo,
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output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi,
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//`ifdef DCCM_ENABLE
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//`endif
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//ICCM ports
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input logic [ICCM_BITS-1:1] iccm_rw_addr,
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input logic iccm_buf_correct_ecc, // ICCM is doing a single bit error correct cycle
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input logic iccm_correction_state, // ICCM is doing a single bit error correct cycle
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input logic iccm_wren,
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input logic iccm_rden,
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input logic [2:0] iccm_wr_size,
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input logic [77:0] iccm_wr_data,
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output logic [63:0] iccm_rd_data,
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output logic [77:0] iccm_rd_data_ecc,
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// Icache and Itag Ports
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input logic [31:1] ic_rw_addr,
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input logic [ICACHE_NUM_WAYS-1:0] ic_tag_valid,
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input logic [ICACHE_NUM_WAYS-1:0] ic_wr_en,
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input logic ic_rd_en,
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input logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache.
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input logic ic_sel_premux_data, // Premux data sel
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input logic [ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data, // Data to fill to the Icache. With ECC
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input logic [70:0] ic_debug_wr_data, // Debug wr cache.
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output logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
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input logic [ICACHE_INDEX_HI:3] ic_debug_addr, // Read/Write addresss to the Icache.
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input logic ic_debug_rd_en, // Icache debug rd
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input logic ic_debug_wr_en, // Icache debug wr
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input logic ic_debug_tag_array, // Debug tag array
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input logic [ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr.
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output logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
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output logic [25:0] ictag_debug_rd_data,// Debug icache tag.
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output logic [ICACHE_BANKS_WAY-1:0] ic_eccerr, // ecc error per bank
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output logic [ICACHE_BANKS_WAY-1:0] ic_parerr, // parity error per bank
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output logic [ICACHE_NUM_WAYS-1:0] ic_rd_hit,
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output logic ic_tag_perr, // Icache Tag parity error
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input logic scan_mode
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);
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// DCCM Instantiation
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if (DCCM_ENABLE == 1) begin: Gen_dccm_enable
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el2_lsu_dccm_mem #(
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.DCCM_BYTE_WIDTH(DCCM_BYTE_WIDTH),
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.DCCM_BITS(DCCM_BITS),
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.DCCM_NUM_BANKS(DCCM_NUM_BANKS),
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.DCCM_BANK_BITS(DCCM_BANK_BITS),
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.DCCM_SIZE(DCCM_SIZE),
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.DCCM_FDATA_WIDTH(DCCM_FDATA_WIDTH)) dccm (
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.clk_override(dccm_clk_override),
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.*
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);
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end else begin: Gen_dccm_disable
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assign dccm_rd_data_lo = '0;
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assign dccm_rd_data_hi = '0;
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end
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if ( ICACHE_ENABLE ) begin: icache
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el2_ifu_ic_mem #(
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.ICACHE_BEAT_BITS(ICACHE_BEAT_BITS),
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.ICACHE_NUM_WAYS(ICACHE_NUM_WAYS),
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.ICACHE_BANK_BITS(ICACHE_BANK_BITS),
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.ICACHE_BEAT_ADDR_HI(ICACHE_BEAT_ADDR_HI),
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.ICACHE_BANKS_WAY(ICACHE_BANKS_WAY),
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.ICACHE_INDEX_HI(ICACHE_INDEX_HI),
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.ICACHE_BANK_HI(ICACHE_BANK_HI),
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.ICACHE_BANK_LO(ICACHE_BANK_LO),
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.ICACHE_TAG_LO(ICACHE_TAG_LO),
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.ICACHE_DATA_INDEX_LO(ICACHE_DATA_INDEX_LO),
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.ICACHE_ECC(ICACHE_ECC),
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.ICACHE_TAG_DEPTH(ICACHE_TAG_DEPTH),
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.ICACHE_WAYPACK(ICACHE_WAYPACK),
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.ICACHE_TAG_INDEX_LO(ICACHE_TAG_INDEX_LO),
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.ICACHE_DATA_DEPTH(ICACHE_DATA_DEPTH)) icm (
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.clk_override(icm_clk_override),
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.*
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);
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end
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else begin
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assign ic_rd_hit[ICACHE_NUM_WAYS-1:0] = '0;
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assign ic_tag_perr = '0 ;
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assign ic_rd_data = '0 ;
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assign ictag_debug_rd_data = '0 ;
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end // else: !if( ICACHE_ENABLE )
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if (ICCM_ENABLE) begin : iccm
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el2_ifu_iccm_mem #(
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.ICCM_BITS(ICCM_BITS),
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.ICCM_BANK_INDEX_LO(ICCM_BANK_INDEX_LO),
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.ICCM_INDEX_BITS(ICCM_INDEX_BITS),
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.ICCM_BANK_HI(ICCM_BANK_HI),
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.ICCM_NUM_BANKS(ICCM_NUM_BANKS),
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.ICCM_BANK_BITS(ICCM_BANK_BITS)) iccm (.*,
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.clk_override(icm_clk_override),
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.iccm_rw_addr(iccm_rw_addr[ICCM_BITS-1:1]),
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.iccm_rd_data(iccm_rd_data[63:0])
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);
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end
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else begin
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assign iccm_rd_data = '0 ;
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assign iccm_rd_data_ecc = '0 ;
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end
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endmodule
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File diff suppressed because one or more lines are too long
15
el2_swerv.v
15
el2_swerv.v
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@ -59920,6 +59920,9 @@ initial begin
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_RAND_20 = {1{`RANDOM}};
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data0_reg = _RAND_20[31:0];
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`endif // RANDOMIZE_REG_INIT
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if (io_dbg_rst_l) begin
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dm_temp_0 = 1'h0;
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end
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`endif // RANDOMIZE
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end // initial
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`ifdef FIRRTL_AFTER_INITIAL
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@ -59983,11 +59986,6 @@ end // initial
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end else if (dmcontrol_wren) begin
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dm_temp <= _T_139;
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end
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if (io_dbg_rst_l) begin
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dm_temp_0 <= 1'h0;
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end else if (dmcontrol_wren) begin
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dm_temp_0 <= io_dmi_reg_wdata[0];
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end
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if (_T_29) begin
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dmstatus_havereset <= 1'h0;
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end else if (dmstatus_havereset_wren) begin
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@ -60163,6 +60161,13 @@ end // initial
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data0_reg <= data0_din;
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end
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end
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always @(posedge rvclkhdr_io_l1clk or posedge io_dbg_rst_l) begin
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if (io_dbg_rst_l) begin
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dm_temp_0 <= 1'h0;
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end else if (dmcontrol_wren) begin
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dm_temp_0 <= io_dmi_reg_wdata[0];
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end
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end
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endmodule
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module el2_exu_alu_ctl(
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input clock,
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|
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@ -0,0 +1,997 @@
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[
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{
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"class":"firrtl.EmitCircuitAnnotation",
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"emitter":"firrtl.VerilogEmitter"
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},
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{
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"class":"firrtl.transforms.BlackBoxResourceAnno",
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"target":"el2_swerv_wrapper.gated_latch",
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"resourceId":"/vsrc/gated_latch.v"
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},
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{
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"class":"firrtl.transforms.DontTouchAnnotation",
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"target":"~el2_swerv_wrapper|el2_pic_ctrl>selected_int_priority"
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},
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{
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"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_4_2"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_4_0"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_3_4"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_3_2"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_3_0"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_2_8"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_2_6"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_2_4"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_2_2"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_2_0"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_1_16"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_1_14"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_1_12"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_1_10"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_1_8"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_1_6"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_1_4"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_1_2"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_1_0"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_0_32"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_0_30"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_0_28"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_0_26"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_0_24"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_0_22"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_0_20"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_0_18"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_0_16"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_0_14"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_0_12"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_0_10"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_0_8"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_0_6"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_0_4"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_0_2"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_0_0"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_w_prior_en_0_0"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_w_prior_en_0_1"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_w_prior_en_0_2"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_w_prior_en_0_3"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_w_prior_en_0_4"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_w_prior_en_0_5"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_w_prior_en_0_6"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_w_prior_en_0_7"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_w_prior_en_0_8"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_w_prior_en_0_9"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_w_prior_en_0_10"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_w_prior_en_0_11"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_w_prior_en_0_12"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_w_prior_en_0_13"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_w_prior_en_0_14"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_w_prior_en_0_15"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_w_prior_en_0_16"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_w_prior_en_0_17"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_w_prior_en_0_18"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_w_prior_en_0_19"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_w_prior_en_0_20"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_w_prior_en_0_21"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_w_prior_en_0_22"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_w_prior_en_0_23"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_w_prior_en_0_24"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_w_prior_en_0_25"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_w_prior_en_0_26"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_w_prior_en_0_27"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_w_prior_en_0_28"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_w_prior_en_0_29"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_w_prior_en_0_30"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_w_prior_en_0_31"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_w_prior_en_0_32"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_w_prior_en_0_33"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_0_1"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_0_3"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_0_5"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_0_7"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_0_9"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_0_11"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_0_13"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_0_15"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_0_17"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_0_19"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_0_21"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_0_23"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_0_25"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_0_27"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_0_29"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_0_31"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_0_33"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_1_1"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_1_3"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_1_5"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_1_7"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_1_9"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_1_11"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_1_13"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_1_15"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_1_17"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_1_18"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_1_19"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_1_20"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_1_21"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_1_22"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_1_23"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_1_24"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_1_25"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_1_26"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_1_27"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_1_28"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_1_29"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_1_30"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_1_31"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_1_32"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_1_33"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_2_1"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_2_3"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_2_5"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_2_7"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_2_9"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_2_10"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_2_11"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_2_12"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_2_13"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_2_14"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_2_15"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_2_16"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_2_17"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_2_18"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_2_19"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_2_20"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_2_21"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_2_22"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_2_23"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_2_24"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_2_25"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_2_26"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_2_27"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_2_28"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_2_29"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_2_30"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_2_31"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_2_32"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_2_33"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_3_1"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_3_3"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_3_5"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_3_6"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_3_7"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_3_8"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_3_9"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_3_10"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_3_11"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_3_12"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_3_13"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_3_14"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_3_15"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_3_16"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_3_17"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_3_18"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_3_19"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_3_20"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_3_21"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_3_22"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_3_23"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_3_24"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_3_25"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_3_26"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_3_27"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_3_28"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_3_29"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_3_30"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_3_31"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_3_32"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_3_33"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_4_1"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_4_3"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_4_4"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_4_5"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_4_6"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_4_7"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_4_8"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_4_9"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_4_10"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_4_11"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_4_12"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_4_13"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_4_14"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_4_15"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_4_16"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_4_17"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_4_18"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_4_19"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_4_20"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_4_21"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_4_22"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_4_23"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_4_24"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_4_25"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_4_26"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_4_27"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_4_28"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_4_29"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_4_30"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_4_31"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_4_32"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_4_33"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_0"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_1"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_2"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_3"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_4"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_5"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_6"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_7"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_8"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_9"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_10"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_11"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_12"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_13"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_14"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_15"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_16"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_17"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_18"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_19"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_20"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_21"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_22"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_23"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_24"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_25"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_26"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_27"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_28"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_29"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_30"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_31"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_32"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_33"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_exu>i0_rs2_d"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
||||
"target":"~el2_swerv_wrapper|el2_dec_trigger>io_dec_i0_trigger_match_d"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.BlackBoxResourceAnno",
|
||||
"target":"el2_swerv_wrapper.dmi_wrapper",
|
||||
"resourceId":"/vsrc/dmi_wrapper.sv"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.BlackBoxResourceAnno",
|
||||
"target":"el2_swerv_wrapper.el2_mem",
|
||||
"resourceId":"/vsrc/el2_mem.sv"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.options.TargetDirAnnotation",
|
||||
"directory":"."
|
||||
},
|
||||
{
|
||||
"class":"firrtl.options.OutputAnnotationFileAnnotation",
|
||||
"file":"el2_swerv_wrapper"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
|
||||
"targetDir":"."
|
||||
}
|
||||
]
|
||||
File diff suppressed because one or more lines are too long
File diff suppressed because it is too large
Load Diff
|
|
@ -1 +1,3 @@
|
|||
/home/laraibkhan/Desktop/SweRV-Chislified/gated_latch.v
|
||||
/home/laraibkhan/Desktop/SweRV-Chislified/gated_latch.v
|
||||
/home/laraibkhan/Desktop/SweRV-Chislified/dmi_wrapper.sv
|
||||
/home/laraibkhan/Desktop/SweRV-Chislified/el2_mem.sv
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -7,331 +7,329 @@ import lsu._
|
|||
import lib._
|
||||
import include._
|
||||
import dbg._
|
||||
class el2_swerv_bundle extends Bundle with el2_lib{
|
||||
val dbg_rst_l = Input(AsyncReset())
|
||||
val rst_vec = Input(UInt(31.W))
|
||||
val nmi_int = Input(Bool())
|
||||
val nmi_vec = Input(UInt(31.W))
|
||||
val core_rst_l = Output(AsyncReset())
|
||||
val trace_rv_i_insn_ip = Output(UInt(32.W))
|
||||
val trace_rv_i_address_ip = Output(UInt(32.W))
|
||||
val trace_rv_i_valid_ip = Output(UInt(2.W))
|
||||
val trace_rv_i_exception_ip = Output(UInt(2.W))
|
||||
val trace_rv_i_ecause_ip = Output(UInt(5.W))
|
||||
val trace_rv_i_interrupt_ip = Output(UInt(2.W))
|
||||
val trace_rv_i_tval_ip = Output(UInt(32.W))
|
||||
val dccm_clk_override = Output(Bool())
|
||||
val icm_clk_override = Output(Bool())
|
||||
val dec_tlu_core_ecc_disable = Output(Bool())
|
||||
val i_cpu_halt_req = Input(Bool())
|
||||
val i_cpu_run_req = Input(Bool())
|
||||
val o_cpu_halt_ack = Output(Bool())
|
||||
val o_cpu_halt_status = Output(Bool())
|
||||
val o_cpu_run_ack = Output(Bool())
|
||||
val o_debug_mode_status = Output(Bool())
|
||||
val core_id = Input(UInt(28.W))
|
||||
val mpc_debug_halt_req = Input(Bool())
|
||||
val mpc_debug_run_req = Input(Bool())
|
||||
val mpc_reset_run_req = Input(Bool())
|
||||
val mpc_debug_halt_ack = Output(Bool())
|
||||
val mpc_debug_run_ack = Output(Bool())
|
||||
val debug_brkpt_status = Output(Bool())
|
||||
val dec_tlu_perfcnt0 = Output(Bool())
|
||||
val dec_tlu_perfcnt1 = Output(Bool())
|
||||
val dec_tlu_perfcnt2 = Output(Bool())
|
||||
val dec_tlu_perfcnt3 = Output(Bool())
|
||||
val dccm_wren = Output(Bool())
|
||||
val dccm_rden = Output(Bool())
|
||||
val dccm_wr_addr_lo = Output(UInt(DCCM_BITS.W))
|
||||
val dccm_wr_addr_hi = Output(UInt(DCCM_BITS.W))
|
||||
val dccm_rd_addr_lo = Output(UInt(DCCM_BITS.W))
|
||||
val dccm_rd_addr_hi = Output(UInt(DCCM_BITS.W))
|
||||
|
||||
val dccm_wr_data_lo = Output(UInt(DCCM_FDATA_WIDTH.W))
|
||||
val dccm_wr_data_hi = Output(UInt(DCCM_FDATA_WIDTH.W))
|
||||
val dccm_rd_data_lo = Input(UInt(DCCM_FDATA_WIDTH.W))
|
||||
val dccm_rd_data_hi = Input(UInt(DCCM_FDATA_WIDTH.W))
|
||||
|
||||
val iccm_rw_addr = Output(UInt((ICCM_BITS-1).W))
|
||||
val iccm_wren = Output(Bool())
|
||||
val iccm_rden = Output(Bool())
|
||||
val iccm_wr_size = Output(UInt(3.W))
|
||||
val iccm_wr_data = Output(UInt(78.W))
|
||||
val iccm_buf_correct_ecc = Output(Bool())
|
||||
val iccm_correction_state = Output(Bool())
|
||||
|
||||
val iccm_rd_data = Input(UInt(64.W))
|
||||
val iccm_rd_data_ecc = Input(UInt(78.W))
|
||||
|
||||
val ic_rw_addr = Output(UInt(31.W))
|
||||
val ic_tag_valid = Output(UInt(ICACHE_NUM_WAYS.W))
|
||||
val ic_wr_en = Output(UInt(ICACHE_NUM_WAYS.W))
|
||||
val ic_rd_en = Output(Bool())
|
||||
val ic_wr_data = Output(Vec(ICACHE_BANKS_WAY, UInt(71.W)))
|
||||
val ic_rd_data = Input(UInt(64.W))
|
||||
val ic_debug_rd_data = Input(UInt(71.W))
|
||||
val ictag_debug_rd_data = Input(UInt(26.W))
|
||||
val ic_debug_wr_data = Output(UInt(71.W))
|
||||
|
||||
val ic_eccerr = Input(UInt(ICACHE_BANKS_WAY.W))
|
||||
val ic_parerr = Input(UInt(ICACHE_BANKS_WAY.W))
|
||||
val ic_premux_data = Output(UInt(64.W))
|
||||
val ic_sel_premux_data = Output(Bool())
|
||||
|
||||
val ic_debug_addr = Output(UInt((ICACHE_INDEX_HI-2).W))
|
||||
val ic_debug_rd_en = Output(Bool())
|
||||
val ic_debug_wr_en = Output(Bool())
|
||||
val ic_debug_tag_array = Output(Bool())
|
||||
val ic_debug_way = Output(UInt(ICACHE_NUM_WAYS.W))
|
||||
val ic_rd_hit = Input(UInt(ICACHE_NUM_WAYS.W))
|
||||
val ic_tag_perr = Input(Bool())
|
||||
|
||||
// AXI Signals
|
||||
val lsu_axi_awvalid = Output(Bool())
|
||||
val lsu_axi_awready = Input(Bool())
|
||||
val lsu_axi_awid = Output(UInt(LSU_BUS_TAG.W))
|
||||
val lsu_axi_awaddr = Output(UInt(32.W))
|
||||
val lsu_axi_awregion = Output(UInt(4.W))
|
||||
val lsu_axi_awlen = Output(UInt(8.W))
|
||||
val lsu_axi_awsize = Output(UInt(3.W))
|
||||
val lsu_axi_awburst = Output(UInt(2.W))
|
||||
val lsu_axi_awlock = Output(Bool())
|
||||
val lsu_axi_awcache = Output(UInt(4.W))
|
||||
val lsu_axi_awprot = Output(UInt(3.W))
|
||||
val lsu_axi_awqos = Output(UInt(4.W))
|
||||
val lsu_axi_wvalid = Output(Bool())
|
||||
val lsu_axi_wready = Input(Bool())
|
||||
val lsu_axi_wdata = Output(UInt(64.W))
|
||||
val lsu_axi_wstrb = Output(UInt(8.W))
|
||||
val lsu_axi_wlast = Output(Bool())
|
||||
val lsu_axi_bvalid = Input(Bool())
|
||||
val lsu_axi_bready = Output(Bool())
|
||||
val lsu_axi_bresp = Input(UInt(2.W))
|
||||
val lsu_axi_bid = Input(UInt(LSU_BUS_TAG.W))
|
||||
|
||||
|
||||
val lsu_axi_arvalid = Output(Bool())
|
||||
val lsu_axi_arready = Input(Bool())
|
||||
val lsu_axi_arid = Output(UInt(LSU_BUS_TAG.W))
|
||||
val lsu_axi_araddr = Output(UInt(32.W))
|
||||
val lsu_axi_arregion = Output(UInt(4.W))
|
||||
val lsu_axi_arlen = Output(UInt(8.W))
|
||||
val lsu_axi_arsize = Output(UInt(3.W))
|
||||
val lsu_axi_arburst = Output(UInt(2.W))
|
||||
val lsu_axi_arlock = Output(Bool())
|
||||
val lsu_axi_arcache = Output(UInt(4.W))
|
||||
val lsu_axi_arprot = Output(UInt(3.W))
|
||||
val lsu_axi_arqos = Output(UInt(4.W))
|
||||
val lsu_axi_rvalid = Input(Bool())
|
||||
val lsu_axi_rready = Output(Bool())
|
||||
val lsu_axi_rid = Input(UInt(LSU_BUS_TAG.W))
|
||||
val lsu_axi_rdata = Input(UInt(64.W))
|
||||
val lsu_axi_rresp = Input(UInt(2.W))
|
||||
val lsu_axi_rlast = Input(Bool())
|
||||
|
||||
|
||||
// AXI IFU Signals
|
||||
val ifu_axi_awvalid = Output(Bool())
|
||||
val ifu_axi_awready = Input(Bool())
|
||||
val ifu_axi_awid = Output(UInt(IFU_BUS_TAG.W))
|
||||
val ifu_axi_awaddr = Output(UInt(32.W))
|
||||
val ifu_axi_awregion = Output(UInt(4.W))
|
||||
val ifu_axi_awlen = Output(UInt(8.W))
|
||||
val ifu_axi_awsize = Output(UInt(3.W))
|
||||
val ifu_axi_awburst = Output(UInt(2.W))
|
||||
val ifu_axi_awlock = Output(Bool())
|
||||
val ifu_axi_awcache = Output(UInt(4.W))
|
||||
val ifu_axi_awprot = Output(UInt(3.W))
|
||||
val ifu_axi_awqos = Output(UInt(4.W))
|
||||
val ifu_axi_wvalid = Output(Bool())
|
||||
val ifu_axi_wready = Input(Bool())
|
||||
val ifu_axi_wdata = Output(UInt(64.W))
|
||||
val ifu_axi_wstrb = Output(UInt(8.W))
|
||||
val ifu_axi_wlast = Output(Bool())
|
||||
val ifu_axi_bvalid = Input(Bool())
|
||||
val ifu_axi_bready = Output(Bool())
|
||||
val ifu_axi_bresp = Input(UInt(2.W))
|
||||
val ifu_axi_bid = Input(UInt(IFU_BUS_TAG.W))
|
||||
val ifu_axi_arvalid = Output(Bool())
|
||||
val ifu_axi_arready = Input(Bool())
|
||||
val ifu_axi_arid = Output(UInt(IFU_BUS_TAG.W))
|
||||
val ifu_axi_araddr = Output(UInt(32.W))
|
||||
val ifu_axi_arregion = Output(UInt(4.W))
|
||||
val ifu_axi_arlen = Output(UInt(8.W))
|
||||
val ifu_axi_arsize = Output(UInt(3.W))
|
||||
val ifu_axi_arburst = Output(UInt(2.W))
|
||||
val ifu_axi_arlock = Output(Bool())
|
||||
val ifu_axi_arcache = Output(UInt(4.W))
|
||||
val ifu_axi_arprot = Output(UInt(3.W))
|
||||
val ifu_axi_arqos = Output(UInt(4.W))
|
||||
val ifu_axi_rvalid = Input(Bool())
|
||||
val ifu_axi_rready = Output(Bool())
|
||||
val ifu_axi_rid = Input(UInt(IFU_BUS_TAG.W))
|
||||
val ifu_axi_rdata = Input(UInt(64.W))
|
||||
val ifu_axi_rresp = Input(UInt(2.W))
|
||||
val ifu_axi_rlast = Input(Bool())
|
||||
|
||||
// SB AXI Signals
|
||||
val sb_axi_awvalid = Output(Bool())
|
||||
val sb_axi_awready = Input(Bool())
|
||||
val sb_axi_awid = Output(UInt(SB_BUS_TAG.W))
|
||||
val sb_axi_awaddr = Output(UInt(32.W))
|
||||
val sb_axi_awregion = Output(UInt(4.W))
|
||||
val sb_axi_awlen = Output(UInt(8.W))
|
||||
val sb_axi_awsize = Output(UInt(3.W))
|
||||
val sb_axi_awburst = Output(UInt(2.W))
|
||||
val sb_axi_awlock = Output(Bool())
|
||||
val sb_axi_awcache = Output(UInt(4.W))
|
||||
val sb_axi_awprot = Output(UInt(3.W))
|
||||
val sb_axi_awqos = Output(UInt(4.W))
|
||||
val sb_axi_wvalid = Output(Bool())
|
||||
val sb_axi_wready = Input(Bool())
|
||||
val sb_axi_wdata = Output(UInt(64.W))
|
||||
val sb_axi_wstrb = Output(UInt(8.W))
|
||||
val sb_axi_wlast = Output(Bool())
|
||||
val sb_axi_bvalid = Input(Bool())
|
||||
val sb_axi_bready = Output(Bool())
|
||||
val sb_axi_bresp = Input(UInt(2.W))
|
||||
val sb_axi_bid = Input(UInt(SB_BUS_TAG.W))
|
||||
val sb_axi_arvalid = Output(Bool())
|
||||
val sb_axi_arready = Input(Bool())
|
||||
val sb_axi_arid = Output(UInt(SB_BUS_TAG.W))
|
||||
val sb_axi_araddr = Output(UInt(32.W))
|
||||
val sb_axi_arregion = Output(UInt(4.W))
|
||||
val sb_axi_arlen = Output(UInt(8.W))
|
||||
val sb_axi_arsize = Output(UInt(3.W))
|
||||
val sb_axi_arburst = Output(UInt(2.W))
|
||||
val sb_axi_arlock = Output(Bool())
|
||||
val sb_axi_arcache = Output(UInt(4.W))
|
||||
val sb_axi_arprot = Output(UInt(3.W))
|
||||
val sb_axi_arqos = Output(UInt(4.W))
|
||||
val sb_axi_rvalid = Input(Bool())
|
||||
val sb_axi_rready = Output(Bool())
|
||||
val sb_axi_rid = Input(UInt(SB_BUS_TAG.W))
|
||||
val sb_axi_rdata = Input(UInt(64.W))
|
||||
val sb_axi_rresp = Input(UInt(2.W))
|
||||
val sb_axi_rlast = Input(Bool())
|
||||
// DMA signals
|
||||
val dma_axi_awvalid = Input(Bool())
|
||||
val dma_axi_awready = Output(Bool())
|
||||
val dma_axi_awid = Input(UInt(DMA_BUS_TAG.W))
|
||||
val dma_axi_awaddr = Input(UInt(32.W))
|
||||
val dma_axi_awsize = Input(UInt(3.W))
|
||||
val dma_axi_awprot = Input(UInt(3.W))
|
||||
val dma_axi_awlen = Input(UInt(8.W))
|
||||
val dma_axi_awburst = Input(UInt(2.W))
|
||||
val dma_axi_wvalid = Input(Bool())
|
||||
val dma_axi_wready = Output(Bool())
|
||||
val dma_axi_wdata = Input(UInt(64.W))
|
||||
val dma_axi_wstrb = Input(UInt(8.W))
|
||||
val dma_axi_wlast = Input(Bool())
|
||||
val dma_axi_bvalid = Output(Bool())
|
||||
val dma_axi_bready = Input(Bool())
|
||||
val dma_axi_bresp = Output(UInt(2.W))
|
||||
val dma_axi_bid = Output(UInt(DMA_BUS_TAG.W))
|
||||
|
||||
// AXI Read Channels
|
||||
val dma_axi_arvalid = Input(Bool())
|
||||
val dma_axi_arready = Output(Bool())
|
||||
val dma_axi_arid = Input(UInt(DMA_BUS_TAG.W))
|
||||
|
||||
val dma_axi_araddr = Input(UInt(32.W))
|
||||
val dma_axi_arsize = Input(UInt(3.W))
|
||||
|
||||
val dma_axi_arprot = Input(UInt(3.W))
|
||||
val dma_axi_arlen = Input(UInt(8.W))
|
||||
val dma_axi_arburst = Input(UInt(2.W))
|
||||
val dma_axi_rvalid = Output(Bool())
|
||||
val dma_axi_rready = Input(Bool())
|
||||
|
||||
val dma_axi_rid = Output(UInt(DMA_BUS_TAG.W))
|
||||
val dma_axi_rdata = Output(UInt(64.W))
|
||||
val dma_axi_rresp = Output(UInt(2.W))
|
||||
val dma_axi_rlast = Output(Bool())
|
||||
|
||||
// AHB Lite Bus
|
||||
val haddr = Output(UInt(32.W))
|
||||
val hburst = Output(UInt(3.W))
|
||||
val hmastlock = Output(Bool())
|
||||
val hprot = Output(UInt(4.W))
|
||||
val hsize = Output(UInt(3.W))
|
||||
val htrans = Output(UInt(2.W))
|
||||
val hwrite = Output(Bool())
|
||||
val hrdata = Input(UInt(64.W))
|
||||
val hready = Input(Bool())
|
||||
val hresp = Input(Bool())
|
||||
|
||||
// AHB Master
|
||||
val lsu_haddr = Output(UInt(32.W))
|
||||
val lsu_hburst = Output(UInt(3.W))
|
||||
val lsu_hmastlock = Output(Bool())
|
||||
val lsu_hprot = Output(UInt(4.W))
|
||||
val lsu_hsize = Output(UInt(3.W))
|
||||
val lsu_htrans = Output(UInt(2.W))
|
||||
val lsu_hwrite = Output(Bool())
|
||||
val lsu_hwdata = Output(UInt(64.W))
|
||||
val lsu_hrdata = Input(UInt(64.W))
|
||||
val lsu_hready = Input(Bool())
|
||||
val lsu_hresp = Input(Bool())
|
||||
|
||||
// System Bus Debug Master
|
||||
val sb_haddr = Output(UInt(32.W))
|
||||
val sb_hburst = Output(UInt(3.W))
|
||||
val sb_hmastlock = Output(Bool())
|
||||
val sb_hprot = Output(UInt(4.W))
|
||||
val sb_hsize = Output(UInt(3.W))
|
||||
val sb_htrans = Output(UInt(2.W))
|
||||
val sb_hwrite = Output(Bool())
|
||||
val sb_hwdata = Output(UInt(64.W))
|
||||
val sb_hrdata = Input(UInt(64.W))
|
||||
val sb_hready = Input(Bool())
|
||||
val sb_hresp = Input(Bool())
|
||||
|
||||
// DMA slave
|
||||
val dma_hsel = Input(Bool())
|
||||
val dma_haddr = Input(UInt(32.W))
|
||||
val dma_hburst = Input(UInt(3.W))
|
||||
val dma_hmastlock = Input(Bool())
|
||||
val dma_hprot = Input(UInt(4.W))
|
||||
val dma_hsize = Input(UInt(3.W))
|
||||
val dma_htrans = Input(UInt(2.W))
|
||||
val dma_hwrite = Input(Bool())
|
||||
val dma_hwdata = Input(UInt(64.W))
|
||||
val dma_hreadyin = Input(Bool())
|
||||
val dma_hrdata = Output(UInt(64.W))
|
||||
val dma_hreadyout = Output(Bool())
|
||||
val dma_hresp = Output(Bool())
|
||||
val lsu_bus_clk_en = Input(Bool())
|
||||
val ifu_bus_clk_en = Input(Bool())
|
||||
val dbg_bus_clk_en = Input(Bool())
|
||||
val dma_bus_clk_en = Input(Bool())
|
||||
val dmi_reg_en = Input(Bool())
|
||||
val dmi_reg_addr = Input(UInt(7.W))
|
||||
val dmi_reg_wr_en = Input(Bool())
|
||||
val dmi_reg_wdata = Input(UInt(32.W))
|
||||
val dmi_reg_rdata = Output(UInt(32.W))
|
||||
val dmi_hard_reset = Input(Bool())
|
||||
val extintsrc_req = Input(UInt(PIC_TOTAL_INT.W))
|
||||
val timer_int = Input(Bool())
|
||||
val soft_int = Input(Bool())
|
||||
val scan_mode = Input(Bool())
|
||||
}
|
||||
class el2_swerv extends Module with RequireAsyncReset with el2_lib {
|
||||
val io = IO (new Bundle{
|
||||
val dbg_rst_l = Input(Bool())
|
||||
val rst_vec = Input(UInt(31.W))
|
||||
val nmi_int = Input(Bool())
|
||||
val nmi_vec = Input(UInt(31.W))
|
||||
val core_rst_l = Output(AsyncReset())
|
||||
val trace_rv_i_insn_ip = Output(UInt(32.W))
|
||||
val trace_rv_i_address_ip = Output(UInt(32.W))
|
||||
val trace_rv_i_valid_ip = Output(UInt(2.W))
|
||||
val trace_rv_i_exception_ip = Output(UInt(2.W))
|
||||
val trace_rv_i_ecause_ip = Output(UInt(5.W))
|
||||
val trace_rv_i_interrupt_ip = Output(UInt(2.W))
|
||||
val trace_rv_i_tval_ip = Output(UInt(32.W))
|
||||
val dccm_clk_override = Output(Bool())
|
||||
val icm_clk_override = Output(Bool())
|
||||
val dec_tlu_core_ecc_disable = Output(Bool())
|
||||
val i_cpu_halt_req = Input(Bool())
|
||||
val i_cpu_run_req = Input(Bool())
|
||||
val o_cpu_halt_ack = Output(Bool())
|
||||
val o_cpu_halt_status = Output(Bool())
|
||||
val o_cpu_run_ack = Output(Bool())
|
||||
val o_debug_mode_status = Output(Bool())
|
||||
val core_id = Input(UInt(28.W))
|
||||
val mpc_debug_halt_req = Input(Bool())
|
||||
val mpc_debug_run_req = Input(Bool())
|
||||
val mpc_reset_run_req = Input(Bool())
|
||||
val mpc_debug_halt_ack = Output(Bool())
|
||||
val mpc_debug_run_ack = Output(Bool())
|
||||
val debug_brkpt_status = Output(Bool())
|
||||
val dec_tlu_perfcnt0 = Output(Bool())
|
||||
val dec_tlu_perfcnt1 = Output(Bool())
|
||||
val dec_tlu_perfcnt2 = Output(Bool())
|
||||
val dec_tlu_perfcnt3 = Output(Bool())
|
||||
val dccm_wren = Output(Bool())
|
||||
val dccm_rden = Output(Bool())
|
||||
val dccm_wr_addr_lo = Output(UInt(DCCM_BITS.W))
|
||||
val dccm_wr_addr_hi = Output(UInt(DCCM_BITS.W))
|
||||
val dccm_rd_addr_lo = Output(UInt(DCCM_BITS.W))
|
||||
val dccm_rd_addr_hi = Output(UInt(DCCM_BITS.W))
|
||||
|
||||
val dccm_wr_data_lo = Output(UInt(DCCM_FDATA_WIDTH.W))
|
||||
val dccm_wr_data_hi = Output(UInt(DCCM_FDATA_WIDTH.W))
|
||||
val dccm_rd_data_lo = Input(UInt(DCCM_FDATA_WIDTH.W))
|
||||
val dccm_rd_data_hi = Input(UInt(DCCM_FDATA_WIDTH.W))
|
||||
|
||||
val iccm_rw_addr = Output(UInt(ICCM_BITS.W))
|
||||
val iccm_wren = Output(Bool())
|
||||
val iccm_rden = Output(Bool())
|
||||
val iccm_wr_size = Output(UInt(3.W))
|
||||
val iccm_wr_data = Output(UInt(78.W))
|
||||
val iccm_buf_correct_ecc = Output(Bool())
|
||||
val iccm_correction_state = Output(Bool())
|
||||
|
||||
val iccm_rd_data = Input(UInt(64.W))
|
||||
val iccm_rd_data_ecc = Input(UInt(78.W))
|
||||
|
||||
val ic_rw_addr = Output(UInt(31.W))
|
||||
val ic_tag_valid = Output(UInt(ICACHE_NUM_WAYS.W))
|
||||
val ic_wr_en = Output(UInt(ICACHE_NUM_WAYS.W))
|
||||
val ic_rd_en = Output(Bool())
|
||||
val ic_wr_data = Output(Vec(ICACHE_BANKS_WAY, UInt(71.W)))
|
||||
val ic_rd_data = Input(UInt(64.W))
|
||||
val ic_debug_rd_data = Input(UInt(71.W))
|
||||
val ictag_debug_rd_data = Input(UInt(26.W))
|
||||
val ic_debug_wr_data = Output(UInt(71.W))
|
||||
|
||||
val ic_eccerr = Input(UInt(ICACHE_BANKS_WAY.W))
|
||||
val ic_parerr = Input(UInt(ICACHE_BANKS_WAY.W))
|
||||
val ic_premux_data = Output(UInt(64.W))
|
||||
val ic_sel_premux_data = Output(Bool())
|
||||
|
||||
val ic_debug_addr = Output(UInt((ICACHE_INDEX_HI-2).W))
|
||||
val ic_debug_rd_en = Output(Bool())
|
||||
val ic_debug_wr_en = Output(Bool())
|
||||
val ic_debug_tag_array = Output(Bool())
|
||||
val ic_debug_way = Output(UInt(ICACHE_NUM_WAYS.W))
|
||||
val ic_rd_hit = Input(UInt(ICACHE_NUM_WAYS.W))
|
||||
val ic_tag_perr = Input(Bool())
|
||||
|
||||
// AXI Signals
|
||||
val lsu_axi_awvalid = Output(Bool())
|
||||
val lsu_axi_awready = Input(Bool())
|
||||
val lsu_axi_awid = Output(UInt(LSU_BUS_TAG.W))
|
||||
val lsu_axi_awaddr = Output(UInt(32.W))
|
||||
val lsu_axi_awregion = Output(UInt(4.W))
|
||||
val lsu_axi_awlen = Output(UInt(8.W))
|
||||
val lsu_axi_awsize = Output(UInt(3.W))
|
||||
val lsu_axi_awburst = Output(UInt(2.W))
|
||||
val lsu_axi_awlock = Output(Bool())
|
||||
val lsu_axi_awcache = Output(UInt(4.W))
|
||||
val lsu_axi_awprot = Output(UInt(3.W))
|
||||
val lsu_axi_awqos = Output(UInt(4.W))
|
||||
val lsu_axi_wvalid = Output(Bool())
|
||||
val lsu_axi_wready = Input(Bool())
|
||||
val lsu_axi_wdata = Output(UInt(64.W))
|
||||
val lsu_axi_wstrb = Output(UInt(8.W))
|
||||
val lsu_axi_wlast = Output(Bool())
|
||||
val lsu_axi_bvalid = Input(Bool())
|
||||
val lsu_axi_bready = Output(Bool())
|
||||
val lsu_axi_bresp = Input(UInt(2.W))
|
||||
val lsu_axi_bid = Input(UInt(LSU_BUS_TAG.W))
|
||||
|
||||
|
||||
val lsu_axi_arvalid = Output(Bool())
|
||||
val lsu_axi_arready = Input(Bool())
|
||||
val lsu_axi_arid = Output(UInt(LSU_BUS_TAG.W))
|
||||
val lsu_axi_araddr = Output(UInt(32.W))
|
||||
val lsu_axi_arregion = Output(UInt(4.W))
|
||||
val lsu_axi_arlen = Output(UInt(8.W))
|
||||
val lsu_axi_arsize = Output(UInt(3.W))
|
||||
val lsu_axi_arburst = Output(UInt(2.W))
|
||||
val lsu_axi_arlock = Output(Bool())
|
||||
val lsu_axi_arcache = Output(UInt(4.W))
|
||||
val lsu_axi_arprot = Output(UInt(3.W))
|
||||
val lsu_axi_arqos = Output(UInt(4.W))
|
||||
val lsu_axi_rvalid = Input(Bool())
|
||||
val lsu_axi_rready = Output(Bool())
|
||||
val lsu_axi_rid = Input(UInt(LSU_BUS_TAG.W))
|
||||
val lsu_axi_rdata = Input(UInt(64.W))
|
||||
val lsu_axi_rresp = Input(UInt(2.W))
|
||||
val lsu_axi_rlast = Input(Bool())
|
||||
|
||||
|
||||
// AXI IFU Signals
|
||||
val ifu_axi_awvalid = Output(Bool())
|
||||
val ifu_axi_awready = Input(Bool())
|
||||
val ifu_axi_awid = Output(UInt(IFU_BUS_TAG.W))
|
||||
val ifu_axi_awaddr = Output(UInt(32.W))
|
||||
val ifu_axi_awregion = Output(UInt(4.W))
|
||||
val ifu_axi_awlen = Output(UInt(8.W))
|
||||
val ifu_axi_awsize = Output(UInt(3.W))
|
||||
val ifu_axi_awburst = Output(UInt(2.W))
|
||||
val ifu_axi_awlock = Output(Bool())
|
||||
val ifu_axi_awcache = Output(UInt(4.W))
|
||||
val ifu_axi_awprot = Output(UInt(3.W))
|
||||
val ifu_axi_awqos = Output(UInt(4.W))
|
||||
val ifu_axi_wvalid = Output(Bool())
|
||||
val ifu_axi_wready = Output(Bool())
|
||||
val ifu_axi_wdata = Output(UInt(64.W))
|
||||
val ifu_axi_wstrb = Output(UInt(8.W))
|
||||
val ifu_axi_wlast = Output(Bool())
|
||||
val ifu_axi_bvalid = Input(Bool())
|
||||
val ifu_axi_bready = Output(Bool())
|
||||
val ifu_axi_bresp = Input(UInt(2.W))
|
||||
val ifu_axi_bid = Input(UInt(IFU_BUS_TAG.W))
|
||||
val ifu_axi_arvalid = Output(Bool())
|
||||
val ifu_axi_arready = Input(Bool())
|
||||
val ifu_axi_arid = Output(UInt(IFU_BUS_TAG.W))
|
||||
val ifu_axi_araddr = Output(UInt(32.W))
|
||||
val ifu_axi_arregion = Output(UInt(4.W))
|
||||
val ifu_axi_arlen = Output(UInt(8.W))
|
||||
val ifu_axi_arsize = Output(UInt(3.W))
|
||||
val ifu_axi_arburst = Output(UInt(2.W))
|
||||
val ifu_axi_arlock = Output(Bool())
|
||||
val ifu_axi_arcache = Output(UInt(4.W))
|
||||
val ifu_axi_arprot = Output(UInt(3.W))
|
||||
val ifu_axi_arqos = Output(UInt(4.W))
|
||||
val ifu_axi_rvalid = Input(Bool())
|
||||
val ifu_axi_rready = Output(Bool())
|
||||
val ifu_axi_rid = Input(UInt(IFU_BUS_TAG.W))
|
||||
val ifu_axi_rdata = Input(UInt(64.W))
|
||||
val ifu_axi_rresp = Input(UInt(2.W))
|
||||
val ifu_axi_rlast = Input(Bool())
|
||||
|
||||
// SB AXI Signals
|
||||
val sb_axi_awvalid = Output(Bool())
|
||||
val sb_axi_awready = Input(Bool())
|
||||
val sb_axi_awid = Output(UInt(SB_BUS_TAG.W))
|
||||
val sb_axi_awaddr = Output(UInt(32.W))
|
||||
val sb_axi_awregion = Output(UInt(4.W))
|
||||
val sb_axi_awlen = Output(UInt(8.W))
|
||||
val sb_axi_awsize = Output(UInt(3.W))
|
||||
val sb_axi_awburst = Output(UInt(2.W))
|
||||
val sb_axi_awlock = Output(Bool())
|
||||
val sb_axi_awcache = Output(UInt(4.W))
|
||||
val sb_axi_awprot = Output(UInt(3.W))
|
||||
val sb_axi_awqos = Output(UInt(4.W))
|
||||
val sb_axi_wvalid = Output(Bool())
|
||||
val sb_axi_wready = Input(Bool())
|
||||
val sb_axi_wdata = Output(UInt(64.W))
|
||||
val sb_axi_wstrb = Output(UInt(8.W))
|
||||
val sb_axi_wlast = Output(Bool())
|
||||
val sb_axi_bvalid = Input(Bool())
|
||||
val sb_axi_bready = Output(Bool())
|
||||
val sb_axi_bresp = Input(UInt(2.W))
|
||||
val sb_axi_bid = Input(UInt(SB_BUS_TAG.W))
|
||||
val sb_axi_arvalid = Output(Bool())
|
||||
val sb_axi_arready = Input(Bool())
|
||||
val sb_axi_arid = Output(UInt(SB_BUS_TAG.W))
|
||||
val sb_axi_araddr = Output(UInt(32.W))
|
||||
val sb_axi_arregion = Output(UInt(4.W))
|
||||
val sb_axi_arlen = Output(UInt(8.W))
|
||||
val sb_axi_arsize = Output(UInt(3.W))
|
||||
val sb_axi_arburst = Output(UInt(2.W))
|
||||
val sb_axi_arlock = Output(Bool())
|
||||
val sb_axi_arcache = Output(UInt(4.W))
|
||||
val sb_axi_arprot = Output(UInt(3.W))
|
||||
val sb_axi_arqos = Output(UInt(4.W))
|
||||
val sb_axi_rvalid = Input(Bool())
|
||||
val sb_axi_rready = Output(Bool())
|
||||
val sb_axi_rid = Input(UInt(SB_BUS_TAG.W))
|
||||
val sb_axi_rdata = Input(UInt(64.W))
|
||||
val sb_axi_rresp = Input(UInt(2.W))
|
||||
val sb_axi_rlast = Input(Bool())
|
||||
// DMA signals
|
||||
val dma_axi_awvalid = Input(Bool())
|
||||
val dma_axi_awready = Output(Bool())
|
||||
val dma_axi_awid = Input(UInt(DMA_BUS_TAG.W))
|
||||
val dma_axi_awaddr = Input(UInt(32.W))
|
||||
val dma_axi_awsize = Input(UInt(3.W))
|
||||
val dma_axi_awprot = Input(UInt(3.W))
|
||||
val dma_axi_awlen = Input(UInt(8.W))
|
||||
val dma_axi_awburst = Input(UInt(2.W))
|
||||
val dma_axi_wvalid = Input(Bool())
|
||||
val dma_axi_wready = Output(Bool())
|
||||
val dma_axi_wdata = Input(UInt(64.W))
|
||||
val dma_axi_wstrb = Input(UInt(8.W))
|
||||
val dma_axi_wlast = Input(Bool())
|
||||
val dma_axi_bvalid = Output(Bool())
|
||||
val dma_axi_bready = Input(Bool())
|
||||
val dma_axi_bresp = Output(UInt(2.W))
|
||||
val dma_axi_bid = Output(UInt(DMA_BUS_TAG.W))
|
||||
|
||||
// AXI Read Channels
|
||||
val dma_axi_arvalid = Input(Bool())
|
||||
val dma_axi_arready = Output(Bool())
|
||||
val dma_axi_arid = Input(UInt(DMA_BUS_TAG.W))
|
||||
|
||||
val dma_axi_araddr = Input(UInt(32.W))
|
||||
val dma_axi_arsize = Input(UInt(3.W))
|
||||
|
||||
val dma_axi_arprot = Input(UInt(3.W))
|
||||
val dma_axi_arlen = Input(UInt(8.W))
|
||||
val dma_axi_arburst = Input(UInt(2.W))
|
||||
val dma_axi_rvalid = Output(Bool())
|
||||
val dma_axi_rready = Input(Bool())
|
||||
|
||||
val dma_axi_rid = Output(UInt(DMA_BUS_TAG.W))
|
||||
val dma_axi_rdata = Output(UInt(64.W))
|
||||
val dma_axi_rresp = Output(UInt(2.W))
|
||||
val dma_axi_rlast = Output(Bool())
|
||||
|
||||
// AHB Lite Bus
|
||||
val haddr = Output(UInt(32.W))
|
||||
val hburst = Output(UInt(3.W))
|
||||
val hmastlock = Output(Bool())
|
||||
val hprot = Output(UInt(4.W))
|
||||
val hsize = Output(UInt(3.W))
|
||||
val htrans = Output(UInt(2.W))
|
||||
val hwrite = Output(Bool())
|
||||
val hrdata = Input(UInt(64.W))
|
||||
val hready = Input(Bool())
|
||||
val hresp = Input(Bool())
|
||||
|
||||
// AHB Master
|
||||
val lsu_haddr = Output(UInt(32.W))
|
||||
val lsu_hburst = Output(UInt(3.W))
|
||||
val lsu_hmastlock = Output(Bool())
|
||||
val lsu_hprot = Output(UInt(4.W))
|
||||
val lsu_hsize = Output(UInt(3.W))
|
||||
val lsu_htrans = Output(UInt(2.W))
|
||||
val lsu_hwrite = Output(Bool())
|
||||
val lsu_hwdata = Output(UInt(64.W))
|
||||
val lsu_hrdata = Input(UInt(64.W))
|
||||
val lsu_hready = Input(Bool())
|
||||
val lsu_hresp = Input(Bool())
|
||||
|
||||
// System Bus Debug Master
|
||||
val sb_haddr = Output(UInt(32.W))
|
||||
val sb_hburst = Output(UInt(3.W))
|
||||
val sb_hmastlock = Output(Bool())
|
||||
val sb_hprot = Output(UInt(4.W))
|
||||
val sb_hsize = Output(UInt(3.W))
|
||||
val sb_htrans = Output(UInt(2.W))
|
||||
val sb_hwrite = Output(Bool())
|
||||
val sb_hwdata = Output(UInt(64.W))
|
||||
val sb_hrdata = Input(UInt(64.W))
|
||||
val sb_hready = Input(Bool())
|
||||
val sb_hresp = Input(Bool())
|
||||
|
||||
// DMA slave
|
||||
val dma_hsel = Input(Bool())
|
||||
val dma_haddr = Input(UInt(32.W))
|
||||
val dma_hburst = Input(UInt(3.W))
|
||||
val dma_hmastlock = Input(Bool())
|
||||
val dma_hprot = Input(UInt(4.W))
|
||||
val dma_hsize = Input(UInt(3.W))
|
||||
val dma_htrans = Input(UInt(2.W))
|
||||
val dma_hwrite = Input(Bool())
|
||||
val dma_hwdata = Input(UInt(64.W))
|
||||
val dma_hreadyin = Input(Bool())
|
||||
val dma_hrdata = Output(UInt(64.W))
|
||||
val dma_hreadyout = Output(Bool())
|
||||
val dma_hresp = Output(Bool())
|
||||
val lsu_bus_clk_en = Input(Bool())
|
||||
val ifu_bus_clk_en = Input(Bool())
|
||||
val dbg_bus_clk_en = Input(Bool())
|
||||
val dma_bus_clk_en = Input(Bool())
|
||||
val dmi_reg_en = Input(Bool())
|
||||
val dmi_reg_addr = Input(UInt(7.W))
|
||||
val dmi_reg_wr_en = Input(Bool())
|
||||
val dmi_reg_wdata = Input(UInt(32.W))
|
||||
val dmi_reg_rdata = Output(UInt(32.W))
|
||||
val dmi_hard_reset = Input(Bool())
|
||||
val extintsrc_req = Input(UInt(PIC_TOTAL_INT.W))
|
||||
val timer_int = Input(Bool())
|
||||
val soft_int = Input(Bool())
|
||||
val scan_mode = Input(Bool())
|
||||
})
|
||||
|
||||
|
||||
val io = IO (new el2_swerv_bundle)
|
||||
val ifu = Module(new el2_ifu)
|
||||
val dec = Module(new el2_dec)
|
||||
val dbg = Module(new el2_dbg)
|
||||
val exu = Module(new el2_exu)
|
||||
val lsu = Module(new el2_lsu)
|
||||
val pic_ctl_inst = Module(new el2_pic_ctrl)
|
||||
val pic_ctrl_inst = Module(new el2_pic_ctrl)
|
||||
val dma_ctrl = Module(new el2_dma_ctrl)
|
||||
//val lsu_axi4_to_ahb = Module(new axi4_to_ahb)
|
||||
//val ifu_axi4_to_ahb = Module(new axi4_to_ahb)
|
||||
//val sb_axi4_to_ahb = Module(new axi4_to_ahb)
|
||||
|
||||
io.core_rst_l := (!(reset.asBool() & (dbg.io.dbg_core_rst_l.asBool() | io.scan_mode))).asAsyncReset()
|
||||
io.core_rst_l := (reset.asBool() & (dbg.io.dbg_core_rst_l.asBool() | io.scan_mode)).asAsyncReset()
|
||||
val active_state = (!dec.io.dec_pause_state_cg | dec.io.dec_tlu_flush_lower_r) | dec.io.dec_tlu_misc_clk_override
|
||||
val free_clk = rvclkhdr(clock, true.B, io.scan_mode)
|
||||
val active_clk = rvclkhdr(clock, active_state, io.scan_mode)
|
||||
|
|
@ -477,11 +475,11 @@ class el2_swerv extends Module with RequireAsyncReset with el2_lib {
|
|||
dec.io.ifu_i0_pc := ifu.io.ifu_i0_pc
|
||||
dec.io.ifu_i0_pc4 := ifu.io.ifu_i0_pc4
|
||||
dec.io.exu_i0_pc_x := exu.io.exu_i0_pc_x
|
||||
dec.io.mexintpend := pic_ctl_inst.io.mexintpend
|
||||
dec.io.mexintpend := pic_ctrl_inst.io.mexintpend
|
||||
dec.io.soft_int := io.soft_int
|
||||
dec.io.pic_claimid := pic_ctl_inst.io.claimid
|
||||
dec.io.pic_pl := pic_ctl_inst.io.pl
|
||||
dec.io.mhwakeup := pic_ctl_inst.io.mhwakeup
|
||||
dec.io.pic_claimid := pic_ctrl_inst.io.claimid
|
||||
dec.io.pic_pl := pic_ctrl_inst.io.pl
|
||||
dec.io.mhwakeup := pic_ctrl_inst.io.mhwakeup
|
||||
dec.io.ifu_ic_debug_rd_data := ifu.io.ifu_ic_debug_rd_data
|
||||
dec.io.ifu_ic_debug_rd_data_valid := ifu.io.ifu_ic_debug_rd_data_valid
|
||||
dec.io.dbg_halt_req := dbg.io.dbg_halt_req
|
||||
|
|
@ -597,7 +595,7 @@ class el2_swerv extends Module with RequireAsyncReset with el2_lib {
|
|||
dbg.io.sb_axi_rdata := io.sb_axi_rdata
|
||||
dbg.io.sb_axi_rresp := io.sb_axi_rresp
|
||||
dbg.io.dbg_bus_clk_en := io.dbg_bus_clk_en
|
||||
dbg.io.dbg_rst_l := io.dbg_rst_l
|
||||
dbg.io.dbg_rst_l := io.dbg_rst_l.asBool()
|
||||
dbg.io.clk_override := dec.io.dec_tlu_misc_clk_override
|
||||
dbg.io.scan_mode := io.scan_mode
|
||||
|
||||
|
|
@ -642,21 +640,21 @@ class el2_swerv extends Module with RequireAsyncReset with el2_lib {
|
|||
|
||||
|
||||
// PIC lets go
|
||||
pic_ctl_inst.io.scan_mode := io.scan_mode
|
||||
pic_ctl_inst.reset := io.core_rst_l
|
||||
pic_ctl_inst.io.free_clk := free_clk
|
||||
pic_ctl_inst.io.active_clk := active_clk
|
||||
pic_ctl_inst.io.clk_override := dec.io.dec_tlu_pic_clk_override
|
||||
pic_ctl_inst.io.extintsrc_req := io.extintsrc_req
|
||||
pic_ctl_inst.io.picm_rdaddr := lsu.io.picm_rdaddr
|
||||
pic_ctl_inst.io.picm_wraddr := lsu.io.picm_wraddr
|
||||
pic_ctl_inst.io.picm_wr_data := lsu.io.picm_wr_data
|
||||
pic_ctl_inst.io.picm_wren := lsu.io.picm_wren
|
||||
pic_ctl_inst.io.picm_rden := lsu.io.picm_rden
|
||||
pic_ctl_inst.io.picm_mken := lsu.io.picm_mken
|
||||
pic_ctl_inst.io.meicurpl := dec.io.dec_tlu_meicurpl
|
||||
pic_ctl_inst.io.meipt := dec.io.dec_tlu_meipt
|
||||
lsu.io.picm_rd_data := pic_ctl_inst.io.picm_rd_data
|
||||
pic_ctrl_inst.io.scan_mode := io.scan_mode
|
||||
pic_ctrl_inst.reset := io.core_rst_l
|
||||
pic_ctrl_inst.io.free_clk := free_clk
|
||||
pic_ctrl_inst.io.active_clk := active_clk
|
||||
pic_ctrl_inst.io.clk_override := dec.io.dec_tlu_pic_clk_override
|
||||
pic_ctrl_inst.io.extintsrc_req := io.extintsrc_req
|
||||
pic_ctrl_inst.io.picm_rdaddr := lsu.io.picm_rdaddr
|
||||
pic_ctrl_inst.io.picm_wraddr := lsu.io.picm_wraddr
|
||||
pic_ctrl_inst.io.picm_wr_data := lsu.io.picm_wr_data
|
||||
pic_ctrl_inst.io.picm_wren := lsu.io.picm_wren
|
||||
pic_ctrl_inst.io.picm_rden := lsu.io.picm_rden
|
||||
pic_ctrl_inst.io.picm_mken := lsu.io.picm_mken
|
||||
pic_ctrl_inst.io.meicurpl := dec.io.dec_tlu_meicurpl
|
||||
pic_ctrl_inst.io.meipt := dec.io.dec_tlu_meipt
|
||||
lsu.io.picm_rd_data := pic_ctrl_inst.io.picm_rd_data
|
||||
|
||||
|
||||
|
||||
|
|
@ -853,7 +851,7 @@ class el2_swerv extends Module with RequireAsyncReset with el2_lib {
|
|||
io.dma_hreadyout := 0.U
|
||||
io.dma_hresp := 0.U
|
||||
|
||||
io.ifu_axi_wready := 0.U
|
||||
//io.ifu_axi_wready := 0.U
|
||||
|
||||
io.dma_hresp := 0.U //dbg.io.dma_hresp
|
||||
|
||||
|
|
@ -866,4 +864,3 @@ object SWERV extends App {
|
|||
}
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
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Reference in New Issue