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Packets updated with Valid

This commit is contained in:
​Laraib Khan 2020-11-23 15:42:08 +05:00
parent 37641a8a14
commit 89e70f46c8
24 changed files with 194621 additions and 344 deletions
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0
dmi_wrapper.sv Normal file
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23
dmi_wrapper_module.anno.json Normal file
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@ -0,0 +1,23 @@
[
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"dmi_wrapper_module.dmi_wrapper",
"resourceId":"/vsrc/dmi_wrapper.sv"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"dmi_wrapper_module"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

59
dmi_wrapper_module.fir Normal file
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@ -0,0 +1,59 @@
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit dmi_wrapper_module :
extmodule dmi_wrapper :
input trst_n : UInt<1>
input tck : Clock
input tms : UInt<1>
input tdi : UInt<1>
output tdo : UInt<1>
output tdoEnable : UInt<1>
input core_rst_n : AsyncReset
input core_clk : Clock
input jtag_id : UInt<31>
input rd_data : UInt<32>
output reg_wr_data : UInt<32>
output reg_wr_addr : UInt<7>
output reg_en : UInt<1>
output reg_wr_en : UInt<1>
output dmi_hard_reset : UInt<1>
defname = dmi_wrapper
module dmi_wrapper_module :
input clock : Clock
input reset : UInt<1>
output io : {flip trst_n : UInt<1>, flip tck : Clock, flip tms : UInt<1>, flip tdi : UInt<1>, tdo : UInt<1>, tdoEnable : UInt<1>, flip core_rst_n : AsyncReset, flip core_clk : Clock, flip jtag_id : UInt<32>, flip rd_data : UInt<32>, reg_wr_data : UInt<32>, reg_wr_addr : UInt<7>, reg_en : UInt<1>, reg_wr_en : UInt<1>, dmi_hard_reset : UInt<1>}
inst dwrap of dmi_wrapper @[dmi_wrapper.scala 45:21]
dwrap.dmi_hard_reset is invalid
dwrap.reg_wr_en is invalid
dwrap.reg_en is invalid
dwrap.reg_wr_addr is invalid
dwrap.reg_wr_data is invalid
dwrap.rd_data is invalid
dwrap.jtag_id is invalid
dwrap.core_clk is invalid
dwrap.core_rst_n is invalid
dwrap.tdoEnable is invalid
dwrap.tdo is invalid
dwrap.tdi is invalid
dwrap.tms is invalid
dwrap.tck is invalid
dwrap.trst_n is invalid
io.dmi_hard_reset <= dwrap.dmi_hard_reset @[dmi_wrapper.scala 46:12]
io.reg_wr_en <= dwrap.reg_wr_en @[dmi_wrapper.scala 46:12]
io.reg_en <= dwrap.reg_en @[dmi_wrapper.scala 46:12]
io.reg_wr_addr <= dwrap.reg_wr_addr @[dmi_wrapper.scala 46:12]
io.reg_wr_data <= dwrap.reg_wr_data @[dmi_wrapper.scala 46:12]
dwrap.rd_data <= io.rd_data @[dmi_wrapper.scala 46:12]
dwrap.jtag_id <= io.jtag_id @[dmi_wrapper.scala 46:12]
dwrap.core_clk <= io.core_clk @[dmi_wrapper.scala 46:12]
dwrap.core_rst_n <= io.core_rst_n @[dmi_wrapper.scala 46:12]
io.tdoEnable <= dwrap.tdoEnable @[dmi_wrapper.scala 46:12]
io.tdo <= dwrap.tdo @[dmi_wrapper.scala 46:12]
dwrap.tdi <= io.tdi @[dmi_wrapper.scala 46:12]
dwrap.tms <= io.tms @[dmi_wrapper.scala 46:12]
dwrap.tck <= io.tck @[dmi_wrapper.scala 46:12]
dwrap.trst_n <= io.trst_n @[dmi_wrapper.scala 46:12]

67
dmi_wrapper_module.v Normal file
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@ -0,0 +1,67 @@
module dmi_wrapper_module(
input clock,
input reset,
input io_trst_n,
input io_tck,
input io_tms,
input io_tdi,
output io_tdo,
output io_tdoEnable,
input io_core_rst_n,
input io_core_clk,
input [31:0] io_jtag_id,
input [31:0] io_rd_data,
output [31:0] io_reg_wr_data,
output [6:0] io_reg_wr_addr,
output io_reg_en,
output io_reg_wr_en,
output io_dmi_hard_reset
);
wire dwrap_trst_n; // @[dmi_wrapper.scala 45:21]
wire dwrap_tck; // @[dmi_wrapper.scala 45:21]
wire dwrap_tms; // @[dmi_wrapper.scala 45:21]
wire dwrap_tdi; // @[dmi_wrapper.scala 45:21]
wire dwrap_tdo; // @[dmi_wrapper.scala 45:21]
wire dwrap_tdoEnable; // @[dmi_wrapper.scala 45:21]
wire dwrap_core_rst_n; // @[dmi_wrapper.scala 45:21]
wire dwrap_core_clk; // @[dmi_wrapper.scala 45:21]
wire [30:0] dwrap_jtag_id; // @[dmi_wrapper.scala 45:21]
wire [31:0] dwrap_rd_data; // @[dmi_wrapper.scala 45:21]
wire [31:0] dwrap_reg_wr_data; // @[dmi_wrapper.scala 45:21]
wire [6:0] dwrap_reg_wr_addr; // @[dmi_wrapper.scala 45:21]
wire dwrap_reg_en; // @[dmi_wrapper.scala 45:21]
wire dwrap_reg_wr_en; // @[dmi_wrapper.scala 45:21]
wire dwrap_dmi_hard_reset; // @[dmi_wrapper.scala 45:21]
dmi_wrapper dwrap ( // @[dmi_wrapper.scala 45:21]
.trst_n(dwrap_trst_n),
.tck(dwrap_tck),
.tms(dwrap_tms),
.tdi(dwrap_tdi),
.tdo(dwrap_tdo),
.tdoEnable(dwrap_tdoEnable),
.core_rst_n(dwrap_core_rst_n),
.core_clk(dwrap_core_clk),
.jtag_id(dwrap_jtag_id),
.rd_data(dwrap_rd_data),
.reg_wr_data(dwrap_reg_wr_data),
.reg_wr_addr(dwrap_reg_wr_addr),
.reg_en(dwrap_reg_en),
.reg_wr_en(dwrap_reg_wr_en),
.dmi_hard_reset(dwrap_dmi_hard_reset)
);
assign io_tdo = dwrap_tdo; // @[dmi_wrapper.scala 46:12]
assign io_tdoEnable = dwrap_tdoEnable; // @[dmi_wrapper.scala 46:12]
assign io_reg_wr_data = dwrap_reg_wr_data; // @[dmi_wrapper.scala 46:12]
assign io_reg_wr_addr = dwrap_reg_wr_addr; // @[dmi_wrapper.scala 46:12]
assign io_reg_en = dwrap_reg_en; // @[dmi_wrapper.scala 46:12]
assign io_reg_wr_en = dwrap_reg_wr_en; // @[dmi_wrapper.scala 46:12]
assign io_dmi_hard_reset = dwrap_dmi_hard_reset; // @[dmi_wrapper.scala 46:12]
assign dwrap_trst_n = io_trst_n; // @[dmi_wrapper.scala 46:12]
assign dwrap_tck = io_tck; // @[dmi_wrapper.scala 46:12]
assign dwrap_tms = io_tms; // @[dmi_wrapper.scala 46:12]
assign dwrap_tdi = io_tdi; // @[dmi_wrapper.scala 46:12]
assign dwrap_core_rst_n = io_core_rst_n; // @[dmi_wrapper.scala 46:12]
assign dwrap_core_clk = io_core_clk; // @[dmi_wrapper.scala 46:12]
assign dwrap_jtag_id = io_jtag_id[30:0]; // @[dmi_wrapper.scala 46:12]
assign dwrap_rd_data = io_rd_data; // @[dmi_wrapper.scala 46:12]
endmodule

169
el2_mem.sv Normal file
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@ -0,0 +1,169 @@
module el2_mem #(
parameter ICACHE_BEAT_BITS,
parameter ICCM_BITS,
parameter ICACHE_NUM_WAYS,
parameter DCCM_BYTE_WIDTH,
parameter ICCM_BANK_INDEX_LO,
parameter ICACHE_BANK_BITS,
parameter DCCM_BITS,
parameter ICACHE_BEAT_ADDR_HI,
parameter ICCM_INDEX_BITS,
parameter ICCM_BANK_HI,
parameter ICACHE_BANKS_WAY,
parameter ICACHE_INDEX_HI,
parameter DCCM_NUM_BANKS,
parameter ICACHE_BANK_HI,
parameter ICACHE_BANK_LO,
parameter DCCM_ENABLE,
parameter ICACHE_TAG_LO,
parameter ICACHE_DATA_INDEX_LO,
parameter ICCM_NUM_BANKS,
parameter ICACHE_ECC,
parameter ICACHE_ENABLE,
parameter DCCM_BANK_BITS,
parameter ICCM_ENABLE,
parameter ICCM_BANK_BITS,
parameter ICACHE_TAG_DEPTH,
parameter ICACHE_WAYPACK,
parameter DCCM_SIZE,
parameter DCCM_FDATA_WIDTH,
parameter ICACHE_TAG_INDEX_LO,
parameter ICACHE_DATA_DEPTH)
(
input logic clk,
input logic rst_l,
input logic dccm_clk_override,
input logic icm_clk_override,
input logic dec_tlu_core_ecc_disable,
//DCCM ports
input logic dccm_wren,
input logic dccm_rden,
input logic [DCCM_BITS-1:0] dccm_wr_addr_lo,
input logic [DCCM_BITS-1:0] dccm_wr_addr_hi,
input logic [DCCM_BITS-1:0] dccm_rd_addr_lo,
input logic [DCCM_BITS-1:0] dccm_rd_addr_hi,
input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo,
input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi,
output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo,
output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi,
//`ifdef DCCM_ENABLE
//`endif
//ICCM ports
input logic [ICCM_BITS-1:1] iccm_rw_addr,
input logic iccm_buf_correct_ecc, // ICCM is doing a single bit error correct cycle
input logic iccm_correction_state, // ICCM is doing a single bit error correct cycle
input logic iccm_wren,
input logic iccm_rden,
input logic [2:0] iccm_wr_size,
input logic [77:0] iccm_wr_data,
output logic [63:0] iccm_rd_data,
output logic [77:0] iccm_rd_data_ecc,
// Icache and Itag Ports
input logic [31:1] ic_rw_addr,
input logic [ICACHE_NUM_WAYS-1:0] ic_tag_valid,
input logic [ICACHE_NUM_WAYS-1:0] ic_wr_en,
input logic ic_rd_en,
input logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache.
input logic ic_sel_premux_data, // Premux data sel
input logic [ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data, // Data to fill to the Icache. With ECC
input logic [70:0] ic_debug_wr_data, // Debug wr cache.
output logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
input logic [ICACHE_INDEX_HI:3] ic_debug_addr, // Read/Write addresss to the Icache.
input logic ic_debug_rd_en, // Icache debug rd
input logic ic_debug_wr_en, // Icache debug wr
input logic ic_debug_tag_array, // Debug tag array
input logic [ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr.
output logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
output logic [25:0] ictag_debug_rd_data,// Debug icache tag.
output logic [ICACHE_BANKS_WAY-1:0] ic_eccerr, // ecc error per bank
output logic [ICACHE_BANKS_WAY-1:0] ic_parerr, // parity error per bank
output logic [ICACHE_NUM_WAYS-1:0] ic_rd_hit,
output logic ic_tag_perr, // Icache Tag parity error
input logic scan_mode
);
// DCCM Instantiation
if (DCCM_ENABLE == 1) begin: Gen_dccm_enable
el2_lsu_dccm_mem #(
.DCCM_BYTE_WIDTH(DCCM_BYTE_WIDTH),
.DCCM_BITS(DCCM_BITS),
.DCCM_NUM_BANKS(DCCM_NUM_BANKS),
.DCCM_BANK_BITS(DCCM_BANK_BITS),
.DCCM_SIZE(DCCM_SIZE),
.DCCM_FDATA_WIDTH(DCCM_FDATA_WIDTH)) dccm (
.clk_override(dccm_clk_override),
.*
);
end else begin: Gen_dccm_disable
assign dccm_rd_data_lo = '0;
assign dccm_rd_data_hi = '0;
end
if ( ICACHE_ENABLE ) begin: icache
el2_ifu_ic_mem #(
.ICACHE_BEAT_BITS(ICACHE_BEAT_BITS),
.ICACHE_NUM_WAYS(ICACHE_NUM_WAYS),
.ICACHE_BANK_BITS(ICACHE_BANK_BITS),
.ICACHE_BEAT_ADDR_HI(ICACHE_BEAT_ADDR_HI),
.ICACHE_BANKS_WAY(ICACHE_BANKS_WAY),
.ICACHE_INDEX_HI(ICACHE_INDEX_HI),
.ICACHE_BANK_HI(ICACHE_BANK_HI),
.ICACHE_BANK_LO(ICACHE_BANK_LO),
.ICACHE_TAG_LO(ICACHE_TAG_LO),
.ICACHE_DATA_INDEX_LO(ICACHE_DATA_INDEX_LO),
.ICACHE_ECC(ICACHE_ECC),
.ICACHE_TAG_DEPTH(ICACHE_TAG_DEPTH),
.ICACHE_WAYPACK(ICACHE_WAYPACK),
.ICACHE_TAG_INDEX_LO(ICACHE_TAG_INDEX_LO),
.ICACHE_DATA_DEPTH(ICACHE_DATA_DEPTH)) icm (
.clk_override(icm_clk_override),
.*
);
end
else begin
assign ic_rd_hit[ICACHE_NUM_WAYS-1:0] = '0;
assign ic_tag_perr = '0 ;
assign ic_rd_data = '0 ;
assign ictag_debug_rd_data = '0 ;
end // else: !if( ICACHE_ENABLE )
if (ICCM_ENABLE) begin : iccm
el2_ifu_iccm_mem #(
.ICCM_BITS(ICCM_BITS),
.ICCM_BANK_INDEX_LO(ICCM_BANK_INDEX_LO),
.ICCM_INDEX_BITS(ICCM_INDEX_BITS),
.ICCM_BANK_HI(ICCM_BANK_HI),
.ICCM_NUM_BANKS(ICCM_NUM_BANKS),
.ICCM_BANK_BITS(ICCM_BANK_BITS)) iccm (.*,
.clk_override(icm_clk_override),
.iccm_rw_addr(iccm_rw_addr[ICCM_BITS-1:1]),
.iccm_rd_data(iccm_rd_data[63:0])
);
end
else begin
assign iccm_rd_data = '0 ;
assign iccm_rd_data_ecc = '0 ;
end
endmodule

6
el2_swerv.fir
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15
el2_swerv.v
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@ -59920,6 +59920,9 @@ initial begin
_RAND_20 = {1{`RANDOM}}; _RAND_20 = {1{`RANDOM}};
data0_reg = _RAND_20[31:0]; data0_reg = _RAND_20[31:0];
`endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE_REG_INIT
if (io_dbg_rst_l) begin
dm_temp_0 = 1'h0;
end
`endif // RANDOMIZE `endif // RANDOMIZE
end // initial end // initial
`ifdef FIRRTL_AFTER_INITIAL `ifdef FIRRTL_AFTER_INITIAL
@ -59983,11 +59986,6 @@ end // initial
end else if (dmcontrol_wren) begin end else if (dmcontrol_wren) begin
dm_temp <= _T_139; dm_temp <= _T_139;
end end
if (io_dbg_rst_l) begin
dm_temp_0 <= 1'h0;
end else if (dmcontrol_wren) begin
dm_temp_0 <= io_dmi_reg_wdata[0];
end
if (_T_29) begin if (_T_29) begin
dmstatus_havereset <= 1'h0; dmstatus_havereset <= 1'h0;
end else if (dmstatus_havereset_wren) begin end else if (dmstatus_havereset_wren) begin
@ -60163,6 +60161,13 @@ end // initial
data0_reg <= data0_din; data0_reg <= data0_din;
end end
end end
always @(posedge rvclkhdr_io_l1clk or posedge io_dbg_rst_l) begin
if (io_dbg_rst_l) begin
dm_temp_0 <= 1'h0;
end else if (dmcontrol_wren) begin
dm_temp_0 <= io_dmi_reg_wdata[0];
end
end
endmodule endmodule
module el2_exu_alu_ctl( module el2_exu_alu_ctl(
input clock, input clock,

997
el2_swerv_wrapper.anno.json Normal file
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@ -0,0 +1,997 @@
[
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_swerv_wrapper.gated_latch",
"resourceId":"/vsrc/gated_latch.v"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>selected_int_priority"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_4_2"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_4_0"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_3_4"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_3_2"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_3_0"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_2_8"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_2_6"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_2_4"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_2_2"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_2_0"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_1_16"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_1_14"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_1_12"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_1_10"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_1_8"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_1_6"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_1_4"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_1_2"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_1_0"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_0_32"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_0_30"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_0_28"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_0_26"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_0_24"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_0_22"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_0_20"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_0_18"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_0_16"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_0_14"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_0_12"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_0_10"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_0_8"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_0_6"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_0_4"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_0_2"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_0_0"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_w_prior_en_0_0"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_w_prior_en_0_1"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_w_prior_en_0_2"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_w_prior_en_0_3"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_w_prior_en_0_4"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_w_prior_en_0_5"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
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"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_4_18"
},
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"class":"firrtl.transforms.DontTouchAnnotation",
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},
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},
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"class":"firrtl.transforms.DontTouchAnnotation",
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"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_4_25"
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"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_4_29"
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"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_4_30"
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"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_4_31"
},
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"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_4_32"
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},
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"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_0"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_1"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_2"
},
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"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_3"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_4"
},
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"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_5"
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"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_6"
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"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_7"
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"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_9"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_10"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_11"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_12"
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{
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"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_13"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_14"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_15"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_16"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_17"
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{
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"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_18"
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"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_19"
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"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_20"
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{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_21"
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{
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"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_22"
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{
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"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_23"
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{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_24"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_25"
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{
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"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_26"
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{
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"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_27"
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{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_28"
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"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_29"
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{
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"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_30"
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"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_31"
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"target":"~el2_swerv_wrapper|el2_pic_ctrl>level_intpend_id_5_33"
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{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~el2_swerv_wrapper|el2_exu>i0_rs2_d"
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{
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"target":"~el2_swerv_wrapper|el2_dec_trigger>io_dec_i0_trigger_match_d"
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{
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"target":"el2_swerv_wrapper.dmi_wrapper",
"resourceId":"/vsrc/dmi_wrapper.sv"
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"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_swerv_wrapper.el2_mem",
"resourceId":"/vsrc/el2_mem.sv"
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{
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"directory":"."
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"file":"el2_swerv_wrapper"
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]

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/home/laraibkhan/Desktop/SweRV-Chislified/gated_latch.v /home/laraibkhan/Desktop/SweRV-Chislified/gated_latch.v
/home/laraibkhan/Desktop/SweRV-Chislified/dmi_wrapper.sv
/home/laraibkhan/Desktop/SweRV-Chislified/el2_mem.sv

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src/main/scala/el2_swerv.scala
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@ -7,331 +7,329 @@ import lsu._
import lib._ import lib._
import include._ import include._
import dbg._ import dbg._
class el2_swerv_bundle extends Bundle with el2_lib{
val dbg_rst_l = Input(AsyncReset())
val rst_vec = Input(UInt(31.W))
val nmi_int = Input(Bool())
val nmi_vec = Input(UInt(31.W))
val core_rst_l = Output(AsyncReset())
val trace_rv_i_insn_ip = Output(UInt(32.W))
val trace_rv_i_address_ip = Output(UInt(32.W))
val trace_rv_i_valid_ip = Output(UInt(2.W))
val trace_rv_i_exception_ip = Output(UInt(2.W))
val trace_rv_i_ecause_ip = Output(UInt(5.W))
val trace_rv_i_interrupt_ip = Output(UInt(2.W))
val trace_rv_i_tval_ip = Output(UInt(32.W))
val dccm_clk_override = Output(Bool())
val icm_clk_override = Output(Bool())
val dec_tlu_core_ecc_disable = Output(Bool())
val i_cpu_halt_req = Input(Bool())
val i_cpu_run_req = Input(Bool())
val o_cpu_halt_ack = Output(Bool())
val o_cpu_halt_status = Output(Bool())
val o_cpu_run_ack = Output(Bool())
val o_debug_mode_status = Output(Bool())
val core_id = Input(UInt(28.W))
val mpc_debug_halt_req = Input(Bool())
val mpc_debug_run_req = Input(Bool())
val mpc_reset_run_req = Input(Bool())
val mpc_debug_halt_ack = Output(Bool())
val mpc_debug_run_ack = Output(Bool())
val debug_brkpt_status = Output(Bool())
val dec_tlu_perfcnt0 = Output(Bool())
val dec_tlu_perfcnt1 = Output(Bool())
val dec_tlu_perfcnt2 = Output(Bool())
val dec_tlu_perfcnt3 = Output(Bool())
val dccm_wren = Output(Bool())
val dccm_rden = Output(Bool())
val dccm_wr_addr_lo = Output(UInt(DCCM_BITS.W))
val dccm_wr_addr_hi = Output(UInt(DCCM_BITS.W))
val dccm_rd_addr_lo = Output(UInt(DCCM_BITS.W))
val dccm_rd_addr_hi = Output(UInt(DCCM_BITS.W))
val dccm_wr_data_lo = Output(UInt(DCCM_FDATA_WIDTH.W))
val dccm_wr_data_hi = Output(UInt(DCCM_FDATA_WIDTH.W))
val dccm_rd_data_lo = Input(UInt(DCCM_FDATA_WIDTH.W))
val dccm_rd_data_hi = Input(UInt(DCCM_FDATA_WIDTH.W))
val iccm_rw_addr = Output(UInt((ICCM_BITS-1).W))
val iccm_wren = Output(Bool())
val iccm_rden = Output(Bool())
val iccm_wr_size = Output(UInt(3.W))
val iccm_wr_data = Output(UInt(78.W))
val iccm_buf_correct_ecc = Output(Bool())
val iccm_correction_state = Output(Bool())
val iccm_rd_data = Input(UInt(64.W))
val iccm_rd_data_ecc = Input(UInt(78.W))
val ic_rw_addr = Output(UInt(31.W))
val ic_tag_valid = Output(UInt(ICACHE_NUM_WAYS.W))
val ic_wr_en = Output(UInt(ICACHE_NUM_WAYS.W))
val ic_rd_en = Output(Bool())
val ic_wr_data = Output(Vec(ICACHE_BANKS_WAY, UInt(71.W)))
val ic_rd_data = Input(UInt(64.W))
val ic_debug_rd_data = Input(UInt(71.W))
val ictag_debug_rd_data = Input(UInt(26.W))
val ic_debug_wr_data = Output(UInt(71.W))
val ic_eccerr = Input(UInt(ICACHE_BANKS_WAY.W))
val ic_parerr = Input(UInt(ICACHE_BANKS_WAY.W))
val ic_premux_data = Output(UInt(64.W))
val ic_sel_premux_data = Output(Bool())
val ic_debug_addr = Output(UInt((ICACHE_INDEX_HI-2).W))
val ic_debug_rd_en = Output(Bool())
val ic_debug_wr_en = Output(Bool())
val ic_debug_tag_array = Output(Bool())
val ic_debug_way = Output(UInt(ICACHE_NUM_WAYS.W))
val ic_rd_hit = Input(UInt(ICACHE_NUM_WAYS.W))
val ic_tag_perr = Input(Bool())
// AXI Signals
val lsu_axi_awvalid = Output(Bool())
val lsu_axi_awready = Input(Bool())
val lsu_axi_awid = Output(UInt(LSU_BUS_TAG.W))
val lsu_axi_awaddr = Output(UInt(32.W))
val lsu_axi_awregion = Output(UInt(4.W))
val lsu_axi_awlen = Output(UInt(8.W))
val lsu_axi_awsize = Output(UInt(3.W))
val lsu_axi_awburst = Output(UInt(2.W))
val lsu_axi_awlock = Output(Bool())
val lsu_axi_awcache = Output(UInt(4.W))
val lsu_axi_awprot = Output(UInt(3.W))
val lsu_axi_awqos = Output(UInt(4.W))
val lsu_axi_wvalid = Output(Bool())
val lsu_axi_wready = Input(Bool())
val lsu_axi_wdata = Output(UInt(64.W))
val lsu_axi_wstrb = Output(UInt(8.W))
val lsu_axi_wlast = Output(Bool())
val lsu_axi_bvalid = Input(Bool())
val lsu_axi_bready = Output(Bool())
val lsu_axi_bresp = Input(UInt(2.W))
val lsu_axi_bid = Input(UInt(LSU_BUS_TAG.W))
val lsu_axi_arvalid = Output(Bool())
val lsu_axi_arready = Input(Bool())
val lsu_axi_arid = Output(UInt(LSU_BUS_TAG.W))
val lsu_axi_araddr = Output(UInt(32.W))
val lsu_axi_arregion = Output(UInt(4.W))
val lsu_axi_arlen = Output(UInt(8.W))
val lsu_axi_arsize = Output(UInt(3.W))
val lsu_axi_arburst = Output(UInt(2.W))
val lsu_axi_arlock = Output(Bool())
val lsu_axi_arcache = Output(UInt(4.W))
val lsu_axi_arprot = Output(UInt(3.W))
val lsu_axi_arqos = Output(UInt(4.W))
val lsu_axi_rvalid = Input(Bool())
val lsu_axi_rready = Output(Bool())
val lsu_axi_rid = Input(UInt(LSU_BUS_TAG.W))
val lsu_axi_rdata = Input(UInt(64.W))
val lsu_axi_rresp = Input(UInt(2.W))
val lsu_axi_rlast = Input(Bool())
// AXI IFU Signals
val ifu_axi_awvalid = Output(Bool())
val ifu_axi_awready = Input(Bool())
val ifu_axi_awid = Output(UInt(IFU_BUS_TAG.W))
val ifu_axi_awaddr = Output(UInt(32.W))
val ifu_axi_awregion = Output(UInt(4.W))
val ifu_axi_awlen = Output(UInt(8.W))
val ifu_axi_awsize = Output(UInt(3.W))
val ifu_axi_awburst = Output(UInt(2.W))
val ifu_axi_awlock = Output(Bool())
val ifu_axi_awcache = Output(UInt(4.W))
val ifu_axi_awprot = Output(UInt(3.W))
val ifu_axi_awqos = Output(UInt(4.W))
val ifu_axi_wvalid = Output(Bool())
val ifu_axi_wready = Input(Bool())
val ifu_axi_wdata = Output(UInt(64.W))
val ifu_axi_wstrb = Output(UInt(8.W))
val ifu_axi_wlast = Output(Bool())
val ifu_axi_bvalid = Input(Bool())
val ifu_axi_bready = Output(Bool())
val ifu_axi_bresp = Input(UInt(2.W))
val ifu_axi_bid = Input(UInt(IFU_BUS_TAG.W))
val ifu_axi_arvalid = Output(Bool())
val ifu_axi_arready = Input(Bool())
val ifu_axi_arid = Output(UInt(IFU_BUS_TAG.W))
val ifu_axi_araddr = Output(UInt(32.W))
val ifu_axi_arregion = Output(UInt(4.W))
val ifu_axi_arlen = Output(UInt(8.W))
val ifu_axi_arsize = Output(UInt(3.W))
val ifu_axi_arburst = Output(UInt(2.W))
val ifu_axi_arlock = Output(Bool())
val ifu_axi_arcache = Output(UInt(4.W))
val ifu_axi_arprot = Output(UInt(3.W))
val ifu_axi_arqos = Output(UInt(4.W))
val ifu_axi_rvalid = Input(Bool())
val ifu_axi_rready = Output(Bool())
val ifu_axi_rid = Input(UInt(IFU_BUS_TAG.W))
val ifu_axi_rdata = Input(UInt(64.W))
val ifu_axi_rresp = Input(UInt(2.W))
val ifu_axi_rlast = Input(Bool())
// SB AXI Signals
val sb_axi_awvalid = Output(Bool())
val sb_axi_awready = Input(Bool())
val sb_axi_awid = Output(UInt(SB_BUS_TAG.W))
val sb_axi_awaddr = Output(UInt(32.W))
val sb_axi_awregion = Output(UInt(4.W))
val sb_axi_awlen = Output(UInt(8.W))
val sb_axi_awsize = Output(UInt(3.W))
val sb_axi_awburst = Output(UInt(2.W))
val sb_axi_awlock = Output(Bool())
val sb_axi_awcache = Output(UInt(4.W))
val sb_axi_awprot = Output(UInt(3.W))
val sb_axi_awqos = Output(UInt(4.W))
val sb_axi_wvalid = Output(Bool())
val sb_axi_wready = Input(Bool())
val sb_axi_wdata = Output(UInt(64.W))
val sb_axi_wstrb = Output(UInt(8.W))
val sb_axi_wlast = Output(Bool())
val sb_axi_bvalid = Input(Bool())
val sb_axi_bready = Output(Bool())
val sb_axi_bresp = Input(UInt(2.W))
val sb_axi_bid = Input(UInt(SB_BUS_TAG.W))
val sb_axi_arvalid = Output(Bool())
val sb_axi_arready = Input(Bool())
val sb_axi_arid = Output(UInt(SB_BUS_TAG.W))
val sb_axi_araddr = Output(UInt(32.W))
val sb_axi_arregion = Output(UInt(4.W))
val sb_axi_arlen = Output(UInt(8.W))
val sb_axi_arsize = Output(UInt(3.W))
val sb_axi_arburst = Output(UInt(2.W))
val sb_axi_arlock = Output(Bool())
val sb_axi_arcache = Output(UInt(4.W))
val sb_axi_arprot = Output(UInt(3.W))
val sb_axi_arqos = Output(UInt(4.W))
val sb_axi_rvalid = Input(Bool())
val sb_axi_rready = Output(Bool())
val sb_axi_rid = Input(UInt(SB_BUS_TAG.W))
val sb_axi_rdata = Input(UInt(64.W))
val sb_axi_rresp = Input(UInt(2.W))
val sb_axi_rlast = Input(Bool())
// DMA signals
val dma_axi_awvalid = Input(Bool())
val dma_axi_awready = Output(Bool())
val dma_axi_awid = Input(UInt(DMA_BUS_TAG.W))
val dma_axi_awaddr = Input(UInt(32.W))
val dma_axi_awsize = Input(UInt(3.W))
val dma_axi_awprot = Input(UInt(3.W))
val dma_axi_awlen = Input(UInt(8.W))
val dma_axi_awburst = Input(UInt(2.W))
val dma_axi_wvalid = Input(Bool())
val dma_axi_wready = Output(Bool())
val dma_axi_wdata = Input(UInt(64.W))
val dma_axi_wstrb = Input(UInt(8.W))
val dma_axi_wlast = Input(Bool())
val dma_axi_bvalid = Output(Bool())
val dma_axi_bready = Input(Bool())
val dma_axi_bresp = Output(UInt(2.W))
val dma_axi_bid = Output(UInt(DMA_BUS_TAG.W))
// AXI Read Channels
val dma_axi_arvalid = Input(Bool())
val dma_axi_arready = Output(Bool())
val dma_axi_arid = Input(UInt(DMA_BUS_TAG.W))
val dma_axi_araddr = Input(UInt(32.W))
val dma_axi_arsize = Input(UInt(3.W))
val dma_axi_arprot = Input(UInt(3.W))
val dma_axi_arlen = Input(UInt(8.W))
val dma_axi_arburst = Input(UInt(2.W))
val dma_axi_rvalid = Output(Bool())
val dma_axi_rready = Input(Bool())
val dma_axi_rid = Output(UInt(DMA_BUS_TAG.W))
val dma_axi_rdata = Output(UInt(64.W))
val dma_axi_rresp = Output(UInt(2.W))
val dma_axi_rlast = Output(Bool())
// AHB Lite Bus
val haddr = Output(UInt(32.W))
val hburst = Output(UInt(3.W))
val hmastlock = Output(Bool())
val hprot = Output(UInt(4.W))
val hsize = Output(UInt(3.W))
val htrans = Output(UInt(2.W))
val hwrite = Output(Bool())
val hrdata = Input(UInt(64.W))
val hready = Input(Bool())
val hresp = Input(Bool())
// AHB Master
val lsu_haddr = Output(UInt(32.W))
val lsu_hburst = Output(UInt(3.W))
val lsu_hmastlock = Output(Bool())
val lsu_hprot = Output(UInt(4.W))
val lsu_hsize = Output(UInt(3.W))
val lsu_htrans = Output(UInt(2.W))
val lsu_hwrite = Output(Bool())
val lsu_hwdata = Output(UInt(64.W))
val lsu_hrdata = Input(UInt(64.W))
val lsu_hready = Input(Bool())
val lsu_hresp = Input(Bool())
// System Bus Debug Master
val sb_haddr = Output(UInt(32.W))
val sb_hburst = Output(UInt(3.W))
val sb_hmastlock = Output(Bool())
val sb_hprot = Output(UInt(4.W))
val sb_hsize = Output(UInt(3.W))
val sb_htrans = Output(UInt(2.W))
val sb_hwrite = Output(Bool())
val sb_hwdata = Output(UInt(64.W))
val sb_hrdata = Input(UInt(64.W))
val sb_hready = Input(Bool())
val sb_hresp = Input(Bool())
// DMA slave
val dma_hsel = Input(Bool())
val dma_haddr = Input(UInt(32.W))
val dma_hburst = Input(UInt(3.W))
val dma_hmastlock = Input(Bool())
val dma_hprot = Input(UInt(4.W))
val dma_hsize = Input(UInt(3.W))
val dma_htrans = Input(UInt(2.W))
val dma_hwrite = Input(Bool())
val dma_hwdata = Input(UInt(64.W))
val dma_hreadyin = Input(Bool())
val dma_hrdata = Output(UInt(64.W))
val dma_hreadyout = Output(Bool())
val dma_hresp = Output(Bool())
val lsu_bus_clk_en = Input(Bool())
val ifu_bus_clk_en = Input(Bool())
val dbg_bus_clk_en = Input(Bool())
val dma_bus_clk_en = Input(Bool())
val dmi_reg_en = Input(Bool())
val dmi_reg_addr = Input(UInt(7.W))
val dmi_reg_wr_en = Input(Bool())
val dmi_reg_wdata = Input(UInt(32.W))
val dmi_reg_rdata = Output(UInt(32.W))
val dmi_hard_reset = Input(Bool())
val extintsrc_req = Input(UInt(PIC_TOTAL_INT.W))
val timer_int = Input(Bool())
val soft_int = Input(Bool())
val scan_mode = Input(Bool())
}
class el2_swerv extends Module with RequireAsyncReset with el2_lib { class el2_swerv extends Module with RequireAsyncReset with el2_lib {
val io = IO (new Bundle{ val io = IO (new el2_swerv_bundle)
val dbg_rst_l = Input(Bool())
val rst_vec = Input(UInt(31.W))
val nmi_int = Input(Bool())
val nmi_vec = Input(UInt(31.W))
val core_rst_l = Output(AsyncReset())
val trace_rv_i_insn_ip = Output(UInt(32.W))
val trace_rv_i_address_ip = Output(UInt(32.W))
val trace_rv_i_valid_ip = Output(UInt(2.W))
val trace_rv_i_exception_ip = Output(UInt(2.W))
val trace_rv_i_ecause_ip = Output(UInt(5.W))
val trace_rv_i_interrupt_ip = Output(UInt(2.W))
val trace_rv_i_tval_ip = Output(UInt(32.W))
val dccm_clk_override = Output(Bool())
val icm_clk_override = Output(Bool())
val dec_tlu_core_ecc_disable = Output(Bool())
val i_cpu_halt_req = Input(Bool())
val i_cpu_run_req = Input(Bool())
val o_cpu_halt_ack = Output(Bool())
val o_cpu_halt_status = Output(Bool())
val o_cpu_run_ack = Output(Bool())
val o_debug_mode_status = Output(Bool())
val core_id = Input(UInt(28.W))
val mpc_debug_halt_req = Input(Bool())
val mpc_debug_run_req = Input(Bool())
val mpc_reset_run_req = Input(Bool())
val mpc_debug_halt_ack = Output(Bool())
val mpc_debug_run_ack = Output(Bool())
val debug_brkpt_status = Output(Bool())
val dec_tlu_perfcnt0 = Output(Bool())
val dec_tlu_perfcnt1 = Output(Bool())
val dec_tlu_perfcnt2 = Output(Bool())
val dec_tlu_perfcnt3 = Output(Bool())
val dccm_wren = Output(Bool())
val dccm_rden = Output(Bool())
val dccm_wr_addr_lo = Output(UInt(DCCM_BITS.W))
val dccm_wr_addr_hi = Output(UInt(DCCM_BITS.W))
val dccm_rd_addr_lo = Output(UInt(DCCM_BITS.W))
val dccm_rd_addr_hi = Output(UInt(DCCM_BITS.W))
val dccm_wr_data_lo = Output(UInt(DCCM_FDATA_WIDTH.W))
val dccm_wr_data_hi = Output(UInt(DCCM_FDATA_WIDTH.W))
val dccm_rd_data_lo = Input(UInt(DCCM_FDATA_WIDTH.W))
val dccm_rd_data_hi = Input(UInt(DCCM_FDATA_WIDTH.W))
val iccm_rw_addr = Output(UInt(ICCM_BITS.W))
val iccm_wren = Output(Bool())
val iccm_rden = Output(Bool())
val iccm_wr_size = Output(UInt(3.W))
val iccm_wr_data = Output(UInt(78.W))
val iccm_buf_correct_ecc = Output(Bool())
val iccm_correction_state = Output(Bool())
val iccm_rd_data = Input(UInt(64.W))
val iccm_rd_data_ecc = Input(UInt(78.W))
val ic_rw_addr = Output(UInt(31.W))
val ic_tag_valid = Output(UInt(ICACHE_NUM_WAYS.W))
val ic_wr_en = Output(UInt(ICACHE_NUM_WAYS.W))
val ic_rd_en = Output(Bool())
val ic_wr_data = Output(Vec(ICACHE_BANKS_WAY, UInt(71.W)))
val ic_rd_data = Input(UInt(64.W))
val ic_debug_rd_data = Input(UInt(71.W))
val ictag_debug_rd_data = Input(UInt(26.W))
val ic_debug_wr_data = Output(UInt(71.W))
val ic_eccerr = Input(UInt(ICACHE_BANKS_WAY.W))
val ic_parerr = Input(UInt(ICACHE_BANKS_WAY.W))
val ic_premux_data = Output(UInt(64.W))
val ic_sel_premux_data = Output(Bool())
val ic_debug_addr = Output(UInt((ICACHE_INDEX_HI-2).W))
val ic_debug_rd_en = Output(Bool())
val ic_debug_wr_en = Output(Bool())
val ic_debug_tag_array = Output(Bool())
val ic_debug_way = Output(UInt(ICACHE_NUM_WAYS.W))
val ic_rd_hit = Input(UInt(ICACHE_NUM_WAYS.W))
val ic_tag_perr = Input(Bool())
// AXI Signals
val lsu_axi_awvalid = Output(Bool())
val lsu_axi_awready = Input(Bool())
val lsu_axi_awid = Output(UInt(LSU_BUS_TAG.W))
val lsu_axi_awaddr = Output(UInt(32.W))
val lsu_axi_awregion = Output(UInt(4.W))
val lsu_axi_awlen = Output(UInt(8.W))
val lsu_axi_awsize = Output(UInt(3.W))
val lsu_axi_awburst = Output(UInt(2.W))
val lsu_axi_awlock = Output(Bool())
val lsu_axi_awcache = Output(UInt(4.W))
val lsu_axi_awprot = Output(UInt(3.W))
val lsu_axi_awqos = Output(UInt(4.W))
val lsu_axi_wvalid = Output(Bool())
val lsu_axi_wready = Input(Bool())
val lsu_axi_wdata = Output(UInt(64.W))
val lsu_axi_wstrb = Output(UInt(8.W))
val lsu_axi_wlast = Output(Bool())
val lsu_axi_bvalid = Input(Bool())
val lsu_axi_bready = Output(Bool())
val lsu_axi_bresp = Input(UInt(2.W))
val lsu_axi_bid = Input(UInt(LSU_BUS_TAG.W))
val lsu_axi_arvalid = Output(Bool())
val lsu_axi_arready = Input(Bool())
val lsu_axi_arid = Output(UInt(LSU_BUS_TAG.W))
val lsu_axi_araddr = Output(UInt(32.W))
val lsu_axi_arregion = Output(UInt(4.W))
val lsu_axi_arlen = Output(UInt(8.W))
val lsu_axi_arsize = Output(UInt(3.W))
val lsu_axi_arburst = Output(UInt(2.W))
val lsu_axi_arlock = Output(Bool())
val lsu_axi_arcache = Output(UInt(4.W))
val lsu_axi_arprot = Output(UInt(3.W))
val lsu_axi_arqos = Output(UInt(4.W))
val lsu_axi_rvalid = Input(Bool())
val lsu_axi_rready = Output(Bool())
val lsu_axi_rid = Input(UInt(LSU_BUS_TAG.W))
val lsu_axi_rdata = Input(UInt(64.W))
val lsu_axi_rresp = Input(UInt(2.W))
val lsu_axi_rlast = Input(Bool())
// AXI IFU Signals
val ifu_axi_awvalid = Output(Bool())
val ifu_axi_awready = Input(Bool())
val ifu_axi_awid = Output(UInt(IFU_BUS_TAG.W))
val ifu_axi_awaddr = Output(UInt(32.W))
val ifu_axi_awregion = Output(UInt(4.W))
val ifu_axi_awlen = Output(UInt(8.W))
val ifu_axi_awsize = Output(UInt(3.W))
val ifu_axi_awburst = Output(UInt(2.W))
val ifu_axi_awlock = Output(Bool())
val ifu_axi_awcache = Output(UInt(4.W))
val ifu_axi_awprot = Output(UInt(3.W))
val ifu_axi_awqos = Output(UInt(4.W))
val ifu_axi_wvalid = Output(Bool())
val ifu_axi_wready = Output(Bool())
val ifu_axi_wdata = Output(UInt(64.W))
val ifu_axi_wstrb = Output(UInt(8.W))
val ifu_axi_wlast = Output(Bool())
val ifu_axi_bvalid = Input(Bool())
val ifu_axi_bready = Output(Bool())
val ifu_axi_bresp = Input(UInt(2.W))
val ifu_axi_bid = Input(UInt(IFU_BUS_TAG.W))
val ifu_axi_arvalid = Output(Bool())
val ifu_axi_arready = Input(Bool())
val ifu_axi_arid = Output(UInt(IFU_BUS_TAG.W))
val ifu_axi_araddr = Output(UInt(32.W))
val ifu_axi_arregion = Output(UInt(4.W))
val ifu_axi_arlen = Output(UInt(8.W))
val ifu_axi_arsize = Output(UInt(3.W))
val ifu_axi_arburst = Output(UInt(2.W))
val ifu_axi_arlock = Output(Bool())
val ifu_axi_arcache = Output(UInt(4.W))
val ifu_axi_arprot = Output(UInt(3.W))
val ifu_axi_arqos = Output(UInt(4.W))
val ifu_axi_rvalid = Input(Bool())
val ifu_axi_rready = Output(Bool())
val ifu_axi_rid = Input(UInt(IFU_BUS_TAG.W))
val ifu_axi_rdata = Input(UInt(64.W))
val ifu_axi_rresp = Input(UInt(2.W))
val ifu_axi_rlast = Input(Bool())
// SB AXI Signals
val sb_axi_awvalid = Output(Bool())
val sb_axi_awready = Input(Bool())
val sb_axi_awid = Output(UInt(SB_BUS_TAG.W))
val sb_axi_awaddr = Output(UInt(32.W))
val sb_axi_awregion = Output(UInt(4.W))
val sb_axi_awlen = Output(UInt(8.W))
val sb_axi_awsize = Output(UInt(3.W))
val sb_axi_awburst = Output(UInt(2.W))
val sb_axi_awlock = Output(Bool())
val sb_axi_awcache = Output(UInt(4.W))
val sb_axi_awprot = Output(UInt(3.W))
val sb_axi_awqos = Output(UInt(4.W))
val sb_axi_wvalid = Output(Bool())
val sb_axi_wready = Input(Bool())
val sb_axi_wdata = Output(UInt(64.W))
val sb_axi_wstrb = Output(UInt(8.W))
val sb_axi_wlast = Output(Bool())
val sb_axi_bvalid = Input(Bool())
val sb_axi_bready = Output(Bool())
val sb_axi_bresp = Input(UInt(2.W))
val sb_axi_bid = Input(UInt(SB_BUS_TAG.W))
val sb_axi_arvalid = Output(Bool())
val sb_axi_arready = Input(Bool())
val sb_axi_arid = Output(UInt(SB_BUS_TAG.W))
val sb_axi_araddr = Output(UInt(32.W))
val sb_axi_arregion = Output(UInt(4.W))
val sb_axi_arlen = Output(UInt(8.W))
val sb_axi_arsize = Output(UInt(3.W))
val sb_axi_arburst = Output(UInt(2.W))
val sb_axi_arlock = Output(Bool())
val sb_axi_arcache = Output(UInt(4.W))
val sb_axi_arprot = Output(UInt(3.W))
val sb_axi_arqos = Output(UInt(4.W))
val sb_axi_rvalid = Input(Bool())
val sb_axi_rready = Output(Bool())
val sb_axi_rid = Input(UInt(SB_BUS_TAG.W))
val sb_axi_rdata = Input(UInt(64.W))
val sb_axi_rresp = Input(UInt(2.W))
val sb_axi_rlast = Input(Bool())
// DMA signals
val dma_axi_awvalid = Input(Bool())
val dma_axi_awready = Output(Bool())
val dma_axi_awid = Input(UInt(DMA_BUS_TAG.W))
val dma_axi_awaddr = Input(UInt(32.W))
val dma_axi_awsize = Input(UInt(3.W))
val dma_axi_awprot = Input(UInt(3.W))
val dma_axi_awlen = Input(UInt(8.W))
val dma_axi_awburst = Input(UInt(2.W))
val dma_axi_wvalid = Input(Bool())
val dma_axi_wready = Output(Bool())
val dma_axi_wdata = Input(UInt(64.W))
val dma_axi_wstrb = Input(UInt(8.W))
val dma_axi_wlast = Input(Bool())
val dma_axi_bvalid = Output(Bool())
val dma_axi_bready = Input(Bool())
val dma_axi_bresp = Output(UInt(2.W))
val dma_axi_bid = Output(UInt(DMA_BUS_TAG.W))
// AXI Read Channels
val dma_axi_arvalid = Input(Bool())
val dma_axi_arready = Output(Bool())
val dma_axi_arid = Input(UInt(DMA_BUS_TAG.W))
val dma_axi_araddr = Input(UInt(32.W))
val dma_axi_arsize = Input(UInt(3.W))
val dma_axi_arprot = Input(UInt(3.W))
val dma_axi_arlen = Input(UInt(8.W))
val dma_axi_arburst = Input(UInt(2.W))
val dma_axi_rvalid = Output(Bool())
val dma_axi_rready = Input(Bool())
val dma_axi_rid = Output(UInt(DMA_BUS_TAG.W))
val dma_axi_rdata = Output(UInt(64.W))
val dma_axi_rresp = Output(UInt(2.W))
val dma_axi_rlast = Output(Bool())
// AHB Lite Bus
val haddr = Output(UInt(32.W))
val hburst = Output(UInt(3.W))
val hmastlock = Output(Bool())
val hprot = Output(UInt(4.W))
val hsize = Output(UInt(3.W))
val htrans = Output(UInt(2.W))
val hwrite = Output(Bool())
val hrdata = Input(UInt(64.W))
val hready = Input(Bool())
val hresp = Input(Bool())
// AHB Master
val lsu_haddr = Output(UInt(32.W))
val lsu_hburst = Output(UInt(3.W))
val lsu_hmastlock = Output(Bool())
val lsu_hprot = Output(UInt(4.W))
val lsu_hsize = Output(UInt(3.W))
val lsu_htrans = Output(UInt(2.W))
val lsu_hwrite = Output(Bool())
val lsu_hwdata = Output(UInt(64.W))
val lsu_hrdata = Input(UInt(64.W))
val lsu_hready = Input(Bool())
val lsu_hresp = Input(Bool())
// System Bus Debug Master
val sb_haddr = Output(UInt(32.W))
val sb_hburst = Output(UInt(3.W))
val sb_hmastlock = Output(Bool())
val sb_hprot = Output(UInt(4.W))
val sb_hsize = Output(UInt(3.W))
val sb_htrans = Output(UInt(2.W))
val sb_hwrite = Output(Bool())
val sb_hwdata = Output(UInt(64.W))
val sb_hrdata = Input(UInt(64.W))
val sb_hready = Input(Bool())
val sb_hresp = Input(Bool())
// DMA slave
val dma_hsel = Input(Bool())
val dma_haddr = Input(UInt(32.W))
val dma_hburst = Input(UInt(3.W))
val dma_hmastlock = Input(Bool())
val dma_hprot = Input(UInt(4.W))
val dma_hsize = Input(UInt(3.W))
val dma_htrans = Input(UInt(2.W))
val dma_hwrite = Input(Bool())
val dma_hwdata = Input(UInt(64.W))
val dma_hreadyin = Input(Bool())
val dma_hrdata = Output(UInt(64.W))
val dma_hreadyout = Output(Bool())
val dma_hresp = Output(Bool())
val lsu_bus_clk_en = Input(Bool())
val ifu_bus_clk_en = Input(Bool())
val dbg_bus_clk_en = Input(Bool())
val dma_bus_clk_en = Input(Bool())
val dmi_reg_en = Input(Bool())
val dmi_reg_addr = Input(UInt(7.W))
val dmi_reg_wr_en = Input(Bool())
val dmi_reg_wdata = Input(UInt(32.W))
val dmi_reg_rdata = Output(UInt(32.W))
val dmi_hard_reset = Input(Bool())
val extintsrc_req = Input(UInt(PIC_TOTAL_INT.W))
val timer_int = Input(Bool())
val soft_int = Input(Bool())
val scan_mode = Input(Bool())
})
val ifu = Module(new el2_ifu) val ifu = Module(new el2_ifu)
val dec = Module(new el2_dec) val dec = Module(new el2_dec)
val dbg = Module(new el2_dbg) val dbg = Module(new el2_dbg)
val exu = Module(new el2_exu) val exu = Module(new el2_exu)
val lsu = Module(new el2_lsu) val lsu = Module(new el2_lsu)
val pic_ctl_inst = Module(new el2_pic_ctrl) val pic_ctrl_inst = Module(new el2_pic_ctrl)
val dma_ctrl = Module(new el2_dma_ctrl) val dma_ctrl = Module(new el2_dma_ctrl)
//val lsu_axi4_to_ahb = Module(new axi4_to_ahb) //val lsu_axi4_to_ahb = Module(new axi4_to_ahb)
//val ifu_axi4_to_ahb = Module(new axi4_to_ahb) //val ifu_axi4_to_ahb = Module(new axi4_to_ahb)
//val sb_axi4_to_ahb = Module(new axi4_to_ahb) //val sb_axi4_to_ahb = Module(new axi4_to_ahb)
io.core_rst_l := (!(reset.asBool() & (dbg.io.dbg_core_rst_l.asBool() | io.scan_mode))).asAsyncReset() io.core_rst_l := (reset.asBool() & (dbg.io.dbg_core_rst_l.asBool() | io.scan_mode)).asAsyncReset()
val active_state = (!dec.io.dec_pause_state_cg | dec.io.dec_tlu_flush_lower_r) | dec.io.dec_tlu_misc_clk_override val active_state = (!dec.io.dec_pause_state_cg | dec.io.dec_tlu_flush_lower_r) | dec.io.dec_tlu_misc_clk_override
val free_clk = rvclkhdr(clock, true.B, io.scan_mode) val free_clk = rvclkhdr(clock, true.B, io.scan_mode)
val active_clk = rvclkhdr(clock, active_state, io.scan_mode) val active_clk = rvclkhdr(clock, active_state, io.scan_mode)
@ -477,11 +475,11 @@ class el2_swerv extends Module with RequireAsyncReset with el2_lib {
dec.io.ifu_i0_pc := ifu.io.ifu_i0_pc dec.io.ifu_i0_pc := ifu.io.ifu_i0_pc
dec.io.ifu_i0_pc4 := ifu.io.ifu_i0_pc4 dec.io.ifu_i0_pc4 := ifu.io.ifu_i0_pc4
dec.io.exu_i0_pc_x := exu.io.exu_i0_pc_x dec.io.exu_i0_pc_x := exu.io.exu_i0_pc_x
dec.io.mexintpend := pic_ctl_inst.io.mexintpend dec.io.mexintpend := pic_ctrl_inst.io.mexintpend
dec.io.soft_int := io.soft_int dec.io.soft_int := io.soft_int
dec.io.pic_claimid := pic_ctl_inst.io.claimid dec.io.pic_claimid := pic_ctrl_inst.io.claimid
dec.io.pic_pl := pic_ctl_inst.io.pl dec.io.pic_pl := pic_ctrl_inst.io.pl
dec.io.mhwakeup := pic_ctl_inst.io.mhwakeup dec.io.mhwakeup := pic_ctrl_inst.io.mhwakeup
dec.io.ifu_ic_debug_rd_data := ifu.io.ifu_ic_debug_rd_data dec.io.ifu_ic_debug_rd_data := ifu.io.ifu_ic_debug_rd_data
dec.io.ifu_ic_debug_rd_data_valid := ifu.io.ifu_ic_debug_rd_data_valid dec.io.ifu_ic_debug_rd_data_valid := ifu.io.ifu_ic_debug_rd_data_valid
dec.io.dbg_halt_req := dbg.io.dbg_halt_req dec.io.dbg_halt_req := dbg.io.dbg_halt_req
@ -597,7 +595,7 @@ class el2_swerv extends Module with RequireAsyncReset with el2_lib {
dbg.io.sb_axi_rdata := io.sb_axi_rdata dbg.io.sb_axi_rdata := io.sb_axi_rdata
dbg.io.sb_axi_rresp := io.sb_axi_rresp dbg.io.sb_axi_rresp := io.sb_axi_rresp
dbg.io.dbg_bus_clk_en := io.dbg_bus_clk_en dbg.io.dbg_bus_clk_en := io.dbg_bus_clk_en
dbg.io.dbg_rst_l := io.dbg_rst_l dbg.io.dbg_rst_l := io.dbg_rst_l.asBool()
dbg.io.clk_override := dec.io.dec_tlu_misc_clk_override dbg.io.clk_override := dec.io.dec_tlu_misc_clk_override
dbg.io.scan_mode := io.scan_mode dbg.io.scan_mode := io.scan_mode
@ -642,21 +640,21 @@ class el2_swerv extends Module with RequireAsyncReset with el2_lib {
// PIC lets go // PIC lets go
pic_ctl_inst.io.scan_mode := io.scan_mode pic_ctrl_inst.io.scan_mode := io.scan_mode
pic_ctl_inst.reset := io.core_rst_l pic_ctrl_inst.reset := io.core_rst_l
pic_ctl_inst.io.free_clk := free_clk pic_ctrl_inst.io.free_clk := free_clk
pic_ctl_inst.io.active_clk := active_clk pic_ctrl_inst.io.active_clk := active_clk
pic_ctl_inst.io.clk_override := dec.io.dec_tlu_pic_clk_override pic_ctrl_inst.io.clk_override := dec.io.dec_tlu_pic_clk_override
pic_ctl_inst.io.extintsrc_req := io.extintsrc_req pic_ctrl_inst.io.extintsrc_req := io.extintsrc_req
pic_ctl_inst.io.picm_rdaddr := lsu.io.picm_rdaddr pic_ctrl_inst.io.picm_rdaddr := lsu.io.picm_rdaddr
pic_ctl_inst.io.picm_wraddr := lsu.io.picm_wraddr pic_ctrl_inst.io.picm_wraddr := lsu.io.picm_wraddr
pic_ctl_inst.io.picm_wr_data := lsu.io.picm_wr_data pic_ctrl_inst.io.picm_wr_data := lsu.io.picm_wr_data
pic_ctl_inst.io.picm_wren := lsu.io.picm_wren pic_ctrl_inst.io.picm_wren := lsu.io.picm_wren
pic_ctl_inst.io.picm_rden := lsu.io.picm_rden pic_ctrl_inst.io.picm_rden := lsu.io.picm_rden
pic_ctl_inst.io.picm_mken := lsu.io.picm_mken pic_ctrl_inst.io.picm_mken := lsu.io.picm_mken
pic_ctl_inst.io.meicurpl := dec.io.dec_tlu_meicurpl pic_ctrl_inst.io.meicurpl := dec.io.dec_tlu_meicurpl
pic_ctl_inst.io.meipt := dec.io.dec_tlu_meipt pic_ctrl_inst.io.meipt := dec.io.dec_tlu_meipt
lsu.io.picm_rd_data := pic_ctl_inst.io.picm_rd_data lsu.io.picm_rd_data := pic_ctrl_inst.io.picm_rd_data
@ -853,7 +851,7 @@ class el2_swerv extends Module with RequireAsyncReset with el2_lib {
io.dma_hreadyout := 0.U io.dma_hreadyout := 0.U
io.dma_hresp := 0.U io.dma_hresp := 0.U
io.ifu_axi_wready := 0.U //io.ifu_axi_wready := 0.U
io.dma_hresp := 0.U //dbg.io.dma_hresp io.dma_hresp := 0.U //dbg.io.dma_hresp
@ -866,4 +864,3 @@ object SWERV extends App {
} }

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