From 8a6c7fd88f198462b784c26859ed32d887940b04 Mon Sep 17 00:00:00 2001 From: waleed-lm Date: Tue, 13 Oct 2020 11:20:10 +0500 Subject: [PATCH] Aligner Updated --- el2_ifu_aln_ctl.fir | 2 +- el2_ifu_aln_ctl.v | 9 ++++----- src/main/scala/ifu/el2_ifu_aln_ctl.scala | 5 +++-- .../classes/ifu/el2_ifu_aln_ctl$$anon$1.class | Bin 6820 -> 6822 bytes 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/el2_ifu_aln_ctl.fir b/el2_ifu_aln_ctl.fir index a3adff11..b14d5b21 100644 --- a/el2_ifu_aln_ctl.fir +++ b/el2_ifu_aln_ctl.fir @@ -1996,7 +1996,7 @@ circuit el2_ifu_aln_ctl : module el2_ifu_aln_ctl : input clock : Clock input reset : UInt<1> - output io : {flip scan_mode : UInt<1>, flip active_clk : Clock, flip ifu_async_error_start : UInt<1>, flip iccm_rd_ecc_double_err : UInt<1>, flip ic_access_fault_f : UInt<1>, flip ic_access_fault_type_f : UInt<2>, flip ifu_bp_fghr_f : UInt<8>, flip ifu_bp_btb_target_f : UInt<32>, flip ifu_bp_poffset_f : UInt<12>, flip ifu_bp_hist0_f : UInt<2>, flip ifu_bp_hist1_f : UInt<2>, flip ifu_bp_pc4_f : UInt<2>, flip ifu_bp_way_f : UInt<2>, flip ifu_bp_valid_f : UInt<2>, flip ifu_bp_ret_f : UInt<2>, flip exu_flush_final : UInt<1>, flip dec_i0_decode_d : UInt<1>, flip ifu_fetch_data_f : UInt<32>, flip ifu_fetch_val : UInt<2>, flip ifu_fetch_pc : UInt<31>, ifu_i0_valid : UInt<1>, ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_icaf_f1 : UInt<1>, ifu_i0_dbecc : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<32>, ifu_i0_pc4 : UInt<1>, ifu_fb_consume1 : UInt<1>, ifu_fb_consume2 : UInt<1>, ifu_i0_bp_index : UInt<7>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, ifu_pmu_instr_aligned : UInt<1>, ifu_i0_cinst : UInt<16>, i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}} + output io : {flip scan_mode : UInt<1>, flip active_clk : Clock, flip ifu_async_error_start : UInt<1>, flip iccm_rd_ecc_double_err : UInt<1>, flip ic_access_fault_f : UInt<1>, flip ic_access_fault_type_f : UInt<2>, flip ifu_bp_fghr_f : UInt<8>, flip ifu_bp_btb_target_f : UInt<32>, flip ifu_bp_poffset_f : UInt<12>, flip ifu_bp_hist0_f : UInt<2>, flip ifu_bp_hist1_f : UInt<2>, flip ifu_bp_pc4_f : UInt<2>, flip ifu_bp_way_f : UInt<2>, flip ifu_bp_valid_f : UInt<2>, flip ifu_bp_ret_f : UInt<2>, flip exu_flush_final : UInt<1>, flip dec_i0_decode_d : UInt<1>, flip ifu_fetch_data_f : UInt<32>, flip ifu_fetch_val : UInt<2>, flip ifu_fetch_pc : UInt<31>, ifu_i0_valid : UInt<1>, ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_icaf_f1 : UInt<1>, ifu_i0_dbecc : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<31>, ifu_i0_pc4 : UInt<1>, ifu_fb_consume1 : UInt<1>, ifu_fb_consume2 : UInt<1>, ifu_i0_bp_index : UInt<8>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, ifu_pmu_instr_aligned : UInt<1>, ifu_i0_cinst : UInt<16>, i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}} io.ifu_i0_valid <= UInt<1>("h00") @[el2_ifu_aln_ctl.scala 47:19] io.ifu_i0_icaf <= UInt<1>("h00") @[el2_ifu_aln_ctl.scala 48:18] diff --git a/el2_ifu_aln_ctl.v b/el2_ifu_aln_ctl.v index 277c332e..fe8663d5 100644 --- a/el2_ifu_aln_ctl.v +++ b/el2_ifu_aln_ctl.v @@ -536,11 +536,11 @@ module el2_ifu_aln_ctl( output io_ifu_i0_icaf_f1, output io_ifu_i0_dbecc, output [31:0] io_ifu_i0_instr, - output [31:0] io_ifu_i0_pc, + output [30:0] io_ifu_i0_pc, output io_ifu_i0_pc4, output io_ifu_fb_consume1, output io_ifu_fb_consume2, - output [6:0] io_ifu_i0_bp_index, + output [7:0] io_ifu_i0_bp_index, output [7:0] io_ifu_i0_bp_fghr, output [4:0] io_ifu_i0_bp_btag, output io_ifu_pmu_instr_aligned, @@ -981,7 +981,6 @@ module el2_ifu_aln_ctl( wire _T_769 = ~i0_brp_pc4; // @[el2_ifu_aln_ctl.scala 398:89] wire _T_770 = io_i0_brp_valid & _T_769; // @[el2_ifu_aln_ctl.scala 398:87] wire _T_771 = _T_770 & first4B; // @[el2_ifu_aln_ctl.scala 398:101] - wire [7:0] _T_776 = _T_737 ? firstpc_hash : secondpc_hash; // @[el2_ifu_aln_ctl.scala 400:28] el2_ifu_compress_ctl decompressed ( // @[el2_ifu_aln_ctl.scala 366:28] .io_din(decompressed_io_din), .io_dout(decompressed_io_dout) @@ -992,11 +991,11 @@ module el2_ifu_aln_ctl( assign io_ifu_i0_icaf_f1 = _T_683 & _T_516; // @[el2_ifu_aln_ctl.scala 50:21 el2_ifu_aln_ctl.scala 360:21] assign io_ifu_i0_dbecc = _T_689 | _T_690; // @[el2_ifu_aln_ctl.scala 51:19 el2_ifu_aln_ctl.scala 362:19] assign io_ifu_i0_instr = _T_697[31:0]; // @[el2_ifu_aln_ctl.scala 52:19 el2_ifu_aln_ctl.scala 368:19] - assign io_ifu_i0_pc = {{1'd0}, f0pc}; // @[el2_ifu_aln_ctl.scala 53:16 el2_ifu_aln_ctl.scala 340:16] + assign io_ifu_i0_pc = f0pc; // @[el2_ifu_aln_ctl.scala 53:16 el2_ifu_aln_ctl.scala 340:16] assign io_ifu_i0_pc4 = aligndata[1:0] == 2'h3; // @[el2_ifu_aln_ctl.scala 54:17 el2_ifu_aln_ctl.scala 344:17] assign io_ifu_fb_consume1 = _T_313 & _T_1; // @[el2_ifu_aln_ctl.scala 55:22 el2_ifu_aln_ctl.scala 258:22] assign io_ifu_fb_consume2 = _T_316 & _T_1; // @[el2_ifu_aln_ctl.scala 56:22 el2_ifu_aln_ctl.scala 259:22] - assign io_ifu_i0_bp_index = _T_776[6:0]; // @[el2_ifu_aln_ctl.scala 57:22 el2_ifu_aln_ctl.scala 400:22] + assign io_ifu_i0_bp_index = _T_737 ? firstpc_hash : secondpc_hash; // @[el2_ifu_aln_ctl.scala 57:22 el2_ifu_aln_ctl.scala 400:22] assign io_ifu_i0_bp_fghr = i0_ends_f1 ? f1fghr : f0fghr; // @[el2_ifu_aln_ctl.scala 58:21 el2_ifu_aln_ctl.scala 402:21] assign io_ifu_i0_bp_btag = _T_737 ? firstbrtag_hash : secondbrtag_hash; // @[el2_ifu_aln_ctl.scala 59:21 el2_ifu_aln_ctl.scala 404:21] assign io_ifu_pmu_instr_aligned = io_dec_i0_decode_d & _T_784; // @[el2_ifu_aln_ctl.scala 60:28 el2_ifu_aln_ctl.scala 410:28] diff --git a/src/main/scala/ifu/el2_ifu_aln_ctl.scala b/src/main/scala/ifu/el2_ifu_aln_ctl.scala index ae1dd7c4..5f9d9a1b 100644 --- a/src/main/scala/ifu/el2_ifu_aln_ctl.scala +++ b/src/main/scala/ifu/el2_ifu_aln_ctl.scala @@ -33,11 +33,12 @@ class el2_ifu_aln_ctl extends Module with el2_lib { val ifu_i0_icaf_f1 = Output(Bool()) val ifu_i0_dbecc = Output(Bool()) val ifu_i0_instr = Output(UInt(32.W)) - val ifu_i0_pc = Output(UInt(32.W)) + val ifu_i0_pc = Output(UInt(31.W)) val ifu_i0_pc4 = Output(Bool()) val ifu_fb_consume1 = Output(Bool()) val ifu_fb_consume2 = Output(Bool()) - val ifu_i0_bp_index = Output(UInt((BTB_ADDR_HI-BTB_ADDR_LO).W)) + val ifu_i0_bp_index = Output(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1 + ).W)) val ifu_i0_bp_fghr = Output(UInt(BHT_GHR_SIZE.W)) val ifu_i0_bp_btag = Output(UInt(BTB_BTAG_SIZE.W)) val ifu_pmu_instr_aligned = Output(Bool()) diff --git a/target/scala-2.12/classes/ifu/el2_ifu_aln_ctl$$anon$1.class b/target/scala-2.12/classes/ifu/el2_ifu_aln_ctl$$anon$1.class index bdc81000a80c64ebd84d995f88a9b252b8ccac4e..37cf7c9f5ca486358c37a860e207810204c16a2c 100644 GIT binary patch delta 91 zcmZ2ty3BM#un4CW0~-Sq0|QIZ<`@xMW=8qR3gY6EH;TtIu_SC3knm*GJ;$KQ{Dnb_ oMT$Y2#h5{dC7eN*rI3Mx;TZ!1gBV0BgENB*kOwlPO;U~#0CJ`g4gdfE delta 94 zcmZ2xy2Nxtun4CG0~-Sq0|QIJ<`@xM=E>%wLX-0)*d}ijkDsg{F1}e)!iZ7#41*@~ rCk8DR2?lKzLk1m|PzGI=d|;yNjXLU>K+n_