IMC started

src/main/scala/ifu/el2_ifu_mem_ctl.scala

@@ -126,6 +126,8 @@ class mem_ctl_bundle extends Bundle with el2_lib{
   val iccm_buf_correct_ecc = Output(Bool())
   val iccm_correction_state = Output(Bool())
   val scan_mode = Input(Bool())
+  val ic_miss_buff_ecc = Output(UInt())
+  val ic_wr_ecc = Output(UInt())
 }
 class el2_ifu_mem_ctl extends Module with el2_lib {
   val io = IO(new mem_ctl_bundle)
@@ -338,7 +340,9 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
   val ifu_bus_rdata_ff = WireInit(UInt(64.W), 0.U)
   val ic_miss_buff_half = WireInit(UInt(64.W), 0.U)
   val ic_wr_ecc = rvecc_encode_64(ifu_bus_rdata_ff)
+  io.ic_wr_ecc := ic_wr_ecc
   val ic_miss_buff_ecc = rvecc_encode_64(ic_miss_buff_half)
+  io.ic_miss_buff_ecc := ic_miss_buff_ecc
   val ic_wr_16bytes_data = WireInit(UInt((ICACHE_BANKS_WAY * (if(ICACHE_ECC) 71 else 68)).W), 0.U)
   io.ic_wr_data := (0 until ICACHE_BANKS_WAY).map(i=>ic_wr_16bytes_data((i*(if(ICACHE_ECC) 71 else 68))+(if(ICACHE_ECC) 70 else 67),(if(ICACHE_ECC) 71 else 68)*i))
   io.ic_debug_wr_data := io.dec_tlu_ic_diag_pkt.icache_wrdata

src/main/scala/lib/el2_lib.scala

@@ -323,7 +323,6 @@ trait el2_lib extends param{
     val mask5 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0)
     val mask6 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1)
 
-
     val w0 = Wire(Vec(35,UInt(1.W)))
     val w1 = Wire(Vec(35,UInt(1.W)))
     val w2 = Wire(Vec(35,UInt(1.W)))
@@ -349,7 +348,6 @@ trait el2_lib extends param{
     ecc_out
   }
 
-
   def rvecc_decode_64(en:UInt,din:UInt,ecc_in:UInt) = {
     val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1)
     val mask1 = Array(1,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1)