From 8c477719a6f3d3baf4fc1b1c2b8848a1430f3636 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E2=80=8BLaraib=20Khan?= <​laraib.khan@lampromellon.com> Date: Thu, 24 Dec 2020 10:44:27 +0500 Subject: [PATCH] fir_error updated --- lsu_lsc_ctl.anno.json | 8 + lsu_lsc_ctl.fir | 609 +++++++++--------- lsu_lsc_ctl.v | 409 ++++++------ src/main/scala/include/bundle.scala | 2 +- src/main/scala/lsu/lsu_lsc_ctl.scala | 3 +- .../classes/include/lsu_error_pkt_t.class | Bin 2148 -> 2148 bytes .../classes/include/lsu_pkt_t.class | Bin 2874 -> 3016 bytes target/scala-2.12/classes/lsu/lsc_ctl$.class | Bin 3864 -> 3864 bytes .../lsu/lsc_ctl$delayedInit$body.class | Bin 732 -> 732 bytes .../scala-2.12/classes/lsu/lsu_lsc_ctl.class | Bin 327747 -> 329444 bytes 10 files changed, 543 insertions(+), 488 deletions(-) diff --git a/lsu_lsc_ctl.anno.json b/lsu_lsc_ctl.anno.json index 71e96bbe..bdc211b6 100644 --- a/lsu_lsc_ctl.anno.json +++ b/lsu_lsc_ctl.anno.json @@ -125,6 +125,14 @@ "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d" ] }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_stack", + "sources":[ + "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_stack", + "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d" + ] + }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_in_pic_d", diff --git a/lsu_lsc_ctl.fir b/lsu_lsc_ctl.fir index e84d3e60..7234ac12 100644 --- a/lsu_lsc_ctl.fir +++ b/lsu_lsc_ctl.fir @@ -3,7 +3,7 @@ circuit lsu_lsc_ctl : module lsu_addrcheck : input clock : Clock input reset : AsyncReset - output io : {flip lsu_c2_m_clk : Clock, flip start_addr_d : UInt<32>, flip end_addr_d : UInt<32>, flip lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip dec_tlu_mrac_ff : UInt<32>, flip rs1_region_d : UInt<4>, flip rs1_d : UInt<32>, is_sideeffects_m : UInt<1>, addr_in_dccm_d : UInt<1>, addr_in_pic_d : UInt<1>, addr_external_d : UInt<1>, access_fault_d : UInt<1>, misaligned_fault_d : UInt<1>, exc_mscause_d : UInt<4>, fir_dccm_access_error_d : UInt<1>, fir_nondccm_access_error_d : UInt<1>, flip scan_mode : UInt<1>} + output io : {flip lsu_c2_m_clk : Clock, flip start_addr_d : UInt<32>, flip end_addr_d : UInt<32>, flip lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip dec_tlu_mrac_ff : UInt<32>, flip rs1_region_d : UInt<4>, flip rs1_d : UInt<32>, is_sideeffects_m : UInt<1>, addr_in_dccm_d : UInt<1>, addr_in_pic_d : UInt<1>, addr_external_d : UInt<1>, access_fault_d : UInt<1>, misaligned_fault_d : UInt<1>, exc_mscause_d : UInt<4>, fir_dccm_access_error_d : UInt<1>, fir_nondccm_access_error_d : UInt<1>, flip scan_mode : UInt<1>} node _T = bits(io.start_addr_d, 31, 28) @[lib.scala 365:27] node start_addr_in_dccm_region_d = eq(_T, UInt<4>("h0f")) @[lib.scala 365:49] @@ -350,15 +350,15 @@ circuit lsu_lsc_ctl : module lsu_lsc_ctl : input clock : Clock input reset : AsyncReset - output io : {flip clk_override : UInt<1>, flip lsu_c1_m_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_c2_m_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_store_c1_m_clk : Clock, flip lsu_ld_data_r : UInt<32>, flip lsu_ld_data_corr_r : UInt<32>, flip lsu_single_ecc_error_r : UInt<1>, flip lsu_double_ecc_error_r : UInt<1>, flip lsu_ld_data_m : UInt<32>, flip lsu_single_ecc_error_m : UInt<1>, flip lsu_double_ecc_error_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, flip ldst_dual_d : UInt<1>, flip ldst_dual_m : UInt<1>, flip ldst_dual_r : UInt<1>, lsu_exu : {flip exu_lsu_rs1_d : UInt<32>, flip exu_lsu_rs2_d : UInt<32>}, flip lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip dec_lsu_valid_raw_d : UInt<1>, flip dec_lsu_offset_d : UInt<12>, flip picm_mask_data_m : UInt<32>, flip bus_read_data_m : UInt<32>, lsu_result_m : UInt<32>, lsu_result_corr_r : UInt<32>, lsu_addr_d : UInt<32>, lsu_addr_m : UInt<32>, lsu_addr_r : UInt<32>, end_addr_d : UInt<32>, end_addr_m : UInt<32>, end_addr_r : UInt<32>, store_data_m : UInt<32>, flip dec_tlu_mrac_ff : UInt<32>, lsu_exc_m : UInt<1>, is_sideeffects_m : UInt<1>, lsu_commit_r : UInt<1>, lsu_single_ecc_error_incr : UInt<1>, lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, lsu_fir_addr : UInt<31>, lsu_fir_error : UInt<2>, addr_in_dccm_d : UInt<1>, addr_in_dccm_m : UInt<1>, addr_in_dccm_r : UInt<1>, addr_in_pic_d : UInt<1>, addr_in_pic_m : UInt<1>, addr_in_pic_r : UInt<1>, addr_external_m : UInt<1>, dma_lsc_ctl : {flip dma_dccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>}, lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip scan_mode : UInt<1>} + output io : {flip clk_override : UInt<1>, flip lsu_c1_m_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_c2_m_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_store_c1_m_clk : Clock, flip lsu_ld_data_r : UInt<32>, flip lsu_ld_data_corr_r : UInt<32>, flip lsu_single_ecc_error_r : UInt<1>, flip lsu_double_ecc_error_r : UInt<1>, flip lsu_ld_data_m : UInt<32>, flip lsu_single_ecc_error_m : UInt<1>, flip lsu_double_ecc_error_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, flip ldst_dual_d : UInt<1>, flip ldst_dual_m : UInt<1>, flip ldst_dual_r : UInt<1>, lsu_exu : {flip exu_lsu_rs1_d : UInt<32>, flip exu_lsu_rs2_d : UInt<32>}, flip lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip dec_lsu_valid_raw_d : UInt<1>, flip dec_lsu_offset_d : UInt<12>, flip picm_mask_data_m : UInt<32>, flip bus_read_data_m : UInt<32>, lsu_result_m : UInt<32>, lsu_result_corr_r : UInt<32>, lsu_addr_d : UInt<32>, lsu_addr_m : UInt<32>, lsu_addr_r : UInt<32>, end_addr_d : UInt<32>, end_addr_m : UInt<32>, end_addr_r : UInt<32>, store_data_m : UInt<32>, flip dec_tlu_mrac_ff : UInt<32>, lsu_exc_m : UInt<1>, is_sideeffects_m : UInt<1>, lsu_commit_r : UInt<1>, lsu_single_ecc_error_incr : UInt<1>, lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, lsu_fir_addr : UInt<31>, lsu_fir_error : UInt<2>, addr_in_dccm_d : UInt<1>, addr_in_dccm_m : UInt<1>, addr_in_dccm_r : UInt<1>, addr_in_pic_d : UInt<1>, addr_in_pic_m : UInt<1>, addr_in_pic_r : UInt<1>, addr_external_m : UInt<1>, dma_lsc_ctl : {flip dma_dccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>}, lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip scan_mode : UInt<1>} wire end_addr_pre_m : UInt<29> end_addr_pre_m <= UInt<29>("h00") wire end_addr_pre_r : UInt<29> end_addr_pre_r <= UInt<29>("h00") - wire dma_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 95:29] - wire lsu_pkt_m_in : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 96:29] - wire lsu_pkt_r_in : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 97:29] + wire dma_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 95:29] + wire lsu_pkt_m_in : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 96:29] + wire lsu_pkt_r_in : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 97:29] wire lsu_error_pkt_m : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}} @[lsu_lsc_ctl.scala 98:29] node _T = bits(io.dec_lsu_valid_raw_d, 0, 0) @[lsu_lsc_ctl.scala 100:52] node lsu_rs1_d = mux(_T, io.lsu_exu.exu_lsu_rs1_d, io.dma_lsc_ctl.dma_mem_addr) @[lsu_lsc_ctl.scala 100:28] @@ -451,6 +451,7 @@ circuit lsu_lsc_ctl : addrcheck.io.lsu_pkt_d.bits.word <= io.lsu_pkt_d.bits.word @[lsu_lsc_ctl.scala 124:42] addrcheck.io.lsu_pkt_d.bits.half <= io.lsu_pkt_d.bits.half @[lsu_lsc_ctl.scala 124:42] addrcheck.io.lsu_pkt_d.bits.by <= io.lsu_pkt_d.bits.by @[lsu_lsc_ctl.scala 124:42] + addrcheck.io.lsu_pkt_d.bits.stack <= io.lsu_pkt_d.bits.stack @[lsu_lsc_ctl.scala 124:42] addrcheck.io.lsu_pkt_d.bits.fast_int <= io.lsu_pkt_d.bits.fast_int @[lsu_lsc_ctl.scala 124:42] addrcheck.io.lsu_pkt_d.valid <= io.lsu_pkt_d.valid @[lsu_lsc_ctl.scala 124:42] addrcheck.io.dec_tlu_mrac_ff <= io.dec_tlu_mrac_ff @[lsu_lsc_ctl.scala 125:42] @@ -569,221 +570,231 @@ circuit lsu_lsc_ctl : reg _T_111 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 187:67] _T_111 <= lsu_error_pkt_m.valid @[lsu_lsc_ctl.scala 187:67] io.lsu_error_pkt_r.valid <= _T_111 @[lsu_lsc_ctl.scala 187:30] - reg _T_112 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 188:48] - _T_112 <= lsu_fir_error_m @[lsu_lsc_ctl.scala 188:48] + reg _T_112 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 188:75] + _T_112 <= lsu_fir_error_m @[lsu_lsc_ctl.scala 188:75] io.lsu_fir_error <= _T_112 @[lsu_lsc_ctl.scala 188:38] dma_pkt_d.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 190:27] - dma_pkt_d.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 191:27] - dma_pkt_d.valid <= io.dma_lsc_ctl.dma_dccm_req @[lsu_lsc_ctl.scala 192:22] - dma_pkt_d.bits.dma <= UInt<1>("h01") @[lsu_lsc_ctl.scala 193:27] - dma_pkt_d.bits.store <= io.dma_lsc_ctl.dma_mem_write @[lsu_lsc_ctl.scala 194:27] - node _T_113 = not(io.dma_lsc_ctl.dma_mem_write) @[lsu_lsc_ctl.scala 195:30] - dma_pkt_d.bits.load <= _T_113 @[lsu_lsc_ctl.scala 195:27] - node _T_114 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 196:56] - node _T_115 = eq(_T_114, UInt<3>("h00")) @[lsu_lsc_ctl.scala 196:62] - dma_pkt_d.bits.by <= _T_115 @[lsu_lsc_ctl.scala 196:27] - node _T_116 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 197:56] - node _T_117 = eq(_T_116, UInt<3>("h01")) @[lsu_lsc_ctl.scala 197:62] - dma_pkt_d.bits.half <= _T_117 @[lsu_lsc_ctl.scala 197:27] - node _T_118 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 198:56] - node _T_119 = eq(_T_118, UInt<3>("h02")) @[lsu_lsc_ctl.scala 198:62] - dma_pkt_d.bits.word <= _T_119 @[lsu_lsc_ctl.scala 198:27] - node _T_120 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 199:56] - node _T_121 = eq(_T_120, UInt<3>("h03")) @[lsu_lsc_ctl.scala 199:62] - dma_pkt_d.bits.dword <= _T_121 @[lsu_lsc_ctl.scala 199:27] - dma_pkt_d.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 200:39] - dma_pkt_d.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 201:39] - dma_pkt_d.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 202:39] + dma_pkt_d.bits.stack <= UInt<1>("h00") @[lsu_lsc_ctl.scala 191:26] + dma_pkt_d.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 192:27] + dma_pkt_d.valid <= io.dma_lsc_ctl.dma_dccm_req @[lsu_lsc_ctl.scala 193:22] + dma_pkt_d.bits.dma <= UInt<1>("h01") @[lsu_lsc_ctl.scala 194:27] + dma_pkt_d.bits.store <= io.dma_lsc_ctl.dma_mem_write @[lsu_lsc_ctl.scala 195:27] + node _T_113 = not(io.dma_lsc_ctl.dma_mem_write) @[lsu_lsc_ctl.scala 196:30] + dma_pkt_d.bits.load <= _T_113 @[lsu_lsc_ctl.scala 196:27] + node _T_114 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 197:56] + node _T_115 = eq(_T_114, UInt<3>("h00")) @[lsu_lsc_ctl.scala 197:62] + dma_pkt_d.bits.by <= _T_115 @[lsu_lsc_ctl.scala 197:27] + node _T_116 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 198:56] + node _T_117 = eq(_T_116, UInt<3>("h01")) @[lsu_lsc_ctl.scala 198:62] + dma_pkt_d.bits.half <= _T_117 @[lsu_lsc_ctl.scala 198:27] + node _T_118 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 199:56] + node _T_119 = eq(_T_118, UInt<3>("h02")) @[lsu_lsc_ctl.scala 199:62] + dma_pkt_d.bits.word <= _T_119 @[lsu_lsc_ctl.scala 199:27] + node _T_120 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 200:56] + node _T_121 = eq(_T_120, UInt<3>("h03")) @[lsu_lsc_ctl.scala 200:62] + dma_pkt_d.bits.dword <= _T_121 @[lsu_lsc_ctl.scala 200:27] + dma_pkt_d.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 201:39] + dma_pkt_d.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 202:39] + dma_pkt_d.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 203:39] wire lsu_ld_datafn_r : UInt<32> lsu_ld_datafn_r <= UInt<32>("h00") wire lsu_ld_datafn_corr_r : UInt<32> lsu_ld_datafn_corr_r <= UInt<32>("h00") wire lsu_ld_datafn_m : UInt<32> lsu_ld_datafn_m <= UInt<32>("h00") - node _T_122 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[lsu_lsc_ctl.scala 208:50] - node _T_123 = mux(_T_122, io.lsu_p, dma_pkt_d) @[lsu_lsc_ctl.scala 208:26] - io.lsu_pkt_d.bits.store_data_bypass_m <= _T_123.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 208:20] - io.lsu_pkt_d.bits.load_ldst_bypass_d <= _T_123.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 208:20] - io.lsu_pkt_d.bits.store_data_bypass_d <= _T_123.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 208:20] - io.lsu_pkt_d.bits.dma <= _T_123.bits.dma @[lsu_lsc_ctl.scala 208:20] - io.lsu_pkt_d.bits.unsign <= _T_123.bits.unsign @[lsu_lsc_ctl.scala 208:20] - io.lsu_pkt_d.bits.store <= _T_123.bits.store @[lsu_lsc_ctl.scala 208:20] - io.lsu_pkt_d.bits.load <= _T_123.bits.load @[lsu_lsc_ctl.scala 208:20] - io.lsu_pkt_d.bits.dword <= _T_123.bits.dword @[lsu_lsc_ctl.scala 208:20] - io.lsu_pkt_d.bits.word <= _T_123.bits.word @[lsu_lsc_ctl.scala 208:20] - io.lsu_pkt_d.bits.half <= _T_123.bits.half @[lsu_lsc_ctl.scala 208:20] - io.lsu_pkt_d.bits.by <= _T_123.bits.by @[lsu_lsc_ctl.scala 208:20] - io.lsu_pkt_d.bits.fast_int <= _T_123.bits.fast_int @[lsu_lsc_ctl.scala 208:20] - io.lsu_pkt_d.valid <= _T_123.valid @[lsu_lsc_ctl.scala 208:20] - lsu_pkt_m_in.bits.store_data_bypass_m <= io.lsu_pkt_d.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 209:20] - lsu_pkt_m_in.bits.load_ldst_bypass_d <= io.lsu_pkt_d.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 209:20] - lsu_pkt_m_in.bits.store_data_bypass_d <= io.lsu_pkt_d.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 209:20] - lsu_pkt_m_in.bits.dma <= io.lsu_pkt_d.bits.dma @[lsu_lsc_ctl.scala 209:20] - lsu_pkt_m_in.bits.unsign <= io.lsu_pkt_d.bits.unsign @[lsu_lsc_ctl.scala 209:20] - lsu_pkt_m_in.bits.store <= io.lsu_pkt_d.bits.store @[lsu_lsc_ctl.scala 209:20] - lsu_pkt_m_in.bits.load <= io.lsu_pkt_d.bits.load @[lsu_lsc_ctl.scala 209:20] - lsu_pkt_m_in.bits.dword <= io.lsu_pkt_d.bits.dword @[lsu_lsc_ctl.scala 209:20] - lsu_pkt_m_in.bits.word <= io.lsu_pkt_d.bits.word @[lsu_lsc_ctl.scala 209:20] - lsu_pkt_m_in.bits.half <= io.lsu_pkt_d.bits.half @[lsu_lsc_ctl.scala 209:20] - lsu_pkt_m_in.bits.by <= io.lsu_pkt_d.bits.by @[lsu_lsc_ctl.scala 209:20] - lsu_pkt_m_in.bits.fast_int <= io.lsu_pkt_d.bits.fast_int @[lsu_lsc_ctl.scala 209:20] - lsu_pkt_m_in.valid <= io.lsu_pkt_d.valid @[lsu_lsc_ctl.scala 209:20] - lsu_pkt_r_in.bits.store_data_bypass_m <= io.lsu_pkt_m.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 210:20] - lsu_pkt_r_in.bits.load_ldst_bypass_d <= io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 210:20] - lsu_pkt_r_in.bits.store_data_bypass_d <= io.lsu_pkt_m.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 210:20] - lsu_pkt_r_in.bits.dma <= io.lsu_pkt_m.bits.dma @[lsu_lsc_ctl.scala 210:20] - lsu_pkt_r_in.bits.unsign <= io.lsu_pkt_m.bits.unsign @[lsu_lsc_ctl.scala 210:20] - lsu_pkt_r_in.bits.store <= io.lsu_pkt_m.bits.store @[lsu_lsc_ctl.scala 210:20] - lsu_pkt_r_in.bits.load <= io.lsu_pkt_m.bits.load @[lsu_lsc_ctl.scala 210:20] - lsu_pkt_r_in.bits.dword <= io.lsu_pkt_m.bits.dword @[lsu_lsc_ctl.scala 210:20] - lsu_pkt_r_in.bits.word <= io.lsu_pkt_m.bits.word @[lsu_lsc_ctl.scala 210:20] - lsu_pkt_r_in.bits.half <= io.lsu_pkt_m.bits.half @[lsu_lsc_ctl.scala 210:20] - lsu_pkt_r_in.bits.by <= io.lsu_pkt_m.bits.by @[lsu_lsc_ctl.scala 210:20] - lsu_pkt_r_in.bits.fast_int <= io.lsu_pkt_m.bits.fast_int @[lsu_lsc_ctl.scala 210:20] - lsu_pkt_r_in.valid <= io.lsu_pkt_m.valid @[lsu_lsc_ctl.scala 210:20] - node _T_124 = eq(io.lsu_p.bits.fast_int, UInt<1>("h00")) @[lsu_lsc_ctl.scala 212:64] - node _T_125 = and(io.flush_m_up, _T_124) @[lsu_lsc_ctl.scala 212:61] - node _T_126 = eq(_T_125, UInt<1>("h00")) @[lsu_lsc_ctl.scala 212:45] - node _T_127 = and(io.lsu_p.valid, _T_126) @[lsu_lsc_ctl.scala 212:43] - node _T_128 = or(_T_127, io.dma_lsc_ctl.dma_dccm_req) @[lsu_lsc_ctl.scala 212:90] - io.lsu_pkt_d.valid <= _T_128 @[lsu_lsc_ctl.scala 212:24] - node _T_129 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 213:68] - node _T_130 = and(io.flush_m_up, _T_129) @[lsu_lsc_ctl.scala 213:65] - node _T_131 = eq(_T_130, UInt<1>("h00")) @[lsu_lsc_ctl.scala 213:49] - node _T_132 = and(io.lsu_pkt_d.valid, _T_131) @[lsu_lsc_ctl.scala 213:47] - lsu_pkt_m_in.valid <= _T_132 @[lsu_lsc_ctl.scala 213:24] - node _T_133 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 214:68] - node _T_134 = and(io.flush_m_up, _T_133) @[lsu_lsc_ctl.scala 214:65] - node _T_135 = eq(_T_134, UInt<1>("h00")) @[lsu_lsc_ctl.scala 214:49] - node _T_136 = and(io.lsu_pkt_m.valid, _T_135) @[lsu_lsc_ctl.scala 214:47] - lsu_pkt_r_in.valid <= _T_136 @[lsu_lsc_ctl.scala 214:24] - wire _T_137 : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 216:91] - _T_137.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] - _T_137.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] - _T_137.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] - _T_137.bits.dma <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] - _T_137.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] - _T_137.bits.store <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] - _T_137.bits.load <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] - _T_137.bits.dword <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] - _T_137.bits.word <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] - _T_137.bits.half <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] - _T_137.bits.by <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] - _T_137.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] - _T_137.valid <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] - reg _T_138 : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, io.lsu_c1_m_clk with : (reset => (reset, _T_137)) @[lsu_lsc_ctl.scala 216:65] - _T_138.bits.store_data_bypass_m <= lsu_pkt_m_in.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 216:65] - _T_138.bits.load_ldst_bypass_d <= lsu_pkt_m_in.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 216:65] - _T_138.bits.store_data_bypass_d <= lsu_pkt_m_in.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 216:65] - _T_138.bits.dma <= lsu_pkt_m_in.bits.dma @[lsu_lsc_ctl.scala 216:65] - _T_138.bits.unsign <= lsu_pkt_m_in.bits.unsign @[lsu_lsc_ctl.scala 216:65] - _T_138.bits.store <= lsu_pkt_m_in.bits.store @[lsu_lsc_ctl.scala 216:65] - _T_138.bits.load <= lsu_pkt_m_in.bits.load @[lsu_lsc_ctl.scala 216:65] - _T_138.bits.dword <= lsu_pkt_m_in.bits.dword @[lsu_lsc_ctl.scala 216:65] - _T_138.bits.word <= lsu_pkt_m_in.bits.word @[lsu_lsc_ctl.scala 216:65] - _T_138.bits.half <= lsu_pkt_m_in.bits.half @[lsu_lsc_ctl.scala 216:65] - _T_138.bits.by <= lsu_pkt_m_in.bits.by @[lsu_lsc_ctl.scala 216:65] - _T_138.bits.fast_int <= lsu_pkt_m_in.bits.fast_int @[lsu_lsc_ctl.scala 216:65] - _T_138.valid <= lsu_pkt_m_in.valid @[lsu_lsc_ctl.scala 216:65] - io.lsu_pkt_m.bits.store_data_bypass_m <= _T_138.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 216:28] - io.lsu_pkt_m.bits.load_ldst_bypass_d <= _T_138.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 216:28] - io.lsu_pkt_m.bits.store_data_bypass_d <= _T_138.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 216:28] - io.lsu_pkt_m.bits.dma <= _T_138.bits.dma @[lsu_lsc_ctl.scala 216:28] - io.lsu_pkt_m.bits.unsign <= _T_138.bits.unsign @[lsu_lsc_ctl.scala 216:28] - io.lsu_pkt_m.bits.store <= _T_138.bits.store @[lsu_lsc_ctl.scala 216:28] - io.lsu_pkt_m.bits.load <= _T_138.bits.load @[lsu_lsc_ctl.scala 216:28] - io.lsu_pkt_m.bits.dword <= _T_138.bits.dword @[lsu_lsc_ctl.scala 216:28] - io.lsu_pkt_m.bits.word <= _T_138.bits.word @[lsu_lsc_ctl.scala 216:28] - io.lsu_pkt_m.bits.half <= _T_138.bits.half @[lsu_lsc_ctl.scala 216:28] - io.lsu_pkt_m.bits.by <= _T_138.bits.by @[lsu_lsc_ctl.scala 216:28] - io.lsu_pkt_m.bits.fast_int <= _T_138.bits.fast_int @[lsu_lsc_ctl.scala 216:28] - io.lsu_pkt_m.valid <= _T_138.valid @[lsu_lsc_ctl.scala 216:28] - wire _T_139 : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 217:91] - _T_139.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] - _T_139.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] - _T_139.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] - _T_139.bits.dma <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] - _T_139.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] - _T_139.bits.store <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] - _T_139.bits.load <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] - _T_139.bits.dword <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] - _T_139.bits.word <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] - _T_139.bits.half <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] - _T_139.bits.by <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] - _T_139.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] - _T_139.valid <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] - reg _T_140 : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, io.lsu_c1_r_clk with : (reset => (reset, _T_139)) @[lsu_lsc_ctl.scala 217:65] - _T_140.bits.store_data_bypass_m <= lsu_pkt_r_in.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 217:65] - _T_140.bits.load_ldst_bypass_d <= lsu_pkt_r_in.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 217:65] - _T_140.bits.store_data_bypass_d <= lsu_pkt_r_in.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 217:65] - _T_140.bits.dma <= lsu_pkt_r_in.bits.dma @[lsu_lsc_ctl.scala 217:65] - _T_140.bits.unsign <= lsu_pkt_r_in.bits.unsign @[lsu_lsc_ctl.scala 217:65] - _T_140.bits.store <= lsu_pkt_r_in.bits.store @[lsu_lsc_ctl.scala 217:65] - _T_140.bits.load <= lsu_pkt_r_in.bits.load @[lsu_lsc_ctl.scala 217:65] - _T_140.bits.dword <= lsu_pkt_r_in.bits.dword @[lsu_lsc_ctl.scala 217:65] - _T_140.bits.word <= lsu_pkt_r_in.bits.word @[lsu_lsc_ctl.scala 217:65] - _T_140.bits.half <= lsu_pkt_r_in.bits.half @[lsu_lsc_ctl.scala 217:65] - _T_140.bits.by <= lsu_pkt_r_in.bits.by @[lsu_lsc_ctl.scala 217:65] - _T_140.bits.fast_int <= lsu_pkt_r_in.bits.fast_int @[lsu_lsc_ctl.scala 217:65] - _T_140.valid <= lsu_pkt_r_in.valid @[lsu_lsc_ctl.scala 217:65] - io.lsu_pkt_r.bits.store_data_bypass_m <= _T_140.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 217:28] - io.lsu_pkt_r.bits.load_ldst_bypass_d <= _T_140.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 217:28] - io.lsu_pkt_r.bits.store_data_bypass_d <= _T_140.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 217:28] - io.lsu_pkt_r.bits.dma <= _T_140.bits.dma @[lsu_lsc_ctl.scala 217:28] - io.lsu_pkt_r.bits.unsign <= _T_140.bits.unsign @[lsu_lsc_ctl.scala 217:28] - io.lsu_pkt_r.bits.store <= _T_140.bits.store @[lsu_lsc_ctl.scala 217:28] - io.lsu_pkt_r.bits.load <= _T_140.bits.load @[lsu_lsc_ctl.scala 217:28] - io.lsu_pkt_r.bits.dword <= _T_140.bits.dword @[lsu_lsc_ctl.scala 217:28] - io.lsu_pkt_r.bits.word <= _T_140.bits.word @[lsu_lsc_ctl.scala 217:28] - io.lsu_pkt_r.bits.half <= _T_140.bits.half @[lsu_lsc_ctl.scala 217:28] - io.lsu_pkt_r.bits.by <= _T_140.bits.by @[lsu_lsc_ctl.scala 217:28] - io.lsu_pkt_r.bits.fast_int <= _T_140.bits.fast_int @[lsu_lsc_ctl.scala 217:28] - io.lsu_pkt_r.valid <= _T_140.valid @[lsu_lsc_ctl.scala 217:28] - reg _T_141 : UInt<1>, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 218:65] - _T_141 <= lsu_pkt_m_in.valid @[lsu_lsc_ctl.scala 218:65] - io.lsu_pkt_m.valid <= _T_141 @[lsu_lsc_ctl.scala 218:28] - reg _T_142 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 219:65] - _T_142 <= lsu_pkt_r_in.valid @[lsu_lsc_ctl.scala 219:65] - io.lsu_pkt_r.valid <= _T_142 @[lsu_lsc_ctl.scala 219:28] - node _T_143 = bits(io.dma_lsc_ctl.dma_mem_wdata, 63, 0) @[lsu_lsc_ctl.scala 221:59] - node _T_144 = bits(io.dma_lsc_ctl.dma_mem_addr, 2, 0) @[lsu_lsc_ctl.scala 221:100] + node _T_122 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[lsu_lsc_ctl.scala 209:50] + node _T_123 = mux(_T_122, io.lsu_p, dma_pkt_d) @[lsu_lsc_ctl.scala 209:26] + io.lsu_pkt_d.bits.store_data_bypass_m <= _T_123.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 209:20] + io.lsu_pkt_d.bits.load_ldst_bypass_d <= _T_123.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 209:20] + io.lsu_pkt_d.bits.store_data_bypass_d <= _T_123.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 209:20] + io.lsu_pkt_d.bits.dma <= _T_123.bits.dma @[lsu_lsc_ctl.scala 209:20] + io.lsu_pkt_d.bits.unsign <= _T_123.bits.unsign @[lsu_lsc_ctl.scala 209:20] + io.lsu_pkt_d.bits.store <= _T_123.bits.store @[lsu_lsc_ctl.scala 209:20] + io.lsu_pkt_d.bits.load <= _T_123.bits.load @[lsu_lsc_ctl.scala 209:20] + io.lsu_pkt_d.bits.dword <= _T_123.bits.dword @[lsu_lsc_ctl.scala 209:20] + io.lsu_pkt_d.bits.word <= _T_123.bits.word @[lsu_lsc_ctl.scala 209:20] + io.lsu_pkt_d.bits.half <= _T_123.bits.half @[lsu_lsc_ctl.scala 209:20] + io.lsu_pkt_d.bits.by <= _T_123.bits.by @[lsu_lsc_ctl.scala 209:20] + io.lsu_pkt_d.bits.stack <= _T_123.bits.stack @[lsu_lsc_ctl.scala 209:20] + io.lsu_pkt_d.bits.fast_int <= _T_123.bits.fast_int @[lsu_lsc_ctl.scala 209:20] + io.lsu_pkt_d.valid <= _T_123.valid @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.store_data_bypass_m <= io.lsu_pkt_d.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_m_in.bits.load_ldst_bypass_d <= io.lsu_pkt_d.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_m_in.bits.store_data_bypass_d <= io.lsu_pkt_d.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_m_in.bits.dma <= io.lsu_pkt_d.bits.dma @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_m_in.bits.unsign <= io.lsu_pkt_d.bits.unsign @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_m_in.bits.store <= io.lsu_pkt_d.bits.store @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_m_in.bits.load <= io.lsu_pkt_d.bits.load @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_m_in.bits.dword <= io.lsu_pkt_d.bits.dword @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_m_in.bits.word <= io.lsu_pkt_d.bits.word @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_m_in.bits.half <= io.lsu_pkt_d.bits.half @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_m_in.bits.by <= io.lsu_pkt_d.bits.by @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_m_in.bits.stack <= io.lsu_pkt_d.bits.stack @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_m_in.bits.fast_int <= io.lsu_pkt_d.bits.fast_int @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_m_in.valid <= io.lsu_pkt_d.valid @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.store_data_bypass_m <= io.lsu_pkt_m.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 211:20] + lsu_pkt_r_in.bits.load_ldst_bypass_d <= io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 211:20] + lsu_pkt_r_in.bits.store_data_bypass_d <= io.lsu_pkt_m.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 211:20] + lsu_pkt_r_in.bits.dma <= io.lsu_pkt_m.bits.dma @[lsu_lsc_ctl.scala 211:20] + lsu_pkt_r_in.bits.unsign <= io.lsu_pkt_m.bits.unsign @[lsu_lsc_ctl.scala 211:20] + lsu_pkt_r_in.bits.store <= io.lsu_pkt_m.bits.store @[lsu_lsc_ctl.scala 211:20] + lsu_pkt_r_in.bits.load <= io.lsu_pkt_m.bits.load @[lsu_lsc_ctl.scala 211:20] + lsu_pkt_r_in.bits.dword <= io.lsu_pkt_m.bits.dword @[lsu_lsc_ctl.scala 211:20] + lsu_pkt_r_in.bits.word <= io.lsu_pkt_m.bits.word @[lsu_lsc_ctl.scala 211:20] + lsu_pkt_r_in.bits.half <= io.lsu_pkt_m.bits.half @[lsu_lsc_ctl.scala 211:20] + lsu_pkt_r_in.bits.by <= io.lsu_pkt_m.bits.by @[lsu_lsc_ctl.scala 211:20] + lsu_pkt_r_in.bits.stack <= io.lsu_pkt_m.bits.stack @[lsu_lsc_ctl.scala 211:20] + lsu_pkt_r_in.bits.fast_int <= io.lsu_pkt_m.bits.fast_int @[lsu_lsc_ctl.scala 211:20] + lsu_pkt_r_in.valid <= io.lsu_pkt_m.valid @[lsu_lsc_ctl.scala 211:20] + node _T_124 = eq(io.lsu_p.bits.fast_int, UInt<1>("h00")) @[lsu_lsc_ctl.scala 213:64] + node _T_125 = and(io.flush_m_up, _T_124) @[lsu_lsc_ctl.scala 213:61] + node _T_126 = eq(_T_125, UInt<1>("h00")) @[lsu_lsc_ctl.scala 213:45] + node _T_127 = and(io.lsu_p.valid, _T_126) @[lsu_lsc_ctl.scala 213:43] + node _T_128 = or(_T_127, io.dma_lsc_ctl.dma_dccm_req) @[lsu_lsc_ctl.scala 213:90] + io.lsu_pkt_d.valid <= _T_128 @[lsu_lsc_ctl.scala 213:24] + node _T_129 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 214:68] + node _T_130 = and(io.flush_m_up, _T_129) @[lsu_lsc_ctl.scala 214:65] + node _T_131 = eq(_T_130, UInt<1>("h00")) @[lsu_lsc_ctl.scala 214:49] + node _T_132 = and(io.lsu_pkt_d.valid, _T_131) @[lsu_lsc_ctl.scala 214:47] + lsu_pkt_m_in.valid <= _T_132 @[lsu_lsc_ctl.scala 214:24] + node _T_133 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 215:68] + node _T_134 = and(io.flush_m_up, _T_133) @[lsu_lsc_ctl.scala 215:65] + node _T_135 = eq(_T_134, UInt<1>("h00")) @[lsu_lsc_ctl.scala 215:49] + node _T_136 = and(io.lsu_pkt_m.valid, _T_135) @[lsu_lsc_ctl.scala 215:47] + lsu_pkt_r_in.valid <= _T_136 @[lsu_lsc_ctl.scala 215:24] + wire _T_137 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 217:91] + _T_137.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_137.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_137.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_137.bits.dma <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_137.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_137.bits.store <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_137.bits.load <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_137.bits.dword <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_137.bits.word <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_137.bits.half <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_137.bits.by <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_137.bits.stack <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_137.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_137.valid <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + reg _T_138 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, io.lsu_c1_m_clk with : (reset => (reset, _T_137)) @[lsu_lsc_ctl.scala 217:65] + _T_138.bits.store_data_bypass_m <= lsu_pkt_m_in.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 217:65] + _T_138.bits.load_ldst_bypass_d <= lsu_pkt_m_in.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 217:65] + _T_138.bits.store_data_bypass_d <= lsu_pkt_m_in.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 217:65] + _T_138.bits.dma <= lsu_pkt_m_in.bits.dma @[lsu_lsc_ctl.scala 217:65] + _T_138.bits.unsign <= lsu_pkt_m_in.bits.unsign @[lsu_lsc_ctl.scala 217:65] + _T_138.bits.store <= lsu_pkt_m_in.bits.store @[lsu_lsc_ctl.scala 217:65] + _T_138.bits.load <= lsu_pkt_m_in.bits.load @[lsu_lsc_ctl.scala 217:65] + _T_138.bits.dword <= lsu_pkt_m_in.bits.dword @[lsu_lsc_ctl.scala 217:65] + _T_138.bits.word <= lsu_pkt_m_in.bits.word @[lsu_lsc_ctl.scala 217:65] + _T_138.bits.half <= lsu_pkt_m_in.bits.half @[lsu_lsc_ctl.scala 217:65] + _T_138.bits.by <= lsu_pkt_m_in.bits.by @[lsu_lsc_ctl.scala 217:65] + _T_138.bits.stack <= lsu_pkt_m_in.bits.stack @[lsu_lsc_ctl.scala 217:65] + _T_138.bits.fast_int <= lsu_pkt_m_in.bits.fast_int @[lsu_lsc_ctl.scala 217:65] + _T_138.valid <= lsu_pkt_m_in.valid @[lsu_lsc_ctl.scala 217:65] + io.lsu_pkt_m.bits.store_data_bypass_m <= _T_138.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_m.bits.load_ldst_bypass_d <= _T_138.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_m.bits.store_data_bypass_d <= _T_138.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_m.bits.dma <= _T_138.bits.dma @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_m.bits.unsign <= _T_138.bits.unsign @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_m.bits.store <= _T_138.bits.store @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_m.bits.load <= _T_138.bits.load @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_m.bits.dword <= _T_138.bits.dword @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_m.bits.word <= _T_138.bits.word @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_m.bits.half <= _T_138.bits.half @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_m.bits.by <= _T_138.bits.by @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_m.bits.stack <= _T_138.bits.stack @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_m.bits.fast_int <= _T_138.bits.fast_int @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_m.valid <= _T_138.valid @[lsu_lsc_ctl.scala 217:28] + wire _T_139 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 218:91] + _T_139.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91] + _T_139.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91] + _T_139.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91] + _T_139.bits.dma <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91] + _T_139.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91] + _T_139.bits.store <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91] + _T_139.bits.load <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91] + _T_139.bits.dword <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91] + _T_139.bits.word <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91] + _T_139.bits.half <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91] + _T_139.bits.by <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91] + _T_139.bits.stack <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91] + _T_139.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91] + _T_139.valid <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91] + reg _T_140 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, io.lsu_c1_r_clk with : (reset => (reset, _T_139)) @[lsu_lsc_ctl.scala 218:65] + _T_140.bits.store_data_bypass_m <= lsu_pkt_r_in.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 218:65] + _T_140.bits.load_ldst_bypass_d <= lsu_pkt_r_in.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 218:65] + _T_140.bits.store_data_bypass_d <= lsu_pkt_r_in.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 218:65] + _T_140.bits.dma <= lsu_pkt_r_in.bits.dma @[lsu_lsc_ctl.scala 218:65] + _T_140.bits.unsign <= lsu_pkt_r_in.bits.unsign @[lsu_lsc_ctl.scala 218:65] + _T_140.bits.store <= lsu_pkt_r_in.bits.store @[lsu_lsc_ctl.scala 218:65] + _T_140.bits.load <= lsu_pkt_r_in.bits.load @[lsu_lsc_ctl.scala 218:65] + _T_140.bits.dword <= lsu_pkt_r_in.bits.dword @[lsu_lsc_ctl.scala 218:65] + _T_140.bits.word <= lsu_pkt_r_in.bits.word @[lsu_lsc_ctl.scala 218:65] + _T_140.bits.half <= lsu_pkt_r_in.bits.half @[lsu_lsc_ctl.scala 218:65] + _T_140.bits.by <= lsu_pkt_r_in.bits.by @[lsu_lsc_ctl.scala 218:65] + _T_140.bits.stack <= lsu_pkt_r_in.bits.stack @[lsu_lsc_ctl.scala 218:65] + _T_140.bits.fast_int <= lsu_pkt_r_in.bits.fast_int @[lsu_lsc_ctl.scala 218:65] + _T_140.valid <= lsu_pkt_r_in.valid @[lsu_lsc_ctl.scala 218:65] + io.lsu_pkt_r.bits.store_data_bypass_m <= _T_140.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 218:28] + io.lsu_pkt_r.bits.load_ldst_bypass_d <= _T_140.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 218:28] + io.lsu_pkt_r.bits.store_data_bypass_d <= _T_140.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 218:28] + io.lsu_pkt_r.bits.dma <= _T_140.bits.dma @[lsu_lsc_ctl.scala 218:28] + io.lsu_pkt_r.bits.unsign <= _T_140.bits.unsign @[lsu_lsc_ctl.scala 218:28] + io.lsu_pkt_r.bits.store <= _T_140.bits.store @[lsu_lsc_ctl.scala 218:28] + io.lsu_pkt_r.bits.load <= _T_140.bits.load @[lsu_lsc_ctl.scala 218:28] + io.lsu_pkt_r.bits.dword <= _T_140.bits.dword @[lsu_lsc_ctl.scala 218:28] + io.lsu_pkt_r.bits.word <= _T_140.bits.word @[lsu_lsc_ctl.scala 218:28] + io.lsu_pkt_r.bits.half <= _T_140.bits.half @[lsu_lsc_ctl.scala 218:28] + io.lsu_pkt_r.bits.by <= _T_140.bits.by @[lsu_lsc_ctl.scala 218:28] + io.lsu_pkt_r.bits.stack <= _T_140.bits.stack @[lsu_lsc_ctl.scala 218:28] + io.lsu_pkt_r.bits.fast_int <= _T_140.bits.fast_int @[lsu_lsc_ctl.scala 218:28] + io.lsu_pkt_r.valid <= _T_140.valid @[lsu_lsc_ctl.scala 218:28] + reg _T_141 : UInt<1>, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 219:65] + _T_141 <= lsu_pkt_m_in.valid @[lsu_lsc_ctl.scala 219:65] + io.lsu_pkt_m.valid <= _T_141 @[lsu_lsc_ctl.scala 219:28] + reg _T_142 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 220:65] + _T_142 <= lsu_pkt_r_in.valid @[lsu_lsc_ctl.scala 220:65] + io.lsu_pkt_r.valid <= _T_142 @[lsu_lsc_ctl.scala 220:28] + node _T_143 = bits(io.dma_lsc_ctl.dma_mem_wdata, 63, 0) @[lsu_lsc_ctl.scala 222:59] + node _T_144 = bits(io.dma_lsc_ctl.dma_mem_addr, 2, 0) @[lsu_lsc_ctl.scala 222:100] node _T_145 = cat(_T_144, UInt<3>("h00")) @[Cat.scala 29:58] - node dma_mem_wdata_shifted = dshr(_T_143, _T_145) @[lsu_lsc_ctl.scala 221:66] - node _T_146 = bits(io.dma_lsc_ctl.dma_dccm_req, 0, 0) @[lsu_lsc_ctl.scala 222:63] - node _T_147 = bits(dma_mem_wdata_shifted, 31, 0) @[lsu_lsc_ctl.scala 222:91] - node _T_148 = bits(io.lsu_exu.exu_lsu_rs2_d, 31, 0) @[lsu_lsc_ctl.scala 222:122] - node store_data_d = mux(_T_146, _T_147, _T_148) @[lsu_lsc_ctl.scala 222:34] - node _T_149 = bits(io.lsu_pkt_d.bits.store_data_bypass_d, 0, 0) @[lsu_lsc_ctl.scala 223:73] - node _T_150 = bits(io.lsu_result_m, 31, 0) @[lsu_lsc_ctl.scala 223:95] - node _T_151 = bits(store_data_d, 31, 0) @[lsu_lsc_ctl.scala 223:114] - node store_data_m_in = mux(_T_149, _T_150, _T_151) @[lsu_lsc_ctl.scala 223:34] - reg store_data_pre_m : UInt, io.lsu_store_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 225:72] - store_data_pre_m <= store_data_m_in @[lsu_lsc_ctl.scala 225:72] - reg _T_152 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 226:62] - _T_152 <= io.lsu_addr_d @[lsu_lsc_ctl.scala 226:62] - io.lsu_addr_m <= _T_152 @[lsu_lsc_ctl.scala 226:24] - reg _T_153 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 227:62] - _T_153 <= io.lsu_addr_m @[lsu_lsc_ctl.scala 227:62] - io.lsu_addr_r <= _T_153 @[lsu_lsc_ctl.scala 227:24] + node dma_mem_wdata_shifted = dshr(_T_143, _T_145) @[lsu_lsc_ctl.scala 222:66] + node _T_146 = bits(io.dma_lsc_ctl.dma_dccm_req, 0, 0) @[lsu_lsc_ctl.scala 223:63] + node _T_147 = bits(dma_mem_wdata_shifted, 31, 0) @[lsu_lsc_ctl.scala 223:91] + node _T_148 = bits(io.lsu_exu.exu_lsu_rs2_d, 31, 0) @[lsu_lsc_ctl.scala 223:122] + node store_data_d = mux(_T_146, _T_147, _T_148) @[lsu_lsc_ctl.scala 223:34] + node _T_149 = bits(io.lsu_pkt_d.bits.store_data_bypass_d, 0, 0) @[lsu_lsc_ctl.scala 224:73] + node _T_150 = bits(io.lsu_result_m, 31, 0) @[lsu_lsc_ctl.scala 224:95] + node _T_151 = bits(store_data_d, 31, 0) @[lsu_lsc_ctl.scala 224:114] + node store_data_m_in = mux(_T_149, _T_150, _T_151) @[lsu_lsc_ctl.scala 224:34] + reg store_data_pre_m : UInt, io.lsu_store_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 226:72] + store_data_pre_m <= store_data_m_in @[lsu_lsc_ctl.scala 226:72] + reg _T_152 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 227:62] + _T_152 <= io.lsu_addr_d @[lsu_lsc_ctl.scala 227:62] + io.lsu_addr_m <= _T_152 @[lsu_lsc_ctl.scala 227:24] + reg _T_153 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 228:62] + _T_153 <= io.lsu_addr_m @[lsu_lsc_ctl.scala 228:62] + io.lsu_addr_r <= _T_153 @[lsu_lsc_ctl.scala 228:24] node _T_154 = bits(io.ldst_dual_m, 0, 0) @[lib.scala 8:44] - node _T_155 = bits(io.lsu_addr_m, 31, 3) @[lsu_lsc_ctl.scala 228:71] - node _T_156 = mux(_T_154, end_addr_pre_m, _T_155) @[lsu_lsc_ctl.scala 228:27] - node _T_157 = bits(io.end_addr_d, 2, 0) @[lsu_lsc_ctl.scala 228:128] - reg _T_158 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 228:114] - _T_158 <= _T_157 @[lsu_lsc_ctl.scala 228:114] + node _T_155 = bits(io.lsu_addr_m, 31, 3) @[lsu_lsc_ctl.scala 229:71] + node _T_156 = mux(_T_154, end_addr_pre_m, _T_155) @[lsu_lsc_ctl.scala 229:27] + node _T_157 = bits(io.end_addr_d, 2, 0) @[lsu_lsc_ctl.scala 229:128] + reg _T_158 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 229:114] + _T_158 <= _T_157 @[lsu_lsc_ctl.scala 229:114] node _T_159 = cat(_T_156, _T_158) @[Cat.scala 29:58] - io.end_addr_m <= _T_159 @[lsu_lsc_ctl.scala 228:17] + io.end_addr_m <= _T_159 @[lsu_lsc_ctl.scala 229:17] node _T_160 = bits(io.ldst_dual_r, 0, 0) @[lib.scala 8:44] - node _T_161 = bits(io.lsu_addr_r, 31, 3) @[lsu_lsc_ctl.scala 229:71] - node _T_162 = mux(_T_160, end_addr_pre_r, _T_161) @[lsu_lsc_ctl.scala 229:27] - node _T_163 = bits(io.end_addr_m, 2, 0) @[lsu_lsc_ctl.scala 229:128] - reg _T_164 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 229:114] - _T_164 <= _T_163 @[lsu_lsc_ctl.scala 229:114] + node _T_161 = bits(io.lsu_addr_r, 31, 3) @[lsu_lsc_ctl.scala 230:71] + node _T_162 = mux(_T_160, end_addr_pre_r, _T_161) @[lsu_lsc_ctl.scala 230:27] + node _T_163 = bits(io.end_addr_m, 2, 0) @[lsu_lsc_ctl.scala 230:128] + reg _T_164 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 230:114] + _T_164 <= _T_163 @[lsu_lsc_ctl.scala 230:114] node _T_165 = cat(_T_162, _T_164) @[Cat.scala 29:58] - io.end_addr_r <= _T_165 @[lsu_lsc_ctl.scala 229:17] - node _T_166 = bits(io.end_addr_d, 31, 3) @[lsu_lsc_ctl.scala 230:41] - node _T_167 = and(io.lsu_pkt_d.valid, io.ldst_dual_d) @[lsu_lsc_ctl.scala 230:69] - node _T_168 = or(_T_167, io.clk_override) @[lsu_lsc_ctl.scala 230:87] + io.end_addr_r <= _T_165 @[lsu_lsc_ctl.scala 230:17] + node _T_166 = bits(io.end_addr_d, 31, 3) @[lsu_lsc_ctl.scala 231:41] + node _T_167 = and(io.lsu_pkt_d.valid, io.ldst_dual_d) @[lsu_lsc_ctl.scala 231:69] + node _T_168 = or(_T_167, io.clk_override) @[lsu_lsc_ctl.scala 231:87] node _T_169 = bits(_T_168, 0, 0) @[lib.scala 8:44] node _T_170 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44] inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 377:23] @@ -794,10 +805,10 @@ circuit lsu_lsc_ctl : rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 381:24] reg _T_171 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 383:16] _T_171 <= _T_166 @[lib.scala 383:16] - end_addr_pre_m <= _T_171 @[lsu_lsc_ctl.scala 230:18] - node _T_172 = bits(io.end_addr_m, 31, 3) @[lsu_lsc_ctl.scala 231:41] - node _T_173 = and(io.lsu_pkt_m.valid, io.ldst_dual_m) @[lsu_lsc_ctl.scala 231:69] - node _T_174 = or(_T_173, io.clk_override) @[lsu_lsc_ctl.scala 231:87] + end_addr_pre_m <= _T_171 @[lsu_lsc_ctl.scala 231:18] + node _T_172 = bits(io.end_addr_m, 31, 3) @[lsu_lsc_ctl.scala 232:41] + node _T_173 = and(io.lsu_pkt_m.valid, io.ldst_dual_m) @[lsu_lsc_ctl.scala 232:69] + node _T_174 = or(_T_173, io.clk_override) @[lsu_lsc_ctl.scala 232:87] node _T_175 = bits(_T_174, 0, 0) @[lib.scala 8:44] node _T_176 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44] inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 377:23] @@ -808,25 +819,25 @@ circuit lsu_lsc_ctl : rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 381:24] reg _T_177 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 383:16] _T_177 <= _T_172 @[lib.scala 383:16] - end_addr_pre_r <= _T_177 @[lsu_lsc_ctl.scala 231:18] - reg _T_178 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 232:62] - _T_178 <= io.addr_in_dccm_d @[lsu_lsc_ctl.scala 232:62] - io.addr_in_dccm_m <= _T_178 @[lsu_lsc_ctl.scala 232:24] - reg _T_179 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 233:62] - _T_179 <= io.addr_in_dccm_m @[lsu_lsc_ctl.scala 233:62] - io.addr_in_dccm_r <= _T_179 @[lsu_lsc_ctl.scala 233:24] - reg _T_180 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 234:62] - _T_180 <= io.addr_in_pic_d @[lsu_lsc_ctl.scala 234:62] - io.addr_in_pic_m <= _T_180 @[lsu_lsc_ctl.scala 234:24] - reg _T_181 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 235:62] - _T_181 <= io.addr_in_pic_m @[lsu_lsc_ctl.scala 235:62] - io.addr_in_pic_r <= _T_181 @[lsu_lsc_ctl.scala 235:24] - reg _T_182 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 236:62] - _T_182 <= addrcheck.io.addr_external_d @[lsu_lsc_ctl.scala 236:62] - io.addr_external_m <= _T_182 @[lsu_lsc_ctl.scala 236:24] - reg addr_external_r : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 237:66] - addr_external_r <= io.addr_external_m @[lsu_lsc_ctl.scala 237:66] - node _T_183 = or(io.addr_external_m, io.clk_override) @[lsu_lsc_ctl.scala 238:77] + end_addr_pre_r <= _T_177 @[lsu_lsc_ctl.scala 232:18] + reg _T_178 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 233:62] + _T_178 <= io.addr_in_dccm_d @[lsu_lsc_ctl.scala 233:62] + io.addr_in_dccm_m <= _T_178 @[lsu_lsc_ctl.scala 233:24] + reg _T_179 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 234:62] + _T_179 <= io.addr_in_dccm_m @[lsu_lsc_ctl.scala 234:62] + io.addr_in_dccm_r <= _T_179 @[lsu_lsc_ctl.scala 234:24] + reg _T_180 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 235:62] + _T_180 <= io.addr_in_pic_d @[lsu_lsc_ctl.scala 235:62] + io.addr_in_pic_m <= _T_180 @[lsu_lsc_ctl.scala 235:24] + reg _T_181 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 236:62] + _T_181 <= io.addr_in_pic_m @[lsu_lsc_ctl.scala 236:62] + io.addr_in_pic_r <= _T_181 @[lsu_lsc_ctl.scala 236:24] + reg _T_182 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 237:62] + _T_182 <= addrcheck.io.addr_external_d @[lsu_lsc_ctl.scala 237:62] + io.addr_external_m <= _T_182 @[lsu_lsc_ctl.scala 237:24] + reg addr_external_r : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 238:66] + addr_external_r <= io.addr_external_m @[lsu_lsc_ctl.scala 238:66] + node _T_183 = or(io.addr_external_m, io.clk_override) @[lsu_lsc_ctl.scala 239:77] node _T_184 = bits(_T_183, 0, 0) @[lib.scala 8:44] node _T_185 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44] inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 377:23] @@ -837,111 +848,111 @@ circuit lsu_lsc_ctl : rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 381:24] reg bus_read_data_r : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 383:16] bus_read_data_r <= io.bus_read_data_m @[lib.scala 383:16] - node _T_186 = bits(io.lsu_ld_data_corr_r, 31, 1) @[lsu_lsc_ctl.scala 241:52] - io.lsu_fir_addr <= _T_186 @[lsu_lsc_ctl.scala 241:28] - io.lsu_addr_d <= full_addr_d @[lsu_lsc_ctl.scala 243:28] - node _T_187 = or(io.lsu_pkt_r.bits.store, io.lsu_pkt_r.bits.load) @[lsu_lsc_ctl.scala 245:68] - node _T_188 = and(io.lsu_pkt_r.valid, _T_187) @[lsu_lsc_ctl.scala 245:41] - node _T_189 = eq(io.flush_r, UInt<1>("h00")) @[lsu_lsc_ctl.scala 245:96] - node _T_190 = and(_T_188, _T_189) @[lsu_lsc_ctl.scala 245:94] - node _T_191 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 245:110] - node _T_192 = and(_T_190, _T_191) @[lsu_lsc_ctl.scala 245:108] - io.lsu_commit_r <= _T_192 @[lsu_lsc_ctl.scala 245:19] - node _T_193 = bits(io.picm_mask_data_m, 31, 0) @[lsu_lsc_ctl.scala 246:52] - node _T_194 = eq(io.addr_in_pic_m, UInt<1>("h00")) @[lsu_lsc_ctl.scala 246:69] + node _T_186 = bits(io.lsu_ld_data_corr_r, 31, 1) @[lsu_lsc_ctl.scala 242:52] + io.lsu_fir_addr <= _T_186 @[lsu_lsc_ctl.scala 242:28] + io.lsu_addr_d <= full_addr_d @[lsu_lsc_ctl.scala 244:28] + node _T_187 = or(io.lsu_pkt_r.bits.store, io.lsu_pkt_r.bits.load) @[lsu_lsc_ctl.scala 246:68] + node _T_188 = and(io.lsu_pkt_r.valid, _T_187) @[lsu_lsc_ctl.scala 246:41] + node _T_189 = eq(io.flush_r, UInt<1>("h00")) @[lsu_lsc_ctl.scala 246:96] + node _T_190 = and(_T_188, _T_189) @[lsu_lsc_ctl.scala 246:94] + node _T_191 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 246:110] + node _T_192 = and(_T_190, _T_191) @[lsu_lsc_ctl.scala 246:108] + io.lsu_commit_r <= _T_192 @[lsu_lsc_ctl.scala 246:19] + node _T_193 = bits(io.picm_mask_data_m, 31, 0) @[lsu_lsc_ctl.scala 247:52] + node _T_194 = eq(io.addr_in_pic_m, UInt<1>("h00")) @[lsu_lsc_ctl.scala 247:69] node _T_195 = bits(_T_194, 0, 0) @[Bitwise.scala 72:15] node _T_196 = mux(_T_195, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_197 = or(_T_193, _T_196) @[lsu_lsc_ctl.scala 246:59] - node _T_198 = bits(io.lsu_pkt_m.bits.store_data_bypass_m, 0, 0) @[lsu_lsc_ctl.scala 246:133] - node _T_199 = mux(_T_198, io.lsu_result_m, store_data_pre_m) @[lsu_lsc_ctl.scala 246:94] - node _T_200 = and(_T_197, _T_199) @[lsu_lsc_ctl.scala 246:89] - io.store_data_m <= _T_200 @[lsu_lsc_ctl.scala 246:29] - node _T_201 = bits(io.addr_external_m, 0, 0) @[lsu_lsc_ctl.scala 267:53] - node _T_202 = mux(_T_201, io.bus_read_data_m, io.lsu_ld_data_m) @[lsu_lsc_ctl.scala 267:33] - lsu_ld_datafn_m <= _T_202 @[lsu_lsc_ctl.scala 267:27] - node _T_203 = eq(addr_external_r, UInt<1>("h01")) @[lsu_lsc_ctl.scala 268:49] - node _T_204 = mux(_T_203, bus_read_data_r, io.lsu_ld_data_corr_r) @[lsu_lsc_ctl.scala 268:33] - lsu_ld_datafn_corr_r <= _T_204 @[lsu_lsc_ctl.scala 268:27] - node _T_205 = and(io.lsu_pkt_m.bits.unsign, io.lsu_pkt_m.bits.by) @[lsu_lsc_ctl.scala 269:66] + node _T_197 = or(_T_193, _T_196) @[lsu_lsc_ctl.scala 247:59] + node _T_198 = bits(io.lsu_pkt_m.bits.store_data_bypass_m, 0, 0) @[lsu_lsc_ctl.scala 247:133] + node _T_199 = mux(_T_198, io.lsu_result_m, store_data_pre_m) @[lsu_lsc_ctl.scala 247:94] + node _T_200 = and(_T_197, _T_199) @[lsu_lsc_ctl.scala 247:89] + io.store_data_m <= _T_200 @[lsu_lsc_ctl.scala 247:29] + node _T_201 = bits(io.addr_external_m, 0, 0) @[lsu_lsc_ctl.scala 268:53] + node _T_202 = mux(_T_201, io.bus_read_data_m, io.lsu_ld_data_m) @[lsu_lsc_ctl.scala 268:33] + lsu_ld_datafn_m <= _T_202 @[lsu_lsc_ctl.scala 268:27] + node _T_203 = eq(addr_external_r, UInt<1>("h01")) @[lsu_lsc_ctl.scala 269:49] + node _T_204 = mux(_T_203, bus_read_data_r, io.lsu_ld_data_corr_r) @[lsu_lsc_ctl.scala 269:33] + lsu_ld_datafn_corr_r <= _T_204 @[lsu_lsc_ctl.scala 269:27] + node _T_205 = and(io.lsu_pkt_m.bits.unsign, io.lsu_pkt_m.bits.by) @[lsu_lsc_ctl.scala 270:66] node _T_206 = bits(_T_205, 0, 0) @[Bitwise.scala 72:15] node _T_207 = mux(_T_206, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_208 = bits(lsu_ld_datafn_m, 7, 0) @[lsu_lsc_ctl.scala 269:125] + node _T_208 = bits(lsu_ld_datafn_m, 7, 0) @[lsu_lsc_ctl.scala 270:125] node _T_209 = cat(UInt<24>("h00"), _T_208) @[Cat.scala 29:58] - node _T_210 = and(_T_207, _T_209) @[lsu_lsc_ctl.scala 269:94] - node _T_211 = and(io.lsu_pkt_m.bits.unsign, io.lsu_pkt_m.bits.half) @[lsu_lsc_ctl.scala 270:43] + node _T_210 = and(_T_207, _T_209) @[lsu_lsc_ctl.scala 270:94] + node _T_211 = and(io.lsu_pkt_m.bits.unsign, io.lsu_pkt_m.bits.half) @[lsu_lsc_ctl.scala 271:43] node _T_212 = bits(_T_211, 0, 0) @[Bitwise.scala 72:15] node _T_213 = mux(_T_212, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_214 = bits(lsu_ld_datafn_m, 15, 0) @[lsu_lsc_ctl.scala 270:102] + node _T_214 = bits(lsu_ld_datafn_m, 15, 0) @[lsu_lsc_ctl.scala 271:102] node _T_215 = cat(UInt<16>("h00"), _T_214) @[Cat.scala 29:58] - node _T_216 = and(_T_213, _T_215) @[lsu_lsc_ctl.scala 270:71] - node _T_217 = or(_T_210, _T_216) @[lsu_lsc_ctl.scala 269:133] - node _T_218 = eq(io.lsu_pkt_m.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 271:17] - node _T_219 = and(_T_218, io.lsu_pkt_m.bits.by) @[lsu_lsc_ctl.scala 271:43] + node _T_216 = and(_T_213, _T_215) @[lsu_lsc_ctl.scala 271:71] + node _T_217 = or(_T_210, _T_216) @[lsu_lsc_ctl.scala 270:133] + node _T_218 = eq(io.lsu_pkt_m.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 272:17] + node _T_219 = and(_T_218, io.lsu_pkt_m.bits.by) @[lsu_lsc_ctl.scala 272:43] node _T_220 = bits(_T_219, 0, 0) @[Bitwise.scala 72:15] node _T_221 = mux(_T_220, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_222 = bits(lsu_ld_datafn_m, 7, 7) @[lsu_lsc_ctl.scala 271:102] + node _T_222 = bits(lsu_ld_datafn_m, 7, 7) @[lsu_lsc_ctl.scala 272:102] node _T_223 = bits(_T_222, 0, 0) @[Bitwise.scala 72:15] node _T_224 = mux(_T_223, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12] - node _T_225 = bits(lsu_ld_datafn_m, 7, 0) @[lsu_lsc_ctl.scala 271:125] + node _T_225 = bits(lsu_ld_datafn_m, 7, 0) @[lsu_lsc_ctl.scala 272:125] node _T_226 = cat(_T_224, _T_225) @[Cat.scala 29:58] - node _T_227 = and(_T_221, _T_226) @[lsu_lsc_ctl.scala 271:71] - node _T_228 = or(_T_217, _T_227) @[lsu_lsc_ctl.scala 270:114] - node _T_229 = eq(io.lsu_pkt_m.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 272:17] - node _T_230 = and(_T_229, io.lsu_pkt_m.bits.half) @[lsu_lsc_ctl.scala 272:43] + node _T_227 = and(_T_221, _T_226) @[lsu_lsc_ctl.scala 272:71] + node _T_228 = or(_T_217, _T_227) @[lsu_lsc_ctl.scala 271:114] + node _T_229 = eq(io.lsu_pkt_m.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 273:17] + node _T_230 = and(_T_229, io.lsu_pkt_m.bits.half) @[lsu_lsc_ctl.scala 273:43] node _T_231 = bits(_T_230, 0, 0) @[Bitwise.scala 72:15] node _T_232 = mux(_T_231, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_233 = bits(lsu_ld_datafn_m, 15, 15) @[lsu_lsc_ctl.scala 272:101] + node _T_233 = bits(lsu_ld_datafn_m, 15, 15) @[lsu_lsc_ctl.scala 273:101] node _T_234 = bits(_T_233, 0, 0) @[Bitwise.scala 72:15] node _T_235 = mux(_T_234, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] - node _T_236 = bits(lsu_ld_datafn_m, 15, 0) @[lsu_lsc_ctl.scala 272:125] + node _T_236 = bits(lsu_ld_datafn_m, 15, 0) @[lsu_lsc_ctl.scala 273:125] node _T_237 = cat(_T_235, _T_236) @[Cat.scala 29:58] - node _T_238 = and(_T_232, _T_237) @[lsu_lsc_ctl.scala 272:71] - node _T_239 = or(_T_228, _T_238) @[lsu_lsc_ctl.scala 271:134] + node _T_238 = and(_T_232, _T_237) @[lsu_lsc_ctl.scala 273:71] + node _T_239 = or(_T_228, _T_238) @[lsu_lsc_ctl.scala 272:134] node _T_240 = bits(io.lsu_pkt_m.bits.word, 0, 0) @[Bitwise.scala 72:15] node _T_241 = mux(_T_240, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_242 = bits(lsu_ld_datafn_m, 31, 0) @[lsu_lsc_ctl.scala 273:60] - node _T_243 = and(_T_241, _T_242) @[lsu_lsc_ctl.scala 273:43] - node _T_244 = or(_T_239, _T_243) @[lsu_lsc_ctl.scala 272:134] - io.lsu_result_m <= _T_244 @[lsu_lsc_ctl.scala 269:27] - node _T_245 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 274:66] + node _T_242 = bits(lsu_ld_datafn_m, 31, 0) @[lsu_lsc_ctl.scala 274:60] + node _T_243 = and(_T_241, _T_242) @[lsu_lsc_ctl.scala 274:43] + node _T_244 = or(_T_239, _T_243) @[lsu_lsc_ctl.scala 273:134] + io.lsu_result_m <= _T_244 @[lsu_lsc_ctl.scala 270:27] + node _T_245 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 275:66] node _T_246 = bits(_T_245, 0, 0) @[Bitwise.scala 72:15] node _T_247 = mux(_T_246, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_248 = bits(lsu_ld_datafn_corr_r, 7, 0) @[lsu_lsc_ctl.scala 274:130] + node _T_248 = bits(lsu_ld_datafn_corr_r, 7, 0) @[lsu_lsc_ctl.scala 275:130] node _T_249 = cat(UInt<24>("h00"), _T_248) @[Cat.scala 29:58] - node _T_250 = and(_T_247, _T_249) @[lsu_lsc_ctl.scala 274:94] - node _T_251 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 275:43] + node _T_250 = and(_T_247, _T_249) @[lsu_lsc_ctl.scala 275:94] + node _T_251 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 276:43] node _T_252 = bits(_T_251, 0, 0) @[Bitwise.scala 72:15] node _T_253 = mux(_T_252, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_254 = bits(lsu_ld_datafn_corr_r, 15, 0) @[lsu_lsc_ctl.scala 275:107] + node _T_254 = bits(lsu_ld_datafn_corr_r, 15, 0) @[lsu_lsc_ctl.scala 276:107] node _T_255 = cat(UInt<16>("h00"), _T_254) @[Cat.scala 29:58] - node _T_256 = and(_T_253, _T_255) @[lsu_lsc_ctl.scala 275:71] - node _T_257 = or(_T_250, _T_256) @[lsu_lsc_ctl.scala 274:138] - node _T_258 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 276:17] - node _T_259 = and(_T_258, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 276:43] + node _T_256 = and(_T_253, _T_255) @[lsu_lsc_ctl.scala 276:71] + node _T_257 = or(_T_250, _T_256) @[lsu_lsc_ctl.scala 275:138] + node _T_258 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 277:17] + node _T_259 = and(_T_258, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 277:43] node _T_260 = bits(_T_259, 0, 0) @[Bitwise.scala 72:15] node _T_261 = mux(_T_260, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_262 = bits(lsu_ld_datafn_corr_r, 7, 7) @[lsu_lsc_ctl.scala 276:107] + node _T_262 = bits(lsu_ld_datafn_corr_r, 7, 7) @[lsu_lsc_ctl.scala 277:107] node _T_263 = bits(_T_262, 0, 0) @[Bitwise.scala 72:15] node _T_264 = mux(_T_263, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12] - node _T_265 = bits(lsu_ld_datafn_corr_r, 7, 0) @[lsu_lsc_ctl.scala 276:135] + node _T_265 = bits(lsu_ld_datafn_corr_r, 7, 0) @[lsu_lsc_ctl.scala 277:135] node _T_266 = cat(_T_264, _T_265) @[Cat.scala 29:58] - node _T_267 = and(_T_261, _T_266) @[lsu_lsc_ctl.scala 276:71] - node _T_268 = or(_T_257, _T_267) @[lsu_lsc_ctl.scala 275:119] - node _T_269 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 277:17] - node _T_270 = and(_T_269, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 277:43] + node _T_267 = and(_T_261, _T_266) @[lsu_lsc_ctl.scala 277:71] + node _T_268 = or(_T_257, _T_267) @[lsu_lsc_ctl.scala 276:119] + node _T_269 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 278:17] + node _T_270 = and(_T_269, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 278:43] node _T_271 = bits(_T_270, 0, 0) @[Bitwise.scala 72:15] node _T_272 = mux(_T_271, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_273 = bits(lsu_ld_datafn_corr_r, 15, 15) @[lsu_lsc_ctl.scala 277:106] + node _T_273 = bits(lsu_ld_datafn_corr_r, 15, 15) @[lsu_lsc_ctl.scala 278:106] node _T_274 = bits(_T_273, 0, 0) @[Bitwise.scala 72:15] node _T_275 = mux(_T_274, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] - node _T_276 = bits(lsu_ld_datafn_corr_r, 15, 0) @[lsu_lsc_ctl.scala 277:135] + node _T_276 = bits(lsu_ld_datafn_corr_r, 15, 0) @[lsu_lsc_ctl.scala 278:135] node _T_277 = cat(_T_275, _T_276) @[Cat.scala 29:58] - node _T_278 = and(_T_272, _T_277) @[lsu_lsc_ctl.scala 277:71] - node _T_279 = or(_T_268, _T_278) @[lsu_lsc_ctl.scala 276:144] + node _T_278 = and(_T_272, _T_277) @[lsu_lsc_ctl.scala 278:71] + node _T_279 = or(_T_268, _T_278) @[lsu_lsc_ctl.scala 277:144] node _T_280 = bits(io.lsu_pkt_r.bits.word, 0, 0) @[Bitwise.scala 72:15] node _T_281 = mux(_T_280, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_282 = bits(lsu_ld_datafn_corr_r, 31, 0) @[lsu_lsc_ctl.scala 278:65] - node _T_283 = and(_T_281, _T_282) @[lsu_lsc_ctl.scala 278:43] - node _T_284 = or(_T_279, _T_283) @[lsu_lsc_ctl.scala 277:144] - io.lsu_result_corr_r <= _T_284 @[lsu_lsc_ctl.scala 274:27] + node _T_282 = bits(lsu_ld_datafn_corr_r, 31, 0) @[lsu_lsc_ctl.scala 279:65] + node _T_283 = and(_T_281, _T_282) @[lsu_lsc_ctl.scala 279:43] + node _T_284 = or(_T_279, _T_283) @[lsu_lsc_ctl.scala 278:144] + io.lsu_result_corr_r <= _T_284 @[lsu_lsc_ctl.scala 275:27] diff --git a/lsu_lsc_ctl.v b/lsu_lsc_ctl.v index 0e21211e..a22bc1eb 100644 --- a/lsu_lsc_ctl.v +++ b/lsu_lsc_ctl.v @@ -228,6 +228,7 @@ module lsu_lsc_ctl( input [31:0] io_lsu_exu_exu_lsu_rs2_d, input io_lsu_p_valid, input io_lsu_p_bits_fast_int, + input io_lsu_p_bits_stack, input io_lsu_p_bits_by, input io_lsu_p_bits_half, input io_lsu_p_bits_word, @@ -279,6 +280,7 @@ module lsu_lsc_ctl( input [63:0] io_dma_lsc_ctl_dma_mem_wdata, output io_lsu_pkt_d_valid, output io_lsu_pkt_d_bits_fast_int, + output io_lsu_pkt_d_bits_stack, output io_lsu_pkt_d_bits_by, output io_lsu_pkt_d_bits_half, output io_lsu_pkt_d_bits_word, @@ -292,6 +294,7 @@ module lsu_lsc_ctl( output io_lsu_pkt_d_bits_store_data_bypass_m, output io_lsu_pkt_m_valid, output io_lsu_pkt_m_bits_fast_int, + output io_lsu_pkt_m_bits_stack, output io_lsu_pkt_m_bits_by, output io_lsu_pkt_m_bits_half, output io_lsu_pkt_m_bits_word, @@ -305,6 +308,7 @@ module lsu_lsc_ctl( output io_lsu_pkt_m_bits_store_data_bypass_m, output io_lsu_pkt_r_valid, output io_lsu_pkt_r_bits_fast_int, + output io_lsu_pkt_r_bits_stack, output io_lsu_pkt_r_bits_by, output io_lsu_pkt_r_bits_half, output io_lsu_pkt_r_bits_word, @@ -371,6 +375,8 @@ module lsu_lsc_ctl( reg [31:0] _RAND_49; reg [31:0] _RAND_50; reg [31:0] _RAND_51; + reg [31:0] _RAND_52; + reg [31:0] _RAND_53; `endif // RANDOMIZE_REG_INIT wire addrcheck_reset; // @[lsu_lsc_ctl.scala 118:25] wire addrcheck_io_lsu_c2_m_clk; // @[lsu_lsc_ctl.scala 118:25] @@ -476,126 +482,128 @@ module lsu_lsc_ctl( reg [31:0] _T_109_bits_addr; // @[lib.scala 393:16] reg _T_110; // @[lsu_lsc_ctl.scala 186:83] reg _T_111; // @[lsu_lsc_ctl.scala 187:67] - reg [1:0] _T_112; // @[lsu_lsc_ctl.scala 188:48] - wire dma_pkt_d_bits_load = ~io_dma_lsc_ctl_dma_mem_write; // @[lsu_lsc_ctl.scala 195:30] - wire dma_pkt_d_bits_by = io_dma_lsc_ctl_dma_mem_sz == 3'h0; // @[lsu_lsc_ctl.scala 196:62] - wire dma_pkt_d_bits_half = io_dma_lsc_ctl_dma_mem_sz == 3'h1; // @[lsu_lsc_ctl.scala 197:62] - wire dma_pkt_d_bits_word = io_dma_lsc_ctl_dma_mem_sz == 3'h2; // @[lsu_lsc_ctl.scala 198:62] - wire dma_pkt_d_bits_dword = io_dma_lsc_ctl_dma_mem_sz == 3'h3; // @[lsu_lsc_ctl.scala 199:62] - wire _T_124 = ~io_lsu_p_bits_fast_int; // @[lsu_lsc_ctl.scala 212:64] - wire _T_125 = io_flush_m_up & _T_124; // @[lsu_lsc_ctl.scala 212:61] - wire _T_126 = ~_T_125; // @[lsu_lsc_ctl.scala 212:45] - wire _T_127 = io_lsu_p_valid & _T_126; // @[lsu_lsc_ctl.scala 212:43] - wire _T_129 = ~io_lsu_pkt_d_bits_dma; // @[lsu_lsc_ctl.scala 213:68] - wire _T_130 = io_flush_m_up & _T_129; // @[lsu_lsc_ctl.scala 213:65] - wire _T_131 = ~_T_130; // @[lsu_lsc_ctl.scala 213:49] - wire _T_134 = io_flush_m_up & _T_78; // @[lsu_lsc_ctl.scala 214:65] - wire _T_135 = ~_T_134; // @[lsu_lsc_ctl.scala 214:49] - reg _T_138_bits_fast_int; // @[lsu_lsc_ctl.scala 216:65] - reg _T_138_bits_by; // @[lsu_lsc_ctl.scala 216:65] - reg _T_138_bits_half; // @[lsu_lsc_ctl.scala 216:65] - reg _T_138_bits_word; // @[lsu_lsc_ctl.scala 216:65] - reg _T_138_bits_dword; // @[lsu_lsc_ctl.scala 216:65] - reg _T_138_bits_load; // @[lsu_lsc_ctl.scala 216:65] - reg _T_138_bits_store; // @[lsu_lsc_ctl.scala 216:65] - reg _T_138_bits_unsign; // @[lsu_lsc_ctl.scala 216:65] - reg _T_138_bits_dma; // @[lsu_lsc_ctl.scala 216:65] - reg _T_138_bits_store_data_bypass_d; // @[lsu_lsc_ctl.scala 216:65] - reg _T_138_bits_load_ldst_bypass_d; // @[lsu_lsc_ctl.scala 216:65] - reg _T_138_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 216:65] - reg _T_140_bits_fast_int; // @[lsu_lsc_ctl.scala 217:65] - reg _T_140_bits_by; // @[lsu_lsc_ctl.scala 217:65] - reg _T_140_bits_half; // @[lsu_lsc_ctl.scala 217:65] - reg _T_140_bits_word; // @[lsu_lsc_ctl.scala 217:65] - reg _T_140_bits_dword; // @[lsu_lsc_ctl.scala 217:65] - reg _T_140_bits_load; // @[lsu_lsc_ctl.scala 217:65] - reg _T_140_bits_store; // @[lsu_lsc_ctl.scala 217:65] - reg _T_140_bits_unsign; // @[lsu_lsc_ctl.scala 217:65] - reg _T_140_bits_dma; // @[lsu_lsc_ctl.scala 217:65] - reg _T_140_bits_store_data_bypass_d; // @[lsu_lsc_ctl.scala 217:65] - reg _T_140_bits_load_ldst_bypass_d; // @[lsu_lsc_ctl.scala 217:65] - reg _T_140_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 217:65] - reg _T_141; // @[lsu_lsc_ctl.scala 218:65] - reg _T_142; // @[lsu_lsc_ctl.scala 219:65] + reg [1:0] _T_112; // @[lsu_lsc_ctl.scala 188:75] + wire dma_pkt_d_bits_load = ~io_dma_lsc_ctl_dma_mem_write; // @[lsu_lsc_ctl.scala 196:30] + wire dma_pkt_d_bits_by = io_dma_lsc_ctl_dma_mem_sz == 3'h0; // @[lsu_lsc_ctl.scala 197:62] + wire dma_pkt_d_bits_half = io_dma_lsc_ctl_dma_mem_sz == 3'h1; // @[lsu_lsc_ctl.scala 198:62] + wire dma_pkt_d_bits_word = io_dma_lsc_ctl_dma_mem_sz == 3'h2; // @[lsu_lsc_ctl.scala 199:62] + wire dma_pkt_d_bits_dword = io_dma_lsc_ctl_dma_mem_sz == 3'h3; // @[lsu_lsc_ctl.scala 200:62] + wire _T_124 = ~io_lsu_p_bits_fast_int; // @[lsu_lsc_ctl.scala 213:64] + wire _T_125 = io_flush_m_up & _T_124; // @[lsu_lsc_ctl.scala 213:61] + wire _T_126 = ~_T_125; // @[lsu_lsc_ctl.scala 213:45] + wire _T_127 = io_lsu_p_valid & _T_126; // @[lsu_lsc_ctl.scala 213:43] + wire _T_129 = ~io_lsu_pkt_d_bits_dma; // @[lsu_lsc_ctl.scala 214:68] + wire _T_130 = io_flush_m_up & _T_129; // @[lsu_lsc_ctl.scala 214:65] + wire _T_131 = ~_T_130; // @[lsu_lsc_ctl.scala 214:49] + wire _T_134 = io_flush_m_up & _T_78; // @[lsu_lsc_ctl.scala 215:65] + wire _T_135 = ~_T_134; // @[lsu_lsc_ctl.scala 215:49] + reg _T_138_bits_fast_int; // @[lsu_lsc_ctl.scala 217:65] + reg _T_138_bits_stack; // @[lsu_lsc_ctl.scala 217:65] + reg _T_138_bits_by; // @[lsu_lsc_ctl.scala 217:65] + reg _T_138_bits_half; // @[lsu_lsc_ctl.scala 217:65] + reg _T_138_bits_word; // @[lsu_lsc_ctl.scala 217:65] + reg _T_138_bits_dword; // @[lsu_lsc_ctl.scala 217:65] + reg _T_138_bits_load; // @[lsu_lsc_ctl.scala 217:65] + reg _T_138_bits_store; // @[lsu_lsc_ctl.scala 217:65] + reg _T_138_bits_unsign; // @[lsu_lsc_ctl.scala 217:65] + reg _T_138_bits_dma; // @[lsu_lsc_ctl.scala 217:65] + reg _T_138_bits_store_data_bypass_d; // @[lsu_lsc_ctl.scala 217:65] + reg _T_138_bits_load_ldst_bypass_d; // @[lsu_lsc_ctl.scala 217:65] + reg _T_138_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 217:65] + reg _T_140_bits_fast_int; // @[lsu_lsc_ctl.scala 218:65] + reg _T_140_bits_stack; // @[lsu_lsc_ctl.scala 218:65] + reg _T_140_bits_by; // @[lsu_lsc_ctl.scala 218:65] + reg _T_140_bits_half; // @[lsu_lsc_ctl.scala 218:65] + reg _T_140_bits_word; // @[lsu_lsc_ctl.scala 218:65] + reg _T_140_bits_dword; // @[lsu_lsc_ctl.scala 218:65] + reg _T_140_bits_load; // @[lsu_lsc_ctl.scala 218:65] + reg _T_140_bits_store; // @[lsu_lsc_ctl.scala 218:65] + reg _T_140_bits_unsign; // @[lsu_lsc_ctl.scala 218:65] + reg _T_140_bits_dma; // @[lsu_lsc_ctl.scala 218:65] + reg _T_140_bits_store_data_bypass_d; // @[lsu_lsc_ctl.scala 218:65] + reg _T_140_bits_load_ldst_bypass_d; // @[lsu_lsc_ctl.scala 218:65] + reg _T_140_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 218:65] + reg _T_141; // @[lsu_lsc_ctl.scala 219:65] + reg _T_142; // @[lsu_lsc_ctl.scala 220:65] wire [5:0] _T_145 = {io_dma_lsc_ctl_dma_mem_addr[2:0],3'h0}; // @[Cat.scala 29:58] - wire [63:0] dma_mem_wdata_shifted = io_dma_lsc_ctl_dma_mem_wdata >> _T_145; // @[lsu_lsc_ctl.scala 221:66] - reg [31:0] store_data_pre_m; // @[lsu_lsc_ctl.scala 225:72] - reg [31:0] _T_152; // @[lsu_lsc_ctl.scala 226:62] - reg [31:0] _T_153; // @[lsu_lsc_ctl.scala 227:62] + wire [63:0] dma_mem_wdata_shifted = io_dma_lsc_ctl_dma_mem_wdata >> _T_145; // @[lsu_lsc_ctl.scala 222:66] + reg [31:0] store_data_pre_m; // @[lsu_lsc_ctl.scala 226:72] + reg [31:0] _T_152; // @[lsu_lsc_ctl.scala 227:62] + reg [31:0] _T_153; // @[lsu_lsc_ctl.scala 228:62] reg [28:0] end_addr_pre_m; // @[lib.scala 383:16] - wire [28:0] _T_156 = io_ldst_dual_m ? end_addr_pre_m : io_lsu_addr_m[31:3]; // @[lsu_lsc_ctl.scala 228:27] - reg [2:0] _T_158; // @[lsu_lsc_ctl.scala 228:114] + wire [28:0] _T_156 = io_ldst_dual_m ? end_addr_pre_m : io_lsu_addr_m[31:3]; // @[lsu_lsc_ctl.scala 229:27] + reg [2:0] _T_158; // @[lsu_lsc_ctl.scala 229:114] reg [28:0] end_addr_pre_r; // @[lib.scala 383:16] - wire [28:0] _T_162 = io_ldst_dual_r ? end_addr_pre_r : io_lsu_addr_r[31:3]; // @[lsu_lsc_ctl.scala 229:27] - reg [2:0] _T_164; // @[lsu_lsc_ctl.scala 229:114] - wire _T_167 = io_lsu_pkt_d_valid & io_ldst_dual_d; // @[lsu_lsc_ctl.scala 230:69] - wire _T_173 = io_lsu_pkt_m_valid & io_ldst_dual_m; // @[lsu_lsc_ctl.scala 231:69] - reg _T_178; // @[lsu_lsc_ctl.scala 232:62] - reg _T_179; // @[lsu_lsc_ctl.scala 233:62] - reg _T_180; // @[lsu_lsc_ctl.scala 234:62] - reg _T_181; // @[lsu_lsc_ctl.scala 235:62] - reg _T_182; // @[lsu_lsc_ctl.scala 236:62] - reg addr_external_r; // @[lsu_lsc_ctl.scala 237:66] + wire [28:0] _T_162 = io_ldst_dual_r ? end_addr_pre_r : io_lsu_addr_r[31:3]; // @[lsu_lsc_ctl.scala 230:27] + reg [2:0] _T_164; // @[lsu_lsc_ctl.scala 230:114] + wire _T_167 = io_lsu_pkt_d_valid & io_ldst_dual_d; // @[lsu_lsc_ctl.scala 231:69] + wire _T_173 = io_lsu_pkt_m_valid & io_ldst_dual_m; // @[lsu_lsc_ctl.scala 232:69] + reg _T_178; // @[lsu_lsc_ctl.scala 233:62] + reg _T_179; // @[lsu_lsc_ctl.scala 234:62] + reg _T_180; // @[lsu_lsc_ctl.scala 235:62] + reg _T_181; // @[lsu_lsc_ctl.scala 236:62] + reg _T_182; // @[lsu_lsc_ctl.scala 237:62] + reg addr_external_r; // @[lsu_lsc_ctl.scala 238:66] reg [31:0] bus_read_data_r; // @[lib.scala 383:16] - wire _T_187 = io_lsu_pkt_r_bits_store | io_lsu_pkt_r_bits_load; // @[lsu_lsc_ctl.scala 245:68] - wire _T_188 = io_lsu_pkt_r_valid & _T_187; // @[lsu_lsc_ctl.scala 245:41] - wire _T_189 = ~io_flush_r; // @[lsu_lsc_ctl.scala 245:96] - wire _T_190 = _T_188 & _T_189; // @[lsu_lsc_ctl.scala 245:94] - wire _T_191 = ~io_lsu_pkt_r_bits_dma; // @[lsu_lsc_ctl.scala 245:110] - wire _T_194 = ~io_addr_in_pic_m; // @[lsu_lsc_ctl.scala 246:69] + wire _T_187 = io_lsu_pkt_r_bits_store | io_lsu_pkt_r_bits_load; // @[lsu_lsc_ctl.scala 246:68] + wire _T_188 = io_lsu_pkt_r_valid & _T_187; // @[lsu_lsc_ctl.scala 246:41] + wire _T_189 = ~io_flush_r; // @[lsu_lsc_ctl.scala 246:96] + wire _T_190 = _T_188 & _T_189; // @[lsu_lsc_ctl.scala 246:94] + wire _T_191 = ~io_lsu_pkt_r_bits_dma; // @[lsu_lsc_ctl.scala 246:110] + wire _T_194 = ~io_addr_in_pic_m; // @[lsu_lsc_ctl.scala 247:69] wire [31:0] _T_196 = _T_194 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_197 = io_picm_mask_data_m | _T_196; // @[lsu_lsc_ctl.scala 246:59] - wire [31:0] _T_199 = io_lsu_pkt_m_bits_store_data_bypass_m ? io_lsu_result_m : store_data_pre_m; // @[lsu_lsc_ctl.scala 246:94] - wire [31:0] lsu_ld_datafn_m = io_addr_external_m ? io_bus_read_data_m : io_lsu_ld_data_m; // @[lsu_lsc_ctl.scala 267:33] - wire [31:0] lsu_ld_datafn_corr_r = addr_external_r ? bus_read_data_r : io_lsu_ld_data_corr_r; // @[lsu_lsc_ctl.scala 268:33] - wire _T_205 = io_lsu_pkt_m_bits_unsign & io_lsu_pkt_m_bits_by; // @[lsu_lsc_ctl.scala 269:66] + wire [31:0] _T_197 = io_picm_mask_data_m | _T_196; // @[lsu_lsc_ctl.scala 247:59] + wire [31:0] _T_199 = io_lsu_pkt_m_bits_store_data_bypass_m ? io_lsu_result_m : store_data_pre_m; // @[lsu_lsc_ctl.scala 247:94] + wire [31:0] lsu_ld_datafn_m = io_addr_external_m ? io_bus_read_data_m : io_lsu_ld_data_m; // @[lsu_lsc_ctl.scala 268:33] + wire [31:0] lsu_ld_datafn_corr_r = addr_external_r ? bus_read_data_r : io_lsu_ld_data_corr_r; // @[lsu_lsc_ctl.scala 269:33] + wire _T_205 = io_lsu_pkt_m_bits_unsign & io_lsu_pkt_m_bits_by; // @[lsu_lsc_ctl.scala 270:66] wire [31:0] _T_207 = _T_205 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] wire [31:0] _T_209 = {24'h0,lsu_ld_datafn_m[7:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_210 = _T_207 & _T_209; // @[lsu_lsc_ctl.scala 269:94] - wire _T_211 = io_lsu_pkt_m_bits_unsign & io_lsu_pkt_m_bits_half; // @[lsu_lsc_ctl.scala 270:43] + wire [31:0] _T_210 = _T_207 & _T_209; // @[lsu_lsc_ctl.scala 270:94] + wire _T_211 = io_lsu_pkt_m_bits_unsign & io_lsu_pkt_m_bits_half; // @[lsu_lsc_ctl.scala 271:43] wire [31:0] _T_213 = _T_211 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] wire [31:0] _T_215 = {16'h0,lsu_ld_datafn_m[15:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_216 = _T_213 & _T_215; // @[lsu_lsc_ctl.scala 270:71] - wire [31:0] _T_217 = _T_210 | _T_216; // @[lsu_lsc_ctl.scala 269:133] - wire _T_218 = ~io_lsu_pkt_m_bits_unsign; // @[lsu_lsc_ctl.scala 271:17] - wire _T_219 = _T_218 & io_lsu_pkt_m_bits_by; // @[lsu_lsc_ctl.scala 271:43] + wire [31:0] _T_216 = _T_213 & _T_215; // @[lsu_lsc_ctl.scala 271:71] + wire [31:0] _T_217 = _T_210 | _T_216; // @[lsu_lsc_ctl.scala 270:133] + wire _T_218 = ~io_lsu_pkt_m_bits_unsign; // @[lsu_lsc_ctl.scala 272:17] + wire _T_219 = _T_218 & io_lsu_pkt_m_bits_by; // @[lsu_lsc_ctl.scala 272:43] wire [31:0] _T_221 = _T_219 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] wire [23:0] _T_224 = lsu_ld_datafn_m[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12] wire [31:0] _T_226 = {_T_224,lsu_ld_datafn_m[7:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_227 = _T_221 & _T_226; // @[lsu_lsc_ctl.scala 271:71] - wire [31:0] _T_228 = _T_217 | _T_227; // @[lsu_lsc_ctl.scala 270:114] - wire _T_230 = _T_218 & io_lsu_pkt_m_bits_half; // @[lsu_lsc_ctl.scala 272:43] + wire [31:0] _T_227 = _T_221 & _T_226; // @[lsu_lsc_ctl.scala 272:71] + wire [31:0] _T_228 = _T_217 | _T_227; // @[lsu_lsc_ctl.scala 271:114] + wire _T_230 = _T_218 & io_lsu_pkt_m_bits_half; // @[lsu_lsc_ctl.scala 273:43] wire [31:0] _T_232 = _T_230 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] wire [15:0] _T_235 = lsu_ld_datafn_m[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12] wire [31:0] _T_237 = {_T_235,lsu_ld_datafn_m[15:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_238 = _T_232 & _T_237; // @[lsu_lsc_ctl.scala 272:71] - wire [31:0] _T_239 = _T_228 | _T_238; // @[lsu_lsc_ctl.scala 271:134] + wire [31:0] _T_238 = _T_232 & _T_237; // @[lsu_lsc_ctl.scala 273:71] + wire [31:0] _T_239 = _T_228 | _T_238; // @[lsu_lsc_ctl.scala 272:134] wire [31:0] _T_241 = io_lsu_pkt_m_bits_word ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_243 = _T_241 & lsu_ld_datafn_m; // @[lsu_lsc_ctl.scala 273:43] - wire _T_245 = io_lsu_pkt_r_bits_unsign & io_lsu_pkt_r_bits_by; // @[lsu_lsc_ctl.scala 274:66] + wire [31:0] _T_243 = _T_241 & lsu_ld_datafn_m; // @[lsu_lsc_ctl.scala 274:43] + wire _T_245 = io_lsu_pkt_r_bits_unsign & io_lsu_pkt_r_bits_by; // @[lsu_lsc_ctl.scala 275:66] wire [31:0] _T_247 = _T_245 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] wire [31:0] _T_249 = {24'h0,lsu_ld_datafn_corr_r[7:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_250 = _T_247 & _T_249; // @[lsu_lsc_ctl.scala 274:94] - wire _T_251 = io_lsu_pkt_r_bits_unsign & io_lsu_pkt_r_bits_half; // @[lsu_lsc_ctl.scala 275:43] + wire [31:0] _T_250 = _T_247 & _T_249; // @[lsu_lsc_ctl.scala 275:94] + wire _T_251 = io_lsu_pkt_r_bits_unsign & io_lsu_pkt_r_bits_half; // @[lsu_lsc_ctl.scala 276:43] wire [31:0] _T_253 = _T_251 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] wire [31:0] _T_255 = {16'h0,lsu_ld_datafn_corr_r[15:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_256 = _T_253 & _T_255; // @[lsu_lsc_ctl.scala 275:71] - wire [31:0] _T_257 = _T_250 | _T_256; // @[lsu_lsc_ctl.scala 274:138] - wire _T_258 = ~io_lsu_pkt_r_bits_unsign; // @[lsu_lsc_ctl.scala 276:17] - wire _T_259 = _T_258 & io_lsu_pkt_r_bits_by; // @[lsu_lsc_ctl.scala 276:43] + wire [31:0] _T_256 = _T_253 & _T_255; // @[lsu_lsc_ctl.scala 276:71] + wire [31:0] _T_257 = _T_250 | _T_256; // @[lsu_lsc_ctl.scala 275:138] + wire _T_258 = ~io_lsu_pkt_r_bits_unsign; // @[lsu_lsc_ctl.scala 277:17] + wire _T_259 = _T_258 & io_lsu_pkt_r_bits_by; // @[lsu_lsc_ctl.scala 277:43] wire [31:0] _T_261 = _T_259 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] wire [23:0] _T_264 = lsu_ld_datafn_corr_r[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12] wire [31:0] _T_266 = {_T_264,lsu_ld_datafn_corr_r[7:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_267 = _T_261 & _T_266; // @[lsu_lsc_ctl.scala 276:71] - wire [31:0] _T_268 = _T_257 | _T_267; // @[lsu_lsc_ctl.scala 275:119] - wire _T_270 = _T_258 & io_lsu_pkt_r_bits_half; // @[lsu_lsc_ctl.scala 277:43] + wire [31:0] _T_267 = _T_261 & _T_266; // @[lsu_lsc_ctl.scala 277:71] + wire [31:0] _T_268 = _T_257 | _T_267; // @[lsu_lsc_ctl.scala 276:119] + wire _T_270 = _T_258 & io_lsu_pkt_r_bits_half; // @[lsu_lsc_ctl.scala 278:43] wire [31:0] _T_272 = _T_270 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] wire [15:0] _T_275 = lsu_ld_datafn_corr_r[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12] wire [31:0] _T_277 = {_T_275,lsu_ld_datafn_corr_r[15:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_278 = _T_272 & _T_277; // @[lsu_lsc_ctl.scala 277:71] - wire [31:0] _T_279 = _T_268 | _T_278; // @[lsu_lsc_ctl.scala 276:144] + wire [31:0] _T_278 = _T_272 & _T_277; // @[lsu_lsc_ctl.scala 278:71] + wire [31:0] _T_279 = _T_268 | _T_278; // @[lsu_lsc_ctl.scala 277:144] wire [31:0] _T_281 = io_lsu_pkt_r_bits_word ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_283 = _T_281 & lsu_ld_datafn_corr_r; // @[lsu_lsc_ctl.scala 278:43] + wire [31:0] _T_283 = _T_281 & lsu_ld_datafn_corr_r; // @[lsu_lsc_ctl.scala 279:43] lsu_addrcheck addrcheck ( // @[lsu_lsc_ctl.scala 118:25] .reset(addrcheck_reset), .io_lsu_c2_m_clk(addrcheck_io_lsu_c2_m_clk), @@ -641,18 +649,18 @@ module lsu_lsc_ctl( .io_clk(rvclkhdr_3_io_clk), .io_en(rvclkhdr_3_io_en) ); - assign io_lsu_result_m = _T_239 | _T_243; // @[lsu_lsc_ctl.scala 269:27] - assign io_lsu_result_corr_r = _T_279 | _T_283; // @[lsu_lsc_ctl.scala 274:27] - assign io_lsu_addr_d = {_T_40,_T_10[11:0]}; // @[lsu_lsc_ctl.scala 243:28] - assign io_lsu_addr_m = _T_152; // @[lsu_lsc_ctl.scala 226:24] - assign io_lsu_addr_r = _T_153; // @[lsu_lsc_ctl.scala 227:24] + assign io_lsu_result_m = _T_239 | _T_243; // @[lsu_lsc_ctl.scala 270:27] + assign io_lsu_result_corr_r = _T_279 | _T_283; // @[lsu_lsc_ctl.scala 275:27] + assign io_lsu_addr_d = {_T_40,_T_10[11:0]}; // @[lsu_lsc_ctl.scala 244:28] + assign io_lsu_addr_m = _T_152; // @[lsu_lsc_ctl.scala 227:24] + assign io_lsu_addr_r = _T_153; // @[lsu_lsc_ctl.scala 228:24] assign io_end_addr_d = rs1_d + _T_64; // @[lsu_lsc_ctl.scala 115:24] - assign io_end_addr_m = {_T_156,_T_158}; // @[lsu_lsc_ctl.scala 228:17] - assign io_end_addr_r = {_T_162,_T_164}; // @[lsu_lsc_ctl.scala 229:17] - assign io_store_data_m = _T_197 & _T_199; // @[lsu_lsc_ctl.scala 246:29] + assign io_end_addr_m = {_T_156,_T_158}; // @[lsu_lsc_ctl.scala 229:17] + assign io_end_addr_r = {_T_162,_T_164}; // @[lsu_lsc_ctl.scala 230:17] + assign io_store_data_m = _T_197 & _T_199; // @[lsu_lsc_ctl.scala 247:29] assign io_lsu_exc_m = access_fault_m | misaligned_fault_m; // @[lsu_lsc_ctl.scala 155:16] assign io_is_sideeffects_m = addrcheck_io_is_sideeffects_m; // @[lsu_lsc_ctl.scala 128:42] - assign io_lsu_commit_r = _T_190 & _T_191; // @[lsu_lsc_ctl.scala 245:19] + assign io_lsu_commit_r = _T_190 & _T_191; // @[lsu_lsc_ctl.scala 246:19] assign io_lsu_single_ecc_error_incr = _T_73 & io_lsu_pkt_r_valid; // @[lsu_lsc_ctl.scala 156:32] assign io_lsu_error_pkt_r_valid = _T_111; // @[lsu_lsc_ctl.scala 185:24 lsu_lsc_ctl.scala 187:30] assign io_lsu_error_pkt_r_bits_single_ecc_error = _T_110; // @[lsu_lsc_ctl.scala 185:24 lsu_lsc_ctl.scala 186:46] @@ -660,54 +668,57 @@ module lsu_lsc_ctl( assign io_lsu_error_pkt_r_bits_exc_type = _T_109_bits_exc_type; // @[lsu_lsc_ctl.scala 185:24] assign io_lsu_error_pkt_r_bits_mscause = _T_109_bits_mscause; // @[lsu_lsc_ctl.scala 185:24] assign io_lsu_error_pkt_r_bits_addr = _T_109_bits_addr; // @[lsu_lsc_ctl.scala 185:24] - assign io_lsu_fir_addr = io_lsu_ld_data_corr_r[31:1]; // @[lsu_lsc_ctl.scala 241:28] + assign io_lsu_fir_addr = io_lsu_ld_data_corr_r[31:1]; // @[lsu_lsc_ctl.scala 242:28] assign io_lsu_fir_error = _T_112; // @[lsu_lsc_ctl.scala 188:38] assign io_addr_in_dccm_d = addrcheck_io_addr_in_dccm_d; // @[lsu_lsc_ctl.scala 129:42] - assign io_addr_in_dccm_m = _T_178; // @[lsu_lsc_ctl.scala 232:24] - assign io_addr_in_dccm_r = _T_179; // @[lsu_lsc_ctl.scala 233:24] + assign io_addr_in_dccm_m = _T_178; // @[lsu_lsc_ctl.scala 233:24] + assign io_addr_in_dccm_r = _T_179; // @[lsu_lsc_ctl.scala 234:24] assign io_addr_in_pic_d = addrcheck_io_addr_in_pic_d; // @[lsu_lsc_ctl.scala 130:42] - assign io_addr_in_pic_m = _T_180; // @[lsu_lsc_ctl.scala 234:24] - assign io_addr_in_pic_r = _T_181; // @[lsu_lsc_ctl.scala 235:24] - assign io_addr_external_m = _T_182; // @[lsu_lsc_ctl.scala 236:24] - assign io_lsu_pkt_d_valid = _T_127 | io_dma_lsc_ctl_dma_dccm_req; // @[lsu_lsc_ctl.scala 208:20 lsu_lsc_ctl.scala 212:24] - assign io_lsu_pkt_d_bits_fast_int = io_dec_lsu_valid_raw_d & io_lsu_p_bits_fast_int; // @[lsu_lsc_ctl.scala 208:20] - assign io_lsu_pkt_d_bits_by = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_by : dma_pkt_d_bits_by; // @[lsu_lsc_ctl.scala 208:20] - assign io_lsu_pkt_d_bits_half = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_half : dma_pkt_d_bits_half; // @[lsu_lsc_ctl.scala 208:20] - assign io_lsu_pkt_d_bits_word = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_word : dma_pkt_d_bits_word; // @[lsu_lsc_ctl.scala 208:20] - assign io_lsu_pkt_d_bits_dword = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_dword : dma_pkt_d_bits_dword; // @[lsu_lsc_ctl.scala 208:20] - assign io_lsu_pkt_d_bits_load = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_load : dma_pkt_d_bits_load; // @[lsu_lsc_ctl.scala 208:20] - assign io_lsu_pkt_d_bits_store = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_store : io_dma_lsc_ctl_dma_mem_write; // @[lsu_lsc_ctl.scala 208:20] - assign io_lsu_pkt_d_bits_unsign = io_dec_lsu_valid_raw_d & io_lsu_p_bits_unsign; // @[lsu_lsc_ctl.scala 208:20] - assign io_lsu_pkt_d_bits_dma = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_dma : 1'h1; // @[lsu_lsc_ctl.scala 208:20] - assign io_lsu_pkt_d_bits_store_data_bypass_d = io_dec_lsu_valid_raw_d & io_lsu_p_bits_store_data_bypass_d; // @[lsu_lsc_ctl.scala 208:20] - assign io_lsu_pkt_d_bits_load_ldst_bypass_d = io_dec_lsu_valid_raw_d & io_lsu_p_bits_load_ldst_bypass_d; // @[lsu_lsc_ctl.scala 208:20] - assign io_lsu_pkt_d_bits_store_data_bypass_m = io_dec_lsu_valid_raw_d & io_lsu_p_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 208:20] - assign io_lsu_pkt_m_valid = _T_141; // @[lsu_lsc_ctl.scala 216:28 lsu_lsc_ctl.scala 218:28] - assign io_lsu_pkt_m_bits_fast_int = _T_138_bits_fast_int; // @[lsu_lsc_ctl.scala 216:28] - assign io_lsu_pkt_m_bits_by = _T_138_bits_by; // @[lsu_lsc_ctl.scala 216:28] - assign io_lsu_pkt_m_bits_half = _T_138_bits_half; // @[lsu_lsc_ctl.scala 216:28] - assign io_lsu_pkt_m_bits_word = _T_138_bits_word; // @[lsu_lsc_ctl.scala 216:28] - assign io_lsu_pkt_m_bits_dword = _T_138_bits_dword; // @[lsu_lsc_ctl.scala 216:28] - assign io_lsu_pkt_m_bits_load = _T_138_bits_load; // @[lsu_lsc_ctl.scala 216:28] - assign io_lsu_pkt_m_bits_store = _T_138_bits_store; // @[lsu_lsc_ctl.scala 216:28] - assign io_lsu_pkt_m_bits_unsign = _T_138_bits_unsign; // @[lsu_lsc_ctl.scala 216:28] - assign io_lsu_pkt_m_bits_dma = _T_138_bits_dma; // @[lsu_lsc_ctl.scala 216:28] - assign io_lsu_pkt_m_bits_store_data_bypass_d = _T_138_bits_store_data_bypass_d; // @[lsu_lsc_ctl.scala 216:28] - assign io_lsu_pkt_m_bits_load_ldst_bypass_d = _T_138_bits_load_ldst_bypass_d; // @[lsu_lsc_ctl.scala 216:28] - assign io_lsu_pkt_m_bits_store_data_bypass_m = _T_138_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 216:28] - assign io_lsu_pkt_r_valid = _T_142; // @[lsu_lsc_ctl.scala 217:28 lsu_lsc_ctl.scala 219:28] - assign io_lsu_pkt_r_bits_fast_int = _T_140_bits_fast_int; // @[lsu_lsc_ctl.scala 217:28] - assign io_lsu_pkt_r_bits_by = _T_140_bits_by; // @[lsu_lsc_ctl.scala 217:28] - assign io_lsu_pkt_r_bits_half = _T_140_bits_half; // @[lsu_lsc_ctl.scala 217:28] - assign io_lsu_pkt_r_bits_word = _T_140_bits_word; // @[lsu_lsc_ctl.scala 217:28] - assign io_lsu_pkt_r_bits_dword = _T_140_bits_dword; // @[lsu_lsc_ctl.scala 217:28] - assign io_lsu_pkt_r_bits_load = _T_140_bits_load; // @[lsu_lsc_ctl.scala 217:28] - assign io_lsu_pkt_r_bits_store = _T_140_bits_store; // @[lsu_lsc_ctl.scala 217:28] - assign io_lsu_pkt_r_bits_unsign = _T_140_bits_unsign; // @[lsu_lsc_ctl.scala 217:28] - assign io_lsu_pkt_r_bits_dma = _T_140_bits_dma; // @[lsu_lsc_ctl.scala 217:28] - assign io_lsu_pkt_r_bits_store_data_bypass_d = _T_140_bits_store_data_bypass_d; // @[lsu_lsc_ctl.scala 217:28] - assign io_lsu_pkt_r_bits_load_ldst_bypass_d = _T_140_bits_load_ldst_bypass_d; // @[lsu_lsc_ctl.scala 217:28] - assign io_lsu_pkt_r_bits_store_data_bypass_m = _T_140_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 217:28] + assign io_addr_in_pic_m = _T_180; // @[lsu_lsc_ctl.scala 235:24] + assign io_addr_in_pic_r = _T_181; // @[lsu_lsc_ctl.scala 236:24] + assign io_addr_external_m = _T_182; // @[lsu_lsc_ctl.scala 237:24] + assign io_lsu_pkt_d_valid = _T_127 | io_dma_lsc_ctl_dma_dccm_req; // @[lsu_lsc_ctl.scala 209:20 lsu_lsc_ctl.scala 213:24] + assign io_lsu_pkt_d_bits_fast_int = io_dec_lsu_valid_raw_d & io_lsu_p_bits_fast_int; // @[lsu_lsc_ctl.scala 209:20] + assign io_lsu_pkt_d_bits_stack = io_dec_lsu_valid_raw_d & io_lsu_p_bits_stack; // @[lsu_lsc_ctl.scala 209:20] + assign io_lsu_pkt_d_bits_by = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_by : dma_pkt_d_bits_by; // @[lsu_lsc_ctl.scala 209:20] + assign io_lsu_pkt_d_bits_half = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_half : dma_pkt_d_bits_half; // @[lsu_lsc_ctl.scala 209:20] + assign io_lsu_pkt_d_bits_word = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_word : dma_pkt_d_bits_word; // @[lsu_lsc_ctl.scala 209:20] + assign io_lsu_pkt_d_bits_dword = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_dword : dma_pkt_d_bits_dword; // @[lsu_lsc_ctl.scala 209:20] + assign io_lsu_pkt_d_bits_load = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_load : dma_pkt_d_bits_load; // @[lsu_lsc_ctl.scala 209:20] + assign io_lsu_pkt_d_bits_store = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_store : io_dma_lsc_ctl_dma_mem_write; // @[lsu_lsc_ctl.scala 209:20] + assign io_lsu_pkt_d_bits_unsign = io_dec_lsu_valid_raw_d & io_lsu_p_bits_unsign; // @[lsu_lsc_ctl.scala 209:20] + assign io_lsu_pkt_d_bits_dma = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_dma : 1'h1; // @[lsu_lsc_ctl.scala 209:20] + assign io_lsu_pkt_d_bits_store_data_bypass_d = io_dec_lsu_valid_raw_d & io_lsu_p_bits_store_data_bypass_d; // @[lsu_lsc_ctl.scala 209:20] + assign io_lsu_pkt_d_bits_load_ldst_bypass_d = io_dec_lsu_valid_raw_d & io_lsu_p_bits_load_ldst_bypass_d; // @[lsu_lsc_ctl.scala 209:20] + assign io_lsu_pkt_d_bits_store_data_bypass_m = io_dec_lsu_valid_raw_d & io_lsu_p_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 209:20] + assign io_lsu_pkt_m_valid = _T_141; // @[lsu_lsc_ctl.scala 217:28 lsu_lsc_ctl.scala 219:28] + assign io_lsu_pkt_m_bits_fast_int = _T_138_bits_fast_int; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_m_bits_stack = _T_138_bits_stack; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_m_bits_by = _T_138_bits_by; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_m_bits_half = _T_138_bits_half; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_m_bits_word = _T_138_bits_word; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_m_bits_dword = _T_138_bits_dword; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_m_bits_load = _T_138_bits_load; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_m_bits_store = _T_138_bits_store; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_m_bits_unsign = _T_138_bits_unsign; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_m_bits_dma = _T_138_bits_dma; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_m_bits_store_data_bypass_d = _T_138_bits_store_data_bypass_d; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_m_bits_load_ldst_bypass_d = _T_138_bits_load_ldst_bypass_d; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_m_bits_store_data_bypass_m = _T_138_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_r_valid = _T_142; // @[lsu_lsc_ctl.scala 218:28 lsu_lsc_ctl.scala 220:28] + assign io_lsu_pkt_r_bits_fast_int = _T_140_bits_fast_int; // @[lsu_lsc_ctl.scala 218:28] + assign io_lsu_pkt_r_bits_stack = _T_140_bits_stack; // @[lsu_lsc_ctl.scala 218:28] + assign io_lsu_pkt_r_bits_by = _T_140_bits_by; // @[lsu_lsc_ctl.scala 218:28] + assign io_lsu_pkt_r_bits_half = _T_140_bits_half; // @[lsu_lsc_ctl.scala 218:28] + assign io_lsu_pkt_r_bits_word = _T_140_bits_word; // @[lsu_lsc_ctl.scala 218:28] + assign io_lsu_pkt_r_bits_dword = _T_140_bits_dword; // @[lsu_lsc_ctl.scala 218:28] + assign io_lsu_pkt_r_bits_load = _T_140_bits_load; // @[lsu_lsc_ctl.scala 218:28] + assign io_lsu_pkt_r_bits_store = _T_140_bits_store; // @[lsu_lsc_ctl.scala 218:28] + assign io_lsu_pkt_r_bits_unsign = _T_140_bits_unsign; // @[lsu_lsc_ctl.scala 218:28] + assign io_lsu_pkt_r_bits_dma = _T_140_bits_dma; // @[lsu_lsc_ctl.scala 218:28] + assign io_lsu_pkt_r_bits_store_data_bypass_d = _T_140_bits_store_data_bypass_d; // @[lsu_lsc_ctl.scala 218:28] + assign io_lsu_pkt_r_bits_load_ldst_bypass_d = _T_140_bits_load_ldst_bypass_d; // @[lsu_lsc_ctl.scala 218:28] + assign io_lsu_pkt_r_bits_store_data_bypass_m = _T_140_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 218:28] assign addrcheck_reset = reset; assign addrcheck_io_lsu_c2_m_clk = io_lsu_c2_m_clk; // @[lsu_lsc_ctl.scala 120:42] assign addrcheck_io_start_addr_d = {_T_40,_T_10[11:0]}; // @[lsu_lsc_ctl.scala 122:42] @@ -792,83 +803,87 @@ initial begin _RAND_12 = {1{`RANDOM}}; _T_138_bits_fast_int = _RAND_12[0:0]; _RAND_13 = {1{`RANDOM}}; - _T_138_bits_by = _RAND_13[0:0]; + _T_138_bits_stack = _RAND_13[0:0]; _RAND_14 = {1{`RANDOM}}; - _T_138_bits_half = _RAND_14[0:0]; + _T_138_bits_by = _RAND_14[0:0]; _RAND_15 = {1{`RANDOM}}; - _T_138_bits_word = _RAND_15[0:0]; + _T_138_bits_half = _RAND_15[0:0]; _RAND_16 = {1{`RANDOM}}; - _T_138_bits_dword = _RAND_16[0:0]; + _T_138_bits_word = _RAND_16[0:0]; _RAND_17 = {1{`RANDOM}}; - _T_138_bits_load = _RAND_17[0:0]; + _T_138_bits_dword = _RAND_17[0:0]; _RAND_18 = {1{`RANDOM}}; - _T_138_bits_store = _RAND_18[0:0]; + _T_138_bits_load = _RAND_18[0:0]; _RAND_19 = {1{`RANDOM}}; - _T_138_bits_unsign = _RAND_19[0:0]; + _T_138_bits_store = _RAND_19[0:0]; _RAND_20 = {1{`RANDOM}}; - _T_138_bits_dma = _RAND_20[0:0]; + _T_138_bits_unsign = _RAND_20[0:0]; _RAND_21 = {1{`RANDOM}}; - _T_138_bits_store_data_bypass_d = _RAND_21[0:0]; + _T_138_bits_dma = _RAND_21[0:0]; _RAND_22 = {1{`RANDOM}}; - _T_138_bits_load_ldst_bypass_d = _RAND_22[0:0]; + _T_138_bits_store_data_bypass_d = _RAND_22[0:0]; _RAND_23 = {1{`RANDOM}}; - _T_138_bits_store_data_bypass_m = _RAND_23[0:0]; + _T_138_bits_load_ldst_bypass_d = _RAND_23[0:0]; _RAND_24 = {1{`RANDOM}}; - _T_140_bits_fast_int = _RAND_24[0:0]; + _T_138_bits_store_data_bypass_m = _RAND_24[0:0]; _RAND_25 = {1{`RANDOM}}; - _T_140_bits_by = _RAND_25[0:0]; + _T_140_bits_fast_int = _RAND_25[0:0]; _RAND_26 = {1{`RANDOM}}; - _T_140_bits_half = _RAND_26[0:0]; + _T_140_bits_stack = _RAND_26[0:0]; _RAND_27 = {1{`RANDOM}}; - _T_140_bits_word = _RAND_27[0:0]; + _T_140_bits_by = _RAND_27[0:0]; _RAND_28 = {1{`RANDOM}}; - _T_140_bits_dword = _RAND_28[0:0]; + _T_140_bits_half = _RAND_28[0:0]; _RAND_29 = {1{`RANDOM}}; - _T_140_bits_load = _RAND_29[0:0]; + _T_140_bits_word = _RAND_29[0:0]; _RAND_30 = {1{`RANDOM}}; - _T_140_bits_store = _RAND_30[0:0]; + _T_140_bits_dword = _RAND_30[0:0]; _RAND_31 = {1{`RANDOM}}; - _T_140_bits_unsign = _RAND_31[0:0]; + _T_140_bits_load = _RAND_31[0:0]; _RAND_32 = {1{`RANDOM}}; - _T_140_bits_dma = _RAND_32[0:0]; + _T_140_bits_store = _RAND_32[0:0]; _RAND_33 = {1{`RANDOM}}; - _T_140_bits_store_data_bypass_d = _RAND_33[0:0]; + _T_140_bits_unsign = _RAND_33[0:0]; _RAND_34 = {1{`RANDOM}}; - _T_140_bits_load_ldst_bypass_d = _RAND_34[0:0]; + _T_140_bits_dma = _RAND_34[0:0]; _RAND_35 = {1{`RANDOM}}; - _T_140_bits_store_data_bypass_m = _RAND_35[0:0]; + _T_140_bits_store_data_bypass_d = _RAND_35[0:0]; _RAND_36 = {1{`RANDOM}}; - _T_141 = _RAND_36[0:0]; + _T_140_bits_load_ldst_bypass_d = _RAND_36[0:0]; _RAND_37 = {1{`RANDOM}}; - _T_142 = _RAND_37[0:0]; + _T_140_bits_store_data_bypass_m = _RAND_37[0:0]; _RAND_38 = {1{`RANDOM}}; - store_data_pre_m = _RAND_38[31:0]; + _T_141 = _RAND_38[0:0]; _RAND_39 = {1{`RANDOM}}; - _T_152 = _RAND_39[31:0]; + _T_142 = _RAND_39[0:0]; _RAND_40 = {1{`RANDOM}}; - _T_153 = _RAND_40[31:0]; + store_data_pre_m = _RAND_40[31:0]; _RAND_41 = {1{`RANDOM}}; - end_addr_pre_m = _RAND_41[28:0]; + _T_152 = _RAND_41[31:0]; _RAND_42 = {1{`RANDOM}}; - _T_158 = _RAND_42[2:0]; + _T_153 = _RAND_42[31:0]; _RAND_43 = {1{`RANDOM}}; - end_addr_pre_r = _RAND_43[28:0]; + end_addr_pre_m = _RAND_43[28:0]; _RAND_44 = {1{`RANDOM}}; - _T_164 = _RAND_44[2:0]; + _T_158 = _RAND_44[2:0]; _RAND_45 = {1{`RANDOM}}; - _T_178 = _RAND_45[0:0]; + end_addr_pre_r = _RAND_45[28:0]; _RAND_46 = {1{`RANDOM}}; - _T_179 = _RAND_46[0:0]; + _T_164 = _RAND_46[2:0]; _RAND_47 = {1{`RANDOM}}; - _T_180 = _RAND_47[0:0]; + _T_178 = _RAND_47[0:0]; _RAND_48 = {1{`RANDOM}}; - _T_181 = _RAND_48[0:0]; + _T_179 = _RAND_48[0:0]; _RAND_49 = {1{`RANDOM}}; - _T_182 = _RAND_49[0:0]; + _T_180 = _RAND_49[0:0]; _RAND_50 = {1{`RANDOM}}; - addr_external_r = _RAND_50[0:0]; + _T_181 = _RAND_50[0:0]; _RAND_51 = {1{`RANDOM}}; - bus_read_data_r = _RAND_51[31:0]; + _T_182 = _RAND_51[0:0]; + _RAND_52 = {1{`RANDOM}}; + addr_external_r = _RAND_52[0:0]; + _RAND_53 = {1{`RANDOM}}; + bus_read_data_r = _RAND_53[31:0]; `endif // RANDOMIZE_REG_INIT if (reset) begin access_fault_m = 1'h0; @@ -909,6 +924,9 @@ initial begin if (reset) begin _T_138_bits_fast_int = 1'h0; end + if (reset) begin + _T_138_bits_stack = 1'h0; + end if (reset) begin _T_138_bits_by = 1'h0; end @@ -945,6 +963,9 @@ initial begin if (reset) begin _T_140_bits_fast_int = 1'h0; end + if (reset) begin + _T_140_bits_stack = 1'h0; + end if (reset) begin _T_140_bits_by = 1'h0; end @@ -1111,7 +1132,7 @@ end // initial _T_111 <= _T_81 & _T_82; end end - always @(posedge clock or posedge reset) begin + always @(posedge io_lsu_c2_r_clk or posedge reset) begin if (reset) begin _T_112 <= 2'h0; end else if (fir_nondccm_access_error_m) begin @@ -1131,6 +1152,13 @@ end // initial _T_138_bits_fast_int <= io_lsu_pkt_d_bits_fast_int; end end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_138_bits_stack <= 1'h0; + end else begin + _T_138_bits_stack <= io_lsu_pkt_d_bits_stack; + end + end always @(posedge io_lsu_c1_m_clk or posedge reset) begin if (reset) begin _T_138_bits_by <= 1'h0; @@ -1215,6 +1243,13 @@ end // initial _T_140_bits_fast_int <= io_lsu_pkt_m_bits_fast_int; end end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_140_bits_stack <= 1'h0; + end else begin + _T_140_bits_stack <= io_lsu_pkt_m_bits_stack; + end + end always @(posedge io_lsu_c1_r_clk or posedge reset) begin if (reset) begin _T_140_bits_by <= 1'h0; diff --git a/src/main/scala/include/bundle.scala b/src/main/scala/include/bundle.scala index de30db2c..167d812d 100644 --- a/src/main/scala/include/bundle.scala +++ b/src/main/scala/include/bundle.scala @@ -525,6 +525,7 @@ class alu_pkt_t extends Bundle { class lsu_pkt_t extends Bundle { val fast_int = Bool() + val stack = Bool() val by = Bool() val half = Bool() val word = Bool() @@ -545,7 +546,6 @@ class lsu_error_pkt_t extends Bundle { val mscause = UInt(4.W) val addr = UInt(32.W) } - class dec_pkt_t extends Bundle { val alu = Bool() val rs1 = Bool() diff --git a/src/main/scala/lsu/lsu_lsc_ctl.scala b/src/main/scala/lsu/lsu_lsc_ctl.scala index a4ac7234..830ecf43 100644 --- a/src/main/scala/lsu/lsu_lsc_ctl.scala +++ b/src/main/scala/lsu/lsu_lsc_ctl.scala @@ -185,9 +185,10 @@ class lsu_lsc_ctl extends Module with RequireAsyncReset with lib io.lsu_error_pkt_r := rvdffe(lsu_error_pkt_m,(lsu_error_pkt_m.valid | lsu_error_pkt_m.bits.single_ecc_error | io.clk_override),clock,io.scan_mode) io.lsu_error_pkt_r.bits.single_ecc_error := withClock(io.lsu_c2_r_clk){RegNext(lsu_error_pkt_m.bits.single_ecc_error, 0.U)} io.lsu_error_pkt_r.valid := withClock(io.lsu_c2_r_clk){RegNext(lsu_error_pkt_m.valid, 0.U)} - io.lsu_fir_error := RegNext(lsu_fir_error_m,0.U) + io.lsu_fir_error := withClock(io.lsu_c2_r_clk){RegNext(lsu_fir_error_m,0.U)} } dma_pkt_d.bits.unsign := 0.U + dma_pkt_d.bits.stack := 0.U dma_pkt_d.bits.fast_int := 0.U dma_pkt_d.valid := io.dma_lsc_ctl.dma_dccm_req dma_pkt_d.bits.dma := 1.U diff --git a/target/scala-2.12/classes/include/lsu_error_pkt_t.class b/target/scala-2.12/classes/include/lsu_error_pkt_t.class index c9f92bd3325493dc455ae30ebbee82b3f5e0d754..2ec391ccbb7725b70ae5170311faa5dc8b6a207c 100644 GIT binary patch delta 79 zcmaDN@I+vPA=~6UHnGX>Z0eI&1L+nZ{Q^iI1k$SPVw3-|sWU21&Sw*yY|TDNQjUR( eNuEKDNrAzLNs+;gNr@qfNtq#^NpA8p_BsHp4ir)V delta 79 zcmaDN@I+vPAseIIK$?k0GlMUI#Cbt0TJRp4#NUsLc|A6!hAZ^V)Nm7=9i%E__ bj!B-uh)IFLjY*Lqib;tfpGkJ|Gxj4S~yF7-}7vAH6ufAmdIDWhwTK!z5;;mADu4=w}r+!9-DJ$1~ofXC8T9O2i1? zkz%l0VrRv{s7H>=91~9{7(j^$YivHzkDOgbyAwQdCOfkrc-^%%FcU z@lFb2k_mINm-Vb6dQ+0XwVk2ZA&%gT7*#wNlew4DN~X=p<3=-&2TmTyUgp7b%{*kW zna7Be2hUvQ(akpVQ25I{l#r80%FcuFAMH<{3&%^1`v*@%c?a9Fs{`A!LklN9jEJ$j_7s;VSY~3Ik4v$kyXsMopy1=hO7_5bI4XCGT#U(#$U#Po z3d_N-Z@)P{m<~w-&u*^lN=iD!^89yafmi6?^A7A(o-bB3#-C9J*Yex5f?`KcSjPEp z*$y$%nL;k(EuPNEtd^X=;~PizJhwX*krL}wHRK6P%!1XH?P!jda$Xu|ma9o~Jh9ry z?M_EzJJPu4o8$fT+1@K`d%HT&Tkg9nu^rO0*(2mqOM-7)_8Zzp*Yi^ELSFN}zd19! zl0V&lzcqvHuKgV;3?FR>+oj%R_4MG2`Lf^4<4hP>FtiWhNau0fIQ=ks-TH^K?&}{0 zc!c?;`!~<4x>nGPWTjNqboEiy&?@En*wtoISL$^i5I6MyoDbR&!Y(jEcay9tg}2J7 zI+mzZ^f4a<5P~g3KIo*{vc?hGPL#Tl)5->wY`Qto95d^$ZqQ-~O#TAF^IFkQD4bPl zMH(vF(W6%svspJPH5I|zDA%cg5!hmhDm-j;=ZcD<HnNSYXWrJ({2jTW2;F4BDR_mpx0K@0z_>!D?p#E zZVS+Ft9bziY;{L~L0c^eFl4K{0u0+~Re&3|TBk3tu9Y=ogTBCI>=0qN`AM%af)5@b z`1T$>e45@ILy(-ey=FeWSpt$g$ncQ%${IDTK!0xOi_dfo=wcdLYYVphwAKzn|D?0^ z)v0T-Ljg8m*AE`}3L)Z5yJ9peuRR`uuupDKs#X0$fX5*DsV76fDp@I#J%aSB)cr;& zuhyO@d7XMf=?b0the}N|+n1d}s$5oUR#njP5B_YWQ7fohR6hvOgGSlVO6s9j*NBkI z<%*$LMMcY7H%O|i(=MsVS}GAyOgJBUU7bSdsi;MRJD~$s1NA zXIPPZVMTI<70DA;Bu7}0{9r|L1H}N4H)&slEVbq+B1LZMR~Y??1Ord#=`}lSgR_gdk8 zS9k;Nlf%uz_?s%hER2s+zrf}vNc|3JQjb2t!EZ3?s0l~K9Cgc4Gme^bRNPSuj#_lo zvZGcUwdSaMKT|?>fo{+N2223_RHR)@Ck!znOfn&uXTq?~bio$W4Ud@~c)>)V$n-*) ziNZP42j4UO@B?w53;W|`VRLXutA}WPKb3q3n1`lFZ62OkyK?ZHVmo~l^KkIhp$(3x zW0yWsfDYpOKsTBMbRp5hEEnsLp}UQgSpak^(Zf7D=pLhoX%H~~6mK(^* z>P2(emr1+Ybgf?W0s0nwk*;n@u@YR-o7w-2=9}4){yp>8KY#oQ0CVs)0YTMkTDz{y zXsvdo@!G7I0U!i=YbR<;(F!xAwqDni05Amjs;#G6HCdAhjI7&Yrl}lhO3j?vv4(fl zV_i1eO{GYHtzMW)i_o9^BwmoD)n0N>%x<%!Og6+t!B46r$ZRtunj#W2p7WP|vxEz* z2_(UVB}(EVb6XhZd{RzgX|^OwVItDlK2t3X5Y{)&Ng+0%5)u+h2`;ir#k5!^yJAib zkZls2DxJx_q)cP1=x2P3g!tFw5ZlutLRc6hw}kYzk7OnGrMQ^uaq}4MP z$PBXF^)V8qk?@10epom?9v7r>jt1C0b2WTWpy9J8$J2wwl`Ol+lu4WnviniO%vFz{ zze{Wm6%))99V1*a$leKFCv>b)$@4<#RnAm@czWDBB2boFPst?zR$@gmot{5t;!-j^ zG$%5`;`!!qfrbv>-HZ$fG$btB{jd}9x%_52jn8xMl40xlM&^9;5c6@O$fUC;`r)0E zL;vFT*1^(uTT8x}ObUA0FG^DfIg!~&KQ@Mzj#i@l>dgLZtySXZjl)@m+4dfnSfQjJ ztyTaywEO>a0SFO@dB6nX9kLz#?#GpsFIy&&K_k+mZXZ;WOgvAPp|nju@=mT5E<0{*t%!lER= z)K9T$WA<>RE}L?tdeOkQtKj6Q#Z-{PmE|Gjs9QXw9W}+nfTL!37<5#QhapE5co=rn9Uev;HP6GS zqZaYKmsMRg@8f$%y3(|3 z01t8q?ilT6O?iaXLLmLTt()qpvZuCGBqUuoOxZ3WT;9G5)^rVbS<{aU^m6BR01=(y z!`p|4sAU{fQOg;2L|@nuU13M`gdNclc0@ne5#3-%^nxAH33fyu*b!ZTF%0NLxQ6XB z?9E^#7}?2RVeA763ftKFtw9=r=csvS0$hg-_ONh0;Tzp>pC_E~geSUT!4pn;!js)_ z)Dup5!neEOm?xa}gr~dVeouJ76Q1pc=gk?18Gqmd8Xl8=({p2rD`UsDHhc#5|A7Se^7<1JPS53HT z(p9%zHSMZdSLIzb=c>D|T5#3U&zOc&SxeB1vKN9_UH!BVMyLQ2GzxhdgJs$ek7yj8 z(FDArNvP8l=rj%IbO3%t=5sZ^|5S}E?BL2#Tsw$$8V2ix6R^+03wuWvb}@$VGguWJ zXh9F`;Q$_}INADAb~WSeaSiaQ!Nxin@FK#-vOHcP*jWC>YXuwY$Ka)dja7>95&#$$ F;9u!i>o@=a diff --git a/target/scala-2.12/classes/lsu/lsc_ctl$.class b/target/scala-2.12/classes/lsu/lsc_ctl$.class index 5fa673d0e35f44985d48cdd8ce4e3514d94615df..ad18ccbdd36a8f1a0a6721f89b15d8f635aa5f9f 100644 GIT binary patch delta 114 zcmbOsH$!g21r|n=%@?=k o*c={LuqyG%KY6U7EFWH1M(N3uczs!=8PtJdPk1YUWGvrq0Am{;*#H0l delta 114 zcmbOsH$!g21r|o*%@?=k o*c={LuqyG%KY6U7EFWH1Mybh@czs!=7}SAcPk1YUWGvrq0AMyB%K!iX diff --git a/target/scala-2.12/classes/lsu/lsc_ctl$delayedInit$body.class b/target/scala-2.12/classes/lsu/lsc_ctl$delayedInit$body.class index 050f20981defc1c1c3e7a380baf2fab8a9a181c5..2a406ce11d85bf60f3f000ec63d24e50d859e79f 100644 GIT binary patch delta 19 Zcmcb^dWUs`JrkqUWCx}IAUToA8vs4W1%Lnm delta 19 Zcmcb^dWUs`JrkqkWCx}IAUToA8vs4G1%3bk diff --git a/target/scala-2.12/classes/lsu/lsu_lsc_ctl.class b/target/scala-2.12/classes/lsu/lsu_lsc_ctl.class index b03902a8bc5157278c3082e66bad76932ecb6829..aae7cca3a61409d86cc1a36563701daf131f5daf 100644 GIT binary patch literal 329444 zcmcd!2Yg+%)xYCCzx$qL$9DDv2WJn*b`ob0QpZ_NY=^|z1Lwtlc1%1Hj|@n{-q5l~ zp`{ckl+v0%UGS_%{>Wp)5%wEa5iq~AF@db-2Pjd&*fz|lF^r^rMhEA)HGtPE!&FWFJ{C{Bj00xYF9(D zHE9~7syR{InQCfHHFOu(VRT(fb9=J8r!zIzG@{$~b*H+_0alh7pSRt#rfxR(Rjy2q zGNV><;jZLSW~J3XT9H>7v6yLQ=P#Ha?;o9ER+Lmkt>`?{s;q$Mtg6DoXuN;?fJO0B zY|CCyNbv(8KF9XNALGW46!B}KAU}r3C&z;P6mR@EH-4Tseu5icla6=5&LoOI4(x0Z z@f^<-9$$!f+Pv|_Zu|jne2E*M6Y=0LbK^&P<7c?>Q@ruzZu~rN{A@SA#v4D^jo;#p zpXbK6QGC270_Cm5_=@DwP_B_t56(rd{1k8e5;uOHH@?b^ukpq&cjLEs<7?dbHgEh2 zH~xS(ex)0qljXr#=f;op#;W1!Z|<_8g?7AZ&(ti-DyS;VFR84^$r&1-FxoP$ zf_SoG>6WtQx;c~AO&vC?=RkC5e*1|0{Mc-^VRWTsjT$o`S+R0%M^)+M*n-N6e0yAe zPX1`qDvBmcayHN0TEB7fxD{Jwq?WJE&tDmhN48{*EC8GX>k@^9Et_YxcJkiV4MVqXg7$3Rlx^D$W@*Ldiede8;uDI7TUoKv{pD@LquF*>eCPt| z{|n4WdH0Tk!v{AHnX`3C>1M=nR2s*$XcGNl>yl+Bt!-al+O}@=%KZGQibOOrCSI6i z)=>1H^`&L=m+hYkc;f@31N)cQ+suR=-*=3eXlq`(e`dcEW_2w``|Hco_Q#~{S4Ug8 z{S5{C7f%^Fcia4BlSda84#4`^HwNlw)tCVlg=@!jv_QTqm#6dXZ;c_pP0cT0ONuv4 zYph>3U~lzEC|6lRlxs@=iY#8PA+?*Qw=F+7sl08&w5HUu{o^`@%mJJ|X`CCzm<(|) zZreP!VZ)&PYuh%IZe0%cYPU@5g8Ge*6ZKoN%*@65Wh2VAR%I0pXu zIsNP`t20_tIJB_Rv8dxJ}g z%KM!#Ewv-7anIxtP+upz^_8^CQ_ZWO9Zo1|o4;&fAvAwL zMSIxBlAg+gJMg(V!S!o;Zc>9rtnW8sE^pUe>)m!ZhWqcFrslPcOW^t034Y1jabcEh z-$Dz^kyW&$W(&tRdy0!M8~tbU(6UsD@@;bSUCE!P%7P-{=ko@;{+ZRZrC|S{oMB~M z^9!&%Gu-k_n9!WNaoV=3f&qKEUlcQ0Ulo;Q9aRUjm*fnavo!_&RI=GE$IzN0cuu^} z!vQzH3MaKZcmLvko1y&6Sb5u!>CITr#cnwgyd1;kHO}YtJIBRSQB~fte$I(igC;lE zY%FVRsolRe7yP`{t)B{BKe_wYP2D`Bhx=>tSXV#A{j9rg&aq3TZk*P%BzOPXnvrvM zrVcJ|ZXb%zf6Wk4FB7I!IQaaFbnaJO=%0DQKl6{~{NAul!j-kD#DZ}S%#dd(_)6R0A&y^hau&v=Q#|>~6*bAa=`|Zl- z?E~W(gMMMt!DC{O9y@e8_?^8Ve(3c6Xg}LcZ*lE!nbC-Tu%IyJ*4vCYZ|Ax>`?HES zm7?Dku3YH0_wXq9#}l_4w1>2B!2U5mo*sXof6U{4x4vv&%b)?HB9FrJKp{x!a+Al*(AE23Dh zSslaYV!u|na*4oIIM(XVpQqWaE%-dx3r42PI|!!LIDRFk7V+^RdUAT)o6^6qa!zCA zoc(LtN0c?$vt9pZBj+^DpUHNO9yTi_p1)lw7#DJ@%zn$~6z!qs&K_U9aaxx>FQB(9 z(!bCyYpRK<=M3k`qi8&8lTygnLYDo?jKaUS&S!XendWvr$ewD{r65DKFb;| z%f-A|4mP9MAA0<8eR-ihhRby|FFtAU6f+C!ZEVMupb`7 zQq}|GC;6k~5&xX-h6Bg!soqku*Pf6+tGH%bYW^~|r(cyBuOBwOym%PYe^%A5+F{eX zms7d2Qnjp`Z8T#%9F}hl9y)nx?q=#wAU>xC`nmS?C8?@qydHANPi8gO)J}%yr_35j zekJ?kifDXQ4UDrvxiJH~m$Z?c-JbmO$iCZ8Rb`pmri?0Yn?Fd(WBn(%y`eLjmQ0;I z8s4|^V=V*X6Dln`(%zryf%mtiEz5H^53Z<0ydz>$HDzXc7QuLw zZ;hEzT@K^(i7VzzUIP6h#cwnRY#KXaNY3UN+qVoV+Ecx;WcLQD-`wTfM(mlq8T@ta zi1lq)UjrA;g84`HlB~(Izz-qc+1s$csmjH1OXNrW%U-Dep*3R%K#2WGHq3*{x|`Gf zQV{815u1Ku>R{KN+7V@qOTaG$e$gKS{_ynJn2K1_F6dv|x0G(%Q9Bv@2A&fi-Z_Q# zmXg6RpGqysZQV0@Luupk+7Wvv51Z3f59403nbTYcegXNm&(9iBK4s&a?(}>pWhDw1 zZk*9If6jgwpA`6)v6Ap~C|{ud0bgDv)KlA*Ia_P8z)w$@)>RSBUo~~poNXJ%9@{*1 zSecBsYgz`kZz*Z38`ZroXXCWyN*u3;KzZmnMBJjDc8KS&49iLLOneRxUGBA0L(0AB zaOIwPm~zkTUGB-7dzHKW5an)HmK)16V?u1_hH351xolkrjQg9icCE~*hjF5I#Na6> zV80pZPvc_)_;uN~maOT`?L+2Rh2Hu4(CHoXp`SGQ{M;ia=0U|3+1Ot#hWSXUausW? z*_@u==UYbw?aXARjq{{ZF%KKo4fEQ3YZ8t#>&u%q9h|$AzgN^Q99%nWZc|lO$$}}H zOSWzr)Vim26yk&TlT9<4TLu-y#+b40mg5HC^M&z?r&RcP=s)scemoAJH^2qY}sJa~_Si%eNJ+uNgUO+lGVv zhnS0aKe;yNsJTt4Icy2kAIJsgn;;i0-Q9e!|N1FI#rzB8U_r7pz1p~F@6OhihL-Ni zj<%gGt*I3|yIVTiyNdj5WoxplD`w=tDr2}_%;;wt{T0fladcX9XR={OvN=`M)Y;Ki z)!x0jqq+swM3b;kS^%r30jZcVz%=rLq8=Q*tgUNl?A{(T2Af8%RO4}`G3LbN?qqRm zvb`DBVRv`zNEO$ly0>>UE={&Kwx+s@syjM%^z4io!@z#HXv`R48d)T7!g4IF%@%d; zZfM=Hy|J?>W*lW2amnJUuoP)*YD$5?Xjs$j+|3!&C~%WIq=_-6k?7o==6%`V+HhAF zSQ*c=5v*wp4lF(w6(!p{+KWnJ#w61i*q&@_X>YFVfHmm7-9>H5hR%+n64RJgovw7b zI!%(rwO$2it5j!GvH{nUt(FdG7OA(O2P+Wbb5re&^~uJ@&ib95srojEkTPpPzn4TO zz;A3z*6-ZWUEgRL1Eh3McS~#W+GJ}>Bj`*}L?2t-(%#V8)0pCG?Wo^9_c)McxHOJz zTYXErhwbDnF3#7dIy*Z6Aj+6V@nLPd;*>)iZFF{(AYh(bM^h85(jyz^(e<6lJ*MHf z(NQ6t-PF_CO4S3xIlP`+seD;?Zd^aEArmkQ)N0tCYS;k}T6Ma)WhB%t`uqwZffbQZ)|92s~752 z5s)$rQ^2p3i9R#XzK1XaDTg)#iGIuw(Hk>F^7ceDgbmvB5ZOV>p|e9j^;Ho>^v(_< zePsilXW!ab-AeZNMl4-#K)xA4ZkjxPsZdxqgBgT7TkjY-Kbaj2j!iB5qmjYIo zt6l+!c-pE}6&vaoE;@eoQm96ZS+W#_E9#ckLubm;5p`7?p_(0JiOgQGdV$w)nj^!= zc@5{F^n%qDOX?S|s9p%rB~R7{Adg9<^;NYC7p><2gcy$~;rO|l;4veYFAb!Z*89`T z0_kNu-N9@LLGFSzRn-gYE0!(*ms$;FO^Ar~RnwtSBvW5ovASw4q(f9){qd_-W92Qb zSW~?khBWS#6_u5X>gssiOjE=`t@e^DRm7Dk;s8l6-5H9wnToh_a7-`0MYRpBNXcPmBxJC&mTq6XSyQ ziE+XD#5lm0yRfpdrhY+1?eh8sRjcb@IHL$o_al14>P7YIsutqYMKQb$L<|{NR9Tr8 z$>vJbG~i;KTkO>!8}y7&o@AqT4FLfVWMkE$B~>eG(~#;a7Os*sf0W4($05MyEUc-h zU$ACzx-&=+UsqoR4=hVF=<%2bm#wRZM;b<{#T9j{;lW+KXw|AU$FHtmwP<10szsIX zMC4ReR#YxsR9}jf1laNf@2Rs~ZxnV?z6gAZ^Su(H=DddL>ep2Orv7QMMHQYdPYPlz z)mYjduUFCY4G_vaj;hz2wYLcpLKK?KEnvFI3Phs6(L^NK#WFGxQ(aqMx6!Q@-iiPe zYO0@*z$hplwyTI)QCkhAO_!^#vUXv8HPpW=Kpk2dN!{v-)zDK>(bHPk6N{3ks|};v zf~Ok}W3eLAjRH`Puc%zkBmBM(MM_6t2_gG5>spOdB!51jI3SR&H{z&-yzr1ldcw=O zw8zWI6x9VOOONNG!sChN9-pXMyaxPR_;Z>O{+wpHKj&A~fhJ8eERL2QIgI z#p;S`?6{%j(1hgEwUE1N5lr}2!xJy2NpXZNo}p|(Q&l7cM>Vm!s%Fuu`szhX!2Ti_ zh6->a7p+eeQ2=#3WxQt=&R1pTPVmH}_kNK)OlIx9_<}!RyjMs}=kv@sEXvSJKxa>T zcS~EUxURdirvbK$C0i?#t*v#iE)z4eVHDif(b3)2-I?5J8W(#Jgsh@?Ul+hEtUGvP ze2T00?M#Iydf^MzG{Cvc%rSElCNul>%QEv|n_F_{&enaVQ3QoPTO=EaK9p9H$^|Y^snktH!L&4)~RxDgoy{HKG_XV@^%0e!~%@J{P zm^l)>3ttfV8+xN-!Xi=b&SYn@Ed?*@SPfmgu{L>{lp2|th3064bqsX%?wc8{%b8=K ziJDX0)as`3Id2n*y6t$v=tZVsjeS4){8Qy4>E;Seb-15@1IM8>W|s!&4F? z9S|RO==`zM3)DQQ4soOWcw^=))iVtJv+DtEjtM5bh#^^k0jhTo06lraT?}%}&-t|> zS!e^*TO0a(R~zz%Zqb`JBnxezdTYbzkjwqHrJYuVz<-zdEr5uy090=aFqZf&00x*S zc`<;9umDtV3o!D~su^I|+0sxC5LWvQfP^prRBr>&CO!jz0A_|>1Rx;{DBEu~Jb(W6 zH8634-vr1A6F~Jxx1c98-HpRo-oG)`02_pR>UZN3CoULbSsDPH*L^|I5w3|ky)A*q z#?VS?Z;xYc4`@STS{q1(Hn>+m~08*iVuIE(%KCJ+xLIIq|rvQ9fLFree;3HlIlo9x8T*# zPztN%u%70a7Y9tZK7_&w6W|xVJYAP5Rk}f1V#4fRb;j`_8K71u>dl`c{m za1rFw4XAXHQt$(Yzb$m8n&DSF>_Wa3$kTNi6z+|@Y?@=t_v@6oeuJb!2V5bqrK`TH zr7@L)AF~>|yYLZuAYjJzoie5Glm&bTc~M*>75RcYc$=ln^%Nu(3IR_kb3Fw~g+jnn z%3M!DQlSv=lrq;-kW?s?JI3NbF6D`{~NIpAHQihxvGW zJ*?fQ9P>8;eb*IGQh_tz3e#OzKvJOq?M()RgP(6Z9SgQ1c=4ck+Md#PW`K7LQrZJ!Spj3NQ=ysy9JmTM z*4WVlZ#EuqU<}@SeaKu7o1yfu8Q@0bFdc1eE#38CA}?UV^*Iz)-~l(1^BT|}7|?ee zZidp~W&|7#`E+e69c~7A75{0{{f!&4g|}2+$z3l*c?Il%7tV0K5J`nXzzb)%UWjCG zg_+=6UP#D`f+49;0O#>3xPCQL=~pwsL3|3X?_iQ52XF$Pg6khMmHsgkn%t-0dIKgY za)37WDY(r)Q`!781I>?ox|Wp9KNFhMmxJ5Vn52LdXz7`5OCzaJ2(|MoKvJOqKA`U6+Z-$KzB|ix9V8XTz#nA)4Emk^3Z3P84w4Fe z^c>GS;4IfokW?rH++>#PCP*q2z!wrttvy}aVbapG)3FW&a&+BhmeOrzfhVZPS19l4 z0b{NMp_&3sz=3AD4uqsaA>cr>Tn9o@p%8GOS*`;i*;`?Dz=4n#4uqsa0X)ImX0u%< zK~kXrP4821y<)b~D`p400{Ju~rB}>`rf2ZFUf;1B#%*{BbFAwEdAfdr!U~Yk_&$)X zU(8ne#cXI`pMu-=n54)78aTbUAo`zM0w!EzmfoAvXK!nr*TBQRm@7I9{sROi12O8h60})aOXq67MwqFM# zqz=$39cXaB4n#;DpjA51=6)TBkUBuCbfA&_IuIdsfL7^1JNtDYLh1mm(t)P->p+Cm zQTstj&<`*ot%I~8pAu;5D9!_*n|&dWC8kMrwM&!)T>>Mdj@l(kf-Zp(Qb+9)B|(?K z2&toXiISj8V1(3ByF^LQB``wjs9mBY=n@zqb<{3V5_AcSkUDCYC<(d*Mo1mCOW>NR z&y6r5t%J0}C2*0{ujBCpOjPLv{QwtEWj<;@z=ctNJ{~{7L{&aPKfuLOnUC5JaCy|9 zkH-%%QI${74{*s;=A-rlTo3i<*FgRGc>Dkp75U&As80tY z()l2*(h2$ju7FA%wIAS`r#~N$A7G*?pP(P$I;hM??FYE>>CeaG2bieJC+G*b8Y=Tq z`vIbTA@~8EKVH&_8gYRO+bx1J_0U`FQ*T6IJ;H{ev%~is=o~DxIKz;QFY< zruGk9|IBV}?1GOAdXla1V}Ly`2-f2;D6Psk=rFiQDl=9)3@(fME5+k5n5fDJe8T-5 zywkC98@G23h)bt3U$q0_VyUOVV5BB!#N#^GPo`Xx7{(L;1gNdqqz#05H9#6rgPL&R{ymaSj2iHdZIv#hyM3qj^U2uI==A(8OT>cDvj0B^@mx7sld#b>NCH?hbP7Zv=Dpco2%Kat4p!lM?aySUr6_ z=Gb=zZF$@X*Hu-vf^LM%sj?JmH^K!}Uu|JTS_f%GKDbWm*YUU!CaQFTZiI`aG9R@Y z;qs_IACJdiqADM7iWsehLW4XWG~jU`TuW6M2)Yk0nM$B)_rZlw?Z(d7=o+}bDzT|u16Nf2`FLCd z6MN@V8eC)L5h5Q>t8}2Lz4??*bNztRDxH8IlumQ~fYT}+Xlj0#s@MrAy4*-Kn7!*B zrPGw|Q93Q)9y~%8Q|TV1(*o|nBczVfJxZqq+=E9*9i@AeP7AmPkB~Y__b8nfa1S0K zb(HQ=IxXNHJVNTI-6Od4TIyMP<+P&NaCz0|9-j5qQlwQnLHF>ix0WKU(t)P-=i~7M zTzggN1pUCX-dc*ZN(Y+S*Auomkx9XA=6*|Es*iz3DET>gELD#@#*L1z9mtaeA#nso$o+VhGsLChk z8o2B#^HIA7uDJU1fe5Lic8%Z?Y$--a9kn0eimN{#h>$vJKL{?tmSTj|QTqX|xcc*f z2&tp?gWwWuDMm;gwI2kRU`stqu$)%353acSuz8kXOOaOT1pNS)UDMdqOR%N5;_A=G z;|G|i$|vXtxa=zPQTqX|xcc+)_yH!W@(KC@F1yNnfX;>kUrOQQuGUl%&Ps`lubKd# z)|%U33hPOL&zo|_rw>Y)3nDDCE7F;5IFT;U>4t;N@zWSsO)bV1Rq-(aeAg21NgILV zbjHhLR`@wE?ujl7Aa@W>NMXosoSR*!8jI|UoPQ8;)uFNxht`-$_^A(t!Q6NkT(}yGoEaFQ!r>9R|)bR>B+aZI*WWh@&(N7VrW2U#7I+X z%TD;7iD#8QDJQwNrM_W%vb{ak+68qUMH#SsjNh_SnnkXNT#5Ft0yjj6E;jh}e|&F1 z_??VT3^E$wX4G4OMXrrphdIFFKn%|*sjPsVS$Xm+K6y~d#z54kdsKP_&ZZ0m;hg7ZzbC%fPaoI^Xha3yOee&yp;f~+(go~yIS*CV%K#<0AQ z@3m3i)X~}q%Ll#Uidf`Zq;iMImVdoOU~^Gi@*sLQiQXfM)x5n^6l-$e`8~|@l7;s1 z_$3=mhE0)fLyGZ3b1>UD z#q%Sd`u7%vl75d&eIGo`m(Cy1{9qI)JWf^f1Q_q!y{!{!Ed?dZqOYFd0hf^=`!pH< z5maO6?oK#vEF};gJ-(_}pFtm)a?dJ-hw`|?h#V{Hi1(a+jvuyzhXl~K{0=Air~DCY zW@rg79%zXPZc7{n8H+q0c>!zx=e!15yF?Ax@cjudzKDV1|ALDD3iK46yKw;nj#q0- zb~nJ|F(=fI{DlcLKlEv63j%CrsCwkEJB4F{yqQ3$D&0~^liY<4!SR|5WXB?JMSg|l z{WTOr>WR^+UqeTGQ%iGCXA-xKH}5fx9d5xYTRR$d%#|wcJsxhHqUof(A}s(79xK@W z1^;$-b;F|oCw;*{+tt|sp8@Tv$K#VAvMtrpyr-eNv$cL_M=O6w`1BziNdpY*jlzgl zaE!b_iJ%s{6}5Q8%f=$VkNg3v{g2SFvQ8*l7&&E(r&jq>#=k3QZ-8$@pk5lW4**wp zBf%^GMi21cr8s=A#l@GpO&8`QinPG6U>c`?N~YY0T#>7+14SBk02V$JSy*7Qg=BtpqVeENb&M ziAJP2f#c$uT?I$n>j4pYNpn!#PueM{46~>cjbi~59I@NA!?cPY&X7JxQBjXozRJR` zetD?31mr_q0-GI*?85^^h7a|{F=%erqk)V?`$hAxl=(0T3R-PU@lyng;LXM!KLI`$ z8+J$uK)_rC6RKErU~~}L9n1%e?mZn{4RGoxOmsVUrx|dHVdNCU!FSts@C%S&OES#) z(sk>5^c^7rd6l@;+3N}=I3+`&&Z0*}kIpu-qJ_-ZY9!-^6+MO-4MrnUV_+_xKBx|k z>jMDpk#gxX>X?x-not<_jSNf+7qyZ#X10 zXp~}$<}#z%*p5a)8H|c(uTd5)BXjUn!E8jF5K6V=f=nMA3Iz zhb)34WzivdIIZ`Vna;;!#tx$uZNW#QFtg&3erOeBXaStP09cCfuO5!agaa<>i};~X z=`#rHi&DE_8arN`&>-g46V{r>CV$+gIKfBjBYVM0A5Tb#@HKcXGup@vs+iGE)N*EY z5LLsBokXo*#x9~(GNY5II%aecwT2npM6F{+4^bPKv74w(%-BQJ7G~@vs-7A9h)Oc! zB%&IaaWYXUX6z@bnHdL&YGKAfqINLj6r$RgaVk+A%s7pxUCcP0s4ixlK~xVj&LnCN zGtMGvA2ZG->SSh|L(~CgoJ-Ux%s7vz)0lBSQD-pY0;0}h#)U+k!;FiFI*%EjC+Y%b ze1WKom~k;tUtq>1L|wv+ONqLS8J7`t1v4%u>MCYjLDV(OxRR)AnQ;|SUt-49L|xB} zYlymm8DAvoMrK?~)XmJej;LFh@g<_Z&WtY;^$liRPt-S=@fD)(V8#tZ-NlTr5_JzV zZY1hHX52*71I)OYsE3&GHKHD2#w|oW%8Xly`YtoRPSp3AaT`&OG2Q~Hon5f?{;}N3XX2!RPdY2iG67?Q4zC+Xp%=j)*zh}nxi25Tl zzE9MjnDGOm{=$sMi255d9w+J}W;{XEKbi3)QU7Mf4~hCOGoB*qf6REAQ&}c6engbb zj2{yfWyUi^#hCFEqTDN)(Xc$TOfX8eq(e$04|sC;HTPgH+qyg<}IX8fF}!OVD( zsG-bwiKyYsc$uh?%=iUSM=|3Sq6(SuOQMcp#;Zh)Va97jjbp~^L``7E8$?ZF#+yV< zVa8iT6*J>kM3pe(*F=>u<2OXjV8(BWDrd&qM9pT#J4DT8#=At#W5(}@n$L{)h^k=5 z`$SbT;{&1=G2=s`mN4V@L{%~44@50z#vh5QVaERvwSpOcB5EZw{!COIGyX!<8fN^J zsCCTv8&MmW@pqy&G2VP{7iQ2_Xi>NL*44$YSW=4qG!^|jA`^31#k7aU4E`IPU9STdM1RvZE zB~-nFgvR1fqY_#rkB}w7F^3RzPnIRQV?yNclroY!>JU<{gc3a-L3`LDriDU_h(f_4 z@|i%eEWh|>=)}X+t2h<&lL(8t)w3*WS5H{fub!}|VLf3{$9lq| zmi2^1Js+;2@dV9jdaZ||n*NKTn*NKTn*NKTn*NKTn*NKTn*NKTqFz<~79AL!K24e` z^=Or!<3c!|9ZDjqVL5R2^kD?u(~U{+kl^G=)g-4HcRdGKlaQ)c4W4U#7<}$Qz=y#n z&j&sXJ~|JTgbrE5b#P|(;Y8#l<&cfwp0G`}RKqPDrY#QMCNb4`l|FO3Y9Yy}rcY@Z zJd>5Al#S$`-c3SN6>fHjL%m5sRSa=HbtymVo5WO&FT~^#;3TQ?Ij>}T=5RQ<^wdGs zae3`gyYNMu!+_++ixWsy*O@lzId%N-WltYQPLd&5`J>5C>LyXuOi>`(8j88qUsE|gd@s`9UD4a={@*Im!va07s$Wl?#?XGfmA;=F=Cvzc9$@>O8Tm7&Z zqa+@=PJ*iEM`Vnrj~_N)c|iMN&AGGMkQ($H=YH6%@$hz!?}T_SO8Q+Vq^(gn?O`F0 zqc|#_P^#r{9P^KN>Sj*MrJX@tKWQm{K~()aKU~`#LDfwR=Dc2gNFm`2{0ULJGgu-_ zZkC6vkH8RiNc67n9TM2#Mmc#-J~h!HvvU1X*-6M#^~sE~1%*ubsN^|=pG+zH#o*EW z`l2C|Pw!#$xM~nG`3#DNOg@96A(PLbXvpLk>P42p)lJb6VA`|{LVIOOH2w{XbI zQ*U8WzskAxtd>Axtd z>Axtd>Axtd>Axr%Qm?(PaG-u+lwvLd_buSf4kV!J((pnCy5xXlR9#wHCcH~aOW}~o z2MATak3!h()2$ICr<&&lXsBYX%I41-%U{8s>zJ$#tbwKKWdc| z1wU%dA`13NlxWy;PZ-5pG?_7*w8t}JE`goMjAMzK%#3+NO=ZS$L``GHe4Q z6#Oii%BUE5&e~v-90sN}krk?g9 z*;KfF2EWeZ9~Q{iSnLe254%iaXU5Kg9ZIgA_m8%jsxZ7#73hY+dOvf}iG#Ie{V zUiEY|SHCPCyEJw=Tu2OCO=JdX33+R=xEC4fdr<7k1ZcqCdvgtoU4xnSkA2ZJ#-=ls z{YzIzPiI4_rM;=6xQ>%>O)gaTb&e5-Tj#v@t%!?Zs&KOlG}rZs*q35ofsY~5CJ%8j zbS(B&s8rqSwd@>&Sn zfZcs=NVV;C7(cHxkg&w}XGD>jm8=7W)?LBa)8S>o#3*KIlit zH|~No6CSTG4X);dahGMEHg4%Sf8)4?R@glET&!Uy9Scm&cF=Z-S5*iT^__qLX9 z_;ScQj!~t@einN!5qmcFJUDFnTNM1V$TNb(Vm}AX;F01i_7VV!y%>8r2naqai}IUR z{Q2>%)-3kR*sGY|Yp|!&-v%(~tfV5sXX$}7=w0xujYIY>ZfW89EvMRmL+j%W@Rd>u zuXkteFwJY(nkQtccx%_C3HN$gY3k%I1$GmsQ2Ts_hKKw=E;^ey0jhdxf<(z zsKwo0-dmVN6pQ^n_J;)M!^UcjZUY~aSnN+Qfk-!>|51s>{sQ|p8$0TgU09eEO{Q_e zp&rdo>0ylhE%x_B?2gz+z1jkvh*?y_|LT!k@_ z*-dgsv-EvWRdAJjL$Vt#;8>mPglo7K?QKZyL^cM;+Z(y*`lC5q%!$AjP>|x+UC|y( z*CgG6#hffBmT;nu!^|wWjm)qd*l(QYicyosAlb;G>(ESNw!#g(mwttKhLh{`OPI5r zJb?@^0LQ_?>qTn+odKRs5uefphnt>-)ft%Ky6Y-hEDR1Ciwb=Jcrf$67Hdc(qf_=?t0 z3;(n?*L5cwb`-^&jnHSxDNmRvcGJ%0xU zf*Gv?LdS&8f!DP(c5jCfbf~i%<@bO)t;2b}TL-c^;P9o+?$%!0KT_@<||6#7df7}9DgKa;rd)0F={^UJOOh# z=Sjyn7FK|0NO{^ZU`gg!VxDn~s&Ls}K zDM*LKmWeq(PdG24pByCpmtjST%)SEaNJPB~YfD7E&LS^G?#CYVO~?2gGtVHUUqipR zJ=xmCoZnJ5Z!`03N_rQP_P|mIbKaw*_eJGxOLj8nLn_UKAePZ%)F4dOgs;k3n{t)daokLuA`l=Qp3lQ>BjkVp69hJJ|I3Y z;S7$$EV*CWc1=fPPb=Ie93KMSAafM4*y!kd}P0@_^7+Ma!Q=T z%&UlkuJCi@jnMU7M{&>}T~E{kW`32Zh0MH}sKv~@ji{x}{3cP$n0Yr*)y%w~s9I(| zLe%lh{0>p8nE8F8Rx|T)qSi9=heWMs=8uTl$jqM-wV9dE6LkVJUm|KNGk;0cHfFv- z6x^cyYoeN%`7Tl09i!SYY8<21F;+On@s6?5F;+PS%+%!y(Vmv>?Yw&6f#~#(VQvC{ zCc5MCt~h+W@jjW}!(!*e&c&x=A2`ZMd9h)99@KknCg>gLJO>Iu4<>q^4v4-s@8wIX zc`q0^H348wa}21&KN6lZS?o^2b2i{Pr@*k|2OVP#GyhEK7qHkplztJUf4;zoU^-O& z-zfc37Q3I)FNgFi3XEv{AoR=eLCpLINnFEX50S*RAaPxRkrhA4%zsnj^~^Gex`A0y zqHbhXf~cF}d52-Xr#;!ZufAv-98SUFx4^s#?BB|)ek61ovjz}#JAO{zmSpj7@qsIT z2eXD!%3bg|P!wNe;`cCX1jXG4zk84aKLEdb5cLqV3MuswW)%_jD6_^9^<5aKG2@BE z!X(6LO2Rqf@Vv74KSIuBQ=&%6$2U#b2h3e!(nSNr?XvaNt@kslG<4uS3V}R$X^XD;_rR zX-;!#P>a7Ae+!%ASIk;KNMYSD)&|ZC>oP348KQFeSg5LrIhe{ z7I}_@|H!Q66!#})9Z%F>;MXeB_#6C!Mbt;kT0^P-WEL$5#Q%*`sVAAWi4s0$v2SzN zOBnsK5@vxB1J|>*^29`h#lB04S&$ejFdR&5pu_}={eTh~B<2(taZGHY#5@*zf)WcL zv44S)z{D0x9K>QzQQ{Ct99m#xVK)8WJ@X3?xRaWu1N=9n1Gto>x9h*_r* zHI`X4k4uba7ERF-6PZO*g2ZHe1AuvOY8U-~Bqzf(`ASSp6hj*(rZJ1gi$p22E+wqf znRNwGGnsWYQL|WdUi3J4@)C2fZGO+JYbjwKi|mQ)#RT{|I|?h!4RA_GzUN(;dN!7* zNGw39N@jh9G#8mhjXUEJKR3(4)Bm<3y2tbsh9|mj(CMG5&4R=d_+>A#lvy`Y9?O{Z zHKM9n?8nrewa}g`3Jiwr`3*{3#jI};wVK6VA+fa}wywa)L9x3iaU-+tC2BK^y+L9p zfLMKjkqctRbiN>**amA!J?&jB&Fw7F$e;2AJhbrK!@>?rG*irWW<5Z*P86?yjSX=2 zE*z)A60In5SE7ws50gj-jOFP!#658OP>LmXkqiu35qwKwiEgsn!>mV1X%CCPi7&4& zCScNRZQI8ZCzHs2W_^!DU<^v6?RK5S5~so=2^pWptj9>;3}!t^)LG1Wny7PNR^(a2 zmTyLh^T_=9%JeptxRBB>a*TD3vEDH@FzXpIc`37=CF*i!(Qu!*l36cP+|}@l1@^@> z<|nRY*6Wn;C1$-v6pTN=AqvKycZj;t_Z0d4sn1h0dWxLK6E|Z8e~nr1QKq-Ts~E+> zc=jR1-Oel;r4!#`7LCV=JDEizZ{lud(FmKkmsvENChlj}$E5opvrVENX0czzevOaN zx54Ee&5IpXVDtm8vm=!LeP+jqdW^;XNs>>1 zIL0Psk0!A{FnbJ9{|8$V$OydiZf5p)ivAmmeM}|!2ukvg0;509fwnN42KmH)m`#Ix z;$!BRTrwL5oNO3y24IS)?*}1SyhQrCu zV|E3{l3l=TTAa@wz?`GW$RIE>xWE{MMwXD+FlJX1H3D|nkdaZ$UP*CBGkY~rqnR^_ zj1+;9F$Kn8G_sBo$1{5)Q4^U>YvkFJnZ1qTrZPK4)HKtmayw-I8jSz(3Ga^6@5$Mv z&>3f!F?&1NpTX=MM3pnUov7K&rjayzF0;ESZXUDu5H+9KClOV_oM}|RN+{sM0%Hgk z@Bk$)VfN`nRWWAH=dZik(G?E0}#QQ7f4#C6QRn5YfR znNMPyKx}h?F&xD%qr`e$j1eey4J9@+X9*>?K;nr7#z=I!6PSG+ zrMENt2BLN{`zE3~nSBdU-HrkI+(yhEX5T^7K4#NElzlR@X&A{qz-$^VvQJ?)4FTDw zF`Ih&>@%26U3&Ie%zlcjoWtxN6LlW5e@4^=%zlxmiG#8fMdLS@yNCcZlM?#BA!Kv#)11b3Fq`_#>>HU)y=C^z%%asO{S9VQZ<+l~W>asOeFw9tx6HnaMX0yTzK2DqU(CLbMdF110Ty9I zJ;WmYhp;97oivEFyXgSTPhm#+xi6 zx`$t}$TE`q4U5ze^)`zfPt?0CQb*K#EV7oU4_IUaQ7}{AOw=D)q@Jihv54pu{=y=n zSNI!?i0Ahs77@?yKVgQ`nrd(E-p;cB4KHNQrtJT~@dr*etkxy)cOBS4(A2UQcf)xW zXVSmrtYyq#Cj4~6U=c2FX9uk9b@z0(i(jowW35+7{MsYug>vK${e=lu?c6n<^bbbR z{850)vS2!d2YzSq-++Oz@c3@xfUxjjZsLHj@W^fAfUxi|ZQ_8i@JwvtfUxkiYvO>g z@EmL6fUxj{YT|&f@a$>gfUxj{Y0e>G;d#--Ar?FpnmELQ=RFgLSnz0P;t&g-(M%j- z!Q+^TLo9f%GI59nk5DEKvEW(A#32?u<(P9wSa@bJafk&^BPI^9;5oy@Ar?GMm^j3O zX9E+5Snvd3;t&g7uSOhV!OPN!Lo9gR8F7dOFEZmC5*A)pMjT?n%g2aAEO@OLafk&k z4fgvEO?g`afk(Pj3N%P;Qdd;Ar`#Zi8#c9cQz4+SnxI`&LLspolC?a7Q8`; zIK+bYBoT*L@IXA`5DVU8L>ywlTZxE6EO_@2afk)44I&P);N?KXAr`#qhjU0+c!>{j zhy}0eAr7(N9XrG!7Q9J^IK+bY;t+>e@b(+x5DVU1LmXnkyJv_)EO^5Vafk))i{Ts+ z7TyFy9Ad%yUWh|1czX+Rhy|}=Ar7(Ng)77%7Q8HlIK+Y%o)Cvv@G2AH5DQ*dLL6ej z>qj_;goU?=5QkXst`Oo73*P)e9Ad#cJ%~drcykAFhz0NAAP%wM4I9KE7Q9D;IK+at zVh{&}%`X*>QD+BefCm(U2MTz=A$XvG2PA?A3V6UGc%Xm>G=c{Tc)%lgpnwNNf(HtC zz$AE}fCp59=lHNQCLSrf1iNFwb9~q#3!dY{E?Mv#A9l)u=lHN&7Cgs?9kbv$KJ1zW z&+%dBEO?F&yJx|3eAq7&kCa`4U9{jiKJ26g&+%b5EqIO(J8HpmeArbBp5w#LTJRhn zcGrUE_^`tkJjaJ!w%|EF?5l}K$}YifTksqocHDyJ_^|61JjaKfx8ONG?7juh@nHup zc#aRdaKUqY*oh0Cec#aP{bHQ_b*qsZW4N9@ zuu~U2$A{gz;5k0**agq=Vb?Brjt~2E;*qjTuzMFg$A=xf;5k0*;swv~VJ9zmjt{$e z!E=1r(F>mA!>(TN93OV}g6H_KyB9pihy6V9NZBRW+C1<&ze_b+&k4+j9jb9^`i2%h7^zMpuc>=GOX1kdr|Kp=RI4~GK5b9^`$ z2%h7^;Xv>l9}WnD=lF0)5Io0+gM#2WJ{%SV&+*}SKs-`*2@VZ{=lF1N5Io0+!-L>C zJ{%wf&+*|9A$X1t2MNJ*d^k)9p5w!TLhu|P4i$pu_;8FM9x1y7hYP`Td^lhTp5wzI zL+~6Q4jO{z_;A<|JjaIvhu}Fr96AKg@!{Yhc#aQ;55Xfoeqj>lIR$(gAE$s%+kld5W&I%q zyu^nT@Dd+Vz)O5c0Wa|(1-!(E6z~!sQZ~QNgz)k4gI`r5cwT>U{3t~VtitSMNg?Sfw=s^Hd+PQE`p1#E&o?tyJx zV0Gv!s@b(IT`gdwqP@MNo9{;l!8}+j?C$D@Z8u~SqWaZAj>)R_R=|S$@8G9S9s}@= zLc=m5@RwycaHwVhevSxxObYP3Lmt8>hCGB140#CO1sZ0~t3X@EOpt@G1ARPvBk1Gd zt3S!l0eSfLkK2JS|9A-B{qYdK`r{#d^T$K@;*W>$y&n(ZYd;>sw|+c?FZy^0-}CVh zzUJd0e9Ol}_>zx@@Esoy;VV8KR*Mk6;Nv`ezsE!PdXI$s*h@!UG~aD8f@jc&Z3b6XEG1JVS(MitsEE!coM$9B>dZ58)VM z9>O8SJUm~7Z~!sqFBIWLBK*7vzaYYkMRW6C#A8fO)y#AYdNCF~B^8Lx6esBN4&@z?^?Zgg+7CPeu5w z2!AHR=S29t2wxE4&qes62wxK6%Od=R2wxH5FGcvO2wxN7>mqzZgl~%QEfM}ogufQy zZ$$W85xy-#ILeoo3l8$-Aspk&Lpa2jhwqCJ4)Eptha&vF2>&3$KZ@}GMEEBW{#k^7 z5#e7&_%{*$U4$Qr@E;=lrwIQg!hehKKO+3E2tO9#|0u*`c@ZaUTBOhtp)JCQ2%{KU zm%{$gEHh?UIj@1%ei)f>$K#ZT&4GqdJ!#_o=8&4nPa4t5ciwG|n%LhwdeZ%7(fuaG zPpz3Waq|6U>AJ~xf`Xm%I{ce$nEy2jVkV23vvb~nh%C6J!Z3c5^CtXzG+2%r$H)UvbM!$Sn+d4j`asQ-ppFXz1zVSNYpNm> zP;dJ{Es&rp!$85$B)Xs$X9DUSAE+e~)Y33eRr;WoX9DUyAE;^xswNB+e9xs@Q^#il z>U|%ml@ipdFi`NDl`g0?nSlDh2WqVZwJr?QdVNqEGXeFX57Z_JYI7JU_$^oQtrAo+3>5r;s0*qw6HtvlP$>zjDGXGzKB$(ygE~=y+7Sk-RUcG)-$8XqP&>mw z!EOxQ=IhD?RLa+U-4aw!7^vO)pfd6)Kd3zt)ZQ>q`}9GboJmb>_tn&X3F<%?sDt{T zPVGCW(-9lp)KBgAf%=LBbwe1auYRVWZj_*I z3IlbsKB!wV@u>s8nz~hj`g#~B*e0p#Q=bB;Z%9zLhk^R0KBzk~si}j$nz~bhx+@IS z-TI*J$pq9XK2Y~cQ1^v_x?dmEgPDLj)d%V!3F_f6P>+13puR0ZJsJk;JNlq9T1z<1 zS5x1WpuQId>ieH5s2@mBkA;DHTpv_MYYC_OYU&9I>d7!rKm1HVJtaXs9R})0`k;QC z$?a`mj1k{;6P(PEPo(lu@ygsNGG68j#57f^ks29UPy`&H7 z`)VV%TZ%I(U3Ip|PeNey6 z1k`yxP;X06?}UMR_cI0cI|=H&Fi`L7gZeO&n!3VQQ@@v>{tyNVK3LK1r!oR{r4Q8q zNl1e+>f#pYa^gn!4Ht>hBWNM`57gi=rb6>KY%Ye@amQ3Ihcn zH|c`pLh%f{KTMO6Y@P zeFv2zLFI;lf{)&Gn=ilbpb8|Y{$Zd7=z|*6cTj^Rs3BpXhJL1?hDlJv!$6JD2Q?~_ zn)-_G={rh-Iywv#dX?xX%>ScnNAk z7^sP#DX2*j)Z{Qw@Ik(A^JV1dH~1WVssvRW1`5sw&;^yzFyjYRB0-ggfr2v$bU}Rz zH8ov=3froL$0F&1%IN9y*HpO#H7l&9X6u8>sHVQ^^Qk!!)Z8#o$LfR1sHXg&32I3gsHOU# zGHSk?eKl1jK`jddwOk)mO(s(pKd4#>YDE|*I442Z(N|>x>TAB5s*|8rhk;t74=STB z!4FDqf3w22zu~!Tx;2%Nqx(T^kTtb2tfn^UgW8fw^WExez7r&<`Y=#ik1(jO`#>cn zsBK}O8jdii+kBuJC8$&wsHP(f>Ki^#%@Wl1FiCJk3-WR7U;O{XS4~qo5VGQ4o(e)dXc`^xez@K2R4+N53S@(J$2o zWo6WPKIj8=nFMut7^o}sL1ol@eo$9RP*;V4x>_GpMsG6@`D*GK3F?bspsv*i^`%Vu zDL<$$OHkK`f%=LzC^Mtqko}-;kf6RA2I@v_P*z6G_pq<|ZjzvG4g>WyeNeY%(tLhU zUzeb63j_5HeNY+I)FZx{x?O_$W*8_q6U@B3=%K?&-iFi>zx=@A9>m=Dw=64bZD zK*52jM-O8B&Z*UfqF(CR7T%8Jm&-T6A9|4VW6JX2bIzHeST1KpQjbJ z&lAs~*L?b{pJy^l@Pm3$*3?U3HTAMKC^Mtxd*0W4a-XLaw$Bp}=GU#MjNWEm@PT?& z*3@fZHTAkSsLX2WMIWd)B&avTK)t06Dl?z*gZh;O_3JQDztIPk(Nd5f)NduIx5Gfa zqYo;hr_T@ST?y)UVW8gA29?=-$`9&&3F?C|P#@}p%BV|t$>->DN30dLBNi{b(Crd3 z@+m(kxg*vJ+YyU*Z)k$btV{5Nk~?CpupO~@4TvVF%$9;)_BEf}5o?9*h{YR8bU|g* ze11@JN30dLBNi`5(FK*!FyjaHANlnCH|**A_y~h~#n*iQOM|lE2JS zsDWXi25E!JZ0hocucqWKYddV0HQo@V>FA#ZD7nkp4%=moH&Go?P;dHbYNTwwQDMz@ zls>484lweAI$DA%3InHmJ<@CHO(fqciQWqcibNLd}}W?8U(kYLTp|#bGtI zL>rV{l}Yoxkc7^s!npfc;H{57>of~pGxwOSigWVwK?KII1`4;i(?4jIJ@Lp8euJEKEJ{h+qW zno5S%)HZEURz@3e{Gb{nsKzi*DQ!@hZNTw^YLcLu!$85^jhfAu*?{~zpQE=(P$!0g zf@>r-L1nhU;Rn?!LA8Z}f*WZyL1i{e@Pm@OtnIK})_6ItCaBCD-4Ci$)>KzmO?7L7 z%FNOIpn4>z-C>~i=!44WENkBZ+xA`wYF`+rlk`Dl^fu!Mb+QDtKMd3XZBX_pnM_@L zr+(X~N>HbTfjV6ql$Fujj33k)64aStpw7|;WoC5hx9=!&`)mp7oG?)5>VwM2r~IJK zlc3HI19gEmDEp#Je9Ct|y8U?x>I-3@F4hK>nNRsaT_QnU8V2ezZBS-L^Qqta2IR{n zs4K!iU8xT$BcJkvx=Mn&ItXhGsGB9IuZ4lSMH^IRQx`v|TP3Kkhk?3H8Lg8Eh%s5|sQ-PLzca+kFow#(Yq-({WI%{+hg)s)<2ZHMi$w)J;eTN$0I z^miX9xy#xP+huL*@3PM9mr*|`xy#xP+huL*@3Q_hK*?R!cGxa!TYs1JrvXatvbMu^ zS=;)%tnDWS?Nv;_5|Fi=0%24(*wlbZU-_w@Z#f_gR# z)X(%mJ>PdwFGx^74+Hh0HmJt-eEgz@38#|_6~mvpyb}+NZ8)ti2mN;j2zvxyfqb(dxs-odxsGFNJHnu%zUIr5 zpz^~&6?~?k`b$s)!axl?!l1HzH8n_r8XN{{$Y%;_s01}E4Ak%=3@YZUsSy&?$S_c& zK2uOfNl-_Jfhs)0pd4RKjh3K}2?JH64JxB0Ym@mv$rG9*VJ9?4^iOEcXmLLPN}kXh z2|J-VqJKhjWO62BpTDN2$mW|G)_ld<&6m-8pPA!pzG)IvNf@Y7ZBQA#_nEmqP-PO- z^e|8}v_WOGz!3m7Q-UfF12yY21vOiOniB?U?hyvn&)0m%N>KB{Kppp)f|7fOBVl`o zBl>%XGxMoDUrouq!;!GP!x8@RfmD9Il`a{d^J@oL9GY_b-XsH%-;L@`#`OfpjL%}s?!FQ*?XTK)M^Q8O&F-P zpDCzy64d%IP#cagr~$s_+bBV83InzIGX=Fpf;u4#RQ(YKHPBa6a+h@^Y?pQ96YR3i zXno2LO760bgzd79=d(i7PYagY|- zX*3#U&Ral7O7xd0y#DkGbbaS{6 z>z3zmQRGrLhYKNxi+B!~MJ`w7aP_B_!!?mFiX43I@nv-ez1;(WOZOnq*GIl0Ocq1w zuzb;p4@PcQTVy0a)t>Vz2wRaGpl-hwxuq8_@Uh#~R(j*Q6`D-qx|LVvH`ONZ?1Ra> z)F$ukgUS0M_xEb@N#M5MR@?0Dwhv&*xl=vpb=wEPsUGC@@aQ3O_JHS@4G+9s=}_)i!%q3wH=!El+ttgKI>d;yFAM`H5lY zyapo28xi==Fr10QM@)Gz@}fG6i6kRC3@7rec$}Tc&w#?N)`>g^nc2dxf69xLV}oEG zh~z;c7VV`&6z!Mle0vw|W!WCSqP;AO_G;uc;ZttWCQXK-{YITd@1ngfvT!1AVD0gu zy&3r}6zwgbp-8VoW^cgXo4iPGN8S+`b{jGH&oFW)LWV;lL!(2p9*q2-I@_frDQh%0 z@^0i$+?R7Bzl;2tXPX;&53@y!k@tbZcFK)>092Gy9|D!dK@H7{ybFMS2Y>Iu-}~_Q z0sMW)0sckpp&zM%_4d%eVtu4N^sn6HKO+AW{<9gdAesb~`N62EHanf9WO);je~W5P zL@)!a=0xN_Kw)_kk^ce}5x(>^@v%&MEIyXvVT|Uc zGlqvS{Xjy-{i6e*VX+tR3|`S8>e-TS@B-zb>Y5*+#;jHIBcr1fct)!&2JjeL6(jMz z(IO3HcO*6%6g6^hbgW*DjEjyJ@GGG;us!l7-W#3xLzs&_5S@x7g0XX6$A1koyVr!2 zij*gw5i?pGou)8YN(N_u!O~A?aAvezVQ@AXJQfVj{)7hSMUPV${2Upq1cRUZga#Kz zVFJrt(w(ABx-VLE7u1=?blY@{Bmm-5tLS3UXF()(6-%N^ML+GD9)4eRtiEY?+D#^n zHl@2P({dN1U8!8Hr`(}buGLfCsZ>5*PkEP8d6k}Wr&4*fo^qE`d99vuw^Dh%o^p>; zd83~4Zl&^OJ>@-0M8G2DsR(MK1r$EsHc3gQn^V_dB0M5yPom^rSge- z$_JIot$NC*D3#mwluuPE@6=O1O{v_er+m6n`4HM5VAR6bQt`8=ia>3YiNE0xdGQ@%i{e72tQg-Ydf^^`ACDxa^X z{CTDFg?h?gP%3|3Px)e{^2K_}mnfAl)l@Sdm2c8hzE-LHH9h6)l*+g2DSt_+e4C!~ zmzB!5>nUHaRQ{Hp@>i6~cj_tMpj5tFPx-4#<$Lv%Z&WJZucv&IQu#qW<(rkt59=v^ zO{x5CJ>^@J%HPpbzE!FGJw4^GE0uqsr+k}I`EfnvZzz?Y)Kk7)sr;0l@;8;rKhjhF zmQwi{J>@%;%0JapzEi3EGd<FdVrShNklz*U9{;QtyV@l<}>nT63RQ`va@)Jtsf9WYd zsZ{=tp7IZs${*_~Kc!O6GW3+6Rw`S1%0E&nNA#3`tW?g@Q+`IN?C2@~M5&z6Q~s$^ zndvD%t5nX_Q~sG!IZsddIi+%ep7Qfb^%F%A@s^f2mY1(o=p_sXSIs`8B2Tcs=FUmC6(Kl;2P)Pu5d@ zQ>i>vPx&pS@-#i=Un!MK^^||DRGzM<{2Qh6Og-h_DwSvHDZi~$o};Jyj#BwpJ>_?m z%E##`|4ym=IX&g~l*$YAl;2k>FVs{1K&iY~Px(Wo@=`tJ-z$}u=_&s~sa&n6{70p7 zt)BA#DV2}cQ~r}ud6k~>pOwn1^_2gjR9>s6{8y#&dOhX8DU~H|Z(=N2$DBPx-$}M8$Esobum zY#K`CoqEcqQn^!4*-|QZ>nYnx<=uM95vB58J>{rU`6MmntdrIIn3iR}k11=v+GKSf zOde31tnGuzgKCq<_rc^TYLlz_VDeP8$<=)@d79ef+CG>(U2SrGA55O1Ho376CeKux z+}sC~XQ@q|&YdZD7x@$F3Ig(61WiB&_XA4LMLDjnajZiNML?{-b}vR`DW(5Z{E)C z?cFUDQ%(zla*>#FMi7*5iYZ?Uf^xB#^7SAnmxw861wpw~OgSeA%4K58c|lMv7gH_> zg7Pgf<)R=cSBNPW2SK?~Ot~}&%D2Uo%Y&eNM@+dQ2+DWGly3(?xk^m=ZV;5K#gwaq zpnOkE`F;?T?~5td20^(-Ou0S?%C%z3jX_YZ6H_JyLAhQ`xg`k74Pwe|K~QcKQ|<_Y za+8>HR}hp*V#+;1P;M4eeh>uZ7BS_%ASkzrDGvlexlK%YCooQ0@>@ejEhl zPBG=DK~U}zQyvR~a<`cB^B^eqh$+7ef^x5z@Enu$b~v5R^y6l$V2`{8&tRH3-U2 z#FW>9p!`%!`D+lAN5z!C1wnaCOnE&B%Fo1N{v)QW9|YyUV#N_2ue*%*)|Bu5HV%@ASf+j%8o%$hKeaW2SFJortBI7 zWw@BKdk~aXF=fvnD0MMq?;t2`V#>ZjP};?m{ez&45K|5af-+J}IVcFqC^6-bASly` zDW3>}GQF7c$si~lV#=q2po|t%4iADdgP3we5R@@u%29VuNs3#2zfgIjH8Xw(uJ4!E zdVd{aNoy9@cjBo&1u1p}A{Hk4~j-?p9nuj&1jk+5;Yz#2CeHf|hP<0it! zO#^G(RM@zAV2zsz8@CLsadTng)`2x{A#B_>u*NNgjoSy-xRtPR$G{r57B=o2SmQRr z#$5wz+*a7Qdti;*2^;qetZ{o`#GJwX8nqfJu!+cIRN!F(WYD`L6hYK2y2%s^^5LPs-n5%Ig z_z4^Qp_kl6IyC+Oe-Ps!Nnd0;DcqsRX6xupVMU65xRQhy{c!g>*an4?EF=g1QU?3I z4ETkVnH+h1E!zE*;c5-o0tb%_0fEIkVk5vBPHT3#bK+`$?1G zaP*7T$*yaIc0`Am5>kAx}i*H!MlkIZ4*}+pP;b#8?+alQ$fVHd~jhx2{OC zzMEuyZ;y42x4hn9KilWLdMR$5fSX&{ zom_uM-2HWT<(Kl#{PIbX^@}~$<4M-91RZa4v`R)e+qjO)ixSP(?v6XUIxgkz_&Y(D z+a0x&>2f>QWhqgYr`=t8<#`xRK7`&+AFnzxG&^%~=;fX8^sk=z(hB{#;K?znkL1w1E`$~WF!`kV&8;kpz`yp&$Jsh6npe6g5mt=sOB>q4Op{~Y&!gyF57<=AR)I&HWC6mP^%tB zG^=j84Zmn;{2gMozGT&-xb4r6YzFxImDxzRo>ix?U9yrKdNu;T>4w7<=vmL6+^lj2 zKC5&0Vpiu&v&!Y3Rjj{R<#x~NGGr2r)kt%!@``7bKg_~smh;i%IcaLq;{<^{?|3rh z1AE@&g2HYW6mhv=q$sdOlXF4wfLw6lj$Lr!Ubx_b$pt0cE-2~G1*P0BkgV9!Vi$;3 z>`(VX+dr9RRmMH5vi`JPF1cA%2z*wT@5QVxn`TwfJ*!IoW|ffKtf~Y)t1I_nR#!~3 zs_LFqHGi|Jp4_Zz20p8+_hMF8O|z=yo>gssvr2T&%InNqSCA2Z77W|`-sI104DxGi zy`H;2$vSQjxEHTEYNdRFzGm`bL$?rIPn z(Obg5cJQx5k@b4lB)!KbYvv+FlJs71lciV(ZL{7tNgoiS58SE`wU9k}*d{AwFGC2D z^ru~cfWnb8Ngt7zYm09D$N_^(L9*A<5+=(WkE0 zr*GF^?XX#YElGdF=)RjHC)fR~7=5;@<%&h@k`$hWi} zhtbaCM%&Z7<$O=e!mgH!;i|;g1uhk9F~4VD;ppus3l0!pu;?q0t7&nzqkOx#dq)|O z5K2SYo>G5zkN$3w{vIBe5Jtn;k!xrecW5{bcOJTKkG?KR-)QPPhrI92uwjkSx40$< zYADJk$a=C;E9+?+wQ@b_RCjN5^E)EA-IJq_qnNy>xb^yOMzX9}Lv9Lv9A)Ih2V?X@p79rVjbA?;qaX3WB@OtK82wWZ9M6X{A%aG*aUG)(+_)lX zq;p(H;ldIx`Sn+m^e?#4^=Ao265JDP#!(cm65xX2D;mWyr=#hN8S7bKp`S95CKokr zgJ&LPoYMo2Z{gqRB>hZ`{)6Y`a;|Ca4rilDPt&u}{7BPtqj6A&?>sNCK)ewOw^1Rp zfW};jg&XN$M}nW=K-8U`M$>54=_MM?b((=@@a^=9v(s=toeput`RmkuufQ?bQCEK8 zHTURZXbcON#t1tixCjh& z6q3*JCL9>L)4HaE#o3NuutWXz{$Hy-`t2l}CCL`PUjG|cug!Iifg9@1^=a_hbp9&J zG1Skk51ps=glVXwigXILh!|U>#}Ad9S_i2+V)@BD$xcs_W%!?K3Nb~JZ0Q`4ob#Ua zCy<+7^Mt16F1tuaEt%+(eqx0aP4Ag#Wwux|(M+gJTQtqYDKj(8%%=`pjB%| za@`TLWpQf8mSdZ(1cAFG#w|1lym2BOxh;N=bz+RIv}+_2H(9HJ*UBc@$|Yo>S=eAI z&@9|wveK+B8?dXV>@+)Ls7kYQ3^`~H z)3mD_EThCMIVtRgz zdAQ^9(!8GIjPZ^Z_mq$3V+{3ZK8_(j&Cib)HUR}_0d`yiT7WyQAT8)Q&gf~3xTiw2 z5MyXW3vmo_G|t0-XA?)PBL^p&v5wMG+35cnU5*uZS(p}PT{fYGxh{)P=*PHmhFuyg zsY=iip59zN!Tk&yX_XeHLP3$4U8 zO`r+xrbj(Ftd^;1Wm=gv?M5qeO{>rR;5*0(;l=c*R&d~=5Bh@)3mOs zX?0qiHSI;Kb4_c|8t$gwc$(HXHLXc&vZj4#O|EGzTFc$^dr#AbhI4Dv+N@PSTAOQ? zNE2PHjC@gt)?vpzM(c3L)unYk$GL+!MG#Cl9h)xvV7qR526)EX zm`&B21THzeNnY_Lab1Gq)nn5@Nv3&|4DyVmd7vcIy-5apNLmI;GQ*o>h=-)LkOZ!{ zynXVjH_783lD0w;fn#6uCV9d`(mqgv4LkPwO+i z!P(nZsmM0lI6{(a<6~?SJT#q6G!1A2Ml*>v;Ak4sh9;URE}E$xnyx0AMzj&5d6_oi zXd2VTCYl*8npZtE-C;8O*1P7^gf?L;Giei!r73M{VwufYVBNXb(;P=Z&%&_H0m_30 zWi#50QO={yILhX#;R$ZR&AELL1tK9k-me;f`xd+ZxAN*TASo zB($UL*l{apJMOslw7usze&h=rHKZfAy<JIY){>B^Z>62_5Ll@h3vZ;5Y-B_VrJciP?5D>T^x|F-eH zFLuPsJHN)rd(a+?dGXUb z+J}+up?x^gzO*k-%I@2k!@t-uN=j{mr*k}!TI?7hJyLfLq95(Y2Js>7#|@%C?e9B? z119QdGE>U!HHv8Rs`OC(pj$7C9l78z;~LO8yvOKcY6JEleF!7rr9;c79 z?vK*Px$d8!Pw?FfV!y=kSipnmCq0sL`VvP8&gpnU8IdrQ4rPP;j1J`n_auGNJUDQ= z?Mv2R7#+qMoS?(F22ata%njfUr0r{WxRz0sbe{Nb6n!h%dq=) z-COl+-eFW%!@1i`(PVivnIZ4)KXZ4*Kqs&UH|Yef!9+UIn5A`%X=Kr4seEWAZLEkUyXA*+TI6Qoe1saj#A6PU`BtYCBZ87%pljtPo%-eJl=gb%A3(T3WOCCEsE(Di6 z{N=&hCQ8VuwyOr^i}XdLw1?3bIm*d&vWe2>L-~#mCIDUtyG4=qnuMG&;>hncatSwV85d z1iTYrg@hSLv&a zF_yl{F}_A$b219H?&}@h(mXfiFiVa%qp*)R&w+1xPZ&^eNjMU(fX zl;#sL40N^hP;Ps+-jN*+Gjaq*$n*F%OS^OFTsFi)bS^iOv&RMvlG@Rwy zr!J%m*+`4hh1^IN(M7%^_3TqO%2{C#YQ6!o$xj;K_Mn^OlH|-{p{M|n=ou8BBQF87gm(V3FL}lm_E<{V|QX@n@yU5Ls z%JN})c9ENXdOqX4>@aQ7x3EXW#b*dVJ4Cn%$;EbypJdEPq&viAbQzm{Il7FS{c^h8 zcQHA4h;PxiSc3}mEv~@|y25am`2@HnnyipI%Vvrx9QvXB(7W0p0_7AbrOys=i^I=- zHt+4^7JtthnH0E1aBFrYUCF#yiLT_l_%?mpa67)2ZO1p^KY{z!#)id6g!rK!&%)m7 zC%N0JK(W&m z^J==$=<-7-?w@_B!DdM(f1fjBl;f4@;-gvaEJ5ZC+Fv#TsPm>&^4@06S{_L zvzD%9ZH(P@3!fd~Ho?7;b#xu$YDL#^T~#?%>n& zcEPQ&O>`6E>O?njTuC&^*)#h1K9l7rL1{bPL^L>b8eZw>wPwLtXW9JxONo z3yInLQ>weXH!GgQ9}^tD+mQ`c7`L}^A8vz9oe%pS5j$?iMs> zKQ$Fi_B$%d6D6c+7Dy<<-S0;7Bj3-Sx|WPQ-aYdD(vj;I*vR+Ny=>$Y>0WN+AJ7l{ zjQl`yBlq+CU^F=p*vJpaM}CEk{6qR78~F?LLvG~z=srIqKbYLeU1x2v&kqJR@`Lh` z|IS9fpYCTPpG^02BR@b7_!;@3CX4t;}u#2tE=9(EoI zCob+8^l0*#zlXP0u+ERrBaCr2J;E`5Oh5K?jzQ(~&S&i8BhEXxz4Lq)_cKRE?rZ@k zLF+lz=_m9P*6CdO3D@bT^ixl#?pS`#bJ*uW`+ph7QF@edETBg@j$`zgfa41vju8o; z(a%`>Mf5YS{pa*^qdo3^oae|d=ojqJ#q2dDR6ZC}hQ1^Ri zC+SIc+;V!7JMJs`6;J6rQJU`39QXHTyXo%3aYt48xy5ubblf3-1HpWadYoNci6d`c z$-?qA{hCee9r`slu~YOEo0zem;N^7O(NQ{3`zp5%j+=I{csmC_>CF24hJM5Pe2;#^ z_4zIRmUpJ}(C_GX?9eszJMPfa^t4xezNg=_R^ADJZ#|gebAo+3 zTI@^n`$;GKTy~q|bAmk>B<8fQbi49|k1O#L+{~3f&>z^mH_#urd7q_c`FT4J{gM92 z4&6k5JU!2j+f2`M$6cTocuIjQPX_GDlL5Q(WWcUG8JH_i`nYmL!bN(K zO?WH4$W8bXy<|)n^118k;wSnOJ9In!i97T%z03|ZE~obRTwQ$az|V>p`+rQVBNDFA zD~#&{dWGYvQ@$$90`v7xw%I{evC-CH;dt z`UbsW>iH|5p1<|#8TTNp`#2DgneIDBb<_L0r~Tcc8pV zjQV@}H%I*s{fDF0H=3^{PW!umh_`&4AKh^6vY_y6a9epk_QBoZIPK>{PWH1g_8&dF zq5jU@kZY6jFa4K|{yhDc8~sgslN-H#2!9Ir-cen83ee&6RQ8KrZz+H8_wy#qhyT(4 z*eHIY|8b+ZMQ=Gr!9HMTzv{y)e?G{3FZ6r%7MD2HvU^-H_Mbft8enqJZF-vx?H796 zJ+$=u5;U@pYJ?5X_3RkSin#Cg+;=+T=e`rV$~ppwG$7Jg7yrYWsgn>uLY$r8cG1fL zXB>W>a)^US{O;2LzYIa*2h*L#Gs%05`|Q&or^lRm5~gHqpz-tbpA$-CUZ(&A6yBbEri_xrM4Ax8y zGXRpoXowmO=a;~F_6<)G$-x(Pcoxffb}=hC(sggyl@{GX!_maBab?1qXbI@(FO z&2K=!_zM6}0oF%6)=YgA1f-y6{PZ24Or99*J3f3j>V6mi+A&+N#HLzylD-B3# zgU@}X1BxjFFO*@8YGKXPs4O65StHjOJfg18iR&lfiK`s6EXP>uW6i{h3MwxeN(FeK z0&CO|YovwK>*Itf-p=(NHSG3zb=;mRK`2LP1n94W+Hm zP_77vQWaWOWvuP7W@1GNR1*!QI=oPwHR^~pQzMLX4bxD%`V8f&a40pQWlhG~9cw05 z6hbZ0P-?>qwOON{STi+B1SHWkl)gSg`PpkIc+uwB&D8;hI*h$P)=cbm0jX*W zBDfEpJ;64oT-K@wt?Dtx$FXK&L|xW5CJB$wyOMMRfE%zTL$PLRf~suDHF0jW8Ufmf zwHSsqQ;WucG-fS)GQ}@`9=`WU>rH^C3G3r&teN^~3P@AWsGON1CStf}kNu=;Zq4Ax zW{hP7)=Vt8HkunO&JT}6a%cf)3)W&3)=VvMVYGC&fZbpyzsLK{-!~d~o(uWSbQy2# zz*_-zE7t93teLuP4M=Nux6s07eD*w=Tol-BSc~Vd zW@>>ex4pB4>v2SvcRRof9ay9BSTi-kmD`bTEYv8EHTW@_3Qkj_3$ z?ZbIz-|%x!&c4cgqlDLVZ(U=Yo_6J1*EItF!Oo!hMz|<%{N4EIJ!!= zH11J!gPyvvQB1~~X%v{Vy8AfA{Gp;7jv>-c%n#$;a14?j$=#p5;fUdONQPE>z)*Uy zVNS)GX_%NLdm7GiFREUE_F^qw#+s=`Z$NsxTX^3F_|xyA!fyu2?Gj@j;OWEqn1(e| zAAJGoYxH3b;h+AtM(;SkgTuXJ{L|k}Gx$cA#jdgRgZ}!lvCP1lX)KuO`}+hE-*xm{ zF8=BF(RSnJ%45Lv80+OVteJWl0LTDi#u$f)*G(Pxk)zLpQGYt%`_E-}Ry-g5`jh|e zD&wPq>B~UZvzTWh;A?z5Q~cM@JA$^$&5I^MxBron8yi?L=J?+`$Sh{t==5$JetdXJa62~YQrvu>AS z&D8A^fIPu<%dHwb`6eLbT)J5edk?3_Fgdr2G9M&Sko0)Gc|n*kf(f` zj^QJ8%inF?mALZYu7mr@69?Q?7~%Y8IUq5<{U>6U!)m&%eakUM9(LjP|3s5p{uaYQ zKF8ozX1dtI62Ss;3rb@D#eOr7AaYqW1CykMadd^BC$iQNz^Oe!m;Jcrdh zKKawv`c3mUJ$Y*y`n_XKLmT|@0P$GOZ|dIm^C3aq6r?fWqcO~XYq4hXAMP{9`ufil zBrT92jRT@_tdsRvGj)Pn)8~9TF|89#3ou9y7NqoikTgG^We^0(w3MLVI}ef;Xpl4# zO2OEb(d@Q%F|7Vy%9 zU`&PM)PUzRdCX)%z^u`W^y22Xuam^ zK+|c?8c3980?|y?$pNgHI(Z$C*L^xMFBEHlQNq(4tOq_yR>uIjpM9fbUQ5=yiIO$o zD1iw4eA|F&F}(p^dV_iJ5Y|i{oCU}%Uk|#@bBoMR4rsc+r?&p%U8no;y7@c@e)2aF z<2(mhng48PmX+yeLBI}s?j+2HnapOh{1|JdS$=R*6r zjQdlpnYiZxGSAIzoPXy7I-j*ThBZ?QygFatX~DZKGSF*V7&q?@^R>9~nGT*g%FknT z_IPlmaTj4BjBX(t`R7s?tl0^ynVR9{{ZeN$(N*~}czGFX`W4npP4Ntx&=>oqhe+N7Ow?M%=r?F=84&KFh*T*~N{fZ-yGvO*ATE#j!gEdnp zcr#$NZzm?fIsyrSYrg`zvZIfpeE_)^wEu~?cPr^k zCplwRumQ%ufz9m_)=YE5dk`C)bMw9`-vlphV$CjN&D0Dp?~{C7;=U^13@>kHO|N3j z)D$oAxA-^>nh=aYugZ6V2X->={Dw7?cknL8 zE+6lh&vKapNuaxdXgBNRI@U~`;LU(NzMYs9n<p;_KE^{DJ`VfddWS#tlHB%>eGhm-jC+3BcIlw3h zuF5k9b5)-CZlaVq;3$Cz{9VlQ=ehmhrTxr<|6tAJLA=v(z}JJ4tMV)XUzKO^<8||S z4*cYABJT5CjQKo=KZzCbU+7|zp$I&_6%%oLYosNFtRxnAfjxkg6lra@j{K6Q?C2o1>rWtot~ka|!q40%6f9h5gLR*PM?Sf*Ltv@C`4lI3s9P2CbYJoLrTsZd@C zy%~C2w}edzn-{iFx9IuwvU&w5*Xn!qeNcX-|D<2lEw*g7qP7xHcDD_+Jq6_o+h*G~ zC_lA*Z#%17><)V#dwwV@+8fv#LpjR+l6@MKKih9bXu2h$R7A~)L?}B&42pOh%J~ti zBi2B9AmU`iDcuqo9+@Q)ej7A0KC)J19VkaePK|s8%8ilxBM(9OOB9K+=$5D=QI(^r zLD?s2c+^NJ7e}p&+6d)|sEbjTp}dtYeYy;~#WBP&&M_X!O^ySOkD$C69Tn}+Ezz~2 zTSd2p@{Q;f(eFU{L-cRaf9RGBtupk^&=1OIGrXK(I+V*YY|OA(x5UK8l!_?>Wxbg8 zF`c0NIOe;UGrA>Xt&FWQ0#C*_Gp^0J0m}bn3dt0vTQb$n)Gkv;D34_NHq-aICG&vH z&t@JA<^0U6GsAo{f0+5p%qMkAmRea_Wr6ltzR&V&mfv+tR!7!6S;2oIlD$Os>e*{S`D6C$+5glnIWp!bkRwjF z1#-UAgw^me_K!bz>Vq`C{yx*!fU? z8~bzYuev37kK9k@hW5EH<^DT2=p@fec^2e(Q@7+zmp3+VUMRQZ{V4Cpx+P!ld{5^a zp<4=A3uG+-`~|}bW-dsfEMKr*!G^k}(C9+16q*6$l|nZQfxhDE#I=p<0Od<@3*vw; zZgO`x1qcvj)LP_8Y!x9~pQQe;MvB}HJ~Mbj6}T{It* z-HJX@bQqLh7rk8cXWde4X0hePR_d1GO^SCd-b1&Pu$IVL0>)D+rd0k?g`lifs#&R) zP|hf|q!jSPhs9@(hjGR?i0>HR1F!e ztT43#=)S_?3g1)!zKR7ZmakX|${#CUuLyjV9;-B}(iq*65SoxF0d$ejCt*|q{9UX;IDyyr24yzoia=ywX-BQ(7 zHCNRXWPE-(OU} zRQ-x>siD`%StB=;y=#oDF&fH4HNL9>>!W7wn&oO%gz~wXZ`7Ov<))g4Yks0zYDL#7 zSgSCUPuH4S3+7pCf2~uszJv0g+UaY*J z662ukoA_)Ztf$2JiE9(V?}`7b6JE!rTj~_7Q@KtxC@0pLTW0~3C+b|Ob4|C@wbjj4 z7v@*Da^2>2TS56|-HmlOLwUaLKXw1pE%mb0D^{;0l+)@htG5EmZ|nW99>lwTy88L* z7lg8Q{r2@cK{>Ym%=)u*OM|Eec^edfa%O|K8?4eT4HFtRYY2X7IH=+C4JSf*tl{~F z;MYc-8x3s)d9u+5jZQX#{MPvG#ycDD(Jf8dHyPaI2`G;?IoIT(ZfP3cG<(xrP}XeP zwkgD?S=nX{nnC_-_IR_2&0f?k&0lH0wE0_5{?@|U0`hpv(k<(?g!R>OcFWZ*A&#xS zYV~s~ShuY=w*II!tjpF{+K@JoC)*TkQ@IWJqiwdfCEJ#UvQ66oZ3pX?cEj3DZU^ye z_f@-}+d(_{&iN7@;-MVdVP*%IU&lQik9Yh^w{%+3X?v$#x}|eS=PaEeFLy56xj|jC=cS-fYho^^CfuOYoA^m;+J^lsR@TkoDwKHqy*@3~O! z=>1vmFLg_wwSD&YIRxdEzN9bAtDmi3u6_{Dena|A=m+ikuj#+9|3TgISjNW+KUPe) z3}`!G-~d=>>^G)E7U!N;x_uIHB*V?~2Xd^t50^UzkqiO!!1og9@dDq! zK{5u|8QrIH#ly?@4nw{d-$>WENlvu zNRGQ4f-wxIE2@%QLGXBUxzf1;`?rA(K zMr543q}HV8Logp>PPhwsSmpz&b3YH&fb@PyqQpn)VVV;kt;VG9LliAOVh`KA_^6F0 z{U5TZ@sWEN=f+2G78&pmM$d?#^IRQA20f&6H0Fut?}vGgA;vXtEE)0;hmsHH!#+=T zo78p5Hk>^1kVln|?4vMOKDw`yCm(_68WA>5IZr(zb2jFUr=Uk^&hArE4Kn-@3bhe# zr_6_t5s%p1&GRoxMm>V_H++Cg{!yJjJHa_W=%-B}qaRTf7)mfsdSf49KN!BiRq?3% z!F_V}iPmVj^yx=SFY3evKQR#;1##m37 zW|dEz+CiV#<@#Y?EubZm7nFqD65?f~{Nj-j`h|aju_2kPRAW*NuN>tYvvPdZGgYa_ zM?JiPlz)5`yM}kcqKf_KH$|bn#_8H)xay_QTGF{ zim_zQBd!Ww8Oj%U%h2RWg-4MEN+RxSa6=}_C!XtV z{sGb@WRX&fTP^&lNBPC081#!f!7L+-m1Ink;bo(IW0np2hJT=M9$Bi?WkNy@{?R+=qI~eXU+%5 zs*<;r)ci`#kel-v-@fEs<*#J@W%vxA<5d3gzeLej_%9rv@g(`I)}tse*N10Ykkv|V z0m+S*obp*pFSxPj%NO>y`TMSbc^9oh!Hi*{FPYS3WfSh$~t7@Xl8<`VarHH(g!d<6WC1DK*}; z8VyA{S9V^qMfox)UmE_z6|Q`F_bZ%R=~;|#>@WN<%c|NxUbM9WOoQJ&E(A(&Ob9Vj+i={3IUqCqF}i#+}#0%8PgDMZ=SL&sBL* z;zYlT+0ZGxuad>;{BBp$fPAbJDRHLZujESO&Xe+_#E}8161~iR>JF9ZyzM!Ne5%AL z@o93R8tRE_QYm&&s#=vnl%kqDG$C62x0L}2LG{kC6Taze>g;$6d8cT*bDRo<02 z_pYUj(O^#lx-JZ2$yZ9j5+~n{a``rfij{{Y4h~Ai=xMmhh3i}Qk2oJAr<9l_zUGB_ zw{=6%%F7Zb2Q6rf44<9{l5drwCC7T0?pSh0DO}?8U=%HCYp7g#T;lK)RXIk$Yv26~Ijh7j@x4f}!D5Es zmDeRsPjSIx#JJtdIVE?A=Yy5Dti2(5<#~zY?}_9w8s=Ti1*LpR0A$Kd3EWV>^1j6R z_e}j5J+Ix)C2~nE0!bWFLhSxHa3L7)7++RVctBCW2pK6!ML`mTdzzArH3BDR_s9Kf zldEb)NP=Pb>t2_9e!8Zj@qnYj=P4BpNign9o-)>*IbZ#%R){1hhQIDt>B(CK$Zskt zsU#|V{!&qq1m(WwFJnEjnEpD)NwTawR>q-(bUf&P0Zmca8DM_GG#o9uJgc@fo`1Sz!?T#_z zmRekrm_5h^<=wZjz*Mv(!Adm?3?moLEi(7#mtNE08+qU{v*5o5{6TTZTpv9Cpk^fN z*SXvxRK%pAm3i(#;a=yp_F9NqY?9zTs1W(<*H~~WYLcL(s`Hx>N#kP8^Ho#_H0MH8 zCpq6Z8eU6nrLp!@r;(pb|f%90?b`8AE|lw4NjP)l19^|ZXC`LP?zTSZzD z=!ar?W5oSkc6HKnsg*7f0KZz&dfiyl7K%{s~n>r=342v-r-|)@NQ$6e zNCPVRlHfnIX@Du%vm1bCqimIoYk@{uoXQ3gK|CxgUp5aTBPaz(1n_WY1fRQrMN}q` z2tl@j9wyw#21*4I5j^zS0M#tITUbox1&JgcruFY{E=F!pN{|TQk;o0G5XoJ|5-LSV zl;Lk#J#4QTX+o(%B8EpMP57n?_ua=*Dpg3-@vxqmVz0IhxNk2`ZCFgkt#XQ7-v&P8FpTr4+x}(>V7i zrAUP0*L#mro-v<;s;SH(5zM2ciR9+WpNncJ#VExDlueCul2VLBFadcnxwZK)y>31? z)l!*8BAkaQ<|#E7{v4I4l%te$N7>alS1IL4gmXvUOsO@U7I^q`Rtv4J$~+PQrG;2N zs4*JZN2y059+iFIIcu3ZLs`xlYQ#5vhdaXJ=%nDBQI}f~4g6%DVzuW0jgDsxlm> zO8+U!NKZ;h5+SMd6hL}ntIRt^xj!7&RAniNxKwuXpPhLB7@10`Ng^hdsRGSZaGY++ zR;F(ctE4qo2}`0eenF~w^2rO6mh&@x1+nV9AO6^?kZCISvQKd17%2Im})57?SRHjrW5t&M5cW_fxrg-**G2COtUur3#bygWo zA~u=-6rTK@R^CTOR#Qro2u)?R6v%3*xKMV#3^JQDxsBJls^lio9KS$S{mv4ax4(=8 zr_?49n@Vsgl;BW#{Pu06)?H;diRipnsrox*vYb+!L~tt0rC^rx&UEv%o+{Hxgr_oF zaG6cyKitz9j|%lx%2Ud_ui4$WqEO0{2=Bf|LzEvLR?PigS39k*N_!IZJ*>e`4f8Tm zpHiPhd@A*&@MQ+C`Y^nMj31TS0Xl^D$Hr;>RTh*8k@uUb-5;h)^ZOdz=tak?t)bBt_?Q248D~ zR9=)w(t8c7zwb?+G;*U-qC|))H{OTb=**9<9piC!Aq^MN%d{aXKT2e&^5MP7ha$fk zIZ~-nB1V-X?^BKx=g9%u6Dm(iq$yg@3cGi?6LY2W`G+FflS-9Jm8s_3V4TI3DkY*! zHIaIh^0V`!C$4u5OK4B2lqpf?qa=#dG*=^SDrHK9snX_sy!hc)2D_oo9=LGcPQRcH zSJ_h{Qr>T>e(x@SM7}jLs8XjyoGODppbUy?b-yj?-h+-%SyUoa(dt&%{mZ6CCRGZR z2vlX#2bf7Q6NK~60kdtX7Ojm^300z3l|1iX@|5}7NUBPu5|OH;`hb%vD%X3P+Fl#2 zvZ_R|vX!pz`Tebd_o)qE$&Zl_gzNwD&gms5Vh$U5S8`%K+;22a}aC^BSLIc|oaHsW;7?X^g#t zQm;h3X)dCV(z(FvlQEN33YMt&Q4&R3oU4(Bm4YP#R%tjDUc&J!ja|-hpR~ECO;y=g zB4*xis{UXu-IDXWk&%^(B_dWCIhAK*RJiv|wi4RQDl1C_om@sxucwYoZDeMpWQmYf zW=;c{8MBGtz2|6cno7_TU8@9~IudXoaWIm!QnN(NDoLl2B#mnK-bT0AW~eMJ5q2Qi zK^>ENGP#kdm7*nrR+%~tWopbUf^BtK?KPFKCHhv$IQ1msKx1JfZKZ07s8!NVV@Vs8 z@4L-@U1e>Fzyr+`>bTUE-Hptxlr0gq%G_x%b7PhfY`e>8vs40?=v*b{)Rma;BpyZ* zSL&9CTP5){n#6GxcyGhktKa68$z19DKIoj>CIz)QY9k>L;hmhg)UkKB>5#Zy2&0dU z4T4gw&_w_$CElG9@5FC1--~eMwXk1Rh2NfrA69Lq%~Kgyy(<)l$zN?Y25eA zUC>sjEG-eXzpS8MOPQ^Q#PvcrIiDMuS}9uSJ^+*Rpn5%cRm*%Y!jtp2_anq5w6|5Z z7CBOB`@XDgiR*=Ma@xk%jf|~SEp(w$b(&PQ;1hh&+Pf-oOEexxqEN>Kw=t2pUI+*3 zYa@9pWeeR1V4$8<$KAcUWxf~Tf%@5d+udGUt+Kbsp-SWTWsOT*FN6ctI38zYaHVdc zE0wy_w7Lb`@G{!_Dv?XHekX}T9eZ~h7K!VH@SXbDNajl6LU#gqryfR;b&`C66DMUGWkzb|WD;(8%`r&`D3jf}2TE_A6<`9q;{!8X0Dwq7N6iRSMnk*GFz zwvmyzUI^cht@iyW@jzVK%!FL-VtTHB>g1d_Fol8Hxgi8n+N*9+m4_MveyP%A*_ zZU9r--wF(}I zRUo)bD64&-P7IPYaW4{);xuoRB(4|2_sVz1$w93Iq1yqxSDshAp4A}py$HWoe)GL- z*r(18q5!BhabI$R#Pve>Uabk_HO>%fH3(g=R>LE;8U&XS<+KCpL?Kxl_cAdlZs!I{ z;(8%`uYG2mEYyk+x*x!M9RbB3CUd6YY zoQcq88dQLJ-?+#@jGF+bv`ip36XQ4Tty~EegWkLGASw@u|?$}FGMwf zvNL%x3dS5Yn@o<{4do|fO1g@~maZy!Io;z>jwi3A+X&@BGA-TT#FjpiOiy18$`)is z`Uz0ZBCn=D1m!p6HAfV&IdYSkj+RjNA#XTftd7-Wmg5YRzmwU~g@`S>9GMe6naqv; zhRn~AyQC^=VUIyqnUZ*rk}FLJS_gIub$ll)Y>KDk``3vwl~E4iBZ6ZyH$Q^ZzhB)L{+ zGn9wPFLjR+Tix%-Z}nav*Xw;rZZs@S{%qWh{N1=8`L{_Ha#O>4DSBdv~TA*~3nIuy&QT&~|;b@b+i5 zunv)$wc}(hyyFH<@6oQ$S*LA0szS|WoUH8nIqsOaS z`X1Z0=w9VDN3R}QhF-U|=-x%NbiHe7F}l5#3Rra5Lcp>C zmND!_z_J4tqgMbd2Vj}?Jb>i{ER((uuv~y;)!zp!7O*V(RlsrsmQ6naSRTNrtps3s z0n1^_3RphCvfG{lEI(kmY+V5>09a1jHoyu3mfN-*utI>v+Rg$N2UuR)$AA?EERQ`u zU_}7SZ%+qUQNZ%q8v|Ahu!8pTfE5R;=Fj{vMBV1*(yz)AsD#C`>^c)$ur zBm!0%uwoG<04oDn(TK+ZD+^eOhz@|21FU$&8o8F31*ihz}l*aui8 zz~Upb0hRz**~n19Dg#y~vJPNX04opU$P-x=uyT>F09FmKijmI%RvoYkk%s`Q0a!xh zdcbM|Rw>E?SS`S+ME(p|ZNMr=RRb&$uxe3pfYkx4YSc);>H=0Hsuy7O0IMFg5wQAz z)rwjKSOdUnMqLK1Az+D7Ujo($u-fS|0M;0=x=}X)YXVpu$9TY+0#@HK2(V^=)pL9V zSaZM{IyL~-0zgSNu)%=!$@D#7 zLjdca=_9}%2drP_v4A}R*nrIa0UHX~W0_G`PXab5GwNy>U;{Is1neomhGgCg*wcUw z&Vu6`4%ib}aD2}I_IQ@x0UH6>lUcq4Y$RYqv*P*~1=v$raeX`s*s!dF0UHh2@T~0s z8w1$WSjFT^MH-awj8kWfQ`;J4X_D-J)7+~U=slw zn{78>lK>l&y%u0E0QOw=Vt~B}*tqO}0yY`2@!5X>Yzkn{=ZFJrDqs_HWB}|Xz$WB; z8nBlEdm(2xz+M4tQche8(*T>C6W79Yz+TLi9k3aIP0bYs*sFj|$u$J9*8qDtS9`!_ z0`^j_y@0(A*tA@$0DA+lS7I9gHVd#Bv1I_84cPS9`GCyHb3vjfGr1XQQjoL-U4i4z7c?}0Bmu-o`9_c?9Bo=-?srv1MGNd9P??w zzABAl{vNQCrLO~a2C!45PXqP?U|*N%57=42zAe)dupa^Yrp!#h&H;A1%oxDV1NL2+ z?SNeX>`a-r0J{j-_hmN#b_uYvWfubW6JS4-Jq_4pz|NID1lSe8ek>Ob*j2zTl>HU3 zp8-2x4%hxQz%G@;wf_rX7t7;X_!Y3r<#8?i53rxg9{r(QvmGY>U>wsM= zk9zq7u%FAH2kZu5zm`7=*q?y?QXvMgzX1EK{C|M`4cPxGbOY=kz^+$l0NB5P{ayjj zwKoB~Q321j{{i+#1)Rq%!2YU$^SBMzpA{<+J&FMKPsMyBPm~7O-xXmVQ6YfctO)af zvvDc%Z>2GSg#vb~Qa`}L0Q)Z?D~XH>*QrJlLP&uqD`2-1#sH=R7Lw3|6pgZxQkqt| zIbe3cLMxXAECMh~<+*@G0v29*3}8`!g;o9(uylawmDdB79x!W_{D3(Cvscjpiw4YA zr2}9Y0E?_r6|fk}o|6JSwQE&-MqFh`Y-0m}kd`l@*V%L-VAs$qap zz@n>e1uPq28LKV?EIVK^)nIoSl>@NMRsRDlCt#VXwFE2|U|Fk`2P_t_EY)5DEH_}; zsyz-^9>8eze1PQzEJt-KVEF*cULB9i4_L11cw7O%a#p_rSV6#YS3e3^A;4m5&2@m40jy}P!hn?ptVFFSz{&wuyw)p#l?SX;t)YNb z0IX!K?*OX^Sm|1O0jmU9eC-T?B>+~o)(yZa16HPXf555$R=##)z^VdPuJ%H}ssUE9 z_Va*M2dqNv-vO%uSVHZSfYk)7QeqrnwE(M<7ztQyz$zz>1uPM;YKc7os{>fo#0`Me z1*}HmY{2RPR=ti5u=;@2O8gnH27uM9Qw^|&fF;(+3s@t-YS&o+SYyEI)_D%FCVs)^nV7&nA)Bx_0 zMD+%&YXci#eE{pyU=?6}0qfpiI$-?(>(&r8-XE}@4N>Ed0oJ48M8F0B*1KVUzy<== zt0AtfL4fsbh-+&wV0{`r1=tY4`ZsD1*yDipYjg^*CjcAJXcu5Z0eh_R9>AUiY*6Fn zfDHp|V3Q{RdkU~2OE1IU?Tu~vS|olBLN%Q6!XC- zz@BP~`QTZ=hBa#p*l56pH-oF2s4;*&-Rwoc#sW5?*+9U?0rpJuw*Y$%uu;vY0QNj! zBU{)38xPp%=GOq50NArF8v-^Fu(2&m05%D*F)cCYya3p9Eivc32-vt*zXCQHu<@ zYOBUq zoq%oX{Uu<#0Nc`g3t+ne+uY|6V0!@D)@L{^*3JS0~0<4JuYa_tA2(Uf^Y#@(CorHUDv9@PzlWo&&vuq3PA$HxK z&Ysbp&EDMJ-rn853w(Cee$xJTL`Z}^B5Op!h&mBXBHBcBiRcqCFzP%ZkzZ>h0`2)=jG=G8#eG>!v7ykJ- znt#yzi{>Vp|Ipk*a~q6C&}e8v&{)ufq6q^-dZDRj%|=LTG|kY|Mbi~cO*DztDkOAn z=sXfSCUh(bof`TQ30)Vul7wywO(LNyu=XAp(hUv{Js*03kdD}_tTmR9T3CxmQwB`~ zG;Pr|M$-^YOEgW;G(yt~O;a$TGech|qz3+38~+><`Zysaty$0vCt-PuW0^<<~KCIqq&ae4>UK>{E6l-G=HP{2hG1|Zld`Q%`G&y!B`0z4NV9d z3z|?gVQ9k9SkdTcY-sFgBG5#li9(YOO?osAG|^}>posxPD&ZPVt&jz(0j7m(R-*L;6S5A?Ml_qzY(ujX%^ox# zqB(%(BQzg_(fVQSD4NgFoJ4a9&39z*7;PxlqR=?d#GuKHhN8)VCKgRzGzHMafzgIztvDLEZ$>O-(3D402@UK| zh@~c)L^So#GzO!M#2UO)Of0R@v_sPoO&2uiFiRga{m~3WGX#t_7He#zPhssDG^5ar zK{FoBBs8!qA(ofW%mAZJz}ieSv(U^%vjEK!G|SPfMDs41HE1wU+6!32Xjw2?7L1k! zqh-NpSq`B&g60^S<7mDDqfNouH)u|y!5CREMiz{b1!H8v@K`WB77ULC!=ojjc^Uu2 zKv^(Qp%|!83{X@aIXnpSAqg3)GUtpl3QXu6@nkcDE%LNR2a7%~lAti6e5 zDVn#?po_Kl&{RjW9!(OO?PzwP*^6c$nuBN#qxlrg=V)+z+6gqL(40nd7R^O8m(iei zwcpU7cQxkS23SMKh7dGiXzXavogo>~P&7Hvp#MV9e_B(lp%X)jph2OBpwL55=pp6N zR6A-t83wn+%Y+rv!m5T<)52;(E%dL@ze!kl7_|63bR|460VZ@O?o~d-+6kNLUQ)hr$Yl#c5$hk(5FU(h0lljHV0r`%LHv5(T>)Vu8o3 F{tu=F)NTL( literal 327747 zcmcd!2Yg+%)z^LZJ-_>&WhZv_0vw!>?buG@3?Ox!<-|@%oIP+}>}SWsBk{<95LQ_& z1AGZ7p5t*7A~;_U?3Nd#bghCf%HB z*jwAt*wdPhGuvXrG9oL}J9}C>)0JI&+Z$G zT2mG~tVR$eo$035bVGMZ9Y)u+G`FX^dpgr|EEe0kw>#Zs4UFViiDR}|ktv(3y;Unx zhgq>mYW~jD;Z{{-K&-NVRW!maE4N_Y+{A#`bgQzoG8Ty)V@0YeAv&kJs3?{gkT^L) z@ssU{J+Fx32SR+F?TJ6qjUOfBSI0npjEGN-1^LO|_@mtTW4!U>-T2x}yaRS7Qv9)C zXS0kKcqWVZBE-|?jW2QIPxi)_y775Y5B_pDev~(Ux*I>)8(-nZALEUm<;K@~%>ev~&p?Z!{`#y7k1$9Usg-1u5={B}2fvp2rYjc@bDcewEl{la3l~O-sfmHy%|v@2DNsYZ}+qV*0#-RQslQq;711RWc${IA$rGCStqn2-;o?g19pkPHT5#5|Kst|Avs!J9XwQQQ% zRxm!%a%3uo{d>XAg;w7BWs~-_t{=8#BeZAx#$4NOu*xboRSqAJml$6>B9ap?+gH&x zB9?1+C5FwT{=d+QR&;OQKVnGp(AirSm2E;Chi7n1jit~Zwk%q5;+pn#Wo>ImuP7*} zu1vSYY|wyGd#jbS6MK)el5Ndv_RZ*b{LHSUXn$Qr z#{QU${hC;du)n@=-@?hm=4_q2WYXxOqJdaHd&fZitQ<42vS`hijuyyw#nMc^10rL{ zZ_{%N`J$5bQyc4-4BS&Q3d&WUl;xT{pfX34Yv{5~)7qBqpIFhheri*C$-bjHhRz0@ zJsF(q$5z9u#-%_1ZJhW|H z1(tW9EN{lnjFJ&Ew*~C9gPm%Rogu=`hMBt-lug<_X+v4#+`$9Kb&Q<7Wh0hznOn|5 z!y4CijG7MZInn87=R`VVwMD~morrD6(z?{ZQ8j8+h=q^A~tH!ij{HO9#B_QlsYofZ%lVZ-ljR}rDKZn@EX^t2%{P?xRPEo6&&~0!U(<7w9z1egzmao9yY5`)w!@Lae`hx}uW4Ka z&(99#fxe;3w*OCyZCa^eR znA)@`f8UzgQL}fX_b+X3ABN9=?NC`S(|o1`pge z1^OSMzku{BQ_0AXg4Q8znfb=1Tsu~0%_~ZcwkM4#Dq67+`i;p&Yp1NA+SZ&8zr(?t%?AMA`ERwj2#zqE+=V?}J3qB9_yiu9*4u)wpj$f%M#bSJj zos=2(CJ!j8n%!76d*7P&k>ySHEZ6_}sM$?(XYie)htEvQ=Wk~k#)bT9tKZVu#k=Xb zv&WTenA&9@6VO`{9Z+PKw^vdBl(xr<^6Xp-{c2t{jn91ZjGnnO_6=UPNscEOeq;fS zr$ezE1NKZBF*7nkl}qqN_A%5C(>Nx|JH(1%f9UbYbrnVS7$Miyyzs<@ldT-Ax3L|Y zhi$2jBXHN z$mYnM%e=cha}iu_9T$Ca_f%32s_gK}dAbuVfoJG(sj_b2;qKUJM$ZJm5rMcdrL zN*?P!DeMiK-n3}Sq|xxcRS<6(m>6Fbv7_w+s2)UrTh_8Pf76i4D#SZ7K4n8$Yh`RN zJvT7FEEzt#qpA$X1uH@Q&B zu>&E*{v;RXLFL`e8Gk8^4ycSzJ0ZQlYxlB|<&BHLFC~829|HdH^!S*{c+*bkU)wjA zZQZ_X68H@~CqBHhi|oy%Lts9YUXCxi=oH+%pbR?iszyJ!w;~ay<GrCW>F)sC9Eb^ZPUL#+j(pIno7_?)KnY`zHU59EULO^}O~?P}gXVBO?la{dK! zupn8MS#4afXGd#GLrZs6N865;*7Win-7OvMUB!O3sx{Ts6=!*{${4N}XZty)q_L?f4FaQKO}BHGU@TVXCU+O#fAhHpNorA?H%pKrExaVVuRXKZ7uE1RUNPfy{Egl zE!EK3QCw=VsWq8OSF6(`S+dNl0Bx1-Y)UoYT5_bN1DZwY&FjGmg!ue)dt-g7v9Ys$ zM`yae4I-4xYS8Z`(FyPy+fwyAws+SzT5O<_?&)r6Em@OlZD|CZ@tWwPYg*bHT6-GP zVyzwZyXPDWvK*Jjk!`DQY4@<5g2l!8`gCV!2LMDFiD;EC)>f(>5Y7|z8A$YFhKSynAyTv_q9JV1o(ISd zQVyIQ`l+vqAfk765a}x$@FM%x#`?xocdDtq9smtQ=Wt^hIyyTsIv@zDgV62U(rxv- zQMtZrTT4@S8tRsJb$7s{BO-zA=V8gC`+H*KLl$Up%x`N?SAAzXMbHpI-u%i{mG!j? zYU^vNmo2~t6I!}8RkEsQM{9Z-xXn6W#L+cw2e^Fe3Gjo`oa|!onRHgAn(NngbV7No zY5>={OLkao;^!~n$f|pkN$AL`|J2FJZW84ByPaf4a9~aE4izNxWQUs(EAWVko)~0u z=Ph1UUpasN%KF8C)#YlI10s>Oa%JWE`uPivTeTRf5n~oD2I0!O#r4pc@=Qcs^#-VB z2U#L>=dGIOHJstdFmhhQc_=+^Rpp}kh0AN^19ZicwSmZEQdxcVviS?v2>?<|M3f5r zLQV3Rk;|6_(#z`o>E(g+a*^&}wuB&m-sZ3RaI^Myvk)u>*rOks)ON-A_U!!==G}>)UU0c zk53oHh>hWMDy6RYoLNC{fdZiwSO_SA%TOGeUWijb*C|2!J3PD;F%PUcM{?sjhPV zN=1uDnG6XW5`5nL+RFNQs~2WEgCy~F_0{me@(hC>k9i2$x_Wq|VU$`}S+@!v+*J!! zu3UZGs``}+=2x#=Pz6s!UUgMv)#3&9Wmrjot-s_wb(Zgq!cNK;flqOPS3=gD*HB&k z+DgDQAS1S*($nQBL5!su%h(h3Dto?xQdz`N^?I}RHbGK~LbJIA%rse{O!POJj3m2Q zMlNG&metp7aH~bMA^?S&>L(>I3W|sADr1%}tAWyH%2ijjY<_(W)W0i09a;uS-Kxq} z&{I*-Gg{aa%aUiR4WrzGXBrM;u_7{!0#J^ttXe7}{JsxG%0yrZA^QyLT1`--cs`&w zAdsmy;;4k8@Q_A&(#wUk$IHnS)deXlj~AlSN4o%U?KpN>o*xj`b~xvev^+J`slKGXc6B4eG#gc$LKnk z5Ya#(xK*B>w_w@wdh&M+u>%DZ$5mI=msPE=ssSbsnR%6f7N>SFFB815CX%2lu3x)+ z<$UNhgkI*+5OUN#2)R|uS5?+v#|l zs)<$AwF_3(*DP2B_7}h~REQh7XnmrX0;uE3<2bg678eqFvsduWEI8xx&UTj-N75;&w3ty^c0M6l7o|T`pxYe&;j@2KwxutgOXx(eE zVkq>%N(ah?)__9BtbrDbHnp@ja%->^M{7eYHX@*o?@KFt+E+nM700b%;PJJ~=dZ3= zPz?L~f?0WGA(s)>$b>cA8U@~kFNop|z0t8?ktlyhsx#G=hL?4$hAz=q8$C@*jm)hg zYc#?-61sZ#&5YLNtTE6;&FOAxb&Gw@+eEVNdzE~V?}Gh< zm0|^?C4;_^zv|cO5&sg;=>P|KX!V7ng`XPZj>Ky+?uI-hM|9UJ)q68z=RhuBug+r z_3iH>4sSQ+bZ5SQ$h2OTc)2a~o?-IWS z5Rn#u>TLnW62Aq&023uI1`v@Jfa+}lMjl!<0}MM_8tMVUD!&1ckOqM2Z2;QDX8;hu z%+QMfB%}dt`^|#q&%eF~CXV-;02yflr~&8}^kinbaTv=7G^QJ1gK$s%E?nZo1w$-L z1EBM|F9$1F6vl7t6&}s8-sj>{z(M<;@=iG8TZ; zSO7QcpD9UZ(bBOx17<)fV+Kf#8Spn>zQAV`fYc~}dx=$8v25&ECkFH(IinAxMjxC@ ztlV~{yKqGmn(&l>36RK`08(QDUC~=tz-JVI)F`0qc@==qC;+KZ0O#>30H0CN`c)bD zh*tr5seokf9Lm5gL^U*&!D>0Ir#aSz0TZqdp|HjT_=PV|*JaAIE>i{`085;y&Tcgb zUJ)?ix(fe{Y81c;d>~!_DAW2!88o?1!Sx1A(&PY5-VYyy?$)0Aw$4;T zeN&TT-5Rjsx=5MUMalv$f_$a{wJuTye!%g!h0b&{{A!0?$TtFcx=w?_y^)tsb=X|L zPPywhNNRMz75cYy)pxZtrql3aRzr6eK0@~g%(%W&uJxVrfbSqLi;JWtUvLL+vy{7@ zf}}nTWT6at=7?s^K68ifjnEesUH^^0u7_1rjitf5b zxz;txXE_WO(0n?sFO+M2VH)@XtV4Kprn$a=Wbg7!D|Hym0(?4d!%x#T{IoKM!Fq^K z$8Gy*+P0qt4V-}aczZpp-KQPv-GIL93Mi?;8E}PZt}7s^QGoWQ&apJpIsPt?r|TTk zw9YXt;2g+H2S-wqCp5pWR$R}RruB?z(DptB*DWwflLIuoPr>zxXJmA0>y!ZN$xgIuM>tWNujmTj-+S*#W>%m0-fC<;< zP*{Tp+(^x9Kz~p`-*vd@T8En+a5&^MwW)Qu>EKo3r%CrWZpaqiQhg)eNm)%>W1SDY(9aNtztM3498! zf6UPO#|&t4pMvWRn54-8+SsSyHvbH5^Unx0Kk}Jc(l-ALXii@aZcAg522!A`Ajjj&QK9>2IMmeT4$($7SD`donmqy*%Scjx(5nt3L0>a z3fDc5)F=epqr!C$BsB^F_o#5)1IgYBGXw5{ysQQ!H45MZ`YyiBi3HwvXS%L~q{bNd zgX*6_ztdl#GhNR?QlpQa<9P?1>ADG$8ijzH%yiuZNsR*dLb9o~r)wKbT6%Ukk&^>C zx^6R5>ozmN6ZGRNl=t+2G1q}mO@k)jKr>wjLQS+0{HsZoHY_bIquF-z+evjSd$dvW*a{W=h#bb!|BKqLEgAVTQ?t}mIhq{Bb1KbB}#)Xfe}ha z?-Hd!m%s?6qj!nYpi5wc($Tv_Y0xDwLh0yTqBQ6d7@>6ZE>RkE35-xWdY32-x&%fj z9lcAG23-Opl#bpdaLv@`Mi`ONL0aPnxJc^P@%RBI>U4sBfD5N8AH5&o!l*wVj~`&7 zE}x(u;9{xDNACx?JnGNK;|G|i%O~guxMZsG(fa|ehx+sJ_yH#B@(KC@E|;o&^nQSA zp#FS3et?OZd~glar-Kohe2~`Z1pNS4K$VW(4{*)XpO426Fj1FJ&<}7OROO@h16=v^ z=i~7MOw{EQ^aETCRr%=s0M|eL`FQ*Q6Lt9n{Qwt4RX%z@!1d2Uu_7ckPB&zh>+G?? z{5}4GO1k`m{(%dnDu2Cy;JT=t9Q->ntX6s)34)k3{2GN1RVpHI#oV;$H2u+|1J)AU``6=?ePs%(B&QU4O|3O zdFy=xmp%Pu^!NrQ>hcNt2Cj;#eDuB{)qYruC zx^aDzub@>GS1y@Z~K6-yq>!!H6i$37kUkm2!@gNk}FeOQdKGRZiK6+{@U`m5hiN#!39*G4n}11L0YF1bR%3i zRXTb%!nILeunO5GLxd1ziZ2R#iTF7sACEc1D9A;K3dl(3$C$>2&p6J-uaYG4fuhGP&!&aD4PmREe=MNyZU688;$sj zDddzXt$UPB4Y-GhP&!)oD4QB^4-uhswC+(hHQ*j1Lg{GTqikxxJw$}k(Yi<3)PQ@4 z2&JQSkFu!&_Ye_EN9!JCQv>cHB9xBaJ#b0Y>xN~X^;SV^+#|T&TIN}A6|_zVn%bWa zL}akx+N(|{=m(zl)-t4ZI?&YO=iy9G*ycpX1+xYjm9^eAf=jSvo+Vg8>#`2IhGz-3 z3~8NC&^0_uuw_W=bb_woS%NJ?TBj3q4bKv68PXb^;1X<^X9-r&I-Ow8fy=I$y4Ekj zmf?!4&ow+tup&{HPtY}R*;VDEcMV)|_2=X915DKA6YL^z*;VDE?;>!;)t?VUC>^~Y z1eajTFhc3*{Qy^7{rNzI($V`ta0#{yBb1Kb4}wduWu7HiL2K#_S6qGAJWH@;Nb7Wh zet^ra8EpC`*fLyk_2=X915DKA6Z8XIc2)W4{Qy^7{rPzO026cJ@Rl<8P^&eaYKM=R z##N7p&t$EwFopFbz^6)i<1&XH%mEP|ZI5>3GAFtNbh_b?a{SB%=5ZxrE=L~*z&9$1 zo{SMV8fTn3GDV!};-1bj4{`_Lq!Nbgj&idLRpZfJ(cK7S4;-wM>T2z1Z>CbfVqBc~ zAowLbx-WV%>g)&6&h(B}iyc0$`as#p18A%i{M3iSU~ZfXE?kXA&xn2=b2<}>w-tVK zZ%)@Yr=gw)j;r3_sesHmICggm;5(^pTkE^wvo2^IR|)bR<;l0VI*)!adLCx>C1^ls z#As7%3pCGgkyYl@o7A3``i5<(_V#pZ7u0zSWx(>0e#=^E9=#}fG1|WbTnZt&*x;A^ zalHZIH!nUh$Y`XSQEvqvy&`%g<^YQWaXfRRsuFft^;ciysY6FL1fo9OV@G7pfOeRR zHuF`W#K5E1MXyJwH^7s!wHw+C&MMiK>VmIn4(#aCl_ERviyf~LWM$y+LY+r%jeZp~ zhUJ9o?@*+-F1<{=Vq_SojC6c-2J zV73X07sodZ=q(B*{T`Wm7(C3EE*{W=U=%3)fU4$EFy6UqYbVrN8cLQ!UogP~t|CG9 zNizOJsK(A+op5wmS|U7RTy?KLgFYA)o>c}9<*^45Ia<|`=sEqII5-DC_^0pk9YKoE z@}t^1lY__^~hm&3P=8UGl5c7xusGjg$o^k6Ezvgjz@nM zeH+XBb0~(=lcQC?hK}~8mS*_q8MlBp@3z=>w_sJR9Sz&(C>8fk4mVEIbV^>67Jvqi z73}1Kznxv(@F>8kT`6Yf*4c(os^*cIR#X};d0+~n}U|^pU zMzn%s^beE>YOz~Wi-){yJo?+{@37iGgoaghLfOK|sbV~}DxNa&jX-+?eCGl6(ujQk zxVjq&UioKwfd8Vz;oB=AzSwQLFelNZ1%?HSo&G7AavyR{uBr|+Y1jco@S(`TvST&G zyWqUGMm!}(F+F@EH4qC_@im0i_YF}kx zSHCpWTLSW-E`iMsMfTx=BEv`b@<=nc>oGvaV?36JrOby(P|#{)TAT=23~wp+xbg7m z*YE>M00QnJ7+=j}g|Pu>cc2(Bx_5VUHNXj?FwyPYm0`dshLBSX1>bGkE-o{I?Zq(X z%hav!(RZW>K`bL2iODO2^OzjZ$p! z9L}2AHZ(d#7?sgpqdYd1%z=5BjmXnJsg_)jnL|LqU<*3|4Z<7WU?uK@$zv5{5njM^ z=)gOi)_coLXWenOowcH^qj3W-9YyMgb}Si!4@5@;mSX%@4@X_XVHNeo;(({jd4l!D z>76i*9Vbs)kaO$tYb>_WANMIv@X`9HUa&Gp4H6=J4PL`p8@a(k&f1Au%vlFfOE}v> zR1If4iCV^4CsD_7)p0s@)CSJ>5VeW3y+j?)*@;AL;p`-$ zwsN+Qs7B6CCaQ_E{X}i!>=dF-;OtbQS~)w7sCLdyCu#?0XAsrN+2@Js=Il(Oc5!wV zQF}N$o2U~xJBO%!oSjS5e$Ku?)Tx|(k*L!-JCCT(bM_^o&f@HRqR!#$0;0aa*@Z-% z$Jv*OI-j$Ph`Nxoi;233vrCA>JSDx{R~Sh`NHa%Zd65XIBt)HD^~6buDLKA?kY0 zt|ID2&aNivX3nl5>Q>IKCF*OOT}RYyoLx`U9h}`j)HgW0k*K>kyNRf8b9OUP_i%O# zQTK6nD^U+{_En-DKV?yMbvYgeVeGCaCSFQFLHJdQ7?0LFHx^>b{|o%adtmZZ*cYiQEzef9iram z>_MV_!P$3-dWW-zh3i25^U zj}!G*&YmFZ|2TV+sDE(wL!$o0*;7RQhqE6M^)Y8p3o3_k_G6+VoIOKSl(T1v%Hixe zq8!eiCo0L=Pl)22y+BkxXD<@fpR<>UD&*{Cq6TvIQ=$fQ_6ku$IeV3;;heoj)JV== zC+aZH-XQ7-&fX+yG-q!SRm|DXh#Je;+eD4y?B_&H;OrMfP2%jAL`~uB9ipak_AXIn zoV`cXG|t{9Y6fS&B5EdQ9}qR0vtJW+G-tmd>R8TxOVsB$`yEm9IQx*O`JDZpsD+&U zfvClt{gJ38oc)QY8qPiCQ+PM`WY6l$b zPE;qiqC|CbD@N2VIc|v~mfVp`9O6m`ywWHk2DbwV)hs8Wu{hM|gjTBKU`cSy0R-Js zVoC1E5IH7icSn$xz9czLV^hoinXs&5GhtcFX2P7#ooz}&2dv>bIRE-!B5IOy zz(#OS%O+d8;g$}@mWODQm~OnvoS$7ipJa5?r;H4quS!zdMsiQ$CZQ=BH#@)q-K3x^ zhCFM!Oq|Y(emy!NPF#G=hXK#HTn38b#;%oz2Y zAb#+&XATx8$q=mK(G;g{lc;W{C=m!zdQ=Q5A^6Pe98Ma>r(RT4NTbtuOJd_S&LmBF zjyNY--E$*lsVJFt*Ezcs6bGV{xsaw5eFL78e$b3j5|2+OLEZBsGscs|51Ow!Z2h3- z+*xf%4SJ4dKWNr?5WB~BLcA9x{jL+z)+n6uu#m@59{Wxx^>R3l`NunbGiT&7&Y-WK zjFi71y8c}plqnrnLQH@R)sb(U8ff_h5NkH3*q}21P?ApFz=( z$!AbBWbzpl4ViofMMGYmyrKtvdFm}3^77PMIOOH2x3H{VZRh3j1;QNi^3>aM$jei2 z;gFZ7-oha-PhMes9|(DQ3W^%~FIqM9UlcX;UlcX;UlcX;UlcX;Ula|g*Iw5#P`_}P zW-bDEC*Um&B%tfk@NxyZuz+NAU0Oyayi3bS;gBf?2wlIALfGxo4G<)!o96}OJTq9` z5P;J1z6dg@8=HiXdyNDM>bl)tw@Z+yuJ+tZCrCy&lknX|L1MbKzRVRB;fB=B72%k? z!{LE4bBDSEp?0sk5bde!mNd6w5Helk`!CBNIo(LC?$96+U5k6J);MrYxHoPb7?b}Z z4w5VL>{);fTHDu{v~wPq3p`y@&YY`Ld};*FS`%_8kF zoXsJyM{#yEQR6u~hNy|09ZS??&gK$T!rAADD&?$_sB+Hc5jCB&Dx%=?1F>mC?n}r0 zk75@lK6X&WjR!SH{?dL~+^Uzmtr5dSh)tEG5&H85PTvQ6St=L^AlUGdHmJ*Ynb2bu&2}C22<(F zj05%{Zi(O-t)LSB47TJoz?VpAyqbx}e-5!=`xmhNmNxny*O`Vbl+d}n1KG)~Z!%6i zH18$i@5bMU4U#Qwbjdp2OEuQ};L5wWytgLFC?5YH{_7;@|Hi0mz(*k-{~b&cGEL-v z9OCic!`{rsj`~y=7G`;q#g0GF{z0%5h#lY^= z5vnbNmmlN9wTWE!pS?7vS!|*^VrA}Us)noI8&Y`9{i;+aT${CEPeWSVdLNJf2b?Wa ze>6{v$3KQ`o**Tzr=oq7u1R@0m%|(@8ULRX;Z_dZ9>yY06r9r)qb7|zInaO7^<@^D zrEvrAC0!w&;W$nrY0Ywy5*c3DjRS($i`4KuhdbQKOUD1}svBRQ~P!L(P{gD@ah%B^)IHyh+&qpy&IFdzrx z%R=#VIIxFzxO$3k{sost$s6K3;UTg%leu|d4trQ^VhBgLeT2V1nImQz&cY;%I*Y)q zi*f1*8@D~*%xN}mui;L$vjlc&J4>N!g~bV&VZrTpaixu(yK_J@0D=}y6z~5z#~6X(}#GTWjQPKb_=YI`E2dWavD1ZA)YKHW)#NIXh5(C%6;TY>~&X zY7RJHsk6JaL~1x)PIrWICZkvaV`>7>%HDU3}@Ul z8FQ|2uEnnQI&L*nmN!5hdn*I(t&2N1L0bSJuEWF2tQxs<3-npe&CaddY9&SZMs`3( z(Q{>8+_??PjuCC?Hu3cqNIi{txj)O{@CxbA2wme8vxVzL|vTzRO`y z_dBT+cL!(C3tL)Sp}Fq$ehnwuT_lJ`yFcOF=RClzU1Z`x@P+7UNr-z0zNvxcD^B58 zH=enicqCNe`dl12YCi0IALeq-BMyW0l{qw|Jm#=tV4;VYCmnVyxAqcBd{t=eNHxM~ zP;idu*1bDYU0v9&KZe=4^F`+wkHcci#GU7o&hzLe`$_)=ST!QEFTq+7Q9p(CBcfjA z(U+okV-Nbe!#>BYGf3$z=oh!8TAR4@Hf8g3Zkzo_E8oy(`mAm7Sfby%sxqoJKJ7Fwk#R}u%N$~dm$6;j(b&@pxBn&z!5dVLG8P*>F))!BkQl_{ zr^IK0hbD&f%SjCFAD?A2#^U$~3S3BUk9FzJmQ-uYiDD5g0W;sx?i+)=jz}B{g@(Bxese}eUD(qu{AwyxQDI_iA+r)kiI0+l z$*M~G{G6os?11`hOSgBYT1)1oy3*80;KYX~#wVeTCO8b1fag;)O~wUC_;BC?ax<8u ztLcIGUOAp9!;W*<3Wu$9Se<7K+uhQ= zO;is&5HN#qzvy-o#52*JNVFw7xb<5yy_3g3A3qbHjxKPN?*8#1Vjk3cbvNi8=sdd% zK@TQ+o(_nHckKOfRBC}gq39_W`7{kioIlDL@1?<0vzLE^GPmXp}S zt$$PEl{~_Tx{60)L|wxpNupqdHXnxhp7vDd-umLLZ~z5Q+yL_`uzw?u^dq60d1N3_ zx8f)BZ7H7kni#keU+0lwlyW3D5Aat12twmfmoP?I87-Sr4;u&9yyMv-@`9br13}im5Qj3cw{xD{)I;1cs#liI=TPX2k9)CzACRx9nq*cfqOl%N|$taJ1pAvH* zFoI`i_k8x9Xj^JF8*z=Iye7Z9FoCcE2sK`9j$nwG4Y>U$G;dYd$`*{2>B>4bHey5Q2L$Np|KE!PraFY-7`2UgbJ_2GtC}jOn zERVz<=XQUhp5*brlh{)r_M<{pfMNqE@fojUHo{svPh!swKJ+}d2b0VT;1AeuHFu^{ zun?OGdGaOk5|n(|VH>zjgLm>(*cLz?% zZj9TNM8&x?To}ns^vlUj7P3KTgcjv<^SE72V*Ox)3>hilHZ8H|4&e3*N*%WqM996&+V@ga{{;TAgYzyG{)q%bDM^d+#TGe(IU5#+cX5^c5|D0 z`rKXIrY=1fpgloWPUQAeMD64DvqbIZHoZyZp33c?Qrzj>evPQl!?ql9!n0s=4^ij9 z1|6bcYe_v(=W+W@(l{Ts{!rY7+@>x%_abgn7oB?vx2fOEy^Pz`TjpNDZR#y^zrtXjJUWR|ALr2$qMqc@GNPX1(dk4z&7(7kdWJ{m5cM37${yn`yuxR3dh~P2M!~qe(!=43)LE;t&g7@kAVA!3&#+Lo9d|6LE+IFIgfEvEWro#32^E7)fwQMDWTZ;t&g7 zY(yMl!7GV~Lo9fn9dU>SuMr{+vEXGv#32^E=Z84Ng17k)hgk4#9^w!S-nt_=BqDgX z4snPDFU27avEbD=#32^E$c8w?g4fj$hgk5c8R8HNUKT?fV!-Wh(j!R2?ueA1+Us54zb|H8N?wLyb^;r#DW)J5QkXs8VlkO z3tm=191ym+-#1R39iRaoP)Hsq-~or^fdU?oNFFHQ0gL2;0v^yv9w^`ekK};@9uP?$ zDBuB;u=AI^z=z$xF@kuc>{1*qBrovcfFXH- z4~GoN3w$_eNM7K>VMFo)9}XOn7x-}Kki5W$gNNh=J{&$IkNCvhMS>R;@ELr90zQLJ zP{3#K2@3cOK0yJW!6zu-Gx!7rdbFt7yor^ec;5G6MXz0?$r*y0HL2y zJA2x@;kWP-5}og65zm8f0WQ{<|FpLc_%;{Nt^^-qneOf-u=4VrNaj7B_hi4EydT1E zA+2I7gac)>}mi4r4 zO?S$e!W!5H-ns@3R7VLJ*`Er29BxZZ!?J7_{0dPGmuz&3t=?&1lk_bP?9c+M!&Xww zu4(CN0V9>|?H%1>YdHw^hsD9}u5Q>tLpC9*UmfI_s%~!uEVz{pezg=a0G}1H2#dnM z9Ol3on1%TDAZ!;Y#Lomp2wwz>5WWW#A$-Qith{G{j<6XZ2OsnKc=)8x$HPZ@ik}Vg z@Ts1#10U*%5I)lrA$+7KLij{agz$l$2;uWQ5yHoLB7{%#Ld9Q!!u;~c^RH5LpV8DlmpHU79pG(EJ8RlScG4Y zA)FU1`154=B^jPC!wY11p$xw)!;55iu?#Pf;iWRXOoo@s@Cq4TDZ{VG@G2QzEyHVM zc&!Ytli~F;yg`OH%J3!`-YmmgWC$n!igLlZzaoTFe?uSWcY0v-Yvs>WO%O(?~~#EGJHUW-;v>iGW@O#AClqsWcaWQzc0f_WcULa zJ}Se>E!?$GkGa0@u!=KCW7c%^%4BwIAyE1%FhVRP| zPTm#ef^&C82&e9f5YF5c;csOK=j{sqLmB>FhJTRZA7%I_8Ga=x`-3@A5s{Rp)JFx3}YBZE`)DP;r9U+ z$$J*G_QA-6n-?cPXboblX5xhVtf94&o@B8}cYWJBY{CHRh>7=E#rIhdKc#l!gh}^V zWoswh1qycFbMQBpS^s5)af`>TS$WSxL=FQu?47)yz~3Xla*U0Gk8!3!Y%UuOpV7>K zF%5FF9IJw{ycd9mdnFv!A3)7E2X%Bdpx*U?I!1vyHVo8Ub5NDpfO^jdYMugB6$T1^ z3^8rKh1r05-v?@u0<|~{6#Q&!3TkOKpnmNGRii-FhJk|LjZHxvmkp@j_&}{tpjL)~ zf?uXgL9NaP)Ng&D)+kVG!$7Sw2ely^P`~qm+NeNn3Ihe7u9?Hu5QFOQf%<|1^~Eqy=b3}bYLeIG z1N9{Z>ijTJ7np#|P>n1?u83P?vnBpe|LQE(-&7xjCpSv#F^QeKqwJ1?s9W zP*c-C$)J+Q1&0(N!F$eY4Y<%iu zUrl{Yf%Qo=7?qd+|y2I@I; zP|s%r>hnHOKT)7w2m|$^IjEPi0d=Mi)XNIgPs2dHVh-xnY(Smm1NE8$^?DenH_So3 znGLA3eW2b_pnetx>TPpSKhFl#IX+OoP@sMp2I?JiQ14{}>RcbF_Z6sLg@O9uGX?c) z1?o3ppnhu(>cebm>QY}#{a%6kLl`LdEX8!uEGtl#`9S?if%+&6)SnMAsLOqz{-Qwr zH4GGdtaC_f>IxsI|5Kp;9tH}&8#<(*uJnQWrvmk_Fi`LblPReGX5;8r`9OWFK>aTS z6rR^$2r3fE2GrGFP!T%=DiRF?6*C7F?>i_*fl7pdN}7Y>eFv4NK;?&lf=}B_o3Ehn zpb8bJ0b!s9nu8kLcThtVsG(t?hJB`>hAU7b!a%|I&!)|HST;3vz3=HeT!A_w3>19m zXbLJTNB4sotw0?a1`58pGzFEFPx(QOQJ}_#fja6l1vO5A8XpE~!eVa5-tRDmiB0|h4!n1cEgYHFGS6}D9gPdG9KmDSVd zuc-an$Wz~GQ_-d+Jfm#v<3QqMh z^{LuyrY?R^%M_^PVW8kN1XEBevjKIhucqo0s8wO0R-1#$s!Q;LQrq7mVcXyEh&9ui z%F5CGpw_FJ+7MP#8_hv&&Zhak=4-y=6{z|!P+JZ$sIU7#r4*>GVW1igF{s;opc)mZ zbQq|nLk#M6AE;&pYFiknmO~8c4j(ABQ7{s=Q4kLhG=2KA+9>#KA1Jj^FcP*=5YI9+ z1(nrCK|d(9Q7{s=Q4o(+{0u>Z><7Wu!MCIrwg*o~@b5Q%U={)_-cZvda zY8a@~%t4)z4XC?)j;=NeM#44<;t`yOwE6s?)JDNb*hWD-4fK$Ly2n>jYNKEzY@;9^ zOlk@$tA6S}A1Jj^FcP*=5Kk&K1Z8FQ-OT+yP!}pk|8kh4Ut|m_l2zyVfDhEg3e+WG zpe{8Bl~wckL0zUmT^=dRJ)l5+CkzyvMS4g~=TT?Oi)Fi>zT>LCU7xDV9B z3e@+*Ks|DZK|SFE^#cX!(J)Yt9b!;V`anIdKs^x#>d8Y4>W4m1KUAQe3Ip{cb5L1* zPVf^SsHYXEABTZ@#vD{upVIk3J*z-H7Y6EiV^EP7vKf&5pk7p|PvR^np_QJR@QIJn{H_)6O%intIs>>P=NsZ-vzq+yr0X!=CJ7J*SH3yZ|)8_~Eo&xoL7^q(vgUW6`e8ph{bCy44=O2I!`|+wIenXwj&mA z*f0c@UFZ3VuldxD*htupSiJ1R6jWBt=Le;B#74q)#Nxdprl7J~pYnrJJ7ObYJ7Vz) zltT*YHDB}nM?HQ24SV`NHU?#Vn9bD159)szP&QnqeZaGV@Cq2yn#$@ov$uUUrFL1{VY{sHmMK$ES)CQ+2Q^AH-(g|RcepvItY)4+_tn%9 z3RF=TsL|%2vN~+W59&w-syGbP7-LZOQP~X0zx36V+GTBr?Xt!j#Y}xFs~;iX@qtpi ztnIK})_A#@DX6TbE`CsIm$eyd~rl7K#y7)n< zUDkHkE^EA3&JdK9)iHqLVhM?>@**txIP)DmS;h3;4;aFo(*=+&v zgPN;AeJ%`Cr8%gqo<2V)b#$g3c626QGicg;S^3oaKA&2oYHD#Ibz_fvO7wwaOe+R!2Sk%I8z76{s~~ zpw^m$%4$C42enRtS|0{#gE1(3Q#PHaAJk?A>i95F^~RtgS?zW4gW94%rNTgMH3pU4 zUKc;81_i1y3{=`2R92nm2R=t{QlOf{K*0@-ru|e_3mkq>Eeg~LVW8l$S3^+Q%@X{e zS{10aFi`Erpt5sxKPa`!+78=gjaT3r)>L+m?g!PWYN{)&rn=2RWp!+{?<{M(M}gWE z25PrCsI2Bweo%W9sJ&sJPBaE(@5`n~_Z_fppR7Rb4+C|IF{nsZZ!>;Srz%jVg@HQV z7?hRO0o%S)zwI*=sLzLiI@26fRzBqib(R8kb{MF0j6vC7$i}C9N0HlKRG`ia1N9|i zP}%vEAJq8@)CFOnE;I&ZWpzIKhrR*%%L>#*VW2KH2bGmi`9WQxKwTOJ>M~Skk5*-c&ipl(s1ZVdzVRbx>0*R%1dk9PZFahhd$o>7^r8>L1lGDtRIv*Bi0T(Bi8-|XT)apHsc5N zlB%hf!)ofM#x<4Q_BTJMR}`pM!$7@e49d#tH)KDk*A=KY!a%)g49fmlHje%;pQEe2 z!*;>pcCS)ZSq` zZ11pbzIXW30HyX0+hKc$?N6|GIIB%vAN!h5?H#tm_72}>d zS5tmaaRtf=1C{tpK_wNa+%Qo55QB>PnlDd*$`1q8?=uC}Ux6wJ166p4LB)JEH9&zH z7zS$4X9{Yt0yQKI)X+l=D#uq-!xX6DVW38Qrl3YDP@}>?9d?L8#eFq(xB_)V7^os+ zP+2WmTe&_^>V)QK*a^*1^Ano0THFtSQYSP=!%k?9nxD`d9iPqE=dY;=s`(~{HQyxT z=F956&*Hx3o2)=h2?JGP3@WSlJ}b`$YN`TN8V0J&7*tjZ905?}3e>bPP}4tCP%{*$ ziZD72GU-QjUpk{}Gn)8{0QhSG^VS9(8=6i>;^QnHmno@g*qhWi8qvm^uKMhc7 z?{GA1?{L(7?{IdY`ul2Xf%2(^VLr9!5c`xL)M5pyItb zd+#gsfl?FFKt=MNN1j>mHzAA+MYM|*mi zocKU=?_D5dX0j}3^2F##y-WhiQ|>f2*$d^V(bJ^K1iFBG3kNmS$dd9kccXI zoJx*r(bHKOn8G?pM6eDZ0_)-I=sCS}82Lc-eA67x#kv(ad?9*)o5Q(~!xuyj7e>FV z&Ee8dEr-jZm&+V{?s1hqgWm3ez?FLt=&PgGNRuT{IxJso!UNG8^%gk^P_^eh1HzH$ zwNSS=MQ`qf3w-SBdMmwg-2zRfaNQy*^ESQ7JNsbr8+w!9>VwH|NAK>{fylycOi#|L=KPWtK~6$2E7|kWRU4| zz%2N~;|Bo!l-_3VY7q`0s^tkUXmE|_6C#HnMW1GN-m@Tb9E-w#j5!lVjGX*H^hJFZ z6G%pN7*6yV`8Ye#XMw`5)`>m`nc32>e=LfWXM_O`HTp`-MJ>-bH&uX5mEN#M%=@dn@`&C>r*PP^32?vp3=2TcSws zMBkMecC$GA$5{RZ$Z%M6SZr9%1JU2>vt3M*sz&pp??wM0d^tb*e)Nwb+x+OSFk7@3 z{QxLzr~K%zfr<(0H$deGP{VSf?*X9q;oq;|-v{vT*YNK*0^pzY9{N{3u-+c}5!Oe> zLq8HG{}%l}=|7tQ3!+IMrn2X&Xn}{TWvGbn8zYNyvgA-CJQh)i3Sg}d5$r^(tWUvejmV82k z<*{iRgEPqBEHF6Z6B?Wyo1-y!3>o|!7(C_^8mx@Xlh1-XMVokUtms=%X9m-4%V8-1 zB&JreD%od2By<(A`LPA^xpqyDxHopBxoLOWO(t2J)?F4ExeII8Dp#8+cW9NDnknzl zD%YAR@6;+UH&gD^Dz7k8?$RpPnJIT`l~EA z`)10wX_bFqrhL0r`7tx)JG9DAm?__>RsNxw@;9`~KQdGPrdIjKX3BSIm7g_J{+3qx zc{Am2Yn5LxQ@&fP{F0gSJzC|TnknC_Rese>`97`k>t@RLYn9(LQ+`0J{4+DLj`S)hZKhP@w z(M6xK{aZX39@!mH%$0{G?X-pJvKG)GGhmO!+CT@_)^gf239Z zpPBO0I^`V8O!>!JW!p^o8Le{6O!--@a@t31F=`DLy0AT#BkYL$nWDZips9%iQes#bY~neuB|pu546g2%#?qvRX)Z{`8QhSxn|10)hbt- zDgREZTxF*Gp;mc;ney+o%8SgD|DaW_HdFqiR(YwJ@}IQIwPwm6X_c3oDgRlkyuwWR zFIwd~Gv&W(l~e?(-e{)$53TZMGv$A3mFvxv|D{zEoRF9(<*N_Qnr{@xy?-3(kgeDDMz%*JI$1Bt#X%{ za#X9_W2PL_D(^N@&e@~i$FwN>eM~uf^(L$PVDd!0$)$ZTd6M2_Z68eT)0hUamKJW*1Mmd^vuq*s3sGy=Kh`oaK}}N9R=kxYRctNP(G`sd^QTo6>7?rQBbZ_Q$8031-<3d-lzlxw1(d_hgQE(*#Q)s*X_pnOS9xiJdL)oRMkQBbZ?Q*McZa;=(j zTNIS*)Ra4-pv+QJ?uvqPy_#}Q6qFm(l&?lXxlv8|dK8qK)Rb>VLAhB?`F0ePFRLl{ zMnSnnP5HklD7UI9-;08Bo0@We6qMW5lpjPvxkF9)Q52Lr)s%;#pxmXV{3Hs>-D=9i zQBdwtQ+^%=nJGSP*Z*z1?8J+%I~9~d`nIF zV-%Ect0{kug7O_T<*!jt?p0Hsh=OvTn)3H3DF3IX{4)y5ch!`CM?v|Xnld{I%JnG%1_mlDN#@!R#O&^g7PypWzi@oKUY)oC@7DpDN95_`GuOYR1}n7swvAv zL3vb7SuP67V`|C@QBZ!RrmPqR<#9D-R#R4ug7Or38Kb5g7zJglnsRUylyPdxp;1uA zt0{*^L77iYIU)*5Q%yN43QC8XawPBrBfQBby4937oH-?{VFrJp@>(;6z5_S-%WDI_4zZS5$opNo{%>Pm zYZi&Da++CGQ8~nyF$cDsuB==lvX<+ZCB0v(D|b7RFKzaGO|MxBUzMDpB#HdXn*~XI zB}s({h9UK&fs&+BYwkyUQ4tXwCu$}N-m$mc_Si=iKeK%F0b6 zYq_1Wa`VV4w^vqf8Cm5H%F3-HtK3mpxou>XJ1Hx-kF0WMW#x{MRqmp!+&Qw!U6qx) zMpn6-vU2yxDtA{_?ipF-9?HtSBdgp~S-Edym3t{G_m8Y{Z)N3ykyY-atUNff%6*lU zhelSppR)4s$SU_&Rvr;q=<-y9z<07j(L|J)!WR-_1 zD_&R->UwkXy7fRXRS6LjLkA1$ub|^Y|ihWVm_YC9&vYEZ!TPIF3B>NXPGOuo2vrl^@#Y{KF`%l z4f8Jg**@=2e3*B+-DvN*Q0={-Xm4(g?aj@py%$5Zw_4HOyd2w`ms5LdLbbO}(cYsu zw)bdG?PY~(Z-b(}$8v1%v7Fl57^=O^iuRsyx6MH>&*aqJ%c0uas%Y=o9NT*~r}nmm zYHx?4y%jmOw<4$Zc7|$ix1zn3IkvYlr}p-QYVTD=d#iG6Z&gn1z2<9gm^Z)F^W>K| zvdn$k&3CiR{fdS+xqIdyoJ~^0^;C)GfUn^J-iB-Y8a}9Kaz-ySmSr&;FbtIcD+toosQAX?5czu9hn2i!`p`16M>^Ox=BThf`$ z?R|VJF#moi^>MhWkH3cM;|W_IPXzSwqlo+Xkvpe8ew0%mPlgH|Jf{lX!N4YimZgJI zlgiNj9;!(=Le=D<9Gg6pQ|QH?zI_ z!HO*A6f4eRup>0hQ_L{U>{IxKLF;dT_m~b-+KwC%BcR`tEY9*d3OZ7-eKA={MJv$2LG^(PJkLruFF{&?YqblYb6%RM6;=WORgG@rPnrx3%N%g2o$H&T<<;!Gt zTgcSnD6a_Ym+lF}bw`XHi-`Ymi$TzCS;YQWOH!Aze>u9FP zh~Fu?ZGW%uJJE;G*SwDAzV<@Q@Mr~f#cQ`#}qHgs&yuh zlw?RC$y7f{2@i?mj@6DCn;kRzuXo&+<#@nqeyF>Y)coue#~g3Xx7L|u!qyxXSo1-D z&2nLD4iBvPkiTXHxu*Fpdi$`{+sguLKH{%g$y;+iu1c(3-~zQ4OZ)c~?vd^~aDe)P z#j%LEy3`Om%BO1hc9aR3aXe1!DIH6CXE_zWQ6Rwv)XoZT8gu}w5B zx8`jL_d66#)#9~8Z#(l^Qg3VX+Wz`hQ)xU+oZ6MANvB@QFZG}5YigRJsdSz$>UZbq zQvEu-j=#RuR9#+IoZ6Gul}@e4>-kUhH8nk;DL8kq#goA^1W#|CA@S7b^}ReP#+&{` z)YzMGJvpEOZy>7nJ)h4`&uj&W>sx56*oARcj>R{efs@jY<^Hr6$O08{GoAc(P>QLTXs@j6L@KrtR zZ?&!E+?Kqhs5P9olxnr&t-Q6Ye9@Y>7UzxNt)=tY@HYPQe8HTd2qu)!2| zuiAa?TK?>c3qR*be}CJHp$3xRk|U60Rv?LW35x55j**hwA4qb!zbBm|C3zr_WVD~8 zYosKz14+jCNxCaZaK#nqlR1GTSNKVKDoGTMeK3$@te>QJq$Cdol8p0{^!1Q9uMw+q zTi#aaZ31sA>8%}aC-jEZ+nJua$vK&^EaxpL&RhL7{cSYud3!-KmA98@I`9rQn%liJ zclc=r+GslRj)LYc-ch3I#5>t&?)B2l^wS`TnLAc{$JCj37A&)PXNjc??_y(_BUmu+ zd=ukQcP0PCa6Smi-47eq4|b=feeg79TE=U&b%<``^wO?pj+gj^HB%;|4xL zVjRgw+PZ5e9TB>l9?y^BqXg+DK1w3JoL?@Jiu*S9@Go-T6q4GBr*r&~TI9YlE0Fm3emk? z{0gaiWBFKn_r&8RB2we{I8k8_A176~l3(emunIR0#d+iTcyZpVe7tntRs1TM*e3hM z?#>}cVIS~f@$^;L6md1bS~UMUzglYk8h(x3ydw6C-B(21iP0g?l$^fUT~l&8EhrN+ zujSW@&b`U6l{z98OoZ^`t=R2apb^JO}VIRLvs&GBO-d+KBAf4~|!u^!ErC^2I z)AB?8Cbt)|-R&X0Y~E>Sdl1HVBu`zgOcYW7BcV{o&d zuXc!==$VuGWKrh}K3S@B6Tit*$0Ia*>RK8`7xqPFsk?oc;89wX=i*ZL@Q`N*@(vAo zrUMVY`BTSI@#c64Z+?m0xA)$vfAfxB9m^-(W=dvDliBRh&HZj~u14rH>2AL-eoGbc zyP4lCVsV_`EXCp$eoJutz7c}GmES5Ve8+EDgk;3nY&fU2AvcD?|o+fCf`Hyi=E`!@Fek`yTJh@ z$N|&%G|}nb_%x~0)A@9}OKD1P7cRY>-!3YgyjrsXfOYajS@N4dCa1`o8K)cPw~4Y%6s@dGNlVoAmJ)XzT$W` zi1HVUat5D4l&*L_L!!Kw-)p0E22rjEqWsCCoXPPn6(|$mU~Xo!#{v*$xn+81JUbXCYxrR~{jcL|(k$}sCUtQ>pYQLYr;=?iyC&RD#C8d>CWoB}y6`xETy&uVe_ZOq0=^(PShma9 zHSSR%U0{#Z8h5yhDc|C|#$8Qv7VRi4XL0q(&5Av! z{RYUoFlj*AgRTor>DymE$)6N`t<0a4`nrfOvIW+5`z6cWEwn>zH!-r@T|%BIrl3s& zS?jln&wvfPBRN1Sqe$wuZ%F*&rSj zSFaFZc8ItMX(I`pj0H)^9pVzcM2tR-FOf#SlrIgQOr9O$)BI^sA)P-hRanNCS?;ng zfE$w8vXIVl+G2`RcZELnjCP2ioDq^TXotAL9p*k;;C6CDxaW;*3f!Q$HM^WI7hbH( zmrGuJhCgGuo!-lKWl-|NeQRsOVkJWQ5RP9#8^a`bm*;)_XZf?DxlI17)Z7ZbLNw>t z8?bBH=nj3s;W(bdX>Fl+9t*zzWK`n1q+!|ZQ*9oq^e4WIV#j`vudp^*C z4|pPX1b@KuWp{0;+q>!s0b;2Xqf9OC&v*Kl7yx4Vn@`|rfQ$loyb7}hf5JAH?$Vb3P^J<sc6T0U|MbCHe9ir!x`3|Y) zJNeEqJ%1&qo_iNwwa;IPtmm(U?)mqk=ezhW(es=6E~)3c`R*`1e>JC`hj{`rnY|iW z&tDDMbJr9_W_ita-%ZX3^vr8eB6>aK>8@#t)87aEdyTXHtV zV+^k8{PiZ+r>-=@WcrSllVtj+Y;cuLhyq&dp z=&Xf(l>g(j``m@3)dH)U`Kf61P5!26^gjNk)aYCMEq|lFSpHAuaLqz}x*s$#^KJgN z;CO()EpfcV-%)V98^kd&b1&a3>d)bOrTY8$KC3=$U_5K&|M>sJsSol0NvFQc-wi(X zJ^r3J^%4G_bn5&3eb1@Bx54)F{o=fNe7|(w0e(QH^emLN8!hjLd%xUv@%X;Gap)-7 zE=AsVhkg&hewq2cxIPN8;&|Sk`G9{Q2DX5IAPww8{-GF{wV#mX^uBvQ$d0-e`gHKV zZ4*j&Waz`nLJA-8k3^e`_(xKk2l+wSnVwS*@k8R&r}!c1)Q|bc0rB~SenwQ!4Jp?GN|vfh|7!#Rr_#zO=t3v_H(1vpqih#j`zXPS<>&EB6Pvl0JkjTzQxu z7UN#V4@=|zjDIGN+jHvY{Bv>YGyHSu)Fb>zfGfY?Ux@Qo@GqqEzT{uZlnPfKh}e|} zB6j70h+TOgGFKi5a^=L#qx`5C@G5>(8t^fG%o;HAx%Z0bEB=)@^?Cl4bn0<_T%2lM z5v>WjF8R<+ANR0sPf}u?nE5sTT5zr7UrSuy@Na^f{g!_#PF>Hxl}`PRe`jlUb5OG% zDVqJBe=oSU@b4wAANUVevm%dL1OAc!D9+x-f0WMtiT`A4c~?-&2W>6W?4OwVGyhp| z?cqO5T)*&Nlr8_te-&rH%72y4{*C`;Yx&KfmJbEAOuGls{0V+S5WdY%NQ5W(NkQn% zbo<;*ZEwwf67EJ6ed<6^|IU9G)bH}&CF(!;9}>0WdHc1*C*f`Z(p?+Rr!Ty_EEN6? zuJp+b=_bV|VLqqi+MnV&;NK06^6ZAZo0LEKpQ864@;{~C|Hc23dhZ%8F9Dyrn}%Eh z9Qa6->tMjU!k>oy$cXUa-~4aUi;wx=QZN4D|9E;KJ|pKk9K;*?5g+^Q%umI;RO(bK zZd0YWKJz__2+x+f_Amcebj|w^mdJ>-=l0(=IvnP<5xEI-;uJq6sK4Z= zeAESYXBuobH<*W>Hi-elKI{(jctUyj|5#83`WAx_qqp56Je;$izViF&3Xh*W*%93~ z&}~Bu=xaK%4Jiglj2M!YC%+eyH^n7=3ThmA1w^qpIaUz;L`OEFI3RI8-&naBmE!S2 zyr}dG9oZ`71A-ZZ=W?vpPX?uqBeumsWNEOPsA&q;Kj_HD>Hy+Ub;XGnoTAcSbY!dK z0^+iD<=>#Le4*@00%|4@YXa#b!N!^hBvI-LeWq(Z!Xw<7gcp-UMT$a_tzv#4`K^lh zXeQlzOo;PVEPxjah>GOE0=9~7Aa1K7X*8cK{x8K>C54b2zG=fhO}-SDup!R$-W2vG zL!Z!+(RQ-v7lk0%)~|v<3d;UXNc8yET;(35_F&mI+sy)U7CZtJ0B;w-S&_7H^PPzltbWmBCS2@K>WF8-EobRXqImU{P19 zib^%;$W|#82zG+1V0{%yu&5i=1a~buvT;`jQeAKd1?#KR2^RIbhG-*=j%;nz1X9!A z|A1h96&Ng$^r@${1YbHG+4yP$scrH3u5X|iYC26+s!K<BO7ZoAk9==X^t0~i%Pxe$X2NZkQTPC^bhLFcL80YOEvF> zCzMFxX(`wT(vgk56_8do_Mw73C1IFV&4>K+&DabY$z!ARvP* zhuNP?IT7X=O8afl6Ye1)w=}+93`R?XMK5lqBU>+q02vbG6#J)vPPnfM*@*oqx)bgz zL!K$!l|A83k#>)fEZfmr}^W_=79plMxx61HUES8)`p}kR} zFSpZ?tuK@^FAoYNz1Qg1?8>q>I}sm_wt%G+MNBCmq>Zp`pJ z03F#zITpxR|0wPJ?3q!YxXK2S4quEvxZiit3|bWbY!b`4UlU*)jWCMbN_FUH!!rc zTq~+RMn|@)6M#$zu6m6eq3m!sbLZ2{!(9j8^CoWG9021ad?g%6tgr1!nBg{UH?yQkn4koY3J`dDY+klg$1NcPqyBCT@1vEJoj4I^h}D&i>p8|Kq}4qK3DQ*yKL-x4~q`R^7Ww*>o7 z4wAtl2@-87ZWWC@O-HsyrU01|)QD}Kpb>iTU#$d}l~oWVw+K=JDM+Xq`a=kcAlar8 zDxY@ZK^^+31a)8S@3)^yW_N`?)fOe%VNDedTuw(e2i^wcwqOSyg#d*+n;VPV9Qz_?#3r-pq1B*X<BfwO_k4tAhznadYRl;(hFj%Z{f9oZUr5Xgf;jo2qjz6hg4%N*u| z9Ho5jv7!AO93}f)%6BGF$`^5zAc8Po6JVQ6banNR@Ze@TvU%`fAP)z7(7Vpfu|GLr znBkt)lAj#FnUSt@@Kd;fSnC|JvizaW{?1hPQw$Wy^pZRtNLH#RI=0yZp3XRtX=ig>?5S0lJnhet-iC+$X0b3kYzzt?P)lFn1m4Veq~F*ekK3uUzHpABTlhNkzbY51;ldUo&V91%{$Kk zc_zp^_WeqMNLE7H$v-O^d5?~4jjRB&BDfKoU<*VN0`GnWx|Fj=fpCrvTnPg;UEmBf zT_EBp<&XHPoGxir3jgh=Bb)zL0a+F7KihW29Z8Vr;^#Th$Om*}Yvg$#&j&SPpC|4J zgGAdEOb0ng?$fy{51dNwGYFD9;vf|We=#dxQ_+>w3&MdP(UHx8F9LZn*n!^N%9eoL zN^-qOPVbY!cV1tcrDsx4;}%#B4Z@B*gbnOv0@jChr!i;?wW%%9Vd zZOj{hYzQ8+waU>Y#zs-~3p%n@-2`M)P*wZvO$j5Uh*!D5tMZg^7mFb-_fjIBng~Xu zSLJm1uvvKLC>`0n^D>Z^gS=y34-!g$@j&cRRN2I5=i3fk8>`Yo%3pW+rVJRj;9oRaX%#)OkGY&na?3*rH+ ztc1V%zQm3gTaCAkeP(uyD~89EM42AbDyA*UCt{wDc?spoSTojTX2;$i`(*4>D38bf z8T*f!9XBcN?znqVejE2s+$l3Ven$NK_$SP4M+HY6M+V9l9XlMmQGV$7+VP#4?JVxB z=B$ZwnDbia^(dD)*E=_%e8+j%dBn_ixn1R4m!PcgYVYcV@+Q|z*ZnBJcm11SnAr)n z6PhQqLOC$u%7m*?KAx~D;RTehBz%x?(9BNEmsm6rKkAv7me?Y(HOk3}_a@Flxi)c6 z;%g{>Okzo~W_D6)Qp2PsC`TntN}7yvQPN9EYf&CZ`YP!gl>g>0kiVdr?Y_!A)jb{M zI`=E?*HQkHoRsV~vy)pS_e}1C@{#0a$7Q2tyvrf|HOUARr* zzJ&*%e6#S!g%6wAMaCAnxyTfhj~7{01mi8TtH}FBJ}|S3wkX=ODC!qIT=b`+zna;_ z+{MZjga3;4FE+N=c$E8!eO~NKGn>cp!n~N7U3_-&#l@GR+)@19;``0)5;aRSEztty z7bSix@w=H_vQWv2C99a(rG}T9P--H|wWaoyg5OG;rHhp=fpS3Uaiy<9`CRF(rFWRw zW$Kn`Q>H!2yURRU=5drCm-)WTPiA)6;bkY3Mg6kJ%l=swIw?1^+=6mXn%U*^moHPk zJjxB_UoZcbnO$LIg^3kzG_xz36^m5_f2H_JMJjQW^(wWk)WOWId`sn7m1m>;w(>uf zp|2{ftMsYTALYy{3#x#x%C;)|s=Q}rS52r|vT7NW4XSpi+8O1YRp(ZH%*;;hnL08R z@ko6)^^4SFW_Gpm)zYigL%E>ZbJbonv#a;1KDzo?GrNYnM!6dBTa7nr9IElDnO*BZ zt*>f92epmb1#1^Z*|YY@+Tf}ETJ4W&e{5!_C8m{1D~qyI+TgTdC~ru+Cv7Imr_$D> zWubf{?NAzcE?sizTKsB9c6!nDD(Tfwwn*=pj(DYyO}{xE@vL)Mo$KmMLOH9>!a9pl zuB-D(9q6p?vbyW*VqVn!U)>{hkDA%_O4X}bFAZh8dj0DSLiupLr|Ug~a%a8w>K!n% zGxBGY$$(!o8fA3O=!SAu#=;EnWgO4=GXwswzpVcH`rvC&y+Pv!%}~DD;KK%o%b%UfuAHhIgaf)9_%!Pf-5Vs6Zpkheq8RjcPOo<%~uP z8-c&k&PE?JI%sA$9?9JIbq? z-`@N#ly5XY-28}{-J)iTmMz+#oYLZ<7IRUqY4KW%H_hyp&X%QHmP6U3WzUv^yJ){R^DXx$s-1Fe^~ zUXF5S>knFEe64?L<7|^?X1D3rW_+7#P%dnUYzS8bcJLsZ)r}o3!k3{)v2S*3^sYAsMnH?IV zoY7%n2l%yP;f|>tYoNTjt&ROd;Qi6{^Wr@2h^8C;c<}cj}Mv4VXOO{sD8$?14iEUO(^#l$!_c8;JQi@cThA zgV3)*%LlzYXq%Zmxb)!k!O-2{-h;;uMxGixd+^hPq30pD4|#M5^2m^_L*5&5z|0={ z@z9@#{$^$mYd);cu>NND@M**64u?L59~=Jn@PEzh5tTdeP&N8z{T`_9PsA(vdj@md1cU z#Y+|TiaO<4KJPD1QysZpATIv)Hn!I^SBdJwnIoXOOrd%$*6IS9>&9G)+A>3^*R9S_ zH?j=Tl?Pa22r`*4+&Ka6?9TFsA(TmTIxpDmcQSVl+%kV8=la_4y5mY#FoG83Rw6xL z;rmBep$Hq38$6vl!HveuVMR`(QLEv$LM(T%Vy9WxUcU@}x!vzmV^%r}oY~+6k3!3^O1a2u zagz&jn^$s0m0a$!)oqVU#&uX5mW?k~ILuIGt^?t_E+XdeF-hp+?<6f0L zdp`74_HIko<2>-LzV+MMZLu<}-+AV8+3n|J z-(%_RChwcQ*RcWTq4(tooUi?tqfmwoI!~h@N8)@QL!5U`c&EiJY{+>W5IHF4`#9uj zGM)`P&!b{R#ZK2C9))O*P`iCuGnM^%pO#V}Smx(~An7eREb2wO|e^%u#Qt#Q*5bTN(Dw?iMK*T(_^Yv-F2eC!KAaa(O0X8aDHpLH zEML&9xY+&RTO3ES+b(iRShDa;kyUKE_J{3r&DtMG82HetQ+$vVpB(qRc_AO*)hg@` ztsCD5d#w-cYM*$tL;7)r){ppV0izYWOH0TnAuBD@YOVd^ml63zeuA+ByGN_WrW#o} z+BbIP1gqy>t)3wD$O_W_306?Bitf`YQmRN+lJ=2WNx^EmU#lsknq)<3KZRCQpsK2$ z_fMU&Q>+J@eV$JZcAEdma=#eIEFQ`n;yxhiC3XkXARL;r^^=Ck=)9pVDZdY?l3!*e0!dt3M>wm?h7 zcMWdIMEk^ly)8dLx|l80YVoN>UV5}&{E8vJ_!7(#wn$6HCK*{a+BbIDkZ=`Y!uu`++=6S~Va<)SID@T7>K7%;5zc3BSA36QYN6&b&3a0s% z5SZsTpSrVET5dVI&T_4FuSNSTXSrEEGySr|U0!E8$&G&CtTB6DD=%W@kvB zdr|xDw0vjzj}{E=yVIGyo^$1=x?8fp}D!KU=1eWdmp`3ReQ&yNyM zVw<#-lzt*N$#T+uQo6~Pmwl3I%U;%!Qu@l0lq@UlE2XP^vLavkq;)OZs->m$mnAmrj%QNZGu$)@MKF%mjj7X8>WAQU#q)N|C%`2JbAsWvOyqtoN z7hhMqBYO07#%hUE`%>-q)A1!fyz-WKuBIV-N9RnXKTpSDu>xOL_LbmaNjZmaERBv{o+d zTcvByShf@k@!XX6GN24Qpw+8%@tLSru45@!`&a4Ss1!_o#`P?&WPLw%yN`XSg{<_n zEXp%Iw#2M`taNeIVy3vrX?YwwsMV}=^_eO-u%4x8?PsN%b4AhQb7`Oav6i&b*MZWE z=5I^Z+Sf`~=bEf3MsmU~!#>sOR=PYIHLL1c3fKNtx;s}DPW}(rXaC4P(?VBzUM1FO zF-z>)=Sr97y4WdR(vIbbmb%jK(aJhheM|1z?@G6y6}eL^>^qq+wd$4b52f1Nz%Au# z-z!~z)|5}N3)tZtXUFseP(~p)gdUEACV}-3=W!i_a}ooJkClvc43r@_tI5ckA6Sx; zP2ZOre4}TBG8C4#&UPthrtfqt&S@;<45eeC48?zvp{zM)&s0C?*`W-H<*om!^k=M! z>?a+QJP{K)bLp5UL-L%T7LO!k|OO`eL4oY8b_l%Y8% z8O@rba%OACPU_jC43Xunb5&aRTXcMs;W?)>h%^yP^Tsh+d^oKK`$NwnWth&@?2+5G zW|EGPGDPQmCQ+>7y|c;0_xJxK=F~d&m!4C~fXUiEm&ew;(s5FTDNoER(np-NQsHy{ z`14lwkDge{h@H#H6xg;kxpb_Qp~^Fpi{h3~nqa=q9zDqZ)zeHFyFjU*>%Xn3rsJgy zSDu<`q?Lg6tcQWGroxvn=r64a3}0UKiD$AU=$Hit%lmg;jG1+D=KrFoSBw}v=ado5 zi}9mAS@TZEO&PX4x5!yKvKBkYT z)$t1oodELUyp#JRKatknaOmxeGK{jv^6IgiOUb){dER7OD{sV$9~Hp!67y(+(wn>04Y!`F z%HUc)JD*Bxccf#g4C#3{UrBrU{Bzd-MU^v+f_mC2V|+eMSGlj&)YWlShV{Ihx)fih zclzQ%Me_?YX*>RJSRcvmX%y14SQ&14W}I)w@`X?l9p4KszNAMhTkH5L!+YLlYb)2N zE|iMtxvUJf<+Jm-wC1ypu`Mrl2}l_5XhXLMlytr@Q4 ztqk`CHNz?P@!nZZbKUcPWfh~Wp6kls2hNoX;csic>zFG;e!$oe!enC$C;OS3a?}D7r*SJJaf29soQ|Cg#tQ4SQuMGVKn*u!g z^<3Xm0@!Oh)2;n~N28L?1WGwvD6>A)IIL`-%c?trsX8Yp1#uzG{cvNk@`BcZQU(`AULbvhxPw?-rw64j!cD0Q?KLY! zXe}tEaM7fQ;56a8(^yld38gkJv{aDOc&t>R^`Ml)MU^T%T2bGTY-!Zi8ABzmsy)wx=_l(=O@cw7fWgXE~Gj-YbfP$v8X{cPI*q9Azi*|Lf^kH9R>gz0`l!@i7i@B6nn@p_}trNv+W6ck1)zLap%H*P7 zbu69OSD!{Yt0?7Sc}tg`uh_Bfq&3lc(RvB93R&~TT8*?`lycFlQGkZ*t5P$aWt6h9 zW|uDQ_wudPsfE^!)=fZW2{%`)RZ8ndDI2{?h0v0`T6H&C>8zuaPq>+PvA6} zq;;f}kxoq!q$ZEPJQr@h^yK@fTPK~Nl+p?}EA?yk>}6#sttF+Dbe4)ZOPyj4+eXUv zy$ksX5>FtBTQ2r!b|)!Yu*%wb0uy**8`i(;8DsOsBCZ(->(@JUfg#s`P6rHH`r} zn<=Fx&q{q9S@u%-$;xP2XG)prjFt--jdT|$?vEj>c@o=nV~|d4O2w%rsm9JM!CA>o zYfULNo!oLMxzYTTw{4S+Av(J$C8smlnPsw2ezP*1)|*mpI>Y5+h6~Jc^NnFT%PD0S zYPM?p%(EY5I_qJe%e3ya?s7S^g`1n!Dywy;l$~B>&yp5>?`rimM(UKO)Lyu0t6w|w z<(7PBr9G`ZrSx>#J4kJi|OM}S%!EgY^rg&&VWi8>MR#smdnY1RuVtL8WKYY8sPt235*5r&+FFKf4*$ z%A#7IN_pxmdJeNF&Ha4xQ@&z5Y9t#s>SU@^t4@|@H(5sFUn`+%jVdLo6Y4omsH9=v z^Ksr=qy3DVbVgOmHIf;x&pG>9*UG9|r%IXXteOY1D&+yib~W9&MJHFKYIWi~`-wAB zA6p4lYgH*#onZ4wf+al%Z(pbA46BrFq_bb2_uphoY2M zXzgn4=D{o*E+1IC2CZGCboH(w59>MLGcR}P^sCfxxaqH7`|q|2p?qznV69)Je02)W z!zq|F9rziVuZ(+iCRR#0R0h!axzEB@46JOdHLR4d&c=B>8~ZY{?K3&|>Wr+Evo-5= znRhaos5oj!LCTc4|Yb`6KtP}KklAtNS z1imZX&$wS_Xr-)mHqM*bI8jVrd(b&T0MSu52YDk*3@?UYh5d4t+V!dn6*joitTn?<6)h= zl`0RHAoOc_JF!~{Tx(k?ZJof+(*#a=Cvf|{TK|TwTI5>g|AETcDOSmttG5tJ3F>Xa z+21B89UlUucvxElty#5`v}W_3W@E+gpW+vyq2I2?qdMCvrK^>j_mnGVT&-KBZ1pzv zzu2a#U9Uu~JQ8PRUC&PoRW#=7#2eOOmg97p`-xcT_z??ho`?@8c zp3Z-A4C18(oGdoK&lwAJ4pzET_M1M=TRNtASb13MS1Dh;3C^RNU@MnMxtKnfir$Vj z7V2EA6tm?sU7nphOnyC`|5S0Hd~AL1+aj%Fr8`xA(^&3mTIu)@U?|^Pdkd{&wc|qh zP2;(zWwqzkXehr2d>`CXIxQ>x7s`Da&s%b)cvz`fYgs8}ec6}CFZ<-268JrF$Bd;q zLn~!1drcqbURIWUsdRh@P_Cyswz9O=v)X|wpJ^<2b*=Wi8qLY~fsY8+G?wX1t#oBh zp46{LuX3g1Lx7R^+sf8j(`qM1;zNB-bh=i1UX4cLYsDw?l8t9{(pGvj5{K$@@|M6U z9#-Pkx>m|s-wZjAZidMDC2+gl&sd=|w^HJ=*Yt6889J2zl#UMphT>4+R`%A~Ry$MW zGmYi0#?_uzqo?D0#r8YhSf!J=(zB=ISbgr9O#r3iLx892V=IwseXAXMy8hJXpT5S` zo>!x%>)+t*`13lGD_wiKp4I2)Eu~XDtZc3|u9UdGsdAp)RFQLyVtZc4cu^;HrQ&7B z>EqK+*pc{5>G%*}Bz&rKti-N$u6C@-XBx|0y{kR1M$gpuf!p=H#%i6}l`cM059@l7 z&kCjELx9ovm9o3_`LnfJ?@A9x<6m7jGR-R;9|DZlr`C=}>s{^OX#K0}=d5|P=hbMm z{tWm$Tb54qN0j-6HJV#~54?q0)7YdlztZKo z<#Ejudd4Un9|FuxKU&#eYhUf`-1N2PQtMysc{Q4wK2$uRkZioH7XhW`bJOvfD{oB% ziifojX#FeYuW$ZbfH!~SJQR32(9hVaR|4f!kiDjl)tNk6zbG9a0*tmTReftU&~rfT zbd}FEmb-I7?RhnNHhizRJg8%A*NcKO0%s!tn$td^l#UMpo-N;53xl2qYR8`~ziVFq zTu^&njh-#P1z#@g)GLEB1ZOJ(nm2FF2#SZbI_SBeoC^9T(gl7KNzO@%%ZIwgZoNn- zXNK%Jee6%{x#HY&CibH?^%m&Xo7c@-NSI|1dLY)o7xbH;UMhMXR{03j&d%WQ{Xj}huDMeB<6INWe>S~pd7^>aig#9Rcx;NGnBuw zdC8TTGr2B%H2EI(Sn?tEc)`wWL7_TqVWCEBQIU~sanX<1Q^k6+CB@!gON-yjo-R>^ zEi2WFJyU8qd$!bHY(?qLY-Q<1Y*p!#Y<0OC*_!fCv$f^_X6q_+VOf{_#@1K7ifyPo ziEXTMC)-pto^7r=mAzc`INO?9lx<6G!?vf+W;;^1v7OZluwB(=u-(;LvOU$a*(){H zvsY_g%U-Lwh`nBOFMFfrzsy-Hmc3Q09?JIY?OL~>e1N@EYbVNmY+voI?0;!7?A^3B z?EQ2X+h3Q ztIdpNVl>k=W z`4+H}z{IAF|uu86az{&!v=(-Hv%gUta5?@tOBr9 z*SEkf0ai7k6|joHswdP0RtZ?OgsXv7239knKd>smY9zb>tSYeD36B9w1y(EJAh2q{ zE=|}CtU9nX^xTnH16Uozr(9x9VCjjifz<+5FR>P|+Q8~2&H|POtbXDRz%B)rk@y<0 zbYPi@tAW)4)*vYsSY2R^62Avl4_L#bCcrX)HA$)htUj>DNt1y!0M;yN1h7nCO_SCF zYY41G(n4U3fHhD023TWYt&-jc)&y9~`~`tE1=c3%A7IUZwRTSj)*M(n_m#j}0Bh@h z9au|X9o%bxwF1^Y*$u2Uuuks3fVBbEF}V-0w!pe1Hv`rVSm)$tfwc$LE%_l}9e{OB zJ^`#FupY^Wfpr4bz2InIoq_c#*d16GU_A>y0IVypJ_RQO>jtcM!S%qp1M63CF|Z!M z`lh4<>j`W?N-1Eyfb~xq2&^}-K`E_)^#L|8u(`k zdB7Hy&jR)+uqP_q2<$Oniz-|OY(B6jE7Eu$2liA&8t(#Niz{(pPXJq5DHhm5U`r}> z0QMxXWtHjxTLkRs%Cmtj2KG$ln}9t9YaF|?71rM0ecqMi&eG&TLJ8as%3z!1h%@W6WA(XFIDXf>^Wd-t7ZUu z9@v_yj{$oDSXR~BfxQT9T`JA?bUk$+XQS|4Vnv^f$gk8bKzxRJ8FCiYzwg6 zHC_X@71*v?loPiBd!-iT#O=WL)GiEc2e8*_odUKK*sHav&%1!VQJea_8`$f$KL)l3 z*ju$<0rm>8H`B@jdllF_X)a)|0ed@b7_irY?Mv$b>~Gc1NI)UgXx8Vy$|f8 zbjln1fqk4#dE)@EL+O-($VBgd$ z0qjd)U)LK1>?pAB>a_uO4A{5zo&ok1upjC@2<$kp@9P}^_BF7d>TL)14X__GXl{KA z?3WChTi*fuIink}?}7c6kqPVvV83S2IDQ0nGK0qP6R;B*G=F~v_D2TI-(P_JUZ2MC zE3m)n(>Q(u_Gg1;z)k@Br$H*PlfeFNa0uA%!2WHp2iPCLvNP+k#Kb=xDF(|d%PJ=R z1?*HqC$PVP#bkcZswMuzY8ytw9>B7J#Wk!4>|bE94etha3Ru2|<5;yM1}wheCoD0^ z0On}816T|&vr$1{vA|pnPXdbr=4>GI%nht?lUBfz zffZ{~1z15~MVovKECpEcCfk7(0>+!td4++MY)a=90al{vQeZ`am2P?uuwuYUHT?(} z2UfP}7GTAJm1$NNSP5X|n{i+zft73a7_d^nE@^fvu+qRPH2WD?8DN!~?FUvCSjFbu zft3SRrFmUo<$+aheiyI`z*3u!1$GIrs?Co8s|c)m^H+dX0#>a>8(@`z)ohUptO~Fi zE#?BN3aoaEn}DSPtJUI7VAX(K+TsOZ)q$n8EC;LxusSW{fzDgmq>u!gO!1eO7;Nvm$a z>H}-sYA3J;z?!vM1}qa;(^kI&YY41Gt3$vV0c+m6H?YRQTD5KftO>A|t(OC93am}* znZTL>Yu%dk(i~X3)})sfz}mJ+1lAH*ht@v(=HiU>$&UZ95cLM_@hLwglD*SogNi0qYE`SKB$jx&Z6h_As!n z!1}b^1*{ve-t7tj>kh16+dqKy0M@r%S71GX4QQ7RtQWBU?LGz88`z+BJAw59Hn9Cj zV10oNY2OZ5KVXA9kjDE18`hpQJ^GJJ8%30&GOb z8o-7EyS!sEuwlSPb$kfeaA0FP-T>?}V52)t1~vlN*iM6ijRbZ@=c>R)0lTtu60pmG zjqAJ!*l1u^b-n}G7+~W&e*o+XVApis3~Vg0tGiG>7zb=ZXUYdx0=u?rJh1V=uJ7_S zu&aPw*R>h2tAS1GdI_*=fKBW+1lYB}ZtT_q*aToVblU~&I$$?-TMq1cV3T{q0-Ffz zmhN8xn*{9U9+Y!#05+uu<(wOV-P-e6V3UE})^irHn}AL2btkZ!flcpq1+ZIyP3!eC zuv>xM(Q6T~DZp;;MLL}d?5h;U~_;yI&eL(2Z7BSM81Cr*!+Ry z`-g!&HfS5LM}RFDv;^2(V2=;RT9Gsl*uufZfjtWBiNWK6JqB#i;O@ZY1AB7tGr%4P z_SE3}fGq&Fc*x_xo&dIV$W&kpfh`$w0N9hjmJQhiY!R@hhyDg^F|cQbehBO-V9ST~ z2et&*ieZg`Ed}=MaLT7o16wtm^64^QD~JCJY&o#!haUm<46x@$GzIo7uop*E0JZ|y z3nNPaTM2CSh*Q8;0efj=4`9y$TRXBIu;+oT8958s3&65QUJL9+VCzOr1NIWI4WmW@ zTMcaeDAL9nV4FsfHr4{$csb>vb--S}obpf>u+5{XFYAGA9Zh}N0Bp;c+kkBZwtdV< zV4Hw#8*>!cW?(zVybkPTU^~WE2DSy*?y(8LwgTJ5*f?k0gt+S%bGwpuB<*Ad?jkal z!VLV6F*9{j(wmIEh(pHmCA|yV0XI|gGdD{{nZgQ-o36!Ba{OI_m13oFgiRnT2Z9PH zFF{!eWo49AQKq7-F8Gp@-a{FKn?~=WOaSh}zl7`1%l*KwXQho~W*9DKMdpCz&f?Az z&XUg3_*dMEO>|E3VUxVrbOkm;fz4K6^Ay-W!IjJadeg#%Yfpt<~y%g9>uGQ9f zaU}fW+N8jCD(b$Wz`j#pClpwAFqV*@z_;;{bCtnQO>gOJ)L@ z>&RSBW+ItMWNsjHBbmu$ZX$CtnOn%*N@fa~sbp>=GmXr2GPjetgUp>|?jmzHnS030 zAagI7nPl!GGmFgqWF8|WPT>|3z=WZ{6^*knUiFG zhlyK20sVvi{FBUIWd0`e51DK-|B^WcV=yuXnHVy$Wa7xg!>|!#+L}cf>qVw3nKopG zkZDe)72bY}n;SQe#oZKlGmE=B?j9EReB4qNw>oYOi(5iRD`41AoE&!~?hD2SP_;T{ zNyb{xQ5u^ndxM1CvyjxJIUNd=58|gkeNZ| zUNSSu+(%{>nfu8+KxQ_XIbWd6LW` zGK<^rDUEavy9AgGS85Cmdpw=E6J=P^BkGy$-F@3MKUjuSxsgQnYCork;x*n zp3DX^8_8@Xvx&@RGB1ncZaeka>m7t7Kjy^E#O~$h=ABEi!MD zd56qiGW*EBTIY#CyGRMh$P39Xi-;()`%=ct|AoC-cpUC`7<`*)*lKG9y2{I?i{7&W%GJlf! zi_G6-{vnf1=3g?WU`$5FAQM9-mP{O(cry9Om}DGeoMc>N638TyNg|Vd7aE#Fve&)+DqnrG9QpRNahnVpON{3%rP=wllczDz?-Tp z=0`HWkU2r-4>Es~`4=YEAQMN%B;$fHuBD?SGHx;{WQvgCWJ;1LL#8~Lieyq@j7fA< zgA8tjvDkDn^~hjX!eX0{X-=jUnf7G5z!;P1s5_ZnWcrdBKxQZza#-vrGGoY$BXbpu zF@=sqPp_w=8_3*5W-6KKWUwJ&vGSPD-pg~!Mwb07Ulfr_O-#ZjQ*@{w_pNhDK%OhGb*$rOVz9-yNVWJ;4MN9GbT zmB~~mQ;W={Wa^Ts4`Vz`M-9m|Awz+Rqd>*ACDVaSXENQ$^d!><#+XM({mBd>Lm`W! zki}8R;wWUs0y0mMd5X-_WLA)Qj!aWBtI1@M*-U0DnH^+ylX;cQ8)V)g^DY_cnsI>4 zK{B6`IYQX^Z#FKH6Ay38>BE!j$#$(8JG2}XfbQ(kc zi%BI@gA8drhBO{ik4ytHjmXf5Vp_l$gm>Fb9D#l