IFC

el2_ifu_bp_ctl.fir

@@ -536,4 +536,75 @@ circuit el2_ifu_bp_ctl :
     node _T_372 = or(_T_371, _T_370) @[Mux.scala 27:72]
     wire adder_pc_in_f : UInt @[Mux.scala 27:72]
     adder_pc_in_f <= _T_372 @[Mux.scala 27:72]
+    node _T_373 = bits(adder_pc_in_f, 31, 2) @[el2_ifu_bp_ctl.scala 303:58]
+    node _T_374 = cat(_T_373, bp_total_branch_offset_f) @[Cat.scala 29:58]
+    node _T_375 = cat(_T_374, UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_376 = cat(btb_rd_tgt_f, UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_377 = bits(_T_375, 12, 1) @[el2_lib.scala 199:28]
+    node _T_378 = bits(_T_376, 12, 1) @[el2_lib.scala 199:44]
+    node _T_379 = add(_T_377, _T_378) @[el2_lib.scala 199:35]
+    node _T_380 = cat(_T_379, UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_381 = bits(_T_375, 31, 13) @[el2_lib.scala 200:20]
+    node _T_382 = add(_T_381, UInt<1>("h01")) @[el2_lib.scala 200:27]
+    node _T_383 = tail(_T_382, 1) @[el2_lib.scala 200:27]
+    node _T_384 = bits(_T_375, 31, 13) @[el2_lib.scala 201:20]
+    node _T_385 = add(_T_384, UInt<1>("h01")) @[el2_lib.scala 201:27]
+    node _T_386 = tail(_T_385, 1) @[el2_lib.scala 201:27]
+    node _T_387 = bits(_T_376, 12, 12) @[el2_lib.scala 202:22]
+    node _T_388 = bits(_T_380, 13, 13) @[el2_lib.scala 203:38]
+    node _T_389 = eq(_T_388, UInt<1>("h00")) @[el2_lib.scala 203:27]
+    node _T_390 = xor(_T_387, _T_389) @[el2_lib.scala 203:25]
+    node _T_391 = bits(_T_390, 0, 0) @[el2_lib.scala 203:63]
+    node _T_392 = bits(_T_375, 31, 13) @[el2_lib.scala 203:75]
+    node _T_393 = eq(_T_387, UInt<1>("h00")) @[el2_lib.scala 204:8]
+    node _T_394 = bits(_T_380, 13, 13) @[el2_lib.scala 204:26]
+    node _T_395 = and(_T_393, _T_394) @[el2_lib.scala 204:14]
+    node _T_396 = bits(_T_395, 0, 0) @[el2_lib.scala 204:51]
+    node _T_397 = bits(_T_375, 31, 13) @[el2_lib.scala 204:64]
+    node _T_398 = add(_T_397, UInt<1>("h01")) @[el2_lib.scala 204:71]
+    node _T_399 = tail(_T_398, 1) @[el2_lib.scala 204:71]
+    node _T_400 = bits(_T_380, 13, 13) @[el2_lib.scala 205:26]
+    node _T_401 = eq(_T_400, UInt<1>("h00")) @[el2_lib.scala 205:15]
+    node _T_402 = and(_T_387, _T_401) @[el2_lib.scala 205:13]
+    node _T_403 = bits(_T_402, 0, 0) @[el2_lib.scala 205:51]
+    node _T_404 = bits(_T_375, 31, 13) @[el2_lib.scala 205:64]
+    node _T_405 = sub(_T_404, UInt<1>("h01")) @[el2_lib.scala 205:71]
+    node _T_406 = tail(_T_405, 1) @[el2_lib.scala 205:71]
+    node _T_407 = mux(_T_391, _T_392, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_408 = mux(_T_396, _T_399, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_409 = mux(_T_403, _T_406, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_410 = or(_T_407, _T_408) @[Mux.scala 27:72]
+    node _T_411 = or(_T_410, _T_409) @[Mux.scala 27:72]
+    wire _T_412 : UInt<19> @[Mux.scala 27:72]
+    _T_412 <= _T_411 @[Mux.scala 27:72]
+    node _T_413 = bits(_T_380, 11, 1) @[el2_lib.scala 205:91]
+    node _T_414 = cat(_T_412, _T_413) @[Cat.scala 29:58]
+    node bp_btb_target_adder_f = cat(_T_414, UInt<1>("h00")) @[Cat.scala 29:58]
+    wire rets_out : UInt<32>[8] @[el2_ifu_bp_ctl.scala 305:22]
+    rets_out[0] <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 306:12]
+    rets_out[1] <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 306:12]
+    rets_out[2] <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 306:12]
+    rets_out[3] <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 306:12]
+    rets_out[4] <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 306:12]
+    rets_out[5] <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 306:12]
+    rets_out[6] <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 306:12]
+    rets_out[7] <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 306:12]
+    node _T_415 = not(btb_rd_call_f) @[el2_ifu_bp_ctl.scala 307:49]
+    node _T_416 = and(btb_rd_ret_f, _T_415) @[el2_ifu_bp_ctl.scala 307:47]
+    node _T_417 = bits(rets_out[0], 0, 0) @[el2_ifu_bp_ctl.scala 307:77]
+    node _T_418 = and(_T_416, _T_417) @[el2_ifu_bp_ctl.scala 307:64]
+    node _T_419 = bits(_T_418, 0, 0) @[el2_ifu_bp_ctl.scala 307:82]
+    node _T_420 = bits(rets_out[0], 31, 1) @[el2_ifu_bp_ctl.scala 308:16]
+    node _T_421 = bits(bp_btb_target_adder_f, 31, 1) @[el2_ifu_bp_ctl.scala 308:44]
+    node _T_422 = mux(_T_419, _T_420, _T_421) @[el2_ifu_bp_ctl.scala 307:32]
+    io.ifu_bp_btb_target_f <= _T_422 @[el2_ifu_bp_ctl.scala 307:26]
+    node _T_423 = not(btb_rd_ret_f) @[el2_ifu_bp_ctl.scala 312:33]
+    node _T_424 = and(btb_rd_call_f, _T_423) @[el2_ifu_bp_ctl.scala 312:31]
+    node rs_push = and(_T_424, ifu_bp_hit_taken_f) @[el2_ifu_bp_ctl.scala 312:47]
+    node _T_425 = not(btb_rd_call_f) @[el2_ifu_bp_ctl.scala 313:31]
+    node _T_426 = and(btb_rd_ret_f, _T_425) @[el2_ifu_bp_ctl.scala 313:29]
+    node rs_pop = and(_T_426, ifu_bp_hit_taken_f) @[el2_ifu_bp_ctl.scala 313:46]
+    node _T_427 = not(rs_push) @[el2_ifu_bp_ctl.scala 314:17]
+    node _T_428 = not(rs_pop) @[el2_ifu_bp_ctl.scala 314:28]
+    node rs_hold = and(_T_427, _T_428) @[el2_ifu_bp_ctl.scala 314:26]
     

src/main/scala/ifu/el2_ifu_bp_ctl.scala

@@ -300,10 +300,20 @@ class el2_ifu_bp_ctl extends Module with el2_lib {
     btb_fg_crossing_f.asBool->ifc_fetch_adder_prior,
     (!btb_fg_crossing_f & !use_fa_plus).asBool->io.ifc_fetch_addr_f(31,2)))
 
-  val bp_btb_target_adder_f = rvbradder(Cat(adder_pc_in_f(31,2),bp_total_branch_offset_f, 0.U), btb_rd_tgt_f)
+  val bp_btb_target_adder_f = rvbradder(Cat(adder_pc_in_f(31,2),bp_total_branch_offset_f, 0.U), Cat(btb_rd_tgt_f,0.U))
+//
+  val rets_out = Wire(Vec(RET_STACK_SIZE, UInt(32.W)))
+  rets_out := (0 until RET_STACK_SIZE).map(i=>0.U)
+  io.ifu_bp_btb_target_f := Mux((btb_rd_ret_f & ~btb_rd_call_f & rets_out(0)(0)).asBool,
+    rets_out(0)(31,1),bp_btb_target_adder_f(31,1))
 
+  //val bp_rs_call_target_f = rvbradder(Cat(adder_pc_in_f(31,2),bp_total_branch_offset_f, 0.U), Cat(Fill(11, 0.U),~btb_rd_pc4_f, 0.U))
 
+  val rs_push = btb_rd_call_f & ~btb_rd_ret_f & ifu_bp_hit_taken_f
+  val rs_pop = btb_rd_ret_f & ~btb_rd_call_f & ifu_bp_hit_taken_f
+  val rs_hold = ~rs_push & ~rs_pop
 
+// Return stack
 
 }
 

src/main/scala/lib/el2_lib.scala

@@ -196,13 +196,13 @@ trait el2_lib extends param{
     data_in.xorR.asUInt
 
   def rvbradder (pc:UInt, offset:UInt) = {
-    val dout_lower = pc(12,1) +& offset(12,1)
+    val dout_lower = Cat(pc(12,1) +& offset(12,1), 0.U)
     val pc_inc = pc(31,13)+1.U
     val pc_dec = pc(31,13)+1.U
-    val sign = offset(offset.getWidth-1)
+    val sign = offset(12)
     Cat(Mux1H(Seq((sign ^ !dout_lower(dout_lower.getWidth-1)).asBool -> pc(31,13),
       (!sign & dout_lower(dout_lower.getWidth-1)).asBool -> (pc(31,13)+1.U),
-      (sign & !dout_lower(dout_lower.getWidth-1)).asBool -> (pc(31,13)-1.U))) , dout_lower(12,1), 0.U)
+      (sign & !dout_lower(dout_lower.getWidth-1)).asBool -> (pc(31,13)-1.U))) , dout_lower(11,1), 0.U)
   }
 
   // RV range