Quasar top done
This commit is contained in:
waleed-lm
parent
b06de8c2a3
commit
8f0104e35b
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@ -1 +1,3 @@
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/home/waleedbinehsan/Desktop/Quasar/gated_latch.v
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/home/waleedbinehsan/Desktop/Quasar/gated_latch.v
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/home/waleedbinehsan/Desktop/Quasar/dmi_wrapper.sv
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/home/waleedbinehsan/Desktop/Quasar/mem.sv
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@ -114830,305 +114830,297 @@ circuit quasar_wrapper :
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inst swerv of quasar @[quasar_wrapper.scala 65:21]
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swerv.clock <= clock
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swerv.reset <= reset
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dmi_wrapper.trst_n <= io.jtag_trst_n @[quasar_wrapper.scala 66:25]
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dmi_wrapper.tck <= io.jtag_tck @[quasar_wrapper.scala 67:22]
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dmi_wrapper.tms <= io.jtag_tms @[quasar_wrapper.scala 68:22]
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dmi_wrapper.tdi <= io.jtag_tdi @[quasar_wrapper.scala 69:22]
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dmi_wrapper.core_clk <= clock @[quasar_wrapper.scala 70:27]
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dmi_wrapper.jtag_id <= io.jtag_id @[quasar_wrapper.scala 71:26]
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dmi_wrapper.rd_data <= swerv.io.dmi_reg_rdata @[quasar_wrapper.scala 72:26]
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dmi_wrapper.core_rst_n <= io.dbg_rst_l @[quasar_wrapper.scala 75:29]
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swerv.io.dmi_reg_wdata <= dmi_wrapper.reg_wr_data @[quasar_wrapper.scala 76:26]
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swerv.io.dmi_reg_addr <= dmi_wrapper.reg_wr_addr @[quasar_wrapper.scala 77:25]
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swerv.io.dmi_reg_en <= dmi_wrapper.reg_en @[quasar_wrapper.scala 78:23]
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swerv.io.dmi_reg_wr_en <= dmi_wrapper.reg_wr_en @[quasar_wrapper.scala 79:26]
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swerv.io.dmi_hard_reset <= dmi_wrapper.dmi_hard_reset @[quasar_wrapper.scala 80:27]
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io.jtag_tdo <= dmi_wrapper.tdo @[quasar_wrapper.scala 81:15]
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mem.dccm_clk_override <= swerv.io.dccm_clk_override @[quasar_wrapper.scala 84:28]
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mem.icm_clk_override <= swerv.io.icm_clk_override @[quasar_wrapper.scala 85:27]
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mem.dec_tlu_core_ecc_disable <= swerv.io.dec_tlu_core_ecc_disable @[quasar_wrapper.scala 86:35]
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swerv.io.dccm.rd_data_hi <= mem.dccm.rd_data_hi @[quasar_wrapper.scala 87:15]
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swerv.io.dccm.rd_data_lo <= mem.dccm.rd_data_lo @[quasar_wrapper.scala 87:15]
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mem.dccm.wr_data_hi <= swerv.io.dccm.wr_data_hi @[quasar_wrapper.scala 87:15]
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mem.dccm.wr_data_lo <= swerv.io.dccm.wr_data_lo @[quasar_wrapper.scala 87:15]
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mem.dccm.rd_addr_hi <= swerv.io.dccm.rd_addr_hi @[quasar_wrapper.scala 87:15]
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mem.dccm.rd_addr_lo <= swerv.io.dccm.rd_addr_lo @[quasar_wrapper.scala 87:15]
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mem.dccm.wr_addr_hi <= swerv.io.dccm.wr_addr_hi @[quasar_wrapper.scala 87:15]
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mem.dccm.wr_addr_lo <= swerv.io.dccm.wr_addr_lo @[quasar_wrapper.scala 87:15]
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mem.dccm.rden <= swerv.io.dccm.rden @[quasar_wrapper.scala 87:15]
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mem.dccm.wren <= swerv.io.dccm.wren @[quasar_wrapper.scala 87:15]
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mem.rst_l <= reset @[quasar_wrapper.scala 88:16]
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mem.clk <= clock @[quasar_wrapper.scala 89:14]
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mem.scan_mode <= io.scan_mode @[quasar_wrapper.scala 90:20]
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swerv.io.dbg_rst_l <= io.dbg_rst_l @[quasar_wrapper.scala 92:22]
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mem.ic.sel_premux_data <= swerv.io.ic.sel_premux_data @[quasar_wrapper.scala 93:15]
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mem.ic.premux_data <= swerv.io.ic.premux_data @[quasar_wrapper.scala 93:15]
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mem.ic.debug_way <= swerv.io.ic.debug_way @[quasar_wrapper.scala 93:15]
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mem.ic.debug_tag_array <= swerv.io.ic.debug_tag_array @[quasar_wrapper.scala 93:15]
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mem.ic.debug_wr_en <= swerv.io.ic.debug_wr_en @[quasar_wrapper.scala 93:15]
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mem.ic.debug_rd_en <= swerv.io.ic.debug_rd_en @[quasar_wrapper.scala 93:15]
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swerv.io.ic.tag_perr <= mem.ic.tag_perr @[quasar_wrapper.scala 93:15]
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swerv.io.ic.rd_hit <= mem.ic.rd_hit @[quasar_wrapper.scala 93:15]
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swerv.io.ic.parerr <= mem.ic.parerr @[quasar_wrapper.scala 93:15]
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swerv.io.ic.eccerr <= mem.ic.eccerr @[quasar_wrapper.scala 93:15]
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swerv.io.ic.tag_debug_rd_data <= mem.ic.tag_debug_rd_data @[quasar_wrapper.scala 93:15]
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swerv.io.ic.debug_rd_data <= mem.ic.debug_rd_data @[quasar_wrapper.scala 93:15]
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swerv.io.ic.rd_data <= mem.ic.rd_data @[quasar_wrapper.scala 93:15]
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mem.ic.debug_addr <= swerv.io.ic.debug_addr @[quasar_wrapper.scala 93:15]
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mem.ic.debug_wr_data <= swerv.io.ic.debug_wr_data @[quasar_wrapper.scala 93:15]
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mem.ic.wr_data[0] <= swerv.io.ic.wr_data[0] @[quasar_wrapper.scala 93:15]
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mem.ic.wr_data[1] <= swerv.io.ic.wr_data[1] @[quasar_wrapper.scala 93:15]
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mem.ic.rd_en <= swerv.io.ic.rd_en @[quasar_wrapper.scala 93:15]
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mem.ic.wr_en <= swerv.io.ic.wr_en @[quasar_wrapper.scala 93:15]
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mem.ic.tag_valid <= swerv.io.ic.tag_valid @[quasar_wrapper.scala 93:15]
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mem.ic.rw_addr <= swerv.io.ic.rw_addr @[quasar_wrapper.scala 93:15]
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swerv.io.iccm.rd_data_ecc <= mem.iccm.rd_data_ecc @[quasar_wrapper.scala 94:17]
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swerv.io.iccm.rd_data <= mem.iccm.rd_data @[quasar_wrapper.scala 94:17]
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mem.iccm.wr_data <= swerv.io.iccm.wr_data @[quasar_wrapper.scala 94:17]
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mem.iccm.wr_size <= swerv.io.iccm.wr_size @[quasar_wrapper.scala 94:17]
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mem.iccm.rden <= swerv.io.iccm.rden @[quasar_wrapper.scala 94:17]
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mem.iccm.wren <= swerv.io.iccm.wren @[quasar_wrapper.scala 94:17]
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mem.iccm.correction_state <= swerv.io.iccm.correction_state @[quasar_wrapper.scala 94:17]
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mem.iccm.buf_correct_ecc <= swerv.io.iccm.buf_correct_ecc @[quasar_wrapper.scala 94:17]
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mem.iccm.rw_addr <= swerv.io.iccm.rw_addr @[quasar_wrapper.scala 94:17]
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wire _T : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>} @[quasar_wrapper.scala 96:39]
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_T.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 96:39]
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_T.hready <= UInt<1>("h00") @[quasar_wrapper.scala 96:39]
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_T.hrdata <= UInt<64>("h00") @[quasar_wrapper.scala 96:39]
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swerv.io.ahb.in.hresp <= _T.hresp @[quasar_wrapper.scala 96:24]
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swerv.io.ahb.in.hready <= _T.hready @[quasar_wrapper.scala 96:24]
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swerv.io.ahb.in.hrdata <= _T.hrdata @[quasar_wrapper.scala 96:24]
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wire _T_1 : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>} @[quasar_wrapper.scala 97:39]
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_T_1.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 97:39]
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_T_1.hready <= UInt<1>("h00") @[quasar_wrapper.scala 97:39]
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_T_1.hrdata <= UInt<64>("h00") @[quasar_wrapper.scala 97:39]
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swerv.io.lsu_ahb.in.hresp <= _T_1.hresp @[quasar_wrapper.scala 97:24]
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swerv.io.lsu_ahb.in.hready <= _T_1.hready @[quasar_wrapper.scala 97:24]
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swerv.io.lsu_ahb.in.hrdata <= _T_1.hrdata @[quasar_wrapper.scala 97:24]
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wire _T_2 : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>} @[quasar_wrapper.scala 98:39]
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_T_2.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 98:39]
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_T_2.hready <= UInt<1>("h00") @[quasar_wrapper.scala 98:39]
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_T_2.hrdata <= UInt<64>("h00") @[quasar_wrapper.scala 98:39]
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swerv.io.sb_ahb.in.hresp <= _T_2.hresp @[quasar_wrapper.scala 98:24]
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swerv.io.sb_ahb.in.hready <= _T_2.hready @[quasar_wrapper.scala 98:24]
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swerv.io.sb_ahb.in.hrdata <= _T_2.hrdata @[quasar_wrapper.scala 98:24]
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wire _T_3 : {flip ahb : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, flip hsel : UInt<1>, flip hreadyin : UInt<1>} @[quasar_wrapper.scala 99:33]
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_T_3.hreadyin <= UInt<1>("h00") @[quasar_wrapper.scala 99:33]
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_T_3.hsel <= UInt<1>("h00") @[quasar_wrapper.scala 99:33]
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_T_3.ahb.out.hwdata <= UInt<64>("h00") @[quasar_wrapper.scala 99:33]
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_T_3.ahb.out.hwrite <= UInt<1>("h00") @[quasar_wrapper.scala 99:33]
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_T_3.ahb.out.htrans <= UInt<2>("h00") @[quasar_wrapper.scala 99:33]
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_T_3.ahb.out.hsize <= UInt<3>("h00") @[quasar_wrapper.scala 99:33]
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_T_3.ahb.out.hprot <= UInt<4>("h00") @[quasar_wrapper.scala 99:33]
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_T_3.ahb.out.hmastlock <= UInt<1>("h00") @[quasar_wrapper.scala 99:33]
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_T_3.ahb.out.hburst <= UInt<3>("h00") @[quasar_wrapper.scala 99:33]
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_T_3.ahb.out.haddr <= UInt<32>("h00") @[quasar_wrapper.scala 99:33]
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_T_3.ahb.in.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 99:33]
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_T_3.ahb.in.hready <= UInt<1>("h00") @[quasar_wrapper.scala 99:33]
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_T_3.ahb.in.hrdata <= UInt<64>("h00") @[quasar_wrapper.scala 99:33]
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swerv.io.dma.hreadyin <= _T_3.hreadyin @[quasar_wrapper.scala 99:18]
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swerv.io.dma.hsel <= _T_3.hsel @[quasar_wrapper.scala 99:18]
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swerv.io.dma.ahb.out.hwdata <= _T_3.ahb.out.hwdata @[quasar_wrapper.scala 99:18]
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swerv.io.dma.ahb.out.hwrite <= _T_3.ahb.out.hwrite @[quasar_wrapper.scala 99:18]
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swerv.io.dma.ahb.out.htrans <= _T_3.ahb.out.htrans @[quasar_wrapper.scala 99:18]
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swerv.io.dma.ahb.out.hsize <= _T_3.ahb.out.hsize @[quasar_wrapper.scala 99:18]
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swerv.io.dma.ahb.out.hprot <= _T_3.ahb.out.hprot @[quasar_wrapper.scala 99:18]
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swerv.io.dma.ahb.out.hmastlock <= _T_3.ahb.out.hmastlock @[quasar_wrapper.scala 99:18]
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swerv.io.dma.ahb.out.hburst <= _T_3.ahb.out.hburst @[quasar_wrapper.scala 99:18]
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swerv.io.dma.ahb.out.haddr <= _T_3.ahb.out.haddr @[quasar_wrapper.scala 99:18]
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_T_3.ahb.in.hresp <= swerv.io.dma.ahb.in.hresp @[quasar_wrapper.scala 99:18]
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_T_3.ahb.in.hready <= swerv.io.dma.ahb.in.hready @[quasar_wrapper.scala 99:18]
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_T_3.ahb.in.hrdata <= swerv.io.dma.ahb.in.hrdata @[quasar_wrapper.scala 99:18]
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swerv.io.scan_mode <= io.scan_mode @[quasar_wrapper.scala 110:22]
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swerv.io.dbg_rst_l <= io.dbg_rst_l @[quasar_wrapper.scala 112:22]
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swerv.io.rst_vec <= io.rst_vec @[quasar_wrapper.scala 113:20]
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swerv.io.nmi_int <= io.nmi_int @[quasar_wrapper.scala 114:20]
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swerv.io.nmi_vec <= io.nmi_vec @[quasar_wrapper.scala 115:20]
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swerv.io.i_cpu_halt_req <= io.i_cpu_halt_req @[quasar_wrapper.scala 118:27]
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swerv.io.i_cpu_run_req <= io.i_cpu_run_req @[quasar_wrapper.scala 119:26]
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swerv.io.core_id <= io.core_id @[quasar_wrapper.scala 120:20]
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swerv.io.mpc_debug_halt_req <= io.mpc_debug_halt_req @[quasar_wrapper.scala 123:31]
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swerv.io.mpc_debug_run_req <= io.mpc_debug_run_req @[quasar_wrapper.scala 124:30]
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swerv.io.mpc_reset_run_req <= io.mpc_reset_run_req @[quasar_wrapper.scala 125:30]
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swerv.io.lsu_axi.r.bits.last <= io.lsu_brg.r.bits.last @[quasar_wrapper.scala 129:20]
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swerv.io.lsu_axi.r.bits.resp <= io.lsu_brg.r.bits.resp @[quasar_wrapper.scala 129:20]
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swerv.io.lsu_axi.r.bits.data <= io.lsu_brg.r.bits.data @[quasar_wrapper.scala 129:20]
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swerv.io.lsu_axi.r.bits.id <= io.lsu_brg.r.bits.id @[quasar_wrapper.scala 129:20]
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swerv.io.lsu_axi.r.valid <= io.lsu_brg.r.valid @[quasar_wrapper.scala 129:20]
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io.lsu_brg.r.ready <= swerv.io.lsu_axi.r.ready @[quasar_wrapper.scala 129:20]
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io.lsu_brg.ar.bits.qos <= swerv.io.lsu_axi.ar.bits.qos @[quasar_wrapper.scala 129:20]
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io.lsu_brg.ar.bits.prot <= swerv.io.lsu_axi.ar.bits.prot @[quasar_wrapper.scala 129:20]
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io.lsu_brg.ar.bits.cache <= swerv.io.lsu_axi.ar.bits.cache @[quasar_wrapper.scala 129:20]
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io.lsu_brg.ar.bits.lock <= swerv.io.lsu_axi.ar.bits.lock @[quasar_wrapper.scala 129:20]
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io.lsu_brg.ar.bits.burst <= swerv.io.lsu_axi.ar.bits.burst @[quasar_wrapper.scala 129:20]
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io.lsu_brg.ar.bits.size <= swerv.io.lsu_axi.ar.bits.size @[quasar_wrapper.scala 129:20]
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io.lsu_brg.ar.bits.len <= swerv.io.lsu_axi.ar.bits.len @[quasar_wrapper.scala 129:20]
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io.lsu_brg.ar.bits.region <= swerv.io.lsu_axi.ar.bits.region @[quasar_wrapper.scala 129:20]
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io.lsu_brg.ar.bits.addr <= swerv.io.lsu_axi.ar.bits.addr @[quasar_wrapper.scala 129:20]
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io.lsu_brg.ar.bits.id <= swerv.io.lsu_axi.ar.bits.id @[quasar_wrapper.scala 129:20]
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io.lsu_brg.ar.valid <= swerv.io.lsu_axi.ar.valid @[quasar_wrapper.scala 129:20]
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swerv.io.lsu_axi.ar.ready <= io.lsu_brg.ar.ready @[quasar_wrapper.scala 129:20]
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swerv.io.lsu_axi.b.bits.id <= io.lsu_brg.b.bits.id @[quasar_wrapper.scala 129:20]
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swerv.io.lsu_axi.b.bits.resp <= io.lsu_brg.b.bits.resp @[quasar_wrapper.scala 129:20]
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swerv.io.lsu_axi.b.valid <= io.lsu_brg.b.valid @[quasar_wrapper.scala 129:20]
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io.lsu_brg.b.ready <= swerv.io.lsu_axi.b.ready @[quasar_wrapper.scala 129:20]
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io.lsu_brg.w.bits.last <= swerv.io.lsu_axi.w.bits.last @[quasar_wrapper.scala 129:20]
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io.lsu_brg.w.bits.strb <= swerv.io.lsu_axi.w.bits.strb @[quasar_wrapper.scala 129:20]
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io.lsu_brg.w.bits.data <= swerv.io.lsu_axi.w.bits.data @[quasar_wrapper.scala 129:20]
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io.lsu_brg.w.valid <= swerv.io.lsu_axi.w.valid @[quasar_wrapper.scala 129:20]
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swerv.io.lsu_axi.w.ready <= io.lsu_brg.w.ready @[quasar_wrapper.scala 129:20]
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io.lsu_brg.aw.bits.qos <= swerv.io.lsu_axi.aw.bits.qos @[quasar_wrapper.scala 129:20]
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io.lsu_brg.aw.bits.prot <= swerv.io.lsu_axi.aw.bits.prot @[quasar_wrapper.scala 129:20]
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io.lsu_brg.aw.bits.cache <= swerv.io.lsu_axi.aw.bits.cache @[quasar_wrapper.scala 129:20]
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io.lsu_brg.aw.bits.lock <= swerv.io.lsu_axi.aw.bits.lock @[quasar_wrapper.scala 129:20]
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io.lsu_brg.aw.bits.burst <= swerv.io.lsu_axi.aw.bits.burst @[quasar_wrapper.scala 129:20]
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io.lsu_brg.aw.bits.size <= swerv.io.lsu_axi.aw.bits.size @[quasar_wrapper.scala 129:20]
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io.lsu_brg.aw.bits.len <= swerv.io.lsu_axi.aw.bits.len @[quasar_wrapper.scala 129:20]
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io.lsu_brg.aw.bits.region <= swerv.io.lsu_axi.aw.bits.region @[quasar_wrapper.scala 129:20]
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io.lsu_brg.aw.bits.addr <= swerv.io.lsu_axi.aw.bits.addr @[quasar_wrapper.scala 129:20]
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io.lsu_brg.aw.bits.id <= swerv.io.lsu_axi.aw.bits.id @[quasar_wrapper.scala 129:20]
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io.lsu_brg.aw.valid <= swerv.io.lsu_axi.aw.valid @[quasar_wrapper.scala 129:20]
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swerv.io.lsu_axi.aw.ready <= io.lsu_brg.aw.ready @[quasar_wrapper.scala 129:20]
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swerv.io.ifu_axi.r.bits.last <= io.ifu_brg.r.bits.last @[quasar_wrapper.scala 132:20]
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swerv.io.ifu_axi.r.bits.resp <= io.ifu_brg.r.bits.resp @[quasar_wrapper.scala 132:20]
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swerv.io.ifu_axi.r.bits.data <= io.ifu_brg.r.bits.data @[quasar_wrapper.scala 132:20]
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swerv.io.ifu_axi.r.bits.id <= io.ifu_brg.r.bits.id @[quasar_wrapper.scala 132:20]
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swerv.io.ifu_axi.r.valid <= io.ifu_brg.r.valid @[quasar_wrapper.scala 132:20]
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io.ifu_brg.r.ready <= swerv.io.ifu_axi.r.ready @[quasar_wrapper.scala 132:20]
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io.ifu_brg.ar.bits.qos <= swerv.io.ifu_axi.ar.bits.qos @[quasar_wrapper.scala 132:20]
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io.ifu_brg.ar.bits.prot <= swerv.io.ifu_axi.ar.bits.prot @[quasar_wrapper.scala 132:20]
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io.ifu_brg.ar.bits.cache <= swerv.io.ifu_axi.ar.bits.cache @[quasar_wrapper.scala 132:20]
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io.ifu_brg.ar.bits.lock <= swerv.io.ifu_axi.ar.bits.lock @[quasar_wrapper.scala 132:20]
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io.ifu_brg.ar.bits.burst <= swerv.io.ifu_axi.ar.bits.burst @[quasar_wrapper.scala 132:20]
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io.ifu_brg.ar.bits.size <= swerv.io.ifu_axi.ar.bits.size @[quasar_wrapper.scala 132:20]
|
||||
io.ifu_brg.ar.bits.len <= swerv.io.ifu_axi.ar.bits.len @[quasar_wrapper.scala 132:20]
|
||||
io.ifu_brg.ar.bits.region <= swerv.io.ifu_axi.ar.bits.region @[quasar_wrapper.scala 132:20]
|
||||
io.ifu_brg.ar.bits.addr <= swerv.io.ifu_axi.ar.bits.addr @[quasar_wrapper.scala 132:20]
|
||||
io.ifu_brg.ar.bits.id <= swerv.io.ifu_axi.ar.bits.id @[quasar_wrapper.scala 132:20]
|
||||
io.ifu_brg.ar.valid <= swerv.io.ifu_axi.ar.valid @[quasar_wrapper.scala 132:20]
|
||||
swerv.io.ifu_axi.ar.ready <= io.ifu_brg.ar.ready @[quasar_wrapper.scala 132:20]
|
||||
swerv.io.ifu_axi.b.bits.id <= io.ifu_brg.b.bits.id @[quasar_wrapper.scala 132:20]
|
||||
swerv.io.ifu_axi.b.bits.resp <= io.ifu_brg.b.bits.resp @[quasar_wrapper.scala 132:20]
|
||||
swerv.io.ifu_axi.b.valid <= io.ifu_brg.b.valid @[quasar_wrapper.scala 132:20]
|
||||
io.ifu_brg.b.ready <= swerv.io.ifu_axi.b.ready @[quasar_wrapper.scala 132:20]
|
||||
io.ifu_brg.w.bits.last <= swerv.io.ifu_axi.w.bits.last @[quasar_wrapper.scala 132:20]
|
||||
io.ifu_brg.w.bits.strb <= swerv.io.ifu_axi.w.bits.strb @[quasar_wrapper.scala 132:20]
|
||||
io.ifu_brg.w.bits.data <= swerv.io.ifu_axi.w.bits.data @[quasar_wrapper.scala 132:20]
|
||||
io.ifu_brg.w.valid <= swerv.io.ifu_axi.w.valid @[quasar_wrapper.scala 132:20]
|
||||
swerv.io.ifu_axi.w.ready <= io.ifu_brg.w.ready @[quasar_wrapper.scala 132:20]
|
||||
io.ifu_brg.aw.bits.qos <= swerv.io.ifu_axi.aw.bits.qos @[quasar_wrapper.scala 132:20]
|
||||
io.ifu_brg.aw.bits.prot <= swerv.io.ifu_axi.aw.bits.prot @[quasar_wrapper.scala 132:20]
|
||||
io.ifu_brg.aw.bits.cache <= swerv.io.ifu_axi.aw.bits.cache @[quasar_wrapper.scala 132:20]
|
||||
io.ifu_brg.aw.bits.lock <= swerv.io.ifu_axi.aw.bits.lock @[quasar_wrapper.scala 132:20]
|
||||
io.ifu_brg.aw.bits.burst <= swerv.io.ifu_axi.aw.bits.burst @[quasar_wrapper.scala 132:20]
|
||||
io.ifu_brg.aw.bits.size <= swerv.io.ifu_axi.aw.bits.size @[quasar_wrapper.scala 132:20]
|
||||
io.ifu_brg.aw.bits.len <= swerv.io.ifu_axi.aw.bits.len @[quasar_wrapper.scala 132:20]
|
||||
io.ifu_brg.aw.bits.region <= swerv.io.ifu_axi.aw.bits.region @[quasar_wrapper.scala 132:20]
|
||||
io.ifu_brg.aw.bits.addr <= swerv.io.ifu_axi.aw.bits.addr @[quasar_wrapper.scala 132:20]
|
||||
io.ifu_brg.aw.bits.id <= swerv.io.ifu_axi.aw.bits.id @[quasar_wrapper.scala 132:20]
|
||||
io.ifu_brg.aw.valid <= swerv.io.ifu_axi.aw.valid @[quasar_wrapper.scala 132:20]
|
||||
swerv.io.ifu_axi.aw.ready <= io.ifu_brg.aw.ready @[quasar_wrapper.scala 132:20]
|
||||
swerv.io.sb_axi.r.bits.last <= io.sb_brg.r.bits.last @[quasar_wrapper.scala 135:19]
|
||||
swerv.io.sb_axi.r.bits.resp <= io.sb_brg.r.bits.resp @[quasar_wrapper.scala 135:19]
|
||||
swerv.io.sb_axi.r.bits.data <= io.sb_brg.r.bits.data @[quasar_wrapper.scala 135:19]
|
||||
swerv.io.sb_axi.r.bits.id <= io.sb_brg.r.bits.id @[quasar_wrapper.scala 135:19]
|
||||
swerv.io.sb_axi.r.valid <= io.sb_brg.r.valid @[quasar_wrapper.scala 135:19]
|
||||
io.sb_brg.r.ready <= swerv.io.sb_axi.r.ready @[quasar_wrapper.scala 135:19]
|
||||
io.sb_brg.ar.bits.qos <= swerv.io.sb_axi.ar.bits.qos @[quasar_wrapper.scala 135:19]
|
||||
io.sb_brg.ar.bits.prot <= swerv.io.sb_axi.ar.bits.prot @[quasar_wrapper.scala 135:19]
|
||||
io.sb_brg.ar.bits.cache <= swerv.io.sb_axi.ar.bits.cache @[quasar_wrapper.scala 135:19]
|
||||
io.sb_brg.ar.bits.lock <= swerv.io.sb_axi.ar.bits.lock @[quasar_wrapper.scala 135:19]
|
||||
io.sb_brg.ar.bits.burst <= swerv.io.sb_axi.ar.bits.burst @[quasar_wrapper.scala 135:19]
|
||||
io.sb_brg.ar.bits.size <= swerv.io.sb_axi.ar.bits.size @[quasar_wrapper.scala 135:19]
|
||||
io.sb_brg.ar.bits.len <= swerv.io.sb_axi.ar.bits.len @[quasar_wrapper.scala 135:19]
|
||||
io.sb_brg.ar.bits.region <= swerv.io.sb_axi.ar.bits.region @[quasar_wrapper.scala 135:19]
|
||||
io.sb_brg.ar.bits.addr <= swerv.io.sb_axi.ar.bits.addr @[quasar_wrapper.scala 135:19]
|
||||
io.sb_brg.ar.bits.id <= swerv.io.sb_axi.ar.bits.id @[quasar_wrapper.scala 135:19]
|
||||
io.sb_brg.ar.valid <= swerv.io.sb_axi.ar.valid @[quasar_wrapper.scala 135:19]
|
||||
swerv.io.sb_axi.ar.ready <= io.sb_brg.ar.ready @[quasar_wrapper.scala 135:19]
|
||||
swerv.io.sb_axi.b.bits.id <= io.sb_brg.b.bits.id @[quasar_wrapper.scala 135:19]
|
||||
swerv.io.sb_axi.b.bits.resp <= io.sb_brg.b.bits.resp @[quasar_wrapper.scala 135:19]
|
||||
swerv.io.sb_axi.b.valid <= io.sb_brg.b.valid @[quasar_wrapper.scala 135:19]
|
||||
io.sb_brg.b.ready <= swerv.io.sb_axi.b.ready @[quasar_wrapper.scala 135:19]
|
||||
io.sb_brg.w.bits.last <= swerv.io.sb_axi.w.bits.last @[quasar_wrapper.scala 135:19]
|
||||
io.sb_brg.w.bits.strb <= swerv.io.sb_axi.w.bits.strb @[quasar_wrapper.scala 135:19]
|
||||
io.sb_brg.w.bits.data <= swerv.io.sb_axi.w.bits.data @[quasar_wrapper.scala 135:19]
|
||||
io.sb_brg.w.valid <= swerv.io.sb_axi.w.valid @[quasar_wrapper.scala 135:19]
|
||||
swerv.io.sb_axi.w.ready <= io.sb_brg.w.ready @[quasar_wrapper.scala 135:19]
|
||||
io.sb_brg.aw.bits.qos <= swerv.io.sb_axi.aw.bits.qos @[quasar_wrapper.scala 135:19]
|
||||
io.sb_brg.aw.bits.prot <= swerv.io.sb_axi.aw.bits.prot @[quasar_wrapper.scala 135:19]
|
||||
io.sb_brg.aw.bits.cache <= swerv.io.sb_axi.aw.bits.cache @[quasar_wrapper.scala 135:19]
|
||||
io.sb_brg.aw.bits.lock <= swerv.io.sb_axi.aw.bits.lock @[quasar_wrapper.scala 135:19]
|
||||
io.sb_brg.aw.bits.burst <= swerv.io.sb_axi.aw.bits.burst @[quasar_wrapper.scala 135:19]
|
||||
io.sb_brg.aw.bits.size <= swerv.io.sb_axi.aw.bits.size @[quasar_wrapper.scala 135:19]
|
||||
io.sb_brg.aw.bits.len <= swerv.io.sb_axi.aw.bits.len @[quasar_wrapper.scala 135:19]
|
||||
io.sb_brg.aw.bits.region <= swerv.io.sb_axi.aw.bits.region @[quasar_wrapper.scala 135:19]
|
||||
io.sb_brg.aw.bits.addr <= swerv.io.sb_axi.aw.bits.addr @[quasar_wrapper.scala 135:19]
|
||||
io.sb_brg.aw.bits.id <= swerv.io.sb_axi.aw.bits.id @[quasar_wrapper.scala 135:19]
|
||||
io.sb_brg.aw.valid <= swerv.io.sb_axi.aw.valid @[quasar_wrapper.scala 135:19]
|
||||
swerv.io.sb_axi.aw.ready <= io.sb_brg.aw.ready @[quasar_wrapper.scala 135:19]
|
||||
io.dma_brg.r.bits.last <= swerv.io.dma_axi.r.bits.last @[quasar_wrapper.scala 139:20]
|
||||
io.dma_brg.r.bits.resp <= swerv.io.dma_axi.r.bits.resp @[quasar_wrapper.scala 139:20]
|
||||
io.dma_brg.r.bits.data <= swerv.io.dma_axi.r.bits.data @[quasar_wrapper.scala 139:20]
|
||||
io.dma_brg.r.bits.id <= swerv.io.dma_axi.r.bits.id @[quasar_wrapper.scala 139:20]
|
||||
io.dma_brg.r.valid <= swerv.io.dma_axi.r.valid @[quasar_wrapper.scala 139:20]
|
||||
swerv.io.dma_axi.r.ready <= io.dma_brg.r.ready @[quasar_wrapper.scala 139:20]
|
||||
swerv.io.dma_axi.ar.bits.qos <= io.dma_brg.ar.bits.qos @[quasar_wrapper.scala 139:20]
|
||||
swerv.io.dma_axi.ar.bits.prot <= io.dma_brg.ar.bits.prot @[quasar_wrapper.scala 139:20]
|
||||
swerv.io.dma_axi.ar.bits.cache <= io.dma_brg.ar.bits.cache @[quasar_wrapper.scala 139:20]
|
||||
swerv.io.dma_axi.ar.bits.lock <= io.dma_brg.ar.bits.lock @[quasar_wrapper.scala 139:20]
|
||||
swerv.io.dma_axi.ar.bits.burst <= io.dma_brg.ar.bits.burst @[quasar_wrapper.scala 139:20]
|
||||
swerv.io.dma_axi.ar.bits.size <= io.dma_brg.ar.bits.size @[quasar_wrapper.scala 139:20]
|
||||
swerv.io.dma_axi.ar.bits.len <= io.dma_brg.ar.bits.len @[quasar_wrapper.scala 139:20]
|
||||
swerv.io.dma_axi.ar.bits.region <= io.dma_brg.ar.bits.region @[quasar_wrapper.scala 139:20]
|
||||
swerv.io.dma_axi.ar.bits.addr <= io.dma_brg.ar.bits.addr @[quasar_wrapper.scala 139:20]
|
||||
swerv.io.dma_axi.ar.bits.id <= io.dma_brg.ar.bits.id @[quasar_wrapper.scala 139:20]
|
||||
swerv.io.dma_axi.ar.valid <= io.dma_brg.ar.valid @[quasar_wrapper.scala 139:20]
|
||||
io.dma_brg.ar.ready <= swerv.io.dma_axi.ar.ready @[quasar_wrapper.scala 139:20]
|
||||
io.dma_brg.b.bits.id <= swerv.io.dma_axi.b.bits.id @[quasar_wrapper.scala 139:20]
|
||||
io.dma_brg.b.bits.resp <= swerv.io.dma_axi.b.bits.resp @[quasar_wrapper.scala 139:20]
|
||||
io.dma_brg.b.valid <= swerv.io.dma_axi.b.valid @[quasar_wrapper.scala 139:20]
|
||||
swerv.io.dma_axi.b.ready <= io.dma_brg.b.ready @[quasar_wrapper.scala 139:20]
|
||||
swerv.io.dma_axi.w.bits.last <= io.dma_brg.w.bits.last @[quasar_wrapper.scala 139:20]
|
||||
swerv.io.dma_axi.w.bits.strb <= io.dma_brg.w.bits.strb @[quasar_wrapper.scala 139:20]
|
||||
swerv.io.dma_axi.w.bits.data <= io.dma_brg.w.bits.data @[quasar_wrapper.scala 139:20]
|
||||
swerv.io.dma_axi.w.valid <= io.dma_brg.w.valid @[quasar_wrapper.scala 139:20]
|
||||
io.dma_brg.w.ready <= swerv.io.dma_axi.w.ready @[quasar_wrapper.scala 139:20]
|
||||
swerv.io.dma_axi.aw.bits.qos <= io.dma_brg.aw.bits.qos @[quasar_wrapper.scala 139:20]
|
||||
swerv.io.dma_axi.aw.bits.prot <= io.dma_brg.aw.bits.prot @[quasar_wrapper.scala 139:20]
|
||||
swerv.io.dma_axi.aw.bits.cache <= io.dma_brg.aw.bits.cache @[quasar_wrapper.scala 139:20]
|
||||
swerv.io.dma_axi.aw.bits.lock <= io.dma_brg.aw.bits.lock @[quasar_wrapper.scala 139:20]
|
||||
swerv.io.dma_axi.aw.bits.burst <= io.dma_brg.aw.bits.burst @[quasar_wrapper.scala 139:20]
|
||||
swerv.io.dma_axi.aw.bits.size <= io.dma_brg.aw.bits.size @[quasar_wrapper.scala 139:20]
|
||||
swerv.io.dma_axi.aw.bits.len <= io.dma_brg.aw.bits.len @[quasar_wrapper.scala 139:20]
|
||||
swerv.io.dma_axi.aw.bits.region <= io.dma_brg.aw.bits.region @[quasar_wrapper.scala 139:20]
|
||||
swerv.io.dma_axi.aw.bits.addr <= io.dma_brg.aw.bits.addr @[quasar_wrapper.scala 139:20]
|
||||
swerv.io.dma_axi.aw.bits.id <= io.dma_brg.aw.bits.id @[quasar_wrapper.scala 139:20]
|
||||
swerv.io.dma_axi.aw.valid <= io.dma_brg.aw.valid @[quasar_wrapper.scala 139:20]
|
||||
io.dma_brg.aw.ready <= swerv.io.dma_axi.aw.ready @[quasar_wrapper.scala 139:20]
|
||||
swerv.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[quasar_wrapper.scala 155:27]
|
||||
swerv.io.ifu_bus_clk_en <= io.ifu_bus_clk_en @[quasar_wrapper.scala 156:27]
|
||||
swerv.io.dbg_bus_clk_en <= io.dbg_bus_clk_en @[quasar_wrapper.scala 157:27]
|
||||
swerv.io.dma_bus_clk_en <= io.dma_bus_clk_en @[quasar_wrapper.scala 158:27]
|
||||
swerv.io.timer_int <= io.timer_int @[quasar_wrapper.scala 160:22]
|
||||
swerv.io.soft_int <= io.soft_int @[quasar_wrapper.scala 161:21]
|
||||
swerv.io.extintsrc_req <= io.extintsrc_req @[quasar_wrapper.scala 162:26]
|
||||
io.rv_trace_pkt.rv_i_tval_ip <= swerv.io.rv_trace_pkt.rv_i_tval_ip @[quasar_wrapper.scala 166:19]
|
||||
io.rv_trace_pkt.rv_i_interrupt_ip <= swerv.io.rv_trace_pkt.rv_i_interrupt_ip @[quasar_wrapper.scala 166:19]
|
||||
io.rv_trace_pkt.rv_i_ecause_ip <= swerv.io.rv_trace_pkt.rv_i_ecause_ip @[quasar_wrapper.scala 166:19]
|
||||
io.rv_trace_pkt.rv_i_exception_ip <= swerv.io.rv_trace_pkt.rv_i_exception_ip @[quasar_wrapper.scala 166:19]
|
||||
io.rv_trace_pkt.rv_i_address_ip <= swerv.io.rv_trace_pkt.rv_i_address_ip @[quasar_wrapper.scala 166:19]
|
||||
io.rv_trace_pkt.rv_i_insn_ip <= swerv.io.rv_trace_pkt.rv_i_insn_ip @[quasar_wrapper.scala 166:19]
|
||||
io.rv_trace_pkt.rv_i_valid_ip <= swerv.io.rv_trace_pkt.rv_i_valid_ip @[quasar_wrapper.scala 166:19]
|
||||
io.o_cpu_halt_ack <= swerv.io.o_cpu_halt_ack @[quasar_wrapper.scala 169:21]
|
||||
io.o_cpu_halt_status <= swerv.io.o_cpu_halt_status @[quasar_wrapper.scala 170:24]
|
||||
io.o_cpu_run_ack <= swerv.io.o_cpu_run_ack @[quasar_wrapper.scala 171:20]
|
||||
io.o_debug_mode_status <= swerv.io.o_debug_mode_status @[quasar_wrapper.scala 172:26]
|
||||
io.mpc_debug_halt_ack <= swerv.io.mpc_debug_halt_ack @[quasar_wrapper.scala 174:25]
|
||||
io.mpc_debug_run_ack <= swerv.io.mpc_debug_run_ack @[quasar_wrapper.scala 175:24]
|
||||
io.debug_brkpt_status <= swerv.io.debug_brkpt_status @[quasar_wrapper.scala 176:25]
|
||||
io.dec_tlu_perfcnt0 <= swerv.io.dec_tlu_perfcnt0 @[quasar_wrapper.scala 178:23]
|
||||
io.dec_tlu_perfcnt1 <= swerv.io.dec_tlu_perfcnt1 @[quasar_wrapper.scala 179:23]
|
||||
io.dec_tlu_perfcnt2 <= swerv.io.dec_tlu_perfcnt2 @[quasar_wrapper.scala 180:23]
|
||||
io.dec_tlu_perfcnt3 <= swerv.io.dec_tlu_perfcnt3 @[quasar_wrapper.scala 181:23]
|
||||
swerv.io.scan_mode <= io.scan_mode @[quasar_wrapper.scala 66:22]
|
||||
dmi_wrapper.trst_n <= io.jtag_trst_n @[quasar_wrapper.scala 67:25]
|
||||
dmi_wrapper.tck <= io.jtag_tck @[quasar_wrapper.scala 68:22]
|
||||
dmi_wrapper.tms <= io.jtag_tms @[quasar_wrapper.scala 69:22]
|
||||
dmi_wrapper.tdi <= io.jtag_tdi @[quasar_wrapper.scala 70:22]
|
||||
dmi_wrapper.core_clk <= clock @[quasar_wrapper.scala 71:27]
|
||||
dmi_wrapper.jtag_id <= io.jtag_id @[quasar_wrapper.scala 72:26]
|
||||
dmi_wrapper.rd_data <= swerv.io.dmi_reg_rdata @[quasar_wrapper.scala 73:26]
|
||||
dmi_wrapper.core_rst_n <= io.dbg_rst_l @[quasar_wrapper.scala 76:29]
|
||||
swerv.io.dmi_reg_wdata <= dmi_wrapper.reg_wr_data @[quasar_wrapper.scala 77:26]
|
||||
swerv.io.dmi_reg_addr <= dmi_wrapper.reg_wr_addr @[quasar_wrapper.scala 78:25]
|
||||
swerv.io.dmi_reg_en <= dmi_wrapper.reg_en @[quasar_wrapper.scala 79:23]
|
||||
swerv.io.dmi_reg_wr_en <= dmi_wrapper.reg_wr_en @[quasar_wrapper.scala 80:26]
|
||||
swerv.io.dmi_hard_reset <= dmi_wrapper.dmi_hard_reset @[quasar_wrapper.scala 81:27]
|
||||
io.jtag_tdo <= dmi_wrapper.tdo @[quasar_wrapper.scala 82:15]
|
||||
mem.dccm_clk_override <= swerv.io.dccm_clk_override @[quasar_wrapper.scala 85:28]
|
||||
mem.icm_clk_override <= swerv.io.icm_clk_override @[quasar_wrapper.scala 86:27]
|
||||
mem.dec_tlu_core_ecc_disable <= swerv.io.dec_tlu_core_ecc_disable @[quasar_wrapper.scala 87:35]
|
||||
swerv.io.dccm.rd_data_hi <= mem.dccm.rd_data_hi @[quasar_wrapper.scala 88:15]
|
||||
swerv.io.dccm.rd_data_lo <= mem.dccm.rd_data_lo @[quasar_wrapper.scala 88:15]
|
||||
mem.dccm.wr_data_hi <= swerv.io.dccm.wr_data_hi @[quasar_wrapper.scala 88:15]
|
||||
mem.dccm.wr_data_lo <= swerv.io.dccm.wr_data_lo @[quasar_wrapper.scala 88:15]
|
||||
mem.dccm.rd_addr_hi <= swerv.io.dccm.rd_addr_hi @[quasar_wrapper.scala 88:15]
|
||||
mem.dccm.rd_addr_lo <= swerv.io.dccm.rd_addr_lo @[quasar_wrapper.scala 88:15]
|
||||
mem.dccm.wr_addr_hi <= swerv.io.dccm.wr_addr_hi @[quasar_wrapper.scala 88:15]
|
||||
mem.dccm.wr_addr_lo <= swerv.io.dccm.wr_addr_lo @[quasar_wrapper.scala 88:15]
|
||||
mem.dccm.rden <= swerv.io.dccm.rden @[quasar_wrapper.scala 88:15]
|
||||
mem.dccm.wren <= swerv.io.dccm.wren @[quasar_wrapper.scala 88:15]
|
||||
mem.rst_l <= reset @[quasar_wrapper.scala 89:16]
|
||||
mem.clk <= clock @[quasar_wrapper.scala 90:14]
|
||||
mem.scan_mode <= io.scan_mode @[quasar_wrapper.scala 91:20]
|
||||
swerv.io.dbg_rst_l <= io.dbg_rst_l @[quasar_wrapper.scala 93:22]
|
||||
mem.ic.sel_premux_data <= swerv.io.ic.sel_premux_data @[quasar_wrapper.scala 94:15]
|
||||
mem.ic.premux_data <= swerv.io.ic.premux_data @[quasar_wrapper.scala 94:15]
|
||||
mem.ic.debug_way <= swerv.io.ic.debug_way @[quasar_wrapper.scala 94:15]
|
||||
mem.ic.debug_tag_array <= swerv.io.ic.debug_tag_array @[quasar_wrapper.scala 94:15]
|
||||
mem.ic.debug_wr_en <= swerv.io.ic.debug_wr_en @[quasar_wrapper.scala 94:15]
|
||||
mem.ic.debug_rd_en <= swerv.io.ic.debug_rd_en @[quasar_wrapper.scala 94:15]
|
||||
swerv.io.ic.tag_perr <= mem.ic.tag_perr @[quasar_wrapper.scala 94:15]
|
||||
swerv.io.ic.rd_hit <= mem.ic.rd_hit @[quasar_wrapper.scala 94:15]
|
||||
swerv.io.ic.parerr <= mem.ic.parerr @[quasar_wrapper.scala 94:15]
|
||||
swerv.io.ic.eccerr <= mem.ic.eccerr @[quasar_wrapper.scala 94:15]
|
||||
swerv.io.ic.tag_debug_rd_data <= mem.ic.tag_debug_rd_data @[quasar_wrapper.scala 94:15]
|
||||
swerv.io.ic.debug_rd_data <= mem.ic.debug_rd_data @[quasar_wrapper.scala 94:15]
|
||||
swerv.io.ic.rd_data <= mem.ic.rd_data @[quasar_wrapper.scala 94:15]
|
||||
mem.ic.debug_addr <= swerv.io.ic.debug_addr @[quasar_wrapper.scala 94:15]
|
||||
mem.ic.debug_wr_data <= swerv.io.ic.debug_wr_data @[quasar_wrapper.scala 94:15]
|
||||
mem.ic.wr_data[0] <= swerv.io.ic.wr_data[0] @[quasar_wrapper.scala 94:15]
|
||||
mem.ic.wr_data[1] <= swerv.io.ic.wr_data[1] @[quasar_wrapper.scala 94:15]
|
||||
mem.ic.rd_en <= swerv.io.ic.rd_en @[quasar_wrapper.scala 94:15]
|
||||
mem.ic.wr_en <= swerv.io.ic.wr_en @[quasar_wrapper.scala 94:15]
|
||||
mem.ic.tag_valid <= swerv.io.ic.tag_valid @[quasar_wrapper.scala 94:15]
|
||||
mem.ic.rw_addr <= swerv.io.ic.rw_addr @[quasar_wrapper.scala 94:15]
|
||||
swerv.io.iccm.rd_data_ecc <= mem.iccm.rd_data_ecc @[quasar_wrapper.scala 95:17]
|
||||
swerv.io.iccm.rd_data <= mem.iccm.rd_data @[quasar_wrapper.scala 95:17]
|
||||
mem.iccm.wr_data <= swerv.io.iccm.wr_data @[quasar_wrapper.scala 95:17]
|
||||
mem.iccm.wr_size <= swerv.io.iccm.wr_size @[quasar_wrapper.scala 95:17]
|
||||
mem.iccm.rden <= swerv.io.iccm.rden @[quasar_wrapper.scala 95:17]
|
||||
mem.iccm.wren <= swerv.io.iccm.wren @[quasar_wrapper.scala 95:17]
|
||||
mem.iccm.correction_state <= swerv.io.iccm.correction_state @[quasar_wrapper.scala 95:17]
|
||||
mem.iccm.buf_correct_ecc <= swerv.io.iccm.buf_correct_ecc @[quasar_wrapper.scala 95:17]
|
||||
mem.iccm.rw_addr <= swerv.io.iccm.rw_addr @[quasar_wrapper.scala 95:17]
|
||||
wire _T : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>} @[quasar_wrapper.scala 99:36]
|
||||
_T.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 99:36]
|
||||
_T.hready <= UInt<1>("h00") @[quasar_wrapper.scala 99:36]
|
||||
_T.hrdata <= UInt<64>("h00") @[quasar_wrapper.scala 99:36]
|
||||
swerv.io.ahb.in.hresp <= _T.hresp @[quasar_wrapper.scala 99:21]
|
||||
swerv.io.ahb.in.hready <= _T.hready @[quasar_wrapper.scala 99:21]
|
||||
swerv.io.ahb.in.hrdata <= _T.hrdata @[quasar_wrapper.scala 99:21]
|
||||
wire _T_1 : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>} @[quasar_wrapper.scala 100:40]
|
||||
_T_1.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 100:40]
|
||||
_T_1.hready <= UInt<1>("h00") @[quasar_wrapper.scala 100:40]
|
||||
_T_1.hrdata <= UInt<64>("h00") @[quasar_wrapper.scala 100:40]
|
||||
swerv.io.lsu_ahb.in.hresp <= _T_1.hresp @[quasar_wrapper.scala 100:25]
|
||||
swerv.io.lsu_ahb.in.hready <= _T_1.hready @[quasar_wrapper.scala 100:25]
|
||||
swerv.io.lsu_ahb.in.hrdata <= _T_1.hrdata @[quasar_wrapper.scala 100:25]
|
||||
wire _T_2 : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>} @[quasar_wrapper.scala 101:39]
|
||||
_T_2.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 101:39]
|
||||
_T_2.hready <= UInt<1>("h00") @[quasar_wrapper.scala 101:39]
|
||||
_T_2.hrdata <= UInt<64>("h00") @[quasar_wrapper.scala 101:39]
|
||||
swerv.io.sb_ahb.in.hresp <= _T_2.hresp @[quasar_wrapper.scala 101:24]
|
||||
swerv.io.sb_ahb.in.hready <= _T_2.hready @[quasar_wrapper.scala 101:24]
|
||||
swerv.io.sb_ahb.in.hrdata <= _T_2.hrdata @[quasar_wrapper.scala 101:24]
|
||||
wire _T_3 : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>} @[quasar_wrapper.scala 102:41]
|
||||
_T_3.hwdata <= UInt<64>("h00") @[quasar_wrapper.scala 102:41]
|
||||
_T_3.hwrite <= UInt<1>("h00") @[quasar_wrapper.scala 102:41]
|
||||
_T_3.htrans <= UInt<2>("h00") @[quasar_wrapper.scala 102:41]
|
||||
_T_3.hsize <= UInt<3>("h00") @[quasar_wrapper.scala 102:41]
|
||||
_T_3.hprot <= UInt<4>("h00") @[quasar_wrapper.scala 102:41]
|
||||
_T_3.hmastlock <= UInt<1>("h00") @[quasar_wrapper.scala 102:41]
|
||||
_T_3.hburst <= UInt<3>("h00") @[quasar_wrapper.scala 102:41]
|
||||
_T_3.haddr <= UInt<32>("h00") @[quasar_wrapper.scala 102:41]
|
||||
swerv.io.dma.ahb.out.hwdata <= _T_3.hwdata @[quasar_wrapper.scala 102:26]
|
||||
swerv.io.dma.ahb.out.hwrite <= _T_3.hwrite @[quasar_wrapper.scala 102:26]
|
||||
swerv.io.dma.ahb.out.htrans <= _T_3.htrans @[quasar_wrapper.scala 102:26]
|
||||
swerv.io.dma.ahb.out.hsize <= _T_3.hsize @[quasar_wrapper.scala 102:26]
|
||||
swerv.io.dma.ahb.out.hprot <= _T_3.hprot @[quasar_wrapper.scala 102:26]
|
||||
swerv.io.dma.ahb.out.hmastlock <= _T_3.hmastlock @[quasar_wrapper.scala 102:26]
|
||||
swerv.io.dma.ahb.out.hburst <= _T_3.hburst @[quasar_wrapper.scala 102:26]
|
||||
swerv.io.dma.ahb.out.haddr <= _T_3.haddr @[quasar_wrapper.scala 102:26]
|
||||
swerv.io.dma.hsel <= UInt<1>("h00") @[quasar_wrapper.scala 103:23]
|
||||
swerv.io.dma.hreadyin <= UInt<1>("h00") @[quasar_wrapper.scala 104:27]
|
||||
swerv.io.lsu_axi.r.bits.last <= io.lsu_brg.r.bits.last @[quasar_wrapper.scala 105:22]
|
||||
swerv.io.lsu_axi.r.bits.resp <= io.lsu_brg.r.bits.resp @[quasar_wrapper.scala 105:22]
|
||||
swerv.io.lsu_axi.r.bits.data <= io.lsu_brg.r.bits.data @[quasar_wrapper.scala 105:22]
|
||||
swerv.io.lsu_axi.r.bits.id <= io.lsu_brg.r.bits.id @[quasar_wrapper.scala 105:22]
|
||||
swerv.io.lsu_axi.r.valid <= io.lsu_brg.r.valid @[quasar_wrapper.scala 105:22]
|
||||
io.lsu_brg.r.ready <= swerv.io.lsu_axi.r.ready @[quasar_wrapper.scala 105:22]
|
||||
io.lsu_brg.ar.bits.qos <= swerv.io.lsu_axi.ar.bits.qos @[quasar_wrapper.scala 105:22]
|
||||
io.lsu_brg.ar.bits.prot <= swerv.io.lsu_axi.ar.bits.prot @[quasar_wrapper.scala 105:22]
|
||||
io.lsu_brg.ar.bits.cache <= swerv.io.lsu_axi.ar.bits.cache @[quasar_wrapper.scala 105:22]
|
||||
io.lsu_brg.ar.bits.lock <= swerv.io.lsu_axi.ar.bits.lock @[quasar_wrapper.scala 105:22]
|
||||
io.lsu_brg.ar.bits.burst <= swerv.io.lsu_axi.ar.bits.burst @[quasar_wrapper.scala 105:22]
|
||||
io.lsu_brg.ar.bits.size <= swerv.io.lsu_axi.ar.bits.size @[quasar_wrapper.scala 105:22]
|
||||
io.lsu_brg.ar.bits.len <= swerv.io.lsu_axi.ar.bits.len @[quasar_wrapper.scala 105:22]
|
||||
io.lsu_brg.ar.bits.region <= swerv.io.lsu_axi.ar.bits.region @[quasar_wrapper.scala 105:22]
|
||||
io.lsu_brg.ar.bits.addr <= swerv.io.lsu_axi.ar.bits.addr @[quasar_wrapper.scala 105:22]
|
||||
io.lsu_brg.ar.bits.id <= swerv.io.lsu_axi.ar.bits.id @[quasar_wrapper.scala 105:22]
|
||||
io.lsu_brg.ar.valid <= swerv.io.lsu_axi.ar.valid @[quasar_wrapper.scala 105:22]
|
||||
swerv.io.lsu_axi.ar.ready <= io.lsu_brg.ar.ready @[quasar_wrapper.scala 105:22]
|
||||
swerv.io.lsu_axi.b.bits.id <= io.lsu_brg.b.bits.id @[quasar_wrapper.scala 105:22]
|
||||
swerv.io.lsu_axi.b.bits.resp <= io.lsu_brg.b.bits.resp @[quasar_wrapper.scala 105:22]
|
||||
swerv.io.lsu_axi.b.valid <= io.lsu_brg.b.valid @[quasar_wrapper.scala 105:22]
|
||||
io.lsu_brg.b.ready <= swerv.io.lsu_axi.b.ready @[quasar_wrapper.scala 105:22]
|
||||
io.lsu_brg.w.bits.last <= swerv.io.lsu_axi.w.bits.last @[quasar_wrapper.scala 105:22]
|
||||
io.lsu_brg.w.bits.strb <= swerv.io.lsu_axi.w.bits.strb @[quasar_wrapper.scala 105:22]
|
||||
io.lsu_brg.w.bits.data <= swerv.io.lsu_axi.w.bits.data @[quasar_wrapper.scala 105:22]
|
||||
io.lsu_brg.w.valid <= swerv.io.lsu_axi.w.valid @[quasar_wrapper.scala 105:22]
|
||||
swerv.io.lsu_axi.w.ready <= io.lsu_brg.w.ready @[quasar_wrapper.scala 105:22]
|
||||
io.lsu_brg.aw.bits.qos <= swerv.io.lsu_axi.aw.bits.qos @[quasar_wrapper.scala 105:22]
|
||||
io.lsu_brg.aw.bits.prot <= swerv.io.lsu_axi.aw.bits.prot @[quasar_wrapper.scala 105:22]
|
||||
io.lsu_brg.aw.bits.cache <= swerv.io.lsu_axi.aw.bits.cache @[quasar_wrapper.scala 105:22]
|
||||
io.lsu_brg.aw.bits.lock <= swerv.io.lsu_axi.aw.bits.lock @[quasar_wrapper.scala 105:22]
|
||||
io.lsu_brg.aw.bits.burst <= swerv.io.lsu_axi.aw.bits.burst @[quasar_wrapper.scala 105:22]
|
||||
io.lsu_brg.aw.bits.size <= swerv.io.lsu_axi.aw.bits.size @[quasar_wrapper.scala 105:22]
|
||||
io.lsu_brg.aw.bits.len <= swerv.io.lsu_axi.aw.bits.len @[quasar_wrapper.scala 105:22]
|
||||
io.lsu_brg.aw.bits.region <= swerv.io.lsu_axi.aw.bits.region @[quasar_wrapper.scala 105:22]
|
||||
io.lsu_brg.aw.bits.addr <= swerv.io.lsu_axi.aw.bits.addr @[quasar_wrapper.scala 105:22]
|
||||
io.lsu_brg.aw.bits.id <= swerv.io.lsu_axi.aw.bits.id @[quasar_wrapper.scala 105:22]
|
||||
io.lsu_brg.aw.valid <= swerv.io.lsu_axi.aw.valid @[quasar_wrapper.scala 105:22]
|
||||
swerv.io.lsu_axi.aw.ready <= io.lsu_brg.aw.ready @[quasar_wrapper.scala 105:22]
|
||||
swerv.io.ifu_axi.r.bits.last <= io.ifu_brg.r.bits.last @[quasar_wrapper.scala 106:22]
|
||||
swerv.io.ifu_axi.r.bits.resp <= io.ifu_brg.r.bits.resp @[quasar_wrapper.scala 106:22]
|
||||
swerv.io.ifu_axi.r.bits.data <= io.ifu_brg.r.bits.data @[quasar_wrapper.scala 106:22]
|
||||
swerv.io.ifu_axi.r.bits.id <= io.ifu_brg.r.bits.id @[quasar_wrapper.scala 106:22]
|
||||
swerv.io.ifu_axi.r.valid <= io.ifu_brg.r.valid @[quasar_wrapper.scala 106:22]
|
||||
io.ifu_brg.r.ready <= swerv.io.ifu_axi.r.ready @[quasar_wrapper.scala 106:22]
|
||||
io.ifu_brg.ar.bits.qos <= swerv.io.ifu_axi.ar.bits.qos @[quasar_wrapper.scala 106:22]
|
||||
io.ifu_brg.ar.bits.prot <= swerv.io.ifu_axi.ar.bits.prot @[quasar_wrapper.scala 106:22]
|
||||
io.ifu_brg.ar.bits.cache <= swerv.io.ifu_axi.ar.bits.cache @[quasar_wrapper.scala 106:22]
|
||||
io.ifu_brg.ar.bits.lock <= swerv.io.ifu_axi.ar.bits.lock @[quasar_wrapper.scala 106:22]
|
||||
io.ifu_brg.ar.bits.burst <= swerv.io.ifu_axi.ar.bits.burst @[quasar_wrapper.scala 106:22]
|
||||
io.ifu_brg.ar.bits.size <= swerv.io.ifu_axi.ar.bits.size @[quasar_wrapper.scala 106:22]
|
||||
io.ifu_brg.ar.bits.len <= swerv.io.ifu_axi.ar.bits.len @[quasar_wrapper.scala 106:22]
|
||||
io.ifu_brg.ar.bits.region <= swerv.io.ifu_axi.ar.bits.region @[quasar_wrapper.scala 106:22]
|
||||
io.ifu_brg.ar.bits.addr <= swerv.io.ifu_axi.ar.bits.addr @[quasar_wrapper.scala 106:22]
|
||||
io.ifu_brg.ar.bits.id <= swerv.io.ifu_axi.ar.bits.id @[quasar_wrapper.scala 106:22]
|
||||
io.ifu_brg.ar.valid <= swerv.io.ifu_axi.ar.valid @[quasar_wrapper.scala 106:22]
|
||||
swerv.io.ifu_axi.ar.ready <= io.ifu_brg.ar.ready @[quasar_wrapper.scala 106:22]
|
||||
swerv.io.ifu_axi.b.bits.id <= io.ifu_brg.b.bits.id @[quasar_wrapper.scala 106:22]
|
||||
swerv.io.ifu_axi.b.bits.resp <= io.ifu_brg.b.bits.resp @[quasar_wrapper.scala 106:22]
|
||||
swerv.io.ifu_axi.b.valid <= io.ifu_brg.b.valid @[quasar_wrapper.scala 106:22]
|
||||
io.ifu_brg.b.ready <= swerv.io.ifu_axi.b.ready @[quasar_wrapper.scala 106:22]
|
||||
io.ifu_brg.w.bits.last <= swerv.io.ifu_axi.w.bits.last @[quasar_wrapper.scala 106:22]
|
||||
io.ifu_brg.w.bits.strb <= swerv.io.ifu_axi.w.bits.strb @[quasar_wrapper.scala 106:22]
|
||||
io.ifu_brg.w.bits.data <= swerv.io.ifu_axi.w.bits.data @[quasar_wrapper.scala 106:22]
|
||||
io.ifu_brg.w.valid <= swerv.io.ifu_axi.w.valid @[quasar_wrapper.scala 106:22]
|
||||
swerv.io.ifu_axi.w.ready <= io.ifu_brg.w.ready @[quasar_wrapper.scala 106:22]
|
||||
io.ifu_brg.aw.bits.qos <= swerv.io.ifu_axi.aw.bits.qos @[quasar_wrapper.scala 106:22]
|
||||
io.ifu_brg.aw.bits.prot <= swerv.io.ifu_axi.aw.bits.prot @[quasar_wrapper.scala 106:22]
|
||||
io.ifu_brg.aw.bits.cache <= swerv.io.ifu_axi.aw.bits.cache @[quasar_wrapper.scala 106:22]
|
||||
io.ifu_brg.aw.bits.lock <= swerv.io.ifu_axi.aw.bits.lock @[quasar_wrapper.scala 106:22]
|
||||
io.ifu_brg.aw.bits.burst <= swerv.io.ifu_axi.aw.bits.burst @[quasar_wrapper.scala 106:22]
|
||||
io.ifu_brg.aw.bits.size <= swerv.io.ifu_axi.aw.bits.size @[quasar_wrapper.scala 106:22]
|
||||
io.ifu_brg.aw.bits.len <= swerv.io.ifu_axi.aw.bits.len @[quasar_wrapper.scala 106:22]
|
||||
io.ifu_brg.aw.bits.region <= swerv.io.ifu_axi.aw.bits.region @[quasar_wrapper.scala 106:22]
|
||||
io.ifu_brg.aw.bits.addr <= swerv.io.ifu_axi.aw.bits.addr @[quasar_wrapper.scala 106:22]
|
||||
io.ifu_brg.aw.bits.id <= swerv.io.ifu_axi.aw.bits.id @[quasar_wrapper.scala 106:22]
|
||||
io.ifu_brg.aw.valid <= swerv.io.ifu_axi.aw.valid @[quasar_wrapper.scala 106:22]
|
||||
swerv.io.ifu_axi.aw.ready <= io.ifu_brg.aw.ready @[quasar_wrapper.scala 106:22]
|
||||
swerv.io.sb_axi.r.bits.last <= io.sb_brg.r.bits.last @[quasar_wrapper.scala 107:21]
|
||||
swerv.io.sb_axi.r.bits.resp <= io.sb_brg.r.bits.resp @[quasar_wrapper.scala 107:21]
|
||||
swerv.io.sb_axi.r.bits.data <= io.sb_brg.r.bits.data @[quasar_wrapper.scala 107:21]
|
||||
swerv.io.sb_axi.r.bits.id <= io.sb_brg.r.bits.id @[quasar_wrapper.scala 107:21]
|
||||
swerv.io.sb_axi.r.valid <= io.sb_brg.r.valid @[quasar_wrapper.scala 107:21]
|
||||
io.sb_brg.r.ready <= swerv.io.sb_axi.r.ready @[quasar_wrapper.scala 107:21]
|
||||
io.sb_brg.ar.bits.qos <= swerv.io.sb_axi.ar.bits.qos @[quasar_wrapper.scala 107:21]
|
||||
io.sb_brg.ar.bits.prot <= swerv.io.sb_axi.ar.bits.prot @[quasar_wrapper.scala 107:21]
|
||||
io.sb_brg.ar.bits.cache <= swerv.io.sb_axi.ar.bits.cache @[quasar_wrapper.scala 107:21]
|
||||
io.sb_brg.ar.bits.lock <= swerv.io.sb_axi.ar.bits.lock @[quasar_wrapper.scala 107:21]
|
||||
io.sb_brg.ar.bits.burst <= swerv.io.sb_axi.ar.bits.burst @[quasar_wrapper.scala 107:21]
|
||||
io.sb_brg.ar.bits.size <= swerv.io.sb_axi.ar.bits.size @[quasar_wrapper.scala 107:21]
|
||||
io.sb_brg.ar.bits.len <= swerv.io.sb_axi.ar.bits.len @[quasar_wrapper.scala 107:21]
|
||||
io.sb_brg.ar.bits.region <= swerv.io.sb_axi.ar.bits.region @[quasar_wrapper.scala 107:21]
|
||||
io.sb_brg.ar.bits.addr <= swerv.io.sb_axi.ar.bits.addr @[quasar_wrapper.scala 107:21]
|
||||
io.sb_brg.ar.bits.id <= swerv.io.sb_axi.ar.bits.id @[quasar_wrapper.scala 107:21]
|
||||
io.sb_brg.ar.valid <= swerv.io.sb_axi.ar.valid @[quasar_wrapper.scala 107:21]
|
||||
swerv.io.sb_axi.ar.ready <= io.sb_brg.ar.ready @[quasar_wrapper.scala 107:21]
|
||||
swerv.io.sb_axi.b.bits.id <= io.sb_brg.b.bits.id @[quasar_wrapper.scala 107:21]
|
||||
swerv.io.sb_axi.b.bits.resp <= io.sb_brg.b.bits.resp @[quasar_wrapper.scala 107:21]
|
||||
swerv.io.sb_axi.b.valid <= io.sb_brg.b.valid @[quasar_wrapper.scala 107:21]
|
||||
io.sb_brg.b.ready <= swerv.io.sb_axi.b.ready @[quasar_wrapper.scala 107:21]
|
||||
io.sb_brg.w.bits.last <= swerv.io.sb_axi.w.bits.last @[quasar_wrapper.scala 107:21]
|
||||
io.sb_brg.w.bits.strb <= swerv.io.sb_axi.w.bits.strb @[quasar_wrapper.scala 107:21]
|
||||
io.sb_brg.w.bits.data <= swerv.io.sb_axi.w.bits.data @[quasar_wrapper.scala 107:21]
|
||||
io.sb_brg.w.valid <= swerv.io.sb_axi.w.valid @[quasar_wrapper.scala 107:21]
|
||||
swerv.io.sb_axi.w.ready <= io.sb_brg.w.ready @[quasar_wrapper.scala 107:21]
|
||||
io.sb_brg.aw.bits.qos <= swerv.io.sb_axi.aw.bits.qos @[quasar_wrapper.scala 107:21]
|
||||
io.sb_brg.aw.bits.prot <= swerv.io.sb_axi.aw.bits.prot @[quasar_wrapper.scala 107:21]
|
||||
io.sb_brg.aw.bits.cache <= swerv.io.sb_axi.aw.bits.cache @[quasar_wrapper.scala 107:21]
|
||||
io.sb_brg.aw.bits.lock <= swerv.io.sb_axi.aw.bits.lock @[quasar_wrapper.scala 107:21]
|
||||
io.sb_brg.aw.bits.burst <= swerv.io.sb_axi.aw.bits.burst @[quasar_wrapper.scala 107:21]
|
||||
io.sb_brg.aw.bits.size <= swerv.io.sb_axi.aw.bits.size @[quasar_wrapper.scala 107:21]
|
||||
io.sb_brg.aw.bits.len <= swerv.io.sb_axi.aw.bits.len @[quasar_wrapper.scala 107:21]
|
||||
io.sb_brg.aw.bits.region <= swerv.io.sb_axi.aw.bits.region @[quasar_wrapper.scala 107:21]
|
||||
io.sb_brg.aw.bits.addr <= swerv.io.sb_axi.aw.bits.addr @[quasar_wrapper.scala 107:21]
|
||||
io.sb_brg.aw.bits.id <= swerv.io.sb_axi.aw.bits.id @[quasar_wrapper.scala 107:21]
|
||||
io.sb_brg.aw.valid <= swerv.io.sb_axi.aw.valid @[quasar_wrapper.scala 107:21]
|
||||
swerv.io.sb_axi.aw.ready <= io.sb_brg.aw.ready @[quasar_wrapper.scala 107:21]
|
||||
io.dma_brg.r.bits.last <= swerv.io.dma_axi.r.bits.last @[quasar_wrapper.scala 108:22]
|
||||
io.dma_brg.r.bits.resp <= swerv.io.dma_axi.r.bits.resp @[quasar_wrapper.scala 108:22]
|
||||
io.dma_brg.r.bits.data <= swerv.io.dma_axi.r.bits.data @[quasar_wrapper.scala 108:22]
|
||||
io.dma_brg.r.bits.id <= swerv.io.dma_axi.r.bits.id @[quasar_wrapper.scala 108:22]
|
||||
io.dma_brg.r.valid <= swerv.io.dma_axi.r.valid @[quasar_wrapper.scala 108:22]
|
||||
swerv.io.dma_axi.r.ready <= io.dma_brg.r.ready @[quasar_wrapper.scala 108:22]
|
||||
swerv.io.dma_axi.ar.bits.qos <= io.dma_brg.ar.bits.qos @[quasar_wrapper.scala 108:22]
|
||||
swerv.io.dma_axi.ar.bits.prot <= io.dma_brg.ar.bits.prot @[quasar_wrapper.scala 108:22]
|
||||
swerv.io.dma_axi.ar.bits.cache <= io.dma_brg.ar.bits.cache @[quasar_wrapper.scala 108:22]
|
||||
swerv.io.dma_axi.ar.bits.lock <= io.dma_brg.ar.bits.lock @[quasar_wrapper.scala 108:22]
|
||||
swerv.io.dma_axi.ar.bits.burst <= io.dma_brg.ar.bits.burst @[quasar_wrapper.scala 108:22]
|
||||
swerv.io.dma_axi.ar.bits.size <= io.dma_brg.ar.bits.size @[quasar_wrapper.scala 108:22]
|
||||
swerv.io.dma_axi.ar.bits.len <= io.dma_brg.ar.bits.len @[quasar_wrapper.scala 108:22]
|
||||
swerv.io.dma_axi.ar.bits.region <= io.dma_brg.ar.bits.region @[quasar_wrapper.scala 108:22]
|
||||
swerv.io.dma_axi.ar.bits.addr <= io.dma_brg.ar.bits.addr @[quasar_wrapper.scala 108:22]
|
||||
swerv.io.dma_axi.ar.bits.id <= io.dma_brg.ar.bits.id @[quasar_wrapper.scala 108:22]
|
||||
swerv.io.dma_axi.ar.valid <= io.dma_brg.ar.valid @[quasar_wrapper.scala 108:22]
|
||||
io.dma_brg.ar.ready <= swerv.io.dma_axi.ar.ready @[quasar_wrapper.scala 108:22]
|
||||
io.dma_brg.b.bits.id <= swerv.io.dma_axi.b.bits.id @[quasar_wrapper.scala 108:22]
|
||||
io.dma_brg.b.bits.resp <= swerv.io.dma_axi.b.bits.resp @[quasar_wrapper.scala 108:22]
|
||||
io.dma_brg.b.valid <= swerv.io.dma_axi.b.valid @[quasar_wrapper.scala 108:22]
|
||||
swerv.io.dma_axi.b.ready <= io.dma_brg.b.ready @[quasar_wrapper.scala 108:22]
|
||||
swerv.io.dma_axi.w.bits.last <= io.dma_brg.w.bits.last @[quasar_wrapper.scala 108:22]
|
||||
swerv.io.dma_axi.w.bits.strb <= io.dma_brg.w.bits.strb @[quasar_wrapper.scala 108:22]
|
||||
swerv.io.dma_axi.w.bits.data <= io.dma_brg.w.bits.data @[quasar_wrapper.scala 108:22]
|
||||
swerv.io.dma_axi.w.valid <= io.dma_brg.w.valid @[quasar_wrapper.scala 108:22]
|
||||
io.dma_brg.w.ready <= swerv.io.dma_axi.w.ready @[quasar_wrapper.scala 108:22]
|
||||
swerv.io.dma_axi.aw.bits.qos <= io.dma_brg.aw.bits.qos @[quasar_wrapper.scala 108:22]
|
||||
swerv.io.dma_axi.aw.bits.prot <= io.dma_brg.aw.bits.prot @[quasar_wrapper.scala 108:22]
|
||||
swerv.io.dma_axi.aw.bits.cache <= io.dma_brg.aw.bits.cache @[quasar_wrapper.scala 108:22]
|
||||
swerv.io.dma_axi.aw.bits.lock <= io.dma_brg.aw.bits.lock @[quasar_wrapper.scala 108:22]
|
||||
swerv.io.dma_axi.aw.bits.burst <= io.dma_brg.aw.bits.burst @[quasar_wrapper.scala 108:22]
|
||||
swerv.io.dma_axi.aw.bits.size <= io.dma_brg.aw.bits.size @[quasar_wrapper.scala 108:22]
|
||||
swerv.io.dma_axi.aw.bits.len <= io.dma_brg.aw.bits.len @[quasar_wrapper.scala 108:22]
|
||||
swerv.io.dma_axi.aw.bits.region <= io.dma_brg.aw.bits.region @[quasar_wrapper.scala 108:22]
|
||||
swerv.io.dma_axi.aw.bits.addr <= io.dma_brg.aw.bits.addr @[quasar_wrapper.scala 108:22]
|
||||
swerv.io.dma_axi.aw.bits.id <= io.dma_brg.aw.bits.id @[quasar_wrapper.scala 108:22]
|
||||
swerv.io.dma_axi.aw.valid <= io.dma_brg.aw.valid @[quasar_wrapper.scala 108:22]
|
||||
io.dma_brg.aw.ready <= swerv.io.dma_axi.aw.ready @[quasar_wrapper.scala 108:22]
|
||||
swerv.io.dbg_rst_l <= io.dbg_rst_l @[quasar_wrapper.scala 122:22]
|
||||
swerv.io.rst_vec <= io.rst_vec @[quasar_wrapper.scala 123:20]
|
||||
swerv.io.nmi_int <= io.nmi_int @[quasar_wrapper.scala 124:20]
|
||||
swerv.io.nmi_vec <= io.nmi_vec @[quasar_wrapper.scala 125:20]
|
||||
swerv.io.i_cpu_halt_req <= io.i_cpu_halt_req @[quasar_wrapper.scala 128:27]
|
||||
swerv.io.i_cpu_run_req <= io.i_cpu_run_req @[quasar_wrapper.scala 129:26]
|
||||
swerv.io.core_id <= io.core_id @[quasar_wrapper.scala 130:20]
|
||||
swerv.io.mpc_debug_halt_req <= io.mpc_debug_halt_req @[quasar_wrapper.scala 133:31]
|
||||
swerv.io.mpc_debug_run_req <= io.mpc_debug_run_req @[quasar_wrapper.scala 134:30]
|
||||
swerv.io.mpc_reset_run_req <= io.mpc_reset_run_req @[quasar_wrapper.scala 135:30]
|
||||
swerv.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[quasar_wrapper.scala 137:27]
|
||||
swerv.io.ifu_bus_clk_en <= io.ifu_bus_clk_en @[quasar_wrapper.scala 138:27]
|
||||
swerv.io.dbg_bus_clk_en <= io.dbg_bus_clk_en @[quasar_wrapper.scala 139:27]
|
||||
swerv.io.dma_bus_clk_en <= io.dma_bus_clk_en @[quasar_wrapper.scala 140:27]
|
||||
swerv.io.timer_int <= io.timer_int @[quasar_wrapper.scala 142:22]
|
||||
swerv.io.soft_int <= io.soft_int @[quasar_wrapper.scala 143:21]
|
||||
swerv.io.extintsrc_req <= io.extintsrc_req @[quasar_wrapper.scala 144:26]
|
||||
io.rv_trace_pkt.rv_i_tval_ip <= swerv.io.rv_trace_pkt.rv_i_tval_ip @[quasar_wrapper.scala 148:19]
|
||||
io.rv_trace_pkt.rv_i_interrupt_ip <= swerv.io.rv_trace_pkt.rv_i_interrupt_ip @[quasar_wrapper.scala 148:19]
|
||||
io.rv_trace_pkt.rv_i_ecause_ip <= swerv.io.rv_trace_pkt.rv_i_ecause_ip @[quasar_wrapper.scala 148:19]
|
||||
io.rv_trace_pkt.rv_i_exception_ip <= swerv.io.rv_trace_pkt.rv_i_exception_ip @[quasar_wrapper.scala 148:19]
|
||||
io.rv_trace_pkt.rv_i_address_ip <= swerv.io.rv_trace_pkt.rv_i_address_ip @[quasar_wrapper.scala 148:19]
|
||||
io.rv_trace_pkt.rv_i_insn_ip <= swerv.io.rv_trace_pkt.rv_i_insn_ip @[quasar_wrapper.scala 148:19]
|
||||
io.rv_trace_pkt.rv_i_valid_ip <= swerv.io.rv_trace_pkt.rv_i_valid_ip @[quasar_wrapper.scala 148:19]
|
||||
io.o_cpu_halt_ack <= swerv.io.o_cpu_halt_ack @[quasar_wrapper.scala 151:21]
|
||||
io.o_cpu_halt_status <= swerv.io.o_cpu_halt_status @[quasar_wrapper.scala 152:24]
|
||||
io.o_cpu_run_ack <= swerv.io.o_cpu_run_ack @[quasar_wrapper.scala 153:20]
|
||||
io.o_debug_mode_status <= swerv.io.o_debug_mode_status @[quasar_wrapper.scala 154:26]
|
||||
io.mpc_debug_halt_ack <= swerv.io.mpc_debug_halt_ack @[quasar_wrapper.scala 156:25]
|
||||
io.mpc_debug_run_ack <= swerv.io.mpc_debug_run_ack @[quasar_wrapper.scala 157:24]
|
||||
io.debug_brkpt_status <= swerv.io.debug_brkpt_status @[quasar_wrapper.scala 158:25]
|
||||
io.dec_tlu_perfcnt0 <= swerv.io.dec_tlu_perfcnt0 @[quasar_wrapper.scala 160:23]
|
||||
io.dec_tlu_perfcnt1 <= swerv.io.dec_tlu_perfcnt1 @[quasar_wrapper.scala 161:23]
|
||||
io.dec_tlu_perfcnt2 <= swerv.io.dec_tlu_perfcnt2 @[quasar_wrapper.scala 162:23]
|
||||
io.dec_tlu_perfcnt3 <= swerv.io.dec_tlu_perfcnt3 @[quasar_wrapper.scala 163:23]
|
||||
|
||||
|
|
|
|||
450
quasar_wrapper.v
450
quasar_wrapper.v
|
|
@ -84235,231 +84235,231 @@ module quasar_wrapper(
|
|||
.io_soft_int(swerv_io_soft_int),
|
||||
.io_scan_mode(swerv_io_scan_mode)
|
||||
);
|
||||
assign io_lsu_brg_aw_valid = swerv_io_lsu_axi_aw_valid; // @[quasar_wrapper.scala 129:20]
|
||||
assign io_lsu_brg_aw_bits_id = swerv_io_lsu_axi_aw_bits_id; // @[quasar_wrapper.scala 129:20]
|
||||
assign io_lsu_brg_aw_bits_addr = swerv_io_lsu_axi_aw_bits_addr; // @[quasar_wrapper.scala 129:20]
|
||||
assign io_lsu_brg_aw_bits_region = swerv_io_lsu_axi_aw_bits_region; // @[quasar_wrapper.scala 129:20]
|
||||
assign io_lsu_brg_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 129:20]
|
||||
assign io_lsu_brg_aw_bits_size = swerv_io_lsu_axi_aw_bits_size; // @[quasar_wrapper.scala 129:20]
|
||||
assign io_lsu_brg_aw_bits_burst = 2'h1; // @[quasar_wrapper.scala 129:20]
|
||||
assign io_lsu_brg_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 129:20]
|
||||
assign io_lsu_brg_aw_bits_cache = swerv_io_lsu_axi_aw_bits_cache; // @[quasar_wrapper.scala 129:20]
|
||||
assign io_lsu_brg_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 129:20]
|
||||
assign io_lsu_brg_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 129:20]
|
||||
assign io_lsu_brg_w_valid = swerv_io_lsu_axi_w_valid; // @[quasar_wrapper.scala 129:20]
|
||||
assign io_lsu_brg_w_bits_data = swerv_io_lsu_axi_w_bits_data; // @[quasar_wrapper.scala 129:20]
|
||||
assign io_lsu_brg_w_bits_strb = swerv_io_lsu_axi_w_bits_strb; // @[quasar_wrapper.scala 129:20]
|
||||
assign io_lsu_brg_w_bits_last = 1'h1; // @[quasar_wrapper.scala 129:20]
|
||||
assign io_lsu_brg_b_ready = 1'h1; // @[quasar_wrapper.scala 129:20]
|
||||
assign io_lsu_brg_ar_valid = swerv_io_lsu_axi_ar_valid; // @[quasar_wrapper.scala 129:20]
|
||||
assign io_lsu_brg_ar_bits_id = swerv_io_lsu_axi_ar_bits_id; // @[quasar_wrapper.scala 129:20]
|
||||
assign io_lsu_brg_ar_bits_addr = swerv_io_lsu_axi_ar_bits_addr; // @[quasar_wrapper.scala 129:20]
|
||||
assign io_lsu_brg_ar_bits_region = swerv_io_lsu_axi_ar_bits_region; // @[quasar_wrapper.scala 129:20]
|
||||
assign io_lsu_brg_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 129:20]
|
||||
assign io_lsu_brg_ar_bits_size = swerv_io_lsu_axi_ar_bits_size; // @[quasar_wrapper.scala 129:20]
|
||||
assign io_lsu_brg_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 129:20]
|
||||
assign io_lsu_brg_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 129:20]
|
||||
assign io_lsu_brg_ar_bits_cache = swerv_io_lsu_axi_ar_bits_cache; // @[quasar_wrapper.scala 129:20]
|
||||
assign io_lsu_brg_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 129:20]
|
||||
assign io_lsu_brg_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 129:20]
|
||||
assign io_lsu_brg_r_ready = 1'h1; // @[quasar_wrapper.scala 129:20]
|
||||
assign io_ifu_brg_aw_valid = 1'h0; // @[quasar_wrapper.scala 132:20]
|
||||
assign io_ifu_brg_aw_bits_id = 3'h0; // @[quasar_wrapper.scala 132:20]
|
||||
assign io_ifu_brg_aw_bits_addr = 32'h0; // @[quasar_wrapper.scala 132:20]
|
||||
assign io_ifu_brg_aw_bits_region = 4'h0; // @[quasar_wrapper.scala 132:20]
|
||||
assign io_ifu_brg_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 132:20]
|
||||
assign io_ifu_brg_aw_bits_size = 3'h0; // @[quasar_wrapper.scala 132:20]
|
||||
assign io_ifu_brg_aw_bits_burst = 2'h0; // @[quasar_wrapper.scala 132:20]
|
||||
assign io_ifu_brg_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 132:20]
|
||||
assign io_ifu_brg_aw_bits_cache = 4'h0; // @[quasar_wrapper.scala 132:20]
|
||||
assign io_ifu_brg_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 132:20]
|
||||
assign io_ifu_brg_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 132:20]
|
||||
assign io_ifu_brg_w_valid = 1'h0; // @[quasar_wrapper.scala 132:20]
|
||||
assign io_ifu_brg_w_bits_data = 64'h0; // @[quasar_wrapper.scala 132:20]
|
||||
assign io_ifu_brg_w_bits_strb = 8'h0; // @[quasar_wrapper.scala 132:20]
|
||||
assign io_ifu_brg_w_bits_last = 1'h0; // @[quasar_wrapper.scala 132:20]
|
||||
assign io_ifu_brg_b_ready = 1'h0; // @[quasar_wrapper.scala 132:20]
|
||||
assign io_ifu_brg_ar_valid = swerv_io_ifu_axi_ar_valid; // @[quasar_wrapper.scala 132:20]
|
||||
assign io_ifu_brg_ar_bits_id = swerv_io_ifu_axi_ar_bits_id; // @[quasar_wrapper.scala 132:20]
|
||||
assign io_ifu_brg_ar_bits_addr = swerv_io_ifu_axi_ar_bits_addr; // @[quasar_wrapper.scala 132:20]
|
||||
assign io_ifu_brg_ar_bits_region = swerv_io_ifu_axi_ar_bits_region; // @[quasar_wrapper.scala 132:20]
|
||||
assign io_ifu_brg_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 132:20]
|
||||
assign io_ifu_brg_ar_bits_size = 3'h3; // @[quasar_wrapper.scala 132:20]
|
||||
assign io_ifu_brg_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 132:20]
|
||||
assign io_ifu_brg_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 132:20]
|
||||
assign io_ifu_brg_ar_bits_cache = 4'hf; // @[quasar_wrapper.scala 132:20]
|
||||
assign io_ifu_brg_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 132:20]
|
||||
assign io_ifu_brg_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 132:20]
|
||||
assign io_ifu_brg_r_ready = 1'h1; // @[quasar_wrapper.scala 132:20]
|
||||
assign io_sb_brg_aw_valid = swerv_io_sb_axi_aw_valid; // @[quasar_wrapper.scala 135:19]
|
||||
assign io_sb_brg_aw_bits_id = 1'h0; // @[quasar_wrapper.scala 135:19]
|
||||
assign io_sb_brg_aw_bits_addr = swerv_io_sb_axi_aw_bits_addr; // @[quasar_wrapper.scala 135:19]
|
||||
assign io_sb_brg_aw_bits_region = swerv_io_sb_axi_aw_bits_region; // @[quasar_wrapper.scala 135:19]
|
||||
assign io_sb_brg_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 135:19]
|
||||
assign io_sb_brg_aw_bits_size = swerv_io_sb_axi_aw_bits_size; // @[quasar_wrapper.scala 135:19]
|
||||
assign io_sb_brg_aw_bits_burst = 2'h1; // @[quasar_wrapper.scala 135:19]
|
||||
assign io_sb_brg_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 135:19]
|
||||
assign io_sb_brg_aw_bits_cache = 4'hf; // @[quasar_wrapper.scala 135:19]
|
||||
assign io_sb_brg_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 135:19]
|
||||
assign io_sb_brg_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 135:19]
|
||||
assign io_sb_brg_w_valid = swerv_io_sb_axi_w_valid; // @[quasar_wrapper.scala 135:19]
|
||||
assign io_sb_brg_w_bits_data = swerv_io_sb_axi_w_bits_data; // @[quasar_wrapper.scala 135:19]
|
||||
assign io_sb_brg_w_bits_strb = swerv_io_sb_axi_w_bits_strb; // @[quasar_wrapper.scala 135:19]
|
||||
assign io_sb_brg_w_bits_last = 1'h1; // @[quasar_wrapper.scala 135:19]
|
||||
assign io_sb_brg_b_ready = 1'h1; // @[quasar_wrapper.scala 135:19]
|
||||
assign io_sb_brg_ar_valid = swerv_io_sb_axi_ar_valid; // @[quasar_wrapper.scala 135:19]
|
||||
assign io_sb_brg_ar_bits_id = 1'h0; // @[quasar_wrapper.scala 135:19]
|
||||
assign io_sb_brg_ar_bits_addr = swerv_io_sb_axi_ar_bits_addr; // @[quasar_wrapper.scala 135:19]
|
||||
assign io_sb_brg_ar_bits_region = swerv_io_sb_axi_ar_bits_region; // @[quasar_wrapper.scala 135:19]
|
||||
assign io_sb_brg_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 135:19]
|
||||
assign io_sb_brg_ar_bits_size = swerv_io_sb_axi_ar_bits_size; // @[quasar_wrapper.scala 135:19]
|
||||
assign io_sb_brg_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 135:19]
|
||||
assign io_sb_brg_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 135:19]
|
||||
assign io_sb_brg_ar_bits_cache = 4'h0; // @[quasar_wrapper.scala 135:19]
|
||||
assign io_sb_brg_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 135:19]
|
||||
assign io_sb_brg_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 135:19]
|
||||
assign io_sb_brg_r_ready = 1'h1; // @[quasar_wrapper.scala 135:19]
|
||||
assign io_dma_brg_aw_ready = swerv_io_dma_axi_aw_ready; // @[quasar_wrapper.scala 139:20]
|
||||
assign io_dma_brg_w_ready = swerv_io_dma_axi_w_ready; // @[quasar_wrapper.scala 139:20]
|
||||
assign io_dma_brg_b_valid = swerv_io_dma_axi_b_valid; // @[quasar_wrapper.scala 139:20]
|
||||
assign io_dma_brg_b_bits_resp = swerv_io_dma_axi_b_bits_resp; // @[quasar_wrapper.scala 139:20]
|
||||
assign io_dma_brg_b_bits_id = swerv_io_dma_axi_b_bits_id; // @[quasar_wrapper.scala 139:20]
|
||||
assign io_dma_brg_ar_ready = swerv_io_dma_axi_ar_ready; // @[quasar_wrapper.scala 139:20]
|
||||
assign io_dma_brg_r_valid = swerv_io_dma_axi_r_valid; // @[quasar_wrapper.scala 139:20]
|
||||
assign io_dma_brg_r_bits_id = swerv_io_dma_axi_r_bits_id; // @[quasar_wrapper.scala 139:20]
|
||||
assign io_dma_brg_r_bits_data = swerv_io_dma_axi_r_bits_data; // @[quasar_wrapper.scala 139:20]
|
||||
assign io_dma_brg_r_bits_resp = swerv_io_dma_axi_r_bits_resp; // @[quasar_wrapper.scala 139:20]
|
||||
assign io_dma_brg_r_bits_last = 1'h1; // @[quasar_wrapper.scala 139:20]
|
||||
assign io_dec_tlu_perfcnt0 = swerv_io_dec_tlu_perfcnt0; // @[quasar_wrapper.scala 178:23]
|
||||
assign io_dec_tlu_perfcnt1 = swerv_io_dec_tlu_perfcnt1; // @[quasar_wrapper.scala 179:23]
|
||||
assign io_dec_tlu_perfcnt2 = swerv_io_dec_tlu_perfcnt2; // @[quasar_wrapper.scala 180:23]
|
||||
assign io_dec_tlu_perfcnt3 = swerv_io_dec_tlu_perfcnt3; // @[quasar_wrapper.scala 181:23]
|
||||
assign io_jtag_tdo = dmi_wrapper_tdo; // @[quasar_wrapper.scala 81:15]
|
||||
assign io_mpc_debug_halt_ack = swerv_io_mpc_debug_halt_ack; // @[quasar_wrapper.scala 174:25]
|
||||
assign io_mpc_debug_run_ack = swerv_io_mpc_debug_run_ack; // @[quasar_wrapper.scala 175:24]
|
||||
assign io_debug_brkpt_status = swerv_io_debug_brkpt_status; // @[quasar_wrapper.scala 176:25]
|
||||
assign io_o_cpu_halt_ack = swerv_io_o_cpu_halt_ack; // @[quasar_wrapper.scala 169:21]
|
||||
assign io_o_cpu_halt_status = swerv_io_o_cpu_halt_status; // @[quasar_wrapper.scala 170:24]
|
||||
assign io_o_debug_mode_status = swerv_io_o_debug_mode_status; // @[quasar_wrapper.scala 172:26]
|
||||
assign io_o_cpu_run_ack = swerv_io_o_cpu_run_ack; // @[quasar_wrapper.scala 171:20]
|
||||
assign io_rv_trace_pkt_rv_i_valid_ip = swerv_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar_wrapper.scala 166:19]
|
||||
assign io_rv_trace_pkt_rv_i_insn_ip = swerv_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar_wrapper.scala 166:19]
|
||||
assign io_rv_trace_pkt_rv_i_address_ip = swerv_io_rv_trace_pkt_rv_i_address_ip; // @[quasar_wrapper.scala 166:19]
|
||||
assign io_rv_trace_pkt_rv_i_exception_ip = swerv_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar_wrapper.scala 166:19]
|
||||
assign io_rv_trace_pkt_rv_i_ecause_ip = swerv_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar_wrapper.scala 166:19]
|
||||
assign io_rv_trace_pkt_rv_i_interrupt_ip = swerv_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar_wrapper.scala 166:19]
|
||||
assign io_rv_trace_pkt_rv_i_tval_ip = swerv_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar_wrapper.scala 166:19]
|
||||
assign mem_clk = clock; // @[quasar_wrapper.scala 89:14]
|
||||
assign mem_rst_l = reset; // @[quasar_wrapper.scala 88:16]
|
||||
assign mem_dccm_clk_override = swerv_io_dccm_clk_override; // @[quasar_wrapper.scala 84:28]
|
||||
assign mem_icm_clk_override = swerv_io_icm_clk_override; // @[quasar_wrapper.scala 85:27]
|
||||
assign mem_dec_tlu_core_ecc_disable = swerv_io_dec_tlu_core_ecc_disable; // @[quasar_wrapper.scala 86:35]
|
||||
assign mem_dccm_wren = swerv_io_dccm_wren; // @[quasar_wrapper.scala 87:15]
|
||||
assign mem_dccm_rden = swerv_io_dccm_rden; // @[quasar_wrapper.scala 87:15]
|
||||
assign mem_dccm_wr_addr_lo = swerv_io_dccm_wr_addr_lo; // @[quasar_wrapper.scala 87:15]
|
||||
assign mem_dccm_wr_addr_hi = swerv_io_dccm_wr_addr_hi; // @[quasar_wrapper.scala 87:15]
|
||||
assign mem_dccm_rd_addr_lo = swerv_io_dccm_rd_addr_lo; // @[quasar_wrapper.scala 87:15]
|
||||
assign mem_dccm_rd_addr_hi = swerv_io_dccm_rd_addr_hi; // @[quasar_wrapper.scala 87:15]
|
||||
assign mem_dccm_wr_data_lo = swerv_io_dccm_wr_data_lo; // @[quasar_wrapper.scala 87:15]
|
||||
assign mem_dccm_wr_data_hi = swerv_io_dccm_wr_data_hi; // @[quasar_wrapper.scala 87:15]
|
||||
assign mem_iccm_rw_addr = swerv_io_iccm_rw_addr; // @[quasar_wrapper.scala 94:17]
|
||||
assign mem_iccm_buf_correct_ecc = swerv_io_iccm_buf_correct_ecc; // @[quasar_wrapper.scala 94:17]
|
||||
assign mem_iccm_correction_state = swerv_io_iccm_correction_state; // @[quasar_wrapper.scala 94:17]
|
||||
assign mem_iccm_wren = swerv_io_iccm_wren; // @[quasar_wrapper.scala 94:17]
|
||||
assign mem_iccm_rden = swerv_io_iccm_rden; // @[quasar_wrapper.scala 94:17]
|
||||
assign mem_iccm_wr_size = swerv_io_iccm_wr_size; // @[quasar_wrapper.scala 94:17]
|
||||
assign mem_iccm_wr_data = swerv_io_iccm_wr_data; // @[quasar_wrapper.scala 94:17]
|
||||
assign mem_ic_rw_addr = swerv_io_ic_rw_addr; // @[quasar_wrapper.scala 93:15]
|
||||
assign mem_ic_tag_valid = swerv_io_ic_tag_valid; // @[quasar_wrapper.scala 93:15]
|
||||
assign mem_ic_wr_en = swerv_io_ic_wr_en; // @[quasar_wrapper.scala 93:15]
|
||||
assign mem_ic_rd_en = swerv_io_ic_rd_en; // @[quasar_wrapper.scala 93:15]
|
||||
assign mem_ic_wr_data_0 = swerv_io_ic_wr_data_0; // @[quasar_wrapper.scala 93:15]
|
||||
assign mem_ic_wr_data_1 = swerv_io_ic_wr_data_1; // @[quasar_wrapper.scala 93:15]
|
||||
assign mem_ic_debug_wr_data = swerv_io_ic_debug_wr_data; // @[quasar_wrapper.scala 93:15]
|
||||
assign mem_ic_debug_addr = swerv_io_ic_debug_addr; // @[quasar_wrapper.scala 93:15]
|
||||
assign mem_ic_debug_rd_en = swerv_io_ic_debug_rd_en; // @[quasar_wrapper.scala 93:15]
|
||||
assign mem_ic_debug_wr_en = swerv_io_ic_debug_wr_en; // @[quasar_wrapper.scala 93:15]
|
||||
assign mem_ic_debug_tag_array = swerv_io_ic_debug_tag_array; // @[quasar_wrapper.scala 93:15]
|
||||
assign mem_ic_debug_way = swerv_io_ic_debug_way; // @[quasar_wrapper.scala 93:15]
|
||||
assign mem_ic_premux_data = swerv_io_ic_premux_data; // @[quasar_wrapper.scala 93:15]
|
||||
assign mem_ic_sel_premux_data = swerv_io_ic_sel_premux_data; // @[quasar_wrapper.scala 93:15]
|
||||
assign mem_scan_mode = io_scan_mode; // @[quasar_wrapper.scala 90:20]
|
||||
assign dmi_wrapper_trst_n = io_jtag_trst_n; // @[quasar_wrapper.scala 66:25]
|
||||
assign dmi_wrapper_tck = io_jtag_tck; // @[quasar_wrapper.scala 67:22]
|
||||
assign dmi_wrapper_tms = io_jtag_tms; // @[quasar_wrapper.scala 68:22]
|
||||
assign dmi_wrapper_tdi = io_jtag_tdi; // @[quasar_wrapper.scala 69:22]
|
||||
assign dmi_wrapper_core_rst_n = io_dbg_rst_l; // @[quasar_wrapper.scala 75:29]
|
||||
assign dmi_wrapper_core_clk = clock; // @[quasar_wrapper.scala 70:27]
|
||||
assign dmi_wrapper_jtag_id = io_jtag_id; // @[quasar_wrapper.scala 71:26]
|
||||
assign dmi_wrapper_rd_data = 32'h0; // @[quasar_wrapper.scala 72:26]
|
||||
assign io_lsu_brg_aw_valid = swerv_io_lsu_axi_aw_valid; // @[quasar_wrapper.scala 105:22]
|
||||
assign io_lsu_brg_aw_bits_id = swerv_io_lsu_axi_aw_bits_id; // @[quasar_wrapper.scala 105:22]
|
||||
assign io_lsu_brg_aw_bits_addr = swerv_io_lsu_axi_aw_bits_addr; // @[quasar_wrapper.scala 105:22]
|
||||
assign io_lsu_brg_aw_bits_region = swerv_io_lsu_axi_aw_bits_region; // @[quasar_wrapper.scala 105:22]
|
||||
assign io_lsu_brg_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 105:22]
|
||||
assign io_lsu_brg_aw_bits_size = swerv_io_lsu_axi_aw_bits_size; // @[quasar_wrapper.scala 105:22]
|
||||
assign io_lsu_brg_aw_bits_burst = 2'h1; // @[quasar_wrapper.scala 105:22]
|
||||
assign io_lsu_brg_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 105:22]
|
||||
assign io_lsu_brg_aw_bits_cache = swerv_io_lsu_axi_aw_bits_cache; // @[quasar_wrapper.scala 105:22]
|
||||
assign io_lsu_brg_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 105:22]
|
||||
assign io_lsu_brg_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 105:22]
|
||||
assign io_lsu_brg_w_valid = swerv_io_lsu_axi_w_valid; // @[quasar_wrapper.scala 105:22]
|
||||
assign io_lsu_brg_w_bits_data = swerv_io_lsu_axi_w_bits_data; // @[quasar_wrapper.scala 105:22]
|
||||
assign io_lsu_brg_w_bits_strb = swerv_io_lsu_axi_w_bits_strb; // @[quasar_wrapper.scala 105:22]
|
||||
assign io_lsu_brg_w_bits_last = 1'h1; // @[quasar_wrapper.scala 105:22]
|
||||
assign io_lsu_brg_b_ready = 1'h1; // @[quasar_wrapper.scala 105:22]
|
||||
assign io_lsu_brg_ar_valid = swerv_io_lsu_axi_ar_valid; // @[quasar_wrapper.scala 105:22]
|
||||
assign io_lsu_brg_ar_bits_id = swerv_io_lsu_axi_ar_bits_id; // @[quasar_wrapper.scala 105:22]
|
||||
assign io_lsu_brg_ar_bits_addr = swerv_io_lsu_axi_ar_bits_addr; // @[quasar_wrapper.scala 105:22]
|
||||
assign io_lsu_brg_ar_bits_region = swerv_io_lsu_axi_ar_bits_region; // @[quasar_wrapper.scala 105:22]
|
||||
assign io_lsu_brg_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 105:22]
|
||||
assign io_lsu_brg_ar_bits_size = swerv_io_lsu_axi_ar_bits_size; // @[quasar_wrapper.scala 105:22]
|
||||
assign io_lsu_brg_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 105:22]
|
||||
assign io_lsu_brg_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 105:22]
|
||||
assign io_lsu_brg_ar_bits_cache = swerv_io_lsu_axi_ar_bits_cache; // @[quasar_wrapper.scala 105:22]
|
||||
assign io_lsu_brg_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 105:22]
|
||||
assign io_lsu_brg_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 105:22]
|
||||
assign io_lsu_brg_r_ready = 1'h1; // @[quasar_wrapper.scala 105:22]
|
||||
assign io_ifu_brg_aw_valid = 1'h0; // @[quasar_wrapper.scala 106:22]
|
||||
assign io_ifu_brg_aw_bits_id = 3'h0; // @[quasar_wrapper.scala 106:22]
|
||||
assign io_ifu_brg_aw_bits_addr = 32'h0; // @[quasar_wrapper.scala 106:22]
|
||||
assign io_ifu_brg_aw_bits_region = 4'h0; // @[quasar_wrapper.scala 106:22]
|
||||
assign io_ifu_brg_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 106:22]
|
||||
assign io_ifu_brg_aw_bits_size = 3'h0; // @[quasar_wrapper.scala 106:22]
|
||||
assign io_ifu_brg_aw_bits_burst = 2'h0; // @[quasar_wrapper.scala 106:22]
|
||||
assign io_ifu_brg_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 106:22]
|
||||
assign io_ifu_brg_aw_bits_cache = 4'h0; // @[quasar_wrapper.scala 106:22]
|
||||
assign io_ifu_brg_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 106:22]
|
||||
assign io_ifu_brg_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 106:22]
|
||||
assign io_ifu_brg_w_valid = 1'h0; // @[quasar_wrapper.scala 106:22]
|
||||
assign io_ifu_brg_w_bits_data = 64'h0; // @[quasar_wrapper.scala 106:22]
|
||||
assign io_ifu_brg_w_bits_strb = 8'h0; // @[quasar_wrapper.scala 106:22]
|
||||
assign io_ifu_brg_w_bits_last = 1'h0; // @[quasar_wrapper.scala 106:22]
|
||||
assign io_ifu_brg_b_ready = 1'h0; // @[quasar_wrapper.scala 106:22]
|
||||
assign io_ifu_brg_ar_valid = swerv_io_ifu_axi_ar_valid; // @[quasar_wrapper.scala 106:22]
|
||||
assign io_ifu_brg_ar_bits_id = swerv_io_ifu_axi_ar_bits_id; // @[quasar_wrapper.scala 106:22]
|
||||
assign io_ifu_brg_ar_bits_addr = swerv_io_ifu_axi_ar_bits_addr; // @[quasar_wrapper.scala 106:22]
|
||||
assign io_ifu_brg_ar_bits_region = swerv_io_ifu_axi_ar_bits_region; // @[quasar_wrapper.scala 106:22]
|
||||
assign io_ifu_brg_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 106:22]
|
||||
assign io_ifu_brg_ar_bits_size = 3'h3; // @[quasar_wrapper.scala 106:22]
|
||||
assign io_ifu_brg_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 106:22]
|
||||
assign io_ifu_brg_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 106:22]
|
||||
assign io_ifu_brg_ar_bits_cache = 4'hf; // @[quasar_wrapper.scala 106:22]
|
||||
assign io_ifu_brg_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 106:22]
|
||||
assign io_ifu_brg_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 106:22]
|
||||
assign io_ifu_brg_r_ready = 1'h1; // @[quasar_wrapper.scala 106:22]
|
||||
assign io_sb_brg_aw_valid = swerv_io_sb_axi_aw_valid; // @[quasar_wrapper.scala 107:21]
|
||||
assign io_sb_brg_aw_bits_id = 1'h0; // @[quasar_wrapper.scala 107:21]
|
||||
assign io_sb_brg_aw_bits_addr = swerv_io_sb_axi_aw_bits_addr; // @[quasar_wrapper.scala 107:21]
|
||||
assign io_sb_brg_aw_bits_region = swerv_io_sb_axi_aw_bits_region; // @[quasar_wrapper.scala 107:21]
|
||||
assign io_sb_brg_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 107:21]
|
||||
assign io_sb_brg_aw_bits_size = swerv_io_sb_axi_aw_bits_size; // @[quasar_wrapper.scala 107:21]
|
||||
assign io_sb_brg_aw_bits_burst = 2'h1; // @[quasar_wrapper.scala 107:21]
|
||||
assign io_sb_brg_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 107:21]
|
||||
assign io_sb_brg_aw_bits_cache = 4'hf; // @[quasar_wrapper.scala 107:21]
|
||||
assign io_sb_brg_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 107:21]
|
||||
assign io_sb_brg_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 107:21]
|
||||
assign io_sb_brg_w_valid = swerv_io_sb_axi_w_valid; // @[quasar_wrapper.scala 107:21]
|
||||
assign io_sb_brg_w_bits_data = swerv_io_sb_axi_w_bits_data; // @[quasar_wrapper.scala 107:21]
|
||||
assign io_sb_brg_w_bits_strb = swerv_io_sb_axi_w_bits_strb; // @[quasar_wrapper.scala 107:21]
|
||||
assign io_sb_brg_w_bits_last = 1'h1; // @[quasar_wrapper.scala 107:21]
|
||||
assign io_sb_brg_b_ready = 1'h1; // @[quasar_wrapper.scala 107:21]
|
||||
assign io_sb_brg_ar_valid = swerv_io_sb_axi_ar_valid; // @[quasar_wrapper.scala 107:21]
|
||||
assign io_sb_brg_ar_bits_id = 1'h0; // @[quasar_wrapper.scala 107:21]
|
||||
assign io_sb_brg_ar_bits_addr = swerv_io_sb_axi_ar_bits_addr; // @[quasar_wrapper.scala 107:21]
|
||||
assign io_sb_brg_ar_bits_region = swerv_io_sb_axi_ar_bits_region; // @[quasar_wrapper.scala 107:21]
|
||||
assign io_sb_brg_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 107:21]
|
||||
assign io_sb_brg_ar_bits_size = swerv_io_sb_axi_ar_bits_size; // @[quasar_wrapper.scala 107:21]
|
||||
assign io_sb_brg_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 107:21]
|
||||
assign io_sb_brg_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 107:21]
|
||||
assign io_sb_brg_ar_bits_cache = 4'h0; // @[quasar_wrapper.scala 107:21]
|
||||
assign io_sb_brg_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 107:21]
|
||||
assign io_sb_brg_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 107:21]
|
||||
assign io_sb_brg_r_ready = 1'h1; // @[quasar_wrapper.scala 107:21]
|
||||
assign io_dma_brg_aw_ready = swerv_io_dma_axi_aw_ready; // @[quasar_wrapper.scala 108:22]
|
||||
assign io_dma_brg_w_ready = swerv_io_dma_axi_w_ready; // @[quasar_wrapper.scala 108:22]
|
||||
assign io_dma_brg_b_valid = swerv_io_dma_axi_b_valid; // @[quasar_wrapper.scala 108:22]
|
||||
assign io_dma_brg_b_bits_resp = swerv_io_dma_axi_b_bits_resp; // @[quasar_wrapper.scala 108:22]
|
||||
assign io_dma_brg_b_bits_id = swerv_io_dma_axi_b_bits_id; // @[quasar_wrapper.scala 108:22]
|
||||
assign io_dma_brg_ar_ready = swerv_io_dma_axi_ar_ready; // @[quasar_wrapper.scala 108:22]
|
||||
assign io_dma_brg_r_valid = swerv_io_dma_axi_r_valid; // @[quasar_wrapper.scala 108:22]
|
||||
assign io_dma_brg_r_bits_id = swerv_io_dma_axi_r_bits_id; // @[quasar_wrapper.scala 108:22]
|
||||
assign io_dma_brg_r_bits_data = swerv_io_dma_axi_r_bits_data; // @[quasar_wrapper.scala 108:22]
|
||||
assign io_dma_brg_r_bits_resp = swerv_io_dma_axi_r_bits_resp; // @[quasar_wrapper.scala 108:22]
|
||||
assign io_dma_brg_r_bits_last = 1'h1; // @[quasar_wrapper.scala 108:22]
|
||||
assign io_dec_tlu_perfcnt0 = swerv_io_dec_tlu_perfcnt0; // @[quasar_wrapper.scala 160:23]
|
||||
assign io_dec_tlu_perfcnt1 = swerv_io_dec_tlu_perfcnt1; // @[quasar_wrapper.scala 161:23]
|
||||
assign io_dec_tlu_perfcnt2 = swerv_io_dec_tlu_perfcnt2; // @[quasar_wrapper.scala 162:23]
|
||||
assign io_dec_tlu_perfcnt3 = swerv_io_dec_tlu_perfcnt3; // @[quasar_wrapper.scala 163:23]
|
||||
assign io_jtag_tdo = dmi_wrapper_tdo; // @[quasar_wrapper.scala 82:15]
|
||||
assign io_mpc_debug_halt_ack = swerv_io_mpc_debug_halt_ack; // @[quasar_wrapper.scala 156:25]
|
||||
assign io_mpc_debug_run_ack = swerv_io_mpc_debug_run_ack; // @[quasar_wrapper.scala 157:24]
|
||||
assign io_debug_brkpt_status = swerv_io_debug_brkpt_status; // @[quasar_wrapper.scala 158:25]
|
||||
assign io_o_cpu_halt_ack = swerv_io_o_cpu_halt_ack; // @[quasar_wrapper.scala 151:21]
|
||||
assign io_o_cpu_halt_status = swerv_io_o_cpu_halt_status; // @[quasar_wrapper.scala 152:24]
|
||||
assign io_o_debug_mode_status = swerv_io_o_debug_mode_status; // @[quasar_wrapper.scala 154:26]
|
||||
assign io_o_cpu_run_ack = swerv_io_o_cpu_run_ack; // @[quasar_wrapper.scala 153:20]
|
||||
assign io_rv_trace_pkt_rv_i_valid_ip = swerv_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar_wrapper.scala 148:19]
|
||||
assign io_rv_trace_pkt_rv_i_insn_ip = swerv_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar_wrapper.scala 148:19]
|
||||
assign io_rv_trace_pkt_rv_i_address_ip = swerv_io_rv_trace_pkt_rv_i_address_ip; // @[quasar_wrapper.scala 148:19]
|
||||
assign io_rv_trace_pkt_rv_i_exception_ip = swerv_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar_wrapper.scala 148:19]
|
||||
assign io_rv_trace_pkt_rv_i_ecause_ip = swerv_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar_wrapper.scala 148:19]
|
||||
assign io_rv_trace_pkt_rv_i_interrupt_ip = swerv_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar_wrapper.scala 148:19]
|
||||
assign io_rv_trace_pkt_rv_i_tval_ip = swerv_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar_wrapper.scala 148:19]
|
||||
assign mem_clk = clock; // @[quasar_wrapper.scala 90:14]
|
||||
assign mem_rst_l = reset; // @[quasar_wrapper.scala 89:16]
|
||||
assign mem_dccm_clk_override = swerv_io_dccm_clk_override; // @[quasar_wrapper.scala 85:28]
|
||||
assign mem_icm_clk_override = swerv_io_icm_clk_override; // @[quasar_wrapper.scala 86:27]
|
||||
assign mem_dec_tlu_core_ecc_disable = swerv_io_dec_tlu_core_ecc_disable; // @[quasar_wrapper.scala 87:35]
|
||||
assign mem_dccm_wren = swerv_io_dccm_wren; // @[quasar_wrapper.scala 88:15]
|
||||
assign mem_dccm_rden = swerv_io_dccm_rden; // @[quasar_wrapper.scala 88:15]
|
||||
assign mem_dccm_wr_addr_lo = swerv_io_dccm_wr_addr_lo; // @[quasar_wrapper.scala 88:15]
|
||||
assign mem_dccm_wr_addr_hi = swerv_io_dccm_wr_addr_hi; // @[quasar_wrapper.scala 88:15]
|
||||
assign mem_dccm_rd_addr_lo = swerv_io_dccm_rd_addr_lo; // @[quasar_wrapper.scala 88:15]
|
||||
assign mem_dccm_rd_addr_hi = swerv_io_dccm_rd_addr_hi; // @[quasar_wrapper.scala 88:15]
|
||||
assign mem_dccm_wr_data_lo = swerv_io_dccm_wr_data_lo; // @[quasar_wrapper.scala 88:15]
|
||||
assign mem_dccm_wr_data_hi = swerv_io_dccm_wr_data_hi; // @[quasar_wrapper.scala 88:15]
|
||||
assign mem_iccm_rw_addr = swerv_io_iccm_rw_addr; // @[quasar_wrapper.scala 95:17]
|
||||
assign mem_iccm_buf_correct_ecc = swerv_io_iccm_buf_correct_ecc; // @[quasar_wrapper.scala 95:17]
|
||||
assign mem_iccm_correction_state = swerv_io_iccm_correction_state; // @[quasar_wrapper.scala 95:17]
|
||||
assign mem_iccm_wren = swerv_io_iccm_wren; // @[quasar_wrapper.scala 95:17]
|
||||
assign mem_iccm_rden = swerv_io_iccm_rden; // @[quasar_wrapper.scala 95:17]
|
||||
assign mem_iccm_wr_size = swerv_io_iccm_wr_size; // @[quasar_wrapper.scala 95:17]
|
||||
assign mem_iccm_wr_data = swerv_io_iccm_wr_data; // @[quasar_wrapper.scala 95:17]
|
||||
assign mem_ic_rw_addr = swerv_io_ic_rw_addr; // @[quasar_wrapper.scala 94:15]
|
||||
assign mem_ic_tag_valid = swerv_io_ic_tag_valid; // @[quasar_wrapper.scala 94:15]
|
||||
assign mem_ic_wr_en = swerv_io_ic_wr_en; // @[quasar_wrapper.scala 94:15]
|
||||
assign mem_ic_rd_en = swerv_io_ic_rd_en; // @[quasar_wrapper.scala 94:15]
|
||||
assign mem_ic_wr_data_0 = swerv_io_ic_wr_data_0; // @[quasar_wrapper.scala 94:15]
|
||||
assign mem_ic_wr_data_1 = swerv_io_ic_wr_data_1; // @[quasar_wrapper.scala 94:15]
|
||||
assign mem_ic_debug_wr_data = swerv_io_ic_debug_wr_data; // @[quasar_wrapper.scala 94:15]
|
||||
assign mem_ic_debug_addr = swerv_io_ic_debug_addr; // @[quasar_wrapper.scala 94:15]
|
||||
assign mem_ic_debug_rd_en = swerv_io_ic_debug_rd_en; // @[quasar_wrapper.scala 94:15]
|
||||
assign mem_ic_debug_wr_en = swerv_io_ic_debug_wr_en; // @[quasar_wrapper.scala 94:15]
|
||||
assign mem_ic_debug_tag_array = swerv_io_ic_debug_tag_array; // @[quasar_wrapper.scala 94:15]
|
||||
assign mem_ic_debug_way = swerv_io_ic_debug_way; // @[quasar_wrapper.scala 94:15]
|
||||
assign mem_ic_premux_data = swerv_io_ic_premux_data; // @[quasar_wrapper.scala 94:15]
|
||||
assign mem_ic_sel_premux_data = swerv_io_ic_sel_premux_data; // @[quasar_wrapper.scala 94:15]
|
||||
assign mem_scan_mode = io_scan_mode; // @[quasar_wrapper.scala 91:20]
|
||||
assign dmi_wrapper_trst_n = io_jtag_trst_n; // @[quasar_wrapper.scala 67:25]
|
||||
assign dmi_wrapper_tck = io_jtag_tck; // @[quasar_wrapper.scala 68:22]
|
||||
assign dmi_wrapper_tms = io_jtag_tms; // @[quasar_wrapper.scala 69:22]
|
||||
assign dmi_wrapper_tdi = io_jtag_tdi; // @[quasar_wrapper.scala 70:22]
|
||||
assign dmi_wrapper_core_rst_n = io_dbg_rst_l; // @[quasar_wrapper.scala 76:29]
|
||||
assign dmi_wrapper_core_clk = clock; // @[quasar_wrapper.scala 71:27]
|
||||
assign dmi_wrapper_jtag_id = io_jtag_id; // @[quasar_wrapper.scala 72:26]
|
||||
assign dmi_wrapper_rd_data = 32'h0; // @[quasar_wrapper.scala 73:26]
|
||||
assign swerv_clock = clock;
|
||||
assign swerv_reset = reset;
|
||||
assign swerv_io_lsu_axi_aw_ready = io_lsu_brg_aw_ready; // @[quasar_wrapper.scala 129:20]
|
||||
assign swerv_io_lsu_axi_w_ready = io_lsu_brg_w_ready; // @[quasar_wrapper.scala 129:20]
|
||||
assign swerv_io_lsu_axi_b_valid = io_lsu_brg_b_valid; // @[quasar_wrapper.scala 129:20]
|
||||
assign swerv_io_lsu_axi_b_bits_resp = io_lsu_brg_b_bits_resp; // @[quasar_wrapper.scala 129:20]
|
||||
assign swerv_io_lsu_axi_b_bits_id = io_lsu_brg_b_bits_id; // @[quasar_wrapper.scala 129:20]
|
||||
assign swerv_io_lsu_axi_ar_ready = io_lsu_brg_ar_ready; // @[quasar_wrapper.scala 129:20]
|
||||
assign swerv_io_lsu_axi_r_valid = io_lsu_brg_r_valid; // @[quasar_wrapper.scala 129:20]
|
||||
assign swerv_io_lsu_axi_r_bits_id = io_lsu_brg_r_bits_id; // @[quasar_wrapper.scala 129:20]
|
||||
assign swerv_io_lsu_axi_r_bits_data = io_lsu_brg_r_bits_data; // @[quasar_wrapper.scala 129:20]
|
||||
assign swerv_io_lsu_axi_r_bits_resp = io_lsu_brg_r_bits_resp; // @[quasar_wrapper.scala 129:20]
|
||||
assign swerv_io_ifu_axi_ar_ready = io_ifu_brg_ar_ready; // @[quasar_wrapper.scala 132:20]
|
||||
assign swerv_io_ifu_axi_r_valid = io_ifu_brg_r_valid; // @[quasar_wrapper.scala 132:20]
|
||||
assign swerv_io_ifu_axi_r_bits_id = io_ifu_brg_r_bits_id; // @[quasar_wrapper.scala 132:20]
|
||||
assign swerv_io_ifu_axi_r_bits_data = io_ifu_brg_r_bits_data; // @[quasar_wrapper.scala 132:20]
|
||||
assign swerv_io_ifu_axi_r_bits_resp = io_ifu_brg_r_bits_resp; // @[quasar_wrapper.scala 132:20]
|
||||
assign swerv_io_sb_axi_aw_ready = io_sb_brg_aw_ready; // @[quasar_wrapper.scala 135:19]
|
||||
assign swerv_io_sb_axi_w_ready = io_sb_brg_w_ready; // @[quasar_wrapper.scala 135:19]
|
||||
assign swerv_io_sb_axi_b_valid = io_sb_brg_b_valid; // @[quasar_wrapper.scala 135:19]
|
||||
assign swerv_io_sb_axi_b_bits_resp = io_sb_brg_b_bits_resp; // @[quasar_wrapper.scala 135:19]
|
||||
assign swerv_io_sb_axi_ar_ready = io_sb_brg_ar_ready; // @[quasar_wrapper.scala 135:19]
|
||||
assign swerv_io_sb_axi_r_valid = io_sb_brg_r_valid; // @[quasar_wrapper.scala 135:19]
|
||||
assign swerv_io_sb_axi_r_bits_data = io_sb_brg_r_bits_data; // @[quasar_wrapper.scala 135:19]
|
||||
assign swerv_io_sb_axi_r_bits_resp = io_sb_brg_r_bits_resp; // @[quasar_wrapper.scala 135:19]
|
||||
assign swerv_io_dma_axi_aw_valid = io_dma_brg_aw_valid; // @[quasar_wrapper.scala 139:20]
|
||||
assign swerv_io_dma_axi_aw_bits_id = io_dma_brg_aw_bits_id; // @[quasar_wrapper.scala 139:20]
|
||||
assign swerv_io_dma_axi_aw_bits_addr = io_dma_brg_aw_bits_addr; // @[quasar_wrapper.scala 139:20]
|
||||
assign swerv_io_dma_axi_aw_bits_size = io_dma_brg_aw_bits_size; // @[quasar_wrapper.scala 139:20]
|
||||
assign swerv_io_dma_axi_w_valid = io_dma_brg_w_valid; // @[quasar_wrapper.scala 139:20]
|
||||
assign swerv_io_dma_axi_w_bits_data = io_dma_brg_w_bits_data; // @[quasar_wrapper.scala 139:20]
|
||||
assign swerv_io_dma_axi_w_bits_strb = io_dma_brg_w_bits_strb; // @[quasar_wrapper.scala 139:20]
|
||||
assign swerv_io_dma_axi_b_ready = io_dma_brg_b_ready; // @[quasar_wrapper.scala 139:20]
|
||||
assign swerv_io_dma_axi_ar_valid = io_dma_brg_ar_valid; // @[quasar_wrapper.scala 139:20]
|
||||
assign swerv_io_dma_axi_ar_bits_id = io_dma_brg_ar_bits_id; // @[quasar_wrapper.scala 139:20]
|
||||
assign swerv_io_dma_axi_ar_bits_addr = io_dma_brg_ar_bits_addr; // @[quasar_wrapper.scala 139:20]
|
||||
assign swerv_io_dma_axi_ar_bits_size = io_dma_brg_ar_bits_size; // @[quasar_wrapper.scala 139:20]
|
||||
assign swerv_io_dma_axi_r_ready = io_dma_brg_r_ready; // @[quasar_wrapper.scala 139:20]
|
||||
assign swerv_io_dbg_rst_l = io_dbg_rst_l; // @[quasar_wrapper.scala 92:22 quasar_wrapper.scala 112:22]
|
||||
assign swerv_io_rst_vec = io_rst_vec; // @[quasar_wrapper.scala 113:20]
|
||||
assign swerv_io_nmi_int = io_nmi_int; // @[quasar_wrapper.scala 114:20]
|
||||
assign swerv_io_nmi_vec = io_nmi_vec; // @[quasar_wrapper.scala 115:20]
|
||||
assign swerv_io_i_cpu_halt_req = io_i_cpu_halt_req; // @[quasar_wrapper.scala 118:27]
|
||||
assign swerv_io_i_cpu_run_req = io_i_cpu_run_req; // @[quasar_wrapper.scala 119:26]
|
||||
assign swerv_io_core_id = io_core_id; // @[quasar_wrapper.scala 120:20]
|
||||
assign swerv_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[quasar_wrapper.scala 123:31]
|
||||
assign swerv_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[quasar_wrapper.scala 124:30]
|
||||
assign swerv_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[quasar_wrapper.scala 125:30]
|
||||
assign swerv_io_dccm_rd_data_lo = mem_dccm_rd_data_lo; // @[quasar_wrapper.scala 87:15]
|
||||
assign swerv_io_dccm_rd_data_hi = mem_dccm_rd_data_hi; // @[quasar_wrapper.scala 87:15]
|
||||
assign swerv_io_ic_rd_data = mem_ic_rd_data; // @[quasar_wrapper.scala 93:15]
|
||||
assign swerv_io_ic_debug_rd_data = mem_ic_debug_rd_data; // @[quasar_wrapper.scala 93:15]
|
||||
assign swerv_io_ic_tag_debug_rd_data = mem_ic_tag_debug_rd_data; // @[quasar_wrapper.scala 93:15]
|
||||
assign swerv_io_ic_eccerr = mem_ic_eccerr; // @[quasar_wrapper.scala 93:15]
|
||||
assign swerv_io_ic_rd_hit = mem_ic_rd_hit; // @[quasar_wrapper.scala 93:15]
|
||||
assign swerv_io_ic_tag_perr = mem_ic_tag_perr; // @[quasar_wrapper.scala 93:15]
|
||||
assign swerv_io_iccm_rd_data = mem_iccm_rd_data; // @[quasar_wrapper.scala 94:17]
|
||||
assign swerv_io_iccm_rd_data_ecc = mem_iccm_rd_data_ecc; // @[quasar_wrapper.scala 94:17]
|
||||
assign swerv_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[quasar_wrapper.scala 155:27]
|
||||
assign swerv_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[quasar_wrapper.scala 156:27]
|
||||
assign swerv_io_dbg_bus_clk_en = io_dbg_bus_clk_en; // @[quasar_wrapper.scala 157:27]
|
||||
assign swerv_io_dma_bus_clk_en = io_dma_bus_clk_en; // @[quasar_wrapper.scala 158:27]
|
||||
assign swerv_io_dmi_reg_en = dmi_wrapper_reg_en; // @[quasar_wrapper.scala 78:23]
|
||||
assign swerv_io_dmi_reg_addr = dmi_wrapper_reg_wr_addr; // @[quasar_wrapper.scala 77:25]
|
||||
assign swerv_io_dmi_reg_wr_en = dmi_wrapper_reg_wr_en; // @[quasar_wrapper.scala 79:26]
|
||||
assign swerv_io_dmi_reg_wdata = dmi_wrapper_reg_wr_data; // @[quasar_wrapper.scala 76:26]
|
||||
assign swerv_io_extintsrc_req = io_extintsrc_req; // @[quasar_wrapper.scala 162:26]
|
||||
assign swerv_io_timer_int = io_timer_int; // @[quasar_wrapper.scala 160:22]
|
||||
assign swerv_io_soft_int = io_soft_int; // @[quasar_wrapper.scala 161:21]
|
||||
assign swerv_io_scan_mode = io_scan_mode; // @[quasar_wrapper.scala 110:22]
|
||||
assign swerv_io_lsu_axi_aw_ready = io_lsu_brg_aw_ready; // @[quasar_wrapper.scala 105:22]
|
||||
assign swerv_io_lsu_axi_w_ready = io_lsu_brg_w_ready; // @[quasar_wrapper.scala 105:22]
|
||||
assign swerv_io_lsu_axi_b_valid = io_lsu_brg_b_valid; // @[quasar_wrapper.scala 105:22]
|
||||
assign swerv_io_lsu_axi_b_bits_resp = io_lsu_brg_b_bits_resp; // @[quasar_wrapper.scala 105:22]
|
||||
assign swerv_io_lsu_axi_b_bits_id = io_lsu_brg_b_bits_id; // @[quasar_wrapper.scala 105:22]
|
||||
assign swerv_io_lsu_axi_ar_ready = io_lsu_brg_ar_ready; // @[quasar_wrapper.scala 105:22]
|
||||
assign swerv_io_lsu_axi_r_valid = io_lsu_brg_r_valid; // @[quasar_wrapper.scala 105:22]
|
||||
assign swerv_io_lsu_axi_r_bits_id = io_lsu_brg_r_bits_id; // @[quasar_wrapper.scala 105:22]
|
||||
assign swerv_io_lsu_axi_r_bits_data = io_lsu_brg_r_bits_data; // @[quasar_wrapper.scala 105:22]
|
||||
assign swerv_io_lsu_axi_r_bits_resp = io_lsu_brg_r_bits_resp; // @[quasar_wrapper.scala 105:22]
|
||||
assign swerv_io_ifu_axi_ar_ready = io_ifu_brg_ar_ready; // @[quasar_wrapper.scala 106:22]
|
||||
assign swerv_io_ifu_axi_r_valid = io_ifu_brg_r_valid; // @[quasar_wrapper.scala 106:22]
|
||||
assign swerv_io_ifu_axi_r_bits_id = io_ifu_brg_r_bits_id; // @[quasar_wrapper.scala 106:22]
|
||||
assign swerv_io_ifu_axi_r_bits_data = io_ifu_brg_r_bits_data; // @[quasar_wrapper.scala 106:22]
|
||||
assign swerv_io_ifu_axi_r_bits_resp = io_ifu_brg_r_bits_resp; // @[quasar_wrapper.scala 106:22]
|
||||
assign swerv_io_sb_axi_aw_ready = io_sb_brg_aw_ready; // @[quasar_wrapper.scala 107:21]
|
||||
assign swerv_io_sb_axi_w_ready = io_sb_brg_w_ready; // @[quasar_wrapper.scala 107:21]
|
||||
assign swerv_io_sb_axi_b_valid = io_sb_brg_b_valid; // @[quasar_wrapper.scala 107:21]
|
||||
assign swerv_io_sb_axi_b_bits_resp = io_sb_brg_b_bits_resp; // @[quasar_wrapper.scala 107:21]
|
||||
assign swerv_io_sb_axi_ar_ready = io_sb_brg_ar_ready; // @[quasar_wrapper.scala 107:21]
|
||||
assign swerv_io_sb_axi_r_valid = io_sb_brg_r_valid; // @[quasar_wrapper.scala 107:21]
|
||||
assign swerv_io_sb_axi_r_bits_data = io_sb_brg_r_bits_data; // @[quasar_wrapper.scala 107:21]
|
||||
assign swerv_io_sb_axi_r_bits_resp = io_sb_brg_r_bits_resp; // @[quasar_wrapper.scala 107:21]
|
||||
assign swerv_io_dma_axi_aw_valid = io_dma_brg_aw_valid; // @[quasar_wrapper.scala 108:22]
|
||||
assign swerv_io_dma_axi_aw_bits_id = io_dma_brg_aw_bits_id; // @[quasar_wrapper.scala 108:22]
|
||||
assign swerv_io_dma_axi_aw_bits_addr = io_dma_brg_aw_bits_addr; // @[quasar_wrapper.scala 108:22]
|
||||
assign swerv_io_dma_axi_aw_bits_size = io_dma_brg_aw_bits_size; // @[quasar_wrapper.scala 108:22]
|
||||
assign swerv_io_dma_axi_w_valid = io_dma_brg_w_valid; // @[quasar_wrapper.scala 108:22]
|
||||
assign swerv_io_dma_axi_w_bits_data = io_dma_brg_w_bits_data; // @[quasar_wrapper.scala 108:22]
|
||||
assign swerv_io_dma_axi_w_bits_strb = io_dma_brg_w_bits_strb; // @[quasar_wrapper.scala 108:22]
|
||||
assign swerv_io_dma_axi_b_ready = io_dma_brg_b_ready; // @[quasar_wrapper.scala 108:22]
|
||||
assign swerv_io_dma_axi_ar_valid = io_dma_brg_ar_valid; // @[quasar_wrapper.scala 108:22]
|
||||
assign swerv_io_dma_axi_ar_bits_id = io_dma_brg_ar_bits_id; // @[quasar_wrapper.scala 108:22]
|
||||
assign swerv_io_dma_axi_ar_bits_addr = io_dma_brg_ar_bits_addr; // @[quasar_wrapper.scala 108:22]
|
||||
assign swerv_io_dma_axi_ar_bits_size = io_dma_brg_ar_bits_size; // @[quasar_wrapper.scala 108:22]
|
||||
assign swerv_io_dma_axi_r_ready = io_dma_brg_r_ready; // @[quasar_wrapper.scala 108:22]
|
||||
assign swerv_io_dbg_rst_l = io_dbg_rst_l; // @[quasar_wrapper.scala 93:22 quasar_wrapper.scala 122:22]
|
||||
assign swerv_io_rst_vec = io_rst_vec; // @[quasar_wrapper.scala 123:20]
|
||||
assign swerv_io_nmi_int = io_nmi_int; // @[quasar_wrapper.scala 124:20]
|
||||
assign swerv_io_nmi_vec = io_nmi_vec; // @[quasar_wrapper.scala 125:20]
|
||||
assign swerv_io_i_cpu_halt_req = io_i_cpu_halt_req; // @[quasar_wrapper.scala 128:27]
|
||||
assign swerv_io_i_cpu_run_req = io_i_cpu_run_req; // @[quasar_wrapper.scala 129:26]
|
||||
assign swerv_io_core_id = io_core_id; // @[quasar_wrapper.scala 130:20]
|
||||
assign swerv_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[quasar_wrapper.scala 133:31]
|
||||
assign swerv_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[quasar_wrapper.scala 134:30]
|
||||
assign swerv_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[quasar_wrapper.scala 135:30]
|
||||
assign swerv_io_dccm_rd_data_lo = mem_dccm_rd_data_lo; // @[quasar_wrapper.scala 88:15]
|
||||
assign swerv_io_dccm_rd_data_hi = mem_dccm_rd_data_hi; // @[quasar_wrapper.scala 88:15]
|
||||
assign swerv_io_ic_rd_data = mem_ic_rd_data; // @[quasar_wrapper.scala 94:15]
|
||||
assign swerv_io_ic_debug_rd_data = mem_ic_debug_rd_data; // @[quasar_wrapper.scala 94:15]
|
||||
assign swerv_io_ic_tag_debug_rd_data = mem_ic_tag_debug_rd_data; // @[quasar_wrapper.scala 94:15]
|
||||
assign swerv_io_ic_eccerr = mem_ic_eccerr; // @[quasar_wrapper.scala 94:15]
|
||||
assign swerv_io_ic_rd_hit = mem_ic_rd_hit; // @[quasar_wrapper.scala 94:15]
|
||||
assign swerv_io_ic_tag_perr = mem_ic_tag_perr; // @[quasar_wrapper.scala 94:15]
|
||||
assign swerv_io_iccm_rd_data = mem_iccm_rd_data; // @[quasar_wrapper.scala 95:17]
|
||||
assign swerv_io_iccm_rd_data_ecc = mem_iccm_rd_data_ecc; // @[quasar_wrapper.scala 95:17]
|
||||
assign swerv_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[quasar_wrapper.scala 137:27]
|
||||
assign swerv_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[quasar_wrapper.scala 138:27]
|
||||
assign swerv_io_dbg_bus_clk_en = io_dbg_bus_clk_en; // @[quasar_wrapper.scala 139:27]
|
||||
assign swerv_io_dma_bus_clk_en = io_dma_bus_clk_en; // @[quasar_wrapper.scala 140:27]
|
||||
assign swerv_io_dmi_reg_en = dmi_wrapper_reg_en; // @[quasar_wrapper.scala 79:23]
|
||||
assign swerv_io_dmi_reg_addr = dmi_wrapper_reg_wr_addr; // @[quasar_wrapper.scala 78:25]
|
||||
assign swerv_io_dmi_reg_wr_en = dmi_wrapper_reg_wr_en; // @[quasar_wrapper.scala 80:26]
|
||||
assign swerv_io_dmi_reg_wdata = dmi_wrapper_reg_wr_data; // @[quasar_wrapper.scala 77:26]
|
||||
assign swerv_io_extintsrc_req = io_extintsrc_req; // @[quasar_wrapper.scala 144:26]
|
||||
assign swerv_io_timer_int = io_timer_int; // @[quasar_wrapper.scala 142:22]
|
||||
assign swerv_io_soft_int = io_soft_int; // @[quasar_wrapper.scala 143:21]
|
||||
assign swerv_io_scan_mode = io_scan_mode; // @[quasar_wrapper.scala 66:22]
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -508,7 +508,3 @@ class dma_ctrl extends Module with lib with RequireAsyncReset {
|
|||
io.ifu_dma.dma_mem_ctl.dma_mem_write := io.lsu_dma.dma_lsc_ctl.dma_mem_write
|
||||
io.ifu_dma.dma_mem_ctl.dma_mem_tag := io.lsu_dma.dma_mem_tag
|
||||
}
|
||||
|
||||
object dma_main extends App {
|
||||
println((new chisel3.stage.ChiselStage).emitVerilog(new dma_ctrl()))
|
||||
}
|
||||
|
|
|
|||
|
|
@ -227,6 +227,3 @@ class ahb_to_axi4 extends Module with lib with RequireAsyncReset {
|
|||
|
||||
bus_clk := rvclkhdr(clock, io.bus_clk_en, io.scan_mode)
|
||||
}
|
||||
object AHB_main extends App {
|
||||
println("Generate Verilog")
|
||||
println((new chisel3.stage.ChiselStage).emitVerilog(new ahb_to_axi4()))}
|
||||
|
|
@ -405,8 +405,3 @@ class axi4_to_ahb extends Module with lib with RequireAsyncReset with Config {
|
|||
ahbm_addr_clk := rvclkhdr(clock, ahbm_addr_clken, io.scan_mode)
|
||||
ahbm_data_clk := rvclkhdr(clock, ahbm_data_clken, io.scan_mode)
|
||||
}
|
||||
|
||||
object AXImain extends App {
|
||||
println("Generate Verilog")
|
||||
println((new chisel3.stage.ChiselStage).emitVerilog(new axi4_to_ahb()))
|
||||
}
|
||||
|
|
@ -318,7 +318,4 @@ class lsu extends Module with RequireAsyncReset with param with lib {
|
|||
withClock(clkdomain.io.lsu_c2_r_clk){lsu_raw_fwd_hi_r := RegNext(lsu_raw_fwd_hi_m,0.U)}
|
||||
withClock(clkdomain.io.lsu_c2_r_clk){lsu_raw_fwd_lo_r := RegNext(lsu_raw_fwd_lo_m,0.U)}
|
||||
|
||||
}
|
||||
object lsu extends App {
|
||||
println((new chisel3.stage.ChiselStage).emitVerilog(new lsu()))
|
||||
}
|
||||
|
|
@ -616,6 +616,3 @@ class lsu_bus_buffer extends Module with RequireAsyncReset with lib {
|
|||
io.lsu_busreq_r := withClock(io.lsu_c2_r_clk){RegNext(io.lsu_busreq_m & !io.flush_r & !io.ld_full_hit_m, false.B)}
|
||||
lsu_nonblock_load_valid_r := withClock(io.lsu_c2_r_clk){RegNext(io.dctl_busbuff.lsu_nonblock_load_valid_m, false.B)}
|
||||
}
|
||||
object bus_buffer extends App {
|
||||
println((new chisel3.stage.ChiselStage).emitVerilog(new lsu_bus_buffer()))
|
||||
}
|
||||
|
|
@ -405,7 +405,3 @@ class pic_ctrl extends Module with RequireAsyncReset with lib {
|
|||
}
|
||||
|
||||
}
|
||||
|
||||
object pic_main extends App {
|
||||
println((new chisel3.stage.ChiselStage).emitVerilog(new pic_ctrl()))
|
||||
}
|
||||
|
|
@ -532,8 +532,5 @@ class quasar extends Module with RequireAsyncReset with lib {
|
|||
}
|
||||
io.dmi_reg_rdata := 0.U
|
||||
}
|
||||
object QUASAR extends App {
|
||||
println((new chisel3.stage.ChiselStage).emitVerilog(new quasar()))
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -96,11 +96,12 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset {
|
|||
|
||||
|
||||
if(BUILD_AXI4) {
|
||||
swerv.io.ahb <> 0.U.asTypeOf(swerv.io.ahb.in)
|
||||
swerv.io.lsu_ahb <> 0.U.asTypeOf(swerv.io.lsu_ahb.in)
|
||||
swerv.io.sb_ahb <> 0.U.asTypeOf(swerv.io.sb_ahb.in)
|
||||
swerv.io.dma <> 0.U.asTypeOf(swerv.io.dma)
|
||||
|
||||
swerv.io.ahb.in <> 0.U.asTypeOf(swerv.io.ahb.in)
|
||||
swerv.io.lsu_ahb.in <> 0.U.asTypeOf(swerv.io.lsu_ahb.in)
|
||||
swerv.io.sb_ahb.in <> 0.U.asTypeOf(swerv.io.sb_ahb.in)
|
||||
swerv.io.dma.ahb.out <> 0.U.asTypeOf(swerv.io.dma.ahb.out)
|
||||
swerv.io.dma.hsel := 0.U
|
||||
swerv.io.dma.hreadyin := 0.U
|
||||
swerv.io.lsu_axi <> io.lsu_brg
|
||||
swerv.io.ifu_axi <> io.ifu_brg
|
||||
swerv.io.sb_axi <> io.sb_brg
|
||||
|
|
@ -133,25 +134,6 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset {
|
|||
swerv.io.mpc_debug_run_req := io.mpc_debug_run_req
|
||||
swerv.io.mpc_reset_run_req := io.mpc_reset_run_req
|
||||
|
||||
|
||||
//-------------------------- DMA AXI signals--------------------------
|
||||
// AXI Write Channels
|
||||
swerv.io.dma_axi <> io.dma_brg
|
||||
|
||||
// DMA Slave
|
||||
//swerv.io.dma.hsel := io.dma.hsel
|
||||
//swerv.io.dma.ahb.out <> io.dma.ahb.out
|
||||
// swerv.io.dma_haddr := io.dma_haddr
|
||||
// swerv.io.dma_hburst := io.dma_hburst
|
||||
// swerv.io.dma_hmastlock := io.dma_hmastlock
|
||||
// swerv.io.dma_hprot := io.dma_hprot
|
||||
// swerv.io.dma_hsize := io.dma_hsize
|
||||
// swerv.io.dma_htrans := io.dma_htrans
|
||||
// swerv.io.dma_hwrite := io.dma_hwrite
|
||||
// swerv.io.dma_hwdata := io.dma_hwdata
|
||||
//swerv.io.dma.hreadyin := io.dma.hreadyin
|
||||
|
||||
|
||||
swerv.io.lsu_bus_clk_en := io.lsu_bus_clk_en
|
||||
swerv.io.ifu_bus_clk_en := io.ifu_bus_clk_en
|
||||
swerv.io.dbg_bus_clk_en := io.dbg_bus_clk_en
|
||||
|
|
@ -180,15 +162,6 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset {
|
|||
io.dec_tlu_perfcnt2 := swerv.io.dec_tlu_perfcnt2
|
||||
io.dec_tlu_perfcnt3 := swerv.io.dec_tlu_perfcnt3
|
||||
|
||||
|
||||
//-------------------------- LSU AXI signals--------------------------
|
||||
// AXI Write Channels
|
||||
|
||||
// DMA Slave
|
||||
// io.dma_hrdata := swerv.io.dma_hrdata
|
||||
// io.dma_hreadyout := swerv.io.dma_hreadyout
|
||||
// io.dma_hresp := swerv.io.dma_hresp
|
||||
|
||||
}
|
||||
object QUASAR_Wrp extends App {
|
||||
println((new chisel3.stage.ChiselStage).emitVerilog(new quasar_wrapper()))
|
||||
|
|
|
|||
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Reference in New Issue