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Quasar Wrapper updated

This commit is contained in:
​Laraib Khan 2021-02-17 09:51:40 +05:00
parent 21b5cc23f7
commit 904ac0263f
109 changed files with 258692 additions and 14060 deletions
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2
firrtl_black_box_resource_files.f
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@ -1 +1,3 @@
/home/laraibkhan/Desktop/SweRV-Chislified/gated_latch.sv
/home/laraibkhan/Desktop/SweRV-Chislified/dmi_wrapper.sv
/home/laraibkhan/Desktop/SweRV-Chislified/mem.sv

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mem.sv
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//********************************************************************************
// SPDX-License-Identifier: Apache-2.0
// Copyright 2020 Western Digital Corporation or its affiliates.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//********************************************************************************
module mem #(
parameter ICACHE_BEAT_BITS,
parameter ICCM_BITS,
parameter ICACHE_NUM_WAYS,
parameter DCCM_BYTE_WIDTH,
parameter ICCM_BANK_INDEX_LO,
parameter ICACHE_BANK_BITS,
parameter DCCM_BITS,
parameter ICACHE_BEAT_ADDR_HI,
parameter ICCM_INDEX_BITS,
parameter ICCM_BANK_HI,
parameter ICACHE_BANKS_WAY,
parameter ICACHE_INDEX_HI,
parameter DCCM_NUM_BANKS,
parameter ICACHE_BANK_HI,
parameter ICACHE_BANK_LO,
parameter DCCM_ENABLE= 'b1,
parameter ICACHE_TAG_LO,
parameter ICACHE_DATA_INDEX_LO,
parameter ICCM_NUM_BANKS,
parameter ICACHE_ECC,
parameter ICACHE_ENABLE= 'b1,
parameter DCCM_BANK_BITS,
parameter ICCM_ENABLE= 'b1,
parameter ICCM_BANK_BITS,
parameter ICACHE_TAG_DEPTH,
parameter ICACHE_WAYPACK,
parameter DCCM_SIZE,
parameter DCCM_FDATA_WIDTH,
parameter ICACHE_TAG_INDEX_LO,
parameter ICACHE_DATA_DEPTH)
module mem
(
input logic clk,
input logic rst_l,
@ -52,10 +38,12 @@ module mem #(
output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi,
//`ifdef DCCM_ENABLE
input dccm_ext_in_pkt_t [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt,
//`endif
//ICCM ports
input ccm_ext_in_pkt_t [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt,
input logic [ICCM_BITS-1:1] iccm_rw_addr,
input logic iccm_buf_correct_ecc, // ICCM is doing a single bit error correct cycle
@ -76,9 +64,10 @@ module mem #(
input logic ic_rd_en,
input logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache.
input logic ic_sel_premux_data, // Premux data sel
input ic_data_ext_in_pkt_t [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt,
input ic_tag_ext_in_pkt_t [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt,
input logic [70:0] ic_wr_data_0, // Data to fill to the Icache. With ECC
input logic [70:0] ic_wr_data_1,
input logic [ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data, // Data to fill to the Icache. With ECC
input logic [70:0] ic_debug_wr_data, // Debug wr cache.
output logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
input logic [ICACHE_INDEX_HI:3] ic_debug_addr, // Read/Write addresss to the Icache.
@ -88,7 +77,7 @@ module mem #(
input logic [ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr.
output logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
output logic [25:0] ic_tag_debug_rd_data,// Debug icache tag.
output logic [25:0] ictag_debug_rd_data,// Debug icache tag.
output logic [ICACHE_BANKS_WAY-1:0] ic_eccerr, // ecc error per bank
@ -101,18 +90,19 @@ module mem #(
);
logic [ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data;
assign ic_wr_data [0] = ic_wr_data_0;
assign ic_wr_data [1] = ic_wr_data_1;
logic active_clk;
rvoclkhdr active_cg ( .en(1'b1), .l1clk(active_clk), .* );
// DCCM Instantiation
if (DCCM_ENABLE == 1) begin: Gen_dccm_enable
lsu_dccm_mem #(
lsu_dccm_mem dccm #(
.DCCM_BYTE_WIDTH(DCCM_BYTE_WIDTH),
.DCCM_BITS(DCCM_BITS),
.DCCM_NUM_BANKS(DCCM_NUM_BANKS),
.DCCM_BANK_BITS(DCCM_BANK_BITS),
.DCCM_SIZE(DCCM_SIZE),
.DCCM_FDATA_WIDTH(DCCM_FDATA_WIDTH)) dccm (
.DCCM_FDATA_WIDTH(DCCM_FDATA_WIDTH),
.DCCM_WIDTH_BITS(DCCM_WIDTH_BITS))(
.clk_override(dccm_clk_override),
.*
);
@ -137,7 +127,13 @@ if ( ICACHE_ENABLE ) begin: icache
.ICACHE_TAG_DEPTH(ICACHE_TAG_DEPTH),
.ICACHE_WAYPACK(ICACHE_WAYPACK),
.ICACHE_TAG_INDEX_LO(ICACHE_TAG_INDEX_LO),
.ICACHE_DATA_DEPTH(ICACHE_DATA_DEPTH)) icm (
.ICACHE_DATA_DEPTH(ICACHE_DATA_DEPTH),
.ICACHE_TAG_NUM_BYPASS(ICACHE_TAG_NUM_BYPASS),
.ICACHE_TAG_NUM_BYPASS_WIDTH(ICACHE_TAG_NUM_BYPASS_WIDTH),
.ICACHE_TAG_BYPASS_ENABLE(ICACHE_TAG_BYPASS_ENABLE),
.ICACHE_NUM_BYPASS_WIDTH(ICACHE_NUM_BYPASS_WIDTH),
.ICACHE_BYPASS_ENABLE(ICACHE_BYPASS_ENABLE),
.ICACHE_LN_SZ(ICACHE_LN_SZ)) icm (
.clk_override(icm_clk_override),
.*
);
@ -146,7 +142,7 @@ else begin
assign ic_rd_hit[ICACHE_NUM_WAYS-1:0] = '0;
assign ic_tag_perr = '0 ;
assign ic_rd_data = '0 ;
assign ic_tag_debug_rd_data = '0 ;
assign ictag_debug_rd_data = '0 ;
end // else: !if( ICACHE_ENABLE )
@ -171,3 +167,4 @@ end
endmodule

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src/main/resources/vsrc/ifu_ic_mem.sv
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src/main/resources/vsrc/ifu_iccm_mem.sv
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@ -1,6 +1,6 @@
//********************************************************************************
// SPDX-License-Identifier: Apache-2.0
// Copyright 2020 Western Digital Corporation or it's affiliates.
// Copyright 2020 Western Digital Corporation or its affiliates.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@ -19,30 +19,40 @@
// Icache closely coupled memory --- ICCM
//********************************************************************************
module ifu_iccm_mem
module el2_ifu_iccm_mem
#(
parameter ICCM_BITS,
parameter ICCM_BANK_INDEX_LO,
parameter ICCM_INDEX_BITS,
parameter ICCM_BANK_HI,
parameter ICCM_NUM_BANKS,
parameter ICCM_BANK_BITS )(
input logic clk,
input logic rst_l,
input logic clk_override,
parameter ICCM_BANK_BITS
)(
input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.
input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in.
input logic rst_l, // reset, active low
input logic clk_override, // Override non-functional clock gating
input logic iccm_wren,
input logic iccm_rden,
input logic [ICCM_BITS-1:1] iccm_rw_addr,
input logic iccm_wren, // ICCM write enable
input logic iccm_rden, // ICCM read enable
input logic [ICCM_BITS-1:1] iccm_rw_addr, // ICCM read/write address
input logic iccm_buf_correct_ecc, // ICCM is doing a single bit error correct cycle
input logic iccm_correction_state, // We are under a correction - This is needed to guard replacements when hit
input logic [2:0] iccm_wr_size,
input logic [77:0] iccm_wr_data,
input logic iccm_correction_state, // ICCM under a correction - This is needed to guard replacements when hit
input logic [2:0] iccm_wr_size, // ICCM write size
input logic [77:0] iccm_wr_data, // ICCM write data
output logic [63:0] iccm_rd_data,
output logic [77:0] iccm_rd_data_ecc,
input logic scan_mode
//input el2_ccm_ext_in_pkt_t [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt, // External packet
input [ICCM_NUM_BANKS-1:0] TEST1,
input [ICCM_NUM_BANKS-1:0] RME,
input [ICCM_NUM_BANKS-1:0][3:0] RM,
input [ICCM_NUM_BANKS-1:0] LS,
input [ICCM_NUM_BANKS-1:0] DS,
input [ICCM_NUM_BANKS-1:0] TEST-RNM,
input [ICCM_NUM_BANKS-1:0] BC1,
input [ICCM_NUM_BANKS-1:0] BC2,
output logic [63:0] iccm_rd_data, // ICCM read data
output logic [77:0] iccm_rd_data_ecc, // ICCM read ecc
input logic scan_mode // Scan mode control
);
@ -75,15 +85,32 @@ module ifu_iccm_mem
logic redundant_data1_en;
logic r0_addr_en, r1_addr_en;
// Testing persistent flip
// logic [3:0] not_iccm_bank_dout;
// logic [15:3] ecc_insert_flip_in, ecc_insert_flip;
// logic flip_en, flip_match, flip_match_q;
//
// assign flip_in = (iccm_rw_addr[3:2] != 2'b00); // dont flip when bank0 - this is to make some progress in DMA streaming cases
// assign flip_en = iccm_rden;
//
// rvdffs #(1) flipmatch (.*,
// .clk(clk),
// .din(flip_in),
// .en(flip_en),
// .dout(flip_match_q));
//
// end of testing flip
assign addr_incr[1:0] = (iccm_wr_size[1:0] == 2'b11) ? 2'b10: 2'b01;
assign addr_bank_inc[ICCM_BITS-1 : 1] = iccm_rw_addr[ICCM_BITS-1 : 1] + addr_incr[1:0];
for (genvar i=0; i<32'(ICCM_NUM_BANKS)/2; i++) begin: mem_bank_data
for (genvar i=0; i<ICCM_NUM_BANKS/2; i++) begin: mem_bank_data
assign iccm_bank_wr_data_vec[(2*i)] = iccm_wr_data[38:0];
assign iccm_bank_wr_data_vec[(2*i)+1] = iccm_wr_data[77:39];
end
for (genvar i=0; i<32'(ICCM_NUM_BANKS); i++) begin: mem_bank
for (genvar i=0; i<ICCM_NUM_BANKS; i++) begin: mem_bank
assign wren_bank[i] = iccm_wren & ((iccm_rw_addr[ICCM_BANK_HI:2] == i) | (addr_bank_inc[ICCM_BANK_HI:2] == i));
assign iccm_bank_wr_data[i] = iccm_bank_wr_data_vec[i];
assign rden_bank[i] = iccm_rden & ( (iccm_rw_addr[ICCM_BANK_HI:2] == i) | (addr_bank_inc[ICCM_BANK_HI:2] == i));
@ -101,7 +128,18 @@ module ifu_iccm_mem
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(iccm_bank_wr_data[i][38:0]),
.Q(iccm_bank_dout[i][38:0])
.Q(iccm_bank_dout[i][38:0]),
.ROP ( ),
// These are used by SoC
.TEST1(TEST1[i]),
.RME(RME[i]),
.RM(RM[i][3:0]),
.LS(LS[i]),
.DS(DS[i]),
.SD(SD[i]) ,
.TEST_RNM(TEST_RNM[i]),
.BC1(BC1[i]),
.BC2(BC2[i])
);
`else
@ -114,7 +152,18 @@ module ifu_iccm_mem
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(iccm_bank_wr_data[i][38:0]),
.Q(iccm_bank_dout[i][38:0])
.Q(iccm_bank_dout[i][38:0]),
.ROP ( ),
// These are used by SoC
.TEST1(TEST1[i]),
.RME(RME[i]),
.RM(RM[i][3:0]),
.LS(LS[i]),
.DS(DS[i]),
.SD(SD[i]) ,
.TEST_RNM(TEST_RNM[i]),
.BC1(BC1[i]),
.BC2(BC2[i])
);
end // block: iccm
@ -127,7 +176,18 @@ module ifu_iccm_mem
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(iccm_bank_wr_data[i][38:0]),
.Q(iccm_bank_dout[i][38:0])
.Q(iccm_bank_dout[i][38:0]),
.ROP ( ),
// These are used by SoC
.TEST1(TEST1[i]),
.RME(RME[i]),
.RM(RM[i][3:0]),
.LS(LS[i]),
.DS(DS[i]),
.SD(SD[i]) ,
.TEST_RNM(TEST_RNM[i]),
.BC1(BC1[i]),
.BC2(BC2[i])
);
end // block: iccm
@ -140,7 +200,18 @@ module ifu_iccm_mem
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(iccm_bank_wr_data[i][38:0]),
.Q(iccm_bank_dout[i][38:0])
.Q(iccm_bank_dout[i][38:0]),
.ROP ( ),
// These are used by SoC
.TEST1(TEST1[i]),
.RME(RME[i]),
.RM(RM[i][3:0]),
.LS(LS[i]),
.DS(DS[i]),
.SD(SD[i]) ,
.TEST_RNM(TEST_RNM[i]),
.BC1(BC1[i]),
.BC2(BC2[i])
);
end // block: iccm
@ -152,7 +223,18 @@ module ifu_iccm_mem
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(iccm_bank_wr_data[i][38:0]),
.Q(iccm_bank_dout[i][38:0])
.Q(iccm_bank_dout[i][38:0]),
.ROP ( ),
// These are used by SoC
.TEST1(TEST1[i]),
.RME(RME[i]),
.RM(RM[i][3:0]),
.LS(LS[i]),
.DS(DS[i]),
.SD(SD[i]) ,
.TEST_RNM(TEST_RNM[i]),
.BC1(BC1[i]),
.BC2(BC2[i])
);
end // block: iccm
@ -164,7 +246,18 @@ module ifu_iccm_mem
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(iccm_bank_wr_data[i][38:0]),
.Q(iccm_bank_dout[i][38:0])
.Q(iccm_bank_dout[i][38:0]),
.ROP ( ),
// These are used by SoC
.TEST1(TEST1[i]),
.RME(RME[i]),
.RM(RM[i][3:0]),
.LS(LS[i]),
.DS(DS[i]),
.SD(SD[i]) ,
.TEST_RNM(TEST_RNM[i]),
.BC1(BC1[i]),
.BC2(BC2[i])
);
end // block: iccm
@ -176,7 +269,18 @@ module ifu_iccm_mem
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(iccm_bank_wr_data[i][38:0]),
.Q(iccm_bank_dout[i][38:0])
.Q(iccm_bank_dout[i][38:0]),
.ROP ( ),
// These are used by SoC
.TEST1(TEST1[i]),
.RME(RME[i]),
.RM(RM[i][3:0]),
.LS(LS[i]),
.DS(DS[i]),
.SD(SD[i]) ,
.TEST_RNM(TEST_RNM[i]),
.BC1(BC1[i]),
.BC2(BC2[i])
);
end // block: iccm
@ -188,7 +292,18 @@ module ifu_iccm_mem
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(iccm_bank_wr_data[i][38:0]),
.Q(iccm_bank_dout[i][38:0])
.Q(iccm_bank_dout[i][38:0]),
.ROP ( ),
// These are used by SoC
.TEST1(TEST1[i]),
.RME(RME[i]),
.RM(RM[i][3:0]),
.LS(LS[i]),
.DS(DS[i]),
.SD(SD[i]) ,
.TEST_RNM(TEST_RNM[i]),
.BC1(BC1[i]),
.BC2(BC2[i])
);
end // block: iccm
@ -200,7 +315,18 @@ module ifu_iccm_mem
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(iccm_bank_wr_data[i][38:0]),
.Q(iccm_bank_dout[i][38:0])
.Q(iccm_bank_dout[i][38:0]),
.ROP ( ),
// These are used by SoC
.TEST1(TEST1[i]),
.RME(RME[i]),
.RM(RM[i][3:0]),
.LS(LS[i]),
.DS(DS[i]),
.SD(SD[i]) ,
.TEST_RNM(TEST_RNM[i]),
.BC1(BC1[i]),
.BC2(BC2[i])
);
end // block: iccm
@ -212,7 +338,18 @@ module ifu_iccm_mem
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(iccm_bank_wr_data[i][38:0]),
.Q(iccm_bank_dout[i][38:0])
.Q(iccm_bank_dout[i][38:0]),
.ROP ( ),
// These are used by SoC
.TEST1(TEST1[i]),
.RME(RME[i]),
.RM(RM[i][3:0]),
.LS(LS[i]),
.DS(DS[i]),
.SD(SD[i]) ,
.TEST_RNM(TEST_RNM[i]),
.BC1(BC1[i]),
.BC2(BC2[i])
);
end // block: iccm
@ -224,7 +361,18 @@ module ifu_iccm_mem
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(iccm_bank_wr_data[i][38:0]),
.Q(iccm_bank_dout[i][38:0])
.Q(iccm_bank_dout[i][38:0]),
.ROP ( ),
// These are used by SoC
.TEST1(TEST1[i]),
.RME(RME[i]),
.RM(RM[i][3:0]),
.LS(LS[i]),
.DS(DS[i]),
.SD(SD[i]) ,
.TEST_RNM(TEST_RNM[i]),
.BC1(BC1[i]),
.BC2(BC2[i])
);
end // block: iccm
@ -238,12 +386,12 @@ module ifu_iccm_mem
((addr_bank_inc[ICCM_BITS-1:2]== redundant_address[0][ICCM_BITS-1:2]) & (addr_bank_inc[3:2] == i))));
rvdff #(1) selred0 (.*,
.clk(clk),
.clk(active_clk),
.din(sel_red0[i]),
.dout(sel_red0_q[i]));
rvdff #(1) selred1 (.*,
.clk(clk),
.clk(active_clk),
.din(sel_red1[i]),
.dout(sel_red1_q[i]));
@ -253,7 +401,6 @@ module ifu_iccm_mem
({39{sel_red0_q[i]}} & redundant_data[0][38:0]) |
({39{~sel_red0_q[i] & ~sel_red1_q[i]}} & iccm_bank_dout[i][38:0]);
end : mem_bank
// This section does the redundancy for tolerating single bit errors
// 2x 39 bit data values with address[hi:2] and a valid bit is needed to CAM and sub out the reads/writes to the particular locations
@ -264,31 +411,31 @@ module ifu_iccm_mem
assign redundant_lru_in = iccm_buf_correct_ecc ? ~redundant_lru : (|sel_red0[ICCM_NUM_BANKS-1:0]) ? 1'b1 : 1'b0;
rvdffs #() red_lru (.*, // LRU flop for the redundant replacements
.clk(clk),
.clk(active_clk),
.en(redundant_lru_en),
.din(redundant_lru_in),
.dout(redundant_lru));
rvdffs #(ICCM_BITS-2) r0_address (.*, // Redundant Row 0 address
.clk(clk),
.clk(active_clk),
.en(r0_addr_en),
.din(iccm_rw_addr[ICCM_BITS-1:2]),
.dout(redundant_address[0][ICCM_BITS-1:2]));
rvdffs #(ICCM_BITS-2) r1_address (.*, // Redundant Row 0 address
.clk(clk),
.clk(active_clk),
.en(r1_addr_en),
.din(iccm_rw_addr[ICCM_BITS-1:2]),
.dout(redundant_address[1][ICCM_BITS-1:2]));
rvdffs #(1) r0_valid (.*,
.clk(clk), // Redundant Row 0 Valid
.clk(active_clk), // Redundant Row 0 Valid
.en(r0_addr_en),
.din(1'b1),
.dout(redundant_valid[0]));
rvdffs #(1) r1_valid (.*, // Redundant Row 1 Valid
.clk(clk),
.clk(active_clk),
.en(r1_addr_en),
.din(1'b1),
.dout(redundant_valid[1]));
@ -305,7 +452,7 @@ module ifu_iccm_mem
assign redundant_data0_in[38:0] = (((iccm_rw_addr[2] == redundant_address[0][2]) & iccm_rw_addr[2]) | (redundant_address[0][2] & (iccm_wr_size[1:0] == 2'b11))) ? iccm_wr_data[77:39] : iccm_wr_data[38:0];
rvdffs #(39) r0_data (.*, // Redundant Row 1 data
.clk(clk),
.clk(active_clk),
.en(redundant_data0_en),
.din(redundant_data0_in[38:0]),
.dout(redundant_data[0][38:0]));
@ -316,14 +463,14 @@ module ifu_iccm_mem
assign redundant_data1_in[38:0] = (((iccm_rw_addr[2] == redundant_address[1][2]) & iccm_rw_addr[2]) | (redundant_address[1][2] & (iccm_wr_size[1:0] == 2'b11))) ? iccm_wr_data[77:39] : iccm_wr_data[38:0];
rvdffs #(39) r1_data (.*, // Redundant Row 1 data
.clk(clk),
.clk(active_clk),
.en(redundant_data1_en),
.din(redundant_data1_in[38:0]),
.dout(redundant_data[1][38:0]));
rvdffs #(ICCM_BANK_HI) rd_addr_lo_ff (.*, .din(iccm_rw_addr [ICCM_BANK_HI:1]), .dout(iccm_rd_addr_lo_q[ICCM_BANK_HI:1]), .en(1'b1)); // bit 0 of address is always 0
rvdffs #(ICCM_BANK_BITS) rd_addr_hi_ff (.*, .din(addr_bank_inc[ICCM_BANK_HI:2]), .dout(iccm_rd_addr_hi_q[ICCM_BANK_HI:2]), .en(1'b1));
rvdffs #(ICCM_BANK_HI) rd_addr_lo_ff (.*, .clk(active_clk), .din(iccm_rw_addr [ICCM_BANK_HI:1]), .dout(iccm_rd_addr_lo_q[ICCM_BANK_HI:1]), .en(1'b1)); // bit 0 of address is always 0
rvdffs #(ICCM_BANK_BITS) rd_addr_hi_ff (.*, .clk(active_clk), .din(addr_bank_inc[ICCM_BANK_HI:2]), .dout(iccm_rd_addr_hi_q[ICCM_BANK_HI:2]), .en(1'b1));
assign iccm_rd_data_pre[63:0] = {iccm_bank_dout_fn[iccm_rd_addr_hi_q][31:0], iccm_bank_dout_fn[iccm_rd_addr_lo_q[ICCM_BANK_HI:2]][31:0]};
assign iccm_data[63:0] = 64'({16'b0, (iccm_rd_data_pre[63:0] >> (16*iccm_rd_addr_lo_q[1]))});
@ -331,3 +478,4 @@ module ifu_iccm_mem
assign iccm_rd_data_ecc[77:0] = {iccm_bank_dout_fn[iccm_rd_addr_hi_q][38:0], iccm_bank_dout_fn[iccm_rd_addr_lo_q[ICCM_BANK_HI:2]][38:0]};
endmodule // el2_ifu_iccm_mem

119
src/main/resources/vsrc/lsu_dccm_mem.sv
View File

@ -1,5 +1,5 @@
// SPDX-License-Identifier: Apache-2.0
// Copyright 2020 Western Digital Corporation or it's affiliates.
// Copyright 2020 Western Digital Corporation or its affiliates.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@ -27,17 +27,32 @@
// //********************************************************************************
module lsu_dccm_mem
`define EL2_LOCAL_DCCM_RAM_TEST_PORTS .TEST1(TEST1[i]), \
.RME(RME[i]), \
.RM(RM[i][3:0]), \
.LS(LS[i]), \
.DS(DS[i]), \
.SD(SD[i]), \
.TEST_RNM(TEST_RNM[i]), \
.BC1(BC1[i]), \
.BC2(BC2[i]), \
module el2_lsu_dccm_mem
#(
parameter DCCM_BYTE_WIDTH,
parameter DCCM_BITS,
parameter DCCM_NUM_BANKS,
parameter DCCM_BANK_BITS,
parameter DCCM_SIZE,
parameter DCCM_FDATA_WIDTH )(
input logic clk, // clock
input logic rst_l,
input logic clk_override, // clock override
parameter DCCM_FDATA_WIDTH,
parameter DCCM_WIDTH_BITS
)(
input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.
input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in.
input logic rst_l, // reset, active low
input logic clk_override, // Override non-functional clock gating
input logic dccm_wren, // write enable
input logic dccm_rden, // read enable
@ -48,6 +63,15 @@ module lsu_dccm_mem
input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo, // write data
input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi, // write data
//input el2_dccm_ext_in_pkt_t [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt, // the dccm packet from the soc
input [ICCM_NUM_BANKS-1:0] dccm_TEST1,
input [ICCM_NUM_BANKS-1:0] RME,
input [ICCM_NUM_BANKS-1:0][3:0] RM,
input [ICCM_NUM_BANKS-1:0] LS,
input [ICCM_NUM_BANKS-1:0] DS,
input [ICCM_NUM_BANKS-1:0] TEST-RNM,
input [ICCM_NUM_BANKS-1:0] BC1,
input [ICCM_NUM_BANKS-1:0] BC2,
output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo, // read data from the lo bank
output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi, // read data from the hi bank
@ -55,44 +79,43 @@ module lsu_dccm_mem
);
localparam DCCM_WIDTH_BITS = $clog2(DCCM_BYTE_WIDTH);
localparam DCCM_WIDTH_BITS_INT = $clog2(DCCM_BYTE_WIDTH);
localparam DCCM_INDEX_BITS = (DCCM_BITS - DCCM_BANK_BITS - DCCM_WIDTH_BITS);
localparam DCCM_INDEX_DEPTH = ((DCCM_SIZE)*1024)/((DCCM_BYTE_WIDTH)*(DCCM_NUM_BANKS)); // Depth of memory bank
logic [DCCM_NUM_BANKS-1:0] wren_bank;
logic [DCCM_NUM_BANKS-1:0] rden_bank;
logic [DCCM_NUM_BANKS-1:0] [DCCM_BITS-1:(DCCM_BANK_BITS+2)] addr_bank;
logic [DCCM_BITS-1:(DCCM_BANK_BITS+DCCM_WIDTH_BITS)] rd_addr_even, rd_addr_odd;
logic [DCCM_BITS-1:(DCCM_BANK_BITS+DCCM_WIDTH_BITS_INT)] rd_addr_even, rd_addr_odd;
logic rd_unaligned, wr_unaligned;
logic [DCCM_NUM_BANKS-1:0] [DCCM_FDATA_WIDTH-1:0] dccm_bank_dout;
logic [DCCM_FDATA_WIDTH-1:0] wrdata;
logic [DCCM_NUM_BANKS-1:0][DCCM_FDATA_WIDTH-1:0] wr_data_bank;
logic [(DCCM_WIDTH_BITS+DCCM_BANK_BITS-1):DCCM_WIDTH_BITS] dccm_rd_addr_lo_q;
logic [(DCCM_WIDTH_BITS+DCCM_BANK_BITS-1):DCCM_WIDTH_BITS] dccm_rd_addr_hi_q;
logic [(DCCM_WIDTH_BITS_INT+DCCM_BANK_BITS-1):DCCM_WIDTH_BITS_INT] dccm_rd_addr_lo_q;
logic [(DCCM_WIDTH_BITS_INT+DCCM_BANK_BITS-1):DCCM_WIDTH_BITS_INT] dccm_rd_addr_hi_q;
logic [DCCM_NUM_BANKS-1:0] dccm_clken;
assign rd_unaligned = (dccm_rd_addr_lo[DCCM_WIDTH_BITS+:DCCM_BANK_BITS] != dccm_rd_addr_hi[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]);
assign wr_unaligned = (dccm_wr_addr_lo[DCCM_WIDTH_BITS+:DCCM_BANK_BITS] != dccm_wr_addr_hi[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]);
assign rd_unaligned = (dccm_rd_addr_lo[DCCM_WIDTH_BITS_INT+:DCCM_BANK_BITS] != dccm_rd_addr_hi[DCCM_WIDTH_BITS_INT+:DCCM_BANK_BITS]);
assign wr_unaligned = (dccm_wr_addr_lo[DCCM_WIDTH_BITS_INT+:DCCM_BANK_BITS] != dccm_wr_addr_hi[DCCM_WIDTH_BITS_INT+:DCCM_BANK_BITS]);
// Align the read data
assign dccm_rd_data_lo[DCCM_FDATA_WIDTH-1:0] = dccm_bank_dout[dccm_rd_addr_lo_q[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]][DCCM_FDATA_WIDTH-1:0];
assign dccm_rd_data_hi[DCCM_FDATA_WIDTH-1:0] = dccm_bank_dout[dccm_rd_addr_hi_q[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]][DCCM_FDATA_WIDTH-1:0];
assign dccm_rd_data_hi[DCCM_FDATA_WIDTH-1:0] = dccm_bank_dout[dccm_rd_addr_hi_q[DCCM_WIDTH_BITS_INT+:DCCM_BANK_BITS]][DCCM_FDATA_WIDTH-1:0];
// Generate even/odd address
// 8 Banks, 16KB each (2048 x 72)
for (genvar i=0; i<32'(DCCM_NUM_BANKS); i++) begin: mem_bank
for (genvar i=0; i<DCCM_NUM_BANKS; i++) begin: mem_bank
assign wren_bank[i] = dccm_wren & ((dccm_wr_addr_hi[2+:DCCM_BANK_BITS] == i) | (dccm_wr_addr_lo[2+:DCCM_BANK_BITS] == i));
assign rden_bank[i] = dccm_rden & ((dccm_rd_addr_hi[2+:DCCM_BANK_BITS] == i) | (dccm_rd_addr_lo[2+:DCCM_BANK_BITS] == i));
assign addr_bank[i][(DCCM_BANK_BITS+DCCM_WIDTH_BITS)+:DCCM_INDEX_BITS] = wren_bank[i] ? (((dccm_wr_addr_hi[2+:DCCM_BANK_BITS] == i) & wr_unaligned) ?
dccm_wr_addr_hi[(DCCM_BANK_BITS+DCCM_WIDTH_BITS)+:DCCM_INDEX_BITS] :
dccm_wr_addr_lo[(DCCM_BANK_BITS+DCCM_WIDTH_BITS)+:DCCM_INDEX_BITS]) :
assign addr_bank[i][(DCCM_BANK_BITS+DCCM_WIDTH_BITS_INT)+:DCCM_INDEX_BITS] = wren_bank[i] ? (((dccm_wr_addr_hi[2+:DCCM_BANK_BITS] == i) & wr_unaligned) ?
dccm_wr_addr_hi[(DCCM_BANK_BITS+DCCM_WIDTH_BITS_INT)+:DCCM_INDEX_BITS] :
dccm_wr_addr_lo[(DCCM_BANK_BITS+DCCM_WIDTH_BITS_INT)+:DCCM_INDEX_BITS]) :
(((dccm_rd_addr_hi[2+:DCCM_BANK_BITS] == i) & rd_unaligned) ?
dccm_rd_addr_hi[(DCCM_BANK_BITS+DCCM_WIDTH_BITS)+:DCCM_INDEX_BITS] :
dccm_rd_addr_lo[(DCCM_BANK_BITS+DCCM_WIDTH_BITS)+:DCCM_INDEX_BITS]);
dccm_rd_addr_hi[(DCCM_BANK_BITS+DCCM_WIDTH_BITS_INT)+:DCCM_INDEX_BITS] :
dccm_rd_addr_lo[(DCCM_BANK_BITS+DCCM_WIDTH_BITS_INT)+:DCCM_INDEX_BITS]);
assign wr_data_bank[i] = ((dccm_wr_addr_hi[2+:DCCM_BANK_BITS] == i) & wr_unaligned) ? dccm_wr_data_hi[DCCM_FDATA_WIDTH-1:0] : dccm_wr_data_lo[DCCM_FDATA_WIDTH-1:0];
@ -101,6 +124,7 @@ module lsu_dccm_mem
// end clock gating section
`ifdef VERILATOR
el2_ram #(DCCM_INDEX_DEPTH,39) ram (
// Primary ports
.ME(dccm_clken[i]),
@ -109,10 +133,13 @@ module lsu_dccm_mem
.ADR(addr_bank[i]),
.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ),
// These are used by SoC
`EL2_LOCAL_DCCM_RAM_TEST_PORTS
.*
);
`else
if (DCCM_INDEX_DEPTH == 32768) begin : dccm
ram_32768x39 dccm_bank (
// Primary ports
@ -122,6 +149,9 @@ module lsu_dccm_mem
.ADR(addr_bank[i]),
.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ),
// These are used by SoC
`EL2_LOCAL_DCCM_RAM_TEST_PORTS
.*
);
end
@ -134,6 +164,9 @@ module lsu_dccm_mem
.ADR(addr_bank[i]),
.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ),
// These are used by SoC
`EL2_LOCAL_DCCM_RAM_TEST_PORTS
.*
);
end
@ -146,6 +179,9 @@ module lsu_dccm_mem
.ADR(addr_bank[i]),
.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ),
// These are used by SoC
`EL2_LOCAL_DCCM_RAM_TEST_PORTS
.*
);
end
@ -158,6 +194,9 @@ module lsu_dccm_mem
.ADR(addr_bank[i]),
.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ),
// These are used by SoC
`EL2_LOCAL_DCCM_RAM_TEST_PORTS
.*
);
end
@ -170,6 +209,9 @@ module lsu_dccm_mem
.ADR(addr_bank[i]),
.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ),
// These are used by SoC
`EL2_LOCAL_DCCM_RAM_TEST_PORTS
.*
);
end
@ -182,6 +224,9 @@ module lsu_dccm_mem
.ADR(addr_bank[i]),
.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ),
// These are used by SoC
`EL2_LOCAL_DCCM_RAM_TEST_PORTS
.*
);
end
@ -194,6 +239,9 @@ module lsu_dccm_mem
.ADR(addr_bank[i]),
.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ),
// These are used by SoC
`EL2_LOCAL_DCCM_RAM_TEST_PORTS
.*
);
end
@ -206,6 +254,9 @@ module lsu_dccm_mem
.ADR(addr_bank[i]),
.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ),
// These are used by SoC
`EL2_LOCAL_DCCM_RAM_TEST_PORTS
.*
);
end
@ -218,18 +269,38 @@ module lsu_dccm_mem
.ADR(addr_bank[i]),
.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ),
// These are used by SoC
`EL2_LOCAL_DCCM_RAM_TEST_PORTS
.*
);
end
`endif // VERILATOR
else if (DCCM_INDEX_DEPTH == 128) begin : dccm
ram_128x39 dccm_bank (
// Primary ports
.ME(dccm_clken[i]),
.CLK(clk),
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ),
// These are used by SoC
`EL2_LOCAL_DCCM_RAM_TEST_PORTS
.*
);
end
`endif
end : mem_bank
// Flops
rvdffs #(DCCM_BANK_BITS) rd_addr_lo_ff (.*, .din(dccm_rd_addr_lo[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]), .dout(dccm_rd_addr_lo_q[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]), .en(1'b1));
rvdffs #(DCCM_BANK_BITS) rd_addr_hi_ff (.*, .din(dccm_rd_addr_hi[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]), .dout(dccm_rd_addr_hi_q[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]), .en(1'b1));
rvdff #(DCCM_BANK_BITS) rd_addr_lo_ff (.*, .din(dccm_rd_addr_lo[DCCM_WIDTH_BITS_INT+:DCCM_BANK_BITS]), .dout(dccm_rd_addr_lo_q[DCCM_WIDTH_BITS_INT+:DCCM_BANK_BITS]), .clk(active_clk));
rvdff #(DCCM_BANK_BITS) rd_addr_hi_ff (.*, .din(dccm_rd_addr_hi[DCCM_WIDTH_BITS_INT+:DCCM_BANK_BITS]), .dout(dccm_rd_addr_hi_q[DCCM_WIDTH_BITS_INT+:DCCM_BANK_BITS]), .clk(active_clk));
`undef EL2_LOCAL_DCCM_RAM_TEST_PORTS
endmodule // el2_lsu_dccm_mem

79
src/main/resources/vsrc/mem.sv
View File

@ -1,35 +1,21 @@
//********************************************************************************
// SPDX-License-Identifier: Apache-2.0
// Copyright 2020 Western Digital Corporation or its affiliates.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//********************************************************************************
module mem #(
parameter ICACHE_BEAT_BITS,
parameter ICCM_BITS,
parameter ICACHE_NUM_WAYS,
parameter DCCM_BYTE_WIDTH,
parameter ICCM_BANK_INDEX_LO,
parameter ICACHE_BANK_BITS,
parameter DCCM_BITS,
parameter ICACHE_BEAT_ADDR_HI,
parameter ICCM_INDEX_BITS,
parameter ICCM_BANK_HI,
parameter ICACHE_BANKS_WAY,
parameter ICACHE_INDEX_HI,
parameter DCCM_NUM_BANKS,
parameter ICACHE_BANK_HI,
parameter ICACHE_BANK_LO,
parameter DCCM_ENABLE= 'b1,
parameter ICACHE_TAG_LO,
parameter ICACHE_DATA_INDEX_LO,
parameter ICCM_NUM_BANKS,
parameter ICACHE_ECC,
parameter ICACHE_ENABLE= 'b1,
parameter DCCM_BANK_BITS,
parameter ICCM_ENABLE= 'b1,
parameter ICCM_BANK_BITS,
parameter ICACHE_TAG_DEPTH,
parameter ICACHE_WAYPACK,
parameter DCCM_SIZE,
parameter DCCM_FDATA_WIDTH,
parameter ICACHE_TAG_INDEX_LO,
parameter ICACHE_DATA_DEPTH)
module mem
(
input logic clk,
input logic rst_l,
@ -52,10 +38,12 @@ module mem #(
output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi,
//`ifdef DCCM_ENABLE
input dccm_ext_in_pkt_t [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt,
//`endif
//ICCM ports
input ccm_ext_in_pkt_t [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt,
input logic [ICCM_BITS-1:1] iccm_rw_addr,
input logic iccm_buf_correct_ecc, // ICCM is doing a single bit error correct cycle
@ -76,9 +64,10 @@ module mem #(
input logic ic_rd_en,
input logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache.
input logic ic_sel_premux_data, // Premux data sel
input ic_data_ext_in_pkt_t [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt,
input ic_tag_ext_in_pkt_t [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt,
input logic [70:0] ic_wr_data_0, // Data to fill to the Icache. With ECC
input logic [70:0] ic_wr_data_1,
input logic [ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data, // Data to fill to the Icache. With ECC
input logic [70:0] ic_debug_wr_data, // Debug wr cache.
output logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
input logic [ICACHE_INDEX_HI:3] ic_debug_addr, // Read/Write addresss to the Icache.
@ -88,7 +77,7 @@ module mem #(
input logic [ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr.
output logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
output logic [25:0] ic_tag_debug_rd_data,// Debug icache tag.
output logic [25:0] ictag_debug_rd_data,// Debug icache tag.
output logic [ICACHE_BANKS_WAY-1:0] ic_eccerr, // ecc error per bank
@ -101,18 +90,19 @@ module mem #(
);
logic [ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data;
assign ic_wr_data [0] = ic_wr_data_0;
assign ic_wr_data [1] = ic_wr_data_1;
logic active_clk;
rvoclkhdr active_cg ( .en(1'b1), .l1clk(active_clk), .* );
// DCCM Instantiation
if (DCCM_ENABLE == 1) begin: Gen_dccm_enable
lsu_dccm_mem #(
lsu_dccm_mem dccm #(
.DCCM_BYTE_WIDTH(DCCM_BYTE_WIDTH),
.DCCM_BITS(DCCM_BITS),
.DCCM_NUM_BANKS(DCCM_NUM_BANKS),
.DCCM_BANK_BITS(DCCM_BANK_BITS),
.DCCM_SIZE(DCCM_SIZE),
.DCCM_FDATA_WIDTH(DCCM_FDATA_WIDTH)) dccm (
.DCCM_FDATA_WIDTH(DCCM_FDATA_WIDTH),
.DCCM_WIDTH_BITS(DCCM_WIDTH_BITS))(
.clk_override(dccm_clk_override),
.*
);
@ -137,7 +127,13 @@ if ( ICACHE_ENABLE ) begin: icache
.ICACHE_TAG_DEPTH(ICACHE_TAG_DEPTH),
.ICACHE_WAYPACK(ICACHE_WAYPACK),
.ICACHE_TAG_INDEX_LO(ICACHE_TAG_INDEX_LO),
.ICACHE_DATA_DEPTH(ICACHE_DATA_DEPTH)) icm (
.ICACHE_DATA_DEPTH(ICACHE_DATA_DEPTH),
.ICACHE_TAG_NUM_BYPASS(ICACHE_TAG_NUM_BYPASS),
.ICACHE_TAG_NUM_BYPASS_WIDTH(ICACHE_TAG_NUM_BYPASS_WIDTH),
.ICACHE_TAG_BYPASS_ENABLE(ICACHE_TAG_BYPASS_ENABLE),
.ICACHE_NUM_BYPASS_WIDTH(ICACHE_NUM_BYPASS_WIDTH),
.ICACHE_BYPASS_ENABLE(ICACHE_BYPASS_ENABLE),
.ICACHE_LN_SZ(ICACHE_LN_SZ)) icm (
.clk_override(icm_clk_override),
.*
);
@ -146,7 +142,7 @@ else begin
assign ic_rd_hit[ICACHE_NUM_WAYS-1:0] = '0;
assign ic_tag_perr = '0 ;
assign ic_rd_data = '0 ;
assign ic_tag_debug_rd_data = '0 ;
assign ictag_debug_rd_data = '0 ;
end // else: !if( ICACHE_ENABLE )
@ -171,3 +167,4 @@ end
endmodule

55
src/main/resources/vsrc/mem_lib.sv
View File

@ -16,7 +16,17 @@
`define EL2_LOCAL_RAM_TEST_IO \
input logic WE, \
input logic ME, \
input logic CLK
input logic CLK, \
input logic TEST1, \
input logic RME, \
input logic [3:0] RM, \
input logic LS, \
input logic DS, \
input logic SD, \
input logic TEST_RNM, \
input logic BC1, \
input logic BC2, \
output logic ROP
`define EL2_RAM(depth, width) \
module ram_``depth``x``width( \
@ -26,11 +36,22 @@ module ram_``depth``x``width( \
`EL2_LOCAL_RAM_TEST_IO \
); \
reg [(width-1):0] ram_core [(depth-1):0]; \
\
`ifdef GTLSIM \
integer i; \
initial begin \
for (i=0; i<depth; i=i+1) \
ram_core[i] = '0; \
end \
`endif \
always @(posedge CLK) begin \
if (ME && WE) ram_core[ADR] = D; \
`ifdef GTLSIM \
if (ME && WE) ram_core[ADR] <= D; \
`else \
if (ME && WE) begin ram_core[ADR] <= D; Q <= 'x; end \
`endif \
if (ME && ~WE) Q <= ram_core[ADR]; \
end \
assign ROP = ME; \
\
endmodule
@ -42,12 +63,22 @@ module ram_be_``depth``x``width( \
`EL2_LOCAL_RAM_TEST_IO \
); \
reg [(width-1):0] ram_core [(depth-1):0]; \
\
`ifdef GTLSIM \
integer i; \
initial begin \
for (i=0; i<depth; i=i+1) \
ram_core[i] = '0; \
end \
`endif \
always @(posedge CLK) begin \
if (ME && WE) ram_core[ADR] = D & WEM | ~WEM & ram_core[ADR];\
`ifdef GTLSIM \
if (ME && WE) ram_core[ADR] <= D & WEM | ~WEM & ram_core[ADR]; \
`else \
if (ME && WE) begin ram_core[ADR] <= D & WEM | ~WEM & ram_core[ADR]; Q <= 'x; end \
`endif \
if (ME && ~WE) Q <= ram_core[ADR]; \
end \
\
assign ROP = ME; \
\
endmodule
@ -61,7 +92,11 @@ output logic [(width-1):0] Q,
reg [(width-1):0] ram_core [(depth-1):0];
always @(posedge CLK) begin
if (ME && WE) ram_core[ADR] = D;
`ifdef GTLSIM
if (ME && WE) ram_core[ADR] <= D;
`else
if (ME && WE) begin ram_core[ADR] <= D; Q <= 'x; end
`endif
if (ME && ~WE) Q <= ram_core[ADR];
end
endmodule
@ -172,6 +207,7 @@ endmodule
`EL2_RAM_BE(256, 52)
`EL2_RAM_BE(128, 52)
`EL2_RAM_BE(64, 52)
`EL2_RAM_BE(32, 52)
`EL2_RAM_BE(4096, 104)
`EL2_RAM_BE(2048, 104)
`EL2_RAM_BE(1024, 104)
@ -179,6 +215,7 @@ endmodule
`EL2_RAM_BE(256, 104)
`EL2_RAM_BE(128, 104)
`EL2_RAM_BE(64, 104)
`EL2_RAM_BE(32, 104)
`EL2_RAM_BE(4096, 44)
`EL2_RAM_BE(2048, 44)
`EL2_RAM_BE(1024, 44)
@ -186,6 +223,7 @@ endmodule
`EL2_RAM_BE(256, 44)
`EL2_RAM_BE(128, 44)
`EL2_RAM_BE(64, 44)
`EL2_RAM_BE(32, 44)
`EL2_RAM_BE(4096, 88)
`EL2_RAM_BE(2048, 88)
`EL2_RAM_BE(1024, 88)
@ -193,6 +231,8 @@ endmodule
`EL2_RAM_BE(256, 88)
`EL2_RAM_BE(128, 88)
`EL2_RAM_BE(64, 88)
`EL2_RAM_BE(32, 88)
`EL2_RAM(64, 39)
`undef EL2_RAM
@ -200,3 +240,4 @@ endmodule
`undef EL2_LOCAL_RAM_TEST_IO

1
src/main/resources/vsrc/mem_mod.sv
View File

@ -62,3 +62,4 @@ module el2_btb_ghr_hash #(
endmodule

16
src/main/scala/ifu/ifu.scala
View File

@ -42,7 +42,6 @@ class ifu extends Module with lib with RequireAsyncReset {
val ifc_ctl = Module(new ifu_ifc_ctl)
// IFC wiring Inputs
//ifc_ctl.io.active_clk := io.active_clk
ifc_ctl.io.free_l2clk := io.free_l2clk
ifc_ctl.io.scan_mode := io.scan_mode
ifc_ctl.io.ic_hit_f := mem_ctl.io.ic_hit_f
@ -76,21 +75,7 @@ class ifu extends Module with lib with RequireAsyncReset {
aln_ctl.io.ifu_bp_ret_f := bp_ctl.io.ifu_bp_ret_f
aln_ctl.io.exu_flush_final := io.exu_flush_final
aln_ctl.io.dec_aln <> io.ifu_dec.dec_aln
// io.ifu_dec.dec_aln.aln_dec.ifu_i0_cinst := aln_ctl.io.ifu_i0_cinst
// io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf := aln_ctl.io.ifu_i0_icaf
// io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_type := aln_ctl.io.ifu_i0_icaf_type
// io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_second := aln_ctl.io.ifu_i0_icaf_second
// io.ifu_dec.dec_aln.aln_ib.ifu_i0_dbecc := aln_ctl.io.ifu_i0_dbecc
// io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_index := aln_ctl.io.ifu_i0_bp_index
io.ifu_i0_fa_index := aln_ctl.io.ifu_i0_fa_index
// io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_fghr := aln_ctl.io.ifu_i0_bp_fghr
// io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_btag := aln_ctl.io.ifu_i0_bp_btag
// io.ifu_dec.dec_aln.aln_ib.ifu_i0_valid := aln_ctl.io.ifu_i0_valid
// io.ifu_dec.dec_aln.aln_ib.ifu_i0_instr := aln_ctl.io.ifu_i0_instr
// io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc := aln_ctl.io.ifu_i0_pc
// io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc4 := aln_ctl.io.ifu_i0_pc4
// io.ifu_dec.dec_aln.ifu_pmu_instr_aligned := aln_ctl.io.ifu_pmu_instr_aligned
// aln_ctl.io.i0_brp <> io.ifu_dec.dec_aln.aln_ib.i0_brp
aln_ctl.io.dec_i0_decode_d := io.dec_i0_decode_d
aln_ctl.io.ifu_bp_fa_index_f := bp_ctl.io.ifu_bp_fa_index_f
@ -100,7 +85,6 @@ class ifu extends Module with lib with RequireAsyncReset {
// BP wiring Inputs
bp_ctl.io.scan_mode := io.scan_mode
// bp_ctl.io.active_clk := io.active_clk
bp_ctl.io.ic_hit_f := mem_ctl.io.ic_hit_f
bp_ctl.io.ifc_fetch_addr_f := ifc_ctl.io.ifc_fetch_addr_f
bp_ctl.io.ifc_fetch_req_f := ifc_ctl.io.ifc_fetch_req_f

23
src/main/scala/include/bundle.scala
View File

@ -182,11 +182,6 @@ class lsu_dec extends Bundle {
val tlu_busbuff = new tlu_busbuff
val dctl_busbuff = new dctl_busbuff
}
class dbg_dma extends Bundle {
val dbg_dma_bubble = Input(Bool()) // Debug needs a bubble to send a valid
val dma_dbg_ready = Output(Bool()) // DMA is ready to accept debug request
}
class tlu_busbuff extends Bundle {
val lsu_pmu_bus_trxn = Output(Bool())
@ -225,6 +220,17 @@ class iccm_mem extends Bundle with lib {
val rd_data = Input(UInt(64.W))
val rd_data_ecc = Input(UInt(78.W))
}
class ext_in_pkt_t(val size :Int) extends Bundle{
val TEST1 = UInt(size.W)
val RME = UInt(size.W)
val RM = Vec(size,UInt(4.W))
val LS = UInt(size.W)
val DS = UInt(size.W)
val SD = UInt(size.W)
val TEST_RNM = UInt(size.W)
val BC1 = UInt(size.W)
val BC2 = UInt(size.W)
}
class ic_mem extends Bundle with lib {
val rw_addr = Output(UInt(31.W))
val tag_valid = Output(UInt(ICACHE_NUM_WAYS.W))
@ -246,6 +252,7 @@ class ic_mem extends Bundle with lib {
val debug_way = Output(UInt(ICACHE_NUM_WAYS.W))
val premux_data = Output(UInt(64.W))
val sel_premux_data = Output(Bool())
}
class aln_ib extends Bundle with lib{
val ifu_i0_icaf = Output(Bool())
@ -322,6 +329,12 @@ class dbg_ib extends Bundle{
val dbg_cmd_addr = Input(UInt(32.W)) // command address
}
class dbg_dma extends Bundle {
val dbg_dma_bubble = Input(Bool()) // Debug needs a bubble to send a valid
val dma_dbg_ready = Output(Bool()) // DMA is ready to accept debug request
}
class dbg_dctl extends Bundle{
val dbg_cmd_wrdata = Input(UInt(32.W)) // command write data, for fence/fence_i
}

7
src/main/scala/lib/lib.scala
View File

@ -408,6 +408,13 @@ trait lib extends param{
else dout := withClock(clk) {RegNext (Mux(en,din,dout) & !clear, 0.U)}
dout
}
def apply(din: Bool, en:Bool,clear: UInt, clk: Clock, clken: Bool,rawclk:Clock) = {
val dout =Wire(Bool())
if (RV_FPGA_OPTIMIZE)
dout := withClock (rawclk) {RegEnable ((din & Fill(din.getWidth,!clear)), 0.B, ((en|clear)& clken))}
else dout := withClock(clk) {RegNext (Mux(en,din,dout) & !clear, 0.B)}
dout
}
}
////rvdffe ///////////////////////////////////////////////////////////////////////
object rvdffe {

12
src/main/scala/mem.scala
View File

@ -25,6 +25,11 @@ class Mem_bundle extends Bundle with lib {
val icm_clk_override = Input(Bool())
val dec_tlu_core_ecc_disable = Input(Bool())
val dccm = new mem_lsu()
val dccm_ext_in_pkt = Input(new ext_in_pkt_t(DCCM_NUM_BANKS))
val iccm_ext_in_pkt = Input(new ext_in_pkt_t(ICCM_NUM_BANKS))
val ic_data_ext_in_pkt = Input(Vec(ICACHE_NUM_WAYS,new ext_in_pkt_t(ICACHE_NUM_WAYS)))
val ic_tag_ext_in_pkt = Input(new ext_in_pkt_t(ICACHE_NUM_WAYS))
val iccm = Flipped(new iccm_mem())
val ic = Flipped (new ic_mem())
val scan_mode = Input(Bool())
@ -45,20 +50,27 @@ object quasar extends lib {
"ICACHE_BANK_LO" -> ICACHE_BANK_LO,
"ICACHE_BANK_HI" -> ICACHE_BANK_HI,
"ICACHE_WAYPACK" -> ICACHE_WAYPACK,
"ICACHE_NUM_BYPASS_WIDTH" -> ICACHE_NUM_BYPASS_WIDTH,
"ICACHE_BYPASS_ENABLE" -> ICACHE_BYPASS_ENABLE,
"ICACHE_ECC" -> ICACHE_ECC,
"ICACHE_DATA_DEPTH" -> ICACHE_DATA_DEPTH,
"ICACHE_BANK_BITS" -> ICACHE_BANK_BITS,
"ICACHE_BEAT_ADDR_HI" -> ICACHE_BEAT_ADDR_HI,
"ICACHE_BEAT_BITS" -> ICACHE_BEAT_BITS,
"ICACHE_TAG_DEPTH" -> ICACHE_TAG_DEPTH,
"ICACHE_TAG_NUM_BYPASS" -> ICACHE_TAG_NUM_BYPASS,
"ICACHE_TAG_NUM_BYPASS_WIDTH" -> ICACHE_TAG_NUM_BYPASS_WIDTH,
"ICACHE_TAG_BYPASS_ENABLE" -> ICACHE_TAG_BYPASS_ENABLE,
"ICCM_BANK_INDEX_LO" -> ICCM_BANK_INDEX_LO,
"ICCM_NUM_BANKS" -> ICCM_NUM_BANKS,
"ICACHE_LN_SZ" -> ICACHE_LN_SZ,
"ICCM_BANK_HI" -> ICCM_BANK_HI,
"ICCM_INDEX_BITS" -> ICCM_INDEX_BITS,
"ICCM_BANK_BITS" -> ICCM_BANK_BITS,
"DCCM_BYTE_WIDTH" -> DCCM_BYTE_WIDTH,
"DCCM_BANK_BITS" -> DCCM_BANK_BITS,
"DCCM_SIZE" -> DCCM_SIZE,
"DCCM_WIDTH_BITS" -> DCCM_WIDTH_BITS,
"DCCM_NUM_BANKS" -> DCCM_NUM_BANKS)) with HasBlackBoxResource {
val io = IO(new Mem_bundle)
addResource("/vsrc/mem.sv")

337
src/main/scala/quasar_wrapper.scala
View File

@ -1,165 +1,174 @@
//import chisel3._
//import mem._
//import chisel3.util._
//import dmi._
//import include._
//import lib._
//class quasar_wrapper extends Module with lib with RequireAsyncReset {
// val io = IO(new Bundle{
// val dbg_rst_l = Input(AsyncReset())
// val rst_vec = Input(UInt(31.W))
// val nmi_int = Input(Bool())
// val nmi_vec = Input(UInt(31.W))
// val jtag_id = Input(UInt(31.W))
//
// // AXI Signals
// val lsu_brg = bridge_gen(LSU_BUS_TAG, false)
// val ifu_brg = bridge_gen(IFU_BUS_TAG, false)
// val sb_brg = bridge_gen(SB_BUS_TAG , false)
// val dma_brg = bridge_gen(DMA_BUS_TAG, true)
//
// val lsu_bus_clk_en = Input(Bool())
// val ifu_bus_clk_en = Input(Bool())
// val dbg_bus_clk_en = Input(Bool())
// val dma_bus_clk_en = Input(Bool())
//
// val timer_int = Input(Bool())
// val soft_int = Input(Bool())
//
// val extintsrc_req = Input(UInt(PIC_TOTAL_INT.W))
//
// val dec_tlu_perfcnt0 = Output(Bool())
// val dec_tlu_perfcnt1 = Output(Bool())
// val dec_tlu_perfcnt2 = Output(Bool())
// val dec_tlu_perfcnt3 = Output(Bool())
//
// val jtag_tck = Input(Clock())
// val jtag_tms = Input(Bool())
// val jtag_tdi = Input(Bool())
// val jtag_trst_n = Input(Bool())
// val jtag_tdo = Output(Bool())
//
// val core_id = Input(UInt(28.W))
//
// val mpc_debug_halt_req = Input(Bool())
// val mpc_debug_run_req = Input(Bool())
// val mpc_reset_run_req = Input(Bool())
// val mpc_debug_halt_ack = Output(Bool())
// val mpc_debug_run_ack = Output(Bool())
// val debug_brkpt_status = Output(Bool())
//
// val i_cpu_halt_req = Input(Bool())
// val i_cpu_run_req = Input(Bool())
// val o_cpu_halt_ack = Output(Bool())
// val o_cpu_halt_status = Output(Bool())
// val o_debug_mode_status = Output(Bool())
// val o_cpu_run_ack = Output(Bool())
// val mbist_mode = Input(Bool())
//
// val rv_trace_pkt = new trace_pkt_t()
// val scan_mode = Input(Bool())
//
// })
// val mem = Module(new quasar.mem())
// val dmi_wrapper = Module(new dmi_wrapper())
// val core = Module(new quasar())
// core.io.scan_mode := io.scan_mode
// dmi_wrapper.io.trst_n := io.jtag_trst_n
// dmi_wrapper.io.tck := io.jtag_tck
// dmi_wrapper.io.tms := io.jtag_tms
// dmi_wrapper.io.tdi := io.jtag_tdi
// dmi_wrapper.io.core_clk := clock
// dmi_wrapper.io.jtag_id := io.jtag_id
// dmi_wrapper.io.rd_data := core.io.dmi_reg_rdata
// dmi_wrapper.io.core_rst_n := io.dbg_rst_l
// core.io.dmi_reg_wdata := dmi_wrapper.io.reg_wr_data
// core.io.dmi_reg_addr := dmi_wrapper.io.reg_wr_addr
// core.io.dmi_reg_en := dmi_wrapper.io.reg_en
// core.io.dmi_reg_wr_en := dmi_wrapper.io.reg_wr_en
import chisel3._
import mem._
import chisel3.util._
import dmi._
import include._
import lib._
class quasar_wrapper extends Module with lib with RequireAsyncReset {
val io = IO(new Bundle{
val dbg_rst_l = Input(AsyncReset())
val rst_vec = Input(UInt(31.W))
val nmi_int = Input(Bool())
val nmi_vec = Input(UInt(31.W))
val jtag_id = Input(UInt(31.W))
// AXI Signals
val lsu_brg = bridge_gen(LSU_BUS_TAG, false)
val ifu_brg = bridge_gen(IFU_BUS_TAG, false)
val sb_brg = bridge_gen(SB_BUS_TAG , false)
val dma_brg = bridge_gen(DMA_BUS_TAG, true)
val lsu_bus_clk_en = Input(Bool())
val ifu_bus_clk_en = Input(Bool())
val dbg_bus_clk_en = Input(Bool())
val dma_bus_clk_en = Input(Bool())
val timer_int = Input(Bool())
val soft_int = Input(Bool())
val extintsrc_req = Input(UInt(PIC_TOTAL_INT.W))
val dec_tlu_perfcnt0 = Output(Bool())
val dec_tlu_perfcnt1 = Output(Bool())
val dec_tlu_perfcnt2 = Output(Bool())
val dec_tlu_perfcnt3 = Output(Bool())
val jtag_tck = Input(Clock())
val jtag_tms = Input(Bool())
val jtag_tdi = Input(Bool())
val jtag_trst_n = Input(Bool())
val jtag_tdo = Output(Bool())
val core_id = Input(UInt(28.W))
val mpc_debug_halt_req = Input(Bool())
val mpc_debug_run_req = Input(Bool())
val mpc_reset_run_req = Input(Bool())
val mpc_debug_halt_ack = Output(Bool())
val mpc_debug_run_ack = Output(Bool())
val debug_brkpt_status = Output(Bool())
val i_cpu_halt_req = Input(Bool())
val i_cpu_run_req = Input(Bool())
val o_cpu_halt_ack = Output(Bool())
val o_cpu_halt_status = Output(Bool())
val o_debug_mode_status = Output(Bool())
val o_cpu_run_ack = Output(Bool())
val mbist_mode = Input(Bool())
val dccm_ext_in_pkt = Input(new ext_in_pkt_t(DCCM_NUM_BANKS))
val iccm_ext_in_pkt = Input(new ext_in_pkt_t(ICCM_NUM_BANKS))
val ic_data_ext_in_pkt = Input(Vec(ICACHE_NUM_WAYS,new ext_in_pkt_t(ICACHE_NUM_WAYS)))
val ic_tag_ext_in_pkt = Input(new ext_in_pkt_t(ICACHE_NUM_WAYS))
val rv_trace_pkt = new trace_pkt_t()
val scan_mode = Input(Bool())
})
val mem = Module(new quasar.mem())
val dmi_wrapper = Module(new dmi_wrapper())
val core = Module(new quasar())
core.io.scan_mode := io.scan_mode
dmi_wrapper.io.trst_n := io.jtag_trst_n
dmi_wrapper.io.tck := io.jtag_tck
dmi_wrapper.io.tms := io.jtag_tms
dmi_wrapper.io.tdi := io.jtag_tdi
dmi_wrapper.io.core_clk := clock
dmi_wrapper.io.jtag_id := io.jtag_id
dmi_wrapper.io.rd_data := core.io.dmi_reg_rdata
dmi_wrapper.io.core_rst_n := io.dbg_rst_l
core.io.dmi_reg_wdata := dmi_wrapper.io.reg_wr_data
core.io.dmi_reg_addr := dmi_wrapper.io.reg_wr_addr
core.io.dmi_reg_en := dmi_wrapper.io.reg_en
core.io.dmi_reg_wr_en := dmi_wrapper.io.reg_wr_en
// core.io.dmi_hard_reset := dmi_wrapper.io.dmi_hard_reset
// io.jtag_tdo := dmi_wrapper.io.tdo
//
// // Memory signals
// mem.io.dccm_clk_override := core.io.dccm_clk_override
// mem.io.icm_clk_override := core.io.icm_clk_override
// mem.io.dec_tlu_core_ecc_disable := core.io.dec_tlu_core_ecc_disable
// mem.io.dccm <> core.io.dccm
// mem.io.rst_l := reset
// mem.io.clk := clock
// mem.io.scan_mode := io.scan_mode
// // Memory outputs
// core.io.dbg_rst_l := io.dbg_rst_l
// core.io.ic <> mem.io.ic
// core.io.iccm <> mem.io.iccm
//
//
// if(BUILD_AXI4) {
// core.io.ifu_ahb <> 0.U.asTypeOf(core.io.ifu_ahb)
// core.io.lsu_ahb <> 0.U.asTypeOf(core.io.lsu_ahb)
// core.io.sb_ahb <> 0.U.asTypeOf(core.io.sb_ahb)
// core.io.dma_ahb <> 0.U.asTypeOf(core.io.dma_ahb)
//
// core.io.lsu_axi <> io.lsu_brg
// core.io.ifu_axi <> io.ifu_brg
// core.io.sb_axi <> io.sb_brg
// core.io.dma_axi <> io.dma_brg
// }
// else {
// core.io.ifu_ahb <> io.ifu_brg
// core.io.lsu_ahb <> io.lsu_brg
// core.io.sb_ahb <> io.sb_brg
// core.io.dma_ahb <> io.dma_brg
//
// core.io.lsu_axi <> 0.U.asTypeOf(core.io.lsu_axi)
// core.io.ifu_axi <> 0.U.asTypeOf(core.io.ifu_axi)
// core.io.sb_axi <> 0.U.asTypeOf(core.io.sb_axi)
// core.io.dma_axi <> 0.U.asTypeOf(core.io.lsu_axi)
// }
// // core Inputs
// core.io.dbg_rst_l := io.dbg_rst_l
// core.io.rst_vec := io.rst_vec
// core.io.nmi_int := io.nmi_int
// core.io.nmi_vec := io.nmi_vec
//
// // external halt/run interface
// core.io.i_cpu_halt_req := io.i_cpu_halt_req
// core.io.i_cpu_run_req := io.i_cpu_run_req
// core.io.core_id := io.core_id
//
// // external MPC halt/run interface
// core.io.mpc_debug_halt_req := io.mpc_debug_halt_req
// core.io.mpc_debug_run_req := io.mpc_debug_run_req
// core.io.mpc_reset_run_req := io.mpc_reset_run_req
//
// core.io.lsu_bus_clk_en := io.lsu_bus_clk_en
// core.io.ifu_bus_clk_en := io.ifu_bus_clk_en
// core.io.dbg_bus_clk_en := io.dbg_bus_clk_en
// core.io.dma_bus_clk_en := io.dma_bus_clk_en
//
// core.io.timer_int := io.timer_int
// core.io.soft_int := io.soft_int
// core.io.extintsrc_req := io.extintsrc_req
//
// // Outputs
// val core_rst_l = core.io.core_rst_l
// io.rv_trace_pkt <> core.io.rv_trace_pkt
//
// // external halt/run interface
// io.o_cpu_halt_ack := core.io.o_cpu_halt_ack
// io.o_cpu_halt_status := core.io.o_cpu_halt_status
// io.o_cpu_run_ack := core.io.o_cpu_run_ack
// io.o_debug_mode_status := core.io.o_debug_mode_status
//
// io.mpc_debug_halt_ack := core.io.mpc_debug_halt_ack
// io.mpc_debug_run_ack := core.io.mpc_debug_run_ack
// io.debug_brkpt_status := core.io.debug_brkpt_status
//
// io.dec_tlu_perfcnt0 := core.io.dec_tlu_perfcnt0
// io.dec_tlu_perfcnt1 := core.io.dec_tlu_perfcnt1
// io.dec_tlu_perfcnt2 := core.io.dec_tlu_perfcnt2
// io.dec_tlu_perfcnt3 := core.io.dec_tlu_perfcnt3
//
//}
//object QUASAR_Wrp extends App {
// println((new chisel3.stage.ChiselStage).emitVerilog(new quasar_wrapper()))
//}
io.jtag_tdo := dmi_wrapper.io.tdo
// Memory signals
mem.io.dccm_clk_override := core.io.dccm_clk_override
mem.io.icm_clk_override := core.io.icm_clk_override
mem.io.dec_tlu_core_ecc_disable := core.io.dec_tlu_core_ecc_disable
mem.io.dccm <> core.io.dccm
mem.io.rst_l := reset
mem.io.clk := core.io.active_l2clk
mem.io.scan_mode := io.scan_mode
mem.io.dccm_ext_in_pkt := io.dccm_ext_in_pkt
mem.io.iccm_ext_in_pkt := io.iccm_ext_in_pkt
mem.io.ic_data_ext_in_pkt := io.ic_data_ext_in_pkt
mem.io.ic_tag_ext_in_pkt := io.ic_tag_ext_in_pkt
// Memory outputs
core.io.dbg_rst_l := io.dbg_rst_l
core.io.ic <> mem.io.ic
core.io.iccm <> mem.io.iccm
if(BUILD_AXI4) {
core.io.ifu_ahb <> 0.U.asTypeOf(core.io.ifu_ahb)
core.io.lsu_ahb <> 0.U.asTypeOf(core.io.lsu_ahb)
core.io.sb_ahb <> 0.U.asTypeOf(core.io.sb_ahb)
core.io.dma_ahb <> 0.U.asTypeOf(core.io.dma_ahb)
core.io.lsu_axi <> io.lsu_brg
core.io.ifu_axi <> io.ifu_brg
core.io.sb_axi <> io.sb_brg
core.io.dma_axi <> io.dma_brg
}
else {
core.io.ifu_ahb <> io.ifu_brg
core.io.lsu_ahb <> io.lsu_brg
core.io.sb_ahb <> io.sb_brg
core.io.dma_ahb <> io.dma_brg
core.io.lsu_axi <> 0.U.asTypeOf(core.io.lsu_axi)
core.io.ifu_axi <> 0.U.asTypeOf(core.io.ifu_axi)
core.io.sb_axi <> 0.U.asTypeOf(core.io.sb_axi)
core.io.dma_axi <> 0.U.asTypeOf(core.io.lsu_axi)
}
// core Inputs
core.io.dbg_rst_l := io.dbg_rst_l
core.io.rst_vec := io.rst_vec
core.io.nmi_int := io.nmi_int
core.io.nmi_vec := io.nmi_vec
// external halt/run interface
core.io.i_cpu_halt_req := io.i_cpu_halt_req
core.io.i_cpu_run_req := io.i_cpu_run_req
core.io.core_id := io.core_id
// external MPC halt/run interface
core.io.mpc_debug_halt_req := io.mpc_debug_halt_req
core.io.mpc_debug_run_req := io.mpc_debug_run_req
core.io.mpc_reset_run_req := io.mpc_reset_run_req
core.io.lsu_bus_clk_en := io.lsu_bus_clk_en
core.io.ifu_bus_clk_en := io.ifu_bus_clk_en
core.io.dbg_bus_clk_en := io.dbg_bus_clk_en
core.io.dma_bus_clk_en := io.dma_bus_clk_en
core.io.timer_int := io.timer_int
core.io.soft_int := io.soft_int
core.io.extintsrc_req := io.extintsrc_req
// Outputs
val core_rst_l = core.io.core_rst_l
io.rv_trace_pkt <> core.io.rv_trace_pkt
// external halt/run interface
io.o_cpu_halt_ack := core.io.o_cpu_halt_ack
io.o_cpu_halt_status := core.io.o_cpu_halt_status
io.o_cpu_run_ack := core.io.o_cpu_run_ack
io.o_debug_mode_status := core.io.o_debug_mode_status
io.mpc_debug_halt_ack := core.io.mpc_debug_halt_ack
io.mpc_debug_run_ack := core.io.mpc_debug_run_ack
io.debug_brkpt_status := core.io.debug_brkpt_status
io.dec_tlu_perfcnt0 := core.io.dec_tlu_perfcnt0
io.dec_tlu_perfcnt1 := core.io.dec_tlu_perfcnt1
io.dec_tlu_perfcnt2 := core.io.dec_tlu_perfcnt2
io.dec_tlu_perfcnt3 := core.io.dec_tlu_perfcnt3
}
object QUASAR_Wrp extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new quasar_wrapper()))
}

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