Update lsu_dccm_ctl.scala
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@ -109,7 +109,7 @@ class lsu_dccm_ctl extends Module with RequireAsyncReset with lib
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val picm_rd_data_r_32 = WireInit(UInt(32.W),0.U)
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val picm_rd_data_r = WireInit(UInt(64.W),0.U)
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val lsu_ld_data_corr_m = WireInit(UInt(64.W),0.U)
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io.lsu_ld_data_m := 0.U
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//Forwarding stbuf
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if (LOAD_TO_USE_PLUS1 == 1){
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