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ifu_bp_btb_target_f corrected

This commit is contained in:
​Laraib Khan 2021-01-25 10:44:37 +05:00
parent a5be674839
commit 91635292c6
6 changed files with 1703 additions and 1707 deletions
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2820
ifu_bp_ctl.fir
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583
ifu_bp_ctl.v
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@ -251,66 +251,66 @@ module ifu_bp_ctl(
wire [7:0] _T_11 = _T_8[8:1] ^ _T_8[16:9]; // @[lib.scala 51:47] wire [7:0] _T_11 = _T_8[8:1] ^ _T_8[16:9]; // @[lib.scala 51:47]
wire [7:0] btb_rd_addr_p1_f = _T_11 ^ _T_8[24:17]; // @[lib.scala 51:85] wire [7:0] btb_rd_addr_p1_f = _T_11 ^ _T_8[24:17]; // @[lib.scala 51:85]
wire _T_147 = ~io_ifc_fetch_addr_f[0]; // @[ifu_bp_ctl.scala 191:37] wire _T_147 = ~io_ifc_fetch_addr_f[0]; // @[ifu_bp_ctl.scala 191:37]
wire _T_709 = btb_rd_addr_f == 8'h0; // @[ifu_bp_ctl.scala 447:80] wire _T_709 = btb_rd_addr_f == 8'h0; // @[ifu_bp_ctl.scala 445:80]
reg [21:0] btb_bank0_rd_data_way0_out_0; // @[Reg.scala 27:20] reg [21:0] btb_bank0_rd_data_way0_out_0; // @[Reg.scala 27:20]
wire [21:0] _T_741 = _T_709 ? btb_bank0_rd_data_way0_out_0 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_741 = _T_709 ? btb_bank0_rd_data_way0_out_0 : 22'h0; // @[Mux.scala 27:72]
wire _T_711 = btb_rd_addr_f == 8'h1; // @[ifu_bp_ctl.scala 447:80] wire _T_711 = btb_rd_addr_f == 8'h1; // @[ifu_bp_ctl.scala 445:80]
reg [21:0] btb_bank0_rd_data_way0_out_1; // @[Reg.scala 27:20] reg [21:0] btb_bank0_rd_data_way0_out_1; // @[Reg.scala 27:20]
wire [21:0] _T_742 = _T_711 ? btb_bank0_rd_data_way0_out_1 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_742 = _T_711 ? btb_bank0_rd_data_way0_out_1 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_757 = _T_741 | _T_742; // @[Mux.scala 27:72] wire [21:0] _T_757 = _T_741 | _T_742; // @[Mux.scala 27:72]
wire _T_713 = btb_rd_addr_f == 8'h2; // @[ifu_bp_ctl.scala 447:80] wire _T_713 = btb_rd_addr_f == 8'h2; // @[ifu_bp_ctl.scala 445:80]
reg [21:0] btb_bank0_rd_data_way0_out_2; // @[Reg.scala 27:20] reg [21:0] btb_bank0_rd_data_way0_out_2; // @[Reg.scala 27:20]
wire [21:0] _T_743 = _T_713 ? btb_bank0_rd_data_way0_out_2 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_743 = _T_713 ? btb_bank0_rd_data_way0_out_2 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_758 = _T_757 | _T_743; // @[Mux.scala 27:72] wire [21:0] _T_758 = _T_757 | _T_743; // @[Mux.scala 27:72]
wire _T_715 = btb_rd_addr_f == 8'h3; // @[ifu_bp_ctl.scala 447:80] wire _T_715 = btb_rd_addr_f == 8'h3; // @[ifu_bp_ctl.scala 445:80]
reg [21:0] btb_bank0_rd_data_way0_out_3; // @[Reg.scala 27:20] reg [21:0] btb_bank0_rd_data_way0_out_3; // @[Reg.scala 27:20]
wire [21:0] _T_744 = _T_715 ? btb_bank0_rd_data_way0_out_3 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_744 = _T_715 ? btb_bank0_rd_data_way0_out_3 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_759 = _T_758 | _T_744; // @[Mux.scala 27:72] wire [21:0] _T_759 = _T_758 | _T_744; // @[Mux.scala 27:72]
wire _T_717 = btb_rd_addr_f == 8'h4; // @[ifu_bp_ctl.scala 447:80] wire _T_717 = btb_rd_addr_f == 8'h4; // @[ifu_bp_ctl.scala 445:80]
reg [21:0] btb_bank0_rd_data_way0_out_4; // @[Reg.scala 27:20] reg [21:0] btb_bank0_rd_data_way0_out_4; // @[Reg.scala 27:20]
wire [21:0] _T_745 = _T_717 ? btb_bank0_rd_data_way0_out_4 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_745 = _T_717 ? btb_bank0_rd_data_way0_out_4 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_760 = _T_759 | _T_745; // @[Mux.scala 27:72] wire [21:0] _T_760 = _T_759 | _T_745; // @[Mux.scala 27:72]
wire _T_719 = btb_rd_addr_f == 8'h5; // @[ifu_bp_ctl.scala 447:80] wire _T_719 = btb_rd_addr_f == 8'h5; // @[ifu_bp_ctl.scala 445:80]
reg [21:0] btb_bank0_rd_data_way0_out_5; // @[Reg.scala 27:20] reg [21:0] btb_bank0_rd_data_way0_out_5; // @[Reg.scala 27:20]
wire [21:0] _T_746 = _T_719 ? btb_bank0_rd_data_way0_out_5 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_746 = _T_719 ? btb_bank0_rd_data_way0_out_5 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_761 = _T_760 | _T_746; // @[Mux.scala 27:72] wire [21:0] _T_761 = _T_760 | _T_746; // @[Mux.scala 27:72]
wire _T_721 = btb_rd_addr_f == 8'h6; // @[ifu_bp_ctl.scala 447:80] wire _T_721 = btb_rd_addr_f == 8'h6; // @[ifu_bp_ctl.scala 445:80]
reg [21:0] btb_bank0_rd_data_way0_out_6; // @[Reg.scala 27:20] reg [21:0] btb_bank0_rd_data_way0_out_6; // @[Reg.scala 27:20]
wire [21:0] _T_747 = _T_721 ? btb_bank0_rd_data_way0_out_6 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_747 = _T_721 ? btb_bank0_rd_data_way0_out_6 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_762 = _T_761 | _T_747; // @[Mux.scala 27:72] wire [21:0] _T_762 = _T_761 | _T_747; // @[Mux.scala 27:72]
wire _T_723 = btb_rd_addr_f == 8'h7; // @[ifu_bp_ctl.scala 447:80] wire _T_723 = btb_rd_addr_f == 8'h7; // @[ifu_bp_ctl.scala 445:80]
reg [21:0] btb_bank0_rd_data_way0_out_7; // @[Reg.scala 27:20] reg [21:0] btb_bank0_rd_data_way0_out_7; // @[Reg.scala 27:20]
wire [21:0] _T_748 = _T_723 ? btb_bank0_rd_data_way0_out_7 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_748 = _T_723 ? btb_bank0_rd_data_way0_out_7 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_763 = _T_762 | _T_748; // @[Mux.scala 27:72] wire [21:0] _T_763 = _T_762 | _T_748; // @[Mux.scala 27:72]
wire _T_725 = btb_rd_addr_f == 8'h8; // @[ifu_bp_ctl.scala 447:80] wire _T_725 = btb_rd_addr_f == 8'h8; // @[ifu_bp_ctl.scala 445:80]
reg [21:0] btb_bank0_rd_data_way0_out_8; // @[Reg.scala 27:20] reg [21:0] btb_bank0_rd_data_way0_out_8; // @[Reg.scala 27:20]
wire [21:0] _T_749 = _T_725 ? btb_bank0_rd_data_way0_out_8 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_749 = _T_725 ? btb_bank0_rd_data_way0_out_8 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_764 = _T_763 | _T_749; // @[Mux.scala 27:72] wire [21:0] _T_764 = _T_763 | _T_749; // @[Mux.scala 27:72]
wire _T_727 = btb_rd_addr_f == 8'h9; // @[ifu_bp_ctl.scala 447:80] wire _T_727 = btb_rd_addr_f == 8'h9; // @[ifu_bp_ctl.scala 445:80]
reg [21:0] btb_bank0_rd_data_way0_out_9; // @[Reg.scala 27:20] reg [21:0] btb_bank0_rd_data_way0_out_9; // @[Reg.scala 27:20]
wire [21:0] _T_750 = _T_727 ? btb_bank0_rd_data_way0_out_9 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_750 = _T_727 ? btb_bank0_rd_data_way0_out_9 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_765 = _T_764 | _T_750; // @[Mux.scala 27:72] wire [21:0] _T_765 = _T_764 | _T_750; // @[Mux.scala 27:72]
wire _T_729 = btb_rd_addr_f == 8'ha; // @[ifu_bp_ctl.scala 447:80] wire _T_729 = btb_rd_addr_f == 8'ha; // @[ifu_bp_ctl.scala 445:80]
reg [21:0] btb_bank0_rd_data_way0_out_10; // @[Reg.scala 27:20] reg [21:0] btb_bank0_rd_data_way0_out_10; // @[Reg.scala 27:20]
wire [21:0] _T_751 = _T_729 ? btb_bank0_rd_data_way0_out_10 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_751 = _T_729 ? btb_bank0_rd_data_way0_out_10 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_766 = _T_765 | _T_751; // @[Mux.scala 27:72] wire [21:0] _T_766 = _T_765 | _T_751; // @[Mux.scala 27:72]
wire _T_731 = btb_rd_addr_f == 8'hb; // @[ifu_bp_ctl.scala 447:80] wire _T_731 = btb_rd_addr_f == 8'hb; // @[ifu_bp_ctl.scala 445:80]
reg [21:0] btb_bank0_rd_data_way0_out_11; // @[Reg.scala 27:20] reg [21:0] btb_bank0_rd_data_way0_out_11; // @[Reg.scala 27:20]
wire [21:0] _T_752 = _T_731 ? btb_bank0_rd_data_way0_out_11 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_752 = _T_731 ? btb_bank0_rd_data_way0_out_11 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_767 = _T_766 | _T_752; // @[Mux.scala 27:72] wire [21:0] _T_767 = _T_766 | _T_752; // @[Mux.scala 27:72]
wire _T_733 = btb_rd_addr_f == 8'hc; // @[ifu_bp_ctl.scala 447:80] wire _T_733 = btb_rd_addr_f == 8'hc; // @[ifu_bp_ctl.scala 445:80]
reg [21:0] btb_bank0_rd_data_way0_out_12; // @[Reg.scala 27:20] reg [21:0] btb_bank0_rd_data_way0_out_12; // @[Reg.scala 27:20]
wire [21:0] _T_753 = _T_733 ? btb_bank0_rd_data_way0_out_12 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_753 = _T_733 ? btb_bank0_rd_data_way0_out_12 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_768 = _T_767 | _T_753; // @[Mux.scala 27:72] wire [21:0] _T_768 = _T_767 | _T_753; // @[Mux.scala 27:72]
wire _T_735 = btb_rd_addr_f == 8'hd; // @[ifu_bp_ctl.scala 447:80] wire _T_735 = btb_rd_addr_f == 8'hd; // @[ifu_bp_ctl.scala 445:80]
reg [21:0] btb_bank0_rd_data_way0_out_13; // @[Reg.scala 27:20] reg [21:0] btb_bank0_rd_data_way0_out_13; // @[Reg.scala 27:20]
wire [21:0] _T_754 = _T_735 ? btb_bank0_rd_data_way0_out_13 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_754 = _T_735 ? btb_bank0_rd_data_way0_out_13 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_769 = _T_768 | _T_754; // @[Mux.scala 27:72] wire [21:0] _T_769 = _T_768 | _T_754; // @[Mux.scala 27:72]
wire _T_737 = btb_rd_addr_f == 8'he; // @[ifu_bp_ctl.scala 447:80] wire _T_737 = btb_rd_addr_f == 8'he; // @[ifu_bp_ctl.scala 445:80]
reg [21:0] btb_bank0_rd_data_way0_out_14; // @[Reg.scala 27:20] reg [21:0] btb_bank0_rd_data_way0_out_14; // @[Reg.scala 27:20]
wire [21:0] _T_755 = _T_737 ? btb_bank0_rd_data_way0_out_14 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_755 = _T_737 ? btb_bank0_rd_data_way0_out_14 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_770 = _T_769 | _T_755; // @[Mux.scala 27:72] wire [21:0] _T_770 = _T_769 | _T_755; // @[Mux.scala 27:72]
wire _T_739 = btb_rd_addr_f == 8'hf; // @[ifu_bp_ctl.scala 447:80] wire _T_739 = btb_rd_addr_f == 8'hf; // @[ifu_bp_ctl.scala 445:80]
reg [21:0] btb_bank0_rd_data_way0_out_15; // @[Reg.scala 27:20] reg [21:0] btb_bank0_rd_data_way0_out_15; // @[Reg.scala 27:20]
wire [21:0] _T_756 = _T_739 ? btb_bank0_rd_data_way0_out_15 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_756 = _T_739 ? btb_bank0_rd_data_way0_out_15 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] btb_bank0_rd_data_way0_f = _T_770 | _T_756; // @[Mux.scala 27:72] wire [21:0] btb_bank0_rd_data_way0_f = _T_770 | _T_756; // @[Mux.scala 27:72]
@ -392,51 +392,51 @@ module ifu_bp_ctl(
wire [21:0] _T_130 = tag_match_way1_expanded_f[1] ? btb_bank0_rd_data_way1_f : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_130 = tag_match_way1_expanded_f[1] ? btb_bank0_rd_data_way1_f : 22'h0; // @[Mux.scala 27:72]
wire [21:0] btb_bank0o_rd_data_f = _T_129 | _T_130; // @[Mux.scala 27:72] wire [21:0] btb_bank0o_rd_data_f = _T_129 | _T_130; // @[Mux.scala 27:72]
wire [21:0] _T_149 = _T_147 ? btb_bank0o_rd_data_f : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_149 = _T_147 ? btb_bank0o_rd_data_f : 22'h0; // @[Mux.scala 27:72]
wire _T_837 = btb_rd_addr_p1_f == 8'h0; // @[ifu_bp_ctl.scala 451:86] wire _T_837 = btb_rd_addr_p1_f == 8'h0; // @[ifu_bp_ctl.scala 449:86]
wire [21:0] _T_869 = _T_837 ? btb_bank0_rd_data_way0_out_0 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_869 = _T_837 ? btb_bank0_rd_data_way0_out_0 : 22'h0; // @[Mux.scala 27:72]
wire _T_839 = btb_rd_addr_p1_f == 8'h1; // @[ifu_bp_ctl.scala 451:86] wire _T_839 = btb_rd_addr_p1_f == 8'h1; // @[ifu_bp_ctl.scala 449:86]
wire [21:0] _T_870 = _T_839 ? btb_bank0_rd_data_way0_out_1 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_870 = _T_839 ? btb_bank0_rd_data_way0_out_1 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_885 = _T_869 | _T_870; // @[Mux.scala 27:72] wire [21:0] _T_885 = _T_869 | _T_870; // @[Mux.scala 27:72]
wire _T_841 = btb_rd_addr_p1_f == 8'h2; // @[ifu_bp_ctl.scala 451:86] wire _T_841 = btb_rd_addr_p1_f == 8'h2; // @[ifu_bp_ctl.scala 449:86]
wire [21:0] _T_871 = _T_841 ? btb_bank0_rd_data_way0_out_2 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_871 = _T_841 ? btb_bank0_rd_data_way0_out_2 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_886 = _T_885 | _T_871; // @[Mux.scala 27:72] wire [21:0] _T_886 = _T_885 | _T_871; // @[Mux.scala 27:72]
wire _T_843 = btb_rd_addr_p1_f == 8'h3; // @[ifu_bp_ctl.scala 451:86] wire _T_843 = btb_rd_addr_p1_f == 8'h3; // @[ifu_bp_ctl.scala 449:86]
wire [21:0] _T_872 = _T_843 ? btb_bank0_rd_data_way0_out_3 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_872 = _T_843 ? btb_bank0_rd_data_way0_out_3 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_887 = _T_886 | _T_872; // @[Mux.scala 27:72] wire [21:0] _T_887 = _T_886 | _T_872; // @[Mux.scala 27:72]
wire _T_845 = btb_rd_addr_p1_f == 8'h4; // @[ifu_bp_ctl.scala 451:86] wire _T_845 = btb_rd_addr_p1_f == 8'h4; // @[ifu_bp_ctl.scala 449:86]
wire [21:0] _T_873 = _T_845 ? btb_bank0_rd_data_way0_out_4 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_873 = _T_845 ? btb_bank0_rd_data_way0_out_4 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_888 = _T_887 | _T_873; // @[Mux.scala 27:72] wire [21:0] _T_888 = _T_887 | _T_873; // @[Mux.scala 27:72]
wire _T_847 = btb_rd_addr_p1_f == 8'h5; // @[ifu_bp_ctl.scala 451:86] wire _T_847 = btb_rd_addr_p1_f == 8'h5; // @[ifu_bp_ctl.scala 449:86]
wire [21:0] _T_874 = _T_847 ? btb_bank0_rd_data_way0_out_5 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_874 = _T_847 ? btb_bank0_rd_data_way0_out_5 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_889 = _T_888 | _T_874; // @[Mux.scala 27:72] wire [21:0] _T_889 = _T_888 | _T_874; // @[Mux.scala 27:72]
wire _T_849 = btb_rd_addr_p1_f == 8'h6; // @[ifu_bp_ctl.scala 451:86] wire _T_849 = btb_rd_addr_p1_f == 8'h6; // @[ifu_bp_ctl.scala 449:86]
wire [21:0] _T_875 = _T_849 ? btb_bank0_rd_data_way0_out_6 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_875 = _T_849 ? btb_bank0_rd_data_way0_out_6 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_890 = _T_889 | _T_875; // @[Mux.scala 27:72] wire [21:0] _T_890 = _T_889 | _T_875; // @[Mux.scala 27:72]
wire _T_851 = btb_rd_addr_p1_f == 8'h7; // @[ifu_bp_ctl.scala 451:86] wire _T_851 = btb_rd_addr_p1_f == 8'h7; // @[ifu_bp_ctl.scala 449:86]
wire [21:0] _T_876 = _T_851 ? btb_bank0_rd_data_way0_out_7 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_876 = _T_851 ? btb_bank0_rd_data_way0_out_7 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_891 = _T_890 | _T_876; // @[Mux.scala 27:72] wire [21:0] _T_891 = _T_890 | _T_876; // @[Mux.scala 27:72]
wire _T_853 = btb_rd_addr_p1_f == 8'h8; // @[ifu_bp_ctl.scala 451:86] wire _T_853 = btb_rd_addr_p1_f == 8'h8; // @[ifu_bp_ctl.scala 449:86]
wire [21:0] _T_877 = _T_853 ? btb_bank0_rd_data_way0_out_8 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_877 = _T_853 ? btb_bank0_rd_data_way0_out_8 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_892 = _T_891 | _T_877; // @[Mux.scala 27:72] wire [21:0] _T_892 = _T_891 | _T_877; // @[Mux.scala 27:72]
wire _T_855 = btb_rd_addr_p1_f == 8'h9; // @[ifu_bp_ctl.scala 451:86] wire _T_855 = btb_rd_addr_p1_f == 8'h9; // @[ifu_bp_ctl.scala 449:86]
wire [21:0] _T_878 = _T_855 ? btb_bank0_rd_data_way0_out_9 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_878 = _T_855 ? btb_bank0_rd_data_way0_out_9 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_893 = _T_892 | _T_878; // @[Mux.scala 27:72] wire [21:0] _T_893 = _T_892 | _T_878; // @[Mux.scala 27:72]
wire _T_857 = btb_rd_addr_p1_f == 8'ha; // @[ifu_bp_ctl.scala 451:86] wire _T_857 = btb_rd_addr_p1_f == 8'ha; // @[ifu_bp_ctl.scala 449:86]
wire [21:0] _T_879 = _T_857 ? btb_bank0_rd_data_way0_out_10 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_879 = _T_857 ? btb_bank0_rd_data_way0_out_10 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_894 = _T_893 | _T_879; // @[Mux.scala 27:72] wire [21:0] _T_894 = _T_893 | _T_879; // @[Mux.scala 27:72]
wire _T_859 = btb_rd_addr_p1_f == 8'hb; // @[ifu_bp_ctl.scala 451:86] wire _T_859 = btb_rd_addr_p1_f == 8'hb; // @[ifu_bp_ctl.scala 449:86]
wire [21:0] _T_880 = _T_859 ? btb_bank0_rd_data_way0_out_11 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_880 = _T_859 ? btb_bank0_rd_data_way0_out_11 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_895 = _T_894 | _T_880; // @[Mux.scala 27:72] wire [21:0] _T_895 = _T_894 | _T_880; // @[Mux.scala 27:72]
wire _T_861 = btb_rd_addr_p1_f == 8'hc; // @[ifu_bp_ctl.scala 451:86] wire _T_861 = btb_rd_addr_p1_f == 8'hc; // @[ifu_bp_ctl.scala 449:86]
wire [21:0] _T_881 = _T_861 ? btb_bank0_rd_data_way0_out_12 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_881 = _T_861 ? btb_bank0_rd_data_way0_out_12 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_896 = _T_895 | _T_881; // @[Mux.scala 27:72] wire [21:0] _T_896 = _T_895 | _T_881; // @[Mux.scala 27:72]
wire _T_863 = btb_rd_addr_p1_f == 8'hd; // @[ifu_bp_ctl.scala 451:86] wire _T_863 = btb_rd_addr_p1_f == 8'hd; // @[ifu_bp_ctl.scala 449:86]
wire [21:0] _T_882 = _T_863 ? btb_bank0_rd_data_way0_out_13 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_882 = _T_863 ? btb_bank0_rd_data_way0_out_13 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_897 = _T_896 | _T_882; // @[Mux.scala 27:72] wire [21:0] _T_897 = _T_896 | _T_882; // @[Mux.scala 27:72]
wire _T_865 = btb_rd_addr_p1_f == 8'he; // @[ifu_bp_ctl.scala 451:86] wire _T_865 = btb_rd_addr_p1_f == 8'he; // @[ifu_bp_ctl.scala 449:86]
wire [21:0] _T_883 = _T_865 ? btb_bank0_rd_data_way0_out_14 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_883 = _T_865 ? btb_bank0_rd_data_way0_out_14 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_898 = _T_897 | _T_883; // @[Mux.scala 27:72] wire [21:0] _T_898 = _T_897 | _T_883; // @[Mux.scala 27:72]
wire _T_867 = btb_rd_addr_p1_f == 8'hf; // @[ifu_bp_ctl.scala 451:86] wire _T_867 = btb_rd_addr_p1_f == 8'hf; // @[ifu_bp_ctl.scala 449:86]
wire [21:0] _T_884 = _T_867 ? btb_bank0_rd_data_way0_out_15 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_884 = _T_867 ? btb_bank0_rd_data_way0_out_15 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] btb_bank0_rd_data_way0_p1_f = _T_898 | _T_884; // @[Mux.scala 27:72] wire [21:0] btb_bank0_rd_data_way0_p1_f = _T_898 | _T_884; // @[Mux.scala 27:72]
wire [4:0] _T_35 = _T_8[13:9] ^ _T_8[18:14]; // @[lib.scala 42:111] wire [4:0] _T_35 = _T_8[13:9] ^ _T_8[18:14]; // @[lib.scala 42:111]
@ -514,132 +514,132 @@ module ifu_bp_ctl(
wire [9:0] _T_582 = {btb_rd_addr_f,2'h0}; // @[Cat.scala 29:58] wire [9:0] _T_582 = {btb_rd_addr_f,2'h0}; // @[Cat.scala 29:58]
reg [7:0] fghr; // @[Reg.scala 27:20] reg [7:0] fghr; // @[Reg.scala 27:20]
wire [7:0] bht_rd_addr_hashed_f = _T_582[9:2] ^ fghr; // @[lib.scala 56:35] wire [7:0] bht_rd_addr_hashed_f = _T_582[9:2] ^ fghr; // @[lib.scala 56:35]
wire _T_1947 = bht_rd_addr_hashed_f == 8'h0; // @[ifu_bp_ctl.scala 543:79] wire _T_1947 = bht_rd_addr_hashed_f == 8'h0; // @[ifu_bp_ctl.scala 540:79]
reg [1:0] bht_bank_rd_data_out_1_0; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_1_0; // @[Reg.scala 27:20]
wire [1:0] _T_1979 = _T_1947 ? bht_bank_rd_data_out_1_0 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_1979 = _T_1947 ? bht_bank_rd_data_out_1_0 : 2'h0; // @[Mux.scala 27:72]
wire _T_1949 = bht_rd_addr_hashed_f == 8'h1; // @[ifu_bp_ctl.scala 543:79] wire _T_1949 = bht_rd_addr_hashed_f == 8'h1; // @[ifu_bp_ctl.scala 540:79]
reg [1:0] bht_bank_rd_data_out_1_1; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_1_1; // @[Reg.scala 27:20]
wire [1:0] _T_1980 = _T_1949 ? bht_bank_rd_data_out_1_1 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_1980 = _T_1949 ? bht_bank_rd_data_out_1_1 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_1995 = _T_1979 | _T_1980; // @[Mux.scala 27:72] wire [1:0] _T_1995 = _T_1979 | _T_1980; // @[Mux.scala 27:72]
wire _T_1951 = bht_rd_addr_hashed_f == 8'h2; // @[ifu_bp_ctl.scala 543:79] wire _T_1951 = bht_rd_addr_hashed_f == 8'h2; // @[ifu_bp_ctl.scala 540:79]
reg [1:0] bht_bank_rd_data_out_1_2; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_1_2; // @[Reg.scala 27:20]
wire [1:0] _T_1981 = _T_1951 ? bht_bank_rd_data_out_1_2 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_1981 = _T_1951 ? bht_bank_rd_data_out_1_2 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_1996 = _T_1995 | _T_1981; // @[Mux.scala 27:72] wire [1:0] _T_1996 = _T_1995 | _T_1981; // @[Mux.scala 27:72]
wire _T_1953 = bht_rd_addr_hashed_f == 8'h3; // @[ifu_bp_ctl.scala 543:79] wire _T_1953 = bht_rd_addr_hashed_f == 8'h3; // @[ifu_bp_ctl.scala 540:79]
reg [1:0] bht_bank_rd_data_out_1_3; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_1_3; // @[Reg.scala 27:20]
wire [1:0] _T_1982 = _T_1953 ? bht_bank_rd_data_out_1_3 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_1982 = _T_1953 ? bht_bank_rd_data_out_1_3 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_1997 = _T_1996 | _T_1982; // @[Mux.scala 27:72] wire [1:0] _T_1997 = _T_1996 | _T_1982; // @[Mux.scala 27:72]
wire _T_1955 = bht_rd_addr_hashed_f == 8'h4; // @[ifu_bp_ctl.scala 543:79] wire _T_1955 = bht_rd_addr_hashed_f == 8'h4; // @[ifu_bp_ctl.scala 540:79]
reg [1:0] bht_bank_rd_data_out_1_4; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_1_4; // @[Reg.scala 27:20]
wire [1:0] _T_1983 = _T_1955 ? bht_bank_rd_data_out_1_4 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_1983 = _T_1955 ? bht_bank_rd_data_out_1_4 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_1998 = _T_1997 | _T_1983; // @[Mux.scala 27:72] wire [1:0] _T_1998 = _T_1997 | _T_1983; // @[Mux.scala 27:72]
wire _T_1957 = bht_rd_addr_hashed_f == 8'h5; // @[ifu_bp_ctl.scala 543:79] wire _T_1957 = bht_rd_addr_hashed_f == 8'h5; // @[ifu_bp_ctl.scala 540:79]
reg [1:0] bht_bank_rd_data_out_1_5; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_1_5; // @[Reg.scala 27:20]
wire [1:0] _T_1984 = _T_1957 ? bht_bank_rd_data_out_1_5 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_1984 = _T_1957 ? bht_bank_rd_data_out_1_5 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_1999 = _T_1998 | _T_1984; // @[Mux.scala 27:72] wire [1:0] _T_1999 = _T_1998 | _T_1984; // @[Mux.scala 27:72]
wire _T_1959 = bht_rd_addr_hashed_f == 8'h6; // @[ifu_bp_ctl.scala 543:79] wire _T_1959 = bht_rd_addr_hashed_f == 8'h6; // @[ifu_bp_ctl.scala 540:79]
reg [1:0] bht_bank_rd_data_out_1_6; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_1_6; // @[Reg.scala 27:20]
wire [1:0] _T_1985 = _T_1959 ? bht_bank_rd_data_out_1_6 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_1985 = _T_1959 ? bht_bank_rd_data_out_1_6 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_2000 = _T_1999 | _T_1985; // @[Mux.scala 27:72] wire [1:0] _T_2000 = _T_1999 | _T_1985; // @[Mux.scala 27:72]
wire _T_1961 = bht_rd_addr_hashed_f == 8'h7; // @[ifu_bp_ctl.scala 543:79] wire _T_1961 = bht_rd_addr_hashed_f == 8'h7; // @[ifu_bp_ctl.scala 540:79]
reg [1:0] bht_bank_rd_data_out_1_7; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_1_7; // @[Reg.scala 27:20]
wire [1:0] _T_1986 = _T_1961 ? bht_bank_rd_data_out_1_7 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_1986 = _T_1961 ? bht_bank_rd_data_out_1_7 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_2001 = _T_2000 | _T_1986; // @[Mux.scala 27:72] wire [1:0] _T_2001 = _T_2000 | _T_1986; // @[Mux.scala 27:72]
wire _T_1963 = bht_rd_addr_hashed_f == 8'h8; // @[ifu_bp_ctl.scala 543:79] wire _T_1963 = bht_rd_addr_hashed_f == 8'h8; // @[ifu_bp_ctl.scala 540:79]
reg [1:0] bht_bank_rd_data_out_1_8; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_1_8; // @[Reg.scala 27:20]
wire [1:0] _T_1987 = _T_1963 ? bht_bank_rd_data_out_1_8 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_1987 = _T_1963 ? bht_bank_rd_data_out_1_8 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_2002 = _T_2001 | _T_1987; // @[Mux.scala 27:72] wire [1:0] _T_2002 = _T_2001 | _T_1987; // @[Mux.scala 27:72]
wire _T_1965 = bht_rd_addr_hashed_f == 8'h9; // @[ifu_bp_ctl.scala 543:79] wire _T_1965 = bht_rd_addr_hashed_f == 8'h9; // @[ifu_bp_ctl.scala 540:79]
reg [1:0] bht_bank_rd_data_out_1_9; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_1_9; // @[Reg.scala 27:20]
wire [1:0] _T_1988 = _T_1965 ? bht_bank_rd_data_out_1_9 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_1988 = _T_1965 ? bht_bank_rd_data_out_1_9 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_2003 = _T_2002 | _T_1988; // @[Mux.scala 27:72] wire [1:0] _T_2003 = _T_2002 | _T_1988; // @[Mux.scala 27:72]
wire _T_1967 = bht_rd_addr_hashed_f == 8'ha; // @[ifu_bp_ctl.scala 543:79] wire _T_1967 = bht_rd_addr_hashed_f == 8'ha; // @[ifu_bp_ctl.scala 540:79]
reg [1:0] bht_bank_rd_data_out_1_10; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_1_10; // @[Reg.scala 27:20]
wire [1:0] _T_1989 = _T_1967 ? bht_bank_rd_data_out_1_10 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_1989 = _T_1967 ? bht_bank_rd_data_out_1_10 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_2004 = _T_2003 | _T_1989; // @[Mux.scala 27:72] wire [1:0] _T_2004 = _T_2003 | _T_1989; // @[Mux.scala 27:72]
wire _T_1969 = bht_rd_addr_hashed_f == 8'hb; // @[ifu_bp_ctl.scala 543:79] wire _T_1969 = bht_rd_addr_hashed_f == 8'hb; // @[ifu_bp_ctl.scala 540:79]
reg [1:0] bht_bank_rd_data_out_1_11; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_1_11; // @[Reg.scala 27:20]
wire [1:0] _T_1990 = _T_1969 ? bht_bank_rd_data_out_1_11 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_1990 = _T_1969 ? bht_bank_rd_data_out_1_11 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_2005 = _T_2004 | _T_1990; // @[Mux.scala 27:72] wire [1:0] _T_2005 = _T_2004 | _T_1990; // @[Mux.scala 27:72]
wire _T_1971 = bht_rd_addr_hashed_f == 8'hc; // @[ifu_bp_ctl.scala 543:79] wire _T_1971 = bht_rd_addr_hashed_f == 8'hc; // @[ifu_bp_ctl.scala 540:79]
reg [1:0] bht_bank_rd_data_out_1_12; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_1_12; // @[Reg.scala 27:20]
wire [1:0] _T_1991 = _T_1971 ? bht_bank_rd_data_out_1_12 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_1991 = _T_1971 ? bht_bank_rd_data_out_1_12 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_2006 = _T_2005 | _T_1991; // @[Mux.scala 27:72] wire [1:0] _T_2006 = _T_2005 | _T_1991; // @[Mux.scala 27:72]
wire _T_1973 = bht_rd_addr_hashed_f == 8'hd; // @[ifu_bp_ctl.scala 543:79] wire _T_1973 = bht_rd_addr_hashed_f == 8'hd; // @[ifu_bp_ctl.scala 540:79]
reg [1:0] bht_bank_rd_data_out_1_13; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_1_13; // @[Reg.scala 27:20]
wire [1:0] _T_1992 = _T_1973 ? bht_bank_rd_data_out_1_13 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_1992 = _T_1973 ? bht_bank_rd_data_out_1_13 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_2007 = _T_2006 | _T_1992; // @[Mux.scala 27:72] wire [1:0] _T_2007 = _T_2006 | _T_1992; // @[Mux.scala 27:72]
wire _T_1975 = bht_rd_addr_hashed_f == 8'he; // @[ifu_bp_ctl.scala 543:79] wire _T_1975 = bht_rd_addr_hashed_f == 8'he; // @[ifu_bp_ctl.scala 540:79]
reg [1:0] bht_bank_rd_data_out_1_14; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_1_14; // @[Reg.scala 27:20]
wire [1:0] _T_1993 = _T_1975 ? bht_bank_rd_data_out_1_14 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_1993 = _T_1975 ? bht_bank_rd_data_out_1_14 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_2008 = _T_2007 | _T_1993; // @[Mux.scala 27:72] wire [1:0] _T_2008 = _T_2007 | _T_1993; // @[Mux.scala 27:72]
wire _T_1977 = bht_rd_addr_hashed_f == 8'hf; // @[ifu_bp_ctl.scala 543:79] wire _T_1977 = bht_rd_addr_hashed_f == 8'hf; // @[ifu_bp_ctl.scala 540:79]
reg [1:0] bht_bank_rd_data_out_1_15; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_1_15; // @[Reg.scala 27:20]
wire [1:0] _T_1994 = _T_1977 ? bht_bank_rd_data_out_1_15 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_1994 = _T_1977 ? bht_bank_rd_data_out_1_15 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] bht_bank1_rd_data_f = _T_2008 | _T_1994; // @[Mux.scala 27:72] wire [1:0] bht_bank1_rd_data_f = _T_2008 | _T_1994; // @[Mux.scala 27:72]
wire [1:0] _T_253 = _T_147 ? bht_bank1_rd_data_f : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_253 = _T_147 ? bht_bank1_rd_data_f : 2'h0; // @[Mux.scala 27:72]
wire [9:0] _T_585 = {btb_rd_addr_p1_f,2'h0}; // @[Cat.scala 29:58] wire [9:0] _T_585 = {btb_rd_addr_p1_f,2'h0}; // @[Cat.scala 29:58]
wire [7:0] bht_rd_addr_hashed_p1_f = _T_585[9:2] ^ fghr; // @[lib.scala 56:35] wire [7:0] bht_rd_addr_hashed_p1_f = _T_585[9:2] ^ fghr; // @[lib.scala 56:35]
wire _T_2011 = bht_rd_addr_hashed_p1_f == 8'h0; // @[ifu_bp_ctl.scala 544:85] wire _T_2011 = bht_rd_addr_hashed_p1_f == 8'h0; // @[ifu_bp_ctl.scala 541:85]
reg [1:0] bht_bank_rd_data_out_0_0; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_0_0; // @[Reg.scala 27:20]
wire [1:0] _T_2043 = _T_2011 ? bht_bank_rd_data_out_0_0 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_2043 = _T_2011 ? bht_bank_rd_data_out_0_0 : 2'h0; // @[Mux.scala 27:72]
wire _T_2013 = bht_rd_addr_hashed_p1_f == 8'h1; // @[ifu_bp_ctl.scala 544:85] wire _T_2013 = bht_rd_addr_hashed_p1_f == 8'h1; // @[ifu_bp_ctl.scala 541:85]
reg [1:0] bht_bank_rd_data_out_0_1; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_0_1; // @[Reg.scala 27:20]
wire [1:0] _T_2044 = _T_2013 ? bht_bank_rd_data_out_0_1 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_2044 = _T_2013 ? bht_bank_rd_data_out_0_1 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_2059 = _T_2043 | _T_2044; // @[Mux.scala 27:72] wire [1:0] _T_2059 = _T_2043 | _T_2044; // @[Mux.scala 27:72]
wire _T_2015 = bht_rd_addr_hashed_p1_f == 8'h2; // @[ifu_bp_ctl.scala 544:85] wire _T_2015 = bht_rd_addr_hashed_p1_f == 8'h2; // @[ifu_bp_ctl.scala 541:85]
reg [1:0] bht_bank_rd_data_out_0_2; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_0_2; // @[Reg.scala 27:20]
wire [1:0] _T_2045 = _T_2015 ? bht_bank_rd_data_out_0_2 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_2045 = _T_2015 ? bht_bank_rd_data_out_0_2 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_2060 = _T_2059 | _T_2045; // @[Mux.scala 27:72] wire [1:0] _T_2060 = _T_2059 | _T_2045; // @[Mux.scala 27:72]
wire _T_2017 = bht_rd_addr_hashed_p1_f == 8'h3; // @[ifu_bp_ctl.scala 544:85] wire _T_2017 = bht_rd_addr_hashed_p1_f == 8'h3; // @[ifu_bp_ctl.scala 541:85]
reg [1:0] bht_bank_rd_data_out_0_3; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_0_3; // @[Reg.scala 27:20]
wire [1:0] _T_2046 = _T_2017 ? bht_bank_rd_data_out_0_3 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_2046 = _T_2017 ? bht_bank_rd_data_out_0_3 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_2061 = _T_2060 | _T_2046; // @[Mux.scala 27:72] wire [1:0] _T_2061 = _T_2060 | _T_2046; // @[Mux.scala 27:72]
wire _T_2019 = bht_rd_addr_hashed_p1_f == 8'h4; // @[ifu_bp_ctl.scala 544:85] wire _T_2019 = bht_rd_addr_hashed_p1_f == 8'h4; // @[ifu_bp_ctl.scala 541:85]
reg [1:0] bht_bank_rd_data_out_0_4; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_0_4; // @[Reg.scala 27:20]
wire [1:0] _T_2047 = _T_2019 ? bht_bank_rd_data_out_0_4 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_2047 = _T_2019 ? bht_bank_rd_data_out_0_4 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_2062 = _T_2061 | _T_2047; // @[Mux.scala 27:72] wire [1:0] _T_2062 = _T_2061 | _T_2047; // @[Mux.scala 27:72]
wire _T_2021 = bht_rd_addr_hashed_p1_f == 8'h5; // @[ifu_bp_ctl.scala 544:85] wire _T_2021 = bht_rd_addr_hashed_p1_f == 8'h5; // @[ifu_bp_ctl.scala 541:85]
reg [1:0] bht_bank_rd_data_out_0_5; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_0_5; // @[Reg.scala 27:20]
wire [1:0] _T_2048 = _T_2021 ? bht_bank_rd_data_out_0_5 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_2048 = _T_2021 ? bht_bank_rd_data_out_0_5 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_2063 = _T_2062 | _T_2048; // @[Mux.scala 27:72] wire [1:0] _T_2063 = _T_2062 | _T_2048; // @[Mux.scala 27:72]
wire _T_2023 = bht_rd_addr_hashed_p1_f == 8'h6; // @[ifu_bp_ctl.scala 544:85] wire _T_2023 = bht_rd_addr_hashed_p1_f == 8'h6; // @[ifu_bp_ctl.scala 541:85]
reg [1:0] bht_bank_rd_data_out_0_6; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_0_6; // @[Reg.scala 27:20]
wire [1:0] _T_2049 = _T_2023 ? bht_bank_rd_data_out_0_6 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_2049 = _T_2023 ? bht_bank_rd_data_out_0_6 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_2064 = _T_2063 | _T_2049; // @[Mux.scala 27:72] wire [1:0] _T_2064 = _T_2063 | _T_2049; // @[Mux.scala 27:72]
wire _T_2025 = bht_rd_addr_hashed_p1_f == 8'h7; // @[ifu_bp_ctl.scala 544:85] wire _T_2025 = bht_rd_addr_hashed_p1_f == 8'h7; // @[ifu_bp_ctl.scala 541:85]
reg [1:0] bht_bank_rd_data_out_0_7; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_0_7; // @[Reg.scala 27:20]
wire [1:0] _T_2050 = _T_2025 ? bht_bank_rd_data_out_0_7 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_2050 = _T_2025 ? bht_bank_rd_data_out_0_7 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_2065 = _T_2064 | _T_2050; // @[Mux.scala 27:72] wire [1:0] _T_2065 = _T_2064 | _T_2050; // @[Mux.scala 27:72]
wire _T_2027 = bht_rd_addr_hashed_p1_f == 8'h8; // @[ifu_bp_ctl.scala 544:85] wire _T_2027 = bht_rd_addr_hashed_p1_f == 8'h8; // @[ifu_bp_ctl.scala 541:85]
reg [1:0] bht_bank_rd_data_out_0_8; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_0_8; // @[Reg.scala 27:20]
wire [1:0] _T_2051 = _T_2027 ? bht_bank_rd_data_out_0_8 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_2051 = _T_2027 ? bht_bank_rd_data_out_0_8 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_2066 = _T_2065 | _T_2051; // @[Mux.scala 27:72] wire [1:0] _T_2066 = _T_2065 | _T_2051; // @[Mux.scala 27:72]
wire _T_2029 = bht_rd_addr_hashed_p1_f == 8'h9; // @[ifu_bp_ctl.scala 544:85] wire _T_2029 = bht_rd_addr_hashed_p1_f == 8'h9; // @[ifu_bp_ctl.scala 541:85]
reg [1:0] bht_bank_rd_data_out_0_9; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_0_9; // @[Reg.scala 27:20]
wire [1:0] _T_2052 = _T_2029 ? bht_bank_rd_data_out_0_9 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_2052 = _T_2029 ? bht_bank_rd_data_out_0_9 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_2067 = _T_2066 | _T_2052; // @[Mux.scala 27:72] wire [1:0] _T_2067 = _T_2066 | _T_2052; // @[Mux.scala 27:72]
wire _T_2031 = bht_rd_addr_hashed_p1_f == 8'ha; // @[ifu_bp_ctl.scala 544:85] wire _T_2031 = bht_rd_addr_hashed_p1_f == 8'ha; // @[ifu_bp_ctl.scala 541:85]
reg [1:0] bht_bank_rd_data_out_0_10; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_0_10; // @[Reg.scala 27:20]
wire [1:0] _T_2053 = _T_2031 ? bht_bank_rd_data_out_0_10 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_2053 = _T_2031 ? bht_bank_rd_data_out_0_10 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_2068 = _T_2067 | _T_2053; // @[Mux.scala 27:72] wire [1:0] _T_2068 = _T_2067 | _T_2053; // @[Mux.scala 27:72]
wire _T_2033 = bht_rd_addr_hashed_p1_f == 8'hb; // @[ifu_bp_ctl.scala 544:85] wire _T_2033 = bht_rd_addr_hashed_p1_f == 8'hb; // @[ifu_bp_ctl.scala 541:85]
reg [1:0] bht_bank_rd_data_out_0_11; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_0_11; // @[Reg.scala 27:20]
wire [1:0] _T_2054 = _T_2033 ? bht_bank_rd_data_out_0_11 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_2054 = _T_2033 ? bht_bank_rd_data_out_0_11 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_2069 = _T_2068 | _T_2054; // @[Mux.scala 27:72] wire [1:0] _T_2069 = _T_2068 | _T_2054; // @[Mux.scala 27:72]
wire _T_2035 = bht_rd_addr_hashed_p1_f == 8'hc; // @[ifu_bp_ctl.scala 544:85] wire _T_2035 = bht_rd_addr_hashed_p1_f == 8'hc; // @[ifu_bp_ctl.scala 541:85]
reg [1:0] bht_bank_rd_data_out_0_12; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_0_12; // @[Reg.scala 27:20]
wire [1:0] _T_2055 = _T_2035 ? bht_bank_rd_data_out_0_12 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_2055 = _T_2035 ? bht_bank_rd_data_out_0_12 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_2070 = _T_2069 | _T_2055; // @[Mux.scala 27:72] wire [1:0] _T_2070 = _T_2069 | _T_2055; // @[Mux.scala 27:72]
wire _T_2037 = bht_rd_addr_hashed_p1_f == 8'hd; // @[ifu_bp_ctl.scala 544:85] wire _T_2037 = bht_rd_addr_hashed_p1_f == 8'hd; // @[ifu_bp_ctl.scala 541:85]
reg [1:0] bht_bank_rd_data_out_0_13; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_0_13; // @[Reg.scala 27:20]
wire [1:0] _T_2056 = _T_2037 ? bht_bank_rd_data_out_0_13 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_2056 = _T_2037 ? bht_bank_rd_data_out_0_13 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_2071 = _T_2070 | _T_2056; // @[Mux.scala 27:72] wire [1:0] _T_2071 = _T_2070 | _T_2056; // @[Mux.scala 27:72]
wire _T_2039 = bht_rd_addr_hashed_p1_f == 8'he; // @[ifu_bp_ctl.scala 544:85] wire _T_2039 = bht_rd_addr_hashed_p1_f == 8'he; // @[ifu_bp_ctl.scala 541:85]
reg [1:0] bht_bank_rd_data_out_0_14; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_0_14; // @[Reg.scala 27:20]
wire [1:0] _T_2057 = _T_2039 ? bht_bank_rd_data_out_0_14 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_2057 = _T_2039 ? bht_bank_rd_data_out_0_14 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_2072 = _T_2071 | _T_2057; // @[Mux.scala 27:72] wire [1:0] _T_2072 = _T_2071 | _T_2057; // @[Mux.scala 27:72]
wire _T_2041 = bht_rd_addr_hashed_p1_f == 8'hf; // @[ifu_bp_ctl.scala 544:85] wire _T_2041 = bht_rd_addr_hashed_p1_f == 8'hf; // @[ifu_bp_ctl.scala 541:85]
reg [1:0] bht_bank_rd_data_out_0_15; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_0_15; // @[Reg.scala 27:20]
wire [1:0] _T_2058 = _T_2041 ? bht_bank_rd_data_out_0_15 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_2058 = _T_2041 ? bht_bank_rd_data_out_0_15 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] bht_bank0_rd_data_p1_f = _T_2072 | _T_2058; // @[Mux.scala 27:72] wire [1:0] bht_bank0_rd_data_p1_f = _T_2072 | _T_2058; // @[Mux.scala 27:72]
@ -658,7 +658,7 @@ module ifu_bp_ctl(
wire _T_215 = |_T_214; // @[ifu_bp_ctl.scala 260:58] wire _T_215 = |_T_214; // @[ifu_bp_ctl.scala 260:58]
wire eoc_mask = _T_212 | _T_215; // @[ifu_bp_ctl.scala 260:25] wire eoc_mask = _T_212 | _T_215; // @[ifu_bp_ctl.scala 260:25]
wire [1:0] _T_611 = {eoc_mask,1'h1}; // @[Cat.scala 29:58] wire [1:0] _T_611 = {eoc_mask,1'h1}; // @[Cat.scala 29:58]
wire [1:0] vwayhit_f = _T_609 & _T_611; // @[ifu_bp_ctl.scala 443:71] wire [1:0] vwayhit_f = _T_609 & _T_611; // @[ifu_bp_ctl.scala 441:71]
wire _T_260 = _T_258 & vwayhit_f[1]; // @[ifu_bp_ctl.scala 298:69] wire _T_260 = _T_258 & vwayhit_f[1]; // @[ifu_bp_ctl.scala 298:69]
wire [1:0] _T_1915 = _T_1947 ? bht_bank_rd_data_out_0_0 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_1915 = _T_1947 ? bht_bank_rd_data_out_0_0 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_1916 = _T_1949 ? bht_bank_rd_data_out_0_1 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_1916 = _T_1949 ? bht_bank_rd_data_out_0_1 : 2'h0; // @[Mux.scala 27:72]
@ -835,9 +835,9 @@ module ifu_bp_ctl(
wire _T_384 = io_ifc_fetch_req_f & _T_269; // @[ifu_bp_ctl.scala 361:117] wire _T_384 = io_ifc_fetch_req_f & _T_269; // @[ifu_bp_ctl.scala 361:117]
wire _T_385 = _T_384 & io_ic_hit_f; // @[ifu_bp_ctl.scala 361:142] wire _T_385 = _T_384 & io_ic_hit_f; // @[ifu_bp_ctl.scala 361:142]
reg [29:0] ifc_fetch_adder_prior; // @[Reg.scala 27:20] reg [29:0] ifc_fetch_adder_prior; // @[Reg.scala 27:20]
wire _T_390 = ~btb_fg_crossing_f; // @[ifu_bp_ctl.scala 367:32] wire _T_390 = ~btb_fg_crossing_f; // @[ifu_bp_ctl.scala 366:32]
wire _T_391 = ~use_fa_plus; // @[ifu_bp_ctl.scala 367:53] wire _T_391 = ~use_fa_plus; // @[ifu_bp_ctl.scala 366:53]
wire _T_392 = _T_390 & _T_391; // @[ifu_bp_ctl.scala 367:51] wire _T_392 = _T_390 & _T_391; // @[ifu_bp_ctl.scala 366:51]
wire [29:0] _T_395 = use_fa_plus ? fetch_addr_p1_f : 30'h0; // @[Mux.scala 27:72] wire [29:0] _T_395 = use_fa_plus ? fetch_addr_p1_f : 30'h0; // @[Mux.scala 27:72]
wire [29:0] _T_396 = btb_fg_crossing_f ? ifc_fetch_adder_prior : 30'h0; // @[Mux.scala 27:72] wire [29:0] _T_396 = btb_fg_crossing_f ? ifc_fetch_adder_prior : 30'h0; // @[Mux.scala 27:72]
wire [29:0] _T_397 = _T_392 ? io_ifc_fetch_addr_f[30:1] : 30'h0; // @[Mux.scala 27:72] wire [29:0] _T_397 = _T_392 ? io_ifc_fetch_addr_f[30:1] : 30'h0; // @[Mux.scala 27:72]
@ -859,19 +859,17 @@ module ifu_bp_ctl(
wire [18:0] _T_430 = _T_427 | _T_428; // @[Mux.scala 27:72] wire [18:0] _T_430 = _T_427 | _T_428; // @[Mux.scala 27:72]
wire [18:0] _T_431 = _T_430 | _T_429; // @[Mux.scala 27:72] wire [18:0] _T_431 = _T_430 | _T_429; // @[Mux.scala 27:72]
wire [31:0] bp_btb_target_adder_f = {_T_431,_T_406[11:0],1'h0}; // @[Cat.scala 29:58] wire [31:0] bp_btb_target_adder_f = {_T_431,_T_406[11:0],1'h0}; // @[Cat.scala 29:58]
wire _T_435 = ~btb_rd_call_f; // @[ifu_bp_ctl.scala 375:55] wire _T_435 = ~btb_rd_call_f; // @[ifu_bp_ctl.scala 374:55]
wire _T_436 = btb_rd_ret_f & _T_435; // @[ifu_bp_ctl.scala 375:53] wire _T_436 = btb_rd_ret_f & _T_435; // @[ifu_bp_ctl.scala 374:53]
reg [31:0] rets_out_0; // @[Reg.scala 27:20] reg [31:0] rets_out_0; // @[Reg.scala 27:20]
wire _T_438 = _T_436 & rets_out_0[0]; // @[ifu_bp_ctl.scala 375:70] wire _T_438 = _T_436 & rets_out_0[0]; // @[ifu_bp_ctl.scala 374:70]
wire _T_439 = _T_438 & io_ifu_bp_hit_taken_f; // @[ifu_bp_ctl.scala 375:87] wire _T_439 = _T_438 & io_ifu_bp_hit_taken_f; // @[ifu_bp_ctl.scala 374:87]
wire [30:0] _T_441 = _T_439 ? 31'h7fffffff : 31'h0; // @[Bitwise.scala 72:12] wire [30:0] _T_441 = _T_439 ? 31'h7fffffff : 31'h0; // @[Bitwise.scala 72:12]
wire [30:0] _T_443 = _T_441 & rets_out_0[31:1]; // @[ifu_bp_ctl.scala 375:113] wire [30:0] _T_443 = _T_441 & rets_out_0[31:1]; // @[ifu_bp_ctl.scala 374:113]
wire _T_444 = ~btb_rd_ret_f; // @[ifu_bp_ctl.scala 376:15] wire _T_448 = ~_T_438; // @[ifu_bp_ctl.scala 375:15]
wire _T_446 = _T_444 & _T_435; // @[ifu_bp_ctl.scala 376:29] wire _T_449 = _T_448 & io_ifu_bp_hit_taken_f; // @[ifu_bp_ctl.scala 375:65]
wire _T_448 = _T_446 & rets_out_0[0]; // @[ifu_bp_ctl.scala 376:46]
wire _T_449 = _T_448 & io_ifu_bp_hit_taken_f; // @[ifu_bp_ctl.scala 376:63]
wire [30:0] _T_451 = _T_449 ? 31'h7fffffff : 31'h0; // @[Bitwise.scala 72:12] wire [30:0] _T_451 = _T_449 ? 31'h7fffffff : 31'h0; // @[Bitwise.scala 72:12]
wire [30:0] _T_453 = _T_451 & bp_btb_target_adder_f[31:1]; // @[ifu_bp_ctl.scala 376:89] wire [30:0] _T_453 = _T_451 & bp_btb_target_adder_f[31:1]; // @[ifu_bp_ctl.scala 375:91]
wire [12:0] _T_461 = {11'h0,_T_377,1'h0}; // @[Cat.scala 29:58] wire [12:0] _T_461 = {11'h0,_T_377,1'h0}; // @[Cat.scala 29:58]
wire [12:0] _T_464 = _T_402[12:1] + _T_461[12:1]; // @[lib.scala 68:31] wire [12:0] _T_464 = _T_402[12:1] + _T_461[12:1]; // @[lib.scala 68:31]
wire _T_473 = ~_T_464[12]; // @[lib.scala 72:28] wire _T_473 = ~_T_464[12]; // @[lib.scala 72:28]
@ -885,14 +883,15 @@ module ifu_bp_ctl(
wire [18:0] _T_488 = _T_485 | _T_486; // @[Mux.scala 27:72] wire [18:0] _T_488 = _T_485 | _T_486; // @[Mux.scala 27:72]
wire [18:0] _T_489 = _T_488 | _T_487; // @[Mux.scala 27:72] wire [18:0] _T_489 = _T_488 | _T_487; // @[Mux.scala 27:72]
wire [31:0] bp_rs_call_target_f = {_T_489,_T_464[11:0],1'h0}; // @[Cat.scala 29:58] wire [31:0] bp_rs_call_target_f = {_T_489,_T_464[11:0],1'h0}; // @[Cat.scala 29:58]
wire _T_494 = btb_rd_call_f & _T_444; // @[ifu_bp_ctl.scala 381:31] wire _T_493 = ~btb_rd_ret_f; // @[ifu_bp_ctl.scala 379:33]
wire rs_push = _T_494 & io_ifu_bp_hit_taken_f; // @[ifu_bp_ctl.scala 381:47] wire _T_494 = btb_rd_call_f & _T_493; // @[ifu_bp_ctl.scala 379:31]
wire rs_pop = _T_436 & io_ifu_bp_hit_taken_f; // @[ifu_bp_ctl.scala 382:46] wire rs_push = _T_494 & io_ifu_bp_hit_taken_f; // @[ifu_bp_ctl.scala 379:47]
wire _T_497 = ~rs_push; // @[ifu_bp_ctl.scala 383:17] wire rs_pop = _T_436 & io_ifu_bp_hit_taken_f; // @[ifu_bp_ctl.scala 380:46]
wire _T_498 = ~rs_pop; // @[ifu_bp_ctl.scala 383:28] wire _T_497 = ~rs_push; // @[ifu_bp_ctl.scala 381:17]
wire rs_hold = _T_497 & _T_498; // @[ifu_bp_ctl.scala 383:26] wire _T_498 = ~rs_pop; // @[ifu_bp_ctl.scala 381:28]
wire rsenable_0 = ~rs_hold; // @[ifu_bp_ctl.scala 385:60] wire rs_hold = _T_497 & _T_498; // @[ifu_bp_ctl.scala 381:26]
wire rsenable_1 = rs_push | rs_pop; // @[ifu_bp_ctl.scala 385:119] wire rsenable_0 = ~rs_hold; // @[ifu_bp_ctl.scala 383:60]
wire rsenable_1 = rs_push | rs_pop; // @[ifu_bp_ctl.scala 383:119]
wire [31:0] _T_501 = {bp_rs_call_target_f[31:1],1'h1}; // @[Cat.scala 29:58] wire [31:0] _T_501 = {bp_rs_call_target_f[31:1],1'h1}; // @[Cat.scala 29:58]
wire [31:0] _T_503 = rs_push ? _T_501 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_503 = rs_push ? _T_501 : 32'h0; // @[Mux.scala 27:72]
reg [31:0] rets_out_1; // @[Reg.scala 27:20] reg [31:0] rets_out_1; // @[Reg.scala 27:20]
@ -922,219 +921,219 @@ module ifu_bp_ctl(
reg [31:0] rets_out_7; // @[Reg.scala 27:20] reg [31:0] rets_out_7; // @[Reg.scala 27:20]
wire [31:0] _T_534 = rs_pop ? rets_out_7 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_534 = rs_pop ? rets_out_7 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] rets_in_6 = _T_533 | _T_534; // @[Mux.scala 27:72] wire [31:0] rets_in_6 = _T_533 | _T_534; // @[Mux.scala 27:72]
wire _T_552 = ~dec_tlu_error_wb; // @[ifu_bp_ctl.scala 397:35] wire _T_552 = ~dec_tlu_error_wb; // @[ifu_bp_ctl.scala 395:35]
wire btb_valid = exu_mp_valid & _T_552; // @[ifu_bp_ctl.scala 397:32] wire btb_valid = exu_mp_valid & _T_552; // @[ifu_bp_ctl.scala 395:32]
wire _T_553 = io_exu_bp_exu_mp_pkt_bits_pcall | io_exu_bp_exu_mp_pkt_bits_pja; // @[ifu_bp_ctl.scala 411:89] wire _T_553 = io_exu_bp_exu_mp_pkt_bits_pcall | io_exu_bp_exu_mp_pkt_bits_pja; // @[ifu_bp_ctl.scala 409:89]
wire _T_554 = io_exu_bp_exu_mp_pkt_bits_pret | io_exu_bp_exu_mp_pkt_bits_pja; // @[ifu_bp_ctl.scala 411:113] wire _T_554 = io_exu_bp_exu_mp_pkt_bits_pret | io_exu_bp_exu_mp_pkt_bits_pja; // @[ifu_bp_ctl.scala 409:113]
wire [21:0] btb_wr_data = {io_exu_bp_exu_mp_btag,io_exu_bp_exu_mp_pkt_bits_toffset,io_exu_bp_exu_mp_pkt_bits_pc4,io_exu_bp_exu_mp_pkt_bits_boffset,_T_553,_T_554,btb_valid}; // @[Cat.scala 29:58] wire [21:0] btb_wr_data = {io_exu_bp_exu_mp_btag,io_exu_bp_exu_mp_pkt_bits_toffset,io_exu_bp_exu_mp_pkt_bits_pc4,io_exu_bp_exu_mp_pkt_bits_boffset,_T_553,_T_554,btb_valid}; // @[Cat.scala 29:58]
wire _T_560 = exu_mp_valid & io_exu_bp_exu_mp_pkt_bits_ataken; // @[ifu_bp_ctl.scala 412:41] wire _T_560 = exu_mp_valid & io_exu_bp_exu_mp_pkt_bits_ataken; // @[ifu_bp_ctl.scala 410:41]
wire _T_561 = ~io_exu_bp_exu_mp_pkt_valid; // @[ifu_bp_ctl.scala 412:59] wire _T_561 = ~io_exu_bp_exu_mp_pkt_valid; // @[ifu_bp_ctl.scala 410:59]
wire exu_mp_valid_write = _T_560 & _T_561; // @[ifu_bp_ctl.scala 412:57] wire exu_mp_valid_write = _T_560 & _T_561; // @[ifu_bp_ctl.scala 410:57]
wire middle_of_bank = io_exu_bp_exu_mp_pkt_bits_pc4 ^ io_exu_bp_exu_mp_pkt_bits_boffset; // @[ifu_bp_ctl.scala 413:35] wire middle_of_bank = io_exu_bp_exu_mp_pkt_bits_pc4 ^ io_exu_bp_exu_mp_pkt_bits_boffset; // @[ifu_bp_ctl.scala 411:35]
wire _T_562 = ~io_exu_bp_exu_mp_pkt_bits_pcall; // @[ifu_bp_ctl.scala 416:43] wire _T_562 = ~io_exu_bp_exu_mp_pkt_bits_pcall; // @[ifu_bp_ctl.scala 414:43]
wire _T_563 = exu_mp_valid & _T_562; // @[ifu_bp_ctl.scala 416:41] wire _T_563 = exu_mp_valid & _T_562; // @[ifu_bp_ctl.scala 414:41]
wire _T_564 = ~io_exu_bp_exu_mp_pkt_bits_pret; // @[ifu_bp_ctl.scala 416:58] wire _T_564 = ~io_exu_bp_exu_mp_pkt_bits_pret; // @[ifu_bp_ctl.scala 414:58]
wire _T_565 = _T_563 & _T_564; // @[ifu_bp_ctl.scala 416:56] wire _T_565 = _T_563 & _T_564; // @[ifu_bp_ctl.scala 414:56]
wire _T_566 = ~io_exu_bp_exu_mp_pkt_bits_pja; // @[ifu_bp_ctl.scala 416:72] wire _T_566 = ~io_exu_bp_exu_mp_pkt_bits_pja; // @[ifu_bp_ctl.scala 414:72]
wire _T_567 = _T_565 & _T_566; // @[ifu_bp_ctl.scala 416:70] wire _T_567 = _T_565 & _T_566; // @[ifu_bp_ctl.scala 414:70]
wire [1:0] _T_569 = _T_567 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] wire [1:0] _T_569 = _T_567 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire _T_570 = ~middle_of_bank; // @[ifu_bp_ctl.scala 416:106] wire _T_570 = ~middle_of_bank; // @[ifu_bp_ctl.scala 414:106]
wire [1:0] _T_571 = {middle_of_bank,_T_570}; // @[Cat.scala 29:58] wire [1:0] _T_571 = {middle_of_bank,_T_570}; // @[Cat.scala 29:58]
wire [1:0] bht_wr_en0 = _T_569 & _T_571; // @[ifu_bp_ctl.scala 416:84] wire [1:0] bht_wr_en0 = _T_569 & _T_571; // @[ifu_bp_ctl.scala 414:84]
wire [1:0] _T_573 = io_dec_bp_dec_tlu_br0_r_pkt_valid ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] wire [1:0] _T_573 = io_dec_bp_dec_tlu_br0_r_pkt_valid ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire _T_574 = ~io_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[ifu_bp_ctl.scala 417:75] wire _T_574 = ~io_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[ifu_bp_ctl.scala 415:75]
wire [1:0] _T_575 = {io_dec_bp_dec_tlu_br0_r_pkt_bits_middle,_T_574}; // @[Cat.scala 29:58] wire [1:0] _T_575 = {io_dec_bp_dec_tlu_br0_r_pkt_bits_middle,_T_574}; // @[Cat.scala 29:58]
wire [1:0] bht_wr_en2 = _T_573 & _T_575; // @[ifu_bp_ctl.scala 417:46] wire [1:0] bht_wr_en2 = _T_573 & _T_575; // @[ifu_bp_ctl.scala 415:46]
wire [9:0] _T_576 = {io_exu_bp_exu_mp_index,2'h0}; // @[Cat.scala 29:58] wire [9:0] _T_576 = {io_exu_bp_exu_mp_index,2'h0}; // @[Cat.scala 29:58]
wire [7:0] mp_hashed = _T_576[9:2] ^ io_exu_bp_exu_mp_eghr; // @[lib.scala 56:35] wire [7:0] mp_hashed = _T_576[9:2] ^ io_exu_bp_exu_mp_eghr; // @[lib.scala 56:35]
wire [9:0] _T_579 = {io_exu_bp_exu_i0_br_index_r,2'h0}; // @[Cat.scala 29:58] wire [9:0] _T_579 = {io_exu_bp_exu_i0_br_index_r,2'h0}; // @[Cat.scala 29:58]
wire [7:0] br0_hashed_wb = _T_579[9:2] ^ io_exu_bp_exu_i0_br_fghr_r; // @[lib.scala 56:35] wire [7:0] br0_hashed_wb = _T_579[9:2] ^ io_exu_bp_exu_i0_br_fghr_r; // @[lib.scala 56:35]
wire _T_589 = _T_170 & exu_mp_valid_write; // @[ifu_bp_ctl.scala 436:39] wire _T_589 = _T_170 & exu_mp_valid_write; // @[ifu_bp_ctl.scala 434:39]
wire _T_591 = _T_589 & _T_552; // @[ifu_bp_ctl.scala 436:60] wire _T_591 = _T_589 & _T_552; // @[ifu_bp_ctl.scala 434:60]
wire _T_592 = ~io_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[ifu_bp_ctl.scala 436:87] wire _T_592 = ~io_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[ifu_bp_ctl.scala 434:87]
wire _T_593 = _T_592 & dec_tlu_error_wb; // @[ifu_bp_ctl.scala 436:104] wire _T_593 = _T_592 & dec_tlu_error_wb; // @[ifu_bp_ctl.scala 434:104]
wire btb_wr_en_way0 = _T_591 | _T_593; // @[ifu_bp_ctl.scala 436:83] wire btb_wr_en_way0 = _T_591 | _T_593; // @[ifu_bp_ctl.scala 434:83]
wire _T_594 = io_exu_bp_exu_mp_pkt_bits_way & exu_mp_valid_write; // @[ifu_bp_ctl.scala 437:36] wire _T_594 = io_exu_bp_exu_mp_pkt_bits_way & exu_mp_valid_write; // @[ifu_bp_ctl.scala 435:36]
wire _T_596 = _T_594 & _T_552; // @[ifu_bp_ctl.scala 437:57] wire _T_596 = _T_594 & _T_552; // @[ifu_bp_ctl.scala 435:57]
wire _T_597 = io_dec_bp_dec_tlu_br0_r_pkt_bits_way & dec_tlu_error_wb; // @[ifu_bp_ctl.scala 437:98] wire _T_597 = io_dec_bp_dec_tlu_br0_r_pkt_bits_way & dec_tlu_error_wb; // @[ifu_bp_ctl.scala 435:98]
wire btb_wr_en_way1 = _T_596 | _T_597; // @[ifu_bp_ctl.scala 437:80] wire btb_wr_en_way1 = _T_596 | _T_597; // @[ifu_bp_ctl.scala 435:80]
wire [7:0] btb_wr_addr = dec_tlu_error_wb ? io_exu_bp_exu_i0_br_index_r : io_exu_bp_exu_mp_index; // @[ifu_bp_ctl.scala 440:24] wire [7:0] btb_wr_addr = dec_tlu_error_wb ? io_exu_bp_exu_i0_br_index_r : io_exu_bp_exu_mp_index; // @[ifu_bp_ctl.scala 438:24]
wire _T_613 = btb_wr_addr == 8'h0; // @[ifu_bp_ctl.scala 444:98] wire _T_613 = btb_wr_addr == 8'h0; // @[ifu_bp_ctl.scala 442:98]
wire _T_614 = _T_613 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 444:107] wire _T_614 = _T_613 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 442:107]
wire _T_616 = btb_wr_addr == 8'h1; // @[ifu_bp_ctl.scala 444:98] wire _T_616 = btb_wr_addr == 8'h1; // @[ifu_bp_ctl.scala 442:98]
wire _T_617 = _T_616 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 444:107] wire _T_617 = _T_616 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 442:107]
wire _T_619 = btb_wr_addr == 8'h2; // @[ifu_bp_ctl.scala 444:98] wire _T_619 = btb_wr_addr == 8'h2; // @[ifu_bp_ctl.scala 442:98]
wire _T_620 = _T_619 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 444:107] wire _T_620 = _T_619 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 442:107]
wire _T_622 = btb_wr_addr == 8'h3; // @[ifu_bp_ctl.scala 444:98] wire _T_622 = btb_wr_addr == 8'h3; // @[ifu_bp_ctl.scala 442:98]
wire _T_623 = _T_622 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 444:107] wire _T_623 = _T_622 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 442:107]
wire _T_625 = btb_wr_addr == 8'h4; // @[ifu_bp_ctl.scala 444:98] wire _T_625 = btb_wr_addr == 8'h4; // @[ifu_bp_ctl.scala 442:98]
wire _T_626 = _T_625 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 444:107] wire _T_626 = _T_625 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 442:107]
wire _T_628 = btb_wr_addr == 8'h5; // @[ifu_bp_ctl.scala 444:98] wire _T_628 = btb_wr_addr == 8'h5; // @[ifu_bp_ctl.scala 442:98]
wire _T_629 = _T_628 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 444:107] wire _T_629 = _T_628 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 442:107]
wire _T_631 = btb_wr_addr == 8'h6; // @[ifu_bp_ctl.scala 444:98] wire _T_631 = btb_wr_addr == 8'h6; // @[ifu_bp_ctl.scala 442:98]
wire _T_632 = _T_631 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 444:107] wire _T_632 = _T_631 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 442:107]
wire _T_634 = btb_wr_addr == 8'h7; // @[ifu_bp_ctl.scala 444:98] wire _T_634 = btb_wr_addr == 8'h7; // @[ifu_bp_ctl.scala 442:98]
wire _T_635 = _T_634 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 444:107] wire _T_635 = _T_634 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 442:107]
wire _T_637 = btb_wr_addr == 8'h8; // @[ifu_bp_ctl.scala 444:98] wire _T_637 = btb_wr_addr == 8'h8; // @[ifu_bp_ctl.scala 442:98]
wire _T_638 = _T_637 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 444:107] wire _T_638 = _T_637 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 442:107]
wire _T_640 = btb_wr_addr == 8'h9; // @[ifu_bp_ctl.scala 444:98] wire _T_640 = btb_wr_addr == 8'h9; // @[ifu_bp_ctl.scala 442:98]
wire _T_641 = _T_640 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 444:107] wire _T_641 = _T_640 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 442:107]
wire _T_643 = btb_wr_addr == 8'ha; // @[ifu_bp_ctl.scala 444:98] wire _T_643 = btb_wr_addr == 8'ha; // @[ifu_bp_ctl.scala 442:98]
wire _T_644 = _T_643 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 444:107] wire _T_644 = _T_643 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 442:107]
wire _T_646 = btb_wr_addr == 8'hb; // @[ifu_bp_ctl.scala 444:98] wire _T_646 = btb_wr_addr == 8'hb; // @[ifu_bp_ctl.scala 442:98]
wire _T_647 = _T_646 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 444:107] wire _T_647 = _T_646 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 442:107]
wire _T_649 = btb_wr_addr == 8'hc; // @[ifu_bp_ctl.scala 444:98] wire _T_649 = btb_wr_addr == 8'hc; // @[ifu_bp_ctl.scala 442:98]
wire _T_650 = _T_649 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 444:107] wire _T_650 = _T_649 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 442:107]
wire _T_652 = btb_wr_addr == 8'hd; // @[ifu_bp_ctl.scala 444:98] wire _T_652 = btb_wr_addr == 8'hd; // @[ifu_bp_ctl.scala 442:98]
wire _T_653 = _T_652 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 444:107] wire _T_653 = _T_652 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 442:107]
wire _T_655 = btb_wr_addr == 8'he; // @[ifu_bp_ctl.scala 444:98] wire _T_655 = btb_wr_addr == 8'he; // @[ifu_bp_ctl.scala 442:98]
wire _T_656 = _T_655 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 444:107] wire _T_656 = _T_655 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 442:107]
wire _T_658 = btb_wr_addr == 8'hf; // @[ifu_bp_ctl.scala 444:98] wire _T_658 = btb_wr_addr == 8'hf; // @[ifu_bp_ctl.scala 442:98]
wire _T_659 = _T_658 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 444:107] wire _T_659 = _T_658 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 442:107]
wire _T_662 = _T_613 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 445:107] wire _T_662 = _T_613 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 443:107]
wire _T_665 = _T_616 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 445:107] wire _T_665 = _T_616 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 443:107]
wire _T_668 = _T_619 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 445:107] wire _T_668 = _T_619 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 443:107]
wire _T_671 = _T_622 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 445:107] wire _T_671 = _T_622 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 443:107]
wire _T_674 = _T_625 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 445:107] wire _T_674 = _T_625 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 443:107]
wire _T_677 = _T_628 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 445:107] wire _T_677 = _T_628 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 443:107]
wire _T_680 = _T_631 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 445:107] wire _T_680 = _T_631 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 443:107]
wire _T_683 = _T_634 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 445:107] wire _T_683 = _T_634 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 443:107]
wire _T_686 = _T_637 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 445:107] wire _T_686 = _T_637 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 443:107]
wire _T_689 = _T_640 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 445:107] wire _T_689 = _T_640 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 443:107]
wire _T_692 = _T_643 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 445:107] wire _T_692 = _T_643 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 443:107]
wire _T_695 = _T_646 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 445:107] wire _T_695 = _T_646 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 443:107]
wire _T_698 = _T_649 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 445:107] wire _T_698 = _T_649 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 443:107]
wire _T_701 = _T_652 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 445:107] wire _T_701 = _T_652 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 443:107]
wire _T_704 = _T_655 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 445:107] wire _T_704 = _T_655 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 443:107]
wire _T_707 = _T_658 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 445:107] wire _T_707 = _T_658 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 443:107]
wire _T_967 = mp_hashed == 8'h0; // @[ifu_bp_ctl.scala 518:109] wire _T_967 = mp_hashed == 8'h0; // @[ifu_bp_ctl.scala 516:109]
wire _T_972 = br0_hashed_wb == 8'h0; // @[ifu_bp_ctl.scala 519:109] wire _T_972 = br0_hashed_wb == 8'h0; // @[ifu_bp_ctl.scala 517:109]
wire _T_990 = bht_wr_en2[0] & _T_972; // @[ifu_bp_ctl.scala 524:23] wire _T_990 = bht_wr_en2[0] & _T_972; // @[ifu_bp_ctl.scala 522:23]
wire _T_998 = br0_hashed_wb == 8'h1; // @[ifu_bp_ctl.scala 524:74] wire _T_998 = br0_hashed_wb == 8'h1; // @[ifu_bp_ctl.scala 522:74]
wire _T_999 = bht_wr_en2[0] & _T_998; // @[ifu_bp_ctl.scala 524:23] wire _T_999 = bht_wr_en2[0] & _T_998; // @[ifu_bp_ctl.scala 522:23]
wire _T_1007 = br0_hashed_wb == 8'h2; // @[ifu_bp_ctl.scala 524:74] wire _T_1007 = br0_hashed_wb == 8'h2; // @[ifu_bp_ctl.scala 522:74]
wire _T_1008 = bht_wr_en2[0] & _T_1007; // @[ifu_bp_ctl.scala 524:23] wire _T_1008 = bht_wr_en2[0] & _T_1007; // @[ifu_bp_ctl.scala 522:23]
wire _T_1016 = br0_hashed_wb == 8'h3; // @[ifu_bp_ctl.scala 524:74] wire _T_1016 = br0_hashed_wb == 8'h3; // @[ifu_bp_ctl.scala 522:74]
wire _T_1017 = bht_wr_en2[0] & _T_1016; // @[ifu_bp_ctl.scala 524:23] wire _T_1017 = bht_wr_en2[0] & _T_1016; // @[ifu_bp_ctl.scala 522:23]
wire _T_1025 = br0_hashed_wb == 8'h4; // @[ifu_bp_ctl.scala 524:74] wire _T_1025 = br0_hashed_wb == 8'h4; // @[ifu_bp_ctl.scala 522:74]
wire _T_1026 = bht_wr_en2[0] & _T_1025; // @[ifu_bp_ctl.scala 524:23] wire _T_1026 = bht_wr_en2[0] & _T_1025; // @[ifu_bp_ctl.scala 522:23]
wire _T_1034 = br0_hashed_wb == 8'h5; // @[ifu_bp_ctl.scala 524:74] wire _T_1034 = br0_hashed_wb == 8'h5; // @[ifu_bp_ctl.scala 522:74]
wire _T_1035 = bht_wr_en2[0] & _T_1034; // @[ifu_bp_ctl.scala 524:23] wire _T_1035 = bht_wr_en2[0] & _T_1034; // @[ifu_bp_ctl.scala 522:23]
wire _T_1043 = br0_hashed_wb == 8'h6; // @[ifu_bp_ctl.scala 524:74] wire _T_1043 = br0_hashed_wb == 8'h6; // @[ifu_bp_ctl.scala 522:74]
wire _T_1044 = bht_wr_en2[0] & _T_1043; // @[ifu_bp_ctl.scala 524:23] wire _T_1044 = bht_wr_en2[0] & _T_1043; // @[ifu_bp_ctl.scala 522:23]
wire _T_1052 = br0_hashed_wb == 8'h7; // @[ifu_bp_ctl.scala 524:74] wire _T_1052 = br0_hashed_wb == 8'h7; // @[ifu_bp_ctl.scala 522:74]
wire _T_1053 = bht_wr_en2[0] & _T_1052; // @[ifu_bp_ctl.scala 524:23] wire _T_1053 = bht_wr_en2[0] & _T_1052; // @[ifu_bp_ctl.scala 522:23]
wire _T_1061 = br0_hashed_wb == 8'h8; // @[ifu_bp_ctl.scala 524:74] wire _T_1061 = br0_hashed_wb == 8'h8; // @[ifu_bp_ctl.scala 522:74]
wire _T_1062 = bht_wr_en2[0] & _T_1061; // @[ifu_bp_ctl.scala 524:23] wire _T_1062 = bht_wr_en2[0] & _T_1061; // @[ifu_bp_ctl.scala 522:23]
wire _T_1070 = br0_hashed_wb == 8'h9; // @[ifu_bp_ctl.scala 524:74] wire _T_1070 = br0_hashed_wb == 8'h9; // @[ifu_bp_ctl.scala 522:74]
wire _T_1071 = bht_wr_en2[0] & _T_1070; // @[ifu_bp_ctl.scala 524:23] wire _T_1071 = bht_wr_en2[0] & _T_1070; // @[ifu_bp_ctl.scala 522:23]
wire _T_1079 = br0_hashed_wb == 8'ha; // @[ifu_bp_ctl.scala 524:74] wire _T_1079 = br0_hashed_wb == 8'ha; // @[ifu_bp_ctl.scala 522:74]
wire _T_1080 = bht_wr_en2[0] & _T_1079; // @[ifu_bp_ctl.scala 524:23] wire _T_1080 = bht_wr_en2[0] & _T_1079; // @[ifu_bp_ctl.scala 522:23]
wire _T_1088 = br0_hashed_wb == 8'hb; // @[ifu_bp_ctl.scala 524:74] wire _T_1088 = br0_hashed_wb == 8'hb; // @[ifu_bp_ctl.scala 522:74]
wire _T_1089 = bht_wr_en2[0] & _T_1088; // @[ifu_bp_ctl.scala 524:23] wire _T_1089 = bht_wr_en2[0] & _T_1088; // @[ifu_bp_ctl.scala 522:23]
wire _T_1097 = br0_hashed_wb == 8'hc; // @[ifu_bp_ctl.scala 524:74] wire _T_1097 = br0_hashed_wb == 8'hc; // @[ifu_bp_ctl.scala 522:74]
wire _T_1098 = bht_wr_en2[0] & _T_1097; // @[ifu_bp_ctl.scala 524:23] wire _T_1098 = bht_wr_en2[0] & _T_1097; // @[ifu_bp_ctl.scala 522:23]
wire _T_1106 = br0_hashed_wb == 8'hd; // @[ifu_bp_ctl.scala 524:74] wire _T_1106 = br0_hashed_wb == 8'hd; // @[ifu_bp_ctl.scala 522:74]
wire _T_1107 = bht_wr_en2[0] & _T_1106; // @[ifu_bp_ctl.scala 524:23] wire _T_1107 = bht_wr_en2[0] & _T_1106; // @[ifu_bp_ctl.scala 522:23]
wire _T_1115 = br0_hashed_wb == 8'he; // @[ifu_bp_ctl.scala 524:74] wire _T_1115 = br0_hashed_wb == 8'he; // @[ifu_bp_ctl.scala 522:74]
wire _T_1116 = bht_wr_en2[0] & _T_1115; // @[ifu_bp_ctl.scala 524:23] wire _T_1116 = bht_wr_en2[0] & _T_1115; // @[ifu_bp_ctl.scala 522:23]
wire _T_1124 = br0_hashed_wb == 8'hf; // @[ifu_bp_ctl.scala 524:74] wire _T_1124 = br0_hashed_wb == 8'hf; // @[ifu_bp_ctl.scala 522:74]
wire _T_1125 = bht_wr_en2[0] & _T_1124; // @[ifu_bp_ctl.scala 524:23] wire _T_1125 = bht_wr_en2[0] & _T_1124; // @[ifu_bp_ctl.scala 522:23]
wire _T_1134 = bht_wr_en2[1] & _T_972; // @[ifu_bp_ctl.scala 524:23] wire _T_1134 = bht_wr_en2[1] & _T_972; // @[ifu_bp_ctl.scala 522:23]
wire _T_1143 = bht_wr_en2[1] & _T_998; // @[ifu_bp_ctl.scala 524:23] wire _T_1143 = bht_wr_en2[1] & _T_998; // @[ifu_bp_ctl.scala 522:23]
wire _T_1152 = bht_wr_en2[1] & _T_1007; // @[ifu_bp_ctl.scala 524:23] wire _T_1152 = bht_wr_en2[1] & _T_1007; // @[ifu_bp_ctl.scala 522:23]
wire _T_1161 = bht_wr_en2[1] & _T_1016; // @[ifu_bp_ctl.scala 524:23] wire _T_1161 = bht_wr_en2[1] & _T_1016; // @[ifu_bp_ctl.scala 522:23]
wire _T_1170 = bht_wr_en2[1] & _T_1025; // @[ifu_bp_ctl.scala 524:23] wire _T_1170 = bht_wr_en2[1] & _T_1025; // @[ifu_bp_ctl.scala 522:23]
wire _T_1179 = bht_wr_en2[1] & _T_1034; // @[ifu_bp_ctl.scala 524:23] wire _T_1179 = bht_wr_en2[1] & _T_1034; // @[ifu_bp_ctl.scala 522:23]
wire _T_1188 = bht_wr_en2[1] & _T_1043; // @[ifu_bp_ctl.scala 524:23] wire _T_1188 = bht_wr_en2[1] & _T_1043; // @[ifu_bp_ctl.scala 522:23]
wire _T_1197 = bht_wr_en2[1] & _T_1052; // @[ifu_bp_ctl.scala 524:23] wire _T_1197 = bht_wr_en2[1] & _T_1052; // @[ifu_bp_ctl.scala 522:23]
wire _T_1206 = bht_wr_en2[1] & _T_1061; // @[ifu_bp_ctl.scala 524:23] wire _T_1206 = bht_wr_en2[1] & _T_1061; // @[ifu_bp_ctl.scala 522:23]
wire _T_1215 = bht_wr_en2[1] & _T_1070; // @[ifu_bp_ctl.scala 524:23] wire _T_1215 = bht_wr_en2[1] & _T_1070; // @[ifu_bp_ctl.scala 522:23]
wire _T_1224 = bht_wr_en2[1] & _T_1079; // @[ifu_bp_ctl.scala 524:23] wire _T_1224 = bht_wr_en2[1] & _T_1079; // @[ifu_bp_ctl.scala 522:23]
wire _T_1233 = bht_wr_en2[1] & _T_1088; // @[ifu_bp_ctl.scala 524:23] wire _T_1233 = bht_wr_en2[1] & _T_1088; // @[ifu_bp_ctl.scala 522:23]
wire _T_1242 = bht_wr_en2[1] & _T_1097; // @[ifu_bp_ctl.scala 524:23] wire _T_1242 = bht_wr_en2[1] & _T_1097; // @[ifu_bp_ctl.scala 522:23]
wire _T_1251 = bht_wr_en2[1] & _T_1106; // @[ifu_bp_ctl.scala 524:23] wire _T_1251 = bht_wr_en2[1] & _T_1106; // @[ifu_bp_ctl.scala 522:23]
wire _T_1260 = bht_wr_en2[1] & _T_1115; // @[ifu_bp_ctl.scala 524:23] wire _T_1260 = bht_wr_en2[1] & _T_1115; // @[ifu_bp_ctl.scala 522:23]
wire _T_1269 = bht_wr_en2[1] & _T_1124; // @[ifu_bp_ctl.scala 524:23] wire _T_1269 = bht_wr_en2[1] & _T_1124; // @[ifu_bp_ctl.scala 522:23]
wire _T_1278 = bht_wr_en0[0] & _T_967; // @[ifu_bp_ctl.scala 532:45] wire _T_1278 = bht_wr_en0[0] & _T_967; // @[ifu_bp_ctl.scala 530:45]
wire bht_bank_sel_0_0_0 = _T_1278 | _T_990; // @[ifu_bp_ctl.scala 532:223] wire bht_bank_sel_0_0_0 = _T_1278 | _T_990; // @[ifu_bp_ctl.scala 530:223]
wire _T_1294 = mp_hashed == 8'h1; // @[ifu_bp_ctl.scala 532:97] wire _T_1294 = mp_hashed == 8'h1; // @[ifu_bp_ctl.scala 530:97]
wire _T_1295 = bht_wr_en0[0] & _T_1294; // @[ifu_bp_ctl.scala 532:45] wire _T_1295 = bht_wr_en0[0] & _T_1294; // @[ifu_bp_ctl.scala 530:45]
wire bht_bank_sel_0_0_1 = _T_1295 | _T_999; // @[ifu_bp_ctl.scala 532:223] wire bht_bank_sel_0_0_1 = _T_1295 | _T_999; // @[ifu_bp_ctl.scala 530:223]
wire _T_1311 = mp_hashed == 8'h2; // @[ifu_bp_ctl.scala 532:97] wire _T_1311 = mp_hashed == 8'h2; // @[ifu_bp_ctl.scala 530:97]
wire _T_1312 = bht_wr_en0[0] & _T_1311; // @[ifu_bp_ctl.scala 532:45] wire _T_1312 = bht_wr_en0[0] & _T_1311; // @[ifu_bp_ctl.scala 530:45]
wire bht_bank_sel_0_0_2 = _T_1312 | _T_1008; // @[ifu_bp_ctl.scala 532:223] wire bht_bank_sel_0_0_2 = _T_1312 | _T_1008; // @[ifu_bp_ctl.scala 530:223]
wire _T_1328 = mp_hashed == 8'h3; // @[ifu_bp_ctl.scala 532:97] wire _T_1328 = mp_hashed == 8'h3; // @[ifu_bp_ctl.scala 530:97]
wire _T_1329 = bht_wr_en0[0] & _T_1328; // @[ifu_bp_ctl.scala 532:45] wire _T_1329 = bht_wr_en0[0] & _T_1328; // @[ifu_bp_ctl.scala 530:45]
wire bht_bank_sel_0_0_3 = _T_1329 | _T_1017; // @[ifu_bp_ctl.scala 532:223] wire bht_bank_sel_0_0_3 = _T_1329 | _T_1017; // @[ifu_bp_ctl.scala 530:223]
wire _T_1345 = mp_hashed == 8'h4; // @[ifu_bp_ctl.scala 532:97] wire _T_1345 = mp_hashed == 8'h4; // @[ifu_bp_ctl.scala 530:97]
wire _T_1346 = bht_wr_en0[0] & _T_1345; // @[ifu_bp_ctl.scala 532:45] wire _T_1346 = bht_wr_en0[0] & _T_1345; // @[ifu_bp_ctl.scala 530:45]
wire bht_bank_sel_0_0_4 = _T_1346 | _T_1026; // @[ifu_bp_ctl.scala 532:223] wire bht_bank_sel_0_0_4 = _T_1346 | _T_1026; // @[ifu_bp_ctl.scala 530:223]
wire _T_1362 = mp_hashed == 8'h5; // @[ifu_bp_ctl.scala 532:97] wire _T_1362 = mp_hashed == 8'h5; // @[ifu_bp_ctl.scala 530:97]
wire _T_1363 = bht_wr_en0[0] & _T_1362; // @[ifu_bp_ctl.scala 532:45] wire _T_1363 = bht_wr_en0[0] & _T_1362; // @[ifu_bp_ctl.scala 530:45]
wire bht_bank_sel_0_0_5 = _T_1363 | _T_1035; // @[ifu_bp_ctl.scala 532:223] wire bht_bank_sel_0_0_5 = _T_1363 | _T_1035; // @[ifu_bp_ctl.scala 530:223]
wire _T_1379 = mp_hashed == 8'h6; // @[ifu_bp_ctl.scala 532:97] wire _T_1379 = mp_hashed == 8'h6; // @[ifu_bp_ctl.scala 530:97]
wire _T_1380 = bht_wr_en0[0] & _T_1379; // @[ifu_bp_ctl.scala 532:45] wire _T_1380 = bht_wr_en0[0] & _T_1379; // @[ifu_bp_ctl.scala 530:45]
wire bht_bank_sel_0_0_6 = _T_1380 | _T_1044; // @[ifu_bp_ctl.scala 532:223] wire bht_bank_sel_0_0_6 = _T_1380 | _T_1044; // @[ifu_bp_ctl.scala 530:223]
wire _T_1396 = mp_hashed == 8'h7; // @[ifu_bp_ctl.scala 532:97] wire _T_1396 = mp_hashed == 8'h7; // @[ifu_bp_ctl.scala 530:97]
wire _T_1397 = bht_wr_en0[0] & _T_1396; // @[ifu_bp_ctl.scala 532:45] wire _T_1397 = bht_wr_en0[0] & _T_1396; // @[ifu_bp_ctl.scala 530:45]
wire bht_bank_sel_0_0_7 = _T_1397 | _T_1053; // @[ifu_bp_ctl.scala 532:223] wire bht_bank_sel_0_0_7 = _T_1397 | _T_1053; // @[ifu_bp_ctl.scala 530:223]
wire _T_1413 = mp_hashed == 8'h8; // @[ifu_bp_ctl.scala 532:97] wire _T_1413 = mp_hashed == 8'h8; // @[ifu_bp_ctl.scala 530:97]
wire _T_1414 = bht_wr_en0[0] & _T_1413; // @[ifu_bp_ctl.scala 532:45] wire _T_1414 = bht_wr_en0[0] & _T_1413; // @[ifu_bp_ctl.scala 530:45]
wire bht_bank_sel_0_0_8 = _T_1414 | _T_1062; // @[ifu_bp_ctl.scala 532:223] wire bht_bank_sel_0_0_8 = _T_1414 | _T_1062; // @[ifu_bp_ctl.scala 530:223]
wire _T_1430 = mp_hashed == 8'h9; // @[ifu_bp_ctl.scala 532:97] wire _T_1430 = mp_hashed == 8'h9; // @[ifu_bp_ctl.scala 530:97]
wire _T_1431 = bht_wr_en0[0] & _T_1430; // @[ifu_bp_ctl.scala 532:45] wire _T_1431 = bht_wr_en0[0] & _T_1430; // @[ifu_bp_ctl.scala 530:45]
wire bht_bank_sel_0_0_9 = _T_1431 | _T_1071; // @[ifu_bp_ctl.scala 532:223] wire bht_bank_sel_0_0_9 = _T_1431 | _T_1071; // @[ifu_bp_ctl.scala 530:223]
wire _T_1447 = mp_hashed == 8'ha; // @[ifu_bp_ctl.scala 532:97] wire _T_1447 = mp_hashed == 8'ha; // @[ifu_bp_ctl.scala 530:97]
wire _T_1448 = bht_wr_en0[0] & _T_1447; // @[ifu_bp_ctl.scala 532:45] wire _T_1448 = bht_wr_en0[0] & _T_1447; // @[ifu_bp_ctl.scala 530:45]
wire bht_bank_sel_0_0_10 = _T_1448 | _T_1080; // @[ifu_bp_ctl.scala 532:223] wire bht_bank_sel_0_0_10 = _T_1448 | _T_1080; // @[ifu_bp_ctl.scala 530:223]
wire _T_1464 = mp_hashed == 8'hb; // @[ifu_bp_ctl.scala 532:97] wire _T_1464 = mp_hashed == 8'hb; // @[ifu_bp_ctl.scala 530:97]
wire _T_1465 = bht_wr_en0[0] & _T_1464; // @[ifu_bp_ctl.scala 532:45] wire _T_1465 = bht_wr_en0[0] & _T_1464; // @[ifu_bp_ctl.scala 530:45]
wire bht_bank_sel_0_0_11 = _T_1465 | _T_1089; // @[ifu_bp_ctl.scala 532:223] wire bht_bank_sel_0_0_11 = _T_1465 | _T_1089; // @[ifu_bp_ctl.scala 530:223]
wire _T_1481 = mp_hashed == 8'hc; // @[ifu_bp_ctl.scala 532:97] wire _T_1481 = mp_hashed == 8'hc; // @[ifu_bp_ctl.scala 530:97]
wire _T_1482 = bht_wr_en0[0] & _T_1481; // @[ifu_bp_ctl.scala 532:45] wire _T_1482 = bht_wr_en0[0] & _T_1481; // @[ifu_bp_ctl.scala 530:45]
wire bht_bank_sel_0_0_12 = _T_1482 | _T_1098; // @[ifu_bp_ctl.scala 532:223] wire bht_bank_sel_0_0_12 = _T_1482 | _T_1098; // @[ifu_bp_ctl.scala 530:223]
wire _T_1498 = mp_hashed == 8'hd; // @[ifu_bp_ctl.scala 532:97] wire _T_1498 = mp_hashed == 8'hd; // @[ifu_bp_ctl.scala 530:97]
wire _T_1499 = bht_wr_en0[0] & _T_1498; // @[ifu_bp_ctl.scala 532:45] wire _T_1499 = bht_wr_en0[0] & _T_1498; // @[ifu_bp_ctl.scala 530:45]
wire bht_bank_sel_0_0_13 = _T_1499 | _T_1107; // @[ifu_bp_ctl.scala 532:223] wire bht_bank_sel_0_0_13 = _T_1499 | _T_1107; // @[ifu_bp_ctl.scala 530:223]
wire _T_1515 = mp_hashed == 8'he; // @[ifu_bp_ctl.scala 532:97] wire _T_1515 = mp_hashed == 8'he; // @[ifu_bp_ctl.scala 530:97]
wire _T_1516 = bht_wr_en0[0] & _T_1515; // @[ifu_bp_ctl.scala 532:45] wire _T_1516 = bht_wr_en0[0] & _T_1515; // @[ifu_bp_ctl.scala 530:45]
wire bht_bank_sel_0_0_14 = _T_1516 | _T_1116; // @[ifu_bp_ctl.scala 532:223] wire bht_bank_sel_0_0_14 = _T_1516 | _T_1116; // @[ifu_bp_ctl.scala 530:223]
wire _T_1532 = mp_hashed == 8'hf; // @[ifu_bp_ctl.scala 532:97] wire _T_1532 = mp_hashed == 8'hf; // @[ifu_bp_ctl.scala 530:97]
wire _T_1533 = bht_wr_en0[0] & _T_1532; // @[ifu_bp_ctl.scala 532:45] wire _T_1533 = bht_wr_en0[0] & _T_1532; // @[ifu_bp_ctl.scala 530:45]
wire bht_bank_sel_0_0_15 = _T_1533 | _T_1125; // @[ifu_bp_ctl.scala 532:223] wire bht_bank_sel_0_0_15 = _T_1533 | _T_1125; // @[ifu_bp_ctl.scala 530:223]
wire _T_1550 = bht_wr_en0[1] & _T_967; // @[ifu_bp_ctl.scala 532:45] wire _T_1550 = bht_wr_en0[1] & _T_967; // @[ifu_bp_ctl.scala 530:45]
wire bht_bank_sel_1_0_0 = _T_1550 | _T_1134; // @[ifu_bp_ctl.scala 532:223] wire bht_bank_sel_1_0_0 = _T_1550 | _T_1134; // @[ifu_bp_ctl.scala 530:223]
wire _T_1567 = bht_wr_en0[1] & _T_1294; // @[ifu_bp_ctl.scala 532:45] wire _T_1567 = bht_wr_en0[1] & _T_1294; // @[ifu_bp_ctl.scala 530:45]
wire bht_bank_sel_1_0_1 = _T_1567 | _T_1143; // @[ifu_bp_ctl.scala 532:223] wire bht_bank_sel_1_0_1 = _T_1567 | _T_1143; // @[ifu_bp_ctl.scala 530:223]
wire _T_1584 = bht_wr_en0[1] & _T_1311; // @[ifu_bp_ctl.scala 532:45] wire _T_1584 = bht_wr_en0[1] & _T_1311; // @[ifu_bp_ctl.scala 530:45]
wire bht_bank_sel_1_0_2 = _T_1584 | _T_1152; // @[ifu_bp_ctl.scala 532:223] wire bht_bank_sel_1_0_2 = _T_1584 | _T_1152; // @[ifu_bp_ctl.scala 530:223]
wire _T_1601 = bht_wr_en0[1] & _T_1328; // @[ifu_bp_ctl.scala 532:45] wire _T_1601 = bht_wr_en0[1] & _T_1328; // @[ifu_bp_ctl.scala 530:45]
wire bht_bank_sel_1_0_3 = _T_1601 | _T_1161; // @[ifu_bp_ctl.scala 532:223] wire bht_bank_sel_1_0_3 = _T_1601 | _T_1161; // @[ifu_bp_ctl.scala 530:223]
wire _T_1618 = bht_wr_en0[1] & _T_1345; // @[ifu_bp_ctl.scala 532:45] wire _T_1618 = bht_wr_en0[1] & _T_1345; // @[ifu_bp_ctl.scala 530:45]
wire bht_bank_sel_1_0_4 = _T_1618 | _T_1170; // @[ifu_bp_ctl.scala 532:223] wire bht_bank_sel_1_0_4 = _T_1618 | _T_1170; // @[ifu_bp_ctl.scala 530:223]
wire _T_1635 = bht_wr_en0[1] & _T_1362; // @[ifu_bp_ctl.scala 532:45] wire _T_1635 = bht_wr_en0[1] & _T_1362; // @[ifu_bp_ctl.scala 530:45]
wire bht_bank_sel_1_0_5 = _T_1635 | _T_1179; // @[ifu_bp_ctl.scala 532:223] wire bht_bank_sel_1_0_5 = _T_1635 | _T_1179; // @[ifu_bp_ctl.scala 530:223]
wire _T_1652 = bht_wr_en0[1] & _T_1379; // @[ifu_bp_ctl.scala 532:45] wire _T_1652 = bht_wr_en0[1] & _T_1379; // @[ifu_bp_ctl.scala 530:45]
wire bht_bank_sel_1_0_6 = _T_1652 | _T_1188; // @[ifu_bp_ctl.scala 532:223] wire bht_bank_sel_1_0_6 = _T_1652 | _T_1188; // @[ifu_bp_ctl.scala 530:223]
wire _T_1669 = bht_wr_en0[1] & _T_1396; // @[ifu_bp_ctl.scala 532:45] wire _T_1669 = bht_wr_en0[1] & _T_1396; // @[ifu_bp_ctl.scala 530:45]
wire bht_bank_sel_1_0_7 = _T_1669 | _T_1197; // @[ifu_bp_ctl.scala 532:223] wire bht_bank_sel_1_0_7 = _T_1669 | _T_1197; // @[ifu_bp_ctl.scala 530:223]
wire _T_1686 = bht_wr_en0[1] & _T_1413; // @[ifu_bp_ctl.scala 532:45] wire _T_1686 = bht_wr_en0[1] & _T_1413; // @[ifu_bp_ctl.scala 530:45]
wire bht_bank_sel_1_0_8 = _T_1686 | _T_1206; // @[ifu_bp_ctl.scala 532:223] wire bht_bank_sel_1_0_8 = _T_1686 | _T_1206; // @[ifu_bp_ctl.scala 530:223]
wire _T_1703 = bht_wr_en0[1] & _T_1430; // @[ifu_bp_ctl.scala 532:45] wire _T_1703 = bht_wr_en0[1] & _T_1430; // @[ifu_bp_ctl.scala 530:45]
wire bht_bank_sel_1_0_9 = _T_1703 | _T_1215; // @[ifu_bp_ctl.scala 532:223] wire bht_bank_sel_1_0_9 = _T_1703 | _T_1215; // @[ifu_bp_ctl.scala 530:223]
wire _T_1720 = bht_wr_en0[1] & _T_1447; // @[ifu_bp_ctl.scala 532:45] wire _T_1720 = bht_wr_en0[1] & _T_1447; // @[ifu_bp_ctl.scala 530:45]
wire bht_bank_sel_1_0_10 = _T_1720 | _T_1224; // @[ifu_bp_ctl.scala 532:223] wire bht_bank_sel_1_0_10 = _T_1720 | _T_1224; // @[ifu_bp_ctl.scala 530:223]
wire _T_1737 = bht_wr_en0[1] & _T_1464; // @[ifu_bp_ctl.scala 532:45] wire _T_1737 = bht_wr_en0[1] & _T_1464; // @[ifu_bp_ctl.scala 530:45]
wire bht_bank_sel_1_0_11 = _T_1737 | _T_1233; // @[ifu_bp_ctl.scala 532:223] wire bht_bank_sel_1_0_11 = _T_1737 | _T_1233; // @[ifu_bp_ctl.scala 530:223]
wire _T_1754 = bht_wr_en0[1] & _T_1481; // @[ifu_bp_ctl.scala 532:45] wire _T_1754 = bht_wr_en0[1] & _T_1481; // @[ifu_bp_ctl.scala 530:45]
wire bht_bank_sel_1_0_12 = _T_1754 | _T_1242; // @[ifu_bp_ctl.scala 532:223] wire bht_bank_sel_1_0_12 = _T_1754 | _T_1242; // @[ifu_bp_ctl.scala 530:223]
wire _T_1771 = bht_wr_en0[1] & _T_1498; // @[ifu_bp_ctl.scala 532:45] wire _T_1771 = bht_wr_en0[1] & _T_1498; // @[ifu_bp_ctl.scala 530:45]
wire bht_bank_sel_1_0_13 = _T_1771 | _T_1251; // @[ifu_bp_ctl.scala 532:223] wire bht_bank_sel_1_0_13 = _T_1771 | _T_1251; // @[ifu_bp_ctl.scala 530:223]
wire _T_1788 = bht_wr_en0[1] & _T_1515; // @[ifu_bp_ctl.scala 532:45] wire _T_1788 = bht_wr_en0[1] & _T_1515; // @[ifu_bp_ctl.scala 530:45]
wire bht_bank_sel_1_0_14 = _T_1788 | _T_1260; // @[ifu_bp_ctl.scala 532:223] wire bht_bank_sel_1_0_14 = _T_1788 | _T_1260; // @[ifu_bp_ctl.scala 530:223]
wire _T_1805 = bht_wr_en0[1] & _T_1532; // @[ifu_bp_ctl.scala 532:45] wire _T_1805 = bht_wr_en0[1] & _T_1532; // @[ifu_bp_ctl.scala 530:45]
wire bht_bank_sel_1_0_15 = _T_1805 | _T_1269; // @[ifu_bp_ctl.scala 532:223] wire bht_bank_sel_1_0_15 = _T_1805 | _T_1269; // @[ifu_bp_ctl.scala 530:223]
rvclkhdr rvclkhdr ( // @[lib.scala 399:23] rvclkhdr rvclkhdr ( // @[lib.scala 399:23]
.io_clk(rvclkhdr_io_clk), .io_clk(rvclkhdr_io_clk),
.io_en(rvclkhdr_io_en) .io_en(rvclkhdr_io_en)
@ -1308,7 +1307,7 @@ module ifu_bp_ctl(
.io_en(rvclkhdr_42_io_en) .io_en(rvclkhdr_42_io_en)
); );
assign io_ifu_bp_hit_taken_f = _T_231 & _T_232; // @[ifu_bp_ctl.scala 277:25] assign io_ifu_bp_hit_taken_f = _T_231 & _T_232; // @[ifu_bp_ctl.scala 277:25]
assign io_ifu_bp_btb_target_f = _T_443 | _T_453; // @[ifu_bp_ctl.scala 375:26] assign io_ifu_bp_btb_target_f = _T_443 | _T_453; // @[ifu_bp_ctl.scala 374:26]
assign io_ifu_bp_inst_mask_f = _T_268 | _T_269; // @[ifu_bp_ctl.scala 302:25] assign io_ifu_bp_inst_mask_f = _T_268 | _T_269; // @[ifu_bp_ctl.scala 302:25]
assign io_ifu_bp_fghr_f = fghr; // @[ifu_bp_ctl.scala 345:20] assign io_ifu_bp_fghr_f = fghr; // @[ifu_bp_ctl.scala 345:20]
assign io_ifu_bp_way_f = tag_match_vway1_expanded_f | _T_154; // @[ifu_bp_ctl.scala 254:19] assign io_ifu_bp_way_f = tag_match_vway1_expanded_f | _T_154; // @[ifu_bp_ctl.scala 254:19]
@ -1317,7 +1316,7 @@ module ifu_bp_ctl(
assign io_ifu_bp_hist0_f = {bht_vbank1_rd_data_f[0],bht_vbank0_rd_data_f[0]}; // @[ifu_bp_ctl.scala 347:21] assign io_ifu_bp_hist0_f = {bht_vbank1_rd_data_f[0],bht_vbank0_rd_data_f[0]}; // @[ifu_bp_ctl.scala 347:21]
assign io_ifu_bp_pc4_f = {_T_279,_T_282}; // @[ifu_bp_ctl.scala 348:19] assign io_ifu_bp_pc4_f = {_T_279,_T_282}; // @[ifu_bp_ctl.scala 348:19]
assign io_ifu_bp_valid_f = vwayhit_f & _T_353; // @[ifu_bp_ctl.scala 350:21] assign io_ifu_bp_valid_f = vwayhit_f & _T_353; // @[ifu_bp_ctl.scala 350:21]
assign io_ifu_bp_poffset_f = btb_sel_data_f[15:4]; // @[ifu_bp_ctl.scala 363:23] assign io_ifu_bp_poffset_f = btb_sel_data_f[15:4]; // @[ifu_bp_ctl.scala 362:23]
assign io_ifu_bp_fa_index_f_0 = 4'h0; // @[ifu_bp_ctl.scala 35:24] assign io_ifu_bp_fa_index_f_0 = 4'h0; // @[ifu_bp_ctl.scala 35:24]
assign io_ifu_bp_fa_index_f_1 = 4'h0; // @[ifu_bp_ctl.scala 35:24] assign io_ifu_bp_fa_index_f_1 = 4'h0; // @[ifu_bp_ctl.scala 35:24]
assign rvclkhdr_io_clk = clock; // @[lib.scala 401:18] assign rvclkhdr_io_clk = clock; // @[lib.scala 401:18]

5
src/main/scala/ifu/ifu_bp_ctl.scala
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@ -359,7 +359,6 @@ if(!BTB_FULLYA) {
val btb_fg_crossing_f = fetch_start_f(0) & btb_sel_f(0) & btb_rd_pc4_f val btb_fg_crossing_f = fetch_start_f(0) & btb_sel_f(0) & btb_rd_pc4_f
val bp_total_branch_offset_f = bloc_f(1)^btb_rd_pc4_f val bp_total_branch_offset_f = bloc_f(1)^btb_rd_pc4_f
val ifc_fetch_adder_prior = rvdfflie_UInt(io.ifc_fetch_addr_f(30,1), clock,reset.asAsyncReset,(io.ifc_fetch_req_f & !io.ifu_bp_hit_taken_f & io.ic_hit_f).asBool,io.scan_mode,WIDTH =30, LEFT =19 ) val ifc_fetch_adder_prior = rvdfflie_UInt(io.ifc_fetch_addr_f(30,1), clock,reset.asAsyncReset,(io.ifc_fetch_req_f & !io.ifu_bp_hit_taken_f & io.ic_hit_f).asBool,io.scan_mode,WIDTH =30, LEFT =19 )
io.ifu_bp_poffset_f := btb_rd_tgt_f io.ifu_bp_poffset_f := btb_rd_tgt_f
val adder_pc_in_f = Mux1H(Seq(use_fa_plus.asBool -> fetch_addr_p1_f, val adder_pc_in_f = Mux1H(Seq(use_fa_plus.asBool -> fetch_addr_p1_f,
@ -373,8 +372,7 @@ if(!BTB_FULLYA) {
rets_out := (0 until RET_STACK_SIZE).map(i=>0.U) rets_out := (0 until RET_STACK_SIZE).map(i=>0.U)
// Final target if its a RET then pop else take the target pc // Final target if its a RET then pop else take the target pc
io.ifu_bp_btb_target_f := ((Fill(31,(btb_rd_ret_f & !btb_rd_call_f & rets_out(0)(0) & io.ifu_bp_hit_taken_f)) & rets_out(0)(31,1)) | io.ifu_bp_btb_target_f := ((Fill(31,(btb_rd_ret_f & !btb_rd_call_f & rets_out(0)(0) & io.ifu_bp_hit_taken_f)) & rets_out(0)(31,1)) |
(Fill(31,(!btb_rd_ret_f & !btb_rd_call_f & rets_out(0)(0) & io.ifu_bp_hit_taken_f)) & bp_btb_target_adder_f(31,1))) (Fill(31,(!(btb_rd_ret_f & !btb_rd_call_f & rets_out(0)(0)) & io.ifu_bp_hit_taken_f)) & bp_btb_target_adder_f(31,1)))
// Return stack // Return stack
val bp_rs_call_target_f = rvbradder(Cat(adder_pc_in_f(29,0),bp_total_branch_offset_f, 0.U), Cat(Fill(11, 0.U),~btb_rd_pc4_f, 0.U)) val bp_rs_call_target_f = rvbradder(Cat(adder_pc_in_f(29,0),bp_total_branch_offset_f, 0.U), Cat(Fill(11, 0.U),~btb_rd_pc4_f, 0.U))
@ -537,7 +535,6 @@ if(!BTB_FULLYA) {
for(i<-0 until 2; k<-0 until BHT_ARRAY_DEPTH/NUM_BHT_LOOP; j<-0 until NUM_BHT_LOOP){ for(i<-0 until 2; k<-0 until BHT_ARRAY_DEPTH/NUM_BHT_LOOP; j<-0 until NUM_BHT_LOOP){
bht_bank_rd_data_out(i)((16*k)+j) := rvdffs_fpga(bht_bank_wr_data(i)(k)(j), bht_bank_sel(i)(k)(j),bht_bank_clk(i)(k),bht_bank_sel(i)(k)(j),clock)} bht_bank_rd_data_out(i)((16*k)+j) := rvdffs_fpga(bht_bank_wr_data(i)(k)(j), bht_bank_sel(i)(k)(j),bht_bank_clk(i)(k),bht_bank_sel(i)(k)(j),clock)}
// Make the final read mux // Make the final read mux
bht_bank0_rd_data_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_f===i.U).asBool->bht_bank_rd_data_out(0)(i))) bht_bank0_rd_data_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_f===i.U).asBool->bht_bank_rd_data_out(0)(i)))
bht_bank1_rd_data_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_f===i.U).asBool->bht_bank_rd_data_out(1)(i))) bht_bank1_rd_data_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_f===i.U).asBool->bht_bank_rd_data_out(1)(i)))

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target/scala-2.12/classes/ifu/bp_MAIN$.class
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target/scala-2.12/classes/ifu/bp_MAIN$delayedInit$body.class
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target/scala-2.12/classes/ifu/ifu_bp_ctl.class
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