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Aligner Updated

This commit is contained in:
waleed-lm 2020-10-13 13:21:02 +05:00
parent 8a6c7fd88f
commit 91ed771e91
4 changed files with 96 additions and 97 deletions
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116
el2_ifu_aln_ctl.fir
View File

@ -2589,27 +2589,27 @@ circuit el2_ifu_aln_ctl :
node _T_337 = and(_T_335, _T_336) @[el2_ifu_aln_ctl.scala 268:37] node _T_337 = and(_T_335, _T_336) @[el2_ifu_aln_ctl.scala 268:37]
node _T_338 = and(_T_337, f2_valid) @[el2_ifu_aln_ctl.scala 268:50] node _T_338 = and(_T_337, f2_valid) @[el2_ifu_aln_ctl.scala 268:50]
node _T_339 = and(_T_338, ifvalid) @[el2_ifu_aln_ctl.scala 268:62] node _T_339 = and(_T_338, ifvalid) @[el2_ifu_aln_ctl.scala 268:62]
node _T_340 = eq(sf0_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 269:6] node _T_340 = eq(sf0_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 269:26]
node _T_341 = and(_T_340, sf1_valid) @[el2_ifu_aln_ctl.scala 269:17] node _T_341 = and(_T_340, sf1_valid) @[el2_ifu_aln_ctl.scala 269:37]
node _T_342 = eq(f2_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 269:32] node _T_342 = eq(f2_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 269:52]
node _T_343 = and(_T_341, _T_342) @[el2_ifu_aln_ctl.scala 269:30] node _T_343 = and(_T_341, _T_342) @[el2_ifu_aln_ctl.scala 269:50]
node _T_344 = and(_T_343, ifvalid) @[el2_ifu_aln_ctl.scala 269:42] node _T_344 = and(_T_343, ifvalid) @[el2_ifu_aln_ctl.scala 269:62]
node _T_345 = or(_T_339, _T_344) @[el2_ifu_aln_ctl.scala 268:74] node _T_345 = or(_T_339, _T_344) @[el2_ifu_aln_ctl.scala 268:74]
node _T_346 = eq(sf1_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 270:19] node _T_346 = eq(sf1_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 270:39]
node _T_347 = and(sf0_valid, _T_346) @[el2_ifu_aln_ctl.scala 270:17] node _T_347 = and(sf0_valid, _T_346) @[el2_ifu_aln_ctl.scala 270:37]
node _T_348 = eq(f2_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 270:32] node _T_348 = eq(f2_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 270:52]
node _T_349 = and(_T_347, _T_348) @[el2_ifu_aln_ctl.scala 270:30] node _T_349 = and(_T_347, _T_348) @[el2_ifu_aln_ctl.scala 270:50]
node _T_350 = and(_T_349, ifvalid) @[el2_ifu_aln_ctl.scala 270:42] node _T_350 = and(_T_349, ifvalid) @[el2_ifu_aln_ctl.scala 270:62]
node _T_351 = or(_T_345, _T_350) @[el2_ifu_aln_ctl.scala 269:54] node _T_351 = or(_T_345, _T_350) @[el2_ifu_aln_ctl.scala 269:74]
fetch_to_f1 <= _T_351 @[el2_ifu_aln_ctl.scala 268:22] fetch_to_f1 <= _T_351 @[el2_ifu_aln_ctl.scala 268:22]
node _T_352 = eq(sf0_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 272:26] node _T_352 = eq(sf0_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 272:26]
node _T_353 = and(_T_352, sf1_valid) @[el2_ifu_aln_ctl.scala 272:37] node _T_353 = and(_T_352, sf1_valid) @[el2_ifu_aln_ctl.scala 272:37]
node _T_354 = and(_T_353, f2_valid) @[el2_ifu_aln_ctl.scala 272:50] node _T_354 = and(_T_353, f2_valid) @[el2_ifu_aln_ctl.scala 272:50]
node _T_355 = and(_T_354, ifvalid) @[el2_ifu_aln_ctl.scala 272:62] node _T_355 = and(_T_354, ifvalid) @[el2_ifu_aln_ctl.scala 272:62]
node _T_356 = and(sf0_valid, sf1_valid) @[el2_ifu_aln_ctl.scala 273:17] node _T_356 = and(sf0_valid, sf1_valid) @[el2_ifu_aln_ctl.scala 273:37]
node _T_357 = eq(f2_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 273:32] node _T_357 = eq(f2_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 273:52]
node _T_358 = and(_T_356, _T_357) @[el2_ifu_aln_ctl.scala 273:30] node _T_358 = and(_T_356, _T_357) @[el2_ifu_aln_ctl.scala 273:50]
node _T_359 = and(_T_358, ifvalid) @[el2_ifu_aln_ctl.scala 273:42] node _T_359 = and(_T_358, ifvalid) @[el2_ifu_aln_ctl.scala 273:62]
node _T_360 = or(_T_355, _T_359) @[el2_ifu_aln_ctl.scala 272:74] node _T_360 = or(_T_355, _T_359) @[el2_ifu_aln_ctl.scala 272:74]
fetch_to_f2 <= _T_360 @[el2_ifu_aln_ctl.scala 272:22] fetch_to_f2 <= _T_360 @[el2_ifu_aln_ctl.scala 272:22]
node _T_361 = add(f0pc, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 275:25] node _T_361 = add(f0pc, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 275:25]
@ -2660,14 +2660,14 @@ circuit el2_ifu_aln_ctl :
node _T_399 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 290:40] node _T_399 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 290:40]
node _T_400 = and(fetch_to_f2, _T_399) @[el2_ifu_aln_ctl.scala 290:38] node _T_400 = and(fetch_to_f2, _T_399) @[el2_ifu_aln_ctl.scala 290:38]
node _T_401 = bits(_T_400, 0, 0) @[el2_ifu_aln_ctl.scala 290:61] node _T_401 = bits(_T_400, 0, 0) @[el2_ifu_aln_ctl.scala 290:61]
node _T_402 = eq(fetch_to_f2, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 291:6] node _T_402 = eq(fetch_to_f2, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 291:25]
node _T_403 = eq(shift_f2_f1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 291:21] node _T_403 = eq(shift_f2_f1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 291:40]
node _T_404 = and(_T_402, _T_403) @[el2_ifu_aln_ctl.scala 291:19] node _T_404 = and(_T_402, _T_403) @[el2_ifu_aln_ctl.scala 291:38]
node _T_405 = eq(shift_f2_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 291:36] node _T_405 = eq(shift_f2_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 291:55]
node _T_406 = and(_T_404, _T_405) @[el2_ifu_aln_ctl.scala 291:34] node _T_406 = and(_T_404, _T_405) @[el2_ifu_aln_ctl.scala 291:53]
node _T_407 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 291:51] node _T_407 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 291:70]
node _T_408 = and(_T_406, _T_407) @[el2_ifu_aln_ctl.scala 291:49] node _T_408 = and(_T_406, _T_407) @[el2_ifu_aln_ctl.scala 291:68]
node _T_409 = bits(_T_408, 0, 0) @[el2_ifu_aln_ctl.scala 291:72] node _T_409 = bits(_T_408, 0, 0) @[el2_ifu_aln_ctl.scala 291:91]
node _T_410 = mux(_T_401, io.ifu_fetch_val, UInt<1>("h00")) @[Mux.scala 27:72] node _T_410 = mux(_T_401, io.ifu_fetch_val, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_411 = mux(_T_409, f2val, UInt<1>("h00")) @[Mux.scala 27:72] node _T_411 = mux(_T_409, f2val, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_412 = or(_T_410, _T_411) @[Mux.scala 27:72] node _T_412 = or(_T_410, _T_411) @[Mux.scala 27:72]
@ -2684,20 +2684,20 @@ circuit el2_ifu_aln_ctl :
wire _T_421 : UInt @[Mux.scala 27:72] wire _T_421 : UInt @[Mux.scala 27:72]
_T_421 <= _T_420 @[Mux.scala 27:72] _T_421 <= _T_420 @[Mux.scala 27:72]
sf1val <= _T_421 @[el2_ifu_aln_ctl.scala 293:10] sf1val <= _T_421 @[el2_ifu_aln_ctl.scala 293:10]
node _T_422 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 295:40] node _T_422 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 295:71]
node _T_423 = and(fetch_to_f1, _T_422) @[el2_ifu_aln_ctl.scala 295:38] node _T_423 = and(fetch_to_f1, _T_422) @[el2_ifu_aln_ctl.scala 295:39]
node _T_424 = bits(_T_423, 0, 0) @[el2_ifu_aln_ctl.scala 295:61] node _T_424 = bits(_T_423, 0, 0) @[el2_ifu_aln_ctl.scala 295:92]
node _T_425 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 296:20] node _T_425 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 296:71]
node _T_426 = and(shift_f2_f1, _T_425) @[el2_ifu_aln_ctl.scala 296:18] node _T_426 = and(shift_f2_f1, _T_425) @[el2_ifu_aln_ctl.scala 296:54]
node _T_427 = bits(_T_426, 0, 0) @[el2_ifu_aln_ctl.scala 296:41] node _T_427 = bits(_T_426, 0, 0) @[el2_ifu_aln_ctl.scala 296:92]
node _T_428 = eq(fetch_to_f1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 297:6] node _T_428 = eq(fetch_to_f1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 297:26]
node _T_429 = eq(shift_f2_f1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 297:21] node _T_429 = eq(shift_f2_f1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 297:41]
node _T_430 = and(_T_428, _T_429) @[el2_ifu_aln_ctl.scala 297:19] node _T_430 = and(_T_428, _T_429) @[el2_ifu_aln_ctl.scala 297:39]
node _T_431 = eq(shift_f1_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 297:36] node _T_431 = eq(shift_f1_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 297:56]
node _T_432 = and(_T_430, _T_431) @[el2_ifu_aln_ctl.scala 297:34] node _T_432 = and(_T_430, _T_431) @[el2_ifu_aln_ctl.scala 297:54]
node _T_433 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 297:51] node _T_433 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 297:71]
node _T_434 = and(_T_432, _T_433) @[el2_ifu_aln_ctl.scala 297:49] node _T_434 = and(_T_432, _T_433) @[el2_ifu_aln_ctl.scala 297:69]
node _T_435 = bits(_T_434, 0, 0) @[el2_ifu_aln_ctl.scala 297:72] node _T_435 = bits(_T_434, 0, 0) @[el2_ifu_aln_ctl.scala 297:92]
node _T_436 = mux(_T_424, io.ifu_fetch_val, UInt<1>("h00")) @[Mux.scala 27:72] node _T_436 = mux(_T_424, io.ifu_fetch_val, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_437 = mux(_T_427, f2val, UInt<1>("h00")) @[Mux.scala 27:72] node _T_437 = mux(_T_427, f2val, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_438 = mux(_T_435, sf1val, UInt<1>("h00")) @[Mux.scala 27:72] node _T_438 = mux(_T_435, sf1val, UInt<1>("h00")) @[Mux.scala 27:72]
@ -2709,33 +2709,33 @@ circuit el2_ifu_aln_ctl :
node _T_442 = bits(shift_2B, 0, 0) @[el2_ifu_aln_ctl.scala 299:32] node _T_442 = bits(shift_2B, 0, 0) @[el2_ifu_aln_ctl.scala 299:32]
node _T_443 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 299:54] node _T_443 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 299:54]
node _T_444 = cat(UInt<1>("h00"), _T_443) @[Cat.scala 29:58] node _T_444 = cat(UInt<1>("h00"), _T_443) @[Cat.scala 29:58]
node _T_445 = eq(shift_2B, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 300:6] node _T_445 = eq(shift_2B, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 300:18]
node _T_446 = eq(shift_4B, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 300:18] node _T_446 = eq(shift_4B, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 300:30]
node _T_447 = and(_T_445, _T_446) @[el2_ifu_aln_ctl.scala 300:16] node _T_447 = and(_T_445, _T_446) @[el2_ifu_aln_ctl.scala 300:28]
node _T_448 = bits(_T_447, 0, 0) @[el2_ifu_aln_ctl.scala 300:29] node _T_448 = bits(_T_447, 0, 0) @[el2_ifu_aln_ctl.scala 300:41]
node _T_449 = mux(_T_442, _T_444, UInt<1>("h00")) @[Mux.scala 27:72] node _T_449 = mux(_T_442, _T_444, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_450 = mux(_T_448, f1val, UInt<1>("h00")) @[Mux.scala 27:72] node _T_450 = mux(_T_448, f0val, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_451 = or(_T_449, _T_450) @[Mux.scala 27:72] node _T_451 = or(_T_449, _T_450) @[Mux.scala 27:72]
wire _T_452 : UInt @[Mux.scala 27:72] wire _T_452 : UInt @[Mux.scala 27:72]
_T_452 <= _T_451 @[Mux.scala 27:72] _T_452 <= _T_451 @[Mux.scala 27:72]
sf0val <= _T_452 @[el2_ifu_aln_ctl.scala 299:10] sf0val <= _T_452 @[el2_ifu_aln_ctl.scala 299:10]
node _T_453 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 302:40] node _T_453 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 302:71]
node _T_454 = and(fetch_to_f0, _T_453) @[el2_ifu_aln_ctl.scala 302:38] node _T_454 = and(fetch_to_f0, _T_453) @[el2_ifu_aln_ctl.scala 302:38]
node _T_455 = bits(_T_454, 0, 0) @[el2_ifu_aln_ctl.scala 302:61] node _T_455 = bits(_T_454, 0, 0) @[el2_ifu_aln_ctl.scala 302:92]
node _T_456 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 303:20] node _T_456 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 303:71]
node _T_457 = and(shift_f2_f0, _T_456) @[el2_ifu_aln_ctl.scala 303:18] node _T_457 = and(shift_f2_f0, _T_456) @[el2_ifu_aln_ctl.scala 303:54]
node _T_458 = bits(_T_457, 0, 0) @[el2_ifu_aln_ctl.scala 303:41] node _T_458 = bits(_T_457, 0, 0) @[el2_ifu_aln_ctl.scala 303:92]
node _T_459 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 304:20] node _T_459 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 304:71]
node _T_460 = and(shift_f1_f0, _T_459) @[el2_ifu_aln_ctl.scala 304:18] node _T_460 = and(shift_f1_f0, _T_459) @[el2_ifu_aln_ctl.scala 304:69]
node _T_461 = bits(_T_460, 0, 0) @[el2_ifu_aln_ctl.scala 304:47] node _T_461 = bits(_T_460, 0, 0) @[el2_ifu_aln_ctl.scala 304:92]
node _T_462 = eq(fetch_to_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 305:6] node _T_462 = eq(fetch_to_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 305:26]
node _T_463 = eq(shift_f2_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 305:21] node _T_463 = eq(shift_f2_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 305:41]
node _T_464 = and(_T_462, _T_463) @[el2_ifu_aln_ctl.scala 305:19] node _T_464 = and(_T_462, _T_463) @[el2_ifu_aln_ctl.scala 305:39]
node _T_465 = eq(shift_f1_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 305:36] node _T_465 = eq(shift_f1_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 305:56]
node _T_466 = and(_T_464, _T_465) @[el2_ifu_aln_ctl.scala 305:34] node _T_466 = and(_T_464, _T_465) @[el2_ifu_aln_ctl.scala 305:54]
node _T_467 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 305:51] node _T_467 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 305:71]
node _T_468 = and(_T_466, _T_467) @[el2_ifu_aln_ctl.scala 305:49] node _T_468 = and(_T_466, _T_467) @[el2_ifu_aln_ctl.scala 305:69]
node _T_469 = bits(_T_468, 0, 0) @[el2_ifu_aln_ctl.scala 305:72] node _T_469 = bits(_T_468, 0, 0) @[el2_ifu_aln_ctl.scala 305:92]
node _T_470 = mux(_T_455, io.ifu_fetch_val, UInt<1>("h00")) @[Mux.scala 27:72] node _T_470 = mux(_T_455, io.ifu_fetch_val, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_471 = mux(_T_458, f2val, UInt<1>("h00")) @[Mux.scala 27:72] node _T_471 = mux(_T_458, f2val, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_472 = mux(_T_461, sf1val, UInt<1>("h00")) @[Mux.scala 27:72] node _T_472 = mux(_T_461, sf1val, UInt<1>("h00")) @[Mux.scala 27:72]

50
el2_ifu_aln_ctl.v
View File

@ -644,11 +644,11 @@ module el2_ifu_aln_ctl(
wire shift_2B = i0_shift & first2B; // @[el2_ifu_aln_ctl.scala 412:24] wire shift_2B = i0_shift & first2B; // @[el2_ifu_aln_ctl.scala 412:24]
wire [1:0] _T_444 = {1'h0,f0val[1]}; // @[Cat.scala 29:58] wire [1:0] _T_444 = {1'h0,f0val[1]}; // @[Cat.scala 29:58]
wire [1:0] _T_449 = shift_2B ? _T_444 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_449 = shift_2B ? _T_444 : 2'h0; // @[Mux.scala 27:72]
wire _T_445 = ~shift_2B; // @[el2_ifu_aln_ctl.scala 300:6] wire _T_445 = ~shift_2B; // @[el2_ifu_aln_ctl.scala 300:18]
wire shift_4B = i0_shift & first4B; // @[el2_ifu_aln_ctl.scala 413:24] wire shift_4B = i0_shift & first4B; // @[el2_ifu_aln_ctl.scala 413:24]
wire _T_446 = ~shift_4B; // @[el2_ifu_aln_ctl.scala 300:18] wire _T_446 = ~shift_4B; // @[el2_ifu_aln_ctl.scala 300:30]
wire _T_447 = _T_445 & _T_446; // @[el2_ifu_aln_ctl.scala 300:16] wire _T_447 = _T_445 & _T_446; // @[el2_ifu_aln_ctl.scala 300:28]
wire [1:0] _T_450 = _T_447 ? f1val : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_450 = _T_447 ? f0val : 2'h0; // @[Mux.scala 27:72]
wire [1:0] sf0val = _T_449 | _T_450; // @[Mux.scala 27:72] wire [1:0] sf0val = _T_449 | _T_450; // @[Mux.scala 27:72]
wire sf0_valid = sf0val[0]; // @[el2_ifu_aln_ctl.scala 253:22] wire sf0_valid = sf0val[0]; // @[el2_ifu_aln_ctl.scala 253:22]
wire _T_352 = ~sf0_valid; // @[el2_ifu_aln_ctl.scala 272:26] wire _T_352 = ~sf0_valid; // @[el2_ifu_aln_ctl.scala 272:26]
@ -665,23 +665,23 @@ module el2_ifu_aln_ctl(
wire _T_354 = _T_353 & f2_valid; // @[el2_ifu_aln_ctl.scala 272:50] wire _T_354 = _T_353 & f2_valid; // @[el2_ifu_aln_ctl.scala 272:50]
wire ifvalid = io_ifu_fetch_val[0]; // @[el2_ifu_aln_ctl.scala 261:30] wire ifvalid = io_ifu_fetch_val[0]; // @[el2_ifu_aln_ctl.scala 261:30]
wire _T_355 = _T_354 & ifvalid; // @[el2_ifu_aln_ctl.scala 272:62] wire _T_355 = _T_354 & ifvalid; // @[el2_ifu_aln_ctl.scala 272:62]
wire _T_356 = sf0_valid & sf1_valid; // @[el2_ifu_aln_ctl.scala 273:17] wire _T_356 = sf0_valid & sf1_valid; // @[el2_ifu_aln_ctl.scala 273:37]
wire _T_357 = ~f2_valid; // @[el2_ifu_aln_ctl.scala 273:32] wire _T_357 = ~f2_valid; // @[el2_ifu_aln_ctl.scala 273:52]
wire _T_358 = _T_356 & _T_357; // @[el2_ifu_aln_ctl.scala 273:30] wire _T_358 = _T_356 & _T_357; // @[el2_ifu_aln_ctl.scala 273:50]
wire _T_359 = _T_358 & ifvalid; // @[el2_ifu_aln_ctl.scala 273:42] wire _T_359 = _T_358 & ifvalid; // @[el2_ifu_aln_ctl.scala 273:62]
wire fetch_to_f2 = _T_355 | _T_359; // @[el2_ifu_aln_ctl.scala 272:74] wire fetch_to_f2 = _T_355 | _T_359; // @[el2_ifu_aln_ctl.scala 272:74]
reg [30:0] f2pc; // @[Reg.scala 27:20] reg [30:0] f2pc; // @[Reg.scala 27:20]
wire _T_336 = ~sf1_valid; // @[el2_ifu_aln_ctl.scala 268:39] wire _T_336 = ~sf1_valid; // @[el2_ifu_aln_ctl.scala 268:39]
wire _T_337 = _T_352 & _T_336; // @[el2_ifu_aln_ctl.scala 268:37] wire _T_337 = _T_352 & _T_336; // @[el2_ifu_aln_ctl.scala 268:37]
wire _T_338 = _T_337 & f2_valid; // @[el2_ifu_aln_ctl.scala 268:50] wire _T_338 = _T_337 & f2_valid; // @[el2_ifu_aln_ctl.scala 268:50]
wire _T_339 = _T_338 & ifvalid; // @[el2_ifu_aln_ctl.scala 268:62] wire _T_339 = _T_338 & ifvalid; // @[el2_ifu_aln_ctl.scala 268:62]
wire _T_343 = _T_353 & _T_357; // @[el2_ifu_aln_ctl.scala 269:30] wire _T_343 = _T_353 & _T_357; // @[el2_ifu_aln_ctl.scala 269:50]
wire _T_344 = _T_343 & ifvalid; // @[el2_ifu_aln_ctl.scala 269:42] wire _T_344 = _T_343 & ifvalid; // @[el2_ifu_aln_ctl.scala 269:62]
wire _T_345 = _T_339 | _T_344; // @[el2_ifu_aln_ctl.scala 268:74] wire _T_345 = _T_339 | _T_344; // @[el2_ifu_aln_ctl.scala 268:74]
wire _T_347 = sf0_valid & _T_336; // @[el2_ifu_aln_ctl.scala 270:17] wire _T_347 = sf0_valid & _T_336; // @[el2_ifu_aln_ctl.scala 270:37]
wire _T_349 = _T_347 & _T_357; // @[el2_ifu_aln_ctl.scala 270:30] wire _T_349 = _T_347 & _T_357; // @[el2_ifu_aln_ctl.scala 270:50]
wire _T_350 = _T_349 & ifvalid; // @[el2_ifu_aln_ctl.scala 270:42] wire _T_350 = _T_349 & ifvalid; // @[el2_ifu_aln_ctl.scala 270:62]
wire fetch_to_f1 = _T_345 | _T_350; // @[el2_ifu_aln_ctl.scala 269:54] wire fetch_to_f1 = _T_345 | _T_350; // @[el2_ifu_aln_ctl.scala 269:74]
wire _T_25 = fetch_to_f1 | _T_354; // @[el2_ifu_aln_ctl.scala 157:33] wire _T_25 = fetch_to_f1 | _T_354; // @[el2_ifu_aln_ctl.scala 157:33]
wire f1_shift_wr_en = _T_25 | f1_shift_2B; // @[el2_ifu_aln_ctl.scala 157:47] wire f1_shift_wr_en = _T_25 | f1_shift_2B; // @[el2_ifu_aln_ctl.scala 157:47]
reg [30:0] f1pc; // @[Reg.scala 27:20] reg [30:0] f1pc; // @[Reg.scala 27:20]
@ -863,26 +863,26 @@ module el2_ifu_aln_ctl(
wire _T_313 = consume_fb0 & _T_312; // @[el2_ifu_aln_ctl.scala 258:37] wire _T_313 = consume_fb0 & _T_312; // @[el2_ifu_aln_ctl.scala 258:37]
wire _T_316 = consume_fb0 & consume_fb1; // @[el2_ifu_aln_ctl.scala 259:37] wire _T_316 = consume_fb0 & consume_fb1; // @[el2_ifu_aln_ctl.scala 259:37]
wire _T_400 = fetch_to_f2 & _T_1; // @[el2_ifu_aln_ctl.scala 290:38] wire _T_400 = fetch_to_f2 & _T_1; // @[el2_ifu_aln_ctl.scala 290:38]
wire _T_402 = ~fetch_to_f2; // @[el2_ifu_aln_ctl.scala 291:6] wire _T_402 = ~fetch_to_f2; // @[el2_ifu_aln_ctl.scala 291:25]
wire _T_404 = _T_402 & _T_373; // @[el2_ifu_aln_ctl.scala 291:19] wire _T_404 = _T_402 & _T_373; // @[el2_ifu_aln_ctl.scala 291:38]
wire _T_406 = _T_404 & _T_386; // @[el2_ifu_aln_ctl.scala 291:34] wire _T_406 = _T_404 & _T_386; // @[el2_ifu_aln_ctl.scala 291:53]
wire _T_408 = _T_406 & _T_1; // @[el2_ifu_aln_ctl.scala 291:49] wire _T_408 = _T_406 & _T_1; // @[el2_ifu_aln_ctl.scala 291:68]
wire [1:0] _T_410 = _T_400 ? io_ifu_fetch_val : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_410 = _T_400 ? io_ifu_fetch_val : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_411 = _T_408 ? f2val : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_411 = _T_408 ? f2val : 2'h0; // @[Mux.scala 27:72]
wire [1:0] f2val_in = _T_410 | _T_411; // @[Mux.scala 27:72] wire [1:0] f2val_in = _T_410 | _T_411; // @[Mux.scala 27:72]
wire _T_423 = fetch_to_f1 & _T_1; // @[el2_ifu_aln_ctl.scala 295:38] wire _T_423 = fetch_to_f1 & _T_1; // @[el2_ifu_aln_ctl.scala 295:39]
wire _T_426 = _T_354 & _T_1; // @[el2_ifu_aln_ctl.scala 296:18] wire _T_426 = _T_354 & _T_1; // @[el2_ifu_aln_ctl.scala 296:54]
wire _T_432 = _T_374 & _T_388; // @[el2_ifu_aln_ctl.scala 297:34] wire _T_432 = _T_374 & _T_388; // @[el2_ifu_aln_ctl.scala 297:54]
wire _T_434 = _T_432 & _T_1; // @[el2_ifu_aln_ctl.scala 297:49] wire _T_434 = _T_432 & _T_1; // @[el2_ifu_aln_ctl.scala 297:69]
wire [1:0] _T_436 = _T_423 ? io_ifu_fetch_val : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_436 = _T_423 ? io_ifu_fetch_val : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_437 = _T_426 ? f2val : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_437 = _T_426 ? f2val : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_438 = _T_434 ? sf1val : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_438 = _T_434 ? sf1val : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_439 = _T_436 | _T_437; // @[Mux.scala 27:72] wire [1:0] _T_439 = _T_436 | _T_437; // @[Mux.scala 27:72]
wire [1:0] f1val_in = _T_439 | _T_438; // @[Mux.scala 27:72] wire [1:0] f1val_in = _T_439 | _T_438; // @[Mux.scala 27:72]
wire _T_454 = fetch_to_f0 & _T_1; // @[el2_ifu_aln_ctl.scala 302:38] wire _T_454 = fetch_to_f0 & _T_1; // @[el2_ifu_aln_ctl.scala 302:38]
wire _T_457 = _T_338 & _T_1; // @[el2_ifu_aln_ctl.scala 303:18] wire _T_457 = _T_338 & _T_1; // @[el2_ifu_aln_ctl.scala 303:54]
wire _T_460 = _T_353 & _T_1; // @[el2_ifu_aln_ctl.scala 304:18] wire _T_460 = _T_353 & _T_1; // @[el2_ifu_aln_ctl.scala 304:69]
wire _T_468 = _T_389 & _T_1; // @[el2_ifu_aln_ctl.scala 305:49] wire _T_468 = _T_389 & _T_1; // @[el2_ifu_aln_ctl.scala 305:69]
wire [1:0] _T_470 = _T_454 ? io_ifu_fetch_val : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_470 = _T_454 ? io_ifu_fetch_val : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_471 = _T_457 ? f2val : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_471 = _T_457 ? f2val : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_472 = _T_460 ? sf1val : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_472 = _T_460 ? sf1val : 2'h0; // @[Mux.scala 27:72]

7
src/main/scala/ifu/el2_ifu_aln_ctl.scala
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@ -37,8 +37,7 @@ class el2_ifu_aln_ctl extends Module with el2_lib {
val ifu_i0_pc4 = Output(Bool()) val ifu_i0_pc4 = Output(Bool())
val ifu_fb_consume1 = Output(Bool()) val ifu_fb_consume1 = Output(Bool())
val ifu_fb_consume2 = Output(Bool()) val ifu_fb_consume2 = Output(Bool())
val ifu_i0_bp_index = Output(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1 val ifu_i0_bp_index = Output(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W))
).W))
val ifu_i0_bp_fghr = Output(UInt(BHT_GHR_SIZE.W)) val ifu_i0_bp_fghr = Output(UInt(BHT_GHR_SIZE.W))
val ifu_i0_bp_btag = Output(UInt(BTB_BTAG_SIZE.W)) val ifu_i0_bp_btag = Output(UInt(BTB_BTAG_SIZE.W))
val ifu_pmu_instr_aligned = Output(Bool()) val ifu_pmu_instr_aligned = Output(Bool())
@ -298,11 +297,11 @@ class el2_ifu_aln_ctl extends Module with el2_lib {
(!fetch_to_f1 & !shift_f2_f1 & !shift_f1_f0 & !io.exu_flush_final).asBool->sf1val)) (!fetch_to_f1 & !shift_f2_f1 & !shift_f1_f0 & !io.exu_flush_final).asBool->sf1val))
sf0val := Mux1H(Seq(shift_2B.asBool->Cat(0.U, f0val(1)), sf0val := Mux1H(Seq(shift_2B.asBool->Cat(0.U, f0val(1)),
(!shift_2B & !shift_4B).asBool->f1val)) (!shift_2B & !shift_4B).asBool->f0val))
f0val_in := Mux1H(Seq((fetch_to_f0 & !io.exu_flush_final).asBool->io.ifu_fetch_val, f0val_in := Mux1H(Seq((fetch_to_f0 & !io.exu_flush_final).asBool->io.ifu_fetch_val,
( shift_f2_f0 & !io.exu_flush_final).asBool->f2val, ( shift_f2_f0 & !io.exu_flush_final).asBool->f2val,
(shift_f1_f0 & !io.exu_flush_final).asBool()->sf1val, ( shift_f1_f0 & !io.exu_flush_final).asBool->sf1val,
(!fetch_to_f0 & !shift_f2_f0 & !shift_f1_f0 & !io.exu_flush_final).asBool->sf0val)) (!fetch_to_f0 & !shift_f2_f0 & !shift_f1_f0 & !io.exu_flush_final).asBool->sf0val))
val qeff = Mux1H(Seq(qren(0).asBool->Cat(q1,q0), val qeff = Mux1H(Seq(qren(0).asBool->Cat(q1,q0),

BIN
target/scala-2.12/classes/ifu/el2_ifu_aln_ctl.class
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