From 92cf8220898a29af4c1485734e2f97de28d81b27 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=E2=80=8BLaraib=20Khan?= <​laraib.khan@lampromellon.com>
Date: Wed, 6 Jan 2021 15:04:21 +0500
Subject: [PATCH] divider 4 added

---
 exu_div_new_3bit_fullshortq.anno.json         |   30 +
 exu_div_new_3bit_fullshortq.fir               | 2430 +++++++++++++++++
 exu_div_new_3bit_fullshortq.v                 | 1082 ++++++++
 src/main/scala/exu/exu_div_ctl.scala          |  254 +-
 .../exu/div_main3$delayedInit$body.class      |  Bin 744 -> 0 bytes
 .../{div_main3$.class => div_main4$.class}    |  Bin 3905 -> 3905 bytes
 .../exu/div_main4$delayedInit$body.class      |  Bin 0 -> 744 bytes
 .../exu/{div_main3.class => div_main4.class}  |  Bin 787 -> 787 bytes
 .../classes/exu/exu_div_cls$$anon$7.class     |  Bin 1694 -> 1694 bytes
 .../scala-2.12/classes/exu/exu_div_cls.class  |  Bin 11053 -> 11054 bytes
 .../exu_div_existing_1bit_cheapshortq.class   |  Bin 112188 -> 112188 bytes
 .../exu/exu_div_new_1bit_fullshortq.class     |  Bin 104405 -> 104405 bytes
 .../exu/exu_div_new_2bit_fullshortq.class     |  Bin 108459 -> 108459 bytes
 .../exu_div_new_3bit_fullshortq$$anon$5.class |  Bin 2817 -> 2817 bytes
 .../exu/exu_div_new_3bit_fullshortq.class     |  Bin 49555 -> 118142 bytes
 .../exu_div_new_4bit_fullshortq$$anon$6.class |  Bin 2817 -> 2817 bytes
 .../exu/exu_div_new_4bit_fullshortq.class     |  Bin 49555 -> 49555 bytes
 17 files changed, 3751 insertions(+), 45 deletions(-)
 create mode 100644 exu_div_new_3bit_fullshortq.anno.json
 create mode 100644 exu_div_new_3bit_fullshortq.fir
 create mode 100644 exu_div_new_3bit_fullshortq.v
 delete mode 100644 target/scala-2.12/classes/exu/div_main3$delayedInit$body.class
 rename target/scala-2.12/classes/exu/{div_main3$.class => div_main4$.class} (73%)
 create mode 100644 target/scala-2.12/classes/exu/div_main4$delayedInit$body.class
 rename target/scala-2.12/classes/exu/{div_main3.class => div_main4.class} (65%)

diff --git a/exu_div_new_3bit_fullshortq.anno.json b/exu_div_new_3bit_fullshortq.anno.json
new file mode 100644
index 00000000..904bed6c
--- /dev/null
+++ b/exu_div_new_3bit_fullshortq.anno.json
@@ -0,0 +1,30 @@
+[
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~exu_div_new_3bit_fullshortq|exu_div_new_3bit_fullshortq>io_valid_out",
+    "sources":[
+      "~exu_div_new_3bit_fullshortq|exu_div_new_3bit_fullshortq>io_cancel"
+    ]
+  },
+  {
+    "class":"firrtl.EmitCircuitAnnotation",
+    "emitter":"firrtl.VerilogEmitter"
+  },
+  {
+    "class":"firrtl.transforms.BlackBoxResourceAnno",
+    "target":"exu_div_new_3bit_fullshortq.gated_latch",
+    "resourceId":"/vsrc/gated_latch.sv"
+  },
+  {
+    "class":"firrtl.options.TargetDirAnnotation",
+    "directory":"."
+  },
+  {
+    "class":"firrtl.options.OutputAnnotationFileAnnotation",
+    "file":"exu_div_new_3bit_fullshortq"
+  },
+  {
+    "class":"firrtl.transforms.BlackBoxTargetDirAnno",
+    "targetDir":"."
+  }
+]
\ No newline at end of file
diff --git a/exu_div_new_3bit_fullshortq.fir b/exu_div_new_3bit_fullshortq.fir
new file mode 100644
index 00000000..f614d4fd
--- /dev/null
+++ b/exu_div_new_3bit_fullshortq.fir
@@ -0,0 +1,2430 @@
+;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
+circuit exu_div_new_3bit_fullshortq : 
+  module exu_div_cls : 
+    input clock : Clock
+    input reset : Reset
+    output io : {flip operand : UInt<33>, cls : UInt<5>}
+    
+    wire cls_zeros : UInt<5>
+    cls_zeros <= UInt<5>("h00")
+    wire cls_ones : UInt<5>
+    cls_ones <= UInt<5>("h00")
+    node _T = bits(io.operand, 31, 31) @[exu_div_ctl.scala 819:54]
+    node _T_1 = eq(_T, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_2 = bits(io.operand, 31, 30) @[exu_div_ctl.scala 819:54]
+    node _T_3 = eq(_T_2, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_4 = bits(io.operand, 31, 29) @[exu_div_ctl.scala 819:54]
+    node _T_5 = eq(_T_4, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_6 = bits(io.operand, 31, 28) @[exu_div_ctl.scala 819:54]
+    node _T_7 = eq(_T_6, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_8 = bits(io.operand, 31, 27) @[exu_div_ctl.scala 819:54]
+    node _T_9 = eq(_T_8, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_10 = bits(io.operand, 31, 26) @[exu_div_ctl.scala 819:54]
+    node _T_11 = eq(_T_10, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_12 = bits(io.operand, 31, 25) @[exu_div_ctl.scala 819:54]
+    node _T_13 = eq(_T_12, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_14 = bits(io.operand, 31, 24) @[exu_div_ctl.scala 819:54]
+    node _T_15 = eq(_T_14, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_16 = bits(io.operand, 31, 23) @[exu_div_ctl.scala 819:54]
+    node _T_17 = eq(_T_16, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_18 = bits(io.operand, 31, 22) @[exu_div_ctl.scala 819:54]
+    node _T_19 = eq(_T_18, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_20 = bits(io.operand, 31, 21) @[exu_div_ctl.scala 819:54]
+    node _T_21 = eq(_T_20, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_22 = bits(io.operand, 31, 20) @[exu_div_ctl.scala 819:54]
+    node _T_23 = eq(_T_22, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_24 = bits(io.operand, 31, 19) @[exu_div_ctl.scala 819:54]
+    node _T_25 = eq(_T_24, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_26 = bits(io.operand, 31, 18) @[exu_div_ctl.scala 819:54]
+    node _T_27 = eq(_T_26, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_28 = bits(io.operand, 31, 17) @[exu_div_ctl.scala 819:54]
+    node _T_29 = eq(_T_28, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_30 = bits(io.operand, 31, 16) @[exu_div_ctl.scala 819:54]
+    node _T_31 = eq(_T_30, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_32 = bits(io.operand, 31, 15) @[exu_div_ctl.scala 819:54]
+    node _T_33 = eq(_T_32, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_34 = bits(io.operand, 31, 14) @[exu_div_ctl.scala 819:54]
+    node _T_35 = eq(_T_34, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_36 = bits(io.operand, 31, 13) @[exu_div_ctl.scala 819:54]
+    node _T_37 = eq(_T_36, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_38 = bits(io.operand, 31, 12) @[exu_div_ctl.scala 819:54]
+    node _T_39 = eq(_T_38, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_40 = bits(io.operand, 31, 11) @[exu_div_ctl.scala 819:54]
+    node _T_41 = eq(_T_40, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_42 = bits(io.operand, 31, 10) @[exu_div_ctl.scala 819:54]
+    node _T_43 = eq(_T_42, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_44 = bits(io.operand, 31, 9) @[exu_div_ctl.scala 819:54]
+    node _T_45 = eq(_T_44, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_46 = bits(io.operand, 31, 8) @[exu_div_ctl.scala 819:54]
+    node _T_47 = eq(_T_46, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_48 = bits(io.operand, 31, 7) @[exu_div_ctl.scala 819:54]
+    node _T_49 = eq(_T_48, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_50 = bits(io.operand, 31, 6) @[exu_div_ctl.scala 819:54]
+    node _T_51 = eq(_T_50, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_52 = bits(io.operand, 31, 5) @[exu_div_ctl.scala 819:54]
+    node _T_53 = eq(_T_52, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_54 = bits(io.operand, 31, 4) @[exu_div_ctl.scala 819:54]
+    node _T_55 = eq(_T_54, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_56 = bits(io.operand, 31, 3) @[exu_div_ctl.scala 819:54]
+    node _T_57 = eq(_T_56, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_58 = bits(io.operand, 31, 2) @[exu_div_ctl.scala 819:54]
+    node _T_59 = eq(_T_58, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_60 = bits(io.operand, 31, 1) @[exu_div_ctl.scala 819:54]
+    node _T_61 = eq(_T_60, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_62 = bits(io.operand, 31, 0) @[exu_div_ctl.scala 819:54]
+    node _T_63 = eq(_T_62, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_64 = mux(_T_1, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_65 = mux(_T_3, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_66 = mux(_T_5, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_67 = mux(_T_7, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_68 = mux(_T_9, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_69 = mux(_T_11, UInt<3>("h05"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_70 = mux(_T_13, UInt<3>("h06"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_71 = mux(_T_15, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_72 = mux(_T_17, UInt<4>("h08"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_73 = mux(_T_19, UInt<4>("h09"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_74 = mux(_T_21, UInt<4>("h0a"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_75 = mux(_T_23, UInt<4>("h0b"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_76 = mux(_T_25, UInt<4>("h0c"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_77 = mux(_T_27, UInt<4>("h0d"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_78 = mux(_T_29, UInt<4>("h0e"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_79 = mux(_T_31, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_80 = mux(_T_33, UInt<5>("h010"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_81 = mux(_T_35, UInt<5>("h011"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_82 = mux(_T_37, UInt<5>("h012"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_83 = mux(_T_39, UInt<5>("h013"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_84 = mux(_T_41, UInt<5>("h014"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_85 = mux(_T_43, UInt<5>("h015"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_86 = mux(_T_45, UInt<5>("h016"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_87 = mux(_T_47, UInt<5>("h017"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_88 = mux(_T_49, UInt<5>("h018"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_89 = mux(_T_51, UInt<5>("h019"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_90 = mux(_T_53, UInt<5>("h01a"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_91 = mux(_T_55, UInt<5>("h01b"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_92 = mux(_T_57, UInt<5>("h01c"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_93 = mux(_T_59, UInt<5>("h01d"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_94 = mux(_T_61, UInt<5>("h01e"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_95 = mux(_T_63, UInt<5>("h01f"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_96 = or(_T_64, _T_65) @[Mux.scala 27:72]
+    node _T_97 = or(_T_96, _T_66) @[Mux.scala 27:72]
+    node _T_98 = or(_T_97, _T_67) @[Mux.scala 27:72]
+    node _T_99 = or(_T_98, _T_68) @[Mux.scala 27:72]
+    node _T_100 = or(_T_99, _T_69) @[Mux.scala 27:72]
+    node _T_101 = or(_T_100, _T_70) @[Mux.scala 27:72]
+    node _T_102 = or(_T_101, _T_71) @[Mux.scala 27:72]
+    node _T_103 = or(_T_102, _T_72) @[Mux.scala 27:72]
+    node _T_104 = or(_T_103, _T_73) @[Mux.scala 27:72]
+    node _T_105 = or(_T_104, _T_74) @[Mux.scala 27:72]
+    node _T_106 = or(_T_105, _T_75) @[Mux.scala 27:72]
+    node _T_107 = or(_T_106, _T_76) @[Mux.scala 27:72]
+    node _T_108 = or(_T_107, _T_77) @[Mux.scala 27:72]
+    node _T_109 = or(_T_108, _T_78) @[Mux.scala 27:72]
+    node _T_110 = or(_T_109, _T_79) @[Mux.scala 27:72]
+    node _T_111 = or(_T_110, _T_80) @[Mux.scala 27:72]
+    node _T_112 = or(_T_111, _T_81) @[Mux.scala 27:72]
+    node _T_113 = or(_T_112, _T_82) @[Mux.scala 27:72]
+    node _T_114 = or(_T_113, _T_83) @[Mux.scala 27:72]
+    node _T_115 = or(_T_114, _T_84) @[Mux.scala 27:72]
+    node _T_116 = or(_T_115, _T_85) @[Mux.scala 27:72]
+    node _T_117 = or(_T_116, _T_86) @[Mux.scala 27:72]
+    node _T_118 = or(_T_117, _T_87) @[Mux.scala 27:72]
+    node _T_119 = or(_T_118, _T_88) @[Mux.scala 27:72]
+    node _T_120 = or(_T_119, _T_89) @[Mux.scala 27:72]
+    node _T_121 = or(_T_120, _T_90) @[Mux.scala 27:72]
+    node _T_122 = or(_T_121, _T_91) @[Mux.scala 27:72]
+    node _T_123 = or(_T_122, _T_92) @[Mux.scala 27:72]
+    node _T_124 = or(_T_123, _T_93) @[Mux.scala 27:72]
+    node _T_125 = or(_T_124, _T_94) @[Mux.scala 27:72]
+    node _T_126 = or(_T_125, _T_95) @[Mux.scala 27:72]
+    wire _T_127 : UInt<5> @[Mux.scala 27:72]
+    _T_127 <= _T_126 @[Mux.scala 27:72]
+    cls_zeros <= _T_127 @[exu_div_ctl.scala 819:13]
+    node _T_128 = bits(io.operand, 31, 0) @[exu_div_ctl.scala 821:18]
+    node _T_129 = eq(_T_128, UInt<32>("h0ffffffff")) @[exu_div_ctl.scala 821:25]
+    when _T_129 : @[exu_div_ctl.scala 821:44]
+      cls_ones <= UInt<5>("h01f") @[exu_div_ctl.scala 821:55]
+      skip @[exu_div_ctl.scala 821:44]
+    else : @[exu_div_ctl.scala 822:15]
+      node _T_130 = bits(io.operand, 31, 30) @[exu_div_ctl.scala 822:66]
+      node _T_131 = cat(UInt<1>("h01"), UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_132 = eq(_T_130, _T_131) @[exu_div_ctl.scala 822:76]
+      node _T_133 = bits(_T_132, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_134 = bits(io.operand, 31, 29) @[exu_div_ctl.scala 822:66]
+      node _T_135 = mux(UInt<1>("h01"), UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
+      node _T_136 = cat(_T_135, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_137 = eq(_T_134, _T_136) @[exu_div_ctl.scala 822:76]
+      node _T_138 = bits(_T_137, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_139 = bits(io.operand, 31, 28) @[exu_div_ctl.scala 822:66]
+      node _T_140 = mux(UInt<1>("h01"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
+      node _T_141 = cat(_T_140, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_142 = eq(_T_139, _T_141) @[exu_div_ctl.scala 822:76]
+      node _T_143 = bits(_T_142, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_144 = bits(io.operand, 31, 27) @[exu_div_ctl.scala 822:66]
+      node _T_145 = mux(UInt<1>("h01"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
+      node _T_146 = cat(_T_145, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_147 = eq(_T_144, _T_146) @[exu_div_ctl.scala 822:76]
+      node _T_148 = bits(_T_147, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_149 = bits(io.operand, 31, 26) @[exu_div_ctl.scala 822:66]
+      node _T_150 = mux(UInt<1>("h01"), UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12]
+      node _T_151 = cat(_T_150, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_152 = eq(_T_149, _T_151) @[exu_div_ctl.scala 822:76]
+      node _T_153 = bits(_T_152, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_154 = bits(io.operand, 31, 25) @[exu_div_ctl.scala 822:66]
+      node _T_155 = mux(UInt<1>("h01"), UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+      node _T_156 = cat(_T_155, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_157 = eq(_T_154, _T_156) @[exu_div_ctl.scala 822:76]
+      node _T_158 = bits(_T_157, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_159 = bits(io.operand, 31, 24) @[exu_div_ctl.scala 822:66]
+      node _T_160 = mux(UInt<1>("h01"), UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 72:12]
+      node _T_161 = cat(_T_160, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_162 = eq(_T_159, _T_161) @[exu_div_ctl.scala 822:76]
+      node _T_163 = bits(_T_162, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_164 = bits(io.operand, 31, 23) @[exu_div_ctl.scala 822:66]
+      node _T_165 = mux(UInt<1>("h01"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
+      node _T_166 = cat(_T_165, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_167 = eq(_T_164, _T_166) @[exu_div_ctl.scala 822:76]
+      node _T_168 = bits(_T_167, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_169 = bits(io.operand, 31, 22) @[exu_div_ctl.scala 822:66]
+      node _T_170 = mux(UInt<1>("h01"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 72:12]
+      node _T_171 = cat(_T_170, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_172 = eq(_T_169, _T_171) @[exu_div_ctl.scala 822:76]
+      node _T_173 = bits(_T_172, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_174 = bits(io.operand, 31, 21) @[exu_div_ctl.scala 822:66]
+      node _T_175 = mux(UInt<1>("h01"), UInt<10>("h03ff"), UInt<10>("h00")) @[Bitwise.scala 72:12]
+      node _T_176 = cat(_T_175, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_177 = eq(_T_174, _T_176) @[exu_div_ctl.scala 822:76]
+      node _T_178 = bits(_T_177, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_179 = bits(io.operand, 31, 20) @[exu_div_ctl.scala 822:66]
+      node _T_180 = mux(UInt<1>("h01"), UInt<11>("h07ff"), UInt<11>("h00")) @[Bitwise.scala 72:12]
+      node _T_181 = cat(_T_180, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_182 = eq(_T_179, _T_181) @[exu_div_ctl.scala 822:76]
+      node _T_183 = bits(_T_182, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_184 = bits(io.operand, 31, 19) @[exu_div_ctl.scala 822:66]
+      node _T_185 = mux(UInt<1>("h01"), UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12]
+      node _T_186 = cat(_T_185, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_187 = eq(_T_184, _T_186) @[exu_div_ctl.scala 822:76]
+      node _T_188 = bits(_T_187, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_189 = bits(io.operand, 31, 18) @[exu_div_ctl.scala 822:66]
+      node _T_190 = mux(UInt<1>("h01"), UInt<13>("h01fff"), UInt<13>("h00")) @[Bitwise.scala 72:12]
+      node _T_191 = cat(_T_190, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_192 = eq(_T_189, _T_191) @[exu_div_ctl.scala 822:76]
+      node _T_193 = bits(_T_192, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_194 = bits(io.operand, 31, 17) @[exu_div_ctl.scala 822:66]
+      node _T_195 = mux(UInt<1>("h01"), UInt<14>("h03fff"), UInt<14>("h00")) @[Bitwise.scala 72:12]
+      node _T_196 = cat(_T_195, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_197 = eq(_T_194, _T_196) @[exu_div_ctl.scala 822:76]
+      node _T_198 = bits(_T_197, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_199 = bits(io.operand, 31, 16) @[exu_div_ctl.scala 822:66]
+      node _T_200 = mux(UInt<1>("h01"), UInt<15>("h07fff"), UInt<15>("h00")) @[Bitwise.scala 72:12]
+      node _T_201 = cat(_T_200, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_202 = eq(_T_199, _T_201) @[exu_div_ctl.scala 822:76]
+      node _T_203 = bits(_T_202, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_204 = bits(io.operand, 31, 15) @[exu_div_ctl.scala 822:66]
+      node _T_205 = mux(UInt<1>("h01"), UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
+      node _T_206 = cat(_T_205, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_207 = eq(_T_204, _T_206) @[exu_div_ctl.scala 822:76]
+      node _T_208 = bits(_T_207, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_209 = bits(io.operand, 31, 14) @[exu_div_ctl.scala 822:66]
+      node _T_210 = mux(UInt<1>("h01"), UInt<17>("h01ffff"), UInt<17>("h00")) @[Bitwise.scala 72:12]
+      node _T_211 = cat(_T_210, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_212 = eq(_T_209, _T_211) @[exu_div_ctl.scala 822:76]
+      node _T_213 = bits(_T_212, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_214 = bits(io.operand, 31, 13) @[exu_div_ctl.scala 822:66]
+      node _T_215 = mux(UInt<1>("h01"), UInt<18>("h03ffff"), UInt<18>("h00")) @[Bitwise.scala 72:12]
+      node _T_216 = cat(_T_215, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_217 = eq(_T_214, _T_216) @[exu_div_ctl.scala 822:76]
+      node _T_218 = bits(_T_217, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_219 = bits(io.operand, 31, 12) @[exu_div_ctl.scala 822:66]
+      node _T_220 = mux(UInt<1>("h01"), UInt<19>("h07ffff"), UInt<19>("h00")) @[Bitwise.scala 72:12]
+      node _T_221 = cat(_T_220, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_222 = eq(_T_219, _T_221) @[exu_div_ctl.scala 822:76]
+      node _T_223 = bits(_T_222, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_224 = bits(io.operand, 31, 11) @[exu_div_ctl.scala 822:66]
+      node _T_225 = mux(UInt<1>("h01"), UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12]
+      node _T_226 = cat(_T_225, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_227 = eq(_T_224, _T_226) @[exu_div_ctl.scala 822:76]
+      node _T_228 = bits(_T_227, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_229 = bits(io.operand, 31, 10) @[exu_div_ctl.scala 822:66]
+      node _T_230 = mux(UInt<1>("h01"), UInt<21>("h01fffff"), UInt<21>("h00")) @[Bitwise.scala 72:12]
+      node _T_231 = cat(_T_230, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_232 = eq(_T_229, _T_231) @[exu_div_ctl.scala 822:76]
+      node _T_233 = bits(_T_232, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_234 = bits(io.operand, 31, 9) @[exu_div_ctl.scala 822:66]
+      node _T_235 = mux(UInt<1>("h01"), UInt<22>("h03fffff"), UInt<22>("h00")) @[Bitwise.scala 72:12]
+      node _T_236 = cat(_T_235, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_237 = eq(_T_234, _T_236) @[exu_div_ctl.scala 822:76]
+      node _T_238 = bits(_T_237, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_239 = bits(io.operand, 31, 8) @[exu_div_ctl.scala 822:66]
+      node _T_240 = mux(UInt<1>("h01"), UInt<23>("h07fffff"), UInt<23>("h00")) @[Bitwise.scala 72:12]
+      node _T_241 = cat(_T_240, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_242 = eq(_T_239, _T_241) @[exu_div_ctl.scala 822:76]
+      node _T_243 = bits(_T_242, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_244 = bits(io.operand, 31, 7) @[exu_div_ctl.scala 822:66]
+      node _T_245 = mux(UInt<1>("h01"), UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12]
+      node _T_246 = cat(_T_245, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_247 = eq(_T_244, _T_246) @[exu_div_ctl.scala 822:76]
+      node _T_248 = bits(_T_247, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_249 = bits(io.operand, 31, 6) @[exu_div_ctl.scala 822:66]
+      node _T_250 = mux(UInt<1>("h01"), UInt<25>("h01ffffff"), UInt<25>("h00")) @[Bitwise.scala 72:12]
+      node _T_251 = cat(_T_250, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_252 = eq(_T_249, _T_251) @[exu_div_ctl.scala 822:76]
+      node _T_253 = bits(_T_252, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_254 = bits(io.operand, 31, 5) @[exu_div_ctl.scala 822:66]
+      node _T_255 = mux(UInt<1>("h01"), UInt<26>("h03ffffff"), UInt<26>("h00")) @[Bitwise.scala 72:12]
+      node _T_256 = cat(_T_255, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_257 = eq(_T_254, _T_256) @[exu_div_ctl.scala 822:76]
+      node _T_258 = bits(_T_257, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_259 = bits(io.operand, 31, 4) @[exu_div_ctl.scala 822:66]
+      node _T_260 = mux(UInt<1>("h01"), UInt<27>("h07ffffff"), UInt<27>("h00")) @[Bitwise.scala 72:12]
+      node _T_261 = cat(_T_260, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_262 = eq(_T_259, _T_261) @[exu_div_ctl.scala 822:76]
+      node _T_263 = bits(_T_262, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_264 = bits(io.operand, 31, 3) @[exu_div_ctl.scala 822:66]
+      node _T_265 = mux(UInt<1>("h01"), UInt<28>("h0fffffff"), UInt<28>("h00")) @[Bitwise.scala 72:12]
+      node _T_266 = cat(_T_265, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_267 = eq(_T_264, _T_266) @[exu_div_ctl.scala 822:76]
+      node _T_268 = bits(_T_267, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_269 = bits(io.operand, 31, 2) @[exu_div_ctl.scala 822:66]
+      node _T_270 = mux(UInt<1>("h01"), UInt<29>("h01fffffff"), UInt<29>("h00")) @[Bitwise.scala 72:12]
+      node _T_271 = cat(_T_270, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_272 = eq(_T_269, _T_271) @[exu_div_ctl.scala 822:76]
+      node _T_273 = bits(_T_272, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_274 = bits(io.operand, 31, 1) @[exu_div_ctl.scala 822:66]
+      node _T_275 = mux(UInt<1>("h01"), UInt<30>("h03fffffff"), UInt<30>("h00")) @[Bitwise.scala 72:12]
+      node _T_276 = cat(_T_275, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_277 = eq(_T_274, _T_276) @[exu_div_ctl.scala 822:76]
+      node _T_278 = bits(_T_277, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_279 = bits(io.operand, 31, 0) @[exu_div_ctl.scala 822:66]
+      node _T_280 = mux(UInt<1>("h01"), UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12]
+      node _T_281 = cat(_T_280, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_282 = eq(_T_279, _T_281) @[exu_div_ctl.scala 822:76]
+      node _T_283 = bits(_T_282, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_284 = mux(_T_133, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_285 = mux(_T_138, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_286 = mux(_T_143, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_287 = mux(_T_148, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_288 = mux(_T_153, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_289 = mux(_T_158, UInt<3>("h05"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_290 = mux(_T_163, UInt<3>("h06"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_291 = mux(_T_168, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_292 = mux(_T_173, UInt<4>("h08"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_293 = mux(_T_178, UInt<4>("h09"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_294 = mux(_T_183, UInt<4>("h0a"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_295 = mux(_T_188, UInt<4>("h0b"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_296 = mux(_T_193, UInt<4>("h0c"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_297 = mux(_T_198, UInt<4>("h0d"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_298 = mux(_T_203, UInt<4>("h0e"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_299 = mux(_T_208, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_300 = mux(_T_213, UInt<5>("h010"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_301 = mux(_T_218, UInt<5>("h011"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_302 = mux(_T_223, UInt<5>("h012"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_303 = mux(_T_228, UInt<5>("h013"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_304 = mux(_T_233, UInt<5>("h014"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_305 = mux(_T_238, UInt<5>("h015"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_306 = mux(_T_243, UInt<5>("h016"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_307 = mux(_T_248, UInt<5>("h017"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_308 = mux(_T_253, UInt<5>("h018"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_309 = mux(_T_258, UInt<5>("h019"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_310 = mux(_T_263, UInt<5>("h01a"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_311 = mux(_T_268, UInt<5>("h01b"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_312 = mux(_T_273, UInt<5>("h01c"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_313 = mux(_T_278, UInt<5>("h01d"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_314 = mux(_T_283, UInt<5>("h01e"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_315 = or(_T_284, _T_285) @[Mux.scala 27:72]
+      node _T_316 = or(_T_315, _T_286) @[Mux.scala 27:72]
+      node _T_317 = or(_T_316, _T_287) @[Mux.scala 27:72]
+      node _T_318 = or(_T_317, _T_288) @[Mux.scala 27:72]
+      node _T_319 = or(_T_318, _T_289) @[Mux.scala 27:72]
+      node _T_320 = or(_T_319, _T_290) @[Mux.scala 27:72]
+      node _T_321 = or(_T_320, _T_291) @[Mux.scala 27:72]
+      node _T_322 = or(_T_321, _T_292) @[Mux.scala 27:72]
+      node _T_323 = or(_T_322, _T_293) @[Mux.scala 27:72]
+      node _T_324 = or(_T_323, _T_294) @[Mux.scala 27:72]
+      node _T_325 = or(_T_324, _T_295) @[Mux.scala 27:72]
+      node _T_326 = or(_T_325, _T_296) @[Mux.scala 27:72]
+      node _T_327 = or(_T_326, _T_297) @[Mux.scala 27:72]
+      node _T_328 = or(_T_327, _T_298) @[Mux.scala 27:72]
+      node _T_329 = or(_T_328, _T_299) @[Mux.scala 27:72]
+      node _T_330 = or(_T_329, _T_300) @[Mux.scala 27:72]
+      node _T_331 = or(_T_330, _T_301) @[Mux.scala 27:72]
+      node _T_332 = or(_T_331, _T_302) @[Mux.scala 27:72]
+      node _T_333 = or(_T_332, _T_303) @[Mux.scala 27:72]
+      node _T_334 = or(_T_333, _T_304) @[Mux.scala 27:72]
+      node _T_335 = or(_T_334, _T_305) @[Mux.scala 27:72]
+      node _T_336 = or(_T_335, _T_306) @[Mux.scala 27:72]
+      node _T_337 = or(_T_336, _T_307) @[Mux.scala 27:72]
+      node _T_338 = or(_T_337, _T_308) @[Mux.scala 27:72]
+      node _T_339 = or(_T_338, _T_309) @[Mux.scala 27:72]
+      node _T_340 = or(_T_339, _T_310) @[Mux.scala 27:72]
+      node _T_341 = or(_T_340, _T_311) @[Mux.scala 27:72]
+      node _T_342 = or(_T_341, _T_312) @[Mux.scala 27:72]
+      node _T_343 = or(_T_342, _T_313) @[Mux.scala 27:72]
+      node _T_344 = or(_T_343, _T_314) @[Mux.scala 27:72]
+      wire _T_345 : UInt<5> @[Mux.scala 27:72]
+      _T_345 <= _T_344 @[Mux.scala 27:72]
+      cls_ones <= _T_345 @[exu_div_ctl.scala 822:25]
+      skip @[exu_div_ctl.scala 822:15]
+    node _T_346 = bits(io.operand, 32, 32) @[exu_div_ctl.scala 823:27]
+    node _T_347 = mux(_T_346, cls_ones, cls_zeros) @[exu_div_ctl.scala 823:16]
+    io.cls <= _T_347 @[exu_div_ctl.scala 823:10]
+    
+  module exu_div_cls_1 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {flip operand : UInt<33>, cls : UInt<5>}
+    
+    wire cls_zeros : UInt<5>
+    cls_zeros <= UInt<5>("h00")
+    wire cls_ones : UInt<5>
+    cls_ones <= UInt<5>("h00")
+    node _T = bits(io.operand, 31, 31) @[exu_div_ctl.scala 819:54]
+    node _T_1 = eq(_T, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_2 = bits(io.operand, 31, 30) @[exu_div_ctl.scala 819:54]
+    node _T_3 = eq(_T_2, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_4 = bits(io.operand, 31, 29) @[exu_div_ctl.scala 819:54]
+    node _T_5 = eq(_T_4, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_6 = bits(io.operand, 31, 28) @[exu_div_ctl.scala 819:54]
+    node _T_7 = eq(_T_6, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_8 = bits(io.operand, 31, 27) @[exu_div_ctl.scala 819:54]
+    node _T_9 = eq(_T_8, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_10 = bits(io.operand, 31, 26) @[exu_div_ctl.scala 819:54]
+    node _T_11 = eq(_T_10, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_12 = bits(io.operand, 31, 25) @[exu_div_ctl.scala 819:54]
+    node _T_13 = eq(_T_12, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_14 = bits(io.operand, 31, 24) @[exu_div_ctl.scala 819:54]
+    node _T_15 = eq(_T_14, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_16 = bits(io.operand, 31, 23) @[exu_div_ctl.scala 819:54]
+    node _T_17 = eq(_T_16, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_18 = bits(io.operand, 31, 22) @[exu_div_ctl.scala 819:54]
+    node _T_19 = eq(_T_18, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_20 = bits(io.operand, 31, 21) @[exu_div_ctl.scala 819:54]
+    node _T_21 = eq(_T_20, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_22 = bits(io.operand, 31, 20) @[exu_div_ctl.scala 819:54]
+    node _T_23 = eq(_T_22, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_24 = bits(io.operand, 31, 19) @[exu_div_ctl.scala 819:54]
+    node _T_25 = eq(_T_24, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_26 = bits(io.operand, 31, 18) @[exu_div_ctl.scala 819:54]
+    node _T_27 = eq(_T_26, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_28 = bits(io.operand, 31, 17) @[exu_div_ctl.scala 819:54]
+    node _T_29 = eq(_T_28, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_30 = bits(io.operand, 31, 16) @[exu_div_ctl.scala 819:54]
+    node _T_31 = eq(_T_30, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_32 = bits(io.operand, 31, 15) @[exu_div_ctl.scala 819:54]
+    node _T_33 = eq(_T_32, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_34 = bits(io.operand, 31, 14) @[exu_div_ctl.scala 819:54]
+    node _T_35 = eq(_T_34, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_36 = bits(io.operand, 31, 13) @[exu_div_ctl.scala 819:54]
+    node _T_37 = eq(_T_36, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_38 = bits(io.operand, 31, 12) @[exu_div_ctl.scala 819:54]
+    node _T_39 = eq(_T_38, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_40 = bits(io.operand, 31, 11) @[exu_div_ctl.scala 819:54]
+    node _T_41 = eq(_T_40, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_42 = bits(io.operand, 31, 10) @[exu_div_ctl.scala 819:54]
+    node _T_43 = eq(_T_42, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_44 = bits(io.operand, 31, 9) @[exu_div_ctl.scala 819:54]
+    node _T_45 = eq(_T_44, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_46 = bits(io.operand, 31, 8) @[exu_div_ctl.scala 819:54]
+    node _T_47 = eq(_T_46, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_48 = bits(io.operand, 31, 7) @[exu_div_ctl.scala 819:54]
+    node _T_49 = eq(_T_48, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_50 = bits(io.operand, 31, 6) @[exu_div_ctl.scala 819:54]
+    node _T_51 = eq(_T_50, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_52 = bits(io.operand, 31, 5) @[exu_div_ctl.scala 819:54]
+    node _T_53 = eq(_T_52, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_54 = bits(io.operand, 31, 4) @[exu_div_ctl.scala 819:54]
+    node _T_55 = eq(_T_54, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_56 = bits(io.operand, 31, 3) @[exu_div_ctl.scala 819:54]
+    node _T_57 = eq(_T_56, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_58 = bits(io.operand, 31, 2) @[exu_div_ctl.scala 819:54]
+    node _T_59 = eq(_T_58, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_60 = bits(io.operand, 31, 1) @[exu_div_ctl.scala 819:54]
+    node _T_61 = eq(_T_60, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_62 = bits(io.operand, 31, 0) @[exu_div_ctl.scala 819:54]
+    node _T_63 = eq(_T_62, UInt<1>("h01")) @[exu_div_ctl.scala 819:63]
+    node _T_64 = mux(_T_1, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_65 = mux(_T_3, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_66 = mux(_T_5, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_67 = mux(_T_7, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_68 = mux(_T_9, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_69 = mux(_T_11, UInt<3>("h05"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_70 = mux(_T_13, UInt<3>("h06"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_71 = mux(_T_15, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_72 = mux(_T_17, UInt<4>("h08"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_73 = mux(_T_19, UInt<4>("h09"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_74 = mux(_T_21, UInt<4>("h0a"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_75 = mux(_T_23, UInt<4>("h0b"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_76 = mux(_T_25, UInt<4>("h0c"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_77 = mux(_T_27, UInt<4>("h0d"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_78 = mux(_T_29, UInt<4>("h0e"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_79 = mux(_T_31, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_80 = mux(_T_33, UInt<5>("h010"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_81 = mux(_T_35, UInt<5>("h011"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_82 = mux(_T_37, UInt<5>("h012"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_83 = mux(_T_39, UInt<5>("h013"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_84 = mux(_T_41, UInt<5>("h014"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_85 = mux(_T_43, UInt<5>("h015"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_86 = mux(_T_45, UInt<5>("h016"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_87 = mux(_T_47, UInt<5>("h017"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_88 = mux(_T_49, UInt<5>("h018"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_89 = mux(_T_51, UInt<5>("h019"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_90 = mux(_T_53, UInt<5>("h01a"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_91 = mux(_T_55, UInt<5>("h01b"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_92 = mux(_T_57, UInt<5>("h01c"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_93 = mux(_T_59, UInt<5>("h01d"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_94 = mux(_T_61, UInt<5>("h01e"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_95 = mux(_T_63, UInt<5>("h01f"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_96 = or(_T_64, _T_65) @[Mux.scala 27:72]
+    node _T_97 = or(_T_96, _T_66) @[Mux.scala 27:72]
+    node _T_98 = or(_T_97, _T_67) @[Mux.scala 27:72]
+    node _T_99 = or(_T_98, _T_68) @[Mux.scala 27:72]
+    node _T_100 = or(_T_99, _T_69) @[Mux.scala 27:72]
+    node _T_101 = or(_T_100, _T_70) @[Mux.scala 27:72]
+    node _T_102 = or(_T_101, _T_71) @[Mux.scala 27:72]
+    node _T_103 = or(_T_102, _T_72) @[Mux.scala 27:72]
+    node _T_104 = or(_T_103, _T_73) @[Mux.scala 27:72]
+    node _T_105 = or(_T_104, _T_74) @[Mux.scala 27:72]
+    node _T_106 = or(_T_105, _T_75) @[Mux.scala 27:72]
+    node _T_107 = or(_T_106, _T_76) @[Mux.scala 27:72]
+    node _T_108 = or(_T_107, _T_77) @[Mux.scala 27:72]
+    node _T_109 = or(_T_108, _T_78) @[Mux.scala 27:72]
+    node _T_110 = or(_T_109, _T_79) @[Mux.scala 27:72]
+    node _T_111 = or(_T_110, _T_80) @[Mux.scala 27:72]
+    node _T_112 = or(_T_111, _T_81) @[Mux.scala 27:72]
+    node _T_113 = or(_T_112, _T_82) @[Mux.scala 27:72]
+    node _T_114 = or(_T_113, _T_83) @[Mux.scala 27:72]
+    node _T_115 = or(_T_114, _T_84) @[Mux.scala 27:72]
+    node _T_116 = or(_T_115, _T_85) @[Mux.scala 27:72]
+    node _T_117 = or(_T_116, _T_86) @[Mux.scala 27:72]
+    node _T_118 = or(_T_117, _T_87) @[Mux.scala 27:72]
+    node _T_119 = or(_T_118, _T_88) @[Mux.scala 27:72]
+    node _T_120 = or(_T_119, _T_89) @[Mux.scala 27:72]
+    node _T_121 = or(_T_120, _T_90) @[Mux.scala 27:72]
+    node _T_122 = or(_T_121, _T_91) @[Mux.scala 27:72]
+    node _T_123 = or(_T_122, _T_92) @[Mux.scala 27:72]
+    node _T_124 = or(_T_123, _T_93) @[Mux.scala 27:72]
+    node _T_125 = or(_T_124, _T_94) @[Mux.scala 27:72]
+    node _T_126 = or(_T_125, _T_95) @[Mux.scala 27:72]
+    wire _T_127 : UInt<5> @[Mux.scala 27:72]
+    _T_127 <= _T_126 @[Mux.scala 27:72]
+    cls_zeros <= _T_127 @[exu_div_ctl.scala 819:13]
+    node _T_128 = bits(io.operand, 31, 0) @[exu_div_ctl.scala 821:18]
+    node _T_129 = eq(_T_128, UInt<32>("h0ffffffff")) @[exu_div_ctl.scala 821:25]
+    when _T_129 : @[exu_div_ctl.scala 821:44]
+      cls_ones <= UInt<5>("h01f") @[exu_div_ctl.scala 821:55]
+      skip @[exu_div_ctl.scala 821:44]
+    else : @[exu_div_ctl.scala 822:15]
+      node _T_130 = bits(io.operand, 31, 30) @[exu_div_ctl.scala 822:66]
+      node _T_131 = cat(UInt<1>("h01"), UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_132 = eq(_T_130, _T_131) @[exu_div_ctl.scala 822:76]
+      node _T_133 = bits(_T_132, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_134 = bits(io.operand, 31, 29) @[exu_div_ctl.scala 822:66]
+      node _T_135 = mux(UInt<1>("h01"), UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
+      node _T_136 = cat(_T_135, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_137 = eq(_T_134, _T_136) @[exu_div_ctl.scala 822:76]
+      node _T_138 = bits(_T_137, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_139 = bits(io.operand, 31, 28) @[exu_div_ctl.scala 822:66]
+      node _T_140 = mux(UInt<1>("h01"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
+      node _T_141 = cat(_T_140, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_142 = eq(_T_139, _T_141) @[exu_div_ctl.scala 822:76]
+      node _T_143 = bits(_T_142, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_144 = bits(io.operand, 31, 27) @[exu_div_ctl.scala 822:66]
+      node _T_145 = mux(UInt<1>("h01"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
+      node _T_146 = cat(_T_145, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_147 = eq(_T_144, _T_146) @[exu_div_ctl.scala 822:76]
+      node _T_148 = bits(_T_147, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_149 = bits(io.operand, 31, 26) @[exu_div_ctl.scala 822:66]
+      node _T_150 = mux(UInt<1>("h01"), UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12]
+      node _T_151 = cat(_T_150, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_152 = eq(_T_149, _T_151) @[exu_div_ctl.scala 822:76]
+      node _T_153 = bits(_T_152, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_154 = bits(io.operand, 31, 25) @[exu_div_ctl.scala 822:66]
+      node _T_155 = mux(UInt<1>("h01"), UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+      node _T_156 = cat(_T_155, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_157 = eq(_T_154, _T_156) @[exu_div_ctl.scala 822:76]
+      node _T_158 = bits(_T_157, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_159 = bits(io.operand, 31, 24) @[exu_div_ctl.scala 822:66]
+      node _T_160 = mux(UInt<1>("h01"), UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 72:12]
+      node _T_161 = cat(_T_160, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_162 = eq(_T_159, _T_161) @[exu_div_ctl.scala 822:76]
+      node _T_163 = bits(_T_162, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_164 = bits(io.operand, 31, 23) @[exu_div_ctl.scala 822:66]
+      node _T_165 = mux(UInt<1>("h01"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
+      node _T_166 = cat(_T_165, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_167 = eq(_T_164, _T_166) @[exu_div_ctl.scala 822:76]
+      node _T_168 = bits(_T_167, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_169 = bits(io.operand, 31, 22) @[exu_div_ctl.scala 822:66]
+      node _T_170 = mux(UInt<1>("h01"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 72:12]
+      node _T_171 = cat(_T_170, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_172 = eq(_T_169, _T_171) @[exu_div_ctl.scala 822:76]
+      node _T_173 = bits(_T_172, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_174 = bits(io.operand, 31, 21) @[exu_div_ctl.scala 822:66]
+      node _T_175 = mux(UInt<1>("h01"), UInt<10>("h03ff"), UInt<10>("h00")) @[Bitwise.scala 72:12]
+      node _T_176 = cat(_T_175, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_177 = eq(_T_174, _T_176) @[exu_div_ctl.scala 822:76]
+      node _T_178 = bits(_T_177, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_179 = bits(io.operand, 31, 20) @[exu_div_ctl.scala 822:66]
+      node _T_180 = mux(UInt<1>("h01"), UInt<11>("h07ff"), UInt<11>("h00")) @[Bitwise.scala 72:12]
+      node _T_181 = cat(_T_180, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_182 = eq(_T_179, _T_181) @[exu_div_ctl.scala 822:76]
+      node _T_183 = bits(_T_182, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_184 = bits(io.operand, 31, 19) @[exu_div_ctl.scala 822:66]
+      node _T_185 = mux(UInt<1>("h01"), UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12]
+      node _T_186 = cat(_T_185, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_187 = eq(_T_184, _T_186) @[exu_div_ctl.scala 822:76]
+      node _T_188 = bits(_T_187, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_189 = bits(io.operand, 31, 18) @[exu_div_ctl.scala 822:66]
+      node _T_190 = mux(UInt<1>("h01"), UInt<13>("h01fff"), UInt<13>("h00")) @[Bitwise.scala 72:12]
+      node _T_191 = cat(_T_190, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_192 = eq(_T_189, _T_191) @[exu_div_ctl.scala 822:76]
+      node _T_193 = bits(_T_192, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_194 = bits(io.operand, 31, 17) @[exu_div_ctl.scala 822:66]
+      node _T_195 = mux(UInt<1>("h01"), UInt<14>("h03fff"), UInt<14>("h00")) @[Bitwise.scala 72:12]
+      node _T_196 = cat(_T_195, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_197 = eq(_T_194, _T_196) @[exu_div_ctl.scala 822:76]
+      node _T_198 = bits(_T_197, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_199 = bits(io.operand, 31, 16) @[exu_div_ctl.scala 822:66]
+      node _T_200 = mux(UInt<1>("h01"), UInt<15>("h07fff"), UInt<15>("h00")) @[Bitwise.scala 72:12]
+      node _T_201 = cat(_T_200, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_202 = eq(_T_199, _T_201) @[exu_div_ctl.scala 822:76]
+      node _T_203 = bits(_T_202, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_204 = bits(io.operand, 31, 15) @[exu_div_ctl.scala 822:66]
+      node _T_205 = mux(UInt<1>("h01"), UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
+      node _T_206 = cat(_T_205, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_207 = eq(_T_204, _T_206) @[exu_div_ctl.scala 822:76]
+      node _T_208 = bits(_T_207, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_209 = bits(io.operand, 31, 14) @[exu_div_ctl.scala 822:66]
+      node _T_210 = mux(UInt<1>("h01"), UInt<17>("h01ffff"), UInt<17>("h00")) @[Bitwise.scala 72:12]
+      node _T_211 = cat(_T_210, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_212 = eq(_T_209, _T_211) @[exu_div_ctl.scala 822:76]
+      node _T_213 = bits(_T_212, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_214 = bits(io.operand, 31, 13) @[exu_div_ctl.scala 822:66]
+      node _T_215 = mux(UInt<1>("h01"), UInt<18>("h03ffff"), UInt<18>("h00")) @[Bitwise.scala 72:12]
+      node _T_216 = cat(_T_215, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_217 = eq(_T_214, _T_216) @[exu_div_ctl.scala 822:76]
+      node _T_218 = bits(_T_217, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_219 = bits(io.operand, 31, 12) @[exu_div_ctl.scala 822:66]
+      node _T_220 = mux(UInt<1>("h01"), UInt<19>("h07ffff"), UInt<19>("h00")) @[Bitwise.scala 72:12]
+      node _T_221 = cat(_T_220, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_222 = eq(_T_219, _T_221) @[exu_div_ctl.scala 822:76]
+      node _T_223 = bits(_T_222, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_224 = bits(io.operand, 31, 11) @[exu_div_ctl.scala 822:66]
+      node _T_225 = mux(UInt<1>("h01"), UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12]
+      node _T_226 = cat(_T_225, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_227 = eq(_T_224, _T_226) @[exu_div_ctl.scala 822:76]
+      node _T_228 = bits(_T_227, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_229 = bits(io.operand, 31, 10) @[exu_div_ctl.scala 822:66]
+      node _T_230 = mux(UInt<1>("h01"), UInt<21>("h01fffff"), UInt<21>("h00")) @[Bitwise.scala 72:12]
+      node _T_231 = cat(_T_230, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_232 = eq(_T_229, _T_231) @[exu_div_ctl.scala 822:76]
+      node _T_233 = bits(_T_232, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_234 = bits(io.operand, 31, 9) @[exu_div_ctl.scala 822:66]
+      node _T_235 = mux(UInt<1>("h01"), UInt<22>("h03fffff"), UInt<22>("h00")) @[Bitwise.scala 72:12]
+      node _T_236 = cat(_T_235, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_237 = eq(_T_234, _T_236) @[exu_div_ctl.scala 822:76]
+      node _T_238 = bits(_T_237, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_239 = bits(io.operand, 31, 8) @[exu_div_ctl.scala 822:66]
+      node _T_240 = mux(UInt<1>("h01"), UInt<23>("h07fffff"), UInt<23>("h00")) @[Bitwise.scala 72:12]
+      node _T_241 = cat(_T_240, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_242 = eq(_T_239, _T_241) @[exu_div_ctl.scala 822:76]
+      node _T_243 = bits(_T_242, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_244 = bits(io.operand, 31, 7) @[exu_div_ctl.scala 822:66]
+      node _T_245 = mux(UInt<1>("h01"), UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12]
+      node _T_246 = cat(_T_245, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_247 = eq(_T_244, _T_246) @[exu_div_ctl.scala 822:76]
+      node _T_248 = bits(_T_247, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_249 = bits(io.operand, 31, 6) @[exu_div_ctl.scala 822:66]
+      node _T_250 = mux(UInt<1>("h01"), UInt<25>("h01ffffff"), UInt<25>("h00")) @[Bitwise.scala 72:12]
+      node _T_251 = cat(_T_250, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_252 = eq(_T_249, _T_251) @[exu_div_ctl.scala 822:76]
+      node _T_253 = bits(_T_252, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_254 = bits(io.operand, 31, 5) @[exu_div_ctl.scala 822:66]
+      node _T_255 = mux(UInt<1>("h01"), UInt<26>("h03ffffff"), UInt<26>("h00")) @[Bitwise.scala 72:12]
+      node _T_256 = cat(_T_255, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_257 = eq(_T_254, _T_256) @[exu_div_ctl.scala 822:76]
+      node _T_258 = bits(_T_257, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_259 = bits(io.operand, 31, 4) @[exu_div_ctl.scala 822:66]
+      node _T_260 = mux(UInt<1>("h01"), UInt<27>("h07ffffff"), UInt<27>("h00")) @[Bitwise.scala 72:12]
+      node _T_261 = cat(_T_260, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_262 = eq(_T_259, _T_261) @[exu_div_ctl.scala 822:76]
+      node _T_263 = bits(_T_262, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_264 = bits(io.operand, 31, 3) @[exu_div_ctl.scala 822:66]
+      node _T_265 = mux(UInt<1>("h01"), UInt<28>("h0fffffff"), UInt<28>("h00")) @[Bitwise.scala 72:12]
+      node _T_266 = cat(_T_265, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_267 = eq(_T_264, _T_266) @[exu_div_ctl.scala 822:76]
+      node _T_268 = bits(_T_267, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_269 = bits(io.operand, 31, 2) @[exu_div_ctl.scala 822:66]
+      node _T_270 = mux(UInt<1>("h01"), UInt<29>("h01fffffff"), UInt<29>("h00")) @[Bitwise.scala 72:12]
+      node _T_271 = cat(_T_270, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_272 = eq(_T_269, _T_271) @[exu_div_ctl.scala 822:76]
+      node _T_273 = bits(_T_272, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_274 = bits(io.operand, 31, 1) @[exu_div_ctl.scala 822:66]
+      node _T_275 = mux(UInt<1>("h01"), UInt<30>("h03fffffff"), UInt<30>("h00")) @[Bitwise.scala 72:12]
+      node _T_276 = cat(_T_275, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_277 = eq(_T_274, _T_276) @[exu_div_ctl.scala 822:76]
+      node _T_278 = bits(_T_277, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_279 = bits(io.operand, 31, 0) @[exu_div_ctl.scala 822:66]
+      node _T_280 = mux(UInt<1>("h01"), UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12]
+      node _T_281 = cat(_T_280, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_282 = eq(_T_279, _T_281) @[exu_div_ctl.scala 822:76]
+      node _T_283 = bits(_T_282, 0, 0) @[exu_div_ctl.scala 822:102]
+      node _T_284 = mux(_T_133, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_285 = mux(_T_138, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_286 = mux(_T_143, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_287 = mux(_T_148, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_288 = mux(_T_153, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_289 = mux(_T_158, UInt<3>("h05"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_290 = mux(_T_163, UInt<3>("h06"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_291 = mux(_T_168, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_292 = mux(_T_173, UInt<4>("h08"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_293 = mux(_T_178, UInt<4>("h09"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_294 = mux(_T_183, UInt<4>("h0a"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_295 = mux(_T_188, UInt<4>("h0b"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_296 = mux(_T_193, UInt<4>("h0c"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_297 = mux(_T_198, UInt<4>("h0d"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_298 = mux(_T_203, UInt<4>("h0e"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_299 = mux(_T_208, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_300 = mux(_T_213, UInt<5>("h010"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_301 = mux(_T_218, UInt<5>("h011"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_302 = mux(_T_223, UInt<5>("h012"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_303 = mux(_T_228, UInt<5>("h013"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_304 = mux(_T_233, UInt<5>("h014"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_305 = mux(_T_238, UInt<5>("h015"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_306 = mux(_T_243, UInt<5>("h016"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_307 = mux(_T_248, UInt<5>("h017"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_308 = mux(_T_253, UInt<5>("h018"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_309 = mux(_T_258, UInt<5>("h019"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_310 = mux(_T_263, UInt<5>("h01a"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_311 = mux(_T_268, UInt<5>("h01b"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_312 = mux(_T_273, UInt<5>("h01c"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_313 = mux(_T_278, UInt<5>("h01d"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_314 = mux(_T_283, UInt<5>("h01e"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_315 = or(_T_284, _T_285) @[Mux.scala 27:72]
+      node _T_316 = or(_T_315, _T_286) @[Mux.scala 27:72]
+      node _T_317 = or(_T_316, _T_287) @[Mux.scala 27:72]
+      node _T_318 = or(_T_317, _T_288) @[Mux.scala 27:72]
+      node _T_319 = or(_T_318, _T_289) @[Mux.scala 27:72]
+      node _T_320 = or(_T_319, _T_290) @[Mux.scala 27:72]
+      node _T_321 = or(_T_320, _T_291) @[Mux.scala 27:72]
+      node _T_322 = or(_T_321, _T_292) @[Mux.scala 27:72]
+      node _T_323 = or(_T_322, _T_293) @[Mux.scala 27:72]
+      node _T_324 = or(_T_323, _T_294) @[Mux.scala 27:72]
+      node _T_325 = or(_T_324, _T_295) @[Mux.scala 27:72]
+      node _T_326 = or(_T_325, _T_296) @[Mux.scala 27:72]
+      node _T_327 = or(_T_326, _T_297) @[Mux.scala 27:72]
+      node _T_328 = or(_T_327, _T_298) @[Mux.scala 27:72]
+      node _T_329 = or(_T_328, _T_299) @[Mux.scala 27:72]
+      node _T_330 = or(_T_329, _T_300) @[Mux.scala 27:72]
+      node _T_331 = or(_T_330, _T_301) @[Mux.scala 27:72]
+      node _T_332 = or(_T_331, _T_302) @[Mux.scala 27:72]
+      node _T_333 = or(_T_332, _T_303) @[Mux.scala 27:72]
+      node _T_334 = or(_T_333, _T_304) @[Mux.scala 27:72]
+      node _T_335 = or(_T_334, _T_305) @[Mux.scala 27:72]
+      node _T_336 = or(_T_335, _T_306) @[Mux.scala 27:72]
+      node _T_337 = or(_T_336, _T_307) @[Mux.scala 27:72]
+      node _T_338 = or(_T_337, _T_308) @[Mux.scala 27:72]
+      node _T_339 = or(_T_338, _T_309) @[Mux.scala 27:72]
+      node _T_340 = or(_T_339, _T_310) @[Mux.scala 27:72]
+      node _T_341 = or(_T_340, _T_311) @[Mux.scala 27:72]
+      node _T_342 = or(_T_341, _T_312) @[Mux.scala 27:72]
+      node _T_343 = or(_T_342, _T_313) @[Mux.scala 27:72]
+      node _T_344 = or(_T_343, _T_314) @[Mux.scala 27:72]
+      wire _T_345 : UInt<5> @[Mux.scala 27:72]
+      _T_345 <= _T_344 @[Mux.scala 27:72]
+      cls_ones <= _T_345 @[exu_div_ctl.scala 822:25]
+      skip @[exu_div_ctl.scala 822:15]
+    node _T_346 = bits(io.operand, 32, 32) @[exu_div_ctl.scala 823:27]
+    node _T_347 = mux(_T_346, cls_ones, cls_zeros) @[exu_div_ctl.scala 823:16]
+    io.cls <= _T_347 @[exu_div_ctl.scala 823:10]
+    
+  extmodule gated_latch : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  extmodule gated_latch_1 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_1 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_1 @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  extmodule gated_latch_2 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_2 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_2 @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  extmodule gated_latch_3 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_3 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_3 @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  extmodule gated_latch_4 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_4 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_4 @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  extmodule gated_latch_5 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_5 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_5 @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  extmodule gated_latch_6 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_6 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_6 @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  extmodule gated_latch_7 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_7 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_7 @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  extmodule gated_latch_8 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_8 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_8 @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  extmodule gated_latch_9 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_9 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_9 @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  extmodule gated_latch_10 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_10 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_10 @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  module exu_div_new_3bit_fullshortq : 
+    input clock : Clock
+    input reset : AsyncReset
+    output io : {flip scan_mode : UInt<1>, flip cancel : UInt<1>, flip valid_in : UInt<1>, flip signed_in : UInt<1>, flip rem_in : UInt<1>, flip dividend_in : UInt<32>, flip divisor_in : UInt<32>, data_out : UInt<32>, valid_out : UInt<1>}
+    
+    wire valid_ff : UInt<1>
+    valid_ff <= UInt<1>("h00")
+    wire finish_ff : UInt<1>
+    finish_ff <= UInt<1>("h00")
+    wire control_ff : UInt<3>
+    control_ff <= UInt<3>("h00")
+    wire count_ff : UInt<7>
+    count_ff <= UInt<7>("h00")
+    wire smallnum : UInt<4>
+    smallnum <= UInt<4>("h00")
+    wire a_ff : UInt<33>
+    a_ff <= UInt<33>("h00")
+    wire b_ff1 : UInt<33>
+    b_ff1 <= UInt<33>("h00")
+    wire b_ff : UInt<37>
+    b_ff <= UInt<37>("h00")
+    wire q_ff : UInt<32>
+    q_ff <= UInt<32>("h00")
+    wire r_ff : UInt<33>
+    r_ff <= UInt<33>("h00")
+    wire quotient_raw : UInt<8>
+    quotient_raw <= UInt<8>("h00")
+    wire quotient_new : UInt<3>
+    quotient_new <= UInt<3>("h00")
+    wire shortq_enable : UInt<1>
+    shortq_enable <= UInt<1>("h00")
+    wire shortq_enable_ff : UInt<1>
+    shortq_enable_ff <= UInt<1>("h00")
+    wire by_zero_case_ff : UInt<1>
+    by_zero_case_ff <= UInt<1>("h00")
+    wire ar_shifted : UInt<66>
+    ar_shifted <= UInt<66>("h00")
+    wire shortq_decode : UInt<5>
+    shortq_decode <= UInt<5>("h00")
+    wire shortq_shift_ff : UInt<5>
+    shortq_shift_ff <= UInt<5>("h00")
+    node _T = eq(io.cancel, UInt<1>("h00")) @[exu_div_ctl.scala 649:35]
+    node valid_ff_in = and(io.valid_in, _T) @[exu_div_ctl.scala 649:33]
+    node _T_1 = eq(io.valid_in, UInt<1>("h00")) @[exu_div_ctl.scala 650:35]
+    node _T_2 = bits(control_ff, 2, 2) @[exu_div_ctl.scala 650:60]
+    node _T_3 = and(_T_1, _T_2) @[exu_div_ctl.scala 650:48]
+    node _T_4 = and(io.valid_in, io.signed_in) @[exu_div_ctl.scala 650:80]
+    node _T_5 = bits(io.dividend_in, 31, 31) @[exu_div_ctl.scala 650:112]
+    node _T_6 = and(_T_4, _T_5) @[exu_div_ctl.scala 650:96]
+    node _T_7 = or(_T_3, _T_6) @[exu_div_ctl.scala 650:65]
+    node _T_8 = eq(io.valid_in, UInt<1>("h00")) @[exu_div_ctl.scala 650:120]
+    node _T_9 = bits(control_ff, 1, 1) @[exu_div_ctl.scala 650:145]
+    node _T_10 = and(_T_8, _T_9) @[exu_div_ctl.scala 650:133]
+    node _T_11 = and(io.valid_in, io.signed_in) @[exu_div_ctl.scala 650:165]
+    node _T_12 = bits(io.divisor_in, 31, 31) @[exu_div_ctl.scala 650:197]
+    node _T_13 = and(_T_11, _T_12) @[exu_div_ctl.scala 650:181]
+    node _T_14 = or(_T_10, _T_13) @[exu_div_ctl.scala 650:150]
+    node _T_15 = eq(io.valid_in, UInt<1>("h00")) @[exu_div_ctl.scala 650:205]
+    node _T_16 = bits(control_ff, 0, 0) @[exu_div_ctl.scala 650:230]
+    node _T_17 = and(_T_15, _T_16) @[exu_div_ctl.scala 650:218]
+    node _T_18 = and(io.valid_in, io.rem_in) @[exu_div_ctl.scala 650:250]
+    node _T_19 = or(_T_17, _T_18) @[exu_div_ctl.scala 650:235]
+    node _T_20 = cat(_T_7, _T_14) @[Cat.scala 29:58]
+    node control_in = cat(_T_20, _T_19) @[Cat.scala 29:58]
+    node dividend_sign_ff = bits(control_ff, 2, 2) @[exu_div_ctl.scala 651:40]
+    node divisor_sign_ff = bits(control_ff, 1, 1) @[exu_div_ctl.scala 652:40]
+    node rem_ff = bits(control_ff, 0, 0) @[exu_div_ctl.scala 653:40]
+    node _T_21 = bits(b_ff, 31, 0) @[exu_div_ctl.scala 654:47]
+    node _T_22 = eq(_T_21, UInt<1>("h00")) @[exu_div_ctl.scala 654:54]
+    node by_zero_case = and(valid_ff, _T_22) @[exu_div_ctl.scala 654:40]
+    node _T_23 = bits(a_ff, 31, 4) @[exu_div_ctl.scala 656:30]
+    node _T_24 = eq(_T_23, UInt<1>("h00")) @[exu_div_ctl.scala 656:37]
+    node _T_25 = bits(b_ff, 31, 4) @[exu_div_ctl.scala 656:53]
+    node _T_26 = eq(_T_25, UInt<1>("h00")) @[exu_div_ctl.scala 656:60]
+    node _T_27 = and(_T_24, _T_26) @[exu_div_ctl.scala 656:46]
+    node _T_28 = eq(by_zero_case, UInt<1>("h00")) @[exu_div_ctl.scala 656:71]
+    node _T_29 = and(_T_27, _T_28) @[exu_div_ctl.scala 656:69]
+    node _T_30 = eq(rem_ff, UInt<1>("h00")) @[exu_div_ctl.scala 656:87]
+    node _T_31 = and(_T_29, _T_30) @[exu_div_ctl.scala 656:85]
+    node _T_32 = and(_T_31, valid_ff) @[exu_div_ctl.scala 656:95]
+    node _T_33 = eq(io.cancel, UInt<1>("h00")) @[exu_div_ctl.scala 656:108]
+    node _T_34 = and(_T_32, _T_33) @[exu_div_ctl.scala 656:106]
+    node _T_35 = bits(a_ff, 31, 0) @[exu_div_ctl.scala 657:11]
+    node _T_36 = eq(_T_35, UInt<1>("h00")) @[exu_div_ctl.scala 657:18]
+    node _T_37 = eq(by_zero_case, UInt<1>("h00")) @[exu_div_ctl.scala 657:29]
+    node _T_38 = and(_T_36, _T_37) @[exu_div_ctl.scala 657:27]
+    node _T_39 = eq(rem_ff, UInt<1>("h00")) @[exu_div_ctl.scala 657:45]
+    node _T_40 = and(_T_38, _T_39) @[exu_div_ctl.scala 657:43]
+    node _T_41 = and(_T_40, valid_ff) @[exu_div_ctl.scala 657:53]
+    node _T_42 = eq(io.cancel, UInt<1>("h00")) @[exu_div_ctl.scala 657:66]
+    node _T_43 = and(_T_41, _T_42) @[exu_div_ctl.scala 657:64]
+    node smallnum_case = or(_T_34, _T_43) @[exu_div_ctl.scala 656:120]
+    node _T_44 = orr(count_ff) @[exu_div_ctl.scala 658:42]
+    node running_state = or(_T_44, shortq_enable_ff) @[exu_div_ctl.scala 658:45]
+    node _T_45 = or(io.valid_in, valid_ff) @[exu_div_ctl.scala 659:43]
+    node _T_46 = or(_T_45, io.cancel) @[exu_div_ctl.scala 659:54]
+    node _T_47 = or(_T_46, running_state) @[exu_div_ctl.scala 659:66]
+    node misc_enable = or(_T_47, finish_ff) @[exu_div_ctl.scala 659:82]
+    node _T_48 = or(smallnum_case, by_zero_case) @[exu_div_ctl.scala 660:45]
+    node _T_49 = eq(count_ff, UInt<6>("h021")) @[exu_div_ctl.scala 660:72]
+    node finish_raw = or(_T_48, _T_49) @[exu_div_ctl.scala 660:60]
+    node _T_50 = eq(io.cancel, UInt<1>("h00")) @[exu_div_ctl.scala 661:43]
+    node finish = and(finish_raw, _T_50) @[exu_div_ctl.scala 661:41]
+    node _T_51 = or(valid_ff, running_state) @[exu_div_ctl.scala 662:40]
+    node _T_52 = eq(finish, UInt<1>("h00")) @[exu_div_ctl.scala 662:59]
+    node _T_53 = and(_T_51, _T_52) @[exu_div_ctl.scala 662:57]
+    node _T_54 = eq(finish_ff, UInt<1>("h00")) @[exu_div_ctl.scala 662:69]
+    node _T_55 = and(_T_53, _T_54) @[exu_div_ctl.scala 662:67]
+    node _T_56 = eq(io.cancel, UInt<1>("h00")) @[exu_div_ctl.scala 662:82]
+    node _T_57 = and(_T_55, _T_56) @[exu_div_ctl.scala 662:80]
+    node _T_58 = eq(shortq_enable, UInt<1>("h00")) @[exu_div_ctl.scala 662:95]
+    node count_enable = and(_T_57, _T_58) @[exu_div_ctl.scala 662:93]
+    node _T_59 = bits(count_enable, 0, 0) @[Bitwise.scala 72:15]
+    node _T_60 = mux(_T_59, UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 72:12]
+    node _T_61 = cat(UInt<5>("h00"), UInt<2>("h03")) @[Cat.scala 29:58]
+    node _T_62 = add(count_ff, _T_61) @[exu_div_ctl.scala 663:63]
+    node _T_63 = tail(_T_62, 1) @[exu_div_ctl.scala 663:63]
+    node _T_64 = cat(UInt<2>("h00"), shortq_shift_ff) @[Cat.scala 29:58]
+    node _T_65 = add(_T_63, _T_64) @[exu_div_ctl.scala 663:83]
+    node _T_66 = tail(_T_65, 1) @[exu_div_ctl.scala 663:83]
+    node count_in = and(_T_60, _T_66) @[exu_div_ctl.scala 663:51]
+    node a_enable = or(io.valid_in, running_state) @[exu_div_ctl.scala 664:43]
+    node _T_67 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 665:47]
+    node a_shift = and(running_state, _T_67) @[exu_div_ctl.scala 665:45]
+    node _T_68 = bits(dividend_sign_ff, 0, 0) @[Bitwise.scala 72:15]
+    node _T_69 = mux(_T_68, UInt<33>("h01ffffffff"), UInt<33>("h00")) @[Bitwise.scala 72:12]
+    node _T_70 = cat(_T_69, a_ff) @[Cat.scala 29:58]
+    node _T_71 = dshl(_T_70, shortq_shift_ff) @[exu_div_ctl.scala 666:68]
+    ar_shifted <= _T_71 @[exu_div_ctl.scala 666:28]
+    node _T_72 = xor(dividend_sign_ff, divisor_sign_ff) @[exu_div_ctl.scala 667:61]
+    node _T_73 = eq(_T_72, UInt<1>("h00")) @[exu_div_ctl.scala 667:42]
+    node b_twos_comp = and(valid_ff, _T_73) @[exu_div_ctl.scala 667:40]
+    node _T_74 = xor(dividend_sign_ff, divisor_sign_ff) @[exu_div_ctl.scala 668:62]
+    node _T_75 = eq(_T_74, UInt<1>("h00")) @[exu_div_ctl.scala 668:43]
+    node twos_comp_b_sel = and(valid_ff, _T_75) @[exu_div_ctl.scala 668:41]
+    node _T_76 = eq(valid_ff, UInt<1>("h00")) @[exu_div_ctl.scala 669:30]
+    node _T_77 = eq(rem_ff, UInt<1>("h00")) @[exu_div_ctl.scala 669:42]
+    node _T_78 = and(_T_76, _T_77) @[exu_div_ctl.scala 669:40]
+    node _T_79 = xor(dividend_sign_ff, divisor_sign_ff) @[exu_div_ctl.scala 669:71]
+    node _T_80 = and(_T_78, _T_79) @[exu_div_ctl.scala 669:50]
+    node _T_81 = eq(by_zero_case_ff, UInt<1>("h00")) @[exu_div_ctl.scala 669:92]
+    node twos_comp_q_sel = and(_T_80, _T_81) @[exu_div_ctl.scala 669:90]
+    node b_enable = or(io.valid_in, b_twos_comp) @[exu_div_ctl.scala 670:43]
+    node _T_82 = or(io.valid_in, valid_ff) @[exu_div_ctl.scala 671:43]
+    node rq_enable = or(_T_82, running_state) @[exu_div_ctl.scala 671:54]
+    node _T_83 = and(valid_ff, dividend_sign_ff) @[exu_div_ctl.scala 672:40]
+    node _T_84 = eq(by_zero_case, UInt<1>("h00")) @[exu_div_ctl.scala 672:61]
+    node r_sign_sel = and(_T_83, _T_84) @[exu_div_ctl.scala 672:59]
+    node _T_85 = eq(quotient_new, UInt<1>("h00")) @[exu_div_ctl.scala 673:61]
+    node _T_86 = and(running_state, _T_85) @[exu_div_ctl.scala 673:45]
+    node _T_87 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 673:72]
+    node r_restore_sel = and(_T_86, _T_87) @[exu_div_ctl.scala 673:70]
+    node _T_88 = eq(quotient_new, UInt<1>("h01")) @[exu_div_ctl.scala 674:61]
+    node _T_89 = and(running_state, _T_88) @[exu_div_ctl.scala 674:45]
+    node _T_90 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 674:72]
+    node r_adder1_sel = and(_T_89, _T_90) @[exu_div_ctl.scala 674:70]
+    node _T_91 = eq(quotient_new, UInt<2>("h02")) @[exu_div_ctl.scala 675:61]
+    node _T_92 = and(running_state, _T_91) @[exu_div_ctl.scala 675:45]
+    node _T_93 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 675:72]
+    node r_adder2_sel = and(_T_92, _T_93) @[exu_div_ctl.scala 675:70]
+    node _T_94 = eq(quotient_new, UInt<2>("h03")) @[exu_div_ctl.scala 676:61]
+    node _T_95 = and(running_state, _T_94) @[exu_div_ctl.scala 676:45]
+    node _T_96 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 676:72]
+    node r_adder3_sel = and(_T_95, _T_96) @[exu_div_ctl.scala 676:70]
+    node _T_97 = eq(quotient_new, UInt<3>("h04")) @[exu_div_ctl.scala 677:61]
+    node _T_98 = and(running_state, _T_97) @[exu_div_ctl.scala 677:45]
+    node _T_99 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 677:72]
+    node r_adder4_sel = and(_T_98, _T_99) @[exu_div_ctl.scala 677:70]
+    node _T_100 = eq(quotient_new, UInt<3>("h05")) @[exu_div_ctl.scala 678:61]
+    node _T_101 = and(running_state, _T_100) @[exu_div_ctl.scala 678:45]
+    node _T_102 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 678:72]
+    node r_adder5_sel = and(_T_101, _T_102) @[exu_div_ctl.scala 678:70]
+    node _T_103 = eq(quotient_new, UInt<3>("h06")) @[exu_div_ctl.scala 679:61]
+    node _T_104 = and(running_state, _T_103) @[exu_div_ctl.scala 679:45]
+    node _T_105 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 679:72]
+    node r_adder6_sel = and(_T_104, _T_105) @[exu_div_ctl.scala 679:70]
+    node _T_106 = eq(quotient_new, UInt<3>("h06")) @[exu_div_ctl.scala 680:61]
+    node _T_107 = and(running_state, _T_106) @[exu_div_ctl.scala 680:45]
+    node _T_108 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 680:72]
+    node r_adder7_sel = and(_T_107, _T_108) @[exu_div_ctl.scala 680:70]
+    node _T_109 = bits(r_ff, 30, 0) @[exu_div_ctl.scala 681:28]
+    node _T_110 = bits(a_ff, 32, 30) @[exu_div_ctl.scala 681:39]
+    node _T_111 = cat(_T_109, _T_110) @[Cat.scala 29:58]
+    node _T_112 = bits(b_ff, 33, 0) @[exu_div_ctl.scala 681:54]
+    node _T_113 = add(_T_111, _T_112) @[exu_div_ctl.scala 681:48]
+    node adder1_out = tail(_T_113, 1) @[exu_div_ctl.scala 681:48]
+    node _T_114 = bits(r_ff, 31, 0) @[exu_div_ctl.scala 682:28]
+    node _T_115 = bits(a_ff, 32, 30) @[exu_div_ctl.scala 682:39]
+    node _T_116 = cat(_T_114, _T_115) @[Cat.scala 29:58]
+    node _T_117 = bits(b_ff, 33, 0) @[exu_div_ctl.scala 682:58]
+    node _T_118 = cat(_T_117, UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_119 = add(_T_116, _T_118) @[exu_div_ctl.scala 682:48]
+    node adder2_out = tail(_T_119, 1) @[exu_div_ctl.scala 682:48]
+    node _T_120 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 683:28]
+    node _T_121 = bits(a_ff, 32, 30) @[exu_div_ctl.scala 683:39]
+    node _T_122 = cat(_T_120, _T_121) @[Cat.scala 29:58]
+    node _T_123 = bits(b_ff, 34, 0) @[exu_div_ctl.scala 683:58]
+    node _T_124 = cat(_T_123, UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_125 = add(_T_122, _T_124) @[exu_div_ctl.scala 683:48]
+    node _T_126 = tail(_T_125, 1) @[exu_div_ctl.scala 683:48]
+    node _T_127 = bits(b_ff, 35, 0) @[exu_div_ctl.scala 683:76]
+    node _T_128 = add(_T_126, _T_127) @[exu_div_ctl.scala 683:70]
+    node adder3_out = tail(_T_128, 1) @[exu_div_ctl.scala 683:70]
+    node _T_129 = bits(r_ff, 32, 32) @[exu_div_ctl.scala 684:28]
+    node _T_130 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 684:37]
+    node _T_131 = bits(a_ff, 32, 30) @[exu_div_ctl.scala 684:48]
+    node _T_132 = cat(_T_129, _T_130) @[Cat.scala 29:58]
+    node _T_133 = cat(_T_132, _T_131) @[Cat.scala 29:58]
+    node _T_134 = bits(b_ff, 34, 0) @[exu_div_ctl.scala 684:67]
+    node _T_135 = cat(_T_134, UInt<2>("h00")) @[Cat.scala 29:58]
+    node _T_136 = add(_T_133, _T_135) @[exu_div_ctl.scala 684:57]
+    node adder4_out = tail(_T_136, 1) @[exu_div_ctl.scala 684:57]
+    node _T_137 = bits(r_ff, 32, 32) @[exu_div_ctl.scala 685:28]
+    node _T_138 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 685:37]
+    node _T_139 = bits(a_ff, 32, 30) @[exu_div_ctl.scala 685:48]
+    node _T_140 = cat(_T_137, _T_138) @[Cat.scala 29:58]
+    node _T_141 = cat(_T_140, _T_139) @[Cat.scala 29:58]
+    node _T_142 = bits(b_ff, 34, 0) @[exu_div_ctl.scala 685:67]
+    node _T_143 = cat(_T_142, UInt<2>("h00")) @[Cat.scala 29:58]
+    node _T_144 = add(_T_141, _T_143) @[exu_div_ctl.scala 685:57]
+    node _T_145 = tail(_T_144, 1) @[exu_div_ctl.scala 685:57]
+    node _T_146 = add(_T_145, b_ff) @[exu_div_ctl.scala 685:84]
+    node adder5_out = tail(_T_146, 1) @[exu_div_ctl.scala 685:84]
+    node _T_147 = bits(r_ff, 32, 32) @[exu_div_ctl.scala 686:28]
+    node _T_148 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 686:37]
+    node _T_149 = bits(a_ff, 32, 30) @[exu_div_ctl.scala 686:48]
+    node _T_150 = cat(_T_147, _T_148) @[Cat.scala 29:58]
+    node _T_151 = cat(_T_150, _T_149) @[Cat.scala 29:58]
+    node _T_152 = bits(b_ff, 34, 0) @[exu_div_ctl.scala 686:67]
+    node _T_153 = cat(_T_152, UInt<2>("h00")) @[Cat.scala 29:58]
+    node _T_154 = add(_T_151, _T_153) @[exu_div_ctl.scala 686:57]
+    node _T_155 = tail(_T_154, 1) @[exu_div_ctl.scala 686:57]
+    node _T_156 = bits(b_ff, 35, 0) @[exu_div_ctl.scala 686:94]
+    node _T_157 = cat(_T_156, UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_158 = add(_T_155, _T_157) @[exu_div_ctl.scala 686:84]
+    node adder6_out = tail(_T_158, 1) @[exu_div_ctl.scala 686:84]
+    node _T_159 = bits(r_ff, 32, 32) @[exu_div_ctl.scala 687:28]
+    node _T_160 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 687:37]
+    node _T_161 = bits(a_ff, 32, 30) @[exu_div_ctl.scala 687:48]
+    node _T_162 = cat(_T_159, _T_160) @[Cat.scala 29:58]
+    node _T_163 = cat(_T_162, _T_161) @[Cat.scala 29:58]
+    node _T_164 = bits(b_ff, 34, 0) @[exu_div_ctl.scala 687:67]
+    node _T_165 = cat(_T_164, UInt<2>("h00")) @[Cat.scala 29:58]
+    node _T_166 = add(_T_163, _T_165) @[exu_div_ctl.scala 687:57]
+    node _T_167 = tail(_T_166, 1) @[exu_div_ctl.scala 687:57]
+    node _T_168 = bits(b_ff, 35, 0) @[exu_div_ctl.scala 687:94]
+    node _T_169 = cat(_T_168, UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_170 = add(_T_167, _T_169) @[exu_div_ctl.scala 687:84]
+    node _T_171 = tail(_T_170, 1) @[exu_div_ctl.scala 687:84]
+    node _T_172 = add(_T_171, b_ff) @[exu_div_ctl.scala 687:106]
+    node adder7_out = tail(_T_172, 1) @[exu_div_ctl.scala 687:106]
+    node _T_173 = bits(adder7_out, 36, 36) @[exu_div_ctl.scala 688:35]
+    node _T_174 = eq(_T_173, UInt<1>("h00")) @[exu_div_ctl.scala 688:24]
+    node _T_175 = xor(_T_174, dividend_sign_ff) @[exu_div_ctl.scala 688:40]
+    node _T_176 = bits(a_ff, 29, 0) @[exu_div_ctl.scala 688:68]
+    node _T_177 = eq(_T_176, UInt<1>("h00")) @[exu_div_ctl.scala 688:75]
+    node _T_178 = eq(adder7_out, UInt<1>("h00")) @[exu_div_ctl.scala 688:98]
+    node _T_179 = and(_T_177, _T_178) @[exu_div_ctl.scala 688:84]
+    node _T_180 = or(_T_175, _T_179) @[exu_div_ctl.scala 688:60]
+    node _T_181 = bits(adder6_out, 36, 36) @[exu_div_ctl.scala 689:34]
+    node _T_182 = eq(_T_181, UInt<1>("h00")) @[exu_div_ctl.scala 689:23]
+    node _T_183 = xor(_T_182, dividend_sign_ff) @[exu_div_ctl.scala 689:39]
+    node _T_184 = bits(a_ff, 29, 0) @[exu_div_ctl.scala 689:67]
+    node _T_185 = eq(_T_184, UInt<1>("h00")) @[exu_div_ctl.scala 689:74]
+    node _T_186 = eq(adder6_out, UInt<1>("h00")) @[exu_div_ctl.scala 689:97]
+    node _T_187 = and(_T_185, _T_186) @[exu_div_ctl.scala 689:83]
+    node _T_188 = or(_T_183, _T_187) @[exu_div_ctl.scala 689:59]
+    node _T_189 = bits(adder5_out, 36, 36) @[exu_div_ctl.scala 690:34]
+    node _T_190 = eq(_T_189, UInt<1>("h00")) @[exu_div_ctl.scala 690:23]
+    node _T_191 = xor(_T_190, dividend_sign_ff) @[exu_div_ctl.scala 690:39]
+    node _T_192 = bits(a_ff, 29, 0) @[exu_div_ctl.scala 690:67]
+    node _T_193 = eq(_T_192, UInt<1>("h00")) @[exu_div_ctl.scala 690:74]
+    node _T_194 = eq(adder5_out, UInt<1>("h00")) @[exu_div_ctl.scala 690:97]
+    node _T_195 = and(_T_193, _T_194) @[exu_div_ctl.scala 690:83]
+    node _T_196 = or(_T_191, _T_195) @[exu_div_ctl.scala 690:59]
+    node _T_197 = bits(adder4_out, 36, 36) @[exu_div_ctl.scala 691:34]
+    node _T_198 = eq(_T_197, UInt<1>("h00")) @[exu_div_ctl.scala 691:23]
+    node _T_199 = xor(_T_198, dividend_sign_ff) @[exu_div_ctl.scala 691:39]
+    node _T_200 = bits(a_ff, 29, 0) @[exu_div_ctl.scala 691:67]
+    node _T_201 = eq(_T_200, UInt<1>("h00")) @[exu_div_ctl.scala 691:74]
+    node _T_202 = eq(adder4_out, UInt<1>("h00")) @[exu_div_ctl.scala 691:97]
+    node _T_203 = and(_T_201, _T_202) @[exu_div_ctl.scala 691:83]
+    node _T_204 = or(_T_199, _T_203) @[exu_div_ctl.scala 691:59]
+    node _T_205 = bits(adder3_out, 35, 35) @[exu_div_ctl.scala 692:34]
+    node _T_206 = eq(_T_205, UInt<1>("h00")) @[exu_div_ctl.scala 692:23]
+    node _T_207 = xor(_T_206, dividend_sign_ff) @[exu_div_ctl.scala 692:39]
+    node _T_208 = bits(a_ff, 29, 0) @[exu_div_ctl.scala 692:67]
+    node _T_209 = eq(_T_208, UInt<1>("h00")) @[exu_div_ctl.scala 692:74]
+    node _T_210 = eq(adder3_out, UInt<1>("h00")) @[exu_div_ctl.scala 692:97]
+    node _T_211 = and(_T_209, _T_210) @[exu_div_ctl.scala 692:83]
+    node _T_212 = or(_T_207, _T_211) @[exu_div_ctl.scala 692:59]
+    node _T_213 = bits(adder2_out, 34, 34) @[exu_div_ctl.scala 693:34]
+    node _T_214 = eq(_T_213, UInt<1>("h00")) @[exu_div_ctl.scala 693:23]
+    node _T_215 = xor(_T_214, dividend_sign_ff) @[exu_div_ctl.scala 693:39]
+    node _T_216 = bits(a_ff, 29, 0) @[exu_div_ctl.scala 693:67]
+    node _T_217 = eq(_T_216, UInt<1>("h00")) @[exu_div_ctl.scala 693:74]
+    node _T_218 = eq(adder2_out, UInt<1>("h00")) @[exu_div_ctl.scala 693:97]
+    node _T_219 = and(_T_217, _T_218) @[exu_div_ctl.scala 693:83]
+    node _T_220 = or(_T_215, _T_219) @[exu_div_ctl.scala 693:59]
+    node _T_221 = bits(adder1_out, 33, 33) @[exu_div_ctl.scala 694:34]
+    node _T_222 = eq(_T_221, UInt<1>("h00")) @[exu_div_ctl.scala 694:23]
+    node _T_223 = xor(_T_222, dividend_sign_ff) @[exu_div_ctl.scala 694:39]
+    node _T_224 = bits(a_ff, 29, 0) @[exu_div_ctl.scala 694:67]
+    node _T_225 = eq(_T_224, UInt<1>("h00")) @[exu_div_ctl.scala 694:74]
+    node _T_226 = eq(adder1_out, UInt<1>("h00")) @[exu_div_ctl.scala 694:97]
+    node _T_227 = and(_T_225, _T_226) @[exu_div_ctl.scala 694:83]
+    node _T_228 = or(_T_223, _T_227) @[exu_div_ctl.scala 694:59]
+    node _T_229 = cat(_T_228, UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_230 = cat(_T_212, _T_220) @[Cat.scala 29:58]
+    node _T_231 = cat(_T_230, _T_229) @[Cat.scala 29:58]
+    node _T_232 = cat(_T_196, _T_204) @[Cat.scala 29:58]
+    node _T_233 = cat(_T_180, _T_188) @[Cat.scala 29:58]
+    node _T_234 = cat(_T_233, _T_232) @[Cat.scala 29:58]
+    node _T_235 = cat(_T_234, _T_231) @[Cat.scala 29:58]
+    quotient_raw <= _T_235 @[exu_div_ctl.scala 688:16]
+    node _T_236 = bits(quotient_raw, 7, 7) @[exu_div_ctl.scala 695:39]
+    node _T_237 = bits(quotient_raw, 6, 6) @[exu_div_ctl.scala 695:58]
+    node _T_238 = or(_T_236, _T_237) @[exu_div_ctl.scala 695:43]
+    node _T_239 = bits(quotient_raw, 5, 5) @[exu_div_ctl.scala 695:76]
+    node _T_240 = or(_T_238, _T_239) @[exu_div_ctl.scala 695:62]
+    node _T_241 = bits(quotient_raw, 4, 4) @[exu_div_ctl.scala 695:95]
+    node _T_242 = or(_T_240, _T_241) @[exu_div_ctl.scala 695:80]
+    node _T_243 = bits(quotient_raw, 7, 7) @[exu_div_ctl.scala 696:38]
+    node _T_244 = bits(quotient_raw, 6, 6) @[exu_div_ctl.scala 696:57]
+    node _T_245 = or(_T_243, _T_244) @[exu_div_ctl.scala 696:42]
+    node _T_246 = bits(quotient_raw, 4, 4) @[exu_div_ctl.scala 696:76]
+    node _T_247 = eq(_T_246, UInt<1>("h00")) @[exu_div_ctl.scala 696:63]
+    node _T_248 = bits(quotient_raw, 3, 3) @[exu_div_ctl.scala 696:94]
+    node _T_249 = and(_T_247, _T_248) @[exu_div_ctl.scala 696:80]
+    node _T_250 = or(_T_245, _T_249) @[exu_div_ctl.scala 696:61]
+    node _T_251 = bits(quotient_raw, 3, 3) @[exu_div_ctl.scala 696:114]
+    node _T_252 = eq(_T_251, UInt<1>("h00")) @[exu_div_ctl.scala 696:101]
+    node _T_253 = bits(quotient_raw, 2, 2) @[exu_div_ctl.scala 696:132]
+    node _T_254 = and(_T_252, _T_253) @[exu_div_ctl.scala 696:118]
+    node _T_255 = or(_T_250, _T_254) @[exu_div_ctl.scala 696:99]
+    node _T_256 = bits(quotient_raw, 7, 7) @[exu_div_ctl.scala 697:38]
+    node _T_257 = bits(quotient_raw, 6, 6) @[exu_div_ctl.scala 697:57]
+    node _T_258 = bits(quotient_raw, 5, 5) @[exu_div_ctl.scala 697:75]
+    node _T_259 = and(_T_257, _T_258) @[exu_div_ctl.scala 697:61]
+    node _T_260 = or(_T_256, _T_259) @[exu_div_ctl.scala 697:42]
+    node _T_261 = bits(quotient_raw, 4, 4) @[exu_div_ctl.scala 697:94]
+    node _T_262 = eq(_T_261, UInt<1>("h00")) @[exu_div_ctl.scala 697:81]
+    node _T_263 = bits(quotient_raw, 3, 3) @[exu_div_ctl.scala 697:112]
+    node _T_264 = and(_T_262, _T_263) @[exu_div_ctl.scala 697:98]
+    node _T_265 = or(_T_260, _T_264) @[exu_div_ctl.scala 697:79]
+    node _T_266 = bits(quotient_raw, 2, 2) @[exu_div_ctl.scala 697:132]
+    node _T_267 = eq(_T_266, UInt<1>("h00")) @[exu_div_ctl.scala 697:119]
+    node _T_268 = bits(quotient_raw, 1, 1) @[exu_div_ctl.scala 697:150]
+    node _T_269 = and(_T_267, _T_268) @[exu_div_ctl.scala 697:136]
+    node _T_270 = or(_T_265, _T_269) @[exu_div_ctl.scala 697:117]
+    node _T_271 = cat(_T_242, _T_255) @[Cat.scala 29:58]
+    node _T_272 = cat(_T_271, _T_270) @[Cat.scala 29:58]
+    quotient_new <= _T_272 @[exu_div_ctl.scala 695:18]
+    node _T_273 = bits(b_ff, 31, 0) @[exu_div_ctl.scala 700:48]
+    node _T_274 = mux(twos_comp_q_sel, q_ff, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_275 = mux(twos_comp_b_sel, _T_273, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_276 = or(_T_274, _T_275) @[Mux.scala 27:72]
+    wire twos_comp_in : UInt<32> @[Mux.scala 27:72]
+    twos_comp_in <= _T_276 @[Mux.scala 27:72]
+    wire _T_277 : UInt<1>[31] @[lib.scala 426:20]
+    node _T_278 = bits(twos_comp_in, 0, 0) @[lib.scala 428:27]
+    node _T_279 = orr(_T_278) @[lib.scala 428:35]
+    node _T_280 = bits(twos_comp_in, 1, 1) @[lib.scala 428:44]
+    node _T_281 = not(_T_280) @[lib.scala 428:40]
+    node _T_282 = bits(twos_comp_in, 1, 1) @[lib.scala 428:51]
+    node _T_283 = mux(_T_279, _T_281, _T_282) @[lib.scala 428:23]
+    _T_277[0] <= _T_283 @[lib.scala 428:17]
+    node _T_284 = bits(twos_comp_in, 1, 0) @[lib.scala 428:27]
+    node _T_285 = orr(_T_284) @[lib.scala 428:35]
+    node _T_286 = bits(twos_comp_in, 2, 2) @[lib.scala 428:44]
+    node _T_287 = not(_T_286) @[lib.scala 428:40]
+    node _T_288 = bits(twos_comp_in, 2, 2) @[lib.scala 428:51]
+    node _T_289 = mux(_T_285, _T_287, _T_288) @[lib.scala 428:23]
+    _T_277[1] <= _T_289 @[lib.scala 428:17]
+    node _T_290 = bits(twos_comp_in, 2, 0) @[lib.scala 428:27]
+    node _T_291 = orr(_T_290) @[lib.scala 428:35]
+    node _T_292 = bits(twos_comp_in, 3, 3) @[lib.scala 428:44]
+    node _T_293 = not(_T_292) @[lib.scala 428:40]
+    node _T_294 = bits(twos_comp_in, 3, 3) @[lib.scala 428:51]
+    node _T_295 = mux(_T_291, _T_293, _T_294) @[lib.scala 428:23]
+    _T_277[2] <= _T_295 @[lib.scala 428:17]
+    node _T_296 = bits(twos_comp_in, 3, 0) @[lib.scala 428:27]
+    node _T_297 = orr(_T_296) @[lib.scala 428:35]
+    node _T_298 = bits(twos_comp_in, 4, 4) @[lib.scala 428:44]
+    node _T_299 = not(_T_298) @[lib.scala 428:40]
+    node _T_300 = bits(twos_comp_in, 4, 4) @[lib.scala 428:51]
+    node _T_301 = mux(_T_297, _T_299, _T_300) @[lib.scala 428:23]
+    _T_277[3] <= _T_301 @[lib.scala 428:17]
+    node _T_302 = bits(twos_comp_in, 4, 0) @[lib.scala 428:27]
+    node _T_303 = orr(_T_302) @[lib.scala 428:35]
+    node _T_304 = bits(twos_comp_in, 5, 5) @[lib.scala 428:44]
+    node _T_305 = not(_T_304) @[lib.scala 428:40]
+    node _T_306 = bits(twos_comp_in, 5, 5) @[lib.scala 428:51]
+    node _T_307 = mux(_T_303, _T_305, _T_306) @[lib.scala 428:23]
+    _T_277[4] <= _T_307 @[lib.scala 428:17]
+    node _T_308 = bits(twos_comp_in, 5, 0) @[lib.scala 428:27]
+    node _T_309 = orr(_T_308) @[lib.scala 428:35]
+    node _T_310 = bits(twos_comp_in, 6, 6) @[lib.scala 428:44]
+    node _T_311 = not(_T_310) @[lib.scala 428:40]
+    node _T_312 = bits(twos_comp_in, 6, 6) @[lib.scala 428:51]
+    node _T_313 = mux(_T_309, _T_311, _T_312) @[lib.scala 428:23]
+    _T_277[5] <= _T_313 @[lib.scala 428:17]
+    node _T_314 = bits(twos_comp_in, 6, 0) @[lib.scala 428:27]
+    node _T_315 = orr(_T_314) @[lib.scala 428:35]
+    node _T_316 = bits(twos_comp_in, 7, 7) @[lib.scala 428:44]
+    node _T_317 = not(_T_316) @[lib.scala 428:40]
+    node _T_318 = bits(twos_comp_in, 7, 7) @[lib.scala 428:51]
+    node _T_319 = mux(_T_315, _T_317, _T_318) @[lib.scala 428:23]
+    _T_277[6] <= _T_319 @[lib.scala 428:17]
+    node _T_320 = bits(twos_comp_in, 7, 0) @[lib.scala 428:27]
+    node _T_321 = orr(_T_320) @[lib.scala 428:35]
+    node _T_322 = bits(twos_comp_in, 8, 8) @[lib.scala 428:44]
+    node _T_323 = not(_T_322) @[lib.scala 428:40]
+    node _T_324 = bits(twos_comp_in, 8, 8) @[lib.scala 428:51]
+    node _T_325 = mux(_T_321, _T_323, _T_324) @[lib.scala 428:23]
+    _T_277[7] <= _T_325 @[lib.scala 428:17]
+    node _T_326 = bits(twos_comp_in, 8, 0) @[lib.scala 428:27]
+    node _T_327 = orr(_T_326) @[lib.scala 428:35]
+    node _T_328 = bits(twos_comp_in, 9, 9) @[lib.scala 428:44]
+    node _T_329 = not(_T_328) @[lib.scala 428:40]
+    node _T_330 = bits(twos_comp_in, 9, 9) @[lib.scala 428:51]
+    node _T_331 = mux(_T_327, _T_329, _T_330) @[lib.scala 428:23]
+    _T_277[8] <= _T_331 @[lib.scala 428:17]
+    node _T_332 = bits(twos_comp_in, 9, 0) @[lib.scala 428:27]
+    node _T_333 = orr(_T_332) @[lib.scala 428:35]
+    node _T_334 = bits(twos_comp_in, 10, 10) @[lib.scala 428:44]
+    node _T_335 = not(_T_334) @[lib.scala 428:40]
+    node _T_336 = bits(twos_comp_in, 10, 10) @[lib.scala 428:51]
+    node _T_337 = mux(_T_333, _T_335, _T_336) @[lib.scala 428:23]
+    _T_277[9] <= _T_337 @[lib.scala 428:17]
+    node _T_338 = bits(twos_comp_in, 10, 0) @[lib.scala 428:27]
+    node _T_339 = orr(_T_338) @[lib.scala 428:35]
+    node _T_340 = bits(twos_comp_in, 11, 11) @[lib.scala 428:44]
+    node _T_341 = not(_T_340) @[lib.scala 428:40]
+    node _T_342 = bits(twos_comp_in, 11, 11) @[lib.scala 428:51]
+    node _T_343 = mux(_T_339, _T_341, _T_342) @[lib.scala 428:23]
+    _T_277[10] <= _T_343 @[lib.scala 428:17]
+    node _T_344 = bits(twos_comp_in, 11, 0) @[lib.scala 428:27]
+    node _T_345 = orr(_T_344) @[lib.scala 428:35]
+    node _T_346 = bits(twos_comp_in, 12, 12) @[lib.scala 428:44]
+    node _T_347 = not(_T_346) @[lib.scala 428:40]
+    node _T_348 = bits(twos_comp_in, 12, 12) @[lib.scala 428:51]
+    node _T_349 = mux(_T_345, _T_347, _T_348) @[lib.scala 428:23]
+    _T_277[11] <= _T_349 @[lib.scala 428:17]
+    node _T_350 = bits(twos_comp_in, 12, 0) @[lib.scala 428:27]
+    node _T_351 = orr(_T_350) @[lib.scala 428:35]
+    node _T_352 = bits(twos_comp_in, 13, 13) @[lib.scala 428:44]
+    node _T_353 = not(_T_352) @[lib.scala 428:40]
+    node _T_354 = bits(twos_comp_in, 13, 13) @[lib.scala 428:51]
+    node _T_355 = mux(_T_351, _T_353, _T_354) @[lib.scala 428:23]
+    _T_277[12] <= _T_355 @[lib.scala 428:17]
+    node _T_356 = bits(twos_comp_in, 13, 0) @[lib.scala 428:27]
+    node _T_357 = orr(_T_356) @[lib.scala 428:35]
+    node _T_358 = bits(twos_comp_in, 14, 14) @[lib.scala 428:44]
+    node _T_359 = not(_T_358) @[lib.scala 428:40]
+    node _T_360 = bits(twos_comp_in, 14, 14) @[lib.scala 428:51]
+    node _T_361 = mux(_T_357, _T_359, _T_360) @[lib.scala 428:23]
+    _T_277[13] <= _T_361 @[lib.scala 428:17]
+    node _T_362 = bits(twos_comp_in, 14, 0) @[lib.scala 428:27]
+    node _T_363 = orr(_T_362) @[lib.scala 428:35]
+    node _T_364 = bits(twos_comp_in, 15, 15) @[lib.scala 428:44]
+    node _T_365 = not(_T_364) @[lib.scala 428:40]
+    node _T_366 = bits(twos_comp_in, 15, 15) @[lib.scala 428:51]
+    node _T_367 = mux(_T_363, _T_365, _T_366) @[lib.scala 428:23]
+    _T_277[14] <= _T_367 @[lib.scala 428:17]
+    node _T_368 = bits(twos_comp_in, 15, 0) @[lib.scala 428:27]
+    node _T_369 = orr(_T_368) @[lib.scala 428:35]
+    node _T_370 = bits(twos_comp_in, 16, 16) @[lib.scala 428:44]
+    node _T_371 = not(_T_370) @[lib.scala 428:40]
+    node _T_372 = bits(twos_comp_in, 16, 16) @[lib.scala 428:51]
+    node _T_373 = mux(_T_369, _T_371, _T_372) @[lib.scala 428:23]
+    _T_277[15] <= _T_373 @[lib.scala 428:17]
+    node _T_374 = bits(twos_comp_in, 16, 0) @[lib.scala 428:27]
+    node _T_375 = orr(_T_374) @[lib.scala 428:35]
+    node _T_376 = bits(twos_comp_in, 17, 17) @[lib.scala 428:44]
+    node _T_377 = not(_T_376) @[lib.scala 428:40]
+    node _T_378 = bits(twos_comp_in, 17, 17) @[lib.scala 428:51]
+    node _T_379 = mux(_T_375, _T_377, _T_378) @[lib.scala 428:23]
+    _T_277[16] <= _T_379 @[lib.scala 428:17]
+    node _T_380 = bits(twos_comp_in, 17, 0) @[lib.scala 428:27]
+    node _T_381 = orr(_T_380) @[lib.scala 428:35]
+    node _T_382 = bits(twos_comp_in, 18, 18) @[lib.scala 428:44]
+    node _T_383 = not(_T_382) @[lib.scala 428:40]
+    node _T_384 = bits(twos_comp_in, 18, 18) @[lib.scala 428:51]
+    node _T_385 = mux(_T_381, _T_383, _T_384) @[lib.scala 428:23]
+    _T_277[17] <= _T_385 @[lib.scala 428:17]
+    node _T_386 = bits(twos_comp_in, 18, 0) @[lib.scala 428:27]
+    node _T_387 = orr(_T_386) @[lib.scala 428:35]
+    node _T_388 = bits(twos_comp_in, 19, 19) @[lib.scala 428:44]
+    node _T_389 = not(_T_388) @[lib.scala 428:40]
+    node _T_390 = bits(twos_comp_in, 19, 19) @[lib.scala 428:51]
+    node _T_391 = mux(_T_387, _T_389, _T_390) @[lib.scala 428:23]
+    _T_277[18] <= _T_391 @[lib.scala 428:17]
+    node _T_392 = bits(twos_comp_in, 19, 0) @[lib.scala 428:27]
+    node _T_393 = orr(_T_392) @[lib.scala 428:35]
+    node _T_394 = bits(twos_comp_in, 20, 20) @[lib.scala 428:44]
+    node _T_395 = not(_T_394) @[lib.scala 428:40]
+    node _T_396 = bits(twos_comp_in, 20, 20) @[lib.scala 428:51]
+    node _T_397 = mux(_T_393, _T_395, _T_396) @[lib.scala 428:23]
+    _T_277[19] <= _T_397 @[lib.scala 428:17]
+    node _T_398 = bits(twos_comp_in, 20, 0) @[lib.scala 428:27]
+    node _T_399 = orr(_T_398) @[lib.scala 428:35]
+    node _T_400 = bits(twos_comp_in, 21, 21) @[lib.scala 428:44]
+    node _T_401 = not(_T_400) @[lib.scala 428:40]
+    node _T_402 = bits(twos_comp_in, 21, 21) @[lib.scala 428:51]
+    node _T_403 = mux(_T_399, _T_401, _T_402) @[lib.scala 428:23]
+    _T_277[20] <= _T_403 @[lib.scala 428:17]
+    node _T_404 = bits(twos_comp_in, 21, 0) @[lib.scala 428:27]
+    node _T_405 = orr(_T_404) @[lib.scala 428:35]
+    node _T_406 = bits(twos_comp_in, 22, 22) @[lib.scala 428:44]
+    node _T_407 = not(_T_406) @[lib.scala 428:40]
+    node _T_408 = bits(twos_comp_in, 22, 22) @[lib.scala 428:51]
+    node _T_409 = mux(_T_405, _T_407, _T_408) @[lib.scala 428:23]
+    _T_277[21] <= _T_409 @[lib.scala 428:17]
+    node _T_410 = bits(twos_comp_in, 22, 0) @[lib.scala 428:27]
+    node _T_411 = orr(_T_410) @[lib.scala 428:35]
+    node _T_412 = bits(twos_comp_in, 23, 23) @[lib.scala 428:44]
+    node _T_413 = not(_T_412) @[lib.scala 428:40]
+    node _T_414 = bits(twos_comp_in, 23, 23) @[lib.scala 428:51]
+    node _T_415 = mux(_T_411, _T_413, _T_414) @[lib.scala 428:23]
+    _T_277[22] <= _T_415 @[lib.scala 428:17]
+    node _T_416 = bits(twos_comp_in, 23, 0) @[lib.scala 428:27]
+    node _T_417 = orr(_T_416) @[lib.scala 428:35]
+    node _T_418 = bits(twos_comp_in, 24, 24) @[lib.scala 428:44]
+    node _T_419 = not(_T_418) @[lib.scala 428:40]
+    node _T_420 = bits(twos_comp_in, 24, 24) @[lib.scala 428:51]
+    node _T_421 = mux(_T_417, _T_419, _T_420) @[lib.scala 428:23]
+    _T_277[23] <= _T_421 @[lib.scala 428:17]
+    node _T_422 = bits(twos_comp_in, 24, 0) @[lib.scala 428:27]
+    node _T_423 = orr(_T_422) @[lib.scala 428:35]
+    node _T_424 = bits(twos_comp_in, 25, 25) @[lib.scala 428:44]
+    node _T_425 = not(_T_424) @[lib.scala 428:40]
+    node _T_426 = bits(twos_comp_in, 25, 25) @[lib.scala 428:51]
+    node _T_427 = mux(_T_423, _T_425, _T_426) @[lib.scala 428:23]
+    _T_277[24] <= _T_427 @[lib.scala 428:17]
+    node _T_428 = bits(twos_comp_in, 25, 0) @[lib.scala 428:27]
+    node _T_429 = orr(_T_428) @[lib.scala 428:35]
+    node _T_430 = bits(twos_comp_in, 26, 26) @[lib.scala 428:44]
+    node _T_431 = not(_T_430) @[lib.scala 428:40]
+    node _T_432 = bits(twos_comp_in, 26, 26) @[lib.scala 428:51]
+    node _T_433 = mux(_T_429, _T_431, _T_432) @[lib.scala 428:23]
+    _T_277[25] <= _T_433 @[lib.scala 428:17]
+    node _T_434 = bits(twos_comp_in, 26, 0) @[lib.scala 428:27]
+    node _T_435 = orr(_T_434) @[lib.scala 428:35]
+    node _T_436 = bits(twos_comp_in, 27, 27) @[lib.scala 428:44]
+    node _T_437 = not(_T_436) @[lib.scala 428:40]
+    node _T_438 = bits(twos_comp_in, 27, 27) @[lib.scala 428:51]
+    node _T_439 = mux(_T_435, _T_437, _T_438) @[lib.scala 428:23]
+    _T_277[26] <= _T_439 @[lib.scala 428:17]
+    node _T_440 = bits(twos_comp_in, 27, 0) @[lib.scala 428:27]
+    node _T_441 = orr(_T_440) @[lib.scala 428:35]
+    node _T_442 = bits(twos_comp_in, 28, 28) @[lib.scala 428:44]
+    node _T_443 = not(_T_442) @[lib.scala 428:40]
+    node _T_444 = bits(twos_comp_in, 28, 28) @[lib.scala 428:51]
+    node _T_445 = mux(_T_441, _T_443, _T_444) @[lib.scala 428:23]
+    _T_277[27] <= _T_445 @[lib.scala 428:17]
+    node _T_446 = bits(twos_comp_in, 28, 0) @[lib.scala 428:27]
+    node _T_447 = orr(_T_446) @[lib.scala 428:35]
+    node _T_448 = bits(twos_comp_in, 29, 29) @[lib.scala 428:44]
+    node _T_449 = not(_T_448) @[lib.scala 428:40]
+    node _T_450 = bits(twos_comp_in, 29, 29) @[lib.scala 428:51]
+    node _T_451 = mux(_T_447, _T_449, _T_450) @[lib.scala 428:23]
+    _T_277[28] <= _T_451 @[lib.scala 428:17]
+    node _T_452 = bits(twos_comp_in, 29, 0) @[lib.scala 428:27]
+    node _T_453 = orr(_T_452) @[lib.scala 428:35]
+    node _T_454 = bits(twos_comp_in, 30, 30) @[lib.scala 428:44]
+    node _T_455 = not(_T_454) @[lib.scala 428:40]
+    node _T_456 = bits(twos_comp_in, 30, 30) @[lib.scala 428:51]
+    node _T_457 = mux(_T_453, _T_455, _T_456) @[lib.scala 428:23]
+    _T_277[29] <= _T_457 @[lib.scala 428:17]
+    node _T_458 = bits(twos_comp_in, 30, 0) @[lib.scala 428:27]
+    node _T_459 = orr(_T_458) @[lib.scala 428:35]
+    node _T_460 = bits(twos_comp_in, 31, 31) @[lib.scala 428:44]
+    node _T_461 = not(_T_460) @[lib.scala 428:40]
+    node _T_462 = bits(twos_comp_in, 31, 31) @[lib.scala 428:51]
+    node _T_463 = mux(_T_459, _T_461, _T_462) @[lib.scala 428:23]
+    _T_277[30] <= _T_463 @[lib.scala 428:17]
+    node _T_464 = cat(_T_277[2], _T_277[1]) @[lib.scala 430:14]
+    node _T_465 = cat(_T_464, _T_277[0]) @[lib.scala 430:14]
+    node _T_466 = cat(_T_277[4], _T_277[3]) @[lib.scala 430:14]
+    node _T_467 = cat(_T_277[6], _T_277[5]) @[lib.scala 430:14]
+    node _T_468 = cat(_T_467, _T_466) @[lib.scala 430:14]
+    node _T_469 = cat(_T_468, _T_465) @[lib.scala 430:14]
+    node _T_470 = cat(_T_277[8], _T_277[7]) @[lib.scala 430:14]
+    node _T_471 = cat(_T_277[10], _T_277[9]) @[lib.scala 430:14]
+    node _T_472 = cat(_T_471, _T_470) @[lib.scala 430:14]
+    node _T_473 = cat(_T_277[12], _T_277[11]) @[lib.scala 430:14]
+    node _T_474 = cat(_T_277[14], _T_277[13]) @[lib.scala 430:14]
+    node _T_475 = cat(_T_474, _T_473) @[lib.scala 430:14]
+    node _T_476 = cat(_T_475, _T_472) @[lib.scala 430:14]
+    node _T_477 = cat(_T_476, _T_469) @[lib.scala 430:14]
+    node _T_478 = cat(_T_277[16], _T_277[15]) @[lib.scala 430:14]
+    node _T_479 = cat(_T_277[18], _T_277[17]) @[lib.scala 430:14]
+    node _T_480 = cat(_T_479, _T_478) @[lib.scala 430:14]
+    node _T_481 = cat(_T_277[20], _T_277[19]) @[lib.scala 430:14]
+    node _T_482 = cat(_T_277[22], _T_277[21]) @[lib.scala 430:14]
+    node _T_483 = cat(_T_482, _T_481) @[lib.scala 430:14]
+    node _T_484 = cat(_T_483, _T_480) @[lib.scala 430:14]
+    node _T_485 = cat(_T_277[24], _T_277[23]) @[lib.scala 430:14]
+    node _T_486 = cat(_T_277[26], _T_277[25]) @[lib.scala 430:14]
+    node _T_487 = cat(_T_486, _T_485) @[lib.scala 430:14]
+    node _T_488 = cat(_T_277[28], _T_277[27]) @[lib.scala 430:14]
+    node _T_489 = cat(_T_277[30], _T_277[29]) @[lib.scala 430:14]
+    node _T_490 = cat(_T_489, _T_488) @[lib.scala 430:14]
+    node _T_491 = cat(_T_490, _T_487) @[lib.scala 430:14]
+    node _T_492 = cat(_T_491, _T_484) @[lib.scala 430:14]
+    node _T_493 = cat(_T_492, _T_477) @[lib.scala 430:14]
+    node _T_494 = bits(twos_comp_in, 0, 0) @[lib.scala 430:24]
+    node twos_comp_out = cat(_T_493, _T_494) @[Cat.scala 29:58]
+    node _T_495 = eq(a_shift, UInt<1>("h00")) @[exu_div_ctl.scala 705:6]
+    node _T_496 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 705:17]
+    node _T_497 = and(_T_495, _T_496) @[exu_div_ctl.scala 705:15]
+    node _T_498 = bits(_T_497, 0, 0) @[exu_div_ctl.scala 705:36]
+    node _T_499 = bits(io.dividend_in, 31, 31) @[exu_div_ctl.scala 705:79]
+    node _T_500 = and(io.signed_in, _T_499) @[exu_div_ctl.scala 705:63]
+    node _T_501 = bits(io.dividend_in, 31, 0) @[exu_div_ctl.scala 705:98]
+    node _T_502 = cat(_T_500, _T_501) @[Cat.scala 29:58]
+    node _T_503 = bits(a_ff, 29, 0) @[exu_div_ctl.scala 706:52]
+    node _T_504 = cat(_T_503, UInt<3>("h00")) @[Cat.scala 29:58]
+    node _T_505 = bits(ar_shifted, 32, 0) @[exu_div_ctl.scala 707:54]
+    node _T_506 = mux(_T_498, _T_502, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_507 = mux(a_shift, _T_504, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_508 = mux(shortq_enable_ff, _T_505, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_509 = or(_T_506, _T_507) @[Mux.scala 27:72]
+    node _T_510 = or(_T_509, _T_508) @[Mux.scala 27:72]
+    wire a_in : UInt<33> @[Mux.scala 27:72]
+    a_in <= _T_510 @[Mux.scala 27:72]
+    node _T_511 = eq(b_twos_comp, UInt<1>("h00")) @[exu_div_ctl.scala 710:5]
+    node _T_512 = bits(io.divisor_in, 31, 31) @[exu_div_ctl.scala 710:78]
+    node _T_513 = and(io.signed_in, _T_512) @[exu_div_ctl.scala 710:63]
+    node _T_514 = bits(io.divisor_in, 31, 0) @[exu_div_ctl.scala 710:96]
+    node _T_515 = cat(_T_513, _T_514) @[Cat.scala 29:58]
+    node _T_516 = eq(divisor_sign_ff, UInt<1>("h00")) @[exu_div_ctl.scala 711:49]
+    node _T_517 = bits(twos_comp_out, 31, 0) @[exu_div_ctl.scala 711:79]
+    node _T_518 = cat(_T_516, _T_517) @[Cat.scala 29:58]
+    node _T_519 = mux(_T_511, _T_515, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_520 = mux(b_twos_comp, _T_518, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_521 = or(_T_519, _T_520) @[Mux.scala 27:72]
+    wire b_in : UInt<33> @[Mux.scala 27:72]
+    b_in <= _T_521 @[Mux.scala 27:72]
+    node _T_522 = bits(r_ff, 29, 0) @[exu_div_ctl.scala 716:54]
+    node _T_523 = bits(a_ff, 32, 30) @[exu_div_ctl.scala 716:65]
+    node _T_524 = cat(_T_522, _T_523) @[Cat.scala 29:58]
+    node _T_525 = bits(adder1_out, 32, 0) @[exu_div_ctl.scala 717:57]
+    node _T_526 = bits(adder2_out, 32, 0) @[exu_div_ctl.scala 718:57]
+    node _T_527 = bits(adder3_out, 32, 0) @[exu_div_ctl.scala 719:57]
+    node _T_528 = bits(adder4_out, 32, 0) @[exu_div_ctl.scala 720:57]
+    node _T_529 = bits(adder5_out, 32, 0) @[exu_div_ctl.scala 721:57]
+    node _T_530 = bits(adder6_out, 32, 0) @[exu_div_ctl.scala 722:57]
+    node _T_531 = bits(adder7_out, 32, 0) @[exu_div_ctl.scala 723:57]
+    node _T_532 = bits(ar_shifted, 65, 33) @[exu_div_ctl.scala 724:57]
+    node _T_533 = bits(a_ff, 31, 0) @[exu_div_ctl.scala 725:59]
+    node _T_534 = cat(UInt<1>("h00"), _T_533) @[Cat.scala 29:58]
+    node _T_535 = mux(r_sign_sel, UInt<33>("h01ffffffff"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_536 = mux(r_restore_sel, _T_524, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_537 = mux(r_adder1_sel, _T_525, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_538 = mux(r_adder2_sel, _T_526, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_539 = mux(r_adder3_sel, _T_527, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_540 = mux(r_adder4_sel, _T_528, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_541 = mux(r_adder5_sel, _T_529, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_542 = mux(r_adder6_sel, _T_530, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_543 = mux(r_adder7_sel, _T_531, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_544 = mux(shortq_enable_ff, _T_532, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_545 = mux(by_zero_case, _T_534, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_546 = or(_T_535, _T_536) @[Mux.scala 27:72]
+    node _T_547 = or(_T_546, _T_537) @[Mux.scala 27:72]
+    node _T_548 = or(_T_547, _T_538) @[Mux.scala 27:72]
+    node _T_549 = or(_T_548, _T_539) @[Mux.scala 27:72]
+    node _T_550 = or(_T_549, _T_540) @[Mux.scala 27:72]
+    node _T_551 = or(_T_550, _T_541) @[Mux.scala 27:72]
+    node _T_552 = or(_T_551, _T_542) @[Mux.scala 27:72]
+    node _T_553 = or(_T_552, _T_543) @[Mux.scala 27:72]
+    node _T_554 = or(_T_553, _T_544) @[Mux.scala 27:72]
+    node _T_555 = or(_T_554, _T_545) @[Mux.scala 27:72]
+    wire r_in : UInt<33> @[Mux.scala 27:72]
+    r_in <= _T_555 @[Mux.scala 27:72]
+    node _T_556 = eq(valid_ff, UInt<1>("h00")) @[exu_div_ctl.scala 728:4]
+    node _T_557 = bits(q_ff, 28, 0) @[exu_div_ctl.scala 728:54]
+    node _T_558 = cat(_T_557, quotient_new) @[Cat.scala 29:58]
+    node _T_559 = cat(UInt<28>("h00"), smallnum) @[Cat.scala 29:58]
+    node _T_560 = mux(UInt<1>("h01"), UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_561 = mux(_T_556, _T_558, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_562 = mux(smallnum_case, _T_559, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_563 = mux(by_zero_case, _T_560, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_564 = or(_T_561, _T_562) @[Mux.scala 27:72]
+    node _T_565 = or(_T_564, _T_563) @[Mux.scala 27:72]
+    wire q_in : UInt<32> @[Mux.scala 27:72]
+    q_in <= _T_565 @[Mux.scala 27:72]
+    node _T_566 = eq(io.cancel, UInt<1>("h00")) @[exu_div_ctl.scala 732:31]
+    node _T_567 = and(finish_ff, _T_566) @[exu_div_ctl.scala 732:29]
+    io.valid_out <= _T_567 @[exu_div_ctl.scala 732:16]
+    node _T_568 = eq(rem_ff, UInt<1>("h00")) @[exu_div_ctl.scala 734:6]
+    node _T_569 = eq(twos_comp_q_sel, UInt<1>("h00")) @[exu_div_ctl.scala 734:16]
+    node _T_570 = and(_T_568, _T_569) @[exu_div_ctl.scala 734:14]
+    node _T_571 = bits(_T_570, 0, 0) @[exu_div_ctl.scala 734:40]
+    node _T_572 = bits(r_ff, 31, 0) @[exu_div_ctl.scala 735:48]
+    node _T_573 = mux(_T_571, q_ff, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_574 = mux(rem_ff, _T_572, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_575 = mux(twos_comp_q_sel, twos_comp_out, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_576 = or(_T_573, _T_574) @[Mux.scala 27:72]
+    node _T_577 = or(_T_576, _T_575) @[Mux.scala 27:72]
+    wire _T_578 : UInt<32> @[Mux.scala 27:72]
+    _T_578 <= _T_577 @[Mux.scala 27:72]
+    io.data_out <= _T_578 @[exu_div_ctl.scala 733:15]
+    node _T_579 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 739:58]
+    node _T_580 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 740:75]
+    node _T_581 = eq(_T_580, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_582 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 740:75]
+    node _T_583 = eq(_T_582, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_584 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 740:75]
+    node _T_585 = eq(_T_584, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_586 = and(_T_581, _T_583) @[exu_div_ctl.scala 740:95]
+    node _T_587 = and(_T_586, _T_585) @[exu_div_ctl.scala 740:95]
+    node _T_588 = and(_T_579, _T_587) @[exu_div_ctl.scala 741:11]
+    node _T_589 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 739:58]
+    node _T_590 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 740:75]
+    node _T_591 = eq(_T_590, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_592 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 740:75]
+    node _T_593 = eq(_T_592, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_594 = and(_T_591, _T_593) @[exu_div_ctl.scala 740:95]
+    node _T_595 = and(_T_589, _T_594) @[exu_div_ctl.scala 741:11]
+    node _T_596 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 746:38]
+    node _T_597 = eq(_T_596, UInt<1>("h00")) @[exu_div_ctl.scala 746:33]
+    node _T_598 = and(_T_595, _T_597) @[exu_div_ctl.scala 746:31]
+    node _T_599 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 739:58]
+    node _T_600 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 740:75]
+    node _T_601 = eq(_T_600, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_602 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 740:75]
+    node _T_603 = eq(_T_602, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_604 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 740:75]
+    node _T_605 = eq(_T_604, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_606 = and(_T_601, _T_603) @[exu_div_ctl.scala 740:95]
+    node _T_607 = and(_T_606, _T_605) @[exu_div_ctl.scala 740:95]
+    node _T_608 = and(_T_599, _T_607) @[exu_div_ctl.scala 741:11]
+    node _T_609 = or(_T_598, _T_608) @[exu_div_ctl.scala 746:42]
+    node _T_610 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 739:58]
+    node _T_611 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 739:58]
+    node _T_612 = and(_T_610, _T_611) @[exu_div_ctl.scala 739:95]
+    node _T_613 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 740:75]
+    node _T_614 = eq(_T_613, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_615 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 740:75]
+    node _T_616 = eq(_T_615, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_617 = and(_T_614, _T_616) @[exu_div_ctl.scala 740:95]
+    node _T_618 = and(_T_612, _T_617) @[exu_div_ctl.scala 741:11]
+    node _T_619 = or(_T_609, _T_618) @[exu_div_ctl.scala 746:75]
+    node _T_620 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 739:58]
+    node _T_621 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 740:75]
+    node _T_622 = eq(_T_621, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_623 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 740:75]
+    node _T_624 = eq(_T_623, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_625 = and(_T_622, _T_624) @[exu_div_ctl.scala 740:95]
+    node _T_626 = and(_T_620, _T_625) @[exu_div_ctl.scala 741:11]
+    node _T_627 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 748:38]
+    node _T_628 = eq(_T_627, UInt<1>("h00")) @[exu_div_ctl.scala 748:33]
+    node _T_629 = and(_T_626, _T_628) @[exu_div_ctl.scala 748:31]
+    node _T_630 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 739:58]
+    node _T_631 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 740:75]
+    node _T_632 = eq(_T_631, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_633 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 740:75]
+    node _T_634 = eq(_T_633, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_635 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 740:75]
+    node _T_636 = eq(_T_635, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_637 = and(_T_632, _T_634) @[exu_div_ctl.scala 740:95]
+    node _T_638 = and(_T_637, _T_636) @[exu_div_ctl.scala 740:95]
+    node _T_639 = and(_T_630, _T_638) @[exu_div_ctl.scala 741:11]
+    node _T_640 = or(_T_629, _T_639) @[exu_div_ctl.scala 748:42]
+    node _T_641 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 739:58]
+    node _T_642 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 740:75]
+    node _T_643 = eq(_T_642, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_644 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 740:75]
+    node _T_645 = eq(_T_644, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_646 = and(_T_643, _T_645) @[exu_div_ctl.scala 740:95]
+    node _T_647 = and(_T_641, _T_646) @[exu_div_ctl.scala 741:11]
+    node _T_648 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 748:113]
+    node _T_649 = eq(_T_648, UInt<1>("h00")) @[exu_div_ctl.scala 748:108]
+    node _T_650 = and(_T_647, _T_649) @[exu_div_ctl.scala 748:106]
+    node _T_651 = or(_T_640, _T_650) @[exu_div_ctl.scala 748:78]
+    node _T_652 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 739:58]
+    node _T_653 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 739:75]
+    node _T_654 = eq(_T_653, UInt<1>("h00")) @[exu_div_ctl.scala 739:70]
+    node _T_655 = and(_T_652, _T_654) @[exu_div_ctl.scala 739:95]
+    node _T_656 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 740:75]
+    node _T_657 = eq(_T_656, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_658 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 740:75]
+    node _T_659 = eq(_T_658, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_660 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 740:58]
+    node _T_661 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 740:58]
+    node _T_662 = and(_T_657, _T_659) @[exu_div_ctl.scala 740:95]
+    node _T_663 = and(_T_662, _T_660) @[exu_div_ctl.scala 740:95]
+    node _T_664 = and(_T_663, _T_661) @[exu_div_ctl.scala 740:95]
+    node _T_665 = and(_T_655, _T_664) @[exu_div_ctl.scala 741:11]
+    node _T_666 = or(_T_651, _T_665) @[exu_div_ctl.scala 748:117]
+    node _T_667 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 739:75]
+    node _T_668 = eq(_T_667, UInt<1>("h00")) @[exu_div_ctl.scala 739:70]
+    node _T_669 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 739:58]
+    node _T_670 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 739:58]
+    node _T_671 = and(_T_668, _T_669) @[exu_div_ctl.scala 739:95]
+    node _T_672 = and(_T_671, _T_670) @[exu_div_ctl.scala 739:95]
+    node _T_673 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 740:75]
+    node _T_674 = eq(_T_673, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_675 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 740:75]
+    node _T_676 = eq(_T_675, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_677 = and(_T_674, _T_676) @[exu_div_ctl.scala 740:95]
+    node _T_678 = and(_T_672, _T_677) @[exu_div_ctl.scala 741:11]
+    node _T_679 = or(_T_666, _T_678) @[exu_div_ctl.scala 749:44]
+    node _T_680 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 739:58]
+    node _T_681 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 739:58]
+    node _T_682 = and(_T_680, _T_681) @[exu_div_ctl.scala 739:95]
+    node _T_683 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 740:75]
+    node _T_684 = eq(_T_683, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_685 = and(_T_682, _T_684) @[exu_div_ctl.scala 741:11]
+    node _T_686 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 749:114]
+    node _T_687 = eq(_T_686, UInt<1>("h00")) @[exu_div_ctl.scala 749:109]
+    node _T_688 = and(_T_685, _T_687) @[exu_div_ctl.scala 749:107]
+    node _T_689 = or(_T_679, _T_688) @[exu_div_ctl.scala 749:80]
+    node _T_690 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 739:58]
+    node _T_691 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 739:58]
+    node _T_692 = and(_T_690, _T_691) @[exu_div_ctl.scala 739:95]
+    node _T_693 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 740:75]
+    node _T_694 = eq(_T_693, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_695 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 740:58]
+    node _T_696 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 740:75]
+    node _T_697 = eq(_T_696, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_698 = and(_T_694, _T_695) @[exu_div_ctl.scala 740:95]
+    node _T_699 = and(_T_698, _T_697) @[exu_div_ctl.scala 740:95]
+    node _T_700 = and(_T_692, _T_699) @[exu_div_ctl.scala 741:11]
+    node _T_701 = or(_T_689, _T_700) @[exu_div_ctl.scala 749:119]
+    node _T_702 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 739:58]
+    node _T_703 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 739:58]
+    node _T_704 = and(_T_702, _T_703) @[exu_div_ctl.scala 739:95]
+    node _T_705 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 740:75]
+    node _T_706 = eq(_T_705, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_707 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 740:75]
+    node _T_708 = eq(_T_707, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_709 = and(_T_706, _T_708) @[exu_div_ctl.scala 740:95]
+    node _T_710 = and(_T_704, _T_709) @[exu_div_ctl.scala 741:11]
+    node _T_711 = or(_T_701, _T_710) @[exu_div_ctl.scala 750:44]
+    node _T_712 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 739:58]
+    node _T_713 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 739:58]
+    node _T_714 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 739:58]
+    node _T_715 = and(_T_712, _T_713) @[exu_div_ctl.scala 739:95]
+    node _T_716 = and(_T_715, _T_714) @[exu_div_ctl.scala 739:95]
+    node _T_717 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 740:75]
+    node _T_718 = eq(_T_717, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_719 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 740:58]
+    node _T_720 = and(_T_718, _T_719) @[exu_div_ctl.scala 740:95]
+    node _T_721 = and(_T_716, _T_720) @[exu_div_ctl.scala 741:11]
+    node _T_722 = or(_T_711, _T_721) @[exu_div_ctl.scala 750:79]
+    node _T_723 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 739:58]
+    node _T_724 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 739:58]
+    node _T_725 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 739:58]
+    node _T_726 = and(_T_723, _T_724) @[exu_div_ctl.scala 739:95]
+    node _T_727 = and(_T_726, _T_725) @[exu_div_ctl.scala 739:95]
+    node _T_728 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 740:75]
+    node _T_729 = eq(_T_728, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_730 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 740:75]
+    node _T_731 = eq(_T_730, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_732 = and(_T_729, _T_731) @[exu_div_ctl.scala 740:95]
+    node _T_733 = and(_T_727, _T_732) @[exu_div_ctl.scala 741:11]
+    node _T_734 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 739:58]
+    node _T_735 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 739:75]
+    node _T_736 = eq(_T_735, UInt<1>("h00")) @[exu_div_ctl.scala 739:70]
+    node _T_737 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 739:58]
+    node _T_738 = and(_T_734, _T_736) @[exu_div_ctl.scala 739:95]
+    node _T_739 = and(_T_738, _T_737) @[exu_div_ctl.scala 739:95]
+    node _T_740 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 740:75]
+    node _T_741 = eq(_T_740, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_742 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 740:58]
+    node _T_743 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 740:58]
+    node _T_744 = and(_T_741, _T_742) @[exu_div_ctl.scala 740:95]
+    node _T_745 = and(_T_744, _T_743) @[exu_div_ctl.scala 740:95]
+    node _T_746 = and(_T_739, _T_745) @[exu_div_ctl.scala 741:11]
+    node _T_747 = or(_T_733, _T_746) @[exu_div_ctl.scala 752:45]
+    node _T_748 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 739:58]
+    node _T_749 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 740:75]
+    node _T_750 = eq(_T_749, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_751 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 740:75]
+    node _T_752 = eq(_T_751, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_753 = and(_T_750, _T_752) @[exu_div_ctl.scala 740:95]
+    node _T_754 = and(_T_748, _T_753) @[exu_div_ctl.scala 741:11]
+    node _T_755 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 752:121]
+    node _T_756 = eq(_T_755, UInt<1>("h00")) @[exu_div_ctl.scala 752:116]
+    node _T_757 = and(_T_754, _T_756) @[exu_div_ctl.scala 752:114]
+    node _T_758 = or(_T_747, _T_757) @[exu_div_ctl.scala 752:86]
+    node _T_759 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 739:58]
+    node _T_760 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 740:75]
+    node _T_761 = eq(_T_760, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_762 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 740:75]
+    node _T_763 = eq(_T_762, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_764 = and(_T_761, _T_763) @[exu_div_ctl.scala 740:95]
+    node _T_765 = and(_T_759, _T_764) @[exu_div_ctl.scala 741:11]
+    node _T_766 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 753:40]
+    node _T_767 = eq(_T_766, UInt<1>("h00")) @[exu_div_ctl.scala 753:35]
+    node _T_768 = and(_T_765, _T_767) @[exu_div_ctl.scala 753:33]
+    node _T_769 = or(_T_758, _T_768) @[exu_div_ctl.scala 752:129]
+    node _T_770 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 739:58]
+    node _T_771 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 740:75]
+    node _T_772 = eq(_T_771, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_773 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 740:75]
+    node _T_774 = eq(_T_773, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_775 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 740:75]
+    node _T_776 = eq(_T_775, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_777 = and(_T_772, _T_774) @[exu_div_ctl.scala 740:95]
+    node _T_778 = and(_T_777, _T_776) @[exu_div_ctl.scala 740:95]
+    node _T_779 = and(_T_770, _T_778) @[exu_div_ctl.scala 741:11]
+    node _T_780 = or(_T_769, _T_779) @[exu_div_ctl.scala 753:47]
+    node _T_781 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 739:75]
+    node _T_782 = eq(_T_781, UInt<1>("h00")) @[exu_div_ctl.scala 739:70]
+    node _T_783 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 739:58]
+    node _T_784 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 739:75]
+    node _T_785 = eq(_T_784, UInt<1>("h00")) @[exu_div_ctl.scala 739:70]
+    node _T_786 = and(_T_782, _T_783) @[exu_div_ctl.scala 739:95]
+    node _T_787 = and(_T_786, _T_785) @[exu_div_ctl.scala 739:95]
+    node _T_788 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 740:75]
+    node _T_789 = eq(_T_788, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_790 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 740:75]
+    node _T_791 = eq(_T_790, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_792 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 740:58]
+    node _T_793 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 740:58]
+    node _T_794 = and(_T_789, _T_791) @[exu_div_ctl.scala 740:95]
+    node _T_795 = and(_T_794, _T_792) @[exu_div_ctl.scala 740:95]
+    node _T_796 = and(_T_795, _T_793) @[exu_div_ctl.scala 740:95]
+    node _T_797 = and(_T_787, _T_796) @[exu_div_ctl.scala 741:11]
+    node _T_798 = or(_T_780, _T_797) @[exu_div_ctl.scala 753:88]
+    node _T_799 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 739:75]
+    node _T_800 = eq(_T_799, UInt<1>("h00")) @[exu_div_ctl.scala 739:70]
+    node _T_801 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 739:58]
+    node _T_802 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 739:58]
+    node _T_803 = and(_T_800, _T_801) @[exu_div_ctl.scala 739:95]
+    node _T_804 = and(_T_803, _T_802) @[exu_div_ctl.scala 739:95]
+    node _T_805 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 740:75]
+    node _T_806 = eq(_T_805, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_807 = and(_T_804, _T_806) @[exu_div_ctl.scala 741:11]
+    node _T_808 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 754:43]
+    node _T_809 = eq(_T_808, UInt<1>("h00")) @[exu_div_ctl.scala 754:38]
+    node _T_810 = and(_T_807, _T_809) @[exu_div_ctl.scala 754:36]
+    node _T_811 = or(_T_798, _T_810) @[exu_div_ctl.scala 753:131]
+    node _T_812 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 739:58]
+    node _T_813 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 740:75]
+    node _T_814 = eq(_T_813, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_815 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 740:75]
+    node _T_816 = eq(_T_815, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_817 = and(_T_814, _T_816) @[exu_div_ctl.scala 740:95]
+    node _T_818 = and(_T_812, _T_817) @[exu_div_ctl.scala 741:11]
+    node _T_819 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 754:83]
+    node _T_820 = eq(_T_819, UInt<1>("h00")) @[exu_div_ctl.scala 754:78]
+    node _T_821 = and(_T_818, _T_820) @[exu_div_ctl.scala 754:76]
+    node _T_822 = or(_T_811, _T_821) @[exu_div_ctl.scala 754:47]
+    node _T_823 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 739:58]
+    node _T_824 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 739:75]
+    node _T_825 = eq(_T_824, UInt<1>("h00")) @[exu_div_ctl.scala 739:70]
+    node _T_826 = and(_T_823, _T_825) @[exu_div_ctl.scala 739:95]
+    node _T_827 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 740:75]
+    node _T_828 = eq(_T_827, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_829 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 740:58]
+    node _T_830 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 740:58]
+    node _T_831 = and(_T_828, _T_829) @[exu_div_ctl.scala 740:95]
+    node _T_832 = and(_T_831, _T_830) @[exu_div_ctl.scala 740:95]
+    node _T_833 = and(_T_826, _T_832) @[exu_div_ctl.scala 741:11]
+    node _T_834 = or(_T_822, _T_833) @[exu_div_ctl.scala 754:88]
+    node _T_835 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 739:75]
+    node _T_836 = eq(_T_835, UInt<1>("h00")) @[exu_div_ctl.scala 739:70]
+    node _T_837 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 739:58]
+    node _T_838 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 739:58]
+    node _T_839 = and(_T_836, _T_837) @[exu_div_ctl.scala 739:95]
+    node _T_840 = and(_T_839, _T_838) @[exu_div_ctl.scala 739:95]
+    node _T_841 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 740:75]
+    node _T_842 = eq(_T_841, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_843 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 740:58]
+    node _T_844 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 740:75]
+    node _T_845 = eq(_T_844, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_846 = and(_T_842, _T_843) @[exu_div_ctl.scala 740:95]
+    node _T_847 = and(_T_846, _T_845) @[exu_div_ctl.scala 740:95]
+    node _T_848 = and(_T_840, _T_847) @[exu_div_ctl.scala 741:11]
+    node _T_849 = or(_T_834, _T_848) @[exu_div_ctl.scala 754:131]
+    node _T_850 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 739:75]
+    node _T_851 = eq(_T_850, UInt<1>("h00")) @[exu_div_ctl.scala 739:70]
+    node _T_852 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 739:58]
+    node _T_853 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 739:58]
+    node _T_854 = and(_T_851, _T_852) @[exu_div_ctl.scala 739:95]
+    node _T_855 = and(_T_854, _T_853) @[exu_div_ctl.scala 739:95]
+    node _T_856 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 740:75]
+    node _T_857 = eq(_T_856, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_858 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 740:75]
+    node _T_859 = eq(_T_858, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_860 = and(_T_857, _T_859) @[exu_div_ctl.scala 740:95]
+    node _T_861 = and(_T_855, _T_860) @[exu_div_ctl.scala 741:11]
+    node _T_862 = or(_T_849, _T_861) @[exu_div_ctl.scala 755:47]
+    node _T_863 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 739:58]
+    node _T_864 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 739:75]
+    node _T_865 = eq(_T_864, UInt<1>("h00")) @[exu_div_ctl.scala 739:70]
+    node _T_866 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 739:75]
+    node _T_867 = eq(_T_866, UInt<1>("h00")) @[exu_div_ctl.scala 739:70]
+    node _T_868 = and(_T_863, _T_865) @[exu_div_ctl.scala 739:95]
+    node _T_869 = and(_T_868, _T_867) @[exu_div_ctl.scala 739:95]
+    node _T_870 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 740:75]
+    node _T_871 = eq(_T_870, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_872 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 740:58]
+    node _T_873 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 740:58]
+    node _T_874 = and(_T_871, _T_872) @[exu_div_ctl.scala 740:95]
+    node _T_875 = and(_T_874, _T_873) @[exu_div_ctl.scala 740:95]
+    node _T_876 = and(_T_869, _T_875) @[exu_div_ctl.scala 741:11]
+    node _T_877 = or(_T_862, _T_876) @[exu_div_ctl.scala 755:88]
+    node _T_878 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 739:75]
+    node _T_879 = eq(_T_878, UInt<1>("h00")) @[exu_div_ctl.scala 739:70]
+    node _T_880 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 739:58]
+    node _T_881 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 739:58]
+    node _T_882 = and(_T_879, _T_880) @[exu_div_ctl.scala 739:95]
+    node _T_883 = and(_T_882, _T_881) @[exu_div_ctl.scala 739:95]
+    node _T_884 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 740:75]
+    node _T_885 = eq(_T_884, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_886 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 740:75]
+    node _T_887 = eq(_T_886, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_888 = and(_T_885, _T_887) @[exu_div_ctl.scala 740:95]
+    node _T_889 = and(_T_883, _T_888) @[exu_div_ctl.scala 741:11]
+    node _T_890 = or(_T_877, _T_889) @[exu_div_ctl.scala 755:131]
+    node _T_891 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 739:58]
+    node _T_892 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 739:58]
+    node _T_893 = and(_T_891, _T_892) @[exu_div_ctl.scala 739:95]
+    node _T_894 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 740:75]
+    node _T_895 = eq(_T_894, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_896 = and(_T_893, _T_895) @[exu_div_ctl.scala 741:11]
+    node _T_897 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 756:82]
+    node _T_898 = eq(_T_897, UInt<1>("h00")) @[exu_div_ctl.scala 756:77]
+    node _T_899 = and(_T_896, _T_898) @[exu_div_ctl.scala 756:75]
+    node _T_900 = or(_T_890, _T_899) @[exu_div_ctl.scala 756:47]
+    node _T_901 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 739:75]
+    node _T_902 = eq(_T_901, UInt<1>("h00")) @[exu_div_ctl.scala 739:70]
+    node _T_903 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 739:58]
+    node _T_904 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 739:58]
+    node _T_905 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 739:58]
+    node _T_906 = and(_T_902, _T_903) @[exu_div_ctl.scala 739:95]
+    node _T_907 = and(_T_906, _T_904) @[exu_div_ctl.scala 739:95]
+    node _T_908 = and(_T_907, _T_905) @[exu_div_ctl.scala 739:95]
+    node _T_909 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 740:75]
+    node _T_910 = eq(_T_909, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_911 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 740:58]
+    node _T_912 = and(_T_910, _T_911) @[exu_div_ctl.scala 740:95]
+    node _T_913 = and(_T_908, _T_912) @[exu_div_ctl.scala 741:11]
+    node _T_914 = or(_T_900, _T_913) @[exu_div_ctl.scala 756:88]
+    node _T_915 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 739:58]
+    node _T_916 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 739:58]
+    node _T_917 = and(_T_915, _T_916) @[exu_div_ctl.scala 739:95]
+    node _T_918 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 740:58]
+    node _T_919 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 740:75]
+    node _T_920 = eq(_T_919, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_921 = and(_T_918, _T_920) @[exu_div_ctl.scala 740:95]
+    node _T_922 = and(_T_917, _T_921) @[exu_div_ctl.scala 741:11]
+    node _T_923 = or(_T_914, _T_922) @[exu_div_ctl.scala 756:131]
+    node _T_924 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 739:58]
+    node _T_925 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 739:58]
+    node _T_926 = and(_T_924, _T_925) @[exu_div_ctl.scala 739:95]
+    node _T_927 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 740:58]
+    node _T_928 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 740:75]
+    node _T_929 = eq(_T_928, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_930 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 740:75]
+    node _T_931 = eq(_T_930, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_932 = and(_T_927, _T_929) @[exu_div_ctl.scala 740:95]
+    node _T_933 = and(_T_932, _T_931) @[exu_div_ctl.scala 740:95]
+    node _T_934 = and(_T_926, _T_933) @[exu_div_ctl.scala 741:11]
+    node _T_935 = or(_T_923, _T_934) @[exu_div_ctl.scala 757:47]
+    node _T_936 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 739:58]
+    node _T_937 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 739:58]
+    node _T_938 = and(_T_936, _T_937) @[exu_div_ctl.scala 739:95]
+    node _T_939 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 740:75]
+    node _T_940 = eq(_T_939, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_941 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 740:75]
+    node _T_942 = eq(_T_941, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_943 = and(_T_940, _T_942) @[exu_div_ctl.scala 740:95]
+    node _T_944 = and(_T_938, _T_943) @[exu_div_ctl.scala 741:11]
+    node _T_945 = or(_T_935, _T_944) @[exu_div_ctl.scala 757:88]
+    node _T_946 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 739:58]
+    node _T_947 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 739:75]
+    node _T_948 = eq(_T_947, UInt<1>("h00")) @[exu_div_ctl.scala 739:70]
+    node _T_949 = and(_T_946, _T_948) @[exu_div_ctl.scala 739:95]
+    node _T_950 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 740:75]
+    node _T_951 = eq(_T_950, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_952 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 740:58]
+    node _T_953 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 740:58]
+    node _T_954 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 740:58]
+    node _T_955 = and(_T_951, _T_952) @[exu_div_ctl.scala 740:95]
+    node _T_956 = and(_T_955, _T_953) @[exu_div_ctl.scala 740:95]
+    node _T_957 = and(_T_956, _T_954) @[exu_div_ctl.scala 740:95]
+    node _T_958 = and(_T_949, _T_957) @[exu_div_ctl.scala 741:11]
+    node _T_959 = or(_T_945, _T_958) @[exu_div_ctl.scala 757:131]
+    node _T_960 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 739:58]
+    node _T_961 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 739:58]
+    node _T_962 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 739:58]
+    node _T_963 = and(_T_960, _T_961) @[exu_div_ctl.scala 739:95]
+    node _T_964 = and(_T_963, _T_962) @[exu_div_ctl.scala 739:95]
+    node _T_965 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 740:58]
+    node _T_966 = and(_T_964, _T_965) @[exu_div_ctl.scala 741:11]
+    node _T_967 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 758:84]
+    node _T_968 = eq(_T_967, UInt<1>("h00")) @[exu_div_ctl.scala 758:79]
+    node _T_969 = and(_T_966, _T_968) @[exu_div_ctl.scala 758:77]
+    node _T_970 = or(_T_959, _T_969) @[exu_div_ctl.scala 758:47]
+    node _T_971 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 739:58]
+    node _T_972 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 739:58]
+    node _T_973 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 739:58]
+    node _T_974 = and(_T_971, _T_972) @[exu_div_ctl.scala 739:95]
+    node _T_975 = and(_T_974, _T_973) @[exu_div_ctl.scala 739:95]
+    node _T_976 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 740:58]
+    node _T_977 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 740:75]
+    node _T_978 = eq(_T_977, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_979 = and(_T_976, _T_978) @[exu_div_ctl.scala 740:95]
+    node _T_980 = and(_T_975, _T_979) @[exu_div_ctl.scala 741:11]
+    node _T_981 = or(_T_970, _T_980) @[exu_div_ctl.scala 758:88]
+    node _T_982 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 739:58]
+    node _T_983 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 739:58]
+    node _T_984 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 739:58]
+    node _T_985 = and(_T_982, _T_983) @[exu_div_ctl.scala 739:95]
+    node _T_986 = and(_T_985, _T_984) @[exu_div_ctl.scala 739:95]
+    node _T_987 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 740:58]
+    node _T_988 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 740:75]
+    node _T_989 = eq(_T_988, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_990 = and(_T_987, _T_989) @[exu_div_ctl.scala 740:95]
+    node _T_991 = and(_T_986, _T_990) @[exu_div_ctl.scala 741:11]
+    node _T_992 = or(_T_981, _T_991) @[exu_div_ctl.scala 758:131]
+    node _T_993 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 739:58]
+    node _T_994 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 739:75]
+    node _T_995 = eq(_T_994, UInt<1>("h00")) @[exu_div_ctl.scala 739:70]
+    node _T_996 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 739:58]
+    node _T_997 = and(_T_993, _T_995) @[exu_div_ctl.scala 739:95]
+    node _T_998 = and(_T_997, _T_996) @[exu_div_ctl.scala 739:95]
+    node _T_999 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 740:75]
+    node _T_1000 = eq(_T_999, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_1001 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 740:58]
+    node _T_1002 = and(_T_1000, _T_1001) @[exu_div_ctl.scala 740:95]
+    node _T_1003 = and(_T_998, _T_1002) @[exu_div_ctl.scala 741:11]
+    node _T_1004 = or(_T_992, _T_1003) @[exu_div_ctl.scala 759:47]
+    node _T_1005 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 739:58]
+    node _T_1006 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 739:58]
+    node _T_1007 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 739:58]
+    node _T_1008 = and(_T_1005, _T_1006) @[exu_div_ctl.scala 739:95]
+    node _T_1009 = and(_T_1008, _T_1007) @[exu_div_ctl.scala 739:95]
+    node _T_1010 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 740:75]
+    node _T_1011 = eq(_T_1010, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_1012 = and(_T_1009, _T_1011) @[exu_div_ctl.scala 741:11]
+    node _T_1013 = or(_T_1004, _T_1012) @[exu_div_ctl.scala 759:88]
+    node _T_1014 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 739:58]
+    node _T_1015 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 739:58]
+    node _T_1016 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 739:58]
+    node _T_1017 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 739:58]
+    node _T_1018 = and(_T_1014, _T_1015) @[exu_div_ctl.scala 739:95]
+    node _T_1019 = and(_T_1018, _T_1016) @[exu_div_ctl.scala 739:95]
+    node _T_1020 = and(_T_1019, _T_1017) @[exu_div_ctl.scala 739:95]
+    node _T_1021 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 740:58]
+    node _T_1022 = and(_T_1020, _T_1021) @[exu_div_ctl.scala 741:11]
+    node _T_1023 = or(_T_1013, _T_1022) @[exu_div_ctl.scala 759:131]
+    node _T_1024 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 739:58]
+    node _T_1025 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 739:58]
+    node _T_1026 = and(_T_1024, _T_1025) @[exu_div_ctl.scala 739:95]
+    node _T_1027 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 740:75]
+    node _T_1028 = eq(_T_1027, UInt<1>("h00")) @[exu_div_ctl.scala 740:70]
+    node _T_1029 = and(_T_1026, _T_1028) @[exu_div_ctl.scala 741:11]
+    node _T_1030 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 760:81]
+    node _T_1031 = eq(_T_1030, UInt<1>("h00")) @[exu_div_ctl.scala 760:76]
+    node _T_1032 = and(_T_1029, _T_1031) @[exu_div_ctl.scala 760:74]
+    node _T_1033 = or(_T_1023, _T_1032) @[exu_div_ctl.scala 760:47]
+    node _T_1034 = cat(_T_722, _T_1033) @[Cat.scala 29:58]
+    node _T_1035 = cat(_T_588, _T_619) @[Cat.scala 29:58]
+    node _T_1036 = cat(_T_1035, _T_1034) @[Cat.scala 29:58]
+    smallnum <= _T_1036 @[exu_div_ctl.scala 743:12]
+    node shortq_dividend = cat(dividend_sign_ff, a_ff) @[Cat.scala 29:58]
+    inst a_enc of exu_div_cls @[exu_div_ctl.scala 763:21]
+    a_enc.clock <= clock
+    a_enc.reset <= reset
+    a_enc.io.operand <= shortq_dividend @[exu_div_ctl.scala 764:20]
+    inst b_enc of exu_div_cls_1 @[exu_div_ctl.scala 766:20]
+    b_enc.clock <= clock
+    b_enc.reset <= reset
+    node _T_1037 = bits(b_ff, 32, 0) @[exu_div_ctl.scala 767:27]
+    b_enc.io.operand <= _T_1037 @[exu_div_ctl.scala 767:20]
+    node dw_a_enc = cat(UInt<1>("h00"), a_enc.io.cls) @[Cat.scala 29:58]
+    node dw_b_enc = cat(UInt<1>("h00"), b_enc.io.cls) @[Cat.scala 29:58]
+    node _T_1038 = cat(UInt<1>("h00"), dw_b_enc) @[Cat.scala 29:58]
+    node _T_1039 = cat(UInt<1>("h00"), dw_a_enc) @[Cat.scala 29:58]
+    node _T_1040 = sub(_T_1038, _T_1039) @[exu_div_ctl.scala 771:41]
+    node _T_1041 = tail(_T_1040, 1) @[exu_div_ctl.scala 771:41]
+    node _T_1042 = add(_T_1041, UInt<7>("h01")) @[exu_div_ctl.scala 771:61]
+    node dw_shortq_raw = tail(_T_1042, 1) @[exu_div_ctl.scala 771:61]
+    node _T_1043 = bits(dw_shortq_raw, 6, 6) @[exu_div_ctl.scala 772:33]
+    node _T_1044 = bits(_T_1043, 0, 0) @[exu_div_ctl.scala 772:43]
+    node _T_1045 = bits(dw_shortq_raw, 5, 0) @[exu_div_ctl.scala 772:63]
+    node shortq = mux(_T_1044, UInt<1>("h00"), _T_1045) @[exu_div_ctl.scala 772:19]
+    node _T_1046 = bits(shortq, 5, 5) @[exu_div_ctl.scala 773:38]
+    node _T_1047 = eq(_T_1046, UInt<1>("h00")) @[exu_div_ctl.scala 773:31]
+    node _T_1048 = and(valid_ff, _T_1047) @[exu_div_ctl.scala 773:29]
+    node _T_1049 = bits(shortq, 4, 2) @[exu_div_ctl.scala 773:52]
+    node _T_1050 = eq(_T_1049, UInt<3>("h07")) @[exu_div_ctl.scala 773:58]
+    node _T_1051 = eq(_T_1050, UInt<1>("h00")) @[exu_div_ctl.scala 773:44]
+    node _T_1052 = and(_T_1048, _T_1051) @[exu_div_ctl.scala 773:42]
+    node _T_1053 = eq(io.cancel, UInt<1>("h00")) @[exu_div_ctl.scala 773:75]
+    node _T_1054 = and(_T_1052, _T_1053) @[exu_div_ctl.scala 773:73]
+    shortq_enable <= _T_1054 @[exu_div_ctl.scala 773:17]
+    node _T_1055 = eq(shortq, UInt<5>("h01f")) @[exu_div_ctl.scala 775:58]
+    node _T_1056 = eq(shortq, UInt<5>("h01e")) @[exu_div_ctl.scala 775:58]
+    node _T_1057 = eq(shortq, UInt<5>("h01d")) @[exu_div_ctl.scala 775:58]
+    node _T_1058 = eq(shortq, UInt<5>("h01c")) @[exu_div_ctl.scala 775:58]
+    node _T_1059 = eq(shortq, UInt<5>("h01b")) @[exu_div_ctl.scala 775:58]
+    node _T_1060 = eq(shortq, UInt<5>("h01a")) @[exu_div_ctl.scala 775:58]
+    node _T_1061 = eq(shortq, UInt<5>("h019")) @[exu_div_ctl.scala 775:58]
+    node _T_1062 = eq(shortq, UInt<5>("h018")) @[exu_div_ctl.scala 775:58]
+    node _T_1063 = eq(shortq, UInt<5>("h017")) @[exu_div_ctl.scala 775:58]
+    node _T_1064 = eq(shortq, UInt<5>("h016")) @[exu_div_ctl.scala 775:58]
+    node _T_1065 = eq(shortq, UInt<5>("h015")) @[exu_div_ctl.scala 775:58]
+    node _T_1066 = eq(shortq, UInt<5>("h014")) @[exu_div_ctl.scala 775:58]
+    node _T_1067 = eq(shortq, UInt<5>("h013")) @[exu_div_ctl.scala 775:58]
+    node _T_1068 = eq(shortq, UInt<5>("h012")) @[exu_div_ctl.scala 775:58]
+    node _T_1069 = eq(shortq, UInt<5>("h011")) @[exu_div_ctl.scala 775:58]
+    node _T_1070 = eq(shortq, UInt<5>("h010")) @[exu_div_ctl.scala 775:58]
+    node _T_1071 = eq(shortq, UInt<4>("h0f")) @[exu_div_ctl.scala 775:58]
+    node _T_1072 = eq(shortq, UInt<4>("h0e")) @[exu_div_ctl.scala 775:58]
+    node _T_1073 = eq(shortq, UInt<4>("h0d")) @[exu_div_ctl.scala 775:58]
+    node _T_1074 = eq(shortq, UInt<4>("h0c")) @[exu_div_ctl.scala 775:58]
+    node _T_1075 = eq(shortq, UInt<4>("h0b")) @[exu_div_ctl.scala 775:58]
+    node _T_1076 = eq(shortq, UInt<4>("h0a")) @[exu_div_ctl.scala 775:58]
+    node _T_1077 = eq(shortq, UInt<4>("h09")) @[exu_div_ctl.scala 775:58]
+    node _T_1078 = eq(shortq, UInt<4>("h08")) @[exu_div_ctl.scala 775:58]
+    node _T_1079 = eq(shortq, UInt<3>("h07")) @[exu_div_ctl.scala 775:58]
+    node _T_1080 = eq(shortq, UInt<3>("h06")) @[exu_div_ctl.scala 775:58]
+    node _T_1081 = eq(shortq, UInt<3>("h05")) @[exu_div_ctl.scala 775:58]
+    node _T_1082 = eq(shortq, UInt<3>("h04")) @[exu_div_ctl.scala 775:58]
+    node _T_1083 = eq(shortq, UInt<2>("h03")) @[exu_div_ctl.scala 775:58]
+    node _T_1084 = eq(shortq, UInt<2>("h02")) @[exu_div_ctl.scala 775:58]
+    node _T_1085 = eq(shortq, UInt<1>("h01")) @[exu_div_ctl.scala 775:58]
+    node _T_1086 = eq(shortq, UInt<1>("h00")) @[exu_div_ctl.scala 775:58]
+    node _T_1087 = mux(_T_1055, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1088 = mux(_T_1056, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1089 = mux(_T_1057, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1090 = mux(_T_1058, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1091 = mux(_T_1059, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1092 = mux(_T_1060, UInt<3>("h06"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1093 = mux(_T_1061, UInt<3>("h06"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1094 = mux(_T_1062, UInt<3>("h06"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1095 = mux(_T_1063, UInt<4>("h09"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1096 = mux(_T_1064, UInt<4>("h09"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1097 = mux(_T_1065, UInt<4>("h09"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1098 = mux(_T_1066, UInt<4>("h0c"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1099 = mux(_T_1067, UInt<4>("h0c"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1100 = mux(_T_1068, UInt<4>("h0c"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1101 = mux(_T_1069, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1102 = mux(_T_1070, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1103 = mux(_T_1071, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1104 = mux(_T_1072, UInt<5>("h012"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1105 = mux(_T_1073, UInt<5>("h012"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1106 = mux(_T_1074, UInt<5>("h012"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1107 = mux(_T_1075, UInt<5>("h015"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1108 = mux(_T_1076, UInt<5>("h015"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1109 = mux(_T_1077, UInt<5>("h015"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1110 = mux(_T_1078, UInt<5>("h018"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1111 = mux(_T_1079, UInt<5>("h018"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1112 = mux(_T_1080, UInt<5>("h018"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1113 = mux(_T_1081, UInt<5>("h01b"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1114 = mux(_T_1082, UInt<5>("h01b"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1115 = mux(_T_1083, UInt<5>("h01b"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1116 = mux(_T_1084, UInt<5>("h01b"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1117 = mux(_T_1085, UInt<5>("h01b"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1118 = mux(_T_1086, UInt<5>("h01b"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1119 = or(_T_1087, _T_1088) @[Mux.scala 27:72]
+    node _T_1120 = or(_T_1119, _T_1089) @[Mux.scala 27:72]
+    node _T_1121 = or(_T_1120, _T_1090) @[Mux.scala 27:72]
+    node _T_1122 = or(_T_1121, _T_1091) @[Mux.scala 27:72]
+    node _T_1123 = or(_T_1122, _T_1092) @[Mux.scala 27:72]
+    node _T_1124 = or(_T_1123, _T_1093) @[Mux.scala 27:72]
+    node _T_1125 = or(_T_1124, _T_1094) @[Mux.scala 27:72]
+    node _T_1126 = or(_T_1125, _T_1095) @[Mux.scala 27:72]
+    node _T_1127 = or(_T_1126, _T_1096) @[Mux.scala 27:72]
+    node _T_1128 = or(_T_1127, _T_1097) @[Mux.scala 27:72]
+    node _T_1129 = or(_T_1128, _T_1098) @[Mux.scala 27:72]
+    node _T_1130 = or(_T_1129, _T_1099) @[Mux.scala 27:72]
+    node _T_1131 = or(_T_1130, _T_1100) @[Mux.scala 27:72]
+    node _T_1132 = or(_T_1131, _T_1101) @[Mux.scala 27:72]
+    node _T_1133 = or(_T_1132, _T_1102) @[Mux.scala 27:72]
+    node _T_1134 = or(_T_1133, _T_1103) @[Mux.scala 27:72]
+    node _T_1135 = or(_T_1134, _T_1104) @[Mux.scala 27:72]
+    node _T_1136 = or(_T_1135, _T_1105) @[Mux.scala 27:72]
+    node _T_1137 = or(_T_1136, _T_1106) @[Mux.scala 27:72]
+    node _T_1138 = or(_T_1137, _T_1107) @[Mux.scala 27:72]
+    node _T_1139 = or(_T_1138, _T_1108) @[Mux.scala 27:72]
+    node _T_1140 = or(_T_1139, _T_1109) @[Mux.scala 27:72]
+    node _T_1141 = or(_T_1140, _T_1110) @[Mux.scala 27:72]
+    node _T_1142 = or(_T_1141, _T_1111) @[Mux.scala 27:72]
+    node _T_1143 = or(_T_1142, _T_1112) @[Mux.scala 27:72]
+    node _T_1144 = or(_T_1143, _T_1113) @[Mux.scala 27:72]
+    node _T_1145 = or(_T_1144, _T_1114) @[Mux.scala 27:72]
+    node _T_1146 = or(_T_1145, _T_1115) @[Mux.scala 27:72]
+    node _T_1147 = or(_T_1146, _T_1116) @[Mux.scala 27:72]
+    node _T_1148 = or(_T_1147, _T_1117) @[Mux.scala 27:72]
+    node _T_1149 = or(_T_1148, _T_1118) @[Mux.scala 27:72]
+    wire _T_1150 : UInt<5> @[Mux.scala 27:72]
+    _T_1150 <= _T_1149 @[Mux.scala 27:72]
+    shortq_decode <= _T_1150 @[exu_div_ctl.scala 775:17]
+    node _T_1151 = eq(shortq_enable, UInt<1>("h00")) @[exu_div_ctl.scala 776:26]
+    node shortq_shift = mux(_T_1151, UInt<1>("h00"), shortq_decode) @[exu_div_ctl.scala 776:25]
+    node _T_1152 = bits(b_ff1, 32, 32) @[exu_div_ctl.scala 777:20]
+    node _T_1153 = bits(b_ff1, 32, 32) @[exu_div_ctl.scala 777:30]
+    node _T_1154 = bits(b_ff1, 32, 32) @[exu_div_ctl.scala 777:40]
+    node _T_1155 = bits(b_ff1, 32, 32) @[exu_div_ctl.scala 777:50]
+    node _T_1156 = cat(_T_1155, b_ff1) @[Cat.scala 29:58]
+    node _T_1157 = cat(_T_1152, _T_1153) @[Cat.scala 29:58]
+    node _T_1158 = cat(_T_1157, _T_1154) @[Cat.scala 29:58]
+    node _T_1159 = cat(_T_1158, _T_1156) @[Cat.scala 29:58]
+    b_ff <= _T_1159 @[exu_div_ctl.scala 777:8]
+    inst rvclkhdr of rvclkhdr @[lib.scala 390:23]
+    rvclkhdr.clock <= clock
+    rvclkhdr.reset <= reset
+    rvclkhdr.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr.io.en <= misc_enable @[lib.scala 393:17]
+    rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_1160 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when misc_enable : @[Reg.scala 28:19]
+      _T_1160 <= valid_ff_in @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    valid_ff <= _T_1160 @[exu_div_ctl.scala 778:12]
+    inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 390:23]
+    rvclkhdr_1.clock <= clock
+    rvclkhdr_1.reset <= reset
+    rvclkhdr_1.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_1.io.en <= misc_enable @[lib.scala 393:17]
+    rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_1161 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when misc_enable : @[Reg.scala 28:19]
+      _T_1161 <= control_in @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    control_ff <= _T_1161 @[exu_div_ctl.scala 779:16]
+    inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 390:23]
+    rvclkhdr_2.clock <= clock
+    rvclkhdr_2.reset <= reset
+    rvclkhdr_2.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_2.io.en <= misc_enable @[lib.scala 393:17]
+    rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_1162 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when misc_enable : @[Reg.scala 28:19]
+      _T_1162 <= by_zero_case @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    by_zero_case_ff <= _T_1162 @[exu_div_ctl.scala 780:19]
+    inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 390:23]
+    rvclkhdr_3.clock <= clock
+    rvclkhdr_3.reset <= reset
+    rvclkhdr_3.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_3.io.en <= misc_enable @[lib.scala 393:17]
+    rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_1163 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when misc_enable : @[Reg.scala 28:19]
+      _T_1163 <= shortq_enable @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    shortq_enable_ff <= _T_1163 @[exu_div_ctl.scala 781:20]
+    inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 390:23]
+    rvclkhdr_4.clock <= clock
+    rvclkhdr_4.reset <= reset
+    rvclkhdr_4.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_4.io.en <= misc_enable @[lib.scala 393:17]
+    rvclkhdr_4.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_1164 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when misc_enable : @[Reg.scala 28:19]
+      _T_1164 <= shortq_shift @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    node _T_1165 = cat(_T_1164, UInt<1>("h00")) @[Cat.scala 29:58]
+    shortq_shift_ff <= _T_1165 @[exu_div_ctl.scala 782:19]
+    inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 390:23]
+    rvclkhdr_5.clock <= clock
+    rvclkhdr_5.reset <= reset
+    rvclkhdr_5.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_5.io.en <= misc_enable @[lib.scala 393:17]
+    rvclkhdr_5.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_1166 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when misc_enable : @[Reg.scala 28:19]
+      _T_1166 <= finish @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    finish_ff <= _T_1166 @[exu_div_ctl.scala 783:13]
+    inst rvclkhdr_6 of rvclkhdr_6 @[lib.scala 390:23]
+    rvclkhdr_6.clock <= clock
+    rvclkhdr_6.reset <= reset
+    rvclkhdr_6.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_6.io.en <= misc_enable @[lib.scala 393:17]
+    rvclkhdr_6.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_1167 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when misc_enable : @[Reg.scala 28:19]
+      _T_1167 <= count_in @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    count_ff <= _T_1167 @[exu_div_ctl.scala 784:12]
+    inst rvclkhdr_7 of rvclkhdr_7 @[lib.scala 390:23]
+    rvclkhdr_7.clock <= clock
+    rvclkhdr_7.reset <= reset
+    rvclkhdr_7.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_7.io.en <= a_enable @[lib.scala 393:17]
+    rvclkhdr_7.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_1168 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when a_enable : @[Reg.scala 28:19]
+      _T_1168 <= a_in @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    a_ff <= _T_1168 @[exu_div_ctl.scala 786:8]
+    node _T_1169 = bits(b_in, 32, 0) @[exu_div_ctl.scala 787:23]
+    inst rvclkhdr_8 of rvclkhdr_8 @[lib.scala 390:23]
+    rvclkhdr_8.clock <= clock
+    rvclkhdr_8.reset <= reset
+    rvclkhdr_8.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_8.io.en <= b_enable @[lib.scala 393:17]
+    rvclkhdr_8.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_1170 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when b_enable : @[Reg.scala 28:19]
+      _T_1170 <= _T_1169 @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    b_ff1 <= _T_1170 @[exu_div_ctl.scala 787:9]
+    inst rvclkhdr_9 of rvclkhdr_9 @[lib.scala 390:23]
+    rvclkhdr_9.clock <= clock
+    rvclkhdr_9.reset <= reset
+    rvclkhdr_9.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_9.io.en <= rq_enable @[lib.scala 393:17]
+    rvclkhdr_9.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_1171 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when rq_enable : @[Reg.scala 28:19]
+      _T_1171 <= r_in @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    r_ff <= _T_1171 @[exu_div_ctl.scala 788:8]
+    inst rvclkhdr_10 of rvclkhdr_10 @[lib.scala 390:23]
+    rvclkhdr_10.clock <= clock
+    rvclkhdr_10.reset <= reset
+    rvclkhdr_10.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_10.io.en <= rq_enable @[lib.scala 393:17]
+    rvclkhdr_10.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_1172 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when rq_enable : @[Reg.scala 28:19]
+      _T_1172 <= q_in @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    q_ff <= _T_1172 @[exu_div_ctl.scala 789:8]
+    
diff --git a/exu_div_new_3bit_fullshortq.v b/exu_div_new_3bit_fullshortq.v
new file mode 100644
index 00000000..a209303f
--- /dev/null
+++ b/exu_div_new_3bit_fullshortq.v
@@ -0,0 +1,1082 @@
+module exu_div_cls(
+  input  [32:0] io_operand,
+  output [4:0]  io_cls
+);
+  wire  _T_3 = io_operand[31:30] == 2'h1; // @[exu_div_ctl.scala 819:63]
+  wire  _T_5 = io_operand[31:29] == 3'h1; // @[exu_div_ctl.scala 819:63]
+  wire  _T_7 = io_operand[31:28] == 4'h1; // @[exu_div_ctl.scala 819:63]
+  wire  _T_9 = io_operand[31:27] == 5'h1; // @[exu_div_ctl.scala 819:63]
+  wire  _T_11 = io_operand[31:26] == 6'h1; // @[exu_div_ctl.scala 819:63]
+  wire  _T_13 = io_operand[31:25] == 7'h1; // @[exu_div_ctl.scala 819:63]
+  wire  _T_15 = io_operand[31:24] == 8'h1; // @[exu_div_ctl.scala 819:63]
+  wire  _T_17 = io_operand[31:23] == 9'h1; // @[exu_div_ctl.scala 819:63]
+  wire  _T_19 = io_operand[31:22] == 10'h1; // @[exu_div_ctl.scala 819:63]
+  wire  _T_21 = io_operand[31:21] == 11'h1; // @[exu_div_ctl.scala 819:63]
+  wire  _T_23 = io_operand[31:20] == 12'h1; // @[exu_div_ctl.scala 819:63]
+  wire  _T_25 = io_operand[31:19] == 13'h1; // @[exu_div_ctl.scala 819:63]
+  wire  _T_27 = io_operand[31:18] == 14'h1; // @[exu_div_ctl.scala 819:63]
+  wire  _T_29 = io_operand[31:17] == 15'h1; // @[exu_div_ctl.scala 819:63]
+  wire  _T_31 = io_operand[31:16] == 16'h1; // @[exu_div_ctl.scala 819:63]
+  wire  _T_33 = io_operand[31:15] == 17'h1; // @[exu_div_ctl.scala 819:63]
+  wire  _T_35 = io_operand[31:14] == 18'h1; // @[exu_div_ctl.scala 819:63]
+  wire  _T_37 = io_operand[31:13] == 19'h1; // @[exu_div_ctl.scala 819:63]
+  wire  _T_39 = io_operand[31:12] == 20'h1; // @[exu_div_ctl.scala 819:63]
+  wire  _T_41 = io_operand[31:11] == 21'h1; // @[exu_div_ctl.scala 819:63]
+  wire  _T_43 = io_operand[31:10] == 22'h1; // @[exu_div_ctl.scala 819:63]
+  wire  _T_45 = io_operand[31:9] == 23'h1; // @[exu_div_ctl.scala 819:63]
+  wire  _T_47 = io_operand[31:8] == 24'h1; // @[exu_div_ctl.scala 819:63]
+  wire  _T_49 = io_operand[31:7] == 25'h1; // @[exu_div_ctl.scala 819:63]
+  wire  _T_51 = io_operand[31:6] == 26'h1; // @[exu_div_ctl.scala 819:63]
+  wire  _T_53 = io_operand[31:5] == 27'h1; // @[exu_div_ctl.scala 819:63]
+  wire  _T_55 = io_operand[31:4] == 28'h1; // @[exu_div_ctl.scala 819:63]
+  wire  _T_57 = io_operand[31:3] == 29'h1; // @[exu_div_ctl.scala 819:63]
+  wire  _T_59 = io_operand[31:2] == 30'h1; // @[exu_div_ctl.scala 819:63]
+  wire  _T_61 = io_operand[31:1] == 31'h1; // @[exu_div_ctl.scala 819:63]
+  wire  _T_63 = io_operand[31:0] == 32'h1; // @[exu_div_ctl.scala 819:63]
+  wire [1:0] _T_66 = _T_5 ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
+  wire [1:0] _T_67 = _T_7 ? 2'h3 : 2'h0; // @[Mux.scala 27:72]
+  wire [2:0] _T_68 = _T_9 ? 3'h4 : 3'h0; // @[Mux.scala 27:72]
+  wire [2:0] _T_69 = _T_11 ? 3'h5 : 3'h0; // @[Mux.scala 27:72]
+  wire [2:0] _T_70 = _T_13 ? 3'h6 : 3'h0; // @[Mux.scala 27:72]
+  wire [2:0] _T_71 = _T_15 ? 3'h7 : 3'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_72 = _T_17 ? 4'h8 : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_73 = _T_19 ? 4'h9 : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_74 = _T_21 ? 4'ha : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_75 = _T_23 ? 4'hb : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_76 = _T_25 ? 4'hc : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_77 = _T_27 ? 4'hd : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_78 = _T_29 ? 4'he : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_79 = _T_31 ? 4'hf : 4'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_80 = _T_33 ? 5'h10 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_81 = _T_35 ? 5'h11 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_82 = _T_37 ? 5'h12 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_83 = _T_39 ? 5'h13 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_84 = _T_41 ? 5'h14 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_85 = _T_43 ? 5'h15 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_86 = _T_45 ? 5'h16 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_87 = _T_47 ? 5'h17 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_88 = _T_49 ? 5'h18 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_89 = _T_51 ? 5'h19 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_90 = _T_53 ? 5'h1a : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_91 = _T_55 ? 5'h1b : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_92 = _T_57 ? 5'h1c : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_93 = _T_59 ? 5'h1d : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_94 = _T_61 ? 5'h1e : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_95 = _T_63 ? 5'h1f : 5'h0; // @[Mux.scala 27:72]
+  wire [1:0] _GEN_1 = {{1'd0}, _T_3}; // @[Mux.scala 27:72]
+  wire [1:0] _T_97 = _GEN_1 | _T_66; // @[Mux.scala 27:72]
+  wire [1:0] _T_98 = _T_97 | _T_67; // @[Mux.scala 27:72]
+  wire [2:0] _GEN_2 = {{1'd0}, _T_98}; // @[Mux.scala 27:72]
+  wire [2:0] _T_99 = _GEN_2 | _T_68; // @[Mux.scala 27:72]
+  wire [2:0] _T_100 = _T_99 | _T_69; // @[Mux.scala 27:72]
+  wire [2:0] _T_101 = _T_100 | _T_70; // @[Mux.scala 27:72]
+  wire [2:0] _T_102 = _T_101 | _T_71; // @[Mux.scala 27:72]
+  wire [3:0] _GEN_3 = {{1'd0}, _T_102}; // @[Mux.scala 27:72]
+  wire [3:0] _T_103 = _GEN_3 | _T_72; // @[Mux.scala 27:72]
+  wire [3:0] _T_104 = _T_103 | _T_73; // @[Mux.scala 27:72]
+  wire [3:0] _T_105 = _T_104 | _T_74; // @[Mux.scala 27:72]
+  wire [3:0] _T_106 = _T_105 | _T_75; // @[Mux.scala 27:72]
+  wire [3:0] _T_107 = _T_106 | _T_76; // @[Mux.scala 27:72]
+  wire [3:0] _T_108 = _T_107 | _T_77; // @[Mux.scala 27:72]
+  wire [3:0] _T_109 = _T_108 | _T_78; // @[Mux.scala 27:72]
+  wire [3:0] _T_110 = _T_109 | _T_79; // @[Mux.scala 27:72]
+  wire [4:0] _GEN_4 = {{1'd0}, _T_110}; // @[Mux.scala 27:72]
+  wire [4:0] _T_111 = _GEN_4 | _T_80; // @[Mux.scala 27:72]
+  wire [4:0] _T_112 = _T_111 | _T_81; // @[Mux.scala 27:72]
+  wire [4:0] _T_113 = _T_112 | _T_82; // @[Mux.scala 27:72]
+  wire [4:0] _T_114 = _T_113 | _T_83; // @[Mux.scala 27:72]
+  wire [4:0] _T_115 = _T_114 | _T_84; // @[Mux.scala 27:72]
+  wire [4:0] _T_116 = _T_115 | _T_85; // @[Mux.scala 27:72]
+  wire [4:0] _T_117 = _T_116 | _T_86; // @[Mux.scala 27:72]
+  wire [4:0] _T_118 = _T_117 | _T_87; // @[Mux.scala 27:72]
+  wire [4:0] _T_119 = _T_118 | _T_88; // @[Mux.scala 27:72]
+  wire [4:0] _T_120 = _T_119 | _T_89; // @[Mux.scala 27:72]
+  wire [4:0] _T_121 = _T_120 | _T_90; // @[Mux.scala 27:72]
+  wire [4:0] _T_122 = _T_121 | _T_91; // @[Mux.scala 27:72]
+  wire [4:0] _T_123 = _T_122 | _T_92; // @[Mux.scala 27:72]
+  wire [4:0] _T_124 = _T_123 | _T_93; // @[Mux.scala 27:72]
+  wire [4:0] _T_125 = _T_124 | _T_94; // @[Mux.scala 27:72]
+  wire [4:0] cls_zeros = _T_125 | _T_95; // @[Mux.scala 27:72]
+  wire  _T_129 = io_operand[31:0] == 32'hffffffff; // @[exu_div_ctl.scala 821:25]
+  wire  _T_137 = io_operand[31:29] == 3'h6; // @[exu_div_ctl.scala 822:76]
+  wire  _T_142 = io_operand[31:28] == 4'he; // @[exu_div_ctl.scala 822:76]
+  wire  _T_147 = io_operand[31:27] == 5'h1e; // @[exu_div_ctl.scala 822:76]
+  wire  _T_152 = io_operand[31:26] == 6'h3e; // @[exu_div_ctl.scala 822:76]
+  wire  _T_157 = io_operand[31:25] == 7'h7e; // @[exu_div_ctl.scala 822:76]
+  wire  _T_162 = io_operand[31:24] == 8'hfe; // @[exu_div_ctl.scala 822:76]
+  wire  _T_167 = io_operand[31:23] == 9'h1fe; // @[exu_div_ctl.scala 822:76]
+  wire  _T_172 = io_operand[31:22] == 10'h3fe; // @[exu_div_ctl.scala 822:76]
+  wire  _T_177 = io_operand[31:21] == 11'h7fe; // @[exu_div_ctl.scala 822:76]
+  wire  _T_182 = io_operand[31:20] == 12'hffe; // @[exu_div_ctl.scala 822:76]
+  wire  _T_187 = io_operand[31:19] == 13'h1ffe; // @[exu_div_ctl.scala 822:76]
+  wire  _T_192 = io_operand[31:18] == 14'h3ffe; // @[exu_div_ctl.scala 822:76]
+  wire  _T_197 = io_operand[31:17] == 15'h7ffe; // @[exu_div_ctl.scala 822:76]
+  wire  _T_202 = io_operand[31:16] == 16'hfffe; // @[exu_div_ctl.scala 822:76]
+  wire  _T_207 = io_operand[31:15] == 17'h1fffe; // @[exu_div_ctl.scala 822:76]
+  wire  _T_212 = io_operand[31:14] == 18'h3fffe; // @[exu_div_ctl.scala 822:76]
+  wire  _T_217 = io_operand[31:13] == 19'h7fffe; // @[exu_div_ctl.scala 822:76]
+  wire  _T_222 = io_operand[31:12] == 20'hffffe; // @[exu_div_ctl.scala 822:76]
+  wire  _T_227 = io_operand[31:11] == 21'h1ffffe; // @[exu_div_ctl.scala 822:76]
+  wire  _T_232 = io_operand[31:10] == 22'h3ffffe; // @[exu_div_ctl.scala 822:76]
+  wire  _T_237 = io_operand[31:9] == 23'h7ffffe; // @[exu_div_ctl.scala 822:76]
+  wire  _T_242 = io_operand[31:8] == 24'hfffffe; // @[exu_div_ctl.scala 822:76]
+  wire  _T_247 = io_operand[31:7] == 25'h1fffffe; // @[exu_div_ctl.scala 822:76]
+  wire  _T_252 = io_operand[31:6] == 26'h3fffffe; // @[exu_div_ctl.scala 822:76]
+  wire  _T_257 = io_operand[31:5] == 27'h7fffffe; // @[exu_div_ctl.scala 822:76]
+  wire  _T_262 = io_operand[31:4] == 28'hffffffe; // @[exu_div_ctl.scala 822:76]
+  wire  _T_267 = io_operand[31:3] == 29'h1ffffffe; // @[exu_div_ctl.scala 822:76]
+  wire  _T_272 = io_operand[31:2] == 30'h3ffffffe; // @[exu_div_ctl.scala 822:76]
+  wire  _T_277 = io_operand[31:1] == 31'h7ffffffe; // @[exu_div_ctl.scala 822:76]
+  wire  _T_282 = io_operand[31:0] == 32'hfffffffe; // @[exu_div_ctl.scala 822:76]
+  wire [1:0] _T_286 = _T_142 ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
+  wire [1:0] _T_287 = _T_147 ? 2'h3 : 2'h0; // @[Mux.scala 27:72]
+  wire [2:0] _T_288 = _T_152 ? 3'h4 : 3'h0; // @[Mux.scala 27:72]
+  wire [2:0] _T_289 = _T_157 ? 3'h5 : 3'h0; // @[Mux.scala 27:72]
+  wire [2:0] _T_290 = _T_162 ? 3'h6 : 3'h0; // @[Mux.scala 27:72]
+  wire [2:0] _T_291 = _T_167 ? 3'h7 : 3'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_292 = _T_172 ? 4'h8 : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_293 = _T_177 ? 4'h9 : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_294 = _T_182 ? 4'ha : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_295 = _T_187 ? 4'hb : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_296 = _T_192 ? 4'hc : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_297 = _T_197 ? 4'hd : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_298 = _T_202 ? 4'he : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_299 = _T_207 ? 4'hf : 4'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_300 = _T_212 ? 5'h10 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_301 = _T_217 ? 5'h11 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_302 = _T_222 ? 5'h12 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_303 = _T_227 ? 5'h13 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_304 = _T_232 ? 5'h14 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_305 = _T_237 ? 5'h15 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_306 = _T_242 ? 5'h16 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_307 = _T_247 ? 5'h17 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_308 = _T_252 ? 5'h18 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_309 = _T_257 ? 5'h19 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_310 = _T_262 ? 5'h1a : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_311 = _T_267 ? 5'h1b : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_312 = _T_272 ? 5'h1c : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_313 = _T_277 ? 5'h1d : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_314 = _T_282 ? 5'h1e : 5'h0; // @[Mux.scala 27:72]
+  wire [1:0] _GEN_5 = {{1'd0}, _T_137}; // @[Mux.scala 27:72]
+  wire [1:0] _T_316 = _GEN_5 | _T_286; // @[Mux.scala 27:72]
+  wire [1:0] _T_317 = _T_316 | _T_287; // @[Mux.scala 27:72]
+  wire [2:0] _GEN_6 = {{1'd0}, _T_317}; // @[Mux.scala 27:72]
+  wire [2:0] _T_318 = _GEN_6 | _T_288; // @[Mux.scala 27:72]
+  wire [2:0] _T_319 = _T_318 | _T_289; // @[Mux.scala 27:72]
+  wire [2:0] _T_320 = _T_319 | _T_290; // @[Mux.scala 27:72]
+  wire [2:0] _T_321 = _T_320 | _T_291; // @[Mux.scala 27:72]
+  wire [3:0] _GEN_7 = {{1'd0}, _T_321}; // @[Mux.scala 27:72]
+  wire [3:0] _T_322 = _GEN_7 | _T_292; // @[Mux.scala 27:72]
+  wire [3:0] _T_323 = _T_322 | _T_293; // @[Mux.scala 27:72]
+  wire [3:0] _T_324 = _T_323 | _T_294; // @[Mux.scala 27:72]
+  wire [3:0] _T_325 = _T_324 | _T_295; // @[Mux.scala 27:72]
+  wire [3:0] _T_326 = _T_325 | _T_296; // @[Mux.scala 27:72]
+  wire [3:0] _T_327 = _T_326 | _T_297; // @[Mux.scala 27:72]
+  wire [3:0] _T_328 = _T_327 | _T_298; // @[Mux.scala 27:72]
+  wire [3:0] _T_329 = _T_328 | _T_299; // @[Mux.scala 27:72]
+  wire [4:0] _GEN_8 = {{1'd0}, _T_329}; // @[Mux.scala 27:72]
+  wire [4:0] _T_330 = _GEN_8 | _T_300; // @[Mux.scala 27:72]
+  wire [4:0] _T_331 = _T_330 | _T_301; // @[Mux.scala 27:72]
+  wire [4:0] _T_332 = _T_331 | _T_302; // @[Mux.scala 27:72]
+  wire [4:0] _T_333 = _T_332 | _T_303; // @[Mux.scala 27:72]
+  wire [4:0] _T_334 = _T_333 | _T_304; // @[Mux.scala 27:72]
+  wire [4:0] _T_335 = _T_334 | _T_305; // @[Mux.scala 27:72]
+  wire [4:0] _T_336 = _T_335 | _T_306; // @[Mux.scala 27:72]
+  wire [4:0] _T_337 = _T_336 | _T_307; // @[Mux.scala 27:72]
+  wire [4:0] _T_338 = _T_337 | _T_308; // @[Mux.scala 27:72]
+  wire [4:0] _T_339 = _T_338 | _T_309; // @[Mux.scala 27:72]
+  wire [4:0] _T_340 = _T_339 | _T_310; // @[Mux.scala 27:72]
+  wire [4:0] _T_341 = _T_340 | _T_311; // @[Mux.scala 27:72]
+  wire [4:0] _T_342 = _T_341 | _T_312; // @[Mux.scala 27:72]
+  wire [4:0] _T_343 = _T_342 | _T_313; // @[Mux.scala 27:72]
+  wire [4:0] _T_344 = _T_343 | _T_314; // @[Mux.scala 27:72]
+  wire [4:0] cls_ones = _T_129 ? 5'h1f : _T_344; // @[exu_div_ctl.scala 821:44]
+  assign io_cls = io_operand[32] ? cls_ones : cls_zeros; // @[exu_div_ctl.scala 823:10]
+endmodule
+module rvclkhdr(
+  input   io_clk,
+  input   io_en
+);
+  wire  clkhdr_Q; // @[lib.scala 334:26]
+  wire  clkhdr_CK; // @[lib.scala 334:26]
+  wire  clkhdr_EN; // @[lib.scala 334:26]
+  wire  clkhdr_SE; // @[lib.scala 334:26]
+  gated_latch clkhdr ( // @[lib.scala 334:26]
+    .Q(clkhdr_Q),
+    .CK(clkhdr_CK),
+    .EN(clkhdr_EN),
+    .SE(clkhdr_SE)
+  );
+  assign clkhdr_CK = io_clk; // @[lib.scala 336:18]
+  assign clkhdr_EN = io_en; // @[lib.scala 337:18]
+  assign clkhdr_SE = 1'h0; // @[lib.scala 338:18]
+endmodule
+module exu_div_new_3bit_fullshortq(
+  input         clock,
+  input         reset,
+  input         io_scan_mode,
+  input         io_cancel,
+  input         io_valid_in,
+  input         io_signed_in,
+  input         io_rem_in,
+  input  [31:0] io_dividend_in,
+  input  [31:0] io_divisor_in,
+  output [31:0] io_data_out,
+  output        io_valid_out
+);
+`ifdef RANDOMIZE_REG_INIT
+  reg [31:0] _RAND_0;
+  reg [63:0] _RAND_1;
+  reg [31:0] _RAND_2;
+  reg [63:0] _RAND_3;
+  reg [31:0] _RAND_4;
+  reg [31:0] _RAND_5;
+  reg [31:0] _RAND_6;
+  reg [31:0] _RAND_7;
+  reg [31:0] _RAND_8;
+  reg [63:0] _RAND_9;
+  reg [31:0] _RAND_10;
+`endif // RANDOMIZE_REG_INIT
+  wire [32:0] a_enc_io_operand; // @[exu_div_ctl.scala 763:21]
+  wire [4:0] a_enc_io_cls; // @[exu_div_ctl.scala 763:21]
+  wire [32:0] b_enc_io_operand; // @[exu_div_ctl.scala 766:20]
+  wire [4:0] b_enc_io_cls; // @[exu_div_ctl.scala 766:20]
+  wire  rvclkhdr_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_1_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_1_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_2_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_2_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_3_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_3_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_4_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_4_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_5_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_5_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_6_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_6_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_7_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_7_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_8_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_8_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_9_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_9_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_10_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_10_io_en; // @[lib.scala 390:23]
+  wire  _T = ~io_cancel; // @[exu_div_ctl.scala 649:35]
+  wire  valid_ff_in = io_valid_in & _T; // @[exu_div_ctl.scala 649:33]
+  wire  _T_1 = ~io_valid_in; // @[exu_div_ctl.scala 650:35]
+  reg [2:0] control_ff; // @[Reg.scala 27:20]
+  wire  _T_3 = _T_1 & control_ff[2]; // @[exu_div_ctl.scala 650:48]
+  wire  _T_4 = io_valid_in & io_signed_in; // @[exu_div_ctl.scala 650:80]
+  wire  _T_6 = _T_4 & io_dividend_in[31]; // @[exu_div_ctl.scala 650:96]
+  wire  _T_7 = _T_3 | _T_6; // @[exu_div_ctl.scala 650:65]
+  wire  _T_10 = _T_1 & control_ff[1]; // @[exu_div_ctl.scala 650:133]
+  wire  _T_13 = _T_4 & io_divisor_in[31]; // @[exu_div_ctl.scala 650:181]
+  wire  _T_14 = _T_10 | _T_13; // @[exu_div_ctl.scala 650:150]
+  wire  _T_17 = _T_1 & control_ff[0]; // @[exu_div_ctl.scala 650:218]
+  wire  _T_18 = io_valid_in & io_rem_in; // @[exu_div_ctl.scala 650:250]
+  wire  _T_19 = _T_17 | _T_18; // @[exu_div_ctl.scala 650:235]
+  wire [2:0] control_in = {_T_7,_T_14,_T_19}; // @[Cat.scala 29:58]
+  reg [32:0] b_ff1; // @[Reg.scala 27:20]
+  wire [36:0] b_ff = {b_ff1[32],b_ff1[32],b_ff1[32],b_ff1[32],b_ff1}; // @[Cat.scala 29:58]
+  wire  _T_22 = b_ff[31:0] == 32'h0; // @[exu_div_ctl.scala 654:54]
+  reg  valid_ff; // @[Reg.scala 27:20]
+  wire  by_zero_case = valid_ff & _T_22; // @[exu_div_ctl.scala 654:40]
+  reg [32:0] a_ff; // @[Reg.scala 27:20]
+  wire  _T_24 = a_ff[31:4] == 28'h0; // @[exu_div_ctl.scala 656:37]
+  wire  _T_26 = b_ff[31:4] == 28'h0; // @[exu_div_ctl.scala 656:60]
+  wire  _T_27 = _T_24 & _T_26; // @[exu_div_ctl.scala 656:46]
+  wire  _T_28 = ~by_zero_case; // @[exu_div_ctl.scala 656:71]
+  wire  _T_29 = _T_27 & _T_28; // @[exu_div_ctl.scala 656:69]
+  wire  _T_30 = ~control_ff[0]; // @[exu_div_ctl.scala 656:87]
+  wire  _T_31 = _T_29 & _T_30; // @[exu_div_ctl.scala 656:85]
+  wire  _T_32 = _T_31 & valid_ff; // @[exu_div_ctl.scala 656:95]
+  wire  _T_34 = _T_32 & _T; // @[exu_div_ctl.scala 656:106]
+  wire  _T_36 = a_ff[31:0] == 32'h0; // @[exu_div_ctl.scala 657:18]
+  wire  _T_38 = _T_36 & _T_28; // @[exu_div_ctl.scala 657:27]
+  wire  _T_40 = _T_38 & _T_30; // @[exu_div_ctl.scala 657:43]
+  wire  _T_41 = _T_40 & valid_ff; // @[exu_div_ctl.scala 657:53]
+  wire  _T_43 = _T_41 & _T; // @[exu_div_ctl.scala 657:64]
+  wire  smallnum_case = _T_34 | _T_43; // @[exu_div_ctl.scala 656:120]
+  reg [6:0] count_ff; // @[Reg.scala 27:20]
+  wire  _T_44 = |count_ff; // @[exu_div_ctl.scala 658:42]
+  reg  shortq_enable_ff; // @[Reg.scala 27:20]
+  wire  running_state = _T_44 | shortq_enable_ff; // @[exu_div_ctl.scala 658:45]
+  wire  _T_45 = io_valid_in | valid_ff; // @[exu_div_ctl.scala 659:43]
+  wire  _T_46 = _T_45 | io_cancel; // @[exu_div_ctl.scala 659:54]
+  wire  _T_47 = _T_46 | running_state; // @[exu_div_ctl.scala 659:66]
+  reg  finish_ff; // @[Reg.scala 27:20]
+  wire  misc_enable = _T_47 | finish_ff; // @[exu_div_ctl.scala 659:82]
+  wire  _T_48 = smallnum_case | by_zero_case; // @[exu_div_ctl.scala 660:45]
+  wire  _T_49 = count_ff == 7'h21; // @[exu_div_ctl.scala 660:72]
+  wire  finish_raw = _T_48 | _T_49; // @[exu_div_ctl.scala 660:60]
+  wire  finish = finish_raw & _T; // @[exu_div_ctl.scala 661:41]
+  wire  _T_51 = valid_ff | running_state; // @[exu_div_ctl.scala 662:40]
+  wire  _T_52 = ~finish; // @[exu_div_ctl.scala 662:59]
+  wire  _T_53 = _T_51 & _T_52; // @[exu_div_ctl.scala 662:57]
+  wire  _T_54 = ~finish_ff; // @[exu_div_ctl.scala 662:69]
+  wire  _T_55 = _T_53 & _T_54; // @[exu_div_ctl.scala 662:67]
+  wire  _T_57 = _T_55 & _T; // @[exu_div_ctl.scala 662:80]
+  wire [6:0] _T_1038 = {1'h0,1'h0,b_enc_io_cls}; // @[Cat.scala 29:58]
+  wire [6:0] _T_1039 = {1'h0,1'h0,a_enc_io_cls}; // @[Cat.scala 29:58]
+  wire [6:0] _T_1041 = _T_1038 - _T_1039; // @[exu_div_ctl.scala 771:41]
+  wire [6:0] dw_shortq_raw = _T_1041 + 7'h1; // @[exu_div_ctl.scala 771:61]
+  wire [5:0] shortq = dw_shortq_raw[6] ? 6'h0 : dw_shortq_raw[5:0]; // @[exu_div_ctl.scala 772:19]
+  wire  _T_1047 = ~shortq[5]; // @[exu_div_ctl.scala 773:31]
+  wire  _T_1048 = valid_ff & _T_1047; // @[exu_div_ctl.scala 773:29]
+  wire  _T_1050 = shortq[4:2] == 3'h7; // @[exu_div_ctl.scala 773:58]
+  wire  _T_1051 = ~_T_1050; // @[exu_div_ctl.scala 773:44]
+  wire  _T_1052 = _T_1048 & _T_1051; // @[exu_div_ctl.scala 773:42]
+  wire  shortq_enable = _T_1052 & _T; // @[exu_div_ctl.scala 773:73]
+  wire  _T_58 = ~shortq_enable; // @[exu_div_ctl.scala 662:95]
+  wire  count_enable = _T_57 & _T_58; // @[exu_div_ctl.scala 662:93]
+  wire [6:0] _T_60 = count_enable ? 7'h7f : 7'h0; // @[Bitwise.scala 72:12]
+  wire [6:0] _T_63 = count_ff + 7'h3; // @[exu_div_ctl.scala 663:63]
+  reg [4:0] _T_1164; // @[Reg.scala 27:20]
+  wire [5:0] _T_1165 = {_T_1164,1'h0}; // @[Cat.scala 29:58]
+  wire [4:0] shortq_shift_ff = _T_1165[4:0]; // @[exu_div_ctl.scala 782:19]
+  wire [6:0] _T_64 = {2'h0,shortq_shift_ff}; // @[Cat.scala 29:58]
+  wire [6:0] _T_66 = _T_63 + _T_64; // @[exu_div_ctl.scala 663:83]
+  wire [6:0] count_in = _T_60 & _T_66; // @[exu_div_ctl.scala 663:51]
+  wire  a_enable = io_valid_in | running_state; // @[exu_div_ctl.scala 664:43]
+  wire  _T_67 = ~shortq_enable_ff; // @[exu_div_ctl.scala 665:47]
+  wire  a_shift = running_state & _T_67; // @[exu_div_ctl.scala 665:45]
+  wire [32:0] _T_69 = control_ff[2] ? 33'h1ffffffff : 33'h0; // @[Bitwise.scala 72:12]
+  wire [65:0] _T_70 = {_T_69,a_ff}; // @[Cat.scala 29:58]
+  wire [96:0] _GEN_11 = {{31'd0}, _T_70}; // @[exu_div_ctl.scala 666:68]
+  wire [96:0] _T_71 = _GEN_11 << shortq_shift_ff; // @[exu_div_ctl.scala 666:68]
+  wire  _T_72 = control_ff[2] ^ control_ff[1]; // @[exu_div_ctl.scala 667:61]
+  wire  _T_73 = ~_T_72; // @[exu_div_ctl.scala 667:42]
+  wire  b_twos_comp = valid_ff & _T_73; // @[exu_div_ctl.scala 667:40]
+  wire  _T_76 = ~valid_ff; // @[exu_div_ctl.scala 669:30]
+  wire  _T_78 = _T_76 & _T_30; // @[exu_div_ctl.scala 669:40]
+  wire  _T_80 = _T_78 & _T_72; // @[exu_div_ctl.scala 669:50]
+  reg  by_zero_case_ff; // @[Reg.scala 27:20]
+  wire  _T_81 = ~by_zero_case_ff; // @[exu_div_ctl.scala 669:92]
+  wire  twos_comp_q_sel = _T_80 & _T_81; // @[exu_div_ctl.scala 669:90]
+  wire  b_enable = io_valid_in | b_twos_comp; // @[exu_div_ctl.scala 670:43]
+  wire  rq_enable = _T_45 | running_state; // @[exu_div_ctl.scala 671:54]
+  wire  _T_83 = valid_ff & control_ff[2]; // @[exu_div_ctl.scala 672:40]
+  wire  r_sign_sel = _T_83 & _T_28; // @[exu_div_ctl.scala 672:59]
+  reg [32:0] r_ff; // @[Reg.scala 27:20]
+  wire [36:0] _T_163 = {r_ff[32],r_ff,a_ff[32:30]}; // @[Cat.scala 29:58]
+  wire [36:0] _T_165 = {b_ff[34:0],2'h0}; // @[Cat.scala 29:58]
+  wire [36:0] _T_167 = _T_163 + _T_165; // @[exu_div_ctl.scala 687:57]
+  wire [36:0] _T_169 = {b_ff[35:0],1'h0}; // @[Cat.scala 29:58]
+  wire [36:0] _T_171 = _T_167 + _T_169; // @[exu_div_ctl.scala 687:84]
+  wire [36:0] adder7_out = _T_171 + b_ff; // @[exu_div_ctl.scala 687:106]
+  wire  _T_174 = ~adder7_out[36]; // @[exu_div_ctl.scala 688:24]
+  wire  _T_175 = _T_174 ^ control_ff[2]; // @[exu_div_ctl.scala 688:40]
+  wire  _T_177 = a_ff[29:0] == 30'h0; // @[exu_div_ctl.scala 688:75]
+  wire  _T_178 = adder7_out == 37'h0; // @[exu_div_ctl.scala 688:98]
+  wire  _T_179 = _T_177 & _T_178; // @[exu_div_ctl.scala 688:84]
+  wire  _T_180 = _T_175 | _T_179; // @[exu_div_ctl.scala 688:60]
+  wire  _T_182 = ~_T_171[36]; // @[exu_div_ctl.scala 689:23]
+  wire  _T_183 = _T_182 ^ control_ff[2]; // @[exu_div_ctl.scala 689:39]
+  wire  _T_186 = _T_171 == 37'h0; // @[exu_div_ctl.scala 689:97]
+  wire  _T_187 = _T_177 & _T_186; // @[exu_div_ctl.scala 689:83]
+  wire  _T_188 = _T_183 | _T_187; // @[exu_div_ctl.scala 689:59]
+  wire [36:0] adder5_out = _T_167 + b_ff; // @[exu_div_ctl.scala 685:84]
+  wire  _T_190 = ~adder5_out[36]; // @[exu_div_ctl.scala 690:23]
+  wire  _T_191 = _T_190 ^ control_ff[2]; // @[exu_div_ctl.scala 690:39]
+  wire  _T_194 = adder5_out == 37'h0; // @[exu_div_ctl.scala 690:97]
+  wire  _T_195 = _T_177 & _T_194; // @[exu_div_ctl.scala 690:83]
+  wire  _T_196 = _T_191 | _T_195; // @[exu_div_ctl.scala 690:59]
+  wire  _T_198 = ~_T_167[36]; // @[exu_div_ctl.scala 691:23]
+  wire  _T_199 = _T_198 ^ control_ff[2]; // @[exu_div_ctl.scala 691:39]
+  wire  _T_202 = _T_167 == 37'h0; // @[exu_div_ctl.scala 691:97]
+  wire  _T_203 = _T_177 & _T_202; // @[exu_div_ctl.scala 691:83]
+  wire  _T_204 = _T_199 | _T_203; // @[exu_div_ctl.scala 691:59]
+  wire [35:0] _T_122 = {r_ff,a_ff[32:30]}; // @[Cat.scala 29:58]
+  wire [35:0] _T_124 = {b_ff[34:0],1'h0}; // @[Cat.scala 29:58]
+  wire [35:0] _T_126 = _T_122 + _T_124; // @[exu_div_ctl.scala 683:48]
+  wire [35:0] adder3_out = _T_126 + b_ff[35:0]; // @[exu_div_ctl.scala 683:70]
+  wire  _T_206 = ~adder3_out[35]; // @[exu_div_ctl.scala 692:23]
+  wire  _T_207 = _T_206 ^ control_ff[2]; // @[exu_div_ctl.scala 692:39]
+  wire  _T_210 = adder3_out == 36'h0; // @[exu_div_ctl.scala 692:97]
+  wire  _T_211 = _T_177 & _T_210; // @[exu_div_ctl.scala 692:83]
+  wire  _T_212 = _T_207 | _T_211; // @[exu_div_ctl.scala 692:59]
+  wire [34:0] _T_116 = {r_ff[31:0],a_ff[32:30]}; // @[Cat.scala 29:58]
+  wire [34:0] _T_118 = {b_ff[33:0],1'h0}; // @[Cat.scala 29:58]
+  wire [34:0] adder2_out = _T_116 + _T_118; // @[exu_div_ctl.scala 682:48]
+  wire  _T_214 = ~adder2_out[34]; // @[exu_div_ctl.scala 693:23]
+  wire  _T_215 = _T_214 ^ control_ff[2]; // @[exu_div_ctl.scala 693:39]
+  wire  _T_218 = adder2_out == 35'h0; // @[exu_div_ctl.scala 693:97]
+  wire  _T_219 = _T_177 & _T_218; // @[exu_div_ctl.scala 693:83]
+  wire  _T_220 = _T_215 | _T_219; // @[exu_div_ctl.scala 693:59]
+  wire [33:0] _T_111 = {r_ff[30:0],a_ff[32:30]}; // @[Cat.scala 29:58]
+  wire [33:0] adder1_out = _T_111 + b_ff[33:0]; // @[exu_div_ctl.scala 681:48]
+  wire  _T_222 = ~adder1_out[33]; // @[exu_div_ctl.scala 694:23]
+  wire  _T_223 = _T_222 ^ control_ff[2]; // @[exu_div_ctl.scala 694:39]
+  wire  _T_226 = adder1_out == 34'h0; // @[exu_div_ctl.scala 694:97]
+  wire  _T_227 = _T_177 & _T_226; // @[exu_div_ctl.scala 694:83]
+  wire  _T_228 = _T_223 | _T_227; // @[exu_div_ctl.scala 694:59]
+  wire [7:0] quotient_raw = {_T_180,_T_188,_T_196,_T_204,_T_212,_T_220,_T_228,1'h0}; // @[Cat.scala 29:58]
+  wire  _T_238 = quotient_raw[7] | quotient_raw[6]; // @[exu_div_ctl.scala 695:43]
+  wire  _T_240 = _T_238 | quotient_raw[5]; // @[exu_div_ctl.scala 695:62]
+  wire  _T_242 = _T_240 | quotient_raw[4]; // @[exu_div_ctl.scala 695:80]
+  wire  _T_247 = ~quotient_raw[4]; // @[exu_div_ctl.scala 696:63]
+  wire  _T_249 = _T_247 & quotient_raw[3]; // @[exu_div_ctl.scala 696:80]
+  wire  _T_250 = _T_238 | _T_249; // @[exu_div_ctl.scala 696:61]
+  wire  _T_252 = ~quotient_raw[3]; // @[exu_div_ctl.scala 696:101]
+  wire  _T_254 = _T_252 & quotient_raw[2]; // @[exu_div_ctl.scala 696:118]
+  wire  _T_255 = _T_250 | _T_254; // @[exu_div_ctl.scala 696:99]
+  wire  _T_259 = quotient_raw[6] & quotient_raw[5]; // @[exu_div_ctl.scala 697:61]
+  wire  _T_260 = quotient_raw[7] | _T_259; // @[exu_div_ctl.scala 697:42]
+  wire  _T_265 = _T_260 | _T_249; // @[exu_div_ctl.scala 697:79]
+  wire  _T_267 = ~quotient_raw[2]; // @[exu_div_ctl.scala 697:119]
+  wire  _T_269 = _T_267 & quotient_raw[1]; // @[exu_div_ctl.scala 697:136]
+  wire  _T_270 = _T_265 | _T_269; // @[exu_div_ctl.scala 697:117]
+  wire [2:0] quotient_new = {_T_242,_T_255,_T_270}; // @[Cat.scala 29:58]
+  wire  _T_85 = quotient_new == 3'h0; // @[exu_div_ctl.scala 673:61]
+  wire  _T_86 = running_state & _T_85; // @[exu_div_ctl.scala 673:45]
+  wire  r_restore_sel = _T_86 & _T_67; // @[exu_div_ctl.scala 673:70]
+  wire  _T_88 = quotient_new == 3'h1; // @[exu_div_ctl.scala 674:61]
+  wire  _T_89 = running_state & _T_88; // @[exu_div_ctl.scala 674:45]
+  wire  r_adder1_sel = _T_89 & _T_67; // @[exu_div_ctl.scala 674:70]
+  wire  _T_91 = quotient_new == 3'h2; // @[exu_div_ctl.scala 675:61]
+  wire  _T_92 = running_state & _T_91; // @[exu_div_ctl.scala 675:45]
+  wire  r_adder2_sel = _T_92 & _T_67; // @[exu_div_ctl.scala 675:70]
+  wire  _T_94 = quotient_new == 3'h3; // @[exu_div_ctl.scala 676:61]
+  wire  _T_95 = running_state & _T_94; // @[exu_div_ctl.scala 676:45]
+  wire  r_adder3_sel = _T_95 & _T_67; // @[exu_div_ctl.scala 676:70]
+  wire  _T_97 = quotient_new == 3'h4; // @[exu_div_ctl.scala 677:61]
+  wire  _T_98 = running_state & _T_97; // @[exu_div_ctl.scala 677:45]
+  wire  r_adder4_sel = _T_98 & _T_67; // @[exu_div_ctl.scala 677:70]
+  wire  _T_100 = quotient_new == 3'h5; // @[exu_div_ctl.scala 678:61]
+  wire  _T_101 = running_state & _T_100; // @[exu_div_ctl.scala 678:45]
+  wire  r_adder5_sel = _T_101 & _T_67; // @[exu_div_ctl.scala 678:70]
+  wire  _T_103 = quotient_new == 3'h6; // @[exu_div_ctl.scala 679:61]
+  wire  _T_104 = running_state & _T_103; // @[exu_div_ctl.scala 679:45]
+  wire  r_adder6_sel = _T_104 & _T_67; // @[exu_div_ctl.scala 679:70]
+  reg [31:0] q_ff; // @[Reg.scala 27:20]
+  wire [31:0] _T_274 = twos_comp_q_sel ? q_ff : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_275 = b_twos_comp ? b_ff[31:0] : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] twos_comp_in = _T_274 | _T_275; // @[Mux.scala 27:72]
+  wire  _T_279 = |twos_comp_in[0]; // @[lib.scala 428:35]
+  wire  _T_281 = ~twos_comp_in[1]; // @[lib.scala 428:40]
+  wire  _T_283 = _T_279 ? _T_281 : twos_comp_in[1]; // @[lib.scala 428:23]
+  wire  _T_285 = |twos_comp_in[1:0]; // @[lib.scala 428:35]
+  wire  _T_287 = ~twos_comp_in[2]; // @[lib.scala 428:40]
+  wire  _T_289 = _T_285 ? _T_287 : twos_comp_in[2]; // @[lib.scala 428:23]
+  wire  _T_291 = |twos_comp_in[2:0]; // @[lib.scala 428:35]
+  wire  _T_293 = ~twos_comp_in[3]; // @[lib.scala 428:40]
+  wire  _T_295 = _T_291 ? _T_293 : twos_comp_in[3]; // @[lib.scala 428:23]
+  wire  _T_297 = |twos_comp_in[3:0]; // @[lib.scala 428:35]
+  wire  _T_299 = ~twos_comp_in[4]; // @[lib.scala 428:40]
+  wire  _T_301 = _T_297 ? _T_299 : twos_comp_in[4]; // @[lib.scala 428:23]
+  wire  _T_303 = |twos_comp_in[4:0]; // @[lib.scala 428:35]
+  wire  _T_305 = ~twos_comp_in[5]; // @[lib.scala 428:40]
+  wire  _T_307 = _T_303 ? _T_305 : twos_comp_in[5]; // @[lib.scala 428:23]
+  wire  _T_309 = |twos_comp_in[5:0]; // @[lib.scala 428:35]
+  wire  _T_311 = ~twos_comp_in[6]; // @[lib.scala 428:40]
+  wire  _T_313 = _T_309 ? _T_311 : twos_comp_in[6]; // @[lib.scala 428:23]
+  wire  _T_315 = |twos_comp_in[6:0]; // @[lib.scala 428:35]
+  wire  _T_317 = ~twos_comp_in[7]; // @[lib.scala 428:40]
+  wire  _T_319 = _T_315 ? _T_317 : twos_comp_in[7]; // @[lib.scala 428:23]
+  wire  _T_321 = |twos_comp_in[7:0]; // @[lib.scala 428:35]
+  wire  _T_323 = ~twos_comp_in[8]; // @[lib.scala 428:40]
+  wire  _T_325 = _T_321 ? _T_323 : twos_comp_in[8]; // @[lib.scala 428:23]
+  wire  _T_327 = |twos_comp_in[8:0]; // @[lib.scala 428:35]
+  wire  _T_329 = ~twos_comp_in[9]; // @[lib.scala 428:40]
+  wire  _T_331 = _T_327 ? _T_329 : twos_comp_in[9]; // @[lib.scala 428:23]
+  wire  _T_333 = |twos_comp_in[9:0]; // @[lib.scala 428:35]
+  wire  _T_335 = ~twos_comp_in[10]; // @[lib.scala 428:40]
+  wire  _T_337 = _T_333 ? _T_335 : twos_comp_in[10]; // @[lib.scala 428:23]
+  wire  _T_339 = |twos_comp_in[10:0]; // @[lib.scala 428:35]
+  wire  _T_341 = ~twos_comp_in[11]; // @[lib.scala 428:40]
+  wire  _T_343 = _T_339 ? _T_341 : twos_comp_in[11]; // @[lib.scala 428:23]
+  wire  _T_345 = |twos_comp_in[11:0]; // @[lib.scala 428:35]
+  wire  _T_347 = ~twos_comp_in[12]; // @[lib.scala 428:40]
+  wire  _T_349 = _T_345 ? _T_347 : twos_comp_in[12]; // @[lib.scala 428:23]
+  wire  _T_351 = |twos_comp_in[12:0]; // @[lib.scala 428:35]
+  wire  _T_353 = ~twos_comp_in[13]; // @[lib.scala 428:40]
+  wire  _T_355 = _T_351 ? _T_353 : twos_comp_in[13]; // @[lib.scala 428:23]
+  wire  _T_357 = |twos_comp_in[13:0]; // @[lib.scala 428:35]
+  wire  _T_359 = ~twos_comp_in[14]; // @[lib.scala 428:40]
+  wire  _T_361 = _T_357 ? _T_359 : twos_comp_in[14]; // @[lib.scala 428:23]
+  wire  _T_363 = |twos_comp_in[14:0]; // @[lib.scala 428:35]
+  wire  _T_365 = ~twos_comp_in[15]; // @[lib.scala 428:40]
+  wire  _T_367 = _T_363 ? _T_365 : twos_comp_in[15]; // @[lib.scala 428:23]
+  wire  _T_369 = |twos_comp_in[15:0]; // @[lib.scala 428:35]
+  wire  _T_371 = ~twos_comp_in[16]; // @[lib.scala 428:40]
+  wire  _T_373 = _T_369 ? _T_371 : twos_comp_in[16]; // @[lib.scala 428:23]
+  wire  _T_375 = |twos_comp_in[16:0]; // @[lib.scala 428:35]
+  wire  _T_377 = ~twos_comp_in[17]; // @[lib.scala 428:40]
+  wire  _T_379 = _T_375 ? _T_377 : twos_comp_in[17]; // @[lib.scala 428:23]
+  wire  _T_381 = |twos_comp_in[17:0]; // @[lib.scala 428:35]
+  wire  _T_383 = ~twos_comp_in[18]; // @[lib.scala 428:40]
+  wire  _T_385 = _T_381 ? _T_383 : twos_comp_in[18]; // @[lib.scala 428:23]
+  wire  _T_387 = |twos_comp_in[18:0]; // @[lib.scala 428:35]
+  wire  _T_389 = ~twos_comp_in[19]; // @[lib.scala 428:40]
+  wire  _T_391 = _T_387 ? _T_389 : twos_comp_in[19]; // @[lib.scala 428:23]
+  wire  _T_393 = |twos_comp_in[19:0]; // @[lib.scala 428:35]
+  wire  _T_395 = ~twos_comp_in[20]; // @[lib.scala 428:40]
+  wire  _T_397 = _T_393 ? _T_395 : twos_comp_in[20]; // @[lib.scala 428:23]
+  wire  _T_399 = |twos_comp_in[20:0]; // @[lib.scala 428:35]
+  wire  _T_401 = ~twos_comp_in[21]; // @[lib.scala 428:40]
+  wire  _T_403 = _T_399 ? _T_401 : twos_comp_in[21]; // @[lib.scala 428:23]
+  wire  _T_405 = |twos_comp_in[21:0]; // @[lib.scala 428:35]
+  wire  _T_407 = ~twos_comp_in[22]; // @[lib.scala 428:40]
+  wire  _T_409 = _T_405 ? _T_407 : twos_comp_in[22]; // @[lib.scala 428:23]
+  wire  _T_411 = |twos_comp_in[22:0]; // @[lib.scala 428:35]
+  wire  _T_413 = ~twos_comp_in[23]; // @[lib.scala 428:40]
+  wire  _T_415 = _T_411 ? _T_413 : twos_comp_in[23]; // @[lib.scala 428:23]
+  wire  _T_417 = |twos_comp_in[23:0]; // @[lib.scala 428:35]
+  wire  _T_419 = ~twos_comp_in[24]; // @[lib.scala 428:40]
+  wire  _T_421 = _T_417 ? _T_419 : twos_comp_in[24]; // @[lib.scala 428:23]
+  wire  _T_423 = |twos_comp_in[24:0]; // @[lib.scala 428:35]
+  wire  _T_425 = ~twos_comp_in[25]; // @[lib.scala 428:40]
+  wire  _T_427 = _T_423 ? _T_425 : twos_comp_in[25]; // @[lib.scala 428:23]
+  wire  _T_429 = |twos_comp_in[25:0]; // @[lib.scala 428:35]
+  wire  _T_431 = ~twos_comp_in[26]; // @[lib.scala 428:40]
+  wire  _T_433 = _T_429 ? _T_431 : twos_comp_in[26]; // @[lib.scala 428:23]
+  wire  _T_435 = |twos_comp_in[26:0]; // @[lib.scala 428:35]
+  wire  _T_437 = ~twos_comp_in[27]; // @[lib.scala 428:40]
+  wire  _T_439 = _T_435 ? _T_437 : twos_comp_in[27]; // @[lib.scala 428:23]
+  wire  _T_441 = |twos_comp_in[27:0]; // @[lib.scala 428:35]
+  wire  _T_443 = ~twos_comp_in[28]; // @[lib.scala 428:40]
+  wire  _T_445 = _T_441 ? _T_443 : twos_comp_in[28]; // @[lib.scala 428:23]
+  wire  _T_447 = |twos_comp_in[28:0]; // @[lib.scala 428:35]
+  wire  _T_449 = ~twos_comp_in[29]; // @[lib.scala 428:40]
+  wire  _T_451 = _T_447 ? _T_449 : twos_comp_in[29]; // @[lib.scala 428:23]
+  wire  _T_453 = |twos_comp_in[29:0]; // @[lib.scala 428:35]
+  wire  _T_455 = ~twos_comp_in[30]; // @[lib.scala 428:40]
+  wire  _T_457 = _T_453 ? _T_455 : twos_comp_in[30]; // @[lib.scala 428:23]
+  wire  _T_459 = |twos_comp_in[30:0]; // @[lib.scala 428:35]
+  wire  _T_461 = ~twos_comp_in[31]; // @[lib.scala 428:40]
+  wire  _T_463 = _T_459 ? _T_461 : twos_comp_in[31]; // @[lib.scala 428:23]
+  wire [6:0] _T_469 = {_T_319,_T_313,_T_307,_T_301,_T_295,_T_289,_T_283}; // @[lib.scala 430:14]
+  wire [14:0] _T_477 = {_T_367,_T_361,_T_355,_T_349,_T_343,_T_337,_T_331,_T_325,_T_469}; // @[lib.scala 430:14]
+  wire [7:0] _T_484 = {_T_415,_T_409,_T_403,_T_397,_T_391,_T_385,_T_379,_T_373}; // @[lib.scala 430:14]
+  wire [30:0] _T_493 = {_T_463,_T_457,_T_451,_T_445,_T_439,_T_433,_T_427,_T_421,_T_484,_T_477}; // @[lib.scala 430:14]
+  wire [31:0] twos_comp_out = {_T_493,twos_comp_in[0]}; // @[Cat.scala 29:58]
+  wire  _T_495 = ~a_shift; // @[exu_div_ctl.scala 705:6]
+  wire  _T_497 = _T_495 & _T_67; // @[exu_div_ctl.scala 705:15]
+  wire  _T_500 = io_signed_in & io_dividend_in[31]; // @[exu_div_ctl.scala 705:63]
+  wire [32:0] _T_502 = {_T_500,io_dividend_in}; // @[Cat.scala 29:58]
+  wire [32:0] _T_504 = {a_ff[29:0],3'h0}; // @[Cat.scala 29:58]
+  wire [65:0] ar_shifted = _T_71[65:0]; // @[exu_div_ctl.scala 666:28]
+  wire [32:0] _T_506 = _T_497 ? _T_502 : 33'h0; // @[Mux.scala 27:72]
+  wire [32:0] _T_507 = a_shift ? _T_504 : 33'h0; // @[Mux.scala 27:72]
+  wire [32:0] _T_508 = shortq_enable_ff ? ar_shifted[32:0] : 33'h0; // @[Mux.scala 27:72]
+  wire [32:0] _T_509 = _T_506 | _T_507; // @[Mux.scala 27:72]
+  wire [32:0] a_in = _T_509 | _T_508; // @[Mux.scala 27:72]
+  wire  _T_511 = ~b_twos_comp; // @[exu_div_ctl.scala 710:5]
+  wire  _T_513 = io_signed_in & io_divisor_in[31]; // @[exu_div_ctl.scala 710:63]
+  wire [32:0] _T_515 = {_T_513,io_divisor_in}; // @[Cat.scala 29:58]
+  wire  _T_516 = ~control_ff[1]; // @[exu_div_ctl.scala 711:49]
+  wire [32:0] _T_518 = {_T_516,_T_493,twos_comp_in[0]}; // @[Cat.scala 29:58]
+  wire [32:0] _T_519 = _T_511 ? _T_515 : 33'h0; // @[Mux.scala 27:72]
+  wire [32:0] _T_520 = b_twos_comp ? _T_518 : 33'h0; // @[Mux.scala 27:72]
+  wire [32:0] b_in = _T_519 | _T_520; // @[Mux.scala 27:72]
+  wire [32:0] _T_524 = {r_ff[29:0],a_ff[32:30]}; // @[Cat.scala 29:58]
+  wire [32:0] _T_534 = {1'h0,a_ff[31:0]}; // @[Cat.scala 29:58]
+  wire [32:0] _T_535 = r_sign_sel ? 33'h1ffffffff : 33'h0; // @[Mux.scala 27:72]
+  wire [32:0] _T_536 = r_restore_sel ? _T_524 : 33'h0; // @[Mux.scala 27:72]
+  wire [32:0] _T_537 = r_adder1_sel ? adder1_out[32:0] : 33'h0; // @[Mux.scala 27:72]
+  wire [32:0] _T_538 = r_adder2_sel ? adder2_out[32:0] : 33'h0; // @[Mux.scala 27:72]
+  wire [32:0] _T_539 = r_adder3_sel ? adder3_out[32:0] : 33'h0; // @[Mux.scala 27:72]
+  wire [32:0] _T_540 = r_adder4_sel ? _T_167[32:0] : 33'h0; // @[Mux.scala 27:72]
+  wire [32:0] _T_541 = r_adder5_sel ? adder5_out[32:0] : 33'h0; // @[Mux.scala 27:72]
+  wire [32:0] _T_542 = r_adder6_sel ? _T_171[32:0] : 33'h0; // @[Mux.scala 27:72]
+  wire [32:0] _T_543 = r_adder6_sel ? adder7_out[32:0] : 33'h0; // @[Mux.scala 27:72]
+  wire [32:0] _T_544 = shortq_enable_ff ? ar_shifted[65:33] : 33'h0; // @[Mux.scala 27:72]
+  wire [32:0] _T_545 = by_zero_case ? _T_534 : 33'h0; // @[Mux.scala 27:72]
+  wire [32:0] _T_546 = _T_535 | _T_536; // @[Mux.scala 27:72]
+  wire [32:0] _T_547 = _T_546 | _T_537; // @[Mux.scala 27:72]
+  wire [32:0] _T_548 = _T_547 | _T_538; // @[Mux.scala 27:72]
+  wire [32:0] _T_549 = _T_548 | _T_539; // @[Mux.scala 27:72]
+  wire [32:0] _T_550 = _T_549 | _T_540; // @[Mux.scala 27:72]
+  wire [32:0] _T_551 = _T_550 | _T_541; // @[Mux.scala 27:72]
+  wire [32:0] _T_552 = _T_551 | _T_542; // @[Mux.scala 27:72]
+  wire [32:0] _T_553 = _T_552 | _T_543; // @[Mux.scala 27:72]
+  wire [32:0] _T_554 = _T_553 | _T_544; // @[Mux.scala 27:72]
+  wire [32:0] r_in = _T_554 | _T_545; // @[Mux.scala 27:72]
+  wire [31:0] _T_558 = {q_ff[28:0],_T_242,_T_255,_T_270}; // @[Cat.scala 29:58]
+  wire  _T_581 = ~b_ff[3]; // @[exu_div_ctl.scala 740:70]
+  wire  _T_583 = ~b_ff[2]; // @[exu_div_ctl.scala 740:70]
+  wire  _T_586 = _T_581 & _T_583; // @[exu_div_ctl.scala 740:95]
+  wire  _T_585 = ~b_ff[1]; // @[exu_div_ctl.scala 740:70]
+  wire  _T_587 = _T_586 & _T_585; // @[exu_div_ctl.scala 740:95]
+  wire  _T_588 = a_ff[3] & _T_587; // @[exu_div_ctl.scala 741:11]
+  wire  _T_595 = a_ff[3] & _T_586; // @[exu_div_ctl.scala 741:11]
+  wire  _T_597 = ~b_ff[0]; // @[exu_div_ctl.scala 746:33]
+  wire  _T_598 = _T_595 & _T_597; // @[exu_div_ctl.scala 746:31]
+  wire  _T_608 = a_ff[2] & _T_587; // @[exu_div_ctl.scala 741:11]
+  wire  _T_609 = _T_598 | _T_608; // @[exu_div_ctl.scala 746:42]
+  wire  _T_612 = a_ff[3] & a_ff[2]; // @[exu_div_ctl.scala 739:95]
+  wire  _T_618 = _T_612 & _T_586; // @[exu_div_ctl.scala 741:11]
+  wire  _T_619 = _T_609 | _T_618; // @[exu_div_ctl.scala 746:75]
+  wire  _T_626 = a_ff[2] & _T_586; // @[exu_div_ctl.scala 741:11]
+  wire  _T_629 = _T_626 & _T_597; // @[exu_div_ctl.scala 748:31]
+  wire  _T_639 = a_ff[1] & _T_587; // @[exu_div_ctl.scala 741:11]
+  wire  _T_640 = _T_629 | _T_639; // @[exu_div_ctl.scala 748:42]
+  wire  _T_646 = _T_581 & _T_585; // @[exu_div_ctl.scala 740:95]
+  wire  _T_647 = a_ff[3] & _T_646; // @[exu_div_ctl.scala 741:11]
+  wire  _T_650 = _T_647 & _T_597; // @[exu_div_ctl.scala 748:106]
+  wire  _T_651 = _T_640 | _T_650; // @[exu_div_ctl.scala 748:78]
+  wire  _T_654 = ~a_ff[2]; // @[exu_div_ctl.scala 739:70]
+  wire  _T_655 = a_ff[3] & _T_654; // @[exu_div_ctl.scala 739:95]
+  wire  _T_663 = _T_586 & b_ff[1]; // @[exu_div_ctl.scala 740:95]
+  wire  _T_664 = _T_663 & b_ff[0]; // @[exu_div_ctl.scala 740:95]
+  wire  _T_665 = _T_655 & _T_664; // @[exu_div_ctl.scala 741:11]
+  wire  _T_666 = _T_651 | _T_665; // @[exu_div_ctl.scala 748:117]
+  wire  _T_668 = ~a_ff[3]; // @[exu_div_ctl.scala 739:70]
+  wire  _T_671 = _T_668 & a_ff[2]; // @[exu_div_ctl.scala 739:95]
+  wire  _T_672 = _T_671 & a_ff[1]; // @[exu_div_ctl.scala 739:95]
+  wire  _T_678 = _T_672 & _T_586; // @[exu_div_ctl.scala 741:11]
+  wire  _T_679 = _T_666 | _T_678; // @[exu_div_ctl.scala 749:44]
+  wire  _T_685 = _T_612 & _T_581; // @[exu_div_ctl.scala 741:11]
+  wire  _T_688 = _T_685 & _T_597; // @[exu_div_ctl.scala 749:107]
+  wire  _T_689 = _T_679 | _T_688; // @[exu_div_ctl.scala 749:80]
+  wire  _T_698 = _T_581 & b_ff[2]; // @[exu_div_ctl.scala 740:95]
+  wire  _T_699 = _T_698 & _T_585; // @[exu_div_ctl.scala 740:95]
+  wire  _T_700 = _T_612 & _T_699; // @[exu_div_ctl.scala 741:11]
+  wire  _T_701 = _T_689 | _T_700; // @[exu_div_ctl.scala 749:119]
+  wire  _T_704 = a_ff[3] & a_ff[1]; // @[exu_div_ctl.scala 739:95]
+  wire  _T_710 = _T_704 & _T_646; // @[exu_div_ctl.scala 741:11]
+  wire  _T_711 = _T_701 | _T_710; // @[exu_div_ctl.scala 750:44]
+  wire  _T_716 = _T_612 & a_ff[1]; // @[exu_div_ctl.scala 739:95]
+  wire  _T_721 = _T_716 & _T_698; // @[exu_div_ctl.scala 741:11]
+  wire  _T_722 = _T_711 | _T_721; // @[exu_div_ctl.scala 750:79]
+  wire  _T_726 = a_ff[2] & a_ff[1]; // @[exu_div_ctl.scala 739:95]
+  wire  _T_727 = _T_726 & a_ff[0]; // @[exu_div_ctl.scala 739:95]
+  wire  _T_733 = _T_727 & _T_646; // @[exu_div_ctl.scala 741:11]
+  wire  _T_739 = _T_655 & a_ff[0]; // @[exu_div_ctl.scala 739:95]
+  wire  _T_744 = _T_581 & b_ff[1]; // @[exu_div_ctl.scala 740:95]
+  wire  _T_745 = _T_744 & b_ff[0]; // @[exu_div_ctl.scala 740:95]
+  wire  _T_746 = _T_739 & _T_745; // @[exu_div_ctl.scala 741:11]
+  wire  _T_747 = _T_733 | _T_746; // @[exu_div_ctl.scala 752:45]
+  wire  _T_754 = a_ff[2] & _T_646; // @[exu_div_ctl.scala 741:11]
+  wire  _T_757 = _T_754 & _T_597; // @[exu_div_ctl.scala 752:114]
+  wire  _T_758 = _T_747 | _T_757; // @[exu_div_ctl.scala 752:86]
+  wire  _T_765 = a_ff[1] & _T_586; // @[exu_div_ctl.scala 741:11]
+  wire  _T_768 = _T_765 & _T_597; // @[exu_div_ctl.scala 753:33]
+  wire  _T_769 = _T_758 | _T_768; // @[exu_div_ctl.scala 752:129]
+  wire  _T_779 = a_ff[0] & _T_587; // @[exu_div_ctl.scala 741:11]
+  wire  _T_780 = _T_769 | _T_779; // @[exu_div_ctl.scala 753:47]
+  wire  _T_785 = ~a_ff[1]; // @[exu_div_ctl.scala 739:70]
+  wire  _T_787 = _T_671 & _T_785; // @[exu_div_ctl.scala 739:95]
+  wire  _T_797 = _T_787 & _T_664; // @[exu_div_ctl.scala 741:11]
+  wire  _T_798 = _T_780 | _T_797; // @[exu_div_ctl.scala 753:88]
+  wire  _T_807 = _T_672 & _T_581; // @[exu_div_ctl.scala 741:11]
+  wire  _T_810 = _T_807 & _T_597; // @[exu_div_ctl.scala 754:36]
+  wire  _T_811 = _T_798 | _T_810; // @[exu_div_ctl.scala 753:131]
+  wire  _T_817 = _T_583 & _T_585; // @[exu_div_ctl.scala 740:95]
+  wire  _T_818 = a_ff[3] & _T_817; // @[exu_div_ctl.scala 741:11]
+  wire  _T_821 = _T_818 & _T_597; // @[exu_div_ctl.scala 754:76]
+  wire  _T_822 = _T_811 | _T_821; // @[exu_div_ctl.scala 754:47]
+  wire  _T_832 = _T_698 & b_ff[1]; // @[exu_div_ctl.scala 740:95]
+  wire  _T_833 = _T_655 & _T_832; // @[exu_div_ctl.scala 741:11]
+  wire  _T_834 = _T_822 | _T_833; // @[exu_div_ctl.scala 754:88]
+  wire  _T_848 = _T_672 & _T_699; // @[exu_div_ctl.scala 741:11]
+  wire  _T_849 = _T_834 | _T_848; // @[exu_div_ctl.scala 754:131]
+  wire  _T_855 = _T_671 & a_ff[0]; // @[exu_div_ctl.scala 739:95]
+  wire  _T_861 = _T_855 & _T_646; // @[exu_div_ctl.scala 741:11]
+  wire  _T_862 = _T_849 | _T_861; // @[exu_div_ctl.scala 755:47]
+  wire  _T_869 = _T_655 & _T_785; // @[exu_div_ctl.scala 739:95]
+  wire  _T_875 = _T_698 & b_ff[0]; // @[exu_div_ctl.scala 740:95]
+  wire  _T_876 = _T_869 & _T_875; // @[exu_div_ctl.scala 741:11]
+  wire  _T_877 = _T_862 | _T_876; // @[exu_div_ctl.scala 755:88]
+  wire  _T_882 = _T_654 & a_ff[1]; // @[exu_div_ctl.scala 739:95]
+  wire  _T_883 = _T_882 & a_ff[0]; // @[exu_div_ctl.scala 739:95]
+  wire  _T_889 = _T_883 & _T_586; // @[exu_div_ctl.scala 741:11]
+  wire  _T_890 = _T_877 | _T_889; // @[exu_div_ctl.scala 755:131]
+  wire  _T_896 = _T_612 & _T_585; // @[exu_div_ctl.scala 741:11]
+  wire  _T_899 = _T_896 & _T_597; // @[exu_div_ctl.scala 756:75]
+  wire  _T_900 = _T_890 | _T_899; // @[exu_div_ctl.scala 756:47]
+  wire  _T_908 = _T_672 & a_ff[0]; // @[exu_div_ctl.scala 739:95]
+  wire  _T_913 = _T_908 & _T_698; // @[exu_div_ctl.scala 741:11]
+  wire  _T_914 = _T_900 | _T_913; // @[exu_div_ctl.scala 756:88]
+  wire  _T_921 = b_ff[3] & _T_583; // @[exu_div_ctl.scala 740:95]
+  wire  _T_922 = _T_612 & _T_921; // @[exu_div_ctl.scala 741:11]
+  wire  _T_923 = _T_914 | _T_922; // @[exu_div_ctl.scala 756:131]
+  wire  _T_933 = _T_921 & _T_585; // @[exu_div_ctl.scala 740:95]
+  wire  _T_934 = _T_704 & _T_933; // @[exu_div_ctl.scala 741:11]
+  wire  _T_935 = _T_923 | _T_934; // @[exu_div_ctl.scala 757:47]
+  wire  _T_938 = a_ff[3] & a_ff[0]; // @[exu_div_ctl.scala 739:95]
+  wire  _T_944 = _T_938 & _T_817; // @[exu_div_ctl.scala 741:11]
+  wire  _T_945 = _T_935 | _T_944; // @[exu_div_ctl.scala 757:88]
+  wire  _T_949 = a_ff[3] & _T_785; // @[exu_div_ctl.scala 739:95]
+  wire  _T_957 = _T_832 & b_ff[0]; // @[exu_div_ctl.scala 740:95]
+  wire  _T_958 = _T_949 & _T_957; // @[exu_div_ctl.scala 741:11]
+  wire  _T_959 = _T_945 | _T_958; // @[exu_div_ctl.scala 757:131]
+  wire  _T_966 = _T_716 & b_ff[3]; // @[exu_div_ctl.scala 741:11]
+  wire  _T_969 = _T_966 & _T_597; // @[exu_div_ctl.scala 758:77]
+  wire  _T_970 = _T_959 | _T_969; // @[exu_div_ctl.scala 758:47]
+  wire  _T_979 = b_ff[3] & _T_585; // @[exu_div_ctl.scala 740:95]
+  wire  _T_980 = _T_716 & _T_979; // @[exu_div_ctl.scala 741:11]
+  wire  _T_981 = _T_970 | _T_980; // @[exu_div_ctl.scala 758:88]
+  wire  _T_986 = _T_612 & a_ff[0]; // @[exu_div_ctl.scala 739:95]
+  wire  _T_991 = _T_986 & _T_979; // @[exu_div_ctl.scala 741:11]
+  wire  _T_992 = _T_981 | _T_991; // @[exu_div_ctl.scala 758:131]
+  wire  _T_998 = _T_655 & a_ff[1]; // @[exu_div_ctl.scala 739:95]
+  wire  _T_1003 = _T_998 & _T_744; // @[exu_div_ctl.scala 741:11]
+  wire  _T_1004 = _T_992 | _T_1003; // @[exu_div_ctl.scala 759:47]
+  wire  _T_1009 = _T_704 & a_ff[0]; // @[exu_div_ctl.scala 739:95]
+  wire  _T_1012 = _T_1009 & _T_583; // @[exu_div_ctl.scala 741:11]
+  wire  _T_1013 = _T_1004 | _T_1012; // @[exu_div_ctl.scala 759:88]
+  wire  _T_1020 = _T_716 & a_ff[0]; // @[exu_div_ctl.scala 739:95]
+  wire  _T_1022 = _T_1020 & b_ff[3]; // @[exu_div_ctl.scala 741:11]
+  wire  _T_1023 = _T_1013 | _T_1022; // @[exu_div_ctl.scala 759:131]
+  wire  _T_1029 = _T_704 & _T_583; // @[exu_div_ctl.scala 741:11]
+  wire  _T_1032 = _T_1029 & _T_597; // @[exu_div_ctl.scala 760:74]
+  wire  _T_1033 = _T_1023 | _T_1032; // @[exu_div_ctl.scala 760:47]
+  wire [31:0] _T_559 = {28'h0,_T_588,_T_619,_T_722,_T_1033}; // @[Cat.scala 29:58]
+  wire [31:0] _T_561 = _T_76 ? _T_558 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_562 = smallnum_case ? _T_559 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_563 = by_zero_case ? 32'hffffffff : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_564 = _T_561 | _T_562; // @[Mux.scala 27:72]
+  wire [31:0] q_in = _T_564 | _T_563; // @[Mux.scala 27:72]
+  wire  _T_569 = ~twos_comp_q_sel; // @[exu_div_ctl.scala 734:16]
+  wire  _T_570 = _T_30 & _T_569; // @[exu_div_ctl.scala 734:14]
+  wire [31:0] _T_573 = _T_570 ? q_ff : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_574 = control_ff[0] ? r_ff[31:0] : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_575 = twos_comp_q_sel ? twos_comp_out : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_576 = _T_573 | _T_574; // @[Mux.scala 27:72]
+  wire [33:0] shortq_dividend = {control_ff[2],a_ff}; // @[Cat.scala 29:58]
+  wire  _T_1059 = shortq == 6'h1b; // @[exu_div_ctl.scala 775:58]
+  wire  _T_1060 = shortq == 6'h1a; // @[exu_div_ctl.scala 775:58]
+  wire  _T_1061 = shortq == 6'h19; // @[exu_div_ctl.scala 775:58]
+  wire  _T_1062 = shortq == 6'h18; // @[exu_div_ctl.scala 775:58]
+  wire  _T_1063 = shortq == 6'h17; // @[exu_div_ctl.scala 775:58]
+  wire  _T_1064 = shortq == 6'h16; // @[exu_div_ctl.scala 775:58]
+  wire  _T_1065 = shortq == 6'h15; // @[exu_div_ctl.scala 775:58]
+  wire  _T_1066 = shortq == 6'h14; // @[exu_div_ctl.scala 775:58]
+  wire  _T_1067 = shortq == 6'h13; // @[exu_div_ctl.scala 775:58]
+  wire  _T_1068 = shortq == 6'h12; // @[exu_div_ctl.scala 775:58]
+  wire  _T_1069 = shortq == 6'h11; // @[exu_div_ctl.scala 775:58]
+  wire  _T_1070 = shortq == 6'h10; // @[exu_div_ctl.scala 775:58]
+  wire  _T_1071 = shortq == 6'hf; // @[exu_div_ctl.scala 775:58]
+  wire  _T_1072 = shortq == 6'he; // @[exu_div_ctl.scala 775:58]
+  wire  _T_1073 = shortq == 6'hd; // @[exu_div_ctl.scala 775:58]
+  wire  _T_1074 = shortq == 6'hc; // @[exu_div_ctl.scala 775:58]
+  wire  _T_1075 = shortq == 6'hb; // @[exu_div_ctl.scala 775:58]
+  wire  _T_1076 = shortq == 6'ha; // @[exu_div_ctl.scala 775:58]
+  wire  _T_1077 = shortq == 6'h9; // @[exu_div_ctl.scala 775:58]
+  wire  _T_1078 = shortq == 6'h8; // @[exu_div_ctl.scala 775:58]
+  wire  _T_1079 = shortq == 6'h7; // @[exu_div_ctl.scala 775:58]
+  wire  _T_1080 = shortq == 6'h6; // @[exu_div_ctl.scala 775:58]
+  wire  _T_1081 = shortq == 6'h5; // @[exu_div_ctl.scala 775:58]
+  wire  _T_1082 = shortq == 6'h4; // @[exu_div_ctl.scala 775:58]
+  wire  _T_1083 = shortq == 6'h3; // @[exu_div_ctl.scala 775:58]
+  wire  _T_1084 = shortq == 6'h2; // @[exu_div_ctl.scala 775:58]
+  wire  _T_1085 = shortq == 6'h1; // @[exu_div_ctl.scala 775:58]
+  wire  _T_1086 = shortq == 6'h0; // @[exu_div_ctl.scala 775:58]
+  wire [1:0] _T_1091 = _T_1059 ? 2'h3 : 2'h0; // @[Mux.scala 27:72]
+  wire [2:0] _T_1092 = _T_1060 ? 3'h6 : 3'h0; // @[Mux.scala 27:72]
+  wire [2:0] _T_1093 = _T_1061 ? 3'h6 : 3'h0; // @[Mux.scala 27:72]
+  wire [2:0] _T_1094 = _T_1062 ? 3'h6 : 3'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_1095 = _T_1063 ? 4'h9 : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_1096 = _T_1064 ? 4'h9 : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_1097 = _T_1065 ? 4'h9 : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_1098 = _T_1066 ? 4'hc : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_1099 = _T_1067 ? 4'hc : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_1100 = _T_1068 ? 4'hc : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_1101 = _T_1069 ? 4'hf : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_1102 = _T_1070 ? 4'hf : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_1103 = _T_1071 ? 4'hf : 4'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_1104 = _T_1072 ? 5'h12 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_1105 = _T_1073 ? 5'h12 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_1106 = _T_1074 ? 5'h12 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_1107 = _T_1075 ? 5'h15 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_1108 = _T_1076 ? 5'h15 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_1109 = _T_1077 ? 5'h15 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_1110 = _T_1078 ? 5'h18 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_1111 = _T_1079 ? 5'h18 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_1112 = _T_1080 ? 5'h18 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_1113 = _T_1081 ? 5'h1b : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_1114 = _T_1082 ? 5'h1b : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_1115 = _T_1083 ? 5'h1b : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_1116 = _T_1084 ? 5'h1b : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_1117 = _T_1085 ? 5'h1b : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_1118 = _T_1086 ? 5'h1b : 5'h0; // @[Mux.scala 27:72]
+  wire [2:0] _GEN_12 = {{1'd0}, _T_1091}; // @[Mux.scala 27:72]
+  wire [2:0] _T_1123 = _GEN_12 | _T_1092; // @[Mux.scala 27:72]
+  wire [2:0] _T_1124 = _T_1123 | _T_1093; // @[Mux.scala 27:72]
+  wire [2:0] _T_1125 = _T_1124 | _T_1094; // @[Mux.scala 27:72]
+  wire [3:0] _GEN_13 = {{1'd0}, _T_1125}; // @[Mux.scala 27:72]
+  wire [3:0] _T_1126 = _GEN_13 | _T_1095; // @[Mux.scala 27:72]
+  wire [3:0] _T_1127 = _T_1126 | _T_1096; // @[Mux.scala 27:72]
+  wire [3:0] _T_1128 = _T_1127 | _T_1097; // @[Mux.scala 27:72]
+  wire [3:0] _T_1129 = _T_1128 | _T_1098; // @[Mux.scala 27:72]
+  wire [3:0] _T_1130 = _T_1129 | _T_1099; // @[Mux.scala 27:72]
+  wire [3:0] _T_1131 = _T_1130 | _T_1100; // @[Mux.scala 27:72]
+  wire [3:0] _T_1132 = _T_1131 | _T_1101; // @[Mux.scala 27:72]
+  wire [3:0] _T_1133 = _T_1132 | _T_1102; // @[Mux.scala 27:72]
+  wire [3:0] _T_1134 = _T_1133 | _T_1103; // @[Mux.scala 27:72]
+  wire [4:0] _GEN_14 = {{1'd0}, _T_1134}; // @[Mux.scala 27:72]
+  wire [4:0] _T_1135 = _GEN_14 | _T_1104; // @[Mux.scala 27:72]
+  wire [4:0] _T_1136 = _T_1135 | _T_1105; // @[Mux.scala 27:72]
+  wire [4:0] _T_1137 = _T_1136 | _T_1106; // @[Mux.scala 27:72]
+  wire [4:0] _T_1138 = _T_1137 | _T_1107; // @[Mux.scala 27:72]
+  wire [4:0] _T_1139 = _T_1138 | _T_1108; // @[Mux.scala 27:72]
+  wire [4:0] _T_1140 = _T_1139 | _T_1109; // @[Mux.scala 27:72]
+  wire [4:0] _T_1141 = _T_1140 | _T_1110; // @[Mux.scala 27:72]
+  wire [4:0] _T_1142 = _T_1141 | _T_1111; // @[Mux.scala 27:72]
+  wire [4:0] _T_1143 = _T_1142 | _T_1112; // @[Mux.scala 27:72]
+  wire [4:0] _T_1144 = _T_1143 | _T_1113; // @[Mux.scala 27:72]
+  wire [4:0] _T_1145 = _T_1144 | _T_1114; // @[Mux.scala 27:72]
+  wire [4:0] _T_1146 = _T_1145 | _T_1115; // @[Mux.scala 27:72]
+  wire [4:0] _T_1147 = _T_1146 | _T_1116; // @[Mux.scala 27:72]
+  wire [4:0] _T_1148 = _T_1147 | _T_1117; // @[Mux.scala 27:72]
+  wire [4:0] shortq_decode = _T_1148 | _T_1118; // @[Mux.scala 27:72]
+  exu_div_cls a_enc ( // @[exu_div_ctl.scala 763:21]
+    .io_operand(a_enc_io_operand),
+    .io_cls(a_enc_io_cls)
+  );
+  exu_div_cls b_enc ( // @[exu_div_ctl.scala 766:20]
+    .io_operand(b_enc_io_operand),
+    .io_cls(b_enc_io_cls)
+  );
+  rvclkhdr rvclkhdr ( // @[lib.scala 390:23]
+    .io_clk(rvclkhdr_io_clk),
+    .io_en(rvclkhdr_io_en)
+  );
+  rvclkhdr rvclkhdr_1 ( // @[lib.scala 390:23]
+    .io_clk(rvclkhdr_1_io_clk),
+    .io_en(rvclkhdr_1_io_en)
+  );
+  rvclkhdr rvclkhdr_2 ( // @[lib.scala 390:23]
+    .io_clk(rvclkhdr_2_io_clk),
+    .io_en(rvclkhdr_2_io_en)
+  );
+  rvclkhdr rvclkhdr_3 ( // @[lib.scala 390:23]
+    .io_clk(rvclkhdr_3_io_clk),
+    .io_en(rvclkhdr_3_io_en)
+  );
+  rvclkhdr rvclkhdr_4 ( // @[lib.scala 390:23]
+    .io_clk(rvclkhdr_4_io_clk),
+    .io_en(rvclkhdr_4_io_en)
+  );
+  rvclkhdr rvclkhdr_5 ( // @[lib.scala 390:23]
+    .io_clk(rvclkhdr_5_io_clk),
+    .io_en(rvclkhdr_5_io_en)
+  );
+  rvclkhdr rvclkhdr_6 ( // @[lib.scala 390:23]
+    .io_clk(rvclkhdr_6_io_clk),
+    .io_en(rvclkhdr_6_io_en)
+  );
+  rvclkhdr rvclkhdr_7 ( // @[lib.scala 390:23]
+    .io_clk(rvclkhdr_7_io_clk),
+    .io_en(rvclkhdr_7_io_en)
+  );
+  rvclkhdr rvclkhdr_8 ( // @[lib.scala 390:23]
+    .io_clk(rvclkhdr_8_io_clk),
+    .io_en(rvclkhdr_8_io_en)
+  );
+  rvclkhdr rvclkhdr_9 ( // @[lib.scala 390:23]
+    .io_clk(rvclkhdr_9_io_clk),
+    .io_en(rvclkhdr_9_io_en)
+  );
+  rvclkhdr rvclkhdr_10 ( // @[lib.scala 390:23]
+    .io_clk(rvclkhdr_10_io_clk),
+    .io_en(rvclkhdr_10_io_en)
+  );
+  assign io_data_out = _T_576 | _T_575; // @[exu_div_ctl.scala 733:15]
+  assign io_valid_out = finish_ff & _T; // @[exu_div_ctl.scala 732:16]
+  assign a_enc_io_operand = shortq_dividend[32:0]; // @[exu_div_ctl.scala 764:20]
+  assign b_enc_io_operand = b_ff[32:0]; // @[exu_div_ctl.scala 767:20]
+  assign rvclkhdr_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_io_en = _T_47 | finish_ff; // @[lib.scala 393:17]
+  assign rvclkhdr_1_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_1_io_en = _T_47 | finish_ff; // @[lib.scala 393:17]
+  assign rvclkhdr_2_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_2_io_en = _T_47 | finish_ff; // @[lib.scala 393:17]
+  assign rvclkhdr_3_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_3_io_en = _T_47 | finish_ff; // @[lib.scala 393:17]
+  assign rvclkhdr_4_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_4_io_en = _T_47 | finish_ff; // @[lib.scala 393:17]
+  assign rvclkhdr_5_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_5_io_en = _T_47 | finish_ff; // @[lib.scala 393:17]
+  assign rvclkhdr_6_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_6_io_en = _T_47 | finish_ff; // @[lib.scala 393:17]
+  assign rvclkhdr_7_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_7_io_en = io_valid_in | running_state; // @[lib.scala 393:17]
+  assign rvclkhdr_8_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_8_io_en = io_valid_in | b_twos_comp; // @[lib.scala 393:17]
+  assign rvclkhdr_9_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_9_io_en = _T_45 | running_state; // @[lib.scala 393:17]
+  assign rvclkhdr_10_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_10_io_en = _T_45 | running_state; // @[lib.scala 393:17]
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+  integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+  `ifdef RANDOMIZE
+    `ifdef INIT_RANDOM
+      `INIT_RANDOM
+    `endif
+    `ifndef VERILATOR
+      `ifdef RANDOMIZE_DELAY
+        #`RANDOMIZE_DELAY begin end
+      `else
+        #0.002 begin end
+      `endif
+    `endif
+`ifdef RANDOMIZE_REG_INIT
+  _RAND_0 = {1{`RANDOM}};
+  control_ff = _RAND_0[2:0];
+  _RAND_1 = {2{`RANDOM}};
+  b_ff1 = _RAND_1[32:0];
+  _RAND_2 = {1{`RANDOM}};
+  valid_ff = _RAND_2[0:0];
+  _RAND_3 = {2{`RANDOM}};
+  a_ff = _RAND_3[32:0];
+  _RAND_4 = {1{`RANDOM}};
+  count_ff = _RAND_4[6:0];
+  _RAND_5 = {1{`RANDOM}};
+  shortq_enable_ff = _RAND_5[0:0];
+  _RAND_6 = {1{`RANDOM}};
+  finish_ff = _RAND_6[0:0];
+  _RAND_7 = {1{`RANDOM}};
+  _T_1164 = _RAND_7[4:0];
+  _RAND_8 = {1{`RANDOM}};
+  by_zero_case_ff = _RAND_8[0:0];
+  _RAND_9 = {2{`RANDOM}};
+  r_ff = _RAND_9[32:0];
+  _RAND_10 = {1{`RANDOM}};
+  q_ff = _RAND_10[31:0];
+`endif // RANDOMIZE_REG_INIT
+  if (reset) begin
+    control_ff = 3'h0;
+  end
+  if (reset) begin
+    b_ff1 = 33'h0;
+  end
+  if (reset) begin
+    valid_ff = 1'h0;
+  end
+  if (reset) begin
+    a_ff = 33'h0;
+  end
+  if (reset) begin
+    count_ff = 7'h0;
+  end
+  if (reset) begin
+    shortq_enable_ff = 1'h0;
+  end
+  if (reset) begin
+    finish_ff = 1'h0;
+  end
+  if (reset) begin
+    _T_1164 = 5'h0;
+  end
+  if (reset) begin
+    by_zero_case_ff = 1'h0;
+  end
+  if (reset) begin
+    r_ff = 33'h0;
+  end
+  if (reset) begin
+    q_ff = 32'h0;
+  end
+  `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      control_ff <= 3'h0;
+    end else if (misc_enable) begin
+      control_ff <= control_in;
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      b_ff1 <= 33'h0;
+    end else if (b_enable) begin
+      b_ff1 <= b_in;
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      valid_ff <= 1'h0;
+    end else if (misc_enable) begin
+      valid_ff <= valid_ff_in;
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      a_ff <= 33'h0;
+    end else if (a_enable) begin
+      a_ff <= a_in;
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      count_ff <= 7'h0;
+    end else if (misc_enable) begin
+      count_ff <= count_in;
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      shortq_enable_ff <= 1'h0;
+    end else if (misc_enable) begin
+      shortq_enable_ff <= shortq_enable;
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      finish_ff <= 1'h0;
+    end else if (misc_enable) begin
+      finish_ff <= finish;
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      _T_1164 <= 5'h0;
+    end else if (misc_enable) begin
+      if (_T_58) begin
+        _T_1164 <= 5'h0;
+      end else begin
+        _T_1164 <= shortq_decode;
+      end
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      by_zero_case_ff <= 1'h0;
+    end else if (misc_enable) begin
+      by_zero_case_ff <= by_zero_case;
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      r_ff <= 33'h0;
+    end else if (rq_enable) begin
+      r_ff <= r_in;
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      q_ff <= 32'h0;
+    end else if (rq_enable) begin
+      q_ff <= q_in;
+    end
+  end
+endmodule
diff --git a/src/main/scala/exu/exu_div_ctl.scala b/src/main/scala/exu/exu_div_ctl.scala
index de3148fe..94993b53 100644
--- a/src/main/scala/exu/exu_div_ctl.scala
+++ b/src/main/scala/exu/exu_div_ctl.scala
@@ -432,66 +432,29 @@ class exu_div_new_2bit_fullshortq extends Module with RequireAsyncReset with lib
     val data_out              = Output(UInt(32.W))
     val valid_out             = Output(UInt(1.W))
   })
-//  val valid_ff_in          = WireInit(Bool(),init=false.B)
   val valid_ff             = WireInit(Bool(),init=false.B)
-//  val finish_raw           = WireInit(Bool(),init=false.B)
- // val finish               = WireInit(Bool(),init=false.B)
   val finish_ff            = WireInit(Bool(),init=false.B)
- // val running_state        = WireInit(Bool(),init=false.B)
- // val misc_enable          = WireInit(Bool(),init=false.B)
- // val control_in           = WireInit(0.U(3.W))
   val control_ff           = WireInit(0.U(3.W))
- // val dividend_sign_ff     = WireInit(Bool(),init=false.B)
-//  val divisor_sign_ff      = WireInit(Bool(),init=false.B)
-//  val count_enable         = WireInit(Bool(),init=false.B)
-//  val count_in             = WireInit(0.U(7.W))
   val count_ff             = WireInit(0.U(7.W))
   val smallnum             = WireInit(0.U(4.W))
-//  val smallnum_case        = WireInit(Bool(),init=false.B)
- // val a_enable             = WireInit(Bool(),init=false.B)
- // val a_shift              = WireInit(Bool(),init=false.B)
- // val b_enable             = WireInit(Bool(),init=false.B)
- // val b_twos_comp          = WireInit(Bool(),init=false.B)
- // val a_in                 = WireInit(0.U(32.W))
   val a_ff                 = WireInit(0.U(32.W))
-//  val b_in                 = WireInit(0.U(33.W))
   val b_ff1                = WireInit(0.U(33.W))
   val b_ff                 = WireInit(0.U(35.W))
-//  val q_in                 = WireInit(0.U(32.W))
   val q_ff                 = WireInit(0.U(32.W))
- // val r_in                 = WireInit(0.U(32.W))
   val r_ff                 = WireInit(0.U(32.W))
-//  val rq_enable            = WireInit(Bool(),init=false.B)
- // val r_sign_sel           = WireInit(Bool(),init=false.B)
- // val r_restore_sel        = WireInit(Bool(),init=false.B)
-//  val r_adder1_sel         = WireInit(Bool(),init=false.B)
-//  val r_adder2_sel         = WireInit(Bool(),init=false.B)
- // val r_adder3_sel         = WireInit(Bool(),init=false.B)
-//  val twos_comp_q_sel      = WireInit(Bool(),init=false.B)
-//  val twos_comp_b_sel      = WireInit(Bool(),init=false.B)
   val quotient_raw         = WireInit(0.U(4.W))
   val quotient_new         = WireInit(0.U(2.W))
   val shortq_enable        = WireInit(Bool(),init=false.B)
   val shortq_enable_ff     = WireInit(Bool(),init=false.B)
-//  val by_zero_case         = WireInit(Bool(),init=false.B)
   val by_zero_case_ff      = WireInit(Bool(),init=false.B)
- // val twos_comp_in         = WireInit(0.U(32.W))
-//  val twos_comp_out        = WireInit(0.U(32.W))
- // val adder1_out            = WireInit(0.U(33.W))
- // val adder2_out            = WireInit(0.U(34.W))
-//  val adder3_out            = WireInit(0.U(35.W))
   val ar_shifted           = WireInit(0.U(64.W))
- // val shortq               = WireInit(0.U(6.W))
-//  val shortq_shift         = WireInit(0.U(5.W))
   val shortq_shift_ff      = WireInit(0.U(5.W))
- // val shortq_dividend      = WireInit(0.U(33.W))
   val valid_ff_in = io.valid_in & !io.cancel
   val control_in           = Cat((!io.valid_in & control_ff(2)) | (io.valid_in & io.signed_in  & io.dividend_in(31)), (!io.valid_in & control_ff(1)) | (io.valid_in & io.signed_in  &  io.divisor_in(31)), (!io.valid_in & control_ff(0)) | (io.valid_in & io.rem_in))
   val dividend_sign_ff     = control_ff(2)
   val divisor_sign_ff      = control_ff(1)
   val rem_ff               = control_ff(0)
   val by_zero_case         =  valid_ff & (b_ff(31,0) === 0.U)
-
   val smallnum_case =  ((a_ff(31,4) === 0.U) & (b_ff(31,4) === 0.U) & !by_zero_case & !rem_ff & valid_ff & !io.cancel) |
     ((a_ff(31,0) === 0.U) & !by_zero_case & !rem_ff & valid_ff & !io.cancel)
   val running_state        = count_ff.orR() | shortq_enable_ff
@@ -608,12 +571,6 @@ class exu_div_new_2bit_fullshortq extends Module with RequireAsyncReset with lib
   q_ff := rvdffe(q_in, rq_enable,clock,io.scan_mode)
 
 }
-
-object div_main3 extends App {
-  println((new chisel3.stage.ChiselStage).emitVerilog(new exu_div_new_2bit_fullshortq()))
-}
-
-
 class exu_div_new_3bit_fullshortq extends Module with RequireAsyncReset with lib {
   val io = IO(new Bundle{
     val scan_mode             = Input(Bool())
@@ -626,8 +583,215 @@ class exu_div_new_3bit_fullshortq extends Module with RequireAsyncReset with lib
     val data_out              = Output(UInt(32.W))
     val valid_out             = Output(UInt(1.W))
   })
-  io.data_out :=0.U
-  io.valid_out :=0.U
+
+ // val valid_ff_in          = WireInit(Bool(),init=false.B)
+  val valid_ff             = WireInit(Bool(),init=false.B)
+ // val finish_raw           = WireInit(Bool(),init=false.B)
+  //val finish               = WireInit(Bool(),init=false.B)
+  val finish_ff            = WireInit(Bool(),init=false.B)
+//  val running_state        = WireInit(Bool(),init=false.B)
+//  val misc_enable          = WireInit(Bool(),init=false.B)
+//  val control_in           = WireInit(0.U(3.W))
+  val control_ff           = WireInit(0.U(3.W))
+//   val dividend_sign_ff     = WireInit(Bool(),init=false.B)
+//    val divisor_sign_ff      = WireInit(Bool(),init=false.B)
+//    val count_enable         = WireInit(Bool(),init=false.B)
+//    val count_in             = WireInit(0.U(7.W))
+  val count_ff             = WireInit(0.U(7.W))
+  val smallnum             = WireInit(0.U(4.W))
+ //  val smallnum_case        = WireInit(Bool(),init=false.B)
+//  val a_enable             = WireInit(Bool(),init=false.B)
+//  val a_shift              = WireInit(Bool(),init=false.B)
+//  val b_enable             = WireInit(Bool(),init=false.B)
+//  val b_twos_comp          = WireInit(Bool(),init=false.B)
+//  val a_in                 = WireInit(0.U(33.W))
+  val a_ff                 = WireInit(0.U(33.W))
+  //  val b_in                 = WireInit(0.U(33.W))
+  val b_ff1                = WireInit(0.U(33.W))
+  val b_ff                 = WireInit(0.U(37.W))
+ //   val q_in                 = WireInit(0.U(32.W))
+  val q_ff                 = WireInit(0.U(32.W))
+ //  val r_in                 = WireInit(0.U(33.W))
+  val r_ff                 = WireInit(0.U(33.W))
+  //  val rq_enable            = WireInit(Bool(),init=false.B)
+ //  val r_sign_sel           = WireInit(Bool(),init=false.B)
+ //  val r_restore_sel        = WireInit(Bool(),init=false.B)
+   // val r_adder1_sel         = WireInit(Bool(),init=false.B)
+  //  val r_adder2_sel         = WireInit(Bool(),init=false.B)
+ //  val r_adder3_sel         = WireInit(Bool(),init=false.B)
+  //  val r_adder4_sel         = WireInit(Bool(),init=false.B)
+  //  val r_adder5_sel         = WireInit(Bool(),init=false.B)
+  // val r_adder6_sel         = WireInit(Bool(),init=false.B)
+ //  val r_adder7_sel         = WireInit(Bool(),init=false.B)
+//    val twos_comp_q_sel      = WireInit(Bool(),init=false.B)
+//    val twos_comp_b_sel      = WireInit(Bool(),init=false.B)
+  val quotient_raw         = WireInit(0.U(8.W))
+  val quotient_new         = WireInit(0.U(3.W))
+  val shortq_enable        = WireInit(Bool(),init=false.B)
+  val shortq_enable_ff     = WireInit(Bool(),init=false.B)
+ //   val by_zero_case         = WireInit(Bool(),init=false.B)
+  val by_zero_case_ff      = WireInit(Bool(),init=false.B)
+ //  val twos_comp_in         = WireInit(0.U(32.W))
+ //   val twos_comp_out        = WireInit(0.U(32.W))
+ //  val adder1_out            = WireInit(0.U(34.W))
+//   val adder2_out            = WireInit(0.U(35.W))
+ //   val adder3_out            = WireInit(0.U(36.W))
+//   val adder4_out            = WireInit(0.U(37.W))
+ //  val adder5_out            = WireInit(0.U(37.W))
+ //   val adder6_out            = WireInit(0.U(37.W))
+//    val adder7_out            = WireInit(0.U(37.W))
+  val ar_shifted           = WireInit(0.U(66.W))
+//  val shortq               = WireInit(0.U(6.W))
+ //  val shortq_shift         = WireInit(0.U(5.W))
+   val shortq_decode         = WireInit(0.U(5.W))
+  val shortq_shift_ff      = WireInit(0.U(5.W))
+//   val shortq_dividend      = WireInit(0.U(33.W))
+  val valid_ff_in = io.valid_in & !io.cancel
+  val control_in           = Cat((!io.valid_in & control_ff(2)) | (io.valid_in & io.signed_in  & io.dividend_in(31)), (!io.valid_in & control_ff(1)) | (io.valid_in & io.signed_in  &  io.divisor_in(31)), (!io.valid_in & control_ff(0)) | (io.valid_in & io.rem_in))
+  val dividend_sign_ff     = control_ff(2)
+  val divisor_sign_ff      = control_ff(1)
+  val rem_ff               = control_ff(0)
+  val by_zero_case         =  valid_ff & (b_ff(31,0) === 0.U)
+
+  val smallnum_case =  ((a_ff(31,4) === 0.U) & (b_ff(31,4) === 0.U) & !by_zero_case & !rem_ff & valid_ff & !io.cancel) |
+    ((a_ff(31,0) === 0.U) & !by_zero_case & !rem_ff & valid_ff & !io.cancel)
+  val running_state        = count_ff.orR() | shortq_enable_ff
+  val misc_enable          =  io.valid_in | valid_ff | io.cancel | running_state | finish_ff
+  val finish_raw           =  smallnum_case | by_zero_case | (count_ff === 33.U)
+  val finish               = finish_raw & !io.cancel
+  val count_enable         = (valid_ff | running_state) & !finish & !finish_ff & !io.cancel & !shortq_enable
+  val count_in             = Fill(7,count_enable) & (count_ff + Cat(0.U(5.W),3.U) + Cat(0.U(2.W),shortq_shift_ff))
+  val a_enable             =  io.valid_in | running_state
+  val a_shift              =  running_state & !shortq_enable_ff
+  ar_shifted               := Cat (Fill(33,dividend_sign_ff),a_ff) << shortq_shift_ff
+  val b_twos_comp          =  valid_ff & !(dividend_sign_ff ^ divisor_sign_ff)
+  val twos_comp_b_sel      =  valid_ff  & !(dividend_sign_ff ^ divisor_sign_ff)
+  val twos_comp_q_sel      = !valid_ff & !rem_ff &  (dividend_sign_ff ^ divisor_sign_ff) & !by_zero_case_ff
+  val b_enable             =  io.valid_in | b_twos_comp
+  val rq_enable            =  io.valid_in | valid_ff | running_state
+  val r_sign_sel           =  valid_ff & dividend_sign_ff & !by_zero_case
+  val r_restore_sel        =  running_state & (quotient_new === 0.U) & !shortq_enable_ff
+  val r_adder1_sel         =  running_state & (quotient_new === 1.U) & !shortq_enable_ff
+  val r_adder2_sel         =  running_state & (quotient_new === 2.U) & !shortq_enable_ff
+  val r_adder3_sel         =  running_state & (quotient_new === 3.U) & !shortq_enable_ff
+  val r_adder4_sel         =  running_state & (quotient_new === 4.U) & !shortq_enable_ff
+  val r_adder5_sel         =  running_state & (quotient_new === 5.U) & !shortq_enable_ff
+  val r_adder6_sel         =  running_state & (quotient_new === 6.U) & !shortq_enable_ff
+  val r_adder7_sel         =  running_state & (quotient_new === 6.U) & !shortq_enable_ff
+  val adder1_out = Cat(r_ff(30,0),a_ff(32,30)) + b_ff(33,0)
+  val adder2_out = Cat(r_ff(31,0),a_ff(32,30)) + Cat(b_ff(33,0),0.U)
+  val adder3_out = Cat(r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U) + b_ff(35,0)
+  val adder4_out = Cat(r_ff(32),r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U(2.W))
+  val adder5_out = Cat(r_ff(32),r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U(2.W)) + b_ff
+  val adder6_out = Cat(r_ff(32),r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U(2.W)) + Cat(b_ff(35,0),0.U)
+  val adder7_out = Cat(r_ff(32),r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U(2.W)) + Cat(b_ff(35,0),0.U) + b_ff
+  quotient_raw := Cat((!adder7_out(36) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder7_out === 0.U)),
+                     (!adder6_out(36) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder6_out === 0.U)),
+                     (!adder5_out(36) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder5_out === 0.U)),
+                     (!adder4_out(36) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder4_out === 0.U)),
+                     (!adder3_out(35) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder3_out === 0.U)),
+                     (!adder2_out(34) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder2_out === 0.U)),
+                     (!adder1_out(33) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder1_out === 0.U)), 0.U)
+    quotient_new := Cat ((quotient_raw(7) |  quotient_raw(6) | quotient_raw(5) |  quotient_raw(4)),
+                        (quotient_raw(7) |  quotient_raw(6) |(!quotient_raw(4) & quotient_raw(3)) |(!quotient_raw(3) & quotient_raw(2))),
+                        (quotient_raw(7) |  quotient_raw(6) & quotient_raw(5) |(!quotient_raw(4) & quotient_raw(3)) |(!quotient_raw(2) & quotient_raw(1))))
+  val twos_comp_in = Mux1H(Seq (
+    twos_comp_q_sel                       -> q_ff,
+    twos_comp_b_sel                     -> b_ff(31,0)
+  ))
+  val twos_comp_out = rvtwoscomp(twos_comp_in)
+
+  val a_in = Mux1H(Seq (
+    (!a_shift & !shortq_enable_ff).asBool -> Cat(io.signed_in & io.dividend_in(31),io.dividend_in(31,0)),
+    a_shift                             -> Cat(a_ff(29,0),0.U(3.W)),
+    shortq_enable_ff                    -> ar_shifted(32,0)
+  ))
+  val b_in = Mux1H(Seq (
+    !b_twos_comp                          -> Cat(io.signed_in & io.divisor_in(31),io.divisor_in(31,0)),
+    b_twos_comp                          -> Cat(!divisor_sign_ff,twos_comp_out(31,0))
+  ))
+
+  val r_in = Mux1H (Seq(
+    r_sign_sel                            -> "h1ffffffff".U(33.W),
+    r_restore_sel                         -> Cat(r_ff(29,0),a_ff(32,30)),
+    r_adder1_sel                           -> adder1_out(32,0),
+    r_adder2_sel                           -> adder2_out(32,0),
+    r_adder3_sel                           -> adder3_out(32,0),
+    r_adder4_sel                           -> adder4_out(32,0),
+    r_adder5_sel                           -> adder5_out(32,0),
+    r_adder6_sel                           -> adder6_out(32,0),
+    r_adder7_sel                           -> adder7_out(32,0),
+    shortq_enable_ff                       -> ar_shifted(65,33),
+    by_zero_case                           -> Cat(0.U,a_ff(31,0))
+))
+  val q_in = Mux1H (Seq(
+   !valid_ff                              -> Cat(q_ff(28,0),quotient_new),
+    smallnum_case                         -> Cat(0.U(28.W),smallnum),
+    by_zero_case                          -> Fill(32,1.U)
+  ))
+  io.valid_out := finish_ff & !io.cancel
+  io.data_out := Mux1H(Seq(
+    (!rem_ff & !twos_comp_q_sel).asBool() -> q_ff,
+    rem_ff                              -> r_ff(31,0),
+    twos_comp_q_sel                     -> twos_comp_out
+  ))
+  def pat1(x : List[Int], y : List[Int]) = {
+    val pat_a = (0 until x.size).map(i=> if(x(i)>=0) a_ff(x(i)) else !a_ff(x(i).abs)).reduce(_&_)
+    val pat_b = (0 until y.size).map(i=> if(y(i)>=0) b_ff(y(i)) else !b_ff(y(i).abs)).reduce(_&_)
+    pat_a & pat_b
+  }
+  smallnum := Cat(
+    pat1(List(3),List(-3, -2, -1)),
+
+    pat1(List(3),List(-3, -2))& !b_ff(0) | pat1(List(2),List(-3, -2, -1)) | pat1(List(3, 2),List(-3, -2)),
+
+    pat1(List(2),List(-3, -2))& !b_ff(0) | pat1(List(1),List(-3, -2, -1))    | pat1(List(3),List(-3, -1))& !b_ff(0) |
+      pat1(List(3, -2),List(-3, -2, 1, 0)) | pat1(List(-3, 2, 1),List(-3, -2)) | pat1(List(3, 2),List(-3))& !b_ff(0)  |
+      pat1(List(3, 2),List(-3, 2, -1))     | pat1(List(3, 1),List(-3,-1))     | pat1(List(3, 2, 1),List(-3, 2)),
+
+    pat1(List(2, 1, 0),List(-3, -1))        | pat1(List(3, -2, 0),List(-3, 1, 0))    | pat1(List(2),List(-3, -1))& !b_ff(0)     |
+      pat1(List(1),List(-3, -2))& !b_ff(0)    | pat1(List(0),List(-3, -2, -1))         | pat1(List(-3, 2, -1),List(-3, -2, 1, 0)) |
+      pat1(List(-3, 2, 1),List(-3))& !b_ff(0) | pat1(List(3),List(-2, -1)) & !b_ff(0)  | pat1(List(3, -2),List(-3, 2, 1))         |
+      pat1(List(-3, 2, 1),List(-3, 2, -1))    | pat1(List(-3, 2, 0),List(-3, -1))      | pat1(List(3, -2, -1),List(-3, 2, 0))     |
+      pat1(List(-2, 1, 0),List(-3, -2))       | pat1(List(3, 2),List(-1)) & !b_ff(0)   | pat1(List(-3, 2, 1, 0),List(-3, 2))      |
+      pat1(List(3, 2),List(3, -2))            | pat1(List(3, 1),List(3,-2,-1))         | pat1(List(3, 0),List(-2, -1))            |
+      pat1(List(3, -1),List(-3, 2, 1, 0))     | pat1(List(3, 2, 1),List(3)) & !b_ff(0) | pat1(List(3, 2, 1),List(3, -1))          |
+      pat1(List(3, 2, 0),List(3, -1))         | pat1(List(3, -2, 1),List(-3, 1))       | pat1(List(3, 1, 0),List(-2))             |
+      pat1(List(3, 2, 1, 0),List(3))          |pat1(List(3, 1),List(-2)) & !b_ff(0))
+
+  val shortq_dividend = Cat(dividend_sign_ff,a_ff)
+  val a_enc = Module(new exu_div_cls)
+  a_enc.io.operand := shortq_dividend
+  val dw_a_enc1 = a_enc.io.cls
+ val b_enc = Module(new exu_div_cls)
+  b_enc.io.operand := b_ff(32,0)
+  val dw_b_enc1 = b_enc.io.cls
+  val dw_a_enc = Cat (0.U, dw_a_enc1)
+  val dw_b_enc = Cat (0.U, dw_b_enc1)
+  val dw_shortq_raw = Cat(0.U,dw_b_enc) - Cat(0.U,dw_a_enc) + 1.U(7.W)
+  val shortq = Mux(dw_shortq_raw(6).asBool(),0.U,dw_shortq_raw(5,0))
+  shortq_enable := valid_ff & !shortq(5) & !(shortq(4,2) ===  "b111".U) & !io.cancel
+  val list = Array(27,27,27,27,27,27,24,24,24,21,21,21,18,18,18,15,15,15,12,12,12,9,9,9,6,6,6,3,0,0,0,0)
+  shortq_decode := Mux1H((31 to 0 by -1).map(i=> (shortq === i.U) -> list(i).U))
+  val shortq_shift = Mux(!shortq_enable,0.U,shortq_decode)
+  b_ff := Cat(b_ff1(32),b_ff1(32),b_ff1(32),b_ff1(32),b_ff1)
+  valid_ff := rvdffe(valid_ff_in, misc_enable,clock,io.scan_mode)
+  control_ff   := rvdffe(control_in, misc_enable,clock,io.scan_mode)
+  by_zero_case_ff := rvdffe(by_zero_case,misc_enable,clock,io.scan_mode)
+  shortq_enable_ff := rvdffe(shortq_enable, misc_enable,clock,io.scan_mode)
+  shortq_shift_ff := Cat(rvdffe(shortq_shift, misc_enable,clock,io.scan_mode),0.U)
+  finish_ff := rvdffe(finish, misc_enable,clock,io.scan_mode)
+  count_ff := rvdffe(count_in, misc_enable,clock,io.scan_mode)
+
+  a_ff := rvdffe(a_in, a_enable,clock,io.scan_mode)
+  b_ff1 := rvdffe(b_in(32,0), b_enable,clock,io.scan_mode)
+  r_ff := rvdffe(r_in, rq_enable,clock,io.scan_mode)
+  q_ff := rvdffe(q_in, rq_enable,clock,io.scan_mode)
+
+}
+
+object div_main4 extends App {
+  println((new chisel3.stage.ChiselStage).emitVerilog(new exu_div_new_3bit_fullshortq()))
 }
 class exu_div_new_4bit_fullshortq extends Module with RequireAsyncReset with lib {
   val io = IO(new Bundle{
diff --git a/target/scala-2.12/classes/exu/div_main3$delayedInit$body.class b/target/scala-2.12/classes/exu/div_main3$delayedInit$body.class
deleted file mode 100644
index bba81eefa3f3767624c661a94ee09098e510a581..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 744
zcmZ`%U279T6g_wIWzsYsZEdX|ZPiuM7K}xGiU=we0-GwN?Q5Cc9qrW3OxVnp=3lA!
z0Y2!X;ExjTqyb65m$`G#-h1x3XXp2y?>_)M#(lzuyvW+IIzJf*r62jROvG5mU9GGi
zns{6S5jIDWNJKl$v{eJyejbi&Dk8g|>BuUhAC{0KG@0nc5k)q6FlitZeUn+45*oqm
zm=2*JhQnk`SZQqsXX0G66QSR=Ux#NhvYjf5D3#%%La5EQmQZCyQ=PALJTyvMpKJVo
zTkH{Xt?lC~YN%JRhz4P8c83?{LdHkDWeH1!{Lw-8kgy*7r-=2e;A$DmSmk1Ssz!vZ
zxs~Rf;}wff6;F6ZSZ>V~cbvHEPFx;0newHHC7~WDEf2CmDAPj`CX6fvhOIvqsdD)g
zT<lvBz3++PG;j2zJvH$gk&1z2yIEYNZ?ZI!`^u5j`|kI3b;9gj{noJe69ju~aGoCm
z&vAb9%|jDcP-bL<vnL#h<HF8oEPO@t6V^UViZ=Nyx=&t=ExuPT%Ww_roDpw!gQ*-v
zkE6%2vHJ@J`nj|Fh1tI0)<?#2xIH<kh<U=*%cdzIw@>sD?r=kajb$K*yPS9^z~@-w
OXX?4R<n$BnF^0e8Kce0M

diff --git a/target/scala-2.12/classes/exu/div_main3$.class b/target/scala-2.12/classes/exu/div_main4$.class
similarity index 73%
rename from target/scala-2.12/classes/exu/div_main3$.class
rename to target/scala-2.12/classes/exu/div_main4$.class
index ee70ad5f5458b1fdf95fdb0b7d573d0b345ca263..aa8f93cba1be0271af27d84a50b953f41f0ac992 100644
GIT binary patch
delta 176
zcmX>ocTjGEB%{ehsr8H|8&7evNSHG+C~Ii?q*j#b195yxW?6h*YI(fz<ku`pjK-7s
zSWOvCHoLIOFf*D=PUKJpa@slSn3$L)C$n?gfT%cL@yRjV9x&!!Zc7mJ2e&ndGUb7)
vk(}JaV-6BI%Hsl2Dmht&*8;+fW@46_yqnjDjaiC89jJzvuN)-N#<v>)A~Y*<

delta 176
zcmX>ocTjGEB%|>}sr8J;8&7evNSHA)C~Ii?q*j#b195yxW?6h*YI(fT<ku`pj7F3B
zSWOv?H@mRPFf$rYPUKJpa@slSn3$MSCbM(ffT%cL@yRjV9x&!!Zc7mJ2e&ndGUb7)
vk(}JaV-6BI%Hsl2Dmht&*8;+fW@1X6yqnjDjVYBu9jJzvuN)-N#<v>)+T$-Q

diff --git a/target/scala-2.12/classes/exu/div_main4$delayedInit$body.class b/target/scala-2.12/classes/exu/div_main4$delayedInit$body.class
new file mode 100644
index 0000000000000000000000000000000000000000..a4ea7abf6a58c4d991658c840d8b4ecca9df12e0
GIT binary patch
literal 744
zcmZ`%U279T6g_v7Y)qQwqphv+qpiA?v;||KK1Bo-3xT8xY5Q7ccgJ?>W;SeQOY^T(
z`~V;HQSe8JceVjZz?Zpm&)$3Pxo7A1pYJ~a?Bfw(U0$W_P+gu5h0^<8C?heEVOJ~T
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zn{zA8JI5=!&lFF1PFQZu6?d$-+g4m2cbW2497;m1r?fmwhrUdXgdZ`o)Qj2r6OkyJ
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zhrn~J-+Xh>zzvibS?BC2N8-4!^BD_Y(fEY54_VO$pRWCsYhsh{mFqIxLX$J%&F(Oj
zrRZ~XIM#Q6p+G-(cE2#&H{AQkSPu8IlU&Rbu3k4y3AsJfM|i*u1vZv}93FDwpa73!
Qm7l3&=aSV=*kTNS0j^P^Pyhe`

literal 0
HcmV?d00001

diff --git a/target/scala-2.12/classes/exu/div_main3.class b/target/scala-2.12/classes/exu/div_main4.class
similarity index 65%
rename from target/scala-2.12/classes/exu/div_main3.class
rename to target/scala-2.12/classes/exu/div_main4.class
index a0d90512fffda2c4da081117644aeda0ea3c4135..76f2f01d6c89b0b8223d4c041ca06b4e0698db48 100644
GIT binary patch
delta 61
zcmbQtHkoaLB%{ehsd^?E>4~%DK;-U91rrr^1|CKRc3*#&P#;$nMg{?&)QVF5l+3dD
O+{Da0lg%NF`xyb<Nf259

delta 61
zcmbQtHkoaLB%|>}sd}ausfn}YK;-U91!EO<1|CKRc3*#&P#;$nMg{?&)QVF5l+3dD
O+{Da0<IN$A`xycAju6!V

diff --git a/target/scala-2.12/classes/exu/exu_div_cls$$anon$7.class b/target/scala-2.12/classes/exu/exu_div_cls$$anon$7.class
index a373ea092b2d6bbcb3567179df2f1bafa264b4fa..41571e9fa7ca9d0faf25f770a71fd5c08db3ece4 100644
GIT binary patch
delta 40
vcmbQoJCApRJ1Y~j?qp9^YbIvB$!)A1e9SrwT+F%*ddzwZfy_FSW!Rbkw{Hjs

delta 40
vcmbQoJCApRJ1Y}Y=VVV-YbK_y$!)A1d`uk-Tuhw|dQ4pmflM8fW!Rbk+L{U}

diff --git a/target/scala-2.12/classes/exu/exu_div_cls.class b/target/scala-2.12/classes/exu/exu_div_cls.class
index e4b9c0f34831493748d40cf6914147237e62a69f..91373b2ff18b817f2ca510967e8f361ab0f30c1f 100644
GIT binary patch
delta 743
zcmaKo&1(};6vgkGH!+DwlTIm;ek7S>nvXWxe3*IGY!tDgL{On6T3v*iT4<V3ZRua2
zA}AE^!iAy>cLl3WAc9>gx-8m-3m1xlyNaNK8^wFm5HJfjbMD;tn=|LU$CGQ5Psemk
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z_YWdJ8DDiu^Jedy9N?C%54dkyQSR2esu%jVHBDylxc`nOv-qCH#%h2>p$s<VZt%P&
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Mft$kt{62i>FX#`&1poj5

delta 727
zcmaJ--%FEG7=F*Y&$h+b=0sv@Zu|DRA5yvRTja(nsOT4F5TR&MFzhqI`PmP}zn~_u
zrQ3TG1x0iziEW^ew}O{J65Rv^MRy5BU33w3-fao(qMP%)=Q+=L&hwn*;pf9EX$6f`
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M*xthj`qq2+4-&%71^@s6

diff --git a/target/scala-2.12/classes/exu/exu_div_existing_1bit_cheapshortq.class b/target/scala-2.12/classes/exu/exu_div_existing_1bit_cheapshortq.class
index 2d963f2be045085bb05e51086c5adad6278f46a1..f9f0c6cce3478bb1a3af5752581630ba9500bf98 100644
GIT binary patch
delta 33
pcmdn<hHcLqwhe`8T;_}njG2rKq8gr)FUATt_oZ#`OJiK;4*=1;3=04N

delta 33
pcmdn<hHcLqwhe`8T*izHjG2rKq8gr)FUATt_oZ#`OJiK;4*=0%3<m%J

diff --git a/target/scala-2.12/classes/exu/exu_div_new_1bit_fullshortq.class b/target/scala-2.12/classes/exu/exu_div_new_1bit_fullshortq.class
index bb04b8184c01e9d43f6c531e8c1543f42c0362c4..8a6f31306a2c87d56417c7905c996d7bcb41243b 100644
GIT binary patch
delta 34
qcmcb*p6%*-whfaqxh)tO7&93eL^V7$CpR_-H*d(?z9ExQRSy8u$_s@6

delta 34
qcmcb*p6%*-whfaqxlI@u7&93eL^V7$CpR_-H*d(?z9ExQRSy8uY72n?

diff --git a/target/scala-2.12/classes/exu/exu_div_new_2bit_fullshortq.class b/target/scala-2.12/classes/exu/exu_div_new_2bit_fullshortq.class
index 053dfebd5d6a7e47b1d6c33af06d6f9985cdc610..b289a3b6645ed0c1616d3605304157e5668a9734 100644
GIT binary patch
delta 5604
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sWXw8MI_9)08=I@j$G)s8#`RW}yB~WDhvfgD`CG9B!Mj_xqNDFW0nN8*=l}o!

delta 5627
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diff --git a/target/scala-2.12/classes/exu/exu_div_new_3bit_fullshortq$$anon$5.class b/target/scala-2.12/classes/exu/exu_div_new_3bit_fullshortq$$anon$5.class
index dca114826399ae539b731c643f8f5ecb3cd6dbca..8f45e24a352b4dd55bb6033d19f0d38eba0481fa 100644
GIT binary patch
delta 140
zcmZn^YZTk?g^kf+@&XRg$z1H}jE-QIJCNlBX0-rW&S2I-Aj<{J`UhmWf?3ua>Wpq+
zRt1pd4rJLddVu(wKXF(xYT7e!F*z_OGdVKYFgY=VGC4EkF}X0bGr2OXW^!XV&*aYV
PnaP7ujLCj-2-jKw%!MSV

delta 140
zcmZn^YZTk?g^e+L@&XRg$z1H}j5%PIJCKzNX0-rWd0^H-AS)lt`UhkcfLYcY>Wqb8
zRt1n%1Z3GT7K8YkKXF(xYGyHTF=aC-GvzSYFy%6YGUYMkG37I~GZiqbW-4Sj&s4<l
PnW>mjj45k!2-jKwhJ`2u

diff --git a/target/scala-2.12/classes/exu/exu_div_new_3bit_fullshortq.class b/target/scala-2.12/classes/exu/exu_div_new_3bit_fullshortq.class
index e810fbd8226f32e8832baac785cd662c68285503..8878e11596940e8b25e0e473b496d6fd509b8f60 100644
GIT binary patch
literal 118142
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zc?{os$Id{p4aKP_PD61ziZfB1h2m@!=b$(j#d#>sM{xm)3sGEz;$jq+ptuypWhgF3
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zW()5RTX;v;x*EkbD6U0u9g6Ew+<@Xn6gQ!`8O1FqZbh*j#ce2VM{x&=J5k();%*f8
zptu*seJJin@c@bkQS3mm69rzEweU)+h1WhUyjp4D^+gM>2wIP#cnrnkD4sy^B#Ng{
zJdNTR6wjh~4#o2*UO@38ikDEljN%m(ucCMj#p@{ELGcEPH&MKW;%yN4v2qY_R4za1
zD8He|@zZ_si(mM;7mkOqoWo~TIEO<$&f)VVoWtP|=kR3|&f!>$bNu)c$FCG|{IV0r
zPayHN9L6Pnij1F#7JdYa!`EIohhtRE@pE7DGehc=Kk%U%j)&;#BR(8IacIwnoumaj
G`~L@W(q=yZ

diff --git a/target/scala-2.12/classes/exu/exu_div_new_4bit_fullshortq$$anon$6.class b/target/scala-2.12/classes/exu/exu_div_new_4bit_fullshortq$$anon$6.class
index 5d88a092bb21b5d24deb7ee67d978082f3a450df..2def56f32f87860e12d31b6654984303490fa34d 100644
GIT binary patch
delta 150
zcmZn^YZTk?nT?5AZt?;S(aBuwYD~=XV5U2WsQ_lSfS8J4=0Ols3C#QlVk(1~)*L{l
z3Yb{|VyXg})=bQ5Ad$_VI4l^om}MEbnB^FhndKR5m=zd8nH3rGn3WjXnUxt<GpjJ1
TXI5qS%&f*J#w<HIgljDT*4iQ{

delta 150
zcmZn^YZTk?nT?65YVraO(aBuwYD`SkV5U2WSp#OafS9#l=0Om%4$S-qV%CG1)*L`)
z1DII>Vm1Pq)=W%IAd$_VI4l^om?{~#n5r0*nW`CVm}(e8nQ9sGnCckXnd%u<Gc_=r
TXKG~l%+$mv##A{ugljDTaAYY&

diff --git a/target/scala-2.12/classes/exu/exu_div_new_4bit_fullshortq.class b/target/scala-2.12/classes/exu/exu_div_new_4bit_fullshortq.class
index d1b4e18ec497ecdb9ea71da75a2574cd57544452..15f0a7b5b97a766442c09cd368118224a746abe9 100644
GIT binary patch
delta 4008
zcmYk<dr(wm9LDiwPf9l91=tm(MY4;st4y)jtXZRMX#yz%%2mKtK*3a41w{o!QCATX
zd<DTQF5XjaA_}24mQLx^BwEqUYi5(Tri+%^RC~_ZeIEbfv+w(T&;Aa|oH?RI5+zb=
znpa;-u!klnP}KR1Zm;tCPph>Ai)!8TedJ|7(dOePuIVOgEoKp<A2z^Z_R#cOkdd32
zoo=?6+Y|N6LzFPc8TyEuVNZL@$0X;ThsM*MXPYlq0pWA{YNbHom?pH6Q5d3TY9)iP
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zM?U(o>Cum`C_B#UTW8?<J7(a5QmiYm$z5=wujr1Q<vtP;7vWy5j!Tt!FK(-{>Ab0j
zi8|30KT7_1J-+18)v5%e{87GGZ$g5~TqQ`=iS9)8zLYB{H)BoJiz!JX<lsh(K~yBE
zH{)zSPf~twb;)`WFjHw|=8z{y?_>mNZmPHD7%J{1hbrIiFbZ3W>+*V0m!f>B{QW<W
zLsMO=>c5$DQ@B_3;w;&J7EVWy4)P@F@g~~w<O;Hryi1yGIF?NwAb(NmH5;?0&Bl>>
z@&f6Xh9I8YLiUgY($T&_t|w2C+6=T4$O5uU<&_M~8Zrk*a>yp~203yr+H|skyhuKo
zi8g_(BF~Wnv(Qc<H>hmO!mQFfbfIJ+`2qPCIp!@Kvy;u_O)_vk+6=OhyhIunpiNY{
zY5`_F&&@##(M=^w$xq0~ve8<}BC?zOn|v_`#}<(-<So)@SK4ShX5FE#$bW;EN&iK-
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zLw-ei=cAoQmXW7b{+5qfUt5MF#pE&a0clx|HkWK8?~tQbpv@$Akypup0<_6wt;!Px
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z8f~<jI#Isb^(-`rE2~|PaFZBQ0y@a=$e=X{iplfjh_wiok)M$P>kup=Pmx0$t{_@{
zZkoh#_lik)t;gwf@(B6F1_UW&D=C#Ch$Hur|B%x*qHQGal3`^^U@yb0chnWD!z8Tb
zIK74ZnH={vf^zaQ8L|n%I`Ug`bOnNy<T>)WN(A{T8!9pDu+7-ClP5`EfnXkaj2yHD
zK^l3O>{o>#nQS4o)d*tAy()XEF>B;jbPeR6<m4Iz+sNBwXe|OkUMFALhM<hRM4I10
zu$KHrrN?&6TC^Qq5Bco7SY1k<A^qP&kVAe<4z5FxMII#w)+3lrc94%ZC_!)oW^Gni
z<o~Z8jW|7n+(SMfr|v*oPyRu^z7s($d5fH|3&CdcCvxm=C9v(rtQXZ4dDh@PIK77K
zB~5z~6q0AjXZ9gjLY^iK?<2@2KO*(}5oD^Y+>coY9KfcHJVbgnAxI*dz|GCrpHA*3
z?~_wn(AJT^lapEz)Tlhsic!b6VY8CFMp_OcC?zkDFSH{lA-^V#hY%EyU$|)$!#kXT
zzli8io^}rPhc(ql^mZsOe-%fZFKUOA<tKv74@vV8*Q(vUIiyorS<<;qekK05bCUc@
eJgLj(Eg3X}C4Y@k3e+r=jG7L~(B9egz32asEu>8V

delta 4008
zcmYk<dr(wm9LDkGkdn=K0d~EGl3f&5nQ}2PYt$`CAw^g&0xsAJD3}VXpo@ZlfU5`z
zymHYjM7*XTh$!Txv2;qOCeey+UNf5zZMtZwO||Eo-RI#iKKs7k_w4VW%$Xw!-9@2$
zbCPFY!$dbtfS;)I9@kps`JW^iCW>n9^L^yy;iAQRxVWjEAsK>1fNtafLy()M-_n%K
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zCXDvMVsrS*F5VzFhigShgrBk#Jw%j5gt!=H8YTLhuoGsQ={nwInk=*1G~Kn*6R8#P
zkz;y)Z0!B<6=lb9ePa}^-w=fhx<@+$i`<Qm8zPQJ&vzXOj0ttER>vgDydP7eY&vf0
zQJhwE%pEI#yfwG5_i9zFzx+|YSXXSU%1k9l)QaPA>U}9!P;SPUs1vi|N6SIC$w!pO
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z4)QWNJPE;Eatql>4oF7(2DyPeOG+tdr;<5jhsx_Im^E-Aj%1LHWH&ix5!z(3p1eXn
znTj@+tRgRx1JlsXA~&jRNyDt}i_uLZbIA|LzsL!1;h2?dB5#v^OVFl}JISl0&r-B;
zDhrlk)=S(Rv<%&BvV{DEd@LQUkz7k2C;uj2%)qhb<RP+$^tUQ)gcY+ks4Mc{;5Bl@
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zb{*OX7qy~no%30!7uVN0AK`j2p%Ao_-;n`D2=d8G<mh4q+2m)W?|KBw$+P58yEBMT
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gD{*j##Y?hj220r*f2l~bOe)s2Nw(JZj_*DG2e*JG(EtDd