diff --git a/el2_ifu_mem_ctl.fir b/el2_ifu_mem_ctl.fir
index d4e0b16e..b929e226 100644
--- a/el2_ifu_mem_ctl.fir
+++ b/el2_ifu_mem_ctl.fir
@@ -13538,90 +13538,84 @@ circuit el2_ifu_mem_ctl :
     node _T_10421 = and(_T_10420, io.ic_debug_way) @[el2_ifu_mem_ctl.scala 829:90]
     ic_debug_tag_wr_en <= _T_10421 @[el2_ifu_mem_ctl.scala 829:22]
     node ic_debug_ict_array_sel_in = and(io.ic_debug_rd_en, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 830:53]
-    node _T_10422 = or(io.ic_debug_rd_en, io.ic_debug_wr_en) @[el2_ifu_mem_ctl.scala 831:72]
-    reg _T_10423 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_10422 : @[Reg.scala 28:19]
-      _T_10423 <= io.ic_debug_way @[Reg.scala 28:23]
+    reg _T_10422 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 831:53]
+    _T_10422 <= io.ic_debug_way @[el2_ifu_mem_ctl.scala 831:53]
+    ic_debug_way_ff <= _T_10422 @[el2_ifu_mem_ctl.scala 831:19]
+    reg _T_10423 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 832:63]
+    _T_10423 <= ic_debug_ict_array_sel_in @[el2_ifu_mem_ctl.scala 832:63]
+    ic_debug_ict_array_sel_ff <= _T_10423 @[el2_ifu_mem_ctl.scala 832:29]
+    reg _T_10424 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 833:54]
+    _T_10424 <= io.ic_debug_rd_en @[el2_ifu_mem_ctl.scala 833:54]
+    ic_debug_rd_en_ff <= _T_10424 @[el2_ifu_mem_ctl.scala 833:21]
+    node _T_10425 = bits(ic_debug_rd_en_ff, 0, 0) @[el2_ifu_mem_ctl.scala 834:111]
+    reg _T_10426 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_10425 : @[Reg.scala 28:19]
+      _T_10426 <= ic_debug_rd_en_ff @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    ic_debug_way_ff <= _T_10423 @[el2_ifu_mem_ctl.scala 831:19]
-    node _T_10424 = or(io.ic_debug_rd_en, io.ic_debug_wr_en) @[el2_ifu_mem_ctl.scala 832:92]
-    reg _T_10425 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_10424 : @[Reg.scala 28:19]
-      _T_10425 <= ic_debug_ict_array_sel_in @[Reg.scala 28:23]
-      skip @[Reg.scala 28:19]
-    ic_debug_ict_array_sel_ff <= _T_10425 @[el2_ifu_mem_ctl.scala 832:29]
-    reg _T_10426 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 833:54]
-    _T_10426 <= io.ic_debug_rd_en @[el2_ifu_mem_ctl.scala 833:54]
-    ic_debug_rd_en_ff <= _T_10426 @[el2_ifu_mem_ctl.scala 833:21]
-    node _T_10427 = bits(ic_debug_rd_en_ff, 0, 0) @[el2_ifu_mem_ctl.scala 834:111]
-    reg _T_10428 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_10427 : @[Reg.scala 28:19]
-      _T_10428 <= ic_debug_rd_en_ff @[Reg.scala 28:23]
-      skip @[Reg.scala 28:19]
-    io.ifu_ic_debug_rd_data_valid <= _T_10428 @[el2_ifu_mem_ctl.scala 834:33]
-    node _T_10429 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
-    node _T_10430 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
-    node _T_10431 = cat(_T_10430, _T_10429) @[Cat.scala 29:58]
-    node _T_10432 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
-    node _T_10433 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
-    node _T_10434 = cat(_T_10433, _T_10432) @[Cat.scala 29:58]
-    node _T_10435 = cat(_T_10434, _T_10431) @[Cat.scala 29:58]
-    node _T_10436 = orr(_T_10435) @[el2_ifu_mem_ctl.scala 835:213]
-    node _T_10437 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
-    node _T_10438 = or(_T_10437, UInt<31>("h07fffffff")) @[el2_ifu_mem_ctl.scala 836:62]
-    node _T_10439 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[el2_ifu_mem_ctl.scala 836:110]
-    node _T_10440 = eq(_T_10438, _T_10439) @[el2_ifu_mem_ctl.scala 836:85]
-    node _T_10441 = and(UInt<1>("h01"), _T_10440) @[el2_ifu_mem_ctl.scala 836:27]
-    node _T_10442 = or(_T_10436, _T_10441) @[el2_ifu_mem_ctl.scala 835:216]
-    node _T_10443 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
-    node _T_10444 = or(_T_10443, UInt<30>("h03fffffff")) @[el2_ifu_mem_ctl.scala 837:62]
-    node _T_10445 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[el2_ifu_mem_ctl.scala 837:110]
-    node _T_10446 = eq(_T_10444, _T_10445) @[el2_ifu_mem_ctl.scala 837:85]
-    node _T_10447 = and(UInt<1>("h01"), _T_10446) @[el2_ifu_mem_ctl.scala 837:27]
-    node _T_10448 = or(_T_10442, _T_10447) @[el2_ifu_mem_ctl.scala 836:134]
-    node _T_10449 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
-    node _T_10450 = or(_T_10449, UInt<29>("h01fffffff")) @[el2_ifu_mem_ctl.scala 838:62]
-    node _T_10451 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[el2_ifu_mem_ctl.scala 838:110]
-    node _T_10452 = eq(_T_10450, _T_10451) @[el2_ifu_mem_ctl.scala 838:85]
-    node _T_10453 = and(UInt<1>("h01"), _T_10452) @[el2_ifu_mem_ctl.scala 838:27]
-    node _T_10454 = or(_T_10448, _T_10453) @[el2_ifu_mem_ctl.scala 837:134]
-    node _T_10455 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
-    node _T_10456 = or(_T_10455, UInt<28>("h0fffffff")) @[el2_ifu_mem_ctl.scala 839:62]
-    node _T_10457 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[el2_ifu_mem_ctl.scala 839:110]
-    node _T_10458 = eq(_T_10456, _T_10457) @[el2_ifu_mem_ctl.scala 839:85]
-    node _T_10459 = and(UInt<1>("h01"), _T_10458) @[el2_ifu_mem_ctl.scala 839:27]
-    node _T_10460 = or(_T_10454, _T_10459) @[el2_ifu_mem_ctl.scala 838:134]
-    node _T_10461 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
-    node _T_10462 = or(_T_10461, UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 840:62]
-    node _T_10463 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 840:110]
-    node _T_10464 = eq(_T_10462, _T_10463) @[el2_ifu_mem_ctl.scala 840:85]
-    node _T_10465 = and(UInt<1>("h00"), _T_10464) @[el2_ifu_mem_ctl.scala 840:27]
-    node _T_10466 = or(_T_10460, _T_10465) @[el2_ifu_mem_ctl.scala 839:134]
-    node _T_10467 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
-    node _T_10468 = or(_T_10467, UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 841:62]
-    node _T_10469 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 841:110]
-    node _T_10470 = eq(_T_10468, _T_10469) @[el2_ifu_mem_ctl.scala 841:85]
-    node _T_10471 = and(UInt<1>("h00"), _T_10470) @[el2_ifu_mem_ctl.scala 841:27]
-    node _T_10472 = or(_T_10466, _T_10471) @[el2_ifu_mem_ctl.scala 840:134]
-    node _T_10473 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
-    node _T_10474 = or(_T_10473, UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 842:62]
-    node _T_10475 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 842:110]
-    node _T_10476 = eq(_T_10474, _T_10475) @[el2_ifu_mem_ctl.scala 842:85]
-    node _T_10477 = and(UInt<1>("h00"), _T_10476) @[el2_ifu_mem_ctl.scala 842:27]
-    node _T_10478 = or(_T_10472, _T_10477) @[el2_ifu_mem_ctl.scala 841:134]
-    node _T_10479 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
-    node _T_10480 = or(_T_10479, UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 843:62]
-    node _T_10481 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 843:110]
-    node _T_10482 = eq(_T_10480, _T_10481) @[el2_ifu_mem_ctl.scala 843:85]
-    node _T_10483 = and(UInt<1>("h00"), _T_10482) @[el2_ifu_mem_ctl.scala 843:27]
-    node ifc_region_acc_okay = or(_T_10478, _T_10483) @[el2_ifu_mem_ctl.scala 842:134]
-    node _T_10484 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 844:40]
-    node _T_10485 = eq(ifc_region_acc_okay, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 844:65]
-    node _T_10486 = and(_T_10484, _T_10485) @[el2_ifu_mem_ctl.scala 844:63]
-    node ifc_region_acc_fault_memory_bf = and(_T_10486, io.ifc_fetch_req_bf) @[el2_ifu_mem_ctl.scala 844:86]
-    node _T_10487 = or(io.ifc_region_acc_fault_bf, ifc_region_acc_fault_memory_bf) @[el2_ifu_mem_ctl.scala 845:63]
-    ifc_region_acc_fault_final_bf <= _T_10487 @[el2_ifu_mem_ctl.scala 845:33]
-    reg _T_10488 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 846:66]
-    _T_10488 <= ifc_region_acc_fault_memory_bf @[el2_ifu_mem_ctl.scala 846:66]
-    ifc_region_acc_fault_memory_f <= _T_10488 @[el2_ifu_mem_ctl.scala 846:33]
+    io.ifu_ic_debug_rd_data_valid <= _T_10426 @[el2_ifu_mem_ctl.scala 834:33]
+    node _T_10427 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_10428 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_10429 = cat(_T_10428, _T_10427) @[Cat.scala 29:58]
+    node _T_10430 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
+    node _T_10431 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
+    node _T_10432 = cat(_T_10431, _T_10430) @[Cat.scala 29:58]
+    node _T_10433 = cat(_T_10432, _T_10429) @[Cat.scala 29:58]
+    node _T_10434 = orr(_T_10433) @[el2_ifu_mem_ctl.scala 835:213]
+    node _T_10435 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_10436 = or(_T_10435, UInt<31>("h07fffffff")) @[el2_ifu_mem_ctl.scala 836:62]
+    node _T_10437 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[el2_ifu_mem_ctl.scala 836:110]
+    node _T_10438 = eq(_T_10436, _T_10437) @[el2_ifu_mem_ctl.scala 836:85]
+    node _T_10439 = and(UInt<1>("h01"), _T_10438) @[el2_ifu_mem_ctl.scala 836:27]
+    node _T_10440 = or(_T_10434, _T_10439) @[el2_ifu_mem_ctl.scala 835:216]
+    node _T_10441 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_10442 = or(_T_10441, UInt<30>("h03fffffff")) @[el2_ifu_mem_ctl.scala 837:62]
+    node _T_10443 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[el2_ifu_mem_ctl.scala 837:110]
+    node _T_10444 = eq(_T_10442, _T_10443) @[el2_ifu_mem_ctl.scala 837:85]
+    node _T_10445 = and(UInt<1>("h01"), _T_10444) @[el2_ifu_mem_ctl.scala 837:27]
+    node _T_10446 = or(_T_10440, _T_10445) @[el2_ifu_mem_ctl.scala 836:134]
+    node _T_10447 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_10448 = or(_T_10447, UInt<29>("h01fffffff")) @[el2_ifu_mem_ctl.scala 838:62]
+    node _T_10449 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[el2_ifu_mem_ctl.scala 838:110]
+    node _T_10450 = eq(_T_10448, _T_10449) @[el2_ifu_mem_ctl.scala 838:85]
+    node _T_10451 = and(UInt<1>("h01"), _T_10450) @[el2_ifu_mem_ctl.scala 838:27]
+    node _T_10452 = or(_T_10446, _T_10451) @[el2_ifu_mem_ctl.scala 837:134]
+    node _T_10453 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_10454 = or(_T_10453, UInt<28>("h0fffffff")) @[el2_ifu_mem_ctl.scala 839:62]
+    node _T_10455 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[el2_ifu_mem_ctl.scala 839:110]
+    node _T_10456 = eq(_T_10454, _T_10455) @[el2_ifu_mem_ctl.scala 839:85]
+    node _T_10457 = and(UInt<1>("h01"), _T_10456) @[el2_ifu_mem_ctl.scala 839:27]
+    node _T_10458 = or(_T_10452, _T_10457) @[el2_ifu_mem_ctl.scala 838:134]
+    node _T_10459 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_10460 = or(_T_10459, UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 840:62]
+    node _T_10461 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 840:110]
+    node _T_10462 = eq(_T_10460, _T_10461) @[el2_ifu_mem_ctl.scala 840:85]
+    node _T_10463 = and(UInt<1>("h00"), _T_10462) @[el2_ifu_mem_ctl.scala 840:27]
+    node _T_10464 = or(_T_10458, _T_10463) @[el2_ifu_mem_ctl.scala 839:134]
+    node _T_10465 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_10466 = or(_T_10465, UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 841:62]
+    node _T_10467 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 841:110]
+    node _T_10468 = eq(_T_10466, _T_10467) @[el2_ifu_mem_ctl.scala 841:85]
+    node _T_10469 = and(UInt<1>("h00"), _T_10468) @[el2_ifu_mem_ctl.scala 841:27]
+    node _T_10470 = or(_T_10464, _T_10469) @[el2_ifu_mem_ctl.scala 840:134]
+    node _T_10471 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_10472 = or(_T_10471, UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 842:62]
+    node _T_10473 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 842:110]
+    node _T_10474 = eq(_T_10472, _T_10473) @[el2_ifu_mem_ctl.scala 842:85]
+    node _T_10475 = and(UInt<1>("h00"), _T_10474) @[el2_ifu_mem_ctl.scala 842:27]
+    node _T_10476 = or(_T_10470, _T_10475) @[el2_ifu_mem_ctl.scala 841:134]
+    node _T_10477 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_10478 = or(_T_10477, UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 843:62]
+    node _T_10479 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 843:110]
+    node _T_10480 = eq(_T_10478, _T_10479) @[el2_ifu_mem_ctl.scala 843:85]
+    node _T_10481 = and(UInt<1>("h00"), _T_10480) @[el2_ifu_mem_ctl.scala 843:27]
+    node ifc_region_acc_okay = or(_T_10476, _T_10481) @[el2_ifu_mem_ctl.scala 842:134]
+    node _T_10482 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 844:40]
+    node _T_10483 = eq(ifc_region_acc_okay, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 844:65]
+    node _T_10484 = and(_T_10482, _T_10483) @[el2_ifu_mem_ctl.scala 844:63]
+    node ifc_region_acc_fault_memory_bf = and(_T_10484, io.ifc_fetch_req_bf) @[el2_ifu_mem_ctl.scala 844:86]
+    node _T_10485 = or(io.ifc_region_acc_fault_bf, ifc_region_acc_fault_memory_bf) @[el2_ifu_mem_ctl.scala 845:63]
+    ifc_region_acc_fault_final_bf <= _T_10485 @[el2_ifu_mem_ctl.scala 845:33]
+    reg _T_10486 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 846:66]
+    _T_10486 <= ifc_region_acc_fault_memory_bf @[el2_ifu_mem_ctl.scala 846:66]
+    ifc_region_acc_fault_memory_f <= _T_10486 @[el2_ifu_mem_ctl.scala 846:33]
     
diff --git a/el2_ifu_mem_ctl.v b/el2_ifu_mem_ctl.v
index 472921ca..62314e85 100644
--- a/el2_ifu_mem_ctl.v
+++ b/el2_ifu_mem_ctl.v
@@ -637,24 +637,24 @@ module el2_ifu_mem_ctl(
   wire  debug_c1_clken = io_ic_debug_rd_en | io_ic_debug_wr_en; // @[el2_ifu_mem_ctl.scala 187:42]
   wire [3:0] ic_fetch_val_int_f = {2'h0,io_ic_fetch_val_f}; // @[Cat.scala 29:58]
   reg [30:0] ifu_fetch_addr_int_f; // @[el2_ifu_mem_ctl.scala 308:63]
-  wire [4:0] _GEN_464 = {{1'd0}, ic_fetch_val_int_f}; // @[el2_ifu_mem_ctl.scala 665:53]
-  wire [4:0] ic_fetch_val_shift_right = _GEN_464 << ifu_fetch_addr_int_f[0]; // @[el2_ifu_mem_ctl.scala 665:53]
-  wire [1:0] _GEN_465 = {{1'd0}, _T_317}; // @[el2_ifu_mem_ctl.scala 668:91]
-  wire [1:0] _T_3098 = ic_fetch_val_shift_right[3:2] & _GEN_465; // @[el2_ifu_mem_ctl.scala 668:91]
+  wire [4:0] _GEN_462 = {{1'd0}, ic_fetch_val_int_f}; // @[el2_ifu_mem_ctl.scala 665:53]
+  wire [4:0] ic_fetch_val_shift_right = _GEN_462 << ifu_fetch_addr_int_f[0]; // @[el2_ifu_mem_ctl.scala 665:53]
+  wire [1:0] _GEN_463 = {{1'd0}, _T_317}; // @[el2_ifu_mem_ctl.scala 668:91]
+  wire [1:0] _T_3098 = ic_fetch_val_shift_right[3:2] & _GEN_463; // @[el2_ifu_mem_ctl.scala 668:91]
   reg  ifc_iccm_access_f; // @[el2_ifu_mem_ctl.scala 322:60]
   wire  fetch_req_iccm_f = ifc_fetch_req_f & ifc_iccm_access_f; // @[el2_ifu_mem_ctl.scala 275:46]
-  wire [1:0] _GEN_466 = {{1'd0}, fetch_req_iccm_f}; // @[el2_ifu_mem_ctl.scala 668:113]
-  wire [1:0] _T_3099 = _T_3098 & _GEN_466; // @[el2_ifu_mem_ctl.scala 668:113]
+  wire [1:0] _GEN_464 = {{1'd0}, fetch_req_iccm_f}; // @[el2_ifu_mem_ctl.scala 668:113]
+  wire [1:0] _T_3099 = _T_3098 & _GEN_464; // @[el2_ifu_mem_ctl.scala 668:113]
   reg  iccm_dma_rvalid_in; // @[el2_ifu_mem_ctl.scala 654:59]
-  wire [1:0] _GEN_467 = {{1'd0}, iccm_dma_rvalid_in}; // @[el2_ifu_mem_ctl.scala 668:130]
-  wire [1:0] _T_3100 = _T_3099 | _GEN_467; // @[el2_ifu_mem_ctl.scala 668:130]
+  wire [1:0] _GEN_465 = {{1'd0}, iccm_dma_rvalid_in}; // @[el2_ifu_mem_ctl.scala 668:130]
+  wire [1:0] _T_3100 = _T_3099 | _GEN_465; // @[el2_ifu_mem_ctl.scala 668:130]
   wire  _T_3101 = ~io_dec_tlu_core_ecc_disable; // @[el2_ifu_mem_ctl.scala 668:154]
-  wire [1:0] _GEN_468 = {{1'd0}, _T_3101}; // @[el2_ifu_mem_ctl.scala 668:152]
-  wire [1:0] _T_3102 = _T_3100 & _GEN_468; // @[el2_ifu_mem_ctl.scala 668:152]
-  wire [1:0] _T_3091 = ic_fetch_val_shift_right[1:0] & _GEN_465; // @[el2_ifu_mem_ctl.scala 668:91]
-  wire [1:0] _T_3092 = _T_3091 & _GEN_466; // @[el2_ifu_mem_ctl.scala 668:113]
-  wire [1:0] _T_3093 = _T_3092 | _GEN_467; // @[el2_ifu_mem_ctl.scala 668:130]
-  wire [1:0] _T_3095 = _T_3093 & _GEN_468; // @[el2_ifu_mem_ctl.scala 668:152]
+  wire [1:0] _GEN_466 = {{1'd0}, _T_3101}; // @[el2_ifu_mem_ctl.scala 668:152]
+  wire [1:0] _T_3102 = _T_3100 & _GEN_466; // @[el2_ifu_mem_ctl.scala 668:152]
+  wire [1:0] _T_3091 = ic_fetch_val_shift_right[1:0] & _GEN_463; // @[el2_ifu_mem_ctl.scala 668:91]
+  wire [1:0] _T_3092 = _T_3091 & _GEN_464; // @[el2_ifu_mem_ctl.scala 668:113]
+  wire [1:0] _T_3093 = _T_3092 | _GEN_465; // @[el2_ifu_mem_ctl.scala 668:130]
+  wire [1:0] _T_3095 = _T_3093 & _GEN_466; // @[el2_ifu_mem_ctl.scala 668:152]
   wire [3:0] iccm_ecc_word_enable = {_T_3102,_T_3095}; // @[Cat.scala 29:58]
   wire  _T_3202 = ^io_iccm_rd_data_ecc[31:0]; // @[el2_lib.scala 311:30]
   wire  _T_3203 = ^io_iccm_rd_data_ecc[38:32]; // @[el2_lib.scala 311:44]
@@ -1914,8 +1914,8 @@ module el2_ifu_mem_ctl(
   wire  _T_1503 = _T_1502 | _T_1496; // @[Mux.scala 27:72]
   wire  _T_1505 = _T_1472 & _T_1503; // @[el2_ifu_mem_ctl.scala 417:69]
   wire  _T_1506 = _T_1468 | _T_1505; // @[el2_ifu_mem_ctl.scala 416:94]
-  wire [4:0] _GEN_473 = {{2'd0}, bypass_index[4:2]}; // @[el2_ifu_mem_ctl.scala 418:95]
-  wire  _T_1509 = _GEN_473 == 5'h1f; // @[el2_ifu_mem_ctl.scala 418:95]
+  wire [4:0] _GEN_471 = {{2'd0}, bypass_index[4:2]}; // @[el2_ifu_mem_ctl.scala 418:95]
+  wire  _T_1509 = _GEN_471 == 5'h1f; // @[el2_ifu_mem_ctl.scala 418:95]
   wire  _T_1510 = bypass_valid_value_check & _T_1509; // @[el2_ifu_mem_ctl.scala 418:56]
   wire  bypass_data_ready_in = _T_1506 | _T_1510; // @[el2_ifu_mem_ctl.scala 417:181]
   wire  _T_1511 = bypass_data_ready_in & crit_wd_byp_ok_ff; // @[el2_ifu_mem_ctl.scala 422:53]
@@ -1977,7 +1977,7 @@ module el2_ifu_mem_ctl(
   wire  _T_2457 = ifc_region_acc_fault_final_f | ifc_bus_acc_fault_f; // @[el2_ifu_mem_ctl.scala 469:91]
   wire  _T_2458 = ~_T_2457; // @[el2_ifu_mem_ctl.scala 469:60]
   wire  ic_rd_parity_final_err = _T_2456 & _T_2458; // @[el2_ifu_mem_ctl.scala 469:58]
-  reg  ic_debug_ict_array_sel_ff; // @[Reg.scala 27:20]
+  reg  ic_debug_ict_array_sel_ff; // @[el2_ifu_mem_ctl.scala 832:63]
   reg  ic_tag_valid_out_1_0; // @[Reg.scala 27:20]
   wire  _T_9973 = _T_4766 & ic_tag_valid_out_1_0; // @[el2_ifu_mem_ctl.scala 759:10]
   reg  ic_tag_valid_out_1_1; // @[Reg.scala 27:20]
@@ -2745,7 +2745,7 @@ module el2_ifu_mem_ctl(
   wire  _T_9844 = _T_4893 & ic_tag_valid_out_0_127; // @[el2_ifu_mem_ctl.scala 759:10]
   wire  _T_9971 = _T_9970 | _T_9844; // @[el2_ifu_mem_ctl.scala 759:91]
   wire [1:0] ic_tag_valid_unq = {_T_10354,_T_9971}; // @[Cat.scala 29:58]
-  reg [1:0] ic_debug_way_ff; // @[Reg.scala 27:20]
+  reg [1:0] ic_debug_way_ff; // @[el2_ifu_mem_ctl.scala 831:53]
   reg  ic_debug_rd_en_ff; // @[el2_ifu_mem_ctl.scala 833:54]
   wire [1:0] _T_10394 = ic_debug_rd_en_ff ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
   wire [1:0] _T_10395 = ic_debug_way_ff & _T_10394; // @[el2_ifu_mem_ctl.scala 814:67]
@@ -2989,10 +2989,10 @@ module el2_ifu_mem_ctl(
   wire [79:0] ic_byp_data_only_pre_new = _T_1626 ? _T_1868 : _T_2110; // @[el2_ifu_mem_ctl.scala 440:37]
   wire [79:0] _T_2115 = {16'h0,ic_byp_data_only_pre_new[79:16]}; // @[Cat.scala 29:58]
   wire [79:0] ic_byp_data_only_new = _T_2113 ? ic_byp_data_only_pre_new : _T_2115; // @[el2_ifu_mem_ctl.scala 444:30]
-  wire [79:0] _GEN_474 = {{16'd0}, _T_1261}; // @[el2_ifu_mem_ctl.scala 376:114]
-  wire [79:0] _T_1262 = _GEN_474 & ic_byp_data_only_new; // @[el2_ifu_mem_ctl.scala 376:114]
-  wire [79:0] _GEN_475 = {{16'd0}, _T_1259}; // @[el2_ifu_mem_ctl.scala 376:88]
-  wire [79:0] ic_premux_data_temp = _GEN_475 | _T_1262; // @[el2_ifu_mem_ctl.scala 376:88]
+  wire [79:0] _GEN_472 = {{16'd0}, _T_1261}; // @[el2_ifu_mem_ctl.scala 376:114]
+  wire [79:0] _T_1262 = _GEN_472 & ic_byp_data_only_new; // @[el2_ifu_mem_ctl.scala 376:114]
+  wire [79:0] _GEN_473 = {{16'd0}, _T_1259}; // @[el2_ifu_mem_ctl.scala 376:88]
+  wire [79:0] ic_premux_data_temp = _GEN_473 | _T_1262; // @[el2_ifu_mem_ctl.scala 376:88]
   wire  fetch_req_f_qual = io_ic_hit_f & _T_317; // @[el2_ifu_mem_ctl.scala 383:38]
   wire [1:0] _T_1271 = ifc_region_acc_fault_f ? 2'h2 : 2'h0; // @[el2_ifu_mem_ctl.scala 387:8]
   wire  _T_1273 = fetch_req_f_qual & io_ifu_bp_inst_mask_f; // @[el2_ifu_mem_ctl.scala 389:45]
@@ -5144,7 +5144,7 @@ module el2_ifu_mem_ctl(
   wire  _T_10414 = io_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h0; // @[el2_ifu_mem_ctl.scala 828:103]
   wire [3:0] _T_10417 = {_T_10408,_T_10410,_T_10412,_T_10414}; // @[Cat.scala 29:58]
   wire  ic_debug_ict_array_sel_in = io_ic_debug_rd_en & io_ic_debug_tag_array; // @[el2_ifu_mem_ctl.scala 830:53]
-  reg  _T_10428; // @[Reg.scala 27:20]
+  reg  _T_10426; // @[Reg.scala 27:20]
   rvclkhdr rvclkhdr ( // @[el2_lib.scala 461:22]
     .io_l1clk(rvclkhdr_io_l1clk),
     .io_clk(rvclkhdr_io_clk),
@@ -5229,7 +5229,7 @@ module el2_ifu_mem_ctl(
   assign io_ic_data_f = io_ic_rd_data[31:0]; // @[el2_ifu_mem_ctl.scala 382:16]
   assign io_ic_premux_data = ic_premux_data_temp[63:0]; // @[el2_ifu_mem_ctl.scala 379:21]
   assign io_ic_sel_premux_data = fetch_req_iccm_f | sel_byp_data; // @[el2_ifu_mem_ctl.scala 380:25]
-  assign io_ifu_ic_debug_rd_data_valid = _T_10428; // @[el2_ifu_mem_ctl.scala 834:33]
+  assign io_ifu_ic_debug_rd_data_valid = _T_10426; // @[el2_ifu_mem_ctl.scala 834:33]
   assign io_iccm_buf_correct_ecc = iccm_correct_ecc & _T_2462; // @[el2_ifu_mem_ctl.scala 479:27]
   assign io_iccm_correction_state = _T_2490 ? 1'h0 : _GEN_60; // @[el2_ifu_mem_ctl.scala 514:28 el2_ifu_mem_ctl.scala 527:32 el2_ifu_mem_ctl.scala 534:32 el2_ifu_mem_ctl.scala 541:32]
   assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 462:17]
@@ -6212,7 +6212,7 @@ initial begin
   _RAND_468 = {1{`RANDOM}};
   _T_10405 = _RAND_468[0:0];
   _RAND_469 = {1{`RANDOM}};
-  _T_10428 = _RAND_469[0:0];
+  _T_10426 = _RAND_469[0:0];
 `endif // RANDOMIZE_REG_INIT
   `endif // RANDOMIZE
 end // initial
@@ -7074,11 +7074,6 @@ end // initial
     end else if (write_fill_data_7) begin
       ic_miss_buff_data_15 <= io_ifu_axi_rdata[63:32];
     end
-    if (reset) begin
-      ic_debug_ict_array_sel_ff <= 1'h0;
-    end else if (debug_c1_clken) begin
-      ic_debug_ict_array_sel_ff <= ic_debug_ict_array_sel_in;
-    end
     if (reset) begin
       ic_tag_valid_out_1_0 <= 1'h0;
     end else if (_T_5795) begin
@@ -8359,11 +8354,6 @@ end // initial
     end else if (_T_9042) begin
       ic_tag_valid_out_0_127 <= _T_5241;
     end
-    if (reset) begin
-      ic_debug_way_ff <= 2'h0;
-    end else if (debug_c1_clken) begin
-      ic_debug_way_ff <= io_ic_debug_way;
-    end
     if (reset) begin
       _T_1209 <= 71'h0;
     end else if (ic_debug_rd_en_ff) begin
@@ -8621,9 +8611,9 @@ end // initial
       ic_valid_ff <= ic_valid;
     end
     if (reset) begin
-      _T_10428 <= 1'h0;
+      _T_10426 <= 1'h0;
     end else if (ic_debug_rd_en_ff) begin
-      _T_10428 <= ic_debug_rd_en_ff;
+      _T_10426 <= ic_debug_rd_en_ff;
     end
   end
   always @(posedge rvclkhdr_1_io_l1clk) begin
@@ -8738,4 +8728,16 @@ end // initial
       _T_10405 <= bus_cmd_sent;
     end
   end
+  always @(posedge rvclkhdr_io_l1clk) begin
+    if (reset) begin
+      ic_debug_ict_array_sel_ff <= 1'h0;
+    end else begin
+      ic_debug_ict_array_sel_ff <= ic_debug_ict_array_sel_in;
+    end
+    if (reset) begin
+      ic_debug_way_ff <= 2'h0;
+    end else begin
+      ic_debug_way_ff <= io_ic_debug_way;
+    end
+  end
 endmodule
diff --git a/src/main/scala/ifu/el2_ifu_mem_ctl.scala b/src/main/scala/ifu/el2_ifu_mem_ctl.scala
index 4466b765..a9cebf63 100644
--- a/src/main/scala/ifu/el2_ifu_mem_ctl.scala
+++ b/src/main/scala/ifu/el2_ifu_mem_ctl.scala
@@ -828,8 +828,8 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
     io.dec_tlu_ic_diag_pkt.icache_dicawics(15,14)===1.U, io.dec_tlu_ic_diag_pkt.icache_dicawics(15,14)===0.U)
   ic_debug_tag_wr_en := Fill(ICACHE_NUM_WAYS, io.ic_debug_wr_en & io.ic_debug_tag_array) & io.ic_debug_way
   val ic_debug_ict_array_sel_in = io.ic_debug_rd_en & io.ic_debug_tag_array
-  ic_debug_way_ff := RegEnable(io.ic_debug_way, 0.U, io.ic_debug_rd_en | io.ic_debug_wr_en)
-  ic_debug_ict_array_sel_ff := RegEnable(ic_debug_ict_array_sel_in, 0.U, io.ic_debug_rd_en | io.ic_debug_wr_en)
+  ic_debug_way_ff := withClock(debug_c1_clk){RegNext(io.ic_debug_way, 0.U)}
+  ic_debug_ict_array_sel_ff := withClock(debug_c1_clk){RegNext(ic_debug_ict_array_sel_in, 0.U)}
   ic_debug_rd_en_ff := withClock(io.free_clk){RegNext(io.ic_debug_rd_en, false.B)}
   io.ifu_ic_debug_rd_data_valid := withClock(io.free_clk){RegEnable(ic_debug_rd_en_ff, 0.U, ic_debug_rd_en_ff.asBool)}
   val ifc_region_acc_okay = Cat(INST_ACCESS_ENABLE0.U,INST_ACCESS_ENABLE1.U,INST_ACCESS_ENABLE2.U,INST_ACCESS_ENABLE3.U,INST_ACCESS_ENABLE4.U,INST_ACCESS_ENABLE5.U,INST_ACCESS_ENABLE6.U,INST_ACCESS_ENABLE7.U).orR() |
diff --git a/target/scala-2.12/classes/ifu/el2_ifu_mem_ctl.class b/target/scala-2.12/classes/ifu/el2_ifu_mem_ctl.class
index d2c2b3cf..ca0e3250 100644
Binary files a/target/scala-2.12/classes/ifu/el2_ifu_mem_ctl.class and b/target/scala-2.12/classes/ifu/el2_ifu_mem_ctl.class differ
diff --git a/target/scala-2.12/classes/ifu/ifu_mem$.class b/target/scala-2.12/classes/ifu/ifu_mem$.class
index 23bd32b4..d134d711 100644
Binary files a/target/scala-2.12/classes/ifu/ifu_mem$.class and b/target/scala-2.12/classes/ifu/ifu_mem$.class differ