colin
/
quasar
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

BP output intialized

This commit is contained in:
waleed-lm 2020-10-08 09:45:45 +05:00
parent 8be2028806
commit 93a6914abe
10 changed files with 35 additions and 1242 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
el2_ifu_bp_ctl.anno.json
View File

@ -134,11 +134,6 @@
"class":"firrtl.EmitCircuitAnnotation", "class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter" "emitter":"firrtl.VerilogEmitter"
}, },
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_ifu_bp_ctl.TEC_RV_ICG",
"resourceId":"/vsrc/TEC_RV_ICG.v"
},
{ {
"class":"firrtl.options.TargetDirAnnotation", "class":"firrtl.options.TargetDirAnnotation",
"directory":"." "directory":"."

960
el2_ifu_bp_ctl.fir
View File

@ -1,773 +1,5 @@
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 ;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit el2_ifu_bp_ctl : circuit el2_ifu_bp_ctl :
extmodule TEC_RV_ICG :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG @[el2_lib.scala 398:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 399:14]
clkhdr.CK <= io.clk @[el2_lib.scala 400:18]
clkhdr.EN <= io.en @[el2_lib.scala 401:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 402:18]
extmodule TEC_RV_ICG_1 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_1 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_1 @[el2_lib.scala 398:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 399:14]
clkhdr.CK <= io.clk @[el2_lib.scala 400:18]
clkhdr.EN <= io.en @[el2_lib.scala 401:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 402:18]
extmodule TEC_RV_ICG_2 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_2 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_2 @[el2_lib.scala 398:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 399:14]
clkhdr.CK <= io.clk @[el2_lib.scala 400:18]
clkhdr.EN <= io.en @[el2_lib.scala 401:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 402:18]
extmodule TEC_RV_ICG_3 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_3 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_3 @[el2_lib.scala 398:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 399:14]
clkhdr.CK <= io.clk @[el2_lib.scala 400:18]
clkhdr.EN <= io.en @[el2_lib.scala 401:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 402:18]
extmodule TEC_RV_ICG_4 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_4 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_4 @[el2_lib.scala 398:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 399:14]
clkhdr.CK <= io.clk @[el2_lib.scala 400:18]
clkhdr.EN <= io.en @[el2_lib.scala 401:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 402:18]
extmodule TEC_RV_ICG_5 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_5 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_5 @[el2_lib.scala 398:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 399:14]
clkhdr.CK <= io.clk @[el2_lib.scala 400:18]
clkhdr.EN <= io.en @[el2_lib.scala 401:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 402:18]
extmodule TEC_RV_ICG_6 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_6 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_6 @[el2_lib.scala 398:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 399:14]
clkhdr.CK <= io.clk @[el2_lib.scala 400:18]
clkhdr.EN <= io.en @[el2_lib.scala 401:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 402:18]
extmodule TEC_RV_ICG_7 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_7 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_7 @[el2_lib.scala 398:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 399:14]
clkhdr.CK <= io.clk @[el2_lib.scala 400:18]
clkhdr.EN <= io.en @[el2_lib.scala 401:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 402:18]
extmodule TEC_RV_ICG_8 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_8 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_8 @[el2_lib.scala 398:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 399:14]
clkhdr.CK <= io.clk @[el2_lib.scala 400:18]
clkhdr.EN <= io.en @[el2_lib.scala 401:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 402:18]
extmodule TEC_RV_ICG_9 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_9 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_9 @[el2_lib.scala 398:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 399:14]
clkhdr.CK <= io.clk @[el2_lib.scala 400:18]
clkhdr.EN <= io.en @[el2_lib.scala 401:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 402:18]
extmodule TEC_RV_ICG_10 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_10 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_10 @[el2_lib.scala 398:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 399:14]
clkhdr.CK <= io.clk @[el2_lib.scala 400:18]
clkhdr.EN <= io.en @[el2_lib.scala 401:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 402:18]
extmodule TEC_RV_ICG_11 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_11 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_11 @[el2_lib.scala 398:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 399:14]
clkhdr.CK <= io.clk @[el2_lib.scala 400:18]
clkhdr.EN <= io.en @[el2_lib.scala 401:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 402:18]
extmodule TEC_RV_ICG_12 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_12 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_12 @[el2_lib.scala 398:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 399:14]
clkhdr.CK <= io.clk @[el2_lib.scala 400:18]
clkhdr.EN <= io.en @[el2_lib.scala 401:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 402:18]
extmodule TEC_RV_ICG_13 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_13 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_13 @[el2_lib.scala 398:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 399:14]
clkhdr.CK <= io.clk @[el2_lib.scala 400:18]
clkhdr.EN <= io.en @[el2_lib.scala 401:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 402:18]
extmodule TEC_RV_ICG_14 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_14 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_14 @[el2_lib.scala 398:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 399:14]
clkhdr.CK <= io.clk @[el2_lib.scala 400:18]
clkhdr.EN <= io.en @[el2_lib.scala 401:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 402:18]
extmodule TEC_RV_ICG_15 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_15 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_15 @[el2_lib.scala 398:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 399:14]
clkhdr.CK <= io.clk @[el2_lib.scala 400:18]
clkhdr.EN <= io.en @[el2_lib.scala 401:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 402:18]
extmodule TEC_RV_ICG_16 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_16 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_16 @[el2_lib.scala 398:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 399:14]
clkhdr.CK <= io.clk @[el2_lib.scala 400:18]
clkhdr.EN <= io.en @[el2_lib.scala 401:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 402:18]
extmodule TEC_RV_ICG_17 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_17 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_17 @[el2_lib.scala 398:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 399:14]
clkhdr.CK <= io.clk @[el2_lib.scala 400:18]
clkhdr.EN <= io.en @[el2_lib.scala 401:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 402:18]
extmodule TEC_RV_ICG_18 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_18 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_18 @[el2_lib.scala 398:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 399:14]
clkhdr.CK <= io.clk @[el2_lib.scala 400:18]
clkhdr.EN <= io.en @[el2_lib.scala 401:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 402:18]
extmodule TEC_RV_ICG_19 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_19 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_19 @[el2_lib.scala 398:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 399:14]
clkhdr.CK <= io.clk @[el2_lib.scala 400:18]
clkhdr.EN <= io.en @[el2_lib.scala 401:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 402:18]
extmodule TEC_RV_ICG_20 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_20 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_20 @[el2_lib.scala 398:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 399:14]
clkhdr.CK <= io.clk @[el2_lib.scala 400:18]
clkhdr.EN <= io.en @[el2_lib.scala 401:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 402:18]
extmodule TEC_RV_ICG_21 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_21 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_21 @[el2_lib.scala 398:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 399:14]
clkhdr.CK <= io.clk @[el2_lib.scala 400:18]
clkhdr.EN <= io.en @[el2_lib.scala 401:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 402:18]
extmodule TEC_RV_ICG_22 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_22 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_22 @[el2_lib.scala 398:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 399:14]
clkhdr.CK <= io.clk @[el2_lib.scala 400:18]
clkhdr.EN <= io.en @[el2_lib.scala 401:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 402:18]
extmodule TEC_RV_ICG_23 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_23 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_23 @[el2_lib.scala 398:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 399:14]
clkhdr.CK <= io.clk @[el2_lib.scala 400:18]
clkhdr.EN <= io.en @[el2_lib.scala 401:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 402:18]
extmodule TEC_RV_ICG_24 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_24 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_24 @[el2_lib.scala 398:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 399:14]
clkhdr.CK <= io.clk @[el2_lib.scala 400:18]
clkhdr.EN <= io.en @[el2_lib.scala 401:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 402:18]
extmodule TEC_RV_ICG_25 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_25 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_25 @[el2_lib.scala 398:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 399:14]
clkhdr.CK <= io.clk @[el2_lib.scala 400:18]
clkhdr.EN <= io.en @[el2_lib.scala 401:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 402:18]
extmodule TEC_RV_ICG_26 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_26 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_26 @[el2_lib.scala 398:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 399:14]
clkhdr.CK <= io.clk @[el2_lib.scala 400:18]
clkhdr.EN <= io.en @[el2_lib.scala 401:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 402:18]
extmodule TEC_RV_ICG_27 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_27 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_27 @[el2_lib.scala 398:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 399:14]
clkhdr.CK <= io.clk @[el2_lib.scala 400:18]
clkhdr.EN <= io.en @[el2_lib.scala 401:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 402:18]
extmodule TEC_RV_ICG_28 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_28 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_28 @[el2_lib.scala 398:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 399:14]
clkhdr.CK <= io.clk @[el2_lib.scala 400:18]
clkhdr.EN <= io.en @[el2_lib.scala 401:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 402:18]
extmodule TEC_RV_ICG_29 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_29 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_29 @[el2_lib.scala 398:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 399:14]
clkhdr.CK <= io.clk @[el2_lib.scala 400:18]
clkhdr.EN <= io.en @[el2_lib.scala 401:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 402:18]
extmodule TEC_RV_ICG_30 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_30 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_30 @[el2_lib.scala 398:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 399:14]
clkhdr.CK <= io.clk @[el2_lib.scala 400:18]
clkhdr.EN <= io.en @[el2_lib.scala 401:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 402:18]
extmodule TEC_RV_ICG_31 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_31 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_31 @[el2_lib.scala 398:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 399:14]
clkhdr.CK <= io.clk @[el2_lib.scala 400:18]
clkhdr.EN <= io.en @[el2_lib.scala 401:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 402:18]
module el2_ifu_bp_ctl : module el2_ifu_bp_ctl :
input clock : Clock input clock : Clock
input reset : AsyncReset input reset : AsyncReset
@ -9667,198 +8899,6 @@ circuit el2_ifu_bp_ctl :
node _T_6554 = and(_T_6550, _T_6553) @[el2_ifu_bp_ctl.scala 387:44] node _T_6554 = and(_T_6550, _T_6553) @[el2_ifu_bp_ctl.scala 387:44]
node _T_6555 = or(_T_6549, _T_6554) @[el2_ifu_bp_ctl.scala 386:142] node _T_6555 = or(_T_6549, _T_6554) @[el2_ifu_bp_ctl.scala 386:142]
bht_bank_clken[1][15] <= _T_6555 @[el2_ifu_bp_ctl.scala 386:26] bht_bank_clken[1][15] <= _T_6555 @[el2_ifu_bp_ctl.scala 386:26]
inst rvclkhdr of rvclkhdr @[el2_lib.scala 407:22]
rvclkhdr.clock <= clock
rvclkhdr.reset <= reset
rvclkhdr.io.clk <= clock @[el2_lib.scala 408:17]
rvclkhdr.io.en <= bht_bank_clken[0][0] @[el2_lib.scala 409:16]
rvclkhdr.io.scan_mode <= UInt<1>("h01") @[el2_lib.scala 410:23]
inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 407:22]
rvclkhdr_1.clock <= clock
rvclkhdr_1.reset <= reset
rvclkhdr_1.io.clk <= clock @[el2_lib.scala 408:17]
rvclkhdr_1.io.en <= bht_bank_clken[0][1] @[el2_lib.scala 409:16]
rvclkhdr_1.io.scan_mode <= UInt<1>("h01") @[el2_lib.scala 410:23]
inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 407:22]
rvclkhdr_2.clock <= clock
rvclkhdr_2.reset <= reset
rvclkhdr_2.io.clk <= clock @[el2_lib.scala 408:17]
rvclkhdr_2.io.en <= bht_bank_clken[0][2] @[el2_lib.scala 409:16]
rvclkhdr_2.io.scan_mode <= UInt<1>("h01") @[el2_lib.scala 410:23]
inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 407:22]
rvclkhdr_3.clock <= clock
rvclkhdr_3.reset <= reset
rvclkhdr_3.io.clk <= clock @[el2_lib.scala 408:17]
rvclkhdr_3.io.en <= bht_bank_clken[0][3] @[el2_lib.scala 409:16]
rvclkhdr_3.io.scan_mode <= UInt<1>("h01") @[el2_lib.scala 410:23]
inst rvclkhdr_4 of rvclkhdr_4 @[el2_lib.scala 407:22]
rvclkhdr_4.clock <= clock
rvclkhdr_4.reset <= reset
rvclkhdr_4.io.clk <= clock @[el2_lib.scala 408:17]
rvclkhdr_4.io.en <= bht_bank_clken[0][4] @[el2_lib.scala 409:16]
rvclkhdr_4.io.scan_mode <= UInt<1>("h01") @[el2_lib.scala 410:23]
inst rvclkhdr_5 of rvclkhdr_5 @[el2_lib.scala 407:22]
rvclkhdr_5.clock <= clock
rvclkhdr_5.reset <= reset
rvclkhdr_5.io.clk <= clock @[el2_lib.scala 408:17]
rvclkhdr_5.io.en <= bht_bank_clken[0][5] @[el2_lib.scala 409:16]
rvclkhdr_5.io.scan_mode <= UInt<1>("h01") @[el2_lib.scala 410:23]
inst rvclkhdr_6 of rvclkhdr_6 @[el2_lib.scala 407:22]
rvclkhdr_6.clock <= clock
rvclkhdr_6.reset <= reset
rvclkhdr_6.io.clk <= clock @[el2_lib.scala 408:17]
rvclkhdr_6.io.en <= bht_bank_clken[0][6] @[el2_lib.scala 409:16]
rvclkhdr_6.io.scan_mode <= UInt<1>("h01") @[el2_lib.scala 410:23]
inst rvclkhdr_7 of rvclkhdr_7 @[el2_lib.scala 407:22]
rvclkhdr_7.clock <= clock
rvclkhdr_7.reset <= reset
rvclkhdr_7.io.clk <= clock @[el2_lib.scala 408:17]
rvclkhdr_7.io.en <= bht_bank_clken[0][7] @[el2_lib.scala 409:16]
rvclkhdr_7.io.scan_mode <= UInt<1>("h01") @[el2_lib.scala 410:23]
inst rvclkhdr_8 of rvclkhdr_8 @[el2_lib.scala 407:22]
rvclkhdr_8.clock <= clock
rvclkhdr_8.reset <= reset
rvclkhdr_8.io.clk <= clock @[el2_lib.scala 408:17]
rvclkhdr_8.io.en <= bht_bank_clken[0][8] @[el2_lib.scala 409:16]
rvclkhdr_8.io.scan_mode <= UInt<1>("h01") @[el2_lib.scala 410:23]
inst rvclkhdr_9 of rvclkhdr_9 @[el2_lib.scala 407:22]
rvclkhdr_9.clock <= clock
rvclkhdr_9.reset <= reset
rvclkhdr_9.io.clk <= clock @[el2_lib.scala 408:17]
rvclkhdr_9.io.en <= bht_bank_clken[0][9] @[el2_lib.scala 409:16]
rvclkhdr_9.io.scan_mode <= UInt<1>("h01") @[el2_lib.scala 410:23]
inst rvclkhdr_10 of rvclkhdr_10 @[el2_lib.scala 407:22]
rvclkhdr_10.clock <= clock
rvclkhdr_10.reset <= reset
rvclkhdr_10.io.clk <= clock @[el2_lib.scala 408:17]
rvclkhdr_10.io.en <= bht_bank_clken[0][10] @[el2_lib.scala 409:16]
rvclkhdr_10.io.scan_mode <= UInt<1>("h01") @[el2_lib.scala 410:23]
inst rvclkhdr_11 of rvclkhdr_11 @[el2_lib.scala 407:22]
rvclkhdr_11.clock <= clock
rvclkhdr_11.reset <= reset
rvclkhdr_11.io.clk <= clock @[el2_lib.scala 408:17]
rvclkhdr_11.io.en <= bht_bank_clken[0][11] @[el2_lib.scala 409:16]
rvclkhdr_11.io.scan_mode <= UInt<1>("h01") @[el2_lib.scala 410:23]
inst rvclkhdr_12 of rvclkhdr_12 @[el2_lib.scala 407:22]
rvclkhdr_12.clock <= clock
rvclkhdr_12.reset <= reset
rvclkhdr_12.io.clk <= clock @[el2_lib.scala 408:17]
rvclkhdr_12.io.en <= bht_bank_clken[0][12] @[el2_lib.scala 409:16]
rvclkhdr_12.io.scan_mode <= UInt<1>("h01") @[el2_lib.scala 410:23]
inst rvclkhdr_13 of rvclkhdr_13 @[el2_lib.scala 407:22]
rvclkhdr_13.clock <= clock
rvclkhdr_13.reset <= reset
rvclkhdr_13.io.clk <= clock @[el2_lib.scala 408:17]
rvclkhdr_13.io.en <= bht_bank_clken[0][13] @[el2_lib.scala 409:16]
rvclkhdr_13.io.scan_mode <= UInt<1>("h01") @[el2_lib.scala 410:23]
inst rvclkhdr_14 of rvclkhdr_14 @[el2_lib.scala 407:22]
rvclkhdr_14.clock <= clock
rvclkhdr_14.reset <= reset
rvclkhdr_14.io.clk <= clock @[el2_lib.scala 408:17]
rvclkhdr_14.io.en <= bht_bank_clken[0][14] @[el2_lib.scala 409:16]
rvclkhdr_14.io.scan_mode <= UInt<1>("h01") @[el2_lib.scala 410:23]
inst rvclkhdr_15 of rvclkhdr_15 @[el2_lib.scala 407:22]
rvclkhdr_15.clock <= clock
rvclkhdr_15.reset <= reset
rvclkhdr_15.io.clk <= clock @[el2_lib.scala 408:17]
rvclkhdr_15.io.en <= bht_bank_clken[0][15] @[el2_lib.scala 409:16]
rvclkhdr_15.io.scan_mode <= UInt<1>("h01") @[el2_lib.scala 410:23]
inst rvclkhdr_16 of rvclkhdr_16 @[el2_lib.scala 407:22]
rvclkhdr_16.clock <= clock
rvclkhdr_16.reset <= reset
rvclkhdr_16.io.clk <= clock @[el2_lib.scala 408:17]
rvclkhdr_16.io.en <= bht_bank_clken[1][0] @[el2_lib.scala 409:16]
rvclkhdr_16.io.scan_mode <= UInt<1>("h01") @[el2_lib.scala 410:23]
inst rvclkhdr_17 of rvclkhdr_17 @[el2_lib.scala 407:22]
rvclkhdr_17.clock <= clock
rvclkhdr_17.reset <= reset
rvclkhdr_17.io.clk <= clock @[el2_lib.scala 408:17]
rvclkhdr_17.io.en <= bht_bank_clken[1][1] @[el2_lib.scala 409:16]
rvclkhdr_17.io.scan_mode <= UInt<1>("h01") @[el2_lib.scala 410:23]
inst rvclkhdr_18 of rvclkhdr_18 @[el2_lib.scala 407:22]
rvclkhdr_18.clock <= clock
rvclkhdr_18.reset <= reset
rvclkhdr_18.io.clk <= clock @[el2_lib.scala 408:17]
rvclkhdr_18.io.en <= bht_bank_clken[1][2] @[el2_lib.scala 409:16]
rvclkhdr_18.io.scan_mode <= UInt<1>("h01") @[el2_lib.scala 410:23]
inst rvclkhdr_19 of rvclkhdr_19 @[el2_lib.scala 407:22]
rvclkhdr_19.clock <= clock
rvclkhdr_19.reset <= reset
rvclkhdr_19.io.clk <= clock @[el2_lib.scala 408:17]
rvclkhdr_19.io.en <= bht_bank_clken[1][3] @[el2_lib.scala 409:16]
rvclkhdr_19.io.scan_mode <= UInt<1>("h01") @[el2_lib.scala 410:23]
inst rvclkhdr_20 of rvclkhdr_20 @[el2_lib.scala 407:22]
rvclkhdr_20.clock <= clock
rvclkhdr_20.reset <= reset
rvclkhdr_20.io.clk <= clock @[el2_lib.scala 408:17]
rvclkhdr_20.io.en <= bht_bank_clken[1][4] @[el2_lib.scala 409:16]
rvclkhdr_20.io.scan_mode <= UInt<1>("h01") @[el2_lib.scala 410:23]
inst rvclkhdr_21 of rvclkhdr_21 @[el2_lib.scala 407:22]
rvclkhdr_21.clock <= clock
rvclkhdr_21.reset <= reset
rvclkhdr_21.io.clk <= clock @[el2_lib.scala 408:17]
rvclkhdr_21.io.en <= bht_bank_clken[1][5] @[el2_lib.scala 409:16]
rvclkhdr_21.io.scan_mode <= UInt<1>("h01") @[el2_lib.scala 410:23]
inst rvclkhdr_22 of rvclkhdr_22 @[el2_lib.scala 407:22]
rvclkhdr_22.clock <= clock
rvclkhdr_22.reset <= reset
rvclkhdr_22.io.clk <= clock @[el2_lib.scala 408:17]
rvclkhdr_22.io.en <= bht_bank_clken[1][6] @[el2_lib.scala 409:16]
rvclkhdr_22.io.scan_mode <= UInt<1>("h01") @[el2_lib.scala 410:23]
inst rvclkhdr_23 of rvclkhdr_23 @[el2_lib.scala 407:22]
rvclkhdr_23.clock <= clock
rvclkhdr_23.reset <= reset
rvclkhdr_23.io.clk <= clock @[el2_lib.scala 408:17]
rvclkhdr_23.io.en <= bht_bank_clken[1][7] @[el2_lib.scala 409:16]
rvclkhdr_23.io.scan_mode <= UInt<1>("h01") @[el2_lib.scala 410:23]
inst rvclkhdr_24 of rvclkhdr_24 @[el2_lib.scala 407:22]
rvclkhdr_24.clock <= clock
rvclkhdr_24.reset <= reset
rvclkhdr_24.io.clk <= clock @[el2_lib.scala 408:17]
rvclkhdr_24.io.en <= bht_bank_clken[1][8] @[el2_lib.scala 409:16]
rvclkhdr_24.io.scan_mode <= UInt<1>("h01") @[el2_lib.scala 410:23]
inst rvclkhdr_25 of rvclkhdr_25 @[el2_lib.scala 407:22]
rvclkhdr_25.clock <= clock
rvclkhdr_25.reset <= reset
rvclkhdr_25.io.clk <= clock @[el2_lib.scala 408:17]
rvclkhdr_25.io.en <= bht_bank_clken[1][9] @[el2_lib.scala 409:16]
rvclkhdr_25.io.scan_mode <= UInt<1>("h01") @[el2_lib.scala 410:23]
inst rvclkhdr_26 of rvclkhdr_26 @[el2_lib.scala 407:22]
rvclkhdr_26.clock <= clock
rvclkhdr_26.reset <= reset
rvclkhdr_26.io.clk <= clock @[el2_lib.scala 408:17]
rvclkhdr_26.io.en <= bht_bank_clken[1][10] @[el2_lib.scala 409:16]
rvclkhdr_26.io.scan_mode <= UInt<1>("h01") @[el2_lib.scala 410:23]
inst rvclkhdr_27 of rvclkhdr_27 @[el2_lib.scala 407:22]
rvclkhdr_27.clock <= clock
rvclkhdr_27.reset <= reset
rvclkhdr_27.io.clk <= clock @[el2_lib.scala 408:17]
rvclkhdr_27.io.en <= bht_bank_clken[1][11] @[el2_lib.scala 409:16]
rvclkhdr_27.io.scan_mode <= UInt<1>("h01") @[el2_lib.scala 410:23]
inst rvclkhdr_28 of rvclkhdr_28 @[el2_lib.scala 407:22]
rvclkhdr_28.clock <= clock
rvclkhdr_28.reset <= reset
rvclkhdr_28.io.clk <= clock @[el2_lib.scala 408:17]
rvclkhdr_28.io.en <= bht_bank_clken[1][12] @[el2_lib.scala 409:16]
rvclkhdr_28.io.scan_mode <= UInt<1>("h01") @[el2_lib.scala 410:23]
inst rvclkhdr_29 of rvclkhdr_29 @[el2_lib.scala 407:22]
rvclkhdr_29.clock <= clock
rvclkhdr_29.reset <= reset
rvclkhdr_29.io.clk <= clock @[el2_lib.scala 408:17]
rvclkhdr_29.io.en <= bht_bank_clken[1][13] @[el2_lib.scala 409:16]
rvclkhdr_29.io.scan_mode <= UInt<1>("h01") @[el2_lib.scala 410:23]
inst rvclkhdr_30 of rvclkhdr_30 @[el2_lib.scala 407:22]
rvclkhdr_30.clock <= clock
rvclkhdr_30.reset <= reset
rvclkhdr_30.io.clk <= clock @[el2_lib.scala 408:17]
rvclkhdr_30.io.en <= bht_bank_clken[1][14] @[el2_lib.scala 409:16]
rvclkhdr_30.io.scan_mode <= UInt<1>("h01") @[el2_lib.scala 410:23]
inst rvclkhdr_31 of rvclkhdr_31 @[el2_lib.scala 407:22]
rvclkhdr_31.clock <= clock
rvclkhdr_31.reset <= reset
rvclkhdr_31.io.clk <= clock @[el2_lib.scala 408:17]
rvclkhdr_31.io.en <= bht_bank_clken[1][15] @[el2_lib.scala 409:16]
rvclkhdr_31.io.scan_mode <= UInt<1>("h01") @[el2_lib.scala 410:23]
node _T_6556 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 394:20] node _T_6556 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 394:20]
node _T_6557 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 394:37] node _T_6557 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 394:37]
node _T_6558 = eq(_T_6557, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 394:74] node _T_6558 = eq(_T_6557, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 394:74]

274
el2_ifu_bp_ctl.v
View File

@ -1,21 +1,3 @@
module rvclkhdr(
input io_clk,
input io_en
);
wire clkhdr_Q; // @[el2_lib.scala 398:26]
wire clkhdr_CK; // @[el2_lib.scala 398:26]
wire clkhdr_EN; // @[el2_lib.scala 398:26]
wire clkhdr_SE; // @[el2_lib.scala 398:26]
TEC_RV_ICG clkhdr ( // @[el2_lib.scala 398:26]
.Q(clkhdr_Q),
.CK(clkhdr_CK),
.EN(clkhdr_EN),
.SE(clkhdr_SE)
);
assign clkhdr_CK = io_clk; // @[el2_lib.scala 400:18]
assign clkhdr_EN = io_en; // @[el2_lib.scala 401:18]
assign clkhdr_SE = 1'h1; // @[el2_lib.scala 402:18]
endmodule
module el2_ifu_bp_ctl( module el2_ifu_bp_ctl(
input clock, input clock,
input reset, input reset,
@ -1106,70 +1088,6 @@ module el2_ifu_bp_ctl(
reg [31:0] _RAND_1037; reg [31:0] _RAND_1037;
reg [31:0] _RAND_1038; reg [31:0] _RAND_1038;
`endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE_REG_INIT
wire rvclkhdr_io_clk; // @[el2_lib.scala 407:22]
wire rvclkhdr_io_en; // @[el2_lib.scala 407:22]
wire rvclkhdr_1_io_clk; // @[el2_lib.scala 407:22]
wire rvclkhdr_1_io_en; // @[el2_lib.scala 407:22]
wire rvclkhdr_2_io_clk; // @[el2_lib.scala 407:22]
wire rvclkhdr_2_io_en; // @[el2_lib.scala 407:22]
wire rvclkhdr_3_io_clk; // @[el2_lib.scala 407:22]
wire rvclkhdr_3_io_en; // @[el2_lib.scala 407:22]
wire rvclkhdr_4_io_clk; // @[el2_lib.scala 407:22]
wire rvclkhdr_4_io_en; // @[el2_lib.scala 407:22]
wire rvclkhdr_5_io_clk; // @[el2_lib.scala 407:22]
wire rvclkhdr_5_io_en; // @[el2_lib.scala 407:22]
wire rvclkhdr_6_io_clk; // @[el2_lib.scala 407:22]
wire rvclkhdr_6_io_en; // @[el2_lib.scala 407:22]
wire rvclkhdr_7_io_clk; // @[el2_lib.scala 407:22]
wire rvclkhdr_7_io_en; // @[el2_lib.scala 407:22]
wire rvclkhdr_8_io_clk; // @[el2_lib.scala 407:22]
wire rvclkhdr_8_io_en; // @[el2_lib.scala 407:22]
wire rvclkhdr_9_io_clk; // @[el2_lib.scala 407:22]
wire rvclkhdr_9_io_en; // @[el2_lib.scala 407:22]
wire rvclkhdr_10_io_clk; // @[el2_lib.scala 407:22]
wire rvclkhdr_10_io_en; // @[el2_lib.scala 407:22]
wire rvclkhdr_11_io_clk; // @[el2_lib.scala 407:22]
wire rvclkhdr_11_io_en; // @[el2_lib.scala 407:22]
wire rvclkhdr_12_io_clk; // @[el2_lib.scala 407:22]
wire rvclkhdr_12_io_en; // @[el2_lib.scala 407:22]
wire rvclkhdr_13_io_clk; // @[el2_lib.scala 407:22]
wire rvclkhdr_13_io_en; // @[el2_lib.scala 407:22]
wire rvclkhdr_14_io_clk; // @[el2_lib.scala 407:22]
wire rvclkhdr_14_io_en; // @[el2_lib.scala 407:22]
wire rvclkhdr_15_io_clk; // @[el2_lib.scala 407:22]
wire rvclkhdr_15_io_en; // @[el2_lib.scala 407:22]
wire rvclkhdr_16_io_clk; // @[el2_lib.scala 407:22]
wire rvclkhdr_16_io_en; // @[el2_lib.scala 407:22]
wire rvclkhdr_17_io_clk; // @[el2_lib.scala 407:22]
wire rvclkhdr_17_io_en; // @[el2_lib.scala 407:22]
wire rvclkhdr_18_io_clk; // @[el2_lib.scala 407:22]
wire rvclkhdr_18_io_en; // @[el2_lib.scala 407:22]
wire rvclkhdr_19_io_clk; // @[el2_lib.scala 407:22]
wire rvclkhdr_19_io_en; // @[el2_lib.scala 407:22]
wire rvclkhdr_20_io_clk; // @[el2_lib.scala 407:22]
wire rvclkhdr_20_io_en; // @[el2_lib.scala 407:22]
wire rvclkhdr_21_io_clk; // @[el2_lib.scala 407:22]
wire rvclkhdr_21_io_en; // @[el2_lib.scala 407:22]
wire rvclkhdr_22_io_clk; // @[el2_lib.scala 407:22]
wire rvclkhdr_22_io_en; // @[el2_lib.scala 407:22]
wire rvclkhdr_23_io_clk; // @[el2_lib.scala 407:22]
wire rvclkhdr_23_io_en; // @[el2_lib.scala 407:22]
wire rvclkhdr_24_io_clk; // @[el2_lib.scala 407:22]
wire rvclkhdr_24_io_en; // @[el2_lib.scala 407:22]
wire rvclkhdr_25_io_clk; // @[el2_lib.scala 407:22]
wire rvclkhdr_25_io_en; // @[el2_lib.scala 407:22]
wire rvclkhdr_26_io_clk; // @[el2_lib.scala 407:22]
wire rvclkhdr_26_io_en; // @[el2_lib.scala 407:22]
wire rvclkhdr_27_io_clk; // @[el2_lib.scala 407:22]
wire rvclkhdr_27_io_en; // @[el2_lib.scala 407:22]
wire rvclkhdr_28_io_clk; // @[el2_lib.scala 407:22]
wire rvclkhdr_28_io_en; // @[el2_lib.scala 407:22]
wire rvclkhdr_29_io_clk; // @[el2_lib.scala 407:22]
wire rvclkhdr_29_io_en; // @[el2_lib.scala 407:22]
wire rvclkhdr_30_io_clk; // @[el2_lib.scala 407:22]
wire rvclkhdr_30_io_en; // @[el2_lib.scala 407:22]
wire rvclkhdr_31_io_clk; // @[el2_lib.scala 407:22]
wire rvclkhdr_31_io_en; // @[el2_lib.scala 407:22]
wire _T_40 = io_dec_tlu_flush_leak_one_wb & io_dec_tlu_flush_lower_wb; // @[el2_ifu_bp_ctl.scala 141:47] wire _T_40 = io_dec_tlu_flush_leak_one_wb & io_dec_tlu_flush_lower_wb; // @[el2_ifu_bp_ctl.scala 141:47]
reg leak_one_f_d1; // @[el2_ifu_bp_ctl.scala 135:56] reg leak_one_f_d1; // @[el2_ifu_bp_ctl.scala 135:56]
wire _T_41 = leak_one_f_d1 & io_dec_tlu_flush_lower_wb; // @[el2_ifu_bp_ctl.scala 141:93] wire _T_41 = leak_one_f_d1 & io_dec_tlu_flush_lower_wb; // @[el2_ifu_bp_ctl.scala 141:93]
@ -10720,134 +10638,6 @@ module el2_ifu_bp_ctl(
wire _T_20886 = bht_bank_sel_1_15_13 & bht_bank_clken_1_15; // @[el2_ifu_bp_ctl.scala 405:105] wire _T_20886 = bht_bank_sel_1_15_13 & bht_bank_clken_1_15; // @[el2_ifu_bp_ctl.scala 405:105]
wire _T_20888 = bht_bank_sel_1_15_14 & bht_bank_clken_1_15; // @[el2_ifu_bp_ctl.scala 405:105] wire _T_20888 = bht_bank_sel_1_15_14 & bht_bank_clken_1_15; // @[el2_ifu_bp_ctl.scala 405:105]
wire _T_20890 = bht_bank_sel_1_15_15 & bht_bank_clken_1_15; // @[el2_ifu_bp_ctl.scala 405:105] wire _T_20890 = bht_bank_sel_1_15_15 & bht_bank_clken_1_15; // @[el2_ifu_bp_ctl.scala 405:105]
rvclkhdr rvclkhdr ( // @[el2_lib.scala 407:22]
.io_clk(rvclkhdr_io_clk),
.io_en(rvclkhdr_io_en)
);
rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 407:22]
.io_clk(rvclkhdr_1_io_clk),
.io_en(rvclkhdr_1_io_en)
);
rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 407:22]
.io_clk(rvclkhdr_2_io_clk),
.io_en(rvclkhdr_2_io_en)
);
rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 407:22]
.io_clk(rvclkhdr_3_io_clk),
.io_en(rvclkhdr_3_io_en)
);
rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 407:22]
.io_clk(rvclkhdr_4_io_clk),
.io_en(rvclkhdr_4_io_en)
);
rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 407:22]
.io_clk(rvclkhdr_5_io_clk),
.io_en(rvclkhdr_5_io_en)
);
rvclkhdr rvclkhdr_6 ( // @[el2_lib.scala 407:22]
.io_clk(rvclkhdr_6_io_clk),
.io_en(rvclkhdr_6_io_en)
);
rvclkhdr rvclkhdr_7 ( // @[el2_lib.scala 407:22]
.io_clk(rvclkhdr_7_io_clk),
.io_en(rvclkhdr_7_io_en)
);
rvclkhdr rvclkhdr_8 ( // @[el2_lib.scala 407:22]
.io_clk(rvclkhdr_8_io_clk),
.io_en(rvclkhdr_8_io_en)
);
rvclkhdr rvclkhdr_9 ( // @[el2_lib.scala 407:22]
.io_clk(rvclkhdr_9_io_clk),
.io_en(rvclkhdr_9_io_en)
);
rvclkhdr rvclkhdr_10 ( // @[el2_lib.scala 407:22]
.io_clk(rvclkhdr_10_io_clk),
.io_en(rvclkhdr_10_io_en)
);
rvclkhdr rvclkhdr_11 ( // @[el2_lib.scala 407:22]
.io_clk(rvclkhdr_11_io_clk),
.io_en(rvclkhdr_11_io_en)
);
rvclkhdr rvclkhdr_12 ( // @[el2_lib.scala 407:22]
.io_clk(rvclkhdr_12_io_clk),
.io_en(rvclkhdr_12_io_en)
);
rvclkhdr rvclkhdr_13 ( // @[el2_lib.scala 407:22]
.io_clk(rvclkhdr_13_io_clk),
.io_en(rvclkhdr_13_io_en)
);
rvclkhdr rvclkhdr_14 ( // @[el2_lib.scala 407:22]
.io_clk(rvclkhdr_14_io_clk),
.io_en(rvclkhdr_14_io_en)
);
rvclkhdr rvclkhdr_15 ( // @[el2_lib.scala 407:22]
.io_clk(rvclkhdr_15_io_clk),
.io_en(rvclkhdr_15_io_en)
);
rvclkhdr rvclkhdr_16 ( // @[el2_lib.scala 407:22]
.io_clk(rvclkhdr_16_io_clk),
.io_en(rvclkhdr_16_io_en)
);
rvclkhdr rvclkhdr_17 ( // @[el2_lib.scala 407:22]
.io_clk(rvclkhdr_17_io_clk),
.io_en(rvclkhdr_17_io_en)
);
rvclkhdr rvclkhdr_18 ( // @[el2_lib.scala 407:22]
.io_clk(rvclkhdr_18_io_clk),
.io_en(rvclkhdr_18_io_en)
);
rvclkhdr rvclkhdr_19 ( // @[el2_lib.scala 407:22]
.io_clk(rvclkhdr_19_io_clk),
.io_en(rvclkhdr_19_io_en)
);
rvclkhdr rvclkhdr_20 ( // @[el2_lib.scala 407:22]
.io_clk(rvclkhdr_20_io_clk),
.io_en(rvclkhdr_20_io_en)
);
rvclkhdr rvclkhdr_21 ( // @[el2_lib.scala 407:22]
.io_clk(rvclkhdr_21_io_clk),
.io_en(rvclkhdr_21_io_en)
);
rvclkhdr rvclkhdr_22 ( // @[el2_lib.scala 407:22]
.io_clk(rvclkhdr_22_io_clk),
.io_en(rvclkhdr_22_io_en)
);
rvclkhdr rvclkhdr_23 ( // @[el2_lib.scala 407:22]
.io_clk(rvclkhdr_23_io_clk),
.io_en(rvclkhdr_23_io_en)
);
rvclkhdr rvclkhdr_24 ( // @[el2_lib.scala 407:22]
.io_clk(rvclkhdr_24_io_clk),
.io_en(rvclkhdr_24_io_en)
);
rvclkhdr rvclkhdr_25 ( // @[el2_lib.scala 407:22]
.io_clk(rvclkhdr_25_io_clk),
.io_en(rvclkhdr_25_io_en)
);
rvclkhdr rvclkhdr_26 ( // @[el2_lib.scala 407:22]
.io_clk(rvclkhdr_26_io_clk),
.io_en(rvclkhdr_26_io_en)
);
rvclkhdr rvclkhdr_27 ( // @[el2_lib.scala 407:22]
.io_clk(rvclkhdr_27_io_clk),
.io_en(rvclkhdr_27_io_en)
);
rvclkhdr rvclkhdr_28 ( // @[el2_lib.scala 407:22]
.io_clk(rvclkhdr_28_io_clk),
.io_en(rvclkhdr_28_io_en)
);
rvclkhdr rvclkhdr_29 ( // @[el2_lib.scala 407:22]
.io_clk(rvclkhdr_29_io_clk),
.io_en(rvclkhdr_29_io_en)
);
rvclkhdr rvclkhdr_30 ( // @[el2_lib.scala 407:22]
.io_clk(rvclkhdr_30_io_clk),
.io_en(rvclkhdr_30_io_en)
);
rvclkhdr rvclkhdr_31 ( // @[el2_lib.scala 407:22]
.io_clk(rvclkhdr_31_io_clk),
.io_en(rvclkhdr_31_io_en)
);
assign io_ifu_bp_hit_taken_f = _T_236 & _T_237; // @[el2_ifu_bp_ctl.scala 43:25 el2_ifu_bp_ctl.scala 243:25] assign io_ifu_bp_hit_taken_f = _T_236 & _T_237; // @[el2_ifu_bp_ctl.scala 43:25 el2_ifu_bp_ctl.scala 243:25]
assign io_ifu_bp_btb_target_f = _T_425 ? rets_out_0[31:1] : bp_btb_target_adder_f[31:1]; // @[el2_ifu_bp_ctl.scala 44:26 el2_ifu_bp_ctl.scala 325:26] assign io_ifu_bp_btb_target_f = _T_425 ? rets_out_0[31:1] : bp_btb_target_adder_f[31:1]; // @[el2_ifu_bp_ctl.scala 44:26 el2_ifu_bp_ctl.scala 325:26]
assign io_ifu_bp_inst_mask_f = _T_273 | _T_274; // @[el2_ifu_bp_ctl.scala 45:25 el2_ifu_bp_ctl.scala 263:25] assign io_ifu_bp_inst_mask_f = _T_273 | _T_274; // @[el2_ifu_bp_ctl.scala 45:25 el2_ifu_bp_ctl.scala 263:25]
@ -10859,70 +10649,6 @@ module el2_ifu_bp_ctl(
assign io_ifu_bp_pc4_f = {_T_284,_T_287}; // @[el2_ifu_bp_ctl.scala 51:19 el2_ifu_bp_ctl.scala 300:19] assign io_ifu_bp_pc4_f = {_T_284,_T_287}; // @[el2_ifu_bp_ctl.scala 51:19 el2_ifu_bp_ctl.scala 300:19]
assign io_ifu_bp_valid_f = vwayhit_f & _T_342; // @[el2_ifu_bp_ctl.scala 52:21 el2_ifu_bp_ctl.scala 302:21] assign io_ifu_bp_valid_f = vwayhit_f & _T_342; // @[el2_ifu_bp_ctl.scala 52:21 el2_ifu_bp_ctl.scala 302:21]
assign io_ifu_bp_poffset_f = btb_sel_data_f[15:4]; // @[el2_ifu_bp_ctl.scala 53:23 el2_ifu_bp_ctl.scala 315:23] assign io_ifu_bp_poffset_f = btb_sel_data_f[15:4]; // @[el2_ifu_bp_ctl.scala 53:23 el2_ifu_bp_ctl.scala 315:23]
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 408:17]
assign rvclkhdr_io_en = _T_6208 | _T_6213; // @[el2_lib.scala 409:16]
assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 408:17]
assign rvclkhdr_1_io_en = _T_6219 | _T_6224; // @[el2_lib.scala 409:16]
assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 408:17]
assign rvclkhdr_2_io_en = _T_6230 | _T_6235; // @[el2_lib.scala 409:16]
assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 408:17]
assign rvclkhdr_3_io_en = _T_6241 | _T_6246; // @[el2_lib.scala 409:16]
assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 408:17]
assign rvclkhdr_4_io_en = _T_6252 | _T_6257; // @[el2_lib.scala 409:16]
assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 408:17]
assign rvclkhdr_5_io_en = _T_6263 | _T_6268; // @[el2_lib.scala 409:16]
assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 408:17]
assign rvclkhdr_6_io_en = _T_6274 | _T_6279; // @[el2_lib.scala 409:16]
assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 408:17]
assign rvclkhdr_7_io_en = _T_6285 | _T_6290; // @[el2_lib.scala 409:16]
assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 408:17]
assign rvclkhdr_8_io_en = _T_6296 | _T_6301; // @[el2_lib.scala 409:16]
assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 408:17]
assign rvclkhdr_9_io_en = _T_6307 | _T_6312; // @[el2_lib.scala 409:16]
assign rvclkhdr_10_io_clk = clock; // @[el2_lib.scala 408:17]
assign rvclkhdr_10_io_en = _T_6318 | _T_6323; // @[el2_lib.scala 409:16]
assign rvclkhdr_11_io_clk = clock; // @[el2_lib.scala 408:17]
assign rvclkhdr_11_io_en = _T_6329 | _T_6334; // @[el2_lib.scala 409:16]
assign rvclkhdr_12_io_clk = clock; // @[el2_lib.scala 408:17]
assign rvclkhdr_12_io_en = _T_6340 | _T_6345; // @[el2_lib.scala 409:16]
assign rvclkhdr_13_io_clk = clock; // @[el2_lib.scala 408:17]
assign rvclkhdr_13_io_en = _T_6351 | _T_6356; // @[el2_lib.scala 409:16]
assign rvclkhdr_14_io_clk = clock; // @[el2_lib.scala 408:17]
assign rvclkhdr_14_io_en = _T_6362 | _T_6367; // @[el2_lib.scala 409:16]
assign rvclkhdr_15_io_clk = clock; // @[el2_lib.scala 408:17]
assign rvclkhdr_15_io_en = _T_6373 | _T_6378; // @[el2_lib.scala 409:16]
assign rvclkhdr_16_io_clk = clock; // @[el2_lib.scala 408:17]
assign rvclkhdr_16_io_en = _T_6384 | _T_6389; // @[el2_lib.scala 409:16]
assign rvclkhdr_17_io_clk = clock; // @[el2_lib.scala 408:17]
assign rvclkhdr_17_io_en = _T_6395 | _T_6400; // @[el2_lib.scala 409:16]
assign rvclkhdr_18_io_clk = clock; // @[el2_lib.scala 408:17]
assign rvclkhdr_18_io_en = _T_6406 | _T_6411; // @[el2_lib.scala 409:16]
assign rvclkhdr_19_io_clk = clock; // @[el2_lib.scala 408:17]
assign rvclkhdr_19_io_en = _T_6417 | _T_6422; // @[el2_lib.scala 409:16]
assign rvclkhdr_20_io_clk = clock; // @[el2_lib.scala 408:17]
assign rvclkhdr_20_io_en = _T_6428 | _T_6433; // @[el2_lib.scala 409:16]
assign rvclkhdr_21_io_clk = clock; // @[el2_lib.scala 408:17]
assign rvclkhdr_21_io_en = _T_6439 | _T_6444; // @[el2_lib.scala 409:16]
assign rvclkhdr_22_io_clk = clock; // @[el2_lib.scala 408:17]
assign rvclkhdr_22_io_en = _T_6450 | _T_6455; // @[el2_lib.scala 409:16]
assign rvclkhdr_23_io_clk = clock; // @[el2_lib.scala 408:17]
assign rvclkhdr_23_io_en = _T_6461 | _T_6466; // @[el2_lib.scala 409:16]
assign rvclkhdr_24_io_clk = clock; // @[el2_lib.scala 408:17]
assign rvclkhdr_24_io_en = _T_6472 | _T_6477; // @[el2_lib.scala 409:16]
assign rvclkhdr_25_io_clk = clock; // @[el2_lib.scala 408:17]
assign rvclkhdr_25_io_en = _T_6483 | _T_6488; // @[el2_lib.scala 409:16]
assign rvclkhdr_26_io_clk = clock; // @[el2_lib.scala 408:17]
assign rvclkhdr_26_io_en = _T_6494 | _T_6499; // @[el2_lib.scala 409:16]
assign rvclkhdr_27_io_clk = clock; // @[el2_lib.scala 408:17]
assign rvclkhdr_27_io_en = _T_6505 | _T_6510; // @[el2_lib.scala 409:16]
assign rvclkhdr_28_io_clk = clock; // @[el2_lib.scala 408:17]
assign rvclkhdr_28_io_en = _T_6516 | _T_6521; // @[el2_lib.scala 409:16]
assign rvclkhdr_29_io_clk = clock; // @[el2_lib.scala 408:17]
assign rvclkhdr_29_io_en = _T_6527 | _T_6532; // @[el2_lib.scala 409:16]
assign rvclkhdr_30_io_clk = clock; // @[el2_lib.scala 408:17]
assign rvclkhdr_30_io_en = _T_6538 | _T_6543; // @[el2_lib.scala 409:16]
assign rvclkhdr_31_io_clk = clock; // @[el2_lib.scala 408:17]
assign rvclkhdr_31_io_en = _T_6549 | _T_6554; // @[el2_lib.scala 409:16]
`ifdef RANDOMIZE_GARBAGE_ASSIGN `ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE `define RANDOMIZE
`endif `endif

4
src/main/scala/ifu/el2_ifu_bp_ctl.scala
View File

@ -387,8 +387,8 @@ class el2_ifu_bp_ctl extends Module with el2_lib with RequireAsyncReset {
(bht_wr_en2(i) & ((bht_wr_addr2(BHT_ADDR_HI-BHT_ADDR_LO,NUM_BHT_LOOP_OUTER_LO-2)===k.U) | BHT_NO_ADDR_MATCH.B)) (bht_wr_en2(i) & ((bht_wr_addr2(BHT_ADDR_HI-BHT_ADDR_LO,NUM_BHT_LOOP_OUTER_LO-2)===k.U) | BHT_NO_ADDR_MATCH.B))
} }
val bht_bank_clk = (0 until 2).map(i=>(0 until BHT_ARRAY_DEPTH/NUM_BHT_LOOP).map(k=> // val bht_bank_clk = (0 until 2).map(i=>(0 until BHT_ARRAY_DEPTH/NUM_BHT_LOOP).map(k=>
rvclkhdr(clock, bht_bank_clken(i)(k), 1.U.asBool))) // rvclkhdr(clock, bht_bank_clken(i)(k), 1.U.asBool)))
val bht_bank_wr_data = (0 until 2).map(i=>(0 until BHT_ARRAY_DEPTH/NUM_BHT_LOOP).map(k=>(0 until NUM_BHT_LOOP).map(j=> val bht_bank_wr_data = (0 until 2).map(i=>(0 until BHT_ARRAY_DEPTH/NUM_BHT_LOOP).map(k=>(0 until NUM_BHT_LOOP).map(j=>
Mux((bht_wr_en2(i)&(bht_wr_addr2(NUM_BHT_LOOP_INNER_HI-BHT_ADDR_LO,0)===j.asUInt)&(bht_wr_addr2(BHT_ADDR_HI-NUM_BHT_LOOP_OUTER_LO+1,NUM_BHT_LOOP_OUTER_LO-BHT_ADDR_LO)===k.asUInt)|BHT_NO_ADDR_MATCH.B).asBool, bht_wr_data2, bht_wr_data0)))) Mux((bht_wr_en2(i)&(bht_wr_addr2(NUM_BHT_LOOP_INNER_HI-BHT_ADDR_LO,0)===j.asUInt)&(bht_wr_addr2(BHT_ADDR_HI-NUM_BHT_LOOP_OUTER_LO+1,NUM_BHT_LOOP_OUTER_LO-BHT_ADDR_LO)===k.asUInt)|BHT_NO_ADDR_MATCH.B).asBool, bht_wr_data2, bht_wr_data0))))

34
src/main/scala/ifu/el2_ifu_mem_ctl.scala
View File

@ -122,6 +122,8 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
val ifu_ic_debug_rd_data_valid = Output(Bool()) val ifu_ic_debug_rd_data_valid = Output(Bool())
val iccm_buf_correct_ecc = Output(Bool()) val iccm_buf_correct_ecc = Output(Bool())
val iccm_correction_state = Output(Bool()) val iccm_correction_state = Output(Bool())
val scan_mode = Input(Bool())
}) })
io.ic_debug_rd_en:=0.U io.ic_debug_rd_en:=0.U
io.ic_debug_wr_en:=0.U io.ic_debug_wr_en:=0.U
@ -197,8 +199,38 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
io.iccm_correction_state:=0.U io.iccm_correction_state:=0.U
io.ic_debug_way:=0.U io.ic_debug_way:=0.U
io.ifu_axi_awregion:=0.U io.ifu_axi_awregion:=0.U
} val idle_C :: crit_byp_ok_C :: hit_u_miss_C :: miss_wait_C :: crit_wrd_rdy_C :: scnd_miss_C :: stream_C :: stall_scnd_miss_C :: Nil = Enum(8)
val err_stop_idle_C :: err_fetch1_C :: err_fetch2_C :: err_stop_fetch_C :: Nil = Enum(4)
val err_idle_C :: ic_wff_C :: ecc_wff_C :: ecc_cor_C :: dma_sb_err_C :: Nil = Enum(5)
val iccm_single_ecc_error = WireInit(UInt(2.W), 0.U)
val ifc_fetch_req_f = WireInit(Bool(), 0.U)
val miss_pending = WireInit(Bool(), 0.U)
val scnd_miss_req = WireInit(Bool(), 0.U)
val dma_iccm_req_f = WireInit(Bool(), 0.U)
val iccm_correct_ecc = WireInit(Bool(), 0.U)
val perr_state = WireInit(UInt(3.W), 0.U)
val err_stop_state = WireInit(UInt(2.W), 0.U)
val err_stop_fetch = WireInit(Bool(), 0.U)
val miss_state = WireInit(UInt(3.W), 0.U)
val miss_nxtstate = WireInit(UInt(3.W), 0.U)
val ifu_bus_rsp_valid = WireInit(Bool(), 0.U)
val bus_ifu_bus_clk_en = WireInit(Bool(), 0.U)
val ifu_bus_rsp_ready = WireInit(Bool(), 0.U)
val uncacheable_miss_ff = WireInit(Bool(), 0.U)
val bus_new_data_beat_count = WireInit(UInt(ICACHE_BEAT_BITS.W), 0.U)
val fetch_bf_f_c1_clken = io.ifc_fetch_req_bf_raw | ifc_fetch_req_f | miss_pending | io.exu_flush_final | scnd_miss_req
val debug_c1_clken = io.ic_debug_rd_en | io.ic_debug_wr_en
val debug_c1_clk = rvclkhdr(clock, debug_c1_clken, io.scan_mode)
val fetch_bf_f_c1_clk = rvclkhdr(clock, fetch_bf_f_c1_clken.asBool, io.scan_mode)
io.iccm_dma_sb_error := iccm_single_ecc_error.orR() & dma_iccm_req_f.asBool()
io.ifu_async_error_start := io.iccm_rd_ecc_single_err | io.ic_error_start
io.ic_dma_active := iccm_correct_ecc | (perr_state === dma_sb_err_C) | (err_stop_state === err_stop_fetch_C) | err_stop_fetch | io.dec_tlu_flush_err_wb
val scnd_miss_req_in = ifu_bus_rsp_valid & bus_ifu_bus_clk_en & ifu_bus_rsp_ready & bus_new_data_beat_count.andR &
!uncacheable_miss_ff ((miss_state === scnd_miss_C)|(miss_nxtstate === scnd_miss_C)) & !io.exu_flush_final
}
object ifu_mem extends App { object ifu_mem extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_mem_ctl())) println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_mem_ctl()))
} }

BIN
target/scala-2.12/classes/ifu/el2_ifu_bp_ctl.class
View File

Binary file not shown.

BIN
target/scala-2.12/classes/ifu/el2_ifu_mem_ctl$$anon$1.class
View File

Binary file not shown.

BIN
target/scala-2.12/classes/ifu/el2_ifu_mem_ctl.class
View File

Binary file not shown.

BIN
target/scala-2.12/classes/ifu/ifu_mem$.class
View File

Binary file not shown.

BIN
target/scala-2.12/classes/ifu/ifu_mem$delayedInit$body.class
View File

Binary file not shown.