Aligner Updated

el2_ifu_aln_ctl.fir

@@ -2002,7 +2002,7 @@ circuit el2_ifu_aln_ctl :
     error_stall_in <= UInt<1>("h00")
     wire alignval : UInt<2>
     alignval <= UInt<1>("h00")
-    wire q0final : UInt<16>
+    wire q0final : UInt<32>
     q0final <= UInt<1>("h00")
     wire q1final : UInt<16>
     q1final <= UInt<1>("h00")
@@ -2783,7 +2783,7 @@ circuit el2_ifu_aln_ctl :
     node _T_519 = mux(_T_512, q0final, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_520 = mux(_T_517, _T_518, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_521 = or(_T_519, _T_520) @[Mux.scala 27:72]
-    wire aligndata : UInt<32> @[Mux.scala 27:72]
+    wire aligndata : UInt<48> @[Mux.scala 27:72]
     aligndata <= _T_521 @[Mux.scala 27:72]
     node _T_522 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 302:30]
     node _T_523 = bits(_T_522, 0, 0) @[el2_ifu_aln_ctl.scala 302:34]
@@ -2999,7 +2999,7 @@ circuit el2_ifu_aln_ctl :
     node _T_695 = mux(_T_693, aligndata, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_696 = mux(_T_694, decompressed.io.dout, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_697 = or(_T_695, _T_696) @[Mux.scala 27:72]
-    wire _T_698 : UInt<32> @[Mux.scala 27:72]
+    wire _T_698 : UInt<48> @[Mux.scala 27:72]
     _T_698 <= _T_697 @[Mux.scala 27:72]
     io.ifu_i0_instr <= _T_698 @[el2_ifu_aln_ctl.scala 352:19]
     node _T_699 = bits(f0pc, 8, 1) @[el2_lib.scala 191:12]

el2_ifu_aln_ctl.v

@@ -620,9 +620,8 @@ module el2_ifu_aln_ctl(
   wire [31:0] _T_497 = q0sel[0] ? q0eff : 32'h0; // @[Mux.scala 27:72]
   wire [15:0] _T_498 = q0sel[1] ? q0eff[31:16] : 16'h0; // @[Mux.scala 27:72]
   wire [31:0] _GEN_12 = {{16'd0}, _T_498}; // @[Mux.scala 27:72]
-  wire [31:0] _T_499 = _T_497 | _GEN_12; // @[Mux.scala 27:72]
+  wire [31:0] q0final = _T_497 | _GEN_12; // @[Mux.scala 27:72]
-  wire [15:0] q0final = _T_499[15:0]; // @[el2_ifu_aln_ctl.scala 296:11]
+  wire [31:0] _T_519 = f0val[0] ? q0final : 32'h0; // @[Mux.scala 27:72]
-  wire [15:0] _T_519 = f0val[0] ? q0final : 16'h0; // @[Mux.scala 27:72]
   wire  _T_514 = ~f0val[1]; // @[el2_ifu_aln_ctl.scala 300:58]
   wire  _T_516 = _T_514 & f0val[0]; // @[el2_ifu_aln_ctl.scala 300:68]
   wire  _T_197 = _T_186 & q1off; // @[Mux.scala 27:72]
@@ -636,10 +635,10 @@ module el2_ifu_aln_ctl(
   wire [15:0] _T_507 = q1sel[0] ? q1eff[15:0] : 16'h0; // @[Mux.scala 27:72]
   wire [15:0] _T_508 = q1sel[1] ? q1eff[31:16] : 16'h0; // @[Mux.scala 27:72]
   wire [15:0] q1final = _T_507 | _T_508; // @[Mux.scala 27:72]
-  wire [31:0] _T_518 = {q1final,q0final}; // @[Cat.scala 29:58]
+  wire [47:0] _T_518 = {q1final,q0final}; // @[Cat.scala 29:58]
-  wire [31:0] _T_520 = _T_516 ? _T_518 : 32'h0; // @[Mux.scala 27:72]
+  wire [47:0] _T_520 = _T_516 ? _T_518 : 48'h0; // @[Mux.scala 27:72]
-  wire [31:0] _GEN_13 = {{16'd0}, _T_519}; // @[Mux.scala 27:72]
+  wire [47:0] _GEN_13 = {{16'd0}, _T_519}; // @[Mux.scala 27:72]
-  wire [31:0] aligndata = _GEN_13 | _T_520; // @[Mux.scala 27:72]
+  wire [47:0] aligndata = _GEN_13 | _T_520; // @[Mux.scala 27:72]
   wire  first4B = aligndata[1:0] == 2'h3; // @[el2_ifu_aln_ctl.scala 332:29]
   wire  first2B = ~first4B; // @[el2_ifu_aln_ctl.scala 334:17]
   wire  shift_2B = i0_shift & first2B; // @[el2_ifu_aln_ctl.scala 396:24]
@@ -948,8 +947,10 @@ module el2_ifu_aln_ctl(
   wire  _T_686 = |aligndbecc; // @[el2_ifu_aln_ctl.scala 346:59]
   wire  _T_689 = first4B & _T_686; // @[Mux.scala 27:72]
   wire  _T_690 = first2B & aligndbecc[0]; // @[Mux.scala 27:72]
-  wire [31:0] _T_695 = first4B ? aligndata : 32'h0; // @[Mux.scala 27:72]
+  wire [47:0] _T_695 = first4B ? aligndata : 48'h0; // @[Mux.scala 27:72]
   wire [31:0] _T_696 = first2B ? decompressed_io_dout : 32'h0; // @[Mux.scala 27:72]
+  wire [47:0] _GEN_21 = {{16'd0}, _T_696}; // @[Mux.scala 27:72]
+  wire [47:0] _T_697 = _T_695 | _GEN_21; // @[Mux.scala 27:72]
   wire [7:0] _T_701 = f0pc[8:1] ^ f0pc[16:9]; // @[el2_lib.scala 191:46]
   wire [7:0] firstpc_hash = _T_701 ^ f0pc[24:17]; // @[el2_lib.scala 191:84]
   wire [7:0] _T_705 = secondpc[8:1] ^ secondpc[16:9]; // @[el2_lib.scala 191:46]
@@ -990,7 +991,7 @@ module el2_ifu_aln_ctl(
   assign io_ifu_i0_icaf_type = _T_678 ? f1ictype : f0ictype; // @[el2_ifu_aln_ctl.scala 340:23]
   assign io_ifu_i0_icaf_f1 = _T_683 & _T_516; // @[el2_ifu_aln_ctl.scala 344:21]
   assign io_ifu_i0_dbecc = _T_689 | _T_690; // @[el2_ifu_aln_ctl.scala 346:19]
-  assign io_ifu_i0_instr = _T_695 | _T_696; // @[el2_ifu_aln_ctl.scala 352:19]
+  assign io_ifu_i0_instr = _T_697[31:0]; // @[el2_ifu_aln_ctl.scala 352:19]
   assign io_ifu_i0_pc = {{1'd0}, f0pc}; // @[el2_ifu_aln_ctl.scala 324:16]
   assign io_ifu_i0_pc4 = aligndata[1:0] == 2'h3; // @[el2_ifu_aln_ctl.scala 328:17]
   assign io_ifu_fb_consume1 = _T_313 & _T_1; // @[el2_ifu_aln_ctl.scala 242:22]

src/main/scala/ifu/el2_ifu_aln_ctl.scala

@@ -48,7 +48,7 @@ class el2_ifu_aln_ctl extends Module with el2_lib {
   val BRDATA_SIZE = 12
   val error_stall_in = WireInit(Bool(),0.U)
   val alignval = WireInit(UInt(2.W), 0.U)
-  val q0final = WireInit(UInt(16.W), 0.U)
+  val q0final = WireInit(UInt(32.W), 0.U)
   val q1final = WireInit(UInt(16.W), 0.U)
   val wrptr_in = WireInit(UInt(2.W), init = 0.U)
   val rdptr_in = WireInit(UInt(2.W), init = 0.U)