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ahb_size corrected in AHB/AXI

This commit is contained in:
​Laraib Khan 2021-01-13 12:29:47 +05:00
parent d13d0efa85
commit 9479360020
4 changed files with 57 additions and 57 deletions
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95
ahb_to_axi4.fir
View File

@ -453,76 +453,77 @@ circuit ahb_to_axi4 :
_T_170 <= ahb_hwrite_q @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
cmdbuf_write <= _T_170 @[ahb_to_axi4.scala 146:31]
node _T_171 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 147:78]
node _T_172 = and(io.bus_clk_en, _T_171) @[lib.scala 383:57]
reg _T_173 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_172 : @[Reg.scala 28:19]
_T_173 <= ahb_hsize_q @[Reg.scala 28:23]
node _T_171 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 147:57]
node _T_172 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 147:83]
node _T_173 = and(io.bus_clk_en, _T_172) @[lib.scala 383:57]
reg _T_174 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_173 : @[Reg.scala 28:19]
_T_174 <= _T_171 @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
cmdbuf_size <= _T_173 @[ahb_to_axi4.scala 147:31]
node _T_174 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 148:79]
node _T_175 = and(io.bus_clk_en, _T_174) @[lib.scala 383:57]
reg _T_176 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_175 : @[Reg.scala 28:19]
_T_176 <= master_wstrb @[Reg.scala 28:23]
cmdbuf_size <= _T_174 @[ahb_to_axi4.scala 147:31]
node _T_175 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 148:79]
node _T_176 = and(io.bus_clk_en, _T_175) @[lib.scala 383:57]
reg _T_177 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_176 : @[Reg.scala 28:19]
_T_177 <= master_wstrb @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
cmdbuf_wstrb <= _T_176 @[ahb_to_axi4.scala 148:31]
node _T_177 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 150:57]
node _T_178 = and(_T_177, io.bus_clk_en) @[ahb_to_axi4.scala 150:59]
cmdbuf_wstrb <= _T_177 @[ahb_to_axi4.scala 148:31]
node _T_178 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 150:57]
node _T_179 = and(_T_178, io.bus_clk_en) @[ahb_to_axi4.scala 150:59]
inst rvclkhdr of rvclkhdr @[lib.scala 399:23]
rvclkhdr.clock <= clock
rvclkhdr.reset <= reset
rvclkhdr.io.clk <= clock @[lib.scala 401:18]
rvclkhdr.io.en <= _T_178 @[lib.scala 402:17]
rvclkhdr.io.en <= _T_179 @[lib.scala 402:17]
rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24]
reg _T_179 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_178 : @[Reg.scala 28:19]
_T_179 <= ahb_haddr_q @[Reg.scala 28:23]
reg _T_180 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_179 : @[Reg.scala 28:19]
_T_180 <= ahb_haddr_q @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
cmdbuf_addr <= _T_179 @[ahb_to_axi4.scala 150:15]
node _T_180 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 151:68]
node _T_181 = and(_T_180, io.bus_clk_en) @[ahb_to_axi4.scala 151:70]
cmdbuf_addr <= _T_180 @[ahb_to_axi4.scala 150:15]
node _T_181 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 151:68]
node _T_182 = and(_T_181, io.bus_clk_en) @[ahb_to_axi4.scala 151:70]
inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 399:23]
rvclkhdr_1.clock <= clock
rvclkhdr_1.reset <= reset
rvclkhdr_1.io.clk <= clock @[lib.scala 401:18]
rvclkhdr_1.io.en <= _T_181 @[lib.scala 402:17]
rvclkhdr_1.io.en <= _T_182 @[lib.scala 402:17]
rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24]
reg _T_182 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_181 : @[Reg.scala 28:19]
_T_182 <= io.ahb.sig.out.hwdata @[Reg.scala 28:23]
reg _T_183 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_182 : @[Reg.scala 28:19]
_T_183 <= io.ahb.sig.out.hwdata @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
cmdbuf_wdata <= _T_182 @[ahb_to_axi4.scala 151:16]
node _T_183 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 154:42]
io.axi.aw.valid <= _T_183 @[ahb_to_axi4.scala 154:28]
cmdbuf_wdata <= _T_183 @[ahb_to_axi4.scala 151:16]
node _T_184 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 154:42]
io.axi.aw.valid <= _T_184 @[ahb_to_axi4.scala 154:28]
io.axi.aw.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 155:33]
io.axi.aw.bits.addr <= cmdbuf_addr @[ahb_to_axi4.scala 156:33]
node _T_184 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 157:59]
node _T_185 = cat(UInt<1>("h00"), _T_184) @[Cat.scala 29:58]
io.axi.aw.bits.size <= _T_185 @[ahb_to_axi4.scala 157:33]
node _T_186 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
io.axi.aw.bits.prot <= _T_186 @[ahb_to_axi4.scala 158:33]
node _T_187 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
io.axi.aw.bits.len <= _T_187 @[ahb_to_axi4.scala 159:33]
node _T_185 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 157:59]
node _T_186 = cat(UInt<1>("h00"), _T_185) @[Cat.scala 29:58]
io.axi.aw.bits.size <= _T_186 @[ahb_to_axi4.scala 157:33]
node _T_187 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
io.axi.aw.bits.prot <= _T_187 @[ahb_to_axi4.scala 158:33]
node _T_188 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
io.axi.aw.bits.len <= _T_188 @[ahb_to_axi4.scala 159:33]
io.axi.aw.bits.burst <= UInt<2>("h01") @[ahb_to_axi4.scala 160:33]
node _T_188 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 162:42]
io.axi.w.valid <= _T_188 @[ahb_to_axi4.scala 162:28]
node _T_189 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 162:42]
io.axi.w.valid <= _T_189 @[ahb_to_axi4.scala 162:28]
io.axi.w.bits.data <= cmdbuf_wdata @[ahb_to_axi4.scala 163:33]
io.axi.w.bits.strb <= cmdbuf_wstrb @[ahb_to_axi4.scala 164:33]
io.axi.w.bits.last <= UInt<1>("h01") @[ahb_to_axi4.scala 165:33]
io.axi.b.ready <= UInt<1>("h01") @[ahb_to_axi4.scala 167:28]
node _T_189 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 169:44]
node _T_190 = and(cmdbuf_vld, _T_189) @[ahb_to_axi4.scala 169:42]
io.axi.ar.valid <= _T_190 @[ahb_to_axi4.scala 169:28]
node _T_190 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 169:44]
node _T_191 = and(cmdbuf_vld, _T_190) @[ahb_to_axi4.scala 169:42]
io.axi.ar.valid <= _T_191 @[ahb_to_axi4.scala 169:28]
io.axi.ar.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 170:33]
io.axi.ar.bits.addr <= cmdbuf_addr @[ahb_to_axi4.scala 171:33]
node _T_191 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 172:59]
node _T_192 = cat(UInt<1>("h00"), _T_191) @[Cat.scala 29:58]
io.axi.ar.bits.size <= _T_192 @[ahb_to_axi4.scala 172:33]
node _T_193 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
io.axi.ar.bits.prot <= _T_193 @[ahb_to_axi4.scala 173:33]
node _T_194 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
io.axi.ar.bits.len <= _T_194 @[ahb_to_axi4.scala 174:33]
node _T_192 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 172:59]
node _T_193 = cat(UInt<1>("h00"), _T_192) @[Cat.scala 29:58]
io.axi.ar.bits.size <= _T_193 @[ahb_to_axi4.scala 172:33]
node _T_194 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
io.axi.ar.bits.prot <= _T_194 @[ahb_to_axi4.scala 173:33]
node _T_195 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
io.axi.ar.bits.len <= _T_195 @[ahb_to_axi4.scala 174:33]
io.axi.ar.bits.burst <= UInt<2>("h01") @[ahb_to_axi4.scala 175:33]
io.axi.r.ready <= UInt<1>("h01") @[ahb_to_axi4.scala 177:28]

17
ahb_to_axi4.v
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@ -219,13 +219,12 @@ module ahb_to_axi4(
wire _T_164 = cmdbuf_wr_en | cmdbuf_rst; // @[lib.scala 391:95]
wire _T_165 = _T_164 & io_bus_clk_en; // @[lib.scala 391:102]
wire _T_169 = io_bus_clk_en & cmdbuf_wr_en; // @[lib.scala 383:57]
reg [2:0] _T_173; // @[Reg.scala 27:20]
reg [1:0] cmdbuf_size; // @[Reg.scala 27:20]
reg [7:0] cmdbuf_wstrb; // @[Reg.scala 27:20]
wire [7:0] master_wstrb = _T_74[7:0]; // @[ahb_to_axi4.scala 96:31]
wire _T_178 = cmdbuf_wr_en & io_bus_clk_en; // @[ahb_to_axi4.scala 150:59]
wire _T_179 = cmdbuf_wr_en & io_bus_clk_en; // @[ahb_to_axi4.scala 150:59]
reg [31:0] cmdbuf_addr; // @[Reg.scala 27:20]
reg [63:0] cmdbuf_wdata; // @[Reg.scala 27:20]
wire [1:0] cmdbuf_size = _T_173[1:0]; // @[ahb_to_axi4.scala 147:31]
rvclkhdr rvclkhdr ( // @[lib.scala 399:23]
.io_clk(rvclkhdr_io_clk),
.io_en(rvclkhdr_io_en)
@ -327,7 +326,7 @@ initial begin
_RAND_10 = {1{`RANDOM}};
ahb_hwrite_q = _RAND_10[0:0];
_RAND_11 = {1{`RANDOM}};
_T_173 = _RAND_11[2:0];
cmdbuf_size = _RAND_11[1:0];
_RAND_12 = {1{`RANDOM}};
cmdbuf_wstrb = _RAND_12[7:0];
_RAND_13 = {1{`RANDOM}};
@ -369,7 +368,7 @@ initial begin
ahb_hwrite_q = 1'h0;
end
if (reset) begin
_T_173 = 3'h0;
cmdbuf_size = 2'h0;
end
if (reset) begin
cmdbuf_wstrb = 8'h0;
@ -495,9 +494,9 @@ end // initial
end
always @(posedge clock or posedge reset) begin
if (reset) begin
_T_173 <= 3'h0;
cmdbuf_size <= 2'h0;
end else if (_T_169) begin
_T_173 <= ahb_hsize_q;
cmdbuf_size <= ahb_hsize_q[1:0];
end
end
always @(posedge clock or posedge reset) begin
@ -510,14 +509,14 @@ end // initial
always @(posedge clock or posedge reset) begin
if (reset) begin
cmdbuf_addr <= 32'h0;
end else if (_T_178) begin
end else if (_T_179) begin
cmdbuf_addr <= ahb_haddr_q;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
cmdbuf_wdata <= 64'h0;
end else if (_T_178) begin
end else if (_T_179) begin
cmdbuf_wdata <= io_ahb_sig_out_hwdata;
end
end

2
src/main/scala/lib/ahb_to_axi4.scala
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@ -144,7 +144,7 @@ class ahb_to_axi4(TAG : Int) extends Module with lib with RequireAsyncReset {
cmdbuf_vld := rvdffsc_fpga("b1".U,cmdbuf_wr_en.asBool(),cmdbuf_rst,bus_clk,io.bus_clk_en,clock)
//dffs
cmdbuf_write := rvdffs_fpga(ahb_hwrite_q, cmdbuf_wr_en.asBool(),bus_clk,io.bus_clk_en,clock)
cmdbuf_size := rvdffs_fpga(ahb_hsize_q, cmdbuf_wr_en.asBool(),bus_clk,io.bus_clk_en,clock)
cmdbuf_size := rvdffs_fpga(ahb_hsize_q(1,0), cmdbuf_wr_en.asBool(),bus_clk,io.bus_clk_en,clock)
cmdbuf_wstrb := rvdffs_fpga(master_wstrb, cmdbuf_wr_en.asBool(),bus_clk,io.bus_clk_en,clock)
//rvdffe
cmdbuf_addr := rvdffe(ahb_haddr_q, cmdbuf_wr_en.asBool()& io.bus_clk_en,clock,io.scan_mode)

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target/scala-2.12/classes/lib/ahb_to_axi4.class
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