From 95f191bcb9f036a655472f02923040b64d23e570 Mon Sep 17 00:00:00 2001 From: waleed-lm Date: Tue, 15 Dec 2020 12:01:57 +0500 Subject: [PATCH] Chisel Freeze --- axi4_to_ahb.fir | 1556 +- axi4_to_ahb.v | 452 +- quasar_wrapper.fir | 12383 ++++++++-------- quasar_wrapper.v | 8954 +++++++---- src/main/scala/lib/ahb_to_axi4.scala | 5 +- src/main/scala/lib/axi4_to_ahb.scala | 19 +- src/main/scala/lib/param.scala | 2 +- src/main/scala/quasar.scala | 17 +- target/scala-2.12/classes/QUASAR$.class | Bin 0 -> 3815 bytes .../classes/QUASAR$delayedInit$body.class | Bin 0 -> 697 bytes target/scala-2.12/classes/QUASAR.class | Bin 0 -> 758 bytes target/scala-2.12/classes/lib/Config.class | Bin 684 -> 0 bytes .../classes/lib/ahb_to_axi4$$anon$1.class | Bin 1925 -> 1965 bytes .../scala-2.12/classes/lib/ahb_to_axi4.class | Bin 131123 -> 131021 bytes target/scala-2.12/classes/lib/axi4$.class | Bin 0 -> 3862 bytes .../classes/lib/axi4$delayedInit$body.class | Bin 0 -> 714 bytes target/scala-2.12/classes/lib/axi4.class | Bin 0 -> 760 bytes .../scala-2.12/classes/lib/axi4_to_ahb$.class | Bin 0 -> 496 bytes .../scala-2.12/classes/lib/axi4_to_ahb.class | Bin 107336 -> 107553 bytes .../classes/lib/axi4_to_ahb_IO.class | Bin 2631 -> 2533 bytes target/scala-2.12/classes/lib/param.class | Bin 23339 -> 23339 bytes target/scala-2.12/classes/quasar.class | Bin 154782 -> 156561 bytes 22 files changed, 12949 insertions(+), 10439 deletions(-) create mode 100644 target/scala-2.12/classes/QUASAR$.class create mode 100644 target/scala-2.12/classes/QUASAR$delayedInit$body.class create mode 100644 target/scala-2.12/classes/QUASAR.class delete mode 100644 target/scala-2.12/classes/lib/Config.class create mode 100644 target/scala-2.12/classes/lib/axi4$.class create mode 100644 target/scala-2.12/classes/lib/axi4$delayedInit$body.class create mode 100644 target/scala-2.12/classes/lib/axi4.class create mode 100644 target/scala-2.12/classes/lib/axi4_to_ahb$.class diff --git a/axi4_to_ahb.fir b/axi4_to_ahb.fir index 6f56dc26..0ecf6351 100644 --- a/axi4_to_ahb.fir +++ b/axi4_to_ahb.fir @@ -243,36 +243,36 @@ circuit axi4_to_ahb : module axi4_to_ahb : input clock : Clock input reset : AsyncReset - output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ahb : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}} + output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ahb : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}} wire buf_rst : UInt<1> buf_rst <= UInt<1>("h00") - buf_rst <= UInt<1>("h00") @[axi4_to_ahb.scala 28:11] - io.ahb.out.htrans <= UInt<1>("h00") @[axi4_to_ahb.scala 29:21] + buf_rst <= UInt<1>("h00") @[axi4_to_ahb.scala 21:11] + io.ahb.out.htrans <= UInt<1>("h00") @[axi4_to_ahb.scala 22:21] wire buf_state_en : UInt<1> buf_state_en <= UInt<1>("h00") - wire ahbm_clk : Clock @[axi4_to_ahb.scala 31:22] - wire ahbm_addr_clk : Clock @[axi4_to_ahb.scala 32:27] - wire ahbm_data_clk : Clock @[axi4_to_ahb.scala 33:27] + wire ahbm_clk : Clock @[axi4_to_ahb.scala 24:22] + wire ahbm_addr_clk : Clock @[axi4_to_ahb.scala 25:27] + wire ahbm_data_clk : Clock @[axi4_to_ahb.scala 26:27] wire buf_state : UInt<3> buf_state <= UInt<3>("h00") wire buf_nxtstate : UInt<3> buf_nxtstate <= UInt<3>("h00") - node _T = bits(buf_state_en, 0, 0) @[axi4_to_ahb.scala 37:70] - node _T_1 = mux(_T, buf_nxtstate, buf_state) @[axi4_to_ahb.scala 37:50] - node _T_2 = eq(buf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 37:108] + node _T = bits(buf_state_en, 0, 0) @[axi4_to_ahb.scala 30:70] + node _T_1 = mux(_T, buf_nxtstate, buf_state) @[axi4_to_ahb.scala 30:50] + node _T_2 = eq(buf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 30:108] node _T_3 = bits(_T_2, 0, 0) @[Bitwise.scala 72:15] node _T_4 = mux(_T_3, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_5 = and(_T_1, _T_4) @[axi4_to_ahb.scala 37:98] - reg _T_6 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 37:45] - _T_6 <= _T_5 @[axi4_to_ahb.scala 37:45] - buf_state <= _T_6 @[axi4_to_ahb.scala 37:13] + node _T_5 = and(_T_1, _T_4) @[axi4_to_ahb.scala 30:98] + reg _T_6 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 30:45] + _T_6 <= _T_5 @[axi4_to_ahb.scala 30:45] + buf_state <= _T_6 @[axi4_to_ahb.scala 30:13] wire slave_valid : UInt<1> slave_valid <= UInt<1>("h00") wire slave_ready : UInt<1> slave_ready <= UInt<1>("h00") - wire slave_tag : UInt<1> - slave_tag <= UInt<1>("h00") + wire slave_tag : UInt<3> + slave_tag <= UInt<3>("h00") wire slave_rdata : UInt<64> slave_rdata <= UInt<64>("h00") wire slave_opc : UInt<4> @@ -289,8 +289,8 @@ circuit axi4_to_ahb : wrbuf_vld <= UInt<1>("h00") wire wrbuf_data_vld : UInt<1> wrbuf_data_vld <= UInt<1>("h00") - wire wrbuf_tag : UInt<1> - wrbuf_tag <= UInt<1>("h00") + wire wrbuf_tag : UInt<3> + wrbuf_tag <= UInt<3>("h00") wire wrbuf_size : UInt<3> wrbuf_size <= UInt<3>("h00") wire wrbuf_addr : UInt<32> @@ -301,14 +301,14 @@ circuit axi4_to_ahb : wrbuf_byteen <= UInt<8>("h00") wire bus_write_clk_en : UInt<1> bus_write_clk_en <= UInt<1>("h00") - wire bus_clk : Clock @[axi4_to_ahb.scala 57:21] - wire bus_write_clk : Clock @[axi4_to_ahb.scala 58:27] + wire bus_clk : Clock @[axi4_to_ahb.scala 50:21] + wire bus_write_clk : Clock @[axi4_to_ahb.scala 51:27] wire master_valid : UInt<1> master_valid <= UInt<1>("h00") wire master_ready : UInt<1> master_ready <= UInt<1>("h00") - wire master_tag : UInt<1> - master_tag <= UInt<1>("h00") + wire master_tag : UInt<3> + master_tag <= UInt<3>("h00") wire master_addr : UInt<32> master_addr <= UInt<32>("h00") wire master_wdata : UInt<64> @@ -331,10 +331,10 @@ circuit axi4_to_ahb : buf_aligned <= UInt<1>("h00") wire buf_data : UInt<64> buf_data <= UInt<64>("h00") - wire buf_tag : UInt<1> - buf_tag <= UInt<1>("h00") - wire buf_tag_in : UInt<1> - buf_tag_in <= UInt<1>("h00") + wire buf_tag : UInt<3> + buf_tag <= UInt<3>("h00") + wire buf_tag_in : UInt<3> + buf_tag_in <= UInt<3>("h00") wire buf_addr_in : UInt<32> buf_addr_in <= UInt<32>("h00") wire buf_byteen_in : UInt<8> @@ -389,8 +389,8 @@ circuit axi4_to_ahb : slvbuf_write <= UInt<1>("h00") wire slvbuf_error : UInt<1> slvbuf_error <= UInt<1>("h00") - wire slvbuf_tag : UInt<1> - slvbuf_tag <= UInt<1>("h00") + wire slvbuf_tag : UInt<3> + slvbuf_tag <= UInt<3>("h00") wire slvbuf_error_in : UInt<1> slvbuf_error_in <= UInt<1>("h00") wire slvbuf_wr_en : UInt<1> @@ -411,125 +411,125 @@ circuit axi4_to_ahb : ahbm_addr_clken <= UInt<1>("h00") wire ahbm_data_clken : UInt<1> ahbm_data_clken <= UInt<1>("h00") - wire buf_clk : Clock @[axi4_to_ahb.scala 125:21] - node _T_7 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 146:27] - wr_cmd_vld <= _T_7 @[axi4_to_ahb.scala 146:14] - node _T_8 = or(wr_cmd_vld, io.axi.ar.valid) @[axi4_to_ahb.scala 147:30] - master_valid <= _T_8 @[axi4_to_ahb.scala 147:16] - node _T_9 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 148:38] - node _T_10 = bits(wrbuf_tag, 0, 0) @[axi4_to_ahb.scala 148:51] - node _T_11 = bits(io.axi.ar.bits.id, 0, 0) @[axi4_to_ahb.scala 148:82] - node _T_12 = mux(_T_9, _T_10, _T_11) @[axi4_to_ahb.scala 148:20] - master_tag <= _T_12 @[axi4_to_ahb.scala 148:14] - node _T_13 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 149:38] - node _T_14 = mux(_T_13, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 149:20] - master_opc <= _T_14 @[axi4_to_ahb.scala 149:14] - node _T_15 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 150:39] - node _T_16 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 150:53] - node _T_17 = bits(io.axi.ar.bits.addr, 31, 0) @[axi4_to_ahb.scala 150:81] - node _T_18 = mux(_T_15, _T_16, _T_17) @[axi4_to_ahb.scala 150:21] - master_addr <= _T_18 @[axi4_to_ahb.scala 150:15] - node _T_19 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 151:39] - node _T_20 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 151:53] - node _T_21 = bits(io.axi.ar.bits.size, 2, 0) @[axi4_to_ahb.scala 151:80] - node _T_22 = mux(_T_19, _T_20, _T_21) @[axi4_to_ahb.scala 151:21] - master_size <= _T_22 @[axi4_to_ahb.scala 151:15] - node _T_23 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 152:32] - master_byteen <= _T_23 @[axi4_to_ahb.scala 152:17] - node _T_24 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 153:29] - master_wdata <= _T_24 @[axi4_to_ahb.scala 153:16] - node _T_25 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 156:33] - node _T_26 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 156:58] - node _T_27 = and(_T_25, _T_26) @[axi4_to_ahb.scala 156:47] - io.axi.b.valid <= _T_27 @[axi4_to_ahb.scala 156:18] - node _T_28 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 157:38] - node _T_29 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 157:65] - node _T_30 = mux(_T_29, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 157:55] - node _T_31 = mux(_T_28, UInt<2>("h02"), _T_30) @[axi4_to_ahb.scala 157:28] - io.axi.b.bits.resp <= _T_31 @[axi4_to_ahb.scala 157:22] - node _T_32 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 158:32] - io.axi.b.bits.id <= _T_32 @[axi4_to_ahb.scala 158:20] - node _T_33 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 160:33] - node _T_34 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 160:59] - node _T_35 = eq(_T_34, UInt<1>("h00")) @[axi4_to_ahb.scala 160:66] - node _T_36 = and(_T_33, _T_35) @[axi4_to_ahb.scala 160:47] - io.axi.r.valid <= _T_36 @[axi4_to_ahb.scala 160:18] - node _T_37 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 161:38] - node _T_38 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 161:65] - node _T_39 = mux(_T_38, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 161:55] - node _T_40 = mux(_T_37, UInt<2>("h02"), _T_39) @[axi4_to_ahb.scala 161:28] - io.axi.r.bits.resp <= _T_40 @[axi4_to_ahb.scala 161:22] - node _T_41 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 162:32] - io.axi.r.bits.id <= _T_41 @[axi4_to_ahb.scala 162:20] - node _T_42 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 163:36] - io.axi.r.bits.data <= _T_42 @[axi4_to_ahb.scala 163:22] - node _T_43 = and(io.axi.b.ready, io.axi.r.ready) @[axi4_to_ahb.scala 164:33] - slave_ready <= _T_43 @[axi4_to_ahb.scala 164:15] - node _T_44 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 167:57] - node _T_45 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 167:94] - node _T_46 = or(_T_44, _T_45) @[axi4_to_ahb.scala 167:76] - node _T_47 = and(io.bus_clk_en, _T_46) @[axi4_to_ahb.scala 167:37] - bus_write_clk_en <= _T_47 @[axi4_to_ahb.scala 167:20] + wire buf_clk : Clock @[axi4_to_ahb.scala 118:21] + node _T_7 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 139:27] + wr_cmd_vld <= _T_7 @[axi4_to_ahb.scala 139:14] + node _T_8 = or(wr_cmd_vld, io.axi.ar.valid) @[axi4_to_ahb.scala 140:30] + master_valid <= _T_8 @[axi4_to_ahb.scala 140:16] + node _T_9 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 141:38] + node _T_10 = bits(wrbuf_tag, 2, 0) @[axi4_to_ahb.scala 141:51] + node _T_11 = bits(io.axi.ar.bits.id, 2, 0) @[axi4_to_ahb.scala 141:82] + node _T_12 = mux(_T_9, _T_10, _T_11) @[axi4_to_ahb.scala 141:20] + master_tag <= _T_12 @[axi4_to_ahb.scala 141:14] + node _T_13 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 142:38] + node _T_14 = mux(_T_13, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 142:20] + master_opc <= _T_14 @[axi4_to_ahb.scala 142:14] + node _T_15 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 143:39] + node _T_16 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 143:53] + node _T_17 = bits(io.axi.ar.bits.addr, 31, 0) @[axi4_to_ahb.scala 143:81] + node _T_18 = mux(_T_15, _T_16, _T_17) @[axi4_to_ahb.scala 143:21] + master_addr <= _T_18 @[axi4_to_ahb.scala 143:15] + node _T_19 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 144:39] + node _T_20 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 144:53] + node _T_21 = bits(io.axi.ar.bits.size, 2, 0) @[axi4_to_ahb.scala 144:80] + node _T_22 = mux(_T_19, _T_20, _T_21) @[axi4_to_ahb.scala 144:21] + master_size <= _T_22 @[axi4_to_ahb.scala 144:15] + node _T_23 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 145:32] + master_byteen <= _T_23 @[axi4_to_ahb.scala 145:17] + node _T_24 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 146:29] + master_wdata <= _T_24 @[axi4_to_ahb.scala 146:16] + node _T_25 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 149:33] + node _T_26 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 149:58] + node _T_27 = and(_T_25, _T_26) @[axi4_to_ahb.scala 149:47] + io.axi.b.valid <= _T_27 @[axi4_to_ahb.scala 149:18] + node _T_28 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 150:38] + node _T_29 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 150:65] + node _T_30 = mux(_T_29, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 150:55] + node _T_31 = mux(_T_28, UInt<2>("h02"), _T_30) @[axi4_to_ahb.scala 150:28] + io.axi.b.bits.resp <= _T_31 @[axi4_to_ahb.scala 150:22] + node _T_32 = bits(slave_tag, 2, 0) @[axi4_to_ahb.scala 151:32] + io.axi.b.bits.id <= _T_32 @[axi4_to_ahb.scala 151:20] + node _T_33 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 153:33] + node _T_34 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 153:59] + node _T_35 = eq(_T_34, UInt<1>("h00")) @[axi4_to_ahb.scala 153:66] + node _T_36 = and(_T_33, _T_35) @[axi4_to_ahb.scala 153:47] + io.axi.r.valid <= _T_36 @[axi4_to_ahb.scala 153:18] + node _T_37 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 154:38] + node _T_38 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 154:65] + node _T_39 = mux(_T_38, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 154:55] + node _T_40 = mux(_T_37, UInt<2>("h02"), _T_39) @[axi4_to_ahb.scala 154:28] + io.axi.r.bits.resp <= _T_40 @[axi4_to_ahb.scala 154:22] + node _T_41 = bits(slave_tag, 2, 0) @[axi4_to_ahb.scala 155:32] + io.axi.r.bits.id <= _T_41 @[axi4_to_ahb.scala 155:20] + node _T_42 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 156:36] + io.axi.r.bits.data <= _T_42 @[axi4_to_ahb.scala 156:22] + node _T_43 = and(io.axi.b.ready, io.axi.r.ready) @[axi4_to_ahb.scala 157:33] + slave_ready <= _T_43 @[axi4_to_ahb.scala 157:15] + node _T_44 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 160:57] + node _T_45 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 160:94] + node _T_46 = or(_T_44, _T_45) @[axi4_to_ahb.scala 160:76] + node _T_47 = and(io.bus_clk_en, _T_46) @[axi4_to_ahb.scala 160:37] + bus_write_clk_en <= _T_47 @[axi4_to_ahb.scala 160:20] inst rvclkhdr of rvclkhdr @[lib.scala 343:22] rvclkhdr.clock <= clock rvclkhdr.reset <= reset rvclkhdr.io.clk <= clock @[lib.scala 344:17] rvclkhdr.io.en <= io.bus_clk_en @[lib.scala 345:16] rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - bus_clk <= rvclkhdr.io.l1clk @[axi4_to_ahb.scala 169:11] - node _T_48 = bits(bus_write_clk_en, 0, 0) @[axi4_to_ahb.scala 170:59] + bus_clk <= rvclkhdr.io.l1clk @[axi4_to_ahb.scala 162:11] + node _T_48 = bits(bus_write_clk_en, 0, 0) @[axi4_to_ahb.scala 163:59] inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 343:22] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] rvclkhdr_1.io.en <= _T_48 @[lib.scala 345:16] rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - bus_write_clk <= rvclkhdr_1.io.l1clk @[axi4_to_ahb.scala 170:17] + bus_write_clk <= rvclkhdr_1.io.l1clk @[axi4_to_ahb.scala 163:17] node _T_49 = eq(UInt<3>("h00"), buf_state) @[Conditional.scala 37:30] when _T_49 : @[Conditional.scala 40:58] - master_ready <= UInt<1>("h01") @[axi4_to_ahb.scala 174:20] - node _T_50 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 175:34] - node _T_51 = eq(_T_50, UInt<1>("h01")) @[axi4_to_ahb.scala 175:41] - buf_write_in <= _T_51 @[axi4_to_ahb.scala 175:20] - node _T_52 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 176:46] - node _T_53 = mux(_T_52, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 176:26] - buf_nxtstate <= _T_53 @[axi4_to_ahb.scala 176:20] - node _T_54 = and(master_valid, UInt<1>("h01")) @[axi4_to_ahb.scala 177:36] - buf_state_en <= _T_54 @[axi4_to_ahb.scala 177:20] - buf_wr_en <= buf_state_en @[axi4_to_ahb.scala 178:17] - node _T_55 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 179:54] - node _T_56 = and(buf_state_en, _T_55) @[axi4_to_ahb.scala 179:38] - buf_data_wr_en <= _T_56 @[axi4_to_ahb.scala 179:22] - buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 180:27] - node _T_57 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 182:50] - node _T_58 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 182:94] - node _T_59 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 142:52] - node _T_60 = tail(_T_59, 1) @[axi4_to_ahb.scala 142:52] - node _T_61 = mux(UInt<1>("h00"), _T_60, UInt<3>("h00")) @[axi4_to_ahb.scala 142:24] - node _T_62 = bits(_T_58, 0, 0) @[axi4_to_ahb.scala 143:44] - node _T_63 = geq(UInt<1>("h00"), _T_61) @[axi4_to_ahb.scala 143:62] - node _T_64 = and(_T_62, _T_63) @[axi4_to_ahb.scala 143:48] - node _T_65 = bits(_T_58, 1, 1) @[axi4_to_ahb.scala 143:44] - node _T_66 = geq(UInt<1>("h01"), _T_61) @[axi4_to_ahb.scala 143:62] - node _T_67 = and(_T_65, _T_66) @[axi4_to_ahb.scala 143:48] - node _T_68 = bits(_T_58, 2, 2) @[axi4_to_ahb.scala 143:44] - node _T_69 = geq(UInt<2>("h02"), _T_61) @[axi4_to_ahb.scala 143:62] - node _T_70 = and(_T_68, _T_69) @[axi4_to_ahb.scala 143:48] - node _T_71 = bits(_T_58, 3, 3) @[axi4_to_ahb.scala 143:44] - node _T_72 = geq(UInt<2>("h03"), _T_61) @[axi4_to_ahb.scala 143:62] - node _T_73 = and(_T_71, _T_72) @[axi4_to_ahb.scala 143:48] - node _T_74 = bits(_T_58, 4, 4) @[axi4_to_ahb.scala 143:44] - node _T_75 = geq(UInt<3>("h04"), _T_61) @[axi4_to_ahb.scala 143:62] - node _T_76 = and(_T_74, _T_75) @[axi4_to_ahb.scala 143:48] - node _T_77 = bits(_T_58, 5, 5) @[axi4_to_ahb.scala 143:44] - node _T_78 = geq(UInt<3>("h05"), _T_61) @[axi4_to_ahb.scala 143:62] - node _T_79 = and(_T_77, _T_78) @[axi4_to_ahb.scala 143:48] - node _T_80 = bits(_T_58, 6, 6) @[axi4_to_ahb.scala 143:44] - node _T_81 = geq(UInt<3>("h06"), _T_61) @[axi4_to_ahb.scala 143:62] - node _T_82 = and(_T_80, _T_81) @[axi4_to_ahb.scala 143:48] - node _T_83 = bits(_T_58, 7, 7) @[axi4_to_ahb.scala 143:44] - node _T_84 = geq(UInt<3>("h07"), _T_61) @[axi4_to_ahb.scala 143:62] - node _T_85 = and(_T_83, _T_84) @[axi4_to_ahb.scala 143:48] + master_ready <= UInt<1>("h01") @[axi4_to_ahb.scala 167:20] + node _T_50 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 168:34] + node _T_51 = eq(_T_50, UInt<1>("h01")) @[axi4_to_ahb.scala 168:41] + buf_write_in <= _T_51 @[axi4_to_ahb.scala 168:20] + node _T_52 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 169:46] + node _T_53 = mux(_T_52, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 169:26] + buf_nxtstate <= _T_53 @[axi4_to_ahb.scala 169:20] + node _T_54 = and(master_valid, UInt<1>("h01")) @[axi4_to_ahb.scala 170:36] + buf_state_en <= _T_54 @[axi4_to_ahb.scala 170:20] + buf_wr_en <= buf_state_en @[axi4_to_ahb.scala 171:17] + node _T_55 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 172:54] + node _T_56 = and(buf_state_en, _T_55) @[axi4_to_ahb.scala 172:38] + buf_data_wr_en <= _T_56 @[axi4_to_ahb.scala 172:22] + buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 173:27] + node _T_57 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 175:50] + node _T_58 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 175:94] + node _T_59 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] + node _T_60 = tail(_T_59, 1) @[axi4_to_ahb.scala 135:52] + node _T_61 = mux(UInt<1>("h00"), _T_60, UInt<3>("h00")) @[axi4_to_ahb.scala 135:24] + node _T_62 = bits(_T_58, 0, 0) @[axi4_to_ahb.scala 136:44] + node _T_63 = geq(UInt<1>("h00"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_64 = and(_T_62, _T_63) @[axi4_to_ahb.scala 136:48] + node _T_65 = bits(_T_58, 1, 1) @[axi4_to_ahb.scala 136:44] + node _T_66 = geq(UInt<1>("h01"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_67 = and(_T_65, _T_66) @[axi4_to_ahb.scala 136:48] + node _T_68 = bits(_T_58, 2, 2) @[axi4_to_ahb.scala 136:44] + node _T_69 = geq(UInt<2>("h02"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_70 = and(_T_68, _T_69) @[axi4_to_ahb.scala 136:48] + node _T_71 = bits(_T_58, 3, 3) @[axi4_to_ahb.scala 136:44] + node _T_72 = geq(UInt<2>("h03"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_73 = and(_T_71, _T_72) @[axi4_to_ahb.scala 136:48] + node _T_74 = bits(_T_58, 4, 4) @[axi4_to_ahb.scala 136:44] + node _T_75 = geq(UInt<3>("h04"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_76 = and(_T_74, _T_75) @[axi4_to_ahb.scala 136:48] + node _T_77 = bits(_T_58, 5, 5) @[axi4_to_ahb.scala 136:44] + node _T_78 = geq(UInt<3>("h05"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_79 = and(_T_77, _T_78) @[axi4_to_ahb.scala 136:48] + node _T_80 = bits(_T_58, 6, 6) @[axi4_to_ahb.scala 136:44] + node _T_81 = geq(UInt<3>("h06"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_82 = and(_T_80, _T_81) @[axi4_to_ahb.scala 136:48] + node _T_83 = bits(_T_58, 7, 7) @[axi4_to_ahb.scala 136:44] + node _T_84 = geq(UInt<3>("h07"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_85 = and(_T_83, _T_84) @[axi4_to_ahb.scala 136:48] node _T_86 = mux(_T_85, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_87 = mux(_T_82, UInt<3>("h06"), _T_86) @[Mux.scala 98:16] node _T_88 = mux(_T_79, UInt<3>("h05"), _T_87) @[Mux.scala 98:16] @@ -538,193 +538,193 @@ circuit axi4_to_ahb : node _T_91 = mux(_T_70, UInt<2>("h02"), _T_90) @[Mux.scala 98:16] node _T_92 = mux(_T_67, UInt<1>("h01"), _T_91) @[Mux.scala 98:16] node _T_93 = mux(_T_64, UInt<1>("h00"), _T_92) @[Mux.scala 98:16] - node _T_94 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 182:124] - node _T_95 = mux(_T_57, _T_93, _T_94) @[axi4_to_ahb.scala 182:30] - buf_cmd_byte_ptr <= _T_95 @[axi4_to_ahb.scala 182:24] - bypass_en <= buf_state_en @[axi4_to_ahb.scala 183:17] - node _T_96 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 184:51] - node _T_97 = and(bypass_en, _T_96) @[axi4_to_ahb.scala 184:35] - rd_bypass_idle <= _T_97 @[axi4_to_ahb.scala 184:22] + node _T_94 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 175:124] + node _T_95 = mux(_T_57, _T_93, _T_94) @[axi4_to_ahb.scala 175:30] + buf_cmd_byte_ptr <= _T_95 @[axi4_to_ahb.scala 175:24] + bypass_en <= buf_state_en @[axi4_to_ahb.scala 176:17] + node _T_96 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 177:51] + node _T_97 = and(bypass_en, _T_96) @[axi4_to_ahb.scala 177:35] + rd_bypass_idle <= _T_97 @[axi4_to_ahb.scala 177:22] node _T_98 = bits(bypass_en, 0, 0) @[Bitwise.scala 72:15] node _T_99 = mux(_T_98, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_100 = and(_T_99, UInt<2>("h02")) @[axi4_to_ahb.scala 185:49] - io.ahb.out.htrans <= _T_100 @[axi4_to_ahb.scala 185:25] + node _T_100 = and(_T_99, UInt<2>("h02")) @[axi4_to_ahb.scala 178:49] + io.ahb.out.htrans <= _T_100 @[axi4_to_ahb.scala 178:25] skip @[Conditional.scala 40:58] else : @[Conditional.scala 39:67] node _T_101 = eq(UInt<3>("h01"), buf_state) @[Conditional.scala 37:30] when _T_101 : @[Conditional.scala 39:67] - node _T_102 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 189:54] - node _T_103 = eq(_T_102, UInt<1>("h00")) @[axi4_to_ahb.scala 189:61] - node _T_104 = and(master_valid, _T_103) @[axi4_to_ahb.scala 189:41] - node _T_105 = bits(_T_104, 0, 0) @[axi4_to_ahb.scala 189:82] - node _T_106 = mux(_T_105, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 189:26] - buf_nxtstate <= _T_106 @[axi4_to_ahb.scala 189:20] - node _T_107 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 190:51] - node _T_108 = neq(_T_107, UInt<1>("h00")) @[axi4_to_ahb.scala 190:58] - node _T_109 = and(ahb_hready_q, _T_108) @[axi4_to_ahb.scala 190:36] - node _T_110 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 190:72] - node _T_111 = and(_T_109, _T_110) @[axi4_to_ahb.scala 190:70] - buf_state_en <= _T_111 @[axi4_to_ahb.scala 190:20] - node _T_112 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 191:34] - node _T_113 = and(buf_state_en, _T_112) @[axi4_to_ahb.scala 191:32] - cmd_done <= _T_113 @[axi4_to_ahb.scala 191:16] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 192:20] - node _T_114 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 193:52] - node _T_115 = neq(_T_114, UInt<1>("h00")) @[axi4_to_ahb.scala 193:59] - node _T_116 = and(ahb_hready_q, _T_115) @[axi4_to_ahb.scala 193:37] - node _T_117 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 193:73] - node _T_118 = and(_T_116, _T_117) @[axi4_to_ahb.scala 193:71] - node _T_119 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 193:122] - node _T_120 = eq(_T_119, UInt<1>("h00")) @[axi4_to_ahb.scala 193:129] - node _T_121 = and(master_valid, _T_120) @[axi4_to_ahb.scala 193:109] - node _T_122 = bits(_T_121, 0, 0) @[axi4_to_ahb.scala 193:150] - node _T_123 = mux(_T_122, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 193:94] - node _T_124 = eq(_T_123, UInt<3>("h06")) @[axi4_to_ahb.scala 193:174] - node _T_125 = and(_T_118, _T_124) @[axi4_to_ahb.scala 193:88] - master_ready <= _T_125 @[axi4_to_ahb.scala 193:20] - buf_wr_en <= master_ready @[axi4_to_ahb.scala 194:17] - node _T_126 = and(master_ready, master_valid) @[axi4_to_ahb.scala 195:33] - bypass_en <= _T_126 @[axi4_to_ahb.scala 195:17] - node _T_127 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 196:47] - node _T_128 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 196:62] - node _T_129 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 196:78] - node _T_130 = mux(_T_127, _T_128, _T_129) @[axi4_to_ahb.scala 196:30] - buf_cmd_byte_ptr <= _T_130 @[axi4_to_ahb.scala 196:24] - node _T_131 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 197:48] - node _T_132 = or(_T_131, bypass_en) @[axi4_to_ahb.scala 197:62] + node _T_102 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 182:54] + node _T_103 = eq(_T_102, UInt<1>("h00")) @[axi4_to_ahb.scala 182:61] + node _T_104 = and(master_valid, _T_103) @[axi4_to_ahb.scala 182:41] + node _T_105 = bits(_T_104, 0, 0) @[axi4_to_ahb.scala 182:82] + node _T_106 = mux(_T_105, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 182:26] + buf_nxtstate <= _T_106 @[axi4_to_ahb.scala 182:20] + node _T_107 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 183:51] + node _T_108 = neq(_T_107, UInt<1>("h00")) @[axi4_to_ahb.scala 183:58] + node _T_109 = and(ahb_hready_q, _T_108) @[axi4_to_ahb.scala 183:36] + node _T_110 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 183:72] + node _T_111 = and(_T_109, _T_110) @[axi4_to_ahb.scala 183:70] + buf_state_en <= _T_111 @[axi4_to_ahb.scala 183:20] + node _T_112 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 184:34] + node _T_113 = and(buf_state_en, _T_112) @[axi4_to_ahb.scala 184:32] + cmd_done <= _T_113 @[axi4_to_ahb.scala 184:16] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 185:20] + node _T_114 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 186:52] + node _T_115 = neq(_T_114, UInt<1>("h00")) @[axi4_to_ahb.scala 186:59] + node _T_116 = and(ahb_hready_q, _T_115) @[axi4_to_ahb.scala 186:37] + node _T_117 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 186:73] + node _T_118 = and(_T_116, _T_117) @[axi4_to_ahb.scala 186:71] + node _T_119 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 186:122] + node _T_120 = eq(_T_119, UInt<1>("h00")) @[axi4_to_ahb.scala 186:129] + node _T_121 = and(master_valid, _T_120) @[axi4_to_ahb.scala 186:109] + node _T_122 = bits(_T_121, 0, 0) @[axi4_to_ahb.scala 186:150] + node _T_123 = mux(_T_122, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 186:94] + node _T_124 = eq(_T_123, UInt<3>("h06")) @[axi4_to_ahb.scala 186:174] + node _T_125 = and(_T_118, _T_124) @[axi4_to_ahb.scala 186:88] + master_ready <= _T_125 @[axi4_to_ahb.scala 186:20] + buf_wr_en <= master_ready @[axi4_to_ahb.scala 187:17] + node _T_126 = and(master_ready, master_valid) @[axi4_to_ahb.scala 188:33] + bypass_en <= _T_126 @[axi4_to_ahb.scala 188:17] + node _T_127 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 189:47] + node _T_128 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 189:62] + node _T_129 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 189:78] + node _T_130 = mux(_T_127, _T_128, _T_129) @[axi4_to_ahb.scala 189:30] + buf_cmd_byte_ptr <= _T_130 @[axi4_to_ahb.scala 189:24] + node _T_131 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 190:48] + node _T_132 = or(_T_131, bypass_en) @[axi4_to_ahb.scala 190:62] node _T_133 = bits(_T_132, 0, 0) @[Bitwise.scala 72:15] node _T_134 = mux(_T_133, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_135 = and(UInt<2>("h02"), _T_134) @[axi4_to_ahb.scala 197:36] - io.ahb.out.htrans <= _T_135 @[axi4_to_ahb.scala 197:25] + node _T_135 = and(UInt<2>("h02"), _T_134) @[axi4_to_ahb.scala 190:36] + io.ahb.out.htrans <= _T_135 @[axi4_to_ahb.scala 190:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_136 = eq(UInt<3>("h06"), buf_state) @[Conditional.scala 37:30] when _T_136 : @[Conditional.scala 39:67] - node _T_137 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 201:39] - node _T_138 = and(ahb_hready_q, _T_137) @[axi4_to_ahb.scala 201:37] - node _T_139 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 201:82] - node _T_140 = eq(_T_139, UInt<1>("h01")) @[axi4_to_ahb.scala 201:89] - node _T_141 = and(master_valid, _T_140) @[axi4_to_ahb.scala 201:70] - node _T_142 = not(_T_141) @[axi4_to_ahb.scala 201:55] - node _T_143 = and(_T_138, _T_142) @[axi4_to_ahb.scala 201:53] - master_ready <= _T_143 @[axi4_to_ahb.scala 201:20] - node _T_144 = and(master_valid, master_ready) @[axi4_to_ahb.scala 202:34] - node _T_145 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 202:62] - node _T_146 = eq(_T_145, UInt<1>("h00")) @[axi4_to_ahb.scala 202:69] - node _T_147 = and(_T_144, _T_146) @[axi4_to_ahb.scala 202:49] - buf_wr_en <= _T_147 @[axi4_to_ahb.scala 202:17] - node _T_148 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 203:45] - node _T_149 = and(master_valid, master_ready) @[axi4_to_ahb.scala 203:82] - node _T_150 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 203:110] - node _T_151 = eq(_T_150, UInt<1>("h00")) @[axi4_to_ahb.scala 203:117] - node _T_152 = and(_T_149, _T_151) @[axi4_to_ahb.scala 203:97] - node _T_153 = bits(_T_152, 0, 0) @[axi4_to_ahb.scala 203:138] - node _T_154 = mux(_T_153, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 203:67] - node _T_155 = mux(_T_148, UInt<3>("h07"), _T_154) @[axi4_to_ahb.scala 203:26] - buf_nxtstate <= _T_155 @[axi4_to_ahb.scala 203:20] - node _T_156 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 204:37] - buf_state_en <= _T_156 @[axi4_to_ahb.scala 204:20] - buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 205:22] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 206:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 207:23] - node _T_157 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 208:41] - node _T_158 = and(buf_state_en, _T_157) @[axi4_to_ahb.scala 208:39] - slave_valid_pre <= _T_158 @[axi4_to_ahb.scala 208:23] - node _T_159 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 209:34] - node _T_160 = and(buf_state_en, _T_159) @[axi4_to_ahb.scala 209:32] - cmd_done <= _T_160 @[axi4_to_ahb.scala 209:16] - node _T_161 = and(master_ready, master_valid) @[axi4_to_ahb.scala 210:33] - node _T_162 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 210:64] - node _T_163 = and(_T_161, _T_162) @[axi4_to_ahb.scala 210:48] - node _T_164 = and(_T_163, buf_state_en) @[axi4_to_ahb.scala 210:79] - bypass_en <= _T_164 @[axi4_to_ahb.scala 210:17] - node _T_165 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 211:47] - node _T_166 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 211:62] - node _T_167 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 211:78] - node _T_168 = mux(_T_165, _T_166, _T_167) @[axi4_to_ahb.scala 211:30] - buf_cmd_byte_ptr <= _T_168 @[axi4_to_ahb.scala 211:24] - node _T_169 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 212:63] - node _T_170 = and(_T_169, buf_state_en) @[axi4_to_ahb.scala 212:78] - node _T_171 = eq(_T_170, UInt<1>("h00")) @[axi4_to_ahb.scala 212:47] + node _T_137 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 194:39] + node _T_138 = and(ahb_hready_q, _T_137) @[axi4_to_ahb.scala 194:37] + node _T_139 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 194:82] + node _T_140 = eq(_T_139, UInt<1>("h01")) @[axi4_to_ahb.scala 194:89] + node _T_141 = and(master_valid, _T_140) @[axi4_to_ahb.scala 194:70] + node _T_142 = not(_T_141) @[axi4_to_ahb.scala 194:55] + node _T_143 = and(_T_138, _T_142) @[axi4_to_ahb.scala 194:53] + master_ready <= _T_143 @[axi4_to_ahb.scala 194:20] + node _T_144 = and(master_valid, master_ready) @[axi4_to_ahb.scala 195:34] + node _T_145 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 195:62] + node _T_146 = eq(_T_145, UInt<1>("h00")) @[axi4_to_ahb.scala 195:69] + node _T_147 = and(_T_144, _T_146) @[axi4_to_ahb.scala 195:49] + buf_wr_en <= _T_147 @[axi4_to_ahb.scala 195:17] + node _T_148 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 196:45] + node _T_149 = and(master_valid, master_ready) @[axi4_to_ahb.scala 196:82] + node _T_150 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 196:110] + node _T_151 = eq(_T_150, UInt<1>("h00")) @[axi4_to_ahb.scala 196:117] + node _T_152 = and(_T_149, _T_151) @[axi4_to_ahb.scala 196:97] + node _T_153 = bits(_T_152, 0, 0) @[axi4_to_ahb.scala 196:138] + node _T_154 = mux(_T_153, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 196:67] + node _T_155 = mux(_T_148, UInt<3>("h07"), _T_154) @[axi4_to_ahb.scala 196:26] + buf_nxtstate <= _T_155 @[axi4_to_ahb.scala 196:20] + node _T_156 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 197:37] + buf_state_en <= _T_156 @[axi4_to_ahb.scala 197:20] + buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 198:22] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 199:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 200:23] + node _T_157 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 201:41] + node _T_158 = and(buf_state_en, _T_157) @[axi4_to_ahb.scala 201:39] + slave_valid_pre <= _T_158 @[axi4_to_ahb.scala 201:23] + node _T_159 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 202:34] + node _T_160 = and(buf_state_en, _T_159) @[axi4_to_ahb.scala 202:32] + cmd_done <= _T_160 @[axi4_to_ahb.scala 202:16] + node _T_161 = and(master_ready, master_valid) @[axi4_to_ahb.scala 203:33] + node _T_162 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 203:64] + node _T_163 = and(_T_161, _T_162) @[axi4_to_ahb.scala 203:48] + node _T_164 = and(_T_163, buf_state_en) @[axi4_to_ahb.scala 203:79] + bypass_en <= _T_164 @[axi4_to_ahb.scala 203:17] + node _T_165 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 204:47] + node _T_166 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 204:62] + node _T_167 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 204:78] + node _T_168 = mux(_T_165, _T_166, _T_167) @[axi4_to_ahb.scala 204:30] + buf_cmd_byte_ptr <= _T_168 @[axi4_to_ahb.scala 204:24] + node _T_169 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 205:63] + node _T_170 = and(_T_169, buf_state_en) @[axi4_to_ahb.scala 205:78] + node _T_171 = eq(_T_170, UInt<1>("h00")) @[axi4_to_ahb.scala 205:47] node _T_172 = bits(_T_171, 0, 0) @[Bitwise.scala 72:15] node _T_173 = mux(_T_172, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_174 = and(UInt<2>("h02"), _T_173) @[axi4_to_ahb.scala 212:36] - io.ahb.out.htrans <= _T_174 @[axi4_to_ahb.scala 212:25] - slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 213:20] + node _T_174 = and(UInt<2>("h02"), _T_173) @[axi4_to_ahb.scala 205:36] + io.ahb.out.htrans <= _T_174 @[axi4_to_ahb.scala 205:25] + slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 206:20] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_175 = eq(UInt<3>("h07"), buf_state) @[Conditional.scala 37:30] when _T_175 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 217:20] - node _T_176 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 218:51] - node _T_177 = neq(_T_176, UInt<1>("h00")) @[axi4_to_ahb.scala 218:58] - node _T_178 = and(ahb_hready_q, _T_177) @[axi4_to_ahb.scala 218:36] - node _T_179 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 218:72] - node _T_180 = and(_T_178, _T_179) @[axi4_to_ahb.scala 218:70] - buf_state_en <= _T_180 @[axi4_to_ahb.scala 218:20] - slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 219:23] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 220:20] - node _T_181 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 221:35] - buf_cmd_byte_ptr <= _T_181 @[axi4_to_ahb.scala 221:24] - node _T_182 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 222:51] + buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 210:20] + node _T_176 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 211:51] + node _T_177 = neq(_T_176, UInt<1>("h00")) @[axi4_to_ahb.scala 211:58] + node _T_178 = and(ahb_hready_q, _T_177) @[axi4_to_ahb.scala 211:36] + node _T_179 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 211:72] + node _T_180 = and(_T_178, _T_179) @[axi4_to_ahb.scala 211:70] + buf_state_en <= _T_180 @[axi4_to_ahb.scala 211:20] + slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 212:23] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 213:20] + node _T_181 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 214:35] + buf_cmd_byte_ptr <= _T_181 @[axi4_to_ahb.scala 214:24] + node _T_182 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 215:51] node _T_183 = bits(_T_182, 0, 0) @[Bitwise.scala 72:15] node _T_184 = mux(_T_183, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_185 = and(UInt<2>("h02"), _T_184) @[axi4_to_ahb.scala 222:41] - io.ahb.out.htrans <= _T_185 @[axi4_to_ahb.scala 222:25] + node _T_185 = and(UInt<2>("h02"), _T_184) @[axi4_to_ahb.scala 215:41] + io.ahb.out.htrans <= _T_185 @[axi4_to_ahb.scala 215:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_186 = eq(UInt<3>("h03"), buf_state) @[Conditional.scala 37:30] when _T_186 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 226:20] - node _T_187 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 227:37] - buf_state_en <= _T_187 @[axi4_to_ahb.scala 227:20] - buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 228:22] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 229:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 230:23] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 231:20] + buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 219:20] + node _T_187 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 220:37] + buf_state_en <= _T_187 @[axi4_to_ahb.scala 220:20] + buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 221:22] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 222:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 223:23] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 224:20] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_188 = eq(UInt<3>("h02"), buf_state) @[Conditional.scala 37:30] when _T_188 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 235:20] - node _T_189 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 236:33] - node _T_190 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 236:63] - node _T_191 = neq(_T_190, UInt<1>("h00")) @[axi4_to_ahb.scala 236:70] - node _T_192 = and(_T_189, _T_191) @[axi4_to_ahb.scala 236:48] - trxn_done <= _T_192 @[axi4_to_ahb.scala 236:17] - buf_state_en <= trxn_done @[axi4_to_ahb.scala 237:20] - buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 238:27] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 239:20] - node _T_193 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 240:47] - node _T_194 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 240:85] - node _T_195 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 240:103] - node _T_196 = add(_T_194, UInt<1>("h01")) @[axi4_to_ahb.scala 142:52] - node _T_197 = tail(_T_196, 1) @[axi4_to_ahb.scala 142:52] - node _T_198 = mux(UInt<1>("h01"), _T_197, _T_194) @[axi4_to_ahb.scala 142:24] - node _T_199 = bits(_T_195, 0, 0) @[axi4_to_ahb.scala 143:44] - node _T_200 = geq(UInt<1>("h00"), _T_198) @[axi4_to_ahb.scala 143:62] - node _T_201 = and(_T_199, _T_200) @[axi4_to_ahb.scala 143:48] - node _T_202 = bits(_T_195, 1, 1) @[axi4_to_ahb.scala 143:44] - node _T_203 = geq(UInt<1>("h01"), _T_198) @[axi4_to_ahb.scala 143:62] - node _T_204 = and(_T_202, _T_203) @[axi4_to_ahb.scala 143:48] - node _T_205 = bits(_T_195, 2, 2) @[axi4_to_ahb.scala 143:44] - node _T_206 = geq(UInt<2>("h02"), _T_198) @[axi4_to_ahb.scala 143:62] - node _T_207 = and(_T_205, _T_206) @[axi4_to_ahb.scala 143:48] - node _T_208 = bits(_T_195, 3, 3) @[axi4_to_ahb.scala 143:44] - node _T_209 = geq(UInt<2>("h03"), _T_198) @[axi4_to_ahb.scala 143:62] - node _T_210 = and(_T_208, _T_209) @[axi4_to_ahb.scala 143:48] - node _T_211 = bits(_T_195, 4, 4) @[axi4_to_ahb.scala 143:44] - node _T_212 = geq(UInt<3>("h04"), _T_198) @[axi4_to_ahb.scala 143:62] - node _T_213 = and(_T_211, _T_212) @[axi4_to_ahb.scala 143:48] - node _T_214 = bits(_T_195, 5, 5) @[axi4_to_ahb.scala 143:44] - node _T_215 = geq(UInt<3>("h05"), _T_198) @[axi4_to_ahb.scala 143:62] - node _T_216 = and(_T_214, _T_215) @[axi4_to_ahb.scala 143:48] - node _T_217 = bits(_T_195, 6, 6) @[axi4_to_ahb.scala 143:44] - node _T_218 = geq(UInt<3>("h06"), _T_198) @[axi4_to_ahb.scala 143:62] - node _T_219 = and(_T_217, _T_218) @[axi4_to_ahb.scala 143:48] - node _T_220 = bits(_T_195, 7, 7) @[axi4_to_ahb.scala 143:44] - node _T_221 = geq(UInt<3>("h07"), _T_198) @[axi4_to_ahb.scala 143:62] - node _T_222 = and(_T_220, _T_221) @[axi4_to_ahb.scala 143:48] + buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 228:20] + node _T_189 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 229:33] + node _T_190 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 229:63] + node _T_191 = neq(_T_190, UInt<1>("h00")) @[axi4_to_ahb.scala 229:70] + node _T_192 = and(_T_189, _T_191) @[axi4_to_ahb.scala 229:48] + trxn_done <= _T_192 @[axi4_to_ahb.scala 229:17] + buf_state_en <= trxn_done @[axi4_to_ahb.scala 230:20] + buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 231:27] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 232:20] + node _T_193 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 233:47] + node _T_194 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 233:85] + node _T_195 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 233:103] + node _T_196 = add(_T_194, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] + node _T_197 = tail(_T_196, 1) @[axi4_to_ahb.scala 135:52] + node _T_198 = mux(UInt<1>("h01"), _T_197, _T_194) @[axi4_to_ahb.scala 135:24] + node _T_199 = bits(_T_195, 0, 0) @[axi4_to_ahb.scala 136:44] + node _T_200 = geq(UInt<1>("h00"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_201 = and(_T_199, _T_200) @[axi4_to_ahb.scala 136:48] + node _T_202 = bits(_T_195, 1, 1) @[axi4_to_ahb.scala 136:44] + node _T_203 = geq(UInt<1>("h01"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_204 = and(_T_202, _T_203) @[axi4_to_ahb.scala 136:48] + node _T_205 = bits(_T_195, 2, 2) @[axi4_to_ahb.scala 136:44] + node _T_206 = geq(UInt<2>("h02"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_207 = and(_T_205, _T_206) @[axi4_to_ahb.scala 136:48] + node _T_208 = bits(_T_195, 3, 3) @[axi4_to_ahb.scala 136:44] + node _T_209 = geq(UInt<2>("h03"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_210 = and(_T_208, _T_209) @[axi4_to_ahb.scala 136:48] + node _T_211 = bits(_T_195, 4, 4) @[axi4_to_ahb.scala 136:44] + node _T_212 = geq(UInt<3>("h04"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_213 = and(_T_211, _T_212) @[axi4_to_ahb.scala 136:48] + node _T_214 = bits(_T_195, 5, 5) @[axi4_to_ahb.scala 136:44] + node _T_215 = geq(UInt<3>("h05"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_216 = and(_T_214, _T_215) @[axi4_to_ahb.scala 136:48] + node _T_217 = bits(_T_195, 6, 6) @[axi4_to_ahb.scala 136:44] + node _T_218 = geq(UInt<3>("h06"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_219 = and(_T_217, _T_218) @[axi4_to_ahb.scala 136:48] + node _T_220 = bits(_T_195, 7, 7) @[axi4_to_ahb.scala 136:44] + node _T_221 = geq(UInt<3>("h07"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_222 = and(_T_220, _T_221) @[axi4_to_ahb.scala 136:48] node _T_223 = mux(_T_222, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_224 = mux(_T_219, UInt<3>("h06"), _T_223) @[Mux.scala 98:16] node _T_225 = mux(_T_216, UInt<3>("h05"), _T_224) @[Mux.scala 98:16] @@ -733,39 +733,39 @@ circuit axi4_to_ahb : node _T_228 = mux(_T_207, UInt<2>("h02"), _T_227) @[Mux.scala 98:16] node _T_229 = mux(_T_204, UInt<1>("h01"), _T_228) @[Mux.scala 98:16] node _T_230 = mux(_T_201, UInt<1>("h00"), _T_229) @[Mux.scala 98:16] - node _T_231 = mux(_T_193, _T_230, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 240:30] - buf_cmd_byte_ptr <= _T_231 @[axi4_to_ahb.scala 240:24] - node _T_232 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 241:65] - node _T_233 = or(buf_aligned, _T_232) @[axi4_to_ahb.scala 241:44] - node _T_234 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 241:127] - node _T_235 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 241:145] - node _T_236 = add(_T_234, UInt<1>("h01")) @[axi4_to_ahb.scala 142:52] - node _T_237 = tail(_T_236, 1) @[axi4_to_ahb.scala 142:52] - node _T_238 = mux(UInt<1>("h01"), _T_237, _T_234) @[axi4_to_ahb.scala 142:24] - node _T_239 = bits(_T_235, 0, 0) @[axi4_to_ahb.scala 143:44] - node _T_240 = geq(UInt<1>("h00"), _T_238) @[axi4_to_ahb.scala 143:62] - node _T_241 = and(_T_239, _T_240) @[axi4_to_ahb.scala 143:48] - node _T_242 = bits(_T_235, 1, 1) @[axi4_to_ahb.scala 143:44] - node _T_243 = geq(UInt<1>("h01"), _T_238) @[axi4_to_ahb.scala 143:62] - node _T_244 = and(_T_242, _T_243) @[axi4_to_ahb.scala 143:48] - node _T_245 = bits(_T_235, 2, 2) @[axi4_to_ahb.scala 143:44] - node _T_246 = geq(UInt<2>("h02"), _T_238) @[axi4_to_ahb.scala 143:62] - node _T_247 = and(_T_245, _T_246) @[axi4_to_ahb.scala 143:48] - node _T_248 = bits(_T_235, 3, 3) @[axi4_to_ahb.scala 143:44] - node _T_249 = geq(UInt<2>("h03"), _T_238) @[axi4_to_ahb.scala 143:62] - node _T_250 = and(_T_248, _T_249) @[axi4_to_ahb.scala 143:48] - node _T_251 = bits(_T_235, 4, 4) @[axi4_to_ahb.scala 143:44] - node _T_252 = geq(UInt<3>("h04"), _T_238) @[axi4_to_ahb.scala 143:62] - node _T_253 = and(_T_251, _T_252) @[axi4_to_ahb.scala 143:48] - node _T_254 = bits(_T_235, 5, 5) @[axi4_to_ahb.scala 143:44] - node _T_255 = geq(UInt<3>("h05"), _T_238) @[axi4_to_ahb.scala 143:62] - node _T_256 = and(_T_254, _T_255) @[axi4_to_ahb.scala 143:48] - node _T_257 = bits(_T_235, 6, 6) @[axi4_to_ahb.scala 143:44] - node _T_258 = geq(UInt<3>("h06"), _T_238) @[axi4_to_ahb.scala 143:62] - node _T_259 = and(_T_257, _T_258) @[axi4_to_ahb.scala 143:48] - node _T_260 = bits(_T_235, 7, 7) @[axi4_to_ahb.scala 143:44] - node _T_261 = geq(UInt<3>("h07"), _T_238) @[axi4_to_ahb.scala 143:62] - node _T_262 = and(_T_260, _T_261) @[axi4_to_ahb.scala 143:48] + node _T_231 = mux(_T_193, _T_230, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 233:30] + buf_cmd_byte_ptr <= _T_231 @[axi4_to_ahb.scala 233:24] + node _T_232 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 234:65] + node _T_233 = or(buf_aligned, _T_232) @[axi4_to_ahb.scala 234:44] + node _T_234 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 234:127] + node _T_235 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 234:145] + node _T_236 = add(_T_234, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] + node _T_237 = tail(_T_236, 1) @[axi4_to_ahb.scala 135:52] + node _T_238 = mux(UInt<1>("h01"), _T_237, _T_234) @[axi4_to_ahb.scala 135:24] + node _T_239 = bits(_T_235, 0, 0) @[axi4_to_ahb.scala 136:44] + node _T_240 = geq(UInt<1>("h00"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_241 = and(_T_239, _T_240) @[axi4_to_ahb.scala 136:48] + node _T_242 = bits(_T_235, 1, 1) @[axi4_to_ahb.scala 136:44] + node _T_243 = geq(UInt<1>("h01"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_244 = and(_T_242, _T_243) @[axi4_to_ahb.scala 136:48] + node _T_245 = bits(_T_235, 2, 2) @[axi4_to_ahb.scala 136:44] + node _T_246 = geq(UInt<2>("h02"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_247 = and(_T_245, _T_246) @[axi4_to_ahb.scala 136:48] + node _T_248 = bits(_T_235, 3, 3) @[axi4_to_ahb.scala 136:44] + node _T_249 = geq(UInt<2>("h03"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_250 = and(_T_248, _T_249) @[axi4_to_ahb.scala 136:48] + node _T_251 = bits(_T_235, 4, 4) @[axi4_to_ahb.scala 136:44] + node _T_252 = geq(UInt<3>("h04"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_253 = and(_T_251, _T_252) @[axi4_to_ahb.scala 136:48] + node _T_254 = bits(_T_235, 5, 5) @[axi4_to_ahb.scala 136:44] + node _T_255 = geq(UInt<3>("h05"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_256 = and(_T_254, _T_255) @[axi4_to_ahb.scala 136:48] + node _T_257 = bits(_T_235, 6, 6) @[axi4_to_ahb.scala 136:44] + node _T_258 = geq(UInt<3>("h06"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_259 = and(_T_257, _T_258) @[axi4_to_ahb.scala 136:48] + node _T_260 = bits(_T_235, 7, 7) @[axi4_to_ahb.scala 136:44] + node _T_261 = geq(UInt<3>("h07"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_262 = and(_T_260, _T_261) @[axi4_to_ahb.scala 136:48] node _T_263 = mux(_T_262, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_264 = mux(_T_259, UInt<3>("h06"), _T_263) @[Mux.scala 98:16] node _T_265 = mux(_T_256, UInt<3>("h05"), _T_264) @[Mux.scala 98:16] @@ -774,83 +774,83 @@ circuit axi4_to_ahb : node _T_268 = mux(_T_247, UInt<2>("h02"), _T_267) @[Mux.scala 98:16] node _T_269 = mux(_T_244, UInt<1>("h01"), _T_268) @[Mux.scala 98:16] node _T_270 = mux(_T_241, UInt<1>("h00"), _T_269) @[Mux.scala 98:16] - node _T_271 = dshr(buf_byteen, _T_270) @[axi4_to_ahb.scala 241:92] - node _T_272 = bits(_T_271, 0, 0) @[axi4_to_ahb.scala 241:92] - node _T_273 = eq(_T_272, UInt<1>("h00")) @[axi4_to_ahb.scala 241:163] - node _T_274 = or(_T_233, _T_273) @[axi4_to_ahb.scala 241:79] - node _T_275 = and(trxn_done, _T_274) @[axi4_to_ahb.scala 241:29] - cmd_done <= _T_275 @[axi4_to_ahb.scala 241:16] - node _T_276 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 242:47] - node _T_277 = eq(_T_276, UInt<1>("h00")) @[axi4_to_ahb.scala 242:36] + node _T_271 = dshr(buf_byteen, _T_270) @[axi4_to_ahb.scala 234:92] + node _T_272 = bits(_T_271, 0, 0) @[axi4_to_ahb.scala 234:92] + node _T_273 = eq(_T_272, UInt<1>("h00")) @[axi4_to_ahb.scala 234:163] + node _T_274 = or(_T_233, _T_273) @[axi4_to_ahb.scala 234:79] + node _T_275 = and(trxn_done, _T_274) @[axi4_to_ahb.scala 234:29] + cmd_done <= _T_275 @[axi4_to_ahb.scala 234:16] + node _T_276 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 235:47] + node _T_277 = eq(_T_276, UInt<1>("h00")) @[axi4_to_ahb.scala 235:36] node _T_278 = bits(_T_277, 0, 0) @[Bitwise.scala 72:15] node _T_279 = mux(_T_278, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_280 = and(_T_279, UInt<2>("h02")) @[axi4_to_ahb.scala 242:61] - io.ahb.out.htrans <= _T_280 @[axi4_to_ahb.scala 242:25] + node _T_280 = and(_T_279, UInt<2>("h02")) @[axi4_to_ahb.scala 235:61] + io.ahb.out.htrans <= _T_280 @[axi4_to_ahb.scala 235:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_281 = eq(UInt<3>("h04"), buf_state) @[Conditional.scala 37:30] when _T_281 : @[Conditional.scala 39:67] - node _T_282 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 246:34] - node _T_283 = or(_T_282, ahb_hresp_q) @[axi4_to_ahb.scala 246:50] - buf_state_en <= _T_283 @[axi4_to_ahb.scala 246:20] - node _T_284 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 247:38] - node _T_285 = and(buf_state_en, _T_284) @[axi4_to_ahb.scala 247:36] - node _T_286 = and(_T_285, slave_ready) @[axi4_to_ahb.scala 247:51] - master_ready <= _T_286 @[axi4_to_ahb.scala 247:20] - node _T_287 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 248:42] - node _T_288 = or(ahb_hresp_q, _T_287) @[axi4_to_ahb.scala 248:40] - node _T_289 = and(master_valid, master_valid) @[axi4_to_ahb.scala 248:80] - node _T_290 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 248:111] - node _T_291 = eq(_T_290, UInt<1>("h01")) @[axi4_to_ahb.scala 248:117] - node _T_292 = bits(_T_291, 0, 0) @[axi4_to_ahb.scala 248:132] - node _T_293 = mux(_T_292, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 248:99] - node _T_294 = mux(_T_289, _T_293, UInt<3>("h00")) @[axi4_to_ahb.scala 248:65] - node _T_295 = mux(_T_288, UInt<3>("h05"), _T_294) @[axi4_to_ahb.scala 248:26] - buf_nxtstate <= _T_295 @[axi4_to_ahb.scala 248:20] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 249:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 250:23] - node _T_296 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 251:33] - node _T_297 = eq(_T_296, UInt<1>("h01")) @[axi4_to_ahb.scala 251:39] - buf_write_in <= _T_297 @[axi4_to_ahb.scala 251:20] - node _T_298 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 252:50] - node _T_299 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 252:78] - node _T_300 = or(_T_298, _T_299) @[axi4_to_ahb.scala 252:62] - node _T_301 = and(buf_state_en, _T_300) @[axi4_to_ahb.scala 252:33] - buf_wr_en <= _T_301 @[axi4_to_ahb.scala 252:17] - buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 253:22] - node _T_302 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 254:65] - node _T_303 = neq(_T_302, UInt<1>("h00")) @[axi4_to_ahb.scala 254:71] - node _T_304 = and(ahb_hready_q, _T_303) @[axi4_to_ahb.scala 254:50] - node _T_305 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 255:29] - node _T_306 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 255:85] - node _T_307 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 255:101] - node _T_308 = add(_T_306, UInt<1>("h01")) @[axi4_to_ahb.scala 142:52] - node _T_309 = tail(_T_308, 1) @[axi4_to_ahb.scala 142:52] - node _T_310 = mux(UInt<1>("h01"), _T_309, _T_306) @[axi4_to_ahb.scala 142:24] - node _T_311 = bits(_T_307, 0, 0) @[axi4_to_ahb.scala 143:44] - node _T_312 = geq(UInt<1>("h00"), _T_310) @[axi4_to_ahb.scala 143:62] - node _T_313 = and(_T_311, _T_312) @[axi4_to_ahb.scala 143:48] - node _T_314 = bits(_T_307, 1, 1) @[axi4_to_ahb.scala 143:44] - node _T_315 = geq(UInt<1>("h01"), _T_310) @[axi4_to_ahb.scala 143:62] - node _T_316 = and(_T_314, _T_315) @[axi4_to_ahb.scala 143:48] - node _T_317 = bits(_T_307, 2, 2) @[axi4_to_ahb.scala 143:44] - node _T_318 = geq(UInt<2>("h02"), _T_310) @[axi4_to_ahb.scala 143:62] - node _T_319 = and(_T_317, _T_318) @[axi4_to_ahb.scala 143:48] - node _T_320 = bits(_T_307, 3, 3) @[axi4_to_ahb.scala 143:44] - node _T_321 = geq(UInt<2>("h03"), _T_310) @[axi4_to_ahb.scala 143:62] - node _T_322 = and(_T_320, _T_321) @[axi4_to_ahb.scala 143:48] - node _T_323 = bits(_T_307, 4, 4) @[axi4_to_ahb.scala 143:44] - node _T_324 = geq(UInt<3>("h04"), _T_310) @[axi4_to_ahb.scala 143:62] - node _T_325 = and(_T_323, _T_324) @[axi4_to_ahb.scala 143:48] - node _T_326 = bits(_T_307, 5, 5) @[axi4_to_ahb.scala 143:44] - node _T_327 = geq(UInt<3>("h05"), _T_310) @[axi4_to_ahb.scala 143:62] - node _T_328 = and(_T_326, _T_327) @[axi4_to_ahb.scala 143:48] - node _T_329 = bits(_T_307, 6, 6) @[axi4_to_ahb.scala 143:44] - node _T_330 = geq(UInt<3>("h06"), _T_310) @[axi4_to_ahb.scala 143:62] - node _T_331 = and(_T_329, _T_330) @[axi4_to_ahb.scala 143:48] - node _T_332 = bits(_T_307, 7, 7) @[axi4_to_ahb.scala 143:44] - node _T_333 = geq(UInt<3>("h07"), _T_310) @[axi4_to_ahb.scala 143:62] - node _T_334 = and(_T_332, _T_333) @[axi4_to_ahb.scala 143:48] + node _T_282 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 239:34] + node _T_283 = or(_T_282, ahb_hresp_q) @[axi4_to_ahb.scala 239:50] + buf_state_en <= _T_283 @[axi4_to_ahb.scala 239:20] + node _T_284 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 240:38] + node _T_285 = and(buf_state_en, _T_284) @[axi4_to_ahb.scala 240:36] + node _T_286 = and(_T_285, slave_ready) @[axi4_to_ahb.scala 240:51] + master_ready <= _T_286 @[axi4_to_ahb.scala 240:20] + node _T_287 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 241:42] + node _T_288 = or(ahb_hresp_q, _T_287) @[axi4_to_ahb.scala 241:40] + node _T_289 = and(master_valid, master_valid) @[axi4_to_ahb.scala 241:80] + node _T_290 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 241:111] + node _T_291 = eq(_T_290, UInt<1>("h01")) @[axi4_to_ahb.scala 241:117] + node _T_292 = bits(_T_291, 0, 0) @[axi4_to_ahb.scala 241:132] + node _T_293 = mux(_T_292, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 241:99] + node _T_294 = mux(_T_289, _T_293, UInt<3>("h00")) @[axi4_to_ahb.scala 241:65] + node _T_295 = mux(_T_288, UInt<3>("h05"), _T_294) @[axi4_to_ahb.scala 241:26] + buf_nxtstate <= _T_295 @[axi4_to_ahb.scala 241:20] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 242:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 243:23] + node _T_296 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 244:33] + node _T_297 = eq(_T_296, UInt<1>("h01")) @[axi4_to_ahb.scala 244:39] + buf_write_in <= _T_297 @[axi4_to_ahb.scala 244:20] + node _T_298 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 245:50] + node _T_299 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 245:78] + node _T_300 = or(_T_298, _T_299) @[axi4_to_ahb.scala 245:62] + node _T_301 = and(buf_state_en, _T_300) @[axi4_to_ahb.scala 245:33] + buf_wr_en <= _T_301 @[axi4_to_ahb.scala 245:17] + buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 246:22] + node _T_302 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 247:65] + node _T_303 = neq(_T_302, UInt<1>("h00")) @[axi4_to_ahb.scala 247:71] + node _T_304 = and(ahb_hready_q, _T_303) @[axi4_to_ahb.scala 247:50] + node _T_305 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 248:29] + node _T_306 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 248:85] + node _T_307 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 248:101] + node _T_308 = add(_T_306, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] + node _T_309 = tail(_T_308, 1) @[axi4_to_ahb.scala 135:52] + node _T_310 = mux(UInt<1>("h01"), _T_309, _T_306) @[axi4_to_ahb.scala 135:24] + node _T_311 = bits(_T_307, 0, 0) @[axi4_to_ahb.scala 136:44] + node _T_312 = geq(UInt<1>("h00"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_313 = and(_T_311, _T_312) @[axi4_to_ahb.scala 136:48] + node _T_314 = bits(_T_307, 1, 1) @[axi4_to_ahb.scala 136:44] + node _T_315 = geq(UInt<1>("h01"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_316 = and(_T_314, _T_315) @[axi4_to_ahb.scala 136:48] + node _T_317 = bits(_T_307, 2, 2) @[axi4_to_ahb.scala 136:44] + node _T_318 = geq(UInt<2>("h02"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_319 = and(_T_317, _T_318) @[axi4_to_ahb.scala 136:48] + node _T_320 = bits(_T_307, 3, 3) @[axi4_to_ahb.scala 136:44] + node _T_321 = geq(UInt<2>("h03"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_322 = and(_T_320, _T_321) @[axi4_to_ahb.scala 136:48] + node _T_323 = bits(_T_307, 4, 4) @[axi4_to_ahb.scala 136:44] + node _T_324 = geq(UInt<3>("h04"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_325 = and(_T_323, _T_324) @[axi4_to_ahb.scala 136:48] + node _T_326 = bits(_T_307, 5, 5) @[axi4_to_ahb.scala 136:44] + node _T_327 = geq(UInt<3>("h05"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_328 = and(_T_326, _T_327) @[axi4_to_ahb.scala 136:48] + node _T_329 = bits(_T_307, 6, 6) @[axi4_to_ahb.scala 136:44] + node _T_330 = geq(UInt<3>("h06"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_331 = and(_T_329, _T_330) @[axi4_to_ahb.scala 136:48] + node _T_332 = bits(_T_307, 7, 7) @[axi4_to_ahb.scala 136:44] + node _T_333 = geq(UInt<3>("h07"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_334 = and(_T_332, _T_333) @[axi4_to_ahb.scala 136:48] node _T_335 = mux(_T_334, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_336 = mux(_T_331, UInt<3>("h06"), _T_335) @[Mux.scala 98:16] node _T_337 = mux(_T_328, UInt<3>("h05"), _T_336) @[Mux.scala 98:16] @@ -859,62 +859,62 @@ circuit axi4_to_ahb : node _T_340 = mux(_T_319, UInt<2>("h02"), _T_339) @[Mux.scala 98:16] node _T_341 = mux(_T_316, UInt<1>("h01"), _T_340) @[Mux.scala 98:16] node _T_342 = mux(_T_313, UInt<1>("h00"), _T_341) @[Mux.scala 98:16] - node _T_343 = dshr(buf_byteen, _T_342) @[axi4_to_ahb.scala 255:51] - node _T_344 = bits(_T_343, 0, 0) @[axi4_to_ahb.scala 255:51] - node _T_345 = eq(_T_344, UInt<1>("h00")) @[axi4_to_ahb.scala 255:116] - node _T_346 = or(_T_305, _T_345) @[axi4_to_ahb.scala 255:38] - node _T_347 = and(_T_304, _T_346) @[axi4_to_ahb.scala 254:80] - node _T_348 = or(ahb_hresp_q, _T_347) @[axi4_to_ahb.scala 254:34] - cmd_done <= _T_348 @[axi4_to_ahb.scala 254:16] - node _T_349 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 256:33] - node _T_350 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 256:64] - node _T_351 = and(_T_349, _T_350) @[axi4_to_ahb.scala 256:48] - bypass_en <= _T_351 @[axi4_to_ahb.scala 256:17] - node _T_352 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 257:48] - node _T_353 = eq(_T_352, UInt<1>("h00")) @[axi4_to_ahb.scala 257:37] - node _T_354 = or(_T_353, bypass_en) @[axi4_to_ahb.scala 257:61] + node _T_343 = dshr(buf_byteen, _T_342) @[axi4_to_ahb.scala 248:51] + node _T_344 = bits(_T_343, 0, 0) @[axi4_to_ahb.scala 248:51] + node _T_345 = eq(_T_344, UInt<1>("h00")) @[axi4_to_ahb.scala 248:116] + node _T_346 = or(_T_305, _T_345) @[axi4_to_ahb.scala 248:38] + node _T_347 = and(_T_304, _T_346) @[axi4_to_ahb.scala 247:80] + node _T_348 = or(ahb_hresp_q, _T_347) @[axi4_to_ahb.scala 247:34] + cmd_done <= _T_348 @[axi4_to_ahb.scala 247:16] + node _T_349 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 249:33] + node _T_350 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 249:64] + node _T_351 = and(_T_349, _T_350) @[axi4_to_ahb.scala 249:48] + bypass_en <= _T_351 @[axi4_to_ahb.scala 249:17] + node _T_352 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 250:48] + node _T_353 = eq(_T_352, UInt<1>("h00")) @[axi4_to_ahb.scala 250:37] + node _T_354 = or(_T_353, bypass_en) @[axi4_to_ahb.scala 250:61] node _T_355 = bits(_T_354, 0, 0) @[Bitwise.scala 72:15] node _T_356 = mux(_T_355, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_357 = and(_T_356, UInt<2>("h02")) @[axi4_to_ahb.scala 257:75] - io.ahb.out.htrans <= _T_357 @[axi4_to_ahb.scala 257:25] - node _T_358 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 258:55] - node _T_359 = and(buf_state_en, _T_358) @[axi4_to_ahb.scala 258:39] - slave_valid_pre <= _T_359 @[axi4_to_ahb.scala 258:23] - node _T_360 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 259:33] - node _T_361 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 259:63] - node _T_362 = neq(_T_361, UInt<1>("h00")) @[axi4_to_ahb.scala 259:69] - node _T_363 = and(_T_360, _T_362) @[axi4_to_ahb.scala 259:48] - trxn_done <= _T_363 @[axi4_to_ahb.scala 259:17] - node _T_364 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 260:40] - buf_cmd_byte_ptr_en <= _T_364 @[axi4_to_ahb.scala 260:27] - node _T_365 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 261:79] - node _T_366 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 142:52] - node _T_367 = tail(_T_366, 1) @[axi4_to_ahb.scala 142:52] - node _T_368 = mux(UInt<1>("h00"), _T_367, UInt<3>("h00")) @[axi4_to_ahb.scala 142:24] - node _T_369 = bits(_T_365, 0, 0) @[axi4_to_ahb.scala 143:44] - node _T_370 = geq(UInt<1>("h00"), _T_368) @[axi4_to_ahb.scala 143:62] - node _T_371 = and(_T_369, _T_370) @[axi4_to_ahb.scala 143:48] - node _T_372 = bits(_T_365, 1, 1) @[axi4_to_ahb.scala 143:44] - node _T_373 = geq(UInt<1>("h01"), _T_368) @[axi4_to_ahb.scala 143:62] - node _T_374 = and(_T_372, _T_373) @[axi4_to_ahb.scala 143:48] - node _T_375 = bits(_T_365, 2, 2) @[axi4_to_ahb.scala 143:44] - node _T_376 = geq(UInt<2>("h02"), _T_368) @[axi4_to_ahb.scala 143:62] - node _T_377 = and(_T_375, _T_376) @[axi4_to_ahb.scala 143:48] - node _T_378 = bits(_T_365, 3, 3) @[axi4_to_ahb.scala 143:44] - node _T_379 = geq(UInt<2>("h03"), _T_368) @[axi4_to_ahb.scala 143:62] - node _T_380 = and(_T_378, _T_379) @[axi4_to_ahb.scala 143:48] - node _T_381 = bits(_T_365, 4, 4) @[axi4_to_ahb.scala 143:44] - node _T_382 = geq(UInt<3>("h04"), _T_368) @[axi4_to_ahb.scala 143:62] - node _T_383 = and(_T_381, _T_382) @[axi4_to_ahb.scala 143:48] - node _T_384 = bits(_T_365, 5, 5) @[axi4_to_ahb.scala 143:44] - node _T_385 = geq(UInt<3>("h05"), _T_368) @[axi4_to_ahb.scala 143:62] - node _T_386 = and(_T_384, _T_385) @[axi4_to_ahb.scala 143:48] - node _T_387 = bits(_T_365, 6, 6) @[axi4_to_ahb.scala 143:44] - node _T_388 = geq(UInt<3>("h06"), _T_368) @[axi4_to_ahb.scala 143:62] - node _T_389 = and(_T_387, _T_388) @[axi4_to_ahb.scala 143:48] - node _T_390 = bits(_T_365, 7, 7) @[axi4_to_ahb.scala 143:44] - node _T_391 = geq(UInt<3>("h07"), _T_368) @[axi4_to_ahb.scala 143:62] - node _T_392 = and(_T_390, _T_391) @[axi4_to_ahb.scala 143:48] + node _T_357 = and(_T_356, UInt<2>("h02")) @[axi4_to_ahb.scala 250:75] + io.ahb.out.htrans <= _T_357 @[axi4_to_ahb.scala 250:25] + node _T_358 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 251:55] + node _T_359 = and(buf_state_en, _T_358) @[axi4_to_ahb.scala 251:39] + slave_valid_pre <= _T_359 @[axi4_to_ahb.scala 251:23] + node _T_360 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 252:33] + node _T_361 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 252:63] + node _T_362 = neq(_T_361, UInt<1>("h00")) @[axi4_to_ahb.scala 252:69] + node _T_363 = and(_T_360, _T_362) @[axi4_to_ahb.scala 252:48] + trxn_done <= _T_363 @[axi4_to_ahb.scala 252:17] + node _T_364 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 253:40] + buf_cmd_byte_ptr_en <= _T_364 @[axi4_to_ahb.scala 253:27] + node _T_365 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 254:79] + node _T_366 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] + node _T_367 = tail(_T_366, 1) @[axi4_to_ahb.scala 135:52] + node _T_368 = mux(UInt<1>("h00"), _T_367, UInt<3>("h00")) @[axi4_to_ahb.scala 135:24] + node _T_369 = bits(_T_365, 0, 0) @[axi4_to_ahb.scala 136:44] + node _T_370 = geq(UInt<1>("h00"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_371 = and(_T_369, _T_370) @[axi4_to_ahb.scala 136:48] + node _T_372 = bits(_T_365, 1, 1) @[axi4_to_ahb.scala 136:44] + node _T_373 = geq(UInt<1>("h01"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_374 = and(_T_372, _T_373) @[axi4_to_ahb.scala 136:48] + node _T_375 = bits(_T_365, 2, 2) @[axi4_to_ahb.scala 136:44] + node _T_376 = geq(UInt<2>("h02"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_377 = and(_T_375, _T_376) @[axi4_to_ahb.scala 136:48] + node _T_378 = bits(_T_365, 3, 3) @[axi4_to_ahb.scala 136:44] + node _T_379 = geq(UInt<2>("h03"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_380 = and(_T_378, _T_379) @[axi4_to_ahb.scala 136:48] + node _T_381 = bits(_T_365, 4, 4) @[axi4_to_ahb.scala 136:44] + node _T_382 = geq(UInt<3>("h04"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_383 = and(_T_381, _T_382) @[axi4_to_ahb.scala 136:48] + node _T_384 = bits(_T_365, 5, 5) @[axi4_to_ahb.scala 136:44] + node _T_385 = geq(UInt<3>("h05"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_386 = and(_T_384, _T_385) @[axi4_to_ahb.scala 136:48] + node _T_387 = bits(_T_365, 6, 6) @[axi4_to_ahb.scala 136:44] + node _T_388 = geq(UInt<3>("h06"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_389 = and(_T_387, _T_388) @[axi4_to_ahb.scala 136:48] + node _T_390 = bits(_T_365, 7, 7) @[axi4_to_ahb.scala 136:44] + node _T_391 = geq(UInt<3>("h07"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_392 = and(_T_390, _T_391) @[axi4_to_ahb.scala 136:48] node _T_393 = mux(_T_392, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_394 = mux(_T_389, UInt<3>("h06"), _T_393) @[Mux.scala 98:16] node _T_395 = mux(_T_386, UInt<3>("h05"), _T_394) @[Mux.scala 98:16] @@ -923,35 +923,35 @@ circuit axi4_to_ahb : node _T_398 = mux(_T_377, UInt<2>("h02"), _T_397) @[Mux.scala 98:16] node _T_399 = mux(_T_374, UInt<1>("h01"), _T_398) @[Mux.scala 98:16] node _T_400 = mux(_T_371, UInt<1>("h00"), _T_399) @[Mux.scala 98:16] - node _T_401 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 261:141] - node _T_402 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 261:157] - node _T_403 = add(_T_401, UInt<1>("h01")) @[axi4_to_ahb.scala 142:52] - node _T_404 = tail(_T_403, 1) @[axi4_to_ahb.scala 142:52] - node _T_405 = mux(UInt<1>("h01"), _T_404, _T_401) @[axi4_to_ahb.scala 142:24] - node _T_406 = bits(_T_402, 0, 0) @[axi4_to_ahb.scala 143:44] - node _T_407 = geq(UInt<1>("h00"), _T_405) @[axi4_to_ahb.scala 143:62] - node _T_408 = and(_T_406, _T_407) @[axi4_to_ahb.scala 143:48] - node _T_409 = bits(_T_402, 1, 1) @[axi4_to_ahb.scala 143:44] - node _T_410 = geq(UInt<1>("h01"), _T_405) @[axi4_to_ahb.scala 143:62] - node _T_411 = and(_T_409, _T_410) @[axi4_to_ahb.scala 143:48] - node _T_412 = bits(_T_402, 2, 2) @[axi4_to_ahb.scala 143:44] - node _T_413 = geq(UInt<2>("h02"), _T_405) @[axi4_to_ahb.scala 143:62] - node _T_414 = and(_T_412, _T_413) @[axi4_to_ahb.scala 143:48] - node _T_415 = bits(_T_402, 3, 3) @[axi4_to_ahb.scala 143:44] - node _T_416 = geq(UInt<2>("h03"), _T_405) @[axi4_to_ahb.scala 143:62] - node _T_417 = and(_T_415, _T_416) @[axi4_to_ahb.scala 143:48] - node _T_418 = bits(_T_402, 4, 4) @[axi4_to_ahb.scala 143:44] - node _T_419 = geq(UInt<3>("h04"), _T_405) @[axi4_to_ahb.scala 143:62] - node _T_420 = and(_T_418, _T_419) @[axi4_to_ahb.scala 143:48] - node _T_421 = bits(_T_402, 5, 5) @[axi4_to_ahb.scala 143:44] - node _T_422 = geq(UInt<3>("h05"), _T_405) @[axi4_to_ahb.scala 143:62] - node _T_423 = and(_T_421, _T_422) @[axi4_to_ahb.scala 143:48] - node _T_424 = bits(_T_402, 6, 6) @[axi4_to_ahb.scala 143:44] - node _T_425 = geq(UInt<3>("h06"), _T_405) @[axi4_to_ahb.scala 143:62] - node _T_426 = and(_T_424, _T_425) @[axi4_to_ahb.scala 143:48] - node _T_427 = bits(_T_402, 7, 7) @[axi4_to_ahb.scala 143:44] - node _T_428 = geq(UInt<3>("h07"), _T_405) @[axi4_to_ahb.scala 143:62] - node _T_429 = and(_T_427, _T_428) @[axi4_to_ahb.scala 143:48] + node _T_401 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 254:141] + node _T_402 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 254:157] + node _T_403 = add(_T_401, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] + node _T_404 = tail(_T_403, 1) @[axi4_to_ahb.scala 135:52] + node _T_405 = mux(UInt<1>("h01"), _T_404, _T_401) @[axi4_to_ahb.scala 135:24] + node _T_406 = bits(_T_402, 0, 0) @[axi4_to_ahb.scala 136:44] + node _T_407 = geq(UInt<1>("h00"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_408 = and(_T_406, _T_407) @[axi4_to_ahb.scala 136:48] + node _T_409 = bits(_T_402, 1, 1) @[axi4_to_ahb.scala 136:44] + node _T_410 = geq(UInt<1>("h01"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_411 = and(_T_409, _T_410) @[axi4_to_ahb.scala 136:48] + node _T_412 = bits(_T_402, 2, 2) @[axi4_to_ahb.scala 136:44] + node _T_413 = geq(UInt<2>("h02"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_414 = and(_T_412, _T_413) @[axi4_to_ahb.scala 136:48] + node _T_415 = bits(_T_402, 3, 3) @[axi4_to_ahb.scala 136:44] + node _T_416 = geq(UInt<2>("h03"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_417 = and(_T_415, _T_416) @[axi4_to_ahb.scala 136:48] + node _T_418 = bits(_T_402, 4, 4) @[axi4_to_ahb.scala 136:44] + node _T_419 = geq(UInt<3>("h04"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_420 = and(_T_418, _T_419) @[axi4_to_ahb.scala 136:48] + node _T_421 = bits(_T_402, 5, 5) @[axi4_to_ahb.scala 136:44] + node _T_422 = geq(UInt<3>("h05"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_423 = and(_T_421, _T_422) @[axi4_to_ahb.scala 136:48] + node _T_424 = bits(_T_402, 6, 6) @[axi4_to_ahb.scala 136:44] + node _T_425 = geq(UInt<3>("h06"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_426 = and(_T_424, _T_425) @[axi4_to_ahb.scala 136:48] + node _T_427 = bits(_T_402, 7, 7) @[axi4_to_ahb.scala 136:44] + node _T_428 = geq(UInt<3>("h07"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_429 = and(_T_427, _T_428) @[axi4_to_ahb.scala 136:48] node _T_430 = mux(_T_429, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_431 = mux(_T_426, UInt<3>("h06"), _T_430) @[Mux.scala 98:16] node _T_432 = mux(_T_423, UInt<3>("h05"), _T_431) @[Mux.scala 98:16] @@ -960,268 +960,268 @@ circuit axi4_to_ahb : node _T_435 = mux(_T_414, UInt<2>("h02"), _T_434) @[Mux.scala 98:16] node _T_436 = mux(_T_411, UInt<1>("h01"), _T_435) @[Mux.scala 98:16] node _T_437 = mux(_T_408, UInt<1>("h00"), _T_436) @[Mux.scala 98:16] - node _T_438 = mux(trxn_done, _T_437, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 261:97] - node _T_439 = mux(bypass_en, _T_400, _T_438) @[axi4_to_ahb.scala 261:30] - buf_cmd_byte_ptr <= _T_439 @[axi4_to_ahb.scala 261:24] + node _T_438 = mux(trxn_done, _T_437, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 254:97] + node _T_439 = mux(bypass_en, _T_400, _T_438) @[axi4_to_ahb.scala 254:30] + buf_cmd_byte_ptr <= _T_439 @[axi4_to_ahb.scala 254:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_440 = eq(UInt<3>("h05"), buf_state) @[Conditional.scala 37:30] when _T_440 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 264:20] - buf_state_en <= slave_ready @[axi4_to_ahb.scala 265:20] - slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 266:23] - slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 267:23] + buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 257:20] + buf_state_en <= slave_ready @[axi4_to_ahb.scala 258:20] + slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 259:23] + slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 260:23] skip @[Conditional.scala 39:67] - cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 271:16] - node _T_441 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 272:33] - node _T_442 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 272:73] - node _T_443 = eq(_T_442, UInt<1>("h01")) @[axi4_to_ahb.scala 272:80] - node _T_444 = and(buf_aligned_in, _T_443) @[axi4_to_ahb.scala 272:60] - node _T_445 = bits(_T_444, 0, 0) @[axi4_to_ahb.scala 272:100] - node _T_446 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:132] - node _T_447 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 134:50] - node _T_448 = eq(_T_447, UInt<8>("h0ff")) @[axi4_to_ahb.scala 134:57] - node _T_449 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 134:81] - node _T_450 = eq(_T_449, UInt<8>("h0f")) @[axi4_to_ahb.scala 134:88] - node _T_451 = or(_T_448, _T_450) @[axi4_to_ahb.scala 134:70] - node _T_452 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 134:117] - node _T_453 = eq(_T_452, UInt<8>("h03")) @[axi4_to_ahb.scala 134:124] - node _T_454 = or(_T_451, _T_453) @[axi4_to_ahb.scala 134:106] + cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 264:16] + node _T_441 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 265:33] + node _T_442 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 265:73] + node _T_443 = eq(_T_442, UInt<1>("h01")) @[axi4_to_ahb.scala 265:80] + node _T_444 = and(buf_aligned_in, _T_443) @[axi4_to_ahb.scala 265:60] + node _T_445 = bits(_T_444, 0, 0) @[axi4_to_ahb.scala 265:100] + node _T_446 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 265:132] + node _T_447 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:50] + node _T_448 = eq(_T_447, UInt<8>("h0ff")) @[axi4_to_ahb.scala 127:57] + node _T_449 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:81] + node _T_450 = eq(_T_449, UInt<8>("h0f")) @[axi4_to_ahb.scala 127:88] + node _T_451 = or(_T_448, _T_450) @[axi4_to_ahb.scala 127:70] + node _T_452 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:117] + node _T_453 = eq(_T_452, UInt<8>("h03")) @[axi4_to_ahb.scala 127:124] + node _T_454 = or(_T_451, _T_453) @[axi4_to_ahb.scala 127:106] node _T_455 = bits(_T_454, 0, 0) @[Bitwise.scala 72:15] node _T_456 = mux(_T_455, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_457 = and(UInt<3>("h00"), _T_456) @[axi4_to_ahb.scala 134:29] - node _T_458 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 135:35] - node _T_459 = eq(_T_458, UInt<8>("h0c")) @[axi4_to_ahb.scala 135:42] + node _T_457 = and(UInt<3>("h00"), _T_456) @[axi4_to_ahb.scala 127:29] + node _T_458 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 128:35] + node _T_459 = eq(_T_458, UInt<8>("h0c")) @[axi4_to_ahb.scala 128:42] node _T_460 = bits(_T_459, 0, 0) @[Bitwise.scala 72:15] node _T_461 = mux(_T_460, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_462 = and(UInt<2>("h02"), _T_461) @[axi4_to_ahb.scala 135:15] - node _T_463 = or(_T_457, _T_462) @[axi4_to_ahb.scala 134:146] - node _T_464 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 136:36] - node _T_465 = eq(_T_464, UInt<8>("h0f0")) @[axi4_to_ahb.scala 136:43] - node _T_466 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 136:67] - node _T_467 = eq(_T_466, UInt<8>("h03")) @[axi4_to_ahb.scala 136:74] - node _T_468 = or(_T_465, _T_467) @[axi4_to_ahb.scala 136:56] + node _T_462 = and(UInt<2>("h02"), _T_461) @[axi4_to_ahb.scala 128:15] + node _T_463 = or(_T_457, _T_462) @[axi4_to_ahb.scala 127:146] + node _T_464 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 129:36] + node _T_465 = eq(_T_464, UInt<8>("h0f0")) @[axi4_to_ahb.scala 129:43] + node _T_466 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 129:67] + node _T_467 = eq(_T_466, UInt<8>("h03")) @[axi4_to_ahb.scala 129:74] + node _T_468 = or(_T_465, _T_467) @[axi4_to_ahb.scala 129:56] node _T_469 = bits(_T_468, 0, 0) @[Bitwise.scala 72:15] node _T_470 = mux(_T_469, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_471 = and(UInt<3>("h04"), _T_470) @[axi4_to_ahb.scala 136:15] - node _T_472 = or(_T_463, _T_471) @[axi4_to_ahb.scala 135:63] - node _T_473 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 137:35] - node _T_474 = eq(_T_473, UInt<8>("h0c0")) @[axi4_to_ahb.scala 137:42] + node _T_471 = and(UInt<3>("h04"), _T_470) @[axi4_to_ahb.scala 129:15] + node _T_472 = or(_T_463, _T_471) @[axi4_to_ahb.scala 128:63] + node _T_473 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 130:35] + node _T_474 = eq(_T_473, UInt<8>("h0c0")) @[axi4_to_ahb.scala 130:42] node _T_475 = bits(_T_474, 0, 0) @[Bitwise.scala 72:15] node _T_476 = mux(_T_475, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_477 = and(UInt<3>("h06"), _T_476) @[axi4_to_ahb.scala 137:15] - node _T_478 = or(_T_472, _T_477) @[axi4_to_ahb.scala 136:96] - node _T_479 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 138:33] - node _T_480 = eq(_T_479, UInt<8>("h0c0")) @[axi4_to_ahb.scala 138:40] + node _T_477 = and(UInt<3>("h06"), _T_476) @[axi4_to_ahb.scala 130:15] + node _T_478 = or(_T_472, _T_477) @[axi4_to_ahb.scala 129:96] + node _T_479 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 131:33] + node _T_480 = eq(_T_479, UInt<8>("h0c0")) @[axi4_to_ahb.scala 131:40] node _T_481 = bits(_T_480, 0, 0) @[Bitwise.scala 72:15] node _T_482 = mux(_T_481, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_483 = and(UInt<3>("h06"), _T_482) @[axi4_to_ahb.scala 138:13] - node _T_484 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 272:152] - node _T_485 = mux(_T_445, _T_478, _T_484) @[axi4_to_ahb.scala 272:43] + node _T_483 = and(UInt<3>("h06"), _T_482) @[axi4_to_ahb.scala 131:13] + node _T_484 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 265:152] + node _T_485 = mux(_T_445, _T_478, _T_484) @[axi4_to_ahb.scala 265:43] node _T_486 = cat(_T_441, _T_485) @[Cat.scala 29:58] - buf_addr_in <= _T_486 @[axi4_to_ahb.scala 272:15] - node _T_487 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 273:27] - buf_tag_in <= _T_487 @[axi4_to_ahb.scala 273:14] - node _T_488 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 274:32] - buf_byteen_in <= _T_488 @[axi4_to_ahb.scala 274:17] - node _T_489 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 275:33] - node _T_490 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 275:59] - node _T_491 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 275:80] - node _T_492 = mux(_T_489, _T_490, _T_491) @[axi4_to_ahb.scala 275:21] - buf_data_in <= _T_492 @[axi4_to_ahb.scala 275:15] - node _T_493 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 276:52] - node _T_494 = eq(_T_493, UInt<2>("h03")) @[axi4_to_ahb.scala 276:58] - node _T_495 = and(buf_aligned_in, _T_494) @[axi4_to_ahb.scala 276:38] - node _T_496 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 276:84] - node _T_497 = eq(_T_496, UInt<1>("h01")) @[axi4_to_ahb.scala 276:91] - node _T_498 = and(_T_495, _T_497) @[axi4_to_ahb.scala 276:71] - node _T_499 = bits(_T_498, 0, 0) @[axi4_to_ahb.scala 276:111] - node _T_500 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 276:142] - node _T_501 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 128:42] - node _T_502 = eq(_T_501, UInt<8>("h0ff")) @[axi4_to_ahb.scala 128:49] + buf_addr_in <= _T_486 @[axi4_to_ahb.scala 265:15] + node _T_487 = bits(master_tag, 2, 0) @[axi4_to_ahb.scala 266:27] + buf_tag_in <= _T_487 @[axi4_to_ahb.scala 266:14] + node _T_488 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 267:32] + buf_byteen_in <= _T_488 @[axi4_to_ahb.scala 267:17] + node _T_489 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 268:33] + node _T_490 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 268:59] + node _T_491 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 268:80] + node _T_492 = mux(_T_489, _T_490, _T_491) @[axi4_to_ahb.scala 268:21] + buf_data_in <= _T_492 @[axi4_to_ahb.scala 268:15] + node _T_493 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 269:52] + node _T_494 = eq(_T_493, UInt<2>("h03")) @[axi4_to_ahb.scala 269:58] + node _T_495 = and(buf_aligned_in, _T_494) @[axi4_to_ahb.scala 269:38] + node _T_496 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 269:84] + node _T_497 = eq(_T_496, UInt<1>("h01")) @[axi4_to_ahb.scala 269:91] + node _T_498 = and(_T_495, _T_497) @[axi4_to_ahb.scala 269:71] + node _T_499 = bits(_T_498, 0, 0) @[axi4_to_ahb.scala 269:111] + node _T_500 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 269:142] + node _T_501 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 121:42] + node _T_502 = eq(_T_501, UInt<8>("h0ff")) @[axi4_to_ahb.scala 121:49] node _T_503 = bits(_T_502, 0, 0) @[Bitwise.scala 72:15] node _T_504 = mux(_T_503, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_505 = and(UInt<2>("h03"), _T_504) @[axi4_to_ahb.scala 128:25] - node _T_506 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 129:35] - node _T_507 = eq(_T_506, UInt<8>("h0f0")) @[axi4_to_ahb.scala 129:42] - node _T_508 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 129:64] - node _T_509 = eq(_T_508, UInt<8>("h0f")) @[axi4_to_ahb.scala 129:71] - node _T_510 = or(_T_507, _T_509) @[axi4_to_ahb.scala 129:55] + node _T_505 = and(UInt<2>("h03"), _T_504) @[axi4_to_ahb.scala 121:25] + node _T_506 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 122:35] + node _T_507 = eq(_T_506, UInt<8>("h0f0")) @[axi4_to_ahb.scala 122:42] + node _T_508 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 122:64] + node _T_509 = eq(_T_508, UInt<8>("h0f")) @[axi4_to_ahb.scala 122:71] + node _T_510 = or(_T_507, _T_509) @[axi4_to_ahb.scala 122:55] node _T_511 = bits(_T_510, 0, 0) @[Bitwise.scala 72:15] node _T_512 = mux(_T_511, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_513 = and(UInt<2>("h02"), _T_512) @[axi4_to_ahb.scala 129:16] - node _T_514 = or(_T_505, _T_513) @[axi4_to_ahb.scala 128:64] - node _T_515 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 130:40] - node _T_516 = eq(_T_515, UInt<8>("h0c0")) @[axi4_to_ahb.scala 130:47] - node _T_517 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 130:69] - node _T_518 = eq(_T_517, UInt<6>("h030")) @[axi4_to_ahb.scala 130:76] - node _T_519 = or(_T_516, _T_518) @[axi4_to_ahb.scala 130:60] - node _T_520 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 130:98] - node _T_521 = eq(_T_520, UInt<8>("h0c")) @[axi4_to_ahb.scala 130:105] - node _T_522 = or(_T_519, _T_521) @[axi4_to_ahb.scala 130:89] - node _T_523 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 130:132] - node _T_524 = eq(_T_523, UInt<8>("h03")) @[axi4_to_ahb.scala 130:139] - node _T_525 = or(_T_522, _T_524) @[axi4_to_ahb.scala 130:123] + node _T_513 = and(UInt<2>("h02"), _T_512) @[axi4_to_ahb.scala 122:16] + node _T_514 = or(_T_505, _T_513) @[axi4_to_ahb.scala 121:64] + node _T_515 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:40] + node _T_516 = eq(_T_515, UInt<8>("h0c0")) @[axi4_to_ahb.scala 123:47] + node _T_517 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:69] + node _T_518 = eq(_T_517, UInt<6>("h030")) @[axi4_to_ahb.scala 123:76] + node _T_519 = or(_T_516, _T_518) @[axi4_to_ahb.scala 123:60] + node _T_520 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:98] + node _T_521 = eq(_T_520, UInt<8>("h0c")) @[axi4_to_ahb.scala 123:105] + node _T_522 = or(_T_519, _T_521) @[axi4_to_ahb.scala 123:89] + node _T_523 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:132] + node _T_524 = eq(_T_523, UInt<8>("h03")) @[axi4_to_ahb.scala 123:139] + node _T_525 = or(_T_522, _T_524) @[axi4_to_ahb.scala 123:123] node _T_526 = bits(_T_525, 0, 0) @[Bitwise.scala 72:15] node _T_527 = mux(_T_526, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_528 = and(UInt<2>("h01"), _T_527) @[axi4_to_ahb.scala 130:21] - node _T_529 = or(_T_514, _T_528) @[axi4_to_ahb.scala 129:93] - node _T_530 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 276:161] - node _T_531 = mux(_T_499, _T_529, _T_530) @[axi4_to_ahb.scala 276:21] - buf_size_in <= _T_531 @[axi4_to_ahb.scala 276:15] - node _T_532 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 277:32] - node _T_533 = eq(_T_532, UInt<1>("h00")) @[axi4_to_ahb.scala 277:39] - node _T_534 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 278:17] - node _T_535 = eq(_T_534, UInt<1>("h00")) @[axi4_to_ahb.scala 278:24] - node _T_536 = or(_T_533, _T_535) @[axi4_to_ahb.scala 277:48] - node _T_537 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 278:47] - node _T_538 = eq(_T_537, UInt<2>("h01")) @[axi4_to_ahb.scala 278:54] - node _T_539 = or(_T_536, _T_538) @[axi4_to_ahb.scala 278:33] - node _T_540 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 278:86] - node _T_541 = eq(_T_540, UInt<2>("h02")) @[axi4_to_ahb.scala 278:93] - node _T_542 = or(_T_539, _T_541) @[axi4_to_ahb.scala 278:72] - node _T_543 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 279:18] - node _T_544 = eq(_T_543, UInt<2>("h03")) @[axi4_to_ahb.scala 279:25] - node _T_545 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 279:55] - node _T_546 = eq(_T_545, UInt<2>("h03")) @[axi4_to_ahb.scala 279:62] - node _T_547 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 279:90] - node _T_548 = eq(_T_547, UInt<4>("h0c")) @[axi4_to_ahb.scala 279:97] - node _T_549 = or(_T_546, _T_548) @[axi4_to_ahb.scala 279:74] - node _T_550 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 279:125] - node _T_551 = eq(_T_550, UInt<6>("h030")) @[axi4_to_ahb.scala 279:132] - node _T_552 = or(_T_549, _T_551) @[axi4_to_ahb.scala 279:109] - node _T_553 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 279:161] - node _T_554 = eq(_T_553, UInt<8>("h0c0")) @[axi4_to_ahb.scala 279:168] - node _T_555 = or(_T_552, _T_554) @[axi4_to_ahb.scala 279:145] - node _T_556 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 280:21] - node _T_557 = eq(_T_556, UInt<4>("h0f")) @[axi4_to_ahb.scala 280:28] - node _T_558 = or(_T_555, _T_557) @[axi4_to_ahb.scala 279:181] - node _T_559 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 280:56] - node _T_560 = eq(_T_559, UInt<8>("h0f0")) @[axi4_to_ahb.scala 280:63] - node _T_561 = or(_T_558, _T_560) @[axi4_to_ahb.scala 280:40] - node _T_562 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 280:92] - node _T_563 = eq(_T_562, UInt<8>("h0ff")) @[axi4_to_ahb.scala 280:99] - node _T_564 = or(_T_561, _T_563) @[axi4_to_ahb.scala 280:76] - node _T_565 = and(_T_544, _T_564) @[axi4_to_ahb.scala 279:38] - node _T_566 = or(_T_542, _T_565) @[axi4_to_ahb.scala 278:106] - buf_aligned_in <= _T_566 @[axi4_to_ahb.scala 277:18] - node _T_567 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 282:43] - node _T_568 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 282:62] - node _T_569 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 282:87] + node _T_528 = and(UInt<2>("h01"), _T_527) @[axi4_to_ahb.scala 123:21] + node _T_529 = or(_T_514, _T_528) @[axi4_to_ahb.scala 122:93] + node _T_530 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 269:161] + node _T_531 = mux(_T_499, _T_529, _T_530) @[axi4_to_ahb.scala 269:21] + buf_size_in <= _T_531 @[axi4_to_ahb.scala 269:15] + node _T_532 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 270:32] + node _T_533 = eq(_T_532, UInt<1>("h00")) @[axi4_to_ahb.scala 270:39] + node _T_534 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 271:17] + node _T_535 = eq(_T_534, UInt<1>("h00")) @[axi4_to_ahb.scala 271:24] + node _T_536 = or(_T_533, _T_535) @[axi4_to_ahb.scala 270:48] + node _T_537 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 271:47] + node _T_538 = eq(_T_537, UInt<2>("h01")) @[axi4_to_ahb.scala 271:54] + node _T_539 = or(_T_536, _T_538) @[axi4_to_ahb.scala 271:33] + node _T_540 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 271:86] + node _T_541 = eq(_T_540, UInt<2>("h02")) @[axi4_to_ahb.scala 271:93] + node _T_542 = or(_T_539, _T_541) @[axi4_to_ahb.scala 271:72] + node _T_543 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 272:18] + node _T_544 = eq(_T_543, UInt<2>("h03")) @[axi4_to_ahb.scala 272:25] + node _T_545 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:55] + node _T_546 = eq(_T_545, UInt<2>("h03")) @[axi4_to_ahb.scala 272:62] + node _T_547 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:90] + node _T_548 = eq(_T_547, UInt<4>("h0c")) @[axi4_to_ahb.scala 272:97] + node _T_549 = or(_T_546, _T_548) @[axi4_to_ahb.scala 272:74] + node _T_550 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:125] + node _T_551 = eq(_T_550, UInt<6>("h030")) @[axi4_to_ahb.scala 272:132] + node _T_552 = or(_T_549, _T_551) @[axi4_to_ahb.scala 272:109] + node _T_553 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:161] + node _T_554 = eq(_T_553, UInt<8>("h0c0")) @[axi4_to_ahb.scala 272:168] + node _T_555 = or(_T_552, _T_554) @[axi4_to_ahb.scala 272:145] + node _T_556 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 273:21] + node _T_557 = eq(_T_556, UInt<4>("h0f")) @[axi4_to_ahb.scala 273:28] + node _T_558 = or(_T_555, _T_557) @[axi4_to_ahb.scala 272:181] + node _T_559 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 273:56] + node _T_560 = eq(_T_559, UInt<8>("h0f0")) @[axi4_to_ahb.scala 273:63] + node _T_561 = or(_T_558, _T_560) @[axi4_to_ahb.scala 273:40] + node _T_562 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 273:92] + node _T_563 = eq(_T_562, UInt<8>("h0ff")) @[axi4_to_ahb.scala 273:99] + node _T_564 = or(_T_561, _T_563) @[axi4_to_ahb.scala 273:76] + node _T_565 = and(_T_544, _T_564) @[axi4_to_ahb.scala 272:38] + node _T_566 = or(_T_542, _T_565) @[axi4_to_ahb.scala 271:106] + buf_aligned_in <= _T_566 @[axi4_to_ahb.scala 270:18] + node _T_567 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 275:43] + node _T_568 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 275:62] + node _T_569 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 275:87] node _T_570 = cat(_T_568, _T_569) @[Cat.scala 29:58] - node _T_571 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 282:108] - node _T_572 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 282:133] + node _T_571 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 275:108] + node _T_572 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 275:133] node _T_573 = cat(_T_571, _T_572) @[Cat.scala 29:58] - node _T_574 = mux(_T_567, _T_570, _T_573) @[axi4_to_ahb.scala 282:26] - io.ahb.out.haddr <= _T_574 @[axi4_to_ahb.scala 282:20] - node _T_575 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 283:43] + node _T_574 = mux(_T_567, _T_570, _T_573) @[axi4_to_ahb.scala 275:26] + io.ahb.out.haddr <= _T_574 @[axi4_to_ahb.scala 275:20] + node _T_575 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 276:43] node _T_576 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15] node _T_577 = mux(_T_576, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_578 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 283:94] - node _T_579 = and(_T_577, _T_578) @[axi4_to_ahb.scala 283:81] + node _T_578 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 276:94] + node _T_579 = and(_T_577, _T_578) @[axi4_to_ahb.scala 276:81] node _T_580 = cat(UInt<1>("h00"), _T_579) @[Cat.scala 29:58] node _T_581 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15] node _T_582 = mux(_T_581, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_583 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 283:148] - node _T_584 = and(_T_582, _T_583) @[axi4_to_ahb.scala 283:138] + node _T_583 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 276:148] + node _T_584 = and(_T_582, _T_583) @[axi4_to_ahb.scala 276:138] node _T_585 = cat(UInt<1>("h00"), _T_584) @[Cat.scala 29:58] - node _T_586 = mux(_T_575, _T_580, _T_585) @[axi4_to_ahb.scala 283:26] - io.ahb.out.hsize <= _T_586 @[axi4_to_ahb.scala 283:20] - io.ahb.out.hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 285:21] - io.ahb.out.hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 286:24] - node _T_587 = bits(io.axi.ar.bits.prot, 2, 2) @[axi4_to_ahb.scala 287:57] - node _T_588 = eq(_T_587, UInt<1>("h00")) @[axi4_to_ahb.scala 287:37] + node _T_586 = mux(_T_575, _T_580, _T_585) @[axi4_to_ahb.scala 276:26] + io.ahb.out.hsize <= _T_586 @[axi4_to_ahb.scala 276:20] + io.ahb.out.hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 278:21] + io.ahb.out.hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 279:24] + node _T_587 = bits(io.axi.ar.bits.prot, 2, 2) @[axi4_to_ahb.scala 280:57] + node _T_588 = eq(_T_587, UInt<1>("h00")) @[axi4_to_ahb.scala 280:37] node _T_589 = cat(UInt<1>("h01"), _T_588) @[Cat.scala 29:58] - io.ahb.out.hprot <= _T_589 @[axi4_to_ahb.scala 287:20] - node _T_590 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 288:44] - node _T_591 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 288:59] - node _T_592 = eq(_T_591, UInt<1>("h01")) @[axi4_to_ahb.scala 288:66] - node _T_593 = mux(_T_590, _T_592, buf_write) @[axi4_to_ahb.scala 288:27] - io.ahb.out.hwrite <= _T_593 @[axi4_to_ahb.scala 288:21] - node _T_594 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 289:32] - io.ahb.out.hwdata <= _T_594 @[axi4_to_ahb.scala 289:21] - slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 291:15] - node _T_595 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 292:43] - node _T_596 = mux(_T_595, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 292:23] + io.ahb.out.hprot <= _T_589 @[axi4_to_ahb.scala 280:20] + node _T_590 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 281:44] + node _T_591 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 281:59] + node _T_592 = eq(_T_591, UInt<1>("h01")) @[axi4_to_ahb.scala 281:66] + node _T_593 = mux(_T_590, _T_592, buf_write) @[axi4_to_ahb.scala 281:27] + io.ahb.out.hwrite <= _T_593 @[axi4_to_ahb.scala 281:21] + node _T_594 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 282:32] + io.ahb.out.hwdata <= _T_594 @[axi4_to_ahb.scala 282:21] + slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 284:15] + node _T_595 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 285:43] + node _T_596 = mux(_T_595, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 285:23] node _T_597 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15] node _T_598 = mux(_T_597, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_599 = and(_T_598, UInt<2>("h02")) @[axi4_to_ahb.scala 292:88] + node _T_599 = and(_T_598, UInt<2>("h02")) @[axi4_to_ahb.scala 285:88] node _T_600 = cat(_T_596, _T_599) @[Cat.scala 29:58] - slave_opc <= _T_600 @[axi4_to_ahb.scala 292:13] - node _T_601 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 293:41] - node _T_602 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 293:66] + slave_opc <= _T_600 @[axi4_to_ahb.scala 285:13] + node _T_601 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 286:41] + node _T_602 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 286:66] node _T_603 = cat(_T_602, _T_602) @[Cat.scala 29:58] - node _T_604 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 293:91] - node _T_605 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 293:110] - node _T_606 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 293:131] - node _T_607 = mux(_T_604, _T_605, _T_606) @[axi4_to_ahb.scala 293:79] - node _T_608 = mux(_T_601, _T_603, _T_607) @[axi4_to_ahb.scala 293:21] - slave_rdata <= _T_608 @[axi4_to_ahb.scala 293:15] - node _T_609 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 294:26] - slave_tag <= _T_609 @[axi4_to_ahb.scala 294:13] - node _T_610 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 296:37] - node _T_611 = neq(_T_610, UInt<1>("h00")) @[axi4_to_ahb.scala 296:44] - node _T_612 = and(_T_611, io.ahb.in.hready) @[axi4_to_ahb.scala 296:56] - node _T_613 = and(_T_612, io.ahb.out.hwrite) @[axi4_to_ahb.scala 296:75] - last_addr_en <= _T_613 @[axi4_to_ahb.scala 296:16] - node _T_614 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 298:31] - node _T_615 = and(_T_614, master_ready) @[axi4_to_ahb.scala 298:49] - wrbuf_en <= _T_615 @[axi4_to_ahb.scala 298:12] - node _T_616 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 299:35] - node _T_617 = and(_T_616, master_ready) @[axi4_to_ahb.scala 299:52] - wrbuf_data_en <= _T_617 @[axi4_to_ahb.scala 299:17] - node _T_618 = and(master_valid, master_ready) @[axi4_to_ahb.scala 300:34] - node _T_619 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 300:62] - node _T_620 = eq(_T_619, UInt<1>("h01")) @[axi4_to_ahb.scala 300:69] - node _T_621 = and(_T_618, _T_620) @[axi4_to_ahb.scala 300:49] - wrbuf_cmd_sent <= _T_621 @[axi4_to_ahb.scala 300:18] - node _T_622 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 301:33] - node _T_623 = and(wrbuf_cmd_sent, _T_622) @[axi4_to_ahb.scala 301:31] - wrbuf_rst <= _T_623 @[axi4_to_ahb.scala 301:13] - node _T_624 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 303:36] - node _T_625 = and(wrbuf_vld, _T_624) @[axi4_to_ahb.scala 303:34] - node _T_626 = eq(_T_625, UInt<1>("h00")) @[axi4_to_ahb.scala 303:22] - node _T_627 = and(_T_626, master_ready) @[axi4_to_ahb.scala 303:53] - io.axi.aw.ready <= _T_627 @[axi4_to_ahb.scala 303:19] - node _T_628 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 304:40] - node _T_629 = and(wrbuf_data_vld, _T_628) @[axi4_to_ahb.scala 304:38] - node _T_630 = eq(_T_629, UInt<1>("h00")) @[axi4_to_ahb.scala 304:21] - node _T_631 = and(_T_630, master_ready) @[axi4_to_ahb.scala 304:57] - io.axi.w.ready <= _T_631 @[axi4_to_ahb.scala 304:18] - node _T_632 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 305:34] - node _T_633 = eq(_T_632, UInt<1>("h00")) @[axi4_to_ahb.scala 305:22] - node _T_634 = and(_T_633, master_ready) @[axi4_to_ahb.scala 305:52] - io.axi.ar.ready <= _T_634 @[axi4_to_ahb.scala 305:19] - io.axi.r.bits.last <= UInt<1>("h01") @[axi4_to_ahb.scala 306:22] - node _T_635 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 308:71] - node _T_636 = mux(_T_635, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 308:55] - node _T_637 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 308:91] - node _T_638 = and(_T_636, _T_637) @[axi4_to_ahb.scala 308:89] - reg _T_639 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 308:51] - _T_639 <= _T_638 @[axi4_to_ahb.scala 308:51] - wrbuf_vld <= _T_639 @[axi4_to_ahb.scala 308:21] - node _T_640 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 309:76] - node _T_641 = mux(_T_640, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 309:55] - node _T_642 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 309:102] - node _T_643 = and(_T_641, _T_642) @[axi4_to_ahb.scala 309:100] - reg _T_644 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 309:51] - _T_644 <= _T_643 @[axi4_to_ahb.scala 309:51] - wrbuf_data_vld <= _T_644 @[axi4_to_ahb.scala 309:21] - node _T_645 = bits(io.axi.aw.bits.id, 0, 0) @[axi4_to_ahb.scala 310:71] - node _T_646 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 310:105] + node _T_604 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 286:91] + node _T_605 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 286:110] + node _T_606 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 286:131] + node _T_607 = mux(_T_604, _T_605, _T_606) @[axi4_to_ahb.scala 286:79] + node _T_608 = mux(_T_601, _T_603, _T_607) @[axi4_to_ahb.scala 286:21] + slave_rdata <= _T_608 @[axi4_to_ahb.scala 286:15] + node _T_609 = bits(slvbuf_tag, 2, 0) @[axi4_to_ahb.scala 287:26] + slave_tag <= _T_609 @[axi4_to_ahb.scala 287:13] + node _T_610 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 289:37] + node _T_611 = neq(_T_610, UInt<1>("h00")) @[axi4_to_ahb.scala 289:44] + node _T_612 = and(_T_611, io.ahb.in.hready) @[axi4_to_ahb.scala 289:56] + node _T_613 = and(_T_612, io.ahb.out.hwrite) @[axi4_to_ahb.scala 289:75] + last_addr_en <= _T_613 @[axi4_to_ahb.scala 289:16] + node _T_614 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 291:31] + node _T_615 = and(_T_614, master_ready) @[axi4_to_ahb.scala 291:49] + wrbuf_en <= _T_615 @[axi4_to_ahb.scala 291:12] + node _T_616 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 292:35] + node _T_617 = and(_T_616, master_ready) @[axi4_to_ahb.scala 292:52] + wrbuf_data_en <= _T_617 @[axi4_to_ahb.scala 292:17] + node _T_618 = and(master_valid, master_ready) @[axi4_to_ahb.scala 293:34] + node _T_619 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 293:62] + node _T_620 = eq(_T_619, UInt<1>("h01")) @[axi4_to_ahb.scala 293:69] + node _T_621 = and(_T_618, _T_620) @[axi4_to_ahb.scala 293:49] + wrbuf_cmd_sent <= _T_621 @[axi4_to_ahb.scala 293:18] + node _T_622 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 294:33] + node _T_623 = and(wrbuf_cmd_sent, _T_622) @[axi4_to_ahb.scala 294:31] + wrbuf_rst <= _T_623 @[axi4_to_ahb.scala 294:13] + node _T_624 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 296:36] + node _T_625 = and(wrbuf_vld, _T_624) @[axi4_to_ahb.scala 296:34] + node _T_626 = eq(_T_625, UInt<1>("h00")) @[axi4_to_ahb.scala 296:22] + node _T_627 = and(_T_626, master_ready) @[axi4_to_ahb.scala 296:53] + io.axi.aw.ready <= _T_627 @[axi4_to_ahb.scala 296:19] + node _T_628 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 297:40] + node _T_629 = and(wrbuf_data_vld, _T_628) @[axi4_to_ahb.scala 297:38] + node _T_630 = eq(_T_629, UInt<1>("h00")) @[axi4_to_ahb.scala 297:21] + node _T_631 = and(_T_630, master_ready) @[axi4_to_ahb.scala 297:57] + io.axi.w.ready <= _T_631 @[axi4_to_ahb.scala 297:18] + node _T_632 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 298:34] + node _T_633 = eq(_T_632, UInt<1>("h00")) @[axi4_to_ahb.scala 298:22] + node _T_634 = and(_T_633, master_ready) @[axi4_to_ahb.scala 298:52] + io.axi.ar.ready <= _T_634 @[axi4_to_ahb.scala 298:19] + io.axi.r.bits.last <= UInt<1>("h01") @[axi4_to_ahb.scala 299:22] + node _T_635 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 301:71] + node _T_636 = mux(_T_635, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 301:55] + node _T_637 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 301:91] + node _T_638 = and(_T_636, _T_637) @[axi4_to_ahb.scala 301:89] + reg _T_639 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 301:51] + _T_639 <= _T_638 @[axi4_to_ahb.scala 301:51] + wrbuf_vld <= _T_639 @[axi4_to_ahb.scala 301:21] + node _T_640 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 302:76] + node _T_641 = mux(_T_640, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 302:55] + node _T_642 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 302:102] + node _T_643 = and(_T_641, _T_642) @[axi4_to_ahb.scala 302:100] + reg _T_644 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 302:51] + _T_644 <= _T_643 @[axi4_to_ahb.scala 302:51] + wrbuf_data_vld <= _T_644 @[axi4_to_ahb.scala 302:21] + node _T_645 = bits(io.axi.aw.bits.id, 2, 0) @[axi4_to_ahb.scala 303:71] + node _T_646 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 303:105] reg _T_647 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_646 : @[Reg.scala 28:19] _T_647 <= _T_645 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_tag <= _T_647 @[axi4_to_ahb.scala 310:21] - node _T_648 = bits(io.axi.aw.bits.size, 2, 0) @[axi4_to_ahb.scala 311:73] - node _T_649 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 311:101] + wrbuf_tag <= _T_647 @[axi4_to_ahb.scala 303:21] + node _T_648 = bits(io.axi.aw.bits.size, 2, 0) @[axi4_to_ahb.scala 304:73] + node _T_649 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 304:101] reg _T_650 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_649 : @[Reg.scala 28:19] _T_650 <= _T_648 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_size <= _T_650 @[axi4_to_ahb.scala 311:21] - node _T_651 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 312:61] + wrbuf_size <= _T_650 @[axi4_to_ahb.scala 304:21] + node _T_651 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 305:61] inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 368:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset @@ -1230,8 +1230,8 @@ circuit axi4_to_ahb : rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_652 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_652 <= io.axi.aw.bits.addr @[lib.scala 374:16] - wrbuf_addr <= _T_652 @[axi4_to_ahb.scala 312:21] - node _T_653 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 313:65] + wrbuf_addr <= _T_652 @[axi4_to_ahb.scala 305:21] + node _T_653 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 306:65] inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 368:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset @@ -1240,37 +1240,37 @@ circuit axi4_to_ahb : rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_654 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_654 <= io.axi.w.bits.data @[lib.scala 374:16] - wrbuf_data <= _T_654 @[axi4_to_ahb.scala 313:21] - node _T_655 = bits(io.axi.w.bits.strb, 7, 0) @[axi4_to_ahb.scala 314:72] - node _T_656 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 314:105] + wrbuf_data <= _T_654 @[axi4_to_ahb.scala 306:21] + node _T_655 = bits(io.axi.w.bits.strb, 7, 0) @[axi4_to_ahb.scala 307:72] + node _T_656 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 307:105] reg _T_657 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_656 : @[Reg.scala 28:19] _T_657 <= _T_655 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_byteen <= _T_657 @[axi4_to_ahb.scala 314:21] - node _T_658 = bits(io.ahb.out.haddr, 31, 0) @[axi4_to_ahb.scala 315:71] - node _T_659 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 315:104] + wrbuf_byteen <= _T_657 @[axi4_to_ahb.scala 307:21] + node _T_658 = bits(io.ahb.out.haddr, 31, 0) @[axi4_to_ahb.scala 308:71] + node _T_659 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 308:104] reg _T_660 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_659 : @[Reg.scala 28:19] _T_660 <= _T_658 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - last_bus_addr <= _T_660 @[axi4_to_ahb.scala 315:21] - node _T_661 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 316:89] + last_bus_addr <= _T_660 @[axi4_to_ahb.scala 308:21] + node _T_661 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 309:89] reg _T_662 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_661 : @[Reg.scala 28:19] _T_662 <= buf_write_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_write <= _T_662 @[axi4_to_ahb.scala 316:21] - node _T_663 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 317:64] - node _T_664 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 317:99] + buf_write <= _T_662 @[axi4_to_ahb.scala 309:21] + node _T_663 = bits(buf_tag_in, 2, 0) @[axi4_to_ahb.scala 310:64] + node _T_664 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 310:99] reg _T_665 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_664 : @[Reg.scala 28:19] _T_665 <= _T_663 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_tag <= _T_665 @[axi4_to_ahb.scala 317:21] - node _T_666 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 318:42] - node _T_667 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 318:61] - node _T_668 = bits(_T_667, 0, 0) @[axi4_to_ahb.scala 318:78] + buf_tag <= _T_665 @[axi4_to_ahb.scala 310:21] + node _T_666 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 311:42] + node _T_667 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 311:61] + node _T_668 = bits(_T_667, 0, 0) @[axi4_to_ahb.scala 311:78] inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 368:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset @@ -1279,30 +1279,30 @@ circuit axi4_to_ahb : rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_669 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_669 <= _T_666 @[lib.scala 374:16] - buf_addr <= _T_669 @[axi4_to_ahb.scala 318:21] - node _T_670 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 319:65] - node _T_671 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 319:94] + buf_addr <= _T_669 @[axi4_to_ahb.scala 311:21] + node _T_670 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 312:65] + node _T_671 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 312:94] reg _T_672 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_671 : @[Reg.scala 28:19] _T_672 <= _T_670 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_size <= _T_672 @[axi4_to_ahb.scala 319:21] - node _T_673 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 320:91] + buf_size <= _T_672 @[axi4_to_ahb.scala 312:21] + node _T_673 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 313:91] reg _T_674 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_673 : @[Reg.scala 28:19] _T_674 <= buf_aligned_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_aligned <= _T_674 @[axi4_to_ahb.scala 320:21] - node _T_675 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 321:67] - node _T_676 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 321:96] + buf_aligned <= _T_674 @[axi4_to_ahb.scala 313:21] + node _T_675 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 314:67] + node _T_676 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 314:96] reg _T_677 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_676 : @[Reg.scala 28:19] _T_677 <= _T_675 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_byteen <= _T_677 @[axi4_to_ahb.scala 321:21] - node _T_678 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 322:42] - node _T_679 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 322:66] - node _T_680 = bits(_T_679, 0, 0) @[axi4_to_ahb.scala 322:89] + buf_byteen <= _T_677 @[axi4_to_ahb.scala 314:21] + node _T_678 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 315:42] + node _T_679 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 315:66] + node _T_680 = bits(_T_679, 0, 0) @[axi4_to_ahb.scala 315:89] inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 368:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset @@ -1311,96 +1311,96 @@ circuit axi4_to_ahb : rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_681 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_681 <= _T_678 @[lib.scala 374:16] - buf_data <= _T_681 @[axi4_to_ahb.scala 322:21] - node _T_682 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 323:89] + buf_data <= _T_681 @[axi4_to_ahb.scala 315:21] + node _T_682 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 316:89] reg _T_683 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_682 : @[Reg.scala 28:19] _T_683 <= buf_write @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_write <= _T_683 @[axi4_to_ahb.scala 323:21] - node _T_684 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 324:61] - node _T_685 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 324:99] + slvbuf_write <= _T_683 @[axi4_to_ahb.scala 316:21] + node _T_684 = bits(buf_tag, 2, 0) @[axi4_to_ahb.scala 317:61] + node _T_685 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 317:99] reg _T_686 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_685 : @[Reg.scala 28:19] _T_686 <= _T_684 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_tag <= _T_686 @[axi4_to_ahb.scala 324:21] - node _T_687 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 325:99] + slvbuf_tag <= _T_686 @[axi4_to_ahb.scala 317:21] + node _T_687 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 318:99] reg _T_688 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_687 : @[Reg.scala 28:19] _T_688 <= slvbuf_error_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_error <= _T_688 @[axi4_to_ahb.scala 325:21] - node _T_689 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 326:72] - node _T_690 = mux(_T_689, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 326:56] - node _T_691 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 326:92] - node _T_692 = and(_T_690, _T_691) @[axi4_to_ahb.scala 326:90] - reg _T_693 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 326:52] - _T_693 <= _T_692 @[axi4_to_ahb.scala 326:52] - cmd_doneQ <= _T_693 @[axi4_to_ahb.scala 326:21] - node _T_694 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 327:71] - node _T_695 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 327:110] + slvbuf_error <= _T_688 @[axi4_to_ahb.scala 318:21] + node _T_689 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 319:72] + node _T_690 = mux(_T_689, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 319:56] + node _T_691 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 319:92] + node _T_692 = and(_T_690, _T_691) @[axi4_to_ahb.scala 319:90] + reg _T_693 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 319:52] + _T_693 <= _T_692 @[axi4_to_ahb.scala 319:52] + cmd_doneQ <= _T_693 @[axi4_to_ahb.scala 319:21] + node _T_694 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 320:71] + node _T_695 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 320:110] reg _T_696 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_695 : @[Reg.scala 28:19] _T_696 <= _T_694 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_cmd_byte_ptrQ <= _T_696 @[axi4_to_ahb.scala 327:21] - reg _T_697 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 328:52] - _T_697 <= io.ahb.in.hready @[axi4_to_ahb.scala 328:52] - ahb_hready_q <= _T_697 @[axi4_to_ahb.scala 328:21] - node _T_698 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 329:70] - reg _T_699 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 329:52] - _T_699 <= _T_698 @[axi4_to_ahb.scala 329:52] - ahb_htrans_q <= _T_699 @[axi4_to_ahb.scala 329:21] - reg _T_700 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 330:57] - _T_700 <= io.ahb.out.hwrite @[axi4_to_ahb.scala 330:57] - ahb_hwrite_q <= _T_700 @[axi4_to_ahb.scala 330:21] - reg _T_701 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 331:52] - _T_701 <= io.ahb.in.hresp @[axi4_to_ahb.scala 331:52] - ahb_hresp_q <= _T_701 @[axi4_to_ahb.scala 331:21] - node _T_702 = bits(io.ahb.in.hrdata, 63, 0) @[axi4_to_ahb.scala 332:74] - reg _T_703 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 332:57] - _T_703 <= _T_702 @[axi4_to_ahb.scala 332:57] - ahb_hrdata_q <= _T_703 @[axi4_to_ahb.scala 332:21] - node _T_704 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 334:43] - node _T_705 = or(_T_704, io.clk_override) @[axi4_to_ahb.scala 334:58] - node _T_706 = and(io.bus_clk_en, _T_705) @[axi4_to_ahb.scala 334:30] - buf_clken <= _T_706 @[axi4_to_ahb.scala 334:13] - node _T_707 = bits(io.ahb.out.htrans, 1, 1) @[axi4_to_ahb.scala 335:76] - node _T_708 = and(io.ahb.in.hready, _T_707) @[axi4_to_ahb.scala 335:57] - node _T_709 = or(_T_708, io.clk_override) @[axi4_to_ahb.scala 335:81] - node _T_710 = and(io.bus_clk_en, _T_709) @[axi4_to_ahb.scala 335:36] - ahbm_addr_clken <= _T_710 @[axi4_to_ahb.scala 335:19] - node _T_711 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 336:50] - node _T_712 = or(_T_711, io.clk_override) @[axi4_to_ahb.scala 336:60] - node _T_713 = and(io.bus_clk_en, _T_712) @[axi4_to_ahb.scala 336:36] - ahbm_data_clken <= _T_713 @[axi4_to_ahb.scala 336:19] + buf_cmd_byte_ptrQ <= _T_696 @[axi4_to_ahb.scala 320:21] + reg _T_697 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 321:52] + _T_697 <= io.ahb.in.hready @[axi4_to_ahb.scala 321:52] + ahb_hready_q <= _T_697 @[axi4_to_ahb.scala 321:21] + node _T_698 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 322:70] + reg _T_699 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 322:52] + _T_699 <= _T_698 @[axi4_to_ahb.scala 322:52] + ahb_htrans_q <= _T_699 @[axi4_to_ahb.scala 322:21] + reg _T_700 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 323:57] + _T_700 <= io.ahb.out.hwrite @[axi4_to_ahb.scala 323:57] + ahb_hwrite_q <= _T_700 @[axi4_to_ahb.scala 323:21] + reg _T_701 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 324:52] + _T_701 <= io.ahb.in.hresp @[axi4_to_ahb.scala 324:52] + ahb_hresp_q <= _T_701 @[axi4_to_ahb.scala 324:21] + node _T_702 = bits(io.ahb.in.hrdata, 63, 0) @[axi4_to_ahb.scala 325:74] + reg _T_703 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 325:57] + _T_703 <= _T_702 @[axi4_to_ahb.scala 325:57] + ahb_hrdata_q <= _T_703 @[axi4_to_ahb.scala 325:21] + node _T_704 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 327:43] + node _T_705 = or(_T_704, io.clk_override) @[axi4_to_ahb.scala 327:58] + node _T_706 = and(io.bus_clk_en, _T_705) @[axi4_to_ahb.scala 327:30] + buf_clken <= _T_706 @[axi4_to_ahb.scala 327:13] + node _T_707 = bits(io.ahb.out.htrans, 1, 1) @[axi4_to_ahb.scala 328:76] + node _T_708 = and(io.ahb.in.hready, _T_707) @[axi4_to_ahb.scala 328:57] + node _T_709 = or(_T_708, io.clk_override) @[axi4_to_ahb.scala 328:81] + node _T_710 = and(io.bus_clk_en, _T_709) @[axi4_to_ahb.scala 328:36] + ahbm_addr_clken <= _T_710 @[axi4_to_ahb.scala 328:19] + node _T_711 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 329:50] + node _T_712 = or(_T_711, io.clk_override) @[axi4_to_ahb.scala 329:60] + node _T_713 = and(io.bus_clk_en, _T_712) @[axi4_to_ahb.scala 329:36] + ahbm_data_clken <= _T_713 @[axi4_to_ahb.scala 329:19] inst rvclkhdr_6 of rvclkhdr_6 @[lib.scala 343:22] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset rvclkhdr_6.io.clk <= clock @[lib.scala 344:17] rvclkhdr_6.io.en <= buf_clken @[lib.scala 345:16] rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 339:12] + buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 332:12] inst rvclkhdr_7 of rvclkhdr_7 @[lib.scala 343:22] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= reset rvclkhdr_7.io.clk <= clock @[lib.scala 344:17] rvclkhdr_7.io.en <= io.bus_clk_en @[lib.scala 345:16] rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 340:12] + ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 333:12] inst rvclkhdr_8 of rvclkhdr_8 @[lib.scala 343:22] rvclkhdr_8.clock <= clock rvclkhdr_8.reset <= reset rvclkhdr_8.io.clk <= clock @[lib.scala 344:17] rvclkhdr_8.io.en <= ahbm_addr_clken @[lib.scala 345:16] rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 341:17] + ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 334:17] inst rvclkhdr_9 of rvclkhdr_9 @[lib.scala 343:22] rvclkhdr_9.clock <= clock rvclkhdr_9.reset <= reset rvclkhdr_9.io.clk <= clock @[lib.scala 344:17] rvclkhdr_9.io.en <= ahbm_data_clken @[lib.scala 345:16] rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 342:17] + ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 335:17] diff --git a/axi4_to_ahb.v b/axi4_to_ahb.v index 2c3bf777..5659c6fa 100644 --- a/axi4_to_ahb.v +++ b/axi4_to_ahb.v @@ -27,7 +27,7 @@ module axi4_to_ahb( input io_clk_override, output io_axi_aw_ready, input io_axi_aw_valid, - input io_axi_aw_bits_id, + input [2:0] io_axi_aw_bits_id, input [31:0] io_axi_aw_bits_addr, input [3:0] io_axi_aw_bits_region, input [7:0] io_axi_aw_bits_len, @@ -45,10 +45,10 @@ module axi4_to_ahb( input io_axi_b_ready, output io_axi_b_valid, output [1:0] io_axi_b_bits_resp, - output io_axi_b_bits_id, + output [2:0] io_axi_b_bits_id, output io_axi_ar_ready, input io_axi_ar_valid, - input io_axi_ar_bits_id, + input [2:0] io_axi_ar_bits_id, input [31:0] io_axi_ar_bits_addr, input [3:0] io_axi_ar_bits_region, input [7:0] io_axi_ar_bits_len, @@ -60,7 +60,7 @@ module axi4_to_ahb( input [3:0] io_axi_ar_bits_qos, input io_axi_r_ready, output io_axi_r_valid, - output io_axi_r_bits_id, + output [2:0] io_axi_r_bits_id, output [63:0] io_axi_r_bits_data, output [1:0] io_axi_r_bits_resp, output io_axi_r_bits_last, @@ -144,31 +144,31 @@ module axi4_to_ahb( wire rvclkhdr_9_io_clk; // @[lib.scala 343:22] wire rvclkhdr_9_io_en; // @[lib.scala 343:22] wire rvclkhdr_9_io_scan_mode; // @[lib.scala 343:22] - wire ahbm_clk = rvclkhdr_7_io_l1clk; // @[axi4_to_ahb.scala 31:22 axi4_to_ahb.scala 340:12] - reg [2:0] buf_state; // @[axi4_to_ahb.scala 37:45] + wire ahbm_clk = rvclkhdr_7_io_l1clk; // @[axi4_to_ahb.scala 24:22 axi4_to_ahb.scala 333:12] + reg [2:0] buf_state; // @[axi4_to_ahb.scala 30:45] wire _T_49 = 3'h0 == buf_state; // @[Conditional.scala 37:30] - wire bus_clk = rvclkhdr_io_l1clk; // @[axi4_to_ahb.scala 57:21 axi4_to_ahb.scala 169:11] - reg wrbuf_vld; // @[axi4_to_ahb.scala 308:51] - reg wrbuf_data_vld; // @[axi4_to_ahb.scala 309:51] - wire wr_cmd_vld = wrbuf_vld & wrbuf_data_vld; // @[axi4_to_ahb.scala 146:27] - wire master_valid = wr_cmd_vld | io_axi_ar_valid; // @[axi4_to_ahb.scala 147:30] + wire bus_clk = rvclkhdr_io_l1clk; // @[axi4_to_ahb.scala 50:21 axi4_to_ahb.scala 162:11] + reg wrbuf_vld; // @[axi4_to_ahb.scala 301:51] + reg wrbuf_data_vld; // @[axi4_to_ahb.scala 302:51] + wire wr_cmd_vld = wrbuf_vld & wrbuf_data_vld; // @[axi4_to_ahb.scala 139:27] + wire master_valid = wr_cmd_vld | io_axi_ar_valid; // @[axi4_to_ahb.scala 140:30] wire _T_101 = 3'h1 == buf_state; // @[Conditional.scala 37:30] - reg ahb_hready_q; // @[axi4_to_ahb.scala 328:52] - reg [1:0] ahb_htrans_q; // @[axi4_to_ahb.scala 329:52] - wire _T_108 = ahb_htrans_q != 2'h0; // @[axi4_to_ahb.scala 190:58] - wire _T_109 = ahb_hready_q & _T_108; // @[axi4_to_ahb.scala 190:36] - wire ahbm_addr_clk = rvclkhdr_8_io_l1clk; // @[axi4_to_ahb.scala 32:27 axi4_to_ahb.scala 341:17] - reg ahb_hwrite_q; // @[axi4_to_ahb.scala 330:57] - wire _T_110 = ~ahb_hwrite_q; // @[axi4_to_ahb.scala 190:72] - wire _T_111 = _T_109 & _T_110; // @[axi4_to_ahb.scala 190:70] + reg ahb_hready_q; // @[axi4_to_ahb.scala 321:52] + reg [1:0] ahb_htrans_q; // @[axi4_to_ahb.scala 322:52] + wire _T_108 = ahb_htrans_q != 2'h0; // @[axi4_to_ahb.scala 183:58] + wire _T_109 = ahb_hready_q & _T_108; // @[axi4_to_ahb.scala 183:36] + wire ahbm_addr_clk = rvclkhdr_8_io_l1clk; // @[axi4_to_ahb.scala 25:27 axi4_to_ahb.scala 334:17] + reg ahb_hwrite_q; // @[axi4_to_ahb.scala 323:57] + wire _T_110 = ~ahb_hwrite_q; // @[axi4_to_ahb.scala 183:72] + wire _T_111 = _T_109 & _T_110; // @[axi4_to_ahb.scala 183:70] wire _T_136 = 3'h6 == buf_state; // @[Conditional.scala 37:30] - reg ahb_hresp_q; // @[axi4_to_ahb.scala 331:52] - wire _T_156 = ahb_hready_q | ahb_hresp_q; // @[axi4_to_ahb.scala 204:37] + reg ahb_hresp_q; // @[axi4_to_ahb.scala 324:52] + wire _T_156 = ahb_hready_q | ahb_hresp_q; // @[axi4_to_ahb.scala 197:37] wire _T_175 = 3'h7 == buf_state; // @[Conditional.scala 37:30] wire _T_186 = 3'h3 == buf_state; // @[Conditional.scala 37:30] wire _T_188 = 3'h2 == buf_state; // @[Conditional.scala 37:30] - wire _T_189 = ahb_hready_q & ahb_hwrite_q; // @[axi4_to_ahb.scala 236:33] - wire _T_192 = _T_189 & _T_108; // @[axi4_to_ahb.scala 236:48] + wire _T_189 = ahb_hready_q & ahb_hwrite_q; // @[axi4_to_ahb.scala 229:33] + wire _T_192 = _T_189 & _T_108; // @[axi4_to_ahb.scala 229:48] wire _T_281 = 3'h4 == buf_state; // @[Conditional.scala 37:30] wire _GEN_15 = _T_281 & _T_192; // @[Conditional.scala 39:67] wire _GEN_19 = _T_188 ? _T_192 : _GEN_15; // @[Conditional.scala 39:67] @@ -177,11 +177,11 @@ module axi4_to_ahb( wire _GEN_79 = _T_136 ? 1'h0 : _GEN_59; // @[Conditional.scala 39:67] wire _GEN_95 = _T_101 ? 1'h0 : _GEN_79; // @[Conditional.scala 39:67] wire trxn_done = _T_49 ? 1'h0 : _GEN_95; // @[Conditional.scala 40:58] - reg cmd_doneQ; // @[axi4_to_ahb.scala 326:52] - wire _T_282 = cmd_doneQ & ahb_hready_q; // @[axi4_to_ahb.scala 246:34] - wire _T_283 = _T_282 | ahb_hresp_q; // @[axi4_to_ahb.scala 246:50] + reg cmd_doneQ; // @[axi4_to_ahb.scala 319:52] + wire _T_282 = cmd_doneQ & ahb_hready_q; // @[axi4_to_ahb.scala 239:34] + wire _T_283 = _T_282 | ahb_hresp_q; // @[axi4_to_ahb.scala 239:50] wire _T_440 = 3'h5 == buf_state; // @[Conditional.scala 37:30] - wire slave_ready = io_axi_b_ready & io_axi_r_ready; // @[axi4_to_ahb.scala 164:33] + wire slave_ready = io_axi_b_ready & io_axi_r_ready; // @[axi4_to_ahb.scala 157:33] wire _GEN_1 = _T_440 & slave_ready; // @[Conditional.scala 39:67] wire _GEN_3 = _T_281 ? _T_283 : _GEN_1; // @[Conditional.scala 39:67] wire _GEN_20 = _T_188 ? trxn_done : _GEN_3; // @[Conditional.scala 39:67] @@ -190,9 +190,9 @@ module axi4_to_ahb( wire _GEN_69 = _T_136 ? _T_156 : _GEN_51; // @[Conditional.scala 39:67] wire _GEN_83 = _T_101 ? _T_111 : _GEN_69; // @[Conditional.scala 39:67] wire buf_state_en = _T_49 ? master_valid : _GEN_83; // @[Conditional.scala 40:58] - wire [1:0] _T_14 = wr_cmd_vld ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 149:20] - wire [2:0] master_opc = {{1'd0}, _T_14}; // @[axi4_to_ahb.scala 149:14] - wire _T_51 = master_opc[2:1] == 2'h1; // @[axi4_to_ahb.scala 175:41] + wire [1:0] _T_14 = wr_cmd_vld ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 142:20] + wire [2:0] master_opc = {{1'd0}, _T_14}; // @[axi4_to_ahb.scala 142:14] + wire _T_51 = master_opc[2:1] == 2'h1; // @[axi4_to_ahb.scala 168:41] wire _GEN_8 = _T_281 & _T_51; // @[Conditional.scala 39:67] wire _GEN_29 = _T_188 ? 1'h0 : _GEN_8; // @[Conditional.scala 39:67] wire _GEN_46 = _T_186 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67] @@ -200,19 +200,19 @@ module axi4_to_ahb( wire _GEN_81 = _T_136 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67] wire _GEN_97 = _T_101 ? 1'h0 : _GEN_81; // @[Conditional.scala 39:67] wire buf_write_in = _T_49 ? _T_51 : _GEN_97; // @[Conditional.scala 40:58] - wire [2:0] _T_53 = buf_write_in ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 176:26] - wire _T_103 = master_opc == 3'h0; // @[axi4_to_ahb.scala 189:61] - wire _T_104 = master_valid & _T_103; // @[axi4_to_ahb.scala 189:41] - wire [2:0] _T_106 = _T_104 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 189:26] - wire _T_124 = _T_106 == 3'h6; // @[axi4_to_ahb.scala 193:174] - wire _T_125 = _T_111 & _T_124; // @[axi4_to_ahb.scala 193:88] - wire _T_137 = ~ahb_hresp_q; // @[axi4_to_ahb.scala 201:39] - wire _T_138 = ahb_hready_q & _T_137; // @[axi4_to_ahb.scala 201:37] - wire _T_141 = master_valid & _T_51; // @[axi4_to_ahb.scala 201:70] - wire _T_142 = ~_T_141; // @[axi4_to_ahb.scala 201:55] - wire _T_143 = _T_138 & _T_142; // @[axi4_to_ahb.scala 201:53] - wire _T_285 = buf_state_en & _T_137; // @[axi4_to_ahb.scala 247:36] - wire _T_286 = _T_285 & slave_ready; // @[axi4_to_ahb.scala 247:51] + wire [2:0] _T_53 = buf_write_in ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 169:26] + wire _T_103 = master_opc == 3'h0; // @[axi4_to_ahb.scala 182:61] + wire _T_104 = master_valid & _T_103; // @[axi4_to_ahb.scala 182:41] + wire [2:0] _T_106 = _T_104 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 182:26] + wire _T_124 = _T_106 == 3'h6; // @[axi4_to_ahb.scala 186:174] + wire _T_125 = _T_111 & _T_124; // @[axi4_to_ahb.scala 186:88] + wire _T_137 = ~ahb_hresp_q; // @[axi4_to_ahb.scala 194:39] + wire _T_138 = ahb_hready_q & _T_137; // @[axi4_to_ahb.scala 194:37] + wire _T_141 = master_valid & _T_51; // @[axi4_to_ahb.scala 194:70] + wire _T_142 = ~_T_141; // @[axi4_to_ahb.scala 194:55] + wire _T_143 = _T_138 & _T_142; // @[axi4_to_ahb.scala 194:53] + wire _T_285 = buf_state_en & _T_137; // @[axi4_to_ahb.scala 240:36] + wire _T_286 = _T_285 & slave_ready; // @[axi4_to_ahb.scala 240:51] wire _GEN_4 = _T_281 & _T_286; // @[Conditional.scala 39:67] wire _GEN_26 = _T_188 ? 1'h0 : _GEN_4; // @[Conditional.scala 39:67] wire _GEN_45 = _T_186 ? 1'h0 : _GEN_26; // @[Conditional.scala 39:67] @@ -220,15 +220,15 @@ module axi4_to_ahb( wire _GEN_66 = _T_136 ? _T_143 : _GEN_62; // @[Conditional.scala 39:67] wire _GEN_86 = _T_101 ? _T_125 : _GEN_66; // @[Conditional.scala 39:67] wire master_ready = _T_49 | _GEN_86; // @[Conditional.scala 40:58] - wire _T_149 = master_valid & master_ready; // @[axi4_to_ahb.scala 203:82] - wire _T_152 = _T_149 & _T_103; // @[axi4_to_ahb.scala 203:97] - wire [2:0] _T_154 = _T_152 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 203:67] - wire [2:0] _T_155 = ahb_hresp_q ? 3'h7 : _T_154; // @[axi4_to_ahb.scala 203:26] - wire _T_287 = ~slave_ready; // @[axi4_to_ahb.scala 248:42] - wire _T_288 = ahb_hresp_q | _T_287; // @[axi4_to_ahb.scala 248:40] - wire [2:0] _T_293 = _T_51 ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 248:99] - wire [2:0] _T_294 = master_valid ? _T_293 : 3'h0; // @[axi4_to_ahb.scala 248:65] - wire [2:0] _T_295 = _T_288 ? 3'h5 : _T_294; // @[axi4_to_ahb.scala 248:26] + wire _T_149 = master_valid & master_ready; // @[axi4_to_ahb.scala 196:82] + wire _T_152 = _T_149 & _T_103; // @[axi4_to_ahb.scala 196:97] + wire [2:0] _T_154 = _T_152 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 196:67] + wire [2:0] _T_155 = ahb_hresp_q ? 3'h7 : _T_154; // @[axi4_to_ahb.scala 196:26] + wire _T_287 = ~slave_ready; // @[axi4_to_ahb.scala 241:42] + wire _T_288 = ahb_hresp_q | _T_287; // @[axi4_to_ahb.scala 241:40] + wire [2:0] _T_293 = _T_51 ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 241:99] + wire [2:0] _T_294 = master_valid ? _T_293 : 3'h0; // @[axi4_to_ahb.scala 241:65] + wire [2:0] _T_295 = _T_288 ? 3'h5 : _T_294; // @[axi4_to_ahb.scala 241:26] wire [2:0] _GEN_5 = _T_281 ? _T_295 : 3'h0; // @[Conditional.scala 39:67] wire [2:0] _GEN_18 = _T_188 ? 3'h4 : _GEN_5; // @[Conditional.scala 39:67] wire [2:0] _GEN_34 = _T_186 ? 3'h5 : _GEN_18; // @[Conditional.scala 39:67] @@ -236,15 +236,15 @@ module axi4_to_ahb( wire [2:0] _GEN_68 = _T_136 ? _T_155 : _GEN_50; // @[Conditional.scala 39:67] wire [2:0] _GEN_82 = _T_101 ? _T_106 : _GEN_68; // @[Conditional.scala 39:67] wire [2:0] buf_nxtstate = _T_49 ? _T_53 : _GEN_82; // @[Conditional.scala 40:58] - reg wrbuf_tag; // @[Reg.scala 27:20] + reg [2:0] wrbuf_tag; // @[Reg.scala 27:20] reg [31:0] wrbuf_addr; // @[lib.scala 374:16] - wire [31:0] master_addr = wr_cmd_vld ? wrbuf_addr : io_axi_ar_bits_addr; // @[axi4_to_ahb.scala 150:21] + wire [31:0] master_addr = wr_cmd_vld ? wrbuf_addr : io_axi_ar_bits_addr; // @[axi4_to_ahb.scala 143:21] reg [2:0] wrbuf_size; // @[Reg.scala 27:20] - wire [2:0] master_size = wr_cmd_vld ? wrbuf_size : io_axi_ar_bits_size; // @[axi4_to_ahb.scala 151:21] + wire [2:0] master_size = wr_cmd_vld ? wrbuf_size : io_axi_ar_bits_size; // @[axi4_to_ahb.scala 144:21] reg [7:0] wrbuf_byteen; // @[Reg.scala 27:20] reg [63:0] wrbuf_data; // @[lib.scala 374:16] - wire _T_358 = buf_nxtstate != 3'h5; // @[axi4_to_ahb.scala 258:55] - wire _T_359 = buf_state_en & _T_358; // @[axi4_to_ahb.scala 258:39] + wire _T_358 = buf_nxtstate != 3'h5; // @[axi4_to_ahb.scala 251:55] + wire _T_359 = buf_state_en & _T_358; // @[axi4_to_ahb.scala 251:39] wire _GEN_14 = _T_281 ? _T_359 : _T_440; // @[Conditional.scala 39:67] wire _GEN_33 = _T_188 ? 1'h0 : _GEN_14; // @[Conditional.scala 39:67] wire _GEN_49 = _T_186 ? 1'h0 : _GEN_33; // @[Conditional.scala 39:67] @@ -252,29 +252,29 @@ module axi4_to_ahb( wire _GEN_73 = _T_136 ? _T_285 : _GEN_52; // @[Conditional.scala 39:67] wire _GEN_94 = _T_101 ? 1'h0 : _GEN_73; // @[Conditional.scala 39:67] wire slave_valid_pre = _T_49 ? 1'h0 : _GEN_94; // @[Conditional.scala 40:58] - wire _T_25 = slave_valid_pre & slave_ready; // @[axi4_to_ahb.scala 156:33] - wire buf_clk = rvclkhdr_6_io_l1clk; // @[axi4_to_ahb.scala 125:21 axi4_to_ahb.scala 339:12] + wire _T_25 = slave_valid_pre & slave_ready; // @[axi4_to_ahb.scala 149:33] + wire buf_clk = rvclkhdr_6_io_l1clk; // @[axi4_to_ahb.scala 118:21 axi4_to_ahb.scala 332:12] reg slvbuf_write; // @[Reg.scala 27:20] - wire [1:0] _T_596 = slvbuf_write ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 292:23] + wire [1:0] _T_596 = slvbuf_write ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 285:23] reg slvbuf_error; // @[Reg.scala 27:20] wire [1:0] _T_598 = slvbuf_error ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_599 = _T_598 & 2'h2; // @[axi4_to_ahb.scala 292:88] + wire [1:0] _T_599 = _T_598 & 2'h2; // @[axi4_to_ahb.scala 285:88] wire [3:0] slave_opc = {_T_596,_T_599}; // @[Cat.scala 29:58] - wire [1:0] _T_30 = slave_opc[1] ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 157:55] - reg slvbuf_tag; // @[Reg.scala 27:20] - wire _T_35 = slave_opc[3:2] == 2'h0; // @[axi4_to_ahb.scala 160:66] + wire [1:0] _T_30 = slave_opc[1] ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 150:55] + reg [2:0] slvbuf_tag; // @[Reg.scala 27:20] + wire _T_35 = slave_opc[3:2] == 2'h0; // @[axi4_to_ahb.scala 153:66] reg [31:0] last_bus_addr; // @[Reg.scala 27:20] wire [63:0] _T_603 = {last_bus_addr,last_bus_addr}; // @[Cat.scala 29:58] - wire _T_604 = buf_state == 3'h5; // @[axi4_to_ahb.scala 293:91] + wire _T_604 = buf_state == 3'h5; // @[axi4_to_ahb.scala 286:91] reg [63:0] buf_data; // @[lib.scala 374:16] - wire ahbm_data_clk = rvclkhdr_9_io_l1clk; // @[axi4_to_ahb.scala 33:27 axi4_to_ahb.scala 342:17] - reg [63:0] ahb_hrdata_q; // @[axi4_to_ahb.scala 332:57] - wire [63:0] _T_607 = _T_604 ? buf_data : ahb_hrdata_q; // @[axi4_to_ahb.scala 293:79] - wire _T_44 = io_axi_aw_valid & io_axi_aw_ready; // @[axi4_to_ahb.scala 167:57] - wire _T_45 = io_axi_w_valid & io_axi_w_ready; // @[axi4_to_ahb.scala 167:94] - wire _T_46 = _T_44 | _T_45; // @[axi4_to_ahb.scala 167:76] - wire _T_55 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 179:54] - wire _T_56 = buf_state_en & _T_55; // @[axi4_to_ahb.scala 179:38] + wire ahbm_data_clk = rvclkhdr_9_io_l1clk; // @[axi4_to_ahb.scala 26:27 axi4_to_ahb.scala 335:17] + reg [63:0] ahb_hrdata_q; // @[axi4_to_ahb.scala 325:57] + wire [63:0] _T_607 = _T_604 ? buf_data : ahb_hrdata_q; // @[axi4_to_ahb.scala 286:79] + wire _T_44 = io_axi_aw_valid & io_axi_aw_ready; // @[axi4_to_ahb.scala 160:57] + wire _T_45 = io_axi_w_valid & io_axi_w_ready; // @[axi4_to_ahb.scala 160:94] + wire _T_46 = _T_44 | _T_45; // @[axi4_to_ahb.scala 160:76] + wire _T_55 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 172:54] + wire _T_56 = buf_state_en & _T_55; // @[axi4_to_ahb.scala 172:38] wire [2:0] _T_87 = wrbuf_byteen[6] ? 3'h6 : 3'h7; // @[Mux.scala 98:16] wire [2:0] _T_88 = wrbuf_byteen[5] ? 3'h5 : _T_87; // @[Mux.scala 98:16] wire [2:0] _T_89 = wrbuf_byteen[4] ? 3'h4 : _T_88; // @[Mux.scala 98:16] @@ -282,14 +282,14 @@ module axi4_to_ahb( wire [2:0] _T_91 = wrbuf_byteen[2] ? 3'h2 : _T_90; // @[Mux.scala 98:16] wire [2:0] _T_92 = wrbuf_byteen[1] ? 3'h1 : _T_91; // @[Mux.scala 98:16] wire [2:0] _T_93 = wrbuf_byteen[0] ? 3'h0 : _T_92; // @[Mux.scala 98:16] - wire [2:0] _T_95 = buf_write_in ? _T_93 : master_addr[2:0]; // @[axi4_to_ahb.scala 182:30] - wire _T_96 = buf_nxtstate == 3'h1; // @[axi4_to_ahb.scala 184:51] - wire _T_126 = master_ready & master_valid; // @[axi4_to_ahb.scala 195:33] - wire _T_162 = buf_nxtstate == 3'h6; // @[axi4_to_ahb.scala 210:64] - wire _T_163 = _T_126 & _T_162; // @[axi4_to_ahb.scala 210:48] - wire _T_164 = _T_163 & buf_state_en; // @[axi4_to_ahb.scala 210:79] - wire _T_349 = buf_state_en & buf_write_in; // @[axi4_to_ahb.scala 256:33] - wire _T_351 = _T_349 & _T_55; // @[axi4_to_ahb.scala 256:48] + wire [2:0] _T_95 = buf_write_in ? _T_93 : master_addr[2:0]; // @[axi4_to_ahb.scala 175:30] + wire _T_96 = buf_nxtstate == 3'h1; // @[axi4_to_ahb.scala 177:51] + wire _T_126 = master_ready & master_valid; // @[axi4_to_ahb.scala 188:33] + wire _T_162 = buf_nxtstate == 3'h6; // @[axi4_to_ahb.scala 203:64] + wire _T_163 = _T_126 & _T_162; // @[axi4_to_ahb.scala 203:48] + wire _T_164 = _T_163 & buf_state_en; // @[axi4_to_ahb.scala 203:79] + wire _T_349 = buf_state_en & buf_write_in; // @[axi4_to_ahb.scala 249:33] + wire _T_351 = _T_349 & _T_55; // @[axi4_to_ahb.scala 249:48] wire _GEN_12 = _T_281 & _T_351; // @[Conditional.scala 39:67] wire _GEN_32 = _T_188 ? 1'h0 : _GEN_12; // @[Conditional.scala 39:67] wire _GEN_48 = _T_186 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67] @@ -298,39 +298,39 @@ module axi4_to_ahb( wire _GEN_88 = _T_101 ? _T_126 : _GEN_75; // @[Conditional.scala 39:67] wire bypass_en = _T_49 ? buf_state_en : _GEN_88; // @[Conditional.scala 40:58] wire [1:0] _T_99 = bypass_en ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_100 = _T_99 & 2'h2; // @[axi4_to_ahb.scala 185:49] - wire _T_112 = ~master_valid; // @[axi4_to_ahb.scala 191:34] - wire _T_113 = buf_state_en & _T_112; // @[axi4_to_ahb.scala 191:32] + wire [1:0] _T_100 = _T_99 & 2'h2; // @[axi4_to_ahb.scala 178:49] + wire _T_112 = ~master_valid; // @[axi4_to_ahb.scala 184:34] + wire _T_113 = buf_state_en & _T_112; // @[axi4_to_ahb.scala 184:32] reg [31:0] buf_addr; // @[lib.scala 374:16] - wire [2:0] _T_130 = bypass_en ? master_addr[2:0] : buf_addr[2:0]; // @[axi4_to_ahb.scala 196:30] - wire _T_131 = ~buf_state_en; // @[axi4_to_ahb.scala 197:48] - wire _T_132 = _T_131 | bypass_en; // @[axi4_to_ahb.scala 197:62] + wire [2:0] _T_130 = bypass_en ? master_addr[2:0] : buf_addr[2:0]; // @[axi4_to_ahb.scala 189:30] + wire _T_131 = ~buf_state_en; // @[axi4_to_ahb.scala 190:48] + wire _T_132 = _T_131 | bypass_en; // @[axi4_to_ahb.scala 190:62] wire [1:0] _T_134 = _T_132 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_135 = 2'h2 & _T_134; // @[axi4_to_ahb.scala 197:36] - wire _T_169 = buf_nxtstate != 3'h6; // @[axi4_to_ahb.scala 212:63] - wire _T_170 = _T_169 & buf_state_en; // @[axi4_to_ahb.scala 212:78] - wire _T_171 = ~_T_170; // @[axi4_to_ahb.scala 212:47] + wire [1:0] _T_135 = 2'h2 & _T_134; // @[axi4_to_ahb.scala 190:36] + wire _T_169 = buf_nxtstate != 3'h6; // @[axi4_to_ahb.scala 205:63] + wire _T_170 = _T_169 & buf_state_en; // @[axi4_to_ahb.scala 205:78] + wire _T_171 = ~_T_170; // @[axi4_to_ahb.scala 205:47] wire [1:0] _T_173 = _T_171 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_174 = 2'h2 & _T_173; // @[axi4_to_ahb.scala 212:36] + wire [1:0] _T_174 = 2'h2 & _T_173; // @[axi4_to_ahb.scala 205:36] wire [1:0] _T_184 = _T_131 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_185 = 2'h2 & _T_184; // @[axi4_to_ahb.scala 222:41] + wire [1:0] _T_185 = 2'h2 & _T_184; // @[axi4_to_ahb.scala 215:41] reg [2:0] buf_cmd_byte_ptrQ; // @[Reg.scala 27:20] reg [7:0] buf_byteen; // @[Reg.scala 27:20] - wire [2:0] _T_197 = buf_cmd_byte_ptrQ + 3'h1; // @[axi4_to_ahb.scala 142:52] - wire _T_200 = 3'h0 >= _T_197; // @[axi4_to_ahb.scala 143:62] - wire _T_201 = buf_byteen[0] & _T_200; // @[axi4_to_ahb.scala 143:48] - wire _T_203 = 3'h1 >= _T_197; // @[axi4_to_ahb.scala 143:62] - wire _T_204 = buf_byteen[1] & _T_203; // @[axi4_to_ahb.scala 143:48] - wire _T_206 = 3'h2 >= _T_197; // @[axi4_to_ahb.scala 143:62] - wire _T_207 = buf_byteen[2] & _T_206; // @[axi4_to_ahb.scala 143:48] - wire _T_209 = 3'h3 >= _T_197; // @[axi4_to_ahb.scala 143:62] - wire _T_210 = buf_byteen[3] & _T_209; // @[axi4_to_ahb.scala 143:48] - wire _T_212 = 3'h4 >= _T_197; // @[axi4_to_ahb.scala 143:62] - wire _T_213 = buf_byteen[4] & _T_212; // @[axi4_to_ahb.scala 143:48] - wire _T_215 = 3'h5 >= _T_197; // @[axi4_to_ahb.scala 143:62] - wire _T_216 = buf_byteen[5] & _T_215; // @[axi4_to_ahb.scala 143:48] - wire _T_218 = 3'h6 >= _T_197; // @[axi4_to_ahb.scala 143:62] - wire _T_219 = buf_byteen[6] & _T_218; // @[axi4_to_ahb.scala 143:48] + wire [2:0] _T_197 = buf_cmd_byte_ptrQ + 3'h1; // @[axi4_to_ahb.scala 135:52] + wire _T_200 = 3'h0 >= _T_197; // @[axi4_to_ahb.scala 136:62] + wire _T_201 = buf_byteen[0] & _T_200; // @[axi4_to_ahb.scala 136:48] + wire _T_203 = 3'h1 >= _T_197; // @[axi4_to_ahb.scala 136:62] + wire _T_204 = buf_byteen[1] & _T_203; // @[axi4_to_ahb.scala 136:48] + wire _T_206 = 3'h2 >= _T_197; // @[axi4_to_ahb.scala 136:62] + wire _T_207 = buf_byteen[2] & _T_206; // @[axi4_to_ahb.scala 136:48] + wire _T_209 = 3'h3 >= _T_197; // @[axi4_to_ahb.scala 136:62] + wire _T_210 = buf_byteen[3] & _T_209; // @[axi4_to_ahb.scala 136:48] + wire _T_212 = 3'h4 >= _T_197; // @[axi4_to_ahb.scala 136:62] + wire _T_213 = buf_byteen[4] & _T_212; // @[axi4_to_ahb.scala 136:48] + wire _T_215 = 3'h5 >= _T_197; // @[axi4_to_ahb.scala 136:62] + wire _T_216 = buf_byteen[5] & _T_215; // @[axi4_to_ahb.scala 136:48] + wire _T_218 = 3'h6 >= _T_197; // @[axi4_to_ahb.scala 136:62] + wire _T_219 = buf_byteen[6] & _T_218; // @[axi4_to_ahb.scala 136:48] wire [2:0] _T_224 = _T_219 ? 3'h6 : 3'h7; // @[Mux.scala 98:16] wire [2:0] _T_225 = _T_216 ? 3'h5 : _T_224; // @[Mux.scala 98:16] wire [2:0] _T_226 = _T_213 ? 3'h4 : _T_225; // @[Mux.scala 98:16] @@ -338,17 +338,17 @@ module axi4_to_ahb( wire [2:0] _T_228 = _T_207 ? 3'h2 : _T_227; // @[Mux.scala 98:16] wire [2:0] _T_229 = _T_204 ? 3'h1 : _T_228; // @[Mux.scala 98:16] wire [2:0] _T_230 = _T_201 ? 3'h0 : _T_229; // @[Mux.scala 98:16] - wire [2:0] _T_231 = trxn_done ? _T_230 : buf_cmd_byte_ptrQ; // @[axi4_to_ahb.scala 240:30] - wire _T_232 = buf_cmd_byte_ptrQ == 3'h7; // @[axi4_to_ahb.scala 241:65] + wire [2:0] _T_231 = trxn_done ? _T_230 : buf_cmd_byte_ptrQ; // @[axi4_to_ahb.scala 233:30] + wire _T_232 = buf_cmd_byte_ptrQ == 3'h7; // @[axi4_to_ahb.scala 234:65] reg buf_aligned; // @[Reg.scala 27:20] - wire _T_233 = buf_aligned | _T_232; // @[axi4_to_ahb.scala 241:44] - wire [7:0] _T_271 = buf_byteen >> _T_230; // @[axi4_to_ahb.scala 241:92] - wire _T_273 = ~_T_271[0]; // @[axi4_to_ahb.scala 241:163] - wire _T_274 = _T_233 | _T_273; // @[axi4_to_ahb.scala 241:79] - wire _T_275 = trxn_done & _T_274; // @[axi4_to_ahb.scala 241:29] - wire _T_346 = _T_232 | _T_273; // @[axi4_to_ahb.scala 255:38] - wire _T_347 = _T_109 & _T_346; // @[axi4_to_ahb.scala 254:80] - wire _T_348 = ahb_hresp_q | _T_347; // @[axi4_to_ahb.scala 254:34] + wire _T_233 = buf_aligned | _T_232; // @[axi4_to_ahb.scala 234:44] + wire [7:0] _T_271 = buf_byteen >> _T_230; // @[axi4_to_ahb.scala 234:92] + wire _T_273 = ~_T_271[0]; // @[axi4_to_ahb.scala 234:163] + wire _T_274 = _T_233 | _T_273; // @[axi4_to_ahb.scala 234:79] + wire _T_275 = trxn_done & _T_274; // @[axi4_to_ahb.scala 234:29] + wire _T_346 = _T_232 | _T_273; // @[axi4_to_ahb.scala 248:38] + wire _T_347 = _T_109 & _T_346; // @[axi4_to_ahb.scala 247:80] + wire _T_348 = ahb_hresp_q | _T_347; // @[axi4_to_ahb.scala 247:34] wire _GEN_11 = _T_281 & _T_348; // @[Conditional.scala 39:67] wire _GEN_24 = _T_188 ? _T_275 : _GEN_11; // @[Conditional.scala 39:67] wire _GEN_43 = _T_186 ? 1'h0 : _GEN_24; // @[Conditional.scala 39:67] @@ -356,17 +356,17 @@ module axi4_to_ahb( wire _GEN_74 = _T_136 ? _T_113 : _GEN_61; // @[Conditional.scala 39:67] wire _GEN_84 = _T_101 ? _T_113 : _GEN_74; // @[Conditional.scala 39:67] wire cmd_done = _T_49 ? 1'h0 : _GEN_84; // @[Conditional.scala 40:58] - wire _T_276 = cmd_done | cmd_doneQ; // @[axi4_to_ahb.scala 242:47] - wire _T_277 = ~_T_276; // @[axi4_to_ahb.scala 242:36] + wire _T_276 = cmd_done | cmd_doneQ; // @[axi4_to_ahb.scala 235:47] + wire _T_277 = ~_T_276; // @[axi4_to_ahb.scala 235:36] wire [1:0] _T_279 = _T_277 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_280 = _T_279 & 2'h2; // @[axi4_to_ahb.scala 242:61] - wire _T_300 = _T_55 | _T_96; // @[axi4_to_ahb.scala 252:62] - wire _T_301 = buf_state_en & _T_300; // @[axi4_to_ahb.scala 252:33] - wire _T_354 = _T_277 | bypass_en; // @[axi4_to_ahb.scala 257:61] + wire [1:0] _T_280 = _T_279 & 2'h2; // @[axi4_to_ahb.scala 235:61] + wire _T_300 = _T_55 | _T_96; // @[axi4_to_ahb.scala 245:62] + wire _T_301 = buf_state_en & _T_300; // @[axi4_to_ahb.scala 245:33] + wire _T_354 = _T_277 | bypass_en; // @[axi4_to_ahb.scala 250:61] wire [1:0] _T_356 = _T_354 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_357 = _T_356 & 2'h2; // @[axi4_to_ahb.scala 257:75] - wire _T_364 = trxn_done | bypass_en; // @[axi4_to_ahb.scala 260:40] - wire [2:0] _T_439 = bypass_en ? _T_93 : _T_231; // @[axi4_to_ahb.scala 261:30] + wire [1:0] _T_357 = _T_356 & 2'h2; // @[axi4_to_ahb.scala 250:75] + wire _T_364 = trxn_done | bypass_en; // @[axi4_to_ahb.scala 253:40] + wire [2:0] _T_439 = bypass_en ? _T_93 : _T_231; // @[axi4_to_ahb.scala 254:30] wire _GEN_6 = _T_281 & ahb_hresp_q; // @[Conditional.scala 39:67] wire _GEN_7 = _T_281 ? buf_state_en : _T_440; // @[Conditional.scala 39:67] wire _GEN_9 = _T_281 & _T_301; // @[Conditional.scala 39:67] @@ -415,92 +415,92 @@ module axi4_to_ahb( wire [2:0] buf_cmd_byte_ptr = _T_49 ? _T_95 : _GEN_89; // @[Conditional.scala 40:58] wire slvbuf_wr_en = _T_49 ? 1'h0 : _GEN_85; // @[Conditional.scala 40:58] wire slvbuf_error_en = _T_49 ? 1'h0 : _GEN_93; // @[Conditional.scala 40:58] - wire _T_535 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 278:24] - wire _T_536 = _T_103 | _T_535; // @[axi4_to_ahb.scala 277:48] - wire _T_538 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 278:54] - wire _T_539 = _T_536 | _T_538; // @[axi4_to_ahb.scala 278:33] - wire _T_541 = master_size[1:0] == 2'h2; // @[axi4_to_ahb.scala 278:93] - wire _T_542 = _T_539 | _T_541; // @[axi4_to_ahb.scala 278:72] - wire _T_544 = master_size[1:0] == 2'h3; // @[axi4_to_ahb.scala 279:25] - wire _T_546 = wrbuf_byteen == 8'h3; // @[axi4_to_ahb.scala 279:62] - wire _T_548 = wrbuf_byteen == 8'hc; // @[axi4_to_ahb.scala 279:97] - wire _T_549 = _T_546 | _T_548; // @[axi4_to_ahb.scala 279:74] - wire _T_551 = wrbuf_byteen == 8'h30; // @[axi4_to_ahb.scala 279:132] - wire _T_552 = _T_549 | _T_551; // @[axi4_to_ahb.scala 279:109] - wire _T_554 = wrbuf_byteen == 8'hc0; // @[axi4_to_ahb.scala 279:168] - wire _T_555 = _T_552 | _T_554; // @[axi4_to_ahb.scala 279:145] - wire _T_557 = wrbuf_byteen == 8'hf; // @[axi4_to_ahb.scala 280:28] - wire _T_558 = _T_555 | _T_557; // @[axi4_to_ahb.scala 279:181] - wire _T_560 = wrbuf_byteen == 8'hf0; // @[axi4_to_ahb.scala 280:63] - wire _T_561 = _T_558 | _T_560; // @[axi4_to_ahb.scala 280:40] - wire _T_563 = wrbuf_byteen == 8'hff; // @[axi4_to_ahb.scala 280:99] - wire _T_564 = _T_561 | _T_563; // @[axi4_to_ahb.scala 280:76] - wire _T_565 = _T_544 & _T_564; // @[axi4_to_ahb.scala 279:38] - wire buf_aligned_in = _T_542 | _T_565; // @[axi4_to_ahb.scala 278:106] - wire _T_444 = buf_aligned_in & _T_51; // @[axi4_to_ahb.scala 272:60] + wire _T_535 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 271:24] + wire _T_536 = _T_103 | _T_535; // @[axi4_to_ahb.scala 270:48] + wire _T_538 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 271:54] + wire _T_539 = _T_536 | _T_538; // @[axi4_to_ahb.scala 271:33] + wire _T_541 = master_size[1:0] == 2'h2; // @[axi4_to_ahb.scala 271:93] + wire _T_542 = _T_539 | _T_541; // @[axi4_to_ahb.scala 271:72] + wire _T_544 = master_size[1:0] == 2'h3; // @[axi4_to_ahb.scala 272:25] + wire _T_546 = wrbuf_byteen == 8'h3; // @[axi4_to_ahb.scala 272:62] + wire _T_548 = wrbuf_byteen == 8'hc; // @[axi4_to_ahb.scala 272:97] + wire _T_549 = _T_546 | _T_548; // @[axi4_to_ahb.scala 272:74] + wire _T_551 = wrbuf_byteen == 8'h30; // @[axi4_to_ahb.scala 272:132] + wire _T_552 = _T_549 | _T_551; // @[axi4_to_ahb.scala 272:109] + wire _T_554 = wrbuf_byteen == 8'hc0; // @[axi4_to_ahb.scala 272:168] + wire _T_555 = _T_552 | _T_554; // @[axi4_to_ahb.scala 272:145] + wire _T_557 = wrbuf_byteen == 8'hf; // @[axi4_to_ahb.scala 273:28] + wire _T_558 = _T_555 | _T_557; // @[axi4_to_ahb.scala 272:181] + wire _T_560 = wrbuf_byteen == 8'hf0; // @[axi4_to_ahb.scala 273:63] + wire _T_561 = _T_558 | _T_560; // @[axi4_to_ahb.scala 273:40] + wire _T_563 = wrbuf_byteen == 8'hff; // @[axi4_to_ahb.scala 273:99] + wire _T_564 = _T_561 | _T_563; // @[axi4_to_ahb.scala 273:76] + wire _T_565 = _T_544 & _T_564; // @[axi4_to_ahb.scala 272:38] + wire buf_aligned_in = _T_542 | _T_565; // @[axi4_to_ahb.scala 271:106] + wire _T_444 = buf_aligned_in & _T_51; // @[axi4_to_ahb.scala 265:60] wire [2:0] _T_461 = _T_548 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_462 = 3'h2 & _T_461; // @[axi4_to_ahb.scala 135:15] - wire _T_468 = _T_560 | _T_546; // @[axi4_to_ahb.scala 136:56] + wire [2:0] _T_462 = 3'h2 & _T_461; // @[axi4_to_ahb.scala 128:15] + wire _T_468 = _T_560 | _T_546; // @[axi4_to_ahb.scala 129:56] wire [2:0] _T_470 = _T_468 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_471 = 3'h4 & _T_470; // @[axi4_to_ahb.scala 136:15] - wire [2:0] _T_472 = _T_462 | _T_471; // @[axi4_to_ahb.scala 135:63] + wire [2:0] _T_471 = 3'h4 & _T_470; // @[axi4_to_ahb.scala 129:15] + wire [2:0] _T_472 = _T_462 | _T_471; // @[axi4_to_ahb.scala 128:63] wire [2:0] _T_476 = _T_554 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_477 = 3'h6 & _T_476; // @[axi4_to_ahb.scala 137:15] - wire [2:0] _T_478 = _T_472 | _T_477; // @[axi4_to_ahb.scala 136:96] - wire [2:0] _T_485 = _T_444 ? _T_478 : master_addr[2:0]; // @[axi4_to_ahb.scala 272:43] - wire _T_489 = buf_state == 3'h3; // @[axi4_to_ahb.scala 275:33] - wire _T_495 = buf_aligned_in & _T_544; // @[axi4_to_ahb.scala 276:38] - wire _T_498 = _T_495 & _T_51; // @[axi4_to_ahb.scala 276:71] + wire [2:0] _T_477 = 3'h6 & _T_476; // @[axi4_to_ahb.scala 130:15] + wire [2:0] _T_478 = _T_472 | _T_477; // @[axi4_to_ahb.scala 129:96] + wire [2:0] _T_485 = _T_444 ? _T_478 : master_addr[2:0]; // @[axi4_to_ahb.scala 265:43] + wire _T_489 = buf_state == 3'h3; // @[axi4_to_ahb.scala 268:33] + wire _T_495 = buf_aligned_in & _T_544; // @[axi4_to_ahb.scala 269:38] + wire _T_498 = _T_495 & _T_51; // @[axi4_to_ahb.scala 269:71] wire [1:0] _T_504 = _T_563 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire _T_510 = _T_560 | _T_557; // @[axi4_to_ahb.scala 129:55] + wire _T_510 = _T_560 | _T_557; // @[axi4_to_ahb.scala 122:55] wire [1:0] _T_512 = _T_510 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_513 = 2'h2 & _T_512; // @[axi4_to_ahb.scala 129:16] - wire [1:0] _T_514 = _T_504 | _T_513; // @[axi4_to_ahb.scala 128:64] - wire _T_519 = _T_554 | _T_551; // @[axi4_to_ahb.scala 130:60] - wire _T_522 = _T_519 | _T_548; // @[axi4_to_ahb.scala 130:89] - wire _T_525 = _T_522 | _T_546; // @[axi4_to_ahb.scala 130:123] + wire [1:0] _T_513 = 2'h2 & _T_512; // @[axi4_to_ahb.scala 122:16] + wire [1:0] _T_514 = _T_504 | _T_513; // @[axi4_to_ahb.scala 121:64] + wire _T_519 = _T_554 | _T_551; // @[axi4_to_ahb.scala 123:60] + wire _T_522 = _T_519 | _T_548; // @[axi4_to_ahb.scala 123:89] + wire _T_525 = _T_522 | _T_546; // @[axi4_to_ahb.scala 123:123] wire [1:0] _T_527 = _T_525 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_528 = 2'h1 & _T_527; // @[axi4_to_ahb.scala 130:21] - wire [1:0] _T_529 = _T_514 | _T_528; // @[axi4_to_ahb.scala 129:93] - wire [1:0] _T_531 = _T_498 ? _T_529 : master_size[1:0]; // @[axi4_to_ahb.scala 276:21] + wire [1:0] _T_528 = 2'h1 & _T_527; // @[axi4_to_ahb.scala 123:21] + wire [1:0] _T_529 = _T_514 | _T_528; // @[axi4_to_ahb.scala 122:93] + wire [1:0] _T_531 = _T_498 ? _T_529 : master_size[1:0]; // @[axi4_to_ahb.scala 269:21] wire [31:0] _T_570 = {master_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] wire [31:0] _T_573 = {buf_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] wire [1:0] _T_577 = buf_aligned_in ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [2:0] buf_size_in = {{1'd0}, _T_531}; // @[axi4_to_ahb.scala 276:15] - wire [1:0] _T_579 = _T_577 & buf_size_in[1:0]; // @[axi4_to_ahb.scala 283:81] + wire [2:0] buf_size_in = {{1'd0}, _T_531}; // @[axi4_to_ahb.scala 269:15] + wire [1:0] _T_579 = _T_577 & buf_size_in[1:0]; // @[axi4_to_ahb.scala 276:81] wire [2:0] _T_580 = {1'h0,_T_579}; // @[Cat.scala 29:58] wire [1:0] _T_582 = buf_aligned ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] reg [1:0] buf_size; // @[Reg.scala 27:20] - wire [1:0] _T_584 = _T_582 & buf_size; // @[axi4_to_ahb.scala 283:138] + wire [1:0] _T_584 = _T_582 & buf_size; // @[axi4_to_ahb.scala 276:138] wire [2:0] _T_585 = {1'h0,_T_584}; // @[Cat.scala 29:58] - wire _T_588 = ~io_axi_ar_bits_prot[2]; // @[axi4_to_ahb.scala 287:37] + wire _T_588 = ~io_axi_ar_bits_prot[2]; // @[axi4_to_ahb.scala 280:37] wire [1:0] _T_589 = {1'h1,_T_588}; // @[Cat.scala 29:58] reg buf_write; // @[Reg.scala 27:20] - wire _T_611 = io_ahb_out_htrans != 2'h0; // @[axi4_to_ahb.scala 296:44] - wire _T_612 = _T_611 & io_ahb_in_hready; // @[axi4_to_ahb.scala 296:56] - wire last_addr_en = _T_612 & io_ahb_out_hwrite; // @[axi4_to_ahb.scala 296:75] - wire wrbuf_en = _T_44 & master_ready; // @[axi4_to_ahb.scala 298:49] - wire wrbuf_data_en = _T_45 & master_ready; // @[axi4_to_ahb.scala 299:52] - wire wrbuf_cmd_sent = _T_149 & _T_51; // @[axi4_to_ahb.scala 300:49] - wire _T_622 = ~wrbuf_en; // @[axi4_to_ahb.scala 301:33] - wire wrbuf_rst = wrbuf_cmd_sent & _T_622; // @[axi4_to_ahb.scala 301:31] - wire _T_624 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 303:36] - wire _T_625 = wrbuf_vld & _T_624; // @[axi4_to_ahb.scala 303:34] - wire _T_626 = ~_T_625; // @[axi4_to_ahb.scala 303:22] - wire _T_629 = wrbuf_data_vld & _T_624; // @[axi4_to_ahb.scala 304:38] - wire _T_630 = ~_T_629; // @[axi4_to_ahb.scala 304:21] - wire _T_633 = ~wr_cmd_vld; // @[axi4_to_ahb.scala 305:22] - wire _T_636 = wrbuf_en | wrbuf_vld; // @[axi4_to_ahb.scala 308:55] - wire _T_637 = ~wrbuf_rst; // @[axi4_to_ahb.scala 308:91] - wire _T_641 = wrbuf_data_en | wrbuf_data_vld; // @[axi4_to_ahb.scala 309:55] - reg buf_tag; // @[Reg.scala 27:20] - wire _T_691 = ~slave_valid_pre; // @[axi4_to_ahb.scala 326:92] - wire _T_704 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 334:43] - wire _T_705 = _T_704 | io_clk_override; // @[axi4_to_ahb.scala 334:58] - wire _T_708 = io_ahb_in_hready & io_ahb_out_htrans[1]; // @[axi4_to_ahb.scala 335:57] - wire _T_709 = _T_708 | io_clk_override; // @[axi4_to_ahb.scala 335:81] - wire _T_711 = buf_state != 3'h0; // @[axi4_to_ahb.scala 336:50] - wire _T_712 = _T_711 | io_clk_override; // @[axi4_to_ahb.scala 336:60] + wire _T_611 = io_ahb_out_htrans != 2'h0; // @[axi4_to_ahb.scala 289:44] + wire _T_612 = _T_611 & io_ahb_in_hready; // @[axi4_to_ahb.scala 289:56] + wire last_addr_en = _T_612 & io_ahb_out_hwrite; // @[axi4_to_ahb.scala 289:75] + wire wrbuf_en = _T_44 & master_ready; // @[axi4_to_ahb.scala 291:49] + wire wrbuf_data_en = _T_45 & master_ready; // @[axi4_to_ahb.scala 292:52] + wire wrbuf_cmd_sent = _T_149 & _T_51; // @[axi4_to_ahb.scala 293:49] + wire _T_622 = ~wrbuf_en; // @[axi4_to_ahb.scala 294:33] + wire wrbuf_rst = wrbuf_cmd_sent & _T_622; // @[axi4_to_ahb.scala 294:31] + wire _T_624 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 296:36] + wire _T_625 = wrbuf_vld & _T_624; // @[axi4_to_ahb.scala 296:34] + wire _T_626 = ~_T_625; // @[axi4_to_ahb.scala 296:22] + wire _T_629 = wrbuf_data_vld & _T_624; // @[axi4_to_ahb.scala 297:38] + wire _T_630 = ~_T_629; // @[axi4_to_ahb.scala 297:21] + wire _T_633 = ~wr_cmd_vld; // @[axi4_to_ahb.scala 298:22] + wire _T_636 = wrbuf_en | wrbuf_vld; // @[axi4_to_ahb.scala 301:55] + wire _T_637 = ~wrbuf_rst; // @[axi4_to_ahb.scala 301:91] + wire _T_641 = wrbuf_data_en | wrbuf_data_vld; // @[axi4_to_ahb.scala 302:55] + reg [2:0] buf_tag; // @[Reg.scala 27:20] + wire _T_691 = ~slave_valid_pre; // @[axi4_to_ahb.scala 319:92] + wire _T_704 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 327:43] + wire _T_705 = _T_704 | io_clk_override; // @[axi4_to_ahb.scala 327:58] + wire _T_708 = io_ahb_in_hready & io_ahb_out_htrans[1]; // @[axi4_to_ahb.scala 328:57] + wire _T_709 = _T_708 | io_clk_override; // @[axi4_to_ahb.scala 328:81] + wire _T_711 = buf_state != 3'h0; // @[axi4_to_ahb.scala 329:50] + wire _T_712 = _T_711 | io_clk_override; // @[axi4_to_ahb.scala 329:60] rvclkhdr rvclkhdr ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), @@ -561,25 +561,25 @@ module axi4_to_ahb( .io_en(rvclkhdr_9_io_en), .io_scan_mode(rvclkhdr_9_io_scan_mode) ); - assign io_axi_aw_ready = _T_626 & master_ready; // @[axi4_to_ahb.scala 303:19] - assign io_axi_w_ready = _T_630 & master_ready; // @[axi4_to_ahb.scala 304:18] - assign io_axi_b_valid = _T_25 & slave_opc[3]; // @[axi4_to_ahb.scala 156:18] - assign io_axi_b_bits_resp = slave_opc[0] ? 2'h2 : _T_30; // @[axi4_to_ahb.scala 157:22] - assign io_axi_b_bits_id = slvbuf_tag; // @[axi4_to_ahb.scala 158:20] - assign io_axi_ar_ready = _T_633 & master_ready; // @[axi4_to_ahb.scala 305:19] - assign io_axi_r_valid = _T_25 & _T_35; // @[axi4_to_ahb.scala 160:18] - assign io_axi_r_bits_id = slvbuf_tag; // @[axi4_to_ahb.scala 162:20] - assign io_axi_r_bits_data = slvbuf_error ? _T_603 : _T_607; // @[axi4_to_ahb.scala 163:22] - assign io_axi_r_bits_resp = slave_opc[0] ? 2'h2 : _T_30; // @[axi4_to_ahb.scala 161:22] - assign io_axi_r_bits_last = 1'h1; // @[axi4_to_ahb.scala 306:22] - assign io_ahb_out_haddr = bypass_en ? _T_570 : _T_573; // @[axi4_to_ahb.scala 282:20] - assign io_ahb_out_hburst = 3'h0; // @[axi4_to_ahb.scala 285:21] - assign io_ahb_out_hmastlock = 1'h0; // @[axi4_to_ahb.scala 286:24] - assign io_ahb_out_hprot = {{2'd0}, _T_589}; // @[axi4_to_ahb.scala 287:20] - assign io_ahb_out_hsize = bypass_en ? _T_580 : _T_585; // @[axi4_to_ahb.scala 283:20] - assign io_ahb_out_htrans = _T_49 ? _T_100 : _GEN_90; // @[axi4_to_ahb.scala 29:21 axi4_to_ahb.scala 185:25 axi4_to_ahb.scala 197:25 axi4_to_ahb.scala 212:25 axi4_to_ahb.scala 222:25 axi4_to_ahb.scala 242:25 axi4_to_ahb.scala 257:25] - assign io_ahb_out_hwrite = bypass_en ? _T_51 : buf_write; // @[axi4_to_ahb.scala 288:21] - assign io_ahb_out_hwdata = buf_data; // @[axi4_to_ahb.scala 289:21] + assign io_axi_aw_ready = _T_626 & master_ready; // @[axi4_to_ahb.scala 296:19] + assign io_axi_w_ready = _T_630 & master_ready; // @[axi4_to_ahb.scala 297:18] + assign io_axi_b_valid = _T_25 & slave_opc[3]; // @[axi4_to_ahb.scala 149:18] + assign io_axi_b_bits_resp = slave_opc[0] ? 2'h2 : _T_30; // @[axi4_to_ahb.scala 150:22] + assign io_axi_b_bits_id = slvbuf_tag; // @[axi4_to_ahb.scala 151:20] + assign io_axi_ar_ready = _T_633 & master_ready; // @[axi4_to_ahb.scala 298:19] + assign io_axi_r_valid = _T_25 & _T_35; // @[axi4_to_ahb.scala 153:18] + assign io_axi_r_bits_id = slvbuf_tag; // @[axi4_to_ahb.scala 155:20] + assign io_axi_r_bits_data = slvbuf_error ? _T_603 : _T_607; // @[axi4_to_ahb.scala 156:22] + assign io_axi_r_bits_resp = slave_opc[0] ? 2'h2 : _T_30; // @[axi4_to_ahb.scala 154:22] + assign io_axi_r_bits_last = 1'h1; // @[axi4_to_ahb.scala 299:22] + assign io_ahb_out_haddr = bypass_en ? _T_570 : _T_573; // @[axi4_to_ahb.scala 275:20] + assign io_ahb_out_hburst = 3'h0; // @[axi4_to_ahb.scala 278:21] + assign io_ahb_out_hmastlock = 1'h0; // @[axi4_to_ahb.scala 279:24] + assign io_ahb_out_hprot = {{2'd0}, _T_589}; // @[axi4_to_ahb.scala 280:20] + assign io_ahb_out_hsize = bypass_en ? _T_580 : _T_585; // @[axi4_to_ahb.scala 276:20] + assign io_ahb_out_htrans = _T_49 ? _T_100 : _GEN_90; // @[axi4_to_ahb.scala 22:21 axi4_to_ahb.scala 178:25 axi4_to_ahb.scala 190:25 axi4_to_ahb.scala 205:25 axi4_to_ahb.scala 215:25 axi4_to_ahb.scala 235:25 axi4_to_ahb.scala 250:25] + assign io_ahb_out_hwrite = bypass_en ? _T_51 : buf_write; // @[axi4_to_ahb.scala 281:21] + assign io_ahb_out_hwdata = buf_data; // @[axi4_to_ahb.scala 282:21] assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17] assign rvclkhdr_io_en = io_bus_clk_en; // @[lib.scala 345:16] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] @@ -662,7 +662,7 @@ initial begin _RAND_7 = {1{`RANDOM}}; cmd_doneQ = _RAND_7[0:0]; _RAND_8 = {1{`RANDOM}}; - wrbuf_tag = _RAND_8[0:0]; + wrbuf_tag = _RAND_8[2:0]; _RAND_9 = {1{`RANDOM}}; wrbuf_addr = _RAND_9[31:0]; _RAND_10 = {1{`RANDOM}}; @@ -676,7 +676,7 @@ initial begin _RAND_14 = {1{`RANDOM}}; slvbuf_error = _RAND_14[0:0]; _RAND_15 = {1{`RANDOM}}; - slvbuf_tag = _RAND_15[0:0]; + slvbuf_tag = _RAND_15[2:0]; _RAND_16 = {1{`RANDOM}}; last_bus_addr = _RAND_16[31:0]; _RAND_17 = {2{`RANDOM}}; @@ -696,7 +696,7 @@ initial begin _RAND_24 = {1{`RANDOM}}; buf_write = _RAND_24[0:0]; _RAND_25 = {1{`RANDOM}}; - buf_tag = _RAND_25[0:0]; + buf_tag = _RAND_25[2:0]; `endif // RANDOMIZE_REG_INIT if (reset) begin buf_state = 3'h0; @@ -723,7 +723,7 @@ initial begin cmd_doneQ = 1'h0; end if (reset) begin - wrbuf_tag = 1'h0; + wrbuf_tag = 3'h0; end if (reset) begin wrbuf_addr = 32'h0; @@ -744,7 +744,7 @@ initial begin slvbuf_error = 1'h0; end if (reset) begin - slvbuf_tag = 1'h0; + slvbuf_tag = 3'h0; end if (reset) begin last_bus_addr = 32'h0; @@ -774,7 +774,7 @@ initial begin buf_write = 1'h0; end if (reset) begin - buf_tag = 1'h0; + buf_tag = 3'h0; end `endif // RANDOMIZE end // initial @@ -880,7 +880,7 @@ end // initial end always @(posedge bus_clk or posedge reset) begin if (reset) begin - wrbuf_tag <= 1'h0; + wrbuf_tag <= 3'h0; end else if (wrbuf_en) begin wrbuf_tag <= io_axi_aw_bits_id; end @@ -943,7 +943,7 @@ end // initial end always @(posedge buf_clk or posedge reset) begin if (reset) begin - slvbuf_tag <= 1'h0; + slvbuf_tag <= 3'h0; end else if (slvbuf_wr_en) begin slvbuf_tag <= buf_tag; end @@ -1127,7 +1127,7 @@ end // initial end always @(posedge buf_clk or posedge reset) begin if (reset) begin - buf_tag <= 1'h0; + buf_tag <= 3'h0; end else if (buf_wr_en) begin if (wr_cmd_vld) begin buf_tag <= wrbuf_tag; diff --git a/quasar_wrapper.fir b/quasar_wrapper.fir index 4c78863d..04602610 100644 --- a/quasar_wrapper.fir +++ b/quasar_wrapper.fir @@ -73424,983 +73424,973 @@ circuit quasar_wrapper : reg _T_339 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_339 <= mfdc_ns @[lib.scala 374:16] mfdc_int <= _T_339 @[dec_tlu_ctl.scala 1748:11] - node _T_340 = bits(io.dec_csr_wrdata_r, 18, 16) @[dec_tlu_ctl.scala 1753:40] - node _T_341 = not(_T_340) @[dec_tlu_ctl.scala 1753:20] - node _T_342 = bits(io.dec_csr_wrdata_r, 11, 7) @[dec_tlu_ctl.scala 1753:67] - node _T_343 = bits(io.dec_csr_wrdata_r, 6, 6) @[dec_tlu_ctl.scala 1753:95] - node _T_344 = not(_T_343) @[dec_tlu_ctl.scala 1753:75] - node _T_345 = bits(io.dec_csr_wrdata_r, 5, 0) @[dec_tlu_ctl.scala 1753:119] - node _T_346 = cat(_T_344, _T_345) @[Cat.scala 29:58] - node _T_347 = cat(_T_341, _T_342) @[Cat.scala 29:58] + node _T_340 = bits(io.dec_csr_wrdata_r, 18, 16) @[dec_tlu_ctl.scala 1757:39] + node _T_341 = not(_T_340) @[dec_tlu_ctl.scala 1757:19] + node _T_342 = bits(io.dec_csr_wrdata_r, 11, 0) @[dec_tlu_ctl.scala 1757:66] + node _T_343 = cat(_T_341, _T_342) @[Cat.scala 29:58] + mfdc_ns <= _T_343 @[dec_tlu_ctl.scala 1757:12] + node _T_344 = bits(mfdc_int, 14, 12) @[dec_tlu_ctl.scala 1758:28] + node _T_345 = not(_T_344) @[dec_tlu_ctl.scala 1758:19] + node _T_346 = bits(mfdc_int, 11, 0) @[dec_tlu_ctl.scala 1758:54] + node _T_347 = cat(_T_345, UInt<4>("h00")) @[Cat.scala 29:58] node _T_348 = cat(_T_347, _T_346) @[Cat.scala 29:58] - mfdc_ns <= _T_348 @[dec_tlu_ctl.scala 1753:13] - node _T_349 = bits(mfdc_int, 14, 12) @[dec_tlu_ctl.scala 1754:29] - node _T_350 = not(_T_349) @[dec_tlu_ctl.scala 1754:20] - node _T_351 = bits(mfdc_int, 11, 7) @[dec_tlu_ctl.scala 1754:55] - node _T_352 = bits(mfdc_int, 6, 6) @[dec_tlu_ctl.scala 1754:72] - node _T_353 = not(_T_352) @[dec_tlu_ctl.scala 1754:63] - node _T_354 = bits(mfdc_int, 5, 0) @[dec_tlu_ctl.scala 1754:85] - node _T_355 = cat(_T_353, _T_354) @[Cat.scala 29:58] - node _T_356 = cat(_T_350, UInt<4>("h00")) @[Cat.scala 29:58] - node _T_357 = cat(_T_356, _T_351) @[Cat.scala 29:58] - node _T_358 = cat(_T_357, _T_355) @[Cat.scala 29:58] - mfdc <= _T_358 @[dec_tlu_ctl.scala 1754:13] - node _T_359 = bits(mfdc, 18, 16) @[dec_tlu_ctl.scala 1762:46] - io.dec_tlu_dma_qos_prty <= _T_359 @[dec_tlu_ctl.scala 1762:39] - node _T_360 = bits(mfdc, 11, 11) @[dec_tlu_ctl.scala 1763:46] - io.dec_tlu_external_ldfwd_disable <= _T_360 @[dec_tlu_ctl.scala 1763:39] - node _T_361 = bits(mfdc, 8, 8) @[dec_tlu_ctl.scala 1764:46] - io.dec_tlu_core_ecc_disable <= _T_361 @[dec_tlu_ctl.scala 1764:39] - node _T_362 = bits(mfdc, 6, 6) @[dec_tlu_ctl.scala 1765:46] - io.dec_tlu_sideeffect_posted_disable <= _T_362 @[dec_tlu_ctl.scala 1765:39] - node _T_363 = bits(mfdc, 3, 3) @[dec_tlu_ctl.scala 1766:46] - io.dec_tlu_bpred_disable <= _T_363 @[dec_tlu_ctl.scala 1766:39] - node _T_364 = bits(mfdc, 2, 2) @[dec_tlu_ctl.scala 1767:46] - io.dec_tlu_wb_coalescing_disable <= _T_364 @[dec_tlu_ctl.scala 1767:39] - node _T_365 = bits(mfdc, 0, 0) @[dec_tlu_ctl.scala 1768:46] - io.dec_tlu_pipelining_disable <= _T_365 @[dec_tlu_ctl.scala 1768:39] - node _T_366 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1777:70] - node _T_367 = eq(_T_366, UInt<12>("h07c2")) @[dec_tlu_ctl.scala 1777:77] - node _T_368 = and(io.dec_csr_wen_r_mod, _T_367) @[dec_tlu_ctl.scala 1777:48] - node _T_369 = not(io.interrupt_valid_r) @[dec_tlu_ctl.scala 1777:89] - node _T_370 = and(_T_368, _T_369) @[dec_tlu_ctl.scala 1777:87] - node _T_371 = not(io.take_ext_int_start) @[dec_tlu_ctl.scala 1777:113] - node _T_372 = and(_T_370, _T_371) @[dec_tlu_ctl.scala 1777:111] - io.dec_tlu_wr_pause_r <= _T_372 @[dec_tlu_ctl.scala 1777:24] - node _T_373 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1784:61] - node _T_374 = eq(_T_373, UInt<12>("h07c0")) @[dec_tlu_ctl.scala 1784:68] - node wr_mrac_r = and(io.dec_csr_wen_r_mod, _T_374) @[dec_tlu_ctl.scala 1784:39] - node _T_375 = bits(io.dec_csr_wrdata_r, 31, 31) @[dec_tlu_ctl.scala 1787:39] - node _T_376 = bits(io.dec_csr_wrdata_r, 30, 30) @[dec_tlu_ctl.scala 1787:64] - node _T_377 = bits(io.dec_csr_wrdata_r, 31, 31) @[dec_tlu_ctl.scala 1787:91] - node _T_378 = not(_T_377) @[dec_tlu_ctl.scala 1787:71] - node _T_379 = and(_T_376, _T_378) @[dec_tlu_ctl.scala 1787:69] - node _T_380 = bits(io.dec_csr_wrdata_r, 29, 29) @[dec_tlu_ctl.scala 1788:41] - node _T_381 = bits(io.dec_csr_wrdata_r, 28, 28) @[dec_tlu_ctl.scala 1788:66] - node _T_382 = bits(io.dec_csr_wrdata_r, 29, 29) @[dec_tlu_ctl.scala 1788:93] - node _T_383 = not(_T_382) @[dec_tlu_ctl.scala 1788:73] - node _T_384 = and(_T_381, _T_383) @[dec_tlu_ctl.scala 1788:71] - node _T_385 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 1789:41] - node _T_386 = bits(io.dec_csr_wrdata_r, 26, 26) @[dec_tlu_ctl.scala 1789:66] - node _T_387 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 1789:93] - node _T_388 = not(_T_387) @[dec_tlu_ctl.scala 1789:73] - node _T_389 = and(_T_386, _T_388) @[dec_tlu_ctl.scala 1789:71] - node _T_390 = bits(io.dec_csr_wrdata_r, 25, 25) @[dec_tlu_ctl.scala 1790:41] - node _T_391 = bits(io.dec_csr_wrdata_r, 24, 24) @[dec_tlu_ctl.scala 1790:66] - node _T_392 = bits(io.dec_csr_wrdata_r, 25, 25) @[dec_tlu_ctl.scala 1790:93] - node _T_393 = not(_T_392) @[dec_tlu_ctl.scala 1790:73] - node _T_394 = and(_T_391, _T_393) @[dec_tlu_ctl.scala 1790:71] - node _T_395 = bits(io.dec_csr_wrdata_r, 23, 23) @[dec_tlu_ctl.scala 1791:41] - node _T_396 = bits(io.dec_csr_wrdata_r, 22, 22) @[dec_tlu_ctl.scala 1791:66] - node _T_397 = bits(io.dec_csr_wrdata_r, 23, 23) @[dec_tlu_ctl.scala 1791:93] - node _T_398 = not(_T_397) @[dec_tlu_ctl.scala 1791:73] - node _T_399 = and(_T_396, _T_398) @[dec_tlu_ctl.scala 1791:71] - node _T_400 = bits(io.dec_csr_wrdata_r, 21, 21) @[dec_tlu_ctl.scala 1792:41] - node _T_401 = bits(io.dec_csr_wrdata_r, 20, 20) @[dec_tlu_ctl.scala 1792:66] - node _T_402 = bits(io.dec_csr_wrdata_r, 21, 21) @[dec_tlu_ctl.scala 1792:93] - node _T_403 = not(_T_402) @[dec_tlu_ctl.scala 1792:73] - node _T_404 = and(_T_401, _T_403) @[dec_tlu_ctl.scala 1792:71] - node _T_405 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 1793:41] - node _T_406 = bits(io.dec_csr_wrdata_r, 18, 18) @[dec_tlu_ctl.scala 1793:66] - node _T_407 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 1793:93] - node _T_408 = not(_T_407) @[dec_tlu_ctl.scala 1793:73] - node _T_409 = and(_T_406, _T_408) @[dec_tlu_ctl.scala 1793:71] - node _T_410 = bits(io.dec_csr_wrdata_r, 17, 17) @[dec_tlu_ctl.scala 1794:41] - node _T_411 = bits(io.dec_csr_wrdata_r, 16, 16) @[dec_tlu_ctl.scala 1794:66] - node _T_412 = bits(io.dec_csr_wrdata_r, 17, 17) @[dec_tlu_ctl.scala 1794:93] - node _T_413 = not(_T_412) @[dec_tlu_ctl.scala 1794:73] - node _T_414 = and(_T_411, _T_413) @[dec_tlu_ctl.scala 1794:71] - node _T_415 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 1795:41] - node _T_416 = bits(io.dec_csr_wrdata_r, 14, 14) @[dec_tlu_ctl.scala 1795:66] - node _T_417 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 1795:93] - node _T_418 = not(_T_417) @[dec_tlu_ctl.scala 1795:73] - node _T_419 = and(_T_416, _T_418) @[dec_tlu_ctl.scala 1795:71] - node _T_420 = bits(io.dec_csr_wrdata_r, 13, 13) @[dec_tlu_ctl.scala 1796:41] - node _T_421 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 1796:66] - node _T_422 = bits(io.dec_csr_wrdata_r, 13, 13) @[dec_tlu_ctl.scala 1796:93] - node _T_423 = not(_T_422) @[dec_tlu_ctl.scala 1796:73] - node _T_424 = and(_T_421, _T_423) @[dec_tlu_ctl.scala 1796:71] - node _T_425 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1797:41] - node _T_426 = bits(io.dec_csr_wrdata_r, 10, 10) @[dec_tlu_ctl.scala 1797:66] - node _T_427 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1797:93] - node _T_428 = not(_T_427) @[dec_tlu_ctl.scala 1797:73] - node _T_429 = and(_T_426, _T_428) @[dec_tlu_ctl.scala 1797:71] - node _T_430 = bits(io.dec_csr_wrdata_r, 9, 9) @[dec_tlu_ctl.scala 1798:41] - node _T_431 = bits(io.dec_csr_wrdata_r, 8, 8) @[dec_tlu_ctl.scala 1798:66] - node _T_432 = bits(io.dec_csr_wrdata_r, 9, 9) @[dec_tlu_ctl.scala 1798:93] - node _T_433 = not(_T_432) @[dec_tlu_ctl.scala 1798:73] - node _T_434 = and(_T_431, _T_433) @[dec_tlu_ctl.scala 1798:70] - node _T_435 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1799:41] - node _T_436 = bits(io.dec_csr_wrdata_r, 6, 6) @[dec_tlu_ctl.scala 1799:66] - node _T_437 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1799:93] - node _T_438 = not(_T_437) @[dec_tlu_ctl.scala 1799:73] - node _T_439 = and(_T_436, _T_438) @[dec_tlu_ctl.scala 1799:70] - node _T_440 = bits(io.dec_csr_wrdata_r, 5, 5) @[dec_tlu_ctl.scala 1800:41] - node _T_441 = bits(io.dec_csr_wrdata_r, 4, 4) @[dec_tlu_ctl.scala 1800:66] - node _T_442 = bits(io.dec_csr_wrdata_r, 5, 5) @[dec_tlu_ctl.scala 1800:93] - node _T_443 = not(_T_442) @[dec_tlu_ctl.scala 1800:73] - node _T_444 = and(_T_441, _T_443) @[dec_tlu_ctl.scala 1800:70] - node _T_445 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1801:41] - node _T_446 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 1801:66] - node _T_447 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1801:93] - node _T_448 = not(_T_447) @[dec_tlu_ctl.scala 1801:73] - node _T_449 = and(_T_446, _T_448) @[dec_tlu_ctl.scala 1801:70] - node _T_450 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1802:41] - node _T_451 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1802:66] - node _T_452 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1802:93] - node _T_453 = not(_T_452) @[dec_tlu_ctl.scala 1802:73] - node _T_454 = and(_T_451, _T_453) @[dec_tlu_ctl.scala 1802:70] - node _T_455 = cat(_T_450, _T_454) @[Cat.scala 29:58] - node _T_456 = cat(_T_445, _T_449) @[Cat.scala 29:58] + mfdc <= _T_348 @[dec_tlu_ctl.scala 1758:12] + node _T_349 = bits(mfdc, 18, 16) @[dec_tlu_ctl.scala 1762:46] + io.dec_tlu_dma_qos_prty <= _T_349 @[dec_tlu_ctl.scala 1762:39] + node _T_350 = bits(mfdc, 11, 11) @[dec_tlu_ctl.scala 1763:46] + io.dec_tlu_external_ldfwd_disable <= _T_350 @[dec_tlu_ctl.scala 1763:39] + node _T_351 = bits(mfdc, 8, 8) @[dec_tlu_ctl.scala 1764:46] + io.dec_tlu_core_ecc_disable <= _T_351 @[dec_tlu_ctl.scala 1764:39] + node _T_352 = bits(mfdc, 6, 6) @[dec_tlu_ctl.scala 1765:46] + io.dec_tlu_sideeffect_posted_disable <= _T_352 @[dec_tlu_ctl.scala 1765:39] + node _T_353 = bits(mfdc, 3, 3) @[dec_tlu_ctl.scala 1766:46] + io.dec_tlu_bpred_disable <= _T_353 @[dec_tlu_ctl.scala 1766:39] + node _T_354 = bits(mfdc, 2, 2) @[dec_tlu_ctl.scala 1767:46] + io.dec_tlu_wb_coalescing_disable <= _T_354 @[dec_tlu_ctl.scala 1767:39] + node _T_355 = bits(mfdc, 0, 0) @[dec_tlu_ctl.scala 1768:46] + io.dec_tlu_pipelining_disable <= _T_355 @[dec_tlu_ctl.scala 1768:39] + node _T_356 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1777:70] + node _T_357 = eq(_T_356, UInt<12>("h07c2")) @[dec_tlu_ctl.scala 1777:77] + node _T_358 = and(io.dec_csr_wen_r_mod, _T_357) @[dec_tlu_ctl.scala 1777:48] + node _T_359 = not(io.interrupt_valid_r) @[dec_tlu_ctl.scala 1777:89] + node _T_360 = and(_T_358, _T_359) @[dec_tlu_ctl.scala 1777:87] + node _T_361 = not(io.take_ext_int_start) @[dec_tlu_ctl.scala 1777:113] + node _T_362 = and(_T_360, _T_361) @[dec_tlu_ctl.scala 1777:111] + io.dec_tlu_wr_pause_r <= _T_362 @[dec_tlu_ctl.scala 1777:24] + node _T_363 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1784:61] + node _T_364 = eq(_T_363, UInt<12>("h07c0")) @[dec_tlu_ctl.scala 1784:68] + node wr_mrac_r = and(io.dec_csr_wen_r_mod, _T_364) @[dec_tlu_ctl.scala 1784:39] + node _T_365 = bits(io.dec_csr_wrdata_r, 31, 31) @[dec_tlu_ctl.scala 1787:39] + node _T_366 = bits(io.dec_csr_wrdata_r, 30, 30) @[dec_tlu_ctl.scala 1787:64] + node _T_367 = bits(io.dec_csr_wrdata_r, 31, 31) @[dec_tlu_ctl.scala 1787:91] + node _T_368 = not(_T_367) @[dec_tlu_ctl.scala 1787:71] + node _T_369 = and(_T_366, _T_368) @[dec_tlu_ctl.scala 1787:69] + node _T_370 = bits(io.dec_csr_wrdata_r, 29, 29) @[dec_tlu_ctl.scala 1788:41] + node _T_371 = bits(io.dec_csr_wrdata_r, 28, 28) @[dec_tlu_ctl.scala 1788:66] + node _T_372 = bits(io.dec_csr_wrdata_r, 29, 29) @[dec_tlu_ctl.scala 1788:93] + node _T_373 = not(_T_372) @[dec_tlu_ctl.scala 1788:73] + node _T_374 = and(_T_371, _T_373) @[dec_tlu_ctl.scala 1788:71] + node _T_375 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 1789:41] + node _T_376 = bits(io.dec_csr_wrdata_r, 26, 26) @[dec_tlu_ctl.scala 1789:66] + node _T_377 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 1789:93] + node _T_378 = not(_T_377) @[dec_tlu_ctl.scala 1789:73] + node _T_379 = and(_T_376, _T_378) @[dec_tlu_ctl.scala 1789:71] + node _T_380 = bits(io.dec_csr_wrdata_r, 25, 25) @[dec_tlu_ctl.scala 1790:41] + node _T_381 = bits(io.dec_csr_wrdata_r, 24, 24) @[dec_tlu_ctl.scala 1790:66] + node _T_382 = bits(io.dec_csr_wrdata_r, 25, 25) @[dec_tlu_ctl.scala 1790:93] + node _T_383 = not(_T_382) @[dec_tlu_ctl.scala 1790:73] + node _T_384 = and(_T_381, _T_383) @[dec_tlu_ctl.scala 1790:71] + node _T_385 = bits(io.dec_csr_wrdata_r, 23, 23) @[dec_tlu_ctl.scala 1791:41] + node _T_386 = bits(io.dec_csr_wrdata_r, 22, 22) @[dec_tlu_ctl.scala 1791:66] + node _T_387 = bits(io.dec_csr_wrdata_r, 23, 23) @[dec_tlu_ctl.scala 1791:93] + node _T_388 = not(_T_387) @[dec_tlu_ctl.scala 1791:73] + node _T_389 = and(_T_386, _T_388) @[dec_tlu_ctl.scala 1791:71] + node _T_390 = bits(io.dec_csr_wrdata_r, 21, 21) @[dec_tlu_ctl.scala 1792:41] + node _T_391 = bits(io.dec_csr_wrdata_r, 20, 20) @[dec_tlu_ctl.scala 1792:66] + node _T_392 = bits(io.dec_csr_wrdata_r, 21, 21) @[dec_tlu_ctl.scala 1792:93] + node _T_393 = not(_T_392) @[dec_tlu_ctl.scala 1792:73] + node _T_394 = and(_T_391, _T_393) @[dec_tlu_ctl.scala 1792:71] + node _T_395 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 1793:41] + node _T_396 = bits(io.dec_csr_wrdata_r, 18, 18) @[dec_tlu_ctl.scala 1793:66] + node _T_397 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 1793:93] + node _T_398 = not(_T_397) @[dec_tlu_ctl.scala 1793:73] + node _T_399 = and(_T_396, _T_398) @[dec_tlu_ctl.scala 1793:71] + node _T_400 = bits(io.dec_csr_wrdata_r, 17, 17) @[dec_tlu_ctl.scala 1794:41] + node _T_401 = bits(io.dec_csr_wrdata_r, 16, 16) @[dec_tlu_ctl.scala 1794:66] + node _T_402 = bits(io.dec_csr_wrdata_r, 17, 17) @[dec_tlu_ctl.scala 1794:93] + node _T_403 = not(_T_402) @[dec_tlu_ctl.scala 1794:73] + node _T_404 = and(_T_401, _T_403) @[dec_tlu_ctl.scala 1794:71] + node _T_405 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 1795:41] + node _T_406 = bits(io.dec_csr_wrdata_r, 14, 14) @[dec_tlu_ctl.scala 1795:66] + node _T_407 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 1795:93] + node _T_408 = not(_T_407) @[dec_tlu_ctl.scala 1795:73] + node _T_409 = and(_T_406, _T_408) @[dec_tlu_ctl.scala 1795:71] + node _T_410 = bits(io.dec_csr_wrdata_r, 13, 13) @[dec_tlu_ctl.scala 1796:41] + node _T_411 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 1796:66] + node _T_412 = bits(io.dec_csr_wrdata_r, 13, 13) @[dec_tlu_ctl.scala 1796:93] + node _T_413 = not(_T_412) @[dec_tlu_ctl.scala 1796:73] + node _T_414 = and(_T_411, _T_413) @[dec_tlu_ctl.scala 1796:71] + node _T_415 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1797:41] + node _T_416 = bits(io.dec_csr_wrdata_r, 10, 10) @[dec_tlu_ctl.scala 1797:66] + node _T_417 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1797:93] + node _T_418 = not(_T_417) @[dec_tlu_ctl.scala 1797:73] + node _T_419 = and(_T_416, _T_418) @[dec_tlu_ctl.scala 1797:71] + node _T_420 = bits(io.dec_csr_wrdata_r, 9, 9) @[dec_tlu_ctl.scala 1798:41] + node _T_421 = bits(io.dec_csr_wrdata_r, 8, 8) @[dec_tlu_ctl.scala 1798:66] + node _T_422 = bits(io.dec_csr_wrdata_r, 9, 9) @[dec_tlu_ctl.scala 1798:93] + node _T_423 = not(_T_422) @[dec_tlu_ctl.scala 1798:73] + node _T_424 = and(_T_421, _T_423) @[dec_tlu_ctl.scala 1798:70] + node _T_425 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1799:41] + node _T_426 = bits(io.dec_csr_wrdata_r, 6, 6) @[dec_tlu_ctl.scala 1799:66] + node _T_427 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1799:93] + node _T_428 = not(_T_427) @[dec_tlu_ctl.scala 1799:73] + node _T_429 = and(_T_426, _T_428) @[dec_tlu_ctl.scala 1799:70] + node _T_430 = bits(io.dec_csr_wrdata_r, 5, 5) @[dec_tlu_ctl.scala 1800:41] + node _T_431 = bits(io.dec_csr_wrdata_r, 4, 4) @[dec_tlu_ctl.scala 1800:66] + node _T_432 = bits(io.dec_csr_wrdata_r, 5, 5) @[dec_tlu_ctl.scala 1800:93] + node _T_433 = not(_T_432) @[dec_tlu_ctl.scala 1800:73] + node _T_434 = and(_T_431, _T_433) @[dec_tlu_ctl.scala 1800:70] + node _T_435 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1801:41] + node _T_436 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 1801:66] + node _T_437 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1801:93] + node _T_438 = not(_T_437) @[dec_tlu_ctl.scala 1801:73] + node _T_439 = and(_T_436, _T_438) @[dec_tlu_ctl.scala 1801:70] + node _T_440 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1802:41] + node _T_441 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1802:66] + node _T_442 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1802:93] + node _T_443 = not(_T_442) @[dec_tlu_ctl.scala 1802:73] + node _T_444 = and(_T_441, _T_443) @[dec_tlu_ctl.scala 1802:70] + node _T_445 = cat(_T_440, _T_444) @[Cat.scala 29:58] + node _T_446 = cat(_T_435, _T_439) @[Cat.scala 29:58] + node _T_447 = cat(_T_446, _T_445) @[Cat.scala 29:58] + node _T_448 = cat(_T_430, _T_434) @[Cat.scala 29:58] + node _T_449 = cat(_T_425, _T_429) @[Cat.scala 29:58] + node _T_450 = cat(_T_449, _T_448) @[Cat.scala 29:58] + node _T_451 = cat(_T_450, _T_447) @[Cat.scala 29:58] + node _T_452 = cat(_T_420, _T_424) @[Cat.scala 29:58] + node _T_453 = cat(_T_415, _T_419) @[Cat.scala 29:58] + node _T_454 = cat(_T_453, _T_452) @[Cat.scala 29:58] + node _T_455 = cat(_T_410, _T_414) @[Cat.scala 29:58] + node _T_456 = cat(_T_405, _T_409) @[Cat.scala 29:58] node _T_457 = cat(_T_456, _T_455) @[Cat.scala 29:58] - node _T_458 = cat(_T_440, _T_444) @[Cat.scala 29:58] - node _T_459 = cat(_T_435, _T_439) @[Cat.scala 29:58] - node _T_460 = cat(_T_459, _T_458) @[Cat.scala 29:58] - node _T_461 = cat(_T_460, _T_457) @[Cat.scala 29:58] - node _T_462 = cat(_T_430, _T_434) @[Cat.scala 29:58] - node _T_463 = cat(_T_425, _T_429) @[Cat.scala 29:58] - node _T_464 = cat(_T_463, _T_462) @[Cat.scala 29:58] - node _T_465 = cat(_T_420, _T_424) @[Cat.scala 29:58] - node _T_466 = cat(_T_415, _T_419) @[Cat.scala 29:58] - node _T_467 = cat(_T_466, _T_465) @[Cat.scala 29:58] - node _T_468 = cat(_T_467, _T_464) @[Cat.scala 29:58] - node _T_469 = cat(_T_468, _T_461) @[Cat.scala 29:58] - node _T_470 = cat(_T_410, _T_414) @[Cat.scala 29:58] - node _T_471 = cat(_T_405, _T_409) @[Cat.scala 29:58] + node _T_458 = cat(_T_457, _T_454) @[Cat.scala 29:58] + node _T_459 = cat(_T_458, _T_451) @[Cat.scala 29:58] + node _T_460 = cat(_T_400, _T_404) @[Cat.scala 29:58] + node _T_461 = cat(_T_395, _T_399) @[Cat.scala 29:58] + node _T_462 = cat(_T_461, _T_460) @[Cat.scala 29:58] + node _T_463 = cat(_T_390, _T_394) @[Cat.scala 29:58] + node _T_464 = cat(_T_385, _T_389) @[Cat.scala 29:58] + node _T_465 = cat(_T_464, _T_463) @[Cat.scala 29:58] + node _T_466 = cat(_T_465, _T_462) @[Cat.scala 29:58] + node _T_467 = cat(_T_380, _T_384) @[Cat.scala 29:58] + node _T_468 = cat(_T_375, _T_379) @[Cat.scala 29:58] + node _T_469 = cat(_T_468, _T_467) @[Cat.scala 29:58] + node _T_470 = cat(_T_370, _T_374) @[Cat.scala 29:58] + node _T_471 = cat(_T_365, _T_369) @[Cat.scala 29:58] node _T_472 = cat(_T_471, _T_470) @[Cat.scala 29:58] - node _T_473 = cat(_T_400, _T_404) @[Cat.scala 29:58] - node _T_474 = cat(_T_395, _T_399) @[Cat.scala 29:58] - node _T_475 = cat(_T_474, _T_473) @[Cat.scala 29:58] - node _T_476 = cat(_T_475, _T_472) @[Cat.scala 29:58] - node _T_477 = cat(_T_390, _T_394) @[Cat.scala 29:58] - node _T_478 = cat(_T_385, _T_389) @[Cat.scala 29:58] - node _T_479 = cat(_T_478, _T_477) @[Cat.scala 29:58] - node _T_480 = cat(_T_380, _T_384) @[Cat.scala 29:58] - node _T_481 = cat(_T_375, _T_379) @[Cat.scala 29:58] - node _T_482 = cat(_T_481, _T_480) @[Cat.scala 29:58] - node _T_483 = cat(_T_482, _T_479) @[Cat.scala 29:58] - node _T_484 = cat(_T_483, _T_476) @[Cat.scala 29:58] - node mrac_in = cat(_T_484, _T_469) @[Cat.scala 29:58] - node _T_485 = bits(wr_mrac_r, 0, 0) @[dec_tlu_ctl.scala 1805:38] + node _T_473 = cat(_T_472, _T_469) @[Cat.scala 29:58] + node _T_474 = cat(_T_473, _T_466) @[Cat.scala 29:58] + node mrac_in = cat(_T_474, _T_459) @[Cat.scala 29:58] + node _T_475 = bits(wr_mrac_r, 0, 0) @[dec_tlu_ctl.scala 1805:38] inst rvclkhdr_10 of rvclkhdr_730 @[lib.scala 368:23] rvclkhdr_10.clock <= clock rvclkhdr_10.reset <= reset rvclkhdr_10.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_10.io.en <= _T_485 @[lib.scala 371:17] + rvclkhdr_10.io.en <= _T_475 @[lib.scala 371:17] rvclkhdr_10.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg mrac : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] mrac <= mrac_in @[lib.scala 374:16] io.dec_tlu_mrac_ff <= mrac @[dec_tlu_ctl.scala 1807:21] - node _T_486 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1815:62] - node _T_487 = eq(_T_486, UInt<12>("h0bc0")) @[dec_tlu_ctl.scala 1815:69] - node wr_mdeau_r = and(io.dec_csr_wen_r_mod, _T_487) @[dec_tlu_ctl.scala 1815:40] - node _T_488 = not(wr_mdeau_r) @[dec_tlu_ctl.scala 1825:59] - node _T_489 = and(io.mdseac_locked_f, _T_488) @[dec_tlu_ctl.scala 1825:57] - node _T_490 = or(mdseac_en, _T_489) @[dec_tlu_ctl.scala 1825:35] - io.mdseac_locked_ns <= _T_490 @[dec_tlu_ctl.scala 1825:22] - node _T_491 = or(io.lsu_imprecise_error_store_any, io.lsu_imprecise_error_load_any) @[dec_tlu_ctl.scala 1827:49] - node _T_492 = not(io.nmi_int_detected_f) @[dec_tlu_ctl.scala 1827:86] - node _T_493 = and(_T_491, _T_492) @[dec_tlu_ctl.scala 1827:84] - node _T_494 = not(io.mdseac_locked_f) @[dec_tlu_ctl.scala 1827:111] - node _T_495 = and(_T_493, _T_494) @[dec_tlu_ctl.scala 1827:109] - mdseac_en <= _T_495 @[dec_tlu_ctl.scala 1827:12] - node _T_496 = bits(mdseac_en, 0, 0) @[dec_tlu_ctl.scala 1829:64] + node _T_476 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1815:62] + node _T_477 = eq(_T_476, UInt<12>("h0bc0")) @[dec_tlu_ctl.scala 1815:69] + node wr_mdeau_r = and(io.dec_csr_wen_r_mod, _T_477) @[dec_tlu_ctl.scala 1815:40] + node _T_478 = not(wr_mdeau_r) @[dec_tlu_ctl.scala 1825:59] + node _T_479 = and(io.mdseac_locked_f, _T_478) @[dec_tlu_ctl.scala 1825:57] + node _T_480 = or(mdseac_en, _T_479) @[dec_tlu_ctl.scala 1825:35] + io.mdseac_locked_ns <= _T_480 @[dec_tlu_ctl.scala 1825:22] + node _T_481 = or(io.lsu_imprecise_error_store_any, io.lsu_imprecise_error_load_any) @[dec_tlu_ctl.scala 1827:49] + node _T_482 = not(io.nmi_int_detected_f) @[dec_tlu_ctl.scala 1827:86] + node _T_483 = and(_T_481, _T_482) @[dec_tlu_ctl.scala 1827:84] + node _T_484 = not(io.mdseac_locked_f) @[dec_tlu_ctl.scala 1827:111] + node _T_485 = and(_T_483, _T_484) @[dec_tlu_ctl.scala 1827:109] + mdseac_en <= _T_485 @[dec_tlu_ctl.scala 1827:12] + node _T_486 = bits(mdseac_en, 0, 0) @[dec_tlu_ctl.scala 1829:64] inst rvclkhdr_11 of rvclkhdr_731 @[lib.scala 368:23] rvclkhdr_11.clock <= clock rvclkhdr_11.reset <= reset rvclkhdr_11.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_11.io.en <= _T_496 @[lib.scala 371:17] + rvclkhdr_11.io.en <= _T_486 @[lib.scala 371:17] rvclkhdr_11.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg mdseac : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] mdseac <= io.lsu_imprecise_error_addr_any @[lib.scala 374:16] - node _T_497 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1838:61] - node _T_498 = eq(_T_497, UInt<12>("h07c6")) @[dec_tlu_ctl.scala 1838:68] - node wr_mpmc_r = and(io.dec_csr_wen_r_mod, _T_498) @[dec_tlu_ctl.scala 1838:39] - node _T_499 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1842:51] - node _T_500 = and(wr_mpmc_r, _T_499) @[dec_tlu_ctl.scala 1842:30] - node _T_501 = not(io.internal_dbg_halt_mode_f2) @[dec_tlu_ctl.scala 1842:57] - node _T_502 = and(_T_500, _T_501) @[dec_tlu_ctl.scala 1842:55] - node _T_503 = not(io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 1842:89] - node _T_504 = and(_T_502, _T_503) @[dec_tlu_ctl.scala 1842:87] - io.fw_halt_req <= _T_504 @[dec_tlu_ctl.scala 1842:17] + node _T_487 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1838:61] + node _T_488 = eq(_T_487, UInt<12>("h07c6")) @[dec_tlu_ctl.scala 1838:68] + node wr_mpmc_r = and(io.dec_csr_wen_r_mod, _T_488) @[dec_tlu_ctl.scala 1838:39] + node _T_489 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1842:51] + node _T_490 = and(wr_mpmc_r, _T_489) @[dec_tlu_ctl.scala 1842:30] + node _T_491 = not(io.internal_dbg_halt_mode_f2) @[dec_tlu_ctl.scala 1842:57] + node _T_492 = and(_T_490, _T_491) @[dec_tlu_ctl.scala 1842:55] + node _T_493 = not(io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 1842:89] + node _T_494 = and(_T_492, _T_493) @[dec_tlu_ctl.scala 1842:87] + io.fw_halt_req <= _T_494 @[dec_tlu_ctl.scala 1842:17] wire fw_halted_ns : UInt<1> fw_halted_ns <= UInt<1>("h00") reg fw_halted : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1844:48] fw_halted <= fw_halted_ns @[dec_tlu_ctl.scala 1844:48] - node _T_505 = or(io.fw_halt_req, fw_halted) @[dec_tlu_ctl.scala 1845:34] - node _T_506 = not(set_mie_pmu_fw_halt) @[dec_tlu_ctl.scala 1845:49] - node _T_507 = and(_T_505, _T_506) @[dec_tlu_ctl.scala 1845:47] - fw_halted_ns <= _T_507 @[dec_tlu_ctl.scala 1845:15] - node _T_508 = bits(wr_mpmc_r, 0, 0) @[dec_tlu_ctl.scala 1846:29] - node _T_509 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1846:57] - node _T_510 = not(_T_509) @[dec_tlu_ctl.scala 1846:37] - node _T_511 = not(mpmc) @[dec_tlu_ctl.scala 1846:62] - node _T_512 = mux(_T_508, _T_510, _T_511) @[dec_tlu_ctl.scala 1846:18] - mpmc_b_ns <= _T_512 @[dec_tlu_ctl.scala 1846:12] - reg _T_513 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1848:44] - _T_513 <= mpmc_b_ns @[dec_tlu_ctl.scala 1848:44] - mpmc_b <= _T_513 @[dec_tlu_ctl.scala 1848:9] - node _T_514 = not(mpmc_b) @[dec_tlu_ctl.scala 1851:10] - mpmc <= _T_514 @[dec_tlu_ctl.scala 1851:7] - node _T_515 = bits(io.dec_csr_wrdata_r, 31, 27) @[dec_tlu_ctl.scala 1860:40] - node _T_516 = gt(_T_515, UInt<5>("h01a")) @[dec_tlu_ctl.scala 1860:48] - node _T_517 = bits(io.dec_csr_wrdata_r, 31, 27) @[dec_tlu_ctl.scala 1860:92] - node csr_sat = mux(_T_516, UInt<5>("h01a"), _T_517) @[dec_tlu_ctl.scala 1860:19] - node _T_518 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1862:63] - node _T_519 = eq(_T_518, UInt<12>("h07f0")) @[dec_tlu_ctl.scala 1862:70] - node wr_micect_r = and(io.dec_csr_wen_r_mod, _T_519) @[dec_tlu_ctl.scala 1862:41] - node _T_520 = cat(UInt<26>("h00"), io.ic_perr_r_d1) @[Cat.scala 29:58] - node _T_521 = add(micect, _T_520) @[dec_tlu_ctl.scala 1863:23] - node _T_522 = tail(_T_521, 1) @[dec_tlu_ctl.scala 1863:23] - micect_inc <= _T_522 @[dec_tlu_ctl.scala 1863:13] - node _T_523 = bits(wr_micect_r, 0, 0) @[dec_tlu_ctl.scala 1864:35] - node _T_524 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1864:75] - node _T_525 = cat(csr_sat, _T_524) @[Cat.scala 29:58] - node _T_526 = bits(micect, 31, 27) @[dec_tlu_ctl.scala 1864:95] - node _T_527 = cat(_T_526, micect_inc) @[Cat.scala 29:58] - node micect_ns = mux(_T_523, _T_525, _T_527) @[dec_tlu_ctl.scala 1864:22] - node _T_528 = or(wr_micect_r, io.ic_perr_r_d1) @[dec_tlu_ctl.scala 1866:42] - node _T_529 = bits(_T_528, 0, 0) @[dec_tlu_ctl.scala 1866:61] + node _T_495 = or(io.fw_halt_req, fw_halted) @[dec_tlu_ctl.scala 1845:34] + node _T_496 = not(set_mie_pmu_fw_halt) @[dec_tlu_ctl.scala 1845:49] + node _T_497 = and(_T_495, _T_496) @[dec_tlu_ctl.scala 1845:47] + fw_halted_ns <= _T_497 @[dec_tlu_ctl.scala 1845:15] + node _T_498 = bits(wr_mpmc_r, 0, 0) @[dec_tlu_ctl.scala 1846:29] + node _T_499 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1846:57] + node _T_500 = not(_T_499) @[dec_tlu_ctl.scala 1846:37] + node _T_501 = not(mpmc) @[dec_tlu_ctl.scala 1846:62] + node _T_502 = mux(_T_498, _T_500, _T_501) @[dec_tlu_ctl.scala 1846:18] + mpmc_b_ns <= _T_502 @[dec_tlu_ctl.scala 1846:12] + reg _T_503 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1848:44] + _T_503 <= mpmc_b_ns @[dec_tlu_ctl.scala 1848:44] + mpmc_b <= _T_503 @[dec_tlu_ctl.scala 1848:9] + node _T_504 = not(mpmc_b) @[dec_tlu_ctl.scala 1851:10] + mpmc <= _T_504 @[dec_tlu_ctl.scala 1851:7] + node _T_505 = bits(io.dec_csr_wrdata_r, 31, 27) @[dec_tlu_ctl.scala 1860:40] + node _T_506 = gt(_T_505, UInt<5>("h01a")) @[dec_tlu_ctl.scala 1860:48] + node _T_507 = bits(io.dec_csr_wrdata_r, 31, 27) @[dec_tlu_ctl.scala 1860:92] + node csr_sat = mux(_T_506, UInt<5>("h01a"), _T_507) @[dec_tlu_ctl.scala 1860:19] + node _T_508 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1862:63] + node _T_509 = eq(_T_508, UInt<12>("h07f0")) @[dec_tlu_ctl.scala 1862:70] + node wr_micect_r = and(io.dec_csr_wen_r_mod, _T_509) @[dec_tlu_ctl.scala 1862:41] + node _T_510 = cat(UInt<26>("h00"), io.ic_perr_r_d1) @[Cat.scala 29:58] + node _T_511 = add(micect, _T_510) @[dec_tlu_ctl.scala 1863:23] + node _T_512 = tail(_T_511, 1) @[dec_tlu_ctl.scala 1863:23] + micect_inc <= _T_512 @[dec_tlu_ctl.scala 1863:13] + node _T_513 = bits(wr_micect_r, 0, 0) @[dec_tlu_ctl.scala 1864:35] + node _T_514 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1864:75] + node _T_515 = cat(csr_sat, _T_514) @[Cat.scala 29:58] + node _T_516 = bits(micect, 31, 27) @[dec_tlu_ctl.scala 1864:95] + node _T_517 = cat(_T_516, micect_inc) @[Cat.scala 29:58] + node micect_ns = mux(_T_513, _T_515, _T_517) @[dec_tlu_ctl.scala 1864:22] + node _T_518 = or(wr_micect_r, io.ic_perr_r_d1) @[dec_tlu_ctl.scala 1866:42] + node _T_519 = bits(_T_518, 0, 0) @[dec_tlu_ctl.scala 1866:61] inst rvclkhdr_12 of rvclkhdr_732 @[lib.scala 368:23] rvclkhdr_12.clock <= clock rvclkhdr_12.reset <= reset rvclkhdr_12.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_12.io.en <= _T_529 @[lib.scala 371:17] + rvclkhdr_12.io.en <= _T_519 @[lib.scala 371:17] rvclkhdr_12.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_530 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_530 <= micect_ns @[lib.scala 374:16] - micect <= _T_530 @[dec_tlu_ctl.scala 1866:9] - node _T_531 = bits(micect, 31, 27) @[dec_tlu_ctl.scala 1868:48] - node _T_532 = dshl(UInt<32>("h0ffffffff"), _T_531) @[dec_tlu_ctl.scala 1868:39] - node _T_533 = bits(micect, 26, 0) @[dec_tlu_ctl.scala 1868:79] - node _T_534 = cat(UInt<5>("h00"), _T_533) @[Cat.scala 29:58] - node _T_535 = and(_T_532, _T_534) @[dec_tlu_ctl.scala 1868:57] - node _T_536 = orr(_T_535) @[dec_tlu_ctl.scala 1868:88] - mice_ce_req <= _T_536 @[dec_tlu_ctl.scala 1868:14] - node _T_537 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1877:69] - node _T_538 = eq(_T_537, UInt<12>("h07f1")) @[dec_tlu_ctl.scala 1877:76] - node wr_miccmect_r = and(io.dec_csr_wen_r_mod, _T_538) @[dec_tlu_ctl.scala 1877:47] - node _T_539 = bits(miccmect, 26, 0) @[dec_tlu_ctl.scala 1878:26] - node _T_540 = or(io.iccm_sbecc_r_d1, io.iccm_dma_sb_error) @[dec_tlu_ctl.scala 1878:70] - node _T_541 = cat(UInt<26>("h00"), _T_540) @[Cat.scala 29:58] - node _T_542 = add(_T_539, _T_541) @[dec_tlu_ctl.scala 1878:33] - node _T_543 = tail(_T_542, 1) @[dec_tlu_ctl.scala 1878:33] - miccmect_inc <= _T_543 @[dec_tlu_ctl.scala 1878:15] - node _T_544 = bits(wr_miccmect_r, 0, 0) @[dec_tlu_ctl.scala 1879:45] - node _T_545 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1879:85] - node _T_546 = cat(csr_sat, _T_545) @[Cat.scala 29:58] - node _T_547 = bits(miccmect, 31, 27) @[dec_tlu_ctl.scala 1879:107] - node _T_548 = cat(_T_547, miccmect_inc) @[Cat.scala 29:58] - node miccmect_ns = mux(_T_544, _T_546, _T_548) @[dec_tlu_ctl.scala 1879:30] - node _T_549 = or(wr_miccmect_r, io.iccm_sbecc_r_d1) @[dec_tlu_ctl.scala 1881:48] - node _T_550 = or(_T_549, io.iccm_dma_sb_error) @[dec_tlu_ctl.scala 1881:69] - node _T_551 = bits(_T_550, 0, 0) @[dec_tlu_ctl.scala 1881:93] + reg _T_520 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_520 <= micect_ns @[lib.scala 374:16] + micect <= _T_520 @[dec_tlu_ctl.scala 1866:9] + node _T_521 = bits(micect, 31, 27) @[dec_tlu_ctl.scala 1868:48] + node _T_522 = dshl(UInt<32>("h0ffffffff"), _T_521) @[dec_tlu_ctl.scala 1868:39] + node _T_523 = bits(micect, 26, 0) @[dec_tlu_ctl.scala 1868:79] + node _T_524 = cat(UInt<5>("h00"), _T_523) @[Cat.scala 29:58] + node _T_525 = and(_T_522, _T_524) @[dec_tlu_ctl.scala 1868:57] + node _T_526 = orr(_T_525) @[dec_tlu_ctl.scala 1868:88] + mice_ce_req <= _T_526 @[dec_tlu_ctl.scala 1868:14] + node _T_527 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1877:69] + node _T_528 = eq(_T_527, UInt<12>("h07f1")) @[dec_tlu_ctl.scala 1877:76] + node wr_miccmect_r = and(io.dec_csr_wen_r_mod, _T_528) @[dec_tlu_ctl.scala 1877:47] + node _T_529 = bits(miccmect, 26, 0) @[dec_tlu_ctl.scala 1878:26] + node _T_530 = or(io.iccm_sbecc_r_d1, io.iccm_dma_sb_error) @[dec_tlu_ctl.scala 1878:70] + node _T_531 = cat(UInt<26>("h00"), _T_530) @[Cat.scala 29:58] + node _T_532 = add(_T_529, _T_531) @[dec_tlu_ctl.scala 1878:33] + node _T_533 = tail(_T_532, 1) @[dec_tlu_ctl.scala 1878:33] + miccmect_inc <= _T_533 @[dec_tlu_ctl.scala 1878:15] + node _T_534 = bits(wr_miccmect_r, 0, 0) @[dec_tlu_ctl.scala 1879:45] + node _T_535 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1879:85] + node _T_536 = cat(csr_sat, _T_535) @[Cat.scala 29:58] + node _T_537 = bits(miccmect, 31, 27) @[dec_tlu_ctl.scala 1879:107] + node _T_538 = cat(_T_537, miccmect_inc) @[Cat.scala 29:58] + node miccmect_ns = mux(_T_534, _T_536, _T_538) @[dec_tlu_ctl.scala 1879:30] + node _T_539 = or(wr_miccmect_r, io.iccm_sbecc_r_d1) @[dec_tlu_ctl.scala 1881:48] + node _T_540 = or(_T_539, io.iccm_dma_sb_error) @[dec_tlu_ctl.scala 1881:69] + node _T_541 = bits(_T_540, 0, 0) @[dec_tlu_ctl.scala 1881:93] inst rvclkhdr_13 of rvclkhdr_733 @[lib.scala 368:23] rvclkhdr_13.clock <= clock rvclkhdr_13.reset <= reset rvclkhdr_13.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_13.io.en <= _T_551 @[lib.scala 371:17] + rvclkhdr_13.io.en <= _T_541 @[lib.scala 371:17] rvclkhdr_13.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_552 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_552 <= miccmect_ns @[lib.scala 374:16] - miccmect <= _T_552 @[dec_tlu_ctl.scala 1881:11] - node _T_553 = bits(miccmect, 31, 27) @[dec_tlu_ctl.scala 1883:51] - node _T_554 = dshl(UInt<32>("h0ffffffff"), _T_553) @[dec_tlu_ctl.scala 1883:40] - node _T_555 = bits(miccmect, 26, 0) @[dec_tlu_ctl.scala 1883:84] - node _T_556 = cat(UInt<5>("h00"), _T_555) @[Cat.scala 29:58] - node _T_557 = and(_T_554, _T_556) @[dec_tlu_ctl.scala 1883:60] - node _T_558 = orr(_T_557) @[dec_tlu_ctl.scala 1883:93] - miccme_ce_req <= _T_558 @[dec_tlu_ctl.scala 1883:15] - node _T_559 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1892:69] - node _T_560 = eq(_T_559, UInt<12>("h07f2")) @[dec_tlu_ctl.scala 1892:76] - node wr_mdccmect_r = and(io.dec_csr_wen_r_mod, _T_560) @[dec_tlu_ctl.scala 1892:47] - node _T_561 = bits(mdccmect, 26, 0) @[dec_tlu_ctl.scala 1893:26] - node _T_562 = cat(UInt<26>("h00"), io.lsu_single_ecc_error_r_d1) @[Cat.scala 29:58] - node _T_563 = add(_T_561, _T_562) @[dec_tlu_ctl.scala 1893:33] - node _T_564 = tail(_T_563, 1) @[dec_tlu_ctl.scala 1893:33] - mdccmect_inc <= _T_564 @[dec_tlu_ctl.scala 1893:15] - node _T_565 = bits(wr_mdccmect_r, 0, 0) @[dec_tlu_ctl.scala 1894:45] - node _T_566 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1894:85] - node _T_567 = cat(csr_sat, _T_566) @[Cat.scala 29:58] - node _T_568 = bits(mdccmect, 31, 27) @[dec_tlu_ctl.scala 1894:107] - node _T_569 = cat(_T_568, mdccmect_inc) @[Cat.scala 29:58] - node mdccmect_ns = mux(_T_565, _T_567, _T_569) @[dec_tlu_ctl.scala 1894:30] - node _T_570 = or(wr_mdccmect_r, io.lsu_single_ecc_error_r_d1) @[dec_tlu_ctl.scala 1896:49] - node _T_571 = bits(_T_570, 0, 0) @[dec_tlu_ctl.scala 1896:81] + reg _T_542 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_542 <= miccmect_ns @[lib.scala 374:16] + miccmect <= _T_542 @[dec_tlu_ctl.scala 1881:11] + node _T_543 = bits(miccmect, 31, 27) @[dec_tlu_ctl.scala 1883:51] + node _T_544 = dshl(UInt<32>("h0ffffffff"), _T_543) @[dec_tlu_ctl.scala 1883:40] + node _T_545 = bits(miccmect, 26, 0) @[dec_tlu_ctl.scala 1883:84] + node _T_546 = cat(UInt<5>("h00"), _T_545) @[Cat.scala 29:58] + node _T_547 = and(_T_544, _T_546) @[dec_tlu_ctl.scala 1883:60] + node _T_548 = orr(_T_547) @[dec_tlu_ctl.scala 1883:93] + miccme_ce_req <= _T_548 @[dec_tlu_ctl.scala 1883:15] + node _T_549 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1892:69] + node _T_550 = eq(_T_549, UInt<12>("h07f2")) @[dec_tlu_ctl.scala 1892:76] + node wr_mdccmect_r = and(io.dec_csr_wen_r_mod, _T_550) @[dec_tlu_ctl.scala 1892:47] + node _T_551 = bits(mdccmect, 26, 0) @[dec_tlu_ctl.scala 1893:26] + node _T_552 = cat(UInt<26>("h00"), io.lsu_single_ecc_error_r_d1) @[Cat.scala 29:58] + node _T_553 = add(_T_551, _T_552) @[dec_tlu_ctl.scala 1893:33] + node _T_554 = tail(_T_553, 1) @[dec_tlu_ctl.scala 1893:33] + mdccmect_inc <= _T_554 @[dec_tlu_ctl.scala 1893:15] + node _T_555 = bits(wr_mdccmect_r, 0, 0) @[dec_tlu_ctl.scala 1894:45] + node _T_556 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1894:85] + node _T_557 = cat(csr_sat, _T_556) @[Cat.scala 29:58] + node _T_558 = bits(mdccmect, 31, 27) @[dec_tlu_ctl.scala 1894:107] + node _T_559 = cat(_T_558, mdccmect_inc) @[Cat.scala 29:58] + node mdccmect_ns = mux(_T_555, _T_557, _T_559) @[dec_tlu_ctl.scala 1894:30] + node _T_560 = or(wr_mdccmect_r, io.lsu_single_ecc_error_r_d1) @[dec_tlu_ctl.scala 1896:49] + node _T_561 = bits(_T_560, 0, 0) @[dec_tlu_ctl.scala 1896:81] inst rvclkhdr_14 of rvclkhdr_734 @[lib.scala 368:23] rvclkhdr_14.clock <= clock rvclkhdr_14.reset <= reset rvclkhdr_14.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_14.io.en <= _T_571 @[lib.scala 371:17] + rvclkhdr_14.io.en <= _T_561 @[lib.scala 371:17] rvclkhdr_14.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_572 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_572 <= mdccmect_ns @[lib.scala 374:16] - mdccmect <= _T_572 @[dec_tlu_ctl.scala 1896:11] - node _T_573 = bits(mdccmect, 31, 27) @[dec_tlu_ctl.scala 1898:52] - node _T_574 = dshl(UInt<32>("h0ffffffff"), _T_573) @[dec_tlu_ctl.scala 1898:41] - node _T_575 = bits(mdccmect, 26, 0) @[dec_tlu_ctl.scala 1898:85] - node _T_576 = cat(UInt<5>("h00"), _T_575) @[Cat.scala 29:58] - node _T_577 = and(_T_574, _T_576) @[dec_tlu_ctl.scala 1898:61] - node _T_578 = orr(_T_577) @[dec_tlu_ctl.scala 1898:94] - mdccme_ce_req <= _T_578 @[dec_tlu_ctl.scala 1898:16] - node _T_579 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1908:62] - node _T_580 = eq(_T_579, UInt<12>("h07ce")) @[dec_tlu_ctl.scala 1908:69] - node wr_mfdht_r = and(io.dec_csr_wen_r_mod, _T_580) @[dec_tlu_ctl.scala 1908:40] - node _T_581 = bits(wr_mfdht_r, 0, 0) @[dec_tlu_ctl.scala 1910:32] - node _T_582 = bits(io.dec_csr_wrdata_r, 5, 0) @[dec_tlu_ctl.scala 1910:59] - node mfdht_ns = mux(_T_581, _T_582, mfdht) @[dec_tlu_ctl.scala 1910:20] - reg _T_583 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1912:43] - _T_583 <= mfdht_ns @[dec_tlu_ctl.scala 1912:43] - mfdht <= _T_583 @[dec_tlu_ctl.scala 1912:8] - node _T_584 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1921:62] - node _T_585 = eq(_T_584, UInt<12>("h07cf")) @[dec_tlu_ctl.scala 1921:69] - node wr_mfdhs_r = and(io.dec_csr_wen_r_mod, _T_585) @[dec_tlu_ctl.scala 1921:40] - node _T_586 = bits(wr_mfdhs_r, 0, 0) @[dec_tlu_ctl.scala 1923:32] - node _T_587 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 1923:60] - node _T_588 = not(io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 1924:43] - node _T_589 = and(io.dbg_tlu_halted, _T_588) @[dec_tlu_ctl.scala 1924:41] - node _T_590 = bits(_T_589, 0, 0) @[dec_tlu_ctl.scala 1924:65] - node _T_591 = not(io.lsu_idle_any_f) @[dec_tlu_ctl.scala 1924:78] - node _T_592 = not(io.ifu_miss_state_idle_f) @[dec_tlu_ctl.scala 1924:98] - node _T_593 = cat(_T_591, _T_592) @[Cat.scala 29:58] - node _T_594 = mux(_T_590, _T_593, mfdhs) @[dec_tlu_ctl.scala 1924:21] - node mfdhs_ns = mux(_T_586, _T_587, _T_594) @[dec_tlu_ctl.scala 1923:20] - node _T_595 = or(wr_mfdhs_r, io.dbg_tlu_halted) @[dec_tlu_ctl.scala 1926:71] - node _T_596 = bits(_T_595, 0, 0) @[dec_tlu_ctl.scala 1926:92] - reg _T_597 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_596 : @[Reg.scala 28:19] - _T_597 <= mfdhs_ns @[Reg.scala 28:23] + reg _T_562 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_562 <= mdccmect_ns @[lib.scala 374:16] + mdccmect <= _T_562 @[dec_tlu_ctl.scala 1896:11] + node _T_563 = bits(mdccmect, 31, 27) @[dec_tlu_ctl.scala 1898:52] + node _T_564 = dshl(UInt<32>("h0ffffffff"), _T_563) @[dec_tlu_ctl.scala 1898:41] + node _T_565 = bits(mdccmect, 26, 0) @[dec_tlu_ctl.scala 1898:85] + node _T_566 = cat(UInt<5>("h00"), _T_565) @[Cat.scala 29:58] + node _T_567 = and(_T_564, _T_566) @[dec_tlu_ctl.scala 1898:61] + node _T_568 = orr(_T_567) @[dec_tlu_ctl.scala 1898:94] + mdccme_ce_req <= _T_568 @[dec_tlu_ctl.scala 1898:16] + node _T_569 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1908:62] + node _T_570 = eq(_T_569, UInt<12>("h07ce")) @[dec_tlu_ctl.scala 1908:69] + node wr_mfdht_r = and(io.dec_csr_wen_r_mod, _T_570) @[dec_tlu_ctl.scala 1908:40] + node _T_571 = bits(wr_mfdht_r, 0, 0) @[dec_tlu_ctl.scala 1910:32] + node _T_572 = bits(io.dec_csr_wrdata_r, 5, 0) @[dec_tlu_ctl.scala 1910:59] + node mfdht_ns = mux(_T_571, _T_572, mfdht) @[dec_tlu_ctl.scala 1910:20] + reg _T_573 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1912:43] + _T_573 <= mfdht_ns @[dec_tlu_ctl.scala 1912:43] + mfdht <= _T_573 @[dec_tlu_ctl.scala 1912:8] + node _T_574 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1921:62] + node _T_575 = eq(_T_574, UInt<12>("h07cf")) @[dec_tlu_ctl.scala 1921:69] + node wr_mfdhs_r = and(io.dec_csr_wen_r_mod, _T_575) @[dec_tlu_ctl.scala 1921:40] + node _T_576 = bits(wr_mfdhs_r, 0, 0) @[dec_tlu_ctl.scala 1923:32] + node _T_577 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 1923:60] + node _T_578 = not(io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 1924:43] + node _T_579 = and(io.dbg_tlu_halted, _T_578) @[dec_tlu_ctl.scala 1924:41] + node _T_580 = bits(_T_579, 0, 0) @[dec_tlu_ctl.scala 1924:65] + node _T_581 = not(io.lsu_idle_any_f) @[dec_tlu_ctl.scala 1924:78] + node _T_582 = not(io.ifu_miss_state_idle_f) @[dec_tlu_ctl.scala 1924:98] + node _T_583 = cat(_T_581, _T_582) @[Cat.scala 29:58] + node _T_584 = mux(_T_580, _T_583, mfdhs) @[dec_tlu_ctl.scala 1924:21] + node mfdhs_ns = mux(_T_576, _T_577, _T_584) @[dec_tlu_ctl.scala 1923:20] + node _T_585 = or(wr_mfdhs_r, io.dbg_tlu_halted) @[dec_tlu_ctl.scala 1926:71] + node _T_586 = bits(_T_585, 0, 0) @[dec_tlu_ctl.scala 1926:92] + reg _T_587 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_586 : @[Reg.scala 28:19] + _T_587 <= mfdhs_ns @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mfdhs <= _T_597 @[dec_tlu_ctl.scala 1926:8] - node _T_598 = bits(io.debug_halt_req_f, 0, 0) @[dec_tlu_ctl.scala 1928:47] - node _T_599 = add(force_halt_ctr_f, UInt<32>("h01")) @[dec_tlu_ctl.scala 1928:74] - node _T_600 = tail(_T_599, 1) @[dec_tlu_ctl.scala 1928:74] - node _T_601 = bits(io.dbg_tlu_halted_f, 0, 0) @[dec_tlu_ctl.scala 1929:48] - node _T_602 = mux(_T_601, UInt<32>("h00"), force_halt_ctr_f) @[dec_tlu_ctl.scala 1929:27] - node force_halt_ctr = mux(_T_598, _T_600, _T_602) @[dec_tlu_ctl.scala 1928:26] - node _T_603 = bits(mfdht, 0, 0) @[dec_tlu_ctl.scala 1931:81] - reg _T_604 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_603 : @[Reg.scala 28:19] - _T_604 <= force_halt_ctr @[Reg.scala 28:23] + mfdhs <= _T_587 @[dec_tlu_ctl.scala 1926:8] + node _T_588 = bits(io.debug_halt_req_f, 0, 0) @[dec_tlu_ctl.scala 1928:47] + node _T_589 = add(force_halt_ctr_f, UInt<32>("h01")) @[dec_tlu_ctl.scala 1928:74] + node _T_590 = tail(_T_589, 1) @[dec_tlu_ctl.scala 1928:74] + node _T_591 = bits(io.dbg_tlu_halted_f, 0, 0) @[dec_tlu_ctl.scala 1929:48] + node _T_592 = mux(_T_591, UInt<32>("h00"), force_halt_ctr_f) @[dec_tlu_ctl.scala 1929:27] + node force_halt_ctr = mux(_T_588, _T_590, _T_592) @[dec_tlu_ctl.scala 1928:26] + node _T_593 = bits(mfdht, 0, 0) @[dec_tlu_ctl.scala 1931:81] + reg _T_594 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_593 : @[Reg.scala 28:19] + _T_594 <= force_halt_ctr @[Reg.scala 28:23] skip @[Reg.scala 28:19] - force_halt_ctr_f <= _T_604 @[dec_tlu_ctl.scala 1931:19] - node _T_605 = bits(mfdht, 0, 0) @[dec_tlu_ctl.scala 1933:24] - node _T_606 = bits(mfdht, 5, 1) @[dec_tlu_ctl.scala 1933:79] - node _T_607 = dshl(UInt<32>("h0ffffffff"), _T_606) @[dec_tlu_ctl.scala 1933:71] - node _T_608 = and(force_halt_ctr_f, _T_607) @[dec_tlu_ctl.scala 1933:48] - node _T_609 = orr(_T_608) @[dec_tlu_ctl.scala 1933:87] - node _T_610 = and(_T_605, _T_609) @[dec_tlu_ctl.scala 1933:28] - io.force_halt <= _T_610 @[dec_tlu_ctl.scala 1933:16] - node _T_611 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1941:62] - node _T_612 = eq(_T_611, UInt<12>("h0bc8")) @[dec_tlu_ctl.scala 1941:69] - node wr_meivt_r = and(io.dec_csr_wen_r_mod, _T_612) @[dec_tlu_ctl.scala 1941:40] - node _T_613 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 1943:40] - node _T_614 = bits(wr_meivt_r, 0, 0) @[dec_tlu_ctl.scala 1943:59] + force_halt_ctr_f <= _T_594 @[dec_tlu_ctl.scala 1931:19] + node _T_595 = bits(mfdht, 0, 0) @[dec_tlu_ctl.scala 1933:24] + node _T_596 = bits(mfdht, 5, 1) @[dec_tlu_ctl.scala 1933:79] + node _T_597 = dshl(UInt<32>("h0ffffffff"), _T_596) @[dec_tlu_ctl.scala 1933:71] + node _T_598 = and(force_halt_ctr_f, _T_597) @[dec_tlu_ctl.scala 1933:48] + node _T_599 = orr(_T_598) @[dec_tlu_ctl.scala 1933:87] + node _T_600 = and(_T_595, _T_599) @[dec_tlu_ctl.scala 1933:28] + io.force_halt <= _T_600 @[dec_tlu_ctl.scala 1933:16] + node _T_601 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1941:62] + node _T_602 = eq(_T_601, UInt<12>("h0bc8")) @[dec_tlu_ctl.scala 1941:69] + node wr_meivt_r = and(io.dec_csr_wen_r_mod, _T_602) @[dec_tlu_ctl.scala 1941:40] + node _T_603 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 1943:40] + node _T_604 = bits(wr_meivt_r, 0, 0) @[dec_tlu_ctl.scala 1943:59] inst rvclkhdr_15 of rvclkhdr_735 @[lib.scala 368:23] rvclkhdr_15.clock <= clock rvclkhdr_15.reset <= reset rvclkhdr_15.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_15.io.en <= _T_614 @[lib.scala 371:17] + rvclkhdr_15.io.en <= _T_604 @[lib.scala 371:17] rvclkhdr_15.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg meivt : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - meivt <= _T_613 @[lib.scala 374:16] - node _T_615 = bits(wr_meicpct_r, 0, 0) @[dec_tlu_ctl.scala 1955:49] + meivt <= _T_603 @[lib.scala 374:16] + node _T_605 = bits(wr_meicpct_r, 0, 0) @[dec_tlu_ctl.scala 1955:49] inst rvclkhdr_16 of rvclkhdr_736 @[lib.scala 368:23] rvclkhdr_16.clock <= clock rvclkhdr_16.reset <= reset rvclkhdr_16.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_16.io.en <= _T_615 @[lib.scala 371:17] + rvclkhdr_16.io.en <= _T_605 @[lib.scala 371:17] rvclkhdr_16.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg meihap : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] meihap <= io.pic_claimid @[lib.scala 374:16] - node _T_616 = cat(meivt, meihap) @[Cat.scala 29:58] - io.dec_tlu_meihap <= _T_616 @[dec_tlu_ctl.scala 1956:20] - node _T_617 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1965:65] - node _T_618 = eq(_T_617, UInt<12>("h0bcc")) @[dec_tlu_ctl.scala 1965:72] - node wr_meicurpl_r = and(io.dec_csr_wen_r_mod, _T_618) @[dec_tlu_ctl.scala 1965:43] - node _T_619 = bits(wr_meicurpl_r, 0, 0) @[dec_tlu_ctl.scala 1966:38] - node _T_620 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1966:65] - node meicurpl_ns = mux(_T_619, _T_620, meicurpl) @[dec_tlu_ctl.scala 1966:23] - reg _T_621 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1968:46] - _T_621 <= meicurpl_ns @[dec_tlu_ctl.scala 1968:46] - meicurpl <= _T_621 @[dec_tlu_ctl.scala 1968:11] + node _T_606 = cat(meivt, meihap) @[Cat.scala 29:58] + io.dec_tlu_meihap <= _T_606 @[dec_tlu_ctl.scala 1956:20] + node _T_607 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1965:65] + node _T_608 = eq(_T_607, UInt<12>("h0bcc")) @[dec_tlu_ctl.scala 1965:72] + node wr_meicurpl_r = and(io.dec_csr_wen_r_mod, _T_608) @[dec_tlu_ctl.scala 1965:43] + node _T_609 = bits(wr_meicurpl_r, 0, 0) @[dec_tlu_ctl.scala 1966:38] + node _T_610 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1966:65] + node meicurpl_ns = mux(_T_609, _T_610, meicurpl) @[dec_tlu_ctl.scala 1966:23] + reg _T_611 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1968:46] + _T_611 <= meicurpl_ns @[dec_tlu_ctl.scala 1968:46] + meicurpl <= _T_611 @[dec_tlu_ctl.scala 1968:11] io.dec_tlu_meicurpl <= meicurpl @[dec_tlu_ctl.scala 1970:22] - node _T_622 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1980:66] - node _T_623 = eq(_T_622, UInt<12>("h0bcb")) @[dec_tlu_ctl.scala 1980:73] - node _T_624 = and(io.dec_csr_wen_r_mod, _T_623) @[dec_tlu_ctl.scala 1980:44] - node wr_meicidpl_r = or(_T_624, io.take_ext_int_start) @[dec_tlu_ctl.scala 1980:88] - node _T_625 = bits(wr_meicpct_r, 0, 0) @[dec_tlu_ctl.scala 1982:37] - node _T_626 = bits(wr_meicidpl_r, 0, 0) @[dec_tlu_ctl.scala 1983:38] - node _T_627 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1983:65] - node _T_628 = mux(_T_626, _T_627, meicidpl) @[dec_tlu_ctl.scala 1983:23] - node meicidpl_ns = mux(_T_625, io.pic_pl, _T_628) @[dec_tlu_ctl.scala 1982:23] - reg _T_629 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1985:44] - _T_629 <= meicidpl_ns @[dec_tlu_ctl.scala 1985:44] - meicidpl <= _T_629 @[dec_tlu_ctl.scala 1985:11] - node _T_630 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1992:62] - node _T_631 = eq(_T_630, UInt<12>("h0bca")) @[dec_tlu_ctl.scala 1992:69] - node _T_632 = and(io.dec_csr_wen_r_mod, _T_631) @[dec_tlu_ctl.scala 1992:40] - node _T_633 = or(_T_632, io.take_ext_int_start) @[dec_tlu_ctl.scala 1992:83] - wr_meicpct_r <= _T_633 @[dec_tlu_ctl.scala 1992:15] - node _T_634 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2001:62] - node _T_635 = eq(_T_634, UInt<12>("h0bc9")) @[dec_tlu_ctl.scala 2001:69] - node wr_meipt_r = and(io.dec_csr_wen_r_mod, _T_635) @[dec_tlu_ctl.scala 2001:40] - node _T_636 = bits(wr_meipt_r, 0, 0) @[dec_tlu_ctl.scala 2002:32] - node _T_637 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 2002:59] - node meipt_ns = mux(_T_636, _T_637, meipt) @[dec_tlu_ctl.scala 2002:20] - reg _T_638 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2004:43] - _T_638 <= meipt_ns @[dec_tlu_ctl.scala 2004:43] - meipt <= _T_638 @[dec_tlu_ctl.scala 2004:8] + node _T_612 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1980:66] + node _T_613 = eq(_T_612, UInt<12>("h0bcb")) @[dec_tlu_ctl.scala 1980:73] + node _T_614 = and(io.dec_csr_wen_r_mod, _T_613) @[dec_tlu_ctl.scala 1980:44] + node wr_meicidpl_r = or(_T_614, io.take_ext_int_start) @[dec_tlu_ctl.scala 1980:88] + node _T_615 = bits(wr_meicpct_r, 0, 0) @[dec_tlu_ctl.scala 1982:37] + node _T_616 = bits(wr_meicidpl_r, 0, 0) @[dec_tlu_ctl.scala 1983:38] + node _T_617 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1983:65] + node _T_618 = mux(_T_616, _T_617, meicidpl) @[dec_tlu_ctl.scala 1983:23] + node meicidpl_ns = mux(_T_615, io.pic_pl, _T_618) @[dec_tlu_ctl.scala 1982:23] + reg _T_619 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1985:44] + _T_619 <= meicidpl_ns @[dec_tlu_ctl.scala 1985:44] + meicidpl <= _T_619 @[dec_tlu_ctl.scala 1985:11] + node _T_620 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1992:62] + node _T_621 = eq(_T_620, UInt<12>("h0bca")) @[dec_tlu_ctl.scala 1992:69] + node _T_622 = and(io.dec_csr_wen_r_mod, _T_621) @[dec_tlu_ctl.scala 1992:40] + node _T_623 = or(_T_622, io.take_ext_int_start) @[dec_tlu_ctl.scala 1992:83] + wr_meicpct_r <= _T_623 @[dec_tlu_ctl.scala 1992:15] + node _T_624 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2001:62] + node _T_625 = eq(_T_624, UInt<12>("h0bc9")) @[dec_tlu_ctl.scala 2001:69] + node wr_meipt_r = and(io.dec_csr_wen_r_mod, _T_625) @[dec_tlu_ctl.scala 2001:40] + node _T_626 = bits(wr_meipt_r, 0, 0) @[dec_tlu_ctl.scala 2002:32] + node _T_627 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 2002:59] + node meipt_ns = mux(_T_626, _T_627, meipt) @[dec_tlu_ctl.scala 2002:20] + reg _T_628 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2004:43] + _T_628 <= meipt_ns @[dec_tlu_ctl.scala 2004:43] + meipt <= _T_628 @[dec_tlu_ctl.scala 2004:8] io.dec_tlu_meipt <= meipt @[dec_tlu_ctl.scala 2006:19] - node _T_639 = and(io.trigger_hit_r_d1, io.dcsr_single_step_done_f) @[dec_tlu_ctl.scala 2032:89] - node trigger_hit_for_dscr_cause_r_d1 = or(io.trigger_hit_dmode_r_d1, _T_639) @[dec_tlu_ctl.scala 2032:66] - node _T_640 = not(io.ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 2035:31] - node _T_641 = and(io.dcsr_single_step_done_f, _T_640) @[dec_tlu_ctl.scala 2035:29] - node _T_642 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2035:63] - node _T_643 = and(_T_641, _T_642) @[dec_tlu_ctl.scala 2035:61] - node _T_644 = not(io.debug_halt_req) @[dec_tlu_ctl.scala 2035:98] - node _T_645 = and(_T_643, _T_644) @[dec_tlu_ctl.scala 2035:96] - node _T_646 = bits(_T_645, 0, 0) @[dec_tlu_ctl.scala 2035:118] - node _T_647 = not(io.ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 2036:48] - node _T_648 = and(io.debug_halt_req, _T_647) @[dec_tlu_ctl.scala 2036:46] - node _T_649 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2036:80] - node _T_650 = and(_T_648, _T_649) @[dec_tlu_ctl.scala 2036:78] - node _T_651 = bits(_T_650, 0, 0) @[dec_tlu_ctl.scala 2036:114] - node _T_652 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2037:77] - node _T_653 = and(io.ebreak_to_debug_mode_r_d1, _T_652) @[dec_tlu_ctl.scala 2037:75] - node _T_654 = bits(_T_653, 0, 0) @[dec_tlu_ctl.scala 2037:111] - node _T_655 = bits(trigger_hit_for_dscr_cause_r_d1, 0, 0) @[dec_tlu_ctl.scala 2038:108] - node _T_656 = mux(_T_646, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_657 = mux(_T_651, UInt<3>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_658 = mux(_T_654, UInt<3>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_659 = mux(_T_655, UInt<3>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_660 = or(_T_656, _T_657) @[Mux.scala 27:72] - node _T_661 = or(_T_660, _T_658) @[Mux.scala 27:72] - node _T_662 = or(_T_661, _T_659) @[Mux.scala 27:72] + node _T_629 = and(io.trigger_hit_r_d1, io.dcsr_single_step_done_f) @[dec_tlu_ctl.scala 2032:89] + node trigger_hit_for_dscr_cause_r_d1 = or(io.trigger_hit_dmode_r_d1, _T_629) @[dec_tlu_ctl.scala 2032:66] + node _T_630 = not(io.ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 2035:31] + node _T_631 = and(io.dcsr_single_step_done_f, _T_630) @[dec_tlu_ctl.scala 2035:29] + node _T_632 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2035:63] + node _T_633 = and(_T_631, _T_632) @[dec_tlu_ctl.scala 2035:61] + node _T_634 = not(io.debug_halt_req) @[dec_tlu_ctl.scala 2035:98] + node _T_635 = and(_T_633, _T_634) @[dec_tlu_ctl.scala 2035:96] + node _T_636 = bits(_T_635, 0, 0) @[dec_tlu_ctl.scala 2035:118] + node _T_637 = not(io.ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 2036:48] + node _T_638 = and(io.debug_halt_req, _T_637) @[dec_tlu_ctl.scala 2036:46] + node _T_639 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2036:80] + node _T_640 = and(_T_638, _T_639) @[dec_tlu_ctl.scala 2036:78] + node _T_641 = bits(_T_640, 0, 0) @[dec_tlu_ctl.scala 2036:114] + node _T_642 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2037:77] + node _T_643 = and(io.ebreak_to_debug_mode_r_d1, _T_642) @[dec_tlu_ctl.scala 2037:75] + node _T_644 = bits(_T_643, 0, 0) @[dec_tlu_ctl.scala 2037:111] + node _T_645 = bits(trigger_hit_for_dscr_cause_r_d1, 0, 0) @[dec_tlu_ctl.scala 2038:108] + node _T_646 = mux(_T_636, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_647 = mux(_T_641, UInt<3>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_648 = mux(_T_644, UInt<3>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_649 = mux(_T_645, UInt<3>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_650 = or(_T_646, _T_647) @[Mux.scala 27:72] + node _T_651 = or(_T_650, _T_648) @[Mux.scala 27:72] + node _T_652 = or(_T_651, _T_649) @[Mux.scala 27:72] wire dcsr_cause : UInt<3> @[Mux.scala 27:72] - dcsr_cause <= _T_662 @[Mux.scala 27:72] - node _T_663 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2040:46] - node _T_664 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2040:91] - node _T_665 = eq(_T_664, UInt<12>("h07b0")) @[dec_tlu_ctl.scala 2040:98] - node wr_dcsr_r = and(_T_663, _T_665) @[dec_tlu_ctl.scala 2040:69] - node _T_666 = bits(io.dcsr, 8, 6) @[dec_tlu_ctl.scala 2046:69] - node _T_667 = eq(_T_666, UInt<3>("h03")) @[dec_tlu_ctl.scala 2046:75] - node dcsr_cause_upgradeable = and(io.internal_dbg_halt_mode_f, _T_667) @[dec_tlu_ctl.scala 2046:59] - node _T_668 = not(io.dbg_tlu_halted) @[dec_tlu_ctl.scala 2047:59] - node _T_669 = or(_T_668, dcsr_cause_upgradeable) @[dec_tlu_ctl.scala 2047:78] - node enter_debug_halt_req_le = and(io.enter_debug_halt_req, _T_669) @[dec_tlu_ctl.scala 2047:56] + dcsr_cause <= _T_652 @[Mux.scala 27:72] + node _T_653 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2040:46] + node _T_654 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2040:91] + node _T_655 = eq(_T_654, UInt<12>("h07b0")) @[dec_tlu_ctl.scala 2040:98] + node wr_dcsr_r = and(_T_653, _T_655) @[dec_tlu_ctl.scala 2040:69] + node _T_656 = bits(io.dcsr, 8, 6) @[dec_tlu_ctl.scala 2046:69] + node _T_657 = eq(_T_656, UInt<3>("h03")) @[dec_tlu_ctl.scala 2046:75] + node dcsr_cause_upgradeable = and(io.internal_dbg_halt_mode_f, _T_657) @[dec_tlu_ctl.scala 2046:59] + node _T_658 = not(io.dbg_tlu_halted) @[dec_tlu_ctl.scala 2047:59] + node _T_659 = or(_T_658, dcsr_cause_upgradeable) @[dec_tlu_ctl.scala 2047:78] + node enter_debug_halt_req_le = and(io.enter_debug_halt_req, _T_659) @[dec_tlu_ctl.scala 2047:56] node nmi_in_debug_mode = and(io.nmi_int_detected_f, io.internal_dbg_halt_mode_f) @[dec_tlu_ctl.scala 2049:48] - node _T_670 = bits(enter_debug_halt_req_le, 0, 0) @[dec_tlu_ctl.scala 2050:44] - node _T_671 = bits(io.dcsr, 15, 9) @[dec_tlu_ctl.scala 2050:64] - node _T_672 = bits(io.dcsr, 5, 2) @[dec_tlu_ctl.scala 2050:91] + node _T_660 = bits(enter_debug_halt_req_le, 0, 0) @[dec_tlu_ctl.scala 2050:44] + node _T_661 = bits(io.dcsr, 15, 9) @[dec_tlu_ctl.scala 2050:64] + node _T_662 = bits(io.dcsr, 5, 2) @[dec_tlu_ctl.scala 2050:91] + node _T_663 = cat(_T_662, UInt<2>("h03")) @[Cat.scala 29:58] + node _T_664 = cat(_T_661, dcsr_cause) @[Cat.scala 29:58] + node _T_665 = cat(_T_664, _T_663) @[Cat.scala 29:58] + node _T_666 = bits(wr_dcsr_r, 0, 0) @[dec_tlu_ctl.scala 2051:18] + node _T_667 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 2051:49] + node _T_668 = bits(io.dec_csr_wrdata_r, 11, 10) @[dec_tlu_ctl.scala 2051:84] + node _T_669 = bits(io.dcsr, 8, 6) @[dec_tlu_ctl.scala 2051:110] + node _T_670 = bits(io.dcsr, 3, 3) @[dec_tlu_ctl.scala 2051:154] + node _T_671 = or(nmi_in_debug_mode, _T_670) @[dec_tlu_ctl.scala 2051:145] + node _T_672 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2051:178] node _T_673 = cat(_T_672, UInt<2>("h03")) @[Cat.scala 29:58] - node _T_674 = cat(_T_671, dcsr_cause) @[Cat.scala 29:58] + node _T_674 = cat(UInt<2>("h00"), _T_671) @[Cat.scala 29:58] node _T_675 = cat(_T_674, _T_673) @[Cat.scala 29:58] - node _T_676 = bits(wr_dcsr_r, 0, 0) @[dec_tlu_ctl.scala 2051:18] - node _T_677 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 2051:49] - node _T_678 = bits(io.dec_csr_wrdata_r, 11, 10) @[dec_tlu_ctl.scala 2051:84] - node _T_679 = bits(io.dcsr, 8, 6) @[dec_tlu_ctl.scala 2051:110] - node _T_680 = bits(io.dcsr, 3, 3) @[dec_tlu_ctl.scala 2051:154] - node _T_681 = or(nmi_in_debug_mode, _T_680) @[dec_tlu_ctl.scala 2051:145] - node _T_682 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2051:178] + node _T_676 = cat(UInt<1>("h00"), _T_669) @[Cat.scala 29:58] + node _T_677 = cat(_T_667, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_678 = cat(_T_677, _T_668) @[Cat.scala 29:58] + node _T_679 = cat(_T_678, _T_676) @[Cat.scala 29:58] + node _T_680 = cat(_T_679, _T_675) @[Cat.scala 29:58] + node _T_681 = bits(io.dcsr, 15, 4) @[dec_tlu_ctl.scala 2051:211] + node _T_682 = bits(io.dcsr, 2, 2) @[dec_tlu_ctl.scala 2051:245] node _T_683 = cat(_T_682, UInt<2>("h03")) @[Cat.scala 29:58] - node _T_684 = cat(UInt<2>("h00"), _T_681) @[Cat.scala 29:58] + node _T_684 = cat(_T_681, nmi_in_debug_mode) @[Cat.scala 29:58] node _T_685 = cat(_T_684, _T_683) @[Cat.scala 29:58] - node _T_686 = cat(UInt<1>("h00"), _T_679) @[Cat.scala 29:58] - node _T_687 = cat(_T_677, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_688 = cat(_T_687, _T_678) @[Cat.scala 29:58] - node _T_689 = cat(_T_688, _T_686) @[Cat.scala 29:58] - node _T_690 = cat(_T_689, _T_685) @[Cat.scala 29:58] - node _T_691 = bits(io.dcsr, 15, 4) @[dec_tlu_ctl.scala 2051:211] - node _T_692 = bits(io.dcsr, 2, 2) @[dec_tlu_ctl.scala 2051:245] - node _T_693 = cat(_T_692, UInt<2>("h03")) @[Cat.scala 29:58] - node _T_694 = cat(_T_691, nmi_in_debug_mode) @[Cat.scala 29:58] - node _T_695 = cat(_T_694, _T_693) @[Cat.scala 29:58] - node _T_696 = mux(_T_676, _T_690, _T_695) @[dec_tlu_ctl.scala 2051:7] - node dcsr_ns = mux(_T_670, _T_675, _T_696) @[dec_tlu_ctl.scala 2050:19] - node _T_697 = or(enter_debug_halt_req_le, wr_dcsr_r) @[dec_tlu_ctl.scala 2053:54] - node _T_698 = or(_T_697, io.internal_dbg_halt_mode) @[dec_tlu_ctl.scala 2053:66] - node _T_699 = or(_T_698, io.take_nmi) @[dec_tlu_ctl.scala 2053:94] - node _T_700 = bits(_T_699, 0, 0) @[dec_tlu_ctl.scala 2053:109] + node _T_686 = mux(_T_666, _T_680, _T_685) @[dec_tlu_ctl.scala 2051:7] + node dcsr_ns = mux(_T_660, _T_665, _T_686) @[dec_tlu_ctl.scala 2050:19] + node _T_687 = or(enter_debug_halt_req_le, wr_dcsr_r) @[dec_tlu_ctl.scala 2053:54] + node _T_688 = or(_T_687, io.internal_dbg_halt_mode) @[dec_tlu_ctl.scala 2053:66] + node _T_689 = or(_T_688, io.take_nmi) @[dec_tlu_ctl.scala 2053:94] + node _T_690 = bits(_T_689, 0, 0) @[dec_tlu_ctl.scala 2053:109] inst rvclkhdr_17 of rvclkhdr_737 @[lib.scala 368:23] rvclkhdr_17.clock <= clock rvclkhdr_17.reset <= reset rvclkhdr_17.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_17.io.en <= _T_700 @[lib.scala 371:17] + rvclkhdr_17.io.en <= _T_690 @[lib.scala 371:17] rvclkhdr_17.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_701 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_701 <= dcsr_ns @[lib.scala 374:16] - io.dcsr <= _T_701 @[dec_tlu_ctl.scala 2053:10] - node _T_702 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2061:45] - node _T_703 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2061:90] - node _T_704 = eq(_T_703, UInt<12>("h07b1")) @[dec_tlu_ctl.scala 2061:97] - node wr_dpc_r = and(_T_702, _T_704) @[dec_tlu_ctl.scala 2061:68] - node _T_705 = not(io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2062:44] - node _T_706 = and(io.dbg_tlu_halted, _T_705) @[dec_tlu_ctl.scala 2062:42] - node _T_707 = not(io.request_debug_mode_done) @[dec_tlu_ctl.scala 2062:67] - node dpc_capture_npc = and(_T_706, _T_707) @[dec_tlu_ctl.scala 2062:65] - node _T_708 = not(io.request_debug_mode_r) @[dec_tlu_ctl.scala 2066:21] - node _T_709 = not(dpc_capture_npc) @[dec_tlu_ctl.scala 2066:39] - node _T_710 = and(_T_708, _T_709) @[dec_tlu_ctl.scala 2066:37] - node _T_711 = and(_T_710, wr_dpc_r) @[dec_tlu_ctl.scala 2066:56] - node _T_712 = bits(_T_711, 0, 0) @[dec_tlu_ctl.scala 2066:68] - node _T_713 = bits(io.dec_csr_wrdata_r, 31, 1) @[dec_tlu_ctl.scala 2066:97] - node _T_714 = bits(io.request_debug_mode_r, 0, 0) @[dec_tlu_ctl.scala 2067:68] - node _T_715 = not(io.request_debug_mode_r) @[dec_tlu_ctl.scala 2068:33] - node _T_716 = and(_T_715, dpc_capture_npc) @[dec_tlu_ctl.scala 2068:49] - node _T_717 = bits(_T_716, 0, 0) @[dec_tlu_ctl.scala 2068:68] - node _T_718 = mux(_T_712, _T_713, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_719 = mux(_T_714, pc_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_720 = mux(_T_717, io.npc_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_721 = or(_T_718, _T_719) @[Mux.scala 27:72] - node _T_722 = or(_T_721, _T_720) @[Mux.scala 27:72] + reg _T_691 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_691 <= dcsr_ns @[lib.scala 374:16] + io.dcsr <= _T_691 @[dec_tlu_ctl.scala 2053:10] + node _T_692 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2061:45] + node _T_693 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2061:90] + node _T_694 = eq(_T_693, UInt<12>("h07b1")) @[dec_tlu_ctl.scala 2061:97] + node wr_dpc_r = and(_T_692, _T_694) @[dec_tlu_ctl.scala 2061:68] + node _T_695 = not(io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2062:44] + node _T_696 = and(io.dbg_tlu_halted, _T_695) @[dec_tlu_ctl.scala 2062:42] + node _T_697 = not(io.request_debug_mode_done) @[dec_tlu_ctl.scala 2062:67] + node dpc_capture_npc = and(_T_696, _T_697) @[dec_tlu_ctl.scala 2062:65] + node _T_698 = not(io.request_debug_mode_r) @[dec_tlu_ctl.scala 2066:21] + node _T_699 = not(dpc_capture_npc) @[dec_tlu_ctl.scala 2066:39] + node _T_700 = and(_T_698, _T_699) @[dec_tlu_ctl.scala 2066:37] + node _T_701 = and(_T_700, wr_dpc_r) @[dec_tlu_ctl.scala 2066:56] + node _T_702 = bits(_T_701, 0, 0) @[dec_tlu_ctl.scala 2066:68] + node _T_703 = bits(io.dec_csr_wrdata_r, 31, 1) @[dec_tlu_ctl.scala 2066:97] + node _T_704 = bits(io.request_debug_mode_r, 0, 0) @[dec_tlu_ctl.scala 2067:68] + node _T_705 = not(io.request_debug_mode_r) @[dec_tlu_ctl.scala 2068:33] + node _T_706 = and(_T_705, dpc_capture_npc) @[dec_tlu_ctl.scala 2068:49] + node _T_707 = bits(_T_706, 0, 0) @[dec_tlu_ctl.scala 2068:68] + node _T_708 = mux(_T_702, _T_703, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_709 = mux(_T_704, pc_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_710 = mux(_T_707, io.npc_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_711 = or(_T_708, _T_709) @[Mux.scala 27:72] + node _T_712 = or(_T_711, _T_710) @[Mux.scala 27:72] wire dpc_ns : UInt<31> @[Mux.scala 27:72] - dpc_ns <= _T_722 @[Mux.scala 27:72] - node _T_723 = or(wr_dpc_r, io.request_debug_mode_r) @[dec_tlu_ctl.scala 2070:36] - node _T_724 = or(_T_723, dpc_capture_npc) @[dec_tlu_ctl.scala 2070:53] - node _T_725 = bits(_T_724, 0, 0) @[dec_tlu_ctl.scala 2070:72] + dpc_ns <= _T_712 @[Mux.scala 27:72] + node _T_713 = or(wr_dpc_r, io.request_debug_mode_r) @[dec_tlu_ctl.scala 2070:36] + node _T_714 = or(_T_713, dpc_capture_npc) @[dec_tlu_ctl.scala 2070:53] + node _T_715 = bits(_T_714, 0, 0) @[dec_tlu_ctl.scala 2070:72] inst rvclkhdr_18 of rvclkhdr_738 @[lib.scala 368:23] rvclkhdr_18.clock <= clock rvclkhdr_18.reset <= reset rvclkhdr_18.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_18.io.en <= _T_725 @[lib.scala 371:17] + rvclkhdr_18.io.en <= _T_715 @[lib.scala 371:17] rvclkhdr_18.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_726 : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_726 <= dpc_ns @[lib.scala 374:16] - io.dpc <= _T_726 @[dec_tlu_ctl.scala 2070:9] - node _T_727 = bits(io.dec_csr_wrdata_r, 24, 24) @[dec_tlu_ctl.scala 2084:43] - node _T_728 = bits(io.dec_csr_wrdata_r, 21, 20) @[dec_tlu_ctl.scala 2084:68] - node _T_729 = bits(io.dec_csr_wrdata_r, 16, 3) @[dec_tlu_ctl.scala 2084:96] - node _T_730 = cat(_T_727, _T_728) @[Cat.scala 29:58] - node dicawics_ns = cat(_T_730, _T_729) @[Cat.scala 29:58] - node _T_731 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2085:50] - node _T_732 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2085:95] - node _T_733 = eq(_T_732, UInt<12>("h07c8")) @[dec_tlu_ctl.scala 2085:102] - node wr_dicawics_r = and(_T_731, _T_733) @[dec_tlu_ctl.scala 2085:73] - node _T_734 = bits(wr_dicawics_r, 0, 0) @[dec_tlu_ctl.scala 2087:50] + reg _T_716 : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_716 <= dpc_ns @[lib.scala 374:16] + io.dpc <= _T_716 @[dec_tlu_ctl.scala 2070:9] + node _T_717 = bits(io.dec_csr_wrdata_r, 24, 24) @[dec_tlu_ctl.scala 2084:43] + node _T_718 = bits(io.dec_csr_wrdata_r, 21, 20) @[dec_tlu_ctl.scala 2084:68] + node _T_719 = bits(io.dec_csr_wrdata_r, 16, 3) @[dec_tlu_ctl.scala 2084:96] + node _T_720 = cat(_T_717, _T_718) @[Cat.scala 29:58] + node dicawics_ns = cat(_T_720, _T_719) @[Cat.scala 29:58] + node _T_721 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2085:50] + node _T_722 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2085:95] + node _T_723 = eq(_T_722, UInt<12>("h07c8")) @[dec_tlu_ctl.scala 2085:102] + node wr_dicawics_r = and(_T_721, _T_723) @[dec_tlu_ctl.scala 2085:73] + node _T_724 = bits(wr_dicawics_r, 0, 0) @[dec_tlu_ctl.scala 2087:50] inst rvclkhdr_19 of rvclkhdr_739 @[lib.scala 368:23] rvclkhdr_19.clock <= clock rvclkhdr_19.reset <= reset rvclkhdr_19.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_19.io.en <= _T_734 @[lib.scala 371:17] + rvclkhdr_19.io.en <= _T_724 @[lib.scala 371:17] rvclkhdr_19.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg dicawics : UInt, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] dicawics <= dicawics_ns @[lib.scala 374:16] - node _T_735 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2103:48] - node _T_736 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2103:93] - node _T_737 = eq(_T_736, UInt<12>("h07c9")) @[dec_tlu_ctl.scala 2103:100] - node wr_dicad0_r = and(_T_735, _T_737) @[dec_tlu_ctl.scala 2103:71] - node _T_738 = bits(wr_dicad0_r, 0, 0) @[dec_tlu_ctl.scala 2104:34] - node dicad0_ns = mux(_T_738, io.dec_csr_wrdata_r, io.ifu_ic_debug_rd_data) @[dec_tlu_ctl.scala 2104:21] - node _T_739 = or(wr_dicad0_r, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2106:46] - node _T_740 = bits(_T_739, 0, 0) @[dec_tlu_ctl.scala 2106:79] + node _T_725 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2103:48] + node _T_726 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2103:93] + node _T_727 = eq(_T_726, UInt<12>("h07c9")) @[dec_tlu_ctl.scala 2103:100] + node wr_dicad0_r = and(_T_725, _T_727) @[dec_tlu_ctl.scala 2103:71] + node _T_728 = bits(wr_dicad0_r, 0, 0) @[dec_tlu_ctl.scala 2104:34] + node dicad0_ns = mux(_T_728, io.dec_csr_wrdata_r, io.ifu_ic_debug_rd_data) @[dec_tlu_ctl.scala 2104:21] + node _T_729 = or(wr_dicad0_r, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2106:46] + node _T_730 = bits(_T_729, 0, 0) @[dec_tlu_ctl.scala 2106:79] inst rvclkhdr_20 of rvclkhdr_740 @[lib.scala 368:23] rvclkhdr_20.clock <= clock rvclkhdr_20.reset <= reset rvclkhdr_20.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_20.io.en <= _T_740 @[lib.scala 371:17] + rvclkhdr_20.io.en <= _T_730 @[lib.scala 371:17] rvclkhdr_20.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg dicad0 : UInt, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] dicad0 <= dicad0_ns @[lib.scala 374:16] - node _T_741 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2116:49] - node _T_742 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2116:94] - node _T_743 = eq(_T_742, UInt<12>("h07cc")) @[dec_tlu_ctl.scala 2116:101] - node wr_dicad0h_r = and(_T_741, _T_743) @[dec_tlu_ctl.scala 2116:72] - node _T_744 = bits(wr_dicad0h_r, 0, 0) @[dec_tlu_ctl.scala 2118:36] - node _T_745 = bits(io.ifu_ic_debug_rd_data, 63, 32) @[dec_tlu_ctl.scala 2118:88] - node dicad0h_ns = mux(_T_744, io.dec_csr_wrdata_r, _T_745) @[dec_tlu_ctl.scala 2118:22] - node _T_746 = or(wr_dicad0h_r, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2120:48] - node _T_747 = bits(_T_746, 0, 0) @[dec_tlu_ctl.scala 2120:81] + node _T_731 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2116:49] + node _T_732 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2116:94] + node _T_733 = eq(_T_732, UInt<12>("h07cc")) @[dec_tlu_ctl.scala 2116:101] + node wr_dicad0h_r = and(_T_731, _T_733) @[dec_tlu_ctl.scala 2116:72] + node _T_734 = bits(wr_dicad0h_r, 0, 0) @[dec_tlu_ctl.scala 2118:36] + node _T_735 = bits(io.ifu_ic_debug_rd_data, 63, 32) @[dec_tlu_ctl.scala 2118:88] + node dicad0h_ns = mux(_T_734, io.dec_csr_wrdata_r, _T_735) @[dec_tlu_ctl.scala 2118:22] + node _T_736 = or(wr_dicad0h_r, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2120:48] + node _T_737 = bits(_T_736, 0, 0) @[dec_tlu_ctl.scala 2120:81] inst rvclkhdr_21 of rvclkhdr_741 @[lib.scala 368:23] rvclkhdr_21.clock <= clock rvclkhdr_21.reset <= reset rvclkhdr_21.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_21.io.en <= _T_747 @[lib.scala 371:17] + rvclkhdr_21.io.en <= _T_737 @[lib.scala 371:17] rvclkhdr_21.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg dicad0h : UInt, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] dicad0h <= dicad0h_ns @[lib.scala 374:16] - wire _T_748 : UInt<7> - _T_748 <= UInt<1>("h00") - node _T_749 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2128:48] - node _T_750 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2128:93] - node _T_751 = eq(_T_750, UInt<12>("h07ca")) @[dec_tlu_ctl.scala 2128:100] - node _T_752 = and(_T_749, _T_751) @[dec_tlu_ctl.scala 2128:71] - node _T_753 = bits(_T_752, 0, 0) @[dec_tlu_ctl.scala 2130:34] - node _T_754 = bits(io.dec_csr_wrdata_r, 6, 0) @[dec_tlu_ctl.scala 2130:61] - node _T_755 = bits(io.ifu_ic_debug_rd_data, 70, 64) @[dec_tlu_ctl.scala 2130:91] - node _T_756 = mux(_T_753, _T_754, _T_755) @[dec_tlu_ctl.scala 2130:21] - node _T_757 = or(_T_752, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2132:78] - node _T_758 = bits(_T_757, 0, 0) @[dec_tlu_ctl.scala 2132:111] - reg _T_759 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_758 : @[Reg.scala 28:19] - _T_759 <= _T_756 @[Reg.scala 28:23] + wire _T_738 : UInt<7> + _T_738 <= UInt<1>("h00") + node _T_739 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2128:48] + node _T_740 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2128:93] + node _T_741 = eq(_T_740, UInt<12>("h07ca")) @[dec_tlu_ctl.scala 2128:100] + node _T_742 = and(_T_739, _T_741) @[dec_tlu_ctl.scala 2128:71] + node _T_743 = bits(_T_742, 0, 0) @[dec_tlu_ctl.scala 2130:34] + node _T_744 = bits(io.dec_csr_wrdata_r, 6, 0) @[dec_tlu_ctl.scala 2130:61] + node _T_745 = bits(io.ifu_ic_debug_rd_data, 70, 64) @[dec_tlu_ctl.scala 2130:91] + node _T_746 = mux(_T_743, _T_744, _T_745) @[dec_tlu_ctl.scala 2130:21] + node _T_747 = or(_T_742, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2132:78] + node _T_748 = bits(_T_747, 0, 0) @[dec_tlu_ctl.scala 2132:111] + reg _T_749 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_748 : @[Reg.scala 28:19] + _T_749 <= _T_746 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - _T_748 <= _T_759 @[dec_tlu_ctl.scala 2132:13] - node _T_760 = cat(UInt<25>("h00"), _T_748) @[Cat.scala 29:58] - dicad1 <= _T_760 @[dec_tlu_ctl.scala 2133:9] - node _T_761 = bits(dicad1, 6, 0) @[dec_tlu_ctl.scala 2155:69] - node _T_762 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2155:83] - node _T_763 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2155:97] - node _T_764 = cat(_T_761, _T_762) @[Cat.scala 29:58] - node _T_765 = cat(_T_764, _T_763) @[Cat.scala 29:58] - io.dec_tlu_ic_diag_pkt.icache_wrdata <= _T_765 @[dec_tlu_ctl.scala 2155:56] + _T_738 <= _T_749 @[dec_tlu_ctl.scala 2132:13] + node _T_750 = cat(UInt<25>("h00"), _T_738) @[Cat.scala 29:58] + dicad1 <= _T_750 @[dec_tlu_ctl.scala 2133:9] + node _T_751 = bits(dicad1, 6, 0) @[dec_tlu_ctl.scala 2155:69] + node _T_752 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2155:83] + node _T_753 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2155:97] + node _T_754 = cat(_T_751, _T_752) @[Cat.scala 29:58] + node _T_755 = cat(_T_754, _T_753) @[Cat.scala 29:58] + io.dec_tlu_ic_diag_pkt.icache_wrdata <= _T_755 @[dec_tlu_ctl.scala 2155:56] io.dec_tlu_ic_diag_pkt.icache_dicawics <= dicawics @[dec_tlu_ctl.scala 2158:41] - node _T_766 = and(io.allow_dbg_halt_csr_write, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 2160:52] - node _T_767 = and(_T_766, io.dec_i0_decode_d) @[dec_tlu_ctl.scala 2160:75] - node _T_768 = not(io.dec_csr_wen_unq_d) @[dec_tlu_ctl.scala 2160:98] - node _T_769 = and(_T_767, _T_768) @[dec_tlu_ctl.scala 2160:96] - node _T_770 = bits(io.dec_csr_rdaddr_d, 11, 0) @[dec_tlu_ctl.scala 2160:142] - node _T_771 = eq(_T_770, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2160:149] - node icache_rd_valid = and(_T_769, _T_771) @[dec_tlu_ctl.scala 2160:120] - node _T_772 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2161:52] - node _T_773 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2161:97] - node _T_774 = eq(_T_773, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2161:104] - node icache_wr_valid = and(_T_772, _T_774) @[dec_tlu_ctl.scala 2161:75] + node _T_756 = and(io.allow_dbg_halt_csr_write, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 2160:52] + node _T_757 = and(_T_756, io.dec_i0_decode_d) @[dec_tlu_ctl.scala 2160:75] + node _T_758 = not(io.dec_csr_wen_unq_d) @[dec_tlu_ctl.scala 2160:98] + node _T_759 = and(_T_757, _T_758) @[dec_tlu_ctl.scala 2160:96] + node _T_760 = bits(io.dec_csr_rdaddr_d, 11, 0) @[dec_tlu_ctl.scala 2160:142] + node _T_761 = eq(_T_760, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2160:149] + node icache_rd_valid = and(_T_759, _T_761) @[dec_tlu_ctl.scala 2160:120] + node _T_762 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2161:52] + node _T_763 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2161:97] + node _T_764 = eq(_T_763, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2161:104] + node icache_wr_valid = and(_T_762, _T_764) @[dec_tlu_ctl.scala 2161:75] reg icache_rd_valid_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2163:58] icache_rd_valid_f <= icache_rd_valid @[dec_tlu_ctl.scala 2163:58] reg icache_wr_valid_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2164:58] icache_wr_valid_f <= icache_wr_valid @[dec_tlu_ctl.scala 2164:58] io.dec_tlu_ic_diag_pkt.icache_rd_valid <= icache_rd_valid_f @[dec_tlu_ctl.scala 2166:41] io.dec_tlu_ic_diag_pkt.icache_wr_valid <= icache_wr_valid_f @[dec_tlu_ctl.scala 2167:41] - node _T_775 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2175:62] - node _T_776 = eq(_T_775, UInt<12>("h07a0")) @[dec_tlu_ctl.scala 2175:69] - node wr_mtsel_r = and(io.dec_csr_wen_r_mod, _T_776) @[dec_tlu_ctl.scala 2175:40] - node _T_777 = bits(wr_mtsel_r, 0, 0) @[dec_tlu_ctl.scala 2176:32] - node _T_778 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 2176:59] - node mtsel_ns = mux(_T_777, _T_778, mtsel) @[dec_tlu_ctl.scala 2176:20] - reg _T_779 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2178:43] - _T_779 <= mtsel_ns @[dec_tlu_ctl.scala 2178:43] - mtsel <= _T_779 @[dec_tlu_ctl.scala 2178:8] - node _T_780 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2213:38] - node _T_781 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2213:64] - node _T_782 = not(_T_781) @[dec_tlu_ctl.scala 2213:44] - node tdata_load = and(_T_780, _T_782) @[dec_tlu_ctl.scala 2213:42] - node _T_783 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2215:40] - node _T_784 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2215:66] - node _T_785 = not(_T_784) @[dec_tlu_ctl.scala 2215:46] - node tdata_opcode = and(_T_783, _T_785) @[dec_tlu_ctl.scala 2215:44] - node _T_786 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2217:41] - node _T_787 = and(_T_786, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2217:46] - node _T_788 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 2217:90] - node tdata_action = and(_T_787, _T_788) @[dec_tlu_ctl.scala 2217:69] - node _T_789 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2219:47] - node _T_790 = and(_T_789, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2219:52] - node _T_791 = bits(io.dec_csr_wrdata_r, 20, 19) @[dec_tlu_ctl.scala 2219:94] - node _T_792 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 2219:136] - node _T_793 = bits(io.dec_csr_wrdata_r, 7, 6) @[dec_tlu_ctl.scala 2220:43] - node _T_794 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 2220:83] - node _T_795 = cat(_T_794, tdata_load) @[Cat.scala 29:58] - node _T_796 = cat(_T_793, tdata_opcode) @[Cat.scala 29:58] - node _T_797 = cat(_T_796, _T_795) @[Cat.scala 29:58] - node _T_798 = cat(tdata_action, _T_792) @[Cat.scala 29:58] - node _T_799 = cat(_T_790, _T_791) @[Cat.scala 29:58] - node _T_800 = cat(_T_799, _T_798) @[Cat.scala 29:58] - node tdata_wrdata_r = cat(_T_800, _T_797) @[Cat.scala 29:58] - node _T_801 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2223:92] - node _T_802 = eq(_T_801, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2223:99] - node _T_803 = and(io.dec_csr_wen_r_mod, _T_802) @[dec_tlu_ctl.scala 2223:70] - node _T_804 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2223:121] - node _T_805 = and(_T_803, _T_804) @[dec_tlu_ctl.scala 2223:112] - node _T_806 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2223:154] - node _T_807 = not(_T_806) @[dec_tlu_ctl.scala 2223:138] - node _T_808 = or(_T_807, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2223:170] - node _T_809 = and(_T_805, _T_808) @[dec_tlu_ctl.scala 2223:135] - node _T_810 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2223:92] - node _T_811 = eq(_T_810, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2223:99] - node _T_812 = and(io.dec_csr_wen_r_mod, _T_811) @[dec_tlu_ctl.scala 2223:70] - node _T_813 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2223:121] - node _T_814 = and(_T_812, _T_813) @[dec_tlu_ctl.scala 2223:112] - node _T_815 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2223:154] - node _T_816 = not(_T_815) @[dec_tlu_ctl.scala 2223:138] - node _T_817 = or(_T_816, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2223:170] - node _T_818 = and(_T_814, _T_817) @[dec_tlu_ctl.scala 2223:135] - node _T_819 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2223:92] - node _T_820 = eq(_T_819, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2223:99] - node _T_821 = and(io.dec_csr_wen_r_mod, _T_820) @[dec_tlu_ctl.scala 2223:70] - node _T_822 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2223:121] - node _T_823 = and(_T_821, _T_822) @[dec_tlu_ctl.scala 2223:112] - node _T_824 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2223:154] - node _T_825 = not(_T_824) @[dec_tlu_ctl.scala 2223:138] - node _T_826 = or(_T_825, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2223:170] - node _T_827 = and(_T_823, _T_826) @[dec_tlu_ctl.scala 2223:135] - node _T_828 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2223:92] - node _T_829 = eq(_T_828, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2223:99] - node _T_830 = and(io.dec_csr_wen_r_mod, _T_829) @[dec_tlu_ctl.scala 2223:70] - node _T_831 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2223:121] - node _T_832 = and(_T_830, _T_831) @[dec_tlu_ctl.scala 2223:112] - node _T_833 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2223:154] - node _T_834 = not(_T_833) @[dec_tlu_ctl.scala 2223:138] - node _T_835 = or(_T_834, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2223:170] - node _T_836 = and(_T_832, _T_835) @[dec_tlu_ctl.scala 2223:135] + node _T_765 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2175:62] + node _T_766 = eq(_T_765, UInt<12>("h07a0")) @[dec_tlu_ctl.scala 2175:69] + node wr_mtsel_r = and(io.dec_csr_wen_r_mod, _T_766) @[dec_tlu_ctl.scala 2175:40] + node _T_767 = bits(wr_mtsel_r, 0, 0) @[dec_tlu_ctl.scala 2176:32] + node _T_768 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 2176:59] + node mtsel_ns = mux(_T_767, _T_768, mtsel) @[dec_tlu_ctl.scala 2176:20] + reg _T_769 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2178:43] + _T_769 <= mtsel_ns @[dec_tlu_ctl.scala 2178:43] + mtsel <= _T_769 @[dec_tlu_ctl.scala 2178:8] + node _T_770 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2213:38] + node _T_771 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2213:64] + node _T_772 = not(_T_771) @[dec_tlu_ctl.scala 2213:44] + node tdata_load = and(_T_770, _T_772) @[dec_tlu_ctl.scala 2213:42] + node _T_773 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2215:40] + node _T_774 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2215:66] + node _T_775 = not(_T_774) @[dec_tlu_ctl.scala 2215:46] + node tdata_opcode = and(_T_773, _T_775) @[dec_tlu_ctl.scala 2215:44] + node _T_776 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2217:41] + node _T_777 = and(_T_776, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2217:46] + node _T_778 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 2217:90] + node tdata_action = and(_T_777, _T_778) @[dec_tlu_ctl.scala 2217:69] + node _T_779 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2219:47] + node _T_780 = and(_T_779, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2219:52] + node _T_781 = bits(io.dec_csr_wrdata_r, 20, 19) @[dec_tlu_ctl.scala 2219:94] + node _T_782 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 2219:136] + node _T_783 = bits(io.dec_csr_wrdata_r, 7, 6) @[dec_tlu_ctl.scala 2220:43] + node _T_784 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 2220:83] + node _T_785 = cat(_T_784, tdata_load) @[Cat.scala 29:58] + node _T_786 = cat(_T_783, tdata_opcode) @[Cat.scala 29:58] + node _T_787 = cat(_T_786, _T_785) @[Cat.scala 29:58] + node _T_788 = cat(tdata_action, _T_782) @[Cat.scala 29:58] + node _T_789 = cat(_T_780, _T_781) @[Cat.scala 29:58] + node _T_790 = cat(_T_789, _T_788) @[Cat.scala 29:58] + node tdata_wrdata_r = cat(_T_790, _T_787) @[Cat.scala 29:58] + node _T_791 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2223:92] + node _T_792 = eq(_T_791, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2223:99] + node _T_793 = and(io.dec_csr_wen_r_mod, _T_792) @[dec_tlu_ctl.scala 2223:70] + node _T_794 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2223:121] + node _T_795 = and(_T_793, _T_794) @[dec_tlu_ctl.scala 2223:112] + node _T_796 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2223:154] + node _T_797 = not(_T_796) @[dec_tlu_ctl.scala 2223:138] + node _T_798 = or(_T_797, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2223:170] + node _T_799 = and(_T_795, _T_798) @[dec_tlu_ctl.scala 2223:135] + node _T_800 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2223:92] + node _T_801 = eq(_T_800, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2223:99] + node _T_802 = and(io.dec_csr_wen_r_mod, _T_801) @[dec_tlu_ctl.scala 2223:70] + node _T_803 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2223:121] + node _T_804 = and(_T_802, _T_803) @[dec_tlu_ctl.scala 2223:112] + node _T_805 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2223:154] + node _T_806 = not(_T_805) @[dec_tlu_ctl.scala 2223:138] + node _T_807 = or(_T_806, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2223:170] + node _T_808 = and(_T_804, _T_807) @[dec_tlu_ctl.scala 2223:135] + node _T_809 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2223:92] + node _T_810 = eq(_T_809, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2223:99] + node _T_811 = and(io.dec_csr_wen_r_mod, _T_810) @[dec_tlu_ctl.scala 2223:70] + node _T_812 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2223:121] + node _T_813 = and(_T_811, _T_812) @[dec_tlu_ctl.scala 2223:112] + node _T_814 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2223:154] + node _T_815 = not(_T_814) @[dec_tlu_ctl.scala 2223:138] + node _T_816 = or(_T_815, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2223:170] + node _T_817 = and(_T_813, _T_816) @[dec_tlu_ctl.scala 2223:135] + node _T_818 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2223:92] + node _T_819 = eq(_T_818, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2223:99] + node _T_820 = and(io.dec_csr_wen_r_mod, _T_819) @[dec_tlu_ctl.scala 2223:70] + node _T_821 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2223:121] + node _T_822 = and(_T_820, _T_821) @[dec_tlu_ctl.scala 2223:112] + node _T_823 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2223:154] + node _T_824 = not(_T_823) @[dec_tlu_ctl.scala 2223:138] + node _T_825 = or(_T_824, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2223:170] + node _T_826 = and(_T_822, _T_825) @[dec_tlu_ctl.scala 2223:135] wire wr_mtdata1_t_r : UInt<1>[4] @[dec_tlu_ctl.scala 2223:42] - wr_mtdata1_t_r[0] <= _T_809 @[dec_tlu_ctl.scala 2223:42] - wr_mtdata1_t_r[1] <= _T_818 @[dec_tlu_ctl.scala 2223:42] - wr_mtdata1_t_r[2] <= _T_827 @[dec_tlu_ctl.scala 2223:42] - wr_mtdata1_t_r[3] <= _T_836 @[dec_tlu_ctl.scala 2223:42] - node _T_837 = bits(wr_mtdata1_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2224:68] - node _T_838 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2224:111] - node _T_839 = bits(io.update_hit_bit_r, 0, 0) @[dec_tlu_ctl.scala 2224:135] - node _T_840 = bits(io.mtdata1_t[0], 8, 8) @[dec_tlu_ctl.scala 2224:156] - node _T_841 = or(_T_839, _T_840) @[dec_tlu_ctl.scala 2224:139] - node _T_842 = bits(io.mtdata1_t[0], 7, 0) @[dec_tlu_ctl.scala 2224:176] - node _T_843 = cat(_T_838, _T_841) @[Cat.scala 29:58] - node _T_844 = cat(_T_843, _T_842) @[Cat.scala 29:58] - node _T_845 = mux(_T_837, tdata_wrdata_r, _T_844) @[dec_tlu_ctl.scala 2224:49] - node _T_846 = bits(wr_mtdata1_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2224:68] - node _T_847 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2224:111] - node _T_848 = bits(io.update_hit_bit_r, 1, 1) @[dec_tlu_ctl.scala 2224:135] - node _T_849 = bits(io.mtdata1_t[1], 8, 8) @[dec_tlu_ctl.scala 2224:156] - node _T_850 = or(_T_848, _T_849) @[dec_tlu_ctl.scala 2224:139] - node _T_851 = bits(io.mtdata1_t[1], 7, 0) @[dec_tlu_ctl.scala 2224:176] - node _T_852 = cat(_T_847, _T_850) @[Cat.scala 29:58] - node _T_853 = cat(_T_852, _T_851) @[Cat.scala 29:58] - node _T_854 = mux(_T_846, tdata_wrdata_r, _T_853) @[dec_tlu_ctl.scala 2224:49] - node _T_855 = bits(wr_mtdata1_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2224:68] - node _T_856 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2224:111] - node _T_857 = bits(io.update_hit_bit_r, 2, 2) @[dec_tlu_ctl.scala 2224:135] - node _T_858 = bits(io.mtdata1_t[2], 8, 8) @[dec_tlu_ctl.scala 2224:156] - node _T_859 = or(_T_857, _T_858) @[dec_tlu_ctl.scala 2224:139] - node _T_860 = bits(io.mtdata1_t[2], 7, 0) @[dec_tlu_ctl.scala 2224:176] - node _T_861 = cat(_T_856, _T_859) @[Cat.scala 29:58] - node _T_862 = cat(_T_861, _T_860) @[Cat.scala 29:58] - node _T_863 = mux(_T_855, tdata_wrdata_r, _T_862) @[dec_tlu_ctl.scala 2224:49] - node _T_864 = bits(wr_mtdata1_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2224:68] - node _T_865 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2224:111] - node _T_866 = bits(io.update_hit_bit_r, 3, 3) @[dec_tlu_ctl.scala 2224:135] - node _T_867 = bits(io.mtdata1_t[3], 8, 8) @[dec_tlu_ctl.scala 2224:156] - node _T_868 = or(_T_866, _T_867) @[dec_tlu_ctl.scala 2224:139] - node _T_869 = bits(io.mtdata1_t[3], 7, 0) @[dec_tlu_ctl.scala 2224:176] - node _T_870 = cat(_T_865, _T_868) @[Cat.scala 29:58] - node _T_871 = cat(_T_870, _T_869) @[Cat.scala 29:58] - node _T_872 = mux(_T_864, tdata_wrdata_r, _T_871) @[dec_tlu_ctl.scala 2224:49] + wr_mtdata1_t_r[0] <= _T_799 @[dec_tlu_ctl.scala 2223:42] + wr_mtdata1_t_r[1] <= _T_808 @[dec_tlu_ctl.scala 2223:42] + wr_mtdata1_t_r[2] <= _T_817 @[dec_tlu_ctl.scala 2223:42] + wr_mtdata1_t_r[3] <= _T_826 @[dec_tlu_ctl.scala 2223:42] + node _T_827 = bits(wr_mtdata1_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2224:68] + node _T_828 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2224:111] + node _T_829 = bits(io.update_hit_bit_r, 0, 0) @[dec_tlu_ctl.scala 2224:135] + node _T_830 = bits(io.mtdata1_t[0], 8, 8) @[dec_tlu_ctl.scala 2224:156] + node _T_831 = or(_T_829, _T_830) @[dec_tlu_ctl.scala 2224:139] + node _T_832 = bits(io.mtdata1_t[0], 7, 0) @[dec_tlu_ctl.scala 2224:176] + node _T_833 = cat(_T_828, _T_831) @[Cat.scala 29:58] + node _T_834 = cat(_T_833, _T_832) @[Cat.scala 29:58] + node _T_835 = mux(_T_827, tdata_wrdata_r, _T_834) @[dec_tlu_ctl.scala 2224:49] + node _T_836 = bits(wr_mtdata1_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2224:68] + node _T_837 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2224:111] + node _T_838 = bits(io.update_hit_bit_r, 1, 1) @[dec_tlu_ctl.scala 2224:135] + node _T_839 = bits(io.mtdata1_t[1], 8, 8) @[dec_tlu_ctl.scala 2224:156] + node _T_840 = or(_T_838, _T_839) @[dec_tlu_ctl.scala 2224:139] + node _T_841 = bits(io.mtdata1_t[1], 7, 0) @[dec_tlu_ctl.scala 2224:176] + node _T_842 = cat(_T_837, _T_840) @[Cat.scala 29:58] + node _T_843 = cat(_T_842, _T_841) @[Cat.scala 29:58] + node _T_844 = mux(_T_836, tdata_wrdata_r, _T_843) @[dec_tlu_ctl.scala 2224:49] + node _T_845 = bits(wr_mtdata1_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2224:68] + node _T_846 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2224:111] + node _T_847 = bits(io.update_hit_bit_r, 2, 2) @[dec_tlu_ctl.scala 2224:135] + node _T_848 = bits(io.mtdata1_t[2], 8, 8) @[dec_tlu_ctl.scala 2224:156] + node _T_849 = or(_T_847, _T_848) @[dec_tlu_ctl.scala 2224:139] + node _T_850 = bits(io.mtdata1_t[2], 7, 0) @[dec_tlu_ctl.scala 2224:176] + node _T_851 = cat(_T_846, _T_849) @[Cat.scala 29:58] + node _T_852 = cat(_T_851, _T_850) @[Cat.scala 29:58] + node _T_853 = mux(_T_845, tdata_wrdata_r, _T_852) @[dec_tlu_ctl.scala 2224:49] + node _T_854 = bits(wr_mtdata1_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2224:68] + node _T_855 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2224:111] + node _T_856 = bits(io.update_hit_bit_r, 3, 3) @[dec_tlu_ctl.scala 2224:135] + node _T_857 = bits(io.mtdata1_t[3], 8, 8) @[dec_tlu_ctl.scala 2224:156] + node _T_858 = or(_T_856, _T_857) @[dec_tlu_ctl.scala 2224:139] + node _T_859 = bits(io.mtdata1_t[3], 7, 0) @[dec_tlu_ctl.scala 2224:176] + node _T_860 = cat(_T_855, _T_858) @[Cat.scala 29:58] + node _T_861 = cat(_T_860, _T_859) @[Cat.scala 29:58] + node _T_862 = mux(_T_854, tdata_wrdata_r, _T_861) @[dec_tlu_ctl.scala 2224:49] wire mtdata1_t_ns : UInt<10>[4] @[dec_tlu_ctl.scala 2224:40] - mtdata1_t_ns[0] <= _T_845 @[dec_tlu_ctl.scala 2224:40] - mtdata1_t_ns[1] <= _T_854 @[dec_tlu_ctl.scala 2224:40] - mtdata1_t_ns[2] <= _T_863 @[dec_tlu_ctl.scala 2224:40] - mtdata1_t_ns[3] <= _T_872 @[dec_tlu_ctl.scala 2224:40] - reg _T_873 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2226:74] - _T_873 <= mtdata1_t_ns[0] @[dec_tlu_ctl.scala 2226:74] - io.mtdata1_t[0] <= _T_873 @[dec_tlu_ctl.scala 2226:39] - reg _T_874 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2226:74] - _T_874 <= mtdata1_t_ns[1] @[dec_tlu_ctl.scala 2226:74] - io.mtdata1_t[1] <= _T_874 @[dec_tlu_ctl.scala 2226:39] - reg _T_875 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2226:74] - _T_875 <= mtdata1_t_ns[2] @[dec_tlu_ctl.scala 2226:74] - io.mtdata1_t[2] <= _T_875 @[dec_tlu_ctl.scala 2226:39] - reg _T_876 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2226:74] - _T_876 <= mtdata1_t_ns[3] @[dec_tlu_ctl.scala 2226:74] - io.mtdata1_t[3] <= _T_876 @[dec_tlu_ctl.scala 2226:39] - node _T_877 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2229:58] - node _T_878 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2229:104] - node _T_879 = bits(io.mtdata1_t[0], 8, 7) @[dec_tlu_ctl.scala 2229:142] - node _T_880 = bits(io.mtdata1_t[0], 6, 5) @[dec_tlu_ctl.scala 2229:174] - node _T_881 = bits(io.mtdata1_t[0], 4, 3) @[dec_tlu_ctl.scala 2229:206] - node _T_882 = bits(io.mtdata1_t[0], 2, 0) @[dec_tlu_ctl.scala 2229:238] - node _T_883 = cat(UInt<3>("h00"), _T_882) @[Cat.scala 29:58] - node _T_884 = cat(_T_880, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_885 = cat(_T_884, _T_881) @[Cat.scala 29:58] - node _T_886 = cat(_T_885, _T_883) @[Cat.scala 29:58] - node _T_887 = cat(_T_879, UInt<6>("h00")) @[Cat.scala 29:58] - node _T_888 = cat(UInt<4>("h02"), _T_878) @[Cat.scala 29:58] - node _T_889 = cat(_T_888, UInt<6>("h01f")) @[Cat.scala 29:58] - node _T_890 = cat(_T_889, _T_887) @[Cat.scala 29:58] - node _T_891 = cat(_T_890, _T_886) @[Cat.scala 29:58] - node _T_892 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2229:58] - node _T_893 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2229:104] - node _T_894 = bits(io.mtdata1_t[1], 8, 7) @[dec_tlu_ctl.scala 2229:142] - node _T_895 = bits(io.mtdata1_t[1], 6, 5) @[dec_tlu_ctl.scala 2229:174] - node _T_896 = bits(io.mtdata1_t[1], 4, 3) @[dec_tlu_ctl.scala 2229:206] - node _T_897 = bits(io.mtdata1_t[1], 2, 0) @[dec_tlu_ctl.scala 2229:238] - node _T_898 = cat(UInt<3>("h00"), _T_897) @[Cat.scala 29:58] - node _T_899 = cat(_T_895, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_900 = cat(_T_899, _T_896) @[Cat.scala 29:58] - node _T_901 = cat(_T_900, _T_898) @[Cat.scala 29:58] - node _T_902 = cat(_T_894, UInt<6>("h00")) @[Cat.scala 29:58] - node _T_903 = cat(UInt<4>("h02"), _T_893) @[Cat.scala 29:58] - node _T_904 = cat(_T_903, UInt<6>("h01f")) @[Cat.scala 29:58] - node _T_905 = cat(_T_904, _T_902) @[Cat.scala 29:58] - node _T_906 = cat(_T_905, _T_901) @[Cat.scala 29:58] - node _T_907 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2229:58] - node _T_908 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2229:104] - node _T_909 = bits(io.mtdata1_t[2], 8, 7) @[dec_tlu_ctl.scala 2229:142] - node _T_910 = bits(io.mtdata1_t[2], 6, 5) @[dec_tlu_ctl.scala 2229:174] - node _T_911 = bits(io.mtdata1_t[2], 4, 3) @[dec_tlu_ctl.scala 2229:206] - node _T_912 = bits(io.mtdata1_t[2], 2, 0) @[dec_tlu_ctl.scala 2229:238] - node _T_913 = cat(UInt<3>("h00"), _T_912) @[Cat.scala 29:58] - node _T_914 = cat(_T_910, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_915 = cat(_T_914, _T_911) @[Cat.scala 29:58] - node _T_916 = cat(_T_915, _T_913) @[Cat.scala 29:58] - node _T_917 = cat(_T_909, UInt<6>("h00")) @[Cat.scala 29:58] - node _T_918 = cat(UInt<4>("h02"), _T_908) @[Cat.scala 29:58] - node _T_919 = cat(_T_918, UInt<6>("h01f")) @[Cat.scala 29:58] - node _T_920 = cat(_T_919, _T_917) @[Cat.scala 29:58] - node _T_921 = cat(_T_920, _T_916) @[Cat.scala 29:58] - node _T_922 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2229:58] - node _T_923 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2229:104] - node _T_924 = bits(io.mtdata1_t[3], 8, 7) @[dec_tlu_ctl.scala 2229:142] - node _T_925 = bits(io.mtdata1_t[3], 6, 5) @[dec_tlu_ctl.scala 2229:174] - node _T_926 = bits(io.mtdata1_t[3], 4, 3) @[dec_tlu_ctl.scala 2229:206] - node _T_927 = bits(io.mtdata1_t[3], 2, 0) @[dec_tlu_ctl.scala 2229:238] - node _T_928 = cat(UInt<3>("h00"), _T_927) @[Cat.scala 29:58] - node _T_929 = cat(_T_925, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_930 = cat(_T_929, _T_926) @[Cat.scala 29:58] - node _T_931 = cat(_T_930, _T_928) @[Cat.scala 29:58] - node _T_932 = cat(_T_924, UInt<6>("h00")) @[Cat.scala 29:58] - node _T_933 = cat(UInt<4>("h02"), _T_923) @[Cat.scala 29:58] - node _T_934 = cat(_T_933, UInt<6>("h01f")) @[Cat.scala 29:58] - node _T_935 = cat(_T_934, _T_932) @[Cat.scala 29:58] - node _T_936 = cat(_T_935, _T_931) @[Cat.scala 29:58] - node _T_937 = mux(_T_877, _T_891, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_938 = mux(_T_892, _T_906, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_939 = mux(_T_907, _T_921, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_940 = mux(_T_922, _T_936, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_941 = or(_T_937, _T_938) @[Mux.scala 27:72] - node _T_942 = or(_T_941, _T_939) @[Mux.scala 27:72] - node _T_943 = or(_T_942, _T_940) @[Mux.scala 27:72] + mtdata1_t_ns[0] <= _T_835 @[dec_tlu_ctl.scala 2224:40] + mtdata1_t_ns[1] <= _T_844 @[dec_tlu_ctl.scala 2224:40] + mtdata1_t_ns[2] <= _T_853 @[dec_tlu_ctl.scala 2224:40] + mtdata1_t_ns[3] <= _T_862 @[dec_tlu_ctl.scala 2224:40] + reg _T_863 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2226:74] + _T_863 <= mtdata1_t_ns[0] @[dec_tlu_ctl.scala 2226:74] + io.mtdata1_t[0] <= _T_863 @[dec_tlu_ctl.scala 2226:39] + reg _T_864 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2226:74] + _T_864 <= mtdata1_t_ns[1] @[dec_tlu_ctl.scala 2226:74] + io.mtdata1_t[1] <= _T_864 @[dec_tlu_ctl.scala 2226:39] + reg _T_865 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2226:74] + _T_865 <= mtdata1_t_ns[2] @[dec_tlu_ctl.scala 2226:74] + io.mtdata1_t[2] <= _T_865 @[dec_tlu_ctl.scala 2226:39] + reg _T_866 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2226:74] + _T_866 <= mtdata1_t_ns[3] @[dec_tlu_ctl.scala 2226:74] + io.mtdata1_t[3] <= _T_866 @[dec_tlu_ctl.scala 2226:39] + node _T_867 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2229:58] + node _T_868 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2229:104] + node _T_869 = bits(io.mtdata1_t[0], 8, 7) @[dec_tlu_ctl.scala 2229:142] + node _T_870 = bits(io.mtdata1_t[0], 6, 5) @[dec_tlu_ctl.scala 2229:174] + node _T_871 = bits(io.mtdata1_t[0], 4, 3) @[dec_tlu_ctl.scala 2229:206] + node _T_872 = bits(io.mtdata1_t[0], 2, 0) @[dec_tlu_ctl.scala 2229:238] + node _T_873 = cat(UInt<3>("h00"), _T_872) @[Cat.scala 29:58] + node _T_874 = cat(_T_870, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_875 = cat(_T_874, _T_871) @[Cat.scala 29:58] + node _T_876 = cat(_T_875, _T_873) @[Cat.scala 29:58] + node _T_877 = cat(_T_869, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_878 = cat(UInt<4>("h02"), _T_868) @[Cat.scala 29:58] + node _T_879 = cat(_T_878, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_880 = cat(_T_879, _T_877) @[Cat.scala 29:58] + node _T_881 = cat(_T_880, _T_876) @[Cat.scala 29:58] + node _T_882 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2229:58] + node _T_883 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2229:104] + node _T_884 = bits(io.mtdata1_t[1], 8, 7) @[dec_tlu_ctl.scala 2229:142] + node _T_885 = bits(io.mtdata1_t[1], 6, 5) @[dec_tlu_ctl.scala 2229:174] + node _T_886 = bits(io.mtdata1_t[1], 4, 3) @[dec_tlu_ctl.scala 2229:206] + node _T_887 = bits(io.mtdata1_t[1], 2, 0) @[dec_tlu_ctl.scala 2229:238] + node _T_888 = cat(UInt<3>("h00"), _T_887) @[Cat.scala 29:58] + node _T_889 = cat(_T_885, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_890 = cat(_T_889, _T_886) @[Cat.scala 29:58] + node _T_891 = cat(_T_890, _T_888) @[Cat.scala 29:58] + node _T_892 = cat(_T_884, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_893 = cat(UInt<4>("h02"), _T_883) @[Cat.scala 29:58] + node _T_894 = cat(_T_893, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_895 = cat(_T_894, _T_892) @[Cat.scala 29:58] + node _T_896 = cat(_T_895, _T_891) @[Cat.scala 29:58] + node _T_897 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2229:58] + node _T_898 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2229:104] + node _T_899 = bits(io.mtdata1_t[2], 8, 7) @[dec_tlu_ctl.scala 2229:142] + node _T_900 = bits(io.mtdata1_t[2], 6, 5) @[dec_tlu_ctl.scala 2229:174] + node _T_901 = bits(io.mtdata1_t[2], 4, 3) @[dec_tlu_ctl.scala 2229:206] + node _T_902 = bits(io.mtdata1_t[2], 2, 0) @[dec_tlu_ctl.scala 2229:238] + node _T_903 = cat(UInt<3>("h00"), _T_902) @[Cat.scala 29:58] + node _T_904 = cat(_T_900, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_905 = cat(_T_904, _T_901) @[Cat.scala 29:58] + node _T_906 = cat(_T_905, _T_903) @[Cat.scala 29:58] + node _T_907 = cat(_T_899, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_908 = cat(UInt<4>("h02"), _T_898) @[Cat.scala 29:58] + node _T_909 = cat(_T_908, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_910 = cat(_T_909, _T_907) @[Cat.scala 29:58] + node _T_911 = cat(_T_910, _T_906) @[Cat.scala 29:58] + node _T_912 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2229:58] + node _T_913 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2229:104] + node _T_914 = bits(io.mtdata1_t[3], 8, 7) @[dec_tlu_ctl.scala 2229:142] + node _T_915 = bits(io.mtdata1_t[3], 6, 5) @[dec_tlu_ctl.scala 2229:174] + node _T_916 = bits(io.mtdata1_t[3], 4, 3) @[dec_tlu_ctl.scala 2229:206] + node _T_917 = bits(io.mtdata1_t[3], 2, 0) @[dec_tlu_ctl.scala 2229:238] + node _T_918 = cat(UInt<3>("h00"), _T_917) @[Cat.scala 29:58] + node _T_919 = cat(_T_915, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_920 = cat(_T_919, _T_916) @[Cat.scala 29:58] + node _T_921 = cat(_T_920, _T_918) @[Cat.scala 29:58] + node _T_922 = cat(_T_914, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_923 = cat(UInt<4>("h02"), _T_913) @[Cat.scala 29:58] + node _T_924 = cat(_T_923, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_925 = cat(_T_924, _T_922) @[Cat.scala 29:58] + node _T_926 = cat(_T_925, _T_921) @[Cat.scala 29:58] + node _T_927 = mux(_T_867, _T_881, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_928 = mux(_T_882, _T_896, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_929 = mux(_T_897, _T_911, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_930 = mux(_T_912, _T_926, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_931 = or(_T_927, _T_928) @[Mux.scala 27:72] + node _T_932 = or(_T_931, _T_929) @[Mux.scala 27:72] + node _T_933 = or(_T_932, _T_930) @[Mux.scala 27:72] wire mtdata1_tsel_out : UInt<32> @[Mux.scala 27:72] - mtdata1_tsel_out <= _T_943 @[Mux.scala 27:72] - node _T_944 = bits(io.mtdata1_t[0], 7, 7) @[dec_tlu_ctl.scala 2231:58] - io.trigger_pkt_any[0].select <= _T_944 @[dec_tlu_ctl.scala 2231:40] - node _T_945 = bits(io.mtdata1_t[0], 4, 4) @[dec_tlu_ctl.scala 2232:61] - io.trigger_pkt_any[0].match_pkt <= _T_945 @[dec_tlu_ctl.scala 2232:43] - node _T_946 = bits(io.mtdata1_t[0], 1, 1) @[dec_tlu_ctl.scala 2233:58] - io.trigger_pkt_any[0].store <= _T_946 @[dec_tlu_ctl.scala 2233:40] - node _T_947 = bits(io.mtdata1_t[0], 0, 0) @[dec_tlu_ctl.scala 2234:58] - io.trigger_pkt_any[0].load <= _T_947 @[dec_tlu_ctl.scala 2234:40] - node _T_948 = bits(io.mtdata1_t[0], 2, 2) @[dec_tlu_ctl.scala 2235:58] - io.trigger_pkt_any[0].execute <= _T_948 @[dec_tlu_ctl.scala 2235:40] - node _T_949 = bits(io.mtdata1_t[0], 3, 3) @[dec_tlu_ctl.scala 2236:58] - io.trigger_pkt_any[0].m <= _T_949 @[dec_tlu_ctl.scala 2236:40] - node _T_950 = bits(io.mtdata1_t[1], 7, 7) @[dec_tlu_ctl.scala 2231:58] - io.trigger_pkt_any[1].select <= _T_950 @[dec_tlu_ctl.scala 2231:40] - node _T_951 = bits(io.mtdata1_t[1], 4, 4) @[dec_tlu_ctl.scala 2232:61] - io.trigger_pkt_any[1].match_pkt <= _T_951 @[dec_tlu_ctl.scala 2232:43] - node _T_952 = bits(io.mtdata1_t[1], 1, 1) @[dec_tlu_ctl.scala 2233:58] - io.trigger_pkt_any[1].store <= _T_952 @[dec_tlu_ctl.scala 2233:40] - node _T_953 = bits(io.mtdata1_t[1], 0, 0) @[dec_tlu_ctl.scala 2234:58] - io.trigger_pkt_any[1].load <= _T_953 @[dec_tlu_ctl.scala 2234:40] - node _T_954 = bits(io.mtdata1_t[1], 2, 2) @[dec_tlu_ctl.scala 2235:58] - io.trigger_pkt_any[1].execute <= _T_954 @[dec_tlu_ctl.scala 2235:40] - node _T_955 = bits(io.mtdata1_t[1], 3, 3) @[dec_tlu_ctl.scala 2236:58] - io.trigger_pkt_any[1].m <= _T_955 @[dec_tlu_ctl.scala 2236:40] - node _T_956 = bits(io.mtdata1_t[2], 7, 7) @[dec_tlu_ctl.scala 2231:58] - io.trigger_pkt_any[2].select <= _T_956 @[dec_tlu_ctl.scala 2231:40] - node _T_957 = bits(io.mtdata1_t[2], 4, 4) @[dec_tlu_ctl.scala 2232:61] - io.trigger_pkt_any[2].match_pkt <= _T_957 @[dec_tlu_ctl.scala 2232:43] - node _T_958 = bits(io.mtdata1_t[2], 1, 1) @[dec_tlu_ctl.scala 2233:58] - io.trigger_pkt_any[2].store <= _T_958 @[dec_tlu_ctl.scala 2233:40] - node _T_959 = bits(io.mtdata1_t[2], 0, 0) @[dec_tlu_ctl.scala 2234:58] - io.trigger_pkt_any[2].load <= _T_959 @[dec_tlu_ctl.scala 2234:40] - node _T_960 = bits(io.mtdata1_t[2], 2, 2) @[dec_tlu_ctl.scala 2235:58] - io.trigger_pkt_any[2].execute <= _T_960 @[dec_tlu_ctl.scala 2235:40] - node _T_961 = bits(io.mtdata1_t[2], 3, 3) @[dec_tlu_ctl.scala 2236:58] - io.trigger_pkt_any[2].m <= _T_961 @[dec_tlu_ctl.scala 2236:40] - node _T_962 = bits(io.mtdata1_t[3], 7, 7) @[dec_tlu_ctl.scala 2231:58] - io.trigger_pkt_any[3].select <= _T_962 @[dec_tlu_ctl.scala 2231:40] - node _T_963 = bits(io.mtdata1_t[3], 4, 4) @[dec_tlu_ctl.scala 2232:61] - io.trigger_pkt_any[3].match_pkt <= _T_963 @[dec_tlu_ctl.scala 2232:43] - node _T_964 = bits(io.mtdata1_t[3], 1, 1) @[dec_tlu_ctl.scala 2233:58] - io.trigger_pkt_any[3].store <= _T_964 @[dec_tlu_ctl.scala 2233:40] - node _T_965 = bits(io.mtdata1_t[3], 0, 0) @[dec_tlu_ctl.scala 2234:58] - io.trigger_pkt_any[3].load <= _T_965 @[dec_tlu_ctl.scala 2234:40] - node _T_966 = bits(io.mtdata1_t[3], 2, 2) @[dec_tlu_ctl.scala 2235:58] - io.trigger_pkt_any[3].execute <= _T_966 @[dec_tlu_ctl.scala 2235:40] - node _T_967 = bits(io.mtdata1_t[3], 3, 3) @[dec_tlu_ctl.scala 2236:58] - io.trigger_pkt_any[3].m <= _T_967 @[dec_tlu_ctl.scala 2236:40] - node _T_968 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2243:91] - node _T_969 = eq(_T_968, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2243:98] - node _T_970 = and(io.dec_csr_wen_r_mod, _T_969) @[dec_tlu_ctl.scala 2243:69] - node _T_971 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2243:120] - node _T_972 = and(_T_970, _T_971) @[dec_tlu_ctl.scala 2243:111] - node _T_973 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2243:153] - node _T_974 = not(_T_973) @[dec_tlu_ctl.scala 2243:137] - node _T_975 = or(_T_974, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2243:169] - node _T_976 = and(_T_972, _T_975) @[dec_tlu_ctl.scala 2243:134] - node _T_977 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2243:91] - node _T_978 = eq(_T_977, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2243:98] - node _T_979 = and(io.dec_csr_wen_r_mod, _T_978) @[dec_tlu_ctl.scala 2243:69] - node _T_980 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2243:120] - node _T_981 = and(_T_979, _T_980) @[dec_tlu_ctl.scala 2243:111] - node _T_982 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2243:153] - node _T_983 = not(_T_982) @[dec_tlu_ctl.scala 2243:137] - node _T_984 = or(_T_983, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2243:169] - node _T_985 = and(_T_981, _T_984) @[dec_tlu_ctl.scala 2243:134] - node _T_986 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2243:91] - node _T_987 = eq(_T_986, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2243:98] - node _T_988 = and(io.dec_csr_wen_r_mod, _T_987) @[dec_tlu_ctl.scala 2243:69] - node _T_989 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2243:120] - node _T_990 = and(_T_988, _T_989) @[dec_tlu_ctl.scala 2243:111] - node _T_991 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2243:153] - node _T_992 = not(_T_991) @[dec_tlu_ctl.scala 2243:137] - node _T_993 = or(_T_992, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2243:169] - node _T_994 = and(_T_990, _T_993) @[dec_tlu_ctl.scala 2243:134] - node _T_995 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2243:91] - node _T_996 = eq(_T_995, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2243:98] - node _T_997 = and(io.dec_csr_wen_r_mod, _T_996) @[dec_tlu_ctl.scala 2243:69] - node _T_998 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2243:120] - node _T_999 = and(_T_997, _T_998) @[dec_tlu_ctl.scala 2243:111] - node _T_1000 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2243:153] - node _T_1001 = not(_T_1000) @[dec_tlu_ctl.scala 2243:137] - node _T_1002 = or(_T_1001, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2243:169] - node _T_1003 = and(_T_999, _T_1002) @[dec_tlu_ctl.scala 2243:134] + mtdata1_tsel_out <= _T_933 @[Mux.scala 27:72] + node _T_934 = bits(io.mtdata1_t[0], 7, 7) @[dec_tlu_ctl.scala 2231:58] + io.trigger_pkt_any[0].select <= _T_934 @[dec_tlu_ctl.scala 2231:40] + node _T_935 = bits(io.mtdata1_t[0], 4, 4) @[dec_tlu_ctl.scala 2232:61] + io.trigger_pkt_any[0].match_pkt <= _T_935 @[dec_tlu_ctl.scala 2232:43] + node _T_936 = bits(io.mtdata1_t[0], 1, 1) @[dec_tlu_ctl.scala 2233:58] + io.trigger_pkt_any[0].store <= _T_936 @[dec_tlu_ctl.scala 2233:40] + node _T_937 = bits(io.mtdata1_t[0], 0, 0) @[dec_tlu_ctl.scala 2234:58] + io.trigger_pkt_any[0].load <= _T_937 @[dec_tlu_ctl.scala 2234:40] + node _T_938 = bits(io.mtdata1_t[0], 2, 2) @[dec_tlu_ctl.scala 2235:58] + io.trigger_pkt_any[0].execute <= _T_938 @[dec_tlu_ctl.scala 2235:40] + node _T_939 = bits(io.mtdata1_t[0], 3, 3) @[dec_tlu_ctl.scala 2236:58] + io.trigger_pkt_any[0].m <= _T_939 @[dec_tlu_ctl.scala 2236:40] + node _T_940 = bits(io.mtdata1_t[1], 7, 7) @[dec_tlu_ctl.scala 2231:58] + io.trigger_pkt_any[1].select <= _T_940 @[dec_tlu_ctl.scala 2231:40] + node _T_941 = bits(io.mtdata1_t[1], 4, 4) @[dec_tlu_ctl.scala 2232:61] + io.trigger_pkt_any[1].match_pkt <= _T_941 @[dec_tlu_ctl.scala 2232:43] + node _T_942 = bits(io.mtdata1_t[1], 1, 1) @[dec_tlu_ctl.scala 2233:58] + io.trigger_pkt_any[1].store <= _T_942 @[dec_tlu_ctl.scala 2233:40] + node _T_943 = bits(io.mtdata1_t[1], 0, 0) @[dec_tlu_ctl.scala 2234:58] + io.trigger_pkt_any[1].load <= _T_943 @[dec_tlu_ctl.scala 2234:40] + node _T_944 = bits(io.mtdata1_t[1], 2, 2) @[dec_tlu_ctl.scala 2235:58] + io.trigger_pkt_any[1].execute <= _T_944 @[dec_tlu_ctl.scala 2235:40] + node _T_945 = bits(io.mtdata1_t[1], 3, 3) @[dec_tlu_ctl.scala 2236:58] + io.trigger_pkt_any[1].m <= _T_945 @[dec_tlu_ctl.scala 2236:40] + node _T_946 = bits(io.mtdata1_t[2], 7, 7) @[dec_tlu_ctl.scala 2231:58] + io.trigger_pkt_any[2].select <= _T_946 @[dec_tlu_ctl.scala 2231:40] + node _T_947 = bits(io.mtdata1_t[2], 4, 4) @[dec_tlu_ctl.scala 2232:61] + io.trigger_pkt_any[2].match_pkt <= _T_947 @[dec_tlu_ctl.scala 2232:43] + node _T_948 = bits(io.mtdata1_t[2], 1, 1) @[dec_tlu_ctl.scala 2233:58] + io.trigger_pkt_any[2].store <= _T_948 @[dec_tlu_ctl.scala 2233:40] + node _T_949 = bits(io.mtdata1_t[2], 0, 0) @[dec_tlu_ctl.scala 2234:58] + io.trigger_pkt_any[2].load <= _T_949 @[dec_tlu_ctl.scala 2234:40] + node _T_950 = bits(io.mtdata1_t[2], 2, 2) @[dec_tlu_ctl.scala 2235:58] + io.trigger_pkt_any[2].execute <= _T_950 @[dec_tlu_ctl.scala 2235:40] + node _T_951 = bits(io.mtdata1_t[2], 3, 3) @[dec_tlu_ctl.scala 2236:58] + io.trigger_pkt_any[2].m <= _T_951 @[dec_tlu_ctl.scala 2236:40] + node _T_952 = bits(io.mtdata1_t[3], 7, 7) @[dec_tlu_ctl.scala 2231:58] + io.trigger_pkt_any[3].select <= _T_952 @[dec_tlu_ctl.scala 2231:40] + node _T_953 = bits(io.mtdata1_t[3], 4, 4) @[dec_tlu_ctl.scala 2232:61] + io.trigger_pkt_any[3].match_pkt <= _T_953 @[dec_tlu_ctl.scala 2232:43] + node _T_954 = bits(io.mtdata1_t[3], 1, 1) @[dec_tlu_ctl.scala 2233:58] + io.trigger_pkt_any[3].store <= _T_954 @[dec_tlu_ctl.scala 2233:40] + node _T_955 = bits(io.mtdata1_t[3], 0, 0) @[dec_tlu_ctl.scala 2234:58] + io.trigger_pkt_any[3].load <= _T_955 @[dec_tlu_ctl.scala 2234:40] + node _T_956 = bits(io.mtdata1_t[3], 2, 2) @[dec_tlu_ctl.scala 2235:58] + io.trigger_pkt_any[3].execute <= _T_956 @[dec_tlu_ctl.scala 2235:40] + node _T_957 = bits(io.mtdata1_t[3], 3, 3) @[dec_tlu_ctl.scala 2236:58] + io.trigger_pkt_any[3].m <= _T_957 @[dec_tlu_ctl.scala 2236:40] + node _T_958 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2243:91] + node _T_959 = eq(_T_958, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2243:98] + node _T_960 = and(io.dec_csr_wen_r_mod, _T_959) @[dec_tlu_ctl.scala 2243:69] + node _T_961 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2243:120] + node _T_962 = and(_T_960, _T_961) @[dec_tlu_ctl.scala 2243:111] + node _T_963 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2243:153] + node _T_964 = not(_T_963) @[dec_tlu_ctl.scala 2243:137] + node _T_965 = or(_T_964, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2243:169] + node _T_966 = and(_T_962, _T_965) @[dec_tlu_ctl.scala 2243:134] + node _T_967 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2243:91] + node _T_968 = eq(_T_967, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2243:98] + node _T_969 = and(io.dec_csr_wen_r_mod, _T_968) @[dec_tlu_ctl.scala 2243:69] + node _T_970 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2243:120] + node _T_971 = and(_T_969, _T_970) @[dec_tlu_ctl.scala 2243:111] + node _T_972 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2243:153] + node _T_973 = not(_T_972) @[dec_tlu_ctl.scala 2243:137] + node _T_974 = or(_T_973, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2243:169] + node _T_975 = and(_T_971, _T_974) @[dec_tlu_ctl.scala 2243:134] + node _T_976 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2243:91] + node _T_977 = eq(_T_976, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2243:98] + node _T_978 = and(io.dec_csr_wen_r_mod, _T_977) @[dec_tlu_ctl.scala 2243:69] + node _T_979 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2243:120] + node _T_980 = and(_T_978, _T_979) @[dec_tlu_ctl.scala 2243:111] + node _T_981 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2243:153] + node _T_982 = not(_T_981) @[dec_tlu_ctl.scala 2243:137] + node _T_983 = or(_T_982, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2243:169] + node _T_984 = and(_T_980, _T_983) @[dec_tlu_ctl.scala 2243:134] + node _T_985 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2243:91] + node _T_986 = eq(_T_985, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2243:98] + node _T_987 = and(io.dec_csr_wen_r_mod, _T_986) @[dec_tlu_ctl.scala 2243:69] + node _T_988 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2243:120] + node _T_989 = and(_T_987, _T_988) @[dec_tlu_ctl.scala 2243:111] + node _T_990 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2243:153] + node _T_991 = not(_T_990) @[dec_tlu_ctl.scala 2243:137] + node _T_992 = or(_T_991, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2243:169] + node _T_993 = and(_T_989, _T_992) @[dec_tlu_ctl.scala 2243:134] wire wr_mtdata2_t_r : UInt<1>[4] @[dec_tlu_ctl.scala 2243:42] - wr_mtdata2_t_r[0] <= _T_976 @[dec_tlu_ctl.scala 2243:42] - wr_mtdata2_t_r[1] <= _T_985 @[dec_tlu_ctl.scala 2243:42] - wr_mtdata2_t_r[2] <= _T_994 @[dec_tlu_ctl.scala 2243:42] - wr_mtdata2_t_r[3] <= _T_1003 @[dec_tlu_ctl.scala 2243:42] - node _T_1004 = bits(wr_mtdata2_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2244:84] + wr_mtdata2_t_r[0] <= _T_966 @[dec_tlu_ctl.scala 2243:42] + wr_mtdata2_t_r[1] <= _T_975 @[dec_tlu_ctl.scala 2243:42] + wr_mtdata2_t_r[2] <= _T_984 @[dec_tlu_ctl.scala 2243:42] + wr_mtdata2_t_r[3] <= _T_993 @[dec_tlu_ctl.scala 2243:42] + node _T_994 = bits(wr_mtdata2_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2244:84] inst rvclkhdr_22 of rvclkhdr_742 @[lib.scala 368:23] rvclkhdr_22.clock <= clock rvclkhdr_22.reset <= reset rvclkhdr_22.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_22.io.en <= _T_1004 @[lib.scala 371:17] + rvclkhdr_22.io.en <= _T_994 @[lib.scala 371:17] rvclkhdr_22.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_1005 : UInt, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_1005 <= io.dec_csr_wrdata_r @[lib.scala 374:16] - mtdata2_t[0] <= _T_1005 @[dec_tlu_ctl.scala 2244:36] - node _T_1006 = bits(wr_mtdata2_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2244:84] + reg _T_995 : UInt, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_995 <= io.dec_csr_wrdata_r @[lib.scala 374:16] + mtdata2_t[0] <= _T_995 @[dec_tlu_ctl.scala 2244:36] + node _T_996 = bits(wr_mtdata2_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2244:84] inst rvclkhdr_23 of rvclkhdr_743 @[lib.scala 368:23] rvclkhdr_23.clock <= clock rvclkhdr_23.reset <= reset rvclkhdr_23.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_23.io.en <= _T_1006 @[lib.scala 371:17] + rvclkhdr_23.io.en <= _T_996 @[lib.scala 371:17] rvclkhdr_23.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_1007 : UInt, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_1007 <= io.dec_csr_wrdata_r @[lib.scala 374:16] - mtdata2_t[1] <= _T_1007 @[dec_tlu_ctl.scala 2244:36] - node _T_1008 = bits(wr_mtdata2_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2244:84] + reg _T_997 : UInt, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_997 <= io.dec_csr_wrdata_r @[lib.scala 374:16] + mtdata2_t[1] <= _T_997 @[dec_tlu_ctl.scala 2244:36] + node _T_998 = bits(wr_mtdata2_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2244:84] inst rvclkhdr_24 of rvclkhdr_744 @[lib.scala 368:23] rvclkhdr_24.clock <= clock rvclkhdr_24.reset <= reset rvclkhdr_24.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_24.io.en <= _T_1008 @[lib.scala 371:17] + rvclkhdr_24.io.en <= _T_998 @[lib.scala 371:17] rvclkhdr_24.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_1009 : UInt, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_1009 <= io.dec_csr_wrdata_r @[lib.scala 374:16] - mtdata2_t[2] <= _T_1009 @[dec_tlu_ctl.scala 2244:36] - node _T_1010 = bits(wr_mtdata2_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2244:84] + reg _T_999 : UInt, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_999 <= io.dec_csr_wrdata_r @[lib.scala 374:16] + mtdata2_t[2] <= _T_999 @[dec_tlu_ctl.scala 2244:36] + node _T_1000 = bits(wr_mtdata2_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2244:84] inst rvclkhdr_25 of rvclkhdr_745 @[lib.scala 368:23] rvclkhdr_25.clock <= clock rvclkhdr_25.reset <= reset rvclkhdr_25.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_25.io.en <= _T_1010 @[lib.scala 371:17] + rvclkhdr_25.io.en <= _T_1000 @[lib.scala 371:17] rvclkhdr_25.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_1011 : UInt, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_1011 <= io.dec_csr_wrdata_r @[lib.scala 374:16] - mtdata2_t[3] <= _T_1011 @[dec_tlu_ctl.scala 2244:36] - node _T_1012 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2248:57] - node _T_1013 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2248:57] - node _T_1014 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2248:57] - node _T_1015 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2248:57] - node _T_1016 = mux(_T_1012, mtdata2_t[0], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1017 = mux(_T_1013, mtdata2_t[1], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1018 = mux(_T_1014, mtdata2_t[2], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1019 = mux(_T_1015, mtdata2_t[3], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1020 = or(_T_1016, _T_1017) @[Mux.scala 27:72] - node _T_1021 = or(_T_1020, _T_1018) @[Mux.scala 27:72] - node _T_1022 = or(_T_1021, _T_1019) @[Mux.scala 27:72] + reg _T_1001 : UInt, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_1001 <= io.dec_csr_wrdata_r @[lib.scala 374:16] + mtdata2_t[3] <= _T_1001 @[dec_tlu_ctl.scala 2244:36] + node _T_1002 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2248:57] + node _T_1003 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2248:57] + node _T_1004 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2248:57] + node _T_1005 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2248:57] + node _T_1006 = mux(_T_1002, mtdata2_t[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1007 = mux(_T_1003, mtdata2_t[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1008 = mux(_T_1004, mtdata2_t[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1009 = mux(_T_1005, mtdata2_t[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1010 = or(_T_1006, _T_1007) @[Mux.scala 27:72] + node _T_1011 = or(_T_1010, _T_1008) @[Mux.scala 27:72] + node _T_1012 = or(_T_1011, _T_1009) @[Mux.scala 27:72] wire mtdata2_tsel_out : UInt<32> @[Mux.scala 27:72] - mtdata2_tsel_out <= _T_1022 @[Mux.scala 27:72] + mtdata2_tsel_out <= _T_1012 @[Mux.scala 27:72] io.trigger_pkt_any[0].tdata2 <= mtdata2_t[0] @[dec_tlu_ctl.scala 2249:51] io.trigger_pkt_any[1].tdata2 <= mtdata2_t[1] @[dec_tlu_ctl.scala 2249:51] io.trigger_pkt_any[2].tdata2 <= mtdata2_t[2] @[dec_tlu_ctl.scala 2249:51] @@ -74409,238 +74399,248 @@ circuit quasar_wrapper : mhpme_vec[1] <= mhpme4 @[dec_tlu_ctl.scala 2260:15] mhpme_vec[2] <= mhpme5 @[dec_tlu_ctl.scala 2261:15] mhpme_vec[3] <= mhpme6 @[dec_tlu_ctl.scala 2262:15] - node _T_1023 = bits(io.tlu_i0_commit_cmt, 0, 0) @[Bitwise.scala 72:15] - node _T_1024 = mux(_T_1023, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node pmu_i0_itype_qual = and(io.dec_tlu_packet_r.pmu_i0_itype, _T_1024) @[dec_tlu_ctl.scala 2268:59] + node _T_1013 = bits(io.tlu_i0_commit_cmt, 0, 0) @[Bitwise.scala 72:15] + node _T_1014 = mux(_T_1013, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node pmu_i0_itype_qual = and(io.dec_tlu_packet_r.pmu_i0_itype, _T_1014) @[dec_tlu_ctl.scala 2268:59] wire mhpmc_inc_r : UInt<1>[4] @[dec_tlu_ctl.scala 2269:24] wire mhpmc_inc_r_d1 : UInt<1>[4] @[dec_tlu_ctl.scala 2270:27] - node _T_1025 = bits(mcountinhibit, 3, 3) @[dec_tlu_ctl.scala 2274:38] - node _T_1026 = not(_T_1025) @[dec_tlu_ctl.scala 2274:24] - node _T_1027 = eq(mhpme_vec[0], UInt<1>("h01")) @[dec_tlu_ctl.scala 2275:34] - node _T_1028 = bits(_T_1027, 0, 0) @[dec_tlu_ctl.scala 2275:62] - node _T_1029 = eq(mhpme_vec[0], UInt<2>("h02")) @[dec_tlu_ctl.scala 2276:34] - node _T_1030 = bits(_T_1029, 0, 0) @[dec_tlu_ctl.scala 2276:62] - node _T_1031 = eq(mhpme_vec[0], UInt<2>("h03")) @[dec_tlu_ctl.scala 2277:34] - node _T_1032 = bits(_T_1031, 0, 0) @[dec_tlu_ctl.scala 2277:62] - node _T_1033 = eq(mhpme_vec[0], UInt<3>("h04")) @[dec_tlu_ctl.scala 2278:34] - node _T_1034 = bits(_T_1033, 0, 0) @[dec_tlu_ctl.scala 2278:62] - node _T_1035 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:96] - node _T_1036 = and(io.tlu_i0_commit_cmt, _T_1035) @[dec_tlu_ctl.scala 2278:94] - node _T_1037 = eq(mhpme_vec[0], UInt<3>("h05")) @[dec_tlu_ctl.scala 2279:34] - node _T_1038 = bits(_T_1037, 0, 0) @[dec_tlu_ctl.scala 2279:62] - node _T_1039 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:96] - node _T_1040 = and(io.tlu_i0_commit_cmt, _T_1039) @[dec_tlu_ctl.scala 2279:94] - node _T_1041 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] - node _T_1042 = and(_T_1040, _T_1041) @[dec_tlu_ctl.scala 2279:115] - node _T_1043 = eq(mhpme_vec[0], UInt<3>("h06")) @[dec_tlu_ctl.scala 2280:34] - node _T_1044 = bits(_T_1043, 0, 0) @[dec_tlu_ctl.scala 2280:62] - node _T_1045 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2280:94] - node _T_1046 = not(io.illegal_r) @[dec_tlu_ctl.scala 2280:117] - node _T_1047 = and(_T_1045, _T_1046) @[dec_tlu_ctl.scala 2280:115] - node _T_1048 = eq(mhpme_vec[0], UInt<3>("h07")) @[dec_tlu_ctl.scala 2281:34] - node _T_1049 = bits(_T_1048, 0, 0) @[dec_tlu_ctl.scala 2281:62] - node _T_1050 = eq(mhpme_vec[0], UInt<4>("h08")) @[dec_tlu_ctl.scala 2282:34] - node _T_1051 = bits(_T_1050, 0, 0) @[dec_tlu_ctl.scala 2282:62] - node _T_1052 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2283:34] - node _T_1053 = bits(_T_1052, 0, 0) @[dec_tlu_ctl.scala 2283:62] - node _T_1054 = eq(mhpme_vec[0], UInt<4>("h09")) @[dec_tlu_ctl.scala 2284:34] - node _T_1055 = bits(_T_1054, 0, 0) @[dec_tlu_ctl.scala 2284:62] - node _T_1056 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2284:91] - node _T_1057 = eq(mhpme_vec[0], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2285:34] - node _T_1058 = bits(_T_1057, 0, 0) @[dec_tlu_ctl.scala 2285:62] - node _T_1059 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2285:105] - node _T_1060 = eq(mhpme_vec[0], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2286:34] - node _T_1061 = bits(_T_1060, 0, 0) @[dec_tlu_ctl.scala 2286:62] - node _T_1062 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2286:91] - node _T_1063 = eq(mhpme_vec[0], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2287:34] - node _T_1064 = bits(_T_1063, 0, 0) @[dec_tlu_ctl.scala 2287:62] - node _T_1065 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2287:91] - node _T_1066 = eq(mhpme_vec[0], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2288:34] - node _T_1067 = bits(_T_1066, 0, 0) @[dec_tlu_ctl.scala 2288:62] - node _T_1068 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2288:91] - node _T_1069 = and(_T_1068, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2288:100] - node _T_1070 = eq(mhpme_vec[0], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2289:34] - node _T_1071 = bits(_T_1070, 0, 0) @[dec_tlu_ctl.scala 2289:62] - node _T_1072 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2289:91] - node _T_1073 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2289:142] - node _T_1074 = and(_T_1072, _T_1073) @[dec_tlu_ctl.scala 2289:101] - node _T_1075 = eq(mhpme_vec[0], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2290:34] - node _T_1076 = bits(_T_1075, 0, 0) @[dec_tlu_ctl.scala 2290:59] - node _T_1077 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2290:89] - node _T_1078 = eq(mhpme_vec[0], UInt<5>("h010")) @[dec_tlu_ctl.scala 2291:34] - node _T_1079 = bits(_T_1078, 0, 0) @[dec_tlu_ctl.scala 2291:59] - node _T_1080 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2291:89] - node _T_1081 = eq(mhpme_vec[0], UInt<5>("h012")) @[dec_tlu_ctl.scala 2292:34] - node _T_1082 = bits(_T_1081, 0, 0) @[dec_tlu_ctl.scala 2292:59] - node _T_1083 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2292:89] - node _T_1084 = eq(mhpme_vec[0], UInt<5>("h011")) @[dec_tlu_ctl.scala 2293:34] - node _T_1085 = bits(_T_1084, 0, 0) @[dec_tlu_ctl.scala 2293:59] - node _T_1086 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2293:89] - node _T_1087 = eq(mhpme_vec[0], UInt<5>("h013")) @[dec_tlu_ctl.scala 2294:34] - node _T_1088 = bits(_T_1087, 0, 0) @[dec_tlu_ctl.scala 2294:59] - node _T_1089 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2294:89] - node _T_1090 = eq(mhpme_vec[0], UInt<5>("h014")) @[dec_tlu_ctl.scala 2295:34] - node _T_1091 = bits(_T_1090, 0, 0) @[dec_tlu_ctl.scala 2295:59] - node _T_1092 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2295:89] - node _T_1093 = eq(mhpme_vec[0], UInt<5>("h015")) @[dec_tlu_ctl.scala 2296:34] - node _T_1094 = bits(_T_1093, 0, 0) @[dec_tlu_ctl.scala 2296:59] - node _T_1095 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2296:89] - node _T_1096 = eq(mhpme_vec[0], UInt<5>("h016")) @[dec_tlu_ctl.scala 2297:34] - node _T_1097 = bits(_T_1096, 0, 0) @[dec_tlu_ctl.scala 2297:59] - node _T_1098 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2297:89] - node _T_1099 = eq(mhpme_vec[0], UInt<5>("h017")) @[dec_tlu_ctl.scala 2298:34] - node _T_1100 = bits(_T_1099, 0, 0) @[dec_tlu_ctl.scala 2298:59] - node _T_1101 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2298:89] - node _T_1102 = eq(mhpme_vec[0], UInt<5>("h018")) @[dec_tlu_ctl.scala 2299:34] - node _T_1103 = bits(_T_1102, 0, 0) @[dec_tlu_ctl.scala 2299:59] - node _T_1104 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2299:89] - node _T_1105 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2299:122] - node _T_1106 = or(_T_1104, _T_1105) @[dec_tlu_ctl.scala 2299:101] - node _T_1107 = eq(mhpme_vec[0], UInt<5>("h019")) @[dec_tlu_ctl.scala 2300:34] - node _T_1108 = bits(_T_1107, 0, 0) @[dec_tlu_ctl.scala 2300:62] - node _T_1109 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:95] - node _T_1110 = eq(mhpme_vec[0], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2301:34] - node _T_1111 = bits(_T_1110, 0, 0) @[dec_tlu_ctl.scala 2301:62] - node _T_1112 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:97] - node _T_1113 = eq(mhpme_vec[0], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2302:34] - node _T_1114 = bits(_T_1113, 0, 0) @[dec_tlu_ctl.scala 2302:62] - node _T_1115 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2302:110] - node _T_1116 = eq(mhpme_vec[0], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2303:34] - node _T_1117 = bits(_T_1116, 0, 0) @[dec_tlu_ctl.scala 2303:62] - node _T_1118 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2304:34] - node _T_1119 = bits(_T_1118, 0, 0) @[dec_tlu_ctl.scala 2304:62] - node _T_1120 = eq(mhpme_vec[0], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2305:34] - node _T_1121 = bits(_T_1120, 0, 0) @[dec_tlu_ctl.scala 2305:62] - node _T_1122 = eq(mhpme_vec[0], UInt<6>("h020")) @[dec_tlu_ctl.scala 2306:34] - node _T_1123 = bits(_T_1122, 0, 0) @[dec_tlu_ctl.scala 2306:62] - node _T_1124 = eq(mhpme_vec[0], UInt<6>("h022")) @[dec_tlu_ctl.scala 2307:34] - node _T_1125 = bits(_T_1124, 0, 0) @[dec_tlu_ctl.scala 2307:62] - node _T_1126 = eq(mhpme_vec[0], UInt<6>("h023")) @[dec_tlu_ctl.scala 2308:34] - node _T_1127 = bits(_T_1126, 0, 0) @[dec_tlu_ctl.scala 2308:62] - node _T_1128 = eq(mhpme_vec[0], UInt<6>("h024")) @[dec_tlu_ctl.scala 2309:34] - node _T_1129 = bits(_T_1128, 0, 0) @[dec_tlu_ctl.scala 2309:62] - node _T_1130 = eq(mhpme_vec[0], UInt<6>("h025")) @[dec_tlu_ctl.scala 2310:34] - node _T_1131 = bits(_T_1130, 0, 0) @[dec_tlu_ctl.scala 2310:62] - node _T_1132 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2310:98] - node _T_1133 = or(_T_1132, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2310:120] - node _T_1134 = eq(mhpme_vec[0], UInt<6>("h026")) @[dec_tlu_ctl.scala 2311:34] - node _T_1135 = bits(_T_1134, 0, 0) @[dec_tlu_ctl.scala 2311:62] - node _T_1136 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2311:92] - node _T_1137 = or(_T_1136, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2311:117] - node _T_1138 = eq(mhpme_vec[0], UInt<6>("h027")) @[dec_tlu_ctl.scala 2312:34] - node _T_1139 = bits(_T_1138, 0, 0) @[dec_tlu_ctl.scala 2312:62] - node _T_1140 = eq(mhpme_vec[0], UInt<6>("h028")) @[dec_tlu_ctl.scala 2313:34] - node _T_1141 = bits(_T_1140, 0, 0) @[dec_tlu_ctl.scala 2313:62] - node _T_1142 = eq(mhpme_vec[0], UInt<6>("h029")) @[dec_tlu_ctl.scala 2314:34] - node _T_1143 = bits(_T_1142, 0, 0) @[dec_tlu_ctl.scala 2314:62] - node _T_1144 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2314:97] - node _T_1145 = and(_T_1144, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2314:129] - node _T_1146 = eq(mhpme_vec[0], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2315:34] - node _T_1147 = bits(_T_1146, 0, 0) @[dec_tlu_ctl.scala 2315:62] - node _T_1148 = eq(mhpme_vec[0], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2316:34] - node _T_1149 = bits(_T_1148, 0, 0) @[dec_tlu_ctl.scala 2316:62] - node _T_1150 = eq(mhpme_vec[0], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2317:34] - node _T_1151 = bits(_T_1150, 0, 0) @[dec_tlu_ctl.scala 2317:62] - node _T_1152 = eq(mhpme_vec[0], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2318:34] - node _T_1153 = bits(_T_1152, 0, 0) @[dec_tlu_ctl.scala 2318:62] - node _T_1154 = eq(mhpme_vec[0], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2319:34] - node _T_1155 = bits(_T_1154, 0, 0) @[dec_tlu_ctl.scala 2319:62] - node _T_1156 = eq(mhpme_vec[0], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2320:34] - node _T_1157 = bits(_T_1156, 0, 0) @[dec_tlu_ctl.scala 2320:62] - node _T_1158 = eq(mhpme_vec[0], UInt<6>("h030")) @[dec_tlu_ctl.scala 2321:34] - node _T_1159 = bits(_T_1158, 0, 0) @[dec_tlu_ctl.scala 2321:62] - node _T_1160 = eq(mhpme_vec[0], UInt<6>("h031")) @[dec_tlu_ctl.scala 2322:34] - node _T_1161 = bits(_T_1160, 0, 0) @[dec_tlu_ctl.scala 2322:62] - node _T_1162 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] - node _T_1163 = bits(_T_1162, 0, 0) @[dec_tlu_ctl.scala 2322:84] - node _T_1164 = not(_T_1163) @[dec_tlu_ctl.scala 2322:73] - node _T_1165 = eq(mhpme_vec[0], UInt<6>("h032")) @[dec_tlu_ctl.scala 2323:34] - node _T_1166 = bits(_T_1165, 0, 0) @[dec_tlu_ctl.scala 2323:62] - node _T_1167 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2323:84] - node _T_1168 = bits(_T_1167, 0, 0) @[dec_tlu_ctl.scala 2323:84] - node _T_1169 = not(_T_1168) @[dec_tlu_ctl.scala 2323:73] - node _T_1170 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2323:107] - node _T_1171 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2323:118] - node _T_1172 = and(_T_1170, _T_1171) @[dec_tlu_ctl.scala 2323:113] - node _T_1173 = orr(_T_1172) @[dec_tlu_ctl.scala 2323:125] - node _T_1174 = and(_T_1169, _T_1173) @[dec_tlu_ctl.scala 2323:98] - node _T_1175 = eq(mhpme_vec[0], UInt<6>("h036")) @[dec_tlu_ctl.scala 2324:34] - node _T_1176 = bits(_T_1175, 0, 0) @[dec_tlu_ctl.scala 2324:62] - node _T_1177 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2324:91] - node _T_1178 = eq(mhpme_vec[0], UInt<6>("h037")) @[dec_tlu_ctl.scala 2325:34] - node _T_1179 = bits(_T_1178, 0, 0) @[dec_tlu_ctl.scala 2325:62] - node _T_1180 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2325:94] - node _T_1181 = eq(mhpme_vec[0], UInt<6>("h038")) @[dec_tlu_ctl.scala 2326:34] - node _T_1182 = bits(_T_1181, 0, 0) @[dec_tlu_ctl.scala 2326:62] - node _T_1183 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2326:94] - node _T_1184 = eq(mhpme_vec[0], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2328:34] - node _T_1185 = bits(_T_1184, 0, 0) @[dec_tlu_ctl.scala 2328:62] - node _T_1186 = eq(mhpme_vec[0], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2329:34] - node _T_1187 = bits(_T_1186, 0, 0) @[dec_tlu_ctl.scala 2329:62] - node _T_1188 = eq(mhpme_vec[0], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2330:34] - node _T_1189 = bits(_T_1188, 0, 0) @[dec_tlu_ctl.scala 2330:62] - node _T_1190 = eq(mhpme_vec[0], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2331:34] - node _T_1191 = bits(_T_1190, 0, 0) @[dec_tlu_ctl.scala 2331:62] - node _T_1192 = eq(mhpme_vec[0], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2332:34] - node _T_1193 = bits(_T_1192, 0, 0) @[dec_tlu_ctl.scala 2332:62] - node _T_1194 = mux(_T_1028, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1195 = mux(_T_1030, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1196 = mux(_T_1032, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1197 = mux(_T_1034, _T_1036, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1198 = mux(_T_1038, _T_1042, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1199 = mux(_T_1044, _T_1047, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1200 = mux(_T_1049, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1201 = mux(_T_1051, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1202 = mux(_T_1053, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1203 = mux(_T_1055, _T_1056, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1204 = mux(_T_1058, _T_1059, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1205 = mux(_T_1061, _T_1062, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1206 = mux(_T_1064, _T_1065, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1207 = mux(_T_1067, _T_1069, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1208 = mux(_T_1071, _T_1074, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1209 = mux(_T_1076, _T_1077, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1210 = mux(_T_1079, _T_1080, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1211 = mux(_T_1082, _T_1083, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1212 = mux(_T_1085, _T_1086, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1213 = mux(_T_1088, _T_1089, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1214 = mux(_T_1091, _T_1092, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1215 = mux(_T_1094, _T_1095, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1216 = mux(_T_1097, _T_1098, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1217 = mux(_T_1100, _T_1101, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1218 = mux(_T_1103, _T_1106, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1219 = mux(_T_1108, _T_1109, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1220 = mux(_T_1111, _T_1112, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1221 = mux(_T_1114, _T_1115, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1222 = mux(_T_1117, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1223 = mux(_T_1119, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1224 = mux(_T_1121, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1225 = mux(_T_1123, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1226 = mux(_T_1125, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1227 = mux(_T_1127, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1228 = mux(_T_1129, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1229 = mux(_T_1131, _T_1133, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1230 = mux(_T_1135, _T_1137, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1231 = mux(_T_1139, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1232 = mux(_T_1141, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1233 = mux(_T_1143, _T_1145, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1234 = mux(_T_1147, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1235 = mux(_T_1149, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1236 = mux(_T_1151, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1237 = mux(_T_1153, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1238 = mux(_T_1155, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1239 = mux(_T_1157, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1240 = mux(_T_1159, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1241 = mux(_T_1161, _T_1164, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1242 = mux(_T_1166, _T_1174, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1243 = mux(_T_1176, _T_1177, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1244 = mux(_T_1179, _T_1180, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1245 = mux(_T_1182, _T_1183, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1246 = mux(_T_1185, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1247 = mux(_T_1187, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1248 = mux(_T_1189, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1249 = mux(_T_1191, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1250 = mux(_T_1193, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1251 = or(_T_1194, _T_1195) @[Mux.scala 27:72] + node _T_1015 = bits(mcountinhibit, 3, 3) @[dec_tlu_ctl.scala 2274:38] + node _T_1016 = not(_T_1015) @[dec_tlu_ctl.scala 2274:24] + node _T_1017 = eq(mhpme_vec[0], UInt<1>("h01")) @[dec_tlu_ctl.scala 2275:34] + node _T_1018 = bits(_T_1017, 0, 0) @[dec_tlu_ctl.scala 2275:62] + node _T_1019 = eq(mhpme_vec[0], UInt<2>("h02")) @[dec_tlu_ctl.scala 2276:34] + node _T_1020 = bits(_T_1019, 0, 0) @[dec_tlu_ctl.scala 2276:62] + node _T_1021 = eq(mhpme_vec[0], UInt<2>("h03")) @[dec_tlu_ctl.scala 2277:34] + node _T_1022 = bits(_T_1021, 0, 0) @[dec_tlu_ctl.scala 2277:62] + node _T_1023 = eq(mhpme_vec[0], UInt<3>("h04")) @[dec_tlu_ctl.scala 2278:34] + node _T_1024 = bits(_T_1023, 0, 0) @[dec_tlu_ctl.scala 2278:62] + node _T_1025 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:96] + node _T_1026 = and(io.tlu_i0_commit_cmt, _T_1025) @[dec_tlu_ctl.scala 2278:94] + node _T_1027 = eq(mhpme_vec[0], UInt<3>("h05")) @[dec_tlu_ctl.scala 2279:34] + node _T_1028 = bits(_T_1027, 0, 0) @[dec_tlu_ctl.scala 2279:62] + node _T_1029 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:96] + node _T_1030 = and(io.tlu_i0_commit_cmt, _T_1029) @[dec_tlu_ctl.scala 2279:94] + node _T_1031 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] + node _T_1032 = and(_T_1030, _T_1031) @[dec_tlu_ctl.scala 2279:115] + node _T_1033 = eq(mhpme_vec[0], UInt<3>("h06")) @[dec_tlu_ctl.scala 2280:34] + node _T_1034 = bits(_T_1033, 0, 0) @[dec_tlu_ctl.scala 2280:62] + node _T_1035 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2280:94] + node _T_1036 = not(io.illegal_r) @[dec_tlu_ctl.scala 2280:117] + node _T_1037 = and(_T_1035, _T_1036) @[dec_tlu_ctl.scala 2280:115] + node _T_1038 = eq(mhpme_vec[0], UInt<3>("h07")) @[dec_tlu_ctl.scala 2281:34] + node _T_1039 = bits(_T_1038, 0, 0) @[dec_tlu_ctl.scala 2281:62] + node _T_1040 = eq(mhpme_vec[0], UInt<4>("h08")) @[dec_tlu_ctl.scala 2282:34] + node _T_1041 = bits(_T_1040, 0, 0) @[dec_tlu_ctl.scala 2282:62] + node _T_1042 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2283:34] + node _T_1043 = bits(_T_1042, 0, 0) @[dec_tlu_ctl.scala 2283:62] + node _T_1044 = eq(mhpme_vec[0], UInt<4>("h09")) @[dec_tlu_ctl.scala 2284:34] + node _T_1045 = bits(_T_1044, 0, 0) @[dec_tlu_ctl.scala 2284:62] + node _T_1046 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2284:91] + node _T_1047 = eq(mhpme_vec[0], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2285:34] + node _T_1048 = bits(_T_1047, 0, 0) @[dec_tlu_ctl.scala 2285:62] + node _T_1049 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2285:105] + node _T_1050 = eq(mhpme_vec[0], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2286:34] + node _T_1051 = bits(_T_1050, 0, 0) @[dec_tlu_ctl.scala 2286:62] + node _T_1052 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2286:91] + node _T_1053 = eq(mhpme_vec[0], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2287:34] + node _T_1054 = bits(_T_1053, 0, 0) @[dec_tlu_ctl.scala 2287:62] + node _T_1055 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2287:91] + node _T_1056 = eq(mhpme_vec[0], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2288:34] + node _T_1057 = bits(_T_1056, 0, 0) @[dec_tlu_ctl.scala 2288:62] + node _T_1058 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2288:91] + node _T_1059 = and(_T_1058, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2288:100] + node _T_1060 = eq(mhpme_vec[0], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2289:34] + node _T_1061 = bits(_T_1060, 0, 0) @[dec_tlu_ctl.scala 2289:62] + node _T_1062 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2289:91] + node _T_1063 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2289:142] + node _T_1064 = and(_T_1062, _T_1063) @[dec_tlu_ctl.scala 2289:101] + node _T_1065 = eq(mhpme_vec[0], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2290:34] + node _T_1066 = bits(_T_1065, 0, 0) @[dec_tlu_ctl.scala 2290:59] + node _T_1067 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2290:89] + node _T_1068 = eq(mhpme_vec[0], UInt<5>("h010")) @[dec_tlu_ctl.scala 2291:34] + node _T_1069 = bits(_T_1068, 0, 0) @[dec_tlu_ctl.scala 2291:59] + node _T_1070 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2291:89] + node _T_1071 = eq(mhpme_vec[0], UInt<5>("h012")) @[dec_tlu_ctl.scala 2292:34] + node _T_1072 = bits(_T_1071, 0, 0) @[dec_tlu_ctl.scala 2292:59] + node _T_1073 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2292:89] + node _T_1074 = eq(mhpme_vec[0], UInt<5>("h011")) @[dec_tlu_ctl.scala 2293:34] + node _T_1075 = bits(_T_1074, 0, 0) @[dec_tlu_ctl.scala 2293:59] + node _T_1076 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2293:89] + node _T_1077 = eq(mhpme_vec[0], UInt<5>("h013")) @[dec_tlu_ctl.scala 2294:34] + node _T_1078 = bits(_T_1077, 0, 0) @[dec_tlu_ctl.scala 2294:59] + node _T_1079 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2294:89] + node _T_1080 = eq(mhpme_vec[0], UInt<5>("h014")) @[dec_tlu_ctl.scala 2295:34] + node _T_1081 = bits(_T_1080, 0, 0) @[dec_tlu_ctl.scala 2295:59] + node _T_1082 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2295:89] + node _T_1083 = eq(mhpme_vec[0], UInt<5>("h015")) @[dec_tlu_ctl.scala 2296:34] + node _T_1084 = bits(_T_1083, 0, 0) @[dec_tlu_ctl.scala 2296:59] + node _T_1085 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2296:89] + node _T_1086 = eq(mhpme_vec[0], UInt<5>("h016")) @[dec_tlu_ctl.scala 2297:34] + node _T_1087 = bits(_T_1086, 0, 0) @[dec_tlu_ctl.scala 2297:59] + node _T_1088 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2297:89] + node _T_1089 = eq(mhpme_vec[0], UInt<5>("h017")) @[dec_tlu_ctl.scala 2298:34] + node _T_1090 = bits(_T_1089, 0, 0) @[dec_tlu_ctl.scala 2298:59] + node _T_1091 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2298:89] + node _T_1092 = eq(mhpme_vec[0], UInt<5>("h018")) @[dec_tlu_ctl.scala 2299:34] + node _T_1093 = bits(_T_1092, 0, 0) @[dec_tlu_ctl.scala 2299:59] + node _T_1094 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2299:89] + node _T_1095 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2299:122] + node _T_1096 = or(_T_1094, _T_1095) @[dec_tlu_ctl.scala 2299:101] + node _T_1097 = eq(mhpme_vec[0], UInt<5>("h019")) @[dec_tlu_ctl.scala 2300:34] + node _T_1098 = bits(_T_1097, 0, 0) @[dec_tlu_ctl.scala 2300:62] + node _T_1099 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:95] + node _T_1100 = eq(mhpme_vec[0], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2301:34] + node _T_1101 = bits(_T_1100, 0, 0) @[dec_tlu_ctl.scala 2301:62] + node _T_1102 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:97] + node _T_1103 = eq(mhpme_vec[0], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2302:34] + node _T_1104 = bits(_T_1103, 0, 0) @[dec_tlu_ctl.scala 2302:62] + node _T_1105 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2302:110] + node _T_1106 = eq(mhpme_vec[0], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2303:34] + node _T_1107 = bits(_T_1106, 0, 0) @[dec_tlu_ctl.scala 2303:62] + node _T_1108 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2304:34] + node _T_1109 = bits(_T_1108, 0, 0) @[dec_tlu_ctl.scala 2304:62] + node _T_1110 = eq(mhpme_vec[0], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2305:34] + node _T_1111 = bits(_T_1110, 0, 0) @[dec_tlu_ctl.scala 2305:62] + node _T_1112 = eq(mhpme_vec[0], UInt<6>("h020")) @[dec_tlu_ctl.scala 2306:34] + node _T_1113 = bits(_T_1112, 0, 0) @[dec_tlu_ctl.scala 2306:62] + node _T_1114 = eq(mhpme_vec[0], UInt<6>("h022")) @[dec_tlu_ctl.scala 2307:34] + node _T_1115 = bits(_T_1114, 0, 0) @[dec_tlu_ctl.scala 2307:62] + node _T_1116 = eq(mhpme_vec[0], UInt<6>("h023")) @[dec_tlu_ctl.scala 2308:34] + node _T_1117 = bits(_T_1116, 0, 0) @[dec_tlu_ctl.scala 2308:62] + node _T_1118 = eq(mhpme_vec[0], UInt<6>("h024")) @[dec_tlu_ctl.scala 2309:34] + node _T_1119 = bits(_T_1118, 0, 0) @[dec_tlu_ctl.scala 2309:62] + node _T_1120 = eq(mhpme_vec[0], UInt<6>("h025")) @[dec_tlu_ctl.scala 2310:34] + node _T_1121 = bits(_T_1120, 0, 0) @[dec_tlu_ctl.scala 2310:62] + node _T_1122 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2310:98] + node _T_1123 = or(_T_1122, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2310:120] + node _T_1124 = eq(mhpme_vec[0], UInt<6>("h026")) @[dec_tlu_ctl.scala 2311:34] + node _T_1125 = bits(_T_1124, 0, 0) @[dec_tlu_ctl.scala 2311:62] + node _T_1126 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2311:92] + node _T_1127 = or(_T_1126, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2311:117] + node _T_1128 = eq(mhpme_vec[0], UInt<6>("h027")) @[dec_tlu_ctl.scala 2312:34] + node _T_1129 = bits(_T_1128, 0, 0) @[dec_tlu_ctl.scala 2312:62] + node _T_1130 = eq(mhpme_vec[0], UInt<6>("h028")) @[dec_tlu_ctl.scala 2313:34] + node _T_1131 = bits(_T_1130, 0, 0) @[dec_tlu_ctl.scala 2313:62] + node _T_1132 = eq(mhpme_vec[0], UInt<6>("h029")) @[dec_tlu_ctl.scala 2314:34] + node _T_1133 = bits(_T_1132, 0, 0) @[dec_tlu_ctl.scala 2314:62] + node _T_1134 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2314:97] + node _T_1135 = and(_T_1134, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2314:129] + node _T_1136 = eq(mhpme_vec[0], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2315:34] + node _T_1137 = bits(_T_1136, 0, 0) @[dec_tlu_ctl.scala 2315:62] + node _T_1138 = eq(mhpme_vec[0], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2316:34] + node _T_1139 = bits(_T_1138, 0, 0) @[dec_tlu_ctl.scala 2316:62] + node _T_1140 = eq(mhpme_vec[0], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2317:34] + node _T_1141 = bits(_T_1140, 0, 0) @[dec_tlu_ctl.scala 2317:62] + node _T_1142 = eq(mhpme_vec[0], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2318:34] + node _T_1143 = bits(_T_1142, 0, 0) @[dec_tlu_ctl.scala 2318:62] + node _T_1144 = eq(mhpme_vec[0], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2319:34] + node _T_1145 = bits(_T_1144, 0, 0) @[dec_tlu_ctl.scala 2319:62] + node _T_1146 = eq(mhpme_vec[0], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2320:34] + node _T_1147 = bits(_T_1146, 0, 0) @[dec_tlu_ctl.scala 2320:62] + node _T_1148 = eq(mhpme_vec[0], UInt<6>("h030")) @[dec_tlu_ctl.scala 2321:34] + node _T_1149 = bits(_T_1148, 0, 0) @[dec_tlu_ctl.scala 2321:62] + node _T_1150 = eq(mhpme_vec[0], UInt<6>("h031")) @[dec_tlu_ctl.scala 2322:34] + node _T_1151 = bits(_T_1150, 0, 0) @[dec_tlu_ctl.scala 2322:62] + node _T_1152 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] + node _T_1153 = bits(_T_1152, 0, 0) @[dec_tlu_ctl.scala 2322:84] + node _T_1154 = not(_T_1153) @[dec_tlu_ctl.scala 2322:73] + node _T_1155 = eq(mhpme_vec[0], UInt<6>("h032")) @[dec_tlu_ctl.scala 2323:34] + node _T_1156 = bits(_T_1155, 0, 0) @[dec_tlu_ctl.scala 2323:62] + node _T_1157 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2323:84] + node _T_1158 = bits(_T_1157, 0, 0) @[dec_tlu_ctl.scala 2323:84] + node _T_1159 = not(_T_1158) @[dec_tlu_ctl.scala 2323:73] + node _T_1160 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2323:107] + node _T_1161 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2323:118] + node _T_1162 = and(_T_1160, _T_1161) @[dec_tlu_ctl.scala 2323:113] + node _T_1163 = orr(_T_1162) @[dec_tlu_ctl.scala 2323:125] + node _T_1164 = and(_T_1159, _T_1163) @[dec_tlu_ctl.scala 2323:98] + node _T_1165 = eq(mhpme_vec[0], UInt<6>("h036")) @[dec_tlu_ctl.scala 2324:34] + node _T_1166 = bits(_T_1165, 0, 0) @[dec_tlu_ctl.scala 2324:62] + node _T_1167 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2324:91] + node _T_1168 = eq(mhpme_vec[0], UInt<6>("h037")) @[dec_tlu_ctl.scala 2325:34] + node _T_1169 = bits(_T_1168, 0, 0) @[dec_tlu_ctl.scala 2325:62] + node _T_1170 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2325:94] + node _T_1171 = eq(mhpme_vec[0], UInt<6>("h038")) @[dec_tlu_ctl.scala 2326:34] + node _T_1172 = bits(_T_1171, 0, 0) @[dec_tlu_ctl.scala 2326:62] + node _T_1173 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2326:94] + node _T_1174 = eq(mhpme_vec[0], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2328:34] + node _T_1175 = bits(_T_1174, 0, 0) @[dec_tlu_ctl.scala 2328:62] + node _T_1176 = eq(mhpme_vec[0], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2329:34] + node _T_1177 = bits(_T_1176, 0, 0) @[dec_tlu_ctl.scala 2329:62] + node _T_1178 = eq(mhpme_vec[0], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2330:34] + node _T_1179 = bits(_T_1178, 0, 0) @[dec_tlu_ctl.scala 2330:62] + node _T_1180 = eq(mhpme_vec[0], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2331:34] + node _T_1181 = bits(_T_1180, 0, 0) @[dec_tlu_ctl.scala 2331:62] + node _T_1182 = eq(mhpme_vec[0], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2332:34] + node _T_1183 = bits(_T_1182, 0, 0) @[dec_tlu_ctl.scala 2332:62] + node _T_1184 = mux(_T_1018, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1185 = mux(_T_1020, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1186 = mux(_T_1022, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1187 = mux(_T_1024, _T_1026, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1188 = mux(_T_1028, _T_1032, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1189 = mux(_T_1034, _T_1037, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1190 = mux(_T_1039, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1191 = mux(_T_1041, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1192 = mux(_T_1043, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1193 = mux(_T_1045, _T_1046, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1194 = mux(_T_1048, _T_1049, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1195 = mux(_T_1051, _T_1052, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1196 = mux(_T_1054, _T_1055, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1197 = mux(_T_1057, _T_1059, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1198 = mux(_T_1061, _T_1064, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1199 = mux(_T_1066, _T_1067, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1200 = mux(_T_1069, _T_1070, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1201 = mux(_T_1072, _T_1073, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1202 = mux(_T_1075, _T_1076, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1203 = mux(_T_1078, _T_1079, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1204 = mux(_T_1081, _T_1082, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1205 = mux(_T_1084, _T_1085, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1206 = mux(_T_1087, _T_1088, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1207 = mux(_T_1090, _T_1091, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1208 = mux(_T_1093, _T_1096, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1209 = mux(_T_1098, _T_1099, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1210 = mux(_T_1101, _T_1102, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1211 = mux(_T_1104, _T_1105, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1212 = mux(_T_1107, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1213 = mux(_T_1109, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1214 = mux(_T_1111, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1215 = mux(_T_1113, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1216 = mux(_T_1115, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1217 = mux(_T_1117, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1218 = mux(_T_1119, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1219 = mux(_T_1121, _T_1123, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1220 = mux(_T_1125, _T_1127, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1221 = mux(_T_1129, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1222 = mux(_T_1131, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1223 = mux(_T_1133, _T_1135, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1224 = mux(_T_1137, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1225 = mux(_T_1139, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1226 = mux(_T_1141, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1227 = mux(_T_1143, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1228 = mux(_T_1145, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1229 = mux(_T_1147, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1230 = mux(_T_1149, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1231 = mux(_T_1151, _T_1154, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1232 = mux(_T_1156, _T_1164, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1233 = mux(_T_1166, _T_1167, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1234 = mux(_T_1169, _T_1170, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1235 = mux(_T_1172, _T_1173, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1236 = mux(_T_1175, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1237 = mux(_T_1177, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1238 = mux(_T_1179, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1239 = mux(_T_1181, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1240 = mux(_T_1183, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1241 = or(_T_1184, _T_1185) @[Mux.scala 27:72] + node _T_1242 = or(_T_1241, _T_1186) @[Mux.scala 27:72] + node _T_1243 = or(_T_1242, _T_1187) @[Mux.scala 27:72] + node _T_1244 = or(_T_1243, _T_1188) @[Mux.scala 27:72] + node _T_1245 = or(_T_1244, _T_1189) @[Mux.scala 27:72] + node _T_1246 = or(_T_1245, _T_1190) @[Mux.scala 27:72] + node _T_1247 = or(_T_1246, _T_1191) @[Mux.scala 27:72] + node _T_1248 = or(_T_1247, _T_1192) @[Mux.scala 27:72] + node _T_1249 = or(_T_1248, _T_1193) @[Mux.scala 27:72] + node _T_1250 = or(_T_1249, _T_1194) @[Mux.scala 27:72] + node _T_1251 = or(_T_1250, _T_1195) @[Mux.scala 27:72] node _T_1252 = or(_T_1251, _T_1196) @[Mux.scala 27:72] node _T_1253 = or(_T_1252, _T_1197) @[Mux.scala 27:72] node _T_1254 = or(_T_1253, _T_1198) @[Mux.scala 27:72] @@ -74686,247 +74686,247 @@ circuit quasar_wrapper : node _T_1294 = or(_T_1293, _T_1238) @[Mux.scala 27:72] node _T_1295 = or(_T_1294, _T_1239) @[Mux.scala 27:72] node _T_1296 = or(_T_1295, _T_1240) @[Mux.scala 27:72] - node _T_1297 = or(_T_1296, _T_1241) @[Mux.scala 27:72] - node _T_1298 = or(_T_1297, _T_1242) @[Mux.scala 27:72] - node _T_1299 = or(_T_1298, _T_1243) @[Mux.scala 27:72] - node _T_1300 = or(_T_1299, _T_1244) @[Mux.scala 27:72] - node _T_1301 = or(_T_1300, _T_1245) @[Mux.scala 27:72] - node _T_1302 = or(_T_1301, _T_1246) @[Mux.scala 27:72] - node _T_1303 = or(_T_1302, _T_1247) @[Mux.scala 27:72] - node _T_1304 = or(_T_1303, _T_1248) @[Mux.scala 27:72] - node _T_1305 = or(_T_1304, _T_1249) @[Mux.scala 27:72] - node _T_1306 = or(_T_1305, _T_1250) @[Mux.scala 27:72] - wire _T_1307 : UInt<1> @[Mux.scala 27:72] - _T_1307 <= _T_1306 @[Mux.scala 27:72] - node _T_1308 = and(_T_1026, _T_1307) @[dec_tlu_ctl.scala 2274:44] - mhpmc_inc_r[0] <= _T_1308 @[dec_tlu_ctl.scala 2274:19] - node _T_1309 = bits(mcountinhibit, 4, 4) @[dec_tlu_ctl.scala 2274:38] - node _T_1310 = not(_T_1309) @[dec_tlu_ctl.scala 2274:24] - node _T_1311 = eq(mhpme_vec[1], UInt<1>("h01")) @[dec_tlu_ctl.scala 2275:34] - node _T_1312 = bits(_T_1311, 0, 0) @[dec_tlu_ctl.scala 2275:62] - node _T_1313 = eq(mhpme_vec[1], UInt<2>("h02")) @[dec_tlu_ctl.scala 2276:34] - node _T_1314 = bits(_T_1313, 0, 0) @[dec_tlu_ctl.scala 2276:62] - node _T_1315 = eq(mhpme_vec[1], UInt<2>("h03")) @[dec_tlu_ctl.scala 2277:34] - node _T_1316 = bits(_T_1315, 0, 0) @[dec_tlu_ctl.scala 2277:62] - node _T_1317 = eq(mhpme_vec[1], UInt<3>("h04")) @[dec_tlu_ctl.scala 2278:34] - node _T_1318 = bits(_T_1317, 0, 0) @[dec_tlu_ctl.scala 2278:62] - node _T_1319 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:96] - node _T_1320 = and(io.tlu_i0_commit_cmt, _T_1319) @[dec_tlu_ctl.scala 2278:94] - node _T_1321 = eq(mhpme_vec[1], UInt<3>("h05")) @[dec_tlu_ctl.scala 2279:34] - node _T_1322 = bits(_T_1321, 0, 0) @[dec_tlu_ctl.scala 2279:62] - node _T_1323 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:96] - node _T_1324 = and(io.tlu_i0_commit_cmt, _T_1323) @[dec_tlu_ctl.scala 2279:94] - node _T_1325 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] - node _T_1326 = and(_T_1324, _T_1325) @[dec_tlu_ctl.scala 2279:115] - node _T_1327 = eq(mhpme_vec[1], UInt<3>("h06")) @[dec_tlu_ctl.scala 2280:34] - node _T_1328 = bits(_T_1327, 0, 0) @[dec_tlu_ctl.scala 2280:62] - node _T_1329 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2280:94] - node _T_1330 = not(io.illegal_r) @[dec_tlu_ctl.scala 2280:117] - node _T_1331 = and(_T_1329, _T_1330) @[dec_tlu_ctl.scala 2280:115] - node _T_1332 = eq(mhpme_vec[1], UInt<3>("h07")) @[dec_tlu_ctl.scala 2281:34] - node _T_1333 = bits(_T_1332, 0, 0) @[dec_tlu_ctl.scala 2281:62] - node _T_1334 = eq(mhpme_vec[1], UInt<4>("h08")) @[dec_tlu_ctl.scala 2282:34] - node _T_1335 = bits(_T_1334, 0, 0) @[dec_tlu_ctl.scala 2282:62] - node _T_1336 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2283:34] - node _T_1337 = bits(_T_1336, 0, 0) @[dec_tlu_ctl.scala 2283:62] - node _T_1338 = eq(mhpme_vec[1], UInt<4>("h09")) @[dec_tlu_ctl.scala 2284:34] - node _T_1339 = bits(_T_1338, 0, 0) @[dec_tlu_ctl.scala 2284:62] - node _T_1340 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2284:91] - node _T_1341 = eq(mhpme_vec[1], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2285:34] - node _T_1342 = bits(_T_1341, 0, 0) @[dec_tlu_ctl.scala 2285:62] - node _T_1343 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2285:105] - node _T_1344 = eq(mhpme_vec[1], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2286:34] - node _T_1345 = bits(_T_1344, 0, 0) @[dec_tlu_ctl.scala 2286:62] - node _T_1346 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2286:91] - node _T_1347 = eq(mhpme_vec[1], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2287:34] - node _T_1348 = bits(_T_1347, 0, 0) @[dec_tlu_ctl.scala 2287:62] - node _T_1349 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2287:91] - node _T_1350 = eq(mhpme_vec[1], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2288:34] - node _T_1351 = bits(_T_1350, 0, 0) @[dec_tlu_ctl.scala 2288:62] - node _T_1352 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2288:91] - node _T_1353 = and(_T_1352, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2288:100] - node _T_1354 = eq(mhpme_vec[1], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2289:34] - node _T_1355 = bits(_T_1354, 0, 0) @[dec_tlu_ctl.scala 2289:62] - node _T_1356 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2289:91] - node _T_1357 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2289:142] - node _T_1358 = and(_T_1356, _T_1357) @[dec_tlu_ctl.scala 2289:101] - node _T_1359 = eq(mhpme_vec[1], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2290:34] - node _T_1360 = bits(_T_1359, 0, 0) @[dec_tlu_ctl.scala 2290:59] - node _T_1361 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2290:89] - node _T_1362 = eq(mhpme_vec[1], UInt<5>("h010")) @[dec_tlu_ctl.scala 2291:34] - node _T_1363 = bits(_T_1362, 0, 0) @[dec_tlu_ctl.scala 2291:59] - node _T_1364 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2291:89] - node _T_1365 = eq(mhpme_vec[1], UInt<5>("h012")) @[dec_tlu_ctl.scala 2292:34] - node _T_1366 = bits(_T_1365, 0, 0) @[dec_tlu_ctl.scala 2292:59] - node _T_1367 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2292:89] - node _T_1368 = eq(mhpme_vec[1], UInt<5>("h011")) @[dec_tlu_ctl.scala 2293:34] - node _T_1369 = bits(_T_1368, 0, 0) @[dec_tlu_ctl.scala 2293:59] - node _T_1370 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2293:89] - node _T_1371 = eq(mhpme_vec[1], UInt<5>("h013")) @[dec_tlu_ctl.scala 2294:34] - node _T_1372 = bits(_T_1371, 0, 0) @[dec_tlu_ctl.scala 2294:59] - node _T_1373 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2294:89] - node _T_1374 = eq(mhpme_vec[1], UInt<5>("h014")) @[dec_tlu_ctl.scala 2295:34] - node _T_1375 = bits(_T_1374, 0, 0) @[dec_tlu_ctl.scala 2295:59] - node _T_1376 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2295:89] - node _T_1377 = eq(mhpme_vec[1], UInt<5>("h015")) @[dec_tlu_ctl.scala 2296:34] - node _T_1378 = bits(_T_1377, 0, 0) @[dec_tlu_ctl.scala 2296:59] - node _T_1379 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2296:89] - node _T_1380 = eq(mhpme_vec[1], UInt<5>("h016")) @[dec_tlu_ctl.scala 2297:34] - node _T_1381 = bits(_T_1380, 0, 0) @[dec_tlu_ctl.scala 2297:59] - node _T_1382 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2297:89] - node _T_1383 = eq(mhpme_vec[1], UInt<5>("h017")) @[dec_tlu_ctl.scala 2298:34] - node _T_1384 = bits(_T_1383, 0, 0) @[dec_tlu_ctl.scala 2298:59] - node _T_1385 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2298:89] - node _T_1386 = eq(mhpme_vec[1], UInt<5>("h018")) @[dec_tlu_ctl.scala 2299:34] - node _T_1387 = bits(_T_1386, 0, 0) @[dec_tlu_ctl.scala 2299:59] - node _T_1388 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2299:89] - node _T_1389 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2299:122] - node _T_1390 = or(_T_1388, _T_1389) @[dec_tlu_ctl.scala 2299:101] - node _T_1391 = eq(mhpme_vec[1], UInt<5>("h019")) @[dec_tlu_ctl.scala 2300:34] - node _T_1392 = bits(_T_1391, 0, 0) @[dec_tlu_ctl.scala 2300:62] - node _T_1393 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:95] - node _T_1394 = eq(mhpme_vec[1], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2301:34] - node _T_1395 = bits(_T_1394, 0, 0) @[dec_tlu_ctl.scala 2301:62] - node _T_1396 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:97] - node _T_1397 = eq(mhpme_vec[1], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2302:34] - node _T_1398 = bits(_T_1397, 0, 0) @[dec_tlu_ctl.scala 2302:62] - node _T_1399 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2302:110] - node _T_1400 = eq(mhpme_vec[1], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2303:34] - node _T_1401 = bits(_T_1400, 0, 0) @[dec_tlu_ctl.scala 2303:62] - node _T_1402 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2304:34] - node _T_1403 = bits(_T_1402, 0, 0) @[dec_tlu_ctl.scala 2304:62] - node _T_1404 = eq(mhpme_vec[1], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2305:34] - node _T_1405 = bits(_T_1404, 0, 0) @[dec_tlu_ctl.scala 2305:62] - node _T_1406 = eq(mhpme_vec[1], UInt<6>("h020")) @[dec_tlu_ctl.scala 2306:34] - node _T_1407 = bits(_T_1406, 0, 0) @[dec_tlu_ctl.scala 2306:62] - node _T_1408 = eq(mhpme_vec[1], UInt<6>("h022")) @[dec_tlu_ctl.scala 2307:34] - node _T_1409 = bits(_T_1408, 0, 0) @[dec_tlu_ctl.scala 2307:62] - node _T_1410 = eq(mhpme_vec[1], UInt<6>("h023")) @[dec_tlu_ctl.scala 2308:34] - node _T_1411 = bits(_T_1410, 0, 0) @[dec_tlu_ctl.scala 2308:62] - node _T_1412 = eq(mhpme_vec[1], UInt<6>("h024")) @[dec_tlu_ctl.scala 2309:34] - node _T_1413 = bits(_T_1412, 0, 0) @[dec_tlu_ctl.scala 2309:62] - node _T_1414 = eq(mhpme_vec[1], UInt<6>("h025")) @[dec_tlu_ctl.scala 2310:34] - node _T_1415 = bits(_T_1414, 0, 0) @[dec_tlu_ctl.scala 2310:62] - node _T_1416 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2310:98] - node _T_1417 = or(_T_1416, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2310:120] - node _T_1418 = eq(mhpme_vec[1], UInt<6>("h026")) @[dec_tlu_ctl.scala 2311:34] - node _T_1419 = bits(_T_1418, 0, 0) @[dec_tlu_ctl.scala 2311:62] - node _T_1420 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2311:92] - node _T_1421 = or(_T_1420, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2311:117] - node _T_1422 = eq(mhpme_vec[1], UInt<6>("h027")) @[dec_tlu_ctl.scala 2312:34] - node _T_1423 = bits(_T_1422, 0, 0) @[dec_tlu_ctl.scala 2312:62] - node _T_1424 = eq(mhpme_vec[1], UInt<6>("h028")) @[dec_tlu_ctl.scala 2313:34] - node _T_1425 = bits(_T_1424, 0, 0) @[dec_tlu_ctl.scala 2313:62] - node _T_1426 = eq(mhpme_vec[1], UInt<6>("h029")) @[dec_tlu_ctl.scala 2314:34] - node _T_1427 = bits(_T_1426, 0, 0) @[dec_tlu_ctl.scala 2314:62] - node _T_1428 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2314:97] - node _T_1429 = and(_T_1428, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2314:129] - node _T_1430 = eq(mhpme_vec[1], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2315:34] - node _T_1431 = bits(_T_1430, 0, 0) @[dec_tlu_ctl.scala 2315:62] - node _T_1432 = eq(mhpme_vec[1], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2316:34] - node _T_1433 = bits(_T_1432, 0, 0) @[dec_tlu_ctl.scala 2316:62] - node _T_1434 = eq(mhpme_vec[1], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2317:34] - node _T_1435 = bits(_T_1434, 0, 0) @[dec_tlu_ctl.scala 2317:62] - node _T_1436 = eq(mhpme_vec[1], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2318:34] - node _T_1437 = bits(_T_1436, 0, 0) @[dec_tlu_ctl.scala 2318:62] - node _T_1438 = eq(mhpme_vec[1], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2319:34] - node _T_1439 = bits(_T_1438, 0, 0) @[dec_tlu_ctl.scala 2319:62] - node _T_1440 = eq(mhpme_vec[1], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2320:34] - node _T_1441 = bits(_T_1440, 0, 0) @[dec_tlu_ctl.scala 2320:62] - node _T_1442 = eq(mhpme_vec[1], UInt<6>("h030")) @[dec_tlu_ctl.scala 2321:34] - node _T_1443 = bits(_T_1442, 0, 0) @[dec_tlu_ctl.scala 2321:62] - node _T_1444 = eq(mhpme_vec[1], UInt<6>("h031")) @[dec_tlu_ctl.scala 2322:34] - node _T_1445 = bits(_T_1444, 0, 0) @[dec_tlu_ctl.scala 2322:62] - node _T_1446 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] - node _T_1447 = bits(_T_1446, 0, 0) @[dec_tlu_ctl.scala 2322:84] - node _T_1448 = not(_T_1447) @[dec_tlu_ctl.scala 2322:73] - node _T_1449 = eq(mhpme_vec[1], UInt<6>("h032")) @[dec_tlu_ctl.scala 2323:34] - node _T_1450 = bits(_T_1449, 0, 0) @[dec_tlu_ctl.scala 2323:62] - node _T_1451 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2323:84] - node _T_1452 = bits(_T_1451, 0, 0) @[dec_tlu_ctl.scala 2323:84] - node _T_1453 = not(_T_1452) @[dec_tlu_ctl.scala 2323:73] - node _T_1454 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2323:107] - node _T_1455 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2323:118] - node _T_1456 = and(_T_1454, _T_1455) @[dec_tlu_ctl.scala 2323:113] - node _T_1457 = orr(_T_1456) @[dec_tlu_ctl.scala 2323:125] - node _T_1458 = and(_T_1453, _T_1457) @[dec_tlu_ctl.scala 2323:98] - node _T_1459 = eq(mhpme_vec[1], UInt<6>("h036")) @[dec_tlu_ctl.scala 2324:34] - node _T_1460 = bits(_T_1459, 0, 0) @[dec_tlu_ctl.scala 2324:62] - node _T_1461 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2324:91] - node _T_1462 = eq(mhpme_vec[1], UInt<6>("h037")) @[dec_tlu_ctl.scala 2325:34] - node _T_1463 = bits(_T_1462, 0, 0) @[dec_tlu_ctl.scala 2325:62] - node _T_1464 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2325:94] - node _T_1465 = eq(mhpme_vec[1], UInt<6>("h038")) @[dec_tlu_ctl.scala 2326:34] - node _T_1466 = bits(_T_1465, 0, 0) @[dec_tlu_ctl.scala 2326:62] - node _T_1467 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2326:94] - node _T_1468 = eq(mhpme_vec[1], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2328:34] - node _T_1469 = bits(_T_1468, 0, 0) @[dec_tlu_ctl.scala 2328:62] - node _T_1470 = eq(mhpme_vec[1], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2329:34] - node _T_1471 = bits(_T_1470, 0, 0) @[dec_tlu_ctl.scala 2329:62] - node _T_1472 = eq(mhpme_vec[1], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2330:34] - node _T_1473 = bits(_T_1472, 0, 0) @[dec_tlu_ctl.scala 2330:62] - node _T_1474 = eq(mhpme_vec[1], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2331:34] - node _T_1475 = bits(_T_1474, 0, 0) @[dec_tlu_ctl.scala 2331:62] - node _T_1476 = eq(mhpme_vec[1], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2332:34] - node _T_1477 = bits(_T_1476, 0, 0) @[dec_tlu_ctl.scala 2332:62] - node _T_1478 = mux(_T_1312, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1479 = mux(_T_1314, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1480 = mux(_T_1316, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1481 = mux(_T_1318, _T_1320, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1482 = mux(_T_1322, _T_1326, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1483 = mux(_T_1328, _T_1331, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1484 = mux(_T_1333, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1485 = mux(_T_1335, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1486 = mux(_T_1337, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1487 = mux(_T_1339, _T_1340, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1488 = mux(_T_1342, _T_1343, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1489 = mux(_T_1345, _T_1346, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1490 = mux(_T_1348, _T_1349, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1491 = mux(_T_1351, _T_1353, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1492 = mux(_T_1355, _T_1358, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1493 = mux(_T_1360, _T_1361, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1494 = mux(_T_1363, _T_1364, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1495 = mux(_T_1366, _T_1367, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1496 = mux(_T_1369, _T_1370, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1497 = mux(_T_1372, _T_1373, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1498 = mux(_T_1375, _T_1376, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1499 = mux(_T_1378, _T_1379, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1500 = mux(_T_1381, _T_1382, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1501 = mux(_T_1384, _T_1385, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1502 = mux(_T_1387, _T_1390, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1503 = mux(_T_1392, _T_1393, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1504 = mux(_T_1395, _T_1396, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1505 = mux(_T_1398, _T_1399, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1506 = mux(_T_1401, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1507 = mux(_T_1403, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1508 = mux(_T_1405, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1509 = mux(_T_1407, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1510 = mux(_T_1409, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1511 = mux(_T_1411, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1512 = mux(_T_1413, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1513 = mux(_T_1415, _T_1417, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1514 = mux(_T_1419, _T_1421, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1515 = mux(_T_1423, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1516 = mux(_T_1425, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1517 = mux(_T_1427, _T_1429, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1518 = mux(_T_1431, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1519 = mux(_T_1433, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1520 = mux(_T_1435, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1521 = mux(_T_1437, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1522 = mux(_T_1439, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1523 = mux(_T_1441, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1524 = mux(_T_1443, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1525 = mux(_T_1445, _T_1448, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1526 = mux(_T_1450, _T_1458, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1527 = mux(_T_1460, _T_1461, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1528 = mux(_T_1463, _T_1464, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1529 = mux(_T_1466, _T_1467, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1530 = mux(_T_1469, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1531 = mux(_T_1471, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1532 = mux(_T_1473, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1533 = mux(_T_1475, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1534 = mux(_T_1477, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1535 = or(_T_1478, _T_1479) @[Mux.scala 27:72] + wire _T_1297 : UInt<1> @[Mux.scala 27:72] + _T_1297 <= _T_1296 @[Mux.scala 27:72] + node _T_1298 = and(_T_1016, _T_1297) @[dec_tlu_ctl.scala 2274:44] + mhpmc_inc_r[0] <= _T_1298 @[dec_tlu_ctl.scala 2274:19] + node _T_1299 = bits(mcountinhibit, 4, 4) @[dec_tlu_ctl.scala 2274:38] + node _T_1300 = not(_T_1299) @[dec_tlu_ctl.scala 2274:24] + node _T_1301 = eq(mhpme_vec[1], UInt<1>("h01")) @[dec_tlu_ctl.scala 2275:34] + node _T_1302 = bits(_T_1301, 0, 0) @[dec_tlu_ctl.scala 2275:62] + node _T_1303 = eq(mhpme_vec[1], UInt<2>("h02")) @[dec_tlu_ctl.scala 2276:34] + node _T_1304 = bits(_T_1303, 0, 0) @[dec_tlu_ctl.scala 2276:62] + node _T_1305 = eq(mhpme_vec[1], UInt<2>("h03")) @[dec_tlu_ctl.scala 2277:34] + node _T_1306 = bits(_T_1305, 0, 0) @[dec_tlu_ctl.scala 2277:62] + node _T_1307 = eq(mhpme_vec[1], UInt<3>("h04")) @[dec_tlu_ctl.scala 2278:34] + node _T_1308 = bits(_T_1307, 0, 0) @[dec_tlu_ctl.scala 2278:62] + node _T_1309 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:96] + node _T_1310 = and(io.tlu_i0_commit_cmt, _T_1309) @[dec_tlu_ctl.scala 2278:94] + node _T_1311 = eq(mhpme_vec[1], UInt<3>("h05")) @[dec_tlu_ctl.scala 2279:34] + node _T_1312 = bits(_T_1311, 0, 0) @[dec_tlu_ctl.scala 2279:62] + node _T_1313 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:96] + node _T_1314 = and(io.tlu_i0_commit_cmt, _T_1313) @[dec_tlu_ctl.scala 2279:94] + node _T_1315 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] + node _T_1316 = and(_T_1314, _T_1315) @[dec_tlu_ctl.scala 2279:115] + node _T_1317 = eq(mhpme_vec[1], UInt<3>("h06")) @[dec_tlu_ctl.scala 2280:34] + node _T_1318 = bits(_T_1317, 0, 0) @[dec_tlu_ctl.scala 2280:62] + node _T_1319 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2280:94] + node _T_1320 = not(io.illegal_r) @[dec_tlu_ctl.scala 2280:117] + node _T_1321 = and(_T_1319, _T_1320) @[dec_tlu_ctl.scala 2280:115] + node _T_1322 = eq(mhpme_vec[1], UInt<3>("h07")) @[dec_tlu_ctl.scala 2281:34] + node _T_1323 = bits(_T_1322, 0, 0) @[dec_tlu_ctl.scala 2281:62] + node _T_1324 = eq(mhpme_vec[1], UInt<4>("h08")) @[dec_tlu_ctl.scala 2282:34] + node _T_1325 = bits(_T_1324, 0, 0) @[dec_tlu_ctl.scala 2282:62] + node _T_1326 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2283:34] + node _T_1327 = bits(_T_1326, 0, 0) @[dec_tlu_ctl.scala 2283:62] + node _T_1328 = eq(mhpme_vec[1], UInt<4>("h09")) @[dec_tlu_ctl.scala 2284:34] + node _T_1329 = bits(_T_1328, 0, 0) @[dec_tlu_ctl.scala 2284:62] + node _T_1330 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2284:91] + node _T_1331 = eq(mhpme_vec[1], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2285:34] + node _T_1332 = bits(_T_1331, 0, 0) @[dec_tlu_ctl.scala 2285:62] + node _T_1333 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2285:105] + node _T_1334 = eq(mhpme_vec[1], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2286:34] + node _T_1335 = bits(_T_1334, 0, 0) @[dec_tlu_ctl.scala 2286:62] + node _T_1336 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2286:91] + node _T_1337 = eq(mhpme_vec[1], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2287:34] + node _T_1338 = bits(_T_1337, 0, 0) @[dec_tlu_ctl.scala 2287:62] + node _T_1339 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2287:91] + node _T_1340 = eq(mhpme_vec[1], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2288:34] + node _T_1341 = bits(_T_1340, 0, 0) @[dec_tlu_ctl.scala 2288:62] + node _T_1342 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2288:91] + node _T_1343 = and(_T_1342, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2288:100] + node _T_1344 = eq(mhpme_vec[1], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2289:34] + node _T_1345 = bits(_T_1344, 0, 0) @[dec_tlu_ctl.scala 2289:62] + node _T_1346 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2289:91] + node _T_1347 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2289:142] + node _T_1348 = and(_T_1346, _T_1347) @[dec_tlu_ctl.scala 2289:101] + node _T_1349 = eq(mhpme_vec[1], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2290:34] + node _T_1350 = bits(_T_1349, 0, 0) @[dec_tlu_ctl.scala 2290:59] + node _T_1351 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2290:89] + node _T_1352 = eq(mhpme_vec[1], UInt<5>("h010")) @[dec_tlu_ctl.scala 2291:34] + node _T_1353 = bits(_T_1352, 0, 0) @[dec_tlu_ctl.scala 2291:59] + node _T_1354 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2291:89] + node _T_1355 = eq(mhpme_vec[1], UInt<5>("h012")) @[dec_tlu_ctl.scala 2292:34] + node _T_1356 = bits(_T_1355, 0, 0) @[dec_tlu_ctl.scala 2292:59] + node _T_1357 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2292:89] + node _T_1358 = eq(mhpme_vec[1], UInt<5>("h011")) @[dec_tlu_ctl.scala 2293:34] + node _T_1359 = bits(_T_1358, 0, 0) @[dec_tlu_ctl.scala 2293:59] + node _T_1360 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2293:89] + node _T_1361 = eq(mhpme_vec[1], UInt<5>("h013")) @[dec_tlu_ctl.scala 2294:34] + node _T_1362 = bits(_T_1361, 0, 0) @[dec_tlu_ctl.scala 2294:59] + node _T_1363 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2294:89] + node _T_1364 = eq(mhpme_vec[1], UInt<5>("h014")) @[dec_tlu_ctl.scala 2295:34] + node _T_1365 = bits(_T_1364, 0, 0) @[dec_tlu_ctl.scala 2295:59] + node _T_1366 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2295:89] + node _T_1367 = eq(mhpme_vec[1], UInt<5>("h015")) @[dec_tlu_ctl.scala 2296:34] + node _T_1368 = bits(_T_1367, 0, 0) @[dec_tlu_ctl.scala 2296:59] + node _T_1369 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2296:89] + node _T_1370 = eq(mhpme_vec[1], UInt<5>("h016")) @[dec_tlu_ctl.scala 2297:34] + node _T_1371 = bits(_T_1370, 0, 0) @[dec_tlu_ctl.scala 2297:59] + node _T_1372 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2297:89] + node _T_1373 = eq(mhpme_vec[1], UInt<5>("h017")) @[dec_tlu_ctl.scala 2298:34] + node _T_1374 = bits(_T_1373, 0, 0) @[dec_tlu_ctl.scala 2298:59] + node _T_1375 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2298:89] + node _T_1376 = eq(mhpme_vec[1], UInt<5>("h018")) @[dec_tlu_ctl.scala 2299:34] + node _T_1377 = bits(_T_1376, 0, 0) @[dec_tlu_ctl.scala 2299:59] + node _T_1378 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2299:89] + node _T_1379 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2299:122] + node _T_1380 = or(_T_1378, _T_1379) @[dec_tlu_ctl.scala 2299:101] + node _T_1381 = eq(mhpme_vec[1], UInt<5>("h019")) @[dec_tlu_ctl.scala 2300:34] + node _T_1382 = bits(_T_1381, 0, 0) @[dec_tlu_ctl.scala 2300:62] + node _T_1383 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:95] + node _T_1384 = eq(mhpme_vec[1], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2301:34] + node _T_1385 = bits(_T_1384, 0, 0) @[dec_tlu_ctl.scala 2301:62] + node _T_1386 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:97] + node _T_1387 = eq(mhpme_vec[1], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2302:34] + node _T_1388 = bits(_T_1387, 0, 0) @[dec_tlu_ctl.scala 2302:62] + node _T_1389 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2302:110] + node _T_1390 = eq(mhpme_vec[1], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2303:34] + node _T_1391 = bits(_T_1390, 0, 0) @[dec_tlu_ctl.scala 2303:62] + node _T_1392 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2304:34] + node _T_1393 = bits(_T_1392, 0, 0) @[dec_tlu_ctl.scala 2304:62] + node _T_1394 = eq(mhpme_vec[1], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2305:34] + node _T_1395 = bits(_T_1394, 0, 0) @[dec_tlu_ctl.scala 2305:62] + node _T_1396 = eq(mhpme_vec[1], UInt<6>("h020")) @[dec_tlu_ctl.scala 2306:34] + node _T_1397 = bits(_T_1396, 0, 0) @[dec_tlu_ctl.scala 2306:62] + node _T_1398 = eq(mhpme_vec[1], UInt<6>("h022")) @[dec_tlu_ctl.scala 2307:34] + node _T_1399 = bits(_T_1398, 0, 0) @[dec_tlu_ctl.scala 2307:62] + node _T_1400 = eq(mhpme_vec[1], UInt<6>("h023")) @[dec_tlu_ctl.scala 2308:34] + node _T_1401 = bits(_T_1400, 0, 0) @[dec_tlu_ctl.scala 2308:62] + node _T_1402 = eq(mhpme_vec[1], UInt<6>("h024")) @[dec_tlu_ctl.scala 2309:34] + node _T_1403 = bits(_T_1402, 0, 0) @[dec_tlu_ctl.scala 2309:62] + node _T_1404 = eq(mhpme_vec[1], UInt<6>("h025")) @[dec_tlu_ctl.scala 2310:34] + node _T_1405 = bits(_T_1404, 0, 0) @[dec_tlu_ctl.scala 2310:62] + node _T_1406 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2310:98] + node _T_1407 = or(_T_1406, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2310:120] + node _T_1408 = eq(mhpme_vec[1], UInt<6>("h026")) @[dec_tlu_ctl.scala 2311:34] + node _T_1409 = bits(_T_1408, 0, 0) @[dec_tlu_ctl.scala 2311:62] + node _T_1410 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2311:92] + node _T_1411 = or(_T_1410, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2311:117] + node _T_1412 = eq(mhpme_vec[1], UInt<6>("h027")) @[dec_tlu_ctl.scala 2312:34] + node _T_1413 = bits(_T_1412, 0, 0) @[dec_tlu_ctl.scala 2312:62] + node _T_1414 = eq(mhpme_vec[1], UInt<6>("h028")) @[dec_tlu_ctl.scala 2313:34] + node _T_1415 = bits(_T_1414, 0, 0) @[dec_tlu_ctl.scala 2313:62] + node _T_1416 = eq(mhpme_vec[1], UInt<6>("h029")) @[dec_tlu_ctl.scala 2314:34] + node _T_1417 = bits(_T_1416, 0, 0) @[dec_tlu_ctl.scala 2314:62] + node _T_1418 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2314:97] + node _T_1419 = and(_T_1418, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2314:129] + node _T_1420 = eq(mhpme_vec[1], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2315:34] + node _T_1421 = bits(_T_1420, 0, 0) @[dec_tlu_ctl.scala 2315:62] + node _T_1422 = eq(mhpme_vec[1], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2316:34] + node _T_1423 = bits(_T_1422, 0, 0) @[dec_tlu_ctl.scala 2316:62] + node _T_1424 = eq(mhpme_vec[1], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2317:34] + node _T_1425 = bits(_T_1424, 0, 0) @[dec_tlu_ctl.scala 2317:62] + node _T_1426 = eq(mhpme_vec[1], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2318:34] + node _T_1427 = bits(_T_1426, 0, 0) @[dec_tlu_ctl.scala 2318:62] + node _T_1428 = eq(mhpme_vec[1], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2319:34] + node _T_1429 = bits(_T_1428, 0, 0) @[dec_tlu_ctl.scala 2319:62] + node _T_1430 = eq(mhpme_vec[1], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2320:34] + node _T_1431 = bits(_T_1430, 0, 0) @[dec_tlu_ctl.scala 2320:62] + node _T_1432 = eq(mhpme_vec[1], UInt<6>("h030")) @[dec_tlu_ctl.scala 2321:34] + node _T_1433 = bits(_T_1432, 0, 0) @[dec_tlu_ctl.scala 2321:62] + node _T_1434 = eq(mhpme_vec[1], UInt<6>("h031")) @[dec_tlu_ctl.scala 2322:34] + node _T_1435 = bits(_T_1434, 0, 0) @[dec_tlu_ctl.scala 2322:62] + node _T_1436 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] + node _T_1437 = bits(_T_1436, 0, 0) @[dec_tlu_ctl.scala 2322:84] + node _T_1438 = not(_T_1437) @[dec_tlu_ctl.scala 2322:73] + node _T_1439 = eq(mhpme_vec[1], UInt<6>("h032")) @[dec_tlu_ctl.scala 2323:34] + node _T_1440 = bits(_T_1439, 0, 0) @[dec_tlu_ctl.scala 2323:62] + node _T_1441 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2323:84] + node _T_1442 = bits(_T_1441, 0, 0) @[dec_tlu_ctl.scala 2323:84] + node _T_1443 = not(_T_1442) @[dec_tlu_ctl.scala 2323:73] + node _T_1444 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2323:107] + node _T_1445 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2323:118] + node _T_1446 = and(_T_1444, _T_1445) @[dec_tlu_ctl.scala 2323:113] + node _T_1447 = orr(_T_1446) @[dec_tlu_ctl.scala 2323:125] + node _T_1448 = and(_T_1443, _T_1447) @[dec_tlu_ctl.scala 2323:98] + node _T_1449 = eq(mhpme_vec[1], UInt<6>("h036")) @[dec_tlu_ctl.scala 2324:34] + node _T_1450 = bits(_T_1449, 0, 0) @[dec_tlu_ctl.scala 2324:62] + node _T_1451 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2324:91] + node _T_1452 = eq(mhpme_vec[1], UInt<6>("h037")) @[dec_tlu_ctl.scala 2325:34] + node _T_1453 = bits(_T_1452, 0, 0) @[dec_tlu_ctl.scala 2325:62] + node _T_1454 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2325:94] + node _T_1455 = eq(mhpme_vec[1], UInt<6>("h038")) @[dec_tlu_ctl.scala 2326:34] + node _T_1456 = bits(_T_1455, 0, 0) @[dec_tlu_ctl.scala 2326:62] + node _T_1457 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2326:94] + node _T_1458 = eq(mhpme_vec[1], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2328:34] + node _T_1459 = bits(_T_1458, 0, 0) @[dec_tlu_ctl.scala 2328:62] + node _T_1460 = eq(mhpme_vec[1], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2329:34] + node _T_1461 = bits(_T_1460, 0, 0) @[dec_tlu_ctl.scala 2329:62] + node _T_1462 = eq(mhpme_vec[1], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2330:34] + node _T_1463 = bits(_T_1462, 0, 0) @[dec_tlu_ctl.scala 2330:62] + node _T_1464 = eq(mhpme_vec[1], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2331:34] + node _T_1465 = bits(_T_1464, 0, 0) @[dec_tlu_ctl.scala 2331:62] + node _T_1466 = eq(mhpme_vec[1], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2332:34] + node _T_1467 = bits(_T_1466, 0, 0) @[dec_tlu_ctl.scala 2332:62] + node _T_1468 = mux(_T_1302, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1469 = mux(_T_1304, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1470 = mux(_T_1306, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1471 = mux(_T_1308, _T_1310, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1472 = mux(_T_1312, _T_1316, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1473 = mux(_T_1318, _T_1321, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1474 = mux(_T_1323, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1475 = mux(_T_1325, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1476 = mux(_T_1327, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1477 = mux(_T_1329, _T_1330, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1478 = mux(_T_1332, _T_1333, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1479 = mux(_T_1335, _T_1336, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1480 = mux(_T_1338, _T_1339, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1481 = mux(_T_1341, _T_1343, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1482 = mux(_T_1345, _T_1348, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1483 = mux(_T_1350, _T_1351, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1484 = mux(_T_1353, _T_1354, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1485 = mux(_T_1356, _T_1357, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1486 = mux(_T_1359, _T_1360, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1487 = mux(_T_1362, _T_1363, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1488 = mux(_T_1365, _T_1366, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1489 = mux(_T_1368, _T_1369, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1490 = mux(_T_1371, _T_1372, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1491 = mux(_T_1374, _T_1375, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1492 = mux(_T_1377, _T_1380, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1493 = mux(_T_1382, _T_1383, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1494 = mux(_T_1385, _T_1386, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1495 = mux(_T_1388, _T_1389, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1496 = mux(_T_1391, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1497 = mux(_T_1393, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1498 = mux(_T_1395, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1499 = mux(_T_1397, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1500 = mux(_T_1399, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1501 = mux(_T_1401, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1502 = mux(_T_1403, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1503 = mux(_T_1405, _T_1407, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1504 = mux(_T_1409, _T_1411, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1505 = mux(_T_1413, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1506 = mux(_T_1415, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1507 = mux(_T_1417, _T_1419, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1508 = mux(_T_1421, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1509 = mux(_T_1423, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1510 = mux(_T_1425, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1511 = mux(_T_1427, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1512 = mux(_T_1429, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1513 = mux(_T_1431, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1514 = mux(_T_1433, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1515 = mux(_T_1435, _T_1438, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1516 = mux(_T_1440, _T_1448, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1517 = mux(_T_1450, _T_1451, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1518 = mux(_T_1453, _T_1454, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1519 = mux(_T_1456, _T_1457, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1520 = mux(_T_1459, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1521 = mux(_T_1461, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1522 = mux(_T_1463, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1523 = mux(_T_1465, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1524 = mux(_T_1467, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1525 = or(_T_1468, _T_1469) @[Mux.scala 27:72] + node _T_1526 = or(_T_1525, _T_1470) @[Mux.scala 27:72] + node _T_1527 = or(_T_1526, _T_1471) @[Mux.scala 27:72] + node _T_1528 = or(_T_1527, _T_1472) @[Mux.scala 27:72] + node _T_1529 = or(_T_1528, _T_1473) @[Mux.scala 27:72] + node _T_1530 = or(_T_1529, _T_1474) @[Mux.scala 27:72] + node _T_1531 = or(_T_1530, _T_1475) @[Mux.scala 27:72] + node _T_1532 = or(_T_1531, _T_1476) @[Mux.scala 27:72] + node _T_1533 = or(_T_1532, _T_1477) @[Mux.scala 27:72] + node _T_1534 = or(_T_1533, _T_1478) @[Mux.scala 27:72] + node _T_1535 = or(_T_1534, _T_1479) @[Mux.scala 27:72] node _T_1536 = or(_T_1535, _T_1480) @[Mux.scala 27:72] node _T_1537 = or(_T_1536, _T_1481) @[Mux.scala 27:72] node _T_1538 = or(_T_1537, _T_1482) @[Mux.scala 27:72] @@ -74972,247 +74972,247 @@ circuit quasar_wrapper : node _T_1578 = or(_T_1577, _T_1522) @[Mux.scala 27:72] node _T_1579 = or(_T_1578, _T_1523) @[Mux.scala 27:72] node _T_1580 = or(_T_1579, _T_1524) @[Mux.scala 27:72] - node _T_1581 = or(_T_1580, _T_1525) @[Mux.scala 27:72] - node _T_1582 = or(_T_1581, _T_1526) @[Mux.scala 27:72] - node _T_1583 = or(_T_1582, _T_1527) @[Mux.scala 27:72] - node _T_1584 = or(_T_1583, _T_1528) @[Mux.scala 27:72] - node _T_1585 = or(_T_1584, _T_1529) @[Mux.scala 27:72] - node _T_1586 = or(_T_1585, _T_1530) @[Mux.scala 27:72] - node _T_1587 = or(_T_1586, _T_1531) @[Mux.scala 27:72] - node _T_1588 = or(_T_1587, _T_1532) @[Mux.scala 27:72] - node _T_1589 = or(_T_1588, _T_1533) @[Mux.scala 27:72] - node _T_1590 = or(_T_1589, _T_1534) @[Mux.scala 27:72] - wire _T_1591 : UInt<1> @[Mux.scala 27:72] - _T_1591 <= _T_1590 @[Mux.scala 27:72] - node _T_1592 = and(_T_1310, _T_1591) @[dec_tlu_ctl.scala 2274:44] - mhpmc_inc_r[1] <= _T_1592 @[dec_tlu_ctl.scala 2274:19] - node _T_1593 = bits(mcountinhibit, 5, 5) @[dec_tlu_ctl.scala 2274:38] - node _T_1594 = not(_T_1593) @[dec_tlu_ctl.scala 2274:24] - node _T_1595 = eq(mhpme_vec[2], UInt<1>("h01")) @[dec_tlu_ctl.scala 2275:34] - node _T_1596 = bits(_T_1595, 0, 0) @[dec_tlu_ctl.scala 2275:62] - node _T_1597 = eq(mhpme_vec[2], UInt<2>("h02")) @[dec_tlu_ctl.scala 2276:34] - node _T_1598 = bits(_T_1597, 0, 0) @[dec_tlu_ctl.scala 2276:62] - node _T_1599 = eq(mhpme_vec[2], UInt<2>("h03")) @[dec_tlu_ctl.scala 2277:34] - node _T_1600 = bits(_T_1599, 0, 0) @[dec_tlu_ctl.scala 2277:62] - node _T_1601 = eq(mhpme_vec[2], UInt<3>("h04")) @[dec_tlu_ctl.scala 2278:34] - node _T_1602 = bits(_T_1601, 0, 0) @[dec_tlu_ctl.scala 2278:62] - node _T_1603 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:96] - node _T_1604 = and(io.tlu_i0_commit_cmt, _T_1603) @[dec_tlu_ctl.scala 2278:94] - node _T_1605 = eq(mhpme_vec[2], UInt<3>("h05")) @[dec_tlu_ctl.scala 2279:34] - node _T_1606 = bits(_T_1605, 0, 0) @[dec_tlu_ctl.scala 2279:62] - node _T_1607 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:96] - node _T_1608 = and(io.tlu_i0_commit_cmt, _T_1607) @[dec_tlu_ctl.scala 2279:94] - node _T_1609 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] - node _T_1610 = and(_T_1608, _T_1609) @[dec_tlu_ctl.scala 2279:115] - node _T_1611 = eq(mhpme_vec[2], UInt<3>("h06")) @[dec_tlu_ctl.scala 2280:34] - node _T_1612 = bits(_T_1611, 0, 0) @[dec_tlu_ctl.scala 2280:62] - node _T_1613 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2280:94] - node _T_1614 = not(io.illegal_r) @[dec_tlu_ctl.scala 2280:117] - node _T_1615 = and(_T_1613, _T_1614) @[dec_tlu_ctl.scala 2280:115] - node _T_1616 = eq(mhpme_vec[2], UInt<3>("h07")) @[dec_tlu_ctl.scala 2281:34] - node _T_1617 = bits(_T_1616, 0, 0) @[dec_tlu_ctl.scala 2281:62] - node _T_1618 = eq(mhpme_vec[2], UInt<4>("h08")) @[dec_tlu_ctl.scala 2282:34] - node _T_1619 = bits(_T_1618, 0, 0) @[dec_tlu_ctl.scala 2282:62] - node _T_1620 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2283:34] - node _T_1621 = bits(_T_1620, 0, 0) @[dec_tlu_ctl.scala 2283:62] - node _T_1622 = eq(mhpme_vec[2], UInt<4>("h09")) @[dec_tlu_ctl.scala 2284:34] - node _T_1623 = bits(_T_1622, 0, 0) @[dec_tlu_ctl.scala 2284:62] - node _T_1624 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2284:91] - node _T_1625 = eq(mhpme_vec[2], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2285:34] - node _T_1626 = bits(_T_1625, 0, 0) @[dec_tlu_ctl.scala 2285:62] - node _T_1627 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2285:105] - node _T_1628 = eq(mhpme_vec[2], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2286:34] - node _T_1629 = bits(_T_1628, 0, 0) @[dec_tlu_ctl.scala 2286:62] - node _T_1630 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2286:91] - node _T_1631 = eq(mhpme_vec[2], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2287:34] - node _T_1632 = bits(_T_1631, 0, 0) @[dec_tlu_ctl.scala 2287:62] - node _T_1633 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2287:91] - node _T_1634 = eq(mhpme_vec[2], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2288:34] - node _T_1635 = bits(_T_1634, 0, 0) @[dec_tlu_ctl.scala 2288:62] - node _T_1636 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2288:91] - node _T_1637 = and(_T_1636, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2288:100] - node _T_1638 = eq(mhpme_vec[2], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2289:34] - node _T_1639 = bits(_T_1638, 0, 0) @[dec_tlu_ctl.scala 2289:62] - node _T_1640 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2289:91] - node _T_1641 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2289:142] - node _T_1642 = and(_T_1640, _T_1641) @[dec_tlu_ctl.scala 2289:101] - node _T_1643 = eq(mhpme_vec[2], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2290:34] - node _T_1644 = bits(_T_1643, 0, 0) @[dec_tlu_ctl.scala 2290:59] - node _T_1645 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2290:89] - node _T_1646 = eq(mhpme_vec[2], UInt<5>("h010")) @[dec_tlu_ctl.scala 2291:34] - node _T_1647 = bits(_T_1646, 0, 0) @[dec_tlu_ctl.scala 2291:59] - node _T_1648 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2291:89] - node _T_1649 = eq(mhpme_vec[2], UInt<5>("h012")) @[dec_tlu_ctl.scala 2292:34] - node _T_1650 = bits(_T_1649, 0, 0) @[dec_tlu_ctl.scala 2292:59] - node _T_1651 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2292:89] - node _T_1652 = eq(mhpme_vec[2], UInt<5>("h011")) @[dec_tlu_ctl.scala 2293:34] - node _T_1653 = bits(_T_1652, 0, 0) @[dec_tlu_ctl.scala 2293:59] - node _T_1654 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2293:89] - node _T_1655 = eq(mhpme_vec[2], UInt<5>("h013")) @[dec_tlu_ctl.scala 2294:34] - node _T_1656 = bits(_T_1655, 0, 0) @[dec_tlu_ctl.scala 2294:59] - node _T_1657 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2294:89] - node _T_1658 = eq(mhpme_vec[2], UInt<5>("h014")) @[dec_tlu_ctl.scala 2295:34] - node _T_1659 = bits(_T_1658, 0, 0) @[dec_tlu_ctl.scala 2295:59] - node _T_1660 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2295:89] - node _T_1661 = eq(mhpme_vec[2], UInt<5>("h015")) @[dec_tlu_ctl.scala 2296:34] - node _T_1662 = bits(_T_1661, 0, 0) @[dec_tlu_ctl.scala 2296:59] - node _T_1663 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2296:89] - node _T_1664 = eq(mhpme_vec[2], UInt<5>("h016")) @[dec_tlu_ctl.scala 2297:34] - node _T_1665 = bits(_T_1664, 0, 0) @[dec_tlu_ctl.scala 2297:59] - node _T_1666 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2297:89] - node _T_1667 = eq(mhpme_vec[2], UInt<5>("h017")) @[dec_tlu_ctl.scala 2298:34] - node _T_1668 = bits(_T_1667, 0, 0) @[dec_tlu_ctl.scala 2298:59] - node _T_1669 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2298:89] - node _T_1670 = eq(mhpme_vec[2], UInt<5>("h018")) @[dec_tlu_ctl.scala 2299:34] - node _T_1671 = bits(_T_1670, 0, 0) @[dec_tlu_ctl.scala 2299:59] - node _T_1672 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2299:89] - node _T_1673 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2299:122] - node _T_1674 = or(_T_1672, _T_1673) @[dec_tlu_ctl.scala 2299:101] - node _T_1675 = eq(mhpme_vec[2], UInt<5>("h019")) @[dec_tlu_ctl.scala 2300:34] - node _T_1676 = bits(_T_1675, 0, 0) @[dec_tlu_ctl.scala 2300:62] - node _T_1677 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:95] - node _T_1678 = eq(mhpme_vec[2], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2301:34] - node _T_1679 = bits(_T_1678, 0, 0) @[dec_tlu_ctl.scala 2301:62] - node _T_1680 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:97] - node _T_1681 = eq(mhpme_vec[2], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2302:34] - node _T_1682 = bits(_T_1681, 0, 0) @[dec_tlu_ctl.scala 2302:62] - node _T_1683 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2302:110] - node _T_1684 = eq(mhpme_vec[2], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2303:34] - node _T_1685 = bits(_T_1684, 0, 0) @[dec_tlu_ctl.scala 2303:62] - node _T_1686 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2304:34] - node _T_1687 = bits(_T_1686, 0, 0) @[dec_tlu_ctl.scala 2304:62] - node _T_1688 = eq(mhpme_vec[2], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2305:34] - node _T_1689 = bits(_T_1688, 0, 0) @[dec_tlu_ctl.scala 2305:62] - node _T_1690 = eq(mhpme_vec[2], UInt<6>("h020")) @[dec_tlu_ctl.scala 2306:34] - node _T_1691 = bits(_T_1690, 0, 0) @[dec_tlu_ctl.scala 2306:62] - node _T_1692 = eq(mhpme_vec[2], UInt<6>("h022")) @[dec_tlu_ctl.scala 2307:34] - node _T_1693 = bits(_T_1692, 0, 0) @[dec_tlu_ctl.scala 2307:62] - node _T_1694 = eq(mhpme_vec[2], UInt<6>("h023")) @[dec_tlu_ctl.scala 2308:34] - node _T_1695 = bits(_T_1694, 0, 0) @[dec_tlu_ctl.scala 2308:62] - node _T_1696 = eq(mhpme_vec[2], UInt<6>("h024")) @[dec_tlu_ctl.scala 2309:34] - node _T_1697 = bits(_T_1696, 0, 0) @[dec_tlu_ctl.scala 2309:62] - node _T_1698 = eq(mhpme_vec[2], UInt<6>("h025")) @[dec_tlu_ctl.scala 2310:34] - node _T_1699 = bits(_T_1698, 0, 0) @[dec_tlu_ctl.scala 2310:62] - node _T_1700 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2310:98] - node _T_1701 = or(_T_1700, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2310:120] - node _T_1702 = eq(mhpme_vec[2], UInt<6>("h026")) @[dec_tlu_ctl.scala 2311:34] - node _T_1703 = bits(_T_1702, 0, 0) @[dec_tlu_ctl.scala 2311:62] - node _T_1704 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2311:92] - node _T_1705 = or(_T_1704, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2311:117] - node _T_1706 = eq(mhpme_vec[2], UInt<6>("h027")) @[dec_tlu_ctl.scala 2312:34] - node _T_1707 = bits(_T_1706, 0, 0) @[dec_tlu_ctl.scala 2312:62] - node _T_1708 = eq(mhpme_vec[2], UInt<6>("h028")) @[dec_tlu_ctl.scala 2313:34] - node _T_1709 = bits(_T_1708, 0, 0) @[dec_tlu_ctl.scala 2313:62] - node _T_1710 = eq(mhpme_vec[2], UInt<6>("h029")) @[dec_tlu_ctl.scala 2314:34] - node _T_1711 = bits(_T_1710, 0, 0) @[dec_tlu_ctl.scala 2314:62] - node _T_1712 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2314:97] - node _T_1713 = and(_T_1712, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2314:129] - node _T_1714 = eq(mhpme_vec[2], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2315:34] - node _T_1715 = bits(_T_1714, 0, 0) @[dec_tlu_ctl.scala 2315:62] - node _T_1716 = eq(mhpme_vec[2], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2316:34] - node _T_1717 = bits(_T_1716, 0, 0) @[dec_tlu_ctl.scala 2316:62] - node _T_1718 = eq(mhpme_vec[2], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2317:34] - node _T_1719 = bits(_T_1718, 0, 0) @[dec_tlu_ctl.scala 2317:62] - node _T_1720 = eq(mhpme_vec[2], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2318:34] - node _T_1721 = bits(_T_1720, 0, 0) @[dec_tlu_ctl.scala 2318:62] - node _T_1722 = eq(mhpme_vec[2], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2319:34] - node _T_1723 = bits(_T_1722, 0, 0) @[dec_tlu_ctl.scala 2319:62] - node _T_1724 = eq(mhpme_vec[2], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2320:34] - node _T_1725 = bits(_T_1724, 0, 0) @[dec_tlu_ctl.scala 2320:62] - node _T_1726 = eq(mhpme_vec[2], UInt<6>("h030")) @[dec_tlu_ctl.scala 2321:34] - node _T_1727 = bits(_T_1726, 0, 0) @[dec_tlu_ctl.scala 2321:62] - node _T_1728 = eq(mhpme_vec[2], UInt<6>("h031")) @[dec_tlu_ctl.scala 2322:34] - node _T_1729 = bits(_T_1728, 0, 0) @[dec_tlu_ctl.scala 2322:62] - node _T_1730 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] - node _T_1731 = bits(_T_1730, 0, 0) @[dec_tlu_ctl.scala 2322:84] - node _T_1732 = not(_T_1731) @[dec_tlu_ctl.scala 2322:73] - node _T_1733 = eq(mhpme_vec[2], UInt<6>("h032")) @[dec_tlu_ctl.scala 2323:34] - node _T_1734 = bits(_T_1733, 0, 0) @[dec_tlu_ctl.scala 2323:62] - node _T_1735 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2323:84] - node _T_1736 = bits(_T_1735, 0, 0) @[dec_tlu_ctl.scala 2323:84] - node _T_1737 = not(_T_1736) @[dec_tlu_ctl.scala 2323:73] - node _T_1738 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2323:107] - node _T_1739 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2323:118] - node _T_1740 = and(_T_1738, _T_1739) @[dec_tlu_ctl.scala 2323:113] - node _T_1741 = orr(_T_1740) @[dec_tlu_ctl.scala 2323:125] - node _T_1742 = and(_T_1737, _T_1741) @[dec_tlu_ctl.scala 2323:98] - node _T_1743 = eq(mhpme_vec[2], UInt<6>("h036")) @[dec_tlu_ctl.scala 2324:34] - node _T_1744 = bits(_T_1743, 0, 0) @[dec_tlu_ctl.scala 2324:62] - node _T_1745 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2324:91] - node _T_1746 = eq(mhpme_vec[2], UInt<6>("h037")) @[dec_tlu_ctl.scala 2325:34] - node _T_1747 = bits(_T_1746, 0, 0) @[dec_tlu_ctl.scala 2325:62] - node _T_1748 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2325:94] - node _T_1749 = eq(mhpme_vec[2], UInt<6>("h038")) @[dec_tlu_ctl.scala 2326:34] - node _T_1750 = bits(_T_1749, 0, 0) @[dec_tlu_ctl.scala 2326:62] - node _T_1751 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2326:94] - node _T_1752 = eq(mhpme_vec[2], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2328:34] - node _T_1753 = bits(_T_1752, 0, 0) @[dec_tlu_ctl.scala 2328:62] - node _T_1754 = eq(mhpme_vec[2], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2329:34] - node _T_1755 = bits(_T_1754, 0, 0) @[dec_tlu_ctl.scala 2329:62] - node _T_1756 = eq(mhpme_vec[2], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2330:34] - node _T_1757 = bits(_T_1756, 0, 0) @[dec_tlu_ctl.scala 2330:62] - node _T_1758 = eq(mhpme_vec[2], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2331:34] - node _T_1759 = bits(_T_1758, 0, 0) @[dec_tlu_ctl.scala 2331:62] - node _T_1760 = eq(mhpme_vec[2], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2332:34] - node _T_1761 = bits(_T_1760, 0, 0) @[dec_tlu_ctl.scala 2332:62] - node _T_1762 = mux(_T_1596, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1763 = mux(_T_1598, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1764 = mux(_T_1600, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1765 = mux(_T_1602, _T_1604, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1766 = mux(_T_1606, _T_1610, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1767 = mux(_T_1612, _T_1615, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1768 = mux(_T_1617, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1769 = mux(_T_1619, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1770 = mux(_T_1621, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1771 = mux(_T_1623, _T_1624, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1772 = mux(_T_1626, _T_1627, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1773 = mux(_T_1629, _T_1630, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1774 = mux(_T_1632, _T_1633, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1775 = mux(_T_1635, _T_1637, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1776 = mux(_T_1639, _T_1642, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1777 = mux(_T_1644, _T_1645, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1778 = mux(_T_1647, _T_1648, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1779 = mux(_T_1650, _T_1651, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1780 = mux(_T_1653, _T_1654, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1781 = mux(_T_1656, _T_1657, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1782 = mux(_T_1659, _T_1660, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1783 = mux(_T_1662, _T_1663, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1784 = mux(_T_1665, _T_1666, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1785 = mux(_T_1668, _T_1669, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1786 = mux(_T_1671, _T_1674, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1787 = mux(_T_1676, _T_1677, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1788 = mux(_T_1679, _T_1680, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1789 = mux(_T_1682, _T_1683, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1790 = mux(_T_1685, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1791 = mux(_T_1687, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1792 = mux(_T_1689, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1793 = mux(_T_1691, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1794 = mux(_T_1693, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1795 = mux(_T_1695, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1796 = mux(_T_1697, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1797 = mux(_T_1699, _T_1701, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1798 = mux(_T_1703, _T_1705, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1799 = mux(_T_1707, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1800 = mux(_T_1709, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1801 = mux(_T_1711, _T_1713, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1802 = mux(_T_1715, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1803 = mux(_T_1717, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1804 = mux(_T_1719, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1805 = mux(_T_1721, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1806 = mux(_T_1723, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1807 = mux(_T_1725, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1808 = mux(_T_1727, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1809 = mux(_T_1729, _T_1732, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1810 = mux(_T_1734, _T_1742, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1811 = mux(_T_1744, _T_1745, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1812 = mux(_T_1747, _T_1748, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1813 = mux(_T_1750, _T_1751, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1814 = mux(_T_1753, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1815 = mux(_T_1755, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1816 = mux(_T_1757, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1817 = mux(_T_1759, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1818 = mux(_T_1761, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1819 = or(_T_1762, _T_1763) @[Mux.scala 27:72] + wire _T_1581 : UInt<1> @[Mux.scala 27:72] + _T_1581 <= _T_1580 @[Mux.scala 27:72] + node _T_1582 = and(_T_1300, _T_1581) @[dec_tlu_ctl.scala 2274:44] + mhpmc_inc_r[1] <= _T_1582 @[dec_tlu_ctl.scala 2274:19] + node _T_1583 = bits(mcountinhibit, 5, 5) @[dec_tlu_ctl.scala 2274:38] + node _T_1584 = not(_T_1583) @[dec_tlu_ctl.scala 2274:24] + node _T_1585 = eq(mhpme_vec[2], UInt<1>("h01")) @[dec_tlu_ctl.scala 2275:34] + node _T_1586 = bits(_T_1585, 0, 0) @[dec_tlu_ctl.scala 2275:62] + node _T_1587 = eq(mhpme_vec[2], UInt<2>("h02")) @[dec_tlu_ctl.scala 2276:34] + node _T_1588 = bits(_T_1587, 0, 0) @[dec_tlu_ctl.scala 2276:62] + node _T_1589 = eq(mhpme_vec[2], UInt<2>("h03")) @[dec_tlu_ctl.scala 2277:34] + node _T_1590 = bits(_T_1589, 0, 0) @[dec_tlu_ctl.scala 2277:62] + node _T_1591 = eq(mhpme_vec[2], UInt<3>("h04")) @[dec_tlu_ctl.scala 2278:34] + node _T_1592 = bits(_T_1591, 0, 0) @[dec_tlu_ctl.scala 2278:62] + node _T_1593 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:96] + node _T_1594 = and(io.tlu_i0_commit_cmt, _T_1593) @[dec_tlu_ctl.scala 2278:94] + node _T_1595 = eq(mhpme_vec[2], UInt<3>("h05")) @[dec_tlu_ctl.scala 2279:34] + node _T_1596 = bits(_T_1595, 0, 0) @[dec_tlu_ctl.scala 2279:62] + node _T_1597 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:96] + node _T_1598 = and(io.tlu_i0_commit_cmt, _T_1597) @[dec_tlu_ctl.scala 2279:94] + node _T_1599 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] + node _T_1600 = and(_T_1598, _T_1599) @[dec_tlu_ctl.scala 2279:115] + node _T_1601 = eq(mhpme_vec[2], UInt<3>("h06")) @[dec_tlu_ctl.scala 2280:34] + node _T_1602 = bits(_T_1601, 0, 0) @[dec_tlu_ctl.scala 2280:62] + node _T_1603 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2280:94] + node _T_1604 = not(io.illegal_r) @[dec_tlu_ctl.scala 2280:117] + node _T_1605 = and(_T_1603, _T_1604) @[dec_tlu_ctl.scala 2280:115] + node _T_1606 = eq(mhpme_vec[2], UInt<3>("h07")) @[dec_tlu_ctl.scala 2281:34] + node _T_1607 = bits(_T_1606, 0, 0) @[dec_tlu_ctl.scala 2281:62] + node _T_1608 = eq(mhpme_vec[2], UInt<4>("h08")) @[dec_tlu_ctl.scala 2282:34] + node _T_1609 = bits(_T_1608, 0, 0) @[dec_tlu_ctl.scala 2282:62] + node _T_1610 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2283:34] + node _T_1611 = bits(_T_1610, 0, 0) @[dec_tlu_ctl.scala 2283:62] + node _T_1612 = eq(mhpme_vec[2], UInt<4>("h09")) @[dec_tlu_ctl.scala 2284:34] + node _T_1613 = bits(_T_1612, 0, 0) @[dec_tlu_ctl.scala 2284:62] + node _T_1614 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2284:91] + node _T_1615 = eq(mhpme_vec[2], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2285:34] + node _T_1616 = bits(_T_1615, 0, 0) @[dec_tlu_ctl.scala 2285:62] + node _T_1617 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2285:105] + node _T_1618 = eq(mhpme_vec[2], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2286:34] + node _T_1619 = bits(_T_1618, 0, 0) @[dec_tlu_ctl.scala 2286:62] + node _T_1620 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2286:91] + node _T_1621 = eq(mhpme_vec[2], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2287:34] + node _T_1622 = bits(_T_1621, 0, 0) @[dec_tlu_ctl.scala 2287:62] + node _T_1623 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2287:91] + node _T_1624 = eq(mhpme_vec[2], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2288:34] + node _T_1625 = bits(_T_1624, 0, 0) @[dec_tlu_ctl.scala 2288:62] + node _T_1626 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2288:91] + node _T_1627 = and(_T_1626, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2288:100] + node _T_1628 = eq(mhpme_vec[2], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2289:34] + node _T_1629 = bits(_T_1628, 0, 0) @[dec_tlu_ctl.scala 2289:62] + node _T_1630 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2289:91] + node _T_1631 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2289:142] + node _T_1632 = and(_T_1630, _T_1631) @[dec_tlu_ctl.scala 2289:101] + node _T_1633 = eq(mhpme_vec[2], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2290:34] + node _T_1634 = bits(_T_1633, 0, 0) @[dec_tlu_ctl.scala 2290:59] + node _T_1635 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2290:89] + node _T_1636 = eq(mhpme_vec[2], UInt<5>("h010")) @[dec_tlu_ctl.scala 2291:34] + node _T_1637 = bits(_T_1636, 0, 0) @[dec_tlu_ctl.scala 2291:59] + node _T_1638 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2291:89] + node _T_1639 = eq(mhpme_vec[2], UInt<5>("h012")) @[dec_tlu_ctl.scala 2292:34] + node _T_1640 = bits(_T_1639, 0, 0) @[dec_tlu_ctl.scala 2292:59] + node _T_1641 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2292:89] + node _T_1642 = eq(mhpme_vec[2], UInt<5>("h011")) @[dec_tlu_ctl.scala 2293:34] + node _T_1643 = bits(_T_1642, 0, 0) @[dec_tlu_ctl.scala 2293:59] + node _T_1644 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2293:89] + node _T_1645 = eq(mhpme_vec[2], UInt<5>("h013")) @[dec_tlu_ctl.scala 2294:34] + node _T_1646 = bits(_T_1645, 0, 0) @[dec_tlu_ctl.scala 2294:59] + node _T_1647 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2294:89] + node _T_1648 = eq(mhpme_vec[2], UInt<5>("h014")) @[dec_tlu_ctl.scala 2295:34] + node _T_1649 = bits(_T_1648, 0, 0) @[dec_tlu_ctl.scala 2295:59] + node _T_1650 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2295:89] + node _T_1651 = eq(mhpme_vec[2], UInt<5>("h015")) @[dec_tlu_ctl.scala 2296:34] + node _T_1652 = bits(_T_1651, 0, 0) @[dec_tlu_ctl.scala 2296:59] + node _T_1653 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2296:89] + node _T_1654 = eq(mhpme_vec[2], UInt<5>("h016")) @[dec_tlu_ctl.scala 2297:34] + node _T_1655 = bits(_T_1654, 0, 0) @[dec_tlu_ctl.scala 2297:59] + node _T_1656 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2297:89] + node _T_1657 = eq(mhpme_vec[2], UInt<5>("h017")) @[dec_tlu_ctl.scala 2298:34] + node _T_1658 = bits(_T_1657, 0, 0) @[dec_tlu_ctl.scala 2298:59] + node _T_1659 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2298:89] + node _T_1660 = eq(mhpme_vec[2], UInt<5>("h018")) @[dec_tlu_ctl.scala 2299:34] + node _T_1661 = bits(_T_1660, 0, 0) @[dec_tlu_ctl.scala 2299:59] + node _T_1662 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2299:89] + node _T_1663 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2299:122] + node _T_1664 = or(_T_1662, _T_1663) @[dec_tlu_ctl.scala 2299:101] + node _T_1665 = eq(mhpme_vec[2], UInt<5>("h019")) @[dec_tlu_ctl.scala 2300:34] + node _T_1666 = bits(_T_1665, 0, 0) @[dec_tlu_ctl.scala 2300:62] + node _T_1667 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:95] + node _T_1668 = eq(mhpme_vec[2], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2301:34] + node _T_1669 = bits(_T_1668, 0, 0) @[dec_tlu_ctl.scala 2301:62] + node _T_1670 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:97] + node _T_1671 = eq(mhpme_vec[2], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2302:34] + node _T_1672 = bits(_T_1671, 0, 0) @[dec_tlu_ctl.scala 2302:62] + node _T_1673 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2302:110] + node _T_1674 = eq(mhpme_vec[2], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2303:34] + node _T_1675 = bits(_T_1674, 0, 0) @[dec_tlu_ctl.scala 2303:62] + node _T_1676 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2304:34] + node _T_1677 = bits(_T_1676, 0, 0) @[dec_tlu_ctl.scala 2304:62] + node _T_1678 = eq(mhpme_vec[2], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2305:34] + node _T_1679 = bits(_T_1678, 0, 0) @[dec_tlu_ctl.scala 2305:62] + node _T_1680 = eq(mhpme_vec[2], UInt<6>("h020")) @[dec_tlu_ctl.scala 2306:34] + node _T_1681 = bits(_T_1680, 0, 0) @[dec_tlu_ctl.scala 2306:62] + node _T_1682 = eq(mhpme_vec[2], UInt<6>("h022")) @[dec_tlu_ctl.scala 2307:34] + node _T_1683 = bits(_T_1682, 0, 0) @[dec_tlu_ctl.scala 2307:62] + node _T_1684 = eq(mhpme_vec[2], UInt<6>("h023")) @[dec_tlu_ctl.scala 2308:34] + node _T_1685 = bits(_T_1684, 0, 0) @[dec_tlu_ctl.scala 2308:62] + node _T_1686 = eq(mhpme_vec[2], UInt<6>("h024")) @[dec_tlu_ctl.scala 2309:34] + node _T_1687 = bits(_T_1686, 0, 0) @[dec_tlu_ctl.scala 2309:62] + node _T_1688 = eq(mhpme_vec[2], UInt<6>("h025")) @[dec_tlu_ctl.scala 2310:34] + node _T_1689 = bits(_T_1688, 0, 0) @[dec_tlu_ctl.scala 2310:62] + node _T_1690 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2310:98] + node _T_1691 = or(_T_1690, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2310:120] + node _T_1692 = eq(mhpme_vec[2], UInt<6>("h026")) @[dec_tlu_ctl.scala 2311:34] + node _T_1693 = bits(_T_1692, 0, 0) @[dec_tlu_ctl.scala 2311:62] + node _T_1694 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2311:92] + node _T_1695 = or(_T_1694, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2311:117] + node _T_1696 = eq(mhpme_vec[2], UInt<6>("h027")) @[dec_tlu_ctl.scala 2312:34] + node _T_1697 = bits(_T_1696, 0, 0) @[dec_tlu_ctl.scala 2312:62] + node _T_1698 = eq(mhpme_vec[2], UInt<6>("h028")) @[dec_tlu_ctl.scala 2313:34] + node _T_1699 = bits(_T_1698, 0, 0) @[dec_tlu_ctl.scala 2313:62] + node _T_1700 = eq(mhpme_vec[2], UInt<6>("h029")) @[dec_tlu_ctl.scala 2314:34] + node _T_1701 = bits(_T_1700, 0, 0) @[dec_tlu_ctl.scala 2314:62] + node _T_1702 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2314:97] + node _T_1703 = and(_T_1702, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2314:129] + node _T_1704 = eq(mhpme_vec[2], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2315:34] + node _T_1705 = bits(_T_1704, 0, 0) @[dec_tlu_ctl.scala 2315:62] + node _T_1706 = eq(mhpme_vec[2], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2316:34] + node _T_1707 = bits(_T_1706, 0, 0) @[dec_tlu_ctl.scala 2316:62] + node _T_1708 = eq(mhpme_vec[2], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2317:34] + node _T_1709 = bits(_T_1708, 0, 0) @[dec_tlu_ctl.scala 2317:62] + node _T_1710 = eq(mhpme_vec[2], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2318:34] + node _T_1711 = bits(_T_1710, 0, 0) @[dec_tlu_ctl.scala 2318:62] + node _T_1712 = eq(mhpme_vec[2], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2319:34] + node _T_1713 = bits(_T_1712, 0, 0) @[dec_tlu_ctl.scala 2319:62] + node _T_1714 = eq(mhpme_vec[2], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2320:34] + node _T_1715 = bits(_T_1714, 0, 0) @[dec_tlu_ctl.scala 2320:62] + node _T_1716 = eq(mhpme_vec[2], UInt<6>("h030")) @[dec_tlu_ctl.scala 2321:34] + node _T_1717 = bits(_T_1716, 0, 0) @[dec_tlu_ctl.scala 2321:62] + node _T_1718 = eq(mhpme_vec[2], UInt<6>("h031")) @[dec_tlu_ctl.scala 2322:34] + node _T_1719 = bits(_T_1718, 0, 0) @[dec_tlu_ctl.scala 2322:62] + node _T_1720 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] + node _T_1721 = bits(_T_1720, 0, 0) @[dec_tlu_ctl.scala 2322:84] + node _T_1722 = not(_T_1721) @[dec_tlu_ctl.scala 2322:73] + node _T_1723 = eq(mhpme_vec[2], UInt<6>("h032")) @[dec_tlu_ctl.scala 2323:34] + node _T_1724 = bits(_T_1723, 0, 0) @[dec_tlu_ctl.scala 2323:62] + node _T_1725 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2323:84] + node _T_1726 = bits(_T_1725, 0, 0) @[dec_tlu_ctl.scala 2323:84] + node _T_1727 = not(_T_1726) @[dec_tlu_ctl.scala 2323:73] + node _T_1728 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2323:107] + node _T_1729 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2323:118] + node _T_1730 = and(_T_1728, _T_1729) @[dec_tlu_ctl.scala 2323:113] + node _T_1731 = orr(_T_1730) @[dec_tlu_ctl.scala 2323:125] + node _T_1732 = and(_T_1727, _T_1731) @[dec_tlu_ctl.scala 2323:98] + node _T_1733 = eq(mhpme_vec[2], UInt<6>("h036")) @[dec_tlu_ctl.scala 2324:34] + node _T_1734 = bits(_T_1733, 0, 0) @[dec_tlu_ctl.scala 2324:62] + node _T_1735 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2324:91] + node _T_1736 = eq(mhpme_vec[2], UInt<6>("h037")) @[dec_tlu_ctl.scala 2325:34] + node _T_1737 = bits(_T_1736, 0, 0) @[dec_tlu_ctl.scala 2325:62] + node _T_1738 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2325:94] + node _T_1739 = eq(mhpme_vec[2], UInt<6>("h038")) @[dec_tlu_ctl.scala 2326:34] + node _T_1740 = bits(_T_1739, 0, 0) @[dec_tlu_ctl.scala 2326:62] + node _T_1741 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2326:94] + node _T_1742 = eq(mhpme_vec[2], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2328:34] + node _T_1743 = bits(_T_1742, 0, 0) @[dec_tlu_ctl.scala 2328:62] + node _T_1744 = eq(mhpme_vec[2], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2329:34] + node _T_1745 = bits(_T_1744, 0, 0) @[dec_tlu_ctl.scala 2329:62] + node _T_1746 = eq(mhpme_vec[2], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2330:34] + node _T_1747 = bits(_T_1746, 0, 0) @[dec_tlu_ctl.scala 2330:62] + node _T_1748 = eq(mhpme_vec[2], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2331:34] + node _T_1749 = bits(_T_1748, 0, 0) @[dec_tlu_ctl.scala 2331:62] + node _T_1750 = eq(mhpme_vec[2], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2332:34] + node _T_1751 = bits(_T_1750, 0, 0) @[dec_tlu_ctl.scala 2332:62] + node _T_1752 = mux(_T_1586, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1753 = mux(_T_1588, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1754 = mux(_T_1590, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1755 = mux(_T_1592, _T_1594, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1756 = mux(_T_1596, _T_1600, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1757 = mux(_T_1602, _T_1605, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1758 = mux(_T_1607, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1759 = mux(_T_1609, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1760 = mux(_T_1611, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1761 = mux(_T_1613, _T_1614, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1762 = mux(_T_1616, _T_1617, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1763 = mux(_T_1619, _T_1620, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1764 = mux(_T_1622, _T_1623, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1765 = mux(_T_1625, _T_1627, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1766 = mux(_T_1629, _T_1632, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1767 = mux(_T_1634, _T_1635, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1768 = mux(_T_1637, _T_1638, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1769 = mux(_T_1640, _T_1641, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1770 = mux(_T_1643, _T_1644, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1771 = mux(_T_1646, _T_1647, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1772 = mux(_T_1649, _T_1650, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1773 = mux(_T_1652, _T_1653, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1774 = mux(_T_1655, _T_1656, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1775 = mux(_T_1658, _T_1659, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1776 = mux(_T_1661, _T_1664, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1777 = mux(_T_1666, _T_1667, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1778 = mux(_T_1669, _T_1670, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1779 = mux(_T_1672, _T_1673, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1780 = mux(_T_1675, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1781 = mux(_T_1677, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1782 = mux(_T_1679, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1783 = mux(_T_1681, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1784 = mux(_T_1683, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1785 = mux(_T_1685, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1786 = mux(_T_1687, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1787 = mux(_T_1689, _T_1691, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1788 = mux(_T_1693, _T_1695, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1789 = mux(_T_1697, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1790 = mux(_T_1699, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1791 = mux(_T_1701, _T_1703, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1792 = mux(_T_1705, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1793 = mux(_T_1707, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1794 = mux(_T_1709, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1795 = mux(_T_1711, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1796 = mux(_T_1713, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1797 = mux(_T_1715, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1798 = mux(_T_1717, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1799 = mux(_T_1719, _T_1722, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1800 = mux(_T_1724, _T_1732, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1801 = mux(_T_1734, _T_1735, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1802 = mux(_T_1737, _T_1738, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1803 = mux(_T_1740, _T_1741, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1804 = mux(_T_1743, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1805 = mux(_T_1745, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1806 = mux(_T_1747, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1807 = mux(_T_1749, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1808 = mux(_T_1751, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1809 = or(_T_1752, _T_1753) @[Mux.scala 27:72] + node _T_1810 = or(_T_1809, _T_1754) @[Mux.scala 27:72] + node _T_1811 = or(_T_1810, _T_1755) @[Mux.scala 27:72] + node _T_1812 = or(_T_1811, _T_1756) @[Mux.scala 27:72] + node _T_1813 = or(_T_1812, _T_1757) @[Mux.scala 27:72] + node _T_1814 = or(_T_1813, _T_1758) @[Mux.scala 27:72] + node _T_1815 = or(_T_1814, _T_1759) @[Mux.scala 27:72] + node _T_1816 = or(_T_1815, _T_1760) @[Mux.scala 27:72] + node _T_1817 = or(_T_1816, _T_1761) @[Mux.scala 27:72] + node _T_1818 = or(_T_1817, _T_1762) @[Mux.scala 27:72] + node _T_1819 = or(_T_1818, _T_1763) @[Mux.scala 27:72] node _T_1820 = or(_T_1819, _T_1764) @[Mux.scala 27:72] node _T_1821 = or(_T_1820, _T_1765) @[Mux.scala 27:72] node _T_1822 = or(_T_1821, _T_1766) @[Mux.scala 27:72] @@ -75258,247 +75258,247 @@ circuit quasar_wrapper : node _T_1862 = or(_T_1861, _T_1806) @[Mux.scala 27:72] node _T_1863 = or(_T_1862, _T_1807) @[Mux.scala 27:72] node _T_1864 = or(_T_1863, _T_1808) @[Mux.scala 27:72] - node _T_1865 = or(_T_1864, _T_1809) @[Mux.scala 27:72] - node _T_1866 = or(_T_1865, _T_1810) @[Mux.scala 27:72] - node _T_1867 = or(_T_1866, _T_1811) @[Mux.scala 27:72] - node _T_1868 = or(_T_1867, _T_1812) @[Mux.scala 27:72] - node _T_1869 = or(_T_1868, _T_1813) @[Mux.scala 27:72] - node _T_1870 = or(_T_1869, _T_1814) @[Mux.scala 27:72] - node _T_1871 = or(_T_1870, _T_1815) @[Mux.scala 27:72] - node _T_1872 = or(_T_1871, _T_1816) @[Mux.scala 27:72] - node _T_1873 = or(_T_1872, _T_1817) @[Mux.scala 27:72] - node _T_1874 = or(_T_1873, _T_1818) @[Mux.scala 27:72] - wire _T_1875 : UInt<1> @[Mux.scala 27:72] - _T_1875 <= _T_1874 @[Mux.scala 27:72] - node _T_1876 = and(_T_1594, _T_1875) @[dec_tlu_ctl.scala 2274:44] - mhpmc_inc_r[2] <= _T_1876 @[dec_tlu_ctl.scala 2274:19] - node _T_1877 = bits(mcountinhibit, 6, 6) @[dec_tlu_ctl.scala 2274:38] - node _T_1878 = not(_T_1877) @[dec_tlu_ctl.scala 2274:24] - node _T_1879 = eq(mhpme_vec[3], UInt<1>("h01")) @[dec_tlu_ctl.scala 2275:34] - node _T_1880 = bits(_T_1879, 0, 0) @[dec_tlu_ctl.scala 2275:62] - node _T_1881 = eq(mhpme_vec[3], UInt<2>("h02")) @[dec_tlu_ctl.scala 2276:34] - node _T_1882 = bits(_T_1881, 0, 0) @[dec_tlu_ctl.scala 2276:62] - node _T_1883 = eq(mhpme_vec[3], UInt<2>("h03")) @[dec_tlu_ctl.scala 2277:34] - node _T_1884 = bits(_T_1883, 0, 0) @[dec_tlu_ctl.scala 2277:62] - node _T_1885 = eq(mhpme_vec[3], UInt<3>("h04")) @[dec_tlu_ctl.scala 2278:34] - node _T_1886 = bits(_T_1885, 0, 0) @[dec_tlu_ctl.scala 2278:62] - node _T_1887 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:96] - node _T_1888 = and(io.tlu_i0_commit_cmt, _T_1887) @[dec_tlu_ctl.scala 2278:94] - node _T_1889 = eq(mhpme_vec[3], UInt<3>("h05")) @[dec_tlu_ctl.scala 2279:34] - node _T_1890 = bits(_T_1889, 0, 0) @[dec_tlu_ctl.scala 2279:62] - node _T_1891 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:96] - node _T_1892 = and(io.tlu_i0_commit_cmt, _T_1891) @[dec_tlu_ctl.scala 2279:94] - node _T_1893 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] - node _T_1894 = and(_T_1892, _T_1893) @[dec_tlu_ctl.scala 2279:115] - node _T_1895 = eq(mhpme_vec[3], UInt<3>("h06")) @[dec_tlu_ctl.scala 2280:34] - node _T_1896 = bits(_T_1895, 0, 0) @[dec_tlu_ctl.scala 2280:62] - node _T_1897 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2280:94] - node _T_1898 = not(io.illegal_r) @[dec_tlu_ctl.scala 2280:117] - node _T_1899 = and(_T_1897, _T_1898) @[dec_tlu_ctl.scala 2280:115] - node _T_1900 = eq(mhpme_vec[3], UInt<3>("h07")) @[dec_tlu_ctl.scala 2281:34] - node _T_1901 = bits(_T_1900, 0, 0) @[dec_tlu_ctl.scala 2281:62] - node _T_1902 = eq(mhpme_vec[3], UInt<4>("h08")) @[dec_tlu_ctl.scala 2282:34] - node _T_1903 = bits(_T_1902, 0, 0) @[dec_tlu_ctl.scala 2282:62] - node _T_1904 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2283:34] - node _T_1905 = bits(_T_1904, 0, 0) @[dec_tlu_ctl.scala 2283:62] - node _T_1906 = eq(mhpme_vec[3], UInt<4>("h09")) @[dec_tlu_ctl.scala 2284:34] - node _T_1907 = bits(_T_1906, 0, 0) @[dec_tlu_ctl.scala 2284:62] - node _T_1908 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2284:91] - node _T_1909 = eq(mhpme_vec[3], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2285:34] - node _T_1910 = bits(_T_1909, 0, 0) @[dec_tlu_ctl.scala 2285:62] - node _T_1911 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2285:105] - node _T_1912 = eq(mhpme_vec[3], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2286:34] - node _T_1913 = bits(_T_1912, 0, 0) @[dec_tlu_ctl.scala 2286:62] - node _T_1914 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2286:91] - node _T_1915 = eq(mhpme_vec[3], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2287:34] - node _T_1916 = bits(_T_1915, 0, 0) @[dec_tlu_ctl.scala 2287:62] - node _T_1917 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2287:91] - node _T_1918 = eq(mhpme_vec[3], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2288:34] - node _T_1919 = bits(_T_1918, 0, 0) @[dec_tlu_ctl.scala 2288:62] - node _T_1920 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2288:91] - node _T_1921 = and(_T_1920, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2288:100] - node _T_1922 = eq(mhpme_vec[3], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2289:34] - node _T_1923 = bits(_T_1922, 0, 0) @[dec_tlu_ctl.scala 2289:62] - node _T_1924 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2289:91] - node _T_1925 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2289:142] - node _T_1926 = and(_T_1924, _T_1925) @[dec_tlu_ctl.scala 2289:101] - node _T_1927 = eq(mhpme_vec[3], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2290:34] - node _T_1928 = bits(_T_1927, 0, 0) @[dec_tlu_ctl.scala 2290:59] - node _T_1929 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2290:89] - node _T_1930 = eq(mhpme_vec[3], UInt<5>("h010")) @[dec_tlu_ctl.scala 2291:34] - node _T_1931 = bits(_T_1930, 0, 0) @[dec_tlu_ctl.scala 2291:59] - node _T_1932 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2291:89] - node _T_1933 = eq(mhpme_vec[3], UInt<5>("h012")) @[dec_tlu_ctl.scala 2292:34] - node _T_1934 = bits(_T_1933, 0, 0) @[dec_tlu_ctl.scala 2292:59] - node _T_1935 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2292:89] - node _T_1936 = eq(mhpme_vec[3], UInt<5>("h011")) @[dec_tlu_ctl.scala 2293:34] - node _T_1937 = bits(_T_1936, 0, 0) @[dec_tlu_ctl.scala 2293:59] - node _T_1938 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2293:89] - node _T_1939 = eq(mhpme_vec[3], UInt<5>("h013")) @[dec_tlu_ctl.scala 2294:34] - node _T_1940 = bits(_T_1939, 0, 0) @[dec_tlu_ctl.scala 2294:59] - node _T_1941 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2294:89] - node _T_1942 = eq(mhpme_vec[3], UInt<5>("h014")) @[dec_tlu_ctl.scala 2295:34] - node _T_1943 = bits(_T_1942, 0, 0) @[dec_tlu_ctl.scala 2295:59] - node _T_1944 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2295:89] - node _T_1945 = eq(mhpme_vec[3], UInt<5>("h015")) @[dec_tlu_ctl.scala 2296:34] - node _T_1946 = bits(_T_1945, 0, 0) @[dec_tlu_ctl.scala 2296:59] - node _T_1947 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2296:89] - node _T_1948 = eq(mhpme_vec[3], UInt<5>("h016")) @[dec_tlu_ctl.scala 2297:34] - node _T_1949 = bits(_T_1948, 0, 0) @[dec_tlu_ctl.scala 2297:59] - node _T_1950 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2297:89] - node _T_1951 = eq(mhpme_vec[3], UInt<5>("h017")) @[dec_tlu_ctl.scala 2298:34] - node _T_1952 = bits(_T_1951, 0, 0) @[dec_tlu_ctl.scala 2298:59] - node _T_1953 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2298:89] - node _T_1954 = eq(mhpme_vec[3], UInt<5>("h018")) @[dec_tlu_ctl.scala 2299:34] - node _T_1955 = bits(_T_1954, 0, 0) @[dec_tlu_ctl.scala 2299:59] - node _T_1956 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2299:89] - node _T_1957 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2299:122] - node _T_1958 = or(_T_1956, _T_1957) @[dec_tlu_ctl.scala 2299:101] - node _T_1959 = eq(mhpme_vec[3], UInt<5>("h019")) @[dec_tlu_ctl.scala 2300:34] - node _T_1960 = bits(_T_1959, 0, 0) @[dec_tlu_ctl.scala 2300:62] - node _T_1961 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:95] - node _T_1962 = eq(mhpme_vec[3], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2301:34] - node _T_1963 = bits(_T_1962, 0, 0) @[dec_tlu_ctl.scala 2301:62] - node _T_1964 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:97] - node _T_1965 = eq(mhpme_vec[3], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2302:34] - node _T_1966 = bits(_T_1965, 0, 0) @[dec_tlu_ctl.scala 2302:62] - node _T_1967 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2302:110] - node _T_1968 = eq(mhpme_vec[3], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2303:34] - node _T_1969 = bits(_T_1968, 0, 0) @[dec_tlu_ctl.scala 2303:62] - node _T_1970 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2304:34] - node _T_1971 = bits(_T_1970, 0, 0) @[dec_tlu_ctl.scala 2304:62] - node _T_1972 = eq(mhpme_vec[3], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2305:34] - node _T_1973 = bits(_T_1972, 0, 0) @[dec_tlu_ctl.scala 2305:62] - node _T_1974 = eq(mhpme_vec[3], UInt<6>("h020")) @[dec_tlu_ctl.scala 2306:34] - node _T_1975 = bits(_T_1974, 0, 0) @[dec_tlu_ctl.scala 2306:62] - node _T_1976 = eq(mhpme_vec[3], UInt<6>("h022")) @[dec_tlu_ctl.scala 2307:34] - node _T_1977 = bits(_T_1976, 0, 0) @[dec_tlu_ctl.scala 2307:62] - node _T_1978 = eq(mhpme_vec[3], UInt<6>("h023")) @[dec_tlu_ctl.scala 2308:34] - node _T_1979 = bits(_T_1978, 0, 0) @[dec_tlu_ctl.scala 2308:62] - node _T_1980 = eq(mhpme_vec[3], UInt<6>("h024")) @[dec_tlu_ctl.scala 2309:34] - node _T_1981 = bits(_T_1980, 0, 0) @[dec_tlu_ctl.scala 2309:62] - node _T_1982 = eq(mhpme_vec[3], UInt<6>("h025")) @[dec_tlu_ctl.scala 2310:34] - node _T_1983 = bits(_T_1982, 0, 0) @[dec_tlu_ctl.scala 2310:62] - node _T_1984 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2310:98] - node _T_1985 = or(_T_1984, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2310:120] - node _T_1986 = eq(mhpme_vec[3], UInt<6>("h026")) @[dec_tlu_ctl.scala 2311:34] - node _T_1987 = bits(_T_1986, 0, 0) @[dec_tlu_ctl.scala 2311:62] - node _T_1988 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2311:92] - node _T_1989 = or(_T_1988, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2311:117] - node _T_1990 = eq(mhpme_vec[3], UInt<6>("h027")) @[dec_tlu_ctl.scala 2312:34] - node _T_1991 = bits(_T_1990, 0, 0) @[dec_tlu_ctl.scala 2312:62] - node _T_1992 = eq(mhpme_vec[3], UInt<6>("h028")) @[dec_tlu_ctl.scala 2313:34] - node _T_1993 = bits(_T_1992, 0, 0) @[dec_tlu_ctl.scala 2313:62] - node _T_1994 = eq(mhpme_vec[3], UInt<6>("h029")) @[dec_tlu_ctl.scala 2314:34] - node _T_1995 = bits(_T_1994, 0, 0) @[dec_tlu_ctl.scala 2314:62] - node _T_1996 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2314:97] - node _T_1997 = and(_T_1996, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2314:129] - node _T_1998 = eq(mhpme_vec[3], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2315:34] - node _T_1999 = bits(_T_1998, 0, 0) @[dec_tlu_ctl.scala 2315:62] - node _T_2000 = eq(mhpme_vec[3], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2316:34] - node _T_2001 = bits(_T_2000, 0, 0) @[dec_tlu_ctl.scala 2316:62] - node _T_2002 = eq(mhpme_vec[3], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2317:34] - node _T_2003 = bits(_T_2002, 0, 0) @[dec_tlu_ctl.scala 2317:62] - node _T_2004 = eq(mhpme_vec[3], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2318:34] - node _T_2005 = bits(_T_2004, 0, 0) @[dec_tlu_ctl.scala 2318:62] - node _T_2006 = eq(mhpme_vec[3], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2319:34] - node _T_2007 = bits(_T_2006, 0, 0) @[dec_tlu_ctl.scala 2319:62] - node _T_2008 = eq(mhpme_vec[3], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2320:34] - node _T_2009 = bits(_T_2008, 0, 0) @[dec_tlu_ctl.scala 2320:62] - node _T_2010 = eq(mhpme_vec[3], UInt<6>("h030")) @[dec_tlu_ctl.scala 2321:34] - node _T_2011 = bits(_T_2010, 0, 0) @[dec_tlu_ctl.scala 2321:62] - node _T_2012 = eq(mhpme_vec[3], UInt<6>("h031")) @[dec_tlu_ctl.scala 2322:34] - node _T_2013 = bits(_T_2012, 0, 0) @[dec_tlu_ctl.scala 2322:62] - node _T_2014 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] - node _T_2015 = bits(_T_2014, 0, 0) @[dec_tlu_ctl.scala 2322:84] - node _T_2016 = not(_T_2015) @[dec_tlu_ctl.scala 2322:73] - node _T_2017 = eq(mhpme_vec[3], UInt<6>("h032")) @[dec_tlu_ctl.scala 2323:34] - node _T_2018 = bits(_T_2017, 0, 0) @[dec_tlu_ctl.scala 2323:62] - node _T_2019 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2323:84] - node _T_2020 = bits(_T_2019, 0, 0) @[dec_tlu_ctl.scala 2323:84] - node _T_2021 = not(_T_2020) @[dec_tlu_ctl.scala 2323:73] - node _T_2022 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2323:107] - node _T_2023 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2323:118] - node _T_2024 = and(_T_2022, _T_2023) @[dec_tlu_ctl.scala 2323:113] - node _T_2025 = orr(_T_2024) @[dec_tlu_ctl.scala 2323:125] - node _T_2026 = and(_T_2021, _T_2025) @[dec_tlu_ctl.scala 2323:98] - node _T_2027 = eq(mhpme_vec[3], UInt<6>("h036")) @[dec_tlu_ctl.scala 2324:34] - node _T_2028 = bits(_T_2027, 0, 0) @[dec_tlu_ctl.scala 2324:62] - node _T_2029 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2324:91] - node _T_2030 = eq(mhpme_vec[3], UInt<6>("h037")) @[dec_tlu_ctl.scala 2325:34] - node _T_2031 = bits(_T_2030, 0, 0) @[dec_tlu_ctl.scala 2325:62] - node _T_2032 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2325:94] - node _T_2033 = eq(mhpme_vec[3], UInt<6>("h038")) @[dec_tlu_ctl.scala 2326:34] - node _T_2034 = bits(_T_2033, 0, 0) @[dec_tlu_ctl.scala 2326:62] - node _T_2035 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2326:94] - node _T_2036 = eq(mhpme_vec[3], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2328:34] - node _T_2037 = bits(_T_2036, 0, 0) @[dec_tlu_ctl.scala 2328:62] - node _T_2038 = eq(mhpme_vec[3], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2329:34] - node _T_2039 = bits(_T_2038, 0, 0) @[dec_tlu_ctl.scala 2329:62] - node _T_2040 = eq(mhpme_vec[3], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2330:34] - node _T_2041 = bits(_T_2040, 0, 0) @[dec_tlu_ctl.scala 2330:62] - node _T_2042 = eq(mhpme_vec[3], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2331:34] - node _T_2043 = bits(_T_2042, 0, 0) @[dec_tlu_ctl.scala 2331:62] - node _T_2044 = eq(mhpme_vec[3], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2332:34] - node _T_2045 = bits(_T_2044, 0, 0) @[dec_tlu_ctl.scala 2332:62] - node _T_2046 = mux(_T_1880, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2047 = mux(_T_1882, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2048 = mux(_T_1884, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2049 = mux(_T_1886, _T_1888, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2050 = mux(_T_1890, _T_1894, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2051 = mux(_T_1896, _T_1899, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2052 = mux(_T_1901, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2053 = mux(_T_1903, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2054 = mux(_T_1905, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2055 = mux(_T_1907, _T_1908, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2056 = mux(_T_1910, _T_1911, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2057 = mux(_T_1913, _T_1914, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2058 = mux(_T_1916, _T_1917, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2059 = mux(_T_1919, _T_1921, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2060 = mux(_T_1923, _T_1926, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2061 = mux(_T_1928, _T_1929, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2062 = mux(_T_1931, _T_1932, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2063 = mux(_T_1934, _T_1935, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2064 = mux(_T_1937, _T_1938, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2065 = mux(_T_1940, _T_1941, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2066 = mux(_T_1943, _T_1944, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2067 = mux(_T_1946, _T_1947, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2068 = mux(_T_1949, _T_1950, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2069 = mux(_T_1952, _T_1953, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2070 = mux(_T_1955, _T_1958, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2071 = mux(_T_1960, _T_1961, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2072 = mux(_T_1963, _T_1964, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2073 = mux(_T_1966, _T_1967, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2074 = mux(_T_1969, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2075 = mux(_T_1971, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2076 = mux(_T_1973, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2077 = mux(_T_1975, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2078 = mux(_T_1977, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2079 = mux(_T_1979, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2080 = mux(_T_1981, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2081 = mux(_T_1983, _T_1985, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2082 = mux(_T_1987, _T_1989, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2083 = mux(_T_1991, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2084 = mux(_T_1993, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2085 = mux(_T_1995, _T_1997, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2086 = mux(_T_1999, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2087 = mux(_T_2001, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2088 = mux(_T_2003, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2089 = mux(_T_2005, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2090 = mux(_T_2007, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2091 = mux(_T_2009, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2092 = mux(_T_2011, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2093 = mux(_T_2013, _T_2016, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2094 = mux(_T_2018, _T_2026, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2095 = mux(_T_2028, _T_2029, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2096 = mux(_T_2031, _T_2032, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2097 = mux(_T_2034, _T_2035, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2098 = mux(_T_2037, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2099 = mux(_T_2039, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2100 = mux(_T_2041, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2101 = mux(_T_2043, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2102 = mux(_T_2045, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2103 = or(_T_2046, _T_2047) @[Mux.scala 27:72] + wire _T_1865 : UInt<1> @[Mux.scala 27:72] + _T_1865 <= _T_1864 @[Mux.scala 27:72] + node _T_1866 = and(_T_1584, _T_1865) @[dec_tlu_ctl.scala 2274:44] + mhpmc_inc_r[2] <= _T_1866 @[dec_tlu_ctl.scala 2274:19] + node _T_1867 = bits(mcountinhibit, 6, 6) @[dec_tlu_ctl.scala 2274:38] + node _T_1868 = not(_T_1867) @[dec_tlu_ctl.scala 2274:24] + node _T_1869 = eq(mhpme_vec[3], UInt<1>("h01")) @[dec_tlu_ctl.scala 2275:34] + node _T_1870 = bits(_T_1869, 0, 0) @[dec_tlu_ctl.scala 2275:62] + node _T_1871 = eq(mhpme_vec[3], UInt<2>("h02")) @[dec_tlu_ctl.scala 2276:34] + node _T_1872 = bits(_T_1871, 0, 0) @[dec_tlu_ctl.scala 2276:62] + node _T_1873 = eq(mhpme_vec[3], UInt<2>("h03")) @[dec_tlu_ctl.scala 2277:34] + node _T_1874 = bits(_T_1873, 0, 0) @[dec_tlu_ctl.scala 2277:62] + node _T_1875 = eq(mhpme_vec[3], UInt<3>("h04")) @[dec_tlu_ctl.scala 2278:34] + node _T_1876 = bits(_T_1875, 0, 0) @[dec_tlu_ctl.scala 2278:62] + node _T_1877 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:96] + node _T_1878 = and(io.tlu_i0_commit_cmt, _T_1877) @[dec_tlu_ctl.scala 2278:94] + node _T_1879 = eq(mhpme_vec[3], UInt<3>("h05")) @[dec_tlu_ctl.scala 2279:34] + node _T_1880 = bits(_T_1879, 0, 0) @[dec_tlu_ctl.scala 2279:62] + node _T_1881 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:96] + node _T_1882 = and(io.tlu_i0_commit_cmt, _T_1881) @[dec_tlu_ctl.scala 2279:94] + node _T_1883 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] + node _T_1884 = and(_T_1882, _T_1883) @[dec_tlu_ctl.scala 2279:115] + node _T_1885 = eq(mhpme_vec[3], UInt<3>("h06")) @[dec_tlu_ctl.scala 2280:34] + node _T_1886 = bits(_T_1885, 0, 0) @[dec_tlu_ctl.scala 2280:62] + node _T_1887 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2280:94] + node _T_1888 = not(io.illegal_r) @[dec_tlu_ctl.scala 2280:117] + node _T_1889 = and(_T_1887, _T_1888) @[dec_tlu_ctl.scala 2280:115] + node _T_1890 = eq(mhpme_vec[3], UInt<3>("h07")) @[dec_tlu_ctl.scala 2281:34] + node _T_1891 = bits(_T_1890, 0, 0) @[dec_tlu_ctl.scala 2281:62] + node _T_1892 = eq(mhpme_vec[3], UInt<4>("h08")) @[dec_tlu_ctl.scala 2282:34] + node _T_1893 = bits(_T_1892, 0, 0) @[dec_tlu_ctl.scala 2282:62] + node _T_1894 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2283:34] + node _T_1895 = bits(_T_1894, 0, 0) @[dec_tlu_ctl.scala 2283:62] + node _T_1896 = eq(mhpme_vec[3], UInt<4>("h09")) @[dec_tlu_ctl.scala 2284:34] + node _T_1897 = bits(_T_1896, 0, 0) @[dec_tlu_ctl.scala 2284:62] + node _T_1898 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2284:91] + node _T_1899 = eq(mhpme_vec[3], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2285:34] + node _T_1900 = bits(_T_1899, 0, 0) @[dec_tlu_ctl.scala 2285:62] + node _T_1901 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2285:105] + node _T_1902 = eq(mhpme_vec[3], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2286:34] + node _T_1903 = bits(_T_1902, 0, 0) @[dec_tlu_ctl.scala 2286:62] + node _T_1904 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2286:91] + node _T_1905 = eq(mhpme_vec[3], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2287:34] + node _T_1906 = bits(_T_1905, 0, 0) @[dec_tlu_ctl.scala 2287:62] + node _T_1907 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2287:91] + node _T_1908 = eq(mhpme_vec[3], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2288:34] + node _T_1909 = bits(_T_1908, 0, 0) @[dec_tlu_ctl.scala 2288:62] + node _T_1910 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2288:91] + node _T_1911 = and(_T_1910, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2288:100] + node _T_1912 = eq(mhpme_vec[3], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2289:34] + node _T_1913 = bits(_T_1912, 0, 0) @[dec_tlu_ctl.scala 2289:62] + node _T_1914 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2289:91] + node _T_1915 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2289:142] + node _T_1916 = and(_T_1914, _T_1915) @[dec_tlu_ctl.scala 2289:101] + node _T_1917 = eq(mhpme_vec[3], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2290:34] + node _T_1918 = bits(_T_1917, 0, 0) @[dec_tlu_ctl.scala 2290:59] + node _T_1919 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2290:89] + node _T_1920 = eq(mhpme_vec[3], UInt<5>("h010")) @[dec_tlu_ctl.scala 2291:34] + node _T_1921 = bits(_T_1920, 0, 0) @[dec_tlu_ctl.scala 2291:59] + node _T_1922 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2291:89] + node _T_1923 = eq(mhpme_vec[3], UInt<5>("h012")) @[dec_tlu_ctl.scala 2292:34] + node _T_1924 = bits(_T_1923, 0, 0) @[dec_tlu_ctl.scala 2292:59] + node _T_1925 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2292:89] + node _T_1926 = eq(mhpme_vec[3], UInt<5>("h011")) @[dec_tlu_ctl.scala 2293:34] + node _T_1927 = bits(_T_1926, 0, 0) @[dec_tlu_ctl.scala 2293:59] + node _T_1928 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2293:89] + node _T_1929 = eq(mhpme_vec[3], UInt<5>("h013")) @[dec_tlu_ctl.scala 2294:34] + node _T_1930 = bits(_T_1929, 0, 0) @[dec_tlu_ctl.scala 2294:59] + node _T_1931 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2294:89] + node _T_1932 = eq(mhpme_vec[3], UInt<5>("h014")) @[dec_tlu_ctl.scala 2295:34] + node _T_1933 = bits(_T_1932, 0, 0) @[dec_tlu_ctl.scala 2295:59] + node _T_1934 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2295:89] + node _T_1935 = eq(mhpme_vec[3], UInt<5>("h015")) @[dec_tlu_ctl.scala 2296:34] + node _T_1936 = bits(_T_1935, 0, 0) @[dec_tlu_ctl.scala 2296:59] + node _T_1937 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2296:89] + node _T_1938 = eq(mhpme_vec[3], UInt<5>("h016")) @[dec_tlu_ctl.scala 2297:34] + node _T_1939 = bits(_T_1938, 0, 0) @[dec_tlu_ctl.scala 2297:59] + node _T_1940 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2297:89] + node _T_1941 = eq(mhpme_vec[3], UInt<5>("h017")) @[dec_tlu_ctl.scala 2298:34] + node _T_1942 = bits(_T_1941, 0, 0) @[dec_tlu_ctl.scala 2298:59] + node _T_1943 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2298:89] + node _T_1944 = eq(mhpme_vec[3], UInt<5>("h018")) @[dec_tlu_ctl.scala 2299:34] + node _T_1945 = bits(_T_1944, 0, 0) @[dec_tlu_ctl.scala 2299:59] + node _T_1946 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2299:89] + node _T_1947 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2299:122] + node _T_1948 = or(_T_1946, _T_1947) @[dec_tlu_ctl.scala 2299:101] + node _T_1949 = eq(mhpme_vec[3], UInt<5>("h019")) @[dec_tlu_ctl.scala 2300:34] + node _T_1950 = bits(_T_1949, 0, 0) @[dec_tlu_ctl.scala 2300:62] + node _T_1951 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:95] + node _T_1952 = eq(mhpme_vec[3], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2301:34] + node _T_1953 = bits(_T_1952, 0, 0) @[dec_tlu_ctl.scala 2301:62] + node _T_1954 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:97] + node _T_1955 = eq(mhpme_vec[3], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2302:34] + node _T_1956 = bits(_T_1955, 0, 0) @[dec_tlu_ctl.scala 2302:62] + node _T_1957 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2302:110] + node _T_1958 = eq(mhpme_vec[3], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2303:34] + node _T_1959 = bits(_T_1958, 0, 0) @[dec_tlu_ctl.scala 2303:62] + node _T_1960 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2304:34] + node _T_1961 = bits(_T_1960, 0, 0) @[dec_tlu_ctl.scala 2304:62] + node _T_1962 = eq(mhpme_vec[3], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2305:34] + node _T_1963 = bits(_T_1962, 0, 0) @[dec_tlu_ctl.scala 2305:62] + node _T_1964 = eq(mhpme_vec[3], UInt<6>("h020")) @[dec_tlu_ctl.scala 2306:34] + node _T_1965 = bits(_T_1964, 0, 0) @[dec_tlu_ctl.scala 2306:62] + node _T_1966 = eq(mhpme_vec[3], UInt<6>("h022")) @[dec_tlu_ctl.scala 2307:34] + node _T_1967 = bits(_T_1966, 0, 0) @[dec_tlu_ctl.scala 2307:62] + node _T_1968 = eq(mhpme_vec[3], UInt<6>("h023")) @[dec_tlu_ctl.scala 2308:34] + node _T_1969 = bits(_T_1968, 0, 0) @[dec_tlu_ctl.scala 2308:62] + node _T_1970 = eq(mhpme_vec[3], UInt<6>("h024")) @[dec_tlu_ctl.scala 2309:34] + node _T_1971 = bits(_T_1970, 0, 0) @[dec_tlu_ctl.scala 2309:62] + node _T_1972 = eq(mhpme_vec[3], UInt<6>("h025")) @[dec_tlu_ctl.scala 2310:34] + node _T_1973 = bits(_T_1972, 0, 0) @[dec_tlu_ctl.scala 2310:62] + node _T_1974 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2310:98] + node _T_1975 = or(_T_1974, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2310:120] + node _T_1976 = eq(mhpme_vec[3], UInt<6>("h026")) @[dec_tlu_ctl.scala 2311:34] + node _T_1977 = bits(_T_1976, 0, 0) @[dec_tlu_ctl.scala 2311:62] + node _T_1978 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2311:92] + node _T_1979 = or(_T_1978, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2311:117] + node _T_1980 = eq(mhpme_vec[3], UInt<6>("h027")) @[dec_tlu_ctl.scala 2312:34] + node _T_1981 = bits(_T_1980, 0, 0) @[dec_tlu_ctl.scala 2312:62] + node _T_1982 = eq(mhpme_vec[3], UInt<6>("h028")) @[dec_tlu_ctl.scala 2313:34] + node _T_1983 = bits(_T_1982, 0, 0) @[dec_tlu_ctl.scala 2313:62] + node _T_1984 = eq(mhpme_vec[3], UInt<6>("h029")) @[dec_tlu_ctl.scala 2314:34] + node _T_1985 = bits(_T_1984, 0, 0) @[dec_tlu_ctl.scala 2314:62] + node _T_1986 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2314:97] + node _T_1987 = and(_T_1986, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2314:129] + node _T_1988 = eq(mhpme_vec[3], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2315:34] + node _T_1989 = bits(_T_1988, 0, 0) @[dec_tlu_ctl.scala 2315:62] + node _T_1990 = eq(mhpme_vec[3], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2316:34] + node _T_1991 = bits(_T_1990, 0, 0) @[dec_tlu_ctl.scala 2316:62] + node _T_1992 = eq(mhpme_vec[3], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2317:34] + node _T_1993 = bits(_T_1992, 0, 0) @[dec_tlu_ctl.scala 2317:62] + node _T_1994 = eq(mhpme_vec[3], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2318:34] + node _T_1995 = bits(_T_1994, 0, 0) @[dec_tlu_ctl.scala 2318:62] + node _T_1996 = eq(mhpme_vec[3], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2319:34] + node _T_1997 = bits(_T_1996, 0, 0) @[dec_tlu_ctl.scala 2319:62] + node _T_1998 = eq(mhpme_vec[3], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2320:34] + node _T_1999 = bits(_T_1998, 0, 0) @[dec_tlu_ctl.scala 2320:62] + node _T_2000 = eq(mhpme_vec[3], UInt<6>("h030")) @[dec_tlu_ctl.scala 2321:34] + node _T_2001 = bits(_T_2000, 0, 0) @[dec_tlu_ctl.scala 2321:62] + node _T_2002 = eq(mhpme_vec[3], UInt<6>("h031")) @[dec_tlu_ctl.scala 2322:34] + node _T_2003 = bits(_T_2002, 0, 0) @[dec_tlu_ctl.scala 2322:62] + node _T_2004 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] + node _T_2005 = bits(_T_2004, 0, 0) @[dec_tlu_ctl.scala 2322:84] + node _T_2006 = not(_T_2005) @[dec_tlu_ctl.scala 2322:73] + node _T_2007 = eq(mhpme_vec[3], UInt<6>("h032")) @[dec_tlu_ctl.scala 2323:34] + node _T_2008 = bits(_T_2007, 0, 0) @[dec_tlu_ctl.scala 2323:62] + node _T_2009 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2323:84] + node _T_2010 = bits(_T_2009, 0, 0) @[dec_tlu_ctl.scala 2323:84] + node _T_2011 = not(_T_2010) @[dec_tlu_ctl.scala 2323:73] + node _T_2012 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2323:107] + node _T_2013 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2323:118] + node _T_2014 = and(_T_2012, _T_2013) @[dec_tlu_ctl.scala 2323:113] + node _T_2015 = orr(_T_2014) @[dec_tlu_ctl.scala 2323:125] + node _T_2016 = and(_T_2011, _T_2015) @[dec_tlu_ctl.scala 2323:98] + node _T_2017 = eq(mhpme_vec[3], UInt<6>("h036")) @[dec_tlu_ctl.scala 2324:34] + node _T_2018 = bits(_T_2017, 0, 0) @[dec_tlu_ctl.scala 2324:62] + node _T_2019 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2324:91] + node _T_2020 = eq(mhpme_vec[3], UInt<6>("h037")) @[dec_tlu_ctl.scala 2325:34] + node _T_2021 = bits(_T_2020, 0, 0) @[dec_tlu_ctl.scala 2325:62] + node _T_2022 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2325:94] + node _T_2023 = eq(mhpme_vec[3], UInt<6>("h038")) @[dec_tlu_ctl.scala 2326:34] + node _T_2024 = bits(_T_2023, 0, 0) @[dec_tlu_ctl.scala 2326:62] + node _T_2025 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2326:94] + node _T_2026 = eq(mhpme_vec[3], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2328:34] + node _T_2027 = bits(_T_2026, 0, 0) @[dec_tlu_ctl.scala 2328:62] + node _T_2028 = eq(mhpme_vec[3], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2329:34] + node _T_2029 = bits(_T_2028, 0, 0) @[dec_tlu_ctl.scala 2329:62] + node _T_2030 = eq(mhpme_vec[3], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2330:34] + node _T_2031 = bits(_T_2030, 0, 0) @[dec_tlu_ctl.scala 2330:62] + node _T_2032 = eq(mhpme_vec[3], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2331:34] + node _T_2033 = bits(_T_2032, 0, 0) @[dec_tlu_ctl.scala 2331:62] + node _T_2034 = eq(mhpme_vec[3], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2332:34] + node _T_2035 = bits(_T_2034, 0, 0) @[dec_tlu_ctl.scala 2332:62] + node _T_2036 = mux(_T_1870, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2037 = mux(_T_1872, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2038 = mux(_T_1874, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2039 = mux(_T_1876, _T_1878, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2040 = mux(_T_1880, _T_1884, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2041 = mux(_T_1886, _T_1889, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2042 = mux(_T_1891, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2043 = mux(_T_1893, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2044 = mux(_T_1895, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2045 = mux(_T_1897, _T_1898, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2046 = mux(_T_1900, _T_1901, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2047 = mux(_T_1903, _T_1904, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2048 = mux(_T_1906, _T_1907, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2049 = mux(_T_1909, _T_1911, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2050 = mux(_T_1913, _T_1916, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2051 = mux(_T_1918, _T_1919, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2052 = mux(_T_1921, _T_1922, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2053 = mux(_T_1924, _T_1925, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2054 = mux(_T_1927, _T_1928, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2055 = mux(_T_1930, _T_1931, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2056 = mux(_T_1933, _T_1934, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2057 = mux(_T_1936, _T_1937, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2058 = mux(_T_1939, _T_1940, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2059 = mux(_T_1942, _T_1943, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2060 = mux(_T_1945, _T_1948, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2061 = mux(_T_1950, _T_1951, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2062 = mux(_T_1953, _T_1954, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2063 = mux(_T_1956, _T_1957, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2064 = mux(_T_1959, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2065 = mux(_T_1961, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2066 = mux(_T_1963, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2067 = mux(_T_1965, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2068 = mux(_T_1967, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2069 = mux(_T_1969, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2070 = mux(_T_1971, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2071 = mux(_T_1973, _T_1975, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2072 = mux(_T_1977, _T_1979, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2073 = mux(_T_1981, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2074 = mux(_T_1983, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2075 = mux(_T_1985, _T_1987, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2076 = mux(_T_1989, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2077 = mux(_T_1991, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2078 = mux(_T_1993, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2079 = mux(_T_1995, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2080 = mux(_T_1997, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2081 = mux(_T_1999, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2082 = mux(_T_2001, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2083 = mux(_T_2003, _T_2006, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2084 = mux(_T_2008, _T_2016, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2085 = mux(_T_2018, _T_2019, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2086 = mux(_T_2021, _T_2022, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2087 = mux(_T_2024, _T_2025, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2088 = mux(_T_2027, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2089 = mux(_T_2029, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2090 = mux(_T_2031, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2091 = mux(_T_2033, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2092 = mux(_T_2035, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2093 = or(_T_2036, _T_2037) @[Mux.scala 27:72] + node _T_2094 = or(_T_2093, _T_2038) @[Mux.scala 27:72] + node _T_2095 = or(_T_2094, _T_2039) @[Mux.scala 27:72] + node _T_2096 = or(_T_2095, _T_2040) @[Mux.scala 27:72] + node _T_2097 = or(_T_2096, _T_2041) @[Mux.scala 27:72] + node _T_2098 = or(_T_2097, _T_2042) @[Mux.scala 27:72] + node _T_2099 = or(_T_2098, _T_2043) @[Mux.scala 27:72] + node _T_2100 = or(_T_2099, _T_2044) @[Mux.scala 27:72] + node _T_2101 = or(_T_2100, _T_2045) @[Mux.scala 27:72] + node _T_2102 = or(_T_2101, _T_2046) @[Mux.scala 27:72] + node _T_2103 = or(_T_2102, _T_2047) @[Mux.scala 27:72] node _T_2104 = or(_T_2103, _T_2048) @[Mux.scala 27:72] node _T_2105 = or(_T_2104, _T_2049) @[Mux.scala 27:72] node _T_2106 = or(_T_2105, _T_2050) @[Mux.scala 27:72] @@ -75544,585 +75544,585 @@ circuit quasar_wrapper : node _T_2146 = or(_T_2145, _T_2090) @[Mux.scala 27:72] node _T_2147 = or(_T_2146, _T_2091) @[Mux.scala 27:72] node _T_2148 = or(_T_2147, _T_2092) @[Mux.scala 27:72] - node _T_2149 = or(_T_2148, _T_2093) @[Mux.scala 27:72] - node _T_2150 = or(_T_2149, _T_2094) @[Mux.scala 27:72] - node _T_2151 = or(_T_2150, _T_2095) @[Mux.scala 27:72] - node _T_2152 = or(_T_2151, _T_2096) @[Mux.scala 27:72] - node _T_2153 = or(_T_2152, _T_2097) @[Mux.scala 27:72] - node _T_2154 = or(_T_2153, _T_2098) @[Mux.scala 27:72] - node _T_2155 = or(_T_2154, _T_2099) @[Mux.scala 27:72] - node _T_2156 = or(_T_2155, _T_2100) @[Mux.scala 27:72] - node _T_2157 = or(_T_2156, _T_2101) @[Mux.scala 27:72] - node _T_2158 = or(_T_2157, _T_2102) @[Mux.scala 27:72] - wire _T_2159 : UInt<1> @[Mux.scala 27:72] - _T_2159 <= _T_2158 @[Mux.scala 27:72] - node _T_2160 = and(_T_1878, _T_2159) @[dec_tlu_ctl.scala 2274:44] - mhpmc_inc_r[3] <= _T_2160 @[dec_tlu_ctl.scala 2274:19] - reg _T_2161 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2335:53] - _T_2161 <= mhpmc_inc_r[0] @[dec_tlu_ctl.scala 2335:53] - mhpmc_inc_r_d1[0] <= _T_2161 @[dec_tlu_ctl.scala 2335:20] - reg _T_2162 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2336:53] - _T_2162 <= mhpmc_inc_r[1] @[dec_tlu_ctl.scala 2336:53] - mhpmc_inc_r_d1[1] <= _T_2162 @[dec_tlu_ctl.scala 2336:20] - reg _T_2163 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2337:53] - _T_2163 <= mhpmc_inc_r[2] @[dec_tlu_ctl.scala 2337:53] - mhpmc_inc_r_d1[2] <= _T_2163 @[dec_tlu_ctl.scala 2337:20] - reg _T_2164 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2338:53] - _T_2164 <= mhpmc_inc_r[3] @[dec_tlu_ctl.scala 2338:53] - mhpmc_inc_r_d1[3] <= _T_2164 @[dec_tlu_ctl.scala 2338:20] + wire _T_2149 : UInt<1> @[Mux.scala 27:72] + _T_2149 <= _T_2148 @[Mux.scala 27:72] + node _T_2150 = and(_T_1868, _T_2149) @[dec_tlu_ctl.scala 2274:44] + mhpmc_inc_r[3] <= _T_2150 @[dec_tlu_ctl.scala 2274:19] + reg _T_2151 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2335:53] + _T_2151 <= mhpmc_inc_r[0] @[dec_tlu_ctl.scala 2335:53] + mhpmc_inc_r_d1[0] <= _T_2151 @[dec_tlu_ctl.scala 2335:20] + reg _T_2152 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2336:53] + _T_2152 <= mhpmc_inc_r[1] @[dec_tlu_ctl.scala 2336:53] + mhpmc_inc_r_d1[1] <= _T_2152 @[dec_tlu_ctl.scala 2336:20] + reg _T_2153 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2337:53] + _T_2153 <= mhpmc_inc_r[2] @[dec_tlu_ctl.scala 2337:53] + mhpmc_inc_r_d1[2] <= _T_2153 @[dec_tlu_ctl.scala 2337:20] + reg _T_2154 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2338:53] + _T_2154 <= mhpmc_inc_r[3] @[dec_tlu_ctl.scala 2338:53] + mhpmc_inc_r_d1[3] <= _T_2154 @[dec_tlu_ctl.scala 2338:20] reg perfcnt_halted_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2339:56] perfcnt_halted_d1 <= perfcnt_halted @[dec_tlu_ctl.scala 2339:56] - node _T_2165 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2342:53] - node _T_2166 = and(io.dec_tlu_dbg_halted, _T_2165) @[dec_tlu_ctl.scala 2342:44] - node _T_2167 = or(_T_2166, io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2342:67] - perfcnt_halted <= _T_2167 @[dec_tlu_ctl.scala 2342:17] - node _T_2168 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2343:70] - node _T_2169 = and(io.dec_tlu_dbg_halted, _T_2168) @[dec_tlu_ctl.scala 2343:61] - node _T_2170 = not(_T_2169) @[dec_tlu_ctl.scala 2343:37] - node _T_2171 = bits(_T_2170, 0, 0) @[Bitwise.scala 72:15] - node _T_2172 = mux(_T_2171, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_2173 = bits(mhpme_vec[3], 9, 9) @[dec_tlu_ctl.scala 2343:104] - node _T_2174 = bits(mhpme_vec[2], 9, 9) @[dec_tlu_ctl.scala 2343:120] - node _T_2175 = bits(mhpme_vec[1], 9, 9) @[dec_tlu_ctl.scala 2343:136] - node _T_2176 = bits(mhpme_vec[0], 9, 9) @[dec_tlu_ctl.scala 2343:152] - node _T_2177 = cat(_T_2175, _T_2176) @[Cat.scala 29:58] - node _T_2178 = cat(_T_2173, _T_2174) @[Cat.scala 29:58] - node _T_2179 = cat(_T_2178, _T_2177) @[Cat.scala 29:58] - node perfcnt_during_sleep = and(_T_2172, _T_2179) @[dec_tlu_ctl.scala 2343:86] - node _T_2180 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2345:88] - node _T_2181 = not(_T_2180) @[dec_tlu_ctl.scala 2345:67] - node _T_2182 = and(perfcnt_halted_d1, _T_2181) @[dec_tlu_ctl.scala 2345:65] - node _T_2183 = not(_T_2182) @[dec_tlu_ctl.scala 2345:45] - node _T_2184 = and(mhpmc_inc_r_d1[0], _T_2183) @[dec_tlu_ctl.scala 2345:43] - io.dec_tlu_perfcnt0 <= _T_2184 @[dec_tlu_ctl.scala 2345:22] - node _T_2185 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2346:88] - node _T_2186 = not(_T_2185) @[dec_tlu_ctl.scala 2346:67] - node _T_2187 = and(perfcnt_halted_d1, _T_2186) @[dec_tlu_ctl.scala 2346:65] - node _T_2188 = not(_T_2187) @[dec_tlu_ctl.scala 2346:45] - node _T_2189 = and(mhpmc_inc_r_d1[1], _T_2188) @[dec_tlu_ctl.scala 2346:43] - io.dec_tlu_perfcnt1 <= _T_2189 @[dec_tlu_ctl.scala 2346:22] - node _T_2190 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2347:88] - node _T_2191 = not(_T_2190) @[dec_tlu_ctl.scala 2347:67] - node _T_2192 = and(perfcnt_halted_d1, _T_2191) @[dec_tlu_ctl.scala 2347:65] - node _T_2193 = not(_T_2192) @[dec_tlu_ctl.scala 2347:45] - node _T_2194 = and(mhpmc_inc_r_d1[2], _T_2193) @[dec_tlu_ctl.scala 2347:43] - io.dec_tlu_perfcnt2 <= _T_2194 @[dec_tlu_ctl.scala 2347:22] - node _T_2195 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2348:88] - node _T_2196 = not(_T_2195) @[dec_tlu_ctl.scala 2348:67] - node _T_2197 = and(perfcnt_halted_d1, _T_2196) @[dec_tlu_ctl.scala 2348:65] - node _T_2198 = not(_T_2197) @[dec_tlu_ctl.scala 2348:45] - node _T_2199 = and(mhpmc_inc_r_d1[3], _T_2198) @[dec_tlu_ctl.scala 2348:43] - io.dec_tlu_perfcnt3 <= _T_2199 @[dec_tlu_ctl.scala 2348:22] - node _T_2200 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2354:65] - node _T_2201 = eq(_T_2200, UInt<12>("h0b03")) @[dec_tlu_ctl.scala 2354:72] - node mhpmc3_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2201) @[dec_tlu_ctl.scala 2354:43] - node _T_2202 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2355:23] - node _T_2203 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2355:61] - node _T_2204 = or(_T_2202, _T_2203) @[dec_tlu_ctl.scala 2355:39] - node _T_2205 = orr(mhpmc_inc_r[0]) @[dec_tlu_ctl.scala 2355:86] - node mhpmc3_wr_en1 = and(_T_2204, _T_2205) @[dec_tlu_ctl.scala 2355:66] + node _T_2155 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2342:53] + node _T_2156 = and(io.dec_tlu_dbg_halted, _T_2155) @[dec_tlu_ctl.scala 2342:44] + node _T_2157 = or(_T_2156, io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2342:67] + perfcnt_halted <= _T_2157 @[dec_tlu_ctl.scala 2342:17] + node _T_2158 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2343:70] + node _T_2159 = and(io.dec_tlu_dbg_halted, _T_2158) @[dec_tlu_ctl.scala 2343:61] + node _T_2160 = not(_T_2159) @[dec_tlu_ctl.scala 2343:37] + node _T_2161 = bits(_T_2160, 0, 0) @[Bitwise.scala 72:15] + node _T_2162 = mux(_T_2161, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_2163 = bits(mhpme_vec[3], 9, 9) @[dec_tlu_ctl.scala 2343:104] + node _T_2164 = bits(mhpme_vec[2], 9, 9) @[dec_tlu_ctl.scala 2343:120] + node _T_2165 = bits(mhpme_vec[1], 9, 9) @[dec_tlu_ctl.scala 2343:136] + node _T_2166 = bits(mhpme_vec[0], 9, 9) @[dec_tlu_ctl.scala 2343:152] + node _T_2167 = cat(_T_2165, _T_2166) @[Cat.scala 29:58] + node _T_2168 = cat(_T_2163, _T_2164) @[Cat.scala 29:58] + node _T_2169 = cat(_T_2168, _T_2167) @[Cat.scala 29:58] + node perfcnt_during_sleep = and(_T_2162, _T_2169) @[dec_tlu_ctl.scala 2343:86] + node _T_2170 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2345:88] + node _T_2171 = not(_T_2170) @[dec_tlu_ctl.scala 2345:67] + node _T_2172 = and(perfcnt_halted_d1, _T_2171) @[dec_tlu_ctl.scala 2345:65] + node _T_2173 = not(_T_2172) @[dec_tlu_ctl.scala 2345:45] + node _T_2174 = and(mhpmc_inc_r_d1[0], _T_2173) @[dec_tlu_ctl.scala 2345:43] + io.dec_tlu_perfcnt0 <= _T_2174 @[dec_tlu_ctl.scala 2345:22] + node _T_2175 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2346:88] + node _T_2176 = not(_T_2175) @[dec_tlu_ctl.scala 2346:67] + node _T_2177 = and(perfcnt_halted_d1, _T_2176) @[dec_tlu_ctl.scala 2346:65] + node _T_2178 = not(_T_2177) @[dec_tlu_ctl.scala 2346:45] + node _T_2179 = and(mhpmc_inc_r_d1[1], _T_2178) @[dec_tlu_ctl.scala 2346:43] + io.dec_tlu_perfcnt1 <= _T_2179 @[dec_tlu_ctl.scala 2346:22] + node _T_2180 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2347:88] + node _T_2181 = not(_T_2180) @[dec_tlu_ctl.scala 2347:67] + node _T_2182 = and(perfcnt_halted_d1, _T_2181) @[dec_tlu_ctl.scala 2347:65] + node _T_2183 = not(_T_2182) @[dec_tlu_ctl.scala 2347:45] + node _T_2184 = and(mhpmc_inc_r_d1[2], _T_2183) @[dec_tlu_ctl.scala 2347:43] + io.dec_tlu_perfcnt2 <= _T_2184 @[dec_tlu_ctl.scala 2347:22] + node _T_2185 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2348:88] + node _T_2186 = not(_T_2185) @[dec_tlu_ctl.scala 2348:67] + node _T_2187 = and(perfcnt_halted_d1, _T_2186) @[dec_tlu_ctl.scala 2348:65] + node _T_2188 = not(_T_2187) @[dec_tlu_ctl.scala 2348:45] + node _T_2189 = and(mhpmc_inc_r_d1[3], _T_2188) @[dec_tlu_ctl.scala 2348:43] + io.dec_tlu_perfcnt3 <= _T_2189 @[dec_tlu_ctl.scala 2348:22] + node _T_2190 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2354:65] + node _T_2191 = eq(_T_2190, UInt<12>("h0b03")) @[dec_tlu_ctl.scala 2354:72] + node mhpmc3_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2191) @[dec_tlu_ctl.scala 2354:43] + node _T_2192 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2355:23] + node _T_2193 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2355:61] + node _T_2194 = or(_T_2192, _T_2193) @[dec_tlu_ctl.scala 2355:39] + node _T_2195 = orr(mhpmc_inc_r[0]) @[dec_tlu_ctl.scala 2355:86] + node mhpmc3_wr_en1 = and(_T_2194, _T_2195) @[dec_tlu_ctl.scala 2355:66] node mhpmc3_wr_en = or(mhpmc3_wr_en0, mhpmc3_wr_en1) @[dec_tlu_ctl.scala 2356:36] - node _T_2206 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2359:28] - node _T_2207 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2359:41] - node _T_2208 = cat(_T_2206, _T_2207) @[Cat.scala 29:58] - node _T_2209 = cat(UInt<63>("h00"), mhpmc_inc_r[0]) @[Cat.scala 29:58] - node _T_2210 = add(_T_2208, _T_2209) @[dec_tlu_ctl.scala 2359:49] - node _T_2211 = tail(_T_2210, 1) @[dec_tlu_ctl.scala 2359:49] - mhpmc3_incr <= _T_2211 @[dec_tlu_ctl.scala 2359:14] - node _T_2212 = bits(mhpmc3_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2360:36] - node _T_2213 = bits(mhpmc3_incr, 31, 0) @[dec_tlu_ctl.scala 2360:76] - node mhpmc3_ns = mux(_T_2212, io.dec_csr_wrdata_r, _T_2213) @[dec_tlu_ctl.scala 2360:21] - node _T_2214 = bits(mhpmc3_wr_en, 0, 0) @[dec_tlu_ctl.scala 2362:42] + node _T_2196 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2359:28] + node _T_2197 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2359:41] + node _T_2198 = cat(_T_2196, _T_2197) @[Cat.scala 29:58] + node _T_2199 = cat(UInt<63>("h00"), mhpmc_inc_r[0]) @[Cat.scala 29:58] + node _T_2200 = add(_T_2198, _T_2199) @[dec_tlu_ctl.scala 2359:49] + node _T_2201 = tail(_T_2200, 1) @[dec_tlu_ctl.scala 2359:49] + mhpmc3_incr <= _T_2201 @[dec_tlu_ctl.scala 2359:14] + node _T_2202 = bits(mhpmc3_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2360:36] + node _T_2203 = bits(mhpmc3_incr, 31, 0) @[dec_tlu_ctl.scala 2360:76] + node mhpmc3_ns = mux(_T_2202, io.dec_csr_wrdata_r, _T_2203) @[dec_tlu_ctl.scala 2360:21] + node _T_2204 = bits(mhpmc3_wr_en, 0, 0) @[dec_tlu_ctl.scala 2362:42] inst rvclkhdr_26 of rvclkhdr_746 @[lib.scala 368:23] rvclkhdr_26.clock <= clock rvclkhdr_26.reset <= reset rvclkhdr_26.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_26.io.en <= _T_2214 @[lib.scala 371:17] + rvclkhdr_26.io.en <= _T_2204 @[lib.scala 371:17] rvclkhdr_26.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2215 : UInt, rvclkhdr_26.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2215 <= mhpmc3_ns @[lib.scala 374:16] - mhpmc3 <= _T_2215 @[dec_tlu_ctl.scala 2362:9] - node _T_2216 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2364:66] - node _T_2217 = eq(_T_2216, UInt<12>("h0b83")) @[dec_tlu_ctl.scala 2364:73] - node mhpmc3h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2217) @[dec_tlu_ctl.scala 2364:44] + reg _T_2205 : UInt, rvclkhdr_26.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2205 <= mhpmc3_ns @[lib.scala 374:16] + mhpmc3 <= _T_2205 @[dec_tlu_ctl.scala 2362:9] + node _T_2206 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2364:66] + node _T_2207 = eq(_T_2206, UInt<12>("h0b83")) @[dec_tlu_ctl.scala 2364:73] + node mhpmc3h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2207) @[dec_tlu_ctl.scala 2364:44] node mhpmc3h_wr_en = or(mhpmc3h_wr_en0, mhpmc3_wr_en1) @[dec_tlu_ctl.scala 2365:38] - node _T_2218 = bits(mhpmc3h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2366:38] - node _T_2219 = bits(mhpmc3_incr, 63, 32) @[dec_tlu_ctl.scala 2366:78] - node mhpmc3h_ns = mux(_T_2218, io.dec_csr_wrdata_r, _T_2219) @[dec_tlu_ctl.scala 2366:22] - node _T_2220 = bits(mhpmc3h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2368:46] + node _T_2208 = bits(mhpmc3h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2366:38] + node _T_2209 = bits(mhpmc3_incr, 63, 32) @[dec_tlu_ctl.scala 2366:78] + node mhpmc3h_ns = mux(_T_2208, io.dec_csr_wrdata_r, _T_2209) @[dec_tlu_ctl.scala 2366:22] + node _T_2210 = bits(mhpmc3h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2368:46] inst rvclkhdr_27 of rvclkhdr_747 @[lib.scala 368:23] rvclkhdr_27.clock <= clock rvclkhdr_27.reset <= reset rvclkhdr_27.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_27.io.en <= _T_2220 @[lib.scala 371:17] + rvclkhdr_27.io.en <= _T_2210 @[lib.scala 371:17] rvclkhdr_27.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2221 : UInt, rvclkhdr_27.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2221 <= mhpmc3h_ns @[lib.scala 374:16] - mhpmc3h <= _T_2221 @[dec_tlu_ctl.scala 2368:10] - node _T_2222 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2373:65] - node _T_2223 = eq(_T_2222, UInt<12>("h0b04")) @[dec_tlu_ctl.scala 2373:72] - node mhpmc4_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2223) @[dec_tlu_ctl.scala 2373:43] - node _T_2224 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2374:23] - node _T_2225 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2374:61] - node _T_2226 = or(_T_2224, _T_2225) @[dec_tlu_ctl.scala 2374:39] - node _T_2227 = orr(mhpmc_inc_r[1]) @[dec_tlu_ctl.scala 2374:86] - node mhpmc4_wr_en1 = and(_T_2226, _T_2227) @[dec_tlu_ctl.scala 2374:66] + reg _T_2211 : UInt, rvclkhdr_27.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2211 <= mhpmc3h_ns @[lib.scala 374:16] + mhpmc3h <= _T_2211 @[dec_tlu_ctl.scala 2368:10] + node _T_2212 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2373:65] + node _T_2213 = eq(_T_2212, UInt<12>("h0b04")) @[dec_tlu_ctl.scala 2373:72] + node mhpmc4_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2213) @[dec_tlu_ctl.scala 2373:43] + node _T_2214 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2374:23] + node _T_2215 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2374:61] + node _T_2216 = or(_T_2214, _T_2215) @[dec_tlu_ctl.scala 2374:39] + node _T_2217 = orr(mhpmc_inc_r[1]) @[dec_tlu_ctl.scala 2374:86] + node mhpmc4_wr_en1 = and(_T_2216, _T_2217) @[dec_tlu_ctl.scala 2374:66] node mhpmc4_wr_en = or(mhpmc4_wr_en0, mhpmc4_wr_en1) @[dec_tlu_ctl.scala 2375:36] - node _T_2228 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2379:28] - node _T_2229 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2379:41] - node _T_2230 = cat(_T_2228, _T_2229) @[Cat.scala 29:58] - node _T_2231 = cat(UInt<63>("h00"), mhpmc_inc_r[1]) @[Cat.scala 29:58] - node _T_2232 = add(_T_2230, _T_2231) @[dec_tlu_ctl.scala 2379:49] - node _T_2233 = tail(_T_2232, 1) @[dec_tlu_ctl.scala 2379:49] - mhpmc4_incr <= _T_2233 @[dec_tlu_ctl.scala 2379:14] - node _T_2234 = bits(mhpmc4_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2380:36] - node _T_2235 = bits(io.dec_csr_wrdata_r, 31, 0) @[dec_tlu_ctl.scala 2380:63] - node _T_2236 = bits(mhpmc4_incr, 31, 0) @[dec_tlu_ctl.scala 2380:82] - node mhpmc4_ns = mux(_T_2234, _T_2235, _T_2236) @[dec_tlu_ctl.scala 2380:21] - node _T_2237 = bits(mhpmc4_wr_en, 0, 0) @[dec_tlu_ctl.scala 2381:43] + node _T_2218 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2379:28] + node _T_2219 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2379:41] + node _T_2220 = cat(_T_2218, _T_2219) @[Cat.scala 29:58] + node _T_2221 = cat(UInt<63>("h00"), mhpmc_inc_r[1]) @[Cat.scala 29:58] + node _T_2222 = add(_T_2220, _T_2221) @[dec_tlu_ctl.scala 2379:49] + node _T_2223 = tail(_T_2222, 1) @[dec_tlu_ctl.scala 2379:49] + mhpmc4_incr <= _T_2223 @[dec_tlu_ctl.scala 2379:14] + node _T_2224 = bits(mhpmc4_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2380:36] + node _T_2225 = bits(io.dec_csr_wrdata_r, 31, 0) @[dec_tlu_ctl.scala 2380:63] + node _T_2226 = bits(mhpmc4_incr, 31, 0) @[dec_tlu_ctl.scala 2380:82] + node mhpmc4_ns = mux(_T_2224, _T_2225, _T_2226) @[dec_tlu_ctl.scala 2380:21] + node _T_2227 = bits(mhpmc4_wr_en, 0, 0) @[dec_tlu_ctl.scala 2381:43] inst rvclkhdr_28 of rvclkhdr_748 @[lib.scala 368:23] rvclkhdr_28.clock <= clock rvclkhdr_28.reset <= reset rvclkhdr_28.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_28.io.en <= _T_2237 @[lib.scala 371:17] + rvclkhdr_28.io.en <= _T_2227 @[lib.scala 371:17] rvclkhdr_28.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2238 : UInt, rvclkhdr_28.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2238 <= mhpmc4_ns @[lib.scala 374:16] - mhpmc4 <= _T_2238 @[dec_tlu_ctl.scala 2381:9] - node _T_2239 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2383:66] - node _T_2240 = eq(_T_2239, UInt<12>("h0b84")) @[dec_tlu_ctl.scala 2383:73] - node mhpmc4h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2240) @[dec_tlu_ctl.scala 2383:44] + reg _T_2228 : UInt, rvclkhdr_28.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2228 <= mhpmc4_ns @[lib.scala 374:16] + mhpmc4 <= _T_2228 @[dec_tlu_ctl.scala 2381:9] + node _T_2229 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2383:66] + node _T_2230 = eq(_T_2229, UInt<12>("h0b84")) @[dec_tlu_ctl.scala 2383:73] + node mhpmc4h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2230) @[dec_tlu_ctl.scala 2383:44] node mhpmc4h_wr_en = or(mhpmc4h_wr_en0, mhpmc4_wr_en1) @[dec_tlu_ctl.scala 2384:38] - node _T_2241 = bits(mhpmc4h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2385:38] - node _T_2242 = bits(mhpmc4_incr, 63, 32) @[dec_tlu_ctl.scala 2385:78] - node mhpmc4h_ns = mux(_T_2241, io.dec_csr_wrdata_r, _T_2242) @[dec_tlu_ctl.scala 2385:22] - node _T_2243 = bits(mhpmc4h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2386:46] + node _T_2231 = bits(mhpmc4h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2385:38] + node _T_2232 = bits(mhpmc4_incr, 63, 32) @[dec_tlu_ctl.scala 2385:78] + node mhpmc4h_ns = mux(_T_2231, io.dec_csr_wrdata_r, _T_2232) @[dec_tlu_ctl.scala 2385:22] + node _T_2233 = bits(mhpmc4h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2386:46] inst rvclkhdr_29 of rvclkhdr_749 @[lib.scala 368:23] rvclkhdr_29.clock <= clock rvclkhdr_29.reset <= reset rvclkhdr_29.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_29.io.en <= _T_2243 @[lib.scala 371:17] + rvclkhdr_29.io.en <= _T_2233 @[lib.scala 371:17] rvclkhdr_29.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2244 : UInt, rvclkhdr_29.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2244 <= mhpmc4h_ns @[lib.scala 374:16] - mhpmc4h <= _T_2244 @[dec_tlu_ctl.scala 2386:10] - node _T_2245 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2392:65] - node _T_2246 = eq(_T_2245, UInt<12>("h0b05")) @[dec_tlu_ctl.scala 2392:72] - node mhpmc5_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2246) @[dec_tlu_ctl.scala 2392:43] - node _T_2247 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2393:23] - node _T_2248 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2393:61] - node _T_2249 = or(_T_2247, _T_2248) @[dec_tlu_ctl.scala 2393:39] - node _T_2250 = orr(mhpmc_inc_r[2]) @[dec_tlu_ctl.scala 2393:86] - node mhpmc5_wr_en1 = and(_T_2249, _T_2250) @[dec_tlu_ctl.scala 2393:66] + reg _T_2234 : UInt, rvclkhdr_29.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2234 <= mhpmc4h_ns @[lib.scala 374:16] + mhpmc4h <= _T_2234 @[dec_tlu_ctl.scala 2386:10] + node _T_2235 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2392:65] + node _T_2236 = eq(_T_2235, UInt<12>("h0b05")) @[dec_tlu_ctl.scala 2392:72] + node mhpmc5_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2236) @[dec_tlu_ctl.scala 2392:43] + node _T_2237 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2393:23] + node _T_2238 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2393:61] + node _T_2239 = or(_T_2237, _T_2238) @[dec_tlu_ctl.scala 2393:39] + node _T_2240 = orr(mhpmc_inc_r[2]) @[dec_tlu_ctl.scala 2393:86] + node mhpmc5_wr_en1 = and(_T_2239, _T_2240) @[dec_tlu_ctl.scala 2393:66] node mhpmc5_wr_en = or(mhpmc5_wr_en0, mhpmc5_wr_en1) @[dec_tlu_ctl.scala 2394:36] - node _T_2251 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2396:28] - node _T_2252 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2396:41] - node _T_2253 = cat(_T_2251, _T_2252) @[Cat.scala 29:58] - node _T_2254 = cat(UInt<63>("h00"), mhpmc_inc_r[2]) @[Cat.scala 29:58] - node _T_2255 = add(_T_2253, _T_2254) @[dec_tlu_ctl.scala 2396:49] - node _T_2256 = tail(_T_2255, 1) @[dec_tlu_ctl.scala 2396:49] - mhpmc5_incr <= _T_2256 @[dec_tlu_ctl.scala 2396:14] - node _T_2257 = bits(mhpmc5_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2397:36] - node _T_2258 = bits(mhpmc5_incr, 31, 0) @[dec_tlu_ctl.scala 2397:76] - node mhpmc5_ns = mux(_T_2257, io.dec_csr_wrdata_r, _T_2258) @[dec_tlu_ctl.scala 2397:21] - node _T_2259 = bits(mhpmc5_wr_en, 0, 0) @[dec_tlu_ctl.scala 2399:43] + node _T_2241 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2396:28] + node _T_2242 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2396:41] + node _T_2243 = cat(_T_2241, _T_2242) @[Cat.scala 29:58] + node _T_2244 = cat(UInt<63>("h00"), mhpmc_inc_r[2]) @[Cat.scala 29:58] + node _T_2245 = add(_T_2243, _T_2244) @[dec_tlu_ctl.scala 2396:49] + node _T_2246 = tail(_T_2245, 1) @[dec_tlu_ctl.scala 2396:49] + mhpmc5_incr <= _T_2246 @[dec_tlu_ctl.scala 2396:14] + node _T_2247 = bits(mhpmc5_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2397:36] + node _T_2248 = bits(mhpmc5_incr, 31, 0) @[dec_tlu_ctl.scala 2397:76] + node mhpmc5_ns = mux(_T_2247, io.dec_csr_wrdata_r, _T_2248) @[dec_tlu_ctl.scala 2397:21] + node _T_2249 = bits(mhpmc5_wr_en, 0, 0) @[dec_tlu_ctl.scala 2399:43] inst rvclkhdr_30 of rvclkhdr_750 @[lib.scala 368:23] rvclkhdr_30.clock <= clock rvclkhdr_30.reset <= reset rvclkhdr_30.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_30.io.en <= _T_2259 @[lib.scala 371:17] + rvclkhdr_30.io.en <= _T_2249 @[lib.scala 371:17] rvclkhdr_30.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2260 : UInt, rvclkhdr_30.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2260 <= mhpmc5_ns @[lib.scala 374:16] - mhpmc5 <= _T_2260 @[dec_tlu_ctl.scala 2399:9] - node _T_2261 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2401:66] - node _T_2262 = eq(_T_2261, UInt<12>("h0b85")) @[dec_tlu_ctl.scala 2401:73] - node mhpmc5h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2262) @[dec_tlu_ctl.scala 2401:44] + reg _T_2250 : UInt, rvclkhdr_30.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2250 <= mhpmc5_ns @[lib.scala 374:16] + mhpmc5 <= _T_2250 @[dec_tlu_ctl.scala 2399:9] + node _T_2251 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2401:66] + node _T_2252 = eq(_T_2251, UInt<12>("h0b85")) @[dec_tlu_ctl.scala 2401:73] + node mhpmc5h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2252) @[dec_tlu_ctl.scala 2401:44] node mhpmc5h_wr_en = or(mhpmc5h_wr_en0, mhpmc5_wr_en1) @[dec_tlu_ctl.scala 2402:38] - node _T_2263 = bits(mhpmc5h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2403:38] - node _T_2264 = bits(mhpmc5_incr, 63, 32) @[dec_tlu_ctl.scala 2403:78] - node mhpmc5h_ns = mux(_T_2263, io.dec_csr_wrdata_r, _T_2264) @[dec_tlu_ctl.scala 2403:22] - node _T_2265 = bits(mhpmc5h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2405:46] + node _T_2253 = bits(mhpmc5h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2403:38] + node _T_2254 = bits(mhpmc5_incr, 63, 32) @[dec_tlu_ctl.scala 2403:78] + node mhpmc5h_ns = mux(_T_2253, io.dec_csr_wrdata_r, _T_2254) @[dec_tlu_ctl.scala 2403:22] + node _T_2255 = bits(mhpmc5h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2405:46] inst rvclkhdr_31 of rvclkhdr_751 @[lib.scala 368:23] rvclkhdr_31.clock <= clock rvclkhdr_31.reset <= reset rvclkhdr_31.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_31.io.en <= _T_2265 @[lib.scala 371:17] + rvclkhdr_31.io.en <= _T_2255 @[lib.scala 371:17] rvclkhdr_31.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2266 : UInt, rvclkhdr_31.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2266 <= mhpmc5h_ns @[lib.scala 374:16] - mhpmc5h <= _T_2266 @[dec_tlu_ctl.scala 2405:10] - node _T_2267 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2410:65] - node _T_2268 = eq(_T_2267, UInt<12>("h0b06")) @[dec_tlu_ctl.scala 2410:72] - node mhpmc6_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2268) @[dec_tlu_ctl.scala 2410:43] - node _T_2269 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2411:23] - node _T_2270 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2411:61] - node _T_2271 = or(_T_2269, _T_2270) @[dec_tlu_ctl.scala 2411:39] - node _T_2272 = orr(mhpmc_inc_r[3]) @[dec_tlu_ctl.scala 2411:86] - node mhpmc6_wr_en1 = and(_T_2271, _T_2272) @[dec_tlu_ctl.scala 2411:66] + reg _T_2256 : UInt, rvclkhdr_31.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2256 <= mhpmc5h_ns @[lib.scala 374:16] + mhpmc5h <= _T_2256 @[dec_tlu_ctl.scala 2405:10] + node _T_2257 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2410:65] + node _T_2258 = eq(_T_2257, UInt<12>("h0b06")) @[dec_tlu_ctl.scala 2410:72] + node mhpmc6_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2258) @[dec_tlu_ctl.scala 2410:43] + node _T_2259 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2411:23] + node _T_2260 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2411:61] + node _T_2261 = or(_T_2259, _T_2260) @[dec_tlu_ctl.scala 2411:39] + node _T_2262 = orr(mhpmc_inc_r[3]) @[dec_tlu_ctl.scala 2411:86] + node mhpmc6_wr_en1 = and(_T_2261, _T_2262) @[dec_tlu_ctl.scala 2411:66] node mhpmc6_wr_en = or(mhpmc6_wr_en0, mhpmc6_wr_en1) @[dec_tlu_ctl.scala 2412:36] - node _T_2273 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2414:28] - node _T_2274 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2414:41] - node _T_2275 = cat(_T_2273, _T_2274) @[Cat.scala 29:58] - node _T_2276 = cat(UInt<63>("h00"), mhpmc_inc_r[3]) @[Cat.scala 29:58] - node _T_2277 = add(_T_2275, _T_2276) @[dec_tlu_ctl.scala 2414:49] - node _T_2278 = tail(_T_2277, 1) @[dec_tlu_ctl.scala 2414:49] - mhpmc6_incr <= _T_2278 @[dec_tlu_ctl.scala 2414:14] - node _T_2279 = bits(mhpmc6_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2415:36] - node _T_2280 = bits(mhpmc6_incr, 31, 0) @[dec_tlu_ctl.scala 2415:76] - node mhpmc6_ns = mux(_T_2279, io.dec_csr_wrdata_r, _T_2280) @[dec_tlu_ctl.scala 2415:21] - node _T_2281 = bits(mhpmc6_wr_en, 0, 0) @[dec_tlu_ctl.scala 2417:43] + node _T_2263 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2414:28] + node _T_2264 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2414:41] + node _T_2265 = cat(_T_2263, _T_2264) @[Cat.scala 29:58] + node _T_2266 = cat(UInt<63>("h00"), mhpmc_inc_r[3]) @[Cat.scala 29:58] + node _T_2267 = add(_T_2265, _T_2266) @[dec_tlu_ctl.scala 2414:49] + node _T_2268 = tail(_T_2267, 1) @[dec_tlu_ctl.scala 2414:49] + mhpmc6_incr <= _T_2268 @[dec_tlu_ctl.scala 2414:14] + node _T_2269 = bits(mhpmc6_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2415:36] + node _T_2270 = bits(mhpmc6_incr, 31, 0) @[dec_tlu_ctl.scala 2415:76] + node mhpmc6_ns = mux(_T_2269, io.dec_csr_wrdata_r, _T_2270) @[dec_tlu_ctl.scala 2415:21] + node _T_2271 = bits(mhpmc6_wr_en, 0, 0) @[dec_tlu_ctl.scala 2417:43] inst rvclkhdr_32 of rvclkhdr_752 @[lib.scala 368:23] rvclkhdr_32.clock <= clock rvclkhdr_32.reset <= reset rvclkhdr_32.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_32.io.en <= _T_2281 @[lib.scala 371:17] + rvclkhdr_32.io.en <= _T_2271 @[lib.scala 371:17] rvclkhdr_32.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2282 : UInt, rvclkhdr_32.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2282 <= mhpmc6_ns @[lib.scala 374:16] - mhpmc6 <= _T_2282 @[dec_tlu_ctl.scala 2417:9] - node _T_2283 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2419:66] - node _T_2284 = eq(_T_2283, UInt<12>("h0b86")) @[dec_tlu_ctl.scala 2419:73] - node mhpmc6h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2284) @[dec_tlu_ctl.scala 2419:44] + reg _T_2272 : UInt, rvclkhdr_32.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2272 <= mhpmc6_ns @[lib.scala 374:16] + mhpmc6 <= _T_2272 @[dec_tlu_ctl.scala 2417:9] + node _T_2273 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2419:66] + node _T_2274 = eq(_T_2273, UInt<12>("h0b86")) @[dec_tlu_ctl.scala 2419:73] + node mhpmc6h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2274) @[dec_tlu_ctl.scala 2419:44] node mhpmc6h_wr_en = or(mhpmc6h_wr_en0, mhpmc6_wr_en1) @[dec_tlu_ctl.scala 2420:38] - node _T_2285 = bits(mhpmc6h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2421:38] - node _T_2286 = bits(mhpmc6_incr, 63, 32) @[dec_tlu_ctl.scala 2421:78] - node mhpmc6h_ns = mux(_T_2285, io.dec_csr_wrdata_r, _T_2286) @[dec_tlu_ctl.scala 2421:22] - node _T_2287 = bits(mhpmc6h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2423:46] + node _T_2275 = bits(mhpmc6h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2421:38] + node _T_2276 = bits(mhpmc6_incr, 63, 32) @[dec_tlu_ctl.scala 2421:78] + node mhpmc6h_ns = mux(_T_2275, io.dec_csr_wrdata_r, _T_2276) @[dec_tlu_ctl.scala 2421:22] + node _T_2277 = bits(mhpmc6h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2423:46] inst rvclkhdr_33 of rvclkhdr_753 @[lib.scala 368:23] rvclkhdr_33.clock <= clock rvclkhdr_33.reset <= reset rvclkhdr_33.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_33.io.en <= _T_2287 @[lib.scala 371:17] + rvclkhdr_33.io.en <= _T_2277 @[lib.scala 371:17] rvclkhdr_33.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2288 : UInt, rvclkhdr_33.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2288 <= mhpmc6h_ns @[lib.scala 374:16] - mhpmc6h <= _T_2288 @[dec_tlu_ctl.scala 2423:10] - node _T_2289 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2430:50] - node _T_2290 = gt(_T_2289, UInt<10>("h0204")) @[dec_tlu_ctl.scala 2430:56] - node _T_2291 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 2430:93] - node _T_2292 = orr(_T_2291) @[dec_tlu_ctl.scala 2430:102] - node _T_2293 = or(_T_2290, _T_2292) @[dec_tlu_ctl.scala 2430:71] - node _T_2294 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2430:141] - node event_saturate_r = mux(_T_2293, UInt<10>("h0204"), _T_2294) @[dec_tlu_ctl.scala 2430:28] - node _T_2295 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2432:63] - node _T_2296 = eq(_T_2295, UInt<12>("h0323")) @[dec_tlu_ctl.scala 2432:70] - node wr_mhpme3_r = and(io.dec_csr_wen_r_mod, _T_2296) @[dec_tlu_ctl.scala 2432:41] - node _T_2297 = bits(wr_mhpme3_r, 0, 0) @[dec_tlu_ctl.scala 2434:80] - reg _T_2298 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2297 : @[Reg.scala 28:19] - _T_2298 <= event_saturate_r @[Reg.scala 28:23] + reg _T_2278 : UInt, rvclkhdr_33.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2278 <= mhpmc6h_ns @[lib.scala 374:16] + mhpmc6h <= _T_2278 @[dec_tlu_ctl.scala 2423:10] + node _T_2279 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2430:50] + node _T_2280 = gt(_T_2279, UInt<10>("h0204")) @[dec_tlu_ctl.scala 2430:56] + node _T_2281 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 2430:93] + node _T_2282 = orr(_T_2281) @[dec_tlu_ctl.scala 2430:102] + node _T_2283 = or(_T_2280, _T_2282) @[dec_tlu_ctl.scala 2430:71] + node _T_2284 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2430:141] + node event_saturate_r = mux(_T_2283, UInt<10>("h0204"), _T_2284) @[dec_tlu_ctl.scala 2430:28] + node _T_2285 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2432:63] + node _T_2286 = eq(_T_2285, UInt<12>("h0323")) @[dec_tlu_ctl.scala 2432:70] + node wr_mhpme3_r = and(io.dec_csr_wen_r_mod, _T_2286) @[dec_tlu_ctl.scala 2432:41] + node _T_2287 = bits(wr_mhpme3_r, 0, 0) @[dec_tlu_ctl.scala 2434:80] + reg _T_2288 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2287 : @[Reg.scala 28:19] + _T_2288 <= event_saturate_r @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mhpme3 <= _T_2298 @[dec_tlu_ctl.scala 2434:9] - node _T_2299 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2439:63] - node _T_2300 = eq(_T_2299, UInt<12>("h0324")) @[dec_tlu_ctl.scala 2439:70] - node wr_mhpme4_r = and(io.dec_csr_wen_r_mod, _T_2300) @[dec_tlu_ctl.scala 2439:41] - node _T_2301 = bits(wr_mhpme4_r, 0, 0) @[dec_tlu_ctl.scala 2440:80] - reg _T_2302 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2301 : @[Reg.scala 28:19] - _T_2302 <= event_saturate_r @[Reg.scala 28:23] + mhpme3 <= _T_2288 @[dec_tlu_ctl.scala 2434:9] + node _T_2289 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2439:63] + node _T_2290 = eq(_T_2289, UInt<12>("h0324")) @[dec_tlu_ctl.scala 2439:70] + node wr_mhpme4_r = and(io.dec_csr_wen_r_mod, _T_2290) @[dec_tlu_ctl.scala 2439:41] + node _T_2291 = bits(wr_mhpme4_r, 0, 0) @[dec_tlu_ctl.scala 2440:80] + reg _T_2292 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2291 : @[Reg.scala 28:19] + _T_2292 <= event_saturate_r @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mhpme4 <= _T_2302 @[dec_tlu_ctl.scala 2440:9] - node _T_2303 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2446:63] - node _T_2304 = eq(_T_2303, UInt<12>("h0325")) @[dec_tlu_ctl.scala 2446:70] - node wr_mhpme5_r = and(io.dec_csr_wen_r_mod, _T_2304) @[dec_tlu_ctl.scala 2446:41] - node _T_2305 = bits(wr_mhpme5_r, 0, 0) @[dec_tlu_ctl.scala 2447:80] - reg _T_2306 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2305 : @[Reg.scala 28:19] - _T_2306 <= event_saturate_r @[Reg.scala 28:23] + mhpme4 <= _T_2292 @[dec_tlu_ctl.scala 2440:9] + node _T_2293 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2446:63] + node _T_2294 = eq(_T_2293, UInt<12>("h0325")) @[dec_tlu_ctl.scala 2446:70] + node wr_mhpme5_r = and(io.dec_csr_wen_r_mod, _T_2294) @[dec_tlu_ctl.scala 2446:41] + node _T_2295 = bits(wr_mhpme5_r, 0, 0) @[dec_tlu_ctl.scala 2447:80] + reg _T_2296 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2295 : @[Reg.scala 28:19] + _T_2296 <= event_saturate_r @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mhpme5 <= _T_2306 @[dec_tlu_ctl.scala 2447:9] - node _T_2307 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2453:63] - node _T_2308 = eq(_T_2307, UInt<12>("h0326")) @[dec_tlu_ctl.scala 2453:70] - node wr_mhpme6_r = and(io.dec_csr_wen_r_mod, _T_2308) @[dec_tlu_ctl.scala 2453:41] - node _T_2309 = bits(wr_mhpme6_r, 0, 0) @[dec_tlu_ctl.scala 2454:80] - reg _T_2310 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2309 : @[Reg.scala 28:19] - _T_2310 <= event_saturate_r @[Reg.scala 28:23] + mhpme5 <= _T_2296 @[dec_tlu_ctl.scala 2447:9] + node _T_2297 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2453:63] + node _T_2298 = eq(_T_2297, UInt<12>("h0326")) @[dec_tlu_ctl.scala 2453:70] + node wr_mhpme6_r = and(io.dec_csr_wen_r_mod, _T_2298) @[dec_tlu_ctl.scala 2453:41] + node _T_2299 = bits(wr_mhpme6_r, 0, 0) @[dec_tlu_ctl.scala 2454:80] + reg _T_2300 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2299 : @[Reg.scala 28:19] + _T_2300 <= event_saturate_r @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mhpme6 <= _T_2310 @[dec_tlu_ctl.scala 2454:9] - node _T_2311 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2470:70] - node _T_2312 = eq(_T_2311, UInt<12>("h0320")) @[dec_tlu_ctl.scala 2470:77] - node wr_mcountinhibit_r = and(io.dec_csr_wen_r_mod, _T_2312) @[dec_tlu_ctl.scala 2470:48] - node _T_2313 = bits(mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2472:54] + mhpme6 <= _T_2300 @[dec_tlu_ctl.scala 2454:9] + node _T_2301 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2470:70] + node _T_2302 = eq(_T_2301, UInt<12>("h0320")) @[dec_tlu_ctl.scala 2470:77] + node wr_mcountinhibit_r = and(io.dec_csr_wen_r_mod, _T_2302) @[dec_tlu_ctl.scala 2470:48] + node _T_2303 = bits(mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2472:54] wire temp_ncount0 : UInt<1> - temp_ncount0 <= _T_2313 - node _T_2314 = bits(mcountinhibit, 1, 1) @[dec_tlu_ctl.scala 2473:54] + temp_ncount0 <= _T_2303 + node _T_2304 = bits(mcountinhibit, 1, 1) @[dec_tlu_ctl.scala 2473:54] wire temp_ncount1 : UInt<1> - temp_ncount1 <= _T_2314 - node _T_2315 = bits(mcountinhibit, 6, 2) @[dec_tlu_ctl.scala 2474:55] + temp_ncount1 <= _T_2304 + node _T_2305 = bits(mcountinhibit, 6, 2) @[dec_tlu_ctl.scala 2474:55] wire temp_ncount6_2 : UInt<5> - temp_ncount6_2 <= _T_2315 - node _T_2316 = bits(io.dec_csr_wrdata_r, 6, 2) @[dec_tlu_ctl.scala 2475:74] - node _T_2317 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2475:103] - reg _T_2318 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2317 : @[Reg.scala 28:19] - _T_2318 <= _T_2316 @[Reg.scala 28:23] + temp_ncount6_2 <= _T_2305 + node _T_2306 = bits(io.dec_csr_wrdata_r, 6, 2) @[dec_tlu_ctl.scala 2475:74] + node _T_2307 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2475:103] + reg _T_2308 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2307 : @[Reg.scala 28:19] + _T_2308 <= _T_2306 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - temp_ncount6_2 <= _T_2318 @[dec_tlu_ctl.scala 2475:17] - node _T_2319 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2477:72] - node _T_2320 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2477:99] - reg _T_2321 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2320 : @[Reg.scala 28:19] - _T_2321 <= _T_2319 @[Reg.scala 28:23] + temp_ncount6_2 <= _T_2308 @[dec_tlu_ctl.scala 2475:17] + node _T_2309 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2477:72] + node _T_2310 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2477:99] + reg _T_2311 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2310 : @[Reg.scala 28:19] + _T_2311 <= _T_2309 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - temp_ncount0 <= _T_2321 @[dec_tlu_ctl.scala 2477:15] - node _T_2322 = cat(temp_ncount6_2, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2323 = cat(_T_2322, temp_ncount0) @[Cat.scala 29:58] - mcountinhibit <= _T_2323 @[dec_tlu_ctl.scala 2478:16] - node _T_2324 = or(io.i0_valid_wb, io.exc_or_int_valid_r_d1) @[dec_tlu_ctl.scala 2485:51] - node _T_2325 = or(_T_2324, io.interrupt_valid_r_d1) @[dec_tlu_ctl.scala 2485:78] - node _T_2326 = or(_T_2325, io.dec_tlu_i0_valid_wb1) @[dec_tlu_ctl.scala 2485:104] - node _T_2327 = or(_T_2326, io.dec_tlu_i0_exc_valid_wb1) @[dec_tlu_ctl.scala 2485:130] - node _T_2328 = or(_T_2327, io.dec_tlu_int_valid_wb1) @[dec_tlu_ctl.scala 2486:32] - node _T_2329 = or(_T_2328, io.clk_override) @[dec_tlu_ctl.scala 2486:59] - node _T_2330 = bits(_T_2329, 0, 0) @[dec_tlu_ctl.scala 2486:78] + temp_ncount0 <= _T_2311 @[dec_tlu_ctl.scala 2477:15] + node _T_2312 = cat(temp_ncount6_2, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2313 = cat(_T_2312, temp_ncount0) @[Cat.scala 29:58] + mcountinhibit <= _T_2313 @[dec_tlu_ctl.scala 2478:16] + node _T_2314 = or(io.i0_valid_wb, io.exc_or_int_valid_r_d1) @[dec_tlu_ctl.scala 2485:51] + node _T_2315 = or(_T_2314, io.interrupt_valid_r_d1) @[dec_tlu_ctl.scala 2485:78] + node _T_2316 = or(_T_2315, io.dec_tlu_i0_valid_wb1) @[dec_tlu_ctl.scala 2485:104] + node _T_2317 = or(_T_2316, io.dec_tlu_i0_exc_valid_wb1) @[dec_tlu_ctl.scala 2485:130] + node _T_2318 = or(_T_2317, io.dec_tlu_int_valid_wb1) @[dec_tlu_ctl.scala 2486:32] + node _T_2319 = or(_T_2318, io.clk_override) @[dec_tlu_ctl.scala 2486:59] + node _T_2320 = bits(_T_2319, 0, 0) @[dec_tlu_ctl.scala 2486:78] inst rvclkhdr_34 of rvclkhdr_754 @[lib.scala 343:22] rvclkhdr_34.clock <= clock rvclkhdr_34.reset <= reset rvclkhdr_34.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_34.io.en <= _T_2330 @[lib.scala 345:16] + rvclkhdr_34.io.en <= _T_2320 @[lib.scala 345:16] rvclkhdr_34.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - reg _T_2331 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2488:62] - _T_2331 <= io.i0_valid_wb @[dec_tlu_ctl.scala 2488:62] - io.dec_tlu_i0_valid_wb1 <= _T_2331 @[dec_tlu_ctl.scala 2488:30] - node _T_2332 = or(io.i0_exception_valid_r_d1, io.lsu_i0_exc_r_d1) @[dec_tlu_ctl.scala 2489:91] - node _T_2333 = not(io.trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 2489:137] - node _T_2334 = and(io.trigger_hit_r_d1, _T_2333) @[dec_tlu_ctl.scala 2489:135] - node _T_2335 = or(_T_2332, _T_2334) @[dec_tlu_ctl.scala 2489:112] - reg _T_2336 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2489:62] - _T_2336 <= _T_2335 @[dec_tlu_ctl.scala 2489:62] - io.dec_tlu_i0_exc_valid_wb1 <= _T_2336 @[dec_tlu_ctl.scala 2489:30] - reg _T_2337 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2490:62] - _T_2337 <= io.exc_cause_wb @[dec_tlu_ctl.scala 2490:62] - io.dec_tlu_exc_cause_wb1 <= _T_2337 @[dec_tlu_ctl.scala 2490:30] - reg _T_2338 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2491:62] - _T_2338 <= io.interrupt_valid_r_d1 @[dec_tlu_ctl.scala 2491:62] - io.dec_tlu_int_valid_wb1 <= _T_2338 @[dec_tlu_ctl.scala 2491:30] + reg _T_2321 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2488:62] + _T_2321 <= io.i0_valid_wb @[dec_tlu_ctl.scala 2488:62] + io.dec_tlu_i0_valid_wb1 <= _T_2321 @[dec_tlu_ctl.scala 2488:30] + node _T_2322 = or(io.i0_exception_valid_r_d1, io.lsu_i0_exc_r_d1) @[dec_tlu_ctl.scala 2489:91] + node _T_2323 = not(io.trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 2489:137] + node _T_2324 = and(io.trigger_hit_r_d1, _T_2323) @[dec_tlu_ctl.scala 2489:135] + node _T_2325 = or(_T_2322, _T_2324) @[dec_tlu_ctl.scala 2489:112] + reg _T_2326 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2489:62] + _T_2326 <= _T_2325 @[dec_tlu_ctl.scala 2489:62] + io.dec_tlu_i0_exc_valid_wb1 <= _T_2326 @[dec_tlu_ctl.scala 2489:30] + reg _T_2327 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2490:62] + _T_2327 <= io.exc_cause_wb @[dec_tlu_ctl.scala 2490:62] + io.dec_tlu_exc_cause_wb1 <= _T_2327 @[dec_tlu_ctl.scala 2490:30] + reg _T_2328 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2491:62] + _T_2328 <= io.interrupt_valid_r_d1 @[dec_tlu_ctl.scala 2491:62] + io.dec_tlu_int_valid_wb1 <= _T_2328 @[dec_tlu_ctl.scala 2491:30] io.dec_tlu_mtval_wb1 <= mtval @[dec_tlu_ctl.scala 2493:24] - node _T_2339 = bits(io.csr_pkt.csr_misa, 0, 0) @[dec_tlu_ctl.scala 2499:61] - node _T_2340 = bits(io.csr_pkt.csr_mvendorid, 0, 0) @[dec_tlu_ctl.scala 2500:42] - node _T_2341 = bits(io.csr_pkt.csr_marchid, 0, 0) @[dec_tlu_ctl.scala 2501:40] - node _T_2342 = bits(io.csr_pkt.csr_mimpid, 0, 0) @[dec_tlu_ctl.scala 2502:39] - node _T_2343 = bits(io.csr_pkt.csr_mhartid, 0, 0) @[dec_tlu_ctl.scala 2503:40] - node _T_2344 = cat(io.core_id, UInt<4>("h00")) @[Cat.scala 29:58] - node _T_2345 = bits(io.csr_pkt.csr_mstatus, 0, 0) @[dec_tlu_ctl.scala 2504:40] - node _T_2346 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 2504:103] - node _T_2347 = bits(io.mstatus, 0, 0) @[dec_tlu_ctl.scala 2504:128] - node _T_2348 = cat(UInt<3>("h00"), _T_2347) @[Cat.scala 29:58] - node _T_2349 = cat(_T_2348, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2350 = cat(UInt<3>("h00"), _T_2346) @[Cat.scala 29:58] - node _T_2351 = cat(UInt<19>("h00"), UInt<2>("h03")) @[Cat.scala 29:58] - node _T_2352 = cat(_T_2351, _T_2350) @[Cat.scala 29:58] - node _T_2353 = cat(_T_2352, _T_2349) @[Cat.scala 29:58] - node _T_2354 = bits(io.csr_pkt.csr_mtvec, 0, 0) @[dec_tlu_ctl.scala 2505:38] - node _T_2355 = bits(io.mtvec, 30, 1) @[dec_tlu_ctl.scala 2505:70] - node _T_2356 = bits(io.mtvec, 0, 0) @[dec_tlu_ctl.scala 2505:96] - node _T_2357 = cat(_T_2355, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2358 = cat(_T_2357, _T_2356) @[Cat.scala 29:58] - node _T_2359 = bits(io.csr_pkt.csr_mip, 0, 0) @[dec_tlu_ctl.scala 2506:36] - node _T_2360 = bits(io.mip, 5, 3) @[dec_tlu_ctl.scala 2506:78] - node _T_2361 = bits(io.mip, 2, 2) @[dec_tlu_ctl.scala 2506:102] - node _T_2362 = bits(io.mip, 1, 1) @[dec_tlu_ctl.scala 2506:123] - node _T_2363 = bits(io.mip, 0, 0) @[dec_tlu_ctl.scala 2506:144] - node _T_2364 = cat(_T_2363, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2365 = cat(_T_2362, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2366 = cat(_T_2365, _T_2364) @[Cat.scala 29:58] - node _T_2367 = cat(_T_2361, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2368 = cat(UInt<1>("h00"), _T_2360) @[Cat.scala 29:58] - node _T_2369 = cat(_T_2368, UInt<16>("h00")) @[Cat.scala 29:58] - node _T_2370 = cat(_T_2369, _T_2367) @[Cat.scala 29:58] - node _T_2371 = cat(_T_2370, _T_2366) @[Cat.scala 29:58] - node _T_2372 = bits(io.csr_pkt.csr_mie, 0, 0) @[dec_tlu_ctl.scala 2507:36] - node _T_2373 = bits(mie, 5, 3) @[dec_tlu_ctl.scala 2507:75] - node _T_2374 = bits(mie, 2, 2) @[dec_tlu_ctl.scala 2507:96] - node _T_2375 = bits(mie, 1, 1) @[dec_tlu_ctl.scala 2507:114] - node _T_2376 = bits(mie, 0, 0) @[dec_tlu_ctl.scala 2507:132] - node _T_2377 = cat(_T_2376, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2378 = cat(_T_2375, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2379 = cat(_T_2378, _T_2377) @[Cat.scala 29:58] - node _T_2380 = cat(_T_2374, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2381 = cat(UInt<1>("h00"), _T_2373) @[Cat.scala 29:58] - node _T_2382 = cat(_T_2381, UInt<16>("h00")) @[Cat.scala 29:58] - node _T_2383 = cat(_T_2382, _T_2380) @[Cat.scala 29:58] - node _T_2384 = cat(_T_2383, _T_2379) @[Cat.scala 29:58] - node _T_2385 = bits(io.csr_pkt.csr_mcyclel, 0, 0) @[dec_tlu_ctl.scala 2508:40] - node _T_2386 = bits(mcyclel, 31, 0) @[dec_tlu_ctl.scala 2508:65] - node _T_2387 = bits(io.csr_pkt.csr_mcycleh, 0, 0) @[dec_tlu_ctl.scala 2509:40] - node _T_2388 = bits(mcycleh_inc, 31, 0) @[dec_tlu_ctl.scala 2509:69] - node _T_2389 = bits(io.csr_pkt.csr_minstretl, 0, 0) @[dec_tlu_ctl.scala 2510:42] - node _T_2390 = bits(minstretl, 31, 0) @[dec_tlu_ctl.scala 2510:72] - node _T_2391 = bits(io.csr_pkt.csr_minstreth, 0, 0) @[dec_tlu_ctl.scala 2511:42] - node _T_2392 = bits(minstreth_inc, 31, 0) @[dec_tlu_ctl.scala 2511:72] - node _T_2393 = bits(io.csr_pkt.csr_mscratch, 0, 0) @[dec_tlu_ctl.scala 2512:41] - node _T_2394 = bits(mscratch, 31, 0) @[dec_tlu_ctl.scala 2512:66] - node _T_2395 = bits(io.csr_pkt.csr_mepc, 0, 0) @[dec_tlu_ctl.scala 2513:37] - node _T_2396 = cat(io.mepc, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2397 = bits(io.csr_pkt.csr_mcause, 0, 0) @[dec_tlu_ctl.scala 2514:39] - node _T_2398 = bits(mcause, 31, 0) @[dec_tlu_ctl.scala 2514:64] - node _T_2399 = bits(io.csr_pkt.csr_mscause, 0, 0) @[dec_tlu_ctl.scala 2515:40] - node _T_2400 = bits(mscause, 3, 0) @[dec_tlu_ctl.scala 2515:80] - node _T_2401 = cat(UInt<28>("h00"), _T_2400) @[Cat.scala 29:58] - node _T_2402 = bits(io.csr_pkt.csr_mtval, 0, 0) @[dec_tlu_ctl.scala 2516:38] - node _T_2403 = bits(mtval, 31, 0) @[dec_tlu_ctl.scala 2516:63] - node _T_2404 = bits(io.csr_pkt.csr_mrac, 0, 0) @[dec_tlu_ctl.scala 2517:37] - node _T_2405 = bits(mrac, 31, 0) @[dec_tlu_ctl.scala 2517:62] - node _T_2406 = bits(io.csr_pkt.csr_mdseac, 0, 0) @[dec_tlu_ctl.scala 2518:39] - node _T_2407 = bits(mdseac, 31, 0) @[dec_tlu_ctl.scala 2518:64] - node _T_2408 = bits(io.csr_pkt.csr_meivt, 0, 0) @[dec_tlu_ctl.scala 2519:38] - node _T_2409 = cat(meivt, UInt<10>("h00")) @[Cat.scala 29:58] - node _T_2410 = bits(io.csr_pkt.csr_meihap, 0, 0) @[dec_tlu_ctl.scala 2520:39] - node _T_2411 = cat(meivt, meihap) @[Cat.scala 29:58] - node _T_2412 = cat(_T_2411, UInt<2>("h00")) @[Cat.scala 29:58] - node _T_2413 = bits(io.csr_pkt.csr_meicurpl, 0, 0) @[dec_tlu_ctl.scala 2521:41] - node _T_2414 = bits(meicurpl, 3, 0) @[dec_tlu_ctl.scala 2521:81] - node _T_2415 = cat(UInt<28>("h00"), _T_2414) @[Cat.scala 29:58] - node _T_2416 = bits(io.csr_pkt.csr_meicidpl, 0, 0) @[dec_tlu_ctl.scala 2522:41] - node _T_2417 = bits(meicidpl, 3, 0) @[dec_tlu_ctl.scala 2522:81] - node _T_2418 = cat(UInt<28>("h00"), _T_2417) @[Cat.scala 29:58] - node _T_2419 = bits(io.csr_pkt.csr_meipt, 0, 0) @[dec_tlu_ctl.scala 2523:38] - node _T_2420 = bits(meipt, 3, 0) @[dec_tlu_ctl.scala 2523:78] - node _T_2421 = cat(UInt<28>("h00"), _T_2420) @[Cat.scala 29:58] - node _T_2422 = bits(io.csr_pkt.csr_mcgc, 0, 0) @[dec_tlu_ctl.scala 2524:37] - node _T_2423 = bits(mcgc, 8, 0) @[dec_tlu_ctl.scala 2524:77] - node _T_2424 = cat(UInt<23>("h00"), _T_2423) @[Cat.scala 29:58] - node _T_2425 = bits(io.csr_pkt.csr_mfdc, 0, 0) @[dec_tlu_ctl.scala 2525:37] - node _T_2426 = bits(mfdc, 18, 0) @[dec_tlu_ctl.scala 2525:77] - node _T_2427 = cat(UInt<13>("h00"), _T_2426) @[Cat.scala 29:58] - node _T_2428 = bits(io.csr_pkt.csr_dcsr, 0, 0) @[dec_tlu_ctl.scala 2526:37] - node _T_2429 = bits(io.dcsr, 15, 2) @[dec_tlu_ctl.scala 2526:85] - node _T_2430 = cat(UInt<16>("h04000"), _T_2429) @[Cat.scala 29:58] - node _T_2431 = cat(_T_2430, UInt<2>("h03")) @[Cat.scala 29:58] - node _T_2432 = bits(io.csr_pkt.csr_dpc, 0, 0) @[dec_tlu_ctl.scala 2527:36] - node _T_2433 = cat(io.dpc, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2434 = bits(io.csr_pkt.csr_dicad0, 0, 0) @[dec_tlu_ctl.scala 2528:39] - node _T_2435 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2528:64] - node _T_2436 = bits(io.csr_pkt.csr_dicad0h, 0, 0) @[dec_tlu_ctl.scala 2529:40] - node _T_2437 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2529:65] - node _T_2438 = bits(io.csr_pkt.csr_dicad1, 0, 0) @[dec_tlu_ctl.scala 2530:39] - node _T_2439 = bits(dicad1, 31, 0) @[dec_tlu_ctl.scala 2530:64] - node _T_2440 = bits(io.csr_pkt.csr_dicawics, 0, 0) @[dec_tlu_ctl.scala 2531:41] - node _T_2441 = bits(dicawics, 16, 16) @[dec_tlu_ctl.scala 2531:80] - node _T_2442 = bits(dicawics, 15, 14) @[dec_tlu_ctl.scala 2531:104] - node _T_2443 = bits(dicawics, 13, 0) @[dec_tlu_ctl.scala 2531:131] - node _T_2444 = cat(UInt<3>("h00"), _T_2443) @[Cat.scala 29:58] - node _T_2445 = cat(_T_2444, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2446 = cat(UInt<2>("h00"), _T_2442) @[Cat.scala 29:58] - node _T_2447 = cat(UInt<7>("h00"), _T_2441) @[Cat.scala 29:58] - node _T_2448 = cat(_T_2447, _T_2446) @[Cat.scala 29:58] - node _T_2449 = cat(_T_2448, _T_2445) @[Cat.scala 29:58] - node _T_2450 = bits(io.csr_pkt.csr_mtsel, 0, 0) @[dec_tlu_ctl.scala 2532:38] - node _T_2451 = bits(mtsel, 1, 0) @[dec_tlu_ctl.scala 2532:78] - node _T_2452 = cat(UInt<30>("h00"), _T_2451) @[Cat.scala 29:58] - node _T_2453 = bits(io.csr_pkt.csr_mtdata1, 0, 0) @[dec_tlu_ctl.scala 2533:40] - node _T_2454 = bits(mtdata1_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2533:74] - node _T_2455 = bits(io.csr_pkt.csr_mtdata2, 0, 0) @[dec_tlu_ctl.scala 2534:40] - node _T_2456 = bits(mtdata2_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2534:74] - node _T_2457 = bits(io.csr_pkt.csr_micect, 0, 0) @[dec_tlu_ctl.scala 2535:39] - node _T_2458 = bits(micect, 31, 0) @[dec_tlu_ctl.scala 2535:64] - node _T_2459 = bits(io.csr_pkt.csr_miccmect, 0, 0) @[dec_tlu_ctl.scala 2536:41] - node _T_2460 = bits(miccmect, 31, 0) @[dec_tlu_ctl.scala 2536:66] - node _T_2461 = bits(io.csr_pkt.csr_mdccmect, 0, 0) @[dec_tlu_ctl.scala 2537:41] - node _T_2462 = bits(mdccmect, 31, 0) @[dec_tlu_ctl.scala 2537:66] - node _T_2463 = bits(io.csr_pkt.csr_mhpmc3, 0, 0) @[dec_tlu_ctl.scala 2538:39] - node _T_2464 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2538:64] - node _T_2465 = bits(io.csr_pkt.csr_mhpmc4, 0, 0) @[dec_tlu_ctl.scala 2539:39] - node _T_2466 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2539:64] - node _T_2467 = bits(io.csr_pkt.csr_mhpmc5, 0, 0) @[dec_tlu_ctl.scala 2540:39] - node _T_2468 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2540:64] - node _T_2469 = bits(io.csr_pkt.csr_mhpmc6, 0, 0) @[dec_tlu_ctl.scala 2541:39] - node _T_2470 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2541:64] - node _T_2471 = bits(io.csr_pkt.csr_mhpmc3h, 0, 0) @[dec_tlu_ctl.scala 2542:40] - node _T_2472 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2542:65] - node _T_2473 = bits(io.csr_pkt.csr_mhpmc4h, 0, 0) @[dec_tlu_ctl.scala 2543:40] - node _T_2474 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2543:65] - node _T_2475 = bits(io.csr_pkt.csr_mhpmc5h, 0, 0) @[dec_tlu_ctl.scala 2544:40] - node _T_2476 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2544:65] - node _T_2477 = bits(io.csr_pkt.csr_mhpmc6h, 0, 0) @[dec_tlu_ctl.scala 2545:40] - node _T_2478 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2545:65] - node _T_2479 = bits(io.csr_pkt.csr_mfdht, 0, 0) @[dec_tlu_ctl.scala 2546:38] - node _T_2480 = bits(mfdht, 5, 0) @[dec_tlu_ctl.scala 2546:78] - node _T_2481 = cat(UInt<26>("h00"), _T_2480) @[Cat.scala 29:58] - node _T_2482 = bits(io.csr_pkt.csr_mfdhs, 0, 0) @[dec_tlu_ctl.scala 2547:38] - node _T_2483 = bits(mfdhs, 1, 0) @[dec_tlu_ctl.scala 2547:78] - node _T_2484 = cat(UInt<30>("h00"), _T_2483) @[Cat.scala 29:58] - node _T_2485 = bits(io.csr_pkt.csr_mhpme3, 0, 0) @[dec_tlu_ctl.scala 2548:39] - node _T_2486 = bits(mhpme3, 9, 0) @[dec_tlu_ctl.scala 2548:79] - node _T_2487 = cat(UInt<22>("h00"), _T_2486) @[Cat.scala 29:58] - node _T_2488 = bits(io.csr_pkt.csr_mhpme4, 0, 0) @[dec_tlu_ctl.scala 2549:39] - node _T_2489 = bits(mhpme4, 9, 0) @[dec_tlu_ctl.scala 2549:79] - node _T_2490 = cat(UInt<22>("h00"), _T_2489) @[Cat.scala 29:58] - node _T_2491 = bits(io.csr_pkt.csr_mhpme5, 0, 0) @[dec_tlu_ctl.scala 2550:39] - node _T_2492 = bits(mhpme5, 9, 0) @[dec_tlu_ctl.scala 2550:78] - node _T_2493 = cat(UInt<22>("h00"), _T_2492) @[Cat.scala 29:58] - node _T_2494 = bits(io.csr_pkt.csr_mhpme6, 0, 0) @[dec_tlu_ctl.scala 2551:39] - node _T_2495 = bits(mhpme6, 9, 0) @[dec_tlu_ctl.scala 2551:78] - node _T_2496 = cat(UInt<22>("h00"), _T_2495) @[Cat.scala 29:58] - node _T_2497 = bits(io.csr_pkt.csr_mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2552:46] - node _T_2498 = bits(mcountinhibit, 6, 0) @[dec_tlu_ctl.scala 2552:86] - node _T_2499 = cat(UInt<25>("h00"), _T_2498) @[Cat.scala 29:58] - node _T_2500 = bits(io.csr_pkt.csr_mpmc, 0, 0) @[dec_tlu_ctl.scala 2553:37] - node _T_2501 = cat(UInt<30>("h00"), mpmc) @[Cat.scala 29:58] - node _T_2502 = cat(_T_2501, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2503 = bits(io.dec_timer_read_d, 0, 0) @[dec_tlu_ctl.scala 2554:37] - node _T_2504 = bits(io.dec_timer_rddata_d, 31, 0) @[dec_tlu_ctl.scala 2554:76] - node _T_2505 = mux(_T_2339, UInt<32>("h040001104"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2506 = mux(_T_2340, UInt<32>("h045"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2507 = mux(_T_2341, UInt<32>("h010"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2508 = mux(_T_2342, UInt<32>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2509 = mux(_T_2343, _T_2344, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2510 = mux(_T_2345, _T_2353, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2511 = mux(_T_2354, _T_2358, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2512 = mux(_T_2359, _T_2371, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2513 = mux(_T_2372, _T_2384, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2514 = mux(_T_2385, _T_2386, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2515 = mux(_T_2387, _T_2388, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2516 = mux(_T_2389, _T_2390, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2517 = mux(_T_2391, _T_2392, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2518 = mux(_T_2393, _T_2394, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2519 = mux(_T_2395, _T_2396, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2520 = mux(_T_2397, _T_2398, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2521 = mux(_T_2399, _T_2401, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2522 = mux(_T_2402, _T_2403, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2523 = mux(_T_2404, _T_2405, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2524 = mux(_T_2406, _T_2407, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2525 = mux(_T_2408, _T_2409, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2526 = mux(_T_2410, _T_2412, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2527 = mux(_T_2413, _T_2415, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2528 = mux(_T_2416, _T_2418, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2529 = mux(_T_2419, _T_2421, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2530 = mux(_T_2422, _T_2424, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2531 = mux(_T_2425, _T_2427, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2532 = mux(_T_2428, _T_2431, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2533 = mux(_T_2432, _T_2433, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2534 = mux(_T_2434, _T_2435, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2535 = mux(_T_2436, _T_2437, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2536 = mux(_T_2438, _T_2439, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2537 = mux(_T_2440, _T_2449, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2538 = mux(_T_2450, _T_2452, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2539 = mux(_T_2453, _T_2454, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2540 = mux(_T_2455, _T_2456, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2541 = mux(_T_2457, _T_2458, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2542 = mux(_T_2459, _T_2460, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2543 = mux(_T_2461, _T_2462, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2544 = mux(_T_2463, _T_2464, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2545 = mux(_T_2465, _T_2466, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2546 = mux(_T_2467, _T_2468, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2547 = mux(_T_2469, _T_2470, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2548 = mux(_T_2471, _T_2472, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2549 = mux(_T_2473, _T_2474, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2550 = mux(_T_2475, _T_2476, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2551 = mux(_T_2477, _T_2478, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2552 = mux(_T_2479, _T_2481, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2553 = mux(_T_2482, _T_2484, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2554 = mux(_T_2485, _T_2487, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2555 = mux(_T_2488, _T_2490, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2556 = mux(_T_2491, _T_2493, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2557 = mux(_T_2494, _T_2496, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2558 = mux(_T_2497, _T_2499, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2559 = mux(_T_2500, _T_2502, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2560 = mux(_T_2503, _T_2504, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2561 = or(_T_2505, _T_2506) @[Mux.scala 27:72] + node _T_2329 = bits(io.csr_pkt.csr_misa, 0, 0) @[dec_tlu_ctl.scala 2499:61] + node _T_2330 = bits(io.csr_pkt.csr_mvendorid, 0, 0) @[dec_tlu_ctl.scala 2500:42] + node _T_2331 = bits(io.csr_pkt.csr_marchid, 0, 0) @[dec_tlu_ctl.scala 2501:40] + node _T_2332 = bits(io.csr_pkt.csr_mimpid, 0, 0) @[dec_tlu_ctl.scala 2502:39] + node _T_2333 = bits(io.csr_pkt.csr_mhartid, 0, 0) @[dec_tlu_ctl.scala 2503:40] + node _T_2334 = cat(io.core_id, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_2335 = bits(io.csr_pkt.csr_mstatus, 0, 0) @[dec_tlu_ctl.scala 2504:40] + node _T_2336 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 2504:103] + node _T_2337 = bits(io.mstatus, 0, 0) @[dec_tlu_ctl.scala 2504:128] + node _T_2338 = cat(UInt<3>("h00"), _T_2337) @[Cat.scala 29:58] + node _T_2339 = cat(_T_2338, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2340 = cat(UInt<3>("h00"), _T_2336) @[Cat.scala 29:58] + node _T_2341 = cat(UInt<19>("h00"), UInt<2>("h03")) @[Cat.scala 29:58] + node _T_2342 = cat(_T_2341, _T_2340) @[Cat.scala 29:58] + node _T_2343 = cat(_T_2342, _T_2339) @[Cat.scala 29:58] + node _T_2344 = bits(io.csr_pkt.csr_mtvec, 0, 0) @[dec_tlu_ctl.scala 2505:38] + node _T_2345 = bits(io.mtvec, 30, 1) @[dec_tlu_ctl.scala 2505:70] + node _T_2346 = bits(io.mtvec, 0, 0) @[dec_tlu_ctl.scala 2505:96] + node _T_2347 = cat(_T_2345, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2348 = cat(_T_2347, _T_2346) @[Cat.scala 29:58] + node _T_2349 = bits(io.csr_pkt.csr_mip, 0, 0) @[dec_tlu_ctl.scala 2506:36] + node _T_2350 = bits(io.mip, 5, 3) @[dec_tlu_ctl.scala 2506:78] + node _T_2351 = bits(io.mip, 2, 2) @[dec_tlu_ctl.scala 2506:102] + node _T_2352 = bits(io.mip, 1, 1) @[dec_tlu_ctl.scala 2506:123] + node _T_2353 = bits(io.mip, 0, 0) @[dec_tlu_ctl.scala 2506:144] + node _T_2354 = cat(_T_2353, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2355 = cat(_T_2352, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2356 = cat(_T_2355, _T_2354) @[Cat.scala 29:58] + node _T_2357 = cat(_T_2351, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2358 = cat(UInt<1>("h00"), _T_2350) @[Cat.scala 29:58] + node _T_2359 = cat(_T_2358, UInt<16>("h00")) @[Cat.scala 29:58] + node _T_2360 = cat(_T_2359, _T_2357) @[Cat.scala 29:58] + node _T_2361 = cat(_T_2360, _T_2356) @[Cat.scala 29:58] + node _T_2362 = bits(io.csr_pkt.csr_mie, 0, 0) @[dec_tlu_ctl.scala 2507:36] + node _T_2363 = bits(mie, 5, 3) @[dec_tlu_ctl.scala 2507:75] + node _T_2364 = bits(mie, 2, 2) @[dec_tlu_ctl.scala 2507:96] + node _T_2365 = bits(mie, 1, 1) @[dec_tlu_ctl.scala 2507:114] + node _T_2366 = bits(mie, 0, 0) @[dec_tlu_ctl.scala 2507:132] + node _T_2367 = cat(_T_2366, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2368 = cat(_T_2365, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2369 = cat(_T_2368, _T_2367) @[Cat.scala 29:58] + node _T_2370 = cat(_T_2364, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2371 = cat(UInt<1>("h00"), _T_2363) @[Cat.scala 29:58] + node _T_2372 = cat(_T_2371, UInt<16>("h00")) @[Cat.scala 29:58] + node _T_2373 = cat(_T_2372, _T_2370) @[Cat.scala 29:58] + node _T_2374 = cat(_T_2373, _T_2369) @[Cat.scala 29:58] + node _T_2375 = bits(io.csr_pkt.csr_mcyclel, 0, 0) @[dec_tlu_ctl.scala 2508:40] + node _T_2376 = bits(mcyclel, 31, 0) @[dec_tlu_ctl.scala 2508:65] + node _T_2377 = bits(io.csr_pkt.csr_mcycleh, 0, 0) @[dec_tlu_ctl.scala 2509:40] + node _T_2378 = bits(mcycleh_inc, 31, 0) @[dec_tlu_ctl.scala 2509:69] + node _T_2379 = bits(io.csr_pkt.csr_minstretl, 0, 0) @[dec_tlu_ctl.scala 2510:42] + node _T_2380 = bits(minstretl, 31, 0) @[dec_tlu_ctl.scala 2510:72] + node _T_2381 = bits(io.csr_pkt.csr_minstreth, 0, 0) @[dec_tlu_ctl.scala 2511:42] + node _T_2382 = bits(minstreth_inc, 31, 0) @[dec_tlu_ctl.scala 2511:72] + node _T_2383 = bits(io.csr_pkt.csr_mscratch, 0, 0) @[dec_tlu_ctl.scala 2512:41] + node _T_2384 = bits(mscratch, 31, 0) @[dec_tlu_ctl.scala 2512:66] + node _T_2385 = bits(io.csr_pkt.csr_mepc, 0, 0) @[dec_tlu_ctl.scala 2513:37] + node _T_2386 = cat(io.mepc, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2387 = bits(io.csr_pkt.csr_mcause, 0, 0) @[dec_tlu_ctl.scala 2514:39] + node _T_2388 = bits(mcause, 31, 0) @[dec_tlu_ctl.scala 2514:64] + node _T_2389 = bits(io.csr_pkt.csr_mscause, 0, 0) @[dec_tlu_ctl.scala 2515:40] + node _T_2390 = bits(mscause, 3, 0) @[dec_tlu_ctl.scala 2515:80] + node _T_2391 = cat(UInt<28>("h00"), _T_2390) @[Cat.scala 29:58] + node _T_2392 = bits(io.csr_pkt.csr_mtval, 0, 0) @[dec_tlu_ctl.scala 2516:38] + node _T_2393 = bits(mtval, 31, 0) @[dec_tlu_ctl.scala 2516:63] + node _T_2394 = bits(io.csr_pkt.csr_mrac, 0, 0) @[dec_tlu_ctl.scala 2517:37] + node _T_2395 = bits(mrac, 31, 0) @[dec_tlu_ctl.scala 2517:62] + node _T_2396 = bits(io.csr_pkt.csr_mdseac, 0, 0) @[dec_tlu_ctl.scala 2518:39] + node _T_2397 = bits(mdseac, 31, 0) @[dec_tlu_ctl.scala 2518:64] + node _T_2398 = bits(io.csr_pkt.csr_meivt, 0, 0) @[dec_tlu_ctl.scala 2519:38] + node _T_2399 = cat(meivt, UInt<10>("h00")) @[Cat.scala 29:58] + node _T_2400 = bits(io.csr_pkt.csr_meihap, 0, 0) @[dec_tlu_ctl.scala 2520:39] + node _T_2401 = cat(meivt, meihap) @[Cat.scala 29:58] + node _T_2402 = cat(_T_2401, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_2403 = bits(io.csr_pkt.csr_meicurpl, 0, 0) @[dec_tlu_ctl.scala 2521:41] + node _T_2404 = bits(meicurpl, 3, 0) @[dec_tlu_ctl.scala 2521:81] + node _T_2405 = cat(UInt<28>("h00"), _T_2404) @[Cat.scala 29:58] + node _T_2406 = bits(io.csr_pkt.csr_meicidpl, 0, 0) @[dec_tlu_ctl.scala 2522:41] + node _T_2407 = bits(meicidpl, 3, 0) @[dec_tlu_ctl.scala 2522:81] + node _T_2408 = cat(UInt<28>("h00"), _T_2407) @[Cat.scala 29:58] + node _T_2409 = bits(io.csr_pkt.csr_meipt, 0, 0) @[dec_tlu_ctl.scala 2523:38] + node _T_2410 = bits(meipt, 3, 0) @[dec_tlu_ctl.scala 2523:78] + node _T_2411 = cat(UInt<28>("h00"), _T_2410) @[Cat.scala 29:58] + node _T_2412 = bits(io.csr_pkt.csr_mcgc, 0, 0) @[dec_tlu_ctl.scala 2524:37] + node _T_2413 = bits(mcgc, 8, 0) @[dec_tlu_ctl.scala 2524:77] + node _T_2414 = cat(UInt<23>("h00"), _T_2413) @[Cat.scala 29:58] + node _T_2415 = bits(io.csr_pkt.csr_mfdc, 0, 0) @[dec_tlu_ctl.scala 2525:37] + node _T_2416 = bits(mfdc, 18, 0) @[dec_tlu_ctl.scala 2525:77] + node _T_2417 = cat(UInt<13>("h00"), _T_2416) @[Cat.scala 29:58] + node _T_2418 = bits(io.csr_pkt.csr_dcsr, 0, 0) @[dec_tlu_ctl.scala 2526:37] + node _T_2419 = bits(io.dcsr, 15, 2) @[dec_tlu_ctl.scala 2526:85] + node _T_2420 = cat(UInt<16>("h04000"), _T_2419) @[Cat.scala 29:58] + node _T_2421 = cat(_T_2420, UInt<2>("h03")) @[Cat.scala 29:58] + node _T_2422 = bits(io.csr_pkt.csr_dpc, 0, 0) @[dec_tlu_ctl.scala 2527:36] + node _T_2423 = cat(io.dpc, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2424 = bits(io.csr_pkt.csr_dicad0, 0, 0) @[dec_tlu_ctl.scala 2528:39] + node _T_2425 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2528:64] + node _T_2426 = bits(io.csr_pkt.csr_dicad0h, 0, 0) @[dec_tlu_ctl.scala 2529:40] + node _T_2427 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2529:65] + node _T_2428 = bits(io.csr_pkt.csr_dicad1, 0, 0) @[dec_tlu_ctl.scala 2530:39] + node _T_2429 = bits(dicad1, 31, 0) @[dec_tlu_ctl.scala 2530:64] + node _T_2430 = bits(io.csr_pkt.csr_dicawics, 0, 0) @[dec_tlu_ctl.scala 2531:41] + node _T_2431 = bits(dicawics, 16, 16) @[dec_tlu_ctl.scala 2531:80] + node _T_2432 = bits(dicawics, 15, 14) @[dec_tlu_ctl.scala 2531:104] + node _T_2433 = bits(dicawics, 13, 0) @[dec_tlu_ctl.scala 2531:131] + node _T_2434 = cat(UInt<3>("h00"), _T_2433) @[Cat.scala 29:58] + node _T_2435 = cat(_T_2434, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2436 = cat(UInt<2>("h00"), _T_2432) @[Cat.scala 29:58] + node _T_2437 = cat(UInt<7>("h00"), _T_2431) @[Cat.scala 29:58] + node _T_2438 = cat(_T_2437, _T_2436) @[Cat.scala 29:58] + node _T_2439 = cat(_T_2438, _T_2435) @[Cat.scala 29:58] + node _T_2440 = bits(io.csr_pkt.csr_mtsel, 0, 0) @[dec_tlu_ctl.scala 2532:38] + node _T_2441 = bits(mtsel, 1, 0) @[dec_tlu_ctl.scala 2532:78] + node _T_2442 = cat(UInt<30>("h00"), _T_2441) @[Cat.scala 29:58] + node _T_2443 = bits(io.csr_pkt.csr_mtdata1, 0, 0) @[dec_tlu_ctl.scala 2533:40] + node _T_2444 = bits(mtdata1_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2533:74] + node _T_2445 = bits(io.csr_pkt.csr_mtdata2, 0, 0) @[dec_tlu_ctl.scala 2534:40] + node _T_2446 = bits(mtdata2_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2534:74] + node _T_2447 = bits(io.csr_pkt.csr_micect, 0, 0) @[dec_tlu_ctl.scala 2535:39] + node _T_2448 = bits(micect, 31, 0) @[dec_tlu_ctl.scala 2535:64] + node _T_2449 = bits(io.csr_pkt.csr_miccmect, 0, 0) @[dec_tlu_ctl.scala 2536:41] + node _T_2450 = bits(miccmect, 31, 0) @[dec_tlu_ctl.scala 2536:66] + node _T_2451 = bits(io.csr_pkt.csr_mdccmect, 0, 0) @[dec_tlu_ctl.scala 2537:41] + node _T_2452 = bits(mdccmect, 31, 0) @[dec_tlu_ctl.scala 2537:66] + node _T_2453 = bits(io.csr_pkt.csr_mhpmc3, 0, 0) @[dec_tlu_ctl.scala 2538:39] + node _T_2454 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2538:64] + node _T_2455 = bits(io.csr_pkt.csr_mhpmc4, 0, 0) @[dec_tlu_ctl.scala 2539:39] + node _T_2456 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2539:64] + node _T_2457 = bits(io.csr_pkt.csr_mhpmc5, 0, 0) @[dec_tlu_ctl.scala 2540:39] + node _T_2458 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2540:64] + node _T_2459 = bits(io.csr_pkt.csr_mhpmc6, 0, 0) @[dec_tlu_ctl.scala 2541:39] + node _T_2460 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2541:64] + node _T_2461 = bits(io.csr_pkt.csr_mhpmc3h, 0, 0) @[dec_tlu_ctl.scala 2542:40] + node _T_2462 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2542:65] + node _T_2463 = bits(io.csr_pkt.csr_mhpmc4h, 0, 0) @[dec_tlu_ctl.scala 2543:40] + node _T_2464 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2543:65] + node _T_2465 = bits(io.csr_pkt.csr_mhpmc5h, 0, 0) @[dec_tlu_ctl.scala 2544:40] + node _T_2466 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2544:65] + node _T_2467 = bits(io.csr_pkt.csr_mhpmc6h, 0, 0) @[dec_tlu_ctl.scala 2545:40] + node _T_2468 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2545:65] + node _T_2469 = bits(io.csr_pkt.csr_mfdht, 0, 0) @[dec_tlu_ctl.scala 2546:38] + node _T_2470 = bits(mfdht, 5, 0) @[dec_tlu_ctl.scala 2546:78] + node _T_2471 = cat(UInt<26>("h00"), _T_2470) @[Cat.scala 29:58] + node _T_2472 = bits(io.csr_pkt.csr_mfdhs, 0, 0) @[dec_tlu_ctl.scala 2547:38] + node _T_2473 = bits(mfdhs, 1, 0) @[dec_tlu_ctl.scala 2547:78] + node _T_2474 = cat(UInt<30>("h00"), _T_2473) @[Cat.scala 29:58] + node _T_2475 = bits(io.csr_pkt.csr_mhpme3, 0, 0) @[dec_tlu_ctl.scala 2548:39] + node _T_2476 = bits(mhpme3, 9, 0) @[dec_tlu_ctl.scala 2548:79] + node _T_2477 = cat(UInt<22>("h00"), _T_2476) @[Cat.scala 29:58] + node _T_2478 = bits(io.csr_pkt.csr_mhpme4, 0, 0) @[dec_tlu_ctl.scala 2549:39] + node _T_2479 = bits(mhpme4, 9, 0) @[dec_tlu_ctl.scala 2549:79] + node _T_2480 = cat(UInt<22>("h00"), _T_2479) @[Cat.scala 29:58] + node _T_2481 = bits(io.csr_pkt.csr_mhpme5, 0, 0) @[dec_tlu_ctl.scala 2550:39] + node _T_2482 = bits(mhpme5, 9, 0) @[dec_tlu_ctl.scala 2550:78] + node _T_2483 = cat(UInt<22>("h00"), _T_2482) @[Cat.scala 29:58] + node _T_2484 = bits(io.csr_pkt.csr_mhpme6, 0, 0) @[dec_tlu_ctl.scala 2551:39] + node _T_2485 = bits(mhpme6, 9, 0) @[dec_tlu_ctl.scala 2551:78] + node _T_2486 = cat(UInt<22>("h00"), _T_2485) @[Cat.scala 29:58] + node _T_2487 = bits(io.csr_pkt.csr_mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2552:46] + node _T_2488 = bits(mcountinhibit, 6, 0) @[dec_tlu_ctl.scala 2552:86] + node _T_2489 = cat(UInt<25>("h00"), _T_2488) @[Cat.scala 29:58] + node _T_2490 = bits(io.csr_pkt.csr_mpmc, 0, 0) @[dec_tlu_ctl.scala 2553:37] + node _T_2491 = cat(UInt<30>("h00"), mpmc) @[Cat.scala 29:58] + node _T_2492 = cat(_T_2491, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2493 = bits(io.dec_timer_read_d, 0, 0) @[dec_tlu_ctl.scala 2554:37] + node _T_2494 = bits(io.dec_timer_rddata_d, 31, 0) @[dec_tlu_ctl.scala 2554:76] + node _T_2495 = mux(_T_2329, UInt<32>("h040001104"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2496 = mux(_T_2330, UInt<32>("h045"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2497 = mux(_T_2331, UInt<32>("h010"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2498 = mux(_T_2332, UInt<32>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2499 = mux(_T_2333, _T_2334, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2500 = mux(_T_2335, _T_2343, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2501 = mux(_T_2344, _T_2348, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2502 = mux(_T_2349, _T_2361, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2503 = mux(_T_2362, _T_2374, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2504 = mux(_T_2375, _T_2376, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2505 = mux(_T_2377, _T_2378, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2506 = mux(_T_2379, _T_2380, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2507 = mux(_T_2381, _T_2382, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2508 = mux(_T_2383, _T_2384, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2509 = mux(_T_2385, _T_2386, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2510 = mux(_T_2387, _T_2388, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2511 = mux(_T_2389, _T_2391, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2512 = mux(_T_2392, _T_2393, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2513 = mux(_T_2394, _T_2395, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2514 = mux(_T_2396, _T_2397, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2515 = mux(_T_2398, _T_2399, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2516 = mux(_T_2400, _T_2402, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2517 = mux(_T_2403, _T_2405, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2518 = mux(_T_2406, _T_2408, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2519 = mux(_T_2409, _T_2411, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2520 = mux(_T_2412, _T_2414, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2521 = mux(_T_2415, _T_2417, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2522 = mux(_T_2418, _T_2421, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2523 = mux(_T_2422, _T_2423, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2524 = mux(_T_2424, _T_2425, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2525 = mux(_T_2426, _T_2427, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2526 = mux(_T_2428, _T_2429, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2527 = mux(_T_2430, _T_2439, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2528 = mux(_T_2440, _T_2442, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2529 = mux(_T_2443, _T_2444, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2530 = mux(_T_2445, _T_2446, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2531 = mux(_T_2447, _T_2448, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2532 = mux(_T_2449, _T_2450, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2533 = mux(_T_2451, _T_2452, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2534 = mux(_T_2453, _T_2454, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2535 = mux(_T_2455, _T_2456, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2536 = mux(_T_2457, _T_2458, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2537 = mux(_T_2459, _T_2460, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2538 = mux(_T_2461, _T_2462, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2539 = mux(_T_2463, _T_2464, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2540 = mux(_T_2465, _T_2466, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2541 = mux(_T_2467, _T_2468, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2542 = mux(_T_2469, _T_2471, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2543 = mux(_T_2472, _T_2474, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2544 = mux(_T_2475, _T_2477, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2545 = mux(_T_2478, _T_2480, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2546 = mux(_T_2481, _T_2483, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2547 = mux(_T_2484, _T_2486, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2548 = mux(_T_2487, _T_2489, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2549 = mux(_T_2490, _T_2492, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2550 = mux(_T_2493, _T_2494, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2551 = or(_T_2495, _T_2496) @[Mux.scala 27:72] + node _T_2552 = or(_T_2551, _T_2497) @[Mux.scala 27:72] + node _T_2553 = or(_T_2552, _T_2498) @[Mux.scala 27:72] + node _T_2554 = or(_T_2553, _T_2499) @[Mux.scala 27:72] + node _T_2555 = or(_T_2554, _T_2500) @[Mux.scala 27:72] + node _T_2556 = or(_T_2555, _T_2501) @[Mux.scala 27:72] + node _T_2557 = or(_T_2556, _T_2502) @[Mux.scala 27:72] + node _T_2558 = or(_T_2557, _T_2503) @[Mux.scala 27:72] + node _T_2559 = or(_T_2558, _T_2504) @[Mux.scala 27:72] + node _T_2560 = or(_T_2559, _T_2505) @[Mux.scala 27:72] + node _T_2561 = or(_T_2560, _T_2506) @[Mux.scala 27:72] node _T_2562 = or(_T_2561, _T_2507) @[Mux.scala 27:72] node _T_2563 = or(_T_2562, _T_2508) @[Mux.scala 27:72] node _T_2564 = or(_T_2563, _T_2509) @[Mux.scala 27:72] @@ -76167,19 +76167,9 @@ circuit quasar_wrapper : node _T_2603 = or(_T_2602, _T_2548) @[Mux.scala 27:72] node _T_2604 = or(_T_2603, _T_2549) @[Mux.scala 27:72] node _T_2605 = or(_T_2604, _T_2550) @[Mux.scala 27:72] - node _T_2606 = or(_T_2605, _T_2551) @[Mux.scala 27:72] - node _T_2607 = or(_T_2606, _T_2552) @[Mux.scala 27:72] - node _T_2608 = or(_T_2607, _T_2553) @[Mux.scala 27:72] - node _T_2609 = or(_T_2608, _T_2554) @[Mux.scala 27:72] - node _T_2610 = or(_T_2609, _T_2555) @[Mux.scala 27:72] - node _T_2611 = or(_T_2610, _T_2556) @[Mux.scala 27:72] - node _T_2612 = or(_T_2611, _T_2557) @[Mux.scala 27:72] - node _T_2613 = or(_T_2612, _T_2558) @[Mux.scala 27:72] - node _T_2614 = or(_T_2613, _T_2559) @[Mux.scala 27:72] - node _T_2615 = or(_T_2614, _T_2560) @[Mux.scala 27:72] - wire _T_2616 : UInt @[Mux.scala 27:72] - _T_2616 <= _T_2615 @[Mux.scala 27:72] - io.dec_csr_rddata_d <= _T_2616 @[dec_tlu_ctl.scala 2498:21] + wire _T_2606 : UInt @[Mux.scala 27:72] + _T_2606 <= _T_2605 @[Mux.scala 27:72] + io.dec_csr_rddata_d <= _T_2606 @[dec_tlu_ctl.scala 2498:21] module dec_decode_csr_read : input clock : Clock @@ -109305,26 +109295,26 @@ circuit quasar_wrapper : wire buf_rst : UInt<1> buf_rst <= UInt<1>("h00") - buf_rst <= UInt<1>("h00") @[axi4_to_ahb.scala 28:11] - io.ahb.out.htrans <= UInt<1>("h00") @[axi4_to_ahb.scala 29:21] + buf_rst <= UInt<1>("h00") @[axi4_to_ahb.scala 21:11] + io.ahb.out.htrans <= UInt<1>("h00") @[axi4_to_ahb.scala 22:21] wire buf_state_en : UInt<1> buf_state_en <= UInt<1>("h00") - wire ahbm_clk : Clock @[axi4_to_ahb.scala 31:22] - wire ahbm_addr_clk : Clock @[axi4_to_ahb.scala 32:27] - wire ahbm_data_clk : Clock @[axi4_to_ahb.scala 33:27] + wire ahbm_clk : Clock @[axi4_to_ahb.scala 24:22] + wire ahbm_addr_clk : Clock @[axi4_to_ahb.scala 25:27] + wire ahbm_data_clk : Clock @[axi4_to_ahb.scala 26:27] wire buf_state : UInt<3> buf_state <= UInt<3>("h00") wire buf_nxtstate : UInt<3> buf_nxtstate <= UInt<3>("h00") - node _T = bits(buf_state_en, 0, 0) @[axi4_to_ahb.scala 37:70] - node _T_1 = mux(_T, buf_nxtstate, buf_state) @[axi4_to_ahb.scala 37:50] - node _T_2 = eq(buf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 37:108] + node _T = bits(buf_state_en, 0, 0) @[axi4_to_ahb.scala 30:70] + node _T_1 = mux(_T, buf_nxtstate, buf_state) @[axi4_to_ahb.scala 30:50] + node _T_2 = eq(buf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 30:108] node _T_3 = bits(_T_2, 0, 0) @[Bitwise.scala 72:15] node _T_4 = mux(_T_3, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_5 = and(_T_1, _T_4) @[axi4_to_ahb.scala 37:98] - reg _T_6 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 37:45] - _T_6 <= _T_5 @[axi4_to_ahb.scala 37:45] - buf_state <= _T_6 @[axi4_to_ahb.scala 37:13] + node _T_5 = and(_T_1, _T_4) @[axi4_to_ahb.scala 30:98] + reg _T_6 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 30:45] + _T_6 <= _T_5 @[axi4_to_ahb.scala 30:45] + buf_state <= _T_6 @[axi4_to_ahb.scala 30:13] wire slave_valid : UInt<1> slave_valid <= UInt<1>("h00") wire slave_ready : UInt<1> @@ -109359,8 +109349,8 @@ circuit quasar_wrapper : wrbuf_byteen <= UInt<8>("h00") wire bus_write_clk_en : UInt<1> bus_write_clk_en <= UInt<1>("h00") - wire bus_clk : Clock @[axi4_to_ahb.scala 57:21] - wire bus_write_clk : Clock @[axi4_to_ahb.scala 58:27] + wire bus_clk : Clock @[axi4_to_ahb.scala 50:21] + wire bus_write_clk : Clock @[axi4_to_ahb.scala 51:27] wire master_valid : UInt<1> master_valid <= UInt<1>("h00") wire master_ready : UInt<1> @@ -109469,125 +109459,125 @@ circuit quasar_wrapper : ahbm_addr_clken <= UInt<1>("h00") wire ahbm_data_clken : UInt<1> ahbm_data_clken <= UInt<1>("h00") - wire buf_clk : Clock @[axi4_to_ahb.scala 125:21] - node _T_7 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 146:27] - wr_cmd_vld <= _T_7 @[axi4_to_ahb.scala 146:14] - node _T_8 = or(wr_cmd_vld, io.axi.ar.valid) @[axi4_to_ahb.scala 147:30] - master_valid <= _T_8 @[axi4_to_ahb.scala 147:16] - node _T_9 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 148:38] - node _T_10 = bits(wrbuf_tag, 0, 0) @[axi4_to_ahb.scala 148:51] - node _T_11 = bits(io.axi.ar.bits.id, 0, 0) @[axi4_to_ahb.scala 148:82] - node _T_12 = mux(_T_9, _T_10, _T_11) @[axi4_to_ahb.scala 148:20] - master_tag <= _T_12 @[axi4_to_ahb.scala 148:14] - node _T_13 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 149:38] - node _T_14 = mux(_T_13, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 149:20] - master_opc <= _T_14 @[axi4_to_ahb.scala 149:14] - node _T_15 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 150:39] - node _T_16 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 150:53] - node _T_17 = bits(io.axi.ar.bits.addr, 31, 0) @[axi4_to_ahb.scala 150:81] - node _T_18 = mux(_T_15, _T_16, _T_17) @[axi4_to_ahb.scala 150:21] - master_addr <= _T_18 @[axi4_to_ahb.scala 150:15] - node _T_19 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 151:39] - node _T_20 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 151:53] - node _T_21 = bits(io.axi.ar.bits.size, 2, 0) @[axi4_to_ahb.scala 151:80] - node _T_22 = mux(_T_19, _T_20, _T_21) @[axi4_to_ahb.scala 151:21] - master_size <= _T_22 @[axi4_to_ahb.scala 151:15] - node _T_23 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 152:32] - master_byteen <= _T_23 @[axi4_to_ahb.scala 152:17] - node _T_24 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 153:29] - master_wdata <= _T_24 @[axi4_to_ahb.scala 153:16] - node _T_25 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 156:33] - node _T_26 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 156:58] - node _T_27 = and(_T_25, _T_26) @[axi4_to_ahb.scala 156:47] - io.axi.b.valid <= _T_27 @[axi4_to_ahb.scala 156:18] - node _T_28 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 157:38] - node _T_29 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 157:65] - node _T_30 = mux(_T_29, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 157:55] - node _T_31 = mux(_T_28, UInt<2>("h02"), _T_30) @[axi4_to_ahb.scala 157:28] - io.axi.b.bits.resp <= _T_31 @[axi4_to_ahb.scala 157:22] - node _T_32 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 158:32] - io.axi.b.bits.id <= _T_32 @[axi4_to_ahb.scala 158:20] - node _T_33 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 160:33] - node _T_34 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 160:59] - node _T_35 = eq(_T_34, UInt<1>("h00")) @[axi4_to_ahb.scala 160:66] - node _T_36 = and(_T_33, _T_35) @[axi4_to_ahb.scala 160:47] - io.axi.r.valid <= _T_36 @[axi4_to_ahb.scala 160:18] - node _T_37 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 161:38] - node _T_38 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 161:65] - node _T_39 = mux(_T_38, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 161:55] - node _T_40 = mux(_T_37, UInt<2>("h02"), _T_39) @[axi4_to_ahb.scala 161:28] - io.axi.r.bits.resp <= _T_40 @[axi4_to_ahb.scala 161:22] - node _T_41 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 162:32] - io.axi.r.bits.id <= _T_41 @[axi4_to_ahb.scala 162:20] - node _T_42 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 163:36] - io.axi.r.bits.data <= _T_42 @[axi4_to_ahb.scala 163:22] - node _T_43 = and(io.axi.b.ready, io.axi.r.ready) @[axi4_to_ahb.scala 164:33] - slave_ready <= _T_43 @[axi4_to_ahb.scala 164:15] - node _T_44 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 167:57] - node _T_45 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 167:94] - node _T_46 = or(_T_44, _T_45) @[axi4_to_ahb.scala 167:76] - node _T_47 = and(io.bus_clk_en, _T_46) @[axi4_to_ahb.scala 167:37] - bus_write_clk_en <= _T_47 @[axi4_to_ahb.scala 167:20] + wire buf_clk : Clock @[axi4_to_ahb.scala 118:21] + node _T_7 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 139:27] + wr_cmd_vld <= _T_7 @[axi4_to_ahb.scala 139:14] + node _T_8 = or(wr_cmd_vld, io.axi.ar.valid) @[axi4_to_ahb.scala 140:30] + master_valid <= _T_8 @[axi4_to_ahb.scala 140:16] + node _T_9 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 141:38] + node _T_10 = bits(wrbuf_tag, 0, 0) @[axi4_to_ahb.scala 141:51] + node _T_11 = bits(io.axi.ar.bits.id, 0, 0) @[axi4_to_ahb.scala 141:82] + node _T_12 = mux(_T_9, _T_10, _T_11) @[axi4_to_ahb.scala 141:20] + master_tag <= _T_12 @[axi4_to_ahb.scala 141:14] + node _T_13 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 142:38] + node _T_14 = mux(_T_13, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 142:20] + master_opc <= _T_14 @[axi4_to_ahb.scala 142:14] + node _T_15 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 143:39] + node _T_16 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 143:53] + node _T_17 = bits(io.axi.ar.bits.addr, 31, 0) @[axi4_to_ahb.scala 143:81] + node _T_18 = mux(_T_15, _T_16, _T_17) @[axi4_to_ahb.scala 143:21] + master_addr <= _T_18 @[axi4_to_ahb.scala 143:15] + node _T_19 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 144:39] + node _T_20 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 144:53] + node _T_21 = bits(io.axi.ar.bits.size, 2, 0) @[axi4_to_ahb.scala 144:80] + node _T_22 = mux(_T_19, _T_20, _T_21) @[axi4_to_ahb.scala 144:21] + master_size <= _T_22 @[axi4_to_ahb.scala 144:15] + node _T_23 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 145:32] + master_byteen <= _T_23 @[axi4_to_ahb.scala 145:17] + node _T_24 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 146:29] + master_wdata <= _T_24 @[axi4_to_ahb.scala 146:16] + node _T_25 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 149:33] + node _T_26 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 149:58] + node _T_27 = and(_T_25, _T_26) @[axi4_to_ahb.scala 149:47] + io.axi.b.valid <= _T_27 @[axi4_to_ahb.scala 149:18] + node _T_28 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 150:38] + node _T_29 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 150:65] + node _T_30 = mux(_T_29, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 150:55] + node _T_31 = mux(_T_28, UInt<2>("h02"), _T_30) @[axi4_to_ahb.scala 150:28] + io.axi.b.bits.resp <= _T_31 @[axi4_to_ahb.scala 150:22] + node _T_32 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 151:32] + io.axi.b.bits.id <= _T_32 @[axi4_to_ahb.scala 151:20] + node _T_33 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 153:33] + node _T_34 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 153:59] + node _T_35 = eq(_T_34, UInt<1>("h00")) @[axi4_to_ahb.scala 153:66] + node _T_36 = and(_T_33, _T_35) @[axi4_to_ahb.scala 153:47] + io.axi.r.valid <= _T_36 @[axi4_to_ahb.scala 153:18] + node _T_37 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 154:38] + node _T_38 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 154:65] + node _T_39 = mux(_T_38, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 154:55] + node _T_40 = mux(_T_37, UInt<2>("h02"), _T_39) @[axi4_to_ahb.scala 154:28] + io.axi.r.bits.resp <= _T_40 @[axi4_to_ahb.scala 154:22] + node _T_41 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 155:32] + io.axi.r.bits.id <= _T_41 @[axi4_to_ahb.scala 155:20] + node _T_42 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 156:36] + io.axi.r.bits.data <= _T_42 @[axi4_to_ahb.scala 156:22] + node _T_43 = and(io.axi.b.ready, io.axi.r.ready) @[axi4_to_ahb.scala 157:33] + slave_ready <= _T_43 @[axi4_to_ahb.scala 157:15] + node _T_44 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 160:57] + node _T_45 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 160:94] + node _T_46 = or(_T_44, _T_45) @[axi4_to_ahb.scala 160:76] + node _T_47 = and(io.bus_clk_en, _T_46) @[axi4_to_ahb.scala 160:37] + bus_write_clk_en <= _T_47 @[axi4_to_ahb.scala 160:20] inst rvclkhdr of rvclkhdr_849 @[lib.scala 343:22] rvclkhdr.clock <= clock rvclkhdr.reset <= reset rvclkhdr.io.clk <= clock @[lib.scala 344:17] rvclkhdr.io.en <= io.bus_clk_en @[lib.scala 345:16] rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - bus_clk <= rvclkhdr.io.l1clk @[axi4_to_ahb.scala 169:11] - node _T_48 = bits(bus_write_clk_en, 0, 0) @[axi4_to_ahb.scala 170:59] + bus_clk <= rvclkhdr.io.l1clk @[axi4_to_ahb.scala 162:11] + node _T_48 = bits(bus_write_clk_en, 0, 0) @[axi4_to_ahb.scala 163:59] inst rvclkhdr_1 of rvclkhdr_850 @[lib.scala 343:22] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] rvclkhdr_1.io.en <= _T_48 @[lib.scala 345:16] rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - bus_write_clk <= rvclkhdr_1.io.l1clk @[axi4_to_ahb.scala 170:17] + bus_write_clk <= rvclkhdr_1.io.l1clk @[axi4_to_ahb.scala 163:17] node _T_49 = eq(UInt<3>("h00"), buf_state) @[Conditional.scala 37:30] when _T_49 : @[Conditional.scala 40:58] - master_ready <= UInt<1>("h01") @[axi4_to_ahb.scala 174:20] - node _T_50 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 175:34] - node _T_51 = eq(_T_50, UInt<1>("h01")) @[axi4_to_ahb.scala 175:41] - buf_write_in <= _T_51 @[axi4_to_ahb.scala 175:20] - node _T_52 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 176:46] - node _T_53 = mux(_T_52, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 176:26] - buf_nxtstate <= _T_53 @[axi4_to_ahb.scala 176:20] - node _T_54 = and(master_valid, UInt<1>("h01")) @[axi4_to_ahb.scala 177:36] - buf_state_en <= _T_54 @[axi4_to_ahb.scala 177:20] - buf_wr_en <= buf_state_en @[axi4_to_ahb.scala 178:17] - node _T_55 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 179:54] - node _T_56 = and(buf_state_en, _T_55) @[axi4_to_ahb.scala 179:38] - buf_data_wr_en <= _T_56 @[axi4_to_ahb.scala 179:22] - buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 180:27] - node _T_57 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 182:50] - node _T_58 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 182:94] - node _T_59 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 142:52] - node _T_60 = tail(_T_59, 1) @[axi4_to_ahb.scala 142:52] - node _T_61 = mux(UInt<1>("h00"), _T_60, UInt<3>("h00")) @[axi4_to_ahb.scala 142:24] - node _T_62 = bits(_T_58, 0, 0) @[axi4_to_ahb.scala 143:44] - node _T_63 = geq(UInt<1>("h00"), _T_61) @[axi4_to_ahb.scala 143:62] - node _T_64 = and(_T_62, _T_63) @[axi4_to_ahb.scala 143:48] - node _T_65 = bits(_T_58, 1, 1) @[axi4_to_ahb.scala 143:44] - node _T_66 = geq(UInt<1>("h01"), _T_61) @[axi4_to_ahb.scala 143:62] - node _T_67 = and(_T_65, _T_66) @[axi4_to_ahb.scala 143:48] - node _T_68 = bits(_T_58, 2, 2) @[axi4_to_ahb.scala 143:44] - node _T_69 = geq(UInt<2>("h02"), _T_61) @[axi4_to_ahb.scala 143:62] - node _T_70 = and(_T_68, _T_69) @[axi4_to_ahb.scala 143:48] - node _T_71 = bits(_T_58, 3, 3) @[axi4_to_ahb.scala 143:44] - node _T_72 = geq(UInt<2>("h03"), _T_61) @[axi4_to_ahb.scala 143:62] - node _T_73 = and(_T_71, _T_72) @[axi4_to_ahb.scala 143:48] - node _T_74 = bits(_T_58, 4, 4) @[axi4_to_ahb.scala 143:44] - node _T_75 = geq(UInt<3>("h04"), _T_61) @[axi4_to_ahb.scala 143:62] - node _T_76 = and(_T_74, _T_75) @[axi4_to_ahb.scala 143:48] - node _T_77 = bits(_T_58, 5, 5) @[axi4_to_ahb.scala 143:44] - node _T_78 = geq(UInt<3>("h05"), _T_61) @[axi4_to_ahb.scala 143:62] - node _T_79 = and(_T_77, _T_78) @[axi4_to_ahb.scala 143:48] - node _T_80 = bits(_T_58, 6, 6) @[axi4_to_ahb.scala 143:44] - node _T_81 = geq(UInt<3>("h06"), _T_61) @[axi4_to_ahb.scala 143:62] - node _T_82 = and(_T_80, _T_81) @[axi4_to_ahb.scala 143:48] - node _T_83 = bits(_T_58, 7, 7) @[axi4_to_ahb.scala 143:44] - node _T_84 = geq(UInt<3>("h07"), _T_61) @[axi4_to_ahb.scala 143:62] - node _T_85 = and(_T_83, _T_84) @[axi4_to_ahb.scala 143:48] + master_ready <= UInt<1>("h01") @[axi4_to_ahb.scala 167:20] + node _T_50 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 168:34] + node _T_51 = eq(_T_50, UInt<1>("h01")) @[axi4_to_ahb.scala 168:41] + buf_write_in <= _T_51 @[axi4_to_ahb.scala 168:20] + node _T_52 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 169:46] + node _T_53 = mux(_T_52, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 169:26] + buf_nxtstate <= _T_53 @[axi4_to_ahb.scala 169:20] + node _T_54 = and(master_valid, UInt<1>("h01")) @[axi4_to_ahb.scala 170:36] + buf_state_en <= _T_54 @[axi4_to_ahb.scala 170:20] + buf_wr_en <= buf_state_en @[axi4_to_ahb.scala 171:17] + node _T_55 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 172:54] + node _T_56 = and(buf_state_en, _T_55) @[axi4_to_ahb.scala 172:38] + buf_data_wr_en <= _T_56 @[axi4_to_ahb.scala 172:22] + buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 173:27] + node _T_57 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 175:50] + node _T_58 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 175:94] + node _T_59 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] + node _T_60 = tail(_T_59, 1) @[axi4_to_ahb.scala 135:52] + node _T_61 = mux(UInt<1>("h00"), _T_60, UInt<3>("h00")) @[axi4_to_ahb.scala 135:24] + node _T_62 = bits(_T_58, 0, 0) @[axi4_to_ahb.scala 136:44] + node _T_63 = geq(UInt<1>("h00"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_64 = and(_T_62, _T_63) @[axi4_to_ahb.scala 136:48] + node _T_65 = bits(_T_58, 1, 1) @[axi4_to_ahb.scala 136:44] + node _T_66 = geq(UInt<1>("h01"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_67 = and(_T_65, _T_66) @[axi4_to_ahb.scala 136:48] + node _T_68 = bits(_T_58, 2, 2) @[axi4_to_ahb.scala 136:44] + node _T_69 = geq(UInt<2>("h02"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_70 = and(_T_68, _T_69) @[axi4_to_ahb.scala 136:48] + node _T_71 = bits(_T_58, 3, 3) @[axi4_to_ahb.scala 136:44] + node _T_72 = geq(UInt<2>("h03"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_73 = and(_T_71, _T_72) @[axi4_to_ahb.scala 136:48] + node _T_74 = bits(_T_58, 4, 4) @[axi4_to_ahb.scala 136:44] + node _T_75 = geq(UInt<3>("h04"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_76 = and(_T_74, _T_75) @[axi4_to_ahb.scala 136:48] + node _T_77 = bits(_T_58, 5, 5) @[axi4_to_ahb.scala 136:44] + node _T_78 = geq(UInt<3>("h05"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_79 = and(_T_77, _T_78) @[axi4_to_ahb.scala 136:48] + node _T_80 = bits(_T_58, 6, 6) @[axi4_to_ahb.scala 136:44] + node _T_81 = geq(UInt<3>("h06"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_82 = and(_T_80, _T_81) @[axi4_to_ahb.scala 136:48] + node _T_83 = bits(_T_58, 7, 7) @[axi4_to_ahb.scala 136:44] + node _T_84 = geq(UInt<3>("h07"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_85 = and(_T_83, _T_84) @[axi4_to_ahb.scala 136:48] node _T_86 = mux(_T_85, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_87 = mux(_T_82, UInt<3>("h06"), _T_86) @[Mux.scala 98:16] node _T_88 = mux(_T_79, UInt<3>("h05"), _T_87) @[Mux.scala 98:16] @@ -109596,193 +109586,193 @@ circuit quasar_wrapper : node _T_91 = mux(_T_70, UInt<2>("h02"), _T_90) @[Mux.scala 98:16] node _T_92 = mux(_T_67, UInt<1>("h01"), _T_91) @[Mux.scala 98:16] node _T_93 = mux(_T_64, UInt<1>("h00"), _T_92) @[Mux.scala 98:16] - node _T_94 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 182:124] - node _T_95 = mux(_T_57, _T_93, _T_94) @[axi4_to_ahb.scala 182:30] - buf_cmd_byte_ptr <= _T_95 @[axi4_to_ahb.scala 182:24] - bypass_en <= buf_state_en @[axi4_to_ahb.scala 183:17] - node _T_96 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 184:51] - node _T_97 = and(bypass_en, _T_96) @[axi4_to_ahb.scala 184:35] - rd_bypass_idle <= _T_97 @[axi4_to_ahb.scala 184:22] + node _T_94 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 175:124] + node _T_95 = mux(_T_57, _T_93, _T_94) @[axi4_to_ahb.scala 175:30] + buf_cmd_byte_ptr <= _T_95 @[axi4_to_ahb.scala 175:24] + bypass_en <= buf_state_en @[axi4_to_ahb.scala 176:17] + node _T_96 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 177:51] + node _T_97 = and(bypass_en, _T_96) @[axi4_to_ahb.scala 177:35] + rd_bypass_idle <= _T_97 @[axi4_to_ahb.scala 177:22] node _T_98 = bits(bypass_en, 0, 0) @[Bitwise.scala 72:15] node _T_99 = mux(_T_98, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_100 = and(_T_99, UInt<2>("h02")) @[axi4_to_ahb.scala 185:49] - io.ahb.out.htrans <= _T_100 @[axi4_to_ahb.scala 185:25] + node _T_100 = and(_T_99, UInt<2>("h02")) @[axi4_to_ahb.scala 178:49] + io.ahb.out.htrans <= _T_100 @[axi4_to_ahb.scala 178:25] skip @[Conditional.scala 40:58] else : @[Conditional.scala 39:67] node _T_101 = eq(UInt<3>("h01"), buf_state) @[Conditional.scala 37:30] when _T_101 : @[Conditional.scala 39:67] - node _T_102 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 189:54] - node _T_103 = eq(_T_102, UInt<1>("h00")) @[axi4_to_ahb.scala 189:61] - node _T_104 = and(master_valid, _T_103) @[axi4_to_ahb.scala 189:41] - node _T_105 = bits(_T_104, 0, 0) @[axi4_to_ahb.scala 189:82] - node _T_106 = mux(_T_105, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 189:26] - buf_nxtstate <= _T_106 @[axi4_to_ahb.scala 189:20] - node _T_107 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 190:51] - node _T_108 = neq(_T_107, UInt<1>("h00")) @[axi4_to_ahb.scala 190:58] - node _T_109 = and(ahb_hready_q, _T_108) @[axi4_to_ahb.scala 190:36] - node _T_110 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 190:72] - node _T_111 = and(_T_109, _T_110) @[axi4_to_ahb.scala 190:70] - buf_state_en <= _T_111 @[axi4_to_ahb.scala 190:20] - node _T_112 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 191:34] - node _T_113 = and(buf_state_en, _T_112) @[axi4_to_ahb.scala 191:32] - cmd_done <= _T_113 @[axi4_to_ahb.scala 191:16] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 192:20] - node _T_114 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 193:52] - node _T_115 = neq(_T_114, UInt<1>("h00")) @[axi4_to_ahb.scala 193:59] - node _T_116 = and(ahb_hready_q, _T_115) @[axi4_to_ahb.scala 193:37] - node _T_117 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 193:73] - node _T_118 = and(_T_116, _T_117) @[axi4_to_ahb.scala 193:71] - node _T_119 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 193:122] - node _T_120 = eq(_T_119, UInt<1>("h00")) @[axi4_to_ahb.scala 193:129] - node _T_121 = and(master_valid, _T_120) @[axi4_to_ahb.scala 193:109] - node _T_122 = bits(_T_121, 0, 0) @[axi4_to_ahb.scala 193:150] - node _T_123 = mux(_T_122, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 193:94] - node _T_124 = eq(_T_123, UInt<3>("h06")) @[axi4_to_ahb.scala 193:174] - node _T_125 = and(_T_118, _T_124) @[axi4_to_ahb.scala 193:88] - master_ready <= _T_125 @[axi4_to_ahb.scala 193:20] - buf_wr_en <= master_ready @[axi4_to_ahb.scala 194:17] - node _T_126 = and(master_ready, master_valid) @[axi4_to_ahb.scala 195:33] - bypass_en <= _T_126 @[axi4_to_ahb.scala 195:17] - node _T_127 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 196:47] - node _T_128 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 196:62] - node _T_129 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 196:78] - node _T_130 = mux(_T_127, _T_128, _T_129) @[axi4_to_ahb.scala 196:30] - buf_cmd_byte_ptr <= _T_130 @[axi4_to_ahb.scala 196:24] - node _T_131 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 197:48] - node _T_132 = or(_T_131, bypass_en) @[axi4_to_ahb.scala 197:62] + node _T_102 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 182:54] + node _T_103 = eq(_T_102, UInt<1>("h00")) @[axi4_to_ahb.scala 182:61] + node _T_104 = and(master_valid, _T_103) @[axi4_to_ahb.scala 182:41] + node _T_105 = bits(_T_104, 0, 0) @[axi4_to_ahb.scala 182:82] + node _T_106 = mux(_T_105, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 182:26] + buf_nxtstate <= _T_106 @[axi4_to_ahb.scala 182:20] + node _T_107 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 183:51] + node _T_108 = neq(_T_107, UInt<1>("h00")) @[axi4_to_ahb.scala 183:58] + node _T_109 = and(ahb_hready_q, _T_108) @[axi4_to_ahb.scala 183:36] + node _T_110 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 183:72] + node _T_111 = and(_T_109, _T_110) @[axi4_to_ahb.scala 183:70] + buf_state_en <= _T_111 @[axi4_to_ahb.scala 183:20] + node _T_112 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 184:34] + node _T_113 = and(buf_state_en, _T_112) @[axi4_to_ahb.scala 184:32] + cmd_done <= _T_113 @[axi4_to_ahb.scala 184:16] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 185:20] + node _T_114 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 186:52] + node _T_115 = neq(_T_114, UInt<1>("h00")) @[axi4_to_ahb.scala 186:59] + node _T_116 = and(ahb_hready_q, _T_115) @[axi4_to_ahb.scala 186:37] + node _T_117 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 186:73] + node _T_118 = and(_T_116, _T_117) @[axi4_to_ahb.scala 186:71] + node _T_119 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 186:122] + node _T_120 = eq(_T_119, UInt<1>("h00")) @[axi4_to_ahb.scala 186:129] + node _T_121 = and(master_valid, _T_120) @[axi4_to_ahb.scala 186:109] + node _T_122 = bits(_T_121, 0, 0) @[axi4_to_ahb.scala 186:150] + node _T_123 = mux(_T_122, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 186:94] + node _T_124 = eq(_T_123, UInt<3>("h06")) @[axi4_to_ahb.scala 186:174] + node _T_125 = and(_T_118, _T_124) @[axi4_to_ahb.scala 186:88] + master_ready <= _T_125 @[axi4_to_ahb.scala 186:20] + buf_wr_en <= master_ready @[axi4_to_ahb.scala 187:17] + node _T_126 = and(master_ready, master_valid) @[axi4_to_ahb.scala 188:33] + bypass_en <= _T_126 @[axi4_to_ahb.scala 188:17] + node _T_127 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 189:47] + node _T_128 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 189:62] + node _T_129 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 189:78] + node _T_130 = mux(_T_127, _T_128, _T_129) @[axi4_to_ahb.scala 189:30] + buf_cmd_byte_ptr <= _T_130 @[axi4_to_ahb.scala 189:24] + node _T_131 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 190:48] + node _T_132 = or(_T_131, bypass_en) @[axi4_to_ahb.scala 190:62] node _T_133 = bits(_T_132, 0, 0) @[Bitwise.scala 72:15] node _T_134 = mux(_T_133, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_135 = and(UInt<2>("h02"), _T_134) @[axi4_to_ahb.scala 197:36] - io.ahb.out.htrans <= _T_135 @[axi4_to_ahb.scala 197:25] + node _T_135 = and(UInt<2>("h02"), _T_134) @[axi4_to_ahb.scala 190:36] + io.ahb.out.htrans <= _T_135 @[axi4_to_ahb.scala 190:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_136 = eq(UInt<3>("h06"), buf_state) @[Conditional.scala 37:30] when _T_136 : @[Conditional.scala 39:67] - node _T_137 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 201:39] - node _T_138 = and(ahb_hready_q, _T_137) @[axi4_to_ahb.scala 201:37] - node _T_139 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 201:82] - node _T_140 = eq(_T_139, UInt<1>("h01")) @[axi4_to_ahb.scala 201:89] - node _T_141 = and(master_valid, _T_140) @[axi4_to_ahb.scala 201:70] - node _T_142 = not(_T_141) @[axi4_to_ahb.scala 201:55] - node _T_143 = and(_T_138, _T_142) @[axi4_to_ahb.scala 201:53] - master_ready <= _T_143 @[axi4_to_ahb.scala 201:20] - node _T_144 = and(master_valid, master_ready) @[axi4_to_ahb.scala 202:34] - node _T_145 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 202:62] - node _T_146 = eq(_T_145, UInt<1>("h00")) @[axi4_to_ahb.scala 202:69] - node _T_147 = and(_T_144, _T_146) @[axi4_to_ahb.scala 202:49] - buf_wr_en <= _T_147 @[axi4_to_ahb.scala 202:17] - node _T_148 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 203:45] - node _T_149 = and(master_valid, master_ready) @[axi4_to_ahb.scala 203:82] - node _T_150 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 203:110] - node _T_151 = eq(_T_150, UInt<1>("h00")) @[axi4_to_ahb.scala 203:117] - node _T_152 = and(_T_149, _T_151) @[axi4_to_ahb.scala 203:97] - node _T_153 = bits(_T_152, 0, 0) @[axi4_to_ahb.scala 203:138] - node _T_154 = mux(_T_153, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 203:67] - node _T_155 = mux(_T_148, UInt<3>("h07"), _T_154) @[axi4_to_ahb.scala 203:26] - buf_nxtstate <= _T_155 @[axi4_to_ahb.scala 203:20] - node _T_156 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 204:37] - buf_state_en <= _T_156 @[axi4_to_ahb.scala 204:20] - buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 205:22] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 206:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 207:23] - node _T_157 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 208:41] - node _T_158 = and(buf_state_en, _T_157) @[axi4_to_ahb.scala 208:39] - slave_valid_pre <= _T_158 @[axi4_to_ahb.scala 208:23] - node _T_159 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 209:34] - node _T_160 = and(buf_state_en, _T_159) @[axi4_to_ahb.scala 209:32] - cmd_done <= _T_160 @[axi4_to_ahb.scala 209:16] - node _T_161 = and(master_ready, master_valid) @[axi4_to_ahb.scala 210:33] - node _T_162 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 210:64] - node _T_163 = and(_T_161, _T_162) @[axi4_to_ahb.scala 210:48] - node _T_164 = and(_T_163, buf_state_en) @[axi4_to_ahb.scala 210:79] - bypass_en <= _T_164 @[axi4_to_ahb.scala 210:17] - node _T_165 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 211:47] - node _T_166 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 211:62] - node _T_167 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 211:78] - node _T_168 = mux(_T_165, _T_166, _T_167) @[axi4_to_ahb.scala 211:30] - buf_cmd_byte_ptr <= _T_168 @[axi4_to_ahb.scala 211:24] - node _T_169 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 212:63] - node _T_170 = and(_T_169, buf_state_en) @[axi4_to_ahb.scala 212:78] - node _T_171 = eq(_T_170, UInt<1>("h00")) @[axi4_to_ahb.scala 212:47] + node _T_137 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 194:39] + node _T_138 = and(ahb_hready_q, _T_137) @[axi4_to_ahb.scala 194:37] + node _T_139 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 194:82] + node _T_140 = eq(_T_139, UInt<1>("h01")) @[axi4_to_ahb.scala 194:89] + node _T_141 = and(master_valid, _T_140) @[axi4_to_ahb.scala 194:70] + node _T_142 = not(_T_141) @[axi4_to_ahb.scala 194:55] + node _T_143 = and(_T_138, _T_142) @[axi4_to_ahb.scala 194:53] + master_ready <= _T_143 @[axi4_to_ahb.scala 194:20] + node _T_144 = and(master_valid, master_ready) @[axi4_to_ahb.scala 195:34] + node _T_145 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 195:62] + node _T_146 = eq(_T_145, UInt<1>("h00")) @[axi4_to_ahb.scala 195:69] + node _T_147 = and(_T_144, _T_146) @[axi4_to_ahb.scala 195:49] + buf_wr_en <= _T_147 @[axi4_to_ahb.scala 195:17] + node _T_148 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 196:45] + node _T_149 = and(master_valid, master_ready) @[axi4_to_ahb.scala 196:82] + node _T_150 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 196:110] + node _T_151 = eq(_T_150, UInt<1>("h00")) @[axi4_to_ahb.scala 196:117] + node _T_152 = and(_T_149, _T_151) @[axi4_to_ahb.scala 196:97] + node _T_153 = bits(_T_152, 0, 0) @[axi4_to_ahb.scala 196:138] + node _T_154 = mux(_T_153, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 196:67] + node _T_155 = mux(_T_148, UInt<3>("h07"), _T_154) @[axi4_to_ahb.scala 196:26] + buf_nxtstate <= _T_155 @[axi4_to_ahb.scala 196:20] + node _T_156 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 197:37] + buf_state_en <= _T_156 @[axi4_to_ahb.scala 197:20] + buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 198:22] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 199:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 200:23] + node _T_157 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 201:41] + node _T_158 = and(buf_state_en, _T_157) @[axi4_to_ahb.scala 201:39] + slave_valid_pre <= _T_158 @[axi4_to_ahb.scala 201:23] + node _T_159 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 202:34] + node _T_160 = and(buf_state_en, _T_159) @[axi4_to_ahb.scala 202:32] + cmd_done <= _T_160 @[axi4_to_ahb.scala 202:16] + node _T_161 = and(master_ready, master_valid) @[axi4_to_ahb.scala 203:33] + node _T_162 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 203:64] + node _T_163 = and(_T_161, _T_162) @[axi4_to_ahb.scala 203:48] + node _T_164 = and(_T_163, buf_state_en) @[axi4_to_ahb.scala 203:79] + bypass_en <= _T_164 @[axi4_to_ahb.scala 203:17] + node _T_165 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 204:47] + node _T_166 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 204:62] + node _T_167 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 204:78] + node _T_168 = mux(_T_165, _T_166, _T_167) @[axi4_to_ahb.scala 204:30] + buf_cmd_byte_ptr <= _T_168 @[axi4_to_ahb.scala 204:24] + node _T_169 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 205:63] + node _T_170 = and(_T_169, buf_state_en) @[axi4_to_ahb.scala 205:78] + node _T_171 = eq(_T_170, UInt<1>("h00")) @[axi4_to_ahb.scala 205:47] node _T_172 = bits(_T_171, 0, 0) @[Bitwise.scala 72:15] node _T_173 = mux(_T_172, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_174 = and(UInt<2>("h02"), _T_173) @[axi4_to_ahb.scala 212:36] - io.ahb.out.htrans <= _T_174 @[axi4_to_ahb.scala 212:25] - slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 213:20] + node _T_174 = and(UInt<2>("h02"), _T_173) @[axi4_to_ahb.scala 205:36] + io.ahb.out.htrans <= _T_174 @[axi4_to_ahb.scala 205:25] + slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 206:20] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_175 = eq(UInt<3>("h07"), buf_state) @[Conditional.scala 37:30] when _T_175 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 217:20] - node _T_176 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 218:51] - node _T_177 = neq(_T_176, UInt<1>("h00")) @[axi4_to_ahb.scala 218:58] - node _T_178 = and(ahb_hready_q, _T_177) @[axi4_to_ahb.scala 218:36] - node _T_179 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 218:72] - node _T_180 = and(_T_178, _T_179) @[axi4_to_ahb.scala 218:70] - buf_state_en <= _T_180 @[axi4_to_ahb.scala 218:20] - slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 219:23] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 220:20] - node _T_181 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 221:35] - buf_cmd_byte_ptr <= _T_181 @[axi4_to_ahb.scala 221:24] - node _T_182 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 222:51] + buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 210:20] + node _T_176 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 211:51] + node _T_177 = neq(_T_176, UInt<1>("h00")) @[axi4_to_ahb.scala 211:58] + node _T_178 = and(ahb_hready_q, _T_177) @[axi4_to_ahb.scala 211:36] + node _T_179 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 211:72] + node _T_180 = and(_T_178, _T_179) @[axi4_to_ahb.scala 211:70] + buf_state_en <= _T_180 @[axi4_to_ahb.scala 211:20] + slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 212:23] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 213:20] + node _T_181 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 214:35] + buf_cmd_byte_ptr <= _T_181 @[axi4_to_ahb.scala 214:24] + node _T_182 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 215:51] node _T_183 = bits(_T_182, 0, 0) @[Bitwise.scala 72:15] node _T_184 = mux(_T_183, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_185 = and(UInt<2>("h02"), _T_184) @[axi4_to_ahb.scala 222:41] - io.ahb.out.htrans <= _T_185 @[axi4_to_ahb.scala 222:25] + node _T_185 = and(UInt<2>("h02"), _T_184) @[axi4_to_ahb.scala 215:41] + io.ahb.out.htrans <= _T_185 @[axi4_to_ahb.scala 215:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_186 = eq(UInt<3>("h03"), buf_state) @[Conditional.scala 37:30] when _T_186 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 226:20] - node _T_187 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 227:37] - buf_state_en <= _T_187 @[axi4_to_ahb.scala 227:20] - buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 228:22] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 229:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 230:23] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 231:20] + buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 219:20] + node _T_187 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 220:37] + buf_state_en <= _T_187 @[axi4_to_ahb.scala 220:20] + buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 221:22] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 222:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 223:23] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 224:20] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_188 = eq(UInt<3>("h02"), buf_state) @[Conditional.scala 37:30] when _T_188 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 235:20] - node _T_189 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 236:33] - node _T_190 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 236:63] - node _T_191 = neq(_T_190, UInt<1>("h00")) @[axi4_to_ahb.scala 236:70] - node _T_192 = and(_T_189, _T_191) @[axi4_to_ahb.scala 236:48] - trxn_done <= _T_192 @[axi4_to_ahb.scala 236:17] - buf_state_en <= trxn_done @[axi4_to_ahb.scala 237:20] - buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 238:27] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 239:20] - node _T_193 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 240:47] - node _T_194 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 240:85] - node _T_195 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 240:103] - node _T_196 = add(_T_194, UInt<1>("h01")) @[axi4_to_ahb.scala 142:52] - node _T_197 = tail(_T_196, 1) @[axi4_to_ahb.scala 142:52] - node _T_198 = mux(UInt<1>("h01"), _T_197, _T_194) @[axi4_to_ahb.scala 142:24] - node _T_199 = bits(_T_195, 0, 0) @[axi4_to_ahb.scala 143:44] - node _T_200 = geq(UInt<1>("h00"), _T_198) @[axi4_to_ahb.scala 143:62] - node _T_201 = and(_T_199, _T_200) @[axi4_to_ahb.scala 143:48] - node _T_202 = bits(_T_195, 1, 1) @[axi4_to_ahb.scala 143:44] - node _T_203 = geq(UInt<1>("h01"), _T_198) @[axi4_to_ahb.scala 143:62] - node _T_204 = and(_T_202, _T_203) @[axi4_to_ahb.scala 143:48] - node _T_205 = bits(_T_195, 2, 2) @[axi4_to_ahb.scala 143:44] - node _T_206 = geq(UInt<2>("h02"), _T_198) @[axi4_to_ahb.scala 143:62] - node _T_207 = and(_T_205, _T_206) @[axi4_to_ahb.scala 143:48] - node _T_208 = bits(_T_195, 3, 3) @[axi4_to_ahb.scala 143:44] - node _T_209 = geq(UInt<2>("h03"), _T_198) @[axi4_to_ahb.scala 143:62] - node _T_210 = and(_T_208, _T_209) @[axi4_to_ahb.scala 143:48] - node _T_211 = bits(_T_195, 4, 4) @[axi4_to_ahb.scala 143:44] - node _T_212 = geq(UInt<3>("h04"), _T_198) @[axi4_to_ahb.scala 143:62] - node _T_213 = and(_T_211, _T_212) @[axi4_to_ahb.scala 143:48] - node _T_214 = bits(_T_195, 5, 5) @[axi4_to_ahb.scala 143:44] - node _T_215 = geq(UInt<3>("h05"), _T_198) @[axi4_to_ahb.scala 143:62] - node _T_216 = and(_T_214, _T_215) @[axi4_to_ahb.scala 143:48] - node _T_217 = bits(_T_195, 6, 6) @[axi4_to_ahb.scala 143:44] - node _T_218 = geq(UInt<3>("h06"), _T_198) @[axi4_to_ahb.scala 143:62] - node _T_219 = and(_T_217, _T_218) @[axi4_to_ahb.scala 143:48] - node _T_220 = bits(_T_195, 7, 7) @[axi4_to_ahb.scala 143:44] - node _T_221 = geq(UInt<3>("h07"), _T_198) @[axi4_to_ahb.scala 143:62] - node _T_222 = and(_T_220, _T_221) @[axi4_to_ahb.scala 143:48] + buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 228:20] + node _T_189 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 229:33] + node _T_190 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 229:63] + node _T_191 = neq(_T_190, UInt<1>("h00")) @[axi4_to_ahb.scala 229:70] + node _T_192 = and(_T_189, _T_191) @[axi4_to_ahb.scala 229:48] + trxn_done <= _T_192 @[axi4_to_ahb.scala 229:17] + buf_state_en <= trxn_done @[axi4_to_ahb.scala 230:20] + buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 231:27] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 232:20] + node _T_193 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 233:47] + node _T_194 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 233:85] + node _T_195 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 233:103] + node _T_196 = add(_T_194, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] + node _T_197 = tail(_T_196, 1) @[axi4_to_ahb.scala 135:52] + node _T_198 = mux(UInt<1>("h01"), _T_197, _T_194) @[axi4_to_ahb.scala 135:24] + node _T_199 = bits(_T_195, 0, 0) @[axi4_to_ahb.scala 136:44] + node _T_200 = geq(UInt<1>("h00"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_201 = and(_T_199, _T_200) @[axi4_to_ahb.scala 136:48] + node _T_202 = bits(_T_195, 1, 1) @[axi4_to_ahb.scala 136:44] + node _T_203 = geq(UInt<1>("h01"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_204 = and(_T_202, _T_203) @[axi4_to_ahb.scala 136:48] + node _T_205 = bits(_T_195, 2, 2) @[axi4_to_ahb.scala 136:44] + node _T_206 = geq(UInt<2>("h02"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_207 = and(_T_205, _T_206) @[axi4_to_ahb.scala 136:48] + node _T_208 = bits(_T_195, 3, 3) @[axi4_to_ahb.scala 136:44] + node _T_209 = geq(UInt<2>("h03"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_210 = and(_T_208, _T_209) @[axi4_to_ahb.scala 136:48] + node _T_211 = bits(_T_195, 4, 4) @[axi4_to_ahb.scala 136:44] + node _T_212 = geq(UInt<3>("h04"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_213 = and(_T_211, _T_212) @[axi4_to_ahb.scala 136:48] + node _T_214 = bits(_T_195, 5, 5) @[axi4_to_ahb.scala 136:44] + node _T_215 = geq(UInt<3>("h05"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_216 = and(_T_214, _T_215) @[axi4_to_ahb.scala 136:48] + node _T_217 = bits(_T_195, 6, 6) @[axi4_to_ahb.scala 136:44] + node _T_218 = geq(UInt<3>("h06"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_219 = and(_T_217, _T_218) @[axi4_to_ahb.scala 136:48] + node _T_220 = bits(_T_195, 7, 7) @[axi4_to_ahb.scala 136:44] + node _T_221 = geq(UInt<3>("h07"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_222 = and(_T_220, _T_221) @[axi4_to_ahb.scala 136:48] node _T_223 = mux(_T_222, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_224 = mux(_T_219, UInt<3>("h06"), _T_223) @[Mux.scala 98:16] node _T_225 = mux(_T_216, UInt<3>("h05"), _T_224) @[Mux.scala 98:16] @@ -109791,39 +109781,39 @@ circuit quasar_wrapper : node _T_228 = mux(_T_207, UInt<2>("h02"), _T_227) @[Mux.scala 98:16] node _T_229 = mux(_T_204, UInt<1>("h01"), _T_228) @[Mux.scala 98:16] node _T_230 = mux(_T_201, UInt<1>("h00"), _T_229) @[Mux.scala 98:16] - node _T_231 = mux(_T_193, _T_230, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 240:30] - buf_cmd_byte_ptr <= _T_231 @[axi4_to_ahb.scala 240:24] - node _T_232 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 241:65] - node _T_233 = or(buf_aligned, _T_232) @[axi4_to_ahb.scala 241:44] - node _T_234 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 241:127] - node _T_235 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 241:145] - node _T_236 = add(_T_234, UInt<1>("h01")) @[axi4_to_ahb.scala 142:52] - node _T_237 = tail(_T_236, 1) @[axi4_to_ahb.scala 142:52] - node _T_238 = mux(UInt<1>("h01"), _T_237, _T_234) @[axi4_to_ahb.scala 142:24] - node _T_239 = bits(_T_235, 0, 0) @[axi4_to_ahb.scala 143:44] - node _T_240 = geq(UInt<1>("h00"), _T_238) @[axi4_to_ahb.scala 143:62] - node _T_241 = and(_T_239, _T_240) @[axi4_to_ahb.scala 143:48] - node _T_242 = bits(_T_235, 1, 1) @[axi4_to_ahb.scala 143:44] - node _T_243 = geq(UInt<1>("h01"), _T_238) @[axi4_to_ahb.scala 143:62] - node _T_244 = and(_T_242, _T_243) @[axi4_to_ahb.scala 143:48] - node _T_245 = bits(_T_235, 2, 2) @[axi4_to_ahb.scala 143:44] - node _T_246 = geq(UInt<2>("h02"), _T_238) @[axi4_to_ahb.scala 143:62] - node _T_247 = and(_T_245, _T_246) @[axi4_to_ahb.scala 143:48] - node _T_248 = bits(_T_235, 3, 3) @[axi4_to_ahb.scala 143:44] - node _T_249 = geq(UInt<2>("h03"), _T_238) @[axi4_to_ahb.scala 143:62] - node _T_250 = and(_T_248, _T_249) @[axi4_to_ahb.scala 143:48] - node _T_251 = bits(_T_235, 4, 4) @[axi4_to_ahb.scala 143:44] - node _T_252 = geq(UInt<3>("h04"), _T_238) @[axi4_to_ahb.scala 143:62] - node _T_253 = and(_T_251, _T_252) @[axi4_to_ahb.scala 143:48] - node _T_254 = bits(_T_235, 5, 5) @[axi4_to_ahb.scala 143:44] - node _T_255 = geq(UInt<3>("h05"), _T_238) @[axi4_to_ahb.scala 143:62] - node _T_256 = and(_T_254, _T_255) @[axi4_to_ahb.scala 143:48] - node _T_257 = bits(_T_235, 6, 6) @[axi4_to_ahb.scala 143:44] - node _T_258 = geq(UInt<3>("h06"), _T_238) @[axi4_to_ahb.scala 143:62] - node _T_259 = and(_T_257, _T_258) @[axi4_to_ahb.scala 143:48] - node _T_260 = bits(_T_235, 7, 7) @[axi4_to_ahb.scala 143:44] - node _T_261 = geq(UInt<3>("h07"), _T_238) @[axi4_to_ahb.scala 143:62] - node _T_262 = and(_T_260, _T_261) @[axi4_to_ahb.scala 143:48] + node _T_231 = mux(_T_193, _T_230, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 233:30] + buf_cmd_byte_ptr <= _T_231 @[axi4_to_ahb.scala 233:24] + node _T_232 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 234:65] + node _T_233 = or(buf_aligned, _T_232) @[axi4_to_ahb.scala 234:44] + node _T_234 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 234:127] + node _T_235 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 234:145] + node _T_236 = add(_T_234, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] + node _T_237 = tail(_T_236, 1) @[axi4_to_ahb.scala 135:52] + node _T_238 = mux(UInt<1>("h01"), _T_237, _T_234) @[axi4_to_ahb.scala 135:24] + node _T_239 = bits(_T_235, 0, 0) @[axi4_to_ahb.scala 136:44] + node _T_240 = geq(UInt<1>("h00"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_241 = and(_T_239, _T_240) @[axi4_to_ahb.scala 136:48] + node _T_242 = bits(_T_235, 1, 1) @[axi4_to_ahb.scala 136:44] + node _T_243 = geq(UInt<1>("h01"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_244 = and(_T_242, _T_243) @[axi4_to_ahb.scala 136:48] + node _T_245 = bits(_T_235, 2, 2) @[axi4_to_ahb.scala 136:44] + node _T_246 = geq(UInt<2>("h02"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_247 = and(_T_245, _T_246) @[axi4_to_ahb.scala 136:48] + node _T_248 = bits(_T_235, 3, 3) @[axi4_to_ahb.scala 136:44] + node _T_249 = geq(UInt<2>("h03"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_250 = and(_T_248, _T_249) @[axi4_to_ahb.scala 136:48] + node _T_251 = bits(_T_235, 4, 4) @[axi4_to_ahb.scala 136:44] + node _T_252 = geq(UInt<3>("h04"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_253 = and(_T_251, _T_252) @[axi4_to_ahb.scala 136:48] + node _T_254 = bits(_T_235, 5, 5) @[axi4_to_ahb.scala 136:44] + node _T_255 = geq(UInt<3>("h05"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_256 = and(_T_254, _T_255) @[axi4_to_ahb.scala 136:48] + node _T_257 = bits(_T_235, 6, 6) @[axi4_to_ahb.scala 136:44] + node _T_258 = geq(UInt<3>("h06"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_259 = and(_T_257, _T_258) @[axi4_to_ahb.scala 136:48] + node _T_260 = bits(_T_235, 7, 7) @[axi4_to_ahb.scala 136:44] + node _T_261 = geq(UInt<3>("h07"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_262 = and(_T_260, _T_261) @[axi4_to_ahb.scala 136:48] node _T_263 = mux(_T_262, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_264 = mux(_T_259, UInt<3>("h06"), _T_263) @[Mux.scala 98:16] node _T_265 = mux(_T_256, UInt<3>("h05"), _T_264) @[Mux.scala 98:16] @@ -109832,83 +109822,83 @@ circuit quasar_wrapper : node _T_268 = mux(_T_247, UInt<2>("h02"), _T_267) @[Mux.scala 98:16] node _T_269 = mux(_T_244, UInt<1>("h01"), _T_268) @[Mux.scala 98:16] node _T_270 = mux(_T_241, UInt<1>("h00"), _T_269) @[Mux.scala 98:16] - node _T_271 = dshr(buf_byteen, _T_270) @[axi4_to_ahb.scala 241:92] - node _T_272 = bits(_T_271, 0, 0) @[axi4_to_ahb.scala 241:92] - node _T_273 = eq(_T_272, UInt<1>("h00")) @[axi4_to_ahb.scala 241:163] - node _T_274 = or(_T_233, _T_273) @[axi4_to_ahb.scala 241:79] - node _T_275 = and(trxn_done, _T_274) @[axi4_to_ahb.scala 241:29] - cmd_done <= _T_275 @[axi4_to_ahb.scala 241:16] - node _T_276 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 242:47] - node _T_277 = eq(_T_276, UInt<1>("h00")) @[axi4_to_ahb.scala 242:36] + node _T_271 = dshr(buf_byteen, _T_270) @[axi4_to_ahb.scala 234:92] + node _T_272 = bits(_T_271, 0, 0) @[axi4_to_ahb.scala 234:92] + node _T_273 = eq(_T_272, UInt<1>("h00")) @[axi4_to_ahb.scala 234:163] + node _T_274 = or(_T_233, _T_273) @[axi4_to_ahb.scala 234:79] + node _T_275 = and(trxn_done, _T_274) @[axi4_to_ahb.scala 234:29] + cmd_done <= _T_275 @[axi4_to_ahb.scala 234:16] + node _T_276 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 235:47] + node _T_277 = eq(_T_276, UInt<1>("h00")) @[axi4_to_ahb.scala 235:36] node _T_278 = bits(_T_277, 0, 0) @[Bitwise.scala 72:15] node _T_279 = mux(_T_278, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_280 = and(_T_279, UInt<2>("h02")) @[axi4_to_ahb.scala 242:61] - io.ahb.out.htrans <= _T_280 @[axi4_to_ahb.scala 242:25] + node _T_280 = and(_T_279, UInt<2>("h02")) @[axi4_to_ahb.scala 235:61] + io.ahb.out.htrans <= _T_280 @[axi4_to_ahb.scala 235:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_281 = eq(UInt<3>("h04"), buf_state) @[Conditional.scala 37:30] when _T_281 : @[Conditional.scala 39:67] - node _T_282 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 246:34] - node _T_283 = or(_T_282, ahb_hresp_q) @[axi4_to_ahb.scala 246:50] - buf_state_en <= _T_283 @[axi4_to_ahb.scala 246:20] - node _T_284 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 247:38] - node _T_285 = and(buf_state_en, _T_284) @[axi4_to_ahb.scala 247:36] - node _T_286 = and(_T_285, slave_ready) @[axi4_to_ahb.scala 247:51] - master_ready <= _T_286 @[axi4_to_ahb.scala 247:20] - node _T_287 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 248:42] - node _T_288 = or(ahb_hresp_q, _T_287) @[axi4_to_ahb.scala 248:40] - node _T_289 = and(master_valid, master_valid) @[axi4_to_ahb.scala 248:80] - node _T_290 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 248:111] - node _T_291 = eq(_T_290, UInt<1>("h01")) @[axi4_to_ahb.scala 248:117] - node _T_292 = bits(_T_291, 0, 0) @[axi4_to_ahb.scala 248:132] - node _T_293 = mux(_T_292, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 248:99] - node _T_294 = mux(_T_289, _T_293, UInt<3>("h00")) @[axi4_to_ahb.scala 248:65] - node _T_295 = mux(_T_288, UInt<3>("h05"), _T_294) @[axi4_to_ahb.scala 248:26] - buf_nxtstate <= _T_295 @[axi4_to_ahb.scala 248:20] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 249:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 250:23] - node _T_296 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 251:33] - node _T_297 = eq(_T_296, UInt<1>("h01")) @[axi4_to_ahb.scala 251:39] - buf_write_in <= _T_297 @[axi4_to_ahb.scala 251:20] - node _T_298 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 252:50] - node _T_299 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 252:78] - node _T_300 = or(_T_298, _T_299) @[axi4_to_ahb.scala 252:62] - node _T_301 = and(buf_state_en, _T_300) @[axi4_to_ahb.scala 252:33] - buf_wr_en <= _T_301 @[axi4_to_ahb.scala 252:17] - buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 253:22] - node _T_302 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 254:65] - node _T_303 = neq(_T_302, UInt<1>("h00")) @[axi4_to_ahb.scala 254:71] - node _T_304 = and(ahb_hready_q, _T_303) @[axi4_to_ahb.scala 254:50] - node _T_305 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 255:29] - node _T_306 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 255:85] - node _T_307 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 255:101] - node _T_308 = add(_T_306, UInt<1>("h01")) @[axi4_to_ahb.scala 142:52] - node _T_309 = tail(_T_308, 1) @[axi4_to_ahb.scala 142:52] - node _T_310 = mux(UInt<1>("h01"), _T_309, _T_306) @[axi4_to_ahb.scala 142:24] - node _T_311 = bits(_T_307, 0, 0) @[axi4_to_ahb.scala 143:44] - node _T_312 = geq(UInt<1>("h00"), _T_310) @[axi4_to_ahb.scala 143:62] - node _T_313 = and(_T_311, _T_312) @[axi4_to_ahb.scala 143:48] - node _T_314 = bits(_T_307, 1, 1) @[axi4_to_ahb.scala 143:44] - node _T_315 = geq(UInt<1>("h01"), _T_310) @[axi4_to_ahb.scala 143:62] - node _T_316 = and(_T_314, _T_315) @[axi4_to_ahb.scala 143:48] - node _T_317 = bits(_T_307, 2, 2) @[axi4_to_ahb.scala 143:44] - node _T_318 = geq(UInt<2>("h02"), _T_310) @[axi4_to_ahb.scala 143:62] - node _T_319 = and(_T_317, _T_318) @[axi4_to_ahb.scala 143:48] - node _T_320 = bits(_T_307, 3, 3) @[axi4_to_ahb.scala 143:44] - node _T_321 = geq(UInt<2>("h03"), _T_310) @[axi4_to_ahb.scala 143:62] - node _T_322 = and(_T_320, _T_321) @[axi4_to_ahb.scala 143:48] - node _T_323 = bits(_T_307, 4, 4) @[axi4_to_ahb.scala 143:44] - node _T_324 = geq(UInt<3>("h04"), _T_310) @[axi4_to_ahb.scala 143:62] - node _T_325 = and(_T_323, _T_324) @[axi4_to_ahb.scala 143:48] - node _T_326 = bits(_T_307, 5, 5) @[axi4_to_ahb.scala 143:44] - node _T_327 = geq(UInt<3>("h05"), _T_310) @[axi4_to_ahb.scala 143:62] - node _T_328 = and(_T_326, _T_327) @[axi4_to_ahb.scala 143:48] - node _T_329 = bits(_T_307, 6, 6) @[axi4_to_ahb.scala 143:44] - node _T_330 = geq(UInt<3>("h06"), _T_310) @[axi4_to_ahb.scala 143:62] - node _T_331 = and(_T_329, _T_330) @[axi4_to_ahb.scala 143:48] - node _T_332 = bits(_T_307, 7, 7) @[axi4_to_ahb.scala 143:44] - node _T_333 = geq(UInt<3>("h07"), _T_310) @[axi4_to_ahb.scala 143:62] - node _T_334 = and(_T_332, _T_333) @[axi4_to_ahb.scala 143:48] + node _T_282 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 239:34] + node _T_283 = or(_T_282, ahb_hresp_q) @[axi4_to_ahb.scala 239:50] + buf_state_en <= _T_283 @[axi4_to_ahb.scala 239:20] + node _T_284 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 240:38] + node _T_285 = and(buf_state_en, _T_284) @[axi4_to_ahb.scala 240:36] + node _T_286 = and(_T_285, slave_ready) @[axi4_to_ahb.scala 240:51] + master_ready <= _T_286 @[axi4_to_ahb.scala 240:20] + node _T_287 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 241:42] + node _T_288 = or(ahb_hresp_q, _T_287) @[axi4_to_ahb.scala 241:40] + node _T_289 = and(master_valid, master_valid) @[axi4_to_ahb.scala 241:80] + node _T_290 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 241:111] + node _T_291 = eq(_T_290, UInt<1>("h01")) @[axi4_to_ahb.scala 241:117] + node _T_292 = bits(_T_291, 0, 0) @[axi4_to_ahb.scala 241:132] + node _T_293 = mux(_T_292, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 241:99] + node _T_294 = mux(_T_289, _T_293, UInt<3>("h00")) @[axi4_to_ahb.scala 241:65] + node _T_295 = mux(_T_288, UInt<3>("h05"), _T_294) @[axi4_to_ahb.scala 241:26] + buf_nxtstate <= _T_295 @[axi4_to_ahb.scala 241:20] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 242:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 243:23] + node _T_296 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 244:33] + node _T_297 = eq(_T_296, UInt<1>("h01")) @[axi4_to_ahb.scala 244:39] + buf_write_in <= _T_297 @[axi4_to_ahb.scala 244:20] + node _T_298 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 245:50] + node _T_299 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 245:78] + node _T_300 = or(_T_298, _T_299) @[axi4_to_ahb.scala 245:62] + node _T_301 = and(buf_state_en, _T_300) @[axi4_to_ahb.scala 245:33] + buf_wr_en <= _T_301 @[axi4_to_ahb.scala 245:17] + buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 246:22] + node _T_302 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 247:65] + node _T_303 = neq(_T_302, UInt<1>("h00")) @[axi4_to_ahb.scala 247:71] + node _T_304 = and(ahb_hready_q, _T_303) @[axi4_to_ahb.scala 247:50] + node _T_305 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 248:29] + node _T_306 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 248:85] + node _T_307 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 248:101] + node _T_308 = add(_T_306, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] + node _T_309 = tail(_T_308, 1) @[axi4_to_ahb.scala 135:52] + node _T_310 = mux(UInt<1>("h01"), _T_309, _T_306) @[axi4_to_ahb.scala 135:24] + node _T_311 = bits(_T_307, 0, 0) @[axi4_to_ahb.scala 136:44] + node _T_312 = geq(UInt<1>("h00"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_313 = and(_T_311, _T_312) @[axi4_to_ahb.scala 136:48] + node _T_314 = bits(_T_307, 1, 1) @[axi4_to_ahb.scala 136:44] + node _T_315 = geq(UInt<1>("h01"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_316 = and(_T_314, _T_315) @[axi4_to_ahb.scala 136:48] + node _T_317 = bits(_T_307, 2, 2) @[axi4_to_ahb.scala 136:44] + node _T_318 = geq(UInt<2>("h02"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_319 = and(_T_317, _T_318) @[axi4_to_ahb.scala 136:48] + node _T_320 = bits(_T_307, 3, 3) @[axi4_to_ahb.scala 136:44] + node _T_321 = geq(UInt<2>("h03"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_322 = and(_T_320, _T_321) @[axi4_to_ahb.scala 136:48] + node _T_323 = bits(_T_307, 4, 4) @[axi4_to_ahb.scala 136:44] + node _T_324 = geq(UInt<3>("h04"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_325 = and(_T_323, _T_324) @[axi4_to_ahb.scala 136:48] + node _T_326 = bits(_T_307, 5, 5) @[axi4_to_ahb.scala 136:44] + node _T_327 = geq(UInt<3>("h05"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_328 = and(_T_326, _T_327) @[axi4_to_ahb.scala 136:48] + node _T_329 = bits(_T_307, 6, 6) @[axi4_to_ahb.scala 136:44] + node _T_330 = geq(UInt<3>("h06"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_331 = and(_T_329, _T_330) @[axi4_to_ahb.scala 136:48] + node _T_332 = bits(_T_307, 7, 7) @[axi4_to_ahb.scala 136:44] + node _T_333 = geq(UInt<3>("h07"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_334 = and(_T_332, _T_333) @[axi4_to_ahb.scala 136:48] node _T_335 = mux(_T_334, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_336 = mux(_T_331, UInt<3>("h06"), _T_335) @[Mux.scala 98:16] node _T_337 = mux(_T_328, UInt<3>("h05"), _T_336) @[Mux.scala 98:16] @@ -109917,62 +109907,62 @@ circuit quasar_wrapper : node _T_340 = mux(_T_319, UInt<2>("h02"), _T_339) @[Mux.scala 98:16] node _T_341 = mux(_T_316, UInt<1>("h01"), _T_340) @[Mux.scala 98:16] node _T_342 = mux(_T_313, UInt<1>("h00"), _T_341) @[Mux.scala 98:16] - node _T_343 = dshr(buf_byteen, _T_342) @[axi4_to_ahb.scala 255:51] - node _T_344 = bits(_T_343, 0, 0) @[axi4_to_ahb.scala 255:51] - node _T_345 = eq(_T_344, UInt<1>("h00")) @[axi4_to_ahb.scala 255:116] - node _T_346 = or(_T_305, _T_345) @[axi4_to_ahb.scala 255:38] - node _T_347 = and(_T_304, _T_346) @[axi4_to_ahb.scala 254:80] - node _T_348 = or(ahb_hresp_q, _T_347) @[axi4_to_ahb.scala 254:34] - cmd_done <= _T_348 @[axi4_to_ahb.scala 254:16] - node _T_349 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 256:33] - node _T_350 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 256:64] - node _T_351 = and(_T_349, _T_350) @[axi4_to_ahb.scala 256:48] - bypass_en <= _T_351 @[axi4_to_ahb.scala 256:17] - node _T_352 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 257:48] - node _T_353 = eq(_T_352, UInt<1>("h00")) @[axi4_to_ahb.scala 257:37] - node _T_354 = or(_T_353, bypass_en) @[axi4_to_ahb.scala 257:61] + node _T_343 = dshr(buf_byteen, _T_342) @[axi4_to_ahb.scala 248:51] + node _T_344 = bits(_T_343, 0, 0) @[axi4_to_ahb.scala 248:51] + node _T_345 = eq(_T_344, UInt<1>("h00")) @[axi4_to_ahb.scala 248:116] + node _T_346 = or(_T_305, _T_345) @[axi4_to_ahb.scala 248:38] + node _T_347 = and(_T_304, _T_346) @[axi4_to_ahb.scala 247:80] + node _T_348 = or(ahb_hresp_q, _T_347) @[axi4_to_ahb.scala 247:34] + cmd_done <= _T_348 @[axi4_to_ahb.scala 247:16] + node _T_349 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 249:33] + node _T_350 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 249:64] + node _T_351 = and(_T_349, _T_350) @[axi4_to_ahb.scala 249:48] + bypass_en <= _T_351 @[axi4_to_ahb.scala 249:17] + node _T_352 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 250:48] + node _T_353 = eq(_T_352, UInt<1>("h00")) @[axi4_to_ahb.scala 250:37] + node _T_354 = or(_T_353, bypass_en) @[axi4_to_ahb.scala 250:61] node _T_355 = bits(_T_354, 0, 0) @[Bitwise.scala 72:15] node _T_356 = mux(_T_355, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_357 = and(_T_356, UInt<2>("h02")) @[axi4_to_ahb.scala 257:75] - io.ahb.out.htrans <= _T_357 @[axi4_to_ahb.scala 257:25] - node _T_358 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 258:55] - node _T_359 = and(buf_state_en, _T_358) @[axi4_to_ahb.scala 258:39] - slave_valid_pre <= _T_359 @[axi4_to_ahb.scala 258:23] - node _T_360 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 259:33] - node _T_361 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 259:63] - node _T_362 = neq(_T_361, UInt<1>("h00")) @[axi4_to_ahb.scala 259:69] - node _T_363 = and(_T_360, _T_362) @[axi4_to_ahb.scala 259:48] - trxn_done <= _T_363 @[axi4_to_ahb.scala 259:17] - node _T_364 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 260:40] - buf_cmd_byte_ptr_en <= _T_364 @[axi4_to_ahb.scala 260:27] - node _T_365 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 261:79] - node _T_366 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 142:52] - node _T_367 = tail(_T_366, 1) @[axi4_to_ahb.scala 142:52] - node _T_368 = mux(UInt<1>("h00"), _T_367, UInt<3>("h00")) @[axi4_to_ahb.scala 142:24] - node _T_369 = bits(_T_365, 0, 0) @[axi4_to_ahb.scala 143:44] - node _T_370 = geq(UInt<1>("h00"), _T_368) @[axi4_to_ahb.scala 143:62] - node _T_371 = and(_T_369, _T_370) @[axi4_to_ahb.scala 143:48] - node _T_372 = bits(_T_365, 1, 1) @[axi4_to_ahb.scala 143:44] - node _T_373 = geq(UInt<1>("h01"), _T_368) @[axi4_to_ahb.scala 143:62] - node _T_374 = and(_T_372, _T_373) @[axi4_to_ahb.scala 143:48] - node _T_375 = bits(_T_365, 2, 2) @[axi4_to_ahb.scala 143:44] - node _T_376 = geq(UInt<2>("h02"), _T_368) @[axi4_to_ahb.scala 143:62] - node _T_377 = and(_T_375, _T_376) @[axi4_to_ahb.scala 143:48] - node _T_378 = bits(_T_365, 3, 3) @[axi4_to_ahb.scala 143:44] - node _T_379 = geq(UInt<2>("h03"), _T_368) @[axi4_to_ahb.scala 143:62] - node _T_380 = and(_T_378, _T_379) @[axi4_to_ahb.scala 143:48] - node _T_381 = bits(_T_365, 4, 4) @[axi4_to_ahb.scala 143:44] - node _T_382 = geq(UInt<3>("h04"), _T_368) @[axi4_to_ahb.scala 143:62] - node _T_383 = and(_T_381, _T_382) @[axi4_to_ahb.scala 143:48] - node _T_384 = bits(_T_365, 5, 5) @[axi4_to_ahb.scala 143:44] - node _T_385 = geq(UInt<3>("h05"), _T_368) @[axi4_to_ahb.scala 143:62] - node _T_386 = and(_T_384, _T_385) @[axi4_to_ahb.scala 143:48] - node _T_387 = bits(_T_365, 6, 6) @[axi4_to_ahb.scala 143:44] - node _T_388 = geq(UInt<3>("h06"), _T_368) @[axi4_to_ahb.scala 143:62] - node _T_389 = and(_T_387, _T_388) @[axi4_to_ahb.scala 143:48] - node _T_390 = bits(_T_365, 7, 7) @[axi4_to_ahb.scala 143:44] - node _T_391 = geq(UInt<3>("h07"), _T_368) @[axi4_to_ahb.scala 143:62] - node _T_392 = and(_T_390, _T_391) @[axi4_to_ahb.scala 143:48] + node _T_357 = and(_T_356, UInt<2>("h02")) @[axi4_to_ahb.scala 250:75] + io.ahb.out.htrans <= _T_357 @[axi4_to_ahb.scala 250:25] + node _T_358 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 251:55] + node _T_359 = and(buf_state_en, _T_358) @[axi4_to_ahb.scala 251:39] + slave_valid_pre <= _T_359 @[axi4_to_ahb.scala 251:23] + node _T_360 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 252:33] + node _T_361 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 252:63] + node _T_362 = neq(_T_361, UInt<1>("h00")) @[axi4_to_ahb.scala 252:69] + node _T_363 = and(_T_360, _T_362) @[axi4_to_ahb.scala 252:48] + trxn_done <= _T_363 @[axi4_to_ahb.scala 252:17] + node _T_364 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 253:40] + buf_cmd_byte_ptr_en <= _T_364 @[axi4_to_ahb.scala 253:27] + node _T_365 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 254:79] + node _T_366 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] + node _T_367 = tail(_T_366, 1) @[axi4_to_ahb.scala 135:52] + node _T_368 = mux(UInt<1>("h00"), _T_367, UInt<3>("h00")) @[axi4_to_ahb.scala 135:24] + node _T_369 = bits(_T_365, 0, 0) @[axi4_to_ahb.scala 136:44] + node _T_370 = geq(UInt<1>("h00"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_371 = and(_T_369, _T_370) @[axi4_to_ahb.scala 136:48] + node _T_372 = bits(_T_365, 1, 1) @[axi4_to_ahb.scala 136:44] + node _T_373 = geq(UInt<1>("h01"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_374 = and(_T_372, _T_373) @[axi4_to_ahb.scala 136:48] + node _T_375 = bits(_T_365, 2, 2) @[axi4_to_ahb.scala 136:44] + node _T_376 = geq(UInt<2>("h02"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_377 = and(_T_375, _T_376) @[axi4_to_ahb.scala 136:48] + node _T_378 = bits(_T_365, 3, 3) @[axi4_to_ahb.scala 136:44] + node _T_379 = geq(UInt<2>("h03"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_380 = and(_T_378, _T_379) @[axi4_to_ahb.scala 136:48] + node _T_381 = bits(_T_365, 4, 4) @[axi4_to_ahb.scala 136:44] + node _T_382 = geq(UInt<3>("h04"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_383 = and(_T_381, _T_382) @[axi4_to_ahb.scala 136:48] + node _T_384 = bits(_T_365, 5, 5) @[axi4_to_ahb.scala 136:44] + node _T_385 = geq(UInt<3>("h05"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_386 = and(_T_384, _T_385) @[axi4_to_ahb.scala 136:48] + node _T_387 = bits(_T_365, 6, 6) @[axi4_to_ahb.scala 136:44] + node _T_388 = geq(UInt<3>("h06"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_389 = and(_T_387, _T_388) @[axi4_to_ahb.scala 136:48] + node _T_390 = bits(_T_365, 7, 7) @[axi4_to_ahb.scala 136:44] + node _T_391 = geq(UInt<3>("h07"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_392 = and(_T_390, _T_391) @[axi4_to_ahb.scala 136:48] node _T_393 = mux(_T_392, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_394 = mux(_T_389, UInt<3>("h06"), _T_393) @[Mux.scala 98:16] node _T_395 = mux(_T_386, UInt<3>("h05"), _T_394) @[Mux.scala 98:16] @@ -109981,35 +109971,35 @@ circuit quasar_wrapper : node _T_398 = mux(_T_377, UInt<2>("h02"), _T_397) @[Mux.scala 98:16] node _T_399 = mux(_T_374, UInt<1>("h01"), _T_398) @[Mux.scala 98:16] node _T_400 = mux(_T_371, UInt<1>("h00"), _T_399) @[Mux.scala 98:16] - node _T_401 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 261:141] - node _T_402 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 261:157] - node _T_403 = add(_T_401, UInt<1>("h01")) @[axi4_to_ahb.scala 142:52] - node _T_404 = tail(_T_403, 1) @[axi4_to_ahb.scala 142:52] - node _T_405 = mux(UInt<1>("h01"), _T_404, _T_401) @[axi4_to_ahb.scala 142:24] - node _T_406 = bits(_T_402, 0, 0) @[axi4_to_ahb.scala 143:44] - node _T_407 = geq(UInt<1>("h00"), _T_405) @[axi4_to_ahb.scala 143:62] - node _T_408 = and(_T_406, _T_407) @[axi4_to_ahb.scala 143:48] - node _T_409 = bits(_T_402, 1, 1) @[axi4_to_ahb.scala 143:44] - node _T_410 = geq(UInt<1>("h01"), _T_405) @[axi4_to_ahb.scala 143:62] - node _T_411 = and(_T_409, _T_410) @[axi4_to_ahb.scala 143:48] - node _T_412 = bits(_T_402, 2, 2) @[axi4_to_ahb.scala 143:44] - node _T_413 = geq(UInt<2>("h02"), _T_405) @[axi4_to_ahb.scala 143:62] - node _T_414 = and(_T_412, _T_413) @[axi4_to_ahb.scala 143:48] - node _T_415 = bits(_T_402, 3, 3) @[axi4_to_ahb.scala 143:44] - node _T_416 = geq(UInt<2>("h03"), _T_405) @[axi4_to_ahb.scala 143:62] - node _T_417 = and(_T_415, _T_416) @[axi4_to_ahb.scala 143:48] - node _T_418 = bits(_T_402, 4, 4) @[axi4_to_ahb.scala 143:44] - node _T_419 = geq(UInt<3>("h04"), _T_405) @[axi4_to_ahb.scala 143:62] - node _T_420 = and(_T_418, _T_419) @[axi4_to_ahb.scala 143:48] - node _T_421 = bits(_T_402, 5, 5) @[axi4_to_ahb.scala 143:44] - node _T_422 = geq(UInt<3>("h05"), _T_405) @[axi4_to_ahb.scala 143:62] - node _T_423 = and(_T_421, _T_422) @[axi4_to_ahb.scala 143:48] - node _T_424 = bits(_T_402, 6, 6) @[axi4_to_ahb.scala 143:44] - node _T_425 = geq(UInt<3>("h06"), _T_405) @[axi4_to_ahb.scala 143:62] - node _T_426 = and(_T_424, _T_425) @[axi4_to_ahb.scala 143:48] - node _T_427 = bits(_T_402, 7, 7) @[axi4_to_ahb.scala 143:44] - node _T_428 = geq(UInt<3>("h07"), _T_405) @[axi4_to_ahb.scala 143:62] - node _T_429 = and(_T_427, _T_428) @[axi4_to_ahb.scala 143:48] + node _T_401 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 254:141] + node _T_402 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 254:157] + node _T_403 = add(_T_401, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] + node _T_404 = tail(_T_403, 1) @[axi4_to_ahb.scala 135:52] + node _T_405 = mux(UInt<1>("h01"), _T_404, _T_401) @[axi4_to_ahb.scala 135:24] + node _T_406 = bits(_T_402, 0, 0) @[axi4_to_ahb.scala 136:44] + node _T_407 = geq(UInt<1>("h00"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_408 = and(_T_406, _T_407) @[axi4_to_ahb.scala 136:48] + node _T_409 = bits(_T_402, 1, 1) @[axi4_to_ahb.scala 136:44] + node _T_410 = geq(UInt<1>("h01"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_411 = and(_T_409, _T_410) @[axi4_to_ahb.scala 136:48] + node _T_412 = bits(_T_402, 2, 2) @[axi4_to_ahb.scala 136:44] + node _T_413 = geq(UInt<2>("h02"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_414 = and(_T_412, _T_413) @[axi4_to_ahb.scala 136:48] + node _T_415 = bits(_T_402, 3, 3) @[axi4_to_ahb.scala 136:44] + node _T_416 = geq(UInt<2>("h03"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_417 = and(_T_415, _T_416) @[axi4_to_ahb.scala 136:48] + node _T_418 = bits(_T_402, 4, 4) @[axi4_to_ahb.scala 136:44] + node _T_419 = geq(UInt<3>("h04"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_420 = and(_T_418, _T_419) @[axi4_to_ahb.scala 136:48] + node _T_421 = bits(_T_402, 5, 5) @[axi4_to_ahb.scala 136:44] + node _T_422 = geq(UInt<3>("h05"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_423 = and(_T_421, _T_422) @[axi4_to_ahb.scala 136:48] + node _T_424 = bits(_T_402, 6, 6) @[axi4_to_ahb.scala 136:44] + node _T_425 = geq(UInt<3>("h06"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_426 = and(_T_424, _T_425) @[axi4_to_ahb.scala 136:48] + node _T_427 = bits(_T_402, 7, 7) @[axi4_to_ahb.scala 136:44] + node _T_428 = geq(UInt<3>("h07"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_429 = and(_T_427, _T_428) @[axi4_to_ahb.scala 136:48] node _T_430 = mux(_T_429, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_431 = mux(_T_426, UInt<3>("h06"), _T_430) @[Mux.scala 98:16] node _T_432 = mux(_T_423, UInt<3>("h05"), _T_431) @[Mux.scala 98:16] @@ -110018,268 +110008,268 @@ circuit quasar_wrapper : node _T_435 = mux(_T_414, UInt<2>("h02"), _T_434) @[Mux.scala 98:16] node _T_436 = mux(_T_411, UInt<1>("h01"), _T_435) @[Mux.scala 98:16] node _T_437 = mux(_T_408, UInt<1>("h00"), _T_436) @[Mux.scala 98:16] - node _T_438 = mux(trxn_done, _T_437, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 261:97] - node _T_439 = mux(bypass_en, _T_400, _T_438) @[axi4_to_ahb.scala 261:30] - buf_cmd_byte_ptr <= _T_439 @[axi4_to_ahb.scala 261:24] + node _T_438 = mux(trxn_done, _T_437, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 254:97] + node _T_439 = mux(bypass_en, _T_400, _T_438) @[axi4_to_ahb.scala 254:30] + buf_cmd_byte_ptr <= _T_439 @[axi4_to_ahb.scala 254:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_440 = eq(UInt<3>("h05"), buf_state) @[Conditional.scala 37:30] when _T_440 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 264:20] - buf_state_en <= slave_ready @[axi4_to_ahb.scala 265:20] - slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 266:23] - slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 267:23] + buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 257:20] + buf_state_en <= slave_ready @[axi4_to_ahb.scala 258:20] + slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 259:23] + slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 260:23] skip @[Conditional.scala 39:67] - cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 271:16] - node _T_441 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 272:33] - node _T_442 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 272:73] - node _T_443 = eq(_T_442, UInt<1>("h01")) @[axi4_to_ahb.scala 272:80] - node _T_444 = and(buf_aligned_in, _T_443) @[axi4_to_ahb.scala 272:60] - node _T_445 = bits(_T_444, 0, 0) @[axi4_to_ahb.scala 272:100] - node _T_446 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:132] - node _T_447 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 134:50] - node _T_448 = eq(_T_447, UInt<8>("h0ff")) @[axi4_to_ahb.scala 134:57] - node _T_449 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 134:81] - node _T_450 = eq(_T_449, UInt<8>("h0f")) @[axi4_to_ahb.scala 134:88] - node _T_451 = or(_T_448, _T_450) @[axi4_to_ahb.scala 134:70] - node _T_452 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 134:117] - node _T_453 = eq(_T_452, UInt<8>("h03")) @[axi4_to_ahb.scala 134:124] - node _T_454 = or(_T_451, _T_453) @[axi4_to_ahb.scala 134:106] + cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 264:16] + node _T_441 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 265:33] + node _T_442 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 265:73] + node _T_443 = eq(_T_442, UInt<1>("h01")) @[axi4_to_ahb.scala 265:80] + node _T_444 = and(buf_aligned_in, _T_443) @[axi4_to_ahb.scala 265:60] + node _T_445 = bits(_T_444, 0, 0) @[axi4_to_ahb.scala 265:100] + node _T_446 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 265:132] + node _T_447 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:50] + node _T_448 = eq(_T_447, UInt<8>("h0ff")) @[axi4_to_ahb.scala 127:57] + node _T_449 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:81] + node _T_450 = eq(_T_449, UInt<8>("h0f")) @[axi4_to_ahb.scala 127:88] + node _T_451 = or(_T_448, _T_450) @[axi4_to_ahb.scala 127:70] + node _T_452 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:117] + node _T_453 = eq(_T_452, UInt<8>("h03")) @[axi4_to_ahb.scala 127:124] + node _T_454 = or(_T_451, _T_453) @[axi4_to_ahb.scala 127:106] node _T_455 = bits(_T_454, 0, 0) @[Bitwise.scala 72:15] node _T_456 = mux(_T_455, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_457 = and(UInt<3>("h00"), _T_456) @[axi4_to_ahb.scala 134:29] - node _T_458 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 135:35] - node _T_459 = eq(_T_458, UInt<8>("h0c")) @[axi4_to_ahb.scala 135:42] + node _T_457 = and(UInt<3>("h00"), _T_456) @[axi4_to_ahb.scala 127:29] + node _T_458 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 128:35] + node _T_459 = eq(_T_458, UInt<8>("h0c")) @[axi4_to_ahb.scala 128:42] node _T_460 = bits(_T_459, 0, 0) @[Bitwise.scala 72:15] node _T_461 = mux(_T_460, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_462 = and(UInt<2>("h02"), _T_461) @[axi4_to_ahb.scala 135:15] - node _T_463 = or(_T_457, _T_462) @[axi4_to_ahb.scala 134:146] - node _T_464 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 136:36] - node _T_465 = eq(_T_464, UInt<8>("h0f0")) @[axi4_to_ahb.scala 136:43] - node _T_466 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 136:67] - node _T_467 = eq(_T_466, UInt<8>("h03")) @[axi4_to_ahb.scala 136:74] - node _T_468 = or(_T_465, _T_467) @[axi4_to_ahb.scala 136:56] + node _T_462 = and(UInt<2>("h02"), _T_461) @[axi4_to_ahb.scala 128:15] + node _T_463 = or(_T_457, _T_462) @[axi4_to_ahb.scala 127:146] + node _T_464 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 129:36] + node _T_465 = eq(_T_464, UInt<8>("h0f0")) @[axi4_to_ahb.scala 129:43] + node _T_466 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 129:67] + node _T_467 = eq(_T_466, UInt<8>("h03")) @[axi4_to_ahb.scala 129:74] + node _T_468 = or(_T_465, _T_467) @[axi4_to_ahb.scala 129:56] node _T_469 = bits(_T_468, 0, 0) @[Bitwise.scala 72:15] node _T_470 = mux(_T_469, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_471 = and(UInt<3>("h04"), _T_470) @[axi4_to_ahb.scala 136:15] - node _T_472 = or(_T_463, _T_471) @[axi4_to_ahb.scala 135:63] - node _T_473 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 137:35] - node _T_474 = eq(_T_473, UInt<8>("h0c0")) @[axi4_to_ahb.scala 137:42] + node _T_471 = and(UInt<3>("h04"), _T_470) @[axi4_to_ahb.scala 129:15] + node _T_472 = or(_T_463, _T_471) @[axi4_to_ahb.scala 128:63] + node _T_473 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 130:35] + node _T_474 = eq(_T_473, UInt<8>("h0c0")) @[axi4_to_ahb.scala 130:42] node _T_475 = bits(_T_474, 0, 0) @[Bitwise.scala 72:15] node _T_476 = mux(_T_475, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_477 = and(UInt<3>("h06"), _T_476) @[axi4_to_ahb.scala 137:15] - node _T_478 = or(_T_472, _T_477) @[axi4_to_ahb.scala 136:96] - node _T_479 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 138:33] - node _T_480 = eq(_T_479, UInt<8>("h0c0")) @[axi4_to_ahb.scala 138:40] + node _T_477 = and(UInt<3>("h06"), _T_476) @[axi4_to_ahb.scala 130:15] + node _T_478 = or(_T_472, _T_477) @[axi4_to_ahb.scala 129:96] + node _T_479 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 131:33] + node _T_480 = eq(_T_479, UInt<8>("h0c0")) @[axi4_to_ahb.scala 131:40] node _T_481 = bits(_T_480, 0, 0) @[Bitwise.scala 72:15] node _T_482 = mux(_T_481, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_483 = and(UInt<3>("h06"), _T_482) @[axi4_to_ahb.scala 138:13] - node _T_484 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 272:152] - node _T_485 = mux(_T_445, _T_478, _T_484) @[axi4_to_ahb.scala 272:43] + node _T_483 = and(UInt<3>("h06"), _T_482) @[axi4_to_ahb.scala 131:13] + node _T_484 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 265:152] + node _T_485 = mux(_T_445, _T_478, _T_484) @[axi4_to_ahb.scala 265:43] node _T_486 = cat(_T_441, _T_485) @[Cat.scala 29:58] - buf_addr_in <= _T_486 @[axi4_to_ahb.scala 272:15] - node _T_487 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 273:27] - buf_tag_in <= _T_487 @[axi4_to_ahb.scala 273:14] - node _T_488 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 274:32] - buf_byteen_in <= _T_488 @[axi4_to_ahb.scala 274:17] - node _T_489 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 275:33] - node _T_490 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 275:59] - node _T_491 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 275:80] - node _T_492 = mux(_T_489, _T_490, _T_491) @[axi4_to_ahb.scala 275:21] - buf_data_in <= _T_492 @[axi4_to_ahb.scala 275:15] - node _T_493 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 276:52] - node _T_494 = eq(_T_493, UInt<2>("h03")) @[axi4_to_ahb.scala 276:58] - node _T_495 = and(buf_aligned_in, _T_494) @[axi4_to_ahb.scala 276:38] - node _T_496 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 276:84] - node _T_497 = eq(_T_496, UInt<1>("h01")) @[axi4_to_ahb.scala 276:91] - node _T_498 = and(_T_495, _T_497) @[axi4_to_ahb.scala 276:71] - node _T_499 = bits(_T_498, 0, 0) @[axi4_to_ahb.scala 276:111] - node _T_500 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 276:142] - node _T_501 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 128:42] - node _T_502 = eq(_T_501, UInt<8>("h0ff")) @[axi4_to_ahb.scala 128:49] + buf_addr_in <= _T_486 @[axi4_to_ahb.scala 265:15] + node _T_487 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 266:27] + buf_tag_in <= _T_487 @[axi4_to_ahb.scala 266:14] + node _T_488 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 267:32] + buf_byteen_in <= _T_488 @[axi4_to_ahb.scala 267:17] + node _T_489 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 268:33] + node _T_490 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 268:59] + node _T_491 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 268:80] + node _T_492 = mux(_T_489, _T_490, _T_491) @[axi4_to_ahb.scala 268:21] + buf_data_in <= _T_492 @[axi4_to_ahb.scala 268:15] + node _T_493 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 269:52] + node _T_494 = eq(_T_493, UInt<2>("h03")) @[axi4_to_ahb.scala 269:58] + node _T_495 = and(buf_aligned_in, _T_494) @[axi4_to_ahb.scala 269:38] + node _T_496 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 269:84] + node _T_497 = eq(_T_496, UInt<1>("h01")) @[axi4_to_ahb.scala 269:91] + node _T_498 = and(_T_495, _T_497) @[axi4_to_ahb.scala 269:71] + node _T_499 = bits(_T_498, 0, 0) @[axi4_to_ahb.scala 269:111] + node _T_500 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 269:142] + node _T_501 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 121:42] + node _T_502 = eq(_T_501, UInt<8>("h0ff")) @[axi4_to_ahb.scala 121:49] node _T_503 = bits(_T_502, 0, 0) @[Bitwise.scala 72:15] node _T_504 = mux(_T_503, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_505 = and(UInt<2>("h03"), _T_504) @[axi4_to_ahb.scala 128:25] - node _T_506 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 129:35] - node _T_507 = eq(_T_506, UInt<8>("h0f0")) @[axi4_to_ahb.scala 129:42] - node _T_508 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 129:64] - node _T_509 = eq(_T_508, UInt<8>("h0f")) @[axi4_to_ahb.scala 129:71] - node _T_510 = or(_T_507, _T_509) @[axi4_to_ahb.scala 129:55] + node _T_505 = and(UInt<2>("h03"), _T_504) @[axi4_to_ahb.scala 121:25] + node _T_506 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 122:35] + node _T_507 = eq(_T_506, UInt<8>("h0f0")) @[axi4_to_ahb.scala 122:42] + node _T_508 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 122:64] + node _T_509 = eq(_T_508, UInt<8>("h0f")) @[axi4_to_ahb.scala 122:71] + node _T_510 = or(_T_507, _T_509) @[axi4_to_ahb.scala 122:55] node _T_511 = bits(_T_510, 0, 0) @[Bitwise.scala 72:15] node _T_512 = mux(_T_511, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_513 = and(UInt<2>("h02"), _T_512) @[axi4_to_ahb.scala 129:16] - node _T_514 = or(_T_505, _T_513) @[axi4_to_ahb.scala 128:64] - node _T_515 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 130:40] - node _T_516 = eq(_T_515, UInt<8>("h0c0")) @[axi4_to_ahb.scala 130:47] - node _T_517 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 130:69] - node _T_518 = eq(_T_517, UInt<6>("h030")) @[axi4_to_ahb.scala 130:76] - node _T_519 = or(_T_516, _T_518) @[axi4_to_ahb.scala 130:60] - node _T_520 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 130:98] - node _T_521 = eq(_T_520, UInt<8>("h0c")) @[axi4_to_ahb.scala 130:105] - node _T_522 = or(_T_519, _T_521) @[axi4_to_ahb.scala 130:89] - node _T_523 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 130:132] - node _T_524 = eq(_T_523, UInt<8>("h03")) @[axi4_to_ahb.scala 130:139] - node _T_525 = or(_T_522, _T_524) @[axi4_to_ahb.scala 130:123] + node _T_513 = and(UInt<2>("h02"), _T_512) @[axi4_to_ahb.scala 122:16] + node _T_514 = or(_T_505, _T_513) @[axi4_to_ahb.scala 121:64] + node _T_515 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:40] + node _T_516 = eq(_T_515, UInt<8>("h0c0")) @[axi4_to_ahb.scala 123:47] + node _T_517 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:69] + node _T_518 = eq(_T_517, UInt<6>("h030")) @[axi4_to_ahb.scala 123:76] + node _T_519 = or(_T_516, _T_518) @[axi4_to_ahb.scala 123:60] + node _T_520 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:98] + node _T_521 = eq(_T_520, UInt<8>("h0c")) @[axi4_to_ahb.scala 123:105] + node _T_522 = or(_T_519, _T_521) @[axi4_to_ahb.scala 123:89] + node _T_523 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:132] + node _T_524 = eq(_T_523, UInt<8>("h03")) @[axi4_to_ahb.scala 123:139] + node _T_525 = or(_T_522, _T_524) @[axi4_to_ahb.scala 123:123] node _T_526 = bits(_T_525, 0, 0) @[Bitwise.scala 72:15] node _T_527 = mux(_T_526, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_528 = and(UInt<2>("h01"), _T_527) @[axi4_to_ahb.scala 130:21] - node _T_529 = or(_T_514, _T_528) @[axi4_to_ahb.scala 129:93] - node _T_530 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 276:161] - node _T_531 = mux(_T_499, _T_529, _T_530) @[axi4_to_ahb.scala 276:21] - buf_size_in <= _T_531 @[axi4_to_ahb.scala 276:15] - node _T_532 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 277:32] - node _T_533 = eq(_T_532, UInt<1>("h00")) @[axi4_to_ahb.scala 277:39] - node _T_534 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 278:17] - node _T_535 = eq(_T_534, UInt<1>("h00")) @[axi4_to_ahb.scala 278:24] - node _T_536 = or(_T_533, _T_535) @[axi4_to_ahb.scala 277:48] - node _T_537 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 278:47] - node _T_538 = eq(_T_537, UInt<2>("h01")) @[axi4_to_ahb.scala 278:54] - node _T_539 = or(_T_536, _T_538) @[axi4_to_ahb.scala 278:33] - node _T_540 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 278:86] - node _T_541 = eq(_T_540, UInt<2>("h02")) @[axi4_to_ahb.scala 278:93] - node _T_542 = or(_T_539, _T_541) @[axi4_to_ahb.scala 278:72] - node _T_543 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 279:18] - node _T_544 = eq(_T_543, UInt<2>("h03")) @[axi4_to_ahb.scala 279:25] - node _T_545 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 279:55] - node _T_546 = eq(_T_545, UInt<2>("h03")) @[axi4_to_ahb.scala 279:62] - node _T_547 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 279:90] - node _T_548 = eq(_T_547, UInt<4>("h0c")) @[axi4_to_ahb.scala 279:97] - node _T_549 = or(_T_546, _T_548) @[axi4_to_ahb.scala 279:74] - node _T_550 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 279:125] - node _T_551 = eq(_T_550, UInt<6>("h030")) @[axi4_to_ahb.scala 279:132] - node _T_552 = or(_T_549, _T_551) @[axi4_to_ahb.scala 279:109] - node _T_553 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 279:161] - node _T_554 = eq(_T_553, UInt<8>("h0c0")) @[axi4_to_ahb.scala 279:168] - node _T_555 = or(_T_552, _T_554) @[axi4_to_ahb.scala 279:145] - node _T_556 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 280:21] - node _T_557 = eq(_T_556, UInt<4>("h0f")) @[axi4_to_ahb.scala 280:28] - node _T_558 = or(_T_555, _T_557) @[axi4_to_ahb.scala 279:181] - node _T_559 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 280:56] - node _T_560 = eq(_T_559, UInt<8>("h0f0")) @[axi4_to_ahb.scala 280:63] - node _T_561 = or(_T_558, _T_560) @[axi4_to_ahb.scala 280:40] - node _T_562 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 280:92] - node _T_563 = eq(_T_562, UInt<8>("h0ff")) @[axi4_to_ahb.scala 280:99] - node _T_564 = or(_T_561, _T_563) @[axi4_to_ahb.scala 280:76] - node _T_565 = and(_T_544, _T_564) @[axi4_to_ahb.scala 279:38] - node _T_566 = or(_T_542, _T_565) @[axi4_to_ahb.scala 278:106] - buf_aligned_in <= _T_566 @[axi4_to_ahb.scala 277:18] - node _T_567 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 282:43] - node _T_568 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 282:62] - node _T_569 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 282:87] + node _T_528 = and(UInt<2>("h01"), _T_527) @[axi4_to_ahb.scala 123:21] + node _T_529 = or(_T_514, _T_528) @[axi4_to_ahb.scala 122:93] + node _T_530 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 269:161] + node _T_531 = mux(_T_499, _T_529, _T_530) @[axi4_to_ahb.scala 269:21] + buf_size_in <= _T_531 @[axi4_to_ahb.scala 269:15] + node _T_532 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 270:32] + node _T_533 = eq(_T_532, UInt<1>("h00")) @[axi4_to_ahb.scala 270:39] + node _T_534 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 271:17] + node _T_535 = eq(_T_534, UInt<1>("h00")) @[axi4_to_ahb.scala 271:24] + node _T_536 = or(_T_533, _T_535) @[axi4_to_ahb.scala 270:48] + node _T_537 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 271:47] + node _T_538 = eq(_T_537, UInt<2>("h01")) @[axi4_to_ahb.scala 271:54] + node _T_539 = or(_T_536, _T_538) @[axi4_to_ahb.scala 271:33] + node _T_540 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 271:86] + node _T_541 = eq(_T_540, UInt<2>("h02")) @[axi4_to_ahb.scala 271:93] + node _T_542 = or(_T_539, _T_541) @[axi4_to_ahb.scala 271:72] + node _T_543 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 272:18] + node _T_544 = eq(_T_543, UInt<2>("h03")) @[axi4_to_ahb.scala 272:25] + node _T_545 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:55] + node _T_546 = eq(_T_545, UInt<2>("h03")) @[axi4_to_ahb.scala 272:62] + node _T_547 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:90] + node _T_548 = eq(_T_547, UInt<4>("h0c")) @[axi4_to_ahb.scala 272:97] + node _T_549 = or(_T_546, _T_548) @[axi4_to_ahb.scala 272:74] + node _T_550 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:125] + node _T_551 = eq(_T_550, UInt<6>("h030")) @[axi4_to_ahb.scala 272:132] + node _T_552 = or(_T_549, _T_551) @[axi4_to_ahb.scala 272:109] + node _T_553 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:161] + node _T_554 = eq(_T_553, UInt<8>("h0c0")) @[axi4_to_ahb.scala 272:168] + node _T_555 = or(_T_552, _T_554) @[axi4_to_ahb.scala 272:145] + node _T_556 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 273:21] + node _T_557 = eq(_T_556, UInt<4>("h0f")) @[axi4_to_ahb.scala 273:28] + node _T_558 = or(_T_555, _T_557) @[axi4_to_ahb.scala 272:181] + node _T_559 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 273:56] + node _T_560 = eq(_T_559, UInt<8>("h0f0")) @[axi4_to_ahb.scala 273:63] + node _T_561 = or(_T_558, _T_560) @[axi4_to_ahb.scala 273:40] + node _T_562 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 273:92] + node _T_563 = eq(_T_562, UInt<8>("h0ff")) @[axi4_to_ahb.scala 273:99] + node _T_564 = or(_T_561, _T_563) @[axi4_to_ahb.scala 273:76] + node _T_565 = and(_T_544, _T_564) @[axi4_to_ahb.scala 272:38] + node _T_566 = or(_T_542, _T_565) @[axi4_to_ahb.scala 271:106] + buf_aligned_in <= _T_566 @[axi4_to_ahb.scala 270:18] + node _T_567 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 275:43] + node _T_568 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 275:62] + node _T_569 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 275:87] node _T_570 = cat(_T_568, _T_569) @[Cat.scala 29:58] - node _T_571 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 282:108] - node _T_572 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 282:133] + node _T_571 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 275:108] + node _T_572 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 275:133] node _T_573 = cat(_T_571, _T_572) @[Cat.scala 29:58] - node _T_574 = mux(_T_567, _T_570, _T_573) @[axi4_to_ahb.scala 282:26] - io.ahb.out.haddr <= _T_574 @[axi4_to_ahb.scala 282:20] - node _T_575 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 283:43] + node _T_574 = mux(_T_567, _T_570, _T_573) @[axi4_to_ahb.scala 275:26] + io.ahb.out.haddr <= _T_574 @[axi4_to_ahb.scala 275:20] + node _T_575 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 276:43] node _T_576 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15] node _T_577 = mux(_T_576, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_578 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 283:94] - node _T_579 = and(_T_577, _T_578) @[axi4_to_ahb.scala 283:81] + node _T_578 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 276:94] + node _T_579 = and(_T_577, _T_578) @[axi4_to_ahb.scala 276:81] node _T_580 = cat(UInt<1>("h00"), _T_579) @[Cat.scala 29:58] node _T_581 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15] node _T_582 = mux(_T_581, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_583 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 283:148] - node _T_584 = and(_T_582, _T_583) @[axi4_to_ahb.scala 283:138] + node _T_583 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 276:148] + node _T_584 = and(_T_582, _T_583) @[axi4_to_ahb.scala 276:138] node _T_585 = cat(UInt<1>("h00"), _T_584) @[Cat.scala 29:58] - node _T_586 = mux(_T_575, _T_580, _T_585) @[axi4_to_ahb.scala 283:26] - io.ahb.out.hsize <= _T_586 @[axi4_to_ahb.scala 283:20] - io.ahb.out.hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 285:21] - io.ahb.out.hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 286:24] - node _T_587 = bits(io.axi.ar.bits.prot, 2, 2) @[axi4_to_ahb.scala 287:57] - node _T_588 = eq(_T_587, UInt<1>("h00")) @[axi4_to_ahb.scala 287:37] + node _T_586 = mux(_T_575, _T_580, _T_585) @[axi4_to_ahb.scala 276:26] + io.ahb.out.hsize <= _T_586 @[axi4_to_ahb.scala 276:20] + io.ahb.out.hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 278:21] + io.ahb.out.hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 279:24] + node _T_587 = bits(io.axi.ar.bits.prot, 2, 2) @[axi4_to_ahb.scala 280:57] + node _T_588 = eq(_T_587, UInt<1>("h00")) @[axi4_to_ahb.scala 280:37] node _T_589 = cat(UInt<1>("h01"), _T_588) @[Cat.scala 29:58] - io.ahb.out.hprot <= _T_589 @[axi4_to_ahb.scala 287:20] - node _T_590 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 288:44] - node _T_591 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 288:59] - node _T_592 = eq(_T_591, UInt<1>("h01")) @[axi4_to_ahb.scala 288:66] - node _T_593 = mux(_T_590, _T_592, buf_write) @[axi4_to_ahb.scala 288:27] - io.ahb.out.hwrite <= _T_593 @[axi4_to_ahb.scala 288:21] - node _T_594 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 289:32] - io.ahb.out.hwdata <= _T_594 @[axi4_to_ahb.scala 289:21] - slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 291:15] - node _T_595 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 292:43] - node _T_596 = mux(_T_595, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 292:23] + io.ahb.out.hprot <= _T_589 @[axi4_to_ahb.scala 280:20] + node _T_590 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 281:44] + node _T_591 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 281:59] + node _T_592 = eq(_T_591, UInt<1>("h01")) @[axi4_to_ahb.scala 281:66] + node _T_593 = mux(_T_590, _T_592, buf_write) @[axi4_to_ahb.scala 281:27] + io.ahb.out.hwrite <= _T_593 @[axi4_to_ahb.scala 281:21] + node _T_594 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 282:32] + io.ahb.out.hwdata <= _T_594 @[axi4_to_ahb.scala 282:21] + slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 284:15] + node _T_595 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 285:43] + node _T_596 = mux(_T_595, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 285:23] node _T_597 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15] node _T_598 = mux(_T_597, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_599 = and(_T_598, UInt<2>("h02")) @[axi4_to_ahb.scala 292:88] + node _T_599 = and(_T_598, UInt<2>("h02")) @[axi4_to_ahb.scala 285:88] node _T_600 = cat(_T_596, _T_599) @[Cat.scala 29:58] - slave_opc <= _T_600 @[axi4_to_ahb.scala 292:13] - node _T_601 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 293:41] - node _T_602 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 293:66] + slave_opc <= _T_600 @[axi4_to_ahb.scala 285:13] + node _T_601 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 286:41] + node _T_602 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 286:66] node _T_603 = cat(_T_602, _T_602) @[Cat.scala 29:58] - node _T_604 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 293:91] - node _T_605 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 293:110] - node _T_606 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 293:131] - node _T_607 = mux(_T_604, _T_605, _T_606) @[axi4_to_ahb.scala 293:79] - node _T_608 = mux(_T_601, _T_603, _T_607) @[axi4_to_ahb.scala 293:21] - slave_rdata <= _T_608 @[axi4_to_ahb.scala 293:15] - node _T_609 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 294:26] - slave_tag <= _T_609 @[axi4_to_ahb.scala 294:13] - node _T_610 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 296:37] - node _T_611 = neq(_T_610, UInt<1>("h00")) @[axi4_to_ahb.scala 296:44] - node _T_612 = and(_T_611, io.ahb.in.hready) @[axi4_to_ahb.scala 296:56] - node _T_613 = and(_T_612, io.ahb.out.hwrite) @[axi4_to_ahb.scala 296:75] - last_addr_en <= _T_613 @[axi4_to_ahb.scala 296:16] - node _T_614 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 298:31] - node _T_615 = and(_T_614, master_ready) @[axi4_to_ahb.scala 298:49] - wrbuf_en <= _T_615 @[axi4_to_ahb.scala 298:12] - node _T_616 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 299:35] - node _T_617 = and(_T_616, master_ready) @[axi4_to_ahb.scala 299:52] - wrbuf_data_en <= _T_617 @[axi4_to_ahb.scala 299:17] - node _T_618 = and(master_valid, master_ready) @[axi4_to_ahb.scala 300:34] - node _T_619 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 300:62] - node _T_620 = eq(_T_619, UInt<1>("h01")) @[axi4_to_ahb.scala 300:69] - node _T_621 = and(_T_618, _T_620) @[axi4_to_ahb.scala 300:49] - wrbuf_cmd_sent <= _T_621 @[axi4_to_ahb.scala 300:18] - node _T_622 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 301:33] - node _T_623 = and(wrbuf_cmd_sent, _T_622) @[axi4_to_ahb.scala 301:31] - wrbuf_rst <= _T_623 @[axi4_to_ahb.scala 301:13] - node _T_624 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 303:36] - node _T_625 = and(wrbuf_vld, _T_624) @[axi4_to_ahb.scala 303:34] - node _T_626 = eq(_T_625, UInt<1>("h00")) @[axi4_to_ahb.scala 303:22] - node _T_627 = and(_T_626, master_ready) @[axi4_to_ahb.scala 303:53] - io.axi.aw.ready <= _T_627 @[axi4_to_ahb.scala 303:19] - node _T_628 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 304:40] - node _T_629 = and(wrbuf_data_vld, _T_628) @[axi4_to_ahb.scala 304:38] - node _T_630 = eq(_T_629, UInt<1>("h00")) @[axi4_to_ahb.scala 304:21] - node _T_631 = and(_T_630, master_ready) @[axi4_to_ahb.scala 304:57] - io.axi.w.ready <= _T_631 @[axi4_to_ahb.scala 304:18] - node _T_632 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 305:34] - node _T_633 = eq(_T_632, UInt<1>("h00")) @[axi4_to_ahb.scala 305:22] - node _T_634 = and(_T_633, master_ready) @[axi4_to_ahb.scala 305:52] - io.axi.ar.ready <= _T_634 @[axi4_to_ahb.scala 305:19] - io.axi.r.bits.last <= UInt<1>("h01") @[axi4_to_ahb.scala 306:22] - node _T_635 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 308:71] - node _T_636 = mux(_T_635, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 308:55] - node _T_637 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 308:91] - node _T_638 = and(_T_636, _T_637) @[axi4_to_ahb.scala 308:89] - reg _T_639 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 308:51] - _T_639 <= _T_638 @[axi4_to_ahb.scala 308:51] - wrbuf_vld <= _T_639 @[axi4_to_ahb.scala 308:21] - node _T_640 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 309:76] - node _T_641 = mux(_T_640, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 309:55] - node _T_642 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 309:102] - node _T_643 = and(_T_641, _T_642) @[axi4_to_ahb.scala 309:100] - reg _T_644 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 309:51] - _T_644 <= _T_643 @[axi4_to_ahb.scala 309:51] - wrbuf_data_vld <= _T_644 @[axi4_to_ahb.scala 309:21] - node _T_645 = bits(io.axi.aw.bits.id, 0, 0) @[axi4_to_ahb.scala 310:71] - node _T_646 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 310:105] + node _T_604 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 286:91] + node _T_605 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 286:110] + node _T_606 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 286:131] + node _T_607 = mux(_T_604, _T_605, _T_606) @[axi4_to_ahb.scala 286:79] + node _T_608 = mux(_T_601, _T_603, _T_607) @[axi4_to_ahb.scala 286:21] + slave_rdata <= _T_608 @[axi4_to_ahb.scala 286:15] + node _T_609 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 287:26] + slave_tag <= _T_609 @[axi4_to_ahb.scala 287:13] + node _T_610 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 289:37] + node _T_611 = neq(_T_610, UInt<1>("h00")) @[axi4_to_ahb.scala 289:44] + node _T_612 = and(_T_611, io.ahb.in.hready) @[axi4_to_ahb.scala 289:56] + node _T_613 = and(_T_612, io.ahb.out.hwrite) @[axi4_to_ahb.scala 289:75] + last_addr_en <= _T_613 @[axi4_to_ahb.scala 289:16] + node _T_614 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 291:31] + node _T_615 = and(_T_614, master_ready) @[axi4_to_ahb.scala 291:49] + wrbuf_en <= _T_615 @[axi4_to_ahb.scala 291:12] + node _T_616 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 292:35] + node _T_617 = and(_T_616, master_ready) @[axi4_to_ahb.scala 292:52] + wrbuf_data_en <= _T_617 @[axi4_to_ahb.scala 292:17] + node _T_618 = and(master_valid, master_ready) @[axi4_to_ahb.scala 293:34] + node _T_619 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 293:62] + node _T_620 = eq(_T_619, UInt<1>("h01")) @[axi4_to_ahb.scala 293:69] + node _T_621 = and(_T_618, _T_620) @[axi4_to_ahb.scala 293:49] + wrbuf_cmd_sent <= _T_621 @[axi4_to_ahb.scala 293:18] + node _T_622 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 294:33] + node _T_623 = and(wrbuf_cmd_sent, _T_622) @[axi4_to_ahb.scala 294:31] + wrbuf_rst <= _T_623 @[axi4_to_ahb.scala 294:13] + node _T_624 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 296:36] + node _T_625 = and(wrbuf_vld, _T_624) @[axi4_to_ahb.scala 296:34] + node _T_626 = eq(_T_625, UInt<1>("h00")) @[axi4_to_ahb.scala 296:22] + node _T_627 = and(_T_626, master_ready) @[axi4_to_ahb.scala 296:53] + io.axi.aw.ready <= _T_627 @[axi4_to_ahb.scala 296:19] + node _T_628 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 297:40] + node _T_629 = and(wrbuf_data_vld, _T_628) @[axi4_to_ahb.scala 297:38] + node _T_630 = eq(_T_629, UInt<1>("h00")) @[axi4_to_ahb.scala 297:21] + node _T_631 = and(_T_630, master_ready) @[axi4_to_ahb.scala 297:57] + io.axi.w.ready <= _T_631 @[axi4_to_ahb.scala 297:18] + node _T_632 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 298:34] + node _T_633 = eq(_T_632, UInt<1>("h00")) @[axi4_to_ahb.scala 298:22] + node _T_634 = and(_T_633, master_ready) @[axi4_to_ahb.scala 298:52] + io.axi.ar.ready <= _T_634 @[axi4_to_ahb.scala 298:19] + io.axi.r.bits.last <= UInt<1>("h01") @[axi4_to_ahb.scala 299:22] + node _T_635 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 301:71] + node _T_636 = mux(_T_635, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 301:55] + node _T_637 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 301:91] + node _T_638 = and(_T_636, _T_637) @[axi4_to_ahb.scala 301:89] + reg _T_639 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 301:51] + _T_639 <= _T_638 @[axi4_to_ahb.scala 301:51] + wrbuf_vld <= _T_639 @[axi4_to_ahb.scala 301:21] + node _T_640 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 302:76] + node _T_641 = mux(_T_640, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 302:55] + node _T_642 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 302:102] + node _T_643 = and(_T_641, _T_642) @[axi4_to_ahb.scala 302:100] + reg _T_644 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 302:51] + _T_644 <= _T_643 @[axi4_to_ahb.scala 302:51] + wrbuf_data_vld <= _T_644 @[axi4_to_ahb.scala 302:21] + node _T_645 = bits(io.axi.aw.bits.id, 0, 0) @[axi4_to_ahb.scala 303:71] + node _T_646 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 303:105] reg _T_647 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_646 : @[Reg.scala 28:19] _T_647 <= _T_645 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_tag <= _T_647 @[axi4_to_ahb.scala 310:21] - node _T_648 = bits(io.axi.aw.bits.size, 2, 0) @[axi4_to_ahb.scala 311:73] - node _T_649 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 311:101] + wrbuf_tag <= _T_647 @[axi4_to_ahb.scala 303:21] + node _T_648 = bits(io.axi.aw.bits.size, 2, 0) @[axi4_to_ahb.scala 304:73] + node _T_649 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 304:101] reg _T_650 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_649 : @[Reg.scala 28:19] _T_650 <= _T_648 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_size <= _T_650 @[axi4_to_ahb.scala 311:21] - node _T_651 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 312:61] + wrbuf_size <= _T_650 @[axi4_to_ahb.scala 304:21] + node _T_651 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 305:61] inst rvclkhdr_2 of rvclkhdr_851 @[lib.scala 368:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset @@ -110288,8 +110278,8 @@ circuit quasar_wrapper : rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_652 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_652 <= io.axi.aw.bits.addr @[lib.scala 374:16] - wrbuf_addr <= _T_652 @[axi4_to_ahb.scala 312:21] - node _T_653 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 313:65] + wrbuf_addr <= _T_652 @[axi4_to_ahb.scala 305:21] + node _T_653 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 306:65] inst rvclkhdr_3 of rvclkhdr_852 @[lib.scala 368:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset @@ -110298,37 +110288,37 @@ circuit quasar_wrapper : rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_654 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_654 <= io.axi.w.bits.data @[lib.scala 374:16] - wrbuf_data <= _T_654 @[axi4_to_ahb.scala 313:21] - node _T_655 = bits(io.axi.w.bits.strb, 7, 0) @[axi4_to_ahb.scala 314:72] - node _T_656 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 314:105] + wrbuf_data <= _T_654 @[axi4_to_ahb.scala 306:21] + node _T_655 = bits(io.axi.w.bits.strb, 7, 0) @[axi4_to_ahb.scala 307:72] + node _T_656 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 307:105] reg _T_657 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_656 : @[Reg.scala 28:19] _T_657 <= _T_655 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_byteen <= _T_657 @[axi4_to_ahb.scala 314:21] - node _T_658 = bits(io.ahb.out.haddr, 31, 0) @[axi4_to_ahb.scala 315:71] - node _T_659 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 315:104] + wrbuf_byteen <= _T_657 @[axi4_to_ahb.scala 307:21] + node _T_658 = bits(io.ahb.out.haddr, 31, 0) @[axi4_to_ahb.scala 308:71] + node _T_659 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 308:104] reg _T_660 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_659 : @[Reg.scala 28:19] _T_660 <= _T_658 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - last_bus_addr <= _T_660 @[axi4_to_ahb.scala 315:21] - node _T_661 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 316:89] + last_bus_addr <= _T_660 @[axi4_to_ahb.scala 308:21] + node _T_661 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 309:89] reg _T_662 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_661 : @[Reg.scala 28:19] _T_662 <= buf_write_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_write <= _T_662 @[axi4_to_ahb.scala 316:21] - node _T_663 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 317:64] - node _T_664 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 317:99] + buf_write <= _T_662 @[axi4_to_ahb.scala 309:21] + node _T_663 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 310:64] + node _T_664 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 310:99] reg _T_665 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_664 : @[Reg.scala 28:19] _T_665 <= _T_663 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_tag <= _T_665 @[axi4_to_ahb.scala 317:21] - node _T_666 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 318:42] - node _T_667 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 318:61] - node _T_668 = bits(_T_667, 0, 0) @[axi4_to_ahb.scala 318:78] + buf_tag <= _T_665 @[axi4_to_ahb.scala 310:21] + node _T_666 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 311:42] + node _T_667 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 311:61] + node _T_668 = bits(_T_667, 0, 0) @[axi4_to_ahb.scala 311:78] inst rvclkhdr_4 of rvclkhdr_853 @[lib.scala 368:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset @@ -110337,30 +110327,30 @@ circuit quasar_wrapper : rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_669 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_669 <= _T_666 @[lib.scala 374:16] - buf_addr <= _T_669 @[axi4_to_ahb.scala 318:21] - node _T_670 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 319:65] - node _T_671 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 319:94] + buf_addr <= _T_669 @[axi4_to_ahb.scala 311:21] + node _T_670 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 312:65] + node _T_671 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 312:94] reg _T_672 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_671 : @[Reg.scala 28:19] _T_672 <= _T_670 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_size <= _T_672 @[axi4_to_ahb.scala 319:21] - node _T_673 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 320:91] + buf_size <= _T_672 @[axi4_to_ahb.scala 312:21] + node _T_673 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 313:91] reg _T_674 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_673 : @[Reg.scala 28:19] _T_674 <= buf_aligned_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_aligned <= _T_674 @[axi4_to_ahb.scala 320:21] - node _T_675 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 321:67] - node _T_676 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 321:96] + buf_aligned <= _T_674 @[axi4_to_ahb.scala 313:21] + node _T_675 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 314:67] + node _T_676 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 314:96] reg _T_677 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_676 : @[Reg.scala 28:19] _T_677 <= _T_675 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_byteen <= _T_677 @[axi4_to_ahb.scala 321:21] - node _T_678 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 322:42] - node _T_679 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 322:66] - node _T_680 = bits(_T_679, 0, 0) @[axi4_to_ahb.scala 322:89] + buf_byteen <= _T_677 @[axi4_to_ahb.scala 314:21] + node _T_678 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 315:42] + node _T_679 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 315:66] + node _T_680 = bits(_T_679, 0, 0) @[axi4_to_ahb.scala 315:89] inst rvclkhdr_5 of rvclkhdr_854 @[lib.scala 368:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset @@ -110369,98 +110359,98 @@ circuit quasar_wrapper : rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_681 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_681 <= _T_678 @[lib.scala 374:16] - buf_data <= _T_681 @[axi4_to_ahb.scala 322:21] - node _T_682 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 323:89] + buf_data <= _T_681 @[axi4_to_ahb.scala 315:21] + node _T_682 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 316:89] reg _T_683 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_682 : @[Reg.scala 28:19] _T_683 <= buf_write @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_write <= _T_683 @[axi4_to_ahb.scala 323:21] - node _T_684 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 324:61] - node _T_685 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 324:99] + slvbuf_write <= _T_683 @[axi4_to_ahb.scala 316:21] + node _T_684 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 317:61] + node _T_685 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 317:99] reg _T_686 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_685 : @[Reg.scala 28:19] _T_686 <= _T_684 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_tag <= _T_686 @[axi4_to_ahb.scala 324:21] - node _T_687 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 325:99] + slvbuf_tag <= _T_686 @[axi4_to_ahb.scala 317:21] + node _T_687 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 318:99] reg _T_688 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_687 : @[Reg.scala 28:19] _T_688 <= slvbuf_error_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_error <= _T_688 @[axi4_to_ahb.scala 325:21] - node _T_689 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 326:72] - node _T_690 = mux(_T_689, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 326:56] - node _T_691 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 326:92] - node _T_692 = and(_T_690, _T_691) @[axi4_to_ahb.scala 326:90] - reg _T_693 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 326:52] - _T_693 <= _T_692 @[axi4_to_ahb.scala 326:52] - cmd_doneQ <= _T_693 @[axi4_to_ahb.scala 326:21] - node _T_694 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 327:71] - node _T_695 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 327:110] + slvbuf_error <= _T_688 @[axi4_to_ahb.scala 318:21] + node _T_689 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 319:72] + node _T_690 = mux(_T_689, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 319:56] + node _T_691 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 319:92] + node _T_692 = and(_T_690, _T_691) @[axi4_to_ahb.scala 319:90] + reg _T_693 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 319:52] + _T_693 <= _T_692 @[axi4_to_ahb.scala 319:52] + cmd_doneQ <= _T_693 @[axi4_to_ahb.scala 319:21] + node _T_694 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 320:71] + node _T_695 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 320:110] reg _T_696 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_695 : @[Reg.scala 28:19] _T_696 <= _T_694 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_cmd_byte_ptrQ <= _T_696 @[axi4_to_ahb.scala 327:21] - reg _T_697 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 328:52] - _T_697 <= io.ahb.in.hready @[axi4_to_ahb.scala 328:52] - ahb_hready_q <= _T_697 @[axi4_to_ahb.scala 328:21] - node _T_698 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 329:70] - reg _T_699 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 329:52] - _T_699 <= _T_698 @[axi4_to_ahb.scala 329:52] - ahb_htrans_q <= _T_699 @[axi4_to_ahb.scala 329:21] - reg _T_700 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 330:57] - _T_700 <= io.ahb.out.hwrite @[axi4_to_ahb.scala 330:57] - ahb_hwrite_q <= _T_700 @[axi4_to_ahb.scala 330:21] - reg _T_701 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 331:52] - _T_701 <= io.ahb.in.hresp @[axi4_to_ahb.scala 331:52] - ahb_hresp_q <= _T_701 @[axi4_to_ahb.scala 331:21] - node _T_702 = bits(io.ahb.in.hrdata, 63, 0) @[axi4_to_ahb.scala 332:74] - reg _T_703 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 332:57] - _T_703 <= _T_702 @[axi4_to_ahb.scala 332:57] - ahb_hrdata_q <= _T_703 @[axi4_to_ahb.scala 332:21] - node _T_704 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 334:43] - node _T_705 = or(_T_704, io.clk_override) @[axi4_to_ahb.scala 334:58] - node _T_706 = and(io.bus_clk_en, _T_705) @[axi4_to_ahb.scala 334:30] - buf_clken <= _T_706 @[axi4_to_ahb.scala 334:13] - node _T_707 = bits(io.ahb.out.htrans, 1, 1) @[axi4_to_ahb.scala 335:76] - node _T_708 = and(io.ahb.in.hready, _T_707) @[axi4_to_ahb.scala 335:57] - node _T_709 = or(_T_708, io.clk_override) @[axi4_to_ahb.scala 335:81] - node _T_710 = and(io.bus_clk_en, _T_709) @[axi4_to_ahb.scala 335:36] - ahbm_addr_clken <= _T_710 @[axi4_to_ahb.scala 335:19] - node _T_711 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 336:50] - node _T_712 = or(_T_711, io.clk_override) @[axi4_to_ahb.scala 336:60] - node _T_713 = and(io.bus_clk_en, _T_712) @[axi4_to_ahb.scala 336:36] - ahbm_data_clken <= _T_713 @[axi4_to_ahb.scala 336:19] + buf_cmd_byte_ptrQ <= _T_696 @[axi4_to_ahb.scala 320:21] + reg _T_697 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 321:52] + _T_697 <= io.ahb.in.hready @[axi4_to_ahb.scala 321:52] + ahb_hready_q <= _T_697 @[axi4_to_ahb.scala 321:21] + node _T_698 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 322:70] + reg _T_699 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 322:52] + _T_699 <= _T_698 @[axi4_to_ahb.scala 322:52] + ahb_htrans_q <= _T_699 @[axi4_to_ahb.scala 322:21] + reg _T_700 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 323:57] + _T_700 <= io.ahb.out.hwrite @[axi4_to_ahb.scala 323:57] + ahb_hwrite_q <= _T_700 @[axi4_to_ahb.scala 323:21] + reg _T_701 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 324:52] + _T_701 <= io.ahb.in.hresp @[axi4_to_ahb.scala 324:52] + ahb_hresp_q <= _T_701 @[axi4_to_ahb.scala 324:21] + node _T_702 = bits(io.ahb.in.hrdata, 63, 0) @[axi4_to_ahb.scala 325:74] + reg _T_703 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 325:57] + _T_703 <= _T_702 @[axi4_to_ahb.scala 325:57] + ahb_hrdata_q <= _T_703 @[axi4_to_ahb.scala 325:21] + node _T_704 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 327:43] + node _T_705 = or(_T_704, io.clk_override) @[axi4_to_ahb.scala 327:58] + node _T_706 = and(io.bus_clk_en, _T_705) @[axi4_to_ahb.scala 327:30] + buf_clken <= _T_706 @[axi4_to_ahb.scala 327:13] + node _T_707 = bits(io.ahb.out.htrans, 1, 1) @[axi4_to_ahb.scala 328:76] + node _T_708 = and(io.ahb.in.hready, _T_707) @[axi4_to_ahb.scala 328:57] + node _T_709 = or(_T_708, io.clk_override) @[axi4_to_ahb.scala 328:81] + node _T_710 = and(io.bus_clk_en, _T_709) @[axi4_to_ahb.scala 328:36] + ahbm_addr_clken <= _T_710 @[axi4_to_ahb.scala 328:19] + node _T_711 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 329:50] + node _T_712 = or(_T_711, io.clk_override) @[axi4_to_ahb.scala 329:60] + node _T_713 = and(io.bus_clk_en, _T_712) @[axi4_to_ahb.scala 329:36] + ahbm_data_clken <= _T_713 @[axi4_to_ahb.scala 329:19] inst rvclkhdr_6 of rvclkhdr_855 @[lib.scala 343:22] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset rvclkhdr_6.io.clk <= clock @[lib.scala 344:17] rvclkhdr_6.io.en <= buf_clken @[lib.scala 345:16] rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 339:12] + buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 332:12] inst rvclkhdr_7 of rvclkhdr_856 @[lib.scala 343:22] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= reset rvclkhdr_7.io.clk <= clock @[lib.scala 344:17] rvclkhdr_7.io.en <= io.bus_clk_en @[lib.scala 345:16] rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 340:12] + ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 333:12] inst rvclkhdr_8 of rvclkhdr_857 @[lib.scala 343:22] rvclkhdr_8.clock <= clock rvclkhdr_8.reset <= reset rvclkhdr_8.io.clk <= clock @[lib.scala 344:17] rvclkhdr_8.io.en <= ahbm_addr_clken @[lib.scala 345:16] rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 341:17] + ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 334:17] inst rvclkhdr_9 of rvclkhdr_858 @[lib.scala 343:22] rvclkhdr_9.clock <= clock rvclkhdr_9.reset <= reset rvclkhdr_9.io.clk <= clock @[lib.scala 344:17] rvclkhdr_9.io.en <= ahbm_data_clken @[lib.scala 345:16] rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 342:17] + ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 335:17] extmodule gated_latch_859 : output Q : Clock @@ -110705,36 +110695,36 @@ circuit quasar_wrapper : module axi4_to_ahb_1 : input clock : Clock input reset : AsyncReset - output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ahb : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}} + output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ahb : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}} wire buf_rst : UInt<1> buf_rst <= UInt<1>("h00") - buf_rst <= UInt<1>("h00") @[axi4_to_ahb.scala 28:11] - io.ahb.out.htrans <= UInt<1>("h00") @[axi4_to_ahb.scala 29:21] + buf_rst <= UInt<1>("h00") @[axi4_to_ahb.scala 21:11] + io.ahb.out.htrans <= UInt<1>("h00") @[axi4_to_ahb.scala 22:21] wire buf_state_en : UInt<1> buf_state_en <= UInt<1>("h00") - wire ahbm_clk : Clock @[axi4_to_ahb.scala 31:22] - wire ahbm_addr_clk : Clock @[axi4_to_ahb.scala 32:27] - wire ahbm_data_clk : Clock @[axi4_to_ahb.scala 33:27] + wire ahbm_clk : Clock @[axi4_to_ahb.scala 24:22] + wire ahbm_addr_clk : Clock @[axi4_to_ahb.scala 25:27] + wire ahbm_data_clk : Clock @[axi4_to_ahb.scala 26:27] wire buf_state : UInt<3> buf_state <= UInt<3>("h00") wire buf_nxtstate : UInt<3> buf_nxtstate <= UInt<3>("h00") - node _T = bits(buf_state_en, 0, 0) @[axi4_to_ahb.scala 37:70] - node _T_1 = mux(_T, buf_nxtstate, buf_state) @[axi4_to_ahb.scala 37:50] - node _T_2 = eq(buf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 37:108] + node _T = bits(buf_state_en, 0, 0) @[axi4_to_ahb.scala 30:70] + node _T_1 = mux(_T, buf_nxtstate, buf_state) @[axi4_to_ahb.scala 30:50] + node _T_2 = eq(buf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 30:108] node _T_3 = bits(_T_2, 0, 0) @[Bitwise.scala 72:15] node _T_4 = mux(_T_3, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_5 = and(_T_1, _T_4) @[axi4_to_ahb.scala 37:98] - reg _T_6 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 37:45] - _T_6 <= _T_5 @[axi4_to_ahb.scala 37:45] - buf_state <= _T_6 @[axi4_to_ahb.scala 37:13] + node _T_5 = and(_T_1, _T_4) @[axi4_to_ahb.scala 30:98] + reg _T_6 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 30:45] + _T_6 <= _T_5 @[axi4_to_ahb.scala 30:45] + buf_state <= _T_6 @[axi4_to_ahb.scala 30:13] wire slave_valid : UInt<1> slave_valid <= UInt<1>("h00") wire slave_ready : UInt<1> slave_ready <= UInt<1>("h00") - wire slave_tag : UInt<1> - slave_tag <= UInt<1>("h00") + wire slave_tag : UInt<3> + slave_tag <= UInt<3>("h00") wire slave_rdata : UInt<64> slave_rdata <= UInt<64>("h00") wire slave_opc : UInt<4> @@ -110751,8 +110741,8 @@ circuit quasar_wrapper : wrbuf_vld <= UInt<1>("h00") wire wrbuf_data_vld : UInt<1> wrbuf_data_vld <= UInt<1>("h00") - wire wrbuf_tag : UInt<1> - wrbuf_tag <= UInt<1>("h00") + wire wrbuf_tag : UInt<3> + wrbuf_tag <= UInt<3>("h00") wire wrbuf_size : UInt<3> wrbuf_size <= UInt<3>("h00") wire wrbuf_addr : UInt<32> @@ -110763,14 +110753,14 @@ circuit quasar_wrapper : wrbuf_byteen <= UInt<8>("h00") wire bus_write_clk_en : UInt<1> bus_write_clk_en <= UInt<1>("h00") - wire bus_clk : Clock @[axi4_to_ahb.scala 57:21] - wire bus_write_clk : Clock @[axi4_to_ahb.scala 58:27] + wire bus_clk : Clock @[axi4_to_ahb.scala 50:21] + wire bus_write_clk : Clock @[axi4_to_ahb.scala 51:27] wire master_valid : UInt<1> master_valid <= UInt<1>("h00") wire master_ready : UInt<1> master_ready <= UInt<1>("h00") - wire master_tag : UInt<1> - master_tag <= UInt<1>("h00") + wire master_tag : UInt<3> + master_tag <= UInt<3>("h00") wire master_addr : UInt<32> master_addr <= UInt<32>("h00") wire master_wdata : UInt<64> @@ -110793,10 +110783,10 @@ circuit quasar_wrapper : buf_aligned <= UInt<1>("h00") wire buf_data : UInt<64> buf_data <= UInt<64>("h00") - wire buf_tag : UInt<1> - buf_tag <= UInt<1>("h00") - wire buf_tag_in : UInt<1> - buf_tag_in <= UInt<1>("h00") + wire buf_tag : UInt<3> + buf_tag <= UInt<3>("h00") + wire buf_tag_in : UInt<3> + buf_tag_in <= UInt<3>("h00") wire buf_addr_in : UInt<32> buf_addr_in <= UInt<32>("h00") wire buf_byteen_in : UInt<8> @@ -110851,8 +110841,8 @@ circuit quasar_wrapper : slvbuf_write <= UInt<1>("h00") wire slvbuf_error : UInt<1> slvbuf_error <= UInt<1>("h00") - wire slvbuf_tag : UInt<1> - slvbuf_tag <= UInt<1>("h00") + wire slvbuf_tag : UInt<3> + slvbuf_tag <= UInt<3>("h00") wire slvbuf_error_in : UInt<1> slvbuf_error_in <= UInt<1>("h00") wire slvbuf_wr_en : UInt<1> @@ -110873,125 +110863,125 @@ circuit quasar_wrapper : ahbm_addr_clken <= UInt<1>("h00") wire ahbm_data_clken : UInt<1> ahbm_data_clken <= UInt<1>("h00") - wire buf_clk : Clock @[axi4_to_ahb.scala 125:21] - node _T_7 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 146:27] - wr_cmd_vld <= _T_7 @[axi4_to_ahb.scala 146:14] - node _T_8 = or(wr_cmd_vld, io.axi.ar.valid) @[axi4_to_ahb.scala 147:30] - master_valid <= _T_8 @[axi4_to_ahb.scala 147:16] - node _T_9 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 148:38] - node _T_10 = bits(wrbuf_tag, 0, 0) @[axi4_to_ahb.scala 148:51] - node _T_11 = bits(io.axi.ar.bits.id, 0, 0) @[axi4_to_ahb.scala 148:82] - node _T_12 = mux(_T_9, _T_10, _T_11) @[axi4_to_ahb.scala 148:20] - master_tag <= _T_12 @[axi4_to_ahb.scala 148:14] - node _T_13 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 149:38] - node _T_14 = mux(_T_13, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 149:20] - master_opc <= _T_14 @[axi4_to_ahb.scala 149:14] - node _T_15 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 150:39] - node _T_16 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 150:53] - node _T_17 = bits(io.axi.ar.bits.addr, 31, 0) @[axi4_to_ahb.scala 150:81] - node _T_18 = mux(_T_15, _T_16, _T_17) @[axi4_to_ahb.scala 150:21] - master_addr <= _T_18 @[axi4_to_ahb.scala 150:15] - node _T_19 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 151:39] - node _T_20 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 151:53] - node _T_21 = bits(io.axi.ar.bits.size, 2, 0) @[axi4_to_ahb.scala 151:80] - node _T_22 = mux(_T_19, _T_20, _T_21) @[axi4_to_ahb.scala 151:21] - master_size <= _T_22 @[axi4_to_ahb.scala 151:15] - node _T_23 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 152:32] - master_byteen <= _T_23 @[axi4_to_ahb.scala 152:17] - node _T_24 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 153:29] - master_wdata <= _T_24 @[axi4_to_ahb.scala 153:16] - node _T_25 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 156:33] - node _T_26 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 156:58] - node _T_27 = and(_T_25, _T_26) @[axi4_to_ahb.scala 156:47] - io.axi.b.valid <= _T_27 @[axi4_to_ahb.scala 156:18] - node _T_28 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 157:38] - node _T_29 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 157:65] - node _T_30 = mux(_T_29, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 157:55] - node _T_31 = mux(_T_28, UInt<2>("h02"), _T_30) @[axi4_to_ahb.scala 157:28] - io.axi.b.bits.resp <= _T_31 @[axi4_to_ahb.scala 157:22] - node _T_32 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 158:32] - io.axi.b.bits.id <= _T_32 @[axi4_to_ahb.scala 158:20] - node _T_33 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 160:33] - node _T_34 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 160:59] - node _T_35 = eq(_T_34, UInt<1>("h00")) @[axi4_to_ahb.scala 160:66] - node _T_36 = and(_T_33, _T_35) @[axi4_to_ahb.scala 160:47] - io.axi.r.valid <= _T_36 @[axi4_to_ahb.scala 160:18] - node _T_37 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 161:38] - node _T_38 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 161:65] - node _T_39 = mux(_T_38, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 161:55] - node _T_40 = mux(_T_37, UInt<2>("h02"), _T_39) @[axi4_to_ahb.scala 161:28] - io.axi.r.bits.resp <= _T_40 @[axi4_to_ahb.scala 161:22] - node _T_41 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 162:32] - io.axi.r.bits.id <= _T_41 @[axi4_to_ahb.scala 162:20] - node _T_42 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 163:36] - io.axi.r.bits.data <= _T_42 @[axi4_to_ahb.scala 163:22] - node _T_43 = and(io.axi.b.ready, io.axi.r.ready) @[axi4_to_ahb.scala 164:33] - slave_ready <= _T_43 @[axi4_to_ahb.scala 164:15] - node _T_44 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 167:57] - node _T_45 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 167:94] - node _T_46 = or(_T_44, _T_45) @[axi4_to_ahb.scala 167:76] - node _T_47 = and(io.bus_clk_en, _T_46) @[axi4_to_ahb.scala 167:37] - bus_write_clk_en <= _T_47 @[axi4_to_ahb.scala 167:20] + wire buf_clk : Clock @[axi4_to_ahb.scala 118:21] + node _T_7 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 139:27] + wr_cmd_vld <= _T_7 @[axi4_to_ahb.scala 139:14] + node _T_8 = or(wr_cmd_vld, io.axi.ar.valid) @[axi4_to_ahb.scala 140:30] + master_valid <= _T_8 @[axi4_to_ahb.scala 140:16] + node _T_9 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 141:38] + node _T_10 = bits(wrbuf_tag, 2, 0) @[axi4_to_ahb.scala 141:51] + node _T_11 = bits(io.axi.ar.bits.id, 2, 0) @[axi4_to_ahb.scala 141:82] + node _T_12 = mux(_T_9, _T_10, _T_11) @[axi4_to_ahb.scala 141:20] + master_tag <= _T_12 @[axi4_to_ahb.scala 141:14] + node _T_13 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 142:38] + node _T_14 = mux(_T_13, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 142:20] + master_opc <= _T_14 @[axi4_to_ahb.scala 142:14] + node _T_15 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 143:39] + node _T_16 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 143:53] + node _T_17 = bits(io.axi.ar.bits.addr, 31, 0) @[axi4_to_ahb.scala 143:81] + node _T_18 = mux(_T_15, _T_16, _T_17) @[axi4_to_ahb.scala 143:21] + master_addr <= _T_18 @[axi4_to_ahb.scala 143:15] + node _T_19 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 144:39] + node _T_20 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 144:53] + node _T_21 = bits(io.axi.ar.bits.size, 2, 0) @[axi4_to_ahb.scala 144:80] + node _T_22 = mux(_T_19, _T_20, _T_21) @[axi4_to_ahb.scala 144:21] + master_size <= _T_22 @[axi4_to_ahb.scala 144:15] + node _T_23 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 145:32] + master_byteen <= _T_23 @[axi4_to_ahb.scala 145:17] + node _T_24 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 146:29] + master_wdata <= _T_24 @[axi4_to_ahb.scala 146:16] + node _T_25 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 149:33] + node _T_26 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 149:58] + node _T_27 = and(_T_25, _T_26) @[axi4_to_ahb.scala 149:47] + io.axi.b.valid <= _T_27 @[axi4_to_ahb.scala 149:18] + node _T_28 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 150:38] + node _T_29 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 150:65] + node _T_30 = mux(_T_29, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 150:55] + node _T_31 = mux(_T_28, UInt<2>("h02"), _T_30) @[axi4_to_ahb.scala 150:28] + io.axi.b.bits.resp <= _T_31 @[axi4_to_ahb.scala 150:22] + node _T_32 = bits(slave_tag, 2, 0) @[axi4_to_ahb.scala 151:32] + io.axi.b.bits.id <= _T_32 @[axi4_to_ahb.scala 151:20] + node _T_33 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 153:33] + node _T_34 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 153:59] + node _T_35 = eq(_T_34, UInt<1>("h00")) @[axi4_to_ahb.scala 153:66] + node _T_36 = and(_T_33, _T_35) @[axi4_to_ahb.scala 153:47] + io.axi.r.valid <= _T_36 @[axi4_to_ahb.scala 153:18] + node _T_37 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 154:38] + node _T_38 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 154:65] + node _T_39 = mux(_T_38, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 154:55] + node _T_40 = mux(_T_37, UInt<2>("h02"), _T_39) @[axi4_to_ahb.scala 154:28] + io.axi.r.bits.resp <= _T_40 @[axi4_to_ahb.scala 154:22] + node _T_41 = bits(slave_tag, 2, 0) @[axi4_to_ahb.scala 155:32] + io.axi.r.bits.id <= _T_41 @[axi4_to_ahb.scala 155:20] + node _T_42 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 156:36] + io.axi.r.bits.data <= _T_42 @[axi4_to_ahb.scala 156:22] + node _T_43 = and(io.axi.b.ready, io.axi.r.ready) @[axi4_to_ahb.scala 157:33] + slave_ready <= _T_43 @[axi4_to_ahb.scala 157:15] + node _T_44 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 160:57] + node _T_45 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 160:94] + node _T_46 = or(_T_44, _T_45) @[axi4_to_ahb.scala 160:76] + node _T_47 = and(io.bus_clk_en, _T_46) @[axi4_to_ahb.scala 160:37] + bus_write_clk_en <= _T_47 @[axi4_to_ahb.scala 160:20] inst rvclkhdr of rvclkhdr_859 @[lib.scala 343:22] rvclkhdr.clock <= clock rvclkhdr.reset <= reset rvclkhdr.io.clk <= clock @[lib.scala 344:17] rvclkhdr.io.en <= io.bus_clk_en @[lib.scala 345:16] rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - bus_clk <= rvclkhdr.io.l1clk @[axi4_to_ahb.scala 169:11] - node _T_48 = bits(bus_write_clk_en, 0, 0) @[axi4_to_ahb.scala 170:59] + bus_clk <= rvclkhdr.io.l1clk @[axi4_to_ahb.scala 162:11] + node _T_48 = bits(bus_write_clk_en, 0, 0) @[axi4_to_ahb.scala 163:59] inst rvclkhdr_1 of rvclkhdr_860 @[lib.scala 343:22] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] rvclkhdr_1.io.en <= _T_48 @[lib.scala 345:16] rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - bus_write_clk <= rvclkhdr_1.io.l1clk @[axi4_to_ahb.scala 170:17] + bus_write_clk <= rvclkhdr_1.io.l1clk @[axi4_to_ahb.scala 163:17] node _T_49 = eq(UInt<3>("h00"), buf_state) @[Conditional.scala 37:30] when _T_49 : @[Conditional.scala 40:58] - master_ready <= UInt<1>("h01") @[axi4_to_ahb.scala 174:20] - node _T_50 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 175:34] - node _T_51 = eq(_T_50, UInt<1>("h01")) @[axi4_to_ahb.scala 175:41] - buf_write_in <= _T_51 @[axi4_to_ahb.scala 175:20] - node _T_52 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 176:46] - node _T_53 = mux(_T_52, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 176:26] - buf_nxtstate <= _T_53 @[axi4_to_ahb.scala 176:20] - node _T_54 = and(master_valid, UInt<1>("h01")) @[axi4_to_ahb.scala 177:36] - buf_state_en <= _T_54 @[axi4_to_ahb.scala 177:20] - buf_wr_en <= buf_state_en @[axi4_to_ahb.scala 178:17] - node _T_55 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 179:54] - node _T_56 = and(buf_state_en, _T_55) @[axi4_to_ahb.scala 179:38] - buf_data_wr_en <= _T_56 @[axi4_to_ahb.scala 179:22] - buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 180:27] - node _T_57 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 182:50] - node _T_58 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 182:94] - node _T_59 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 142:52] - node _T_60 = tail(_T_59, 1) @[axi4_to_ahb.scala 142:52] - node _T_61 = mux(UInt<1>("h00"), _T_60, UInt<3>("h00")) @[axi4_to_ahb.scala 142:24] - node _T_62 = bits(_T_58, 0, 0) @[axi4_to_ahb.scala 143:44] - node _T_63 = geq(UInt<1>("h00"), _T_61) @[axi4_to_ahb.scala 143:62] - node _T_64 = and(_T_62, _T_63) @[axi4_to_ahb.scala 143:48] - node _T_65 = bits(_T_58, 1, 1) @[axi4_to_ahb.scala 143:44] - node _T_66 = geq(UInt<1>("h01"), _T_61) @[axi4_to_ahb.scala 143:62] - node _T_67 = and(_T_65, _T_66) @[axi4_to_ahb.scala 143:48] - node _T_68 = bits(_T_58, 2, 2) @[axi4_to_ahb.scala 143:44] - node _T_69 = geq(UInt<2>("h02"), _T_61) @[axi4_to_ahb.scala 143:62] - node _T_70 = and(_T_68, _T_69) @[axi4_to_ahb.scala 143:48] - node _T_71 = bits(_T_58, 3, 3) @[axi4_to_ahb.scala 143:44] - node _T_72 = geq(UInt<2>("h03"), _T_61) @[axi4_to_ahb.scala 143:62] - node _T_73 = and(_T_71, _T_72) @[axi4_to_ahb.scala 143:48] - node _T_74 = bits(_T_58, 4, 4) @[axi4_to_ahb.scala 143:44] - node _T_75 = geq(UInt<3>("h04"), _T_61) @[axi4_to_ahb.scala 143:62] - node _T_76 = and(_T_74, _T_75) @[axi4_to_ahb.scala 143:48] - node _T_77 = bits(_T_58, 5, 5) @[axi4_to_ahb.scala 143:44] - node _T_78 = geq(UInt<3>("h05"), _T_61) @[axi4_to_ahb.scala 143:62] - node _T_79 = and(_T_77, _T_78) @[axi4_to_ahb.scala 143:48] - node _T_80 = bits(_T_58, 6, 6) @[axi4_to_ahb.scala 143:44] - node _T_81 = geq(UInt<3>("h06"), _T_61) @[axi4_to_ahb.scala 143:62] - node _T_82 = and(_T_80, _T_81) @[axi4_to_ahb.scala 143:48] - node _T_83 = bits(_T_58, 7, 7) @[axi4_to_ahb.scala 143:44] - node _T_84 = geq(UInt<3>("h07"), _T_61) @[axi4_to_ahb.scala 143:62] - node _T_85 = and(_T_83, _T_84) @[axi4_to_ahb.scala 143:48] + master_ready <= UInt<1>("h01") @[axi4_to_ahb.scala 167:20] + node _T_50 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 168:34] + node _T_51 = eq(_T_50, UInt<1>("h01")) @[axi4_to_ahb.scala 168:41] + buf_write_in <= _T_51 @[axi4_to_ahb.scala 168:20] + node _T_52 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 169:46] + node _T_53 = mux(_T_52, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 169:26] + buf_nxtstate <= _T_53 @[axi4_to_ahb.scala 169:20] + node _T_54 = and(master_valid, UInt<1>("h01")) @[axi4_to_ahb.scala 170:36] + buf_state_en <= _T_54 @[axi4_to_ahb.scala 170:20] + buf_wr_en <= buf_state_en @[axi4_to_ahb.scala 171:17] + node _T_55 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 172:54] + node _T_56 = and(buf_state_en, _T_55) @[axi4_to_ahb.scala 172:38] + buf_data_wr_en <= _T_56 @[axi4_to_ahb.scala 172:22] + buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 173:27] + node _T_57 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 175:50] + node _T_58 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 175:94] + node _T_59 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] + node _T_60 = tail(_T_59, 1) @[axi4_to_ahb.scala 135:52] + node _T_61 = mux(UInt<1>("h00"), _T_60, UInt<3>("h00")) @[axi4_to_ahb.scala 135:24] + node _T_62 = bits(_T_58, 0, 0) @[axi4_to_ahb.scala 136:44] + node _T_63 = geq(UInt<1>("h00"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_64 = and(_T_62, _T_63) @[axi4_to_ahb.scala 136:48] + node _T_65 = bits(_T_58, 1, 1) @[axi4_to_ahb.scala 136:44] + node _T_66 = geq(UInt<1>("h01"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_67 = and(_T_65, _T_66) @[axi4_to_ahb.scala 136:48] + node _T_68 = bits(_T_58, 2, 2) @[axi4_to_ahb.scala 136:44] + node _T_69 = geq(UInt<2>("h02"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_70 = and(_T_68, _T_69) @[axi4_to_ahb.scala 136:48] + node _T_71 = bits(_T_58, 3, 3) @[axi4_to_ahb.scala 136:44] + node _T_72 = geq(UInt<2>("h03"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_73 = and(_T_71, _T_72) @[axi4_to_ahb.scala 136:48] + node _T_74 = bits(_T_58, 4, 4) @[axi4_to_ahb.scala 136:44] + node _T_75 = geq(UInt<3>("h04"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_76 = and(_T_74, _T_75) @[axi4_to_ahb.scala 136:48] + node _T_77 = bits(_T_58, 5, 5) @[axi4_to_ahb.scala 136:44] + node _T_78 = geq(UInt<3>("h05"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_79 = and(_T_77, _T_78) @[axi4_to_ahb.scala 136:48] + node _T_80 = bits(_T_58, 6, 6) @[axi4_to_ahb.scala 136:44] + node _T_81 = geq(UInt<3>("h06"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_82 = and(_T_80, _T_81) @[axi4_to_ahb.scala 136:48] + node _T_83 = bits(_T_58, 7, 7) @[axi4_to_ahb.scala 136:44] + node _T_84 = geq(UInt<3>("h07"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_85 = and(_T_83, _T_84) @[axi4_to_ahb.scala 136:48] node _T_86 = mux(_T_85, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_87 = mux(_T_82, UInt<3>("h06"), _T_86) @[Mux.scala 98:16] node _T_88 = mux(_T_79, UInt<3>("h05"), _T_87) @[Mux.scala 98:16] @@ -111000,193 +110990,193 @@ circuit quasar_wrapper : node _T_91 = mux(_T_70, UInt<2>("h02"), _T_90) @[Mux.scala 98:16] node _T_92 = mux(_T_67, UInt<1>("h01"), _T_91) @[Mux.scala 98:16] node _T_93 = mux(_T_64, UInt<1>("h00"), _T_92) @[Mux.scala 98:16] - node _T_94 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 182:124] - node _T_95 = mux(_T_57, _T_93, _T_94) @[axi4_to_ahb.scala 182:30] - buf_cmd_byte_ptr <= _T_95 @[axi4_to_ahb.scala 182:24] - bypass_en <= buf_state_en @[axi4_to_ahb.scala 183:17] - node _T_96 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 184:51] - node _T_97 = and(bypass_en, _T_96) @[axi4_to_ahb.scala 184:35] - rd_bypass_idle <= _T_97 @[axi4_to_ahb.scala 184:22] + node _T_94 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 175:124] + node _T_95 = mux(_T_57, _T_93, _T_94) @[axi4_to_ahb.scala 175:30] + buf_cmd_byte_ptr <= _T_95 @[axi4_to_ahb.scala 175:24] + bypass_en <= buf_state_en @[axi4_to_ahb.scala 176:17] + node _T_96 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 177:51] + node _T_97 = and(bypass_en, _T_96) @[axi4_to_ahb.scala 177:35] + rd_bypass_idle <= _T_97 @[axi4_to_ahb.scala 177:22] node _T_98 = bits(bypass_en, 0, 0) @[Bitwise.scala 72:15] node _T_99 = mux(_T_98, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_100 = and(_T_99, UInt<2>("h02")) @[axi4_to_ahb.scala 185:49] - io.ahb.out.htrans <= _T_100 @[axi4_to_ahb.scala 185:25] + node _T_100 = and(_T_99, UInt<2>("h02")) @[axi4_to_ahb.scala 178:49] + io.ahb.out.htrans <= _T_100 @[axi4_to_ahb.scala 178:25] skip @[Conditional.scala 40:58] else : @[Conditional.scala 39:67] node _T_101 = eq(UInt<3>("h01"), buf_state) @[Conditional.scala 37:30] when _T_101 : @[Conditional.scala 39:67] - node _T_102 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 189:54] - node _T_103 = eq(_T_102, UInt<1>("h00")) @[axi4_to_ahb.scala 189:61] - node _T_104 = and(master_valid, _T_103) @[axi4_to_ahb.scala 189:41] - node _T_105 = bits(_T_104, 0, 0) @[axi4_to_ahb.scala 189:82] - node _T_106 = mux(_T_105, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 189:26] - buf_nxtstate <= _T_106 @[axi4_to_ahb.scala 189:20] - node _T_107 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 190:51] - node _T_108 = neq(_T_107, UInt<1>("h00")) @[axi4_to_ahb.scala 190:58] - node _T_109 = and(ahb_hready_q, _T_108) @[axi4_to_ahb.scala 190:36] - node _T_110 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 190:72] - node _T_111 = and(_T_109, _T_110) @[axi4_to_ahb.scala 190:70] - buf_state_en <= _T_111 @[axi4_to_ahb.scala 190:20] - node _T_112 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 191:34] - node _T_113 = and(buf_state_en, _T_112) @[axi4_to_ahb.scala 191:32] - cmd_done <= _T_113 @[axi4_to_ahb.scala 191:16] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 192:20] - node _T_114 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 193:52] - node _T_115 = neq(_T_114, UInt<1>("h00")) @[axi4_to_ahb.scala 193:59] - node _T_116 = and(ahb_hready_q, _T_115) @[axi4_to_ahb.scala 193:37] - node _T_117 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 193:73] - node _T_118 = and(_T_116, _T_117) @[axi4_to_ahb.scala 193:71] - node _T_119 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 193:122] - node _T_120 = eq(_T_119, UInt<1>("h00")) @[axi4_to_ahb.scala 193:129] - node _T_121 = and(master_valid, _T_120) @[axi4_to_ahb.scala 193:109] - node _T_122 = bits(_T_121, 0, 0) @[axi4_to_ahb.scala 193:150] - node _T_123 = mux(_T_122, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 193:94] - node _T_124 = eq(_T_123, UInt<3>("h06")) @[axi4_to_ahb.scala 193:174] - node _T_125 = and(_T_118, _T_124) @[axi4_to_ahb.scala 193:88] - master_ready <= _T_125 @[axi4_to_ahb.scala 193:20] - buf_wr_en <= master_ready @[axi4_to_ahb.scala 194:17] - node _T_126 = and(master_ready, master_valid) @[axi4_to_ahb.scala 195:33] - bypass_en <= _T_126 @[axi4_to_ahb.scala 195:17] - node _T_127 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 196:47] - node _T_128 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 196:62] - node _T_129 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 196:78] - node _T_130 = mux(_T_127, _T_128, _T_129) @[axi4_to_ahb.scala 196:30] - buf_cmd_byte_ptr <= _T_130 @[axi4_to_ahb.scala 196:24] - node _T_131 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 197:48] - node _T_132 = or(_T_131, bypass_en) @[axi4_to_ahb.scala 197:62] + node _T_102 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 182:54] + node _T_103 = eq(_T_102, UInt<1>("h00")) @[axi4_to_ahb.scala 182:61] + node _T_104 = and(master_valid, _T_103) @[axi4_to_ahb.scala 182:41] + node _T_105 = bits(_T_104, 0, 0) @[axi4_to_ahb.scala 182:82] + node _T_106 = mux(_T_105, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 182:26] + buf_nxtstate <= _T_106 @[axi4_to_ahb.scala 182:20] + node _T_107 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 183:51] + node _T_108 = neq(_T_107, UInt<1>("h00")) @[axi4_to_ahb.scala 183:58] + node _T_109 = and(ahb_hready_q, _T_108) @[axi4_to_ahb.scala 183:36] + node _T_110 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 183:72] + node _T_111 = and(_T_109, _T_110) @[axi4_to_ahb.scala 183:70] + buf_state_en <= _T_111 @[axi4_to_ahb.scala 183:20] + node _T_112 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 184:34] + node _T_113 = and(buf_state_en, _T_112) @[axi4_to_ahb.scala 184:32] + cmd_done <= _T_113 @[axi4_to_ahb.scala 184:16] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 185:20] + node _T_114 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 186:52] + node _T_115 = neq(_T_114, UInt<1>("h00")) @[axi4_to_ahb.scala 186:59] + node _T_116 = and(ahb_hready_q, _T_115) @[axi4_to_ahb.scala 186:37] + node _T_117 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 186:73] + node _T_118 = and(_T_116, _T_117) @[axi4_to_ahb.scala 186:71] + node _T_119 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 186:122] + node _T_120 = eq(_T_119, UInt<1>("h00")) @[axi4_to_ahb.scala 186:129] + node _T_121 = and(master_valid, _T_120) @[axi4_to_ahb.scala 186:109] + node _T_122 = bits(_T_121, 0, 0) @[axi4_to_ahb.scala 186:150] + node _T_123 = mux(_T_122, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 186:94] + node _T_124 = eq(_T_123, UInt<3>("h06")) @[axi4_to_ahb.scala 186:174] + node _T_125 = and(_T_118, _T_124) @[axi4_to_ahb.scala 186:88] + master_ready <= _T_125 @[axi4_to_ahb.scala 186:20] + buf_wr_en <= master_ready @[axi4_to_ahb.scala 187:17] + node _T_126 = and(master_ready, master_valid) @[axi4_to_ahb.scala 188:33] + bypass_en <= _T_126 @[axi4_to_ahb.scala 188:17] + node _T_127 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 189:47] + node _T_128 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 189:62] + node _T_129 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 189:78] + node _T_130 = mux(_T_127, _T_128, _T_129) @[axi4_to_ahb.scala 189:30] + buf_cmd_byte_ptr <= _T_130 @[axi4_to_ahb.scala 189:24] + node _T_131 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 190:48] + node _T_132 = or(_T_131, bypass_en) @[axi4_to_ahb.scala 190:62] node _T_133 = bits(_T_132, 0, 0) @[Bitwise.scala 72:15] node _T_134 = mux(_T_133, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_135 = and(UInt<2>("h02"), _T_134) @[axi4_to_ahb.scala 197:36] - io.ahb.out.htrans <= _T_135 @[axi4_to_ahb.scala 197:25] + node _T_135 = and(UInt<2>("h02"), _T_134) @[axi4_to_ahb.scala 190:36] + io.ahb.out.htrans <= _T_135 @[axi4_to_ahb.scala 190:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_136 = eq(UInt<3>("h06"), buf_state) @[Conditional.scala 37:30] when _T_136 : @[Conditional.scala 39:67] - node _T_137 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 201:39] - node _T_138 = and(ahb_hready_q, _T_137) @[axi4_to_ahb.scala 201:37] - node _T_139 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 201:82] - node _T_140 = eq(_T_139, UInt<1>("h01")) @[axi4_to_ahb.scala 201:89] - node _T_141 = and(master_valid, _T_140) @[axi4_to_ahb.scala 201:70] - node _T_142 = not(_T_141) @[axi4_to_ahb.scala 201:55] - node _T_143 = and(_T_138, _T_142) @[axi4_to_ahb.scala 201:53] - master_ready <= _T_143 @[axi4_to_ahb.scala 201:20] - node _T_144 = and(master_valid, master_ready) @[axi4_to_ahb.scala 202:34] - node _T_145 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 202:62] - node _T_146 = eq(_T_145, UInt<1>("h00")) @[axi4_to_ahb.scala 202:69] - node _T_147 = and(_T_144, _T_146) @[axi4_to_ahb.scala 202:49] - buf_wr_en <= _T_147 @[axi4_to_ahb.scala 202:17] - node _T_148 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 203:45] - node _T_149 = and(master_valid, master_ready) @[axi4_to_ahb.scala 203:82] - node _T_150 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 203:110] - node _T_151 = eq(_T_150, UInt<1>("h00")) @[axi4_to_ahb.scala 203:117] - node _T_152 = and(_T_149, _T_151) @[axi4_to_ahb.scala 203:97] - node _T_153 = bits(_T_152, 0, 0) @[axi4_to_ahb.scala 203:138] - node _T_154 = mux(_T_153, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 203:67] - node _T_155 = mux(_T_148, UInt<3>("h07"), _T_154) @[axi4_to_ahb.scala 203:26] - buf_nxtstate <= _T_155 @[axi4_to_ahb.scala 203:20] - node _T_156 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 204:37] - buf_state_en <= _T_156 @[axi4_to_ahb.scala 204:20] - buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 205:22] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 206:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 207:23] - node _T_157 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 208:41] - node _T_158 = and(buf_state_en, _T_157) @[axi4_to_ahb.scala 208:39] - slave_valid_pre <= _T_158 @[axi4_to_ahb.scala 208:23] - node _T_159 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 209:34] - node _T_160 = and(buf_state_en, _T_159) @[axi4_to_ahb.scala 209:32] - cmd_done <= _T_160 @[axi4_to_ahb.scala 209:16] - node _T_161 = and(master_ready, master_valid) @[axi4_to_ahb.scala 210:33] - node _T_162 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 210:64] - node _T_163 = and(_T_161, _T_162) @[axi4_to_ahb.scala 210:48] - node _T_164 = and(_T_163, buf_state_en) @[axi4_to_ahb.scala 210:79] - bypass_en <= _T_164 @[axi4_to_ahb.scala 210:17] - node _T_165 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 211:47] - node _T_166 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 211:62] - node _T_167 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 211:78] - node _T_168 = mux(_T_165, _T_166, _T_167) @[axi4_to_ahb.scala 211:30] - buf_cmd_byte_ptr <= _T_168 @[axi4_to_ahb.scala 211:24] - node _T_169 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 212:63] - node _T_170 = and(_T_169, buf_state_en) @[axi4_to_ahb.scala 212:78] - node _T_171 = eq(_T_170, UInt<1>("h00")) @[axi4_to_ahb.scala 212:47] + node _T_137 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 194:39] + node _T_138 = and(ahb_hready_q, _T_137) @[axi4_to_ahb.scala 194:37] + node _T_139 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 194:82] + node _T_140 = eq(_T_139, UInt<1>("h01")) @[axi4_to_ahb.scala 194:89] + node _T_141 = and(master_valid, _T_140) @[axi4_to_ahb.scala 194:70] + node _T_142 = not(_T_141) @[axi4_to_ahb.scala 194:55] + node _T_143 = and(_T_138, _T_142) @[axi4_to_ahb.scala 194:53] + master_ready <= _T_143 @[axi4_to_ahb.scala 194:20] + node _T_144 = and(master_valid, master_ready) @[axi4_to_ahb.scala 195:34] + node _T_145 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 195:62] + node _T_146 = eq(_T_145, UInt<1>("h00")) @[axi4_to_ahb.scala 195:69] + node _T_147 = and(_T_144, _T_146) @[axi4_to_ahb.scala 195:49] + buf_wr_en <= _T_147 @[axi4_to_ahb.scala 195:17] + node _T_148 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 196:45] + node _T_149 = and(master_valid, master_ready) @[axi4_to_ahb.scala 196:82] + node _T_150 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 196:110] + node _T_151 = eq(_T_150, UInt<1>("h00")) @[axi4_to_ahb.scala 196:117] + node _T_152 = and(_T_149, _T_151) @[axi4_to_ahb.scala 196:97] + node _T_153 = bits(_T_152, 0, 0) @[axi4_to_ahb.scala 196:138] + node _T_154 = mux(_T_153, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 196:67] + node _T_155 = mux(_T_148, UInt<3>("h07"), _T_154) @[axi4_to_ahb.scala 196:26] + buf_nxtstate <= _T_155 @[axi4_to_ahb.scala 196:20] + node _T_156 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 197:37] + buf_state_en <= _T_156 @[axi4_to_ahb.scala 197:20] + buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 198:22] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 199:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 200:23] + node _T_157 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 201:41] + node _T_158 = and(buf_state_en, _T_157) @[axi4_to_ahb.scala 201:39] + slave_valid_pre <= _T_158 @[axi4_to_ahb.scala 201:23] + node _T_159 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 202:34] + node _T_160 = and(buf_state_en, _T_159) @[axi4_to_ahb.scala 202:32] + cmd_done <= _T_160 @[axi4_to_ahb.scala 202:16] + node _T_161 = and(master_ready, master_valid) @[axi4_to_ahb.scala 203:33] + node _T_162 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 203:64] + node _T_163 = and(_T_161, _T_162) @[axi4_to_ahb.scala 203:48] + node _T_164 = and(_T_163, buf_state_en) @[axi4_to_ahb.scala 203:79] + bypass_en <= _T_164 @[axi4_to_ahb.scala 203:17] + node _T_165 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 204:47] + node _T_166 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 204:62] + node _T_167 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 204:78] + node _T_168 = mux(_T_165, _T_166, _T_167) @[axi4_to_ahb.scala 204:30] + buf_cmd_byte_ptr <= _T_168 @[axi4_to_ahb.scala 204:24] + node _T_169 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 205:63] + node _T_170 = and(_T_169, buf_state_en) @[axi4_to_ahb.scala 205:78] + node _T_171 = eq(_T_170, UInt<1>("h00")) @[axi4_to_ahb.scala 205:47] node _T_172 = bits(_T_171, 0, 0) @[Bitwise.scala 72:15] node _T_173 = mux(_T_172, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_174 = and(UInt<2>("h02"), _T_173) @[axi4_to_ahb.scala 212:36] - io.ahb.out.htrans <= _T_174 @[axi4_to_ahb.scala 212:25] - slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 213:20] + node _T_174 = and(UInt<2>("h02"), _T_173) @[axi4_to_ahb.scala 205:36] + io.ahb.out.htrans <= _T_174 @[axi4_to_ahb.scala 205:25] + slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 206:20] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_175 = eq(UInt<3>("h07"), buf_state) @[Conditional.scala 37:30] when _T_175 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 217:20] - node _T_176 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 218:51] - node _T_177 = neq(_T_176, UInt<1>("h00")) @[axi4_to_ahb.scala 218:58] - node _T_178 = and(ahb_hready_q, _T_177) @[axi4_to_ahb.scala 218:36] - node _T_179 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 218:72] - node _T_180 = and(_T_178, _T_179) @[axi4_to_ahb.scala 218:70] - buf_state_en <= _T_180 @[axi4_to_ahb.scala 218:20] - slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 219:23] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 220:20] - node _T_181 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 221:35] - buf_cmd_byte_ptr <= _T_181 @[axi4_to_ahb.scala 221:24] - node _T_182 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 222:51] + buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 210:20] + node _T_176 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 211:51] + node _T_177 = neq(_T_176, UInt<1>("h00")) @[axi4_to_ahb.scala 211:58] + node _T_178 = and(ahb_hready_q, _T_177) @[axi4_to_ahb.scala 211:36] + node _T_179 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 211:72] + node _T_180 = and(_T_178, _T_179) @[axi4_to_ahb.scala 211:70] + buf_state_en <= _T_180 @[axi4_to_ahb.scala 211:20] + slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 212:23] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 213:20] + node _T_181 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 214:35] + buf_cmd_byte_ptr <= _T_181 @[axi4_to_ahb.scala 214:24] + node _T_182 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 215:51] node _T_183 = bits(_T_182, 0, 0) @[Bitwise.scala 72:15] node _T_184 = mux(_T_183, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_185 = and(UInt<2>("h02"), _T_184) @[axi4_to_ahb.scala 222:41] - io.ahb.out.htrans <= _T_185 @[axi4_to_ahb.scala 222:25] + node _T_185 = and(UInt<2>("h02"), _T_184) @[axi4_to_ahb.scala 215:41] + io.ahb.out.htrans <= _T_185 @[axi4_to_ahb.scala 215:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_186 = eq(UInt<3>("h03"), buf_state) @[Conditional.scala 37:30] when _T_186 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 226:20] - node _T_187 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 227:37] - buf_state_en <= _T_187 @[axi4_to_ahb.scala 227:20] - buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 228:22] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 229:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 230:23] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 231:20] + buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 219:20] + node _T_187 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 220:37] + buf_state_en <= _T_187 @[axi4_to_ahb.scala 220:20] + buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 221:22] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 222:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 223:23] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 224:20] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_188 = eq(UInt<3>("h02"), buf_state) @[Conditional.scala 37:30] when _T_188 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 235:20] - node _T_189 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 236:33] - node _T_190 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 236:63] - node _T_191 = neq(_T_190, UInt<1>("h00")) @[axi4_to_ahb.scala 236:70] - node _T_192 = and(_T_189, _T_191) @[axi4_to_ahb.scala 236:48] - trxn_done <= _T_192 @[axi4_to_ahb.scala 236:17] - buf_state_en <= trxn_done @[axi4_to_ahb.scala 237:20] - buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 238:27] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 239:20] - node _T_193 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 240:47] - node _T_194 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 240:85] - node _T_195 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 240:103] - node _T_196 = add(_T_194, UInt<1>("h01")) @[axi4_to_ahb.scala 142:52] - node _T_197 = tail(_T_196, 1) @[axi4_to_ahb.scala 142:52] - node _T_198 = mux(UInt<1>("h01"), _T_197, _T_194) @[axi4_to_ahb.scala 142:24] - node _T_199 = bits(_T_195, 0, 0) @[axi4_to_ahb.scala 143:44] - node _T_200 = geq(UInt<1>("h00"), _T_198) @[axi4_to_ahb.scala 143:62] - node _T_201 = and(_T_199, _T_200) @[axi4_to_ahb.scala 143:48] - node _T_202 = bits(_T_195, 1, 1) @[axi4_to_ahb.scala 143:44] - node _T_203 = geq(UInt<1>("h01"), _T_198) @[axi4_to_ahb.scala 143:62] - node _T_204 = and(_T_202, _T_203) @[axi4_to_ahb.scala 143:48] - node _T_205 = bits(_T_195, 2, 2) @[axi4_to_ahb.scala 143:44] - node _T_206 = geq(UInt<2>("h02"), _T_198) @[axi4_to_ahb.scala 143:62] - node _T_207 = and(_T_205, _T_206) @[axi4_to_ahb.scala 143:48] - node _T_208 = bits(_T_195, 3, 3) @[axi4_to_ahb.scala 143:44] - node _T_209 = geq(UInt<2>("h03"), _T_198) @[axi4_to_ahb.scala 143:62] - node _T_210 = and(_T_208, _T_209) @[axi4_to_ahb.scala 143:48] - node _T_211 = bits(_T_195, 4, 4) @[axi4_to_ahb.scala 143:44] - node _T_212 = geq(UInt<3>("h04"), _T_198) @[axi4_to_ahb.scala 143:62] - node _T_213 = and(_T_211, _T_212) @[axi4_to_ahb.scala 143:48] - node _T_214 = bits(_T_195, 5, 5) @[axi4_to_ahb.scala 143:44] - node _T_215 = geq(UInt<3>("h05"), _T_198) @[axi4_to_ahb.scala 143:62] - node _T_216 = and(_T_214, _T_215) @[axi4_to_ahb.scala 143:48] - node _T_217 = bits(_T_195, 6, 6) @[axi4_to_ahb.scala 143:44] - node _T_218 = geq(UInt<3>("h06"), _T_198) @[axi4_to_ahb.scala 143:62] - node _T_219 = and(_T_217, _T_218) @[axi4_to_ahb.scala 143:48] - node _T_220 = bits(_T_195, 7, 7) @[axi4_to_ahb.scala 143:44] - node _T_221 = geq(UInt<3>("h07"), _T_198) @[axi4_to_ahb.scala 143:62] - node _T_222 = and(_T_220, _T_221) @[axi4_to_ahb.scala 143:48] + buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 228:20] + node _T_189 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 229:33] + node _T_190 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 229:63] + node _T_191 = neq(_T_190, UInt<1>("h00")) @[axi4_to_ahb.scala 229:70] + node _T_192 = and(_T_189, _T_191) @[axi4_to_ahb.scala 229:48] + trxn_done <= _T_192 @[axi4_to_ahb.scala 229:17] + buf_state_en <= trxn_done @[axi4_to_ahb.scala 230:20] + buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 231:27] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 232:20] + node _T_193 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 233:47] + node _T_194 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 233:85] + node _T_195 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 233:103] + node _T_196 = add(_T_194, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] + node _T_197 = tail(_T_196, 1) @[axi4_to_ahb.scala 135:52] + node _T_198 = mux(UInt<1>("h01"), _T_197, _T_194) @[axi4_to_ahb.scala 135:24] + node _T_199 = bits(_T_195, 0, 0) @[axi4_to_ahb.scala 136:44] + node _T_200 = geq(UInt<1>("h00"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_201 = and(_T_199, _T_200) @[axi4_to_ahb.scala 136:48] + node _T_202 = bits(_T_195, 1, 1) @[axi4_to_ahb.scala 136:44] + node _T_203 = geq(UInt<1>("h01"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_204 = and(_T_202, _T_203) @[axi4_to_ahb.scala 136:48] + node _T_205 = bits(_T_195, 2, 2) @[axi4_to_ahb.scala 136:44] + node _T_206 = geq(UInt<2>("h02"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_207 = and(_T_205, _T_206) @[axi4_to_ahb.scala 136:48] + node _T_208 = bits(_T_195, 3, 3) @[axi4_to_ahb.scala 136:44] + node _T_209 = geq(UInt<2>("h03"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_210 = and(_T_208, _T_209) @[axi4_to_ahb.scala 136:48] + node _T_211 = bits(_T_195, 4, 4) @[axi4_to_ahb.scala 136:44] + node _T_212 = geq(UInt<3>("h04"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_213 = and(_T_211, _T_212) @[axi4_to_ahb.scala 136:48] + node _T_214 = bits(_T_195, 5, 5) @[axi4_to_ahb.scala 136:44] + node _T_215 = geq(UInt<3>("h05"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_216 = and(_T_214, _T_215) @[axi4_to_ahb.scala 136:48] + node _T_217 = bits(_T_195, 6, 6) @[axi4_to_ahb.scala 136:44] + node _T_218 = geq(UInt<3>("h06"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_219 = and(_T_217, _T_218) @[axi4_to_ahb.scala 136:48] + node _T_220 = bits(_T_195, 7, 7) @[axi4_to_ahb.scala 136:44] + node _T_221 = geq(UInt<3>("h07"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_222 = and(_T_220, _T_221) @[axi4_to_ahb.scala 136:48] node _T_223 = mux(_T_222, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_224 = mux(_T_219, UInt<3>("h06"), _T_223) @[Mux.scala 98:16] node _T_225 = mux(_T_216, UInt<3>("h05"), _T_224) @[Mux.scala 98:16] @@ -111195,39 +111185,39 @@ circuit quasar_wrapper : node _T_228 = mux(_T_207, UInt<2>("h02"), _T_227) @[Mux.scala 98:16] node _T_229 = mux(_T_204, UInt<1>("h01"), _T_228) @[Mux.scala 98:16] node _T_230 = mux(_T_201, UInt<1>("h00"), _T_229) @[Mux.scala 98:16] - node _T_231 = mux(_T_193, _T_230, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 240:30] - buf_cmd_byte_ptr <= _T_231 @[axi4_to_ahb.scala 240:24] - node _T_232 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 241:65] - node _T_233 = or(buf_aligned, _T_232) @[axi4_to_ahb.scala 241:44] - node _T_234 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 241:127] - node _T_235 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 241:145] - node _T_236 = add(_T_234, UInt<1>("h01")) @[axi4_to_ahb.scala 142:52] - node _T_237 = tail(_T_236, 1) @[axi4_to_ahb.scala 142:52] - node _T_238 = mux(UInt<1>("h01"), _T_237, _T_234) @[axi4_to_ahb.scala 142:24] - node _T_239 = bits(_T_235, 0, 0) @[axi4_to_ahb.scala 143:44] - node _T_240 = geq(UInt<1>("h00"), _T_238) @[axi4_to_ahb.scala 143:62] - node _T_241 = and(_T_239, _T_240) @[axi4_to_ahb.scala 143:48] - node _T_242 = bits(_T_235, 1, 1) @[axi4_to_ahb.scala 143:44] - node _T_243 = geq(UInt<1>("h01"), _T_238) @[axi4_to_ahb.scala 143:62] - node _T_244 = and(_T_242, _T_243) @[axi4_to_ahb.scala 143:48] - node _T_245 = bits(_T_235, 2, 2) @[axi4_to_ahb.scala 143:44] - node _T_246 = geq(UInt<2>("h02"), _T_238) @[axi4_to_ahb.scala 143:62] - node _T_247 = and(_T_245, _T_246) @[axi4_to_ahb.scala 143:48] - node _T_248 = bits(_T_235, 3, 3) @[axi4_to_ahb.scala 143:44] - node _T_249 = geq(UInt<2>("h03"), _T_238) @[axi4_to_ahb.scala 143:62] - node _T_250 = and(_T_248, _T_249) @[axi4_to_ahb.scala 143:48] - node _T_251 = bits(_T_235, 4, 4) @[axi4_to_ahb.scala 143:44] - node _T_252 = geq(UInt<3>("h04"), _T_238) @[axi4_to_ahb.scala 143:62] - node _T_253 = and(_T_251, _T_252) @[axi4_to_ahb.scala 143:48] - node _T_254 = bits(_T_235, 5, 5) @[axi4_to_ahb.scala 143:44] - node _T_255 = geq(UInt<3>("h05"), _T_238) @[axi4_to_ahb.scala 143:62] - node _T_256 = and(_T_254, _T_255) @[axi4_to_ahb.scala 143:48] - node _T_257 = bits(_T_235, 6, 6) @[axi4_to_ahb.scala 143:44] - node _T_258 = geq(UInt<3>("h06"), _T_238) @[axi4_to_ahb.scala 143:62] - node _T_259 = and(_T_257, _T_258) @[axi4_to_ahb.scala 143:48] - node _T_260 = bits(_T_235, 7, 7) @[axi4_to_ahb.scala 143:44] - node _T_261 = geq(UInt<3>("h07"), _T_238) @[axi4_to_ahb.scala 143:62] - node _T_262 = and(_T_260, _T_261) @[axi4_to_ahb.scala 143:48] + node _T_231 = mux(_T_193, _T_230, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 233:30] + buf_cmd_byte_ptr <= _T_231 @[axi4_to_ahb.scala 233:24] + node _T_232 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 234:65] + node _T_233 = or(buf_aligned, _T_232) @[axi4_to_ahb.scala 234:44] + node _T_234 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 234:127] + node _T_235 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 234:145] + node _T_236 = add(_T_234, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] + node _T_237 = tail(_T_236, 1) @[axi4_to_ahb.scala 135:52] + node _T_238 = mux(UInt<1>("h01"), _T_237, _T_234) @[axi4_to_ahb.scala 135:24] + node _T_239 = bits(_T_235, 0, 0) @[axi4_to_ahb.scala 136:44] + node _T_240 = geq(UInt<1>("h00"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_241 = and(_T_239, _T_240) @[axi4_to_ahb.scala 136:48] + node _T_242 = bits(_T_235, 1, 1) @[axi4_to_ahb.scala 136:44] + node _T_243 = geq(UInt<1>("h01"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_244 = and(_T_242, _T_243) @[axi4_to_ahb.scala 136:48] + node _T_245 = bits(_T_235, 2, 2) @[axi4_to_ahb.scala 136:44] + node _T_246 = geq(UInt<2>("h02"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_247 = and(_T_245, _T_246) @[axi4_to_ahb.scala 136:48] + node _T_248 = bits(_T_235, 3, 3) @[axi4_to_ahb.scala 136:44] + node _T_249 = geq(UInt<2>("h03"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_250 = and(_T_248, _T_249) @[axi4_to_ahb.scala 136:48] + node _T_251 = bits(_T_235, 4, 4) @[axi4_to_ahb.scala 136:44] + node _T_252 = geq(UInt<3>("h04"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_253 = and(_T_251, _T_252) @[axi4_to_ahb.scala 136:48] + node _T_254 = bits(_T_235, 5, 5) @[axi4_to_ahb.scala 136:44] + node _T_255 = geq(UInt<3>("h05"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_256 = and(_T_254, _T_255) @[axi4_to_ahb.scala 136:48] + node _T_257 = bits(_T_235, 6, 6) @[axi4_to_ahb.scala 136:44] + node _T_258 = geq(UInt<3>("h06"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_259 = and(_T_257, _T_258) @[axi4_to_ahb.scala 136:48] + node _T_260 = bits(_T_235, 7, 7) @[axi4_to_ahb.scala 136:44] + node _T_261 = geq(UInt<3>("h07"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_262 = and(_T_260, _T_261) @[axi4_to_ahb.scala 136:48] node _T_263 = mux(_T_262, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_264 = mux(_T_259, UInt<3>("h06"), _T_263) @[Mux.scala 98:16] node _T_265 = mux(_T_256, UInt<3>("h05"), _T_264) @[Mux.scala 98:16] @@ -111236,83 +111226,83 @@ circuit quasar_wrapper : node _T_268 = mux(_T_247, UInt<2>("h02"), _T_267) @[Mux.scala 98:16] node _T_269 = mux(_T_244, UInt<1>("h01"), _T_268) @[Mux.scala 98:16] node _T_270 = mux(_T_241, UInt<1>("h00"), _T_269) @[Mux.scala 98:16] - node _T_271 = dshr(buf_byteen, _T_270) @[axi4_to_ahb.scala 241:92] - node _T_272 = bits(_T_271, 0, 0) @[axi4_to_ahb.scala 241:92] - node _T_273 = eq(_T_272, UInt<1>("h00")) @[axi4_to_ahb.scala 241:163] - node _T_274 = or(_T_233, _T_273) @[axi4_to_ahb.scala 241:79] - node _T_275 = and(trxn_done, _T_274) @[axi4_to_ahb.scala 241:29] - cmd_done <= _T_275 @[axi4_to_ahb.scala 241:16] - node _T_276 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 242:47] - node _T_277 = eq(_T_276, UInt<1>("h00")) @[axi4_to_ahb.scala 242:36] + node _T_271 = dshr(buf_byteen, _T_270) @[axi4_to_ahb.scala 234:92] + node _T_272 = bits(_T_271, 0, 0) @[axi4_to_ahb.scala 234:92] + node _T_273 = eq(_T_272, UInt<1>("h00")) @[axi4_to_ahb.scala 234:163] + node _T_274 = or(_T_233, _T_273) @[axi4_to_ahb.scala 234:79] + node _T_275 = and(trxn_done, _T_274) @[axi4_to_ahb.scala 234:29] + cmd_done <= _T_275 @[axi4_to_ahb.scala 234:16] + node _T_276 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 235:47] + node _T_277 = eq(_T_276, UInt<1>("h00")) @[axi4_to_ahb.scala 235:36] node _T_278 = bits(_T_277, 0, 0) @[Bitwise.scala 72:15] node _T_279 = mux(_T_278, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_280 = and(_T_279, UInt<2>("h02")) @[axi4_to_ahb.scala 242:61] - io.ahb.out.htrans <= _T_280 @[axi4_to_ahb.scala 242:25] + node _T_280 = and(_T_279, UInt<2>("h02")) @[axi4_to_ahb.scala 235:61] + io.ahb.out.htrans <= _T_280 @[axi4_to_ahb.scala 235:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_281 = eq(UInt<3>("h04"), buf_state) @[Conditional.scala 37:30] when _T_281 : @[Conditional.scala 39:67] - node _T_282 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 246:34] - node _T_283 = or(_T_282, ahb_hresp_q) @[axi4_to_ahb.scala 246:50] - buf_state_en <= _T_283 @[axi4_to_ahb.scala 246:20] - node _T_284 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 247:38] - node _T_285 = and(buf_state_en, _T_284) @[axi4_to_ahb.scala 247:36] - node _T_286 = and(_T_285, slave_ready) @[axi4_to_ahb.scala 247:51] - master_ready <= _T_286 @[axi4_to_ahb.scala 247:20] - node _T_287 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 248:42] - node _T_288 = or(ahb_hresp_q, _T_287) @[axi4_to_ahb.scala 248:40] - node _T_289 = and(master_valid, master_valid) @[axi4_to_ahb.scala 248:80] - node _T_290 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 248:111] - node _T_291 = eq(_T_290, UInt<1>("h01")) @[axi4_to_ahb.scala 248:117] - node _T_292 = bits(_T_291, 0, 0) @[axi4_to_ahb.scala 248:132] - node _T_293 = mux(_T_292, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 248:99] - node _T_294 = mux(_T_289, _T_293, UInt<3>("h00")) @[axi4_to_ahb.scala 248:65] - node _T_295 = mux(_T_288, UInt<3>("h05"), _T_294) @[axi4_to_ahb.scala 248:26] - buf_nxtstate <= _T_295 @[axi4_to_ahb.scala 248:20] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 249:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 250:23] - node _T_296 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 251:33] - node _T_297 = eq(_T_296, UInt<1>("h01")) @[axi4_to_ahb.scala 251:39] - buf_write_in <= _T_297 @[axi4_to_ahb.scala 251:20] - node _T_298 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 252:50] - node _T_299 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 252:78] - node _T_300 = or(_T_298, _T_299) @[axi4_to_ahb.scala 252:62] - node _T_301 = and(buf_state_en, _T_300) @[axi4_to_ahb.scala 252:33] - buf_wr_en <= _T_301 @[axi4_to_ahb.scala 252:17] - buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 253:22] - node _T_302 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 254:65] - node _T_303 = neq(_T_302, UInt<1>("h00")) @[axi4_to_ahb.scala 254:71] - node _T_304 = and(ahb_hready_q, _T_303) @[axi4_to_ahb.scala 254:50] - node _T_305 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 255:29] - node _T_306 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 255:85] - node _T_307 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 255:101] - node _T_308 = add(_T_306, UInt<1>("h01")) @[axi4_to_ahb.scala 142:52] - node _T_309 = tail(_T_308, 1) @[axi4_to_ahb.scala 142:52] - node _T_310 = mux(UInt<1>("h01"), _T_309, _T_306) @[axi4_to_ahb.scala 142:24] - node _T_311 = bits(_T_307, 0, 0) @[axi4_to_ahb.scala 143:44] - node _T_312 = geq(UInt<1>("h00"), _T_310) @[axi4_to_ahb.scala 143:62] - node _T_313 = and(_T_311, _T_312) @[axi4_to_ahb.scala 143:48] - node _T_314 = bits(_T_307, 1, 1) @[axi4_to_ahb.scala 143:44] - node _T_315 = geq(UInt<1>("h01"), _T_310) @[axi4_to_ahb.scala 143:62] - node _T_316 = and(_T_314, _T_315) @[axi4_to_ahb.scala 143:48] - node _T_317 = bits(_T_307, 2, 2) @[axi4_to_ahb.scala 143:44] - node _T_318 = geq(UInt<2>("h02"), _T_310) @[axi4_to_ahb.scala 143:62] - node _T_319 = and(_T_317, _T_318) @[axi4_to_ahb.scala 143:48] - node _T_320 = bits(_T_307, 3, 3) @[axi4_to_ahb.scala 143:44] - node _T_321 = geq(UInt<2>("h03"), _T_310) @[axi4_to_ahb.scala 143:62] - node _T_322 = and(_T_320, _T_321) @[axi4_to_ahb.scala 143:48] - node _T_323 = bits(_T_307, 4, 4) @[axi4_to_ahb.scala 143:44] - node _T_324 = geq(UInt<3>("h04"), _T_310) @[axi4_to_ahb.scala 143:62] - node _T_325 = and(_T_323, _T_324) @[axi4_to_ahb.scala 143:48] - node _T_326 = bits(_T_307, 5, 5) @[axi4_to_ahb.scala 143:44] - node _T_327 = geq(UInt<3>("h05"), _T_310) @[axi4_to_ahb.scala 143:62] - node _T_328 = and(_T_326, _T_327) @[axi4_to_ahb.scala 143:48] - node _T_329 = bits(_T_307, 6, 6) @[axi4_to_ahb.scala 143:44] - node _T_330 = geq(UInt<3>("h06"), _T_310) @[axi4_to_ahb.scala 143:62] - node _T_331 = and(_T_329, _T_330) @[axi4_to_ahb.scala 143:48] - node _T_332 = bits(_T_307, 7, 7) @[axi4_to_ahb.scala 143:44] - node _T_333 = geq(UInt<3>("h07"), _T_310) @[axi4_to_ahb.scala 143:62] - node _T_334 = and(_T_332, _T_333) @[axi4_to_ahb.scala 143:48] + node _T_282 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 239:34] + node _T_283 = or(_T_282, ahb_hresp_q) @[axi4_to_ahb.scala 239:50] + buf_state_en <= _T_283 @[axi4_to_ahb.scala 239:20] + node _T_284 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 240:38] + node _T_285 = and(buf_state_en, _T_284) @[axi4_to_ahb.scala 240:36] + node _T_286 = and(_T_285, slave_ready) @[axi4_to_ahb.scala 240:51] + master_ready <= _T_286 @[axi4_to_ahb.scala 240:20] + node _T_287 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 241:42] + node _T_288 = or(ahb_hresp_q, _T_287) @[axi4_to_ahb.scala 241:40] + node _T_289 = and(master_valid, master_valid) @[axi4_to_ahb.scala 241:80] + node _T_290 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 241:111] + node _T_291 = eq(_T_290, UInt<1>("h01")) @[axi4_to_ahb.scala 241:117] + node _T_292 = bits(_T_291, 0, 0) @[axi4_to_ahb.scala 241:132] + node _T_293 = mux(_T_292, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 241:99] + node _T_294 = mux(_T_289, _T_293, UInt<3>("h00")) @[axi4_to_ahb.scala 241:65] + node _T_295 = mux(_T_288, UInt<3>("h05"), _T_294) @[axi4_to_ahb.scala 241:26] + buf_nxtstate <= _T_295 @[axi4_to_ahb.scala 241:20] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 242:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 243:23] + node _T_296 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 244:33] + node _T_297 = eq(_T_296, UInt<1>("h01")) @[axi4_to_ahb.scala 244:39] + buf_write_in <= _T_297 @[axi4_to_ahb.scala 244:20] + node _T_298 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 245:50] + node _T_299 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 245:78] + node _T_300 = or(_T_298, _T_299) @[axi4_to_ahb.scala 245:62] + node _T_301 = and(buf_state_en, _T_300) @[axi4_to_ahb.scala 245:33] + buf_wr_en <= _T_301 @[axi4_to_ahb.scala 245:17] + buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 246:22] + node _T_302 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 247:65] + node _T_303 = neq(_T_302, UInt<1>("h00")) @[axi4_to_ahb.scala 247:71] + node _T_304 = and(ahb_hready_q, _T_303) @[axi4_to_ahb.scala 247:50] + node _T_305 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 248:29] + node _T_306 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 248:85] + node _T_307 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 248:101] + node _T_308 = add(_T_306, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] + node _T_309 = tail(_T_308, 1) @[axi4_to_ahb.scala 135:52] + node _T_310 = mux(UInt<1>("h01"), _T_309, _T_306) @[axi4_to_ahb.scala 135:24] + node _T_311 = bits(_T_307, 0, 0) @[axi4_to_ahb.scala 136:44] + node _T_312 = geq(UInt<1>("h00"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_313 = and(_T_311, _T_312) @[axi4_to_ahb.scala 136:48] + node _T_314 = bits(_T_307, 1, 1) @[axi4_to_ahb.scala 136:44] + node _T_315 = geq(UInt<1>("h01"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_316 = and(_T_314, _T_315) @[axi4_to_ahb.scala 136:48] + node _T_317 = bits(_T_307, 2, 2) @[axi4_to_ahb.scala 136:44] + node _T_318 = geq(UInt<2>("h02"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_319 = and(_T_317, _T_318) @[axi4_to_ahb.scala 136:48] + node _T_320 = bits(_T_307, 3, 3) @[axi4_to_ahb.scala 136:44] + node _T_321 = geq(UInt<2>("h03"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_322 = and(_T_320, _T_321) @[axi4_to_ahb.scala 136:48] + node _T_323 = bits(_T_307, 4, 4) @[axi4_to_ahb.scala 136:44] + node _T_324 = geq(UInt<3>("h04"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_325 = and(_T_323, _T_324) @[axi4_to_ahb.scala 136:48] + node _T_326 = bits(_T_307, 5, 5) @[axi4_to_ahb.scala 136:44] + node _T_327 = geq(UInt<3>("h05"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_328 = and(_T_326, _T_327) @[axi4_to_ahb.scala 136:48] + node _T_329 = bits(_T_307, 6, 6) @[axi4_to_ahb.scala 136:44] + node _T_330 = geq(UInt<3>("h06"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_331 = and(_T_329, _T_330) @[axi4_to_ahb.scala 136:48] + node _T_332 = bits(_T_307, 7, 7) @[axi4_to_ahb.scala 136:44] + node _T_333 = geq(UInt<3>("h07"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_334 = and(_T_332, _T_333) @[axi4_to_ahb.scala 136:48] node _T_335 = mux(_T_334, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_336 = mux(_T_331, UInt<3>("h06"), _T_335) @[Mux.scala 98:16] node _T_337 = mux(_T_328, UInt<3>("h05"), _T_336) @[Mux.scala 98:16] @@ -111321,62 +111311,62 @@ circuit quasar_wrapper : node _T_340 = mux(_T_319, UInt<2>("h02"), _T_339) @[Mux.scala 98:16] node _T_341 = mux(_T_316, UInt<1>("h01"), _T_340) @[Mux.scala 98:16] node _T_342 = mux(_T_313, UInt<1>("h00"), _T_341) @[Mux.scala 98:16] - node _T_343 = dshr(buf_byteen, _T_342) @[axi4_to_ahb.scala 255:51] - node _T_344 = bits(_T_343, 0, 0) @[axi4_to_ahb.scala 255:51] - node _T_345 = eq(_T_344, UInt<1>("h00")) @[axi4_to_ahb.scala 255:116] - node _T_346 = or(_T_305, _T_345) @[axi4_to_ahb.scala 255:38] - node _T_347 = and(_T_304, _T_346) @[axi4_to_ahb.scala 254:80] - node _T_348 = or(ahb_hresp_q, _T_347) @[axi4_to_ahb.scala 254:34] - cmd_done <= _T_348 @[axi4_to_ahb.scala 254:16] - node _T_349 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 256:33] - node _T_350 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 256:64] - node _T_351 = and(_T_349, _T_350) @[axi4_to_ahb.scala 256:48] - bypass_en <= _T_351 @[axi4_to_ahb.scala 256:17] - node _T_352 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 257:48] - node _T_353 = eq(_T_352, UInt<1>("h00")) @[axi4_to_ahb.scala 257:37] - node _T_354 = or(_T_353, bypass_en) @[axi4_to_ahb.scala 257:61] + node _T_343 = dshr(buf_byteen, _T_342) @[axi4_to_ahb.scala 248:51] + node _T_344 = bits(_T_343, 0, 0) @[axi4_to_ahb.scala 248:51] + node _T_345 = eq(_T_344, UInt<1>("h00")) @[axi4_to_ahb.scala 248:116] + node _T_346 = or(_T_305, _T_345) @[axi4_to_ahb.scala 248:38] + node _T_347 = and(_T_304, _T_346) @[axi4_to_ahb.scala 247:80] + node _T_348 = or(ahb_hresp_q, _T_347) @[axi4_to_ahb.scala 247:34] + cmd_done <= _T_348 @[axi4_to_ahb.scala 247:16] + node _T_349 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 249:33] + node _T_350 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 249:64] + node _T_351 = and(_T_349, _T_350) @[axi4_to_ahb.scala 249:48] + bypass_en <= _T_351 @[axi4_to_ahb.scala 249:17] + node _T_352 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 250:48] + node _T_353 = eq(_T_352, UInt<1>("h00")) @[axi4_to_ahb.scala 250:37] + node _T_354 = or(_T_353, bypass_en) @[axi4_to_ahb.scala 250:61] node _T_355 = bits(_T_354, 0, 0) @[Bitwise.scala 72:15] node _T_356 = mux(_T_355, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_357 = and(_T_356, UInt<2>("h02")) @[axi4_to_ahb.scala 257:75] - io.ahb.out.htrans <= _T_357 @[axi4_to_ahb.scala 257:25] - node _T_358 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 258:55] - node _T_359 = and(buf_state_en, _T_358) @[axi4_to_ahb.scala 258:39] - slave_valid_pre <= _T_359 @[axi4_to_ahb.scala 258:23] - node _T_360 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 259:33] - node _T_361 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 259:63] - node _T_362 = neq(_T_361, UInt<1>("h00")) @[axi4_to_ahb.scala 259:69] - node _T_363 = and(_T_360, _T_362) @[axi4_to_ahb.scala 259:48] - trxn_done <= _T_363 @[axi4_to_ahb.scala 259:17] - node _T_364 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 260:40] - buf_cmd_byte_ptr_en <= _T_364 @[axi4_to_ahb.scala 260:27] - node _T_365 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 261:79] - node _T_366 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 142:52] - node _T_367 = tail(_T_366, 1) @[axi4_to_ahb.scala 142:52] - node _T_368 = mux(UInt<1>("h00"), _T_367, UInt<3>("h00")) @[axi4_to_ahb.scala 142:24] - node _T_369 = bits(_T_365, 0, 0) @[axi4_to_ahb.scala 143:44] - node _T_370 = geq(UInt<1>("h00"), _T_368) @[axi4_to_ahb.scala 143:62] - node _T_371 = and(_T_369, _T_370) @[axi4_to_ahb.scala 143:48] - node _T_372 = bits(_T_365, 1, 1) @[axi4_to_ahb.scala 143:44] - node _T_373 = geq(UInt<1>("h01"), _T_368) @[axi4_to_ahb.scala 143:62] - node _T_374 = and(_T_372, _T_373) @[axi4_to_ahb.scala 143:48] - node _T_375 = bits(_T_365, 2, 2) @[axi4_to_ahb.scala 143:44] - node _T_376 = geq(UInt<2>("h02"), _T_368) @[axi4_to_ahb.scala 143:62] - node _T_377 = and(_T_375, _T_376) @[axi4_to_ahb.scala 143:48] - node _T_378 = bits(_T_365, 3, 3) @[axi4_to_ahb.scala 143:44] - node _T_379 = geq(UInt<2>("h03"), _T_368) @[axi4_to_ahb.scala 143:62] - node _T_380 = and(_T_378, _T_379) @[axi4_to_ahb.scala 143:48] - node _T_381 = bits(_T_365, 4, 4) @[axi4_to_ahb.scala 143:44] - node _T_382 = geq(UInt<3>("h04"), _T_368) @[axi4_to_ahb.scala 143:62] - node _T_383 = and(_T_381, _T_382) @[axi4_to_ahb.scala 143:48] - node _T_384 = bits(_T_365, 5, 5) @[axi4_to_ahb.scala 143:44] - node _T_385 = geq(UInt<3>("h05"), _T_368) @[axi4_to_ahb.scala 143:62] - node _T_386 = and(_T_384, _T_385) @[axi4_to_ahb.scala 143:48] - node _T_387 = bits(_T_365, 6, 6) @[axi4_to_ahb.scala 143:44] - node _T_388 = geq(UInt<3>("h06"), _T_368) @[axi4_to_ahb.scala 143:62] - node _T_389 = and(_T_387, _T_388) @[axi4_to_ahb.scala 143:48] - node _T_390 = bits(_T_365, 7, 7) @[axi4_to_ahb.scala 143:44] - node _T_391 = geq(UInt<3>("h07"), _T_368) @[axi4_to_ahb.scala 143:62] - node _T_392 = and(_T_390, _T_391) @[axi4_to_ahb.scala 143:48] + node _T_357 = and(_T_356, UInt<2>("h02")) @[axi4_to_ahb.scala 250:75] + io.ahb.out.htrans <= _T_357 @[axi4_to_ahb.scala 250:25] + node _T_358 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 251:55] + node _T_359 = and(buf_state_en, _T_358) @[axi4_to_ahb.scala 251:39] + slave_valid_pre <= _T_359 @[axi4_to_ahb.scala 251:23] + node _T_360 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 252:33] + node _T_361 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 252:63] + node _T_362 = neq(_T_361, UInt<1>("h00")) @[axi4_to_ahb.scala 252:69] + node _T_363 = and(_T_360, _T_362) @[axi4_to_ahb.scala 252:48] + trxn_done <= _T_363 @[axi4_to_ahb.scala 252:17] + node _T_364 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 253:40] + buf_cmd_byte_ptr_en <= _T_364 @[axi4_to_ahb.scala 253:27] + node _T_365 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 254:79] + node _T_366 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] + node _T_367 = tail(_T_366, 1) @[axi4_to_ahb.scala 135:52] + node _T_368 = mux(UInt<1>("h00"), _T_367, UInt<3>("h00")) @[axi4_to_ahb.scala 135:24] + node _T_369 = bits(_T_365, 0, 0) @[axi4_to_ahb.scala 136:44] + node _T_370 = geq(UInt<1>("h00"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_371 = and(_T_369, _T_370) @[axi4_to_ahb.scala 136:48] + node _T_372 = bits(_T_365, 1, 1) @[axi4_to_ahb.scala 136:44] + node _T_373 = geq(UInt<1>("h01"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_374 = and(_T_372, _T_373) @[axi4_to_ahb.scala 136:48] + node _T_375 = bits(_T_365, 2, 2) @[axi4_to_ahb.scala 136:44] + node _T_376 = geq(UInt<2>("h02"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_377 = and(_T_375, _T_376) @[axi4_to_ahb.scala 136:48] + node _T_378 = bits(_T_365, 3, 3) @[axi4_to_ahb.scala 136:44] + node _T_379 = geq(UInt<2>("h03"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_380 = and(_T_378, _T_379) @[axi4_to_ahb.scala 136:48] + node _T_381 = bits(_T_365, 4, 4) @[axi4_to_ahb.scala 136:44] + node _T_382 = geq(UInt<3>("h04"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_383 = and(_T_381, _T_382) @[axi4_to_ahb.scala 136:48] + node _T_384 = bits(_T_365, 5, 5) @[axi4_to_ahb.scala 136:44] + node _T_385 = geq(UInt<3>("h05"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_386 = and(_T_384, _T_385) @[axi4_to_ahb.scala 136:48] + node _T_387 = bits(_T_365, 6, 6) @[axi4_to_ahb.scala 136:44] + node _T_388 = geq(UInt<3>("h06"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_389 = and(_T_387, _T_388) @[axi4_to_ahb.scala 136:48] + node _T_390 = bits(_T_365, 7, 7) @[axi4_to_ahb.scala 136:44] + node _T_391 = geq(UInt<3>("h07"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_392 = and(_T_390, _T_391) @[axi4_to_ahb.scala 136:48] node _T_393 = mux(_T_392, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_394 = mux(_T_389, UInt<3>("h06"), _T_393) @[Mux.scala 98:16] node _T_395 = mux(_T_386, UInt<3>("h05"), _T_394) @[Mux.scala 98:16] @@ -111385,35 +111375,35 @@ circuit quasar_wrapper : node _T_398 = mux(_T_377, UInt<2>("h02"), _T_397) @[Mux.scala 98:16] node _T_399 = mux(_T_374, UInt<1>("h01"), _T_398) @[Mux.scala 98:16] node _T_400 = mux(_T_371, UInt<1>("h00"), _T_399) @[Mux.scala 98:16] - node _T_401 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 261:141] - node _T_402 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 261:157] - node _T_403 = add(_T_401, UInt<1>("h01")) @[axi4_to_ahb.scala 142:52] - node _T_404 = tail(_T_403, 1) @[axi4_to_ahb.scala 142:52] - node _T_405 = mux(UInt<1>("h01"), _T_404, _T_401) @[axi4_to_ahb.scala 142:24] - node _T_406 = bits(_T_402, 0, 0) @[axi4_to_ahb.scala 143:44] - node _T_407 = geq(UInt<1>("h00"), _T_405) @[axi4_to_ahb.scala 143:62] - node _T_408 = and(_T_406, _T_407) @[axi4_to_ahb.scala 143:48] - node _T_409 = bits(_T_402, 1, 1) @[axi4_to_ahb.scala 143:44] - node _T_410 = geq(UInt<1>("h01"), _T_405) @[axi4_to_ahb.scala 143:62] - node _T_411 = and(_T_409, _T_410) @[axi4_to_ahb.scala 143:48] - node _T_412 = bits(_T_402, 2, 2) @[axi4_to_ahb.scala 143:44] - node _T_413 = geq(UInt<2>("h02"), _T_405) @[axi4_to_ahb.scala 143:62] - node _T_414 = and(_T_412, _T_413) @[axi4_to_ahb.scala 143:48] - node _T_415 = bits(_T_402, 3, 3) @[axi4_to_ahb.scala 143:44] - node _T_416 = geq(UInt<2>("h03"), _T_405) @[axi4_to_ahb.scala 143:62] - node _T_417 = and(_T_415, _T_416) @[axi4_to_ahb.scala 143:48] - node _T_418 = bits(_T_402, 4, 4) @[axi4_to_ahb.scala 143:44] - node _T_419 = geq(UInt<3>("h04"), _T_405) @[axi4_to_ahb.scala 143:62] - node _T_420 = and(_T_418, _T_419) @[axi4_to_ahb.scala 143:48] - node _T_421 = bits(_T_402, 5, 5) @[axi4_to_ahb.scala 143:44] - node _T_422 = geq(UInt<3>("h05"), _T_405) @[axi4_to_ahb.scala 143:62] - node _T_423 = and(_T_421, _T_422) @[axi4_to_ahb.scala 143:48] - node _T_424 = bits(_T_402, 6, 6) @[axi4_to_ahb.scala 143:44] - node _T_425 = geq(UInt<3>("h06"), _T_405) @[axi4_to_ahb.scala 143:62] - node _T_426 = and(_T_424, _T_425) @[axi4_to_ahb.scala 143:48] - node _T_427 = bits(_T_402, 7, 7) @[axi4_to_ahb.scala 143:44] - node _T_428 = geq(UInt<3>("h07"), _T_405) @[axi4_to_ahb.scala 143:62] - node _T_429 = and(_T_427, _T_428) @[axi4_to_ahb.scala 143:48] + node _T_401 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 254:141] + node _T_402 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 254:157] + node _T_403 = add(_T_401, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] + node _T_404 = tail(_T_403, 1) @[axi4_to_ahb.scala 135:52] + node _T_405 = mux(UInt<1>("h01"), _T_404, _T_401) @[axi4_to_ahb.scala 135:24] + node _T_406 = bits(_T_402, 0, 0) @[axi4_to_ahb.scala 136:44] + node _T_407 = geq(UInt<1>("h00"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_408 = and(_T_406, _T_407) @[axi4_to_ahb.scala 136:48] + node _T_409 = bits(_T_402, 1, 1) @[axi4_to_ahb.scala 136:44] + node _T_410 = geq(UInt<1>("h01"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_411 = and(_T_409, _T_410) @[axi4_to_ahb.scala 136:48] + node _T_412 = bits(_T_402, 2, 2) @[axi4_to_ahb.scala 136:44] + node _T_413 = geq(UInt<2>("h02"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_414 = and(_T_412, _T_413) @[axi4_to_ahb.scala 136:48] + node _T_415 = bits(_T_402, 3, 3) @[axi4_to_ahb.scala 136:44] + node _T_416 = geq(UInt<2>("h03"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_417 = and(_T_415, _T_416) @[axi4_to_ahb.scala 136:48] + node _T_418 = bits(_T_402, 4, 4) @[axi4_to_ahb.scala 136:44] + node _T_419 = geq(UInt<3>("h04"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_420 = and(_T_418, _T_419) @[axi4_to_ahb.scala 136:48] + node _T_421 = bits(_T_402, 5, 5) @[axi4_to_ahb.scala 136:44] + node _T_422 = geq(UInt<3>("h05"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_423 = and(_T_421, _T_422) @[axi4_to_ahb.scala 136:48] + node _T_424 = bits(_T_402, 6, 6) @[axi4_to_ahb.scala 136:44] + node _T_425 = geq(UInt<3>("h06"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_426 = and(_T_424, _T_425) @[axi4_to_ahb.scala 136:48] + node _T_427 = bits(_T_402, 7, 7) @[axi4_to_ahb.scala 136:44] + node _T_428 = geq(UInt<3>("h07"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_429 = and(_T_427, _T_428) @[axi4_to_ahb.scala 136:48] node _T_430 = mux(_T_429, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_431 = mux(_T_426, UInt<3>("h06"), _T_430) @[Mux.scala 98:16] node _T_432 = mux(_T_423, UInt<3>("h05"), _T_431) @[Mux.scala 98:16] @@ -111422,268 +111412,268 @@ circuit quasar_wrapper : node _T_435 = mux(_T_414, UInt<2>("h02"), _T_434) @[Mux.scala 98:16] node _T_436 = mux(_T_411, UInt<1>("h01"), _T_435) @[Mux.scala 98:16] node _T_437 = mux(_T_408, UInt<1>("h00"), _T_436) @[Mux.scala 98:16] - node _T_438 = mux(trxn_done, _T_437, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 261:97] - node _T_439 = mux(bypass_en, _T_400, _T_438) @[axi4_to_ahb.scala 261:30] - buf_cmd_byte_ptr <= _T_439 @[axi4_to_ahb.scala 261:24] + node _T_438 = mux(trxn_done, _T_437, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 254:97] + node _T_439 = mux(bypass_en, _T_400, _T_438) @[axi4_to_ahb.scala 254:30] + buf_cmd_byte_ptr <= _T_439 @[axi4_to_ahb.scala 254:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_440 = eq(UInt<3>("h05"), buf_state) @[Conditional.scala 37:30] when _T_440 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 264:20] - buf_state_en <= slave_ready @[axi4_to_ahb.scala 265:20] - slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 266:23] - slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 267:23] + buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 257:20] + buf_state_en <= slave_ready @[axi4_to_ahb.scala 258:20] + slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 259:23] + slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 260:23] skip @[Conditional.scala 39:67] - cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 271:16] - node _T_441 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 272:33] - node _T_442 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 272:73] - node _T_443 = eq(_T_442, UInt<1>("h01")) @[axi4_to_ahb.scala 272:80] - node _T_444 = and(buf_aligned_in, _T_443) @[axi4_to_ahb.scala 272:60] - node _T_445 = bits(_T_444, 0, 0) @[axi4_to_ahb.scala 272:100] - node _T_446 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:132] - node _T_447 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 134:50] - node _T_448 = eq(_T_447, UInt<8>("h0ff")) @[axi4_to_ahb.scala 134:57] - node _T_449 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 134:81] - node _T_450 = eq(_T_449, UInt<8>("h0f")) @[axi4_to_ahb.scala 134:88] - node _T_451 = or(_T_448, _T_450) @[axi4_to_ahb.scala 134:70] - node _T_452 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 134:117] - node _T_453 = eq(_T_452, UInt<8>("h03")) @[axi4_to_ahb.scala 134:124] - node _T_454 = or(_T_451, _T_453) @[axi4_to_ahb.scala 134:106] + cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 264:16] + node _T_441 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 265:33] + node _T_442 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 265:73] + node _T_443 = eq(_T_442, UInt<1>("h01")) @[axi4_to_ahb.scala 265:80] + node _T_444 = and(buf_aligned_in, _T_443) @[axi4_to_ahb.scala 265:60] + node _T_445 = bits(_T_444, 0, 0) @[axi4_to_ahb.scala 265:100] + node _T_446 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 265:132] + node _T_447 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:50] + node _T_448 = eq(_T_447, UInt<8>("h0ff")) @[axi4_to_ahb.scala 127:57] + node _T_449 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:81] + node _T_450 = eq(_T_449, UInt<8>("h0f")) @[axi4_to_ahb.scala 127:88] + node _T_451 = or(_T_448, _T_450) @[axi4_to_ahb.scala 127:70] + node _T_452 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:117] + node _T_453 = eq(_T_452, UInt<8>("h03")) @[axi4_to_ahb.scala 127:124] + node _T_454 = or(_T_451, _T_453) @[axi4_to_ahb.scala 127:106] node _T_455 = bits(_T_454, 0, 0) @[Bitwise.scala 72:15] node _T_456 = mux(_T_455, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_457 = and(UInt<3>("h00"), _T_456) @[axi4_to_ahb.scala 134:29] - node _T_458 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 135:35] - node _T_459 = eq(_T_458, UInt<8>("h0c")) @[axi4_to_ahb.scala 135:42] + node _T_457 = and(UInt<3>("h00"), _T_456) @[axi4_to_ahb.scala 127:29] + node _T_458 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 128:35] + node _T_459 = eq(_T_458, UInt<8>("h0c")) @[axi4_to_ahb.scala 128:42] node _T_460 = bits(_T_459, 0, 0) @[Bitwise.scala 72:15] node _T_461 = mux(_T_460, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_462 = and(UInt<2>("h02"), _T_461) @[axi4_to_ahb.scala 135:15] - node _T_463 = or(_T_457, _T_462) @[axi4_to_ahb.scala 134:146] - node _T_464 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 136:36] - node _T_465 = eq(_T_464, UInt<8>("h0f0")) @[axi4_to_ahb.scala 136:43] - node _T_466 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 136:67] - node _T_467 = eq(_T_466, UInt<8>("h03")) @[axi4_to_ahb.scala 136:74] - node _T_468 = or(_T_465, _T_467) @[axi4_to_ahb.scala 136:56] + node _T_462 = and(UInt<2>("h02"), _T_461) @[axi4_to_ahb.scala 128:15] + node _T_463 = or(_T_457, _T_462) @[axi4_to_ahb.scala 127:146] + node _T_464 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 129:36] + node _T_465 = eq(_T_464, UInt<8>("h0f0")) @[axi4_to_ahb.scala 129:43] + node _T_466 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 129:67] + node _T_467 = eq(_T_466, UInt<8>("h03")) @[axi4_to_ahb.scala 129:74] + node _T_468 = or(_T_465, _T_467) @[axi4_to_ahb.scala 129:56] node _T_469 = bits(_T_468, 0, 0) @[Bitwise.scala 72:15] node _T_470 = mux(_T_469, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_471 = and(UInt<3>("h04"), _T_470) @[axi4_to_ahb.scala 136:15] - node _T_472 = or(_T_463, _T_471) @[axi4_to_ahb.scala 135:63] - node _T_473 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 137:35] - node _T_474 = eq(_T_473, UInt<8>("h0c0")) @[axi4_to_ahb.scala 137:42] + node _T_471 = and(UInt<3>("h04"), _T_470) @[axi4_to_ahb.scala 129:15] + node _T_472 = or(_T_463, _T_471) @[axi4_to_ahb.scala 128:63] + node _T_473 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 130:35] + node _T_474 = eq(_T_473, UInt<8>("h0c0")) @[axi4_to_ahb.scala 130:42] node _T_475 = bits(_T_474, 0, 0) @[Bitwise.scala 72:15] node _T_476 = mux(_T_475, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_477 = and(UInt<3>("h06"), _T_476) @[axi4_to_ahb.scala 137:15] - node _T_478 = or(_T_472, _T_477) @[axi4_to_ahb.scala 136:96] - node _T_479 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 138:33] - node _T_480 = eq(_T_479, UInt<8>("h0c0")) @[axi4_to_ahb.scala 138:40] + node _T_477 = and(UInt<3>("h06"), _T_476) @[axi4_to_ahb.scala 130:15] + node _T_478 = or(_T_472, _T_477) @[axi4_to_ahb.scala 129:96] + node _T_479 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 131:33] + node _T_480 = eq(_T_479, UInt<8>("h0c0")) @[axi4_to_ahb.scala 131:40] node _T_481 = bits(_T_480, 0, 0) @[Bitwise.scala 72:15] node _T_482 = mux(_T_481, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_483 = and(UInt<3>("h06"), _T_482) @[axi4_to_ahb.scala 138:13] - node _T_484 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 272:152] - node _T_485 = mux(_T_445, _T_478, _T_484) @[axi4_to_ahb.scala 272:43] + node _T_483 = and(UInt<3>("h06"), _T_482) @[axi4_to_ahb.scala 131:13] + node _T_484 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 265:152] + node _T_485 = mux(_T_445, _T_478, _T_484) @[axi4_to_ahb.scala 265:43] node _T_486 = cat(_T_441, _T_485) @[Cat.scala 29:58] - buf_addr_in <= _T_486 @[axi4_to_ahb.scala 272:15] - node _T_487 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 273:27] - buf_tag_in <= _T_487 @[axi4_to_ahb.scala 273:14] - node _T_488 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 274:32] - buf_byteen_in <= _T_488 @[axi4_to_ahb.scala 274:17] - node _T_489 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 275:33] - node _T_490 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 275:59] - node _T_491 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 275:80] - node _T_492 = mux(_T_489, _T_490, _T_491) @[axi4_to_ahb.scala 275:21] - buf_data_in <= _T_492 @[axi4_to_ahb.scala 275:15] - node _T_493 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 276:52] - node _T_494 = eq(_T_493, UInt<2>("h03")) @[axi4_to_ahb.scala 276:58] - node _T_495 = and(buf_aligned_in, _T_494) @[axi4_to_ahb.scala 276:38] - node _T_496 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 276:84] - node _T_497 = eq(_T_496, UInt<1>("h01")) @[axi4_to_ahb.scala 276:91] - node _T_498 = and(_T_495, _T_497) @[axi4_to_ahb.scala 276:71] - node _T_499 = bits(_T_498, 0, 0) @[axi4_to_ahb.scala 276:111] - node _T_500 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 276:142] - node _T_501 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 128:42] - node _T_502 = eq(_T_501, UInt<8>("h0ff")) @[axi4_to_ahb.scala 128:49] + buf_addr_in <= _T_486 @[axi4_to_ahb.scala 265:15] + node _T_487 = bits(master_tag, 2, 0) @[axi4_to_ahb.scala 266:27] + buf_tag_in <= _T_487 @[axi4_to_ahb.scala 266:14] + node _T_488 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 267:32] + buf_byteen_in <= _T_488 @[axi4_to_ahb.scala 267:17] + node _T_489 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 268:33] + node _T_490 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 268:59] + node _T_491 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 268:80] + node _T_492 = mux(_T_489, _T_490, _T_491) @[axi4_to_ahb.scala 268:21] + buf_data_in <= _T_492 @[axi4_to_ahb.scala 268:15] + node _T_493 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 269:52] + node _T_494 = eq(_T_493, UInt<2>("h03")) @[axi4_to_ahb.scala 269:58] + node _T_495 = and(buf_aligned_in, _T_494) @[axi4_to_ahb.scala 269:38] + node _T_496 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 269:84] + node _T_497 = eq(_T_496, UInt<1>("h01")) @[axi4_to_ahb.scala 269:91] + node _T_498 = and(_T_495, _T_497) @[axi4_to_ahb.scala 269:71] + node _T_499 = bits(_T_498, 0, 0) @[axi4_to_ahb.scala 269:111] + node _T_500 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 269:142] + node _T_501 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 121:42] + node _T_502 = eq(_T_501, UInt<8>("h0ff")) @[axi4_to_ahb.scala 121:49] node _T_503 = bits(_T_502, 0, 0) @[Bitwise.scala 72:15] node _T_504 = mux(_T_503, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_505 = and(UInt<2>("h03"), _T_504) @[axi4_to_ahb.scala 128:25] - node _T_506 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 129:35] - node _T_507 = eq(_T_506, UInt<8>("h0f0")) @[axi4_to_ahb.scala 129:42] - node _T_508 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 129:64] - node _T_509 = eq(_T_508, UInt<8>("h0f")) @[axi4_to_ahb.scala 129:71] - node _T_510 = or(_T_507, _T_509) @[axi4_to_ahb.scala 129:55] + node _T_505 = and(UInt<2>("h03"), _T_504) @[axi4_to_ahb.scala 121:25] + node _T_506 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 122:35] + node _T_507 = eq(_T_506, UInt<8>("h0f0")) @[axi4_to_ahb.scala 122:42] + node _T_508 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 122:64] + node _T_509 = eq(_T_508, UInt<8>("h0f")) @[axi4_to_ahb.scala 122:71] + node _T_510 = or(_T_507, _T_509) @[axi4_to_ahb.scala 122:55] node _T_511 = bits(_T_510, 0, 0) @[Bitwise.scala 72:15] node _T_512 = mux(_T_511, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_513 = and(UInt<2>("h02"), _T_512) @[axi4_to_ahb.scala 129:16] - node _T_514 = or(_T_505, _T_513) @[axi4_to_ahb.scala 128:64] - node _T_515 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 130:40] - node _T_516 = eq(_T_515, UInt<8>("h0c0")) @[axi4_to_ahb.scala 130:47] - node _T_517 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 130:69] - node _T_518 = eq(_T_517, UInt<6>("h030")) @[axi4_to_ahb.scala 130:76] - node _T_519 = or(_T_516, _T_518) @[axi4_to_ahb.scala 130:60] - node _T_520 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 130:98] - node _T_521 = eq(_T_520, UInt<8>("h0c")) @[axi4_to_ahb.scala 130:105] - node _T_522 = or(_T_519, _T_521) @[axi4_to_ahb.scala 130:89] - node _T_523 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 130:132] - node _T_524 = eq(_T_523, UInt<8>("h03")) @[axi4_to_ahb.scala 130:139] - node _T_525 = or(_T_522, _T_524) @[axi4_to_ahb.scala 130:123] + node _T_513 = and(UInt<2>("h02"), _T_512) @[axi4_to_ahb.scala 122:16] + node _T_514 = or(_T_505, _T_513) @[axi4_to_ahb.scala 121:64] + node _T_515 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:40] + node _T_516 = eq(_T_515, UInt<8>("h0c0")) @[axi4_to_ahb.scala 123:47] + node _T_517 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:69] + node _T_518 = eq(_T_517, UInt<6>("h030")) @[axi4_to_ahb.scala 123:76] + node _T_519 = or(_T_516, _T_518) @[axi4_to_ahb.scala 123:60] + node _T_520 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:98] + node _T_521 = eq(_T_520, UInt<8>("h0c")) @[axi4_to_ahb.scala 123:105] + node _T_522 = or(_T_519, _T_521) @[axi4_to_ahb.scala 123:89] + node _T_523 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:132] + node _T_524 = eq(_T_523, UInt<8>("h03")) @[axi4_to_ahb.scala 123:139] + node _T_525 = or(_T_522, _T_524) @[axi4_to_ahb.scala 123:123] node _T_526 = bits(_T_525, 0, 0) @[Bitwise.scala 72:15] node _T_527 = mux(_T_526, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_528 = and(UInt<2>("h01"), _T_527) @[axi4_to_ahb.scala 130:21] - node _T_529 = or(_T_514, _T_528) @[axi4_to_ahb.scala 129:93] - node _T_530 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 276:161] - node _T_531 = mux(_T_499, _T_529, _T_530) @[axi4_to_ahb.scala 276:21] - buf_size_in <= _T_531 @[axi4_to_ahb.scala 276:15] - node _T_532 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 277:32] - node _T_533 = eq(_T_532, UInt<1>("h00")) @[axi4_to_ahb.scala 277:39] - node _T_534 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 278:17] - node _T_535 = eq(_T_534, UInt<1>("h00")) @[axi4_to_ahb.scala 278:24] - node _T_536 = or(_T_533, _T_535) @[axi4_to_ahb.scala 277:48] - node _T_537 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 278:47] - node _T_538 = eq(_T_537, UInt<2>("h01")) @[axi4_to_ahb.scala 278:54] - node _T_539 = or(_T_536, _T_538) @[axi4_to_ahb.scala 278:33] - node _T_540 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 278:86] - node _T_541 = eq(_T_540, UInt<2>("h02")) @[axi4_to_ahb.scala 278:93] - node _T_542 = or(_T_539, _T_541) @[axi4_to_ahb.scala 278:72] - node _T_543 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 279:18] - node _T_544 = eq(_T_543, UInt<2>("h03")) @[axi4_to_ahb.scala 279:25] - node _T_545 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 279:55] - node _T_546 = eq(_T_545, UInt<2>("h03")) @[axi4_to_ahb.scala 279:62] - node _T_547 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 279:90] - node _T_548 = eq(_T_547, UInt<4>("h0c")) @[axi4_to_ahb.scala 279:97] - node _T_549 = or(_T_546, _T_548) @[axi4_to_ahb.scala 279:74] - node _T_550 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 279:125] - node _T_551 = eq(_T_550, UInt<6>("h030")) @[axi4_to_ahb.scala 279:132] - node _T_552 = or(_T_549, _T_551) @[axi4_to_ahb.scala 279:109] - node _T_553 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 279:161] - node _T_554 = eq(_T_553, UInt<8>("h0c0")) @[axi4_to_ahb.scala 279:168] - node _T_555 = or(_T_552, _T_554) @[axi4_to_ahb.scala 279:145] - node _T_556 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 280:21] - node _T_557 = eq(_T_556, UInt<4>("h0f")) @[axi4_to_ahb.scala 280:28] - node _T_558 = or(_T_555, _T_557) @[axi4_to_ahb.scala 279:181] - node _T_559 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 280:56] - node _T_560 = eq(_T_559, UInt<8>("h0f0")) @[axi4_to_ahb.scala 280:63] - node _T_561 = or(_T_558, _T_560) @[axi4_to_ahb.scala 280:40] - node _T_562 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 280:92] - node _T_563 = eq(_T_562, UInt<8>("h0ff")) @[axi4_to_ahb.scala 280:99] - node _T_564 = or(_T_561, _T_563) @[axi4_to_ahb.scala 280:76] - node _T_565 = and(_T_544, _T_564) @[axi4_to_ahb.scala 279:38] - node _T_566 = or(_T_542, _T_565) @[axi4_to_ahb.scala 278:106] - buf_aligned_in <= _T_566 @[axi4_to_ahb.scala 277:18] - node _T_567 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 282:43] - node _T_568 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 282:62] - node _T_569 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 282:87] + node _T_528 = and(UInt<2>("h01"), _T_527) @[axi4_to_ahb.scala 123:21] + node _T_529 = or(_T_514, _T_528) @[axi4_to_ahb.scala 122:93] + node _T_530 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 269:161] + node _T_531 = mux(_T_499, _T_529, _T_530) @[axi4_to_ahb.scala 269:21] + buf_size_in <= _T_531 @[axi4_to_ahb.scala 269:15] + node _T_532 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 270:32] + node _T_533 = eq(_T_532, UInt<1>("h00")) @[axi4_to_ahb.scala 270:39] + node _T_534 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 271:17] + node _T_535 = eq(_T_534, UInt<1>("h00")) @[axi4_to_ahb.scala 271:24] + node _T_536 = or(_T_533, _T_535) @[axi4_to_ahb.scala 270:48] + node _T_537 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 271:47] + node _T_538 = eq(_T_537, UInt<2>("h01")) @[axi4_to_ahb.scala 271:54] + node _T_539 = or(_T_536, _T_538) @[axi4_to_ahb.scala 271:33] + node _T_540 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 271:86] + node _T_541 = eq(_T_540, UInt<2>("h02")) @[axi4_to_ahb.scala 271:93] + node _T_542 = or(_T_539, _T_541) @[axi4_to_ahb.scala 271:72] + node _T_543 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 272:18] + node _T_544 = eq(_T_543, UInt<2>("h03")) @[axi4_to_ahb.scala 272:25] + node _T_545 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:55] + node _T_546 = eq(_T_545, UInt<2>("h03")) @[axi4_to_ahb.scala 272:62] + node _T_547 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:90] + node _T_548 = eq(_T_547, UInt<4>("h0c")) @[axi4_to_ahb.scala 272:97] + node _T_549 = or(_T_546, _T_548) @[axi4_to_ahb.scala 272:74] + node _T_550 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:125] + node _T_551 = eq(_T_550, UInt<6>("h030")) @[axi4_to_ahb.scala 272:132] + node _T_552 = or(_T_549, _T_551) @[axi4_to_ahb.scala 272:109] + node _T_553 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:161] + node _T_554 = eq(_T_553, UInt<8>("h0c0")) @[axi4_to_ahb.scala 272:168] + node _T_555 = or(_T_552, _T_554) @[axi4_to_ahb.scala 272:145] + node _T_556 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 273:21] + node _T_557 = eq(_T_556, UInt<4>("h0f")) @[axi4_to_ahb.scala 273:28] + node _T_558 = or(_T_555, _T_557) @[axi4_to_ahb.scala 272:181] + node _T_559 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 273:56] + node _T_560 = eq(_T_559, UInt<8>("h0f0")) @[axi4_to_ahb.scala 273:63] + node _T_561 = or(_T_558, _T_560) @[axi4_to_ahb.scala 273:40] + node _T_562 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 273:92] + node _T_563 = eq(_T_562, UInt<8>("h0ff")) @[axi4_to_ahb.scala 273:99] + node _T_564 = or(_T_561, _T_563) @[axi4_to_ahb.scala 273:76] + node _T_565 = and(_T_544, _T_564) @[axi4_to_ahb.scala 272:38] + node _T_566 = or(_T_542, _T_565) @[axi4_to_ahb.scala 271:106] + buf_aligned_in <= _T_566 @[axi4_to_ahb.scala 270:18] + node _T_567 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 275:43] + node _T_568 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 275:62] + node _T_569 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 275:87] node _T_570 = cat(_T_568, _T_569) @[Cat.scala 29:58] - node _T_571 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 282:108] - node _T_572 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 282:133] + node _T_571 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 275:108] + node _T_572 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 275:133] node _T_573 = cat(_T_571, _T_572) @[Cat.scala 29:58] - node _T_574 = mux(_T_567, _T_570, _T_573) @[axi4_to_ahb.scala 282:26] - io.ahb.out.haddr <= _T_574 @[axi4_to_ahb.scala 282:20] - node _T_575 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 283:43] + node _T_574 = mux(_T_567, _T_570, _T_573) @[axi4_to_ahb.scala 275:26] + io.ahb.out.haddr <= _T_574 @[axi4_to_ahb.scala 275:20] + node _T_575 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 276:43] node _T_576 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15] node _T_577 = mux(_T_576, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_578 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 283:94] - node _T_579 = and(_T_577, _T_578) @[axi4_to_ahb.scala 283:81] + node _T_578 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 276:94] + node _T_579 = and(_T_577, _T_578) @[axi4_to_ahb.scala 276:81] node _T_580 = cat(UInt<1>("h00"), _T_579) @[Cat.scala 29:58] node _T_581 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15] node _T_582 = mux(_T_581, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_583 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 283:148] - node _T_584 = and(_T_582, _T_583) @[axi4_to_ahb.scala 283:138] + node _T_583 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 276:148] + node _T_584 = and(_T_582, _T_583) @[axi4_to_ahb.scala 276:138] node _T_585 = cat(UInt<1>("h00"), _T_584) @[Cat.scala 29:58] - node _T_586 = mux(_T_575, _T_580, _T_585) @[axi4_to_ahb.scala 283:26] - io.ahb.out.hsize <= _T_586 @[axi4_to_ahb.scala 283:20] - io.ahb.out.hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 285:21] - io.ahb.out.hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 286:24] - node _T_587 = bits(io.axi.ar.bits.prot, 2, 2) @[axi4_to_ahb.scala 287:57] - node _T_588 = eq(_T_587, UInt<1>("h00")) @[axi4_to_ahb.scala 287:37] + node _T_586 = mux(_T_575, _T_580, _T_585) @[axi4_to_ahb.scala 276:26] + io.ahb.out.hsize <= _T_586 @[axi4_to_ahb.scala 276:20] + io.ahb.out.hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 278:21] + io.ahb.out.hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 279:24] + node _T_587 = bits(io.axi.ar.bits.prot, 2, 2) @[axi4_to_ahb.scala 280:57] + node _T_588 = eq(_T_587, UInt<1>("h00")) @[axi4_to_ahb.scala 280:37] node _T_589 = cat(UInt<1>("h01"), _T_588) @[Cat.scala 29:58] - io.ahb.out.hprot <= _T_589 @[axi4_to_ahb.scala 287:20] - node _T_590 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 288:44] - node _T_591 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 288:59] - node _T_592 = eq(_T_591, UInt<1>("h01")) @[axi4_to_ahb.scala 288:66] - node _T_593 = mux(_T_590, _T_592, buf_write) @[axi4_to_ahb.scala 288:27] - io.ahb.out.hwrite <= _T_593 @[axi4_to_ahb.scala 288:21] - node _T_594 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 289:32] - io.ahb.out.hwdata <= _T_594 @[axi4_to_ahb.scala 289:21] - slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 291:15] - node _T_595 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 292:43] - node _T_596 = mux(_T_595, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 292:23] + io.ahb.out.hprot <= _T_589 @[axi4_to_ahb.scala 280:20] + node _T_590 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 281:44] + node _T_591 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 281:59] + node _T_592 = eq(_T_591, UInt<1>("h01")) @[axi4_to_ahb.scala 281:66] + node _T_593 = mux(_T_590, _T_592, buf_write) @[axi4_to_ahb.scala 281:27] + io.ahb.out.hwrite <= _T_593 @[axi4_to_ahb.scala 281:21] + node _T_594 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 282:32] + io.ahb.out.hwdata <= _T_594 @[axi4_to_ahb.scala 282:21] + slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 284:15] + node _T_595 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 285:43] + node _T_596 = mux(_T_595, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 285:23] node _T_597 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15] node _T_598 = mux(_T_597, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_599 = and(_T_598, UInt<2>("h02")) @[axi4_to_ahb.scala 292:88] + node _T_599 = and(_T_598, UInt<2>("h02")) @[axi4_to_ahb.scala 285:88] node _T_600 = cat(_T_596, _T_599) @[Cat.scala 29:58] - slave_opc <= _T_600 @[axi4_to_ahb.scala 292:13] - node _T_601 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 293:41] - node _T_602 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 293:66] + slave_opc <= _T_600 @[axi4_to_ahb.scala 285:13] + node _T_601 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 286:41] + node _T_602 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 286:66] node _T_603 = cat(_T_602, _T_602) @[Cat.scala 29:58] - node _T_604 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 293:91] - node _T_605 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 293:110] - node _T_606 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 293:131] - node _T_607 = mux(_T_604, _T_605, _T_606) @[axi4_to_ahb.scala 293:79] - node _T_608 = mux(_T_601, _T_603, _T_607) @[axi4_to_ahb.scala 293:21] - slave_rdata <= _T_608 @[axi4_to_ahb.scala 293:15] - node _T_609 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 294:26] - slave_tag <= _T_609 @[axi4_to_ahb.scala 294:13] - node _T_610 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 296:37] - node _T_611 = neq(_T_610, UInt<1>("h00")) @[axi4_to_ahb.scala 296:44] - node _T_612 = and(_T_611, io.ahb.in.hready) @[axi4_to_ahb.scala 296:56] - node _T_613 = and(_T_612, io.ahb.out.hwrite) @[axi4_to_ahb.scala 296:75] - last_addr_en <= _T_613 @[axi4_to_ahb.scala 296:16] - node _T_614 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 298:31] - node _T_615 = and(_T_614, master_ready) @[axi4_to_ahb.scala 298:49] - wrbuf_en <= _T_615 @[axi4_to_ahb.scala 298:12] - node _T_616 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 299:35] - node _T_617 = and(_T_616, master_ready) @[axi4_to_ahb.scala 299:52] - wrbuf_data_en <= _T_617 @[axi4_to_ahb.scala 299:17] - node _T_618 = and(master_valid, master_ready) @[axi4_to_ahb.scala 300:34] - node _T_619 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 300:62] - node _T_620 = eq(_T_619, UInt<1>("h01")) @[axi4_to_ahb.scala 300:69] - node _T_621 = and(_T_618, _T_620) @[axi4_to_ahb.scala 300:49] - wrbuf_cmd_sent <= _T_621 @[axi4_to_ahb.scala 300:18] - node _T_622 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 301:33] - node _T_623 = and(wrbuf_cmd_sent, _T_622) @[axi4_to_ahb.scala 301:31] - wrbuf_rst <= _T_623 @[axi4_to_ahb.scala 301:13] - node _T_624 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 303:36] - node _T_625 = and(wrbuf_vld, _T_624) @[axi4_to_ahb.scala 303:34] - node _T_626 = eq(_T_625, UInt<1>("h00")) @[axi4_to_ahb.scala 303:22] - node _T_627 = and(_T_626, master_ready) @[axi4_to_ahb.scala 303:53] - io.axi.aw.ready <= _T_627 @[axi4_to_ahb.scala 303:19] - node _T_628 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 304:40] - node _T_629 = and(wrbuf_data_vld, _T_628) @[axi4_to_ahb.scala 304:38] - node _T_630 = eq(_T_629, UInt<1>("h00")) @[axi4_to_ahb.scala 304:21] - node _T_631 = and(_T_630, master_ready) @[axi4_to_ahb.scala 304:57] - io.axi.w.ready <= _T_631 @[axi4_to_ahb.scala 304:18] - node _T_632 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 305:34] - node _T_633 = eq(_T_632, UInt<1>("h00")) @[axi4_to_ahb.scala 305:22] - node _T_634 = and(_T_633, master_ready) @[axi4_to_ahb.scala 305:52] - io.axi.ar.ready <= _T_634 @[axi4_to_ahb.scala 305:19] - io.axi.r.bits.last <= UInt<1>("h01") @[axi4_to_ahb.scala 306:22] - node _T_635 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 308:71] - node _T_636 = mux(_T_635, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 308:55] - node _T_637 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 308:91] - node _T_638 = and(_T_636, _T_637) @[axi4_to_ahb.scala 308:89] - reg _T_639 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 308:51] - _T_639 <= _T_638 @[axi4_to_ahb.scala 308:51] - wrbuf_vld <= _T_639 @[axi4_to_ahb.scala 308:21] - node _T_640 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 309:76] - node _T_641 = mux(_T_640, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 309:55] - node _T_642 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 309:102] - node _T_643 = and(_T_641, _T_642) @[axi4_to_ahb.scala 309:100] - reg _T_644 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 309:51] - _T_644 <= _T_643 @[axi4_to_ahb.scala 309:51] - wrbuf_data_vld <= _T_644 @[axi4_to_ahb.scala 309:21] - node _T_645 = bits(io.axi.aw.bits.id, 0, 0) @[axi4_to_ahb.scala 310:71] - node _T_646 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 310:105] + node _T_604 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 286:91] + node _T_605 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 286:110] + node _T_606 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 286:131] + node _T_607 = mux(_T_604, _T_605, _T_606) @[axi4_to_ahb.scala 286:79] + node _T_608 = mux(_T_601, _T_603, _T_607) @[axi4_to_ahb.scala 286:21] + slave_rdata <= _T_608 @[axi4_to_ahb.scala 286:15] + node _T_609 = bits(slvbuf_tag, 2, 0) @[axi4_to_ahb.scala 287:26] + slave_tag <= _T_609 @[axi4_to_ahb.scala 287:13] + node _T_610 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 289:37] + node _T_611 = neq(_T_610, UInt<1>("h00")) @[axi4_to_ahb.scala 289:44] + node _T_612 = and(_T_611, io.ahb.in.hready) @[axi4_to_ahb.scala 289:56] + node _T_613 = and(_T_612, io.ahb.out.hwrite) @[axi4_to_ahb.scala 289:75] + last_addr_en <= _T_613 @[axi4_to_ahb.scala 289:16] + node _T_614 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 291:31] + node _T_615 = and(_T_614, master_ready) @[axi4_to_ahb.scala 291:49] + wrbuf_en <= _T_615 @[axi4_to_ahb.scala 291:12] + node _T_616 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 292:35] + node _T_617 = and(_T_616, master_ready) @[axi4_to_ahb.scala 292:52] + wrbuf_data_en <= _T_617 @[axi4_to_ahb.scala 292:17] + node _T_618 = and(master_valid, master_ready) @[axi4_to_ahb.scala 293:34] + node _T_619 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 293:62] + node _T_620 = eq(_T_619, UInt<1>("h01")) @[axi4_to_ahb.scala 293:69] + node _T_621 = and(_T_618, _T_620) @[axi4_to_ahb.scala 293:49] + wrbuf_cmd_sent <= _T_621 @[axi4_to_ahb.scala 293:18] + node _T_622 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 294:33] + node _T_623 = and(wrbuf_cmd_sent, _T_622) @[axi4_to_ahb.scala 294:31] + wrbuf_rst <= _T_623 @[axi4_to_ahb.scala 294:13] + node _T_624 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 296:36] + node _T_625 = and(wrbuf_vld, _T_624) @[axi4_to_ahb.scala 296:34] + node _T_626 = eq(_T_625, UInt<1>("h00")) @[axi4_to_ahb.scala 296:22] + node _T_627 = and(_T_626, master_ready) @[axi4_to_ahb.scala 296:53] + io.axi.aw.ready <= _T_627 @[axi4_to_ahb.scala 296:19] + node _T_628 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 297:40] + node _T_629 = and(wrbuf_data_vld, _T_628) @[axi4_to_ahb.scala 297:38] + node _T_630 = eq(_T_629, UInt<1>("h00")) @[axi4_to_ahb.scala 297:21] + node _T_631 = and(_T_630, master_ready) @[axi4_to_ahb.scala 297:57] + io.axi.w.ready <= _T_631 @[axi4_to_ahb.scala 297:18] + node _T_632 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 298:34] + node _T_633 = eq(_T_632, UInt<1>("h00")) @[axi4_to_ahb.scala 298:22] + node _T_634 = and(_T_633, master_ready) @[axi4_to_ahb.scala 298:52] + io.axi.ar.ready <= _T_634 @[axi4_to_ahb.scala 298:19] + io.axi.r.bits.last <= UInt<1>("h01") @[axi4_to_ahb.scala 299:22] + node _T_635 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 301:71] + node _T_636 = mux(_T_635, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 301:55] + node _T_637 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 301:91] + node _T_638 = and(_T_636, _T_637) @[axi4_to_ahb.scala 301:89] + reg _T_639 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 301:51] + _T_639 <= _T_638 @[axi4_to_ahb.scala 301:51] + wrbuf_vld <= _T_639 @[axi4_to_ahb.scala 301:21] + node _T_640 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 302:76] + node _T_641 = mux(_T_640, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 302:55] + node _T_642 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 302:102] + node _T_643 = and(_T_641, _T_642) @[axi4_to_ahb.scala 302:100] + reg _T_644 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 302:51] + _T_644 <= _T_643 @[axi4_to_ahb.scala 302:51] + wrbuf_data_vld <= _T_644 @[axi4_to_ahb.scala 302:21] + node _T_645 = bits(io.axi.aw.bits.id, 2, 0) @[axi4_to_ahb.scala 303:71] + node _T_646 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 303:105] reg _T_647 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_646 : @[Reg.scala 28:19] _T_647 <= _T_645 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_tag <= _T_647 @[axi4_to_ahb.scala 310:21] - node _T_648 = bits(io.axi.aw.bits.size, 2, 0) @[axi4_to_ahb.scala 311:73] - node _T_649 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 311:101] + wrbuf_tag <= _T_647 @[axi4_to_ahb.scala 303:21] + node _T_648 = bits(io.axi.aw.bits.size, 2, 0) @[axi4_to_ahb.scala 304:73] + node _T_649 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 304:101] reg _T_650 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_649 : @[Reg.scala 28:19] _T_650 <= _T_648 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_size <= _T_650 @[axi4_to_ahb.scala 311:21] - node _T_651 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 312:61] + wrbuf_size <= _T_650 @[axi4_to_ahb.scala 304:21] + node _T_651 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 305:61] inst rvclkhdr_2 of rvclkhdr_861 @[lib.scala 368:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset @@ -111692,8 +111682,8 @@ circuit quasar_wrapper : rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_652 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_652 <= io.axi.aw.bits.addr @[lib.scala 374:16] - wrbuf_addr <= _T_652 @[axi4_to_ahb.scala 312:21] - node _T_653 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 313:65] + wrbuf_addr <= _T_652 @[axi4_to_ahb.scala 305:21] + node _T_653 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 306:65] inst rvclkhdr_3 of rvclkhdr_862 @[lib.scala 368:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset @@ -111702,37 +111692,37 @@ circuit quasar_wrapper : rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_654 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_654 <= io.axi.w.bits.data @[lib.scala 374:16] - wrbuf_data <= _T_654 @[axi4_to_ahb.scala 313:21] - node _T_655 = bits(io.axi.w.bits.strb, 7, 0) @[axi4_to_ahb.scala 314:72] - node _T_656 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 314:105] + wrbuf_data <= _T_654 @[axi4_to_ahb.scala 306:21] + node _T_655 = bits(io.axi.w.bits.strb, 7, 0) @[axi4_to_ahb.scala 307:72] + node _T_656 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 307:105] reg _T_657 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_656 : @[Reg.scala 28:19] _T_657 <= _T_655 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_byteen <= _T_657 @[axi4_to_ahb.scala 314:21] - node _T_658 = bits(io.ahb.out.haddr, 31, 0) @[axi4_to_ahb.scala 315:71] - node _T_659 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 315:104] + wrbuf_byteen <= _T_657 @[axi4_to_ahb.scala 307:21] + node _T_658 = bits(io.ahb.out.haddr, 31, 0) @[axi4_to_ahb.scala 308:71] + node _T_659 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 308:104] reg _T_660 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_659 : @[Reg.scala 28:19] _T_660 <= _T_658 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - last_bus_addr <= _T_660 @[axi4_to_ahb.scala 315:21] - node _T_661 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 316:89] + last_bus_addr <= _T_660 @[axi4_to_ahb.scala 308:21] + node _T_661 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 309:89] reg _T_662 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_661 : @[Reg.scala 28:19] _T_662 <= buf_write_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_write <= _T_662 @[axi4_to_ahb.scala 316:21] - node _T_663 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 317:64] - node _T_664 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 317:99] + buf_write <= _T_662 @[axi4_to_ahb.scala 309:21] + node _T_663 = bits(buf_tag_in, 2, 0) @[axi4_to_ahb.scala 310:64] + node _T_664 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 310:99] reg _T_665 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_664 : @[Reg.scala 28:19] _T_665 <= _T_663 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_tag <= _T_665 @[axi4_to_ahb.scala 317:21] - node _T_666 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 318:42] - node _T_667 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 318:61] - node _T_668 = bits(_T_667, 0, 0) @[axi4_to_ahb.scala 318:78] + buf_tag <= _T_665 @[axi4_to_ahb.scala 310:21] + node _T_666 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 311:42] + node _T_667 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 311:61] + node _T_668 = bits(_T_667, 0, 0) @[axi4_to_ahb.scala 311:78] inst rvclkhdr_4 of rvclkhdr_863 @[lib.scala 368:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset @@ -111741,30 +111731,30 @@ circuit quasar_wrapper : rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_669 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_669 <= _T_666 @[lib.scala 374:16] - buf_addr <= _T_669 @[axi4_to_ahb.scala 318:21] - node _T_670 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 319:65] - node _T_671 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 319:94] + buf_addr <= _T_669 @[axi4_to_ahb.scala 311:21] + node _T_670 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 312:65] + node _T_671 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 312:94] reg _T_672 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_671 : @[Reg.scala 28:19] _T_672 <= _T_670 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_size <= _T_672 @[axi4_to_ahb.scala 319:21] - node _T_673 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 320:91] + buf_size <= _T_672 @[axi4_to_ahb.scala 312:21] + node _T_673 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 313:91] reg _T_674 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_673 : @[Reg.scala 28:19] _T_674 <= buf_aligned_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_aligned <= _T_674 @[axi4_to_ahb.scala 320:21] - node _T_675 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 321:67] - node _T_676 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 321:96] + buf_aligned <= _T_674 @[axi4_to_ahb.scala 313:21] + node _T_675 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 314:67] + node _T_676 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 314:96] reg _T_677 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_676 : @[Reg.scala 28:19] _T_677 <= _T_675 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_byteen <= _T_677 @[axi4_to_ahb.scala 321:21] - node _T_678 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 322:42] - node _T_679 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 322:66] - node _T_680 = bits(_T_679, 0, 0) @[axi4_to_ahb.scala 322:89] + buf_byteen <= _T_677 @[axi4_to_ahb.scala 314:21] + node _T_678 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 315:42] + node _T_679 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 315:66] + node _T_680 = bits(_T_679, 0, 0) @[axi4_to_ahb.scala 315:89] inst rvclkhdr_5 of rvclkhdr_864 @[lib.scala 368:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset @@ -111773,98 +111763,98 @@ circuit quasar_wrapper : rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_681 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_681 <= _T_678 @[lib.scala 374:16] - buf_data <= _T_681 @[axi4_to_ahb.scala 322:21] - node _T_682 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 323:89] + buf_data <= _T_681 @[axi4_to_ahb.scala 315:21] + node _T_682 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 316:89] reg _T_683 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_682 : @[Reg.scala 28:19] _T_683 <= buf_write @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_write <= _T_683 @[axi4_to_ahb.scala 323:21] - node _T_684 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 324:61] - node _T_685 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 324:99] + slvbuf_write <= _T_683 @[axi4_to_ahb.scala 316:21] + node _T_684 = bits(buf_tag, 2, 0) @[axi4_to_ahb.scala 317:61] + node _T_685 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 317:99] reg _T_686 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_685 : @[Reg.scala 28:19] _T_686 <= _T_684 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_tag <= _T_686 @[axi4_to_ahb.scala 324:21] - node _T_687 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 325:99] + slvbuf_tag <= _T_686 @[axi4_to_ahb.scala 317:21] + node _T_687 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 318:99] reg _T_688 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_687 : @[Reg.scala 28:19] _T_688 <= slvbuf_error_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_error <= _T_688 @[axi4_to_ahb.scala 325:21] - node _T_689 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 326:72] - node _T_690 = mux(_T_689, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 326:56] - node _T_691 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 326:92] - node _T_692 = and(_T_690, _T_691) @[axi4_to_ahb.scala 326:90] - reg _T_693 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 326:52] - _T_693 <= _T_692 @[axi4_to_ahb.scala 326:52] - cmd_doneQ <= _T_693 @[axi4_to_ahb.scala 326:21] - node _T_694 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 327:71] - node _T_695 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 327:110] + slvbuf_error <= _T_688 @[axi4_to_ahb.scala 318:21] + node _T_689 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 319:72] + node _T_690 = mux(_T_689, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 319:56] + node _T_691 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 319:92] + node _T_692 = and(_T_690, _T_691) @[axi4_to_ahb.scala 319:90] + reg _T_693 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 319:52] + _T_693 <= _T_692 @[axi4_to_ahb.scala 319:52] + cmd_doneQ <= _T_693 @[axi4_to_ahb.scala 319:21] + node _T_694 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 320:71] + node _T_695 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 320:110] reg _T_696 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_695 : @[Reg.scala 28:19] _T_696 <= _T_694 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_cmd_byte_ptrQ <= _T_696 @[axi4_to_ahb.scala 327:21] - reg _T_697 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 328:52] - _T_697 <= io.ahb.in.hready @[axi4_to_ahb.scala 328:52] - ahb_hready_q <= _T_697 @[axi4_to_ahb.scala 328:21] - node _T_698 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 329:70] - reg _T_699 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 329:52] - _T_699 <= _T_698 @[axi4_to_ahb.scala 329:52] - ahb_htrans_q <= _T_699 @[axi4_to_ahb.scala 329:21] - reg _T_700 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 330:57] - _T_700 <= io.ahb.out.hwrite @[axi4_to_ahb.scala 330:57] - ahb_hwrite_q <= _T_700 @[axi4_to_ahb.scala 330:21] - reg _T_701 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 331:52] - _T_701 <= io.ahb.in.hresp @[axi4_to_ahb.scala 331:52] - ahb_hresp_q <= _T_701 @[axi4_to_ahb.scala 331:21] - node _T_702 = bits(io.ahb.in.hrdata, 63, 0) @[axi4_to_ahb.scala 332:74] - reg _T_703 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 332:57] - _T_703 <= _T_702 @[axi4_to_ahb.scala 332:57] - ahb_hrdata_q <= _T_703 @[axi4_to_ahb.scala 332:21] - node _T_704 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 334:43] - node _T_705 = or(_T_704, io.clk_override) @[axi4_to_ahb.scala 334:58] - node _T_706 = and(io.bus_clk_en, _T_705) @[axi4_to_ahb.scala 334:30] - buf_clken <= _T_706 @[axi4_to_ahb.scala 334:13] - node _T_707 = bits(io.ahb.out.htrans, 1, 1) @[axi4_to_ahb.scala 335:76] - node _T_708 = and(io.ahb.in.hready, _T_707) @[axi4_to_ahb.scala 335:57] - node _T_709 = or(_T_708, io.clk_override) @[axi4_to_ahb.scala 335:81] - node _T_710 = and(io.bus_clk_en, _T_709) @[axi4_to_ahb.scala 335:36] - ahbm_addr_clken <= _T_710 @[axi4_to_ahb.scala 335:19] - node _T_711 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 336:50] - node _T_712 = or(_T_711, io.clk_override) @[axi4_to_ahb.scala 336:60] - node _T_713 = and(io.bus_clk_en, _T_712) @[axi4_to_ahb.scala 336:36] - ahbm_data_clken <= _T_713 @[axi4_to_ahb.scala 336:19] + buf_cmd_byte_ptrQ <= _T_696 @[axi4_to_ahb.scala 320:21] + reg _T_697 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 321:52] + _T_697 <= io.ahb.in.hready @[axi4_to_ahb.scala 321:52] + ahb_hready_q <= _T_697 @[axi4_to_ahb.scala 321:21] + node _T_698 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 322:70] + reg _T_699 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 322:52] + _T_699 <= _T_698 @[axi4_to_ahb.scala 322:52] + ahb_htrans_q <= _T_699 @[axi4_to_ahb.scala 322:21] + reg _T_700 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 323:57] + _T_700 <= io.ahb.out.hwrite @[axi4_to_ahb.scala 323:57] + ahb_hwrite_q <= _T_700 @[axi4_to_ahb.scala 323:21] + reg _T_701 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 324:52] + _T_701 <= io.ahb.in.hresp @[axi4_to_ahb.scala 324:52] + ahb_hresp_q <= _T_701 @[axi4_to_ahb.scala 324:21] + node _T_702 = bits(io.ahb.in.hrdata, 63, 0) @[axi4_to_ahb.scala 325:74] + reg _T_703 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 325:57] + _T_703 <= _T_702 @[axi4_to_ahb.scala 325:57] + ahb_hrdata_q <= _T_703 @[axi4_to_ahb.scala 325:21] + node _T_704 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 327:43] + node _T_705 = or(_T_704, io.clk_override) @[axi4_to_ahb.scala 327:58] + node _T_706 = and(io.bus_clk_en, _T_705) @[axi4_to_ahb.scala 327:30] + buf_clken <= _T_706 @[axi4_to_ahb.scala 327:13] + node _T_707 = bits(io.ahb.out.htrans, 1, 1) @[axi4_to_ahb.scala 328:76] + node _T_708 = and(io.ahb.in.hready, _T_707) @[axi4_to_ahb.scala 328:57] + node _T_709 = or(_T_708, io.clk_override) @[axi4_to_ahb.scala 328:81] + node _T_710 = and(io.bus_clk_en, _T_709) @[axi4_to_ahb.scala 328:36] + ahbm_addr_clken <= _T_710 @[axi4_to_ahb.scala 328:19] + node _T_711 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 329:50] + node _T_712 = or(_T_711, io.clk_override) @[axi4_to_ahb.scala 329:60] + node _T_713 = and(io.bus_clk_en, _T_712) @[axi4_to_ahb.scala 329:36] + ahbm_data_clken <= _T_713 @[axi4_to_ahb.scala 329:19] inst rvclkhdr_6 of rvclkhdr_865 @[lib.scala 343:22] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset rvclkhdr_6.io.clk <= clock @[lib.scala 344:17] rvclkhdr_6.io.en <= buf_clken @[lib.scala 345:16] rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 339:12] + buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 332:12] inst rvclkhdr_7 of rvclkhdr_866 @[lib.scala 343:22] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= reset rvclkhdr_7.io.clk <= clock @[lib.scala 344:17] rvclkhdr_7.io.en <= io.bus_clk_en @[lib.scala 345:16] rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 340:12] + ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 333:12] inst rvclkhdr_8 of rvclkhdr_867 @[lib.scala 343:22] rvclkhdr_8.clock <= clock rvclkhdr_8.reset <= reset rvclkhdr_8.io.clk <= clock @[lib.scala 344:17] rvclkhdr_8.io.en <= ahbm_addr_clken @[lib.scala 345:16] rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 341:17] + ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 334:17] inst rvclkhdr_9 of rvclkhdr_868 @[lib.scala 343:22] rvclkhdr_9.clock <= clock rvclkhdr_9.reset <= reset rvclkhdr_9.io.clk <= clock @[lib.scala 344:17] rvclkhdr_9.io.en <= ahbm_data_clken @[lib.scala 345:16] rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 342:17] + ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 335:17] extmodule gated_latch_869 : output Q : Clock @@ -112109,36 +112099,36 @@ circuit quasar_wrapper : module axi4_to_ahb_2 : input clock : Clock input reset : AsyncReset - output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ahb : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}} + output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ahb : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}} wire buf_rst : UInt<1> buf_rst <= UInt<1>("h00") - buf_rst <= UInt<1>("h00") @[axi4_to_ahb.scala 28:11] - io.ahb.out.htrans <= UInt<1>("h00") @[axi4_to_ahb.scala 29:21] + buf_rst <= UInt<1>("h00") @[axi4_to_ahb.scala 21:11] + io.ahb.out.htrans <= UInt<1>("h00") @[axi4_to_ahb.scala 22:21] wire buf_state_en : UInt<1> buf_state_en <= UInt<1>("h00") - wire ahbm_clk : Clock @[axi4_to_ahb.scala 31:22] - wire ahbm_addr_clk : Clock @[axi4_to_ahb.scala 32:27] - wire ahbm_data_clk : Clock @[axi4_to_ahb.scala 33:27] + wire ahbm_clk : Clock @[axi4_to_ahb.scala 24:22] + wire ahbm_addr_clk : Clock @[axi4_to_ahb.scala 25:27] + wire ahbm_data_clk : Clock @[axi4_to_ahb.scala 26:27] wire buf_state : UInt<3> buf_state <= UInt<3>("h00") wire buf_nxtstate : UInt<3> buf_nxtstate <= UInt<3>("h00") - node _T = bits(buf_state_en, 0, 0) @[axi4_to_ahb.scala 37:70] - node _T_1 = mux(_T, buf_nxtstate, buf_state) @[axi4_to_ahb.scala 37:50] - node _T_2 = eq(buf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 37:108] + node _T = bits(buf_state_en, 0, 0) @[axi4_to_ahb.scala 30:70] + node _T_1 = mux(_T, buf_nxtstate, buf_state) @[axi4_to_ahb.scala 30:50] + node _T_2 = eq(buf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 30:108] node _T_3 = bits(_T_2, 0, 0) @[Bitwise.scala 72:15] node _T_4 = mux(_T_3, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_5 = and(_T_1, _T_4) @[axi4_to_ahb.scala 37:98] - reg _T_6 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 37:45] - _T_6 <= _T_5 @[axi4_to_ahb.scala 37:45] - buf_state <= _T_6 @[axi4_to_ahb.scala 37:13] + node _T_5 = and(_T_1, _T_4) @[axi4_to_ahb.scala 30:98] + reg _T_6 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 30:45] + _T_6 <= _T_5 @[axi4_to_ahb.scala 30:45] + buf_state <= _T_6 @[axi4_to_ahb.scala 30:13] wire slave_valid : UInt<1> slave_valid <= UInt<1>("h00") wire slave_ready : UInt<1> slave_ready <= UInt<1>("h00") - wire slave_tag : UInt<1> - slave_tag <= UInt<1>("h00") + wire slave_tag : UInt<3> + slave_tag <= UInt<3>("h00") wire slave_rdata : UInt<64> slave_rdata <= UInt<64>("h00") wire slave_opc : UInt<4> @@ -112155,8 +112145,8 @@ circuit quasar_wrapper : wrbuf_vld <= UInt<1>("h00") wire wrbuf_data_vld : UInt<1> wrbuf_data_vld <= UInt<1>("h00") - wire wrbuf_tag : UInt<1> - wrbuf_tag <= UInt<1>("h00") + wire wrbuf_tag : UInt<3> + wrbuf_tag <= UInt<3>("h00") wire wrbuf_size : UInt<3> wrbuf_size <= UInt<3>("h00") wire wrbuf_addr : UInt<32> @@ -112167,14 +112157,14 @@ circuit quasar_wrapper : wrbuf_byteen <= UInt<8>("h00") wire bus_write_clk_en : UInt<1> bus_write_clk_en <= UInt<1>("h00") - wire bus_clk : Clock @[axi4_to_ahb.scala 57:21] - wire bus_write_clk : Clock @[axi4_to_ahb.scala 58:27] + wire bus_clk : Clock @[axi4_to_ahb.scala 50:21] + wire bus_write_clk : Clock @[axi4_to_ahb.scala 51:27] wire master_valid : UInt<1> master_valid <= UInt<1>("h00") wire master_ready : UInt<1> master_ready <= UInt<1>("h00") - wire master_tag : UInt<1> - master_tag <= UInt<1>("h00") + wire master_tag : UInt<3> + master_tag <= UInt<3>("h00") wire master_addr : UInt<32> master_addr <= UInt<32>("h00") wire master_wdata : UInt<64> @@ -112197,10 +112187,10 @@ circuit quasar_wrapper : buf_aligned <= UInt<1>("h00") wire buf_data : UInt<64> buf_data <= UInt<64>("h00") - wire buf_tag : UInt<1> - buf_tag <= UInt<1>("h00") - wire buf_tag_in : UInt<1> - buf_tag_in <= UInt<1>("h00") + wire buf_tag : UInt<3> + buf_tag <= UInt<3>("h00") + wire buf_tag_in : UInt<3> + buf_tag_in <= UInt<3>("h00") wire buf_addr_in : UInt<32> buf_addr_in <= UInt<32>("h00") wire buf_byteen_in : UInt<8> @@ -112255,8 +112245,8 @@ circuit quasar_wrapper : slvbuf_write <= UInt<1>("h00") wire slvbuf_error : UInt<1> slvbuf_error <= UInt<1>("h00") - wire slvbuf_tag : UInt<1> - slvbuf_tag <= UInt<1>("h00") + wire slvbuf_tag : UInt<3> + slvbuf_tag <= UInt<3>("h00") wire slvbuf_error_in : UInt<1> slvbuf_error_in <= UInt<1>("h00") wire slvbuf_wr_en : UInt<1> @@ -112277,125 +112267,125 @@ circuit quasar_wrapper : ahbm_addr_clken <= UInt<1>("h00") wire ahbm_data_clken : UInt<1> ahbm_data_clken <= UInt<1>("h00") - wire buf_clk : Clock @[axi4_to_ahb.scala 125:21] - node _T_7 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 146:27] - wr_cmd_vld <= _T_7 @[axi4_to_ahb.scala 146:14] - node _T_8 = or(wr_cmd_vld, io.axi.ar.valid) @[axi4_to_ahb.scala 147:30] - master_valid <= _T_8 @[axi4_to_ahb.scala 147:16] - node _T_9 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 148:38] - node _T_10 = bits(wrbuf_tag, 0, 0) @[axi4_to_ahb.scala 148:51] - node _T_11 = bits(io.axi.ar.bits.id, 0, 0) @[axi4_to_ahb.scala 148:82] - node _T_12 = mux(_T_9, _T_10, _T_11) @[axi4_to_ahb.scala 148:20] - master_tag <= _T_12 @[axi4_to_ahb.scala 148:14] - node _T_13 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 149:38] - node _T_14 = mux(_T_13, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 149:20] - master_opc <= _T_14 @[axi4_to_ahb.scala 149:14] - node _T_15 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 150:39] - node _T_16 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 150:53] - node _T_17 = bits(io.axi.ar.bits.addr, 31, 0) @[axi4_to_ahb.scala 150:81] - node _T_18 = mux(_T_15, _T_16, _T_17) @[axi4_to_ahb.scala 150:21] - master_addr <= _T_18 @[axi4_to_ahb.scala 150:15] - node _T_19 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 151:39] - node _T_20 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 151:53] - node _T_21 = bits(io.axi.ar.bits.size, 2, 0) @[axi4_to_ahb.scala 151:80] - node _T_22 = mux(_T_19, _T_20, _T_21) @[axi4_to_ahb.scala 151:21] - master_size <= _T_22 @[axi4_to_ahb.scala 151:15] - node _T_23 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 152:32] - master_byteen <= _T_23 @[axi4_to_ahb.scala 152:17] - node _T_24 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 153:29] - master_wdata <= _T_24 @[axi4_to_ahb.scala 153:16] - node _T_25 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 156:33] - node _T_26 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 156:58] - node _T_27 = and(_T_25, _T_26) @[axi4_to_ahb.scala 156:47] - io.axi.b.valid <= _T_27 @[axi4_to_ahb.scala 156:18] - node _T_28 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 157:38] - node _T_29 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 157:65] - node _T_30 = mux(_T_29, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 157:55] - node _T_31 = mux(_T_28, UInt<2>("h02"), _T_30) @[axi4_to_ahb.scala 157:28] - io.axi.b.bits.resp <= _T_31 @[axi4_to_ahb.scala 157:22] - node _T_32 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 158:32] - io.axi.b.bits.id <= _T_32 @[axi4_to_ahb.scala 158:20] - node _T_33 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 160:33] - node _T_34 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 160:59] - node _T_35 = eq(_T_34, UInt<1>("h00")) @[axi4_to_ahb.scala 160:66] - node _T_36 = and(_T_33, _T_35) @[axi4_to_ahb.scala 160:47] - io.axi.r.valid <= _T_36 @[axi4_to_ahb.scala 160:18] - node _T_37 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 161:38] - node _T_38 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 161:65] - node _T_39 = mux(_T_38, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 161:55] - node _T_40 = mux(_T_37, UInt<2>("h02"), _T_39) @[axi4_to_ahb.scala 161:28] - io.axi.r.bits.resp <= _T_40 @[axi4_to_ahb.scala 161:22] - node _T_41 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 162:32] - io.axi.r.bits.id <= _T_41 @[axi4_to_ahb.scala 162:20] - node _T_42 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 163:36] - io.axi.r.bits.data <= _T_42 @[axi4_to_ahb.scala 163:22] - node _T_43 = and(io.axi.b.ready, io.axi.r.ready) @[axi4_to_ahb.scala 164:33] - slave_ready <= _T_43 @[axi4_to_ahb.scala 164:15] - node _T_44 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 167:57] - node _T_45 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 167:94] - node _T_46 = or(_T_44, _T_45) @[axi4_to_ahb.scala 167:76] - node _T_47 = and(io.bus_clk_en, _T_46) @[axi4_to_ahb.scala 167:37] - bus_write_clk_en <= _T_47 @[axi4_to_ahb.scala 167:20] + wire buf_clk : Clock @[axi4_to_ahb.scala 118:21] + node _T_7 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 139:27] + wr_cmd_vld <= _T_7 @[axi4_to_ahb.scala 139:14] + node _T_8 = or(wr_cmd_vld, io.axi.ar.valid) @[axi4_to_ahb.scala 140:30] + master_valid <= _T_8 @[axi4_to_ahb.scala 140:16] + node _T_9 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 141:38] + node _T_10 = bits(wrbuf_tag, 2, 0) @[axi4_to_ahb.scala 141:51] + node _T_11 = bits(io.axi.ar.bits.id, 2, 0) @[axi4_to_ahb.scala 141:82] + node _T_12 = mux(_T_9, _T_10, _T_11) @[axi4_to_ahb.scala 141:20] + master_tag <= _T_12 @[axi4_to_ahb.scala 141:14] + node _T_13 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 142:38] + node _T_14 = mux(_T_13, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 142:20] + master_opc <= _T_14 @[axi4_to_ahb.scala 142:14] + node _T_15 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 143:39] + node _T_16 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 143:53] + node _T_17 = bits(io.axi.ar.bits.addr, 31, 0) @[axi4_to_ahb.scala 143:81] + node _T_18 = mux(_T_15, _T_16, _T_17) @[axi4_to_ahb.scala 143:21] + master_addr <= _T_18 @[axi4_to_ahb.scala 143:15] + node _T_19 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 144:39] + node _T_20 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 144:53] + node _T_21 = bits(io.axi.ar.bits.size, 2, 0) @[axi4_to_ahb.scala 144:80] + node _T_22 = mux(_T_19, _T_20, _T_21) @[axi4_to_ahb.scala 144:21] + master_size <= _T_22 @[axi4_to_ahb.scala 144:15] + node _T_23 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 145:32] + master_byteen <= _T_23 @[axi4_to_ahb.scala 145:17] + node _T_24 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 146:29] + master_wdata <= _T_24 @[axi4_to_ahb.scala 146:16] + node _T_25 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 149:33] + node _T_26 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 149:58] + node _T_27 = and(_T_25, _T_26) @[axi4_to_ahb.scala 149:47] + io.axi.b.valid <= _T_27 @[axi4_to_ahb.scala 149:18] + node _T_28 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 150:38] + node _T_29 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 150:65] + node _T_30 = mux(_T_29, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 150:55] + node _T_31 = mux(_T_28, UInt<2>("h02"), _T_30) @[axi4_to_ahb.scala 150:28] + io.axi.b.bits.resp <= _T_31 @[axi4_to_ahb.scala 150:22] + node _T_32 = bits(slave_tag, 2, 0) @[axi4_to_ahb.scala 151:32] + io.axi.b.bits.id <= _T_32 @[axi4_to_ahb.scala 151:20] + node _T_33 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 153:33] + node _T_34 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 153:59] + node _T_35 = eq(_T_34, UInt<1>("h00")) @[axi4_to_ahb.scala 153:66] + node _T_36 = and(_T_33, _T_35) @[axi4_to_ahb.scala 153:47] + io.axi.r.valid <= _T_36 @[axi4_to_ahb.scala 153:18] + node _T_37 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 154:38] + node _T_38 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 154:65] + node _T_39 = mux(_T_38, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 154:55] + node _T_40 = mux(_T_37, UInt<2>("h02"), _T_39) @[axi4_to_ahb.scala 154:28] + io.axi.r.bits.resp <= _T_40 @[axi4_to_ahb.scala 154:22] + node _T_41 = bits(slave_tag, 2, 0) @[axi4_to_ahb.scala 155:32] + io.axi.r.bits.id <= _T_41 @[axi4_to_ahb.scala 155:20] + node _T_42 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 156:36] + io.axi.r.bits.data <= _T_42 @[axi4_to_ahb.scala 156:22] + node _T_43 = and(io.axi.b.ready, io.axi.r.ready) @[axi4_to_ahb.scala 157:33] + slave_ready <= _T_43 @[axi4_to_ahb.scala 157:15] + node _T_44 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 160:57] + node _T_45 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 160:94] + node _T_46 = or(_T_44, _T_45) @[axi4_to_ahb.scala 160:76] + node _T_47 = and(io.bus_clk_en, _T_46) @[axi4_to_ahb.scala 160:37] + bus_write_clk_en <= _T_47 @[axi4_to_ahb.scala 160:20] inst rvclkhdr of rvclkhdr_869 @[lib.scala 343:22] rvclkhdr.clock <= clock rvclkhdr.reset <= reset rvclkhdr.io.clk <= clock @[lib.scala 344:17] rvclkhdr.io.en <= io.bus_clk_en @[lib.scala 345:16] rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - bus_clk <= rvclkhdr.io.l1clk @[axi4_to_ahb.scala 169:11] - node _T_48 = bits(bus_write_clk_en, 0, 0) @[axi4_to_ahb.scala 170:59] + bus_clk <= rvclkhdr.io.l1clk @[axi4_to_ahb.scala 162:11] + node _T_48 = bits(bus_write_clk_en, 0, 0) @[axi4_to_ahb.scala 163:59] inst rvclkhdr_1 of rvclkhdr_870 @[lib.scala 343:22] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] rvclkhdr_1.io.en <= _T_48 @[lib.scala 345:16] rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - bus_write_clk <= rvclkhdr_1.io.l1clk @[axi4_to_ahb.scala 170:17] + bus_write_clk <= rvclkhdr_1.io.l1clk @[axi4_to_ahb.scala 163:17] node _T_49 = eq(UInt<3>("h00"), buf_state) @[Conditional.scala 37:30] when _T_49 : @[Conditional.scala 40:58] - master_ready <= UInt<1>("h01") @[axi4_to_ahb.scala 174:20] - node _T_50 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 175:34] - node _T_51 = eq(_T_50, UInt<1>("h01")) @[axi4_to_ahb.scala 175:41] - buf_write_in <= _T_51 @[axi4_to_ahb.scala 175:20] - node _T_52 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 176:46] - node _T_53 = mux(_T_52, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 176:26] - buf_nxtstate <= _T_53 @[axi4_to_ahb.scala 176:20] - node _T_54 = and(master_valid, UInt<1>("h01")) @[axi4_to_ahb.scala 177:36] - buf_state_en <= _T_54 @[axi4_to_ahb.scala 177:20] - buf_wr_en <= buf_state_en @[axi4_to_ahb.scala 178:17] - node _T_55 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 179:54] - node _T_56 = and(buf_state_en, _T_55) @[axi4_to_ahb.scala 179:38] - buf_data_wr_en <= _T_56 @[axi4_to_ahb.scala 179:22] - buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 180:27] - node _T_57 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 182:50] - node _T_58 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 182:94] - node _T_59 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 142:52] - node _T_60 = tail(_T_59, 1) @[axi4_to_ahb.scala 142:52] - node _T_61 = mux(UInt<1>("h00"), _T_60, UInt<3>("h00")) @[axi4_to_ahb.scala 142:24] - node _T_62 = bits(_T_58, 0, 0) @[axi4_to_ahb.scala 143:44] - node _T_63 = geq(UInt<1>("h00"), _T_61) @[axi4_to_ahb.scala 143:62] - node _T_64 = and(_T_62, _T_63) @[axi4_to_ahb.scala 143:48] - node _T_65 = bits(_T_58, 1, 1) @[axi4_to_ahb.scala 143:44] - node _T_66 = geq(UInt<1>("h01"), _T_61) @[axi4_to_ahb.scala 143:62] - node _T_67 = and(_T_65, _T_66) @[axi4_to_ahb.scala 143:48] - node _T_68 = bits(_T_58, 2, 2) @[axi4_to_ahb.scala 143:44] - node _T_69 = geq(UInt<2>("h02"), _T_61) @[axi4_to_ahb.scala 143:62] - node _T_70 = and(_T_68, _T_69) @[axi4_to_ahb.scala 143:48] - node _T_71 = bits(_T_58, 3, 3) @[axi4_to_ahb.scala 143:44] - node _T_72 = geq(UInt<2>("h03"), _T_61) @[axi4_to_ahb.scala 143:62] - node _T_73 = and(_T_71, _T_72) @[axi4_to_ahb.scala 143:48] - node _T_74 = bits(_T_58, 4, 4) @[axi4_to_ahb.scala 143:44] - node _T_75 = geq(UInt<3>("h04"), _T_61) @[axi4_to_ahb.scala 143:62] - node _T_76 = and(_T_74, _T_75) @[axi4_to_ahb.scala 143:48] - node _T_77 = bits(_T_58, 5, 5) @[axi4_to_ahb.scala 143:44] - node _T_78 = geq(UInt<3>("h05"), _T_61) @[axi4_to_ahb.scala 143:62] - node _T_79 = and(_T_77, _T_78) @[axi4_to_ahb.scala 143:48] - node _T_80 = bits(_T_58, 6, 6) @[axi4_to_ahb.scala 143:44] - node _T_81 = geq(UInt<3>("h06"), _T_61) @[axi4_to_ahb.scala 143:62] - node _T_82 = and(_T_80, _T_81) @[axi4_to_ahb.scala 143:48] - node _T_83 = bits(_T_58, 7, 7) @[axi4_to_ahb.scala 143:44] - node _T_84 = geq(UInt<3>("h07"), _T_61) @[axi4_to_ahb.scala 143:62] - node _T_85 = and(_T_83, _T_84) @[axi4_to_ahb.scala 143:48] + master_ready <= UInt<1>("h01") @[axi4_to_ahb.scala 167:20] + node _T_50 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 168:34] + node _T_51 = eq(_T_50, UInt<1>("h01")) @[axi4_to_ahb.scala 168:41] + buf_write_in <= _T_51 @[axi4_to_ahb.scala 168:20] + node _T_52 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 169:46] + node _T_53 = mux(_T_52, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 169:26] + buf_nxtstate <= _T_53 @[axi4_to_ahb.scala 169:20] + node _T_54 = and(master_valid, UInt<1>("h01")) @[axi4_to_ahb.scala 170:36] + buf_state_en <= _T_54 @[axi4_to_ahb.scala 170:20] + buf_wr_en <= buf_state_en @[axi4_to_ahb.scala 171:17] + node _T_55 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 172:54] + node _T_56 = and(buf_state_en, _T_55) @[axi4_to_ahb.scala 172:38] + buf_data_wr_en <= _T_56 @[axi4_to_ahb.scala 172:22] + buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 173:27] + node _T_57 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 175:50] + node _T_58 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 175:94] + node _T_59 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] + node _T_60 = tail(_T_59, 1) @[axi4_to_ahb.scala 135:52] + node _T_61 = mux(UInt<1>("h00"), _T_60, UInt<3>("h00")) @[axi4_to_ahb.scala 135:24] + node _T_62 = bits(_T_58, 0, 0) @[axi4_to_ahb.scala 136:44] + node _T_63 = geq(UInt<1>("h00"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_64 = and(_T_62, _T_63) @[axi4_to_ahb.scala 136:48] + node _T_65 = bits(_T_58, 1, 1) @[axi4_to_ahb.scala 136:44] + node _T_66 = geq(UInt<1>("h01"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_67 = and(_T_65, _T_66) @[axi4_to_ahb.scala 136:48] + node _T_68 = bits(_T_58, 2, 2) @[axi4_to_ahb.scala 136:44] + node _T_69 = geq(UInt<2>("h02"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_70 = and(_T_68, _T_69) @[axi4_to_ahb.scala 136:48] + node _T_71 = bits(_T_58, 3, 3) @[axi4_to_ahb.scala 136:44] + node _T_72 = geq(UInt<2>("h03"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_73 = and(_T_71, _T_72) @[axi4_to_ahb.scala 136:48] + node _T_74 = bits(_T_58, 4, 4) @[axi4_to_ahb.scala 136:44] + node _T_75 = geq(UInt<3>("h04"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_76 = and(_T_74, _T_75) @[axi4_to_ahb.scala 136:48] + node _T_77 = bits(_T_58, 5, 5) @[axi4_to_ahb.scala 136:44] + node _T_78 = geq(UInt<3>("h05"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_79 = and(_T_77, _T_78) @[axi4_to_ahb.scala 136:48] + node _T_80 = bits(_T_58, 6, 6) @[axi4_to_ahb.scala 136:44] + node _T_81 = geq(UInt<3>("h06"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_82 = and(_T_80, _T_81) @[axi4_to_ahb.scala 136:48] + node _T_83 = bits(_T_58, 7, 7) @[axi4_to_ahb.scala 136:44] + node _T_84 = geq(UInt<3>("h07"), _T_61) @[axi4_to_ahb.scala 136:62] + node _T_85 = and(_T_83, _T_84) @[axi4_to_ahb.scala 136:48] node _T_86 = mux(_T_85, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_87 = mux(_T_82, UInt<3>("h06"), _T_86) @[Mux.scala 98:16] node _T_88 = mux(_T_79, UInt<3>("h05"), _T_87) @[Mux.scala 98:16] @@ -112404,193 +112394,193 @@ circuit quasar_wrapper : node _T_91 = mux(_T_70, UInt<2>("h02"), _T_90) @[Mux.scala 98:16] node _T_92 = mux(_T_67, UInt<1>("h01"), _T_91) @[Mux.scala 98:16] node _T_93 = mux(_T_64, UInt<1>("h00"), _T_92) @[Mux.scala 98:16] - node _T_94 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 182:124] - node _T_95 = mux(_T_57, _T_93, _T_94) @[axi4_to_ahb.scala 182:30] - buf_cmd_byte_ptr <= _T_95 @[axi4_to_ahb.scala 182:24] - bypass_en <= buf_state_en @[axi4_to_ahb.scala 183:17] - node _T_96 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 184:51] - node _T_97 = and(bypass_en, _T_96) @[axi4_to_ahb.scala 184:35] - rd_bypass_idle <= _T_97 @[axi4_to_ahb.scala 184:22] + node _T_94 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 175:124] + node _T_95 = mux(_T_57, _T_93, _T_94) @[axi4_to_ahb.scala 175:30] + buf_cmd_byte_ptr <= _T_95 @[axi4_to_ahb.scala 175:24] + bypass_en <= buf_state_en @[axi4_to_ahb.scala 176:17] + node _T_96 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 177:51] + node _T_97 = and(bypass_en, _T_96) @[axi4_to_ahb.scala 177:35] + rd_bypass_idle <= _T_97 @[axi4_to_ahb.scala 177:22] node _T_98 = bits(bypass_en, 0, 0) @[Bitwise.scala 72:15] node _T_99 = mux(_T_98, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_100 = and(_T_99, UInt<2>("h02")) @[axi4_to_ahb.scala 185:49] - io.ahb.out.htrans <= _T_100 @[axi4_to_ahb.scala 185:25] + node _T_100 = and(_T_99, UInt<2>("h02")) @[axi4_to_ahb.scala 178:49] + io.ahb.out.htrans <= _T_100 @[axi4_to_ahb.scala 178:25] skip @[Conditional.scala 40:58] else : @[Conditional.scala 39:67] node _T_101 = eq(UInt<3>("h01"), buf_state) @[Conditional.scala 37:30] when _T_101 : @[Conditional.scala 39:67] - node _T_102 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 189:54] - node _T_103 = eq(_T_102, UInt<1>("h00")) @[axi4_to_ahb.scala 189:61] - node _T_104 = and(master_valid, _T_103) @[axi4_to_ahb.scala 189:41] - node _T_105 = bits(_T_104, 0, 0) @[axi4_to_ahb.scala 189:82] - node _T_106 = mux(_T_105, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 189:26] - buf_nxtstate <= _T_106 @[axi4_to_ahb.scala 189:20] - node _T_107 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 190:51] - node _T_108 = neq(_T_107, UInt<1>("h00")) @[axi4_to_ahb.scala 190:58] - node _T_109 = and(ahb_hready_q, _T_108) @[axi4_to_ahb.scala 190:36] - node _T_110 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 190:72] - node _T_111 = and(_T_109, _T_110) @[axi4_to_ahb.scala 190:70] - buf_state_en <= _T_111 @[axi4_to_ahb.scala 190:20] - node _T_112 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 191:34] - node _T_113 = and(buf_state_en, _T_112) @[axi4_to_ahb.scala 191:32] - cmd_done <= _T_113 @[axi4_to_ahb.scala 191:16] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 192:20] - node _T_114 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 193:52] - node _T_115 = neq(_T_114, UInt<1>("h00")) @[axi4_to_ahb.scala 193:59] - node _T_116 = and(ahb_hready_q, _T_115) @[axi4_to_ahb.scala 193:37] - node _T_117 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 193:73] - node _T_118 = and(_T_116, _T_117) @[axi4_to_ahb.scala 193:71] - node _T_119 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 193:122] - node _T_120 = eq(_T_119, UInt<1>("h00")) @[axi4_to_ahb.scala 193:129] - node _T_121 = and(master_valid, _T_120) @[axi4_to_ahb.scala 193:109] - node _T_122 = bits(_T_121, 0, 0) @[axi4_to_ahb.scala 193:150] - node _T_123 = mux(_T_122, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 193:94] - node _T_124 = eq(_T_123, UInt<3>("h06")) @[axi4_to_ahb.scala 193:174] - node _T_125 = and(_T_118, _T_124) @[axi4_to_ahb.scala 193:88] - master_ready <= _T_125 @[axi4_to_ahb.scala 193:20] - buf_wr_en <= master_ready @[axi4_to_ahb.scala 194:17] - node _T_126 = and(master_ready, master_valid) @[axi4_to_ahb.scala 195:33] - bypass_en <= _T_126 @[axi4_to_ahb.scala 195:17] - node _T_127 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 196:47] - node _T_128 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 196:62] - node _T_129 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 196:78] - node _T_130 = mux(_T_127, _T_128, _T_129) @[axi4_to_ahb.scala 196:30] - buf_cmd_byte_ptr <= _T_130 @[axi4_to_ahb.scala 196:24] - node _T_131 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 197:48] - node _T_132 = or(_T_131, bypass_en) @[axi4_to_ahb.scala 197:62] + node _T_102 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 182:54] + node _T_103 = eq(_T_102, UInt<1>("h00")) @[axi4_to_ahb.scala 182:61] + node _T_104 = and(master_valid, _T_103) @[axi4_to_ahb.scala 182:41] + node _T_105 = bits(_T_104, 0, 0) @[axi4_to_ahb.scala 182:82] + node _T_106 = mux(_T_105, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 182:26] + buf_nxtstate <= _T_106 @[axi4_to_ahb.scala 182:20] + node _T_107 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 183:51] + node _T_108 = neq(_T_107, UInt<1>("h00")) @[axi4_to_ahb.scala 183:58] + node _T_109 = and(ahb_hready_q, _T_108) @[axi4_to_ahb.scala 183:36] + node _T_110 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 183:72] + node _T_111 = and(_T_109, _T_110) @[axi4_to_ahb.scala 183:70] + buf_state_en <= _T_111 @[axi4_to_ahb.scala 183:20] + node _T_112 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 184:34] + node _T_113 = and(buf_state_en, _T_112) @[axi4_to_ahb.scala 184:32] + cmd_done <= _T_113 @[axi4_to_ahb.scala 184:16] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 185:20] + node _T_114 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 186:52] + node _T_115 = neq(_T_114, UInt<1>("h00")) @[axi4_to_ahb.scala 186:59] + node _T_116 = and(ahb_hready_q, _T_115) @[axi4_to_ahb.scala 186:37] + node _T_117 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 186:73] + node _T_118 = and(_T_116, _T_117) @[axi4_to_ahb.scala 186:71] + node _T_119 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 186:122] + node _T_120 = eq(_T_119, UInt<1>("h00")) @[axi4_to_ahb.scala 186:129] + node _T_121 = and(master_valid, _T_120) @[axi4_to_ahb.scala 186:109] + node _T_122 = bits(_T_121, 0, 0) @[axi4_to_ahb.scala 186:150] + node _T_123 = mux(_T_122, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 186:94] + node _T_124 = eq(_T_123, UInt<3>("h06")) @[axi4_to_ahb.scala 186:174] + node _T_125 = and(_T_118, _T_124) @[axi4_to_ahb.scala 186:88] + master_ready <= _T_125 @[axi4_to_ahb.scala 186:20] + buf_wr_en <= master_ready @[axi4_to_ahb.scala 187:17] + node _T_126 = and(master_ready, master_valid) @[axi4_to_ahb.scala 188:33] + bypass_en <= _T_126 @[axi4_to_ahb.scala 188:17] + node _T_127 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 189:47] + node _T_128 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 189:62] + node _T_129 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 189:78] + node _T_130 = mux(_T_127, _T_128, _T_129) @[axi4_to_ahb.scala 189:30] + buf_cmd_byte_ptr <= _T_130 @[axi4_to_ahb.scala 189:24] + node _T_131 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 190:48] + node _T_132 = or(_T_131, bypass_en) @[axi4_to_ahb.scala 190:62] node _T_133 = bits(_T_132, 0, 0) @[Bitwise.scala 72:15] node _T_134 = mux(_T_133, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_135 = and(UInt<2>("h02"), _T_134) @[axi4_to_ahb.scala 197:36] - io.ahb.out.htrans <= _T_135 @[axi4_to_ahb.scala 197:25] + node _T_135 = and(UInt<2>("h02"), _T_134) @[axi4_to_ahb.scala 190:36] + io.ahb.out.htrans <= _T_135 @[axi4_to_ahb.scala 190:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_136 = eq(UInt<3>("h06"), buf_state) @[Conditional.scala 37:30] when _T_136 : @[Conditional.scala 39:67] - node _T_137 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 201:39] - node _T_138 = and(ahb_hready_q, _T_137) @[axi4_to_ahb.scala 201:37] - node _T_139 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 201:82] - node _T_140 = eq(_T_139, UInt<1>("h01")) @[axi4_to_ahb.scala 201:89] - node _T_141 = and(master_valid, _T_140) @[axi4_to_ahb.scala 201:70] - node _T_142 = not(_T_141) @[axi4_to_ahb.scala 201:55] - node _T_143 = and(_T_138, _T_142) @[axi4_to_ahb.scala 201:53] - master_ready <= _T_143 @[axi4_to_ahb.scala 201:20] - node _T_144 = and(master_valid, master_ready) @[axi4_to_ahb.scala 202:34] - node _T_145 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 202:62] - node _T_146 = eq(_T_145, UInt<1>("h00")) @[axi4_to_ahb.scala 202:69] - node _T_147 = and(_T_144, _T_146) @[axi4_to_ahb.scala 202:49] - buf_wr_en <= _T_147 @[axi4_to_ahb.scala 202:17] - node _T_148 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 203:45] - node _T_149 = and(master_valid, master_ready) @[axi4_to_ahb.scala 203:82] - node _T_150 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 203:110] - node _T_151 = eq(_T_150, UInt<1>("h00")) @[axi4_to_ahb.scala 203:117] - node _T_152 = and(_T_149, _T_151) @[axi4_to_ahb.scala 203:97] - node _T_153 = bits(_T_152, 0, 0) @[axi4_to_ahb.scala 203:138] - node _T_154 = mux(_T_153, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 203:67] - node _T_155 = mux(_T_148, UInt<3>("h07"), _T_154) @[axi4_to_ahb.scala 203:26] - buf_nxtstate <= _T_155 @[axi4_to_ahb.scala 203:20] - node _T_156 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 204:37] - buf_state_en <= _T_156 @[axi4_to_ahb.scala 204:20] - buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 205:22] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 206:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 207:23] - node _T_157 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 208:41] - node _T_158 = and(buf_state_en, _T_157) @[axi4_to_ahb.scala 208:39] - slave_valid_pre <= _T_158 @[axi4_to_ahb.scala 208:23] - node _T_159 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 209:34] - node _T_160 = and(buf_state_en, _T_159) @[axi4_to_ahb.scala 209:32] - cmd_done <= _T_160 @[axi4_to_ahb.scala 209:16] - node _T_161 = and(master_ready, master_valid) @[axi4_to_ahb.scala 210:33] - node _T_162 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 210:64] - node _T_163 = and(_T_161, _T_162) @[axi4_to_ahb.scala 210:48] - node _T_164 = and(_T_163, buf_state_en) @[axi4_to_ahb.scala 210:79] - bypass_en <= _T_164 @[axi4_to_ahb.scala 210:17] - node _T_165 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 211:47] - node _T_166 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 211:62] - node _T_167 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 211:78] - node _T_168 = mux(_T_165, _T_166, _T_167) @[axi4_to_ahb.scala 211:30] - buf_cmd_byte_ptr <= _T_168 @[axi4_to_ahb.scala 211:24] - node _T_169 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 212:63] - node _T_170 = and(_T_169, buf_state_en) @[axi4_to_ahb.scala 212:78] - node _T_171 = eq(_T_170, UInt<1>("h00")) @[axi4_to_ahb.scala 212:47] + node _T_137 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 194:39] + node _T_138 = and(ahb_hready_q, _T_137) @[axi4_to_ahb.scala 194:37] + node _T_139 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 194:82] + node _T_140 = eq(_T_139, UInt<1>("h01")) @[axi4_to_ahb.scala 194:89] + node _T_141 = and(master_valid, _T_140) @[axi4_to_ahb.scala 194:70] + node _T_142 = not(_T_141) @[axi4_to_ahb.scala 194:55] + node _T_143 = and(_T_138, _T_142) @[axi4_to_ahb.scala 194:53] + master_ready <= _T_143 @[axi4_to_ahb.scala 194:20] + node _T_144 = and(master_valid, master_ready) @[axi4_to_ahb.scala 195:34] + node _T_145 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 195:62] + node _T_146 = eq(_T_145, UInt<1>("h00")) @[axi4_to_ahb.scala 195:69] + node _T_147 = and(_T_144, _T_146) @[axi4_to_ahb.scala 195:49] + buf_wr_en <= _T_147 @[axi4_to_ahb.scala 195:17] + node _T_148 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 196:45] + node _T_149 = and(master_valid, master_ready) @[axi4_to_ahb.scala 196:82] + node _T_150 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 196:110] + node _T_151 = eq(_T_150, UInt<1>("h00")) @[axi4_to_ahb.scala 196:117] + node _T_152 = and(_T_149, _T_151) @[axi4_to_ahb.scala 196:97] + node _T_153 = bits(_T_152, 0, 0) @[axi4_to_ahb.scala 196:138] + node _T_154 = mux(_T_153, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 196:67] + node _T_155 = mux(_T_148, UInt<3>("h07"), _T_154) @[axi4_to_ahb.scala 196:26] + buf_nxtstate <= _T_155 @[axi4_to_ahb.scala 196:20] + node _T_156 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 197:37] + buf_state_en <= _T_156 @[axi4_to_ahb.scala 197:20] + buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 198:22] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 199:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 200:23] + node _T_157 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 201:41] + node _T_158 = and(buf_state_en, _T_157) @[axi4_to_ahb.scala 201:39] + slave_valid_pre <= _T_158 @[axi4_to_ahb.scala 201:23] + node _T_159 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 202:34] + node _T_160 = and(buf_state_en, _T_159) @[axi4_to_ahb.scala 202:32] + cmd_done <= _T_160 @[axi4_to_ahb.scala 202:16] + node _T_161 = and(master_ready, master_valid) @[axi4_to_ahb.scala 203:33] + node _T_162 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 203:64] + node _T_163 = and(_T_161, _T_162) @[axi4_to_ahb.scala 203:48] + node _T_164 = and(_T_163, buf_state_en) @[axi4_to_ahb.scala 203:79] + bypass_en <= _T_164 @[axi4_to_ahb.scala 203:17] + node _T_165 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 204:47] + node _T_166 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 204:62] + node _T_167 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 204:78] + node _T_168 = mux(_T_165, _T_166, _T_167) @[axi4_to_ahb.scala 204:30] + buf_cmd_byte_ptr <= _T_168 @[axi4_to_ahb.scala 204:24] + node _T_169 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 205:63] + node _T_170 = and(_T_169, buf_state_en) @[axi4_to_ahb.scala 205:78] + node _T_171 = eq(_T_170, UInt<1>("h00")) @[axi4_to_ahb.scala 205:47] node _T_172 = bits(_T_171, 0, 0) @[Bitwise.scala 72:15] node _T_173 = mux(_T_172, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_174 = and(UInt<2>("h02"), _T_173) @[axi4_to_ahb.scala 212:36] - io.ahb.out.htrans <= _T_174 @[axi4_to_ahb.scala 212:25] - slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 213:20] + node _T_174 = and(UInt<2>("h02"), _T_173) @[axi4_to_ahb.scala 205:36] + io.ahb.out.htrans <= _T_174 @[axi4_to_ahb.scala 205:25] + slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 206:20] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_175 = eq(UInt<3>("h07"), buf_state) @[Conditional.scala 37:30] when _T_175 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 217:20] - node _T_176 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 218:51] - node _T_177 = neq(_T_176, UInt<1>("h00")) @[axi4_to_ahb.scala 218:58] - node _T_178 = and(ahb_hready_q, _T_177) @[axi4_to_ahb.scala 218:36] - node _T_179 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 218:72] - node _T_180 = and(_T_178, _T_179) @[axi4_to_ahb.scala 218:70] - buf_state_en <= _T_180 @[axi4_to_ahb.scala 218:20] - slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 219:23] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 220:20] - node _T_181 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 221:35] - buf_cmd_byte_ptr <= _T_181 @[axi4_to_ahb.scala 221:24] - node _T_182 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 222:51] + buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 210:20] + node _T_176 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 211:51] + node _T_177 = neq(_T_176, UInt<1>("h00")) @[axi4_to_ahb.scala 211:58] + node _T_178 = and(ahb_hready_q, _T_177) @[axi4_to_ahb.scala 211:36] + node _T_179 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 211:72] + node _T_180 = and(_T_178, _T_179) @[axi4_to_ahb.scala 211:70] + buf_state_en <= _T_180 @[axi4_to_ahb.scala 211:20] + slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 212:23] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 213:20] + node _T_181 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 214:35] + buf_cmd_byte_ptr <= _T_181 @[axi4_to_ahb.scala 214:24] + node _T_182 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 215:51] node _T_183 = bits(_T_182, 0, 0) @[Bitwise.scala 72:15] node _T_184 = mux(_T_183, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_185 = and(UInt<2>("h02"), _T_184) @[axi4_to_ahb.scala 222:41] - io.ahb.out.htrans <= _T_185 @[axi4_to_ahb.scala 222:25] + node _T_185 = and(UInt<2>("h02"), _T_184) @[axi4_to_ahb.scala 215:41] + io.ahb.out.htrans <= _T_185 @[axi4_to_ahb.scala 215:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_186 = eq(UInt<3>("h03"), buf_state) @[Conditional.scala 37:30] when _T_186 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 226:20] - node _T_187 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 227:37] - buf_state_en <= _T_187 @[axi4_to_ahb.scala 227:20] - buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 228:22] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 229:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 230:23] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 231:20] + buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 219:20] + node _T_187 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 220:37] + buf_state_en <= _T_187 @[axi4_to_ahb.scala 220:20] + buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 221:22] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 222:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 223:23] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 224:20] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_188 = eq(UInt<3>("h02"), buf_state) @[Conditional.scala 37:30] when _T_188 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 235:20] - node _T_189 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 236:33] - node _T_190 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 236:63] - node _T_191 = neq(_T_190, UInt<1>("h00")) @[axi4_to_ahb.scala 236:70] - node _T_192 = and(_T_189, _T_191) @[axi4_to_ahb.scala 236:48] - trxn_done <= _T_192 @[axi4_to_ahb.scala 236:17] - buf_state_en <= trxn_done @[axi4_to_ahb.scala 237:20] - buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 238:27] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 239:20] - node _T_193 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 240:47] - node _T_194 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 240:85] - node _T_195 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 240:103] - node _T_196 = add(_T_194, UInt<1>("h01")) @[axi4_to_ahb.scala 142:52] - node _T_197 = tail(_T_196, 1) @[axi4_to_ahb.scala 142:52] - node _T_198 = mux(UInt<1>("h01"), _T_197, _T_194) @[axi4_to_ahb.scala 142:24] - node _T_199 = bits(_T_195, 0, 0) @[axi4_to_ahb.scala 143:44] - node _T_200 = geq(UInt<1>("h00"), _T_198) @[axi4_to_ahb.scala 143:62] - node _T_201 = and(_T_199, _T_200) @[axi4_to_ahb.scala 143:48] - node _T_202 = bits(_T_195, 1, 1) @[axi4_to_ahb.scala 143:44] - node _T_203 = geq(UInt<1>("h01"), _T_198) @[axi4_to_ahb.scala 143:62] - node _T_204 = and(_T_202, _T_203) @[axi4_to_ahb.scala 143:48] - node _T_205 = bits(_T_195, 2, 2) @[axi4_to_ahb.scala 143:44] - node _T_206 = geq(UInt<2>("h02"), _T_198) @[axi4_to_ahb.scala 143:62] - node _T_207 = and(_T_205, _T_206) @[axi4_to_ahb.scala 143:48] - node _T_208 = bits(_T_195, 3, 3) @[axi4_to_ahb.scala 143:44] - node _T_209 = geq(UInt<2>("h03"), _T_198) @[axi4_to_ahb.scala 143:62] - node _T_210 = and(_T_208, _T_209) @[axi4_to_ahb.scala 143:48] - node _T_211 = bits(_T_195, 4, 4) @[axi4_to_ahb.scala 143:44] - node _T_212 = geq(UInt<3>("h04"), _T_198) @[axi4_to_ahb.scala 143:62] - node _T_213 = and(_T_211, _T_212) @[axi4_to_ahb.scala 143:48] - node _T_214 = bits(_T_195, 5, 5) @[axi4_to_ahb.scala 143:44] - node _T_215 = geq(UInt<3>("h05"), _T_198) @[axi4_to_ahb.scala 143:62] - node _T_216 = and(_T_214, _T_215) @[axi4_to_ahb.scala 143:48] - node _T_217 = bits(_T_195, 6, 6) @[axi4_to_ahb.scala 143:44] - node _T_218 = geq(UInt<3>("h06"), _T_198) @[axi4_to_ahb.scala 143:62] - node _T_219 = and(_T_217, _T_218) @[axi4_to_ahb.scala 143:48] - node _T_220 = bits(_T_195, 7, 7) @[axi4_to_ahb.scala 143:44] - node _T_221 = geq(UInt<3>("h07"), _T_198) @[axi4_to_ahb.scala 143:62] - node _T_222 = and(_T_220, _T_221) @[axi4_to_ahb.scala 143:48] + buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 228:20] + node _T_189 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 229:33] + node _T_190 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 229:63] + node _T_191 = neq(_T_190, UInt<1>("h00")) @[axi4_to_ahb.scala 229:70] + node _T_192 = and(_T_189, _T_191) @[axi4_to_ahb.scala 229:48] + trxn_done <= _T_192 @[axi4_to_ahb.scala 229:17] + buf_state_en <= trxn_done @[axi4_to_ahb.scala 230:20] + buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 231:27] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 232:20] + node _T_193 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 233:47] + node _T_194 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 233:85] + node _T_195 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 233:103] + node _T_196 = add(_T_194, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] + node _T_197 = tail(_T_196, 1) @[axi4_to_ahb.scala 135:52] + node _T_198 = mux(UInt<1>("h01"), _T_197, _T_194) @[axi4_to_ahb.scala 135:24] + node _T_199 = bits(_T_195, 0, 0) @[axi4_to_ahb.scala 136:44] + node _T_200 = geq(UInt<1>("h00"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_201 = and(_T_199, _T_200) @[axi4_to_ahb.scala 136:48] + node _T_202 = bits(_T_195, 1, 1) @[axi4_to_ahb.scala 136:44] + node _T_203 = geq(UInt<1>("h01"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_204 = and(_T_202, _T_203) @[axi4_to_ahb.scala 136:48] + node _T_205 = bits(_T_195, 2, 2) @[axi4_to_ahb.scala 136:44] + node _T_206 = geq(UInt<2>("h02"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_207 = and(_T_205, _T_206) @[axi4_to_ahb.scala 136:48] + node _T_208 = bits(_T_195, 3, 3) @[axi4_to_ahb.scala 136:44] + node _T_209 = geq(UInt<2>("h03"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_210 = and(_T_208, _T_209) @[axi4_to_ahb.scala 136:48] + node _T_211 = bits(_T_195, 4, 4) @[axi4_to_ahb.scala 136:44] + node _T_212 = geq(UInt<3>("h04"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_213 = and(_T_211, _T_212) @[axi4_to_ahb.scala 136:48] + node _T_214 = bits(_T_195, 5, 5) @[axi4_to_ahb.scala 136:44] + node _T_215 = geq(UInt<3>("h05"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_216 = and(_T_214, _T_215) @[axi4_to_ahb.scala 136:48] + node _T_217 = bits(_T_195, 6, 6) @[axi4_to_ahb.scala 136:44] + node _T_218 = geq(UInt<3>("h06"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_219 = and(_T_217, _T_218) @[axi4_to_ahb.scala 136:48] + node _T_220 = bits(_T_195, 7, 7) @[axi4_to_ahb.scala 136:44] + node _T_221 = geq(UInt<3>("h07"), _T_198) @[axi4_to_ahb.scala 136:62] + node _T_222 = and(_T_220, _T_221) @[axi4_to_ahb.scala 136:48] node _T_223 = mux(_T_222, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_224 = mux(_T_219, UInt<3>("h06"), _T_223) @[Mux.scala 98:16] node _T_225 = mux(_T_216, UInt<3>("h05"), _T_224) @[Mux.scala 98:16] @@ -112599,39 +112589,39 @@ circuit quasar_wrapper : node _T_228 = mux(_T_207, UInt<2>("h02"), _T_227) @[Mux.scala 98:16] node _T_229 = mux(_T_204, UInt<1>("h01"), _T_228) @[Mux.scala 98:16] node _T_230 = mux(_T_201, UInt<1>("h00"), _T_229) @[Mux.scala 98:16] - node _T_231 = mux(_T_193, _T_230, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 240:30] - buf_cmd_byte_ptr <= _T_231 @[axi4_to_ahb.scala 240:24] - node _T_232 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 241:65] - node _T_233 = or(buf_aligned, _T_232) @[axi4_to_ahb.scala 241:44] - node _T_234 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 241:127] - node _T_235 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 241:145] - node _T_236 = add(_T_234, UInt<1>("h01")) @[axi4_to_ahb.scala 142:52] - node _T_237 = tail(_T_236, 1) @[axi4_to_ahb.scala 142:52] - node _T_238 = mux(UInt<1>("h01"), _T_237, _T_234) @[axi4_to_ahb.scala 142:24] - node _T_239 = bits(_T_235, 0, 0) @[axi4_to_ahb.scala 143:44] - node _T_240 = geq(UInt<1>("h00"), _T_238) @[axi4_to_ahb.scala 143:62] - node _T_241 = and(_T_239, _T_240) @[axi4_to_ahb.scala 143:48] - node _T_242 = bits(_T_235, 1, 1) @[axi4_to_ahb.scala 143:44] - node _T_243 = geq(UInt<1>("h01"), _T_238) @[axi4_to_ahb.scala 143:62] - node _T_244 = and(_T_242, _T_243) @[axi4_to_ahb.scala 143:48] - node _T_245 = bits(_T_235, 2, 2) @[axi4_to_ahb.scala 143:44] - node _T_246 = geq(UInt<2>("h02"), _T_238) @[axi4_to_ahb.scala 143:62] - node _T_247 = and(_T_245, _T_246) @[axi4_to_ahb.scala 143:48] - node _T_248 = bits(_T_235, 3, 3) @[axi4_to_ahb.scala 143:44] - node _T_249 = geq(UInt<2>("h03"), _T_238) @[axi4_to_ahb.scala 143:62] - node _T_250 = and(_T_248, _T_249) @[axi4_to_ahb.scala 143:48] - node _T_251 = bits(_T_235, 4, 4) @[axi4_to_ahb.scala 143:44] - node _T_252 = geq(UInt<3>("h04"), _T_238) @[axi4_to_ahb.scala 143:62] - node _T_253 = and(_T_251, _T_252) @[axi4_to_ahb.scala 143:48] - node _T_254 = bits(_T_235, 5, 5) @[axi4_to_ahb.scala 143:44] - node _T_255 = geq(UInt<3>("h05"), _T_238) @[axi4_to_ahb.scala 143:62] - node _T_256 = and(_T_254, _T_255) @[axi4_to_ahb.scala 143:48] - node _T_257 = bits(_T_235, 6, 6) @[axi4_to_ahb.scala 143:44] - node _T_258 = geq(UInt<3>("h06"), _T_238) @[axi4_to_ahb.scala 143:62] - node _T_259 = and(_T_257, _T_258) @[axi4_to_ahb.scala 143:48] - node _T_260 = bits(_T_235, 7, 7) @[axi4_to_ahb.scala 143:44] - node _T_261 = geq(UInt<3>("h07"), _T_238) @[axi4_to_ahb.scala 143:62] - node _T_262 = and(_T_260, _T_261) @[axi4_to_ahb.scala 143:48] + node _T_231 = mux(_T_193, _T_230, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 233:30] + buf_cmd_byte_ptr <= _T_231 @[axi4_to_ahb.scala 233:24] + node _T_232 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 234:65] + node _T_233 = or(buf_aligned, _T_232) @[axi4_to_ahb.scala 234:44] + node _T_234 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 234:127] + node _T_235 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 234:145] + node _T_236 = add(_T_234, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] + node _T_237 = tail(_T_236, 1) @[axi4_to_ahb.scala 135:52] + node _T_238 = mux(UInt<1>("h01"), _T_237, _T_234) @[axi4_to_ahb.scala 135:24] + node _T_239 = bits(_T_235, 0, 0) @[axi4_to_ahb.scala 136:44] + node _T_240 = geq(UInt<1>("h00"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_241 = and(_T_239, _T_240) @[axi4_to_ahb.scala 136:48] + node _T_242 = bits(_T_235, 1, 1) @[axi4_to_ahb.scala 136:44] + node _T_243 = geq(UInt<1>("h01"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_244 = and(_T_242, _T_243) @[axi4_to_ahb.scala 136:48] + node _T_245 = bits(_T_235, 2, 2) @[axi4_to_ahb.scala 136:44] + node _T_246 = geq(UInt<2>("h02"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_247 = and(_T_245, _T_246) @[axi4_to_ahb.scala 136:48] + node _T_248 = bits(_T_235, 3, 3) @[axi4_to_ahb.scala 136:44] + node _T_249 = geq(UInt<2>("h03"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_250 = and(_T_248, _T_249) @[axi4_to_ahb.scala 136:48] + node _T_251 = bits(_T_235, 4, 4) @[axi4_to_ahb.scala 136:44] + node _T_252 = geq(UInt<3>("h04"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_253 = and(_T_251, _T_252) @[axi4_to_ahb.scala 136:48] + node _T_254 = bits(_T_235, 5, 5) @[axi4_to_ahb.scala 136:44] + node _T_255 = geq(UInt<3>("h05"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_256 = and(_T_254, _T_255) @[axi4_to_ahb.scala 136:48] + node _T_257 = bits(_T_235, 6, 6) @[axi4_to_ahb.scala 136:44] + node _T_258 = geq(UInt<3>("h06"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_259 = and(_T_257, _T_258) @[axi4_to_ahb.scala 136:48] + node _T_260 = bits(_T_235, 7, 7) @[axi4_to_ahb.scala 136:44] + node _T_261 = geq(UInt<3>("h07"), _T_238) @[axi4_to_ahb.scala 136:62] + node _T_262 = and(_T_260, _T_261) @[axi4_to_ahb.scala 136:48] node _T_263 = mux(_T_262, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_264 = mux(_T_259, UInt<3>("h06"), _T_263) @[Mux.scala 98:16] node _T_265 = mux(_T_256, UInt<3>("h05"), _T_264) @[Mux.scala 98:16] @@ -112640,83 +112630,83 @@ circuit quasar_wrapper : node _T_268 = mux(_T_247, UInt<2>("h02"), _T_267) @[Mux.scala 98:16] node _T_269 = mux(_T_244, UInt<1>("h01"), _T_268) @[Mux.scala 98:16] node _T_270 = mux(_T_241, UInt<1>("h00"), _T_269) @[Mux.scala 98:16] - node _T_271 = dshr(buf_byteen, _T_270) @[axi4_to_ahb.scala 241:92] - node _T_272 = bits(_T_271, 0, 0) @[axi4_to_ahb.scala 241:92] - node _T_273 = eq(_T_272, UInt<1>("h00")) @[axi4_to_ahb.scala 241:163] - node _T_274 = or(_T_233, _T_273) @[axi4_to_ahb.scala 241:79] - node _T_275 = and(trxn_done, _T_274) @[axi4_to_ahb.scala 241:29] - cmd_done <= _T_275 @[axi4_to_ahb.scala 241:16] - node _T_276 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 242:47] - node _T_277 = eq(_T_276, UInt<1>("h00")) @[axi4_to_ahb.scala 242:36] + node _T_271 = dshr(buf_byteen, _T_270) @[axi4_to_ahb.scala 234:92] + node _T_272 = bits(_T_271, 0, 0) @[axi4_to_ahb.scala 234:92] + node _T_273 = eq(_T_272, UInt<1>("h00")) @[axi4_to_ahb.scala 234:163] + node _T_274 = or(_T_233, _T_273) @[axi4_to_ahb.scala 234:79] + node _T_275 = and(trxn_done, _T_274) @[axi4_to_ahb.scala 234:29] + cmd_done <= _T_275 @[axi4_to_ahb.scala 234:16] + node _T_276 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 235:47] + node _T_277 = eq(_T_276, UInt<1>("h00")) @[axi4_to_ahb.scala 235:36] node _T_278 = bits(_T_277, 0, 0) @[Bitwise.scala 72:15] node _T_279 = mux(_T_278, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_280 = and(_T_279, UInt<2>("h02")) @[axi4_to_ahb.scala 242:61] - io.ahb.out.htrans <= _T_280 @[axi4_to_ahb.scala 242:25] + node _T_280 = and(_T_279, UInt<2>("h02")) @[axi4_to_ahb.scala 235:61] + io.ahb.out.htrans <= _T_280 @[axi4_to_ahb.scala 235:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_281 = eq(UInt<3>("h04"), buf_state) @[Conditional.scala 37:30] when _T_281 : @[Conditional.scala 39:67] - node _T_282 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 246:34] - node _T_283 = or(_T_282, ahb_hresp_q) @[axi4_to_ahb.scala 246:50] - buf_state_en <= _T_283 @[axi4_to_ahb.scala 246:20] - node _T_284 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 247:38] - node _T_285 = and(buf_state_en, _T_284) @[axi4_to_ahb.scala 247:36] - node _T_286 = and(_T_285, slave_ready) @[axi4_to_ahb.scala 247:51] - master_ready <= _T_286 @[axi4_to_ahb.scala 247:20] - node _T_287 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 248:42] - node _T_288 = or(ahb_hresp_q, _T_287) @[axi4_to_ahb.scala 248:40] - node _T_289 = and(master_valid, master_valid) @[axi4_to_ahb.scala 248:80] - node _T_290 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 248:111] - node _T_291 = eq(_T_290, UInt<1>("h01")) @[axi4_to_ahb.scala 248:117] - node _T_292 = bits(_T_291, 0, 0) @[axi4_to_ahb.scala 248:132] - node _T_293 = mux(_T_292, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 248:99] - node _T_294 = mux(_T_289, _T_293, UInt<3>("h00")) @[axi4_to_ahb.scala 248:65] - node _T_295 = mux(_T_288, UInt<3>("h05"), _T_294) @[axi4_to_ahb.scala 248:26] - buf_nxtstate <= _T_295 @[axi4_to_ahb.scala 248:20] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 249:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 250:23] - node _T_296 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 251:33] - node _T_297 = eq(_T_296, UInt<1>("h01")) @[axi4_to_ahb.scala 251:39] - buf_write_in <= _T_297 @[axi4_to_ahb.scala 251:20] - node _T_298 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 252:50] - node _T_299 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 252:78] - node _T_300 = or(_T_298, _T_299) @[axi4_to_ahb.scala 252:62] - node _T_301 = and(buf_state_en, _T_300) @[axi4_to_ahb.scala 252:33] - buf_wr_en <= _T_301 @[axi4_to_ahb.scala 252:17] - buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 253:22] - node _T_302 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 254:65] - node _T_303 = neq(_T_302, UInt<1>("h00")) @[axi4_to_ahb.scala 254:71] - node _T_304 = and(ahb_hready_q, _T_303) @[axi4_to_ahb.scala 254:50] - node _T_305 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 255:29] - node _T_306 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 255:85] - node _T_307 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 255:101] - node _T_308 = add(_T_306, UInt<1>("h01")) @[axi4_to_ahb.scala 142:52] - node _T_309 = tail(_T_308, 1) @[axi4_to_ahb.scala 142:52] - node _T_310 = mux(UInt<1>("h01"), _T_309, _T_306) @[axi4_to_ahb.scala 142:24] - node _T_311 = bits(_T_307, 0, 0) @[axi4_to_ahb.scala 143:44] - node _T_312 = geq(UInt<1>("h00"), _T_310) @[axi4_to_ahb.scala 143:62] - node _T_313 = and(_T_311, _T_312) @[axi4_to_ahb.scala 143:48] - node _T_314 = bits(_T_307, 1, 1) @[axi4_to_ahb.scala 143:44] - node _T_315 = geq(UInt<1>("h01"), _T_310) @[axi4_to_ahb.scala 143:62] - node _T_316 = and(_T_314, _T_315) @[axi4_to_ahb.scala 143:48] - node _T_317 = bits(_T_307, 2, 2) @[axi4_to_ahb.scala 143:44] - node _T_318 = geq(UInt<2>("h02"), _T_310) @[axi4_to_ahb.scala 143:62] - node _T_319 = and(_T_317, _T_318) @[axi4_to_ahb.scala 143:48] - node _T_320 = bits(_T_307, 3, 3) @[axi4_to_ahb.scala 143:44] - node _T_321 = geq(UInt<2>("h03"), _T_310) @[axi4_to_ahb.scala 143:62] - node _T_322 = and(_T_320, _T_321) @[axi4_to_ahb.scala 143:48] - node _T_323 = bits(_T_307, 4, 4) @[axi4_to_ahb.scala 143:44] - node _T_324 = geq(UInt<3>("h04"), _T_310) @[axi4_to_ahb.scala 143:62] - node _T_325 = and(_T_323, _T_324) @[axi4_to_ahb.scala 143:48] - node _T_326 = bits(_T_307, 5, 5) @[axi4_to_ahb.scala 143:44] - node _T_327 = geq(UInt<3>("h05"), _T_310) @[axi4_to_ahb.scala 143:62] - node _T_328 = and(_T_326, _T_327) @[axi4_to_ahb.scala 143:48] - node _T_329 = bits(_T_307, 6, 6) @[axi4_to_ahb.scala 143:44] - node _T_330 = geq(UInt<3>("h06"), _T_310) @[axi4_to_ahb.scala 143:62] - node _T_331 = and(_T_329, _T_330) @[axi4_to_ahb.scala 143:48] - node _T_332 = bits(_T_307, 7, 7) @[axi4_to_ahb.scala 143:44] - node _T_333 = geq(UInt<3>("h07"), _T_310) @[axi4_to_ahb.scala 143:62] - node _T_334 = and(_T_332, _T_333) @[axi4_to_ahb.scala 143:48] + node _T_282 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 239:34] + node _T_283 = or(_T_282, ahb_hresp_q) @[axi4_to_ahb.scala 239:50] + buf_state_en <= _T_283 @[axi4_to_ahb.scala 239:20] + node _T_284 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 240:38] + node _T_285 = and(buf_state_en, _T_284) @[axi4_to_ahb.scala 240:36] + node _T_286 = and(_T_285, slave_ready) @[axi4_to_ahb.scala 240:51] + master_ready <= _T_286 @[axi4_to_ahb.scala 240:20] + node _T_287 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 241:42] + node _T_288 = or(ahb_hresp_q, _T_287) @[axi4_to_ahb.scala 241:40] + node _T_289 = and(master_valid, master_valid) @[axi4_to_ahb.scala 241:80] + node _T_290 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 241:111] + node _T_291 = eq(_T_290, UInt<1>("h01")) @[axi4_to_ahb.scala 241:117] + node _T_292 = bits(_T_291, 0, 0) @[axi4_to_ahb.scala 241:132] + node _T_293 = mux(_T_292, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 241:99] + node _T_294 = mux(_T_289, _T_293, UInt<3>("h00")) @[axi4_to_ahb.scala 241:65] + node _T_295 = mux(_T_288, UInt<3>("h05"), _T_294) @[axi4_to_ahb.scala 241:26] + buf_nxtstate <= _T_295 @[axi4_to_ahb.scala 241:20] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 242:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 243:23] + node _T_296 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 244:33] + node _T_297 = eq(_T_296, UInt<1>("h01")) @[axi4_to_ahb.scala 244:39] + buf_write_in <= _T_297 @[axi4_to_ahb.scala 244:20] + node _T_298 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 245:50] + node _T_299 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 245:78] + node _T_300 = or(_T_298, _T_299) @[axi4_to_ahb.scala 245:62] + node _T_301 = and(buf_state_en, _T_300) @[axi4_to_ahb.scala 245:33] + buf_wr_en <= _T_301 @[axi4_to_ahb.scala 245:17] + buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 246:22] + node _T_302 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 247:65] + node _T_303 = neq(_T_302, UInt<1>("h00")) @[axi4_to_ahb.scala 247:71] + node _T_304 = and(ahb_hready_q, _T_303) @[axi4_to_ahb.scala 247:50] + node _T_305 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 248:29] + node _T_306 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 248:85] + node _T_307 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 248:101] + node _T_308 = add(_T_306, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] + node _T_309 = tail(_T_308, 1) @[axi4_to_ahb.scala 135:52] + node _T_310 = mux(UInt<1>("h01"), _T_309, _T_306) @[axi4_to_ahb.scala 135:24] + node _T_311 = bits(_T_307, 0, 0) @[axi4_to_ahb.scala 136:44] + node _T_312 = geq(UInt<1>("h00"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_313 = and(_T_311, _T_312) @[axi4_to_ahb.scala 136:48] + node _T_314 = bits(_T_307, 1, 1) @[axi4_to_ahb.scala 136:44] + node _T_315 = geq(UInt<1>("h01"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_316 = and(_T_314, _T_315) @[axi4_to_ahb.scala 136:48] + node _T_317 = bits(_T_307, 2, 2) @[axi4_to_ahb.scala 136:44] + node _T_318 = geq(UInt<2>("h02"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_319 = and(_T_317, _T_318) @[axi4_to_ahb.scala 136:48] + node _T_320 = bits(_T_307, 3, 3) @[axi4_to_ahb.scala 136:44] + node _T_321 = geq(UInt<2>("h03"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_322 = and(_T_320, _T_321) @[axi4_to_ahb.scala 136:48] + node _T_323 = bits(_T_307, 4, 4) @[axi4_to_ahb.scala 136:44] + node _T_324 = geq(UInt<3>("h04"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_325 = and(_T_323, _T_324) @[axi4_to_ahb.scala 136:48] + node _T_326 = bits(_T_307, 5, 5) @[axi4_to_ahb.scala 136:44] + node _T_327 = geq(UInt<3>("h05"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_328 = and(_T_326, _T_327) @[axi4_to_ahb.scala 136:48] + node _T_329 = bits(_T_307, 6, 6) @[axi4_to_ahb.scala 136:44] + node _T_330 = geq(UInt<3>("h06"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_331 = and(_T_329, _T_330) @[axi4_to_ahb.scala 136:48] + node _T_332 = bits(_T_307, 7, 7) @[axi4_to_ahb.scala 136:44] + node _T_333 = geq(UInt<3>("h07"), _T_310) @[axi4_to_ahb.scala 136:62] + node _T_334 = and(_T_332, _T_333) @[axi4_to_ahb.scala 136:48] node _T_335 = mux(_T_334, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_336 = mux(_T_331, UInt<3>("h06"), _T_335) @[Mux.scala 98:16] node _T_337 = mux(_T_328, UInt<3>("h05"), _T_336) @[Mux.scala 98:16] @@ -112725,62 +112715,62 @@ circuit quasar_wrapper : node _T_340 = mux(_T_319, UInt<2>("h02"), _T_339) @[Mux.scala 98:16] node _T_341 = mux(_T_316, UInt<1>("h01"), _T_340) @[Mux.scala 98:16] node _T_342 = mux(_T_313, UInt<1>("h00"), _T_341) @[Mux.scala 98:16] - node _T_343 = dshr(buf_byteen, _T_342) @[axi4_to_ahb.scala 255:51] - node _T_344 = bits(_T_343, 0, 0) @[axi4_to_ahb.scala 255:51] - node _T_345 = eq(_T_344, UInt<1>("h00")) @[axi4_to_ahb.scala 255:116] - node _T_346 = or(_T_305, _T_345) @[axi4_to_ahb.scala 255:38] - node _T_347 = and(_T_304, _T_346) @[axi4_to_ahb.scala 254:80] - node _T_348 = or(ahb_hresp_q, _T_347) @[axi4_to_ahb.scala 254:34] - cmd_done <= _T_348 @[axi4_to_ahb.scala 254:16] - node _T_349 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 256:33] - node _T_350 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 256:64] - node _T_351 = and(_T_349, _T_350) @[axi4_to_ahb.scala 256:48] - bypass_en <= _T_351 @[axi4_to_ahb.scala 256:17] - node _T_352 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 257:48] - node _T_353 = eq(_T_352, UInt<1>("h00")) @[axi4_to_ahb.scala 257:37] - node _T_354 = or(_T_353, bypass_en) @[axi4_to_ahb.scala 257:61] + node _T_343 = dshr(buf_byteen, _T_342) @[axi4_to_ahb.scala 248:51] + node _T_344 = bits(_T_343, 0, 0) @[axi4_to_ahb.scala 248:51] + node _T_345 = eq(_T_344, UInt<1>("h00")) @[axi4_to_ahb.scala 248:116] + node _T_346 = or(_T_305, _T_345) @[axi4_to_ahb.scala 248:38] + node _T_347 = and(_T_304, _T_346) @[axi4_to_ahb.scala 247:80] + node _T_348 = or(ahb_hresp_q, _T_347) @[axi4_to_ahb.scala 247:34] + cmd_done <= _T_348 @[axi4_to_ahb.scala 247:16] + node _T_349 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 249:33] + node _T_350 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 249:64] + node _T_351 = and(_T_349, _T_350) @[axi4_to_ahb.scala 249:48] + bypass_en <= _T_351 @[axi4_to_ahb.scala 249:17] + node _T_352 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 250:48] + node _T_353 = eq(_T_352, UInt<1>("h00")) @[axi4_to_ahb.scala 250:37] + node _T_354 = or(_T_353, bypass_en) @[axi4_to_ahb.scala 250:61] node _T_355 = bits(_T_354, 0, 0) @[Bitwise.scala 72:15] node _T_356 = mux(_T_355, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_357 = and(_T_356, UInt<2>("h02")) @[axi4_to_ahb.scala 257:75] - io.ahb.out.htrans <= _T_357 @[axi4_to_ahb.scala 257:25] - node _T_358 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 258:55] - node _T_359 = and(buf_state_en, _T_358) @[axi4_to_ahb.scala 258:39] - slave_valid_pre <= _T_359 @[axi4_to_ahb.scala 258:23] - node _T_360 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 259:33] - node _T_361 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 259:63] - node _T_362 = neq(_T_361, UInt<1>("h00")) @[axi4_to_ahb.scala 259:69] - node _T_363 = and(_T_360, _T_362) @[axi4_to_ahb.scala 259:48] - trxn_done <= _T_363 @[axi4_to_ahb.scala 259:17] - node _T_364 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 260:40] - buf_cmd_byte_ptr_en <= _T_364 @[axi4_to_ahb.scala 260:27] - node _T_365 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 261:79] - node _T_366 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 142:52] - node _T_367 = tail(_T_366, 1) @[axi4_to_ahb.scala 142:52] - node _T_368 = mux(UInt<1>("h00"), _T_367, UInt<3>("h00")) @[axi4_to_ahb.scala 142:24] - node _T_369 = bits(_T_365, 0, 0) @[axi4_to_ahb.scala 143:44] - node _T_370 = geq(UInt<1>("h00"), _T_368) @[axi4_to_ahb.scala 143:62] - node _T_371 = and(_T_369, _T_370) @[axi4_to_ahb.scala 143:48] - node _T_372 = bits(_T_365, 1, 1) @[axi4_to_ahb.scala 143:44] - node _T_373 = geq(UInt<1>("h01"), _T_368) @[axi4_to_ahb.scala 143:62] - node _T_374 = and(_T_372, _T_373) @[axi4_to_ahb.scala 143:48] - node _T_375 = bits(_T_365, 2, 2) @[axi4_to_ahb.scala 143:44] - node _T_376 = geq(UInt<2>("h02"), _T_368) @[axi4_to_ahb.scala 143:62] - node _T_377 = and(_T_375, _T_376) @[axi4_to_ahb.scala 143:48] - node _T_378 = bits(_T_365, 3, 3) @[axi4_to_ahb.scala 143:44] - node _T_379 = geq(UInt<2>("h03"), _T_368) @[axi4_to_ahb.scala 143:62] - node _T_380 = and(_T_378, _T_379) @[axi4_to_ahb.scala 143:48] - node _T_381 = bits(_T_365, 4, 4) @[axi4_to_ahb.scala 143:44] - node _T_382 = geq(UInt<3>("h04"), _T_368) @[axi4_to_ahb.scala 143:62] - node _T_383 = and(_T_381, _T_382) @[axi4_to_ahb.scala 143:48] - node _T_384 = bits(_T_365, 5, 5) @[axi4_to_ahb.scala 143:44] - node _T_385 = geq(UInt<3>("h05"), _T_368) @[axi4_to_ahb.scala 143:62] - node _T_386 = and(_T_384, _T_385) @[axi4_to_ahb.scala 143:48] - node _T_387 = bits(_T_365, 6, 6) @[axi4_to_ahb.scala 143:44] - node _T_388 = geq(UInt<3>("h06"), _T_368) @[axi4_to_ahb.scala 143:62] - node _T_389 = and(_T_387, _T_388) @[axi4_to_ahb.scala 143:48] - node _T_390 = bits(_T_365, 7, 7) @[axi4_to_ahb.scala 143:44] - node _T_391 = geq(UInt<3>("h07"), _T_368) @[axi4_to_ahb.scala 143:62] - node _T_392 = and(_T_390, _T_391) @[axi4_to_ahb.scala 143:48] + node _T_357 = and(_T_356, UInt<2>("h02")) @[axi4_to_ahb.scala 250:75] + io.ahb.out.htrans <= _T_357 @[axi4_to_ahb.scala 250:25] + node _T_358 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 251:55] + node _T_359 = and(buf_state_en, _T_358) @[axi4_to_ahb.scala 251:39] + slave_valid_pre <= _T_359 @[axi4_to_ahb.scala 251:23] + node _T_360 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 252:33] + node _T_361 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 252:63] + node _T_362 = neq(_T_361, UInt<1>("h00")) @[axi4_to_ahb.scala 252:69] + node _T_363 = and(_T_360, _T_362) @[axi4_to_ahb.scala 252:48] + trxn_done <= _T_363 @[axi4_to_ahb.scala 252:17] + node _T_364 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 253:40] + buf_cmd_byte_ptr_en <= _T_364 @[axi4_to_ahb.scala 253:27] + node _T_365 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 254:79] + node _T_366 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] + node _T_367 = tail(_T_366, 1) @[axi4_to_ahb.scala 135:52] + node _T_368 = mux(UInt<1>("h00"), _T_367, UInt<3>("h00")) @[axi4_to_ahb.scala 135:24] + node _T_369 = bits(_T_365, 0, 0) @[axi4_to_ahb.scala 136:44] + node _T_370 = geq(UInt<1>("h00"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_371 = and(_T_369, _T_370) @[axi4_to_ahb.scala 136:48] + node _T_372 = bits(_T_365, 1, 1) @[axi4_to_ahb.scala 136:44] + node _T_373 = geq(UInt<1>("h01"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_374 = and(_T_372, _T_373) @[axi4_to_ahb.scala 136:48] + node _T_375 = bits(_T_365, 2, 2) @[axi4_to_ahb.scala 136:44] + node _T_376 = geq(UInt<2>("h02"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_377 = and(_T_375, _T_376) @[axi4_to_ahb.scala 136:48] + node _T_378 = bits(_T_365, 3, 3) @[axi4_to_ahb.scala 136:44] + node _T_379 = geq(UInt<2>("h03"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_380 = and(_T_378, _T_379) @[axi4_to_ahb.scala 136:48] + node _T_381 = bits(_T_365, 4, 4) @[axi4_to_ahb.scala 136:44] + node _T_382 = geq(UInt<3>("h04"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_383 = and(_T_381, _T_382) @[axi4_to_ahb.scala 136:48] + node _T_384 = bits(_T_365, 5, 5) @[axi4_to_ahb.scala 136:44] + node _T_385 = geq(UInt<3>("h05"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_386 = and(_T_384, _T_385) @[axi4_to_ahb.scala 136:48] + node _T_387 = bits(_T_365, 6, 6) @[axi4_to_ahb.scala 136:44] + node _T_388 = geq(UInt<3>("h06"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_389 = and(_T_387, _T_388) @[axi4_to_ahb.scala 136:48] + node _T_390 = bits(_T_365, 7, 7) @[axi4_to_ahb.scala 136:44] + node _T_391 = geq(UInt<3>("h07"), _T_368) @[axi4_to_ahb.scala 136:62] + node _T_392 = and(_T_390, _T_391) @[axi4_to_ahb.scala 136:48] node _T_393 = mux(_T_392, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_394 = mux(_T_389, UInt<3>("h06"), _T_393) @[Mux.scala 98:16] node _T_395 = mux(_T_386, UInt<3>("h05"), _T_394) @[Mux.scala 98:16] @@ -112789,35 +112779,35 @@ circuit quasar_wrapper : node _T_398 = mux(_T_377, UInt<2>("h02"), _T_397) @[Mux.scala 98:16] node _T_399 = mux(_T_374, UInt<1>("h01"), _T_398) @[Mux.scala 98:16] node _T_400 = mux(_T_371, UInt<1>("h00"), _T_399) @[Mux.scala 98:16] - node _T_401 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 261:141] - node _T_402 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 261:157] - node _T_403 = add(_T_401, UInt<1>("h01")) @[axi4_to_ahb.scala 142:52] - node _T_404 = tail(_T_403, 1) @[axi4_to_ahb.scala 142:52] - node _T_405 = mux(UInt<1>("h01"), _T_404, _T_401) @[axi4_to_ahb.scala 142:24] - node _T_406 = bits(_T_402, 0, 0) @[axi4_to_ahb.scala 143:44] - node _T_407 = geq(UInt<1>("h00"), _T_405) @[axi4_to_ahb.scala 143:62] - node _T_408 = and(_T_406, _T_407) @[axi4_to_ahb.scala 143:48] - node _T_409 = bits(_T_402, 1, 1) @[axi4_to_ahb.scala 143:44] - node _T_410 = geq(UInt<1>("h01"), _T_405) @[axi4_to_ahb.scala 143:62] - node _T_411 = and(_T_409, _T_410) @[axi4_to_ahb.scala 143:48] - node _T_412 = bits(_T_402, 2, 2) @[axi4_to_ahb.scala 143:44] - node _T_413 = geq(UInt<2>("h02"), _T_405) @[axi4_to_ahb.scala 143:62] - node _T_414 = and(_T_412, _T_413) @[axi4_to_ahb.scala 143:48] - node _T_415 = bits(_T_402, 3, 3) @[axi4_to_ahb.scala 143:44] - node _T_416 = geq(UInt<2>("h03"), _T_405) @[axi4_to_ahb.scala 143:62] - node _T_417 = and(_T_415, _T_416) @[axi4_to_ahb.scala 143:48] - node _T_418 = bits(_T_402, 4, 4) @[axi4_to_ahb.scala 143:44] - node _T_419 = geq(UInt<3>("h04"), _T_405) @[axi4_to_ahb.scala 143:62] - node _T_420 = and(_T_418, _T_419) @[axi4_to_ahb.scala 143:48] - node _T_421 = bits(_T_402, 5, 5) @[axi4_to_ahb.scala 143:44] - node _T_422 = geq(UInt<3>("h05"), _T_405) @[axi4_to_ahb.scala 143:62] - node _T_423 = and(_T_421, _T_422) @[axi4_to_ahb.scala 143:48] - node _T_424 = bits(_T_402, 6, 6) @[axi4_to_ahb.scala 143:44] - node _T_425 = geq(UInt<3>("h06"), _T_405) @[axi4_to_ahb.scala 143:62] - node _T_426 = and(_T_424, _T_425) @[axi4_to_ahb.scala 143:48] - node _T_427 = bits(_T_402, 7, 7) @[axi4_to_ahb.scala 143:44] - node _T_428 = geq(UInt<3>("h07"), _T_405) @[axi4_to_ahb.scala 143:62] - node _T_429 = and(_T_427, _T_428) @[axi4_to_ahb.scala 143:48] + node _T_401 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 254:141] + node _T_402 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 254:157] + node _T_403 = add(_T_401, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] + node _T_404 = tail(_T_403, 1) @[axi4_to_ahb.scala 135:52] + node _T_405 = mux(UInt<1>("h01"), _T_404, _T_401) @[axi4_to_ahb.scala 135:24] + node _T_406 = bits(_T_402, 0, 0) @[axi4_to_ahb.scala 136:44] + node _T_407 = geq(UInt<1>("h00"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_408 = and(_T_406, _T_407) @[axi4_to_ahb.scala 136:48] + node _T_409 = bits(_T_402, 1, 1) @[axi4_to_ahb.scala 136:44] + node _T_410 = geq(UInt<1>("h01"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_411 = and(_T_409, _T_410) @[axi4_to_ahb.scala 136:48] + node _T_412 = bits(_T_402, 2, 2) @[axi4_to_ahb.scala 136:44] + node _T_413 = geq(UInt<2>("h02"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_414 = and(_T_412, _T_413) @[axi4_to_ahb.scala 136:48] + node _T_415 = bits(_T_402, 3, 3) @[axi4_to_ahb.scala 136:44] + node _T_416 = geq(UInt<2>("h03"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_417 = and(_T_415, _T_416) @[axi4_to_ahb.scala 136:48] + node _T_418 = bits(_T_402, 4, 4) @[axi4_to_ahb.scala 136:44] + node _T_419 = geq(UInt<3>("h04"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_420 = and(_T_418, _T_419) @[axi4_to_ahb.scala 136:48] + node _T_421 = bits(_T_402, 5, 5) @[axi4_to_ahb.scala 136:44] + node _T_422 = geq(UInt<3>("h05"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_423 = and(_T_421, _T_422) @[axi4_to_ahb.scala 136:48] + node _T_424 = bits(_T_402, 6, 6) @[axi4_to_ahb.scala 136:44] + node _T_425 = geq(UInt<3>("h06"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_426 = and(_T_424, _T_425) @[axi4_to_ahb.scala 136:48] + node _T_427 = bits(_T_402, 7, 7) @[axi4_to_ahb.scala 136:44] + node _T_428 = geq(UInt<3>("h07"), _T_405) @[axi4_to_ahb.scala 136:62] + node _T_429 = and(_T_427, _T_428) @[axi4_to_ahb.scala 136:48] node _T_430 = mux(_T_429, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_431 = mux(_T_426, UInt<3>("h06"), _T_430) @[Mux.scala 98:16] node _T_432 = mux(_T_423, UInt<3>("h05"), _T_431) @[Mux.scala 98:16] @@ -112826,268 +112816,268 @@ circuit quasar_wrapper : node _T_435 = mux(_T_414, UInt<2>("h02"), _T_434) @[Mux.scala 98:16] node _T_436 = mux(_T_411, UInt<1>("h01"), _T_435) @[Mux.scala 98:16] node _T_437 = mux(_T_408, UInt<1>("h00"), _T_436) @[Mux.scala 98:16] - node _T_438 = mux(trxn_done, _T_437, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 261:97] - node _T_439 = mux(bypass_en, _T_400, _T_438) @[axi4_to_ahb.scala 261:30] - buf_cmd_byte_ptr <= _T_439 @[axi4_to_ahb.scala 261:24] + node _T_438 = mux(trxn_done, _T_437, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 254:97] + node _T_439 = mux(bypass_en, _T_400, _T_438) @[axi4_to_ahb.scala 254:30] + buf_cmd_byte_ptr <= _T_439 @[axi4_to_ahb.scala 254:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_440 = eq(UInt<3>("h05"), buf_state) @[Conditional.scala 37:30] when _T_440 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 264:20] - buf_state_en <= slave_ready @[axi4_to_ahb.scala 265:20] - slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 266:23] - slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 267:23] + buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 257:20] + buf_state_en <= slave_ready @[axi4_to_ahb.scala 258:20] + slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 259:23] + slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 260:23] skip @[Conditional.scala 39:67] - cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 271:16] - node _T_441 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 272:33] - node _T_442 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 272:73] - node _T_443 = eq(_T_442, UInt<1>("h01")) @[axi4_to_ahb.scala 272:80] - node _T_444 = and(buf_aligned_in, _T_443) @[axi4_to_ahb.scala 272:60] - node _T_445 = bits(_T_444, 0, 0) @[axi4_to_ahb.scala 272:100] - node _T_446 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:132] - node _T_447 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 134:50] - node _T_448 = eq(_T_447, UInt<8>("h0ff")) @[axi4_to_ahb.scala 134:57] - node _T_449 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 134:81] - node _T_450 = eq(_T_449, UInt<8>("h0f")) @[axi4_to_ahb.scala 134:88] - node _T_451 = or(_T_448, _T_450) @[axi4_to_ahb.scala 134:70] - node _T_452 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 134:117] - node _T_453 = eq(_T_452, UInt<8>("h03")) @[axi4_to_ahb.scala 134:124] - node _T_454 = or(_T_451, _T_453) @[axi4_to_ahb.scala 134:106] + cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 264:16] + node _T_441 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 265:33] + node _T_442 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 265:73] + node _T_443 = eq(_T_442, UInt<1>("h01")) @[axi4_to_ahb.scala 265:80] + node _T_444 = and(buf_aligned_in, _T_443) @[axi4_to_ahb.scala 265:60] + node _T_445 = bits(_T_444, 0, 0) @[axi4_to_ahb.scala 265:100] + node _T_446 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 265:132] + node _T_447 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:50] + node _T_448 = eq(_T_447, UInt<8>("h0ff")) @[axi4_to_ahb.scala 127:57] + node _T_449 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:81] + node _T_450 = eq(_T_449, UInt<8>("h0f")) @[axi4_to_ahb.scala 127:88] + node _T_451 = or(_T_448, _T_450) @[axi4_to_ahb.scala 127:70] + node _T_452 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:117] + node _T_453 = eq(_T_452, UInt<8>("h03")) @[axi4_to_ahb.scala 127:124] + node _T_454 = or(_T_451, _T_453) @[axi4_to_ahb.scala 127:106] node _T_455 = bits(_T_454, 0, 0) @[Bitwise.scala 72:15] node _T_456 = mux(_T_455, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_457 = and(UInt<3>("h00"), _T_456) @[axi4_to_ahb.scala 134:29] - node _T_458 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 135:35] - node _T_459 = eq(_T_458, UInt<8>("h0c")) @[axi4_to_ahb.scala 135:42] + node _T_457 = and(UInt<3>("h00"), _T_456) @[axi4_to_ahb.scala 127:29] + node _T_458 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 128:35] + node _T_459 = eq(_T_458, UInt<8>("h0c")) @[axi4_to_ahb.scala 128:42] node _T_460 = bits(_T_459, 0, 0) @[Bitwise.scala 72:15] node _T_461 = mux(_T_460, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_462 = and(UInt<2>("h02"), _T_461) @[axi4_to_ahb.scala 135:15] - node _T_463 = or(_T_457, _T_462) @[axi4_to_ahb.scala 134:146] - node _T_464 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 136:36] - node _T_465 = eq(_T_464, UInt<8>("h0f0")) @[axi4_to_ahb.scala 136:43] - node _T_466 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 136:67] - node _T_467 = eq(_T_466, UInt<8>("h03")) @[axi4_to_ahb.scala 136:74] - node _T_468 = or(_T_465, _T_467) @[axi4_to_ahb.scala 136:56] + node _T_462 = and(UInt<2>("h02"), _T_461) @[axi4_to_ahb.scala 128:15] + node _T_463 = or(_T_457, _T_462) @[axi4_to_ahb.scala 127:146] + node _T_464 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 129:36] + node _T_465 = eq(_T_464, UInt<8>("h0f0")) @[axi4_to_ahb.scala 129:43] + node _T_466 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 129:67] + node _T_467 = eq(_T_466, UInt<8>("h03")) @[axi4_to_ahb.scala 129:74] + node _T_468 = or(_T_465, _T_467) @[axi4_to_ahb.scala 129:56] node _T_469 = bits(_T_468, 0, 0) @[Bitwise.scala 72:15] node _T_470 = mux(_T_469, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_471 = and(UInt<3>("h04"), _T_470) @[axi4_to_ahb.scala 136:15] - node _T_472 = or(_T_463, _T_471) @[axi4_to_ahb.scala 135:63] - node _T_473 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 137:35] - node _T_474 = eq(_T_473, UInt<8>("h0c0")) @[axi4_to_ahb.scala 137:42] + node _T_471 = and(UInt<3>("h04"), _T_470) @[axi4_to_ahb.scala 129:15] + node _T_472 = or(_T_463, _T_471) @[axi4_to_ahb.scala 128:63] + node _T_473 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 130:35] + node _T_474 = eq(_T_473, UInt<8>("h0c0")) @[axi4_to_ahb.scala 130:42] node _T_475 = bits(_T_474, 0, 0) @[Bitwise.scala 72:15] node _T_476 = mux(_T_475, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_477 = and(UInt<3>("h06"), _T_476) @[axi4_to_ahb.scala 137:15] - node _T_478 = or(_T_472, _T_477) @[axi4_to_ahb.scala 136:96] - node _T_479 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 138:33] - node _T_480 = eq(_T_479, UInt<8>("h0c0")) @[axi4_to_ahb.scala 138:40] + node _T_477 = and(UInt<3>("h06"), _T_476) @[axi4_to_ahb.scala 130:15] + node _T_478 = or(_T_472, _T_477) @[axi4_to_ahb.scala 129:96] + node _T_479 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 131:33] + node _T_480 = eq(_T_479, UInt<8>("h0c0")) @[axi4_to_ahb.scala 131:40] node _T_481 = bits(_T_480, 0, 0) @[Bitwise.scala 72:15] node _T_482 = mux(_T_481, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_483 = and(UInt<3>("h06"), _T_482) @[axi4_to_ahb.scala 138:13] - node _T_484 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 272:152] - node _T_485 = mux(_T_445, _T_478, _T_484) @[axi4_to_ahb.scala 272:43] + node _T_483 = and(UInt<3>("h06"), _T_482) @[axi4_to_ahb.scala 131:13] + node _T_484 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 265:152] + node _T_485 = mux(_T_445, _T_478, _T_484) @[axi4_to_ahb.scala 265:43] node _T_486 = cat(_T_441, _T_485) @[Cat.scala 29:58] - buf_addr_in <= _T_486 @[axi4_to_ahb.scala 272:15] - node _T_487 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 273:27] - buf_tag_in <= _T_487 @[axi4_to_ahb.scala 273:14] - node _T_488 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 274:32] - buf_byteen_in <= _T_488 @[axi4_to_ahb.scala 274:17] - node _T_489 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 275:33] - node _T_490 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 275:59] - node _T_491 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 275:80] - node _T_492 = mux(_T_489, _T_490, _T_491) @[axi4_to_ahb.scala 275:21] - buf_data_in <= _T_492 @[axi4_to_ahb.scala 275:15] - node _T_493 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 276:52] - node _T_494 = eq(_T_493, UInt<2>("h03")) @[axi4_to_ahb.scala 276:58] - node _T_495 = and(buf_aligned_in, _T_494) @[axi4_to_ahb.scala 276:38] - node _T_496 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 276:84] - node _T_497 = eq(_T_496, UInt<1>("h01")) @[axi4_to_ahb.scala 276:91] - node _T_498 = and(_T_495, _T_497) @[axi4_to_ahb.scala 276:71] - node _T_499 = bits(_T_498, 0, 0) @[axi4_to_ahb.scala 276:111] - node _T_500 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 276:142] - node _T_501 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 128:42] - node _T_502 = eq(_T_501, UInt<8>("h0ff")) @[axi4_to_ahb.scala 128:49] + buf_addr_in <= _T_486 @[axi4_to_ahb.scala 265:15] + node _T_487 = bits(master_tag, 2, 0) @[axi4_to_ahb.scala 266:27] + buf_tag_in <= _T_487 @[axi4_to_ahb.scala 266:14] + node _T_488 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 267:32] + buf_byteen_in <= _T_488 @[axi4_to_ahb.scala 267:17] + node _T_489 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 268:33] + node _T_490 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 268:59] + node _T_491 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 268:80] + node _T_492 = mux(_T_489, _T_490, _T_491) @[axi4_to_ahb.scala 268:21] + buf_data_in <= _T_492 @[axi4_to_ahb.scala 268:15] + node _T_493 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 269:52] + node _T_494 = eq(_T_493, UInt<2>("h03")) @[axi4_to_ahb.scala 269:58] + node _T_495 = and(buf_aligned_in, _T_494) @[axi4_to_ahb.scala 269:38] + node _T_496 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 269:84] + node _T_497 = eq(_T_496, UInt<1>("h01")) @[axi4_to_ahb.scala 269:91] + node _T_498 = and(_T_495, _T_497) @[axi4_to_ahb.scala 269:71] + node _T_499 = bits(_T_498, 0, 0) @[axi4_to_ahb.scala 269:111] + node _T_500 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 269:142] + node _T_501 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 121:42] + node _T_502 = eq(_T_501, UInt<8>("h0ff")) @[axi4_to_ahb.scala 121:49] node _T_503 = bits(_T_502, 0, 0) @[Bitwise.scala 72:15] node _T_504 = mux(_T_503, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_505 = and(UInt<2>("h03"), _T_504) @[axi4_to_ahb.scala 128:25] - node _T_506 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 129:35] - node _T_507 = eq(_T_506, UInt<8>("h0f0")) @[axi4_to_ahb.scala 129:42] - node _T_508 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 129:64] - node _T_509 = eq(_T_508, UInt<8>("h0f")) @[axi4_to_ahb.scala 129:71] - node _T_510 = or(_T_507, _T_509) @[axi4_to_ahb.scala 129:55] + node _T_505 = and(UInt<2>("h03"), _T_504) @[axi4_to_ahb.scala 121:25] + node _T_506 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 122:35] + node _T_507 = eq(_T_506, UInt<8>("h0f0")) @[axi4_to_ahb.scala 122:42] + node _T_508 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 122:64] + node _T_509 = eq(_T_508, UInt<8>("h0f")) @[axi4_to_ahb.scala 122:71] + node _T_510 = or(_T_507, _T_509) @[axi4_to_ahb.scala 122:55] node _T_511 = bits(_T_510, 0, 0) @[Bitwise.scala 72:15] node _T_512 = mux(_T_511, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_513 = and(UInt<2>("h02"), _T_512) @[axi4_to_ahb.scala 129:16] - node _T_514 = or(_T_505, _T_513) @[axi4_to_ahb.scala 128:64] - node _T_515 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 130:40] - node _T_516 = eq(_T_515, UInt<8>("h0c0")) @[axi4_to_ahb.scala 130:47] - node _T_517 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 130:69] - node _T_518 = eq(_T_517, UInt<6>("h030")) @[axi4_to_ahb.scala 130:76] - node _T_519 = or(_T_516, _T_518) @[axi4_to_ahb.scala 130:60] - node _T_520 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 130:98] - node _T_521 = eq(_T_520, UInt<8>("h0c")) @[axi4_to_ahb.scala 130:105] - node _T_522 = or(_T_519, _T_521) @[axi4_to_ahb.scala 130:89] - node _T_523 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 130:132] - node _T_524 = eq(_T_523, UInt<8>("h03")) @[axi4_to_ahb.scala 130:139] - node _T_525 = or(_T_522, _T_524) @[axi4_to_ahb.scala 130:123] + node _T_513 = and(UInt<2>("h02"), _T_512) @[axi4_to_ahb.scala 122:16] + node _T_514 = or(_T_505, _T_513) @[axi4_to_ahb.scala 121:64] + node _T_515 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:40] + node _T_516 = eq(_T_515, UInt<8>("h0c0")) @[axi4_to_ahb.scala 123:47] + node _T_517 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:69] + node _T_518 = eq(_T_517, UInt<6>("h030")) @[axi4_to_ahb.scala 123:76] + node _T_519 = or(_T_516, _T_518) @[axi4_to_ahb.scala 123:60] + node _T_520 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:98] + node _T_521 = eq(_T_520, UInt<8>("h0c")) @[axi4_to_ahb.scala 123:105] + node _T_522 = or(_T_519, _T_521) @[axi4_to_ahb.scala 123:89] + node _T_523 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:132] + node _T_524 = eq(_T_523, UInt<8>("h03")) @[axi4_to_ahb.scala 123:139] + node _T_525 = or(_T_522, _T_524) @[axi4_to_ahb.scala 123:123] node _T_526 = bits(_T_525, 0, 0) @[Bitwise.scala 72:15] node _T_527 = mux(_T_526, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_528 = and(UInt<2>("h01"), _T_527) @[axi4_to_ahb.scala 130:21] - node _T_529 = or(_T_514, _T_528) @[axi4_to_ahb.scala 129:93] - node _T_530 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 276:161] - node _T_531 = mux(_T_499, _T_529, _T_530) @[axi4_to_ahb.scala 276:21] - buf_size_in <= _T_531 @[axi4_to_ahb.scala 276:15] - node _T_532 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 277:32] - node _T_533 = eq(_T_532, UInt<1>("h00")) @[axi4_to_ahb.scala 277:39] - node _T_534 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 278:17] - node _T_535 = eq(_T_534, UInt<1>("h00")) @[axi4_to_ahb.scala 278:24] - node _T_536 = or(_T_533, _T_535) @[axi4_to_ahb.scala 277:48] - node _T_537 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 278:47] - node _T_538 = eq(_T_537, UInt<2>("h01")) @[axi4_to_ahb.scala 278:54] - node _T_539 = or(_T_536, _T_538) @[axi4_to_ahb.scala 278:33] - node _T_540 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 278:86] - node _T_541 = eq(_T_540, UInt<2>("h02")) @[axi4_to_ahb.scala 278:93] - node _T_542 = or(_T_539, _T_541) @[axi4_to_ahb.scala 278:72] - node _T_543 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 279:18] - node _T_544 = eq(_T_543, UInt<2>("h03")) @[axi4_to_ahb.scala 279:25] - node _T_545 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 279:55] - node _T_546 = eq(_T_545, UInt<2>("h03")) @[axi4_to_ahb.scala 279:62] - node _T_547 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 279:90] - node _T_548 = eq(_T_547, UInt<4>("h0c")) @[axi4_to_ahb.scala 279:97] - node _T_549 = or(_T_546, _T_548) @[axi4_to_ahb.scala 279:74] - node _T_550 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 279:125] - node _T_551 = eq(_T_550, UInt<6>("h030")) @[axi4_to_ahb.scala 279:132] - node _T_552 = or(_T_549, _T_551) @[axi4_to_ahb.scala 279:109] - node _T_553 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 279:161] - node _T_554 = eq(_T_553, UInt<8>("h0c0")) @[axi4_to_ahb.scala 279:168] - node _T_555 = or(_T_552, _T_554) @[axi4_to_ahb.scala 279:145] - node _T_556 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 280:21] - node _T_557 = eq(_T_556, UInt<4>("h0f")) @[axi4_to_ahb.scala 280:28] - node _T_558 = or(_T_555, _T_557) @[axi4_to_ahb.scala 279:181] - node _T_559 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 280:56] - node _T_560 = eq(_T_559, UInt<8>("h0f0")) @[axi4_to_ahb.scala 280:63] - node _T_561 = or(_T_558, _T_560) @[axi4_to_ahb.scala 280:40] - node _T_562 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 280:92] - node _T_563 = eq(_T_562, UInt<8>("h0ff")) @[axi4_to_ahb.scala 280:99] - node _T_564 = or(_T_561, _T_563) @[axi4_to_ahb.scala 280:76] - node _T_565 = and(_T_544, _T_564) @[axi4_to_ahb.scala 279:38] - node _T_566 = or(_T_542, _T_565) @[axi4_to_ahb.scala 278:106] - buf_aligned_in <= _T_566 @[axi4_to_ahb.scala 277:18] - node _T_567 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 282:43] - node _T_568 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 282:62] - node _T_569 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 282:87] + node _T_528 = and(UInt<2>("h01"), _T_527) @[axi4_to_ahb.scala 123:21] + node _T_529 = or(_T_514, _T_528) @[axi4_to_ahb.scala 122:93] + node _T_530 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 269:161] + node _T_531 = mux(_T_499, _T_529, _T_530) @[axi4_to_ahb.scala 269:21] + buf_size_in <= _T_531 @[axi4_to_ahb.scala 269:15] + node _T_532 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 270:32] + node _T_533 = eq(_T_532, UInt<1>("h00")) @[axi4_to_ahb.scala 270:39] + node _T_534 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 271:17] + node _T_535 = eq(_T_534, UInt<1>("h00")) @[axi4_to_ahb.scala 271:24] + node _T_536 = or(_T_533, _T_535) @[axi4_to_ahb.scala 270:48] + node _T_537 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 271:47] + node _T_538 = eq(_T_537, UInt<2>("h01")) @[axi4_to_ahb.scala 271:54] + node _T_539 = or(_T_536, _T_538) @[axi4_to_ahb.scala 271:33] + node _T_540 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 271:86] + node _T_541 = eq(_T_540, UInt<2>("h02")) @[axi4_to_ahb.scala 271:93] + node _T_542 = or(_T_539, _T_541) @[axi4_to_ahb.scala 271:72] + node _T_543 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 272:18] + node _T_544 = eq(_T_543, UInt<2>("h03")) @[axi4_to_ahb.scala 272:25] + node _T_545 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:55] + node _T_546 = eq(_T_545, UInt<2>("h03")) @[axi4_to_ahb.scala 272:62] + node _T_547 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:90] + node _T_548 = eq(_T_547, UInt<4>("h0c")) @[axi4_to_ahb.scala 272:97] + node _T_549 = or(_T_546, _T_548) @[axi4_to_ahb.scala 272:74] + node _T_550 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:125] + node _T_551 = eq(_T_550, UInt<6>("h030")) @[axi4_to_ahb.scala 272:132] + node _T_552 = or(_T_549, _T_551) @[axi4_to_ahb.scala 272:109] + node _T_553 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:161] + node _T_554 = eq(_T_553, UInt<8>("h0c0")) @[axi4_to_ahb.scala 272:168] + node _T_555 = or(_T_552, _T_554) @[axi4_to_ahb.scala 272:145] + node _T_556 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 273:21] + node _T_557 = eq(_T_556, UInt<4>("h0f")) @[axi4_to_ahb.scala 273:28] + node _T_558 = or(_T_555, _T_557) @[axi4_to_ahb.scala 272:181] + node _T_559 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 273:56] + node _T_560 = eq(_T_559, UInt<8>("h0f0")) @[axi4_to_ahb.scala 273:63] + node _T_561 = or(_T_558, _T_560) @[axi4_to_ahb.scala 273:40] + node _T_562 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 273:92] + node _T_563 = eq(_T_562, UInt<8>("h0ff")) @[axi4_to_ahb.scala 273:99] + node _T_564 = or(_T_561, _T_563) @[axi4_to_ahb.scala 273:76] + node _T_565 = and(_T_544, _T_564) @[axi4_to_ahb.scala 272:38] + node _T_566 = or(_T_542, _T_565) @[axi4_to_ahb.scala 271:106] + buf_aligned_in <= _T_566 @[axi4_to_ahb.scala 270:18] + node _T_567 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 275:43] + node _T_568 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 275:62] + node _T_569 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 275:87] node _T_570 = cat(_T_568, _T_569) @[Cat.scala 29:58] - node _T_571 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 282:108] - node _T_572 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 282:133] + node _T_571 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 275:108] + node _T_572 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 275:133] node _T_573 = cat(_T_571, _T_572) @[Cat.scala 29:58] - node _T_574 = mux(_T_567, _T_570, _T_573) @[axi4_to_ahb.scala 282:26] - io.ahb.out.haddr <= _T_574 @[axi4_to_ahb.scala 282:20] - node _T_575 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 283:43] + node _T_574 = mux(_T_567, _T_570, _T_573) @[axi4_to_ahb.scala 275:26] + io.ahb.out.haddr <= _T_574 @[axi4_to_ahb.scala 275:20] + node _T_575 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 276:43] node _T_576 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15] node _T_577 = mux(_T_576, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_578 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 283:94] - node _T_579 = and(_T_577, _T_578) @[axi4_to_ahb.scala 283:81] + node _T_578 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 276:94] + node _T_579 = and(_T_577, _T_578) @[axi4_to_ahb.scala 276:81] node _T_580 = cat(UInt<1>("h00"), _T_579) @[Cat.scala 29:58] node _T_581 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15] node _T_582 = mux(_T_581, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_583 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 283:148] - node _T_584 = and(_T_582, _T_583) @[axi4_to_ahb.scala 283:138] + node _T_583 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 276:148] + node _T_584 = and(_T_582, _T_583) @[axi4_to_ahb.scala 276:138] node _T_585 = cat(UInt<1>("h00"), _T_584) @[Cat.scala 29:58] - node _T_586 = mux(_T_575, _T_580, _T_585) @[axi4_to_ahb.scala 283:26] - io.ahb.out.hsize <= _T_586 @[axi4_to_ahb.scala 283:20] - io.ahb.out.hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 285:21] - io.ahb.out.hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 286:24] - node _T_587 = bits(io.axi.ar.bits.prot, 2, 2) @[axi4_to_ahb.scala 287:57] - node _T_588 = eq(_T_587, UInt<1>("h00")) @[axi4_to_ahb.scala 287:37] + node _T_586 = mux(_T_575, _T_580, _T_585) @[axi4_to_ahb.scala 276:26] + io.ahb.out.hsize <= _T_586 @[axi4_to_ahb.scala 276:20] + io.ahb.out.hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 278:21] + io.ahb.out.hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 279:24] + node _T_587 = bits(io.axi.ar.bits.prot, 2, 2) @[axi4_to_ahb.scala 280:57] + node _T_588 = eq(_T_587, UInt<1>("h00")) @[axi4_to_ahb.scala 280:37] node _T_589 = cat(UInt<1>("h01"), _T_588) @[Cat.scala 29:58] - io.ahb.out.hprot <= _T_589 @[axi4_to_ahb.scala 287:20] - node _T_590 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 288:44] - node _T_591 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 288:59] - node _T_592 = eq(_T_591, UInt<1>("h01")) @[axi4_to_ahb.scala 288:66] - node _T_593 = mux(_T_590, _T_592, buf_write) @[axi4_to_ahb.scala 288:27] - io.ahb.out.hwrite <= _T_593 @[axi4_to_ahb.scala 288:21] - node _T_594 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 289:32] - io.ahb.out.hwdata <= _T_594 @[axi4_to_ahb.scala 289:21] - slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 291:15] - node _T_595 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 292:43] - node _T_596 = mux(_T_595, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 292:23] + io.ahb.out.hprot <= _T_589 @[axi4_to_ahb.scala 280:20] + node _T_590 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 281:44] + node _T_591 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 281:59] + node _T_592 = eq(_T_591, UInt<1>("h01")) @[axi4_to_ahb.scala 281:66] + node _T_593 = mux(_T_590, _T_592, buf_write) @[axi4_to_ahb.scala 281:27] + io.ahb.out.hwrite <= _T_593 @[axi4_to_ahb.scala 281:21] + node _T_594 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 282:32] + io.ahb.out.hwdata <= _T_594 @[axi4_to_ahb.scala 282:21] + slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 284:15] + node _T_595 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 285:43] + node _T_596 = mux(_T_595, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 285:23] node _T_597 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15] node _T_598 = mux(_T_597, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_599 = and(_T_598, UInt<2>("h02")) @[axi4_to_ahb.scala 292:88] + node _T_599 = and(_T_598, UInt<2>("h02")) @[axi4_to_ahb.scala 285:88] node _T_600 = cat(_T_596, _T_599) @[Cat.scala 29:58] - slave_opc <= _T_600 @[axi4_to_ahb.scala 292:13] - node _T_601 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 293:41] - node _T_602 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 293:66] + slave_opc <= _T_600 @[axi4_to_ahb.scala 285:13] + node _T_601 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 286:41] + node _T_602 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 286:66] node _T_603 = cat(_T_602, _T_602) @[Cat.scala 29:58] - node _T_604 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 293:91] - node _T_605 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 293:110] - node _T_606 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 293:131] - node _T_607 = mux(_T_604, _T_605, _T_606) @[axi4_to_ahb.scala 293:79] - node _T_608 = mux(_T_601, _T_603, _T_607) @[axi4_to_ahb.scala 293:21] - slave_rdata <= _T_608 @[axi4_to_ahb.scala 293:15] - node _T_609 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 294:26] - slave_tag <= _T_609 @[axi4_to_ahb.scala 294:13] - node _T_610 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 296:37] - node _T_611 = neq(_T_610, UInt<1>("h00")) @[axi4_to_ahb.scala 296:44] - node _T_612 = and(_T_611, io.ahb.in.hready) @[axi4_to_ahb.scala 296:56] - node _T_613 = and(_T_612, io.ahb.out.hwrite) @[axi4_to_ahb.scala 296:75] - last_addr_en <= _T_613 @[axi4_to_ahb.scala 296:16] - node _T_614 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 298:31] - node _T_615 = and(_T_614, master_ready) @[axi4_to_ahb.scala 298:49] - wrbuf_en <= _T_615 @[axi4_to_ahb.scala 298:12] - node _T_616 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 299:35] - node _T_617 = and(_T_616, master_ready) @[axi4_to_ahb.scala 299:52] - wrbuf_data_en <= _T_617 @[axi4_to_ahb.scala 299:17] - node _T_618 = and(master_valid, master_ready) @[axi4_to_ahb.scala 300:34] - node _T_619 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 300:62] - node _T_620 = eq(_T_619, UInt<1>("h01")) @[axi4_to_ahb.scala 300:69] - node _T_621 = and(_T_618, _T_620) @[axi4_to_ahb.scala 300:49] - wrbuf_cmd_sent <= _T_621 @[axi4_to_ahb.scala 300:18] - node _T_622 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 301:33] - node _T_623 = and(wrbuf_cmd_sent, _T_622) @[axi4_to_ahb.scala 301:31] - wrbuf_rst <= _T_623 @[axi4_to_ahb.scala 301:13] - node _T_624 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 303:36] - node _T_625 = and(wrbuf_vld, _T_624) @[axi4_to_ahb.scala 303:34] - node _T_626 = eq(_T_625, UInt<1>("h00")) @[axi4_to_ahb.scala 303:22] - node _T_627 = and(_T_626, master_ready) @[axi4_to_ahb.scala 303:53] - io.axi.aw.ready <= _T_627 @[axi4_to_ahb.scala 303:19] - node _T_628 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 304:40] - node _T_629 = and(wrbuf_data_vld, _T_628) @[axi4_to_ahb.scala 304:38] - node _T_630 = eq(_T_629, UInt<1>("h00")) @[axi4_to_ahb.scala 304:21] - node _T_631 = and(_T_630, master_ready) @[axi4_to_ahb.scala 304:57] - io.axi.w.ready <= _T_631 @[axi4_to_ahb.scala 304:18] - node _T_632 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 305:34] - node _T_633 = eq(_T_632, UInt<1>("h00")) @[axi4_to_ahb.scala 305:22] - node _T_634 = and(_T_633, master_ready) @[axi4_to_ahb.scala 305:52] - io.axi.ar.ready <= _T_634 @[axi4_to_ahb.scala 305:19] - io.axi.r.bits.last <= UInt<1>("h01") @[axi4_to_ahb.scala 306:22] - node _T_635 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 308:71] - node _T_636 = mux(_T_635, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 308:55] - node _T_637 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 308:91] - node _T_638 = and(_T_636, _T_637) @[axi4_to_ahb.scala 308:89] - reg _T_639 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 308:51] - _T_639 <= _T_638 @[axi4_to_ahb.scala 308:51] - wrbuf_vld <= _T_639 @[axi4_to_ahb.scala 308:21] - node _T_640 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 309:76] - node _T_641 = mux(_T_640, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 309:55] - node _T_642 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 309:102] - node _T_643 = and(_T_641, _T_642) @[axi4_to_ahb.scala 309:100] - reg _T_644 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 309:51] - _T_644 <= _T_643 @[axi4_to_ahb.scala 309:51] - wrbuf_data_vld <= _T_644 @[axi4_to_ahb.scala 309:21] - node _T_645 = bits(io.axi.aw.bits.id, 0, 0) @[axi4_to_ahb.scala 310:71] - node _T_646 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 310:105] + node _T_604 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 286:91] + node _T_605 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 286:110] + node _T_606 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 286:131] + node _T_607 = mux(_T_604, _T_605, _T_606) @[axi4_to_ahb.scala 286:79] + node _T_608 = mux(_T_601, _T_603, _T_607) @[axi4_to_ahb.scala 286:21] + slave_rdata <= _T_608 @[axi4_to_ahb.scala 286:15] + node _T_609 = bits(slvbuf_tag, 2, 0) @[axi4_to_ahb.scala 287:26] + slave_tag <= _T_609 @[axi4_to_ahb.scala 287:13] + node _T_610 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 289:37] + node _T_611 = neq(_T_610, UInt<1>("h00")) @[axi4_to_ahb.scala 289:44] + node _T_612 = and(_T_611, io.ahb.in.hready) @[axi4_to_ahb.scala 289:56] + node _T_613 = and(_T_612, io.ahb.out.hwrite) @[axi4_to_ahb.scala 289:75] + last_addr_en <= _T_613 @[axi4_to_ahb.scala 289:16] + node _T_614 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 291:31] + node _T_615 = and(_T_614, master_ready) @[axi4_to_ahb.scala 291:49] + wrbuf_en <= _T_615 @[axi4_to_ahb.scala 291:12] + node _T_616 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 292:35] + node _T_617 = and(_T_616, master_ready) @[axi4_to_ahb.scala 292:52] + wrbuf_data_en <= _T_617 @[axi4_to_ahb.scala 292:17] + node _T_618 = and(master_valid, master_ready) @[axi4_to_ahb.scala 293:34] + node _T_619 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 293:62] + node _T_620 = eq(_T_619, UInt<1>("h01")) @[axi4_to_ahb.scala 293:69] + node _T_621 = and(_T_618, _T_620) @[axi4_to_ahb.scala 293:49] + wrbuf_cmd_sent <= _T_621 @[axi4_to_ahb.scala 293:18] + node _T_622 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 294:33] + node _T_623 = and(wrbuf_cmd_sent, _T_622) @[axi4_to_ahb.scala 294:31] + wrbuf_rst <= _T_623 @[axi4_to_ahb.scala 294:13] + node _T_624 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 296:36] + node _T_625 = and(wrbuf_vld, _T_624) @[axi4_to_ahb.scala 296:34] + node _T_626 = eq(_T_625, UInt<1>("h00")) @[axi4_to_ahb.scala 296:22] + node _T_627 = and(_T_626, master_ready) @[axi4_to_ahb.scala 296:53] + io.axi.aw.ready <= _T_627 @[axi4_to_ahb.scala 296:19] + node _T_628 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 297:40] + node _T_629 = and(wrbuf_data_vld, _T_628) @[axi4_to_ahb.scala 297:38] + node _T_630 = eq(_T_629, UInt<1>("h00")) @[axi4_to_ahb.scala 297:21] + node _T_631 = and(_T_630, master_ready) @[axi4_to_ahb.scala 297:57] + io.axi.w.ready <= _T_631 @[axi4_to_ahb.scala 297:18] + node _T_632 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 298:34] + node _T_633 = eq(_T_632, UInt<1>("h00")) @[axi4_to_ahb.scala 298:22] + node _T_634 = and(_T_633, master_ready) @[axi4_to_ahb.scala 298:52] + io.axi.ar.ready <= _T_634 @[axi4_to_ahb.scala 298:19] + io.axi.r.bits.last <= UInt<1>("h01") @[axi4_to_ahb.scala 299:22] + node _T_635 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 301:71] + node _T_636 = mux(_T_635, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 301:55] + node _T_637 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 301:91] + node _T_638 = and(_T_636, _T_637) @[axi4_to_ahb.scala 301:89] + reg _T_639 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 301:51] + _T_639 <= _T_638 @[axi4_to_ahb.scala 301:51] + wrbuf_vld <= _T_639 @[axi4_to_ahb.scala 301:21] + node _T_640 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 302:76] + node _T_641 = mux(_T_640, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 302:55] + node _T_642 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 302:102] + node _T_643 = and(_T_641, _T_642) @[axi4_to_ahb.scala 302:100] + reg _T_644 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 302:51] + _T_644 <= _T_643 @[axi4_to_ahb.scala 302:51] + wrbuf_data_vld <= _T_644 @[axi4_to_ahb.scala 302:21] + node _T_645 = bits(io.axi.aw.bits.id, 2, 0) @[axi4_to_ahb.scala 303:71] + node _T_646 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 303:105] reg _T_647 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_646 : @[Reg.scala 28:19] _T_647 <= _T_645 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_tag <= _T_647 @[axi4_to_ahb.scala 310:21] - node _T_648 = bits(io.axi.aw.bits.size, 2, 0) @[axi4_to_ahb.scala 311:73] - node _T_649 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 311:101] + wrbuf_tag <= _T_647 @[axi4_to_ahb.scala 303:21] + node _T_648 = bits(io.axi.aw.bits.size, 2, 0) @[axi4_to_ahb.scala 304:73] + node _T_649 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 304:101] reg _T_650 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_649 : @[Reg.scala 28:19] _T_650 <= _T_648 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_size <= _T_650 @[axi4_to_ahb.scala 311:21] - node _T_651 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 312:61] + wrbuf_size <= _T_650 @[axi4_to_ahb.scala 304:21] + node _T_651 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 305:61] inst rvclkhdr_2 of rvclkhdr_871 @[lib.scala 368:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset @@ -113096,8 +113086,8 @@ circuit quasar_wrapper : rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_652 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_652 <= io.axi.aw.bits.addr @[lib.scala 374:16] - wrbuf_addr <= _T_652 @[axi4_to_ahb.scala 312:21] - node _T_653 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 313:65] + wrbuf_addr <= _T_652 @[axi4_to_ahb.scala 305:21] + node _T_653 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 306:65] inst rvclkhdr_3 of rvclkhdr_872 @[lib.scala 368:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset @@ -113106,37 +113096,37 @@ circuit quasar_wrapper : rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_654 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_654 <= io.axi.w.bits.data @[lib.scala 374:16] - wrbuf_data <= _T_654 @[axi4_to_ahb.scala 313:21] - node _T_655 = bits(io.axi.w.bits.strb, 7, 0) @[axi4_to_ahb.scala 314:72] - node _T_656 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 314:105] + wrbuf_data <= _T_654 @[axi4_to_ahb.scala 306:21] + node _T_655 = bits(io.axi.w.bits.strb, 7, 0) @[axi4_to_ahb.scala 307:72] + node _T_656 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 307:105] reg _T_657 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_656 : @[Reg.scala 28:19] _T_657 <= _T_655 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_byteen <= _T_657 @[axi4_to_ahb.scala 314:21] - node _T_658 = bits(io.ahb.out.haddr, 31, 0) @[axi4_to_ahb.scala 315:71] - node _T_659 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 315:104] + wrbuf_byteen <= _T_657 @[axi4_to_ahb.scala 307:21] + node _T_658 = bits(io.ahb.out.haddr, 31, 0) @[axi4_to_ahb.scala 308:71] + node _T_659 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 308:104] reg _T_660 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_659 : @[Reg.scala 28:19] _T_660 <= _T_658 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - last_bus_addr <= _T_660 @[axi4_to_ahb.scala 315:21] - node _T_661 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 316:89] + last_bus_addr <= _T_660 @[axi4_to_ahb.scala 308:21] + node _T_661 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 309:89] reg _T_662 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_661 : @[Reg.scala 28:19] _T_662 <= buf_write_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_write <= _T_662 @[axi4_to_ahb.scala 316:21] - node _T_663 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 317:64] - node _T_664 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 317:99] + buf_write <= _T_662 @[axi4_to_ahb.scala 309:21] + node _T_663 = bits(buf_tag_in, 2, 0) @[axi4_to_ahb.scala 310:64] + node _T_664 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 310:99] reg _T_665 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_664 : @[Reg.scala 28:19] _T_665 <= _T_663 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_tag <= _T_665 @[axi4_to_ahb.scala 317:21] - node _T_666 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 318:42] - node _T_667 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 318:61] - node _T_668 = bits(_T_667, 0, 0) @[axi4_to_ahb.scala 318:78] + buf_tag <= _T_665 @[axi4_to_ahb.scala 310:21] + node _T_666 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 311:42] + node _T_667 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 311:61] + node _T_668 = bits(_T_667, 0, 0) @[axi4_to_ahb.scala 311:78] inst rvclkhdr_4 of rvclkhdr_873 @[lib.scala 368:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset @@ -113145,30 +113135,30 @@ circuit quasar_wrapper : rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_669 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_669 <= _T_666 @[lib.scala 374:16] - buf_addr <= _T_669 @[axi4_to_ahb.scala 318:21] - node _T_670 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 319:65] - node _T_671 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 319:94] + buf_addr <= _T_669 @[axi4_to_ahb.scala 311:21] + node _T_670 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 312:65] + node _T_671 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 312:94] reg _T_672 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_671 : @[Reg.scala 28:19] _T_672 <= _T_670 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_size <= _T_672 @[axi4_to_ahb.scala 319:21] - node _T_673 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 320:91] + buf_size <= _T_672 @[axi4_to_ahb.scala 312:21] + node _T_673 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 313:91] reg _T_674 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_673 : @[Reg.scala 28:19] _T_674 <= buf_aligned_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_aligned <= _T_674 @[axi4_to_ahb.scala 320:21] - node _T_675 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 321:67] - node _T_676 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 321:96] + buf_aligned <= _T_674 @[axi4_to_ahb.scala 313:21] + node _T_675 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 314:67] + node _T_676 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 314:96] reg _T_677 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_676 : @[Reg.scala 28:19] _T_677 <= _T_675 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_byteen <= _T_677 @[axi4_to_ahb.scala 321:21] - node _T_678 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 322:42] - node _T_679 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 322:66] - node _T_680 = bits(_T_679, 0, 0) @[axi4_to_ahb.scala 322:89] + buf_byteen <= _T_677 @[axi4_to_ahb.scala 314:21] + node _T_678 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 315:42] + node _T_679 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 315:66] + node _T_680 = bits(_T_679, 0, 0) @[axi4_to_ahb.scala 315:89] inst rvclkhdr_5 of rvclkhdr_874 @[lib.scala 368:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset @@ -113177,98 +113167,98 @@ circuit quasar_wrapper : rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_681 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_681 <= _T_678 @[lib.scala 374:16] - buf_data <= _T_681 @[axi4_to_ahb.scala 322:21] - node _T_682 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 323:89] + buf_data <= _T_681 @[axi4_to_ahb.scala 315:21] + node _T_682 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 316:89] reg _T_683 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_682 : @[Reg.scala 28:19] _T_683 <= buf_write @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_write <= _T_683 @[axi4_to_ahb.scala 323:21] - node _T_684 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 324:61] - node _T_685 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 324:99] + slvbuf_write <= _T_683 @[axi4_to_ahb.scala 316:21] + node _T_684 = bits(buf_tag, 2, 0) @[axi4_to_ahb.scala 317:61] + node _T_685 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 317:99] reg _T_686 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_685 : @[Reg.scala 28:19] _T_686 <= _T_684 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_tag <= _T_686 @[axi4_to_ahb.scala 324:21] - node _T_687 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 325:99] + slvbuf_tag <= _T_686 @[axi4_to_ahb.scala 317:21] + node _T_687 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 318:99] reg _T_688 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_687 : @[Reg.scala 28:19] _T_688 <= slvbuf_error_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_error <= _T_688 @[axi4_to_ahb.scala 325:21] - node _T_689 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 326:72] - node _T_690 = mux(_T_689, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 326:56] - node _T_691 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 326:92] - node _T_692 = and(_T_690, _T_691) @[axi4_to_ahb.scala 326:90] - reg _T_693 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 326:52] - _T_693 <= _T_692 @[axi4_to_ahb.scala 326:52] - cmd_doneQ <= _T_693 @[axi4_to_ahb.scala 326:21] - node _T_694 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 327:71] - node _T_695 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 327:110] + slvbuf_error <= _T_688 @[axi4_to_ahb.scala 318:21] + node _T_689 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 319:72] + node _T_690 = mux(_T_689, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 319:56] + node _T_691 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 319:92] + node _T_692 = and(_T_690, _T_691) @[axi4_to_ahb.scala 319:90] + reg _T_693 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 319:52] + _T_693 <= _T_692 @[axi4_to_ahb.scala 319:52] + cmd_doneQ <= _T_693 @[axi4_to_ahb.scala 319:21] + node _T_694 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 320:71] + node _T_695 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 320:110] reg _T_696 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_695 : @[Reg.scala 28:19] _T_696 <= _T_694 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_cmd_byte_ptrQ <= _T_696 @[axi4_to_ahb.scala 327:21] - reg _T_697 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 328:52] - _T_697 <= io.ahb.in.hready @[axi4_to_ahb.scala 328:52] - ahb_hready_q <= _T_697 @[axi4_to_ahb.scala 328:21] - node _T_698 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 329:70] - reg _T_699 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 329:52] - _T_699 <= _T_698 @[axi4_to_ahb.scala 329:52] - ahb_htrans_q <= _T_699 @[axi4_to_ahb.scala 329:21] - reg _T_700 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 330:57] - _T_700 <= io.ahb.out.hwrite @[axi4_to_ahb.scala 330:57] - ahb_hwrite_q <= _T_700 @[axi4_to_ahb.scala 330:21] - reg _T_701 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 331:52] - _T_701 <= io.ahb.in.hresp @[axi4_to_ahb.scala 331:52] - ahb_hresp_q <= _T_701 @[axi4_to_ahb.scala 331:21] - node _T_702 = bits(io.ahb.in.hrdata, 63, 0) @[axi4_to_ahb.scala 332:74] - reg _T_703 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 332:57] - _T_703 <= _T_702 @[axi4_to_ahb.scala 332:57] - ahb_hrdata_q <= _T_703 @[axi4_to_ahb.scala 332:21] - node _T_704 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 334:43] - node _T_705 = or(_T_704, io.clk_override) @[axi4_to_ahb.scala 334:58] - node _T_706 = and(io.bus_clk_en, _T_705) @[axi4_to_ahb.scala 334:30] - buf_clken <= _T_706 @[axi4_to_ahb.scala 334:13] - node _T_707 = bits(io.ahb.out.htrans, 1, 1) @[axi4_to_ahb.scala 335:76] - node _T_708 = and(io.ahb.in.hready, _T_707) @[axi4_to_ahb.scala 335:57] - node _T_709 = or(_T_708, io.clk_override) @[axi4_to_ahb.scala 335:81] - node _T_710 = and(io.bus_clk_en, _T_709) @[axi4_to_ahb.scala 335:36] - ahbm_addr_clken <= _T_710 @[axi4_to_ahb.scala 335:19] - node _T_711 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 336:50] - node _T_712 = or(_T_711, io.clk_override) @[axi4_to_ahb.scala 336:60] - node _T_713 = and(io.bus_clk_en, _T_712) @[axi4_to_ahb.scala 336:36] - ahbm_data_clken <= _T_713 @[axi4_to_ahb.scala 336:19] + buf_cmd_byte_ptrQ <= _T_696 @[axi4_to_ahb.scala 320:21] + reg _T_697 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 321:52] + _T_697 <= io.ahb.in.hready @[axi4_to_ahb.scala 321:52] + ahb_hready_q <= _T_697 @[axi4_to_ahb.scala 321:21] + node _T_698 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 322:70] + reg _T_699 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 322:52] + _T_699 <= _T_698 @[axi4_to_ahb.scala 322:52] + ahb_htrans_q <= _T_699 @[axi4_to_ahb.scala 322:21] + reg _T_700 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 323:57] + _T_700 <= io.ahb.out.hwrite @[axi4_to_ahb.scala 323:57] + ahb_hwrite_q <= _T_700 @[axi4_to_ahb.scala 323:21] + reg _T_701 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 324:52] + _T_701 <= io.ahb.in.hresp @[axi4_to_ahb.scala 324:52] + ahb_hresp_q <= _T_701 @[axi4_to_ahb.scala 324:21] + node _T_702 = bits(io.ahb.in.hrdata, 63, 0) @[axi4_to_ahb.scala 325:74] + reg _T_703 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 325:57] + _T_703 <= _T_702 @[axi4_to_ahb.scala 325:57] + ahb_hrdata_q <= _T_703 @[axi4_to_ahb.scala 325:21] + node _T_704 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 327:43] + node _T_705 = or(_T_704, io.clk_override) @[axi4_to_ahb.scala 327:58] + node _T_706 = and(io.bus_clk_en, _T_705) @[axi4_to_ahb.scala 327:30] + buf_clken <= _T_706 @[axi4_to_ahb.scala 327:13] + node _T_707 = bits(io.ahb.out.htrans, 1, 1) @[axi4_to_ahb.scala 328:76] + node _T_708 = and(io.ahb.in.hready, _T_707) @[axi4_to_ahb.scala 328:57] + node _T_709 = or(_T_708, io.clk_override) @[axi4_to_ahb.scala 328:81] + node _T_710 = and(io.bus_clk_en, _T_709) @[axi4_to_ahb.scala 328:36] + ahbm_addr_clken <= _T_710 @[axi4_to_ahb.scala 328:19] + node _T_711 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 329:50] + node _T_712 = or(_T_711, io.clk_override) @[axi4_to_ahb.scala 329:60] + node _T_713 = and(io.bus_clk_en, _T_712) @[axi4_to_ahb.scala 329:36] + ahbm_data_clken <= _T_713 @[axi4_to_ahb.scala 329:19] inst rvclkhdr_6 of rvclkhdr_875 @[lib.scala 343:22] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset rvclkhdr_6.io.clk <= clock @[lib.scala 344:17] rvclkhdr_6.io.en <= buf_clken @[lib.scala 345:16] rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 339:12] + buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 332:12] inst rvclkhdr_7 of rvclkhdr_876 @[lib.scala 343:22] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= reset rvclkhdr_7.io.clk <= clock @[lib.scala 344:17] rvclkhdr_7.io.en <= io.bus_clk_en @[lib.scala 345:16] rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 340:12] + ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 333:12] inst rvclkhdr_8 of rvclkhdr_877 @[lib.scala 343:22] rvclkhdr_8.clock <= clock rvclkhdr_8.reset <= reset rvclkhdr_8.io.clk <= clock @[lib.scala 344:17] rvclkhdr_8.io.en <= ahbm_addr_clken @[lib.scala 345:16] rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 341:17] + ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 334:17] inst rvclkhdr_9 of rvclkhdr_878 @[lib.scala 343:22] rvclkhdr_9.clock <= clock rvclkhdr_9.reset <= reset rvclkhdr_9.io.clk <= clock @[lib.scala 344:17] rvclkhdr_9.io.en <= ahbm_data_clken @[lib.scala 345:16] rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 342:17] + ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 335:17] extmodule gated_latch_879 : output Q : Clock @@ -113532,9 +113522,9 @@ circuit quasar_wrapper : ahb_bus_addr_clk_en <= UInt<1>("h00") wire buf_rdata_clk_en : UInt<1> buf_rdata_clk_en <= UInt<1>("h00") - wire ahb_clk : Clock @[ahb_to_axi4.scala 44:33] - wire ahb_addr_clk : Clock @[ahb_to_axi4.scala 45:33] - wire buf_rdata_clk : Clock @[ahb_to_axi4.scala 46:33] + wire ahb_clk : Clock @[ahb_to_axi4.scala 43:33] + wire ahb_addr_clk : Clock @[ahb_to_axi4.scala 44:33] + wire buf_rdata_clk : Clock @[ahb_to_axi4.scala 45:33] wire cmdbuf_wr_en : UInt<1> cmdbuf_wr_en <= UInt<1>("h00") wire cmdbuf_rst : UInt<1> @@ -113553,7 +113543,7 @@ circuit quasar_wrapper : cmdbuf_addr <= UInt<32>("h00") wire cmdbuf_wdata : UInt<64> cmdbuf_wdata <= UInt<64>("h00") - wire bus_clk : Clock @[ahb_to_axi4.scala 58:33] + wire bus_clk : Clock @[ahb_to_axi4.scala 57:33] node _T_1 = bits(ahb_haddr_q, 31, 28) @[lib.scala 84:25] node ahb_addr_in_dccm_region_nc = eq(_T_1, UInt<4>("h0f")) @[lib.scala 84:47] node _T_2 = bits(ahb_haddr_q, 31, 16) @[lib.scala 87:14] @@ -113570,260 +113560,260 @@ circuit quasar_wrapper : buf_state <= UInt<2>("h00") wire buf_nxtstate : UInt<2> buf_nxtstate <= UInt<2>("h00") - buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 68:31] - buf_state_en <= UInt<1>("h00") @[ahb_to_axi4.scala 69:31] - buf_rdata_en <= UInt<1>("h00") @[ahb_to_axi4.scala 70:31] - buf_read_error_in <= UInt<1>("h00") @[ahb_to_axi4.scala 71:31] - cmdbuf_wr_en <= UInt<1>("h00") @[ahb_to_axi4.scala 72:31] + buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 67:31] + buf_state_en <= UInt<1>("h00") @[ahb_to_axi4.scala 68:31] + buf_rdata_en <= UInt<1>("h00") @[ahb_to_axi4.scala 69:31] + buf_read_error_in <= UInt<1>("h00") @[ahb_to_axi4.scala 70:31] + cmdbuf_wr_en <= UInt<1>("h00") @[ahb_to_axi4.scala 71:31] node _T_7 = eq(UInt<2>("h00"), buf_state) @[Conditional.scala 37:30] when _T_7 : @[Conditional.scala 40:58] - node _T_8 = mux(io.ahb.sig.out.hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 76:26] - buf_nxtstate <= _T_8 @[ahb_to_axi4.scala 76:20] - node _T_9 = bits(io.ahb.sig.out.htrans, 1, 1) @[ahb_to_axi4.scala 77:57] - node _T_10 = and(ahb_hready, _T_9) @[ahb_to_axi4.scala 77:34] - node _T_11 = and(_T_10, io.ahb.hsel) @[ahb_to_axi4.scala 77:61] - buf_state_en <= _T_11 @[ahb_to_axi4.scala 77:20] + node _T_8 = mux(io.ahb.sig.out.hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 75:26] + buf_nxtstate <= _T_8 @[ahb_to_axi4.scala 75:20] + node _T_9 = bits(io.ahb.sig.out.htrans, 1, 1) @[ahb_to_axi4.scala 76:57] + node _T_10 = and(ahb_hready, _T_9) @[ahb_to_axi4.scala 76:34] + node _T_11 = and(_T_10, io.ahb.hsel) @[ahb_to_axi4.scala 76:61] + buf_state_en <= _T_11 @[ahb_to_axi4.scala 76:20] skip @[Conditional.scala 40:58] else : @[Conditional.scala 39:67] node _T_12 = eq(UInt<2>("h01"), buf_state) @[Conditional.scala 37:30] when _T_12 : @[Conditional.scala 39:67] - node _T_13 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 80:72] - node _T_14 = eq(_T_13, UInt<1>("h00")) @[ahb_to_axi4.scala 80:79] - node _T_15 = or(io.ahb.sig.in.hresp, _T_14) @[ahb_to_axi4.scala 80:48] - node _T_16 = eq(io.ahb.hsel, UInt<1>("h00")) @[ahb_to_axi4.scala 80:93] - node _T_17 = or(_T_15, _T_16) @[ahb_to_axi4.scala 80:91] - node _T_18 = bits(_T_17, 0, 0) @[ahb_to_axi4.scala 80:107] - node _T_19 = mux(io.ahb.sig.out.hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 80:124] - node _T_20 = mux(_T_18, UInt<2>("h00"), _T_19) @[ahb_to_axi4.scala 80:26] - buf_nxtstate <= _T_20 @[ahb_to_axi4.scala 80:20] - node _T_21 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 81:24] - node _T_22 = or(_T_21, io.ahb.sig.in.hresp) @[ahb_to_axi4.scala 81:37] - buf_state_en <= _T_22 @[ahb_to_axi4.scala 81:20] - node _T_23 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 82:23] - node _T_24 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 82:85] - node _T_25 = eq(_T_24, UInt<2>("h01")) @[ahb_to_axi4.scala 82:92] - node _T_26 = and(_T_25, io.ahb.hsel) @[ahb_to_axi4.scala 82:110] - node _T_27 = or(io.ahb.sig.in.hresp, _T_26) @[ahb_to_axi4.scala 82:60] - node _T_28 = eq(_T_27, UInt<1>("h00")) @[ahb_to_axi4.scala 82:38] - node _T_29 = and(_T_23, _T_28) @[ahb_to_axi4.scala 82:36] - cmdbuf_wr_en <= _T_29 @[ahb_to_axi4.scala 82:20] + node _T_13 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 79:72] + node _T_14 = eq(_T_13, UInt<1>("h00")) @[ahb_to_axi4.scala 79:79] + node _T_15 = or(io.ahb.sig.in.hresp, _T_14) @[ahb_to_axi4.scala 79:48] + node _T_16 = eq(io.ahb.hsel, UInt<1>("h00")) @[ahb_to_axi4.scala 79:93] + node _T_17 = or(_T_15, _T_16) @[ahb_to_axi4.scala 79:91] + node _T_18 = bits(_T_17, 0, 0) @[ahb_to_axi4.scala 79:107] + node _T_19 = mux(io.ahb.sig.out.hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 79:124] + node _T_20 = mux(_T_18, UInt<2>("h00"), _T_19) @[ahb_to_axi4.scala 79:26] + buf_nxtstate <= _T_20 @[ahb_to_axi4.scala 79:20] + node _T_21 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 80:24] + node _T_22 = or(_T_21, io.ahb.sig.in.hresp) @[ahb_to_axi4.scala 80:37] + buf_state_en <= _T_22 @[ahb_to_axi4.scala 80:20] + node _T_23 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 81:23] + node _T_24 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 81:85] + node _T_25 = eq(_T_24, UInt<2>("h01")) @[ahb_to_axi4.scala 81:92] + node _T_26 = and(_T_25, io.ahb.hsel) @[ahb_to_axi4.scala 81:110] + node _T_27 = or(io.ahb.sig.in.hresp, _T_26) @[ahb_to_axi4.scala 81:60] + node _T_28 = eq(_T_27, UInt<1>("h00")) @[ahb_to_axi4.scala 81:38] + node _T_29 = and(_T_23, _T_28) @[ahb_to_axi4.scala 81:36] + cmdbuf_wr_en <= _T_29 @[ahb_to_axi4.scala 81:20] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_30 = eq(UInt<2>("h02"), buf_state) @[Conditional.scala 37:30] when _T_30 : @[Conditional.scala 39:67] - node _T_31 = mux(io.ahb.sig.in.hresp, UInt<2>("h00"), UInt<2>("h03")) @[ahb_to_axi4.scala 85:26] - buf_nxtstate <= _T_31 @[ahb_to_axi4.scala 85:20] - node _T_32 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 86:24] - node _T_33 = or(_T_32, io.ahb.sig.in.hresp) @[ahb_to_axi4.scala 86:37] - buf_state_en <= _T_33 @[ahb_to_axi4.scala 86:20] - node _T_34 = eq(io.ahb.sig.in.hresp, UInt<1>("h00")) @[ahb_to_axi4.scala 87:23] - node _T_35 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 87:46] - node _T_36 = and(_T_34, _T_35) @[ahb_to_axi4.scala 87:44] - cmdbuf_wr_en <= _T_36 @[ahb_to_axi4.scala 87:20] + node _T_31 = mux(io.ahb.sig.in.hresp, UInt<2>("h00"), UInt<2>("h03")) @[ahb_to_axi4.scala 84:26] + buf_nxtstate <= _T_31 @[ahb_to_axi4.scala 84:20] + node _T_32 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 85:24] + node _T_33 = or(_T_32, io.ahb.sig.in.hresp) @[ahb_to_axi4.scala 85:37] + buf_state_en <= _T_33 @[ahb_to_axi4.scala 85:20] + node _T_34 = eq(io.ahb.sig.in.hresp, UInt<1>("h00")) @[ahb_to_axi4.scala 86:23] + node _T_35 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 86:46] + node _T_36 = and(_T_34, _T_35) @[ahb_to_axi4.scala 86:44] + cmdbuf_wr_en <= _T_36 @[ahb_to_axi4.scala 86:20] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_37 = eq(UInt<2>("h03"), buf_state) @[Conditional.scala 37:30] when _T_37 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 90:20] - node _T_38 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 91:40] - node _T_39 = and(io.axi.r.valid, _T_38) @[ahb_to_axi4.scala 91:38] - buf_state_en <= _T_39 @[ahb_to_axi4.scala 91:20] - buf_rdata_en <= buf_state_en @[ahb_to_axi4.scala 92:20] - node _T_40 = bits(io.axi.r.bits.resp, 1, 0) @[ahb_to_axi4.scala 93:61] - node _T_41 = orr(_T_40) @[ahb_to_axi4.scala 93:68] - node _T_42 = and(buf_state_en, _T_41) @[ahb_to_axi4.scala 93:41] - buf_read_error_in <= _T_42 @[ahb_to_axi4.scala 93:25] + buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 89:20] + node _T_38 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 90:40] + node _T_39 = and(io.axi.r.valid, _T_38) @[ahb_to_axi4.scala 90:38] + buf_state_en <= _T_39 @[ahb_to_axi4.scala 90:20] + buf_rdata_en <= buf_state_en @[ahb_to_axi4.scala 91:20] + node _T_40 = bits(io.axi.r.bits.resp, 1, 0) @[ahb_to_axi4.scala 92:61] + node _T_41 = orr(_T_40) @[ahb_to_axi4.scala 92:68] + node _T_42 = and(buf_state_en, _T_41) @[ahb_to_axi4.scala 92:41] + buf_read_error_in <= _T_42 @[ahb_to_axi4.scala 92:25] skip @[Conditional.scala 39:67] - node _T_43 = bits(buf_state_en, 0, 0) @[ahb_to_axi4.scala 96:99] + node _T_43 = bits(buf_state_en, 0, 0) @[ahb_to_axi4.scala 95:99] reg _T_44 : UInt, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_43 : @[Reg.scala 28:19] _T_44 <= buf_nxtstate @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_state <= _T_44 @[ahb_to_axi4.scala 96:31] - node _T_45 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 98:54] - node _T_46 = eq(_T_45, UInt<1>("h00")) @[ahb_to_axi4.scala 98:60] + buf_state <= _T_44 @[ahb_to_axi4.scala 95:31] + node _T_45 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 97:54] + node _T_46 = eq(_T_45, UInt<1>("h00")) @[ahb_to_axi4.scala 97:60] node _T_47 = bits(_T_46, 0, 0) @[Bitwise.scala 72:15] node _T_48 = mux(_T_47, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_49 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 98:92] - node _T_50 = dshl(UInt<1>("h01"), _T_49) @[ahb_to_axi4.scala 98:78] - node _T_51 = and(_T_48, _T_50) @[ahb_to_axi4.scala 98:70] - node _T_52 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 99:24] - node _T_53 = eq(_T_52, UInt<1>("h01")) @[ahb_to_axi4.scala 99:30] + node _T_49 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 97:92] + node _T_50 = dshl(UInt<1>("h01"), _T_49) @[ahb_to_axi4.scala 97:78] + node _T_51 = and(_T_48, _T_50) @[ahb_to_axi4.scala 97:70] + node _T_52 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 98:24] + node _T_53 = eq(_T_52, UInt<1>("h01")) @[ahb_to_axi4.scala 98:30] node _T_54 = bits(_T_53, 0, 0) @[Bitwise.scala 72:15] node _T_55 = mux(_T_54, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_56 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 99:62] - node _T_57 = dshl(UInt<2>("h03"), _T_56) @[ahb_to_axi4.scala 99:48] - node _T_58 = and(_T_55, _T_57) @[ahb_to_axi4.scala 99:40] - node _T_59 = or(_T_51, _T_58) @[ahb_to_axi4.scala 98:109] - node _T_60 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 100:24] - node _T_61 = eq(_T_60, UInt<2>("h02")) @[ahb_to_axi4.scala 100:30] + node _T_56 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 98:62] + node _T_57 = dshl(UInt<2>("h03"), _T_56) @[ahb_to_axi4.scala 98:48] + node _T_58 = and(_T_55, _T_57) @[ahb_to_axi4.scala 98:40] + node _T_59 = or(_T_51, _T_58) @[ahb_to_axi4.scala 97:109] + node _T_60 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 99:24] + node _T_61 = eq(_T_60, UInt<2>("h02")) @[ahb_to_axi4.scala 99:30] node _T_62 = bits(_T_61, 0, 0) @[Bitwise.scala 72:15] node _T_63 = mux(_T_62, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_64 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 100:62] - node _T_65 = dshl(UInt<4>("h0f"), _T_64) @[ahb_to_axi4.scala 100:48] - node _T_66 = and(_T_63, _T_65) @[ahb_to_axi4.scala 100:40] - node _T_67 = or(_T_59, _T_66) @[ahb_to_axi4.scala 99:79] - node _T_68 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 101:24] - node _T_69 = eq(_T_68, UInt<2>("h03")) @[ahb_to_axi4.scala 101:30] + node _T_64 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 99:62] + node _T_65 = dshl(UInt<4>("h0f"), _T_64) @[ahb_to_axi4.scala 99:48] + node _T_66 = and(_T_63, _T_65) @[ahb_to_axi4.scala 99:40] + node _T_67 = or(_T_59, _T_66) @[ahb_to_axi4.scala 98:79] + node _T_68 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 100:24] + node _T_69 = eq(_T_68, UInt<2>("h03")) @[ahb_to_axi4.scala 100:30] node _T_70 = bits(_T_69, 0, 0) @[Bitwise.scala 72:15] node _T_71 = mux(_T_70, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_72 = and(_T_71, UInt<8>("h0ff")) @[ahb_to_axi4.scala 101:40] - node _T_73 = or(_T_67, _T_72) @[ahb_to_axi4.scala 100:79] - master_wstrb <= _T_73 @[ahb_to_axi4.scala 98:31] - node _T_74 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 104:80] - node _T_75 = and(ahb_hresp_q, _T_74) @[ahb_to_axi4.scala 104:78] - node _T_76 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 104:98] - node _T_77 = eq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 104:124] - node _T_78 = or(_T_76, _T_77) @[ahb_to_axi4.scala 104:111] - node _T_79 = eq(buf_state, UInt<2>("h02")) @[ahb_to_axi4.scala 104:149] - node _T_80 = eq(buf_state, UInt<2>("h03")) @[ahb_to_axi4.scala 104:168] - node _T_81 = or(_T_79, _T_80) @[ahb_to_axi4.scala 104:156] - node _T_82 = eq(_T_81, UInt<1>("h00")) @[ahb_to_axi4.scala 104:137] - node _T_83 = and(_T_78, _T_82) @[ahb_to_axi4.scala 104:135] - node _T_84 = eq(buf_read_error, UInt<1>("h00")) @[ahb_to_axi4.scala 104:181] - node _T_85 = and(_T_83, _T_84) @[ahb_to_axi4.scala 104:179] - node _T_86 = mux(io.ahb.sig.in.hresp, _T_75, _T_85) @[ahb_to_axi4.scala 104:44] - io.ahb.sig.in.hready <= _T_86 @[ahb_to_axi4.scala 104:38] - node _T_87 = and(io.ahb.sig.in.hready, io.ahb.hreadyin) @[ahb_to_axi4.scala 105:55] - ahb_hready <= _T_87 @[ahb_to_axi4.scala 105:31] + node _T_72 = and(_T_71, UInt<8>("h0ff")) @[ahb_to_axi4.scala 100:40] + node _T_73 = or(_T_67, _T_72) @[ahb_to_axi4.scala 99:79] + master_wstrb <= _T_73 @[ahb_to_axi4.scala 97:31] + node _T_74 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 103:80] + node _T_75 = and(ahb_hresp_q, _T_74) @[ahb_to_axi4.scala 103:78] + node _T_76 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 103:98] + node _T_77 = eq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 103:124] + node _T_78 = or(_T_76, _T_77) @[ahb_to_axi4.scala 103:111] + node _T_79 = eq(buf_state, UInt<2>("h02")) @[ahb_to_axi4.scala 103:149] + node _T_80 = eq(buf_state, UInt<2>("h03")) @[ahb_to_axi4.scala 103:168] + node _T_81 = or(_T_79, _T_80) @[ahb_to_axi4.scala 103:156] + node _T_82 = eq(_T_81, UInt<1>("h00")) @[ahb_to_axi4.scala 103:137] + node _T_83 = and(_T_78, _T_82) @[ahb_to_axi4.scala 103:135] + node _T_84 = eq(buf_read_error, UInt<1>("h00")) @[ahb_to_axi4.scala 103:181] + node _T_85 = and(_T_83, _T_84) @[ahb_to_axi4.scala 103:179] + node _T_86 = mux(io.ahb.sig.in.hresp, _T_75, _T_85) @[ahb_to_axi4.scala 103:44] + io.ahb.sig.in.hready <= _T_86 @[ahb_to_axi4.scala 103:38] + node _T_87 = and(io.ahb.sig.in.hready, io.ahb.hreadyin) @[ahb_to_axi4.scala 104:55] + ahb_hready <= _T_87 @[ahb_to_axi4.scala 104:31] node _T_88 = bits(io.ahb.hsel, 0, 0) @[Bitwise.scala 72:15] node _T_89 = mux(_T_88, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_90 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 106:77] - node _T_91 = and(_T_89, _T_90) @[ahb_to_axi4.scala 106:54] - ahb_htrans_in <= _T_91 @[ahb_to_axi4.scala 106:31] - node _T_92 = bits(buf_rdata, 63, 0) @[ahb_to_axi4.scala 107:50] - io.ahb.sig.in.hrdata <= _T_92 @[ahb_to_axi4.scala 107:38] - node _T_93 = bits(ahb_htrans_q, 1, 0) @[ahb_to_axi4.scala 108:55] - node _T_94 = neq(_T_93, UInt<1>("h00")) @[ahb_to_axi4.scala 108:61] - node _T_95 = neq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 108:83] - node _T_96 = and(_T_94, _T_95) @[ahb_to_axi4.scala 108:70] - node _T_97 = or(ahb_addr_in_dccm, ahb_addr_in_iccm) @[ahb_to_axi4.scala 109:26] - node _T_98 = eq(_T_97, UInt<1>("h00")) @[ahb_to_axi4.scala 109:7] - node _T_99 = and(ahb_addr_in_dccm, ahb_hwrite_q) @[ahb_to_axi4.scala 110:46] - node _T_100 = or(ahb_addr_in_iccm, _T_99) @[ahb_to_axi4.scala 110:26] - node _T_101 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 110:80] - node _T_102 = eq(_T_101, UInt<2>("h02")) @[ahb_to_axi4.scala 110:86] - node _T_103 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 110:109] - node _T_104 = eq(_T_103, UInt<2>("h03")) @[ahb_to_axi4.scala 110:115] - node _T_105 = or(_T_102, _T_104) @[ahb_to_axi4.scala 110:95] - node _T_106 = eq(_T_105, UInt<1>("h00")) @[ahb_to_axi4.scala 110:66] - node _T_107 = and(_T_100, _T_106) @[ahb_to_axi4.scala 110:64] - node _T_108 = or(_T_98, _T_107) @[ahb_to_axi4.scala 109:47] - node _T_109 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 111:20] - node _T_110 = eq(_T_109, UInt<1>("h01")) @[ahb_to_axi4.scala 111:26] - node _T_111 = bits(ahb_haddr_q, 0, 0) @[ahb_to_axi4.scala 111:48] - node _T_112 = and(_T_110, _T_111) @[ahb_to_axi4.scala 111:35] - node _T_113 = or(_T_108, _T_112) @[ahb_to_axi4.scala 110:126] - node _T_114 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 112:20] - node _T_115 = eq(_T_114, UInt<2>("h02")) @[ahb_to_axi4.scala 112:26] - node _T_116 = bits(ahb_haddr_q, 1, 0) @[ahb_to_axi4.scala 112:49] - node _T_117 = orr(_T_116) @[ahb_to_axi4.scala 112:56] - node _T_118 = and(_T_115, _T_117) @[ahb_to_axi4.scala 112:35] - node _T_119 = or(_T_113, _T_118) @[ahb_to_axi4.scala 111:55] - node _T_120 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 113:20] - node _T_121 = eq(_T_120, UInt<2>("h03")) @[ahb_to_axi4.scala 113:26] - node _T_122 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 113:49] - node _T_123 = orr(_T_122) @[ahb_to_axi4.scala 113:56] - node _T_124 = and(_T_121, _T_123) @[ahb_to_axi4.scala 113:35] - node _T_125 = or(_T_119, _T_124) @[ahb_to_axi4.scala 112:61] - node _T_126 = and(_T_96, _T_125) @[ahb_to_axi4.scala 108:94] - node _T_127 = or(_T_126, buf_read_error) @[ahb_to_axi4.scala 113:63] - node _T_128 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 115:20] - node _T_129 = and(ahb_hresp_q, _T_128) @[ahb_to_axi4.scala 115:18] - node _T_130 = or(_T_127, _T_129) @[ahb_to_axi4.scala 114:20] - io.ahb.sig.in.hresp <= _T_130 @[ahb_to_axi4.scala 108:38] - reg _T_131 : UInt, buf_rdata_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 118:66] - _T_131 <= io.axi.r.bits.data @[ahb_to_axi4.scala 118:66] - buf_rdata <= _T_131 @[ahb_to_axi4.scala 118:31] - reg _T_132 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 119:60] - _T_132 <= buf_read_error_in @[ahb_to_axi4.scala 119:60] - buf_read_error <= _T_132 @[ahb_to_axi4.scala 119:31] - reg _T_133 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 122:60] - _T_133 <= io.ahb.sig.in.hresp @[ahb_to_axi4.scala 122:60] - ahb_hresp_q <= _T_133 @[ahb_to_axi4.scala 122:31] - reg _T_134 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 123:60] - _T_134 <= ahb_hready @[ahb_to_axi4.scala 123:60] - ahb_hready_q <= _T_134 @[ahb_to_axi4.scala 123:31] - reg _T_135 : UInt, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 124:60] - _T_135 <= ahb_htrans_in @[ahb_to_axi4.scala 124:60] - ahb_htrans_q <= _T_135 @[ahb_to_axi4.scala 124:31] - reg _T_136 : UInt, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 125:65] - _T_136 <= io.ahb.sig.out.hsize @[ahb_to_axi4.scala 125:65] - ahb_hsize_q <= _T_136 @[ahb_to_axi4.scala 125:31] - reg _T_137 : UInt<1>, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 126:65] - _T_137 <= io.ahb.sig.out.hwrite @[ahb_to_axi4.scala 126:65] - ahb_hwrite_q <= _T_137 @[ahb_to_axi4.scala 126:31] - reg _T_138 : UInt, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 127:65] - _T_138 <= io.ahb.sig.out.haddr @[ahb_to_axi4.scala 127:65] - ahb_haddr_q <= _T_138 @[ahb_to_axi4.scala 127:31] - node _T_139 = bits(io.ahb.sig.out.htrans, 1, 1) @[ahb_to_axi4.scala 130:85] - node _T_140 = and(ahb_hready, _T_139) @[ahb_to_axi4.scala 130:62] - node _T_141 = and(io.bus_clk_en, _T_140) @[ahb_to_axi4.scala 130:48] - ahb_bus_addr_clk_en <= _T_141 @[ahb_to_axi4.scala 130:31] - node _T_142 = and(io.bus_clk_en, buf_rdata_en) @[ahb_to_axi4.scala 131:48] - buf_rdata_clk_en <= _T_142 @[ahb_to_axi4.scala 131:31] + node _T_90 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 105:77] + node _T_91 = and(_T_89, _T_90) @[ahb_to_axi4.scala 105:54] + ahb_htrans_in <= _T_91 @[ahb_to_axi4.scala 105:31] + node _T_92 = bits(buf_rdata, 63, 0) @[ahb_to_axi4.scala 106:50] + io.ahb.sig.in.hrdata <= _T_92 @[ahb_to_axi4.scala 106:38] + node _T_93 = bits(ahb_htrans_q, 1, 0) @[ahb_to_axi4.scala 107:55] + node _T_94 = neq(_T_93, UInt<1>("h00")) @[ahb_to_axi4.scala 107:61] + node _T_95 = neq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 107:83] + node _T_96 = and(_T_94, _T_95) @[ahb_to_axi4.scala 107:70] + node _T_97 = or(ahb_addr_in_dccm, ahb_addr_in_iccm) @[ahb_to_axi4.scala 108:26] + node _T_98 = eq(_T_97, UInt<1>("h00")) @[ahb_to_axi4.scala 108:7] + node _T_99 = and(ahb_addr_in_dccm, ahb_hwrite_q) @[ahb_to_axi4.scala 109:46] + node _T_100 = or(ahb_addr_in_iccm, _T_99) @[ahb_to_axi4.scala 109:26] + node _T_101 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 109:80] + node _T_102 = eq(_T_101, UInt<2>("h02")) @[ahb_to_axi4.scala 109:86] + node _T_103 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 109:109] + node _T_104 = eq(_T_103, UInt<2>("h03")) @[ahb_to_axi4.scala 109:115] + node _T_105 = or(_T_102, _T_104) @[ahb_to_axi4.scala 109:95] + node _T_106 = eq(_T_105, UInt<1>("h00")) @[ahb_to_axi4.scala 109:66] + node _T_107 = and(_T_100, _T_106) @[ahb_to_axi4.scala 109:64] + node _T_108 = or(_T_98, _T_107) @[ahb_to_axi4.scala 108:47] + node _T_109 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 110:20] + node _T_110 = eq(_T_109, UInt<1>("h01")) @[ahb_to_axi4.scala 110:26] + node _T_111 = bits(ahb_haddr_q, 0, 0) @[ahb_to_axi4.scala 110:48] + node _T_112 = and(_T_110, _T_111) @[ahb_to_axi4.scala 110:35] + node _T_113 = or(_T_108, _T_112) @[ahb_to_axi4.scala 109:126] + node _T_114 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 111:20] + node _T_115 = eq(_T_114, UInt<2>("h02")) @[ahb_to_axi4.scala 111:26] + node _T_116 = bits(ahb_haddr_q, 1, 0) @[ahb_to_axi4.scala 111:49] + node _T_117 = orr(_T_116) @[ahb_to_axi4.scala 111:56] + node _T_118 = and(_T_115, _T_117) @[ahb_to_axi4.scala 111:35] + node _T_119 = or(_T_113, _T_118) @[ahb_to_axi4.scala 110:55] + node _T_120 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 112:20] + node _T_121 = eq(_T_120, UInt<2>("h03")) @[ahb_to_axi4.scala 112:26] + node _T_122 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 112:49] + node _T_123 = orr(_T_122) @[ahb_to_axi4.scala 112:56] + node _T_124 = and(_T_121, _T_123) @[ahb_to_axi4.scala 112:35] + node _T_125 = or(_T_119, _T_124) @[ahb_to_axi4.scala 111:61] + node _T_126 = and(_T_96, _T_125) @[ahb_to_axi4.scala 107:94] + node _T_127 = or(_T_126, buf_read_error) @[ahb_to_axi4.scala 112:63] + node _T_128 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 114:20] + node _T_129 = and(ahb_hresp_q, _T_128) @[ahb_to_axi4.scala 114:18] + node _T_130 = or(_T_127, _T_129) @[ahb_to_axi4.scala 113:20] + io.ahb.sig.in.hresp <= _T_130 @[ahb_to_axi4.scala 107:38] + reg _T_131 : UInt, buf_rdata_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 117:66] + _T_131 <= io.axi.r.bits.data @[ahb_to_axi4.scala 117:66] + buf_rdata <= _T_131 @[ahb_to_axi4.scala 117:31] + reg _T_132 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 118:60] + _T_132 <= buf_read_error_in @[ahb_to_axi4.scala 118:60] + buf_read_error <= _T_132 @[ahb_to_axi4.scala 118:31] + reg _T_133 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 121:60] + _T_133 <= io.ahb.sig.in.hresp @[ahb_to_axi4.scala 121:60] + ahb_hresp_q <= _T_133 @[ahb_to_axi4.scala 121:31] + reg _T_134 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 122:60] + _T_134 <= ahb_hready @[ahb_to_axi4.scala 122:60] + ahb_hready_q <= _T_134 @[ahb_to_axi4.scala 122:31] + reg _T_135 : UInt, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 123:60] + _T_135 <= ahb_htrans_in @[ahb_to_axi4.scala 123:60] + ahb_htrans_q <= _T_135 @[ahb_to_axi4.scala 123:31] + reg _T_136 : UInt, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 124:65] + _T_136 <= io.ahb.sig.out.hsize @[ahb_to_axi4.scala 124:65] + ahb_hsize_q <= _T_136 @[ahb_to_axi4.scala 124:31] + reg _T_137 : UInt<1>, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 125:65] + _T_137 <= io.ahb.sig.out.hwrite @[ahb_to_axi4.scala 125:65] + ahb_hwrite_q <= _T_137 @[ahb_to_axi4.scala 125:31] + reg _T_138 : UInt, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 126:65] + _T_138 <= io.ahb.sig.out.haddr @[ahb_to_axi4.scala 126:65] + ahb_haddr_q <= _T_138 @[ahb_to_axi4.scala 126:31] + node _T_139 = bits(io.ahb.sig.out.htrans, 1, 1) @[ahb_to_axi4.scala 129:85] + node _T_140 = and(ahb_hready, _T_139) @[ahb_to_axi4.scala 129:62] + node _T_141 = and(io.bus_clk_en, _T_140) @[ahb_to_axi4.scala 129:48] + ahb_bus_addr_clk_en <= _T_141 @[ahb_to_axi4.scala 129:31] + node _T_142 = and(io.bus_clk_en, buf_rdata_en) @[ahb_to_axi4.scala 130:48] + buf_rdata_clk_en <= _T_142 @[ahb_to_axi4.scala 130:31] inst rvclkhdr of rvclkhdr_879 @[lib.scala 343:22] rvclkhdr.clock <= clock rvclkhdr.reset <= reset rvclkhdr.io.clk <= clock @[lib.scala 344:17] rvclkhdr.io.en <= io.bus_clk_en @[lib.scala 345:16] rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahb_clk <= rvclkhdr.io.l1clk @[ahb_to_axi4.scala 133:31] + ahb_clk <= rvclkhdr.io.l1clk @[ahb_to_axi4.scala 132:31] inst rvclkhdr_1 of rvclkhdr_880 @[lib.scala 343:22] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] rvclkhdr_1.io.en <= ahb_bus_addr_clk_en @[lib.scala 345:16] rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahb_addr_clk <= rvclkhdr_1.io.l1clk @[ahb_to_axi4.scala 134:31] + ahb_addr_clk <= rvclkhdr_1.io.l1clk @[ahb_to_axi4.scala 133:31] inst rvclkhdr_2 of rvclkhdr_881 @[lib.scala 343:22] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset rvclkhdr_2.io.clk <= clock @[lib.scala 344:17] rvclkhdr_2.io.en <= buf_rdata_clk_en @[lib.scala 345:16] rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - buf_rdata_clk <= rvclkhdr_2.io.l1clk @[ahb_to_axi4.scala 135:31] - node _T_143 = and(io.axi.aw.valid, io.axi.aw.ready) @[ahb_to_axi4.scala 137:53] - node _T_144 = and(io.axi.ar.valid, io.axi.ar.ready) @[ahb_to_axi4.scala 137:91] - node _T_145 = or(_T_143, _T_144) @[ahb_to_axi4.scala 137:72] - node _T_146 = eq(cmdbuf_wr_en, UInt<1>("h00")) @[ahb_to_axi4.scala 137:113] - node _T_147 = and(_T_145, _T_146) @[ahb_to_axi4.scala 137:111] - node _T_148 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 137:153] - node _T_149 = and(io.ahb.sig.in.hresp, _T_148) @[ahb_to_axi4.scala 137:151] - node _T_150 = or(_T_147, _T_149) @[ahb_to_axi4.scala 137:128] - cmdbuf_rst <= _T_150 @[ahb_to_axi4.scala 137:31] - node _T_151 = and(io.axi.aw.valid, io.axi.aw.ready) @[ahb_to_axi4.scala 138:67] - node _T_152 = and(io.axi.ar.valid, io.axi.ar.ready) @[ahb_to_axi4.scala 138:105] - node _T_153 = or(_T_151, _T_152) @[ahb_to_axi4.scala 138:86] - node _T_154 = eq(_T_153, UInt<1>("h00")) @[ahb_to_axi4.scala 138:48] - node _T_155 = and(cmdbuf_vld, _T_154) @[ahb_to_axi4.scala 138:46] - cmdbuf_full <= _T_155 @[ahb_to_axi4.scala 138:31] - node _T_156 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 140:86] - node _T_157 = mux(_T_156, UInt<1>("h01"), cmdbuf_vld) @[ahb_to_axi4.scala 140:66] - node _T_158 = eq(cmdbuf_rst, UInt<1>("h00")) @[ahb_to_axi4.scala 140:110] - node _T_159 = and(_T_157, _T_158) @[ahb_to_axi4.scala 140:108] - reg _T_160 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 140:61] - _T_160 <= _T_159 @[ahb_to_axi4.scala 140:61] - cmdbuf_vld <= _T_160 @[ahb_to_axi4.scala 140:31] - node _T_161 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 144:53] + buf_rdata_clk <= rvclkhdr_2.io.l1clk @[ahb_to_axi4.scala 134:31] + node _T_143 = and(io.axi.aw.valid, io.axi.aw.ready) @[ahb_to_axi4.scala 136:53] + node _T_144 = and(io.axi.ar.valid, io.axi.ar.ready) @[ahb_to_axi4.scala 136:91] + node _T_145 = or(_T_143, _T_144) @[ahb_to_axi4.scala 136:72] + node _T_146 = eq(cmdbuf_wr_en, UInt<1>("h00")) @[ahb_to_axi4.scala 136:113] + node _T_147 = and(_T_145, _T_146) @[ahb_to_axi4.scala 136:111] + node _T_148 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 136:153] + node _T_149 = and(io.ahb.sig.in.hresp, _T_148) @[ahb_to_axi4.scala 136:151] + node _T_150 = or(_T_147, _T_149) @[ahb_to_axi4.scala 136:128] + cmdbuf_rst <= _T_150 @[ahb_to_axi4.scala 136:31] + node _T_151 = and(io.axi.aw.valid, io.axi.aw.ready) @[ahb_to_axi4.scala 137:67] + node _T_152 = and(io.axi.ar.valid, io.axi.ar.ready) @[ahb_to_axi4.scala 137:105] + node _T_153 = or(_T_151, _T_152) @[ahb_to_axi4.scala 137:86] + node _T_154 = eq(_T_153, UInt<1>("h00")) @[ahb_to_axi4.scala 137:48] + node _T_155 = and(cmdbuf_vld, _T_154) @[ahb_to_axi4.scala 137:46] + cmdbuf_full <= _T_155 @[ahb_to_axi4.scala 137:31] + node _T_156 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 139:86] + node _T_157 = mux(_T_156, UInt<1>("h01"), cmdbuf_vld) @[ahb_to_axi4.scala 139:66] + node _T_158 = eq(cmdbuf_rst, UInt<1>("h00")) @[ahb_to_axi4.scala 139:110] + node _T_159 = and(_T_157, _T_158) @[ahb_to_axi4.scala 139:108] + reg _T_160 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 139:61] + _T_160 <= _T_159 @[ahb_to_axi4.scala 139:61] + cmdbuf_vld <= _T_160 @[ahb_to_axi4.scala 139:31] + node _T_161 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 143:53] reg _T_162 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_161 : @[Reg.scala 28:19] _T_162 <= ahb_hwrite_q @[Reg.scala 28:23] skip @[Reg.scala 28:19] - cmdbuf_write <= _T_162 @[ahb_to_axi4.scala 143:31] - node _T_163 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 147:52] + cmdbuf_write <= _T_162 @[ahb_to_axi4.scala 142:31] + node _T_163 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 146:52] reg _T_164 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_163 : @[Reg.scala 28:19] _T_164 <= ahb_hsize_q @[Reg.scala 28:23] skip @[Reg.scala 28:19] - cmdbuf_size <= _T_164 @[ahb_to_axi4.scala 146:31] - node _T_165 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 150:53] + cmdbuf_size <= _T_164 @[ahb_to_axi4.scala 145:31] + node _T_165 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 149:53] reg _T_166 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_165 : @[Reg.scala 28:19] _T_166 <= master_wstrb @[Reg.scala 28:23] skip @[Reg.scala 28:19] - cmdbuf_wstrb <= _T_166 @[ahb_to_axi4.scala 149:31] - node _T_167 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 153:57] + cmdbuf_wstrb <= _T_166 @[ahb_to_axi4.scala 148:31] + node _T_167 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 152:57] inst rvclkhdr_3 of rvclkhdr_882 @[lib.scala 368:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset @@ -113832,8 +113822,8 @@ circuit quasar_wrapper : rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_168 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_168 <= ahb_haddr_q @[lib.scala 374:16] - cmdbuf_addr <= _T_168 @[ahb_to_axi4.scala 153:15] - node _T_169 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 154:68] + cmdbuf_addr <= _T_168 @[ahb_to_axi4.scala 152:15] + node _T_169 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 153:68] inst rvclkhdr_4 of rvclkhdr_883 @[lib.scala 368:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset @@ -113842,1097 +113832,1098 @@ circuit quasar_wrapper : rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_170 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_170 <= io.ahb.sig.out.hwdata @[lib.scala 374:16] - cmdbuf_wdata <= _T_170 @[ahb_to_axi4.scala 154:16] - node _T_171 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 157:42] - io.axi.aw.valid <= _T_171 @[ahb_to_axi4.scala 157:28] - io.axi.aw.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 158:33] - io.axi.aw.bits.addr <= cmdbuf_addr @[ahb_to_axi4.scala 159:33] - node _T_172 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 160:59] + cmdbuf_wdata <= _T_170 @[ahb_to_axi4.scala 153:16] + node _T_171 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 156:42] + io.axi.aw.valid <= _T_171 @[ahb_to_axi4.scala 156:28] + io.axi.aw.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 157:33] + io.axi.aw.bits.addr <= cmdbuf_addr @[ahb_to_axi4.scala 158:33] + node _T_172 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 159:59] node _T_173 = cat(UInt<1>("h00"), _T_172) @[Cat.scala 29:58] - io.axi.aw.bits.size <= _T_173 @[ahb_to_axi4.scala 160:33] + io.axi.aw.bits.size <= _T_173 @[ahb_to_axi4.scala 159:33] node _T_174 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - io.axi.aw.bits.prot <= _T_174 @[ahb_to_axi4.scala 161:33] + io.axi.aw.bits.prot <= _T_174 @[ahb_to_axi4.scala 160:33] node _T_175 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - io.axi.aw.bits.len <= _T_175 @[ahb_to_axi4.scala 162:33] - io.axi.aw.bits.burst <= UInt<1>("h01") @[ahb_to_axi4.scala 163:33] - node _T_176 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 165:42] - io.axi.w.valid <= _T_176 @[ahb_to_axi4.scala 165:28] - io.axi.w.bits.data <= cmdbuf_wdata @[ahb_to_axi4.scala 166:33] - io.axi.w.bits.strb <= cmdbuf_wstrb @[ahb_to_axi4.scala 167:33] - io.axi.w.bits.last <= UInt<1>("h01") @[ahb_to_axi4.scala 168:33] - io.axi.b.ready <= UInt<1>("h01") @[ahb_to_axi4.scala 170:28] - node _T_177 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 172:44] - node _T_178 = and(cmdbuf_vld, _T_177) @[ahb_to_axi4.scala 172:42] - io.axi.ar.valid <= _T_178 @[ahb_to_axi4.scala 172:28] - io.axi.ar.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 173:33] - io.axi.ar.bits.addr <= cmdbuf_addr @[ahb_to_axi4.scala 174:33] - node _T_179 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 175:59] + io.axi.aw.bits.len <= _T_175 @[ahb_to_axi4.scala 161:33] + io.axi.aw.bits.burst <= UInt<1>("h01") @[ahb_to_axi4.scala 162:33] + node _T_176 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 164:42] + io.axi.w.valid <= _T_176 @[ahb_to_axi4.scala 164:28] + io.axi.w.bits.data <= cmdbuf_wdata @[ahb_to_axi4.scala 165:33] + io.axi.w.bits.strb <= cmdbuf_wstrb @[ahb_to_axi4.scala 166:33] + io.axi.w.bits.last <= UInt<1>("h01") @[ahb_to_axi4.scala 167:33] + io.axi.b.ready <= UInt<1>("h01") @[ahb_to_axi4.scala 169:28] + node _T_177 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 171:44] + node _T_178 = and(cmdbuf_vld, _T_177) @[ahb_to_axi4.scala 171:42] + io.axi.ar.valid <= _T_178 @[ahb_to_axi4.scala 171:28] + io.axi.ar.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 172:33] + io.axi.ar.bits.addr <= cmdbuf_addr @[ahb_to_axi4.scala 173:33] + node _T_179 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 174:59] node _T_180 = cat(UInt<1>("h00"), _T_179) @[Cat.scala 29:58] - io.axi.ar.bits.size <= _T_180 @[ahb_to_axi4.scala 175:33] + io.axi.ar.bits.size <= _T_180 @[ahb_to_axi4.scala 174:33] node _T_181 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - io.axi.ar.bits.prot <= _T_181 @[ahb_to_axi4.scala 176:33] + io.axi.ar.bits.prot <= _T_181 @[ahb_to_axi4.scala 175:33] node _T_182 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - io.axi.ar.bits.len <= _T_182 @[ahb_to_axi4.scala 177:33] - io.axi.ar.bits.burst <= UInt<1>("h01") @[ahb_to_axi4.scala 178:33] - io.axi.r.ready <= UInt<1>("h01") @[ahb_to_axi4.scala 180:28] + io.axi.ar.bits.len <= _T_182 @[ahb_to_axi4.scala 176:33] + io.axi.ar.bits.burst <= UInt<1>("h01") @[ahb_to_axi4.scala 177:33] + io.axi.r.ready <= UInt<1>("h01") @[ahb_to_axi4.scala 179:28] inst rvclkhdr_5 of rvclkhdr_884 @[lib.scala 343:22] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset rvclkhdr_5.io.clk <= clock @[lib.scala 344:17] rvclkhdr_5.io.en <= io.bus_clk_en @[lib.scala 345:16] rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - bus_clk <= rvclkhdr_5.io.l1clk @[ahb_to_axi4.scala 181:27] + bus_clk <= rvclkhdr_5.io.l1clk @[ahb_to_axi4.scala 180:27] module quasar : input clock : Clock input reset : AsyncReset output io : {lsu_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ifu_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, sb_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dma_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, lsu_ahb : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, ifu_ahb : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, sb_ahb : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, dma_ahb : {flip sig : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, flip hsel : UInt<1>, flip hreadyin : UInt<1>}, flip dbg_rst_l : AsyncReset, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, core_rst_l : AsyncReset, rv_trace_pkt : {rv_i_valid_ip : UInt<2>, rv_i_insn_ip : UInt<32>, rv_i_address_ip : UInt<32>, rv_i_exception_ip : UInt<2>, rv_i_ecause_ip : UInt<5>, rv_i_interrupt_ip : UInt<2>, rv_i_tval_ip : UInt<32>}, dccm_clk_override : UInt<1>, icm_clk_override : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, flip dccm : {flip wren : UInt<1>, flip rden : UInt<1>, flip wr_addr_lo : UInt<16>, flip wr_addr_hi : UInt<16>, flip rd_addr_lo : UInt<16>, flip rd_addr_hi : UInt<16>, flip wr_data_lo : UInt<39>, flip wr_data_hi : UInt<39>, rd_data_lo : UInt<39>, rd_data_hi : UInt<39>}, ic : {rw_addr : UInt<31>, tag_valid : UInt<2>, wr_en : UInt<2>, rd_en : UInt<1>, wr_data : UInt<71>[2], debug_wr_data : UInt<71>, debug_addr : UInt<10>, flip rd_data : UInt<64>, flip debug_rd_data : UInt<71>, flip tag_debug_rd_data : UInt<26>, flip eccerr : UInt<2>, flip parerr : UInt<2>, flip rd_hit : UInt<2>, flip tag_perr : UInt<1>, debug_rd_en : UInt<1>, debug_wr_en : UInt<1>, debug_tag_array : UInt<1>, debug_way : UInt<2>, premux_data : UInt<64>, sel_premux_data : UInt<1>}, iccm : {rw_addr : UInt<15>, buf_correct_ecc : UInt<1>, correction_state : UInt<1>, wren : UInt<1>, rden : UInt<1>, wr_size : UInt<3>, wr_data : UInt<78>, flip rd_data : UInt<64>, flip rd_data_ecc : UInt<78>}, flip lsu_bus_clk_en : UInt<1>, flip ifu_bus_clk_en : UInt<1>, flip dbg_bus_clk_en : UInt<1>, flip dma_bus_clk_en : UInt<1>, flip dmi_reg_en : UInt<1>, flip dmi_reg_addr : UInt<7>, flip dmi_reg_wr_en : UInt<1>, flip dmi_reg_wdata : UInt<32>, dmi_reg_rdata : UInt<32>, flip dmi_hard_reset : UInt<1>, flip extintsrc_req : UInt<31>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip scan_mode : UInt<1>} - inst ifu of ifu @[quasar.scala 72:19] + inst ifu of ifu @[quasar.scala 74:19] ifu.clock <= clock ifu.reset <= reset - inst dec of dec @[quasar.scala 73:19] + inst dec of dec @[quasar.scala 75:19] dec.clock <= clock dec.reset <= reset - inst dbg of dbg @[quasar.scala 74:19] + inst dbg of dbg @[quasar.scala 76:19] dbg.clock <= clock dbg.reset <= reset - inst exu of exu @[quasar.scala 75:19] + inst exu of exu @[quasar.scala 77:19] exu.clock <= clock exu.reset <= reset - inst lsu of lsu @[quasar.scala 76:19] + inst lsu of lsu @[quasar.scala 78:19] lsu.clock <= clock lsu.reset <= reset - inst pic_ctrl_inst of pic_ctrl @[quasar.scala 77:29] + inst pic_ctrl_inst of pic_ctrl @[quasar.scala 79:29] pic_ctrl_inst.clock <= clock pic_ctrl_inst.reset <= reset - inst dma_ctrl of dma_ctrl @[quasar.scala 78:24] + inst dma_ctrl of dma_ctrl @[quasar.scala 80:24] dma_ctrl.clock <= clock dma_ctrl.reset <= reset - node _T = asUInt(reset) @[quasar.scala 80:33] - node _T_1 = bits(dbg.io.dbg_core_rst_l, 0, 0) @[quasar.scala 80:67] - node _T_2 = or(_T_1, io.scan_mode) @[quasar.scala 80:70] - node _T_3 = and(_T, _T_2) @[quasar.scala 80:36] - node _T_4 = asAsyncReset(_T_3) @[quasar.scala 80:99] - io.core_rst_l <= _T_4 @[quasar.scala 80:17] - node _T_5 = eq(dec.io.dec_pause_state_cg, UInt<1>("h00")) @[quasar.scala 81:23] - node _T_6 = or(_T_5, dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r) @[quasar.scala 81:50] - node active_state = or(_T_6, dec.io.dec_tlu_misc_clk_override) @[quasar.scala 81:98] + node _T = asUInt(reset) @[quasar.scala 82:33] + node _T_1 = bits(dbg.io.dbg_core_rst_l, 0, 0) @[quasar.scala 82:67] + node _T_2 = or(_T_1, io.scan_mode) @[quasar.scala 82:70] + node _T_3 = and(_T, _T_2) @[quasar.scala 82:36] + node _T_4 = asAsyncReset(_T_3) @[quasar.scala 82:99] + io.core_rst_l <= _T_4 @[quasar.scala 82:17] + node _T_5 = eq(dec.io.dec_pause_state_cg, UInt<1>("h00")) @[quasar.scala 83:23] + node _T_6 = or(_T_5, dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r) @[quasar.scala 83:50] + node active_state = or(_T_6, dec.io.dec_tlu_misc_clk_override) @[quasar.scala 83:98] inst rvclkhdr of rvclkhdr_847 @[lib.scala 343:22] rvclkhdr.clock <= clock rvclkhdr.reset <= reset rvclkhdr.io.clk <= clock @[lib.scala 344:17] rvclkhdr.io.en <= UInt<1>("h01") @[lib.scala 345:16] rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - node _T_7 = bits(active_state, 0, 0) @[quasar.scala 83:49] + node _T_7 = bits(active_state, 0, 0) @[quasar.scala 85:49] inst rvclkhdr_1 of rvclkhdr_848 @[lib.scala 343:22] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] rvclkhdr_1.io.en <= _T_7 @[lib.scala 345:16] rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - node core_dbg_cmd_done = or(dma_ctrl.io.dma_dbg_cmd_done, dec.io.dec_dbg_cmd_done) @[quasar.scala 84:56] - node core_dbg_cmd_fail = or(dma_ctrl.io.dma_dbg_cmd_fail, dec.io.dec_dbg_cmd_fail) @[quasar.scala 85:56] - node core_dbg_rddata = mux(dma_ctrl.io.dma_dbg_cmd_done, dma_ctrl.io.dma_dbg_rddata, dec.io.dec_dbg_rddata) @[quasar.scala 86:28] - ifu.io.ifu_dec.dec_bp.dec_tlu_bpred_disable <= dec.io.ifu_dec.dec_bp.dec_tlu_bpred_disable @[quasar.scala 89:18] - ifu.io.ifu_dec.dec_bp.dec_tlu_flush_leak_one_wb <= dec.io.ifu_dec.dec_bp.dec_tlu_flush_leak_one_wb @[quasar.scala 89:18] - ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.middle <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.middle @[quasar.scala 89:18] - ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.way <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.way @[quasar.scala 89:18] - ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_start_error <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_start_error @[quasar.scala 89:18] - ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_error <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_error @[quasar.scala 89:18] - ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.hist <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.hist @[quasar.scala 89:18] - ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.valid <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.valid @[quasar.scala 89:18] - dec.io.ifu_dec.dec_ifc.ifu_pmu_fetch_stall <= ifu.io.ifu_dec.dec_ifc.ifu_pmu_fetch_stall @[quasar.scala 89:18] - ifu.io.ifu_dec.dec_ifc.dec_tlu_mrac_ff <= dec.io.ifu_dec.dec_ifc.dec_tlu_mrac_ff @[quasar.scala 89:18] - ifu.io.ifu_dec.dec_ifc.dec_tlu_flush_noredir_wb <= dec.io.ifu_dec.dec_ifc.dec_tlu_flush_noredir_wb @[quasar.scala 89:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_miss_state_idle <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_miss_state_idle @[quasar.scala 89:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data_valid <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data_valid @[quasar.scala 89:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data @[quasar.scala 89:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err @[quasar.scala 89:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_ic_error_start <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_ic_error_start @[quasar.scala 89:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_trxn <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_trxn @[quasar.scala 89:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_busy <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_busy @[quasar.scala 89:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_error <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_error @[quasar.scala 89:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_hit <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_hit @[quasar.scala 89:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_miss <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_miss @[quasar.scala 89:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable @[quasar.scala 89:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid @[quasar.scala 89:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid @[quasar.scala 89:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics @[quasar.scala 89:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata @[quasar.scala 89:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_fence_i_wb <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_fence_i_wb @[quasar.scala 89:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt @[quasar.scala 89:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_i0_commit_cmt <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_i0_commit_cmt @[quasar.scala 89:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_flush_err_wb <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_flush_err_wb @[quasar.scala 89:18] - dec.io.ifu_dec.dec_aln.ifu_pmu_instr_aligned <= ifu.io.ifu_dec.dec_aln.ifu_pmu_instr_aligned @[quasar.scala 89:18] - dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.ret <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.ret @[quasar.scala 89:18] - dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.way <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.way @[quasar.scala 89:18] - dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.prett <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.prett @[quasar.scala 89:18] - dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.bank <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.bank @[quasar.scala 89:18] - dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_start_error <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_start_error @[quasar.scala 89:18] - dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_error <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_error @[quasar.scala 89:18] - dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.hist <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.hist @[quasar.scala 89:18] - dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.toffset <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.toffset @[quasar.scala 89:18] - dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.valid <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.valid @[quasar.scala 89:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc4 <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc4 @[quasar.scala 89:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc @[quasar.scala 89:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_instr <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_instr @[quasar.scala 89:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_valid <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_valid @[quasar.scala 89:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_btag <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_btag @[quasar.scala 89:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_fghr <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_fghr @[quasar.scala 89:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_index <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_index @[quasar.scala 89:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_dbecc <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_dbecc @[quasar.scala 89:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_f1 <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_f1 @[quasar.scala 89:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_type <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_type @[quasar.scala 89:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf @[quasar.scala 89:18] - dec.io.ifu_dec.dec_aln.aln_dec.ifu_i0_cinst <= ifu.io.ifu_dec.dec_aln.aln_dec.ifu_i0_cinst @[quasar.scala 89:18] - ifu.io.ifu_dec.dec_aln.aln_dec.dec_i0_decode_d <= dec.io.ifu_dec.dec_aln.aln_dec.dec_i0_decode_d @[quasar.scala 89:18] - ifu.reset <= io.core_rst_l @[quasar.scala 91:13] - ifu.io.scan_mode <= io.scan_mode @[quasar.scala 92:20] - ifu.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 93:19] - ifu.io.active_clk <= rvclkhdr_1.io.l1clk @[quasar.scala 94:21] - ifu.io.exu_flush_final <= dec.io.exu_flush_final @[quasar.scala 96:26] - ifu.io.exu_flush_path_final <= exu.io.exu_flush_path_final @[quasar.scala 97:31] - ifu.io.ifu_bus_clk_en <= io.ifu_bus_clk_en @[quasar.scala 99:25] - ifu.io.ifu_dma.dma_mem_ctl.dma_mem_tag <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_tag @[quasar.scala 100:18] - ifu.io.ifu_dma.dma_mem_ctl.dma_mem_wdata <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_wdata @[quasar.scala 100:18] - ifu.io.ifu_dma.dma_mem_ctl.dma_mem_write <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_write @[quasar.scala 100:18] - ifu.io.ifu_dma.dma_mem_ctl.dma_mem_sz <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_sz @[quasar.scala 100:18] - ifu.io.ifu_dma.dma_mem_ctl.dma_mem_addr <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_addr @[quasar.scala 100:18] - ifu.io.ifu_dma.dma_mem_ctl.dma_iccm_req <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_iccm_req @[quasar.scala 100:18] - ifu.io.ifu_dma.dma_ifc.dma_iccm_stall_any <= dma_ctrl.io.ifu_dma.dma_ifc.dma_iccm_stall_any @[quasar.scala 100:18] - io.ic.sel_premux_data <= ifu.io.ic.sel_premux_data @[quasar.scala 101:13] - io.ic.premux_data <= ifu.io.ic.premux_data @[quasar.scala 101:13] - io.ic.debug_way <= ifu.io.ic.debug_way @[quasar.scala 101:13] - io.ic.debug_tag_array <= ifu.io.ic.debug_tag_array @[quasar.scala 101:13] - io.ic.debug_wr_en <= ifu.io.ic.debug_wr_en @[quasar.scala 101:13] - io.ic.debug_rd_en <= ifu.io.ic.debug_rd_en @[quasar.scala 101:13] - ifu.io.ic.tag_perr <= io.ic.tag_perr @[quasar.scala 101:13] - ifu.io.ic.rd_hit <= io.ic.rd_hit @[quasar.scala 101:13] - ifu.io.ic.parerr <= io.ic.parerr @[quasar.scala 101:13] - ifu.io.ic.eccerr <= io.ic.eccerr @[quasar.scala 101:13] - ifu.io.ic.tag_debug_rd_data <= io.ic.tag_debug_rd_data @[quasar.scala 101:13] - ifu.io.ic.debug_rd_data <= io.ic.debug_rd_data @[quasar.scala 101:13] - ifu.io.ic.rd_data <= io.ic.rd_data @[quasar.scala 101:13] - io.ic.debug_addr <= ifu.io.ic.debug_addr @[quasar.scala 101:13] - io.ic.debug_wr_data <= ifu.io.ic.debug_wr_data @[quasar.scala 101:13] - io.ic.wr_data[0] <= ifu.io.ic.wr_data[0] @[quasar.scala 101:13] - io.ic.wr_data[1] <= ifu.io.ic.wr_data[1] @[quasar.scala 101:13] - io.ic.rd_en <= ifu.io.ic.rd_en @[quasar.scala 101:13] - io.ic.wr_en <= ifu.io.ic.wr_en @[quasar.scala 101:13] - io.ic.tag_valid <= ifu.io.ic.tag_valid @[quasar.scala 101:13] - io.ic.rw_addr <= ifu.io.ic.rw_addr @[quasar.scala 101:13] - ifu.io.iccm.rd_data_ecc <= io.iccm.rd_data_ecc @[quasar.scala 102:15] - ifu.io.iccm.rd_data <= io.iccm.rd_data @[quasar.scala 102:15] - io.iccm.wr_data <= ifu.io.iccm.wr_data @[quasar.scala 102:15] - io.iccm.wr_size <= ifu.io.iccm.wr_size @[quasar.scala 102:15] - io.iccm.rden <= ifu.io.iccm.rden @[quasar.scala 102:15] - io.iccm.wren <= ifu.io.iccm.wren @[quasar.scala 102:15] - io.iccm.correction_state <= ifu.io.iccm.correction_state @[quasar.scala 102:15] - io.iccm.buf_correct_ecc <= ifu.io.iccm.buf_correct_ecc @[quasar.scala 102:15] - io.iccm.rw_addr <= ifu.io.iccm.rw_addr @[quasar.scala 102:15] - ifu.io.exu_ifu.exu_bp.exu_mp_btag <= exu.io.exu_bp.exu_mp_btag @[quasar.scala 103:25] - ifu.io.exu_ifu.exu_bp.exu_mp_index <= exu.io.exu_bp.exu_mp_index @[quasar.scala 103:25] - ifu.io.exu_ifu.exu_bp.exu_mp_fghr <= exu.io.exu_bp.exu_mp_fghr @[quasar.scala 103:25] - ifu.io.exu_ifu.exu_bp.exu_mp_eghr <= exu.io.exu_bp.exu_mp_eghr @[quasar.scala 103:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.way <= exu.io.exu_bp.exu_mp_pkt.bits.way @[quasar.scala 103:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pja <= exu.io.exu_bp.exu_mp_pkt.bits.pja @[quasar.scala 103:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pret <= exu.io.exu_bp.exu_mp_pkt.bits.pret @[quasar.scala 103:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pcall <= exu.io.exu_bp.exu_mp_pkt.bits.pcall @[quasar.scala 103:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.prett <= exu.io.exu_bp.exu_mp_pkt.bits.prett @[quasar.scala 103:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.br_start_error <= exu.io.exu_bp.exu_mp_pkt.bits.br_start_error @[quasar.scala 103:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.br_error <= exu.io.exu_bp.exu_mp_pkt.bits.br_error @[quasar.scala 103:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.toffset <= exu.io.exu_bp.exu_mp_pkt.bits.toffset @[quasar.scala 103:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.hist <= exu.io.exu_bp.exu_mp_pkt.bits.hist @[quasar.scala 103:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pc4 <= exu.io.exu_bp.exu_mp_pkt.bits.pc4 @[quasar.scala 103:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.boffset <= exu.io.exu_bp.exu_mp_pkt.bits.boffset @[quasar.scala 103:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.ataken <= exu.io.exu_bp.exu_mp_pkt.bits.ataken @[quasar.scala 103:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.misp <= exu.io.exu_bp.exu_mp_pkt.bits.misp @[quasar.scala 103:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.valid <= exu.io.exu_bp.exu_mp_pkt.valid @[quasar.scala 103:25] - ifu.io.exu_ifu.exu_bp.exu_i0_br_way_r <= exu.io.exu_bp.exu_i0_br_way_r @[quasar.scala 103:25] - ifu.io.exu_ifu.exu_bp.exu_i0_br_fghr_r <= exu.io.exu_bp.exu_i0_br_fghr_r @[quasar.scala 103:25] - ifu.io.exu_ifu.exu_bp.exu_i0_br_index_r <= exu.io.exu_bp.exu_i0_br_index_r @[quasar.scala 103:25] - ifu.io.exu_ifu.exu_bp.exu_i0_br_fghr_r <= exu.io.exu_bp.exu_i0_br_fghr_r @[quasar.scala 104:42] - ifu.io.exu_ifu.exu_bp.exu_i0_br_index_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_index_r @[quasar.scala 105:43] - ifu.io.dec_tlu_flush_lower_wb <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[quasar.scala 106:33] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid @[quasar.scala 107:51] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid @[quasar.scala 107:51] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics @[quasar.scala 107:51] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata @[quasar.scala 107:51] - dec.reset <= io.core_rst_l @[quasar.scala 110:13] - dec.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 111:19] - dec.io.active_clk <= rvclkhdr_1.io.l1clk @[quasar.scala 112:21] - dec.io.lsu_fastint_stall_any <= lsu.io.lsu_fastint_stall_any @[quasar.scala 113:32] - dec.io.rst_vec <= io.rst_vec @[quasar.scala 114:18] - dec.io.nmi_int <= io.nmi_int @[quasar.scala 115:18] - dec.io.nmi_vec <= io.nmi_vec @[quasar.scala 116:18] - dec.io.i_cpu_halt_req <= io.i_cpu_halt_req @[quasar.scala 117:25] - dec.io.i_cpu_run_req <= io.i_cpu_run_req @[quasar.scala 118:24] - dec.io.core_id <= io.core_id @[quasar.scala 119:18] - dec.io.mpc_debug_halt_req <= io.mpc_debug_halt_req @[quasar.scala 120:29] - dec.io.mpc_debug_run_req <= io.mpc_debug_run_req @[quasar.scala 121:28] - dec.io.mpc_reset_run_req <= io.mpc_reset_run_req @[quasar.scala 122:28] - dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data @[quasar.scala 123:18] - dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_tag <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_tag @[quasar.scala 123:18] - dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_error <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_error @[quasar.scala 123:18] - dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_valid <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_valid @[quasar.scala 123:18] - dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_tag_r <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_tag_r @[quasar.scala 123:18] - dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_r <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_r @[quasar.scala 123:18] - dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_tag_m <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_tag_m @[quasar.scala 123:18] - dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_valid_m <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_valid_m @[quasar.scala 123:18] - dec.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_addr_any <= lsu.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_addr_any @[quasar.scala 123:18] - dec.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_store_any <= lsu.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_store_any @[quasar.scala 123:18] - dec.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_load_any <= lsu.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_load_any @[quasar.scala 123:18] - lsu.io.lsu_dec.tlu_busbuff.dec_tlu_sideeffect_posted_disable <= dec.io.lsu_dec.tlu_busbuff.dec_tlu_sideeffect_posted_disable @[quasar.scala 123:18] - lsu.io.lsu_dec.tlu_busbuff.dec_tlu_wb_coalescing_disable <= dec.io.lsu_dec.tlu_busbuff.dec_tlu_wb_coalescing_disable @[quasar.scala 123:18] - lsu.io.lsu_dec.tlu_busbuff.dec_tlu_external_ldfwd_disable <= dec.io.lsu_dec.tlu_busbuff.dec_tlu_external_ldfwd_disable @[quasar.scala 123:18] - dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_busy <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_busy @[quasar.scala 123:18] - dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_error <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_error @[quasar.scala 123:18] - dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_misaligned <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_misaligned @[quasar.scala 123:18] - dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_trxn <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_trxn @[quasar.scala 123:18] - dec.io.lsu_tlu.lsu_pmu_store_external_m <= lsu.io.lsu_tlu.lsu_pmu_store_external_m @[quasar.scala 124:18] - dec.io.lsu_tlu.lsu_pmu_load_external_m <= lsu.io.lsu_tlu.lsu_pmu_load_external_m @[quasar.scala 124:18] - dec.io.lsu_pmu_misaligned_m <= lsu.io.lsu_pmu_misaligned_m @[quasar.scala 125:31] - dec.io.dec_dma.tlu_dma.dma_iccm_stall_any <= dma_ctrl.io.dec_dma.tlu_dma.dma_iccm_stall_any @[quasar.scala 126:18] - dec.io.dec_dma.tlu_dma.dma_dccm_stall_any <= dma_ctrl.io.dec_dma.tlu_dma.dma_dccm_stall_any @[quasar.scala 126:18] - dma_ctrl.io.dec_dma.tlu_dma.dec_tlu_dma_qos_prty <= dec.io.dec_dma.tlu_dma.dec_tlu_dma_qos_prty @[quasar.scala 126:18] - dec.io.dec_dma.tlu_dma.dma_pmu_any_write <= dma_ctrl.io.dec_dma.tlu_dma.dma_pmu_any_write @[quasar.scala 126:18] - dec.io.dec_dma.tlu_dma.dma_pmu_any_read <= dma_ctrl.io.dec_dma.tlu_dma.dma_pmu_any_read @[quasar.scala 126:18] - dec.io.dec_dma.tlu_dma.dma_pmu_dccm_write <= dma_ctrl.io.dec_dma.tlu_dma.dma_pmu_dccm_write @[quasar.scala 126:18] - dec.io.dec_dma.tlu_dma.dma_pmu_dccm_read <= dma_ctrl.io.dec_dma.tlu_dma.dma_pmu_dccm_read @[quasar.scala 126:18] - dec.io.dec_dma.dctl_dma.dma_dccm_stall_any <= dma_ctrl.io.dec_dma.dctl_dma.dma_dccm_stall_any @[quasar.scala 126:18] - dec.io.lsu_fir_addr <= lsu.io.lsu_fir_addr @[quasar.scala 128:23] - dec.io.lsu_fir_error <= lsu.io.lsu_fir_error @[quasar.scala 129:24] - dec.io.lsu_trigger_match_m <= lsu.io.lsu_trigger_match_m @[quasar.scala 130:30] - dec.io.dec_dbg.dbg_dctl.dbg_cmd_wrdata <= dbg.io.dbg_dec.dbg_dctl.dbg_cmd_wrdata @[quasar.scala 131:18] - dec.io.dec_dbg.dbg_ib.dbg_cmd_addr <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_addr @[quasar.scala 131:18] - dec.io.dec_dbg.dbg_ib.dbg_cmd_type <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_type @[quasar.scala 131:18] - dec.io.dec_dbg.dbg_ib.dbg_cmd_write <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_write @[quasar.scala 131:18] - dec.io.dec_dbg.dbg_ib.dbg_cmd_valid <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_valid @[quasar.scala 131:18] - dec.io.lsu_idle_any <= lsu.io.lsu_idle_any @[quasar.scala 132:23] - dec.io.lsu_error_pkt_r.bits.addr <= lsu.io.lsu_error_pkt_r.bits.addr @[quasar.scala 133:26] - dec.io.lsu_error_pkt_r.bits.mscause <= lsu.io.lsu_error_pkt_r.bits.mscause @[quasar.scala 133:26] - dec.io.lsu_error_pkt_r.bits.exc_type <= lsu.io.lsu_error_pkt_r.bits.exc_type @[quasar.scala 133:26] - dec.io.lsu_error_pkt_r.bits.inst_type <= lsu.io.lsu_error_pkt_r.bits.inst_type @[quasar.scala 133:26] - dec.io.lsu_error_pkt_r.bits.single_ecc_error <= lsu.io.lsu_error_pkt_r.bits.single_ecc_error @[quasar.scala 133:26] - dec.io.lsu_error_pkt_r.valid <= lsu.io.lsu_error_pkt_r.valid @[quasar.scala 133:26] - dec.io.lsu_single_ecc_error_incr <= lsu.io.lsu_single_ecc_error_incr @[quasar.scala 134:36] - dec.io.exu_div_result <= exu.io.exu_div_result @[quasar.scala 135:25] - dec.io.exu_div_wren <= exu.io.exu_div_wren @[quasar.scala 136:23] - dec.io.lsu_result_m <= lsu.io.lsu_result_m @[quasar.scala 137:23] - dec.io.lsu_result_corr_r <= lsu.io.lsu_result_corr_r @[quasar.scala 138:28] - dec.io.lsu_load_stall_any <= lsu.io.lsu_load_stall_any @[quasar.scala 139:29] - dec.io.lsu_store_stall_any <= lsu.io.lsu_store_stall_any @[quasar.scala 140:30] - dec.io.iccm_dma_sb_error <= ifu.io.iccm_dma_sb_error @[quasar.scala 141:28] - dec.io.exu_flush_final <= exu.io.exu_flush_final @[quasar.scala 142:26] - dec.io.soft_int <= io.soft_int @[quasar.scala 144:19] - dec.io.dbg_halt_req <= dbg.io.dbg_halt_req @[quasar.scala 145:23] - dec.io.dbg_resume_req <= dbg.io.dbg_resume_req @[quasar.scala 146:25] - dec.io.exu_i0_br_way_r <= exu.io.exu_bp.exu_i0_br_way_r @[quasar.scala 147:26] - dec.io.timer_int <= io.timer_int @[quasar.scala 148:20] - dec.io.scan_mode <= io.scan_mode @[quasar.scala 149:20] - exu.io.dec_exu.gpr_exu.gpr_i0_rs2_d <= dec.io.dec_exu.gpr_exu.gpr_i0_rs2_d @[quasar.scala 152:18] - exu.io.dec_exu.gpr_exu.gpr_i0_rs1_d <= dec.io.dec_exu.gpr_exu.gpr_i0_rs1_d @[quasar.scala 152:18] - exu.io.dec_exu.ib_exu.dec_debug_wdata_rs1_d <= dec.io.dec_exu.ib_exu.dec_debug_wdata_rs1_d @[quasar.scala 152:18] - exu.io.dec_exu.ib_exu.dec_i0_pc_d <= dec.io.dec_exu.ib_exu.dec_i0_pc_d @[quasar.scala 152:18] - dec.io.dec_exu.tlu_exu.exu_npc_r <= exu.io.dec_exu.tlu_exu.exu_npc_r @[quasar.scala 152:18] - dec.io.dec_exu.tlu_exu.exu_pmu_i0_pc4 <= exu.io.dec_exu.tlu_exu.exu_pmu_i0_pc4 @[quasar.scala 152:18] - dec.io.dec_exu.tlu_exu.exu_pmu_i0_br_ataken <= exu.io.dec_exu.tlu_exu.exu_pmu_i0_br_ataken @[quasar.scala 152:18] - dec.io.dec_exu.tlu_exu.exu_pmu_i0_br_misp <= exu.io.dec_exu.tlu_exu.exu_pmu_i0_br_misp @[quasar.scala 152:18] - dec.io.dec_exu.tlu_exu.exu_i0_br_middle_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_middle_r @[quasar.scala 152:18] - dec.io.dec_exu.tlu_exu.exu_i0_br_mp_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_mp_r @[quasar.scala 152:18] - dec.io.dec_exu.tlu_exu.exu_i0_br_valid_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_valid_r @[quasar.scala 152:18] - dec.io.dec_exu.tlu_exu.exu_i0_br_index_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_index_r @[quasar.scala 152:18] - dec.io.dec_exu.tlu_exu.exu_i0_br_start_error_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_start_error_r @[quasar.scala 152:18] - dec.io.dec_exu.tlu_exu.exu_i0_br_error_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_error_r @[quasar.scala 152:18] - dec.io.dec_exu.tlu_exu.exu_i0_br_hist_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_hist_r @[quasar.scala 152:18] - exu.io.dec_exu.tlu_exu.dec_tlu_flush_path_r <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_path_r @[quasar.scala 152:18] - exu.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[quasar.scala 152:18] - exu.io.dec_exu.tlu_exu.dec_tlu_meihap <= dec.io.dec_exu.tlu_exu.dec_tlu_meihap @[quasar.scala 152:18] - dec.io.dec_exu.decode_exu.exu_csr_rs1_x <= exu.io.dec_exu.decode_exu.exu_csr_rs1_x @[quasar.scala 152:18] - dec.io.dec_exu.decode_exu.exu_i0_result_x <= exu.io.dec_exu.decode_exu.exu_i0_result_x @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.dec_extint_stall <= dec.io.dec_exu.decode_exu.dec_extint_stall @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.pred_correct_npc_x <= dec.io.dec_exu.decode_exu.pred_correct_npc_x @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.mul_p.bits.bfp <= dec.io.dec_exu.decode_exu.mul_p.bits.bfp @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.mul_p.bits.crc32c_w <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32c_w @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.mul_p.bits.crc32c_h <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32c_h @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.mul_p.bits.crc32c_b <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32c_b @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.mul_p.bits.crc32_w <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32_w @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.mul_p.bits.crc32_h <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32_h @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.mul_p.bits.crc32_b <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32_b @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.mul_p.bits.unshfl <= dec.io.dec_exu.decode_exu.mul_p.bits.unshfl @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.mul_p.bits.shfl <= dec.io.dec_exu.decode_exu.mul_p.bits.shfl @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.mul_p.bits.grev <= dec.io.dec_exu.decode_exu.mul_p.bits.grev @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.mul_p.bits.clmulr <= dec.io.dec_exu.decode_exu.mul_p.bits.clmulr @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.mul_p.bits.clmulh <= dec.io.dec_exu.decode_exu.mul_p.bits.clmulh @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.mul_p.bits.clmul <= dec.io.dec_exu.decode_exu.mul_p.bits.clmul @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.mul_p.bits.bdep <= dec.io.dec_exu.decode_exu.mul_p.bits.bdep @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.mul_p.bits.bext <= dec.io.dec_exu.decode_exu.mul_p.bits.bext @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.mul_p.bits.low <= dec.io.dec_exu.decode_exu.mul_p.bits.low @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.mul_p.bits.rs2_sign <= dec.io.dec_exu.decode_exu.mul_p.bits.rs2_sign @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.mul_p.bits.rs1_sign <= dec.io.dec_exu.decode_exu.mul_p.bits.rs1_sign @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.mul_p.valid <= dec.io.dec_exu.decode_exu.mul_p.valid @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.dec_i0_select_pc_d <= dec.io.dec_exu.decode_exu.dec_i0_select_pc_d @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.dec_i0_rs2_bypass_data_d <= dec.io.dec_exu.decode_exu.dec_i0_rs2_bypass_data_d @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.dec_i0_rs1_bypass_data_d <= dec.io.dec_exu.decode_exu.dec_i0_rs1_bypass_data_d @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.dec_i0_immed_d <= dec.io.dec_exu.decode_exu.dec_i0_immed_d @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.dec_i0_rs2_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs2_en_d @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.dec_i0_rs1_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs1_en_d @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.i0_predict_btag_d <= dec.io.dec_exu.decode_exu.i0_predict_btag_d @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.i0_predict_index_d <= dec.io.dec_exu.decode_exu.i0_predict_index_d @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.i0_predict_fghr_d <= dec.io.dec_exu.decode_exu.i0_predict_fghr_d @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.way <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.way @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pja <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pja @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pret <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pret @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pcall <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pcall @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.prett <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.prett @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_start_error <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_start_error @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_error <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_error @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.toffset <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.toffset @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.hist <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.hist @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pc4 <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pc4 @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.boffset <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.boffset @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.ataken <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.ataken @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.misp <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.misp @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.valid <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.valid @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.i0_ap.csr_imm <= dec.io.dec_exu.decode_exu.i0_ap.csr_imm @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.i0_ap.csr_write <= dec.io.dec_exu.decode_exu.i0_ap.csr_write @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.i0_ap.predict_nt <= dec.io.dec_exu.decode_exu.i0_ap.predict_nt @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.i0_ap.predict_t <= dec.io.dec_exu.decode_exu.i0_ap.predict_t @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.i0_ap.jal <= dec.io.dec_exu.decode_exu.i0_ap.jal @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.i0_ap.unsign <= dec.io.dec_exu.decode_exu.i0_ap.unsign @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.i0_ap.slt <= dec.io.dec_exu.decode_exu.i0_ap.slt @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.i0_ap.sub <= dec.io.dec_exu.decode_exu.i0_ap.sub @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.i0_ap.add <= dec.io.dec_exu.decode_exu.i0_ap.add @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.i0_ap.bge <= dec.io.dec_exu.decode_exu.i0_ap.bge @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.i0_ap.blt <= dec.io.dec_exu.decode_exu.i0_ap.blt @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.i0_ap.bne <= dec.io.dec_exu.decode_exu.i0_ap.bne @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.i0_ap.beq <= dec.io.dec_exu.decode_exu.i0_ap.beq @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.i0_ap.sra <= dec.io.dec_exu.decode_exu.i0_ap.sra @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.i0_ap.srl <= dec.io.dec_exu.decode_exu.i0_ap.srl @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.i0_ap.sll <= dec.io.dec_exu.decode_exu.i0_ap.sll @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.i0_ap.lxor <= dec.io.dec_exu.decode_exu.i0_ap.lxor @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.i0_ap.lor <= dec.io.dec_exu.decode_exu.i0_ap.lor @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.i0_ap.land <= dec.io.dec_exu.decode_exu.i0_ap.land @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.dec_ctl_en <= dec.io.dec_exu.decode_exu.dec_ctl_en @[quasar.scala 152:18] - exu.io.dec_exu.decode_exu.dec_data_en <= dec.io.dec_exu.decode_exu.dec_data_en @[quasar.scala 152:18] - exu.io.dec_exu.dec_div.dec_div_cancel <= dec.io.dec_exu.dec_div.dec_div_cancel @[quasar.scala 152:18] - exu.io.dec_exu.dec_div.div_p.bits.rem <= dec.io.dec_exu.dec_div.div_p.bits.rem @[quasar.scala 152:18] - exu.io.dec_exu.dec_div.div_p.bits.unsign <= dec.io.dec_exu.dec_div.div_p.bits.unsign @[quasar.scala 152:18] - exu.io.dec_exu.dec_div.div_p.valid <= dec.io.dec_exu.dec_div.div_p.valid @[quasar.scala 152:18] - dec.io.dec_exu.dec_alu.exu_i0_pc_x <= exu.io.dec_exu.dec_alu.exu_i0_pc_x @[quasar.scala 152:18] - exu.io.dec_exu.dec_alu.dec_i0_br_immed_d <= dec.io.dec_exu.dec_alu.dec_i0_br_immed_d @[quasar.scala 152:18] - exu.io.dec_exu.dec_alu.dec_csr_ren_d <= dec.io.dec_exu.dec_alu.dec_csr_ren_d @[quasar.scala 152:18] - exu.io.dec_exu.dec_alu.dec_i0_alu_decode_d <= dec.io.dec_exu.dec_alu.dec_i0_alu_decode_d @[quasar.scala 152:18] - exu.reset <= io.core_rst_l @[quasar.scala 153:13] - exu.io.scan_mode <= io.scan_mode @[quasar.scala 154:20] - exu.io.dbg_cmd_wrdata <= dbg.io.dbg_dec.dbg_dctl.dbg_cmd_wrdata @[quasar.scala 155:25] - lsu.reset <= io.core_rst_l @[quasar.scala 158:13] - lsu.io.clk_override <= dec.io.dec_tlu_lsu_clk_override @[quasar.scala 159:23] - lsu.io.dec_tlu_flush_lower_r <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[quasar.scala 160:32] - lsu.io.dec_tlu_i0_kill_writeb_r <= dec.io.dec_tlu_i0_kill_writeb_r @[quasar.scala 161:35] - lsu.io.dec_tlu_force_halt <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt @[quasar.scala 162:29] - lsu.io.dec_tlu_core_ecc_disable <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable @[quasar.scala 163:35] - lsu.io.lsu_exu.exu_lsu_rs2_d <= exu.io.lsu_exu.exu_lsu_rs2_d @[quasar.scala 164:18] - lsu.io.lsu_exu.exu_lsu_rs1_d <= exu.io.lsu_exu.exu_lsu_rs1_d @[quasar.scala 164:18] - lsu.io.dec_lsu_offset_d <= dec.io.dec_lsu_offset_d @[quasar.scala 165:27] - lsu.io.lsu_p.bits.store_data_bypass_m <= dec.io.lsu_p.bits.store_data_bypass_m @[quasar.scala 166:16] - lsu.io.lsu_p.bits.load_ldst_bypass_d <= dec.io.lsu_p.bits.load_ldst_bypass_d @[quasar.scala 166:16] - lsu.io.lsu_p.bits.store_data_bypass_d <= dec.io.lsu_p.bits.store_data_bypass_d @[quasar.scala 166:16] - lsu.io.lsu_p.bits.dma <= dec.io.lsu_p.bits.dma @[quasar.scala 166:16] - lsu.io.lsu_p.bits.unsign <= dec.io.lsu_p.bits.unsign @[quasar.scala 166:16] - lsu.io.lsu_p.bits.store <= dec.io.lsu_p.bits.store @[quasar.scala 166:16] - lsu.io.lsu_p.bits.load <= dec.io.lsu_p.bits.load @[quasar.scala 166:16] - lsu.io.lsu_p.bits.dword <= dec.io.lsu_p.bits.dword @[quasar.scala 166:16] - lsu.io.lsu_p.bits.word <= dec.io.lsu_p.bits.word @[quasar.scala 166:16] - lsu.io.lsu_p.bits.half <= dec.io.lsu_p.bits.half @[quasar.scala 166:16] - lsu.io.lsu_p.bits.by <= dec.io.lsu_p.bits.by @[quasar.scala 166:16] - lsu.io.lsu_p.bits.fast_int <= dec.io.lsu_p.bits.fast_int @[quasar.scala 166:16] - lsu.io.lsu_p.valid <= dec.io.lsu_p.valid @[quasar.scala 166:16] - lsu.io.dec_lsu_valid_raw_d <= dec.io.dec_lsu_valid_raw_d @[quasar.scala 167:30] - lsu.io.dec_tlu_mrac_ff <= dec.io.ifu_dec.dec_ifc.dec_tlu_mrac_ff @[quasar.scala 168:26] - lsu.io.trigger_pkt_any[0].tdata2 <= dec.io.trigger_pkt_any[0].tdata2 @[quasar.scala 169:26] - lsu.io.trigger_pkt_any[0].m <= dec.io.trigger_pkt_any[0].m @[quasar.scala 169:26] - lsu.io.trigger_pkt_any[0].execute <= dec.io.trigger_pkt_any[0].execute @[quasar.scala 169:26] - lsu.io.trigger_pkt_any[0].load <= dec.io.trigger_pkt_any[0].load @[quasar.scala 169:26] - lsu.io.trigger_pkt_any[0].store <= dec.io.trigger_pkt_any[0].store @[quasar.scala 169:26] - lsu.io.trigger_pkt_any[0].match_pkt <= dec.io.trigger_pkt_any[0].match_pkt @[quasar.scala 169:26] - lsu.io.trigger_pkt_any[0].select <= dec.io.trigger_pkt_any[0].select @[quasar.scala 169:26] - lsu.io.trigger_pkt_any[1].tdata2 <= dec.io.trigger_pkt_any[1].tdata2 @[quasar.scala 169:26] - lsu.io.trigger_pkt_any[1].m <= dec.io.trigger_pkt_any[1].m @[quasar.scala 169:26] - lsu.io.trigger_pkt_any[1].execute <= dec.io.trigger_pkt_any[1].execute @[quasar.scala 169:26] - lsu.io.trigger_pkt_any[1].load <= dec.io.trigger_pkt_any[1].load @[quasar.scala 169:26] - lsu.io.trigger_pkt_any[1].store <= dec.io.trigger_pkt_any[1].store @[quasar.scala 169:26] - lsu.io.trigger_pkt_any[1].match_pkt <= dec.io.trigger_pkt_any[1].match_pkt @[quasar.scala 169:26] - lsu.io.trigger_pkt_any[1].select <= dec.io.trigger_pkt_any[1].select @[quasar.scala 169:26] - lsu.io.trigger_pkt_any[2].tdata2 <= dec.io.trigger_pkt_any[2].tdata2 @[quasar.scala 169:26] - lsu.io.trigger_pkt_any[2].m <= dec.io.trigger_pkt_any[2].m @[quasar.scala 169:26] - lsu.io.trigger_pkt_any[2].execute <= dec.io.trigger_pkt_any[2].execute @[quasar.scala 169:26] - lsu.io.trigger_pkt_any[2].load <= dec.io.trigger_pkt_any[2].load @[quasar.scala 169:26] - lsu.io.trigger_pkt_any[2].store <= dec.io.trigger_pkt_any[2].store @[quasar.scala 169:26] - lsu.io.trigger_pkt_any[2].match_pkt <= dec.io.trigger_pkt_any[2].match_pkt @[quasar.scala 169:26] - lsu.io.trigger_pkt_any[2].select <= dec.io.trigger_pkt_any[2].select @[quasar.scala 169:26] - lsu.io.trigger_pkt_any[3].tdata2 <= dec.io.trigger_pkt_any[3].tdata2 @[quasar.scala 169:26] - lsu.io.trigger_pkt_any[3].m <= dec.io.trigger_pkt_any[3].m @[quasar.scala 169:26] - lsu.io.trigger_pkt_any[3].execute <= dec.io.trigger_pkt_any[3].execute @[quasar.scala 169:26] - lsu.io.trigger_pkt_any[3].load <= dec.io.trigger_pkt_any[3].load @[quasar.scala 169:26] - lsu.io.trigger_pkt_any[3].store <= dec.io.trigger_pkt_any[3].store @[quasar.scala 169:26] - lsu.io.trigger_pkt_any[3].match_pkt <= dec.io.trigger_pkt_any[3].match_pkt @[quasar.scala 169:26] - lsu.io.trigger_pkt_any[3].select <= dec.io.trigger_pkt_any[3].select @[quasar.scala 169:26] - lsu.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[quasar.scala 171:25] - lsu.io.lsu_dma.dma_mem_tag <= dma_ctrl.io.lsu_dma.dma_mem_tag @[quasar.scala 172:18] - dma_ctrl.io.lsu_dma.dccm_ready <= lsu.io.lsu_dma.dccm_ready @[quasar.scala 172:18] - dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_rdata <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_rdata @[quasar.scala 172:18] - dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag @[quasar.scala 172:18] - dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error @[quasar.scala 172:18] - dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid @[quasar.scala 172:18] - lsu.io.lsu_dma.dma_dccm_ctl.dma_mem_wdata <= dma_ctrl.io.lsu_dma.dma_dccm_ctl.dma_mem_wdata @[quasar.scala 172:18] - lsu.io.lsu_dma.dma_dccm_ctl.dma_mem_addr <= dma_ctrl.io.lsu_dma.dma_dccm_ctl.dma_mem_addr @[quasar.scala 172:18] - lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_wdata <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_wdata @[quasar.scala 172:18] - lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_write <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_write @[quasar.scala 172:18] - lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_sz <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_sz @[quasar.scala 172:18] - lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_addr <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_addr @[quasar.scala 172:18] - lsu.io.lsu_dma.dma_lsc_ctl.dma_dccm_req <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_dccm_req @[quasar.scala 172:18] - lsu.io.scan_mode <= io.scan_mode @[quasar.scala 173:20] - lsu.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 174:19] - dbg.reset <= io.core_rst_l @[quasar.scala 177:13] - node _T_8 = mux(dma_ctrl.io.dma_dbg_cmd_done, dma_ctrl.io.dma_dbg_rddata, dec.io.dec_dbg_rddata) @[quasar.scala 178:32] - dbg.io.core_dbg_rddata <= _T_8 @[quasar.scala 178:26] - node _T_9 = or(dma_ctrl.io.dma_dbg_cmd_done, dec.io.dec_dbg_cmd_done) @[quasar.scala 179:60] - dbg.io.core_dbg_cmd_done <= _T_9 @[quasar.scala 179:28] - node _T_10 = or(dma_ctrl.io.dma_dbg_cmd_fail, dec.io.dec_dbg_cmd_fail) @[quasar.scala 180:60] - dbg.io.core_dbg_cmd_fail <= _T_10 @[quasar.scala 180:28] - dbg.io.dec_tlu_debug_mode <= dec.io.dec_tlu_debug_mode @[quasar.scala 181:29] - dbg.io.dec_tlu_dbg_halted <= dec.io.dec_tlu_dbg_halted @[quasar.scala 182:29] - dbg.io.dec_tlu_mpc_halted_only <= dec.io.dec_tlu_mpc_halted_only @[quasar.scala 183:34] - dbg.io.dec_tlu_resume_ack <= dec.io.dec_tlu_resume_ack @[quasar.scala 184:29] - dbg.io.dmi_reg_en <= io.dmi_reg_en @[quasar.scala 185:21] - dbg.io.dmi_reg_addr <= io.dmi_reg_addr @[quasar.scala 186:23] - dbg.io.dmi_reg_wr_en <= io.dmi_reg_wr_en @[quasar.scala 187:24] - dbg.io.dmi_reg_wdata <= io.dmi_reg_wdata @[quasar.scala 188:24] - dbg.io.dbg_bus_clk_en <= io.dbg_bus_clk_en @[quasar.scala 189:25] - node _T_11 = asUInt(io.dbg_rst_l) @[quasar.scala 190:42] - dbg.io.dbg_rst_l <= _T_11 @[quasar.scala 190:20] - dbg.io.clk_override <= dec.io.dec_tlu_misc_clk_override @[quasar.scala 191:23] - dbg.io.scan_mode <= io.scan_mode @[quasar.scala 192:20] - dma_ctrl.reset <= io.core_rst_l @[quasar.scala 196:18] - dma_ctrl.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 197:24] - dma_ctrl.io.dma_bus_clk_en <= io.dma_bus_clk_en @[quasar.scala 198:30] - dma_ctrl.io.clk_override <= dec.io.dec_tlu_misc_clk_override @[quasar.scala 199:28] - dma_ctrl.io.scan_mode <= io.scan_mode @[quasar.scala 200:25] - dma_ctrl.io.dbg_dma.dbg_dctl.dbg_cmd_wrdata <= dbg.io.dbg_dma.dbg_dctl.dbg_cmd_wrdata @[quasar.scala 201:23] - dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_addr <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_addr @[quasar.scala 201:23] - dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_type <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_type @[quasar.scala 201:23] - dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_write <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_write @[quasar.scala 201:23] - dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_valid <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_valid @[quasar.scala 201:23] - dbg.io.dbg_dma_io.dma_dbg_ready <= dma_ctrl.io.dbg_dma_io.dma_dbg_ready @[quasar.scala 202:26] - dma_ctrl.io.dbg_dma_io.dbg_dma_bubble <= dbg.io.dbg_dma_io.dbg_dma_bubble @[quasar.scala 202:26] - dma_ctrl.io.dbg_cmd_size <= dbg.io.dbg_cmd_size @[quasar.scala 203:28] - dma_ctrl.io.iccm_dma_rvalid <= ifu.io.iccm_dma_rvalid @[quasar.scala 204:31] - dma_ctrl.io.iccm_dma_rtag <= ifu.io.iccm_dma_rtag @[quasar.scala 205:29] - dma_ctrl.io.iccm_dma_rdata <= ifu.io.iccm_dma_rdata @[quasar.scala 206:30] - dma_ctrl.io.iccm_ready <= ifu.io.iccm_ready @[quasar.scala 207:26] - dma_ctrl.io.iccm_dma_ecc_error <= ifu.io.iccm_dma_ecc_error @[quasar.scala 208:34] - pic_ctrl_inst.io.scan_mode <= io.scan_mode @[quasar.scala 211:30] - pic_ctrl_inst.reset <= io.core_rst_l @[quasar.scala 212:23] - pic_ctrl_inst.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 213:29] - pic_ctrl_inst.io.active_clk <= rvclkhdr_1.io.l1clk @[quasar.scala 214:31] - pic_ctrl_inst.io.clk_override <= dec.io.dec_tlu_pic_clk_override @[quasar.scala 215:33] - pic_ctrl_inst.io.extintsrc_req <= io.extintsrc_req @[quasar.scala 216:34] - lsu.io.lsu_pic.picm_rd_data <= pic_ctrl_inst.io.lsu_pic.picm_rd_data @[quasar.scala 217:28] - pic_ctrl_inst.io.lsu_pic.picm_wr_data <= lsu.io.lsu_pic.picm_wr_data @[quasar.scala 217:28] - pic_ctrl_inst.io.lsu_pic.picm_wraddr <= lsu.io.lsu_pic.picm_wraddr @[quasar.scala 217:28] - pic_ctrl_inst.io.lsu_pic.picm_rdaddr <= lsu.io.lsu_pic.picm_rdaddr @[quasar.scala 217:28] - pic_ctrl_inst.io.lsu_pic.picm_mken <= lsu.io.lsu_pic.picm_mken @[quasar.scala 217:28] - pic_ctrl_inst.io.lsu_pic.picm_rden <= lsu.io.lsu_pic.picm_rden @[quasar.scala 217:28] - pic_ctrl_inst.io.lsu_pic.picm_wren <= lsu.io.lsu_pic.picm_wren @[quasar.scala 217:28] - dec.io.dec_pic.mexintpend <= pic_ctrl_inst.io.dec_pic.mexintpend @[quasar.scala 218:28] - pic_ctrl_inst.io.dec_pic.dec_tlu_meipt <= dec.io.dec_pic.dec_tlu_meipt @[quasar.scala 218:28] - pic_ctrl_inst.io.dec_pic.dec_tlu_meicurpl <= dec.io.dec_pic.dec_tlu_meicurpl @[quasar.scala 218:28] - dec.io.dec_pic.mhwakeup <= pic_ctrl_inst.io.dec_pic.mhwakeup @[quasar.scala 218:28] - dec.io.dec_pic.pic_pl <= pic_ctrl_inst.io.dec_pic.pic_pl @[quasar.scala 218:28] - dec.io.dec_pic.pic_claimid <= pic_ctrl_inst.io.dec_pic.pic_claimid @[quasar.scala 218:28] - io.rv_trace_pkt.rv_i_tval_ip <= dec.io.rv_trace_pkt.rv_i_tval_ip @[quasar.scala 220:19] - io.rv_trace_pkt.rv_i_interrupt_ip <= dec.io.rv_trace_pkt.rv_i_interrupt_ip @[quasar.scala 220:19] - io.rv_trace_pkt.rv_i_ecause_ip <= dec.io.rv_trace_pkt.rv_i_ecause_ip @[quasar.scala 220:19] - io.rv_trace_pkt.rv_i_exception_ip <= dec.io.rv_trace_pkt.rv_i_exception_ip @[quasar.scala 220:19] - io.rv_trace_pkt.rv_i_address_ip <= dec.io.rv_trace_pkt.rv_i_address_ip @[quasar.scala 220:19] - io.rv_trace_pkt.rv_i_insn_ip <= dec.io.rv_trace_pkt.rv_i_insn_ip @[quasar.scala 220:19] - io.rv_trace_pkt.rv_i_valid_ip <= dec.io.rv_trace_pkt.rv_i_valid_ip @[quasar.scala 220:19] - io.dccm_clk_override <= dec.io.dec_tlu_dccm_clk_override @[quasar.scala 223:24] - io.icm_clk_override <= dec.io.dec_tlu_icm_clk_override @[quasar.scala 224:23] - io.dec_tlu_core_ecc_disable <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable @[quasar.scala 225:31] - io.o_cpu_halt_ack <= dec.io.o_cpu_halt_ack @[quasar.scala 226:21] - io.o_cpu_halt_status <= dec.io.o_cpu_halt_status @[quasar.scala 227:24] - io.o_cpu_run_ack <= dec.io.o_cpu_run_ack @[quasar.scala 228:20] - io.o_debug_mode_status <= dec.io.o_debug_mode_status @[quasar.scala 229:26] - io.mpc_debug_halt_ack <= dec.io.mpc_debug_halt_ack @[quasar.scala 230:25] - io.mpc_debug_run_ack <= dec.io.mpc_debug_run_ack @[quasar.scala 231:24] - io.debug_brkpt_status <= dec.io.debug_brkpt_status @[quasar.scala 232:25] - io.dec_tlu_perfcnt0 <= dec.io.dec_tlu_perfcnt0 @[quasar.scala 233:23] - io.dec_tlu_perfcnt1 <= dec.io.dec_tlu_perfcnt1 @[quasar.scala 234:23] - io.dec_tlu_perfcnt2 <= dec.io.dec_tlu_perfcnt2 @[quasar.scala 235:23] - io.dec_tlu_perfcnt3 <= dec.io.dec_tlu_perfcnt3 @[quasar.scala 236:23] - lsu.io.dccm.rd_data_hi <= io.dccm.rd_data_hi @[quasar.scala 238:11] - lsu.io.dccm.rd_data_lo <= io.dccm.rd_data_lo @[quasar.scala 238:11] - io.dccm.wr_data_hi <= lsu.io.dccm.wr_data_hi @[quasar.scala 238:11] - io.dccm.wr_data_lo <= lsu.io.dccm.wr_data_lo @[quasar.scala 238:11] - io.dccm.rd_addr_hi <= lsu.io.dccm.rd_addr_hi @[quasar.scala 238:11] - io.dccm.rd_addr_lo <= lsu.io.dccm.rd_addr_lo @[quasar.scala 238:11] - io.dccm.wr_addr_hi <= lsu.io.dccm.wr_addr_hi @[quasar.scala 238:11] - io.dccm.wr_addr_lo <= lsu.io.dccm.wr_addr_lo @[quasar.scala 238:11] - io.dccm.rden <= lsu.io.dccm.rden @[quasar.scala 238:11] - io.dccm.wren <= lsu.io.dccm.wren @[quasar.scala 238:11] - inst axi4_to_ahb of axi4_to_ahb @[quasar.scala 242:32] + node core_dbg_cmd_done = or(dma_ctrl.io.dma_dbg_cmd_done, dec.io.dec_dbg_cmd_done) @[quasar.scala 86:56] + node core_dbg_cmd_fail = or(dma_ctrl.io.dma_dbg_cmd_fail, dec.io.dec_dbg_cmd_fail) @[quasar.scala 87:56] + node core_dbg_rddata = mux(dma_ctrl.io.dma_dbg_cmd_done, dma_ctrl.io.dma_dbg_rddata, dec.io.dec_dbg_rddata) @[quasar.scala 88:28] + ifu.io.ifu_dec.dec_bp.dec_tlu_bpred_disable <= dec.io.ifu_dec.dec_bp.dec_tlu_bpred_disable @[quasar.scala 91:18] + ifu.io.ifu_dec.dec_bp.dec_tlu_flush_leak_one_wb <= dec.io.ifu_dec.dec_bp.dec_tlu_flush_leak_one_wb @[quasar.scala 91:18] + ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.middle <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.middle @[quasar.scala 91:18] + ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.way <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.way @[quasar.scala 91:18] + ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_start_error <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_start_error @[quasar.scala 91:18] + ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_error <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_error @[quasar.scala 91:18] + ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.hist <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.hist @[quasar.scala 91:18] + ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.valid <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.valid @[quasar.scala 91:18] + dec.io.ifu_dec.dec_ifc.ifu_pmu_fetch_stall <= ifu.io.ifu_dec.dec_ifc.ifu_pmu_fetch_stall @[quasar.scala 91:18] + ifu.io.ifu_dec.dec_ifc.dec_tlu_mrac_ff <= dec.io.ifu_dec.dec_ifc.dec_tlu_mrac_ff @[quasar.scala 91:18] + ifu.io.ifu_dec.dec_ifc.dec_tlu_flush_noredir_wb <= dec.io.ifu_dec.dec_ifc.dec_tlu_flush_noredir_wb @[quasar.scala 91:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_miss_state_idle <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_miss_state_idle @[quasar.scala 91:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data_valid <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data_valid @[quasar.scala 91:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data @[quasar.scala 91:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err @[quasar.scala 91:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_ic_error_start <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_ic_error_start @[quasar.scala 91:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_trxn <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_trxn @[quasar.scala 91:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_busy <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_busy @[quasar.scala 91:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_error <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_error @[quasar.scala 91:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_hit <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_hit @[quasar.scala 91:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_miss <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_miss @[quasar.scala 91:18] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable @[quasar.scala 91:18] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid @[quasar.scala 91:18] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid @[quasar.scala 91:18] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics @[quasar.scala 91:18] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata @[quasar.scala 91:18] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_fence_i_wb <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_fence_i_wb @[quasar.scala 91:18] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt @[quasar.scala 91:18] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_i0_commit_cmt <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_i0_commit_cmt @[quasar.scala 91:18] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_flush_err_wb <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_flush_err_wb @[quasar.scala 91:18] + dec.io.ifu_dec.dec_aln.ifu_pmu_instr_aligned <= ifu.io.ifu_dec.dec_aln.ifu_pmu_instr_aligned @[quasar.scala 91:18] + dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.ret <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.ret @[quasar.scala 91:18] + dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.way <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.way @[quasar.scala 91:18] + dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.prett <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.prett @[quasar.scala 91:18] + dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.bank <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.bank @[quasar.scala 91:18] + dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_start_error <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_start_error @[quasar.scala 91:18] + dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_error <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_error @[quasar.scala 91:18] + dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.hist <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.hist @[quasar.scala 91:18] + dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.toffset <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.toffset @[quasar.scala 91:18] + dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.valid <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.valid @[quasar.scala 91:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc4 <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc4 @[quasar.scala 91:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc @[quasar.scala 91:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_instr <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_instr @[quasar.scala 91:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_valid <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_valid @[quasar.scala 91:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_btag <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_btag @[quasar.scala 91:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_fghr <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_fghr @[quasar.scala 91:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_index <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_index @[quasar.scala 91:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_dbecc <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_dbecc @[quasar.scala 91:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_f1 <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_f1 @[quasar.scala 91:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_type <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_type @[quasar.scala 91:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf @[quasar.scala 91:18] + dec.io.ifu_dec.dec_aln.aln_dec.ifu_i0_cinst <= ifu.io.ifu_dec.dec_aln.aln_dec.ifu_i0_cinst @[quasar.scala 91:18] + ifu.io.ifu_dec.dec_aln.aln_dec.dec_i0_decode_d <= dec.io.ifu_dec.dec_aln.aln_dec.dec_i0_decode_d @[quasar.scala 91:18] + ifu.reset <= io.core_rst_l @[quasar.scala 93:13] + ifu.io.scan_mode <= io.scan_mode @[quasar.scala 94:20] + ifu.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 95:19] + ifu.io.active_clk <= rvclkhdr_1.io.l1clk @[quasar.scala 96:21] + ifu.io.exu_flush_final <= dec.io.exu_flush_final @[quasar.scala 98:26] + ifu.io.exu_flush_path_final <= exu.io.exu_flush_path_final @[quasar.scala 99:31] + ifu.io.ifu_bus_clk_en <= io.ifu_bus_clk_en @[quasar.scala 101:25] + ifu.io.ifu_dma.dma_mem_ctl.dma_mem_tag <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_tag @[quasar.scala 102:18] + ifu.io.ifu_dma.dma_mem_ctl.dma_mem_wdata <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_wdata @[quasar.scala 102:18] + ifu.io.ifu_dma.dma_mem_ctl.dma_mem_write <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_write @[quasar.scala 102:18] + ifu.io.ifu_dma.dma_mem_ctl.dma_mem_sz <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_sz @[quasar.scala 102:18] + ifu.io.ifu_dma.dma_mem_ctl.dma_mem_addr <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_addr @[quasar.scala 102:18] + ifu.io.ifu_dma.dma_mem_ctl.dma_iccm_req <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_iccm_req @[quasar.scala 102:18] + ifu.io.ifu_dma.dma_ifc.dma_iccm_stall_any <= dma_ctrl.io.ifu_dma.dma_ifc.dma_iccm_stall_any @[quasar.scala 102:18] + io.ic.sel_premux_data <= ifu.io.ic.sel_premux_data @[quasar.scala 103:13] + io.ic.premux_data <= ifu.io.ic.premux_data @[quasar.scala 103:13] + io.ic.debug_way <= ifu.io.ic.debug_way @[quasar.scala 103:13] + io.ic.debug_tag_array <= ifu.io.ic.debug_tag_array @[quasar.scala 103:13] + io.ic.debug_wr_en <= ifu.io.ic.debug_wr_en @[quasar.scala 103:13] + io.ic.debug_rd_en <= ifu.io.ic.debug_rd_en @[quasar.scala 103:13] + ifu.io.ic.tag_perr <= io.ic.tag_perr @[quasar.scala 103:13] + ifu.io.ic.rd_hit <= io.ic.rd_hit @[quasar.scala 103:13] + ifu.io.ic.parerr <= io.ic.parerr @[quasar.scala 103:13] + ifu.io.ic.eccerr <= io.ic.eccerr @[quasar.scala 103:13] + ifu.io.ic.tag_debug_rd_data <= io.ic.tag_debug_rd_data @[quasar.scala 103:13] + ifu.io.ic.debug_rd_data <= io.ic.debug_rd_data @[quasar.scala 103:13] + ifu.io.ic.rd_data <= io.ic.rd_data @[quasar.scala 103:13] + io.ic.debug_addr <= ifu.io.ic.debug_addr @[quasar.scala 103:13] + io.ic.debug_wr_data <= ifu.io.ic.debug_wr_data @[quasar.scala 103:13] + io.ic.wr_data[0] <= ifu.io.ic.wr_data[0] @[quasar.scala 103:13] + io.ic.wr_data[1] <= ifu.io.ic.wr_data[1] @[quasar.scala 103:13] + io.ic.rd_en <= ifu.io.ic.rd_en @[quasar.scala 103:13] + io.ic.wr_en <= ifu.io.ic.wr_en @[quasar.scala 103:13] + io.ic.tag_valid <= ifu.io.ic.tag_valid @[quasar.scala 103:13] + io.ic.rw_addr <= ifu.io.ic.rw_addr @[quasar.scala 103:13] + ifu.io.iccm.rd_data_ecc <= io.iccm.rd_data_ecc @[quasar.scala 104:15] + ifu.io.iccm.rd_data <= io.iccm.rd_data @[quasar.scala 104:15] + io.iccm.wr_data <= ifu.io.iccm.wr_data @[quasar.scala 104:15] + io.iccm.wr_size <= ifu.io.iccm.wr_size @[quasar.scala 104:15] + io.iccm.rden <= ifu.io.iccm.rden @[quasar.scala 104:15] + io.iccm.wren <= ifu.io.iccm.wren @[quasar.scala 104:15] + io.iccm.correction_state <= ifu.io.iccm.correction_state @[quasar.scala 104:15] + io.iccm.buf_correct_ecc <= ifu.io.iccm.buf_correct_ecc @[quasar.scala 104:15] + io.iccm.rw_addr <= ifu.io.iccm.rw_addr @[quasar.scala 104:15] + ifu.io.exu_ifu.exu_bp.exu_mp_btag <= exu.io.exu_bp.exu_mp_btag @[quasar.scala 105:25] + ifu.io.exu_ifu.exu_bp.exu_mp_index <= exu.io.exu_bp.exu_mp_index @[quasar.scala 105:25] + ifu.io.exu_ifu.exu_bp.exu_mp_fghr <= exu.io.exu_bp.exu_mp_fghr @[quasar.scala 105:25] + ifu.io.exu_ifu.exu_bp.exu_mp_eghr <= exu.io.exu_bp.exu_mp_eghr @[quasar.scala 105:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.way <= exu.io.exu_bp.exu_mp_pkt.bits.way @[quasar.scala 105:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pja <= exu.io.exu_bp.exu_mp_pkt.bits.pja @[quasar.scala 105:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pret <= exu.io.exu_bp.exu_mp_pkt.bits.pret @[quasar.scala 105:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pcall <= exu.io.exu_bp.exu_mp_pkt.bits.pcall @[quasar.scala 105:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.prett <= exu.io.exu_bp.exu_mp_pkt.bits.prett @[quasar.scala 105:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.br_start_error <= exu.io.exu_bp.exu_mp_pkt.bits.br_start_error @[quasar.scala 105:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.br_error <= exu.io.exu_bp.exu_mp_pkt.bits.br_error @[quasar.scala 105:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.toffset <= exu.io.exu_bp.exu_mp_pkt.bits.toffset @[quasar.scala 105:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.hist <= exu.io.exu_bp.exu_mp_pkt.bits.hist @[quasar.scala 105:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pc4 <= exu.io.exu_bp.exu_mp_pkt.bits.pc4 @[quasar.scala 105:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.boffset <= exu.io.exu_bp.exu_mp_pkt.bits.boffset @[quasar.scala 105:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.ataken <= exu.io.exu_bp.exu_mp_pkt.bits.ataken @[quasar.scala 105:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.misp <= exu.io.exu_bp.exu_mp_pkt.bits.misp @[quasar.scala 105:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.valid <= exu.io.exu_bp.exu_mp_pkt.valid @[quasar.scala 105:25] + ifu.io.exu_ifu.exu_bp.exu_i0_br_way_r <= exu.io.exu_bp.exu_i0_br_way_r @[quasar.scala 105:25] + ifu.io.exu_ifu.exu_bp.exu_i0_br_fghr_r <= exu.io.exu_bp.exu_i0_br_fghr_r @[quasar.scala 105:25] + ifu.io.exu_ifu.exu_bp.exu_i0_br_index_r <= exu.io.exu_bp.exu_i0_br_index_r @[quasar.scala 105:25] + ifu.io.exu_ifu.exu_bp.exu_i0_br_fghr_r <= exu.io.exu_bp.exu_i0_br_fghr_r @[quasar.scala 106:42] + ifu.io.exu_ifu.exu_bp.exu_i0_br_index_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_index_r @[quasar.scala 107:43] + ifu.io.dec_tlu_flush_lower_wb <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[quasar.scala 108:33] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid @[quasar.scala 109:51] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid @[quasar.scala 109:51] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics @[quasar.scala 109:51] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata @[quasar.scala 109:51] + dec.reset <= io.core_rst_l @[quasar.scala 112:13] + dec.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 113:19] + dec.io.active_clk <= rvclkhdr_1.io.l1clk @[quasar.scala 114:21] + dec.io.lsu_fastint_stall_any <= lsu.io.lsu_fastint_stall_any @[quasar.scala 115:32] + dec.io.rst_vec <= io.rst_vec @[quasar.scala 116:18] + dec.io.nmi_int <= io.nmi_int @[quasar.scala 117:18] + dec.io.nmi_vec <= io.nmi_vec @[quasar.scala 118:18] + dec.io.i_cpu_halt_req <= io.i_cpu_halt_req @[quasar.scala 119:25] + dec.io.i_cpu_run_req <= io.i_cpu_run_req @[quasar.scala 120:24] + dec.io.core_id <= io.core_id @[quasar.scala 121:18] + dec.io.mpc_debug_halt_req <= io.mpc_debug_halt_req @[quasar.scala 122:29] + dec.io.mpc_debug_run_req <= io.mpc_debug_run_req @[quasar.scala 123:28] + dec.io.mpc_reset_run_req <= io.mpc_reset_run_req @[quasar.scala 124:28] + dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data @[quasar.scala 125:18] + dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_tag <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_tag @[quasar.scala 125:18] + dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_error <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_error @[quasar.scala 125:18] + dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_valid <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_valid @[quasar.scala 125:18] + dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_tag_r <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_tag_r @[quasar.scala 125:18] + dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_r <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_r @[quasar.scala 125:18] + dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_tag_m <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_tag_m @[quasar.scala 125:18] + dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_valid_m <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_valid_m @[quasar.scala 125:18] + dec.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_addr_any <= lsu.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_addr_any @[quasar.scala 125:18] + dec.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_store_any <= lsu.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_store_any @[quasar.scala 125:18] + dec.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_load_any <= lsu.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_load_any @[quasar.scala 125:18] + lsu.io.lsu_dec.tlu_busbuff.dec_tlu_sideeffect_posted_disable <= dec.io.lsu_dec.tlu_busbuff.dec_tlu_sideeffect_posted_disable @[quasar.scala 125:18] + lsu.io.lsu_dec.tlu_busbuff.dec_tlu_wb_coalescing_disable <= dec.io.lsu_dec.tlu_busbuff.dec_tlu_wb_coalescing_disable @[quasar.scala 125:18] + lsu.io.lsu_dec.tlu_busbuff.dec_tlu_external_ldfwd_disable <= dec.io.lsu_dec.tlu_busbuff.dec_tlu_external_ldfwd_disable @[quasar.scala 125:18] + dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_busy <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_busy @[quasar.scala 125:18] + dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_error <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_error @[quasar.scala 125:18] + dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_misaligned <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_misaligned @[quasar.scala 125:18] + dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_trxn <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_trxn @[quasar.scala 125:18] + dec.io.lsu_tlu.lsu_pmu_store_external_m <= lsu.io.lsu_tlu.lsu_pmu_store_external_m @[quasar.scala 126:18] + dec.io.lsu_tlu.lsu_pmu_load_external_m <= lsu.io.lsu_tlu.lsu_pmu_load_external_m @[quasar.scala 126:18] + dec.io.lsu_pmu_misaligned_m <= lsu.io.lsu_pmu_misaligned_m @[quasar.scala 127:31] + dec.io.dec_dma.tlu_dma.dma_iccm_stall_any <= dma_ctrl.io.dec_dma.tlu_dma.dma_iccm_stall_any @[quasar.scala 128:18] + dec.io.dec_dma.tlu_dma.dma_dccm_stall_any <= dma_ctrl.io.dec_dma.tlu_dma.dma_dccm_stall_any @[quasar.scala 128:18] + dma_ctrl.io.dec_dma.tlu_dma.dec_tlu_dma_qos_prty <= dec.io.dec_dma.tlu_dma.dec_tlu_dma_qos_prty @[quasar.scala 128:18] + dec.io.dec_dma.tlu_dma.dma_pmu_any_write <= dma_ctrl.io.dec_dma.tlu_dma.dma_pmu_any_write @[quasar.scala 128:18] + dec.io.dec_dma.tlu_dma.dma_pmu_any_read <= dma_ctrl.io.dec_dma.tlu_dma.dma_pmu_any_read @[quasar.scala 128:18] + dec.io.dec_dma.tlu_dma.dma_pmu_dccm_write <= dma_ctrl.io.dec_dma.tlu_dma.dma_pmu_dccm_write @[quasar.scala 128:18] + dec.io.dec_dma.tlu_dma.dma_pmu_dccm_read <= dma_ctrl.io.dec_dma.tlu_dma.dma_pmu_dccm_read @[quasar.scala 128:18] + dec.io.dec_dma.dctl_dma.dma_dccm_stall_any <= dma_ctrl.io.dec_dma.dctl_dma.dma_dccm_stall_any @[quasar.scala 128:18] + dec.io.lsu_fir_addr <= lsu.io.lsu_fir_addr @[quasar.scala 130:23] + dec.io.lsu_fir_error <= lsu.io.lsu_fir_error @[quasar.scala 131:24] + dec.io.lsu_trigger_match_m <= lsu.io.lsu_trigger_match_m @[quasar.scala 132:30] + dec.io.dec_dbg.dbg_dctl.dbg_cmd_wrdata <= dbg.io.dbg_dec.dbg_dctl.dbg_cmd_wrdata @[quasar.scala 133:18] + dec.io.dec_dbg.dbg_ib.dbg_cmd_addr <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_addr @[quasar.scala 133:18] + dec.io.dec_dbg.dbg_ib.dbg_cmd_type <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_type @[quasar.scala 133:18] + dec.io.dec_dbg.dbg_ib.dbg_cmd_write <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_write @[quasar.scala 133:18] + dec.io.dec_dbg.dbg_ib.dbg_cmd_valid <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_valid @[quasar.scala 133:18] + dec.io.lsu_idle_any <= lsu.io.lsu_idle_any @[quasar.scala 134:23] + dec.io.lsu_error_pkt_r.bits.addr <= lsu.io.lsu_error_pkt_r.bits.addr @[quasar.scala 135:26] + dec.io.lsu_error_pkt_r.bits.mscause <= lsu.io.lsu_error_pkt_r.bits.mscause @[quasar.scala 135:26] + dec.io.lsu_error_pkt_r.bits.exc_type <= lsu.io.lsu_error_pkt_r.bits.exc_type @[quasar.scala 135:26] + dec.io.lsu_error_pkt_r.bits.inst_type <= lsu.io.lsu_error_pkt_r.bits.inst_type @[quasar.scala 135:26] + dec.io.lsu_error_pkt_r.bits.single_ecc_error <= lsu.io.lsu_error_pkt_r.bits.single_ecc_error @[quasar.scala 135:26] + dec.io.lsu_error_pkt_r.valid <= lsu.io.lsu_error_pkt_r.valid @[quasar.scala 135:26] + dec.io.lsu_single_ecc_error_incr <= lsu.io.lsu_single_ecc_error_incr @[quasar.scala 136:36] + dec.io.exu_div_result <= exu.io.exu_div_result @[quasar.scala 137:25] + dec.io.exu_div_wren <= exu.io.exu_div_wren @[quasar.scala 138:23] + dec.io.lsu_result_m <= lsu.io.lsu_result_m @[quasar.scala 139:23] + dec.io.lsu_result_corr_r <= lsu.io.lsu_result_corr_r @[quasar.scala 140:28] + dec.io.lsu_load_stall_any <= lsu.io.lsu_load_stall_any @[quasar.scala 141:29] + dec.io.lsu_store_stall_any <= lsu.io.lsu_store_stall_any @[quasar.scala 142:30] + dec.io.iccm_dma_sb_error <= ifu.io.iccm_dma_sb_error @[quasar.scala 143:28] + dec.io.exu_flush_final <= exu.io.exu_flush_final @[quasar.scala 144:26] + dec.io.soft_int <= io.soft_int @[quasar.scala 146:19] + dec.io.dbg_halt_req <= dbg.io.dbg_halt_req @[quasar.scala 147:23] + dec.io.dbg_resume_req <= dbg.io.dbg_resume_req @[quasar.scala 148:25] + dec.io.exu_i0_br_way_r <= exu.io.exu_bp.exu_i0_br_way_r @[quasar.scala 149:26] + dec.io.timer_int <= io.timer_int @[quasar.scala 150:20] + dec.io.scan_mode <= io.scan_mode @[quasar.scala 151:20] + exu.io.dec_exu.gpr_exu.gpr_i0_rs2_d <= dec.io.dec_exu.gpr_exu.gpr_i0_rs2_d @[quasar.scala 154:18] + exu.io.dec_exu.gpr_exu.gpr_i0_rs1_d <= dec.io.dec_exu.gpr_exu.gpr_i0_rs1_d @[quasar.scala 154:18] + exu.io.dec_exu.ib_exu.dec_debug_wdata_rs1_d <= dec.io.dec_exu.ib_exu.dec_debug_wdata_rs1_d @[quasar.scala 154:18] + exu.io.dec_exu.ib_exu.dec_i0_pc_d <= dec.io.dec_exu.ib_exu.dec_i0_pc_d @[quasar.scala 154:18] + dec.io.dec_exu.tlu_exu.exu_npc_r <= exu.io.dec_exu.tlu_exu.exu_npc_r @[quasar.scala 154:18] + dec.io.dec_exu.tlu_exu.exu_pmu_i0_pc4 <= exu.io.dec_exu.tlu_exu.exu_pmu_i0_pc4 @[quasar.scala 154:18] + dec.io.dec_exu.tlu_exu.exu_pmu_i0_br_ataken <= exu.io.dec_exu.tlu_exu.exu_pmu_i0_br_ataken @[quasar.scala 154:18] + dec.io.dec_exu.tlu_exu.exu_pmu_i0_br_misp <= exu.io.dec_exu.tlu_exu.exu_pmu_i0_br_misp @[quasar.scala 154:18] + dec.io.dec_exu.tlu_exu.exu_i0_br_middle_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_middle_r @[quasar.scala 154:18] + dec.io.dec_exu.tlu_exu.exu_i0_br_mp_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_mp_r @[quasar.scala 154:18] + dec.io.dec_exu.tlu_exu.exu_i0_br_valid_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_valid_r @[quasar.scala 154:18] + dec.io.dec_exu.tlu_exu.exu_i0_br_index_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_index_r @[quasar.scala 154:18] + dec.io.dec_exu.tlu_exu.exu_i0_br_start_error_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_start_error_r @[quasar.scala 154:18] + dec.io.dec_exu.tlu_exu.exu_i0_br_error_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_error_r @[quasar.scala 154:18] + dec.io.dec_exu.tlu_exu.exu_i0_br_hist_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_hist_r @[quasar.scala 154:18] + exu.io.dec_exu.tlu_exu.dec_tlu_flush_path_r <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_path_r @[quasar.scala 154:18] + exu.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[quasar.scala 154:18] + exu.io.dec_exu.tlu_exu.dec_tlu_meihap <= dec.io.dec_exu.tlu_exu.dec_tlu_meihap @[quasar.scala 154:18] + dec.io.dec_exu.decode_exu.exu_csr_rs1_x <= exu.io.dec_exu.decode_exu.exu_csr_rs1_x @[quasar.scala 154:18] + dec.io.dec_exu.decode_exu.exu_i0_result_x <= exu.io.dec_exu.decode_exu.exu_i0_result_x @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.dec_extint_stall <= dec.io.dec_exu.decode_exu.dec_extint_stall @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.pred_correct_npc_x <= dec.io.dec_exu.decode_exu.pred_correct_npc_x @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.mul_p.bits.bfp <= dec.io.dec_exu.decode_exu.mul_p.bits.bfp @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.mul_p.bits.crc32c_w <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32c_w @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.mul_p.bits.crc32c_h <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32c_h @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.mul_p.bits.crc32c_b <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32c_b @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.mul_p.bits.crc32_w <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32_w @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.mul_p.bits.crc32_h <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32_h @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.mul_p.bits.crc32_b <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32_b @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.mul_p.bits.unshfl <= dec.io.dec_exu.decode_exu.mul_p.bits.unshfl @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.mul_p.bits.shfl <= dec.io.dec_exu.decode_exu.mul_p.bits.shfl @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.mul_p.bits.grev <= dec.io.dec_exu.decode_exu.mul_p.bits.grev @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.mul_p.bits.clmulr <= dec.io.dec_exu.decode_exu.mul_p.bits.clmulr @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.mul_p.bits.clmulh <= dec.io.dec_exu.decode_exu.mul_p.bits.clmulh @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.mul_p.bits.clmul <= dec.io.dec_exu.decode_exu.mul_p.bits.clmul @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.mul_p.bits.bdep <= dec.io.dec_exu.decode_exu.mul_p.bits.bdep @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.mul_p.bits.bext <= dec.io.dec_exu.decode_exu.mul_p.bits.bext @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.mul_p.bits.low <= dec.io.dec_exu.decode_exu.mul_p.bits.low @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.mul_p.bits.rs2_sign <= dec.io.dec_exu.decode_exu.mul_p.bits.rs2_sign @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.mul_p.bits.rs1_sign <= dec.io.dec_exu.decode_exu.mul_p.bits.rs1_sign @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.mul_p.valid <= dec.io.dec_exu.decode_exu.mul_p.valid @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.dec_i0_select_pc_d <= dec.io.dec_exu.decode_exu.dec_i0_select_pc_d @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.dec_i0_rs2_bypass_data_d <= dec.io.dec_exu.decode_exu.dec_i0_rs2_bypass_data_d @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.dec_i0_rs1_bypass_data_d <= dec.io.dec_exu.decode_exu.dec_i0_rs1_bypass_data_d @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.dec_i0_immed_d <= dec.io.dec_exu.decode_exu.dec_i0_immed_d @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.dec_i0_rs2_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs2_en_d @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.dec_i0_rs1_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs1_en_d @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.i0_predict_btag_d <= dec.io.dec_exu.decode_exu.i0_predict_btag_d @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.i0_predict_index_d <= dec.io.dec_exu.decode_exu.i0_predict_index_d @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.i0_predict_fghr_d <= dec.io.dec_exu.decode_exu.i0_predict_fghr_d @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.way <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.way @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pja <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pja @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pret <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pret @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pcall <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pcall @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.prett <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.prett @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_start_error <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_start_error @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_error <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_error @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.toffset <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.toffset @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.hist <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.hist @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pc4 <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pc4 @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.boffset <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.boffset @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.ataken <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.ataken @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.misp <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.misp @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.valid <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.valid @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.i0_ap.csr_imm <= dec.io.dec_exu.decode_exu.i0_ap.csr_imm @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.i0_ap.csr_write <= dec.io.dec_exu.decode_exu.i0_ap.csr_write @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.i0_ap.predict_nt <= dec.io.dec_exu.decode_exu.i0_ap.predict_nt @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.i0_ap.predict_t <= dec.io.dec_exu.decode_exu.i0_ap.predict_t @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.i0_ap.jal <= dec.io.dec_exu.decode_exu.i0_ap.jal @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.i0_ap.unsign <= dec.io.dec_exu.decode_exu.i0_ap.unsign @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.i0_ap.slt <= dec.io.dec_exu.decode_exu.i0_ap.slt @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.i0_ap.sub <= dec.io.dec_exu.decode_exu.i0_ap.sub @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.i0_ap.add <= dec.io.dec_exu.decode_exu.i0_ap.add @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.i0_ap.bge <= dec.io.dec_exu.decode_exu.i0_ap.bge @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.i0_ap.blt <= dec.io.dec_exu.decode_exu.i0_ap.blt @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.i0_ap.bne <= dec.io.dec_exu.decode_exu.i0_ap.bne @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.i0_ap.beq <= dec.io.dec_exu.decode_exu.i0_ap.beq @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.i0_ap.sra <= dec.io.dec_exu.decode_exu.i0_ap.sra @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.i0_ap.srl <= dec.io.dec_exu.decode_exu.i0_ap.srl @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.i0_ap.sll <= dec.io.dec_exu.decode_exu.i0_ap.sll @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.i0_ap.lxor <= dec.io.dec_exu.decode_exu.i0_ap.lxor @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.i0_ap.lor <= dec.io.dec_exu.decode_exu.i0_ap.lor @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.i0_ap.land <= dec.io.dec_exu.decode_exu.i0_ap.land @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.dec_ctl_en <= dec.io.dec_exu.decode_exu.dec_ctl_en @[quasar.scala 154:18] + exu.io.dec_exu.decode_exu.dec_data_en <= dec.io.dec_exu.decode_exu.dec_data_en @[quasar.scala 154:18] + exu.io.dec_exu.dec_div.dec_div_cancel <= dec.io.dec_exu.dec_div.dec_div_cancel @[quasar.scala 154:18] + exu.io.dec_exu.dec_div.div_p.bits.rem <= dec.io.dec_exu.dec_div.div_p.bits.rem @[quasar.scala 154:18] + exu.io.dec_exu.dec_div.div_p.bits.unsign <= dec.io.dec_exu.dec_div.div_p.bits.unsign @[quasar.scala 154:18] + exu.io.dec_exu.dec_div.div_p.valid <= dec.io.dec_exu.dec_div.div_p.valid @[quasar.scala 154:18] + dec.io.dec_exu.dec_alu.exu_i0_pc_x <= exu.io.dec_exu.dec_alu.exu_i0_pc_x @[quasar.scala 154:18] + exu.io.dec_exu.dec_alu.dec_i0_br_immed_d <= dec.io.dec_exu.dec_alu.dec_i0_br_immed_d @[quasar.scala 154:18] + exu.io.dec_exu.dec_alu.dec_csr_ren_d <= dec.io.dec_exu.dec_alu.dec_csr_ren_d @[quasar.scala 154:18] + exu.io.dec_exu.dec_alu.dec_i0_alu_decode_d <= dec.io.dec_exu.dec_alu.dec_i0_alu_decode_d @[quasar.scala 154:18] + exu.reset <= io.core_rst_l @[quasar.scala 155:13] + exu.io.scan_mode <= io.scan_mode @[quasar.scala 156:20] + exu.io.dbg_cmd_wrdata <= dbg.io.dbg_dec.dbg_dctl.dbg_cmd_wrdata @[quasar.scala 157:25] + lsu.reset <= io.core_rst_l @[quasar.scala 160:13] + lsu.io.clk_override <= dec.io.dec_tlu_lsu_clk_override @[quasar.scala 161:23] + lsu.io.dec_tlu_flush_lower_r <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[quasar.scala 162:32] + lsu.io.dec_tlu_i0_kill_writeb_r <= dec.io.dec_tlu_i0_kill_writeb_r @[quasar.scala 163:35] + lsu.io.dec_tlu_force_halt <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt @[quasar.scala 164:29] + lsu.io.dec_tlu_core_ecc_disable <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable @[quasar.scala 165:35] + lsu.io.lsu_exu.exu_lsu_rs2_d <= exu.io.lsu_exu.exu_lsu_rs2_d @[quasar.scala 166:18] + lsu.io.lsu_exu.exu_lsu_rs1_d <= exu.io.lsu_exu.exu_lsu_rs1_d @[quasar.scala 166:18] + lsu.io.dec_lsu_offset_d <= dec.io.dec_lsu_offset_d @[quasar.scala 167:27] + lsu.io.lsu_p.bits.store_data_bypass_m <= dec.io.lsu_p.bits.store_data_bypass_m @[quasar.scala 168:16] + lsu.io.lsu_p.bits.load_ldst_bypass_d <= dec.io.lsu_p.bits.load_ldst_bypass_d @[quasar.scala 168:16] + lsu.io.lsu_p.bits.store_data_bypass_d <= dec.io.lsu_p.bits.store_data_bypass_d @[quasar.scala 168:16] + lsu.io.lsu_p.bits.dma <= dec.io.lsu_p.bits.dma @[quasar.scala 168:16] + lsu.io.lsu_p.bits.unsign <= dec.io.lsu_p.bits.unsign @[quasar.scala 168:16] + lsu.io.lsu_p.bits.store <= dec.io.lsu_p.bits.store @[quasar.scala 168:16] + lsu.io.lsu_p.bits.load <= dec.io.lsu_p.bits.load @[quasar.scala 168:16] + lsu.io.lsu_p.bits.dword <= dec.io.lsu_p.bits.dword @[quasar.scala 168:16] + lsu.io.lsu_p.bits.word <= dec.io.lsu_p.bits.word @[quasar.scala 168:16] + lsu.io.lsu_p.bits.half <= dec.io.lsu_p.bits.half @[quasar.scala 168:16] + lsu.io.lsu_p.bits.by <= dec.io.lsu_p.bits.by @[quasar.scala 168:16] + lsu.io.lsu_p.bits.fast_int <= dec.io.lsu_p.bits.fast_int @[quasar.scala 168:16] + lsu.io.lsu_p.valid <= dec.io.lsu_p.valid @[quasar.scala 168:16] + lsu.io.dec_lsu_valid_raw_d <= dec.io.dec_lsu_valid_raw_d @[quasar.scala 169:30] + lsu.io.dec_tlu_mrac_ff <= dec.io.ifu_dec.dec_ifc.dec_tlu_mrac_ff @[quasar.scala 170:26] + lsu.io.trigger_pkt_any[0].tdata2 <= dec.io.trigger_pkt_any[0].tdata2 @[quasar.scala 171:26] + lsu.io.trigger_pkt_any[0].m <= dec.io.trigger_pkt_any[0].m @[quasar.scala 171:26] + lsu.io.trigger_pkt_any[0].execute <= dec.io.trigger_pkt_any[0].execute @[quasar.scala 171:26] + lsu.io.trigger_pkt_any[0].load <= dec.io.trigger_pkt_any[0].load @[quasar.scala 171:26] + lsu.io.trigger_pkt_any[0].store <= dec.io.trigger_pkt_any[0].store @[quasar.scala 171:26] + lsu.io.trigger_pkt_any[0].match_pkt <= dec.io.trigger_pkt_any[0].match_pkt @[quasar.scala 171:26] + lsu.io.trigger_pkt_any[0].select <= dec.io.trigger_pkt_any[0].select @[quasar.scala 171:26] + lsu.io.trigger_pkt_any[1].tdata2 <= dec.io.trigger_pkt_any[1].tdata2 @[quasar.scala 171:26] + lsu.io.trigger_pkt_any[1].m <= dec.io.trigger_pkt_any[1].m @[quasar.scala 171:26] + lsu.io.trigger_pkt_any[1].execute <= dec.io.trigger_pkt_any[1].execute @[quasar.scala 171:26] + lsu.io.trigger_pkt_any[1].load <= dec.io.trigger_pkt_any[1].load @[quasar.scala 171:26] + lsu.io.trigger_pkt_any[1].store <= dec.io.trigger_pkt_any[1].store @[quasar.scala 171:26] + lsu.io.trigger_pkt_any[1].match_pkt <= dec.io.trigger_pkt_any[1].match_pkt @[quasar.scala 171:26] + lsu.io.trigger_pkt_any[1].select <= dec.io.trigger_pkt_any[1].select @[quasar.scala 171:26] + lsu.io.trigger_pkt_any[2].tdata2 <= dec.io.trigger_pkt_any[2].tdata2 @[quasar.scala 171:26] + lsu.io.trigger_pkt_any[2].m <= dec.io.trigger_pkt_any[2].m @[quasar.scala 171:26] + lsu.io.trigger_pkt_any[2].execute <= dec.io.trigger_pkt_any[2].execute @[quasar.scala 171:26] + lsu.io.trigger_pkt_any[2].load <= dec.io.trigger_pkt_any[2].load @[quasar.scala 171:26] + lsu.io.trigger_pkt_any[2].store <= dec.io.trigger_pkt_any[2].store @[quasar.scala 171:26] + lsu.io.trigger_pkt_any[2].match_pkt <= dec.io.trigger_pkt_any[2].match_pkt @[quasar.scala 171:26] + lsu.io.trigger_pkt_any[2].select <= dec.io.trigger_pkt_any[2].select @[quasar.scala 171:26] + lsu.io.trigger_pkt_any[3].tdata2 <= dec.io.trigger_pkt_any[3].tdata2 @[quasar.scala 171:26] + lsu.io.trigger_pkt_any[3].m <= dec.io.trigger_pkt_any[3].m @[quasar.scala 171:26] + lsu.io.trigger_pkt_any[3].execute <= dec.io.trigger_pkt_any[3].execute @[quasar.scala 171:26] + lsu.io.trigger_pkt_any[3].load <= dec.io.trigger_pkt_any[3].load @[quasar.scala 171:26] + lsu.io.trigger_pkt_any[3].store <= dec.io.trigger_pkt_any[3].store @[quasar.scala 171:26] + lsu.io.trigger_pkt_any[3].match_pkt <= dec.io.trigger_pkt_any[3].match_pkt @[quasar.scala 171:26] + lsu.io.trigger_pkt_any[3].select <= dec.io.trigger_pkt_any[3].select @[quasar.scala 171:26] + lsu.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[quasar.scala 173:25] + lsu.io.lsu_dma.dma_mem_tag <= dma_ctrl.io.lsu_dma.dma_mem_tag @[quasar.scala 174:18] + dma_ctrl.io.lsu_dma.dccm_ready <= lsu.io.lsu_dma.dccm_ready @[quasar.scala 174:18] + dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_rdata <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_rdata @[quasar.scala 174:18] + dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag @[quasar.scala 174:18] + dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error @[quasar.scala 174:18] + dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid @[quasar.scala 174:18] + lsu.io.lsu_dma.dma_dccm_ctl.dma_mem_wdata <= dma_ctrl.io.lsu_dma.dma_dccm_ctl.dma_mem_wdata @[quasar.scala 174:18] + lsu.io.lsu_dma.dma_dccm_ctl.dma_mem_addr <= dma_ctrl.io.lsu_dma.dma_dccm_ctl.dma_mem_addr @[quasar.scala 174:18] + lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_wdata <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_wdata @[quasar.scala 174:18] + lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_write <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_write @[quasar.scala 174:18] + lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_sz <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_sz @[quasar.scala 174:18] + lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_addr <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_addr @[quasar.scala 174:18] + lsu.io.lsu_dma.dma_lsc_ctl.dma_dccm_req <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_dccm_req @[quasar.scala 174:18] + lsu.io.scan_mode <= io.scan_mode @[quasar.scala 175:20] + lsu.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 176:19] + dbg.reset <= io.core_rst_l @[quasar.scala 179:13] + node _T_8 = mux(dma_ctrl.io.dma_dbg_cmd_done, dma_ctrl.io.dma_dbg_rddata, dec.io.dec_dbg_rddata) @[quasar.scala 180:32] + dbg.io.core_dbg_rddata <= _T_8 @[quasar.scala 180:26] + node _T_9 = or(dma_ctrl.io.dma_dbg_cmd_done, dec.io.dec_dbg_cmd_done) @[quasar.scala 181:60] + dbg.io.core_dbg_cmd_done <= _T_9 @[quasar.scala 181:28] + node _T_10 = or(dma_ctrl.io.dma_dbg_cmd_fail, dec.io.dec_dbg_cmd_fail) @[quasar.scala 182:60] + dbg.io.core_dbg_cmd_fail <= _T_10 @[quasar.scala 182:28] + dbg.io.dec_tlu_debug_mode <= dec.io.dec_tlu_debug_mode @[quasar.scala 183:29] + dbg.io.dec_tlu_dbg_halted <= dec.io.dec_tlu_dbg_halted @[quasar.scala 184:29] + dbg.io.dec_tlu_mpc_halted_only <= dec.io.dec_tlu_mpc_halted_only @[quasar.scala 185:34] + dbg.io.dec_tlu_resume_ack <= dec.io.dec_tlu_resume_ack @[quasar.scala 186:29] + dbg.io.dmi_reg_en <= io.dmi_reg_en @[quasar.scala 187:21] + dbg.io.dmi_reg_addr <= io.dmi_reg_addr @[quasar.scala 188:23] + dbg.io.dmi_reg_wr_en <= io.dmi_reg_wr_en @[quasar.scala 189:24] + dbg.io.dmi_reg_wdata <= io.dmi_reg_wdata @[quasar.scala 190:24] + dbg.io.dbg_bus_clk_en <= io.dbg_bus_clk_en @[quasar.scala 191:25] + node _T_11 = asUInt(io.dbg_rst_l) @[quasar.scala 192:42] + dbg.io.dbg_rst_l <= _T_11 @[quasar.scala 192:20] + dbg.io.clk_override <= dec.io.dec_tlu_misc_clk_override @[quasar.scala 193:23] + dbg.io.scan_mode <= io.scan_mode @[quasar.scala 194:20] + dma_ctrl.reset <= io.core_rst_l @[quasar.scala 198:18] + dma_ctrl.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 199:24] + dma_ctrl.io.dma_bus_clk_en <= io.dma_bus_clk_en @[quasar.scala 200:30] + dma_ctrl.io.clk_override <= dec.io.dec_tlu_misc_clk_override @[quasar.scala 201:28] + dma_ctrl.io.scan_mode <= io.scan_mode @[quasar.scala 202:25] + dma_ctrl.io.dbg_dma.dbg_dctl.dbg_cmd_wrdata <= dbg.io.dbg_dma.dbg_dctl.dbg_cmd_wrdata @[quasar.scala 203:23] + dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_addr <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_addr @[quasar.scala 203:23] + dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_type <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_type @[quasar.scala 203:23] + dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_write <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_write @[quasar.scala 203:23] + dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_valid <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_valid @[quasar.scala 203:23] + dbg.io.dbg_dma_io.dma_dbg_ready <= dma_ctrl.io.dbg_dma_io.dma_dbg_ready @[quasar.scala 204:26] + dma_ctrl.io.dbg_dma_io.dbg_dma_bubble <= dbg.io.dbg_dma_io.dbg_dma_bubble @[quasar.scala 204:26] + dma_ctrl.io.dbg_cmd_size <= dbg.io.dbg_cmd_size @[quasar.scala 205:28] + dma_ctrl.io.iccm_dma_rvalid <= ifu.io.iccm_dma_rvalid @[quasar.scala 206:31] + dma_ctrl.io.iccm_dma_rtag <= ifu.io.iccm_dma_rtag @[quasar.scala 207:29] + dma_ctrl.io.iccm_dma_rdata <= ifu.io.iccm_dma_rdata @[quasar.scala 208:30] + dma_ctrl.io.iccm_ready <= ifu.io.iccm_ready @[quasar.scala 209:26] + dma_ctrl.io.iccm_dma_ecc_error <= ifu.io.iccm_dma_ecc_error @[quasar.scala 210:34] + pic_ctrl_inst.io.scan_mode <= io.scan_mode @[quasar.scala 213:30] + pic_ctrl_inst.reset <= io.core_rst_l @[quasar.scala 214:23] + pic_ctrl_inst.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 215:29] + pic_ctrl_inst.io.active_clk <= rvclkhdr_1.io.l1clk @[quasar.scala 216:31] + pic_ctrl_inst.io.clk_override <= dec.io.dec_tlu_pic_clk_override @[quasar.scala 217:33] + pic_ctrl_inst.io.extintsrc_req <= io.extintsrc_req @[quasar.scala 218:34] + lsu.io.lsu_pic.picm_rd_data <= pic_ctrl_inst.io.lsu_pic.picm_rd_data @[quasar.scala 219:28] + pic_ctrl_inst.io.lsu_pic.picm_wr_data <= lsu.io.lsu_pic.picm_wr_data @[quasar.scala 219:28] + pic_ctrl_inst.io.lsu_pic.picm_wraddr <= lsu.io.lsu_pic.picm_wraddr @[quasar.scala 219:28] + pic_ctrl_inst.io.lsu_pic.picm_rdaddr <= lsu.io.lsu_pic.picm_rdaddr @[quasar.scala 219:28] + pic_ctrl_inst.io.lsu_pic.picm_mken <= lsu.io.lsu_pic.picm_mken @[quasar.scala 219:28] + pic_ctrl_inst.io.lsu_pic.picm_rden <= lsu.io.lsu_pic.picm_rden @[quasar.scala 219:28] + pic_ctrl_inst.io.lsu_pic.picm_wren <= lsu.io.lsu_pic.picm_wren @[quasar.scala 219:28] + dec.io.dec_pic.mexintpend <= pic_ctrl_inst.io.dec_pic.mexintpend @[quasar.scala 220:28] + pic_ctrl_inst.io.dec_pic.dec_tlu_meipt <= dec.io.dec_pic.dec_tlu_meipt @[quasar.scala 220:28] + pic_ctrl_inst.io.dec_pic.dec_tlu_meicurpl <= dec.io.dec_pic.dec_tlu_meicurpl @[quasar.scala 220:28] + dec.io.dec_pic.mhwakeup <= pic_ctrl_inst.io.dec_pic.mhwakeup @[quasar.scala 220:28] + dec.io.dec_pic.pic_pl <= pic_ctrl_inst.io.dec_pic.pic_pl @[quasar.scala 220:28] + dec.io.dec_pic.pic_claimid <= pic_ctrl_inst.io.dec_pic.pic_claimid @[quasar.scala 220:28] + io.rv_trace_pkt.rv_i_tval_ip <= dec.io.rv_trace_pkt.rv_i_tval_ip @[quasar.scala 222:19] + io.rv_trace_pkt.rv_i_interrupt_ip <= dec.io.rv_trace_pkt.rv_i_interrupt_ip @[quasar.scala 222:19] + io.rv_trace_pkt.rv_i_ecause_ip <= dec.io.rv_trace_pkt.rv_i_ecause_ip @[quasar.scala 222:19] + io.rv_trace_pkt.rv_i_exception_ip <= dec.io.rv_trace_pkt.rv_i_exception_ip @[quasar.scala 222:19] + io.rv_trace_pkt.rv_i_address_ip <= dec.io.rv_trace_pkt.rv_i_address_ip @[quasar.scala 222:19] + io.rv_trace_pkt.rv_i_insn_ip <= dec.io.rv_trace_pkt.rv_i_insn_ip @[quasar.scala 222:19] + io.rv_trace_pkt.rv_i_valid_ip <= dec.io.rv_trace_pkt.rv_i_valid_ip @[quasar.scala 222:19] + io.dccm_clk_override <= dec.io.dec_tlu_dccm_clk_override @[quasar.scala 225:24] + io.icm_clk_override <= dec.io.dec_tlu_icm_clk_override @[quasar.scala 226:23] + io.dec_tlu_core_ecc_disable <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable @[quasar.scala 227:31] + io.o_cpu_halt_ack <= dec.io.o_cpu_halt_ack @[quasar.scala 228:21] + io.o_cpu_halt_status <= dec.io.o_cpu_halt_status @[quasar.scala 229:24] + io.o_cpu_run_ack <= dec.io.o_cpu_run_ack @[quasar.scala 230:20] + io.o_debug_mode_status <= dec.io.o_debug_mode_status @[quasar.scala 231:26] + io.mpc_debug_halt_ack <= dec.io.mpc_debug_halt_ack @[quasar.scala 232:25] + io.mpc_debug_run_ack <= dec.io.mpc_debug_run_ack @[quasar.scala 233:24] + io.debug_brkpt_status <= dec.io.debug_brkpt_status @[quasar.scala 234:25] + io.dec_tlu_perfcnt0 <= dec.io.dec_tlu_perfcnt0 @[quasar.scala 235:23] + io.dec_tlu_perfcnt1 <= dec.io.dec_tlu_perfcnt1 @[quasar.scala 236:23] + io.dec_tlu_perfcnt2 <= dec.io.dec_tlu_perfcnt2 @[quasar.scala 237:23] + io.dec_tlu_perfcnt3 <= dec.io.dec_tlu_perfcnt3 @[quasar.scala 238:23] + io.dmi_reg_rdata <= dbg.io.dmi_reg_rdata @[quasar.scala 239:20] + lsu.io.dccm.rd_data_hi <= io.dccm.rd_data_hi @[quasar.scala 242:11] + lsu.io.dccm.rd_data_lo <= io.dccm.rd_data_lo @[quasar.scala 242:11] + io.dccm.wr_data_hi <= lsu.io.dccm.wr_data_hi @[quasar.scala 242:11] + io.dccm.wr_data_lo <= lsu.io.dccm.wr_data_lo @[quasar.scala 242:11] + io.dccm.rd_addr_hi <= lsu.io.dccm.rd_addr_hi @[quasar.scala 242:11] + io.dccm.rd_addr_lo <= lsu.io.dccm.rd_addr_lo @[quasar.scala 242:11] + io.dccm.wr_addr_hi <= lsu.io.dccm.wr_addr_hi @[quasar.scala 242:11] + io.dccm.wr_addr_lo <= lsu.io.dccm.wr_addr_lo @[quasar.scala 242:11] + io.dccm.rden <= lsu.io.dccm.rden @[quasar.scala 242:11] + io.dccm.wren <= lsu.io.dccm.wren @[quasar.scala 242:11] + inst axi4_to_ahb of axi4_to_ahb @[quasar.scala 245:32] axi4_to_ahb.clock <= clock axi4_to_ahb.reset <= reset - inst axi4_to_ahb_1 of axi4_to_ahb_1 @[quasar.scala 243:33] + inst axi4_to_ahb_1 of axi4_to_ahb_1 @[quasar.scala 246:33] axi4_to_ahb_1.clock <= clock axi4_to_ahb_1.reset <= reset - inst axi4_to_ahb_2 of axi4_to_ahb_2 @[quasar.scala 244:33] + inst axi4_to_ahb_2 of axi4_to_ahb_2 @[quasar.scala 247:33] axi4_to_ahb_2.clock <= clock axi4_to_ahb_2.reset <= reset - inst ahb_to_axi4 of ahb_to_axi4 @[quasar.scala 245:33] + inst ahb_to_axi4 of ahb_to_axi4 @[quasar.scala 248:33] ahb_to_axi4.clock <= clock ahb_to_axi4.reset <= reset - axi4_to_ahb_2.io.scan_mode <= io.scan_mode @[quasar.scala 247:34] - axi4_to_ahb_2.io.bus_clk_en <= io.lsu_bus_clk_en @[quasar.scala 248:35] - axi4_to_ahb_2.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 249:37] - lsu.io.axi.r.bits.last <= axi4_to_ahb_2.io.axi.r.bits.last @[quasar.scala 250:28] - lsu.io.axi.r.bits.resp <= axi4_to_ahb_2.io.axi.r.bits.resp @[quasar.scala 250:28] - lsu.io.axi.r.bits.data <= axi4_to_ahb_2.io.axi.r.bits.data @[quasar.scala 250:28] - lsu.io.axi.r.bits.id <= axi4_to_ahb_2.io.axi.r.bits.id @[quasar.scala 250:28] - lsu.io.axi.r.valid <= axi4_to_ahb_2.io.axi.r.valid @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.r.ready <= lsu.io.axi.r.ready @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.ar.bits.qos <= lsu.io.axi.ar.bits.qos @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.ar.bits.prot <= lsu.io.axi.ar.bits.prot @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.ar.bits.cache <= lsu.io.axi.ar.bits.cache @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.ar.bits.lock <= lsu.io.axi.ar.bits.lock @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.ar.bits.burst <= lsu.io.axi.ar.bits.burst @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.ar.bits.size <= lsu.io.axi.ar.bits.size @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.ar.bits.len <= lsu.io.axi.ar.bits.len @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.ar.bits.region <= lsu.io.axi.ar.bits.region @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.ar.bits.addr <= lsu.io.axi.ar.bits.addr @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.ar.bits.id <= lsu.io.axi.ar.bits.id @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.ar.valid <= lsu.io.axi.ar.valid @[quasar.scala 250:28] - lsu.io.axi.ar.ready <= axi4_to_ahb_2.io.axi.ar.ready @[quasar.scala 250:28] - lsu.io.axi.b.bits.id <= axi4_to_ahb_2.io.axi.b.bits.id @[quasar.scala 250:28] - lsu.io.axi.b.bits.resp <= axi4_to_ahb_2.io.axi.b.bits.resp @[quasar.scala 250:28] - lsu.io.axi.b.valid <= axi4_to_ahb_2.io.axi.b.valid @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.b.ready <= lsu.io.axi.b.ready @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.w.bits.last <= lsu.io.axi.w.bits.last @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.w.bits.strb <= lsu.io.axi.w.bits.strb @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.w.bits.data <= lsu.io.axi.w.bits.data @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.w.valid <= lsu.io.axi.w.valid @[quasar.scala 250:28] - lsu.io.axi.w.ready <= axi4_to_ahb_2.io.axi.w.ready @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.aw.bits.qos <= lsu.io.axi.aw.bits.qos @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.aw.bits.prot <= lsu.io.axi.aw.bits.prot @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.aw.bits.cache <= lsu.io.axi.aw.bits.cache @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.aw.bits.lock <= lsu.io.axi.aw.bits.lock @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.aw.bits.burst <= lsu.io.axi.aw.bits.burst @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.aw.bits.size <= lsu.io.axi.aw.bits.size @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.aw.bits.len <= lsu.io.axi.aw.bits.len @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.aw.bits.region <= lsu.io.axi.aw.bits.region @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.aw.bits.addr <= lsu.io.axi.aw.bits.addr @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.aw.bits.id <= lsu.io.axi.aw.bits.id @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.aw.valid <= lsu.io.axi.aw.valid @[quasar.scala 250:28] - lsu.io.axi.aw.ready <= axi4_to_ahb_2.io.axi.aw.ready @[quasar.scala 250:28] - io.lsu_ahb.out.hwdata <= axi4_to_ahb_2.io.ahb.out.hwdata @[quasar.scala 251:28] - io.lsu_ahb.out.hwrite <= axi4_to_ahb_2.io.ahb.out.hwrite @[quasar.scala 251:28] - io.lsu_ahb.out.htrans <= axi4_to_ahb_2.io.ahb.out.htrans @[quasar.scala 251:28] - io.lsu_ahb.out.hsize <= axi4_to_ahb_2.io.ahb.out.hsize @[quasar.scala 251:28] - io.lsu_ahb.out.hprot <= axi4_to_ahb_2.io.ahb.out.hprot @[quasar.scala 251:28] - io.lsu_ahb.out.hmastlock <= axi4_to_ahb_2.io.ahb.out.hmastlock @[quasar.scala 251:28] - io.lsu_ahb.out.hburst <= axi4_to_ahb_2.io.ahb.out.hburst @[quasar.scala 251:28] - io.lsu_ahb.out.haddr <= axi4_to_ahb_2.io.ahb.out.haddr @[quasar.scala 251:28] - axi4_to_ahb_2.io.ahb.in.hresp <= io.lsu_ahb.in.hresp @[quasar.scala 251:28] - axi4_to_ahb_2.io.ahb.in.hready <= io.lsu_ahb.in.hready @[quasar.scala 251:28] - axi4_to_ahb_2.io.ahb.in.hrdata <= io.lsu_ahb.in.hrdata @[quasar.scala 251:28] - axi4_to_ahb_1.io.scan_mode <= io.scan_mode @[quasar.scala 254:34] - axi4_to_ahb_1.io.bus_clk_en <= io.ifu_bus_clk_en @[quasar.scala 255:35] - axi4_to_ahb_1.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 256:37] - ifu.io.ifu.r.bits.last <= axi4_to_ahb_1.io.axi.r.bits.last @[quasar.scala 257:28] - ifu.io.ifu.r.bits.resp <= axi4_to_ahb_1.io.axi.r.bits.resp @[quasar.scala 257:28] - ifu.io.ifu.r.bits.data <= axi4_to_ahb_1.io.axi.r.bits.data @[quasar.scala 257:28] - ifu.io.ifu.r.bits.id <= axi4_to_ahb_1.io.axi.r.bits.id @[quasar.scala 257:28] - ifu.io.ifu.r.valid <= axi4_to_ahb_1.io.axi.r.valid @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.r.ready <= ifu.io.ifu.r.ready @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.ar.bits.qos <= ifu.io.ifu.ar.bits.qos @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.ar.bits.prot <= ifu.io.ifu.ar.bits.prot @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.ar.bits.cache <= ifu.io.ifu.ar.bits.cache @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.ar.bits.lock <= ifu.io.ifu.ar.bits.lock @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.ar.bits.burst <= ifu.io.ifu.ar.bits.burst @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.ar.bits.size <= ifu.io.ifu.ar.bits.size @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.ar.bits.len <= ifu.io.ifu.ar.bits.len @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.ar.bits.region <= ifu.io.ifu.ar.bits.region @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.ar.bits.addr <= ifu.io.ifu.ar.bits.addr @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.ar.bits.id <= ifu.io.ifu.ar.bits.id @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.ar.valid <= ifu.io.ifu.ar.valid @[quasar.scala 257:28] - ifu.io.ifu.ar.ready <= axi4_to_ahb_1.io.axi.ar.ready @[quasar.scala 257:28] - ifu.io.ifu.b.bits.id <= axi4_to_ahb_1.io.axi.b.bits.id @[quasar.scala 257:28] - ifu.io.ifu.b.bits.resp <= axi4_to_ahb_1.io.axi.b.bits.resp @[quasar.scala 257:28] - ifu.io.ifu.b.valid <= axi4_to_ahb_1.io.axi.b.valid @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.b.ready <= ifu.io.ifu.b.ready @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.w.bits.last <= ifu.io.ifu.w.bits.last @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.w.bits.strb <= ifu.io.ifu.w.bits.strb @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.w.bits.data <= ifu.io.ifu.w.bits.data @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.w.valid <= ifu.io.ifu.w.valid @[quasar.scala 257:28] - ifu.io.ifu.w.ready <= axi4_to_ahb_1.io.axi.w.ready @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.aw.bits.qos <= ifu.io.ifu.aw.bits.qos @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.aw.bits.prot <= ifu.io.ifu.aw.bits.prot @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.aw.bits.cache <= ifu.io.ifu.aw.bits.cache @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.aw.bits.lock <= ifu.io.ifu.aw.bits.lock @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.aw.bits.burst <= ifu.io.ifu.aw.bits.burst @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.aw.bits.size <= ifu.io.ifu.aw.bits.size @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.aw.bits.len <= ifu.io.ifu.aw.bits.len @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.aw.bits.region <= ifu.io.ifu.aw.bits.region @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.aw.bits.addr <= ifu.io.ifu.aw.bits.addr @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.aw.bits.id <= ifu.io.ifu.aw.bits.id @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.aw.valid <= ifu.io.ifu.aw.valid @[quasar.scala 257:28] - ifu.io.ifu.aw.ready <= axi4_to_ahb_1.io.axi.aw.ready @[quasar.scala 257:28] - io.ifu_ahb.out.hwdata <= axi4_to_ahb_1.io.ahb.out.hwdata @[quasar.scala 258:28] - io.ifu_ahb.out.hwrite <= axi4_to_ahb_1.io.ahb.out.hwrite @[quasar.scala 258:28] - io.ifu_ahb.out.htrans <= axi4_to_ahb_1.io.ahb.out.htrans @[quasar.scala 258:28] - io.ifu_ahb.out.hsize <= axi4_to_ahb_1.io.ahb.out.hsize @[quasar.scala 258:28] - io.ifu_ahb.out.hprot <= axi4_to_ahb_1.io.ahb.out.hprot @[quasar.scala 258:28] - io.ifu_ahb.out.hmastlock <= axi4_to_ahb_1.io.ahb.out.hmastlock @[quasar.scala 258:28] - io.ifu_ahb.out.hburst <= axi4_to_ahb_1.io.ahb.out.hburst @[quasar.scala 258:28] - io.ifu_ahb.out.haddr <= axi4_to_ahb_1.io.ahb.out.haddr @[quasar.scala 258:28] - axi4_to_ahb_1.io.ahb.in.hresp <= io.ifu_ahb.in.hresp @[quasar.scala 258:28] - axi4_to_ahb_1.io.ahb.in.hready <= io.ifu_ahb.in.hready @[quasar.scala 258:28] - axi4_to_ahb_1.io.ahb.in.hrdata <= io.ifu_ahb.in.hrdata @[quasar.scala 258:28] - axi4_to_ahb.io.scan_mode <= io.scan_mode @[quasar.scala 260:33] - axi4_to_ahb.io.bus_clk_en <= io.dbg_bus_clk_en @[quasar.scala 261:34] - axi4_to_ahb.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 262:36] - dbg.io.sb_axi.r.bits.last <= axi4_to_ahb.io.axi.r.bits.last @[quasar.scala 263:27] - dbg.io.sb_axi.r.bits.resp <= axi4_to_ahb.io.axi.r.bits.resp @[quasar.scala 263:27] - dbg.io.sb_axi.r.bits.data <= axi4_to_ahb.io.axi.r.bits.data @[quasar.scala 263:27] - dbg.io.sb_axi.r.bits.id <= axi4_to_ahb.io.axi.r.bits.id @[quasar.scala 263:27] - dbg.io.sb_axi.r.valid <= axi4_to_ahb.io.axi.r.valid @[quasar.scala 263:27] - axi4_to_ahb.io.axi.r.ready <= dbg.io.sb_axi.r.ready @[quasar.scala 263:27] - axi4_to_ahb.io.axi.ar.bits.qos <= dbg.io.sb_axi.ar.bits.qos @[quasar.scala 263:27] - axi4_to_ahb.io.axi.ar.bits.prot <= dbg.io.sb_axi.ar.bits.prot @[quasar.scala 263:27] - axi4_to_ahb.io.axi.ar.bits.cache <= dbg.io.sb_axi.ar.bits.cache @[quasar.scala 263:27] - axi4_to_ahb.io.axi.ar.bits.lock <= dbg.io.sb_axi.ar.bits.lock @[quasar.scala 263:27] - axi4_to_ahb.io.axi.ar.bits.burst <= dbg.io.sb_axi.ar.bits.burst @[quasar.scala 263:27] - axi4_to_ahb.io.axi.ar.bits.size <= dbg.io.sb_axi.ar.bits.size @[quasar.scala 263:27] - axi4_to_ahb.io.axi.ar.bits.len <= dbg.io.sb_axi.ar.bits.len @[quasar.scala 263:27] - axi4_to_ahb.io.axi.ar.bits.region <= dbg.io.sb_axi.ar.bits.region @[quasar.scala 263:27] - axi4_to_ahb.io.axi.ar.bits.addr <= dbg.io.sb_axi.ar.bits.addr @[quasar.scala 263:27] - axi4_to_ahb.io.axi.ar.bits.id <= dbg.io.sb_axi.ar.bits.id @[quasar.scala 263:27] - axi4_to_ahb.io.axi.ar.valid <= dbg.io.sb_axi.ar.valid @[quasar.scala 263:27] - dbg.io.sb_axi.ar.ready <= axi4_to_ahb.io.axi.ar.ready @[quasar.scala 263:27] - dbg.io.sb_axi.b.bits.id <= axi4_to_ahb.io.axi.b.bits.id @[quasar.scala 263:27] - dbg.io.sb_axi.b.bits.resp <= axi4_to_ahb.io.axi.b.bits.resp @[quasar.scala 263:27] - dbg.io.sb_axi.b.valid <= axi4_to_ahb.io.axi.b.valid @[quasar.scala 263:27] - axi4_to_ahb.io.axi.b.ready <= dbg.io.sb_axi.b.ready @[quasar.scala 263:27] - axi4_to_ahb.io.axi.w.bits.last <= dbg.io.sb_axi.w.bits.last @[quasar.scala 263:27] - axi4_to_ahb.io.axi.w.bits.strb <= dbg.io.sb_axi.w.bits.strb @[quasar.scala 263:27] - axi4_to_ahb.io.axi.w.bits.data <= dbg.io.sb_axi.w.bits.data @[quasar.scala 263:27] - axi4_to_ahb.io.axi.w.valid <= dbg.io.sb_axi.w.valid @[quasar.scala 263:27] - dbg.io.sb_axi.w.ready <= axi4_to_ahb.io.axi.w.ready @[quasar.scala 263:27] - axi4_to_ahb.io.axi.aw.bits.qos <= dbg.io.sb_axi.aw.bits.qos @[quasar.scala 263:27] - axi4_to_ahb.io.axi.aw.bits.prot <= dbg.io.sb_axi.aw.bits.prot @[quasar.scala 263:27] - axi4_to_ahb.io.axi.aw.bits.cache <= dbg.io.sb_axi.aw.bits.cache @[quasar.scala 263:27] - axi4_to_ahb.io.axi.aw.bits.lock <= dbg.io.sb_axi.aw.bits.lock @[quasar.scala 263:27] - axi4_to_ahb.io.axi.aw.bits.burst <= dbg.io.sb_axi.aw.bits.burst @[quasar.scala 263:27] - axi4_to_ahb.io.axi.aw.bits.size <= dbg.io.sb_axi.aw.bits.size @[quasar.scala 263:27] - axi4_to_ahb.io.axi.aw.bits.len <= dbg.io.sb_axi.aw.bits.len @[quasar.scala 263:27] - axi4_to_ahb.io.axi.aw.bits.region <= dbg.io.sb_axi.aw.bits.region @[quasar.scala 263:27] - axi4_to_ahb.io.axi.aw.bits.addr <= dbg.io.sb_axi.aw.bits.addr @[quasar.scala 263:27] - axi4_to_ahb.io.axi.aw.bits.id <= dbg.io.sb_axi.aw.bits.id @[quasar.scala 263:27] - axi4_to_ahb.io.axi.aw.valid <= dbg.io.sb_axi.aw.valid @[quasar.scala 263:27] - dbg.io.sb_axi.aw.ready <= axi4_to_ahb.io.axi.aw.ready @[quasar.scala 263:27] - io.sb_ahb.out.hwdata <= axi4_to_ahb.io.ahb.out.hwdata @[quasar.scala 264:27] - io.sb_ahb.out.hwrite <= axi4_to_ahb.io.ahb.out.hwrite @[quasar.scala 264:27] - io.sb_ahb.out.htrans <= axi4_to_ahb.io.ahb.out.htrans @[quasar.scala 264:27] - io.sb_ahb.out.hsize <= axi4_to_ahb.io.ahb.out.hsize @[quasar.scala 264:27] - io.sb_ahb.out.hprot <= axi4_to_ahb.io.ahb.out.hprot @[quasar.scala 264:27] - io.sb_ahb.out.hmastlock <= axi4_to_ahb.io.ahb.out.hmastlock @[quasar.scala 264:27] - io.sb_ahb.out.hburst <= axi4_to_ahb.io.ahb.out.hburst @[quasar.scala 264:27] - io.sb_ahb.out.haddr <= axi4_to_ahb.io.ahb.out.haddr @[quasar.scala 264:27] - axi4_to_ahb.io.ahb.in.hresp <= io.sb_ahb.in.hresp @[quasar.scala 264:27] - axi4_to_ahb.io.ahb.in.hready <= io.sb_ahb.in.hready @[quasar.scala 264:27] - axi4_to_ahb.io.ahb.in.hrdata <= io.sb_ahb.in.hrdata @[quasar.scala 264:27] - ahb_to_axi4.io.scan_mode <= io.scan_mode @[quasar.scala 266:34] - ahb_to_axi4.io.bus_clk_en <= io.dma_bus_clk_en @[quasar.scala 267:35] - ahb_to_axi4.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 268:37] - ahb_to_axi4.io.axi.r.bits.last <= dma_ctrl.io.dma_axi.r.bits.last @[quasar.scala 269:28] - ahb_to_axi4.io.axi.r.bits.resp <= dma_ctrl.io.dma_axi.r.bits.resp @[quasar.scala 269:28] - ahb_to_axi4.io.axi.r.bits.data <= dma_ctrl.io.dma_axi.r.bits.data @[quasar.scala 269:28] - ahb_to_axi4.io.axi.r.bits.id <= dma_ctrl.io.dma_axi.r.bits.id @[quasar.scala 269:28] - ahb_to_axi4.io.axi.r.valid <= dma_ctrl.io.dma_axi.r.valid @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.r.ready <= ahb_to_axi4.io.axi.r.ready @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.ar.bits.qos <= ahb_to_axi4.io.axi.ar.bits.qos @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.ar.bits.prot <= ahb_to_axi4.io.axi.ar.bits.prot @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.ar.bits.cache <= ahb_to_axi4.io.axi.ar.bits.cache @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.ar.bits.lock <= ahb_to_axi4.io.axi.ar.bits.lock @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.ar.bits.burst <= ahb_to_axi4.io.axi.ar.bits.burst @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.ar.bits.size <= ahb_to_axi4.io.axi.ar.bits.size @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.ar.bits.len <= ahb_to_axi4.io.axi.ar.bits.len @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.ar.bits.region <= ahb_to_axi4.io.axi.ar.bits.region @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.ar.bits.addr <= ahb_to_axi4.io.axi.ar.bits.addr @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.ar.bits.id <= ahb_to_axi4.io.axi.ar.bits.id @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.ar.valid <= ahb_to_axi4.io.axi.ar.valid @[quasar.scala 269:28] - ahb_to_axi4.io.axi.ar.ready <= dma_ctrl.io.dma_axi.ar.ready @[quasar.scala 269:28] - ahb_to_axi4.io.axi.b.bits.id <= dma_ctrl.io.dma_axi.b.bits.id @[quasar.scala 269:28] - ahb_to_axi4.io.axi.b.bits.resp <= dma_ctrl.io.dma_axi.b.bits.resp @[quasar.scala 269:28] - ahb_to_axi4.io.axi.b.valid <= dma_ctrl.io.dma_axi.b.valid @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.b.ready <= ahb_to_axi4.io.axi.b.ready @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.w.bits.last <= ahb_to_axi4.io.axi.w.bits.last @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.w.bits.strb <= ahb_to_axi4.io.axi.w.bits.strb @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.w.bits.data <= ahb_to_axi4.io.axi.w.bits.data @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.w.valid <= ahb_to_axi4.io.axi.w.valid @[quasar.scala 269:28] - ahb_to_axi4.io.axi.w.ready <= dma_ctrl.io.dma_axi.w.ready @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.aw.bits.qos <= ahb_to_axi4.io.axi.aw.bits.qos @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.aw.bits.prot <= ahb_to_axi4.io.axi.aw.bits.prot @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.aw.bits.cache <= ahb_to_axi4.io.axi.aw.bits.cache @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.aw.bits.lock <= ahb_to_axi4.io.axi.aw.bits.lock @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.aw.bits.burst <= ahb_to_axi4.io.axi.aw.bits.burst @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.aw.bits.size <= ahb_to_axi4.io.axi.aw.bits.size @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.aw.bits.len <= ahb_to_axi4.io.axi.aw.bits.len @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.aw.bits.region <= ahb_to_axi4.io.axi.aw.bits.region @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.aw.bits.addr <= ahb_to_axi4.io.axi.aw.bits.addr @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.aw.bits.id <= ahb_to_axi4.io.axi.aw.bits.id @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.aw.valid <= ahb_to_axi4.io.axi.aw.valid @[quasar.scala 269:28] - ahb_to_axi4.io.axi.aw.ready <= dma_ctrl.io.dma_axi.aw.ready @[quasar.scala 269:28] - ahb_to_axi4.io.ahb.hreadyin <= io.dma_ahb.hreadyin @[quasar.scala 270:28] - ahb_to_axi4.io.ahb.hsel <= io.dma_ahb.hsel @[quasar.scala 270:28] - ahb_to_axi4.io.ahb.sig.out.hwdata <= io.dma_ahb.sig.out.hwdata @[quasar.scala 270:28] - ahb_to_axi4.io.ahb.sig.out.hwrite <= io.dma_ahb.sig.out.hwrite @[quasar.scala 270:28] - ahb_to_axi4.io.ahb.sig.out.htrans <= io.dma_ahb.sig.out.htrans @[quasar.scala 270:28] - ahb_to_axi4.io.ahb.sig.out.hsize <= io.dma_ahb.sig.out.hsize @[quasar.scala 270:28] - ahb_to_axi4.io.ahb.sig.out.hprot <= io.dma_ahb.sig.out.hprot @[quasar.scala 270:28] - ahb_to_axi4.io.ahb.sig.out.hmastlock <= io.dma_ahb.sig.out.hmastlock @[quasar.scala 270:28] - ahb_to_axi4.io.ahb.sig.out.hburst <= io.dma_ahb.sig.out.hburst @[quasar.scala 270:28] - ahb_to_axi4.io.ahb.sig.out.haddr <= io.dma_ahb.sig.out.haddr @[quasar.scala 270:28] - io.dma_ahb.sig.in.hresp <= ahb_to_axi4.io.ahb.sig.in.hresp @[quasar.scala 270:28] - io.dma_ahb.sig.in.hready <= ahb_to_axi4.io.ahb.sig.in.hready @[quasar.scala 270:28] - io.dma_ahb.sig.in.hrdata <= ahb_to_axi4.io.ahb.sig.in.hrdata @[quasar.scala 270:28] - wire _T_12 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar.scala 272:31] - _T_12.r.bits.last <= UInt<1>("h00") @[quasar.scala 272:31] - _T_12.r.bits.resp <= UInt<2>("h00") @[quasar.scala 272:31] - _T_12.r.bits.data <= UInt<64>("h00") @[quasar.scala 272:31] - _T_12.r.bits.id <= UInt<1>("h00") @[quasar.scala 272:31] - _T_12.r.valid <= UInt<1>("h00") @[quasar.scala 272:31] - _T_12.r.ready <= UInt<1>("h00") @[quasar.scala 272:31] - _T_12.ar.bits.qos <= UInt<4>("h00") @[quasar.scala 272:31] - _T_12.ar.bits.prot <= UInt<3>("h00") @[quasar.scala 272:31] - _T_12.ar.bits.cache <= UInt<4>("h00") @[quasar.scala 272:31] - _T_12.ar.bits.lock <= UInt<1>("h00") @[quasar.scala 272:31] - _T_12.ar.bits.burst <= UInt<2>("h00") @[quasar.scala 272:31] - _T_12.ar.bits.size <= UInt<3>("h00") @[quasar.scala 272:31] - _T_12.ar.bits.len <= UInt<8>("h00") @[quasar.scala 272:31] - _T_12.ar.bits.region <= UInt<4>("h00") @[quasar.scala 272:31] - _T_12.ar.bits.addr <= UInt<32>("h00") @[quasar.scala 272:31] - _T_12.ar.bits.id <= UInt<1>("h00") @[quasar.scala 272:31] - _T_12.ar.valid <= UInt<1>("h00") @[quasar.scala 272:31] - _T_12.ar.ready <= UInt<1>("h00") @[quasar.scala 272:31] - _T_12.b.bits.id <= UInt<1>("h00") @[quasar.scala 272:31] - _T_12.b.bits.resp <= UInt<2>("h00") @[quasar.scala 272:31] - _T_12.b.valid <= UInt<1>("h00") @[quasar.scala 272:31] - _T_12.b.ready <= UInt<1>("h00") @[quasar.scala 272:31] - _T_12.w.bits.last <= UInt<1>("h00") @[quasar.scala 272:31] - _T_12.w.bits.strb <= UInt<8>("h00") @[quasar.scala 272:31] - _T_12.w.bits.data <= UInt<64>("h00") @[quasar.scala 272:31] - _T_12.w.valid <= UInt<1>("h00") @[quasar.scala 272:31] - _T_12.w.ready <= UInt<1>("h00") @[quasar.scala 272:31] - _T_12.aw.bits.qos <= UInt<4>("h00") @[quasar.scala 272:31] - _T_12.aw.bits.prot <= UInt<3>("h00") @[quasar.scala 272:31] - _T_12.aw.bits.cache <= UInt<4>("h00") @[quasar.scala 272:31] - _T_12.aw.bits.lock <= UInt<1>("h00") @[quasar.scala 272:31] - _T_12.aw.bits.burst <= UInt<2>("h00") @[quasar.scala 272:31] - _T_12.aw.bits.size <= UInt<3>("h00") @[quasar.scala 272:31] - _T_12.aw.bits.len <= UInt<8>("h00") @[quasar.scala 272:31] - _T_12.aw.bits.region <= UInt<4>("h00") @[quasar.scala 272:31] - _T_12.aw.bits.addr <= UInt<32>("h00") @[quasar.scala 272:31] - _T_12.aw.bits.id <= UInt<1>("h00") @[quasar.scala 272:31] - _T_12.aw.valid <= UInt<1>("h00") @[quasar.scala 272:31] - _T_12.aw.ready <= UInt<1>("h00") @[quasar.scala 272:31] - io.dma_axi.r.bits.last <= _T_12.r.bits.last @[quasar.scala 272:16] - io.dma_axi.r.bits.resp <= _T_12.r.bits.resp @[quasar.scala 272:16] - io.dma_axi.r.bits.data <= _T_12.r.bits.data @[quasar.scala 272:16] - io.dma_axi.r.bits.id <= _T_12.r.bits.id @[quasar.scala 272:16] - io.dma_axi.r.valid <= _T_12.r.valid @[quasar.scala 272:16] - _T_12.r.ready <= io.dma_axi.r.ready @[quasar.scala 272:16] - _T_12.ar.bits.qos <= io.dma_axi.ar.bits.qos @[quasar.scala 272:16] - _T_12.ar.bits.prot <= io.dma_axi.ar.bits.prot @[quasar.scala 272:16] - _T_12.ar.bits.cache <= io.dma_axi.ar.bits.cache @[quasar.scala 272:16] - _T_12.ar.bits.lock <= io.dma_axi.ar.bits.lock @[quasar.scala 272:16] - _T_12.ar.bits.burst <= io.dma_axi.ar.bits.burst @[quasar.scala 272:16] - _T_12.ar.bits.size <= io.dma_axi.ar.bits.size @[quasar.scala 272:16] - _T_12.ar.bits.len <= io.dma_axi.ar.bits.len @[quasar.scala 272:16] - _T_12.ar.bits.region <= io.dma_axi.ar.bits.region @[quasar.scala 272:16] - _T_12.ar.bits.addr <= io.dma_axi.ar.bits.addr @[quasar.scala 272:16] - _T_12.ar.bits.id <= io.dma_axi.ar.bits.id @[quasar.scala 272:16] - _T_12.ar.valid <= io.dma_axi.ar.valid @[quasar.scala 272:16] - io.dma_axi.ar.ready <= _T_12.ar.ready @[quasar.scala 272:16] - io.dma_axi.b.bits.id <= _T_12.b.bits.id @[quasar.scala 272:16] - io.dma_axi.b.bits.resp <= _T_12.b.bits.resp @[quasar.scala 272:16] - io.dma_axi.b.valid <= _T_12.b.valid @[quasar.scala 272:16] - _T_12.b.ready <= io.dma_axi.b.ready @[quasar.scala 272:16] - _T_12.w.bits.last <= io.dma_axi.w.bits.last @[quasar.scala 272:16] - _T_12.w.bits.strb <= io.dma_axi.w.bits.strb @[quasar.scala 272:16] - _T_12.w.bits.data <= io.dma_axi.w.bits.data @[quasar.scala 272:16] - _T_12.w.valid <= io.dma_axi.w.valid @[quasar.scala 272:16] - io.dma_axi.w.ready <= _T_12.w.ready @[quasar.scala 272:16] - _T_12.aw.bits.qos <= io.dma_axi.aw.bits.qos @[quasar.scala 272:16] - _T_12.aw.bits.prot <= io.dma_axi.aw.bits.prot @[quasar.scala 272:16] - _T_12.aw.bits.cache <= io.dma_axi.aw.bits.cache @[quasar.scala 272:16] - _T_12.aw.bits.lock <= io.dma_axi.aw.bits.lock @[quasar.scala 272:16] - _T_12.aw.bits.burst <= io.dma_axi.aw.bits.burst @[quasar.scala 272:16] - _T_12.aw.bits.size <= io.dma_axi.aw.bits.size @[quasar.scala 272:16] - _T_12.aw.bits.len <= io.dma_axi.aw.bits.len @[quasar.scala 272:16] - _T_12.aw.bits.region <= io.dma_axi.aw.bits.region @[quasar.scala 272:16] - _T_12.aw.bits.addr <= io.dma_axi.aw.bits.addr @[quasar.scala 272:16] - _T_12.aw.bits.id <= io.dma_axi.aw.bits.id @[quasar.scala 272:16] - _T_12.aw.valid <= io.dma_axi.aw.valid @[quasar.scala 272:16] - io.dma_axi.aw.ready <= _T_12.aw.ready @[quasar.scala 272:16] - wire _T_13 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar.scala 273:36] - _T_13.r.bits.last <= UInt<1>("h00") @[quasar.scala 273:36] - _T_13.r.bits.resp <= UInt<2>("h00") @[quasar.scala 273:36] - _T_13.r.bits.data <= UInt<64>("h00") @[quasar.scala 273:36] - _T_13.r.bits.id <= UInt<1>("h00") @[quasar.scala 273:36] - _T_13.r.valid <= UInt<1>("h00") @[quasar.scala 273:36] - _T_13.r.ready <= UInt<1>("h00") @[quasar.scala 273:36] - _T_13.ar.bits.qos <= UInt<4>("h00") @[quasar.scala 273:36] - _T_13.ar.bits.prot <= UInt<3>("h00") @[quasar.scala 273:36] - _T_13.ar.bits.cache <= UInt<4>("h00") @[quasar.scala 273:36] - _T_13.ar.bits.lock <= UInt<1>("h00") @[quasar.scala 273:36] - _T_13.ar.bits.burst <= UInt<2>("h00") @[quasar.scala 273:36] - _T_13.ar.bits.size <= UInt<3>("h00") @[quasar.scala 273:36] - _T_13.ar.bits.len <= UInt<8>("h00") @[quasar.scala 273:36] - _T_13.ar.bits.region <= UInt<4>("h00") @[quasar.scala 273:36] - _T_13.ar.bits.addr <= UInt<32>("h00") @[quasar.scala 273:36] - _T_13.ar.bits.id <= UInt<1>("h00") @[quasar.scala 273:36] - _T_13.ar.valid <= UInt<1>("h00") @[quasar.scala 273:36] - _T_13.ar.ready <= UInt<1>("h00") @[quasar.scala 273:36] - _T_13.b.bits.id <= UInt<1>("h00") @[quasar.scala 273:36] - _T_13.b.bits.resp <= UInt<2>("h00") @[quasar.scala 273:36] - _T_13.b.valid <= UInt<1>("h00") @[quasar.scala 273:36] - _T_13.b.ready <= UInt<1>("h00") @[quasar.scala 273:36] - _T_13.w.bits.last <= UInt<1>("h00") @[quasar.scala 273:36] - _T_13.w.bits.strb <= UInt<8>("h00") @[quasar.scala 273:36] - _T_13.w.bits.data <= UInt<64>("h00") @[quasar.scala 273:36] - _T_13.w.valid <= UInt<1>("h00") @[quasar.scala 273:36] - _T_13.w.ready <= UInt<1>("h00") @[quasar.scala 273:36] - _T_13.aw.bits.qos <= UInt<4>("h00") @[quasar.scala 273:36] - _T_13.aw.bits.prot <= UInt<3>("h00") @[quasar.scala 273:36] - _T_13.aw.bits.cache <= UInt<4>("h00") @[quasar.scala 273:36] - _T_13.aw.bits.lock <= UInt<1>("h00") @[quasar.scala 273:36] - _T_13.aw.bits.burst <= UInt<2>("h00") @[quasar.scala 273:36] - _T_13.aw.bits.size <= UInt<3>("h00") @[quasar.scala 273:36] - _T_13.aw.bits.len <= UInt<8>("h00") @[quasar.scala 273:36] - _T_13.aw.bits.region <= UInt<4>("h00") @[quasar.scala 273:36] - _T_13.aw.bits.addr <= UInt<32>("h00") @[quasar.scala 273:36] - _T_13.aw.bits.id <= UInt<1>("h00") @[quasar.scala 273:36] - _T_13.aw.valid <= UInt<1>("h00") @[quasar.scala 273:36] - _T_13.aw.ready <= UInt<1>("h00") @[quasar.scala 273:36] - _T_13.r.bits.last <= io.sb_axi.r.bits.last @[quasar.scala 273:21] - _T_13.r.bits.resp <= io.sb_axi.r.bits.resp @[quasar.scala 273:21] - _T_13.r.bits.data <= io.sb_axi.r.bits.data @[quasar.scala 273:21] - _T_13.r.bits.id <= io.sb_axi.r.bits.id @[quasar.scala 273:21] - _T_13.r.valid <= io.sb_axi.r.valid @[quasar.scala 273:21] - io.sb_axi.r.ready <= _T_13.r.ready @[quasar.scala 273:21] - io.sb_axi.ar.bits.qos <= _T_13.ar.bits.qos @[quasar.scala 273:21] - io.sb_axi.ar.bits.prot <= _T_13.ar.bits.prot @[quasar.scala 273:21] - io.sb_axi.ar.bits.cache <= _T_13.ar.bits.cache @[quasar.scala 273:21] - io.sb_axi.ar.bits.lock <= _T_13.ar.bits.lock @[quasar.scala 273:21] - io.sb_axi.ar.bits.burst <= _T_13.ar.bits.burst @[quasar.scala 273:21] - io.sb_axi.ar.bits.size <= _T_13.ar.bits.size @[quasar.scala 273:21] - io.sb_axi.ar.bits.len <= _T_13.ar.bits.len @[quasar.scala 273:21] - io.sb_axi.ar.bits.region <= _T_13.ar.bits.region @[quasar.scala 273:21] - io.sb_axi.ar.bits.addr <= _T_13.ar.bits.addr @[quasar.scala 273:21] - io.sb_axi.ar.bits.id <= _T_13.ar.bits.id @[quasar.scala 273:21] - io.sb_axi.ar.valid <= _T_13.ar.valid @[quasar.scala 273:21] - _T_13.ar.ready <= io.sb_axi.ar.ready @[quasar.scala 273:21] - _T_13.b.bits.id <= io.sb_axi.b.bits.id @[quasar.scala 273:21] - _T_13.b.bits.resp <= io.sb_axi.b.bits.resp @[quasar.scala 273:21] - _T_13.b.valid <= io.sb_axi.b.valid @[quasar.scala 273:21] - io.sb_axi.b.ready <= _T_13.b.ready @[quasar.scala 273:21] - io.sb_axi.w.bits.last <= _T_13.w.bits.last @[quasar.scala 273:21] - io.sb_axi.w.bits.strb <= _T_13.w.bits.strb @[quasar.scala 273:21] - io.sb_axi.w.bits.data <= _T_13.w.bits.data @[quasar.scala 273:21] - io.sb_axi.w.valid <= _T_13.w.valid @[quasar.scala 273:21] - _T_13.w.ready <= io.sb_axi.w.ready @[quasar.scala 273:21] - io.sb_axi.aw.bits.qos <= _T_13.aw.bits.qos @[quasar.scala 273:21] - io.sb_axi.aw.bits.prot <= _T_13.aw.bits.prot @[quasar.scala 273:21] - io.sb_axi.aw.bits.cache <= _T_13.aw.bits.cache @[quasar.scala 273:21] - io.sb_axi.aw.bits.lock <= _T_13.aw.bits.lock @[quasar.scala 273:21] - io.sb_axi.aw.bits.burst <= _T_13.aw.bits.burst @[quasar.scala 273:21] - io.sb_axi.aw.bits.size <= _T_13.aw.bits.size @[quasar.scala 273:21] - io.sb_axi.aw.bits.len <= _T_13.aw.bits.len @[quasar.scala 273:21] - io.sb_axi.aw.bits.region <= _T_13.aw.bits.region @[quasar.scala 273:21] - io.sb_axi.aw.bits.addr <= _T_13.aw.bits.addr @[quasar.scala 273:21] - io.sb_axi.aw.bits.id <= _T_13.aw.bits.id @[quasar.scala 273:21] - io.sb_axi.aw.valid <= _T_13.aw.valid @[quasar.scala 273:21] - _T_13.aw.ready <= io.sb_axi.aw.ready @[quasar.scala 273:21] - wire _T_14 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar.scala 274:40] - _T_14.r.bits.last <= UInt<1>("h00") @[quasar.scala 274:40] - _T_14.r.bits.resp <= UInt<2>("h00") @[quasar.scala 274:40] - _T_14.r.bits.data <= UInt<64>("h00") @[quasar.scala 274:40] - _T_14.r.bits.id <= UInt<1>("h00") @[quasar.scala 274:40] - _T_14.r.valid <= UInt<1>("h00") @[quasar.scala 274:40] - _T_14.r.ready <= UInt<1>("h00") @[quasar.scala 274:40] - _T_14.ar.bits.qos <= UInt<4>("h00") @[quasar.scala 274:40] - _T_14.ar.bits.prot <= UInt<3>("h00") @[quasar.scala 274:40] - _T_14.ar.bits.cache <= UInt<4>("h00") @[quasar.scala 274:40] - _T_14.ar.bits.lock <= UInt<1>("h00") @[quasar.scala 274:40] - _T_14.ar.bits.burst <= UInt<2>("h00") @[quasar.scala 274:40] - _T_14.ar.bits.size <= UInt<3>("h00") @[quasar.scala 274:40] - _T_14.ar.bits.len <= UInt<8>("h00") @[quasar.scala 274:40] - _T_14.ar.bits.region <= UInt<4>("h00") @[quasar.scala 274:40] - _T_14.ar.bits.addr <= UInt<32>("h00") @[quasar.scala 274:40] - _T_14.ar.bits.id <= UInt<1>("h00") @[quasar.scala 274:40] - _T_14.ar.valid <= UInt<1>("h00") @[quasar.scala 274:40] - _T_14.ar.ready <= UInt<1>("h00") @[quasar.scala 274:40] - _T_14.b.bits.id <= UInt<1>("h00") @[quasar.scala 274:40] - _T_14.b.bits.resp <= UInt<2>("h00") @[quasar.scala 274:40] - _T_14.b.valid <= UInt<1>("h00") @[quasar.scala 274:40] - _T_14.b.ready <= UInt<1>("h00") @[quasar.scala 274:40] - _T_14.w.bits.last <= UInt<1>("h00") @[quasar.scala 274:40] - _T_14.w.bits.strb <= UInt<8>("h00") @[quasar.scala 274:40] - _T_14.w.bits.data <= UInt<64>("h00") @[quasar.scala 274:40] - _T_14.w.valid <= UInt<1>("h00") @[quasar.scala 274:40] - _T_14.w.ready <= UInt<1>("h00") @[quasar.scala 274:40] - _T_14.aw.bits.qos <= UInt<4>("h00") @[quasar.scala 274:40] - _T_14.aw.bits.prot <= UInt<3>("h00") @[quasar.scala 274:40] - _T_14.aw.bits.cache <= UInt<4>("h00") @[quasar.scala 274:40] - _T_14.aw.bits.lock <= UInt<1>("h00") @[quasar.scala 274:40] - _T_14.aw.bits.burst <= UInt<2>("h00") @[quasar.scala 274:40] - _T_14.aw.bits.size <= UInt<3>("h00") @[quasar.scala 274:40] - _T_14.aw.bits.len <= UInt<8>("h00") @[quasar.scala 274:40] - _T_14.aw.bits.region <= UInt<4>("h00") @[quasar.scala 274:40] - _T_14.aw.bits.addr <= UInt<32>("h00") @[quasar.scala 274:40] - _T_14.aw.bits.id <= UInt<1>("h00") @[quasar.scala 274:40] - _T_14.aw.valid <= UInt<1>("h00") @[quasar.scala 274:40] - _T_14.aw.ready <= UInt<1>("h00") @[quasar.scala 274:40] - _T_14.r.bits.last <= io.ifu_axi.r.bits.last @[quasar.scala 274:25] - _T_14.r.bits.resp <= io.ifu_axi.r.bits.resp @[quasar.scala 274:25] - _T_14.r.bits.data <= io.ifu_axi.r.bits.data @[quasar.scala 274:25] - _T_14.r.bits.id <= io.ifu_axi.r.bits.id @[quasar.scala 274:25] - _T_14.r.valid <= io.ifu_axi.r.valid @[quasar.scala 274:25] - io.ifu_axi.r.ready <= _T_14.r.ready @[quasar.scala 274:25] - io.ifu_axi.ar.bits.qos <= _T_14.ar.bits.qos @[quasar.scala 274:25] - io.ifu_axi.ar.bits.prot <= _T_14.ar.bits.prot @[quasar.scala 274:25] - io.ifu_axi.ar.bits.cache <= _T_14.ar.bits.cache @[quasar.scala 274:25] - io.ifu_axi.ar.bits.lock <= _T_14.ar.bits.lock @[quasar.scala 274:25] - io.ifu_axi.ar.bits.burst <= _T_14.ar.bits.burst @[quasar.scala 274:25] - io.ifu_axi.ar.bits.size <= _T_14.ar.bits.size @[quasar.scala 274:25] - io.ifu_axi.ar.bits.len <= _T_14.ar.bits.len @[quasar.scala 274:25] - io.ifu_axi.ar.bits.region <= _T_14.ar.bits.region @[quasar.scala 274:25] - io.ifu_axi.ar.bits.addr <= _T_14.ar.bits.addr @[quasar.scala 274:25] - io.ifu_axi.ar.bits.id <= _T_14.ar.bits.id @[quasar.scala 274:25] - io.ifu_axi.ar.valid <= _T_14.ar.valid @[quasar.scala 274:25] - _T_14.ar.ready <= io.ifu_axi.ar.ready @[quasar.scala 274:25] - _T_14.b.bits.id <= io.ifu_axi.b.bits.id @[quasar.scala 274:25] - _T_14.b.bits.resp <= io.ifu_axi.b.bits.resp @[quasar.scala 274:25] - _T_14.b.valid <= io.ifu_axi.b.valid @[quasar.scala 274:25] - io.ifu_axi.b.ready <= _T_14.b.ready @[quasar.scala 274:25] - io.ifu_axi.w.bits.last <= _T_14.w.bits.last @[quasar.scala 274:25] - io.ifu_axi.w.bits.strb <= _T_14.w.bits.strb @[quasar.scala 274:25] - io.ifu_axi.w.bits.data <= _T_14.w.bits.data @[quasar.scala 274:25] - io.ifu_axi.w.valid <= _T_14.w.valid @[quasar.scala 274:25] - _T_14.w.ready <= io.ifu_axi.w.ready @[quasar.scala 274:25] - io.ifu_axi.aw.bits.qos <= _T_14.aw.bits.qos @[quasar.scala 274:25] - io.ifu_axi.aw.bits.prot <= _T_14.aw.bits.prot @[quasar.scala 274:25] - io.ifu_axi.aw.bits.cache <= _T_14.aw.bits.cache @[quasar.scala 274:25] - io.ifu_axi.aw.bits.lock <= _T_14.aw.bits.lock @[quasar.scala 274:25] - io.ifu_axi.aw.bits.burst <= _T_14.aw.bits.burst @[quasar.scala 274:25] - io.ifu_axi.aw.bits.size <= _T_14.aw.bits.size @[quasar.scala 274:25] - io.ifu_axi.aw.bits.len <= _T_14.aw.bits.len @[quasar.scala 274:25] - io.ifu_axi.aw.bits.region <= _T_14.aw.bits.region @[quasar.scala 274:25] - io.ifu_axi.aw.bits.addr <= _T_14.aw.bits.addr @[quasar.scala 274:25] - io.ifu_axi.aw.bits.id <= _T_14.aw.bits.id @[quasar.scala 274:25] - io.ifu_axi.aw.valid <= _T_14.aw.valid @[quasar.scala 274:25] - _T_14.aw.ready <= io.ifu_axi.aw.ready @[quasar.scala 274:25] - wire _T_15 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar.scala 275:40] - _T_15.r.bits.last <= UInt<1>("h00") @[quasar.scala 275:40] - _T_15.r.bits.resp <= UInt<2>("h00") @[quasar.scala 275:40] - _T_15.r.bits.data <= UInt<64>("h00") @[quasar.scala 275:40] - _T_15.r.bits.id <= UInt<1>("h00") @[quasar.scala 275:40] - _T_15.r.valid <= UInt<1>("h00") @[quasar.scala 275:40] - _T_15.r.ready <= UInt<1>("h00") @[quasar.scala 275:40] - _T_15.ar.bits.qos <= UInt<4>("h00") @[quasar.scala 275:40] - _T_15.ar.bits.prot <= UInt<3>("h00") @[quasar.scala 275:40] - _T_15.ar.bits.cache <= UInt<4>("h00") @[quasar.scala 275:40] - _T_15.ar.bits.lock <= UInt<1>("h00") @[quasar.scala 275:40] - _T_15.ar.bits.burst <= UInt<2>("h00") @[quasar.scala 275:40] - _T_15.ar.bits.size <= UInt<3>("h00") @[quasar.scala 275:40] - _T_15.ar.bits.len <= UInt<8>("h00") @[quasar.scala 275:40] - _T_15.ar.bits.region <= UInt<4>("h00") @[quasar.scala 275:40] - _T_15.ar.bits.addr <= UInt<32>("h00") @[quasar.scala 275:40] - _T_15.ar.bits.id <= UInt<1>("h00") @[quasar.scala 275:40] - _T_15.ar.valid <= UInt<1>("h00") @[quasar.scala 275:40] - _T_15.ar.ready <= UInt<1>("h00") @[quasar.scala 275:40] - _T_15.b.bits.id <= UInt<1>("h00") @[quasar.scala 275:40] - _T_15.b.bits.resp <= UInt<2>("h00") @[quasar.scala 275:40] - _T_15.b.valid <= UInt<1>("h00") @[quasar.scala 275:40] - _T_15.b.ready <= UInt<1>("h00") @[quasar.scala 275:40] - _T_15.w.bits.last <= UInt<1>("h00") @[quasar.scala 275:40] - _T_15.w.bits.strb <= UInt<8>("h00") @[quasar.scala 275:40] - _T_15.w.bits.data <= UInt<64>("h00") @[quasar.scala 275:40] - _T_15.w.valid <= UInt<1>("h00") @[quasar.scala 275:40] - _T_15.w.ready <= UInt<1>("h00") @[quasar.scala 275:40] - _T_15.aw.bits.qos <= UInt<4>("h00") @[quasar.scala 275:40] - _T_15.aw.bits.prot <= UInt<3>("h00") @[quasar.scala 275:40] - _T_15.aw.bits.cache <= UInt<4>("h00") @[quasar.scala 275:40] - _T_15.aw.bits.lock <= UInt<1>("h00") @[quasar.scala 275:40] - _T_15.aw.bits.burst <= UInt<2>("h00") @[quasar.scala 275:40] - _T_15.aw.bits.size <= UInt<3>("h00") @[quasar.scala 275:40] - _T_15.aw.bits.len <= UInt<8>("h00") @[quasar.scala 275:40] - _T_15.aw.bits.region <= UInt<4>("h00") @[quasar.scala 275:40] - _T_15.aw.bits.addr <= UInt<32>("h00") @[quasar.scala 275:40] - _T_15.aw.bits.id <= UInt<1>("h00") @[quasar.scala 275:40] - _T_15.aw.valid <= UInt<1>("h00") @[quasar.scala 275:40] - _T_15.aw.ready <= UInt<1>("h00") @[quasar.scala 275:40] - _T_15.r.bits.last <= io.lsu_axi.r.bits.last @[quasar.scala 275:25] - _T_15.r.bits.resp <= io.lsu_axi.r.bits.resp @[quasar.scala 275:25] - _T_15.r.bits.data <= io.lsu_axi.r.bits.data @[quasar.scala 275:25] - _T_15.r.bits.id <= io.lsu_axi.r.bits.id @[quasar.scala 275:25] - _T_15.r.valid <= io.lsu_axi.r.valid @[quasar.scala 275:25] - io.lsu_axi.r.ready <= _T_15.r.ready @[quasar.scala 275:25] - io.lsu_axi.ar.bits.qos <= _T_15.ar.bits.qos @[quasar.scala 275:25] - io.lsu_axi.ar.bits.prot <= _T_15.ar.bits.prot @[quasar.scala 275:25] - io.lsu_axi.ar.bits.cache <= _T_15.ar.bits.cache @[quasar.scala 275:25] - io.lsu_axi.ar.bits.lock <= _T_15.ar.bits.lock @[quasar.scala 275:25] - io.lsu_axi.ar.bits.burst <= _T_15.ar.bits.burst @[quasar.scala 275:25] - io.lsu_axi.ar.bits.size <= _T_15.ar.bits.size @[quasar.scala 275:25] - io.lsu_axi.ar.bits.len <= _T_15.ar.bits.len @[quasar.scala 275:25] - io.lsu_axi.ar.bits.region <= _T_15.ar.bits.region @[quasar.scala 275:25] - io.lsu_axi.ar.bits.addr <= _T_15.ar.bits.addr @[quasar.scala 275:25] - io.lsu_axi.ar.bits.id <= _T_15.ar.bits.id @[quasar.scala 275:25] - io.lsu_axi.ar.valid <= _T_15.ar.valid @[quasar.scala 275:25] - _T_15.ar.ready <= io.lsu_axi.ar.ready @[quasar.scala 275:25] - _T_15.b.bits.id <= io.lsu_axi.b.bits.id @[quasar.scala 275:25] - _T_15.b.bits.resp <= io.lsu_axi.b.bits.resp @[quasar.scala 275:25] - _T_15.b.valid <= io.lsu_axi.b.valid @[quasar.scala 275:25] - io.lsu_axi.b.ready <= _T_15.b.ready @[quasar.scala 275:25] - io.lsu_axi.w.bits.last <= _T_15.w.bits.last @[quasar.scala 275:25] - io.lsu_axi.w.bits.strb <= _T_15.w.bits.strb @[quasar.scala 275:25] - io.lsu_axi.w.bits.data <= _T_15.w.bits.data @[quasar.scala 275:25] - io.lsu_axi.w.valid <= _T_15.w.valid @[quasar.scala 275:25] - _T_15.w.ready <= io.lsu_axi.w.ready @[quasar.scala 275:25] - io.lsu_axi.aw.bits.qos <= _T_15.aw.bits.qos @[quasar.scala 275:25] - io.lsu_axi.aw.bits.prot <= _T_15.aw.bits.prot @[quasar.scala 275:25] - io.lsu_axi.aw.bits.cache <= _T_15.aw.bits.cache @[quasar.scala 275:25] - io.lsu_axi.aw.bits.lock <= _T_15.aw.bits.lock @[quasar.scala 275:25] - io.lsu_axi.aw.bits.burst <= _T_15.aw.bits.burst @[quasar.scala 275:25] - io.lsu_axi.aw.bits.size <= _T_15.aw.bits.size @[quasar.scala 275:25] - io.lsu_axi.aw.bits.len <= _T_15.aw.bits.len @[quasar.scala 275:25] - io.lsu_axi.aw.bits.region <= _T_15.aw.bits.region @[quasar.scala 275:25] - io.lsu_axi.aw.bits.addr <= _T_15.aw.bits.addr @[quasar.scala 275:25] - io.lsu_axi.aw.bits.id <= _T_15.aw.bits.id @[quasar.scala 275:25] - io.lsu_axi.aw.valid <= _T_15.aw.valid @[quasar.scala 275:25] - _T_15.aw.ready <= io.lsu_axi.aw.ready @[quasar.scala 275:25] - io.dmi_reg_rdata <= UInt<1>("h00") @[quasar.scala 287:20] + axi4_to_ahb_2.io.scan_mode <= io.scan_mode @[quasar.scala 250:34] + axi4_to_ahb_2.io.bus_clk_en <= io.lsu_bus_clk_en @[quasar.scala 251:35] + axi4_to_ahb_2.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 252:37] + lsu.io.axi.r.bits.last <= axi4_to_ahb_2.io.axi.r.bits.last @[quasar.scala 253:28] + lsu.io.axi.r.bits.resp <= axi4_to_ahb_2.io.axi.r.bits.resp @[quasar.scala 253:28] + lsu.io.axi.r.bits.data <= axi4_to_ahb_2.io.axi.r.bits.data @[quasar.scala 253:28] + lsu.io.axi.r.bits.id <= axi4_to_ahb_2.io.axi.r.bits.id @[quasar.scala 253:28] + lsu.io.axi.r.valid <= axi4_to_ahb_2.io.axi.r.valid @[quasar.scala 253:28] + axi4_to_ahb_2.io.axi.r.ready <= lsu.io.axi.r.ready @[quasar.scala 253:28] + axi4_to_ahb_2.io.axi.ar.bits.qos <= lsu.io.axi.ar.bits.qos @[quasar.scala 253:28] + axi4_to_ahb_2.io.axi.ar.bits.prot <= lsu.io.axi.ar.bits.prot @[quasar.scala 253:28] + axi4_to_ahb_2.io.axi.ar.bits.cache <= lsu.io.axi.ar.bits.cache @[quasar.scala 253:28] + axi4_to_ahb_2.io.axi.ar.bits.lock <= lsu.io.axi.ar.bits.lock @[quasar.scala 253:28] + axi4_to_ahb_2.io.axi.ar.bits.burst <= lsu.io.axi.ar.bits.burst @[quasar.scala 253:28] + axi4_to_ahb_2.io.axi.ar.bits.size <= lsu.io.axi.ar.bits.size @[quasar.scala 253:28] + axi4_to_ahb_2.io.axi.ar.bits.len <= lsu.io.axi.ar.bits.len @[quasar.scala 253:28] + axi4_to_ahb_2.io.axi.ar.bits.region <= lsu.io.axi.ar.bits.region @[quasar.scala 253:28] + axi4_to_ahb_2.io.axi.ar.bits.addr <= lsu.io.axi.ar.bits.addr @[quasar.scala 253:28] + axi4_to_ahb_2.io.axi.ar.bits.id <= lsu.io.axi.ar.bits.id @[quasar.scala 253:28] + axi4_to_ahb_2.io.axi.ar.valid <= lsu.io.axi.ar.valid @[quasar.scala 253:28] + lsu.io.axi.ar.ready <= axi4_to_ahb_2.io.axi.ar.ready @[quasar.scala 253:28] + lsu.io.axi.b.bits.id <= axi4_to_ahb_2.io.axi.b.bits.id @[quasar.scala 253:28] + lsu.io.axi.b.bits.resp <= axi4_to_ahb_2.io.axi.b.bits.resp @[quasar.scala 253:28] + lsu.io.axi.b.valid <= axi4_to_ahb_2.io.axi.b.valid @[quasar.scala 253:28] + axi4_to_ahb_2.io.axi.b.ready <= lsu.io.axi.b.ready @[quasar.scala 253:28] + axi4_to_ahb_2.io.axi.w.bits.last <= lsu.io.axi.w.bits.last @[quasar.scala 253:28] + axi4_to_ahb_2.io.axi.w.bits.strb <= lsu.io.axi.w.bits.strb @[quasar.scala 253:28] + axi4_to_ahb_2.io.axi.w.bits.data <= lsu.io.axi.w.bits.data @[quasar.scala 253:28] + axi4_to_ahb_2.io.axi.w.valid <= lsu.io.axi.w.valid @[quasar.scala 253:28] + lsu.io.axi.w.ready <= axi4_to_ahb_2.io.axi.w.ready @[quasar.scala 253:28] + axi4_to_ahb_2.io.axi.aw.bits.qos <= lsu.io.axi.aw.bits.qos @[quasar.scala 253:28] + axi4_to_ahb_2.io.axi.aw.bits.prot <= lsu.io.axi.aw.bits.prot @[quasar.scala 253:28] + axi4_to_ahb_2.io.axi.aw.bits.cache <= lsu.io.axi.aw.bits.cache @[quasar.scala 253:28] + axi4_to_ahb_2.io.axi.aw.bits.lock <= lsu.io.axi.aw.bits.lock @[quasar.scala 253:28] + axi4_to_ahb_2.io.axi.aw.bits.burst <= lsu.io.axi.aw.bits.burst @[quasar.scala 253:28] + axi4_to_ahb_2.io.axi.aw.bits.size <= lsu.io.axi.aw.bits.size @[quasar.scala 253:28] + axi4_to_ahb_2.io.axi.aw.bits.len <= lsu.io.axi.aw.bits.len @[quasar.scala 253:28] + axi4_to_ahb_2.io.axi.aw.bits.region <= lsu.io.axi.aw.bits.region @[quasar.scala 253:28] + axi4_to_ahb_2.io.axi.aw.bits.addr <= lsu.io.axi.aw.bits.addr @[quasar.scala 253:28] + axi4_to_ahb_2.io.axi.aw.bits.id <= lsu.io.axi.aw.bits.id @[quasar.scala 253:28] + axi4_to_ahb_2.io.axi.aw.valid <= lsu.io.axi.aw.valid @[quasar.scala 253:28] + lsu.io.axi.aw.ready <= axi4_to_ahb_2.io.axi.aw.ready @[quasar.scala 253:28] + io.lsu_ahb.out.hwdata <= axi4_to_ahb_2.io.ahb.out.hwdata @[quasar.scala 254:28] + io.lsu_ahb.out.hwrite <= axi4_to_ahb_2.io.ahb.out.hwrite @[quasar.scala 254:28] + io.lsu_ahb.out.htrans <= axi4_to_ahb_2.io.ahb.out.htrans @[quasar.scala 254:28] + io.lsu_ahb.out.hsize <= axi4_to_ahb_2.io.ahb.out.hsize @[quasar.scala 254:28] + io.lsu_ahb.out.hprot <= axi4_to_ahb_2.io.ahb.out.hprot @[quasar.scala 254:28] + io.lsu_ahb.out.hmastlock <= axi4_to_ahb_2.io.ahb.out.hmastlock @[quasar.scala 254:28] + io.lsu_ahb.out.hburst <= axi4_to_ahb_2.io.ahb.out.hburst @[quasar.scala 254:28] + io.lsu_ahb.out.haddr <= axi4_to_ahb_2.io.ahb.out.haddr @[quasar.scala 254:28] + axi4_to_ahb_2.io.ahb.in.hresp <= io.lsu_ahb.in.hresp @[quasar.scala 254:28] + axi4_to_ahb_2.io.ahb.in.hready <= io.lsu_ahb.in.hready @[quasar.scala 254:28] + axi4_to_ahb_2.io.ahb.in.hrdata <= io.lsu_ahb.in.hrdata @[quasar.scala 254:28] + axi4_to_ahb_1.io.scan_mode <= io.scan_mode @[quasar.scala 256:34] + axi4_to_ahb_1.io.bus_clk_en <= io.ifu_bus_clk_en @[quasar.scala 257:35] + axi4_to_ahb_1.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 258:37] + ifu.io.ifu.r.bits.last <= axi4_to_ahb_1.io.axi.r.bits.last @[quasar.scala 259:28] + ifu.io.ifu.r.bits.resp <= axi4_to_ahb_1.io.axi.r.bits.resp @[quasar.scala 259:28] + ifu.io.ifu.r.bits.data <= axi4_to_ahb_1.io.axi.r.bits.data @[quasar.scala 259:28] + ifu.io.ifu.r.bits.id <= axi4_to_ahb_1.io.axi.r.bits.id @[quasar.scala 259:28] + ifu.io.ifu.r.valid <= axi4_to_ahb_1.io.axi.r.valid @[quasar.scala 259:28] + axi4_to_ahb_1.io.axi.r.ready <= ifu.io.ifu.r.ready @[quasar.scala 259:28] + axi4_to_ahb_1.io.axi.ar.bits.qos <= ifu.io.ifu.ar.bits.qos @[quasar.scala 259:28] + axi4_to_ahb_1.io.axi.ar.bits.prot <= ifu.io.ifu.ar.bits.prot @[quasar.scala 259:28] + axi4_to_ahb_1.io.axi.ar.bits.cache <= ifu.io.ifu.ar.bits.cache @[quasar.scala 259:28] + axi4_to_ahb_1.io.axi.ar.bits.lock <= ifu.io.ifu.ar.bits.lock @[quasar.scala 259:28] + axi4_to_ahb_1.io.axi.ar.bits.burst <= ifu.io.ifu.ar.bits.burst @[quasar.scala 259:28] + axi4_to_ahb_1.io.axi.ar.bits.size <= ifu.io.ifu.ar.bits.size @[quasar.scala 259:28] + axi4_to_ahb_1.io.axi.ar.bits.len <= ifu.io.ifu.ar.bits.len @[quasar.scala 259:28] + axi4_to_ahb_1.io.axi.ar.bits.region <= ifu.io.ifu.ar.bits.region @[quasar.scala 259:28] + axi4_to_ahb_1.io.axi.ar.bits.addr <= ifu.io.ifu.ar.bits.addr @[quasar.scala 259:28] + axi4_to_ahb_1.io.axi.ar.bits.id <= ifu.io.ifu.ar.bits.id @[quasar.scala 259:28] + axi4_to_ahb_1.io.axi.ar.valid <= ifu.io.ifu.ar.valid @[quasar.scala 259:28] + ifu.io.ifu.ar.ready <= axi4_to_ahb_1.io.axi.ar.ready @[quasar.scala 259:28] + ifu.io.ifu.b.bits.id <= axi4_to_ahb_1.io.axi.b.bits.id @[quasar.scala 259:28] + ifu.io.ifu.b.bits.resp <= axi4_to_ahb_1.io.axi.b.bits.resp @[quasar.scala 259:28] + ifu.io.ifu.b.valid <= axi4_to_ahb_1.io.axi.b.valid @[quasar.scala 259:28] + axi4_to_ahb_1.io.axi.b.ready <= ifu.io.ifu.b.ready @[quasar.scala 259:28] + axi4_to_ahb_1.io.axi.w.bits.last <= ifu.io.ifu.w.bits.last @[quasar.scala 259:28] + axi4_to_ahb_1.io.axi.w.bits.strb <= ifu.io.ifu.w.bits.strb @[quasar.scala 259:28] + axi4_to_ahb_1.io.axi.w.bits.data <= ifu.io.ifu.w.bits.data @[quasar.scala 259:28] + axi4_to_ahb_1.io.axi.w.valid <= ifu.io.ifu.w.valid @[quasar.scala 259:28] + ifu.io.ifu.w.ready <= axi4_to_ahb_1.io.axi.w.ready @[quasar.scala 259:28] + axi4_to_ahb_1.io.axi.aw.bits.qos <= ifu.io.ifu.aw.bits.qos @[quasar.scala 259:28] + axi4_to_ahb_1.io.axi.aw.bits.prot <= ifu.io.ifu.aw.bits.prot @[quasar.scala 259:28] + axi4_to_ahb_1.io.axi.aw.bits.cache <= ifu.io.ifu.aw.bits.cache @[quasar.scala 259:28] + axi4_to_ahb_1.io.axi.aw.bits.lock <= ifu.io.ifu.aw.bits.lock @[quasar.scala 259:28] + axi4_to_ahb_1.io.axi.aw.bits.burst <= ifu.io.ifu.aw.bits.burst @[quasar.scala 259:28] + axi4_to_ahb_1.io.axi.aw.bits.size <= ifu.io.ifu.aw.bits.size @[quasar.scala 259:28] + axi4_to_ahb_1.io.axi.aw.bits.len <= ifu.io.ifu.aw.bits.len @[quasar.scala 259:28] + axi4_to_ahb_1.io.axi.aw.bits.region <= ifu.io.ifu.aw.bits.region @[quasar.scala 259:28] + axi4_to_ahb_1.io.axi.aw.bits.addr <= ifu.io.ifu.aw.bits.addr @[quasar.scala 259:28] + axi4_to_ahb_1.io.axi.aw.bits.id <= ifu.io.ifu.aw.bits.id @[quasar.scala 259:28] + axi4_to_ahb_1.io.axi.aw.valid <= ifu.io.ifu.aw.valid @[quasar.scala 259:28] + ifu.io.ifu.aw.ready <= axi4_to_ahb_1.io.axi.aw.ready @[quasar.scala 259:28] + io.ifu_ahb.out.hwdata <= axi4_to_ahb_1.io.ahb.out.hwdata @[quasar.scala 260:28] + io.ifu_ahb.out.hwrite <= axi4_to_ahb_1.io.ahb.out.hwrite @[quasar.scala 260:28] + io.ifu_ahb.out.htrans <= axi4_to_ahb_1.io.ahb.out.htrans @[quasar.scala 260:28] + io.ifu_ahb.out.hsize <= axi4_to_ahb_1.io.ahb.out.hsize @[quasar.scala 260:28] + io.ifu_ahb.out.hprot <= axi4_to_ahb_1.io.ahb.out.hprot @[quasar.scala 260:28] + io.ifu_ahb.out.hmastlock <= axi4_to_ahb_1.io.ahb.out.hmastlock @[quasar.scala 260:28] + io.ifu_ahb.out.hburst <= axi4_to_ahb_1.io.ahb.out.hburst @[quasar.scala 260:28] + io.ifu_ahb.out.haddr <= axi4_to_ahb_1.io.ahb.out.haddr @[quasar.scala 260:28] + axi4_to_ahb_1.io.ahb.in.hresp <= io.ifu_ahb.in.hresp @[quasar.scala 260:28] + axi4_to_ahb_1.io.ahb.in.hready <= io.ifu_ahb.in.hready @[quasar.scala 260:28] + axi4_to_ahb_1.io.ahb.in.hrdata <= io.ifu_ahb.in.hrdata @[quasar.scala 260:28] + axi4_to_ahb_1.io.axi.b.ready <= UInt<1>("h01") @[quasar.scala 261:36] + axi4_to_ahb.io.scan_mode <= io.scan_mode @[quasar.scala 263:33] + axi4_to_ahb.io.bus_clk_en <= io.dbg_bus_clk_en @[quasar.scala 264:34] + axi4_to_ahb.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 265:36] + dbg.io.sb_axi.r.bits.last <= axi4_to_ahb.io.axi.r.bits.last @[quasar.scala 266:27] + dbg.io.sb_axi.r.bits.resp <= axi4_to_ahb.io.axi.r.bits.resp @[quasar.scala 266:27] + dbg.io.sb_axi.r.bits.data <= axi4_to_ahb.io.axi.r.bits.data @[quasar.scala 266:27] + dbg.io.sb_axi.r.bits.id <= axi4_to_ahb.io.axi.r.bits.id @[quasar.scala 266:27] + dbg.io.sb_axi.r.valid <= axi4_to_ahb.io.axi.r.valid @[quasar.scala 266:27] + axi4_to_ahb.io.axi.r.ready <= dbg.io.sb_axi.r.ready @[quasar.scala 266:27] + axi4_to_ahb.io.axi.ar.bits.qos <= dbg.io.sb_axi.ar.bits.qos @[quasar.scala 266:27] + axi4_to_ahb.io.axi.ar.bits.prot <= dbg.io.sb_axi.ar.bits.prot @[quasar.scala 266:27] + axi4_to_ahb.io.axi.ar.bits.cache <= dbg.io.sb_axi.ar.bits.cache @[quasar.scala 266:27] + axi4_to_ahb.io.axi.ar.bits.lock <= dbg.io.sb_axi.ar.bits.lock @[quasar.scala 266:27] + axi4_to_ahb.io.axi.ar.bits.burst <= dbg.io.sb_axi.ar.bits.burst @[quasar.scala 266:27] + axi4_to_ahb.io.axi.ar.bits.size <= dbg.io.sb_axi.ar.bits.size @[quasar.scala 266:27] + axi4_to_ahb.io.axi.ar.bits.len <= dbg.io.sb_axi.ar.bits.len @[quasar.scala 266:27] + axi4_to_ahb.io.axi.ar.bits.region <= dbg.io.sb_axi.ar.bits.region @[quasar.scala 266:27] + axi4_to_ahb.io.axi.ar.bits.addr <= dbg.io.sb_axi.ar.bits.addr @[quasar.scala 266:27] + axi4_to_ahb.io.axi.ar.bits.id <= dbg.io.sb_axi.ar.bits.id @[quasar.scala 266:27] + axi4_to_ahb.io.axi.ar.valid <= dbg.io.sb_axi.ar.valid @[quasar.scala 266:27] + dbg.io.sb_axi.ar.ready <= axi4_to_ahb.io.axi.ar.ready @[quasar.scala 266:27] + dbg.io.sb_axi.b.bits.id <= axi4_to_ahb.io.axi.b.bits.id @[quasar.scala 266:27] + dbg.io.sb_axi.b.bits.resp <= axi4_to_ahb.io.axi.b.bits.resp @[quasar.scala 266:27] + dbg.io.sb_axi.b.valid <= axi4_to_ahb.io.axi.b.valid @[quasar.scala 266:27] + axi4_to_ahb.io.axi.b.ready <= dbg.io.sb_axi.b.ready @[quasar.scala 266:27] + axi4_to_ahb.io.axi.w.bits.last <= dbg.io.sb_axi.w.bits.last @[quasar.scala 266:27] + axi4_to_ahb.io.axi.w.bits.strb <= dbg.io.sb_axi.w.bits.strb @[quasar.scala 266:27] + axi4_to_ahb.io.axi.w.bits.data <= dbg.io.sb_axi.w.bits.data @[quasar.scala 266:27] + axi4_to_ahb.io.axi.w.valid <= dbg.io.sb_axi.w.valid @[quasar.scala 266:27] + dbg.io.sb_axi.w.ready <= axi4_to_ahb.io.axi.w.ready @[quasar.scala 266:27] + axi4_to_ahb.io.axi.aw.bits.qos <= dbg.io.sb_axi.aw.bits.qos @[quasar.scala 266:27] + axi4_to_ahb.io.axi.aw.bits.prot <= dbg.io.sb_axi.aw.bits.prot @[quasar.scala 266:27] + axi4_to_ahb.io.axi.aw.bits.cache <= dbg.io.sb_axi.aw.bits.cache @[quasar.scala 266:27] + axi4_to_ahb.io.axi.aw.bits.lock <= dbg.io.sb_axi.aw.bits.lock @[quasar.scala 266:27] + axi4_to_ahb.io.axi.aw.bits.burst <= dbg.io.sb_axi.aw.bits.burst @[quasar.scala 266:27] + axi4_to_ahb.io.axi.aw.bits.size <= dbg.io.sb_axi.aw.bits.size @[quasar.scala 266:27] + axi4_to_ahb.io.axi.aw.bits.len <= dbg.io.sb_axi.aw.bits.len @[quasar.scala 266:27] + axi4_to_ahb.io.axi.aw.bits.region <= dbg.io.sb_axi.aw.bits.region @[quasar.scala 266:27] + axi4_to_ahb.io.axi.aw.bits.addr <= dbg.io.sb_axi.aw.bits.addr @[quasar.scala 266:27] + axi4_to_ahb.io.axi.aw.bits.id <= dbg.io.sb_axi.aw.bits.id @[quasar.scala 266:27] + axi4_to_ahb.io.axi.aw.valid <= dbg.io.sb_axi.aw.valid @[quasar.scala 266:27] + dbg.io.sb_axi.aw.ready <= axi4_to_ahb.io.axi.aw.ready @[quasar.scala 266:27] + io.sb_ahb.out.hwdata <= axi4_to_ahb.io.ahb.out.hwdata @[quasar.scala 267:27] + io.sb_ahb.out.hwrite <= axi4_to_ahb.io.ahb.out.hwrite @[quasar.scala 267:27] + io.sb_ahb.out.htrans <= axi4_to_ahb.io.ahb.out.htrans @[quasar.scala 267:27] + io.sb_ahb.out.hsize <= axi4_to_ahb.io.ahb.out.hsize @[quasar.scala 267:27] + io.sb_ahb.out.hprot <= axi4_to_ahb.io.ahb.out.hprot @[quasar.scala 267:27] + io.sb_ahb.out.hmastlock <= axi4_to_ahb.io.ahb.out.hmastlock @[quasar.scala 267:27] + io.sb_ahb.out.hburst <= axi4_to_ahb.io.ahb.out.hburst @[quasar.scala 267:27] + io.sb_ahb.out.haddr <= axi4_to_ahb.io.ahb.out.haddr @[quasar.scala 267:27] + axi4_to_ahb.io.ahb.in.hresp <= io.sb_ahb.in.hresp @[quasar.scala 267:27] + axi4_to_ahb.io.ahb.in.hready <= io.sb_ahb.in.hready @[quasar.scala 267:27] + axi4_to_ahb.io.ahb.in.hrdata <= io.sb_ahb.in.hrdata @[quasar.scala 267:27] + ahb_to_axi4.io.scan_mode <= io.scan_mode @[quasar.scala 269:34] + ahb_to_axi4.io.bus_clk_en <= io.dma_bus_clk_en @[quasar.scala 270:35] + ahb_to_axi4.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 271:37] + ahb_to_axi4.io.axi.r.bits.last <= dma_ctrl.io.dma_axi.r.bits.last @[quasar.scala 272:28] + ahb_to_axi4.io.axi.r.bits.resp <= dma_ctrl.io.dma_axi.r.bits.resp @[quasar.scala 272:28] + ahb_to_axi4.io.axi.r.bits.data <= dma_ctrl.io.dma_axi.r.bits.data @[quasar.scala 272:28] + ahb_to_axi4.io.axi.r.bits.id <= dma_ctrl.io.dma_axi.r.bits.id @[quasar.scala 272:28] + ahb_to_axi4.io.axi.r.valid <= dma_ctrl.io.dma_axi.r.valid @[quasar.scala 272:28] + dma_ctrl.io.dma_axi.r.ready <= ahb_to_axi4.io.axi.r.ready @[quasar.scala 272:28] + dma_ctrl.io.dma_axi.ar.bits.qos <= ahb_to_axi4.io.axi.ar.bits.qos @[quasar.scala 272:28] + dma_ctrl.io.dma_axi.ar.bits.prot <= ahb_to_axi4.io.axi.ar.bits.prot @[quasar.scala 272:28] + dma_ctrl.io.dma_axi.ar.bits.cache <= ahb_to_axi4.io.axi.ar.bits.cache @[quasar.scala 272:28] + dma_ctrl.io.dma_axi.ar.bits.lock <= ahb_to_axi4.io.axi.ar.bits.lock @[quasar.scala 272:28] + dma_ctrl.io.dma_axi.ar.bits.burst <= ahb_to_axi4.io.axi.ar.bits.burst @[quasar.scala 272:28] + dma_ctrl.io.dma_axi.ar.bits.size <= ahb_to_axi4.io.axi.ar.bits.size @[quasar.scala 272:28] + dma_ctrl.io.dma_axi.ar.bits.len <= ahb_to_axi4.io.axi.ar.bits.len @[quasar.scala 272:28] + dma_ctrl.io.dma_axi.ar.bits.region <= ahb_to_axi4.io.axi.ar.bits.region @[quasar.scala 272:28] + dma_ctrl.io.dma_axi.ar.bits.addr <= ahb_to_axi4.io.axi.ar.bits.addr @[quasar.scala 272:28] + dma_ctrl.io.dma_axi.ar.bits.id <= ahb_to_axi4.io.axi.ar.bits.id @[quasar.scala 272:28] + dma_ctrl.io.dma_axi.ar.valid <= ahb_to_axi4.io.axi.ar.valid @[quasar.scala 272:28] + ahb_to_axi4.io.axi.ar.ready <= dma_ctrl.io.dma_axi.ar.ready @[quasar.scala 272:28] + ahb_to_axi4.io.axi.b.bits.id <= dma_ctrl.io.dma_axi.b.bits.id @[quasar.scala 272:28] + ahb_to_axi4.io.axi.b.bits.resp <= dma_ctrl.io.dma_axi.b.bits.resp @[quasar.scala 272:28] + ahb_to_axi4.io.axi.b.valid <= dma_ctrl.io.dma_axi.b.valid @[quasar.scala 272:28] + dma_ctrl.io.dma_axi.b.ready <= ahb_to_axi4.io.axi.b.ready @[quasar.scala 272:28] + dma_ctrl.io.dma_axi.w.bits.last <= ahb_to_axi4.io.axi.w.bits.last @[quasar.scala 272:28] + dma_ctrl.io.dma_axi.w.bits.strb <= ahb_to_axi4.io.axi.w.bits.strb @[quasar.scala 272:28] + dma_ctrl.io.dma_axi.w.bits.data <= ahb_to_axi4.io.axi.w.bits.data @[quasar.scala 272:28] + dma_ctrl.io.dma_axi.w.valid <= ahb_to_axi4.io.axi.w.valid @[quasar.scala 272:28] + ahb_to_axi4.io.axi.w.ready <= dma_ctrl.io.dma_axi.w.ready @[quasar.scala 272:28] + dma_ctrl.io.dma_axi.aw.bits.qos <= ahb_to_axi4.io.axi.aw.bits.qos @[quasar.scala 272:28] + dma_ctrl.io.dma_axi.aw.bits.prot <= ahb_to_axi4.io.axi.aw.bits.prot @[quasar.scala 272:28] + dma_ctrl.io.dma_axi.aw.bits.cache <= ahb_to_axi4.io.axi.aw.bits.cache @[quasar.scala 272:28] + dma_ctrl.io.dma_axi.aw.bits.lock <= ahb_to_axi4.io.axi.aw.bits.lock @[quasar.scala 272:28] + dma_ctrl.io.dma_axi.aw.bits.burst <= ahb_to_axi4.io.axi.aw.bits.burst @[quasar.scala 272:28] + dma_ctrl.io.dma_axi.aw.bits.size <= ahb_to_axi4.io.axi.aw.bits.size @[quasar.scala 272:28] + dma_ctrl.io.dma_axi.aw.bits.len <= ahb_to_axi4.io.axi.aw.bits.len @[quasar.scala 272:28] + dma_ctrl.io.dma_axi.aw.bits.region <= ahb_to_axi4.io.axi.aw.bits.region @[quasar.scala 272:28] + dma_ctrl.io.dma_axi.aw.bits.addr <= ahb_to_axi4.io.axi.aw.bits.addr @[quasar.scala 272:28] + dma_ctrl.io.dma_axi.aw.bits.id <= ahb_to_axi4.io.axi.aw.bits.id @[quasar.scala 272:28] + dma_ctrl.io.dma_axi.aw.valid <= ahb_to_axi4.io.axi.aw.valid @[quasar.scala 272:28] + ahb_to_axi4.io.axi.aw.ready <= dma_ctrl.io.dma_axi.aw.ready @[quasar.scala 272:28] + ahb_to_axi4.io.ahb.hreadyin <= io.dma_ahb.hreadyin @[quasar.scala 273:28] + ahb_to_axi4.io.ahb.hsel <= io.dma_ahb.hsel @[quasar.scala 273:28] + ahb_to_axi4.io.ahb.sig.out.hwdata <= io.dma_ahb.sig.out.hwdata @[quasar.scala 273:28] + ahb_to_axi4.io.ahb.sig.out.hwrite <= io.dma_ahb.sig.out.hwrite @[quasar.scala 273:28] + ahb_to_axi4.io.ahb.sig.out.htrans <= io.dma_ahb.sig.out.htrans @[quasar.scala 273:28] + ahb_to_axi4.io.ahb.sig.out.hsize <= io.dma_ahb.sig.out.hsize @[quasar.scala 273:28] + ahb_to_axi4.io.ahb.sig.out.hprot <= io.dma_ahb.sig.out.hprot @[quasar.scala 273:28] + ahb_to_axi4.io.ahb.sig.out.hmastlock <= io.dma_ahb.sig.out.hmastlock @[quasar.scala 273:28] + ahb_to_axi4.io.ahb.sig.out.hburst <= io.dma_ahb.sig.out.hburst @[quasar.scala 273:28] + ahb_to_axi4.io.ahb.sig.out.haddr <= io.dma_ahb.sig.out.haddr @[quasar.scala 273:28] + io.dma_ahb.sig.in.hresp <= ahb_to_axi4.io.ahb.sig.in.hresp @[quasar.scala 273:28] + io.dma_ahb.sig.in.hready <= ahb_to_axi4.io.ahb.sig.in.hready @[quasar.scala 273:28] + io.dma_ahb.sig.in.hrdata <= ahb_to_axi4.io.ahb.sig.in.hrdata @[quasar.scala 273:28] + wire _T_12 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar.scala 275:36] + _T_12.r.bits.last <= UInt<1>("h00") @[quasar.scala 275:36] + _T_12.r.bits.resp <= UInt<2>("h00") @[quasar.scala 275:36] + _T_12.r.bits.data <= UInt<64>("h00") @[quasar.scala 275:36] + _T_12.r.bits.id <= UInt<1>("h00") @[quasar.scala 275:36] + _T_12.r.valid <= UInt<1>("h00") @[quasar.scala 275:36] + _T_12.r.ready <= UInt<1>("h00") @[quasar.scala 275:36] + _T_12.ar.bits.qos <= UInt<4>("h00") @[quasar.scala 275:36] + _T_12.ar.bits.prot <= UInt<3>("h00") @[quasar.scala 275:36] + _T_12.ar.bits.cache <= UInt<4>("h00") @[quasar.scala 275:36] + _T_12.ar.bits.lock <= UInt<1>("h00") @[quasar.scala 275:36] + _T_12.ar.bits.burst <= UInt<2>("h00") @[quasar.scala 275:36] + _T_12.ar.bits.size <= UInt<3>("h00") @[quasar.scala 275:36] + _T_12.ar.bits.len <= UInt<8>("h00") @[quasar.scala 275:36] + _T_12.ar.bits.region <= UInt<4>("h00") @[quasar.scala 275:36] + _T_12.ar.bits.addr <= UInt<32>("h00") @[quasar.scala 275:36] + _T_12.ar.bits.id <= UInt<1>("h00") @[quasar.scala 275:36] + _T_12.ar.valid <= UInt<1>("h00") @[quasar.scala 275:36] + _T_12.ar.ready <= UInt<1>("h00") @[quasar.scala 275:36] + _T_12.b.bits.id <= UInt<1>("h00") @[quasar.scala 275:36] + _T_12.b.bits.resp <= UInt<2>("h00") @[quasar.scala 275:36] + _T_12.b.valid <= UInt<1>("h00") @[quasar.scala 275:36] + _T_12.b.ready <= UInt<1>("h00") @[quasar.scala 275:36] + _T_12.w.bits.last <= UInt<1>("h00") @[quasar.scala 275:36] + _T_12.w.bits.strb <= UInt<8>("h00") @[quasar.scala 275:36] + _T_12.w.bits.data <= UInt<64>("h00") @[quasar.scala 275:36] + _T_12.w.valid <= UInt<1>("h00") @[quasar.scala 275:36] + _T_12.w.ready <= UInt<1>("h00") @[quasar.scala 275:36] + _T_12.aw.bits.qos <= UInt<4>("h00") @[quasar.scala 275:36] + _T_12.aw.bits.prot <= UInt<3>("h00") @[quasar.scala 275:36] + _T_12.aw.bits.cache <= UInt<4>("h00") @[quasar.scala 275:36] + _T_12.aw.bits.lock <= UInt<1>("h00") @[quasar.scala 275:36] + _T_12.aw.bits.burst <= UInt<2>("h00") @[quasar.scala 275:36] + _T_12.aw.bits.size <= UInt<3>("h00") @[quasar.scala 275:36] + _T_12.aw.bits.len <= UInt<8>("h00") @[quasar.scala 275:36] + _T_12.aw.bits.region <= UInt<4>("h00") @[quasar.scala 275:36] + _T_12.aw.bits.addr <= UInt<32>("h00") @[quasar.scala 275:36] + _T_12.aw.bits.id <= UInt<1>("h00") @[quasar.scala 275:36] + _T_12.aw.valid <= UInt<1>("h00") @[quasar.scala 275:36] + _T_12.aw.ready <= UInt<1>("h00") @[quasar.scala 275:36] + io.dma_axi.r.bits.last <= _T_12.r.bits.last @[quasar.scala 275:21] + io.dma_axi.r.bits.resp <= _T_12.r.bits.resp @[quasar.scala 275:21] + io.dma_axi.r.bits.data <= _T_12.r.bits.data @[quasar.scala 275:21] + io.dma_axi.r.bits.id <= _T_12.r.bits.id @[quasar.scala 275:21] + io.dma_axi.r.valid <= _T_12.r.valid @[quasar.scala 275:21] + _T_12.r.ready <= io.dma_axi.r.ready @[quasar.scala 275:21] + _T_12.ar.bits.qos <= io.dma_axi.ar.bits.qos @[quasar.scala 275:21] + _T_12.ar.bits.prot <= io.dma_axi.ar.bits.prot @[quasar.scala 275:21] + _T_12.ar.bits.cache <= io.dma_axi.ar.bits.cache @[quasar.scala 275:21] + _T_12.ar.bits.lock <= io.dma_axi.ar.bits.lock @[quasar.scala 275:21] + _T_12.ar.bits.burst <= io.dma_axi.ar.bits.burst @[quasar.scala 275:21] + _T_12.ar.bits.size <= io.dma_axi.ar.bits.size @[quasar.scala 275:21] + _T_12.ar.bits.len <= io.dma_axi.ar.bits.len @[quasar.scala 275:21] + _T_12.ar.bits.region <= io.dma_axi.ar.bits.region @[quasar.scala 275:21] + _T_12.ar.bits.addr <= io.dma_axi.ar.bits.addr @[quasar.scala 275:21] + _T_12.ar.bits.id <= io.dma_axi.ar.bits.id @[quasar.scala 275:21] + _T_12.ar.valid <= io.dma_axi.ar.valid @[quasar.scala 275:21] + io.dma_axi.ar.ready <= _T_12.ar.ready @[quasar.scala 275:21] + io.dma_axi.b.bits.id <= _T_12.b.bits.id @[quasar.scala 275:21] + io.dma_axi.b.bits.resp <= _T_12.b.bits.resp @[quasar.scala 275:21] + io.dma_axi.b.valid <= _T_12.b.valid @[quasar.scala 275:21] + _T_12.b.ready <= io.dma_axi.b.ready @[quasar.scala 275:21] + _T_12.w.bits.last <= io.dma_axi.w.bits.last @[quasar.scala 275:21] + _T_12.w.bits.strb <= io.dma_axi.w.bits.strb @[quasar.scala 275:21] + _T_12.w.bits.data <= io.dma_axi.w.bits.data @[quasar.scala 275:21] + _T_12.w.valid <= io.dma_axi.w.valid @[quasar.scala 275:21] + io.dma_axi.w.ready <= _T_12.w.ready @[quasar.scala 275:21] + _T_12.aw.bits.qos <= io.dma_axi.aw.bits.qos @[quasar.scala 275:21] + _T_12.aw.bits.prot <= io.dma_axi.aw.bits.prot @[quasar.scala 275:21] + _T_12.aw.bits.cache <= io.dma_axi.aw.bits.cache @[quasar.scala 275:21] + _T_12.aw.bits.lock <= io.dma_axi.aw.bits.lock @[quasar.scala 275:21] + _T_12.aw.bits.burst <= io.dma_axi.aw.bits.burst @[quasar.scala 275:21] + _T_12.aw.bits.size <= io.dma_axi.aw.bits.size @[quasar.scala 275:21] + _T_12.aw.bits.len <= io.dma_axi.aw.bits.len @[quasar.scala 275:21] + _T_12.aw.bits.region <= io.dma_axi.aw.bits.region @[quasar.scala 275:21] + _T_12.aw.bits.addr <= io.dma_axi.aw.bits.addr @[quasar.scala 275:21] + _T_12.aw.bits.id <= io.dma_axi.aw.bits.id @[quasar.scala 275:21] + _T_12.aw.valid <= io.dma_axi.aw.valid @[quasar.scala 275:21] + io.dma_axi.aw.ready <= _T_12.aw.ready @[quasar.scala 275:21] + wire _T_13 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar.scala 276:36] + _T_13.r.bits.last <= UInt<1>("h00") @[quasar.scala 276:36] + _T_13.r.bits.resp <= UInt<2>("h00") @[quasar.scala 276:36] + _T_13.r.bits.data <= UInt<64>("h00") @[quasar.scala 276:36] + _T_13.r.bits.id <= UInt<1>("h00") @[quasar.scala 276:36] + _T_13.r.valid <= UInt<1>("h00") @[quasar.scala 276:36] + _T_13.r.ready <= UInt<1>("h00") @[quasar.scala 276:36] + _T_13.ar.bits.qos <= UInt<4>("h00") @[quasar.scala 276:36] + _T_13.ar.bits.prot <= UInt<3>("h00") @[quasar.scala 276:36] + _T_13.ar.bits.cache <= UInt<4>("h00") @[quasar.scala 276:36] + _T_13.ar.bits.lock <= UInt<1>("h00") @[quasar.scala 276:36] + _T_13.ar.bits.burst <= UInt<2>("h00") @[quasar.scala 276:36] + _T_13.ar.bits.size <= UInt<3>("h00") @[quasar.scala 276:36] + _T_13.ar.bits.len <= UInt<8>("h00") @[quasar.scala 276:36] + _T_13.ar.bits.region <= UInt<4>("h00") @[quasar.scala 276:36] + _T_13.ar.bits.addr <= UInt<32>("h00") @[quasar.scala 276:36] + _T_13.ar.bits.id <= UInt<1>("h00") @[quasar.scala 276:36] + _T_13.ar.valid <= UInt<1>("h00") @[quasar.scala 276:36] + _T_13.ar.ready <= UInt<1>("h00") @[quasar.scala 276:36] + _T_13.b.bits.id <= UInt<1>("h00") @[quasar.scala 276:36] + _T_13.b.bits.resp <= UInt<2>("h00") @[quasar.scala 276:36] + _T_13.b.valid <= UInt<1>("h00") @[quasar.scala 276:36] + _T_13.b.ready <= UInt<1>("h00") @[quasar.scala 276:36] + _T_13.w.bits.last <= UInt<1>("h00") @[quasar.scala 276:36] + _T_13.w.bits.strb <= UInt<8>("h00") @[quasar.scala 276:36] + _T_13.w.bits.data <= UInt<64>("h00") @[quasar.scala 276:36] + _T_13.w.valid <= UInt<1>("h00") @[quasar.scala 276:36] + _T_13.w.ready <= UInt<1>("h00") @[quasar.scala 276:36] + _T_13.aw.bits.qos <= UInt<4>("h00") @[quasar.scala 276:36] + _T_13.aw.bits.prot <= UInt<3>("h00") @[quasar.scala 276:36] + _T_13.aw.bits.cache <= UInt<4>("h00") @[quasar.scala 276:36] + _T_13.aw.bits.lock <= UInt<1>("h00") @[quasar.scala 276:36] + _T_13.aw.bits.burst <= UInt<2>("h00") @[quasar.scala 276:36] + _T_13.aw.bits.size <= UInt<3>("h00") @[quasar.scala 276:36] + _T_13.aw.bits.len <= UInt<8>("h00") @[quasar.scala 276:36] + _T_13.aw.bits.region <= UInt<4>("h00") @[quasar.scala 276:36] + _T_13.aw.bits.addr <= UInt<32>("h00") @[quasar.scala 276:36] + _T_13.aw.bits.id <= UInt<1>("h00") @[quasar.scala 276:36] + _T_13.aw.valid <= UInt<1>("h00") @[quasar.scala 276:36] + _T_13.aw.ready <= UInt<1>("h00") @[quasar.scala 276:36] + _T_13.r.bits.last <= io.sb_axi.r.bits.last @[quasar.scala 276:21] + _T_13.r.bits.resp <= io.sb_axi.r.bits.resp @[quasar.scala 276:21] + _T_13.r.bits.data <= io.sb_axi.r.bits.data @[quasar.scala 276:21] + _T_13.r.bits.id <= io.sb_axi.r.bits.id @[quasar.scala 276:21] + _T_13.r.valid <= io.sb_axi.r.valid @[quasar.scala 276:21] + io.sb_axi.r.ready <= _T_13.r.ready @[quasar.scala 276:21] + io.sb_axi.ar.bits.qos <= _T_13.ar.bits.qos @[quasar.scala 276:21] + io.sb_axi.ar.bits.prot <= _T_13.ar.bits.prot @[quasar.scala 276:21] + io.sb_axi.ar.bits.cache <= _T_13.ar.bits.cache @[quasar.scala 276:21] + io.sb_axi.ar.bits.lock <= _T_13.ar.bits.lock @[quasar.scala 276:21] + io.sb_axi.ar.bits.burst <= _T_13.ar.bits.burst @[quasar.scala 276:21] + io.sb_axi.ar.bits.size <= _T_13.ar.bits.size @[quasar.scala 276:21] + io.sb_axi.ar.bits.len <= _T_13.ar.bits.len @[quasar.scala 276:21] + io.sb_axi.ar.bits.region <= _T_13.ar.bits.region @[quasar.scala 276:21] + io.sb_axi.ar.bits.addr <= _T_13.ar.bits.addr @[quasar.scala 276:21] + io.sb_axi.ar.bits.id <= _T_13.ar.bits.id @[quasar.scala 276:21] + io.sb_axi.ar.valid <= _T_13.ar.valid @[quasar.scala 276:21] + _T_13.ar.ready <= io.sb_axi.ar.ready @[quasar.scala 276:21] + _T_13.b.bits.id <= io.sb_axi.b.bits.id @[quasar.scala 276:21] + _T_13.b.bits.resp <= io.sb_axi.b.bits.resp @[quasar.scala 276:21] + _T_13.b.valid <= io.sb_axi.b.valid @[quasar.scala 276:21] + io.sb_axi.b.ready <= _T_13.b.ready @[quasar.scala 276:21] + io.sb_axi.w.bits.last <= _T_13.w.bits.last @[quasar.scala 276:21] + io.sb_axi.w.bits.strb <= _T_13.w.bits.strb @[quasar.scala 276:21] + io.sb_axi.w.bits.data <= _T_13.w.bits.data @[quasar.scala 276:21] + io.sb_axi.w.valid <= _T_13.w.valid @[quasar.scala 276:21] + _T_13.w.ready <= io.sb_axi.w.ready @[quasar.scala 276:21] + io.sb_axi.aw.bits.qos <= _T_13.aw.bits.qos @[quasar.scala 276:21] + io.sb_axi.aw.bits.prot <= _T_13.aw.bits.prot @[quasar.scala 276:21] + io.sb_axi.aw.bits.cache <= _T_13.aw.bits.cache @[quasar.scala 276:21] + io.sb_axi.aw.bits.lock <= _T_13.aw.bits.lock @[quasar.scala 276:21] + io.sb_axi.aw.bits.burst <= _T_13.aw.bits.burst @[quasar.scala 276:21] + io.sb_axi.aw.bits.size <= _T_13.aw.bits.size @[quasar.scala 276:21] + io.sb_axi.aw.bits.len <= _T_13.aw.bits.len @[quasar.scala 276:21] + io.sb_axi.aw.bits.region <= _T_13.aw.bits.region @[quasar.scala 276:21] + io.sb_axi.aw.bits.addr <= _T_13.aw.bits.addr @[quasar.scala 276:21] + io.sb_axi.aw.bits.id <= _T_13.aw.bits.id @[quasar.scala 276:21] + io.sb_axi.aw.valid <= _T_13.aw.valid @[quasar.scala 276:21] + _T_13.aw.ready <= io.sb_axi.aw.ready @[quasar.scala 276:21] + wire _T_14 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar.scala 277:36] + _T_14.r.bits.last <= UInt<1>("h00") @[quasar.scala 277:36] + _T_14.r.bits.resp <= UInt<2>("h00") @[quasar.scala 277:36] + _T_14.r.bits.data <= UInt<64>("h00") @[quasar.scala 277:36] + _T_14.r.bits.id <= UInt<3>("h00") @[quasar.scala 277:36] + _T_14.r.valid <= UInt<1>("h00") @[quasar.scala 277:36] + _T_14.r.ready <= UInt<1>("h00") @[quasar.scala 277:36] + _T_14.ar.bits.qos <= UInt<4>("h00") @[quasar.scala 277:36] + _T_14.ar.bits.prot <= UInt<3>("h00") @[quasar.scala 277:36] + _T_14.ar.bits.cache <= UInt<4>("h00") @[quasar.scala 277:36] + _T_14.ar.bits.lock <= UInt<1>("h00") @[quasar.scala 277:36] + _T_14.ar.bits.burst <= UInt<2>("h00") @[quasar.scala 277:36] + _T_14.ar.bits.size <= UInt<3>("h00") @[quasar.scala 277:36] + _T_14.ar.bits.len <= UInt<8>("h00") @[quasar.scala 277:36] + _T_14.ar.bits.region <= UInt<4>("h00") @[quasar.scala 277:36] + _T_14.ar.bits.addr <= UInt<32>("h00") @[quasar.scala 277:36] + _T_14.ar.bits.id <= UInt<3>("h00") @[quasar.scala 277:36] + _T_14.ar.valid <= UInt<1>("h00") @[quasar.scala 277:36] + _T_14.ar.ready <= UInt<1>("h00") @[quasar.scala 277:36] + _T_14.b.bits.id <= UInt<3>("h00") @[quasar.scala 277:36] + _T_14.b.bits.resp <= UInt<2>("h00") @[quasar.scala 277:36] + _T_14.b.valid <= UInt<1>("h00") @[quasar.scala 277:36] + _T_14.b.ready <= UInt<1>("h00") @[quasar.scala 277:36] + _T_14.w.bits.last <= UInt<1>("h00") @[quasar.scala 277:36] + _T_14.w.bits.strb <= UInt<8>("h00") @[quasar.scala 277:36] + _T_14.w.bits.data <= UInt<64>("h00") @[quasar.scala 277:36] + _T_14.w.valid <= UInt<1>("h00") @[quasar.scala 277:36] + _T_14.w.ready <= UInt<1>("h00") @[quasar.scala 277:36] + _T_14.aw.bits.qos <= UInt<4>("h00") @[quasar.scala 277:36] + _T_14.aw.bits.prot <= UInt<3>("h00") @[quasar.scala 277:36] + _T_14.aw.bits.cache <= UInt<4>("h00") @[quasar.scala 277:36] + _T_14.aw.bits.lock <= UInt<1>("h00") @[quasar.scala 277:36] + _T_14.aw.bits.burst <= UInt<2>("h00") @[quasar.scala 277:36] + _T_14.aw.bits.size <= UInt<3>("h00") @[quasar.scala 277:36] + _T_14.aw.bits.len <= UInt<8>("h00") @[quasar.scala 277:36] + _T_14.aw.bits.region <= UInt<4>("h00") @[quasar.scala 277:36] + _T_14.aw.bits.addr <= UInt<32>("h00") @[quasar.scala 277:36] + _T_14.aw.bits.id <= UInt<3>("h00") @[quasar.scala 277:36] + _T_14.aw.valid <= UInt<1>("h00") @[quasar.scala 277:36] + _T_14.aw.ready <= UInt<1>("h00") @[quasar.scala 277:36] + _T_14.r.bits.last <= io.ifu_axi.r.bits.last @[quasar.scala 277:21] + _T_14.r.bits.resp <= io.ifu_axi.r.bits.resp @[quasar.scala 277:21] + _T_14.r.bits.data <= io.ifu_axi.r.bits.data @[quasar.scala 277:21] + _T_14.r.bits.id <= io.ifu_axi.r.bits.id @[quasar.scala 277:21] + _T_14.r.valid <= io.ifu_axi.r.valid @[quasar.scala 277:21] + io.ifu_axi.r.ready <= _T_14.r.ready @[quasar.scala 277:21] + io.ifu_axi.ar.bits.qos <= _T_14.ar.bits.qos @[quasar.scala 277:21] + io.ifu_axi.ar.bits.prot <= _T_14.ar.bits.prot @[quasar.scala 277:21] + io.ifu_axi.ar.bits.cache <= _T_14.ar.bits.cache @[quasar.scala 277:21] + io.ifu_axi.ar.bits.lock <= _T_14.ar.bits.lock @[quasar.scala 277:21] + io.ifu_axi.ar.bits.burst <= _T_14.ar.bits.burst @[quasar.scala 277:21] + io.ifu_axi.ar.bits.size <= _T_14.ar.bits.size @[quasar.scala 277:21] + io.ifu_axi.ar.bits.len <= _T_14.ar.bits.len @[quasar.scala 277:21] + io.ifu_axi.ar.bits.region <= _T_14.ar.bits.region @[quasar.scala 277:21] + io.ifu_axi.ar.bits.addr <= _T_14.ar.bits.addr @[quasar.scala 277:21] + io.ifu_axi.ar.bits.id <= _T_14.ar.bits.id @[quasar.scala 277:21] + io.ifu_axi.ar.valid <= _T_14.ar.valid @[quasar.scala 277:21] + _T_14.ar.ready <= io.ifu_axi.ar.ready @[quasar.scala 277:21] + _T_14.b.bits.id <= io.ifu_axi.b.bits.id @[quasar.scala 277:21] + _T_14.b.bits.resp <= io.ifu_axi.b.bits.resp @[quasar.scala 277:21] + _T_14.b.valid <= io.ifu_axi.b.valid @[quasar.scala 277:21] + io.ifu_axi.b.ready <= _T_14.b.ready @[quasar.scala 277:21] + io.ifu_axi.w.bits.last <= _T_14.w.bits.last @[quasar.scala 277:21] + io.ifu_axi.w.bits.strb <= _T_14.w.bits.strb @[quasar.scala 277:21] + io.ifu_axi.w.bits.data <= _T_14.w.bits.data @[quasar.scala 277:21] + io.ifu_axi.w.valid <= _T_14.w.valid @[quasar.scala 277:21] + _T_14.w.ready <= io.ifu_axi.w.ready @[quasar.scala 277:21] + io.ifu_axi.aw.bits.qos <= _T_14.aw.bits.qos @[quasar.scala 277:21] + io.ifu_axi.aw.bits.prot <= _T_14.aw.bits.prot @[quasar.scala 277:21] + io.ifu_axi.aw.bits.cache <= _T_14.aw.bits.cache @[quasar.scala 277:21] + io.ifu_axi.aw.bits.lock <= _T_14.aw.bits.lock @[quasar.scala 277:21] + io.ifu_axi.aw.bits.burst <= _T_14.aw.bits.burst @[quasar.scala 277:21] + io.ifu_axi.aw.bits.size <= _T_14.aw.bits.size @[quasar.scala 277:21] + io.ifu_axi.aw.bits.len <= _T_14.aw.bits.len @[quasar.scala 277:21] + io.ifu_axi.aw.bits.region <= _T_14.aw.bits.region @[quasar.scala 277:21] + io.ifu_axi.aw.bits.addr <= _T_14.aw.bits.addr @[quasar.scala 277:21] + io.ifu_axi.aw.bits.id <= _T_14.aw.bits.id @[quasar.scala 277:21] + io.ifu_axi.aw.valid <= _T_14.aw.valid @[quasar.scala 277:21] + _T_14.aw.ready <= io.ifu_axi.aw.ready @[quasar.scala 277:21] + wire _T_15 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar.scala 278:36] + _T_15.r.bits.last <= UInt<1>("h00") @[quasar.scala 278:36] + _T_15.r.bits.resp <= UInt<2>("h00") @[quasar.scala 278:36] + _T_15.r.bits.data <= UInt<64>("h00") @[quasar.scala 278:36] + _T_15.r.bits.id <= UInt<3>("h00") @[quasar.scala 278:36] + _T_15.r.valid <= UInt<1>("h00") @[quasar.scala 278:36] + _T_15.r.ready <= UInt<1>("h00") @[quasar.scala 278:36] + _T_15.ar.bits.qos <= UInt<4>("h00") @[quasar.scala 278:36] + _T_15.ar.bits.prot <= UInt<3>("h00") @[quasar.scala 278:36] + _T_15.ar.bits.cache <= UInt<4>("h00") @[quasar.scala 278:36] + _T_15.ar.bits.lock <= UInt<1>("h00") @[quasar.scala 278:36] + _T_15.ar.bits.burst <= UInt<2>("h00") @[quasar.scala 278:36] + _T_15.ar.bits.size <= UInt<3>("h00") @[quasar.scala 278:36] + _T_15.ar.bits.len <= UInt<8>("h00") @[quasar.scala 278:36] + _T_15.ar.bits.region <= UInt<4>("h00") @[quasar.scala 278:36] + _T_15.ar.bits.addr <= UInt<32>("h00") @[quasar.scala 278:36] + _T_15.ar.bits.id <= UInt<3>("h00") @[quasar.scala 278:36] + _T_15.ar.valid <= UInt<1>("h00") @[quasar.scala 278:36] + _T_15.ar.ready <= UInt<1>("h00") @[quasar.scala 278:36] + _T_15.b.bits.id <= UInt<3>("h00") @[quasar.scala 278:36] + _T_15.b.bits.resp <= UInt<2>("h00") @[quasar.scala 278:36] + _T_15.b.valid <= UInt<1>("h00") @[quasar.scala 278:36] + _T_15.b.ready <= UInt<1>("h00") @[quasar.scala 278:36] + _T_15.w.bits.last <= UInt<1>("h00") @[quasar.scala 278:36] + _T_15.w.bits.strb <= UInt<8>("h00") @[quasar.scala 278:36] + _T_15.w.bits.data <= UInt<64>("h00") @[quasar.scala 278:36] + _T_15.w.valid <= UInt<1>("h00") @[quasar.scala 278:36] + _T_15.w.ready <= UInt<1>("h00") @[quasar.scala 278:36] + _T_15.aw.bits.qos <= UInt<4>("h00") @[quasar.scala 278:36] + _T_15.aw.bits.prot <= UInt<3>("h00") @[quasar.scala 278:36] + _T_15.aw.bits.cache <= UInt<4>("h00") @[quasar.scala 278:36] + _T_15.aw.bits.lock <= UInt<1>("h00") @[quasar.scala 278:36] + _T_15.aw.bits.burst <= UInt<2>("h00") @[quasar.scala 278:36] + _T_15.aw.bits.size <= UInt<3>("h00") @[quasar.scala 278:36] + _T_15.aw.bits.len <= UInt<8>("h00") @[quasar.scala 278:36] + _T_15.aw.bits.region <= UInt<4>("h00") @[quasar.scala 278:36] + _T_15.aw.bits.addr <= UInt<32>("h00") @[quasar.scala 278:36] + _T_15.aw.bits.id <= UInt<3>("h00") @[quasar.scala 278:36] + _T_15.aw.valid <= UInt<1>("h00") @[quasar.scala 278:36] + _T_15.aw.ready <= UInt<1>("h00") @[quasar.scala 278:36] + _T_15.r.bits.last <= io.lsu_axi.r.bits.last @[quasar.scala 278:21] + _T_15.r.bits.resp <= io.lsu_axi.r.bits.resp @[quasar.scala 278:21] + _T_15.r.bits.data <= io.lsu_axi.r.bits.data @[quasar.scala 278:21] + _T_15.r.bits.id <= io.lsu_axi.r.bits.id @[quasar.scala 278:21] + _T_15.r.valid <= io.lsu_axi.r.valid @[quasar.scala 278:21] + io.lsu_axi.r.ready <= _T_15.r.ready @[quasar.scala 278:21] + io.lsu_axi.ar.bits.qos <= _T_15.ar.bits.qos @[quasar.scala 278:21] + io.lsu_axi.ar.bits.prot <= _T_15.ar.bits.prot @[quasar.scala 278:21] + io.lsu_axi.ar.bits.cache <= _T_15.ar.bits.cache @[quasar.scala 278:21] + io.lsu_axi.ar.bits.lock <= _T_15.ar.bits.lock @[quasar.scala 278:21] + io.lsu_axi.ar.bits.burst <= _T_15.ar.bits.burst @[quasar.scala 278:21] + io.lsu_axi.ar.bits.size <= _T_15.ar.bits.size @[quasar.scala 278:21] + io.lsu_axi.ar.bits.len <= _T_15.ar.bits.len @[quasar.scala 278:21] + io.lsu_axi.ar.bits.region <= _T_15.ar.bits.region @[quasar.scala 278:21] + io.lsu_axi.ar.bits.addr <= _T_15.ar.bits.addr @[quasar.scala 278:21] + io.lsu_axi.ar.bits.id <= _T_15.ar.bits.id @[quasar.scala 278:21] + io.lsu_axi.ar.valid <= _T_15.ar.valid @[quasar.scala 278:21] + _T_15.ar.ready <= io.lsu_axi.ar.ready @[quasar.scala 278:21] + _T_15.b.bits.id <= io.lsu_axi.b.bits.id @[quasar.scala 278:21] + _T_15.b.bits.resp <= io.lsu_axi.b.bits.resp @[quasar.scala 278:21] + _T_15.b.valid <= io.lsu_axi.b.valid @[quasar.scala 278:21] + io.lsu_axi.b.ready <= _T_15.b.ready @[quasar.scala 278:21] + io.lsu_axi.w.bits.last <= _T_15.w.bits.last @[quasar.scala 278:21] + io.lsu_axi.w.bits.strb <= _T_15.w.bits.strb @[quasar.scala 278:21] + io.lsu_axi.w.bits.data <= _T_15.w.bits.data @[quasar.scala 278:21] + io.lsu_axi.w.valid <= _T_15.w.valid @[quasar.scala 278:21] + _T_15.w.ready <= io.lsu_axi.w.ready @[quasar.scala 278:21] + io.lsu_axi.aw.bits.qos <= _T_15.aw.bits.qos @[quasar.scala 278:21] + io.lsu_axi.aw.bits.prot <= _T_15.aw.bits.prot @[quasar.scala 278:21] + io.lsu_axi.aw.bits.cache <= _T_15.aw.bits.cache @[quasar.scala 278:21] + io.lsu_axi.aw.bits.lock <= _T_15.aw.bits.lock @[quasar.scala 278:21] + io.lsu_axi.aw.bits.burst <= _T_15.aw.bits.burst @[quasar.scala 278:21] + io.lsu_axi.aw.bits.size <= _T_15.aw.bits.size @[quasar.scala 278:21] + io.lsu_axi.aw.bits.len <= _T_15.aw.bits.len @[quasar.scala 278:21] + io.lsu_axi.aw.bits.region <= _T_15.aw.bits.region @[quasar.scala 278:21] + io.lsu_axi.aw.bits.addr <= _T_15.aw.bits.addr @[quasar.scala 278:21] + io.lsu_axi.aw.bits.id <= _T_15.aw.bits.id @[quasar.scala 278:21] + io.lsu_axi.aw.valid <= _T_15.aw.valid @[quasar.scala 278:21] + _T_15.aw.ready <= io.lsu_axi.aw.ready @[quasar.scala 278:21] module quasar_wrapper : input clock : Clock input reset : AsyncReset - output io : {flip dbg_rst_l : AsyncReset, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip jtag_id : UInt<31>, lsu_brg : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ifu_brg : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, sb_brg : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dma_brg : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip lsu_bus_clk_en : UInt<1>, flip ifu_bus_clk_en : UInt<1>, flip dbg_bus_clk_en : UInt<1>, flip dma_bus_clk_en : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip extintsrc_req : UInt<31>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, flip jtag_tck : Clock, flip jtag_tms : UInt<1>, flip jtag_tdi : UInt<1>, flip jtag_trst_n : UInt<1>, jtag_tdo : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_halt_status : UInt<1>, o_debug_mode_status : UInt<1>, o_cpu_run_ack : UInt<1>, flip mbist_mode : UInt<1>, rv_trace_pkt : {rv_i_valid_ip : UInt<2>, rv_i_insn_ip : UInt<32>, rv_i_address_ip : UInt<32>, rv_i_exception_ip : UInt<2>, rv_i_ecause_ip : UInt<5>, rv_i_interrupt_ip : UInt<2>, rv_i_tval_ip : UInt<32>}, flip scan_mode : UInt<1>} + output io : {flip dbg_rst_l : AsyncReset, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip jtag_id : UInt<31>, lsu_brg : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, ifu_brg : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, sb_brg : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, dma_brg : {flip sig : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, flip hsel : UInt<1>, flip hreadyin : UInt<1>}, flip lsu_bus_clk_en : UInt<1>, flip ifu_bus_clk_en : UInt<1>, flip dbg_bus_clk_en : UInt<1>, flip dma_bus_clk_en : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip extintsrc_req : UInt<31>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, flip jtag_tck : Clock, flip jtag_tms : UInt<1>, flip jtag_tdi : UInt<1>, flip jtag_trst_n : UInt<1>, jtag_tdo : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_halt_status : UInt<1>, o_debug_mode_status : UInt<1>, o_cpu_run_ack : UInt<1>, flip mbist_mode : UInt<1>, rv_trace_pkt : {rv_i_valid_ip : UInt<2>, rv_i_insn_ip : UInt<32>, rv_i_address_ip : UInt<32>, rv_i_exception_ip : UInt<2>, rv_i_ecause_ip : UInt<5>, rv_i_interrupt_ip : UInt<2>, rv_i_tval_ip : UInt<32>}, flip scan_mode : UInt<1>} inst mem of mem @[quasar_wrapper.scala 63:19] mem.scan_mode is invalid @@ -115025,258 +115016,368 @@ circuit quasar_wrapper : mem.iccm.correction_state <= core.io.iccm.correction_state @[quasar_wrapper.scala 95:16] mem.iccm.buf_correct_ecc <= core.io.iccm.buf_correct_ecc @[quasar_wrapper.scala 95:16] mem.iccm.rw_addr <= core.io.iccm.rw_addr @[quasar_wrapper.scala 95:16] - wire _T : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}} @[quasar_wrapper.scala 99:36] - _T.out.hwdata <= UInt<64>("h00") @[quasar_wrapper.scala 99:36] - _T.out.hwrite <= UInt<1>("h00") @[quasar_wrapper.scala 99:36] - _T.out.htrans <= UInt<2>("h00") @[quasar_wrapper.scala 99:36] - _T.out.hsize <= UInt<3>("h00") @[quasar_wrapper.scala 99:36] - _T.out.hprot <= UInt<4>("h00") @[quasar_wrapper.scala 99:36] - _T.out.hmastlock <= UInt<1>("h00") @[quasar_wrapper.scala 99:36] - _T.out.hburst <= UInt<3>("h00") @[quasar_wrapper.scala 99:36] - _T.out.haddr <= UInt<32>("h00") @[quasar_wrapper.scala 99:36] - _T.in.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 99:36] - _T.in.hready <= UInt<1>("h00") @[quasar_wrapper.scala 99:36] - _T.in.hrdata <= UInt<64>("h00") @[quasar_wrapper.scala 99:36] - _T.out.hwdata <= core.io.ifu_ahb.out.hwdata @[quasar_wrapper.scala 99:21] - _T.out.hwrite <= core.io.ifu_ahb.out.hwrite @[quasar_wrapper.scala 99:21] - _T.out.htrans <= core.io.ifu_ahb.out.htrans @[quasar_wrapper.scala 99:21] - _T.out.hsize <= core.io.ifu_ahb.out.hsize @[quasar_wrapper.scala 99:21] - _T.out.hprot <= core.io.ifu_ahb.out.hprot @[quasar_wrapper.scala 99:21] - _T.out.hmastlock <= core.io.ifu_ahb.out.hmastlock @[quasar_wrapper.scala 99:21] - _T.out.hburst <= core.io.ifu_ahb.out.hburst @[quasar_wrapper.scala 99:21] - _T.out.haddr <= core.io.ifu_ahb.out.haddr @[quasar_wrapper.scala 99:21] - core.io.ifu_ahb.in.hresp <= _T.in.hresp @[quasar_wrapper.scala 99:21] - core.io.ifu_ahb.in.hready <= _T.in.hready @[quasar_wrapper.scala 99:21] - core.io.ifu_ahb.in.hrdata <= _T.in.hrdata @[quasar_wrapper.scala 99:21] - wire _T_1 : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}} @[quasar_wrapper.scala 100:36] - _T_1.out.hwdata <= UInt<64>("h00") @[quasar_wrapper.scala 100:36] - _T_1.out.hwrite <= UInt<1>("h00") @[quasar_wrapper.scala 100:36] - _T_1.out.htrans <= UInt<2>("h00") @[quasar_wrapper.scala 100:36] - _T_1.out.hsize <= UInt<3>("h00") @[quasar_wrapper.scala 100:36] - _T_1.out.hprot <= UInt<4>("h00") @[quasar_wrapper.scala 100:36] - _T_1.out.hmastlock <= UInt<1>("h00") @[quasar_wrapper.scala 100:36] - _T_1.out.hburst <= UInt<3>("h00") @[quasar_wrapper.scala 100:36] - _T_1.out.haddr <= UInt<32>("h00") @[quasar_wrapper.scala 100:36] - _T_1.in.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 100:36] - _T_1.in.hready <= UInt<1>("h00") @[quasar_wrapper.scala 100:36] - _T_1.in.hrdata <= UInt<64>("h00") @[quasar_wrapper.scala 100:36] - _T_1.out.hwdata <= core.io.lsu_ahb.out.hwdata @[quasar_wrapper.scala 100:21] - _T_1.out.hwrite <= core.io.lsu_ahb.out.hwrite @[quasar_wrapper.scala 100:21] - _T_1.out.htrans <= core.io.lsu_ahb.out.htrans @[quasar_wrapper.scala 100:21] - _T_1.out.hsize <= core.io.lsu_ahb.out.hsize @[quasar_wrapper.scala 100:21] - _T_1.out.hprot <= core.io.lsu_ahb.out.hprot @[quasar_wrapper.scala 100:21] - _T_1.out.hmastlock <= core.io.lsu_ahb.out.hmastlock @[quasar_wrapper.scala 100:21] - _T_1.out.hburst <= core.io.lsu_ahb.out.hburst @[quasar_wrapper.scala 100:21] - _T_1.out.haddr <= core.io.lsu_ahb.out.haddr @[quasar_wrapper.scala 100:21] - core.io.lsu_ahb.in.hresp <= _T_1.in.hresp @[quasar_wrapper.scala 100:21] - core.io.lsu_ahb.in.hready <= _T_1.in.hready @[quasar_wrapper.scala 100:21] - core.io.lsu_ahb.in.hrdata <= _T_1.in.hrdata @[quasar_wrapper.scala 100:21] - wire _T_2 : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}} @[quasar_wrapper.scala 101:36] - _T_2.out.hwdata <= UInt<64>("h00") @[quasar_wrapper.scala 101:36] - _T_2.out.hwrite <= UInt<1>("h00") @[quasar_wrapper.scala 101:36] - _T_2.out.htrans <= UInt<2>("h00") @[quasar_wrapper.scala 101:36] - _T_2.out.hsize <= UInt<3>("h00") @[quasar_wrapper.scala 101:36] - _T_2.out.hprot <= UInt<4>("h00") @[quasar_wrapper.scala 101:36] - _T_2.out.hmastlock <= UInt<1>("h00") @[quasar_wrapper.scala 101:36] - _T_2.out.hburst <= UInt<3>("h00") @[quasar_wrapper.scala 101:36] - _T_2.out.haddr <= UInt<32>("h00") @[quasar_wrapper.scala 101:36] - _T_2.in.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 101:36] - _T_2.in.hready <= UInt<1>("h00") @[quasar_wrapper.scala 101:36] - _T_2.in.hrdata <= UInt<64>("h00") @[quasar_wrapper.scala 101:36] - _T_2.out.hwdata <= core.io.sb_ahb.out.hwdata @[quasar_wrapper.scala 101:21] - _T_2.out.hwrite <= core.io.sb_ahb.out.hwrite @[quasar_wrapper.scala 101:21] - _T_2.out.htrans <= core.io.sb_ahb.out.htrans @[quasar_wrapper.scala 101:21] - _T_2.out.hsize <= core.io.sb_ahb.out.hsize @[quasar_wrapper.scala 101:21] - _T_2.out.hprot <= core.io.sb_ahb.out.hprot @[quasar_wrapper.scala 101:21] - _T_2.out.hmastlock <= core.io.sb_ahb.out.hmastlock @[quasar_wrapper.scala 101:21] - _T_2.out.hburst <= core.io.sb_ahb.out.hburst @[quasar_wrapper.scala 101:21] - _T_2.out.haddr <= core.io.sb_ahb.out.haddr @[quasar_wrapper.scala 101:21] - core.io.sb_ahb.in.hresp <= _T_2.in.hresp @[quasar_wrapper.scala 101:21] - core.io.sb_ahb.in.hready <= _T_2.in.hready @[quasar_wrapper.scala 101:21] - core.io.sb_ahb.in.hrdata <= _T_2.in.hrdata @[quasar_wrapper.scala 101:21] - wire _T_3 : {flip sig : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, flip hsel : UInt<1>, flip hreadyin : UInt<1>} @[quasar_wrapper.scala 102:36] - _T_3.hreadyin <= UInt<1>("h00") @[quasar_wrapper.scala 102:36] - _T_3.hsel <= UInt<1>("h00") @[quasar_wrapper.scala 102:36] - _T_3.sig.out.hwdata <= UInt<64>("h00") @[quasar_wrapper.scala 102:36] - _T_3.sig.out.hwrite <= UInt<1>("h00") @[quasar_wrapper.scala 102:36] - _T_3.sig.out.htrans <= UInt<2>("h00") @[quasar_wrapper.scala 102:36] - _T_3.sig.out.hsize <= UInt<3>("h00") @[quasar_wrapper.scala 102:36] - _T_3.sig.out.hprot <= UInt<4>("h00") @[quasar_wrapper.scala 102:36] - _T_3.sig.out.hmastlock <= UInt<1>("h00") @[quasar_wrapper.scala 102:36] - _T_3.sig.out.hburst <= UInt<3>("h00") @[quasar_wrapper.scala 102:36] - _T_3.sig.out.haddr <= UInt<32>("h00") @[quasar_wrapper.scala 102:36] - _T_3.sig.in.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 102:36] - _T_3.sig.in.hready <= UInt<1>("h00") @[quasar_wrapper.scala 102:36] - _T_3.sig.in.hrdata <= UInt<64>("h00") @[quasar_wrapper.scala 102:36] - core.io.dma_ahb.hreadyin <= _T_3.hreadyin @[quasar_wrapper.scala 102:21] - core.io.dma_ahb.hsel <= _T_3.hsel @[quasar_wrapper.scala 102:21] - core.io.dma_ahb.sig.out.hwdata <= _T_3.sig.out.hwdata @[quasar_wrapper.scala 102:21] - core.io.dma_ahb.sig.out.hwrite <= _T_3.sig.out.hwrite @[quasar_wrapper.scala 102:21] - core.io.dma_ahb.sig.out.htrans <= _T_3.sig.out.htrans @[quasar_wrapper.scala 102:21] - core.io.dma_ahb.sig.out.hsize <= _T_3.sig.out.hsize @[quasar_wrapper.scala 102:21] - core.io.dma_ahb.sig.out.hprot <= _T_3.sig.out.hprot @[quasar_wrapper.scala 102:21] - core.io.dma_ahb.sig.out.hmastlock <= _T_3.sig.out.hmastlock @[quasar_wrapper.scala 102:21] - core.io.dma_ahb.sig.out.hburst <= _T_3.sig.out.hburst @[quasar_wrapper.scala 102:21] - core.io.dma_ahb.sig.out.haddr <= _T_3.sig.out.haddr @[quasar_wrapper.scala 102:21] - _T_3.sig.in.hresp <= core.io.dma_ahb.sig.in.hresp @[quasar_wrapper.scala 102:21] - _T_3.sig.in.hready <= core.io.dma_ahb.sig.in.hready @[quasar_wrapper.scala 102:21] - _T_3.sig.in.hrdata <= core.io.dma_ahb.sig.in.hrdata @[quasar_wrapper.scala 102:21] - core.io.lsu_axi.r.bits.last <= io.lsu_brg.r.bits.last @[quasar_wrapper.scala 104:21] - core.io.lsu_axi.r.bits.resp <= io.lsu_brg.r.bits.resp @[quasar_wrapper.scala 104:21] - core.io.lsu_axi.r.bits.data <= io.lsu_brg.r.bits.data @[quasar_wrapper.scala 104:21] - core.io.lsu_axi.r.bits.id <= io.lsu_brg.r.bits.id @[quasar_wrapper.scala 104:21] - core.io.lsu_axi.r.valid <= io.lsu_brg.r.valid @[quasar_wrapper.scala 104:21] - io.lsu_brg.r.ready <= core.io.lsu_axi.r.ready @[quasar_wrapper.scala 104:21] - io.lsu_brg.ar.bits.qos <= core.io.lsu_axi.ar.bits.qos @[quasar_wrapper.scala 104:21] - io.lsu_brg.ar.bits.prot <= core.io.lsu_axi.ar.bits.prot @[quasar_wrapper.scala 104:21] - io.lsu_brg.ar.bits.cache <= core.io.lsu_axi.ar.bits.cache @[quasar_wrapper.scala 104:21] - io.lsu_brg.ar.bits.lock <= core.io.lsu_axi.ar.bits.lock @[quasar_wrapper.scala 104:21] - io.lsu_brg.ar.bits.burst <= core.io.lsu_axi.ar.bits.burst @[quasar_wrapper.scala 104:21] - io.lsu_brg.ar.bits.size <= core.io.lsu_axi.ar.bits.size @[quasar_wrapper.scala 104:21] - io.lsu_brg.ar.bits.len <= core.io.lsu_axi.ar.bits.len @[quasar_wrapper.scala 104:21] - io.lsu_brg.ar.bits.region <= core.io.lsu_axi.ar.bits.region @[quasar_wrapper.scala 104:21] - io.lsu_brg.ar.bits.addr <= core.io.lsu_axi.ar.bits.addr @[quasar_wrapper.scala 104:21] - io.lsu_brg.ar.bits.id <= core.io.lsu_axi.ar.bits.id @[quasar_wrapper.scala 104:21] - io.lsu_brg.ar.valid <= core.io.lsu_axi.ar.valid @[quasar_wrapper.scala 104:21] - core.io.lsu_axi.ar.ready <= io.lsu_brg.ar.ready @[quasar_wrapper.scala 104:21] - core.io.lsu_axi.b.bits.id <= io.lsu_brg.b.bits.id @[quasar_wrapper.scala 104:21] - core.io.lsu_axi.b.bits.resp <= io.lsu_brg.b.bits.resp @[quasar_wrapper.scala 104:21] - core.io.lsu_axi.b.valid <= io.lsu_brg.b.valid @[quasar_wrapper.scala 104:21] - io.lsu_brg.b.ready <= core.io.lsu_axi.b.ready @[quasar_wrapper.scala 104:21] - io.lsu_brg.w.bits.last <= core.io.lsu_axi.w.bits.last @[quasar_wrapper.scala 104:21] - io.lsu_brg.w.bits.strb <= core.io.lsu_axi.w.bits.strb @[quasar_wrapper.scala 104:21] - io.lsu_brg.w.bits.data <= core.io.lsu_axi.w.bits.data @[quasar_wrapper.scala 104:21] - io.lsu_brg.w.valid <= core.io.lsu_axi.w.valid @[quasar_wrapper.scala 104:21] - core.io.lsu_axi.w.ready <= io.lsu_brg.w.ready @[quasar_wrapper.scala 104:21] - io.lsu_brg.aw.bits.qos <= core.io.lsu_axi.aw.bits.qos @[quasar_wrapper.scala 104:21] - io.lsu_brg.aw.bits.prot <= core.io.lsu_axi.aw.bits.prot @[quasar_wrapper.scala 104:21] - io.lsu_brg.aw.bits.cache <= core.io.lsu_axi.aw.bits.cache @[quasar_wrapper.scala 104:21] - io.lsu_brg.aw.bits.lock <= core.io.lsu_axi.aw.bits.lock @[quasar_wrapper.scala 104:21] - io.lsu_brg.aw.bits.burst <= core.io.lsu_axi.aw.bits.burst @[quasar_wrapper.scala 104:21] - io.lsu_brg.aw.bits.size <= core.io.lsu_axi.aw.bits.size @[quasar_wrapper.scala 104:21] - io.lsu_brg.aw.bits.len <= core.io.lsu_axi.aw.bits.len @[quasar_wrapper.scala 104:21] - io.lsu_brg.aw.bits.region <= core.io.lsu_axi.aw.bits.region @[quasar_wrapper.scala 104:21] - io.lsu_brg.aw.bits.addr <= core.io.lsu_axi.aw.bits.addr @[quasar_wrapper.scala 104:21] - io.lsu_brg.aw.bits.id <= core.io.lsu_axi.aw.bits.id @[quasar_wrapper.scala 104:21] - io.lsu_brg.aw.valid <= core.io.lsu_axi.aw.valid @[quasar_wrapper.scala 104:21] - core.io.lsu_axi.aw.ready <= io.lsu_brg.aw.ready @[quasar_wrapper.scala 104:21] - core.io.ifu_axi.r.bits.last <= io.ifu_brg.r.bits.last @[quasar_wrapper.scala 105:21] - core.io.ifu_axi.r.bits.resp <= io.ifu_brg.r.bits.resp @[quasar_wrapper.scala 105:21] - core.io.ifu_axi.r.bits.data <= io.ifu_brg.r.bits.data @[quasar_wrapper.scala 105:21] - core.io.ifu_axi.r.bits.id <= io.ifu_brg.r.bits.id @[quasar_wrapper.scala 105:21] - core.io.ifu_axi.r.valid <= io.ifu_brg.r.valid @[quasar_wrapper.scala 105:21] - io.ifu_brg.r.ready <= core.io.ifu_axi.r.ready @[quasar_wrapper.scala 105:21] - io.ifu_brg.ar.bits.qos <= core.io.ifu_axi.ar.bits.qos @[quasar_wrapper.scala 105:21] - io.ifu_brg.ar.bits.prot <= core.io.ifu_axi.ar.bits.prot @[quasar_wrapper.scala 105:21] - io.ifu_brg.ar.bits.cache <= core.io.ifu_axi.ar.bits.cache @[quasar_wrapper.scala 105:21] - io.ifu_brg.ar.bits.lock <= core.io.ifu_axi.ar.bits.lock @[quasar_wrapper.scala 105:21] - io.ifu_brg.ar.bits.burst <= core.io.ifu_axi.ar.bits.burst @[quasar_wrapper.scala 105:21] - io.ifu_brg.ar.bits.size <= core.io.ifu_axi.ar.bits.size @[quasar_wrapper.scala 105:21] - io.ifu_brg.ar.bits.len <= core.io.ifu_axi.ar.bits.len @[quasar_wrapper.scala 105:21] - io.ifu_brg.ar.bits.region <= core.io.ifu_axi.ar.bits.region @[quasar_wrapper.scala 105:21] - io.ifu_brg.ar.bits.addr <= core.io.ifu_axi.ar.bits.addr @[quasar_wrapper.scala 105:21] - io.ifu_brg.ar.bits.id <= core.io.ifu_axi.ar.bits.id @[quasar_wrapper.scala 105:21] - io.ifu_brg.ar.valid <= core.io.ifu_axi.ar.valid @[quasar_wrapper.scala 105:21] - core.io.ifu_axi.ar.ready <= io.ifu_brg.ar.ready @[quasar_wrapper.scala 105:21] - core.io.ifu_axi.b.bits.id <= io.ifu_brg.b.bits.id @[quasar_wrapper.scala 105:21] - core.io.ifu_axi.b.bits.resp <= io.ifu_brg.b.bits.resp @[quasar_wrapper.scala 105:21] - core.io.ifu_axi.b.valid <= io.ifu_brg.b.valid @[quasar_wrapper.scala 105:21] - io.ifu_brg.b.ready <= core.io.ifu_axi.b.ready @[quasar_wrapper.scala 105:21] - io.ifu_brg.w.bits.last <= core.io.ifu_axi.w.bits.last @[quasar_wrapper.scala 105:21] - io.ifu_brg.w.bits.strb <= core.io.ifu_axi.w.bits.strb @[quasar_wrapper.scala 105:21] - io.ifu_brg.w.bits.data <= core.io.ifu_axi.w.bits.data @[quasar_wrapper.scala 105:21] - io.ifu_brg.w.valid <= core.io.ifu_axi.w.valid @[quasar_wrapper.scala 105:21] - core.io.ifu_axi.w.ready <= io.ifu_brg.w.ready @[quasar_wrapper.scala 105:21] - io.ifu_brg.aw.bits.qos <= core.io.ifu_axi.aw.bits.qos @[quasar_wrapper.scala 105:21] - io.ifu_brg.aw.bits.prot <= core.io.ifu_axi.aw.bits.prot @[quasar_wrapper.scala 105:21] - io.ifu_brg.aw.bits.cache <= core.io.ifu_axi.aw.bits.cache @[quasar_wrapper.scala 105:21] - io.ifu_brg.aw.bits.lock <= core.io.ifu_axi.aw.bits.lock @[quasar_wrapper.scala 105:21] - io.ifu_brg.aw.bits.burst <= core.io.ifu_axi.aw.bits.burst @[quasar_wrapper.scala 105:21] - io.ifu_brg.aw.bits.size <= core.io.ifu_axi.aw.bits.size @[quasar_wrapper.scala 105:21] - io.ifu_brg.aw.bits.len <= core.io.ifu_axi.aw.bits.len @[quasar_wrapper.scala 105:21] - io.ifu_brg.aw.bits.region <= core.io.ifu_axi.aw.bits.region @[quasar_wrapper.scala 105:21] - io.ifu_brg.aw.bits.addr <= core.io.ifu_axi.aw.bits.addr @[quasar_wrapper.scala 105:21] - io.ifu_brg.aw.bits.id <= core.io.ifu_axi.aw.bits.id @[quasar_wrapper.scala 105:21] - io.ifu_brg.aw.valid <= core.io.ifu_axi.aw.valid @[quasar_wrapper.scala 105:21] - core.io.ifu_axi.aw.ready <= io.ifu_brg.aw.ready @[quasar_wrapper.scala 105:21] - core.io.sb_axi.r.bits.last <= io.sb_brg.r.bits.last @[quasar_wrapper.scala 106:21] - core.io.sb_axi.r.bits.resp <= io.sb_brg.r.bits.resp @[quasar_wrapper.scala 106:21] - core.io.sb_axi.r.bits.data <= io.sb_brg.r.bits.data @[quasar_wrapper.scala 106:21] - core.io.sb_axi.r.bits.id <= io.sb_brg.r.bits.id @[quasar_wrapper.scala 106:21] - core.io.sb_axi.r.valid <= io.sb_brg.r.valid @[quasar_wrapper.scala 106:21] - io.sb_brg.r.ready <= core.io.sb_axi.r.ready @[quasar_wrapper.scala 106:21] - io.sb_brg.ar.bits.qos <= core.io.sb_axi.ar.bits.qos @[quasar_wrapper.scala 106:21] - io.sb_brg.ar.bits.prot <= core.io.sb_axi.ar.bits.prot @[quasar_wrapper.scala 106:21] - io.sb_brg.ar.bits.cache <= core.io.sb_axi.ar.bits.cache @[quasar_wrapper.scala 106:21] - io.sb_brg.ar.bits.lock <= core.io.sb_axi.ar.bits.lock @[quasar_wrapper.scala 106:21] - io.sb_brg.ar.bits.burst <= core.io.sb_axi.ar.bits.burst @[quasar_wrapper.scala 106:21] - io.sb_brg.ar.bits.size <= core.io.sb_axi.ar.bits.size @[quasar_wrapper.scala 106:21] - io.sb_brg.ar.bits.len <= core.io.sb_axi.ar.bits.len @[quasar_wrapper.scala 106:21] - io.sb_brg.ar.bits.region <= core.io.sb_axi.ar.bits.region @[quasar_wrapper.scala 106:21] - io.sb_brg.ar.bits.addr <= core.io.sb_axi.ar.bits.addr @[quasar_wrapper.scala 106:21] - io.sb_brg.ar.bits.id <= core.io.sb_axi.ar.bits.id @[quasar_wrapper.scala 106:21] - io.sb_brg.ar.valid <= core.io.sb_axi.ar.valid @[quasar_wrapper.scala 106:21] - core.io.sb_axi.ar.ready <= io.sb_brg.ar.ready @[quasar_wrapper.scala 106:21] - core.io.sb_axi.b.bits.id <= io.sb_brg.b.bits.id @[quasar_wrapper.scala 106:21] - core.io.sb_axi.b.bits.resp <= io.sb_brg.b.bits.resp @[quasar_wrapper.scala 106:21] - core.io.sb_axi.b.valid <= io.sb_brg.b.valid @[quasar_wrapper.scala 106:21] - io.sb_brg.b.ready <= core.io.sb_axi.b.ready @[quasar_wrapper.scala 106:21] - io.sb_brg.w.bits.last <= core.io.sb_axi.w.bits.last @[quasar_wrapper.scala 106:21] - io.sb_brg.w.bits.strb <= core.io.sb_axi.w.bits.strb @[quasar_wrapper.scala 106:21] - io.sb_brg.w.bits.data <= core.io.sb_axi.w.bits.data @[quasar_wrapper.scala 106:21] - io.sb_brg.w.valid <= core.io.sb_axi.w.valid @[quasar_wrapper.scala 106:21] - core.io.sb_axi.w.ready <= io.sb_brg.w.ready @[quasar_wrapper.scala 106:21] - io.sb_brg.aw.bits.qos <= core.io.sb_axi.aw.bits.qos @[quasar_wrapper.scala 106:21] - io.sb_brg.aw.bits.prot <= core.io.sb_axi.aw.bits.prot @[quasar_wrapper.scala 106:21] - io.sb_brg.aw.bits.cache <= core.io.sb_axi.aw.bits.cache @[quasar_wrapper.scala 106:21] - io.sb_brg.aw.bits.lock <= core.io.sb_axi.aw.bits.lock @[quasar_wrapper.scala 106:21] - io.sb_brg.aw.bits.burst <= core.io.sb_axi.aw.bits.burst @[quasar_wrapper.scala 106:21] - io.sb_brg.aw.bits.size <= core.io.sb_axi.aw.bits.size @[quasar_wrapper.scala 106:21] - io.sb_brg.aw.bits.len <= core.io.sb_axi.aw.bits.len @[quasar_wrapper.scala 106:21] - io.sb_brg.aw.bits.region <= core.io.sb_axi.aw.bits.region @[quasar_wrapper.scala 106:21] - io.sb_brg.aw.bits.addr <= core.io.sb_axi.aw.bits.addr @[quasar_wrapper.scala 106:21] - io.sb_brg.aw.bits.id <= core.io.sb_axi.aw.bits.id @[quasar_wrapper.scala 106:21] - io.sb_brg.aw.valid <= core.io.sb_axi.aw.valid @[quasar_wrapper.scala 106:21] - core.io.sb_axi.aw.ready <= io.sb_brg.aw.ready @[quasar_wrapper.scala 106:21] - io.dma_brg.r.bits.last <= core.io.dma_axi.r.bits.last @[quasar_wrapper.scala 107:21] - io.dma_brg.r.bits.resp <= core.io.dma_axi.r.bits.resp @[quasar_wrapper.scala 107:21] - io.dma_brg.r.bits.data <= core.io.dma_axi.r.bits.data @[quasar_wrapper.scala 107:21] - io.dma_brg.r.bits.id <= core.io.dma_axi.r.bits.id @[quasar_wrapper.scala 107:21] - io.dma_brg.r.valid <= core.io.dma_axi.r.valid @[quasar_wrapper.scala 107:21] - core.io.dma_axi.r.ready <= io.dma_brg.r.ready @[quasar_wrapper.scala 107:21] - core.io.dma_axi.ar.bits.qos <= io.dma_brg.ar.bits.qos @[quasar_wrapper.scala 107:21] - core.io.dma_axi.ar.bits.prot <= io.dma_brg.ar.bits.prot @[quasar_wrapper.scala 107:21] - core.io.dma_axi.ar.bits.cache <= io.dma_brg.ar.bits.cache @[quasar_wrapper.scala 107:21] - core.io.dma_axi.ar.bits.lock <= io.dma_brg.ar.bits.lock @[quasar_wrapper.scala 107:21] - core.io.dma_axi.ar.bits.burst <= io.dma_brg.ar.bits.burst @[quasar_wrapper.scala 107:21] - core.io.dma_axi.ar.bits.size <= io.dma_brg.ar.bits.size @[quasar_wrapper.scala 107:21] - core.io.dma_axi.ar.bits.len <= io.dma_brg.ar.bits.len @[quasar_wrapper.scala 107:21] - core.io.dma_axi.ar.bits.region <= io.dma_brg.ar.bits.region @[quasar_wrapper.scala 107:21] - core.io.dma_axi.ar.bits.addr <= io.dma_brg.ar.bits.addr @[quasar_wrapper.scala 107:21] - core.io.dma_axi.ar.bits.id <= io.dma_brg.ar.bits.id @[quasar_wrapper.scala 107:21] - core.io.dma_axi.ar.valid <= io.dma_brg.ar.valid @[quasar_wrapper.scala 107:21] - io.dma_brg.ar.ready <= core.io.dma_axi.ar.ready @[quasar_wrapper.scala 107:21] - io.dma_brg.b.bits.id <= core.io.dma_axi.b.bits.id @[quasar_wrapper.scala 107:21] - io.dma_brg.b.bits.resp <= core.io.dma_axi.b.bits.resp @[quasar_wrapper.scala 107:21] - io.dma_brg.b.valid <= core.io.dma_axi.b.valid @[quasar_wrapper.scala 107:21] - core.io.dma_axi.b.ready <= io.dma_brg.b.ready @[quasar_wrapper.scala 107:21] - core.io.dma_axi.w.bits.last <= io.dma_brg.w.bits.last @[quasar_wrapper.scala 107:21] - core.io.dma_axi.w.bits.strb <= io.dma_brg.w.bits.strb @[quasar_wrapper.scala 107:21] - core.io.dma_axi.w.bits.data <= io.dma_brg.w.bits.data @[quasar_wrapper.scala 107:21] - core.io.dma_axi.w.valid <= io.dma_brg.w.valid @[quasar_wrapper.scala 107:21] - io.dma_brg.w.ready <= core.io.dma_axi.w.ready @[quasar_wrapper.scala 107:21] - core.io.dma_axi.aw.bits.qos <= io.dma_brg.aw.bits.qos @[quasar_wrapper.scala 107:21] - core.io.dma_axi.aw.bits.prot <= io.dma_brg.aw.bits.prot @[quasar_wrapper.scala 107:21] - core.io.dma_axi.aw.bits.cache <= io.dma_brg.aw.bits.cache @[quasar_wrapper.scala 107:21] - core.io.dma_axi.aw.bits.lock <= io.dma_brg.aw.bits.lock @[quasar_wrapper.scala 107:21] - core.io.dma_axi.aw.bits.burst <= io.dma_brg.aw.bits.burst @[quasar_wrapper.scala 107:21] - core.io.dma_axi.aw.bits.size <= io.dma_brg.aw.bits.size @[quasar_wrapper.scala 107:21] - core.io.dma_axi.aw.bits.len <= io.dma_brg.aw.bits.len @[quasar_wrapper.scala 107:21] - core.io.dma_axi.aw.bits.region <= io.dma_brg.aw.bits.region @[quasar_wrapper.scala 107:21] - core.io.dma_axi.aw.bits.addr <= io.dma_brg.aw.bits.addr @[quasar_wrapper.scala 107:21] - core.io.dma_axi.aw.bits.id <= io.dma_brg.aw.bits.id @[quasar_wrapper.scala 107:21] - core.io.dma_axi.aw.valid <= io.dma_brg.aw.valid @[quasar_wrapper.scala 107:21] - io.dma_brg.aw.ready <= core.io.dma_axi.aw.ready @[quasar_wrapper.scala 107:21] + io.ifu_brg.out.hwdata <= core.io.ifu_ahb.out.hwdata @[quasar_wrapper.scala 110:21] + io.ifu_brg.out.hwrite <= core.io.ifu_ahb.out.hwrite @[quasar_wrapper.scala 110:21] + io.ifu_brg.out.htrans <= core.io.ifu_ahb.out.htrans @[quasar_wrapper.scala 110:21] + io.ifu_brg.out.hsize <= core.io.ifu_ahb.out.hsize @[quasar_wrapper.scala 110:21] + io.ifu_brg.out.hprot <= core.io.ifu_ahb.out.hprot @[quasar_wrapper.scala 110:21] + io.ifu_brg.out.hmastlock <= core.io.ifu_ahb.out.hmastlock @[quasar_wrapper.scala 110:21] + io.ifu_brg.out.hburst <= core.io.ifu_ahb.out.hburst @[quasar_wrapper.scala 110:21] + io.ifu_brg.out.haddr <= core.io.ifu_ahb.out.haddr @[quasar_wrapper.scala 110:21] + core.io.ifu_ahb.in.hresp <= io.ifu_brg.in.hresp @[quasar_wrapper.scala 110:21] + core.io.ifu_ahb.in.hready <= io.ifu_brg.in.hready @[quasar_wrapper.scala 110:21] + core.io.ifu_ahb.in.hrdata <= io.ifu_brg.in.hrdata @[quasar_wrapper.scala 110:21] + io.lsu_brg.out.hwdata <= core.io.lsu_ahb.out.hwdata @[quasar_wrapper.scala 111:21] + io.lsu_brg.out.hwrite <= core.io.lsu_ahb.out.hwrite @[quasar_wrapper.scala 111:21] + io.lsu_brg.out.htrans <= core.io.lsu_ahb.out.htrans @[quasar_wrapper.scala 111:21] + io.lsu_brg.out.hsize <= core.io.lsu_ahb.out.hsize @[quasar_wrapper.scala 111:21] + io.lsu_brg.out.hprot <= core.io.lsu_ahb.out.hprot @[quasar_wrapper.scala 111:21] + io.lsu_brg.out.hmastlock <= core.io.lsu_ahb.out.hmastlock @[quasar_wrapper.scala 111:21] + io.lsu_brg.out.hburst <= core.io.lsu_ahb.out.hburst @[quasar_wrapper.scala 111:21] + io.lsu_brg.out.haddr <= core.io.lsu_ahb.out.haddr @[quasar_wrapper.scala 111:21] + core.io.lsu_ahb.in.hresp <= io.lsu_brg.in.hresp @[quasar_wrapper.scala 111:21] + core.io.lsu_ahb.in.hready <= io.lsu_brg.in.hready @[quasar_wrapper.scala 111:21] + core.io.lsu_ahb.in.hrdata <= io.lsu_brg.in.hrdata @[quasar_wrapper.scala 111:21] + io.sb_brg.out.hwdata <= core.io.sb_ahb.out.hwdata @[quasar_wrapper.scala 112:20] + io.sb_brg.out.hwrite <= core.io.sb_ahb.out.hwrite @[quasar_wrapper.scala 112:20] + io.sb_brg.out.htrans <= core.io.sb_ahb.out.htrans @[quasar_wrapper.scala 112:20] + io.sb_brg.out.hsize <= core.io.sb_ahb.out.hsize @[quasar_wrapper.scala 112:20] + io.sb_brg.out.hprot <= core.io.sb_ahb.out.hprot @[quasar_wrapper.scala 112:20] + io.sb_brg.out.hmastlock <= core.io.sb_ahb.out.hmastlock @[quasar_wrapper.scala 112:20] + io.sb_brg.out.hburst <= core.io.sb_ahb.out.hburst @[quasar_wrapper.scala 112:20] + io.sb_brg.out.haddr <= core.io.sb_ahb.out.haddr @[quasar_wrapper.scala 112:20] + core.io.sb_ahb.in.hresp <= io.sb_brg.in.hresp @[quasar_wrapper.scala 112:20] + core.io.sb_ahb.in.hready <= io.sb_brg.in.hready @[quasar_wrapper.scala 112:20] + core.io.sb_ahb.in.hrdata <= io.sb_brg.in.hrdata @[quasar_wrapper.scala 112:20] + core.io.dma_ahb.hreadyin <= io.dma_brg.hreadyin @[quasar_wrapper.scala 113:21] + core.io.dma_ahb.hsel <= io.dma_brg.hsel @[quasar_wrapper.scala 113:21] + core.io.dma_ahb.sig.out.hwdata <= io.dma_brg.sig.out.hwdata @[quasar_wrapper.scala 113:21] + core.io.dma_ahb.sig.out.hwrite <= io.dma_brg.sig.out.hwrite @[quasar_wrapper.scala 113:21] + core.io.dma_ahb.sig.out.htrans <= io.dma_brg.sig.out.htrans @[quasar_wrapper.scala 113:21] + core.io.dma_ahb.sig.out.hsize <= io.dma_brg.sig.out.hsize @[quasar_wrapper.scala 113:21] + core.io.dma_ahb.sig.out.hprot <= io.dma_brg.sig.out.hprot @[quasar_wrapper.scala 113:21] + core.io.dma_ahb.sig.out.hmastlock <= io.dma_brg.sig.out.hmastlock @[quasar_wrapper.scala 113:21] + core.io.dma_ahb.sig.out.hburst <= io.dma_brg.sig.out.hburst @[quasar_wrapper.scala 113:21] + core.io.dma_ahb.sig.out.haddr <= io.dma_brg.sig.out.haddr @[quasar_wrapper.scala 113:21] + io.dma_brg.sig.in.hresp <= core.io.dma_ahb.sig.in.hresp @[quasar_wrapper.scala 113:21] + io.dma_brg.sig.in.hready <= core.io.dma_ahb.sig.in.hready @[quasar_wrapper.scala 113:21] + io.dma_brg.sig.in.hrdata <= core.io.dma_ahb.sig.in.hrdata @[quasar_wrapper.scala 113:21] + wire _T : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar_wrapper.scala 115:36] + _T.r.bits.last <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] + _T.r.bits.resp <= UInt<2>("h00") @[quasar_wrapper.scala 115:36] + _T.r.bits.data <= UInt<64>("h00") @[quasar_wrapper.scala 115:36] + _T.r.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 115:36] + _T.r.valid <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] + _T.r.ready <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] + _T.ar.bits.qos <= UInt<4>("h00") @[quasar_wrapper.scala 115:36] + _T.ar.bits.prot <= UInt<3>("h00") @[quasar_wrapper.scala 115:36] + _T.ar.bits.cache <= UInt<4>("h00") @[quasar_wrapper.scala 115:36] + _T.ar.bits.lock <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] + _T.ar.bits.burst <= UInt<2>("h00") @[quasar_wrapper.scala 115:36] + _T.ar.bits.size <= UInt<3>("h00") @[quasar_wrapper.scala 115:36] + _T.ar.bits.len <= UInt<8>("h00") @[quasar_wrapper.scala 115:36] + _T.ar.bits.region <= UInt<4>("h00") @[quasar_wrapper.scala 115:36] + _T.ar.bits.addr <= UInt<32>("h00") @[quasar_wrapper.scala 115:36] + _T.ar.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 115:36] + _T.ar.valid <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] + _T.ar.ready <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] + _T.b.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 115:36] + _T.b.bits.resp <= UInt<2>("h00") @[quasar_wrapper.scala 115:36] + _T.b.valid <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] + _T.b.ready <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] + _T.w.bits.last <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] + _T.w.bits.strb <= UInt<8>("h00") @[quasar_wrapper.scala 115:36] + _T.w.bits.data <= UInt<64>("h00") @[quasar_wrapper.scala 115:36] + _T.w.valid <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] + _T.w.ready <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] + _T.aw.bits.qos <= UInt<4>("h00") @[quasar_wrapper.scala 115:36] + _T.aw.bits.prot <= UInt<3>("h00") @[quasar_wrapper.scala 115:36] + _T.aw.bits.cache <= UInt<4>("h00") @[quasar_wrapper.scala 115:36] + _T.aw.bits.lock <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] + _T.aw.bits.burst <= UInt<2>("h00") @[quasar_wrapper.scala 115:36] + _T.aw.bits.size <= UInt<3>("h00") @[quasar_wrapper.scala 115:36] + _T.aw.bits.len <= UInt<8>("h00") @[quasar_wrapper.scala 115:36] + _T.aw.bits.region <= UInt<4>("h00") @[quasar_wrapper.scala 115:36] + _T.aw.bits.addr <= UInt<32>("h00") @[quasar_wrapper.scala 115:36] + _T.aw.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 115:36] + _T.aw.valid <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] + _T.aw.ready <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] + core.io.lsu_axi.r.bits.last <= _T.r.bits.last @[quasar_wrapper.scala 115:21] + core.io.lsu_axi.r.bits.resp <= _T.r.bits.resp @[quasar_wrapper.scala 115:21] + core.io.lsu_axi.r.bits.data <= _T.r.bits.data @[quasar_wrapper.scala 115:21] + core.io.lsu_axi.r.bits.id <= _T.r.bits.id @[quasar_wrapper.scala 115:21] + core.io.lsu_axi.r.valid <= _T.r.valid @[quasar_wrapper.scala 115:21] + _T.r.ready <= core.io.lsu_axi.r.ready @[quasar_wrapper.scala 115:21] + _T.ar.bits.qos <= core.io.lsu_axi.ar.bits.qos @[quasar_wrapper.scala 115:21] + _T.ar.bits.prot <= core.io.lsu_axi.ar.bits.prot @[quasar_wrapper.scala 115:21] + _T.ar.bits.cache <= core.io.lsu_axi.ar.bits.cache @[quasar_wrapper.scala 115:21] + _T.ar.bits.lock <= core.io.lsu_axi.ar.bits.lock @[quasar_wrapper.scala 115:21] + _T.ar.bits.burst <= core.io.lsu_axi.ar.bits.burst @[quasar_wrapper.scala 115:21] + _T.ar.bits.size <= core.io.lsu_axi.ar.bits.size @[quasar_wrapper.scala 115:21] + _T.ar.bits.len <= core.io.lsu_axi.ar.bits.len @[quasar_wrapper.scala 115:21] + _T.ar.bits.region <= core.io.lsu_axi.ar.bits.region @[quasar_wrapper.scala 115:21] + _T.ar.bits.addr <= core.io.lsu_axi.ar.bits.addr @[quasar_wrapper.scala 115:21] + _T.ar.bits.id <= core.io.lsu_axi.ar.bits.id @[quasar_wrapper.scala 115:21] + _T.ar.valid <= core.io.lsu_axi.ar.valid @[quasar_wrapper.scala 115:21] + core.io.lsu_axi.ar.ready <= _T.ar.ready @[quasar_wrapper.scala 115:21] + core.io.lsu_axi.b.bits.id <= _T.b.bits.id @[quasar_wrapper.scala 115:21] + core.io.lsu_axi.b.bits.resp <= _T.b.bits.resp @[quasar_wrapper.scala 115:21] + core.io.lsu_axi.b.valid <= _T.b.valid @[quasar_wrapper.scala 115:21] + _T.b.ready <= core.io.lsu_axi.b.ready @[quasar_wrapper.scala 115:21] + _T.w.bits.last <= core.io.lsu_axi.w.bits.last @[quasar_wrapper.scala 115:21] + _T.w.bits.strb <= core.io.lsu_axi.w.bits.strb @[quasar_wrapper.scala 115:21] + _T.w.bits.data <= core.io.lsu_axi.w.bits.data @[quasar_wrapper.scala 115:21] + _T.w.valid <= core.io.lsu_axi.w.valid @[quasar_wrapper.scala 115:21] + core.io.lsu_axi.w.ready <= _T.w.ready @[quasar_wrapper.scala 115:21] + _T.aw.bits.qos <= core.io.lsu_axi.aw.bits.qos @[quasar_wrapper.scala 115:21] + _T.aw.bits.prot <= core.io.lsu_axi.aw.bits.prot @[quasar_wrapper.scala 115:21] + _T.aw.bits.cache <= core.io.lsu_axi.aw.bits.cache @[quasar_wrapper.scala 115:21] + _T.aw.bits.lock <= core.io.lsu_axi.aw.bits.lock @[quasar_wrapper.scala 115:21] + _T.aw.bits.burst <= core.io.lsu_axi.aw.bits.burst @[quasar_wrapper.scala 115:21] + _T.aw.bits.size <= core.io.lsu_axi.aw.bits.size @[quasar_wrapper.scala 115:21] + _T.aw.bits.len <= core.io.lsu_axi.aw.bits.len @[quasar_wrapper.scala 115:21] + _T.aw.bits.region <= core.io.lsu_axi.aw.bits.region @[quasar_wrapper.scala 115:21] + _T.aw.bits.addr <= core.io.lsu_axi.aw.bits.addr @[quasar_wrapper.scala 115:21] + _T.aw.bits.id <= core.io.lsu_axi.aw.bits.id @[quasar_wrapper.scala 115:21] + _T.aw.valid <= core.io.lsu_axi.aw.valid @[quasar_wrapper.scala 115:21] + core.io.lsu_axi.aw.ready <= _T.aw.ready @[quasar_wrapper.scala 115:21] + wire _T_1 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar_wrapper.scala 116:36] + _T_1.r.bits.last <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] + _T_1.r.bits.resp <= UInt<2>("h00") @[quasar_wrapper.scala 116:36] + _T_1.r.bits.data <= UInt<64>("h00") @[quasar_wrapper.scala 116:36] + _T_1.r.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 116:36] + _T_1.r.valid <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] + _T_1.r.ready <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] + _T_1.ar.bits.qos <= UInt<4>("h00") @[quasar_wrapper.scala 116:36] + _T_1.ar.bits.prot <= UInt<3>("h00") @[quasar_wrapper.scala 116:36] + _T_1.ar.bits.cache <= UInt<4>("h00") @[quasar_wrapper.scala 116:36] + _T_1.ar.bits.lock <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] + _T_1.ar.bits.burst <= UInt<2>("h00") @[quasar_wrapper.scala 116:36] + _T_1.ar.bits.size <= UInt<3>("h00") @[quasar_wrapper.scala 116:36] + _T_1.ar.bits.len <= UInt<8>("h00") @[quasar_wrapper.scala 116:36] + _T_1.ar.bits.region <= UInt<4>("h00") @[quasar_wrapper.scala 116:36] + _T_1.ar.bits.addr <= UInt<32>("h00") @[quasar_wrapper.scala 116:36] + _T_1.ar.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 116:36] + _T_1.ar.valid <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] + _T_1.ar.ready <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] + _T_1.b.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 116:36] + _T_1.b.bits.resp <= UInt<2>("h00") @[quasar_wrapper.scala 116:36] + _T_1.b.valid <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] + _T_1.b.ready <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] + _T_1.w.bits.last <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] + _T_1.w.bits.strb <= UInt<8>("h00") @[quasar_wrapper.scala 116:36] + _T_1.w.bits.data <= UInt<64>("h00") @[quasar_wrapper.scala 116:36] + _T_1.w.valid <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] + _T_1.w.ready <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] + _T_1.aw.bits.qos <= UInt<4>("h00") @[quasar_wrapper.scala 116:36] + _T_1.aw.bits.prot <= UInt<3>("h00") @[quasar_wrapper.scala 116:36] + _T_1.aw.bits.cache <= UInt<4>("h00") @[quasar_wrapper.scala 116:36] + _T_1.aw.bits.lock <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] + _T_1.aw.bits.burst <= UInt<2>("h00") @[quasar_wrapper.scala 116:36] + _T_1.aw.bits.size <= UInt<3>("h00") @[quasar_wrapper.scala 116:36] + _T_1.aw.bits.len <= UInt<8>("h00") @[quasar_wrapper.scala 116:36] + _T_1.aw.bits.region <= UInt<4>("h00") @[quasar_wrapper.scala 116:36] + _T_1.aw.bits.addr <= UInt<32>("h00") @[quasar_wrapper.scala 116:36] + _T_1.aw.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 116:36] + _T_1.aw.valid <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] + _T_1.aw.ready <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] + core.io.ifu_axi.r.bits.last <= _T_1.r.bits.last @[quasar_wrapper.scala 116:21] + core.io.ifu_axi.r.bits.resp <= _T_1.r.bits.resp @[quasar_wrapper.scala 116:21] + core.io.ifu_axi.r.bits.data <= _T_1.r.bits.data @[quasar_wrapper.scala 116:21] + core.io.ifu_axi.r.bits.id <= _T_1.r.bits.id @[quasar_wrapper.scala 116:21] + core.io.ifu_axi.r.valid <= _T_1.r.valid @[quasar_wrapper.scala 116:21] + _T_1.r.ready <= core.io.ifu_axi.r.ready @[quasar_wrapper.scala 116:21] + _T_1.ar.bits.qos <= core.io.ifu_axi.ar.bits.qos @[quasar_wrapper.scala 116:21] + _T_1.ar.bits.prot <= core.io.ifu_axi.ar.bits.prot @[quasar_wrapper.scala 116:21] + _T_1.ar.bits.cache <= core.io.ifu_axi.ar.bits.cache @[quasar_wrapper.scala 116:21] + _T_1.ar.bits.lock <= core.io.ifu_axi.ar.bits.lock @[quasar_wrapper.scala 116:21] + _T_1.ar.bits.burst <= core.io.ifu_axi.ar.bits.burst @[quasar_wrapper.scala 116:21] + _T_1.ar.bits.size <= core.io.ifu_axi.ar.bits.size @[quasar_wrapper.scala 116:21] + _T_1.ar.bits.len <= core.io.ifu_axi.ar.bits.len @[quasar_wrapper.scala 116:21] + _T_1.ar.bits.region <= core.io.ifu_axi.ar.bits.region @[quasar_wrapper.scala 116:21] + _T_1.ar.bits.addr <= core.io.ifu_axi.ar.bits.addr @[quasar_wrapper.scala 116:21] + _T_1.ar.bits.id <= core.io.ifu_axi.ar.bits.id @[quasar_wrapper.scala 116:21] + _T_1.ar.valid <= core.io.ifu_axi.ar.valid @[quasar_wrapper.scala 116:21] + core.io.ifu_axi.ar.ready <= _T_1.ar.ready @[quasar_wrapper.scala 116:21] + core.io.ifu_axi.b.bits.id <= _T_1.b.bits.id @[quasar_wrapper.scala 116:21] + core.io.ifu_axi.b.bits.resp <= _T_1.b.bits.resp @[quasar_wrapper.scala 116:21] + core.io.ifu_axi.b.valid <= _T_1.b.valid @[quasar_wrapper.scala 116:21] + _T_1.b.ready <= core.io.ifu_axi.b.ready @[quasar_wrapper.scala 116:21] + _T_1.w.bits.last <= core.io.ifu_axi.w.bits.last @[quasar_wrapper.scala 116:21] + _T_1.w.bits.strb <= core.io.ifu_axi.w.bits.strb @[quasar_wrapper.scala 116:21] + _T_1.w.bits.data <= core.io.ifu_axi.w.bits.data @[quasar_wrapper.scala 116:21] + _T_1.w.valid <= core.io.ifu_axi.w.valid @[quasar_wrapper.scala 116:21] + core.io.ifu_axi.w.ready <= _T_1.w.ready @[quasar_wrapper.scala 116:21] + _T_1.aw.bits.qos <= core.io.ifu_axi.aw.bits.qos @[quasar_wrapper.scala 116:21] + _T_1.aw.bits.prot <= core.io.ifu_axi.aw.bits.prot @[quasar_wrapper.scala 116:21] + _T_1.aw.bits.cache <= core.io.ifu_axi.aw.bits.cache @[quasar_wrapper.scala 116:21] + _T_1.aw.bits.lock <= core.io.ifu_axi.aw.bits.lock @[quasar_wrapper.scala 116:21] + _T_1.aw.bits.burst <= core.io.ifu_axi.aw.bits.burst @[quasar_wrapper.scala 116:21] + _T_1.aw.bits.size <= core.io.ifu_axi.aw.bits.size @[quasar_wrapper.scala 116:21] + _T_1.aw.bits.len <= core.io.ifu_axi.aw.bits.len @[quasar_wrapper.scala 116:21] + _T_1.aw.bits.region <= core.io.ifu_axi.aw.bits.region @[quasar_wrapper.scala 116:21] + _T_1.aw.bits.addr <= core.io.ifu_axi.aw.bits.addr @[quasar_wrapper.scala 116:21] + _T_1.aw.bits.id <= core.io.ifu_axi.aw.bits.id @[quasar_wrapper.scala 116:21] + _T_1.aw.valid <= core.io.ifu_axi.aw.valid @[quasar_wrapper.scala 116:21] + core.io.ifu_axi.aw.ready <= _T_1.aw.ready @[quasar_wrapper.scala 116:21] + wire _T_2 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar_wrapper.scala 117:36] + _T_2.r.bits.last <= UInt<1>("h00") @[quasar_wrapper.scala 117:36] + _T_2.r.bits.resp <= UInt<2>("h00") @[quasar_wrapper.scala 117:36] + _T_2.r.bits.data <= UInt<64>("h00") @[quasar_wrapper.scala 117:36] + _T_2.r.bits.id <= UInt<1>("h00") @[quasar_wrapper.scala 117:36] + _T_2.r.valid <= UInt<1>("h00") @[quasar_wrapper.scala 117:36] + _T_2.r.ready <= UInt<1>("h00") @[quasar_wrapper.scala 117:36] + _T_2.ar.bits.qos <= UInt<4>("h00") @[quasar_wrapper.scala 117:36] + _T_2.ar.bits.prot <= UInt<3>("h00") @[quasar_wrapper.scala 117:36] + _T_2.ar.bits.cache <= UInt<4>("h00") @[quasar_wrapper.scala 117:36] + _T_2.ar.bits.lock <= UInt<1>("h00") @[quasar_wrapper.scala 117:36] + _T_2.ar.bits.burst <= UInt<2>("h00") @[quasar_wrapper.scala 117:36] + _T_2.ar.bits.size <= UInt<3>("h00") @[quasar_wrapper.scala 117:36] + _T_2.ar.bits.len <= UInt<8>("h00") @[quasar_wrapper.scala 117:36] + _T_2.ar.bits.region <= UInt<4>("h00") @[quasar_wrapper.scala 117:36] + _T_2.ar.bits.addr <= UInt<32>("h00") @[quasar_wrapper.scala 117:36] + _T_2.ar.bits.id <= UInt<1>("h00") @[quasar_wrapper.scala 117:36] + _T_2.ar.valid <= UInt<1>("h00") @[quasar_wrapper.scala 117:36] + _T_2.ar.ready <= UInt<1>("h00") @[quasar_wrapper.scala 117:36] + _T_2.b.bits.id <= UInt<1>("h00") @[quasar_wrapper.scala 117:36] + _T_2.b.bits.resp <= UInt<2>("h00") @[quasar_wrapper.scala 117:36] + _T_2.b.valid <= UInt<1>("h00") @[quasar_wrapper.scala 117:36] + _T_2.b.ready <= UInt<1>("h00") @[quasar_wrapper.scala 117:36] + _T_2.w.bits.last <= UInt<1>("h00") @[quasar_wrapper.scala 117:36] + _T_2.w.bits.strb <= UInt<8>("h00") @[quasar_wrapper.scala 117:36] + _T_2.w.bits.data <= UInt<64>("h00") @[quasar_wrapper.scala 117:36] + _T_2.w.valid <= UInt<1>("h00") @[quasar_wrapper.scala 117:36] + _T_2.w.ready <= UInt<1>("h00") @[quasar_wrapper.scala 117:36] + _T_2.aw.bits.qos <= UInt<4>("h00") @[quasar_wrapper.scala 117:36] + _T_2.aw.bits.prot <= UInt<3>("h00") @[quasar_wrapper.scala 117:36] + _T_2.aw.bits.cache <= UInt<4>("h00") @[quasar_wrapper.scala 117:36] + _T_2.aw.bits.lock <= UInt<1>("h00") @[quasar_wrapper.scala 117:36] + _T_2.aw.bits.burst <= UInt<2>("h00") @[quasar_wrapper.scala 117:36] + _T_2.aw.bits.size <= UInt<3>("h00") @[quasar_wrapper.scala 117:36] + _T_2.aw.bits.len <= UInt<8>("h00") @[quasar_wrapper.scala 117:36] + _T_2.aw.bits.region <= UInt<4>("h00") @[quasar_wrapper.scala 117:36] + _T_2.aw.bits.addr <= UInt<32>("h00") @[quasar_wrapper.scala 117:36] + _T_2.aw.bits.id <= UInt<1>("h00") @[quasar_wrapper.scala 117:36] + _T_2.aw.valid <= UInt<1>("h00") @[quasar_wrapper.scala 117:36] + _T_2.aw.ready <= UInt<1>("h00") @[quasar_wrapper.scala 117:36] + core.io.sb_axi.r.bits.last <= _T_2.r.bits.last @[quasar_wrapper.scala 117:21] + core.io.sb_axi.r.bits.resp <= _T_2.r.bits.resp @[quasar_wrapper.scala 117:21] + core.io.sb_axi.r.bits.data <= _T_2.r.bits.data @[quasar_wrapper.scala 117:21] + core.io.sb_axi.r.bits.id <= _T_2.r.bits.id @[quasar_wrapper.scala 117:21] + core.io.sb_axi.r.valid <= _T_2.r.valid @[quasar_wrapper.scala 117:21] + _T_2.r.ready <= core.io.sb_axi.r.ready @[quasar_wrapper.scala 117:21] + _T_2.ar.bits.qos <= core.io.sb_axi.ar.bits.qos @[quasar_wrapper.scala 117:21] + _T_2.ar.bits.prot <= core.io.sb_axi.ar.bits.prot @[quasar_wrapper.scala 117:21] + _T_2.ar.bits.cache <= core.io.sb_axi.ar.bits.cache @[quasar_wrapper.scala 117:21] + _T_2.ar.bits.lock <= core.io.sb_axi.ar.bits.lock @[quasar_wrapper.scala 117:21] + _T_2.ar.bits.burst <= core.io.sb_axi.ar.bits.burst @[quasar_wrapper.scala 117:21] + _T_2.ar.bits.size <= core.io.sb_axi.ar.bits.size @[quasar_wrapper.scala 117:21] + _T_2.ar.bits.len <= core.io.sb_axi.ar.bits.len @[quasar_wrapper.scala 117:21] + _T_2.ar.bits.region <= core.io.sb_axi.ar.bits.region @[quasar_wrapper.scala 117:21] + _T_2.ar.bits.addr <= core.io.sb_axi.ar.bits.addr @[quasar_wrapper.scala 117:21] + _T_2.ar.bits.id <= core.io.sb_axi.ar.bits.id @[quasar_wrapper.scala 117:21] + _T_2.ar.valid <= core.io.sb_axi.ar.valid @[quasar_wrapper.scala 117:21] + core.io.sb_axi.ar.ready <= _T_2.ar.ready @[quasar_wrapper.scala 117:21] + core.io.sb_axi.b.bits.id <= _T_2.b.bits.id @[quasar_wrapper.scala 117:21] + core.io.sb_axi.b.bits.resp <= _T_2.b.bits.resp @[quasar_wrapper.scala 117:21] + core.io.sb_axi.b.valid <= _T_2.b.valid @[quasar_wrapper.scala 117:21] + _T_2.b.ready <= core.io.sb_axi.b.ready @[quasar_wrapper.scala 117:21] + _T_2.w.bits.last <= core.io.sb_axi.w.bits.last @[quasar_wrapper.scala 117:21] + _T_2.w.bits.strb <= core.io.sb_axi.w.bits.strb @[quasar_wrapper.scala 117:21] + _T_2.w.bits.data <= core.io.sb_axi.w.bits.data @[quasar_wrapper.scala 117:21] + _T_2.w.valid <= core.io.sb_axi.w.valid @[quasar_wrapper.scala 117:21] + core.io.sb_axi.w.ready <= _T_2.w.ready @[quasar_wrapper.scala 117:21] + _T_2.aw.bits.qos <= core.io.sb_axi.aw.bits.qos @[quasar_wrapper.scala 117:21] + _T_2.aw.bits.prot <= core.io.sb_axi.aw.bits.prot @[quasar_wrapper.scala 117:21] + _T_2.aw.bits.cache <= core.io.sb_axi.aw.bits.cache @[quasar_wrapper.scala 117:21] + _T_2.aw.bits.lock <= core.io.sb_axi.aw.bits.lock @[quasar_wrapper.scala 117:21] + _T_2.aw.bits.burst <= core.io.sb_axi.aw.bits.burst @[quasar_wrapper.scala 117:21] + _T_2.aw.bits.size <= core.io.sb_axi.aw.bits.size @[quasar_wrapper.scala 117:21] + _T_2.aw.bits.len <= core.io.sb_axi.aw.bits.len @[quasar_wrapper.scala 117:21] + _T_2.aw.bits.region <= core.io.sb_axi.aw.bits.region @[quasar_wrapper.scala 117:21] + _T_2.aw.bits.addr <= core.io.sb_axi.aw.bits.addr @[quasar_wrapper.scala 117:21] + _T_2.aw.bits.id <= core.io.sb_axi.aw.bits.id @[quasar_wrapper.scala 117:21] + _T_2.aw.valid <= core.io.sb_axi.aw.valid @[quasar_wrapper.scala 117:21] + core.io.sb_axi.aw.ready <= _T_2.aw.ready @[quasar_wrapper.scala 117:21] + wire _T_3 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar_wrapper.scala 118:36] + _T_3.r.bits.last <= UInt<1>("h00") @[quasar_wrapper.scala 118:36] + _T_3.r.bits.resp <= UInt<2>("h00") @[quasar_wrapper.scala 118:36] + _T_3.r.bits.data <= UInt<64>("h00") @[quasar_wrapper.scala 118:36] + _T_3.r.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 118:36] + _T_3.r.valid <= UInt<1>("h00") @[quasar_wrapper.scala 118:36] + _T_3.r.ready <= UInt<1>("h00") @[quasar_wrapper.scala 118:36] + _T_3.ar.bits.qos <= UInt<4>("h00") @[quasar_wrapper.scala 118:36] + _T_3.ar.bits.prot <= UInt<3>("h00") @[quasar_wrapper.scala 118:36] + _T_3.ar.bits.cache <= UInt<4>("h00") @[quasar_wrapper.scala 118:36] + _T_3.ar.bits.lock <= UInt<1>("h00") @[quasar_wrapper.scala 118:36] + _T_3.ar.bits.burst <= UInt<2>("h00") @[quasar_wrapper.scala 118:36] + _T_3.ar.bits.size <= UInt<3>("h00") @[quasar_wrapper.scala 118:36] + _T_3.ar.bits.len <= UInt<8>("h00") @[quasar_wrapper.scala 118:36] + _T_3.ar.bits.region <= UInt<4>("h00") @[quasar_wrapper.scala 118:36] + _T_3.ar.bits.addr <= UInt<32>("h00") @[quasar_wrapper.scala 118:36] + _T_3.ar.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 118:36] + _T_3.ar.valid <= UInt<1>("h00") @[quasar_wrapper.scala 118:36] + _T_3.ar.ready <= UInt<1>("h00") @[quasar_wrapper.scala 118:36] + _T_3.b.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 118:36] + _T_3.b.bits.resp <= UInt<2>("h00") @[quasar_wrapper.scala 118:36] + _T_3.b.valid <= UInt<1>("h00") @[quasar_wrapper.scala 118:36] + _T_3.b.ready <= UInt<1>("h00") @[quasar_wrapper.scala 118:36] + _T_3.w.bits.last <= UInt<1>("h00") @[quasar_wrapper.scala 118:36] + _T_3.w.bits.strb <= UInt<8>("h00") @[quasar_wrapper.scala 118:36] + _T_3.w.bits.data <= UInt<64>("h00") @[quasar_wrapper.scala 118:36] + _T_3.w.valid <= UInt<1>("h00") @[quasar_wrapper.scala 118:36] + _T_3.w.ready <= UInt<1>("h00") @[quasar_wrapper.scala 118:36] + _T_3.aw.bits.qos <= UInt<4>("h00") @[quasar_wrapper.scala 118:36] + _T_3.aw.bits.prot <= UInt<3>("h00") @[quasar_wrapper.scala 118:36] + _T_3.aw.bits.cache <= UInt<4>("h00") @[quasar_wrapper.scala 118:36] + _T_3.aw.bits.lock <= UInt<1>("h00") @[quasar_wrapper.scala 118:36] + _T_3.aw.bits.burst <= UInt<2>("h00") @[quasar_wrapper.scala 118:36] + _T_3.aw.bits.size <= UInt<3>("h00") @[quasar_wrapper.scala 118:36] + _T_3.aw.bits.len <= UInt<8>("h00") @[quasar_wrapper.scala 118:36] + _T_3.aw.bits.region <= UInt<4>("h00") @[quasar_wrapper.scala 118:36] + _T_3.aw.bits.addr <= UInt<32>("h00") @[quasar_wrapper.scala 118:36] + _T_3.aw.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 118:36] + _T_3.aw.valid <= UInt<1>("h00") @[quasar_wrapper.scala 118:36] + _T_3.aw.ready <= UInt<1>("h00") @[quasar_wrapper.scala 118:36] + _T_3.r.bits.last <= core.io.dma_axi.r.bits.last @[quasar_wrapper.scala 118:21] + _T_3.r.bits.resp <= core.io.dma_axi.r.bits.resp @[quasar_wrapper.scala 118:21] + _T_3.r.bits.data <= core.io.dma_axi.r.bits.data @[quasar_wrapper.scala 118:21] + _T_3.r.bits.id <= core.io.dma_axi.r.bits.id @[quasar_wrapper.scala 118:21] + _T_3.r.valid <= core.io.dma_axi.r.valid @[quasar_wrapper.scala 118:21] + core.io.dma_axi.r.ready <= _T_3.r.ready @[quasar_wrapper.scala 118:21] + core.io.dma_axi.ar.bits.qos <= _T_3.ar.bits.qos @[quasar_wrapper.scala 118:21] + core.io.dma_axi.ar.bits.prot <= _T_3.ar.bits.prot @[quasar_wrapper.scala 118:21] + core.io.dma_axi.ar.bits.cache <= _T_3.ar.bits.cache @[quasar_wrapper.scala 118:21] + core.io.dma_axi.ar.bits.lock <= _T_3.ar.bits.lock @[quasar_wrapper.scala 118:21] + core.io.dma_axi.ar.bits.burst <= _T_3.ar.bits.burst @[quasar_wrapper.scala 118:21] + core.io.dma_axi.ar.bits.size <= _T_3.ar.bits.size @[quasar_wrapper.scala 118:21] + core.io.dma_axi.ar.bits.len <= _T_3.ar.bits.len @[quasar_wrapper.scala 118:21] + core.io.dma_axi.ar.bits.region <= _T_3.ar.bits.region @[quasar_wrapper.scala 118:21] + core.io.dma_axi.ar.bits.addr <= _T_3.ar.bits.addr @[quasar_wrapper.scala 118:21] + core.io.dma_axi.ar.bits.id <= _T_3.ar.bits.id @[quasar_wrapper.scala 118:21] + core.io.dma_axi.ar.valid <= _T_3.ar.valid @[quasar_wrapper.scala 118:21] + _T_3.ar.ready <= core.io.dma_axi.ar.ready @[quasar_wrapper.scala 118:21] + _T_3.b.bits.id <= core.io.dma_axi.b.bits.id @[quasar_wrapper.scala 118:21] + _T_3.b.bits.resp <= core.io.dma_axi.b.bits.resp @[quasar_wrapper.scala 118:21] + _T_3.b.valid <= core.io.dma_axi.b.valid @[quasar_wrapper.scala 118:21] + core.io.dma_axi.b.ready <= _T_3.b.ready @[quasar_wrapper.scala 118:21] + core.io.dma_axi.w.bits.last <= _T_3.w.bits.last @[quasar_wrapper.scala 118:21] + core.io.dma_axi.w.bits.strb <= _T_3.w.bits.strb @[quasar_wrapper.scala 118:21] + core.io.dma_axi.w.bits.data <= _T_3.w.bits.data @[quasar_wrapper.scala 118:21] + core.io.dma_axi.w.valid <= _T_3.w.valid @[quasar_wrapper.scala 118:21] + _T_3.w.ready <= core.io.dma_axi.w.ready @[quasar_wrapper.scala 118:21] + core.io.dma_axi.aw.bits.qos <= _T_3.aw.bits.qos @[quasar_wrapper.scala 118:21] + core.io.dma_axi.aw.bits.prot <= _T_3.aw.bits.prot @[quasar_wrapper.scala 118:21] + core.io.dma_axi.aw.bits.cache <= _T_3.aw.bits.cache @[quasar_wrapper.scala 118:21] + core.io.dma_axi.aw.bits.lock <= _T_3.aw.bits.lock @[quasar_wrapper.scala 118:21] + core.io.dma_axi.aw.bits.burst <= _T_3.aw.bits.burst @[quasar_wrapper.scala 118:21] + core.io.dma_axi.aw.bits.size <= _T_3.aw.bits.size @[quasar_wrapper.scala 118:21] + core.io.dma_axi.aw.bits.len <= _T_3.aw.bits.len @[quasar_wrapper.scala 118:21] + core.io.dma_axi.aw.bits.region <= _T_3.aw.bits.region @[quasar_wrapper.scala 118:21] + core.io.dma_axi.aw.bits.addr <= _T_3.aw.bits.addr @[quasar_wrapper.scala 118:21] + core.io.dma_axi.aw.bits.id <= _T_3.aw.bits.id @[quasar_wrapper.scala 118:21] + core.io.dma_axi.aw.valid <= _T_3.aw.valid @[quasar_wrapper.scala 118:21] + _T_3.aw.ready <= core.io.dma_axi.aw.ready @[quasar_wrapper.scala 118:21] core.io.dbg_rst_l <= io.dbg_rst_l @[quasar_wrapper.scala 121:21] core.io.rst_vec <= io.rst_vec @[quasar_wrapper.scala 122:19] core.io.nmi_int <= io.nmi_int @[quasar_wrapper.scala 123:19] diff --git a/quasar_wrapper.v b/quasar_wrapper.v index 1b4055c2..6eb457d5 100644 --- a/quasar_wrapper.v +++ b/quasar_wrapper.v @@ -56,6 +56,7 @@ module ifu_mem_ctl( input io_ifu_axi_ar_ready, output io_ifu_axi_ar_valid, output [2:0] io_ifu_axi_ar_bits_id, + output [31:0] io_ifu_axi_ar_bits_addr, output io_ifu_axi_r_ready, input io_ifu_axi_r_valid, input [2:0] io_ifu_axi_r_bits_id, @@ -281,8 +282,8 @@ module ifu_mem_ctl( reg [31:0] _RAND_160; reg [31:0] _RAND_161; reg [31:0] _RAND_162; - reg [63:0] _RAND_163; - reg [31:0] _RAND_164; + reg [31:0] _RAND_163; + reg [63:0] _RAND_164; reg [31:0] _RAND_165; reg [31:0] _RAND_166; reg [31:0] _RAND_167; @@ -559,8 +560,8 @@ module ifu_mem_ctl( reg [31:0] _RAND_438; reg [31:0] _RAND_439; reg [31:0] _RAND_440; - reg [95:0] _RAND_441; - reg [31:0] _RAND_442; + reg [31:0] _RAND_441; + reg [95:0] _RAND_442; reg [31:0] _RAND_443; reg [31:0] _RAND_444; reg [31:0] _RAND_445; @@ -569,14 +570,14 @@ module ifu_mem_ctl( reg [31:0] _RAND_448; reg [31:0] _RAND_449; reg [31:0] _RAND_450; - reg [63:0] _RAND_451; - reg [31:0] _RAND_452; + reg [31:0] _RAND_451; + reg [63:0] _RAND_452; reg [31:0] _RAND_453; reg [31:0] _RAND_454; reg [31:0] _RAND_455; reg [31:0] _RAND_456; - reg [63:0] _RAND_457; - reg [31:0] _RAND_458; + reg [31:0] _RAND_457; + reg [63:0] _RAND_458; reg [31:0] _RAND_459; reg [31:0] _RAND_460; reg [31:0] _RAND_461; @@ -590,6 +591,7 @@ module ifu_mem_ctl( reg [31:0] _RAND_469; reg [31:0] _RAND_470; reg [31:0] _RAND_471; + reg [31:0] _RAND_472; `endif // RANDOMIZE_REG_INIT wire rvclkhdr_io_l1clk; // @[lib.scala 343:22] wire rvclkhdr_io_clk; // @[lib.scala 343:22] @@ -1915,6 +1917,7 @@ module ifu_mem_ctl( wire _T_299 = reset_all_tags | reset_ic_ff; // @[ifu_mem_ctl.scala 211:72] wire reset_ic_in = _T_298 & _T_299; // @[ifu_mem_ctl.scala 211:53] reg fetch_uncacheable_ff; // @[ifu_mem_ctl.scala 213:62] + reg [25:0] miss_addr; // @[ifu_mem_ctl.scala 222:48] wire _T_309 = io_ifu_bus_clk_en | ic_act_miss_f; // @[ifu_mem_ctl.scala 221:57] wire _T_315 = _T_2283 & flush_final_f; // @[ifu_mem_ctl.scala 226:87] wire _T_316 = ~_T_315; // @[ifu_mem_ctl.scala 226:55] @@ -3410,6 +3413,8 @@ module ifu_mem_ctl( wire _T_2603 = ~bus_cmd_sent; // @[ifu_mem_ctl.scala 474:61] wire _T_2604 = _T_2591 & _T_2603; // @[ifu_mem_ctl.scala 474:59] wire [2:0] _T_2608 = ifu_bus_cmd_valid ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_2610 = {miss_addr,bus_rd_addr_count,3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2612 = ifu_bus_cmd_valid ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] reg ifu_bus_arready_unq_ff; // @[ifu_mem_ctl.scala 509:57] reg ifu_bus_arvalid_ff; // @[ifu_mem_ctl.scala 511:53] wire ifu_bus_arready_ff = ifu_bus_arready_unq_ff & bus_ifu_bus_clk_en_ff; // @[ifu_mem_ctl.scala 523:51] @@ -5654,6 +5659,7 @@ module ifu_mem_ctl( assign io_dec_mem_ctrl_ifu_miss_state_idle = miss_state == 3'h0; // @[ifu_mem_ctl.scala 235:39] assign io_ifu_axi_ar_valid = ifu_bus_cmd_valid; // @[ifu_mem_ctl.scala 497:23] assign io_ifu_axi_ar_bits_id = bus_rd_addr_count & _T_2608; // @[ifu_mem_ctl.scala 498:25] + assign io_ifu_axi_ar_bits_addr = _T_2610 & _T_2612; // @[ifu_mem_ctl.scala 499:27] assign io_ifu_axi_r_ready = 1'h1; // @[ifu_mem_ctl.scala 504:22] assign io_iccm_rw_addr = _T_3110 ? io_dma_mem_ctl_dma_mem_addr[15:1] : _T_3117; // @[ifu_mem_ctl.scala 599:19] assign io_iccm_buf_correct_ecc = iccm_correct_ecc & _T_2497; // @[ifu_mem_ctl.scala 395:27] @@ -6330,629 +6336,631 @@ initial begin _RAND_159 = {1{`RANDOM}}; fetch_uncacheable_ff = _RAND_159[0:0]; _RAND_160 = {1{`RANDOM}}; - ifc_region_acc_fault_f = _RAND_160[0:0]; + miss_addr = _RAND_160[25:0]; _RAND_161 = {1{`RANDOM}}; - bus_rd_addr_count = _RAND_161[2:0]; + ifc_region_acc_fault_f = _RAND_161[0:0]; _RAND_162 = {1{`RANDOM}}; - ic_act_miss_f_delayed = _RAND_162[0:0]; - _RAND_163 = {2{`RANDOM}}; - ifu_bus_rdata_ff = _RAND_163[63:0]; - _RAND_164 = {1{`RANDOM}}; - ic_miss_buff_data_0 = _RAND_164[31:0]; + bus_rd_addr_count = _RAND_162[2:0]; + _RAND_163 = {1{`RANDOM}}; + ic_act_miss_f_delayed = _RAND_163[0:0]; + _RAND_164 = {2{`RANDOM}}; + ifu_bus_rdata_ff = _RAND_164[63:0]; _RAND_165 = {1{`RANDOM}}; - ic_miss_buff_data_1 = _RAND_165[31:0]; + ic_miss_buff_data_0 = _RAND_165[31:0]; _RAND_166 = {1{`RANDOM}}; - ic_miss_buff_data_2 = _RAND_166[31:0]; + ic_miss_buff_data_1 = _RAND_166[31:0]; _RAND_167 = {1{`RANDOM}}; - ic_miss_buff_data_3 = _RAND_167[31:0]; + ic_miss_buff_data_2 = _RAND_167[31:0]; _RAND_168 = {1{`RANDOM}}; - ic_miss_buff_data_4 = _RAND_168[31:0]; + ic_miss_buff_data_3 = _RAND_168[31:0]; _RAND_169 = {1{`RANDOM}}; - ic_miss_buff_data_5 = _RAND_169[31:0]; + ic_miss_buff_data_4 = _RAND_169[31:0]; _RAND_170 = {1{`RANDOM}}; - ic_miss_buff_data_6 = _RAND_170[31:0]; + ic_miss_buff_data_5 = _RAND_170[31:0]; _RAND_171 = {1{`RANDOM}}; - ic_miss_buff_data_7 = _RAND_171[31:0]; + ic_miss_buff_data_6 = _RAND_171[31:0]; _RAND_172 = {1{`RANDOM}}; - ic_miss_buff_data_8 = _RAND_172[31:0]; + ic_miss_buff_data_7 = _RAND_172[31:0]; _RAND_173 = {1{`RANDOM}}; - ic_miss_buff_data_9 = _RAND_173[31:0]; + ic_miss_buff_data_8 = _RAND_173[31:0]; _RAND_174 = {1{`RANDOM}}; - ic_miss_buff_data_10 = _RAND_174[31:0]; + ic_miss_buff_data_9 = _RAND_174[31:0]; _RAND_175 = {1{`RANDOM}}; - ic_miss_buff_data_11 = _RAND_175[31:0]; + ic_miss_buff_data_10 = _RAND_175[31:0]; _RAND_176 = {1{`RANDOM}}; - ic_miss_buff_data_12 = _RAND_176[31:0]; + ic_miss_buff_data_11 = _RAND_176[31:0]; _RAND_177 = {1{`RANDOM}}; - ic_miss_buff_data_13 = _RAND_177[31:0]; + ic_miss_buff_data_12 = _RAND_177[31:0]; _RAND_178 = {1{`RANDOM}}; - ic_miss_buff_data_14 = _RAND_178[31:0]; + ic_miss_buff_data_13 = _RAND_178[31:0]; _RAND_179 = {1{`RANDOM}}; - ic_miss_buff_data_15 = _RAND_179[31:0]; + ic_miss_buff_data_14 = _RAND_179[31:0]; _RAND_180 = {1{`RANDOM}}; - ic_crit_wd_rdy_new_ff = _RAND_180[0:0]; + ic_miss_buff_data_15 = _RAND_180[31:0]; _RAND_181 = {1{`RANDOM}}; - ic_miss_buff_data_error = _RAND_181[7:0]; + ic_crit_wd_rdy_new_ff = _RAND_181[0:0]; _RAND_182 = {1{`RANDOM}}; - ic_debug_ict_array_sel_ff = _RAND_182[0:0]; + ic_miss_buff_data_error = _RAND_182[7:0]; _RAND_183 = {1{`RANDOM}}; - ic_tag_valid_out_1_0 = _RAND_183[0:0]; + ic_debug_ict_array_sel_ff = _RAND_183[0:0]; _RAND_184 = {1{`RANDOM}}; - ic_tag_valid_out_1_1 = _RAND_184[0:0]; + ic_tag_valid_out_1_0 = _RAND_184[0:0]; _RAND_185 = {1{`RANDOM}}; - ic_tag_valid_out_1_2 = _RAND_185[0:0]; + ic_tag_valid_out_1_1 = _RAND_185[0:0]; _RAND_186 = {1{`RANDOM}}; - ic_tag_valid_out_1_3 = _RAND_186[0:0]; + ic_tag_valid_out_1_2 = _RAND_186[0:0]; _RAND_187 = {1{`RANDOM}}; - ic_tag_valid_out_1_4 = _RAND_187[0:0]; + ic_tag_valid_out_1_3 = _RAND_187[0:0]; _RAND_188 = {1{`RANDOM}}; - ic_tag_valid_out_1_5 = _RAND_188[0:0]; + ic_tag_valid_out_1_4 = _RAND_188[0:0]; _RAND_189 = {1{`RANDOM}}; - ic_tag_valid_out_1_6 = _RAND_189[0:0]; + ic_tag_valid_out_1_5 = _RAND_189[0:0]; _RAND_190 = {1{`RANDOM}}; - ic_tag_valid_out_1_7 = _RAND_190[0:0]; + ic_tag_valid_out_1_6 = _RAND_190[0:0]; _RAND_191 = {1{`RANDOM}}; - ic_tag_valid_out_1_8 = _RAND_191[0:0]; + ic_tag_valid_out_1_7 = _RAND_191[0:0]; _RAND_192 = {1{`RANDOM}}; - ic_tag_valid_out_1_9 = _RAND_192[0:0]; + ic_tag_valid_out_1_8 = _RAND_192[0:0]; _RAND_193 = {1{`RANDOM}}; - ic_tag_valid_out_1_10 = _RAND_193[0:0]; + ic_tag_valid_out_1_9 = _RAND_193[0:0]; _RAND_194 = {1{`RANDOM}}; - ic_tag_valid_out_1_11 = _RAND_194[0:0]; + ic_tag_valid_out_1_10 = _RAND_194[0:0]; _RAND_195 = {1{`RANDOM}}; - ic_tag_valid_out_1_12 = _RAND_195[0:0]; + ic_tag_valid_out_1_11 = _RAND_195[0:0]; _RAND_196 = {1{`RANDOM}}; - ic_tag_valid_out_1_13 = _RAND_196[0:0]; + ic_tag_valid_out_1_12 = _RAND_196[0:0]; _RAND_197 = {1{`RANDOM}}; - ic_tag_valid_out_1_14 = _RAND_197[0:0]; + ic_tag_valid_out_1_13 = _RAND_197[0:0]; _RAND_198 = {1{`RANDOM}}; - ic_tag_valid_out_1_15 = _RAND_198[0:0]; + ic_tag_valid_out_1_14 = _RAND_198[0:0]; _RAND_199 = {1{`RANDOM}}; - ic_tag_valid_out_1_16 = _RAND_199[0:0]; + ic_tag_valid_out_1_15 = _RAND_199[0:0]; _RAND_200 = {1{`RANDOM}}; - ic_tag_valid_out_1_17 = _RAND_200[0:0]; + ic_tag_valid_out_1_16 = _RAND_200[0:0]; _RAND_201 = {1{`RANDOM}}; - ic_tag_valid_out_1_18 = _RAND_201[0:0]; + ic_tag_valid_out_1_17 = _RAND_201[0:0]; _RAND_202 = {1{`RANDOM}}; - ic_tag_valid_out_1_19 = _RAND_202[0:0]; + ic_tag_valid_out_1_18 = _RAND_202[0:0]; _RAND_203 = {1{`RANDOM}}; - ic_tag_valid_out_1_20 = _RAND_203[0:0]; + ic_tag_valid_out_1_19 = _RAND_203[0:0]; _RAND_204 = {1{`RANDOM}}; - ic_tag_valid_out_1_21 = _RAND_204[0:0]; + ic_tag_valid_out_1_20 = _RAND_204[0:0]; _RAND_205 = {1{`RANDOM}}; - ic_tag_valid_out_1_22 = _RAND_205[0:0]; + ic_tag_valid_out_1_21 = _RAND_205[0:0]; _RAND_206 = {1{`RANDOM}}; - ic_tag_valid_out_1_23 = _RAND_206[0:0]; + ic_tag_valid_out_1_22 = _RAND_206[0:0]; _RAND_207 = {1{`RANDOM}}; - ic_tag_valid_out_1_24 = _RAND_207[0:0]; + ic_tag_valid_out_1_23 = _RAND_207[0:0]; _RAND_208 = {1{`RANDOM}}; - ic_tag_valid_out_1_25 = _RAND_208[0:0]; + ic_tag_valid_out_1_24 = _RAND_208[0:0]; _RAND_209 = {1{`RANDOM}}; - ic_tag_valid_out_1_26 = _RAND_209[0:0]; + ic_tag_valid_out_1_25 = _RAND_209[0:0]; _RAND_210 = {1{`RANDOM}}; - ic_tag_valid_out_1_27 = _RAND_210[0:0]; + ic_tag_valid_out_1_26 = _RAND_210[0:0]; _RAND_211 = {1{`RANDOM}}; - ic_tag_valid_out_1_28 = _RAND_211[0:0]; + ic_tag_valid_out_1_27 = _RAND_211[0:0]; _RAND_212 = {1{`RANDOM}}; - ic_tag_valid_out_1_29 = _RAND_212[0:0]; + ic_tag_valid_out_1_28 = _RAND_212[0:0]; _RAND_213 = {1{`RANDOM}}; - ic_tag_valid_out_1_30 = _RAND_213[0:0]; + ic_tag_valid_out_1_29 = _RAND_213[0:0]; _RAND_214 = {1{`RANDOM}}; - ic_tag_valid_out_1_31 = _RAND_214[0:0]; + ic_tag_valid_out_1_30 = _RAND_214[0:0]; _RAND_215 = {1{`RANDOM}}; - ic_tag_valid_out_1_32 = _RAND_215[0:0]; + ic_tag_valid_out_1_31 = _RAND_215[0:0]; _RAND_216 = {1{`RANDOM}}; - ic_tag_valid_out_1_33 = _RAND_216[0:0]; + ic_tag_valid_out_1_32 = _RAND_216[0:0]; _RAND_217 = {1{`RANDOM}}; - ic_tag_valid_out_1_34 = _RAND_217[0:0]; + ic_tag_valid_out_1_33 = _RAND_217[0:0]; _RAND_218 = {1{`RANDOM}}; - ic_tag_valid_out_1_35 = _RAND_218[0:0]; + ic_tag_valid_out_1_34 = _RAND_218[0:0]; _RAND_219 = {1{`RANDOM}}; - ic_tag_valid_out_1_36 = _RAND_219[0:0]; + ic_tag_valid_out_1_35 = _RAND_219[0:0]; _RAND_220 = {1{`RANDOM}}; - ic_tag_valid_out_1_37 = _RAND_220[0:0]; + ic_tag_valid_out_1_36 = _RAND_220[0:0]; _RAND_221 = {1{`RANDOM}}; - ic_tag_valid_out_1_38 = _RAND_221[0:0]; + ic_tag_valid_out_1_37 = _RAND_221[0:0]; _RAND_222 = {1{`RANDOM}}; - ic_tag_valid_out_1_39 = _RAND_222[0:0]; + ic_tag_valid_out_1_38 = _RAND_222[0:0]; _RAND_223 = {1{`RANDOM}}; - ic_tag_valid_out_1_40 = _RAND_223[0:0]; + ic_tag_valid_out_1_39 = _RAND_223[0:0]; _RAND_224 = {1{`RANDOM}}; - ic_tag_valid_out_1_41 = _RAND_224[0:0]; + ic_tag_valid_out_1_40 = _RAND_224[0:0]; _RAND_225 = {1{`RANDOM}}; - ic_tag_valid_out_1_42 = _RAND_225[0:0]; + ic_tag_valid_out_1_41 = _RAND_225[0:0]; _RAND_226 = {1{`RANDOM}}; - ic_tag_valid_out_1_43 = _RAND_226[0:0]; + ic_tag_valid_out_1_42 = _RAND_226[0:0]; _RAND_227 = {1{`RANDOM}}; - ic_tag_valid_out_1_44 = _RAND_227[0:0]; + ic_tag_valid_out_1_43 = _RAND_227[0:0]; _RAND_228 = {1{`RANDOM}}; - ic_tag_valid_out_1_45 = _RAND_228[0:0]; + ic_tag_valid_out_1_44 = _RAND_228[0:0]; _RAND_229 = {1{`RANDOM}}; - ic_tag_valid_out_1_46 = _RAND_229[0:0]; + ic_tag_valid_out_1_45 = _RAND_229[0:0]; _RAND_230 = {1{`RANDOM}}; - ic_tag_valid_out_1_47 = _RAND_230[0:0]; + ic_tag_valid_out_1_46 = _RAND_230[0:0]; _RAND_231 = {1{`RANDOM}}; - ic_tag_valid_out_1_48 = _RAND_231[0:0]; + ic_tag_valid_out_1_47 = _RAND_231[0:0]; _RAND_232 = {1{`RANDOM}}; - ic_tag_valid_out_1_49 = _RAND_232[0:0]; + ic_tag_valid_out_1_48 = _RAND_232[0:0]; _RAND_233 = {1{`RANDOM}}; - ic_tag_valid_out_1_50 = _RAND_233[0:0]; + ic_tag_valid_out_1_49 = _RAND_233[0:0]; _RAND_234 = {1{`RANDOM}}; - ic_tag_valid_out_1_51 = _RAND_234[0:0]; + ic_tag_valid_out_1_50 = _RAND_234[0:0]; _RAND_235 = {1{`RANDOM}}; - ic_tag_valid_out_1_52 = _RAND_235[0:0]; + ic_tag_valid_out_1_51 = _RAND_235[0:0]; _RAND_236 = {1{`RANDOM}}; - ic_tag_valid_out_1_53 = _RAND_236[0:0]; + ic_tag_valid_out_1_52 = _RAND_236[0:0]; _RAND_237 = {1{`RANDOM}}; - ic_tag_valid_out_1_54 = _RAND_237[0:0]; + ic_tag_valid_out_1_53 = _RAND_237[0:0]; _RAND_238 = {1{`RANDOM}}; - ic_tag_valid_out_1_55 = _RAND_238[0:0]; + ic_tag_valid_out_1_54 = _RAND_238[0:0]; _RAND_239 = {1{`RANDOM}}; - ic_tag_valid_out_1_56 = _RAND_239[0:0]; + ic_tag_valid_out_1_55 = _RAND_239[0:0]; _RAND_240 = {1{`RANDOM}}; - ic_tag_valid_out_1_57 = _RAND_240[0:0]; + ic_tag_valid_out_1_56 = _RAND_240[0:0]; _RAND_241 = {1{`RANDOM}}; - ic_tag_valid_out_1_58 = _RAND_241[0:0]; + ic_tag_valid_out_1_57 = _RAND_241[0:0]; _RAND_242 = {1{`RANDOM}}; - ic_tag_valid_out_1_59 = _RAND_242[0:0]; + ic_tag_valid_out_1_58 = _RAND_242[0:0]; _RAND_243 = {1{`RANDOM}}; - ic_tag_valid_out_1_60 = _RAND_243[0:0]; + ic_tag_valid_out_1_59 = _RAND_243[0:0]; _RAND_244 = {1{`RANDOM}}; - ic_tag_valid_out_1_61 = _RAND_244[0:0]; + ic_tag_valid_out_1_60 = _RAND_244[0:0]; _RAND_245 = {1{`RANDOM}}; - ic_tag_valid_out_1_62 = _RAND_245[0:0]; + ic_tag_valid_out_1_61 = _RAND_245[0:0]; _RAND_246 = {1{`RANDOM}}; - ic_tag_valid_out_1_63 = _RAND_246[0:0]; + ic_tag_valid_out_1_62 = _RAND_246[0:0]; _RAND_247 = {1{`RANDOM}}; - ic_tag_valid_out_1_64 = _RAND_247[0:0]; + ic_tag_valid_out_1_63 = _RAND_247[0:0]; _RAND_248 = {1{`RANDOM}}; - ic_tag_valid_out_1_65 = _RAND_248[0:0]; + ic_tag_valid_out_1_64 = _RAND_248[0:0]; _RAND_249 = {1{`RANDOM}}; - ic_tag_valid_out_1_66 = _RAND_249[0:0]; + ic_tag_valid_out_1_65 = _RAND_249[0:0]; _RAND_250 = {1{`RANDOM}}; - ic_tag_valid_out_1_67 = _RAND_250[0:0]; + ic_tag_valid_out_1_66 = _RAND_250[0:0]; _RAND_251 = {1{`RANDOM}}; - ic_tag_valid_out_1_68 = _RAND_251[0:0]; + ic_tag_valid_out_1_67 = _RAND_251[0:0]; _RAND_252 = {1{`RANDOM}}; - ic_tag_valid_out_1_69 = _RAND_252[0:0]; + ic_tag_valid_out_1_68 = _RAND_252[0:0]; _RAND_253 = {1{`RANDOM}}; - ic_tag_valid_out_1_70 = _RAND_253[0:0]; + ic_tag_valid_out_1_69 = _RAND_253[0:0]; _RAND_254 = {1{`RANDOM}}; - ic_tag_valid_out_1_71 = _RAND_254[0:0]; + ic_tag_valid_out_1_70 = _RAND_254[0:0]; _RAND_255 = {1{`RANDOM}}; - ic_tag_valid_out_1_72 = _RAND_255[0:0]; + ic_tag_valid_out_1_71 = _RAND_255[0:0]; _RAND_256 = {1{`RANDOM}}; - ic_tag_valid_out_1_73 = _RAND_256[0:0]; + ic_tag_valid_out_1_72 = _RAND_256[0:0]; _RAND_257 = {1{`RANDOM}}; - ic_tag_valid_out_1_74 = _RAND_257[0:0]; + ic_tag_valid_out_1_73 = _RAND_257[0:0]; _RAND_258 = {1{`RANDOM}}; - ic_tag_valid_out_1_75 = _RAND_258[0:0]; + ic_tag_valid_out_1_74 = _RAND_258[0:0]; _RAND_259 = {1{`RANDOM}}; - ic_tag_valid_out_1_76 = _RAND_259[0:0]; + ic_tag_valid_out_1_75 = _RAND_259[0:0]; _RAND_260 = {1{`RANDOM}}; - ic_tag_valid_out_1_77 = _RAND_260[0:0]; + ic_tag_valid_out_1_76 = _RAND_260[0:0]; _RAND_261 = {1{`RANDOM}}; - ic_tag_valid_out_1_78 = _RAND_261[0:0]; + ic_tag_valid_out_1_77 = _RAND_261[0:0]; _RAND_262 = {1{`RANDOM}}; - ic_tag_valid_out_1_79 = _RAND_262[0:0]; + ic_tag_valid_out_1_78 = _RAND_262[0:0]; _RAND_263 = {1{`RANDOM}}; - ic_tag_valid_out_1_80 = _RAND_263[0:0]; + ic_tag_valid_out_1_79 = _RAND_263[0:0]; _RAND_264 = {1{`RANDOM}}; - ic_tag_valid_out_1_81 = _RAND_264[0:0]; + ic_tag_valid_out_1_80 = _RAND_264[0:0]; _RAND_265 = {1{`RANDOM}}; - ic_tag_valid_out_1_82 = _RAND_265[0:0]; + ic_tag_valid_out_1_81 = _RAND_265[0:0]; _RAND_266 = {1{`RANDOM}}; - ic_tag_valid_out_1_83 = _RAND_266[0:0]; + ic_tag_valid_out_1_82 = _RAND_266[0:0]; _RAND_267 = {1{`RANDOM}}; - ic_tag_valid_out_1_84 = _RAND_267[0:0]; + ic_tag_valid_out_1_83 = _RAND_267[0:0]; _RAND_268 = {1{`RANDOM}}; - ic_tag_valid_out_1_85 = _RAND_268[0:0]; + ic_tag_valid_out_1_84 = _RAND_268[0:0]; _RAND_269 = {1{`RANDOM}}; - ic_tag_valid_out_1_86 = _RAND_269[0:0]; + ic_tag_valid_out_1_85 = _RAND_269[0:0]; _RAND_270 = {1{`RANDOM}}; - ic_tag_valid_out_1_87 = _RAND_270[0:0]; + ic_tag_valid_out_1_86 = _RAND_270[0:0]; _RAND_271 = {1{`RANDOM}}; - ic_tag_valid_out_1_88 = _RAND_271[0:0]; + ic_tag_valid_out_1_87 = _RAND_271[0:0]; _RAND_272 = {1{`RANDOM}}; - ic_tag_valid_out_1_89 = _RAND_272[0:0]; + ic_tag_valid_out_1_88 = _RAND_272[0:0]; _RAND_273 = {1{`RANDOM}}; - ic_tag_valid_out_1_90 = _RAND_273[0:0]; + ic_tag_valid_out_1_89 = _RAND_273[0:0]; _RAND_274 = {1{`RANDOM}}; - ic_tag_valid_out_1_91 = _RAND_274[0:0]; + ic_tag_valid_out_1_90 = _RAND_274[0:0]; _RAND_275 = {1{`RANDOM}}; - ic_tag_valid_out_1_92 = _RAND_275[0:0]; + ic_tag_valid_out_1_91 = _RAND_275[0:0]; _RAND_276 = {1{`RANDOM}}; - ic_tag_valid_out_1_93 = _RAND_276[0:0]; + ic_tag_valid_out_1_92 = _RAND_276[0:0]; _RAND_277 = {1{`RANDOM}}; - ic_tag_valid_out_1_94 = _RAND_277[0:0]; + ic_tag_valid_out_1_93 = _RAND_277[0:0]; _RAND_278 = {1{`RANDOM}}; - ic_tag_valid_out_1_95 = _RAND_278[0:0]; + ic_tag_valid_out_1_94 = _RAND_278[0:0]; _RAND_279 = {1{`RANDOM}}; - ic_tag_valid_out_1_96 = _RAND_279[0:0]; + ic_tag_valid_out_1_95 = _RAND_279[0:0]; _RAND_280 = {1{`RANDOM}}; - ic_tag_valid_out_1_97 = _RAND_280[0:0]; + ic_tag_valid_out_1_96 = _RAND_280[0:0]; _RAND_281 = {1{`RANDOM}}; - ic_tag_valid_out_1_98 = _RAND_281[0:0]; + ic_tag_valid_out_1_97 = _RAND_281[0:0]; _RAND_282 = {1{`RANDOM}}; - ic_tag_valid_out_1_99 = _RAND_282[0:0]; + ic_tag_valid_out_1_98 = _RAND_282[0:0]; _RAND_283 = {1{`RANDOM}}; - ic_tag_valid_out_1_100 = _RAND_283[0:0]; + ic_tag_valid_out_1_99 = _RAND_283[0:0]; _RAND_284 = {1{`RANDOM}}; - ic_tag_valid_out_1_101 = _RAND_284[0:0]; + ic_tag_valid_out_1_100 = _RAND_284[0:0]; _RAND_285 = {1{`RANDOM}}; - ic_tag_valid_out_1_102 = _RAND_285[0:0]; + ic_tag_valid_out_1_101 = _RAND_285[0:0]; _RAND_286 = {1{`RANDOM}}; - ic_tag_valid_out_1_103 = _RAND_286[0:0]; + ic_tag_valid_out_1_102 = _RAND_286[0:0]; _RAND_287 = {1{`RANDOM}}; - ic_tag_valid_out_1_104 = _RAND_287[0:0]; + ic_tag_valid_out_1_103 = _RAND_287[0:0]; _RAND_288 = {1{`RANDOM}}; - ic_tag_valid_out_1_105 = _RAND_288[0:0]; + ic_tag_valid_out_1_104 = _RAND_288[0:0]; _RAND_289 = {1{`RANDOM}}; - ic_tag_valid_out_1_106 = _RAND_289[0:0]; + ic_tag_valid_out_1_105 = _RAND_289[0:0]; _RAND_290 = {1{`RANDOM}}; - ic_tag_valid_out_1_107 = _RAND_290[0:0]; + ic_tag_valid_out_1_106 = _RAND_290[0:0]; _RAND_291 = {1{`RANDOM}}; - ic_tag_valid_out_1_108 = _RAND_291[0:0]; + ic_tag_valid_out_1_107 = _RAND_291[0:0]; _RAND_292 = {1{`RANDOM}}; - ic_tag_valid_out_1_109 = _RAND_292[0:0]; + ic_tag_valid_out_1_108 = _RAND_292[0:0]; _RAND_293 = {1{`RANDOM}}; - ic_tag_valid_out_1_110 = _RAND_293[0:0]; + ic_tag_valid_out_1_109 = _RAND_293[0:0]; _RAND_294 = {1{`RANDOM}}; - ic_tag_valid_out_1_111 = _RAND_294[0:0]; + ic_tag_valid_out_1_110 = _RAND_294[0:0]; _RAND_295 = {1{`RANDOM}}; - ic_tag_valid_out_1_112 = _RAND_295[0:0]; + ic_tag_valid_out_1_111 = _RAND_295[0:0]; _RAND_296 = {1{`RANDOM}}; - ic_tag_valid_out_1_113 = _RAND_296[0:0]; + ic_tag_valid_out_1_112 = _RAND_296[0:0]; _RAND_297 = {1{`RANDOM}}; - ic_tag_valid_out_1_114 = _RAND_297[0:0]; + ic_tag_valid_out_1_113 = _RAND_297[0:0]; _RAND_298 = {1{`RANDOM}}; - ic_tag_valid_out_1_115 = _RAND_298[0:0]; + ic_tag_valid_out_1_114 = _RAND_298[0:0]; _RAND_299 = {1{`RANDOM}}; - ic_tag_valid_out_1_116 = _RAND_299[0:0]; + ic_tag_valid_out_1_115 = _RAND_299[0:0]; _RAND_300 = {1{`RANDOM}}; - ic_tag_valid_out_1_117 = _RAND_300[0:0]; + ic_tag_valid_out_1_116 = _RAND_300[0:0]; _RAND_301 = {1{`RANDOM}}; - ic_tag_valid_out_1_118 = _RAND_301[0:0]; + ic_tag_valid_out_1_117 = _RAND_301[0:0]; _RAND_302 = {1{`RANDOM}}; - ic_tag_valid_out_1_119 = _RAND_302[0:0]; + ic_tag_valid_out_1_118 = _RAND_302[0:0]; _RAND_303 = {1{`RANDOM}}; - ic_tag_valid_out_1_120 = _RAND_303[0:0]; + ic_tag_valid_out_1_119 = _RAND_303[0:0]; _RAND_304 = {1{`RANDOM}}; - ic_tag_valid_out_1_121 = _RAND_304[0:0]; + ic_tag_valid_out_1_120 = _RAND_304[0:0]; _RAND_305 = {1{`RANDOM}}; - ic_tag_valid_out_1_122 = _RAND_305[0:0]; + ic_tag_valid_out_1_121 = _RAND_305[0:0]; _RAND_306 = {1{`RANDOM}}; - ic_tag_valid_out_1_123 = _RAND_306[0:0]; + ic_tag_valid_out_1_122 = _RAND_306[0:0]; _RAND_307 = {1{`RANDOM}}; - ic_tag_valid_out_1_124 = _RAND_307[0:0]; + ic_tag_valid_out_1_123 = _RAND_307[0:0]; _RAND_308 = {1{`RANDOM}}; - ic_tag_valid_out_1_125 = _RAND_308[0:0]; + ic_tag_valid_out_1_124 = _RAND_308[0:0]; _RAND_309 = {1{`RANDOM}}; - ic_tag_valid_out_1_126 = _RAND_309[0:0]; + ic_tag_valid_out_1_125 = _RAND_309[0:0]; _RAND_310 = {1{`RANDOM}}; - ic_tag_valid_out_1_127 = _RAND_310[0:0]; + ic_tag_valid_out_1_126 = _RAND_310[0:0]; _RAND_311 = {1{`RANDOM}}; - ic_tag_valid_out_0_0 = _RAND_311[0:0]; + ic_tag_valid_out_1_127 = _RAND_311[0:0]; _RAND_312 = {1{`RANDOM}}; - ic_tag_valid_out_0_1 = _RAND_312[0:0]; + ic_tag_valid_out_0_0 = _RAND_312[0:0]; _RAND_313 = {1{`RANDOM}}; - ic_tag_valid_out_0_2 = _RAND_313[0:0]; + ic_tag_valid_out_0_1 = _RAND_313[0:0]; _RAND_314 = {1{`RANDOM}}; - ic_tag_valid_out_0_3 = _RAND_314[0:0]; + ic_tag_valid_out_0_2 = _RAND_314[0:0]; _RAND_315 = {1{`RANDOM}}; - ic_tag_valid_out_0_4 = _RAND_315[0:0]; + ic_tag_valid_out_0_3 = _RAND_315[0:0]; _RAND_316 = {1{`RANDOM}}; - ic_tag_valid_out_0_5 = _RAND_316[0:0]; + ic_tag_valid_out_0_4 = _RAND_316[0:0]; _RAND_317 = {1{`RANDOM}}; - ic_tag_valid_out_0_6 = _RAND_317[0:0]; + ic_tag_valid_out_0_5 = _RAND_317[0:0]; _RAND_318 = {1{`RANDOM}}; - ic_tag_valid_out_0_7 = _RAND_318[0:0]; + ic_tag_valid_out_0_6 = _RAND_318[0:0]; _RAND_319 = {1{`RANDOM}}; - ic_tag_valid_out_0_8 = _RAND_319[0:0]; + ic_tag_valid_out_0_7 = _RAND_319[0:0]; _RAND_320 = {1{`RANDOM}}; - ic_tag_valid_out_0_9 = _RAND_320[0:0]; + ic_tag_valid_out_0_8 = _RAND_320[0:0]; _RAND_321 = {1{`RANDOM}}; - ic_tag_valid_out_0_10 = _RAND_321[0:0]; + ic_tag_valid_out_0_9 = _RAND_321[0:0]; _RAND_322 = {1{`RANDOM}}; - ic_tag_valid_out_0_11 = _RAND_322[0:0]; + ic_tag_valid_out_0_10 = _RAND_322[0:0]; _RAND_323 = {1{`RANDOM}}; - ic_tag_valid_out_0_12 = _RAND_323[0:0]; + ic_tag_valid_out_0_11 = _RAND_323[0:0]; _RAND_324 = {1{`RANDOM}}; - ic_tag_valid_out_0_13 = _RAND_324[0:0]; + ic_tag_valid_out_0_12 = _RAND_324[0:0]; _RAND_325 = {1{`RANDOM}}; - ic_tag_valid_out_0_14 = _RAND_325[0:0]; + ic_tag_valid_out_0_13 = _RAND_325[0:0]; _RAND_326 = {1{`RANDOM}}; - ic_tag_valid_out_0_15 = _RAND_326[0:0]; + ic_tag_valid_out_0_14 = _RAND_326[0:0]; _RAND_327 = {1{`RANDOM}}; - ic_tag_valid_out_0_16 = _RAND_327[0:0]; + ic_tag_valid_out_0_15 = _RAND_327[0:0]; _RAND_328 = {1{`RANDOM}}; - ic_tag_valid_out_0_17 = _RAND_328[0:0]; + ic_tag_valid_out_0_16 = _RAND_328[0:0]; _RAND_329 = {1{`RANDOM}}; - ic_tag_valid_out_0_18 = _RAND_329[0:0]; + ic_tag_valid_out_0_17 = _RAND_329[0:0]; _RAND_330 = {1{`RANDOM}}; - ic_tag_valid_out_0_19 = _RAND_330[0:0]; + ic_tag_valid_out_0_18 = _RAND_330[0:0]; _RAND_331 = {1{`RANDOM}}; - ic_tag_valid_out_0_20 = _RAND_331[0:0]; + ic_tag_valid_out_0_19 = _RAND_331[0:0]; _RAND_332 = {1{`RANDOM}}; - ic_tag_valid_out_0_21 = _RAND_332[0:0]; + ic_tag_valid_out_0_20 = _RAND_332[0:0]; _RAND_333 = {1{`RANDOM}}; - ic_tag_valid_out_0_22 = _RAND_333[0:0]; + ic_tag_valid_out_0_21 = _RAND_333[0:0]; _RAND_334 = {1{`RANDOM}}; - ic_tag_valid_out_0_23 = _RAND_334[0:0]; + ic_tag_valid_out_0_22 = _RAND_334[0:0]; _RAND_335 = {1{`RANDOM}}; - ic_tag_valid_out_0_24 = _RAND_335[0:0]; + ic_tag_valid_out_0_23 = _RAND_335[0:0]; _RAND_336 = {1{`RANDOM}}; - ic_tag_valid_out_0_25 = _RAND_336[0:0]; + ic_tag_valid_out_0_24 = _RAND_336[0:0]; _RAND_337 = {1{`RANDOM}}; - ic_tag_valid_out_0_26 = _RAND_337[0:0]; + ic_tag_valid_out_0_25 = _RAND_337[0:0]; _RAND_338 = {1{`RANDOM}}; - ic_tag_valid_out_0_27 = _RAND_338[0:0]; + ic_tag_valid_out_0_26 = _RAND_338[0:0]; _RAND_339 = {1{`RANDOM}}; - ic_tag_valid_out_0_28 = _RAND_339[0:0]; + ic_tag_valid_out_0_27 = _RAND_339[0:0]; _RAND_340 = {1{`RANDOM}}; - ic_tag_valid_out_0_29 = _RAND_340[0:0]; + ic_tag_valid_out_0_28 = _RAND_340[0:0]; _RAND_341 = {1{`RANDOM}}; - ic_tag_valid_out_0_30 = _RAND_341[0:0]; + ic_tag_valid_out_0_29 = _RAND_341[0:0]; _RAND_342 = {1{`RANDOM}}; - ic_tag_valid_out_0_31 = _RAND_342[0:0]; + ic_tag_valid_out_0_30 = _RAND_342[0:0]; _RAND_343 = {1{`RANDOM}}; - ic_tag_valid_out_0_32 = _RAND_343[0:0]; + ic_tag_valid_out_0_31 = _RAND_343[0:0]; _RAND_344 = {1{`RANDOM}}; - ic_tag_valid_out_0_33 = _RAND_344[0:0]; + ic_tag_valid_out_0_32 = _RAND_344[0:0]; _RAND_345 = {1{`RANDOM}}; - ic_tag_valid_out_0_34 = _RAND_345[0:0]; + ic_tag_valid_out_0_33 = _RAND_345[0:0]; _RAND_346 = {1{`RANDOM}}; - ic_tag_valid_out_0_35 = _RAND_346[0:0]; + ic_tag_valid_out_0_34 = _RAND_346[0:0]; _RAND_347 = {1{`RANDOM}}; - ic_tag_valid_out_0_36 = _RAND_347[0:0]; + ic_tag_valid_out_0_35 = _RAND_347[0:0]; _RAND_348 = {1{`RANDOM}}; - ic_tag_valid_out_0_37 = _RAND_348[0:0]; + ic_tag_valid_out_0_36 = _RAND_348[0:0]; _RAND_349 = {1{`RANDOM}}; - ic_tag_valid_out_0_38 = _RAND_349[0:0]; + ic_tag_valid_out_0_37 = _RAND_349[0:0]; _RAND_350 = {1{`RANDOM}}; - ic_tag_valid_out_0_39 = _RAND_350[0:0]; + ic_tag_valid_out_0_38 = _RAND_350[0:0]; _RAND_351 = {1{`RANDOM}}; - ic_tag_valid_out_0_40 = _RAND_351[0:0]; + ic_tag_valid_out_0_39 = _RAND_351[0:0]; _RAND_352 = {1{`RANDOM}}; - ic_tag_valid_out_0_41 = _RAND_352[0:0]; + ic_tag_valid_out_0_40 = _RAND_352[0:0]; _RAND_353 = {1{`RANDOM}}; - ic_tag_valid_out_0_42 = _RAND_353[0:0]; + ic_tag_valid_out_0_41 = _RAND_353[0:0]; _RAND_354 = {1{`RANDOM}}; - ic_tag_valid_out_0_43 = _RAND_354[0:0]; + ic_tag_valid_out_0_42 = _RAND_354[0:0]; _RAND_355 = {1{`RANDOM}}; - ic_tag_valid_out_0_44 = _RAND_355[0:0]; + ic_tag_valid_out_0_43 = _RAND_355[0:0]; _RAND_356 = {1{`RANDOM}}; - ic_tag_valid_out_0_45 = _RAND_356[0:0]; + ic_tag_valid_out_0_44 = _RAND_356[0:0]; _RAND_357 = {1{`RANDOM}}; - ic_tag_valid_out_0_46 = _RAND_357[0:0]; + ic_tag_valid_out_0_45 = _RAND_357[0:0]; _RAND_358 = {1{`RANDOM}}; - ic_tag_valid_out_0_47 = _RAND_358[0:0]; + ic_tag_valid_out_0_46 = _RAND_358[0:0]; _RAND_359 = {1{`RANDOM}}; - ic_tag_valid_out_0_48 = _RAND_359[0:0]; + ic_tag_valid_out_0_47 = _RAND_359[0:0]; _RAND_360 = {1{`RANDOM}}; - ic_tag_valid_out_0_49 = _RAND_360[0:0]; + ic_tag_valid_out_0_48 = _RAND_360[0:0]; _RAND_361 = {1{`RANDOM}}; - ic_tag_valid_out_0_50 = _RAND_361[0:0]; + ic_tag_valid_out_0_49 = _RAND_361[0:0]; _RAND_362 = {1{`RANDOM}}; - ic_tag_valid_out_0_51 = _RAND_362[0:0]; + ic_tag_valid_out_0_50 = _RAND_362[0:0]; _RAND_363 = {1{`RANDOM}}; - ic_tag_valid_out_0_52 = _RAND_363[0:0]; + ic_tag_valid_out_0_51 = _RAND_363[0:0]; _RAND_364 = {1{`RANDOM}}; - ic_tag_valid_out_0_53 = _RAND_364[0:0]; + ic_tag_valid_out_0_52 = _RAND_364[0:0]; _RAND_365 = {1{`RANDOM}}; - ic_tag_valid_out_0_54 = _RAND_365[0:0]; + ic_tag_valid_out_0_53 = _RAND_365[0:0]; _RAND_366 = {1{`RANDOM}}; - ic_tag_valid_out_0_55 = _RAND_366[0:0]; + ic_tag_valid_out_0_54 = _RAND_366[0:0]; _RAND_367 = {1{`RANDOM}}; - ic_tag_valid_out_0_56 = _RAND_367[0:0]; + ic_tag_valid_out_0_55 = _RAND_367[0:0]; _RAND_368 = {1{`RANDOM}}; - ic_tag_valid_out_0_57 = _RAND_368[0:0]; + ic_tag_valid_out_0_56 = _RAND_368[0:0]; _RAND_369 = {1{`RANDOM}}; - ic_tag_valid_out_0_58 = _RAND_369[0:0]; + ic_tag_valid_out_0_57 = _RAND_369[0:0]; _RAND_370 = {1{`RANDOM}}; - ic_tag_valid_out_0_59 = _RAND_370[0:0]; + ic_tag_valid_out_0_58 = _RAND_370[0:0]; _RAND_371 = {1{`RANDOM}}; - ic_tag_valid_out_0_60 = _RAND_371[0:0]; + ic_tag_valid_out_0_59 = _RAND_371[0:0]; _RAND_372 = {1{`RANDOM}}; - ic_tag_valid_out_0_61 = _RAND_372[0:0]; + ic_tag_valid_out_0_60 = _RAND_372[0:0]; _RAND_373 = {1{`RANDOM}}; - ic_tag_valid_out_0_62 = _RAND_373[0:0]; + ic_tag_valid_out_0_61 = _RAND_373[0:0]; _RAND_374 = {1{`RANDOM}}; - ic_tag_valid_out_0_63 = _RAND_374[0:0]; + ic_tag_valid_out_0_62 = _RAND_374[0:0]; _RAND_375 = {1{`RANDOM}}; - ic_tag_valid_out_0_64 = _RAND_375[0:0]; + ic_tag_valid_out_0_63 = _RAND_375[0:0]; _RAND_376 = {1{`RANDOM}}; - ic_tag_valid_out_0_65 = _RAND_376[0:0]; + ic_tag_valid_out_0_64 = _RAND_376[0:0]; _RAND_377 = {1{`RANDOM}}; - ic_tag_valid_out_0_66 = _RAND_377[0:0]; + ic_tag_valid_out_0_65 = _RAND_377[0:0]; _RAND_378 = {1{`RANDOM}}; - ic_tag_valid_out_0_67 = _RAND_378[0:0]; + ic_tag_valid_out_0_66 = _RAND_378[0:0]; _RAND_379 = {1{`RANDOM}}; - ic_tag_valid_out_0_68 = _RAND_379[0:0]; + ic_tag_valid_out_0_67 = _RAND_379[0:0]; _RAND_380 = {1{`RANDOM}}; - ic_tag_valid_out_0_69 = _RAND_380[0:0]; + ic_tag_valid_out_0_68 = _RAND_380[0:0]; _RAND_381 = {1{`RANDOM}}; - ic_tag_valid_out_0_70 = _RAND_381[0:0]; + ic_tag_valid_out_0_69 = _RAND_381[0:0]; _RAND_382 = {1{`RANDOM}}; - ic_tag_valid_out_0_71 = _RAND_382[0:0]; + ic_tag_valid_out_0_70 = _RAND_382[0:0]; _RAND_383 = {1{`RANDOM}}; - ic_tag_valid_out_0_72 = _RAND_383[0:0]; + ic_tag_valid_out_0_71 = _RAND_383[0:0]; _RAND_384 = {1{`RANDOM}}; - ic_tag_valid_out_0_73 = _RAND_384[0:0]; + ic_tag_valid_out_0_72 = _RAND_384[0:0]; _RAND_385 = {1{`RANDOM}}; - ic_tag_valid_out_0_74 = _RAND_385[0:0]; + ic_tag_valid_out_0_73 = _RAND_385[0:0]; _RAND_386 = {1{`RANDOM}}; - ic_tag_valid_out_0_75 = _RAND_386[0:0]; + ic_tag_valid_out_0_74 = _RAND_386[0:0]; _RAND_387 = {1{`RANDOM}}; - ic_tag_valid_out_0_76 = _RAND_387[0:0]; + ic_tag_valid_out_0_75 = _RAND_387[0:0]; _RAND_388 = {1{`RANDOM}}; - ic_tag_valid_out_0_77 = _RAND_388[0:0]; + ic_tag_valid_out_0_76 = _RAND_388[0:0]; _RAND_389 = {1{`RANDOM}}; - ic_tag_valid_out_0_78 = _RAND_389[0:0]; + ic_tag_valid_out_0_77 = _RAND_389[0:0]; _RAND_390 = {1{`RANDOM}}; - ic_tag_valid_out_0_79 = _RAND_390[0:0]; + ic_tag_valid_out_0_78 = _RAND_390[0:0]; _RAND_391 = {1{`RANDOM}}; - ic_tag_valid_out_0_80 = _RAND_391[0:0]; + ic_tag_valid_out_0_79 = _RAND_391[0:0]; _RAND_392 = {1{`RANDOM}}; - ic_tag_valid_out_0_81 = _RAND_392[0:0]; + ic_tag_valid_out_0_80 = _RAND_392[0:0]; _RAND_393 = {1{`RANDOM}}; - ic_tag_valid_out_0_82 = _RAND_393[0:0]; + ic_tag_valid_out_0_81 = _RAND_393[0:0]; _RAND_394 = {1{`RANDOM}}; - ic_tag_valid_out_0_83 = _RAND_394[0:0]; + ic_tag_valid_out_0_82 = _RAND_394[0:0]; _RAND_395 = {1{`RANDOM}}; - ic_tag_valid_out_0_84 = _RAND_395[0:0]; + ic_tag_valid_out_0_83 = _RAND_395[0:0]; _RAND_396 = {1{`RANDOM}}; - ic_tag_valid_out_0_85 = _RAND_396[0:0]; + ic_tag_valid_out_0_84 = _RAND_396[0:0]; _RAND_397 = {1{`RANDOM}}; - ic_tag_valid_out_0_86 = _RAND_397[0:0]; + ic_tag_valid_out_0_85 = _RAND_397[0:0]; _RAND_398 = {1{`RANDOM}}; - ic_tag_valid_out_0_87 = _RAND_398[0:0]; + ic_tag_valid_out_0_86 = _RAND_398[0:0]; _RAND_399 = {1{`RANDOM}}; - ic_tag_valid_out_0_88 = _RAND_399[0:0]; + ic_tag_valid_out_0_87 = _RAND_399[0:0]; _RAND_400 = {1{`RANDOM}}; - ic_tag_valid_out_0_89 = _RAND_400[0:0]; + ic_tag_valid_out_0_88 = _RAND_400[0:0]; _RAND_401 = {1{`RANDOM}}; - ic_tag_valid_out_0_90 = _RAND_401[0:0]; + ic_tag_valid_out_0_89 = _RAND_401[0:0]; _RAND_402 = {1{`RANDOM}}; - ic_tag_valid_out_0_91 = _RAND_402[0:0]; + ic_tag_valid_out_0_90 = _RAND_402[0:0]; _RAND_403 = {1{`RANDOM}}; - ic_tag_valid_out_0_92 = _RAND_403[0:0]; + ic_tag_valid_out_0_91 = _RAND_403[0:0]; _RAND_404 = {1{`RANDOM}}; - ic_tag_valid_out_0_93 = _RAND_404[0:0]; + ic_tag_valid_out_0_92 = _RAND_404[0:0]; _RAND_405 = {1{`RANDOM}}; - ic_tag_valid_out_0_94 = _RAND_405[0:0]; + ic_tag_valid_out_0_93 = _RAND_405[0:0]; _RAND_406 = {1{`RANDOM}}; - ic_tag_valid_out_0_95 = _RAND_406[0:0]; + ic_tag_valid_out_0_94 = _RAND_406[0:0]; _RAND_407 = {1{`RANDOM}}; - ic_tag_valid_out_0_96 = _RAND_407[0:0]; + ic_tag_valid_out_0_95 = _RAND_407[0:0]; _RAND_408 = {1{`RANDOM}}; - ic_tag_valid_out_0_97 = _RAND_408[0:0]; + ic_tag_valid_out_0_96 = _RAND_408[0:0]; _RAND_409 = {1{`RANDOM}}; - ic_tag_valid_out_0_98 = _RAND_409[0:0]; + ic_tag_valid_out_0_97 = _RAND_409[0:0]; _RAND_410 = {1{`RANDOM}}; - ic_tag_valid_out_0_99 = _RAND_410[0:0]; + ic_tag_valid_out_0_98 = _RAND_410[0:0]; _RAND_411 = {1{`RANDOM}}; - ic_tag_valid_out_0_100 = _RAND_411[0:0]; + ic_tag_valid_out_0_99 = _RAND_411[0:0]; _RAND_412 = {1{`RANDOM}}; - ic_tag_valid_out_0_101 = _RAND_412[0:0]; + ic_tag_valid_out_0_100 = _RAND_412[0:0]; _RAND_413 = {1{`RANDOM}}; - ic_tag_valid_out_0_102 = _RAND_413[0:0]; + ic_tag_valid_out_0_101 = _RAND_413[0:0]; _RAND_414 = {1{`RANDOM}}; - ic_tag_valid_out_0_103 = _RAND_414[0:0]; + ic_tag_valid_out_0_102 = _RAND_414[0:0]; _RAND_415 = {1{`RANDOM}}; - ic_tag_valid_out_0_104 = _RAND_415[0:0]; + ic_tag_valid_out_0_103 = _RAND_415[0:0]; _RAND_416 = {1{`RANDOM}}; - ic_tag_valid_out_0_105 = _RAND_416[0:0]; + ic_tag_valid_out_0_104 = _RAND_416[0:0]; _RAND_417 = {1{`RANDOM}}; - ic_tag_valid_out_0_106 = _RAND_417[0:0]; + ic_tag_valid_out_0_105 = _RAND_417[0:0]; _RAND_418 = {1{`RANDOM}}; - ic_tag_valid_out_0_107 = _RAND_418[0:0]; + ic_tag_valid_out_0_106 = _RAND_418[0:0]; _RAND_419 = {1{`RANDOM}}; - ic_tag_valid_out_0_108 = _RAND_419[0:0]; + ic_tag_valid_out_0_107 = _RAND_419[0:0]; _RAND_420 = {1{`RANDOM}}; - ic_tag_valid_out_0_109 = _RAND_420[0:0]; + ic_tag_valid_out_0_108 = _RAND_420[0:0]; _RAND_421 = {1{`RANDOM}}; - ic_tag_valid_out_0_110 = _RAND_421[0:0]; + ic_tag_valid_out_0_109 = _RAND_421[0:0]; _RAND_422 = {1{`RANDOM}}; - ic_tag_valid_out_0_111 = _RAND_422[0:0]; + ic_tag_valid_out_0_110 = _RAND_422[0:0]; _RAND_423 = {1{`RANDOM}}; - ic_tag_valid_out_0_112 = _RAND_423[0:0]; + ic_tag_valid_out_0_111 = _RAND_423[0:0]; _RAND_424 = {1{`RANDOM}}; - ic_tag_valid_out_0_113 = _RAND_424[0:0]; + ic_tag_valid_out_0_112 = _RAND_424[0:0]; _RAND_425 = {1{`RANDOM}}; - ic_tag_valid_out_0_114 = _RAND_425[0:0]; + ic_tag_valid_out_0_113 = _RAND_425[0:0]; _RAND_426 = {1{`RANDOM}}; - ic_tag_valid_out_0_115 = _RAND_426[0:0]; + ic_tag_valid_out_0_114 = _RAND_426[0:0]; _RAND_427 = {1{`RANDOM}}; - ic_tag_valid_out_0_116 = _RAND_427[0:0]; + ic_tag_valid_out_0_115 = _RAND_427[0:0]; _RAND_428 = {1{`RANDOM}}; - ic_tag_valid_out_0_117 = _RAND_428[0:0]; + ic_tag_valid_out_0_116 = _RAND_428[0:0]; _RAND_429 = {1{`RANDOM}}; - ic_tag_valid_out_0_118 = _RAND_429[0:0]; + ic_tag_valid_out_0_117 = _RAND_429[0:0]; _RAND_430 = {1{`RANDOM}}; - ic_tag_valid_out_0_119 = _RAND_430[0:0]; + ic_tag_valid_out_0_118 = _RAND_430[0:0]; _RAND_431 = {1{`RANDOM}}; - ic_tag_valid_out_0_120 = _RAND_431[0:0]; + ic_tag_valid_out_0_119 = _RAND_431[0:0]; _RAND_432 = {1{`RANDOM}}; - ic_tag_valid_out_0_121 = _RAND_432[0:0]; + ic_tag_valid_out_0_120 = _RAND_432[0:0]; _RAND_433 = {1{`RANDOM}}; - ic_tag_valid_out_0_122 = _RAND_433[0:0]; + ic_tag_valid_out_0_121 = _RAND_433[0:0]; _RAND_434 = {1{`RANDOM}}; - ic_tag_valid_out_0_123 = _RAND_434[0:0]; + ic_tag_valid_out_0_122 = _RAND_434[0:0]; _RAND_435 = {1{`RANDOM}}; - ic_tag_valid_out_0_124 = _RAND_435[0:0]; + ic_tag_valid_out_0_123 = _RAND_435[0:0]; _RAND_436 = {1{`RANDOM}}; - ic_tag_valid_out_0_125 = _RAND_436[0:0]; + ic_tag_valid_out_0_124 = _RAND_436[0:0]; _RAND_437 = {1{`RANDOM}}; - ic_tag_valid_out_0_126 = _RAND_437[0:0]; + ic_tag_valid_out_0_125 = _RAND_437[0:0]; _RAND_438 = {1{`RANDOM}}; - ic_tag_valid_out_0_127 = _RAND_438[0:0]; + ic_tag_valid_out_0_126 = _RAND_438[0:0]; _RAND_439 = {1{`RANDOM}}; - ic_debug_way_ff = _RAND_439[1:0]; + ic_tag_valid_out_0_127 = _RAND_439[0:0]; _RAND_440 = {1{`RANDOM}}; - ic_debug_rd_en_ff = _RAND_440[0:0]; - _RAND_441 = {3{`RANDOM}}; - _T_1212 = _RAND_441[70:0]; - _RAND_442 = {1{`RANDOM}}; - ifc_region_acc_fault_memory_f = _RAND_442[0:0]; + ic_debug_way_ff = _RAND_440[1:0]; + _RAND_441 = {1{`RANDOM}}; + ic_debug_rd_en_ff = _RAND_441[0:0]; + _RAND_442 = {3{`RANDOM}}; + _T_1212 = _RAND_442[70:0]; _RAND_443 = {1{`RANDOM}}; - perr_ic_index_ff = _RAND_443[6:0]; + ifc_region_acc_fault_memory_f = _RAND_443[0:0]; _RAND_444 = {1{`RANDOM}}; - dma_sb_err_state_ff = _RAND_444[0:0]; + perr_ic_index_ff = _RAND_444[6:0]; _RAND_445 = {1{`RANDOM}}; - bus_cmd_req_hold = _RAND_445[0:0]; + dma_sb_err_state_ff = _RAND_445[0:0]; _RAND_446 = {1{`RANDOM}}; - ifu_bus_cmd_valid = _RAND_446[0:0]; + bus_cmd_req_hold = _RAND_446[0:0]; _RAND_447 = {1{`RANDOM}}; - bus_cmd_beat_count = _RAND_447[2:0]; + ifu_bus_cmd_valid = _RAND_447[0:0]; _RAND_448 = {1{`RANDOM}}; - ifu_bus_arready_unq_ff = _RAND_448[0:0]; + bus_cmd_beat_count = _RAND_448[2:0]; _RAND_449 = {1{`RANDOM}}; - ifu_bus_arvalid_ff = _RAND_449[0:0]; + ifu_bus_arready_unq_ff = _RAND_449[0:0]; _RAND_450 = {1{`RANDOM}}; - ifc_dma_access_ok_prev = _RAND_450[0:0]; - _RAND_451 = {2{`RANDOM}}; - iccm_ecc_corr_data_ff = _RAND_451[38:0]; - _RAND_452 = {1{`RANDOM}}; - dma_mem_addr_ff = _RAND_452[1:0]; + ifu_bus_arvalid_ff = _RAND_450[0:0]; + _RAND_451 = {1{`RANDOM}}; + ifc_dma_access_ok_prev = _RAND_451[0:0]; + _RAND_452 = {2{`RANDOM}}; + iccm_ecc_corr_data_ff = _RAND_452[38:0]; _RAND_453 = {1{`RANDOM}}; - dma_mem_tag_ff = _RAND_453[2:0]; + dma_mem_addr_ff = _RAND_453[1:0]; _RAND_454 = {1{`RANDOM}}; - iccm_dma_rtag_temp = _RAND_454[2:0]; + dma_mem_tag_ff = _RAND_454[2:0]; _RAND_455 = {1{`RANDOM}}; - iccm_dma_rvalid_temp = _RAND_455[0:0]; + iccm_dma_rtag_temp = _RAND_455[2:0]; _RAND_456 = {1{`RANDOM}}; - iccm_dma_ecc_error = _RAND_456[0:0]; - _RAND_457 = {2{`RANDOM}}; - iccm_dma_rdata_temp = _RAND_457[63:0]; - _RAND_458 = {1{`RANDOM}}; - iccm_ecc_corr_index_ff = _RAND_458[13:0]; + iccm_dma_rvalid_temp = _RAND_456[0:0]; + _RAND_457 = {1{`RANDOM}}; + iccm_dma_ecc_error = _RAND_457[0:0]; + _RAND_458 = {2{`RANDOM}}; + iccm_dma_rdata_temp = _RAND_458[63:0]; _RAND_459 = {1{`RANDOM}}; - iccm_rd_ecc_single_err_ff = _RAND_459[0:0]; + iccm_ecc_corr_index_ff = _RAND_459[13:0]; _RAND_460 = {1{`RANDOM}}; - iccm_rw_addr_f = _RAND_460[13:0]; + iccm_rd_ecc_single_err_ff = _RAND_460[0:0]; _RAND_461 = {1{`RANDOM}}; - ifu_status_wr_addr_ff = _RAND_461[6:0]; + iccm_rw_addr_f = _RAND_461[13:0]; _RAND_462 = {1{`RANDOM}}; - way_status_wr_en_ff = _RAND_462[0:0]; + ifu_status_wr_addr_ff = _RAND_462[6:0]; _RAND_463 = {1{`RANDOM}}; - way_status_new_ff = _RAND_463[0:0]; + way_status_wr_en_ff = _RAND_463[0:0]; _RAND_464 = {1{`RANDOM}}; - ifu_tag_wren_ff = _RAND_464[1:0]; + way_status_new_ff = _RAND_464[0:0]; _RAND_465 = {1{`RANDOM}}; - ic_valid_ff = _RAND_465[0:0]; + ifu_tag_wren_ff = _RAND_465[1:0]; _RAND_466 = {1{`RANDOM}}; - _T_9799 = _RAND_466[0:0]; + ic_valid_ff = _RAND_466[0:0]; _RAND_467 = {1{`RANDOM}}; - _T_9800 = _RAND_467[0:0]; + _T_9799 = _RAND_467[0:0]; _RAND_468 = {1{`RANDOM}}; - _T_9801 = _RAND_468[0:0]; + _T_9800 = _RAND_468[0:0]; _RAND_469 = {1{`RANDOM}}; - _T_9805 = _RAND_469[0:0]; + _T_9801 = _RAND_469[0:0]; _RAND_470 = {1{`RANDOM}}; - _T_9806 = _RAND_470[0:0]; + _T_9805 = _RAND_470[0:0]; _RAND_471 = {1{`RANDOM}}; - _T_9826 = _RAND_471[0:0]; + _T_9806 = _RAND_471[0:0]; + _RAND_472 = {1{`RANDOM}}; + _T_9826 = _RAND_472[0:0]; `endif // RANDOMIZE_REG_INIT if (reset) begin flush_final_f = 1'h0; @@ -7434,6 +7442,9 @@ initial begin if (reset) begin fetch_uncacheable_ff = 1'h0; end + if (reset) begin + miss_addr = 26'h0; + end if (reset) begin ifc_region_acc_fault_f = 1'h0; end @@ -9636,6 +9647,15 @@ end // initial fetch_uncacheable_ff <= io_ifc_fetch_uncacheable_bf; end end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + miss_addr <= 26'h0; + end else if (_T_231) begin + miss_addr <= imb_ff[30:5]; + end else if (scnd_miss_req_q) begin + miss_addr <= imb_scnd_ff[30:5]; + end + end always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin if (reset) begin ifc_region_acc_fault_f <= 1'h0; @@ -44509,6 +44529,7 @@ module ifu( input io_ifu_ar_ready, output io_ifu_ar_valid, output [2:0] io_ifu_ar_bits_id, + output [31:0] io_ifu_ar_bits_addr, input io_ifu_r_valid, input [2:0] io_ifu_r_bits_id, input [63:0] io_ifu_r_bits_data, @@ -44566,6 +44587,7 @@ module ifu( wire mem_ctl_io_ifu_axi_ar_ready; // @[ifu.scala 34:23] wire mem_ctl_io_ifu_axi_ar_valid; // @[ifu.scala 34:23] wire [2:0] mem_ctl_io_ifu_axi_ar_bits_id; // @[ifu.scala 34:23] + wire [31:0] mem_ctl_io_ifu_axi_ar_bits_addr; // @[ifu.scala 34:23] wire mem_ctl_io_ifu_axi_r_ready; // @[ifu.scala 34:23] wire mem_ctl_io_ifu_axi_r_valid; // @[ifu.scala 34:23] wire [2:0] mem_ctl_io_ifu_axi_r_bits_id; // @[ifu.scala 34:23] @@ -44780,6 +44802,7 @@ module ifu( .io_ifu_axi_ar_ready(mem_ctl_io_ifu_axi_ar_ready), .io_ifu_axi_ar_valid(mem_ctl_io_ifu_axi_ar_valid), .io_ifu_axi_ar_bits_id(mem_ctl_io_ifu_axi_ar_bits_id), + .io_ifu_axi_ar_bits_addr(mem_ctl_io_ifu_axi_ar_bits_addr), .io_ifu_axi_r_ready(mem_ctl_io_ifu_axi_r_ready), .io_ifu_axi_r_valid(mem_ctl_io_ifu_axi_r_valid), .io_ifu_axi_r_bits_id(mem_ctl_io_ifu_axi_r_bits_id), @@ -45019,6 +45042,7 @@ module ifu( assign io_ic_sel_premux_data = mem_ctl_io_ic_sel_premux_data; // @[ifu.scala 106:17] assign io_ifu_ar_valid = mem_ctl_io_ifu_axi_ar_valid; // @[ifu.scala 103:22] assign io_ifu_ar_bits_id = mem_ctl_io_ifu_axi_ar_bits_id; // @[ifu.scala 103:22] + assign io_ifu_ar_bits_addr = mem_ctl_io_ifu_axi_ar_bits_addr; // @[ifu.scala 103:22] assign io_iccm_dma_ecc_error = mem_ctl_io_iccm_dma_ecc_error; // @[ifu.scala 113:25] assign io_iccm_dma_rvalid = mem_ctl_io_iccm_dma_rvalid; // @[ifu.scala 114:22] assign io_iccm_dma_rdata = mem_ctl_io_iccm_dma_rdata; // @[ifu.scala 115:21] @@ -50900,13 +50924,13 @@ module csr_tlu( wire _T_2 = ~io_rfpc_i0_r; // @[dec_tlu_ctl.scala 1451:68] wire _T_5 = io_dec_csr_wraddr_r == 12'h300; // @[dec_tlu_ctl.scala 1452:71] wire wr_mstatus_r = io_dec_csr_wen_r_mod & _T_5; // @[dec_tlu_ctl.scala 1452:42] - wire _T_498 = io_dec_csr_wraddr_r == 12'h7c6; // @[dec_tlu_ctl.scala 1838:68] - wire wr_mpmc_r = io_dec_csr_wen_r_mod & _T_498; // @[dec_tlu_ctl.scala 1838:39] - wire _T_510 = ~io_dec_csr_wrdata_r[1]; // @[dec_tlu_ctl.scala 1846:37] + wire _T_488 = io_dec_csr_wraddr_r == 12'h7c6; // @[dec_tlu_ctl.scala 1838:68] + wire wr_mpmc_r = io_dec_csr_wen_r_mod & _T_488; // @[dec_tlu_ctl.scala 1838:39] + wire _T_500 = ~io_dec_csr_wrdata_r[1]; // @[dec_tlu_ctl.scala 1846:37] reg mpmc_b; // @[dec_tlu_ctl.scala 1848:44] wire mpmc = ~mpmc_b; // @[dec_tlu_ctl.scala 1851:10] - wire _T_511 = ~mpmc; // @[dec_tlu_ctl.scala 1846:62] - wire mpmc_b_ns = wr_mpmc_r ? _T_510 : _T_511; // @[dec_tlu_ctl.scala 1846:18] + wire _T_501 = ~mpmc; // @[dec_tlu_ctl.scala 1846:62] + wire mpmc_b_ns = wr_mpmc_r ? _T_500 : _T_501; // @[dec_tlu_ctl.scala 1846:18] wire _T_6 = ~mpmc_b_ns; // @[dec_tlu_ctl.scala 1455:28] wire set_mie_pmu_fw_halt = _T_6 & io_fw_halt_req; // @[dec_tlu_ctl.scala 1455:39] wire _T_7 = ~wr_mstatus_r; // @[dec_tlu_ctl.scala 1458:5] @@ -50941,24 +50965,24 @@ module csr_tlu( wire _T_58 = io_dec_csr_wraddr_r == 12'h305; // @[dec_tlu_ctl.scala 1477:69] reg [30:0] _T_62; // @[lib.scala 374:16] reg [31:0] mdccmect; // @[lib.scala 374:16] - wire [62:0] _T_574 = 63'hffffffff << mdccmect[31:27]; // @[dec_tlu_ctl.scala 1898:41] - wire [31:0] _T_576 = {5'h0,mdccmect[26:0]}; // @[Cat.scala 29:58] - wire [62:0] _GEN_9 = {{31'd0}, _T_576}; // @[dec_tlu_ctl.scala 1898:61] - wire [62:0] _T_577 = _T_574 & _GEN_9; // @[dec_tlu_ctl.scala 1898:61] - wire mdccme_ce_req = |_T_577; // @[dec_tlu_ctl.scala 1898:94] + wire [62:0] _T_564 = 63'hffffffff << mdccmect[31:27]; // @[dec_tlu_ctl.scala 1898:41] + wire [31:0] _T_566 = {5'h0,mdccmect[26:0]}; // @[Cat.scala 29:58] + wire [62:0] _GEN_9 = {{31'd0}, _T_566}; // @[dec_tlu_ctl.scala 1898:61] + wire [62:0] _T_567 = _T_564 & _GEN_9; // @[dec_tlu_ctl.scala 1898:61] + wire mdccme_ce_req = |_T_567; // @[dec_tlu_ctl.scala 1898:94] reg [31:0] miccmect; // @[lib.scala 374:16] - wire [62:0] _T_554 = 63'hffffffff << miccmect[31:27]; // @[dec_tlu_ctl.scala 1883:40] - wire [31:0] _T_556 = {5'h0,miccmect[26:0]}; // @[Cat.scala 29:58] - wire [62:0] _GEN_10 = {{31'd0}, _T_556}; // @[dec_tlu_ctl.scala 1883:60] - wire [62:0] _T_557 = _T_554 & _GEN_10; // @[dec_tlu_ctl.scala 1883:60] - wire miccme_ce_req = |_T_557; // @[dec_tlu_ctl.scala 1883:93] + wire [62:0] _T_544 = 63'hffffffff << miccmect[31:27]; // @[dec_tlu_ctl.scala 1883:40] + wire [31:0] _T_546 = {5'h0,miccmect[26:0]}; // @[Cat.scala 29:58] + wire [62:0] _GEN_10 = {{31'd0}, _T_546}; // @[dec_tlu_ctl.scala 1883:60] + wire [62:0] _T_547 = _T_544 & _GEN_10; // @[dec_tlu_ctl.scala 1883:60] + wire miccme_ce_req = |_T_547; // @[dec_tlu_ctl.scala 1883:93] wire _T_63 = mdccme_ce_req | miccme_ce_req; // @[dec_tlu_ctl.scala 1491:30] reg [31:0] micect; // @[lib.scala 374:16] - wire [62:0] _T_532 = 63'hffffffff << micect[31:27]; // @[dec_tlu_ctl.scala 1868:39] - wire [31:0] _T_534 = {5'h0,micect[26:0]}; // @[Cat.scala 29:58] - wire [62:0] _GEN_11 = {{31'd0}, _T_534}; // @[dec_tlu_ctl.scala 1868:57] - wire [62:0] _T_535 = _T_532 & _GEN_11; // @[dec_tlu_ctl.scala 1868:57] - wire mice_ce_req = |_T_535; // @[dec_tlu_ctl.scala 1868:88] + wire [62:0] _T_522 = 63'hffffffff << micect[31:27]; // @[dec_tlu_ctl.scala 1868:39] + wire [31:0] _T_524 = {5'h0,micect[26:0]}; // @[Cat.scala 29:58] + wire [62:0] _GEN_11 = {{31'd0}, _T_524}; // @[dec_tlu_ctl.scala 1868:57] + wire [62:0] _T_525 = _T_522 & _GEN_11; // @[dec_tlu_ctl.scala 1868:57] + wire mice_ce_req = |_T_525; // @[dec_tlu_ctl.scala 1868:88] wire ce_int = _T_63 | mice_ce_req; // @[dec_tlu_ctl.scala 1491:46] wire [2:0] _T_65 = {io_mexintpend,io_timer_int_sync,io_soft_int_sync}; // @[Cat.scala 29:58] wire [2:0] _T_67 = {ce_int,io_dec_timer_t0_pulse,io_dec_timer_t1_pulse}; // @[Cat.scala 29:58] @@ -51150,423 +51174,429 @@ module csr_tlu( reg [8:0] mcgc; // @[lib.scala 374:16] wire _T_337 = io_dec_csr_wraddr_r == 12'h7f9; // @[dec_tlu_ctl.scala 1744:68] reg [14:0] mfdc_int; // @[lib.scala 374:16] - wire [2:0] _T_341 = ~io_dec_csr_wrdata_r[18:16]; // @[dec_tlu_ctl.scala 1753:20] - wire _T_344 = ~io_dec_csr_wrdata_r[6]; // @[dec_tlu_ctl.scala 1753:75] - wire [6:0] _T_346 = {_T_344,io_dec_csr_wrdata_r[5:0]}; // @[Cat.scala 29:58] - wire [7:0] _T_347 = {_T_341,io_dec_csr_wrdata_r[11:7]}; // @[Cat.scala 29:58] - wire [2:0] _T_350 = ~mfdc_int[14:12]; // @[dec_tlu_ctl.scala 1754:20] - wire _T_353 = ~mfdc_int[6]; // @[dec_tlu_ctl.scala 1754:63] - wire [18:0] mfdc = {_T_350,4'h0,mfdc_int[11:7],_T_353,mfdc_int[5:0]}; // @[Cat.scala 29:58] - wire _T_367 = io_dec_csr_wraddr_r == 12'h7c2; // @[dec_tlu_ctl.scala 1777:77] - wire _T_368 = io_dec_csr_wen_r_mod & _T_367; // @[dec_tlu_ctl.scala 1777:48] - wire _T_370 = _T_368 & _T_297; // @[dec_tlu_ctl.scala 1777:87] - wire _T_371 = ~io_take_ext_int_start; // @[dec_tlu_ctl.scala 1777:113] - wire _T_374 = io_dec_csr_wraddr_r == 12'h7c0; // @[dec_tlu_ctl.scala 1784:68] - wire _T_378 = ~io_dec_csr_wrdata_r[31]; // @[dec_tlu_ctl.scala 1787:71] - wire _T_379 = io_dec_csr_wrdata_r[30] & _T_378; // @[dec_tlu_ctl.scala 1787:69] - wire _T_383 = ~io_dec_csr_wrdata_r[29]; // @[dec_tlu_ctl.scala 1788:73] - wire _T_384 = io_dec_csr_wrdata_r[28] & _T_383; // @[dec_tlu_ctl.scala 1788:71] - wire _T_388 = ~io_dec_csr_wrdata_r[27]; // @[dec_tlu_ctl.scala 1789:73] - wire _T_389 = io_dec_csr_wrdata_r[26] & _T_388; // @[dec_tlu_ctl.scala 1789:71] - wire _T_393 = ~io_dec_csr_wrdata_r[25]; // @[dec_tlu_ctl.scala 1790:73] - wire _T_394 = io_dec_csr_wrdata_r[24] & _T_393; // @[dec_tlu_ctl.scala 1790:71] - wire _T_398 = ~io_dec_csr_wrdata_r[23]; // @[dec_tlu_ctl.scala 1791:73] - wire _T_399 = io_dec_csr_wrdata_r[22] & _T_398; // @[dec_tlu_ctl.scala 1791:71] - wire _T_403 = ~io_dec_csr_wrdata_r[21]; // @[dec_tlu_ctl.scala 1792:73] - wire _T_404 = io_dec_csr_wrdata_r[20] & _T_403; // @[dec_tlu_ctl.scala 1792:71] - wire _T_408 = ~io_dec_csr_wrdata_r[19]; // @[dec_tlu_ctl.scala 1793:73] - wire _T_409 = io_dec_csr_wrdata_r[18] & _T_408; // @[dec_tlu_ctl.scala 1793:71] - wire _T_413 = ~io_dec_csr_wrdata_r[17]; // @[dec_tlu_ctl.scala 1794:73] - wire _T_414 = io_dec_csr_wrdata_r[16] & _T_413; // @[dec_tlu_ctl.scala 1794:71] - wire _T_418 = ~io_dec_csr_wrdata_r[15]; // @[dec_tlu_ctl.scala 1795:73] - wire _T_419 = io_dec_csr_wrdata_r[14] & _T_418; // @[dec_tlu_ctl.scala 1795:71] - wire _T_423 = ~io_dec_csr_wrdata_r[13]; // @[dec_tlu_ctl.scala 1796:73] - wire _T_424 = io_dec_csr_wrdata_r[12] & _T_423; // @[dec_tlu_ctl.scala 1796:71] - wire _T_428 = ~io_dec_csr_wrdata_r[11]; // @[dec_tlu_ctl.scala 1797:73] - wire _T_429 = io_dec_csr_wrdata_r[10] & _T_428; // @[dec_tlu_ctl.scala 1797:71] - wire _T_433 = ~io_dec_csr_wrdata_r[9]; // @[dec_tlu_ctl.scala 1798:73] - wire _T_434 = io_dec_csr_wrdata_r[8] & _T_433; // @[dec_tlu_ctl.scala 1798:70] - wire _T_438 = ~io_dec_csr_wrdata_r[7]; // @[dec_tlu_ctl.scala 1799:73] - wire _T_439 = io_dec_csr_wrdata_r[6] & _T_438; // @[dec_tlu_ctl.scala 1799:70] - wire _T_443 = ~io_dec_csr_wrdata_r[5]; // @[dec_tlu_ctl.scala 1800:73] - wire _T_444 = io_dec_csr_wrdata_r[4] & _T_443; // @[dec_tlu_ctl.scala 1800:70] - wire _T_448 = ~io_dec_csr_wrdata_r[3]; // @[dec_tlu_ctl.scala 1801:73] - wire _T_449 = io_dec_csr_wrdata_r[2] & _T_448; // @[dec_tlu_ctl.scala 1801:70] - wire _T_454 = io_dec_csr_wrdata_r[0] & _T_510; // @[dec_tlu_ctl.scala 1802:70] - wire [7:0] _T_461 = {io_dec_csr_wrdata_r[7],_T_439,io_dec_csr_wrdata_r[5],_T_444,io_dec_csr_wrdata_r[3],_T_449,io_dec_csr_wrdata_r[1],_T_454}; // @[Cat.scala 29:58] - wire [15:0] _T_469 = {io_dec_csr_wrdata_r[15],_T_419,io_dec_csr_wrdata_r[13],_T_424,io_dec_csr_wrdata_r[11],_T_429,io_dec_csr_wrdata_r[9],_T_434,_T_461}; // @[Cat.scala 29:58] - wire [7:0] _T_476 = {io_dec_csr_wrdata_r[23],_T_399,io_dec_csr_wrdata_r[21],_T_404,io_dec_csr_wrdata_r[19],_T_409,io_dec_csr_wrdata_r[17],_T_414}; // @[Cat.scala 29:58] - wire [15:0] _T_484 = {io_dec_csr_wrdata_r[31],_T_379,io_dec_csr_wrdata_r[29],_T_384,io_dec_csr_wrdata_r[27],_T_389,io_dec_csr_wrdata_r[25],_T_394,_T_476}; // @[Cat.scala 29:58] + wire [2:0] _T_341 = ~io_dec_csr_wrdata_r[18:16]; // @[dec_tlu_ctl.scala 1757:19] + wire [2:0] _T_345 = ~mfdc_int[14:12]; // @[dec_tlu_ctl.scala 1758:19] + wire [18:0] mfdc = {_T_345,4'h0,mfdc_int[11:0]}; // @[Cat.scala 29:58] + wire _T_357 = io_dec_csr_wraddr_r == 12'h7c2; // @[dec_tlu_ctl.scala 1777:77] + wire _T_358 = io_dec_csr_wen_r_mod & _T_357; // @[dec_tlu_ctl.scala 1777:48] + wire _T_360 = _T_358 & _T_297; // @[dec_tlu_ctl.scala 1777:87] + wire _T_361 = ~io_take_ext_int_start; // @[dec_tlu_ctl.scala 1777:113] + wire _T_364 = io_dec_csr_wraddr_r == 12'h7c0; // @[dec_tlu_ctl.scala 1784:68] + wire _T_368 = ~io_dec_csr_wrdata_r[31]; // @[dec_tlu_ctl.scala 1787:71] + wire _T_369 = io_dec_csr_wrdata_r[30] & _T_368; // @[dec_tlu_ctl.scala 1787:69] + wire _T_373 = ~io_dec_csr_wrdata_r[29]; // @[dec_tlu_ctl.scala 1788:73] + wire _T_374 = io_dec_csr_wrdata_r[28] & _T_373; // @[dec_tlu_ctl.scala 1788:71] + wire _T_378 = ~io_dec_csr_wrdata_r[27]; // @[dec_tlu_ctl.scala 1789:73] + wire _T_379 = io_dec_csr_wrdata_r[26] & _T_378; // @[dec_tlu_ctl.scala 1789:71] + wire _T_383 = ~io_dec_csr_wrdata_r[25]; // @[dec_tlu_ctl.scala 1790:73] + wire _T_384 = io_dec_csr_wrdata_r[24] & _T_383; // @[dec_tlu_ctl.scala 1790:71] + wire _T_388 = ~io_dec_csr_wrdata_r[23]; // @[dec_tlu_ctl.scala 1791:73] + wire _T_389 = io_dec_csr_wrdata_r[22] & _T_388; // @[dec_tlu_ctl.scala 1791:71] + wire _T_393 = ~io_dec_csr_wrdata_r[21]; // @[dec_tlu_ctl.scala 1792:73] + wire _T_394 = io_dec_csr_wrdata_r[20] & _T_393; // @[dec_tlu_ctl.scala 1792:71] + wire _T_398 = ~io_dec_csr_wrdata_r[19]; // @[dec_tlu_ctl.scala 1793:73] + wire _T_399 = io_dec_csr_wrdata_r[18] & _T_398; // @[dec_tlu_ctl.scala 1793:71] + wire _T_403 = ~io_dec_csr_wrdata_r[17]; // @[dec_tlu_ctl.scala 1794:73] + wire _T_404 = io_dec_csr_wrdata_r[16] & _T_403; // @[dec_tlu_ctl.scala 1794:71] + wire _T_408 = ~io_dec_csr_wrdata_r[15]; // @[dec_tlu_ctl.scala 1795:73] + wire _T_409 = io_dec_csr_wrdata_r[14] & _T_408; // @[dec_tlu_ctl.scala 1795:71] + wire _T_413 = ~io_dec_csr_wrdata_r[13]; // @[dec_tlu_ctl.scala 1796:73] + wire _T_414 = io_dec_csr_wrdata_r[12] & _T_413; // @[dec_tlu_ctl.scala 1796:71] + wire _T_418 = ~io_dec_csr_wrdata_r[11]; // @[dec_tlu_ctl.scala 1797:73] + wire _T_419 = io_dec_csr_wrdata_r[10] & _T_418; // @[dec_tlu_ctl.scala 1797:71] + wire _T_423 = ~io_dec_csr_wrdata_r[9]; // @[dec_tlu_ctl.scala 1798:73] + wire _T_424 = io_dec_csr_wrdata_r[8] & _T_423; // @[dec_tlu_ctl.scala 1798:70] + wire _T_428 = ~io_dec_csr_wrdata_r[7]; // @[dec_tlu_ctl.scala 1799:73] + wire _T_429 = io_dec_csr_wrdata_r[6] & _T_428; // @[dec_tlu_ctl.scala 1799:70] + wire _T_433 = ~io_dec_csr_wrdata_r[5]; // @[dec_tlu_ctl.scala 1800:73] + wire _T_434 = io_dec_csr_wrdata_r[4] & _T_433; // @[dec_tlu_ctl.scala 1800:70] + wire _T_438 = ~io_dec_csr_wrdata_r[3]; // @[dec_tlu_ctl.scala 1801:73] + wire _T_439 = io_dec_csr_wrdata_r[2] & _T_438; // @[dec_tlu_ctl.scala 1801:70] + wire _T_444 = io_dec_csr_wrdata_r[0] & _T_500; // @[dec_tlu_ctl.scala 1802:70] + wire [7:0] _T_451 = {io_dec_csr_wrdata_r[7],_T_429,io_dec_csr_wrdata_r[5],_T_434,io_dec_csr_wrdata_r[3],_T_439,io_dec_csr_wrdata_r[1],_T_444}; // @[Cat.scala 29:58] + wire [15:0] _T_459 = {io_dec_csr_wrdata_r[15],_T_409,io_dec_csr_wrdata_r[13],_T_414,io_dec_csr_wrdata_r[11],_T_419,io_dec_csr_wrdata_r[9],_T_424,_T_451}; // @[Cat.scala 29:58] + wire [7:0] _T_466 = {io_dec_csr_wrdata_r[23],_T_389,io_dec_csr_wrdata_r[21],_T_394,io_dec_csr_wrdata_r[19],_T_399,io_dec_csr_wrdata_r[17],_T_404}; // @[Cat.scala 29:58] + wire [15:0] _T_474 = {io_dec_csr_wrdata_r[31],_T_369,io_dec_csr_wrdata_r[29],_T_374,io_dec_csr_wrdata_r[27],_T_379,io_dec_csr_wrdata_r[25],_T_384,_T_466}; // @[Cat.scala 29:58] reg [31:0] mrac; // @[lib.scala 374:16] - wire _T_487 = io_dec_csr_wraddr_r == 12'hbc0; // @[dec_tlu_ctl.scala 1815:69] - wire wr_mdeau_r = io_dec_csr_wen_r_mod & _T_487; // @[dec_tlu_ctl.scala 1815:40] - wire _T_488 = ~wr_mdeau_r; // @[dec_tlu_ctl.scala 1825:59] - wire _T_489 = io_mdseac_locked_f & _T_488; // @[dec_tlu_ctl.scala 1825:57] - wire _T_491 = io_lsu_imprecise_error_store_any | io_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 1827:49] - wire _T_492 = ~io_nmi_int_detected_f; // @[dec_tlu_ctl.scala 1827:86] - wire _T_493 = _T_491 & _T_492; // @[dec_tlu_ctl.scala 1827:84] - wire _T_494 = ~io_mdseac_locked_f; // @[dec_tlu_ctl.scala 1827:111] - wire mdseac_en = _T_493 & _T_494; // @[dec_tlu_ctl.scala 1827:109] + wire _T_477 = io_dec_csr_wraddr_r == 12'hbc0; // @[dec_tlu_ctl.scala 1815:69] + wire wr_mdeau_r = io_dec_csr_wen_r_mod & _T_477; // @[dec_tlu_ctl.scala 1815:40] + wire _T_478 = ~wr_mdeau_r; // @[dec_tlu_ctl.scala 1825:59] + wire _T_479 = io_mdseac_locked_f & _T_478; // @[dec_tlu_ctl.scala 1825:57] + wire _T_481 = io_lsu_imprecise_error_store_any | io_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 1827:49] + wire _T_482 = ~io_nmi_int_detected_f; // @[dec_tlu_ctl.scala 1827:86] + wire _T_483 = _T_481 & _T_482; // @[dec_tlu_ctl.scala 1827:84] + wire _T_484 = ~io_mdseac_locked_f; // @[dec_tlu_ctl.scala 1827:111] + wire mdseac_en = _T_483 & _T_484; // @[dec_tlu_ctl.scala 1827:109] reg [31:0] mdseac; // @[lib.scala 374:16] - wire _T_500 = wr_mpmc_r & io_dec_csr_wrdata_r[0]; // @[dec_tlu_ctl.scala 1842:30] - wire _T_501 = ~io_internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 1842:57] - wire _T_502 = _T_500 & _T_501; // @[dec_tlu_ctl.scala 1842:55] - wire _T_503 = ~io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 1842:89] - wire _T_516 = io_dec_csr_wrdata_r[31:27] > 5'h1a; // @[dec_tlu_ctl.scala 1860:48] - wire [4:0] csr_sat = _T_516 ? 5'h1a : io_dec_csr_wrdata_r[31:27]; // @[dec_tlu_ctl.scala 1860:19] - wire _T_519 = io_dec_csr_wraddr_r == 12'h7f0; // @[dec_tlu_ctl.scala 1862:70] - wire wr_micect_r = io_dec_csr_wen_r_mod & _T_519; // @[dec_tlu_ctl.scala 1862:41] - wire [26:0] _T_520 = {26'h0,io_ic_perr_r_d1}; // @[Cat.scala 29:58] - wire [31:0] _GEN_14 = {{5'd0}, _T_520}; // @[dec_tlu_ctl.scala 1863:23] - wire [31:0] _T_522 = micect + _GEN_14; // @[dec_tlu_ctl.scala 1863:23] - wire [31:0] _T_525 = {csr_sat,io_dec_csr_wrdata_r[26:0]}; // @[Cat.scala 29:58] - wire [26:0] micect_inc = _T_522[26:0]; // @[dec_tlu_ctl.scala 1863:13] - wire [31:0] _T_527 = {micect[31:27],micect_inc}; // @[Cat.scala 29:58] - wire _T_538 = io_dec_csr_wraddr_r == 12'h7f1; // @[dec_tlu_ctl.scala 1877:76] - wire wr_miccmect_r = io_dec_csr_wen_r_mod & _T_538; // @[dec_tlu_ctl.scala 1877:47] - wire _T_540 = io_iccm_sbecc_r_d1 | io_iccm_dma_sb_error; // @[dec_tlu_ctl.scala 1878:70] - wire [26:0] _T_541 = {26'h0,_T_540}; // @[Cat.scala 29:58] - wire [26:0] miccmect_inc = miccmect[26:0] + _T_541; // @[dec_tlu_ctl.scala 1878:33] - wire [31:0] _T_548 = {miccmect[31:27],miccmect_inc}; // @[Cat.scala 29:58] - wire _T_549 = wr_miccmect_r | io_iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 1881:48] - wire _T_560 = io_dec_csr_wraddr_r == 12'h7f2; // @[dec_tlu_ctl.scala 1892:76] - wire wr_mdccmect_r = io_dec_csr_wen_r_mod & _T_560; // @[dec_tlu_ctl.scala 1892:47] - wire [26:0] _T_562 = {26'h0,io_lsu_single_ecc_error_r_d1}; // @[Cat.scala 29:58] - wire [26:0] mdccmect_inc = mdccmect[26:0] + _T_562; // @[dec_tlu_ctl.scala 1893:33] - wire [31:0] _T_569 = {mdccmect[31:27],mdccmect_inc}; // @[Cat.scala 29:58] - wire _T_580 = io_dec_csr_wraddr_r == 12'h7ce; // @[dec_tlu_ctl.scala 1908:69] - wire wr_mfdht_r = io_dec_csr_wen_r_mod & _T_580; // @[dec_tlu_ctl.scala 1908:40] + wire _T_490 = wr_mpmc_r & io_dec_csr_wrdata_r[0]; // @[dec_tlu_ctl.scala 1842:30] + wire _T_491 = ~io_internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 1842:57] + wire _T_492 = _T_490 & _T_491; // @[dec_tlu_ctl.scala 1842:55] + wire _T_493 = ~io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 1842:89] + wire _T_506 = io_dec_csr_wrdata_r[31:27] > 5'h1a; // @[dec_tlu_ctl.scala 1860:48] + wire [4:0] csr_sat = _T_506 ? 5'h1a : io_dec_csr_wrdata_r[31:27]; // @[dec_tlu_ctl.scala 1860:19] + wire _T_509 = io_dec_csr_wraddr_r == 12'h7f0; // @[dec_tlu_ctl.scala 1862:70] + wire wr_micect_r = io_dec_csr_wen_r_mod & _T_509; // @[dec_tlu_ctl.scala 1862:41] + wire [26:0] _T_510 = {26'h0,io_ic_perr_r_d1}; // @[Cat.scala 29:58] + wire [31:0] _GEN_14 = {{5'd0}, _T_510}; // @[dec_tlu_ctl.scala 1863:23] + wire [31:0] _T_512 = micect + _GEN_14; // @[dec_tlu_ctl.scala 1863:23] + wire [31:0] _T_515 = {csr_sat,io_dec_csr_wrdata_r[26:0]}; // @[Cat.scala 29:58] + wire [26:0] micect_inc = _T_512[26:0]; // @[dec_tlu_ctl.scala 1863:13] + wire [31:0] _T_517 = {micect[31:27],micect_inc}; // @[Cat.scala 29:58] + wire _T_528 = io_dec_csr_wraddr_r == 12'h7f1; // @[dec_tlu_ctl.scala 1877:76] + wire wr_miccmect_r = io_dec_csr_wen_r_mod & _T_528; // @[dec_tlu_ctl.scala 1877:47] + wire _T_530 = io_iccm_sbecc_r_d1 | io_iccm_dma_sb_error; // @[dec_tlu_ctl.scala 1878:70] + wire [26:0] _T_531 = {26'h0,_T_530}; // @[Cat.scala 29:58] + wire [26:0] miccmect_inc = miccmect[26:0] + _T_531; // @[dec_tlu_ctl.scala 1878:33] + wire [31:0] _T_538 = {miccmect[31:27],miccmect_inc}; // @[Cat.scala 29:58] + wire _T_539 = wr_miccmect_r | io_iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 1881:48] + wire _T_550 = io_dec_csr_wraddr_r == 12'h7f2; // @[dec_tlu_ctl.scala 1892:76] + wire wr_mdccmect_r = io_dec_csr_wen_r_mod & _T_550; // @[dec_tlu_ctl.scala 1892:47] + wire [26:0] _T_552 = {26'h0,io_lsu_single_ecc_error_r_d1}; // @[Cat.scala 29:58] + wire [26:0] mdccmect_inc = mdccmect[26:0] + _T_552; // @[dec_tlu_ctl.scala 1893:33] + wire [31:0] _T_559 = {mdccmect[31:27],mdccmect_inc}; // @[Cat.scala 29:58] + wire _T_570 = io_dec_csr_wraddr_r == 12'h7ce; // @[dec_tlu_ctl.scala 1908:69] + wire wr_mfdht_r = io_dec_csr_wen_r_mod & _T_570; // @[dec_tlu_ctl.scala 1908:40] reg [5:0] mfdht; // @[dec_tlu_ctl.scala 1912:43] - wire _T_585 = io_dec_csr_wraddr_r == 12'h7cf; // @[dec_tlu_ctl.scala 1921:69] - wire wr_mfdhs_r = io_dec_csr_wen_r_mod & _T_585; // @[dec_tlu_ctl.scala 1921:40] - wire _T_588 = ~io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 1924:43] - wire _T_589 = io_dbg_tlu_halted & _T_588; // @[dec_tlu_ctl.scala 1924:41] - wire _T_591 = ~io_lsu_idle_any_f; // @[dec_tlu_ctl.scala 1924:78] - wire _T_592 = ~io_ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 1924:98] - wire [1:0] _T_593 = {_T_591,_T_592}; // @[Cat.scala 29:58] + wire _T_575 = io_dec_csr_wraddr_r == 12'h7cf; // @[dec_tlu_ctl.scala 1921:69] + wire wr_mfdhs_r = io_dec_csr_wen_r_mod & _T_575; // @[dec_tlu_ctl.scala 1921:40] + wire _T_578 = ~io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 1924:43] + wire _T_579 = io_dbg_tlu_halted & _T_578; // @[dec_tlu_ctl.scala 1924:41] + wire _T_581 = ~io_lsu_idle_any_f; // @[dec_tlu_ctl.scala 1924:78] + wire _T_582 = ~io_ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 1924:98] + wire [1:0] _T_583 = {_T_581,_T_582}; // @[Cat.scala 29:58] reg [1:0] mfdhs; // @[Reg.scala 27:20] - wire _T_595 = wr_mfdhs_r | io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 1926:71] + wire _T_585 = wr_mfdhs_r | io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 1926:71] reg [31:0] force_halt_ctr_f; // @[Reg.scala 27:20] - wire [31:0] _T_600 = force_halt_ctr_f + 32'h1; // @[dec_tlu_ctl.scala 1928:74] - wire [62:0] _T_607 = 63'hffffffff << mfdht[5:1]; // @[dec_tlu_ctl.scala 1933:71] + wire [31:0] _T_590 = force_halt_ctr_f + 32'h1; // @[dec_tlu_ctl.scala 1928:74] + wire [62:0] _T_597 = 63'hffffffff << mfdht[5:1]; // @[dec_tlu_ctl.scala 1933:71] wire [62:0] _GEN_15 = {{31'd0}, force_halt_ctr_f}; // @[dec_tlu_ctl.scala 1933:48] - wire [62:0] _T_608 = _GEN_15 & _T_607; // @[dec_tlu_ctl.scala 1933:48] - wire _T_609 = |_T_608; // @[dec_tlu_ctl.scala 1933:87] - wire _T_612 = io_dec_csr_wraddr_r == 12'hbc8; // @[dec_tlu_ctl.scala 1941:69] + wire [62:0] _T_598 = _GEN_15 & _T_597; // @[dec_tlu_ctl.scala 1933:48] + wire _T_599 = |_T_598; // @[dec_tlu_ctl.scala 1933:87] + wire _T_602 = io_dec_csr_wraddr_r == 12'hbc8; // @[dec_tlu_ctl.scala 1941:69] reg [21:0] meivt; // @[lib.scala 374:16] - wire _T_631 = io_dec_csr_wraddr_r == 12'hbca; // @[dec_tlu_ctl.scala 1992:69] - wire _T_632 = io_dec_csr_wen_r_mod & _T_631; // @[dec_tlu_ctl.scala 1992:40] - wire wr_meicpct_r = _T_632 | io_take_ext_int_start; // @[dec_tlu_ctl.scala 1992:83] + wire _T_621 = io_dec_csr_wraddr_r == 12'hbca; // @[dec_tlu_ctl.scala 1992:69] + wire _T_622 = io_dec_csr_wen_r_mod & _T_621; // @[dec_tlu_ctl.scala 1992:40] + wire wr_meicpct_r = _T_622 | io_take_ext_int_start; // @[dec_tlu_ctl.scala 1992:83] reg [7:0] meihap; // @[lib.scala 374:16] - wire _T_618 = io_dec_csr_wraddr_r == 12'hbcc; // @[dec_tlu_ctl.scala 1965:72] - wire wr_meicurpl_r = io_dec_csr_wen_r_mod & _T_618; // @[dec_tlu_ctl.scala 1965:43] + wire _T_608 = io_dec_csr_wraddr_r == 12'hbcc; // @[dec_tlu_ctl.scala 1965:72] + wire wr_meicurpl_r = io_dec_csr_wen_r_mod & _T_608; // @[dec_tlu_ctl.scala 1965:43] reg [3:0] meicurpl; // @[dec_tlu_ctl.scala 1968:46] - wire _T_623 = io_dec_csr_wraddr_r == 12'hbcb; // @[dec_tlu_ctl.scala 1980:73] - wire _T_624 = io_dec_csr_wen_r_mod & _T_623; // @[dec_tlu_ctl.scala 1980:44] - wire wr_meicidpl_r = _T_624 | io_take_ext_int_start; // @[dec_tlu_ctl.scala 1980:88] + wire _T_613 = io_dec_csr_wraddr_r == 12'hbcb; // @[dec_tlu_ctl.scala 1980:73] + wire _T_614 = io_dec_csr_wen_r_mod & _T_613; // @[dec_tlu_ctl.scala 1980:44] + wire wr_meicidpl_r = _T_614 | io_take_ext_int_start; // @[dec_tlu_ctl.scala 1980:88] reg [3:0] meicidpl; // @[dec_tlu_ctl.scala 1985:44] - wire _T_635 = io_dec_csr_wraddr_r == 12'hbc9; // @[dec_tlu_ctl.scala 2001:69] - wire wr_meipt_r = io_dec_csr_wen_r_mod & _T_635; // @[dec_tlu_ctl.scala 2001:40] + wire _T_625 = io_dec_csr_wraddr_r == 12'hbc9; // @[dec_tlu_ctl.scala 2001:69] + wire wr_meipt_r = io_dec_csr_wen_r_mod & _T_625; // @[dec_tlu_ctl.scala 2001:40] reg [3:0] meipt; // @[dec_tlu_ctl.scala 2004:43] - wire _T_639 = io_trigger_hit_r_d1 & io_dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 2032:89] - wire trigger_hit_for_dscr_cause_r_d1 = io_trigger_hit_dmode_r_d1 | _T_639; // @[dec_tlu_ctl.scala 2032:66] - wire _T_640 = ~io_ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 2035:31] - wire _T_641 = io_dcsr_single_step_done_f & _T_640; // @[dec_tlu_ctl.scala 2035:29] - wire _T_642 = ~trigger_hit_for_dscr_cause_r_d1; // @[dec_tlu_ctl.scala 2035:63] - wire _T_643 = _T_641 & _T_642; // @[dec_tlu_ctl.scala 2035:61] - wire _T_644 = ~io_debug_halt_req; // @[dec_tlu_ctl.scala 2035:98] - wire _T_645 = _T_643 & _T_644; // @[dec_tlu_ctl.scala 2035:96] - wire _T_648 = io_debug_halt_req & _T_640; // @[dec_tlu_ctl.scala 2036:46] - wire _T_650 = _T_648 & _T_642; // @[dec_tlu_ctl.scala 2036:78] - wire _T_653 = io_ebreak_to_debug_mode_r_d1 & _T_642; // @[dec_tlu_ctl.scala 2037:75] - wire [2:0] _T_656 = _T_645 ? 3'h4 : 3'h0; // @[Mux.scala 27:72] - wire [2:0] _T_657 = _T_650 ? 3'h3 : 3'h0; // @[Mux.scala 27:72] - wire [2:0] _T_658 = _T_653 ? 3'h1 : 3'h0; // @[Mux.scala 27:72] - wire [2:0] _T_659 = trigger_hit_for_dscr_cause_r_d1 ? 3'h2 : 3'h0; // @[Mux.scala 27:72] - wire [2:0] _T_660 = _T_656 | _T_657; // @[Mux.scala 27:72] - wire [2:0] _T_661 = _T_660 | _T_658; // @[Mux.scala 27:72] - wire [2:0] dcsr_cause = _T_661 | _T_659; // @[Mux.scala 27:72] - wire _T_663 = io_allow_dbg_halt_csr_write & io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 2040:46] - wire _T_665 = io_dec_csr_wraddr_r == 12'h7b0; // @[dec_tlu_ctl.scala 2040:98] - wire wr_dcsr_r = _T_663 & _T_665; // @[dec_tlu_ctl.scala 2040:69] - wire _T_667 = io_dcsr[8:6] == 3'h3; // @[dec_tlu_ctl.scala 2046:75] - wire dcsr_cause_upgradeable = io_internal_dbg_halt_mode_f & _T_667; // @[dec_tlu_ctl.scala 2046:59] - wire _T_668 = ~io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 2047:59] - wire _T_669 = _T_668 | dcsr_cause_upgradeable; // @[dec_tlu_ctl.scala 2047:78] - wire enter_debug_halt_req_le = io_enter_debug_halt_req & _T_669; // @[dec_tlu_ctl.scala 2047:56] + wire _T_629 = io_trigger_hit_r_d1 & io_dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 2032:89] + wire trigger_hit_for_dscr_cause_r_d1 = io_trigger_hit_dmode_r_d1 | _T_629; // @[dec_tlu_ctl.scala 2032:66] + wire _T_630 = ~io_ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 2035:31] + wire _T_631 = io_dcsr_single_step_done_f & _T_630; // @[dec_tlu_ctl.scala 2035:29] + wire _T_632 = ~trigger_hit_for_dscr_cause_r_d1; // @[dec_tlu_ctl.scala 2035:63] + wire _T_633 = _T_631 & _T_632; // @[dec_tlu_ctl.scala 2035:61] + wire _T_634 = ~io_debug_halt_req; // @[dec_tlu_ctl.scala 2035:98] + wire _T_635 = _T_633 & _T_634; // @[dec_tlu_ctl.scala 2035:96] + wire _T_638 = io_debug_halt_req & _T_630; // @[dec_tlu_ctl.scala 2036:46] + wire _T_640 = _T_638 & _T_632; // @[dec_tlu_ctl.scala 2036:78] + wire _T_643 = io_ebreak_to_debug_mode_r_d1 & _T_632; // @[dec_tlu_ctl.scala 2037:75] + wire [2:0] _T_646 = _T_635 ? 3'h4 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_647 = _T_640 ? 3'h3 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_648 = _T_643 ? 3'h1 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_649 = trigger_hit_for_dscr_cause_r_d1 ? 3'h2 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_650 = _T_646 | _T_647; // @[Mux.scala 27:72] + wire [2:0] _T_651 = _T_650 | _T_648; // @[Mux.scala 27:72] + wire [2:0] dcsr_cause = _T_651 | _T_649; // @[Mux.scala 27:72] + wire _T_653 = io_allow_dbg_halt_csr_write & io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 2040:46] + wire _T_655 = io_dec_csr_wraddr_r == 12'h7b0; // @[dec_tlu_ctl.scala 2040:98] + wire wr_dcsr_r = _T_653 & _T_655; // @[dec_tlu_ctl.scala 2040:69] + wire _T_657 = io_dcsr[8:6] == 3'h3; // @[dec_tlu_ctl.scala 2046:75] + wire dcsr_cause_upgradeable = io_internal_dbg_halt_mode_f & _T_657; // @[dec_tlu_ctl.scala 2046:59] + wire _T_658 = ~io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 2047:59] + wire _T_659 = _T_658 | dcsr_cause_upgradeable; // @[dec_tlu_ctl.scala 2047:78] + wire enter_debug_halt_req_le = io_enter_debug_halt_req & _T_659; // @[dec_tlu_ctl.scala 2047:56] wire nmi_in_debug_mode = io_nmi_int_detected_f & io_internal_dbg_halt_mode_f; // @[dec_tlu_ctl.scala 2049:48] - wire [15:0] _T_675 = {io_dcsr[15:9],dcsr_cause,io_dcsr[5:2],2'h3}; // @[Cat.scala 29:58] - wire _T_681 = nmi_in_debug_mode | io_dcsr[3]; // @[dec_tlu_ctl.scala 2051:145] - wire [15:0] _T_690 = {io_dec_csr_wrdata_r[15],3'h0,io_dec_csr_wrdata_r[11:10],1'h0,io_dcsr[8:6],2'h0,_T_681,io_dec_csr_wrdata_r[2],2'h3}; // @[Cat.scala 29:58] - wire [15:0] _T_695 = {io_dcsr[15:4],nmi_in_debug_mode,io_dcsr[2],2'h3}; // @[Cat.scala 29:58] - wire _T_697 = enter_debug_halt_req_le | wr_dcsr_r; // @[dec_tlu_ctl.scala 2053:54] - wire _T_698 = _T_697 | io_internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 2053:66] - reg [15:0] _T_701; // @[lib.scala 374:16] - wire _T_704 = io_dec_csr_wraddr_r == 12'h7b1; // @[dec_tlu_ctl.scala 2061:97] - wire wr_dpc_r = _T_663 & _T_704; // @[dec_tlu_ctl.scala 2061:68] - wire _T_707 = ~io_request_debug_mode_done; // @[dec_tlu_ctl.scala 2062:67] - wire dpc_capture_npc = _T_589 & _T_707; // @[dec_tlu_ctl.scala 2062:65] - wire _T_708 = ~io_request_debug_mode_r; // @[dec_tlu_ctl.scala 2066:21] - wire _T_709 = ~dpc_capture_npc; // @[dec_tlu_ctl.scala 2066:39] - wire _T_710 = _T_708 & _T_709; // @[dec_tlu_ctl.scala 2066:37] - wire _T_711 = _T_710 & wr_dpc_r; // @[dec_tlu_ctl.scala 2066:56] - wire _T_716 = _T_708 & dpc_capture_npc; // @[dec_tlu_ctl.scala 2068:49] - wire [30:0] _T_718 = _T_711 ? io_dec_csr_wrdata_r[31:1] : 31'h0; // @[Mux.scala 27:72] - wire [30:0] _T_719 = io_request_debug_mode_r ? pc_r : 31'h0; // @[Mux.scala 27:72] - wire [30:0] _T_720 = _T_716 ? io_npc_r : 31'h0; // @[Mux.scala 27:72] - wire [30:0] _T_721 = _T_718 | _T_719; // @[Mux.scala 27:72] - wire _T_723 = wr_dpc_r | io_request_debug_mode_r; // @[dec_tlu_ctl.scala 2070:36] - reg [30:0] _T_726; // @[lib.scala 374:16] - wire [2:0] _T_730 = {io_dec_csr_wrdata_r[24],io_dec_csr_wrdata_r[21:20]}; // @[Cat.scala 29:58] - wire _T_733 = io_dec_csr_wraddr_r == 12'h7c8; // @[dec_tlu_ctl.scala 2085:102] + wire [15:0] _T_665 = {io_dcsr[15:9],dcsr_cause,io_dcsr[5:2],2'h3}; // @[Cat.scala 29:58] + wire _T_671 = nmi_in_debug_mode | io_dcsr[3]; // @[dec_tlu_ctl.scala 2051:145] + wire [15:0] _T_680 = {io_dec_csr_wrdata_r[15],3'h0,io_dec_csr_wrdata_r[11:10],1'h0,io_dcsr[8:6],2'h0,_T_671,io_dec_csr_wrdata_r[2],2'h3}; // @[Cat.scala 29:58] + wire [15:0] _T_685 = {io_dcsr[15:4],nmi_in_debug_mode,io_dcsr[2],2'h3}; // @[Cat.scala 29:58] + wire _T_687 = enter_debug_halt_req_le | wr_dcsr_r; // @[dec_tlu_ctl.scala 2053:54] + wire _T_688 = _T_687 | io_internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 2053:66] + reg [15:0] _T_691; // @[lib.scala 374:16] + wire _T_694 = io_dec_csr_wraddr_r == 12'h7b1; // @[dec_tlu_ctl.scala 2061:97] + wire wr_dpc_r = _T_653 & _T_694; // @[dec_tlu_ctl.scala 2061:68] + wire _T_697 = ~io_request_debug_mode_done; // @[dec_tlu_ctl.scala 2062:67] + wire dpc_capture_npc = _T_579 & _T_697; // @[dec_tlu_ctl.scala 2062:65] + wire _T_698 = ~io_request_debug_mode_r; // @[dec_tlu_ctl.scala 2066:21] + wire _T_699 = ~dpc_capture_npc; // @[dec_tlu_ctl.scala 2066:39] + wire _T_700 = _T_698 & _T_699; // @[dec_tlu_ctl.scala 2066:37] + wire _T_701 = _T_700 & wr_dpc_r; // @[dec_tlu_ctl.scala 2066:56] + wire _T_706 = _T_698 & dpc_capture_npc; // @[dec_tlu_ctl.scala 2068:49] + wire [30:0] _T_708 = _T_701 ? io_dec_csr_wrdata_r[31:1] : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_709 = io_request_debug_mode_r ? pc_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_710 = _T_706 ? io_npc_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_711 = _T_708 | _T_709; // @[Mux.scala 27:72] + wire _T_713 = wr_dpc_r | io_request_debug_mode_r; // @[dec_tlu_ctl.scala 2070:36] + reg [30:0] _T_716; // @[lib.scala 374:16] + wire [2:0] _T_720 = {io_dec_csr_wrdata_r[24],io_dec_csr_wrdata_r[21:20]}; // @[Cat.scala 29:58] + wire _T_723 = io_dec_csr_wraddr_r == 12'h7c8; // @[dec_tlu_ctl.scala 2085:102] reg [16:0] dicawics; // @[lib.scala 374:16] - wire _T_737 = io_dec_csr_wraddr_r == 12'h7c9; // @[dec_tlu_ctl.scala 2103:100] - wire wr_dicad0_r = _T_663 & _T_737; // @[dec_tlu_ctl.scala 2103:71] + wire _T_727 = io_dec_csr_wraddr_r == 12'h7c9; // @[dec_tlu_ctl.scala 2103:100] + wire wr_dicad0_r = _T_653 & _T_727; // @[dec_tlu_ctl.scala 2103:71] reg [70:0] dicad0; // @[lib.scala 374:16] - wire _T_743 = io_dec_csr_wraddr_r == 12'h7cc; // @[dec_tlu_ctl.scala 2116:101] - wire wr_dicad0h_r = _T_663 & _T_743; // @[dec_tlu_ctl.scala 2116:72] + wire _T_733 = io_dec_csr_wraddr_r == 12'h7cc; // @[dec_tlu_ctl.scala 2116:101] + wire wr_dicad0h_r = _T_653 & _T_733; // @[dec_tlu_ctl.scala 2116:72] reg [31:0] dicad0h; // @[lib.scala 374:16] - wire _T_751 = io_dec_csr_wraddr_r == 12'h7ca; // @[dec_tlu_ctl.scala 2128:100] - wire _T_752 = _T_663 & _T_751; // @[dec_tlu_ctl.scala 2128:71] - wire _T_757 = _T_752 | io_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 2132:78] - reg [6:0] _T_759; // @[Reg.scala 27:20] - wire [31:0] dicad1 = {25'h0,_T_759}; // @[Cat.scala 29:58] - wire [38:0] _T_764 = {dicad1[6:0],dicad0h}; // @[Cat.scala 29:58] - wire _T_766 = io_allow_dbg_halt_csr_write & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 2160:52] - wire _T_767 = _T_766 & io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 2160:75] - wire _T_768 = ~io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 2160:98] - wire _T_769 = _T_767 & _T_768; // @[dec_tlu_ctl.scala 2160:96] - wire _T_771 = io_dec_csr_rdaddr_d == 12'h7cb; // @[dec_tlu_ctl.scala 2160:149] - wire _T_774 = io_dec_csr_wraddr_r == 12'h7cb; // @[dec_tlu_ctl.scala 2161:104] + wire _T_741 = io_dec_csr_wraddr_r == 12'h7ca; // @[dec_tlu_ctl.scala 2128:100] + wire _T_742 = _T_653 & _T_741; // @[dec_tlu_ctl.scala 2128:71] + wire _T_747 = _T_742 | io_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 2132:78] + reg [6:0] _T_749; // @[Reg.scala 27:20] + wire [31:0] dicad1 = {25'h0,_T_749}; // @[Cat.scala 29:58] + wire [38:0] _T_754 = {dicad1[6:0],dicad0h}; // @[Cat.scala 29:58] + wire _T_756 = io_allow_dbg_halt_csr_write & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 2160:52] + wire _T_757 = _T_756 & io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 2160:75] + wire _T_758 = ~io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 2160:98] + wire _T_759 = _T_757 & _T_758; // @[dec_tlu_ctl.scala 2160:96] + wire _T_761 = io_dec_csr_rdaddr_d == 12'h7cb; // @[dec_tlu_ctl.scala 2160:149] + wire _T_764 = io_dec_csr_wraddr_r == 12'h7cb; // @[dec_tlu_ctl.scala 2161:104] reg icache_rd_valid_f; // @[dec_tlu_ctl.scala 2163:58] reg icache_wr_valid_f; // @[dec_tlu_ctl.scala 2164:58] - wire _T_776 = io_dec_csr_wraddr_r == 12'h7a0; // @[dec_tlu_ctl.scala 2175:69] - wire wr_mtsel_r = io_dec_csr_wen_r_mod & _T_776; // @[dec_tlu_ctl.scala 2175:40] + wire _T_766 = io_dec_csr_wraddr_r == 12'h7a0; // @[dec_tlu_ctl.scala 2175:69] + wire wr_mtsel_r = io_dec_csr_wen_r_mod & _T_766; // @[dec_tlu_ctl.scala 2175:40] reg [1:0] mtsel; // @[dec_tlu_ctl.scala 2178:43] - wire tdata_load = io_dec_csr_wrdata_r[0] & _T_408; // @[dec_tlu_ctl.scala 2213:42] - wire tdata_opcode = io_dec_csr_wrdata_r[2] & _T_408; // @[dec_tlu_ctl.scala 2215:44] - wire _T_787 = io_dec_csr_wrdata_r[27] & io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2217:46] - wire tdata_action = _T_787 & io_dec_csr_wrdata_r[12]; // @[dec_tlu_ctl.scala 2217:69] - wire [9:0] tdata_wrdata_r = {_T_787,io_dec_csr_wrdata_r[20:19],tdata_action,io_dec_csr_wrdata_r[11],io_dec_csr_wrdata_r[7:6],tdata_opcode,io_dec_csr_wrdata_r[1],tdata_load}; // @[Cat.scala 29:58] - wire _T_802 = io_dec_csr_wraddr_r == 12'h7a1; // @[dec_tlu_ctl.scala 2223:99] - wire _T_803 = io_dec_csr_wen_r_mod & _T_802; // @[dec_tlu_ctl.scala 2223:70] - wire _T_804 = mtsel == 2'h0; // @[dec_tlu_ctl.scala 2223:121] - wire _T_805 = _T_803 & _T_804; // @[dec_tlu_ctl.scala 2223:112] - wire _T_807 = ~io_mtdata1_t_0[9]; // @[dec_tlu_ctl.scala 2223:138] - wire _T_808 = _T_807 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2223:170] - wire wr_mtdata1_t_r_0 = _T_805 & _T_808; // @[dec_tlu_ctl.scala 2223:135] - wire _T_813 = mtsel == 2'h1; // @[dec_tlu_ctl.scala 2223:121] - wire _T_814 = _T_803 & _T_813; // @[dec_tlu_ctl.scala 2223:112] - wire _T_816 = ~io_mtdata1_t_1[9]; // @[dec_tlu_ctl.scala 2223:138] - wire _T_817 = _T_816 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2223:170] - wire wr_mtdata1_t_r_1 = _T_814 & _T_817; // @[dec_tlu_ctl.scala 2223:135] - wire _T_822 = mtsel == 2'h2; // @[dec_tlu_ctl.scala 2223:121] - wire _T_823 = _T_803 & _T_822; // @[dec_tlu_ctl.scala 2223:112] - wire _T_825 = ~io_mtdata1_t_2[9]; // @[dec_tlu_ctl.scala 2223:138] - wire _T_826 = _T_825 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2223:170] - wire wr_mtdata1_t_r_2 = _T_823 & _T_826; // @[dec_tlu_ctl.scala 2223:135] - wire _T_831 = mtsel == 2'h3; // @[dec_tlu_ctl.scala 2223:121] - wire _T_832 = _T_803 & _T_831; // @[dec_tlu_ctl.scala 2223:112] - wire _T_834 = ~io_mtdata1_t_3[9]; // @[dec_tlu_ctl.scala 2223:138] - wire _T_835 = _T_834 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2223:170] - wire wr_mtdata1_t_r_3 = _T_832 & _T_835; // @[dec_tlu_ctl.scala 2223:135] - wire _T_841 = io_update_hit_bit_r[0] | io_mtdata1_t_0[8]; // @[dec_tlu_ctl.scala 2224:139] - wire [9:0] _T_844 = {io_mtdata1_t_0[9],_T_841,io_mtdata1_t_0[7:0]}; // @[Cat.scala 29:58] - wire _T_850 = io_update_hit_bit_r[1] | io_mtdata1_t_1[8]; // @[dec_tlu_ctl.scala 2224:139] - wire [9:0] _T_853 = {io_mtdata1_t_1[9],_T_850,io_mtdata1_t_1[7:0]}; // @[Cat.scala 29:58] - wire _T_859 = io_update_hit_bit_r[2] | io_mtdata1_t_2[8]; // @[dec_tlu_ctl.scala 2224:139] - wire [9:0] _T_862 = {io_mtdata1_t_2[9],_T_859,io_mtdata1_t_2[7:0]}; // @[Cat.scala 29:58] - wire _T_868 = io_update_hit_bit_r[3] | io_mtdata1_t_3[8]; // @[dec_tlu_ctl.scala 2224:139] - wire [9:0] _T_871 = {io_mtdata1_t_3[9],_T_868,io_mtdata1_t_3[7:0]}; // @[Cat.scala 29:58] - reg [9:0] _T_873; // @[dec_tlu_ctl.scala 2226:74] - reg [9:0] _T_874; // @[dec_tlu_ctl.scala 2226:74] - reg [9:0] _T_875; // @[dec_tlu_ctl.scala 2226:74] - reg [9:0] _T_876; // @[dec_tlu_ctl.scala 2226:74] - wire [31:0] _T_891 = {4'h2,io_mtdata1_t_0[9],6'h1f,io_mtdata1_t_0[8:7],6'h0,io_mtdata1_t_0[6:5],3'h0,io_mtdata1_t_0[4:3],3'h0,io_mtdata1_t_0[2:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_906 = {4'h2,io_mtdata1_t_1[9],6'h1f,io_mtdata1_t_1[8:7],6'h0,io_mtdata1_t_1[6:5],3'h0,io_mtdata1_t_1[4:3],3'h0,io_mtdata1_t_1[2:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_921 = {4'h2,io_mtdata1_t_2[9],6'h1f,io_mtdata1_t_2[8:7],6'h0,io_mtdata1_t_2[6:5],3'h0,io_mtdata1_t_2[4:3],3'h0,io_mtdata1_t_2[2:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_936 = {4'h2,io_mtdata1_t_3[9],6'h1f,io_mtdata1_t_3[8:7],6'h0,io_mtdata1_t_3[6:5],3'h0,io_mtdata1_t_3[4:3],3'h0,io_mtdata1_t_3[2:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_937 = _T_804 ? _T_891 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_938 = _T_813 ? _T_906 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_939 = _T_822 ? _T_921 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_940 = _T_831 ? _T_936 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_941 = _T_937 | _T_938; // @[Mux.scala 27:72] - wire [31:0] _T_942 = _T_941 | _T_939; // @[Mux.scala 27:72] - wire [31:0] mtdata1_tsel_out = _T_942 | _T_940; // @[Mux.scala 27:72] - wire _T_969 = io_dec_csr_wraddr_r == 12'h7a2; // @[dec_tlu_ctl.scala 2243:98] - wire _T_970 = io_dec_csr_wen_r_mod & _T_969; // @[dec_tlu_ctl.scala 2243:69] - wire _T_972 = _T_970 & _T_804; // @[dec_tlu_ctl.scala 2243:111] - wire _T_981 = _T_970 & _T_813; // @[dec_tlu_ctl.scala 2243:111] - wire _T_990 = _T_970 & _T_822; // @[dec_tlu_ctl.scala 2243:111] - wire _T_999 = _T_970 & _T_831; // @[dec_tlu_ctl.scala 2243:111] + wire tdata_load = io_dec_csr_wrdata_r[0] & _T_398; // @[dec_tlu_ctl.scala 2213:42] + wire tdata_opcode = io_dec_csr_wrdata_r[2] & _T_398; // @[dec_tlu_ctl.scala 2215:44] + wire _T_777 = io_dec_csr_wrdata_r[27] & io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2217:46] + wire tdata_action = _T_777 & io_dec_csr_wrdata_r[12]; // @[dec_tlu_ctl.scala 2217:69] + wire [9:0] tdata_wrdata_r = {_T_777,io_dec_csr_wrdata_r[20:19],tdata_action,io_dec_csr_wrdata_r[11],io_dec_csr_wrdata_r[7:6],tdata_opcode,io_dec_csr_wrdata_r[1],tdata_load}; // @[Cat.scala 29:58] + wire _T_792 = io_dec_csr_wraddr_r == 12'h7a1; // @[dec_tlu_ctl.scala 2223:99] + wire _T_793 = io_dec_csr_wen_r_mod & _T_792; // @[dec_tlu_ctl.scala 2223:70] + wire _T_794 = mtsel == 2'h0; // @[dec_tlu_ctl.scala 2223:121] + wire _T_795 = _T_793 & _T_794; // @[dec_tlu_ctl.scala 2223:112] + wire _T_797 = ~io_mtdata1_t_0[9]; // @[dec_tlu_ctl.scala 2223:138] + wire _T_798 = _T_797 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2223:170] + wire wr_mtdata1_t_r_0 = _T_795 & _T_798; // @[dec_tlu_ctl.scala 2223:135] + wire _T_803 = mtsel == 2'h1; // @[dec_tlu_ctl.scala 2223:121] + wire _T_804 = _T_793 & _T_803; // @[dec_tlu_ctl.scala 2223:112] + wire _T_806 = ~io_mtdata1_t_1[9]; // @[dec_tlu_ctl.scala 2223:138] + wire _T_807 = _T_806 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2223:170] + wire wr_mtdata1_t_r_1 = _T_804 & _T_807; // @[dec_tlu_ctl.scala 2223:135] + wire _T_812 = mtsel == 2'h2; // @[dec_tlu_ctl.scala 2223:121] + wire _T_813 = _T_793 & _T_812; // @[dec_tlu_ctl.scala 2223:112] + wire _T_815 = ~io_mtdata1_t_2[9]; // @[dec_tlu_ctl.scala 2223:138] + wire _T_816 = _T_815 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2223:170] + wire wr_mtdata1_t_r_2 = _T_813 & _T_816; // @[dec_tlu_ctl.scala 2223:135] + wire _T_821 = mtsel == 2'h3; // @[dec_tlu_ctl.scala 2223:121] + wire _T_822 = _T_793 & _T_821; // @[dec_tlu_ctl.scala 2223:112] + wire _T_824 = ~io_mtdata1_t_3[9]; // @[dec_tlu_ctl.scala 2223:138] + wire _T_825 = _T_824 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2223:170] + wire wr_mtdata1_t_r_3 = _T_822 & _T_825; // @[dec_tlu_ctl.scala 2223:135] + wire _T_831 = io_update_hit_bit_r[0] | io_mtdata1_t_0[8]; // @[dec_tlu_ctl.scala 2224:139] + wire [9:0] _T_834 = {io_mtdata1_t_0[9],_T_831,io_mtdata1_t_0[7:0]}; // @[Cat.scala 29:58] + wire _T_840 = io_update_hit_bit_r[1] | io_mtdata1_t_1[8]; // @[dec_tlu_ctl.scala 2224:139] + wire [9:0] _T_843 = {io_mtdata1_t_1[9],_T_840,io_mtdata1_t_1[7:0]}; // @[Cat.scala 29:58] + wire _T_849 = io_update_hit_bit_r[2] | io_mtdata1_t_2[8]; // @[dec_tlu_ctl.scala 2224:139] + wire [9:0] _T_852 = {io_mtdata1_t_2[9],_T_849,io_mtdata1_t_2[7:0]}; // @[Cat.scala 29:58] + wire _T_858 = io_update_hit_bit_r[3] | io_mtdata1_t_3[8]; // @[dec_tlu_ctl.scala 2224:139] + wire [9:0] _T_861 = {io_mtdata1_t_3[9],_T_858,io_mtdata1_t_3[7:0]}; // @[Cat.scala 29:58] + reg [9:0] _T_863; // @[dec_tlu_ctl.scala 2226:74] + reg [9:0] _T_864; // @[dec_tlu_ctl.scala 2226:74] + reg [9:0] _T_865; // @[dec_tlu_ctl.scala 2226:74] + reg [9:0] _T_866; // @[dec_tlu_ctl.scala 2226:74] + wire [31:0] _T_881 = {4'h2,io_mtdata1_t_0[9],6'h1f,io_mtdata1_t_0[8:7],6'h0,io_mtdata1_t_0[6:5],3'h0,io_mtdata1_t_0[4:3],3'h0,io_mtdata1_t_0[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_896 = {4'h2,io_mtdata1_t_1[9],6'h1f,io_mtdata1_t_1[8:7],6'h0,io_mtdata1_t_1[6:5],3'h0,io_mtdata1_t_1[4:3],3'h0,io_mtdata1_t_1[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_911 = {4'h2,io_mtdata1_t_2[9],6'h1f,io_mtdata1_t_2[8:7],6'h0,io_mtdata1_t_2[6:5],3'h0,io_mtdata1_t_2[4:3],3'h0,io_mtdata1_t_2[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_926 = {4'h2,io_mtdata1_t_3[9],6'h1f,io_mtdata1_t_3[8:7],6'h0,io_mtdata1_t_3[6:5],3'h0,io_mtdata1_t_3[4:3],3'h0,io_mtdata1_t_3[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_927 = _T_794 ? _T_881 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_928 = _T_803 ? _T_896 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_929 = _T_812 ? _T_911 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_930 = _T_821 ? _T_926 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_931 = _T_927 | _T_928; // @[Mux.scala 27:72] + wire [31:0] _T_932 = _T_931 | _T_929; // @[Mux.scala 27:72] + wire [31:0] mtdata1_tsel_out = _T_932 | _T_930; // @[Mux.scala 27:72] + wire _T_959 = io_dec_csr_wraddr_r == 12'h7a2; // @[dec_tlu_ctl.scala 2243:98] + wire _T_960 = io_dec_csr_wen_r_mod & _T_959; // @[dec_tlu_ctl.scala 2243:69] + wire _T_962 = _T_960 & _T_794; // @[dec_tlu_ctl.scala 2243:111] + wire _T_971 = _T_960 & _T_803; // @[dec_tlu_ctl.scala 2243:111] + wire _T_980 = _T_960 & _T_812; // @[dec_tlu_ctl.scala 2243:111] + wire _T_989 = _T_960 & _T_821; // @[dec_tlu_ctl.scala 2243:111] reg [31:0] mtdata2_t_0; // @[lib.scala 374:16] reg [31:0] mtdata2_t_1; // @[lib.scala 374:16] reg [31:0] mtdata2_t_2; // @[lib.scala 374:16] reg [31:0] mtdata2_t_3; // @[lib.scala 374:16] - wire [31:0] _T_1016 = _T_804 ? mtdata2_t_0 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_1017 = _T_813 ? mtdata2_t_1 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_1018 = _T_822 ? mtdata2_t_2 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_1019 = _T_831 ? mtdata2_t_3 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_1020 = _T_1016 | _T_1017; // @[Mux.scala 27:72] - wire [31:0] _T_1021 = _T_1020 | _T_1018; // @[Mux.scala 27:72] - wire [31:0] mtdata2_tsel_out = _T_1021 | _T_1019; // @[Mux.scala 27:72] - wire [3:0] _T_1024 = io_tlu_i0_commit_cmt ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] pmu_i0_itype_qual = io_dec_tlu_packet_r_pmu_i0_itype & _T_1024; // @[dec_tlu_ctl.scala 2268:59] - wire _T_1026 = ~mcountinhibit[3]; // @[dec_tlu_ctl.scala 2274:24] + wire [31:0] _T_1006 = _T_794 ? mtdata2_t_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1007 = _T_803 ? mtdata2_t_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1008 = _T_812 ? mtdata2_t_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1009 = _T_821 ? mtdata2_t_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1010 = _T_1006 | _T_1007; // @[Mux.scala 27:72] + wire [31:0] _T_1011 = _T_1010 | _T_1008; // @[Mux.scala 27:72] + wire [31:0] mtdata2_tsel_out = _T_1011 | _T_1009; // @[Mux.scala 27:72] + wire [3:0] _T_1014 = io_tlu_i0_commit_cmt ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] pmu_i0_itype_qual = io_dec_tlu_packet_r_pmu_i0_itype & _T_1014; // @[dec_tlu_ctl.scala 2268:59] + wire _T_1016 = ~mcountinhibit[3]; // @[dec_tlu_ctl.scala 2274:24] reg [9:0] mhpme3; // @[Reg.scala 27:20] - wire _T_1027 = mhpme3 == 10'h1; // @[dec_tlu_ctl.scala 2275:34] - wire _T_1029 = mhpme3 == 10'h2; // @[dec_tlu_ctl.scala 2276:34] - wire _T_1031 = mhpme3 == 10'h3; // @[dec_tlu_ctl.scala 2277:34] - wire _T_1033 = mhpme3 == 10'h4; // @[dec_tlu_ctl.scala 2278:34] - wire _T_1035 = ~io_illegal_r; // @[dec_tlu_ctl.scala 2278:96] - wire _T_1036 = io_tlu_i0_commit_cmt & _T_1035; // @[dec_tlu_ctl.scala 2278:94] - wire _T_1037 = mhpme3 == 10'h5; // @[dec_tlu_ctl.scala 2279:34] - wire _T_1039 = ~io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2279:96] - wire _T_1040 = io_tlu_i0_commit_cmt & _T_1039; // @[dec_tlu_ctl.scala 2279:94] - wire _T_1042 = _T_1040 & _T_1035; // @[dec_tlu_ctl.scala 2279:115] - wire _T_1043 = mhpme3 == 10'h6; // @[dec_tlu_ctl.scala 2280:34] - wire _T_1045 = io_tlu_i0_commit_cmt & io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2280:94] - wire _T_1047 = _T_1045 & _T_1035; // @[dec_tlu_ctl.scala 2280:115] - wire _T_1048 = mhpme3 == 10'h7; // @[dec_tlu_ctl.scala 2281:34] - wire _T_1050 = mhpme3 == 10'h8; // @[dec_tlu_ctl.scala 2282:34] - wire _T_1052 = mhpme3 == 10'h1e; // @[dec_tlu_ctl.scala 2283:34] - wire _T_1054 = mhpme3 == 10'h9; // @[dec_tlu_ctl.scala 2284:34] - wire _T_1056 = pmu_i0_itype_qual == 4'h1; // @[dec_tlu_ctl.scala 2284:91] - wire _T_1057 = mhpme3 == 10'ha; // @[dec_tlu_ctl.scala 2285:34] - wire _T_1059 = io_dec_tlu_packet_r_pmu_divide & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2285:105] - wire _T_1060 = mhpme3 == 10'hb; // @[dec_tlu_ctl.scala 2286:34] - wire _T_1062 = pmu_i0_itype_qual == 4'h2; // @[dec_tlu_ctl.scala 2286:91] - wire _T_1063 = mhpme3 == 10'hc; // @[dec_tlu_ctl.scala 2287:34] - wire _T_1065 = pmu_i0_itype_qual == 4'h3; // @[dec_tlu_ctl.scala 2287:91] - wire _T_1066 = mhpme3 == 10'hd; // @[dec_tlu_ctl.scala 2288:34] - wire _T_1069 = _T_1062 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2288:100] - wire _T_1070 = mhpme3 == 10'he; // @[dec_tlu_ctl.scala 2289:34] - wire _T_1074 = _T_1065 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2289:101] - wire _T_1075 = mhpme3 == 10'hf; // @[dec_tlu_ctl.scala 2290:34] - wire _T_1077 = pmu_i0_itype_qual == 4'h4; // @[dec_tlu_ctl.scala 2290:89] - wire _T_1078 = mhpme3 == 10'h10; // @[dec_tlu_ctl.scala 2291:34] - wire _T_1080 = pmu_i0_itype_qual == 4'h5; // @[dec_tlu_ctl.scala 2291:89] - wire _T_1081 = mhpme3 == 10'h12; // @[dec_tlu_ctl.scala 2292:34] - wire _T_1083 = pmu_i0_itype_qual == 4'h6; // @[dec_tlu_ctl.scala 2292:89] - wire _T_1084 = mhpme3 == 10'h11; // @[dec_tlu_ctl.scala 2293:34] - wire _T_1086 = pmu_i0_itype_qual == 4'h7; // @[dec_tlu_ctl.scala 2293:89] - wire _T_1087 = mhpme3 == 10'h13; // @[dec_tlu_ctl.scala 2294:34] - wire _T_1089 = pmu_i0_itype_qual == 4'h8; // @[dec_tlu_ctl.scala 2294:89] - wire _T_1090 = mhpme3 == 10'h14; // @[dec_tlu_ctl.scala 2295:34] - wire _T_1092 = pmu_i0_itype_qual == 4'h9; // @[dec_tlu_ctl.scala 2295:89] - wire _T_1093 = mhpme3 == 10'h15; // @[dec_tlu_ctl.scala 2296:34] - wire _T_1095 = pmu_i0_itype_qual == 4'ha; // @[dec_tlu_ctl.scala 2296:89] - wire _T_1096 = mhpme3 == 10'h16; // @[dec_tlu_ctl.scala 2297:34] - wire _T_1098 = pmu_i0_itype_qual == 4'hb; // @[dec_tlu_ctl.scala 2297:89] - wire _T_1099 = mhpme3 == 10'h17; // @[dec_tlu_ctl.scala 2298:34] - wire _T_1101 = pmu_i0_itype_qual == 4'hc; // @[dec_tlu_ctl.scala 2298:89] - wire _T_1102 = mhpme3 == 10'h18; // @[dec_tlu_ctl.scala 2299:34] - wire _T_1104 = pmu_i0_itype_qual == 4'hd; // @[dec_tlu_ctl.scala 2299:89] - wire _T_1105 = pmu_i0_itype_qual == 4'he; // @[dec_tlu_ctl.scala 2299:122] - wire _T_1106 = _T_1104 | _T_1105; // @[dec_tlu_ctl.scala 2299:101] - wire _T_1107 = mhpme3 == 10'h19; // @[dec_tlu_ctl.scala 2300:34] - wire _T_1109 = io_exu_pmu_i0_br_misp & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2300:95] - wire _T_1110 = mhpme3 == 10'h1a; // @[dec_tlu_ctl.scala 2301:34] - wire _T_1112 = io_exu_pmu_i0_br_ataken & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2301:97] - wire _T_1113 = mhpme3 == 10'h1b; // @[dec_tlu_ctl.scala 2302:34] - wire _T_1115 = io_dec_tlu_packet_r_pmu_i0_br_unpred & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2302:110] - wire _T_1116 = mhpme3 == 10'h1c; // @[dec_tlu_ctl.scala 2303:34] - wire _T_1120 = mhpme3 == 10'h1f; // @[dec_tlu_ctl.scala 2305:34] - wire _T_1122 = mhpme3 == 10'h20; // @[dec_tlu_ctl.scala 2306:34] - wire _T_1124 = mhpme3 == 10'h22; // @[dec_tlu_ctl.scala 2307:34] - wire _T_1126 = mhpme3 == 10'h23; // @[dec_tlu_ctl.scala 2308:34] - wire _T_1128 = mhpme3 == 10'h24; // @[dec_tlu_ctl.scala 2309:34] - wire _T_1130 = mhpme3 == 10'h25; // @[dec_tlu_ctl.scala 2310:34] - wire _T_1132 = io_i0_exception_valid_r | io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 2310:98] - wire _T_1133 = _T_1132 | io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 2310:120] - wire _T_1134 = mhpme3 == 10'h26; // @[dec_tlu_ctl.scala 2311:34] - wire _T_1136 = io_take_timer_int | io_take_int_timer0_int; // @[dec_tlu_ctl.scala 2311:92] - wire _T_1137 = _T_1136 | io_take_int_timer1_int; // @[dec_tlu_ctl.scala 2311:117] - wire _T_1138 = mhpme3 == 10'h27; // @[dec_tlu_ctl.scala 2312:34] - wire _T_1140 = mhpme3 == 10'h28; // @[dec_tlu_ctl.scala 2313:34] - wire _T_1142 = mhpme3 == 10'h29; // @[dec_tlu_ctl.scala 2314:34] - wire _T_1144 = io_dec_tlu_br0_error_r | io_dec_tlu_br0_start_error_r; // @[dec_tlu_ctl.scala 2314:97] - wire _T_1145 = _T_1144 & io_rfpc_i0_r; // @[dec_tlu_ctl.scala 2314:129] - wire _T_1146 = mhpme3 == 10'h2a; // @[dec_tlu_ctl.scala 2315:34] - wire _T_1148 = mhpme3 == 10'h2b; // @[dec_tlu_ctl.scala 2316:34] - wire _T_1150 = mhpme3 == 10'h2c; // @[dec_tlu_ctl.scala 2317:34] - wire _T_1152 = mhpme3 == 10'h2d; // @[dec_tlu_ctl.scala 2318:34] - wire _T_1154 = mhpme3 == 10'h2e; // @[dec_tlu_ctl.scala 2319:34] - wire _T_1156 = mhpme3 == 10'h2f; // @[dec_tlu_ctl.scala 2320:34] - wire _T_1158 = mhpme3 == 10'h30; // @[dec_tlu_ctl.scala 2321:34] - wire _T_1160 = mhpme3 == 10'h31; // @[dec_tlu_ctl.scala 2322:34] - wire _T_1164 = ~io_mstatus[0]; // @[dec_tlu_ctl.scala 2322:73] - wire _T_1165 = mhpme3 == 10'h32; // @[dec_tlu_ctl.scala 2323:34] - wire [5:0] _T_1172 = io_mip & mie; // @[dec_tlu_ctl.scala 2323:113] - wire _T_1173 = |_T_1172; // @[dec_tlu_ctl.scala 2323:125] - wire _T_1174 = _T_1164 & _T_1173; // @[dec_tlu_ctl.scala 2323:98] - wire _T_1175 = mhpme3 == 10'h36; // @[dec_tlu_ctl.scala 2324:34] - wire _T_1177 = pmu_i0_itype_qual == 4'hf; // @[dec_tlu_ctl.scala 2324:91] - wire _T_1178 = mhpme3 == 10'h37; // @[dec_tlu_ctl.scala 2325:34] - wire _T_1180 = io_tlu_i0_commit_cmt & io_lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 2325:94] - wire _T_1181 = mhpme3 == 10'h38; // @[dec_tlu_ctl.scala 2326:34] - wire _T_1183 = io_tlu_i0_commit_cmt & io_lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 2326:94] - wire _T_1184 = mhpme3 == 10'h200; // @[dec_tlu_ctl.scala 2328:34] - wire _T_1186 = mhpme3 == 10'h201; // @[dec_tlu_ctl.scala 2329:34] - wire _T_1188 = mhpme3 == 10'h202; // @[dec_tlu_ctl.scala 2330:34] - wire _T_1190 = mhpme3 == 10'h203; // @[dec_tlu_ctl.scala 2331:34] - wire _T_1192 = mhpme3 == 10'h204; // @[dec_tlu_ctl.scala 2332:34] - wire _T_1195 = _T_1029 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] - wire _T_1196 = _T_1031 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] - wire _T_1197 = _T_1033 & _T_1036; // @[Mux.scala 27:72] - wire _T_1198 = _T_1037 & _T_1042; // @[Mux.scala 27:72] - wire _T_1199 = _T_1043 & _T_1047; // @[Mux.scala 27:72] - wire _T_1200 = _T_1048 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] - wire _T_1201 = _T_1050 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] - wire _T_1202 = _T_1052 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] - wire _T_1203 = _T_1054 & _T_1056; // @[Mux.scala 27:72] - wire _T_1204 = _T_1057 & _T_1059; // @[Mux.scala 27:72] - wire _T_1205 = _T_1060 & _T_1062; // @[Mux.scala 27:72] - wire _T_1206 = _T_1063 & _T_1065; // @[Mux.scala 27:72] - wire _T_1207 = _T_1066 & _T_1069; // @[Mux.scala 27:72] - wire _T_1208 = _T_1070 & _T_1074; // @[Mux.scala 27:72] - wire _T_1209 = _T_1075 & _T_1077; // @[Mux.scala 27:72] - wire _T_1210 = _T_1078 & _T_1080; // @[Mux.scala 27:72] - wire _T_1211 = _T_1081 & _T_1083; // @[Mux.scala 27:72] - wire _T_1212 = _T_1084 & _T_1086; // @[Mux.scala 27:72] - wire _T_1213 = _T_1087 & _T_1089; // @[Mux.scala 27:72] - wire _T_1214 = _T_1090 & _T_1092; // @[Mux.scala 27:72] - wire _T_1215 = _T_1093 & _T_1095; // @[Mux.scala 27:72] - wire _T_1216 = _T_1096 & _T_1098; // @[Mux.scala 27:72] - wire _T_1217 = _T_1099 & _T_1101; // @[Mux.scala 27:72] - wire _T_1218 = _T_1102 & _T_1106; // @[Mux.scala 27:72] - wire _T_1219 = _T_1107 & _T_1109; // @[Mux.scala 27:72] - wire _T_1220 = _T_1110 & _T_1112; // @[Mux.scala 27:72] - wire _T_1221 = _T_1113 & _T_1115; // @[Mux.scala 27:72] - wire _T_1222 = _T_1116 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] - wire _T_1224 = _T_1120 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] - wire _T_1225 = _T_1122 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] - wire _T_1226 = _T_1124 & io_lsu_store_stall_any; // @[Mux.scala 27:72] - wire _T_1227 = _T_1126 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] - wire _T_1228 = _T_1128 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] - wire _T_1229 = _T_1130 & _T_1133; // @[Mux.scala 27:72] - wire _T_1230 = _T_1134 & _T_1137; // @[Mux.scala 27:72] - wire _T_1231 = _T_1138 & io_take_ext_int; // @[Mux.scala 27:72] - wire _T_1232 = _T_1140 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] - wire _T_1233 = _T_1142 & _T_1145; // @[Mux.scala 27:72] - wire _T_1234 = _T_1146 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1235 = _T_1148 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1236 = _T_1150 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] - wire _T_1237 = _T_1152 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1238 = _T_1154 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1239 = _T_1156 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1240 = _T_1158 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1241 = _T_1160 & _T_1164; // @[Mux.scala 27:72] - wire _T_1242 = _T_1165 & _T_1174; // @[Mux.scala 27:72] - wire _T_1243 = _T_1175 & _T_1177; // @[Mux.scala 27:72] - wire _T_1244 = _T_1178 & _T_1180; // @[Mux.scala 27:72] - wire _T_1245 = _T_1181 & _T_1183; // @[Mux.scala 27:72] - wire _T_1246 = _T_1184 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] - wire _T_1247 = _T_1186 & io_dma_pmu_any_read; // @[Mux.scala 27:72] - wire _T_1248 = _T_1188 & io_dma_pmu_any_write; // @[Mux.scala 27:72] - wire _T_1249 = _T_1190 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] - wire _T_1250 = _T_1192 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] - wire _T_1251 = _T_1027 | _T_1195; // @[Mux.scala 27:72] + wire _T_1017 = mhpme3 == 10'h1; // @[dec_tlu_ctl.scala 2275:34] + wire _T_1019 = mhpme3 == 10'h2; // @[dec_tlu_ctl.scala 2276:34] + wire _T_1021 = mhpme3 == 10'h3; // @[dec_tlu_ctl.scala 2277:34] + wire _T_1023 = mhpme3 == 10'h4; // @[dec_tlu_ctl.scala 2278:34] + wire _T_1025 = ~io_illegal_r; // @[dec_tlu_ctl.scala 2278:96] + wire _T_1026 = io_tlu_i0_commit_cmt & _T_1025; // @[dec_tlu_ctl.scala 2278:94] + wire _T_1027 = mhpme3 == 10'h5; // @[dec_tlu_ctl.scala 2279:34] + wire _T_1029 = ~io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2279:96] + wire _T_1030 = io_tlu_i0_commit_cmt & _T_1029; // @[dec_tlu_ctl.scala 2279:94] + wire _T_1032 = _T_1030 & _T_1025; // @[dec_tlu_ctl.scala 2279:115] + wire _T_1033 = mhpme3 == 10'h6; // @[dec_tlu_ctl.scala 2280:34] + wire _T_1035 = io_tlu_i0_commit_cmt & io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2280:94] + wire _T_1037 = _T_1035 & _T_1025; // @[dec_tlu_ctl.scala 2280:115] + wire _T_1038 = mhpme3 == 10'h7; // @[dec_tlu_ctl.scala 2281:34] + wire _T_1040 = mhpme3 == 10'h8; // @[dec_tlu_ctl.scala 2282:34] + wire _T_1042 = mhpme3 == 10'h1e; // @[dec_tlu_ctl.scala 2283:34] + wire _T_1044 = mhpme3 == 10'h9; // @[dec_tlu_ctl.scala 2284:34] + wire _T_1046 = pmu_i0_itype_qual == 4'h1; // @[dec_tlu_ctl.scala 2284:91] + wire _T_1047 = mhpme3 == 10'ha; // @[dec_tlu_ctl.scala 2285:34] + wire _T_1049 = io_dec_tlu_packet_r_pmu_divide & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2285:105] + wire _T_1050 = mhpme3 == 10'hb; // @[dec_tlu_ctl.scala 2286:34] + wire _T_1052 = pmu_i0_itype_qual == 4'h2; // @[dec_tlu_ctl.scala 2286:91] + wire _T_1053 = mhpme3 == 10'hc; // @[dec_tlu_ctl.scala 2287:34] + wire _T_1055 = pmu_i0_itype_qual == 4'h3; // @[dec_tlu_ctl.scala 2287:91] + wire _T_1056 = mhpme3 == 10'hd; // @[dec_tlu_ctl.scala 2288:34] + wire _T_1059 = _T_1052 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2288:100] + wire _T_1060 = mhpme3 == 10'he; // @[dec_tlu_ctl.scala 2289:34] + wire _T_1064 = _T_1055 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2289:101] + wire _T_1065 = mhpme3 == 10'hf; // @[dec_tlu_ctl.scala 2290:34] + wire _T_1067 = pmu_i0_itype_qual == 4'h4; // @[dec_tlu_ctl.scala 2290:89] + wire _T_1068 = mhpme3 == 10'h10; // @[dec_tlu_ctl.scala 2291:34] + wire _T_1070 = pmu_i0_itype_qual == 4'h5; // @[dec_tlu_ctl.scala 2291:89] + wire _T_1071 = mhpme3 == 10'h12; // @[dec_tlu_ctl.scala 2292:34] + wire _T_1073 = pmu_i0_itype_qual == 4'h6; // @[dec_tlu_ctl.scala 2292:89] + wire _T_1074 = mhpme3 == 10'h11; // @[dec_tlu_ctl.scala 2293:34] + wire _T_1076 = pmu_i0_itype_qual == 4'h7; // @[dec_tlu_ctl.scala 2293:89] + wire _T_1077 = mhpme3 == 10'h13; // @[dec_tlu_ctl.scala 2294:34] + wire _T_1079 = pmu_i0_itype_qual == 4'h8; // @[dec_tlu_ctl.scala 2294:89] + wire _T_1080 = mhpme3 == 10'h14; // @[dec_tlu_ctl.scala 2295:34] + wire _T_1082 = pmu_i0_itype_qual == 4'h9; // @[dec_tlu_ctl.scala 2295:89] + wire _T_1083 = mhpme3 == 10'h15; // @[dec_tlu_ctl.scala 2296:34] + wire _T_1085 = pmu_i0_itype_qual == 4'ha; // @[dec_tlu_ctl.scala 2296:89] + wire _T_1086 = mhpme3 == 10'h16; // @[dec_tlu_ctl.scala 2297:34] + wire _T_1088 = pmu_i0_itype_qual == 4'hb; // @[dec_tlu_ctl.scala 2297:89] + wire _T_1089 = mhpme3 == 10'h17; // @[dec_tlu_ctl.scala 2298:34] + wire _T_1091 = pmu_i0_itype_qual == 4'hc; // @[dec_tlu_ctl.scala 2298:89] + wire _T_1092 = mhpme3 == 10'h18; // @[dec_tlu_ctl.scala 2299:34] + wire _T_1094 = pmu_i0_itype_qual == 4'hd; // @[dec_tlu_ctl.scala 2299:89] + wire _T_1095 = pmu_i0_itype_qual == 4'he; // @[dec_tlu_ctl.scala 2299:122] + wire _T_1096 = _T_1094 | _T_1095; // @[dec_tlu_ctl.scala 2299:101] + wire _T_1097 = mhpme3 == 10'h19; // @[dec_tlu_ctl.scala 2300:34] + wire _T_1099 = io_exu_pmu_i0_br_misp & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2300:95] + wire _T_1100 = mhpme3 == 10'h1a; // @[dec_tlu_ctl.scala 2301:34] + wire _T_1102 = io_exu_pmu_i0_br_ataken & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2301:97] + wire _T_1103 = mhpme3 == 10'h1b; // @[dec_tlu_ctl.scala 2302:34] + wire _T_1105 = io_dec_tlu_packet_r_pmu_i0_br_unpred & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2302:110] + wire _T_1106 = mhpme3 == 10'h1c; // @[dec_tlu_ctl.scala 2303:34] + wire _T_1110 = mhpme3 == 10'h1f; // @[dec_tlu_ctl.scala 2305:34] + wire _T_1112 = mhpme3 == 10'h20; // @[dec_tlu_ctl.scala 2306:34] + wire _T_1114 = mhpme3 == 10'h22; // @[dec_tlu_ctl.scala 2307:34] + wire _T_1116 = mhpme3 == 10'h23; // @[dec_tlu_ctl.scala 2308:34] + wire _T_1118 = mhpme3 == 10'h24; // @[dec_tlu_ctl.scala 2309:34] + wire _T_1120 = mhpme3 == 10'h25; // @[dec_tlu_ctl.scala 2310:34] + wire _T_1122 = io_i0_exception_valid_r | io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 2310:98] + wire _T_1123 = _T_1122 | io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 2310:120] + wire _T_1124 = mhpme3 == 10'h26; // @[dec_tlu_ctl.scala 2311:34] + wire _T_1126 = io_take_timer_int | io_take_int_timer0_int; // @[dec_tlu_ctl.scala 2311:92] + wire _T_1127 = _T_1126 | io_take_int_timer1_int; // @[dec_tlu_ctl.scala 2311:117] + wire _T_1128 = mhpme3 == 10'h27; // @[dec_tlu_ctl.scala 2312:34] + wire _T_1130 = mhpme3 == 10'h28; // @[dec_tlu_ctl.scala 2313:34] + wire _T_1132 = mhpme3 == 10'h29; // @[dec_tlu_ctl.scala 2314:34] + wire _T_1134 = io_dec_tlu_br0_error_r | io_dec_tlu_br0_start_error_r; // @[dec_tlu_ctl.scala 2314:97] + wire _T_1135 = _T_1134 & io_rfpc_i0_r; // @[dec_tlu_ctl.scala 2314:129] + wire _T_1136 = mhpme3 == 10'h2a; // @[dec_tlu_ctl.scala 2315:34] + wire _T_1138 = mhpme3 == 10'h2b; // @[dec_tlu_ctl.scala 2316:34] + wire _T_1140 = mhpme3 == 10'h2c; // @[dec_tlu_ctl.scala 2317:34] + wire _T_1142 = mhpme3 == 10'h2d; // @[dec_tlu_ctl.scala 2318:34] + wire _T_1144 = mhpme3 == 10'h2e; // @[dec_tlu_ctl.scala 2319:34] + wire _T_1146 = mhpme3 == 10'h2f; // @[dec_tlu_ctl.scala 2320:34] + wire _T_1148 = mhpme3 == 10'h30; // @[dec_tlu_ctl.scala 2321:34] + wire _T_1150 = mhpme3 == 10'h31; // @[dec_tlu_ctl.scala 2322:34] + wire _T_1154 = ~io_mstatus[0]; // @[dec_tlu_ctl.scala 2322:73] + wire _T_1155 = mhpme3 == 10'h32; // @[dec_tlu_ctl.scala 2323:34] + wire [5:0] _T_1162 = io_mip & mie; // @[dec_tlu_ctl.scala 2323:113] + wire _T_1163 = |_T_1162; // @[dec_tlu_ctl.scala 2323:125] + wire _T_1164 = _T_1154 & _T_1163; // @[dec_tlu_ctl.scala 2323:98] + wire _T_1165 = mhpme3 == 10'h36; // @[dec_tlu_ctl.scala 2324:34] + wire _T_1167 = pmu_i0_itype_qual == 4'hf; // @[dec_tlu_ctl.scala 2324:91] + wire _T_1168 = mhpme3 == 10'h37; // @[dec_tlu_ctl.scala 2325:34] + wire _T_1170 = io_tlu_i0_commit_cmt & io_lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 2325:94] + wire _T_1171 = mhpme3 == 10'h38; // @[dec_tlu_ctl.scala 2326:34] + wire _T_1173 = io_tlu_i0_commit_cmt & io_lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 2326:94] + wire _T_1174 = mhpme3 == 10'h200; // @[dec_tlu_ctl.scala 2328:34] + wire _T_1176 = mhpme3 == 10'h201; // @[dec_tlu_ctl.scala 2329:34] + wire _T_1178 = mhpme3 == 10'h202; // @[dec_tlu_ctl.scala 2330:34] + wire _T_1180 = mhpme3 == 10'h203; // @[dec_tlu_ctl.scala 2331:34] + wire _T_1182 = mhpme3 == 10'h204; // @[dec_tlu_ctl.scala 2332:34] + wire _T_1185 = _T_1019 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_1186 = _T_1021 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_1187 = _T_1023 & _T_1026; // @[Mux.scala 27:72] + wire _T_1188 = _T_1027 & _T_1032; // @[Mux.scala 27:72] + wire _T_1189 = _T_1033 & _T_1037; // @[Mux.scala 27:72] + wire _T_1190 = _T_1038 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_1191 = _T_1040 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_1192 = _T_1042 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_1193 = _T_1044 & _T_1046; // @[Mux.scala 27:72] + wire _T_1194 = _T_1047 & _T_1049; // @[Mux.scala 27:72] + wire _T_1195 = _T_1050 & _T_1052; // @[Mux.scala 27:72] + wire _T_1196 = _T_1053 & _T_1055; // @[Mux.scala 27:72] + wire _T_1197 = _T_1056 & _T_1059; // @[Mux.scala 27:72] + wire _T_1198 = _T_1060 & _T_1064; // @[Mux.scala 27:72] + wire _T_1199 = _T_1065 & _T_1067; // @[Mux.scala 27:72] + wire _T_1200 = _T_1068 & _T_1070; // @[Mux.scala 27:72] + wire _T_1201 = _T_1071 & _T_1073; // @[Mux.scala 27:72] + wire _T_1202 = _T_1074 & _T_1076; // @[Mux.scala 27:72] + wire _T_1203 = _T_1077 & _T_1079; // @[Mux.scala 27:72] + wire _T_1204 = _T_1080 & _T_1082; // @[Mux.scala 27:72] + wire _T_1205 = _T_1083 & _T_1085; // @[Mux.scala 27:72] + wire _T_1206 = _T_1086 & _T_1088; // @[Mux.scala 27:72] + wire _T_1207 = _T_1089 & _T_1091; // @[Mux.scala 27:72] + wire _T_1208 = _T_1092 & _T_1096; // @[Mux.scala 27:72] + wire _T_1209 = _T_1097 & _T_1099; // @[Mux.scala 27:72] + wire _T_1210 = _T_1100 & _T_1102; // @[Mux.scala 27:72] + wire _T_1211 = _T_1103 & _T_1105; // @[Mux.scala 27:72] + wire _T_1212 = _T_1106 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_1214 = _T_1110 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_1215 = _T_1112 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_1216 = _T_1114 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_1217 = _T_1116 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_1218 = _T_1118 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_1219 = _T_1120 & _T_1123; // @[Mux.scala 27:72] + wire _T_1220 = _T_1124 & _T_1127; // @[Mux.scala 27:72] + wire _T_1221 = _T_1128 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_1222 = _T_1130 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_1223 = _T_1132 & _T_1135; // @[Mux.scala 27:72] + wire _T_1224 = _T_1136 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1225 = _T_1138 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1226 = _T_1140 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_1227 = _T_1142 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1228 = _T_1144 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1229 = _T_1146 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1230 = _T_1148 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1231 = _T_1150 & _T_1154; // @[Mux.scala 27:72] + wire _T_1232 = _T_1155 & _T_1164; // @[Mux.scala 27:72] + wire _T_1233 = _T_1165 & _T_1167; // @[Mux.scala 27:72] + wire _T_1234 = _T_1168 & _T_1170; // @[Mux.scala 27:72] + wire _T_1235 = _T_1171 & _T_1173; // @[Mux.scala 27:72] + wire _T_1236 = _T_1174 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_1237 = _T_1176 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_1238 = _T_1178 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_1239 = _T_1180 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_1240 = _T_1182 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_1241 = _T_1017 | _T_1185; // @[Mux.scala 27:72] + wire _T_1242 = _T_1241 | _T_1186; // @[Mux.scala 27:72] + wire _T_1243 = _T_1242 | _T_1187; // @[Mux.scala 27:72] + wire _T_1244 = _T_1243 | _T_1188; // @[Mux.scala 27:72] + wire _T_1245 = _T_1244 | _T_1189; // @[Mux.scala 27:72] + wire _T_1246 = _T_1245 | _T_1190; // @[Mux.scala 27:72] + wire _T_1247 = _T_1246 | _T_1191; // @[Mux.scala 27:72] + wire _T_1248 = _T_1247 | _T_1192; // @[Mux.scala 27:72] + wire _T_1249 = _T_1248 | _T_1193; // @[Mux.scala 27:72] + wire _T_1250 = _T_1249 | _T_1194; // @[Mux.scala 27:72] + wire _T_1251 = _T_1250 | _T_1195; // @[Mux.scala 27:72] wire _T_1252 = _T_1251 | _T_1196; // @[Mux.scala 27:72] wire _T_1253 = _T_1252 | _T_1197; // @[Mux.scala 27:72] wire _T_1254 = _T_1253 | _T_1198; // @[Mux.scala 27:72] @@ -51584,7 +51614,7 @@ module csr_tlu( wire _T_1266 = _T_1265 | _T_1210; // @[Mux.scala 27:72] wire _T_1267 = _T_1266 | _T_1211; // @[Mux.scala 27:72] wire _T_1268 = _T_1267 | _T_1212; // @[Mux.scala 27:72] - wire _T_1269 = _T_1268 | _T_1213; // @[Mux.scala 27:72] + wire _T_1269 = _T_1268 | _T_1192; // @[Mux.scala 27:72] wire _T_1270 = _T_1269 | _T_1214; // @[Mux.scala 27:72] wire _T_1271 = _T_1270 | _T_1215; // @[Mux.scala 27:72] wire _T_1272 = _T_1271 | _T_1216; // @[Mux.scala 27:72] @@ -51594,7 +51624,7 @@ module csr_tlu( wire _T_1276 = _T_1275 | _T_1220; // @[Mux.scala 27:72] wire _T_1277 = _T_1276 | _T_1221; // @[Mux.scala 27:72] wire _T_1278 = _T_1277 | _T_1222; // @[Mux.scala 27:72] - wire _T_1279 = _T_1278 | _T_1202; // @[Mux.scala 27:72] + wire _T_1279 = _T_1278 | _T_1223; // @[Mux.scala 27:72] wire _T_1280 = _T_1279 | _T_1224; // @[Mux.scala 27:72] wire _T_1281 = _T_1280 | _T_1225; // @[Mux.scala 27:72] wire _T_1282 = _T_1281 | _T_1226; // @[Mux.scala 27:72] @@ -51612,131 +51642,131 @@ module csr_tlu( wire _T_1294 = _T_1293 | _T_1238; // @[Mux.scala 27:72] wire _T_1295 = _T_1294 | _T_1239; // @[Mux.scala 27:72] wire _T_1296 = _T_1295 | _T_1240; // @[Mux.scala 27:72] - wire _T_1297 = _T_1296 | _T_1241; // @[Mux.scala 27:72] - wire _T_1298 = _T_1297 | _T_1242; // @[Mux.scala 27:72] - wire _T_1299 = _T_1298 | _T_1243; // @[Mux.scala 27:72] - wire _T_1300 = _T_1299 | _T_1244; // @[Mux.scala 27:72] - wire _T_1301 = _T_1300 | _T_1245; // @[Mux.scala 27:72] - wire _T_1302 = _T_1301 | _T_1246; // @[Mux.scala 27:72] - wire _T_1303 = _T_1302 | _T_1247; // @[Mux.scala 27:72] - wire _T_1304 = _T_1303 | _T_1248; // @[Mux.scala 27:72] - wire _T_1305 = _T_1304 | _T_1249; // @[Mux.scala 27:72] - wire _T_1306 = _T_1305 | _T_1250; // @[Mux.scala 27:72] - wire mhpmc_inc_r_0 = _T_1026 & _T_1306; // @[dec_tlu_ctl.scala 2274:44] - wire _T_1310 = ~mcountinhibit[4]; // @[dec_tlu_ctl.scala 2274:24] + wire mhpmc_inc_r_0 = _T_1016 & _T_1296; // @[dec_tlu_ctl.scala 2274:44] + wire _T_1300 = ~mcountinhibit[4]; // @[dec_tlu_ctl.scala 2274:24] reg [9:0] mhpme4; // @[Reg.scala 27:20] - wire _T_1311 = mhpme4 == 10'h1; // @[dec_tlu_ctl.scala 2275:34] - wire _T_1313 = mhpme4 == 10'h2; // @[dec_tlu_ctl.scala 2276:34] - wire _T_1315 = mhpme4 == 10'h3; // @[dec_tlu_ctl.scala 2277:34] - wire _T_1317 = mhpme4 == 10'h4; // @[dec_tlu_ctl.scala 2278:34] - wire _T_1321 = mhpme4 == 10'h5; // @[dec_tlu_ctl.scala 2279:34] - wire _T_1327 = mhpme4 == 10'h6; // @[dec_tlu_ctl.scala 2280:34] - wire _T_1332 = mhpme4 == 10'h7; // @[dec_tlu_ctl.scala 2281:34] - wire _T_1334 = mhpme4 == 10'h8; // @[dec_tlu_ctl.scala 2282:34] - wire _T_1336 = mhpme4 == 10'h1e; // @[dec_tlu_ctl.scala 2283:34] - wire _T_1338 = mhpme4 == 10'h9; // @[dec_tlu_ctl.scala 2284:34] - wire _T_1341 = mhpme4 == 10'ha; // @[dec_tlu_ctl.scala 2285:34] - wire _T_1344 = mhpme4 == 10'hb; // @[dec_tlu_ctl.scala 2286:34] - wire _T_1347 = mhpme4 == 10'hc; // @[dec_tlu_ctl.scala 2287:34] - wire _T_1350 = mhpme4 == 10'hd; // @[dec_tlu_ctl.scala 2288:34] - wire _T_1354 = mhpme4 == 10'he; // @[dec_tlu_ctl.scala 2289:34] - wire _T_1359 = mhpme4 == 10'hf; // @[dec_tlu_ctl.scala 2290:34] - wire _T_1362 = mhpme4 == 10'h10; // @[dec_tlu_ctl.scala 2291:34] - wire _T_1365 = mhpme4 == 10'h12; // @[dec_tlu_ctl.scala 2292:34] - wire _T_1368 = mhpme4 == 10'h11; // @[dec_tlu_ctl.scala 2293:34] - wire _T_1371 = mhpme4 == 10'h13; // @[dec_tlu_ctl.scala 2294:34] - wire _T_1374 = mhpme4 == 10'h14; // @[dec_tlu_ctl.scala 2295:34] - wire _T_1377 = mhpme4 == 10'h15; // @[dec_tlu_ctl.scala 2296:34] - wire _T_1380 = mhpme4 == 10'h16; // @[dec_tlu_ctl.scala 2297:34] - wire _T_1383 = mhpme4 == 10'h17; // @[dec_tlu_ctl.scala 2298:34] - wire _T_1386 = mhpme4 == 10'h18; // @[dec_tlu_ctl.scala 2299:34] - wire _T_1391 = mhpme4 == 10'h19; // @[dec_tlu_ctl.scala 2300:34] - wire _T_1394 = mhpme4 == 10'h1a; // @[dec_tlu_ctl.scala 2301:34] - wire _T_1397 = mhpme4 == 10'h1b; // @[dec_tlu_ctl.scala 2302:34] - wire _T_1400 = mhpme4 == 10'h1c; // @[dec_tlu_ctl.scala 2303:34] - wire _T_1404 = mhpme4 == 10'h1f; // @[dec_tlu_ctl.scala 2305:34] - wire _T_1406 = mhpme4 == 10'h20; // @[dec_tlu_ctl.scala 2306:34] - wire _T_1408 = mhpme4 == 10'h22; // @[dec_tlu_ctl.scala 2307:34] - wire _T_1410 = mhpme4 == 10'h23; // @[dec_tlu_ctl.scala 2308:34] - wire _T_1412 = mhpme4 == 10'h24; // @[dec_tlu_ctl.scala 2309:34] - wire _T_1414 = mhpme4 == 10'h25; // @[dec_tlu_ctl.scala 2310:34] - wire _T_1418 = mhpme4 == 10'h26; // @[dec_tlu_ctl.scala 2311:34] - wire _T_1422 = mhpme4 == 10'h27; // @[dec_tlu_ctl.scala 2312:34] - wire _T_1424 = mhpme4 == 10'h28; // @[dec_tlu_ctl.scala 2313:34] - wire _T_1426 = mhpme4 == 10'h29; // @[dec_tlu_ctl.scala 2314:34] - wire _T_1430 = mhpme4 == 10'h2a; // @[dec_tlu_ctl.scala 2315:34] - wire _T_1432 = mhpme4 == 10'h2b; // @[dec_tlu_ctl.scala 2316:34] - wire _T_1434 = mhpme4 == 10'h2c; // @[dec_tlu_ctl.scala 2317:34] - wire _T_1436 = mhpme4 == 10'h2d; // @[dec_tlu_ctl.scala 2318:34] - wire _T_1438 = mhpme4 == 10'h2e; // @[dec_tlu_ctl.scala 2319:34] - wire _T_1440 = mhpme4 == 10'h2f; // @[dec_tlu_ctl.scala 2320:34] - wire _T_1442 = mhpme4 == 10'h30; // @[dec_tlu_ctl.scala 2321:34] - wire _T_1444 = mhpme4 == 10'h31; // @[dec_tlu_ctl.scala 2322:34] - wire _T_1449 = mhpme4 == 10'h32; // @[dec_tlu_ctl.scala 2323:34] - wire _T_1459 = mhpme4 == 10'h36; // @[dec_tlu_ctl.scala 2324:34] - wire _T_1462 = mhpme4 == 10'h37; // @[dec_tlu_ctl.scala 2325:34] - wire _T_1465 = mhpme4 == 10'h38; // @[dec_tlu_ctl.scala 2326:34] - wire _T_1468 = mhpme4 == 10'h200; // @[dec_tlu_ctl.scala 2328:34] - wire _T_1470 = mhpme4 == 10'h201; // @[dec_tlu_ctl.scala 2329:34] - wire _T_1472 = mhpme4 == 10'h202; // @[dec_tlu_ctl.scala 2330:34] - wire _T_1474 = mhpme4 == 10'h203; // @[dec_tlu_ctl.scala 2331:34] - wire _T_1476 = mhpme4 == 10'h204; // @[dec_tlu_ctl.scala 2332:34] - wire _T_1479 = _T_1313 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] - wire _T_1480 = _T_1315 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] - wire _T_1481 = _T_1317 & _T_1036; // @[Mux.scala 27:72] - wire _T_1482 = _T_1321 & _T_1042; // @[Mux.scala 27:72] - wire _T_1483 = _T_1327 & _T_1047; // @[Mux.scala 27:72] - wire _T_1484 = _T_1332 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] - wire _T_1485 = _T_1334 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] - wire _T_1486 = _T_1336 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] - wire _T_1487 = _T_1338 & _T_1056; // @[Mux.scala 27:72] - wire _T_1488 = _T_1341 & _T_1059; // @[Mux.scala 27:72] - wire _T_1489 = _T_1344 & _T_1062; // @[Mux.scala 27:72] - wire _T_1490 = _T_1347 & _T_1065; // @[Mux.scala 27:72] - wire _T_1491 = _T_1350 & _T_1069; // @[Mux.scala 27:72] - wire _T_1492 = _T_1354 & _T_1074; // @[Mux.scala 27:72] - wire _T_1493 = _T_1359 & _T_1077; // @[Mux.scala 27:72] - wire _T_1494 = _T_1362 & _T_1080; // @[Mux.scala 27:72] - wire _T_1495 = _T_1365 & _T_1083; // @[Mux.scala 27:72] - wire _T_1496 = _T_1368 & _T_1086; // @[Mux.scala 27:72] - wire _T_1497 = _T_1371 & _T_1089; // @[Mux.scala 27:72] - wire _T_1498 = _T_1374 & _T_1092; // @[Mux.scala 27:72] - wire _T_1499 = _T_1377 & _T_1095; // @[Mux.scala 27:72] - wire _T_1500 = _T_1380 & _T_1098; // @[Mux.scala 27:72] - wire _T_1501 = _T_1383 & _T_1101; // @[Mux.scala 27:72] - wire _T_1502 = _T_1386 & _T_1106; // @[Mux.scala 27:72] - wire _T_1503 = _T_1391 & _T_1109; // @[Mux.scala 27:72] - wire _T_1504 = _T_1394 & _T_1112; // @[Mux.scala 27:72] - wire _T_1505 = _T_1397 & _T_1115; // @[Mux.scala 27:72] - wire _T_1506 = _T_1400 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] - wire _T_1508 = _T_1404 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] - wire _T_1509 = _T_1406 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] - wire _T_1510 = _T_1408 & io_lsu_store_stall_any; // @[Mux.scala 27:72] - wire _T_1511 = _T_1410 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] - wire _T_1512 = _T_1412 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] - wire _T_1513 = _T_1414 & _T_1133; // @[Mux.scala 27:72] - wire _T_1514 = _T_1418 & _T_1137; // @[Mux.scala 27:72] - wire _T_1515 = _T_1422 & io_take_ext_int; // @[Mux.scala 27:72] - wire _T_1516 = _T_1424 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] - wire _T_1517 = _T_1426 & _T_1145; // @[Mux.scala 27:72] - wire _T_1518 = _T_1430 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1519 = _T_1432 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1520 = _T_1434 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] - wire _T_1521 = _T_1436 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1522 = _T_1438 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1523 = _T_1440 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1524 = _T_1442 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1525 = _T_1444 & _T_1164; // @[Mux.scala 27:72] - wire _T_1526 = _T_1449 & _T_1174; // @[Mux.scala 27:72] - wire _T_1527 = _T_1459 & _T_1177; // @[Mux.scala 27:72] - wire _T_1528 = _T_1462 & _T_1180; // @[Mux.scala 27:72] - wire _T_1529 = _T_1465 & _T_1183; // @[Mux.scala 27:72] - wire _T_1530 = _T_1468 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] - wire _T_1531 = _T_1470 & io_dma_pmu_any_read; // @[Mux.scala 27:72] - wire _T_1532 = _T_1472 & io_dma_pmu_any_write; // @[Mux.scala 27:72] - wire _T_1533 = _T_1474 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] - wire _T_1534 = _T_1476 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] - wire _T_1535 = _T_1311 | _T_1479; // @[Mux.scala 27:72] + wire _T_1301 = mhpme4 == 10'h1; // @[dec_tlu_ctl.scala 2275:34] + wire _T_1303 = mhpme4 == 10'h2; // @[dec_tlu_ctl.scala 2276:34] + wire _T_1305 = mhpme4 == 10'h3; // @[dec_tlu_ctl.scala 2277:34] + wire _T_1307 = mhpme4 == 10'h4; // @[dec_tlu_ctl.scala 2278:34] + wire _T_1311 = mhpme4 == 10'h5; // @[dec_tlu_ctl.scala 2279:34] + wire _T_1317 = mhpme4 == 10'h6; // @[dec_tlu_ctl.scala 2280:34] + wire _T_1322 = mhpme4 == 10'h7; // @[dec_tlu_ctl.scala 2281:34] + wire _T_1324 = mhpme4 == 10'h8; // @[dec_tlu_ctl.scala 2282:34] + wire _T_1326 = mhpme4 == 10'h1e; // @[dec_tlu_ctl.scala 2283:34] + wire _T_1328 = mhpme4 == 10'h9; // @[dec_tlu_ctl.scala 2284:34] + wire _T_1331 = mhpme4 == 10'ha; // @[dec_tlu_ctl.scala 2285:34] + wire _T_1334 = mhpme4 == 10'hb; // @[dec_tlu_ctl.scala 2286:34] + wire _T_1337 = mhpme4 == 10'hc; // @[dec_tlu_ctl.scala 2287:34] + wire _T_1340 = mhpme4 == 10'hd; // @[dec_tlu_ctl.scala 2288:34] + wire _T_1344 = mhpme4 == 10'he; // @[dec_tlu_ctl.scala 2289:34] + wire _T_1349 = mhpme4 == 10'hf; // @[dec_tlu_ctl.scala 2290:34] + wire _T_1352 = mhpme4 == 10'h10; // @[dec_tlu_ctl.scala 2291:34] + wire _T_1355 = mhpme4 == 10'h12; // @[dec_tlu_ctl.scala 2292:34] + wire _T_1358 = mhpme4 == 10'h11; // @[dec_tlu_ctl.scala 2293:34] + wire _T_1361 = mhpme4 == 10'h13; // @[dec_tlu_ctl.scala 2294:34] + wire _T_1364 = mhpme4 == 10'h14; // @[dec_tlu_ctl.scala 2295:34] + wire _T_1367 = mhpme4 == 10'h15; // @[dec_tlu_ctl.scala 2296:34] + wire _T_1370 = mhpme4 == 10'h16; // @[dec_tlu_ctl.scala 2297:34] + wire _T_1373 = mhpme4 == 10'h17; // @[dec_tlu_ctl.scala 2298:34] + wire _T_1376 = mhpme4 == 10'h18; // @[dec_tlu_ctl.scala 2299:34] + wire _T_1381 = mhpme4 == 10'h19; // @[dec_tlu_ctl.scala 2300:34] + wire _T_1384 = mhpme4 == 10'h1a; // @[dec_tlu_ctl.scala 2301:34] + wire _T_1387 = mhpme4 == 10'h1b; // @[dec_tlu_ctl.scala 2302:34] + wire _T_1390 = mhpme4 == 10'h1c; // @[dec_tlu_ctl.scala 2303:34] + wire _T_1394 = mhpme4 == 10'h1f; // @[dec_tlu_ctl.scala 2305:34] + wire _T_1396 = mhpme4 == 10'h20; // @[dec_tlu_ctl.scala 2306:34] + wire _T_1398 = mhpme4 == 10'h22; // @[dec_tlu_ctl.scala 2307:34] + wire _T_1400 = mhpme4 == 10'h23; // @[dec_tlu_ctl.scala 2308:34] + wire _T_1402 = mhpme4 == 10'h24; // @[dec_tlu_ctl.scala 2309:34] + wire _T_1404 = mhpme4 == 10'h25; // @[dec_tlu_ctl.scala 2310:34] + wire _T_1408 = mhpme4 == 10'h26; // @[dec_tlu_ctl.scala 2311:34] + wire _T_1412 = mhpme4 == 10'h27; // @[dec_tlu_ctl.scala 2312:34] + wire _T_1414 = mhpme4 == 10'h28; // @[dec_tlu_ctl.scala 2313:34] + wire _T_1416 = mhpme4 == 10'h29; // @[dec_tlu_ctl.scala 2314:34] + wire _T_1420 = mhpme4 == 10'h2a; // @[dec_tlu_ctl.scala 2315:34] + wire _T_1422 = mhpme4 == 10'h2b; // @[dec_tlu_ctl.scala 2316:34] + wire _T_1424 = mhpme4 == 10'h2c; // @[dec_tlu_ctl.scala 2317:34] + wire _T_1426 = mhpme4 == 10'h2d; // @[dec_tlu_ctl.scala 2318:34] + wire _T_1428 = mhpme4 == 10'h2e; // @[dec_tlu_ctl.scala 2319:34] + wire _T_1430 = mhpme4 == 10'h2f; // @[dec_tlu_ctl.scala 2320:34] + wire _T_1432 = mhpme4 == 10'h30; // @[dec_tlu_ctl.scala 2321:34] + wire _T_1434 = mhpme4 == 10'h31; // @[dec_tlu_ctl.scala 2322:34] + wire _T_1439 = mhpme4 == 10'h32; // @[dec_tlu_ctl.scala 2323:34] + wire _T_1449 = mhpme4 == 10'h36; // @[dec_tlu_ctl.scala 2324:34] + wire _T_1452 = mhpme4 == 10'h37; // @[dec_tlu_ctl.scala 2325:34] + wire _T_1455 = mhpme4 == 10'h38; // @[dec_tlu_ctl.scala 2326:34] + wire _T_1458 = mhpme4 == 10'h200; // @[dec_tlu_ctl.scala 2328:34] + wire _T_1460 = mhpme4 == 10'h201; // @[dec_tlu_ctl.scala 2329:34] + wire _T_1462 = mhpme4 == 10'h202; // @[dec_tlu_ctl.scala 2330:34] + wire _T_1464 = mhpme4 == 10'h203; // @[dec_tlu_ctl.scala 2331:34] + wire _T_1466 = mhpme4 == 10'h204; // @[dec_tlu_ctl.scala 2332:34] + wire _T_1469 = _T_1303 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_1470 = _T_1305 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_1471 = _T_1307 & _T_1026; // @[Mux.scala 27:72] + wire _T_1472 = _T_1311 & _T_1032; // @[Mux.scala 27:72] + wire _T_1473 = _T_1317 & _T_1037; // @[Mux.scala 27:72] + wire _T_1474 = _T_1322 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_1475 = _T_1324 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_1476 = _T_1326 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_1477 = _T_1328 & _T_1046; // @[Mux.scala 27:72] + wire _T_1478 = _T_1331 & _T_1049; // @[Mux.scala 27:72] + wire _T_1479 = _T_1334 & _T_1052; // @[Mux.scala 27:72] + wire _T_1480 = _T_1337 & _T_1055; // @[Mux.scala 27:72] + wire _T_1481 = _T_1340 & _T_1059; // @[Mux.scala 27:72] + wire _T_1482 = _T_1344 & _T_1064; // @[Mux.scala 27:72] + wire _T_1483 = _T_1349 & _T_1067; // @[Mux.scala 27:72] + wire _T_1484 = _T_1352 & _T_1070; // @[Mux.scala 27:72] + wire _T_1485 = _T_1355 & _T_1073; // @[Mux.scala 27:72] + wire _T_1486 = _T_1358 & _T_1076; // @[Mux.scala 27:72] + wire _T_1487 = _T_1361 & _T_1079; // @[Mux.scala 27:72] + wire _T_1488 = _T_1364 & _T_1082; // @[Mux.scala 27:72] + wire _T_1489 = _T_1367 & _T_1085; // @[Mux.scala 27:72] + wire _T_1490 = _T_1370 & _T_1088; // @[Mux.scala 27:72] + wire _T_1491 = _T_1373 & _T_1091; // @[Mux.scala 27:72] + wire _T_1492 = _T_1376 & _T_1096; // @[Mux.scala 27:72] + wire _T_1493 = _T_1381 & _T_1099; // @[Mux.scala 27:72] + wire _T_1494 = _T_1384 & _T_1102; // @[Mux.scala 27:72] + wire _T_1495 = _T_1387 & _T_1105; // @[Mux.scala 27:72] + wire _T_1496 = _T_1390 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_1498 = _T_1394 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_1499 = _T_1396 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_1500 = _T_1398 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_1501 = _T_1400 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_1502 = _T_1402 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_1503 = _T_1404 & _T_1123; // @[Mux.scala 27:72] + wire _T_1504 = _T_1408 & _T_1127; // @[Mux.scala 27:72] + wire _T_1505 = _T_1412 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_1506 = _T_1414 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_1507 = _T_1416 & _T_1135; // @[Mux.scala 27:72] + wire _T_1508 = _T_1420 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1509 = _T_1422 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1510 = _T_1424 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_1511 = _T_1426 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1512 = _T_1428 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1513 = _T_1430 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1514 = _T_1432 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1515 = _T_1434 & _T_1154; // @[Mux.scala 27:72] + wire _T_1516 = _T_1439 & _T_1164; // @[Mux.scala 27:72] + wire _T_1517 = _T_1449 & _T_1167; // @[Mux.scala 27:72] + wire _T_1518 = _T_1452 & _T_1170; // @[Mux.scala 27:72] + wire _T_1519 = _T_1455 & _T_1173; // @[Mux.scala 27:72] + wire _T_1520 = _T_1458 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_1521 = _T_1460 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_1522 = _T_1462 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_1523 = _T_1464 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_1524 = _T_1466 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_1525 = _T_1301 | _T_1469; // @[Mux.scala 27:72] + wire _T_1526 = _T_1525 | _T_1470; // @[Mux.scala 27:72] + wire _T_1527 = _T_1526 | _T_1471; // @[Mux.scala 27:72] + wire _T_1528 = _T_1527 | _T_1472; // @[Mux.scala 27:72] + wire _T_1529 = _T_1528 | _T_1473; // @[Mux.scala 27:72] + wire _T_1530 = _T_1529 | _T_1474; // @[Mux.scala 27:72] + wire _T_1531 = _T_1530 | _T_1475; // @[Mux.scala 27:72] + wire _T_1532 = _T_1531 | _T_1476; // @[Mux.scala 27:72] + wire _T_1533 = _T_1532 | _T_1477; // @[Mux.scala 27:72] + wire _T_1534 = _T_1533 | _T_1478; // @[Mux.scala 27:72] + wire _T_1535 = _T_1534 | _T_1479; // @[Mux.scala 27:72] wire _T_1536 = _T_1535 | _T_1480; // @[Mux.scala 27:72] wire _T_1537 = _T_1536 | _T_1481; // @[Mux.scala 27:72] wire _T_1538 = _T_1537 | _T_1482; // @[Mux.scala 27:72] @@ -51754,7 +51784,7 @@ module csr_tlu( wire _T_1550 = _T_1549 | _T_1494; // @[Mux.scala 27:72] wire _T_1551 = _T_1550 | _T_1495; // @[Mux.scala 27:72] wire _T_1552 = _T_1551 | _T_1496; // @[Mux.scala 27:72] - wire _T_1553 = _T_1552 | _T_1497; // @[Mux.scala 27:72] + wire _T_1553 = _T_1552 | _T_1476; // @[Mux.scala 27:72] wire _T_1554 = _T_1553 | _T_1498; // @[Mux.scala 27:72] wire _T_1555 = _T_1554 | _T_1499; // @[Mux.scala 27:72] wire _T_1556 = _T_1555 | _T_1500; // @[Mux.scala 27:72] @@ -51764,7 +51794,7 @@ module csr_tlu( wire _T_1560 = _T_1559 | _T_1504; // @[Mux.scala 27:72] wire _T_1561 = _T_1560 | _T_1505; // @[Mux.scala 27:72] wire _T_1562 = _T_1561 | _T_1506; // @[Mux.scala 27:72] - wire _T_1563 = _T_1562 | _T_1486; // @[Mux.scala 27:72] + wire _T_1563 = _T_1562 | _T_1507; // @[Mux.scala 27:72] wire _T_1564 = _T_1563 | _T_1508; // @[Mux.scala 27:72] wire _T_1565 = _T_1564 | _T_1509; // @[Mux.scala 27:72] wire _T_1566 = _T_1565 | _T_1510; // @[Mux.scala 27:72] @@ -51782,131 +51812,131 @@ module csr_tlu( wire _T_1578 = _T_1577 | _T_1522; // @[Mux.scala 27:72] wire _T_1579 = _T_1578 | _T_1523; // @[Mux.scala 27:72] wire _T_1580 = _T_1579 | _T_1524; // @[Mux.scala 27:72] - wire _T_1581 = _T_1580 | _T_1525; // @[Mux.scala 27:72] - wire _T_1582 = _T_1581 | _T_1526; // @[Mux.scala 27:72] - wire _T_1583 = _T_1582 | _T_1527; // @[Mux.scala 27:72] - wire _T_1584 = _T_1583 | _T_1528; // @[Mux.scala 27:72] - wire _T_1585 = _T_1584 | _T_1529; // @[Mux.scala 27:72] - wire _T_1586 = _T_1585 | _T_1530; // @[Mux.scala 27:72] - wire _T_1587 = _T_1586 | _T_1531; // @[Mux.scala 27:72] - wire _T_1588 = _T_1587 | _T_1532; // @[Mux.scala 27:72] - wire _T_1589 = _T_1588 | _T_1533; // @[Mux.scala 27:72] - wire _T_1590 = _T_1589 | _T_1534; // @[Mux.scala 27:72] - wire mhpmc_inc_r_1 = _T_1310 & _T_1590; // @[dec_tlu_ctl.scala 2274:44] - wire _T_1594 = ~mcountinhibit[5]; // @[dec_tlu_ctl.scala 2274:24] + wire mhpmc_inc_r_1 = _T_1300 & _T_1580; // @[dec_tlu_ctl.scala 2274:44] + wire _T_1584 = ~mcountinhibit[5]; // @[dec_tlu_ctl.scala 2274:24] reg [9:0] mhpme5; // @[Reg.scala 27:20] - wire _T_1595 = mhpme5 == 10'h1; // @[dec_tlu_ctl.scala 2275:34] - wire _T_1597 = mhpme5 == 10'h2; // @[dec_tlu_ctl.scala 2276:34] - wire _T_1599 = mhpme5 == 10'h3; // @[dec_tlu_ctl.scala 2277:34] - wire _T_1601 = mhpme5 == 10'h4; // @[dec_tlu_ctl.scala 2278:34] - wire _T_1605 = mhpme5 == 10'h5; // @[dec_tlu_ctl.scala 2279:34] - wire _T_1611 = mhpme5 == 10'h6; // @[dec_tlu_ctl.scala 2280:34] - wire _T_1616 = mhpme5 == 10'h7; // @[dec_tlu_ctl.scala 2281:34] - wire _T_1618 = mhpme5 == 10'h8; // @[dec_tlu_ctl.scala 2282:34] - wire _T_1620 = mhpme5 == 10'h1e; // @[dec_tlu_ctl.scala 2283:34] - wire _T_1622 = mhpme5 == 10'h9; // @[dec_tlu_ctl.scala 2284:34] - wire _T_1625 = mhpme5 == 10'ha; // @[dec_tlu_ctl.scala 2285:34] - wire _T_1628 = mhpme5 == 10'hb; // @[dec_tlu_ctl.scala 2286:34] - wire _T_1631 = mhpme5 == 10'hc; // @[dec_tlu_ctl.scala 2287:34] - wire _T_1634 = mhpme5 == 10'hd; // @[dec_tlu_ctl.scala 2288:34] - wire _T_1638 = mhpme5 == 10'he; // @[dec_tlu_ctl.scala 2289:34] - wire _T_1643 = mhpme5 == 10'hf; // @[dec_tlu_ctl.scala 2290:34] - wire _T_1646 = mhpme5 == 10'h10; // @[dec_tlu_ctl.scala 2291:34] - wire _T_1649 = mhpme5 == 10'h12; // @[dec_tlu_ctl.scala 2292:34] - wire _T_1652 = mhpme5 == 10'h11; // @[dec_tlu_ctl.scala 2293:34] - wire _T_1655 = mhpme5 == 10'h13; // @[dec_tlu_ctl.scala 2294:34] - wire _T_1658 = mhpme5 == 10'h14; // @[dec_tlu_ctl.scala 2295:34] - wire _T_1661 = mhpme5 == 10'h15; // @[dec_tlu_ctl.scala 2296:34] - wire _T_1664 = mhpme5 == 10'h16; // @[dec_tlu_ctl.scala 2297:34] - wire _T_1667 = mhpme5 == 10'h17; // @[dec_tlu_ctl.scala 2298:34] - wire _T_1670 = mhpme5 == 10'h18; // @[dec_tlu_ctl.scala 2299:34] - wire _T_1675 = mhpme5 == 10'h19; // @[dec_tlu_ctl.scala 2300:34] - wire _T_1678 = mhpme5 == 10'h1a; // @[dec_tlu_ctl.scala 2301:34] - wire _T_1681 = mhpme5 == 10'h1b; // @[dec_tlu_ctl.scala 2302:34] - wire _T_1684 = mhpme5 == 10'h1c; // @[dec_tlu_ctl.scala 2303:34] - wire _T_1688 = mhpme5 == 10'h1f; // @[dec_tlu_ctl.scala 2305:34] - wire _T_1690 = mhpme5 == 10'h20; // @[dec_tlu_ctl.scala 2306:34] - wire _T_1692 = mhpme5 == 10'h22; // @[dec_tlu_ctl.scala 2307:34] - wire _T_1694 = mhpme5 == 10'h23; // @[dec_tlu_ctl.scala 2308:34] - wire _T_1696 = mhpme5 == 10'h24; // @[dec_tlu_ctl.scala 2309:34] - wire _T_1698 = mhpme5 == 10'h25; // @[dec_tlu_ctl.scala 2310:34] - wire _T_1702 = mhpme5 == 10'h26; // @[dec_tlu_ctl.scala 2311:34] - wire _T_1706 = mhpme5 == 10'h27; // @[dec_tlu_ctl.scala 2312:34] - wire _T_1708 = mhpme5 == 10'h28; // @[dec_tlu_ctl.scala 2313:34] - wire _T_1710 = mhpme5 == 10'h29; // @[dec_tlu_ctl.scala 2314:34] - wire _T_1714 = mhpme5 == 10'h2a; // @[dec_tlu_ctl.scala 2315:34] - wire _T_1716 = mhpme5 == 10'h2b; // @[dec_tlu_ctl.scala 2316:34] - wire _T_1718 = mhpme5 == 10'h2c; // @[dec_tlu_ctl.scala 2317:34] - wire _T_1720 = mhpme5 == 10'h2d; // @[dec_tlu_ctl.scala 2318:34] - wire _T_1722 = mhpme5 == 10'h2e; // @[dec_tlu_ctl.scala 2319:34] - wire _T_1724 = mhpme5 == 10'h2f; // @[dec_tlu_ctl.scala 2320:34] - wire _T_1726 = mhpme5 == 10'h30; // @[dec_tlu_ctl.scala 2321:34] - wire _T_1728 = mhpme5 == 10'h31; // @[dec_tlu_ctl.scala 2322:34] - wire _T_1733 = mhpme5 == 10'h32; // @[dec_tlu_ctl.scala 2323:34] - wire _T_1743 = mhpme5 == 10'h36; // @[dec_tlu_ctl.scala 2324:34] - wire _T_1746 = mhpme5 == 10'h37; // @[dec_tlu_ctl.scala 2325:34] - wire _T_1749 = mhpme5 == 10'h38; // @[dec_tlu_ctl.scala 2326:34] - wire _T_1752 = mhpme5 == 10'h200; // @[dec_tlu_ctl.scala 2328:34] - wire _T_1754 = mhpme5 == 10'h201; // @[dec_tlu_ctl.scala 2329:34] - wire _T_1756 = mhpme5 == 10'h202; // @[dec_tlu_ctl.scala 2330:34] - wire _T_1758 = mhpme5 == 10'h203; // @[dec_tlu_ctl.scala 2331:34] - wire _T_1760 = mhpme5 == 10'h204; // @[dec_tlu_ctl.scala 2332:34] - wire _T_1763 = _T_1597 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] - wire _T_1764 = _T_1599 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] - wire _T_1765 = _T_1601 & _T_1036; // @[Mux.scala 27:72] - wire _T_1766 = _T_1605 & _T_1042; // @[Mux.scala 27:72] - wire _T_1767 = _T_1611 & _T_1047; // @[Mux.scala 27:72] - wire _T_1768 = _T_1616 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] - wire _T_1769 = _T_1618 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] - wire _T_1770 = _T_1620 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] - wire _T_1771 = _T_1622 & _T_1056; // @[Mux.scala 27:72] - wire _T_1772 = _T_1625 & _T_1059; // @[Mux.scala 27:72] - wire _T_1773 = _T_1628 & _T_1062; // @[Mux.scala 27:72] - wire _T_1774 = _T_1631 & _T_1065; // @[Mux.scala 27:72] - wire _T_1775 = _T_1634 & _T_1069; // @[Mux.scala 27:72] - wire _T_1776 = _T_1638 & _T_1074; // @[Mux.scala 27:72] - wire _T_1777 = _T_1643 & _T_1077; // @[Mux.scala 27:72] - wire _T_1778 = _T_1646 & _T_1080; // @[Mux.scala 27:72] - wire _T_1779 = _T_1649 & _T_1083; // @[Mux.scala 27:72] - wire _T_1780 = _T_1652 & _T_1086; // @[Mux.scala 27:72] - wire _T_1781 = _T_1655 & _T_1089; // @[Mux.scala 27:72] - wire _T_1782 = _T_1658 & _T_1092; // @[Mux.scala 27:72] - wire _T_1783 = _T_1661 & _T_1095; // @[Mux.scala 27:72] - wire _T_1784 = _T_1664 & _T_1098; // @[Mux.scala 27:72] - wire _T_1785 = _T_1667 & _T_1101; // @[Mux.scala 27:72] - wire _T_1786 = _T_1670 & _T_1106; // @[Mux.scala 27:72] - wire _T_1787 = _T_1675 & _T_1109; // @[Mux.scala 27:72] - wire _T_1788 = _T_1678 & _T_1112; // @[Mux.scala 27:72] - wire _T_1789 = _T_1681 & _T_1115; // @[Mux.scala 27:72] - wire _T_1790 = _T_1684 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] - wire _T_1792 = _T_1688 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] - wire _T_1793 = _T_1690 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] - wire _T_1794 = _T_1692 & io_lsu_store_stall_any; // @[Mux.scala 27:72] - wire _T_1795 = _T_1694 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] - wire _T_1796 = _T_1696 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] - wire _T_1797 = _T_1698 & _T_1133; // @[Mux.scala 27:72] - wire _T_1798 = _T_1702 & _T_1137; // @[Mux.scala 27:72] - wire _T_1799 = _T_1706 & io_take_ext_int; // @[Mux.scala 27:72] - wire _T_1800 = _T_1708 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] - wire _T_1801 = _T_1710 & _T_1145; // @[Mux.scala 27:72] - wire _T_1802 = _T_1714 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1803 = _T_1716 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1804 = _T_1718 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] - wire _T_1805 = _T_1720 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1806 = _T_1722 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1807 = _T_1724 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1808 = _T_1726 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1809 = _T_1728 & _T_1164; // @[Mux.scala 27:72] - wire _T_1810 = _T_1733 & _T_1174; // @[Mux.scala 27:72] - wire _T_1811 = _T_1743 & _T_1177; // @[Mux.scala 27:72] - wire _T_1812 = _T_1746 & _T_1180; // @[Mux.scala 27:72] - wire _T_1813 = _T_1749 & _T_1183; // @[Mux.scala 27:72] - wire _T_1814 = _T_1752 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] - wire _T_1815 = _T_1754 & io_dma_pmu_any_read; // @[Mux.scala 27:72] - wire _T_1816 = _T_1756 & io_dma_pmu_any_write; // @[Mux.scala 27:72] - wire _T_1817 = _T_1758 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] - wire _T_1818 = _T_1760 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] - wire _T_1819 = _T_1595 | _T_1763; // @[Mux.scala 27:72] + wire _T_1585 = mhpme5 == 10'h1; // @[dec_tlu_ctl.scala 2275:34] + wire _T_1587 = mhpme5 == 10'h2; // @[dec_tlu_ctl.scala 2276:34] + wire _T_1589 = mhpme5 == 10'h3; // @[dec_tlu_ctl.scala 2277:34] + wire _T_1591 = mhpme5 == 10'h4; // @[dec_tlu_ctl.scala 2278:34] + wire _T_1595 = mhpme5 == 10'h5; // @[dec_tlu_ctl.scala 2279:34] + wire _T_1601 = mhpme5 == 10'h6; // @[dec_tlu_ctl.scala 2280:34] + wire _T_1606 = mhpme5 == 10'h7; // @[dec_tlu_ctl.scala 2281:34] + wire _T_1608 = mhpme5 == 10'h8; // @[dec_tlu_ctl.scala 2282:34] + wire _T_1610 = mhpme5 == 10'h1e; // @[dec_tlu_ctl.scala 2283:34] + wire _T_1612 = mhpme5 == 10'h9; // @[dec_tlu_ctl.scala 2284:34] + wire _T_1615 = mhpme5 == 10'ha; // @[dec_tlu_ctl.scala 2285:34] + wire _T_1618 = mhpme5 == 10'hb; // @[dec_tlu_ctl.scala 2286:34] + wire _T_1621 = mhpme5 == 10'hc; // @[dec_tlu_ctl.scala 2287:34] + wire _T_1624 = mhpme5 == 10'hd; // @[dec_tlu_ctl.scala 2288:34] + wire _T_1628 = mhpme5 == 10'he; // @[dec_tlu_ctl.scala 2289:34] + wire _T_1633 = mhpme5 == 10'hf; // @[dec_tlu_ctl.scala 2290:34] + wire _T_1636 = mhpme5 == 10'h10; // @[dec_tlu_ctl.scala 2291:34] + wire _T_1639 = mhpme5 == 10'h12; // @[dec_tlu_ctl.scala 2292:34] + wire _T_1642 = mhpme5 == 10'h11; // @[dec_tlu_ctl.scala 2293:34] + wire _T_1645 = mhpme5 == 10'h13; // @[dec_tlu_ctl.scala 2294:34] + wire _T_1648 = mhpme5 == 10'h14; // @[dec_tlu_ctl.scala 2295:34] + wire _T_1651 = mhpme5 == 10'h15; // @[dec_tlu_ctl.scala 2296:34] + wire _T_1654 = mhpme5 == 10'h16; // @[dec_tlu_ctl.scala 2297:34] + wire _T_1657 = mhpme5 == 10'h17; // @[dec_tlu_ctl.scala 2298:34] + wire _T_1660 = mhpme5 == 10'h18; // @[dec_tlu_ctl.scala 2299:34] + wire _T_1665 = mhpme5 == 10'h19; // @[dec_tlu_ctl.scala 2300:34] + wire _T_1668 = mhpme5 == 10'h1a; // @[dec_tlu_ctl.scala 2301:34] + wire _T_1671 = mhpme5 == 10'h1b; // @[dec_tlu_ctl.scala 2302:34] + wire _T_1674 = mhpme5 == 10'h1c; // @[dec_tlu_ctl.scala 2303:34] + wire _T_1678 = mhpme5 == 10'h1f; // @[dec_tlu_ctl.scala 2305:34] + wire _T_1680 = mhpme5 == 10'h20; // @[dec_tlu_ctl.scala 2306:34] + wire _T_1682 = mhpme5 == 10'h22; // @[dec_tlu_ctl.scala 2307:34] + wire _T_1684 = mhpme5 == 10'h23; // @[dec_tlu_ctl.scala 2308:34] + wire _T_1686 = mhpme5 == 10'h24; // @[dec_tlu_ctl.scala 2309:34] + wire _T_1688 = mhpme5 == 10'h25; // @[dec_tlu_ctl.scala 2310:34] + wire _T_1692 = mhpme5 == 10'h26; // @[dec_tlu_ctl.scala 2311:34] + wire _T_1696 = mhpme5 == 10'h27; // @[dec_tlu_ctl.scala 2312:34] + wire _T_1698 = mhpme5 == 10'h28; // @[dec_tlu_ctl.scala 2313:34] + wire _T_1700 = mhpme5 == 10'h29; // @[dec_tlu_ctl.scala 2314:34] + wire _T_1704 = mhpme5 == 10'h2a; // @[dec_tlu_ctl.scala 2315:34] + wire _T_1706 = mhpme5 == 10'h2b; // @[dec_tlu_ctl.scala 2316:34] + wire _T_1708 = mhpme5 == 10'h2c; // @[dec_tlu_ctl.scala 2317:34] + wire _T_1710 = mhpme5 == 10'h2d; // @[dec_tlu_ctl.scala 2318:34] + wire _T_1712 = mhpme5 == 10'h2e; // @[dec_tlu_ctl.scala 2319:34] + wire _T_1714 = mhpme5 == 10'h2f; // @[dec_tlu_ctl.scala 2320:34] + wire _T_1716 = mhpme5 == 10'h30; // @[dec_tlu_ctl.scala 2321:34] + wire _T_1718 = mhpme5 == 10'h31; // @[dec_tlu_ctl.scala 2322:34] + wire _T_1723 = mhpme5 == 10'h32; // @[dec_tlu_ctl.scala 2323:34] + wire _T_1733 = mhpme5 == 10'h36; // @[dec_tlu_ctl.scala 2324:34] + wire _T_1736 = mhpme5 == 10'h37; // @[dec_tlu_ctl.scala 2325:34] + wire _T_1739 = mhpme5 == 10'h38; // @[dec_tlu_ctl.scala 2326:34] + wire _T_1742 = mhpme5 == 10'h200; // @[dec_tlu_ctl.scala 2328:34] + wire _T_1744 = mhpme5 == 10'h201; // @[dec_tlu_ctl.scala 2329:34] + wire _T_1746 = mhpme5 == 10'h202; // @[dec_tlu_ctl.scala 2330:34] + wire _T_1748 = mhpme5 == 10'h203; // @[dec_tlu_ctl.scala 2331:34] + wire _T_1750 = mhpme5 == 10'h204; // @[dec_tlu_ctl.scala 2332:34] + wire _T_1753 = _T_1587 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_1754 = _T_1589 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_1755 = _T_1591 & _T_1026; // @[Mux.scala 27:72] + wire _T_1756 = _T_1595 & _T_1032; // @[Mux.scala 27:72] + wire _T_1757 = _T_1601 & _T_1037; // @[Mux.scala 27:72] + wire _T_1758 = _T_1606 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_1759 = _T_1608 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_1760 = _T_1610 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_1761 = _T_1612 & _T_1046; // @[Mux.scala 27:72] + wire _T_1762 = _T_1615 & _T_1049; // @[Mux.scala 27:72] + wire _T_1763 = _T_1618 & _T_1052; // @[Mux.scala 27:72] + wire _T_1764 = _T_1621 & _T_1055; // @[Mux.scala 27:72] + wire _T_1765 = _T_1624 & _T_1059; // @[Mux.scala 27:72] + wire _T_1766 = _T_1628 & _T_1064; // @[Mux.scala 27:72] + wire _T_1767 = _T_1633 & _T_1067; // @[Mux.scala 27:72] + wire _T_1768 = _T_1636 & _T_1070; // @[Mux.scala 27:72] + wire _T_1769 = _T_1639 & _T_1073; // @[Mux.scala 27:72] + wire _T_1770 = _T_1642 & _T_1076; // @[Mux.scala 27:72] + wire _T_1771 = _T_1645 & _T_1079; // @[Mux.scala 27:72] + wire _T_1772 = _T_1648 & _T_1082; // @[Mux.scala 27:72] + wire _T_1773 = _T_1651 & _T_1085; // @[Mux.scala 27:72] + wire _T_1774 = _T_1654 & _T_1088; // @[Mux.scala 27:72] + wire _T_1775 = _T_1657 & _T_1091; // @[Mux.scala 27:72] + wire _T_1776 = _T_1660 & _T_1096; // @[Mux.scala 27:72] + wire _T_1777 = _T_1665 & _T_1099; // @[Mux.scala 27:72] + wire _T_1778 = _T_1668 & _T_1102; // @[Mux.scala 27:72] + wire _T_1779 = _T_1671 & _T_1105; // @[Mux.scala 27:72] + wire _T_1780 = _T_1674 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_1782 = _T_1678 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_1783 = _T_1680 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_1784 = _T_1682 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_1785 = _T_1684 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_1786 = _T_1686 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_1787 = _T_1688 & _T_1123; // @[Mux.scala 27:72] + wire _T_1788 = _T_1692 & _T_1127; // @[Mux.scala 27:72] + wire _T_1789 = _T_1696 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_1790 = _T_1698 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_1791 = _T_1700 & _T_1135; // @[Mux.scala 27:72] + wire _T_1792 = _T_1704 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1793 = _T_1706 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1794 = _T_1708 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_1795 = _T_1710 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1796 = _T_1712 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1797 = _T_1714 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1798 = _T_1716 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1799 = _T_1718 & _T_1154; // @[Mux.scala 27:72] + wire _T_1800 = _T_1723 & _T_1164; // @[Mux.scala 27:72] + wire _T_1801 = _T_1733 & _T_1167; // @[Mux.scala 27:72] + wire _T_1802 = _T_1736 & _T_1170; // @[Mux.scala 27:72] + wire _T_1803 = _T_1739 & _T_1173; // @[Mux.scala 27:72] + wire _T_1804 = _T_1742 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_1805 = _T_1744 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_1806 = _T_1746 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_1807 = _T_1748 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_1808 = _T_1750 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_1809 = _T_1585 | _T_1753; // @[Mux.scala 27:72] + wire _T_1810 = _T_1809 | _T_1754; // @[Mux.scala 27:72] + wire _T_1811 = _T_1810 | _T_1755; // @[Mux.scala 27:72] + wire _T_1812 = _T_1811 | _T_1756; // @[Mux.scala 27:72] + wire _T_1813 = _T_1812 | _T_1757; // @[Mux.scala 27:72] + wire _T_1814 = _T_1813 | _T_1758; // @[Mux.scala 27:72] + wire _T_1815 = _T_1814 | _T_1759; // @[Mux.scala 27:72] + wire _T_1816 = _T_1815 | _T_1760; // @[Mux.scala 27:72] + wire _T_1817 = _T_1816 | _T_1761; // @[Mux.scala 27:72] + wire _T_1818 = _T_1817 | _T_1762; // @[Mux.scala 27:72] + wire _T_1819 = _T_1818 | _T_1763; // @[Mux.scala 27:72] wire _T_1820 = _T_1819 | _T_1764; // @[Mux.scala 27:72] wire _T_1821 = _T_1820 | _T_1765; // @[Mux.scala 27:72] wire _T_1822 = _T_1821 | _T_1766; // @[Mux.scala 27:72] @@ -51924,7 +51954,7 @@ module csr_tlu( wire _T_1834 = _T_1833 | _T_1778; // @[Mux.scala 27:72] wire _T_1835 = _T_1834 | _T_1779; // @[Mux.scala 27:72] wire _T_1836 = _T_1835 | _T_1780; // @[Mux.scala 27:72] - wire _T_1837 = _T_1836 | _T_1781; // @[Mux.scala 27:72] + wire _T_1837 = _T_1836 | _T_1760; // @[Mux.scala 27:72] wire _T_1838 = _T_1837 | _T_1782; // @[Mux.scala 27:72] wire _T_1839 = _T_1838 | _T_1783; // @[Mux.scala 27:72] wire _T_1840 = _T_1839 | _T_1784; // @[Mux.scala 27:72] @@ -51934,7 +51964,7 @@ module csr_tlu( wire _T_1844 = _T_1843 | _T_1788; // @[Mux.scala 27:72] wire _T_1845 = _T_1844 | _T_1789; // @[Mux.scala 27:72] wire _T_1846 = _T_1845 | _T_1790; // @[Mux.scala 27:72] - wire _T_1847 = _T_1846 | _T_1770; // @[Mux.scala 27:72] + wire _T_1847 = _T_1846 | _T_1791; // @[Mux.scala 27:72] wire _T_1848 = _T_1847 | _T_1792; // @[Mux.scala 27:72] wire _T_1849 = _T_1848 | _T_1793; // @[Mux.scala 27:72] wire _T_1850 = _T_1849 | _T_1794; // @[Mux.scala 27:72] @@ -51952,131 +51982,131 @@ module csr_tlu( wire _T_1862 = _T_1861 | _T_1806; // @[Mux.scala 27:72] wire _T_1863 = _T_1862 | _T_1807; // @[Mux.scala 27:72] wire _T_1864 = _T_1863 | _T_1808; // @[Mux.scala 27:72] - wire _T_1865 = _T_1864 | _T_1809; // @[Mux.scala 27:72] - wire _T_1866 = _T_1865 | _T_1810; // @[Mux.scala 27:72] - wire _T_1867 = _T_1866 | _T_1811; // @[Mux.scala 27:72] - wire _T_1868 = _T_1867 | _T_1812; // @[Mux.scala 27:72] - wire _T_1869 = _T_1868 | _T_1813; // @[Mux.scala 27:72] - wire _T_1870 = _T_1869 | _T_1814; // @[Mux.scala 27:72] - wire _T_1871 = _T_1870 | _T_1815; // @[Mux.scala 27:72] - wire _T_1872 = _T_1871 | _T_1816; // @[Mux.scala 27:72] - wire _T_1873 = _T_1872 | _T_1817; // @[Mux.scala 27:72] - wire _T_1874 = _T_1873 | _T_1818; // @[Mux.scala 27:72] - wire mhpmc_inc_r_2 = _T_1594 & _T_1874; // @[dec_tlu_ctl.scala 2274:44] - wire _T_1878 = ~mcountinhibit[6]; // @[dec_tlu_ctl.scala 2274:24] + wire mhpmc_inc_r_2 = _T_1584 & _T_1864; // @[dec_tlu_ctl.scala 2274:44] + wire _T_1868 = ~mcountinhibit[6]; // @[dec_tlu_ctl.scala 2274:24] reg [9:0] mhpme6; // @[Reg.scala 27:20] - wire _T_1879 = mhpme6 == 10'h1; // @[dec_tlu_ctl.scala 2275:34] - wire _T_1881 = mhpme6 == 10'h2; // @[dec_tlu_ctl.scala 2276:34] - wire _T_1883 = mhpme6 == 10'h3; // @[dec_tlu_ctl.scala 2277:34] - wire _T_1885 = mhpme6 == 10'h4; // @[dec_tlu_ctl.scala 2278:34] - wire _T_1889 = mhpme6 == 10'h5; // @[dec_tlu_ctl.scala 2279:34] - wire _T_1895 = mhpme6 == 10'h6; // @[dec_tlu_ctl.scala 2280:34] - wire _T_1900 = mhpme6 == 10'h7; // @[dec_tlu_ctl.scala 2281:34] - wire _T_1902 = mhpme6 == 10'h8; // @[dec_tlu_ctl.scala 2282:34] - wire _T_1904 = mhpme6 == 10'h1e; // @[dec_tlu_ctl.scala 2283:34] - wire _T_1906 = mhpme6 == 10'h9; // @[dec_tlu_ctl.scala 2284:34] - wire _T_1909 = mhpme6 == 10'ha; // @[dec_tlu_ctl.scala 2285:34] - wire _T_1912 = mhpme6 == 10'hb; // @[dec_tlu_ctl.scala 2286:34] - wire _T_1915 = mhpme6 == 10'hc; // @[dec_tlu_ctl.scala 2287:34] - wire _T_1918 = mhpme6 == 10'hd; // @[dec_tlu_ctl.scala 2288:34] - wire _T_1922 = mhpme6 == 10'he; // @[dec_tlu_ctl.scala 2289:34] - wire _T_1927 = mhpme6 == 10'hf; // @[dec_tlu_ctl.scala 2290:34] - wire _T_1930 = mhpme6 == 10'h10; // @[dec_tlu_ctl.scala 2291:34] - wire _T_1933 = mhpme6 == 10'h12; // @[dec_tlu_ctl.scala 2292:34] - wire _T_1936 = mhpme6 == 10'h11; // @[dec_tlu_ctl.scala 2293:34] - wire _T_1939 = mhpme6 == 10'h13; // @[dec_tlu_ctl.scala 2294:34] - wire _T_1942 = mhpme6 == 10'h14; // @[dec_tlu_ctl.scala 2295:34] - wire _T_1945 = mhpme6 == 10'h15; // @[dec_tlu_ctl.scala 2296:34] - wire _T_1948 = mhpme6 == 10'h16; // @[dec_tlu_ctl.scala 2297:34] - wire _T_1951 = mhpme6 == 10'h17; // @[dec_tlu_ctl.scala 2298:34] - wire _T_1954 = mhpme6 == 10'h18; // @[dec_tlu_ctl.scala 2299:34] - wire _T_1959 = mhpme6 == 10'h19; // @[dec_tlu_ctl.scala 2300:34] - wire _T_1962 = mhpme6 == 10'h1a; // @[dec_tlu_ctl.scala 2301:34] - wire _T_1965 = mhpme6 == 10'h1b; // @[dec_tlu_ctl.scala 2302:34] - wire _T_1968 = mhpme6 == 10'h1c; // @[dec_tlu_ctl.scala 2303:34] - wire _T_1972 = mhpme6 == 10'h1f; // @[dec_tlu_ctl.scala 2305:34] - wire _T_1974 = mhpme6 == 10'h20; // @[dec_tlu_ctl.scala 2306:34] - wire _T_1976 = mhpme6 == 10'h22; // @[dec_tlu_ctl.scala 2307:34] - wire _T_1978 = mhpme6 == 10'h23; // @[dec_tlu_ctl.scala 2308:34] - wire _T_1980 = mhpme6 == 10'h24; // @[dec_tlu_ctl.scala 2309:34] - wire _T_1982 = mhpme6 == 10'h25; // @[dec_tlu_ctl.scala 2310:34] - wire _T_1986 = mhpme6 == 10'h26; // @[dec_tlu_ctl.scala 2311:34] - wire _T_1990 = mhpme6 == 10'h27; // @[dec_tlu_ctl.scala 2312:34] - wire _T_1992 = mhpme6 == 10'h28; // @[dec_tlu_ctl.scala 2313:34] - wire _T_1994 = mhpme6 == 10'h29; // @[dec_tlu_ctl.scala 2314:34] - wire _T_1998 = mhpme6 == 10'h2a; // @[dec_tlu_ctl.scala 2315:34] - wire _T_2000 = mhpme6 == 10'h2b; // @[dec_tlu_ctl.scala 2316:34] - wire _T_2002 = mhpme6 == 10'h2c; // @[dec_tlu_ctl.scala 2317:34] - wire _T_2004 = mhpme6 == 10'h2d; // @[dec_tlu_ctl.scala 2318:34] - wire _T_2006 = mhpme6 == 10'h2e; // @[dec_tlu_ctl.scala 2319:34] - wire _T_2008 = mhpme6 == 10'h2f; // @[dec_tlu_ctl.scala 2320:34] - wire _T_2010 = mhpme6 == 10'h30; // @[dec_tlu_ctl.scala 2321:34] - wire _T_2012 = mhpme6 == 10'h31; // @[dec_tlu_ctl.scala 2322:34] - wire _T_2017 = mhpme6 == 10'h32; // @[dec_tlu_ctl.scala 2323:34] - wire _T_2027 = mhpme6 == 10'h36; // @[dec_tlu_ctl.scala 2324:34] - wire _T_2030 = mhpme6 == 10'h37; // @[dec_tlu_ctl.scala 2325:34] - wire _T_2033 = mhpme6 == 10'h38; // @[dec_tlu_ctl.scala 2326:34] - wire _T_2036 = mhpme6 == 10'h200; // @[dec_tlu_ctl.scala 2328:34] - wire _T_2038 = mhpme6 == 10'h201; // @[dec_tlu_ctl.scala 2329:34] - wire _T_2040 = mhpme6 == 10'h202; // @[dec_tlu_ctl.scala 2330:34] - wire _T_2042 = mhpme6 == 10'h203; // @[dec_tlu_ctl.scala 2331:34] - wire _T_2044 = mhpme6 == 10'h204; // @[dec_tlu_ctl.scala 2332:34] - wire _T_2047 = _T_1881 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] - wire _T_2048 = _T_1883 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] - wire _T_2049 = _T_1885 & _T_1036; // @[Mux.scala 27:72] - wire _T_2050 = _T_1889 & _T_1042; // @[Mux.scala 27:72] - wire _T_2051 = _T_1895 & _T_1047; // @[Mux.scala 27:72] - wire _T_2052 = _T_1900 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] - wire _T_2053 = _T_1902 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] - wire _T_2054 = _T_1904 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] - wire _T_2055 = _T_1906 & _T_1056; // @[Mux.scala 27:72] - wire _T_2056 = _T_1909 & _T_1059; // @[Mux.scala 27:72] - wire _T_2057 = _T_1912 & _T_1062; // @[Mux.scala 27:72] - wire _T_2058 = _T_1915 & _T_1065; // @[Mux.scala 27:72] - wire _T_2059 = _T_1918 & _T_1069; // @[Mux.scala 27:72] - wire _T_2060 = _T_1922 & _T_1074; // @[Mux.scala 27:72] - wire _T_2061 = _T_1927 & _T_1077; // @[Mux.scala 27:72] - wire _T_2062 = _T_1930 & _T_1080; // @[Mux.scala 27:72] - wire _T_2063 = _T_1933 & _T_1083; // @[Mux.scala 27:72] - wire _T_2064 = _T_1936 & _T_1086; // @[Mux.scala 27:72] - wire _T_2065 = _T_1939 & _T_1089; // @[Mux.scala 27:72] - wire _T_2066 = _T_1942 & _T_1092; // @[Mux.scala 27:72] - wire _T_2067 = _T_1945 & _T_1095; // @[Mux.scala 27:72] - wire _T_2068 = _T_1948 & _T_1098; // @[Mux.scala 27:72] - wire _T_2069 = _T_1951 & _T_1101; // @[Mux.scala 27:72] - wire _T_2070 = _T_1954 & _T_1106; // @[Mux.scala 27:72] - wire _T_2071 = _T_1959 & _T_1109; // @[Mux.scala 27:72] - wire _T_2072 = _T_1962 & _T_1112; // @[Mux.scala 27:72] - wire _T_2073 = _T_1965 & _T_1115; // @[Mux.scala 27:72] - wire _T_2074 = _T_1968 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] - wire _T_2076 = _T_1972 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] - wire _T_2077 = _T_1974 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] - wire _T_2078 = _T_1976 & io_lsu_store_stall_any; // @[Mux.scala 27:72] - wire _T_2079 = _T_1978 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] - wire _T_2080 = _T_1980 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] - wire _T_2081 = _T_1982 & _T_1133; // @[Mux.scala 27:72] - wire _T_2082 = _T_1986 & _T_1137; // @[Mux.scala 27:72] - wire _T_2083 = _T_1990 & io_take_ext_int; // @[Mux.scala 27:72] - wire _T_2084 = _T_1992 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] - wire _T_2085 = _T_1994 & _T_1145; // @[Mux.scala 27:72] - wire _T_2086 = _T_1998 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_2087 = _T_2000 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_2088 = _T_2002 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] - wire _T_2089 = _T_2004 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_2090 = _T_2006 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_2091 = _T_2008 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_2092 = _T_2010 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_2093 = _T_2012 & _T_1164; // @[Mux.scala 27:72] - wire _T_2094 = _T_2017 & _T_1174; // @[Mux.scala 27:72] - wire _T_2095 = _T_2027 & _T_1177; // @[Mux.scala 27:72] - wire _T_2096 = _T_2030 & _T_1180; // @[Mux.scala 27:72] - wire _T_2097 = _T_2033 & _T_1183; // @[Mux.scala 27:72] - wire _T_2098 = _T_2036 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] - wire _T_2099 = _T_2038 & io_dma_pmu_any_read; // @[Mux.scala 27:72] - wire _T_2100 = _T_2040 & io_dma_pmu_any_write; // @[Mux.scala 27:72] - wire _T_2101 = _T_2042 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] - wire _T_2102 = _T_2044 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] - wire _T_2103 = _T_1879 | _T_2047; // @[Mux.scala 27:72] + wire _T_1869 = mhpme6 == 10'h1; // @[dec_tlu_ctl.scala 2275:34] + wire _T_1871 = mhpme6 == 10'h2; // @[dec_tlu_ctl.scala 2276:34] + wire _T_1873 = mhpme6 == 10'h3; // @[dec_tlu_ctl.scala 2277:34] + wire _T_1875 = mhpme6 == 10'h4; // @[dec_tlu_ctl.scala 2278:34] + wire _T_1879 = mhpme6 == 10'h5; // @[dec_tlu_ctl.scala 2279:34] + wire _T_1885 = mhpme6 == 10'h6; // @[dec_tlu_ctl.scala 2280:34] + wire _T_1890 = mhpme6 == 10'h7; // @[dec_tlu_ctl.scala 2281:34] + wire _T_1892 = mhpme6 == 10'h8; // @[dec_tlu_ctl.scala 2282:34] + wire _T_1894 = mhpme6 == 10'h1e; // @[dec_tlu_ctl.scala 2283:34] + wire _T_1896 = mhpme6 == 10'h9; // @[dec_tlu_ctl.scala 2284:34] + wire _T_1899 = mhpme6 == 10'ha; // @[dec_tlu_ctl.scala 2285:34] + wire _T_1902 = mhpme6 == 10'hb; // @[dec_tlu_ctl.scala 2286:34] + wire _T_1905 = mhpme6 == 10'hc; // @[dec_tlu_ctl.scala 2287:34] + wire _T_1908 = mhpme6 == 10'hd; // @[dec_tlu_ctl.scala 2288:34] + wire _T_1912 = mhpme6 == 10'he; // @[dec_tlu_ctl.scala 2289:34] + wire _T_1917 = mhpme6 == 10'hf; // @[dec_tlu_ctl.scala 2290:34] + wire _T_1920 = mhpme6 == 10'h10; // @[dec_tlu_ctl.scala 2291:34] + wire _T_1923 = mhpme6 == 10'h12; // @[dec_tlu_ctl.scala 2292:34] + wire _T_1926 = mhpme6 == 10'h11; // @[dec_tlu_ctl.scala 2293:34] + wire _T_1929 = mhpme6 == 10'h13; // @[dec_tlu_ctl.scala 2294:34] + wire _T_1932 = mhpme6 == 10'h14; // @[dec_tlu_ctl.scala 2295:34] + wire _T_1935 = mhpme6 == 10'h15; // @[dec_tlu_ctl.scala 2296:34] + wire _T_1938 = mhpme6 == 10'h16; // @[dec_tlu_ctl.scala 2297:34] + wire _T_1941 = mhpme6 == 10'h17; // @[dec_tlu_ctl.scala 2298:34] + wire _T_1944 = mhpme6 == 10'h18; // @[dec_tlu_ctl.scala 2299:34] + wire _T_1949 = mhpme6 == 10'h19; // @[dec_tlu_ctl.scala 2300:34] + wire _T_1952 = mhpme6 == 10'h1a; // @[dec_tlu_ctl.scala 2301:34] + wire _T_1955 = mhpme6 == 10'h1b; // @[dec_tlu_ctl.scala 2302:34] + wire _T_1958 = mhpme6 == 10'h1c; // @[dec_tlu_ctl.scala 2303:34] + wire _T_1962 = mhpme6 == 10'h1f; // @[dec_tlu_ctl.scala 2305:34] + wire _T_1964 = mhpme6 == 10'h20; // @[dec_tlu_ctl.scala 2306:34] + wire _T_1966 = mhpme6 == 10'h22; // @[dec_tlu_ctl.scala 2307:34] + wire _T_1968 = mhpme6 == 10'h23; // @[dec_tlu_ctl.scala 2308:34] + wire _T_1970 = mhpme6 == 10'h24; // @[dec_tlu_ctl.scala 2309:34] + wire _T_1972 = mhpme6 == 10'h25; // @[dec_tlu_ctl.scala 2310:34] + wire _T_1976 = mhpme6 == 10'h26; // @[dec_tlu_ctl.scala 2311:34] + wire _T_1980 = mhpme6 == 10'h27; // @[dec_tlu_ctl.scala 2312:34] + wire _T_1982 = mhpme6 == 10'h28; // @[dec_tlu_ctl.scala 2313:34] + wire _T_1984 = mhpme6 == 10'h29; // @[dec_tlu_ctl.scala 2314:34] + wire _T_1988 = mhpme6 == 10'h2a; // @[dec_tlu_ctl.scala 2315:34] + wire _T_1990 = mhpme6 == 10'h2b; // @[dec_tlu_ctl.scala 2316:34] + wire _T_1992 = mhpme6 == 10'h2c; // @[dec_tlu_ctl.scala 2317:34] + wire _T_1994 = mhpme6 == 10'h2d; // @[dec_tlu_ctl.scala 2318:34] + wire _T_1996 = mhpme6 == 10'h2e; // @[dec_tlu_ctl.scala 2319:34] + wire _T_1998 = mhpme6 == 10'h2f; // @[dec_tlu_ctl.scala 2320:34] + wire _T_2000 = mhpme6 == 10'h30; // @[dec_tlu_ctl.scala 2321:34] + wire _T_2002 = mhpme6 == 10'h31; // @[dec_tlu_ctl.scala 2322:34] + wire _T_2007 = mhpme6 == 10'h32; // @[dec_tlu_ctl.scala 2323:34] + wire _T_2017 = mhpme6 == 10'h36; // @[dec_tlu_ctl.scala 2324:34] + wire _T_2020 = mhpme6 == 10'h37; // @[dec_tlu_ctl.scala 2325:34] + wire _T_2023 = mhpme6 == 10'h38; // @[dec_tlu_ctl.scala 2326:34] + wire _T_2026 = mhpme6 == 10'h200; // @[dec_tlu_ctl.scala 2328:34] + wire _T_2028 = mhpme6 == 10'h201; // @[dec_tlu_ctl.scala 2329:34] + wire _T_2030 = mhpme6 == 10'h202; // @[dec_tlu_ctl.scala 2330:34] + wire _T_2032 = mhpme6 == 10'h203; // @[dec_tlu_ctl.scala 2331:34] + wire _T_2034 = mhpme6 == 10'h204; // @[dec_tlu_ctl.scala 2332:34] + wire _T_2037 = _T_1871 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_2038 = _T_1873 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_2039 = _T_1875 & _T_1026; // @[Mux.scala 27:72] + wire _T_2040 = _T_1879 & _T_1032; // @[Mux.scala 27:72] + wire _T_2041 = _T_1885 & _T_1037; // @[Mux.scala 27:72] + wire _T_2042 = _T_1890 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_2043 = _T_1892 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_2044 = _T_1894 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_2045 = _T_1896 & _T_1046; // @[Mux.scala 27:72] + wire _T_2046 = _T_1899 & _T_1049; // @[Mux.scala 27:72] + wire _T_2047 = _T_1902 & _T_1052; // @[Mux.scala 27:72] + wire _T_2048 = _T_1905 & _T_1055; // @[Mux.scala 27:72] + wire _T_2049 = _T_1908 & _T_1059; // @[Mux.scala 27:72] + wire _T_2050 = _T_1912 & _T_1064; // @[Mux.scala 27:72] + wire _T_2051 = _T_1917 & _T_1067; // @[Mux.scala 27:72] + wire _T_2052 = _T_1920 & _T_1070; // @[Mux.scala 27:72] + wire _T_2053 = _T_1923 & _T_1073; // @[Mux.scala 27:72] + wire _T_2054 = _T_1926 & _T_1076; // @[Mux.scala 27:72] + wire _T_2055 = _T_1929 & _T_1079; // @[Mux.scala 27:72] + wire _T_2056 = _T_1932 & _T_1082; // @[Mux.scala 27:72] + wire _T_2057 = _T_1935 & _T_1085; // @[Mux.scala 27:72] + wire _T_2058 = _T_1938 & _T_1088; // @[Mux.scala 27:72] + wire _T_2059 = _T_1941 & _T_1091; // @[Mux.scala 27:72] + wire _T_2060 = _T_1944 & _T_1096; // @[Mux.scala 27:72] + wire _T_2061 = _T_1949 & _T_1099; // @[Mux.scala 27:72] + wire _T_2062 = _T_1952 & _T_1102; // @[Mux.scala 27:72] + wire _T_2063 = _T_1955 & _T_1105; // @[Mux.scala 27:72] + wire _T_2064 = _T_1958 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_2066 = _T_1962 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_2067 = _T_1964 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_2068 = _T_1966 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_2069 = _T_1968 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_2070 = _T_1970 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_2071 = _T_1972 & _T_1123; // @[Mux.scala 27:72] + wire _T_2072 = _T_1976 & _T_1127; // @[Mux.scala 27:72] + wire _T_2073 = _T_1980 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_2074 = _T_1982 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_2075 = _T_1984 & _T_1135; // @[Mux.scala 27:72] + wire _T_2076 = _T_1988 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_2077 = _T_1990 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_2078 = _T_1992 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_2079 = _T_1994 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_2080 = _T_1996 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_2081 = _T_1998 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_2082 = _T_2000 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_2083 = _T_2002 & _T_1154; // @[Mux.scala 27:72] + wire _T_2084 = _T_2007 & _T_1164; // @[Mux.scala 27:72] + wire _T_2085 = _T_2017 & _T_1167; // @[Mux.scala 27:72] + wire _T_2086 = _T_2020 & _T_1170; // @[Mux.scala 27:72] + wire _T_2087 = _T_2023 & _T_1173; // @[Mux.scala 27:72] + wire _T_2088 = _T_2026 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_2089 = _T_2028 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_2090 = _T_2030 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_2091 = _T_2032 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_2092 = _T_2034 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_2093 = _T_1869 | _T_2037; // @[Mux.scala 27:72] + wire _T_2094 = _T_2093 | _T_2038; // @[Mux.scala 27:72] + wire _T_2095 = _T_2094 | _T_2039; // @[Mux.scala 27:72] + wire _T_2096 = _T_2095 | _T_2040; // @[Mux.scala 27:72] + wire _T_2097 = _T_2096 | _T_2041; // @[Mux.scala 27:72] + wire _T_2098 = _T_2097 | _T_2042; // @[Mux.scala 27:72] + wire _T_2099 = _T_2098 | _T_2043; // @[Mux.scala 27:72] + wire _T_2100 = _T_2099 | _T_2044; // @[Mux.scala 27:72] + wire _T_2101 = _T_2100 | _T_2045; // @[Mux.scala 27:72] + wire _T_2102 = _T_2101 | _T_2046; // @[Mux.scala 27:72] + wire _T_2103 = _T_2102 | _T_2047; // @[Mux.scala 27:72] wire _T_2104 = _T_2103 | _T_2048; // @[Mux.scala 27:72] wire _T_2105 = _T_2104 | _T_2049; // @[Mux.scala 27:72] wire _T_2106 = _T_2105 | _T_2050; // @[Mux.scala 27:72] @@ -52094,7 +52124,7 @@ module csr_tlu( wire _T_2118 = _T_2117 | _T_2062; // @[Mux.scala 27:72] wire _T_2119 = _T_2118 | _T_2063; // @[Mux.scala 27:72] wire _T_2120 = _T_2119 | _T_2064; // @[Mux.scala 27:72] - wire _T_2121 = _T_2120 | _T_2065; // @[Mux.scala 27:72] + wire _T_2121 = _T_2120 | _T_2044; // @[Mux.scala 27:72] wire _T_2122 = _T_2121 | _T_2066; // @[Mux.scala 27:72] wire _T_2123 = _T_2122 | _T_2067; // @[Mux.scala 27:72] wire _T_2124 = _T_2123 | _T_2068; // @[Mux.scala 27:72] @@ -52104,7 +52134,7 @@ module csr_tlu( wire _T_2128 = _T_2127 | _T_2072; // @[Mux.scala 27:72] wire _T_2129 = _T_2128 | _T_2073; // @[Mux.scala 27:72] wire _T_2130 = _T_2129 | _T_2074; // @[Mux.scala 27:72] - wire _T_2131 = _T_2130 | _T_2054; // @[Mux.scala 27:72] + wire _T_2131 = _T_2130 | _T_2075; // @[Mux.scala 27:72] wire _T_2132 = _T_2131 | _T_2076; // @[Mux.scala 27:72] wire _T_2133 = _T_2132 | _T_2077; // @[Mux.scala 27:72] wire _T_2134 = _T_2133 | _T_2078; // @[Mux.scala 27:72] @@ -52122,196 +52152,196 @@ module csr_tlu( wire _T_2146 = _T_2145 | _T_2090; // @[Mux.scala 27:72] wire _T_2147 = _T_2146 | _T_2091; // @[Mux.scala 27:72] wire _T_2148 = _T_2147 | _T_2092; // @[Mux.scala 27:72] - wire _T_2149 = _T_2148 | _T_2093; // @[Mux.scala 27:72] - wire _T_2150 = _T_2149 | _T_2094; // @[Mux.scala 27:72] - wire _T_2151 = _T_2150 | _T_2095; // @[Mux.scala 27:72] - wire _T_2152 = _T_2151 | _T_2096; // @[Mux.scala 27:72] - wire _T_2153 = _T_2152 | _T_2097; // @[Mux.scala 27:72] - wire _T_2154 = _T_2153 | _T_2098; // @[Mux.scala 27:72] - wire _T_2155 = _T_2154 | _T_2099; // @[Mux.scala 27:72] - wire _T_2156 = _T_2155 | _T_2100; // @[Mux.scala 27:72] - wire _T_2157 = _T_2156 | _T_2101; // @[Mux.scala 27:72] - wire _T_2158 = _T_2157 | _T_2102; // @[Mux.scala 27:72] - wire mhpmc_inc_r_3 = _T_1878 & _T_2158; // @[dec_tlu_ctl.scala 2274:44] + wire mhpmc_inc_r_3 = _T_1868 & _T_2148; // @[dec_tlu_ctl.scala 2274:44] reg mhpmc_inc_r_d1_0; // @[dec_tlu_ctl.scala 2335:53] reg mhpmc_inc_r_d1_1; // @[dec_tlu_ctl.scala 2336:53] reg mhpmc_inc_r_d1_2; // @[dec_tlu_ctl.scala 2337:53] reg mhpmc_inc_r_d1_3; // @[dec_tlu_ctl.scala 2338:53] reg perfcnt_halted_d1; // @[dec_tlu_ctl.scala 2339:56] wire perfcnt_halted = _T_85 | io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 2342:67] - wire _T_2170 = ~_T_85; // @[dec_tlu_ctl.scala 2343:37] - wire [3:0] _T_2172 = _T_2170 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_2179 = {mhpme6[9],mhpme5[9],mhpme4[9],mhpme3[9]}; // @[Cat.scala 29:58] - wire [3:0] perfcnt_during_sleep = _T_2172 & _T_2179; // @[dec_tlu_ctl.scala 2343:86] - wire _T_2181 = ~perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2345:67] - wire _T_2182 = perfcnt_halted_d1 & _T_2181; // @[dec_tlu_ctl.scala 2345:65] - wire _T_2183 = ~_T_2182; // @[dec_tlu_ctl.scala 2345:45] - wire _T_2186 = ~perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2346:67] - wire _T_2187 = perfcnt_halted_d1 & _T_2186; // @[dec_tlu_ctl.scala 2346:65] - wire _T_2188 = ~_T_2187; // @[dec_tlu_ctl.scala 2346:45] - wire _T_2191 = ~perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2347:67] - wire _T_2192 = perfcnt_halted_d1 & _T_2191; // @[dec_tlu_ctl.scala 2347:65] - wire _T_2193 = ~_T_2192; // @[dec_tlu_ctl.scala 2347:45] - wire _T_2196 = ~perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2348:67] - wire _T_2197 = perfcnt_halted_d1 & _T_2196; // @[dec_tlu_ctl.scala 2348:65] - wire _T_2198 = ~_T_2197; // @[dec_tlu_ctl.scala 2348:45] - wire _T_2201 = io_dec_csr_wraddr_r == 12'hb03; // @[dec_tlu_ctl.scala 2354:72] - wire mhpmc3_wr_en0 = io_dec_csr_wen_r_mod & _T_2201; // @[dec_tlu_ctl.scala 2354:43] - wire _T_2202 = ~perfcnt_halted; // @[dec_tlu_ctl.scala 2355:23] - wire _T_2204 = _T_2202 | perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2355:39] - wire _T_2205 = |mhpmc_inc_r_0; // @[dec_tlu_ctl.scala 2355:86] - wire mhpmc3_wr_en1 = _T_2204 & _T_2205; // @[dec_tlu_ctl.scala 2355:66] + wire _T_2160 = ~_T_85; // @[dec_tlu_ctl.scala 2343:37] + wire [3:0] _T_2162 = _T_2160 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_2169 = {mhpme6[9],mhpme5[9],mhpme4[9],mhpme3[9]}; // @[Cat.scala 29:58] + wire [3:0] perfcnt_during_sleep = _T_2162 & _T_2169; // @[dec_tlu_ctl.scala 2343:86] + wire _T_2171 = ~perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2345:67] + wire _T_2172 = perfcnt_halted_d1 & _T_2171; // @[dec_tlu_ctl.scala 2345:65] + wire _T_2173 = ~_T_2172; // @[dec_tlu_ctl.scala 2345:45] + wire _T_2176 = ~perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2346:67] + wire _T_2177 = perfcnt_halted_d1 & _T_2176; // @[dec_tlu_ctl.scala 2346:65] + wire _T_2178 = ~_T_2177; // @[dec_tlu_ctl.scala 2346:45] + wire _T_2181 = ~perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2347:67] + wire _T_2182 = perfcnt_halted_d1 & _T_2181; // @[dec_tlu_ctl.scala 2347:65] + wire _T_2183 = ~_T_2182; // @[dec_tlu_ctl.scala 2347:45] + wire _T_2186 = ~perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2348:67] + wire _T_2187 = perfcnt_halted_d1 & _T_2186; // @[dec_tlu_ctl.scala 2348:65] + wire _T_2188 = ~_T_2187; // @[dec_tlu_ctl.scala 2348:45] + wire _T_2191 = io_dec_csr_wraddr_r == 12'hb03; // @[dec_tlu_ctl.scala 2354:72] + wire mhpmc3_wr_en0 = io_dec_csr_wen_r_mod & _T_2191; // @[dec_tlu_ctl.scala 2354:43] + wire _T_2192 = ~perfcnt_halted; // @[dec_tlu_ctl.scala 2355:23] + wire _T_2194 = _T_2192 | perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2355:39] + wire _T_2195 = |mhpmc_inc_r_0; // @[dec_tlu_ctl.scala 2355:86] + wire mhpmc3_wr_en1 = _T_2194 & _T_2195; // @[dec_tlu_ctl.scala 2355:66] reg [31:0] mhpmc3h; // @[lib.scala 374:16] reg [31:0] mhpmc3; // @[lib.scala 374:16] - wire [63:0] _T_2208 = {mhpmc3h,mhpmc3}; // @[Cat.scala 29:58] - wire [63:0] _T_2209 = {63'h0,mhpmc_inc_r_0}; // @[Cat.scala 29:58] - wire [63:0] mhpmc3_incr = _T_2208 + _T_2209; // @[dec_tlu_ctl.scala 2359:49] - wire _T_2217 = io_dec_csr_wraddr_r == 12'hb83; // @[dec_tlu_ctl.scala 2364:73] - wire mhpmc3h_wr_en0 = io_dec_csr_wen_r_mod & _T_2217; // @[dec_tlu_ctl.scala 2364:44] - wire _T_2223 = io_dec_csr_wraddr_r == 12'hb04; // @[dec_tlu_ctl.scala 2373:72] - wire mhpmc4_wr_en0 = io_dec_csr_wen_r_mod & _T_2223; // @[dec_tlu_ctl.scala 2373:43] - wire _T_2226 = _T_2202 | perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2374:39] - wire _T_2227 = |mhpmc_inc_r_1; // @[dec_tlu_ctl.scala 2374:86] - wire mhpmc4_wr_en1 = _T_2226 & _T_2227; // @[dec_tlu_ctl.scala 2374:66] + wire [63:0] _T_2198 = {mhpmc3h,mhpmc3}; // @[Cat.scala 29:58] + wire [63:0] _T_2199 = {63'h0,mhpmc_inc_r_0}; // @[Cat.scala 29:58] + wire [63:0] mhpmc3_incr = _T_2198 + _T_2199; // @[dec_tlu_ctl.scala 2359:49] + wire _T_2207 = io_dec_csr_wraddr_r == 12'hb83; // @[dec_tlu_ctl.scala 2364:73] + wire mhpmc3h_wr_en0 = io_dec_csr_wen_r_mod & _T_2207; // @[dec_tlu_ctl.scala 2364:44] + wire _T_2213 = io_dec_csr_wraddr_r == 12'hb04; // @[dec_tlu_ctl.scala 2373:72] + wire mhpmc4_wr_en0 = io_dec_csr_wen_r_mod & _T_2213; // @[dec_tlu_ctl.scala 2373:43] + wire _T_2216 = _T_2192 | perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2374:39] + wire _T_2217 = |mhpmc_inc_r_1; // @[dec_tlu_ctl.scala 2374:86] + wire mhpmc4_wr_en1 = _T_2216 & _T_2217; // @[dec_tlu_ctl.scala 2374:66] reg [31:0] mhpmc4h; // @[lib.scala 374:16] reg [31:0] mhpmc4; // @[lib.scala 374:16] - wire [63:0] _T_2230 = {mhpmc4h,mhpmc4}; // @[Cat.scala 29:58] - wire [63:0] _T_2231 = {63'h0,mhpmc_inc_r_1}; // @[Cat.scala 29:58] - wire [63:0] mhpmc4_incr = _T_2230 + _T_2231; // @[dec_tlu_ctl.scala 2379:49] - wire _T_2240 = io_dec_csr_wraddr_r == 12'hb84; // @[dec_tlu_ctl.scala 2383:73] - wire mhpmc4h_wr_en0 = io_dec_csr_wen_r_mod & _T_2240; // @[dec_tlu_ctl.scala 2383:44] - wire _T_2246 = io_dec_csr_wraddr_r == 12'hb05; // @[dec_tlu_ctl.scala 2392:72] - wire mhpmc5_wr_en0 = io_dec_csr_wen_r_mod & _T_2246; // @[dec_tlu_ctl.scala 2392:43] - wire _T_2249 = _T_2202 | perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2393:39] - wire _T_2250 = |mhpmc_inc_r_2; // @[dec_tlu_ctl.scala 2393:86] - wire mhpmc5_wr_en1 = _T_2249 & _T_2250; // @[dec_tlu_ctl.scala 2393:66] + wire [63:0] _T_2220 = {mhpmc4h,mhpmc4}; // @[Cat.scala 29:58] + wire [63:0] _T_2221 = {63'h0,mhpmc_inc_r_1}; // @[Cat.scala 29:58] + wire [63:0] mhpmc4_incr = _T_2220 + _T_2221; // @[dec_tlu_ctl.scala 2379:49] + wire _T_2230 = io_dec_csr_wraddr_r == 12'hb84; // @[dec_tlu_ctl.scala 2383:73] + wire mhpmc4h_wr_en0 = io_dec_csr_wen_r_mod & _T_2230; // @[dec_tlu_ctl.scala 2383:44] + wire _T_2236 = io_dec_csr_wraddr_r == 12'hb05; // @[dec_tlu_ctl.scala 2392:72] + wire mhpmc5_wr_en0 = io_dec_csr_wen_r_mod & _T_2236; // @[dec_tlu_ctl.scala 2392:43] + wire _T_2239 = _T_2192 | perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2393:39] + wire _T_2240 = |mhpmc_inc_r_2; // @[dec_tlu_ctl.scala 2393:86] + wire mhpmc5_wr_en1 = _T_2239 & _T_2240; // @[dec_tlu_ctl.scala 2393:66] reg [31:0] mhpmc5h; // @[lib.scala 374:16] reg [31:0] mhpmc5; // @[lib.scala 374:16] - wire [63:0] _T_2253 = {mhpmc5h,mhpmc5}; // @[Cat.scala 29:58] - wire [63:0] _T_2254 = {63'h0,mhpmc_inc_r_2}; // @[Cat.scala 29:58] - wire [63:0] mhpmc5_incr = _T_2253 + _T_2254; // @[dec_tlu_ctl.scala 2396:49] - wire _T_2262 = io_dec_csr_wraddr_r == 12'hb85; // @[dec_tlu_ctl.scala 2401:73] - wire mhpmc5h_wr_en0 = io_dec_csr_wen_r_mod & _T_2262; // @[dec_tlu_ctl.scala 2401:44] - wire _T_2268 = io_dec_csr_wraddr_r == 12'hb06; // @[dec_tlu_ctl.scala 2410:72] - wire mhpmc6_wr_en0 = io_dec_csr_wen_r_mod & _T_2268; // @[dec_tlu_ctl.scala 2410:43] - wire _T_2271 = _T_2202 | perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2411:39] - wire _T_2272 = |mhpmc_inc_r_3; // @[dec_tlu_ctl.scala 2411:86] - wire mhpmc6_wr_en1 = _T_2271 & _T_2272; // @[dec_tlu_ctl.scala 2411:66] + wire [63:0] _T_2243 = {mhpmc5h,mhpmc5}; // @[Cat.scala 29:58] + wire [63:0] _T_2244 = {63'h0,mhpmc_inc_r_2}; // @[Cat.scala 29:58] + wire [63:0] mhpmc5_incr = _T_2243 + _T_2244; // @[dec_tlu_ctl.scala 2396:49] + wire _T_2252 = io_dec_csr_wraddr_r == 12'hb85; // @[dec_tlu_ctl.scala 2401:73] + wire mhpmc5h_wr_en0 = io_dec_csr_wen_r_mod & _T_2252; // @[dec_tlu_ctl.scala 2401:44] + wire _T_2258 = io_dec_csr_wraddr_r == 12'hb06; // @[dec_tlu_ctl.scala 2410:72] + wire mhpmc6_wr_en0 = io_dec_csr_wen_r_mod & _T_2258; // @[dec_tlu_ctl.scala 2410:43] + wire _T_2261 = _T_2192 | perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2411:39] + wire _T_2262 = |mhpmc_inc_r_3; // @[dec_tlu_ctl.scala 2411:86] + wire mhpmc6_wr_en1 = _T_2261 & _T_2262; // @[dec_tlu_ctl.scala 2411:66] reg [31:0] mhpmc6h; // @[lib.scala 374:16] reg [31:0] mhpmc6; // @[lib.scala 374:16] - wire [63:0] _T_2275 = {mhpmc6h,mhpmc6}; // @[Cat.scala 29:58] - wire [63:0] _T_2276 = {63'h0,mhpmc_inc_r_3}; // @[Cat.scala 29:58] - wire [63:0] mhpmc6_incr = _T_2275 + _T_2276; // @[dec_tlu_ctl.scala 2414:49] - wire _T_2284 = io_dec_csr_wraddr_r == 12'hb86; // @[dec_tlu_ctl.scala 2419:73] - wire mhpmc6h_wr_en0 = io_dec_csr_wen_r_mod & _T_2284; // @[dec_tlu_ctl.scala 2419:44] - wire _T_2290 = io_dec_csr_wrdata_r[9:0] > 10'h204; // @[dec_tlu_ctl.scala 2430:56] - wire _T_2292 = |io_dec_csr_wrdata_r[31:10]; // @[dec_tlu_ctl.scala 2430:102] - wire _T_2293 = _T_2290 | _T_2292; // @[dec_tlu_ctl.scala 2430:71] - wire _T_2296 = io_dec_csr_wraddr_r == 12'h323; // @[dec_tlu_ctl.scala 2432:70] - wire wr_mhpme3_r = io_dec_csr_wen_r_mod & _T_2296; // @[dec_tlu_ctl.scala 2432:41] - wire _T_2300 = io_dec_csr_wraddr_r == 12'h324; // @[dec_tlu_ctl.scala 2439:70] - wire wr_mhpme4_r = io_dec_csr_wen_r_mod & _T_2300; // @[dec_tlu_ctl.scala 2439:41] - wire _T_2304 = io_dec_csr_wraddr_r == 12'h325; // @[dec_tlu_ctl.scala 2446:70] - wire wr_mhpme5_r = io_dec_csr_wen_r_mod & _T_2304; // @[dec_tlu_ctl.scala 2446:41] - wire _T_2308 = io_dec_csr_wraddr_r == 12'h326; // @[dec_tlu_ctl.scala 2453:70] - wire wr_mhpme6_r = io_dec_csr_wen_r_mod & _T_2308; // @[dec_tlu_ctl.scala 2453:41] - wire _T_2312 = io_dec_csr_wraddr_r == 12'h320; // @[dec_tlu_ctl.scala 2470:77] - wire wr_mcountinhibit_r = io_dec_csr_wen_r_mod & _T_2312; // @[dec_tlu_ctl.scala 2470:48] - wire _T_2324 = io_i0_valid_wb | io_exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 2485:51] - wire _T_2325 = _T_2324 | io_interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 2485:78] - wire _T_2326 = _T_2325 | io_dec_tlu_i0_valid_wb1; // @[dec_tlu_ctl.scala 2485:104] - wire _T_2327 = _T_2326 | io_dec_tlu_i0_exc_valid_wb1; // @[dec_tlu_ctl.scala 2485:130] - wire _T_2328 = _T_2327 | io_dec_tlu_int_valid_wb1; // @[dec_tlu_ctl.scala 2486:32] - reg _T_2331; // @[dec_tlu_ctl.scala 2488:62] - wire _T_2332 = io_i0_exception_valid_r_d1 | io_lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 2489:91] - wire _T_2333 = ~io_trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 2489:137] - wire _T_2334 = io_trigger_hit_r_d1 & _T_2333; // @[dec_tlu_ctl.scala 2489:135] - reg _T_2336; // @[dec_tlu_ctl.scala 2489:62] - reg [4:0] _T_2337; // @[dec_tlu_ctl.scala 2490:62] - reg _T_2338; // @[dec_tlu_ctl.scala 2491:62] - wire [31:0] _T_2344 = {io_core_id,4'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2353 = {21'h3,3'h0,io_mstatus[1],3'h0,io_mstatus[0],3'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2358 = {io_mtvec[30:1],1'h0,io_mtvec[0]}; // @[Cat.scala 29:58] - wire [31:0] _T_2371 = {1'h0,io_mip[5:3],16'h0,io_mip[2],3'h0,io_mip[1],3'h0,io_mip[0],3'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2384 = {1'h0,mie[5:3],16'h0,mie[2],3'h0,mie[1],3'h0,mie[0],3'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2396 = {io_mepc,1'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2401 = {28'h0,mscause}; // @[Cat.scala 29:58] - wire [31:0] _T_2409 = {meivt,10'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2412 = {meivt,meihap,2'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2415 = {28'h0,meicurpl}; // @[Cat.scala 29:58] - wire [31:0] _T_2418 = {28'h0,meicidpl}; // @[Cat.scala 29:58] - wire [31:0] _T_2421 = {28'h0,meipt}; // @[Cat.scala 29:58] - wire [31:0] _T_2424 = {23'h0,mcgc}; // @[Cat.scala 29:58] - wire [31:0] _T_2427 = {13'h0,_T_350,4'h0,mfdc_int[11:7],_T_353,mfdc_int[5:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_2431 = {16'h4000,io_dcsr[15:2],2'h3}; // @[Cat.scala 29:58] - wire [31:0] _T_2433 = {io_dpc,1'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2449 = {7'h0,dicawics[16],2'h0,dicawics[15:14],3'h0,dicawics[13:0],3'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2452 = {30'h0,mtsel}; // @[Cat.scala 29:58] - wire [31:0] _T_2481 = {26'h0,mfdht}; // @[Cat.scala 29:58] - wire [31:0] _T_2484 = {30'h0,mfdhs}; // @[Cat.scala 29:58] - wire [31:0] _T_2487 = {22'h0,mhpme3}; // @[Cat.scala 29:58] - wire [31:0] _T_2490 = {22'h0,mhpme4}; // @[Cat.scala 29:58] - wire [31:0] _T_2493 = {22'h0,mhpme5}; // @[Cat.scala 29:58] - wire [31:0] _T_2496 = {22'h0,mhpme6}; // @[Cat.scala 29:58] - wire [31:0] _T_2499 = {25'h0,temp_ncount6_2,1'h0,temp_ncount0}; // @[Cat.scala 29:58] - wire [31:0] _T_2502 = {30'h0,mpmc,1'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2505 = io_csr_pkt_csr_misa ? 32'h40001104 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2506 = io_csr_pkt_csr_mvendorid ? 32'h45 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2507 = io_csr_pkt_csr_marchid ? 32'h10 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2508 = io_csr_pkt_csr_mimpid ? 32'h1 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2509 = io_csr_pkt_csr_mhartid ? _T_2344 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2510 = io_csr_pkt_csr_mstatus ? _T_2353 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2511 = io_csr_pkt_csr_mtvec ? _T_2358 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2512 = io_csr_pkt_csr_mip ? _T_2371 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2513 = io_csr_pkt_csr_mie ? _T_2384 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2514 = io_csr_pkt_csr_mcyclel ? mcyclel : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2515 = io_csr_pkt_csr_mcycleh ? mcycleh_inc : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2516 = io_csr_pkt_csr_minstretl ? minstretl : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2517 = io_csr_pkt_csr_minstreth ? minstreth_inc : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2518 = io_csr_pkt_csr_mscratch ? mscratch : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2519 = io_csr_pkt_csr_mepc ? _T_2396 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2520 = io_csr_pkt_csr_mcause ? mcause : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2521 = io_csr_pkt_csr_mscause ? _T_2401 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2522 = io_csr_pkt_csr_mtval ? mtval : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2523 = io_csr_pkt_csr_mrac ? mrac : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2524 = io_csr_pkt_csr_mdseac ? mdseac : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2525 = io_csr_pkt_csr_meivt ? _T_2409 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2526 = io_csr_pkt_csr_meihap ? _T_2412 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2527 = io_csr_pkt_csr_meicurpl ? _T_2415 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2528 = io_csr_pkt_csr_meicidpl ? _T_2418 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2529 = io_csr_pkt_csr_meipt ? _T_2421 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2530 = io_csr_pkt_csr_mcgc ? _T_2424 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2531 = io_csr_pkt_csr_mfdc ? _T_2427 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2532 = io_csr_pkt_csr_dcsr ? _T_2431 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2533 = io_csr_pkt_csr_dpc ? _T_2433 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2534 = io_csr_pkt_csr_dicad0 ? dicad0[31:0] : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2535 = io_csr_pkt_csr_dicad0h ? dicad0h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2536 = io_csr_pkt_csr_dicad1 ? dicad1 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2537 = io_csr_pkt_csr_dicawics ? _T_2449 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2538 = io_csr_pkt_csr_mtsel ? _T_2452 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2539 = io_csr_pkt_csr_mtdata1 ? mtdata1_tsel_out : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2540 = io_csr_pkt_csr_mtdata2 ? mtdata2_tsel_out : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2541 = io_csr_pkt_csr_micect ? micect : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2542 = io_csr_pkt_csr_miccmect ? miccmect : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2543 = io_csr_pkt_csr_mdccmect ? mdccmect : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2544 = io_csr_pkt_csr_mhpmc3 ? mhpmc3 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2545 = io_csr_pkt_csr_mhpmc4 ? mhpmc4 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2546 = io_csr_pkt_csr_mhpmc5 ? mhpmc5 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2547 = io_csr_pkt_csr_mhpmc6 ? mhpmc6 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2548 = io_csr_pkt_csr_mhpmc3h ? mhpmc3h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2549 = io_csr_pkt_csr_mhpmc4h ? mhpmc4h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2550 = io_csr_pkt_csr_mhpmc5h ? mhpmc5h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2551 = io_csr_pkt_csr_mhpmc6h ? mhpmc6h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2552 = io_csr_pkt_csr_mfdht ? _T_2481 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2553 = io_csr_pkt_csr_mfdhs ? _T_2484 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2554 = io_csr_pkt_csr_mhpme3 ? _T_2487 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2555 = io_csr_pkt_csr_mhpme4 ? _T_2490 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2556 = io_csr_pkt_csr_mhpme5 ? _T_2493 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2557 = io_csr_pkt_csr_mhpme6 ? _T_2496 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2558 = io_csr_pkt_csr_mcountinhibit ? _T_2499 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2559 = io_csr_pkt_csr_mpmc ? _T_2502 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2560 = io_dec_timer_read_d ? io_dec_timer_rddata_d : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2561 = _T_2505 | _T_2506; // @[Mux.scala 27:72] + wire [63:0] _T_2265 = {mhpmc6h,mhpmc6}; // @[Cat.scala 29:58] + wire [63:0] _T_2266 = {63'h0,mhpmc_inc_r_3}; // @[Cat.scala 29:58] + wire [63:0] mhpmc6_incr = _T_2265 + _T_2266; // @[dec_tlu_ctl.scala 2414:49] + wire _T_2274 = io_dec_csr_wraddr_r == 12'hb86; // @[dec_tlu_ctl.scala 2419:73] + wire mhpmc6h_wr_en0 = io_dec_csr_wen_r_mod & _T_2274; // @[dec_tlu_ctl.scala 2419:44] + wire _T_2280 = io_dec_csr_wrdata_r[9:0] > 10'h204; // @[dec_tlu_ctl.scala 2430:56] + wire _T_2282 = |io_dec_csr_wrdata_r[31:10]; // @[dec_tlu_ctl.scala 2430:102] + wire _T_2283 = _T_2280 | _T_2282; // @[dec_tlu_ctl.scala 2430:71] + wire _T_2286 = io_dec_csr_wraddr_r == 12'h323; // @[dec_tlu_ctl.scala 2432:70] + wire wr_mhpme3_r = io_dec_csr_wen_r_mod & _T_2286; // @[dec_tlu_ctl.scala 2432:41] + wire _T_2290 = io_dec_csr_wraddr_r == 12'h324; // @[dec_tlu_ctl.scala 2439:70] + wire wr_mhpme4_r = io_dec_csr_wen_r_mod & _T_2290; // @[dec_tlu_ctl.scala 2439:41] + wire _T_2294 = io_dec_csr_wraddr_r == 12'h325; // @[dec_tlu_ctl.scala 2446:70] + wire wr_mhpme5_r = io_dec_csr_wen_r_mod & _T_2294; // @[dec_tlu_ctl.scala 2446:41] + wire _T_2298 = io_dec_csr_wraddr_r == 12'h326; // @[dec_tlu_ctl.scala 2453:70] + wire wr_mhpme6_r = io_dec_csr_wen_r_mod & _T_2298; // @[dec_tlu_ctl.scala 2453:41] + wire _T_2302 = io_dec_csr_wraddr_r == 12'h320; // @[dec_tlu_ctl.scala 2470:77] + wire wr_mcountinhibit_r = io_dec_csr_wen_r_mod & _T_2302; // @[dec_tlu_ctl.scala 2470:48] + wire _T_2314 = io_i0_valid_wb | io_exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 2485:51] + wire _T_2315 = _T_2314 | io_interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 2485:78] + wire _T_2316 = _T_2315 | io_dec_tlu_i0_valid_wb1; // @[dec_tlu_ctl.scala 2485:104] + wire _T_2317 = _T_2316 | io_dec_tlu_i0_exc_valid_wb1; // @[dec_tlu_ctl.scala 2485:130] + wire _T_2318 = _T_2317 | io_dec_tlu_int_valid_wb1; // @[dec_tlu_ctl.scala 2486:32] + reg _T_2321; // @[dec_tlu_ctl.scala 2488:62] + wire _T_2322 = io_i0_exception_valid_r_d1 | io_lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 2489:91] + wire _T_2323 = ~io_trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 2489:137] + wire _T_2324 = io_trigger_hit_r_d1 & _T_2323; // @[dec_tlu_ctl.scala 2489:135] + reg _T_2326; // @[dec_tlu_ctl.scala 2489:62] + reg [4:0] _T_2327; // @[dec_tlu_ctl.scala 2490:62] + reg _T_2328; // @[dec_tlu_ctl.scala 2491:62] + wire [31:0] _T_2334 = {io_core_id,4'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2343 = {21'h3,3'h0,io_mstatus[1],3'h0,io_mstatus[0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2348 = {io_mtvec[30:1],1'h0,io_mtvec[0]}; // @[Cat.scala 29:58] + wire [31:0] _T_2361 = {1'h0,io_mip[5:3],16'h0,io_mip[2],3'h0,io_mip[1],3'h0,io_mip[0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2374 = {1'h0,mie[5:3],16'h0,mie[2],3'h0,mie[1],3'h0,mie[0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2386 = {io_mepc,1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2391 = {28'h0,mscause}; // @[Cat.scala 29:58] + wire [31:0] _T_2399 = {meivt,10'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2402 = {meivt,meihap,2'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2405 = {28'h0,meicurpl}; // @[Cat.scala 29:58] + wire [31:0] _T_2408 = {28'h0,meicidpl}; // @[Cat.scala 29:58] + wire [31:0] _T_2411 = {28'h0,meipt}; // @[Cat.scala 29:58] + wire [31:0] _T_2414 = {23'h0,mcgc}; // @[Cat.scala 29:58] + wire [31:0] _T_2417 = {13'h0,_T_345,4'h0,mfdc_int[11:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_2421 = {16'h4000,io_dcsr[15:2],2'h3}; // @[Cat.scala 29:58] + wire [31:0] _T_2423 = {io_dpc,1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2439 = {7'h0,dicawics[16],2'h0,dicawics[15:14],3'h0,dicawics[13:0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2442 = {30'h0,mtsel}; // @[Cat.scala 29:58] + wire [31:0] _T_2471 = {26'h0,mfdht}; // @[Cat.scala 29:58] + wire [31:0] _T_2474 = {30'h0,mfdhs}; // @[Cat.scala 29:58] + wire [31:0] _T_2477 = {22'h0,mhpme3}; // @[Cat.scala 29:58] + wire [31:0] _T_2480 = {22'h0,mhpme4}; // @[Cat.scala 29:58] + wire [31:0] _T_2483 = {22'h0,mhpme5}; // @[Cat.scala 29:58] + wire [31:0] _T_2486 = {22'h0,mhpme6}; // @[Cat.scala 29:58] + wire [31:0] _T_2489 = {25'h0,temp_ncount6_2,1'h0,temp_ncount0}; // @[Cat.scala 29:58] + wire [31:0] _T_2492 = {30'h0,mpmc,1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2495 = io_csr_pkt_csr_misa ? 32'h40001104 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2496 = io_csr_pkt_csr_mvendorid ? 32'h45 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2497 = io_csr_pkt_csr_marchid ? 32'h10 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2498 = io_csr_pkt_csr_mimpid ? 32'h1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2499 = io_csr_pkt_csr_mhartid ? _T_2334 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2500 = io_csr_pkt_csr_mstatus ? _T_2343 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2501 = io_csr_pkt_csr_mtvec ? _T_2348 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2502 = io_csr_pkt_csr_mip ? _T_2361 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2503 = io_csr_pkt_csr_mie ? _T_2374 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2504 = io_csr_pkt_csr_mcyclel ? mcyclel : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2505 = io_csr_pkt_csr_mcycleh ? mcycleh_inc : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2506 = io_csr_pkt_csr_minstretl ? minstretl : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2507 = io_csr_pkt_csr_minstreth ? minstreth_inc : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2508 = io_csr_pkt_csr_mscratch ? mscratch : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2509 = io_csr_pkt_csr_mepc ? _T_2386 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2510 = io_csr_pkt_csr_mcause ? mcause : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2511 = io_csr_pkt_csr_mscause ? _T_2391 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2512 = io_csr_pkt_csr_mtval ? mtval : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2513 = io_csr_pkt_csr_mrac ? mrac : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2514 = io_csr_pkt_csr_mdseac ? mdseac : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2515 = io_csr_pkt_csr_meivt ? _T_2399 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2516 = io_csr_pkt_csr_meihap ? _T_2402 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2517 = io_csr_pkt_csr_meicurpl ? _T_2405 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2518 = io_csr_pkt_csr_meicidpl ? _T_2408 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2519 = io_csr_pkt_csr_meipt ? _T_2411 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2520 = io_csr_pkt_csr_mcgc ? _T_2414 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2521 = io_csr_pkt_csr_mfdc ? _T_2417 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2522 = io_csr_pkt_csr_dcsr ? _T_2421 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2523 = io_csr_pkt_csr_dpc ? _T_2423 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2524 = io_csr_pkt_csr_dicad0 ? dicad0[31:0] : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2525 = io_csr_pkt_csr_dicad0h ? dicad0h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2526 = io_csr_pkt_csr_dicad1 ? dicad1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2527 = io_csr_pkt_csr_dicawics ? _T_2439 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2528 = io_csr_pkt_csr_mtsel ? _T_2442 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2529 = io_csr_pkt_csr_mtdata1 ? mtdata1_tsel_out : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2530 = io_csr_pkt_csr_mtdata2 ? mtdata2_tsel_out : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2531 = io_csr_pkt_csr_micect ? micect : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2532 = io_csr_pkt_csr_miccmect ? miccmect : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2533 = io_csr_pkt_csr_mdccmect ? mdccmect : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2534 = io_csr_pkt_csr_mhpmc3 ? mhpmc3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2535 = io_csr_pkt_csr_mhpmc4 ? mhpmc4 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2536 = io_csr_pkt_csr_mhpmc5 ? mhpmc5 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2537 = io_csr_pkt_csr_mhpmc6 ? mhpmc6 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2538 = io_csr_pkt_csr_mhpmc3h ? mhpmc3h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2539 = io_csr_pkt_csr_mhpmc4h ? mhpmc4h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2540 = io_csr_pkt_csr_mhpmc5h ? mhpmc5h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2541 = io_csr_pkt_csr_mhpmc6h ? mhpmc6h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2542 = io_csr_pkt_csr_mfdht ? _T_2471 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2543 = io_csr_pkt_csr_mfdhs ? _T_2474 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2544 = io_csr_pkt_csr_mhpme3 ? _T_2477 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2545 = io_csr_pkt_csr_mhpme4 ? _T_2480 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2546 = io_csr_pkt_csr_mhpme5 ? _T_2483 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2547 = io_csr_pkt_csr_mhpme6 ? _T_2486 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2548 = io_csr_pkt_csr_mcountinhibit ? _T_2489 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2549 = io_csr_pkt_csr_mpmc ? _T_2492 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2550 = io_dec_timer_read_d ? io_dec_timer_rddata_d : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2551 = _T_2495 | _T_2496; // @[Mux.scala 27:72] + wire [31:0] _T_2552 = _T_2551 | _T_2497; // @[Mux.scala 27:72] + wire [31:0] _T_2553 = _T_2552 | _T_2498; // @[Mux.scala 27:72] + wire [31:0] _T_2554 = _T_2553 | _T_2499; // @[Mux.scala 27:72] + wire [31:0] _T_2555 = _T_2554 | _T_2500; // @[Mux.scala 27:72] + wire [31:0] _T_2556 = _T_2555 | _T_2501; // @[Mux.scala 27:72] + wire [31:0] _T_2557 = _T_2556 | _T_2502; // @[Mux.scala 27:72] + wire [31:0] _T_2558 = _T_2557 | _T_2503; // @[Mux.scala 27:72] + wire [31:0] _T_2559 = _T_2558 | _T_2504; // @[Mux.scala 27:72] + wire [31:0] _T_2560 = _T_2559 | _T_2505; // @[Mux.scala 27:72] + wire [31:0] _T_2561 = _T_2560 | _T_2506; // @[Mux.scala 27:72] wire [31:0] _T_2562 = _T_2561 | _T_2507; // @[Mux.scala 27:72] wire [31:0] _T_2563 = _T_2562 | _T_2508; // @[Mux.scala 27:72] wire [31:0] _T_2564 = _T_2563 | _T_2509; // @[Mux.scala 27:72] @@ -52355,16 +52385,6 @@ module csr_tlu( wire [31:0] _T_2602 = _T_2601 | _T_2547; // @[Mux.scala 27:72] wire [31:0] _T_2603 = _T_2602 | _T_2548; // @[Mux.scala 27:72] wire [31:0] _T_2604 = _T_2603 | _T_2549; // @[Mux.scala 27:72] - wire [31:0] _T_2605 = _T_2604 | _T_2550; // @[Mux.scala 27:72] - wire [31:0] _T_2606 = _T_2605 | _T_2551; // @[Mux.scala 27:72] - wire [31:0] _T_2607 = _T_2606 | _T_2552; // @[Mux.scala 27:72] - wire [31:0] _T_2608 = _T_2607 | _T_2553; // @[Mux.scala 27:72] - wire [31:0] _T_2609 = _T_2608 | _T_2554; // @[Mux.scala 27:72] - wire [31:0] _T_2610 = _T_2609 | _T_2555; // @[Mux.scala 27:72] - wire [31:0] _T_2611 = _T_2610 | _T_2556; // @[Mux.scala 27:72] - wire [31:0] _T_2612 = _T_2611 | _T_2557; // @[Mux.scala 27:72] - wire [31:0] _T_2613 = _T_2612 | _T_2558; // @[Mux.scala 27:72] - wire [31:0] _T_2614 = _T_2613 | _T_2559; // @[Mux.scala 27:72] rvclkhdr rvclkhdr ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), @@ -52575,7 +52595,7 @@ module csr_tlu( .io_en(rvclkhdr_34_io_en), .io_scan_mode(rvclkhdr_34_io_scan_mode) ); - assign io_dec_tlu_ic_diag_pkt_icache_wrdata = {_T_764,dicad0[31:0]}; // @[dec_tlu_ctl.scala 2155:56] + assign io_dec_tlu_ic_diag_pkt_icache_wrdata = {_T_754,dicad0[31:0]}; // @[dec_tlu_ctl.scala 2155:56] assign io_dec_tlu_ic_diag_pkt_icache_dicawics = dicawics; // @[dec_tlu_ctl.scala 2158:41] assign io_dec_tlu_ic_diag_pkt_icache_rd_valid = icache_rd_valid_f; // @[dec_tlu_ctl.scala 2166:41] assign io_dec_tlu_ic_diag_pkt_icache_wr_valid = icache_wr_valid_f; // @[dec_tlu_ctl.scala 2167:41] @@ -52607,15 +52627,15 @@ module csr_tlu( assign io_trigger_pkt_any_3_execute = io_mtdata1_t_3[2]; // @[dec_tlu_ctl.scala 2235:40] assign io_trigger_pkt_any_3_m = io_mtdata1_t_3[3]; // @[dec_tlu_ctl.scala 2236:40] assign io_trigger_pkt_any_3_tdata2 = mtdata2_t_3; // @[dec_tlu_ctl.scala 2249:51] - assign io_dec_tlu_int_valid_wb1 = _T_2338; // @[dec_tlu_ctl.scala 2491:30] - assign io_dec_tlu_i0_exc_valid_wb1 = _T_2336; // @[dec_tlu_ctl.scala 2489:30] - assign io_dec_tlu_i0_valid_wb1 = _T_2331; // @[dec_tlu_ctl.scala 2488:30] + assign io_dec_tlu_int_valid_wb1 = _T_2328; // @[dec_tlu_ctl.scala 2491:30] + assign io_dec_tlu_i0_exc_valid_wb1 = _T_2326; // @[dec_tlu_ctl.scala 2489:30] + assign io_dec_tlu_i0_valid_wb1 = _T_2321; // @[dec_tlu_ctl.scala 2488:30] assign io_dec_tlu_mtval_wb1 = mtval; // @[dec_tlu_ctl.scala 2493:24] - assign io_dec_tlu_exc_cause_wb1 = _T_2337; // @[dec_tlu_ctl.scala 2490:30] - assign io_dec_tlu_perfcnt0 = mhpmc_inc_r_d1_0 & _T_2183; // @[dec_tlu_ctl.scala 2345:22] - assign io_dec_tlu_perfcnt1 = mhpmc_inc_r_d1_1 & _T_2188; // @[dec_tlu_ctl.scala 2346:22] - assign io_dec_tlu_perfcnt2 = mhpmc_inc_r_d1_2 & _T_2193; // @[dec_tlu_ctl.scala 2347:22] - assign io_dec_tlu_perfcnt3 = mhpmc_inc_r_d1_3 & _T_2198; // @[dec_tlu_ctl.scala 2348:22] + assign io_dec_tlu_exc_cause_wb1 = _T_2327; // @[dec_tlu_ctl.scala 2490:30] + assign io_dec_tlu_perfcnt0 = mhpmc_inc_r_d1_0 & _T_2173; // @[dec_tlu_ctl.scala 2345:22] + assign io_dec_tlu_perfcnt1 = mhpmc_inc_r_d1_1 & _T_2178; // @[dec_tlu_ctl.scala 2346:22] + assign io_dec_tlu_perfcnt2 = mhpmc_inc_r_d1_2 & _T_2183; // @[dec_tlu_ctl.scala 2347:22] + assign io_dec_tlu_perfcnt3 = mhpmc_inc_r_d1_3 & _T_2188; // @[dec_tlu_ctl.scala 2348:22] assign io_dec_tlu_misc_clk_override = mcgc[8]; // @[dec_tlu_ctl.scala 1718:31] assign io_dec_tlu_dec_clk_override = mcgc[7]; // @[dec_tlu_ctl.scala 1719:31] assign io_dec_tlu_lsu_clk_override = mcgc[4]; // @[dec_tlu_ctl.scala 1721:31] @@ -52623,9 +52643,9 @@ module csr_tlu( assign io_dec_tlu_pic_clk_override = mcgc[2]; // @[dec_tlu_ctl.scala 1723:31] assign io_dec_tlu_dccm_clk_override = mcgc[1]; // @[dec_tlu_ctl.scala 1724:31] assign io_dec_tlu_icm_clk_override = mcgc[0]; // @[dec_tlu_ctl.scala 1725:31] - assign io_dec_csr_rddata_d = _T_2614 | _T_2560; // @[dec_tlu_ctl.scala 2498:21] + assign io_dec_csr_rddata_d = _T_2604 | _T_2550; // @[dec_tlu_ctl.scala 2498:21] assign io_dec_tlu_pipelining_disable = mfdc[0]; // @[dec_tlu_ctl.scala 1768:39] - assign io_dec_tlu_wr_pause_r = _T_370 & _T_371; // @[dec_tlu_ctl.scala 1777:24] + assign io_dec_tlu_wr_pause_r = _T_360 & _T_361; // @[dec_tlu_ctl.scala 1777:24] assign io_dec_tlu_meipt = meipt; // @[dec_tlu_ctl.scala 2006:19] assign io_dec_tlu_meicurpl = meicurpl; // @[dec_tlu_ctl.scala 1970:22] assign io_dec_tlu_meihap = {meivt,meihap}; // @[dec_tlu_ctl.scala 1956:20] @@ -52636,23 +52656,23 @@ module csr_tlu( assign io_dec_tlu_external_ldfwd_disable = mfdc[11]; // @[dec_tlu_ctl.scala 1763:39] assign io_dec_tlu_dma_qos_prty = mfdc[18:16]; // @[dec_tlu_ctl.scala 1762:39] assign io_dec_csr_wen_r_mod = _T_1 & _T_2; // @[dec_tlu_ctl.scala 1451:23] - assign io_fw_halt_req = _T_502 & _T_503; // @[dec_tlu_ctl.scala 1842:17] + assign io_fw_halt_req = _T_492 & _T_493; // @[dec_tlu_ctl.scala 1842:17] assign io_mstatus = _T_56; // @[dec_tlu_ctl.scala 1467:13] assign io_mstatus_mie_ns = io_mstatus[0] & _T_54; // @[dec_tlu_ctl.scala 1466:20] - assign io_dcsr = _T_701; // @[dec_tlu_ctl.scala 2053:10] + assign io_dcsr = _T_691; // @[dec_tlu_ctl.scala 2053:10] assign io_mtvec = _T_62; // @[dec_tlu_ctl.scala 1479:11] assign io_mip = _T_68; // @[dec_tlu_ctl.scala 1494:9] assign io_mie_ns = wr_mie_r ? _T_78 : mie; // @[dec_tlu_ctl.scala 1508:12] assign io_npc_r = _T_161 | _T_159; // @[dec_tlu_ctl.scala 1602:11] assign io_npc_r_d1 = _T_167; // @[dec_tlu_ctl.scala 1608:14] assign io_mepc = _T_196; // @[dec_tlu_ctl.scala 1627:10] - assign io_mdseac_locked_ns = mdseac_en | _T_489; // @[dec_tlu_ctl.scala 1825:22] - assign io_force_halt = mfdht[0] & _T_609; // @[dec_tlu_ctl.scala 1933:16] - assign io_dpc = _T_726; // @[dec_tlu_ctl.scala 2070:9] - assign io_mtdata1_t_0 = _T_873; // @[dec_tlu_ctl.scala 2226:39] - assign io_mtdata1_t_1 = _T_874; // @[dec_tlu_ctl.scala 2226:39] - assign io_mtdata1_t_2 = _T_875; // @[dec_tlu_ctl.scala 2226:39] - assign io_mtdata1_t_3 = _T_876; // @[dec_tlu_ctl.scala 2226:39] + assign io_mdseac_locked_ns = mdseac_en | _T_479; // @[dec_tlu_ctl.scala 1825:22] + assign io_force_halt = mfdht[0] & _T_599; // @[dec_tlu_ctl.scala 1933:16] + assign io_dpc = _T_716; // @[dec_tlu_ctl.scala 2070:9] + assign io_mtdata1_t_0 = _T_863; // @[dec_tlu_ctl.scala 2226:39] + assign io_mtdata1_t_1 = _T_864; // @[dec_tlu_ctl.scala 2226:39] + assign io_mtdata1_t_2 = _T_865; // @[dec_tlu_ctl.scala 2226:39] + assign io_mtdata1_t_3 = _T_866; // @[dec_tlu_ctl.scala 2226:39] assign rvclkhdr_io_clk = clock; // @[lib.scala 370:18] assign rvclkhdr_io_en = io_dec_csr_wen_r_mod & _T_58; // @[lib.scala 371:17] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] @@ -52684,34 +52704,34 @@ module csr_tlu( assign rvclkhdr_9_io_en = io_dec_csr_wen_r_mod & _T_337; // @[lib.scala 371:17] assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_10_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_10_io_en = io_dec_csr_wen_r_mod & _T_374; // @[lib.scala 371:17] + assign rvclkhdr_10_io_en = io_dec_csr_wen_r_mod & _T_364; // @[lib.scala 371:17] assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_11_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_11_io_en = _T_493 & _T_494; // @[lib.scala 371:17] + assign rvclkhdr_11_io_en = _T_483 & _T_484; // @[lib.scala 371:17] assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_12_io_clk = clock; // @[lib.scala 370:18] assign rvclkhdr_12_io_en = wr_micect_r | io_ic_perr_r_d1; // @[lib.scala 371:17] assign rvclkhdr_12_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_13_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_13_io_en = _T_549 | io_iccm_dma_sb_error; // @[lib.scala 371:17] + assign rvclkhdr_13_io_en = _T_539 | io_iccm_dma_sb_error; // @[lib.scala 371:17] assign rvclkhdr_13_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_14_io_clk = clock; // @[lib.scala 370:18] assign rvclkhdr_14_io_en = wr_mdccmect_r | io_lsu_single_ecc_error_r_d1; // @[lib.scala 371:17] assign rvclkhdr_14_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_15_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_15_io_en = io_dec_csr_wen_r_mod & _T_612; // @[lib.scala 371:17] + assign rvclkhdr_15_io_en = io_dec_csr_wen_r_mod & _T_602; // @[lib.scala 371:17] assign rvclkhdr_15_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_16_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_16_io_en = _T_632 | io_take_ext_int_start; // @[lib.scala 371:17] + assign rvclkhdr_16_io_en = _T_622 | io_take_ext_int_start; // @[lib.scala 371:17] assign rvclkhdr_16_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_17_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_17_io_en = _T_698 | io_take_nmi; // @[lib.scala 371:17] + assign rvclkhdr_17_io_en = _T_688 | io_take_nmi; // @[lib.scala 371:17] assign rvclkhdr_17_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_18_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_18_io_en = _T_723 | dpc_capture_npc; // @[lib.scala 371:17] + assign rvclkhdr_18_io_en = _T_713 | dpc_capture_npc; // @[lib.scala 371:17] assign rvclkhdr_18_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_19_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_19_io_en = _T_663 & _T_733; // @[lib.scala 371:17] + assign rvclkhdr_19_io_en = _T_653 & _T_723; // @[lib.scala 371:17] assign rvclkhdr_19_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_20_io_clk = clock; // @[lib.scala 370:18] assign rvclkhdr_20_io_en = wr_dicad0_r | io_ifu_ic_debug_rd_data_valid; // @[lib.scala 371:17] @@ -52720,16 +52740,16 @@ module csr_tlu( assign rvclkhdr_21_io_en = wr_dicad0h_r | io_ifu_ic_debug_rd_data_valid; // @[lib.scala 371:17] assign rvclkhdr_21_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_22_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_22_io_en = _T_972 & _T_808; // @[lib.scala 371:17] + assign rvclkhdr_22_io_en = _T_962 & _T_798; // @[lib.scala 371:17] assign rvclkhdr_22_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_23_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_23_io_en = _T_981 & _T_817; // @[lib.scala 371:17] + assign rvclkhdr_23_io_en = _T_971 & _T_807; // @[lib.scala 371:17] assign rvclkhdr_23_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_24_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_24_io_en = _T_990 & _T_826; // @[lib.scala 371:17] + assign rvclkhdr_24_io_en = _T_980 & _T_816; // @[lib.scala 371:17] assign rvclkhdr_24_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_25_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_25_io_en = _T_999 & _T_835; // @[lib.scala 371:17] + assign rvclkhdr_25_io_en = _T_989 & _T_825; // @[lib.scala 371:17] assign rvclkhdr_25_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_26_io_clk = clock; // @[lib.scala 370:18] assign rvclkhdr_26_io_en = mhpmc3_wr_en0 | mhpmc3_wr_en1; // @[lib.scala 371:17] @@ -52756,7 +52776,7 @@ module csr_tlu( assign rvclkhdr_33_io_en = mhpmc6h_wr_en0 | mhpmc6_wr_en1; // @[lib.scala 371:17] assign rvclkhdr_33_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_34_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_34_io_en = _T_2328 | io_clk_override; // @[lib.scala 345:16] + assign rvclkhdr_34_io_en = _T_2318 | io_clk_override; // @[lib.scala 345:16] assign rvclkhdr_34_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE @@ -52866,9 +52886,9 @@ initial begin _RAND_35 = {1{`RANDOM}}; meipt = _RAND_35[3:0]; _RAND_36 = {1{`RANDOM}}; - _T_701 = _RAND_36[15:0]; + _T_691 = _RAND_36[15:0]; _RAND_37 = {1{`RANDOM}}; - _T_726 = _RAND_37[30:0]; + _T_716 = _RAND_37[30:0]; _RAND_38 = {1{`RANDOM}}; dicawics = _RAND_38[16:0]; _RAND_39 = {3{`RANDOM}}; @@ -52876,7 +52896,7 @@ initial begin _RAND_40 = {1{`RANDOM}}; dicad0h = _RAND_40[31:0]; _RAND_41 = {1{`RANDOM}}; - _T_759 = _RAND_41[6:0]; + _T_749 = _RAND_41[6:0]; _RAND_42 = {1{`RANDOM}}; icache_rd_valid_f = _RAND_42[0:0]; _RAND_43 = {1{`RANDOM}}; @@ -52884,13 +52904,13 @@ initial begin _RAND_44 = {1{`RANDOM}}; mtsel = _RAND_44[1:0]; _RAND_45 = {1{`RANDOM}}; - _T_873 = _RAND_45[9:0]; + _T_863 = _RAND_45[9:0]; _RAND_46 = {1{`RANDOM}}; - _T_874 = _RAND_46[9:0]; + _T_864 = _RAND_46[9:0]; _RAND_47 = {1{`RANDOM}}; - _T_875 = _RAND_47[9:0]; + _T_865 = _RAND_47[9:0]; _RAND_48 = {1{`RANDOM}}; - _T_876 = _RAND_48[9:0]; + _T_866 = _RAND_48[9:0]; _RAND_49 = {1{`RANDOM}}; mtdata2_t_0 = _RAND_49[31:0]; _RAND_50 = {1{`RANDOM}}; @@ -52934,13 +52954,13 @@ initial begin _RAND_69 = {1{`RANDOM}}; mhpmc6 = _RAND_69[31:0]; _RAND_70 = {1{`RANDOM}}; - _T_2331 = _RAND_70[0:0]; + _T_2321 = _RAND_70[0:0]; _RAND_71 = {1{`RANDOM}}; - _T_2336 = _RAND_71[0:0]; + _T_2326 = _RAND_71[0:0]; _RAND_72 = {1{`RANDOM}}; - _T_2337 = _RAND_72[4:0]; + _T_2327 = _RAND_72[4:0]; _RAND_73 = {1{`RANDOM}}; - _T_2338 = _RAND_73[0:0]; + _T_2328 = _RAND_73[0:0]; `endif // RANDOMIZE_REG_INIT if (reset) begin mpmc_b = 1'h0; @@ -53051,10 +53071,10 @@ initial begin meipt = 4'h0; end if (reset) begin - _T_701 = 16'h0; + _T_691 = 16'h0; end if (reset) begin - _T_726 = 31'h0; + _T_716 = 31'h0; end if (reset) begin dicawics = 17'h0; @@ -53066,7 +53086,7 @@ initial begin dicad0h = 32'h0; end if (reset) begin - _T_759 = 7'h0; + _T_749 = 7'h0; end if (reset) begin icache_rd_valid_f = 1'h0; @@ -53078,16 +53098,16 @@ initial begin mtsel = 2'h0; end if (reset) begin - _T_873 = 10'h0; + _T_863 = 10'h0; end if (reset) begin - _T_874 = 10'h0; + _T_864 = 10'h0; end if (reset) begin - _T_875 = 10'h0; + _T_865 = 10'h0; end if (reset) begin - _T_876 = 10'h0; + _T_866 = 10'h0; end if (reset) begin mtdata2_t_0 = 32'h0; @@ -53153,16 +53173,16 @@ initial begin mhpmc6 = 32'h0; end if (reset) begin - _T_2331 = 1'h0; + _T_2321 = 1'h0; end if (reset) begin - _T_2336 = 1'h0; + _T_2326 = 1'h0; end if (reset) begin - _T_2337 = 5'h0; + _T_2327 = 5'h0; end if (reset) begin - _T_2338 = 1'h0; + _T_2328 = 1'h0; end `endif // RANDOMIZE end // initial @@ -53174,9 +53194,9 @@ end // initial if (reset) begin mpmc_b <= 1'h0; end else if (wr_mpmc_r) begin - mpmc_b <= _T_510; + mpmc_b <= _T_500; end else begin - mpmc_b <= _T_511; + mpmc_b <= _T_501; end end always @(posedge io_free_clk or posedge reset) begin @@ -53197,27 +53217,27 @@ end // initial if (reset) begin mdccmect <= 32'h0; end else if (wr_mdccmect_r) begin - mdccmect <= _T_525; + mdccmect <= _T_515; end else begin - mdccmect <= _T_569; + mdccmect <= _T_559; end end always @(posedge rvclkhdr_13_io_l1clk or posedge reset) begin if (reset) begin miccmect <= 32'h0; end else if (wr_miccmect_r) begin - miccmect <= _T_525; + miccmect <= _T_515; end else begin - miccmect <= _T_548; + miccmect <= _T_538; end end always @(posedge rvclkhdr_12_io_l1clk or posedge reset) begin if (reset) begin micect <= 32'h0; end else if (wr_micect_r) begin - micect <= _T_525; + micect <= _T_515; end else begin - micect <= _T_527; + micect <= _T_517; end end always @(posedge io_free_clk or posedge reset) begin @@ -53365,14 +53385,14 @@ end // initial if (reset) begin mfdc_int <= 15'h0; end else begin - mfdc_int <= {_T_347,_T_346}; + mfdc_int <= {_T_341,io_dec_csr_wrdata_r[11:0]}; end end always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin if (reset) begin mrac <= 32'h0; end else begin - mrac <= {_T_484,_T_469}; + mrac <= {_T_474,_T_459}; end end always @(posedge rvclkhdr_11_io_l1clk or posedge reset) begin @@ -53392,11 +53412,11 @@ end // initial always @(posedge io_active_clk or posedge reset) begin if (reset) begin mfdhs <= 2'h0; - end else if (_T_595) begin + end else if (_T_585) begin if (wr_mfdhs_r) begin mfdhs <= io_dec_csr_wrdata_r[1:0]; - end else if (_T_589) begin - mfdhs <= _T_593; + end else if (_T_579) begin + mfdhs <= _T_583; end end end @@ -53405,7 +53425,7 @@ end // initial force_halt_ctr_f <= 32'h0; end else if (mfdht[0]) begin if (io_debug_halt_req_f) begin - force_halt_ctr_f <= _T_600; + force_halt_ctr_f <= _T_590; end else if (io_dbg_tlu_halted_f) begin force_halt_ctr_f <= 32'h0; end @@ -53450,27 +53470,27 @@ end // initial end always @(posedge rvclkhdr_17_io_l1clk or posedge reset) begin if (reset) begin - _T_701 <= 16'h0; + _T_691 <= 16'h0; end else if (enter_debug_halt_req_le) begin - _T_701 <= _T_675; + _T_691 <= _T_665; end else if (wr_dcsr_r) begin - _T_701 <= _T_690; + _T_691 <= _T_680; end else begin - _T_701 <= _T_695; + _T_691 <= _T_685; end end always @(posedge rvclkhdr_18_io_l1clk or posedge reset) begin if (reset) begin - _T_726 <= 31'h0; + _T_716 <= 31'h0; end else begin - _T_726 <= _T_721 | _T_720; + _T_716 <= _T_711 | _T_710; end end always @(posedge rvclkhdr_19_io_l1clk or posedge reset) begin if (reset) begin dicawics <= 17'h0; end else begin - dicawics <= {_T_730,io_dec_csr_wrdata_r[16:3]}; + dicawics <= {_T_720,io_dec_csr_wrdata_r[16:3]}; end end always @(posedge rvclkhdr_20_io_l1clk or posedge reset) begin @@ -53493,12 +53513,12 @@ end // initial end always @(posedge io_active_clk or posedge reset) begin if (reset) begin - _T_759 <= 7'h0; - end else if (_T_757) begin - if (_T_752) begin - _T_759 <= io_dec_csr_wrdata_r[6:0]; + _T_749 <= 7'h0; + end else if (_T_747) begin + if (_T_742) begin + _T_749 <= io_dec_csr_wrdata_r[6:0]; end else begin - _T_759 <= io_ifu_ic_debug_rd_data[70:64]; + _T_749 <= io_ifu_ic_debug_rd_data[70:64]; end end end @@ -53506,14 +53526,14 @@ end // initial if (reset) begin icache_rd_valid_f <= 1'h0; end else begin - icache_rd_valid_f <= _T_769 & _T_771; + icache_rd_valid_f <= _T_759 & _T_761; end end always @(posedge io_active_clk or posedge reset) begin if (reset) begin icache_wr_valid_f <= 1'h0; end else begin - icache_wr_valid_f <= _T_663 & _T_774; + icache_wr_valid_f <= _T_653 & _T_764; end end always @(posedge io_csr_wr_clk or posedge reset) begin @@ -53525,38 +53545,38 @@ end // initial end always @(posedge io_active_clk or posedge reset) begin if (reset) begin - _T_873 <= 10'h0; + _T_863 <= 10'h0; end else if (wr_mtdata1_t_r_0) begin - _T_873 <= tdata_wrdata_r; + _T_863 <= tdata_wrdata_r; end else begin - _T_873 <= _T_844; + _T_863 <= _T_834; end end always @(posedge io_active_clk or posedge reset) begin if (reset) begin - _T_874 <= 10'h0; + _T_864 <= 10'h0; end else if (wr_mtdata1_t_r_1) begin - _T_874 <= tdata_wrdata_r; + _T_864 <= tdata_wrdata_r; end else begin - _T_874 <= _T_853; + _T_864 <= _T_843; end end always @(posedge io_active_clk or posedge reset) begin if (reset) begin - _T_875 <= 10'h0; + _T_865 <= 10'h0; end else if (wr_mtdata1_t_r_2) begin - _T_875 <= tdata_wrdata_r; + _T_865 <= tdata_wrdata_r; end else begin - _T_875 <= _T_862; + _T_865 <= _T_852; end end always @(posedge io_active_clk or posedge reset) begin if (reset) begin - _T_876 <= 10'h0; + _T_866 <= 10'h0; end else if (wr_mtdata1_t_r_3) begin - _T_876 <= tdata_wrdata_r; + _T_866 <= tdata_wrdata_r; end else begin - _T_876 <= _T_871; + _T_866 <= _T_861; end end always @(posedge rvclkhdr_22_io_l1clk or posedge reset) begin @@ -53591,7 +53611,7 @@ end // initial if (reset) begin mhpme3 <= 10'h0; end else if (wr_mhpme3_r) begin - if (_T_2293) begin + if (_T_2283) begin mhpme3 <= 10'h204; end else begin mhpme3 <= io_dec_csr_wrdata_r[9:0]; @@ -53602,7 +53622,7 @@ end // initial if (reset) begin mhpme4 <= 10'h0; end else if (wr_mhpme4_r) begin - if (_T_2293) begin + if (_T_2283) begin mhpme4 <= 10'h204; end else begin mhpme4 <= io_dec_csr_wrdata_r[9:0]; @@ -53613,7 +53633,7 @@ end // initial if (reset) begin mhpme5 <= 10'h0; end else if (wr_mhpme5_r) begin - if (_T_2293) begin + if (_T_2283) begin mhpme5 <= 10'h204; end else begin mhpme5 <= io_dec_csr_wrdata_r[9:0]; @@ -53624,7 +53644,7 @@ end // initial if (reset) begin mhpme6 <= 10'h0; end else if (wr_mhpme6_r) begin - if (_T_2293) begin + if (_T_2283) begin mhpme6 <= 10'h204; end else begin mhpme6 <= io_dec_csr_wrdata_r[9:0]; @@ -53635,28 +53655,28 @@ end // initial if (reset) begin mhpmc_inc_r_d1_0 <= 1'h0; end else begin - mhpmc_inc_r_d1_0 <= _T_1026 & _T_1306; + mhpmc_inc_r_d1_0 <= _T_1016 & _T_1296; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin mhpmc_inc_r_d1_1 <= 1'h0; end else begin - mhpmc_inc_r_d1_1 <= _T_1310 & _T_1590; + mhpmc_inc_r_d1_1 <= _T_1300 & _T_1580; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin mhpmc_inc_r_d1_2 <= 1'h0; end else begin - mhpmc_inc_r_d1_2 <= _T_1594 & _T_1874; + mhpmc_inc_r_d1_2 <= _T_1584 & _T_1864; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin mhpmc_inc_r_d1_3 <= 1'h0; end else begin - mhpmc_inc_r_d1_3 <= _T_1878 & _T_2158; + mhpmc_inc_r_d1_3 <= _T_1868 & _T_2148; end end always @(posedge io_free_clk or posedge reset) begin @@ -53740,30 +53760,30 @@ end // initial end always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin if (reset) begin - _T_2331 <= 1'h0; + _T_2321 <= 1'h0; end else begin - _T_2331 <= io_i0_valid_wb; + _T_2321 <= io_i0_valid_wb; end end always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin if (reset) begin - _T_2336 <= 1'h0; + _T_2326 <= 1'h0; end else begin - _T_2336 <= _T_2332 | _T_2334; + _T_2326 <= _T_2322 | _T_2324; end end always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin if (reset) begin - _T_2337 <= 5'h0; + _T_2327 <= 5'h0; end else begin - _T_2337 <= io_exc_cause_wb; + _T_2327 <= io_exc_cause_wb; end end always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin if (reset) begin - _T_2338 <= 1'h0; + _T_2328 <= 1'h0; end else begin - _T_2338 <= io_interrupt_valid_r_d1; + _T_2328 <= io_interrupt_valid_r_d1; end end endmodule @@ -59382,16 +59402,22 @@ module dbg( input [6:0] io_dmi_reg_addr, input io_dmi_reg_wr_en, input [31:0] io_dmi_reg_wdata, + output [31:0] io_dmi_reg_rdata, input io_sb_axi_aw_ready, output io_sb_axi_aw_valid, + output [31:0] io_sb_axi_aw_bits_addr, + output [2:0] io_sb_axi_aw_bits_size, input io_sb_axi_w_ready, output io_sb_axi_w_valid, output [63:0] io_sb_axi_w_bits_data, + output [7:0] io_sb_axi_w_bits_strb, output io_sb_axi_b_ready, input io_sb_axi_b_valid, input [1:0] io_sb_axi_b_bits_resp, input io_sb_axi_ar_ready, output io_sb_axi_ar_valid, + output [31:0] io_sb_axi_ar_bits_addr, + output [2:0] io_sb_axi_ar_bits_size, output io_sb_axi_r_ready, input io_sb_axi_r_valid, input [63:0] io_sb_axi_r_bits_data, @@ -59435,6 +59461,7 @@ module dbg( reg [31:0] _RAND_18; reg [31:0] _RAND_19; reg [31:0] _RAND_20; + reg [31:0] _RAND_21; `endif // RANDOMIZE_REG_INIT wire [2:0] dbg_state; wire dbg_state_en; @@ -59604,6 +59631,7 @@ module dbg( wire _T_189 = dmstatus_havereset_wren | dmstatus_havereset; // @[dbg.scala 209:16] wire _T_190 = ~dmstatus_havereset_rst; // @[dbg.scala 209:72] reg _T_192; // @[dbg.scala 209:12] + wire [31:0] haltsum0_reg = {31'h0,dmstatus_halted}; // @[Cat.scala 29:58] wire [31:0] abstractcs_reg; wire _T_194 = abstractcs_reg[12] & io_dmi_reg_en; // @[dbg.scala 215:50] wire _T_195 = io_dmi_reg_addr == 7'h16; // @[dbg.scala 215:106] @@ -59763,7 +59791,42 @@ module dbg( wire _GEN_35 = _T_318 ? _T_328 : _GEN_32; // @[Conditional.scala 39:67] wire _GEN_36 = _T_318 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67] wire _GEN_38 = _T_318 ? 1'h0 : _GEN_31; // @[Conditional.scala 39:67] + wire [31:0] _T_417 = _T_199 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_418 = _T_417 & data0_reg; // @[dbg.scala 315:71] + wire [31:0] _T_421 = _T_294 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_422 = _T_421 & data1_reg; // @[dbg.scala 315:122] + wire [31:0] _T_423 = _T_418 | _T_422; // @[dbg.scala 315:83] + wire [31:0] _T_426 = _T_130 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_427 = _T_426 & dmcontrol_reg; // @[dbg.scala 316:43] + wire [31:0] _T_428 = _T_423 | _T_427; // @[dbg.scala 315:134] + wire _T_429 = io_dmi_reg_addr == 7'h11; // @[dbg.scala 316:86] + wire [31:0] _T_431 = _T_429 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_432 = _T_431 & dmstatus_reg; // @[dbg.scala 316:99] + wire [31:0] _T_433 = _T_428 | _T_432; // @[dbg.scala 316:59] + wire [31:0] _T_436 = _T_195 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_437 = _T_436 & abstractcs_reg; // @[dbg.scala 317:43] + wire [31:0] _T_438 = _T_433 | _T_437; // @[dbg.scala 316:114] + wire [31:0] _T_441 = _T_196 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_442 = _T_441 & command_reg; // @[dbg.scala 317:100] + wire [31:0] _T_443 = _T_438 | _T_442; // @[dbg.scala 317:60] + wire _T_444 = io_dmi_reg_addr == 7'h40; // @[dbg.scala 318:30] + wire [31:0] _T_446 = _T_444 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_447 = _T_446 & haltsum0_reg; // @[dbg.scala 318:43] + wire [31:0] _T_448 = _T_443 | _T_447; // @[dbg.scala 317:114] + wire [31:0] _T_451 = _T_19 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_452 = _T_451 & sbcs_reg; // @[dbg.scala 318:98] + wire [31:0] _T_453 = _T_448 | _T_452; // @[dbg.scala 318:58] + wire [31:0] _T_456 = _T_27 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_457 = _T_456 & sbaddress0_reg; // @[dbg.scala 319:43] + wire [31:0] _T_458 = _T_453 | _T_457; // @[dbg.scala 318:109] + wire [31:0] _T_461 = _T_28 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_462 = _T_461 & sbdata0_reg; // @[dbg.scala 319:100] + wire [31:0] _T_463 = _T_458 | _T_462; // @[dbg.scala 319:60] + wire [31:0] _T_466 = _T_30 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_467 = _T_466 & sbdata1_reg; // @[dbg.scala 320:43] + wire [31:0] dmi_reg_rdata_din = _T_463 | _T_467; // @[dbg.scala 319:114] reg [2:0] _T_468; // @[Reg.scala 27:20] + reg [31:0] _T_469; // @[Reg.scala 27:20] wire _T_471 = command_reg[31:24] == 8'h2; // @[dbg.scala 331:62] wire [31:0] _T_473 = {data1_reg[31:2],2'h0}; // @[Cat.scala 29:58] wire [31:0] _T_475 = {20'h0,command_reg[11:0]}; // @[Cat.scala 29:58] @@ -59855,6 +59918,25 @@ module dbg( wire [63:0] _T_599 = _T_57 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12] wire [63:0] _T_602 = {sbdata1_reg,sbdata0_reg}; // @[Cat.scala 29:58] wire [63:0] _T_603 = _T_599 & _T_602; // @[dbg.scala 427:119] + wire [7:0] _T_608 = _T_62 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [14:0] _T_610 = 15'h1 << sbaddress0_reg[2:0]; // @[dbg.scala 429:82] + wire [14:0] _GEN_115 = {{7'd0}, _T_608}; // @[dbg.scala 429:67] + wire [14:0] _T_611 = _GEN_115 & _T_610; // @[dbg.scala 429:67] + wire [7:0] _T_615 = _T_47 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_617 = {sbaddress0_reg[2:1],1'h0}; // @[Cat.scala 29:58] + wire [14:0] _T_618 = 15'h3 << _T_617; // @[dbg.scala 430:59] + wire [14:0] _GEN_116 = {{7'd0}, _T_615}; // @[dbg.scala 430:44] + wire [14:0] _T_619 = _GEN_116 & _T_618; // @[dbg.scala 430:44] + wire [14:0] _T_620 = _T_611 | _T_619; // @[dbg.scala 429:107] + wire [7:0] _T_624 = _T_51 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_626 = {sbaddress0_reg[2],2'h0}; // @[Cat.scala 29:58] + wire [14:0] _T_627 = 15'hf << _T_626; // @[dbg.scala 431:59] + wire [14:0] _GEN_117 = {{7'd0}, _T_624}; // @[dbg.scala 431:44] + wire [14:0] _T_628 = _GEN_117 & _T_627; // @[dbg.scala 431:44] + wire [14:0] _T_629 = _T_620 | _T_628; // @[dbg.scala 430:97] + wire [7:0] _T_633 = _T_57 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [14:0] _GEN_118 = {{7'd0}, _T_633}; // @[dbg.scala 431:100] + wire [14:0] _T_635 = _T_629 | _GEN_118; // @[dbg.scala 431:100] wire [3:0] _GEN_119 = {{1'd0}, sbaddress0_reg[2:0]}; // @[dbg.scala 448:99] wire [6:0] _T_646 = 4'h8 * _GEN_119; // @[dbg.scala 448:99] wire [63:0] _T_647 = io_sb_axi_r_bits_data >> _T_646; // @[dbg.scala 448:92] @@ -59925,11 +60007,17 @@ module dbg( assign io_dbg_core_rst_l = ~dmcontrol_reg[1]; // @[dbg.scala 107:21] assign io_dbg_halt_req = _T_300 ? _T_316 : _GEN_35; // @[dbg.scala 268:19 dbg.scala 274:23 dbg.scala 279:23 dbg.scala 290:23 dbg.scala 295:23 dbg.scala 300:23 dbg.scala 307:23 dbg.scala 312:23] assign io_dbg_resume_req = _T_300 ? 1'h0 : _GEN_38; // @[dbg.scala 269:21 dbg.scala 289:25] + assign io_dmi_reg_rdata = _T_469; // @[dbg.scala 327:20] assign io_sb_axi_aw_valid = _T_560 | _T_561; // @[dbg.scala 414:22] + assign io_sb_axi_aw_bits_addr = sbaddress0_reg; // @[dbg.scala 415:26] + assign io_sb_axi_aw_bits_size = sbcs_reg[19:17]; // @[dbg.scala 417:26] assign io_sb_axi_w_valid = _T_560 | _T_567; // @[dbg.scala 425:21] assign io_sb_axi_w_bits_data = _T_595 | _T_603; // @[dbg.scala 426:25] + assign io_sb_axi_w_bits_strb = _T_635[7:0]; // @[dbg.scala 429:25] assign io_sb_axi_b_ready = 1'h1; // @[dbg.scala 446:21] assign io_sb_axi_ar_valid = sb_state == 4'h3; // @[dbg.scala 435:22] + assign io_sb_axi_ar_bits_addr = sbaddress0_reg; // @[dbg.scala 436:26] + assign io_sb_axi_ar_bits_size = sbcs_reg[19:17]; // @[dbg.scala 438:26] assign io_sb_axi_r_ready = 1'h1; // @[dbg.scala 447:21] assign io_dbg_dec_dbg_ib_dbg_cmd_valid = _T_482 & io_dbg_dma_io_dma_dbg_ready; // @[dbg.scala 333:35] assign io_dbg_dec_dbg_ib_dbg_cmd_write = command_reg[16]; // @[dbg.scala 334:35] @@ -60070,7 +60158,9 @@ initial begin _RAND_19 = {1{`RANDOM}}; _T_468 = _RAND_19[2:0]; _RAND_20 = {1{`RANDOM}}; - _T_547 = _RAND_20[3:0]; + _T_469 = _RAND_20[31:0]; + _RAND_21 = {1{`RANDOM}}; + _T_547 = _RAND_21[3:0]; `endif // RANDOMIZE_REG_INIT if (dbg_dm_rst_l) begin temp_sbcs_22 = 1'h0; @@ -60132,6 +60222,9 @@ initial begin if (rst_temp) begin _T_468 = 3'h0; end + if (dbg_dm_rst_l) begin + _T_469 = 32'h0; + end if (dbg_dm_rst_l) begin _T_547 = 4'h0; end @@ -60361,6 +60454,13 @@ end // initial end end end + always @(posedge rvclkhdr_io_l1clk or posedge dbg_dm_rst_l) begin + if (dbg_dm_rst_l) begin + _T_469 <= 32'h0; + end else if (io_dmi_reg_en) begin + _T_469 <= dmi_reg_rdata_din; + end + end always @(posedge rvclkhdr_1_io_l1clk or posedge dbg_dm_rst_l) begin if (dbg_dm_rst_l) begin _T_547 <= 4'h0; @@ -68124,15 +68224,20 @@ module lsu_bus_buffer( input io_lsu_axi_aw_ready, output io_lsu_axi_aw_valid, output [2:0] io_lsu_axi_aw_bits_id, + output [31:0] io_lsu_axi_aw_bits_addr, + output [2:0] io_lsu_axi_aw_bits_size, input io_lsu_axi_w_ready, output io_lsu_axi_w_valid, output [63:0] io_lsu_axi_w_bits_data, + output [7:0] io_lsu_axi_w_bits_strb, output io_lsu_axi_b_ready, input io_lsu_axi_b_valid, input [2:0] io_lsu_axi_b_bits_id, input io_lsu_axi_ar_ready, output io_lsu_axi_ar_valid, output [2:0] io_lsu_axi_ar_bits_id, + output [31:0] io_lsu_axi_ar_bits_addr, + output [2:0] io_lsu_axi_ar_bits_size, output io_lsu_axi_r_ready, input io_lsu_axi_r_valid, input [2:0] io_lsu_axi_r_bits_id, @@ -68226,9 +68331,9 @@ module lsu_bus_buffer( reg [31:0] _RAND_73; reg [31:0] _RAND_74; reg [31:0] _RAND_75; - reg [63:0] _RAND_76; + reg [31:0] _RAND_76; reg [31:0] _RAND_77; - reg [31:0] _RAND_78; + reg [63:0] _RAND_78; reg [31:0] _RAND_79; reg [31:0] _RAND_80; reg [31:0] _RAND_81; @@ -68253,6 +68358,8 @@ module lsu_bus_buffer( reg [31:0] _RAND_100; reg [31:0] _RAND_101; reg [31:0] _RAND_102; + reg [31:0] _RAND_103; + reg [31:0] _RAND_104; `endif // RANDOMIZE_REG_INIT wire rvclkhdr_io_l1clk; // @[lib.scala 368:23] wire rvclkhdr_io_clk; // @[lib.scala 368:23] @@ -69273,6 +69380,20 @@ module lsu_bus_buffer( wire _T_1332 = bus_cmd_sent & _T_1343; // @[lsu_bus_buffer.scala 316:20] wire _T_1333 = ~io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 316:37] wire _T_1334 = _T_1332 & _T_1333; // @[lsu_bus_buffer.scala 316:35] + wire [7:0] _T_1358 = {ldst_byteen_lo_r,4'h0}; // @[Cat.scala 29:58] + wire [7:0] _T_1359 = {4'h0,ldst_byteen_lo_r}; // @[Cat.scala 29:58] + wire [7:0] _T_1360 = io_lsu_addr_r[2] ? _T_1358 : _T_1359; // @[lsu_bus_buffer.scala 323:46] + wire [3:0] _T_1379 = _T_1023 ? buf_byteen_0 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1380 = _T_1024 ? buf_byteen_1 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1381 = _T_1025 ? buf_byteen_2 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1382 = _T_1026 ? buf_byteen_3 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1383 = _T_1379 | _T_1380; // @[Mux.scala 27:72] + wire [3:0] _T_1384 = _T_1383 | _T_1381; // @[Mux.scala 27:72] + wire [3:0] _T_1385 = _T_1384 | _T_1382; // @[Mux.scala 27:72] + wire [7:0] _T_1387 = {_T_1385,4'h0}; // @[Cat.scala 29:58] + wire [7:0] _T_1400 = {4'h0,_T_1385}; // @[Cat.scala 29:58] + wire [7:0] _T_1401 = _T_1289[2] ? _T_1387 : _T_1400; // @[lsu_bus_buffer.scala 324:8] + wire [7:0] obuf_byteen0_in = ibuf_buf_byp ? _T_1360 : _T_1401; // @[lsu_bus_buffer.scala 323:28] wire [7:0] _T_1403 = {ldst_byteen_hi_r,4'h0}; // @[Cat.scala 29:58] wire [7:0] _T_1404 = {4'h0,ldst_byteen_hi_r}; // @[Cat.scala 29:58] wire [7:0] _T_1405 = io_end_addr_r[2] ? _T_1403 : _T_1404; // @[lsu_bus_buffer.scala 325:46] @@ -69362,13 +69483,22 @@ module lsu_bus_buffer( wire _T_1837 = _T_1836 & io_ldst_dual_r; // @[lsu_bus_buffer.scala 342:35] wire obuf_merge_en = _T_1835 | _T_1837; // @[lsu_bus_buffer.scala 341:253] wire _T_1539 = obuf_merge_en & obuf_byteen1_in[0]; // @[lsu_bus_buffer.scala 332:80] + wire _T_1540 = obuf_byteen0_in[0] | _T_1539; // @[lsu_bus_buffer.scala 332:63] wire _T_1543 = obuf_merge_en & obuf_byteen1_in[1]; // @[lsu_bus_buffer.scala 332:80] + wire _T_1544 = obuf_byteen0_in[1] | _T_1543; // @[lsu_bus_buffer.scala 332:63] wire _T_1547 = obuf_merge_en & obuf_byteen1_in[2]; // @[lsu_bus_buffer.scala 332:80] + wire _T_1548 = obuf_byteen0_in[2] | _T_1547; // @[lsu_bus_buffer.scala 332:63] wire _T_1551 = obuf_merge_en & obuf_byteen1_in[3]; // @[lsu_bus_buffer.scala 332:80] + wire _T_1552 = obuf_byteen0_in[3] | _T_1551; // @[lsu_bus_buffer.scala 332:63] wire _T_1555 = obuf_merge_en & obuf_byteen1_in[4]; // @[lsu_bus_buffer.scala 332:80] + wire _T_1556 = obuf_byteen0_in[4] | _T_1555; // @[lsu_bus_buffer.scala 332:63] wire _T_1559 = obuf_merge_en & obuf_byteen1_in[5]; // @[lsu_bus_buffer.scala 332:80] + wire _T_1560 = obuf_byteen0_in[5] | _T_1559; // @[lsu_bus_buffer.scala 332:63] wire _T_1563 = obuf_merge_en & obuf_byteen1_in[6]; // @[lsu_bus_buffer.scala 332:80] + wire _T_1564 = obuf_byteen0_in[6] | _T_1563; // @[lsu_bus_buffer.scala 332:63] wire _T_1567 = obuf_merge_en & obuf_byteen1_in[7]; // @[lsu_bus_buffer.scala 332:80] + wire _T_1568 = obuf_byteen0_in[7] | _T_1567; // @[lsu_bus_buffer.scala 332:63] + wire [7:0] obuf_byteen_in = {_T_1568,_T_1564,_T_1560,_T_1556,_T_1552,_T_1548,_T_1544,_T_1540}; // @[Cat.scala 29:58] wire [7:0] _T_1579 = _T_1539 ? obuf_data1_in[7:0] : obuf_data0_in[7:0]; // @[lsu_bus_buffer.scala 333:44] wire [7:0] _T_1584 = _T_1543 ? obuf_data1_in[15:8] : obuf_data0_in[15:8]; // @[lsu_bus_buffer.scala 333:44] wire [7:0] _T_1589 = _T_1547 ? obuf_data1_in[23:16] : obuf_data0_in[23:16]; // @[lsu_bus_buffer.scala 333:44] @@ -69380,6 +69510,8 @@ module lsu_bus_buffer( wire [55:0] _T_1620 = {_T_1614,_T_1609,_T_1604,_T_1599,_T_1594,_T_1589,_T_1584}; // @[Cat.scala 29:58] wire _T_1839 = obuf_wr_en | obuf_valid; // @[lsu_bus_buffer.scala 345:58] wire _T_1840 = ~obuf_rst; // @[lsu_bus_buffer.scala 345:93] + reg [1:0] obuf_sz; // @[Reg.scala 27:20] + reg [7:0] obuf_byteen; // @[Reg.scala 27:20] reg [63:0] obuf_data; // @[lib.scala 374:16] wire _T_1853 = buf_state_0 == 3'h0; // @[lsu_bus_buffer.scala 363:65] wire _T_1854 = ibuf_tag == 2'h0; // @[lsu_bus_buffer.scala 364:30] @@ -70447,7 +70579,10 @@ module lsu_bus_buffer( wire [63:0] _T_4776 = _GEN_393 | _T_4772; // @[Mux.scala 27:72] wire _T_4874 = obuf_valid & obuf_write; // @[lsu_bus_buffer.scala 568:37] wire _T_4875 = ~obuf_cmd_done; // @[lsu_bus_buffer.scala 568:52] + wire [31:0] _T_4880 = {obuf_addr[31:3],3'h0}; // @[Cat.scala 29:58] + wire [2:0] _T_4882 = {1'h0,obuf_sz}; // @[Cat.scala 29:58] wire _T_4887 = ~obuf_data_done; // @[lsu_bus_buffer.scala 580:51] + wire [7:0] _T_4892 = obuf_write ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] wire _T_4895 = obuf_valid & _T_1343; // @[lsu_bus_buffer.scala 585:37] wire _T_4909 = io_lsu_bus_clk_en_q & buf_error[0]; // @[lsu_bus_buffer.scala 598:126] wire _T_4911 = _T_4909 & buf_write[0]; // @[lsu_bus_buffer.scala 598:141] @@ -70582,11 +70717,16 @@ module lsu_bus_buffer( assign io_dctl_busbuff_lsu_nonblock_load_data = _T_4776[31:0]; // @[lsu_bus_buffer.scala 546:42] assign io_lsu_axi_aw_valid = _T_4874 & _T_4875; // @[lsu_bus_buffer.scala 568:23] assign io_lsu_axi_aw_bits_id = {{1'd0}, _T_1848}; // @[lsu_bus_buffer.scala 569:25] + assign io_lsu_axi_aw_bits_addr = obuf_sideeffect ? obuf_addr : _T_4880; // @[lsu_bus_buffer.scala 570:27] + assign io_lsu_axi_aw_bits_size = obuf_sideeffect ? _T_4882 : 3'h3; // @[lsu_bus_buffer.scala 571:27] assign io_lsu_axi_w_valid = _T_4874 & _T_4887; // @[lsu_bus_buffer.scala 580:22] assign io_lsu_axi_w_bits_data = obuf_data; // @[lsu_bus_buffer.scala 582:26] + assign io_lsu_axi_w_bits_strb = obuf_byteen & _T_4892; // @[lsu_bus_buffer.scala 581:26] assign io_lsu_axi_b_ready = 1'h1; // @[lsu_bus_buffer.scala 596:22] assign io_lsu_axi_ar_valid = _T_4895 & _T_1349; // @[lsu_bus_buffer.scala 585:23] assign io_lsu_axi_ar_bits_id = {{1'd0}, _T_1848}; // @[lsu_bus_buffer.scala 586:25] + assign io_lsu_axi_ar_bits_addr = obuf_sideeffect ? obuf_addr : _T_4880; // @[lsu_bus_buffer.scala 587:27] + assign io_lsu_axi_ar_bits_size = obuf_sideeffect ? _T_4882 : 3'h3; // @[lsu_bus_buffer.scala 588:27] assign io_lsu_axi_r_ready = 1'h1; // @[lsu_bus_buffer.scala 597:22] assign io_lsu_busreq_r = _T_4987; // @[lsu_bus_buffer.scala 616:19] assign io_lsu_bus_buffer_pend_any = |buf_numvld_pend_any; // @[lsu_bus_buffer.scala 525:30] @@ -70819,60 +70959,64 @@ initial begin buf_dualhi_1 = _RAND_74[0:0]; _RAND_75 = {1{`RANDOM}}; buf_dualhi_0 = _RAND_75[0:0]; - _RAND_76 = {2{`RANDOM}}; - obuf_data = _RAND_76[63:0]; + _RAND_76 = {1{`RANDOM}}; + obuf_sz = _RAND_76[1:0]; _RAND_77 = {1{`RANDOM}}; - buf_rspageQ_0 = _RAND_77[3:0]; - _RAND_78 = {1{`RANDOM}}; - buf_rspageQ_1 = _RAND_78[3:0]; + obuf_byteen = _RAND_77[7:0]; + _RAND_78 = {2{`RANDOM}}; + obuf_data = _RAND_78[63:0]; _RAND_79 = {1{`RANDOM}}; - buf_rspageQ_2 = _RAND_79[3:0]; + buf_rspageQ_0 = _RAND_79[3:0]; _RAND_80 = {1{`RANDOM}}; - buf_rspageQ_3 = _RAND_80[3:0]; + buf_rspageQ_1 = _RAND_80[3:0]; _RAND_81 = {1{`RANDOM}}; - _T_4307 = _RAND_81[0:0]; + buf_rspageQ_2 = _RAND_81[3:0]; _RAND_82 = {1{`RANDOM}}; - _T_4305 = _RAND_82[0:0]; + buf_rspageQ_3 = _RAND_82[3:0]; _RAND_83 = {1{`RANDOM}}; - _T_4303 = _RAND_83[0:0]; + _T_4307 = _RAND_83[0:0]; _RAND_84 = {1{`RANDOM}}; - _T_4301 = _RAND_84[0:0]; + _T_4305 = _RAND_84[0:0]; _RAND_85 = {1{`RANDOM}}; - buf_ldfwdtag_0 = _RAND_85[1:0]; + _T_4303 = _RAND_85[0:0]; _RAND_86 = {1{`RANDOM}}; - buf_dualtag_0 = _RAND_86[1:0]; + _T_4301 = _RAND_86[0:0]; _RAND_87 = {1{`RANDOM}}; - buf_ldfwdtag_3 = _RAND_87[1:0]; + buf_ldfwdtag_0 = _RAND_87[1:0]; _RAND_88 = {1{`RANDOM}}; - buf_ldfwdtag_2 = _RAND_88[1:0]; + buf_dualtag_0 = _RAND_88[1:0]; _RAND_89 = {1{`RANDOM}}; - buf_ldfwdtag_1 = _RAND_89[1:0]; + buf_ldfwdtag_3 = _RAND_89[1:0]; _RAND_90 = {1{`RANDOM}}; - buf_dualtag_1 = _RAND_90[1:0]; + buf_ldfwdtag_2 = _RAND_90[1:0]; _RAND_91 = {1{`RANDOM}}; - buf_dualtag_2 = _RAND_91[1:0]; + buf_ldfwdtag_1 = _RAND_91[1:0]; _RAND_92 = {1{`RANDOM}}; - buf_dualtag_3 = _RAND_92[1:0]; + buf_dualtag_1 = _RAND_92[1:0]; _RAND_93 = {1{`RANDOM}}; - _T_4336 = _RAND_93[0:0]; + buf_dualtag_2 = _RAND_93[1:0]; _RAND_94 = {1{`RANDOM}}; - _T_4339 = _RAND_94[0:0]; + buf_dualtag_3 = _RAND_94[1:0]; _RAND_95 = {1{`RANDOM}}; - _T_4342 = _RAND_95[0:0]; + _T_4336 = _RAND_95[0:0]; _RAND_96 = {1{`RANDOM}}; - _T_4345 = _RAND_96[0:0]; + _T_4339 = _RAND_96[0:0]; _RAND_97 = {1{`RANDOM}}; - _T_4411 = _RAND_97[0:0]; + _T_4342 = _RAND_97[0:0]; _RAND_98 = {1{`RANDOM}}; - _T_4406 = _RAND_98[0:0]; + _T_4345 = _RAND_98[0:0]; _RAND_99 = {1{`RANDOM}}; - _T_4401 = _RAND_99[0:0]; + _T_4411 = _RAND_99[0:0]; _RAND_100 = {1{`RANDOM}}; - _T_4396 = _RAND_100[0:0]; + _T_4406 = _RAND_100[0:0]; _RAND_101 = {1{`RANDOM}}; - lsu_nonblock_load_valid_r = _RAND_101[0:0]; + _T_4401 = _RAND_101[0:0]; _RAND_102 = {1{`RANDOM}}; - _T_4987 = _RAND_102[0:0]; + _T_4396 = _RAND_102[0:0]; + _RAND_103 = {1{`RANDOM}}; + lsu_nonblock_load_valid_r = _RAND_103[0:0]; + _RAND_104 = {1{`RANDOM}}; + _T_4987 = _RAND_104[0:0]; `endif // RANDOMIZE_REG_INIT if (reset) begin buf_addr_0 = 32'h0; @@ -71102,6 +71246,12 @@ initial begin if (reset) begin buf_dualhi_0 = 1'h0; end + if (reset) begin + obuf_sz = 2'h0; + end + if (reset) begin + obuf_byteen = 8'h0; + end if (reset) begin obuf_data = 64'h0; end @@ -72105,6 +72255,24 @@ end // initial buf_dualhi_0 <= buf_dualhi_in[0]; end end + always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin + if (reset) begin + obuf_sz <= 2'h0; + end else if (obuf_wr_en) begin + if (ibuf_buf_byp) begin + obuf_sz <= ibuf_sz_in; + end else begin + obuf_sz <= _T_1302; + end + end + end + always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin + if (reset) begin + obuf_byteen <= 8'h0; + end else if (obuf_wr_en) begin + obuf_byteen <= obuf_byteen_in; + end + end always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin if (reset) begin obuf_data <= 64'h0; @@ -72400,14 +72568,19 @@ module lsu_bus_intf( input io_axi_aw_ready, output io_axi_aw_valid, output [2:0] io_axi_aw_bits_id, + output [31:0] io_axi_aw_bits_addr, + output [2:0] io_axi_aw_bits_size, input io_axi_w_ready, output io_axi_w_valid, output [63:0] io_axi_w_bits_data, + output [7:0] io_axi_w_bits_strb, input io_axi_b_valid, input [2:0] io_axi_b_bits_id, input io_axi_ar_ready, output io_axi_ar_valid, output [2:0] io_axi_ar_bits_id, + output [31:0] io_axi_ar_bits_addr, + output [2:0] io_axi_ar_bits_size, input io_axi_r_valid, input [2:0] io_axi_r_bits_id, input [63:0] io_axi_r_bits_data, @@ -72516,15 +72689,20 @@ module lsu_bus_intf( wire bus_buffer_io_lsu_axi_aw_ready; // @[lsu_bus_intf.scala 101:39] wire bus_buffer_io_lsu_axi_aw_valid; // @[lsu_bus_intf.scala 101:39] wire [2:0] bus_buffer_io_lsu_axi_aw_bits_id; // @[lsu_bus_intf.scala 101:39] + wire [31:0] bus_buffer_io_lsu_axi_aw_bits_addr; // @[lsu_bus_intf.scala 101:39] + wire [2:0] bus_buffer_io_lsu_axi_aw_bits_size; // @[lsu_bus_intf.scala 101:39] wire bus_buffer_io_lsu_axi_w_ready; // @[lsu_bus_intf.scala 101:39] wire bus_buffer_io_lsu_axi_w_valid; // @[lsu_bus_intf.scala 101:39] wire [63:0] bus_buffer_io_lsu_axi_w_bits_data; // @[lsu_bus_intf.scala 101:39] + wire [7:0] bus_buffer_io_lsu_axi_w_bits_strb; // @[lsu_bus_intf.scala 101:39] wire bus_buffer_io_lsu_axi_b_ready; // @[lsu_bus_intf.scala 101:39] wire bus_buffer_io_lsu_axi_b_valid; // @[lsu_bus_intf.scala 101:39] wire [2:0] bus_buffer_io_lsu_axi_b_bits_id; // @[lsu_bus_intf.scala 101:39] wire bus_buffer_io_lsu_axi_ar_ready; // @[lsu_bus_intf.scala 101:39] wire bus_buffer_io_lsu_axi_ar_valid; // @[lsu_bus_intf.scala 101:39] wire [2:0] bus_buffer_io_lsu_axi_ar_bits_id; // @[lsu_bus_intf.scala 101:39] + wire [31:0] bus_buffer_io_lsu_axi_ar_bits_addr; // @[lsu_bus_intf.scala 101:39] + wire [2:0] bus_buffer_io_lsu_axi_ar_bits_size; // @[lsu_bus_intf.scala 101:39] wire bus_buffer_io_lsu_axi_r_ready; // @[lsu_bus_intf.scala 101:39] wire bus_buffer_io_lsu_axi_r_valid; // @[lsu_bus_intf.scala 101:39] wire [2:0] bus_buffer_io_lsu_axi_r_bits_id; // @[lsu_bus_intf.scala 101:39] @@ -72778,15 +72956,20 @@ module lsu_bus_intf( .io_lsu_axi_aw_ready(bus_buffer_io_lsu_axi_aw_ready), .io_lsu_axi_aw_valid(bus_buffer_io_lsu_axi_aw_valid), .io_lsu_axi_aw_bits_id(bus_buffer_io_lsu_axi_aw_bits_id), + .io_lsu_axi_aw_bits_addr(bus_buffer_io_lsu_axi_aw_bits_addr), + .io_lsu_axi_aw_bits_size(bus_buffer_io_lsu_axi_aw_bits_size), .io_lsu_axi_w_ready(bus_buffer_io_lsu_axi_w_ready), .io_lsu_axi_w_valid(bus_buffer_io_lsu_axi_w_valid), .io_lsu_axi_w_bits_data(bus_buffer_io_lsu_axi_w_bits_data), + .io_lsu_axi_w_bits_strb(bus_buffer_io_lsu_axi_w_bits_strb), .io_lsu_axi_b_ready(bus_buffer_io_lsu_axi_b_ready), .io_lsu_axi_b_valid(bus_buffer_io_lsu_axi_b_valid), .io_lsu_axi_b_bits_id(bus_buffer_io_lsu_axi_b_bits_id), .io_lsu_axi_ar_ready(bus_buffer_io_lsu_axi_ar_ready), .io_lsu_axi_ar_valid(bus_buffer_io_lsu_axi_ar_valid), .io_lsu_axi_ar_bits_id(bus_buffer_io_lsu_axi_ar_bits_id), + .io_lsu_axi_ar_bits_addr(bus_buffer_io_lsu_axi_ar_bits_addr), + .io_lsu_axi_ar_bits_size(bus_buffer_io_lsu_axi_ar_bits_size), .io_lsu_axi_r_ready(bus_buffer_io_lsu_axi_r_ready), .io_lsu_axi_r_valid(bus_buffer_io_lsu_axi_r_valid), .io_lsu_axi_r_bits_id(bus_buffer_io_lsu_axi_r_bits_id), @@ -72812,10 +72995,15 @@ module lsu_bus_intf( assign io_tlu_busbuff_lsu_imprecise_error_addr_any = bus_buffer_io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[lsu_bus_intf.scala 104:18] assign io_axi_aw_valid = bus_buffer_io_lsu_axi_aw_valid; // @[lsu_bus_intf.scala 130:43] assign io_axi_aw_bits_id = bus_buffer_io_lsu_axi_aw_bits_id; // @[lsu_bus_intf.scala 130:43] + assign io_axi_aw_bits_addr = bus_buffer_io_lsu_axi_aw_bits_addr; // @[lsu_bus_intf.scala 130:43] + assign io_axi_aw_bits_size = bus_buffer_io_lsu_axi_aw_bits_size; // @[lsu_bus_intf.scala 130:43] assign io_axi_w_valid = bus_buffer_io_lsu_axi_w_valid; // @[lsu_bus_intf.scala 130:43] assign io_axi_w_bits_data = bus_buffer_io_lsu_axi_w_bits_data; // @[lsu_bus_intf.scala 130:43] + assign io_axi_w_bits_strb = bus_buffer_io_lsu_axi_w_bits_strb; // @[lsu_bus_intf.scala 130:43] assign io_axi_ar_valid = bus_buffer_io_lsu_axi_ar_valid; // @[lsu_bus_intf.scala 130:43] assign io_axi_ar_bits_id = bus_buffer_io_lsu_axi_ar_bits_id; // @[lsu_bus_intf.scala 130:43] + assign io_axi_ar_bits_addr = bus_buffer_io_lsu_axi_ar_bits_addr; // @[lsu_bus_intf.scala 130:43] + assign io_axi_ar_bits_size = bus_buffer_io_lsu_axi_ar_bits_size; // @[lsu_bus_intf.scala 130:43] assign io_lsu_busreq_r = bus_buffer_io_lsu_busreq_r; // @[lsu_bus_intf.scala 133:38] assign io_lsu_bus_buffer_pend_any = bus_buffer_io_lsu_bus_buffer_pend_any; // @[lsu_bus_intf.scala 134:38] assign io_lsu_bus_buffer_full_any = bus_buffer_io_lsu_bus_buffer_full_any; // @[lsu_bus_intf.scala 135:38] @@ -73039,14 +73227,19 @@ module lsu( input io_axi_aw_ready, output io_axi_aw_valid, output [2:0] io_axi_aw_bits_id, + output [31:0] io_axi_aw_bits_addr, + output [2:0] io_axi_aw_bits_size, input io_axi_w_ready, output io_axi_w_valid, output [63:0] io_axi_w_bits_data, + output [7:0] io_axi_w_bits_strb, input io_axi_b_valid, input [2:0] io_axi_b_bits_id, input io_axi_ar_ready, output io_axi_ar_valid, output [2:0] io_axi_ar_bits_id, + output [31:0] io_axi_ar_bits_addr, + output [2:0] io_axi_ar_bits_size, input io_axi_r_valid, input [2:0] io_axi_r_bits_id, input [63:0] io_axi_r_bits_data, @@ -73487,14 +73680,19 @@ module lsu( wire bus_intf_io_axi_aw_ready; // @[lsu.scala 68:30] wire bus_intf_io_axi_aw_valid; // @[lsu.scala 68:30] wire [2:0] bus_intf_io_axi_aw_bits_id; // @[lsu.scala 68:30] + wire [31:0] bus_intf_io_axi_aw_bits_addr; // @[lsu.scala 68:30] + wire [2:0] bus_intf_io_axi_aw_bits_size; // @[lsu.scala 68:30] wire bus_intf_io_axi_w_ready; // @[lsu.scala 68:30] wire bus_intf_io_axi_w_valid; // @[lsu.scala 68:30] wire [63:0] bus_intf_io_axi_w_bits_data; // @[lsu.scala 68:30] + wire [7:0] bus_intf_io_axi_w_bits_strb; // @[lsu.scala 68:30] wire bus_intf_io_axi_b_valid; // @[lsu.scala 68:30] wire [2:0] bus_intf_io_axi_b_bits_id; // @[lsu.scala 68:30] wire bus_intf_io_axi_ar_ready; // @[lsu.scala 68:30] wire bus_intf_io_axi_ar_valid; // @[lsu.scala 68:30] wire [2:0] bus_intf_io_axi_ar_bits_id; // @[lsu.scala 68:30] + wire [31:0] bus_intf_io_axi_ar_bits_addr; // @[lsu.scala 68:30] + wire [2:0] bus_intf_io_axi_ar_bits_size; // @[lsu.scala 68:30] wire bus_intf_io_axi_r_valid; // @[lsu.scala 68:30] wire [2:0] bus_intf_io_axi_r_bits_id; // @[lsu.scala 68:30] wire [63:0] bus_intf_io_axi_r_bits_data; // @[lsu.scala 68:30] @@ -73961,14 +74159,19 @@ module lsu( .io_axi_aw_ready(bus_intf_io_axi_aw_ready), .io_axi_aw_valid(bus_intf_io_axi_aw_valid), .io_axi_aw_bits_id(bus_intf_io_axi_aw_bits_id), + .io_axi_aw_bits_addr(bus_intf_io_axi_aw_bits_addr), + .io_axi_aw_bits_size(bus_intf_io_axi_aw_bits_size), .io_axi_w_ready(bus_intf_io_axi_w_ready), .io_axi_w_valid(bus_intf_io_axi_w_valid), .io_axi_w_bits_data(bus_intf_io_axi_w_bits_data), + .io_axi_w_bits_strb(bus_intf_io_axi_w_bits_strb), .io_axi_b_valid(bus_intf_io_axi_b_valid), .io_axi_b_bits_id(bus_intf_io_axi_b_bits_id), .io_axi_ar_ready(bus_intf_io_axi_ar_ready), .io_axi_ar_valid(bus_intf_io_axi_ar_valid), .io_axi_ar_bits_id(bus_intf_io_axi_ar_bits_id), + .io_axi_ar_bits_addr(bus_intf_io_axi_ar_bits_addr), + .io_axi_ar_bits_size(bus_intf_io_axi_ar_bits_size), .io_axi_r_valid(bus_intf_io_axi_r_valid), .io_axi_r_bits_id(bus_intf_io_axi_r_bits_id), .io_axi_r_bits_data(bus_intf_io_axi_r_bits_data), @@ -74052,10 +74255,15 @@ module lsu( assign io_lsu_tlu_lsu_pmu_store_external_m = _T_50 & lsu_lsc_ctl_io_addr_external_m; // @[lsu.scala 106:39] assign io_axi_aw_valid = bus_intf_io_axi_aw_valid; // @[lsu.scala 314:49] assign io_axi_aw_bits_id = bus_intf_io_axi_aw_bits_id; // @[lsu.scala 314:49] + assign io_axi_aw_bits_addr = bus_intf_io_axi_aw_bits_addr; // @[lsu.scala 314:49] + assign io_axi_aw_bits_size = bus_intf_io_axi_aw_bits_size; // @[lsu.scala 314:49] assign io_axi_w_valid = bus_intf_io_axi_w_valid; // @[lsu.scala 314:49] assign io_axi_w_bits_data = bus_intf_io_axi_w_bits_data; // @[lsu.scala 314:49] + assign io_axi_w_bits_strb = bus_intf_io_axi_w_bits_strb; // @[lsu.scala 314:49] assign io_axi_ar_valid = bus_intf_io_axi_ar_valid; // @[lsu.scala 314:49] assign io_axi_ar_bits_id = bus_intf_io_axi_ar_bits_id; // @[lsu.scala 314:49] + assign io_axi_ar_bits_addr = bus_intf_io_axi_ar_bits_addr; // @[lsu.scala 314:49] + assign io_axi_ar_bits_size = bus_intf_io_axi_ar_bits_size; // @[lsu.scala 314:49] assign io_lsu_result_m = lsu_lsc_ctl_io_lsu_result_m; // @[lsu.scala 61:19] assign io_lsu_result_corr_r = lsu_lsc_ctl_io_lsu_result_corr_r; // @[lsu.scala 62:24] assign io_lsu_load_stall_any = bus_intf_io_lsu_bus_buffer_full_any | dccm_ctl_io_ld_single_ecc_error_r_ff; // @[lsu.scala 75:25] @@ -78072,10 +78280,21 @@ module dma_ctrl( input [2:0] io_iccm_dma_rtag, input [63:0] io_iccm_dma_rdata, input io_iccm_ready, + output io_dma_axi_aw_ready, + input io_dma_axi_aw_valid, + input [31:0] io_dma_axi_aw_bits_addr, + input [2:0] io_dma_axi_aw_bits_size, + output io_dma_axi_w_ready, + input io_dma_axi_w_valid, + input [63:0] io_dma_axi_w_bits_data, + input [7:0] io_dma_axi_w_bits_strb, output io_dma_axi_b_valid, output io_dma_axi_ar_ready, input io_dma_axi_ar_valid, + input [31:0] io_dma_axi_ar_bits_addr, + input [2:0] io_dma_axi_ar_bits_size, output io_dma_axi_r_valid, + output [63:0] io_dma_axi_r_bits_data, output [1:0] io_dma_axi_r_bits_resp, output io_lsu_dma_dma_lsc_ctl_dma_dccm_req, output [31:0] io_lsu_dma_dma_lsc_ctl_dma_mem_addr, @@ -78148,20 +78367,29 @@ module dma_ctrl( reg [31:0] _RAND_46; reg [31:0] _RAND_47; reg [31:0] _RAND_48; - reg [31:0] _RAND_49; + reg [63:0] _RAND_49; reg [31:0] _RAND_50; reg [31:0] _RAND_51; reg [31:0] _RAND_52; reg [31:0] _RAND_53; reg [31:0] _RAND_54; reg [31:0] _RAND_55; - reg [63:0] _RAND_56; - reg [63:0] _RAND_57; - reg [63:0] _RAND_58; - reg [63:0] _RAND_59; - reg [63:0] _RAND_60; + reg [31:0] _RAND_56; + reg [31:0] _RAND_57; + reg [31:0] _RAND_58; + reg [31:0] _RAND_59; + reg [31:0] _RAND_60; reg [31:0] _RAND_61; reg [31:0] _RAND_62; + reg [31:0] _RAND_63; + reg [31:0] _RAND_64; + reg [63:0] _RAND_65; + reg [63:0] _RAND_66; + reg [63:0] _RAND_67; + reg [63:0] _RAND_68; + reg [63:0] _RAND_69; + reg [31:0] _RAND_70; + reg [31:0] _RAND_71; `endif // RANDOMIZE_REG_INIT wire rvclkhdr_io_l1clk; // @[lib.scala 368:23] wire rvclkhdr_io_clk; // @[lib.scala 368:23] @@ -78242,19 +78470,33 @@ module dma_ctrl( wire dma_mem_addr_in_pic = dma_mem_addr_int[31:15] == 17'h1e018; // @[lib.scala 361:39] wire dma_mem_addr_in_iccm = dma_mem_addr_int[31:16] == 16'hee00; // @[lib.scala 361:39] wire dma_bus_clk = dma_bus_cgc_io_l1clk; // @[dma_ctrl.scala 170:25 dma_ctrl.scala 405:28] + reg wrbuf_vld; // @[dma_ctrl.scala 415:59] + reg wrbuf_data_vld; // @[dma_ctrl.scala 417:59] + wire _T_1260 = wrbuf_vld & wrbuf_data_vld; // @[dma_ctrl.scala 473:43] reg rdbuf_vld; // @[dma_ctrl.scala 441:47] + wire _T_1261 = _T_1260 & rdbuf_vld; // @[dma_ctrl.scala 473:60] + reg axi_mstr_priority; // @[Reg.scala 27:20] + wire axi_mstr_sel = _T_1261 ? axi_mstr_priority : _T_1260; // @[dma_ctrl.scala 473:31] + reg [31:0] wrbuf_addr; // @[lib.scala 374:16] + reg [31:0] rdbuf_addr; // @[lib.scala 374:16] + wire [31:0] bus_cmd_addr = axi_mstr_sel ? wrbuf_addr : rdbuf_addr; // @[dma_ctrl.scala 463:43] wire [2:0] _GEN_90 = {{2'd0}, io_dbg_dma_dbg_ib_dbg_cmd_addr[2]}; // @[dma_ctrl.scala 195:91] wire [3:0] _T_17 = 3'h4 * _GEN_90; // @[dma_ctrl.scala 195:91] wire [18:0] _T_18 = 19'hf << _T_17; // @[dma_ctrl.scala 195:83] - wire [18:0] _T_20 = io_dbg_dma_dbg_ib_dbg_cmd_valid ? _T_18 : 19'h0; // @[dma_ctrl.scala 195:34] + reg [7:0] wrbuf_byteen; // @[Reg.scala 27:20] + wire [18:0] _T_20 = io_dbg_dma_dbg_ib_dbg_cmd_valid ? _T_18 : {{11'd0}, wrbuf_byteen}; // @[dma_ctrl.scala 195:34] wire [2:0] _T_23 = {1'h0,io_dbg_cmd_size}; // @[Cat.scala 29:58] - wire [2:0] fifo_sz_in = io_dbg_dma_dbg_ib_dbg_cmd_valid ? _T_23 : 3'h0; // @[dma_ctrl.scala 197:33] - wire fifo_write_in = io_dbg_dma_dbg_ib_dbg_cmd_valid & io_dbg_dma_dbg_ib_dbg_cmd_write; // @[dma_ctrl.scala 199:33] + reg [2:0] wrbuf_sz; // @[Reg.scala 27:20] + reg [2:0] rdbuf_sz; // @[Reg.scala 27:20] + wire [2:0] bus_cmd_sz = axi_mstr_sel ? wrbuf_sz : rdbuf_sz; // @[dma_ctrl.scala 464:45] + wire [2:0] fifo_sz_in = io_dbg_dma_dbg_ib_dbg_cmd_valid ? _T_23 : bus_cmd_sz; // @[dma_ctrl.scala 197:33] + wire fifo_write_in = io_dbg_dma_dbg_ib_dbg_cmd_valid ? io_dbg_dma_dbg_ib_dbg_cmd_write : axi_mstr_sel; // @[dma_ctrl.scala 199:33] + wire bus_cmd_valid = _T_1260 | rdbuf_vld; // @[dma_ctrl.scala 459:69] reg fifo_full; // @[dma_ctrl.scala 373:12] reg dbg_dma_bubble_bus; // @[dma_ctrl.scala 377:12] wire _T_989 = fifo_full | dbg_dma_bubble_bus; // @[dma_ctrl.scala 299:39] wire dma_fifo_ready = ~_T_989; // @[dma_ctrl.scala 299:27] - wire axi_mstr_prty_en = rdbuf_vld & dma_fifo_ready; // @[dma_ctrl.scala 460:54] + wire axi_mstr_prty_en = bus_cmd_valid & dma_fifo_ready; // @[dma_ctrl.scala 460:54] wire _T_28 = axi_mstr_prty_en & io_dma_bus_clk_en; // @[dma_ctrl.scala 206:80] wire _T_31 = io_dbg_dma_dbg_ib_dbg_cmd_valid & io_dbg_dma_dbg_ib_dbg_cmd_type[1]; // @[dma_ctrl.scala 206:136] wire _T_32 = _T_28 | _T_31; // @[dma_ctrl.scala 206:101] @@ -78562,7 +78804,8 @@ module dma_ctrl( wire _T_491 = fifo_error_en[0] & _T_269; // @[dma_ctrl.scala 224:77] wire [63:0] _T_493 = {32'h0,fifo_addr_0}; // @[Cat.scala 29:58] wire [63:0] _T_498 = {io_dbg_dma_dbg_dctl_dbg_cmd_wrdata,io_dbg_dma_dbg_dctl_dbg_cmd_wrdata}; // @[Cat.scala 29:58] - wire [63:0] _T_500 = io_dbg_dma_dbg_ib_dbg_cmd_valid ? _T_498 : 64'h0; // @[dma_ctrl.scala 224:347] + reg [63:0] wrbuf_data; // @[lib.scala 374:16] + wire [63:0] _T_500 = io_dbg_dma_dbg_ib_dbg_cmd_valid ? _T_498 : wrbuf_data; // @[dma_ctrl.scala 224:347] wire _T_506 = fifo_error_en[1] & _T_276; // @[dma_ctrl.scala 224:77] wire [63:0] _T_508 = {32'h0,fifo_addr_1}; // @[Cat.scala 29:58] wire _T_521 = fifo_error_en[2] & _T_283; // @[dma_ctrl.scala 224:77] @@ -78689,20 +78932,37 @@ module dma_ctrl( wire [63:0] _GEN_76 = 3'h2 == RdPtr ? fifo_data_2 : _GEN_75; // @[dma_ctrl.scala 361:40] wire [63:0] _GEN_77 = 3'h3 == RdPtr ? fifo_data_3 : _GEN_76; // @[dma_ctrl.scala 361:40] reg dma_dbg_cmd_done_q; // @[dma_ctrl.scala 381:12] - wire _T_1212 = rdbuf_vld & io_dma_bus_clk_en; // @[dma_ctrl.scala 386:44] + wire _T_1212 = bus_cmd_valid & io_dma_bus_clk_en; // @[dma_ctrl.scala 386:44] wire _T_1213 = _T_1212 | io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[dma_ctrl.scala 386:65] - wire _T_1214 = rdbuf_vld | bus_rsp_sent; // @[dma_ctrl.scala 387:44] + wire _T_1214 = bus_cmd_valid | bus_rsp_sent; // @[dma_ctrl.scala 387:44] wire _T_1215 = _T_1214 | io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[dma_ctrl.scala 387:60] wire _T_1216 = _T_1215 | io_dma_dbg_cmd_done; // @[dma_ctrl.scala 387:94] wire _T_1217 = _T_1216 | dma_dbg_cmd_done_q; // @[dma_ctrl.scala 387:116] wire _T_1219 = _T_1217 | _T_1143; // @[dma_ctrl.scala 387:137] + wire wrbuf_en = io_dma_axi_aw_valid & io_dma_axi_aw_ready; // @[dma_ctrl.scala 409:47] + wire wrbuf_data_en = io_dma_axi_w_valid & io_dma_axi_w_ready; // @[dma_ctrl.scala 410:46] + wire wrbuf_cmd_sent = axi_mstr_prty_en & axi_mstr_sel; // @[dma_ctrl.scala 411:40] + wire _T_1221 = ~wrbuf_en; // @[dma_ctrl.scala 412:51] + wire wrbuf_rst = wrbuf_cmd_sent & _T_1221; // @[dma_ctrl.scala 412:49] + wire _T_1223 = ~wrbuf_data_en; // @[dma_ctrl.scala 413:51] + wire wrbuf_data_rst = wrbuf_cmd_sent & _T_1223; // @[dma_ctrl.scala 413:49] + wire _T_1224 = wrbuf_en | wrbuf_vld; // @[dma_ctrl.scala 415:63] + wire _T_1225 = ~wrbuf_rst; // @[dma_ctrl.scala 415:92] + wire _T_1228 = wrbuf_data_en | wrbuf_data_vld; // @[dma_ctrl.scala 417:63] + wire _T_1229 = ~wrbuf_data_rst; // @[dma_ctrl.scala 417:102] wire rdbuf_en = io_dma_axi_ar_valid & io_dma_axi_ar_ready; // @[dma_ctrl.scala 437:59] + wire _T_1234 = ~axi_mstr_sel; // @[dma_ctrl.scala 438:44] + wire rdbuf_cmd_sent = axi_mstr_prty_en & _T_1234; // @[dma_ctrl.scala 438:42] wire _T_1236 = ~rdbuf_en; // @[dma_ctrl.scala 439:63] - wire rdbuf_rst = axi_mstr_prty_en & _T_1236; // @[dma_ctrl.scala 439:61] + wire rdbuf_rst = rdbuf_cmd_sent & _T_1236; // @[dma_ctrl.scala 439:61] wire _T_1237 = rdbuf_en | rdbuf_vld; // @[dma_ctrl.scala 441:51] wire _T_1238 = ~rdbuf_rst; // @[dma_ctrl.scala 441:80] - wire _T_1248 = ~axi_mstr_prty_en; // @[dma_ctrl.scala 455:44] + wire _T_1242 = ~wrbuf_cmd_sent; // @[dma_ctrl.scala 453:44] + wire _T_1243 = wrbuf_vld & _T_1242; // @[dma_ctrl.scala 453:42] + wire _T_1246 = wrbuf_data_vld & _T_1242; // @[dma_ctrl.scala 454:47] + wire _T_1248 = ~rdbuf_cmd_sent; // @[dma_ctrl.scala 455:44] wire _T_1249 = rdbuf_vld & _T_1248; // @[dma_ctrl.scala 455:42] + wire axi_mstr_prty_in = ~axi_mstr_priority; // @[dma_ctrl.scala 474:27] wire _T_1271 = ~_T_1108[0]; // @[dma_ctrl.scala 481:50] wire _T_1272 = _T_1106[0] & _T_1271; // @[dma_ctrl.scala 481:48] wire [4:0] _T_1273 = fifo_done_bus >> RspPtr; // @[dma_ctrl.scala 481:83] @@ -78818,9 +79078,12 @@ module dma_ctrl( assign io_dec_dma_tlu_dma_dma_pmu_any_write = _T_165 & io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[dma_ctrl.scala 368:42] assign io_dec_dma_tlu_dma_dma_dccm_stall_any = _T_1137 & _T_1138; // @[dma_ctrl.scala 332:41] assign io_dec_dma_tlu_dma_dma_iccm_stall_any = io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[dma_ctrl.scala 334:41] + assign io_dma_axi_aw_ready = ~_T_1243; // @[dma_ctrl.scala 453:27] + assign io_dma_axi_w_ready = ~_T_1246; // @[dma_ctrl.scala 454:27] assign io_dma_axi_b_valid = axi_rsp_valid & axi_rsp_write; // @[dma_ctrl.scala 490:27] assign io_dma_axi_ar_ready = ~_T_1249; // @[dma_ctrl.scala 455:27] assign io_dma_axi_r_valid = axi_rsp_valid & _T_1281; // @[dma_ctrl.scala 494:27] + assign io_dma_axi_r_bits_data = 3'h4 == RspPtr ? fifo_data_4 : _GEN_51; // @[dma_ctrl.scala 496:43] assign io_dma_axi_r_bits_resp = _GEN_57[0] ? 2'h2 : _T_1278; // @[dma_ctrl.scala 495:41] assign io_lsu_dma_dma_lsc_ctl_dma_dccm_req = _T_1137 & io_lsu_dma_dccm_ready; // @[dma_ctrl.scala 352:40] assign io_lsu_dma_dma_lsc_ctl_dma_mem_addr = _T_1184 ? _T_1188 : dma_mem_addr_int; // @[dma_ctrl.scala 357:40] @@ -78877,10 +79140,10 @@ module dma_ctrl( assign dma_bus_cgc_io_en = io_dma_bus_clk_en; // @[dma_ctrl.scala 402:28] assign dma_bus_cgc_io_scan_mode = io_scan_mode; // @[dma_ctrl.scala 403:28] assign rvclkhdr_10_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_10_io_en = 1'h0; // @[lib.scala 371:17] + assign rvclkhdr_10_io_en = wrbuf_en & io_dma_bus_clk_en; // @[lib.scala 371:17] assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_11_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_11_io_en = 1'h0; // @[lib.scala 371:17] + assign rvclkhdr_11_io_en = wrbuf_data_en & io_dma_bus_clk_en; // @[lib.scala 371:17] assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_12_io_clk = clock; // @[lib.scala 370:18] assign rvclkhdr_12_io_en = rdbuf_en & io_dma_bus_clk_en; // @[lib.scala 371:17] @@ -78933,119 +79196,137 @@ initial begin _RAND_5 = {1{`RANDOM}}; fifo_addr_0 = _RAND_5[31:0]; _RAND_6 = {1{`RANDOM}}; - rdbuf_vld = _RAND_6[0:0]; + wrbuf_vld = _RAND_6[0:0]; _RAND_7 = {1{`RANDOM}}; - fifo_full = _RAND_7[0:0]; + wrbuf_data_vld = _RAND_7[0:0]; _RAND_8 = {1{`RANDOM}}; - dbg_dma_bubble_bus = _RAND_8[0:0]; + rdbuf_vld = _RAND_8[0:0]; _RAND_9 = {1{`RANDOM}}; - WrPtr = _RAND_9[2:0]; + axi_mstr_priority = _RAND_9[0:0]; _RAND_10 = {1{`RANDOM}}; - _T_598 = _RAND_10[0:0]; + wrbuf_addr = _RAND_10[31:0]; _RAND_11 = {1{`RANDOM}}; - _T_591 = _RAND_11[0:0]; + rdbuf_addr = _RAND_11[31:0]; _RAND_12 = {1{`RANDOM}}; - _T_584 = _RAND_12[0:0]; + wrbuf_byteen = _RAND_12[7:0]; _RAND_13 = {1{`RANDOM}}; - _T_577 = _RAND_13[0:0]; + wrbuf_sz = _RAND_13[2:0]; _RAND_14 = {1{`RANDOM}}; - _T_570 = _RAND_14[0:0]; + rdbuf_sz = _RAND_14[2:0]; _RAND_15 = {1{`RANDOM}}; - _T_760 = _RAND_15[0:0]; + fifo_full = _RAND_15[0:0]; _RAND_16 = {1{`RANDOM}}; - _T_753 = _RAND_16[0:0]; + dbg_dma_bubble_bus = _RAND_16[0:0]; _RAND_17 = {1{`RANDOM}}; - _T_746 = _RAND_17[0:0]; + WrPtr = _RAND_17[2:0]; _RAND_18 = {1{`RANDOM}}; - _T_739 = _RAND_18[0:0]; + _T_598 = _RAND_18[0:0]; _RAND_19 = {1{`RANDOM}}; - _T_732 = _RAND_19[0:0]; + _T_591 = _RAND_19[0:0]; _RAND_20 = {1{`RANDOM}}; - _T_886 = _RAND_20[0:0]; + _T_584 = _RAND_20[0:0]; _RAND_21 = {1{`RANDOM}}; - _T_884 = _RAND_21[0:0]; + _T_577 = _RAND_21[0:0]; _RAND_22 = {1{`RANDOM}}; - _T_882 = _RAND_22[0:0]; + _T_570 = _RAND_22[0:0]; _RAND_23 = {1{`RANDOM}}; - _T_880 = _RAND_23[0:0]; + _T_760 = _RAND_23[0:0]; _RAND_24 = {1{`RANDOM}}; - _T_878 = _RAND_24[0:0]; + _T_753 = _RAND_24[0:0]; _RAND_25 = {1{`RANDOM}}; - fifo_sz_4 = _RAND_25[2:0]; + _T_746 = _RAND_25[0:0]; _RAND_26 = {1{`RANDOM}}; - fifo_sz_3 = _RAND_26[2:0]; + _T_739 = _RAND_26[0:0]; _RAND_27 = {1{`RANDOM}}; - fifo_sz_2 = _RAND_27[2:0]; + _T_732 = _RAND_27[0:0]; _RAND_28 = {1{`RANDOM}}; - fifo_sz_1 = _RAND_28[2:0]; + _T_886 = _RAND_28[0:0]; _RAND_29 = {1{`RANDOM}}; - fifo_sz_0 = _RAND_29[2:0]; + _T_884 = _RAND_29[0:0]; _RAND_30 = {1{`RANDOM}}; - fifo_byteen_4 = _RAND_30[7:0]; + _T_882 = _RAND_30[0:0]; _RAND_31 = {1{`RANDOM}}; - fifo_byteen_3 = _RAND_31[7:0]; + _T_880 = _RAND_31[0:0]; _RAND_32 = {1{`RANDOM}}; - fifo_byteen_2 = _RAND_32[7:0]; + _T_878 = _RAND_32[0:0]; _RAND_33 = {1{`RANDOM}}; - fifo_byteen_1 = _RAND_33[7:0]; + fifo_sz_4 = _RAND_33[2:0]; _RAND_34 = {1{`RANDOM}}; - fifo_byteen_0 = _RAND_34[7:0]; + fifo_sz_3 = _RAND_34[2:0]; _RAND_35 = {1{`RANDOM}}; - fifo_error_0 = _RAND_35[1:0]; + fifo_sz_2 = _RAND_35[2:0]; _RAND_36 = {1{`RANDOM}}; - fifo_error_1 = _RAND_36[1:0]; + fifo_sz_1 = _RAND_36[2:0]; _RAND_37 = {1{`RANDOM}}; - fifo_error_2 = _RAND_37[1:0]; + fifo_sz_0 = _RAND_37[2:0]; _RAND_38 = {1{`RANDOM}}; - fifo_error_3 = _RAND_38[1:0]; + fifo_byteen_4 = _RAND_38[7:0]; _RAND_39 = {1{`RANDOM}}; - fifo_error_4 = _RAND_39[1:0]; + fifo_byteen_3 = _RAND_39[7:0]; _RAND_40 = {1{`RANDOM}}; - RspPtr = _RAND_40[2:0]; + fifo_byteen_2 = _RAND_40[7:0]; _RAND_41 = {1{`RANDOM}}; - _T_721 = _RAND_41[0:0]; + fifo_byteen_1 = _RAND_41[7:0]; _RAND_42 = {1{`RANDOM}}; - _T_714 = _RAND_42[0:0]; + fifo_byteen_0 = _RAND_42[7:0]; _RAND_43 = {1{`RANDOM}}; - _T_707 = _RAND_43[0:0]; + fifo_error_0 = _RAND_43[1:0]; _RAND_44 = {1{`RANDOM}}; - _T_700 = _RAND_44[0:0]; + fifo_error_1 = _RAND_44[1:0]; _RAND_45 = {1{`RANDOM}}; - _T_693 = _RAND_45[0:0]; + fifo_error_2 = _RAND_45[1:0]; _RAND_46 = {1{`RANDOM}}; - _T_799 = _RAND_46[0:0]; + fifo_error_3 = _RAND_46[1:0]; _RAND_47 = {1{`RANDOM}}; - _T_792 = _RAND_47[0:0]; + fifo_error_4 = _RAND_47[1:0]; _RAND_48 = {1{`RANDOM}}; - _T_785 = _RAND_48[0:0]; - _RAND_49 = {1{`RANDOM}}; - _T_778 = _RAND_49[0:0]; + RspPtr = _RAND_48[2:0]; + _RAND_49 = {2{`RANDOM}}; + wrbuf_data = _RAND_49[63:0]; _RAND_50 = {1{`RANDOM}}; - _T_771 = _RAND_50[0:0]; + _T_721 = _RAND_50[0:0]; _RAND_51 = {1{`RANDOM}}; - _T_850 = _RAND_51[0:0]; + _T_714 = _RAND_51[0:0]; _RAND_52 = {1{`RANDOM}}; - _T_852 = _RAND_52[0:0]; + _T_707 = _RAND_52[0:0]; _RAND_53 = {1{`RANDOM}}; - _T_854 = _RAND_53[0:0]; + _T_700 = _RAND_53[0:0]; _RAND_54 = {1{`RANDOM}}; - _T_856 = _RAND_54[0:0]; + _T_693 = _RAND_54[0:0]; _RAND_55 = {1{`RANDOM}}; - _T_858 = _RAND_55[0:0]; - _RAND_56 = {2{`RANDOM}}; - fifo_data_0 = _RAND_56[63:0]; - _RAND_57 = {2{`RANDOM}}; - fifo_data_1 = _RAND_57[63:0]; - _RAND_58 = {2{`RANDOM}}; - fifo_data_2 = _RAND_58[63:0]; - _RAND_59 = {2{`RANDOM}}; - fifo_data_3 = _RAND_59[63:0]; - _RAND_60 = {2{`RANDOM}}; - fifo_data_4 = _RAND_60[63:0]; + _T_799 = _RAND_55[0:0]; + _RAND_56 = {1{`RANDOM}}; + _T_792 = _RAND_56[0:0]; + _RAND_57 = {1{`RANDOM}}; + _T_785 = _RAND_57[0:0]; + _RAND_58 = {1{`RANDOM}}; + _T_778 = _RAND_58[0:0]; + _RAND_59 = {1{`RANDOM}}; + _T_771 = _RAND_59[0:0]; + _RAND_60 = {1{`RANDOM}}; + _T_850 = _RAND_60[0:0]; _RAND_61 = {1{`RANDOM}}; - dma_nack_count = _RAND_61[2:0]; + _T_852 = _RAND_61[0:0]; _RAND_62 = {1{`RANDOM}}; - dma_dbg_cmd_done_q = _RAND_62[0:0]; + _T_854 = _RAND_62[0:0]; + _RAND_63 = {1{`RANDOM}}; + _T_856 = _RAND_63[0:0]; + _RAND_64 = {1{`RANDOM}}; + _T_858 = _RAND_64[0:0]; + _RAND_65 = {2{`RANDOM}}; + fifo_data_0 = _RAND_65[63:0]; + _RAND_66 = {2{`RANDOM}}; + fifo_data_1 = _RAND_66[63:0]; + _RAND_67 = {2{`RANDOM}}; + fifo_data_2 = _RAND_67[63:0]; + _RAND_68 = {2{`RANDOM}}; + fifo_data_3 = _RAND_68[63:0]; + _RAND_69 = {2{`RANDOM}}; + fifo_data_4 = _RAND_69[63:0]; + _RAND_70 = {1{`RANDOM}}; + dma_nack_count = _RAND_70[2:0]; + _RAND_71 = {1{`RANDOM}}; + dma_dbg_cmd_done_q = _RAND_71[0:0]; `endif // RANDOMIZE_REG_INIT if (reset) begin RdPtr = 3'h0; @@ -79065,9 +79346,33 @@ initial begin if (reset) begin fifo_addr_0 = 32'h0; end + if (reset) begin + wrbuf_vld = 1'h0; + end + if (reset) begin + wrbuf_data_vld = 1'h0; + end if (reset) begin rdbuf_vld = 1'h0; end + if (reset) begin + axi_mstr_priority = 1'h0; + end + if (reset) begin + wrbuf_addr = 32'h0; + end + if (reset) begin + rdbuf_addr = 32'h0; + end + if (reset) begin + wrbuf_byteen = 8'h0; + end + if (reset) begin + wrbuf_sz = 3'h0; + end + if (reset) begin + rdbuf_sz = 3'h0; + end if (reset) begin fifo_full = 1'h0; end @@ -79170,6 +79475,9 @@ initial begin if (reset) begin RspPtr = 3'h0; end + if (reset) begin + wrbuf_data = 64'h0; + end if (reset) begin _T_721 = 1'h0; end @@ -79258,8 +79566,10 @@ end // initial fifo_addr_4 <= 32'h0; end else if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin fifo_addr_4 <= io_dbg_dma_dbg_ib_dbg_cmd_addr; + end else if (axi_mstr_sel) begin + fifo_addr_4 <= wrbuf_addr; end else begin - fifo_addr_4 <= 32'h0; + fifo_addr_4 <= rdbuf_addr; end end always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin @@ -79267,8 +79577,10 @@ end // initial fifo_addr_3 <= 32'h0; end else if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin fifo_addr_3 <= io_dbg_dma_dbg_ib_dbg_cmd_addr; + end else if (axi_mstr_sel) begin + fifo_addr_3 <= wrbuf_addr; end else begin - fifo_addr_3 <= 32'h0; + fifo_addr_3 <= rdbuf_addr; end end always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin @@ -79276,8 +79588,10 @@ end // initial fifo_addr_2 <= 32'h0; end else if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin fifo_addr_2 <= io_dbg_dma_dbg_ib_dbg_cmd_addr; + end else if (axi_mstr_sel) begin + fifo_addr_2 <= wrbuf_addr; end else begin - fifo_addr_2 <= 32'h0; + fifo_addr_2 <= rdbuf_addr; end end always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin @@ -79285,8 +79599,10 @@ end // initial fifo_addr_1 <= 32'h0; end else if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin fifo_addr_1 <= io_dbg_dma_dbg_ib_dbg_cmd_addr; + end else if (axi_mstr_sel) begin + fifo_addr_1 <= wrbuf_addr; end else begin - fifo_addr_1 <= 32'h0; + fifo_addr_1 <= rdbuf_addr; end end always @(posedge rvclkhdr_io_l1clk or posedge reset) begin @@ -79295,7 +79611,21 @@ end // initial end else if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin fifo_addr_0 <= io_dbg_dma_dbg_ib_dbg_cmd_addr; end else begin - fifo_addr_0 <= 32'h0; + fifo_addr_0 <= bus_cmd_addr; + end + end + always @(posedge dma_bus_clk or posedge reset) begin + if (reset) begin + wrbuf_vld <= 1'h0; + end else begin + wrbuf_vld <= _T_1224 & _T_1225; + end + end + always @(posedge dma_bus_clk or posedge reset) begin + if (reset) begin + wrbuf_data_vld <= 1'h0; + end else begin + wrbuf_data_vld <= _T_1228 & _T_1229; end end always @(posedge dma_bus_clk or posedge reset) begin @@ -79305,6 +79635,48 @@ end // initial rdbuf_vld <= _T_1237 & _T_1238; end end + always @(posedge dma_bus_clk or posedge reset) begin + if (reset) begin + axi_mstr_priority <= 1'h0; + end else if (axi_mstr_prty_en) begin + axi_mstr_priority <= axi_mstr_prty_in; + end + end + always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin + if (reset) begin + wrbuf_addr <= 32'h0; + end else begin + wrbuf_addr <= io_dma_axi_aw_bits_addr; + end + end + always @(posedge rvclkhdr_12_io_l1clk or posedge reset) begin + if (reset) begin + rdbuf_addr <= 32'h0; + end else begin + rdbuf_addr <= io_dma_axi_ar_bits_addr; + end + end + always @(posedge dma_bus_clk or posedge reset) begin + if (reset) begin + wrbuf_byteen <= 8'h0; + end else if (wrbuf_data_en) begin + wrbuf_byteen <= io_dma_axi_w_bits_strb; + end + end + always @(posedge dma_bus_clk or posedge reset) begin + if (reset) begin + wrbuf_sz <= 3'h0; + end else if (wrbuf_en) begin + wrbuf_sz <= io_dma_axi_aw_bits_size; + end + end + always @(posedge dma_bus_clk or posedge reset) begin + if (reset) begin + rdbuf_sz <= 3'h0; + end else if (rdbuf_en) begin + rdbuf_sz <= io_dma_axi_ar_bits_size; + end + end always @(posedge dma_bus_clk or posedge reset) begin if (reset) begin fifo_full <= 1'h0; @@ -79441,8 +79813,10 @@ end // initial end else if (fifo_cmd_en[4]) begin if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin fifo_sz_4 <= _T_23; + end else if (axi_mstr_sel) begin + fifo_sz_4 <= wrbuf_sz; end else begin - fifo_sz_4 <= 3'h0; + fifo_sz_4 <= rdbuf_sz; end end end @@ -79452,8 +79826,10 @@ end // initial end else if (fifo_cmd_en[3]) begin if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin fifo_sz_3 <= _T_23; + end else if (axi_mstr_sel) begin + fifo_sz_3 <= wrbuf_sz; end else begin - fifo_sz_3 <= 3'h0; + fifo_sz_3 <= rdbuf_sz; end end end @@ -79463,8 +79839,10 @@ end // initial end else if (fifo_cmd_en[2]) begin if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin fifo_sz_2 <= _T_23; + end else if (axi_mstr_sel) begin + fifo_sz_2 <= wrbuf_sz; end else begin - fifo_sz_2 <= 3'h0; + fifo_sz_2 <= rdbuf_sz; end end end @@ -79474,8 +79852,10 @@ end // initial end else if (fifo_cmd_en[1]) begin if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin fifo_sz_1 <= _T_23; + end else if (axi_mstr_sel) begin + fifo_sz_1 <= wrbuf_sz; end else begin - fifo_sz_1 <= 3'h0; + fifo_sz_1 <= rdbuf_sz; end end end @@ -79567,6 +79947,13 @@ end // initial end end end + always @(posedge rvclkhdr_11_io_l1clk or posedge reset) begin + if (reset) begin + wrbuf_data <= 64'h0; + end else begin + wrbuf_data <= io_dma_axi_w_bits_data; + end + end always @(posedge dma_free_clk or posedge reset) begin if (reset) begin _T_721 <= 1'h0; @@ -79641,28 +80028,52 @@ end // initial if (reset) begin _T_850 <= 1'h0; end else if (fifo_cmd_en[0]) begin - _T_850 <= fifo_write_in; + if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin + _T_850 <= io_dbg_dma_dbg_ib_dbg_cmd_write; + end else if (_T_1261) begin + _T_850 <= axi_mstr_priority; + end else begin + _T_850 <= _T_1260; + end end end always @(posedge dma_buffer_c1_clk or posedge reset) begin if (reset) begin _T_852 <= 1'h0; end else if (fifo_cmd_en[1]) begin - _T_852 <= fifo_write_in; + if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin + _T_852 <= io_dbg_dma_dbg_ib_dbg_cmd_write; + end else if (_T_1261) begin + _T_852 <= axi_mstr_priority; + end else begin + _T_852 <= _T_1260; + end end end always @(posedge dma_buffer_c1_clk or posedge reset) begin if (reset) begin _T_854 <= 1'h0; end else if (fifo_cmd_en[2]) begin - _T_854 <= fifo_write_in; + if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin + _T_854 <= io_dbg_dma_dbg_ib_dbg_cmd_write; + end else if (_T_1261) begin + _T_854 <= axi_mstr_priority; + end else begin + _T_854 <= _T_1260; + end end end always @(posedge dma_buffer_c1_clk or posedge reset) begin if (reset) begin _T_856 <= 1'h0; end else if (fifo_cmd_en[3]) begin - _T_856 <= fifo_write_in; + if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin + _T_856 <= io_dbg_dma_dbg_ib_dbg_cmd_write; + end else if (_T_1261) begin + _T_856 <= axi_mstr_priority; + end else begin + _T_856 <= _T_1260; + end end end always @(posedge dma_buffer_c1_clk or posedge reset) begin @@ -79684,7 +80095,7 @@ end // initial end else if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin fifo_data_0 <= _T_498; end else begin - fifo_data_0 <= 64'h0; + fifo_data_0 <= wrbuf_data; end end always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin @@ -79699,7 +80110,7 @@ end // initial end else if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin fifo_data_1 <= _T_498; end else begin - fifo_data_1 <= 64'h0; + fifo_data_1 <= wrbuf_data; end end always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin @@ -79714,7 +80125,7 @@ end // initial end else if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin fifo_data_2 <= _T_498; end else begin - fifo_data_2 <= 64'h0; + fifo_data_2 <= wrbuf_data; end end always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin @@ -79729,7 +80140,7 @@ end // initial end else if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin fifo_data_3 <= _T_498; end else begin - fifo_data_3 <= 64'h0; + fifo_data_3 <= wrbuf_data; end end always @(posedge rvclkhdr_9_io_l1clk or posedge reset) begin @@ -79774,33 +80185,54 @@ module axi4_to_ahb( input io_clk_override, output io_axi_aw_ready, input io_axi_aw_valid, - input io_axi_aw_bits_id, + input [31:0] io_axi_aw_bits_addr, + input [2:0] io_axi_aw_bits_size, output io_axi_w_ready, input io_axi_w_valid, input [63:0] io_axi_w_bits_data, - input io_axi_b_ready, + input [7:0] io_axi_w_bits_strb, output io_axi_b_valid, output [1:0] io_axi_b_bits_resp, - output io_axi_b_bits_id, output io_axi_ar_ready, input io_axi_ar_valid, - input io_axi_ar_bits_id, + input [31:0] io_axi_ar_bits_addr, + input [2:0] io_axi_ar_bits_size, output io_axi_r_valid, - output io_axi_r_bits_id, output [63:0] io_axi_r_bits_data, - output [1:0] io_axi_r_bits_resp + output [1:0] io_axi_r_bits_resp, + input [63:0] io_ahb_in_hrdata, + input io_ahb_in_hready, + input io_ahb_in_hresp, + output [31:0] io_ahb_out_haddr, + output [2:0] io_ahb_out_hsize, + output [1:0] io_ahb_out_htrans, + output io_ahb_out_hwrite, + output [63:0] io_ahb_out_hwdata ); `ifdef RANDOMIZE_REG_INIT reg [31:0] _RAND_0; reg [31:0] _RAND_1; reg [31:0] _RAND_2; reg [31:0] _RAND_3; - reg [63:0] _RAND_4; + reg [31:0] _RAND_4; reg [31:0] _RAND_5; reg [31:0] _RAND_6; - reg [63:0] _RAND_7; + reg [31:0] _RAND_7; reg [31:0] _RAND_8; reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [63:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; + reg [63:0] _RAND_15; + reg [63:0] _RAND_16; + reg [31:0] _RAND_17; + reg [31:0] _RAND_18; + reg [31:0] _RAND_19; + reg [31:0] _RAND_20; + reg [31:0] _RAND_21; + reg [31:0] _RAND_22; `endif // RANDOMIZE_REG_INIT wire rvclkhdr_io_l1clk; // @[lib.scala 343:22] wire rvclkhdr_io_clk; // @[lib.scala 343:22] @@ -79842,32 +80274,53 @@ module axi4_to_ahb( wire rvclkhdr_9_io_clk; // @[lib.scala 343:22] wire rvclkhdr_9_io_en; // @[lib.scala 343:22] wire rvclkhdr_9_io_scan_mode; // @[lib.scala 343:22] - wire ahbm_clk = rvclkhdr_7_io_l1clk; // @[axi4_to_ahb.scala 31:22 axi4_to_ahb.scala 340:12] - reg [2:0] buf_state; // @[axi4_to_ahb.scala 37:45] + wire ahbm_clk = rvclkhdr_7_io_l1clk; // @[axi4_to_ahb.scala 24:22 axi4_to_ahb.scala 333:12] + reg [2:0] buf_state; // @[axi4_to_ahb.scala 30:45] wire _T_49 = 3'h0 == buf_state; // @[Conditional.scala 37:30] - wire bus_clk = rvclkhdr_io_l1clk; // @[axi4_to_ahb.scala 57:21 axi4_to_ahb.scala 169:11] - reg wrbuf_vld; // @[axi4_to_ahb.scala 308:51] - reg wrbuf_data_vld; // @[axi4_to_ahb.scala 309:51] - wire wr_cmd_vld = wrbuf_vld & wrbuf_data_vld; // @[axi4_to_ahb.scala 146:27] - wire master_valid = wr_cmd_vld | io_axi_ar_valid; // @[axi4_to_ahb.scala 147:30] + wire bus_clk = rvclkhdr_io_l1clk; // @[axi4_to_ahb.scala 50:21 axi4_to_ahb.scala 162:11] + reg wrbuf_vld; // @[axi4_to_ahb.scala 301:51] + reg wrbuf_data_vld; // @[axi4_to_ahb.scala 302:51] + wire wr_cmd_vld = wrbuf_vld & wrbuf_data_vld; // @[axi4_to_ahb.scala 139:27] + wire master_valid = wr_cmd_vld | io_axi_ar_valid; // @[axi4_to_ahb.scala 140:30] wire _T_101 = 3'h1 == buf_state; // @[Conditional.scala 37:30] + reg ahb_hready_q; // @[axi4_to_ahb.scala 321:52] + reg [1:0] ahb_htrans_q; // @[axi4_to_ahb.scala 322:52] + wire _T_108 = ahb_htrans_q != 2'h0; // @[axi4_to_ahb.scala 183:58] + wire _T_109 = ahb_hready_q & _T_108; // @[axi4_to_ahb.scala 183:36] + wire ahbm_addr_clk = rvclkhdr_8_io_l1clk; // @[axi4_to_ahb.scala 25:27 axi4_to_ahb.scala 334:17] + reg ahb_hwrite_q; // @[axi4_to_ahb.scala 323:57] + wire _T_110 = ~ahb_hwrite_q; // @[axi4_to_ahb.scala 183:72] + wire _T_111 = _T_109 & _T_110; // @[axi4_to_ahb.scala 183:70] wire _T_136 = 3'h6 == buf_state; // @[Conditional.scala 37:30] + reg ahb_hresp_q; // @[axi4_to_ahb.scala 324:52] + wire _T_156 = ahb_hready_q | ahb_hresp_q; // @[axi4_to_ahb.scala 197:37] wire _T_175 = 3'h7 == buf_state; // @[Conditional.scala 37:30] wire _T_186 = 3'h3 == buf_state; // @[Conditional.scala 37:30] wire _T_188 = 3'h2 == buf_state; // @[Conditional.scala 37:30] + wire _T_189 = ahb_hready_q & ahb_hwrite_q; // @[axi4_to_ahb.scala 229:33] + wire _T_192 = _T_189 & _T_108; // @[axi4_to_ahb.scala 229:48] wire _T_281 = 3'h4 == buf_state; // @[Conditional.scala 37:30] + wire _GEN_15 = _T_281 & _T_192; // @[Conditional.scala 39:67] + wire _GEN_19 = _T_188 ? _T_192 : _GEN_15; // @[Conditional.scala 39:67] + wire _GEN_40 = _T_186 ? 1'h0 : _GEN_19; // @[Conditional.scala 39:67] + wire _GEN_59 = _T_175 ? 1'h0 : _GEN_40; // @[Conditional.scala 39:67] + wire _GEN_79 = _T_136 ? 1'h0 : _GEN_59; // @[Conditional.scala 39:67] + wire _GEN_95 = _T_101 ? 1'h0 : _GEN_79; // @[Conditional.scala 39:67] + wire trxn_done = _T_49 ? 1'h0 : _GEN_95; // @[Conditional.scala 40:58] + reg cmd_doneQ; // @[axi4_to_ahb.scala 319:52] + wire _T_282 = cmd_doneQ & ahb_hready_q; // @[axi4_to_ahb.scala 239:34] + wire _T_283 = _T_282 | ahb_hresp_q; // @[axi4_to_ahb.scala 239:50] wire _T_440 = 3'h5 == buf_state; // @[Conditional.scala 37:30] - wire _GEN_1 = _T_440 & io_axi_b_ready; // @[Conditional.scala 39:67] - wire _GEN_3 = _T_281 ? 1'h0 : _GEN_1; // @[Conditional.scala 39:67] - wire _GEN_20 = _T_188 ? 1'h0 : _GEN_3; // @[Conditional.scala 39:67] - wire _GEN_35 = _T_186 ? 1'h0 : _GEN_20; // @[Conditional.scala 39:67] - wire _GEN_51 = _T_175 ? 1'h0 : _GEN_35; // @[Conditional.scala 39:67] - wire _GEN_69 = _T_136 ? 1'h0 : _GEN_51; // @[Conditional.scala 39:67] - wire _GEN_83 = _T_101 ? 1'h0 : _GEN_69; // @[Conditional.scala 39:67] + wire _GEN_3 = _T_281 ? _T_283 : _T_440; // @[Conditional.scala 39:67] + wire _GEN_20 = _T_188 ? trxn_done : _GEN_3; // @[Conditional.scala 39:67] + wire _GEN_35 = _T_186 ? _T_156 : _GEN_20; // @[Conditional.scala 39:67] + wire _GEN_51 = _T_175 ? _T_111 : _GEN_35; // @[Conditional.scala 39:67] + wire _GEN_69 = _T_136 ? _T_156 : _GEN_51; // @[Conditional.scala 39:67] + wire _GEN_83 = _T_101 ? _T_111 : _GEN_69; // @[Conditional.scala 39:67] wire buf_state_en = _T_49 ? master_valid : _GEN_83; // @[Conditional.scala 40:58] - wire [1:0] _T_14 = wr_cmd_vld ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 149:20] - wire [2:0] master_opc = {{1'd0}, _T_14}; // @[axi4_to_ahb.scala 149:14] - wire _T_51 = master_opc[2:1] == 2'h1; // @[axi4_to_ahb.scala 175:41] + wire [1:0] _T_14 = wr_cmd_vld ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 142:20] + wire [2:0] master_opc = {{1'd0}, _T_14}; // @[axi4_to_ahb.scala 142:14] + wire _T_51 = master_opc[2:1] == 2'h1; // @[axi4_to_ahb.scala 168:41] wire _GEN_8 = _T_281 & _T_51; // @[Conditional.scala 39:67] wire _GEN_29 = _T_188 ? 1'h0 : _GEN_8; // @[Conditional.scala 39:67] wire _GEN_46 = _T_186 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67] @@ -79875,61 +80328,169 @@ module axi4_to_ahb( wire _GEN_81 = _T_136 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67] wire _GEN_97 = _T_101 ? 1'h0 : _GEN_81; // @[Conditional.scala 39:67] wire buf_write_in = _T_49 ? _T_51 : _GEN_97; // @[Conditional.scala 40:58] - wire [2:0] _T_53 = buf_write_in ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 176:26] - wire _T_103 = master_opc == 3'h0; // @[axi4_to_ahb.scala 189:61] - wire _T_104 = master_valid & _T_103; // @[axi4_to_ahb.scala 189:41] - wire [2:0] _T_106 = _T_104 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 189:26] - wire _T_286 = buf_state_en & io_axi_b_ready; // @[axi4_to_ahb.scala 247:51] - wire _GEN_4 = _T_281 & _T_286; // @[Conditional.scala 39:67] + wire [2:0] _T_53 = buf_write_in ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 169:26] + wire _T_103 = master_opc == 3'h0; // @[axi4_to_ahb.scala 182:61] + wire _T_104 = master_valid & _T_103; // @[axi4_to_ahb.scala 182:41] + wire [2:0] _T_106 = _T_104 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 182:26] + wire _T_124 = _T_106 == 3'h6; // @[axi4_to_ahb.scala 186:174] + wire _T_125 = _T_111 & _T_124; // @[axi4_to_ahb.scala 186:88] + wire _T_137 = ~ahb_hresp_q; // @[axi4_to_ahb.scala 194:39] + wire _T_138 = ahb_hready_q & _T_137; // @[axi4_to_ahb.scala 194:37] + wire _T_141 = master_valid & _T_51; // @[axi4_to_ahb.scala 194:70] + wire _T_142 = ~_T_141; // @[axi4_to_ahb.scala 194:55] + wire _T_143 = _T_138 & _T_142; // @[axi4_to_ahb.scala 194:53] + wire _T_285 = buf_state_en & _T_137; // @[axi4_to_ahb.scala 240:36] + wire _GEN_4 = _T_281 & _T_285; // @[Conditional.scala 39:67] wire _GEN_26 = _T_188 ? 1'h0 : _GEN_4; // @[Conditional.scala 39:67] wire _GEN_45 = _T_186 ? 1'h0 : _GEN_26; // @[Conditional.scala 39:67] wire _GEN_62 = _T_175 ? 1'h0 : _GEN_45; // @[Conditional.scala 39:67] - wire _GEN_66 = _T_136 ? 1'h0 : _GEN_62; // @[Conditional.scala 39:67] - wire _GEN_86 = _T_101 ? 1'h0 : _GEN_66; // @[Conditional.scala 39:67] + wire _GEN_66 = _T_136 ? _T_143 : _GEN_62; // @[Conditional.scala 39:67] + wire _GEN_86 = _T_101 ? _T_125 : _GEN_66; // @[Conditional.scala 39:67] wire master_ready = _T_49 | _GEN_86; // @[Conditional.scala 40:58] - wire _T_149 = master_valid & master_ready; // @[axi4_to_ahb.scala 203:82] - wire _T_152 = _T_149 & _T_103; // @[axi4_to_ahb.scala 203:97] - wire [2:0] _T_154 = _T_152 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 203:67] - wire _T_287 = ~io_axi_b_ready; // @[axi4_to_ahb.scala 248:42] - wire [2:0] _T_293 = _T_51 ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 248:99] - wire [2:0] _T_294 = master_valid ? _T_293 : 3'h0; // @[axi4_to_ahb.scala 248:65] - wire [2:0] _T_295 = _T_287 ? 3'h5 : _T_294; // @[axi4_to_ahb.scala 248:26] + wire _T_149 = master_valid & master_ready; // @[axi4_to_ahb.scala 196:82] + wire _T_152 = _T_149 & _T_103; // @[axi4_to_ahb.scala 196:97] + wire [2:0] _T_154 = _T_152 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 196:67] + wire [2:0] _T_155 = ahb_hresp_q ? 3'h7 : _T_154; // @[axi4_to_ahb.scala 196:26] + wire [2:0] _T_293 = _T_51 ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 241:99] + wire [2:0] _T_294 = master_valid ? _T_293 : 3'h0; // @[axi4_to_ahb.scala 241:65] + wire [2:0] _T_295 = ahb_hresp_q ? 3'h5 : _T_294; // @[axi4_to_ahb.scala 241:26] wire [2:0] _GEN_5 = _T_281 ? _T_295 : 3'h0; // @[Conditional.scala 39:67] wire [2:0] _GEN_18 = _T_188 ? 3'h4 : _GEN_5; // @[Conditional.scala 39:67] wire [2:0] _GEN_34 = _T_186 ? 3'h5 : _GEN_18; // @[Conditional.scala 39:67] wire [2:0] _GEN_50 = _T_175 ? 3'h3 : _GEN_34; // @[Conditional.scala 39:67] - wire [2:0] _GEN_68 = _T_136 ? _T_154 : _GEN_50; // @[Conditional.scala 39:67] + wire [2:0] _GEN_68 = _T_136 ? _T_155 : _GEN_50; // @[Conditional.scala 39:67] wire [2:0] _GEN_82 = _T_101 ? _T_106 : _GEN_68; // @[Conditional.scala 39:67] wire [2:0] buf_nxtstate = _T_49 ? _T_53 : _GEN_82; // @[Conditional.scala 40:58] - reg wrbuf_tag; // @[Reg.scala 27:20] + reg [31:0] wrbuf_addr; // @[lib.scala 374:16] + wire [31:0] master_addr = wr_cmd_vld ? wrbuf_addr : io_axi_ar_bits_addr; // @[axi4_to_ahb.scala 143:21] + reg [2:0] wrbuf_size; // @[Reg.scala 27:20] + wire [2:0] master_size = wr_cmd_vld ? wrbuf_size : io_axi_ar_bits_size; // @[axi4_to_ahb.scala 144:21] + reg [7:0] wrbuf_byteen; // @[Reg.scala 27:20] reg [63:0] wrbuf_data; // @[lib.scala 374:16] - wire _T_358 = buf_nxtstate != 3'h5; // @[axi4_to_ahb.scala 258:55] - wire _T_359 = buf_state_en & _T_358; // @[axi4_to_ahb.scala 258:39] + wire _T_358 = buf_nxtstate != 3'h5; // @[axi4_to_ahb.scala 251:55] + wire _T_359 = buf_state_en & _T_358; // @[axi4_to_ahb.scala 251:39] wire _GEN_14 = _T_281 ? _T_359 : _T_440; // @[Conditional.scala 39:67] wire _GEN_33 = _T_188 ? 1'h0 : _GEN_14; // @[Conditional.scala 39:67] wire _GEN_49 = _T_186 ? 1'h0 : _GEN_33; // @[Conditional.scala 39:67] wire _GEN_52 = _T_175 ? buf_state_en : _GEN_49; // @[Conditional.scala 39:67] - wire _GEN_73 = _T_136 ? buf_state_en : _GEN_52; // @[Conditional.scala 39:67] + wire _GEN_73 = _T_136 ? _T_285 : _GEN_52; // @[Conditional.scala 39:67] wire _GEN_94 = _T_101 ? 1'h0 : _GEN_73; // @[Conditional.scala 39:67] wire slave_valid_pre = _T_49 ? 1'h0 : _GEN_94; // @[Conditional.scala 40:58] - wire _T_25 = slave_valid_pre & io_axi_b_ready; // @[axi4_to_ahb.scala 156:33] - wire buf_clk = rvclkhdr_6_io_l1clk; // @[axi4_to_ahb.scala 125:21 axi4_to_ahb.scala 339:12] + wire buf_clk = rvclkhdr_6_io_l1clk; // @[axi4_to_ahb.scala 118:21 axi4_to_ahb.scala 332:12] reg slvbuf_write; // @[Reg.scala 27:20] - wire [1:0] _T_596 = slvbuf_write ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 292:23] - wire [3:0] slave_opc = {_T_596,2'h0}; // @[Cat.scala 29:58] - wire [1:0] _T_30 = slave_opc[1] ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 157:55] - reg slvbuf_tag; // @[Reg.scala 27:20] - wire _T_35 = slave_opc[3:2] == 2'h0; // @[axi4_to_ahb.scala 160:66] - wire _T_604 = buf_state == 3'h5; // @[axi4_to_ahb.scala 293:91] + wire [1:0] _T_596 = slvbuf_write ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 285:23] + reg slvbuf_error; // @[Reg.scala 27:20] + wire [1:0] _T_598 = slvbuf_error ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_599 = _T_598 & 2'h2; // @[axi4_to_ahb.scala 285:88] + wire [3:0] slave_opc = {_T_596,_T_599}; // @[Cat.scala 29:58] + wire [1:0] _T_30 = slave_opc[1] ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 150:55] + wire _T_35 = slave_opc[3:2] == 2'h0; // @[axi4_to_ahb.scala 153:66] + reg [31:0] last_bus_addr; // @[Reg.scala 27:20] + wire [63:0] _T_603 = {last_bus_addr,last_bus_addr}; // @[Cat.scala 29:58] + wire _T_604 = buf_state == 3'h5; // @[axi4_to_ahb.scala 286:91] reg [63:0] buf_data; // @[lib.scala 374:16] - wire _T_44 = io_axi_aw_valid & io_axi_aw_ready; // @[axi4_to_ahb.scala 167:57] - wire _T_45 = io_axi_w_valid & io_axi_w_ready; // @[axi4_to_ahb.scala 167:94] - wire _T_46 = _T_44 | _T_45; // @[axi4_to_ahb.scala 167:76] - wire _T_55 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 179:54] - wire _T_56 = buf_state_en & _T_55; // @[axi4_to_ahb.scala 179:38] - wire _T_96 = buf_nxtstate == 3'h1; // @[axi4_to_ahb.scala 184:51] - wire _T_300 = _T_55 | _T_96; // @[axi4_to_ahb.scala 252:62] - wire _T_301 = buf_state_en & _T_300; // @[axi4_to_ahb.scala 252:33] + wire ahbm_data_clk = rvclkhdr_9_io_l1clk; // @[axi4_to_ahb.scala 26:27 axi4_to_ahb.scala 335:17] + reg [63:0] ahb_hrdata_q; // @[axi4_to_ahb.scala 325:57] + wire [63:0] _T_607 = _T_604 ? buf_data : ahb_hrdata_q; // @[axi4_to_ahb.scala 286:79] + wire _T_44 = io_axi_aw_valid & io_axi_aw_ready; // @[axi4_to_ahb.scala 160:57] + wire _T_45 = io_axi_w_valid & io_axi_w_ready; // @[axi4_to_ahb.scala 160:94] + wire _T_46 = _T_44 | _T_45; // @[axi4_to_ahb.scala 160:76] + wire _T_55 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 172:54] + wire _T_56 = buf_state_en & _T_55; // @[axi4_to_ahb.scala 172:38] + wire [2:0] _T_87 = wrbuf_byteen[6] ? 3'h6 : 3'h7; // @[Mux.scala 98:16] + wire [2:0] _T_88 = wrbuf_byteen[5] ? 3'h5 : _T_87; // @[Mux.scala 98:16] + wire [2:0] _T_89 = wrbuf_byteen[4] ? 3'h4 : _T_88; // @[Mux.scala 98:16] + wire [2:0] _T_90 = wrbuf_byteen[3] ? 3'h3 : _T_89; // @[Mux.scala 98:16] + wire [2:0] _T_91 = wrbuf_byteen[2] ? 3'h2 : _T_90; // @[Mux.scala 98:16] + wire [2:0] _T_92 = wrbuf_byteen[1] ? 3'h1 : _T_91; // @[Mux.scala 98:16] + wire [2:0] _T_93 = wrbuf_byteen[0] ? 3'h0 : _T_92; // @[Mux.scala 98:16] + wire [2:0] _T_95 = buf_write_in ? _T_93 : master_addr[2:0]; // @[axi4_to_ahb.scala 175:30] + wire _T_96 = buf_nxtstate == 3'h1; // @[axi4_to_ahb.scala 177:51] + wire _T_126 = master_ready & master_valid; // @[axi4_to_ahb.scala 188:33] + wire _T_162 = buf_nxtstate == 3'h6; // @[axi4_to_ahb.scala 203:64] + wire _T_163 = _T_126 & _T_162; // @[axi4_to_ahb.scala 203:48] + wire _T_164 = _T_163 & buf_state_en; // @[axi4_to_ahb.scala 203:79] + wire _T_349 = buf_state_en & buf_write_in; // @[axi4_to_ahb.scala 249:33] + wire _T_351 = _T_349 & _T_55; // @[axi4_to_ahb.scala 249:48] + wire _GEN_12 = _T_281 & _T_351; // @[Conditional.scala 39:67] + wire _GEN_32 = _T_188 ? 1'h0 : _GEN_12; // @[Conditional.scala 39:67] + wire _GEN_48 = _T_186 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67] + wire _GEN_65 = _T_175 ? 1'h0 : _GEN_48; // @[Conditional.scala 39:67] + wire _GEN_75 = _T_136 ? _T_164 : _GEN_65; // @[Conditional.scala 39:67] + wire _GEN_88 = _T_101 ? _T_126 : _GEN_75; // @[Conditional.scala 39:67] + wire bypass_en = _T_49 ? buf_state_en : _GEN_88; // @[Conditional.scala 40:58] + wire [1:0] _T_99 = bypass_en ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_100 = _T_99 & 2'h2; // @[axi4_to_ahb.scala 178:49] + wire _T_112 = ~master_valid; // @[axi4_to_ahb.scala 184:34] + wire _T_113 = buf_state_en & _T_112; // @[axi4_to_ahb.scala 184:32] + reg [31:0] buf_addr; // @[lib.scala 374:16] + wire [2:0] _T_130 = bypass_en ? master_addr[2:0] : buf_addr[2:0]; // @[axi4_to_ahb.scala 189:30] + wire _T_131 = ~buf_state_en; // @[axi4_to_ahb.scala 190:48] + wire _T_132 = _T_131 | bypass_en; // @[axi4_to_ahb.scala 190:62] + wire [1:0] _T_134 = _T_132 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_135 = 2'h2 & _T_134; // @[axi4_to_ahb.scala 190:36] + wire _T_169 = buf_nxtstate != 3'h6; // @[axi4_to_ahb.scala 205:63] + wire _T_170 = _T_169 & buf_state_en; // @[axi4_to_ahb.scala 205:78] + wire _T_171 = ~_T_170; // @[axi4_to_ahb.scala 205:47] + wire [1:0] _T_173 = _T_171 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_174 = 2'h2 & _T_173; // @[axi4_to_ahb.scala 205:36] + wire [1:0] _T_184 = _T_131 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_185 = 2'h2 & _T_184; // @[axi4_to_ahb.scala 215:41] + reg [2:0] buf_cmd_byte_ptrQ; // @[Reg.scala 27:20] + reg [7:0] buf_byteen; // @[Reg.scala 27:20] + wire [2:0] _T_197 = buf_cmd_byte_ptrQ + 3'h1; // @[axi4_to_ahb.scala 135:52] + wire _T_200 = 3'h0 >= _T_197; // @[axi4_to_ahb.scala 136:62] + wire _T_201 = buf_byteen[0] & _T_200; // @[axi4_to_ahb.scala 136:48] + wire _T_203 = 3'h1 >= _T_197; // @[axi4_to_ahb.scala 136:62] + wire _T_204 = buf_byteen[1] & _T_203; // @[axi4_to_ahb.scala 136:48] + wire _T_206 = 3'h2 >= _T_197; // @[axi4_to_ahb.scala 136:62] + wire _T_207 = buf_byteen[2] & _T_206; // @[axi4_to_ahb.scala 136:48] + wire _T_209 = 3'h3 >= _T_197; // @[axi4_to_ahb.scala 136:62] + wire _T_210 = buf_byteen[3] & _T_209; // @[axi4_to_ahb.scala 136:48] + wire _T_212 = 3'h4 >= _T_197; // @[axi4_to_ahb.scala 136:62] + wire _T_213 = buf_byteen[4] & _T_212; // @[axi4_to_ahb.scala 136:48] + wire _T_215 = 3'h5 >= _T_197; // @[axi4_to_ahb.scala 136:62] + wire _T_216 = buf_byteen[5] & _T_215; // @[axi4_to_ahb.scala 136:48] + wire _T_218 = 3'h6 >= _T_197; // @[axi4_to_ahb.scala 136:62] + wire _T_219 = buf_byteen[6] & _T_218; // @[axi4_to_ahb.scala 136:48] + wire [2:0] _T_224 = _T_219 ? 3'h6 : 3'h7; // @[Mux.scala 98:16] + wire [2:0] _T_225 = _T_216 ? 3'h5 : _T_224; // @[Mux.scala 98:16] + wire [2:0] _T_226 = _T_213 ? 3'h4 : _T_225; // @[Mux.scala 98:16] + wire [2:0] _T_227 = _T_210 ? 3'h3 : _T_226; // @[Mux.scala 98:16] + wire [2:0] _T_228 = _T_207 ? 3'h2 : _T_227; // @[Mux.scala 98:16] + wire [2:0] _T_229 = _T_204 ? 3'h1 : _T_228; // @[Mux.scala 98:16] + wire [2:0] _T_230 = _T_201 ? 3'h0 : _T_229; // @[Mux.scala 98:16] + wire [2:0] _T_231 = trxn_done ? _T_230 : buf_cmd_byte_ptrQ; // @[axi4_to_ahb.scala 233:30] + wire _T_232 = buf_cmd_byte_ptrQ == 3'h7; // @[axi4_to_ahb.scala 234:65] + reg buf_aligned; // @[Reg.scala 27:20] + wire _T_233 = buf_aligned | _T_232; // @[axi4_to_ahb.scala 234:44] + wire [7:0] _T_271 = buf_byteen >> _T_230; // @[axi4_to_ahb.scala 234:92] + wire _T_273 = ~_T_271[0]; // @[axi4_to_ahb.scala 234:163] + wire _T_274 = _T_233 | _T_273; // @[axi4_to_ahb.scala 234:79] + wire _T_275 = trxn_done & _T_274; // @[axi4_to_ahb.scala 234:29] + wire _T_346 = _T_232 | _T_273; // @[axi4_to_ahb.scala 248:38] + wire _T_347 = _T_109 & _T_346; // @[axi4_to_ahb.scala 247:80] + wire _T_348 = ahb_hresp_q | _T_347; // @[axi4_to_ahb.scala 247:34] + wire _GEN_11 = _T_281 & _T_348; // @[Conditional.scala 39:67] + wire _GEN_24 = _T_188 ? _T_275 : _GEN_11; // @[Conditional.scala 39:67] + wire _GEN_43 = _T_186 ? 1'h0 : _GEN_24; // @[Conditional.scala 39:67] + wire _GEN_61 = _T_175 ? 1'h0 : _GEN_43; // @[Conditional.scala 39:67] + wire _GEN_74 = _T_136 ? _T_113 : _GEN_61; // @[Conditional.scala 39:67] + wire _GEN_84 = _T_101 ? _T_113 : _GEN_74; // @[Conditional.scala 39:67] + wire cmd_done = _T_49 ? 1'h0 : _GEN_84; // @[Conditional.scala 40:58] + wire _T_276 = cmd_done | cmd_doneQ; // @[axi4_to_ahb.scala 235:47] + wire _T_277 = ~_T_276; // @[axi4_to_ahb.scala 235:36] + wire [1:0] _T_279 = _T_277 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_280 = _T_279 & 2'h2; // @[axi4_to_ahb.scala 235:61] + wire _T_300 = _T_55 | _T_96; // @[axi4_to_ahb.scala 245:62] + wire _T_301 = buf_state_en & _T_300; // @[axi4_to_ahb.scala 245:33] + wire _T_354 = _T_277 | bypass_en; // @[axi4_to_ahb.scala 250:61] + wire [1:0] _T_356 = _T_354 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_357 = _T_356 & 2'h2; // @[axi4_to_ahb.scala 250:75] + wire _T_364 = trxn_done | bypass_en; // @[axi4_to_ahb.scala 253:40] + wire [2:0] _T_439 = bypass_en ? _T_93 : _T_231; // @[axi4_to_ahb.scala 254:30] + wire _GEN_6 = _T_281 & ahb_hresp_q; // @[Conditional.scala 39:67] + wire _GEN_7 = _T_281 ? buf_state_en : _T_440; // @[Conditional.scala 39:67] wire _GEN_9 = _T_281 & _T_301; // @[Conditional.scala 39:67] wire _GEN_30 = _T_188 ? 1'h0 : _GEN_9; // @[Conditional.scala 39:67] wire _GEN_47 = _T_186 ? 1'h0 : _GEN_30; // @[Conditional.scala 39:67] @@ -79938,39 +80499,127 @@ module axi4_to_ahb( wire _GEN_87 = _T_101 ? master_ready : _GEN_67; // @[Conditional.scala 39:67] wire buf_wr_en = _T_49 ? buf_state_en : _GEN_87; // @[Conditional.scala 40:58] wire _GEN_10 = _T_281 & buf_wr_en; // @[Conditional.scala 39:67] + wire [1:0] _GEN_13 = _T_281 ? _T_357 : 2'h0; // @[Conditional.scala 39:67] + wire _GEN_16 = _T_281 & _T_364; // @[Conditional.scala 39:67] + wire [2:0] _GEN_17 = _T_281 ? _T_439 : 3'h0; // @[Conditional.scala 39:67] + wire _GEN_21 = _T_188 ? buf_state_en : _GEN_16; // @[Conditional.scala 39:67] wire _GEN_22 = _T_188 & buf_state_en; // @[Conditional.scala 39:67] + wire [2:0] _GEN_23 = _T_188 ? _T_231 : _GEN_17; // @[Conditional.scala 39:67] + wire [1:0] _GEN_25 = _T_188 ? _T_280 : _GEN_13; // @[Conditional.scala 39:67] + wire _GEN_28 = _T_188 ? 1'h0 : _GEN_7; // @[Conditional.scala 39:67] wire _GEN_31 = _T_188 ? 1'h0 : _GEN_10; // @[Conditional.scala 39:67] wire _GEN_36 = _T_186 ? buf_state_en : _GEN_31; // @[Conditional.scala 39:67] + wire _GEN_38 = _T_186 ? buf_state_en : _GEN_28; // @[Conditional.scala 39:67] wire _GEN_39 = _T_186 ? buf_state_en : _GEN_22; // @[Conditional.scala 39:67] + wire _GEN_41 = _T_186 ? 1'h0 : _GEN_21; // @[Conditional.scala 39:67] + wire [2:0] _GEN_42 = _T_186 ? 3'h0 : _GEN_23; // @[Conditional.scala 39:67] + wire [1:0] _GEN_44 = _T_186 ? 2'h0 : _GEN_25; // @[Conditional.scala 39:67] wire _GEN_53 = _T_175 ? buf_state_en : _GEN_39; // @[Conditional.scala 39:67] + wire [2:0] _GEN_54 = _T_175 ? buf_addr[2:0] : _GEN_42; // @[Conditional.scala 39:67] + wire [1:0] _GEN_55 = _T_175 ? _T_185 : _GEN_44; // @[Conditional.scala 39:67] wire _GEN_56 = _T_175 ? 1'h0 : _GEN_36; // @[Conditional.scala 39:67] + wire _GEN_58 = _T_175 ? 1'h0 : _GEN_38; // @[Conditional.scala 39:67] + wire _GEN_60 = _T_175 ? 1'h0 : _GEN_41; // @[Conditional.scala 39:67] wire _GEN_70 = _T_136 ? buf_state_en : _GEN_56; // @[Conditional.scala 39:67] + wire _GEN_72 = _T_136 ? buf_state_en : _GEN_58; // @[Conditional.scala 39:67] + wire [2:0] _GEN_76 = _T_136 ? _T_130 : _GEN_54; // @[Conditional.scala 39:67] + wire [1:0] _GEN_77 = _T_136 ? _T_174 : _GEN_55; // @[Conditional.scala 39:67] wire _GEN_78 = _T_136 ? buf_wr_en : _GEN_53; // @[Conditional.scala 39:67] + wire _GEN_80 = _T_136 ? 1'h0 : _GEN_60; // @[Conditional.scala 39:67] wire _GEN_85 = _T_101 ? buf_state_en : _GEN_78; // @[Conditional.scala 39:67] + wire [2:0] _GEN_89 = _T_101 ? _T_130 : _GEN_76; // @[Conditional.scala 39:67] + wire [1:0] _GEN_90 = _T_101 ? _T_135 : _GEN_77; // @[Conditional.scala 39:67] wire _GEN_91 = _T_101 ? 1'h0 : _GEN_70; // @[Conditional.scala 39:67] + wire _GEN_93 = _T_101 ? 1'h0 : _GEN_72; // @[Conditional.scala 39:67] + wire _GEN_96 = _T_101 ? 1'h0 : _GEN_80; // @[Conditional.scala 39:67] wire buf_data_wr_en = _T_49 ? _T_56 : _GEN_91; // @[Conditional.scala 40:58] + wire buf_cmd_byte_ptr_en = _T_49 ? buf_state_en : _GEN_96; // @[Conditional.scala 40:58] + wire [2:0] buf_cmd_byte_ptr = _T_49 ? _T_95 : _GEN_89; // @[Conditional.scala 40:58] wire slvbuf_wr_en = _T_49 ? 1'h0 : _GEN_85; // @[Conditional.scala 40:58] - wire _T_489 = buf_state == 3'h3; // @[axi4_to_ahb.scala 275:33] + wire slvbuf_error_en = _T_49 ? 1'h0 : _GEN_93; // @[Conditional.scala 40:58] + wire _T_535 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 271:24] + wire _T_536 = _T_103 | _T_535; // @[axi4_to_ahb.scala 270:48] + wire _T_538 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 271:54] + wire _T_539 = _T_536 | _T_538; // @[axi4_to_ahb.scala 271:33] + wire _T_541 = master_size[1:0] == 2'h2; // @[axi4_to_ahb.scala 271:93] + wire _T_542 = _T_539 | _T_541; // @[axi4_to_ahb.scala 271:72] + wire _T_544 = master_size[1:0] == 2'h3; // @[axi4_to_ahb.scala 272:25] + wire _T_546 = wrbuf_byteen == 8'h3; // @[axi4_to_ahb.scala 272:62] + wire _T_548 = wrbuf_byteen == 8'hc; // @[axi4_to_ahb.scala 272:97] + wire _T_549 = _T_546 | _T_548; // @[axi4_to_ahb.scala 272:74] + wire _T_551 = wrbuf_byteen == 8'h30; // @[axi4_to_ahb.scala 272:132] + wire _T_552 = _T_549 | _T_551; // @[axi4_to_ahb.scala 272:109] + wire _T_554 = wrbuf_byteen == 8'hc0; // @[axi4_to_ahb.scala 272:168] + wire _T_555 = _T_552 | _T_554; // @[axi4_to_ahb.scala 272:145] + wire _T_557 = wrbuf_byteen == 8'hf; // @[axi4_to_ahb.scala 273:28] + wire _T_558 = _T_555 | _T_557; // @[axi4_to_ahb.scala 272:181] + wire _T_560 = wrbuf_byteen == 8'hf0; // @[axi4_to_ahb.scala 273:63] + wire _T_561 = _T_558 | _T_560; // @[axi4_to_ahb.scala 273:40] + wire _T_563 = wrbuf_byteen == 8'hff; // @[axi4_to_ahb.scala 273:99] + wire _T_564 = _T_561 | _T_563; // @[axi4_to_ahb.scala 273:76] + wire _T_565 = _T_544 & _T_564; // @[axi4_to_ahb.scala 272:38] + wire buf_aligned_in = _T_542 | _T_565; // @[axi4_to_ahb.scala 271:106] + wire _T_444 = buf_aligned_in & _T_51; // @[axi4_to_ahb.scala 265:60] + wire [2:0] _T_461 = _T_548 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_462 = 3'h2 & _T_461; // @[axi4_to_ahb.scala 128:15] + wire _T_468 = _T_560 | _T_546; // @[axi4_to_ahb.scala 129:56] + wire [2:0] _T_470 = _T_468 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_471 = 3'h4 & _T_470; // @[axi4_to_ahb.scala 129:15] + wire [2:0] _T_472 = _T_462 | _T_471; // @[axi4_to_ahb.scala 128:63] + wire [2:0] _T_476 = _T_554 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_477 = 3'h6 & _T_476; // @[axi4_to_ahb.scala 130:15] + wire [2:0] _T_478 = _T_472 | _T_477; // @[axi4_to_ahb.scala 129:96] + wire [2:0] _T_485 = _T_444 ? _T_478 : master_addr[2:0]; // @[axi4_to_ahb.scala 265:43] + wire _T_489 = buf_state == 3'h3; // @[axi4_to_ahb.scala 268:33] + wire _T_495 = buf_aligned_in & _T_544; // @[axi4_to_ahb.scala 269:38] + wire _T_498 = _T_495 & _T_51; // @[axi4_to_ahb.scala 269:71] + wire [1:0] _T_504 = _T_563 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire _T_510 = _T_560 | _T_557; // @[axi4_to_ahb.scala 122:55] + wire [1:0] _T_512 = _T_510 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_513 = 2'h2 & _T_512; // @[axi4_to_ahb.scala 122:16] + wire [1:0] _T_514 = _T_504 | _T_513; // @[axi4_to_ahb.scala 121:64] + wire _T_519 = _T_554 | _T_551; // @[axi4_to_ahb.scala 123:60] + wire _T_522 = _T_519 | _T_548; // @[axi4_to_ahb.scala 123:89] + wire _T_525 = _T_522 | _T_546; // @[axi4_to_ahb.scala 123:123] + wire [1:0] _T_527 = _T_525 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_528 = 2'h1 & _T_527; // @[axi4_to_ahb.scala 123:21] + wire [1:0] _T_529 = _T_514 | _T_528; // @[axi4_to_ahb.scala 122:93] + wire [1:0] _T_531 = _T_498 ? _T_529 : master_size[1:0]; // @[axi4_to_ahb.scala 269:21] + wire [31:0] _T_570 = {master_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] + wire [31:0] _T_573 = {buf_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] + wire [1:0] _T_577 = buf_aligned_in ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [2:0] buf_size_in = {{1'd0}, _T_531}; // @[axi4_to_ahb.scala 269:15] + wire [1:0] _T_579 = _T_577 & buf_size_in[1:0]; // @[axi4_to_ahb.scala 276:81] + wire [2:0] _T_580 = {1'h0,_T_579}; // @[Cat.scala 29:58] + wire [1:0] _T_582 = buf_aligned ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + reg [1:0] buf_size; // @[Reg.scala 27:20] + wire [1:0] _T_584 = _T_582 & buf_size; // @[axi4_to_ahb.scala 276:138] + wire [2:0] _T_585 = {1'h0,_T_584}; // @[Cat.scala 29:58] reg buf_write; // @[Reg.scala 27:20] - wire wrbuf_en = _T_44 & master_ready; // @[axi4_to_ahb.scala 298:49] - wire wrbuf_data_en = _T_45 & master_ready; // @[axi4_to_ahb.scala 299:52] - wire wrbuf_cmd_sent = _T_149 & _T_51; // @[axi4_to_ahb.scala 300:49] - wire _T_622 = ~wrbuf_en; // @[axi4_to_ahb.scala 301:33] - wire wrbuf_rst = wrbuf_cmd_sent & _T_622; // @[axi4_to_ahb.scala 301:31] - wire _T_624 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 303:36] - wire _T_625 = wrbuf_vld & _T_624; // @[axi4_to_ahb.scala 303:34] - wire _T_626 = ~_T_625; // @[axi4_to_ahb.scala 303:22] - wire _T_629 = wrbuf_data_vld & _T_624; // @[axi4_to_ahb.scala 304:38] - wire _T_630 = ~_T_629; // @[axi4_to_ahb.scala 304:21] - wire _T_633 = ~wr_cmd_vld; // @[axi4_to_ahb.scala 305:22] - wire _T_636 = wrbuf_en | wrbuf_vld; // @[axi4_to_ahb.scala 308:55] - wire _T_637 = ~wrbuf_rst; // @[axi4_to_ahb.scala 308:91] - wire _T_641 = wrbuf_data_en | wrbuf_data_vld; // @[axi4_to_ahb.scala 309:55] - reg buf_tag; // @[Reg.scala 27:20] - wire _T_704 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 334:43] - wire _T_705 = _T_704 | io_clk_override; // @[axi4_to_ahb.scala 334:58] - wire _T_711 = buf_state != 3'h0; // @[axi4_to_ahb.scala 336:50] - wire _T_712 = _T_711 | io_clk_override; // @[axi4_to_ahb.scala 336:60] + wire _T_611 = io_ahb_out_htrans != 2'h0; // @[axi4_to_ahb.scala 289:44] + wire _T_612 = _T_611 & io_ahb_in_hready; // @[axi4_to_ahb.scala 289:56] + wire last_addr_en = _T_612 & io_ahb_out_hwrite; // @[axi4_to_ahb.scala 289:75] + wire wrbuf_en = _T_44 & master_ready; // @[axi4_to_ahb.scala 291:49] + wire wrbuf_data_en = _T_45 & master_ready; // @[axi4_to_ahb.scala 292:52] + wire wrbuf_cmd_sent = _T_149 & _T_51; // @[axi4_to_ahb.scala 293:49] + wire _T_622 = ~wrbuf_en; // @[axi4_to_ahb.scala 294:33] + wire wrbuf_rst = wrbuf_cmd_sent & _T_622; // @[axi4_to_ahb.scala 294:31] + wire _T_624 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 296:36] + wire _T_625 = wrbuf_vld & _T_624; // @[axi4_to_ahb.scala 296:34] + wire _T_626 = ~_T_625; // @[axi4_to_ahb.scala 296:22] + wire _T_629 = wrbuf_data_vld & _T_624; // @[axi4_to_ahb.scala 297:38] + wire _T_630 = ~_T_629; // @[axi4_to_ahb.scala 297:21] + wire _T_633 = ~wr_cmd_vld; // @[axi4_to_ahb.scala 298:22] + wire _T_636 = wrbuf_en | wrbuf_vld; // @[axi4_to_ahb.scala 301:55] + wire _T_637 = ~wrbuf_rst; // @[axi4_to_ahb.scala 301:91] + wire _T_641 = wrbuf_data_en | wrbuf_data_vld; // @[axi4_to_ahb.scala 302:55] + wire _T_691 = ~slave_valid_pre; // @[axi4_to_ahb.scala 319:92] + wire _T_704 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 327:43] + wire _T_705 = _T_704 | io_clk_override; // @[axi4_to_ahb.scala 327:58] + wire _T_708 = io_ahb_in_hready & io_ahb_out_htrans[1]; // @[axi4_to_ahb.scala 328:57] + wire _T_709 = _T_708 | io_clk_override; // @[axi4_to_ahb.scala 328:81] + wire _T_711 = buf_state != 3'h0; // @[axi4_to_ahb.scala 329:50] + wire _T_712 = _T_711 | io_clk_override; // @[axi4_to_ahb.scala 329:60] rvclkhdr rvclkhdr ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), @@ -80031,16 +80680,19 @@ module axi4_to_ahb( .io_en(rvclkhdr_9_io_en), .io_scan_mode(rvclkhdr_9_io_scan_mode) ); - assign io_axi_aw_ready = _T_626 & master_ready; // @[axi4_to_ahb.scala 303:19] - assign io_axi_w_ready = _T_630 & master_ready; // @[axi4_to_ahb.scala 304:18] - assign io_axi_b_valid = _T_25 & slave_opc[3]; // @[axi4_to_ahb.scala 156:18] - assign io_axi_b_bits_resp = slave_opc[0] ? 2'h2 : _T_30; // @[axi4_to_ahb.scala 157:22] - assign io_axi_b_bits_id = slvbuf_tag; // @[axi4_to_ahb.scala 158:20] - assign io_axi_ar_ready = _T_633 & master_ready; // @[axi4_to_ahb.scala 305:19] - assign io_axi_r_valid = _T_25 & _T_35; // @[axi4_to_ahb.scala 160:18] - assign io_axi_r_bits_id = slvbuf_tag; // @[axi4_to_ahb.scala 162:20] - assign io_axi_r_bits_data = _T_604 ? buf_data : 64'h0; // @[axi4_to_ahb.scala 163:22] - assign io_axi_r_bits_resp = slave_opc[0] ? 2'h2 : _T_30; // @[axi4_to_ahb.scala 161:22] + assign io_axi_aw_ready = _T_626 & master_ready; // @[axi4_to_ahb.scala 296:19] + assign io_axi_w_ready = _T_630 & master_ready; // @[axi4_to_ahb.scala 297:18] + assign io_axi_b_valid = slave_valid_pre & slave_opc[3]; // @[axi4_to_ahb.scala 149:18] + assign io_axi_b_bits_resp = slave_opc[0] ? 2'h2 : _T_30; // @[axi4_to_ahb.scala 150:22] + assign io_axi_ar_ready = _T_633 & master_ready; // @[axi4_to_ahb.scala 298:19] + assign io_axi_r_valid = slave_valid_pre & _T_35; // @[axi4_to_ahb.scala 153:18] + assign io_axi_r_bits_data = slvbuf_error ? _T_603 : _T_607; // @[axi4_to_ahb.scala 156:22] + assign io_axi_r_bits_resp = slave_opc[0] ? 2'h2 : _T_30; // @[axi4_to_ahb.scala 154:22] + assign io_ahb_out_haddr = bypass_en ? _T_570 : _T_573; // @[axi4_to_ahb.scala 275:20] + assign io_ahb_out_hsize = bypass_en ? _T_580 : _T_585; // @[axi4_to_ahb.scala 276:20] + assign io_ahb_out_htrans = _T_49 ? _T_100 : _GEN_90; // @[axi4_to_ahb.scala 22:21 axi4_to_ahb.scala 178:25 axi4_to_ahb.scala 190:25 axi4_to_ahb.scala 205:25 axi4_to_ahb.scala 215:25 axi4_to_ahb.scala 235:25 axi4_to_ahb.scala 250:25] + assign io_ahb_out_hwrite = bypass_en ? _T_51 : buf_write; // @[axi4_to_ahb.scala 281:21] + assign io_ahb_out_hwdata = buf_data; // @[axi4_to_ahb.scala 282:21] assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17] assign rvclkhdr_io_en = io_bus_clk_en; // @[lib.scala 345:16] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] @@ -80066,7 +80718,7 @@ module axi4_to_ahb( assign rvclkhdr_7_io_en = io_bus_clk_en; // @[lib.scala 345:16] assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] assign rvclkhdr_8_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_8_io_en = io_bus_clk_en & io_clk_override; // @[lib.scala 345:16] + assign rvclkhdr_8_io_en = io_bus_clk_en & _T_709; // @[lib.scala 345:16] assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] assign rvclkhdr_9_io_clk = clock; // @[lib.scala 344:17] assign rvclkhdr_9_io_en = io_bus_clk_en & _T_712; // @[lib.scala 345:16] @@ -80113,19 +80765,45 @@ initial begin _RAND_2 = {1{`RANDOM}}; wrbuf_data_vld = _RAND_2[0:0]; _RAND_3 = {1{`RANDOM}}; - wrbuf_tag = _RAND_3[0:0]; - _RAND_4 = {2{`RANDOM}}; - wrbuf_data = _RAND_4[63:0]; + ahb_hready_q = _RAND_3[0:0]; + _RAND_4 = {1{`RANDOM}}; + ahb_htrans_q = _RAND_4[1:0]; _RAND_5 = {1{`RANDOM}}; - slvbuf_write = _RAND_5[0:0]; + ahb_hwrite_q = _RAND_5[0:0]; _RAND_6 = {1{`RANDOM}}; - slvbuf_tag = _RAND_6[0:0]; - _RAND_7 = {2{`RANDOM}}; - buf_data = _RAND_7[63:0]; + ahb_hresp_q = _RAND_6[0:0]; + _RAND_7 = {1{`RANDOM}}; + cmd_doneQ = _RAND_7[0:0]; _RAND_8 = {1{`RANDOM}}; - buf_write = _RAND_8[0:0]; + wrbuf_addr = _RAND_8[31:0]; _RAND_9 = {1{`RANDOM}}; - buf_tag = _RAND_9[0:0]; + wrbuf_size = _RAND_9[2:0]; + _RAND_10 = {1{`RANDOM}}; + wrbuf_byteen = _RAND_10[7:0]; + _RAND_11 = {2{`RANDOM}}; + wrbuf_data = _RAND_11[63:0]; + _RAND_12 = {1{`RANDOM}}; + slvbuf_write = _RAND_12[0:0]; + _RAND_13 = {1{`RANDOM}}; + slvbuf_error = _RAND_13[0:0]; + _RAND_14 = {1{`RANDOM}}; + last_bus_addr = _RAND_14[31:0]; + _RAND_15 = {2{`RANDOM}}; + buf_data = _RAND_15[63:0]; + _RAND_16 = {2{`RANDOM}}; + ahb_hrdata_q = _RAND_16[63:0]; + _RAND_17 = {1{`RANDOM}}; + buf_addr = _RAND_17[31:0]; + _RAND_18 = {1{`RANDOM}}; + buf_cmd_byte_ptrQ = _RAND_18[2:0]; + _RAND_19 = {1{`RANDOM}}; + buf_byteen = _RAND_19[7:0]; + _RAND_20 = {1{`RANDOM}}; + buf_aligned = _RAND_20[0:0]; + _RAND_21 = {1{`RANDOM}}; + buf_size = _RAND_21[1:0]; + _RAND_22 = {1{`RANDOM}}; + buf_write = _RAND_22[0:0]; `endif // RANDOMIZE_REG_INIT if (reset) begin buf_state = 3'h0; @@ -80137,7 +80815,28 @@ initial begin wrbuf_data_vld = 1'h0; end if (reset) begin - wrbuf_tag = 1'h0; + ahb_hready_q = 1'h0; + end + if (reset) begin + ahb_htrans_q = 2'h0; + end + if (reset) begin + ahb_hwrite_q = 1'h0; + end + if (reset) begin + ahb_hresp_q = 1'h0; + end + if (reset) begin + cmd_doneQ = 1'h0; + end + if (reset) begin + wrbuf_addr = 32'h0; + end + if (reset) begin + wrbuf_size = 3'h0; + end + if (reset) begin + wrbuf_byteen = 8'h0; end if (reset) begin wrbuf_data = 64'h0; @@ -80146,16 +80845,34 @@ initial begin slvbuf_write = 1'h0; end if (reset) begin - slvbuf_tag = 1'h0; + slvbuf_error = 1'h0; + end + if (reset) begin + last_bus_addr = 32'h0; end if (reset) begin buf_data = 64'h0; end if (reset) begin - buf_write = 1'h0; + ahb_hrdata_q = 64'h0; end if (reset) begin - buf_tag = 1'h0; + buf_addr = 32'h0; + end + if (reset) begin + buf_cmd_byte_ptrQ = 3'h0; + end + if (reset) begin + buf_byteen = 8'h0; + end + if (reset) begin + buf_aligned = 1'h0; + end + if (reset) begin + buf_size = 2'h0; + end + if (reset) begin + buf_write = 1'h0; end `endif // RANDOMIZE end // initial @@ -80180,7 +80897,9 @@ end // initial buf_state <= 3'h3; end end else if (_T_136) begin - if (_T_152) begin + if (ahb_hresp_q) begin + buf_state <= 3'h7; + end else if (_T_152) begin buf_state <= 3'h6; end else begin buf_state <= 3'h3; @@ -80192,7 +80911,7 @@ end // initial end else if (_T_188) begin buf_state <= 3'h4; end else if (_T_281) begin - if (_T_287) begin + if (ahb_hresp_q) begin buf_state <= 3'h5; end else if (master_valid) begin if (_T_51) begin @@ -80222,11 +80941,60 @@ end // initial wrbuf_data_vld <= _T_641 & _T_637; end end + always @(posedge ahbm_clk or posedge reset) begin + if (reset) begin + ahb_hready_q <= 1'h0; + end else begin + ahb_hready_q <= io_ahb_in_hready; + end + end + always @(posedge ahbm_clk or posedge reset) begin + if (reset) begin + ahb_htrans_q <= 2'h0; + end else begin + ahb_htrans_q <= io_ahb_out_htrans; + end + end + always @(posedge ahbm_addr_clk or posedge reset) begin + if (reset) begin + ahb_hwrite_q <= 1'h0; + end else begin + ahb_hwrite_q <= io_ahb_out_hwrite; + end + end + always @(posedge ahbm_clk or posedge reset) begin + if (reset) begin + ahb_hresp_q <= 1'h0; + end else begin + ahb_hresp_q <= io_ahb_in_hresp; + end + end + always @(posedge ahbm_clk or posedge reset) begin + if (reset) begin + cmd_doneQ <= 1'h0; + end else begin + cmd_doneQ <= _T_276 & _T_691; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + wrbuf_addr <= 32'h0; + end else begin + wrbuf_addr <= io_axi_aw_bits_addr; + end + end always @(posedge bus_clk or posedge reset) begin if (reset) begin - wrbuf_tag <= 1'h0; + wrbuf_size <= 3'h0; end else if (wrbuf_en) begin - wrbuf_tag <= io_axi_aw_bits_id; + wrbuf_size <= io_axi_aw_bits_size; + end + end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + wrbuf_byteen <= 8'h0; + end else if (wrbuf_data_en) begin + wrbuf_byteen <= io_axi_w_bits_strb; end end always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin @@ -80243,22 +81011,1255 @@ end // initial slvbuf_write <= buf_write; end end - always @(posedge buf_clk or posedge reset) begin + always @(posedge ahbm_clk or posedge reset) begin if (reset) begin - slvbuf_tag <= 1'h0; - end else if (slvbuf_wr_en) begin - slvbuf_tag <= buf_tag; + slvbuf_error <= 1'h0; + end else if (slvbuf_error_en) begin + if (_T_49) begin + slvbuf_error <= 1'h0; + end else if (_T_101) begin + slvbuf_error <= 1'h0; + end else if (_T_136) begin + slvbuf_error <= ahb_hresp_q; + end else if (_T_175) begin + slvbuf_error <= 1'h0; + end else if (_T_186) begin + slvbuf_error <= ahb_hresp_q; + end else if (_T_188) begin + slvbuf_error <= 1'h0; + end else begin + slvbuf_error <= _GEN_6; + end + end + end + always @(posedge ahbm_clk or posedge reset) begin + if (reset) begin + last_bus_addr <= 32'h0; + end else if (last_addr_en) begin + last_bus_addr <= io_ahb_out_haddr; end end always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin if (reset) begin buf_data <= 64'h0; end else if (_T_489) begin - buf_data <= 64'h0; + buf_data <= ahb_hrdata_q; end else begin buf_data <= wrbuf_data; end end + always @(posedge ahbm_data_clk or posedge reset) begin + if (reset) begin + ahb_hrdata_q <= 64'h0; + end else begin + ahb_hrdata_q <= io_ahb_in_hrdata; + end + end + always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + if (reset) begin + buf_addr <= 32'h0; + end else begin + buf_addr <= {master_addr[31:3],_T_485}; + end + end + always @(posedge ahbm_clk or posedge reset) begin + if (reset) begin + buf_cmd_byte_ptrQ <= 3'h0; + end else if (buf_cmd_byte_ptr_en) begin + if (_T_49) begin + if (buf_write_in) begin + if (wrbuf_byteen[0]) begin + buf_cmd_byte_ptrQ <= 3'h0; + end else if (wrbuf_byteen[1]) begin + buf_cmd_byte_ptrQ <= 3'h1; + end else if (wrbuf_byteen[2]) begin + buf_cmd_byte_ptrQ <= 3'h2; + end else if (wrbuf_byteen[3]) begin + buf_cmd_byte_ptrQ <= 3'h3; + end else if (wrbuf_byteen[4]) begin + buf_cmd_byte_ptrQ <= 3'h4; + end else if (wrbuf_byteen[5]) begin + buf_cmd_byte_ptrQ <= 3'h5; + end else if (wrbuf_byteen[6]) begin + buf_cmd_byte_ptrQ <= 3'h6; + end else begin + buf_cmd_byte_ptrQ <= 3'h7; + end + end else begin + buf_cmd_byte_ptrQ <= master_addr[2:0]; + end + end else if (_T_101) begin + if (bypass_en) begin + buf_cmd_byte_ptrQ <= master_addr[2:0]; + end else begin + buf_cmd_byte_ptrQ <= buf_addr[2:0]; + end + end else if (_T_136) begin + if (bypass_en) begin + buf_cmd_byte_ptrQ <= master_addr[2:0]; + end else begin + buf_cmd_byte_ptrQ <= buf_addr[2:0]; + end + end else if (_T_175) begin + buf_cmd_byte_ptrQ <= buf_addr[2:0]; + end else if (_T_186) begin + buf_cmd_byte_ptrQ <= 3'h0; + end else if (_T_188) begin + if (trxn_done) begin + if (_T_201) begin + buf_cmd_byte_ptrQ <= 3'h0; + end else if (_T_204) begin + buf_cmd_byte_ptrQ <= 3'h1; + end else if (_T_207) begin + buf_cmd_byte_ptrQ <= 3'h2; + end else if (_T_210) begin + buf_cmd_byte_ptrQ <= 3'h3; + end else if (_T_213) begin + buf_cmd_byte_ptrQ <= 3'h4; + end else if (_T_216) begin + buf_cmd_byte_ptrQ <= 3'h5; + end else if (_T_219) begin + buf_cmd_byte_ptrQ <= 3'h6; + end else begin + buf_cmd_byte_ptrQ <= 3'h7; + end + end + end else if (_T_281) begin + if (bypass_en) begin + if (wrbuf_byteen[0]) begin + buf_cmd_byte_ptrQ <= 3'h0; + end else if (wrbuf_byteen[1]) begin + buf_cmd_byte_ptrQ <= 3'h1; + end else if (wrbuf_byteen[2]) begin + buf_cmd_byte_ptrQ <= 3'h2; + end else if (wrbuf_byteen[3]) begin + buf_cmd_byte_ptrQ <= 3'h3; + end else if (wrbuf_byteen[4]) begin + buf_cmd_byte_ptrQ <= 3'h4; + end else if (wrbuf_byteen[5]) begin + buf_cmd_byte_ptrQ <= 3'h5; + end else if (wrbuf_byteen[6]) begin + buf_cmd_byte_ptrQ <= 3'h6; + end else begin + buf_cmd_byte_ptrQ <= 3'h7; + end + end else if (trxn_done) begin + if (_T_201) begin + buf_cmd_byte_ptrQ <= 3'h0; + end else if (_T_204) begin + buf_cmd_byte_ptrQ <= 3'h1; + end else if (_T_207) begin + buf_cmd_byte_ptrQ <= 3'h2; + end else if (_T_210) begin + buf_cmd_byte_ptrQ <= 3'h3; + end else if (_T_213) begin + buf_cmd_byte_ptrQ <= 3'h4; + end else if (_T_216) begin + buf_cmd_byte_ptrQ <= 3'h5; + end else if (_T_219) begin + buf_cmd_byte_ptrQ <= 3'h6; + end else begin + buf_cmd_byte_ptrQ <= 3'h7; + end + end + end else begin + buf_cmd_byte_ptrQ <= 3'h0; + end + end + end + always @(posedge buf_clk or posedge reset) begin + if (reset) begin + buf_byteen <= 8'h0; + end else if (buf_wr_en) begin + buf_byteen <= wrbuf_byteen; + end + end + always @(posedge buf_clk or posedge reset) begin + if (reset) begin + buf_aligned <= 1'h0; + end else if (buf_wr_en) begin + buf_aligned <= buf_aligned_in; + end + end + always @(posedge buf_clk or posedge reset) begin + if (reset) begin + buf_size <= 2'h0; + end else if (buf_wr_en) begin + buf_size <= buf_size_in[1:0]; + end + end + always @(posedge buf_clk or posedge reset) begin + if (reset) begin + buf_write <= 1'h0; + end else if (buf_wr_en) begin + if (_T_49) begin + buf_write <= _T_51; + end else if (_T_101) begin + buf_write <= 1'h0; + end else if (_T_136) begin + buf_write <= 1'h0; + end else if (_T_175) begin + buf_write <= 1'h0; + end else if (_T_186) begin + buf_write <= 1'h0; + end else if (_T_188) begin + buf_write <= 1'h0; + end else begin + buf_write <= _GEN_8; + end + end + end +endmodule +module axi4_to_ahb_1( + input clock, + input reset, + input io_scan_mode, + input io_bus_clk_en, + input io_clk_override, + output io_axi_aw_ready, + input io_axi_aw_valid, + input [2:0] io_axi_aw_bits_id, + input [31:0] io_axi_aw_bits_addr, + input [2:0] io_axi_aw_bits_size, + output io_axi_w_ready, + input io_axi_w_valid, + input [63:0] io_axi_w_bits_data, + input [7:0] io_axi_w_bits_strb, + output io_axi_b_valid, + output [2:0] io_axi_b_bits_id, + output io_axi_ar_ready, + input io_axi_ar_valid, + input [2:0] io_axi_ar_bits_id, + input [31:0] io_axi_ar_bits_addr, + input [2:0] io_axi_ar_bits_size, + output io_axi_r_valid, + output [2:0] io_axi_r_bits_id, + output [63:0] io_axi_r_bits_data, + output [1:0] io_axi_r_bits_resp, + input [63:0] io_ahb_in_hrdata, + input io_ahb_in_hready, + input io_ahb_in_hresp, + output [31:0] io_ahb_out_haddr, + output [2:0] io_ahb_out_hsize, + output [1:0] io_ahb_out_htrans, + output io_ahb_out_hwrite, + output [63:0] io_ahb_out_hwdata +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [63:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; + reg [31:0] _RAND_15; + reg [31:0] _RAND_16; + reg [63:0] _RAND_17; + reg [63:0] _RAND_18; + reg [31:0] _RAND_19; + reg [31:0] _RAND_20; + reg [31:0] _RAND_21; + reg [31:0] _RAND_22; + reg [31:0] _RAND_23; + reg [31:0] _RAND_24; + reg [31:0] _RAND_25; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_io_en; // @[lib.scala 343:22] + wire rvclkhdr_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_1_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_1_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_1_io_en; // @[lib.scala 343:22] + wire rvclkhdr_1_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_2_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_2_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_2_io_en; // @[lib.scala 368:23] + wire rvclkhdr_2_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_3_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_3_io_en; // @[lib.scala 368:23] + wire rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_4_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_4_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_4_io_en; // @[lib.scala 368:23] + wire rvclkhdr_4_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_5_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_5_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_5_io_en; // @[lib.scala 368:23] + wire rvclkhdr_5_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_6_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_6_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_6_io_en; // @[lib.scala 343:22] + wire rvclkhdr_6_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_7_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_7_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_7_io_en; // @[lib.scala 343:22] + wire rvclkhdr_7_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_8_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_8_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_8_io_en; // @[lib.scala 343:22] + wire rvclkhdr_8_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_9_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_9_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_9_io_en; // @[lib.scala 343:22] + wire rvclkhdr_9_io_scan_mode; // @[lib.scala 343:22] + wire ahbm_clk = rvclkhdr_7_io_l1clk; // @[axi4_to_ahb.scala 24:22 axi4_to_ahb.scala 333:12] + reg [2:0] buf_state; // @[axi4_to_ahb.scala 30:45] + wire _T_49 = 3'h0 == buf_state; // @[Conditional.scala 37:30] + wire bus_clk = rvclkhdr_io_l1clk; // @[axi4_to_ahb.scala 50:21 axi4_to_ahb.scala 162:11] + reg wrbuf_vld; // @[axi4_to_ahb.scala 301:51] + reg wrbuf_data_vld; // @[axi4_to_ahb.scala 302:51] + wire wr_cmd_vld = wrbuf_vld & wrbuf_data_vld; // @[axi4_to_ahb.scala 139:27] + wire master_valid = wr_cmd_vld | io_axi_ar_valid; // @[axi4_to_ahb.scala 140:30] + wire _T_101 = 3'h1 == buf_state; // @[Conditional.scala 37:30] + reg ahb_hready_q; // @[axi4_to_ahb.scala 321:52] + reg [1:0] ahb_htrans_q; // @[axi4_to_ahb.scala 322:52] + wire _T_108 = ahb_htrans_q != 2'h0; // @[axi4_to_ahb.scala 183:58] + wire _T_109 = ahb_hready_q & _T_108; // @[axi4_to_ahb.scala 183:36] + wire ahbm_addr_clk = rvclkhdr_8_io_l1clk; // @[axi4_to_ahb.scala 25:27 axi4_to_ahb.scala 334:17] + reg ahb_hwrite_q; // @[axi4_to_ahb.scala 323:57] + wire _T_110 = ~ahb_hwrite_q; // @[axi4_to_ahb.scala 183:72] + wire _T_111 = _T_109 & _T_110; // @[axi4_to_ahb.scala 183:70] + wire _T_136 = 3'h6 == buf_state; // @[Conditional.scala 37:30] + reg ahb_hresp_q; // @[axi4_to_ahb.scala 324:52] + wire _T_156 = ahb_hready_q | ahb_hresp_q; // @[axi4_to_ahb.scala 197:37] + wire _T_175 = 3'h7 == buf_state; // @[Conditional.scala 37:30] + wire _T_186 = 3'h3 == buf_state; // @[Conditional.scala 37:30] + wire _T_188 = 3'h2 == buf_state; // @[Conditional.scala 37:30] + wire _T_189 = ahb_hready_q & ahb_hwrite_q; // @[axi4_to_ahb.scala 229:33] + wire _T_192 = _T_189 & _T_108; // @[axi4_to_ahb.scala 229:48] + wire _T_281 = 3'h4 == buf_state; // @[Conditional.scala 37:30] + wire _GEN_15 = _T_281 & _T_192; // @[Conditional.scala 39:67] + wire _GEN_19 = _T_188 ? _T_192 : _GEN_15; // @[Conditional.scala 39:67] + wire _GEN_40 = _T_186 ? 1'h0 : _GEN_19; // @[Conditional.scala 39:67] + wire _GEN_59 = _T_175 ? 1'h0 : _GEN_40; // @[Conditional.scala 39:67] + wire _GEN_79 = _T_136 ? 1'h0 : _GEN_59; // @[Conditional.scala 39:67] + wire _GEN_95 = _T_101 ? 1'h0 : _GEN_79; // @[Conditional.scala 39:67] + wire trxn_done = _T_49 ? 1'h0 : _GEN_95; // @[Conditional.scala 40:58] + reg cmd_doneQ; // @[axi4_to_ahb.scala 319:52] + wire _T_282 = cmd_doneQ & ahb_hready_q; // @[axi4_to_ahb.scala 239:34] + wire _T_283 = _T_282 | ahb_hresp_q; // @[axi4_to_ahb.scala 239:50] + wire _T_440 = 3'h5 == buf_state; // @[Conditional.scala 37:30] + wire _GEN_3 = _T_281 ? _T_283 : _T_440; // @[Conditional.scala 39:67] + wire _GEN_20 = _T_188 ? trxn_done : _GEN_3; // @[Conditional.scala 39:67] + wire _GEN_35 = _T_186 ? _T_156 : _GEN_20; // @[Conditional.scala 39:67] + wire _GEN_51 = _T_175 ? _T_111 : _GEN_35; // @[Conditional.scala 39:67] + wire _GEN_69 = _T_136 ? _T_156 : _GEN_51; // @[Conditional.scala 39:67] + wire _GEN_83 = _T_101 ? _T_111 : _GEN_69; // @[Conditional.scala 39:67] + wire buf_state_en = _T_49 ? master_valid : _GEN_83; // @[Conditional.scala 40:58] + wire [1:0] _T_14 = wr_cmd_vld ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 142:20] + wire [2:0] master_opc = {{1'd0}, _T_14}; // @[axi4_to_ahb.scala 142:14] + wire _T_51 = master_opc[2:1] == 2'h1; // @[axi4_to_ahb.scala 168:41] + wire _GEN_8 = _T_281 & _T_51; // @[Conditional.scala 39:67] + wire _GEN_29 = _T_188 ? 1'h0 : _GEN_8; // @[Conditional.scala 39:67] + wire _GEN_46 = _T_186 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67] + wire _GEN_63 = _T_175 ? 1'h0 : _GEN_46; // @[Conditional.scala 39:67] + wire _GEN_81 = _T_136 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67] + wire _GEN_97 = _T_101 ? 1'h0 : _GEN_81; // @[Conditional.scala 39:67] + wire buf_write_in = _T_49 ? _T_51 : _GEN_97; // @[Conditional.scala 40:58] + wire [2:0] _T_53 = buf_write_in ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 169:26] + wire _T_103 = master_opc == 3'h0; // @[axi4_to_ahb.scala 182:61] + wire _T_104 = master_valid & _T_103; // @[axi4_to_ahb.scala 182:41] + wire [2:0] _T_106 = _T_104 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 182:26] + wire _T_124 = _T_106 == 3'h6; // @[axi4_to_ahb.scala 186:174] + wire _T_125 = _T_111 & _T_124; // @[axi4_to_ahb.scala 186:88] + wire _T_137 = ~ahb_hresp_q; // @[axi4_to_ahb.scala 194:39] + wire _T_138 = ahb_hready_q & _T_137; // @[axi4_to_ahb.scala 194:37] + wire _T_141 = master_valid & _T_51; // @[axi4_to_ahb.scala 194:70] + wire _T_142 = ~_T_141; // @[axi4_to_ahb.scala 194:55] + wire _T_143 = _T_138 & _T_142; // @[axi4_to_ahb.scala 194:53] + wire _T_285 = buf_state_en & _T_137; // @[axi4_to_ahb.scala 240:36] + wire _GEN_4 = _T_281 & _T_285; // @[Conditional.scala 39:67] + wire _GEN_26 = _T_188 ? 1'h0 : _GEN_4; // @[Conditional.scala 39:67] + wire _GEN_45 = _T_186 ? 1'h0 : _GEN_26; // @[Conditional.scala 39:67] + wire _GEN_62 = _T_175 ? 1'h0 : _GEN_45; // @[Conditional.scala 39:67] + wire _GEN_66 = _T_136 ? _T_143 : _GEN_62; // @[Conditional.scala 39:67] + wire _GEN_86 = _T_101 ? _T_125 : _GEN_66; // @[Conditional.scala 39:67] + wire master_ready = _T_49 | _GEN_86; // @[Conditional.scala 40:58] + wire _T_149 = master_valid & master_ready; // @[axi4_to_ahb.scala 196:82] + wire _T_152 = _T_149 & _T_103; // @[axi4_to_ahb.scala 196:97] + wire [2:0] _T_154 = _T_152 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 196:67] + wire [2:0] _T_155 = ahb_hresp_q ? 3'h7 : _T_154; // @[axi4_to_ahb.scala 196:26] + wire [2:0] _T_293 = _T_51 ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 241:99] + wire [2:0] _T_294 = master_valid ? _T_293 : 3'h0; // @[axi4_to_ahb.scala 241:65] + wire [2:0] _T_295 = ahb_hresp_q ? 3'h5 : _T_294; // @[axi4_to_ahb.scala 241:26] + wire [2:0] _GEN_5 = _T_281 ? _T_295 : 3'h0; // @[Conditional.scala 39:67] + wire [2:0] _GEN_18 = _T_188 ? 3'h4 : _GEN_5; // @[Conditional.scala 39:67] + wire [2:0] _GEN_34 = _T_186 ? 3'h5 : _GEN_18; // @[Conditional.scala 39:67] + wire [2:0] _GEN_50 = _T_175 ? 3'h3 : _GEN_34; // @[Conditional.scala 39:67] + wire [2:0] _GEN_68 = _T_136 ? _T_155 : _GEN_50; // @[Conditional.scala 39:67] + wire [2:0] _GEN_82 = _T_101 ? _T_106 : _GEN_68; // @[Conditional.scala 39:67] + wire [2:0] buf_nxtstate = _T_49 ? _T_53 : _GEN_82; // @[Conditional.scala 40:58] + reg [2:0] wrbuf_tag; // @[Reg.scala 27:20] + reg [31:0] wrbuf_addr; // @[lib.scala 374:16] + wire [31:0] master_addr = wr_cmd_vld ? wrbuf_addr : io_axi_ar_bits_addr; // @[axi4_to_ahb.scala 143:21] + reg [2:0] wrbuf_size; // @[Reg.scala 27:20] + wire [2:0] master_size = wr_cmd_vld ? wrbuf_size : io_axi_ar_bits_size; // @[axi4_to_ahb.scala 144:21] + reg [7:0] wrbuf_byteen; // @[Reg.scala 27:20] + reg [63:0] wrbuf_data; // @[lib.scala 374:16] + wire _T_358 = buf_nxtstate != 3'h5; // @[axi4_to_ahb.scala 251:55] + wire _T_359 = buf_state_en & _T_358; // @[axi4_to_ahb.scala 251:39] + wire _GEN_14 = _T_281 ? _T_359 : _T_440; // @[Conditional.scala 39:67] + wire _GEN_33 = _T_188 ? 1'h0 : _GEN_14; // @[Conditional.scala 39:67] + wire _GEN_49 = _T_186 ? 1'h0 : _GEN_33; // @[Conditional.scala 39:67] + wire _GEN_52 = _T_175 ? buf_state_en : _GEN_49; // @[Conditional.scala 39:67] + wire _GEN_73 = _T_136 ? _T_285 : _GEN_52; // @[Conditional.scala 39:67] + wire _GEN_94 = _T_101 ? 1'h0 : _GEN_73; // @[Conditional.scala 39:67] + wire slave_valid_pre = _T_49 ? 1'h0 : _GEN_94; // @[Conditional.scala 40:58] + wire buf_clk = rvclkhdr_6_io_l1clk; // @[axi4_to_ahb.scala 118:21 axi4_to_ahb.scala 332:12] + reg slvbuf_write; // @[Reg.scala 27:20] + wire [1:0] _T_596 = slvbuf_write ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 285:23] + reg slvbuf_error; // @[Reg.scala 27:20] + wire [1:0] _T_598 = slvbuf_error ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_599 = _T_598 & 2'h2; // @[axi4_to_ahb.scala 285:88] + wire [3:0] slave_opc = {_T_596,_T_599}; // @[Cat.scala 29:58] + wire [1:0] _T_30 = slave_opc[1] ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 150:55] + reg [2:0] slvbuf_tag; // @[Reg.scala 27:20] + wire _T_35 = slave_opc[3:2] == 2'h0; // @[axi4_to_ahb.scala 153:66] + reg [31:0] last_bus_addr; // @[Reg.scala 27:20] + wire [63:0] _T_603 = {last_bus_addr,last_bus_addr}; // @[Cat.scala 29:58] + wire _T_604 = buf_state == 3'h5; // @[axi4_to_ahb.scala 286:91] + reg [63:0] buf_data; // @[lib.scala 374:16] + wire ahbm_data_clk = rvclkhdr_9_io_l1clk; // @[axi4_to_ahb.scala 26:27 axi4_to_ahb.scala 335:17] + reg [63:0] ahb_hrdata_q; // @[axi4_to_ahb.scala 325:57] + wire [63:0] _T_607 = _T_604 ? buf_data : ahb_hrdata_q; // @[axi4_to_ahb.scala 286:79] + wire _T_44 = io_axi_aw_valid & io_axi_aw_ready; // @[axi4_to_ahb.scala 160:57] + wire _T_45 = io_axi_w_valid & io_axi_w_ready; // @[axi4_to_ahb.scala 160:94] + wire _T_46 = _T_44 | _T_45; // @[axi4_to_ahb.scala 160:76] + wire _T_55 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 172:54] + wire _T_56 = buf_state_en & _T_55; // @[axi4_to_ahb.scala 172:38] + wire [2:0] _T_87 = wrbuf_byteen[6] ? 3'h6 : 3'h7; // @[Mux.scala 98:16] + wire [2:0] _T_88 = wrbuf_byteen[5] ? 3'h5 : _T_87; // @[Mux.scala 98:16] + wire [2:0] _T_89 = wrbuf_byteen[4] ? 3'h4 : _T_88; // @[Mux.scala 98:16] + wire [2:0] _T_90 = wrbuf_byteen[3] ? 3'h3 : _T_89; // @[Mux.scala 98:16] + wire [2:0] _T_91 = wrbuf_byteen[2] ? 3'h2 : _T_90; // @[Mux.scala 98:16] + wire [2:0] _T_92 = wrbuf_byteen[1] ? 3'h1 : _T_91; // @[Mux.scala 98:16] + wire [2:0] _T_93 = wrbuf_byteen[0] ? 3'h0 : _T_92; // @[Mux.scala 98:16] + wire [2:0] _T_95 = buf_write_in ? _T_93 : master_addr[2:0]; // @[axi4_to_ahb.scala 175:30] + wire _T_96 = buf_nxtstate == 3'h1; // @[axi4_to_ahb.scala 177:51] + wire _T_126 = master_ready & master_valid; // @[axi4_to_ahb.scala 188:33] + wire _T_162 = buf_nxtstate == 3'h6; // @[axi4_to_ahb.scala 203:64] + wire _T_163 = _T_126 & _T_162; // @[axi4_to_ahb.scala 203:48] + wire _T_164 = _T_163 & buf_state_en; // @[axi4_to_ahb.scala 203:79] + wire _T_349 = buf_state_en & buf_write_in; // @[axi4_to_ahb.scala 249:33] + wire _T_351 = _T_349 & _T_55; // @[axi4_to_ahb.scala 249:48] + wire _GEN_12 = _T_281 & _T_351; // @[Conditional.scala 39:67] + wire _GEN_32 = _T_188 ? 1'h0 : _GEN_12; // @[Conditional.scala 39:67] + wire _GEN_48 = _T_186 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67] + wire _GEN_65 = _T_175 ? 1'h0 : _GEN_48; // @[Conditional.scala 39:67] + wire _GEN_75 = _T_136 ? _T_164 : _GEN_65; // @[Conditional.scala 39:67] + wire _GEN_88 = _T_101 ? _T_126 : _GEN_75; // @[Conditional.scala 39:67] + wire bypass_en = _T_49 ? buf_state_en : _GEN_88; // @[Conditional.scala 40:58] + wire [1:0] _T_99 = bypass_en ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_100 = _T_99 & 2'h2; // @[axi4_to_ahb.scala 178:49] + wire _T_112 = ~master_valid; // @[axi4_to_ahb.scala 184:34] + wire _T_113 = buf_state_en & _T_112; // @[axi4_to_ahb.scala 184:32] + reg [31:0] buf_addr; // @[lib.scala 374:16] + wire [2:0] _T_130 = bypass_en ? master_addr[2:0] : buf_addr[2:0]; // @[axi4_to_ahb.scala 189:30] + wire _T_131 = ~buf_state_en; // @[axi4_to_ahb.scala 190:48] + wire _T_132 = _T_131 | bypass_en; // @[axi4_to_ahb.scala 190:62] + wire [1:0] _T_134 = _T_132 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_135 = 2'h2 & _T_134; // @[axi4_to_ahb.scala 190:36] + wire _T_169 = buf_nxtstate != 3'h6; // @[axi4_to_ahb.scala 205:63] + wire _T_170 = _T_169 & buf_state_en; // @[axi4_to_ahb.scala 205:78] + wire _T_171 = ~_T_170; // @[axi4_to_ahb.scala 205:47] + wire [1:0] _T_173 = _T_171 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_174 = 2'h2 & _T_173; // @[axi4_to_ahb.scala 205:36] + wire [1:0] _T_184 = _T_131 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_185 = 2'h2 & _T_184; // @[axi4_to_ahb.scala 215:41] + reg [2:0] buf_cmd_byte_ptrQ; // @[Reg.scala 27:20] + reg [7:0] buf_byteen; // @[Reg.scala 27:20] + wire [2:0] _T_197 = buf_cmd_byte_ptrQ + 3'h1; // @[axi4_to_ahb.scala 135:52] + wire _T_200 = 3'h0 >= _T_197; // @[axi4_to_ahb.scala 136:62] + wire _T_201 = buf_byteen[0] & _T_200; // @[axi4_to_ahb.scala 136:48] + wire _T_203 = 3'h1 >= _T_197; // @[axi4_to_ahb.scala 136:62] + wire _T_204 = buf_byteen[1] & _T_203; // @[axi4_to_ahb.scala 136:48] + wire _T_206 = 3'h2 >= _T_197; // @[axi4_to_ahb.scala 136:62] + wire _T_207 = buf_byteen[2] & _T_206; // @[axi4_to_ahb.scala 136:48] + wire _T_209 = 3'h3 >= _T_197; // @[axi4_to_ahb.scala 136:62] + wire _T_210 = buf_byteen[3] & _T_209; // @[axi4_to_ahb.scala 136:48] + wire _T_212 = 3'h4 >= _T_197; // @[axi4_to_ahb.scala 136:62] + wire _T_213 = buf_byteen[4] & _T_212; // @[axi4_to_ahb.scala 136:48] + wire _T_215 = 3'h5 >= _T_197; // @[axi4_to_ahb.scala 136:62] + wire _T_216 = buf_byteen[5] & _T_215; // @[axi4_to_ahb.scala 136:48] + wire _T_218 = 3'h6 >= _T_197; // @[axi4_to_ahb.scala 136:62] + wire _T_219 = buf_byteen[6] & _T_218; // @[axi4_to_ahb.scala 136:48] + wire [2:0] _T_224 = _T_219 ? 3'h6 : 3'h7; // @[Mux.scala 98:16] + wire [2:0] _T_225 = _T_216 ? 3'h5 : _T_224; // @[Mux.scala 98:16] + wire [2:0] _T_226 = _T_213 ? 3'h4 : _T_225; // @[Mux.scala 98:16] + wire [2:0] _T_227 = _T_210 ? 3'h3 : _T_226; // @[Mux.scala 98:16] + wire [2:0] _T_228 = _T_207 ? 3'h2 : _T_227; // @[Mux.scala 98:16] + wire [2:0] _T_229 = _T_204 ? 3'h1 : _T_228; // @[Mux.scala 98:16] + wire [2:0] _T_230 = _T_201 ? 3'h0 : _T_229; // @[Mux.scala 98:16] + wire [2:0] _T_231 = trxn_done ? _T_230 : buf_cmd_byte_ptrQ; // @[axi4_to_ahb.scala 233:30] + wire _T_232 = buf_cmd_byte_ptrQ == 3'h7; // @[axi4_to_ahb.scala 234:65] + reg buf_aligned; // @[Reg.scala 27:20] + wire _T_233 = buf_aligned | _T_232; // @[axi4_to_ahb.scala 234:44] + wire [7:0] _T_271 = buf_byteen >> _T_230; // @[axi4_to_ahb.scala 234:92] + wire _T_273 = ~_T_271[0]; // @[axi4_to_ahb.scala 234:163] + wire _T_274 = _T_233 | _T_273; // @[axi4_to_ahb.scala 234:79] + wire _T_275 = trxn_done & _T_274; // @[axi4_to_ahb.scala 234:29] + wire _T_346 = _T_232 | _T_273; // @[axi4_to_ahb.scala 248:38] + wire _T_347 = _T_109 & _T_346; // @[axi4_to_ahb.scala 247:80] + wire _T_348 = ahb_hresp_q | _T_347; // @[axi4_to_ahb.scala 247:34] + wire _GEN_11 = _T_281 & _T_348; // @[Conditional.scala 39:67] + wire _GEN_24 = _T_188 ? _T_275 : _GEN_11; // @[Conditional.scala 39:67] + wire _GEN_43 = _T_186 ? 1'h0 : _GEN_24; // @[Conditional.scala 39:67] + wire _GEN_61 = _T_175 ? 1'h0 : _GEN_43; // @[Conditional.scala 39:67] + wire _GEN_74 = _T_136 ? _T_113 : _GEN_61; // @[Conditional.scala 39:67] + wire _GEN_84 = _T_101 ? _T_113 : _GEN_74; // @[Conditional.scala 39:67] + wire cmd_done = _T_49 ? 1'h0 : _GEN_84; // @[Conditional.scala 40:58] + wire _T_276 = cmd_done | cmd_doneQ; // @[axi4_to_ahb.scala 235:47] + wire _T_277 = ~_T_276; // @[axi4_to_ahb.scala 235:36] + wire [1:0] _T_279 = _T_277 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_280 = _T_279 & 2'h2; // @[axi4_to_ahb.scala 235:61] + wire _T_300 = _T_55 | _T_96; // @[axi4_to_ahb.scala 245:62] + wire _T_301 = buf_state_en & _T_300; // @[axi4_to_ahb.scala 245:33] + wire _T_354 = _T_277 | bypass_en; // @[axi4_to_ahb.scala 250:61] + wire [1:0] _T_356 = _T_354 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_357 = _T_356 & 2'h2; // @[axi4_to_ahb.scala 250:75] + wire _T_364 = trxn_done | bypass_en; // @[axi4_to_ahb.scala 253:40] + wire [2:0] _T_439 = bypass_en ? _T_93 : _T_231; // @[axi4_to_ahb.scala 254:30] + wire _GEN_6 = _T_281 & ahb_hresp_q; // @[Conditional.scala 39:67] + wire _GEN_7 = _T_281 ? buf_state_en : _T_440; // @[Conditional.scala 39:67] + wire _GEN_9 = _T_281 & _T_301; // @[Conditional.scala 39:67] + wire _GEN_30 = _T_188 ? 1'h0 : _GEN_9; // @[Conditional.scala 39:67] + wire _GEN_47 = _T_186 ? 1'h0 : _GEN_30; // @[Conditional.scala 39:67] + wire _GEN_64 = _T_175 ? 1'h0 : _GEN_47; // @[Conditional.scala 39:67] + wire _GEN_67 = _T_136 ? _T_152 : _GEN_64; // @[Conditional.scala 39:67] + wire _GEN_87 = _T_101 ? master_ready : _GEN_67; // @[Conditional.scala 39:67] + wire buf_wr_en = _T_49 ? buf_state_en : _GEN_87; // @[Conditional.scala 40:58] + wire _GEN_10 = _T_281 & buf_wr_en; // @[Conditional.scala 39:67] + wire [1:0] _GEN_13 = _T_281 ? _T_357 : 2'h0; // @[Conditional.scala 39:67] + wire _GEN_16 = _T_281 & _T_364; // @[Conditional.scala 39:67] + wire [2:0] _GEN_17 = _T_281 ? _T_439 : 3'h0; // @[Conditional.scala 39:67] + wire _GEN_21 = _T_188 ? buf_state_en : _GEN_16; // @[Conditional.scala 39:67] + wire _GEN_22 = _T_188 & buf_state_en; // @[Conditional.scala 39:67] + wire [2:0] _GEN_23 = _T_188 ? _T_231 : _GEN_17; // @[Conditional.scala 39:67] + wire [1:0] _GEN_25 = _T_188 ? _T_280 : _GEN_13; // @[Conditional.scala 39:67] + wire _GEN_28 = _T_188 ? 1'h0 : _GEN_7; // @[Conditional.scala 39:67] + wire _GEN_31 = _T_188 ? 1'h0 : _GEN_10; // @[Conditional.scala 39:67] + wire _GEN_36 = _T_186 ? buf_state_en : _GEN_31; // @[Conditional.scala 39:67] + wire _GEN_38 = _T_186 ? buf_state_en : _GEN_28; // @[Conditional.scala 39:67] + wire _GEN_39 = _T_186 ? buf_state_en : _GEN_22; // @[Conditional.scala 39:67] + wire _GEN_41 = _T_186 ? 1'h0 : _GEN_21; // @[Conditional.scala 39:67] + wire [2:0] _GEN_42 = _T_186 ? 3'h0 : _GEN_23; // @[Conditional.scala 39:67] + wire [1:0] _GEN_44 = _T_186 ? 2'h0 : _GEN_25; // @[Conditional.scala 39:67] + wire _GEN_53 = _T_175 ? buf_state_en : _GEN_39; // @[Conditional.scala 39:67] + wire [2:0] _GEN_54 = _T_175 ? buf_addr[2:0] : _GEN_42; // @[Conditional.scala 39:67] + wire [1:0] _GEN_55 = _T_175 ? _T_185 : _GEN_44; // @[Conditional.scala 39:67] + wire _GEN_56 = _T_175 ? 1'h0 : _GEN_36; // @[Conditional.scala 39:67] + wire _GEN_58 = _T_175 ? 1'h0 : _GEN_38; // @[Conditional.scala 39:67] + wire _GEN_60 = _T_175 ? 1'h0 : _GEN_41; // @[Conditional.scala 39:67] + wire _GEN_70 = _T_136 ? buf_state_en : _GEN_56; // @[Conditional.scala 39:67] + wire _GEN_72 = _T_136 ? buf_state_en : _GEN_58; // @[Conditional.scala 39:67] + wire [2:0] _GEN_76 = _T_136 ? _T_130 : _GEN_54; // @[Conditional.scala 39:67] + wire [1:0] _GEN_77 = _T_136 ? _T_174 : _GEN_55; // @[Conditional.scala 39:67] + wire _GEN_78 = _T_136 ? buf_wr_en : _GEN_53; // @[Conditional.scala 39:67] + wire _GEN_80 = _T_136 ? 1'h0 : _GEN_60; // @[Conditional.scala 39:67] + wire _GEN_85 = _T_101 ? buf_state_en : _GEN_78; // @[Conditional.scala 39:67] + wire [2:0] _GEN_89 = _T_101 ? _T_130 : _GEN_76; // @[Conditional.scala 39:67] + wire [1:0] _GEN_90 = _T_101 ? _T_135 : _GEN_77; // @[Conditional.scala 39:67] + wire _GEN_91 = _T_101 ? 1'h0 : _GEN_70; // @[Conditional.scala 39:67] + wire _GEN_93 = _T_101 ? 1'h0 : _GEN_72; // @[Conditional.scala 39:67] + wire _GEN_96 = _T_101 ? 1'h0 : _GEN_80; // @[Conditional.scala 39:67] + wire buf_data_wr_en = _T_49 ? _T_56 : _GEN_91; // @[Conditional.scala 40:58] + wire buf_cmd_byte_ptr_en = _T_49 ? buf_state_en : _GEN_96; // @[Conditional.scala 40:58] + wire [2:0] buf_cmd_byte_ptr = _T_49 ? _T_95 : _GEN_89; // @[Conditional.scala 40:58] + wire slvbuf_wr_en = _T_49 ? 1'h0 : _GEN_85; // @[Conditional.scala 40:58] + wire slvbuf_error_en = _T_49 ? 1'h0 : _GEN_93; // @[Conditional.scala 40:58] + wire _T_535 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 271:24] + wire _T_536 = _T_103 | _T_535; // @[axi4_to_ahb.scala 270:48] + wire _T_538 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 271:54] + wire _T_539 = _T_536 | _T_538; // @[axi4_to_ahb.scala 271:33] + wire _T_541 = master_size[1:0] == 2'h2; // @[axi4_to_ahb.scala 271:93] + wire _T_542 = _T_539 | _T_541; // @[axi4_to_ahb.scala 271:72] + wire _T_544 = master_size[1:0] == 2'h3; // @[axi4_to_ahb.scala 272:25] + wire _T_546 = wrbuf_byteen == 8'h3; // @[axi4_to_ahb.scala 272:62] + wire _T_548 = wrbuf_byteen == 8'hc; // @[axi4_to_ahb.scala 272:97] + wire _T_549 = _T_546 | _T_548; // @[axi4_to_ahb.scala 272:74] + wire _T_551 = wrbuf_byteen == 8'h30; // @[axi4_to_ahb.scala 272:132] + wire _T_552 = _T_549 | _T_551; // @[axi4_to_ahb.scala 272:109] + wire _T_554 = wrbuf_byteen == 8'hc0; // @[axi4_to_ahb.scala 272:168] + wire _T_555 = _T_552 | _T_554; // @[axi4_to_ahb.scala 272:145] + wire _T_557 = wrbuf_byteen == 8'hf; // @[axi4_to_ahb.scala 273:28] + wire _T_558 = _T_555 | _T_557; // @[axi4_to_ahb.scala 272:181] + wire _T_560 = wrbuf_byteen == 8'hf0; // @[axi4_to_ahb.scala 273:63] + wire _T_561 = _T_558 | _T_560; // @[axi4_to_ahb.scala 273:40] + wire _T_563 = wrbuf_byteen == 8'hff; // @[axi4_to_ahb.scala 273:99] + wire _T_564 = _T_561 | _T_563; // @[axi4_to_ahb.scala 273:76] + wire _T_565 = _T_544 & _T_564; // @[axi4_to_ahb.scala 272:38] + wire buf_aligned_in = _T_542 | _T_565; // @[axi4_to_ahb.scala 271:106] + wire _T_444 = buf_aligned_in & _T_51; // @[axi4_to_ahb.scala 265:60] + wire [2:0] _T_461 = _T_548 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_462 = 3'h2 & _T_461; // @[axi4_to_ahb.scala 128:15] + wire _T_468 = _T_560 | _T_546; // @[axi4_to_ahb.scala 129:56] + wire [2:0] _T_470 = _T_468 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_471 = 3'h4 & _T_470; // @[axi4_to_ahb.scala 129:15] + wire [2:0] _T_472 = _T_462 | _T_471; // @[axi4_to_ahb.scala 128:63] + wire [2:0] _T_476 = _T_554 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_477 = 3'h6 & _T_476; // @[axi4_to_ahb.scala 130:15] + wire [2:0] _T_478 = _T_472 | _T_477; // @[axi4_to_ahb.scala 129:96] + wire [2:0] _T_485 = _T_444 ? _T_478 : master_addr[2:0]; // @[axi4_to_ahb.scala 265:43] + wire _T_489 = buf_state == 3'h3; // @[axi4_to_ahb.scala 268:33] + wire _T_495 = buf_aligned_in & _T_544; // @[axi4_to_ahb.scala 269:38] + wire _T_498 = _T_495 & _T_51; // @[axi4_to_ahb.scala 269:71] + wire [1:0] _T_504 = _T_563 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire _T_510 = _T_560 | _T_557; // @[axi4_to_ahb.scala 122:55] + wire [1:0] _T_512 = _T_510 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_513 = 2'h2 & _T_512; // @[axi4_to_ahb.scala 122:16] + wire [1:0] _T_514 = _T_504 | _T_513; // @[axi4_to_ahb.scala 121:64] + wire _T_519 = _T_554 | _T_551; // @[axi4_to_ahb.scala 123:60] + wire _T_522 = _T_519 | _T_548; // @[axi4_to_ahb.scala 123:89] + wire _T_525 = _T_522 | _T_546; // @[axi4_to_ahb.scala 123:123] + wire [1:0] _T_527 = _T_525 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_528 = 2'h1 & _T_527; // @[axi4_to_ahb.scala 123:21] + wire [1:0] _T_529 = _T_514 | _T_528; // @[axi4_to_ahb.scala 122:93] + wire [1:0] _T_531 = _T_498 ? _T_529 : master_size[1:0]; // @[axi4_to_ahb.scala 269:21] + wire [31:0] _T_570 = {master_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] + wire [31:0] _T_573 = {buf_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] + wire [1:0] _T_577 = buf_aligned_in ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [2:0] buf_size_in = {{1'd0}, _T_531}; // @[axi4_to_ahb.scala 269:15] + wire [1:0] _T_579 = _T_577 & buf_size_in[1:0]; // @[axi4_to_ahb.scala 276:81] + wire [2:0] _T_580 = {1'h0,_T_579}; // @[Cat.scala 29:58] + wire [1:0] _T_582 = buf_aligned ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + reg [1:0] buf_size; // @[Reg.scala 27:20] + wire [1:0] _T_584 = _T_582 & buf_size; // @[axi4_to_ahb.scala 276:138] + wire [2:0] _T_585 = {1'h0,_T_584}; // @[Cat.scala 29:58] + reg buf_write; // @[Reg.scala 27:20] + wire _T_611 = io_ahb_out_htrans != 2'h0; // @[axi4_to_ahb.scala 289:44] + wire _T_612 = _T_611 & io_ahb_in_hready; // @[axi4_to_ahb.scala 289:56] + wire last_addr_en = _T_612 & io_ahb_out_hwrite; // @[axi4_to_ahb.scala 289:75] + wire wrbuf_en = _T_44 & master_ready; // @[axi4_to_ahb.scala 291:49] + wire wrbuf_data_en = _T_45 & master_ready; // @[axi4_to_ahb.scala 292:52] + wire wrbuf_cmd_sent = _T_149 & _T_51; // @[axi4_to_ahb.scala 293:49] + wire _T_622 = ~wrbuf_en; // @[axi4_to_ahb.scala 294:33] + wire wrbuf_rst = wrbuf_cmd_sent & _T_622; // @[axi4_to_ahb.scala 294:31] + wire _T_624 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 296:36] + wire _T_625 = wrbuf_vld & _T_624; // @[axi4_to_ahb.scala 296:34] + wire _T_626 = ~_T_625; // @[axi4_to_ahb.scala 296:22] + wire _T_629 = wrbuf_data_vld & _T_624; // @[axi4_to_ahb.scala 297:38] + wire _T_630 = ~_T_629; // @[axi4_to_ahb.scala 297:21] + wire _T_633 = ~wr_cmd_vld; // @[axi4_to_ahb.scala 298:22] + wire _T_636 = wrbuf_en | wrbuf_vld; // @[axi4_to_ahb.scala 301:55] + wire _T_637 = ~wrbuf_rst; // @[axi4_to_ahb.scala 301:91] + wire _T_641 = wrbuf_data_en | wrbuf_data_vld; // @[axi4_to_ahb.scala 302:55] + reg [2:0] buf_tag; // @[Reg.scala 27:20] + wire _T_691 = ~slave_valid_pre; // @[axi4_to_ahb.scala 319:92] + wire _T_704 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 327:43] + wire _T_705 = _T_704 | io_clk_override; // @[axi4_to_ahb.scala 327:58] + wire _T_708 = io_ahb_in_hready & io_ahb_out_htrans[1]; // @[axi4_to_ahb.scala 328:57] + wire _T_709 = _T_708 | io_clk_override; // @[axi4_to_ahb.scala 328:81] + wire _T_711 = buf_state != 3'h0; // @[axi4_to_ahb.scala 329:50] + wire _T_712 = _T_711 | io_clk_override; // @[axi4_to_ahb.scala 329:60] + rvclkhdr rvclkhdr ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) + ); + rvclkhdr rvclkhdr_1 ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_1_io_l1clk), + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en), + .io_scan_mode(rvclkhdr_1_io_scan_mode) + ); + rvclkhdr rvclkhdr_2 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_2_io_l1clk), + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en), + .io_scan_mode(rvclkhdr_2_io_scan_mode) + ); + rvclkhdr rvclkhdr_3 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_3_io_l1clk), + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en), + .io_scan_mode(rvclkhdr_3_io_scan_mode) + ); + rvclkhdr rvclkhdr_4 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_4_io_l1clk), + .io_clk(rvclkhdr_4_io_clk), + .io_en(rvclkhdr_4_io_en), + .io_scan_mode(rvclkhdr_4_io_scan_mode) + ); + rvclkhdr rvclkhdr_5 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_5_io_l1clk), + .io_clk(rvclkhdr_5_io_clk), + .io_en(rvclkhdr_5_io_en), + .io_scan_mode(rvclkhdr_5_io_scan_mode) + ); + rvclkhdr rvclkhdr_6 ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_6_io_l1clk), + .io_clk(rvclkhdr_6_io_clk), + .io_en(rvclkhdr_6_io_en), + .io_scan_mode(rvclkhdr_6_io_scan_mode) + ); + rvclkhdr rvclkhdr_7 ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_7_io_l1clk), + .io_clk(rvclkhdr_7_io_clk), + .io_en(rvclkhdr_7_io_en), + .io_scan_mode(rvclkhdr_7_io_scan_mode) + ); + rvclkhdr rvclkhdr_8 ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_8_io_l1clk), + .io_clk(rvclkhdr_8_io_clk), + .io_en(rvclkhdr_8_io_en), + .io_scan_mode(rvclkhdr_8_io_scan_mode) + ); + rvclkhdr rvclkhdr_9 ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_9_io_l1clk), + .io_clk(rvclkhdr_9_io_clk), + .io_en(rvclkhdr_9_io_en), + .io_scan_mode(rvclkhdr_9_io_scan_mode) + ); + assign io_axi_aw_ready = _T_626 & master_ready; // @[axi4_to_ahb.scala 296:19] + assign io_axi_w_ready = _T_630 & master_ready; // @[axi4_to_ahb.scala 297:18] + assign io_axi_b_valid = slave_valid_pre & slave_opc[3]; // @[axi4_to_ahb.scala 149:18] + assign io_axi_b_bits_id = slvbuf_tag; // @[axi4_to_ahb.scala 151:20] + assign io_axi_ar_ready = _T_633 & master_ready; // @[axi4_to_ahb.scala 298:19] + assign io_axi_r_valid = slave_valid_pre & _T_35; // @[axi4_to_ahb.scala 153:18] + assign io_axi_r_bits_id = slvbuf_tag; // @[axi4_to_ahb.scala 155:20] + assign io_axi_r_bits_data = slvbuf_error ? _T_603 : _T_607; // @[axi4_to_ahb.scala 156:22] + assign io_axi_r_bits_resp = slave_opc[0] ? 2'h2 : _T_30; // @[axi4_to_ahb.scala 154:22] + assign io_ahb_out_haddr = bypass_en ? _T_570 : _T_573; // @[axi4_to_ahb.scala 275:20] + assign io_ahb_out_hsize = bypass_en ? _T_580 : _T_585; // @[axi4_to_ahb.scala 276:20] + assign io_ahb_out_htrans = _T_49 ? _T_100 : _GEN_90; // @[axi4_to_ahb.scala 22:21 axi4_to_ahb.scala 178:25 axi4_to_ahb.scala 190:25 axi4_to_ahb.scala 205:25 axi4_to_ahb.scala 215:25 axi4_to_ahb.scala 235:25 axi4_to_ahb.scala 250:25] + assign io_ahb_out_hwrite = bypass_en ? _T_51 : buf_write; // @[axi4_to_ahb.scala 281:21] + assign io_ahb_out_hwdata = buf_data; // @[axi4_to_ahb.scala 282:21] + assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_io_en = io_bus_clk_en; // @[lib.scala 345:16] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_1_io_en = io_bus_clk_en & _T_46; // @[lib.scala 345:16] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_2_io_clk = rvclkhdr_io_l1clk; // @[lib.scala 370:18] + assign rvclkhdr_2_io_en = _T_44 & master_ready; // @[lib.scala 371:17] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_3_io_clk = rvclkhdr_io_l1clk; // @[lib.scala 370:18] + assign rvclkhdr_3_io_en = _T_45 & master_ready; // @[lib.scala 371:17] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_4_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_4_io_en = buf_wr_en & io_bus_clk_en; // @[lib.scala 371:17] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_5_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_5_io_en = buf_data_wr_en & io_bus_clk_en; // @[lib.scala 371:17] + assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_6_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_6_io_en = io_bus_clk_en & _T_705; // @[lib.scala 345:16] + assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_7_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_7_io_en = io_bus_clk_en; // @[lib.scala 345:16] + assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_8_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_8_io_en = io_bus_clk_en & _T_709; // @[lib.scala 345:16] + assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_9_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_9_io_en = io_bus_clk_en & _T_712; // @[lib.scala 345:16] + assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + buf_state = _RAND_0[2:0]; + _RAND_1 = {1{`RANDOM}}; + wrbuf_vld = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + wrbuf_data_vld = _RAND_2[0:0]; + _RAND_3 = {1{`RANDOM}}; + ahb_hready_q = _RAND_3[0:0]; + _RAND_4 = {1{`RANDOM}}; + ahb_htrans_q = _RAND_4[1:0]; + _RAND_5 = {1{`RANDOM}}; + ahb_hwrite_q = _RAND_5[0:0]; + _RAND_6 = {1{`RANDOM}}; + ahb_hresp_q = _RAND_6[0:0]; + _RAND_7 = {1{`RANDOM}}; + cmd_doneQ = _RAND_7[0:0]; + _RAND_8 = {1{`RANDOM}}; + wrbuf_tag = _RAND_8[2:0]; + _RAND_9 = {1{`RANDOM}}; + wrbuf_addr = _RAND_9[31:0]; + _RAND_10 = {1{`RANDOM}}; + wrbuf_size = _RAND_10[2:0]; + _RAND_11 = {1{`RANDOM}}; + wrbuf_byteen = _RAND_11[7:0]; + _RAND_12 = {2{`RANDOM}}; + wrbuf_data = _RAND_12[63:0]; + _RAND_13 = {1{`RANDOM}}; + slvbuf_write = _RAND_13[0:0]; + _RAND_14 = {1{`RANDOM}}; + slvbuf_error = _RAND_14[0:0]; + _RAND_15 = {1{`RANDOM}}; + slvbuf_tag = _RAND_15[2:0]; + _RAND_16 = {1{`RANDOM}}; + last_bus_addr = _RAND_16[31:0]; + _RAND_17 = {2{`RANDOM}}; + buf_data = _RAND_17[63:0]; + _RAND_18 = {2{`RANDOM}}; + ahb_hrdata_q = _RAND_18[63:0]; + _RAND_19 = {1{`RANDOM}}; + buf_addr = _RAND_19[31:0]; + _RAND_20 = {1{`RANDOM}}; + buf_cmd_byte_ptrQ = _RAND_20[2:0]; + _RAND_21 = {1{`RANDOM}}; + buf_byteen = _RAND_21[7:0]; + _RAND_22 = {1{`RANDOM}}; + buf_aligned = _RAND_22[0:0]; + _RAND_23 = {1{`RANDOM}}; + buf_size = _RAND_23[1:0]; + _RAND_24 = {1{`RANDOM}}; + buf_write = _RAND_24[0:0]; + _RAND_25 = {1{`RANDOM}}; + buf_tag = _RAND_25[2:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + buf_state = 3'h0; + end + if (reset) begin + wrbuf_vld = 1'h0; + end + if (reset) begin + wrbuf_data_vld = 1'h0; + end + if (reset) begin + ahb_hready_q = 1'h0; + end + if (reset) begin + ahb_htrans_q = 2'h0; + end + if (reset) begin + ahb_hwrite_q = 1'h0; + end + if (reset) begin + ahb_hresp_q = 1'h0; + end + if (reset) begin + cmd_doneQ = 1'h0; + end + if (reset) begin + wrbuf_tag = 3'h0; + end + if (reset) begin + wrbuf_addr = 32'h0; + end + if (reset) begin + wrbuf_size = 3'h0; + end + if (reset) begin + wrbuf_byteen = 8'h0; + end + if (reset) begin + wrbuf_data = 64'h0; + end + if (reset) begin + slvbuf_write = 1'h0; + end + if (reset) begin + slvbuf_error = 1'h0; + end + if (reset) begin + slvbuf_tag = 3'h0; + end + if (reset) begin + last_bus_addr = 32'h0; + end + if (reset) begin + buf_data = 64'h0; + end + if (reset) begin + ahb_hrdata_q = 64'h0; + end + if (reset) begin + buf_addr = 32'h0; + end + if (reset) begin + buf_cmd_byte_ptrQ = 3'h0; + end + if (reset) begin + buf_byteen = 8'h0; + end + if (reset) begin + buf_aligned = 1'h0; + end + if (reset) begin + buf_size = 2'h0; + end + if (reset) begin + buf_write = 1'h0; + end + if (reset) begin + buf_tag = 3'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge ahbm_clk or posedge reset) begin + if (reset) begin + buf_state <= 3'h0; + end else if (buf_state_en) begin + if (_T_49) begin + if (buf_write_in) begin + buf_state <= 3'h2; + end else begin + buf_state <= 3'h1; + end + end else if (_T_101) begin + if (_T_104) begin + buf_state <= 3'h6; + end else begin + buf_state <= 3'h3; + end + end else if (_T_136) begin + if (ahb_hresp_q) begin + buf_state <= 3'h7; + end else if (_T_152) begin + buf_state <= 3'h6; + end else begin + buf_state <= 3'h3; + end + end else if (_T_175) begin + buf_state <= 3'h3; + end else if (_T_186) begin + buf_state <= 3'h5; + end else if (_T_188) begin + buf_state <= 3'h4; + end else if (_T_281) begin + if (ahb_hresp_q) begin + buf_state <= 3'h5; + end else if (master_valid) begin + if (_T_51) begin + buf_state <= 3'h2; + end else begin + buf_state <= 3'h1; + end + end else begin + buf_state <= 3'h0; + end + end else begin + buf_state <= 3'h0; + end + end + end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + wrbuf_vld <= 1'h0; + end else begin + wrbuf_vld <= _T_636 & _T_637; + end + end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + wrbuf_data_vld <= 1'h0; + end else begin + wrbuf_data_vld <= _T_641 & _T_637; + end + end + always @(posedge ahbm_clk or posedge reset) begin + if (reset) begin + ahb_hready_q <= 1'h0; + end else begin + ahb_hready_q <= io_ahb_in_hready; + end + end + always @(posedge ahbm_clk or posedge reset) begin + if (reset) begin + ahb_htrans_q <= 2'h0; + end else begin + ahb_htrans_q <= io_ahb_out_htrans; + end + end + always @(posedge ahbm_addr_clk or posedge reset) begin + if (reset) begin + ahb_hwrite_q <= 1'h0; + end else begin + ahb_hwrite_q <= io_ahb_out_hwrite; + end + end + always @(posedge ahbm_clk or posedge reset) begin + if (reset) begin + ahb_hresp_q <= 1'h0; + end else begin + ahb_hresp_q <= io_ahb_in_hresp; + end + end + always @(posedge ahbm_clk or posedge reset) begin + if (reset) begin + cmd_doneQ <= 1'h0; + end else begin + cmd_doneQ <= _T_276 & _T_691; + end + end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + wrbuf_tag <= 3'h0; + end else if (wrbuf_en) begin + wrbuf_tag <= io_axi_aw_bits_id; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + wrbuf_addr <= 32'h0; + end else begin + wrbuf_addr <= io_axi_aw_bits_addr; + end + end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + wrbuf_size <= 3'h0; + end else if (wrbuf_en) begin + wrbuf_size <= io_axi_aw_bits_size; + end + end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + wrbuf_byteen <= 8'h0; + end else if (wrbuf_data_en) begin + wrbuf_byteen <= io_axi_w_bits_strb; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + wrbuf_data <= 64'h0; + end else begin + wrbuf_data <= io_axi_w_bits_data; + end + end + always @(posedge buf_clk or posedge reset) begin + if (reset) begin + slvbuf_write <= 1'h0; + end else if (slvbuf_wr_en) begin + slvbuf_write <= buf_write; + end + end + always @(posedge ahbm_clk or posedge reset) begin + if (reset) begin + slvbuf_error <= 1'h0; + end else if (slvbuf_error_en) begin + if (_T_49) begin + slvbuf_error <= 1'h0; + end else if (_T_101) begin + slvbuf_error <= 1'h0; + end else if (_T_136) begin + slvbuf_error <= ahb_hresp_q; + end else if (_T_175) begin + slvbuf_error <= 1'h0; + end else if (_T_186) begin + slvbuf_error <= ahb_hresp_q; + end else if (_T_188) begin + slvbuf_error <= 1'h0; + end else begin + slvbuf_error <= _GEN_6; + end + end + end + always @(posedge buf_clk or posedge reset) begin + if (reset) begin + slvbuf_tag <= 3'h0; + end else if (slvbuf_wr_en) begin + slvbuf_tag <= buf_tag; + end + end + always @(posedge ahbm_clk or posedge reset) begin + if (reset) begin + last_bus_addr <= 32'h0; + end else if (last_addr_en) begin + last_bus_addr <= io_ahb_out_haddr; + end + end + always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + if (reset) begin + buf_data <= 64'h0; + end else if (_T_489) begin + buf_data <= ahb_hrdata_q; + end else begin + buf_data <= wrbuf_data; + end + end + always @(posedge ahbm_data_clk or posedge reset) begin + if (reset) begin + ahb_hrdata_q <= 64'h0; + end else begin + ahb_hrdata_q <= io_ahb_in_hrdata; + end + end + always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + if (reset) begin + buf_addr <= 32'h0; + end else begin + buf_addr <= {master_addr[31:3],_T_485}; + end + end + always @(posedge ahbm_clk or posedge reset) begin + if (reset) begin + buf_cmd_byte_ptrQ <= 3'h0; + end else if (buf_cmd_byte_ptr_en) begin + if (_T_49) begin + if (buf_write_in) begin + if (wrbuf_byteen[0]) begin + buf_cmd_byte_ptrQ <= 3'h0; + end else if (wrbuf_byteen[1]) begin + buf_cmd_byte_ptrQ <= 3'h1; + end else if (wrbuf_byteen[2]) begin + buf_cmd_byte_ptrQ <= 3'h2; + end else if (wrbuf_byteen[3]) begin + buf_cmd_byte_ptrQ <= 3'h3; + end else if (wrbuf_byteen[4]) begin + buf_cmd_byte_ptrQ <= 3'h4; + end else if (wrbuf_byteen[5]) begin + buf_cmd_byte_ptrQ <= 3'h5; + end else if (wrbuf_byteen[6]) begin + buf_cmd_byte_ptrQ <= 3'h6; + end else begin + buf_cmd_byte_ptrQ <= 3'h7; + end + end else begin + buf_cmd_byte_ptrQ <= master_addr[2:0]; + end + end else if (_T_101) begin + if (bypass_en) begin + buf_cmd_byte_ptrQ <= master_addr[2:0]; + end else begin + buf_cmd_byte_ptrQ <= buf_addr[2:0]; + end + end else if (_T_136) begin + if (bypass_en) begin + buf_cmd_byte_ptrQ <= master_addr[2:0]; + end else begin + buf_cmd_byte_ptrQ <= buf_addr[2:0]; + end + end else if (_T_175) begin + buf_cmd_byte_ptrQ <= buf_addr[2:0]; + end else if (_T_186) begin + buf_cmd_byte_ptrQ <= 3'h0; + end else if (_T_188) begin + if (trxn_done) begin + if (_T_201) begin + buf_cmd_byte_ptrQ <= 3'h0; + end else if (_T_204) begin + buf_cmd_byte_ptrQ <= 3'h1; + end else if (_T_207) begin + buf_cmd_byte_ptrQ <= 3'h2; + end else if (_T_210) begin + buf_cmd_byte_ptrQ <= 3'h3; + end else if (_T_213) begin + buf_cmd_byte_ptrQ <= 3'h4; + end else if (_T_216) begin + buf_cmd_byte_ptrQ <= 3'h5; + end else if (_T_219) begin + buf_cmd_byte_ptrQ <= 3'h6; + end else begin + buf_cmd_byte_ptrQ <= 3'h7; + end + end + end else if (_T_281) begin + if (bypass_en) begin + if (wrbuf_byteen[0]) begin + buf_cmd_byte_ptrQ <= 3'h0; + end else if (wrbuf_byteen[1]) begin + buf_cmd_byte_ptrQ <= 3'h1; + end else if (wrbuf_byteen[2]) begin + buf_cmd_byte_ptrQ <= 3'h2; + end else if (wrbuf_byteen[3]) begin + buf_cmd_byte_ptrQ <= 3'h3; + end else if (wrbuf_byteen[4]) begin + buf_cmd_byte_ptrQ <= 3'h4; + end else if (wrbuf_byteen[5]) begin + buf_cmd_byte_ptrQ <= 3'h5; + end else if (wrbuf_byteen[6]) begin + buf_cmd_byte_ptrQ <= 3'h6; + end else begin + buf_cmd_byte_ptrQ <= 3'h7; + end + end else if (trxn_done) begin + if (_T_201) begin + buf_cmd_byte_ptrQ <= 3'h0; + end else if (_T_204) begin + buf_cmd_byte_ptrQ <= 3'h1; + end else if (_T_207) begin + buf_cmd_byte_ptrQ <= 3'h2; + end else if (_T_210) begin + buf_cmd_byte_ptrQ <= 3'h3; + end else if (_T_213) begin + buf_cmd_byte_ptrQ <= 3'h4; + end else if (_T_216) begin + buf_cmd_byte_ptrQ <= 3'h5; + end else if (_T_219) begin + buf_cmd_byte_ptrQ <= 3'h6; + end else begin + buf_cmd_byte_ptrQ <= 3'h7; + end + end + end else begin + buf_cmd_byte_ptrQ <= 3'h0; + end + end + end + always @(posedge buf_clk or posedge reset) begin + if (reset) begin + buf_byteen <= 8'h0; + end else if (buf_wr_en) begin + buf_byteen <= wrbuf_byteen; + end + end + always @(posedge buf_clk or posedge reset) begin + if (reset) begin + buf_aligned <= 1'h0; + end else if (buf_wr_en) begin + buf_aligned <= buf_aligned_in; + end + end + always @(posedge buf_clk or posedge reset) begin + if (reset) begin + buf_size <= 2'h0; + end else if (buf_wr_en) begin + buf_size <= buf_size_in[1:0]; + end + end always @(posedge buf_clk or posedge reset) begin if (reset) begin buf_write <= 1'h0; @@ -80282,7 +82283,7 @@ end // initial end always @(posedge buf_clk or posedge reset) begin if (reset) begin - buf_tag <= 1'h0; + buf_tag <= 3'h0; end else if (buf_wr_en) begin if (wr_cmd_vld) begin buf_tag <= wrbuf_tag; @@ -80293,22 +82294,51 @@ end // initial end endmodule module ahb_to_axi4( - input clock, - input reset, - input io_scan_mode, - input io_bus_clk_en, - output io_axi_aw_valid, - input io_axi_ar_ready, - output io_axi_ar_valid, - input io_axi_r_valid, - input [1:0] io_axi_r_bits_resp, - output io_ahb_sig_in_hresp + input clock, + input reset, + input io_scan_mode, + input io_bus_clk_en, + input io_axi_aw_ready, + output io_axi_aw_valid, + output [31:0] io_axi_aw_bits_addr, + output [2:0] io_axi_aw_bits_size, + output io_axi_w_valid, + output [63:0] io_axi_w_bits_data, + output [7:0] io_axi_w_bits_strb, + input io_axi_ar_ready, + output io_axi_ar_valid, + output [31:0] io_axi_ar_bits_addr, + output [2:0] io_axi_ar_bits_size, + input io_axi_r_valid, + input [63:0] io_axi_r_bits_data, + input [1:0] io_axi_r_bits_resp, + output [63:0] io_ahb_sig_in_hrdata, + output io_ahb_sig_in_hready, + output io_ahb_sig_in_hresp, + input [31:0] io_ahb_sig_out_haddr, + input [2:0] io_ahb_sig_out_hsize, + input [1:0] io_ahb_sig_out_htrans, + input io_ahb_sig_out_hwrite, + input [63:0] io_ahb_sig_out_hwdata, + input io_ahb_hsel, + input io_ahb_hreadyin ); `ifdef RANDOMIZE_REG_INIT reg [31:0] _RAND_0; reg [31:0] _RAND_1; reg [31:0] _RAND_2; reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [63:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [63:0] _RAND_14; `endif // RANDOMIZE_REG_INIT wire rvclkhdr_io_l1clk; // @[lib.scala 343:22] wire rvclkhdr_io_clk; // @[lib.scala 343:22] @@ -80334,29 +82364,48 @@ module ahb_to_axi4( wire rvclkhdr_5_io_clk; // @[lib.scala 343:22] wire rvclkhdr_5_io_en; // @[lib.scala 343:22] wire rvclkhdr_5_io_scan_mode; // @[lib.scala 343:22] - wire ahb_clk = rvclkhdr_io_l1clk; // @[ahb_to_axi4.scala 44:33 ahb_to_axi4.scala 133:31] + wire ahb_addr_clk = rvclkhdr_1_io_l1clk; // @[ahb_to_axi4.scala 44:33 ahb_to_axi4.scala 133:31] + reg [31:0] ahb_haddr_q; // @[ahb_to_axi4.scala 126:65] + wire ahb_addr_in_dccm = ahb_haddr_q[31:16] == 16'hf004; // @[lib.scala 87:29] + wire ahb_addr_in_iccm = ahb_haddr_q[31:16] == 16'hee00; // @[lib.scala 87:29] + wire ahb_clk = rvclkhdr_io_l1clk; // @[ahb_to_axi4.scala 43:33 ahb_to_axi4.scala 132:31] reg [1:0] buf_state; // @[Reg.scala 27:20] wire _T_7 = 2'h0 == buf_state; // @[Conditional.scala 37:30] + wire ahb_hready = io_ahb_sig_in_hready & io_ahb_hreadyin; // @[ahb_to_axi4.scala 104:55] + wire _T_10 = ahb_hready & io_ahb_sig_out_htrans[1]; // @[ahb_to_axi4.scala 76:34] + wire _T_11 = _T_10 & io_ahb_hsel; // @[ahb_to_axi4.scala 76:61] wire _T_12 = 2'h1 == buf_state; // @[Conditional.scala 37:30] - wire bus_clk = rvclkhdr_5_io_l1clk; // @[ahb_to_axi4.scala 58:33 ahb_to_axi4.scala 181:27] - reg cmdbuf_vld; // @[ahb_to_axi4.scala 140:61] - wire _T_152 = io_axi_ar_valid & io_axi_ar_ready; // @[ahb_to_axi4.scala 138:105] - wire _T_153 = io_axi_aw_valid | _T_152; // @[ahb_to_axi4.scala 138:86] - wire _T_154 = ~_T_153; // @[ahb_to_axi4.scala 138:48] - wire cmdbuf_full = cmdbuf_vld & _T_154; // @[ahb_to_axi4.scala 138:46] - wire _T_21 = ~cmdbuf_full; // @[ahb_to_axi4.scala 81:24] - wire _T_22 = _T_21 | io_ahb_sig_in_hresp; // @[ahb_to_axi4.scala 81:37] - wire _T_28 = ~io_ahb_sig_in_hresp; // @[ahb_to_axi4.scala 82:38] - wire _T_29 = _T_21 & _T_28; // @[ahb_to_axi4.scala 82:36] + wire _T_14 = io_ahb_sig_out_htrans == 2'h0; // @[ahb_to_axi4.scala 79:79] + wire _T_15 = io_ahb_sig_in_hresp | _T_14; // @[ahb_to_axi4.scala 79:48] + wire _T_16 = ~io_ahb_hsel; // @[ahb_to_axi4.scala 79:93] + wire _T_17 = _T_15 | _T_16; // @[ahb_to_axi4.scala 79:91] + wire bus_clk = rvclkhdr_5_io_l1clk; // @[ahb_to_axi4.scala 57:33 ahb_to_axi4.scala 180:27] + reg cmdbuf_vld; // @[ahb_to_axi4.scala 139:61] + wire _T_151 = io_axi_aw_valid & io_axi_aw_ready; // @[ahb_to_axi4.scala 137:67] + wire _T_152 = io_axi_ar_valid & io_axi_ar_ready; // @[ahb_to_axi4.scala 137:105] + wire _T_153 = _T_151 | _T_152; // @[ahb_to_axi4.scala 137:86] + wire _T_154 = ~_T_153; // @[ahb_to_axi4.scala 137:48] + wire cmdbuf_full = cmdbuf_vld & _T_154; // @[ahb_to_axi4.scala 137:46] + wire _T_21 = ~cmdbuf_full; // @[ahb_to_axi4.scala 80:24] + wire _T_22 = _T_21 | io_ahb_sig_in_hresp; // @[ahb_to_axi4.scala 80:37] + wire _T_25 = io_ahb_sig_out_htrans == 2'h1; // @[ahb_to_axi4.scala 81:92] + wire _T_26 = _T_25 & io_ahb_hsel; // @[ahb_to_axi4.scala 81:110] + wire _T_27 = io_ahb_sig_in_hresp | _T_26; // @[ahb_to_axi4.scala 81:60] + wire _T_28 = ~_T_27; // @[ahb_to_axi4.scala 81:38] + wire _T_29 = _T_21 & _T_28; // @[ahb_to_axi4.scala 81:36] wire _T_30 = 2'h2 == buf_state; // @[Conditional.scala 37:30] - wire _T_36 = _T_28 & _T_21; // @[ahb_to_axi4.scala 87:44] + wire _T_34 = ~io_ahb_sig_in_hresp; // @[ahb_to_axi4.scala 86:23] + wire _T_36 = _T_34 & _T_21; // @[ahb_to_axi4.scala 86:44] wire _T_37 = 2'h3 == buf_state; // @[Conditional.scala 37:30] - wire _T_41 = |io_axi_r_bits_resp; // @[ahb_to_axi4.scala 93:68] - wire _GEN_1 = _T_37 & io_axi_r_valid; // @[Conditional.scala 39:67] + reg cmdbuf_write; // @[Reg.scala 27:20] + wire _T_38 = ~cmdbuf_write; // @[ahb_to_axi4.scala 90:40] + wire _T_39 = io_axi_r_valid & _T_38; // @[ahb_to_axi4.scala 90:38] + wire _T_41 = |io_axi_r_bits_resp; // @[ahb_to_axi4.scala 92:68] + wire _GEN_1 = _T_37 & _T_39; // @[Conditional.scala 39:67] wire _GEN_5 = _T_30 ? _T_22 : _GEN_1; // @[Conditional.scala 39:67] wire _GEN_10 = _T_12 ? _T_22 : _GEN_5; // @[Conditional.scala 39:67] - wire buf_state_en = _T_7 ? 1'h0 : _GEN_10; // @[Conditional.scala 40:58] - wire _T_42 = buf_state_en & _T_41; // @[ahb_to_axi4.scala 93:41] + wire buf_state_en = _T_7 ? _T_11 : _GEN_10; // @[Conditional.scala 40:58] + wire _T_42 = buf_state_en & _T_41; // @[ahb_to_axi4.scala 92:41] wire _GEN_2 = _T_37 & buf_state_en; // @[Conditional.scala 39:67] wire _GEN_3 = _T_37 & _T_42; // @[Conditional.scala 39:67] wire _GEN_6 = _T_30 & _T_36; // @[Conditional.scala 39:67] @@ -80365,13 +82414,83 @@ module ahb_to_axi4( wire _GEN_12 = _T_12 ? 1'h0 : _GEN_7; // @[Conditional.scala 39:67] wire cmdbuf_wr_en = _T_7 ? 1'h0 : _GEN_11; // @[Conditional.scala 40:58] wire buf_rdata_en = _T_7 ? 1'h0 : _GEN_12; // @[Conditional.scala 40:58] - reg ahb_hresp_q; // @[ahb_to_axi4.scala 122:60] - reg buf_read_error; // @[ahb_to_axi4.scala 119:60] - wire _T_146 = ~cmdbuf_wr_en; // @[ahb_to_axi4.scala 137:113] - wire _T_147 = _T_153 & _T_146; // @[ahb_to_axi4.scala 137:111] - wire cmdbuf_rst = _T_147 | io_ahb_sig_in_hresp; // @[ahb_to_axi4.scala 137:128] - wire _T_157 = cmdbuf_wr_en | cmdbuf_vld; // @[ahb_to_axi4.scala 140:66] - wire _T_158 = ~cmdbuf_rst; // @[ahb_to_axi4.scala 140:110] + reg [2:0] ahb_hsize_q; // @[ahb_to_axi4.scala 124:65] + wire _T_46 = ahb_hsize_q == 3'h0; // @[ahb_to_axi4.scala 97:60] + wire [7:0] _T_48 = _T_46 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_50 = 8'h1 << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 97:78] + wire [7:0] _T_51 = _T_48 & _T_50; // @[ahb_to_axi4.scala 97:70] + wire _T_53 = ahb_hsize_q == 3'h1; // @[ahb_to_axi4.scala 98:30] + wire [7:0] _T_55 = _T_53 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [8:0] _T_57 = 9'h3 << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 98:48] + wire [8:0] _GEN_23 = {{1'd0}, _T_55}; // @[ahb_to_axi4.scala 98:40] + wire [8:0] _T_58 = _GEN_23 & _T_57; // @[ahb_to_axi4.scala 98:40] + wire [8:0] _GEN_24 = {{1'd0}, _T_51}; // @[ahb_to_axi4.scala 97:109] + wire [8:0] _T_59 = _GEN_24 | _T_58; // @[ahb_to_axi4.scala 97:109] + wire _T_61 = ahb_hsize_q == 3'h2; // @[ahb_to_axi4.scala 99:30] + wire [7:0] _T_63 = _T_61 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [10:0] _T_65 = 11'hf << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 99:48] + wire [10:0] _GEN_25 = {{3'd0}, _T_63}; // @[ahb_to_axi4.scala 99:40] + wire [10:0] _T_66 = _GEN_25 & _T_65; // @[ahb_to_axi4.scala 99:40] + wire [10:0] _GEN_26 = {{2'd0}, _T_59}; // @[ahb_to_axi4.scala 98:79] + wire [10:0] _T_67 = _GEN_26 | _T_66; // @[ahb_to_axi4.scala 98:79] + wire _T_69 = ahb_hsize_q == 3'h3; // @[ahb_to_axi4.scala 100:30] + wire [7:0] _T_71 = _T_69 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [10:0] _GEN_27 = {{3'd0}, _T_71}; // @[ahb_to_axi4.scala 99:79] + wire [10:0] _T_73 = _T_67 | _GEN_27; // @[ahb_to_axi4.scala 99:79] + reg ahb_hready_q; // @[ahb_to_axi4.scala 122:60] + wire _T_74 = ~ahb_hready_q; // @[ahb_to_axi4.scala 103:80] + reg ahb_hresp_q; // @[ahb_to_axi4.scala 121:60] + wire _T_75 = ahb_hresp_q & _T_74; // @[ahb_to_axi4.scala 103:78] + wire _T_77 = buf_state == 2'h0; // @[ahb_to_axi4.scala 103:124] + wire _T_78 = _T_21 | _T_77; // @[ahb_to_axi4.scala 103:111] + wire _T_79 = buf_state == 2'h2; // @[ahb_to_axi4.scala 103:149] + wire _T_80 = buf_state == 2'h3; // @[ahb_to_axi4.scala 103:168] + wire _T_81 = _T_79 | _T_80; // @[ahb_to_axi4.scala 103:156] + wire _T_82 = ~_T_81; // @[ahb_to_axi4.scala 103:137] + wire _T_83 = _T_78 & _T_82; // @[ahb_to_axi4.scala 103:135] + reg buf_read_error; // @[ahb_to_axi4.scala 118:60] + wire _T_84 = ~buf_read_error; // @[ahb_to_axi4.scala 103:181] + wire _T_85 = _T_83 & _T_84; // @[ahb_to_axi4.scala 103:179] + wire [1:0] _T_89 = io_ahb_hsel ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire buf_rdata_clk = rvclkhdr_2_io_l1clk; // @[ahb_to_axi4.scala 45:33 ahb_to_axi4.scala 134:31] + reg [63:0] buf_rdata; // @[ahb_to_axi4.scala 117:66] + reg [1:0] ahb_htrans_q; // @[ahb_to_axi4.scala 123:60] + wire _T_94 = ahb_htrans_q != 2'h0; // @[ahb_to_axi4.scala 107:61] + wire _T_95 = buf_state != 2'h0; // @[ahb_to_axi4.scala 107:83] + wire _T_96 = _T_94 & _T_95; // @[ahb_to_axi4.scala 107:70] + wire _T_97 = ahb_addr_in_dccm | ahb_addr_in_iccm; // @[ahb_to_axi4.scala 108:26] + wire _T_98 = ~_T_97; // @[ahb_to_axi4.scala 108:7] + reg ahb_hwrite_q; // @[ahb_to_axi4.scala 125:65] + wire _T_99 = ahb_addr_in_dccm & ahb_hwrite_q; // @[ahb_to_axi4.scala 109:46] + wire _T_100 = ahb_addr_in_iccm | _T_99; // @[ahb_to_axi4.scala 109:26] + wire _T_102 = ahb_hsize_q[1:0] == 2'h2; // @[ahb_to_axi4.scala 109:86] + wire _T_104 = ahb_hsize_q[1:0] == 2'h3; // @[ahb_to_axi4.scala 109:115] + wire _T_105 = _T_102 | _T_104; // @[ahb_to_axi4.scala 109:95] + wire _T_106 = ~_T_105; // @[ahb_to_axi4.scala 109:66] + wire _T_107 = _T_100 & _T_106; // @[ahb_to_axi4.scala 109:64] + wire _T_108 = _T_98 | _T_107; // @[ahb_to_axi4.scala 108:47] + wire _T_112 = _T_53 & ahb_haddr_q[0]; // @[ahb_to_axi4.scala 110:35] + wire _T_113 = _T_108 | _T_112; // @[ahb_to_axi4.scala 109:126] + wire _T_117 = |ahb_haddr_q[1:0]; // @[ahb_to_axi4.scala 111:56] + wire _T_118 = _T_61 & _T_117; // @[ahb_to_axi4.scala 111:35] + wire _T_119 = _T_113 | _T_118; // @[ahb_to_axi4.scala 110:55] + wire _T_123 = |ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 112:56] + wire _T_124 = _T_69 & _T_123; // @[ahb_to_axi4.scala 112:35] + wire _T_125 = _T_119 | _T_124; // @[ahb_to_axi4.scala 111:61] + wire _T_126 = _T_96 & _T_125; // @[ahb_to_axi4.scala 107:94] + wire _T_127 = _T_126 | buf_read_error; // @[ahb_to_axi4.scala 112:63] + wire _T_146 = ~cmdbuf_wr_en; // @[ahb_to_axi4.scala 136:113] + wire _T_147 = _T_153 & _T_146; // @[ahb_to_axi4.scala 136:111] + wire _T_149 = io_ahb_sig_in_hresp & _T_38; // @[ahb_to_axi4.scala 136:151] + wire cmdbuf_rst = _T_147 | _T_149; // @[ahb_to_axi4.scala 136:128] + wire _T_157 = cmdbuf_wr_en | cmdbuf_vld; // @[ahb_to_axi4.scala 139:66] + wire _T_158 = ~cmdbuf_rst; // @[ahb_to_axi4.scala 139:110] + reg [2:0] _T_164; // @[Reg.scala 27:20] + reg [7:0] cmdbuf_wstrb; // @[Reg.scala 27:20] + wire [7:0] master_wstrb = _T_73[7:0]; // @[ahb_to_axi4.scala 97:31] + reg [31:0] cmdbuf_addr; // @[lib.scala 374:16] + reg [63:0] cmdbuf_wdata; // @[lib.scala 374:16] + wire [1:0] cmdbuf_size = _T_164[1:0]; // @[ahb_to_axi4.scala 145:31] rvclkhdr rvclkhdr ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), @@ -80408,14 +82527,23 @@ module ahb_to_axi4( .io_en(rvclkhdr_5_io_en), .io_scan_mode(rvclkhdr_5_io_scan_mode) ); - assign io_axi_aw_valid = 1'h0; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 157:28] - assign io_axi_ar_valid = cmdbuf_vld; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 172:28] - assign io_ahb_sig_in_hresp = buf_read_error | ahb_hresp_q; // @[ahb_to_axi4.scala 108:38] + assign io_axi_aw_valid = cmdbuf_vld & cmdbuf_write; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 156:28] + assign io_axi_aw_bits_addr = cmdbuf_addr; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 158:33] + assign io_axi_aw_bits_size = {1'h0,cmdbuf_size}; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 159:33] + assign io_axi_w_valid = cmdbuf_vld & cmdbuf_write; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 164:28] + assign io_axi_w_bits_data = cmdbuf_wdata; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 165:33] + assign io_axi_w_bits_strb = cmdbuf_wstrb; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 166:33] + assign io_axi_ar_valid = cmdbuf_vld & _T_38; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 171:28] + assign io_axi_ar_bits_addr = cmdbuf_addr; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 173:33] + assign io_axi_ar_bits_size = {1'h0,cmdbuf_size}; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 174:33] + assign io_ahb_sig_in_hrdata = buf_rdata; // @[ahb_to_axi4.scala 106:38] + assign io_ahb_sig_in_hready = io_ahb_sig_in_hresp ? _T_75 : _T_85; // @[ahb_to_axi4.scala 103:38] + assign io_ahb_sig_in_hresp = _T_127 | _T_75; // @[ahb_to_axi4.scala 107:38] assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17] assign rvclkhdr_io_en = io_bus_clk_en; // @[lib.scala 345:16] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] assign rvclkhdr_1_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_1_io_en = 1'h0; // @[lib.scala 345:16] + assign rvclkhdr_1_io_en = io_bus_clk_en & _T_10; // @[lib.scala 345:16] assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] assign rvclkhdr_2_io_clk = clock; // @[lib.scala 344:17] assign rvclkhdr_2_io_en = io_bus_clk_en & buf_rdata_en; // @[lib.scala 345:16] @@ -80465,40 +82593,112 @@ initial begin `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; - buf_state = _RAND_0[1:0]; + ahb_haddr_q = _RAND_0[31:0]; _RAND_1 = {1{`RANDOM}}; - cmdbuf_vld = _RAND_1[0:0]; + buf_state = _RAND_1[1:0]; _RAND_2 = {1{`RANDOM}}; - ahb_hresp_q = _RAND_2[0:0]; + cmdbuf_vld = _RAND_2[0:0]; _RAND_3 = {1{`RANDOM}}; - buf_read_error = _RAND_3[0:0]; + cmdbuf_write = _RAND_3[0:0]; + _RAND_4 = {1{`RANDOM}}; + ahb_hsize_q = _RAND_4[2:0]; + _RAND_5 = {1{`RANDOM}}; + ahb_hready_q = _RAND_5[0:0]; + _RAND_6 = {1{`RANDOM}}; + ahb_hresp_q = _RAND_6[0:0]; + _RAND_7 = {1{`RANDOM}}; + buf_read_error = _RAND_7[0:0]; + _RAND_8 = {2{`RANDOM}}; + buf_rdata = _RAND_8[63:0]; + _RAND_9 = {1{`RANDOM}}; + ahb_htrans_q = _RAND_9[1:0]; + _RAND_10 = {1{`RANDOM}}; + ahb_hwrite_q = _RAND_10[0:0]; + _RAND_11 = {1{`RANDOM}}; + _T_164 = _RAND_11[2:0]; + _RAND_12 = {1{`RANDOM}}; + cmdbuf_wstrb = _RAND_12[7:0]; + _RAND_13 = {1{`RANDOM}}; + cmdbuf_addr = _RAND_13[31:0]; + _RAND_14 = {2{`RANDOM}}; + cmdbuf_wdata = _RAND_14[63:0]; `endif // RANDOMIZE_REG_INIT + if (reset) begin + ahb_haddr_q = 32'h0; + end if (reset) begin buf_state = 2'h0; end if (reset) begin cmdbuf_vld = 1'h0; end + if (reset) begin + cmdbuf_write = 1'h0; + end + if (reset) begin + ahb_hsize_q = 3'h0; + end + if (reset) begin + ahb_hready_q = 1'h0; + end if (reset) begin ahb_hresp_q = 1'h0; end if (reset) begin buf_read_error = 1'h0; end + if (reset) begin + buf_rdata = 64'h0; + end + if (reset) begin + ahb_htrans_q = 2'h0; + end + if (reset) begin + ahb_hwrite_q = 1'h0; + end + if (reset) begin + _T_164 = 3'h0; + end + if (reset) begin + cmdbuf_wstrb = 8'h0; + end + if (reset) begin + cmdbuf_addr = 32'h0; + end + if (reset) begin + cmdbuf_wdata = 64'h0; + end `endif // RANDOMIZE end // initial `ifdef FIRRTL_AFTER_INITIAL `FIRRTL_AFTER_INITIAL `endif `endif // SYNTHESIS + always @(posedge ahb_addr_clk or posedge reset) begin + if (reset) begin + ahb_haddr_q <= 32'h0; + end else begin + ahb_haddr_q <= io_ahb_sig_out_haddr; + end + end always @(posedge ahb_clk or posedge reset) begin if (reset) begin buf_state <= 2'h0; end else if (buf_state_en) begin if (_T_7) begin - buf_state <= 2'h2; + if (io_ahb_sig_out_hwrite) begin + buf_state <= 2'h1; + end else begin + buf_state <= 2'h2; + end end else if (_T_12) begin - buf_state <= 2'h0; + if (_T_17) begin + buf_state <= 2'h0; + end else if (io_ahb_sig_out_hwrite) begin + buf_state <= 2'h1; + end else begin + buf_state <= 2'h2; + end end else if (_T_30) begin if (io_ahb_sig_in_hresp) begin buf_state <= 2'h0; @@ -80517,6 +82717,27 @@ end // initial cmdbuf_vld <= _T_157 & _T_158; end end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + cmdbuf_write <= 1'h0; + end else if (cmdbuf_wr_en) begin + cmdbuf_write <= ahb_hwrite_q; + end + end + always @(posedge ahb_addr_clk or posedge reset) begin + if (reset) begin + ahb_hsize_q <= 3'h0; + end else begin + ahb_hsize_q <= io_ahb_sig_out_hsize; + end + end + always @(posedge ahb_clk or posedge reset) begin + if (reset) begin + ahb_hready_q <= 1'h0; + end else begin + ahb_hready_q <= io_ahb_sig_in_hready & io_ahb_hreadyin; + end + end always @(posedge ahb_clk or posedge reset) begin if (reset) begin ahb_hresp_q <= 1'h0; @@ -80537,10 +82758,93 @@ end // initial buf_read_error <= _GEN_3; end end + always @(posedge buf_rdata_clk or posedge reset) begin + if (reset) begin + buf_rdata <= 64'h0; + end else begin + buf_rdata <= io_axi_r_bits_data; + end + end + always @(posedge ahb_clk or posedge reset) begin + if (reset) begin + ahb_htrans_q <= 2'h0; + end else begin + ahb_htrans_q <= _T_89 & io_ahb_sig_out_htrans; + end + end + always @(posedge ahb_addr_clk or posedge reset) begin + if (reset) begin + ahb_hwrite_q <= 1'h0; + end else begin + ahb_hwrite_q <= io_ahb_sig_out_hwrite; + end + end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + _T_164 <= 3'h0; + end else if (cmdbuf_wr_en) begin + _T_164 <= ahb_hsize_q; + end + end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + cmdbuf_wstrb <= 8'h0; + end else if (cmdbuf_wr_en) begin + cmdbuf_wstrb <= master_wstrb; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + cmdbuf_addr <= 32'h0; + end else begin + cmdbuf_addr <= ahb_haddr_q; + end + end + always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + if (reset) begin + cmdbuf_wdata <= 64'h0; + end else begin + cmdbuf_wdata <= io_ahb_sig_out_hwdata; + end + end endmodule module quasar( input clock, input reset, + input [63:0] io_lsu_ahb_in_hrdata, + input io_lsu_ahb_in_hready, + input io_lsu_ahb_in_hresp, + output [31:0] io_lsu_ahb_out_haddr, + output [2:0] io_lsu_ahb_out_hsize, + output [1:0] io_lsu_ahb_out_htrans, + output io_lsu_ahb_out_hwrite, + output [63:0] io_lsu_ahb_out_hwdata, + input [63:0] io_ifu_ahb_in_hrdata, + input io_ifu_ahb_in_hready, + input io_ifu_ahb_in_hresp, + output [31:0] io_ifu_ahb_out_haddr, + output [2:0] io_ifu_ahb_out_hsize, + output [1:0] io_ifu_ahb_out_htrans, + output io_ifu_ahb_out_hwrite, + output [63:0] io_ifu_ahb_out_hwdata, + input [63:0] io_sb_ahb_in_hrdata, + input io_sb_ahb_in_hready, + input io_sb_ahb_in_hresp, + output [31:0] io_sb_ahb_out_haddr, + output [2:0] io_sb_ahb_out_hsize, + output [1:0] io_sb_ahb_out_htrans, + output io_sb_ahb_out_hwrite, + output [63:0] io_sb_ahb_out_hwdata, + output [63:0] io_dma_ahb_sig_in_hrdata, + output io_dma_ahb_sig_in_hready, + output io_dma_ahb_sig_in_hresp, + input [31:0] io_dma_ahb_sig_out_haddr, + input [2:0] io_dma_ahb_sig_out_hsize, + input [1:0] io_dma_ahb_sig_out_htrans, + input io_dma_ahb_sig_out_hwrite, + input [63:0] io_dma_ahb_sig_out_hwdata, + input io_dma_ahb_hsel, + input io_dma_ahb_hreadyin, input io_dbg_rst_l, input [30:0] io_rst_vec, input io_nmi_int, @@ -80620,759 +82924,783 @@ module quasar( input [6:0] io_dmi_reg_addr, input io_dmi_reg_wr_en, input [31:0] io_dmi_reg_wdata, + output [31:0] io_dmi_reg_rdata, input [30:0] io_extintsrc_req, input io_timer_int, input io_soft_int, input io_scan_mode ); - wire ifu_clock; // @[quasar.scala 72:19] - wire ifu_reset; // @[quasar.scala 72:19] - wire ifu_io_exu_flush_final; // @[quasar.scala 72:19] - wire [30:0] ifu_io_exu_flush_path_final; // @[quasar.scala 72:19] - wire ifu_io_free_clk; // @[quasar.scala 72:19] - wire ifu_io_active_clk; // @[quasar.scala 72:19] - wire ifu_io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d; // @[quasar.scala 72:19] - wire [15:0] ifu_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst; // @[quasar.scala 72:19] - wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf; // @[quasar.scala 72:19] - wire [1:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type; // @[quasar.scala 72:19] - wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1; // @[quasar.scala 72:19] - wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc; // @[quasar.scala 72:19] - wire [7:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index; // @[quasar.scala 72:19] - wire [7:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[quasar.scala 72:19] - wire [4:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag; // @[quasar.scala 72:19] - wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid; // @[quasar.scala 72:19] - wire [31:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr; // @[quasar.scala 72:19] - wire [30:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc; // @[quasar.scala 72:19] - wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4; // @[quasar.scala 72:19] - wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid; // @[quasar.scala 72:19] - wire [11:0] ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset; // @[quasar.scala 72:19] - wire [1:0] ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist; // @[quasar.scala 72:19] - wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error; // @[quasar.scala 72:19] - wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[quasar.scala 72:19] - wire [30:0] ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett; // @[quasar.scala 72:19] - wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way; // @[quasar.scala 72:19] - wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret; // @[quasar.scala 72:19] - wire ifu_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned; // @[quasar.scala 72:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[quasar.scala 72:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[quasar.scala 72:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 72:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb; // @[quasar.scala 72:19] - wire [70:0] ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[quasar.scala 72:19] - wire [16:0] ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics; // @[quasar.scala 72:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[quasar.scala 72:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[quasar.scala 72:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 72:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss; // @[quasar.scala 72:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[quasar.scala 72:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[quasar.scala 72:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[quasar.scala 72:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[quasar.scala 72:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[quasar.scala 72:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[quasar.scala 72:19] - wire [70:0] ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[quasar.scala 72:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[quasar.scala 72:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle; // @[quasar.scala 72:19] - wire ifu_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb; // @[quasar.scala 72:19] - wire [31:0] ifu_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 72:19] - wire ifu_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall; // @[quasar.scala 72:19] - wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid; // @[quasar.scala 72:19] - wire [1:0] ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist; // @[quasar.scala 72:19] - wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[quasar.scala 72:19] - wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[quasar.scala 72:19] - wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[quasar.scala 72:19] - wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[quasar.scala 72:19] - wire ifu_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb; // @[quasar.scala 72:19] - wire ifu_io_ifu_dec_dec_bp_dec_tlu_bpred_disable; // @[quasar.scala 72:19] - wire [7:0] ifu_io_exu_ifu_exu_bp_exu_i0_br_index_r; // @[quasar.scala 72:19] - wire [7:0] ifu_io_exu_ifu_exu_bp_exu_i0_br_fghr_r; // @[quasar.scala 72:19] - wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_misp; // @[quasar.scala 72:19] - wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_ataken; // @[quasar.scala 72:19] - wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_boffset; // @[quasar.scala 72:19] - wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pc4; // @[quasar.scala 72:19] - wire [1:0] ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_hist; // @[quasar.scala 72:19] - wire [11:0] ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_toffset; // @[quasar.scala 72:19] - wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pcall; // @[quasar.scala 72:19] - wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pret; // @[quasar.scala 72:19] - wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pja; // @[quasar.scala 72:19] - wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_way; // @[quasar.scala 72:19] - wire [7:0] ifu_io_exu_ifu_exu_bp_exu_mp_eghr; // @[quasar.scala 72:19] - wire [7:0] ifu_io_exu_ifu_exu_bp_exu_mp_fghr; // @[quasar.scala 72:19] - wire [7:0] ifu_io_exu_ifu_exu_bp_exu_mp_index; // @[quasar.scala 72:19] - wire [4:0] ifu_io_exu_ifu_exu_bp_exu_mp_btag; // @[quasar.scala 72:19] - wire [14:0] ifu_io_iccm_rw_addr; // @[quasar.scala 72:19] - wire ifu_io_iccm_buf_correct_ecc; // @[quasar.scala 72:19] - wire ifu_io_iccm_correction_state; // @[quasar.scala 72:19] - wire ifu_io_iccm_wren; // @[quasar.scala 72:19] - wire ifu_io_iccm_rden; // @[quasar.scala 72:19] - wire [2:0] ifu_io_iccm_wr_size; // @[quasar.scala 72:19] - wire [77:0] ifu_io_iccm_wr_data; // @[quasar.scala 72:19] - wire [63:0] ifu_io_iccm_rd_data; // @[quasar.scala 72:19] - wire [77:0] ifu_io_iccm_rd_data_ecc; // @[quasar.scala 72:19] - wire [30:0] ifu_io_ic_rw_addr; // @[quasar.scala 72:19] - wire [1:0] ifu_io_ic_tag_valid; // @[quasar.scala 72:19] - wire [1:0] ifu_io_ic_wr_en; // @[quasar.scala 72:19] - wire ifu_io_ic_rd_en; // @[quasar.scala 72:19] - wire [70:0] ifu_io_ic_wr_data_0; // @[quasar.scala 72:19] - wire [70:0] ifu_io_ic_wr_data_1; // @[quasar.scala 72:19] - wire [70:0] ifu_io_ic_debug_wr_data; // @[quasar.scala 72:19] - wire [9:0] ifu_io_ic_debug_addr; // @[quasar.scala 72:19] - wire [63:0] ifu_io_ic_rd_data; // @[quasar.scala 72:19] - wire [70:0] ifu_io_ic_debug_rd_data; // @[quasar.scala 72:19] - wire [25:0] ifu_io_ic_tag_debug_rd_data; // @[quasar.scala 72:19] - wire [1:0] ifu_io_ic_eccerr; // @[quasar.scala 72:19] - wire [1:0] ifu_io_ic_rd_hit; // @[quasar.scala 72:19] - wire ifu_io_ic_tag_perr; // @[quasar.scala 72:19] - wire ifu_io_ic_debug_rd_en; // @[quasar.scala 72:19] - wire ifu_io_ic_debug_wr_en; // @[quasar.scala 72:19] - wire ifu_io_ic_debug_tag_array; // @[quasar.scala 72:19] - wire [1:0] ifu_io_ic_debug_way; // @[quasar.scala 72:19] - wire [63:0] ifu_io_ic_premux_data; // @[quasar.scala 72:19] - wire ifu_io_ic_sel_premux_data; // @[quasar.scala 72:19] - wire ifu_io_ifu_ar_ready; // @[quasar.scala 72:19] - wire ifu_io_ifu_ar_valid; // @[quasar.scala 72:19] - wire [2:0] ifu_io_ifu_ar_bits_id; // @[quasar.scala 72:19] - wire ifu_io_ifu_r_valid; // @[quasar.scala 72:19] - wire [2:0] ifu_io_ifu_r_bits_id; // @[quasar.scala 72:19] - wire [63:0] ifu_io_ifu_r_bits_data; // @[quasar.scala 72:19] - wire [1:0] ifu_io_ifu_r_bits_resp; // @[quasar.scala 72:19] - wire ifu_io_ifu_bus_clk_en; // @[quasar.scala 72:19] - wire ifu_io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[quasar.scala 72:19] - wire ifu_io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[quasar.scala 72:19] - wire [31:0] ifu_io_ifu_dma_dma_mem_ctl_dma_mem_addr; // @[quasar.scala 72:19] - wire [2:0] ifu_io_ifu_dma_dma_mem_ctl_dma_mem_sz; // @[quasar.scala 72:19] - wire ifu_io_ifu_dma_dma_mem_ctl_dma_mem_write; // @[quasar.scala 72:19] - wire [63:0] ifu_io_ifu_dma_dma_mem_ctl_dma_mem_wdata; // @[quasar.scala 72:19] - wire [2:0] ifu_io_ifu_dma_dma_mem_ctl_dma_mem_tag; // @[quasar.scala 72:19] - wire ifu_io_iccm_dma_ecc_error; // @[quasar.scala 72:19] - wire ifu_io_iccm_dma_rvalid; // @[quasar.scala 72:19] - wire [63:0] ifu_io_iccm_dma_rdata; // @[quasar.scala 72:19] - wire [2:0] ifu_io_iccm_dma_rtag; // @[quasar.scala 72:19] - wire ifu_io_iccm_ready; // @[quasar.scala 72:19] - wire ifu_io_iccm_dma_sb_error; // @[quasar.scala 72:19] - wire ifu_io_dec_tlu_flush_lower_wb; // @[quasar.scala 72:19] - wire ifu_io_scan_mode; // @[quasar.scala 72:19] - wire dec_clock; // @[quasar.scala 73:19] - wire dec_reset; // @[quasar.scala 73:19] - wire dec_io_free_clk; // @[quasar.scala 73:19] - wire dec_io_active_clk; // @[quasar.scala 73:19] - wire dec_io_lsu_fastint_stall_any; // @[quasar.scala 73:19] - wire dec_io_dec_pause_state_cg; // @[quasar.scala 73:19] - wire [30:0] dec_io_rst_vec; // @[quasar.scala 73:19] - wire dec_io_nmi_int; // @[quasar.scala 73:19] - wire [30:0] dec_io_nmi_vec; // @[quasar.scala 73:19] - wire dec_io_i_cpu_halt_req; // @[quasar.scala 73:19] - wire dec_io_i_cpu_run_req; // @[quasar.scala 73:19] - wire dec_io_o_cpu_halt_status; // @[quasar.scala 73:19] - wire dec_io_o_cpu_halt_ack; // @[quasar.scala 73:19] - wire dec_io_o_cpu_run_ack; // @[quasar.scala 73:19] - wire dec_io_o_debug_mode_status; // @[quasar.scala 73:19] - wire [27:0] dec_io_core_id; // @[quasar.scala 73:19] - wire dec_io_mpc_debug_halt_req; // @[quasar.scala 73:19] - wire dec_io_mpc_debug_run_req; // @[quasar.scala 73:19] - wire dec_io_mpc_reset_run_req; // @[quasar.scala 73:19] - wire dec_io_mpc_debug_halt_ack; // @[quasar.scala 73:19] - wire dec_io_mpc_debug_run_ack; // @[quasar.scala 73:19] - wire dec_io_debug_brkpt_status; // @[quasar.scala 73:19] - wire dec_io_lsu_pmu_misaligned_m; // @[quasar.scala 73:19] - wire [30:0] dec_io_lsu_fir_addr; // @[quasar.scala 73:19] - wire [1:0] dec_io_lsu_fir_error; // @[quasar.scala 73:19] - wire [3:0] dec_io_lsu_trigger_match_m; // @[quasar.scala 73:19] - wire dec_io_lsu_idle_any; // @[quasar.scala 73:19] - wire dec_io_lsu_error_pkt_r_valid; // @[quasar.scala 73:19] - wire dec_io_lsu_error_pkt_r_bits_single_ecc_error; // @[quasar.scala 73:19] - wire dec_io_lsu_error_pkt_r_bits_inst_type; // @[quasar.scala 73:19] - wire dec_io_lsu_error_pkt_r_bits_exc_type; // @[quasar.scala 73:19] - wire [3:0] dec_io_lsu_error_pkt_r_bits_mscause; // @[quasar.scala 73:19] - wire [31:0] dec_io_lsu_error_pkt_r_bits_addr; // @[quasar.scala 73:19] - wire dec_io_lsu_single_ecc_error_incr; // @[quasar.scala 73:19] - wire [31:0] dec_io_exu_div_result; // @[quasar.scala 73:19] - wire dec_io_exu_div_wren; // @[quasar.scala 73:19] - wire [31:0] dec_io_lsu_result_m; // @[quasar.scala 73:19] - wire [31:0] dec_io_lsu_result_corr_r; // @[quasar.scala 73:19] - wire dec_io_lsu_load_stall_any; // @[quasar.scala 73:19] - wire dec_io_lsu_store_stall_any; // @[quasar.scala 73:19] - wire dec_io_iccm_dma_sb_error; // @[quasar.scala 73:19] - wire dec_io_exu_flush_final; // @[quasar.scala 73:19] - wire dec_io_timer_int; // @[quasar.scala 73:19] - wire dec_io_soft_int; // @[quasar.scala 73:19] - wire dec_io_dbg_halt_req; // @[quasar.scala 73:19] - wire dec_io_dbg_resume_req; // @[quasar.scala 73:19] - wire dec_io_dec_tlu_dbg_halted; // @[quasar.scala 73:19] - wire dec_io_dec_tlu_debug_mode; // @[quasar.scala 73:19] - wire dec_io_dec_tlu_resume_ack; // @[quasar.scala 73:19] - wire dec_io_dec_tlu_mpc_halted_only; // @[quasar.scala 73:19] - wire [31:0] dec_io_dec_dbg_rddata; // @[quasar.scala 73:19] - wire dec_io_dec_dbg_cmd_done; // @[quasar.scala 73:19] - wire dec_io_dec_dbg_cmd_fail; // @[quasar.scala 73:19] - wire dec_io_trigger_pkt_any_0_select; // @[quasar.scala 73:19] - wire dec_io_trigger_pkt_any_0_match_pkt; // @[quasar.scala 73:19] - wire dec_io_trigger_pkt_any_0_store; // @[quasar.scala 73:19] - wire dec_io_trigger_pkt_any_0_load; // @[quasar.scala 73:19] - wire [31:0] dec_io_trigger_pkt_any_0_tdata2; // @[quasar.scala 73:19] - wire dec_io_trigger_pkt_any_1_select; // @[quasar.scala 73:19] - wire dec_io_trigger_pkt_any_1_match_pkt; // @[quasar.scala 73:19] - wire dec_io_trigger_pkt_any_1_store; // @[quasar.scala 73:19] - wire dec_io_trigger_pkt_any_1_load; // @[quasar.scala 73:19] - wire [31:0] dec_io_trigger_pkt_any_1_tdata2; // @[quasar.scala 73:19] - wire dec_io_trigger_pkt_any_2_select; // @[quasar.scala 73:19] - wire dec_io_trigger_pkt_any_2_match_pkt; // @[quasar.scala 73:19] - wire dec_io_trigger_pkt_any_2_store; // @[quasar.scala 73:19] - wire dec_io_trigger_pkt_any_2_load; // @[quasar.scala 73:19] - wire [31:0] dec_io_trigger_pkt_any_2_tdata2; // @[quasar.scala 73:19] - wire dec_io_trigger_pkt_any_3_select; // @[quasar.scala 73:19] - wire dec_io_trigger_pkt_any_3_match_pkt; // @[quasar.scala 73:19] - wire dec_io_trigger_pkt_any_3_store; // @[quasar.scala 73:19] - wire dec_io_trigger_pkt_any_3_load; // @[quasar.scala 73:19] - wire [31:0] dec_io_trigger_pkt_any_3_tdata2; // @[quasar.scala 73:19] - wire dec_io_exu_i0_br_way_r; // @[quasar.scala 73:19] - wire dec_io_lsu_p_valid; // @[quasar.scala 73:19] - wire dec_io_lsu_p_bits_fast_int; // @[quasar.scala 73:19] - wire dec_io_lsu_p_bits_by; // @[quasar.scala 73:19] - wire dec_io_lsu_p_bits_half; // @[quasar.scala 73:19] - wire dec_io_lsu_p_bits_word; // @[quasar.scala 73:19] - wire dec_io_lsu_p_bits_load; // @[quasar.scala 73:19] - wire dec_io_lsu_p_bits_store; // @[quasar.scala 73:19] - wire dec_io_lsu_p_bits_unsign; // @[quasar.scala 73:19] - wire dec_io_lsu_p_bits_store_data_bypass_d; // @[quasar.scala 73:19] - wire dec_io_lsu_p_bits_load_ldst_bypass_d; // @[quasar.scala 73:19] - wire [11:0] dec_io_dec_lsu_offset_d; // @[quasar.scala 73:19] - wire dec_io_dec_tlu_i0_kill_writeb_r; // @[quasar.scala 73:19] - wire dec_io_dec_tlu_perfcnt0; // @[quasar.scala 73:19] - wire dec_io_dec_tlu_perfcnt1; // @[quasar.scala 73:19] - wire dec_io_dec_tlu_perfcnt2; // @[quasar.scala 73:19] - wire dec_io_dec_tlu_perfcnt3; // @[quasar.scala 73:19] - wire dec_io_dec_lsu_valid_raw_d; // @[quasar.scala 73:19] - wire [1:0] dec_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar.scala 73:19] - wire [31:0] dec_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar.scala 73:19] - wire [31:0] dec_io_rv_trace_pkt_rv_i_address_ip; // @[quasar.scala 73:19] - wire [1:0] dec_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar.scala 73:19] - wire [4:0] dec_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar.scala 73:19] - wire [1:0] dec_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar.scala 73:19] - wire [31:0] dec_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar.scala 73:19] - wire dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 73:19] - wire dec_io_dec_tlu_lsu_clk_override; // @[quasar.scala 73:19] - wire dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 73:19] - wire dec_io_dec_tlu_pic_clk_override; // @[quasar.scala 73:19] - wire dec_io_dec_tlu_dccm_clk_override; // @[quasar.scala 73:19] - wire dec_io_dec_tlu_icm_clk_override; // @[quasar.scala 73:19] - wire dec_io_scan_mode; // @[quasar.scala 73:19] - wire dec_io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d; // @[quasar.scala 73:19] - wire [15:0] dec_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst; // @[quasar.scala 73:19] - wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf; // @[quasar.scala 73:19] - wire [1:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type; // @[quasar.scala 73:19] - wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1; // @[quasar.scala 73:19] - wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc; // @[quasar.scala 73:19] - wire [7:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index; // @[quasar.scala 73:19] - wire [7:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[quasar.scala 73:19] - wire [4:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag; // @[quasar.scala 73:19] - wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid; // @[quasar.scala 73:19] - wire [31:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr; // @[quasar.scala 73:19] - wire [30:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc; // @[quasar.scala 73:19] - wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4; // @[quasar.scala 73:19] - wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid; // @[quasar.scala 73:19] - wire [11:0] dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset; // @[quasar.scala 73:19] - wire [1:0] dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist; // @[quasar.scala 73:19] - wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error; // @[quasar.scala 73:19] - wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[quasar.scala 73:19] - wire [30:0] dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett; // @[quasar.scala 73:19] - wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way; // @[quasar.scala 73:19] - wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret; // @[quasar.scala 73:19] - wire dec_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned; // @[quasar.scala 73:19] - wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[quasar.scala 73:19] - wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[quasar.scala 73:19] - wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 73:19] - wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb; // @[quasar.scala 73:19] - wire [70:0] dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[quasar.scala 73:19] - wire [16:0] dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics; // @[quasar.scala 73:19] - wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[quasar.scala 73:19] - wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[quasar.scala 73:19] - wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 73:19] - wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss; // @[quasar.scala 73:19] - wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[quasar.scala 73:19] - wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[quasar.scala 73:19] - wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[quasar.scala 73:19] - wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[quasar.scala 73:19] - wire dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[quasar.scala 73:19] - wire dec_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[quasar.scala 73:19] - wire [70:0] dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[quasar.scala 73:19] - wire dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[quasar.scala 73:19] - wire dec_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle; // @[quasar.scala 73:19] - wire dec_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb; // @[quasar.scala 73:19] - wire [31:0] dec_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 73:19] - wire dec_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall; // @[quasar.scala 73:19] - wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid; // @[quasar.scala 73:19] - wire [1:0] dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist; // @[quasar.scala 73:19] - wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[quasar.scala 73:19] - wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[quasar.scala 73:19] - wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[quasar.scala 73:19] - wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[quasar.scala 73:19] - wire dec_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb; // @[quasar.scala 73:19] - wire dec_io_ifu_dec_dec_bp_dec_tlu_bpred_disable; // @[quasar.scala 73:19] - wire dec_io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[quasar.scala 73:19] - wire dec_io_dec_exu_dec_alu_dec_csr_ren_d; // @[quasar.scala 73:19] - wire [11:0] dec_io_dec_exu_dec_alu_dec_i0_br_immed_d; // @[quasar.scala 73:19] - wire [30:0] dec_io_dec_exu_dec_alu_exu_i0_pc_x; // @[quasar.scala 73:19] - wire dec_io_dec_exu_dec_div_div_p_valid; // @[quasar.scala 73:19] - wire dec_io_dec_exu_dec_div_div_p_bits_unsign; // @[quasar.scala 73:19] - wire dec_io_dec_exu_dec_div_div_p_bits_rem; // @[quasar.scala 73:19] - wire dec_io_dec_exu_dec_div_dec_div_cancel; // @[quasar.scala 73:19] - wire [1:0] dec_io_dec_exu_decode_exu_dec_data_en; // @[quasar.scala 73:19] - wire [1:0] dec_io_dec_exu_decode_exu_dec_ctl_en; // @[quasar.scala 73:19] - wire dec_io_dec_exu_decode_exu_i0_ap_land; // @[quasar.scala 73:19] - wire dec_io_dec_exu_decode_exu_i0_ap_lor; // @[quasar.scala 73:19] - wire dec_io_dec_exu_decode_exu_i0_ap_lxor; // @[quasar.scala 73:19] - wire dec_io_dec_exu_decode_exu_i0_ap_sll; // @[quasar.scala 73:19] - wire dec_io_dec_exu_decode_exu_i0_ap_srl; // @[quasar.scala 73:19] - wire dec_io_dec_exu_decode_exu_i0_ap_sra; // @[quasar.scala 73:19] - wire dec_io_dec_exu_decode_exu_i0_ap_beq; // @[quasar.scala 73:19] - wire dec_io_dec_exu_decode_exu_i0_ap_bne; // @[quasar.scala 73:19] - wire dec_io_dec_exu_decode_exu_i0_ap_blt; // @[quasar.scala 73:19] - wire dec_io_dec_exu_decode_exu_i0_ap_bge; // @[quasar.scala 73:19] - wire dec_io_dec_exu_decode_exu_i0_ap_add; // @[quasar.scala 73:19] - wire dec_io_dec_exu_decode_exu_i0_ap_sub; // @[quasar.scala 73:19] - wire dec_io_dec_exu_decode_exu_i0_ap_slt; // @[quasar.scala 73:19] - wire dec_io_dec_exu_decode_exu_i0_ap_unsign; // @[quasar.scala 73:19] - wire dec_io_dec_exu_decode_exu_i0_ap_jal; // @[quasar.scala 73:19] - wire dec_io_dec_exu_decode_exu_i0_ap_predict_t; // @[quasar.scala 73:19] - wire dec_io_dec_exu_decode_exu_i0_ap_predict_nt; // @[quasar.scala 73:19] - wire dec_io_dec_exu_decode_exu_i0_ap_csr_write; // @[quasar.scala 73:19] - wire dec_io_dec_exu_decode_exu_i0_ap_csr_imm; // @[quasar.scala 73:19] - wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid; // @[quasar.scala 73:19] - wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[quasar.scala 73:19] - wire [1:0] dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist; // @[quasar.scala 73:19] - wire [11:0] dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[quasar.scala 73:19] - wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[quasar.scala 73:19] - wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[quasar.scala 73:19] - wire [30:0] dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett; // @[quasar.scala 73:19] - wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[quasar.scala 73:19] - wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret; // @[quasar.scala 73:19] - wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja; // @[quasar.scala 73:19] - wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way; // @[quasar.scala 73:19] - wire [7:0] dec_io_dec_exu_decode_exu_i0_predict_fghr_d; // @[quasar.scala 73:19] - wire [7:0] dec_io_dec_exu_decode_exu_i0_predict_index_d; // @[quasar.scala 73:19] - wire [4:0] dec_io_dec_exu_decode_exu_i0_predict_btag_d; // @[quasar.scala 73:19] - wire dec_io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[quasar.scala 73:19] - wire dec_io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[quasar.scala 73:19] - wire [31:0] dec_io_dec_exu_decode_exu_dec_i0_immed_d; // @[quasar.scala 73:19] - wire [31:0] dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_data_d; // @[quasar.scala 73:19] - wire [31:0] dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_data_d; // @[quasar.scala 73:19] - wire dec_io_dec_exu_decode_exu_dec_i0_select_pc_d; // @[quasar.scala 73:19] - wire [1:0] dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d; // @[quasar.scala 73:19] - wire [1:0] dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d; // @[quasar.scala 73:19] - wire dec_io_dec_exu_decode_exu_mul_p_valid; // @[quasar.scala 73:19] - wire dec_io_dec_exu_decode_exu_mul_p_bits_rs1_sign; // @[quasar.scala 73:19] - wire dec_io_dec_exu_decode_exu_mul_p_bits_rs2_sign; // @[quasar.scala 73:19] - wire dec_io_dec_exu_decode_exu_mul_p_bits_low; // @[quasar.scala 73:19] - wire [30:0] dec_io_dec_exu_decode_exu_pred_correct_npc_x; // @[quasar.scala 73:19] - wire dec_io_dec_exu_decode_exu_dec_extint_stall; // @[quasar.scala 73:19] - wire [31:0] dec_io_dec_exu_decode_exu_exu_i0_result_x; // @[quasar.scala 73:19] - wire [31:0] dec_io_dec_exu_decode_exu_exu_csr_rs1_x; // @[quasar.scala 73:19] - wire [29:0] dec_io_dec_exu_tlu_exu_dec_tlu_meihap; // @[quasar.scala 73:19] - wire dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 73:19] - wire [30:0] dec_io_dec_exu_tlu_exu_dec_tlu_flush_path_r; // @[quasar.scala 73:19] - wire [1:0] dec_io_dec_exu_tlu_exu_exu_i0_br_hist_r; // @[quasar.scala 73:19] - wire dec_io_dec_exu_tlu_exu_exu_i0_br_error_r; // @[quasar.scala 73:19] - wire dec_io_dec_exu_tlu_exu_exu_i0_br_start_error_r; // @[quasar.scala 73:19] - wire dec_io_dec_exu_tlu_exu_exu_i0_br_valid_r; // @[quasar.scala 73:19] - wire dec_io_dec_exu_tlu_exu_exu_i0_br_mp_r; // @[quasar.scala 73:19] - wire dec_io_dec_exu_tlu_exu_exu_i0_br_middle_r; // @[quasar.scala 73:19] - wire dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp; // @[quasar.scala 73:19] - wire dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken; // @[quasar.scala 73:19] - wire dec_io_dec_exu_tlu_exu_exu_pmu_i0_pc4; // @[quasar.scala 73:19] - wire [30:0] dec_io_dec_exu_tlu_exu_exu_npc_r; // @[quasar.scala 73:19] - wire [30:0] dec_io_dec_exu_ib_exu_dec_i0_pc_d; // @[quasar.scala 73:19] - wire dec_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[quasar.scala 73:19] - wire [31:0] dec_io_dec_exu_gpr_exu_gpr_i0_rs1_d; // @[quasar.scala 73:19] - wire [31:0] dec_io_dec_exu_gpr_exu_gpr_i0_rs2_d; // @[quasar.scala 73:19] - wire dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[quasar.scala 73:19] - wire dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[quasar.scala 73:19] - wire dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 73:19] - wire dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 73:19] - wire dec_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 73:19] - wire dec_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 73:19] - wire dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[quasar.scala 73:19] - wire dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[quasar.scala 73:19] - wire [31:0] dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any; // @[quasar.scala 73:19] - wire dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m; // @[quasar.scala 73:19] - wire [1:0] dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m; // @[quasar.scala 73:19] - wire dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r; // @[quasar.scala 73:19] - wire [1:0] dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[quasar.scala 73:19] - wire dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid; // @[quasar.scala 73:19] - wire dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error; // @[quasar.scala 73:19] - wire [1:0] dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag; // @[quasar.scala 73:19] - wire [31:0] dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data; // @[quasar.scala 73:19] - wire dec_io_lsu_tlu_lsu_pmu_load_external_m; // @[quasar.scala 73:19] - wire dec_io_lsu_tlu_lsu_pmu_store_external_m; // @[quasar.scala 73:19] - wire dec_io_dec_dbg_dbg_ib_dbg_cmd_valid; // @[quasar.scala 73:19] - wire dec_io_dec_dbg_dbg_ib_dbg_cmd_write; // @[quasar.scala 73:19] - wire [1:0] dec_io_dec_dbg_dbg_ib_dbg_cmd_type; // @[quasar.scala 73:19] - wire [31:0] dec_io_dec_dbg_dbg_ib_dbg_cmd_addr; // @[quasar.scala 73:19] - wire [31:0] dec_io_dec_dbg_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 73:19] - wire dec_io_dec_dma_dctl_dma_dma_dccm_stall_any; // @[quasar.scala 73:19] - wire dec_io_dec_dma_tlu_dma_dma_pmu_dccm_read; // @[quasar.scala 73:19] - wire dec_io_dec_dma_tlu_dma_dma_pmu_dccm_write; // @[quasar.scala 73:19] - wire dec_io_dec_dma_tlu_dma_dma_pmu_any_read; // @[quasar.scala 73:19] - wire dec_io_dec_dma_tlu_dma_dma_pmu_any_write; // @[quasar.scala 73:19] - wire [2:0] dec_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty; // @[quasar.scala 73:19] - wire dec_io_dec_dma_tlu_dma_dma_dccm_stall_any; // @[quasar.scala 73:19] - wire dec_io_dec_dma_tlu_dma_dma_iccm_stall_any; // @[quasar.scala 73:19] - wire [7:0] dec_io_dec_pic_pic_claimid; // @[quasar.scala 73:19] - wire [3:0] dec_io_dec_pic_pic_pl; // @[quasar.scala 73:19] - wire dec_io_dec_pic_mhwakeup; // @[quasar.scala 73:19] - wire [3:0] dec_io_dec_pic_dec_tlu_meicurpl; // @[quasar.scala 73:19] - wire [3:0] dec_io_dec_pic_dec_tlu_meipt; // @[quasar.scala 73:19] - wire dec_io_dec_pic_mexintpend; // @[quasar.scala 73:19] - wire dbg_clock; // @[quasar.scala 74:19] - wire dbg_reset; // @[quasar.scala 74:19] - wire [1:0] dbg_io_dbg_cmd_size; // @[quasar.scala 74:19] - wire dbg_io_dbg_core_rst_l; // @[quasar.scala 74:19] - wire [31:0] dbg_io_core_dbg_rddata; // @[quasar.scala 74:19] - wire dbg_io_core_dbg_cmd_done; // @[quasar.scala 74:19] - wire dbg_io_core_dbg_cmd_fail; // @[quasar.scala 74:19] - wire dbg_io_dbg_halt_req; // @[quasar.scala 74:19] - wire dbg_io_dbg_resume_req; // @[quasar.scala 74:19] - wire dbg_io_dec_tlu_debug_mode; // @[quasar.scala 74:19] - wire dbg_io_dec_tlu_dbg_halted; // @[quasar.scala 74:19] - wire dbg_io_dec_tlu_mpc_halted_only; // @[quasar.scala 74:19] - wire dbg_io_dec_tlu_resume_ack; // @[quasar.scala 74:19] - wire dbg_io_dmi_reg_en; // @[quasar.scala 74:19] - wire [6:0] dbg_io_dmi_reg_addr; // @[quasar.scala 74:19] - wire dbg_io_dmi_reg_wr_en; // @[quasar.scala 74:19] - wire [31:0] dbg_io_dmi_reg_wdata; // @[quasar.scala 74:19] - wire dbg_io_sb_axi_aw_ready; // @[quasar.scala 74:19] - wire dbg_io_sb_axi_aw_valid; // @[quasar.scala 74:19] - wire dbg_io_sb_axi_w_ready; // @[quasar.scala 74:19] - wire dbg_io_sb_axi_w_valid; // @[quasar.scala 74:19] - wire [63:0] dbg_io_sb_axi_w_bits_data; // @[quasar.scala 74:19] - wire dbg_io_sb_axi_b_ready; // @[quasar.scala 74:19] - wire dbg_io_sb_axi_b_valid; // @[quasar.scala 74:19] - wire [1:0] dbg_io_sb_axi_b_bits_resp; // @[quasar.scala 74:19] - wire dbg_io_sb_axi_ar_ready; // @[quasar.scala 74:19] - wire dbg_io_sb_axi_ar_valid; // @[quasar.scala 74:19] - wire dbg_io_sb_axi_r_ready; // @[quasar.scala 74:19] - wire dbg_io_sb_axi_r_valid; // @[quasar.scala 74:19] - wire [63:0] dbg_io_sb_axi_r_bits_data; // @[quasar.scala 74:19] - wire [1:0] dbg_io_sb_axi_r_bits_resp; // @[quasar.scala 74:19] - wire dbg_io_dbg_dec_dbg_ib_dbg_cmd_valid; // @[quasar.scala 74:19] - wire dbg_io_dbg_dec_dbg_ib_dbg_cmd_write; // @[quasar.scala 74:19] - wire [1:0] dbg_io_dbg_dec_dbg_ib_dbg_cmd_type; // @[quasar.scala 74:19] - wire [31:0] dbg_io_dbg_dec_dbg_ib_dbg_cmd_addr; // @[quasar.scala 74:19] - wire [31:0] dbg_io_dbg_dec_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 74:19] - wire dbg_io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[quasar.scala 74:19] - wire dbg_io_dbg_dma_dbg_ib_dbg_cmd_write; // @[quasar.scala 74:19] - wire [1:0] dbg_io_dbg_dma_dbg_ib_dbg_cmd_type; // @[quasar.scala 74:19] - wire [31:0] dbg_io_dbg_dma_dbg_ib_dbg_cmd_addr; // @[quasar.scala 74:19] - wire [31:0] dbg_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 74:19] - wire dbg_io_dbg_dma_io_dbg_dma_bubble; // @[quasar.scala 74:19] - wire dbg_io_dbg_dma_io_dma_dbg_ready; // @[quasar.scala 74:19] - wire dbg_io_dbg_bus_clk_en; // @[quasar.scala 74:19] - wire dbg_io_dbg_rst_l; // @[quasar.scala 74:19] - wire dbg_io_clk_override; // @[quasar.scala 74:19] - wire dbg_io_scan_mode; // @[quasar.scala 74:19] - wire exu_clock; // @[quasar.scala 75:19] - wire exu_reset; // @[quasar.scala 75:19] - wire exu_io_scan_mode; // @[quasar.scala 75:19] - wire exu_io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[quasar.scala 75:19] - wire exu_io_dec_exu_dec_alu_dec_csr_ren_d; // @[quasar.scala 75:19] - wire [11:0] exu_io_dec_exu_dec_alu_dec_i0_br_immed_d; // @[quasar.scala 75:19] - wire [30:0] exu_io_dec_exu_dec_alu_exu_i0_pc_x; // @[quasar.scala 75:19] - wire exu_io_dec_exu_dec_div_div_p_valid; // @[quasar.scala 75:19] - wire exu_io_dec_exu_dec_div_div_p_bits_unsign; // @[quasar.scala 75:19] - wire exu_io_dec_exu_dec_div_div_p_bits_rem; // @[quasar.scala 75:19] - wire exu_io_dec_exu_dec_div_dec_div_cancel; // @[quasar.scala 75:19] - wire [1:0] exu_io_dec_exu_decode_exu_dec_data_en; // @[quasar.scala 75:19] - wire [1:0] exu_io_dec_exu_decode_exu_dec_ctl_en; // @[quasar.scala 75:19] - wire exu_io_dec_exu_decode_exu_i0_ap_land; // @[quasar.scala 75:19] - wire exu_io_dec_exu_decode_exu_i0_ap_lor; // @[quasar.scala 75:19] - wire exu_io_dec_exu_decode_exu_i0_ap_lxor; // @[quasar.scala 75:19] - wire exu_io_dec_exu_decode_exu_i0_ap_sll; // @[quasar.scala 75:19] - wire exu_io_dec_exu_decode_exu_i0_ap_srl; // @[quasar.scala 75:19] - wire exu_io_dec_exu_decode_exu_i0_ap_sra; // @[quasar.scala 75:19] - wire exu_io_dec_exu_decode_exu_i0_ap_beq; // @[quasar.scala 75:19] - wire exu_io_dec_exu_decode_exu_i0_ap_bne; // @[quasar.scala 75:19] - wire exu_io_dec_exu_decode_exu_i0_ap_blt; // @[quasar.scala 75:19] - wire exu_io_dec_exu_decode_exu_i0_ap_bge; // @[quasar.scala 75:19] - wire exu_io_dec_exu_decode_exu_i0_ap_add; // @[quasar.scala 75:19] - wire exu_io_dec_exu_decode_exu_i0_ap_sub; // @[quasar.scala 75:19] - wire exu_io_dec_exu_decode_exu_i0_ap_slt; // @[quasar.scala 75:19] - wire exu_io_dec_exu_decode_exu_i0_ap_unsign; // @[quasar.scala 75:19] - wire exu_io_dec_exu_decode_exu_i0_ap_jal; // @[quasar.scala 75:19] - wire exu_io_dec_exu_decode_exu_i0_ap_predict_t; // @[quasar.scala 75:19] - wire exu_io_dec_exu_decode_exu_i0_ap_predict_nt; // @[quasar.scala 75:19] - wire exu_io_dec_exu_decode_exu_i0_ap_csr_write; // @[quasar.scala 75:19] - wire exu_io_dec_exu_decode_exu_i0_ap_csr_imm; // @[quasar.scala 75:19] - wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid; // @[quasar.scala 75:19] - wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[quasar.scala 75:19] - wire [1:0] exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist; // @[quasar.scala 75:19] - wire [11:0] exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[quasar.scala 75:19] - wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[quasar.scala 75:19] - wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[quasar.scala 75:19] - wire [30:0] exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett; // @[quasar.scala 75:19] - wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[quasar.scala 75:19] - wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret; // @[quasar.scala 75:19] - wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja; // @[quasar.scala 75:19] - wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way; // @[quasar.scala 75:19] - wire [7:0] exu_io_dec_exu_decode_exu_i0_predict_fghr_d; // @[quasar.scala 75:19] - wire [7:0] exu_io_dec_exu_decode_exu_i0_predict_index_d; // @[quasar.scala 75:19] - wire [4:0] exu_io_dec_exu_decode_exu_i0_predict_btag_d; // @[quasar.scala 75:19] - wire exu_io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[quasar.scala 75:19] - wire exu_io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[quasar.scala 75:19] - wire [31:0] exu_io_dec_exu_decode_exu_dec_i0_immed_d; // @[quasar.scala 75:19] - wire [31:0] exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_data_d; // @[quasar.scala 75:19] - wire [31:0] exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_data_d; // @[quasar.scala 75:19] - wire exu_io_dec_exu_decode_exu_dec_i0_select_pc_d; // @[quasar.scala 75:19] - wire [1:0] exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d; // @[quasar.scala 75:19] - wire [1:0] exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d; // @[quasar.scala 75:19] - wire exu_io_dec_exu_decode_exu_mul_p_valid; // @[quasar.scala 75:19] - wire exu_io_dec_exu_decode_exu_mul_p_bits_rs1_sign; // @[quasar.scala 75:19] - wire exu_io_dec_exu_decode_exu_mul_p_bits_rs2_sign; // @[quasar.scala 75:19] - wire exu_io_dec_exu_decode_exu_mul_p_bits_low; // @[quasar.scala 75:19] - wire [30:0] exu_io_dec_exu_decode_exu_pred_correct_npc_x; // @[quasar.scala 75:19] - wire exu_io_dec_exu_decode_exu_dec_extint_stall; // @[quasar.scala 75:19] - wire [31:0] exu_io_dec_exu_decode_exu_exu_i0_result_x; // @[quasar.scala 75:19] - wire [31:0] exu_io_dec_exu_decode_exu_exu_csr_rs1_x; // @[quasar.scala 75:19] - wire [29:0] exu_io_dec_exu_tlu_exu_dec_tlu_meihap; // @[quasar.scala 75:19] - wire exu_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 75:19] - wire [30:0] exu_io_dec_exu_tlu_exu_dec_tlu_flush_path_r; // @[quasar.scala 75:19] - wire [1:0] exu_io_dec_exu_tlu_exu_exu_i0_br_hist_r; // @[quasar.scala 75:19] - wire exu_io_dec_exu_tlu_exu_exu_i0_br_error_r; // @[quasar.scala 75:19] - wire exu_io_dec_exu_tlu_exu_exu_i0_br_start_error_r; // @[quasar.scala 75:19] - wire [7:0] exu_io_dec_exu_tlu_exu_exu_i0_br_index_r; // @[quasar.scala 75:19] - wire exu_io_dec_exu_tlu_exu_exu_i0_br_valid_r; // @[quasar.scala 75:19] - wire exu_io_dec_exu_tlu_exu_exu_i0_br_mp_r; // @[quasar.scala 75:19] - wire exu_io_dec_exu_tlu_exu_exu_i0_br_middle_r; // @[quasar.scala 75:19] - wire exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp; // @[quasar.scala 75:19] - wire exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken; // @[quasar.scala 75:19] - wire exu_io_dec_exu_tlu_exu_exu_pmu_i0_pc4; // @[quasar.scala 75:19] - wire [30:0] exu_io_dec_exu_tlu_exu_exu_npc_r; // @[quasar.scala 75:19] - wire [30:0] exu_io_dec_exu_ib_exu_dec_i0_pc_d; // @[quasar.scala 75:19] - wire exu_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[quasar.scala 75:19] - wire [31:0] exu_io_dec_exu_gpr_exu_gpr_i0_rs1_d; // @[quasar.scala 75:19] - wire [31:0] exu_io_dec_exu_gpr_exu_gpr_i0_rs2_d; // @[quasar.scala 75:19] - wire [7:0] exu_io_exu_bp_exu_i0_br_fghr_r; // @[quasar.scala 75:19] - wire exu_io_exu_bp_exu_i0_br_way_r; // @[quasar.scala 75:19] - wire exu_io_exu_bp_exu_mp_pkt_bits_misp; // @[quasar.scala 75:19] - wire exu_io_exu_bp_exu_mp_pkt_bits_ataken; // @[quasar.scala 75:19] - wire exu_io_exu_bp_exu_mp_pkt_bits_boffset; // @[quasar.scala 75:19] - wire exu_io_exu_bp_exu_mp_pkt_bits_pc4; // @[quasar.scala 75:19] - wire [1:0] exu_io_exu_bp_exu_mp_pkt_bits_hist; // @[quasar.scala 75:19] - wire [11:0] exu_io_exu_bp_exu_mp_pkt_bits_toffset; // @[quasar.scala 75:19] - wire exu_io_exu_bp_exu_mp_pkt_bits_pcall; // @[quasar.scala 75:19] - wire exu_io_exu_bp_exu_mp_pkt_bits_pret; // @[quasar.scala 75:19] - wire exu_io_exu_bp_exu_mp_pkt_bits_pja; // @[quasar.scala 75:19] - wire exu_io_exu_bp_exu_mp_pkt_bits_way; // @[quasar.scala 75:19] - wire [7:0] exu_io_exu_bp_exu_mp_eghr; // @[quasar.scala 75:19] - wire [7:0] exu_io_exu_bp_exu_mp_fghr; // @[quasar.scala 75:19] - wire [7:0] exu_io_exu_bp_exu_mp_index; // @[quasar.scala 75:19] - wire [4:0] exu_io_exu_bp_exu_mp_btag; // @[quasar.scala 75:19] - wire exu_io_exu_flush_final; // @[quasar.scala 75:19] - wire [31:0] exu_io_exu_div_result; // @[quasar.scala 75:19] - wire exu_io_exu_div_wren; // @[quasar.scala 75:19] - wire [31:0] exu_io_dbg_cmd_wrdata; // @[quasar.scala 75:19] - wire [31:0] exu_io_lsu_exu_exu_lsu_rs1_d; // @[quasar.scala 75:19] - wire [31:0] exu_io_lsu_exu_exu_lsu_rs2_d; // @[quasar.scala 75:19] - wire [30:0] exu_io_exu_flush_path_final; // @[quasar.scala 75:19] - wire lsu_clock; // @[quasar.scala 76:19] - wire lsu_reset; // @[quasar.scala 76:19] - wire lsu_io_clk_override; // @[quasar.scala 76:19] - wire lsu_io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[quasar.scala 76:19] - wire [31:0] lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[quasar.scala 76:19] - wire [2:0] lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[quasar.scala 76:19] - wire lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[quasar.scala 76:19] - wire [63:0] lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[quasar.scala 76:19] - wire [31:0] lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_addr; // @[quasar.scala 76:19] - wire [63:0] lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata; // @[quasar.scala 76:19] - wire lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid; // @[quasar.scala 76:19] - wire lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[quasar.scala 76:19] - wire [2:0] lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[quasar.scala 76:19] - wire [63:0] lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata; // @[quasar.scala 76:19] - wire lsu_io_lsu_dma_dccm_ready; // @[quasar.scala 76:19] - wire [2:0] lsu_io_lsu_dma_dma_mem_tag; // @[quasar.scala 76:19] - wire lsu_io_lsu_pic_picm_wren; // @[quasar.scala 76:19] - wire lsu_io_lsu_pic_picm_rden; // @[quasar.scala 76:19] - wire lsu_io_lsu_pic_picm_mken; // @[quasar.scala 76:19] - wire [31:0] lsu_io_lsu_pic_picm_rdaddr; // @[quasar.scala 76:19] - wire [31:0] lsu_io_lsu_pic_picm_wraddr; // @[quasar.scala 76:19] - wire [31:0] lsu_io_lsu_pic_picm_wr_data; // @[quasar.scala 76:19] - wire [31:0] lsu_io_lsu_pic_picm_rd_data; // @[quasar.scala 76:19] - wire [31:0] lsu_io_lsu_exu_exu_lsu_rs1_d; // @[quasar.scala 76:19] - wire [31:0] lsu_io_lsu_exu_exu_lsu_rs2_d; // @[quasar.scala 76:19] - wire lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[quasar.scala 76:19] - wire lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[quasar.scala 76:19] - wire lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 76:19] - wire lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 76:19] - wire lsu_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 76:19] - wire lsu_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 76:19] - wire lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[quasar.scala 76:19] - wire lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[quasar.scala 76:19] - wire [31:0] lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any; // @[quasar.scala 76:19] - wire lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m; // @[quasar.scala 76:19] - wire [1:0] lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m; // @[quasar.scala 76:19] - wire lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r; // @[quasar.scala 76:19] - wire [1:0] lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[quasar.scala 76:19] - wire lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid; // @[quasar.scala 76:19] - wire lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error; // @[quasar.scala 76:19] - wire [1:0] lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag; // @[quasar.scala 76:19] - wire [31:0] lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data; // @[quasar.scala 76:19] - wire lsu_io_dccm_wren; // @[quasar.scala 76:19] - wire lsu_io_dccm_rden; // @[quasar.scala 76:19] - wire [15:0] lsu_io_dccm_wr_addr_lo; // @[quasar.scala 76:19] - wire [15:0] lsu_io_dccm_wr_addr_hi; // @[quasar.scala 76:19] - wire [15:0] lsu_io_dccm_rd_addr_lo; // @[quasar.scala 76:19] - wire [15:0] lsu_io_dccm_rd_addr_hi; // @[quasar.scala 76:19] - wire [38:0] lsu_io_dccm_wr_data_lo; // @[quasar.scala 76:19] - wire [38:0] lsu_io_dccm_wr_data_hi; // @[quasar.scala 76:19] - wire [38:0] lsu_io_dccm_rd_data_lo; // @[quasar.scala 76:19] - wire [38:0] lsu_io_dccm_rd_data_hi; // @[quasar.scala 76:19] - wire lsu_io_lsu_tlu_lsu_pmu_load_external_m; // @[quasar.scala 76:19] - wire lsu_io_lsu_tlu_lsu_pmu_store_external_m; // @[quasar.scala 76:19] - wire lsu_io_axi_aw_ready; // @[quasar.scala 76:19] - wire lsu_io_axi_aw_valid; // @[quasar.scala 76:19] - wire [2:0] lsu_io_axi_aw_bits_id; // @[quasar.scala 76:19] - wire lsu_io_axi_w_ready; // @[quasar.scala 76:19] - wire lsu_io_axi_w_valid; // @[quasar.scala 76:19] - wire [63:0] lsu_io_axi_w_bits_data; // @[quasar.scala 76:19] - wire lsu_io_axi_b_valid; // @[quasar.scala 76:19] - wire [2:0] lsu_io_axi_b_bits_id; // @[quasar.scala 76:19] - wire lsu_io_axi_ar_ready; // @[quasar.scala 76:19] - wire lsu_io_axi_ar_valid; // @[quasar.scala 76:19] - wire [2:0] lsu_io_axi_ar_bits_id; // @[quasar.scala 76:19] - wire lsu_io_axi_r_valid; // @[quasar.scala 76:19] - wire [2:0] lsu_io_axi_r_bits_id; // @[quasar.scala 76:19] - wire [63:0] lsu_io_axi_r_bits_data; // @[quasar.scala 76:19] - wire [1:0] lsu_io_axi_r_bits_resp; // @[quasar.scala 76:19] - wire lsu_io_dec_tlu_flush_lower_r; // @[quasar.scala 76:19] - wire lsu_io_dec_tlu_i0_kill_writeb_r; // @[quasar.scala 76:19] - wire lsu_io_dec_tlu_force_halt; // @[quasar.scala 76:19] - wire lsu_io_dec_tlu_core_ecc_disable; // @[quasar.scala 76:19] - wire [11:0] lsu_io_dec_lsu_offset_d; // @[quasar.scala 76:19] - wire lsu_io_lsu_p_valid; // @[quasar.scala 76:19] - wire lsu_io_lsu_p_bits_fast_int; // @[quasar.scala 76:19] - wire lsu_io_lsu_p_bits_by; // @[quasar.scala 76:19] - wire lsu_io_lsu_p_bits_half; // @[quasar.scala 76:19] - wire lsu_io_lsu_p_bits_word; // @[quasar.scala 76:19] - wire lsu_io_lsu_p_bits_load; // @[quasar.scala 76:19] - wire lsu_io_lsu_p_bits_store; // @[quasar.scala 76:19] - wire lsu_io_lsu_p_bits_unsign; // @[quasar.scala 76:19] - wire lsu_io_lsu_p_bits_store_data_bypass_d; // @[quasar.scala 76:19] - wire lsu_io_lsu_p_bits_load_ldst_bypass_d; // @[quasar.scala 76:19] - wire lsu_io_trigger_pkt_any_0_select; // @[quasar.scala 76:19] - wire lsu_io_trigger_pkt_any_0_match_pkt; // @[quasar.scala 76:19] - wire lsu_io_trigger_pkt_any_0_store; // @[quasar.scala 76:19] - wire lsu_io_trigger_pkt_any_0_load; // @[quasar.scala 76:19] - wire [31:0] lsu_io_trigger_pkt_any_0_tdata2; // @[quasar.scala 76:19] - wire lsu_io_trigger_pkt_any_1_select; // @[quasar.scala 76:19] - wire lsu_io_trigger_pkt_any_1_match_pkt; // @[quasar.scala 76:19] - wire lsu_io_trigger_pkt_any_1_store; // @[quasar.scala 76:19] - wire lsu_io_trigger_pkt_any_1_load; // @[quasar.scala 76:19] - wire [31:0] lsu_io_trigger_pkt_any_1_tdata2; // @[quasar.scala 76:19] - wire lsu_io_trigger_pkt_any_2_select; // @[quasar.scala 76:19] - wire lsu_io_trigger_pkt_any_2_match_pkt; // @[quasar.scala 76:19] - wire lsu_io_trigger_pkt_any_2_store; // @[quasar.scala 76:19] - wire lsu_io_trigger_pkt_any_2_load; // @[quasar.scala 76:19] - wire [31:0] lsu_io_trigger_pkt_any_2_tdata2; // @[quasar.scala 76:19] - wire lsu_io_trigger_pkt_any_3_select; // @[quasar.scala 76:19] - wire lsu_io_trigger_pkt_any_3_match_pkt; // @[quasar.scala 76:19] - wire lsu_io_trigger_pkt_any_3_store; // @[quasar.scala 76:19] - wire lsu_io_trigger_pkt_any_3_load; // @[quasar.scala 76:19] - wire [31:0] lsu_io_trigger_pkt_any_3_tdata2; // @[quasar.scala 76:19] - wire lsu_io_dec_lsu_valid_raw_d; // @[quasar.scala 76:19] - wire [31:0] lsu_io_dec_tlu_mrac_ff; // @[quasar.scala 76:19] - wire [31:0] lsu_io_lsu_result_m; // @[quasar.scala 76:19] - wire [31:0] lsu_io_lsu_result_corr_r; // @[quasar.scala 76:19] - wire lsu_io_lsu_load_stall_any; // @[quasar.scala 76:19] - wire lsu_io_lsu_store_stall_any; // @[quasar.scala 76:19] - wire lsu_io_lsu_fastint_stall_any; // @[quasar.scala 76:19] - wire lsu_io_lsu_idle_any; // @[quasar.scala 76:19] - wire [30:0] lsu_io_lsu_fir_addr; // @[quasar.scala 76:19] - wire [1:0] lsu_io_lsu_fir_error; // @[quasar.scala 76:19] - wire lsu_io_lsu_single_ecc_error_incr; // @[quasar.scala 76:19] - wire lsu_io_lsu_error_pkt_r_valid; // @[quasar.scala 76:19] - wire lsu_io_lsu_error_pkt_r_bits_single_ecc_error; // @[quasar.scala 76:19] - wire lsu_io_lsu_error_pkt_r_bits_inst_type; // @[quasar.scala 76:19] - wire lsu_io_lsu_error_pkt_r_bits_exc_type; // @[quasar.scala 76:19] - wire [3:0] lsu_io_lsu_error_pkt_r_bits_mscause; // @[quasar.scala 76:19] - wire [31:0] lsu_io_lsu_error_pkt_r_bits_addr; // @[quasar.scala 76:19] - wire lsu_io_lsu_pmu_misaligned_m; // @[quasar.scala 76:19] - wire [3:0] lsu_io_lsu_trigger_match_m; // @[quasar.scala 76:19] - wire lsu_io_lsu_bus_clk_en; // @[quasar.scala 76:19] - wire lsu_io_scan_mode; // @[quasar.scala 76:19] - wire lsu_io_free_clk; // @[quasar.scala 76:19] - wire pic_ctrl_inst_clock; // @[quasar.scala 77:29] - wire pic_ctrl_inst_reset; // @[quasar.scala 77:29] - wire pic_ctrl_inst_io_scan_mode; // @[quasar.scala 77:29] - wire pic_ctrl_inst_io_free_clk; // @[quasar.scala 77:29] - wire pic_ctrl_inst_io_active_clk; // @[quasar.scala 77:29] - wire pic_ctrl_inst_io_clk_override; // @[quasar.scala 77:29] - wire [31:0] pic_ctrl_inst_io_extintsrc_req; // @[quasar.scala 77:29] - wire pic_ctrl_inst_io_lsu_pic_picm_wren; // @[quasar.scala 77:29] - wire pic_ctrl_inst_io_lsu_pic_picm_rden; // @[quasar.scala 77:29] - wire pic_ctrl_inst_io_lsu_pic_picm_mken; // @[quasar.scala 77:29] - wire [31:0] pic_ctrl_inst_io_lsu_pic_picm_rdaddr; // @[quasar.scala 77:29] - wire [31:0] pic_ctrl_inst_io_lsu_pic_picm_wraddr; // @[quasar.scala 77:29] - wire [31:0] pic_ctrl_inst_io_lsu_pic_picm_wr_data; // @[quasar.scala 77:29] - wire [31:0] pic_ctrl_inst_io_lsu_pic_picm_rd_data; // @[quasar.scala 77:29] - wire [7:0] pic_ctrl_inst_io_dec_pic_pic_claimid; // @[quasar.scala 77:29] - wire [3:0] pic_ctrl_inst_io_dec_pic_pic_pl; // @[quasar.scala 77:29] - wire pic_ctrl_inst_io_dec_pic_mhwakeup; // @[quasar.scala 77:29] - wire [3:0] pic_ctrl_inst_io_dec_pic_dec_tlu_meicurpl; // @[quasar.scala 77:29] - wire [3:0] pic_ctrl_inst_io_dec_pic_dec_tlu_meipt; // @[quasar.scala 77:29] - wire pic_ctrl_inst_io_dec_pic_mexintpend; // @[quasar.scala 77:29] - wire dma_ctrl_clock; // @[quasar.scala 78:24] - wire dma_ctrl_reset; // @[quasar.scala 78:24] - wire dma_ctrl_io_free_clk; // @[quasar.scala 78:24] - wire dma_ctrl_io_dma_bus_clk_en; // @[quasar.scala 78:24] - wire dma_ctrl_io_clk_override; // @[quasar.scala 78:24] - wire dma_ctrl_io_scan_mode; // @[quasar.scala 78:24] - wire [1:0] dma_ctrl_io_dbg_cmd_size; // @[quasar.scala 78:24] - wire [31:0] dma_ctrl_io_dma_dbg_rddata; // @[quasar.scala 78:24] - wire dma_ctrl_io_dma_dbg_cmd_done; // @[quasar.scala 78:24] - wire dma_ctrl_io_dma_dbg_cmd_fail; // @[quasar.scala 78:24] - wire dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[quasar.scala 78:24] - wire dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_write; // @[quasar.scala 78:24] - wire [1:0] dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_type; // @[quasar.scala 78:24] - wire [31:0] dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_addr; // @[quasar.scala 78:24] - wire [31:0] dma_ctrl_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 78:24] - wire dma_ctrl_io_dbg_dma_io_dbg_dma_bubble; // @[quasar.scala 78:24] - wire dma_ctrl_io_dbg_dma_io_dma_dbg_ready; // @[quasar.scala 78:24] - wire dma_ctrl_io_dec_dma_dctl_dma_dma_dccm_stall_any; // @[quasar.scala 78:24] - wire dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_read; // @[quasar.scala 78:24] - wire dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_write; // @[quasar.scala 78:24] - wire dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_read; // @[quasar.scala 78:24] - wire dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_write; // @[quasar.scala 78:24] - wire [2:0] dma_ctrl_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty; // @[quasar.scala 78:24] - wire dma_ctrl_io_dec_dma_tlu_dma_dma_dccm_stall_any; // @[quasar.scala 78:24] - wire dma_ctrl_io_dec_dma_tlu_dma_dma_iccm_stall_any; // @[quasar.scala 78:24] - wire dma_ctrl_io_iccm_dma_rvalid; // @[quasar.scala 78:24] - wire dma_ctrl_io_iccm_dma_ecc_error; // @[quasar.scala 78:24] - wire [2:0] dma_ctrl_io_iccm_dma_rtag; // @[quasar.scala 78:24] - wire [63:0] dma_ctrl_io_iccm_dma_rdata; // @[quasar.scala 78:24] - wire dma_ctrl_io_iccm_ready; // @[quasar.scala 78:24] - wire dma_ctrl_io_dma_axi_b_valid; // @[quasar.scala 78:24] - wire dma_ctrl_io_dma_axi_ar_ready; // @[quasar.scala 78:24] - wire dma_ctrl_io_dma_axi_ar_valid; // @[quasar.scala 78:24] - wire dma_ctrl_io_dma_axi_r_valid; // @[quasar.scala 78:24] - wire [1:0] dma_ctrl_io_dma_axi_r_bits_resp; // @[quasar.scala 78:24] - wire dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[quasar.scala 78:24] - wire [31:0] dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[quasar.scala 78:24] - wire [2:0] dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[quasar.scala 78:24] - wire dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[quasar.scala 78:24] - wire [63:0] dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[quasar.scala 78:24] - wire [31:0] dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_addr; // @[quasar.scala 78:24] - wire [63:0] dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata; // @[quasar.scala 78:24] - wire dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid; // @[quasar.scala 78:24] - wire dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[quasar.scala 78:24] - wire [2:0] dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[quasar.scala 78:24] - wire [63:0] dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata; // @[quasar.scala 78:24] - wire dma_ctrl_io_lsu_dma_dccm_ready; // @[quasar.scala 78:24] - wire [2:0] dma_ctrl_io_lsu_dma_dma_mem_tag; // @[quasar.scala 78:24] - wire dma_ctrl_io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[quasar.scala 78:24] - wire dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[quasar.scala 78:24] - wire [31:0] dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_addr; // @[quasar.scala 78:24] - wire [2:0] dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_sz; // @[quasar.scala 78:24] - wire dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_write; // @[quasar.scala 78:24] - wire [63:0] dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_wdata; // @[quasar.scala 78:24] - wire [2:0] dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_tag; // @[quasar.scala 78:24] + wire ifu_clock; // @[quasar.scala 74:19] + wire ifu_reset; // @[quasar.scala 74:19] + wire ifu_io_exu_flush_final; // @[quasar.scala 74:19] + wire [30:0] ifu_io_exu_flush_path_final; // @[quasar.scala 74:19] + wire ifu_io_free_clk; // @[quasar.scala 74:19] + wire ifu_io_active_clk; // @[quasar.scala 74:19] + wire ifu_io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d; // @[quasar.scala 74:19] + wire [15:0] ifu_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst; // @[quasar.scala 74:19] + wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf; // @[quasar.scala 74:19] + wire [1:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type; // @[quasar.scala 74:19] + wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1; // @[quasar.scala 74:19] + wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc; // @[quasar.scala 74:19] + wire [7:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index; // @[quasar.scala 74:19] + wire [7:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[quasar.scala 74:19] + wire [4:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag; // @[quasar.scala 74:19] + wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid; // @[quasar.scala 74:19] + wire [31:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr; // @[quasar.scala 74:19] + wire [30:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc; // @[quasar.scala 74:19] + wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4; // @[quasar.scala 74:19] + wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid; // @[quasar.scala 74:19] + wire [11:0] ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset; // @[quasar.scala 74:19] + wire [1:0] ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist; // @[quasar.scala 74:19] + wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error; // @[quasar.scala 74:19] + wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[quasar.scala 74:19] + wire [30:0] ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett; // @[quasar.scala 74:19] + wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way; // @[quasar.scala 74:19] + wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret; // @[quasar.scala 74:19] + wire ifu_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned; // @[quasar.scala 74:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[quasar.scala 74:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[quasar.scala 74:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 74:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb; // @[quasar.scala 74:19] + wire [70:0] ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[quasar.scala 74:19] + wire [16:0] ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics; // @[quasar.scala 74:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[quasar.scala 74:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[quasar.scala 74:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 74:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss; // @[quasar.scala 74:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[quasar.scala 74:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[quasar.scala 74:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[quasar.scala 74:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[quasar.scala 74:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[quasar.scala 74:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[quasar.scala 74:19] + wire [70:0] ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[quasar.scala 74:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[quasar.scala 74:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle; // @[quasar.scala 74:19] + wire ifu_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb; // @[quasar.scala 74:19] + wire [31:0] ifu_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 74:19] + wire ifu_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall; // @[quasar.scala 74:19] + wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid; // @[quasar.scala 74:19] + wire [1:0] ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist; // @[quasar.scala 74:19] + wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[quasar.scala 74:19] + wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[quasar.scala 74:19] + wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[quasar.scala 74:19] + wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[quasar.scala 74:19] + wire ifu_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb; // @[quasar.scala 74:19] + wire ifu_io_ifu_dec_dec_bp_dec_tlu_bpred_disable; // @[quasar.scala 74:19] + wire [7:0] ifu_io_exu_ifu_exu_bp_exu_i0_br_index_r; // @[quasar.scala 74:19] + wire [7:0] ifu_io_exu_ifu_exu_bp_exu_i0_br_fghr_r; // @[quasar.scala 74:19] + wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_misp; // @[quasar.scala 74:19] + wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_ataken; // @[quasar.scala 74:19] + wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_boffset; // @[quasar.scala 74:19] + wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pc4; // @[quasar.scala 74:19] + wire [1:0] ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_hist; // @[quasar.scala 74:19] + wire [11:0] ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_toffset; // @[quasar.scala 74:19] + wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pcall; // @[quasar.scala 74:19] + wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pret; // @[quasar.scala 74:19] + wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pja; // @[quasar.scala 74:19] + wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_way; // @[quasar.scala 74:19] + wire [7:0] ifu_io_exu_ifu_exu_bp_exu_mp_eghr; // @[quasar.scala 74:19] + wire [7:0] ifu_io_exu_ifu_exu_bp_exu_mp_fghr; // @[quasar.scala 74:19] + wire [7:0] ifu_io_exu_ifu_exu_bp_exu_mp_index; // @[quasar.scala 74:19] + wire [4:0] ifu_io_exu_ifu_exu_bp_exu_mp_btag; // @[quasar.scala 74:19] + wire [14:0] ifu_io_iccm_rw_addr; // @[quasar.scala 74:19] + wire ifu_io_iccm_buf_correct_ecc; // @[quasar.scala 74:19] + wire ifu_io_iccm_correction_state; // @[quasar.scala 74:19] + wire ifu_io_iccm_wren; // @[quasar.scala 74:19] + wire ifu_io_iccm_rden; // @[quasar.scala 74:19] + wire [2:0] ifu_io_iccm_wr_size; // @[quasar.scala 74:19] + wire [77:0] ifu_io_iccm_wr_data; // @[quasar.scala 74:19] + wire [63:0] ifu_io_iccm_rd_data; // @[quasar.scala 74:19] + wire [77:0] ifu_io_iccm_rd_data_ecc; // @[quasar.scala 74:19] + wire [30:0] ifu_io_ic_rw_addr; // @[quasar.scala 74:19] + wire [1:0] ifu_io_ic_tag_valid; // @[quasar.scala 74:19] + wire [1:0] ifu_io_ic_wr_en; // @[quasar.scala 74:19] + wire ifu_io_ic_rd_en; // @[quasar.scala 74:19] + wire [70:0] ifu_io_ic_wr_data_0; // @[quasar.scala 74:19] + wire [70:0] ifu_io_ic_wr_data_1; // @[quasar.scala 74:19] + wire [70:0] ifu_io_ic_debug_wr_data; // @[quasar.scala 74:19] + wire [9:0] ifu_io_ic_debug_addr; // @[quasar.scala 74:19] + wire [63:0] ifu_io_ic_rd_data; // @[quasar.scala 74:19] + wire [70:0] ifu_io_ic_debug_rd_data; // @[quasar.scala 74:19] + wire [25:0] ifu_io_ic_tag_debug_rd_data; // @[quasar.scala 74:19] + wire [1:0] ifu_io_ic_eccerr; // @[quasar.scala 74:19] + wire [1:0] ifu_io_ic_rd_hit; // @[quasar.scala 74:19] + wire ifu_io_ic_tag_perr; // @[quasar.scala 74:19] + wire ifu_io_ic_debug_rd_en; // @[quasar.scala 74:19] + wire ifu_io_ic_debug_wr_en; // @[quasar.scala 74:19] + wire ifu_io_ic_debug_tag_array; // @[quasar.scala 74:19] + wire [1:0] ifu_io_ic_debug_way; // @[quasar.scala 74:19] + wire [63:0] ifu_io_ic_premux_data; // @[quasar.scala 74:19] + wire ifu_io_ic_sel_premux_data; // @[quasar.scala 74:19] + wire ifu_io_ifu_ar_ready; // @[quasar.scala 74:19] + wire ifu_io_ifu_ar_valid; // @[quasar.scala 74:19] + wire [2:0] ifu_io_ifu_ar_bits_id; // @[quasar.scala 74:19] + wire [31:0] ifu_io_ifu_ar_bits_addr; // @[quasar.scala 74:19] + wire ifu_io_ifu_r_valid; // @[quasar.scala 74:19] + wire [2:0] ifu_io_ifu_r_bits_id; // @[quasar.scala 74:19] + wire [63:0] ifu_io_ifu_r_bits_data; // @[quasar.scala 74:19] + wire [1:0] ifu_io_ifu_r_bits_resp; // @[quasar.scala 74:19] + wire ifu_io_ifu_bus_clk_en; // @[quasar.scala 74:19] + wire ifu_io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[quasar.scala 74:19] + wire ifu_io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[quasar.scala 74:19] + wire [31:0] ifu_io_ifu_dma_dma_mem_ctl_dma_mem_addr; // @[quasar.scala 74:19] + wire [2:0] ifu_io_ifu_dma_dma_mem_ctl_dma_mem_sz; // @[quasar.scala 74:19] + wire ifu_io_ifu_dma_dma_mem_ctl_dma_mem_write; // @[quasar.scala 74:19] + wire [63:0] ifu_io_ifu_dma_dma_mem_ctl_dma_mem_wdata; // @[quasar.scala 74:19] + wire [2:0] ifu_io_ifu_dma_dma_mem_ctl_dma_mem_tag; // @[quasar.scala 74:19] + wire ifu_io_iccm_dma_ecc_error; // @[quasar.scala 74:19] + wire ifu_io_iccm_dma_rvalid; // @[quasar.scala 74:19] + wire [63:0] ifu_io_iccm_dma_rdata; // @[quasar.scala 74:19] + wire [2:0] ifu_io_iccm_dma_rtag; // @[quasar.scala 74:19] + wire ifu_io_iccm_ready; // @[quasar.scala 74:19] + wire ifu_io_iccm_dma_sb_error; // @[quasar.scala 74:19] + wire ifu_io_dec_tlu_flush_lower_wb; // @[quasar.scala 74:19] + wire ifu_io_scan_mode; // @[quasar.scala 74:19] + wire dec_clock; // @[quasar.scala 75:19] + wire dec_reset; // @[quasar.scala 75:19] + wire dec_io_free_clk; // @[quasar.scala 75:19] + wire dec_io_active_clk; // @[quasar.scala 75:19] + wire dec_io_lsu_fastint_stall_any; // @[quasar.scala 75:19] + wire dec_io_dec_pause_state_cg; // @[quasar.scala 75:19] + wire [30:0] dec_io_rst_vec; // @[quasar.scala 75:19] + wire dec_io_nmi_int; // @[quasar.scala 75:19] + wire [30:0] dec_io_nmi_vec; // @[quasar.scala 75:19] + wire dec_io_i_cpu_halt_req; // @[quasar.scala 75:19] + wire dec_io_i_cpu_run_req; // @[quasar.scala 75:19] + wire dec_io_o_cpu_halt_status; // @[quasar.scala 75:19] + wire dec_io_o_cpu_halt_ack; // @[quasar.scala 75:19] + wire dec_io_o_cpu_run_ack; // @[quasar.scala 75:19] + wire dec_io_o_debug_mode_status; // @[quasar.scala 75:19] + wire [27:0] dec_io_core_id; // @[quasar.scala 75:19] + wire dec_io_mpc_debug_halt_req; // @[quasar.scala 75:19] + wire dec_io_mpc_debug_run_req; // @[quasar.scala 75:19] + wire dec_io_mpc_reset_run_req; // @[quasar.scala 75:19] + wire dec_io_mpc_debug_halt_ack; // @[quasar.scala 75:19] + wire dec_io_mpc_debug_run_ack; // @[quasar.scala 75:19] + wire dec_io_debug_brkpt_status; // @[quasar.scala 75:19] + wire dec_io_lsu_pmu_misaligned_m; // @[quasar.scala 75:19] + wire [30:0] dec_io_lsu_fir_addr; // @[quasar.scala 75:19] + wire [1:0] dec_io_lsu_fir_error; // @[quasar.scala 75:19] + wire [3:0] dec_io_lsu_trigger_match_m; // @[quasar.scala 75:19] + wire dec_io_lsu_idle_any; // @[quasar.scala 75:19] + wire dec_io_lsu_error_pkt_r_valid; // @[quasar.scala 75:19] + wire dec_io_lsu_error_pkt_r_bits_single_ecc_error; // @[quasar.scala 75:19] + wire dec_io_lsu_error_pkt_r_bits_inst_type; // @[quasar.scala 75:19] + wire dec_io_lsu_error_pkt_r_bits_exc_type; // @[quasar.scala 75:19] + wire [3:0] dec_io_lsu_error_pkt_r_bits_mscause; // @[quasar.scala 75:19] + wire [31:0] dec_io_lsu_error_pkt_r_bits_addr; // @[quasar.scala 75:19] + wire dec_io_lsu_single_ecc_error_incr; // @[quasar.scala 75:19] + wire [31:0] dec_io_exu_div_result; // @[quasar.scala 75:19] + wire dec_io_exu_div_wren; // @[quasar.scala 75:19] + wire [31:0] dec_io_lsu_result_m; // @[quasar.scala 75:19] + wire [31:0] dec_io_lsu_result_corr_r; // @[quasar.scala 75:19] + wire dec_io_lsu_load_stall_any; // @[quasar.scala 75:19] + wire dec_io_lsu_store_stall_any; // @[quasar.scala 75:19] + wire dec_io_iccm_dma_sb_error; // @[quasar.scala 75:19] + wire dec_io_exu_flush_final; // @[quasar.scala 75:19] + wire dec_io_timer_int; // @[quasar.scala 75:19] + wire dec_io_soft_int; // @[quasar.scala 75:19] + wire dec_io_dbg_halt_req; // @[quasar.scala 75:19] + wire dec_io_dbg_resume_req; // @[quasar.scala 75:19] + wire dec_io_dec_tlu_dbg_halted; // @[quasar.scala 75:19] + wire dec_io_dec_tlu_debug_mode; // @[quasar.scala 75:19] + wire dec_io_dec_tlu_resume_ack; // @[quasar.scala 75:19] + wire dec_io_dec_tlu_mpc_halted_only; // @[quasar.scala 75:19] + wire [31:0] dec_io_dec_dbg_rddata; // @[quasar.scala 75:19] + wire dec_io_dec_dbg_cmd_done; // @[quasar.scala 75:19] + wire dec_io_dec_dbg_cmd_fail; // @[quasar.scala 75:19] + wire dec_io_trigger_pkt_any_0_select; // @[quasar.scala 75:19] + wire dec_io_trigger_pkt_any_0_match_pkt; // @[quasar.scala 75:19] + wire dec_io_trigger_pkt_any_0_store; // @[quasar.scala 75:19] + wire dec_io_trigger_pkt_any_0_load; // @[quasar.scala 75:19] + wire [31:0] dec_io_trigger_pkt_any_0_tdata2; // @[quasar.scala 75:19] + wire dec_io_trigger_pkt_any_1_select; // @[quasar.scala 75:19] + wire dec_io_trigger_pkt_any_1_match_pkt; // @[quasar.scala 75:19] + wire dec_io_trigger_pkt_any_1_store; // @[quasar.scala 75:19] + wire dec_io_trigger_pkt_any_1_load; // @[quasar.scala 75:19] + wire [31:0] dec_io_trigger_pkt_any_1_tdata2; // @[quasar.scala 75:19] + wire dec_io_trigger_pkt_any_2_select; // @[quasar.scala 75:19] + wire dec_io_trigger_pkt_any_2_match_pkt; // @[quasar.scala 75:19] + wire dec_io_trigger_pkt_any_2_store; // @[quasar.scala 75:19] + wire dec_io_trigger_pkt_any_2_load; // @[quasar.scala 75:19] + wire [31:0] dec_io_trigger_pkt_any_2_tdata2; // @[quasar.scala 75:19] + wire dec_io_trigger_pkt_any_3_select; // @[quasar.scala 75:19] + wire dec_io_trigger_pkt_any_3_match_pkt; // @[quasar.scala 75:19] + wire dec_io_trigger_pkt_any_3_store; // @[quasar.scala 75:19] + wire dec_io_trigger_pkt_any_3_load; // @[quasar.scala 75:19] + wire [31:0] dec_io_trigger_pkt_any_3_tdata2; // @[quasar.scala 75:19] + wire dec_io_exu_i0_br_way_r; // @[quasar.scala 75:19] + wire dec_io_lsu_p_valid; // @[quasar.scala 75:19] + wire dec_io_lsu_p_bits_fast_int; // @[quasar.scala 75:19] + wire dec_io_lsu_p_bits_by; // @[quasar.scala 75:19] + wire dec_io_lsu_p_bits_half; // @[quasar.scala 75:19] + wire dec_io_lsu_p_bits_word; // @[quasar.scala 75:19] + wire dec_io_lsu_p_bits_load; // @[quasar.scala 75:19] + wire dec_io_lsu_p_bits_store; // @[quasar.scala 75:19] + wire dec_io_lsu_p_bits_unsign; // @[quasar.scala 75:19] + wire dec_io_lsu_p_bits_store_data_bypass_d; // @[quasar.scala 75:19] + wire dec_io_lsu_p_bits_load_ldst_bypass_d; // @[quasar.scala 75:19] + wire [11:0] dec_io_dec_lsu_offset_d; // @[quasar.scala 75:19] + wire dec_io_dec_tlu_i0_kill_writeb_r; // @[quasar.scala 75:19] + wire dec_io_dec_tlu_perfcnt0; // @[quasar.scala 75:19] + wire dec_io_dec_tlu_perfcnt1; // @[quasar.scala 75:19] + wire dec_io_dec_tlu_perfcnt2; // @[quasar.scala 75:19] + wire dec_io_dec_tlu_perfcnt3; // @[quasar.scala 75:19] + wire dec_io_dec_lsu_valid_raw_d; // @[quasar.scala 75:19] + wire [1:0] dec_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar.scala 75:19] + wire [31:0] dec_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar.scala 75:19] + wire [31:0] dec_io_rv_trace_pkt_rv_i_address_ip; // @[quasar.scala 75:19] + wire [1:0] dec_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar.scala 75:19] + wire [4:0] dec_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar.scala 75:19] + wire [1:0] dec_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar.scala 75:19] + wire [31:0] dec_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar.scala 75:19] + wire dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 75:19] + wire dec_io_dec_tlu_lsu_clk_override; // @[quasar.scala 75:19] + wire dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 75:19] + wire dec_io_dec_tlu_pic_clk_override; // @[quasar.scala 75:19] + wire dec_io_dec_tlu_dccm_clk_override; // @[quasar.scala 75:19] + wire dec_io_dec_tlu_icm_clk_override; // @[quasar.scala 75:19] + wire dec_io_scan_mode; // @[quasar.scala 75:19] + wire dec_io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d; // @[quasar.scala 75:19] + wire [15:0] dec_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst; // @[quasar.scala 75:19] + wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf; // @[quasar.scala 75:19] + wire [1:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type; // @[quasar.scala 75:19] + wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1; // @[quasar.scala 75:19] + wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc; // @[quasar.scala 75:19] + wire [7:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index; // @[quasar.scala 75:19] + wire [7:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[quasar.scala 75:19] + wire [4:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag; // @[quasar.scala 75:19] + wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid; // @[quasar.scala 75:19] + wire [31:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr; // @[quasar.scala 75:19] + wire [30:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc; // @[quasar.scala 75:19] + wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4; // @[quasar.scala 75:19] + wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid; // @[quasar.scala 75:19] + wire [11:0] dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset; // @[quasar.scala 75:19] + wire [1:0] dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist; // @[quasar.scala 75:19] + wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error; // @[quasar.scala 75:19] + wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[quasar.scala 75:19] + wire [30:0] dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett; // @[quasar.scala 75:19] + wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way; // @[quasar.scala 75:19] + wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret; // @[quasar.scala 75:19] + wire dec_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned; // @[quasar.scala 75:19] + wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[quasar.scala 75:19] + wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[quasar.scala 75:19] + wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 75:19] + wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb; // @[quasar.scala 75:19] + wire [70:0] dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[quasar.scala 75:19] + wire [16:0] dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics; // @[quasar.scala 75:19] + wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[quasar.scala 75:19] + wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[quasar.scala 75:19] + wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 75:19] + wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss; // @[quasar.scala 75:19] + wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[quasar.scala 75:19] + wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[quasar.scala 75:19] + wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[quasar.scala 75:19] + wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[quasar.scala 75:19] + wire dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[quasar.scala 75:19] + wire dec_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[quasar.scala 75:19] + wire [70:0] dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[quasar.scala 75:19] + wire dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[quasar.scala 75:19] + wire dec_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle; // @[quasar.scala 75:19] + wire dec_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb; // @[quasar.scala 75:19] + wire [31:0] dec_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 75:19] + wire dec_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall; // @[quasar.scala 75:19] + wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid; // @[quasar.scala 75:19] + wire [1:0] dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist; // @[quasar.scala 75:19] + wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[quasar.scala 75:19] + wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[quasar.scala 75:19] + wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[quasar.scala 75:19] + wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[quasar.scala 75:19] + wire dec_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb; // @[quasar.scala 75:19] + wire dec_io_ifu_dec_dec_bp_dec_tlu_bpred_disable; // @[quasar.scala 75:19] + wire dec_io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[quasar.scala 75:19] + wire dec_io_dec_exu_dec_alu_dec_csr_ren_d; // @[quasar.scala 75:19] + wire [11:0] dec_io_dec_exu_dec_alu_dec_i0_br_immed_d; // @[quasar.scala 75:19] + wire [30:0] dec_io_dec_exu_dec_alu_exu_i0_pc_x; // @[quasar.scala 75:19] + wire dec_io_dec_exu_dec_div_div_p_valid; // @[quasar.scala 75:19] + wire dec_io_dec_exu_dec_div_div_p_bits_unsign; // @[quasar.scala 75:19] + wire dec_io_dec_exu_dec_div_div_p_bits_rem; // @[quasar.scala 75:19] + wire dec_io_dec_exu_dec_div_dec_div_cancel; // @[quasar.scala 75:19] + wire [1:0] dec_io_dec_exu_decode_exu_dec_data_en; // @[quasar.scala 75:19] + wire [1:0] dec_io_dec_exu_decode_exu_dec_ctl_en; // @[quasar.scala 75:19] + wire dec_io_dec_exu_decode_exu_i0_ap_land; // @[quasar.scala 75:19] + wire dec_io_dec_exu_decode_exu_i0_ap_lor; // @[quasar.scala 75:19] + wire dec_io_dec_exu_decode_exu_i0_ap_lxor; // @[quasar.scala 75:19] + wire dec_io_dec_exu_decode_exu_i0_ap_sll; // @[quasar.scala 75:19] + wire dec_io_dec_exu_decode_exu_i0_ap_srl; // @[quasar.scala 75:19] + wire dec_io_dec_exu_decode_exu_i0_ap_sra; // @[quasar.scala 75:19] + wire dec_io_dec_exu_decode_exu_i0_ap_beq; // @[quasar.scala 75:19] + wire dec_io_dec_exu_decode_exu_i0_ap_bne; // @[quasar.scala 75:19] + wire dec_io_dec_exu_decode_exu_i0_ap_blt; // @[quasar.scala 75:19] + wire dec_io_dec_exu_decode_exu_i0_ap_bge; // @[quasar.scala 75:19] + wire dec_io_dec_exu_decode_exu_i0_ap_add; // @[quasar.scala 75:19] + wire dec_io_dec_exu_decode_exu_i0_ap_sub; // @[quasar.scala 75:19] + wire dec_io_dec_exu_decode_exu_i0_ap_slt; // @[quasar.scala 75:19] + wire dec_io_dec_exu_decode_exu_i0_ap_unsign; // @[quasar.scala 75:19] + wire dec_io_dec_exu_decode_exu_i0_ap_jal; // @[quasar.scala 75:19] + wire dec_io_dec_exu_decode_exu_i0_ap_predict_t; // @[quasar.scala 75:19] + wire dec_io_dec_exu_decode_exu_i0_ap_predict_nt; // @[quasar.scala 75:19] + wire dec_io_dec_exu_decode_exu_i0_ap_csr_write; // @[quasar.scala 75:19] + wire dec_io_dec_exu_decode_exu_i0_ap_csr_imm; // @[quasar.scala 75:19] + wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid; // @[quasar.scala 75:19] + wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[quasar.scala 75:19] + wire [1:0] dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist; // @[quasar.scala 75:19] + wire [11:0] dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[quasar.scala 75:19] + wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[quasar.scala 75:19] + wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[quasar.scala 75:19] + wire [30:0] dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett; // @[quasar.scala 75:19] + wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[quasar.scala 75:19] + wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret; // @[quasar.scala 75:19] + wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja; // @[quasar.scala 75:19] + wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way; // @[quasar.scala 75:19] + wire [7:0] dec_io_dec_exu_decode_exu_i0_predict_fghr_d; // @[quasar.scala 75:19] + wire [7:0] dec_io_dec_exu_decode_exu_i0_predict_index_d; // @[quasar.scala 75:19] + wire [4:0] dec_io_dec_exu_decode_exu_i0_predict_btag_d; // @[quasar.scala 75:19] + wire dec_io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[quasar.scala 75:19] + wire dec_io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[quasar.scala 75:19] + wire [31:0] dec_io_dec_exu_decode_exu_dec_i0_immed_d; // @[quasar.scala 75:19] + wire [31:0] dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_data_d; // @[quasar.scala 75:19] + wire [31:0] dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_data_d; // @[quasar.scala 75:19] + wire dec_io_dec_exu_decode_exu_dec_i0_select_pc_d; // @[quasar.scala 75:19] + wire [1:0] dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d; // @[quasar.scala 75:19] + wire [1:0] dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d; // @[quasar.scala 75:19] + wire dec_io_dec_exu_decode_exu_mul_p_valid; // @[quasar.scala 75:19] + wire dec_io_dec_exu_decode_exu_mul_p_bits_rs1_sign; // @[quasar.scala 75:19] + wire dec_io_dec_exu_decode_exu_mul_p_bits_rs2_sign; // @[quasar.scala 75:19] + wire dec_io_dec_exu_decode_exu_mul_p_bits_low; // @[quasar.scala 75:19] + wire [30:0] dec_io_dec_exu_decode_exu_pred_correct_npc_x; // @[quasar.scala 75:19] + wire dec_io_dec_exu_decode_exu_dec_extint_stall; // @[quasar.scala 75:19] + wire [31:0] dec_io_dec_exu_decode_exu_exu_i0_result_x; // @[quasar.scala 75:19] + wire [31:0] dec_io_dec_exu_decode_exu_exu_csr_rs1_x; // @[quasar.scala 75:19] + wire [29:0] dec_io_dec_exu_tlu_exu_dec_tlu_meihap; // @[quasar.scala 75:19] + wire dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 75:19] + wire [30:0] dec_io_dec_exu_tlu_exu_dec_tlu_flush_path_r; // @[quasar.scala 75:19] + wire [1:0] dec_io_dec_exu_tlu_exu_exu_i0_br_hist_r; // @[quasar.scala 75:19] + wire dec_io_dec_exu_tlu_exu_exu_i0_br_error_r; // @[quasar.scala 75:19] + wire dec_io_dec_exu_tlu_exu_exu_i0_br_start_error_r; // @[quasar.scala 75:19] + wire dec_io_dec_exu_tlu_exu_exu_i0_br_valid_r; // @[quasar.scala 75:19] + wire dec_io_dec_exu_tlu_exu_exu_i0_br_mp_r; // @[quasar.scala 75:19] + wire dec_io_dec_exu_tlu_exu_exu_i0_br_middle_r; // @[quasar.scala 75:19] + wire dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp; // @[quasar.scala 75:19] + wire dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken; // @[quasar.scala 75:19] + wire dec_io_dec_exu_tlu_exu_exu_pmu_i0_pc4; // @[quasar.scala 75:19] + wire [30:0] dec_io_dec_exu_tlu_exu_exu_npc_r; // @[quasar.scala 75:19] + wire [30:0] dec_io_dec_exu_ib_exu_dec_i0_pc_d; // @[quasar.scala 75:19] + wire dec_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[quasar.scala 75:19] + wire [31:0] dec_io_dec_exu_gpr_exu_gpr_i0_rs1_d; // @[quasar.scala 75:19] + wire [31:0] dec_io_dec_exu_gpr_exu_gpr_i0_rs2_d; // @[quasar.scala 75:19] + wire dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[quasar.scala 75:19] + wire dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[quasar.scala 75:19] + wire dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 75:19] + wire dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 75:19] + wire dec_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 75:19] + wire dec_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 75:19] + wire dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[quasar.scala 75:19] + wire dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[quasar.scala 75:19] + wire [31:0] dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any; // @[quasar.scala 75:19] + wire dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m; // @[quasar.scala 75:19] + wire [1:0] dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m; // @[quasar.scala 75:19] + wire dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r; // @[quasar.scala 75:19] + wire [1:0] dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[quasar.scala 75:19] + wire dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid; // @[quasar.scala 75:19] + wire dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error; // @[quasar.scala 75:19] + wire [1:0] dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag; // @[quasar.scala 75:19] + wire [31:0] dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data; // @[quasar.scala 75:19] + wire dec_io_lsu_tlu_lsu_pmu_load_external_m; // @[quasar.scala 75:19] + wire dec_io_lsu_tlu_lsu_pmu_store_external_m; // @[quasar.scala 75:19] + wire dec_io_dec_dbg_dbg_ib_dbg_cmd_valid; // @[quasar.scala 75:19] + wire dec_io_dec_dbg_dbg_ib_dbg_cmd_write; // @[quasar.scala 75:19] + wire [1:0] dec_io_dec_dbg_dbg_ib_dbg_cmd_type; // @[quasar.scala 75:19] + wire [31:0] dec_io_dec_dbg_dbg_ib_dbg_cmd_addr; // @[quasar.scala 75:19] + wire [31:0] dec_io_dec_dbg_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 75:19] + wire dec_io_dec_dma_dctl_dma_dma_dccm_stall_any; // @[quasar.scala 75:19] + wire dec_io_dec_dma_tlu_dma_dma_pmu_dccm_read; // @[quasar.scala 75:19] + wire dec_io_dec_dma_tlu_dma_dma_pmu_dccm_write; // @[quasar.scala 75:19] + wire dec_io_dec_dma_tlu_dma_dma_pmu_any_read; // @[quasar.scala 75:19] + wire dec_io_dec_dma_tlu_dma_dma_pmu_any_write; // @[quasar.scala 75:19] + wire [2:0] dec_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty; // @[quasar.scala 75:19] + wire dec_io_dec_dma_tlu_dma_dma_dccm_stall_any; // @[quasar.scala 75:19] + wire dec_io_dec_dma_tlu_dma_dma_iccm_stall_any; // @[quasar.scala 75:19] + wire [7:0] dec_io_dec_pic_pic_claimid; // @[quasar.scala 75:19] + wire [3:0] dec_io_dec_pic_pic_pl; // @[quasar.scala 75:19] + wire dec_io_dec_pic_mhwakeup; // @[quasar.scala 75:19] + wire [3:0] dec_io_dec_pic_dec_tlu_meicurpl; // @[quasar.scala 75:19] + wire [3:0] dec_io_dec_pic_dec_tlu_meipt; // @[quasar.scala 75:19] + wire dec_io_dec_pic_mexintpend; // @[quasar.scala 75:19] + wire dbg_clock; // @[quasar.scala 76:19] + wire dbg_reset; // @[quasar.scala 76:19] + wire [1:0] dbg_io_dbg_cmd_size; // @[quasar.scala 76:19] + wire dbg_io_dbg_core_rst_l; // @[quasar.scala 76:19] + wire [31:0] dbg_io_core_dbg_rddata; // @[quasar.scala 76:19] + wire dbg_io_core_dbg_cmd_done; // @[quasar.scala 76:19] + wire dbg_io_core_dbg_cmd_fail; // @[quasar.scala 76:19] + wire dbg_io_dbg_halt_req; // @[quasar.scala 76:19] + wire dbg_io_dbg_resume_req; // @[quasar.scala 76:19] + wire dbg_io_dec_tlu_debug_mode; // @[quasar.scala 76:19] + wire dbg_io_dec_tlu_dbg_halted; // @[quasar.scala 76:19] + wire dbg_io_dec_tlu_mpc_halted_only; // @[quasar.scala 76:19] + wire dbg_io_dec_tlu_resume_ack; // @[quasar.scala 76:19] + wire dbg_io_dmi_reg_en; // @[quasar.scala 76:19] + wire [6:0] dbg_io_dmi_reg_addr; // @[quasar.scala 76:19] + wire dbg_io_dmi_reg_wr_en; // @[quasar.scala 76:19] + wire [31:0] dbg_io_dmi_reg_wdata; // @[quasar.scala 76:19] + wire [31:0] dbg_io_dmi_reg_rdata; // @[quasar.scala 76:19] + wire dbg_io_sb_axi_aw_ready; // @[quasar.scala 76:19] + wire dbg_io_sb_axi_aw_valid; // @[quasar.scala 76:19] + wire [31:0] dbg_io_sb_axi_aw_bits_addr; // @[quasar.scala 76:19] + wire [2:0] dbg_io_sb_axi_aw_bits_size; // @[quasar.scala 76:19] + wire dbg_io_sb_axi_w_ready; // @[quasar.scala 76:19] + wire dbg_io_sb_axi_w_valid; // @[quasar.scala 76:19] + wire [63:0] dbg_io_sb_axi_w_bits_data; // @[quasar.scala 76:19] + wire [7:0] dbg_io_sb_axi_w_bits_strb; // @[quasar.scala 76:19] + wire dbg_io_sb_axi_b_ready; // @[quasar.scala 76:19] + wire dbg_io_sb_axi_b_valid; // @[quasar.scala 76:19] + wire [1:0] dbg_io_sb_axi_b_bits_resp; // @[quasar.scala 76:19] + wire dbg_io_sb_axi_ar_ready; // @[quasar.scala 76:19] + wire dbg_io_sb_axi_ar_valid; // @[quasar.scala 76:19] + wire [31:0] dbg_io_sb_axi_ar_bits_addr; // @[quasar.scala 76:19] + wire [2:0] dbg_io_sb_axi_ar_bits_size; // @[quasar.scala 76:19] + wire dbg_io_sb_axi_r_ready; // @[quasar.scala 76:19] + wire dbg_io_sb_axi_r_valid; // @[quasar.scala 76:19] + wire [63:0] dbg_io_sb_axi_r_bits_data; // @[quasar.scala 76:19] + wire [1:0] dbg_io_sb_axi_r_bits_resp; // @[quasar.scala 76:19] + wire dbg_io_dbg_dec_dbg_ib_dbg_cmd_valid; // @[quasar.scala 76:19] + wire dbg_io_dbg_dec_dbg_ib_dbg_cmd_write; // @[quasar.scala 76:19] + wire [1:0] dbg_io_dbg_dec_dbg_ib_dbg_cmd_type; // @[quasar.scala 76:19] + wire [31:0] dbg_io_dbg_dec_dbg_ib_dbg_cmd_addr; // @[quasar.scala 76:19] + wire [31:0] dbg_io_dbg_dec_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 76:19] + wire dbg_io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[quasar.scala 76:19] + wire dbg_io_dbg_dma_dbg_ib_dbg_cmd_write; // @[quasar.scala 76:19] + wire [1:0] dbg_io_dbg_dma_dbg_ib_dbg_cmd_type; // @[quasar.scala 76:19] + wire [31:0] dbg_io_dbg_dma_dbg_ib_dbg_cmd_addr; // @[quasar.scala 76:19] + wire [31:0] dbg_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 76:19] + wire dbg_io_dbg_dma_io_dbg_dma_bubble; // @[quasar.scala 76:19] + wire dbg_io_dbg_dma_io_dma_dbg_ready; // @[quasar.scala 76:19] + wire dbg_io_dbg_bus_clk_en; // @[quasar.scala 76:19] + wire dbg_io_dbg_rst_l; // @[quasar.scala 76:19] + wire dbg_io_clk_override; // @[quasar.scala 76:19] + wire dbg_io_scan_mode; // @[quasar.scala 76:19] + wire exu_clock; // @[quasar.scala 77:19] + wire exu_reset; // @[quasar.scala 77:19] + wire exu_io_scan_mode; // @[quasar.scala 77:19] + wire exu_io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[quasar.scala 77:19] + wire exu_io_dec_exu_dec_alu_dec_csr_ren_d; // @[quasar.scala 77:19] + wire [11:0] exu_io_dec_exu_dec_alu_dec_i0_br_immed_d; // @[quasar.scala 77:19] + wire [30:0] exu_io_dec_exu_dec_alu_exu_i0_pc_x; // @[quasar.scala 77:19] + wire exu_io_dec_exu_dec_div_div_p_valid; // @[quasar.scala 77:19] + wire exu_io_dec_exu_dec_div_div_p_bits_unsign; // @[quasar.scala 77:19] + wire exu_io_dec_exu_dec_div_div_p_bits_rem; // @[quasar.scala 77:19] + wire exu_io_dec_exu_dec_div_dec_div_cancel; // @[quasar.scala 77:19] + wire [1:0] exu_io_dec_exu_decode_exu_dec_data_en; // @[quasar.scala 77:19] + wire [1:0] exu_io_dec_exu_decode_exu_dec_ctl_en; // @[quasar.scala 77:19] + wire exu_io_dec_exu_decode_exu_i0_ap_land; // @[quasar.scala 77:19] + wire exu_io_dec_exu_decode_exu_i0_ap_lor; // @[quasar.scala 77:19] + wire exu_io_dec_exu_decode_exu_i0_ap_lxor; // @[quasar.scala 77:19] + wire exu_io_dec_exu_decode_exu_i0_ap_sll; // @[quasar.scala 77:19] + wire exu_io_dec_exu_decode_exu_i0_ap_srl; // @[quasar.scala 77:19] + wire exu_io_dec_exu_decode_exu_i0_ap_sra; // @[quasar.scala 77:19] + wire exu_io_dec_exu_decode_exu_i0_ap_beq; // @[quasar.scala 77:19] + wire exu_io_dec_exu_decode_exu_i0_ap_bne; // @[quasar.scala 77:19] + wire exu_io_dec_exu_decode_exu_i0_ap_blt; // @[quasar.scala 77:19] + wire exu_io_dec_exu_decode_exu_i0_ap_bge; // @[quasar.scala 77:19] + wire exu_io_dec_exu_decode_exu_i0_ap_add; // @[quasar.scala 77:19] + wire exu_io_dec_exu_decode_exu_i0_ap_sub; // @[quasar.scala 77:19] + wire exu_io_dec_exu_decode_exu_i0_ap_slt; // @[quasar.scala 77:19] + wire exu_io_dec_exu_decode_exu_i0_ap_unsign; // @[quasar.scala 77:19] + wire exu_io_dec_exu_decode_exu_i0_ap_jal; // @[quasar.scala 77:19] + wire exu_io_dec_exu_decode_exu_i0_ap_predict_t; // @[quasar.scala 77:19] + wire exu_io_dec_exu_decode_exu_i0_ap_predict_nt; // @[quasar.scala 77:19] + wire exu_io_dec_exu_decode_exu_i0_ap_csr_write; // @[quasar.scala 77:19] + wire exu_io_dec_exu_decode_exu_i0_ap_csr_imm; // @[quasar.scala 77:19] + wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid; // @[quasar.scala 77:19] + wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[quasar.scala 77:19] + wire [1:0] exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist; // @[quasar.scala 77:19] + wire [11:0] exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[quasar.scala 77:19] + wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[quasar.scala 77:19] + wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[quasar.scala 77:19] + wire [30:0] exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett; // @[quasar.scala 77:19] + wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[quasar.scala 77:19] + wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret; // @[quasar.scala 77:19] + wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja; // @[quasar.scala 77:19] + wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way; // @[quasar.scala 77:19] + wire [7:0] exu_io_dec_exu_decode_exu_i0_predict_fghr_d; // @[quasar.scala 77:19] + wire [7:0] exu_io_dec_exu_decode_exu_i0_predict_index_d; // @[quasar.scala 77:19] + wire [4:0] exu_io_dec_exu_decode_exu_i0_predict_btag_d; // @[quasar.scala 77:19] + wire exu_io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[quasar.scala 77:19] + wire exu_io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[quasar.scala 77:19] + wire [31:0] exu_io_dec_exu_decode_exu_dec_i0_immed_d; // @[quasar.scala 77:19] + wire [31:0] exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_data_d; // @[quasar.scala 77:19] + wire [31:0] exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_data_d; // @[quasar.scala 77:19] + wire exu_io_dec_exu_decode_exu_dec_i0_select_pc_d; // @[quasar.scala 77:19] + wire [1:0] exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d; // @[quasar.scala 77:19] + wire [1:0] exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d; // @[quasar.scala 77:19] + wire exu_io_dec_exu_decode_exu_mul_p_valid; // @[quasar.scala 77:19] + wire exu_io_dec_exu_decode_exu_mul_p_bits_rs1_sign; // @[quasar.scala 77:19] + wire exu_io_dec_exu_decode_exu_mul_p_bits_rs2_sign; // @[quasar.scala 77:19] + wire exu_io_dec_exu_decode_exu_mul_p_bits_low; // @[quasar.scala 77:19] + wire [30:0] exu_io_dec_exu_decode_exu_pred_correct_npc_x; // @[quasar.scala 77:19] + wire exu_io_dec_exu_decode_exu_dec_extint_stall; // @[quasar.scala 77:19] + wire [31:0] exu_io_dec_exu_decode_exu_exu_i0_result_x; // @[quasar.scala 77:19] + wire [31:0] exu_io_dec_exu_decode_exu_exu_csr_rs1_x; // @[quasar.scala 77:19] + wire [29:0] exu_io_dec_exu_tlu_exu_dec_tlu_meihap; // @[quasar.scala 77:19] + wire exu_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 77:19] + wire [30:0] exu_io_dec_exu_tlu_exu_dec_tlu_flush_path_r; // @[quasar.scala 77:19] + wire [1:0] exu_io_dec_exu_tlu_exu_exu_i0_br_hist_r; // @[quasar.scala 77:19] + wire exu_io_dec_exu_tlu_exu_exu_i0_br_error_r; // @[quasar.scala 77:19] + wire exu_io_dec_exu_tlu_exu_exu_i0_br_start_error_r; // @[quasar.scala 77:19] + wire [7:0] exu_io_dec_exu_tlu_exu_exu_i0_br_index_r; // @[quasar.scala 77:19] + wire exu_io_dec_exu_tlu_exu_exu_i0_br_valid_r; // @[quasar.scala 77:19] + wire exu_io_dec_exu_tlu_exu_exu_i0_br_mp_r; // @[quasar.scala 77:19] + wire exu_io_dec_exu_tlu_exu_exu_i0_br_middle_r; // @[quasar.scala 77:19] + wire exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp; // @[quasar.scala 77:19] + wire exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken; // @[quasar.scala 77:19] + wire exu_io_dec_exu_tlu_exu_exu_pmu_i0_pc4; // @[quasar.scala 77:19] + wire [30:0] exu_io_dec_exu_tlu_exu_exu_npc_r; // @[quasar.scala 77:19] + wire [30:0] exu_io_dec_exu_ib_exu_dec_i0_pc_d; // @[quasar.scala 77:19] + wire exu_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[quasar.scala 77:19] + wire [31:0] exu_io_dec_exu_gpr_exu_gpr_i0_rs1_d; // @[quasar.scala 77:19] + wire [31:0] exu_io_dec_exu_gpr_exu_gpr_i0_rs2_d; // @[quasar.scala 77:19] + wire [7:0] exu_io_exu_bp_exu_i0_br_fghr_r; // @[quasar.scala 77:19] + wire exu_io_exu_bp_exu_i0_br_way_r; // @[quasar.scala 77:19] + wire exu_io_exu_bp_exu_mp_pkt_bits_misp; // @[quasar.scala 77:19] + wire exu_io_exu_bp_exu_mp_pkt_bits_ataken; // @[quasar.scala 77:19] + wire exu_io_exu_bp_exu_mp_pkt_bits_boffset; // @[quasar.scala 77:19] + wire exu_io_exu_bp_exu_mp_pkt_bits_pc4; // @[quasar.scala 77:19] + wire [1:0] exu_io_exu_bp_exu_mp_pkt_bits_hist; // @[quasar.scala 77:19] + wire [11:0] exu_io_exu_bp_exu_mp_pkt_bits_toffset; // @[quasar.scala 77:19] + wire exu_io_exu_bp_exu_mp_pkt_bits_pcall; // @[quasar.scala 77:19] + wire exu_io_exu_bp_exu_mp_pkt_bits_pret; // @[quasar.scala 77:19] + wire exu_io_exu_bp_exu_mp_pkt_bits_pja; // @[quasar.scala 77:19] + wire exu_io_exu_bp_exu_mp_pkt_bits_way; // @[quasar.scala 77:19] + wire [7:0] exu_io_exu_bp_exu_mp_eghr; // @[quasar.scala 77:19] + wire [7:0] exu_io_exu_bp_exu_mp_fghr; // @[quasar.scala 77:19] + wire [7:0] exu_io_exu_bp_exu_mp_index; // @[quasar.scala 77:19] + wire [4:0] exu_io_exu_bp_exu_mp_btag; // @[quasar.scala 77:19] + wire exu_io_exu_flush_final; // @[quasar.scala 77:19] + wire [31:0] exu_io_exu_div_result; // @[quasar.scala 77:19] + wire exu_io_exu_div_wren; // @[quasar.scala 77:19] + wire [31:0] exu_io_dbg_cmd_wrdata; // @[quasar.scala 77:19] + wire [31:0] exu_io_lsu_exu_exu_lsu_rs1_d; // @[quasar.scala 77:19] + wire [31:0] exu_io_lsu_exu_exu_lsu_rs2_d; // @[quasar.scala 77:19] + wire [30:0] exu_io_exu_flush_path_final; // @[quasar.scala 77:19] + wire lsu_clock; // @[quasar.scala 78:19] + wire lsu_reset; // @[quasar.scala 78:19] + wire lsu_io_clk_override; // @[quasar.scala 78:19] + wire lsu_io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[quasar.scala 78:19] + wire [31:0] lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[quasar.scala 78:19] + wire [2:0] lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[quasar.scala 78:19] + wire lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[quasar.scala 78:19] + wire [63:0] lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[quasar.scala 78:19] + wire [31:0] lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_addr; // @[quasar.scala 78:19] + wire [63:0] lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata; // @[quasar.scala 78:19] + wire lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid; // @[quasar.scala 78:19] + wire lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[quasar.scala 78:19] + wire [2:0] lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[quasar.scala 78:19] + wire [63:0] lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata; // @[quasar.scala 78:19] + wire lsu_io_lsu_dma_dccm_ready; // @[quasar.scala 78:19] + wire [2:0] lsu_io_lsu_dma_dma_mem_tag; // @[quasar.scala 78:19] + wire lsu_io_lsu_pic_picm_wren; // @[quasar.scala 78:19] + wire lsu_io_lsu_pic_picm_rden; // @[quasar.scala 78:19] + wire lsu_io_lsu_pic_picm_mken; // @[quasar.scala 78:19] + wire [31:0] lsu_io_lsu_pic_picm_rdaddr; // @[quasar.scala 78:19] + wire [31:0] lsu_io_lsu_pic_picm_wraddr; // @[quasar.scala 78:19] + wire [31:0] lsu_io_lsu_pic_picm_wr_data; // @[quasar.scala 78:19] + wire [31:0] lsu_io_lsu_pic_picm_rd_data; // @[quasar.scala 78:19] + wire [31:0] lsu_io_lsu_exu_exu_lsu_rs1_d; // @[quasar.scala 78:19] + wire [31:0] lsu_io_lsu_exu_exu_lsu_rs2_d; // @[quasar.scala 78:19] + wire lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[quasar.scala 78:19] + wire lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[quasar.scala 78:19] + wire lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 78:19] + wire lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 78:19] + wire lsu_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 78:19] + wire lsu_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 78:19] + wire lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[quasar.scala 78:19] + wire lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[quasar.scala 78:19] + wire [31:0] lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any; // @[quasar.scala 78:19] + wire lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m; // @[quasar.scala 78:19] + wire [1:0] lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m; // @[quasar.scala 78:19] + wire lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r; // @[quasar.scala 78:19] + wire [1:0] lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[quasar.scala 78:19] + wire lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid; // @[quasar.scala 78:19] + wire lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error; // @[quasar.scala 78:19] + wire [1:0] lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag; // @[quasar.scala 78:19] + wire [31:0] lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data; // @[quasar.scala 78:19] + wire lsu_io_dccm_wren; // @[quasar.scala 78:19] + wire lsu_io_dccm_rden; // @[quasar.scala 78:19] + wire [15:0] lsu_io_dccm_wr_addr_lo; // @[quasar.scala 78:19] + wire [15:0] lsu_io_dccm_wr_addr_hi; // @[quasar.scala 78:19] + wire [15:0] lsu_io_dccm_rd_addr_lo; // @[quasar.scala 78:19] + wire [15:0] lsu_io_dccm_rd_addr_hi; // @[quasar.scala 78:19] + wire [38:0] lsu_io_dccm_wr_data_lo; // @[quasar.scala 78:19] + wire [38:0] lsu_io_dccm_wr_data_hi; // @[quasar.scala 78:19] + wire [38:0] lsu_io_dccm_rd_data_lo; // @[quasar.scala 78:19] + wire [38:0] lsu_io_dccm_rd_data_hi; // @[quasar.scala 78:19] + wire lsu_io_lsu_tlu_lsu_pmu_load_external_m; // @[quasar.scala 78:19] + wire lsu_io_lsu_tlu_lsu_pmu_store_external_m; // @[quasar.scala 78:19] + wire lsu_io_axi_aw_ready; // @[quasar.scala 78:19] + wire lsu_io_axi_aw_valid; // @[quasar.scala 78:19] + wire [2:0] lsu_io_axi_aw_bits_id; // @[quasar.scala 78:19] + wire [31:0] lsu_io_axi_aw_bits_addr; // @[quasar.scala 78:19] + wire [2:0] lsu_io_axi_aw_bits_size; // @[quasar.scala 78:19] + wire lsu_io_axi_w_ready; // @[quasar.scala 78:19] + wire lsu_io_axi_w_valid; // @[quasar.scala 78:19] + wire [63:0] lsu_io_axi_w_bits_data; // @[quasar.scala 78:19] + wire [7:0] lsu_io_axi_w_bits_strb; // @[quasar.scala 78:19] + wire lsu_io_axi_b_valid; // @[quasar.scala 78:19] + wire [2:0] lsu_io_axi_b_bits_id; // @[quasar.scala 78:19] + wire lsu_io_axi_ar_ready; // @[quasar.scala 78:19] + wire lsu_io_axi_ar_valid; // @[quasar.scala 78:19] + wire [2:0] lsu_io_axi_ar_bits_id; // @[quasar.scala 78:19] + wire [31:0] lsu_io_axi_ar_bits_addr; // @[quasar.scala 78:19] + wire [2:0] lsu_io_axi_ar_bits_size; // @[quasar.scala 78:19] + wire lsu_io_axi_r_valid; // @[quasar.scala 78:19] + wire [2:0] lsu_io_axi_r_bits_id; // @[quasar.scala 78:19] + wire [63:0] lsu_io_axi_r_bits_data; // @[quasar.scala 78:19] + wire [1:0] lsu_io_axi_r_bits_resp; // @[quasar.scala 78:19] + wire lsu_io_dec_tlu_flush_lower_r; // @[quasar.scala 78:19] + wire lsu_io_dec_tlu_i0_kill_writeb_r; // @[quasar.scala 78:19] + wire lsu_io_dec_tlu_force_halt; // @[quasar.scala 78:19] + wire lsu_io_dec_tlu_core_ecc_disable; // @[quasar.scala 78:19] + wire [11:0] lsu_io_dec_lsu_offset_d; // @[quasar.scala 78:19] + wire lsu_io_lsu_p_valid; // @[quasar.scala 78:19] + wire lsu_io_lsu_p_bits_fast_int; // @[quasar.scala 78:19] + wire lsu_io_lsu_p_bits_by; // @[quasar.scala 78:19] + wire lsu_io_lsu_p_bits_half; // @[quasar.scala 78:19] + wire lsu_io_lsu_p_bits_word; // @[quasar.scala 78:19] + wire lsu_io_lsu_p_bits_load; // @[quasar.scala 78:19] + wire lsu_io_lsu_p_bits_store; // @[quasar.scala 78:19] + wire lsu_io_lsu_p_bits_unsign; // @[quasar.scala 78:19] + wire lsu_io_lsu_p_bits_store_data_bypass_d; // @[quasar.scala 78:19] + wire lsu_io_lsu_p_bits_load_ldst_bypass_d; // @[quasar.scala 78:19] + wire lsu_io_trigger_pkt_any_0_select; // @[quasar.scala 78:19] + wire lsu_io_trigger_pkt_any_0_match_pkt; // @[quasar.scala 78:19] + wire lsu_io_trigger_pkt_any_0_store; // @[quasar.scala 78:19] + wire lsu_io_trigger_pkt_any_0_load; // @[quasar.scala 78:19] + wire [31:0] lsu_io_trigger_pkt_any_0_tdata2; // @[quasar.scala 78:19] + wire lsu_io_trigger_pkt_any_1_select; // @[quasar.scala 78:19] + wire lsu_io_trigger_pkt_any_1_match_pkt; // @[quasar.scala 78:19] + wire lsu_io_trigger_pkt_any_1_store; // @[quasar.scala 78:19] + wire lsu_io_trigger_pkt_any_1_load; // @[quasar.scala 78:19] + wire [31:0] lsu_io_trigger_pkt_any_1_tdata2; // @[quasar.scala 78:19] + wire lsu_io_trigger_pkt_any_2_select; // @[quasar.scala 78:19] + wire lsu_io_trigger_pkt_any_2_match_pkt; // @[quasar.scala 78:19] + wire lsu_io_trigger_pkt_any_2_store; // @[quasar.scala 78:19] + wire lsu_io_trigger_pkt_any_2_load; // @[quasar.scala 78:19] + wire [31:0] lsu_io_trigger_pkt_any_2_tdata2; // @[quasar.scala 78:19] + wire lsu_io_trigger_pkt_any_3_select; // @[quasar.scala 78:19] + wire lsu_io_trigger_pkt_any_3_match_pkt; // @[quasar.scala 78:19] + wire lsu_io_trigger_pkt_any_3_store; // @[quasar.scala 78:19] + wire lsu_io_trigger_pkt_any_3_load; // @[quasar.scala 78:19] + wire [31:0] lsu_io_trigger_pkt_any_3_tdata2; // @[quasar.scala 78:19] + wire lsu_io_dec_lsu_valid_raw_d; // @[quasar.scala 78:19] + wire [31:0] lsu_io_dec_tlu_mrac_ff; // @[quasar.scala 78:19] + wire [31:0] lsu_io_lsu_result_m; // @[quasar.scala 78:19] + wire [31:0] lsu_io_lsu_result_corr_r; // @[quasar.scala 78:19] + wire lsu_io_lsu_load_stall_any; // @[quasar.scala 78:19] + wire lsu_io_lsu_store_stall_any; // @[quasar.scala 78:19] + wire lsu_io_lsu_fastint_stall_any; // @[quasar.scala 78:19] + wire lsu_io_lsu_idle_any; // @[quasar.scala 78:19] + wire [30:0] lsu_io_lsu_fir_addr; // @[quasar.scala 78:19] + wire [1:0] lsu_io_lsu_fir_error; // @[quasar.scala 78:19] + wire lsu_io_lsu_single_ecc_error_incr; // @[quasar.scala 78:19] + wire lsu_io_lsu_error_pkt_r_valid; // @[quasar.scala 78:19] + wire lsu_io_lsu_error_pkt_r_bits_single_ecc_error; // @[quasar.scala 78:19] + wire lsu_io_lsu_error_pkt_r_bits_inst_type; // @[quasar.scala 78:19] + wire lsu_io_lsu_error_pkt_r_bits_exc_type; // @[quasar.scala 78:19] + wire [3:0] lsu_io_lsu_error_pkt_r_bits_mscause; // @[quasar.scala 78:19] + wire [31:0] lsu_io_lsu_error_pkt_r_bits_addr; // @[quasar.scala 78:19] + wire lsu_io_lsu_pmu_misaligned_m; // @[quasar.scala 78:19] + wire [3:0] lsu_io_lsu_trigger_match_m; // @[quasar.scala 78:19] + wire lsu_io_lsu_bus_clk_en; // @[quasar.scala 78:19] + wire lsu_io_scan_mode; // @[quasar.scala 78:19] + wire lsu_io_free_clk; // @[quasar.scala 78:19] + wire pic_ctrl_inst_clock; // @[quasar.scala 79:29] + wire pic_ctrl_inst_reset; // @[quasar.scala 79:29] + wire pic_ctrl_inst_io_scan_mode; // @[quasar.scala 79:29] + wire pic_ctrl_inst_io_free_clk; // @[quasar.scala 79:29] + wire pic_ctrl_inst_io_active_clk; // @[quasar.scala 79:29] + wire pic_ctrl_inst_io_clk_override; // @[quasar.scala 79:29] + wire [31:0] pic_ctrl_inst_io_extintsrc_req; // @[quasar.scala 79:29] + wire pic_ctrl_inst_io_lsu_pic_picm_wren; // @[quasar.scala 79:29] + wire pic_ctrl_inst_io_lsu_pic_picm_rden; // @[quasar.scala 79:29] + wire pic_ctrl_inst_io_lsu_pic_picm_mken; // @[quasar.scala 79:29] + wire [31:0] pic_ctrl_inst_io_lsu_pic_picm_rdaddr; // @[quasar.scala 79:29] + wire [31:0] pic_ctrl_inst_io_lsu_pic_picm_wraddr; // @[quasar.scala 79:29] + wire [31:0] pic_ctrl_inst_io_lsu_pic_picm_wr_data; // @[quasar.scala 79:29] + wire [31:0] pic_ctrl_inst_io_lsu_pic_picm_rd_data; // @[quasar.scala 79:29] + wire [7:0] pic_ctrl_inst_io_dec_pic_pic_claimid; // @[quasar.scala 79:29] + wire [3:0] pic_ctrl_inst_io_dec_pic_pic_pl; // @[quasar.scala 79:29] + wire pic_ctrl_inst_io_dec_pic_mhwakeup; // @[quasar.scala 79:29] + wire [3:0] pic_ctrl_inst_io_dec_pic_dec_tlu_meicurpl; // @[quasar.scala 79:29] + wire [3:0] pic_ctrl_inst_io_dec_pic_dec_tlu_meipt; // @[quasar.scala 79:29] + wire pic_ctrl_inst_io_dec_pic_mexintpend; // @[quasar.scala 79:29] + wire dma_ctrl_clock; // @[quasar.scala 80:24] + wire dma_ctrl_reset; // @[quasar.scala 80:24] + wire dma_ctrl_io_free_clk; // @[quasar.scala 80:24] + wire dma_ctrl_io_dma_bus_clk_en; // @[quasar.scala 80:24] + wire dma_ctrl_io_clk_override; // @[quasar.scala 80:24] + wire dma_ctrl_io_scan_mode; // @[quasar.scala 80:24] + wire [1:0] dma_ctrl_io_dbg_cmd_size; // @[quasar.scala 80:24] + wire [31:0] dma_ctrl_io_dma_dbg_rddata; // @[quasar.scala 80:24] + wire dma_ctrl_io_dma_dbg_cmd_done; // @[quasar.scala 80:24] + wire dma_ctrl_io_dma_dbg_cmd_fail; // @[quasar.scala 80:24] + wire dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[quasar.scala 80:24] + wire dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_write; // @[quasar.scala 80:24] + wire [1:0] dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_type; // @[quasar.scala 80:24] + wire [31:0] dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_addr; // @[quasar.scala 80:24] + wire [31:0] dma_ctrl_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 80:24] + wire dma_ctrl_io_dbg_dma_io_dbg_dma_bubble; // @[quasar.scala 80:24] + wire dma_ctrl_io_dbg_dma_io_dma_dbg_ready; // @[quasar.scala 80:24] + wire dma_ctrl_io_dec_dma_dctl_dma_dma_dccm_stall_any; // @[quasar.scala 80:24] + wire dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_read; // @[quasar.scala 80:24] + wire dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_write; // @[quasar.scala 80:24] + wire dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_read; // @[quasar.scala 80:24] + wire dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_write; // @[quasar.scala 80:24] + wire [2:0] dma_ctrl_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty; // @[quasar.scala 80:24] + wire dma_ctrl_io_dec_dma_tlu_dma_dma_dccm_stall_any; // @[quasar.scala 80:24] + wire dma_ctrl_io_dec_dma_tlu_dma_dma_iccm_stall_any; // @[quasar.scala 80:24] + wire dma_ctrl_io_iccm_dma_rvalid; // @[quasar.scala 80:24] + wire dma_ctrl_io_iccm_dma_ecc_error; // @[quasar.scala 80:24] + wire [2:0] dma_ctrl_io_iccm_dma_rtag; // @[quasar.scala 80:24] + wire [63:0] dma_ctrl_io_iccm_dma_rdata; // @[quasar.scala 80:24] + wire dma_ctrl_io_iccm_ready; // @[quasar.scala 80:24] + wire dma_ctrl_io_dma_axi_aw_ready; // @[quasar.scala 80:24] + wire dma_ctrl_io_dma_axi_aw_valid; // @[quasar.scala 80:24] + wire [31:0] dma_ctrl_io_dma_axi_aw_bits_addr; // @[quasar.scala 80:24] + wire [2:0] dma_ctrl_io_dma_axi_aw_bits_size; // @[quasar.scala 80:24] + wire dma_ctrl_io_dma_axi_w_ready; // @[quasar.scala 80:24] + wire dma_ctrl_io_dma_axi_w_valid; // @[quasar.scala 80:24] + wire [63:0] dma_ctrl_io_dma_axi_w_bits_data; // @[quasar.scala 80:24] + wire [7:0] dma_ctrl_io_dma_axi_w_bits_strb; // @[quasar.scala 80:24] + wire dma_ctrl_io_dma_axi_b_valid; // @[quasar.scala 80:24] + wire dma_ctrl_io_dma_axi_ar_ready; // @[quasar.scala 80:24] + wire dma_ctrl_io_dma_axi_ar_valid; // @[quasar.scala 80:24] + wire [31:0] dma_ctrl_io_dma_axi_ar_bits_addr; // @[quasar.scala 80:24] + wire [2:0] dma_ctrl_io_dma_axi_ar_bits_size; // @[quasar.scala 80:24] + wire dma_ctrl_io_dma_axi_r_valid; // @[quasar.scala 80:24] + wire [63:0] dma_ctrl_io_dma_axi_r_bits_data; // @[quasar.scala 80:24] + wire [1:0] dma_ctrl_io_dma_axi_r_bits_resp; // @[quasar.scala 80:24] + wire dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[quasar.scala 80:24] + wire [31:0] dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[quasar.scala 80:24] + wire [2:0] dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[quasar.scala 80:24] + wire dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[quasar.scala 80:24] + wire [63:0] dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[quasar.scala 80:24] + wire [31:0] dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_addr; // @[quasar.scala 80:24] + wire [63:0] dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata; // @[quasar.scala 80:24] + wire dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid; // @[quasar.scala 80:24] + wire dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[quasar.scala 80:24] + wire [2:0] dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[quasar.scala 80:24] + wire [63:0] dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata; // @[quasar.scala 80:24] + wire dma_ctrl_io_lsu_dma_dccm_ready; // @[quasar.scala 80:24] + wire [2:0] dma_ctrl_io_lsu_dma_dma_mem_tag; // @[quasar.scala 80:24] + wire dma_ctrl_io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[quasar.scala 80:24] + wire dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[quasar.scala 80:24] + wire [31:0] dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_addr; // @[quasar.scala 80:24] + wire [2:0] dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_sz; // @[quasar.scala 80:24] + wire dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_write; // @[quasar.scala 80:24] + wire [63:0] dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_wdata; // @[quasar.scala 80:24] + wire [2:0] dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_tag; // @[quasar.scala 80:24] wire rvclkhdr_io_l1clk; // @[lib.scala 343:22] wire rvclkhdr_io_clk; // @[lib.scala 343:22] wire rvclkhdr_io_en; // @[lib.scala 343:22] @@ -81381,87 +83709,135 @@ module quasar( wire rvclkhdr_1_io_clk; // @[lib.scala 343:22] wire rvclkhdr_1_io_en; // @[lib.scala 343:22] wire rvclkhdr_1_io_scan_mode; // @[lib.scala 343:22] - wire axi4_to_ahb_clock; // @[quasar.scala 242:32] - wire axi4_to_ahb_reset; // @[quasar.scala 242:32] - wire axi4_to_ahb_io_scan_mode; // @[quasar.scala 242:32] - wire axi4_to_ahb_io_bus_clk_en; // @[quasar.scala 242:32] - wire axi4_to_ahb_io_clk_override; // @[quasar.scala 242:32] - wire axi4_to_ahb_io_axi_aw_ready; // @[quasar.scala 242:32] - wire axi4_to_ahb_io_axi_aw_valid; // @[quasar.scala 242:32] - wire axi4_to_ahb_io_axi_aw_bits_id; // @[quasar.scala 242:32] - wire axi4_to_ahb_io_axi_w_ready; // @[quasar.scala 242:32] - wire axi4_to_ahb_io_axi_w_valid; // @[quasar.scala 242:32] - wire [63:0] axi4_to_ahb_io_axi_w_bits_data; // @[quasar.scala 242:32] - wire axi4_to_ahb_io_axi_b_ready; // @[quasar.scala 242:32] - wire axi4_to_ahb_io_axi_b_valid; // @[quasar.scala 242:32] - wire [1:0] axi4_to_ahb_io_axi_b_bits_resp; // @[quasar.scala 242:32] - wire axi4_to_ahb_io_axi_b_bits_id; // @[quasar.scala 242:32] - wire axi4_to_ahb_io_axi_ar_ready; // @[quasar.scala 242:32] - wire axi4_to_ahb_io_axi_ar_valid; // @[quasar.scala 242:32] - wire axi4_to_ahb_io_axi_ar_bits_id; // @[quasar.scala 242:32] - wire axi4_to_ahb_io_axi_r_valid; // @[quasar.scala 242:32] - wire axi4_to_ahb_io_axi_r_bits_id; // @[quasar.scala 242:32] - wire [63:0] axi4_to_ahb_io_axi_r_bits_data; // @[quasar.scala 242:32] - wire [1:0] axi4_to_ahb_io_axi_r_bits_resp; // @[quasar.scala 242:32] - wire axi4_to_ahb_1_clock; // @[quasar.scala 243:33] - wire axi4_to_ahb_1_reset; // @[quasar.scala 243:33] - wire axi4_to_ahb_1_io_scan_mode; // @[quasar.scala 243:33] - wire axi4_to_ahb_1_io_bus_clk_en; // @[quasar.scala 243:33] - wire axi4_to_ahb_1_io_clk_override; // @[quasar.scala 243:33] - wire axi4_to_ahb_1_io_axi_aw_ready; // @[quasar.scala 243:33] - wire axi4_to_ahb_1_io_axi_aw_valid; // @[quasar.scala 243:33] - wire axi4_to_ahb_1_io_axi_aw_bits_id; // @[quasar.scala 243:33] - wire axi4_to_ahb_1_io_axi_w_ready; // @[quasar.scala 243:33] - wire axi4_to_ahb_1_io_axi_w_valid; // @[quasar.scala 243:33] - wire [63:0] axi4_to_ahb_1_io_axi_w_bits_data; // @[quasar.scala 243:33] - wire axi4_to_ahb_1_io_axi_b_ready; // @[quasar.scala 243:33] - wire axi4_to_ahb_1_io_axi_b_valid; // @[quasar.scala 243:33] - wire [1:0] axi4_to_ahb_1_io_axi_b_bits_resp; // @[quasar.scala 243:33] - wire axi4_to_ahb_1_io_axi_b_bits_id; // @[quasar.scala 243:33] - wire axi4_to_ahb_1_io_axi_ar_ready; // @[quasar.scala 243:33] - wire axi4_to_ahb_1_io_axi_ar_valid; // @[quasar.scala 243:33] - wire axi4_to_ahb_1_io_axi_ar_bits_id; // @[quasar.scala 243:33] - wire axi4_to_ahb_1_io_axi_r_valid; // @[quasar.scala 243:33] - wire axi4_to_ahb_1_io_axi_r_bits_id; // @[quasar.scala 243:33] - wire [63:0] axi4_to_ahb_1_io_axi_r_bits_data; // @[quasar.scala 243:33] - wire [1:0] axi4_to_ahb_1_io_axi_r_bits_resp; // @[quasar.scala 243:33] - wire axi4_to_ahb_2_clock; // @[quasar.scala 244:33] - wire axi4_to_ahb_2_reset; // @[quasar.scala 244:33] - wire axi4_to_ahb_2_io_scan_mode; // @[quasar.scala 244:33] - wire axi4_to_ahb_2_io_bus_clk_en; // @[quasar.scala 244:33] - wire axi4_to_ahb_2_io_clk_override; // @[quasar.scala 244:33] - wire axi4_to_ahb_2_io_axi_aw_ready; // @[quasar.scala 244:33] - wire axi4_to_ahb_2_io_axi_aw_valid; // @[quasar.scala 244:33] - wire axi4_to_ahb_2_io_axi_aw_bits_id; // @[quasar.scala 244:33] - wire axi4_to_ahb_2_io_axi_w_ready; // @[quasar.scala 244:33] - wire axi4_to_ahb_2_io_axi_w_valid; // @[quasar.scala 244:33] - wire [63:0] axi4_to_ahb_2_io_axi_w_bits_data; // @[quasar.scala 244:33] - wire axi4_to_ahb_2_io_axi_b_ready; // @[quasar.scala 244:33] - wire axi4_to_ahb_2_io_axi_b_valid; // @[quasar.scala 244:33] - wire [1:0] axi4_to_ahb_2_io_axi_b_bits_resp; // @[quasar.scala 244:33] - wire axi4_to_ahb_2_io_axi_b_bits_id; // @[quasar.scala 244:33] - wire axi4_to_ahb_2_io_axi_ar_ready; // @[quasar.scala 244:33] - wire axi4_to_ahb_2_io_axi_ar_valid; // @[quasar.scala 244:33] - wire axi4_to_ahb_2_io_axi_ar_bits_id; // @[quasar.scala 244:33] - wire axi4_to_ahb_2_io_axi_r_valid; // @[quasar.scala 244:33] - wire axi4_to_ahb_2_io_axi_r_bits_id; // @[quasar.scala 244:33] - wire [63:0] axi4_to_ahb_2_io_axi_r_bits_data; // @[quasar.scala 244:33] - wire [1:0] axi4_to_ahb_2_io_axi_r_bits_resp; // @[quasar.scala 244:33] - wire ahb_to_axi4_clock; // @[quasar.scala 245:33] - wire ahb_to_axi4_reset; // @[quasar.scala 245:33] - wire ahb_to_axi4_io_scan_mode; // @[quasar.scala 245:33] - wire ahb_to_axi4_io_bus_clk_en; // @[quasar.scala 245:33] - wire ahb_to_axi4_io_axi_aw_valid; // @[quasar.scala 245:33] - wire ahb_to_axi4_io_axi_ar_ready; // @[quasar.scala 245:33] - wire ahb_to_axi4_io_axi_ar_valid; // @[quasar.scala 245:33] - wire ahb_to_axi4_io_axi_r_valid; // @[quasar.scala 245:33] - wire [1:0] ahb_to_axi4_io_axi_r_bits_resp; // @[quasar.scala 245:33] - wire ahb_to_axi4_io_ahb_sig_in_hresp; // @[quasar.scala 245:33] - wire _T_1 = dbg_io_dbg_core_rst_l; // @[quasar.scala 80:67] - wire _T_2 = _T_1 | io_scan_mode; // @[quasar.scala 80:70] - wire _T_5 = ~dec_io_dec_pause_state_cg; // @[quasar.scala 81:23] - wire _T_6 = _T_5 | dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 81:50] - ifu ifu ( // @[quasar.scala 72:19] + wire axi4_to_ahb_clock; // @[quasar.scala 245:32] + wire axi4_to_ahb_reset; // @[quasar.scala 245:32] + wire axi4_to_ahb_io_scan_mode; // @[quasar.scala 245:32] + wire axi4_to_ahb_io_bus_clk_en; // @[quasar.scala 245:32] + wire axi4_to_ahb_io_clk_override; // @[quasar.scala 245:32] + wire axi4_to_ahb_io_axi_aw_ready; // @[quasar.scala 245:32] + wire axi4_to_ahb_io_axi_aw_valid; // @[quasar.scala 245:32] + wire [31:0] axi4_to_ahb_io_axi_aw_bits_addr; // @[quasar.scala 245:32] + wire [2:0] axi4_to_ahb_io_axi_aw_bits_size; // @[quasar.scala 245:32] + wire axi4_to_ahb_io_axi_w_ready; // @[quasar.scala 245:32] + wire axi4_to_ahb_io_axi_w_valid; // @[quasar.scala 245:32] + wire [63:0] axi4_to_ahb_io_axi_w_bits_data; // @[quasar.scala 245:32] + wire [7:0] axi4_to_ahb_io_axi_w_bits_strb; // @[quasar.scala 245:32] + wire axi4_to_ahb_io_axi_b_valid; // @[quasar.scala 245:32] + wire [1:0] axi4_to_ahb_io_axi_b_bits_resp; // @[quasar.scala 245:32] + wire axi4_to_ahb_io_axi_ar_ready; // @[quasar.scala 245:32] + wire axi4_to_ahb_io_axi_ar_valid; // @[quasar.scala 245:32] + wire [31:0] axi4_to_ahb_io_axi_ar_bits_addr; // @[quasar.scala 245:32] + wire [2:0] axi4_to_ahb_io_axi_ar_bits_size; // @[quasar.scala 245:32] + wire axi4_to_ahb_io_axi_r_valid; // @[quasar.scala 245:32] + wire [63:0] axi4_to_ahb_io_axi_r_bits_data; // @[quasar.scala 245:32] + wire [1:0] axi4_to_ahb_io_axi_r_bits_resp; // @[quasar.scala 245:32] + wire [63:0] axi4_to_ahb_io_ahb_in_hrdata; // @[quasar.scala 245:32] + wire axi4_to_ahb_io_ahb_in_hready; // @[quasar.scala 245:32] + wire axi4_to_ahb_io_ahb_in_hresp; // @[quasar.scala 245:32] + wire [31:0] axi4_to_ahb_io_ahb_out_haddr; // @[quasar.scala 245:32] + wire [2:0] axi4_to_ahb_io_ahb_out_hsize; // @[quasar.scala 245:32] + wire [1:0] axi4_to_ahb_io_ahb_out_htrans; // @[quasar.scala 245:32] + wire axi4_to_ahb_io_ahb_out_hwrite; // @[quasar.scala 245:32] + wire [63:0] axi4_to_ahb_io_ahb_out_hwdata; // @[quasar.scala 245:32] + wire axi4_to_ahb_1_clock; // @[quasar.scala 246:33] + wire axi4_to_ahb_1_reset; // @[quasar.scala 246:33] + wire axi4_to_ahb_1_io_scan_mode; // @[quasar.scala 246:33] + wire axi4_to_ahb_1_io_bus_clk_en; // @[quasar.scala 246:33] + wire axi4_to_ahb_1_io_clk_override; // @[quasar.scala 246:33] + wire axi4_to_ahb_1_io_axi_aw_ready; // @[quasar.scala 246:33] + wire axi4_to_ahb_1_io_axi_aw_valid; // @[quasar.scala 246:33] + wire [2:0] axi4_to_ahb_1_io_axi_aw_bits_id; // @[quasar.scala 246:33] + wire [31:0] axi4_to_ahb_1_io_axi_aw_bits_addr; // @[quasar.scala 246:33] + wire [2:0] axi4_to_ahb_1_io_axi_aw_bits_size; // @[quasar.scala 246:33] + wire axi4_to_ahb_1_io_axi_w_ready; // @[quasar.scala 246:33] + wire axi4_to_ahb_1_io_axi_w_valid; // @[quasar.scala 246:33] + wire [63:0] axi4_to_ahb_1_io_axi_w_bits_data; // @[quasar.scala 246:33] + wire [7:0] axi4_to_ahb_1_io_axi_w_bits_strb; // @[quasar.scala 246:33] + wire axi4_to_ahb_1_io_axi_b_valid; // @[quasar.scala 246:33] + wire [2:0] axi4_to_ahb_1_io_axi_b_bits_id; // @[quasar.scala 246:33] + wire axi4_to_ahb_1_io_axi_ar_ready; // @[quasar.scala 246:33] + wire axi4_to_ahb_1_io_axi_ar_valid; // @[quasar.scala 246:33] + wire [2:0] axi4_to_ahb_1_io_axi_ar_bits_id; // @[quasar.scala 246:33] + wire [31:0] axi4_to_ahb_1_io_axi_ar_bits_addr; // @[quasar.scala 246:33] + wire [2:0] axi4_to_ahb_1_io_axi_ar_bits_size; // @[quasar.scala 246:33] + wire axi4_to_ahb_1_io_axi_r_valid; // @[quasar.scala 246:33] + wire [2:0] axi4_to_ahb_1_io_axi_r_bits_id; // @[quasar.scala 246:33] + wire [63:0] axi4_to_ahb_1_io_axi_r_bits_data; // @[quasar.scala 246:33] + wire [1:0] axi4_to_ahb_1_io_axi_r_bits_resp; // @[quasar.scala 246:33] + wire [63:0] axi4_to_ahb_1_io_ahb_in_hrdata; // @[quasar.scala 246:33] + wire axi4_to_ahb_1_io_ahb_in_hready; // @[quasar.scala 246:33] + wire axi4_to_ahb_1_io_ahb_in_hresp; // @[quasar.scala 246:33] + wire [31:0] axi4_to_ahb_1_io_ahb_out_haddr; // @[quasar.scala 246:33] + wire [2:0] axi4_to_ahb_1_io_ahb_out_hsize; // @[quasar.scala 246:33] + wire [1:0] axi4_to_ahb_1_io_ahb_out_htrans; // @[quasar.scala 246:33] + wire axi4_to_ahb_1_io_ahb_out_hwrite; // @[quasar.scala 246:33] + wire [63:0] axi4_to_ahb_1_io_ahb_out_hwdata; // @[quasar.scala 246:33] + wire axi4_to_ahb_2_clock; // @[quasar.scala 247:33] + wire axi4_to_ahb_2_reset; // @[quasar.scala 247:33] + wire axi4_to_ahb_2_io_scan_mode; // @[quasar.scala 247:33] + wire axi4_to_ahb_2_io_bus_clk_en; // @[quasar.scala 247:33] + wire axi4_to_ahb_2_io_clk_override; // @[quasar.scala 247:33] + wire axi4_to_ahb_2_io_axi_aw_ready; // @[quasar.scala 247:33] + wire axi4_to_ahb_2_io_axi_aw_valid; // @[quasar.scala 247:33] + wire [2:0] axi4_to_ahb_2_io_axi_aw_bits_id; // @[quasar.scala 247:33] + wire [31:0] axi4_to_ahb_2_io_axi_aw_bits_addr; // @[quasar.scala 247:33] + wire [2:0] axi4_to_ahb_2_io_axi_aw_bits_size; // @[quasar.scala 247:33] + wire axi4_to_ahb_2_io_axi_w_ready; // @[quasar.scala 247:33] + wire axi4_to_ahb_2_io_axi_w_valid; // @[quasar.scala 247:33] + wire [63:0] axi4_to_ahb_2_io_axi_w_bits_data; // @[quasar.scala 247:33] + wire [7:0] axi4_to_ahb_2_io_axi_w_bits_strb; // @[quasar.scala 247:33] + wire axi4_to_ahb_2_io_axi_b_valid; // @[quasar.scala 247:33] + wire [2:0] axi4_to_ahb_2_io_axi_b_bits_id; // @[quasar.scala 247:33] + wire axi4_to_ahb_2_io_axi_ar_ready; // @[quasar.scala 247:33] + wire axi4_to_ahb_2_io_axi_ar_valid; // @[quasar.scala 247:33] + wire [2:0] axi4_to_ahb_2_io_axi_ar_bits_id; // @[quasar.scala 247:33] + wire [31:0] axi4_to_ahb_2_io_axi_ar_bits_addr; // @[quasar.scala 247:33] + wire [2:0] axi4_to_ahb_2_io_axi_ar_bits_size; // @[quasar.scala 247:33] + wire axi4_to_ahb_2_io_axi_r_valid; // @[quasar.scala 247:33] + wire [2:0] axi4_to_ahb_2_io_axi_r_bits_id; // @[quasar.scala 247:33] + wire [63:0] axi4_to_ahb_2_io_axi_r_bits_data; // @[quasar.scala 247:33] + wire [1:0] axi4_to_ahb_2_io_axi_r_bits_resp; // @[quasar.scala 247:33] + wire [63:0] axi4_to_ahb_2_io_ahb_in_hrdata; // @[quasar.scala 247:33] + wire axi4_to_ahb_2_io_ahb_in_hready; // @[quasar.scala 247:33] + wire axi4_to_ahb_2_io_ahb_in_hresp; // @[quasar.scala 247:33] + wire [31:0] axi4_to_ahb_2_io_ahb_out_haddr; // @[quasar.scala 247:33] + wire [2:0] axi4_to_ahb_2_io_ahb_out_hsize; // @[quasar.scala 247:33] + wire [1:0] axi4_to_ahb_2_io_ahb_out_htrans; // @[quasar.scala 247:33] + wire axi4_to_ahb_2_io_ahb_out_hwrite; // @[quasar.scala 247:33] + wire [63:0] axi4_to_ahb_2_io_ahb_out_hwdata; // @[quasar.scala 247:33] + wire ahb_to_axi4_clock; // @[quasar.scala 248:33] + wire ahb_to_axi4_reset; // @[quasar.scala 248:33] + wire ahb_to_axi4_io_scan_mode; // @[quasar.scala 248:33] + wire ahb_to_axi4_io_bus_clk_en; // @[quasar.scala 248:33] + wire ahb_to_axi4_io_axi_aw_ready; // @[quasar.scala 248:33] + wire ahb_to_axi4_io_axi_aw_valid; // @[quasar.scala 248:33] + wire [31:0] ahb_to_axi4_io_axi_aw_bits_addr; // @[quasar.scala 248:33] + wire [2:0] ahb_to_axi4_io_axi_aw_bits_size; // @[quasar.scala 248:33] + wire ahb_to_axi4_io_axi_w_valid; // @[quasar.scala 248:33] + wire [63:0] ahb_to_axi4_io_axi_w_bits_data; // @[quasar.scala 248:33] + wire [7:0] ahb_to_axi4_io_axi_w_bits_strb; // @[quasar.scala 248:33] + wire ahb_to_axi4_io_axi_ar_ready; // @[quasar.scala 248:33] + wire ahb_to_axi4_io_axi_ar_valid; // @[quasar.scala 248:33] + wire [31:0] ahb_to_axi4_io_axi_ar_bits_addr; // @[quasar.scala 248:33] + wire [2:0] ahb_to_axi4_io_axi_ar_bits_size; // @[quasar.scala 248:33] + wire ahb_to_axi4_io_axi_r_valid; // @[quasar.scala 248:33] + wire [63:0] ahb_to_axi4_io_axi_r_bits_data; // @[quasar.scala 248:33] + wire [1:0] ahb_to_axi4_io_axi_r_bits_resp; // @[quasar.scala 248:33] + wire [63:0] ahb_to_axi4_io_ahb_sig_in_hrdata; // @[quasar.scala 248:33] + wire ahb_to_axi4_io_ahb_sig_in_hready; // @[quasar.scala 248:33] + wire ahb_to_axi4_io_ahb_sig_in_hresp; // @[quasar.scala 248:33] + wire [31:0] ahb_to_axi4_io_ahb_sig_out_haddr; // @[quasar.scala 248:33] + wire [2:0] ahb_to_axi4_io_ahb_sig_out_hsize; // @[quasar.scala 248:33] + wire [1:0] ahb_to_axi4_io_ahb_sig_out_htrans; // @[quasar.scala 248:33] + wire ahb_to_axi4_io_ahb_sig_out_hwrite; // @[quasar.scala 248:33] + wire [63:0] ahb_to_axi4_io_ahb_sig_out_hwdata; // @[quasar.scala 248:33] + wire ahb_to_axi4_io_ahb_hsel; // @[quasar.scala 248:33] + wire ahb_to_axi4_io_ahb_hreadyin; // @[quasar.scala 248:33] + wire _T_1 = dbg_io_dbg_core_rst_l; // @[quasar.scala 82:67] + wire _T_2 = _T_1 | io_scan_mode; // @[quasar.scala 82:70] + wire _T_5 = ~dec_io_dec_pause_state_cg; // @[quasar.scala 83:23] + wire _T_6 = _T_5 | dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 83:50] + ifu ifu ( // @[quasar.scala 74:19] .clock(ifu_clock), .reset(ifu_reset), .io_exu_flush_final(ifu_io_exu_flush_final), @@ -81568,6 +83944,7 @@ module quasar( .io_ifu_ar_ready(ifu_io_ifu_ar_ready), .io_ifu_ar_valid(ifu_io_ifu_ar_valid), .io_ifu_ar_bits_id(ifu_io_ifu_ar_bits_id), + .io_ifu_ar_bits_addr(ifu_io_ifu_ar_bits_addr), .io_ifu_r_valid(ifu_io_ifu_r_valid), .io_ifu_r_bits_id(ifu_io_ifu_r_bits_id), .io_ifu_r_bits_data(ifu_io_ifu_r_bits_data), @@ -81589,7 +83966,7 @@ module quasar( .io_dec_tlu_flush_lower_wb(ifu_io_dec_tlu_flush_lower_wb), .io_scan_mode(ifu_io_scan_mode) ); - dec dec ( // @[quasar.scala 73:19] + dec dec ( // @[quasar.scala 75:19] .clock(dec_clock), .reset(dec_reset), .io_free_clk(dec_io_free_clk), @@ -81862,7 +84239,7 @@ module quasar( .io_dec_pic_dec_tlu_meipt(dec_io_dec_pic_dec_tlu_meipt), .io_dec_pic_mexintpend(dec_io_dec_pic_mexintpend) ); - dbg dbg ( // @[quasar.scala 74:19] + dbg dbg ( // @[quasar.scala 76:19] .clock(dbg_clock), .reset(dbg_reset), .io_dbg_cmd_size(dbg_io_dbg_cmd_size), @@ -81880,16 +84257,22 @@ module quasar( .io_dmi_reg_addr(dbg_io_dmi_reg_addr), .io_dmi_reg_wr_en(dbg_io_dmi_reg_wr_en), .io_dmi_reg_wdata(dbg_io_dmi_reg_wdata), + .io_dmi_reg_rdata(dbg_io_dmi_reg_rdata), .io_sb_axi_aw_ready(dbg_io_sb_axi_aw_ready), .io_sb_axi_aw_valid(dbg_io_sb_axi_aw_valid), + .io_sb_axi_aw_bits_addr(dbg_io_sb_axi_aw_bits_addr), + .io_sb_axi_aw_bits_size(dbg_io_sb_axi_aw_bits_size), .io_sb_axi_w_ready(dbg_io_sb_axi_w_ready), .io_sb_axi_w_valid(dbg_io_sb_axi_w_valid), .io_sb_axi_w_bits_data(dbg_io_sb_axi_w_bits_data), + .io_sb_axi_w_bits_strb(dbg_io_sb_axi_w_bits_strb), .io_sb_axi_b_ready(dbg_io_sb_axi_b_ready), .io_sb_axi_b_valid(dbg_io_sb_axi_b_valid), .io_sb_axi_b_bits_resp(dbg_io_sb_axi_b_bits_resp), .io_sb_axi_ar_ready(dbg_io_sb_axi_ar_ready), .io_sb_axi_ar_valid(dbg_io_sb_axi_ar_valid), + .io_sb_axi_ar_bits_addr(dbg_io_sb_axi_ar_bits_addr), + .io_sb_axi_ar_bits_size(dbg_io_sb_axi_ar_bits_size), .io_sb_axi_r_ready(dbg_io_sb_axi_r_ready), .io_sb_axi_r_valid(dbg_io_sb_axi_r_valid), .io_sb_axi_r_bits_data(dbg_io_sb_axi_r_bits_data), @@ -81911,7 +84294,7 @@ module quasar( .io_clk_override(dbg_io_clk_override), .io_scan_mode(dbg_io_scan_mode) ); - exu exu ( // @[quasar.scala 75:19] + exu exu ( // @[quasar.scala 77:19] .clock(exu_clock), .reset(exu_reset), .io_scan_mode(exu_io_scan_mode), @@ -82016,7 +84399,7 @@ module quasar( .io_lsu_exu_exu_lsu_rs2_d(exu_io_lsu_exu_exu_lsu_rs2_d), .io_exu_flush_path_final(exu_io_exu_flush_path_final) ); - lsu lsu ( // @[quasar.scala 76:19] + lsu lsu ( // @[quasar.scala 78:19] .clock(lsu_clock), .reset(lsu_reset), .io_clk_override(lsu_io_clk_override), @@ -82074,14 +84457,19 @@ module quasar( .io_axi_aw_ready(lsu_io_axi_aw_ready), .io_axi_aw_valid(lsu_io_axi_aw_valid), .io_axi_aw_bits_id(lsu_io_axi_aw_bits_id), + .io_axi_aw_bits_addr(lsu_io_axi_aw_bits_addr), + .io_axi_aw_bits_size(lsu_io_axi_aw_bits_size), .io_axi_w_ready(lsu_io_axi_w_ready), .io_axi_w_valid(lsu_io_axi_w_valid), .io_axi_w_bits_data(lsu_io_axi_w_bits_data), + .io_axi_w_bits_strb(lsu_io_axi_w_bits_strb), .io_axi_b_valid(lsu_io_axi_b_valid), .io_axi_b_bits_id(lsu_io_axi_b_bits_id), .io_axi_ar_ready(lsu_io_axi_ar_ready), .io_axi_ar_valid(lsu_io_axi_ar_valid), .io_axi_ar_bits_id(lsu_io_axi_ar_bits_id), + .io_axi_ar_bits_addr(lsu_io_axi_ar_bits_addr), + .io_axi_ar_bits_size(lsu_io_axi_ar_bits_size), .io_axi_r_valid(lsu_io_axi_r_valid), .io_axi_r_bits_id(lsu_io_axi_r_bits_id), .io_axi_r_bits_data(lsu_io_axi_r_bits_data), @@ -82144,7 +84532,7 @@ module quasar( .io_scan_mode(lsu_io_scan_mode), .io_free_clk(lsu_io_free_clk) ); - pic_ctrl pic_ctrl_inst ( // @[quasar.scala 77:29] + pic_ctrl pic_ctrl_inst ( // @[quasar.scala 79:29] .clock(pic_ctrl_inst_clock), .reset(pic_ctrl_inst_reset), .io_scan_mode(pic_ctrl_inst_io_scan_mode), @@ -82166,7 +84554,7 @@ module quasar( .io_dec_pic_dec_tlu_meipt(pic_ctrl_inst_io_dec_pic_dec_tlu_meipt), .io_dec_pic_mexintpend(pic_ctrl_inst_io_dec_pic_mexintpend) ); - dma_ctrl dma_ctrl ( // @[quasar.scala 78:24] + dma_ctrl dma_ctrl ( // @[quasar.scala 80:24] .clock(dma_ctrl_clock), .reset(dma_ctrl_reset), .io_free_clk(dma_ctrl_io_free_clk), @@ -82197,10 +84585,21 @@ module quasar( .io_iccm_dma_rtag(dma_ctrl_io_iccm_dma_rtag), .io_iccm_dma_rdata(dma_ctrl_io_iccm_dma_rdata), .io_iccm_ready(dma_ctrl_io_iccm_ready), + .io_dma_axi_aw_ready(dma_ctrl_io_dma_axi_aw_ready), + .io_dma_axi_aw_valid(dma_ctrl_io_dma_axi_aw_valid), + .io_dma_axi_aw_bits_addr(dma_ctrl_io_dma_axi_aw_bits_addr), + .io_dma_axi_aw_bits_size(dma_ctrl_io_dma_axi_aw_bits_size), + .io_dma_axi_w_ready(dma_ctrl_io_dma_axi_w_ready), + .io_dma_axi_w_valid(dma_ctrl_io_dma_axi_w_valid), + .io_dma_axi_w_bits_data(dma_ctrl_io_dma_axi_w_bits_data), + .io_dma_axi_w_bits_strb(dma_ctrl_io_dma_axi_w_bits_strb), .io_dma_axi_b_valid(dma_ctrl_io_dma_axi_b_valid), .io_dma_axi_ar_ready(dma_ctrl_io_dma_axi_ar_ready), .io_dma_axi_ar_valid(dma_ctrl_io_dma_axi_ar_valid), + .io_dma_axi_ar_bits_addr(dma_ctrl_io_dma_axi_ar_bits_addr), + .io_dma_axi_ar_bits_size(dma_ctrl_io_dma_axi_ar_bits_size), .io_dma_axi_r_valid(dma_ctrl_io_dma_axi_r_valid), + .io_dma_axi_r_bits_data(dma_ctrl_io_dma_axi_r_bits_data), .io_dma_axi_r_bits_resp(dma_ctrl_io_dma_axi_r_bits_resp), .io_lsu_dma_dma_lsc_ctl_dma_dccm_req(dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_dccm_req), .io_lsu_dma_dma_lsc_ctl_dma_mem_addr(dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_addr), @@ -82235,7 +84634,7 @@ module quasar( .io_en(rvclkhdr_1_io_en), .io_scan_mode(rvclkhdr_1_io_scan_mode) ); - axi4_to_ahb axi4_to_ahb ( // @[quasar.scala 242:32] + axi4_to_ahb axi4_to_ahb ( // @[quasar.scala 245:32] .clock(axi4_to_ahb_clock), .reset(axi4_to_ahb_reset), .io_scan_mode(axi4_to_ahb_io_scan_mode), @@ -82243,23 +84642,31 @@ module quasar( .io_clk_override(axi4_to_ahb_io_clk_override), .io_axi_aw_ready(axi4_to_ahb_io_axi_aw_ready), .io_axi_aw_valid(axi4_to_ahb_io_axi_aw_valid), - .io_axi_aw_bits_id(axi4_to_ahb_io_axi_aw_bits_id), + .io_axi_aw_bits_addr(axi4_to_ahb_io_axi_aw_bits_addr), + .io_axi_aw_bits_size(axi4_to_ahb_io_axi_aw_bits_size), .io_axi_w_ready(axi4_to_ahb_io_axi_w_ready), .io_axi_w_valid(axi4_to_ahb_io_axi_w_valid), .io_axi_w_bits_data(axi4_to_ahb_io_axi_w_bits_data), - .io_axi_b_ready(axi4_to_ahb_io_axi_b_ready), + .io_axi_w_bits_strb(axi4_to_ahb_io_axi_w_bits_strb), .io_axi_b_valid(axi4_to_ahb_io_axi_b_valid), .io_axi_b_bits_resp(axi4_to_ahb_io_axi_b_bits_resp), - .io_axi_b_bits_id(axi4_to_ahb_io_axi_b_bits_id), .io_axi_ar_ready(axi4_to_ahb_io_axi_ar_ready), .io_axi_ar_valid(axi4_to_ahb_io_axi_ar_valid), - .io_axi_ar_bits_id(axi4_to_ahb_io_axi_ar_bits_id), + .io_axi_ar_bits_addr(axi4_to_ahb_io_axi_ar_bits_addr), + .io_axi_ar_bits_size(axi4_to_ahb_io_axi_ar_bits_size), .io_axi_r_valid(axi4_to_ahb_io_axi_r_valid), - .io_axi_r_bits_id(axi4_to_ahb_io_axi_r_bits_id), .io_axi_r_bits_data(axi4_to_ahb_io_axi_r_bits_data), - .io_axi_r_bits_resp(axi4_to_ahb_io_axi_r_bits_resp) + .io_axi_r_bits_resp(axi4_to_ahb_io_axi_r_bits_resp), + .io_ahb_in_hrdata(axi4_to_ahb_io_ahb_in_hrdata), + .io_ahb_in_hready(axi4_to_ahb_io_ahb_in_hready), + .io_ahb_in_hresp(axi4_to_ahb_io_ahb_in_hresp), + .io_ahb_out_haddr(axi4_to_ahb_io_ahb_out_haddr), + .io_ahb_out_hsize(axi4_to_ahb_io_ahb_out_hsize), + .io_ahb_out_htrans(axi4_to_ahb_io_ahb_out_htrans), + .io_ahb_out_hwrite(axi4_to_ahb_io_ahb_out_hwrite), + .io_ahb_out_hwdata(axi4_to_ahb_io_ahb_out_hwdata) ); - axi4_to_ahb axi4_to_ahb_1 ( // @[quasar.scala 243:33] + axi4_to_ahb_1 axi4_to_ahb_1 ( // @[quasar.scala 246:33] .clock(axi4_to_ahb_1_clock), .reset(axi4_to_ahb_1_reset), .io_scan_mode(axi4_to_ahb_1_io_scan_mode), @@ -82268,22 +84675,33 @@ module quasar( .io_axi_aw_ready(axi4_to_ahb_1_io_axi_aw_ready), .io_axi_aw_valid(axi4_to_ahb_1_io_axi_aw_valid), .io_axi_aw_bits_id(axi4_to_ahb_1_io_axi_aw_bits_id), + .io_axi_aw_bits_addr(axi4_to_ahb_1_io_axi_aw_bits_addr), + .io_axi_aw_bits_size(axi4_to_ahb_1_io_axi_aw_bits_size), .io_axi_w_ready(axi4_to_ahb_1_io_axi_w_ready), .io_axi_w_valid(axi4_to_ahb_1_io_axi_w_valid), .io_axi_w_bits_data(axi4_to_ahb_1_io_axi_w_bits_data), - .io_axi_b_ready(axi4_to_ahb_1_io_axi_b_ready), + .io_axi_w_bits_strb(axi4_to_ahb_1_io_axi_w_bits_strb), .io_axi_b_valid(axi4_to_ahb_1_io_axi_b_valid), - .io_axi_b_bits_resp(axi4_to_ahb_1_io_axi_b_bits_resp), .io_axi_b_bits_id(axi4_to_ahb_1_io_axi_b_bits_id), .io_axi_ar_ready(axi4_to_ahb_1_io_axi_ar_ready), .io_axi_ar_valid(axi4_to_ahb_1_io_axi_ar_valid), .io_axi_ar_bits_id(axi4_to_ahb_1_io_axi_ar_bits_id), + .io_axi_ar_bits_addr(axi4_to_ahb_1_io_axi_ar_bits_addr), + .io_axi_ar_bits_size(axi4_to_ahb_1_io_axi_ar_bits_size), .io_axi_r_valid(axi4_to_ahb_1_io_axi_r_valid), .io_axi_r_bits_id(axi4_to_ahb_1_io_axi_r_bits_id), .io_axi_r_bits_data(axi4_to_ahb_1_io_axi_r_bits_data), - .io_axi_r_bits_resp(axi4_to_ahb_1_io_axi_r_bits_resp) + .io_axi_r_bits_resp(axi4_to_ahb_1_io_axi_r_bits_resp), + .io_ahb_in_hrdata(axi4_to_ahb_1_io_ahb_in_hrdata), + .io_ahb_in_hready(axi4_to_ahb_1_io_ahb_in_hready), + .io_ahb_in_hresp(axi4_to_ahb_1_io_ahb_in_hresp), + .io_ahb_out_haddr(axi4_to_ahb_1_io_ahb_out_haddr), + .io_ahb_out_hsize(axi4_to_ahb_1_io_ahb_out_hsize), + .io_ahb_out_htrans(axi4_to_ahb_1_io_ahb_out_htrans), + .io_ahb_out_hwrite(axi4_to_ahb_1_io_ahb_out_hwrite), + .io_ahb_out_hwdata(axi4_to_ahb_1_io_ahb_out_hwdata) ); - axi4_to_ahb axi4_to_ahb_2 ( // @[quasar.scala 244:33] + axi4_to_ahb_1 axi4_to_ahb_2 ( // @[quasar.scala 247:33] .clock(axi4_to_ahb_2_clock), .reset(axi4_to_ahb_2_reset), .io_scan_mode(axi4_to_ahb_2_io_scan_mode), @@ -82292,467 +84710,523 @@ module quasar( .io_axi_aw_ready(axi4_to_ahb_2_io_axi_aw_ready), .io_axi_aw_valid(axi4_to_ahb_2_io_axi_aw_valid), .io_axi_aw_bits_id(axi4_to_ahb_2_io_axi_aw_bits_id), + .io_axi_aw_bits_addr(axi4_to_ahb_2_io_axi_aw_bits_addr), + .io_axi_aw_bits_size(axi4_to_ahb_2_io_axi_aw_bits_size), .io_axi_w_ready(axi4_to_ahb_2_io_axi_w_ready), .io_axi_w_valid(axi4_to_ahb_2_io_axi_w_valid), .io_axi_w_bits_data(axi4_to_ahb_2_io_axi_w_bits_data), - .io_axi_b_ready(axi4_to_ahb_2_io_axi_b_ready), + .io_axi_w_bits_strb(axi4_to_ahb_2_io_axi_w_bits_strb), .io_axi_b_valid(axi4_to_ahb_2_io_axi_b_valid), - .io_axi_b_bits_resp(axi4_to_ahb_2_io_axi_b_bits_resp), .io_axi_b_bits_id(axi4_to_ahb_2_io_axi_b_bits_id), .io_axi_ar_ready(axi4_to_ahb_2_io_axi_ar_ready), .io_axi_ar_valid(axi4_to_ahb_2_io_axi_ar_valid), .io_axi_ar_bits_id(axi4_to_ahb_2_io_axi_ar_bits_id), + .io_axi_ar_bits_addr(axi4_to_ahb_2_io_axi_ar_bits_addr), + .io_axi_ar_bits_size(axi4_to_ahb_2_io_axi_ar_bits_size), .io_axi_r_valid(axi4_to_ahb_2_io_axi_r_valid), .io_axi_r_bits_id(axi4_to_ahb_2_io_axi_r_bits_id), .io_axi_r_bits_data(axi4_to_ahb_2_io_axi_r_bits_data), - .io_axi_r_bits_resp(axi4_to_ahb_2_io_axi_r_bits_resp) + .io_axi_r_bits_resp(axi4_to_ahb_2_io_axi_r_bits_resp), + .io_ahb_in_hrdata(axi4_to_ahb_2_io_ahb_in_hrdata), + .io_ahb_in_hready(axi4_to_ahb_2_io_ahb_in_hready), + .io_ahb_in_hresp(axi4_to_ahb_2_io_ahb_in_hresp), + .io_ahb_out_haddr(axi4_to_ahb_2_io_ahb_out_haddr), + .io_ahb_out_hsize(axi4_to_ahb_2_io_ahb_out_hsize), + .io_ahb_out_htrans(axi4_to_ahb_2_io_ahb_out_htrans), + .io_ahb_out_hwrite(axi4_to_ahb_2_io_ahb_out_hwrite), + .io_ahb_out_hwdata(axi4_to_ahb_2_io_ahb_out_hwdata) ); - ahb_to_axi4 ahb_to_axi4 ( // @[quasar.scala 245:33] + ahb_to_axi4 ahb_to_axi4 ( // @[quasar.scala 248:33] .clock(ahb_to_axi4_clock), .reset(ahb_to_axi4_reset), .io_scan_mode(ahb_to_axi4_io_scan_mode), .io_bus_clk_en(ahb_to_axi4_io_bus_clk_en), + .io_axi_aw_ready(ahb_to_axi4_io_axi_aw_ready), .io_axi_aw_valid(ahb_to_axi4_io_axi_aw_valid), + .io_axi_aw_bits_addr(ahb_to_axi4_io_axi_aw_bits_addr), + .io_axi_aw_bits_size(ahb_to_axi4_io_axi_aw_bits_size), + .io_axi_w_valid(ahb_to_axi4_io_axi_w_valid), + .io_axi_w_bits_data(ahb_to_axi4_io_axi_w_bits_data), + .io_axi_w_bits_strb(ahb_to_axi4_io_axi_w_bits_strb), .io_axi_ar_ready(ahb_to_axi4_io_axi_ar_ready), .io_axi_ar_valid(ahb_to_axi4_io_axi_ar_valid), + .io_axi_ar_bits_addr(ahb_to_axi4_io_axi_ar_bits_addr), + .io_axi_ar_bits_size(ahb_to_axi4_io_axi_ar_bits_size), .io_axi_r_valid(ahb_to_axi4_io_axi_r_valid), + .io_axi_r_bits_data(ahb_to_axi4_io_axi_r_bits_data), .io_axi_r_bits_resp(ahb_to_axi4_io_axi_r_bits_resp), - .io_ahb_sig_in_hresp(ahb_to_axi4_io_ahb_sig_in_hresp) + .io_ahb_sig_in_hrdata(ahb_to_axi4_io_ahb_sig_in_hrdata), + .io_ahb_sig_in_hready(ahb_to_axi4_io_ahb_sig_in_hready), + .io_ahb_sig_in_hresp(ahb_to_axi4_io_ahb_sig_in_hresp), + .io_ahb_sig_out_haddr(ahb_to_axi4_io_ahb_sig_out_haddr), + .io_ahb_sig_out_hsize(ahb_to_axi4_io_ahb_sig_out_hsize), + .io_ahb_sig_out_htrans(ahb_to_axi4_io_ahb_sig_out_htrans), + .io_ahb_sig_out_hwrite(ahb_to_axi4_io_ahb_sig_out_hwrite), + .io_ahb_sig_out_hwdata(ahb_to_axi4_io_ahb_sig_out_hwdata), + .io_ahb_hsel(ahb_to_axi4_io_ahb_hsel), + .io_ahb_hreadyin(ahb_to_axi4_io_ahb_hreadyin) ); - assign io_core_rst_l = reset & _T_2; // @[quasar.scala 80:17] - assign io_rv_trace_pkt_rv_i_valid_ip = dec_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar.scala 220:19] - assign io_rv_trace_pkt_rv_i_insn_ip = dec_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar.scala 220:19] - assign io_rv_trace_pkt_rv_i_address_ip = dec_io_rv_trace_pkt_rv_i_address_ip; // @[quasar.scala 220:19] - assign io_rv_trace_pkt_rv_i_exception_ip = dec_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar.scala 220:19] - assign io_rv_trace_pkt_rv_i_ecause_ip = dec_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar.scala 220:19] - assign io_rv_trace_pkt_rv_i_interrupt_ip = dec_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar.scala 220:19] - assign io_rv_trace_pkt_rv_i_tval_ip = dec_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar.scala 220:19] - assign io_dccm_clk_override = dec_io_dec_tlu_dccm_clk_override; // @[quasar.scala 223:24] - assign io_icm_clk_override = dec_io_dec_tlu_icm_clk_override; // @[quasar.scala 224:23] - assign io_dec_tlu_core_ecc_disable = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 225:31] - assign io_o_cpu_halt_ack = dec_io_o_cpu_halt_ack; // @[quasar.scala 226:21] - assign io_o_cpu_halt_status = dec_io_o_cpu_halt_status; // @[quasar.scala 227:24] - assign io_o_cpu_run_ack = dec_io_o_cpu_run_ack; // @[quasar.scala 228:20] - assign io_o_debug_mode_status = dec_io_o_debug_mode_status; // @[quasar.scala 229:26] - assign io_mpc_debug_halt_ack = dec_io_mpc_debug_halt_ack; // @[quasar.scala 230:25] - assign io_mpc_debug_run_ack = dec_io_mpc_debug_run_ack; // @[quasar.scala 231:24] - assign io_debug_brkpt_status = dec_io_debug_brkpt_status; // @[quasar.scala 232:25] - assign io_dec_tlu_perfcnt0 = dec_io_dec_tlu_perfcnt0; // @[quasar.scala 233:23] - assign io_dec_tlu_perfcnt1 = dec_io_dec_tlu_perfcnt1; // @[quasar.scala 234:23] - assign io_dec_tlu_perfcnt2 = dec_io_dec_tlu_perfcnt2; // @[quasar.scala 235:23] - assign io_dec_tlu_perfcnt3 = dec_io_dec_tlu_perfcnt3; // @[quasar.scala 236:23] - assign io_dccm_wren = lsu_io_dccm_wren; // @[quasar.scala 238:11] - assign io_dccm_rden = lsu_io_dccm_rden; // @[quasar.scala 238:11] - assign io_dccm_wr_addr_lo = lsu_io_dccm_wr_addr_lo; // @[quasar.scala 238:11] - assign io_dccm_wr_addr_hi = lsu_io_dccm_wr_addr_hi; // @[quasar.scala 238:11] - assign io_dccm_rd_addr_lo = lsu_io_dccm_rd_addr_lo; // @[quasar.scala 238:11] - assign io_dccm_rd_addr_hi = lsu_io_dccm_rd_addr_hi; // @[quasar.scala 238:11] - assign io_dccm_wr_data_lo = lsu_io_dccm_wr_data_lo; // @[quasar.scala 238:11] - assign io_dccm_wr_data_hi = lsu_io_dccm_wr_data_hi; // @[quasar.scala 238:11] - assign io_ic_rw_addr = ifu_io_ic_rw_addr; // @[quasar.scala 101:13] - assign io_ic_tag_valid = ifu_io_ic_tag_valid; // @[quasar.scala 101:13] - assign io_ic_wr_en = ifu_io_ic_wr_en; // @[quasar.scala 101:13] - assign io_ic_rd_en = ifu_io_ic_rd_en; // @[quasar.scala 101:13] - assign io_ic_wr_data_0 = ifu_io_ic_wr_data_0; // @[quasar.scala 101:13] - assign io_ic_wr_data_1 = ifu_io_ic_wr_data_1; // @[quasar.scala 101:13] - assign io_ic_debug_wr_data = ifu_io_ic_debug_wr_data; // @[quasar.scala 101:13] - assign io_ic_debug_addr = ifu_io_ic_debug_addr; // @[quasar.scala 101:13] - assign io_ic_debug_rd_en = ifu_io_ic_debug_rd_en; // @[quasar.scala 101:13] - assign io_ic_debug_wr_en = ifu_io_ic_debug_wr_en; // @[quasar.scala 101:13] - assign io_ic_debug_tag_array = ifu_io_ic_debug_tag_array; // @[quasar.scala 101:13] - assign io_ic_debug_way = ifu_io_ic_debug_way; // @[quasar.scala 101:13] - assign io_ic_premux_data = ifu_io_ic_premux_data; // @[quasar.scala 101:13] - assign io_ic_sel_premux_data = ifu_io_ic_sel_premux_data; // @[quasar.scala 101:13] - assign io_iccm_rw_addr = ifu_io_iccm_rw_addr; // @[quasar.scala 102:15] - assign io_iccm_buf_correct_ecc = ifu_io_iccm_buf_correct_ecc; // @[quasar.scala 102:15] - assign io_iccm_correction_state = ifu_io_iccm_correction_state; // @[quasar.scala 102:15] - assign io_iccm_wren = ifu_io_iccm_wren; // @[quasar.scala 102:15] - assign io_iccm_rden = ifu_io_iccm_rden; // @[quasar.scala 102:15] - assign io_iccm_wr_size = ifu_io_iccm_wr_size; // @[quasar.scala 102:15] - assign io_iccm_wr_data = ifu_io_iccm_wr_data; // @[quasar.scala 102:15] + assign io_lsu_ahb_out_haddr = axi4_to_ahb_2_io_ahb_out_haddr; // @[quasar.scala 254:28] + assign io_lsu_ahb_out_hsize = axi4_to_ahb_2_io_ahb_out_hsize; // @[quasar.scala 254:28] + assign io_lsu_ahb_out_htrans = axi4_to_ahb_2_io_ahb_out_htrans; // @[quasar.scala 254:28] + assign io_lsu_ahb_out_hwrite = axi4_to_ahb_2_io_ahb_out_hwrite; // @[quasar.scala 254:28] + assign io_lsu_ahb_out_hwdata = axi4_to_ahb_2_io_ahb_out_hwdata; // @[quasar.scala 254:28] + assign io_ifu_ahb_out_haddr = axi4_to_ahb_1_io_ahb_out_haddr; // @[quasar.scala 260:28] + assign io_ifu_ahb_out_hsize = axi4_to_ahb_1_io_ahb_out_hsize; // @[quasar.scala 260:28] + assign io_ifu_ahb_out_htrans = axi4_to_ahb_1_io_ahb_out_htrans; // @[quasar.scala 260:28] + assign io_ifu_ahb_out_hwrite = axi4_to_ahb_1_io_ahb_out_hwrite; // @[quasar.scala 260:28] + assign io_ifu_ahb_out_hwdata = axi4_to_ahb_1_io_ahb_out_hwdata; // @[quasar.scala 260:28] + assign io_sb_ahb_out_haddr = axi4_to_ahb_io_ahb_out_haddr; // @[quasar.scala 267:27] + assign io_sb_ahb_out_hsize = axi4_to_ahb_io_ahb_out_hsize; // @[quasar.scala 267:27] + assign io_sb_ahb_out_htrans = axi4_to_ahb_io_ahb_out_htrans; // @[quasar.scala 267:27] + assign io_sb_ahb_out_hwrite = axi4_to_ahb_io_ahb_out_hwrite; // @[quasar.scala 267:27] + assign io_sb_ahb_out_hwdata = axi4_to_ahb_io_ahb_out_hwdata; // @[quasar.scala 267:27] + assign io_dma_ahb_sig_in_hrdata = ahb_to_axi4_io_ahb_sig_in_hrdata; // @[quasar.scala 273:28] + assign io_dma_ahb_sig_in_hready = ahb_to_axi4_io_ahb_sig_in_hready; // @[quasar.scala 273:28] + assign io_dma_ahb_sig_in_hresp = ahb_to_axi4_io_ahb_sig_in_hresp; // @[quasar.scala 273:28] + assign io_core_rst_l = reset & _T_2; // @[quasar.scala 82:17] + assign io_rv_trace_pkt_rv_i_valid_ip = dec_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar.scala 222:19] + assign io_rv_trace_pkt_rv_i_insn_ip = dec_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar.scala 222:19] + assign io_rv_trace_pkt_rv_i_address_ip = dec_io_rv_trace_pkt_rv_i_address_ip; // @[quasar.scala 222:19] + assign io_rv_trace_pkt_rv_i_exception_ip = dec_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar.scala 222:19] + assign io_rv_trace_pkt_rv_i_ecause_ip = dec_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar.scala 222:19] + assign io_rv_trace_pkt_rv_i_interrupt_ip = dec_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar.scala 222:19] + assign io_rv_trace_pkt_rv_i_tval_ip = dec_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar.scala 222:19] + assign io_dccm_clk_override = dec_io_dec_tlu_dccm_clk_override; // @[quasar.scala 225:24] + assign io_icm_clk_override = dec_io_dec_tlu_icm_clk_override; // @[quasar.scala 226:23] + assign io_dec_tlu_core_ecc_disable = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 227:31] + assign io_o_cpu_halt_ack = dec_io_o_cpu_halt_ack; // @[quasar.scala 228:21] + assign io_o_cpu_halt_status = dec_io_o_cpu_halt_status; // @[quasar.scala 229:24] + assign io_o_cpu_run_ack = dec_io_o_cpu_run_ack; // @[quasar.scala 230:20] + assign io_o_debug_mode_status = dec_io_o_debug_mode_status; // @[quasar.scala 231:26] + assign io_mpc_debug_halt_ack = dec_io_mpc_debug_halt_ack; // @[quasar.scala 232:25] + assign io_mpc_debug_run_ack = dec_io_mpc_debug_run_ack; // @[quasar.scala 233:24] + assign io_debug_brkpt_status = dec_io_debug_brkpt_status; // @[quasar.scala 234:25] + assign io_dec_tlu_perfcnt0 = dec_io_dec_tlu_perfcnt0; // @[quasar.scala 235:23] + assign io_dec_tlu_perfcnt1 = dec_io_dec_tlu_perfcnt1; // @[quasar.scala 236:23] + assign io_dec_tlu_perfcnt2 = dec_io_dec_tlu_perfcnt2; // @[quasar.scala 237:23] + assign io_dec_tlu_perfcnt3 = dec_io_dec_tlu_perfcnt3; // @[quasar.scala 238:23] + assign io_dccm_wren = lsu_io_dccm_wren; // @[quasar.scala 242:11] + assign io_dccm_rden = lsu_io_dccm_rden; // @[quasar.scala 242:11] + assign io_dccm_wr_addr_lo = lsu_io_dccm_wr_addr_lo; // @[quasar.scala 242:11] + assign io_dccm_wr_addr_hi = lsu_io_dccm_wr_addr_hi; // @[quasar.scala 242:11] + assign io_dccm_rd_addr_lo = lsu_io_dccm_rd_addr_lo; // @[quasar.scala 242:11] + assign io_dccm_rd_addr_hi = lsu_io_dccm_rd_addr_hi; // @[quasar.scala 242:11] + assign io_dccm_wr_data_lo = lsu_io_dccm_wr_data_lo; // @[quasar.scala 242:11] + assign io_dccm_wr_data_hi = lsu_io_dccm_wr_data_hi; // @[quasar.scala 242:11] + assign io_ic_rw_addr = ifu_io_ic_rw_addr; // @[quasar.scala 103:13] + assign io_ic_tag_valid = ifu_io_ic_tag_valid; // @[quasar.scala 103:13] + assign io_ic_wr_en = ifu_io_ic_wr_en; // @[quasar.scala 103:13] + assign io_ic_rd_en = ifu_io_ic_rd_en; // @[quasar.scala 103:13] + assign io_ic_wr_data_0 = ifu_io_ic_wr_data_0; // @[quasar.scala 103:13] + assign io_ic_wr_data_1 = ifu_io_ic_wr_data_1; // @[quasar.scala 103:13] + assign io_ic_debug_wr_data = ifu_io_ic_debug_wr_data; // @[quasar.scala 103:13] + assign io_ic_debug_addr = ifu_io_ic_debug_addr; // @[quasar.scala 103:13] + assign io_ic_debug_rd_en = ifu_io_ic_debug_rd_en; // @[quasar.scala 103:13] + assign io_ic_debug_wr_en = ifu_io_ic_debug_wr_en; // @[quasar.scala 103:13] + assign io_ic_debug_tag_array = ifu_io_ic_debug_tag_array; // @[quasar.scala 103:13] + assign io_ic_debug_way = ifu_io_ic_debug_way; // @[quasar.scala 103:13] + assign io_ic_premux_data = ifu_io_ic_premux_data; // @[quasar.scala 103:13] + assign io_ic_sel_premux_data = ifu_io_ic_sel_premux_data; // @[quasar.scala 103:13] + assign io_iccm_rw_addr = ifu_io_iccm_rw_addr; // @[quasar.scala 104:15] + assign io_iccm_buf_correct_ecc = ifu_io_iccm_buf_correct_ecc; // @[quasar.scala 104:15] + assign io_iccm_correction_state = ifu_io_iccm_correction_state; // @[quasar.scala 104:15] + assign io_iccm_wren = ifu_io_iccm_wren; // @[quasar.scala 104:15] + assign io_iccm_rden = ifu_io_iccm_rden; // @[quasar.scala 104:15] + assign io_iccm_wr_size = ifu_io_iccm_wr_size; // @[quasar.scala 104:15] + assign io_iccm_wr_data = ifu_io_iccm_wr_data; // @[quasar.scala 104:15] + assign io_dmi_reg_rdata = dbg_io_dmi_reg_rdata; // @[quasar.scala 239:20] assign ifu_clock = clock; - assign ifu_reset = io_core_rst_l; // @[quasar.scala 91:13] - assign ifu_io_exu_flush_final = dec_io_exu_flush_final; // @[quasar.scala 96:26] - assign ifu_io_exu_flush_path_final = exu_io_exu_flush_path_final; // @[quasar.scala 97:31] - assign ifu_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 93:19] - assign ifu_io_active_clk = rvclkhdr_1_io_l1clk; // @[quasar.scala 94:21] - assign ifu_io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d = dec_io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d; // @[quasar.scala 89:18] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[quasar.scala 89:18] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[quasar.scala 89:18] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 89:18] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb; // @[quasar.scala 89:18] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[quasar.scala 89:18 quasar.scala 107:51] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics; // @[quasar.scala 89:18 quasar.scala 107:51] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[quasar.scala 89:18 quasar.scala 107:51] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[quasar.scala 89:18 quasar.scala 107:51] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 89:18] - assign ifu_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb = dec_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb; // @[quasar.scala 89:18] - assign ifu_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff = dec_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 89:18] - assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid; // @[quasar.scala 89:18] - assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist; // @[quasar.scala 89:18] - assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[quasar.scala 89:18] - assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[quasar.scala 89:18] - assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[quasar.scala 89:18] - assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[quasar.scala 89:18] - assign ifu_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb = dec_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb; // @[quasar.scala 89:18] - assign ifu_io_ifu_dec_dec_bp_dec_tlu_bpred_disable = dec_io_ifu_dec_dec_bp_dec_tlu_bpred_disable; // @[quasar.scala 89:18] - assign ifu_io_exu_ifu_exu_bp_exu_i0_br_index_r = exu_io_dec_exu_tlu_exu_exu_i0_br_index_r; // @[quasar.scala 103:25 quasar.scala 105:43] - assign ifu_io_exu_ifu_exu_bp_exu_i0_br_fghr_r = exu_io_exu_bp_exu_i0_br_fghr_r; // @[quasar.scala 103:25 quasar.scala 104:42] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_misp = exu_io_exu_bp_exu_mp_pkt_bits_misp; // @[quasar.scala 103:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_ataken = exu_io_exu_bp_exu_mp_pkt_bits_ataken; // @[quasar.scala 103:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_boffset = exu_io_exu_bp_exu_mp_pkt_bits_boffset; // @[quasar.scala 103:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pc4 = exu_io_exu_bp_exu_mp_pkt_bits_pc4; // @[quasar.scala 103:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_hist = exu_io_exu_bp_exu_mp_pkt_bits_hist; // @[quasar.scala 103:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_toffset = exu_io_exu_bp_exu_mp_pkt_bits_toffset; // @[quasar.scala 103:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pcall = exu_io_exu_bp_exu_mp_pkt_bits_pcall; // @[quasar.scala 103:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pret = exu_io_exu_bp_exu_mp_pkt_bits_pret; // @[quasar.scala 103:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pja = exu_io_exu_bp_exu_mp_pkt_bits_pja; // @[quasar.scala 103:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_way = exu_io_exu_bp_exu_mp_pkt_bits_way; // @[quasar.scala 103:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_eghr = exu_io_exu_bp_exu_mp_eghr; // @[quasar.scala 103:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_fghr = exu_io_exu_bp_exu_mp_fghr; // @[quasar.scala 103:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_index = exu_io_exu_bp_exu_mp_index; // @[quasar.scala 103:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_btag = exu_io_exu_bp_exu_mp_btag; // @[quasar.scala 103:25] - assign ifu_io_iccm_rd_data = io_iccm_rd_data; // @[quasar.scala 102:15] - assign ifu_io_iccm_rd_data_ecc = io_iccm_rd_data_ecc; // @[quasar.scala 102:15] - assign ifu_io_ic_rd_data = io_ic_rd_data; // @[quasar.scala 101:13] - assign ifu_io_ic_debug_rd_data = io_ic_debug_rd_data; // @[quasar.scala 101:13] - assign ifu_io_ic_tag_debug_rd_data = io_ic_tag_debug_rd_data; // @[quasar.scala 101:13] - assign ifu_io_ic_eccerr = io_ic_eccerr; // @[quasar.scala 101:13] - assign ifu_io_ic_rd_hit = io_ic_rd_hit; // @[quasar.scala 101:13] - assign ifu_io_ic_tag_perr = io_ic_tag_perr; // @[quasar.scala 101:13] - assign ifu_io_ifu_ar_ready = axi4_to_ahb_1_io_axi_ar_ready; // @[quasar.scala 257:28] - assign ifu_io_ifu_r_valid = axi4_to_ahb_1_io_axi_r_valid; // @[quasar.scala 257:28] - assign ifu_io_ifu_r_bits_id = {{2'd0}, axi4_to_ahb_1_io_axi_r_bits_id}; // @[quasar.scala 257:28] - assign ifu_io_ifu_r_bits_data = axi4_to_ahb_1_io_axi_r_bits_data; // @[quasar.scala 257:28] - assign ifu_io_ifu_r_bits_resp = axi4_to_ahb_1_io_axi_r_bits_resp; // @[quasar.scala 257:28] - assign ifu_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[quasar.scala 99:25] - assign ifu_io_ifu_dma_dma_ifc_dma_iccm_stall_any = dma_ctrl_io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[quasar.scala 100:18] - assign ifu_io_ifu_dma_dma_mem_ctl_dma_iccm_req = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[quasar.scala 100:18] - assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_addr = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_addr; // @[quasar.scala 100:18] - assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_sz = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_sz; // @[quasar.scala 100:18] - assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_write = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_write; // @[quasar.scala 100:18] - assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_wdata = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_wdata; // @[quasar.scala 100:18] - assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_tag = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_tag; // @[quasar.scala 100:18] - assign ifu_io_dec_tlu_flush_lower_wb = dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 106:33] - assign ifu_io_scan_mode = io_scan_mode; // @[quasar.scala 92:20] + assign ifu_reset = io_core_rst_l; // @[quasar.scala 93:13] + assign ifu_io_exu_flush_final = dec_io_exu_flush_final; // @[quasar.scala 98:26] + assign ifu_io_exu_flush_path_final = exu_io_exu_flush_path_final; // @[quasar.scala 99:31] + assign ifu_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 95:19] + assign ifu_io_active_clk = rvclkhdr_1_io_l1clk; // @[quasar.scala 96:21] + assign ifu_io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d = dec_io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d; // @[quasar.scala 91:18] + assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[quasar.scala 91:18] + assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[quasar.scala 91:18] + assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 91:18] + assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb; // @[quasar.scala 91:18] + assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[quasar.scala 91:18 quasar.scala 109:51] + assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics; // @[quasar.scala 91:18 quasar.scala 109:51] + assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[quasar.scala 91:18 quasar.scala 109:51] + assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[quasar.scala 91:18 quasar.scala 109:51] + assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 91:18] + assign ifu_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb = dec_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb; // @[quasar.scala 91:18] + assign ifu_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff = dec_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 91:18] + assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid; // @[quasar.scala 91:18] + assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist; // @[quasar.scala 91:18] + assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[quasar.scala 91:18] + assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[quasar.scala 91:18] + assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[quasar.scala 91:18] + assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[quasar.scala 91:18] + assign ifu_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb = dec_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb; // @[quasar.scala 91:18] + assign ifu_io_ifu_dec_dec_bp_dec_tlu_bpred_disable = dec_io_ifu_dec_dec_bp_dec_tlu_bpred_disable; // @[quasar.scala 91:18] + assign ifu_io_exu_ifu_exu_bp_exu_i0_br_index_r = exu_io_dec_exu_tlu_exu_exu_i0_br_index_r; // @[quasar.scala 105:25 quasar.scala 107:43] + assign ifu_io_exu_ifu_exu_bp_exu_i0_br_fghr_r = exu_io_exu_bp_exu_i0_br_fghr_r; // @[quasar.scala 105:25 quasar.scala 106:42] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_misp = exu_io_exu_bp_exu_mp_pkt_bits_misp; // @[quasar.scala 105:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_ataken = exu_io_exu_bp_exu_mp_pkt_bits_ataken; // @[quasar.scala 105:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_boffset = exu_io_exu_bp_exu_mp_pkt_bits_boffset; // @[quasar.scala 105:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pc4 = exu_io_exu_bp_exu_mp_pkt_bits_pc4; // @[quasar.scala 105:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_hist = exu_io_exu_bp_exu_mp_pkt_bits_hist; // @[quasar.scala 105:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_toffset = exu_io_exu_bp_exu_mp_pkt_bits_toffset; // @[quasar.scala 105:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pcall = exu_io_exu_bp_exu_mp_pkt_bits_pcall; // @[quasar.scala 105:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pret = exu_io_exu_bp_exu_mp_pkt_bits_pret; // @[quasar.scala 105:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pja = exu_io_exu_bp_exu_mp_pkt_bits_pja; // @[quasar.scala 105:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_way = exu_io_exu_bp_exu_mp_pkt_bits_way; // @[quasar.scala 105:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_eghr = exu_io_exu_bp_exu_mp_eghr; // @[quasar.scala 105:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_fghr = exu_io_exu_bp_exu_mp_fghr; // @[quasar.scala 105:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_index = exu_io_exu_bp_exu_mp_index; // @[quasar.scala 105:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_btag = exu_io_exu_bp_exu_mp_btag; // @[quasar.scala 105:25] + assign ifu_io_iccm_rd_data = io_iccm_rd_data; // @[quasar.scala 104:15] + assign ifu_io_iccm_rd_data_ecc = io_iccm_rd_data_ecc; // @[quasar.scala 104:15] + assign ifu_io_ic_rd_data = io_ic_rd_data; // @[quasar.scala 103:13] + assign ifu_io_ic_debug_rd_data = io_ic_debug_rd_data; // @[quasar.scala 103:13] + assign ifu_io_ic_tag_debug_rd_data = io_ic_tag_debug_rd_data; // @[quasar.scala 103:13] + assign ifu_io_ic_eccerr = io_ic_eccerr; // @[quasar.scala 103:13] + assign ifu_io_ic_rd_hit = io_ic_rd_hit; // @[quasar.scala 103:13] + assign ifu_io_ic_tag_perr = io_ic_tag_perr; // @[quasar.scala 103:13] + assign ifu_io_ifu_ar_ready = axi4_to_ahb_1_io_axi_ar_ready; // @[quasar.scala 259:28] + assign ifu_io_ifu_r_valid = axi4_to_ahb_1_io_axi_r_valid; // @[quasar.scala 259:28] + assign ifu_io_ifu_r_bits_id = axi4_to_ahb_1_io_axi_r_bits_id; // @[quasar.scala 259:28] + assign ifu_io_ifu_r_bits_data = axi4_to_ahb_1_io_axi_r_bits_data; // @[quasar.scala 259:28] + assign ifu_io_ifu_r_bits_resp = axi4_to_ahb_1_io_axi_r_bits_resp; // @[quasar.scala 259:28] + assign ifu_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[quasar.scala 101:25] + assign ifu_io_ifu_dma_dma_ifc_dma_iccm_stall_any = dma_ctrl_io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[quasar.scala 102:18] + assign ifu_io_ifu_dma_dma_mem_ctl_dma_iccm_req = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[quasar.scala 102:18] + assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_addr = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_addr; // @[quasar.scala 102:18] + assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_sz = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_sz; // @[quasar.scala 102:18] + assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_write = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_write; // @[quasar.scala 102:18] + assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_wdata = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_wdata; // @[quasar.scala 102:18] + assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_tag = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_tag; // @[quasar.scala 102:18] + assign ifu_io_dec_tlu_flush_lower_wb = dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 108:33] + assign ifu_io_scan_mode = io_scan_mode; // @[quasar.scala 94:20] assign dec_clock = clock; - assign dec_reset = io_core_rst_l; // @[quasar.scala 110:13] - assign dec_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 111:19] - assign dec_io_active_clk = rvclkhdr_1_io_l1clk; // @[quasar.scala 112:21] - assign dec_io_lsu_fastint_stall_any = lsu_io_lsu_fastint_stall_any; // @[quasar.scala 113:32] - assign dec_io_rst_vec = io_rst_vec; // @[quasar.scala 114:18] - assign dec_io_nmi_int = io_nmi_int; // @[quasar.scala 115:18] - assign dec_io_nmi_vec = io_nmi_vec; // @[quasar.scala 116:18] - assign dec_io_i_cpu_halt_req = io_i_cpu_halt_req; // @[quasar.scala 117:25] - assign dec_io_i_cpu_run_req = io_i_cpu_run_req; // @[quasar.scala 118:24] - assign dec_io_core_id = io_core_id; // @[quasar.scala 119:18] - assign dec_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[quasar.scala 120:29] - assign dec_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[quasar.scala 121:28] - assign dec_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[quasar.scala 122:28] - assign dec_io_lsu_pmu_misaligned_m = lsu_io_lsu_pmu_misaligned_m; // @[quasar.scala 125:31] - assign dec_io_lsu_fir_addr = lsu_io_lsu_fir_addr; // @[quasar.scala 128:23] - assign dec_io_lsu_fir_error = lsu_io_lsu_fir_error; // @[quasar.scala 129:24] - assign dec_io_lsu_trigger_match_m = lsu_io_lsu_trigger_match_m; // @[quasar.scala 130:30] - assign dec_io_lsu_idle_any = lsu_io_lsu_idle_any; // @[quasar.scala 132:23] - assign dec_io_lsu_error_pkt_r_valid = lsu_io_lsu_error_pkt_r_valid; // @[quasar.scala 133:26] - assign dec_io_lsu_error_pkt_r_bits_single_ecc_error = lsu_io_lsu_error_pkt_r_bits_single_ecc_error; // @[quasar.scala 133:26] - assign dec_io_lsu_error_pkt_r_bits_inst_type = lsu_io_lsu_error_pkt_r_bits_inst_type; // @[quasar.scala 133:26] - assign dec_io_lsu_error_pkt_r_bits_exc_type = lsu_io_lsu_error_pkt_r_bits_exc_type; // @[quasar.scala 133:26] - assign dec_io_lsu_error_pkt_r_bits_mscause = lsu_io_lsu_error_pkt_r_bits_mscause; // @[quasar.scala 133:26] - assign dec_io_lsu_error_pkt_r_bits_addr = lsu_io_lsu_error_pkt_r_bits_addr; // @[quasar.scala 133:26] - assign dec_io_lsu_single_ecc_error_incr = lsu_io_lsu_single_ecc_error_incr; // @[quasar.scala 134:36] - assign dec_io_exu_div_result = exu_io_exu_div_result; // @[quasar.scala 135:25] - assign dec_io_exu_div_wren = exu_io_exu_div_wren; // @[quasar.scala 136:23] - assign dec_io_lsu_result_m = lsu_io_lsu_result_m; // @[quasar.scala 137:23] - assign dec_io_lsu_result_corr_r = lsu_io_lsu_result_corr_r; // @[quasar.scala 138:28] - assign dec_io_lsu_load_stall_any = lsu_io_lsu_load_stall_any; // @[quasar.scala 139:29] - assign dec_io_lsu_store_stall_any = lsu_io_lsu_store_stall_any; // @[quasar.scala 140:30] - assign dec_io_iccm_dma_sb_error = ifu_io_iccm_dma_sb_error; // @[quasar.scala 141:28] - assign dec_io_exu_flush_final = exu_io_exu_flush_final; // @[quasar.scala 142:26] - assign dec_io_timer_int = io_timer_int; // @[quasar.scala 148:20] - assign dec_io_soft_int = io_soft_int; // @[quasar.scala 144:19] - assign dec_io_dbg_halt_req = dbg_io_dbg_halt_req; // @[quasar.scala 145:23] - assign dec_io_dbg_resume_req = dbg_io_dbg_resume_req; // @[quasar.scala 146:25] - assign dec_io_exu_i0_br_way_r = exu_io_exu_bp_exu_i0_br_way_r; // @[quasar.scala 147:26] - assign dec_io_scan_mode = io_scan_mode; // @[quasar.scala 149:20] - assign dec_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst = ifu_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst; // @[quasar.scala 89:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf; // @[quasar.scala 89:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type; // @[quasar.scala 89:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1 = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1; // @[quasar.scala 89:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc; // @[quasar.scala 89:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index; // @[quasar.scala 89:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[quasar.scala 89:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag; // @[quasar.scala 89:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid; // @[quasar.scala 89:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr; // @[quasar.scala 89:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc; // @[quasar.scala 89:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4 = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4; // @[quasar.scala 89:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid; // @[quasar.scala 89:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset; // @[quasar.scala 89:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist; // @[quasar.scala 89:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error; // @[quasar.scala 89:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[quasar.scala 89:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett; // @[quasar.scala 89:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way; // @[quasar.scala 89:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret; // @[quasar.scala 89:18] - assign dec_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned = ifu_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned; // @[quasar.scala 89:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss; // @[quasar.scala 89:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[quasar.scala 89:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[quasar.scala 89:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[quasar.scala 89:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[quasar.scala 89:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start = ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[quasar.scala 89:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err = ifu_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[quasar.scala 89:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data = ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[quasar.scala 89:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid = ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[quasar.scala 89:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle = ifu_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle; // @[quasar.scala 89:18] - assign dec_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall = ifu_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall; // @[quasar.scala 89:18] - assign dec_io_dec_exu_dec_alu_exu_i0_pc_x = exu_io_dec_exu_dec_alu_exu_i0_pc_x; // @[quasar.scala 152:18] - assign dec_io_dec_exu_decode_exu_exu_i0_result_x = exu_io_dec_exu_decode_exu_exu_i0_result_x; // @[quasar.scala 152:18] - assign dec_io_dec_exu_decode_exu_exu_csr_rs1_x = exu_io_dec_exu_decode_exu_exu_csr_rs1_x; // @[quasar.scala 152:18] - assign dec_io_dec_exu_tlu_exu_exu_i0_br_hist_r = exu_io_dec_exu_tlu_exu_exu_i0_br_hist_r; // @[quasar.scala 152:18] - assign dec_io_dec_exu_tlu_exu_exu_i0_br_error_r = exu_io_dec_exu_tlu_exu_exu_i0_br_error_r; // @[quasar.scala 152:18] - assign dec_io_dec_exu_tlu_exu_exu_i0_br_start_error_r = exu_io_dec_exu_tlu_exu_exu_i0_br_start_error_r; // @[quasar.scala 152:18] - assign dec_io_dec_exu_tlu_exu_exu_i0_br_valid_r = exu_io_dec_exu_tlu_exu_exu_i0_br_valid_r; // @[quasar.scala 152:18] - assign dec_io_dec_exu_tlu_exu_exu_i0_br_mp_r = exu_io_dec_exu_tlu_exu_exu_i0_br_mp_r; // @[quasar.scala 152:18] - assign dec_io_dec_exu_tlu_exu_exu_i0_br_middle_r = exu_io_dec_exu_tlu_exu_exu_i0_br_middle_r; // @[quasar.scala 152:18] - assign dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp = exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp; // @[quasar.scala 152:18] - assign dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken = exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken; // @[quasar.scala 152:18] - assign dec_io_dec_exu_tlu_exu_exu_pmu_i0_pc4 = exu_io_dec_exu_tlu_exu_exu_pmu_i0_pc4; // @[quasar.scala 152:18] - assign dec_io_dec_exu_tlu_exu_exu_npc_r = exu_io_dec_exu_tlu_exu_exu_npc_r; // @[quasar.scala 152:18] - assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[quasar.scala 123:18] - assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[quasar.scala 123:18] - assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 123:18] - assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 123:18] - assign dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any = lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[quasar.scala 123:18] - assign dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any = lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[quasar.scala 123:18] - assign dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any = lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any; // @[quasar.scala 123:18] - assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m; // @[quasar.scala 123:18] - assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m; // @[quasar.scala 123:18] - assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r; // @[quasar.scala 123:18] - assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[quasar.scala 123:18] - assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid; // @[quasar.scala 123:18] - assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error; // @[quasar.scala 123:18] - assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag; // @[quasar.scala 123:18] - assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data; // @[quasar.scala 123:18] - assign dec_io_lsu_tlu_lsu_pmu_load_external_m = lsu_io_lsu_tlu_lsu_pmu_load_external_m; // @[quasar.scala 124:18] - assign dec_io_lsu_tlu_lsu_pmu_store_external_m = lsu_io_lsu_tlu_lsu_pmu_store_external_m; // @[quasar.scala 124:18] - assign dec_io_dec_dbg_dbg_ib_dbg_cmd_valid = dbg_io_dbg_dec_dbg_ib_dbg_cmd_valid; // @[quasar.scala 131:18] - assign dec_io_dec_dbg_dbg_ib_dbg_cmd_write = dbg_io_dbg_dec_dbg_ib_dbg_cmd_write; // @[quasar.scala 131:18] - assign dec_io_dec_dbg_dbg_ib_dbg_cmd_type = dbg_io_dbg_dec_dbg_ib_dbg_cmd_type; // @[quasar.scala 131:18] - assign dec_io_dec_dbg_dbg_ib_dbg_cmd_addr = dbg_io_dbg_dec_dbg_ib_dbg_cmd_addr; // @[quasar.scala 131:18] - assign dec_io_dec_dbg_dbg_dctl_dbg_cmd_wrdata = dbg_io_dbg_dec_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 131:18] - assign dec_io_dec_dma_dctl_dma_dma_dccm_stall_any = dma_ctrl_io_dec_dma_dctl_dma_dma_dccm_stall_any; // @[quasar.scala 126:18] - assign dec_io_dec_dma_tlu_dma_dma_pmu_dccm_read = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_read; // @[quasar.scala 126:18] - assign dec_io_dec_dma_tlu_dma_dma_pmu_dccm_write = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_write; // @[quasar.scala 126:18] - assign dec_io_dec_dma_tlu_dma_dma_pmu_any_read = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_read; // @[quasar.scala 126:18] - assign dec_io_dec_dma_tlu_dma_dma_pmu_any_write = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_write; // @[quasar.scala 126:18] - assign dec_io_dec_dma_tlu_dma_dma_dccm_stall_any = dma_ctrl_io_dec_dma_tlu_dma_dma_dccm_stall_any; // @[quasar.scala 126:18] - assign dec_io_dec_dma_tlu_dma_dma_iccm_stall_any = dma_ctrl_io_dec_dma_tlu_dma_dma_iccm_stall_any; // @[quasar.scala 126:18] - assign dec_io_dec_pic_pic_claimid = pic_ctrl_inst_io_dec_pic_pic_claimid; // @[quasar.scala 218:28] - assign dec_io_dec_pic_pic_pl = pic_ctrl_inst_io_dec_pic_pic_pl; // @[quasar.scala 218:28] - assign dec_io_dec_pic_mhwakeup = pic_ctrl_inst_io_dec_pic_mhwakeup; // @[quasar.scala 218:28] - assign dec_io_dec_pic_mexintpend = pic_ctrl_inst_io_dec_pic_mexintpend; // @[quasar.scala 218:28] + assign dec_reset = io_core_rst_l; // @[quasar.scala 112:13] + assign dec_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 113:19] + assign dec_io_active_clk = rvclkhdr_1_io_l1clk; // @[quasar.scala 114:21] + assign dec_io_lsu_fastint_stall_any = lsu_io_lsu_fastint_stall_any; // @[quasar.scala 115:32] + assign dec_io_rst_vec = io_rst_vec; // @[quasar.scala 116:18] + assign dec_io_nmi_int = io_nmi_int; // @[quasar.scala 117:18] + assign dec_io_nmi_vec = io_nmi_vec; // @[quasar.scala 118:18] + assign dec_io_i_cpu_halt_req = io_i_cpu_halt_req; // @[quasar.scala 119:25] + assign dec_io_i_cpu_run_req = io_i_cpu_run_req; // @[quasar.scala 120:24] + assign dec_io_core_id = io_core_id; // @[quasar.scala 121:18] + assign dec_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[quasar.scala 122:29] + assign dec_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[quasar.scala 123:28] + assign dec_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[quasar.scala 124:28] + assign dec_io_lsu_pmu_misaligned_m = lsu_io_lsu_pmu_misaligned_m; // @[quasar.scala 127:31] + assign dec_io_lsu_fir_addr = lsu_io_lsu_fir_addr; // @[quasar.scala 130:23] + assign dec_io_lsu_fir_error = lsu_io_lsu_fir_error; // @[quasar.scala 131:24] + assign dec_io_lsu_trigger_match_m = lsu_io_lsu_trigger_match_m; // @[quasar.scala 132:30] + assign dec_io_lsu_idle_any = lsu_io_lsu_idle_any; // @[quasar.scala 134:23] + assign dec_io_lsu_error_pkt_r_valid = lsu_io_lsu_error_pkt_r_valid; // @[quasar.scala 135:26] + assign dec_io_lsu_error_pkt_r_bits_single_ecc_error = lsu_io_lsu_error_pkt_r_bits_single_ecc_error; // @[quasar.scala 135:26] + assign dec_io_lsu_error_pkt_r_bits_inst_type = lsu_io_lsu_error_pkt_r_bits_inst_type; // @[quasar.scala 135:26] + assign dec_io_lsu_error_pkt_r_bits_exc_type = lsu_io_lsu_error_pkt_r_bits_exc_type; // @[quasar.scala 135:26] + assign dec_io_lsu_error_pkt_r_bits_mscause = lsu_io_lsu_error_pkt_r_bits_mscause; // @[quasar.scala 135:26] + assign dec_io_lsu_error_pkt_r_bits_addr = lsu_io_lsu_error_pkt_r_bits_addr; // @[quasar.scala 135:26] + assign dec_io_lsu_single_ecc_error_incr = lsu_io_lsu_single_ecc_error_incr; // @[quasar.scala 136:36] + assign dec_io_exu_div_result = exu_io_exu_div_result; // @[quasar.scala 137:25] + assign dec_io_exu_div_wren = exu_io_exu_div_wren; // @[quasar.scala 138:23] + assign dec_io_lsu_result_m = lsu_io_lsu_result_m; // @[quasar.scala 139:23] + assign dec_io_lsu_result_corr_r = lsu_io_lsu_result_corr_r; // @[quasar.scala 140:28] + assign dec_io_lsu_load_stall_any = lsu_io_lsu_load_stall_any; // @[quasar.scala 141:29] + assign dec_io_lsu_store_stall_any = lsu_io_lsu_store_stall_any; // @[quasar.scala 142:30] + assign dec_io_iccm_dma_sb_error = ifu_io_iccm_dma_sb_error; // @[quasar.scala 143:28] + assign dec_io_exu_flush_final = exu_io_exu_flush_final; // @[quasar.scala 144:26] + assign dec_io_timer_int = io_timer_int; // @[quasar.scala 150:20] + assign dec_io_soft_int = io_soft_int; // @[quasar.scala 146:19] + assign dec_io_dbg_halt_req = dbg_io_dbg_halt_req; // @[quasar.scala 147:23] + assign dec_io_dbg_resume_req = dbg_io_dbg_resume_req; // @[quasar.scala 148:25] + assign dec_io_exu_i0_br_way_r = exu_io_exu_bp_exu_i0_br_way_r; // @[quasar.scala 149:26] + assign dec_io_scan_mode = io_scan_mode; // @[quasar.scala 151:20] + assign dec_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst = ifu_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst; // @[quasar.scala 91:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf; // @[quasar.scala 91:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type; // @[quasar.scala 91:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1 = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1; // @[quasar.scala 91:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc; // @[quasar.scala 91:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index; // @[quasar.scala 91:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[quasar.scala 91:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag; // @[quasar.scala 91:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid; // @[quasar.scala 91:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr; // @[quasar.scala 91:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc; // @[quasar.scala 91:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4 = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4; // @[quasar.scala 91:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid; // @[quasar.scala 91:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset; // @[quasar.scala 91:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist; // @[quasar.scala 91:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error; // @[quasar.scala 91:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[quasar.scala 91:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett; // @[quasar.scala 91:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way; // @[quasar.scala 91:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret; // @[quasar.scala 91:18] + assign dec_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned = ifu_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned; // @[quasar.scala 91:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss; // @[quasar.scala 91:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[quasar.scala 91:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[quasar.scala 91:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[quasar.scala 91:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[quasar.scala 91:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start = ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[quasar.scala 91:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err = ifu_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[quasar.scala 91:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data = ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[quasar.scala 91:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid = ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[quasar.scala 91:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle = ifu_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle; // @[quasar.scala 91:18] + assign dec_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall = ifu_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall; // @[quasar.scala 91:18] + assign dec_io_dec_exu_dec_alu_exu_i0_pc_x = exu_io_dec_exu_dec_alu_exu_i0_pc_x; // @[quasar.scala 154:18] + assign dec_io_dec_exu_decode_exu_exu_i0_result_x = exu_io_dec_exu_decode_exu_exu_i0_result_x; // @[quasar.scala 154:18] + assign dec_io_dec_exu_decode_exu_exu_csr_rs1_x = exu_io_dec_exu_decode_exu_exu_csr_rs1_x; // @[quasar.scala 154:18] + assign dec_io_dec_exu_tlu_exu_exu_i0_br_hist_r = exu_io_dec_exu_tlu_exu_exu_i0_br_hist_r; // @[quasar.scala 154:18] + assign dec_io_dec_exu_tlu_exu_exu_i0_br_error_r = exu_io_dec_exu_tlu_exu_exu_i0_br_error_r; // @[quasar.scala 154:18] + assign dec_io_dec_exu_tlu_exu_exu_i0_br_start_error_r = exu_io_dec_exu_tlu_exu_exu_i0_br_start_error_r; // @[quasar.scala 154:18] + assign dec_io_dec_exu_tlu_exu_exu_i0_br_valid_r = exu_io_dec_exu_tlu_exu_exu_i0_br_valid_r; // @[quasar.scala 154:18] + assign dec_io_dec_exu_tlu_exu_exu_i0_br_mp_r = exu_io_dec_exu_tlu_exu_exu_i0_br_mp_r; // @[quasar.scala 154:18] + assign dec_io_dec_exu_tlu_exu_exu_i0_br_middle_r = exu_io_dec_exu_tlu_exu_exu_i0_br_middle_r; // @[quasar.scala 154:18] + assign dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp = exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp; // @[quasar.scala 154:18] + assign dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken = exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken; // @[quasar.scala 154:18] + assign dec_io_dec_exu_tlu_exu_exu_pmu_i0_pc4 = exu_io_dec_exu_tlu_exu_exu_pmu_i0_pc4; // @[quasar.scala 154:18] + assign dec_io_dec_exu_tlu_exu_exu_npc_r = exu_io_dec_exu_tlu_exu_exu_npc_r; // @[quasar.scala 154:18] + assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[quasar.scala 125:18] + assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[quasar.scala 125:18] + assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 125:18] + assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 125:18] + assign dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any = lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[quasar.scala 125:18] + assign dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any = lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[quasar.scala 125:18] + assign dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any = lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any; // @[quasar.scala 125:18] + assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m; // @[quasar.scala 125:18] + assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m; // @[quasar.scala 125:18] + assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r; // @[quasar.scala 125:18] + assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[quasar.scala 125:18] + assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid; // @[quasar.scala 125:18] + assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error; // @[quasar.scala 125:18] + assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag; // @[quasar.scala 125:18] + assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data; // @[quasar.scala 125:18] + assign dec_io_lsu_tlu_lsu_pmu_load_external_m = lsu_io_lsu_tlu_lsu_pmu_load_external_m; // @[quasar.scala 126:18] + assign dec_io_lsu_tlu_lsu_pmu_store_external_m = lsu_io_lsu_tlu_lsu_pmu_store_external_m; // @[quasar.scala 126:18] + assign dec_io_dec_dbg_dbg_ib_dbg_cmd_valid = dbg_io_dbg_dec_dbg_ib_dbg_cmd_valid; // @[quasar.scala 133:18] + assign dec_io_dec_dbg_dbg_ib_dbg_cmd_write = dbg_io_dbg_dec_dbg_ib_dbg_cmd_write; // @[quasar.scala 133:18] + assign dec_io_dec_dbg_dbg_ib_dbg_cmd_type = dbg_io_dbg_dec_dbg_ib_dbg_cmd_type; // @[quasar.scala 133:18] + assign dec_io_dec_dbg_dbg_ib_dbg_cmd_addr = dbg_io_dbg_dec_dbg_ib_dbg_cmd_addr; // @[quasar.scala 133:18] + assign dec_io_dec_dbg_dbg_dctl_dbg_cmd_wrdata = dbg_io_dbg_dec_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 133:18] + assign dec_io_dec_dma_dctl_dma_dma_dccm_stall_any = dma_ctrl_io_dec_dma_dctl_dma_dma_dccm_stall_any; // @[quasar.scala 128:18] + assign dec_io_dec_dma_tlu_dma_dma_pmu_dccm_read = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_read; // @[quasar.scala 128:18] + assign dec_io_dec_dma_tlu_dma_dma_pmu_dccm_write = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_write; // @[quasar.scala 128:18] + assign dec_io_dec_dma_tlu_dma_dma_pmu_any_read = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_read; // @[quasar.scala 128:18] + assign dec_io_dec_dma_tlu_dma_dma_pmu_any_write = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_write; // @[quasar.scala 128:18] + assign dec_io_dec_dma_tlu_dma_dma_dccm_stall_any = dma_ctrl_io_dec_dma_tlu_dma_dma_dccm_stall_any; // @[quasar.scala 128:18] + assign dec_io_dec_dma_tlu_dma_dma_iccm_stall_any = dma_ctrl_io_dec_dma_tlu_dma_dma_iccm_stall_any; // @[quasar.scala 128:18] + assign dec_io_dec_pic_pic_claimid = pic_ctrl_inst_io_dec_pic_pic_claimid; // @[quasar.scala 220:28] + assign dec_io_dec_pic_pic_pl = pic_ctrl_inst_io_dec_pic_pic_pl; // @[quasar.scala 220:28] + assign dec_io_dec_pic_mhwakeup = pic_ctrl_inst_io_dec_pic_mhwakeup; // @[quasar.scala 220:28] + assign dec_io_dec_pic_mexintpend = pic_ctrl_inst_io_dec_pic_mexintpend; // @[quasar.scala 220:28] assign dbg_clock = clock; - assign dbg_reset = io_core_rst_l; // @[quasar.scala 177:13] - assign dbg_io_core_dbg_rddata = dma_ctrl_io_dma_dbg_cmd_done ? dma_ctrl_io_dma_dbg_rddata : dec_io_dec_dbg_rddata; // @[quasar.scala 178:26] - assign dbg_io_core_dbg_cmd_done = dma_ctrl_io_dma_dbg_cmd_done | dec_io_dec_dbg_cmd_done; // @[quasar.scala 179:28] - assign dbg_io_core_dbg_cmd_fail = dma_ctrl_io_dma_dbg_cmd_fail | dec_io_dec_dbg_cmd_fail; // @[quasar.scala 180:28] - assign dbg_io_dec_tlu_debug_mode = dec_io_dec_tlu_debug_mode; // @[quasar.scala 181:29] - assign dbg_io_dec_tlu_dbg_halted = dec_io_dec_tlu_dbg_halted; // @[quasar.scala 182:29] - assign dbg_io_dec_tlu_mpc_halted_only = dec_io_dec_tlu_mpc_halted_only; // @[quasar.scala 183:34] - assign dbg_io_dec_tlu_resume_ack = dec_io_dec_tlu_resume_ack; // @[quasar.scala 184:29] - assign dbg_io_dmi_reg_en = io_dmi_reg_en; // @[quasar.scala 185:21] - assign dbg_io_dmi_reg_addr = io_dmi_reg_addr; // @[quasar.scala 186:23] - assign dbg_io_dmi_reg_wr_en = io_dmi_reg_wr_en; // @[quasar.scala 187:24] - assign dbg_io_dmi_reg_wdata = io_dmi_reg_wdata; // @[quasar.scala 188:24] - assign dbg_io_sb_axi_aw_ready = axi4_to_ahb_io_axi_aw_ready; // @[quasar.scala 263:27] - assign dbg_io_sb_axi_w_ready = axi4_to_ahb_io_axi_w_ready; // @[quasar.scala 263:27] - assign dbg_io_sb_axi_b_valid = axi4_to_ahb_io_axi_b_valid; // @[quasar.scala 263:27] - assign dbg_io_sb_axi_b_bits_resp = axi4_to_ahb_io_axi_b_bits_resp; // @[quasar.scala 263:27] - assign dbg_io_sb_axi_ar_ready = axi4_to_ahb_io_axi_ar_ready; // @[quasar.scala 263:27] - assign dbg_io_sb_axi_r_valid = axi4_to_ahb_io_axi_r_valid; // @[quasar.scala 263:27] - assign dbg_io_sb_axi_r_bits_data = axi4_to_ahb_io_axi_r_bits_data; // @[quasar.scala 263:27] - assign dbg_io_sb_axi_r_bits_resp = axi4_to_ahb_io_axi_r_bits_resp; // @[quasar.scala 263:27] - assign dbg_io_dbg_dma_io_dma_dbg_ready = dma_ctrl_io_dbg_dma_io_dma_dbg_ready; // @[quasar.scala 202:26] - assign dbg_io_dbg_bus_clk_en = io_dbg_bus_clk_en; // @[quasar.scala 189:25] - assign dbg_io_dbg_rst_l = io_dbg_rst_l; // @[quasar.scala 190:20] - assign dbg_io_clk_override = dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 191:23] - assign dbg_io_scan_mode = io_scan_mode; // @[quasar.scala 192:20] + assign dbg_reset = io_core_rst_l; // @[quasar.scala 179:13] + assign dbg_io_core_dbg_rddata = dma_ctrl_io_dma_dbg_cmd_done ? dma_ctrl_io_dma_dbg_rddata : dec_io_dec_dbg_rddata; // @[quasar.scala 180:26] + assign dbg_io_core_dbg_cmd_done = dma_ctrl_io_dma_dbg_cmd_done | dec_io_dec_dbg_cmd_done; // @[quasar.scala 181:28] + assign dbg_io_core_dbg_cmd_fail = dma_ctrl_io_dma_dbg_cmd_fail | dec_io_dec_dbg_cmd_fail; // @[quasar.scala 182:28] + assign dbg_io_dec_tlu_debug_mode = dec_io_dec_tlu_debug_mode; // @[quasar.scala 183:29] + assign dbg_io_dec_tlu_dbg_halted = dec_io_dec_tlu_dbg_halted; // @[quasar.scala 184:29] + assign dbg_io_dec_tlu_mpc_halted_only = dec_io_dec_tlu_mpc_halted_only; // @[quasar.scala 185:34] + assign dbg_io_dec_tlu_resume_ack = dec_io_dec_tlu_resume_ack; // @[quasar.scala 186:29] + assign dbg_io_dmi_reg_en = io_dmi_reg_en; // @[quasar.scala 187:21] + assign dbg_io_dmi_reg_addr = io_dmi_reg_addr; // @[quasar.scala 188:23] + assign dbg_io_dmi_reg_wr_en = io_dmi_reg_wr_en; // @[quasar.scala 189:24] + assign dbg_io_dmi_reg_wdata = io_dmi_reg_wdata; // @[quasar.scala 190:24] + assign dbg_io_sb_axi_aw_ready = axi4_to_ahb_io_axi_aw_ready; // @[quasar.scala 266:27] + assign dbg_io_sb_axi_w_ready = axi4_to_ahb_io_axi_w_ready; // @[quasar.scala 266:27] + assign dbg_io_sb_axi_b_valid = axi4_to_ahb_io_axi_b_valid; // @[quasar.scala 266:27] + assign dbg_io_sb_axi_b_bits_resp = axi4_to_ahb_io_axi_b_bits_resp; // @[quasar.scala 266:27] + assign dbg_io_sb_axi_ar_ready = axi4_to_ahb_io_axi_ar_ready; // @[quasar.scala 266:27] + assign dbg_io_sb_axi_r_valid = axi4_to_ahb_io_axi_r_valid; // @[quasar.scala 266:27] + assign dbg_io_sb_axi_r_bits_data = axi4_to_ahb_io_axi_r_bits_data; // @[quasar.scala 266:27] + assign dbg_io_sb_axi_r_bits_resp = axi4_to_ahb_io_axi_r_bits_resp; // @[quasar.scala 266:27] + assign dbg_io_dbg_dma_io_dma_dbg_ready = dma_ctrl_io_dbg_dma_io_dma_dbg_ready; // @[quasar.scala 204:26] + assign dbg_io_dbg_bus_clk_en = io_dbg_bus_clk_en; // @[quasar.scala 191:25] + assign dbg_io_dbg_rst_l = io_dbg_rst_l; // @[quasar.scala 192:20] + assign dbg_io_clk_override = dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 193:23] + assign dbg_io_scan_mode = io_scan_mode; // @[quasar.scala 194:20] assign exu_clock = clock; - assign exu_reset = io_core_rst_l; // @[quasar.scala 153:13] - assign exu_io_scan_mode = io_scan_mode; // @[quasar.scala 154:20] - assign exu_io_dec_exu_dec_alu_dec_i0_alu_decode_d = dec_io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[quasar.scala 152:18] - assign exu_io_dec_exu_dec_alu_dec_csr_ren_d = dec_io_dec_exu_dec_alu_dec_csr_ren_d; // @[quasar.scala 152:18] - assign exu_io_dec_exu_dec_alu_dec_i0_br_immed_d = dec_io_dec_exu_dec_alu_dec_i0_br_immed_d; // @[quasar.scala 152:18] - assign exu_io_dec_exu_dec_div_div_p_valid = dec_io_dec_exu_dec_div_div_p_valid; // @[quasar.scala 152:18] - assign exu_io_dec_exu_dec_div_div_p_bits_unsign = dec_io_dec_exu_dec_div_div_p_bits_unsign; // @[quasar.scala 152:18] - assign exu_io_dec_exu_dec_div_div_p_bits_rem = dec_io_dec_exu_dec_div_div_p_bits_rem; // @[quasar.scala 152:18] - assign exu_io_dec_exu_dec_div_dec_div_cancel = dec_io_dec_exu_dec_div_dec_div_cancel; // @[quasar.scala 152:18] - assign exu_io_dec_exu_decode_exu_dec_data_en = dec_io_dec_exu_decode_exu_dec_data_en; // @[quasar.scala 152:18] - assign exu_io_dec_exu_decode_exu_dec_ctl_en = dec_io_dec_exu_decode_exu_dec_ctl_en; // @[quasar.scala 152:18] - assign exu_io_dec_exu_decode_exu_i0_ap_land = dec_io_dec_exu_decode_exu_i0_ap_land; // @[quasar.scala 152:18] - assign exu_io_dec_exu_decode_exu_i0_ap_lor = dec_io_dec_exu_decode_exu_i0_ap_lor; // @[quasar.scala 152:18] - assign exu_io_dec_exu_decode_exu_i0_ap_lxor = dec_io_dec_exu_decode_exu_i0_ap_lxor; // @[quasar.scala 152:18] - assign exu_io_dec_exu_decode_exu_i0_ap_sll = dec_io_dec_exu_decode_exu_i0_ap_sll; // @[quasar.scala 152:18] - assign exu_io_dec_exu_decode_exu_i0_ap_srl = dec_io_dec_exu_decode_exu_i0_ap_srl; // @[quasar.scala 152:18] - assign exu_io_dec_exu_decode_exu_i0_ap_sra = dec_io_dec_exu_decode_exu_i0_ap_sra; // @[quasar.scala 152:18] - assign exu_io_dec_exu_decode_exu_i0_ap_beq = dec_io_dec_exu_decode_exu_i0_ap_beq; // @[quasar.scala 152:18] - assign exu_io_dec_exu_decode_exu_i0_ap_bne = dec_io_dec_exu_decode_exu_i0_ap_bne; // @[quasar.scala 152:18] - assign exu_io_dec_exu_decode_exu_i0_ap_blt = dec_io_dec_exu_decode_exu_i0_ap_blt; // @[quasar.scala 152:18] - assign exu_io_dec_exu_decode_exu_i0_ap_bge = dec_io_dec_exu_decode_exu_i0_ap_bge; // @[quasar.scala 152:18] - assign exu_io_dec_exu_decode_exu_i0_ap_add = dec_io_dec_exu_decode_exu_i0_ap_add; // @[quasar.scala 152:18] - assign exu_io_dec_exu_decode_exu_i0_ap_sub = dec_io_dec_exu_decode_exu_i0_ap_sub; // @[quasar.scala 152:18] - assign exu_io_dec_exu_decode_exu_i0_ap_slt = dec_io_dec_exu_decode_exu_i0_ap_slt; // @[quasar.scala 152:18] - assign exu_io_dec_exu_decode_exu_i0_ap_unsign = dec_io_dec_exu_decode_exu_i0_ap_unsign; // @[quasar.scala 152:18] - assign exu_io_dec_exu_decode_exu_i0_ap_jal = dec_io_dec_exu_decode_exu_i0_ap_jal; // @[quasar.scala 152:18] - assign exu_io_dec_exu_decode_exu_i0_ap_predict_t = dec_io_dec_exu_decode_exu_i0_ap_predict_t; // @[quasar.scala 152:18] - assign exu_io_dec_exu_decode_exu_i0_ap_predict_nt = dec_io_dec_exu_decode_exu_i0_ap_predict_nt; // @[quasar.scala 152:18] - assign exu_io_dec_exu_decode_exu_i0_ap_csr_write = dec_io_dec_exu_decode_exu_i0_ap_csr_write; // @[quasar.scala 152:18] - assign exu_io_dec_exu_decode_exu_i0_ap_csr_imm = dec_io_dec_exu_decode_exu_i0_ap_csr_imm; // @[quasar.scala 152:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid; // @[quasar.scala 152:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4 = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[quasar.scala 152:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist; // @[quasar.scala 152:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[quasar.scala 152:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[quasar.scala 152:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[quasar.scala 152:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett; // @[quasar.scala 152:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[quasar.scala 152:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret; // @[quasar.scala 152:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja; // @[quasar.scala 152:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way; // @[quasar.scala 152:18] - assign exu_io_dec_exu_decode_exu_i0_predict_fghr_d = dec_io_dec_exu_decode_exu_i0_predict_fghr_d; // @[quasar.scala 152:18] - assign exu_io_dec_exu_decode_exu_i0_predict_index_d = dec_io_dec_exu_decode_exu_i0_predict_index_d; // @[quasar.scala 152:18] - assign exu_io_dec_exu_decode_exu_i0_predict_btag_d = dec_io_dec_exu_decode_exu_i0_predict_btag_d; // @[quasar.scala 152:18] - assign exu_io_dec_exu_decode_exu_dec_i0_rs1_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[quasar.scala 152:18] - assign exu_io_dec_exu_decode_exu_dec_i0_rs2_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[quasar.scala 152:18] - assign exu_io_dec_exu_decode_exu_dec_i0_immed_d = dec_io_dec_exu_decode_exu_dec_i0_immed_d; // @[quasar.scala 152:18] - assign exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_data_d = dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_data_d; // @[quasar.scala 152:18] - assign exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_data_d = dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_data_d; // @[quasar.scala 152:18] - assign exu_io_dec_exu_decode_exu_dec_i0_select_pc_d = dec_io_dec_exu_decode_exu_dec_i0_select_pc_d; // @[quasar.scala 152:18] - assign exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d; // @[quasar.scala 152:18] - assign exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d; // @[quasar.scala 152:18] - assign exu_io_dec_exu_decode_exu_mul_p_valid = dec_io_dec_exu_decode_exu_mul_p_valid; // @[quasar.scala 152:18] - assign exu_io_dec_exu_decode_exu_mul_p_bits_rs1_sign = dec_io_dec_exu_decode_exu_mul_p_bits_rs1_sign; // @[quasar.scala 152:18] - assign exu_io_dec_exu_decode_exu_mul_p_bits_rs2_sign = dec_io_dec_exu_decode_exu_mul_p_bits_rs2_sign; // @[quasar.scala 152:18] - assign exu_io_dec_exu_decode_exu_mul_p_bits_low = dec_io_dec_exu_decode_exu_mul_p_bits_low; // @[quasar.scala 152:18] - assign exu_io_dec_exu_decode_exu_pred_correct_npc_x = dec_io_dec_exu_decode_exu_pred_correct_npc_x; // @[quasar.scala 152:18] - assign exu_io_dec_exu_decode_exu_dec_extint_stall = dec_io_dec_exu_decode_exu_dec_extint_stall; // @[quasar.scala 152:18] - assign exu_io_dec_exu_tlu_exu_dec_tlu_meihap = dec_io_dec_exu_tlu_exu_dec_tlu_meihap; // @[quasar.scala 152:18] - assign exu_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r = dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 152:18] - assign exu_io_dec_exu_tlu_exu_dec_tlu_flush_path_r = dec_io_dec_exu_tlu_exu_dec_tlu_flush_path_r; // @[quasar.scala 152:18] - assign exu_io_dec_exu_ib_exu_dec_i0_pc_d = dec_io_dec_exu_ib_exu_dec_i0_pc_d; // @[quasar.scala 152:18] - assign exu_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d = dec_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[quasar.scala 152:18] - assign exu_io_dec_exu_gpr_exu_gpr_i0_rs1_d = dec_io_dec_exu_gpr_exu_gpr_i0_rs1_d; // @[quasar.scala 152:18] - assign exu_io_dec_exu_gpr_exu_gpr_i0_rs2_d = dec_io_dec_exu_gpr_exu_gpr_i0_rs2_d; // @[quasar.scala 152:18] - assign exu_io_dbg_cmd_wrdata = dbg_io_dbg_dec_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 155:25] + assign exu_reset = io_core_rst_l; // @[quasar.scala 155:13] + assign exu_io_scan_mode = io_scan_mode; // @[quasar.scala 156:20] + assign exu_io_dec_exu_dec_alu_dec_i0_alu_decode_d = dec_io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[quasar.scala 154:18] + assign exu_io_dec_exu_dec_alu_dec_csr_ren_d = dec_io_dec_exu_dec_alu_dec_csr_ren_d; // @[quasar.scala 154:18] + assign exu_io_dec_exu_dec_alu_dec_i0_br_immed_d = dec_io_dec_exu_dec_alu_dec_i0_br_immed_d; // @[quasar.scala 154:18] + assign exu_io_dec_exu_dec_div_div_p_valid = dec_io_dec_exu_dec_div_div_p_valid; // @[quasar.scala 154:18] + assign exu_io_dec_exu_dec_div_div_p_bits_unsign = dec_io_dec_exu_dec_div_div_p_bits_unsign; // @[quasar.scala 154:18] + assign exu_io_dec_exu_dec_div_div_p_bits_rem = dec_io_dec_exu_dec_div_div_p_bits_rem; // @[quasar.scala 154:18] + assign exu_io_dec_exu_dec_div_dec_div_cancel = dec_io_dec_exu_dec_div_dec_div_cancel; // @[quasar.scala 154:18] + assign exu_io_dec_exu_decode_exu_dec_data_en = dec_io_dec_exu_decode_exu_dec_data_en; // @[quasar.scala 154:18] + assign exu_io_dec_exu_decode_exu_dec_ctl_en = dec_io_dec_exu_decode_exu_dec_ctl_en; // @[quasar.scala 154:18] + assign exu_io_dec_exu_decode_exu_i0_ap_land = dec_io_dec_exu_decode_exu_i0_ap_land; // @[quasar.scala 154:18] + assign exu_io_dec_exu_decode_exu_i0_ap_lor = dec_io_dec_exu_decode_exu_i0_ap_lor; // @[quasar.scala 154:18] + assign exu_io_dec_exu_decode_exu_i0_ap_lxor = dec_io_dec_exu_decode_exu_i0_ap_lxor; // @[quasar.scala 154:18] + assign exu_io_dec_exu_decode_exu_i0_ap_sll = dec_io_dec_exu_decode_exu_i0_ap_sll; // @[quasar.scala 154:18] + assign exu_io_dec_exu_decode_exu_i0_ap_srl = dec_io_dec_exu_decode_exu_i0_ap_srl; // @[quasar.scala 154:18] + assign exu_io_dec_exu_decode_exu_i0_ap_sra = dec_io_dec_exu_decode_exu_i0_ap_sra; // @[quasar.scala 154:18] + assign exu_io_dec_exu_decode_exu_i0_ap_beq = dec_io_dec_exu_decode_exu_i0_ap_beq; // @[quasar.scala 154:18] + assign exu_io_dec_exu_decode_exu_i0_ap_bne = dec_io_dec_exu_decode_exu_i0_ap_bne; // @[quasar.scala 154:18] + assign exu_io_dec_exu_decode_exu_i0_ap_blt = dec_io_dec_exu_decode_exu_i0_ap_blt; // @[quasar.scala 154:18] + assign exu_io_dec_exu_decode_exu_i0_ap_bge = dec_io_dec_exu_decode_exu_i0_ap_bge; // @[quasar.scala 154:18] + assign exu_io_dec_exu_decode_exu_i0_ap_add = dec_io_dec_exu_decode_exu_i0_ap_add; // @[quasar.scala 154:18] + assign exu_io_dec_exu_decode_exu_i0_ap_sub = dec_io_dec_exu_decode_exu_i0_ap_sub; // @[quasar.scala 154:18] + assign exu_io_dec_exu_decode_exu_i0_ap_slt = dec_io_dec_exu_decode_exu_i0_ap_slt; // @[quasar.scala 154:18] + assign exu_io_dec_exu_decode_exu_i0_ap_unsign = dec_io_dec_exu_decode_exu_i0_ap_unsign; // @[quasar.scala 154:18] + assign exu_io_dec_exu_decode_exu_i0_ap_jal = dec_io_dec_exu_decode_exu_i0_ap_jal; // @[quasar.scala 154:18] + assign exu_io_dec_exu_decode_exu_i0_ap_predict_t = dec_io_dec_exu_decode_exu_i0_ap_predict_t; // @[quasar.scala 154:18] + assign exu_io_dec_exu_decode_exu_i0_ap_predict_nt = dec_io_dec_exu_decode_exu_i0_ap_predict_nt; // @[quasar.scala 154:18] + assign exu_io_dec_exu_decode_exu_i0_ap_csr_write = dec_io_dec_exu_decode_exu_i0_ap_csr_write; // @[quasar.scala 154:18] + assign exu_io_dec_exu_decode_exu_i0_ap_csr_imm = dec_io_dec_exu_decode_exu_i0_ap_csr_imm; // @[quasar.scala 154:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid; // @[quasar.scala 154:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4 = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[quasar.scala 154:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist; // @[quasar.scala 154:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[quasar.scala 154:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[quasar.scala 154:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[quasar.scala 154:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett; // @[quasar.scala 154:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[quasar.scala 154:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret; // @[quasar.scala 154:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja; // @[quasar.scala 154:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way; // @[quasar.scala 154:18] + assign exu_io_dec_exu_decode_exu_i0_predict_fghr_d = dec_io_dec_exu_decode_exu_i0_predict_fghr_d; // @[quasar.scala 154:18] + assign exu_io_dec_exu_decode_exu_i0_predict_index_d = dec_io_dec_exu_decode_exu_i0_predict_index_d; // @[quasar.scala 154:18] + assign exu_io_dec_exu_decode_exu_i0_predict_btag_d = dec_io_dec_exu_decode_exu_i0_predict_btag_d; // @[quasar.scala 154:18] + assign exu_io_dec_exu_decode_exu_dec_i0_rs1_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[quasar.scala 154:18] + assign exu_io_dec_exu_decode_exu_dec_i0_rs2_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[quasar.scala 154:18] + assign exu_io_dec_exu_decode_exu_dec_i0_immed_d = dec_io_dec_exu_decode_exu_dec_i0_immed_d; // @[quasar.scala 154:18] + assign exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_data_d = dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_data_d; // @[quasar.scala 154:18] + assign exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_data_d = dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_data_d; // @[quasar.scala 154:18] + assign exu_io_dec_exu_decode_exu_dec_i0_select_pc_d = dec_io_dec_exu_decode_exu_dec_i0_select_pc_d; // @[quasar.scala 154:18] + assign exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d; // @[quasar.scala 154:18] + assign exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d; // @[quasar.scala 154:18] + assign exu_io_dec_exu_decode_exu_mul_p_valid = dec_io_dec_exu_decode_exu_mul_p_valid; // @[quasar.scala 154:18] + assign exu_io_dec_exu_decode_exu_mul_p_bits_rs1_sign = dec_io_dec_exu_decode_exu_mul_p_bits_rs1_sign; // @[quasar.scala 154:18] + assign exu_io_dec_exu_decode_exu_mul_p_bits_rs2_sign = dec_io_dec_exu_decode_exu_mul_p_bits_rs2_sign; // @[quasar.scala 154:18] + assign exu_io_dec_exu_decode_exu_mul_p_bits_low = dec_io_dec_exu_decode_exu_mul_p_bits_low; // @[quasar.scala 154:18] + assign exu_io_dec_exu_decode_exu_pred_correct_npc_x = dec_io_dec_exu_decode_exu_pred_correct_npc_x; // @[quasar.scala 154:18] + assign exu_io_dec_exu_decode_exu_dec_extint_stall = dec_io_dec_exu_decode_exu_dec_extint_stall; // @[quasar.scala 154:18] + assign exu_io_dec_exu_tlu_exu_dec_tlu_meihap = dec_io_dec_exu_tlu_exu_dec_tlu_meihap; // @[quasar.scala 154:18] + assign exu_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r = dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 154:18] + assign exu_io_dec_exu_tlu_exu_dec_tlu_flush_path_r = dec_io_dec_exu_tlu_exu_dec_tlu_flush_path_r; // @[quasar.scala 154:18] + assign exu_io_dec_exu_ib_exu_dec_i0_pc_d = dec_io_dec_exu_ib_exu_dec_i0_pc_d; // @[quasar.scala 154:18] + assign exu_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d = dec_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[quasar.scala 154:18] + assign exu_io_dec_exu_gpr_exu_gpr_i0_rs1_d = dec_io_dec_exu_gpr_exu_gpr_i0_rs1_d; // @[quasar.scala 154:18] + assign exu_io_dec_exu_gpr_exu_gpr_i0_rs2_d = dec_io_dec_exu_gpr_exu_gpr_i0_rs2_d; // @[quasar.scala 154:18] + assign exu_io_dbg_cmd_wrdata = dbg_io_dbg_dec_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 157:25] assign lsu_clock = clock; - assign lsu_reset = io_core_rst_l; // @[quasar.scala 158:13] - assign lsu_io_clk_override = dec_io_dec_tlu_lsu_clk_override; // @[quasar.scala 159:23] - assign lsu_io_lsu_dma_dma_lsc_ctl_dma_dccm_req = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[quasar.scala 172:18] - assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_addr = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[quasar.scala 172:18] - assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_sz = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[quasar.scala 172:18] - assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_write = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[quasar.scala 172:18] - assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[quasar.scala 172:18] - assign lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_addr = dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_addr; // @[quasar.scala 172:18] - assign lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata = dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata; // @[quasar.scala 172:18] - assign lsu_io_lsu_dma_dma_mem_tag = dma_ctrl_io_lsu_dma_dma_mem_tag; // @[quasar.scala 172:18] - assign lsu_io_lsu_pic_picm_rd_data = pic_ctrl_inst_io_lsu_pic_picm_rd_data; // @[quasar.scala 217:28] - assign lsu_io_lsu_exu_exu_lsu_rs1_d = exu_io_lsu_exu_exu_lsu_rs1_d; // @[quasar.scala 164:18] - assign lsu_io_lsu_exu_exu_lsu_rs2_d = exu_io_lsu_exu_exu_lsu_rs2_d; // @[quasar.scala 164:18] - assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 123:18] - assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 123:18] - assign lsu_io_dccm_rd_data_lo = io_dccm_rd_data_lo; // @[quasar.scala 238:11] - assign lsu_io_dccm_rd_data_hi = io_dccm_rd_data_hi; // @[quasar.scala 238:11] - assign lsu_io_axi_aw_ready = axi4_to_ahb_2_io_axi_aw_ready; // @[quasar.scala 250:28] - assign lsu_io_axi_w_ready = axi4_to_ahb_2_io_axi_w_ready; // @[quasar.scala 250:28] - assign lsu_io_axi_b_valid = axi4_to_ahb_2_io_axi_b_valid; // @[quasar.scala 250:28] - assign lsu_io_axi_b_bits_id = {{2'd0}, axi4_to_ahb_2_io_axi_b_bits_id}; // @[quasar.scala 250:28] - assign lsu_io_axi_ar_ready = axi4_to_ahb_2_io_axi_ar_ready; // @[quasar.scala 250:28] - assign lsu_io_axi_r_valid = axi4_to_ahb_2_io_axi_r_valid; // @[quasar.scala 250:28] - assign lsu_io_axi_r_bits_id = {{2'd0}, axi4_to_ahb_2_io_axi_r_bits_id}; // @[quasar.scala 250:28] - assign lsu_io_axi_r_bits_data = axi4_to_ahb_2_io_axi_r_bits_data; // @[quasar.scala 250:28] - assign lsu_io_axi_r_bits_resp = axi4_to_ahb_2_io_axi_r_bits_resp; // @[quasar.scala 250:28] - assign lsu_io_dec_tlu_flush_lower_r = dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 160:32] - assign lsu_io_dec_tlu_i0_kill_writeb_r = dec_io_dec_tlu_i0_kill_writeb_r; // @[quasar.scala 161:35] - assign lsu_io_dec_tlu_force_halt = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 162:29] - assign lsu_io_dec_tlu_core_ecc_disable = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 163:35] - assign lsu_io_dec_lsu_offset_d = dec_io_dec_lsu_offset_d; // @[quasar.scala 165:27] - assign lsu_io_lsu_p_valid = dec_io_lsu_p_valid; // @[quasar.scala 166:16] - assign lsu_io_lsu_p_bits_fast_int = dec_io_lsu_p_bits_fast_int; // @[quasar.scala 166:16] - assign lsu_io_lsu_p_bits_by = dec_io_lsu_p_bits_by; // @[quasar.scala 166:16] - assign lsu_io_lsu_p_bits_half = dec_io_lsu_p_bits_half; // @[quasar.scala 166:16] - assign lsu_io_lsu_p_bits_word = dec_io_lsu_p_bits_word; // @[quasar.scala 166:16] - assign lsu_io_lsu_p_bits_load = dec_io_lsu_p_bits_load; // @[quasar.scala 166:16] - assign lsu_io_lsu_p_bits_store = dec_io_lsu_p_bits_store; // @[quasar.scala 166:16] - assign lsu_io_lsu_p_bits_unsign = dec_io_lsu_p_bits_unsign; // @[quasar.scala 166:16] - assign lsu_io_lsu_p_bits_store_data_bypass_d = dec_io_lsu_p_bits_store_data_bypass_d; // @[quasar.scala 166:16] - assign lsu_io_lsu_p_bits_load_ldst_bypass_d = dec_io_lsu_p_bits_load_ldst_bypass_d; // @[quasar.scala 166:16] - assign lsu_io_trigger_pkt_any_0_select = dec_io_trigger_pkt_any_0_select; // @[quasar.scala 169:26] - assign lsu_io_trigger_pkt_any_0_match_pkt = dec_io_trigger_pkt_any_0_match_pkt; // @[quasar.scala 169:26] - assign lsu_io_trigger_pkt_any_0_store = dec_io_trigger_pkt_any_0_store; // @[quasar.scala 169:26] - assign lsu_io_trigger_pkt_any_0_load = dec_io_trigger_pkt_any_0_load; // @[quasar.scala 169:26] - assign lsu_io_trigger_pkt_any_0_tdata2 = dec_io_trigger_pkt_any_0_tdata2; // @[quasar.scala 169:26] - assign lsu_io_trigger_pkt_any_1_select = dec_io_trigger_pkt_any_1_select; // @[quasar.scala 169:26] - assign lsu_io_trigger_pkt_any_1_match_pkt = dec_io_trigger_pkt_any_1_match_pkt; // @[quasar.scala 169:26] - assign lsu_io_trigger_pkt_any_1_store = dec_io_trigger_pkt_any_1_store; // @[quasar.scala 169:26] - assign lsu_io_trigger_pkt_any_1_load = dec_io_trigger_pkt_any_1_load; // @[quasar.scala 169:26] - assign lsu_io_trigger_pkt_any_1_tdata2 = dec_io_trigger_pkt_any_1_tdata2; // @[quasar.scala 169:26] - assign lsu_io_trigger_pkt_any_2_select = dec_io_trigger_pkt_any_2_select; // @[quasar.scala 169:26] - assign lsu_io_trigger_pkt_any_2_match_pkt = dec_io_trigger_pkt_any_2_match_pkt; // @[quasar.scala 169:26] - assign lsu_io_trigger_pkt_any_2_store = dec_io_trigger_pkt_any_2_store; // @[quasar.scala 169:26] - assign lsu_io_trigger_pkt_any_2_load = dec_io_trigger_pkt_any_2_load; // @[quasar.scala 169:26] - assign lsu_io_trigger_pkt_any_2_tdata2 = dec_io_trigger_pkt_any_2_tdata2; // @[quasar.scala 169:26] - assign lsu_io_trigger_pkt_any_3_select = dec_io_trigger_pkt_any_3_select; // @[quasar.scala 169:26] - assign lsu_io_trigger_pkt_any_3_match_pkt = dec_io_trigger_pkt_any_3_match_pkt; // @[quasar.scala 169:26] - assign lsu_io_trigger_pkt_any_3_store = dec_io_trigger_pkt_any_3_store; // @[quasar.scala 169:26] - assign lsu_io_trigger_pkt_any_3_load = dec_io_trigger_pkt_any_3_load; // @[quasar.scala 169:26] - assign lsu_io_trigger_pkt_any_3_tdata2 = dec_io_trigger_pkt_any_3_tdata2; // @[quasar.scala 169:26] - assign lsu_io_dec_lsu_valid_raw_d = dec_io_dec_lsu_valid_raw_d; // @[quasar.scala 167:30] - assign lsu_io_dec_tlu_mrac_ff = dec_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 168:26] - assign lsu_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[quasar.scala 171:25] - assign lsu_io_scan_mode = io_scan_mode; // @[quasar.scala 173:20] - assign lsu_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 174:19] + assign lsu_reset = io_core_rst_l; // @[quasar.scala 160:13] + assign lsu_io_clk_override = dec_io_dec_tlu_lsu_clk_override; // @[quasar.scala 161:23] + assign lsu_io_lsu_dma_dma_lsc_ctl_dma_dccm_req = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[quasar.scala 174:18] + assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_addr = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[quasar.scala 174:18] + assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_sz = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[quasar.scala 174:18] + assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_write = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[quasar.scala 174:18] + assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[quasar.scala 174:18] + assign lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_addr = dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_addr; // @[quasar.scala 174:18] + assign lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata = dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata; // @[quasar.scala 174:18] + assign lsu_io_lsu_dma_dma_mem_tag = dma_ctrl_io_lsu_dma_dma_mem_tag; // @[quasar.scala 174:18] + assign lsu_io_lsu_pic_picm_rd_data = pic_ctrl_inst_io_lsu_pic_picm_rd_data; // @[quasar.scala 219:28] + assign lsu_io_lsu_exu_exu_lsu_rs1_d = exu_io_lsu_exu_exu_lsu_rs1_d; // @[quasar.scala 166:18] + assign lsu_io_lsu_exu_exu_lsu_rs2_d = exu_io_lsu_exu_exu_lsu_rs2_d; // @[quasar.scala 166:18] + assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 125:18] + assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 125:18] + assign lsu_io_dccm_rd_data_lo = io_dccm_rd_data_lo; // @[quasar.scala 242:11] + assign lsu_io_dccm_rd_data_hi = io_dccm_rd_data_hi; // @[quasar.scala 242:11] + assign lsu_io_axi_aw_ready = axi4_to_ahb_2_io_axi_aw_ready; // @[quasar.scala 253:28] + assign lsu_io_axi_w_ready = axi4_to_ahb_2_io_axi_w_ready; // @[quasar.scala 253:28] + assign lsu_io_axi_b_valid = axi4_to_ahb_2_io_axi_b_valid; // @[quasar.scala 253:28] + assign lsu_io_axi_b_bits_id = axi4_to_ahb_2_io_axi_b_bits_id; // @[quasar.scala 253:28] + assign lsu_io_axi_ar_ready = axi4_to_ahb_2_io_axi_ar_ready; // @[quasar.scala 253:28] + assign lsu_io_axi_r_valid = axi4_to_ahb_2_io_axi_r_valid; // @[quasar.scala 253:28] + assign lsu_io_axi_r_bits_id = axi4_to_ahb_2_io_axi_r_bits_id; // @[quasar.scala 253:28] + assign lsu_io_axi_r_bits_data = axi4_to_ahb_2_io_axi_r_bits_data; // @[quasar.scala 253:28] + assign lsu_io_axi_r_bits_resp = axi4_to_ahb_2_io_axi_r_bits_resp; // @[quasar.scala 253:28] + assign lsu_io_dec_tlu_flush_lower_r = dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 162:32] + assign lsu_io_dec_tlu_i0_kill_writeb_r = dec_io_dec_tlu_i0_kill_writeb_r; // @[quasar.scala 163:35] + assign lsu_io_dec_tlu_force_halt = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 164:29] + assign lsu_io_dec_tlu_core_ecc_disable = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 165:35] + assign lsu_io_dec_lsu_offset_d = dec_io_dec_lsu_offset_d; // @[quasar.scala 167:27] + assign lsu_io_lsu_p_valid = dec_io_lsu_p_valid; // @[quasar.scala 168:16] + assign lsu_io_lsu_p_bits_fast_int = dec_io_lsu_p_bits_fast_int; // @[quasar.scala 168:16] + assign lsu_io_lsu_p_bits_by = dec_io_lsu_p_bits_by; // @[quasar.scala 168:16] + assign lsu_io_lsu_p_bits_half = dec_io_lsu_p_bits_half; // @[quasar.scala 168:16] + assign lsu_io_lsu_p_bits_word = dec_io_lsu_p_bits_word; // @[quasar.scala 168:16] + assign lsu_io_lsu_p_bits_load = dec_io_lsu_p_bits_load; // @[quasar.scala 168:16] + assign lsu_io_lsu_p_bits_store = dec_io_lsu_p_bits_store; // @[quasar.scala 168:16] + assign lsu_io_lsu_p_bits_unsign = dec_io_lsu_p_bits_unsign; // @[quasar.scala 168:16] + assign lsu_io_lsu_p_bits_store_data_bypass_d = dec_io_lsu_p_bits_store_data_bypass_d; // @[quasar.scala 168:16] + assign lsu_io_lsu_p_bits_load_ldst_bypass_d = dec_io_lsu_p_bits_load_ldst_bypass_d; // @[quasar.scala 168:16] + assign lsu_io_trigger_pkt_any_0_select = dec_io_trigger_pkt_any_0_select; // @[quasar.scala 171:26] + assign lsu_io_trigger_pkt_any_0_match_pkt = dec_io_trigger_pkt_any_0_match_pkt; // @[quasar.scala 171:26] + assign lsu_io_trigger_pkt_any_0_store = dec_io_trigger_pkt_any_0_store; // @[quasar.scala 171:26] + assign lsu_io_trigger_pkt_any_0_load = dec_io_trigger_pkt_any_0_load; // @[quasar.scala 171:26] + assign lsu_io_trigger_pkt_any_0_tdata2 = dec_io_trigger_pkt_any_0_tdata2; // @[quasar.scala 171:26] + assign lsu_io_trigger_pkt_any_1_select = dec_io_trigger_pkt_any_1_select; // @[quasar.scala 171:26] + assign lsu_io_trigger_pkt_any_1_match_pkt = dec_io_trigger_pkt_any_1_match_pkt; // @[quasar.scala 171:26] + assign lsu_io_trigger_pkt_any_1_store = dec_io_trigger_pkt_any_1_store; // @[quasar.scala 171:26] + assign lsu_io_trigger_pkt_any_1_load = dec_io_trigger_pkt_any_1_load; // @[quasar.scala 171:26] + assign lsu_io_trigger_pkt_any_1_tdata2 = dec_io_trigger_pkt_any_1_tdata2; // @[quasar.scala 171:26] + assign lsu_io_trigger_pkt_any_2_select = dec_io_trigger_pkt_any_2_select; // @[quasar.scala 171:26] + assign lsu_io_trigger_pkt_any_2_match_pkt = dec_io_trigger_pkt_any_2_match_pkt; // @[quasar.scala 171:26] + assign lsu_io_trigger_pkt_any_2_store = dec_io_trigger_pkt_any_2_store; // @[quasar.scala 171:26] + assign lsu_io_trigger_pkt_any_2_load = dec_io_trigger_pkt_any_2_load; // @[quasar.scala 171:26] + assign lsu_io_trigger_pkt_any_2_tdata2 = dec_io_trigger_pkt_any_2_tdata2; // @[quasar.scala 171:26] + assign lsu_io_trigger_pkt_any_3_select = dec_io_trigger_pkt_any_3_select; // @[quasar.scala 171:26] + assign lsu_io_trigger_pkt_any_3_match_pkt = dec_io_trigger_pkt_any_3_match_pkt; // @[quasar.scala 171:26] + assign lsu_io_trigger_pkt_any_3_store = dec_io_trigger_pkt_any_3_store; // @[quasar.scala 171:26] + assign lsu_io_trigger_pkt_any_3_load = dec_io_trigger_pkt_any_3_load; // @[quasar.scala 171:26] + assign lsu_io_trigger_pkt_any_3_tdata2 = dec_io_trigger_pkt_any_3_tdata2; // @[quasar.scala 171:26] + assign lsu_io_dec_lsu_valid_raw_d = dec_io_dec_lsu_valid_raw_d; // @[quasar.scala 169:30] + assign lsu_io_dec_tlu_mrac_ff = dec_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 170:26] + assign lsu_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[quasar.scala 173:25] + assign lsu_io_scan_mode = io_scan_mode; // @[quasar.scala 175:20] + assign lsu_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 176:19] assign pic_ctrl_inst_clock = clock; - assign pic_ctrl_inst_reset = io_core_rst_l; // @[quasar.scala 212:23] - assign pic_ctrl_inst_io_scan_mode = io_scan_mode; // @[quasar.scala 211:30] - assign pic_ctrl_inst_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 213:29] - assign pic_ctrl_inst_io_active_clk = rvclkhdr_1_io_l1clk; // @[quasar.scala 214:31] - assign pic_ctrl_inst_io_clk_override = dec_io_dec_tlu_pic_clk_override; // @[quasar.scala 215:33] - assign pic_ctrl_inst_io_extintsrc_req = {{1'd0}, io_extintsrc_req}; // @[quasar.scala 216:34] - assign pic_ctrl_inst_io_lsu_pic_picm_wren = lsu_io_lsu_pic_picm_wren; // @[quasar.scala 217:28] - assign pic_ctrl_inst_io_lsu_pic_picm_rden = lsu_io_lsu_pic_picm_rden; // @[quasar.scala 217:28] - assign pic_ctrl_inst_io_lsu_pic_picm_mken = lsu_io_lsu_pic_picm_mken; // @[quasar.scala 217:28] - assign pic_ctrl_inst_io_lsu_pic_picm_rdaddr = lsu_io_lsu_pic_picm_rdaddr; // @[quasar.scala 217:28] - assign pic_ctrl_inst_io_lsu_pic_picm_wraddr = lsu_io_lsu_pic_picm_wraddr; // @[quasar.scala 217:28] - assign pic_ctrl_inst_io_lsu_pic_picm_wr_data = lsu_io_lsu_pic_picm_wr_data; // @[quasar.scala 217:28] - assign pic_ctrl_inst_io_dec_pic_dec_tlu_meicurpl = dec_io_dec_pic_dec_tlu_meicurpl; // @[quasar.scala 218:28] - assign pic_ctrl_inst_io_dec_pic_dec_tlu_meipt = dec_io_dec_pic_dec_tlu_meipt; // @[quasar.scala 218:28] + assign pic_ctrl_inst_reset = io_core_rst_l; // @[quasar.scala 214:23] + assign pic_ctrl_inst_io_scan_mode = io_scan_mode; // @[quasar.scala 213:30] + assign pic_ctrl_inst_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 215:29] + assign pic_ctrl_inst_io_active_clk = rvclkhdr_1_io_l1clk; // @[quasar.scala 216:31] + assign pic_ctrl_inst_io_clk_override = dec_io_dec_tlu_pic_clk_override; // @[quasar.scala 217:33] + assign pic_ctrl_inst_io_extintsrc_req = {{1'd0}, io_extintsrc_req}; // @[quasar.scala 218:34] + assign pic_ctrl_inst_io_lsu_pic_picm_wren = lsu_io_lsu_pic_picm_wren; // @[quasar.scala 219:28] + assign pic_ctrl_inst_io_lsu_pic_picm_rden = lsu_io_lsu_pic_picm_rden; // @[quasar.scala 219:28] + assign pic_ctrl_inst_io_lsu_pic_picm_mken = lsu_io_lsu_pic_picm_mken; // @[quasar.scala 219:28] + assign pic_ctrl_inst_io_lsu_pic_picm_rdaddr = lsu_io_lsu_pic_picm_rdaddr; // @[quasar.scala 219:28] + assign pic_ctrl_inst_io_lsu_pic_picm_wraddr = lsu_io_lsu_pic_picm_wraddr; // @[quasar.scala 219:28] + assign pic_ctrl_inst_io_lsu_pic_picm_wr_data = lsu_io_lsu_pic_picm_wr_data; // @[quasar.scala 219:28] + assign pic_ctrl_inst_io_dec_pic_dec_tlu_meicurpl = dec_io_dec_pic_dec_tlu_meicurpl; // @[quasar.scala 220:28] + assign pic_ctrl_inst_io_dec_pic_dec_tlu_meipt = dec_io_dec_pic_dec_tlu_meipt; // @[quasar.scala 220:28] assign dma_ctrl_clock = clock; - assign dma_ctrl_reset = io_core_rst_l; // @[quasar.scala 196:18] - assign dma_ctrl_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 197:24] - assign dma_ctrl_io_dma_bus_clk_en = io_dma_bus_clk_en; // @[quasar.scala 198:30] - assign dma_ctrl_io_clk_override = dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 199:28] - assign dma_ctrl_io_scan_mode = io_scan_mode; // @[quasar.scala 200:25] - assign dma_ctrl_io_dbg_cmd_size = dbg_io_dbg_cmd_size; // @[quasar.scala 203:28] - assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_valid = dbg_io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[quasar.scala 201:23] - assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_write = dbg_io_dbg_dma_dbg_ib_dbg_cmd_write; // @[quasar.scala 201:23] - assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_type = dbg_io_dbg_dma_dbg_ib_dbg_cmd_type; // @[quasar.scala 201:23] - assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_addr = dbg_io_dbg_dma_dbg_ib_dbg_cmd_addr; // @[quasar.scala 201:23] - assign dma_ctrl_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata = dbg_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 201:23] - assign dma_ctrl_io_dbg_dma_io_dbg_dma_bubble = dbg_io_dbg_dma_io_dbg_dma_bubble; // @[quasar.scala 202:26] - assign dma_ctrl_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty = dec_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty; // @[quasar.scala 126:18] - assign dma_ctrl_io_iccm_dma_rvalid = ifu_io_iccm_dma_rvalid; // @[quasar.scala 204:31] - assign dma_ctrl_io_iccm_dma_ecc_error = ifu_io_iccm_dma_ecc_error; // @[quasar.scala 208:34] - assign dma_ctrl_io_iccm_dma_rtag = ifu_io_iccm_dma_rtag; // @[quasar.scala 205:29] - assign dma_ctrl_io_iccm_dma_rdata = ifu_io_iccm_dma_rdata; // @[quasar.scala 206:30] - assign dma_ctrl_io_iccm_ready = ifu_io_iccm_ready; // @[quasar.scala 207:26] - assign dma_ctrl_io_dma_axi_ar_valid = ahb_to_axi4_io_axi_ar_valid; // @[quasar.scala 269:28] - assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid; // @[quasar.scala 172:18] - assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[quasar.scala 172:18] - assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[quasar.scala 172:18] - assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata; // @[quasar.scala 172:18] - assign dma_ctrl_io_lsu_dma_dccm_ready = lsu_io_lsu_dma_dccm_ready; // @[quasar.scala 172:18] + assign dma_ctrl_reset = io_core_rst_l; // @[quasar.scala 198:18] + assign dma_ctrl_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 199:24] + assign dma_ctrl_io_dma_bus_clk_en = io_dma_bus_clk_en; // @[quasar.scala 200:30] + assign dma_ctrl_io_clk_override = dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 201:28] + assign dma_ctrl_io_scan_mode = io_scan_mode; // @[quasar.scala 202:25] + assign dma_ctrl_io_dbg_cmd_size = dbg_io_dbg_cmd_size; // @[quasar.scala 205:28] + assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_valid = dbg_io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[quasar.scala 203:23] + assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_write = dbg_io_dbg_dma_dbg_ib_dbg_cmd_write; // @[quasar.scala 203:23] + assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_type = dbg_io_dbg_dma_dbg_ib_dbg_cmd_type; // @[quasar.scala 203:23] + assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_addr = dbg_io_dbg_dma_dbg_ib_dbg_cmd_addr; // @[quasar.scala 203:23] + assign dma_ctrl_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata = dbg_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 203:23] + assign dma_ctrl_io_dbg_dma_io_dbg_dma_bubble = dbg_io_dbg_dma_io_dbg_dma_bubble; // @[quasar.scala 204:26] + assign dma_ctrl_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty = dec_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty; // @[quasar.scala 128:18] + assign dma_ctrl_io_iccm_dma_rvalid = ifu_io_iccm_dma_rvalid; // @[quasar.scala 206:31] + assign dma_ctrl_io_iccm_dma_ecc_error = ifu_io_iccm_dma_ecc_error; // @[quasar.scala 210:34] + assign dma_ctrl_io_iccm_dma_rtag = ifu_io_iccm_dma_rtag; // @[quasar.scala 207:29] + assign dma_ctrl_io_iccm_dma_rdata = ifu_io_iccm_dma_rdata; // @[quasar.scala 208:30] + assign dma_ctrl_io_iccm_ready = ifu_io_iccm_ready; // @[quasar.scala 209:26] + assign dma_ctrl_io_dma_axi_aw_valid = ahb_to_axi4_io_axi_aw_valid; // @[quasar.scala 272:28] + assign dma_ctrl_io_dma_axi_aw_bits_addr = ahb_to_axi4_io_axi_aw_bits_addr; // @[quasar.scala 272:28] + assign dma_ctrl_io_dma_axi_aw_bits_size = ahb_to_axi4_io_axi_aw_bits_size; // @[quasar.scala 272:28] + assign dma_ctrl_io_dma_axi_w_valid = ahb_to_axi4_io_axi_w_valid; // @[quasar.scala 272:28] + assign dma_ctrl_io_dma_axi_w_bits_data = ahb_to_axi4_io_axi_w_bits_data; // @[quasar.scala 272:28] + assign dma_ctrl_io_dma_axi_w_bits_strb = ahb_to_axi4_io_axi_w_bits_strb; // @[quasar.scala 272:28] + assign dma_ctrl_io_dma_axi_ar_valid = ahb_to_axi4_io_axi_ar_valid; // @[quasar.scala 272:28] + assign dma_ctrl_io_dma_axi_ar_bits_addr = ahb_to_axi4_io_axi_ar_bits_addr; // @[quasar.scala 272:28] + assign dma_ctrl_io_dma_axi_ar_bits_size = ahb_to_axi4_io_axi_ar_bits_size; // @[quasar.scala 272:28] + assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid; // @[quasar.scala 174:18] + assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[quasar.scala 174:18] + assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[quasar.scala 174:18] + assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata; // @[quasar.scala 174:18] + assign dma_ctrl_io_lsu_dma_dccm_ready = lsu_io_lsu_dma_dccm_ready; // @[quasar.scala 174:18] assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17] assign rvclkhdr_io_en = 1'h1; // @[lib.scala 345:16] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] @@ -82761,47 +85235,75 @@ module quasar( assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] assign axi4_to_ahb_clock = clock; assign axi4_to_ahb_reset = reset; - assign axi4_to_ahb_io_scan_mode = io_scan_mode; // @[quasar.scala 260:33] - assign axi4_to_ahb_io_bus_clk_en = io_dbg_bus_clk_en; // @[quasar.scala 261:34] - assign axi4_to_ahb_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 262:36] - assign axi4_to_ahb_io_axi_aw_valid = dbg_io_sb_axi_aw_valid; // @[quasar.scala 263:27] - assign axi4_to_ahb_io_axi_aw_bits_id = 1'h0; // @[quasar.scala 263:27] - assign axi4_to_ahb_io_axi_w_valid = dbg_io_sb_axi_w_valid; // @[quasar.scala 263:27] - assign axi4_to_ahb_io_axi_w_bits_data = dbg_io_sb_axi_w_bits_data; // @[quasar.scala 263:27] - assign axi4_to_ahb_io_axi_b_ready = 1'h1; // @[quasar.scala 263:27] - assign axi4_to_ahb_io_axi_ar_valid = dbg_io_sb_axi_ar_valid; // @[quasar.scala 263:27] - assign axi4_to_ahb_io_axi_ar_bits_id = 1'h0; // @[quasar.scala 263:27] + assign axi4_to_ahb_io_scan_mode = io_scan_mode; // @[quasar.scala 263:33] + assign axi4_to_ahb_io_bus_clk_en = io_dbg_bus_clk_en; // @[quasar.scala 264:34] + assign axi4_to_ahb_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 265:36] + assign axi4_to_ahb_io_axi_aw_valid = dbg_io_sb_axi_aw_valid; // @[quasar.scala 266:27] + assign axi4_to_ahb_io_axi_aw_bits_addr = dbg_io_sb_axi_aw_bits_addr; // @[quasar.scala 266:27] + assign axi4_to_ahb_io_axi_aw_bits_size = dbg_io_sb_axi_aw_bits_size; // @[quasar.scala 266:27] + assign axi4_to_ahb_io_axi_w_valid = dbg_io_sb_axi_w_valid; // @[quasar.scala 266:27] + assign axi4_to_ahb_io_axi_w_bits_data = dbg_io_sb_axi_w_bits_data; // @[quasar.scala 266:27] + assign axi4_to_ahb_io_axi_w_bits_strb = dbg_io_sb_axi_w_bits_strb; // @[quasar.scala 266:27] + assign axi4_to_ahb_io_axi_ar_valid = dbg_io_sb_axi_ar_valid; // @[quasar.scala 266:27] + assign axi4_to_ahb_io_axi_ar_bits_addr = dbg_io_sb_axi_ar_bits_addr; // @[quasar.scala 266:27] + assign axi4_to_ahb_io_axi_ar_bits_size = dbg_io_sb_axi_ar_bits_size; // @[quasar.scala 266:27] + assign axi4_to_ahb_io_ahb_in_hrdata = io_sb_ahb_in_hrdata; // @[quasar.scala 267:27] + assign axi4_to_ahb_io_ahb_in_hready = io_sb_ahb_in_hready; // @[quasar.scala 267:27] + assign axi4_to_ahb_io_ahb_in_hresp = io_sb_ahb_in_hresp; // @[quasar.scala 267:27] assign axi4_to_ahb_1_clock = clock; assign axi4_to_ahb_1_reset = reset; - assign axi4_to_ahb_1_io_scan_mode = io_scan_mode; // @[quasar.scala 254:34] - assign axi4_to_ahb_1_io_bus_clk_en = io_ifu_bus_clk_en; // @[quasar.scala 255:35] - assign axi4_to_ahb_1_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 256:37] - assign axi4_to_ahb_1_io_axi_aw_valid = 1'h0; // @[quasar.scala 257:28] - assign axi4_to_ahb_1_io_axi_aw_bits_id = 1'h0; // @[quasar.scala 257:28] - assign axi4_to_ahb_1_io_axi_w_valid = 1'h0; // @[quasar.scala 257:28] - assign axi4_to_ahb_1_io_axi_w_bits_data = 64'h0; // @[quasar.scala 257:28] - assign axi4_to_ahb_1_io_axi_b_ready = 1'h0; // @[quasar.scala 257:28] - assign axi4_to_ahb_1_io_axi_ar_valid = ifu_io_ifu_ar_valid; // @[quasar.scala 257:28] - assign axi4_to_ahb_1_io_axi_ar_bits_id = ifu_io_ifu_ar_bits_id[0]; // @[quasar.scala 257:28] + assign axi4_to_ahb_1_io_scan_mode = io_scan_mode; // @[quasar.scala 256:34] + assign axi4_to_ahb_1_io_bus_clk_en = io_ifu_bus_clk_en; // @[quasar.scala 257:35] + assign axi4_to_ahb_1_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 258:37] + assign axi4_to_ahb_1_io_axi_aw_valid = 1'h0; // @[quasar.scala 259:28] + assign axi4_to_ahb_1_io_axi_aw_bits_id = 3'h0; // @[quasar.scala 259:28] + assign axi4_to_ahb_1_io_axi_aw_bits_addr = 32'h0; // @[quasar.scala 259:28] + assign axi4_to_ahb_1_io_axi_aw_bits_size = 3'h0; // @[quasar.scala 259:28] + assign axi4_to_ahb_1_io_axi_w_valid = 1'h0; // @[quasar.scala 259:28] + assign axi4_to_ahb_1_io_axi_w_bits_data = 64'h0; // @[quasar.scala 259:28] + assign axi4_to_ahb_1_io_axi_w_bits_strb = 8'h0; // @[quasar.scala 259:28] + assign axi4_to_ahb_1_io_axi_ar_valid = ifu_io_ifu_ar_valid; // @[quasar.scala 259:28] + assign axi4_to_ahb_1_io_axi_ar_bits_id = ifu_io_ifu_ar_bits_id; // @[quasar.scala 259:28] + assign axi4_to_ahb_1_io_axi_ar_bits_addr = ifu_io_ifu_ar_bits_addr; // @[quasar.scala 259:28] + assign axi4_to_ahb_1_io_axi_ar_bits_size = 3'h3; // @[quasar.scala 259:28] + assign axi4_to_ahb_1_io_ahb_in_hrdata = io_ifu_ahb_in_hrdata; // @[quasar.scala 260:28] + assign axi4_to_ahb_1_io_ahb_in_hready = io_ifu_ahb_in_hready; // @[quasar.scala 260:28] + assign axi4_to_ahb_1_io_ahb_in_hresp = io_ifu_ahb_in_hresp; // @[quasar.scala 260:28] assign axi4_to_ahb_2_clock = clock; assign axi4_to_ahb_2_reset = reset; - assign axi4_to_ahb_2_io_scan_mode = io_scan_mode; // @[quasar.scala 247:34] - assign axi4_to_ahb_2_io_bus_clk_en = io_lsu_bus_clk_en; // @[quasar.scala 248:35] - assign axi4_to_ahb_2_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 249:37] - assign axi4_to_ahb_2_io_axi_aw_valid = lsu_io_axi_aw_valid; // @[quasar.scala 250:28] - assign axi4_to_ahb_2_io_axi_aw_bits_id = lsu_io_axi_aw_bits_id[0]; // @[quasar.scala 250:28] - assign axi4_to_ahb_2_io_axi_w_valid = lsu_io_axi_w_valid; // @[quasar.scala 250:28] - assign axi4_to_ahb_2_io_axi_w_bits_data = lsu_io_axi_w_bits_data; // @[quasar.scala 250:28] - assign axi4_to_ahb_2_io_axi_b_ready = 1'h1; // @[quasar.scala 250:28] - assign axi4_to_ahb_2_io_axi_ar_valid = lsu_io_axi_ar_valid; // @[quasar.scala 250:28] - assign axi4_to_ahb_2_io_axi_ar_bits_id = lsu_io_axi_ar_bits_id[0]; // @[quasar.scala 250:28] + assign axi4_to_ahb_2_io_scan_mode = io_scan_mode; // @[quasar.scala 250:34] + assign axi4_to_ahb_2_io_bus_clk_en = io_lsu_bus_clk_en; // @[quasar.scala 251:35] + assign axi4_to_ahb_2_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 252:37] + assign axi4_to_ahb_2_io_axi_aw_valid = lsu_io_axi_aw_valid; // @[quasar.scala 253:28] + assign axi4_to_ahb_2_io_axi_aw_bits_id = lsu_io_axi_aw_bits_id; // @[quasar.scala 253:28] + assign axi4_to_ahb_2_io_axi_aw_bits_addr = lsu_io_axi_aw_bits_addr; // @[quasar.scala 253:28] + assign axi4_to_ahb_2_io_axi_aw_bits_size = lsu_io_axi_aw_bits_size; // @[quasar.scala 253:28] + assign axi4_to_ahb_2_io_axi_w_valid = lsu_io_axi_w_valid; // @[quasar.scala 253:28] + assign axi4_to_ahb_2_io_axi_w_bits_data = lsu_io_axi_w_bits_data; // @[quasar.scala 253:28] + assign axi4_to_ahb_2_io_axi_w_bits_strb = lsu_io_axi_w_bits_strb; // @[quasar.scala 253:28] + assign axi4_to_ahb_2_io_axi_ar_valid = lsu_io_axi_ar_valid; // @[quasar.scala 253:28] + assign axi4_to_ahb_2_io_axi_ar_bits_id = lsu_io_axi_ar_bits_id; // @[quasar.scala 253:28] + assign axi4_to_ahb_2_io_axi_ar_bits_addr = lsu_io_axi_ar_bits_addr; // @[quasar.scala 253:28] + assign axi4_to_ahb_2_io_axi_ar_bits_size = lsu_io_axi_ar_bits_size; // @[quasar.scala 253:28] + assign axi4_to_ahb_2_io_ahb_in_hrdata = io_lsu_ahb_in_hrdata; // @[quasar.scala 254:28] + assign axi4_to_ahb_2_io_ahb_in_hready = io_lsu_ahb_in_hready; // @[quasar.scala 254:28] + assign axi4_to_ahb_2_io_ahb_in_hresp = io_lsu_ahb_in_hresp; // @[quasar.scala 254:28] assign ahb_to_axi4_clock = clock; assign ahb_to_axi4_reset = reset; - assign ahb_to_axi4_io_scan_mode = io_scan_mode; // @[quasar.scala 266:34] - assign ahb_to_axi4_io_bus_clk_en = io_dma_bus_clk_en; // @[quasar.scala 267:35] - assign ahb_to_axi4_io_axi_ar_ready = dma_ctrl_io_dma_axi_ar_ready; // @[quasar.scala 269:28] - assign ahb_to_axi4_io_axi_r_valid = dma_ctrl_io_dma_axi_r_valid; // @[quasar.scala 269:28] - assign ahb_to_axi4_io_axi_r_bits_resp = dma_ctrl_io_dma_axi_r_bits_resp; // @[quasar.scala 269:28] + assign ahb_to_axi4_io_scan_mode = io_scan_mode; // @[quasar.scala 269:34] + assign ahb_to_axi4_io_bus_clk_en = io_dma_bus_clk_en; // @[quasar.scala 270:35] + assign ahb_to_axi4_io_axi_aw_ready = dma_ctrl_io_dma_axi_aw_ready; // @[quasar.scala 272:28] + assign ahb_to_axi4_io_axi_ar_ready = dma_ctrl_io_dma_axi_ar_ready; // @[quasar.scala 272:28] + assign ahb_to_axi4_io_axi_r_valid = dma_ctrl_io_dma_axi_r_valid; // @[quasar.scala 272:28] + assign ahb_to_axi4_io_axi_r_bits_data = dma_ctrl_io_dma_axi_r_bits_data; // @[quasar.scala 272:28] + assign ahb_to_axi4_io_axi_r_bits_resp = dma_ctrl_io_dma_axi_r_bits_resp; // @[quasar.scala 272:28] + assign ahb_to_axi4_io_ahb_sig_out_haddr = io_dma_ahb_sig_out_haddr; // @[quasar.scala 273:28] + assign ahb_to_axi4_io_ahb_sig_out_hsize = io_dma_ahb_sig_out_hsize; // @[quasar.scala 273:28] + assign ahb_to_axi4_io_ahb_sig_out_htrans = io_dma_ahb_sig_out_htrans; // @[quasar.scala 273:28] + assign ahb_to_axi4_io_ahb_sig_out_hwrite = io_dma_ahb_sig_out_hwrite; // @[quasar.scala 273:28] + assign ahb_to_axi4_io_ahb_sig_out_hwdata = io_dma_ahb_sig_out_hwdata; // @[quasar.scala 273:28] + assign ahb_to_axi4_io_ahb_hsel = io_dma_ahb_hsel; // @[quasar.scala 273:28] + assign ahb_to_axi4_io_ahb_hreadyin = io_dma_ahb_hreadyin; // @[quasar.scala 273:28] endmodule module quasar_wrapper( input clock, @@ -82811,162 +85313,52 @@ module quasar_wrapper( input io_nmi_int, input [30:0] io_nmi_vec, input [30:0] io_jtag_id, - input io_lsu_brg_aw_ready, - output io_lsu_brg_aw_valid, - output [2:0] io_lsu_brg_aw_bits_id, - output [31:0] io_lsu_brg_aw_bits_addr, - output [3:0] io_lsu_brg_aw_bits_region, - output [7:0] io_lsu_brg_aw_bits_len, - output [2:0] io_lsu_brg_aw_bits_size, - output [1:0] io_lsu_brg_aw_bits_burst, - output io_lsu_brg_aw_bits_lock, - output [3:0] io_lsu_brg_aw_bits_cache, - output [2:0] io_lsu_brg_aw_bits_prot, - output [3:0] io_lsu_brg_aw_bits_qos, - input io_lsu_brg_w_ready, - output io_lsu_brg_w_valid, - output [63:0] io_lsu_brg_w_bits_data, - output [7:0] io_lsu_brg_w_bits_strb, - output io_lsu_brg_w_bits_last, - output io_lsu_brg_b_ready, - input io_lsu_brg_b_valid, - input [1:0] io_lsu_brg_b_bits_resp, - input [2:0] io_lsu_brg_b_bits_id, - input io_lsu_brg_ar_ready, - output io_lsu_brg_ar_valid, - output [2:0] io_lsu_brg_ar_bits_id, - output [31:0] io_lsu_brg_ar_bits_addr, - output [3:0] io_lsu_brg_ar_bits_region, - output [7:0] io_lsu_brg_ar_bits_len, - output [2:0] io_lsu_brg_ar_bits_size, - output [1:0] io_lsu_brg_ar_bits_burst, - output io_lsu_brg_ar_bits_lock, - output [3:0] io_lsu_brg_ar_bits_cache, - output [2:0] io_lsu_brg_ar_bits_prot, - output [3:0] io_lsu_brg_ar_bits_qos, - output io_lsu_brg_r_ready, - input io_lsu_brg_r_valid, - input [2:0] io_lsu_brg_r_bits_id, - input [63:0] io_lsu_brg_r_bits_data, - input [1:0] io_lsu_brg_r_bits_resp, - input io_lsu_brg_r_bits_last, - input io_ifu_brg_aw_ready, - output io_ifu_brg_aw_valid, - output [2:0] io_ifu_brg_aw_bits_id, - output [31:0] io_ifu_brg_aw_bits_addr, - output [3:0] io_ifu_brg_aw_bits_region, - output [7:0] io_ifu_brg_aw_bits_len, - output [2:0] io_ifu_brg_aw_bits_size, - output [1:0] io_ifu_brg_aw_bits_burst, - output io_ifu_brg_aw_bits_lock, - output [3:0] io_ifu_brg_aw_bits_cache, - output [2:0] io_ifu_brg_aw_bits_prot, - output [3:0] io_ifu_brg_aw_bits_qos, - input io_ifu_brg_w_ready, - output io_ifu_brg_w_valid, - output [63:0] io_ifu_brg_w_bits_data, - output [7:0] io_ifu_brg_w_bits_strb, - output io_ifu_brg_w_bits_last, - output io_ifu_brg_b_ready, - input io_ifu_brg_b_valid, - input [1:0] io_ifu_brg_b_bits_resp, - input [2:0] io_ifu_brg_b_bits_id, - input io_ifu_brg_ar_ready, - output io_ifu_brg_ar_valid, - output [2:0] io_ifu_brg_ar_bits_id, - output [31:0] io_ifu_brg_ar_bits_addr, - output [3:0] io_ifu_brg_ar_bits_region, - output [7:0] io_ifu_brg_ar_bits_len, - output [2:0] io_ifu_brg_ar_bits_size, - output [1:0] io_ifu_brg_ar_bits_burst, - output io_ifu_brg_ar_bits_lock, - output [3:0] io_ifu_brg_ar_bits_cache, - output [2:0] io_ifu_brg_ar_bits_prot, - output [3:0] io_ifu_brg_ar_bits_qos, - output io_ifu_brg_r_ready, - input io_ifu_brg_r_valid, - input [2:0] io_ifu_brg_r_bits_id, - input [63:0] io_ifu_brg_r_bits_data, - input [1:0] io_ifu_brg_r_bits_resp, - input io_ifu_brg_r_bits_last, - input io_sb_brg_aw_ready, - output io_sb_brg_aw_valid, - output io_sb_brg_aw_bits_id, - output [31:0] io_sb_brg_aw_bits_addr, - output [3:0] io_sb_brg_aw_bits_region, - output [7:0] io_sb_brg_aw_bits_len, - output [2:0] io_sb_brg_aw_bits_size, - output [1:0] io_sb_brg_aw_bits_burst, - output io_sb_brg_aw_bits_lock, - output [3:0] io_sb_brg_aw_bits_cache, - output [2:0] io_sb_brg_aw_bits_prot, - output [3:0] io_sb_brg_aw_bits_qos, - input io_sb_brg_w_ready, - output io_sb_brg_w_valid, - output [63:0] io_sb_brg_w_bits_data, - output [7:0] io_sb_brg_w_bits_strb, - output io_sb_brg_w_bits_last, - output io_sb_brg_b_ready, - input io_sb_brg_b_valid, - input [1:0] io_sb_brg_b_bits_resp, - input io_sb_brg_b_bits_id, - input io_sb_brg_ar_ready, - output io_sb_brg_ar_valid, - output io_sb_brg_ar_bits_id, - output [31:0] io_sb_brg_ar_bits_addr, - output [3:0] io_sb_brg_ar_bits_region, - output [7:0] io_sb_brg_ar_bits_len, - output [2:0] io_sb_brg_ar_bits_size, - output [1:0] io_sb_brg_ar_bits_burst, - output io_sb_brg_ar_bits_lock, - output [3:0] io_sb_brg_ar_bits_cache, - output [2:0] io_sb_brg_ar_bits_prot, - output [3:0] io_sb_brg_ar_bits_qos, - output io_sb_brg_r_ready, - input io_sb_brg_r_valid, - input io_sb_brg_r_bits_id, - input [63:0] io_sb_brg_r_bits_data, - input [1:0] io_sb_brg_r_bits_resp, - input io_sb_brg_r_bits_last, - output io_dma_brg_aw_ready, - input io_dma_brg_aw_valid, - input io_dma_brg_aw_bits_id, - input [31:0] io_dma_brg_aw_bits_addr, - input [3:0] io_dma_brg_aw_bits_region, - input [7:0] io_dma_brg_aw_bits_len, - input [2:0] io_dma_brg_aw_bits_size, - input [1:0] io_dma_brg_aw_bits_burst, - input io_dma_brg_aw_bits_lock, - input [3:0] io_dma_brg_aw_bits_cache, - input [2:0] io_dma_brg_aw_bits_prot, - input [3:0] io_dma_brg_aw_bits_qos, - output io_dma_brg_w_ready, - input io_dma_brg_w_valid, - input [63:0] io_dma_brg_w_bits_data, - input [7:0] io_dma_brg_w_bits_strb, - input io_dma_brg_w_bits_last, - input io_dma_brg_b_ready, - output io_dma_brg_b_valid, - output [1:0] io_dma_brg_b_bits_resp, - output io_dma_brg_b_bits_id, - output io_dma_brg_ar_ready, - input io_dma_brg_ar_valid, - input io_dma_brg_ar_bits_id, - input [31:0] io_dma_brg_ar_bits_addr, - input [3:0] io_dma_brg_ar_bits_region, - input [7:0] io_dma_brg_ar_bits_len, - input [2:0] io_dma_brg_ar_bits_size, - input [1:0] io_dma_brg_ar_bits_burst, - input io_dma_brg_ar_bits_lock, - input [3:0] io_dma_brg_ar_bits_cache, - input [2:0] io_dma_brg_ar_bits_prot, - input [3:0] io_dma_brg_ar_bits_qos, - input io_dma_brg_r_ready, - output io_dma_brg_r_valid, - output io_dma_brg_r_bits_id, - output [63:0] io_dma_brg_r_bits_data, - output [1:0] io_dma_brg_r_bits_resp, - output io_dma_brg_r_bits_last, + input [63:0] io_lsu_brg_in_hrdata, + input io_lsu_brg_in_hready, + input io_lsu_brg_in_hresp, + output [31:0] io_lsu_brg_out_haddr, + output [2:0] io_lsu_brg_out_hburst, + output io_lsu_brg_out_hmastlock, + output [3:0] io_lsu_brg_out_hprot, + output [2:0] io_lsu_brg_out_hsize, + output [1:0] io_lsu_brg_out_htrans, + output io_lsu_brg_out_hwrite, + output [63:0] io_lsu_brg_out_hwdata, + input [63:0] io_ifu_brg_in_hrdata, + input io_ifu_brg_in_hready, + input io_ifu_brg_in_hresp, + output [31:0] io_ifu_brg_out_haddr, + output [2:0] io_ifu_brg_out_hburst, + output io_ifu_brg_out_hmastlock, + output [3:0] io_ifu_brg_out_hprot, + output [2:0] io_ifu_brg_out_hsize, + output [1:0] io_ifu_brg_out_htrans, + output io_ifu_brg_out_hwrite, + output [63:0] io_ifu_brg_out_hwdata, + input [63:0] io_sb_brg_in_hrdata, + input io_sb_brg_in_hready, + input io_sb_brg_in_hresp, + output [31:0] io_sb_brg_out_haddr, + output [2:0] io_sb_brg_out_hburst, + output io_sb_brg_out_hmastlock, + output [3:0] io_sb_brg_out_hprot, + output [2:0] io_sb_brg_out_hsize, + output [1:0] io_sb_brg_out_htrans, + output io_sb_brg_out_hwrite, + output [63:0] io_sb_brg_out_hwdata, + output [63:0] io_dma_brg_sig_in_hrdata, + output io_dma_brg_sig_in_hready, + output io_dma_brg_sig_in_hresp, + input [31:0] io_dma_brg_sig_out_haddr, + input [2:0] io_dma_brg_sig_out_hburst, + input io_dma_brg_sig_out_hmastlock, + input [3:0] io_dma_brg_sig_out_hprot, + input [2:0] io_dma_brg_sig_out_hsize, + input [1:0] io_dma_brg_sig_out_htrans, + input io_dma_brg_sig_out_hwrite, + input [63:0] io_dma_brg_sig_out_hwdata, + input io_dma_brg_hsel, + input io_dma_brg_hreadyin, input io_lsu_bus_clk_en, input io_ifu_bus_clk_en, input io_dbg_bus_clk_en, @@ -83069,6 +85461,40 @@ module quasar_wrapper( wire dmi_wrapper_dmi_hard_reset; // @[quasar_wrapper.scala 64:27] wire core_clock; // @[quasar_wrapper.scala 65:20] wire core_reset; // @[quasar_wrapper.scala 65:20] + wire [63:0] core_io_lsu_ahb_in_hrdata; // @[quasar_wrapper.scala 65:20] + wire core_io_lsu_ahb_in_hready; // @[quasar_wrapper.scala 65:20] + wire core_io_lsu_ahb_in_hresp; // @[quasar_wrapper.scala 65:20] + wire [31:0] core_io_lsu_ahb_out_haddr; // @[quasar_wrapper.scala 65:20] + wire [2:0] core_io_lsu_ahb_out_hsize; // @[quasar_wrapper.scala 65:20] + wire [1:0] core_io_lsu_ahb_out_htrans; // @[quasar_wrapper.scala 65:20] + wire core_io_lsu_ahb_out_hwrite; // @[quasar_wrapper.scala 65:20] + wire [63:0] core_io_lsu_ahb_out_hwdata; // @[quasar_wrapper.scala 65:20] + wire [63:0] core_io_ifu_ahb_in_hrdata; // @[quasar_wrapper.scala 65:20] + wire core_io_ifu_ahb_in_hready; // @[quasar_wrapper.scala 65:20] + wire core_io_ifu_ahb_in_hresp; // @[quasar_wrapper.scala 65:20] + wire [31:0] core_io_ifu_ahb_out_haddr; // @[quasar_wrapper.scala 65:20] + wire [2:0] core_io_ifu_ahb_out_hsize; // @[quasar_wrapper.scala 65:20] + wire [1:0] core_io_ifu_ahb_out_htrans; // @[quasar_wrapper.scala 65:20] + wire core_io_ifu_ahb_out_hwrite; // @[quasar_wrapper.scala 65:20] + wire [63:0] core_io_ifu_ahb_out_hwdata; // @[quasar_wrapper.scala 65:20] + wire [63:0] core_io_sb_ahb_in_hrdata; // @[quasar_wrapper.scala 65:20] + wire core_io_sb_ahb_in_hready; // @[quasar_wrapper.scala 65:20] + wire core_io_sb_ahb_in_hresp; // @[quasar_wrapper.scala 65:20] + wire [31:0] core_io_sb_ahb_out_haddr; // @[quasar_wrapper.scala 65:20] + wire [2:0] core_io_sb_ahb_out_hsize; // @[quasar_wrapper.scala 65:20] + wire [1:0] core_io_sb_ahb_out_htrans; // @[quasar_wrapper.scala 65:20] + wire core_io_sb_ahb_out_hwrite; // @[quasar_wrapper.scala 65:20] + wire [63:0] core_io_sb_ahb_out_hwdata; // @[quasar_wrapper.scala 65:20] + wire [63:0] core_io_dma_ahb_sig_in_hrdata; // @[quasar_wrapper.scala 65:20] + wire core_io_dma_ahb_sig_in_hready; // @[quasar_wrapper.scala 65:20] + wire core_io_dma_ahb_sig_in_hresp; // @[quasar_wrapper.scala 65:20] + wire [31:0] core_io_dma_ahb_sig_out_haddr; // @[quasar_wrapper.scala 65:20] + wire [2:0] core_io_dma_ahb_sig_out_hsize; // @[quasar_wrapper.scala 65:20] + wire [1:0] core_io_dma_ahb_sig_out_htrans; // @[quasar_wrapper.scala 65:20] + wire core_io_dma_ahb_sig_out_hwrite; // @[quasar_wrapper.scala 65:20] + wire [63:0] core_io_dma_ahb_sig_out_hwdata; // @[quasar_wrapper.scala 65:20] + wire core_io_dma_ahb_hsel; // @[quasar_wrapper.scala 65:20] + wire core_io_dma_ahb_hreadyin; // @[quasar_wrapper.scala 65:20] wire core_io_dbg_rst_l; // @[quasar_wrapper.scala 65:20] wire [30:0] core_io_rst_vec; // @[quasar_wrapper.scala 65:20] wire core_io_nmi_int; // @[quasar_wrapper.scala 65:20] @@ -83148,6 +85574,7 @@ module quasar_wrapper( wire [6:0] core_io_dmi_reg_addr; // @[quasar_wrapper.scala 65:20] wire core_io_dmi_reg_wr_en; // @[quasar_wrapper.scala 65:20] wire [31:0] core_io_dmi_reg_wdata; // @[quasar_wrapper.scala 65:20] + wire [31:0] core_io_dmi_reg_rdata; // @[quasar_wrapper.scala 65:20] wire [30:0] core_io_extintsrc_req; // @[quasar_wrapper.scala 65:20] wire core_io_timer_int; // @[quasar_wrapper.scala 65:20] wire core_io_soft_int; // @[quasar_wrapper.scala 65:20] @@ -83220,6 +85647,40 @@ module quasar_wrapper( quasar core ( // @[quasar_wrapper.scala 65:20] .clock(core_clock), .reset(core_reset), + .io_lsu_ahb_in_hrdata(core_io_lsu_ahb_in_hrdata), + .io_lsu_ahb_in_hready(core_io_lsu_ahb_in_hready), + .io_lsu_ahb_in_hresp(core_io_lsu_ahb_in_hresp), + .io_lsu_ahb_out_haddr(core_io_lsu_ahb_out_haddr), + .io_lsu_ahb_out_hsize(core_io_lsu_ahb_out_hsize), + .io_lsu_ahb_out_htrans(core_io_lsu_ahb_out_htrans), + .io_lsu_ahb_out_hwrite(core_io_lsu_ahb_out_hwrite), + .io_lsu_ahb_out_hwdata(core_io_lsu_ahb_out_hwdata), + .io_ifu_ahb_in_hrdata(core_io_ifu_ahb_in_hrdata), + .io_ifu_ahb_in_hready(core_io_ifu_ahb_in_hready), + .io_ifu_ahb_in_hresp(core_io_ifu_ahb_in_hresp), + .io_ifu_ahb_out_haddr(core_io_ifu_ahb_out_haddr), + .io_ifu_ahb_out_hsize(core_io_ifu_ahb_out_hsize), + .io_ifu_ahb_out_htrans(core_io_ifu_ahb_out_htrans), + .io_ifu_ahb_out_hwrite(core_io_ifu_ahb_out_hwrite), + .io_ifu_ahb_out_hwdata(core_io_ifu_ahb_out_hwdata), + .io_sb_ahb_in_hrdata(core_io_sb_ahb_in_hrdata), + .io_sb_ahb_in_hready(core_io_sb_ahb_in_hready), + .io_sb_ahb_in_hresp(core_io_sb_ahb_in_hresp), + .io_sb_ahb_out_haddr(core_io_sb_ahb_out_haddr), + .io_sb_ahb_out_hsize(core_io_sb_ahb_out_hsize), + .io_sb_ahb_out_htrans(core_io_sb_ahb_out_htrans), + .io_sb_ahb_out_hwrite(core_io_sb_ahb_out_hwrite), + .io_sb_ahb_out_hwdata(core_io_sb_ahb_out_hwdata), + .io_dma_ahb_sig_in_hrdata(core_io_dma_ahb_sig_in_hrdata), + .io_dma_ahb_sig_in_hready(core_io_dma_ahb_sig_in_hready), + .io_dma_ahb_sig_in_hresp(core_io_dma_ahb_sig_in_hresp), + .io_dma_ahb_sig_out_haddr(core_io_dma_ahb_sig_out_haddr), + .io_dma_ahb_sig_out_hsize(core_io_dma_ahb_sig_out_hsize), + .io_dma_ahb_sig_out_htrans(core_io_dma_ahb_sig_out_htrans), + .io_dma_ahb_sig_out_hwrite(core_io_dma_ahb_sig_out_hwrite), + .io_dma_ahb_sig_out_hwdata(core_io_dma_ahb_sig_out_hwdata), + .io_dma_ahb_hsel(core_io_dma_ahb_hsel), + .io_dma_ahb_hreadyin(core_io_dma_ahb_hreadyin), .io_dbg_rst_l(core_io_dbg_rst_l), .io_rst_vec(core_io_rst_vec), .io_nmi_int(core_io_nmi_int), @@ -83299,106 +85760,39 @@ module quasar_wrapper( .io_dmi_reg_addr(core_io_dmi_reg_addr), .io_dmi_reg_wr_en(core_io_dmi_reg_wr_en), .io_dmi_reg_wdata(core_io_dmi_reg_wdata), + .io_dmi_reg_rdata(core_io_dmi_reg_rdata), .io_extintsrc_req(core_io_extintsrc_req), .io_timer_int(core_io_timer_int), .io_soft_int(core_io_soft_int), .io_scan_mode(core_io_scan_mode) ); - assign io_lsu_brg_aw_valid = 1'h0; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_aw_bits_id = 3'h0; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_aw_bits_addr = 32'h0; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_aw_bits_region = 4'h0; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_aw_bits_size = 3'h0; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_aw_bits_burst = 2'h0; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_aw_bits_cache = 4'h0; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_w_valid = 1'h0; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_w_bits_data = 64'h0; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_w_bits_strb = 8'h0; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_w_bits_last = 1'h0; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_b_ready = 1'h0; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_ar_valid = 1'h0; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_ar_bits_id = 3'h0; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_ar_bits_addr = 32'h0; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_ar_bits_region = 4'h0; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_ar_bits_size = 3'h0; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_ar_bits_burst = 2'h0; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_ar_bits_cache = 4'h0; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_r_ready = 1'h0; // @[quasar_wrapper.scala 104:21] - assign io_ifu_brg_aw_valid = 1'h0; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_aw_bits_id = 3'h0; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_aw_bits_addr = 32'h0; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_aw_bits_region = 4'h0; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_aw_bits_size = 3'h0; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_aw_bits_burst = 2'h0; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_aw_bits_cache = 4'h0; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_w_valid = 1'h0; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_w_bits_data = 64'h0; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_w_bits_strb = 8'h0; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_w_bits_last = 1'h0; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_b_ready = 1'h0; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_ar_valid = 1'h0; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_ar_bits_id = 3'h0; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_ar_bits_addr = 32'h0; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_ar_bits_region = 4'h0; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_ar_bits_size = 3'h0; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_ar_bits_burst = 2'h0; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_ar_bits_cache = 4'h0; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_r_ready = 1'h0; // @[quasar_wrapper.scala 105:21] - assign io_sb_brg_aw_valid = 1'h0; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_aw_bits_id = 1'h0; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_aw_bits_addr = 32'h0; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_aw_bits_region = 4'h0; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_aw_bits_size = 3'h0; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_aw_bits_burst = 2'h0; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_aw_bits_cache = 4'h0; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_w_valid = 1'h0; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_w_bits_data = 64'h0; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_w_bits_strb = 8'h0; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_w_bits_last = 1'h0; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_b_ready = 1'h0; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_ar_valid = 1'h0; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_ar_bits_id = 1'h0; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_ar_bits_addr = 32'h0; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_ar_bits_region = 4'h0; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_ar_bits_size = 3'h0; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_ar_bits_burst = 2'h0; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_ar_bits_cache = 4'h0; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_r_ready = 1'h0; // @[quasar_wrapper.scala 106:21] - assign io_dma_brg_aw_ready = 1'h0; // @[quasar_wrapper.scala 107:21] - assign io_dma_brg_w_ready = 1'h0; // @[quasar_wrapper.scala 107:21] - assign io_dma_brg_b_valid = 1'h0; // @[quasar_wrapper.scala 107:21] - assign io_dma_brg_b_bits_resp = 2'h0; // @[quasar_wrapper.scala 107:21] - assign io_dma_brg_b_bits_id = 1'h0; // @[quasar_wrapper.scala 107:21] - assign io_dma_brg_ar_ready = 1'h0; // @[quasar_wrapper.scala 107:21] - assign io_dma_brg_r_valid = 1'h0; // @[quasar_wrapper.scala 107:21] - assign io_dma_brg_r_bits_id = 1'h0; // @[quasar_wrapper.scala 107:21] - assign io_dma_brg_r_bits_data = 64'h0; // @[quasar_wrapper.scala 107:21] - assign io_dma_brg_r_bits_resp = 2'h0; // @[quasar_wrapper.scala 107:21] - assign io_dma_brg_r_bits_last = 1'h0; // @[quasar_wrapper.scala 107:21] + assign io_lsu_brg_out_haddr = core_io_lsu_ahb_out_haddr; // @[quasar_wrapper.scala 111:21] + assign io_lsu_brg_out_hburst = 3'h0; // @[quasar_wrapper.scala 111:21] + assign io_lsu_brg_out_hmastlock = 1'h0; // @[quasar_wrapper.scala 111:21] + assign io_lsu_brg_out_hprot = 4'h3; // @[quasar_wrapper.scala 111:21] + assign io_lsu_brg_out_hsize = core_io_lsu_ahb_out_hsize; // @[quasar_wrapper.scala 111:21] + assign io_lsu_brg_out_htrans = core_io_lsu_ahb_out_htrans; // @[quasar_wrapper.scala 111:21] + assign io_lsu_brg_out_hwrite = core_io_lsu_ahb_out_hwrite; // @[quasar_wrapper.scala 111:21] + assign io_lsu_brg_out_hwdata = core_io_lsu_ahb_out_hwdata; // @[quasar_wrapper.scala 111:21] + assign io_ifu_brg_out_haddr = core_io_ifu_ahb_out_haddr; // @[quasar_wrapper.scala 110:21] + assign io_ifu_brg_out_hburst = 3'h0; // @[quasar_wrapper.scala 110:21] + assign io_ifu_brg_out_hmastlock = 1'h0; // @[quasar_wrapper.scala 110:21] + assign io_ifu_brg_out_hprot = 4'h3; // @[quasar_wrapper.scala 110:21] + assign io_ifu_brg_out_hsize = core_io_ifu_ahb_out_hsize; // @[quasar_wrapper.scala 110:21] + assign io_ifu_brg_out_htrans = core_io_ifu_ahb_out_htrans; // @[quasar_wrapper.scala 110:21] + assign io_ifu_brg_out_hwrite = core_io_ifu_ahb_out_hwrite; // @[quasar_wrapper.scala 110:21] + assign io_ifu_brg_out_hwdata = core_io_ifu_ahb_out_hwdata; // @[quasar_wrapper.scala 110:21] + assign io_sb_brg_out_haddr = core_io_sb_ahb_out_haddr; // @[quasar_wrapper.scala 112:20] + assign io_sb_brg_out_hburst = 3'h0; // @[quasar_wrapper.scala 112:20] + assign io_sb_brg_out_hmastlock = 1'h0; // @[quasar_wrapper.scala 112:20] + assign io_sb_brg_out_hprot = 4'h3; // @[quasar_wrapper.scala 112:20] + assign io_sb_brg_out_hsize = core_io_sb_ahb_out_hsize; // @[quasar_wrapper.scala 112:20] + assign io_sb_brg_out_htrans = core_io_sb_ahb_out_htrans; // @[quasar_wrapper.scala 112:20] + assign io_sb_brg_out_hwrite = core_io_sb_ahb_out_hwrite; // @[quasar_wrapper.scala 112:20] + assign io_sb_brg_out_hwdata = core_io_sb_ahb_out_hwdata; // @[quasar_wrapper.scala 112:20] + assign io_dma_brg_sig_in_hrdata = core_io_dma_ahb_sig_in_hrdata; // @[quasar_wrapper.scala 113:21] + assign io_dma_brg_sig_in_hready = core_io_dma_ahb_sig_in_hready; // @[quasar_wrapper.scala 113:21] + assign io_dma_brg_sig_in_hresp = core_io_dma_ahb_sig_in_hresp; // @[quasar_wrapper.scala 113:21] assign io_dec_tlu_perfcnt0 = core_io_dec_tlu_perfcnt0; // @[quasar_wrapper.scala 159:23] assign io_dec_tlu_perfcnt1 = core_io_dec_tlu_perfcnt1; // @[quasar_wrapper.scala 160:23] assign io_dec_tlu_perfcnt2 = core_io_dec_tlu_perfcnt2; // @[quasar_wrapper.scala 161:23] @@ -83460,9 +85854,25 @@ module quasar_wrapper( assign dmi_wrapper_core_rst_n = io_dbg_rst_l; // @[quasar_wrapper.scala 76:29] assign dmi_wrapper_core_clk = clock; // @[quasar_wrapper.scala 71:27] assign dmi_wrapper_jtag_id = io_jtag_id; // @[quasar_wrapper.scala 72:26] - assign dmi_wrapper_rd_data = 32'h0; // @[quasar_wrapper.scala 73:26] + assign dmi_wrapper_rd_data = core_io_dmi_reg_rdata; // @[quasar_wrapper.scala 73:26] assign core_clock = clock; assign core_reset = reset; + assign core_io_lsu_ahb_in_hrdata = io_lsu_brg_in_hrdata; // @[quasar_wrapper.scala 111:21] + assign core_io_lsu_ahb_in_hready = io_lsu_brg_in_hready; // @[quasar_wrapper.scala 111:21] + assign core_io_lsu_ahb_in_hresp = io_lsu_brg_in_hresp; // @[quasar_wrapper.scala 111:21] + assign core_io_ifu_ahb_in_hrdata = io_ifu_brg_in_hrdata; // @[quasar_wrapper.scala 110:21] + assign core_io_ifu_ahb_in_hready = io_ifu_brg_in_hready; // @[quasar_wrapper.scala 110:21] + assign core_io_ifu_ahb_in_hresp = io_ifu_brg_in_hresp; // @[quasar_wrapper.scala 110:21] + assign core_io_sb_ahb_in_hrdata = io_sb_brg_in_hrdata; // @[quasar_wrapper.scala 112:20] + assign core_io_sb_ahb_in_hready = io_sb_brg_in_hready; // @[quasar_wrapper.scala 112:20] + assign core_io_sb_ahb_in_hresp = io_sb_brg_in_hresp; // @[quasar_wrapper.scala 112:20] + assign core_io_dma_ahb_sig_out_haddr = io_dma_brg_sig_out_haddr; // @[quasar_wrapper.scala 113:21] + assign core_io_dma_ahb_sig_out_hsize = io_dma_brg_sig_out_hsize; // @[quasar_wrapper.scala 113:21] + assign core_io_dma_ahb_sig_out_htrans = io_dma_brg_sig_out_htrans; // @[quasar_wrapper.scala 113:21] + assign core_io_dma_ahb_sig_out_hwrite = io_dma_brg_sig_out_hwrite; // @[quasar_wrapper.scala 113:21] + assign core_io_dma_ahb_sig_out_hwdata = io_dma_brg_sig_out_hwdata; // @[quasar_wrapper.scala 113:21] + assign core_io_dma_ahb_hsel = io_dma_brg_hsel; // @[quasar_wrapper.scala 113:21] + assign core_io_dma_ahb_hreadyin = io_dma_brg_hreadyin; // @[quasar_wrapper.scala 113:21] assign core_io_dbg_rst_l = io_dbg_rst_l; // @[quasar_wrapper.scala 93:21 quasar_wrapper.scala 121:21] assign core_io_rst_vec = io_rst_vec; // @[quasar_wrapper.scala 122:19] assign core_io_nmi_int = io_nmi_int; // @[quasar_wrapper.scala 123:19] diff --git a/src/main/scala/lib/ahb_to_axi4.scala b/src/main/scala/lib/ahb_to_axi4.scala index 8d13dcd3..223bf4da 100644 --- a/src/main/scala/lib/ahb_to_axi4.scala +++ b/src/main/scala/lib/ahb_to_axi4.scala @@ -5,13 +5,13 @@ import chisel3.experimental.chiselName import include._ @chiselName -class ahb_to_axi4 extends Module with lib with RequireAsyncReset { +class ahb_to_axi4(TAG : Int) extends Module with lib with RequireAsyncReset { val io = IO(new Bundle { val scan_mode = Input(Bool()) val bus_clk_en = Input(Bool()) val clk_override = Input(Bool()) - val axi = new axi_channels(1) + val axi = new axi_channels(TAG) val ahb = new Bundle{ val sig = Flipped(new ahb_channel()) val hsel = Input(Bool()) @@ -19,7 +19,6 @@ class ahb_to_axi4 extends Module with lib with RequireAsyncReset { }) io.axi <> 0.U.asTypeOf(io.axi) val idle:: wr :: rd :: pend :: Nil = Enum(4) - val TAG= 1 val master_wstrb = WireInit(0.U(8.W)) val buf_state_en = WireInit(false.B) diff --git a/src/main/scala/lib/axi4_to_ahb.scala b/src/main/scala/lib/axi4_to_ahb.scala index 834ccf43..e72bbbbd 100644 --- a/src/main/scala/lib/axi4_to_ahb.scala +++ b/src/main/scala/lib/axi4_to_ahb.scala @@ -4,26 +4,19 @@ import chisel3._ import chisel3.util._ import include._ -trait Config { - val TAG = 1 -} - -class axi4_to_ahb_IO extends Bundle with Config { +class axi4_to_ahb_IO(val TAG : Int) extends Bundle { val scan_mode = Input(Bool()) val bus_clk_en = Input(Bool()) val clk_override = Input(Bool()) // AXI-4 signals - val axi = Flipped(new axi_channels(1)) + val axi = Flipped(new axi_channels(TAG)) // AHB-Lite signals val ahb = new ahb_channel() } - - - -class axi4_to_ahb extends Module with lib with RequireAsyncReset with Config { - val io = IO(new axi4_to_ahb_IO) +class axi4_to_ahb(val TAG : Int = 3) extends Module with lib with RequireAsyncReset { + val io = IO(new axi4_to_ahb_IO(TAG)) val buf_rst = WireInit(0.U(1.W)) buf_rst :=0.U io.ahb.out.htrans := 0.U @@ -341,3 +334,7 @@ class axi4_to_ahb extends Module with lib with RequireAsyncReset with Config { ahbm_addr_clk := rvclkhdr(clock, ahbm_addr_clken, io.scan_mode) ahbm_data_clk := rvclkhdr(clock, ahbm_data_clken, io.scan_mode) } + +object axi4 extends App { + println((new chisel3.stage.ChiselStage).emitVerilog(new axi4_to_ahb(3))) +} diff --git a/src/main/scala/lib/param.scala b/src/main/scala/lib/param.scala index 3ee9d0f3..79c7506c 100644 --- a/src/main/scala/lib/param.scala +++ b/src/main/scala/lib/param.scala @@ -22,7 +22,7 @@ trait param { val BTB_INDEX3_LO = 0x12 val BTB_SIZE = 0x200 val BUILD_AHB_LITE = 0x1 - val BUILD_AXI4 = 0x1 + val BUILD_AXI4 = 0x0 val BUILD_AXI_NATIVE = 0x0 val BUS_PRTY_DEFAULT = 0x3 val DATA_ACCESS_ADDR0 = 0x00000000 diff --git a/src/main/scala/quasar.scala b/src/main/scala/quasar.scala index cc69f776..b2becd82 100644 --- a/src/main/scala/quasar.scala +++ b/src/main/scala/quasar.scala @@ -67,8 +67,10 @@ class quasar_bundle extends Bundle with lib{ val soft_int = Input(Bool()) val scan_mode = Input(Bool()) } + class quasar extends Module with RequireAsyncReset with lib { val io = IO (new quasar_bundle) + val ifu = Module(new ifu) val dec = Module(new dec) val dbg = Module(new dbg) @@ -234,15 +236,16 @@ class quasar extends Module with RequireAsyncReset with lib { io.dec_tlu_perfcnt1 := dec.io.dec_tlu_perfcnt1 io.dec_tlu_perfcnt2 := dec.io.dec_tlu_perfcnt2 io.dec_tlu_perfcnt3 := dec.io.dec_tlu_perfcnt3 + io.dmi_reg_rdata := dbg.io.dmi_reg_rdata + // LSU Outputs io.dccm <> lsu.io.dccm - if(BUILD_AHB_LITE) { - val sb_axi4_to_ahb = Module(new axi4_to_ahb()) - val ifu_axi4_to_ahb = Module(new axi4_to_ahb()) - val lsu_axi4_to_ahb = Module(new axi4_to_ahb()) - val dma_ahb_to_axi4 = Module(new ahb_to_axi4()) + val sb_axi4_to_ahb = Module(new axi4_to_ahb(SB_BUS_TAG)) + val ifu_axi4_to_ahb = Module(new axi4_to_ahb(IFU_BUS_TAG)) + val lsu_axi4_to_ahb = Module(new axi4_to_ahb(LSU_BUS_TAG)) + val dma_ahb_to_axi4 = Module(new ahb_to_axi4(DMA_BUS_TAG)) lsu_axi4_to_ahb.io.scan_mode := io.scan_mode lsu_axi4_to_ahb.io.bus_clk_en := io.lsu_bus_clk_en @@ -250,12 +253,12 @@ class quasar extends Module with RequireAsyncReset with lib { lsu_axi4_to_ahb.io.axi <> lsu.io.axi lsu_axi4_to_ahb.io.ahb <> io.lsu_ahb - ifu_axi4_to_ahb.io.scan_mode := io.scan_mode ifu_axi4_to_ahb.io.bus_clk_en := io.ifu_bus_clk_en ifu_axi4_to_ahb.io.clk_override := dec.io.dec_tlu_bus_clk_override ifu_axi4_to_ahb.io.axi <> ifu.io.ifu ifu_axi4_to_ahb.io.ahb <> io.ifu_ahb + ifu_axi4_to_ahb.io.axi.b.ready := true.B sb_axi4_to_ahb.io.scan_mode := io.scan_mode sb_axi4_to_ahb.io.bus_clk_en := io.dbg_bus_clk_en @@ -284,7 +287,7 @@ class quasar extends Module with RequireAsyncReset with lib { ifu.io.ifu <> io.ifu_axi lsu.io.axi <> io.lsu_axi } - io.dmi_reg_rdata := 0.U + } object QUASAR extends App { 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